From d1ec0f00559b28f933176f41f764a5abb5581543 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 12:43:36 +0000 Subject: [PATCH] argh pinmux generating bi-directional SDR DM when it should be output --- .../non_generated/full_core_4_4ksram_ls180.il | 132771 ++++++++------- experiments9/non_generated/full_core_ls180.il | 132771 ++++++++------- 2 files changed, 136794 insertions(+), 128748 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index 2bb27e0..27d000d 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14913 +autoidx 15098 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -72,7 +72,7 @@ module \ALU_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -81,15 +81,15 @@ module \ALU_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -106,7 +106,7 @@ module \ALU_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -114,7 +114,7 @@ module \ALU_dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131,7 +131,7 @@ module \ALU_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -208,13 +208,13 @@ module \ALU_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -222,21 +222,21 @@ module \ALU_dec19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:194.3-203.6" process $proc$libresoc.v:194$1 @@ -249,7 +249,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -272,7 +272,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -295,7 +295,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -318,7 +318,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -341,7 +341,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -364,7 +364,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -387,7 +387,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -410,7 +410,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -433,7 +433,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -456,7 +456,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -479,7 +479,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -502,7 +502,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -525,7 +525,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -548,7 +548,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -642,7 +642,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -651,15 +651,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -670,7 +670,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -679,15 +679,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -704,7 +704,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -712,7 +712,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -729,7 +729,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -806,13 +806,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -820,17 +820,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -841,7 +841,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -850,15 +850,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -875,7 +875,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -883,7 +883,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -900,7 +900,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -977,13 +977,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -991,17 +991,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub10_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1012,7 +1012,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1021,15 +1021,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1046,7 +1046,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1054,7 +1054,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1071,7 +1071,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1148,13 +1148,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1162,17 +1162,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub22_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1183,7 +1183,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1192,15 +1192,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1217,7 +1217,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1225,7 +1225,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1242,7 +1242,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1319,13 +1319,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1333,17 +1333,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1354,7 +1354,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1363,15 +1363,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1388,7 +1388,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1396,7 +1396,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1413,7 +1413,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1490,13 +1490,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1504,17 +1504,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1531,7 +1531,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1539,7 +1539,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1556,7 +1556,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1633,13 +1633,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1647,23 +1647,23 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_sgn attribute \src "libresoc.v:340.7-340.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:1385.22-1401.4" @@ -1771,7 +1771,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1810,7 +1810,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1849,7 +1849,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1888,7 +1888,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1927,7 +1927,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1966,7 +1966,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2005,7 +2005,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2044,7 +2044,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2083,7 +2083,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2122,7 +2122,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2161,7 +2161,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2200,7 +2200,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2239,7 +2239,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2278,7 +2278,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2394,7 +2394,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -2403,15 +2403,15 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -2428,7 +2428,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -2436,7 +2436,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -2453,7 +2453,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -2530,13 +2530,13 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -2544,21 +2544,21 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub0_sgn attribute \src "libresoc.v:1790.7-1790.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:1790.7-1790.20" process $proc$libresoc.v:1790$45 @@ -2579,7 +2579,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2610,7 +2610,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2641,7 +2641,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2672,7 +2672,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2703,7 +2703,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2734,7 +2734,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2765,7 +2765,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2796,7 +2796,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2827,7 +2827,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2858,7 +2858,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2889,7 +2889,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2920,7 +2920,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2951,7 +2951,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2982,7 +2982,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -3076,7 +3076,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -3085,15 +3085,15 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -3110,7 +3110,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -3118,7 +3118,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -3135,7 +3135,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -3212,13 +3212,13 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -3226,21 +3226,21 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub10_sgn attribute \src "libresoc.v:2208.7-2208.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2208.7-2208.20" process $proc$libresoc.v:2208$60 @@ -3261,7 +3261,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3320,7 +3320,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3379,7 +3379,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3438,7 +3438,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3497,7 +3497,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3556,7 +3556,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3615,7 +3615,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3674,7 +3674,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3733,7 +3733,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3792,7 +3792,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3851,7 +3851,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3910,7 +3910,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3969,7 +3969,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4028,7 +4028,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4150,7 +4150,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -4159,15 +4159,15 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -4184,7 +4184,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -4192,7 +4192,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -4209,7 +4209,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -4286,13 +4286,13 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -4300,21 +4300,21 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub22_sgn attribute \src "libresoc.v:2920.7-2920.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2920.7-2920.20" process $proc$libresoc.v:2920$75 @@ -4335,7 +4335,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4382,7 +4382,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4429,7 +4429,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4476,7 +4476,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4523,7 +4523,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4570,7 +4570,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4617,7 +4617,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4664,7 +4664,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4711,7 +4711,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4758,7 +4758,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4805,7 +4805,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4852,7 +4852,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4899,7 +4899,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4946,7 +4946,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -5056,7 +5056,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5065,15 +5065,15 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -5090,7 +5090,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5098,7 +5098,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5115,7 +5115,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5192,13 +5192,13 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5206,21 +5206,21 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub26_sgn attribute \src "libresoc.v:3506.7-3506.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3506.7-3506.20" process $proc$libresoc.v:3506$90 @@ -5241,7 +5241,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5272,7 +5272,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5303,7 +5303,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5334,7 +5334,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5365,7 +5365,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5396,7 +5396,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5427,7 +5427,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5458,7 +5458,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5489,7 +5489,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5520,7 +5520,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5551,7 +5551,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5582,7 +5582,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5613,7 +5613,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5644,7 +5644,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5738,7 +5738,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5747,15 +5747,15 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -5772,7 +5772,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5780,7 +5780,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5797,7 +5797,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5874,13 +5874,13 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5888,21 +5888,21 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub8_sgn attribute \src "libresoc.v:3924.7-3924.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3924.7-3924.20" process $proc$libresoc.v:3924$105 @@ -5923,7 +5923,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -5990,7 +5990,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6057,7 +6057,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6124,7 +6124,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6191,7 +6191,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6258,7 +6258,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6325,7 +6325,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6392,7 +6392,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6459,7 +6459,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6526,7 +6526,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6593,7 +6593,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6660,7 +6660,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6727,7 +6727,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6794,7 +6794,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6900,7 +6900,7 @@ module \BRANCH_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -6909,7 +6909,7 @@ module \BRANCH_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -6926,7 +6926,7 @@ module \BRANCH_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -6943,7 +6943,7 @@ module \BRANCH_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7020,23 +7020,23 @@ module \BRANCH_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \BRANCH_dec19_rc_sel attribute \src "libresoc.v:4720.7-4720.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:4720.7-4720.20" process $proc$libresoc.v:4720$114 @@ -7057,7 +7057,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7088,7 +7088,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7119,7 +7119,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7150,7 +7150,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7181,7 +7181,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7212,7 +7212,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7243,7 +7243,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7274,7 +7274,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7332,7 +7332,7 @@ module \CR_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7341,7 +7341,7 @@ module \CR_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7358,7 +7358,7 @@ module \CR_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7435,19 +7435,19 @@ module \CR_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec19_rc_sel attribute \src "libresoc.v:5008.7-5008.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:5008.7-5008.20" process $proc$libresoc.v:5008$120 @@ -7468,7 +7468,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7523,7 +7523,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7578,7 +7578,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7633,7 +7633,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7688,7 +7688,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7770,7 +7770,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7779,7 +7779,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7790,7 +7790,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7799,7 +7799,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7816,7 +7816,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7893,15 +7893,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7912,7 +7912,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7921,7 +7921,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7938,7 +7938,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8015,15 +8015,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub15_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8034,7 +8034,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8043,7 +8043,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8060,7 +8060,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8137,15 +8137,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub16_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8156,7 +8156,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8165,7 +8165,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8182,7 +8182,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8259,15 +8259,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8284,7 +8284,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8361,21 +8361,21 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_rc_sel attribute \src "libresoc.v:5314.7-5314.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:5934.21-5941.4" @@ -8436,7 +8436,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8471,7 +8471,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8506,7 +8506,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8541,7 +8541,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8576,7 +8576,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8643,7 +8643,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8652,7 +8652,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8669,7 +8669,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8746,19 +8746,19 @@ module \CR_dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:6072.7-6072.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6072.7-6072.20" process $proc$libresoc.v:6072$132 @@ -8779,7 +8779,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8802,7 +8802,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8825,7 +8825,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8848,7 +8848,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8871,7 +8871,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8921,7 +8921,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8930,7 +8930,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8947,7 +8947,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -9024,19 +9024,19 @@ module \CR_dec31_dec_sub15 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:6258.7-6258.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6258.7-6258.20" process $proc$libresoc.v:6258$138 @@ -9057,7 +9057,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9204,7 +9204,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9351,7 +9351,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9498,7 +9498,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9645,7 +9645,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9819,7 +9819,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9828,7 +9828,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -9845,7 +9845,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -9922,19 +9922,19 @@ module \CR_dec31_dec_sub16 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel attribute \src "libresoc.v:6909.7-6909.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6909.7-6909.20" process $proc$libresoc.v:6909$144 @@ -9955,7 +9955,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9978,7 +9978,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10001,7 +10001,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10024,7 +10024,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10047,7 +10047,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10097,7 +10097,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10106,7 +10106,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10123,7 +10123,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10200,19 +10200,19 @@ module \CR_dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:7095.7-7095.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:7095.7-7095.20" process $proc$libresoc.v:7095$150 @@ -10233,7 +10233,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10256,7 +10256,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10279,7 +10279,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10302,7 +10302,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10325,7 +10325,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10411,7 +10411,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10420,15 +10420,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10439,7 +10439,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10448,15 +10448,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10473,7 +10473,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10481,7 +10481,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10498,7 +10498,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10575,13 +10575,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10589,17 +10589,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10610,7 +10610,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10619,15 +10619,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10644,7 +10644,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10652,7 +10652,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10669,7 +10669,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10746,13 +10746,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10760,17 +10760,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10787,7 +10787,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10795,7 +10795,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10812,7 +10812,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10889,13 +10889,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10903,23 +10903,23 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_sgn attribute \src "libresoc.v:7281.7-7281.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:7813.23-7829.4" @@ -10978,7 +10978,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11005,7 +11005,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11032,7 +11032,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11059,7 +11059,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11086,7 +11086,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11113,7 +11113,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11140,7 +11140,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11167,7 +11167,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11194,7 +11194,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11221,7 +11221,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11248,7 +11248,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11275,7 +11275,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11302,7 +11302,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11329,7 +11329,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11422,7 +11422,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -11431,15 +11431,15 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -11456,7 +11456,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -11464,7 +11464,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -11481,7 +11481,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -11558,13 +11558,13 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -11572,21 +11572,21 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub11_sgn attribute \src "libresoc.v:8038.7-8038.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8038.7-8038.20" process $proc$libresoc.v:8038$180 @@ -11607,7 +11607,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11666,7 +11666,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11725,7 +11725,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11784,7 +11784,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11843,7 +11843,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11902,7 +11902,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11961,7 +11961,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12020,7 +12020,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12079,7 +12079,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12138,7 +12138,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12197,7 +12197,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12256,7 +12256,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12315,7 +12315,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12374,7 +12374,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12496,7 +12496,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -12505,15 +12505,15 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -12530,7 +12530,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -12538,7 +12538,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -12555,7 +12555,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -12632,13 +12632,13 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -12646,21 +12646,21 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub9_sgn attribute \src "libresoc.v:8750.7-8750.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8750.7-8750.20" process $proc$libresoc.v:8750$195 @@ -12681,7 +12681,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12740,7 +12740,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12799,7 +12799,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12858,7 +12858,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12917,7 +12917,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12976,7 +12976,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13035,7 +13035,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13094,7 +13094,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13153,7 +13153,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13212,7 +13212,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13271,7 +13271,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13330,7 +13330,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13389,7 +13389,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13448,7 +13448,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13557,7 +13557,7 @@ module \LDST_dec31 wire $1\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13568,7 +13568,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13577,9 +13577,9 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13590,7 +13590,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13599,7 +13599,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13616,7 +13616,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13624,7 +13624,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13641,7 +13641,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13718,9 +13718,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13728,28 +13728,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13760,7 +13760,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13769,7 +13769,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13786,7 +13786,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13794,7 +13794,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13811,7 +13811,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13888,9 +13888,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13898,28 +13898,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13930,7 +13930,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13939,7 +13939,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13956,7 +13956,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13964,7 +13964,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13981,7 +13981,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14058,9 +14058,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14068,28 +14068,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -14100,7 +14100,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -14109,7 +14109,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -14126,7 +14126,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14134,7 +14134,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14151,7 +14151,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14228,9 +14228,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14238,26 +14238,26 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -14274,7 +14274,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14282,7 +14282,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14299,7 +14299,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14376,9 +14376,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14386,32 +14386,32 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_upd attribute \src "libresoc.v:9462.7-9462.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:10330.24-10345.4" @@ -14496,7 +14496,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14531,7 +14531,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14566,7 +14566,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14601,7 +14601,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14636,7 +14636,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14671,7 +14671,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14706,7 +14706,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14741,7 +14741,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14776,7 +14776,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14811,7 +14811,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14846,7 +14846,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14881,7 +14881,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14916,7 +14916,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -15014,7 +15014,7 @@ module \LDST_dec31_dec_sub20 wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15025,7 +15025,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15034,7 +15034,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -15051,7 +15051,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -15059,7 +15059,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15076,7 +15076,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15153,9 +15153,9 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15163,30 +15163,30 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub20_upd attribute \src "libresoc.v:10652.7-10652.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:10652.7-10652.20" process $proc$libresoc.v:10652$223 @@ -15207,7 +15207,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15250,7 +15250,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15293,7 +15293,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15336,7 +15336,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15379,7 +15379,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15422,7 +15422,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15465,7 +15465,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15508,7 +15508,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15551,7 +15551,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15594,7 +15594,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15637,7 +15637,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15680,7 +15680,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15723,7 +15723,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15816,7 +15816,7 @@ module \LDST_dec31_dec_sub21 wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15827,7 +15827,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15836,7 +15836,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -15853,7 +15853,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -15861,7 +15861,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15878,7 +15878,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15955,9 +15955,9 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15965,30 +15965,30 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub21_upd attribute \src "libresoc.v:11169.7-11169.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11169.7-11169.20" process $proc$libresoc.v:11169$237 @@ -16009,7 +16009,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16084,7 +16084,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16159,7 +16159,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16234,7 +16234,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16309,7 +16309,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16384,7 +16384,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16459,7 +16459,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16534,7 +16534,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16609,7 +16609,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16684,7 +16684,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16759,7 +16759,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16834,7 +16834,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16909,7 +16909,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -17034,7 +17034,7 @@ module \LDST_dec31_dec_sub22 wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17045,7 +17045,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17054,7 +17054,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -17071,7 +17071,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -17079,7 +17079,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -17096,7 +17096,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -17173,9 +17173,9 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17183,30 +17183,30 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub22_upd attribute \src "libresoc.v:11998.7-11998.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11998.7-11998.20" process $proc$libresoc.v:11998$251 @@ -17227,7 +17227,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17278,7 +17278,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17329,7 +17329,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17380,7 +17380,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17431,7 +17431,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17482,7 +17482,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17533,7 +17533,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17584,7 +17584,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17635,7 +17635,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17686,7 +17686,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17737,7 +17737,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17788,7 +17788,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17839,7 +17839,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17940,7 +17940,7 @@ module \LDST_dec31_dec_sub23 wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17951,7 +17951,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17960,7 +17960,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -17977,7 +17977,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -17985,7 +17985,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -18002,7 +18002,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -18079,9 +18079,9 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -18089,30 +18089,30 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub23_upd attribute \src "libresoc.v:12593.7-12593.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:12593.7-12593.20" process $proc$libresoc.v:12593$265 @@ -18133,7 +18133,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18208,7 +18208,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18283,7 +18283,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18358,7 +18358,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18433,7 +18433,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18508,7 +18508,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18583,7 +18583,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18658,7 +18658,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18733,7 +18733,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18808,7 +18808,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18883,7 +18883,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18958,7 +18958,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -19033,7 +19033,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -19158,7 +19158,7 @@ module \LDST_dec58 wire $1\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $1\LDST_dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19169,7 +19169,7 @@ module \LDST_dec58 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19178,7 +19178,7 @@ module \LDST_dec58 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -19195,7 +19195,7 @@ module \LDST_dec58 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19203,7 +19203,7 @@ module \LDST_dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19220,7 +19220,7 @@ module \LDST_dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19297,9 +19297,9 @@ module \LDST_dec58 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19307,30 +19307,30 @@ module \LDST_dec58 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec58_upd attribute \src "libresoc.v:13422.7-13422.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13422.7-13422.20" process $proc$libresoc.v:13422$279 @@ -19351,7 +19351,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19382,7 +19382,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19413,7 +19413,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19444,7 +19444,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19475,7 +19475,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19506,7 +19506,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19537,7 +19537,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19568,7 +19568,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19599,7 +19599,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19630,7 +19630,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19661,7 +19661,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19692,7 +19692,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19723,7 +19723,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19804,7 +19804,7 @@ module \LDST_dec62 wire $1\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19815,7 +19815,7 @@ module \LDST_dec62 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19824,7 +19824,7 @@ module \LDST_dec62 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -19841,7 +19841,7 @@ module \LDST_dec62 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19849,7 +19849,7 @@ module \LDST_dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19866,7 +19866,7 @@ module \LDST_dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19943,9 +19943,9 @@ module \LDST_dec62 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19953,30 +19953,30 @@ module \LDST_dec62 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec62_upd attribute \src "libresoc.v:13822.7-13822.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13822.7-13822.20" process $proc$libresoc.v:13822$293 @@ -19997,7 +19997,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20024,7 +20024,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20051,7 +20051,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20078,7 +20078,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20105,7 +20105,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20132,7 +20132,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20159,7 +20159,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20186,7 +20186,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20213,7 +20213,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20240,7 +20240,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20267,7 +20267,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20294,7 +20294,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20321,7 +20321,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20411,7 +20411,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20420,15 +20420,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20439,7 +20439,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20448,15 +20448,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20473,7 +20473,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20481,7 +20481,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20498,7 +20498,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20575,13 +20575,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20589,17 +20589,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20610,7 +20610,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20619,15 +20619,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20644,7 +20644,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20652,7 +20652,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20669,7 +20669,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20746,13 +20746,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20760,17 +20760,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20787,7 +20787,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20795,7 +20795,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20812,7 +20812,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20889,13 +20889,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20903,23 +20903,23 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_sgn attribute \src "libresoc.v:14183.7-14183.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:14715.27-14731.4" @@ -20978,7 +20978,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21005,7 +21005,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21032,7 +21032,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21059,7 +21059,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21086,7 +21086,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21113,7 +21113,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21140,7 +21140,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21167,7 +21167,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21194,7 +21194,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21221,7 +21221,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21248,7 +21248,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21275,7 +21275,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21302,7 +21302,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21329,7 +21329,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21422,7 +21422,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -21431,15 +21431,15 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -21456,7 +21456,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -21464,7 +21464,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -21481,7 +21481,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -21558,13 +21558,13 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -21572,21 +21572,21 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub26_sgn attribute \src "libresoc.v:14940.7-14940.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:14940.7-14940.20" process $proc$libresoc.v:14940$323 @@ -21607,7 +21607,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21662,7 +21662,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21717,7 +21717,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21772,7 +21772,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21827,7 +21827,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21882,7 +21882,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21937,7 +21937,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21992,7 +21992,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22047,7 +22047,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22102,7 +22102,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22157,7 +22157,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22212,7 +22212,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22267,7 +22267,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22322,7 +22322,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22440,7 +22440,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -22449,15 +22449,15 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -22474,7 +22474,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -22482,7 +22482,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -22499,7 +22499,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -22576,13 +22576,13 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -22590,21 +22590,21 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub28_sgn attribute \src "libresoc.v:15610.7-15610.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:15610.7-15610.20" process $proc$libresoc.v:15610$338 @@ -22625,7 +22625,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22684,7 +22684,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22743,7 +22743,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22802,7 +22802,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22861,7 +22861,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22920,7 +22920,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22979,7 +22979,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23038,7 +23038,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23097,7 +23097,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23156,7 +23156,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23215,7 +23215,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23274,7 +23274,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23333,7 +23333,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23392,7 +23392,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23490,7 +23490,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23499,7 +23499,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23510,7 +23510,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23519,7 +23519,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23536,7 +23536,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23553,7 +23553,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23630,19 +23630,19 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23653,7 +23653,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23662,7 +23662,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23679,7 +23679,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23696,7 +23696,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23773,19 +23773,19 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23802,7 +23802,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23819,7 +23819,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23896,25 +23896,25 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_sgn attribute \src "libresoc.v:16322.7-16322.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:16764.23-16774.4" @@ -23961,7 +23961,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23988,7 +23988,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24015,7 +24015,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24042,7 +24042,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24069,7 +24069,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24096,7 +24096,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24123,7 +24123,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24150,7 +24150,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24219,7 +24219,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24228,7 +24228,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -24245,7 +24245,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24262,7 +24262,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24339,23 +24339,23 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub11_sgn attribute \src "libresoc.v:16899.7-16899.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:16899.7-16899.20" process $proc$libresoc.v:16899$356 @@ -24376,7 +24376,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24419,7 +24419,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24462,7 +24462,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24505,7 +24505,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24548,7 +24548,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24591,7 +24591,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24634,7 +24634,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24677,7 +24677,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24759,7 +24759,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24768,7 +24768,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -24785,7 +24785,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24802,7 +24802,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24879,23 +24879,23 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub9_sgn attribute \src "libresoc.v:17259.7-17259.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:17259.7-17259.20" process $proc$libresoc.v:17259$365 @@ -24916,7 +24916,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24959,7 +24959,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25002,7 +25002,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25045,7 +25045,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25088,7 +25088,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25131,7 +25131,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25174,7 +25174,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25217,7 +25217,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25311,7 +25311,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25320,15 +25320,15 @@ module \SHIFT_ROT_dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -25345,7 +25345,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -25362,7 +25362,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -25439,25 +25439,25 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec30_sgn attribute \src "libresoc.v:17619.7-17619.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch attribute \src "libresoc.v:17619.7-17619.20" process $proc$libresoc.v:17619$377 @@ -25478,7 +25478,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25537,7 +25537,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25596,7 +25596,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25655,7 +25655,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25714,7 +25714,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25773,7 +25773,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25832,7 +25832,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25891,7 +25891,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25950,7 +25950,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26009,7 +26009,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26068,7 +26068,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26178,7 +26178,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26187,15 +26187,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26206,7 +26206,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26215,15 +26215,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26240,7 +26240,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26257,7 +26257,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26334,21 +26334,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26359,7 +26359,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26368,15 +26368,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26393,7 +26393,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26410,7 +26410,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26487,21 +26487,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26512,7 +26512,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26521,15 +26521,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26546,7 +26546,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26563,7 +26563,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26640,21 +26640,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26671,7 +26671,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26688,7 +26688,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26765,27 +26765,27 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_sgn attribute \src "libresoc.v:18199.7-18199.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:18827.29-18840.4" @@ -26854,7 +26854,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26885,7 +26885,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26916,7 +26916,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26947,7 +26947,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26978,7 +26978,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27009,7 +27009,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27040,7 +27040,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27071,7 +27071,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27102,7 +27102,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27133,7 +27133,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27164,7 +27164,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27250,7 +27250,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27259,15 +27259,15 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -27284,7 +27284,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27301,7 +27301,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27378,25 +27378,25 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn attribute \src "libresoc.v:19055.7-19055.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19055.7-19055.20" process $proc$libresoc.v:19055$401 @@ -27417,7 +27417,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27452,7 +27452,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27487,7 +27487,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27522,7 +27522,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27557,7 +27557,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27592,7 +27592,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27627,7 +27627,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27662,7 +27662,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27697,7 +27697,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27732,7 +27732,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27767,7 +27767,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27853,7 +27853,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27862,15 +27862,15 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -27887,7 +27887,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27904,7 +27904,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27981,25 +27981,25 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn attribute \src "libresoc.v:19437.7-19437.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19437.7-19437.20" process $proc$libresoc.v:19437$413 @@ -28020,7 +28020,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28051,7 +28051,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28082,7 +28082,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28113,7 +28113,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28144,7 +28144,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28175,7 +28175,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28206,7 +28206,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28237,7 +28237,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28268,7 +28268,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28299,7 +28299,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28330,7 +28330,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28412,7 +28412,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28421,15 +28421,15 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -28446,7 +28446,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -28463,7 +28463,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28540,25 +28540,25 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn attribute \src "libresoc.v:19786.7-19786.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19786.7-19786.20" process $proc$libresoc.v:19786$425 @@ -28579,7 +28579,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28614,7 +28614,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28649,7 +28649,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28684,7 +28684,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28719,7 +28719,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28754,7 +28754,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28789,7 +28789,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28824,7 +28824,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28859,7 +28859,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28894,7 +28894,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28929,7 +28929,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -29010,7 +29010,7 @@ module \SPR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29019,7 +29019,7 @@ module \SPR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -29030,7 +29030,7 @@ module \SPR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29039,7 +29039,7 @@ module \SPR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29056,7 +29056,7 @@ module \SPR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29133,17 +29133,17 @@ module \SPR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29160,7 +29160,7 @@ module \SPR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29237,23 +29237,23 @@ module \SPR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_rc_sel attribute \src "libresoc.v:20168.7-20168.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:20427.23-20435.4" @@ -29285,7 +29285,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29308,7 +29308,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29331,7 +29331,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29354,7 +29354,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29377,7 +29377,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29400,7 +29400,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29456,7 +29456,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29465,7 +29465,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29482,7 +29482,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29559,21 +29559,21 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:20504.7-20504.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:20504.7-20504.20" process $proc$libresoc.v:20504$439 @@ -29594,7 +29594,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29621,7 +29621,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29648,7 +29648,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29675,7 +29675,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29702,7 +29702,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29729,7 +29729,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -30873,9 +30873,9 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:21161.7-21161.15" wire \initial @@ -31077,9 +31077,9 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:21223.7-21223.15" wire \initial @@ -32173,9 +32173,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -35288,9 +35288,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a @@ -36331,9 +36331,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36677,9 +36677,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -37203,9 +37203,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -38725,9 +38725,9 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26241.7-26241.15" wire \initial @@ -38929,9 +38929,9 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26303.7-26303.15" wire \initial @@ -39133,9 +39133,9 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26365.7-26365.15" wire \initial @@ -39337,9 +39337,9 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26427.7-26427.15" wire \initial @@ -39541,9 +39541,9 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26489.7-26489.15" wire \initial @@ -39745,9 +39745,9 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26551.7-26551.15" wire \initial @@ -39949,9 +39949,9 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26613.7-26613.15" wire \initial @@ -40153,9 +40153,9 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26675.7-26675.15" wire \initial @@ -40357,9 +40357,9 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26737.7-26737.15" wire \initial @@ -40561,9 +40561,9 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26799.7-26799.15" wire \initial @@ -40723,9 +40723,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -41749,9 +41749,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a @@ -42981,9 +42981,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -44027,9 +44027,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -44596,9 +44596,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -45524,9 +45524,9 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31575.7-31575.15" wire \initial @@ -45728,9 +45728,9 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31637.7-31637.15" wire \initial @@ -45932,9 +45932,9 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31699.7-31699.15" wire \initial @@ -46136,9 +46136,9 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31761.7-31761.15" wire \initial @@ -46340,9 +46340,9 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31823.7-31823.15" wire \initial @@ -46544,9 +46544,9 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31885.7-31885.15" wire \initial @@ -46748,9 +46748,9 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31947.7-31947.15" wire \initial @@ -46952,9 +46952,9 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:32009.7-32009.15" wire \initial @@ -47156,9 +47156,9 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:32071.7-32071.15" wire \initial @@ -50601,9 +50601,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -52840,9 +52840,9 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:34540.7-34540.15" wire \initial @@ -62431,9 +62431,9 @@ module \core wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 97 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter @@ -62623,11 +62623,11 @@ module \core wire \dec_ALU_ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_ALU_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_ALU_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia @@ -62735,9 +62735,9 @@ module \core wire \dec_BRANCH_BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -62835,9 +62835,9 @@ module \core attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_CR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_CR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_DIV_DIV__data_len @@ -62969,11 +62969,11 @@ module \core wire \dec_DIV_DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_DIV_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_DIV_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse @@ -63102,11 +63102,11 @@ module \core wire \dec_LDST_LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LDST_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LDST_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len @@ -63238,11 +63238,11 @@ module \core wire \dec_LOGICAL_LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LOGICAL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LOGICAL_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63358,9 +63358,9 @@ module \core wire \dec_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_MUL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63490,9 +63490,9 @@ module \core wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63592,9 +63592,9 @@ module \core wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SPR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 74 \dmi__addr @@ -65721,15 +65721,15 @@ module \core wire width 3 input 9 \sv__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" wire input 68 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 87 \wb_dcache_en @@ -85800,97 +85800,125 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:49145.1-49778.10" +attribute \src "libresoc.v:49145.1-49881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr + attribute \src "libresoc.v:49840.3-49849.6" + wire width 4 $0\cr_pred__data_o[3:0] attribute \src "libresoc.v:49146.7-49146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49692.3-49700.6" - wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:49528.3-49529.43" - wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:49474.13-49474.35" - wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49711.3-49719.6" - wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:49526.3-49527.43" - wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:49478.13-49478.35" - wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49730.3-49738.6" - wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:49530.3-49531.35" + attribute \src "libresoc.v:49774.3-49782.6" + wire width 8 $0\ren_delay$17$next[7:0]$3056 + attribute \src "libresoc.v:49594.3-49595.43" + wire width 8 $0\ren_delay$17[7:0]$3053 + attribute \src "libresoc.v:49526.13-49526.35" + wire width 8 $0\ren_delay$17[7:0]$3074 + attribute \src "libresoc.v:49793.3-49801.6" + wire width 8 $0\ren_delay$34$next[7:0]$3060 + attribute \src "libresoc.v:49592.3-49593.43" + wire width 8 $0\ren_delay$34[7:0]$3051 + attribute \src "libresoc.v:49530.13-49530.35" + wire width 8 $0\ren_delay$34[7:0]$3076 + attribute \src "libresoc.v:49812.3-49820.6" + wire width 8 $0\ren_delay$51$next[7:0]$3064 + attribute \src "libresoc.v:49590.3-49591.43" + wire width 8 $0\ren_delay$51[7:0]$3049 + attribute \src "libresoc.v:49534.13-49534.35" + wire width 8 $0\ren_delay$51[7:0]$3078 + attribute \src "libresoc.v:49831.3-49839.6" + wire width 8 $0\ren_delay$next[7:0]$3068 + attribute \src "libresoc.v:49596.3-49597.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49739.3-49748.6" + attribute \src "libresoc.v:49783.3-49792.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49701.3-49710.6" + attribute \src "libresoc.v:49802.3-49811.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49720.3-49729.6" + attribute \src "libresoc.v:49821.3-49830.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49692.3-49700.6" - wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49711.3-49719.6" - wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49730.3-49738.6" - wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49472.13-49472.30" + attribute \src "libresoc.v:49840.3-49849.6" + wire width 4 $1\cr_pred__data_o[3:0] + attribute \src "libresoc.v:49774.3-49782.6" + wire width 8 $1\ren_delay$17$next[7:0]$3057 + attribute \src "libresoc.v:49793.3-49801.6" + wire width 8 $1\ren_delay$34$next[7:0]$3061 + attribute \src "libresoc.v:49812.3-49820.6" + wire width 8 $1\ren_delay$51$next[7:0]$3065 + attribute \src "libresoc.v:49831.3-49839.6" + wire width 8 $1\ren_delay$next[7:0]$3069 + attribute \src "libresoc.v:49524.13-49524.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49739.3-49748.6" + attribute \src "libresoc.v:49783.3-49792.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49701.3-49710.6" + attribute \src "libresoc.v:49802.3-49811.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49720.3-49729.6" + attribute \src "libresoc.v:49821.3-49830.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49502.17-49502.125" - wire width 4 $or$libresoc.v:49502$3016_Y - attribute \src "libresoc.v:49503.18-49503.126" - wire width 4 $or$libresoc.v:49503$3017_Y - attribute \src "libresoc.v:49504.18-49504.96" - wire width 4 $or$libresoc.v:49504$3018_Y - attribute \src "libresoc.v:49505.18-49505.96" - wire width 4 $or$libresoc.v:49505$3019_Y - attribute \src "libresoc.v:49508.18-49508.126" - wire width 4 $or$libresoc.v:49508$3022_Y - attribute \src "libresoc.v:49509.18-49509.126" - wire width 4 $or$libresoc.v:49509$3023_Y - attribute \src "libresoc.v:49510.18-49510.97" - wire width 4 $or$libresoc.v:49510$3024_Y - attribute \src "libresoc.v:49511.18-49511.126" - wire width 4 $or$libresoc.v:49511$3025_Y - attribute \src "libresoc.v:49512.18-49512.126" - wire width 4 $or$libresoc.v:49512$3026_Y - attribute \src "libresoc.v:49513.18-49513.97" - wire width 4 $or$libresoc.v:49513$3027_Y - attribute \src "libresoc.v:49514.18-49514.97" - wire width 4 $or$libresoc.v:49514$3028_Y - attribute \src "libresoc.v:49516.18-49516.126" - wire width 4 $or$libresoc.v:49516$3030_Y - attribute \src "libresoc.v:49517.17-49517.125" - wire width 4 $or$libresoc.v:49517$3031_Y - attribute \src "libresoc.v:49518.18-49518.126" - wire width 4 $or$libresoc.v:49518$3032_Y - attribute \src "libresoc.v:49519.18-49519.97" - wire width 4 $or$libresoc.v:49519$3033_Y - attribute \src "libresoc.v:49520.18-49520.126" - wire width 4 $or$libresoc.v:49520$3034_Y - attribute \src "libresoc.v:49521.18-49521.126" - wire width 4 $or$libresoc.v:49521$3035_Y - attribute \src "libresoc.v:49522.18-49522.97" - wire width 4 $or$libresoc.v:49522$3036_Y - attribute \src "libresoc.v:49523.18-49523.97" - wire width 4 $or$libresoc.v:49523$3037_Y - attribute \src "libresoc.v:49524.17-49524.125" - wire width 4 $or$libresoc.v:49524$3038_Y - attribute \src "libresoc.v:49525.17-49525.94" - wire width 4 $or$libresoc.v:49525$3039_Y - attribute \src "libresoc.v:49506.18-49506.100" - wire $reduce_or$libresoc.v:49506$3020_Y - attribute \src "libresoc.v:49507.17-49507.95" - wire $reduce_or$libresoc.v:49507$3021_Y - attribute \src "libresoc.v:49515.18-49515.100" - wire $reduce_or$libresoc.v:49515$3029_Y + attribute \src "libresoc.v:49558.17-49558.131" + wire width 4 $or$libresoc.v:49558$3016_Y + attribute \src "libresoc.v:49559.18-49559.132" + wire width 4 $or$libresoc.v:49559$3017_Y + attribute \src "libresoc.v:49560.18-49560.96" + wire width 4 $or$libresoc.v:49560$3018_Y + attribute \src "libresoc.v:49561.18-49561.96" + wire width 4 $or$libresoc.v:49561$3019_Y + attribute \src "libresoc.v:49564.18-49564.126" + wire width 4 $or$libresoc.v:49564$3022_Y + attribute \src "libresoc.v:49565.18-49565.126" + wire width 4 $or$libresoc.v:49565$3023_Y + attribute \src "libresoc.v:49566.18-49566.97" + wire width 4 $or$libresoc.v:49566$3024_Y + attribute \src "libresoc.v:49567.18-49567.126" + wire width 4 $or$libresoc.v:49567$3025_Y + attribute \src "libresoc.v:49568.18-49568.126" + wire width 4 $or$libresoc.v:49568$3026_Y + attribute \src "libresoc.v:49569.18-49569.97" + wire width 4 $or$libresoc.v:49569$3027_Y + attribute \src "libresoc.v:49570.18-49570.97" + wire width 4 $or$libresoc.v:49570$3028_Y + attribute \src "libresoc.v:49572.18-49572.126" + wire width 4 $or$libresoc.v:49572$3030_Y + attribute \src "libresoc.v:49573.17-49573.131" + wire width 4 $or$libresoc.v:49573$3031_Y + attribute \src "libresoc.v:49574.18-49574.126" + wire width 4 $or$libresoc.v:49574$3032_Y + attribute \src "libresoc.v:49575.18-49575.97" + wire width 4 $or$libresoc.v:49575$3033_Y + attribute \src "libresoc.v:49576.18-49576.126" + wire width 4 $or$libresoc.v:49576$3034_Y + attribute \src "libresoc.v:49577.18-49577.126" + wire width 4 $or$libresoc.v:49577$3035_Y + attribute \src "libresoc.v:49578.18-49578.97" + wire width 4 $or$libresoc.v:49578$3036_Y + attribute \src "libresoc.v:49579.18-49579.97" + wire width 4 $or$libresoc.v:49579$3037_Y + attribute \src "libresoc.v:49581.18-49581.126" + wire width 4 $or$libresoc.v:49581$3039_Y + attribute \src "libresoc.v:49582.18-49582.126" + wire width 4 $or$libresoc.v:49582$3040_Y + attribute \src "libresoc.v:49583.18-49583.97" + wire width 4 $or$libresoc.v:49583$3041_Y + attribute \src "libresoc.v:49584.17-49584.131" + wire width 4 $or$libresoc.v:49584$3042_Y + attribute \src "libresoc.v:49585.18-49585.126" + wire width 4 $or$libresoc.v:49585$3043_Y + attribute \src "libresoc.v:49586.18-49586.126" + wire width 4 $or$libresoc.v:49586$3044_Y + attribute \src "libresoc.v:49587.18-49587.97" + wire width 4 $or$libresoc.v:49587$3045_Y + attribute \src "libresoc.v:49588.18-49588.97" + wire width 4 $or$libresoc.v:49588$3046_Y + attribute \src "libresoc.v:49589.17-49589.94" + wire width 4 $or$libresoc.v:49589$3047_Y + attribute \src "libresoc.v:49562.18-49562.100" + wire $reduce_or$libresoc.v:49562$3020_Y + attribute \src "libresoc.v:49563.17-49563.95" + wire $reduce_or$libresoc.v:49563$3021_Y + attribute \src "libresoc.v:49571.18-49571.100" + wire $reduce_or$libresoc.v:49571$3029_Y + attribute \src "libresoc.v:49580.18-49580.100" + wire $reduce_or$libresoc.v:49580$3038_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85935,18 +85963,38 @@ module \cr wire width 4 \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_pred__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \data_i$52 + wire width 4 \data_i$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 3 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -85962,6 +86010,10 @@ module \cr attribute \src "libresoc.v:49146.7-49146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_0_cr_pred0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_cr_pred0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen @@ -85994,6 +86046,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_1_cr_pred1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_cr_pred1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen @@ -86026,6 +86082,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_2_cr_pred2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_cr_pred2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen @@ -86058,6 +86118,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_3_cr_pred3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_3_cr_pred3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest13__wen @@ -86090,6 +86154,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_w3__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_4_cr_pred4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_4_cr_pred4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest14__wen @@ -86122,6 +86190,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_w4__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_cr_pred5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_cr_pred5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest15__wen @@ -86154,6 +86226,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_w5__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_cr_pred6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_cr_pred6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest16__wen @@ -86186,6 +86262,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_w6__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_cr_pred7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_cr_pred7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest17__wen @@ -86228,6 +86308,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 6 \src1__data_o @@ -86244,31 +86328,31 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 15 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 8 \wen$51 + wire width 8 \wen$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49502$3016 + cell $or $or$libresoc.v:49558$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49502$3016_Y + connect \A \reg_4_cr_pred4__data_o + connect \B \reg_5_cr_pred5__data_o + connect \Y $or$libresoc.v:49558$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49503$3017 + cell $or $or$libresoc.v:49559$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49503$3017_Y + connect \A \reg_6_cr_pred6__data_o + connect \B \reg_7_cr_pred7__data_o + connect \Y $or$libresoc.v:49559$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49504$3018 + cell $or $or$libresoc.v:49560$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86276,10 +86360,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49504$3018_Y + connect \Y $or$libresoc.v:49560$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49505$3019 + cell $or $or$libresoc.v:49561$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86287,32 +86371,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49505$3019_Y + connect \Y $or$libresoc.v:49561$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49508$3022 + cell $or $or$libresoc.v:49564$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49508$3022_Y + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$libresoc.v:49564$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49509$3023 + cell $or $or$libresoc.v:49565$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49509$3023_Y + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:49565$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49510$3024 + cell $or $or$libresoc.v:49566$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86320,32 +86404,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49510$3024_Y + connect \Y $or$libresoc.v:49566$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49511$3025 + cell $or $or$libresoc.v:49567$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49511$3025_Y + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$libresoc.v:49567$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49512$3026 + cell $or $or$libresoc.v:49568$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49512$3026_Y + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$libresoc.v:49568$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49513$3027 + cell $or $or$libresoc.v:49569$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86353,10 +86437,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49513$3027_Y + connect \Y $or$libresoc.v:49569$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49514$3028 + cell $or $or$libresoc.v:49570$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86364,43 +86448,43 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49514$3028_Y + connect \Y $or$libresoc.v:49570$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49516$3030 + cell $or $or$libresoc.v:49572$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49516$3030_Y + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$libresoc.v:49572$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49517$3031 + cell $or $or$libresoc.v:49573$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49517$3031_Y + connect \A \reg_0_cr_pred0__data_o + connect \B \reg_1_cr_pred1__data_o + connect \Y $or$libresoc.v:49573$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49518$3032 + cell $or $or$libresoc.v:49574$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49518$3032_Y + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$libresoc.v:49574$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49519$3033 + cell $or $or$libresoc.v:49575$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86408,32 +86492,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49519$3033_Y + connect \Y $or$libresoc.v:49575$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49520$3034 + cell $or $or$libresoc.v:49576$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49520$3034_Y + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$libresoc.v:49576$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49521$3035 + cell $or $or$libresoc.v:49577$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49521$3035_Y + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$libresoc.v:49577$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49522$3036 + cell $or $or$libresoc.v:49578$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86441,10 +86525,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49522$3036_Y + connect \Y $or$libresoc.v:49578$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49523$3037 + cell $or $or$libresoc.v:49579$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86452,21 +86536,98 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49523$3037_Y + connect \Y $or$libresoc.v:49579$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49524$3038 + cell $or $or$libresoc.v:49581$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49524$3038_Y + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$libresoc.v:49581$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49582$3040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:49582$3040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49583$3041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$54 + connect \B \$56 + connect \Y $or$libresoc.v:49583$3041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49584$3042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_cr_pred2__data_o + connect \B \reg_3_cr_pred3__data_o + connect \Y $or$libresoc.v:49584$3042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49585$3043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:49585$3043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49586$3044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:49586$3044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49587$3045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$60 + connect \B \$62 + connect \Y $or$libresoc.v:49587$3045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49588$3046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$58 + connect \B \$64 + connect \Y $or$libresoc.v:49588$3046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49525$3039 + cell $or $or$libresoc.v:49589$3047 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86474,37 +86635,47 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49525$3039_Y + connect \Y $or$libresoc.v:49589$3047_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49506$3020 + cell $reduce_or $reduce_or$libresoc.v:49562$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49506$3020_Y + connect \Y $reduce_or$libresoc.v:49562$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49507$3021 + cell $reduce_or $reduce_or$libresoc.v:49563$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49507$3021_Y + connect \Y $reduce_or$libresoc.v:49563$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49515$3029 + cell $reduce_or $reduce_or$libresoc.v:49571$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49515$3029_Y + connect \Y $reduce_or$libresoc.v:49571$3029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49580$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$51 + connect \Y $reduce_or$libresoc.v:49580$3038_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49532.9-49551.4" + attribute \src "libresoc.v:49598.9-49619.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred0__data_o \reg_0_cr_pred0__data_o + connect \cr_pred0__ren \reg_0_cr_pred0__ren connect \dest10__data_i \reg_0_dest10__data_i connect \dest10__wen \reg_0_dest10__wen connect \dest20__data_i \reg_0_dest20__data_i @@ -86523,10 +86694,12 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49552.9-49571.4" + attribute \src "libresoc.v:49620.9-49641.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred1__data_o \reg_1_cr_pred1__data_o + connect \cr_pred1__ren \reg_1_cr_pred1__ren connect \dest11__data_i \reg_1_dest11__data_i connect \dest11__wen \reg_1_dest11__wen connect \dest21__data_i \reg_1_dest21__data_i @@ -86545,10 +86718,12 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49572.9-49591.4" + attribute \src "libresoc.v:49642.9-49663.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred2__data_o \reg_2_cr_pred2__data_o + connect \cr_pred2__ren \reg_2_cr_pred2__ren connect \dest12__data_i \reg_2_dest12__data_i connect \dest12__wen \reg_2_dest12__wen connect \dest22__data_i \reg_2_dest22__data_i @@ -86567,10 +86742,12 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49592.9-49611.4" + attribute \src "libresoc.v:49664.9-49685.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred3__data_o \reg_3_cr_pred3__data_o + connect \cr_pred3__ren \reg_3_cr_pred3__ren connect \dest13__data_i \reg_3_dest13__data_i connect \dest13__wen \reg_3_dest13__wen connect \dest23__data_i \reg_3_dest23__data_i @@ -86589,10 +86766,12 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49612.9-49631.4" + attribute \src "libresoc.v:49686.9-49707.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred4__data_o \reg_4_cr_pred4__data_o + connect \cr_pred4__ren \reg_4_cr_pred4__ren connect \dest14__data_i \reg_4_dest14__data_i connect \dest14__wen \reg_4_dest14__wen connect \dest24__data_i \reg_4_dest24__data_i @@ -86611,10 +86790,12 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49632.9-49651.4" + attribute \src "libresoc.v:49708.9-49729.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred5__data_o \reg_5_cr_pred5__data_o + connect \cr_pred5__ren \reg_5_cr_pred5__ren connect \dest15__data_i \reg_5_dest15__data_i connect \dest15__wen \reg_5_dest15__wen connect \dest25__data_i \reg_5_dest25__data_i @@ -86633,10 +86814,12 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49652.9-49671.4" + attribute \src "libresoc.v:49730.9-49751.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred6__data_o \reg_6_cr_pred6__data_o + connect \cr_pred6__ren \reg_6_cr_pred6__ren connect \dest16__data_i \reg_6_dest16__data_i connect \dest16__wen \reg_6_dest16__wen connect \dest26__data_i \reg_6_dest26__data_i @@ -86655,10 +86838,12 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49672.9-49691.4" + attribute \src "libresoc.v:49752.9-49773.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred7__data_o \reg_7_cr_pred7__data_o + connect \cr_pred7__ren \reg_7_cr_pred7__ren connect \dest17__data_i \reg_7_dest17__data_i connect \dest17__wen \reg_7_dest17__wen connect \dest27__data_i \reg_7_dest27__data_i @@ -86677,66 +86862,81 @@ module \cr connect \w7__wen \reg_7_w7__wen end attribute \src "libresoc.v:49146.7-49146.20" - process $proc$libresoc.v:49146$3057 + process $proc$libresoc.v:49146$3071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49472.13-49472.30" - process $proc$libresoc.v:49472$3058 + attribute \src "libresoc.v:49524.13-49524.30" + process $proc$libresoc.v:49524$3072 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49474.13-49474.35" - process $proc$libresoc.v:49474$3059 + attribute \src "libresoc.v:49526.13-49526.35" + process $proc$libresoc.v:49526$3073 assign { } { } - assign $0\ren_delay$17[7:0]$3060 8'00000000 + assign $0\ren_delay$17[7:0]$3074 8'00000000 sync always sync init - update \ren_delay$17 $0\ren_delay$17[7:0]$3060 + update \ren_delay$17 $0\ren_delay$17[7:0]$3074 end - attribute \src "libresoc.v:49478.13-49478.35" - process $proc$libresoc.v:49478$3061 + attribute \src "libresoc.v:49530.13-49530.35" + process $proc$libresoc.v:49530$3075 assign { } { } - assign $0\ren_delay$34[7:0]$3062 8'00000000 + assign $0\ren_delay$34[7:0]$3076 8'00000000 sync always sync init - update \ren_delay$34 $0\ren_delay$34[7:0]$3062 + update \ren_delay$34 $0\ren_delay$34[7:0]$3076 end - attribute \src "libresoc.v:49526.3-49527.43" - process $proc$libresoc.v:49526$3040 + attribute \src "libresoc.v:49534.13-49534.35" + process $proc$libresoc.v:49534$3077 assign { } { } - assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next + assign $0\ren_delay$51[7:0]$3078 8'00000000 + sync always + sync init + update \ren_delay$51 $0\ren_delay$51[7:0]$3078 + end + attribute \src "libresoc.v:49590.3-49591.43" + process $proc$libresoc.v:49590$3048 + assign { } { } + assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next + sync posedge \coresync_clk + update \ren_delay$51 $0\ren_delay$51[7:0]$3049 + end + attribute \src "libresoc.v:49592.3-49593.43" + process $proc$libresoc.v:49592$3050 + assign { } { } + assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next sync posedge \coresync_clk - update \ren_delay$34 $0\ren_delay$34[7:0]$3041 + update \ren_delay$34 $0\ren_delay$34[7:0]$3051 end - attribute \src "libresoc.v:49528.3-49529.43" - process $proc$libresoc.v:49528$3042 + attribute \src "libresoc.v:49594.3-49595.43" + process $proc$libresoc.v:49594$3052 assign { } { } - assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next + assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$3043 + update \ren_delay$17 $0\ren_delay$17[7:0]$3053 end - attribute \src "libresoc.v:49530.3-49531.35" - process $proc$libresoc.v:49530$3044 + attribute \src "libresoc.v:49596.3-49597.35" + process $proc$libresoc.v:49596$3054 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49692.3-49700.6" - process $proc$libresoc.v:49692$3045 + attribute \src "libresoc.v:49774.3-49782.6" + process $proc$libresoc.v:49774$3055 assign { } { } assign { } { } - assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49693.5-49693.29" + assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057 + attribute \src "libresoc.v:49775.5-49775.29" switch \initial - attribute \src "libresoc.v:49693.9-49693.17" + attribute \src "libresoc.v:49775.9-49775.17" case 1'1 case end @@ -86745,21 +86945,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$17$next[7:0]$3047 8'00000000 + assign $1\ren_delay$17$next[7:0]$3057 8'00000000 case - assign $1\ren_delay$17$next[7:0]$3047 \src2__ren + assign $1\ren_delay$17$next[7:0]$3057 \src1__ren end sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056 end - attribute \src "libresoc.v:49701.3-49710.6" - process $proc$libresoc.v:49701$3048 + attribute \src "libresoc.v:49783.3-49792.6" + process $proc$libresoc.v:49783$3058 assign { } { } assign { } { } - assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49702.5-49702.29" + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49784.5-49784.29" switch \initial - attribute \src "libresoc.v:49702.9-49702.17" + attribute \src "libresoc.v:49784.9-49784.17" case 1'1 case end @@ -86768,21 +86968,67 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src2__data_o[3:0] \$32 + assign $1\src1__data_o[3:0] \$32 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + attribute \src "libresoc.v:49793.3-49801.6" + process $proc$libresoc.v:49793$3059 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061 + attribute \src "libresoc.v:49794.5-49794.29" + switch \initial + attribute \src "libresoc.v:49794.9-49794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3061 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3061 \src2__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060 + end + attribute \src "libresoc.v:49802.3-49811.6" + process $proc$libresoc.v:49802$3062 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:49803.5-49803.29" + switch \initial + attribute \src "libresoc.v:49803.9-49803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$49 case assign $1\src2__data_o[3:0] 4'0000 end sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49711.3-49719.6" - process $proc$libresoc.v:49711$3049 + attribute \src "libresoc.v:49812.3-49820.6" + process $proc$libresoc.v:49812$3063 assign { } { } assign { } { } - assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49712.5-49712.29" + assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065 + attribute \src "libresoc.v:49813.5-49813.29" switch \initial - attribute \src "libresoc.v:49712.9-49712.17" + attribute \src "libresoc.v:49813.9-49813.17" case 1'1 case end @@ -86791,44 +87037,44 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$34$next[7:0]$3051 8'00000000 + assign $1\ren_delay$51$next[7:0]$3065 8'00000000 case - assign $1\ren_delay$34$next[7:0]$3051 \src3__ren + assign $1\ren_delay$51$next[7:0]$3065 \src3__ren end sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 + update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064 end - attribute \src "libresoc.v:49720.3-49729.6" - process $proc$libresoc.v:49720$3052 + attribute \src "libresoc.v:49821.3-49830.6" + process $proc$libresoc.v:49821$3066 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49721.5-49721.29" + attribute \src "libresoc.v:49822.5-49822.29" switch \initial - attribute \src "libresoc.v:49721.9-49721.17" + attribute \src "libresoc.v:49822.9-49822.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$35 + switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src3__data_o[3:0] \$49 + assign $1\src3__data_o[3:0] \$66 case assign $1\src3__data_o[3:0] 4'0000 end sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49730.3-49738.6" - process $proc$libresoc.v:49730$3053 + attribute \src "libresoc.v:49831.3-49839.6" + process $proc$libresoc.v:49831$3067 assign { } { } assign { } { } - assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49731.5-49731.29" + assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069 + attribute \src "libresoc.v:49832.5-49832.29" switch \initial - attribute \src "libresoc.v:49731.9-49731.17" + attribute \src "libresoc.v:49832.9-49832.17" case 1'1 case end @@ -86837,21 +87083,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[7:0]$3055 8'00000000 + assign $1\ren_delay$next[7:0]$3069 8'00000000 case - assign $1\ren_delay$next[7:0]$3055 \src1__ren + assign $1\ren_delay$next[7:0]$3069 \cr_pred__ren end sync always - update \ren_delay$next $0\ren_delay$next[7:0]$3054 + update \ren_delay$next $0\ren_delay$next[7:0]$3068 end - attribute \src "libresoc.v:49739.3-49748.6" - process $proc$libresoc.v:49739$3056 + attribute \src "libresoc.v:49840.3-49849.6" + process $proc$libresoc.v:49840$3070 assign { } { } assign { } { } - assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49740.5-49740.29" + assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0] + attribute \src "libresoc.v:49841.5-49841.29" switch \initial - attribute \src "libresoc.v:49740.9-49740.17" + attribute \src "libresoc.v:49841.9-49841.17" case 1'1 case end @@ -86860,39 +87106,48 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src1__data_o[3:0] \$15 - case - assign $1\src1__data_o[3:0] 4'0000 - end - sync always - update \src1__data_o $0\src1__data_o[3:0] - end - connect \$9 $or$libresoc.v:49502$3016_Y - connect \$11 $or$libresoc.v:49503$3017_Y - connect \$13 $or$libresoc.v:49504$3018_Y - connect \$15 $or$libresoc.v:49505$3019_Y - connect \$18 $reduce_or$libresoc.v:49506$3020_Y - connect \$1 $reduce_or$libresoc.v:49507$3021_Y - connect \$20 $or$libresoc.v:49508$3022_Y - connect \$22 $or$libresoc.v:49509$3023_Y - connect \$24 $or$libresoc.v:49510$3024_Y - connect \$26 $or$libresoc.v:49511$3025_Y - connect \$28 $or$libresoc.v:49512$3026_Y - connect \$30 $or$libresoc.v:49513$3027_Y - connect \$32 $or$libresoc.v:49514$3028_Y - connect \$35 $reduce_or$libresoc.v:49515$3029_Y - connect \$37 $or$libresoc.v:49516$3030_Y - connect \$3 $or$libresoc.v:49517$3031_Y - connect \$39 $or$libresoc.v:49518$3032_Y - connect \$41 $or$libresoc.v:49519$3033_Y - connect \$43 $or$libresoc.v:49520$3034_Y - connect \$45 $or$libresoc.v:49521$3035_Y - connect \$47 $or$libresoc.v:49522$3036_Y - connect \$49 $or$libresoc.v:49523$3037_Y - connect \$5 $or$libresoc.v:49524$3038_Y - connect \$7 $or$libresoc.v:49525$3039_Y - connect \wen$51 8'00000000 - connect \data_i$52 4'0000 + assign $1\cr_pred__data_o[3:0] \$15 + case + assign $1\cr_pred__data_o[3:0] 4'0000 + end + sync always + update \cr_pred__data_o $0\cr_pred__data_o[3:0] + end + connect \$9 $or$libresoc.v:49558$3016_Y + connect \$11 $or$libresoc.v:49559$3017_Y + connect \$13 $or$libresoc.v:49560$3018_Y + connect \$15 $or$libresoc.v:49561$3019_Y + connect \$18 $reduce_or$libresoc.v:49562$3020_Y + connect \$1 $reduce_or$libresoc.v:49563$3021_Y + connect \$20 $or$libresoc.v:49564$3022_Y + connect \$22 $or$libresoc.v:49565$3023_Y + connect \$24 $or$libresoc.v:49566$3024_Y + connect \$26 $or$libresoc.v:49567$3025_Y + connect \$28 $or$libresoc.v:49568$3026_Y + connect \$30 $or$libresoc.v:49569$3027_Y + connect \$32 $or$libresoc.v:49570$3028_Y + connect \$35 $reduce_or$libresoc.v:49571$3029_Y + connect \$37 $or$libresoc.v:49572$3030_Y + connect \$3 $or$libresoc.v:49573$3031_Y + connect \$39 $or$libresoc.v:49574$3032_Y + connect \$41 $or$libresoc.v:49575$3033_Y + connect \$43 $or$libresoc.v:49576$3034_Y + connect \$45 $or$libresoc.v:49577$3035_Y + connect \$47 $or$libresoc.v:49578$3036_Y + connect \$49 $or$libresoc.v:49579$3037_Y + connect \$52 $reduce_or$libresoc.v:49580$3038_Y + connect \$54 $or$libresoc.v:49581$3039_Y + connect \$56 $or$libresoc.v:49582$3040_Y + connect \$58 $or$libresoc.v:49583$3041_Y + connect \$5 $or$libresoc.v:49584$3042_Y + connect \$60 $or$libresoc.v:49585$3043_Y + connect \$62 $or$libresoc.v:49586$3044_Y + connect \$64 $or$libresoc.v:49587$3045_Y + connect \$66 $or$libresoc.v:49588$3046_Y + connect \$7 $or$libresoc.v:49589$3047_Y + connect \cr_pred__ren 8'00000000 + connect \wen$68 8'00000000 + connect \data_i$69 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren @@ -86920,394 +87175,395 @@ module \cr connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000 end -attribute \src "libresoc.v:49782.1-50839.10" +attribute \src "libresoc.v:49885.1-50942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50440.3-50441.25" + attribute \src "libresoc.v:50543.3-50544.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 - attribute \src "libresoc.v:50412.3-50413.61" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + attribute \src "libresoc.v:50515.3-50516.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:50414.3-50415.55" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199 + attribute \src "libresoc.v:50517.3-50518.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:50410.3-50411.65" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 + attribute \src "libresoc.v:50513.3-50514.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50438.3-50439.39" + attribute \src "libresoc.v:50541.3-50542.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50760.3-50768.6" - wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:50382.3-50383.39" + attribute \src "libresoc.v:50863.3-50871.6" + wire $0\alu_l_r_alu$next[0:0]$3250 + attribute \src "libresoc.v:50485.3-50486.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50751.3-50759.6" - wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:50384.3-50385.43" + attribute \src "libresoc.v:50854.3-50862.6" + wire $0\alui_l_r_alui$next[0:0]$3247 + attribute \src "libresoc.v:50487.3-50488.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:50406.3-50407.37" + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $0\data_r0__o$next[63:0]$3205 + attribute \src "libresoc.v:50509.3-50510.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:50408.3-50409.43" + attribute \src "libresoc.v:50728.3-50749.6" + wire $0\data_r0__o_ok$next[0:0]$3206 + attribute \src "libresoc.v:50511.3-50512.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:50402.3-50403.49" + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3213 + attribute \src "libresoc.v:50505.3-50506.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:50404.3-50405.55" + attribute \src "libresoc.v:50750.3-50771.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3214 + attribute \src "libresoc.v:50507.3-50508.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:50398.3-50399.43" + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3221 + attribute \src "libresoc.v:50501.3-50502.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:50400.3-50401.49" + attribute \src "libresoc.v:50772.3-50793.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3222 + attribute \src "libresoc.v:50503.3-50504.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50872.3-50881.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50779.3-50788.6" + attribute \src "libresoc.v:50882.3-50891.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50789.3-50798.6" + attribute \src "libresoc.v:50892.3-50901.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49783.7-49783.20" + attribute \src "libresoc.v:49886.7-49886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50568.3-50576.6" - wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:50424.3-50425.39" + attribute \src "libresoc.v:50671.3-50679.6" + wire $0\opc_l_r_opc$next[0:0]$3183 + attribute \src "libresoc.v:50527.3-50528.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50559.3-50567.6" - wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:50426.3-50427.39" + attribute \src "libresoc.v:50662.3-50670.6" + wire $0\opc_l_s_opc$next[0:0]$3180 + attribute \src "libresoc.v:50529.3-50530.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50799.3-50807.6" - wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:50436.3-50437.37" + attribute \src "libresoc.v:50902.3-50910.6" + wire width 3 $0\prev_wr_go$next[2:0]$3256 + attribute \src "libresoc.v:50539.3-50540.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50513.3-50522.6" + attribute \src "libresoc.v:50616.3-50625.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50604.3-50612.6" - wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:50416.3-50417.39" + attribute \src "libresoc.v:50707.3-50715.6" + wire width 3 $0\req_l_r_req$next[2:0]$3195 + attribute \src "libresoc.v:50519.3-50520.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50595.3-50603.6" - wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:50418.3-50419.39" + attribute \src "libresoc.v:50698.3-50706.6" + wire width 3 $0\req_l_s_req$next[2:0]$3192 + attribute \src "libresoc.v:50521.3-50522.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50532.3-50540.6" - wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:50432.3-50433.41" + attribute \src "libresoc.v:50635.3-50643.6" + wire $0\rok_l_r_rdok$next[0:0]$3171 + attribute \src "libresoc.v:50535.3-50536.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50523.3-50531.6" - wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:50434.3-50435.41" + attribute \src "libresoc.v:50626.3-50634.6" + wire $0\rok_l_s_rdok$next[0:0]$3168 + attribute \src "libresoc.v:50537.3-50538.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50550.3-50558.6" - wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:50428.3-50429.39" + attribute \src "libresoc.v:50653.3-50661.6" + wire $0\rst_l_r_rst$next[0:0]$3177 + attribute \src "libresoc.v:50531.3-50532.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50541.3-50549.6" - wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:50430.3-50431.39" + attribute \src "libresoc.v:50644.3-50652.6" + wire $0\rst_l_s_rst$next[0:0]$3174 + attribute \src "libresoc.v:50533.3-50534.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50586.3-50594.6" - wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:50420.3-50421.39" + attribute \src "libresoc.v:50689.3-50697.6" + wire width 6 $0\src_l_r_src$next[5:0]$3189 + attribute \src "libresoc.v:50523.3-50524.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50577.3-50585.6" - wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:50422.3-50423.39" + attribute \src "libresoc.v:50680.3-50688.6" + wire width 6 $0\src_l_s_src$next[5:0]$3186 + attribute \src "libresoc.v:50525.3-50526.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50691.3-50700.6" - wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:50396.3-50397.29" + attribute \src "libresoc.v:50794.3-50803.6" + wire width 64 $0\src_r0$next[63:0]$3229 + attribute \src "libresoc.v:50499.3-50500.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50701.3-50710.6" - wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:50394.3-50395.29" + attribute \src "libresoc.v:50804.3-50813.6" + wire width 64 $0\src_r1$next[63:0]$3232 + attribute \src "libresoc.v:50497.3-50498.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50711.3-50720.6" - wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:50392.3-50393.29" + attribute \src "libresoc.v:50814.3-50823.6" + wire width 32 $0\src_r2$next[31:0]$3235 + attribute \src "libresoc.v:50495.3-50496.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50721.3-50730.6" - wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:50390.3-50391.29" + attribute \src "libresoc.v:50824.3-50833.6" + wire width 4 $0\src_r3$next[3:0]$3238 + attribute \src "libresoc.v:50493.3-50494.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50731.3-50740.6" - wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:50388.3-50389.29" + attribute \src "libresoc.v:50834.3-50843.6" + wire width 4 $0\src_r4$next[3:0]$3241 + attribute \src "libresoc.v:50491.3-50492.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50741.3-50750.6" - wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:50386.3-50387.29" + attribute \src "libresoc.v:50844.3-50853.6" + wire width 4 $0\src_r5$next[3:0]$3244 + attribute \src "libresoc.v:50489.3-50490.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49901.7-49901.24" + attribute \src "libresoc.v:50004.7-50004.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 - attribute \src "libresoc.v:49932.14-49932.47" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + attribute \src "libresoc.v:50035.14-50035.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49936.14-49936.41" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + attribute \src "libresoc.v:50039.14-50039.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50015.13-50015.45" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50118.13-50118.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50039.7-50039.26" + attribute \src "libresoc.v:50142.7-50142.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50760.3-50768.6" - wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50047.7-50047.25" + attribute \src "libresoc.v:50863.3-50871.6" + wire $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50150.7-50150.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50751.3-50759.6" - wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50059.7-50059.27" + attribute \src "libresoc.v:50854.3-50862.6" + wire $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50162.7-50162.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:50093.14-50093.47" + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $1\data_r0__o$next[63:0]$3207 + attribute \src "libresoc.v:50196.14-50196.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:50097.7-50097.27" + attribute \src "libresoc.v:50728.3-50749.6" + wire $1\data_r0__o_ok$next[0:0]$3208 + attribute \src "libresoc.v:50200.7-50200.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:50101.14-50101.38" + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3215 + attribute \src "libresoc.v:50204.14-50204.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:50105.7-50105.33" + attribute \src "libresoc.v:50750.3-50771.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3216 + attribute \src "libresoc.v:50208.7-50208.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:50109.13-50109.33" + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3223 + attribute \src "libresoc.v:50212.13-50212.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:50113.7-50113.30" + attribute \src "libresoc.v:50772.3-50793.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3224 + attribute \src "libresoc.v:50216.7-50216.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50872.3-50881.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50779.3-50788.6" + attribute \src "libresoc.v:50882.3-50891.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50789.3-50798.6" + attribute \src "libresoc.v:50892.3-50901.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50568.3-50576.6" - wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50132.7-50132.25" + attribute \src "libresoc.v:50671.3-50679.6" + wire $1\opc_l_r_opc$next[0:0]$3184 + attribute \src "libresoc.v:50235.7-50235.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50559.3-50567.6" - wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50136.7-50136.25" + attribute \src "libresoc.v:50662.3-50670.6" + wire $1\opc_l_s_opc$next[0:0]$3181 + attribute \src "libresoc.v:50239.7-50239.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50799.3-50807.6" - wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50236.13-50236.30" + attribute \src "libresoc.v:50902.3-50910.6" + wire width 3 $1\prev_wr_go$next[2:0]$3257 + attribute \src "libresoc.v:50339.13-50339.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50513.3-50522.6" + attribute \src "libresoc.v:50616.3-50625.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50604.3-50612.6" - wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50244.13-50244.31" + attribute \src "libresoc.v:50707.3-50715.6" + wire width 3 $1\req_l_r_req$next[2:0]$3196 + attribute \src "libresoc.v:50347.13-50347.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50595.3-50603.6" - wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50248.13-50248.31" + attribute \src "libresoc.v:50698.3-50706.6" + wire width 3 $1\req_l_s_req$next[2:0]$3193 + attribute \src "libresoc.v:50351.13-50351.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50532.3-50540.6" - wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50260.7-50260.26" + attribute \src "libresoc.v:50635.3-50643.6" + wire $1\rok_l_r_rdok$next[0:0]$3172 + attribute \src "libresoc.v:50363.7-50363.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50523.3-50531.6" - wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50264.7-50264.26" + attribute \src "libresoc.v:50626.3-50634.6" + wire $1\rok_l_s_rdok$next[0:0]$3169 + attribute \src "libresoc.v:50367.7-50367.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50550.3-50558.6" - wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50268.7-50268.25" + attribute \src "libresoc.v:50653.3-50661.6" + wire $1\rst_l_r_rst$next[0:0]$3178 + attribute \src "libresoc.v:50371.7-50371.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50541.3-50549.6" - wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50272.7-50272.25" + attribute \src "libresoc.v:50644.3-50652.6" + wire $1\rst_l_s_rst$next[0:0]$3175 + attribute \src "libresoc.v:50375.7-50375.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50586.3-50594.6" - wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50292.13-50292.32" + attribute \src "libresoc.v:50689.3-50697.6" + wire width 6 $1\src_l_r_src$next[5:0]$3190 + attribute \src "libresoc.v:50395.13-50395.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50577.3-50585.6" - wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50296.13-50296.32" + attribute \src "libresoc.v:50680.3-50688.6" + wire width 6 $1\src_l_s_src$next[5:0]$3187 + attribute \src "libresoc.v:50399.13-50399.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50691.3-50700.6" - wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50300.14-50300.43" + attribute \src "libresoc.v:50794.3-50803.6" + wire width 64 $1\src_r0$next[63:0]$3230 + attribute \src "libresoc.v:50403.14-50403.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50701.3-50710.6" - wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50304.14-50304.43" + attribute \src "libresoc.v:50804.3-50813.6" + wire width 64 $1\src_r1$next[63:0]$3233 + attribute \src "libresoc.v:50407.14-50407.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50711.3-50720.6" - wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50308.14-50308.28" + attribute \src "libresoc.v:50814.3-50823.6" + wire width 32 $1\src_r2$next[31:0]$3236 + attribute \src "libresoc.v:50411.14-50411.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50721.3-50730.6" - wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50312.13-50312.26" + attribute \src "libresoc.v:50824.3-50833.6" + wire width 4 $1\src_r3$next[3:0]$3239 + attribute \src "libresoc.v:50415.13-50415.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50731.3-50740.6" - wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50316.13-50316.26" + attribute \src "libresoc.v:50834.3-50843.6" + wire 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$or$libresoc.v:50464$3115_Y + attribute \src "libresoc.v:50465.18-50465.194" + wire width 6 $or$libresoc.v:50465$3116_Y + attribute \src "libresoc.v:50469.18-50469.120" + wire width 3 $or$libresoc.v:50469$3120_Y + attribute \src "libresoc.v:50479.17-50479.117" + wire width 6 $or$libresoc.v:50479$3130_Y + attribute \src "libresoc.v:50428.17-50428.104" + wire $reduce_and$libresoc.v:50428$3079_Y + attribute \src "libresoc.v:50446.18-50446.106" + wire $reduce_or$libresoc.v:50446$3097_Y + attribute \src "libresoc.v:50449.18-50449.113" + wire $reduce_or$libresoc.v:50449$3100_Y + attribute \src "libresoc.v:50450.18-50450.112" + wire $reduce_or$libresoc.v:50450$3101_Y + attribute \src "libresoc.v:50473.18-50473.118" + wire width 64 $ternary$libresoc.v:50473$3124_Y + attribute \src "libresoc.v:50474.18-50474.118" + wire width 64 $ternary$libresoc.v:50474$3125_Y + attribute \src "libresoc.v:50475.18-50475.118" + wire width 32 $ternary$libresoc.v:50475$3126_Y + attribute \src "libresoc.v:50476.18-50476.118" + wire width 4 $ternary$libresoc.v:50476$3127_Y + attribute \src "libresoc.v:50477.18-50477.118" + wire width 4 $ternary$libresoc.v:50477$3128_Y + attribute \src "libresoc.v:50478.18-50478.118" + wire width 4 $ternary$libresoc.v:50478$3129_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87588,9 +87844,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87648,7 +87904,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49783.7-49783.15" + attribute \src "libresoc.v:49886.7-49886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok @@ -87849,7 +88105,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50326$3064 + cell $and $and$libresoc.v:50429$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87857,10 +88113,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50326$3064_Y + connect \Y $and$libresoc.v:50429$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50327$3065 + cell $and $and$libresoc.v:50430$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87868,10 +88124,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50327$3065_Y + connect \Y $and$libresoc.v:50430$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50328$3066 + cell $and $and$libresoc.v:50431$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87879,10 +88135,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50328$3066_Y + connect \Y $and$libresoc.v:50431$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50329$3067 + cell $and $and$libresoc.v:50432$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87890,10 +88146,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50329$3067_Y + connect \Y $and$libresoc.v:50432$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50330$3068 + cell $and $and$libresoc.v:50433$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87901,10 +88157,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50330$3068_Y + connect \Y $and$libresoc.v:50433$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50331$3069 + cell $and $and$libresoc.v:50434$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87912,10 +88168,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50331$3069_Y + connect \Y $and$libresoc.v:50434$3085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50332$3070 + cell $and $and$libresoc.v:50435$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87923,10 +88179,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50332$3070_Y + connect \Y $and$libresoc.v:50435$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50333$3071 + cell $and $and$libresoc.v:50436$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87934,10 +88190,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50333$3071_Y + connect \Y $and$libresoc.v:50436$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50334$3072 + cell $and $and$libresoc.v:50437$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87945,10 +88201,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50334$3072_Y + connect \Y $and$libresoc.v:50437$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50335$3073 + cell $and $and$libresoc.v:50438$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87956,10 +88212,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50335$3073_Y + connect \Y $and$libresoc.v:50438$3089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50337$3075 + cell $and $and$libresoc.v:50440$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87967,10 +88223,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50337$3075_Y + connect \Y $and$libresoc.v:50440$3091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50339$3077 + cell $and $and$libresoc.v:50442$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87978,10 +88234,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50339$3077_Y + connect \Y $and$libresoc.v:50442$3093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50340$3078 + cell $and $and$libresoc.v:50443$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87989,10 +88245,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50340$3078_Y + connect \Y $and$libresoc.v:50443$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50342$3080 + cell $and $and$libresoc.v:50445$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88000,10 +88256,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50342$3080_Y + connect \Y $and$libresoc.v:50445$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50345$3083 + cell $and $and$libresoc.v:50448$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88011,10 +88267,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50345$3083_Y + connect \Y $and$libresoc.v:50448$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50349$3087 + cell $and $and$libresoc.v:50452$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88022,10 +88278,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50349$3087_Y + connect \Y $and$libresoc.v:50452$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50351$3089 + cell $and $and$libresoc.v:50454$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88033,10 +88289,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50351$3089_Y + connect \Y $and$libresoc.v:50454$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50352$3090 + cell $and $and$libresoc.v:50455$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88044,10 +88300,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50352$3090_Y + connect \Y $and$libresoc.v:50455$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50354$3092 + cell $and $and$libresoc.v:50457$3108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88055,10 +88311,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50354$3092_Y + connect \Y $and$libresoc.v:50457$3108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50356$3094 + cell $and $and$libresoc.v:50459$3110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88066,10 +88322,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50356$3094_Y + connect \Y $and$libresoc.v:50459$3110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50357$3095 + cell $and $and$libresoc.v:50460$3111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88077,10 +88333,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50357$3095_Y + connect \Y $and$libresoc.v:50460$3111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50358$3096 + cell $and $and$libresoc.v:50461$3112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88088,10 +88344,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50358$3096_Y + connect \Y $and$libresoc.v:50461$3112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50363$3101 + cell $and $and$libresoc.v:50466$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88099,10 +88355,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50363$3101_Y + connect \Y $and$libresoc.v:50466$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50364$3102 + cell $and $and$libresoc.v:50467$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88110,10 +88366,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50364$3102_Y + connect \Y $and$libresoc.v:50467$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50367$3105 + cell $and $and$libresoc.v:50470$3121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88121,10 +88377,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50367$3105_Y + connect \Y $and$libresoc.v:50470$3121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50368$3106 + cell $and $and$libresoc.v:50471$3122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88132,10 +88388,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50368$3106_Y + connect \Y $and$libresoc.v:50471$3122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50369$3107 + cell $and $and$libresoc.v:50472$3123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88143,10 +88399,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50369$3107_Y + connect \Y $and$libresoc.v:50472$3123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50377$3115 + cell $and $and$libresoc.v:50480$3131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88154,10 +88410,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50377$3115_Y + connect \Y $and$libresoc.v:50480$3131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50378$3116 + cell $and $and$libresoc.v:50481$3132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88165,10 +88421,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50378$3116_Y + connect \Y $and$libresoc.v:50481$3132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50379$3117 + cell $and $and$libresoc.v:50482$3133 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88176,10 +88432,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50379$3117_Y + connect \Y $and$libresoc.v:50482$3133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50380$3118 + cell $and $and$libresoc.v:50483$3134 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88187,10 +88443,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50380$3118_Y + connect \Y $and$libresoc.v:50483$3134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50353$3091 + cell $eq $eq$libresoc.v:50456$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88198,10 +88454,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50353$3091_Y + connect \Y $eq$libresoc.v:50456$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50355$3093 + cell $eq $eq$libresoc.v:50458$3109 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88209,66 +88465,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50355$3093_Y + connect \Y $eq$libresoc.v:50458$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50336$3074 + cell $not $not$libresoc.v:50439$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50336$3074_Y + connect \Y $not$libresoc.v:50439$3090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50338$3076 + cell $not $not$libresoc.v:50441$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50338$3076_Y + connect \Y $not$libresoc.v:50441$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50341$3079 + cell $not $not$libresoc.v:50444$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50341$3079_Y + connect \Y $not$libresoc.v:50444$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50344$3082 + cell $not $not$libresoc.v:50447$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50344$3082_Y + connect \Y $not$libresoc.v:50447$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50350$3088 + cell $not $not$libresoc.v:50453$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50350$3088_Y + connect \Y $not$libresoc.v:50453$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50365$3103 + cell $not $not$libresoc.v:50468$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50365$3103_Y + connect \Y $not$libresoc.v:50468$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50381$3119 + cell $not $not$libresoc.v:50484$3135 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50381$3119_Y + connect \Y $not$libresoc.v:50484$3135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50348$3086 + cell $or $or$libresoc.v:50451$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88276,10 +88532,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50348$3086_Y + connect \Y $or$libresoc.v:50451$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50359$3097 + cell $or $or$libresoc.v:50462$3113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88287,10 +88543,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50359$3097_Y + connect \Y $or$libresoc.v:50462$3113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50360$3098 + cell $or $or$libresoc.v:50463$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88298,10 +88554,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50360$3098_Y + connect \Y $or$libresoc.v:50463$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50361$3099 + cell $or $or$libresoc.v:50464$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88309,10 +88565,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50361$3099_Y + connect \Y $or$libresoc.v:50464$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50362$3100 + cell $or $or$libresoc.v:50465$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88320,10 +88576,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50362$3100_Y + connect \Y $or$libresoc.v:50465$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50366$3104 + cell $or $or$libresoc.v:50469$3120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88331,10 +88587,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50366$3104_Y + connect \Y $or$libresoc.v:50469$3120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50376$3114 + cell $or $or$libresoc.v:50479$3130 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88342,90 +88598,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50376$3114_Y + connect \Y $or$libresoc.v:50479$3130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50325$3063 + cell $reduce_and $reduce_and$libresoc.v:50428$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50325$3063_Y + connect \Y $reduce_and$libresoc.v:50428$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50343$3081 + cell $reduce_or $reduce_or$libresoc.v:50446$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50343$3081_Y + connect \Y $reduce_or$libresoc.v:50446$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50346$3084 + cell $reduce_or $reduce_or$libresoc.v:50449$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50346$3084_Y + connect \Y $reduce_or$libresoc.v:50449$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50347$3085 + cell $reduce_or $reduce_or$libresoc.v:50450$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50347$3085_Y + connect \Y $reduce_or$libresoc.v:50450$3101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50370$3108 + cell $mux $ternary$libresoc.v:50473$3124 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50370$3108_Y + connect \Y $ternary$libresoc.v:50473$3124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50371$3109 + cell $mux $ternary$libresoc.v:50474$3125 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50371$3109_Y + connect \Y $ternary$libresoc.v:50474$3125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50372$3110 + cell $mux $ternary$libresoc.v:50475$3126 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50372$3110_Y + connect \Y $ternary$libresoc.v:50475$3126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50373$3111 + cell $mux $ternary$libresoc.v:50476$3127 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50373$3111_Y + connect \Y $ternary$libresoc.v:50476$3127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50374$3112 + cell $mux $ternary$libresoc.v:50477$3128 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50374$3112_Y + connect \Y $ternary$libresoc.v:50477$3128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50375$3113 + cell $mux $ternary$libresoc.v:50478$3129 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50375$3113_Y + connect \Y $ternary$libresoc.v:50478$3129_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50442.11-50464.4" + attribute \src "libresoc.v:50545.11-50567.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88450,7 +88706,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50465.14-50471.4" + attribute \src "libresoc.v:50568.14-50574.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88459,7 +88715,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50472.15-50478.4" + attribute \src "libresoc.v:50575.15-50581.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88468,7 +88724,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50479.14-50485.4" + attribute \src "libresoc.v:50582.14-50588.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88477,7 +88733,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50486.14-50492.4" + attribute \src "libresoc.v:50589.14-50595.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88486,7 +88742,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50493.14-50499.4" + attribute \src "libresoc.v:50596.14-50602.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88495,7 +88751,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50500.14-50505.4" + attribute \src "libresoc.v:50603.14-50608.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88503,7 +88759,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50506.14-50512.4" + attribute \src "libresoc.v:50609.14-50615.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88511,472 +88767,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49783.7-49783.20" - process $proc$libresoc.v:49783$3242 + attribute \src "libresoc.v:49886.7-49886.20" + process $proc$libresoc.v:49886$3258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49901.7-49901.24" - process $proc$libresoc.v:49901$3243 + attribute \src "libresoc.v:50004.7-50004.24" + process $proc$libresoc.v:50004$3259 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49932.14-49932.47" - process $proc$libresoc.v:49932$3244 + attribute \src "libresoc.v:50035.14-50035.47" + process $proc$libresoc.v:50035$3260 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49936.14-49936.41" - process $proc$libresoc.v:49936$3245 + attribute \src "libresoc.v:50039.14-50039.41" + process $proc$libresoc.v:50039$3261 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50015.13-50015.45" - process $proc$libresoc.v:50015$3246 + attribute \src "libresoc.v:50118.13-50118.45" + process $proc$libresoc.v:50118$3262 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50039.7-50039.26" - process $proc$libresoc.v:50039$3247 + attribute \src "libresoc.v:50142.7-50142.26" + process $proc$libresoc.v:50142$3263 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:50047.7-50047.25" - process $proc$libresoc.v:50047$3248 + attribute \src "libresoc.v:50150.7-50150.25" + process $proc$libresoc.v:50150$3264 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50059.7-50059.27" - process $proc$libresoc.v:50059$3249 + attribute \src "libresoc.v:50162.7-50162.27" + process $proc$libresoc.v:50162$3265 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50093.14-50093.47" - process $proc$libresoc.v:50093$3250 + attribute \src "libresoc.v:50196.14-50196.47" + process $proc$libresoc.v:50196$3266 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:50097.7-50097.27" - process $proc$libresoc.v:50097$3251 + attribute \src "libresoc.v:50200.7-50200.27" + process $proc$libresoc.v:50200$3267 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50101.14-50101.38" - process $proc$libresoc.v:50101$3252 + attribute \src "libresoc.v:50204.14-50204.38" + process $proc$libresoc.v:50204$3268 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50105.7-50105.33" - process $proc$libresoc.v:50105$3253 + attribute \src "libresoc.v:50208.7-50208.33" + process $proc$libresoc.v:50208$3269 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50109.13-50109.33" - process $proc$libresoc.v:50109$3254 + attribute \src "libresoc.v:50212.13-50212.33" + process $proc$libresoc.v:50212$3270 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50113.7-50113.30" - process $proc$libresoc.v:50113$3255 + attribute \src "libresoc.v:50216.7-50216.30" + process $proc$libresoc.v:50216$3271 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50132.7-50132.25" - process $proc$libresoc.v:50132$3256 + attribute \src "libresoc.v:50235.7-50235.25" + process $proc$libresoc.v:50235$3272 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50136.7-50136.25" - process $proc$libresoc.v:50136$3257 + attribute \src "libresoc.v:50239.7-50239.25" + process $proc$libresoc.v:50239$3273 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50236.13-50236.30" - process $proc$libresoc.v:50236$3258 + attribute \src "libresoc.v:50339.13-50339.30" + process $proc$libresoc.v:50339$3274 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:50244.13-50244.31" - process $proc$libresoc.v:50244$3259 + attribute \src "libresoc.v:50347.13-50347.31" + process $proc$libresoc.v:50347$3275 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:50248.13-50248.31" - process $proc$libresoc.v:50248$3260 + attribute \src "libresoc.v:50351.13-50351.31" + process $proc$libresoc.v:50351$3276 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:50260.7-50260.26" - process $proc$libresoc.v:50260$3261 + attribute \src "libresoc.v:50363.7-50363.26" + process $proc$libresoc.v:50363$3277 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50264.7-50264.26" - process $proc$libresoc.v:50264$3262 + attribute \src "libresoc.v:50367.7-50367.26" + process $proc$libresoc.v:50367$3278 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50268.7-50268.25" - process $proc$libresoc.v:50268$3263 + attribute \src "libresoc.v:50371.7-50371.25" + process $proc$libresoc.v:50371$3279 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50272.7-50272.25" - process $proc$libresoc.v:50272$3264 + attribute \src "libresoc.v:50375.7-50375.25" + process $proc$libresoc.v:50375$3280 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50292.13-50292.32" - process $proc$libresoc.v:50292$3265 + attribute \src "libresoc.v:50395.13-50395.32" + process $proc$libresoc.v:50395$3281 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:50296.13-50296.32" - process $proc$libresoc.v:50296$3266 + attribute \src "libresoc.v:50399.13-50399.32" + process $proc$libresoc.v:50399$3282 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:50300.14-50300.43" - process $proc$libresoc.v:50300$3267 + attribute \src "libresoc.v:50403.14-50403.43" + process $proc$libresoc.v:50403$3283 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50304.14-50304.43" - process $proc$libresoc.v:50304$3268 + attribute \src "libresoc.v:50407.14-50407.43" + process $proc$libresoc.v:50407$3284 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50308.14-50308.28" - process $proc$libresoc.v:50308$3269 + attribute \src "libresoc.v:50411.14-50411.28" + process $proc$libresoc.v:50411$3285 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50312.13-50312.26" - process $proc$libresoc.v:50312$3270 + attribute \src "libresoc.v:50415.13-50415.26" + process $proc$libresoc.v:50415$3286 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50316.13-50316.26" - process $proc$libresoc.v:50316$3271 + attribute \src "libresoc.v:50419.13-50419.26" + process $proc$libresoc.v:50419$3287 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50320.13-50320.26" - process $proc$libresoc.v:50320$3272 + attribute \src "libresoc.v:50423.13-50423.26" + process $proc$libresoc.v:50423$3288 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50382.3-50383.39" - process $proc$libresoc.v:50382$3120 + attribute \src "libresoc.v:50485.3-50486.39" + process $proc$libresoc.v:50485$3136 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50384.3-50385.43" - process $proc$libresoc.v:50384$3121 + attribute \src "libresoc.v:50487.3-50488.43" + process $proc$libresoc.v:50487$3137 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50386.3-50387.29" - process $proc$libresoc.v:50386$3122 + attribute \src "libresoc.v:50489.3-50490.29" + process $proc$libresoc.v:50489$3138 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50388.3-50389.29" - process $proc$libresoc.v:50388$3123 + attribute \src "libresoc.v:50491.3-50492.29" + process $proc$libresoc.v:50491$3139 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50390.3-50391.29" - process $proc$libresoc.v:50390$3124 + attribute \src "libresoc.v:50493.3-50494.29" + process $proc$libresoc.v:50493$3140 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50392.3-50393.29" - process $proc$libresoc.v:50392$3125 + attribute \src "libresoc.v:50495.3-50496.29" + process $proc$libresoc.v:50495$3141 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50394.3-50395.29" - process $proc$libresoc.v:50394$3126 + attribute \src "libresoc.v:50497.3-50498.29" + process $proc$libresoc.v:50497$3142 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50396.3-50397.29" - process $proc$libresoc.v:50396$3127 + attribute \src "libresoc.v:50499.3-50500.29" + process $proc$libresoc.v:50499$3143 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50398.3-50399.43" - process $proc$libresoc.v:50398$3128 + attribute \src "libresoc.v:50501.3-50502.43" + process $proc$libresoc.v:50501$3144 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50400.3-50401.49" - process $proc$libresoc.v:50400$3129 + attribute \src "libresoc.v:50503.3-50504.49" + process $proc$libresoc.v:50503$3145 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50402.3-50403.49" - process $proc$libresoc.v:50402$3130 + attribute \src "libresoc.v:50505.3-50506.49" + process $proc$libresoc.v:50505$3146 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50404.3-50405.55" - process $proc$libresoc.v:50404$3131 + attribute \src "libresoc.v:50507.3-50508.55" + process $proc$libresoc.v:50507$3147 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50406.3-50407.37" - process $proc$libresoc.v:50406$3132 + attribute \src "libresoc.v:50509.3-50510.37" + process $proc$libresoc.v:50509$3148 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50408.3-50409.43" - process $proc$libresoc.v:50408$3133 + attribute \src "libresoc.v:50511.3-50512.43" + process $proc$libresoc.v:50511$3149 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50410.3-50411.65" - process $proc$libresoc.v:50410$3134 + attribute \src "libresoc.v:50513.3-50514.65" + process $proc$libresoc.v:50513$3150 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50412.3-50413.61" - process $proc$libresoc.v:50412$3135 + attribute \src "libresoc.v:50515.3-50516.61" + process $proc$libresoc.v:50515$3151 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50414.3-50415.55" - process $proc$libresoc.v:50414$3136 + attribute \src "libresoc.v:50517.3-50518.55" + process $proc$libresoc.v:50517$3152 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50416.3-50417.39" - process $proc$libresoc.v:50416$3137 + attribute \src "libresoc.v:50519.3-50520.39" + process $proc$libresoc.v:50519$3153 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50418.3-50419.39" - process $proc$libresoc.v:50418$3138 + attribute \src "libresoc.v:50521.3-50522.39" + process $proc$libresoc.v:50521$3154 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50420.3-50421.39" - process $proc$libresoc.v:50420$3139 + attribute \src "libresoc.v:50523.3-50524.39" + process $proc$libresoc.v:50523$3155 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50422.3-50423.39" - process $proc$libresoc.v:50422$3140 + attribute \src "libresoc.v:50525.3-50526.39" + process $proc$libresoc.v:50525$3156 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50424.3-50425.39" - process $proc$libresoc.v:50424$3141 + attribute \src "libresoc.v:50527.3-50528.39" + process $proc$libresoc.v:50527$3157 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50426.3-50427.39" - process $proc$libresoc.v:50426$3142 + attribute \src "libresoc.v:50529.3-50530.39" + process $proc$libresoc.v:50529$3158 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50428.3-50429.39" - process $proc$libresoc.v:50428$3143 + attribute \src "libresoc.v:50531.3-50532.39" + process $proc$libresoc.v:50531$3159 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50430.3-50431.39" - process $proc$libresoc.v:50430$3144 + attribute \src "libresoc.v:50533.3-50534.39" + process $proc$libresoc.v:50533$3160 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50432.3-50433.41" - process $proc$libresoc.v:50432$3145 + attribute \src "libresoc.v:50535.3-50536.41" + process $proc$libresoc.v:50535$3161 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50434.3-50435.41" - process $proc$libresoc.v:50434$3146 + attribute \src "libresoc.v:50537.3-50538.41" + process $proc$libresoc.v:50537$3162 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50436.3-50437.37" - process $proc$libresoc.v:50436$3147 + attribute \src "libresoc.v:50539.3-50540.37" + process $proc$libresoc.v:50539$3163 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50438.3-50439.39" - process $proc$libresoc.v:50438$3148 + attribute \src "libresoc.v:50541.3-50542.39" + process $proc$libresoc.v:50541$3164 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50440.3-50441.25" - process $proc$libresoc.v:50440$3149 + attribute \src "libresoc.v:50543.3-50544.25" + process $proc$libresoc.v:50543$3165 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50513.3-50522.6" - process $proc$libresoc.v:50513$3150 + attribute \src "libresoc.v:50616.3-50625.6" + process $proc$libresoc.v:50616$3166 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50514.5-50514.29" + attribute \src "libresoc.v:50617.5-50617.29" switch \initial - attribute \src "libresoc.v:50514.9-50514.17" + attribute \src "libresoc.v:50617.9-50617.17" case 1'1 case end @@ -88992,14 +89248,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50523.3-50531.6" - process $proc$libresoc.v:50523$3151 + attribute \src "libresoc.v:50626.3-50634.6" + process $proc$libresoc.v:50626$3167 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50524.5-50524.29" + assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169 + attribute \src "libresoc.v:50627.5-50627.29" switch \initial - attribute \src "libresoc.v:50524.9-50524.17" + attribute \src "libresoc.v:50627.9-50627.17" case 1'1 case end @@ -89008,21 +89264,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 + assign $1\rok_l_s_rdok$next[0:0]$3169 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$3169 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168 end - attribute \src "libresoc.v:50532.3-50540.6" - process $proc$libresoc.v:50532$3154 + attribute \src "libresoc.v:50635.3-50643.6" + process $proc$libresoc.v:50635$3170 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50533.5-50533.29" + assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172 + attribute \src "libresoc.v:50636.5-50636.29" switch \initial - attribute \src "libresoc.v:50533.9-50533.17" + attribute \src "libresoc.v:50636.9-50636.17" case 1'1 case end @@ -89031,21 +89287,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 + assign $1\rok_l_r_rdok$next[0:0]$3172 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 + assign $1\rok_l_r_rdok$next[0:0]$3172 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171 end - attribute \src "libresoc.v:50541.3-50549.6" - process $proc$libresoc.v:50541$3157 + attribute \src "libresoc.v:50644.3-50652.6" + process $proc$libresoc.v:50644$3173 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50542.5-50542.29" + assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175 + attribute \src "libresoc.v:50645.5-50645.29" switch \initial - attribute \src "libresoc.v:50542.9-50542.17" + attribute \src "libresoc.v:50645.9-50645.17" case 1'1 case end @@ -89054,21 +89310,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3159 1'0 + assign $1\rst_l_s_rst$next[0:0]$3175 1'0 case - assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd + assign $1\rst_l_s_rst$next[0:0]$3175 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174 end - attribute \src "libresoc.v:50550.3-50558.6" - process $proc$libresoc.v:50550$3160 + attribute \src "libresoc.v:50653.3-50661.6" + process $proc$libresoc.v:50653$3176 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50551.5-50551.29" + assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178 + attribute \src "libresoc.v:50654.5-50654.29" switch \initial - attribute \src "libresoc.v:50551.9-50551.17" + attribute \src "libresoc.v:50654.9-50654.17" case 1'1 case end @@ -89077,21 +89333,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3162 1'1 + assign $1\rst_l_r_rst$next[0:0]$3178 1'1 case - assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r + assign $1\rst_l_r_rst$next[0:0]$3178 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177 end - attribute \src "libresoc.v:50559.3-50567.6" - process $proc$libresoc.v:50559$3163 + attribute \src "libresoc.v:50662.3-50670.6" + process $proc$libresoc.v:50662$3179 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50560.5-50560.29" + assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181 + attribute \src "libresoc.v:50663.5-50663.29" switch \initial - attribute \src "libresoc.v:50560.9-50560.17" + attribute \src "libresoc.v:50663.9-50663.17" case 1'1 case end @@ -89100,21 +89356,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3165 1'0 + assign $1\opc_l_s_opc$next[0:0]$3181 1'0 case - assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$3181 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180 end - attribute \src "libresoc.v:50568.3-50576.6" - process $proc$libresoc.v:50568$3166 + attribute \src "libresoc.v:50671.3-50679.6" + process $proc$libresoc.v:50671$3182 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50569.5-50569.29" + assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184 + attribute \src "libresoc.v:50672.5-50672.29" switch \initial - attribute \src "libresoc.v:50569.9-50569.17" + attribute \src "libresoc.v:50672.9-50672.17" case 1'1 case end @@ -89123,21 +89379,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3168 1'1 + assign $1\opc_l_r_opc$next[0:0]$3184 1'1 case - assign $1\opc_l_r_opc$next[0:0]$3168 \req_done + assign $1\opc_l_r_opc$next[0:0]$3184 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183 end - attribute \src "libresoc.v:50577.3-50585.6" - process $proc$libresoc.v:50577$3169 + attribute \src "libresoc.v:50680.3-50688.6" + process $proc$libresoc.v:50680$3185 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50578.5-50578.29" + assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187 + attribute \src "libresoc.v:50681.5-50681.29" switch \initial - attribute \src "libresoc.v:50578.9-50578.17" + attribute \src "libresoc.v:50681.9-50681.17" case 1'1 case end @@ -89146,21 +89402,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$3171 6'000000 + assign $1\src_l_s_src$next[5:0]$3187 6'000000 case - assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$3187 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186 end - attribute \src "libresoc.v:50586.3-50594.6" - process $proc$libresoc.v:50586$3172 + attribute \src "libresoc.v:50689.3-50697.6" + process $proc$libresoc.v:50689$3188 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50587.5-50587.29" + assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190 + attribute \src "libresoc.v:50690.5-50690.29" switch \initial - attribute \src "libresoc.v:50587.9-50587.17" + attribute \src "libresoc.v:50690.9-50690.17" case 1'1 case end @@ -89169,21 +89425,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$3174 6'111111 + assign $1\src_l_r_src$next[5:0]$3190 6'111111 case - assign $1\src_l_r_src$next[5:0]$3174 \reset_r + assign $1\src_l_r_src$next[5:0]$3190 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189 end - attribute \src "libresoc.v:50595.3-50603.6" - process $proc$libresoc.v:50595$3175 + attribute \src "libresoc.v:50698.3-50706.6" + process $proc$libresoc.v:50698$3191 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50596.5-50596.29" + assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193 + attribute \src "libresoc.v:50699.5-50699.29" switch \initial - attribute \src "libresoc.v:50596.9-50596.17" + attribute \src "libresoc.v:50699.9-50699.17" case 1'1 case end @@ -89192,21 +89448,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$3177 3'000 + assign $1\req_l_s_req$next[2:0]$3193 3'000 case - assign $1\req_l_s_req$next[2:0]$3177 \$67 + assign $1\req_l_s_req$next[2:0]$3193 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192 end - attribute \src "libresoc.v:50604.3-50612.6" - process $proc$libresoc.v:50604$3178 + attribute \src "libresoc.v:50707.3-50715.6" + process $proc$libresoc.v:50707$3194 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50605.5-50605.29" + assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196 + attribute \src "libresoc.v:50708.5-50708.29" switch \initial - attribute \src "libresoc.v:50605.9-50605.17" + attribute \src "libresoc.v:50708.9-50708.17" case 1'1 case end @@ -89215,27 +89471,27 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$3180 3'111 + assign $1\req_l_r_req$next[2:0]$3196 3'111 case - assign $1\req_l_r_req$next[2:0]$3180 \$69 + assign $1\req_l_r_req$next[2:0]$3196 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195 end - attribute \src "libresoc.v:50613.3-50624.6" - process $proc$libresoc.v:50613$3181 + attribute \src "libresoc.v:50716.3-50727.6" + process $proc$libresoc.v:50716$3197 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50614.5-50614.29" + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50717.5-50717.29" switch \initial - attribute \src "libresoc.v:50614.9-50614.17" + attribute \src "libresoc.v:50717.9-50717.17" case 1'1 case end @@ -89246,31 +89502,31 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3202 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3202 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 end - attribute \src "libresoc.v:50625.3-50646.6" - process $proc$libresoc.v:50625$3188 + attribute \src "libresoc.v:50728.3-50749.6" + process $proc$libresoc.v:50728$3204 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 + assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50626.5-50626.29" + assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211 + attribute \src "libresoc.v:50729.5-50729.29" switch \initial - attribute \src "libresoc.v:50626.9-50626.17" + attribute \src "libresoc.v:50729.9-50729.17" case 1'1 case end @@ -89280,10 +89536,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } + assign { $1\data_r0__o_ok$next[0:0]$3208 $1\data_r0__o$next[63:0]$3207 } { \o_ok \alu_cr0_o } case - assign $1\data_r0__o$next[63:0]$3191 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$3207 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3208 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89291,38 +89547,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$3210 $2\data_r0__o$next[63:0]$3209 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 - assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 + assign $2\data_r0__o$next[63:0]$3209 $1\data_r0__o$next[63:0]$3207 + assign $2\data_r0__o_ok$next[0:0]$3210 $1\data_r0__o_ok$next[0:0]$3208 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3195 1'0 + assign $3\data_r0__o_ok$next[0:0]$3211 1'0 case - assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 + assign $3\data_r0__o_ok$next[0:0]$3211 $2\data_r0__o_ok$next[0:0]$3210 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 + update \data_r0__o$next $0\data_r0__o$next[63:0]$3205 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50647.3-50668.6" - process $proc$libresoc.v:50647$3196 + attribute \src "libresoc.v:50750.3-50771.6" + process $proc$libresoc.v:50750$3212 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 + assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217 assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50648.5-50648.29" + assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219 + attribute \src "libresoc.v:50751.5-50751.29" switch \initial - attribute \src "libresoc.v:50648.9-50648.17" + attribute \src "libresoc.v:50751.9-50751.17" case 1'1 case end @@ -89332,10 +89588,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } + assign { $1\data_r1__full_cr_ok$next[0:0]$3216 $1\data_r1__full_cr$next[31:0]$3215 } { \full_cr_ok \alu_cr0_full_cr } case - assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok + assign $1\data_r1__full_cr$next[31:0]$3215 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3216 \data_r1__full_cr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89343,38 +89599,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 + assign { $2\data_r1__full_cr_ok$next[0:0]$3218 $2\data_r1__full_cr$next[31:0]$3217 } 33'000000000000000000000000000000000 case - assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 - assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 + assign $2\data_r1__full_cr$next[31:0]$3217 $1\data_r1__full_cr$next[31:0]$3215 + assign $2\data_r1__full_cr_ok$next[0:0]$3218 $1\data_r1__full_cr_ok$next[0:0]$3216 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 + assign $3\data_r1__full_cr_ok$next[0:0]$3219 1'0 case - assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 + assign $3\data_r1__full_cr_ok$next[0:0]$3219 $2\data_r1__full_cr_ok$next[0:0]$3218 end sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214 end - attribute \src "libresoc.v:50669.3-50690.6" - process $proc$libresoc.v:50669$3204 + attribute \src "libresoc.v:50772.3-50793.6" + process $proc$libresoc.v:50772$3220 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 + assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225 assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50670.5-50670.29" + assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227 + attribute \src "libresoc.v:50773.5-50773.29" switch \initial - attribute \src "libresoc.v:50670.9-50670.17" + attribute \src "libresoc.v:50773.9-50773.17" case 1'1 case end @@ -89384,10 +89640,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } + assign { $1\data_r2__cr_a_ok$next[0:0]$3224 $1\data_r2__cr_a$next[3:0]$3223 } { \cr_a_ok \alu_cr0_cr_a } case - assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok + assign $1\data_r2__cr_a$next[3:0]$3223 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3224 \data_r2__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89395,32 +89651,32 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 + assign { $2\data_r2__cr_a_ok$next[0:0]$3226 $2\data_r2__cr_a$next[3:0]$3225 } 5'00000 case - assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 - assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 + assign $2\data_r2__cr_a$next[3:0]$3225 $1\data_r2__cr_a$next[3:0]$3223 + assign $2\data_r2__cr_a_ok$next[0:0]$3226 $1\data_r2__cr_a_ok$next[0:0]$3224 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 + assign $3\data_r2__cr_a_ok$next[0:0]$3227 1'0 case - assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 + assign $3\data_r2__cr_a_ok$next[0:0]$3227 $2\data_r2__cr_a_ok$next[0:0]$3226 end sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222 end - attribute \src "libresoc.v:50691.3-50700.6" - process $proc$libresoc.v:50691$3212 + attribute \src "libresoc.v:50794.3-50803.6" + process $proc$libresoc.v:50794$3228 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50692.5-50692.29" + assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230 + attribute \src "libresoc.v:50795.5-50795.29" switch \initial - attribute \src "libresoc.v:50692.9-50692.17" + attribute \src "libresoc.v:50795.9-50795.17" case 1'1 case end @@ -89429,21 +89685,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$3214 \src1_i + assign $1\src_r0$next[63:0]$3230 \src1_i case - assign $1\src_r0$next[63:0]$3214 \src_r0 + assign $1\src_r0$next[63:0]$3230 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$3213 + update \src_r0$next $0\src_r0$next[63:0]$3229 end - attribute \src "libresoc.v:50701.3-50710.6" - process $proc$libresoc.v:50701$3215 + attribute \src "libresoc.v:50804.3-50813.6" + process $proc$libresoc.v:50804$3231 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50702.5-50702.29" + assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233 + attribute \src "libresoc.v:50805.5-50805.29" switch \initial - attribute \src "libresoc.v:50702.9-50702.17" + attribute \src "libresoc.v:50805.9-50805.17" case 1'1 case end @@ -89452,21 +89708,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$3217 \src2_i + assign $1\src_r1$next[63:0]$3233 \src2_i case - assign $1\src_r1$next[63:0]$3217 \src_r1 + assign $1\src_r1$next[63:0]$3233 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$3216 + update \src_r1$next $0\src_r1$next[63:0]$3232 end - attribute \src "libresoc.v:50711.3-50720.6" - process $proc$libresoc.v:50711$3218 + attribute \src "libresoc.v:50814.3-50823.6" + process $proc$libresoc.v:50814$3234 assign { } { } assign { } { } - assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50712.5-50712.29" + assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236 + attribute \src "libresoc.v:50815.5-50815.29" switch \initial - attribute \src "libresoc.v:50712.9-50712.17" + attribute \src "libresoc.v:50815.9-50815.17" case 1'1 case end @@ -89475,21 +89731,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[31:0]$3220 \src3_i + assign $1\src_r2$next[31:0]$3236 \src3_i case - assign $1\src_r2$next[31:0]$3220 \src_r2 + assign $1\src_r2$next[31:0]$3236 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[31:0]$3219 + update \src_r2$next $0\src_r2$next[31:0]$3235 end - attribute \src "libresoc.v:50721.3-50730.6" - process $proc$libresoc.v:50721$3221 + attribute \src "libresoc.v:50824.3-50833.6" + process $proc$libresoc.v:50824$3237 assign { } { } assign { } { } - assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50722.5-50722.29" + assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239 + attribute \src "libresoc.v:50825.5-50825.29" switch \initial - attribute \src "libresoc.v:50722.9-50722.17" + attribute \src "libresoc.v:50825.9-50825.17" case 1'1 case end @@ -89498,21 +89754,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[3:0]$3223 \src4_i + assign $1\src_r3$next[3:0]$3239 \src4_i case - assign $1\src_r3$next[3:0]$3223 \src_r3 + assign $1\src_r3$next[3:0]$3239 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[3:0]$3222 + update \src_r3$next $0\src_r3$next[3:0]$3238 end - attribute \src "libresoc.v:50731.3-50740.6" - process $proc$libresoc.v:50731$3224 + attribute \src "libresoc.v:50834.3-50843.6" + process $proc$libresoc.v:50834$3240 assign { } { } assign { } { } - assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50732.5-50732.29" + assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242 + attribute \src "libresoc.v:50835.5-50835.29" switch \initial - attribute \src "libresoc.v:50732.9-50732.17" + attribute \src "libresoc.v:50835.9-50835.17" case 1'1 case end @@ -89521,21 +89777,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[3:0]$3226 \src5_i + assign $1\src_r4$next[3:0]$3242 \src5_i case - assign $1\src_r4$next[3:0]$3226 \src_r4 + assign $1\src_r4$next[3:0]$3242 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[3:0]$3225 + update \src_r4$next $0\src_r4$next[3:0]$3241 end - attribute \src "libresoc.v:50741.3-50750.6" - process $proc$libresoc.v:50741$3227 + attribute \src "libresoc.v:50844.3-50853.6" + process $proc$libresoc.v:50844$3243 assign { } { } assign { } { } - assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50742.5-50742.29" + assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245 + attribute \src "libresoc.v:50845.5-50845.29" switch \initial - attribute \src "libresoc.v:50742.9-50742.17" + attribute \src "libresoc.v:50845.9-50845.17" case 1'1 case end @@ -89544,21 +89800,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[3:0]$3229 \src6_i + assign $1\src_r5$next[3:0]$3245 \src6_i case - assign $1\src_r5$next[3:0]$3229 \src_r5 + assign $1\src_r5$next[3:0]$3245 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[3:0]$3228 + update \src_r5$next $0\src_r5$next[3:0]$3244 end - attribute \src "libresoc.v:50751.3-50759.6" - process $proc$libresoc.v:50751$3230 + attribute \src "libresoc.v:50854.3-50862.6" + process $proc$libresoc.v:50854$3246 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50752.5-50752.29" + assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50855.5-50855.29" switch \initial - attribute \src "libresoc.v:50752.9-50752.17" + attribute \src "libresoc.v:50855.9-50855.17" case 1'1 case end @@ -89567,21 +89823,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3232 1'1 + assign $1\alui_l_r_alui$next[0:0]$3248 1'1 case - assign $1\alui_l_r_alui$next[0:0]$3232 \$89 + assign $1\alui_l_r_alui$next[0:0]$3248 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247 end - attribute \src "libresoc.v:50760.3-50768.6" - process $proc$libresoc.v:50760$3233 + attribute \src "libresoc.v:50863.3-50871.6" + process $proc$libresoc.v:50863$3249 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50761.5-50761.29" + assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50864.5-50864.29" switch \initial - attribute \src "libresoc.v:50761.9-50761.17" + attribute \src "libresoc.v:50864.9-50864.17" case 1'1 case end @@ -89590,21 +89846,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3235 1'1 + assign $1\alu_l_r_alu$next[0:0]$3251 1'1 case - assign $1\alu_l_r_alu$next[0:0]$3235 \$91 + assign $1\alu_l_r_alu$next[0:0]$3251 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250 end - attribute \src "libresoc.v:50769.3-50778.6" - process $proc$libresoc.v:50769$3236 + attribute \src "libresoc.v:50872.3-50881.6" + process $proc$libresoc.v:50872$3252 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50770.5-50770.29" + attribute \src "libresoc.v:50873.5-50873.29" switch \initial - attribute \src "libresoc.v:50770.9-50770.17" + attribute \src "libresoc.v:50873.9-50873.17" case 1'1 case end @@ -89620,14 +89876,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50779.3-50788.6" - process $proc$libresoc.v:50779$3237 + attribute \src "libresoc.v:50882.3-50891.6" + process $proc$libresoc.v:50882$3253 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50780.5-50780.29" + attribute \src "libresoc.v:50883.5-50883.29" switch \initial - attribute \src "libresoc.v:50780.9-50780.17" + attribute \src "libresoc.v:50883.9-50883.17" case 1'1 case end @@ -89643,14 +89899,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50789.3-50798.6" - process $proc$libresoc.v:50789$3238 + attribute \src "libresoc.v:50892.3-50901.6" + process $proc$libresoc.v:50892$3254 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50790.5-50790.29" + attribute \src "libresoc.v:50893.5-50893.29" switch \initial - attribute \src "libresoc.v:50790.9-50790.17" + attribute \src "libresoc.v:50893.9-50893.17" case 1'1 case end @@ -89666,14 +89922,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50799.3-50807.6" - process $proc$libresoc.v:50799$3239 + attribute \src "libresoc.v:50902.3-50910.6" + process $proc$libresoc.v:50902$3255 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50800.5-50800.29" + assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257 + attribute \src "libresoc.v:50903.5-50903.29" switch \initial - attribute \src "libresoc.v:50800.9-50800.17" + attribute \src "libresoc.v:50903.9-50903.17" case 1'1 case end @@ -89682,70 +89938,70 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$3241 3'000 - case - assign $1\prev_wr_go$next[2:0]$3241 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 - end - connect \$5 $reduce_and$libresoc.v:50325$3063_Y - connect \$99 $and$libresoc.v:50326$3064_Y - connect \$101 $and$libresoc.v:50327$3065_Y - connect \$103 $and$libresoc.v:50328$3066_Y - connect \$105 $and$libresoc.v:50329$3067_Y - connect \$107 $and$libresoc.v:50330$3068_Y - connect \$109 $and$libresoc.v:50331$3069_Y - connect \$111 $and$libresoc.v:50332$3070_Y - connect \$113 $and$libresoc.v:50333$3071_Y - connect \$115 $and$libresoc.v:50334$3072_Y - connect \$11 $and$libresoc.v:50335$3073_Y - connect \$13 $not$libresoc.v:50336$3074_Y - connect \$15 $and$libresoc.v:50337$3075_Y - connect \$17 $not$libresoc.v:50338$3076_Y - connect \$19 $and$libresoc.v:50339$3077_Y - connect \$21 $and$libresoc.v:50340$3078_Y - connect \$25 $not$libresoc.v:50341$3079_Y - connect \$27 $and$libresoc.v:50342$3080_Y - connect \$24 $reduce_or$libresoc.v:50343$3081_Y - connect \$23 $not$libresoc.v:50344$3082_Y - connect \$31 $and$libresoc.v:50345$3083_Y - connect \$33 $reduce_or$libresoc.v:50346$3084_Y - connect \$35 $reduce_or$libresoc.v:50347$3085_Y - connect \$37 $or$libresoc.v:50348$3086_Y - connect \$3 $and$libresoc.v:50349$3087_Y - connect \$39 $not$libresoc.v:50350$3088_Y - connect \$41 $and$libresoc.v:50351$3089_Y - connect \$43 $and$libresoc.v:50352$3090_Y - connect \$45 $eq$libresoc.v:50353$3091_Y - connect \$47 $and$libresoc.v:50354$3092_Y - connect \$49 $eq$libresoc.v:50355$3093_Y - connect \$51 $and$libresoc.v:50356$3094_Y - connect \$53 $and$libresoc.v:50357$3095_Y - connect \$55 $and$libresoc.v:50358$3096_Y - connect \$57 $or$libresoc.v:50359$3097_Y - connect \$59 $or$libresoc.v:50360$3098_Y - connect \$61 $or$libresoc.v:50361$3099_Y - connect \$63 $or$libresoc.v:50362$3100_Y - connect \$65 $and$libresoc.v:50363$3101_Y - connect \$67 $and$libresoc.v:50364$3102_Y - connect \$6 $not$libresoc.v:50365$3103_Y - connect \$69 $or$libresoc.v:50366$3104_Y - connect \$71 $and$libresoc.v:50367$3105_Y - connect \$73 $and$libresoc.v:50368$3106_Y - connect \$75 $and$libresoc.v:50369$3107_Y - connect \$77 $ternary$libresoc.v:50370$3108_Y - connect \$79 $ternary$libresoc.v:50371$3109_Y - connect \$81 $ternary$libresoc.v:50372$3110_Y - connect \$83 $ternary$libresoc.v:50373$3111_Y - connect \$85 $ternary$libresoc.v:50374$3112_Y - connect \$87 $ternary$libresoc.v:50375$3113_Y - connect \$8 $or$libresoc.v:50376$3114_Y - connect \$89 $and$libresoc.v:50377$3115_Y - connect \$91 $and$libresoc.v:50378$3116_Y - connect \$93 $and$libresoc.v:50379$3117_Y - connect \$95 $and$libresoc.v:50380$3118_Y - connect \$97 $not$libresoc.v:50381$3119_Y + assign $1\prev_wr_go$next[2:0]$3257 3'000 + case + assign $1\prev_wr_go$next[2:0]$3257 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256 + end + connect \$5 $reduce_and$libresoc.v:50428$3079_Y + connect \$99 $and$libresoc.v:50429$3080_Y + connect \$101 $and$libresoc.v:50430$3081_Y + connect \$103 $and$libresoc.v:50431$3082_Y + connect \$105 $and$libresoc.v:50432$3083_Y + connect \$107 $and$libresoc.v:50433$3084_Y + connect \$109 $and$libresoc.v:50434$3085_Y + connect \$111 $and$libresoc.v:50435$3086_Y + connect \$113 $and$libresoc.v:50436$3087_Y + connect \$115 $and$libresoc.v:50437$3088_Y + connect \$11 $and$libresoc.v:50438$3089_Y + connect \$13 $not$libresoc.v:50439$3090_Y + connect \$15 $and$libresoc.v:50440$3091_Y + connect \$17 $not$libresoc.v:50441$3092_Y + connect \$19 $and$libresoc.v:50442$3093_Y + connect \$21 $and$libresoc.v:50443$3094_Y + connect \$25 $not$libresoc.v:50444$3095_Y + connect \$27 $and$libresoc.v:50445$3096_Y + connect \$24 $reduce_or$libresoc.v:50446$3097_Y + connect \$23 $not$libresoc.v:50447$3098_Y + connect \$31 $and$libresoc.v:50448$3099_Y + connect \$33 $reduce_or$libresoc.v:50449$3100_Y + connect \$35 $reduce_or$libresoc.v:50450$3101_Y + connect \$37 $or$libresoc.v:50451$3102_Y + connect \$3 $and$libresoc.v:50452$3103_Y + connect \$39 $not$libresoc.v:50453$3104_Y + connect \$41 $and$libresoc.v:50454$3105_Y + connect \$43 $and$libresoc.v:50455$3106_Y + connect \$45 $eq$libresoc.v:50456$3107_Y + connect \$47 $and$libresoc.v:50457$3108_Y + connect \$49 $eq$libresoc.v:50458$3109_Y + connect \$51 $and$libresoc.v:50459$3110_Y + connect \$53 $and$libresoc.v:50460$3111_Y + connect \$55 $and$libresoc.v:50461$3112_Y + connect \$57 $or$libresoc.v:50462$3113_Y + connect \$59 $or$libresoc.v:50463$3114_Y + connect \$61 $or$libresoc.v:50464$3115_Y + connect \$63 $or$libresoc.v:50465$3116_Y + connect \$65 $and$libresoc.v:50466$3117_Y + connect \$67 $and$libresoc.v:50467$3118_Y + connect \$6 $not$libresoc.v:50468$3119_Y + connect \$69 $or$libresoc.v:50469$3120_Y + connect \$71 $and$libresoc.v:50470$3121_Y + connect \$73 $and$libresoc.v:50471$3122_Y + connect \$75 $and$libresoc.v:50472$3123_Y + connect \$77 $ternary$libresoc.v:50473$3124_Y + connect \$79 $ternary$libresoc.v:50474$3125_Y + connect \$81 $ternary$libresoc.v:50475$3126_Y + connect \$83 $ternary$libresoc.v:50476$3127_Y + connect \$85 $ternary$libresoc.v:50477$3128_Y + connect \$87 $ternary$libresoc.v:50478$3129_Y + connect \$8 $or$libresoc.v:50479$3130_Y + connect \$89 $and$libresoc.v:50480$3131_Y + connect \$91 $and$libresoc.v:50481$3132_Y + connect \$93 $and$libresoc.v:50482$3133_Y + connect \$95 $and$libresoc.v:50483$3134_Y + connect \$97 $not$libresoc.v:50484$3135_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89778,31 +90034,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50843.1-50892.10" +attribute \src "libresoc.v:50946.1-50995.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50844.7-50844.20" + attribute \src "libresoc.v:50947.7-50947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50880.3-50888.6" - wire $0\q_int$next[0:0]$3280 - attribute \src "libresoc.v:50878.3-50879.27" + attribute \src "libresoc.v:50983.3-50991.6" + wire $0\q_int$next[0:0]$3296 + attribute \src "libresoc.v:50981.3-50982.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50880.3-50888.6" - wire $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50862.7-50862.19" + attribute \src "libresoc.v:50983.3-50991.6" + wire $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50965.7-50965.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50875.17-50875.96" - wire $and$libresoc.v:50875$3275_Y - attribute \src "libresoc.v:50874.17-50874.92" - wire $not$libresoc.v:50874$3274_Y - attribute \src "libresoc.v:50877.17-50877.92" - wire $not$libresoc.v:50877$3277_Y - attribute \src "libresoc.v:50873.17-50873.98" - wire $or$libresoc.v:50873$3273_Y - attribute \src "libresoc.v:50876.17-50876.97" - wire $or$libresoc.v:50876$3276_Y + attribute \src "libresoc.v:50978.17-50978.96" + wire $and$libresoc.v:50978$3291_Y + attribute \src "libresoc.v:50977.17-50977.92" + wire $not$libresoc.v:50977$3290_Y + attribute \src "libresoc.v:50980.17-50980.92" + wire $not$libresoc.v:50980$3293_Y + attribute \src "libresoc.v:50976.17-50976.98" + wire $or$libresoc.v:50976$3289_Y + attribute \src "libresoc.v:50979.17-50979.97" + wire $or$libresoc.v:50979$3292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -89813,11 +90069,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:50844.7-50844.15" + attribute \src "libresoc.v:50947.7-50947.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -89834,7 +90090,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50875$3275 + cell $and $and$libresoc.v:50978$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89842,26 +90098,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50875$3275_Y + connect \Y $and$libresoc.v:50978$3291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50874$3274 + cell $not $not$libresoc.v:50977$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50874$3274_Y + connect \Y $not$libresoc.v:50977$3290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50877$3277 + cell $not $not$libresoc.v:50980$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50877$3277_Y + connect \Y $not$libresoc.v:50980$3293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50873$3273 + cell $or $or$libresoc.v:50976$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89869,10 +90125,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50873$3273_Y + connect \Y $or$libresoc.v:50976$3289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50876$3276 + cell $or $or$libresoc.v:50979$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89880,39 +90136,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50876$3276_Y + connect \Y $or$libresoc.v:50979$3292_Y end - attribute \src "libresoc.v:50844.7-50844.20" - process $proc$libresoc.v:50844$3282 + attribute \src "libresoc.v:50947.7-50947.20" + process $proc$libresoc.v:50947$3298 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50862.7-50862.19" - process $proc$libresoc.v:50862$3283 + attribute \src "libresoc.v:50965.7-50965.19" + process $proc$libresoc.v:50965$3299 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50878.3-50879.27" - process $proc$libresoc.v:50878$3278 + attribute \src "libresoc.v:50981.3-50982.27" + process $proc$libresoc.v:50981$3294 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50880.3-50888.6" - process $proc$libresoc.v:50880$3279 + attribute \src "libresoc.v:50983.3-50991.6" + process $proc$libresoc.v:50983$3295 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50881.5-50881.29" + assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50984.5-50984.29" switch \initial - attribute \src "libresoc.v:50881.9-50881.17" + attribute \src "libresoc.v:50984.9-50984.17" case 1'1 case end @@ -89921,331 +90177,331 @@ module \cyc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$3281 1'0 + assign $1\q_int$next[0:0]$3297 1'0 case - assign $1\q_int$next[0:0]$3281 \$5 + assign $1\q_int$next[0:0]$3297 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$3280 + update \q_int$next $0\q_int$next[0:0]$3296 end - connect \$9 $or$libresoc.v:50873$3273_Y - connect \$1 $not$libresoc.v:50874$3274_Y - connect \$3 $and$libresoc.v:50875$3275_Y - connect \$5 $or$libresoc.v:50876$3276_Y - connect \$7 $not$libresoc.v:50877$3277_Y + connect \$9 $or$libresoc.v:50976$3289_Y + connect \$1 $not$libresoc.v:50977$3290_Y + connect \$3 $and$libresoc.v:50978$3291_Y + connect \$5 $or$libresoc.v:50979$3292_Y + connect \$7 $not$libresoc.v:50980$3293_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50896.1-51628.10" +attribute \src "libresoc.v:50999.1-51731.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51441.3-51450.6" + attribute \src "libresoc.v:51544.3-51553.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51248.3-51257.6" + attribute \src "libresoc.v:51351.3-51360.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51451.3-51460.6" + attribute \src "libresoc.v:51554.3-51563.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51230.3-51247.6" + attribute \src "libresoc.v:51333.3-51350.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51461.3-51494.6" + attribute \src "libresoc.v:51564.3-51597.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51432.3-51440.6" - wire $0\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:51208.3-51209.51" + attribute \src "libresoc.v:51535.3-51543.6" + wire $0\dmi_read_log_data$next[0:0]$3414 + attribute \src "libresoc.v:51311.3-51312.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51423.3-51431.6" - wire $0\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:51210.3-51211.55" + attribute \src "libresoc.v:51526.3-51534.6" + wire $0\dmi_read_log_data_1$next[0:0]$3411 + attribute \src "libresoc.v:51313.3-51314.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51258.3-51266.6" - wire $0\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:51220.3-51221.39" + attribute \src "libresoc.v:51361.3-51369.6" + wire $0\dmi_req_i_1$next[0:0]$3377 + attribute \src "libresoc.v:51323.3-51324.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $0\do_dmi_log_rd$next[0:0]$3425 - attribute \src "libresoc.v:51222.3-51223.43" + attribute \src "libresoc.v:51688.3-51721.6" + wire $0\do_dmi_log_rd$next[0:0]$3441 + attribute \src "libresoc.v:51325.3-51326.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51555.3-51584.6" - wire $0\do_icreset$next[0:0]$3418 - attribute \src "libresoc.v:51224.3-51225.37" + attribute \src "libresoc.v:51658.3-51687.6" + wire $0\do_icreset$next[0:0]$3434 + attribute \src "libresoc.v:51327.3-51328.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51525.3-51554.6" - wire $0\do_reset$next[0:0]$3411 - attribute \src "libresoc.v:51226.3-51227.33" + attribute \src "libresoc.v:51628.3-51657.6" + wire $0\do_reset$next[0:0]$3427 + attribute \src "libresoc.v:51329.3-51330.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51495.3-51524.6" - wire $0\do_step$next[0:0]$3404 - attribute \src "libresoc.v:51228.3-51229.31" + attribute \src "libresoc.v:51598.3-51627.6" + wire $0\do_step$next[0:0]$3420 + attribute \src "libresoc.v:51331.3-51332.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $0\gspr_index$next[6:0]$3383 - attribute \src "libresoc.v:51214.3-51215.37" + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $0\gspr_index$next[6:0]$3399 + attribute \src "libresoc.v:51317.3-51318.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50897.7-50897.20" + attribute \src "libresoc.v:51000.7-51000.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3389 - attribute \src "libresoc.v:51212.3-51213.41" + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3405 + attribute \src "libresoc.v:51315.3-51316.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51317.3-51360.6" - wire $0\stopping$next[0:0]$3374 - attribute \src "libresoc.v:51216.3-51217.33" + attribute \src "libresoc.v:51420.3-51463.6" + wire $0\stopping$next[0:0]$3390 + attribute \src "libresoc.v:51319.3-51320.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51267.3-51316.6" - wire $0\terminated$next[0:0]$3364 - attribute \src "libresoc.v:51218.3-51219.37" + attribute \src "libresoc.v:51370.3-51419.6" + wire $0\terminated$next[0:0]$3380 + attribute \src "libresoc.v:51321.3-51322.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51441.3-51450.6" + attribute \src "libresoc.v:51544.3-51553.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51248.3-51257.6" + attribute \src "libresoc.v:51351.3-51360.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51451.3-51460.6" + attribute \src "libresoc.v:51554.3-51563.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51230.3-51247.6" + attribute \src "libresoc.v:51333.3-51350.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51461.3-51494.6" + attribute \src "libresoc.v:51564.3-51597.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51432.3-51440.6" - wire $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51084.7-51084.31" + attribute \src "libresoc.v:51535.3-51543.6" + wire $1\dmi_read_log_data$next[0:0]$3415 + attribute \src "libresoc.v:51187.7-51187.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51423.3-51431.6" - wire $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51088.7-51088.33" + attribute \src "libresoc.v:51526.3-51534.6" + wire $1\dmi_read_log_data_1$next[0:0]$3412 + attribute \src "libresoc.v:51191.7-51191.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51258.3-51266.6" - wire $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51094.7-51094.25" + attribute \src "libresoc.v:51361.3-51369.6" + wire $1\dmi_req_i_1$next[0:0]$3378 + attribute \src "libresoc.v:51197.7-51197.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $1\do_dmi_log_rd$next[0:0]$3426 - attribute \src "libresoc.v:51100.7-51100.27" + attribute \src "libresoc.v:51688.3-51721.6" + wire $1\do_dmi_log_rd$next[0:0]$3442 + attribute \src "libresoc.v:51203.7-51203.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51555.3-51584.6" - wire $1\do_icreset$next[0:0]$3419 - attribute \src "libresoc.v:51104.7-51104.24" + attribute \src "libresoc.v:51658.3-51687.6" + wire $1\do_icreset$next[0:0]$3435 + attribute \src "libresoc.v:51207.7-51207.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51525.3-51554.6" - wire $1\do_reset$next[0:0]$3412 - attribute \src "libresoc.v:51108.7-51108.22" + attribute \src "libresoc.v:51628.3-51657.6" + wire $1\do_reset$next[0:0]$3428 + attribute \src "libresoc.v:51211.7-51211.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51495.3-51524.6" - wire $1\do_step$next[0:0]$3405 - attribute \src "libresoc.v:51112.7-51112.21" + attribute \src "libresoc.v:51598.3-51627.6" + wire $1\do_step$next[0:0]$3421 + attribute \src "libresoc.v:51215.7-51215.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $1\gspr_index$next[6:0]$3384 - attribute \src "libresoc.v:51116.13-51116.31" + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $1\gspr_index$next[6:0]$3400 + attribute \src "libresoc.v:51219.13-51219.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3390 - attribute \src "libresoc.v:51122.14-51122.34" + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3406 + attribute \src "libresoc.v:51225.14-51225.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51317.3-51360.6" - wire $1\stopping$next[0:0]$3375 - attribute \src "libresoc.v:51134.7-51134.22" + attribute \src "libresoc.v:51420.3-51463.6" + wire $1\stopping$next[0:0]$3391 + attribute \src "libresoc.v:51237.7-51237.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51267.3-51316.6" - wire $1\terminated$next[0:0]$3365 - attribute \src "libresoc.v:51140.7-51140.24" + attribute \src "libresoc.v:51370.3-51419.6" + wire $1\terminated$next[0:0]$3381 + attribute \src "libresoc.v:51243.7-51243.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $2\do_dmi_log_rd$next[0:0]$3427 - attribute \src "libresoc.v:51555.3-51584.6" - wire $2\do_icreset$next[0:0]$3420 - attribute \src "libresoc.v:51525.3-51554.6" - wire $2\do_reset$next[0:0]$3413 - attribute \src "libresoc.v:51495.3-51524.6" - wire $2\do_step$next[0:0]$3406 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $2\gspr_index$next[6:0]$3385 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3391 - attribute \src "libresoc.v:51317.3-51360.6" - wire $2\stopping$next[0:0]$3376 - attribute \src "libresoc.v:51267.3-51316.6" - wire $2\terminated$next[0:0]$3366 - attribute \src "libresoc.v:51585.3-51618.6" - wire $3\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:51555.3-51584.6" - wire $3\do_icreset$next[0:0]$3421 - attribute \src "libresoc.v:51525.3-51554.6" - wire $3\do_reset$next[0:0]$3414 - attribute \src "libresoc.v:51495.3-51524.6" - wire $3\do_step$next[0:0]$3407 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $3\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:51317.3-51360.6" - wire $3\stopping$next[0:0]$3377 - attribute \src "libresoc.v:51267.3-51316.6" - wire $3\terminated$next[0:0]$3367 - attribute \src "libresoc.v:51585.3-51618.6" - wire $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51555.3-51584.6" - wire $4\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:51525.3-51554.6" - wire $4\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:51495.3-51524.6" - wire $4\do_step$next[0:0]$3408 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51317.3-51360.6" - wire $4\stopping$next[0:0]$3378 - attribute \src "libresoc.v:51267.3-51316.6" - wire $4\terminated$next[0:0]$3368 - attribute \src "libresoc.v:51555.3-51584.6" - wire $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51525.3-51554.6" - wire $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51495.3-51524.6" - wire $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51317.3-51360.6" - wire $5\stopping$next[0:0]$3379 - attribute \src "libresoc.v:51267.3-51316.6" - wire $5\terminated$next[0:0]$3369 - attribute \src "libresoc.v:51317.3-51360.6" - wire $6\stopping$next[0:0]$3380 - attribute \src "libresoc.v:51267.3-51316.6" - wire $6\terminated$next[0:0]$3370 - attribute \src "libresoc.v:51317.3-51360.6" - wire $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51267.3-51316.6" - wire $7\terminated$next[0:0]$3371 - attribute \src "libresoc.v:51267.3-51316.6" - wire $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51155.19-51155.110" - wire width 3 $add$libresoc.v:51155$3294_Y - attribute \src "libresoc.v:51149.19-51149.103" - wire $and$libresoc.v:51149$3288_Y - attribute \src "libresoc.v:51151.19-51151.113" - wire $and$libresoc.v:51151$3290_Y - attribute \src "libresoc.v:51156.18-51156.110" - wire $and$libresoc.v:51156$3295_Y - attribute \src "libresoc.v:51158.19-51158.103" - wire $and$libresoc.v:51158$3297_Y - attribute \src "libresoc.v:51160.19-51160.102" - wire $and$libresoc.v:51160$3299_Y - attribute \src "libresoc.v:51166.18-51166.101" - wire $and$libresoc.v:51166$3305_Y - attribute \src "libresoc.v:51168.18-51168.111" - wire $and$libresoc.v:51168$3307_Y - attribute \src "libresoc.v:51173.18-51173.101" - wire $and$libresoc.v:51173$3312_Y - attribute \src "libresoc.v:51176.18-51176.111" - wire $and$libresoc.v:51176$3315_Y - attribute \src "libresoc.v:51181.18-51181.101" - wire $and$libresoc.v:51181$3320_Y - attribute \src "libresoc.v:51183.18-51183.111" - wire $and$libresoc.v:51183$3322_Y - attribute \src "libresoc.v:51189.18-51189.101" - wire $and$libresoc.v:51189$3328_Y - attribute \src "libresoc.v:51191.18-51191.111" - wire $and$libresoc.v:51191$3330_Y - attribute \src "libresoc.v:51196.18-51196.101" - wire $and$libresoc.v:51196$3335_Y - attribute \src "libresoc.v:51197.17-51197.99" - wire $and$libresoc.v:51197$3336_Y - attribute \src "libresoc.v:51199.18-51199.111" - wire $and$libresoc.v:51199$3338_Y - attribute \src "libresoc.v:51204.18-51204.101" - wire $and$libresoc.v:51204$3343_Y - attribute \src "libresoc.v:51206.18-51206.111" - wire $and$libresoc.v:51206$3345_Y - attribute \src "libresoc.v:51146.18-51146.103" - wire $eq$libresoc.v:51146$3285_Y - attribute \src "libresoc.v:51147.19-51147.104" - wire $eq$libresoc.v:51147$3286_Y - attribute \src "libresoc.v:51152.19-51152.104" - wire $eq$libresoc.v:51152$3291_Y - attribute \src "libresoc.v:51153.19-51153.104" - wire $eq$libresoc.v:51153$3292_Y - attribute \src "libresoc.v:51154.19-51154.104" - wire $eq$libresoc.v:51154$3293_Y - attribute \src "libresoc.v:51157.19-51157.104" - wire $eq$libresoc.v:51157$3296_Y - attribute \src "libresoc.v:51161.18-51161.103" - wire $eq$libresoc.v:51161$3300_Y - attribute \src "libresoc.v:51162.18-51162.103" - wire $eq$libresoc.v:51162$3301_Y - attribute \src "libresoc.v:51163.18-51163.103" - wire $eq$libresoc.v:51163$3302_Y - attribute \src "libresoc.v:51169.18-51169.103" - wire $eq$libresoc.v:51169$3308_Y - attribute \src "libresoc.v:51170.18-51170.103" - wire $eq$libresoc.v:51170$3309_Y - attribute \src "libresoc.v:51171.18-51171.103" - wire $eq$libresoc.v:51171$3310_Y - attribute \src "libresoc.v:51177.18-51177.103" - wire $eq$libresoc.v:51177$3316_Y - attribute \src "libresoc.v:51178.18-51178.103" - wire $eq$libresoc.v:51178$3317_Y - attribute \src "libresoc.v:51179.18-51179.103" - wire $eq$libresoc.v:51179$3318_Y - attribute \src "libresoc.v:51184.18-51184.103" - wire $eq$libresoc.v:51184$3323_Y - attribute \src "libresoc.v:51185.18-51185.103" - wire $eq$libresoc.v:51185$3324_Y - attribute \src "libresoc.v:51187.18-51187.103" - wire $eq$libresoc.v:51187$3326_Y - attribute \src "libresoc.v:51192.18-51192.103" - wire $eq$libresoc.v:51192$3331_Y - attribute \src "libresoc.v:51193.18-51193.103" - wire $eq$libresoc.v:51193$3332_Y - attribute \src "libresoc.v:51194.18-51194.103" - wire $eq$libresoc.v:51194$3333_Y - attribute \src "libresoc.v:51200.18-51200.103" - wire $eq$libresoc.v:51200$3339_Y - attribute \src "libresoc.v:51201.18-51201.103" - wire $eq$libresoc.v:51201$3340_Y - attribute \src "libresoc.v:51202.18-51202.103" - wire $eq$libresoc.v:51202$3341_Y - attribute \src "libresoc.v:51207.18-51207.103" - wire $eq$libresoc.v:51207$3346_Y - attribute \src "libresoc.v:51145.17-51145.103" - wire $not$libresoc.v:51145$3284_Y - attribute \src "libresoc.v:51148.19-51148.99" - wire $not$libresoc.v:51148$3287_Y - attribute \src "libresoc.v:51150.19-51150.105" - wire $not$libresoc.v:51150$3289_Y - attribute \src "libresoc.v:51159.19-51159.95" - wire $not$libresoc.v:51159$3298_Y - attribute \src "libresoc.v:51165.18-51165.98" - wire $not$libresoc.v:51165$3304_Y - attribute \src "libresoc.v:51167.18-51167.104" - wire $not$libresoc.v:51167$3306_Y - attribute \src "libresoc.v:51172.18-51172.98" - wire $not$libresoc.v:51172$3311_Y - attribute \src "libresoc.v:51174.18-51174.104" - wire $not$libresoc.v:51174$3313_Y - attribute \src "libresoc.v:51180.18-51180.98" - wire $not$libresoc.v:51180$3319_Y - attribute \src "libresoc.v:51182.18-51182.104" - wire $not$libresoc.v:51182$3321_Y - attribute \src "libresoc.v:51186.17-51186.97" - wire $not$libresoc.v:51186$3325_Y - attribute \src "libresoc.v:51188.18-51188.98" - wire $not$libresoc.v:51188$3327_Y - attribute \src "libresoc.v:51190.18-51190.104" - wire $not$libresoc.v:51190$3329_Y - attribute \src "libresoc.v:51195.18-51195.98" - wire $not$libresoc.v:51195$3334_Y - attribute \src "libresoc.v:51198.18-51198.104" - wire $not$libresoc.v:51198$3337_Y - attribute \src "libresoc.v:51203.18-51203.98" - wire $not$libresoc.v:51203$3342_Y - attribute \src "libresoc.v:51205.18-51205.104" - wire $not$libresoc.v:51205$3344_Y - attribute \src "libresoc.v:51164.17-51164.126" - wire width 64 $pos$libresoc.v:51164$3303_Y - attribute \src "libresoc.v:51175.17-51175.245" - wire width 64 $pos$libresoc.v:51175$3314_Y + attribute \src "libresoc.v:51688.3-51721.6" + wire $2\do_dmi_log_rd$next[0:0]$3443 + attribute \src "libresoc.v:51658.3-51687.6" + wire $2\do_icreset$next[0:0]$3436 + attribute \src "libresoc.v:51628.3-51657.6" + wire $2\do_reset$next[0:0]$3429 + attribute \src "libresoc.v:51598.3-51627.6" + wire $2\do_step$next[0:0]$3422 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $2\gspr_index$next[6:0]$3401 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3407 + attribute \src "libresoc.v:51420.3-51463.6" + wire $2\stopping$next[0:0]$3392 + attribute \src "libresoc.v:51370.3-51419.6" + wire $2\terminated$next[0:0]$3382 + attribute \src "libresoc.v:51688.3-51721.6" + wire $3\do_dmi_log_rd$next[0:0]$3444 + attribute \src "libresoc.v:51658.3-51687.6" + wire $3\do_icreset$next[0:0]$3437 + attribute \src "libresoc.v:51628.3-51657.6" + wire $3\do_reset$next[0:0]$3430 + attribute \src "libresoc.v:51598.3-51627.6" + wire $3\do_step$next[0:0]$3423 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $3\gspr_index$next[6:0]$3402 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3408 + attribute \src "libresoc.v:51420.3-51463.6" + wire $3\stopping$next[0:0]$3393 + attribute \src "libresoc.v:51370.3-51419.6" + wire $3\terminated$next[0:0]$3383 + attribute \src "libresoc.v:51688.3-51721.6" + wire $4\do_dmi_log_rd$next[0:0]$3445 + attribute \src "libresoc.v:51658.3-51687.6" + wire $4\do_icreset$next[0:0]$3438 + attribute \src "libresoc.v:51628.3-51657.6" + wire $4\do_reset$next[0:0]$3431 + attribute \src "libresoc.v:51598.3-51627.6" + wire $4\do_step$next[0:0]$3424 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $4\gspr_index$next[6:0]$3403 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3409 + attribute \src "libresoc.v:51420.3-51463.6" + wire $4\stopping$next[0:0]$3394 + attribute \src "libresoc.v:51370.3-51419.6" + wire $4\terminated$next[0:0]$3384 + attribute \src "libresoc.v:51658.3-51687.6" + wire $5\do_icreset$next[0:0]$3439 + attribute \src "libresoc.v:51628.3-51657.6" + wire $5\do_reset$next[0:0]$3432 + attribute \src "libresoc.v:51598.3-51627.6" + wire $5\do_step$next[0:0]$3425 + attribute \src "libresoc.v:51420.3-51463.6" + wire $5\stopping$next[0:0]$3395 + attribute \src "libresoc.v:51370.3-51419.6" + wire $5\terminated$next[0:0]$3385 + attribute \src "libresoc.v:51420.3-51463.6" + wire $6\stopping$next[0:0]$3396 + attribute \src "libresoc.v:51370.3-51419.6" + wire $6\terminated$next[0:0]$3386 + attribute \src "libresoc.v:51420.3-51463.6" + wire $7\stopping$next[0:0]$3397 + attribute \src "libresoc.v:51370.3-51419.6" + wire $7\terminated$next[0:0]$3387 + attribute \src "libresoc.v:51370.3-51419.6" + wire $8\terminated$next[0:0]$3388 + attribute \src "libresoc.v:51258.19-51258.110" + wire width 3 $add$libresoc.v:51258$3310_Y + attribute \src "libresoc.v:51252.19-51252.103" + wire $and$libresoc.v:51252$3304_Y + attribute \src "libresoc.v:51254.19-51254.113" + wire $and$libresoc.v:51254$3306_Y + attribute \src "libresoc.v:51259.18-51259.110" + wire $and$libresoc.v:51259$3311_Y + attribute \src "libresoc.v:51261.19-51261.103" + wire $and$libresoc.v:51261$3313_Y + attribute \src "libresoc.v:51263.19-51263.102" + wire $and$libresoc.v:51263$3315_Y + attribute \src "libresoc.v:51269.18-51269.101" + wire $and$libresoc.v:51269$3321_Y + attribute \src "libresoc.v:51271.18-51271.111" + wire $and$libresoc.v:51271$3323_Y + attribute \src "libresoc.v:51276.18-51276.101" + wire $and$libresoc.v:51276$3328_Y + attribute \src "libresoc.v:51279.18-51279.111" + wire $and$libresoc.v:51279$3331_Y + attribute \src "libresoc.v:51284.18-51284.101" + wire $and$libresoc.v:51284$3336_Y + attribute \src "libresoc.v:51286.18-51286.111" + wire $and$libresoc.v:51286$3338_Y + attribute \src "libresoc.v:51292.18-51292.101" + wire $and$libresoc.v:51292$3344_Y + attribute \src "libresoc.v:51294.18-51294.111" + wire $and$libresoc.v:51294$3346_Y + attribute \src "libresoc.v:51299.18-51299.101" + wire $and$libresoc.v:51299$3351_Y + attribute \src "libresoc.v:51300.17-51300.99" + wire $and$libresoc.v:51300$3352_Y + attribute \src "libresoc.v:51302.18-51302.111" + wire $and$libresoc.v:51302$3354_Y + attribute \src "libresoc.v:51307.18-51307.101" + wire $and$libresoc.v:51307$3359_Y + attribute \src "libresoc.v:51309.18-51309.111" + wire $and$libresoc.v:51309$3361_Y + attribute \src "libresoc.v:51249.18-51249.103" + wire $eq$libresoc.v:51249$3301_Y + attribute \src "libresoc.v:51250.19-51250.104" + wire $eq$libresoc.v:51250$3302_Y + attribute \src "libresoc.v:51255.19-51255.104" + wire $eq$libresoc.v:51255$3307_Y + attribute \src "libresoc.v:51256.19-51256.104" + wire $eq$libresoc.v:51256$3308_Y + attribute \src "libresoc.v:51257.19-51257.104" + wire $eq$libresoc.v:51257$3309_Y + attribute \src "libresoc.v:51260.19-51260.104" + wire $eq$libresoc.v:51260$3312_Y + attribute \src "libresoc.v:51264.18-51264.103" + wire $eq$libresoc.v:51264$3316_Y + attribute \src "libresoc.v:51265.18-51265.103" + wire $eq$libresoc.v:51265$3317_Y + attribute \src "libresoc.v:51266.18-51266.103" + wire $eq$libresoc.v:51266$3318_Y + attribute \src "libresoc.v:51272.18-51272.103" + wire $eq$libresoc.v:51272$3324_Y + attribute \src "libresoc.v:51273.18-51273.103" + wire $eq$libresoc.v:51273$3325_Y + attribute \src "libresoc.v:51274.18-51274.103" + wire $eq$libresoc.v:51274$3326_Y + attribute \src "libresoc.v:51280.18-51280.103" + wire $eq$libresoc.v:51280$3332_Y + attribute \src "libresoc.v:51281.18-51281.103" + wire $eq$libresoc.v:51281$3333_Y + attribute \src "libresoc.v:51282.18-51282.103" + wire $eq$libresoc.v:51282$3334_Y + attribute \src "libresoc.v:51287.18-51287.103" + wire $eq$libresoc.v:51287$3339_Y + attribute \src "libresoc.v:51288.18-51288.103" + wire $eq$libresoc.v:51288$3340_Y + attribute \src "libresoc.v:51290.18-51290.103" + wire $eq$libresoc.v:51290$3342_Y + attribute \src "libresoc.v:51295.18-51295.103" + wire $eq$libresoc.v:51295$3347_Y + attribute \src "libresoc.v:51296.18-51296.103" + wire $eq$libresoc.v:51296$3348_Y + attribute \src "libresoc.v:51297.18-51297.103" + wire $eq$libresoc.v:51297$3349_Y + attribute \src "libresoc.v:51303.18-51303.103" + wire $eq$libresoc.v:51303$3355_Y + attribute \src "libresoc.v:51304.18-51304.103" + wire $eq$libresoc.v:51304$3356_Y + attribute \src "libresoc.v:51305.18-51305.103" + wire $eq$libresoc.v:51305$3357_Y + attribute \src "libresoc.v:51310.18-51310.103" + wire $eq$libresoc.v:51310$3362_Y + attribute \src "libresoc.v:51248.17-51248.103" + wire $not$libresoc.v:51248$3300_Y + attribute \src "libresoc.v:51251.19-51251.99" + wire $not$libresoc.v:51251$3303_Y + attribute \src "libresoc.v:51253.19-51253.105" + wire $not$libresoc.v:51253$3305_Y + attribute \src "libresoc.v:51262.19-51262.95" + wire $not$libresoc.v:51262$3314_Y + attribute \src "libresoc.v:51268.18-51268.98" + wire $not$libresoc.v:51268$3320_Y + attribute \src "libresoc.v:51270.18-51270.104" + wire $not$libresoc.v:51270$3322_Y + attribute \src "libresoc.v:51275.18-51275.98" + wire $not$libresoc.v:51275$3327_Y + attribute \src "libresoc.v:51277.18-51277.104" + wire $not$libresoc.v:51277$3329_Y + attribute \src "libresoc.v:51283.18-51283.98" + wire $not$libresoc.v:51283$3335_Y + attribute \src "libresoc.v:51285.18-51285.104" + wire $not$libresoc.v:51285$3337_Y + attribute \src "libresoc.v:51289.17-51289.97" + wire $not$libresoc.v:51289$3341_Y + attribute \src "libresoc.v:51291.18-51291.98" + wire $not$libresoc.v:51291$3343_Y + attribute \src "libresoc.v:51293.18-51293.104" + wire $not$libresoc.v:51293$3345_Y + attribute \src "libresoc.v:51298.18-51298.98" + wire $not$libresoc.v:51298$3350_Y + attribute \src "libresoc.v:51301.18-51301.104" + wire $not$libresoc.v:51301$3353_Y + attribute \src "libresoc.v:51306.18-51306.98" + wire $not$libresoc.v:51306$3358_Y + attribute \src "libresoc.v:51308.18-51308.104" + wire $not$libresoc.v:51308$3360_Y + attribute \src "libresoc.v:51267.17-51267.126" + wire width 64 $pos$libresoc.v:51267$3319_Y + attribute \src "libresoc.v:51278.17-51278.245" + wire width 64 $pos$libresoc.v:51278$3330_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90374,7 +90630,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90464,7 +90720,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:50897.7-50897.15" + attribute \src "libresoc.v:51000.7-51000.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90474,7 +90730,7 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg @@ -90491,7 +90747,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:51155$3294 + cell $add $add$libresoc.v:51258$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90499,10 +90755,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51155$3294_Y + connect \Y $add$libresoc.v:51258$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51149$3288 + cell $and $and$libresoc.v:51252$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90510,10 +90766,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:51149$3288_Y + connect \Y $and$libresoc.v:51252$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51151$3290 + cell $and $and$libresoc.v:51254$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90521,10 +90777,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:51151$3290_Y + connect \Y $and$libresoc.v:51254$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51156$3295 + cell $and $and$libresoc.v:51259$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90532,10 +90788,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:51156$3295_Y + connect \Y $and$libresoc.v:51259$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:51158$3297 + cell $and $and$libresoc.v:51261$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90543,10 +90799,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:51158$3297_Y + connect \Y $and$libresoc.v:51261$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:51160$3299 + cell $and $and$libresoc.v:51263$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90554,10 +90810,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:51160$3299_Y + connect \Y $and$libresoc.v:51263$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51166$3305 + cell $and $and$libresoc.v:51269$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90565,10 +90821,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:51166$3305_Y + connect \Y $and$libresoc.v:51269$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51168$3307 + cell $and $and$libresoc.v:51271$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90576,10 +90832,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:51168$3307_Y + connect \Y $and$libresoc.v:51271$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51173$3312 + cell $and $and$libresoc.v:51276$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90587,10 +90843,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:51173$3312_Y + connect \Y $and$libresoc.v:51276$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51176$3315 + cell $and $and$libresoc.v:51279$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90598,10 +90854,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:51176$3315_Y + connect \Y $and$libresoc.v:51279$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51181$3320 + cell $and $and$libresoc.v:51284$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90609,10 +90865,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:51181$3320_Y + connect \Y $and$libresoc.v:51284$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51183$3322 + cell $and $and$libresoc.v:51286$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90620,10 +90876,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:51183$3322_Y + connect \Y $and$libresoc.v:51286$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51189$3328 + cell $and $and$libresoc.v:51292$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90631,10 +90887,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:51189$3328_Y + connect \Y $and$libresoc.v:51292$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51191$3330 + cell $and $and$libresoc.v:51294$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90642,10 +90898,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:51191$3330_Y + connect \Y $and$libresoc.v:51294$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51196$3335 + cell $and $and$libresoc.v:51299$3351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90653,10 +90909,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:51196$3335_Y + connect \Y $and$libresoc.v:51299$3351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51197$3336 + cell $and $and$libresoc.v:51300$3352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90664,10 +90920,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:51197$3336_Y + connect \Y $and$libresoc.v:51300$3352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51199$3338 + cell $and $and$libresoc.v:51302$3354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90675,10 +90931,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:51199$3338_Y + connect \Y $and$libresoc.v:51302$3354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51204$3343 + cell $and $and$libresoc.v:51307$3359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90686,10 +90942,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:51204$3343_Y + connect \Y $and$libresoc.v:51307$3359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51206$3345 + cell $and $and$libresoc.v:51309$3361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90697,10 +90953,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:51206$3345_Y + connect \Y $and$libresoc.v:51309$3361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51146$3285 + cell $eq $eq$libresoc.v:51249$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90708,10 +90964,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51146$3285_Y + connect \Y $eq$libresoc.v:51249$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51147$3286 + cell $eq $eq$libresoc.v:51250$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90719,10 +90975,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51147$3286_Y + connect \Y $eq$libresoc.v:51250$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51152$3291 + cell $eq $eq$libresoc.v:51255$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90730,10 +90986,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51152$3291_Y + connect \Y $eq$libresoc.v:51255$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51153$3292 + cell $eq $eq$libresoc.v:51256$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90741,10 +90997,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51153$3292_Y + connect \Y $eq$libresoc.v:51256$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51154$3293 + cell $eq $eq$libresoc.v:51257$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90752,10 +91008,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51154$3293_Y + connect \Y $eq$libresoc.v:51257$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:51157$3296 + cell $eq $eq$libresoc.v:51260$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90763,10 +91019,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51157$3296_Y + connect \Y $eq$libresoc.v:51260$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51161$3300 + cell $eq $eq$libresoc.v:51264$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90774,10 +91030,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51161$3300_Y + connect \Y $eq$libresoc.v:51264$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51162$3301 + cell $eq $eq$libresoc.v:51265$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90785,10 +91041,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51162$3301_Y + connect \Y $eq$libresoc.v:51265$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51163$3302 + cell $eq $eq$libresoc.v:51266$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90796,10 +91052,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51163$3302_Y + connect \Y $eq$libresoc.v:51266$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51169$3308 + cell $eq $eq$libresoc.v:51272$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90807,10 +91063,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51169$3308_Y + connect \Y $eq$libresoc.v:51272$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51170$3309 + cell $eq $eq$libresoc.v:51273$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90818,10 +91074,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51170$3309_Y + connect \Y $eq$libresoc.v:51273$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51171$3310 + cell $eq $eq$libresoc.v:51274$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90829,10 +91085,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51171$3310_Y + connect \Y $eq$libresoc.v:51274$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51177$3316 + cell $eq $eq$libresoc.v:51280$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90840,10 +91096,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51177$3316_Y + connect \Y $eq$libresoc.v:51280$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51178$3317 + cell $eq $eq$libresoc.v:51281$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90851,10 +91107,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51178$3317_Y + connect \Y $eq$libresoc.v:51281$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51179$3318 + cell $eq $eq$libresoc.v:51282$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90862,10 +91118,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51179$3318_Y + connect \Y $eq$libresoc.v:51282$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51184$3323 + cell $eq $eq$libresoc.v:51287$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90873,10 +91129,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51184$3323_Y + connect \Y $eq$libresoc.v:51287$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51185$3324 + cell $eq $eq$libresoc.v:51288$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90884,10 +91140,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51185$3324_Y + connect \Y $eq$libresoc.v:51288$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51187$3326 + cell $eq $eq$libresoc.v:51290$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90895,10 +91151,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51187$3326_Y + connect \Y $eq$libresoc.v:51290$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51192$3331 + cell $eq $eq$libresoc.v:51295$3347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90906,10 +91162,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51192$3331_Y + connect \Y $eq$libresoc.v:51295$3347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51193$3332 + cell $eq $eq$libresoc.v:51296$3348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90917,10 +91173,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51193$3332_Y + connect \Y $eq$libresoc.v:51296$3348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51194$3333 + cell $eq $eq$libresoc.v:51297$3349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90928,10 +91184,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51194$3333_Y + connect \Y $eq$libresoc.v:51297$3349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51200$3339 + cell $eq $eq$libresoc.v:51303$3355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90939,10 +91195,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51200$3339_Y + connect \Y $eq$libresoc.v:51303$3355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51201$3340 + cell $eq $eq$libresoc.v:51304$3356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90950,10 +91206,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51201$3340_Y + connect \Y $eq$libresoc.v:51304$3356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51202$3341 + cell $eq $eq$libresoc.v:51305$3357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90961,10 +91217,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51202$3341_Y + connect \Y $eq$libresoc.v:51305$3357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51207$3346 + cell $eq $eq$libresoc.v:51310$3362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90972,340 +91228,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51207$3346_Y + connect \Y $eq$libresoc.v:51310$3362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51145$3284 + cell $not $not$libresoc.v:51248$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51145$3284_Y + connect \Y $not$libresoc.v:51248$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51148$3287 + cell $not $not$libresoc.v:51251$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51148$3287_Y + connect \Y $not$libresoc.v:51251$3303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51150$3289 + cell $not $not$libresoc.v:51253$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51150$3289_Y + connect \Y $not$libresoc.v:51253$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:51159$3298 + cell $not $not$libresoc.v:51262$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51159$3298_Y + connect \Y $not$libresoc.v:51262$3314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51165$3304 + cell $not $not$libresoc.v:51268$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51165$3304_Y + connect \Y $not$libresoc.v:51268$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51167$3306 + cell $not $not$libresoc.v:51270$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51167$3306_Y + connect \Y $not$libresoc.v:51270$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51172$3311 + cell $not $not$libresoc.v:51275$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51172$3311_Y + connect \Y $not$libresoc.v:51275$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51174$3313 + cell $not $not$libresoc.v:51277$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51174$3313_Y + connect \Y $not$libresoc.v:51277$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51180$3319 + cell $not $not$libresoc.v:51283$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51180$3319_Y + connect \Y $not$libresoc.v:51283$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51182$3321 + cell $not $not$libresoc.v:51285$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51182$3321_Y + connect \Y $not$libresoc.v:51285$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51186$3325 + cell $not $not$libresoc.v:51289$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51186$3325_Y + connect \Y $not$libresoc.v:51289$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51188$3327 + cell $not $not$libresoc.v:51291$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51188$3327_Y + connect \Y $not$libresoc.v:51291$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51190$3329 + cell $not $not$libresoc.v:51293$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51190$3329_Y + connect \Y $not$libresoc.v:51293$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51195$3334 + cell $not $not$libresoc.v:51298$3350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51195$3334_Y + connect \Y $not$libresoc.v:51298$3350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51198$3337 + cell $not $not$libresoc.v:51301$3353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51198$3337_Y + connect \Y $not$libresoc.v:51301$3353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51203$3342 + cell $not $not$libresoc.v:51306$3358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51203$3342_Y + connect \Y $not$libresoc.v:51306$3358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51205$3344 + cell $not $not$libresoc.v:51308$3360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51205$3344_Y + connect \Y $not$libresoc.v:51308$3360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:51164$3303 + cell $pos $pos$libresoc.v:51267$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51164$3303_Y + connect \Y $pos$libresoc.v:51267$3319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:51175$3314 + cell $pos $pos$libresoc.v:51278$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:51175$3314_Y + connect \Y $pos$libresoc.v:51278$3330_Y end - attribute \src "libresoc.v:50897.7-50897.20" - process $proc$libresoc.v:50897$3430 + attribute \src "libresoc.v:51000.7-51000.20" + process $proc$libresoc.v:51000$3446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51084.7-51084.31" - process $proc$libresoc.v:51084$3431 + attribute \src "libresoc.v:51187.7-51187.31" + process $proc$libresoc.v:51187$3447 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51088.7-51088.33" - process $proc$libresoc.v:51088$3432 + attribute \src "libresoc.v:51191.7-51191.33" + process $proc$libresoc.v:51191$3448 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51094.7-51094.25" - process $proc$libresoc.v:51094$3433 + attribute \src "libresoc.v:51197.7-51197.25" + process $proc$libresoc.v:51197$3449 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51100.7-51100.27" - process $proc$libresoc.v:51100$3434 + attribute \src "libresoc.v:51203.7-51203.27" + process $proc$libresoc.v:51203$3450 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51104.7-51104.24" - process $proc$libresoc.v:51104$3435 + attribute \src "libresoc.v:51207.7-51207.24" + process $proc$libresoc.v:51207$3451 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51108.7-51108.22" - process $proc$libresoc.v:51108$3436 + attribute \src "libresoc.v:51211.7-51211.22" + process $proc$libresoc.v:51211$3452 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51112.7-51112.21" - process $proc$libresoc.v:51112$3437 + attribute \src "libresoc.v:51215.7-51215.21" + process $proc$libresoc.v:51215$3453 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51116.13-51116.31" - process $proc$libresoc.v:51116$3438 + attribute \src "libresoc.v:51219.13-51219.31" + process $proc$libresoc.v:51219$3454 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51122.14-51122.34" - process $proc$libresoc.v:51122$3439 + attribute \src "libresoc.v:51225.14-51225.34" + process $proc$libresoc.v:51225$3455 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51134.7-51134.22" - process $proc$libresoc.v:51134$3440 + attribute \src "libresoc.v:51237.7-51237.22" + process $proc$libresoc.v:51237$3456 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51140.7-51140.24" - process $proc$libresoc.v:51140$3441 + attribute \src "libresoc.v:51243.7-51243.24" + process $proc$libresoc.v:51243$3457 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51208.3-51209.51" - process $proc$libresoc.v:51208$3347 + attribute \src "libresoc.v:51311.3-51312.51" + process $proc$libresoc.v:51311$3363 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51210.3-51211.55" - process $proc$libresoc.v:51210$3348 + attribute \src "libresoc.v:51313.3-51314.55" + process $proc$libresoc.v:51313$3364 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51212.3-51213.41" - process $proc$libresoc.v:51212$3349 + attribute \src "libresoc.v:51315.3-51316.41" + process $proc$libresoc.v:51315$3365 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51214.3-51215.37" - process $proc$libresoc.v:51214$3350 + attribute \src "libresoc.v:51317.3-51318.37" + process $proc$libresoc.v:51317$3366 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51216.3-51217.33" - process $proc$libresoc.v:51216$3351 + attribute \src "libresoc.v:51319.3-51320.33" + process $proc$libresoc.v:51319$3367 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51218.3-51219.37" - process $proc$libresoc.v:51218$3352 + attribute \src "libresoc.v:51321.3-51322.37" + process $proc$libresoc.v:51321$3368 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51220.3-51221.39" - process $proc$libresoc.v:51220$3353 + attribute \src "libresoc.v:51323.3-51324.39" + process $proc$libresoc.v:51323$3369 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51222.3-51223.43" - process $proc$libresoc.v:51222$3354 + attribute \src "libresoc.v:51325.3-51326.43" + process $proc$libresoc.v:51325$3370 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51224.3-51225.37" - process $proc$libresoc.v:51224$3355 + attribute \src "libresoc.v:51327.3-51328.37" + process $proc$libresoc.v:51327$3371 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51226.3-51227.33" - process $proc$libresoc.v:51226$3356 + attribute \src "libresoc.v:51329.3-51330.33" + process $proc$libresoc.v:51329$3372 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51228.3-51229.31" - process $proc$libresoc.v:51228$3357 + attribute \src "libresoc.v:51331.3-51332.31" + process $proc$libresoc.v:51331$3373 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51230.3-51247.6" - process $proc$libresoc.v:51230$3358 + attribute \src "libresoc.v:51333.3-51350.6" + process $proc$libresoc.v:51333$3374 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51231.5-51231.29" + attribute \src "libresoc.v:51334.5-51334.29" switch \initial - attribute \src "libresoc.v:51231.9-51231.17" + attribute \src "libresoc.v:51334.9-51334.17" case 1'1 case end @@ -91331,14 +91587,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51248.3-51257.6" - process $proc$libresoc.v:51248$3359 + attribute \src "libresoc.v:51351.3-51360.6" + process $proc$libresoc.v:51351$3375 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51249.5-51249.29" + attribute \src "libresoc.v:51352.5-51352.29" switch \initial - attribute \src "libresoc.v:51249.9-51249.17" + attribute \src "libresoc.v:51352.9-51352.17" case 1'1 case end @@ -91354,14 +91610,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51258.3-51266.6" - process $proc$libresoc.v:51258$3360 + attribute \src "libresoc.v:51361.3-51369.6" + process $proc$libresoc.v:51361$3376 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51259.5-51259.29" + assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378 + attribute \src "libresoc.v:51362.5-51362.29" switch \initial - attribute \src "libresoc.v:51259.9-51259.17" + attribute \src "libresoc.v:51362.9-51362.17" case 1'1 case end @@ -91370,23 +91626,23 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3362 1'0 + assign $1\dmi_req_i_1$next[0:0]$3378 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3378 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377 end - attribute \src "libresoc.v:51267.3-51316.6" - process $proc$libresoc.v:51267$3363 + attribute \src "libresoc.v:51370.3-51419.6" + process $proc$libresoc.v:51370$3379 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51268.5-51268.29" + assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388 + attribute \src "libresoc.v:51371.5-51371.29" switch \initial - attribute \src "libresoc.v:51268.9-51268.17" + attribute \src "libresoc.v:51371.9-51371.17" case 1'1 case end @@ -91395,13 +91651,13 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366 + assign $1\terminated$next[0:0]$3381 $2\terminated$next[0:0]$3382 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367 + assign $2\terminated$next[0:0]$3382 $3\terminated$next[0:0]$3383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$73 \$71 \$69 } attribute \src "libresoc.v:0.0-0.0" @@ -91409,74 +91665,74 @@ module \dbg assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370 + assign $3\terminated$next[0:0]$3383 $6\terminated$next[0:0]$3386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3368 1'0 + assign $4\terminated$next[0:0]$3384 1'0 case - assign $4\terminated$next[0:0]$3368 \terminated + assign $4\terminated$next[0:0]$3384 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3369 1'0 + assign $5\terminated$next[0:0]$3385 1'0 case - assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368 + assign $5\terminated$next[0:0]$3385 $4\terminated$next[0:0]$3384 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3370 1'0 + assign $6\terminated$next[0:0]$3386 1'0 case - assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369 + assign $6\terminated$next[0:0]$3386 $5\terminated$next[0:0]$3385 end case - assign $3\terminated$next[0:0]$3367 \terminated + assign $3\terminated$next[0:0]$3383 \terminated end case - assign $2\terminated$next[0:0]$3366 \terminated + assign $2\terminated$next[0:0]$3382 \terminated end case - assign $1\terminated$next[0:0]$3365 \terminated + assign $1\terminated$next[0:0]$3381 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3371 1'1 + assign $7\terminated$next[0:0]$3387 1'1 case - assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365 + assign $7\terminated$next[0:0]$3387 $1\terminated$next[0:0]$3381 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3372 1'0 + assign $8\terminated$next[0:0]$3388 1'0 case - assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371 + assign $8\terminated$next[0:0]$3388 $7\terminated$next[0:0]$3387 end sync always - update \terminated$next $0\terminated$next[0:0]$3364 + update \terminated$next $0\terminated$next[0:0]$3380 end - attribute \src "libresoc.v:51317.3-51360.6" - process $proc$libresoc.v:51317$3373 + attribute \src "libresoc.v:51420.3-51463.6" + process $proc$libresoc.v:51420$3389 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51318.5-51318.29" + assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397 + attribute \src "libresoc.v:51421.5-51421.29" switch \initial - attribute \src "libresoc.v:51318.9-51318.17" + attribute \src "libresoc.v:51421.9-51421.17" case 1'1 case end @@ -91485,77 +91741,77 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376 + assign $1\stopping$next[0:0]$3391 $2\stopping$next[0:0]$3392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377 + assign $2\stopping$next[0:0]$3392 $3\stopping$next[0:0]$3393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$87 \$85 \$83 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379 + assign $3\stopping$next[0:0]$3393 $5\stopping$next[0:0]$3395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3378 1'1 + assign $4\stopping$next[0:0]$3394 1'1 case - assign $4\stopping$next[0:0]$3378 \stopping + assign $4\stopping$next[0:0]$3394 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3379 1'0 + assign $5\stopping$next[0:0]$3395 1'0 case - assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378 + assign $5\stopping$next[0:0]$3395 $4\stopping$next[0:0]$3394 end case - assign $3\stopping$next[0:0]$3377 \stopping + assign $3\stopping$next[0:0]$3393 \stopping end case - assign $2\stopping$next[0:0]$3376 \stopping + assign $2\stopping$next[0:0]$3392 \stopping end case - assign $1\stopping$next[0:0]$3375 \stopping + assign $1\stopping$next[0:0]$3391 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3380 1'1 + assign $6\stopping$next[0:0]$3396 1'1 case - assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375 + assign $6\stopping$next[0:0]$3396 $1\stopping$next[0:0]$3391 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3381 1'0 + assign $7\stopping$next[0:0]$3397 1'0 case - assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380 + assign $7\stopping$next[0:0]$3397 $6\stopping$next[0:0]$3396 end sync always - update \stopping$next $0\stopping$next[0:0]$3374 + update \stopping$next $0\stopping$next[0:0]$3390 end - attribute \src "libresoc.v:51361.3-51388.6" - process $proc$libresoc.v:51361$3382 + attribute \src "libresoc.v:51464.3-51491.6" + process $proc$libresoc.v:51464$3398 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51362.5-51362.29" + assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403 + attribute \src "libresoc.v:51465.5-51465.29" switch \initial - attribute \src "libresoc.v:51362.9-51362.17" + attribute \src "libresoc.v:51465.9-51465.17" case 1'1 case end @@ -91564,52 +91820,52 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385 + assign $1\gspr_index$next[6:0]$3400 $2\gspr_index$next[6:0]$3401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386 + assign $2\gspr_index$next[6:0]$3401 $3\gspr_index$next[6:0]$3402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$101 \$99 \$97 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3386 \gspr_index + assign $3\gspr_index$next[6:0]$3402 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3402 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3386 \gspr_index + assign $3\gspr_index$next[6:0]$3402 \gspr_index end case - assign $2\gspr_index$next[6:0]$3385 \gspr_index + assign $2\gspr_index$next[6:0]$3401 \gspr_index end case - assign $1\gspr_index$next[6:0]$3384 \gspr_index + assign $1\gspr_index$next[6:0]$3400 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3387 7'0000000 + assign $4\gspr_index$next[6:0]$3403 7'0000000 case - assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384 + assign $4\gspr_index$next[6:0]$3403 $1\gspr_index$next[6:0]$3400 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3383 + update \gspr_index$next $0\gspr_index$next[6:0]$3399 end - attribute \src "libresoc.v:51389.3-51422.6" - process $proc$libresoc.v:51389$3388 + attribute \src "libresoc.v:51492.3-51525.6" + process $proc$libresoc.v:51492$3404 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51390.5-51390.29" + assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409 + attribute \src "libresoc.v:51493.5-51493.29" switch \initial - attribute \src "libresoc.v:51390.9-51390.17" + attribute \src "libresoc.v:51493.9-51493.17" case 1'1 case end @@ -91618,58 +91874,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391 + assign $1\log_dmi_addr$next[31:0]$3406 $2\log_dmi_addr$next[31:0]$3407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392 + assign $2\log_dmi_addr$next[31:0]$3407 $3\log_dmi_addr$next[31:0]$3408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$115 \$113 \$111 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3408 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3407 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0] + assign $1\log_dmi_addr$next[31:0]$3406 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3406 [1:0] \$117 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3406 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3393 0 + assign $4\log_dmi_addr$next[31:0]$3409 0 case - assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390 + assign $4\log_dmi_addr$next[31:0]$3409 $1\log_dmi_addr$next[31:0]$3406 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405 end - attribute \src "libresoc.v:51423.3-51431.6" - process $proc$libresoc.v:51423$3394 + attribute \src "libresoc.v:51526.3-51534.6" + process $proc$libresoc.v:51526$3410 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51424.5-51424.29" + assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412 + attribute \src "libresoc.v:51527.5-51527.29" switch \initial - attribute \src "libresoc.v:51424.9-51424.17" + attribute \src "libresoc.v:51527.9-51527.17" case 1'1 case end @@ -91678,21 +91934,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3412 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3412 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411 end - attribute \src "libresoc.v:51432.3-51440.6" - process $proc$libresoc.v:51432$3397 + attribute \src "libresoc.v:51535.3-51543.6" + process $proc$libresoc.v:51535$3413 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51433.5-51433.29" + assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415 + attribute \src "libresoc.v:51536.5-51536.29" switch \initial - attribute \src "libresoc.v:51433.9-51433.17" + attribute \src "libresoc.v:51536.9-51536.17" case 1'1 case end @@ -91701,21 +91957,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3399 1'0 + assign $1\dmi_read_log_data$next[0:0]$3415 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3399 \$122 + assign $1\dmi_read_log_data$next[0:0]$3415 \$122 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414 end - attribute \src "libresoc.v:51441.3-51450.6" - process $proc$libresoc.v:51441$3400 + attribute \src "libresoc.v:51544.3-51553.6" + process $proc$libresoc.v:51544$3416 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51442.5-51442.29" + attribute \src "libresoc.v:51545.5-51545.29" switch \initial - attribute \src "libresoc.v:51442.9-51442.17" + attribute \src "libresoc.v:51545.9-51545.17" case 1'1 case end @@ -91731,14 +91987,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51451.3-51460.6" - process $proc$libresoc.v:51451$3401 + attribute \src "libresoc.v:51554.3-51563.6" + process $proc$libresoc.v:51554$3417 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51452.5-51452.29" + attribute \src "libresoc.v:51555.5-51555.29" switch \initial - attribute \src "libresoc.v:51452.9-51452.17" + attribute \src "libresoc.v:51555.9-51555.17" case 1'1 case end @@ -91754,14 +92010,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51461.3-51494.6" - process $proc$libresoc.v:51461$3402 + attribute \src "libresoc.v:51564.3-51597.6" + process $proc$libresoc.v:51564$3418 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51462.5-51462.29" + attribute \src "libresoc.v:51565.5-51565.29" switch \initial - attribute \src "libresoc.v:51462.9-51462.17" + attribute \src "libresoc.v:51565.9-51565.17" case 1'1 case end @@ -91809,15 +92065,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51495.3-51524.6" - process $proc$libresoc.v:51495$3403 + attribute \src "libresoc.v:51598.3-51627.6" + process $proc$libresoc.v:51598$3419 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51496.5-51496.29" + assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425 + attribute \src "libresoc.v:51599.5-51599.29" switch \initial - attribute \src "libresoc.v:51496.9-51496.17" + attribute \src "libresoc.v:51599.9-51599.17" case 1'1 case end @@ -91826,58 +92082,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406 + assign $1\do_step$next[0:0]$3421 $2\do_step$next[0:0]$3422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407 + assign $2\do_step$next[0:0]$3422 $3\do_step$next[0:0]$3423 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$17 \$15 \$13 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408 + assign $3\do_step$next[0:0]$3423 $4\do_step$next[0:0]$3424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3408 1'1 + assign $4\do_step$next[0:0]$3424 1'1 case - assign $4\do_step$next[0:0]$3408 1'0 + assign $4\do_step$next[0:0]$3424 1'0 end case - assign $3\do_step$next[0:0]$3407 1'0 + assign $3\do_step$next[0:0]$3423 1'0 end case - assign $2\do_step$next[0:0]$3406 1'0 + assign $2\do_step$next[0:0]$3422 1'0 end case - assign $1\do_step$next[0:0]$3405 1'0 + assign $1\do_step$next[0:0]$3421 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3409 1'0 + assign $5\do_step$next[0:0]$3425 1'0 case - assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405 + assign $5\do_step$next[0:0]$3425 $1\do_step$next[0:0]$3421 end sync always - update \do_step$next $0\do_step$next[0:0]$3404 + update \do_step$next $0\do_step$next[0:0]$3420 end - attribute \src "libresoc.v:51525.3-51554.6" - process $proc$libresoc.v:51525$3410 + attribute \src "libresoc.v:51628.3-51657.6" + process $proc$libresoc.v:51628$3426 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51526.5-51526.29" + assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432 + attribute \src "libresoc.v:51629.5-51629.29" switch \initial - attribute \src "libresoc.v:51526.9-51526.17" + attribute \src "libresoc.v:51629.9-51629.17" case 1'1 case end @@ -91886,58 +92142,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413 + assign $1\do_reset$next[0:0]$3428 $2\do_reset$next[0:0]$3429 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414 + assign $2\do_reset$next[0:0]$3429 $3\do_reset$next[0:0]$3430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$31 \$29 \$27 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415 + assign $3\do_reset$next[0:0]$3430 $4\do_reset$next[0:0]$3431 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3415 1'1 + assign $4\do_reset$next[0:0]$3431 1'1 case - assign $4\do_reset$next[0:0]$3415 1'0 + assign $4\do_reset$next[0:0]$3431 1'0 end case - assign $3\do_reset$next[0:0]$3414 1'0 + assign $3\do_reset$next[0:0]$3430 1'0 end case - assign $2\do_reset$next[0:0]$3413 1'0 + assign $2\do_reset$next[0:0]$3429 1'0 end case - assign $1\do_reset$next[0:0]$3412 1'0 + assign $1\do_reset$next[0:0]$3428 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3416 1'0 + assign $5\do_reset$next[0:0]$3432 1'0 case - assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412 + assign $5\do_reset$next[0:0]$3432 $1\do_reset$next[0:0]$3428 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3411 + update \do_reset$next $0\do_reset$next[0:0]$3427 end - attribute \src "libresoc.v:51555.3-51584.6" - process $proc$libresoc.v:51555$3417 + attribute \src "libresoc.v:51658.3-51687.6" + process $proc$libresoc.v:51658$3433 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51556.5-51556.29" + assign $0\do_icreset$next[0:0]$3434 $5\do_icreset$next[0:0]$3439 + attribute \src "libresoc.v:51659.5-51659.29" switch \initial - attribute \src "libresoc.v:51556.9-51556.17" + attribute \src "libresoc.v:51659.9-51659.17" case 1'1 case end @@ -91946,58 +92202,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420 + assign $1\do_icreset$next[0:0]$3435 $2\do_icreset$next[0:0]$3436 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421 + assign $2\do_icreset$next[0:0]$3436 $3\do_icreset$next[0:0]$3437 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$45 \$43 \$41 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422 + assign $3\do_icreset$next[0:0]$3437 $4\do_icreset$next[0:0]$3438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3422 1'1 + assign $4\do_icreset$next[0:0]$3438 1'1 case - assign $4\do_icreset$next[0:0]$3422 1'0 + assign $4\do_icreset$next[0:0]$3438 1'0 end case - assign $3\do_icreset$next[0:0]$3421 1'0 + assign $3\do_icreset$next[0:0]$3437 1'0 end case - assign $2\do_icreset$next[0:0]$3420 1'0 + assign $2\do_icreset$next[0:0]$3436 1'0 end case - assign $1\do_icreset$next[0:0]$3419 1'0 + assign $1\do_icreset$next[0:0]$3435 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3423 1'0 + assign $5\do_icreset$next[0:0]$3439 1'0 case - assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419 + assign $5\do_icreset$next[0:0]$3439 $1\do_icreset$next[0:0]$3435 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3418 + update \do_icreset$next $0\do_icreset$next[0:0]$3434 end - attribute \src "libresoc.v:51585.3-51618.6" - process $proc$libresoc.v:51585$3424 + attribute \src "libresoc.v:51688.3-51721.6" + process $proc$libresoc.v:51688$3440 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51586.5-51586.29" + assign $0\do_dmi_log_rd$next[0:0]$3441 $4\do_dmi_log_rd$next[0:0]$3445 + attribute \src "libresoc.v:51689.5-51689.29" switch \initial - attribute \src "libresoc.v:51586.9-51586.17" + attribute \src "libresoc.v:51689.9-51689.17" case 1'1 case end @@ -92006,113 +92262,113 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427 + assign $1\do_dmi_log_rd$next[0:0]$3442 $2\do_dmi_log_rd$next[0:0]$3443 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428 + assign $2\do_dmi_log_rd$next[0:0]$3443 $3\do_dmi_log_rd$next[0:0]$3444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$59 \$57 \$55 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3428 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3427 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3443 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3426 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3442 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3426 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3442 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3429 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 - end - connect \$9 $not$libresoc.v:51145$3284_Y - connect \$99 $eq$libresoc.v:51146$3285_Y - connect \$101 $eq$libresoc.v:51147$3286_Y - connect \$103 $not$libresoc.v:51148$3287_Y - connect \$105 $and$libresoc.v:51149$3288_Y - connect \$107 $not$libresoc.v:51150$3289_Y - connect \$109 $and$libresoc.v:51151$3290_Y - connect \$111 $eq$libresoc.v:51152$3291_Y - connect \$113 $eq$libresoc.v:51153$3292_Y - connect \$115 $eq$libresoc.v:51154$3293_Y - connect \$118 $add$libresoc.v:51155$3294_Y - connect \$11 $and$libresoc.v:51156$3295_Y - connect \$120 $eq$libresoc.v:51157$3296_Y - connect \$122 $and$libresoc.v:51158$3297_Y - connect \$124 $not$libresoc.v:51159$3298_Y - connect \$126 $and$libresoc.v:51160$3299_Y - connect \$13 $eq$libresoc.v:51161$3300_Y - connect \$15 $eq$libresoc.v:51162$3301_Y - connect \$17 $eq$libresoc.v:51163$3302_Y - connect \$1 $pos$libresoc.v:51164$3303_Y - connect \$19 $not$libresoc.v:51165$3304_Y - connect \$21 $and$libresoc.v:51166$3305_Y - connect \$23 $not$libresoc.v:51167$3306_Y - connect \$25 $and$libresoc.v:51168$3307_Y - connect \$27 $eq$libresoc.v:51169$3308_Y - connect \$29 $eq$libresoc.v:51170$3309_Y - connect \$31 $eq$libresoc.v:51171$3310_Y - connect \$33 $not$libresoc.v:51172$3311_Y - connect \$35 $and$libresoc.v:51173$3312_Y - connect \$37 $not$libresoc.v:51174$3313_Y - connect \$3 $pos$libresoc.v:51175$3314_Y - connect \$39 $and$libresoc.v:51176$3315_Y - connect \$41 $eq$libresoc.v:51177$3316_Y - connect \$43 $eq$libresoc.v:51178$3317_Y - connect \$45 $eq$libresoc.v:51179$3318_Y - connect \$47 $not$libresoc.v:51180$3319_Y - connect \$49 $and$libresoc.v:51181$3320_Y - connect \$51 $not$libresoc.v:51182$3321_Y - connect \$53 $and$libresoc.v:51183$3322_Y - connect \$55 $eq$libresoc.v:51184$3323_Y - connect \$57 $eq$libresoc.v:51185$3324_Y - connect \$5 $not$libresoc.v:51186$3325_Y - connect \$59 $eq$libresoc.v:51187$3326_Y - connect \$61 $not$libresoc.v:51188$3327_Y - connect \$63 $and$libresoc.v:51189$3328_Y - connect \$65 $not$libresoc.v:51190$3329_Y - connect \$67 $and$libresoc.v:51191$3330_Y - connect \$69 $eq$libresoc.v:51192$3331_Y - connect \$71 $eq$libresoc.v:51193$3332_Y - connect \$73 $eq$libresoc.v:51194$3333_Y - connect \$75 $not$libresoc.v:51195$3334_Y - connect \$77 $and$libresoc.v:51196$3335_Y - connect \$7 $and$libresoc.v:51197$3336_Y - connect \$79 $not$libresoc.v:51198$3337_Y - connect \$81 $and$libresoc.v:51199$3338_Y - connect \$83 $eq$libresoc.v:51200$3339_Y - connect \$85 $eq$libresoc.v:51201$3340_Y - connect \$87 $eq$libresoc.v:51202$3341_Y - connect \$89 $not$libresoc.v:51203$3342_Y - connect \$91 $and$libresoc.v:51204$3343_Y - connect \$93 $not$libresoc.v:51205$3344_Y - connect \$95 $and$libresoc.v:51206$3345_Y - connect \$97 $eq$libresoc.v:51207$3346_Y + assign $4\do_dmi_log_rd$next[0:0]$3445 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3445 $1\do_dmi_log_rd$next[0:0]$3442 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3441 + end + connect \$9 $not$libresoc.v:51248$3300_Y + connect \$99 $eq$libresoc.v:51249$3301_Y + connect \$101 $eq$libresoc.v:51250$3302_Y + connect \$103 $not$libresoc.v:51251$3303_Y + connect \$105 $and$libresoc.v:51252$3304_Y + connect \$107 $not$libresoc.v:51253$3305_Y + connect \$109 $and$libresoc.v:51254$3306_Y + connect \$111 $eq$libresoc.v:51255$3307_Y + connect \$113 $eq$libresoc.v:51256$3308_Y + connect \$115 $eq$libresoc.v:51257$3309_Y + connect \$118 $add$libresoc.v:51258$3310_Y + connect \$11 $and$libresoc.v:51259$3311_Y + connect \$120 $eq$libresoc.v:51260$3312_Y + connect \$122 $and$libresoc.v:51261$3313_Y + connect \$124 $not$libresoc.v:51262$3314_Y + connect \$126 $and$libresoc.v:51263$3315_Y + connect \$13 $eq$libresoc.v:51264$3316_Y + connect \$15 $eq$libresoc.v:51265$3317_Y + connect \$17 $eq$libresoc.v:51266$3318_Y + connect \$1 $pos$libresoc.v:51267$3319_Y + connect \$19 $not$libresoc.v:51268$3320_Y + connect \$21 $and$libresoc.v:51269$3321_Y + connect \$23 $not$libresoc.v:51270$3322_Y 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+ connect \$67 $and$libresoc.v:51294$3346_Y + connect \$69 $eq$libresoc.v:51295$3347_Y + connect \$71 $eq$libresoc.v:51296$3348_Y + connect \$73 $eq$libresoc.v:51297$3349_Y + connect \$75 $not$libresoc.v:51298$3350_Y + connect \$77 $and$libresoc.v:51299$3351_Y + connect \$7 $and$libresoc.v:51300$3352_Y + connect \$79 $not$libresoc.v:51301$3353_Y + connect \$81 $and$libresoc.v:51302$3354_Y + connect \$83 $eq$libresoc.v:51303$3355_Y + connect \$85 $eq$libresoc.v:51304$3356_Y + connect \$87 $eq$libresoc.v:51305$3357_Y + connect \$89 $not$libresoc.v:51306$3358_Y + connect \$91 $and$libresoc.v:51307$3359_Y + connect \$93 $not$libresoc.v:51308$3360_Y + connect \$95 $and$libresoc.v:51309$3361_Y + connect \$97 $eq$libresoc.v:51310$3362_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92123,140 +92379,140 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51632.1-53682.10" +attribute \src "libresoc.v:51735.1-53785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53243.3-53276.6" + attribute \src "libresoc.v:53346.3-53379.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53277.3-53310.6" + attribute \src "libresoc.v:53380.3-53413.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:52903.3-52936.6" + attribute \src "libresoc.v:53006.3-53039.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:53005.3-53038.6" + attribute \src "libresoc.v:53108.3-53141.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53107.3-53140.6" + attribute \src "libresoc.v:53210.3-53243.6" wire width 14 $0\ALU_function_unit[13:0] - attribute \src "libresoc.v:53175.3-53208.6" + attribute \src "libresoc.v:53278.3-53311.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53209.3-53242.6" + attribute \src "libresoc.v:53312.3-53345.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53141.3-53174.6" + attribute \src "libresoc.v:53244.3-53277.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:52937.3-52970.6" + attribute \src "libresoc.v:53040.3-53073.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:52971.3-53004.6" + attribute \src "libresoc.v:53074.3-53107.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53039.3-53072.6" + attribute \src "libresoc.v:53142.3-53175.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53311.3-53344.6" + attribute \src "libresoc.v:53414.3-53447.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52869.3-52902.6" + attribute \src "libresoc.v:52972.3-53005.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53073.3-53106.6" + attribute \src "libresoc.v:53176.3-53209.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51633.7-51633.20" + attribute \src "libresoc.v:51736.7-51736.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53243.3-53276.6" + attribute \src "libresoc.v:53346.3-53379.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53277.3-53310.6" + attribute \src "libresoc.v:53380.3-53413.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52903.3-52936.6" + attribute \src "libresoc.v:53006.3-53039.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53005.3-53038.6" + attribute \src "libresoc.v:53108.3-53141.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53107.3-53140.6" + attribute \src "libresoc.v:53210.3-53243.6" wire width 14 $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53175.3-53208.6" + attribute \src "libresoc.v:53278.3-53311.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53209.3-53242.6" + attribute \src "libresoc.v:53312.3-53345.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53141.3-53174.6" + attribute \src "libresoc.v:53244.3-53277.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52937.3-52970.6" + attribute \src "libresoc.v:53040.3-53073.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52971.3-53004.6" + attribute \src "libresoc.v:53074.3-53107.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53039.3-53072.6" + attribute \src "libresoc.v:53142.3-53175.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53311.3-53344.6" + attribute \src "libresoc.v:53414.3-53447.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52869.3-52902.6" + attribute \src "libresoc.v:52972.3-53005.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53073.3-53106.6" + attribute \src "libresoc.v:53176.3-53209.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52834.17-52834.211" - wire width 32 $ternary$libresoc.v:52834$3442_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:52937.17-52937.211" + wire width 32 $ternary$libresoc.v:52937$3458_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \ALU_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \ALU_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \ALU_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \ALU_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \ALU_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92267,7 +92523,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92276,15 +92532,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92295,7 +92551,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92304,15 +92560,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92329,7 +92585,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92337,7 +92593,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92354,7 +92610,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92431,13 +92687,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec19_ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92445,17 +92701,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92466,7 +92722,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92475,15 +92731,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92500,7 +92756,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92508,7 +92764,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92525,7 +92781,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92602,13 +92858,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92616,17 +92872,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92643,7 +92899,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92651,7 +92907,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92668,7 +92924,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92745,13 +93001,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92759,634 +93015,634 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:51633.7-51633.15" + attribute \src "libresoc.v:51736.7-51736.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:52834$3442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:52937$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52834$3442_Y + connect \Y $ternary$libresoc.v:52937$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52835.13-52851.4" + attribute \src "libresoc.v:52938.13-52954.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93405,7 +93661,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52852.13-52868.4" + attribute \src "libresoc.v:52955.13-52971.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93423,26 +93679,26 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51633.7-51633.20" - process $proc$libresoc.v:51633$3457 + attribute \src "libresoc.v:51736.7-51736.20" + process $proc$libresoc.v:51736$3473 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52869.3-52902.6" - process $proc$libresoc.v:52869$3443 + attribute \src "libresoc.v:52972.3-53005.6" + process $proc$libresoc.v:52972$3459 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52870.5-52870.29" + attribute \src "libresoc.v:52973.5-52973.29" switch \initial - attribute \src "libresoc.v:52870.9-52870.17" + attribute \src "libresoc.v:52973.9-52973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93486,18 +93742,18 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52903.3-52936.6" - process $proc$libresoc.v:52903$3444 + attribute \src "libresoc.v:53006.3-53039.6" + process $proc$libresoc.v:53006$3460 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52904.5-52904.29" + attribute \src "libresoc.v:53007.5-53007.29" switch \initial - attribute \src "libresoc.v:52904.9-52904.17" + attribute \src "libresoc.v:53007.9-53007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93541,18 +93797,18 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:52937.3-52970.6" - process $proc$libresoc.v:52937$3445 + attribute \src "libresoc.v:53040.3-53073.6" + process $proc$libresoc.v:53040$3461 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52938.5-52938.29" + attribute \src "libresoc.v:53041.5-53041.29" switch \initial - attribute \src "libresoc.v:52938.9-52938.17" + attribute \src "libresoc.v:53041.9-53041.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93596,18 +93852,18 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:52971.3-53004.6" - process $proc$libresoc.v:52971$3446 + attribute \src "libresoc.v:53074.3-53107.6" + process $proc$libresoc.v:53074$3462 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52972.5-52972.29" + attribute \src "libresoc.v:53075.5-53075.29" switch \initial - attribute \src "libresoc.v:52972.9-52972.17" + attribute \src "libresoc.v:53075.9-53075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93651,18 +93907,18 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:53005.3-53038.6" - process $proc$libresoc.v:53005$3447 + attribute \src "libresoc.v:53108.3-53141.6" + process $proc$libresoc.v:53108$3463 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53006.5-53006.29" + attribute \src "libresoc.v:53109.5-53109.29" switch \initial - attribute \src "libresoc.v:53006.9-53006.17" + attribute \src "libresoc.v:53109.9-53109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93706,18 +93962,18 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53039.3-53072.6" - process $proc$libresoc.v:53039$3448 + attribute \src "libresoc.v:53142.3-53175.6" + process $proc$libresoc.v:53142$3464 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53040.5-53040.29" + attribute \src "libresoc.v:53143.5-53143.29" switch \initial - attribute \src "libresoc.v:53040.9-53040.17" + attribute \src "libresoc.v:53143.9-53143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93761,18 +94017,18 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53073.3-53106.6" - process $proc$libresoc.v:53073$3449 + attribute \src "libresoc.v:53176.3-53209.6" + process $proc$libresoc.v:53176$3465 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53074.5-53074.29" + attribute \src "libresoc.v:53177.5-53177.29" switch \initial - attribute \src "libresoc.v:53074.9-53074.17" + attribute \src "libresoc.v:53177.9-53177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93816,18 +94072,18 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53107.3-53140.6" - process $proc$libresoc.v:53107$3450 + attribute \src "libresoc.v:53210.3-53243.6" + process $proc$libresoc.v:53210$3466 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53108.5-53108.29" + attribute \src "libresoc.v:53211.5-53211.29" switch \initial - attribute \src "libresoc.v:53108.9-53108.17" + attribute \src "libresoc.v:53211.9-53211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93871,18 +94127,18 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:53141.3-53174.6" - process $proc$libresoc.v:53141$3451 + attribute \src "libresoc.v:53244.3-53277.6" + process $proc$libresoc.v:53244$3467 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53142.5-53142.29" + attribute \src "libresoc.v:53245.5-53245.29" switch \initial - attribute \src "libresoc.v:53142.9-53142.17" + attribute \src "libresoc.v:53245.9-53245.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93926,18 +94182,18 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53175.3-53208.6" - process $proc$libresoc.v:53175$3452 + attribute \src "libresoc.v:53278.3-53311.6" + process $proc$libresoc.v:53278$3468 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53176.5-53176.29" + attribute \src "libresoc.v:53279.5-53279.29" switch \initial - attribute \src "libresoc.v:53176.9-53176.17" + attribute \src "libresoc.v:53279.9-53279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93981,18 +94237,18 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53209.3-53242.6" - process $proc$libresoc.v:53209$3453 + attribute \src "libresoc.v:53312.3-53345.6" + process $proc$libresoc.v:53312$3469 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53210.5-53210.29" + attribute \src "libresoc.v:53313.5-53313.29" switch \initial - attribute \src "libresoc.v:53210.9-53210.17" + attribute \src "libresoc.v:53313.9-53313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94036,18 +94292,18 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53243.3-53276.6" - process $proc$libresoc.v:53243$3454 + attribute \src "libresoc.v:53346.3-53379.6" + process $proc$libresoc.v:53346$3470 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53244.5-53244.29" + attribute \src "libresoc.v:53347.5-53347.29" switch \initial - attribute \src "libresoc.v:53244.9-53244.17" + attribute \src "libresoc.v:53347.9-53347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94091,18 +94347,18 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53277.3-53310.6" - process $proc$libresoc.v:53277$3455 + attribute \src "libresoc.v:53380.3-53413.6" + process $proc$libresoc.v:53380$3471 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53278.5-53278.29" + attribute \src "libresoc.v:53381.5-53381.29" switch \initial - attribute \src "libresoc.v:53278.9-53278.17" + attribute \src "libresoc.v:53381.9-53381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94146,18 +94402,18 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53311.3-53344.6" - process $proc$libresoc.v:53311$3456 + attribute \src "libresoc.v:53414.3-53447.6" + process $proc$libresoc.v:53414$3472 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53312.5-53312.29" + attribute \src "libresoc.v:53415.5-53415.29" switch \initial - attribute \src "libresoc.v:53312.9-53312.17" + attribute \src "libresoc.v:53415.9-53415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94201,7 +94457,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52834$3442_Y + connect \$1 $ternary$libresoc.v:52937$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94540,134 +94796,134 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53686.1-55151.10" +attribute \src "libresoc.v:53789.1-55254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54775.3-54787.6" + attribute \src "libresoc.v:54878.3-54890.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54788.3-54800.6" + attribute \src "libresoc.v:54891.3-54903.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54749.3-54761.6" + attribute \src "libresoc.v:54852.3-54864.6" wire width 14 $0\CR_function_unit[13:0] - attribute \src "libresoc.v:54762.3-54774.6" + attribute \src "libresoc.v:54865.3-54877.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54801.3-54813.6" + attribute \src "libresoc.v:54904.3-54916.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53687.7-53687.20" + attribute \src "libresoc.v:53790.7-53790.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54775.3-54787.6" + attribute \src "libresoc.v:54878.3-54890.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54788.3-54800.6" + attribute \src "libresoc.v:54891.3-54903.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54749.3-54761.6" + attribute \src "libresoc.v:54852.3-54864.6" wire width 14 $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54762.3-54774.6" + attribute \src "libresoc.v:54865.3-54877.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54801.3-54813.6" + attribute \src "libresoc.v:54904.3-54916.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54732.17-54732.211" - wire width 32 $ternary$libresoc.v:54732$3458_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:54835.17-54835.211" + wire width 32 $ternary$libresoc.v:54835$3474_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \CR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \CR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \CR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \CR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \CR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \CR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 9 \CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \CR_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 8 \CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \CR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94678,7 +94934,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94687,7 +94943,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \CR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94698,7 +94954,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec19_CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94707,7 +94963,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec19_CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94724,7 +94980,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec19_CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -94801,15 +95057,15 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec19_CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec19_CR_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94820,7 +95076,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94829,7 +95085,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_CR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94846,7 +95102,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -94923,15 +95179,15 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_CR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94948,7 +95204,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -95025,602 +95281,602 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \CR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:53687.7-53687.15" + attribute \src "libresoc.v:53790.7-53790.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:54732$3458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:54835$3474 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54732$3458_Y + connect \Y $ternary$libresoc.v:54835$3474_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54733.12-54740.4" + attribute \src "libresoc.v:54836.12-54843.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95630,7 +95886,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54741.12-54748.4" + attribute \src "libresoc.v:54844.12-54851.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95639,26 +95895,26 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53687.7-53687.20" - process $proc$libresoc.v:53687$3464 + attribute \src "libresoc.v:53790.7-53790.20" + process $proc$libresoc.v:53790$3480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54749.3-54761.6" - process $proc$libresoc.v:54749$3459 + attribute \src "libresoc.v:54852.3-54864.6" + process $proc$libresoc.v:54852$3475 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54750.5-54750.29" + attribute \src "libresoc.v:54853.5-54853.29" switch \initial - attribute \src "libresoc.v:54750.9-54750.17" + attribute \src "libresoc.v:54853.9-54853.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95674,18 +95930,18 @@ module \dec$138 sync always update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54762.3-54774.6" - process $proc$libresoc.v:54762$3460 + attribute \src "libresoc.v:54865.3-54877.6" + process $proc$libresoc.v:54865$3476 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54763.5-54763.29" + attribute \src "libresoc.v:54866.5-54866.29" switch \initial - attribute \src "libresoc.v:54763.9-54763.17" + attribute \src "libresoc.v:54866.9-54866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95701,18 +95957,18 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54775.3-54787.6" - process $proc$libresoc.v:54775$3461 + attribute \src "libresoc.v:54878.3-54890.6" + process $proc$libresoc.v:54878$3477 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54776.5-54776.29" + attribute \src "libresoc.v:54879.5-54879.29" switch \initial - attribute \src "libresoc.v:54776.9-54776.17" + attribute \src "libresoc.v:54879.9-54879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95728,18 +95984,18 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54788.3-54800.6" - process $proc$libresoc.v:54788$3462 + attribute \src "libresoc.v:54891.3-54903.6" + process $proc$libresoc.v:54891$3478 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54789.5-54789.29" + attribute \src "libresoc.v:54892.5-54892.29" switch \initial - attribute \src "libresoc.v:54789.9-54789.17" + attribute \src "libresoc.v:54892.9-54892.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95755,18 +96011,18 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54801.3-54813.6" - process $proc$libresoc.v:54801$3463 + attribute \src "libresoc.v:54904.3-54916.6" + process $proc$libresoc.v:54904$3479 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54802.5-54802.29" + attribute \src "libresoc.v:54905.5-54905.29" switch \initial - attribute \src "libresoc.v:54802.9-54802.17" + attribute \src "libresoc.v:54905.9-54905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95782,7 +96038,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54732$3458_Y + connect \$1 $ternary$libresoc.v:54835$3474_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96121,136 +96377,136 @@ module \dec$138 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55155.1-56600.10" +attribute \src "libresoc.v:55258.1-56703.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:56184.3-56199.6" + attribute \src "libresoc.v:56287.3-56302.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56200.3-56215.6" + attribute \src "libresoc.v:56303.3-56318.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56136.3-56151.6" + attribute \src "libresoc.v:56239.3-56254.6" wire width 14 $0\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56168.3-56183.6" + attribute \src "libresoc.v:56271.3-56286.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56152.3-56167.6" + attribute \src "libresoc.v:56255.3-56270.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56232.3-56247.6" + attribute \src "libresoc.v:56335.3-56350.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56248.3-56263.6" + attribute \src "libresoc.v:56351.3-56366.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56216.3-56231.6" + attribute \src "libresoc.v:56319.3-56334.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55156.7-55156.20" + attribute \src "libresoc.v:55259.7-55259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56184.3-56199.6" + attribute \src "libresoc.v:56287.3-56302.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56200.3-56215.6" + attribute \src "libresoc.v:56303.3-56318.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56136.3-56151.6" + attribute \src "libresoc.v:56239.3-56254.6" wire width 14 $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56168.3-56183.6" + attribute \src "libresoc.v:56271.3-56286.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56152.3-56167.6" + attribute \src "libresoc.v:56255.3-56270.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56232.3-56247.6" + attribute \src "libresoc.v:56335.3-56350.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56248.3-56263.6" + attribute \src "libresoc.v:56351.3-56366.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56216.3-56231.6" + attribute \src "libresoc.v:56319.3-56334.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56124.17-56124.211" - wire width 32 $ternary$libresoc.v:56124$3465_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:56227.17-56227.211" + wire width 32 $ternary$libresoc.v:56227$3481_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BRANCH_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BRANCH_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \BRANCH_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \BRANCH_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 20 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 16 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 18 \BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \BRANCH_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 14 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96261,7 +96517,7 @@ module \dec$141 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96270,7 +96526,7 @@ module \dec$141 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96281,7 +96537,7 @@ module \dec$141 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96290,7 +96546,7 @@ module \dec$141 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -96307,7 +96563,7 @@ module \dec$141 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96324,7 +96580,7 @@ module \dec$141 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -96401,19 +96657,19 @@ module \dec$141 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -96430,7 +96686,7 @@ module \dec$141 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96447,7 +96703,7 @@ module \dec$141 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -96524,616 +96780,616 @@ module \dec$141 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 15 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:55156.7-55156.15" + attribute \src "libresoc.v:55259.7-55259.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:56124$3465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:56227$3481 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56124$3465_Y + connect \Y $ternary$libresoc.v:56227$3481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56125.16-56135.4" + attribute \src "libresoc.v:56228.16-56238.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97145,26 +97401,26 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55156.7-55156.20" - process $proc$libresoc.v:55156$3474 + attribute \src "libresoc.v:55259.7-55259.20" + process $proc$libresoc.v:55259$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56136.3-56151.6" - process $proc$libresoc.v:56136$3466 + attribute \src "libresoc.v:56239.3-56254.6" + process $proc$libresoc.v:56239$3482 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56137.5-56137.29" + attribute \src "libresoc.v:56240.5-56240.29" switch \initial - attribute \src "libresoc.v:56137.9-56137.17" + attribute \src "libresoc.v:56240.9-56240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97184,18 +97440,18 @@ module \dec$141 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:56152.3-56167.6" - process $proc$libresoc.v:56152$3467 + attribute \src "libresoc.v:56255.3-56270.6" + process $proc$libresoc.v:56255$3483 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56153.5-56153.29" + attribute \src "libresoc.v:56256.5-56256.29" switch \initial - attribute \src "libresoc.v:56153.9-56153.17" + attribute \src "libresoc.v:56256.9-56256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97215,18 +97471,18 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56168.3-56183.6" - process $proc$libresoc.v:56168$3468 + attribute \src "libresoc.v:56271.3-56286.6" + process $proc$libresoc.v:56271$3484 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56169.5-56169.29" + attribute \src "libresoc.v:56272.5-56272.29" switch \initial - attribute \src "libresoc.v:56169.9-56169.17" + attribute \src "libresoc.v:56272.9-56272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97246,18 +97502,18 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56184.3-56199.6" - process $proc$libresoc.v:56184$3469 + attribute \src "libresoc.v:56287.3-56302.6" + process $proc$libresoc.v:56287$3485 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56185.5-56185.29" + attribute \src "libresoc.v:56288.5-56288.29" switch \initial - attribute \src "libresoc.v:56185.9-56185.17" + attribute \src "libresoc.v:56288.9-56288.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97277,18 +97533,18 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56200.3-56215.6" - process $proc$libresoc.v:56200$3470 + attribute \src "libresoc.v:56303.3-56318.6" + process $proc$libresoc.v:56303$3486 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56201.5-56201.29" + attribute \src "libresoc.v:56304.5-56304.29" switch \initial - attribute \src "libresoc.v:56201.9-56201.17" + attribute \src "libresoc.v:56304.9-56304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97308,18 +97564,18 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56216.3-56231.6" - process $proc$libresoc.v:56216$3471 + attribute \src "libresoc.v:56319.3-56334.6" + process $proc$libresoc.v:56319$3487 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56217.5-56217.29" + attribute \src "libresoc.v:56320.5-56320.29" switch \initial - attribute \src "libresoc.v:56217.9-56217.17" + attribute \src "libresoc.v:56320.9-56320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97339,18 +97595,18 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56232.3-56247.6" - process $proc$libresoc.v:56232$3472 + attribute \src "libresoc.v:56335.3-56350.6" + process $proc$libresoc.v:56335$3488 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56233.5-56233.29" + attribute \src "libresoc.v:56336.5-56336.29" switch \initial - attribute \src "libresoc.v:56233.9-56233.17" + attribute \src "libresoc.v:56336.9-56336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97370,18 +97626,18 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56248.3-56263.6" - process $proc$libresoc.v:56248$3473 + attribute \src "libresoc.v:56351.3-56366.6" + process $proc$libresoc.v:56351$3489 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56249.5-56249.29" + attribute \src "libresoc.v:56352.5-56352.29" switch \initial - attribute \src "libresoc.v:56249.9-56249.17" + attribute \src "libresoc.v:56352.9-56352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97401,7 +97657,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56124$3465_Y + connect \$1 $ternary$libresoc.v:56227$3481_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97739,260 +97995,260 @@ module \dec$141 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56604.1-58381.10" +attribute \src "libresoc.v:56707.1-58484.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:57933.3-57960.6" + attribute \src "libresoc.v:58036.3-58063.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57961.3-57988.6" + attribute \src "libresoc.v:58064.3-58091.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57653.3-57680.6" + attribute \src "libresoc.v:57756.3-57783.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57737.3-57764.6" + attribute \src "libresoc.v:57840.3-57867.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57821.3-57848.6" + attribute \src "libresoc.v:57924.3-57951.6" wire width 14 $0\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57877.3-57904.6" + attribute \src "libresoc.v:57980.3-58007.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57905.3-57932.6" + attribute \src "libresoc.v:58008.3-58035.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57849.3-57876.6" + attribute \src "libresoc.v:57952.3-57979.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57681.3-57708.6" + attribute \src "libresoc.v:57784.3-57811.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57709.3-57736.6" + attribute \src "libresoc.v:57812.3-57839.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57765.3-57792.6" + attribute \src "libresoc.v:57868.3-57895.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57989.3-58016.6" + attribute \src "libresoc.v:58092.3-58119.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58017.3-58044.6" + attribute \src "libresoc.v:58120.3-58147.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57793.3-57820.6" + attribute \src "libresoc.v:57896.3-57923.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56605.7-56605.20" + attribute \src "libresoc.v:56708.7-56708.20" wire $0\initial[0:0] - attribute \src "libresoc.v:57933.3-57960.6" + attribute \src "libresoc.v:58036.3-58063.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57961.3-57988.6" + attribute \src "libresoc.v:58064.3-58091.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57653.3-57680.6" + attribute \src "libresoc.v:57756.3-57783.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57737.3-57764.6" + attribute \src "libresoc.v:57840.3-57867.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57821.3-57848.6" + attribute \src "libresoc.v:57924.3-57951.6" wire width 14 $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57877.3-57904.6" + attribute \src "libresoc.v:57980.3-58007.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57905.3-57932.6" + attribute \src "libresoc.v:58008.3-58035.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57849.3-57876.6" + attribute \src "libresoc.v:57952.3-57979.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57681.3-57708.6" + attribute \src "libresoc.v:57784.3-57811.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57709.3-57736.6" + attribute \src "libresoc.v:57812.3-57839.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57765.3-57792.6" + attribute \src "libresoc.v:57868.3-57895.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57989.3-58016.6" + attribute \src "libresoc.v:58092.3-58119.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58017.3-58044.6" + attribute \src "libresoc.v:58120.3-58147.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57793.3-57820.6" + attribute \src "libresoc.v:57896.3-57923.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57635.17-57635.211" - wire width 32 $ternary$libresoc.v:57635$3475_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:57738.17-57738.211" + wire width 32 $ternary$libresoc.v:57738$3491_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LOGICAL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LOGICAL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LOGICAL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LOGICAL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LOGICAL_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98003,7 +98259,7 @@ module \dec$145 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98012,15 +98268,15 @@ module \dec$145 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98031,7 +98287,7 @@ module \dec$145 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98040,15 +98296,15 @@ module \dec$145 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -98065,7 +98321,7 @@ module \dec$145 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -98073,7 +98329,7 @@ module \dec$145 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -98090,7 +98346,7 @@ module \dec$145 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -98167,13 +98423,13 @@ module \dec$145 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -98181,17 +98437,17 @@ module \dec$145 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -98208,7 +98464,7 @@ module \dec$145 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -98216,7 +98472,7 @@ module \dec$145 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -98233,7 +98489,7 @@ module \dec$145 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -98310,13 +98566,13 @@ module \dec$145 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -98324,514 +98580,514 @@ module \dec$145 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:56605.7-56605.15" + attribute \src "libresoc.v:56708.7-56708.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:57635$3475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:57738$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57635$3475_Y + connect \Y $ternary$libresoc.v:57738$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57636.17-57652.4" + attribute \src "libresoc.v:57739.17-57755.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -98849,26 +99105,26 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56605.7-56605.20" - process $proc$libresoc.v:56605$3490 + attribute \src "libresoc.v:56708.7-56708.20" + process $proc$libresoc.v:56708$3506 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57653.3-57680.6" - process $proc$libresoc.v:57653$3476 + attribute \src "libresoc.v:57756.3-57783.6" + process $proc$libresoc.v:57756$3492 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57654.5-57654.29" + attribute \src "libresoc.v:57757.5-57757.29" switch \initial - attribute \src "libresoc.v:57654.9-57654.17" + attribute \src "libresoc.v:57757.9-57757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98904,18 +99160,18 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57681.3-57708.6" - process $proc$libresoc.v:57681$3477 + attribute \src "libresoc.v:57784.3-57811.6" + process $proc$libresoc.v:57784$3493 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57682.5-57682.29" + attribute \src "libresoc.v:57785.5-57785.29" switch \initial - attribute \src "libresoc.v:57682.9-57682.17" + attribute \src "libresoc.v:57785.9-57785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98951,18 +99207,18 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57709.3-57736.6" - process $proc$libresoc.v:57709$3478 + attribute \src "libresoc.v:57812.3-57839.6" + process $proc$libresoc.v:57812$3494 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57710.5-57710.29" + attribute \src "libresoc.v:57813.5-57813.29" switch \initial - attribute \src "libresoc.v:57710.9-57710.17" + attribute \src "libresoc.v:57813.9-57813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98998,18 +99254,18 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57737.3-57764.6" - process $proc$libresoc.v:57737$3479 + attribute \src "libresoc.v:57840.3-57867.6" + process $proc$libresoc.v:57840$3495 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57738.5-57738.29" + attribute \src "libresoc.v:57841.5-57841.29" switch \initial - attribute \src "libresoc.v:57738.9-57738.17" + attribute \src "libresoc.v:57841.9-57841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99045,18 +99301,18 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57765.3-57792.6" - process $proc$libresoc.v:57765$3480 + attribute \src "libresoc.v:57868.3-57895.6" + process $proc$libresoc.v:57868$3496 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57766.5-57766.29" + attribute \src "libresoc.v:57869.5-57869.29" switch \initial - attribute \src "libresoc.v:57766.9-57766.17" + attribute \src "libresoc.v:57869.9-57869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99092,18 +99348,18 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57793.3-57820.6" - process $proc$libresoc.v:57793$3481 + attribute \src "libresoc.v:57896.3-57923.6" + process $proc$libresoc.v:57896$3497 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57794.5-57794.29" + attribute \src "libresoc.v:57897.5-57897.29" switch \initial - attribute \src "libresoc.v:57794.9-57794.17" + attribute \src "libresoc.v:57897.9-57897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99139,18 +99395,18 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57821.3-57848.6" - process $proc$libresoc.v:57821$3482 + attribute \src "libresoc.v:57924.3-57951.6" + process $proc$libresoc.v:57924$3498 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57822.5-57822.29" + attribute \src "libresoc.v:57925.5-57925.29" switch \initial - attribute \src "libresoc.v:57822.9-57822.17" + attribute \src "libresoc.v:57925.9-57925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99186,18 +99442,18 @@ module \dec$145 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57849.3-57876.6" - process $proc$libresoc.v:57849$3483 + attribute \src "libresoc.v:57952.3-57979.6" + process $proc$libresoc.v:57952$3499 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57850.5-57850.29" + attribute \src "libresoc.v:57953.5-57953.29" switch \initial - attribute \src "libresoc.v:57850.9-57850.17" + attribute \src "libresoc.v:57953.9-57953.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99233,18 +99489,18 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57877.3-57904.6" - process $proc$libresoc.v:57877$3484 + attribute \src "libresoc.v:57980.3-58007.6" + process $proc$libresoc.v:57980$3500 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57878.5-57878.29" + attribute \src "libresoc.v:57981.5-57981.29" switch \initial - attribute \src "libresoc.v:57878.9-57878.17" + attribute \src "libresoc.v:57981.9-57981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99280,18 +99536,18 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57905.3-57932.6" - process $proc$libresoc.v:57905$3485 + attribute \src "libresoc.v:58008.3-58035.6" + process $proc$libresoc.v:58008$3501 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57906.5-57906.29" + attribute \src "libresoc.v:58009.5-58009.29" switch \initial - attribute \src "libresoc.v:57906.9-57906.17" + attribute \src "libresoc.v:58009.9-58009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99327,18 +99583,18 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:57933.3-57960.6" - process $proc$libresoc.v:57933$3486 + attribute \src "libresoc.v:58036.3-58063.6" + process $proc$libresoc.v:58036$3502 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57934.5-57934.29" + attribute \src "libresoc.v:58037.5-58037.29" switch \initial - attribute \src "libresoc.v:57934.9-57934.17" + attribute \src "libresoc.v:58037.9-58037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99374,18 +99630,18 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:57961.3-57988.6" - process $proc$libresoc.v:57961$3487 + attribute \src "libresoc.v:58064.3-58091.6" + process $proc$libresoc.v:58064$3503 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57962.5-57962.29" + attribute \src "libresoc.v:58065.5-58065.29" switch \initial - attribute \src "libresoc.v:57962.9-57962.17" + attribute \src "libresoc.v:58065.9-58065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99421,18 +99677,18 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:57989.3-58016.6" - process $proc$libresoc.v:57989$3488 + attribute \src "libresoc.v:58092.3-58119.6" + process $proc$libresoc.v:58092$3504 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57990.5-57990.29" + attribute \src "libresoc.v:58093.5-58093.29" switch \initial - attribute \src "libresoc.v:57990.9-57990.17" + attribute \src "libresoc.v:58093.9-58093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99468,18 +99724,18 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58017.3-58044.6" - process $proc$libresoc.v:58017$3489 + attribute \src "libresoc.v:58120.3-58147.6" + process $proc$libresoc.v:58120$3505 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58018.5-58018.29" + attribute \src "libresoc.v:58121.5-58121.29" switch \initial - attribute \src "libresoc.v:58018.9-58018.17" + attribute \src "libresoc.v:58121.9-58121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99515,7 +99771,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57635$3475_Y + connect \$1 $ternary$libresoc.v:57738$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -99853,284 +100109,284 @@ module \dec$145 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58385.1-59720.10" +attribute \src "libresoc.v:58488.1-59823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59344.3-59353.6" + attribute \src "libresoc.v:59447.3-59456.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59354.3-59363.6" + attribute \src "libresoc.v:59457.3-59466.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59324.3-59333.6" + attribute \src "libresoc.v:59427.3-59436.6" wire width 14 $0\SPR_function_unit[13:0] - attribute \src "libresoc.v:59334.3-59343.6" + attribute \src "libresoc.v:59437.3-59446.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59374.3-59383.6" + attribute \src "libresoc.v:59477.3-59486.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59364.3-59373.6" + attribute \src "libresoc.v:59467.3-59476.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58386.7-58386.20" + attribute \src "libresoc.v:58489.7-58489.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59344.3-59353.6" + attribute \src "libresoc.v:59447.3-59456.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59354.3-59363.6" + attribute \src "libresoc.v:59457.3-59466.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59324.3-59333.6" + attribute \src "libresoc.v:59427.3-59436.6" wire width 14 $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59334.3-59343.6" + attribute \src "libresoc.v:59437.3-59446.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59374.3-59383.6" + attribute \src "libresoc.v:59477.3-59486.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59364.3-59373.6" + attribute \src "libresoc.v:59467.3-59476.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59314.17-59314.211" - wire width 32 $ternary$libresoc.v:59314$3491_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:59417.17-59417.211" + wire width 32 $ternary$libresoc.v:59417$3507_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SPR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SPR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SPR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \SPR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 10 \SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 9 \SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100141,7 +100397,7 @@ module \dec$150 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100150,7 +100406,7 @@ module \dec$150 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100161,7 +100417,7 @@ module \dec$150 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100170,7 +100426,7 @@ module \dec$150 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -100187,7 +100443,7 @@ module \dec$150 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100264,17 +100520,17 @@ module \dec$150 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_SPR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -100291,7 +100547,7 @@ module \dec$150 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100368,458 +100624,458 @@ module \dec$150 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:58386.7-58386.15" + attribute \src "libresoc.v:58489.7-58489.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:59314$3491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:59417$3507 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59314$3491_Y + connect \Y $ternary$libresoc.v:59417$3507_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59315.13-59323.4" + attribute \src "libresoc.v:59418.13-59426.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -100829,26 +101085,26 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58386.7-58386.20" - process $proc$libresoc.v:58386$3498 + attribute \src "libresoc.v:58489.7-58489.20" + process $proc$libresoc.v:58489$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59324.3-59333.6" - process $proc$libresoc.v:59324$3492 + attribute \src "libresoc.v:59427.3-59436.6" + process $proc$libresoc.v:59427$3508 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59325.5-59325.29" + attribute \src "libresoc.v:59428.5-59428.29" switch \initial - attribute \src "libresoc.v:59325.9-59325.17" + attribute \src "libresoc.v:59428.9-59428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100860,18 +101116,18 @@ module \dec$150 sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59334.3-59343.6" - process $proc$libresoc.v:59334$3493 + attribute \src "libresoc.v:59437.3-59446.6" + process $proc$libresoc.v:59437$3509 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59335.5-59335.29" + attribute \src "libresoc.v:59438.5-59438.29" switch \initial - attribute \src "libresoc.v:59335.9-59335.17" + attribute \src "libresoc.v:59438.9-59438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100883,18 +101139,18 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59344.3-59353.6" - process $proc$libresoc.v:59344$3494 + attribute \src "libresoc.v:59447.3-59456.6" + process $proc$libresoc.v:59447$3510 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59345.5-59345.29" + attribute \src "libresoc.v:59448.5-59448.29" switch \initial - attribute \src "libresoc.v:59345.9-59345.17" + attribute \src "libresoc.v:59448.9-59448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100906,18 +101162,18 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59354.3-59363.6" - process $proc$libresoc.v:59354$3495 + attribute \src "libresoc.v:59457.3-59466.6" + process $proc$libresoc.v:59457$3511 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59355.5-59355.29" + attribute \src "libresoc.v:59458.5-59458.29" switch \initial - attribute \src "libresoc.v:59355.9-59355.17" + attribute \src "libresoc.v:59458.9-59458.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100929,18 +101185,18 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59364.3-59373.6" - process $proc$libresoc.v:59364$3496 + attribute \src "libresoc.v:59467.3-59476.6" + process $proc$libresoc.v:59467$3512 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59365.5-59365.29" + attribute \src "libresoc.v:59468.5-59468.29" switch \initial - attribute \src "libresoc.v:59365.9-59365.17" + attribute \src "libresoc.v:59468.9-59468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100952,18 +101208,18 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59374.3-59383.6" - process $proc$libresoc.v:59374$3497 + attribute \src "libresoc.v:59477.3-59486.6" + process $proc$libresoc.v:59477$3513 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59375.5-59375.29" + attribute \src "libresoc.v:59478.5-59478.29" switch \initial - attribute \src "libresoc.v:59375.9-59375.17" + attribute \src "libresoc.v:59478.9-59478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100975,7 +101231,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59314$3491_Y + connect \$1 $ternary$libresoc.v:59417$3507_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101313,170 +101569,170 @@ module \dec$150 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59724.1-61249.10" +attribute \src "libresoc.v:59827.1-61352.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60873.3-60882.6" + attribute \src "libresoc.v:60976.3-60985.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60883.3-60892.6" + attribute \src "libresoc.v:60986.3-60995.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60773.3-60782.6" + attribute \src "libresoc.v:60876.3-60885.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60803.3-60812.6" + attribute \src "libresoc.v:60906.3-60915.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60833.3-60842.6" + attribute \src "libresoc.v:60936.3-60945.6" wire width 14 $0\DIV_function_unit[13:0] - attribute \src "libresoc.v:60853.3-60862.6" + attribute \src "libresoc.v:60956.3-60965.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60863.3-60872.6" + attribute \src "libresoc.v:60966.3-60975.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60843.3-60852.6" + attribute \src "libresoc.v:60946.3-60955.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60783.3-60792.6" + attribute \src "libresoc.v:60886.3-60895.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60793.3-60802.6" + attribute \src "libresoc.v:60896.3-60905.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60813.3-60822.6" + attribute \src "libresoc.v:60916.3-60925.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60893.3-60902.6" + attribute \src "libresoc.v:60996.3-61005.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60903.3-60912.6" + attribute \src "libresoc.v:61006.3-61015.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60823.3-60832.6" + attribute \src "libresoc.v:60926.3-60935.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59725.7-59725.20" + attribute \src "libresoc.v:59828.7-59828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60873.3-60882.6" + attribute \src "libresoc.v:60976.3-60985.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60883.3-60892.6" + attribute \src "libresoc.v:60986.3-60995.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60773.3-60782.6" + attribute \src "libresoc.v:60876.3-60885.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60803.3-60812.6" + attribute \src "libresoc.v:60906.3-60915.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60833.3-60842.6" + attribute \src "libresoc.v:60936.3-60945.6" wire width 14 $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60853.3-60862.6" + attribute \src "libresoc.v:60956.3-60965.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60863.3-60872.6" + attribute \src "libresoc.v:60966.3-60975.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60843.3-60852.6" + attribute \src "libresoc.v:60946.3-60955.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60783.3-60792.6" + attribute \src "libresoc.v:60886.3-60895.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60793.3-60802.6" + attribute \src "libresoc.v:60896.3-60905.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60813.3-60822.6" + attribute \src "libresoc.v:60916.3-60925.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60893.3-60902.6" + attribute \src "libresoc.v:60996.3-61005.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60903.3-60912.6" + attribute \src "libresoc.v:61006.3-61015.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60823.3-60832.6" + attribute \src "libresoc.v:60926.3-60935.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60755.17-60755.211" - wire width 32 $ternary$libresoc.v:60755$3499_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:60858.17-60858.211" + wire width 32 $ternary$libresoc.v:60858$3515_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \DIV_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -101487,7 +101743,7 @@ module \dec$153 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -101496,15 +101752,15 @@ module \dec$153 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -101515,7 +101771,7 @@ module \dec$153 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -101524,15 +101780,15 @@ module \dec$153 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -101549,7 +101805,7 @@ module \dec$153 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -101557,7 +101813,7 @@ module \dec$153 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -101574,7 +101830,7 @@ module \dec$153 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -101651,13 +101907,13 @@ module \dec$153 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -101665,17 +101921,17 @@ module \dec$153 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -101692,7 +101948,7 @@ module \dec$153 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -101700,7 +101956,7 @@ module \dec$153 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -101717,7 +101973,7 @@ module \dec$153 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -101794,13 +102050,13 @@ module \dec$153 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -101808,604 +102064,604 @@ module \dec$153 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:59725.7-59725.15" + attribute \src "libresoc.v:59828.7-59828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:60755$3499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:60858$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60755$3499_Y + connect \Y $ternary$libresoc.v:60858$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60756.13-60772.4" + attribute \src "libresoc.v:60859.13-60875.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102423,26 +102679,26 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59725.7-59725.20" - process $proc$libresoc.v:59725$3514 + attribute \src "libresoc.v:59828.7-59828.20" + process $proc$libresoc.v:59828$3530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60773.3-60782.6" - process $proc$libresoc.v:60773$3500 + attribute \src "libresoc.v:60876.3-60885.6" + process $proc$libresoc.v:60876$3516 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60774.5-60774.29" + attribute \src "libresoc.v:60877.5-60877.29" switch \initial - attribute \src "libresoc.v:60774.9-60774.17" + attribute \src "libresoc.v:60877.9-60877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102454,18 +102710,18 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60783.3-60792.6" - process $proc$libresoc.v:60783$3501 + attribute \src "libresoc.v:60886.3-60895.6" + process $proc$libresoc.v:60886$3517 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60784.5-60784.29" + attribute \src "libresoc.v:60887.5-60887.29" switch \initial - attribute \src "libresoc.v:60784.9-60784.17" + attribute \src "libresoc.v:60887.9-60887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102477,18 +102733,18 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60793.3-60802.6" - process $proc$libresoc.v:60793$3502 + attribute \src "libresoc.v:60896.3-60905.6" + process $proc$libresoc.v:60896$3518 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60794.5-60794.29" + attribute \src "libresoc.v:60897.5-60897.29" switch \initial - attribute \src "libresoc.v:60794.9-60794.17" + attribute \src "libresoc.v:60897.9-60897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102500,18 +102756,18 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60803.3-60812.6" - process $proc$libresoc.v:60803$3503 + attribute \src "libresoc.v:60906.3-60915.6" + process $proc$libresoc.v:60906$3519 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60804.5-60804.29" + attribute \src "libresoc.v:60907.5-60907.29" switch \initial - attribute \src "libresoc.v:60804.9-60804.17" + attribute \src "libresoc.v:60907.9-60907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102523,18 +102779,18 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60813.3-60822.6" - process $proc$libresoc.v:60813$3504 + attribute \src "libresoc.v:60916.3-60925.6" + process $proc$libresoc.v:60916$3520 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60814.5-60814.29" + attribute \src "libresoc.v:60917.5-60917.29" switch \initial - attribute \src "libresoc.v:60814.9-60814.17" + attribute \src "libresoc.v:60917.9-60917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102546,18 +102802,18 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60823.3-60832.6" - process $proc$libresoc.v:60823$3505 + attribute \src "libresoc.v:60926.3-60935.6" + process $proc$libresoc.v:60926$3521 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60824.5-60824.29" + attribute \src "libresoc.v:60927.5-60927.29" switch \initial - attribute \src "libresoc.v:60824.9-60824.17" + attribute \src "libresoc.v:60927.9-60927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102569,18 +102825,18 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60833.3-60842.6" - process $proc$libresoc.v:60833$3506 + attribute \src "libresoc.v:60936.3-60945.6" + process $proc$libresoc.v:60936$3522 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60834.5-60834.29" + attribute \src "libresoc.v:60937.5-60937.29" switch \initial - attribute \src "libresoc.v:60834.9-60834.17" + attribute \src "libresoc.v:60937.9-60937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102592,18 +102848,18 @@ module \dec$153 sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60843.3-60852.6" - process $proc$libresoc.v:60843$3507 + attribute \src "libresoc.v:60946.3-60955.6" + process $proc$libresoc.v:60946$3523 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60844.5-60844.29" + attribute \src "libresoc.v:60947.5-60947.29" switch \initial - attribute \src "libresoc.v:60844.9-60844.17" + attribute \src "libresoc.v:60947.9-60947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102615,18 +102871,18 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60853.3-60862.6" - process $proc$libresoc.v:60853$3508 + attribute \src "libresoc.v:60956.3-60965.6" + process $proc$libresoc.v:60956$3524 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60854.5-60854.29" + attribute \src "libresoc.v:60957.5-60957.29" switch \initial - attribute \src "libresoc.v:60854.9-60854.17" + attribute \src "libresoc.v:60957.9-60957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102638,18 +102894,18 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60863.3-60872.6" - process $proc$libresoc.v:60863$3509 + attribute \src "libresoc.v:60966.3-60975.6" + process $proc$libresoc.v:60966$3525 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60864.5-60864.29" + attribute \src "libresoc.v:60967.5-60967.29" switch \initial - attribute \src "libresoc.v:60864.9-60864.17" + attribute \src "libresoc.v:60967.9-60967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102661,18 +102917,18 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60873.3-60882.6" - process $proc$libresoc.v:60873$3510 + attribute \src "libresoc.v:60976.3-60985.6" + process $proc$libresoc.v:60976$3526 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60874.5-60874.29" + attribute \src "libresoc.v:60977.5-60977.29" switch \initial - attribute \src "libresoc.v:60874.9-60874.17" + attribute \src "libresoc.v:60977.9-60977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102684,18 +102940,18 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60883.3-60892.6" - process $proc$libresoc.v:60883$3511 + attribute \src "libresoc.v:60986.3-60995.6" + process $proc$libresoc.v:60986$3527 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60884.5-60884.29" + attribute \src "libresoc.v:60987.5-60987.29" switch \initial - attribute \src "libresoc.v:60884.9-60884.17" + attribute \src "libresoc.v:60987.9-60987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102707,18 +102963,18 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60893.3-60902.6" - process $proc$libresoc.v:60893$3512 + attribute \src "libresoc.v:60996.3-61005.6" + process $proc$libresoc.v:60996$3528 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60894.5-60894.29" + attribute \src "libresoc.v:60997.5-60997.29" switch \initial - attribute \src "libresoc.v:60894.9-60894.17" + attribute \src "libresoc.v:60997.9-60997.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102730,18 +102986,18 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60903.3-60912.6" - process $proc$libresoc.v:60903$3513 + attribute \src "libresoc.v:61006.3-61015.6" + process $proc$libresoc.v:61006$3529 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60904.5-60904.29" + attribute \src "libresoc.v:61007.5-61007.29" switch \initial - attribute \src "libresoc.v:60904.9-60904.17" + attribute \src "libresoc.v:61007.9-61007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102753,7 +103009,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60755$3499_Y + connect \$1 $ternary$libresoc.v:60858$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103091,272 +103347,272 @@ module \dec$153 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61253.1-62674.10" +attribute \src "libresoc.v:61356.1-62777.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:62273.3-62285.6" + attribute \src "libresoc.v:62376.3-62388.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62286.3-62298.6" + attribute \src "libresoc.v:62389.3-62401.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62234.3-62246.6" + attribute \src "libresoc.v:62337.3-62349.6" wire width 14 $0\MUL_function_unit[13:0] - attribute \src "libresoc.v:62260.3-62272.6" + attribute \src "libresoc.v:62363.3-62375.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62247.3-62259.6" + attribute \src "libresoc.v:62350.3-62362.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62312.3-62324.6" + attribute \src "libresoc.v:62415.3-62427.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62299.3-62311.6" + attribute \src "libresoc.v:62402.3-62414.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62325.3-62337.6" + attribute \src "libresoc.v:62428.3-62440.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61254.7-61254.20" + attribute \src "libresoc.v:61357.7-61357.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62273.3-62285.6" + attribute \src "libresoc.v:62376.3-62388.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62286.3-62298.6" + attribute \src "libresoc.v:62389.3-62401.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62234.3-62246.6" + attribute \src "libresoc.v:62337.3-62349.6" wire width 14 $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62260.3-62272.6" + attribute \src "libresoc.v:62363.3-62375.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62247.3-62259.6" + attribute \src "libresoc.v:62350.3-62362.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62312.3-62324.6" + attribute \src "libresoc.v:62415.3-62427.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62299.3-62311.6" + attribute \src "libresoc.v:62402.3-62414.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62325.3-62337.6" + attribute \src "libresoc.v:62428.3-62440.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62222.17-62222.211" - wire width 32 $ternary$libresoc.v:62222$3515_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:62325.17-62325.211" + wire width 32 $ternary$libresoc.v:62325$3531_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 18 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \MUL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \MUL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \MUL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \MUL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 15 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \MUL_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 16 \MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 13 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 11 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -103367,7 +103623,7 @@ module \dec$158 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103376,7 +103632,7 @@ module \dec$158 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -103387,7 +103643,7 @@ module \dec$158 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103396,7 +103652,7 @@ module \dec$158 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -103413,7 +103669,7 @@ module \dec$158 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103430,7 +103686,7 @@ module \dec$158 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103507,19 +103763,19 @@ module \dec$158 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -103536,7 +103792,7 @@ module \dec$158 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103553,7 +103809,7 @@ module \dec$158 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103630,480 +103886,480 @@ module \dec$158 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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\XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:61254.7-61254.15" + attribute \src "libresoc.v:61357.7-61357.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:62222$3515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:62325$3531 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62222$3515_Y + connect \Y $ternary$libresoc.v:62325$3531_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62223.13-62233.4" + attribute \src "libresoc.v:62326.13-62336.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104115,26 +104371,26 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61254.7-61254.20" - process $proc$libresoc.v:61254$3524 + attribute \src "libresoc.v:61357.7-61357.20" + process $proc$libresoc.v:61357$3540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62234.3-62246.6" - process $proc$libresoc.v:62234$3516 + attribute \src "libresoc.v:62337.3-62349.6" + process $proc$libresoc.v:62337$3532 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62235.5-62235.29" + attribute \src "libresoc.v:62338.5-62338.29" switch \initial - attribute \src "libresoc.v:62235.9-62235.17" + attribute \src "libresoc.v:62338.9-62338.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104150,18 +104406,18 @@ module \dec$158 sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:62247.3-62259.6" - process $proc$libresoc.v:62247$3517 + attribute \src "libresoc.v:62350.3-62362.6" + process $proc$libresoc.v:62350$3533 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62248.5-62248.29" + attribute \src "libresoc.v:62351.5-62351.29" switch \initial - attribute \src "libresoc.v:62248.9-62248.17" + attribute \src "libresoc.v:62351.9-62351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104177,18 +104433,18 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62260.3-62272.6" - process $proc$libresoc.v:62260$3518 + attribute \src "libresoc.v:62363.3-62375.6" + process $proc$libresoc.v:62363$3534 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62261.5-62261.29" + attribute \src "libresoc.v:62364.5-62364.29" switch \initial - attribute \src "libresoc.v:62261.9-62261.17" + attribute \src "libresoc.v:62364.9-62364.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104204,18 +104460,18 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62273.3-62285.6" - process $proc$libresoc.v:62273$3519 + attribute \src "libresoc.v:62376.3-62388.6" + process $proc$libresoc.v:62376$3535 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62274.5-62274.29" + attribute \src "libresoc.v:62377.5-62377.29" switch \initial - attribute \src "libresoc.v:62274.9-62274.17" + attribute \src "libresoc.v:62377.9-62377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104231,18 +104487,18 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62286.3-62298.6" - process $proc$libresoc.v:62286$3520 + attribute \src "libresoc.v:62389.3-62401.6" + process $proc$libresoc.v:62389$3536 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62287.5-62287.29" + attribute \src "libresoc.v:62390.5-62390.29" switch \initial - attribute \src "libresoc.v:62287.9-62287.17" + attribute \src "libresoc.v:62390.9-62390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104258,18 +104514,18 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62299.3-62311.6" - process $proc$libresoc.v:62299$3521 + attribute \src "libresoc.v:62402.3-62414.6" + process $proc$libresoc.v:62402$3537 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62300.5-62300.29" + attribute \src "libresoc.v:62403.5-62403.29" switch \initial - attribute \src "libresoc.v:62300.9-62300.17" + attribute \src "libresoc.v:62403.9-62403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104285,18 +104541,18 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62312.3-62324.6" - process $proc$libresoc.v:62312$3522 + attribute \src "libresoc.v:62415.3-62427.6" + process $proc$libresoc.v:62415$3538 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62313.5-62313.29" + attribute \src "libresoc.v:62416.5-62416.29" switch \initial - attribute \src "libresoc.v:62313.9-62313.17" + attribute \src "libresoc.v:62416.9-62416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104312,18 +104568,18 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62325.3-62337.6" - process $proc$libresoc.v:62325$3523 + attribute \src "libresoc.v:62428.3-62440.6" + process $proc$libresoc.v:62428$3539 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62326.5-62326.29" + attribute \src "libresoc.v:62429.5-62429.29" switch \initial - attribute \src "libresoc.v:62326.9-62326.17" + attribute \src "libresoc.v:62429.9-62429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104339,7 +104595,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62222$3515_Y + connect \$1 $ternary$libresoc.v:62325$3531_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104677,304 +104933,304 @@ module \dec$158 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62678.1-64432.10" +attribute \src "libresoc.v:62781.1-64535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:64007.3-64028.6" + attribute \src "libresoc.v:64110.3-64131.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64029.3-64050.6" + attribute \src "libresoc.v:64132.3-64153.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64073.3-64094.6" + attribute \src "libresoc.v:64176.3-64197.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63875.3-63896.6" + attribute \src "libresoc.v:63978.3-63999.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63941.3-63962.6" + attribute \src "libresoc.v:64044.3-64065.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63985.3-64006.6" + attribute \src "libresoc.v:64088.3-64109.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63963.3-63984.6" + attribute \src "libresoc.v:64066.3-64087.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63853.3-63874.6" + attribute \src "libresoc.v:63956.3-63977.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63897.3-63918.6" + attribute \src "libresoc.v:64000.3-64021.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64051.3-64072.6" + attribute \src "libresoc.v:64154.3-64175.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63919.3-63940.6" + attribute \src "libresoc.v:64022.3-64043.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62679.7-62679.20" + attribute \src "libresoc.v:62782.7-62782.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64007.3-64028.6" + attribute \src "libresoc.v:64110.3-64131.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64029.3-64050.6" + attribute \src "libresoc.v:64132.3-64153.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64073.3-64094.6" + attribute \src "libresoc.v:64176.3-64197.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63875.3-63896.6" + attribute \src "libresoc.v:63978.3-63999.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63941.3-63962.6" + attribute \src "libresoc.v:64044.3-64065.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63985.3-64006.6" + attribute \src "libresoc.v:64088.3-64109.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63963.3-63984.6" + attribute \src "libresoc.v:64066.3-64087.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63853.3-63874.6" + attribute \src "libresoc.v:63956.3-63977.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63897.3-63918.6" + attribute \src "libresoc.v:64000.3-64021.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64051.3-64072.6" + attribute \src "libresoc.v:64154.3-64175.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63919.3-63940.6" + attribute \src "libresoc.v:64022.3-64043.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63824.17-63824.211" - wire width 32 $ternary$libresoc.v:63824$3525_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:63927.17-63927.211" + wire width 32 $ternary$libresoc.v:63927$3541_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 22 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SHIFT_ROT_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SHIFT_ROT_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 23 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 19 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 21 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SHIFT_ROT_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 20 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 15 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 16 \SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -104985,7 +105241,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -104994,15 +105250,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 11 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \SHIFT_ROT_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105013,7 +105269,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105022,15 +105278,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105047,7 +105303,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105064,7 +105320,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105141,21 +105397,21 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec30_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105166,7 +105422,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105175,15 +105431,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105200,7 +105456,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105217,7 +105473,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105294,21 +105550,21 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105325,7 +105581,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105342,7 +105598,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105419,462 +105675,462 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 18 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:62679.7-62679.15" + attribute \src "libresoc.v:62782.7-62782.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:63824$3525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:63927$3541 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63824$3525_Y + connect \Y $ternary$libresoc.v:63927$3541_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63825.19-63838.4" + attribute \src "libresoc.v:63928.19-63941.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -105890,7 +106146,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63839.19-63852.4" + attribute \src "libresoc.v:63942.19-63955.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -105905,26 +106161,26 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62679.7-62679.20" - process $proc$libresoc.v:62679$3537 + attribute \src "libresoc.v:62782.7-62782.20" + process $proc$libresoc.v:62782$3553 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63853.3-63874.6" - process $proc$libresoc.v:63853$3526 + attribute \src "libresoc.v:63956.3-63977.6" + process $proc$libresoc.v:63956$3542 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63854.5-63854.29" + attribute \src "libresoc.v:63957.5-63957.29" switch \initial - attribute \src "libresoc.v:63854.9-63854.17" + attribute \src "libresoc.v:63957.9-63957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105952,18 +106208,18 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63875.3-63896.6" - process $proc$libresoc.v:63875$3527 + attribute \src "libresoc.v:63978.3-63999.6" + process $proc$libresoc.v:63978$3543 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63876.5-63876.29" + attribute \src "libresoc.v:63979.5-63979.29" switch \initial - attribute \src "libresoc.v:63876.9-63876.17" + attribute \src "libresoc.v:63979.9-63979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105991,18 +106247,18 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63897.3-63918.6" - process $proc$libresoc.v:63897$3528 + attribute \src "libresoc.v:64000.3-64021.6" + process $proc$libresoc.v:64000$3544 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63898.5-63898.29" + attribute \src "libresoc.v:64001.5-64001.29" switch \initial - attribute \src "libresoc.v:63898.9-63898.17" + attribute \src "libresoc.v:64001.9-64001.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106030,18 +106286,18 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63919.3-63940.6" - process $proc$libresoc.v:63919$3529 + attribute \src "libresoc.v:64022.3-64043.6" + process $proc$libresoc.v:64022$3545 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63920.5-63920.29" + attribute \src "libresoc.v:64023.5-64023.29" switch \initial - attribute \src "libresoc.v:63920.9-63920.17" + attribute \src "libresoc.v:64023.9-64023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106069,18 +106325,18 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:63941.3-63962.6" - process $proc$libresoc.v:63941$3530 + attribute \src "libresoc.v:64044.3-64065.6" + process $proc$libresoc.v:64044$3546 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63942.5-63942.29" + attribute \src "libresoc.v:64045.5-64045.29" switch \initial - attribute \src "libresoc.v:63942.9-63942.17" + attribute \src "libresoc.v:64045.9-64045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106108,18 +106364,18 @@ module \dec$162 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:63963.3-63984.6" - process $proc$libresoc.v:63963$3531 + attribute \src "libresoc.v:64066.3-64087.6" + process $proc$libresoc.v:64066$3547 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63964.5-63964.29" + attribute \src "libresoc.v:64067.5-64067.29" switch \initial - attribute \src "libresoc.v:63964.9-63964.17" + attribute \src "libresoc.v:64067.9-64067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106147,18 +106403,18 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:63985.3-64006.6" - process $proc$libresoc.v:63985$3532 + attribute \src "libresoc.v:64088.3-64109.6" + process $proc$libresoc.v:64088$3548 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63986.5-63986.29" + attribute \src "libresoc.v:64089.5-64089.29" switch \initial - attribute \src "libresoc.v:63986.9-63986.17" + attribute \src "libresoc.v:64089.9-64089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106186,18 +106442,18 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:64007.3-64028.6" - process $proc$libresoc.v:64007$3533 + attribute \src "libresoc.v:64110.3-64131.6" + process $proc$libresoc.v:64110$3549 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64008.5-64008.29" + attribute \src "libresoc.v:64111.5-64111.29" switch \initial - attribute \src "libresoc.v:64008.9-64008.17" + attribute \src "libresoc.v:64111.9-64111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106225,18 +106481,18 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64029.3-64050.6" - process $proc$libresoc.v:64029$3534 + attribute \src "libresoc.v:64132.3-64153.6" + process $proc$libresoc.v:64132$3550 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64030.5-64030.29" + attribute \src "libresoc.v:64133.5-64133.29" switch \initial - attribute \src "libresoc.v:64030.9-64030.17" + attribute \src "libresoc.v:64133.9-64133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106264,18 +106520,18 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64051.3-64072.6" - process $proc$libresoc.v:64051$3535 + attribute \src "libresoc.v:64154.3-64175.6" + process $proc$libresoc.v:64154$3551 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64052.5-64052.29" + attribute \src "libresoc.v:64155.5-64155.29" switch \initial - attribute \src "libresoc.v:64052.9-64052.17" + attribute \src "libresoc.v:64155.9-64155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106303,18 +106559,18 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64073.3-64094.6" - process $proc$libresoc.v:64073$3536 + attribute \src "libresoc.v:64176.3-64197.6" + process $proc$libresoc.v:64176$3552 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64074.5-64074.29" + attribute \src "libresoc.v:64177.5-64177.29" switch \initial - attribute \src "libresoc.v:64074.9-64074.17" + attribute \src "libresoc.v:64177.9-64177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106342,7 +106598,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63824$3525_Y + connect \$1 $ternary$libresoc.v:63927$3541_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106681,258 +106937,258 @@ module \dec$162 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64436.1-66945.10" +attribute \src "libresoc.v:64539.1-67048.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:66027.3-66084.6" + attribute \src "libresoc.v:66130.3-66187.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66491.3-66548.6" + attribute \src "libresoc.v:66594.3-66651.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66549.3-66606.6" + attribute \src "libresoc.v:66652.3-66709.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66259.3-66316.6" + attribute \src "libresoc.v:66362.3-66419.6" wire width 14 $0\LDST_function_unit[13:0] - attribute \src "libresoc.v:66375.3-66432.6" + attribute \src "libresoc.v:66478.3-66535.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66433.3-66490.6" + attribute \src "libresoc.v:66536.3-66593.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66317.3-66374.6" + attribute \src "libresoc.v:66420.3-66477.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66143.3-66200.6" + attribute \src "libresoc.v:66246.3-66303.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65853.3-65910.6" + attribute \src "libresoc.v:65956.3-66013.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65969.3-66026.6" + attribute \src "libresoc.v:66072.3-66129.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66201.3-66258.6" + attribute \src "libresoc.v:66304.3-66361.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66085.3-66142.6" + attribute \src "libresoc.v:66188.3-66245.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65911.3-65968.6" + attribute \src "libresoc.v:66014.3-66071.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64437.7-64437.20" + attribute \src "libresoc.v:64540.7-64540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66027.3-66084.6" + attribute \src "libresoc.v:66130.3-66187.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66491.3-66548.6" + attribute \src "libresoc.v:66594.3-66651.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66549.3-66606.6" + attribute \src "libresoc.v:66652.3-66709.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66259.3-66316.6" + attribute \src "libresoc.v:66362.3-66419.6" wire width 14 $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66375.3-66432.6" + attribute \src "libresoc.v:66478.3-66535.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66433.3-66490.6" + attribute \src "libresoc.v:66536.3-66593.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66317.3-66374.6" + attribute \src "libresoc.v:66420.3-66477.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66143.3-66200.6" + attribute \src "libresoc.v:66246.3-66303.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65853.3-65910.6" + attribute \src "libresoc.v:65956.3-66013.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65969.3-66026.6" + attribute \src "libresoc.v:66072.3-66129.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66201.3-66258.6" + attribute \src "libresoc.v:66304.3-66361.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66085.3-66142.6" + attribute \src "libresoc.v:66188.3-66245.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65911.3-65968.6" + attribute \src "libresoc.v:66014.3-66071.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65804.17-65804.211" - wire width 32 $ternary$libresoc.v:65804$3538_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:65907.17-65907.211" + wire width 32 $ternary$libresoc.v:65907$3554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 24 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LDST_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LDST_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LDST_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LDST_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 21 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LDST_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 16 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 22 \LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 17 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106943,7 +107199,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106952,9 +107208,9 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106965,7 +107221,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106974,7 +107230,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -106991,7 +107247,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -106999,7 +107255,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107016,7 +107272,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107093,9 +107349,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107103,28 +107359,28 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -107135,7 +107391,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -107144,7 +107400,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107161,7 +107417,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107169,7 +107425,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107186,7 +107442,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107263,9 +107519,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec58_LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107273,28 +107529,28 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -107305,7 +107561,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -107314,7 +107570,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107331,7 +107587,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107339,7 +107595,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107356,7 +107612,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107433,9 +107689,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec62_LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107443,26 +107699,26 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107479,7 +107735,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107487,7 +107743,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107504,7 +107760,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107581,9 +107837,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107591,523 +107847,523 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:64437.7-64437.15" + attribute \src "libresoc.v:64540.7-64540.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 26 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:65804$3538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:65907$3554 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65804$3538_Y + connect \Y $ternary$libresoc.v:65907$3554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65805.14-65820.4" + attribute \src "libresoc.v:65908.14-65923.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108125,7 +108381,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65821.14-65836.4" + attribute \src "libresoc.v:65924.14-65939.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108143,7 +108399,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65837.14-65852.4" + attribute \src "libresoc.v:65940.14-65955.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108160,26 +108416,26 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64437.7-64437.20" - process $proc$libresoc.v:64437$3552 + attribute \src "libresoc.v:64540.7-64540.20" + process $proc$libresoc.v:64540$3568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65853.3-65910.6" - process $proc$libresoc.v:65853$3539 + attribute \src "libresoc.v:65956.3-66013.6" + process $proc$libresoc.v:65956$3555 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65854.5-65854.29" + attribute \src "libresoc.v:65957.5-65957.29" switch \initial - attribute \src "libresoc.v:65854.9-65854.17" + attribute \src "libresoc.v:65957.9-65957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108255,18 +108511,18 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65911.3-65968.6" - process $proc$libresoc.v:65911$3540 + attribute \src "libresoc.v:66014.3-66071.6" + process $proc$libresoc.v:66014$3556 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65912.5-65912.29" + attribute \src "libresoc.v:66015.5-66015.29" switch \initial - attribute \src "libresoc.v:65912.9-65912.17" + attribute \src "libresoc.v:66015.9-66015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108342,18 +108598,18 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:65969.3-66026.6" - process $proc$libresoc.v:65969$3541 + attribute \src "libresoc.v:66072.3-66129.6" + process $proc$libresoc.v:66072$3557 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65970.5-65970.29" + attribute \src "libresoc.v:66073.5-66073.29" switch \initial - attribute \src "libresoc.v:65970.9-65970.17" + attribute \src "libresoc.v:66073.9-66073.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108429,18 +108685,18 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66027.3-66084.6" - process $proc$libresoc.v:66027$3542 + attribute \src "libresoc.v:66130.3-66187.6" + process $proc$libresoc.v:66130$3558 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66028.5-66028.29" + attribute \src "libresoc.v:66131.5-66131.29" switch \initial - attribute \src "libresoc.v:66028.9-66028.17" + attribute \src "libresoc.v:66131.9-66131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108516,18 +108772,18 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66085.3-66142.6" - process $proc$libresoc.v:66085$3543 + attribute \src "libresoc.v:66188.3-66245.6" + process $proc$libresoc.v:66188$3559 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66086.5-66086.29" + attribute \src "libresoc.v:66189.5-66189.29" switch \initial - attribute \src "libresoc.v:66086.9-66086.17" + attribute \src "libresoc.v:66189.9-66189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108603,18 +108859,18 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66143.3-66200.6" - process $proc$libresoc.v:66143$3544 + attribute \src "libresoc.v:66246.3-66303.6" + process $proc$libresoc.v:66246$3560 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66144.5-66144.29" + attribute \src "libresoc.v:66247.5-66247.29" switch \initial - attribute \src "libresoc.v:66144.9-66144.17" + attribute \src "libresoc.v:66247.9-66247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108690,18 +108946,18 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66201.3-66258.6" - process $proc$libresoc.v:66201$3545 + attribute \src "libresoc.v:66304.3-66361.6" + process $proc$libresoc.v:66304$3561 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66202.5-66202.29" + attribute \src "libresoc.v:66305.5-66305.29" switch \initial - attribute \src "libresoc.v:66202.9-66202.17" + attribute \src "libresoc.v:66305.9-66305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108777,18 +109033,18 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66259.3-66316.6" - process $proc$libresoc.v:66259$3546 + attribute \src "libresoc.v:66362.3-66419.6" + process $proc$libresoc.v:66362$3562 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66260.5-66260.29" + attribute \src "libresoc.v:66363.5-66363.29" switch \initial - attribute \src "libresoc.v:66260.9-66260.17" + attribute \src "libresoc.v:66363.9-66363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108864,18 +109120,18 @@ module \dec$166 sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:66317.3-66374.6" - process $proc$libresoc.v:66317$3547 + attribute \src "libresoc.v:66420.3-66477.6" + process $proc$libresoc.v:66420$3563 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66318.5-66318.29" + attribute \src "libresoc.v:66421.5-66421.29" switch \initial - attribute \src "libresoc.v:66318.9-66318.17" + attribute \src "libresoc.v:66421.9-66421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108951,18 +109207,18 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66375.3-66432.6" - process $proc$libresoc.v:66375$3548 + attribute \src "libresoc.v:66478.3-66535.6" + process $proc$libresoc.v:66478$3564 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66376.5-66376.29" + attribute \src "libresoc.v:66479.5-66479.29" switch \initial - attribute \src "libresoc.v:66376.9-66376.17" + attribute \src "libresoc.v:66479.9-66479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109038,18 +109294,18 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66433.3-66490.6" - process $proc$libresoc.v:66433$3549 + attribute \src "libresoc.v:66536.3-66593.6" + process $proc$libresoc.v:66536$3565 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66434.5-66434.29" + attribute \src "libresoc.v:66537.5-66537.29" switch \initial - attribute \src "libresoc.v:66434.9-66434.17" + attribute \src "libresoc.v:66537.9-66537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109125,18 +109381,18 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66491.3-66548.6" - process $proc$libresoc.v:66491$3550 + attribute \src "libresoc.v:66594.3-66651.6" + process $proc$libresoc.v:66594$3566 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66492.5-66492.29" + attribute \src "libresoc.v:66595.5-66595.29" switch \initial - attribute \src "libresoc.v:66492.9-66492.17" + attribute \src "libresoc.v:66595.9-66595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109212,18 +109468,18 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66549.3-66606.6" - process $proc$libresoc.v:66549$3551 + attribute \src "libresoc.v:66652.3-66709.6" + process $proc$libresoc.v:66652$3567 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66550.5-66550.29" + attribute \src "libresoc.v:66653.5-66653.29" switch \initial - attribute \src "libresoc.v:66550.9-66550.17" + attribute \src "libresoc.v:66653.9-66653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109299,7 +109555,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65804$3538_Y + connect \$1 $ternary$libresoc.v:65907$3554_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109639,890 +109895,896 @@ module \dec$166 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:66949.1-74952.10" +attribute \src "libresoc.v:67052.1-75269.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $0\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $0\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:66950.7-66950.20" + attribute \src "libresoc.v:67053.7-67053.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $0\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $0\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $0\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $1\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $1\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $1\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $1\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $1\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $2\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $2\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $2\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $2\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $2\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69762.17-69762.211" - wire width 32 $ternary$libresoc.v:69762$3553_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:69928.17-69928.211" + wire width 32 $ternary$libresoc.v:69928$3569_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 26 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 25 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 31 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 30 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 29 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 27 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 output 28 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 21 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 22 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 17 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 36 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110533,7 +110795,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110542,31 +110804,31 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec19_dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110577,7 +110839,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110586,15 +110848,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110627,7 +110889,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -110644,7 +110906,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110652,7 +110914,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110669,13 +110931,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110752,13 +111014,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec19_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110766,9 +111028,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -110776,21 +111038,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110799,7 +111061,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110808,7 +111070,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110817,7 +111079,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110826,7 +111088,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110835,7 +111097,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110844,32 +111106,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec19_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec22_dec22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110880,7 +111151,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110889,15 +111160,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110930,7 +111201,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec22_dec22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -110947,7 +111218,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec22_dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110955,7 +111226,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110972,13 +111243,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec22_dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111055,13 +111326,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec22_dec22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111069,9 +111340,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec22_dec22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111079,21 +111350,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111102,7 +111373,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111111,7 +111382,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111120,7 +111391,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111129,7 +111400,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111138,7 +111409,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111147,32 +111418,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec22_dec22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec22_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec30_dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111183,7 +111463,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111192,15 +111472,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111233,7 +111513,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111250,7 +111530,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111258,7 +111538,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111275,13 +111555,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec30_dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111358,13 +111638,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec30_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111372,9 +111652,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec30_dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111382,21 +111662,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111405,7 +111685,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111414,7 +111694,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111423,7 +111703,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111432,7 +111712,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111441,7 +111721,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111450,32 +111730,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec30_dec30_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec30_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111486,7 +111775,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111495,15 +111784,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111536,7 +111825,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111553,7 +111842,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111561,7 +111850,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111578,13 +111867,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111661,13 +111950,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111675,9 +111964,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111685,21 +111974,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111708,7 +111997,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111717,7 +112006,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111726,7 +112015,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111735,7 +112024,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111744,7 +112033,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111753,32 +112042,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec31_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec58_dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111789,7 +112087,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111798,15 +112096,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111839,7 +112137,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111856,7 +112154,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec58_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111864,7 +112162,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111881,13 +112179,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec58_dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111964,13 +112262,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec58_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111978,9 +112276,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec58_dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111988,21 +112286,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112011,7 +112309,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112020,7 +112318,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112029,7 +112327,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112038,7 +112336,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112047,7 +112345,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112056,32 +112354,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec58_dec58_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec58_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec62_dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -112092,7 +112399,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -112101,15 +112408,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -112142,7 +112449,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -112159,7 +112466,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec62_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -112167,7 +112474,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -112184,13 +112491,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec62_dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112267,13 +112574,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec62_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -112281,9 +112588,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec62_dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -112291,21 +112598,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112314,7 +112621,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112323,7 +112630,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112332,7 +112639,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112341,7 +112648,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112350,7 +112657,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112359,16 +112666,25 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec62_dec62_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec62_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -112401,7 +112717,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -112418,7 +112734,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -112426,7 +112742,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -112443,15 +112759,15 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 14 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:66950.7-66950.15" + attribute \src "libresoc.v:67053.7-67053.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112528,13 +112844,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -112542,15 +112858,15 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -112558,25 +112874,25 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \sh attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112585,7 +112901,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112594,7 +112910,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112603,7 +112919,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112612,7 +112928,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112621,7 +112937,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112630,25 +112946,34 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:69762$3553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:69928$3569 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69762$3553_Y + connect \Y $ternary$libresoc.v:69928$3569_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69763.9-69797.4" + attribute \src "libresoc.v:69929.9-69964.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -112681,11 +113006,12 @@ module \dec$171 connect \dec19_sv_in2 \dec19_dec19_sv_in2 connect \dec19_sv_in3 \dec19_dec19_sv_in3 connect \dec19_sv_out \dec19_dec19_sv_out + connect \dec19_sv_out2 \dec19_dec19_sv_out2 connect \dec19_upd \dec19_dec19_upd connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69798.9-69832.4" + attribute \src "libresoc.v:69965.9-70000.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype @@ -112718,11 +113044,12 @@ module \dec$171 connect \dec22_sv_in2 \dec22_dec22_sv_in2 connect \dec22_sv_in3 \dec22_dec22_sv_in3 connect \dec22_sv_out \dec22_dec22_sv_out + connect \dec22_sv_out2 \dec22_dec22_sv_out2 connect \dec22_upd \dec22_dec22_upd connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69833.9-69867.4" + attribute \src "libresoc.v:70001.9-70036.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -112755,11 +113082,12 @@ module \dec$171 connect \dec30_sv_in2 \dec30_dec30_sv_in2 connect \dec30_sv_in3 \dec30_dec30_sv_in3 connect \dec30_sv_out \dec30_dec30_sv_out + connect \dec30_sv_out2 \dec30_dec30_sv_out2 connect \dec30_upd \dec30_dec30_upd connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69868.9-69902.4" + attribute \src "libresoc.v:70037.9-70072.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -112792,11 +113120,12 @@ module \dec$171 connect \dec31_sv_in2 \dec31_dec31_sv_in2 connect \dec31_sv_in3 \dec31_dec31_sv_in3 connect \dec31_sv_out \dec31_dec31_sv_out + connect \dec31_sv_out2 \dec31_dec31_sv_out2 connect \dec31_upd \dec31_dec31_upd connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69903.9-69937.4" + attribute \src "libresoc.v:70073.9-70108.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -112829,11 +113158,12 @@ module \dec$171 connect \dec58_sv_in2 \dec58_dec58_sv_in2 connect \dec58_sv_in3 \dec58_dec58_sv_in3 connect \dec58_sv_out \dec58_dec58_sv_out + connect \dec58_sv_out2 \dec58_dec58_sv_out2 connect \dec58_upd \dec58_dec58_upd connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69938.9-69972.4" + attribute \src "libresoc.v:70109.9-70144.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -112866,30 +113196,31 @@ module \dec$171 connect \dec62_sv_in2 \dec62_dec62_sv_in2 connect \dec62_sv_in3 \dec62_dec62_sv_in3 connect \dec62_sv_out \dec62_dec62_sv_out + connect \dec62_sv_out2 \dec62_dec62_sv_out2 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:66950.7-66950.20" - process $proc$libresoc.v:66950$3586 + attribute \src "libresoc.v:67053.7-67053.20" + process $proc$libresoc.v:67053$3603 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:69973.3-70117.6" - process $proc$libresoc.v:69973$3554 + attribute \src "libresoc.v:70145.3-70289.6" + process $proc$libresoc.v:70145$3570 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:69974.5-69974.29" + attribute \src "libresoc.v:70146.5-70146.29" switch \initial - attribute \src "libresoc.v:69974.9-69974.17" + attribute \src "libresoc.v:70146.9-70146.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113062,7 +113393,7 @@ module \dec$171 case assign $1\form[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113082,19 +113413,19 @@ module \dec$171 sync always update \form $0\form[4:0] end - attribute \src "libresoc.v:70118.3-70259.6" - process $proc$libresoc.v:70118$3555 + attribute \src "libresoc.v:70290.3-70431.6" + process $proc$libresoc.v:70290$3571 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:70119.5-70119.29" + attribute \src "libresoc.v:70291.5-70291.29" switch \initial - attribute \src "libresoc.v:70119.9-70119.17" + attribute \src "libresoc.v:70291.9-70291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113263,7 +113594,7 @@ module \dec$171 case assign $1\asmcode[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113283,19 +113614,19 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:70260.3-70404.6" - process $proc$libresoc.v:70260$3556 + attribute \src "libresoc.v:70432.3-70576.6" + process $proc$libresoc.v:70432$3572 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:70261.5-70261.29" + attribute \src "libresoc.v:70433.5-70433.29" switch \initial - attribute \src "libresoc.v:70261.9-70261.17" + attribute \src "libresoc.v:70433.9-70433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113468,7 +113799,7 @@ module \dec$171 case assign $1\SV_Etype[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113488,19 +113819,19 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:70405.3-70549.6" - process $proc$libresoc.v:70405$3557 + attribute \src "libresoc.v:70577.3-70721.6" + process $proc$libresoc.v:70577$3573 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70406.5-70406.29" + attribute \src "libresoc.v:70578.5-70578.29" switch \initial - attribute \src "libresoc.v:70406.9-70406.17" + attribute \src "libresoc.v:70578.9-70578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113673,7 +114004,7 @@ module \dec$171 case assign $1\SV_Ptype[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113693,19 +114024,19 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70550.3-70694.6" - process $proc$libresoc.v:70550$3558 + attribute \src "libresoc.v:70722.3-70866.6" + process $proc$libresoc.v:70722$3574 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70551.5-70551.29" + attribute \src "libresoc.v:70723.5-70723.29" switch \initial - attribute \src "libresoc.v:70551.9-70551.17" + attribute \src "libresoc.v:70723.9-70723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113878,7 +114209,7 @@ module \dec$171 case assign $1\in1_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113898,19 +114229,19 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70695.3-70839.6" - process $proc$libresoc.v:70695$3559 + attribute \src "libresoc.v:70867.3-71011.6" + process $proc$libresoc.v:70867$3575 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70696.5-70696.29" + attribute \src "libresoc.v:70868.5-70868.29" switch \initial - attribute \src "libresoc.v:70696.9-70696.17" + attribute \src "libresoc.v:70868.9-70868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114083,7 +114414,7 @@ module \dec$171 case assign $1\in2_sel[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114103,19 +114434,19 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:70840.3-70984.6" - process $proc$libresoc.v:70840$3560 + attribute \src "libresoc.v:71012.3-71156.6" + process $proc$libresoc.v:71012$3576 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:70841.5-70841.29" + attribute \src "libresoc.v:71013.5-71013.29" switch \initial - attribute \src "libresoc.v:70841.9-70841.17" + attribute \src "libresoc.v:71013.9-71013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114288,7 +114619,7 @@ module \dec$171 case assign $1\in3_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114308,19 +114639,19 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:70985.3-71129.6" - process $proc$libresoc.v:70985$3561 + attribute \src "libresoc.v:71157.3-71301.6" + process $proc$libresoc.v:71157$3577 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] - attribute \src "libresoc.v:70986.5-70986.29" + attribute \src "libresoc.v:71158.5-71158.29" switch \initial - attribute \src "libresoc.v:70986.9-70986.17" + attribute \src "libresoc.v:71158.9-71158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114493,7 +114824,7 @@ module \dec$171 case assign $1\out_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114513,19 +114844,19 @@ module \dec$171 sync always update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:71130.3-71274.6" - process $proc$libresoc.v:71130$3562 + attribute \src "libresoc.v:71302.3-71446.6" + process $proc$libresoc.v:71302$3578 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:71131.5-71131.29" + attribute \src "libresoc.v:71303.5-71303.29" switch \initial - attribute \src "libresoc.v:71131.9-71131.17" + attribute \src "libresoc.v:71303.9-71303.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114698,7 +115029,7 @@ module \dec$171 case assign $1\cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114718,19 +115049,19 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:71275.3-71419.6" - process $proc$libresoc.v:71275$3563 + attribute \src "libresoc.v:71447.3-71591.6" + process $proc$libresoc.v:71447$3579 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:71276.5-71276.29" + attribute \src "libresoc.v:71448.5-71448.29" switch \initial - attribute \src "libresoc.v:71276.9-71276.17" + attribute \src "libresoc.v:71448.9-71448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114903,7 +115234,7 @@ module \dec$171 case assign $1\cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114923,19 +115254,19 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:71420.3-71564.6" - process $proc$libresoc.v:71420$3564 + attribute \src "libresoc.v:71592.3-71736.6" + process $proc$libresoc.v:71592$3580 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:71421.5-71421.29" + attribute \src "libresoc.v:71593.5-71593.29" switch \initial - attribute \src "libresoc.v:71421.9-71421.17" + attribute \src "libresoc.v:71593.9-71593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115108,7 +115439,7 @@ module \dec$171 case assign $1\sv_in1[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115128,19 +115459,19 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71565.3-71709.6" - process $proc$libresoc.v:71565$3565 + attribute \src "libresoc.v:71737.3-71881.6" + process $proc$libresoc.v:71737$3581 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71566.5-71566.29" + attribute \src "libresoc.v:71738.5-71738.29" switch \initial - attribute \src "libresoc.v:71566.9-71566.17" + attribute \src "libresoc.v:71738.9-71738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115313,7 +115644,7 @@ module \dec$171 case assign $1\sv_in2[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115333,19 +115664,19 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71710.3-71854.6" - process $proc$libresoc.v:71710$3566 + attribute \src "libresoc.v:71882.3-72026.6" + process $proc$libresoc.v:71882$3582 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71711.5-71711.29" + attribute \src "libresoc.v:71883.5-71883.29" switch \initial - attribute \src "libresoc.v:71711.9-71711.17" + attribute \src "libresoc.v:71883.9-71883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115518,7 +115849,7 @@ module \dec$171 case assign $1\sv_in3[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115538,19 +115869,19 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:71855.3-71999.6" - process $proc$libresoc.v:71855$3567 + attribute \src "libresoc.v:72027.3-72171.6" + process $proc$libresoc.v:72027$3583 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:71856.5-71856.29" + attribute \src "libresoc.v:72028.5-72028.29" switch \initial - attribute \src "libresoc.v:71856.9-71856.17" + attribute \src "libresoc.v:72028.9-72028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115723,7 +116054,7 @@ module \dec$171 case assign $1\sv_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115743,19 +116074,224 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:72000.3-72144.6" - process $proc$libresoc.v:72000$3568 + attribute \src "libresoc.v:72172.3-72316.6" + process $proc$libresoc.v:72172$3584 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out2[2:0] $2\sv_out2[2:0] + attribute \src "libresoc.v:72173.5-72173.29" + switch \initial + attribute \src "libresoc.v:72173.9-72173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out2[2:0] \dec19_dec19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out2[2:0] \dec30_dec30_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out2[2:0] \dec31_dec31_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out2[2:0] \dec58_dec58_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out2[2:0] \dec62_dec62_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out2[2:0] \dec22_dec22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + case + assign $1\sv_out2[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + case + assign $2\sv_out2[2:0] $1\sv_out2[2:0] + end + sync always + update \sv_out2 $0\sv_out2[2:0] + end + attribute \src "libresoc.v:72317.3-72461.6" + process $proc$libresoc.v:72317$3585 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72001.5-72001.29" + attribute \src "libresoc.v:72318.5-72318.29" switch \initial - attribute \src "libresoc.v:72001.9-72001.17" + attribute \src "libresoc.v:72318.9-72318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115928,7 +116464,7 @@ module \dec$171 case assign $1\sv_cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115948,19 +116484,19 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:72145.3-72289.6" - process $proc$libresoc.v:72145$3569 + attribute \src "libresoc.v:72462.3-72606.6" + process $proc$libresoc.v:72462$3586 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:72146.5-72146.29" + attribute \src "libresoc.v:72463.5-72463.29" switch \initial - attribute \src "libresoc.v:72146.9-72146.17" + attribute \src "libresoc.v:72463.9-72463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116133,7 +116669,7 @@ module \dec$171 case assign $1\sv_cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116153,19 +116689,19 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:72290.3-72434.6" - process $proc$libresoc.v:72290$3570 + attribute \src "libresoc.v:72607.3-72751.6" + process $proc$libresoc.v:72607$3587 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:72291.5-72291.29" + attribute \src "libresoc.v:72608.5-72608.29" switch \initial - attribute \src "libresoc.v:72291.9-72291.17" + attribute \src "libresoc.v:72608.9-72608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116338,7 +116874,7 @@ module \dec$171 case assign $1\ldst_len[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116358,19 +116894,19 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:72435.3-72579.6" - process $proc$libresoc.v:72435$3571 + attribute \src "libresoc.v:72752.3-72896.6" + process $proc$libresoc.v:72752$3588 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:72436.5-72436.29" + attribute \src "libresoc.v:72753.5-72753.29" switch \initial - attribute \src "libresoc.v:72436.9-72436.17" + attribute \src "libresoc.v:72753.9-72753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116543,7 +117079,7 @@ module \dec$171 case assign $1\upd[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116563,19 +117099,19 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72580.3-72724.6" - process $proc$libresoc.v:72580$3572 + attribute \src "libresoc.v:72897.3-73041.6" + process $proc$libresoc.v:72897$3589 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72581.5-72581.29" + attribute \src "libresoc.v:72898.5-72898.29" switch \initial - attribute \src "libresoc.v:72581.9-72581.17" + attribute \src "libresoc.v:72898.9-72898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116748,7 +117284,7 @@ module \dec$171 case assign $1\rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116768,19 +117304,19 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:72725.3-72869.6" - process $proc$libresoc.v:72725$3573 + attribute \src "libresoc.v:73042.3-73186.6" + process $proc$libresoc.v:73042$3590 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:72726.5-72726.29" + attribute \src "libresoc.v:73043.5-73043.29" switch \initial - attribute \src "libresoc.v:72726.9-72726.17" + attribute \src "libresoc.v:73043.9-73043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116953,7 +117489,7 @@ module \dec$171 case assign $1\cry_in[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116973,19 +117509,19 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:72870.3-73014.6" - process $proc$libresoc.v:72870$3574 + attribute \src "libresoc.v:73187.3-73331.6" + process $proc$libresoc.v:73187$3591 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:72871.5-72871.29" + attribute \src "libresoc.v:73188.5-73188.29" switch \initial - attribute \src "libresoc.v:72871.9-72871.17" + attribute \src "libresoc.v:73188.9-73188.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117158,7 +117694,7 @@ module \dec$171 case assign $1\inv_a[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117178,19 +117714,19 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:73015.3-73159.6" - process $proc$libresoc.v:73015$3575 + attribute \src "libresoc.v:73332.3-73476.6" + process $proc$libresoc.v:73332$3592 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:73016.5-73016.29" + attribute \src "libresoc.v:73333.5-73333.29" switch \initial - attribute \src "libresoc.v:73016.9-73016.17" + attribute \src "libresoc.v:73333.9-73333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117363,7 +117899,7 @@ module \dec$171 case assign $1\inv_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117383,19 +117919,19 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:73160.3-73304.6" - process $proc$libresoc.v:73160$3576 + attribute \src "libresoc.v:73477.3-73621.6" + process $proc$libresoc.v:73477$3593 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:73161.5-73161.29" + attribute \src "libresoc.v:73478.5-73478.29" switch \initial - attribute \src "libresoc.v:73161.9-73161.17" + attribute \src "libresoc.v:73478.9-73478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117568,7 +118104,7 @@ module \dec$171 case assign $1\cry_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117588,19 +118124,19 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:73305.3-73449.6" - process $proc$libresoc.v:73305$3577 + attribute \src "libresoc.v:73622.3-73766.6" + process $proc$libresoc.v:73622$3594 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:73306.5-73306.29" + attribute \src "libresoc.v:73623.5-73623.29" switch \initial - attribute \src "libresoc.v:73306.9-73306.17" + attribute \src "libresoc.v:73623.9-73623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117773,7 +118309,7 @@ module \dec$171 case assign $1\br[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117793,19 +118329,19 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:73450.3-73594.6" - process $proc$libresoc.v:73450$3578 + attribute \src "libresoc.v:73767.3-73911.6" + process $proc$libresoc.v:73767$3595 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:73451.5-73451.29" + attribute \src "libresoc.v:73768.5-73768.29" switch \initial - attribute \src "libresoc.v:73451.9-73451.17" + attribute \src "libresoc.v:73768.9-73768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117978,7 +118514,7 @@ module \dec$171 case assign $1\sgn_ext[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117998,19 +118534,19 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73595.3-73739.6" - process $proc$libresoc.v:73595$3579 + attribute \src "libresoc.v:73912.3-74056.6" + process $proc$libresoc.v:73912$3596 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73596.5-73596.29" + attribute \src "libresoc.v:73913.5-73913.29" switch \initial - attribute \src "libresoc.v:73596.9-73596.17" + attribute \src "libresoc.v:73913.9-73913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118183,7 +118719,7 @@ module \dec$171 case assign $1\rsrv[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118203,19 +118739,19 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:73740.3-73884.6" - process $proc$libresoc.v:73740$3580 + attribute \src "libresoc.v:74057.3-74201.6" + process $proc$libresoc.v:74057$3597 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:73741.5-73741.29" + attribute \src "libresoc.v:74058.5-74058.29" switch \initial - attribute \src "libresoc.v:73741.9-73741.17" + attribute \src "libresoc.v:74058.9-74058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118388,7 +118924,7 @@ module \dec$171 case assign $1\is_32b[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118408,19 +118944,19 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:73885.3-74029.6" - process $proc$libresoc.v:73885$3581 + attribute \src "libresoc.v:74202.3-74346.6" + process $proc$libresoc.v:74202$3598 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:73886.5-73886.29" + attribute \src "libresoc.v:74203.5-74203.29" switch \initial - attribute \src "libresoc.v:73886.9-73886.17" + attribute \src "libresoc.v:74203.9-74203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118593,7 +119129,7 @@ module \dec$171 case assign $1\sgn[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118613,19 +119149,19 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:74030.3-74174.6" - process $proc$libresoc.v:74030$3582 + attribute \src "libresoc.v:74347.3-74491.6" + process $proc$libresoc.v:74347$3599 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:74031.5-74031.29" + attribute \src "libresoc.v:74348.5-74348.29" switch \initial - attribute \src "libresoc.v:74031.9-74031.17" + attribute \src "libresoc.v:74348.9-74348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118798,7 +119334,7 @@ module \dec$171 case assign $1\lk[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118818,19 +119354,19 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:74175.3-74319.6" - process $proc$libresoc.v:74175$3583 + attribute \src "libresoc.v:74492.3-74636.6" + process $proc$libresoc.v:74492$3600 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74176.5-74176.29" + attribute \src "libresoc.v:74493.5-74493.29" switch \initial - attribute \src "libresoc.v:74176.9-74176.17" + attribute \src "libresoc.v:74493.9-74493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119003,7 +119539,7 @@ module \dec$171 case assign $1\sgl_pipe[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119023,19 +119559,19 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:74320.3-74464.6" - process $proc$libresoc.v:74320$3584 + attribute \src "libresoc.v:74637.3-74781.6" + process $proc$libresoc.v:74637$3601 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] - attribute \src "libresoc.v:74321.5-74321.29" + attribute \src "libresoc.v:74638.5-74638.29" switch \initial - attribute \src "libresoc.v:74321.9-74321.17" + attribute \src "libresoc.v:74638.9-74638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119208,7 +119744,7 @@ module \dec$171 case assign $1\function_unit[13:0] 14'00000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119228,19 +119764,19 @@ module \dec$171 sync always update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:74465.3-74609.6" - process $proc$libresoc.v:74465$3585 + attribute \src "libresoc.v:74782.3-74926.6" + process $proc$libresoc.v:74782$3602 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:74466.5-74466.29" + attribute \src "libresoc.v:74783.5-74783.29" switch \initial - attribute \src "libresoc.v:74466.9-74466.17" + attribute \src "libresoc.v:74783.9-74783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119413,7 +119949,7 @@ module \dec$171 case assign $1\internal_op[6:0] 7'0000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119433,7 +119969,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - connect \$2 $ternary$libresoc.v:69762$3553_Y + connect \$2 $ternary$libresoc.v:69928$3569_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -119777,157 +120313,161 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:74956.1-76960.10" +attribute \src "libresoc.v:75273.1-77339.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:76647.3-76698.6" + attribute \src "libresoc.v:77026.3-77077.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76699.3-76750.6" + attribute \src "libresoc.v:77078.3-77129.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76023.3-76074.6" + attribute \src "libresoc.v:76402.3-76453.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:76231.3-76282.6" + attribute \src "libresoc.v:76610.3-76661.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:75347.3-75398.6" + attribute \src "libresoc.v:75674.3-75725.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75399.3-75450.6" + attribute \src "libresoc.v:75726.3-75777.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:75971.3-76022.6" + attribute \src "libresoc.v:76350.3-76401.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:76179.3-76230.6" + attribute \src "libresoc.v:76558.3-76609.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76439.3-76490.6" + attribute \src "libresoc.v:76766.3-76817.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:75295.3-75346.6" + attribute \src "libresoc.v:75622.3-75673.6" wire width 14 $0\dec19_function_unit[13:0] - attribute \src "libresoc.v:76751.3-76802.6" + attribute \src "libresoc.v:77130.3-77181.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76803.3-76854.6" + attribute \src "libresoc.v:77182.3-77233.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76855.3-76906.6" + attribute \src "libresoc.v:77234.3-77285.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75867.3-75918.6" + attribute \src "libresoc.v:76194.3-76245.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:76075.3-76126.6" + attribute \src "libresoc.v:76454.3-76505.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:76127.3-76178.6" + attribute \src "libresoc.v:76506.3-76557.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:76387.3-76438.6" + attribute \src "libresoc.v:76818.3-76869.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:75763.3-75814.6" + attribute \src "libresoc.v:76142.3-76193.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76543.3-76594.6" + attribute \src "libresoc.v:76922.3-76973.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:76907.3-76958.6" + attribute \src "libresoc.v:77286.3-77337.6" wire width 3 $0\dec19_out_sel[2:0] - attribute \src "libresoc.v:75919.3-75970.6" + attribute \src "libresoc.v:76298.3-76349.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76335.3-76386.6" + attribute \src "libresoc.v:76714.3-76765.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76595.3-76646.6" + attribute \src "libresoc.v:76974.3-77025.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76491.3-76542.6" + attribute \src "libresoc.v:76870.3-76921.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:76283.3-76334.6" + attribute \src "libresoc.v:76662.3-76713.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75659.3-75710.6" + attribute \src "libresoc.v:76038.3-76089.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75711.3-75762.6" + attribute \src "libresoc.v:76090.3-76141.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75451.3-75502.6" + attribute \src "libresoc.v:75778.3-75829.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75503.3-75554.6" + attribute \src "libresoc.v:75830.3-75881.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75555.3-75606.6" + attribute \src "libresoc.v:75882.3-75933.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75607.3-75658.6" + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $0\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:75815.3-75866.6" + attribute \src "libresoc.v:76246.3-76297.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:74957.7-74957.20" + attribute \src "libresoc.v:75274.7-75274.20" wire $0\initial[0:0] - attribute \src "libresoc.v:76647.3-76698.6" + attribute \src "libresoc.v:77026.3-77077.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76699.3-76750.6" + attribute \src "libresoc.v:77078.3-77129.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76023.3-76074.6" + attribute \src "libresoc.v:76402.3-76453.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76231.3-76282.6" + attribute \src "libresoc.v:76610.3-76661.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:75347.3-75398.6" + attribute \src "libresoc.v:75674.3-75725.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75399.3-75450.6" + attribute \src "libresoc.v:75726.3-75777.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75971.3-76022.6" + attribute \src "libresoc.v:76350.3-76401.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76179.3-76230.6" + attribute \src "libresoc.v:76558.3-76609.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76439.3-76490.6" + attribute \src "libresoc.v:76766.3-76817.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:75295.3-75346.6" + attribute \src "libresoc.v:75622.3-75673.6" wire width 14 $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:76751.3-76802.6" + attribute \src "libresoc.v:77130.3-77181.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76803.3-76854.6" + attribute \src "libresoc.v:77182.3-77233.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76855.3-76906.6" + attribute \src "libresoc.v:77234.3-77285.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75867.3-75918.6" + attribute \src "libresoc.v:76194.3-76245.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76075.3-76126.6" + attribute \src "libresoc.v:76454.3-76505.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76127.3-76178.6" + attribute \src "libresoc.v:76506.3-76557.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76387.3-76438.6" + attribute \src "libresoc.v:76818.3-76869.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:75763.3-75814.6" + attribute \src "libresoc.v:76142.3-76193.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76543.3-76594.6" + attribute \src "libresoc.v:76922.3-76973.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:76907.3-76958.6" + attribute \src "libresoc.v:77286.3-77337.6" wire width 3 $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:75919.3-75970.6" + attribute \src "libresoc.v:76298.3-76349.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76335.3-76386.6" + attribute \src "libresoc.v:76714.3-76765.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76595.3-76646.6" + attribute \src "libresoc.v:76974.3-77025.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76491.3-76542.6" + attribute \src "libresoc.v:76870.3-76921.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76283.3-76334.6" + attribute \src "libresoc.v:76662.3-76713.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75659.3-75710.6" + attribute \src "libresoc.v:76038.3-76089.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75711.3-75762.6" + attribute \src "libresoc.v:76090.3-76141.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75451.3-75502.6" + attribute \src "libresoc.v:75778.3-75829.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75503.3-75554.6" + attribute \src "libresoc.v:75830.3-75881.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75555.3-75606.6" + attribute \src "libresoc.v:75882.3-75933.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75607.3-75658.6" + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75815.3-75866.6" + attribute \src "libresoc.v:76246.3-76297.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -119937,7 +120477,7 @@ module \dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -119946,16 +120486,16 @@ module \dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -119987,7 +120527,7 @@ module \dec19 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -120004,7 +120544,7 @@ module \dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -120012,7 +120552,7 @@ module \dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -120029,13 +120569,13 @@ module \dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -120112,46 +120652,46 @@ module \dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120159,8 +120699,8 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec19_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120168,8 +120708,8 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec19_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120177,7 +120717,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120186,7 +120726,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120195,7 +120735,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120204,41 +120744,50 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec19_upd - attribute \src "libresoc.v:74957.7-74957.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec19_upd + attribute \src "libresoc.v:75274.7-75274.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch - attribute \src "libresoc.v:74957.7-74957.20" - process $proc$libresoc.v:74957$3619 + attribute \src "libresoc.v:75274.7-75274.20" + process $proc$libresoc.v:75274$3637 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75295.3-75346.6" - process $proc$libresoc.v:75295$3587 + attribute \src "libresoc.v:75622.3-75673.6" + process $proc$libresoc.v:75622$3604 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:75296.5-75296.29" + attribute \src "libresoc.v:75623.5-75623.29" switch \initial - attribute \src "libresoc.v:75296.9-75296.17" + attribute \src "libresoc.v:75623.9-75623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120306,18 +120855,18 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:75347.3-75398.6" - process $proc$libresoc.v:75347$3588 + attribute \src "libresoc.v:75674.3-75725.6" + process $proc$libresoc.v:75674$3605 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75348.5-75348.29" + attribute \src "libresoc.v:75675.5-75675.29" switch \initial - attribute \src "libresoc.v:75348.9-75348.17" + attribute \src "libresoc.v:75675.9-75675.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120385,18 +120934,18 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75399.3-75450.6" - process $proc$libresoc.v:75399$3589 + attribute \src "libresoc.v:75726.3-75777.6" + process $proc$libresoc.v:75726$3606 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75400.5-75400.29" + attribute \src "libresoc.v:75727.5-75727.29" switch \initial - attribute \src "libresoc.v:75400.9-75400.17" + attribute \src "libresoc.v:75727.9-75727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120464,18 +121013,18 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75451.3-75502.6" - process $proc$libresoc.v:75451$3590 + attribute \src "libresoc.v:75778.3-75829.6" + process $proc$libresoc.v:75778$3607 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75452.5-75452.29" + attribute \src "libresoc.v:75779.5-75779.29" switch \initial - attribute \src "libresoc.v:75452.9-75452.17" + attribute \src "libresoc.v:75779.9-75779.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120543,18 +121092,18 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75503.3-75554.6" - process $proc$libresoc.v:75503$3591 + attribute \src "libresoc.v:75830.3-75881.6" + process $proc$libresoc.v:75830$3608 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75504.5-75504.29" + attribute \src "libresoc.v:75831.5-75831.29" switch \initial - attribute \src "libresoc.v:75504.9-75504.17" + attribute \src "libresoc.v:75831.9-75831.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120622,18 +121171,18 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75555.3-75606.6" - process $proc$libresoc.v:75555$3592 + attribute \src "libresoc.v:75882.3-75933.6" + process $proc$libresoc.v:75882$3609 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75556.5-75556.29" + attribute \src "libresoc.v:75883.5-75883.29" switch \initial - attribute \src "libresoc.v:75556.9-75556.17" + attribute \src "libresoc.v:75883.9-75883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120701,18 +121250,18 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75607.3-75658.6" - process $proc$libresoc.v:75607$3593 + attribute \src "libresoc.v:75934.3-75985.6" + process $proc$libresoc.v:75934$3610 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75608.5-75608.29" + attribute \src "libresoc.v:75935.5-75935.29" switch \initial - attribute \src "libresoc.v:75608.9-75608.17" + attribute \src "libresoc.v:75935.9-75935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120780,18 +121329,97 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75659.3-75710.6" - process $proc$libresoc.v:75659$3594 + attribute \src "libresoc.v:75986.3-76037.6" + process $proc$libresoc.v:75986$3611 + assign { } { } + assign { } { } + assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75987.5-75987.29" + switch \initial + attribute \src "libresoc.v:75987.9-75987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + case + assign $1\dec19_sv_out2[2:0] 3'000 + end + sync always + update \dec19_sv_out2 $0\dec19_sv_out2[2:0] + end + attribute \src "libresoc.v:76038.3-76089.6" + process $proc$libresoc.v:76038$3612 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75660.5-75660.29" + attribute \src "libresoc.v:76039.5-76039.29" switch \initial - attribute \src "libresoc.v:75660.9-75660.17" + attribute \src "libresoc.v:76039.9-76039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120859,18 +121487,18 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:75711.3-75762.6" - process $proc$libresoc.v:75711$3595 + attribute \src "libresoc.v:76090.3-76141.6" + process $proc$libresoc.v:76090$3613 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75712.5-75712.29" + attribute \src "libresoc.v:76091.5-76091.29" switch \initial - attribute \src "libresoc.v:75712.9-75712.17" + attribute \src "libresoc.v:76091.9-76091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120938,18 +121566,18 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:75763.3-75814.6" - process $proc$libresoc.v:75763$3596 + attribute \src "libresoc.v:76142.3-76193.6" + process $proc$libresoc.v:76142$3614 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:75764.5-75764.29" + attribute \src "libresoc.v:76143.5-76143.29" switch \initial - attribute \src "libresoc.v:75764.9-75764.17" + attribute \src "libresoc.v:76143.9-76143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121017,176 +121645,176 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:75815.3-75866.6" - process $proc$libresoc.v:75815$3597 + attribute \src "libresoc.v:76194.3-76245.6" + process $proc$libresoc.v:76194$3615 assign { } { } assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:75816.5-75816.29" + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:76195.5-76195.29" switch \initial - attribute \src "libresoc.v:75816.9-75816.17" + attribute \src "libresoc.v:76195.9-76195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0100100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000110 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000110 case - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0000000 end sync always - update \dec19_upd $0\dec19_upd[1:0] + update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:75867.3-75918.6" - process $proc$libresoc.v:75867$3598 + attribute \src "libresoc.v:76246.3-76297.6" + process $proc$libresoc.v:76246$3616 assign { } { } assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75868.5-75868.29" + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:76247.5-76247.29" switch \initial - attribute \src "libresoc.v:75868.9-75868.17" + attribute \src "libresoc.v:76247.9-76247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec19_upd[1:0] 2'00 case - assign $1\dec19_internal_op[6:0] 7'0000000 + assign $1\dec19_upd[1:0] 2'00 end sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] + update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:75919.3-75970.6" - process $proc$libresoc.v:75919$3599 + attribute \src "libresoc.v:76298.3-76349.6" + process $proc$libresoc.v:76298$3617 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75920.5-75920.29" + attribute \src "libresoc.v:76299.5-76299.29" switch \initial - attribute \src "libresoc.v:75920.9-75920.17" + attribute \src "libresoc.v:76299.9-76299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121254,18 +121882,18 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:75971.3-76022.6" - process $proc$libresoc.v:75971$3600 + attribute \src "libresoc.v:76350.3-76401.6" + process $proc$libresoc.v:76350$3618 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75972.5-75972.29" + attribute \src "libresoc.v:76351.5-76351.29" switch \initial - attribute \src "libresoc.v:75972.9-75972.17" + attribute \src "libresoc.v:76351.9-76351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121333,18 +121961,18 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:76023.3-76074.6" - process $proc$libresoc.v:76023$3601 + attribute \src "libresoc.v:76402.3-76453.6" + process $proc$libresoc.v:76402$3619 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76024.5-76024.29" + attribute \src "libresoc.v:76403.5-76403.29" switch \initial - attribute \src "libresoc.v:76024.9-76024.17" + attribute \src "libresoc.v:76403.9-76403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121412,18 +122040,18 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:76075.3-76126.6" - process $proc$libresoc.v:76075$3602 + attribute \src "libresoc.v:76454.3-76505.6" + process $proc$libresoc.v:76454$3620 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76076.5-76076.29" + attribute \src "libresoc.v:76455.5-76455.29" switch \initial - attribute \src "libresoc.v:76076.9-76076.17" + attribute \src "libresoc.v:76455.9-76455.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121491,18 +122119,18 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:76127.3-76178.6" - process $proc$libresoc.v:76127$3603 + attribute \src "libresoc.v:76506.3-76557.6" + process $proc$libresoc.v:76506$3621 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76128.5-76128.29" + attribute \src "libresoc.v:76507.5-76507.29" switch \initial - attribute \src "libresoc.v:76128.9-76128.17" + attribute \src "libresoc.v:76507.9-76507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121570,18 +122198,18 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:76179.3-76230.6" - process $proc$libresoc.v:76179$3604 + attribute \src "libresoc.v:76558.3-76609.6" + process $proc$libresoc.v:76558$3622 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76180.5-76180.29" + attribute \src "libresoc.v:76559.5-76559.29" switch \initial - attribute \src "libresoc.v:76180.9-76180.17" + attribute \src "libresoc.v:76559.9-76559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121649,18 +122277,18 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:76231.3-76282.6" - process $proc$libresoc.v:76231$3605 + attribute \src "libresoc.v:76610.3-76661.6" + process $proc$libresoc.v:76610$3623 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:76232.5-76232.29" + attribute \src "libresoc.v:76611.5-76611.29" switch \initial - attribute \src "libresoc.v:76232.9-76232.17" + attribute \src "libresoc.v:76611.9-76611.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121728,18 +122356,18 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:76283.3-76334.6" - process $proc$libresoc.v:76283$3606 + attribute \src "libresoc.v:76662.3-76713.6" + process $proc$libresoc.v:76662$3624 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76284.5-76284.29" + attribute \src "libresoc.v:76663.5-76663.29" switch \initial - attribute \src "libresoc.v:76284.9-76284.17" + attribute \src "libresoc.v:76663.9-76663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121807,18 +122435,18 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:76335.3-76386.6" - process $proc$libresoc.v:76335$3607 + attribute \src "libresoc.v:76714.3-76765.6" + process $proc$libresoc.v:76714$3625 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76336.5-76336.29" + attribute \src "libresoc.v:76715.5-76715.29" switch \initial - attribute \src "libresoc.v:76336.9-76336.17" + attribute \src "libresoc.v:76715.9-76715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121886,176 +122514,176 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:76387.3-76438.6" - process $proc$libresoc.v:76387$3608 + attribute \src "libresoc.v:76766.3-76817.6" + process $proc$libresoc.v:76766$3626 assign { } { } assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76388.5-76388.29" + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:76767.5-76767.29" switch \initial - attribute \src "libresoc.v:76388.9-76388.17" + attribute \src "libresoc.v:76767.9-76767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 case - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'00000 end sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] + update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76439.3-76490.6" - process $proc$libresoc.v:76439$3609 + attribute \src "libresoc.v:76818.3-76869.6" + process $proc$libresoc.v:76818$3627 assign { } { } assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76440.5-76440.29" + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:76819.5-76819.29" switch \initial - attribute \src "libresoc.v:76440.9-76440.17" + attribute \src "libresoc.v:76819.9-76819.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 case - assign $1\dec19_form[4:0] 5'00000 + assign $1\dec19_is_32b[0:0] 1'0 end sync always - update \dec19_form $0\dec19_form[4:0] + update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76491.3-76542.6" - process $proc$libresoc.v:76491$3610 + attribute \src "libresoc.v:76870.3-76921.6" + process $proc$libresoc.v:76870$3628 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76492.5-76492.29" + attribute \src "libresoc.v:76871.5-76871.29" switch \initial - attribute \src "libresoc.v:76492.9-76492.17" + attribute \src "libresoc.v:76871.9-76871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122123,18 +122751,18 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76543.3-76594.6" - process $proc$libresoc.v:76543$3611 + attribute \src "libresoc.v:76922.3-76973.6" + process $proc$libresoc.v:76922$3629 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76544.5-76544.29" + attribute \src "libresoc.v:76923.5-76923.29" switch \initial - attribute \src "libresoc.v:76544.9-76544.17" + attribute \src "libresoc.v:76923.9-76923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122202,18 +122830,18 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76595.3-76646.6" - process $proc$libresoc.v:76595$3612 + attribute \src "libresoc.v:76974.3-77025.6" + process $proc$libresoc.v:76974$3630 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76596.5-76596.29" + attribute \src "libresoc.v:76975.5-76975.29" switch \initial - attribute \src "libresoc.v:76596.9-76596.17" + attribute \src "libresoc.v:76975.9-76975.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122281,18 +122909,18 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:76647.3-76698.6" - process $proc$libresoc.v:76647$3613 + attribute \src "libresoc.v:77026.3-77077.6" + process $proc$libresoc.v:77026$3631 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76648.5-76648.29" + attribute \src "libresoc.v:77027.5-77027.29" switch \initial - attribute \src "libresoc.v:76648.9-76648.17" + attribute \src "libresoc.v:77027.9-77027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122360,18 +122988,18 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:76699.3-76750.6" - process $proc$libresoc.v:76699$3614 + attribute \src "libresoc.v:77078.3-77129.6" + process $proc$libresoc.v:77078$3632 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76700.5-76700.29" + attribute \src "libresoc.v:77079.5-77079.29" switch \initial - attribute \src "libresoc.v:76700.9-76700.17" + attribute \src "libresoc.v:77079.9-77079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122439,18 +123067,18 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:76751.3-76802.6" - process $proc$libresoc.v:76751$3615 + attribute \src "libresoc.v:77130.3-77181.6" + process $proc$libresoc.v:77130$3633 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76752.5-76752.29" + attribute \src "libresoc.v:77131.5-77131.29" switch \initial - attribute \src "libresoc.v:76752.9-76752.17" + attribute \src "libresoc.v:77131.9-77131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122518,18 +123146,18 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:76803.3-76854.6" - process $proc$libresoc.v:76803$3616 + attribute \src "libresoc.v:77182.3-77233.6" + process $proc$libresoc.v:77182$3634 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76804.5-76804.29" + attribute \src "libresoc.v:77183.5-77183.29" switch \initial - attribute \src "libresoc.v:76804.9-76804.17" + attribute \src "libresoc.v:77183.9-77183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122597,18 +123225,18 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:76855.3-76906.6" - process $proc$libresoc.v:76855$3617 + attribute \src "libresoc.v:77234.3-77285.6" + process $proc$libresoc.v:77234$3635 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76856.5-76856.29" + attribute \src "libresoc.v:77235.5-77235.29" switch \initial - attribute \src "libresoc.v:76856.9-76856.17" + attribute \src "libresoc.v:77235.9-77235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122676,18 +123304,18 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:76907.3-76958.6" - process $proc$libresoc.v:76907$3618 + attribute \src "libresoc.v:77286.3-77337.6" + process $proc$libresoc.v:77286$3636 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:76908.5-76908.29" + attribute \src "libresoc.v:77287.5-77287.29" switch \initial - attribute \src "libresoc.v:76908.9-76908.17" + attribute \src "libresoc.v:77287.9-77287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122757,832 +123385,832 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:76964.1-79185.10" +attribute \src "libresoc.v:77343.1-79564.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $0\cr_in2$1[6:0]$3680 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_in2$1[6:0]$3698 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\cr_in2_ok$2[0:0]$3681 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_in2_ok$2[0:0]$3699 + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$3[0:0]$3683 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$4[0:0]$3684 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$5[0:0]$3685 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$6[0:0]$3686 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$7[0:0]$3687 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$8[0:0]$3688 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$9[0:0]$3689 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal[0:0]$3682 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$3[0:0]$3701 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$4[0:0]$3702 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$5[0:0]$3703 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$6[0:0]$3704 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$7[0:0]$3705 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$8[0:0]$3706 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$9[0:0]$3707 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal[0:0]$3700 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $0\fn_unit[13:0] - attribute \src "libresoc.v:76965.7-76965.20" + attribute \src "libresoc.v:77344.7-77344.20" wire $0\initial[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:78850.3-78864.6" + attribute \src "libresoc.v:79229.3-79243.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78875.3-78887.6" + attribute \src "libresoc.v:79254.3-79266.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78865.3-78874.6" + attribute \src "libresoc.v:79244.3-79253.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78914.3-78923.6" + attribute \src "libresoc.v:79293.3-79302.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:78904.3-78913.6" + attribute \src "libresoc.v:79283.3-79292.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $1\cr_in2$1[6:0]$3690 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_in2$1[6:0]$3708 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\cr_in2_ok$2[0:0]$3691 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_in2_ok$2[0:0]$3709 + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$3[0:0]$3693 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$4[0:0]$3694 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$5[0:0]$3695 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$6[0:0]$3696 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$7[0:0]$3697 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$8[0:0]$3698 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$9[0:0]$3699 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal[0:0]$3692 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$3[0:0]$3711 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$4[0:0]$3712 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$5[0:0]$3713 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$6[0:0]$3714 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$7[0:0]$3715 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$8[0:0]$3716 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$9[0:0]$3717 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal[0:0]$3710 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $1\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:78850.3-78864.6" + attribute \src "libresoc.v:79229.3-79243.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78875.3-78887.6" + attribute \src "libresoc.v:79254.3-79266.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78865.3-78874.6" + attribute \src "libresoc.v:79244.3-79253.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78914.3-78923.6" + attribute \src "libresoc.v:79293.3-79302.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:78904.3-78913.6" + attribute \src "libresoc.v:79283.3-79292.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $2\cr_in2$1[6:0]$3700 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_in2$1[6:0]$3718 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\cr_in2_ok$2[0:0]$3701 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_in2_ok$2[0:0]$3719 + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$3[0:0]$3703 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$4[0:0]$3704 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$5[0:0]$3705 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$6[0:0]$3706 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$7[0:0]$3707 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$8[0:0]$3708 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$9[0:0]$3709 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal[0:0]$3702 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$3[0:0]$3721 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$4[0:0]$3722 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$5[0:0]$3723 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$6[0:0]$3724 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$7[0:0]$3725 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$8[0:0]$3726 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$9[0:0]$3727 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal[0:0]$3720 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $2\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $3\cr_in2$1[6:0]$3710 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $3\cr_in2$1[6:0]$3728 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\cr_in2_ok$2[0:0]$3711 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\cr_in2_ok$2[0:0]$3729 + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$3[0:0]$3713 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$4[0:0]$3714 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$5[0:0]$3715 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$6[0:0]$3716 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$7[0:0]$3717 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$8[0:0]$3718 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$9[0:0]$3719 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal[0:0]$3712 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$3[0:0]$3731 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$4[0:0]$3732 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$5[0:0]$3733 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$6[0:0]$3734 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$7[0:0]$3735 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$8[0:0]$3736 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$9[0:0]$3737 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal[0:0]$3730 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $3\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $4\cr_in2$1[6:0]$3720 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $4\cr_in2$1[6:0]$3738 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\cr_in2_ok$2[0:0]$3721 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\cr_in2_ok$2[0:0]$3739 + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$3[0:0]$3723 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$4[0:0]$3724 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$5[0:0]$3725 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$6[0:0]$3726 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$7[0:0]$3727 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$8[0:0]$3728 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$9[0:0]$3729 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal[0:0]$3722 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$3[0:0]$3741 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$4[0:0]$3742 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$5[0:0]$3743 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$6[0:0]$3744 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$7[0:0]$3745 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$8[0:0]$3746 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$9[0:0]$3747 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal[0:0]$3740 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $4\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:78671.19-78671.122" - wire $and$libresoc.v:78671$3630_Y - attribute \src "libresoc.v:78672.19-78672.125" - wire $and$libresoc.v:78672$3631_Y - attribute \src "libresoc.v:78673.19-78673.126" - wire $and$libresoc.v:78673$3632_Y - attribute \src "libresoc.v:78680.18-78680.114" - wire $and$libresoc.v:78680$3639_Y - attribute \src "libresoc.v:78681.18-78681.116" - wire $and$libresoc.v:78681$3640_Y - attribute \src "libresoc.v:78683.18-78683.114" - wire $and$libresoc.v:78683$3642_Y - attribute \src "libresoc.v:78685.18-78685.110" - wire $and$libresoc.v:78685$3644_Y - attribute \src "libresoc.v:78697.18-78697.114" - wire $and$libresoc.v:78697$3656_Y - attribute \src "libresoc.v:78698.18-78698.116" - wire $and$libresoc.v:78698$3657_Y - attribute \src "libresoc.v:78700.18-78700.114" - wire $and$libresoc.v:78700$3659_Y - attribute \src "libresoc.v:78702.18-78702.110" - wire $and$libresoc.v:78702$3661_Y - attribute \src "libresoc.v:78667.19-78667.124" - wire $eq$libresoc.v:78667$3626_Y - attribute \src "libresoc.v:78668.19-78668.124" - wire $eq$libresoc.v:78668$3627_Y - attribute \src "libresoc.v:78669.19-78669.124" - wire $eq$libresoc.v:78669$3628_Y - attribute \src "libresoc.v:78670.19-78670.124" - wire $eq$libresoc.v:78670$3629_Y - attribute \src "libresoc.v:78674.19-78674.124" - wire $eq$libresoc.v:78674$3633_Y - attribute \src "libresoc.v:78675.18-78675.117" - wire $eq$libresoc.v:78675$3634_Y - attribute \src "libresoc.v:78676.18-78676.117" - wire $eq$libresoc.v:78676$3635_Y - attribute \src "libresoc.v:78678.18-78678.117" - wire $eq$libresoc.v:78678$3637_Y - attribute \src "libresoc.v:78679.18-78679.127" - wire $eq$libresoc.v:78679$3638_Y - attribute \src "libresoc.v:78682.18-78682.127" - wire $eq$libresoc.v:78682$3641_Y - attribute \src "libresoc.v:78686.18-78686.122" - wire $eq$libresoc.v:78686$3645_Y - attribute \src "libresoc.v:78687.18-78687.122" - wire $eq$libresoc.v:78687$3646_Y - attribute \src "libresoc.v:78689.18-78689.110" - wire $eq$libresoc.v:78689$3648_Y - attribute \src "libresoc.v:78690.18-78690.110" - wire $eq$libresoc.v:78690$3649_Y - attribute \src "libresoc.v:78692.18-78692.112" - wire $eq$libresoc.v:78692$3651_Y - attribute \src "libresoc.v:78694.18-78694.110" - wire $eq$libresoc.v:78694$3653_Y - attribute \src "libresoc.v:78696.18-78696.127" - wire $eq$libresoc.v:78696$3655_Y - attribute \src "libresoc.v:78699.18-78699.127" - wire $eq$libresoc.v:78699$3658_Y - attribute \src "libresoc.v:78664.19-78664.124" - wire width 7 $extend$libresoc.v:78664$3620_Y - attribute \src "libresoc.v:78665.19-78665.124" - wire width 7 $extend$libresoc.v:78665$3622_Y - attribute \src "libresoc.v:78666.19-78666.123" - wire width 7 $extend$libresoc.v:78666$3624_Y - attribute \src "libresoc.v:78703.18-78703.111" - wire width 7 $extend$libresoc.v:78703$3662_Y - attribute \src "libresoc.v:78704.18-78704.111" - wire width 7 $extend$libresoc.v:78704$3664_Y - attribute \src "libresoc.v:78705.18-78705.111" - wire width 7 $extend$libresoc.v:78705$3666_Y - attribute \src "libresoc.v:78706.18-78706.113" - wire width 7 $extend$libresoc.v:78706$3668_Y - attribute \src "libresoc.v:78707.18-78707.121" - wire width 7 $extend$libresoc.v:78707$3670_Y - attribute \src "libresoc.v:78684.18-78684.110" - wire $not$libresoc.v:78684$3643_Y - attribute \src "libresoc.v:78701.18-78701.110" - wire $not$libresoc.v:78701$3660_Y - attribute \src "libresoc.v:78677.18-78677.111" - wire $or$libresoc.v:78677$3636_Y - attribute \src "libresoc.v:78688.18-78688.110" - wire $or$libresoc.v:78688$3647_Y - attribute \src "libresoc.v:78691.18-78691.110" - wire $or$libresoc.v:78691$3650_Y - attribute \src "libresoc.v:78693.18-78693.110" - wire $or$libresoc.v:78693$3652_Y - attribute \src "libresoc.v:78695.18-78695.110" - wire $or$libresoc.v:78695$3654_Y - attribute \src "libresoc.v:78664.19-78664.124" - wire width 7 $pos$libresoc.v:78664$3621_Y - attribute \src "libresoc.v:78665.19-78665.124" - wire width 7 $pos$libresoc.v:78665$3623_Y - attribute \src "libresoc.v:78666.19-78666.123" - wire width 7 $pos$libresoc.v:78666$3625_Y - attribute \src "libresoc.v:78703.18-78703.111" - wire width 7 $pos$libresoc.v:78703$3663_Y - attribute \src "libresoc.v:78704.18-78704.111" - wire width 7 $pos$libresoc.v:78704$3665_Y - attribute \src "libresoc.v:78705.18-78705.111" - wire width 7 $pos$libresoc.v:78705$3667_Y - attribute \src "libresoc.v:78706.18-78706.113" - wire width 7 $pos$libresoc.v:78706$3669_Y - attribute \src "libresoc.v:78707.18-78707.121" - wire width 7 $pos$libresoc.v:78707$3671_Y + attribute \src "libresoc.v:79050.19-79050.122" + wire $and$libresoc.v:79050$3648_Y + attribute \src "libresoc.v:79051.19-79051.125" + wire $and$libresoc.v:79051$3649_Y + attribute \src "libresoc.v:79052.19-79052.126" + wire $and$libresoc.v:79052$3650_Y + attribute \src "libresoc.v:79059.18-79059.114" + wire $and$libresoc.v:79059$3657_Y + attribute \src "libresoc.v:79060.18-79060.116" + wire $and$libresoc.v:79060$3658_Y + attribute \src "libresoc.v:79062.18-79062.114" + wire $and$libresoc.v:79062$3660_Y + attribute \src "libresoc.v:79064.18-79064.110" + wire $and$libresoc.v:79064$3662_Y + attribute \src "libresoc.v:79076.18-79076.114" + wire $and$libresoc.v:79076$3674_Y + attribute \src "libresoc.v:79077.18-79077.116" + wire $and$libresoc.v:79077$3675_Y + attribute \src "libresoc.v:79079.18-79079.114" + wire $and$libresoc.v:79079$3677_Y + attribute \src "libresoc.v:79081.18-79081.110" + wire $and$libresoc.v:79081$3679_Y + attribute \src "libresoc.v:79046.19-79046.124" + wire $eq$libresoc.v:79046$3644_Y + attribute \src "libresoc.v:79047.19-79047.124" + wire $eq$libresoc.v:79047$3645_Y + attribute \src "libresoc.v:79048.19-79048.124" + wire $eq$libresoc.v:79048$3646_Y + attribute \src "libresoc.v:79049.19-79049.124" + wire $eq$libresoc.v:79049$3647_Y + attribute \src "libresoc.v:79053.19-79053.124" + wire $eq$libresoc.v:79053$3651_Y + attribute \src "libresoc.v:79054.18-79054.117" + wire $eq$libresoc.v:79054$3652_Y + attribute \src "libresoc.v:79055.18-79055.117" + wire $eq$libresoc.v:79055$3653_Y + attribute \src "libresoc.v:79057.18-79057.117" + wire $eq$libresoc.v:79057$3655_Y + attribute \src "libresoc.v:79058.18-79058.127" + wire $eq$libresoc.v:79058$3656_Y + attribute \src "libresoc.v:79061.18-79061.127" + wire $eq$libresoc.v:79061$3659_Y + attribute \src "libresoc.v:79065.18-79065.122" + wire $eq$libresoc.v:79065$3663_Y + attribute \src "libresoc.v:79066.18-79066.122" + wire $eq$libresoc.v:79066$3664_Y + attribute \src "libresoc.v:79068.18-79068.110" + wire $eq$libresoc.v:79068$3666_Y + attribute \src "libresoc.v:79069.18-79069.110" + wire $eq$libresoc.v:79069$3667_Y + attribute \src "libresoc.v:79071.18-79071.112" + wire $eq$libresoc.v:79071$3669_Y + attribute \src "libresoc.v:79073.18-79073.110" + wire $eq$libresoc.v:79073$3671_Y + attribute \src "libresoc.v:79075.18-79075.127" + wire $eq$libresoc.v:79075$3673_Y + attribute \src "libresoc.v:79078.18-79078.127" + wire $eq$libresoc.v:79078$3676_Y + attribute \src "libresoc.v:79043.19-79043.124" + wire width 7 $extend$libresoc.v:79043$3638_Y + attribute \src "libresoc.v:79044.19-79044.124" + wire width 7 $extend$libresoc.v:79044$3640_Y + attribute \src "libresoc.v:79045.19-79045.123" + wire width 7 $extend$libresoc.v:79045$3642_Y + attribute \src "libresoc.v:79082.18-79082.111" + wire width 7 $extend$libresoc.v:79082$3680_Y + attribute \src "libresoc.v:79083.18-79083.111" + wire width 7 $extend$libresoc.v:79083$3682_Y + attribute \src "libresoc.v:79084.18-79084.111" + wire width 7 $extend$libresoc.v:79084$3684_Y + attribute \src "libresoc.v:79085.18-79085.113" + wire width 7 $extend$libresoc.v:79085$3686_Y + attribute \src "libresoc.v:79086.18-79086.121" + wire width 7 $extend$libresoc.v:79086$3688_Y + attribute \src "libresoc.v:79063.18-79063.110" + wire $not$libresoc.v:79063$3661_Y + attribute \src "libresoc.v:79080.18-79080.110" + wire $not$libresoc.v:79080$3678_Y + attribute \src "libresoc.v:79056.18-79056.111" + wire $or$libresoc.v:79056$3654_Y + attribute \src "libresoc.v:79067.18-79067.110" + wire $or$libresoc.v:79067$3665_Y + attribute \src "libresoc.v:79070.18-79070.110" + wire $or$libresoc.v:79070$3668_Y + attribute \src "libresoc.v:79072.18-79072.110" + wire $or$libresoc.v:79072$3670_Y + attribute \src "libresoc.v:79074.18-79074.110" + wire $or$libresoc.v:79074$3672_Y + attribute \src "libresoc.v:79043.19-79043.124" + wire width 7 $pos$libresoc.v:79043$3639_Y + attribute \src "libresoc.v:79044.19-79044.124" + wire width 7 $pos$libresoc.v:79044$3641_Y + attribute \src "libresoc.v:79045.19-79045.123" + wire width 7 $pos$libresoc.v:79045$3643_Y + attribute \src "libresoc.v:79082.18-79082.111" + wire width 7 $pos$libresoc.v:79082$3681_Y + attribute \src "libresoc.v:79083.18-79083.111" + wire width 7 $pos$libresoc.v:79083$3683_Y + attribute \src "libresoc.v:79084.18-79084.111" + wire width 7 $pos$libresoc.v:79084$3685_Y + attribute \src "libresoc.v:79085.18-79085.113" + wire width 7 $pos$libresoc.v:79085$3687_Y + attribute \src "libresoc.v:79086.18-79086.121" + wire width 7 $pos$libresoc.v:79086$3689_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$90 @@ -123596,7 +124224,7 @@ module \dec2 wire width 7 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 39 \cia @@ -123648,43 +124276,43 @@ module \dec2 wire \dec2_exc_$signal$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_a_fast_a @@ -123700,7 +124328,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -123820,9 +124448,9 @@ module \dec2 wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire \dec_a_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_b_fast_b @@ -123847,7 +124475,7 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c @@ -123857,7 +124485,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123868,7 +124496,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield @@ -123886,7 +124514,7 @@ module \dec2 wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123897,7 +124525,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123906,7 +124534,7 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_out_cr_bitfield @@ -123916,9 +124544,9 @@ module \dec2 wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123927,13 +124555,13 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_cry_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -123950,7 +124578,7 @@ module \dec2 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123958,7 +124586,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123975,13 +124603,13 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124058,19 +124686,19 @@ module \dec2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" wire \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_fast_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o2_reg_o2 @@ -124090,7 +124718,7 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124218,9 +124846,9 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -124228,7 +124856,7 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -124238,20 +124866,20 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 8 \ea @@ -124273,7 +124901,7 @@ module \dec2 wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1214" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 22 \fast1 @@ -124308,9 +124936,9 @@ module \dec2 attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 14 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1199" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217" wire \illeg_ok - attribute \src "libresoc.v:76965.7-76965.15" + attribute \src "libresoc.v:77344.7-77344.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -124320,19 +124948,19 @@ module \dec2 wire width 2 output 48 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" wire width 32 \insn_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194" wire width 32 \insn_in$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" wire width 32 \insn_in$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" wire width 32 \insn_in$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396" wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124413,11 +125041,11 @@ module \dec2 wire width 7 output 41 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 43 \lk @@ -124427,9 +125055,9 @@ module \dec2 wire output 46 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 4 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \rc @@ -124457,9 +125085,9 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire width 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124697,7 +125325,7 @@ module \dec2 wire width 10 output 16 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 65 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode @@ -125147,8 +125775,8 @@ module \dec2 wire width 3 output 20 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" - cell $and $and$libresoc.v:78671$3630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" + cell $and $and$libresoc.v:79050$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125156,10 +125784,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78671$3630_Y + connect \Y $and$libresoc.v:79050$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" - cell $and $and$libresoc.v:78672$3631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" + cell $and $and$libresoc.v:79051$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125167,10 +125795,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78672$3631_Y + connect \Y $and$libresoc.v:79051$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" - cell $and $and$libresoc.v:78673$3632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" + cell $and $and$libresoc.v:79052$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125178,10 +125806,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:78673$3632_Y + connect \Y $and$libresoc.v:79052$3650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78680$3639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79059$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125189,10 +125817,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:78680$3639_Y + connect \Y $and$libresoc.v:79059$3657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78681$3640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79060$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125200,10 +125828,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78681$3640_Y + connect \Y $and$libresoc.v:79060$3658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78683$3642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79062$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125211,10 +125839,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:78683$3642_Y + connect \Y $and$libresoc.v:79062$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78685$3644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79064$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125222,10 +125850,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:78685$3644_Y + connect \Y $and$libresoc.v:79064$3662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78697$3656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79076$3674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125233,10 +125861,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:78697$3656_Y + connect \Y $and$libresoc.v:79076$3674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78698$3657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79077$3675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125244,10 +125872,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78698$3657_Y + connect \Y $and$libresoc.v:79077$3675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78700$3659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79079$3677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125255,10 +125883,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:78700$3659_Y + connect \Y $and$libresoc.v:79079$3677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78702$3661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79081$3679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125266,10 +125894,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:78702$3661_Y + connect \Y $and$libresoc.v:79081$3679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" - cell $eq $eq$libresoc.v:78667$3626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + cell $eq $eq$libresoc.v:79046$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125277,10 +125905,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78667$3626_Y + connect \Y $eq$libresoc.v:79046$3644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" - cell $eq $eq$libresoc.v:78668$3627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + cell $eq $eq$libresoc.v:79047$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125288,10 +125916,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:78668$3627_Y + connect \Y $eq$libresoc.v:79047$3645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" - cell $eq $eq$libresoc.v:78669$3628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + cell $eq $eq$libresoc.v:79048$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125299,10 +125927,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78669$3628_Y + connect \Y $eq$libresoc.v:79048$3646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" - cell $eq $eq$libresoc.v:78670$3629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + cell $eq $eq$libresoc.v:79049$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125310,10 +125938,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:78670$3629_Y + connect \Y $eq$libresoc.v:79049$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" - cell $eq $eq$libresoc.v:78674$3633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" + cell $eq $eq$libresoc.v:79053$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125321,10 +125949,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:78674$3633_Y + connect \Y $eq$libresoc.v:79053$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" - cell $eq $eq$libresoc.v:78675$3634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" + cell $eq $eq$libresoc.v:79054$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125332,10 +125960,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:78675$3634_Y + connect \Y $eq$libresoc.v:79054$3652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" - cell $eq $eq$libresoc.v:78676$3635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $eq $eq$libresoc.v:79055$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125343,10 +125971,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:78676$3635_Y + connect \Y $eq$libresoc.v:79055$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" - cell $eq $eq$libresoc.v:78678$3637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + cell $eq $eq$libresoc.v:79057$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125354,10 +125982,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:78678$3637_Y + connect \Y $eq$libresoc.v:79057$3655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:78679$3638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79058$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125365,10 +125993,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78679$3638_Y + connect \Y $eq$libresoc.v:79058$3656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:78682$3641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79061$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125376,10 +126004,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78682$3641_Y + connect \Y $eq$libresoc.v:79061$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:78686$3645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:79065$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125387,10 +126015,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78686$3645_Y + connect \Y $eq$libresoc.v:79065$3663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:78687$3646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:79066$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125398,10 +126026,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78687$3646_Y + connect \Y $eq$libresoc.v:79066$3664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78689$3648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79068$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125409,10 +126037,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:78689$3648_Y + connect \Y $eq$libresoc.v:79068$3666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78690$3649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79069$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125420,10 +126048,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:78690$3649_Y + connect \Y $eq$libresoc.v:79069$3667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78692$3651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79071$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125431,10 +126059,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:78692$3651_Y + connect \Y $eq$libresoc.v:79071$3669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:78694$3653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:79073$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125442,10 +126070,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:78694$3653_Y + connect \Y $eq$libresoc.v:79073$3671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:78696$3655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79075$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125453,10 +126081,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78696$3655_Y + connect \Y $eq$libresoc.v:79075$3673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:78699$3658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79078$3676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125464,90 +126092,90 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78699$3658_Y + connect \Y $eq$libresoc.v:79078$3676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78664$3620 + cell $pos $extend$libresoc.v:79043$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:78664$3620_Y + connect \Y $extend$libresoc.v:79043$3638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78665$3622 + cell $pos $extend$libresoc.v:79044$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:78665$3622_Y + connect \Y $extend$libresoc.v:79044$3640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78666$3624 + cell $pos $extend$libresoc.v:79045$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:78666$3624_Y + connect \Y $extend$libresoc.v:79045$3642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78703$3662 + cell $pos $extend$libresoc.v:79082$3680 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:78703$3662_Y + connect \Y $extend$libresoc.v:79082$3680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78704$3664 + cell $pos $extend$libresoc.v:79083$3682 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:78704$3664_Y + connect \Y $extend$libresoc.v:79083$3682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78705$3666 + cell $pos $extend$libresoc.v:79084$3684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:78705$3666_Y + connect \Y $extend$libresoc.v:79084$3684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78706$3668 + cell $pos $extend$libresoc.v:79085$3686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:78706$3668_Y + connect \Y $extend$libresoc.v:79085$3686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78707$3670 + cell $pos $extend$libresoc.v:79086$3688 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:78707$3670_Y + connect \Y $extend$libresoc.v:79086$3688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:78684$3643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79063$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78684$3643_Y + connect \Y $not$libresoc.v:79063$3661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:78701$3660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79080$3678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78701$3660_Y + connect \Y $not$libresoc.v:79080$3678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" - cell $or $or$libresoc.v:78677$3636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $or $or$libresoc.v:79056$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125555,10 +126183,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:78677$3636_Y + connect \Y $or$libresoc.v:79056$3654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:78688$3647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:79067$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125566,10 +126194,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:78688$3647_Y + connect \Y $or$libresoc.v:79067$3665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:78691$3650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79070$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125577,10 +126205,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:78691$3650_Y + connect \Y $or$libresoc.v:79070$3668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:78693$3652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79072$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125588,10 +126216,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:78693$3652_Y + connect \Y $or$libresoc.v:79072$3670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:78695$3654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:79074$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125599,74 +126227,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:78695$3654_Y + connect \Y $or$libresoc.v:79074$3672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78664$3621 + cell $pos $pos$libresoc.v:79043$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78664$3620_Y - connect \Y $pos$libresoc.v:78664$3621_Y + connect \A $extend$libresoc.v:79043$3638_Y + connect \Y $pos$libresoc.v:79043$3639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78665$3623 + cell $pos $pos$libresoc.v:79044$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78665$3622_Y - connect \Y $pos$libresoc.v:78665$3623_Y + connect \A $extend$libresoc.v:79044$3640_Y + connect \Y $pos$libresoc.v:79044$3641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78666$3625 + cell $pos $pos$libresoc.v:79045$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78666$3624_Y - connect \Y $pos$libresoc.v:78666$3625_Y + connect \A $extend$libresoc.v:79045$3642_Y + connect \Y $pos$libresoc.v:79045$3643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78703$3663 + cell $pos $pos$libresoc.v:79082$3681 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78703$3662_Y - connect \Y $pos$libresoc.v:78703$3663_Y + connect \A $extend$libresoc.v:79082$3680_Y + connect \Y $pos$libresoc.v:79082$3681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78704$3665 + cell $pos $pos$libresoc.v:79083$3683 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78704$3664_Y - connect \Y $pos$libresoc.v:78704$3665_Y + connect \A $extend$libresoc.v:79083$3682_Y + connect \Y $pos$libresoc.v:79083$3683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78705$3667 + cell $pos $pos$libresoc.v:79084$3685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78705$3666_Y - connect \Y $pos$libresoc.v:78705$3667_Y + connect \A $extend$libresoc.v:79084$3684_Y + connect \Y $pos$libresoc.v:79084$3685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78706$3669 + cell $pos $pos$libresoc.v:79085$3687 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78706$3668_Y - connect \Y $pos$libresoc.v:78706$3669_Y + connect \A $extend$libresoc.v:79085$3686_Y + connect \Y $pos$libresoc.v:79085$3687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78707$3671 + cell $pos $pos$libresoc.v:79086$3689 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78707$3670_Y - connect \Y $pos$libresoc.v:78707$3671_Y + connect \A $extend$libresoc.v:79086$3688_Y + connect \Y $pos$libresoc.v:79086$3689_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:78708.13-78745.4" + attribute \src "libresoc.v:79087.13-79124.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -125706,7 +126334,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78746.9-78761.4" + attribute \src "libresoc.v:79125.9-79140.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -125724,7 +126352,7 @@ module \dec2 connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:78762.9-78772.4" + attribute \src "libresoc.v:79141.9-79151.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -125737,7 +126365,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78773.9-78779.4" + attribute \src "libresoc.v:79152.9-79158.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -125746,7 +126374,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78780.13-78799.4" + attribute \src "libresoc.v:79159.13-79178.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -125768,7 +126396,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78800.14-78812.4" + attribute \src "libresoc.v:79179.14-79191.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -125783,7 +126411,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78813.9-78826.4" + attribute \src "libresoc.v:79192.9-79205.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -125799,7 +126427,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:78827.10-78836.4" + attribute \src "libresoc.v:79206.10-79215.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -125811,7 +126439,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78837.16-78843.4" + attribute \src "libresoc.v:79216.16-79222.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -125820,32 +126448,32 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78844.16-78849.4" + attribute \src "libresoc.v:79223.16-79228.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:76965.7-76965.20" - process $proc$libresoc.v:76965$3730 + attribute \src "libresoc.v:77344.7-77344.20" + process $proc$libresoc.v:77344$3748 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:78850.3-78864.6" - process $proc$libresoc.v:78850$3672 + attribute \src "libresoc.v:79229.3-79243.6" + process $proc$libresoc.v:79229$3690 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78851.5-78851.29" + attribute \src "libresoc.v:79230.5-79230.29" switch \initial - attribute \src "libresoc.v:78851.9-78851.17" + attribute \src "libresoc.v:79230.9-79230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$83 \$75 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125863,18 +126491,18 @@ module \dec2 sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:78865.3-78874.6" - process $proc$libresoc.v:78865$3673 + attribute \src "libresoc.v:79244.3-79253.6" + process $proc$libresoc.v:79244$3691 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78866.5-78866.29" + attribute \src "libresoc.v:79245.5-79245.29" switch \initial - attribute \src "libresoc.v:78866.9-78866.17" + attribute \src "libresoc.v:79245.9-79245.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125886,18 +126514,18 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:78875.3-78887.6" - process $proc$libresoc.v:78875$3674 + attribute \src "libresoc.v:79254.3-79266.6" + process $proc$libresoc.v:79254$3692 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78876.5-78876.29" + attribute \src "libresoc.v:79255.5-79255.29" switch \initial - attribute \src "libresoc.v:78876.9-78876.17" + attribute \src "libresoc.v:79255.9-79255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$49 \$41 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125913,19 +126541,19 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:78888.3-78903.6" - process $proc$libresoc.v:78888$3675 + attribute \src "libresoc.v:79267.3-79282.6" + process $proc$libresoc.v:79267$3693 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78889.5-78889.29" + attribute \src "libresoc.v:79268.5-79268.29" switch \initial - attribute \src "libresoc.v:78889.9-78889.17" + attribute \src "libresoc.v:79268.9-79268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125934,7 +126562,7 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125946,18 +126574,18 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:78904.3-78913.6" - process $proc$libresoc.v:78904$3676 + attribute \src "libresoc.v:79283.3-79292.6" + process $proc$libresoc.v:79283$3694 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78905.5-78905.29" + attribute \src "libresoc.v:79284.5-79284.29" switch \initial - attribute \src "libresoc.v:78905.9-78905.17" + attribute \src "libresoc.v:79284.9-79284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125969,18 +126597,18 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:78914.3-78923.6" - process $proc$libresoc.v:78914$3677 + attribute \src "libresoc.v:79293.3-79302.6" + process $proc$libresoc.v:79293$3695 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78915.5-78915.29" + attribute \src "libresoc.v:79294.5-79294.29" switch \initial - attribute \src "libresoc.v:78915.9-78915.17" + attribute \src "libresoc.v:79294.9-79294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125992,18 +126620,18 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:78924.3-78947.6" - process $proc$libresoc.v:78924$3678 + attribute \src "libresoc.v:79303.3-79326.6" + process $proc$libresoc.v:79303$3696 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78925.5-78925.29" + attribute \src "libresoc.v:79304.5-79304.29" switch \initial - attribute \src "libresoc.v:78925.9-78925.17" + attribute \src "libresoc.v:79304.9-79304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 @@ -126017,7 +126645,7 @@ module \dec2 case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126032,8 +126660,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:78948.3-79105.6" - process $proc$libresoc.v:78948$3679 + attribute \src "libresoc.v:79327.3-79484.6" + process $proc$libresoc.v:79327$3697 assign { } { } assign { } { } assign { } { } @@ -126110,22 +126738,22 @@ module \dec2 assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[6:0] $1\cr_in2[6:0] - assign $0\cr_in2$1[6:0]$3680 $1\cr_in2$1[6:0]$3690 + assign $0\cr_in2$1[6:0]$3698 $1\cr_in2$1[6:0]$3708 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3681 $1\cr_in2_ok$2[0:0]$3691 + assign $0\cr_in2_ok$2[0:0]$3699 $1\cr_in2_ok$2[0:0]$3709 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3682 $1\exc_$signal[0:0]$3692 - assign $0\exc_$signal$3[0:0]$3683 $1\exc_$signal$3[0:0]$3693 - assign $0\exc_$signal$4[0:0]$3684 $1\exc_$signal$4[0:0]$3694 - assign $0\exc_$signal$5[0:0]$3685 $1\exc_$signal$5[0:0]$3695 - assign $0\exc_$signal$6[0:0]$3686 $1\exc_$signal$6[0:0]$3696 - assign $0\exc_$signal$7[0:0]$3687 $1\exc_$signal$7[0:0]$3697 - assign $0\exc_$signal$8[0:0]$3688 $1\exc_$signal$8[0:0]$3698 - assign $0\exc_$signal$9[0:0]$3689 $1\exc_$signal$9[0:0]$3699 + assign $0\exc_$signal[0:0]$3700 $1\exc_$signal[0:0]$3710 + assign $0\exc_$signal$3[0:0]$3701 $1\exc_$signal$3[0:0]$3711 + assign $0\exc_$signal$4[0:0]$3702 $1\exc_$signal$4[0:0]$3712 + assign $0\exc_$signal$5[0:0]$3703 $1\exc_$signal$5[0:0]$3713 + assign $0\exc_$signal$6[0:0]$3704 $1\exc_$signal$6[0:0]$3714 + assign $0\exc_$signal$7[0:0]$3705 $1\exc_$signal$7[0:0]$3715 + assign $0\exc_$signal$8[0:0]$3706 $1\exc_$signal$8[0:0]$3716 + assign $0\exc_$signal$9[0:0]$3707 $1\exc_$signal$9[0:0]$3717 assign { } { } assign { } { } assign { } { } @@ -126161,13 +126789,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:78949.5-78949.29" + attribute \src "libresoc.v:79328.5-79328.29" switch \initial - attribute \src "libresoc.v:78949.9-78949.17" + attribute \src "libresoc.v:79328.9-79328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1227" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -126247,22 +126875,22 @@ module \dec2 assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] assign $1\cr_in2[6:0] $2\cr_in2[6:0] - assign $1\cr_in2$1[6:0]$3690 $2\cr_in2$1[6:0]$3700 + assign $1\cr_in2$1[6:0]$3708 $2\cr_in2$1[6:0]$3718 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3691 $2\cr_in2_ok$2[0:0]$3701 + assign $1\cr_in2_ok$2[0:0]$3709 $2\cr_in2_ok$2[0:0]$3719 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3692 $2\exc_$signal[0:0]$3702 - assign $1\exc_$signal$3[0:0]$3693 $2\exc_$signal$3[0:0]$3703 - assign $1\exc_$signal$4[0:0]$3694 $2\exc_$signal$4[0:0]$3704 - assign $1\exc_$signal$5[0:0]$3695 $2\exc_$signal$5[0:0]$3705 - assign $1\exc_$signal$6[0:0]$3696 $2\exc_$signal$6[0:0]$3706 - assign $1\exc_$signal$7[0:0]$3697 $2\exc_$signal$7[0:0]$3707 - assign $1\exc_$signal$8[0:0]$3698 $2\exc_$signal$8[0:0]$3708 - assign $1\exc_$signal$9[0:0]$3699 $2\exc_$signal$9[0:0]$3709 + assign $1\exc_$signal[0:0]$3710 $2\exc_$signal[0:0]$3720 + assign $1\exc_$signal$3[0:0]$3711 $2\exc_$signal$3[0:0]$3721 + assign $1\exc_$signal$4[0:0]$3712 $2\exc_$signal$4[0:0]$3722 + assign $1\exc_$signal$5[0:0]$3713 $2\exc_$signal$5[0:0]$3723 + assign $1\exc_$signal$6[0:0]$3714 $2\exc_$signal$6[0:0]$3724 + assign $1\exc_$signal$7[0:0]$3715 $2\exc_$signal$7[0:0]$3725 + assign $1\exc_$signal$8[0:0]$3716 $2\exc_$signal$8[0:0]$3726 + assign $1\exc_$signal$9[0:0]$3717 $2\exc_$signal$9[0:0]$3727 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] @@ -126289,7 +126917,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126352,7 +126980,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3709 $2\exc_$signal$8[0:0]$3708 $2\exc_$signal$7[0:0]$3707 $2\exc_$signal$6[0:0]$3706 $2\exc_$signal$5[0:0]$3705 $2\exc_$signal$4[0:0]$3704 $2\exc_$signal$3[0:0]$3703 $2\exc_$signal[0:0]$3702 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3701 $2\cr_in2$1[6:0]$3700 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3727 $2\exc_$signal$8[0:0]$3726 $2\exc_$signal$7[0:0]$3725 $2\exc_$signal$6[0:0]$3724 $2\exc_$signal$5[0:0]$3723 $2\exc_$signal$4[0:0]$3722 $2\exc_$signal$3[0:0]$3721 $2\exc_$signal[0:0]$3720 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3719 $2\cr_in2$1[6:0]$3718 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 assign $2\fn_unit[13:0] 14'00000010000000 @@ -126438,22 +127066,22 @@ module \dec2 assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $3\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3700 $3\cr_in2$1[6:0]$3710 + assign $2\cr_in2$1[6:0]$3718 $3\cr_in2$1[6:0]$3728 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3701 $3\cr_in2_ok$2[0:0]$3711 + assign $2\cr_in2_ok$2[0:0]$3719 $3\cr_in2_ok$2[0:0]$3729 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3702 $3\exc_$signal[0:0]$3712 - assign $2\exc_$signal$3[0:0]$3703 $3\exc_$signal$3[0:0]$3713 - assign $2\exc_$signal$4[0:0]$3704 $3\exc_$signal$4[0:0]$3714 - assign $2\exc_$signal$5[0:0]$3705 $3\exc_$signal$5[0:0]$3715 - assign $2\exc_$signal$6[0:0]$3706 $3\exc_$signal$6[0:0]$3716 - assign $2\exc_$signal$7[0:0]$3707 $3\exc_$signal$7[0:0]$3717 - assign $2\exc_$signal$8[0:0]$3708 $3\exc_$signal$8[0:0]$3718 - assign $2\exc_$signal$9[0:0]$3709 $3\exc_$signal$9[0:0]$3719 + assign $2\exc_$signal[0:0]$3720 $3\exc_$signal[0:0]$3730 + assign $2\exc_$signal$3[0:0]$3721 $3\exc_$signal$3[0:0]$3731 + assign $2\exc_$signal$4[0:0]$3722 $3\exc_$signal$4[0:0]$3732 + assign $2\exc_$signal$5[0:0]$3723 $3\exc_$signal$5[0:0]$3733 + assign $2\exc_$signal$6[0:0]$3724 $3\exc_$signal$6[0:0]$3734 + assign $2\exc_$signal$7[0:0]$3725 $3\exc_$signal$7[0:0]$3735 + assign $2\exc_$signal$8[0:0]$3726 $3\exc_$signal$8[0:0]$3736 + assign $2\exc_$signal$9[0:0]$3727 $3\exc_$signal$9[0:0]$3737 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] @@ -126480,7 +127108,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1231" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126543,7 +127171,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 @@ -126612,13 +127240,13 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign { $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end @@ -126700,22 +127328,22 @@ module \dec2 assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $4\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3700 $4\cr_in2$1[6:0]$3720 + assign $2\cr_in2$1[6:0]$3718 $4\cr_in2$1[6:0]$3738 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3701 $4\cr_in2_ok$2[0:0]$3721 + assign $2\cr_in2_ok$2[0:0]$3719 $4\cr_in2_ok$2[0:0]$3739 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3702 $4\exc_$signal[0:0]$3722 - assign $2\exc_$signal$3[0:0]$3703 $4\exc_$signal$3[0:0]$3723 - assign $2\exc_$signal$4[0:0]$3704 $4\exc_$signal$4[0:0]$3724 - assign $2\exc_$signal$5[0:0]$3705 $4\exc_$signal$5[0:0]$3725 - assign $2\exc_$signal$6[0:0]$3706 $4\exc_$signal$6[0:0]$3726 - assign $2\exc_$signal$7[0:0]$3707 $4\exc_$signal$7[0:0]$3727 - assign $2\exc_$signal$8[0:0]$3708 $4\exc_$signal$8[0:0]$3728 - assign $2\exc_$signal$9[0:0]$3709 $4\exc_$signal$9[0:0]$3729 + assign $2\exc_$signal[0:0]$3720 $4\exc_$signal[0:0]$3740 + assign $2\exc_$signal$3[0:0]$3721 $4\exc_$signal$3[0:0]$3741 + assign $2\exc_$signal$4[0:0]$3722 $4\exc_$signal$4[0:0]$3742 + assign $2\exc_$signal$5[0:0]$3723 $4\exc_$signal$5[0:0]$3743 + assign $2\exc_$signal$6[0:0]$3724 $4\exc_$signal$6[0:0]$3744 + assign $2\exc_$signal$7[0:0]$3725 $4\exc_$signal$7[0:0]$3745 + assign $2\exc_$signal$8[0:0]$3726 $4\exc_$signal$8[0:0]$3746 + assign $2\exc_$signal$9[0:0]$3727 $4\exc_$signal$9[0:0]$3747 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] @@ -126742,7 +127370,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1237" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126805,7 +127433,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -126874,7 +127502,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -126945,7 +127573,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127014,7 +127642,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127083,7 +127711,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127152,7 +127780,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127221,9 +127849,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127241,7 +127869,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127277,22 +127905,22 @@ module \dec2 update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[6:0] - update \cr_in2$1 $0\cr_in2$1[6:0]$3680 + update \cr_in2$1 $0\cr_in2$1[6:0]$3698 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3681 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3699 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3682 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3683 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3684 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3685 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3686 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3687 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3688 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3689 + update \exc_$signal $0\exc_$signal[0:0]$3700 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3701 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3702 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3703 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3704 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3705 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3706 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3707 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] @@ -127320,50 +127948,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:78664$3621_Y - connect \$102 $pos$libresoc.v:78665$3623_Y - connect \$104 $pos$libresoc.v:78666$3625_Y - connect \$106 $eq$libresoc.v:78667$3626_Y - connect \$108 $eq$libresoc.v:78668$3627_Y - connect \$110 $eq$libresoc.v:78669$3628_Y - connect \$112 $eq$libresoc.v:78670$3629_Y - connect \$114 $and$libresoc.v:78671$3630_Y - connect \$116 $and$libresoc.v:78672$3631_Y - connect \$118 $and$libresoc.v:78673$3632_Y - connect \$120 $eq$libresoc.v:78674$3633_Y - connect \$28 $eq$libresoc.v:78675$3634_Y - connect \$30 $eq$libresoc.v:78676$3635_Y - connect \$32 $or$libresoc.v:78677$3636_Y - connect \$34 $eq$libresoc.v:78678$3637_Y - connect \$37 $eq$libresoc.v:78679$3638_Y - connect \$39 $and$libresoc.v:78680$3639_Y - connect \$41 $and$libresoc.v:78681$3640_Y - connect \$43 $eq$libresoc.v:78682$3641_Y - connect \$45 $and$libresoc.v:78683$3642_Y - connect \$47 $not$libresoc.v:78684$3643_Y - connect \$49 $and$libresoc.v:78685$3644_Y - connect \$51 $eq$libresoc.v:78686$3645_Y - connect \$53 $eq$libresoc.v:78687$3646_Y - connect \$55 $or$libresoc.v:78688$3647_Y - connect \$57 $eq$libresoc.v:78689$3648_Y - connect \$59 $eq$libresoc.v:78690$3649_Y - connect \$61 $or$libresoc.v:78691$3650_Y - connect \$63 $eq$libresoc.v:78692$3651_Y - connect \$65 $or$libresoc.v:78693$3652_Y - connect \$67 $eq$libresoc.v:78694$3653_Y - connect \$69 $or$libresoc.v:78695$3654_Y - connect \$71 $eq$libresoc.v:78696$3655_Y - connect \$73 $and$libresoc.v:78697$3656_Y - connect \$75 $and$libresoc.v:78698$3657_Y - connect \$77 $eq$libresoc.v:78699$3658_Y - connect \$79 $and$libresoc.v:78700$3659_Y - connect \$81 $not$libresoc.v:78701$3660_Y - connect \$83 $and$libresoc.v:78702$3661_Y - connect \$90 $pos$libresoc.v:78703$3663_Y - connect \$92 $pos$libresoc.v:78704$3665_Y - connect \$94 $pos$libresoc.v:78705$3667_Y - connect \$96 $pos$libresoc.v:78706$3669_Y - connect \$98 $pos$libresoc.v:78707$3671_Y + connect \$100 $pos$libresoc.v:79043$3639_Y + connect \$102 $pos$libresoc.v:79044$3641_Y + connect \$104 $pos$libresoc.v:79045$3643_Y + connect \$106 $eq$libresoc.v:79046$3644_Y + connect \$108 $eq$libresoc.v:79047$3645_Y + connect \$110 $eq$libresoc.v:79048$3646_Y + connect \$112 $eq$libresoc.v:79049$3647_Y + connect \$114 $and$libresoc.v:79050$3648_Y + connect \$116 $and$libresoc.v:79051$3649_Y + connect \$118 $and$libresoc.v:79052$3650_Y + connect \$120 $eq$libresoc.v:79053$3651_Y + connect \$28 $eq$libresoc.v:79054$3652_Y + connect \$30 $eq$libresoc.v:79055$3653_Y + connect \$32 $or$libresoc.v:79056$3654_Y + connect \$34 $eq$libresoc.v:79057$3655_Y + connect \$37 $eq$libresoc.v:79058$3656_Y + connect \$39 $and$libresoc.v:79059$3657_Y + connect \$41 $and$libresoc.v:79060$3658_Y + connect \$43 $eq$libresoc.v:79061$3659_Y + connect \$45 $and$libresoc.v:79062$3660_Y + connect \$47 $not$libresoc.v:79063$3661_Y + connect \$49 $and$libresoc.v:79064$3662_Y + connect \$51 $eq$libresoc.v:79065$3663_Y + connect \$53 $eq$libresoc.v:79066$3664_Y + connect \$55 $or$libresoc.v:79067$3665_Y + connect \$57 $eq$libresoc.v:79068$3666_Y + connect \$59 $eq$libresoc.v:79069$3667_Y + connect \$61 $or$libresoc.v:79070$3668_Y + connect \$63 $eq$libresoc.v:79071$3669_Y + connect \$65 $or$libresoc.v:79072$3670_Y + connect \$67 $eq$libresoc.v:79073$3671_Y + connect \$69 $or$libresoc.v:79074$3672_Y + connect \$71 $eq$libresoc.v:79075$3673_Y + connect \$73 $and$libresoc.v:79076$3674_Y + connect \$75 $and$libresoc.v:79077$3675_Y + connect \$77 $eq$libresoc.v:79078$3676_Y + connect \$79 $and$libresoc.v:79079$3677_Y + connect \$81 $not$libresoc.v:79080$3678_Y + connect \$83 $and$libresoc.v:79081$3679_Y + connect \$90 $pos$libresoc.v:79082$3681_Y + connect \$92 $pos$libresoc.v:79083$3683_Y + connect \$94 $pos$libresoc.v:79084$3685_Y + connect \$96 $pos$libresoc.v:79085$3687_Y + connect \$98 $pos$libresoc.v:79086$3689_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -127444,157 +128072,161 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79189.1-79849.10" +attribute \src "libresoc.v:79568.1-80248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 - attribute \src "libresoc.v:79788.3-79797.6" + attribute \src "libresoc.v:80187.3-80196.6" wire width 2 $0\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79798.3-79807.6" + attribute \src "libresoc.v:80197.3-80206.6" wire width 2 $0\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79668.3-79677.6" + attribute \src "libresoc.v:80067.3-80076.6" wire width 8 $0\dec22_asmcode[7:0] - attribute \src "libresoc.v:79708.3-79717.6" + attribute \src "libresoc.v:80107.3-80116.6" wire $0\dec22_br[0:0] - attribute \src "libresoc.v:79538.3-79547.6" + attribute \src "libresoc.v:79927.3-79936.6" wire width 3 $0\dec22_cr_in[2:0] - attribute \src "libresoc.v:79548.3-79557.6" + attribute \src "libresoc.v:79937.3-79946.6" wire width 3 $0\dec22_cr_out[2:0] - attribute \src "libresoc.v:79658.3-79667.6" + attribute \src "libresoc.v:80057.3-80066.6" wire width 2 $0\dec22_cry_in[1:0] - attribute \src "libresoc.v:79698.3-79707.6" + attribute \src "libresoc.v:80097.3-80106.6" wire $0\dec22_cry_out[0:0] - attribute \src "libresoc.v:79748.3-79757.6" + attribute \src "libresoc.v:80137.3-80146.6" wire width 5 $0\dec22_form[4:0] - attribute \src "libresoc.v:79528.3-79537.6" + attribute \src "libresoc.v:79917.3-79926.6" wire width 14 $0\dec22_function_unit[13:0] - attribute \src "libresoc.v:79808.3-79817.6" + attribute \src "libresoc.v:80207.3-80216.6" wire width 3 $0\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79818.3-79827.6" + attribute \src "libresoc.v:80217.3-80226.6" wire width 4 $0\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79828.3-79837.6" + attribute \src "libresoc.v:80227.3-80236.6" wire width 2 $0\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79638.3-79647.6" + attribute \src "libresoc.v:80027.3-80036.6" wire width 7 $0\dec22_internal_op[6:0] - attribute \src "libresoc.v:79678.3-79687.6" + attribute \src "libresoc.v:80077.3-80086.6" wire $0\dec22_inv_a[0:0] - attribute \src "libresoc.v:79688.3-79697.6" + attribute \src "libresoc.v:80087.3-80096.6" wire $0\dec22_inv_out[0:0] - attribute \src "libresoc.v:79738.3-79747.6" + attribute \src "libresoc.v:80147.3-80156.6" wire $0\dec22_is_32b[0:0] - attribute \src "libresoc.v:79618.3-79627.6" + attribute \src "libresoc.v:80017.3-80026.6" wire width 4 $0\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79768.3-79777.6" + attribute \src "libresoc.v:80167.3-80176.6" wire $0\dec22_lk[0:0] - attribute \src "libresoc.v:79838.3-79847.6" + attribute \src "libresoc.v:80237.3-80246.6" wire width 3 $0\dec22_out_sel[2:0] - attribute \src "libresoc.v:79648.3-79657.6" + attribute \src "libresoc.v:80047.3-80056.6" wire width 2 $0\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79728.3-79737.6" + attribute \src "libresoc.v:80127.3-80136.6" wire $0\dec22_rsrv[0:0] - attribute \src "libresoc.v:79778.3-79787.6" + attribute \src "libresoc.v:80177.3-80186.6" wire $0\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79758.3-79767.6" + attribute \src "libresoc.v:80157.3-80166.6" wire $0\dec22_sgn[0:0] - attribute \src "libresoc.v:79718.3-79727.6" + attribute \src "libresoc.v:80117.3-80126.6" wire $0\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79598.3-79607.6" + attribute \src "libresoc.v:79997.3-80006.6" wire width 3 $0\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79608.3-79617.6" + attribute \src "libresoc.v:80007.3-80016.6" wire width 3 $0\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79558.3-79567.6" + attribute \src "libresoc.v:79947.3-79956.6" wire width 3 $0\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79568.3-79577.6" + attribute \src "libresoc.v:79957.3-79966.6" wire width 3 $0\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79578.3-79587.6" + attribute \src "libresoc.v:79967.3-79976.6" wire width 3 $0\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79588.3-79597.6" + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $0\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" wire width 3 $0\dec22_sv_out[2:0] - attribute \src "libresoc.v:79628.3-79637.6" + attribute \src "libresoc.v:80037.3-80046.6" wire width 2 $0\dec22_upd[1:0] - attribute \src "libresoc.v:79190.7-79190.20" + attribute \src "libresoc.v:79569.7-79569.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79788.3-79797.6" + attribute \src "libresoc.v:80187.3-80196.6" wire width 2 $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79798.3-79807.6" + attribute \src "libresoc.v:80197.3-80206.6" wire width 2 $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79668.3-79677.6" + attribute \src "libresoc.v:80067.3-80076.6" wire width 8 $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79708.3-79717.6" + attribute \src "libresoc.v:80107.3-80116.6" wire $1\dec22_br[0:0] - attribute \src "libresoc.v:79538.3-79547.6" + attribute \src "libresoc.v:79927.3-79936.6" wire width 3 $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79548.3-79557.6" + attribute \src "libresoc.v:79937.3-79946.6" wire width 3 $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79658.3-79667.6" + attribute \src "libresoc.v:80057.3-80066.6" wire width 2 $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79698.3-79707.6" + attribute \src "libresoc.v:80097.3-80106.6" wire $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:79748.3-79757.6" + attribute \src "libresoc.v:80137.3-80146.6" wire width 5 $1\dec22_form[4:0] - attribute \src "libresoc.v:79528.3-79537.6" + attribute \src "libresoc.v:79917.3-79926.6" wire width 14 $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79808.3-79817.6" + attribute \src "libresoc.v:80207.3-80216.6" wire width 3 $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79818.3-79827.6" + attribute \src "libresoc.v:80217.3-80226.6" wire width 4 $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79828.3-79837.6" + attribute \src "libresoc.v:80227.3-80236.6" wire width 2 $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79638.3-79647.6" + attribute \src "libresoc.v:80027.3-80036.6" wire width 7 $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79678.3-79687.6" + attribute \src "libresoc.v:80077.3-80086.6" wire $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79688.3-79697.6" + attribute \src "libresoc.v:80087.3-80096.6" wire $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:79738.3-79747.6" + attribute \src "libresoc.v:80147.3-80156.6" wire $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:79618.3-79627.6" + attribute \src "libresoc.v:80017.3-80026.6" wire width 4 $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79768.3-79777.6" + attribute \src "libresoc.v:80167.3-80176.6" wire $1\dec22_lk[0:0] - attribute \src "libresoc.v:79838.3-79847.6" + attribute \src "libresoc.v:80237.3-80246.6" wire width 3 $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:79648.3-79657.6" + attribute \src "libresoc.v:80047.3-80056.6" wire width 2 $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79728.3-79737.6" + attribute \src "libresoc.v:80127.3-80136.6" wire $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:79778.3-79787.6" + attribute \src "libresoc.v:80177.3-80186.6" wire $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79758.3-79767.6" + attribute \src "libresoc.v:80157.3-80166.6" wire $1\dec22_sgn[0:0] - attribute \src "libresoc.v:79718.3-79727.6" + attribute \src "libresoc.v:80117.3-80126.6" wire $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79598.3-79607.6" + attribute \src "libresoc.v:79997.3-80006.6" wire width 3 $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79608.3-79617.6" + attribute \src "libresoc.v:80007.3-80016.6" wire width 3 $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79558.3-79567.6" + attribute \src "libresoc.v:79947.3-79956.6" wire width 3 $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79568.3-79577.6" + attribute \src "libresoc.v:79957.3-79966.6" wire width 3 $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79578.3-79587.6" + attribute \src "libresoc.v:79967.3-79976.6" wire width 3 $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79588.3-79597.6" + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" wire width 3 $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79628.3-79637.6" + attribute \src "libresoc.v:80037.3-80046.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -127604,7 +128236,7 @@ module \dec22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127613,16 +128245,16 @@ module \dec22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -127654,7 +128286,7 @@ module \dec22 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -127671,7 +128303,7 @@ module \dec22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -127679,7 +128311,7 @@ module \dec22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127696,13 +128328,13 @@ module \dec22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127779,46 +128411,46 @@ module \dec22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127826,8 +128458,8 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec22_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127835,8 +128467,8 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec22_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127844,7 +128476,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127853,7 +128485,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127862,7 +128494,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127871,41 +128503,50 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec22_upd - attribute \src "libresoc.v:79190.7-79190.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec22_upd + attribute \src "libresoc.v:79569.7-79569.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79190.7-79190.20" - process $proc$libresoc.v:79190$3763 + attribute \src "libresoc.v:79569.7-79569.20" + process $proc$libresoc.v:79569$3782 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79528.3-79537.6" - process $proc$libresoc.v:79528$3731 + attribute \src "libresoc.v:79917.3-79926.6" + process $proc$libresoc.v:79917$3749 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79529.5-79529.29" + attribute \src "libresoc.v:79918.5-79918.29" switch \initial - attribute \src "libresoc.v:79529.9-79529.17" + attribute \src "libresoc.v:79918.9-79918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127917,18 +128558,18 @@ module \dec22 sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end - attribute \src "libresoc.v:79538.3-79547.6" - process $proc$libresoc.v:79538$3732 + attribute \src "libresoc.v:79927.3-79936.6" + process $proc$libresoc.v:79927$3750 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79539.5-79539.29" + attribute \src "libresoc.v:79928.5-79928.29" switch \initial - attribute \src "libresoc.v:79539.9-79539.17" + attribute \src "libresoc.v:79928.9-79928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127940,18 +128581,18 @@ module \dec22 sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end - attribute \src "libresoc.v:79548.3-79557.6" - process $proc$libresoc.v:79548$3733 + attribute \src "libresoc.v:79937.3-79946.6" + process $proc$libresoc.v:79937$3751 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79549.5-79549.29" + attribute \src "libresoc.v:79938.5-79938.29" switch \initial - attribute \src "libresoc.v:79549.9-79549.17" + attribute \src "libresoc.v:79938.9-79938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127963,18 +128604,18 @@ module \dec22 sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end - attribute \src "libresoc.v:79558.3-79567.6" - process $proc$libresoc.v:79558$3734 + attribute \src "libresoc.v:79947.3-79956.6" + process $proc$libresoc.v:79947$3752 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79559.5-79559.29" + attribute \src "libresoc.v:79948.5-79948.29" switch \initial - attribute \src "libresoc.v:79559.9-79559.17" + attribute \src "libresoc.v:79948.9-79948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127986,18 +128627,18 @@ module \dec22 sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end - attribute \src "libresoc.v:79568.3-79577.6" - process $proc$libresoc.v:79568$3735 + attribute \src "libresoc.v:79957.3-79966.6" + process $proc$libresoc.v:79957$3753 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79569.5-79569.29" + attribute \src "libresoc.v:79958.5-79958.29" switch \initial - attribute \src "libresoc.v:79569.9-79569.17" + attribute \src "libresoc.v:79958.9-79958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128009,18 +128650,18 @@ module \dec22 sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end - attribute \src "libresoc.v:79578.3-79587.6" - process $proc$libresoc.v:79578$3736 + attribute \src "libresoc.v:79967.3-79976.6" + process $proc$libresoc.v:79967$3754 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79579.5-79579.29" + attribute \src "libresoc.v:79968.5-79968.29" switch \initial - attribute \src "libresoc.v:79579.9-79579.17" + attribute \src "libresoc.v:79968.9-79968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128032,18 +128673,18 @@ module \dec22 sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end - attribute \src "libresoc.v:79588.3-79597.6" - process $proc$libresoc.v:79588$3737 + attribute \src "libresoc.v:79977.3-79986.6" + process $proc$libresoc.v:79977$3755 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79589.5-79589.29" + attribute \src "libresoc.v:79978.5-79978.29" switch \initial - attribute \src "libresoc.v:79589.9-79589.17" + attribute \src "libresoc.v:79978.9-79978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128055,18 +128696,41 @@ module \dec22 sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end - attribute \src "libresoc.v:79598.3-79607.6" - process $proc$libresoc.v:79598$3738 + attribute \src "libresoc.v:79987.3-79996.6" + process $proc$libresoc.v:79987$3756 + assign { } { } + assign { } { } + assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79988.5-79988.29" + switch \initial + attribute \src "libresoc.v:79988.9-79988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out2[2:0] 3'000 + case + assign $1\dec22_sv_out2[2:0] 3'000 + end + sync always + update \dec22_sv_out2 $0\dec22_sv_out2[2:0] + end + attribute \src "libresoc.v:79997.3-80006.6" + process $proc$libresoc.v:79997$3757 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79599.5-79599.29" + attribute \src "libresoc.v:79998.5-79998.29" switch \initial - attribute \src "libresoc.v:79599.9-79599.17" + attribute \src "libresoc.v:79998.9-79998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128078,18 +128742,18 @@ module \dec22 sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end - attribute \src "libresoc.v:79608.3-79617.6" - process $proc$libresoc.v:79608$3739 + attribute \src "libresoc.v:80007.3-80016.6" + process $proc$libresoc.v:80007$3758 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79609.5-79609.29" + attribute \src "libresoc.v:80008.5-80008.29" switch \initial - attribute \src "libresoc.v:79609.9-79609.17" + attribute \src "libresoc.v:80008.9-80008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128101,18 +128765,18 @@ module \dec22 sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end - attribute \src "libresoc.v:79618.3-79627.6" - process $proc$libresoc.v:79618$3740 + attribute \src "libresoc.v:80017.3-80026.6" + process $proc$libresoc.v:80017$3759 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79619.5-79619.29" + attribute \src "libresoc.v:80018.5-80018.29" switch \initial - attribute \src "libresoc.v:79619.9-79619.17" + attribute \src "libresoc.v:80018.9-80018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128124,64 +128788,64 @@ module \dec22 sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end - attribute \src "libresoc.v:79628.3-79637.6" - process $proc$libresoc.v:79628$3741 + attribute \src "libresoc.v:80027.3-80036.6" + process $proc$libresoc.v:80027$3760 assign { } { } assign { } { } - assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] - attribute \src "libresoc.v:79629.5-79629.29" + assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:80028.5-80028.29" switch \initial - attribute \src "libresoc.v:79629.9-79629.17" + attribute \src "libresoc.v:80028.9-80028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_upd[1:0] 2'00 + assign $1\dec22_internal_op[6:0] 7'1001100 case - assign $1\dec22_upd[1:0] 2'00 + assign $1\dec22_internal_op[6:0] 7'0000000 end sync always - update \dec22_upd $0\dec22_upd[1:0] + update \dec22_internal_op $0\dec22_internal_op[6:0] end - attribute \src "libresoc.v:79638.3-79647.6" - process $proc$libresoc.v:79638$3742 + attribute \src "libresoc.v:80037.3-80046.6" + process $proc$libresoc.v:80037$3761 assign { } { } assign { } { } - assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79639.5-79639.29" + assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] + attribute \src "libresoc.v:80038.5-80038.29" switch \initial - attribute \src "libresoc.v:79639.9-79639.17" + attribute \src "libresoc.v:80038.9-80038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_internal_op[6:0] 7'1001100 + assign $1\dec22_upd[1:0] 2'00 case - assign $1\dec22_internal_op[6:0] 7'0000000 + assign $1\dec22_upd[1:0] 2'00 end sync always - update \dec22_internal_op $0\dec22_internal_op[6:0] + update \dec22_upd $0\dec22_upd[1:0] end - attribute \src "libresoc.v:79648.3-79657.6" - process $proc$libresoc.v:79648$3743 + attribute \src "libresoc.v:80047.3-80056.6" + process $proc$libresoc.v:80047$3762 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79649.5-79649.29" + attribute \src "libresoc.v:80048.5-80048.29" switch \initial - attribute \src "libresoc.v:79649.9-79649.17" + attribute \src "libresoc.v:80048.9-80048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128193,18 +128857,18 @@ module \dec22 sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end - attribute \src "libresoc.v:79658.3-79667.6" - process $proc$libresoc.v:79658$3744 + attribute \src "libresoc.v:80057.3-80066.6" + process $proc$libresoc.v:80057$3763 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79659.5-79659.29" + attribute \src "libresoc.v:80058.5-80058.29" switch \initial - attribute \src "libresoc.v:79659.9-79659.17" + attribute \src "libresoc.v:80058.9-80058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128216,18 +128880,18 @@ module \dec22 sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end - attribute \src "libresoc.v:79668.3-79677.6" - process $proc$libresoc.v:79668$3745 + attribute \src "libresoc.v:80067.3-80076.6" + process $proc$libresoc.v:80067$3764 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79669.5-79669.29" + attribute \src "libresoc.v:80068.5-80068.29" switch \initial - attribute \src "libresoc.v:79669.9-79669.17" + attribute \src "libresoc.v:80068.9-80068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128239,18 +128903,18 @@ module \dec22 sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end - attribute \src "libresoc.v:79678.3-79687.6" - process $proc$libresoc.v:79678$3746 + attribute \src "libresoc.v:80077.3-80086.6" + process $proc$libresoc.v:80077$3765 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79679.5-79679.29" + attribute \src "libresoc.v:80078.5-80078.29" switch \initial - attribute \src "libresoc.v:79679.9-79679.17" + attribute \src "libresoc.v:80078.9-80078.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128262,18 +128926,18 @@ module \dec22 sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end - attribute \src "libresoc.v:79688.3-79697.6" - process $proc$libresoc.v:79688$3747 + attribute \src "libresoc.v:80087.3-80096.6" + process $proc$libresoc.v:80087$3766 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:79689.5-79689.29" + attribute \src "libresoc.v:80088.5-80088.29" switch \initial - attribute \src "libresoc.v:79689.9-79689.17" + attribute \src "libresoc.v:80088.9-80088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128285,18 +128949,18 @@ module \dec22 sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end - attribute \src "libresoc.v:79698.3-79707.6" - process $proc$libresoc.v:79698$3748 + attribute \src "libresoc.v:80097.3-80106.6" + process $proc$libresoc.v:80097$3767 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:79699.5-79699.29" + attribute \src "libresoc.v:80098.5-80098.29" switch \initial - attribute \src "libresoc.v:79699.9-79699.17" + attribute \src "libresoc.v:80098.9-80098.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128308,18 +128972,18 @@ module \dec22 sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end - attribute \src "libresoc.v:79708.3-79717.6" - process $proc$libresoc.v:79708$3749 + attribute \src "libresoc.v:80107.3-80116.6" + process $proc$libresoc.v:80107$3768 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] - attribute \src "libresoc.v:79709.5-79709.29" + attribute \src "libresoc.v:80108.5-80108.29" switch \initial - attribute \src "libresoc.v:79709.9-79709.17" + attribute \src "libresoc.v:80108.9-80108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128331,18 +128995,18 @@ module \dec22 sync always update \dec22_br $0\dec22_br[0:0] end - attribute \src "libresoc.v:79718.3-79727.6" - process $proc$libresoc.v:79718$3750 + attribute \src "libresoc.v:80117.3-80126.6" + process $proc$libresoc.v:80117$3769 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79719.5-79719.29" + attribute \src "libresoc.v:80118.5-80118.29" switch \initial - attribute \src "libresoc.v:79719.9-79719.17" + attribute \src "libresoc.v:80118.9-80118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128354,18 +129018,18 @@ module \dec22 sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end - attribute \src "libresoc.v:79728.3-79737.6" - process $proc$libresoc.v:79728$3751 + attribute \src "libresoc.v:80127.3-80136.6" + process $proc$libresoc.v:80127$3770 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:79729.5-79729.29" + attribute \src "libresoc.v:80128.5-80128.29" switch \initial - attribute \src "libresoc.v:79729.9-79729.17" + attribute \src "libresoc.v:80128.9-80128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128377,64 +129041,64 @@ module \dec22 sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end - attribute \src "libresoc.v:79738.3-79747.6" - process $proc$libresoc.v:79738$3752 + attribute \src "libresoc.v:80137.3-80146.6" + process $proc$libresoc.v:80137$3771 assign { } { } assign { } { } - assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:79739.5-79739.29" + assign $0\dec22_form[4:0] $1\dec22_form[4:0] + attribute \src "libresoc.v:80138.5-80138.29" switch \initial - attribute \src "libresoc.v:79739.9-79739.17" + attribute \src "libresoc.v:80138.9-80138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_is_32b[0:0] 1'0 + assign $1\dec22_form[4:0] 5'11101 case - assign $1\dec22_is_32b[0:0] 1'0 + assign $1\dec22_form[4:0] 5'00000 end sync always - update \dec22_is_32b $0\dec22_is_32b[0:0] + update \dec22_form $0\dec22_form[4:0] end - attribute \src "libresoc.v:79748.3-79757.6" - process $proc$libresoc.v:79748$3753 + attribute \src "libresoc.v:80147.3-80156.6" + process $proc$libresoc.v:80147$3772 assign { } { } assign { } { } - assign $0\dec22_form[4:0] $1\dec22_form[4:0] - attribute \src "libresoc.v:79749.5-79749.29" + assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:80148.5-80148.29" switch \initial - attribute \src "libresoc.v:79749.9-79749.17" + attribute \src "libresoc.v:80148.9-80148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_form[4:0] 5'11101 + assign $1\dec22_is_32b[0:0] 1'0 case - assign $1\dec22_form[4:0] 5'00000 + assign $1\dec22_is_32b[0:0] 1'0 end sync always - update \dec22_form $0\dec22_form[4:0] + update \dec22_is_32b $0\dec22_is_32b[0:0] end - attribute \src "libresoc.v:79758.3-79767.6" - process $proc$libresoc.v:79758$3754 + attribute \src "libresoc.v:80157.3-80166.6" + process $proc$libresoc.v:80157$3773 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] - attribute \src "libresoc.v:79759.5-79759.29" + attribute \src "libresoc.v:80158.5-80158.29" switch \initial - attribute \src "libresoc.v:79759.9-79759.17" + attribute \src "libresoc.v:80158.9-80158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128446,18 +129110,18 @@ module \dec22 sync always update \dec22_sgn $0\dec22_sgn[0:0] end - attribute \src "libresoc.v:79768.3-79777.6" - process $proc$libresoc.v:79768$3755 + attribute \src "libresoc.v:80167.3-80176.6" + process $proc$libresoc.v:80167$3774 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] - attribute \src "libresoc.v:79769.5-79769.29" + attribute \src "libresoc.v:80168.5-80168.29" switch \initial - attribute \src "libresoc.v:79769.9-79769.17" + attribute \src "libresoc.v:80168.9-80168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128469,18 +129133,18 @@ module \dec22 sync always update \dec22_lk $0\dec22_lk[0:0] end - attribute \src "libresoc.v:79778.3-79787.6" - process $proc$libresoc.v:79778$3756 + attribute \src "libresoc.v:80177.3-80186.6" + process $proc$libresoc.v:80177$3775 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79779.5-79779.29" + attribute \src "libresoc.v:80178.5-80178.29" switch \initial - attribute \src "libresoc.v:79779.9-79779.17" + attribute \src "libresoc.v:80178.9-80178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128492,18 +129156,18 @@ module \dec22 sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end - attribute \src "libresoc.v:79788.3-79797.6" - process $proc$libresoc.v:79788$3757 + attribute \src "libresoc.v:80187.3-80196.6" + process $proc$libresoc.v:80187$3776 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79789.5-79789.29" + attribute \src "libresoc.v:80188.5-80188.29" switch \initial - attribute \src "libresoc.v:79789.9-79789.17" + attribute \src "libresoc.v:80188.9-80188.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128515,18 +129179,18 @@ module \dec22 sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end - attribute \src "libresoc.v:79798.3-79807.6" - process $proc$libresoc.v:79798$3758 + attribute \src "libresoc.v:80197.3-80206.6" + process $proc$libresoc.v:80197$3777 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79799.5-79799.29" + attribute \src "libresoc.v:80198.5-80198.29" switch \initial - attribute \src "libresoc.v:79799.9-79799.17" + attribute \src "libresoc.v:80198.9-80198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128538,18 +129202,18 @@ module \dec22 sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end - attribute \src "libresoc.v:79808.3-79817.6" - process $proc$libresoc.v:79808$3759 + attribute \src "libresoc.v:80207.3-80216.6" + process $proc$libresoc.v:80207$3778 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79809.5-79809.29" + attribute \src "libresoc.v:80208.5-80208.29" switch \initial - attribute \src "libresoc.v:79809.9-79809.17" + attribute \src "libresoc.v:80208.9-80208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128561,18 +129225,18 @@ module \dec22 sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end - attribute \src "libresoc.v:79818.3-79827.6" - process $proc$libresoc.v:79818$3760 + attribute \src "libresoc.v:80217.3-80226.6" + process $proc$libresoc.v:80217$3779 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79819.5-79819.29" + attribute \src "libresoc.v:80218.5-80218.29" switch \initial - attribute \src "libresoc.v:79819.9-79819.17" + attribute \src "libresoc.v:80218.9-80218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128584,18 +129248,18 @@ module \dec22 sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end - attribute \src "libresoc.v:79828.3-79837.6" - process $proc$libresoc.v:79828$3761 + attribute \src "libresoc.v:80227.3-80236.6" + process $proc$libresoc.v:80227$3780 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79829.5-79829.29" + attribute \src "libresoc.v:80228.5-80228.29" switch \initial - attribute \src "libresoc.v:79829.9-79829.17" + attribute \src "libresoc.v:80228.9-80228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128607,18 +129271,18 @@ module \dec22 sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end - attribute \src "libresoc.v:79838.3-79847.6" - process $proc$libresoc.v:79838$3762 + attribute \src "libresoc.v:80237.3-80246.6" + process $proc$libresoc.v:80237$3781 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:79839.5-79839.29" + attribute \src "libresoc.v:80238.5-80238.29" switch \initial - attribute \src "libresoc.v:79839.9-79839.17" + attribute \src "libresoc.v:80238.9-80238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128632,157 +129296,161 @@ module \dec22 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:79853.1-81377.10" +attribute \src "libresoc.v:80252.1-81823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:81154.3-81190.6" + attribute \src "libresoc.v:81600.3-81636.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81191.3-81227.6" + attribute \src "libresoc.v:81637.3-81673.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80710.3-80746.6" + attribute \src "libresoc.v:81156.3-81192.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:80858.3-80894.6" + attribute \src "libresoc.v:81304.3-81340.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:80229.3-80265.6" + attribute \src "libresoc.v:80638.3-80674.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:80266.3-80302.6" + attribute \src "libresoc.v:80675.3-80711.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:80673.3-80709.6" + attribute \src "libresoc.v:81119.3-81155.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:80821.3-80857.6" + attribute \src "libresoc.v:81267.3-81303.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:81006.3-81042.6" + attribute \src "libresoc.v:81415.3-81451.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:80192.3-80228.6" + attribute \src "libresoc.v:80601.3-80637.6" wire width 14 $0\dec30_function_unit[13:0] - attribute \src "libresoc.v:81228.3-81264.6" + attribute \src "libresoc.v:81674.3-81710.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81265.3-81301.6" + attribute \src "libresoc.v:81711.3-81747.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81302.3-81338.6" + attribute \src "libresoc.v:81748.3-81784.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80599.3-80635.6" + attribute \src "libresoc.v:81008.3-81044.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:80747.3-80783.6" + attribute \src "libresoc.v:81193.3-81229.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:80784.3-80820.6" + attribute \src "libresoc.v:81230.3-81266.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:80969.3-81005.6" + attribute \src "libresoc.v:81452.3-81488.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:80525.3-80561.6" + attribute \src "libresoc.v:80971.3-81007.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81080.3-81116.6" + attribute \src "libresoc.v:81526.3-81562.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:81339.3-81375.6" + attribute \src "libresoc.v:81785.3-81821.6" wire width 3 $0\dec30_out_sel[2:0] - attribute \src "libresoc.v:80636.3-80672.6" + attribute \src "libresoc.v:81082.3-81118.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80932.3-80968.6" + attribute \src "libresoc.v:81378.3-81414.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:81117.3-81153.6" + attribute \src "libresoc.v:81563.3-81599.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81043.3-81079.6" + attribute \src "libresoc.v:81489.3-81525.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:80895.3-80931.6" + attribute \src "libresoc.v:81341.3-81377.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80451.3-80487.6" + attribute \src "libresoc.v:80897.3-80933.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80488.3-80524.6" + attribute \src "libresoc.v:80934.3-80970.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80303.3-80339.6" + attribute \src "libresoc.v:80712.3-80748.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80340.3-80376.6" + attribute \src "libresoc.v:80749.3-80785.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80377.3-80413.6" + attribute \src "libresoc.v:80786.3-80822.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80414.3-80450.6" + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $0\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:80562.3-80598.6" + attribute \src "libresoc.v:81045.3-81081.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:79854.7-79854.20" + attribute \src "libresoc.v:80253.7-80253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81154.3-81190.6" + attribute \src "libresoc.v:81600.3-81636.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81191.3-81227.6" + attribute \src "libresoc.v:81637.3-81673.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80710.3-80746.6" + attribute \src "libresoc.v:81156.3-81192.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80858.3-80894.6" + attribute \src "libresoc.v:81304.3-81340.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:80229.3-80265.6" + attribute \src "libresoc.v:80638.3-80674.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80266.3-80302.6" + attribute \src "libresoc.v:80675.3-80711.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80673.3-80709.6" + attribute \src "libresoc.v:81119.3-81155.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80821.3-80857.6" + attribute \src "libresoc.v:81267.3-81303.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81006.3-81042.6" + attribute \src "libresoc.v:81415.3-81451.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:80192.3-80228.6" + attribute \src "libresoc.v:80601.3-80637.6" wire width 14 $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:81228.3-81264.6" + attribute \src "libresoc.v:81674.3-81710.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81265.3-81301.6" + attribute \src "libresoc.v:81711.3-81747.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81302.3-81338.6" + attribute \src "libresoc.v:81748.3-81784.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80599.3-80635.6" + attribute \src "libresoc.v:81008.3-81044.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80747.3-80783.6" + attribute \src "libresoc.v:81193.3-81229.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80784.3-80820.6" + attribute \src "libresoc.v:81230.3-81266.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80969.3-81005.6" + attribute \src "libresoc.v:81452.3-81488.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80525.3-80561.6" + attribute \src "libresoc.v:80971.3-81007.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81080.3-81116.6" + attribute \src "libresoc.v:81526.3-81562.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:81339.3-81375.6" + attribute \src "libresoc.v:81785.3-81821.6" wire width 3 $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:80636.3-80672.6" + attribute \src "libresoc.v:81082.3-81118.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80932.3-80968.6" + attribute \src "libresoc.v:81378.3-81414.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81117.3-81153.6" + attribute \src "libresoc.v:81563.3-81599.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81043.3-81079.6" + attribute \src "libresoc.v:81489.3-81525.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:80895.3-80931.6" + attribute \src "libresoc.v:81341.3-81377.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80451.3-80487.6" + attribute \src "libresoc.v:80897.3-80933.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80488.3-80524.6" + attribute \src "libresoc.v:80934.3-80970.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80303.3-80339.6" + attribute \src "libresoc.v:80712.3-80748.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80340.3-80376.6" + attribute \src "libresoc.v:80749.3-80785.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80377.3-80413.6" + attribute \src "libresoc.v:80786.3-80822.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80414.3-80450.6" + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80562.3-80598.6" + attribute \src "libresoc.v:81045.3-81081.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec30_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec30_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128792,7 +129460,7 @@ module \dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -128801,16 +129469,16 @@ module \dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -128842,7 +129510,7 @@ module \dec30 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -128859,7 +129527,7 @@ module \dec30 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -128867,7 +129535,7 @@ module \dec30 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -128884,13 +129552,13 @@ module \dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -128967,46 +129635,46 @@ module \dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec30_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec30_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129014,8 +129682,8 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec30_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec30_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129023,8 +129691,8 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec30_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec30_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129032,7 +129700,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec30_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129041,7 +129709,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec30_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129050,7 +129718,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec30_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129059,41 +129727,50 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec30_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec30_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec30_upd - attribute \src "libresoc.v:79854.7-79854.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec30_upd + attribute \src "libresoc.v:80253.7-80253.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79854.7-79854.20" - process $proc$libresoc.v:79854$3796 + attribute \src "libresoc.v:80253.7-80253.20" + process $proc$libresoc.v:80253$3816 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80192.3-80228.6" - process $proc$libresoc.v:80192$3764 + attribute \src "libresoc.v:80601.3-80637.6" + process $proc$libresoc.v:80601$3783 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:80193.5-80193.29" + attribute \src "libresoc.v:80602.5-80602.29" switch \initial - attribute \src "libresoc.v:80193.9-80193.17" + attribute \src "libresoc.v:80602.9-80602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129141,18 +129818,18 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:80229.3-80265.6" - process $proc$libresoc.v:80229$3765 + attribute \src "libresoc.v:80638.3-80674.6" + process $proc$libresoc.v:80638$3784 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80230.5-80230.29" + attribute \src "libresoc.v:80639.5-80639.29" switch \initial - attribute \src "libresoc.v:80230.9-80230.17" + attribute \src "libresoc.v:80639.9-80639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129200,18 +129877,18 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:80266.3-80302.6" - process $proc$libresoc.v:80266$3766 + attribute \src "libresoc.v:80675.3-80711.6" + process $proc$libresoc.v:80675$3785 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80267.5-80267.29" + attribute \src "libresoc.v:80676.5-80676.29" switch \initial - attribute \src "libresoc.v:80267.9-80267.17" + attribute \src "libresoc.v:80676.9-80676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129259,18 +129936,18 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:80303.3-80339.6" - process $proc$libresoc.v:80303$3767 + attribute \src "libresoc.v:80712.3-80748.6" + process $proc$libresoc.v:80712$3786 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80304.5-80304.29" + attribute \src "libresoc.v:80713.5-80713.29" switch \initial - attribute \src "libresoc.v:80304.9-80304.17" + attribute \src "libresoc.v:80713.9-80713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129318,18 +129995,18 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:80340.3-80376.6" - process $proc$libresoc.v:80340$3768 + attribute \src "libresoc.v:80749.3-80785.6" + process $proc$libresoc.v:80749$3787 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80341.5-80341.29" + attribute \src "libresoc.v:80750.5-80750.29" switch \initial - attribute \src "libresoc.v:80341.9-80341.17" + attribute \src "libresoc.v:80750.9-80750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129377,18 +130054,18 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:80377.3-80413.6" - process $proc$libresoc.v:80377$3769 + attribute \src "libresoc.v:80786.3-80822.6" + process $proc$libresoc.v:80786$3788 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80378.5-80378.29" + attribute \src "libresoc.v:80787.5-80787.29" switch \initial - attribute \src "libresoc.v:80378.9-80378.17" + attribute \src "libresoc.v:80787.9-80787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129436,18 +130113,18 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:80414.3-80450.6" - process $proc$libresoc.v:80414$3770 + attribute \src "libresoc.v:80823.3-80859.6" + process $proc$libresoc.v:80823$3789 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80415.5-80415.29" + attribute \src "libresoc.v:80824.5-80824.29" switch \initial - attribute \src "libresoc.v:80415.9-80415.17" + attribute \src "libresoc.v:80824.9-80824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129495,18 +130172,77 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:80451.3-80487.6" - process $proc$libresoc.v:80451$3771 + attribute \src "libresoc.v:80860.3-80896.6" + process $proc$libresoc.v:80860$3790 + assign { } { } + assign { } { } + assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80861.5-80861.29" + switch \initial + attribute \src "libresoc.v:80861.9-80861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + case + assign $1\dec30_sv_out2[2:0] 3'000 + end + sync always + update \dec30_sv_out2 $0\dec30_sv_out2[2:0] + end + attribute \src "libresoc.v:80897.3-80933.6" + process $proc$libresoc.v:80897$3791 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80452.5-80452.29" + attribute \src "libresoc.v:80898.5-80898.29" switch \initial - attribute \src "libresoc.v:80452.9-80452.17" + attribute \src "libresoc.v:80898.9-80898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129554,18 +130290,18 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:80488.3-80524.6" - process $proc$libresoc.v:80488$3772 + attribute \src "libresoc.v:80934.3-80970.6" + process $proc$libresoc.v:80934$3792 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80489.5-80489.29" + attribute \src "libresoc.v:80935.5-80935.29" switch \initial - attribute \src "libresoc.v:80489.9-80489.17" + attribute \src "libresoc.v:80935.9-80935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129613,18 +130349,18 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:80525.3-80561.6" - process $proc$libresoc.v:80525$3773 + attribute \src "libresoc.v:80971.3-81007.6" + process $proc$libresoc.v:80971$3793 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80526.5-80526.29" + attribute \src "libresoc.v:80972.5-80972.29" switch \initial - attribute \src "libresoc.v:80526.9-80526.17" + attribute \src "libresoc.v:80972.9-80972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129672,136 +130408,136 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:80562.3-80598.6" - process $proc$libresoc.v:80562$3774 + attribute \src "libresoc.v:81008.3-81044.6" + process $proc$libresoc.v:81008$3794 assign { } { } assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:80563.5-80563.29" + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:81009.5-81009.29" switch \initial - attribute \src "libresoc.v:80563.9-80563.17" + attribute \src "libresoc.v:81009.9-81009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 case - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0000000 end sync always - update \dec30_upd $0\dec30_upd[1:0] + update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:80599.3-80635.6" - process $proc$libresoc.v:80599$3775 + attribute \src "libresoc.v:81045.3-81081.6" + process $proc$libresoc.v:81045$3795 assign { } { } assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80600.5-80600.29" + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:81046.5-81046.29" switch \initial - attribute \src "libresoc.v:80600.9-80600.17" + attribute \src "libresoc.v:81046.9-81046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 case - assign $1\dec30_internal_op[6:0] 7'0000000 + assign $1\dec30_upd[1:0] 2'00 end sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] + update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:80636.3-80672.6" - process $proc$libresoc.v:80636$3776 + attribute \src "libresoc.v:81082.3-81118.6" + process $proc$libresoc.v:81082$3796 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80637.5-80637.29" + attribute \src "libresoc.v:81083.5-81083.29" switch \initial - attribute \src "libresoc.v:80637.9-80637.17" + attribute \src "libresoc.v:81083.9-81083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129849,18 +130585,18 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:80673.3-80709.6" - process $proc$libresoc.v:80673$3777 + attribute \src "libresoc.v:81119.3-81155.6" + process $proc$libresoc.v:81119$3797 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80674.5-80674.29" + attribute \src "libresoc.v:81120.5-81120.29" switch \initial - attribute \src "libresoc.v:80674.9-80674.17" + attribute \src "libresoc.v:81120.9-81120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129908,18 +130644,18 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:80710.3-80746.6" - process $proc$libresoc.v:80710$3778 + attribute \src "libresoc.v:81156.3-81192.6" + process $proc$libresoc.v:81156$3798 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80711.5-80711.29" + attribute \src "libresoc.v:81157.5-81157.29" switch \initial - attribute \src "libresoc.v:80711.9-80711.17" + attribute \src "libresoc.v:81157.9-81157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129967,18 +130703,18 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:80747.3-80783.6" - process $proc$libresoc.v:80747$3779 + attribute \src "libresoc.v:81193.3-81229.6" + process $proc$libresoc.v:81193$3799 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80748.5-80748.29" + attribute \src "libresoc.v:81194.5-81194.29" switch \initial - attribute \src "libresoc.v:80748.9-80748.17" + attribute \src "libresoc.v:81194.9-81194.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130026,18 +130762,18 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:80784.3-80820.6" - process $proc$libresoc.v:80784$3780 + attribute \src "libresoc.v:81230.3-81266.6" + process $proc$libresoc.v:81230$3800 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80785.5-80785.29" + attribute \src "libresoc.v:81231.5-81231.29" switch \initial - attribute \src "libresoc.v:80785.9-80785.17" + attribute \src "libresoc.v:81231.9-81231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130085,18 +130821,18 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:80821.3-80857.6" - process $proc$libresoc.v:80821$3781 + attribute \src "libresoc.v:81267.3-81303.6" + process $proc$libresoc.v:81267$3801 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:80822.5-80822.29" + attribute \src "libresoc.v:81268.5-81268.29" switch \initial - attribute \src "libresoc.v:80822.9-80822.17" + attribute \src "libresoc.v:81268.9-81268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130144,18 +130880,18 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:80858.3-80894.6" - process $proc$libresoc.v:80858$3782 + attribute \src "libresoc.v:81304.3-81340.6" + process $proc$libresoc.v:81304$3802 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:80859.5-80859.29" + attribute \src "libresoc.v:81305.5-81305.29" switch \initial - attribute \src "libresoc.v:80859.9-80859.17" + attribute \src "libresoc.v:81305.9-81305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130203,18 +130939,18 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:80895.3-80931.6" - process $proc$libresoc.v:80895$3783 + attribute \src "libresoc.v:81341.3-81377.6" + process $proc$libresoc.v:81341$3803 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80896.5-80896.29" + attribute \src "libresoc.v:81342.5-81342.29" switch \initial - attribute \src "libresoc.v:80896.9-80896.17" + attribute \src "libresoc.v:81342.9-81342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130262,18 +130998,18 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:80932.3-80968.6" - process $proc$libresoc.v:80932$3784 + attribute \src "libresoc.v:81378.3-81414.6" + process $proc$libresoc.v:81378$3804 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:80933.5-80933.29" + attribute \src "libresoc.v:81379.5-81379.29" switch \initial - attribute \src "libresoc.v:80933.9-80933.17" + attribute \src "libresoc.v:81379.9-81379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130321,136 +131057,136 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:80969.3-81005.6" - process $proc$libresoc.v:80969$3785 + attribute \src "libresoc.v:81415.3-81451.6" + process $proc$libresoc.v:81415$3805 assign { } { } assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80970.5-80970.29" + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:81416.5-81416.29" switch \initial - attribute \src "libresoc.v:80970.9-80970.17" + attribute \src "libresoc.v:81416.9-81416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 case - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'00000 end sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] + update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:81006.3-81042.6" - process $proc$libresoc.v:81006$3786 + attribute \src "libresoc.v:81452.3-81488.6" + process $proc$libresoc.v:81452$3806 assign { } { } assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:81007.5-81007.29" + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:81453.5-81453.29" switch \initial - attribute \src "libresoc.v:81007.9-81007.17" + attribute \src "libresoc.v:81453.9-81453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 case - assign $1\dec30_form[4:0] 5'00000 + assign $1\dec30_is_32b[0:0] 1'0 end sync always - update \dec30_form $0\dec30_form[4:0] + update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:81043.3-81079.6" - process $proc$libresoc.v:81043$3787 + attribute \src "libresoc.v:81489.3-81525.6" + process $proc$libresoc.v:81489$3807 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81044.5-81044.29" + attribute \src "libresoc.v:81490.5-81490.29" switch \initial - attribute \src "libresoc.v:81044.9-81044.17" + attribute \src "libresoc.v:81490.9-81490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130498,18 +131234,18 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:81080.3-81116.6" - process $proc$libresoc.v:81080$3788 + attribute \src "libresoc.v:81526.3-81562.6" + process $proc$libresoc.v:81526$3808 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:81081.5-81081.29" + attribute \src "libresoc.v:81527.5-81527.29" switch \initial - attribute \src "libresoc.v:81081.9-81081.17" + attribute \src "libresoc.v:81527.9-81527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130557,18 +131293,18 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:81117.3-81153.6" - process $proc$libresoc.v:81117$3789 + attribute \src "libresoc.v:81563.3-81599.6" + process $proc$libresoc.v:81563$3809 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81118.5-81118.29" + attribute \src "libresoc.v:81564.5-81564.29" switch \initial - attribute \src "libresoc.v:81118.9-81118.17" + attribute \src "libresoc.v:81564.9-81564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130616,18 +131352,18 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:81154.3-81190.6" - process $proc$libresoc.v:81154$3790 + attribute \src "libresoc.v:81600.3-81636.6" + process $proc$libresoc.v:81600$3810 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81155.5-81155.29" + attribute \src "libresoc.v:81601.5-81601.29" switch \initial - attribute \src "libresoc.v:81155.9-81155.17" + attribute \src "libresoc.v:81601.9-81601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130675,18 +131411,18 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:81191.3-81227.6" - process $proc$libresoc.v:81191$3791 + attribute \src "libresoc.v:81637.3-81673.6" + process $proc$libresoc.v:81637$3811 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81192.5-81192.29" + attribute \src "libresoc.v:81638.5-81638.29" switch \initial - attribute \src "libresoc.v:81192.9-81192.17" + attribute \src "libresoc.v:81638.9-81638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130734,18 +131470,18 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:81228.3-81264.6" - process $proc$libresoc.v:81228$3792 + attribute \src "libresoc.v:81674.3-81710.6" + process $proc$libresoc.v:81674$3812 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81229.5-81229.29" + attribute \src "libresoc.v:81675.5-81675.29" switch \initial - attribute \src "libresoc.v:81229.9-81229.17" + attribute \src "libresoc.v:81675.9-81675.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130793,18 +131529,18 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:81265.3-81301.6" - process $proc$libresoc.v:81265$3793 + attribute \src "libresoc.v:81711.3-81747.6" + process $proc$libresoc.v:81711$3813 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81266.5-81266.29" + attribute \src "libresoc.v:81712.5-81712.29" switch \initial - attribute \src "libresoc.v:81266.9-81266.17" + attribute \src "libresoc.v:81712.9-81712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130852,18 +131588,18 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:81302.3-81338.6" - process $proc$libresoc.v:81302$3794 + attribute \src "libresoc.v:81748.3-81784.6" + process $proc$libresoc.v:81748$3814 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81303.5-81303.29" + attribute \src "libresoc.v:81749.5-81749.29" switch \initial - attribute \src "libresoc.v:81303.9-81303.17" + attribute \src "libresoc.v:81749.9-81749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130911,18 +131647,18 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:81339.3-81375.6" - process $proc$libresoc.v:81339$3795 + attribute \src "libresoc.v:81785.3-81821.6" + process $proc$libresoc.v:81785$3815 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81340.5-81340.29" + attribute \src "libresoc.v:81786.5-81786.29" switch \initial - attribute \src "libresoc.v:81340.9-81340.17" + attribute \src "libresoc.v:81786.9-81786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130972,157 +131708,161 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:81381.1-89778.10" +attribute \src "libresoc.v:81827.1-90475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:88050.3-88110.6" + attribute \src "libresoc.v:88686.3-88746.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88111.3-88171.6" + attribute \src "libresoc.v:88747.3-88807.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87989.3-88049.6" + attribute \src "libresoc.v:88625.3-88685.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:89331.3-89391.6" + attribute \src "libresoc.v:90028.3-90088.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:88416.3-88476.6" + attribute \src "libresoc.v:89052.3-89112.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:88477.3-88537.6" + attribute \src "libresoc.v:89113.3-89173.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:89087.3-89147.6" + attribute \src "libresoc.v:89784.3-89844.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:89270.3-89330.6" + attribute \src "libresoc.v:89967.3-90027.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:87928.3-87988.6" + attribute \src "libresoc.v:88564.3-88624.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:87806.3-87866.6" + attribute \src "libresoc.v:88442.3-88502.6" wire width 14 $0\dec31_function_unit[13:0] - attribute \src "libresoc.v:88172.3-88232.6" + attribute \src "libresoc.v:88808.3-88868.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88233.3-88293.6" + attribute \src "libresoc.v:88869.3-88929.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88294.3-88354.6" + attribute \src "libresoc.v:88930.3-88990.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87867.3-87927.6" + attribute \src "libresoc.v:88503.3-88563.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:89148.3-89208.6" + attribute \src "libresoc.v:89845.3-89905.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:89209.3-89269.6" + attribute \src "libresoc.v:89906.3-89966.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:89514.3-89574.6" + attribute \src "libresoc.v:90211.3-90271.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:88904.3-88964.6" + attribute \src "libresoc.v:89601.3-89661.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89636.3-89696.6" + attribute \src "libresoc.v:90333.3-90393.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:88355.3-88415.6" + attribute \src "libresoc.v:88991.3-89051.6" wire width 3 $0\dec31_out_sel[2:0] - attribute \src "libresoc.v:89026.3-89086.6" + attribute \src "libresoc.v:89723.3-89783.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89453.3-89513.6" + attribute \src "libresoc.v:90150.3-90210.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:89697.3-89757.6" + attribute \src "libresoc.v:90394.3-90454.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89575.3-89635.6" + attribute \src "libresoc.v:90272.3-90332.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:89392.3-89452.6" + attribute \src "libresoc.v:90089.3-90149.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88782.3-88842.6" + attribute \src "libresoc.v:89479.3-89539.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88843.3-88903.6" + attribute \src "libresoc.v:89540.3-89600.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88538.3-88598.6" + attribute \src "libresoc.v:89174.3-89234.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88599.3-88659.6" + attribute \src "libresoc.v:89235.3-89295.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88660.3-88720.6" + attribute \src "libresoc.v:89296.3-89356.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88721.3-88781.6" + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $0\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:88965.3-89025.6" + attribute \src "libresoc.v:89662.3-89722.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:81382.7-81382.20" + attribute \src "libresoc.v:81828.7-81828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88050.3-88110.6" + attribute \src "libresoc.v:88686.3-88746.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88111.3-88171.6" + attribute \src "libresoc.v:88747.3-88807.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87989.3-88049.6" + attribute \src "libresoc.v:88625.3-88685.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:89331.3-89391.6" + attribute \src "libresoc.v:90028.3-90088.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:88416.3-88476.6" + attribute \src "libresoc.v:89052.3-89112.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:88477.3-88537.6" + attribute \src "libresoc.v:89113.3-89173.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89087.3-89147.6" + attribute \src "libresoc.v:89784.3-89844.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89270.3-89330.6" + attribute \src "libresoc.v:89967.3-90027.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:87928.3-87988.6" + attribute \src "libresoc.v:88564.3-88624.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:87806.3-87866.6" + attribute \src "libresoc.v:88442.3-88502.6" wire width 14 $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88172.3-88232.6" + attribute \src "libresoc.v:88808.3-88868.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88233.3-88293.6" + attribute \src "libresoc.v:88869.3-88929.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88294.3-88354.6" + attribute \src "libresoc.v:88930.3-88990.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87867.3-87927.6" + attribute \src "libresoc.v:88503.3-88563.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:89148.3-89208.6" + attribute \src "libresoc.v:89845.3-89905.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89209.3-89269.6" + attribute \src "libresoc.v:89906.3-89966.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89514.3-89574.6" + attribute \src "libresoc.v:90211.3-90271.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:88904.3-88964.6" + attribute \src "libresoc.v:89601.3-89661.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89636.3-89696.6" + attribute \src "libresoc.v:90333.3-90393.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:88355.3-88415.6" + attribute \src "libresoc.v:88991.3-89051.6" wire width 3 $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:89026.3-89086.6" + attribute \src "libresoc.v:89723.3-89783.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89453.3-89513.6" + attribute \src "libresoc.v:90150.3-90210.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:89697.3-89757.6" + attribute \src "libresoc.v:90394.3-90454.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89575.3-89635.6" + attribute \src "libresoc.v:90272.3-90332.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:89392.3-89452.6" + attribute \src "libresoc.v:90089.3-90149.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88782.3-88842.6" + attribute \src "libresoc.v:89479.3-89539.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88843.3-88903.6" + attribute \src "libresoc.v:89540.3-89600.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88538.3-88598.6" + attribute \src "libresoc.v:89174.3-89234.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88599.3-88659.6" + attribute \src "libresoc.v:89235.3-89295.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88660.3-88720.6" + attribute \src "libresoc.v:89296.3-89356.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88721.3-88781.6" + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88965.3-89025.6" + attribute \src "libresoc.v:89662.3-89722.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -131132,7 +131872,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131141,31 +131881,31 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131176,7 +131916,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131185,15 +131925,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131226,7 +131966,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131243,7 +131983,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131251,7 +131991,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131268,13 +132008,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131351,13 +132091,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131365,9 +132105,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131375,21 +132115,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131398,7 +132138,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131407,7 +132147,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131416,7 +132156,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131425,7 +132165,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131434,7 +132174,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131443,32 +132183,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub0_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131479,7 +132228,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131488,15 +132237,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131529,7 +132278,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131546,7 +132295,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131554,7 +132303,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131571,13 +132320,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131654,13 +132403,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131668,9 +132417,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131678,21 +132427,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131701,7 +132450,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131710,7 +132459,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131719,7 +132468,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131728,7 +132477,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131737,7 +132486,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131746,32 +132495,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub10_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131782,7 +132540,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131791,15 +132549,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131832,7 +132590,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131849,7 +132607,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131857,7 +132615,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131874,13 +132632,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131957,13 +132715,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131971,9 +132729,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131981,21 +132739,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132004,7 +132762,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132013,7 +132771,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132022,7 +132780,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132031,7 +132789,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132040,7 +132798,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132049,32 +132807,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub11_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132085,7 +132852,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132094,15 +132861,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132135,7 +132902,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132152,7 +132919,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132160,7 +132927,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132177,13 +132944,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132260,13 +133027,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132274,9 +133041,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132284,21 +133051,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132307,7 +133074,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132316,7 +133083,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132325,7 +133092,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132334,7 +133101,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132343,7 +133110,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132352,32 +133119,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub15_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132388,7 +133164,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132397,15 +133173,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132438,7 +133214,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132455,7 +133231,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132463,7 +133239,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132480,13 +133256,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132563,13 +133339,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132577,9 +133353,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132587,21 +133363,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132610,7 +133386,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132619,7 +133395,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132628,7 +133404,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132637,7 +133413,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132646,7 +133422,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132655,32 +133431,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub16_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132691,7 +133476,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132700,15 +133485,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132741,7 +133526,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132758,7 +133543,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132766,7 +133551,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132783,13 +133568,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132866,13 +133651,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132880,9 +133665,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132890,21 +133675,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132913,7 +133698,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132922,7 +133707,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132931,7 +133716,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132940,7 +133725,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132949,7 +133734,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132958,32 +133743,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub18_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132994,7 +133788,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133003,15 +133797,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133044,7 +133838,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133061,7 +133855,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133069,7 +133863,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133086,13 +133880,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133169,13 +133963,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133183,9 +133977,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133193,21 +133987,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133216,7 +134010,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133225,7 +134019,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133234,7 +134028,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133243,7 +134037,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133252,7 +134046,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133261,32 +134055,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub19_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133297,7 +134100,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133306,15 +134109,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133347,7 +134150,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133364,7 +134167,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133372,7 +134175,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133389,13 +134192,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133472,13 +134275,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133486,9 +134289,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133496,21 +134299,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133519,7 +134322,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133528,7 +134331,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133537,7 +134340,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133546,7 +134349,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133555,7 +134358,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133564,32 +134367,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub20_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133600,7 +134412,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133609,15 +134421,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133650,7 +134462,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133667,7 +134479,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133675,7 +134487,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133692,13 +134504,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133775,13 +134587,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133789,9 +134601,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133799,21 +134611,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133822,7 +134634,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133831,7 +134643,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133840,7 +134652,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133849,7 +134661,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133858,7 +134670,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133867,32 +134679,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub21_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133903,7 +134724,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133912,15 +134733,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133953,7 +134774,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133970,7 +134791,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133978,7 +134799,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133995,13 +134816,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134078,13 +134899,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134092,9 +134913,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134102,21 +134923,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134125,7 +134946,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134134,7 +134955,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134143,7 +134964,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134152,7 +134973,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134161,7 +134982,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134170,32 +134991,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub22_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134206,7 +135036,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134215,15 +135045,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134256,7 +135086,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134273,7 +135103,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134281,7 +135111,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134298,13 +135128,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134381,13 +135211,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134395,9 +135225,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134405,21 +135235,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134428,7 +135258,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134437,7 +135267,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134446,7 +135276,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134455,7 +135285,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134464,7 +135294,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134473,32 +135303,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub23_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134509,7 +135348,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134518,15 +135357,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134559,7 +135398,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134576,7 +135415,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134584,7 +135423,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134601,13 +135440,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134684,13 +135523,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134698,9 +135537,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134708,21 +135547,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134731,7 +135570,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134740,7 +135579,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134749,7 +135588,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134758,7 +135597,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134767,7 +135606,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134776,32 +135615,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub24_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134812,7 +135660,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134821,15 +135669,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134862,7 +135710,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134879,7 +135727,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134887,7 +135735,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134904,13 +135752,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134987,13 +135835,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135001,9 +135849,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135011,21 +135859,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135034,7 +135882,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135043,7 +135891,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135052,7 +135900,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135061,7 +135909,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135070,7 +135918,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135079,32 +135927,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub26_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135115,7 +135972,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135124,15 +135981,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135165,7 +136022,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135182,7 +136039,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135190,7 +136047,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135207,13 +136064,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135290,13 +136147,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135304,9 +136161,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135314,21 +136171,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135337,7 +136194,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135346,7 +136203,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135355,7 +136212,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135364,7 +136221,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135373,7 +136230,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135382,32 +136239,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub27_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135418,7 +136284,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135427,15 +136293,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135468,7 +136334,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135485,7 +136351,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135493,7 +136359,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135510,13 +136376,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135593,13 +136459,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135607,9 +136473,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135617,21 +136483,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135640,7 +136506,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135649,7 +136515,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135658,7 +136524,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135667,7 +136533,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135676,7 +136542,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135685,32 +136551,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub28_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135721,7 +136596,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135730,15 +136605,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135771,7 +136646,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135788,7 +136663,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub4_dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135796,7 +136671,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135813,13 +136688,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135896,13 +136771,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135910,9 +136785,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135920,21 +136795,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135943,7 +136818,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135952,7 +136827,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135961,7 +136836,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135970,7 +136845,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135979,7 +136854,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135988,32 +136863,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub4_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -136024,7 +136908,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -136033,15 +136917,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136074,7 +136958,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136091,7 +136975,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136099,7 +136983,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136116,13 +137000,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136199,13 +137083,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -136213,9 +137097,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -136223,21 +137107,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136246,7 +137130,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136255,7 +137139,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136264,7 +137148,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136273,7 +137157,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136282,7 +137166,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136291,32 +137175,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub8_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -136327,7 +137220,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -136336,15 +137229,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136377,7 +137270,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136394,7 +137287,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136402,7 +137295,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136419,13 +137312,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136502,13 +137395,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -136516,9 +137409,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -136526,21 +137419,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136549,7 +137442,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136558,7 +137451,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136567,7 +137460,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136576,7 +137469,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136585,7 +137478,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136594,16 +137487,25 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub9_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136636,7 +137538,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136653,7 +137555,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136661,7 +137563,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136678,13 +137580,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136761,46 +137663,46 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136808,8 +137710,8 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136817,8 +137719,8 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136826,7 +137728,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136835,7 +137737,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136844,7 +137746,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136853,25 +137755,34 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_upd - attribute \src "libresoc.v:81382.7-81382.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_upd + attribute \src "libresoc.v:81828.7-81828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:87176.18-87210.4" + attribute \src "libresoc.v:87794.18-87829.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -136904,11 +137815,12 @@ module \dec31 connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out + connect \dec31_dec_sub0_sv_out2 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87211.19-87245.4" + attribute \src "libresoc.v:87830.19-87865.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -136941,11 +137853,12 @@ module \dec31 connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out + connect \dec31_dec_sub10_sv_out2 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87246.19-87280.4" + attribute \src "libresoc.v:87866.19-87901.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -136978,11 +137891,12 @@ module \dec31 connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out + connect \dec31_dec_sub11_sv_out2 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87281.19-87315.4" + attribute \src "libresoc.v:87902.19-87937.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -137015,11 +137929,12 @@ module \dec31 connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out + connect \dec31_dec_sub15_sv_out2 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87316.19-87350.4" + attribute \src "libresoc.v:87938.19-87973.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -137052,11 +137967,12 @@ module \dec31 connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out + connect \dec31_dec_sub16_sv_out2 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87351.19-87385.4" + attribute \src "libresoc.v:87974.19-88009.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -137089,11 +138005,12 @@ module \dec31 connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out + connect \dec31_dec_sub18_sv_out2 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87386.19-87420.4" + attribute \src "libresoc.v:88010.19-88045.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -137126,11 +138043,12 @@ module \dec31 connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out + connect \dec31_dec_sub19_sv_out2 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87421.19-87455.4" + attribute \src "libresoc.v:88046.19-88081.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -137163,11 +138081,12 @@ module \dec31 connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out + connect \dec31_dec_sub20_sv_out2 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87456.19-87490.4" + attribute \src "libresoc.v:88082.19-88117.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -137200,11 +138119,12 @@ module \dec31 connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out + connect \dec31_dec_sub21_sv_out2 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87491.19-87525.4" + attribute \src "libresoc.v:88118.19-88153.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -137237,11 +138157,12 @@ module \dec31 connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out + connect \dec31_dec_sub22_sv_out2 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87526.19-87560.4" + attribute \src "libresoc.v:88154.19-88189.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -137274,11 +138195,12 @@ module \dec31 connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out + connect \dec31_dec_sub23_sv_out2 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87561.19-87595.4" + attribute \src "libresoc.v:88190.19-88225.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -137311,11 +138233,12 @@ module \dec31 connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out + connect \dec31_dec_sub24_sv_out2 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87596.19-87630.4" + attribute \src "libresoc.v:88226.19-88261.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -137348,11 +138271,12 @@ module \dec31 connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out + connect \dec31_dec_sub26_sv_out2 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87631.19-87665.4" + attribute \src "libresoc.v:88262.19-88297.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -137385,11 +138309,12 @@ module \dec31 connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out + connect \dec31_dec_sub27_sv_out2 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87666.19-87700.4" + attribute \src "libresoc.v:88298.19-88333.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -137422,11 +138347,12 @@ module \dec31 connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out + connect \dec31_dec_sub28_sv_out2 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87701.18-87735.4" + attribute \src "libresoc.v:88334.18-88369.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -137459,11 +138385,12 @@ module \dec31 connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out + connect \dec31_dec_sub4_sv_out2 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87736.18-87770.4" + attribute \src "libresoc.v:88370.18-88405.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -137496,11 +138423,12 @@ module \dec31 connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out + connect \dec31_dec_sub8_sv_out2 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87771.18-87805.4" + attribute \src "libresoc.v:88406.18-88441.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -137533,29 +138461,30 @@ module \dec31 connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out + connect \dec31_dec_sub9_sv_out2 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:81382.7-81382.20" - process $proc$libresoc.v:81382$3829 + attribute \src "libresoc.v:81828.7-81828.20" + process $proc$libresoc.v:81828$3850 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:87806.3-87866.6" - process $proc$libresoc.v:87806$3797 + attribute \src "libresoc.v:88442.3-88502.6" + process $proc$libresoc.v:88442$3817 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:87807.5-87807.29" + attribute \src "libresoc.v:88443.5-88443.29" switch \initial - attribute \src "libresoc.v:87807.9-87807.17" + attribute \src "libresoc.v:88443.9-88443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137635,18 +138564,18 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:87867.3-87927.6" - process $proc$libresoc.v:87867$3798 + attribute \src "libresoc.v:88503.3-88563.6" + process $proc$libresoc.v:88503$3818 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:87868.5-87868.29" + attribute \src "libresoc.v:88504.5-88504.29" switch \initial - attribute \src "libresoc.v:87868.9-87868.17" + attribute \src "libresoc.v:88504.9-88504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137726,18 +138655,18 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:87928.3-87988.6" - process $proc$libresoc.v:87928$3799 + attribute \src "libresoc.v:88564.3-88624.6" + process $proc$libresoc.v:88564$3819 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:87929.5-87929.29" + attribute \src "libresoc.v:88565.5-88565.29" switch \initial - attribute \src "libresoc.v:87929.9-87929.17" + attribute \src "libresoc.v:88565.9-88565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137817,18 +138746,18 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:87989.3-88049.6" - process $proc$libresoc.v:87989$3800 + attribute \src "libresoc.v:88625.3-88685.6" + process $proc$libresoc.v:88625$3820 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:87990.5-87990.29" + attribute \src "libresoc.v:88626.5-88626.29" switch \initial - attribute \src "libresoc.v:87990.9-87990.17" + attribute \src "libresoc.v:88626.9-88626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137908,18 +138837,18 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:88050.3-88110.6" - process $proc$libresoc.v:88050$3801 + attribute \src "libresoc.v:88686.3-88746.6" + process $proc$libresoc.v:88686$3821 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88051.5-88051.29" + attribute \src "libresoc.v:88687.5-88687.29" switch \initial - attribute \src "libresoc.v:88051.9-88051.17" + attribute \src "libresoc.v:88687.9-88687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137999,18 +138928,18 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:88111.3-88171.6" - process $proc$libresoc.v:88111$3802 + attribute \src "libresoc.v:88747.3-88807.6" + process $proc$libresoc.v:88747$3822 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88112.5-88112.29" + attribute \src "libresoc.v:88748.5-88748.29" switch \initial - attribute \src "libresoc.v:88112.9-88112.17" + attribute \src "libresoc.v:88748.9-88748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138090,18 +139019,18 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:88172.3-88232.6" - process $proc$libresoc.v:88172$3803 + attribute \src "libresoc.v:88808.3-88868.6" + process $proc$libresoc.v:88808$3823 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88173.5-88173.29" + attribute \src "libresoc.v:88809.5-88809.29" switch \initial - attribute \src "libresoc.v:88173.9-88173.17" + attribute \src "libresoc.v:88809.9-88809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138181,18 +139110,18 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:88233.3-88293.6" - process $proc$libresoc.v:88233$3804 + attribute \src "libresoc.v:88869.3-88929.6" + process $proc$libresoc.v:88869$3824 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88234.5-88234.29" + attribute \src "libresoc.v:88870.5-88870.29" switch \initial - attribute \src "libresoc.v:88234.9-88234.17" + attribute \src "libresoc.v:88870.9-88870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138272,18 +139201,18 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:88294.3-88354.6" - process $proc$libresoc.v:88294$3805 + attribute \src "libresoc.v:88930.3-88990.6" + process $proc$libresoc.v:88930$3825 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88295.5-88295.29" + attribute \src "libresoc.v:88931.5-88931.29" switch \initial - attribute \src "libresoc.v:88295.9-88295.17" + attribute \src "libresoc.v:88931.9-88931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138363,18 +139292,18 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:88355.3-88415.6" - process $proc$libresoc.v:88355$3806 + attribute \src "libresoc.v:88991.3-89051.6" + process $proc$libresoc.v:88991$3826 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:88356.5-88356.29" + attribute \src "libresoc.v:88992.5-88992.29" switch \initial - attribute \src "libresoc.v:88356.9-88356.17" + attribute \src "libresoc.v:88992.9-88992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138454,18 +139383,18 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:88416.3-88476.6" - process $proc$libresoc.v:88416$3807 + attribute \src "libresoc.v:89052.3-89112.6" + process $proc$libresoc.v:89052$3827 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:88417.5-88417.29" + attribute \src "libresoc.v:89053.5-89053.29" switch \initial - attribute \src "libresoc.v:88417.9-88417.17" + attribute \src "libresoc.v:89053.9-89053.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138545,18 +139474,18 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:88477.3-88537.6" - process $proc$libresoc.v:88477$3808 + attribute \src "libresoc.v:89113.3-89173.6" + process $proc$libresoc.v:89113$3828 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:88478.5-88478.29" + attribute \src "libresoc.v:89114.5-89114.29" switch \initial - attribute \src "libresoc.v:88478.9-88478.17" + attribute \src "libresoc.v:89114.9-89114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138636,18 +139565,18 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:88538.3-88598.6" - process $proc$libresoc.v:88538$3809 + attribute \src "libresoc.v:89174.3-89234.6" + process $proc$libresoc.v:89174$3829 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88539.5-88539.29" + attribute \src "libresoc.v:89175.5-89175.29" switch \initial - attribute \src "libresoc.v:88539.9-88539.17" + attribute \src "libresoc.v:89175.9-89175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138727,18 +139656,18 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:88599.3-88659.6" - process $proc$libresoc.v:88599$3810 + attribute \src "libresoc.v:89235.3-89295.6" + process $proc$libresoc.v:89235$3830 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88600.5-88600.29" + attribute \src "libresoc.v:89236.5-89236.29" switch \initial - attribute \src "libresoc.v:88600.9-88600.17" + attribute \src "libresoc.v:89236.9-89236.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138818,18 +139747,18 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:88660.3-88720.6" - process $proc$libresoc.v:88660$3811 + attribute \src "libresoc.v:89296.3-89356.6" + process $proc$libresoc.v:89296$3831 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88661.5-88661.29" + attribute \src "libresoc.v:89297.5-89297.29" switch \initial - attribute \src "libresoc.v:88661.9-88661.17" + attribute \src "libresoc.v:89297.9-89297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138909,18 +139838,18 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:88721.3-88781.6" - process $proc$libresoc.v:88721$3812 + attribute \src "libresoc.v:89357.3-89417.6" + process $proc$libresoc.v:89357$3832 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88722.5-88722.29" + attribute \src "libresoc.v:89358.5-89358.29" switch \initial - attribute \src "libresoc.v:88722.9-88722.17" + attribute \src "libresoc.v:89358.9-89358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139000,18 +139929,109 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:88782.3-88842.6" - process $proc$libresoc.v:88782$3813 + attribute \src "libresoc.v:89418.3-89478.6" + process $proc$libresoc.v:89418$3833 + assign { } { } + assign { } { } + assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89419.5-89419.29" + switch \initial + attribute \src "libresoc.v:89419.9-89419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out2 + case + assign $1\dec31_sv_out2[2:0] 3'000 + end + sync always + update \dec31_sv_out2 $0\dec31_sv_out2[2:0] + end + attribute \src "libresoc.v:89479.3-89539.6" + process $proc$libresoc.v:89479$3834 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88783.5-88783.29" + attribute \src "libresoc.v:89480.5-89480.29" switch \initial - attribute \src "libresoc.v:88783.9-88783.17" + attribute \src "libresoc.v:89480.9-89480.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139091,18 +140111,18 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:88843.3-88903.6" - process $proc$libresoc.v:88843$3814 + attribute \src "libresoc.v:89540.3-89600.6" + process $proc$libresoc.v:89540$3835 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88844.5-88844.29" + attribute \src "libresoc.v:89541.5-89541.29" switch \initial - attribute \src "libresoc.v:88844.9-88844.17" + attribute \src "libresoc.v:89541.9-89541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139182,18 +140202,18 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:88904.3-88964.6" - process $proc$libresoc.v:88904$3815 + attribute \src "libresoc.v:89601.3-89661.6" + process $proc$libresoc.v:89601$3836 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88905.5-88905.29" + attribute \src "libresoc.v:89602.5-89602.29" switch \initial - attribute \src "libresoc.v:88905.9-88905.17" + attribute \src "libresoc.v:89602.9-89602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139273,18 +140293,18 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:88965.3-89025.6" - process $proc$libresoc.v:88965$3816 + attribute \src "libresoc.v:89662.3-89722.6" + process $proc$libresoc.v:89662$3837 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:88966.5-88966.29" + attribute \src "libresoc.v:89663.5-89663.29" switch \initial - attribute \src "libresoc.v:88966.9-88966.17" + attribute \src "libresoc.v:89663.9-89663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139364,18 +140384,18 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:89026.3-89086.6" - process $proc$libresoc.v:89026$3817 + attribute \src "libresoc.v:89723.3-89783.6" + process $proc$libresoc.v:89723$3838 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89027.5-89027.29" + attribute \src "libresoc.v:89724.5-89724.29" switch \initial - attribute \src "libresoc.v:89027.9-89027.17" + attribute \src "libresoc.v:89724.9-89724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139455,18 +140475,18 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:89087.3-89147.6" - process $proc$libresoc.v:89087$3818 + attribute \src "libresoc.v:89784.3-89844.6" + process $proc$libresoc.v:89784$3839 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89088.5-89088.29" + attribute \src "libresoc.v:89785.5-89785.29" switch \initial - attribute \src "libresoc.v:89088.9-89088.17" + attribute \src "libresoc.v:89785.9-89785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139546,18 +140566,18 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:89148.3-89208.6" - process $proc$libresoc.v:89148$3819 + attribute \src "libresoc.v:89845.3-89905.6" + process $proc$libresoc.v:89845$3840 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89149.5-89149.29" + attribute \src "libresoc.v:89846.5-89846.29" switch \initial - attribute \src "libresoc.v:89149.9-89149.17" + attribute \src "libresoc.v:89846.9-89846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139637,18 +140657,18 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:89209.3-89269.6" - process $proc$libresoc.v:89209$3820 + attribute \src "libresoc.v:89906.3-89966.6" + process $proc$libresoc.v:89906$3841 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89210.5-89210.29" + attribute \src "libresoc.v:89907.5-89907.29" switch \initial - attribute \src "libresoc.v:89210.9-89210.17" + attribute \src "libresoc.v:89907.9-89907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139728,18 +140748,18 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:89270.3-89330.6" - process $proc$libresoc.v:89270$3821 + attribute \src "libresoc.v:89967.3-90027.6" + process $proc$libresoc.v:89967$3842 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:89271.5-89271.29" + attribute \src "libresoc.v:89968.5-89968.29" switch \initial - attribute \src "libresoc.v:89271.9-89271.17" + attribute \src "libresoc.v:89968.9-89968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139819,18 +140839,18 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:89331.3-89391.6" - process $proc$libresoc.v:89331$3822 + attribute \src "libresoc.v:90028.3-90088.6" + process $proc$libresoc.v:90028$3843 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:89332.5-89332.29" + attribute \src "libresoc.v:90029.5-90029.29" switch \initial - attribute \src "libresoc.v:89332.9-89332.17" + attribute \src "libresoc.v:90029.9-90029.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139910,18 +140930,18 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:89392.3-89452.6" - process $proc$libresoc.v:89392$3823 + attribute \src "libresoc.v:90089.3-90149.6" + process $proc$libresoc.v:90089$3844 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89393.5-89393.29" + attribute \src "libresoc.v:90090.5-90090.29" switch \initial - attribute \src "libresoc.v:89393.9-89393.17" + attribute \src "libresoc.v:90090.9-90090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140001,18 +141021,18 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:89453.3-89513.6" - process $proc$libresoc.v:89453$3824 + attribute \src "libresoc.v:90150.3-90210.6" + process $proc$libresoc.v:90150$3845 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:89454.5-89454.29" + attribute \src "libresoc.v:90151.5-90151.29" switch \initial - attribute \src "libresoc.v:89454.9-89454.17" + attribute \src "libresoc.v:90151.9-90151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140092,18 +141112,18 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:89514.3-89574.6" - process $proc$libresoc.v:89514$3825 + attribute \src "libresoc.v:90211.3-90271.6" + process $proc$libresoc.v:90211$3846 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:89515.5-89515.29" + attribute \src "libresoc.v:90212.5-90212.29" switch \initial - attribute \src "libresoc.v:89515.9-89515.17" + attribute \src "libresoc.v:90212.9-90212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140183,18 +141203,18 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:89575.3-89635.6" - process $proc$libresoc.v:89575$3826 + attribute \src "libresoc.v:90272.3-90332.6" + process $proc$libresoc.v:90272$3847 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:89576.5-89576.29" + attribute \src "libresoc.v:90273.5-90273.29" switch \initial - attribute \src "libresoc.v:89576.9-89576.17" + attribute \src "libresoc.v:90273.9-90273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140274,18 +141294,18 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:89636.3-89696.6" - process $proc$libresoc.v:89636$3827 + attribute \src "libresoc.v:90333.3-90393.6" + process $proc$libresoc.v:90333$3848 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:89637.5-89637.29" + attribute \src "libresoc.v:90334.5-90334.29" switch \initial - attribute \src "libresoc.v:89637.9-89637.17" + attribute \src "libresoc.v:90334.9-90334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140365,18 +141385,18 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:89697.3-89757.6" - process $proc$libresoc.v:89697$3828 + attribute \src "libresoc.v:90394.3-90454.6" + process $proc$libresoc.v:90394$3849 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89698.5-89698.29" + attribute \src "libresoc.v:90395.5-90395.29" switch \initial - attribute \src "libresoc.v:89698.9-89698.17" + attribute \src "libresoc.v:90395.9-90395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140477,157 +141497,161 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:89782.1-90730.10" +attribute \src "libresoc.v:90479.1-91456.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:90615.3-90633.6" + attribute \src "libresoc.v:91341.3-91359.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90634.3-90652.6" + attribute \src "libresoc.v:91360.3-91378.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91113.3-91131.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91189.3-91207.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:90847.3-90865.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:90866.3-90884.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91094.3-91112.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91170.3-91188.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91246.3-91264.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90828.3-90846.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90653.3-90671.6" + attribute \src "libresoc.v:91379.3-91397.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90672.3-90690.6" + attribute \src "libresoc.v:91398.3-91416.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90691.3-90709.6" + attribute \src "libresoc.v:91417.3-91435.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91037.3-91055.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91132.3-91150.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91151.3-91169.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91265.3-91283.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91018.3-91036.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90577.3-90595.6" + attribute \src "libresoc.v:91303.3-91321.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90710.3-90728.6" + attribute \src "libresoc.v:91436.3-91454.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91075.3-91093.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91227.3-91245.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90596.3-90614.6" + attribute \src "libresoc.v:91322.3-91340.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90558.3-90576.6" + attribute \src "libresoc.v:91284.3-91302.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91208.3-91226.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:90980.3-90998.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:90999.3-91017.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:90885.3-90903.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:90904.3-90922.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:90923.3-90941.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91056.3-91074.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:89783.7-89783.20" + attribute \src "libresoc.v:90480.7-90480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90615.3-90633.6" + attribute \src "libresoc.v:91341.3-91359.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90634.3-90652.6" + attribute \src "libresoc.v:91360.3-91378.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91113.3-91131.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91189.3-91207.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:90847.3-90865.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:90866.3-90884.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91094.3-91112.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91170.3-91188.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91246.3-91264.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90828.3-90846.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90653.3-90671.6" + attribute \src "libresoc.v:91379.3-91397.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90672.3-90690.6" + attribute \src "libresoc.v:91398.3-91416.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90691.3-90709.6" + attribute \src "libresoc.v:91417.3-91435.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91037.3-91055.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91132.3-91150.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91151.3-91169.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91265.3-91283.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91018.3-91036.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90577.3-90595.6" + attribute \src "libresoc.v:91303.3-91321.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90710.3-90728.6" + attribute \src "libresoc.v:91436.3-91454.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91075.3-91093.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91227.3-91245.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90596.3-90614.6" + attribute \src "libresoc.v:91322.3-91340.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90558.3-90576.6" + attribute \src "libresoc.v:91284.3-91302.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91208.3-91226.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:90980.3-90998.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:90999.3-91017.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:90885.3-90903.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:90904.3-90922.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:90923.3-90941.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91056.3-91074.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub0_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub0_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -140637,7 +141661,7 @@ module \dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -140646,16 +141670,16 @@ module \dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub0_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -140687,7 +141711,7 @@ module \dec31_dec_sub0 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -140704,7 +141728,7 @@ module \dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -140712,7 +141736,7 @@ module \dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -140729,13 +141753,13 @@ module \dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -140812,46 +141836,46 @@ module \dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub0_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub0_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub0_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub0_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140859,8 +141883,8 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub0_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub0_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140868,8 +141892,8 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub0_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub0_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140877,7 +141901,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub0_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140886,7 +141910,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub0_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140895,7 +141919,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub0_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140904,41 +141928,50 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub0_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub0_upd - attribute \src "libresoc.v:89783.7-89783.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub0_upd + attribute \src "libresoc.v:90480.7-90480.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:89783.7-89783.20" - process $proc$libresoc.v:89783$3862 + attribute \src "libresoc.v:90480.7-90480.20" + process $proc$libresoc.v:90480$3884 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90121.3-90139.6" - process $proc$libresoc.v:90121$3830 + attribute \src "libresoc.v:90828.3-90846.6" + process $proc$libresoc.v:90828$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90122.5-90122.29" + attribute \src "libresoc.v:90829.5-90829.29" switch \initial - attribute \src "libresoc.v:90122.9-90122.17" + attribute \src "libresoc.v:90829.9-90829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -140962,18 +141995,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:90140.3-90158.6" - process $proc$libresoc.v:90140$3831 + attribute \src "libresoc.v:90847.3-90865.6" + process $proc$libresoc.v:90847$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90141.5-90141.29" + attribute \src "libresoc.v:90848.5-90848.29" switch \initial - attribute \src "libresoc.v:90141.9-90141.17" + attribute \src "libresoc.v:90848.9-90848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -140997,18 +142030,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:90159.3-90177.6" - process $proc$libresoc.v:90159$3832 + attribute \src "libresoc.v:90866.3-90884.6" + process $proc$libresoc.v:90866$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90160.5-90160.29" + attribute \src "libresoc.v:90867.5-90867.29" switch \initial - attribute \src "libresoc.v:90160.9-90160.17" + attribute \src "libresoc.v:90867.9-90867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141032,18 +142065,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:90178.3-90196.6" - process $proc$libresoc.v:90178$3833 + attribute \src "libresoc.v:90885.3-90903.6" + process $proc$libresoc.v:90885$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90179.5-90179.29" + attribute \src "libresoc.v:90886.5-90886.29" switch \initial - attribute \src "libresoc.v:90179.9-90179.17" + attribute \src "libresoc.v:90886.9-90886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141067,18 +142100,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:90197.3-90215.6" - process $proc$libresoc.v:90197$3834 + attribute \src "libresoc.v:90904.3-90922.6" + process $proc$libresoc.v:90904$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90198.5-90198.29" + attribute \src "libresoc.v:90905.5-90905.29" switch \initial - attribute \src "libresoc.v:90198.9-90198.17" + attribute \src "libresoc.v:90905.9-90905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141102,18 +142135,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:90216.3-90234.6" - process $proc$libresoc.v:90216$3835 + attribute \src "libresoc.v:90923.3-90941.6" + process $proc$libresoc.v:90923$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90217.5-90217.29" + attribute \src "libresoc.v:90924.5-90924.29" switch \initial - attribute \src "libresoc.v:90217.9-90217.17" + attribute \src "libresoc.v:90924.9-90924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141137,18 +142170,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:90235.3-90253.6" - process $proc$libresoc.v:90235$3836 + attribute \src "libresoc.v:90942.3-90960.6" + process $proc$libresoc.v:90942$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90236.5-90236.29" + attribute \src "libresoc.v:90943.5-90943.29" switch \initial - attribute \src "libresoc.v:90236.9-90236.17" + attribute \src "libresoc.v:90943.9-90943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141172,18 +142205,53 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:90254.3-90272.6" - process $proc$libresoc.v:90254$3837 + attribute \src "libresoc.v:90961.3-90979.6" + process $proc$libresoc.v:90961$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90962.5-90962.29" + switch \initial + attribute \src "libresoc.v:90962.9-90962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] + end + attribute \src "libresoc.v:90980.3-90998.6" + process $proc$libresoc.v:90980$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90255.5-90255.29" + attribute \src "libresoc.v:90981.5-90981.29" switch \initial - attribute \src "libresoc.v:90255.9-90255.17" + attribute \src "libresoc.v:90981.9-90981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141207,18 +142275,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:90273.3-90291.6" - process $proc$libresoc.v:90273$3838 + attribute \src "libresoc.v:90999.3-91017.6" + process $proc$libresoc.v:90999$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90274.5-90274.29" + attribute \src "libresoc.v:91000.5-91000.29" switch \initial - attribute \src "libresoc.v:90274.9-90274.17" + attribute \src "libresoc.v:91000.9-91000.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141242,18 +142310,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:90292.3-90310.6" - process $proc$libresoc.v:90292$3839 + attribute \src "libresoc.v:91018.3-91036.6" + process $proc$libresoc.v:91018$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90293.5-90293.29" + attribute \src "libresoc.v:91019.5-91019.29" switch \initial - attribute \src "libresoc.v:90293.9-90293.17" + attribute \src "libresoc.v:91019.9-91019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141277,88 +142345,88 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:90311.3-90329.6" - process $proc$libresoc.v:90311$3840 + attribute \src "libresoc.v:91037.3-91055.6" + process $proc$libresoc.v:91037$3862 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90312.5-90312.29" + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:91038.5-91038.29" switch \initial - attribute \src "libresoc.v:90312.9-90312.17" + attribute \src "libresoc.v:91038.9-91038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 case - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:90330.3-90348.6" - process $proc$libresoc.v:90330$3841 + attribute \src "libresoc.v:91056.3-91074.6" + process $proc$libresoc.v:91056$3863 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90331.5-90331.29" + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:91057.5-91057.29" switch \initial - attribute \src "libresoc.v:90331.9-90331.17" + attribute \src "libresoc.v:91057.9-91057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 end sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:90349.3-90367.6" - process $proc$libresoc.v:90349$3842 + attribute \src "libresoc.v:91075.3-91093.6" + process $proc$libresoc.v:91075$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90350.5-90350.29" + attribute \src "libresoc.v:91076.5-91076.29" switch \initial - attribute \src "libresoc.v:90350.9-90350.17" + attribute \src "libresoc.v:91076.9-91076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141382,18 +142450,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:90368.3-90386.6" - process $proc$libresoc.v:90368$3843 + attribute \src "libresoc.v:91094.3-91112.6" + process $proc$libresoc.v:91094$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90369.5-90369.29" + attribute \src "libresoc.v:91095.5-91095.29" switch \initial - attribute \src "libresoc.v:90369.9-90369.17" + attribute \src "libresoc.v:91095.9-91095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141417,18 +142485,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:90387.3-90405.6" - process $proc$libresoc.v:90387$3844 + attribute \src "libresoc.v:91113.3-91131.6" + process $proc$libresoc.v:91113$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90388.5-90388.29" + attribute \src "libresoc.v:91114.5-91114.29" switch \initial - attribute \src "libresoc.v:90388.9-90388.17" + attribute \src "libresoc.v:91114.9-91114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141452,18 +142520,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:90406.3-90424.6" - process $proc$libresoc.v:90406$3845 + attribute \src "libresoc.v:91132.3-91150.6" + process $proc$libresoc.v:91132$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90407.5-90407.29" + attribute \src "libresoc.v:91133.5-91133.29" switch \initial - attribute \src "libresoc.v:90407.9-90407.17" + attribute \src "libresoc.v:91133.9-91133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141487,18 +142555,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:90425.3-90443.6" - process $proc$libresoc.v:90425$3846 + attribute \src "libresoc.v:91151.3-91169.6" + process $proc$libresoc.v:91151$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90426.5-90426.29" + attribute \src "libresoc.v:91152.5-91152.29" switch \initial - attribute \src "libresoc.v:90426.9-90426.17" + attribute \src "libresoc.v:91152.9-91152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141522,18 +142590,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:90444.3-90462.6" - process $proc$libresoc.v:90444$3847 + attribute \src "libresoc.v:91170.3-91188.6" + process $proc$libresoc.v:91170$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90445.5-90445.29" + attribute \src "libresoc.v:91171.5-91171.29" switch \initial - attribute \src "libresoc.v:90445.9-90445.17" + attribute \src "libresoc.v:91171.9-91171.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141557,18 +142625,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:90463.3-90481.6" - process $proc$libresoc.v:90463$3848 + attribute \src "libresoc.v:91189.3-91207.6" + process $proc$libresoc.v:91189$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90464.5-90464.29" + attribute \src "libresoc.v:91190.5-91190.29" switch \initial - attribute \src "libresoc.v:90464.9-90464.17" + attribute \src "libresoc.v:91190.9-91190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141592,18 +142660,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:90482.3-90500.6" - process $proc$libresoc.v:90482$3849 + attribute \src "libresoc.v:91208.3-91226.6" + process $proc$libresoc.v:91208$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90483.5-90483.29" + attribute \src "libresoc.v:91209.5-91209.29" switch \initial - attribute \src "libresoc.v:90483.9-90483.17" + attribute \src "libresoc.v:91209.9-91209.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141627,18 +142695,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:90501.3-90519.6" - process $proc$libresoc.v:90501$3850 + attribute \src "libresoc.v:91227.3-91245.6" + process $proc$libresoc.v:91227$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90502.5-90502.29" + attribute \src "libresoc.v:91228.5-91228.29" switch \initial - attribute \src "libresoc.v:90502.9-90502.17" + attribute \src "libresoc.v:91228.9-91228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141662,88 +142730,88 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:90520.3-90538.6" - process $proc$libresoc.v:90520$3851 + attribute \src "libresoc.v:91246.3-91264.6" + process $proc$libresoc.v:91246$3873 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90521.5-90521.29" + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:91247.5-91247.29" switch \initial - attribute \src "libresoc.v:90521.9-90521.17" + attribute \src "libresoc.v:91247.9-91247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'11000 case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'00000 end sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:90539.3-90557.6" - process $proc$libresoc.v:90539$3852 + attribute \src "libresoc.v:91265.3-91283.6" + process $proc$libresoc.v:91265$3874 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90540.5-90540.29" + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:91266.5-91266.29" switch \initial - attribute \src "libresoc.v:90540.9-90540.17" + attribute \src "libresoc.v:91266.9-91266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:90558.3-90576.6" - process $proc$libresoc.v:90558$3853 + attribute \src "libresoc.v:91284.3-91302.6" + process $proc$libresoc.v:91284$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90559.5-90559.29" + attribute \src "libresoc.v:91285.5-91285.29" switch \initial - attribute \src "libresoc.v:90559.9-90559.17" + attribute \src "libresoc.v:91285.9-91285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141767,18 +142835,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:90577.3-90595.6" - process $proc$libresoc.v:90577$3854 + attribute \src "libresoc.v:91303.3-91321.6" + process $proc$libresoc.v:91303$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90578.5-90578.29" + attribute \src "libresoc.v:91304.5-91304.29" switch \initial - attribute \src "libresoc.v:90578.9-90578.17" + attribute \src "libresoc.v:91304.9-91304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141802,18 +142870,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:90596.3-90614.6" - process $proc$libresoc.v:90596$3855 + attribute \src "libresoc.v:91322.3-91340.6" + process $proc$libresoc.v:91322$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90597.5-90597.29" + attribute \src "libresoc.v:91323.5-91323.29" switch \initial - attribute \src "libresoc.v:90597.9-90597.17" + attribute \src "libresoc.v:91323.9-91323.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141837,18 +142905,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:90615.3-90633.6" - process $proc$libresoc.v:90615$3856 + attribute \src "libresoc.v:91341.3-91359.6" + process $proc$libresoc.v:91341$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90616.5-90616.29" + attribute \src "libresoc.v:91342.5-91342.29" switch \initial - attribute \src "libresoc.v:90616.9-90616.17" + attribute \src "libresoc.v:91342.9-91342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141872,18 +142940,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:90634.3-90652.6" - process $proc$libresoc.v:90634$3857 + attribute \src "libresoc.v:91360.3-91378.6" + process $proc$libresoc.v:91360$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90635.5-90635.29" + attribute \src "libresoc.v:91361.5-91361.29" switch \initial - attribute \src "libresoc.v:90635.9-90635.17" + attribute \src "libresoc.v:91361.9-91361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141907,18 +142975,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:90653.3-90671.6" - process $proc$libresoc.v:90653$3858 + attribute \src "libresoc.v:91379.3-91397.6" + process $proc$libresoc.v:91379$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90654.5-90654.29" + attribute \src "libresoc.v:91380.5-91380.29" switch \initial - attribute \src "libresoc.v:90654.9-90654.17" + attribute \src "libresoc.v:91380.9-91380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141942,18 +143010,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:90672.3-90690.6" - process $proc$libresoc.v:90672$3859 + attribute \src "libresoc.v:91398.3-91416.6" + process $proc$libresoc.v:91398$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90673.5-90673.29" + attribute \src "libresoc.v:91399.5-91399.29" switch \initial - attribute \src "libresoc.v:90673.9-90673.17" + attribute \src "libresoc.v:91399.9-91399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141977,18 +143045,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:90691.3-90709.6" - process $proc$libresoc.v:90691$3860 + attribute \src "libresoc.v:91417.3-91435.6" + process $proc$libresoc.v:91417$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90692.5-90692.29" + attribute \src "libresoc.v:91418.5-91418.29" switch \initial - attribute \src "libresoc.v:90692.9-90692.17" + attribute \src "libresoc.v:91418.9-91418.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142012,18 +143080,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:90710.3-90728.6" - process $proc$libresoc.v:90710$3861 + attribute \src "libresoc.v:91436.3-91454.6" + process $proc$libresoc.v:91436$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90711.5-90711.29" + attribute \src "libresoc.v:91437.5-91437.29" switch \initial - attribute \src "libresoc.v:90711.9-90711.17" + attribute \src "libresoc.v:91437.9-91437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142049,157 +143117,161 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90734.1-92258.10" +attribute \src "libresoc.v:91460.1-93031.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:92035.3-92071.6" + attribute \src "libresoc.v:92808.3-92844.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92072.3-92108.6" + attribute \src "libresoc.v:92845.3-92881.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:91591.3-91627.6" + attribute \src "libresoc.v:92364.3-92400.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91739.3-91775.6" + attribute \src "libresoc.v:92512.3-92548.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91110.3-91146.6" + attribute \src "libresoc.v:91846.3-91882.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91147.3-91183.6" + attribute \src "libresoc.v:91883.3-91919.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91554.3-91590.6" + attribute \src "libresoc.v:92327.3-92363.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91702.3-91738.6" + attribute \src "libresoc.v:92475.3-92511.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91887.3-91923.6" + attribute \src "libresoc.v:92623.3-92659.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91073.3-91109.6" + attribute \src "libresoc.v:91809.3-91845.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92109.3-92145.6" + attribute \src "libresoc.v:92882.3-92918.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92146.3-92182.6" + attribute \src "libresoc.v:92919.3-92955.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92183.3-92219.6" + attribute \src "libresoc.v:92956.3-92992.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:91480.3-91516.6" + attribute \src "libresoc.v:92216.3-92252.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91628.3-91664.6" + attribute \src "libresoc.v:92401.3-92437.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91665.3-91701.6" + attribute \src "libresoc.v:92438.3-92474.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91850.3-91886.6" + attribute \src "libresoc.v:92660.3-92696.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91406.3-91442.6" + attribute \src "libresoc.v:92179.3-92215.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91961.3-91997.6" + attribute \src "libresoc.v:92734.3-92770.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92220.3-92256.6" + attribute \src "libresoc.v:92993.3-93029.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:91517.3-91553.6" + attribute \src "libresoc.v:92290.3-92326.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91813.3-91849.6" + attribute \src "libresoc.v:92586.3-92622.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91998.3-92034.6" + attribute \src "libresoc.v:92771.3-92807.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91924.3-91960.6" + attribute \src "libresoc.v:92697.3-92733.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91776.3-91812.6" + attribute \src "libresoc.v:92549.3-92585.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91332.3-91368.6" + attribute \src "libresoc.v:92105.3-92141.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91369.3-91405.6" + attribute \src "libresoc.v:92142.3-92178.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91184.3-91220.6" + attribute \src "libresoc.v:91920.3-91956.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91221.3-91257.6" + attribute \src "libresoc.v:91957.3-91993.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91258.3-91294.6" + attribute \src "libresoc.v:91994.3-92030.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91295.3-91331.6" + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91443.3-91479.6" + attribute \src "libresoc.v:92253.3-92289.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:90735.7-90735.20" + attribute \src "libresoc.v:91461.7-91461.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92035.3-92071.6" + attribute \src "libresoc.v:92808.3-92844.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92072.3-92108.6" + attribute \src "libresoc.v:92845.3-92881.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:91591.3-91627.6" + attribute \src "libresoc.v:92364.3-92400.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91739.3-91775.6" + attribute \src "libresoc.v:92512.3-92548.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91110.3-91146.6" + attribute \src "libresoc.v:91846.3-91882.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91147.3-91183.6" + attribute \src "libresoc.v:91883.3-91919.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91554.3-91590.6" + attribute \src "libresoc.v:92327.3-92363.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91702.3-91738.6" + attribute \src "libresoc.v:92475.3-92511.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91887.3-91923.6" + attribute \src "libresoc.v:92623.3-92659.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91073.3-91109.6" + attribute \src "libresoc.v:91809.3-91845.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92109.3-92145.6" + attribute \src "libresoc.v:92882.3-92918.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92146.3-92182.6" + attribute \src "libresoc.v:92919.3-92955.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92183.3-92219.6" + attribute \src "libresoc.v:92956.3-92992.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:91480.3-91516.6" + attribute \src "libresoc.v:92216.3-92252.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91628.3-91664.6" + attribute \src "libresoc.v:92401.3-92437.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91665.3-91701.6" + attribute \src "libresoc.v:92438.3-92474.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91850.3-91886.6" + attribute \src "libresoc.v:92660.3-92696.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91406.3-91442.6" + attribute \src "libresoc.v:92179.3-92215.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91961.3-91997.6" + attribute \src "libresoc.v:92734.3-92770.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92220.3-92256.6" + attribute \src "libresoc.v:92993.3-93029.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:91517.3-91553.6" + attribute \src "libresoc.v:92290.3-92326.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91813.3-91849.6" + attribute \src "libresoc.v:92586.3-92622.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91998.3-92034.6" + attribute \src "libresoc.v:92771.3-92807.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91924.3-91960.6" + attribute \src "libresoc.v:92697.3-92733.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91776.3-91812.6" + attribute \src "libresoc.v:92549.3-92585.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91332.3-91368.6" + attribute \src "libresoc.v:92105.3-92141.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91369.3-91405.6" + attribute \src "libresoc.v:92142.3-92178.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91184.3-91220.6" + attribute \src "libresoc.v:91920.3-91956.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91221.3-91257.6" + attribute \src "libresoc.v:91957.3-91993.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91258.3-91294.6" + attribute \src "libresoc.v:91994.3-92030.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91295.3-91331.6" + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91443.3-91479.6" + attribute \src "libresoc.v:92253.3-92289.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub10_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub10_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub10_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -142209,7 +143281,7 @@ module \dec31_dec_sub10 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -142218,16 +143290,16 @@ module \dec31_dec_sub10 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub10_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -142259,7 +143331,7 @@ module \dec31_dec_sub10 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -142276,7 +143348,7 @@ module \dec31_dec_sub10 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -142284,7 +143356,7 @@ module \dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -142301,13 +143373,13 @@ module \dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -142384,46 +143456,46 @@ module \dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub10_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub10_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub10_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub10_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142431,8 +143503,8 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub10_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub10_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142440,8 +143512,8 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub10_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub10_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142449,7 +143521,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub10_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142458,7 +143530,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub10_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142467,7 +143539,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub10_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142476,41 +143548,50 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub10_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub10_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub10_upd - attribute \src "libresoc.v:90735.7-90735.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub10_upd + attribute \src "libresoc.v:91461.7-91461.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:90735.7-90735.20" - process $proc$libresoc.v:90735$3895 + attribute \src "libresoc.v:91461.7-91461.20" + process $proc$libresoc.v:91461$3918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91073.3-91109.6" - process $proc$libresoc.v:91073$3863 + attribute \src "libresoc.v:91809.3-91845.6" + process $proc$libresoc.v:91809$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:91074.5-91074.29" + attribute \src "libresoc.v:91810.5-91810.29" switch \initial - attribute \src "libresoc.v:91074.9-91074.17" + attribute \src "libresoc.v:91810.9-91810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142558,18 +143639,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:91110.3-91146.6" - process $proc$libresoc.v:91110$3864 + attribute \src "libresoc.v:91846.3-91882.6" + process $proc$libresoc.v:91846$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91111.5-91111.29" + attribute \src "libresoc.v:91847.5-91847.29" switch \initial - attribute \src "libresoc.v:91111.9-91111.17" + attribute \src "libresoc.v:91847.9-91847.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142617,18 +143698,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:91147.3-91183.6" - process $proc$libresoc.v:91147$3865 + attribute \src "libresoc.v:91883.3-91919.6" + process $proc$libresoc.v:91883$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91148.5-91148.29" + attribute \src "libresoc.v:91884.5-91884.29" switch \initial - attribute \src "libresoc.v:91148.9-91148.17" + attribute \src "libresoc.v:91884.9-91884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142676,18 +143757,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:91184.3-91220.6" - process $proc$libresoc.v:91184$3866 + attribute \src "libresoc.v:91920.3-91956.6" + process $proc$libresoc.v:91920$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91185.5-91185.29" + attribute \src "libresoc.v:91921.5-91921.29" switch \initial - attribute \src "libresoc.v:91185.9-91185.17" + attribute \src "libresoc.v:91921.9-91921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142735,18 +143816,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:91221.3-91257.6" - process $proc$libresoc.v:91221$3867 + attribute \src "libresoc.v:91957.3-91993.6" + process $proc$libresoc.v:91957$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91222.5-91222.29" + attribute \src "libresoc.v:91958.5-91958.29" switch \initial - attribute \src "libresoc.v:91222.9-91222.17" + attribute \src "libresoc.v:91958.9-91958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142794,18 +143875,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:91258.3-91294.6" - process $proc$libresoc.v:91258$3868 + attribute \src "libresoc.v:91994.3-92030.6" + process $proc$libresoc.v:91994$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91259.5-91259.29" + attribute \src "libresoc.v:91995.5-91995.29" switch \initial - attribute \src "libresoc.v:91259.9-91259.17" + attribute \src "libresoc.v:91995.9-91995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142853,18 +143934,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:91295.3-91331.6" - process $proc$libresoc.v:91295$3869 + attribute \src "libresoc.v:92031.3-92067.6" + process $proc$libresoc.v:92031$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91296.5-91296.29" + attribute \src "libresoc.v:92032.5-92032.29" switch \initial - attribute \src "libresoc.v:91296.9-91296.17" + attribute \src "libresoc.v:92032.9-92032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142912,18 +143993,77 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:91332.3-91368.6" - process $proc$libresoc.v:91332$3870 + attribute \src "libresoc.v:92068.3-92104.6" + process $proc$libresoc.v:92068$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92069.5-92069.29" + switch \initial + attribute \src "libresoc.v:92069.9-92069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] + end + attribute \src "libresoc.v:92105.3-92141.6" + process $proc$libresoc.v:92105$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91333.5-91333.29" + attribute \src "libresoc.v:92106.5-92106.29" switch \initial - attribute \src "libresoc.v:91333.9-91333.17" + attribute \src "libresoc.v:92106.9-92106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142971,18 +144111,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:91369.3-91405.6" - process $proc$libresoc.v:91369$3871 + attribute \src "libresoc.v:92142.3-92178.6" + process $proc$libresoc.v:92142$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91370.5-91370.29" + attribute \src "libresoc.v:92143.5-92143.29" switch \initial - attribute \src "libresoc.v:91370.9-91370.17" + attribute \src "libresoc.v:92143.9-92143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143030,18 +144170,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:91406.3-91442.6" - process $proc$libresoc.v:91406$3872 + attribute \src "libresoc.v:92179.3-92215.6" + process $proc$libresoc.v:92179$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91407.5-91407.29" + attribute \src "libresoc.v:92180.5-92180.29" switch \initial - attribute \src "libresoc.v:91407.9-91407.17" + attribute \src "libresoc.v:92180.9-92180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143089,136 +144229,136 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:91443.3-91479.6" - process $proc$libresoc.v:91443$3873 + attribute \src "libresoc.v:92216.3-92252.6" + process $proc$libresoc.v:92216$3896 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:91444.5-91444.29" + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:92217.5-92217.29" switch \initial - attribute \src "libresoc.v:91444.9-91444.17" + attribute \src "libresoc.v:92217.9-92217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:91480.3-91516.6" - process $proc$libresoc.v:91480$3874 + attribute \src "libresoc.v:92253.3-92289.6" + process $proc$libresoc.v:92253$3897 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91481.5-91481.29" + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:92254.5-92254.29" switch \initial - attribute \src "libresoc.v:91481.9-91481.17" + attribute \src "libresoc.v:92254.9-92254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 end sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:91517.3-91553.6" - process $proc$libresoc.v:91517$3875 + attribute \src "libresoc.v:92290.3-92326.6" + process $proc$libresoc.v:92290$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91518.5-91518.29" + attribute \src "libresoc.v:92291.5-92291.29" switch \initial - attribute \src "libresoc.v:91518.9-91518.17" + attribute \src "libresoc.v:92291.9-92291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143266,18 +144406,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:91554.3-91590.6" - process $proc$libresoc.v:91554$3876 + attribute \src "libresoc.v:92327.3-92363.6" + process $proc$libresoc.v:92327$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91555.5-91555.29" + attribute \src "libresoc.v:92328.5-92328.29" switch \initial - attribute \src "libresoc.v:91555.9-91555.17" + attribute \src "libresoc.v:92328.9-92328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143325,18 +144465,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:91591.3-91627.6" - process $proc$libresoc.v:91591$3877 + attribute \src "libresoc.v:92364.3-92400.6" + process $proc$libresoc.v:92364$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91592.5-91592.29" + attribute \src "libresoc.v:92365.5-92365.29" switch \initial - attribute \src "libresoc.v:91592.9-91592.17" + attribute \src "libresoc.v:92365.9-92365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143384,18 +144524,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:91628.3-91664.6" - process $proc$libresoc.v:91628$3878 + attribute \src "libresoc.v:92401.3-92437.6" + process $proc$libresoc.v:92401$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91629.5-91629.29" + attribute \src "libresoc.v:92402.5-92402.29" switch \initial - attribute \src "libresoc.v:91629.9-91629.17" + attribute \src "libresoc.v:92402.9-92402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143443,18 +144583,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:91665.3-91701.6" - process $proc$libresoc.v:91665$3879 + attribute \src "libresoc.v:92438.3-92474.6" + process $proc$libresoc.v:92438$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91666.5-91666.29" + attribute \src "libresoc.v:92439.5-92439.29" switch \initial - attribute \src "libresoc.v:91666.9-91666.17" + attribute \src "libresoc.v:92439.9-92439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143502,18 +144642,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:91702.3-91738.6" - process $proc$libresoc.v:91702$3880 + attribute \src "libresoc.v:92475.3-92511.6" + process $proc$libresoc.v:92475$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91703.5-91703.29" + attribute \src "libresoc.v:92476.5-92476.29" switch \initial - attribute \src "libresoc.v:91703.9-91703.17" + attribute \src "libresoc.v:92476.9-92476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143561,18 +144701,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:91739.3-91775.6" - process $proc$libresoc.v:91739$3881 + attribute \src "libresoc.v:92512.3-92548.6" + process $proc$libresoc.v:92512$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91740.5-91740.29" + attribute \src "libresoc.v:92513.5-92513.29" switch \initial - attribute \src "libresoc.v:91740.9-91740.17" + attribute \src "libresoc.v:92513.9-92513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143620,18 +144760,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:91776.3-91812.6" - process $proc$libresoc.v:91776$3882 + attribute \src "libresoc.v:92549.3-92585.6" + process $proc$libresoc.v:92549$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91777.5-91777.29" + attribute \src "libresoc.v:92550.5-92550.29" switch \initial - attribute \src "libresoc.v:91777.9-91777.17" + attribute \src "libresoc.v:92550.9-92550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143679,18 +144819,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:91813.3-91849.6" - process $proc$libresoc.v:91813$3883 + attribute \src "libresoc.v:92586.3-92622.6" + process $proc$libresoc.v:92586$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91814.5-91814.29" + attribute \src "libresoc.v:92587.5-92587.29" switch \initial - attribute \src "libresoc.v:91814.9-91814.17" + attribute \src "libresoc.v:92587.9-92587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143738,136 +144878,136 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:91850.3-91886.6" - process $proc$libresoc.v:91850$3884 + attribute \src "libresoc.v:92623.3-92659.6" + process $proc$libresoc.v:92623$3907 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91851.5-91851.29" + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:92624.5-92624.29" switch \initial - attribute \src "libresoc.v:91851.9-91851.17" + attribute \src "libresoc.v:92624.9-92624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'00000 end sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:91887.3-91923.6" - process $proc$libresoc.v:91887$3885 + attribute \src "libresoc.v:92660.3-92696.6" + process $proc$libresoc.v:92660$3908 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91888.5-91888.29" + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:92661.5-92661.29" switch \initial - attribute \src "libresoc.v:91888.9-91888.17" + attribute \src "libresoc.v:92661.9-92661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:91924.3-91960.6" - process $proc$libresoc.v:91924$3886 + attribute \src "libresoc.v:92697.3-92733.6" + process $proc$libresoc.v:92697$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91925.5-91925.29" + attribute \src "libresoc.v:92698.5-92698.29" switch \initial - attribute \src "libresoc.v:91925.9-91925.17" + attribute \src "libresoc.v:92698.9-92698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143915,18 +145055,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:91961.3-91997.6" - process $proc$libresoc.v:91961$3887 + attribute \src "libresoc.v:92734.3-92770.6" + process $proc$libresoc.v:92734$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:91962.5-91962.29" + attribute \src "libresoc.v:92735.5-92735.29" switch \initial - attribute \src "libresoc.v:91962.9-91962.17" + attribute \src "libresoc.v:92735.9-92735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143974,18 +145114,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:91998.3-92034.6" - process $proc$libresoc.v:91998$3888 + attribute \src "libresoc.v:92771.3-92807.6" + process $proc$libresoc.v:92771$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91999.5-91999.29" + attribute \src "libresoc.v:92772.5-92772.29" switch \initial - attribute \src "libresoc.v:91999.9-91999.17" + attribute \src "libresoc.v:92772.9-92772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144033,18 +145173,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:92035.3-92071.6" - process $proc$libresoc.v:92035$3889 + attribute \src "libresoc.v:92808.3-92844.6" + process $proc$libresoc.v:92808$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92036.5-92036.29" + attribute \src "libresoc.v:92809.5-92809.29" switch \initial - attribute \src "libresoc.v:92036.9-92036.17" + attribute \src "libresoc.v:92809.9-92809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144092,18 +145232,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:92072.3-92108.6" - process $proc$libresoc.v:92072$3890 + attribute \src "libresoc.v:92845.3-92881.6" + process $proc$libresoc.v:92845$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92073.5-92073.29" + attribute \src "libresoc.v:92846.5-92846.29" switch \initial - attribute \src "libresoc.v:92073.9-92073.17" + attribute \src "libresoc.v:92846.9-92846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144151,18 +145291,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:92109.3-92145.6" - process $proc$libresoc.v:92109$3891 + attribute \src "libresoc.v:92882.3-92918.6" + process $proc$libresoc.v:92882$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92110.5-92110.29" + attribute \src "libresoc.v:92883.5-92883.29" switch \initial - attribute \src "libresoc.v:92110.9-92110.17" + attribute \src "libresoc.v:92883.9-92883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144210,18 +145350,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:92146.3-92182.6" - process $proc$libresoc.v:92146$3892 + attribute \src "libresoc.v:92919.3-92955.6" + process $proc$libresoc.v:92919$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92147.5-92147.29" + attribute \src "libresoc.v:92920.5-92920.29" switch \initial - attribute \src "libresoc.v:92147.9-92147.17" + attribute \src "libresoc.v:92920.9-92920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144269,18 +145409,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:92183.3-92219.6" - process $proc$libresoc.v:92183$3893 + attribute \src "libresoc.v:92956.3-92992.6" + process $proc$libresoc.v:92956$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92184.5-92184.29" + attribute \src "libresoc.v:92957.5-92957.29" switch \initial - attribute \src "libresoc.v:92184.9-92184.17" + attribute \src "libresoc.v:92957.9-92957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144328,18 +145468,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:92220.3-92256.6" - process $proc$libresoc.v:92220$3894 + attribute \src "libresoc.v:92993.3-93029.6" + process $proc$libresoc.v:92993$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92221.5-92221.29" + attribute \src "libresoc.v:92994.5-92994.29" switch \initial - attribute \src "libresoc.v:92221.9-92221.17" + attribute \src "libresoc.v:92994.9-92994.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144389,157 +145529,161 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92262.1-94362.10" +attribute \src "libresoc.v:93035.1-95200.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:94031.3-94085.6" + attribute \src "libresoc.v:94869.3-94923.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94086.3-94140.6" + attribute \src "libresoc.v:94924.3-94978.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:93371.3-93425.6" + attribute \src "libresoc.v:94209.3-94263.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93591.3-93645.6" + attribute \src "libresoc.v:94429.3-94483.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92656.3-92710.6" + attribute \src "libresoc.v:93439.3-93493.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92711.3-92765.6" + attribute \src "libresoc.v:93494.3-93548.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93316.3-93370.6" + attribute \src "libresoc.v:94154.3-94208.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93536.3-93590.6" + attribute \src "libresoc.v:94374.3-94428.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93811.3-93865.6" + attribute \src "libresoc.v:94594.3-94648.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:92601.3-92655.6" + attribute \src "libresoc.v:93384.3-93438.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94141.3-94195.6" + attribute \src "libresoc.v:94979.3-95033.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94196.3-94250.6" + attribute \src "libresoc.v:95034.3-95088.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94251.3-94305.6" + attribute \src "libresoc.v:95089.3-95143.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93206.3-93260.6" + attribute \src "libresoc.v:93989.3-94043.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93426.3-93480.6" + attribute \src "libresoc.v:94264.3-94318.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93481.3-93535.6" + attribute \src "libresoc.v:94319.3-94373.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93756.3-93810.6" + attribute \src "libresoc.v:94649.3-94703.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93096.3-93150.6" + attribute \src "libresoc.v:93934.3-93988.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93921.3-93975.6" + attribute \src "libresoc.v:94759.3-94813.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94306.3-94360.6" + attribute \src "libresoc.v:95144.3-95198.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93261.3-93315.6" + attribute \src "libresoc.v:94099.3-94153.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93701.3-93755.6" + attribute \src "libresoc.v:94539.3-94593.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93976.3-94030.6" + attribute \src "libresoc.v:94814.3-94868.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93866.3-93920.6" + attribute \src "libresoc.v:94704.3-94758.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93646.3-93700.6" + attribute \src "libresoc.v:94484.3-94538.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92986.3-93040.6" + attribute \src "libresoc.v:93824.3-93878.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93041.3-93095.6" + attribute \src "libresoc.v:93879.3-93933.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92766.3-92820.6" + attribute \src "libresoc.v:93549.3-93603.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92821.3-92875.6" + attribute \src "libresoc.v:93604.3-93658.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92876.3-92930.6" + attribute \src "libresoc.v:93659.3-93713.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92931.3-92985.6" + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93151.3-93205.6" + attribute \src "libresoc.v:94044.3-94098.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:92263.7-92263.20" + attribute \src "libresoc.v:93036.7-93036.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94031.3-94085.6" + attribute \src "libresoc.v:94869.3-94923.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94086.3-94140.6" + attribute \src "libresoc.v:94924.3-94978.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:93371.3-93425.6" + attribute \src "libresoc.v:94209.3-94263.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93591.3-93645.6" + attribute \src "libresoc.v:94429.3-94483.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92656.3-92710.6" + attribute \src "libresoc.v:93439.3-93493.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92711.3-92765.6" + attribute \src "libresoc.v:93494.3-93548.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93316.3-93370.6" + attribute \src "libresoc.v:94154.3-94208.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93536.3-93590.6" + attribute \src "libresoc.v:94374.3-94428.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93811.3-93865.6" + attribute \src "libresoc.v:94594.3-94648.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:92601.3-92655.6" + attribute \src "libresoc.v:93384.3-93438.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94141.3-94195.6" + attribute \src "libresoc.v:94979.3-95033.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94196.3-94250.6" + attribute \src "libresoc.v:95034.3-95088.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94251.3-94305.6" + attribute \src "libresoc.v:95089.3-95143.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93206.3-93260.6" + attribute \src "libresoc.v:93989.3-94043.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93426.3-93480.6" + attribute \src "libresoc.v:94264.3-94318.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93481.3-93535.6" + attribute \src "libresoc.v:94319.3-94373.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93756.3-93810.6" + attribute \src "libresoc.v:94649.3-94703.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93096.3-93150.6" + attribute \src "libresoc.v:93934.3-93988.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93921.3-93975.6" + attribute \src "libresoc.v:94759.3-94813.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94306.3-94360.6" + attribute \src "libresoc.v:95144.3-95198.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93261.3-93315.6" + attribute \src "libresoc.v:94099.3-94153.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93701.3-93755.6" + attribute \src "libresoc.v:94539.3-94593.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93976.3-94030.6" + attribute \src "libresoc.v:94814.3-94868.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93866.3-93920.6" + attribute \src "libresoc.v:94704.3-94758.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93646.3-93700.6" + attribute \src "libresoc.v:94484.3-94538.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92986.3-93040.6" + attribute \src "libresoc.v:93824.3-93878.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93041.3-93095.6" + attribute \src "libresoc.v:93879.3-93933.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92766.3-92820.6" + attribute \src "libresoc.v:93549.3-93603.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92821.3-92875.6" + attribute \src "libresoc.v:93604.3-93658.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92876.3-92930.6" + attribute \src "libresoc.v:93659.3-93713.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92931.3-92985.6" + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93151.3-93205.6" + attribute \src "libresoc.v:94044.3-94098.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub11_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub11_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub11_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -144549,7 +145693,7 @@ module \dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144558,16 +145702,16 @@ module \dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub11_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -144599,7 +145743,7 @@ module \dec31_dec_sub11 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -144616,7 +145760,7 @@ module \dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -144624,7 +145768,7 @@ module \dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144641,13 +145785,13 @@ module \dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -144724,46 +145868,46 @@ module \dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub11_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub11_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub11_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub11_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144771,8 +145915,8 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub11_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub11_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144780,8 +145924,8 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub11_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub11_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144789,7 +145933,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub11_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144798,7 +145942,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub11_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144807,7 +145951,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub11_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144816,41 +145960,50 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub11_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub11_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub11_upd - attribute \src "libresoc.v:92263.7-92263.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub11_upd + attribute \src "libresoc.v:93036.7-93036.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:92263.7-92263.20" - process $proc$libresoc.v:92263$3928 + attribute \src "libresoc.v:93036.7-93036.20" + process $proc$libresoc.v:93036$3952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:92601.3-92655.6" - process $proc$libresoc.v:92601$3896 + attribute \src "libresoc.v:93384.3-93438.6" + process $proc$libresoc.v:93384$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:92602.5-92602.29" + attribute \src "libresoc.v:93385.5-93385.29" switch \initial - attribute \src "libresoc.v:92602.9-92602.17" + attribute \src "libresoc.v:93385.9-93385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -144922,18 +146075,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:92656.3-92710.6" - process $proc$libresoc.v:92656$3897 + attribute \src "libresoc.v:93439.3-93493.6" + process $proc$libresoc.v:93439$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92657.5-92657.29" + attribute \src "libresoc.v:93440.5-93440.29" switch \initial - attribute \src "libresoc.v:92657.9-92657.17" + attribute \src "libresoc.v:93440.9-93440.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145005,18 +146158,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:92711.3-92765.6" - process $proc$libresoc.v:92711$3898 + attribute \src "libresoc.v:93494.3-93548.6" + process $proc$libresoc.v:93494$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:92712.5-92712.29" + attribute \src "libresoc.v:93495.5-93495.29" switch \initial - attribute \src "libresoc.v:92712.9-92712.17" + attribute \src "libresoc.v:93495.9-93495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145088,18 +146241,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:92766.3-92820.6" - process $proc$libresoc.v:92766$3899 + attribute \src "libresoc.v:93549.3-93603.6" + process $proc$libresoc.v:93549$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92767.5-92767.29" + attribute \src "libresoc.v:93550.5-93550.29" switch \initial - attribute \src "libresoc.v:92767.9-92767.17" + attribute \src "libresoc.v:93550.9-93550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145171,18 +146324,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:92821.3-92875.6" - process $proc$libresoc.v:92821$3900 + attribute \src "libresoc.v:93604.3-93658.6" + process $proc$libresoc.v:93604$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92822.5-92822.29" + attribute \src "libresoc.v:93605.5-93605.29" switch \initial - attribute \src "libresoc.v:92822.9-92822.17" + attribute \src "libresoc.v:93605.9-93605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145254,18 +146407,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:92876.3-92930.6" - process $proc$libresoc.v:92876$3901 + attribute \src "libresoc.v:93659.3-93713.6" + process $proc$libresoc.v:93659$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92877.5-92877.29" + attribute \src "libresoc.v:93660.5-93660.29" switch \initial - attribute \src "libresoc.v:92877.9-92877.17" + attribute \src "libresoc.v:93660.9-93660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145337,18 +146490,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:92931.3-92985.6" - process $proc$libresoc.v:92931$3902 + attribute \src "libresoc.v:93714.3-93768.6" + process $proc$libresoc.v:93714$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:92932.5-92932.29" + attribute \src "libresoc.v:93715.5-93715.29" switch \initial - attribute \src "libresoc.v:92932.9-92932.17" + attribute \src "libresoc.v:93715.9-93715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145420,18 +146573,101 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:92986.3-93040.6" - process $proc$libresoc.v:92986$3903 + attribute \src "libresoc.v:93769.3-93823.6" + process $proc$libresoc.v:93769$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93770.5-93770.29" + switch \initial + attribute \src "libresoc.v:93770.9-93770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] + end + attribute \src "libresoc.v:93824.3-93878.6" + process $proc$libresoc.v:93824$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:92987.5-92987.29" + attribute \src "libresoc.v:93825.5-93825.29" switch \initial - attribute \src "libresoc.v:92987.9-92987.17" + attribute \src "libresoc.v:93825.9-93825.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145503,18 +146739,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:93041.3-93095.6" - process $proc$libresoc.v:93041$3904 + attribute \src "libresoc.v:93879.3-93933.6" + process $proc$libresoc.v:93879$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93042.5-93042.29" + attribute \src "libresoc.v:93880.5-93880.29" switch \initial - attribute \src "libresoc.v:93042.9-93042.17" + attribute \src "libresoc.v:93880.9-93880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145586,18 +146822,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:93096.3-93150.6" - process $proc$libresoc.v:93096$3905 + attribute \src "libresoc.v:93934.3-93988.6" + process $proc$libresoc.v:93934$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93097.5-93097.29" + attribute \src "libresoc.v:93935.5-93935.29" switch \initial - attribute \src "libresoc.v:93097.9-93097.17" + attribute \src "libresoc.v:93935.9-93935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145669,184 +146905,184 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:93151.3-93205.6" - process $proc$libresoc.v:93151$3906 + attribute \src "libresoc.v:93989.3-94043.6" + process $proc$libresoc.v:93989$3930 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:93152.5-93152.29" + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:93990.5-93990.29" switch \initial - attribute \src "libresoc.v:93152.9-93152.17" + attribute \src "libresoc.v:93990.9-93990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:93206.3-93260.6" - process $proc$libresoc.v:93206$3907 + attribute \src "libresoc.v:94044.3-94098.6" + process $proc$libresoc.v:94044$3931 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93207.5-93207.29" + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:94045.5-94045.29" switch \initial - attribute \src "libresoc.v:93207.9-93207.17" + attribute \src "libresoc.v:94045.9-94045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 end sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:93261.3-93315.6" - process $proc$libresoc.v:93261$3908 + attribute \src "libresoc.v:94099.3-94153.6" + process $proc$libresoc.v:94099$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93262.5-93262.29" + attribute \src "libresoc.v:94100.5-94100.29" switch \initial - attribute \src "libresoc.v:93262.9-93262.17" + attribute \src "libresoc.v:94100.9-94100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145918,18 +147154,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:93316.3-93370.6" - process $proc$libresoc.v:93316$3909 + attribute \src "libresoc.v:94154.3-94208.6" + process $proc$libresoc.v:94154$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93317.5-93317.29" + attribute \src "libresoc.v:94155.5-94155.29" switch \initial - attribute \src "libresoc.v:93317.9-93317.17" + attribute \src "libresoc.v:94155.9-94155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146001,18 +147237,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:93371.3-93425.6" - process $proc$libresoc.v:93371$3910 + attribute \src "libresoc.v:94209.3-94263.6" + process $proc$libresoc.v:94209$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93372.5-93372.29" + attribute \src "libresoc.v:94210.5-94210.29" switch \initial - attribute \src "libresoc.v:93372.9-93372.17" + attribute \src "libresoc.v:94210.9-94210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146084,18 +147320,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:93426.3-93480.6" - process $proc$libresoc.v:93426$3911 + attribute \src "libresoc.v:94264.3-94318.6" + process $proc$libresoc.v:94264$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93427.5-93427.29" + attribute \src "libresoc.v:94265.5-94265.29" switch \initial - attribute \src "libresoc.v:93427.9-93427.17" + attribute \src "libresoc.v:94265.9-94265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146167,18 +147403,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:93481.3-93535.6" - process $proc$libresoc.v:93481$3912 + attribute \src "libresoc.v:94319.3-94373.6" + process $proc$libresoc.v:94319$3936 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93482.5-93482.29" + attribute \src "libresoc.v:94320.5-94320.29" switch \initial - attribute \src "libresoc.v:93482.9-93482.17" + attribute \src "libresoc.v:94320.9-94320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146250,18 +147486,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:93536.3-93590.6" - process $proc$libresoc.v:93536$3913 + attribute \src "libresoc.v:94374.3-94428.6" + process $proc$libresoc.v:94374$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93537.5-93537.29" + attribute \src "libresoc.v:94375.5-94375.29" switch \initial - attribute \src "libresoc.v:93537.9-93537.17" + attribute \src "libresoc.v:94375.9-94375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146333,18 +147569,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:93591.3-93645.6" - process $proc$libresoc.v:93591$3914 + attribute \src "libresoc.v:94429.3-94483.6" + process $proc$libresoc.v:94429$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93592.5-93592.29" + attribute \src "libresoc.v:94430.5-94430.29" switch \initial - attribute \src "libresoc.v:93592.9-93592.17" + attribute \src "libresoc.v:94430.9-94430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146416,18 +147652,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:93646.3-93700.6" - process $proc$libresoc.v:93646$3915 + attribute \src "libresoc.v:94484.3-94538.6" + process $proc$libresoc.v:94484$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93647.5-93647.29" + attribute \src "libresoc.v:94485.5-94485.29" switch \initial - attribute \src "libresoc.v:93647.9-93647.17" + attribute \src "libresoc.v:94485.9-94485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146499,18 +147735,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:93701.3-93755.6" - process $proc$libresoc.v:93701$3916 + attribute \src "libresoc.v:94539.3-94593.6" + process $proc$libresoc.v:94539$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93702.5-93702.29" + attribute \src "libresoc.v:94540.5-94540.29" switch \initial - attribute \src "libresoc.v:93702.9-93702.17" + attribute \src "libresoc.v:94540.9-94540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146582,184 +147818,184 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:93756.3-93810.6" - process $proc$libresoc.v:93756$3917 + attribute \src "libresoc.v:94594.3-94648.6" + process $proc$libresoc.v:94594$3941 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93757.5-93757.29" + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:94595.5-94595.29" switch \initial - attribute \src "libresoc.v:93757.9-93757.17" + attribute \src "libresoc.v:94595.9-94595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub11_form[4:0] 5'00000 end sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:93811.3-93865.6" - process $proc$libresoc.v:93811$3918 + attribute \src "libresoc.v:94649.3-94703.6" + process $proc$libresoc.v:94649$3942 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93812.5-93812.29" + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:94650.5-94650.29" switch \initial - attribute \src "libresoc.v:93812.9-93812.17" + attribute \src "libresoc.v:94650.9-94650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:93866.3-93920.6" - process $proc$libresoc.v:93866$3919 + attribute \src "libresoc.v:94704.3-94758.6" + process $proc$libresoc.v:94704$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93867.5-93867.29" + attribute \src "libresoc.v:94705.5-94705.29" switch \initial - attribute \src "libresoc.v:93867.9-93867.17" + attribute \src "libresoc.v:94705.9-94705.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146831,18 +148067,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:93921.3-93975.6" - process $proc$libresoc.v:93921$3920 + attribute \src "libresoc.v:94759.3-94813.6" + process $proc$libresoc.v:94759$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:93922.5-93922.29" + attribute \src "libresoc.v:94760.5-94760.29" switch \initial - attribute \src "libresoc.v:93922.9-93922.17" + attribute \src "libresoc.v:94760.9-94760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146914,18 +148150,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:93976.3-94030.6" - process $proc$libresoc.v:93976$3921 + attribute \src "libresoc.v:94814.3-94868.6" + process $proc$libresoc.v:94814$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93977.5-93977.29" + attribute \src "libresoc.v:94815.5-94815.29" switch \initial - attribute \src "libresoc.v:93977.9-93977.17" + attribute \src "libresoc.v:94815.9-94815.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146997,18 +148233,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:94031.3-94085.6" - process $proc$libresoc.v:94031$3922 + attribute \src "libresoc.v:94869.3-94923.6" + process $proc$libresoc.v:94869$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94032.5-94032.29" + attribute \src "libresoc.v:94870.5-94870.29" switch \initial - attribute \src "libresoc.v:94032.9-94032.17" + attribute \src "libresoc.v:94870.9-94870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147080,18 +148316,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:94086.3-94140.6" - process $proc$libresoc.v:94086$3923 + attribute \src "libresoc.v:94924.3-94978.6" + process $proc$libresoc.v:94924$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94087.5-94087.29" + attribute \src "libresoc.v:94925.5-94925.29" switch \initial - attribute \src "libresoc.v:94087.9-94087.17" + attribute \src "libresoc.v:94925.9-94925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147163,18 +148399,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:94141.3-94195.6" - process $proc$libresoc.v:94141$3924 + attribute \src "libresoc.v:94979.3-95033.6" + process $proc$libresoc.v:94979$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94142.5-94142.29" + attribute \src "libresoc.v:94980.5-94980.29" switch \initial - attribute \src "libresoc.v:94142.9-94142.17" + attribute \src "libresoc.v:94980.9-94980.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147246,18 +148482,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:94196.3-94250.6" - process $proc$libresoc.v:94196$3925 + attribute \src "libresoc.v:95034.3-95088.6" + process $proc$libresoc.v:95034$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94197.5-94197.29" + attribute \src "libresoc.v:95035.5-95035.29" switch \initial - attribute \src "libresoc.v:94197.9-94197.17" + attribute \src "libresoc.v:95035.9-95035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147329,18 +148565,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:94251.3-94305.6" - process $proc$libresoc.v:94251$3926 + attribute \src "libresoc.v:95089.3-95143.6" + process $proc$libresoc.v:95089$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:94252.5-94252.29" + attribute \src "libresoc.v:95090.5-95090.29" switch \initial - attribute \src "libresoc.v:94252.9-94252.17" + attribute \src "libresoc.v:95090.9-95090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147412,18 +148648,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:94306.3-94360.6" - process $proc$libresoc.v:94306$3927 + attribute \src "libresoc.v:95144.3-95198.6" + process $proc$libresoc.v:95144$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94307.5-94307.29" + attribute \src "libresoc.v:95145.5-95145.29" switch \initial - attribute \src "libresoc.v:94307.9-94307.17" + attribute \src "libresoc.v:95145.9-95145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147497,157 +148733,161 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:94366.1-98002.10" +attribute \src "libresoc.v:95204.1-98953.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:97383.3-97485.6" + attribute \src "libresoc.v:98334.3-98436.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97486.3-97588.6" + attribute \src "libresoc.v:98437.3-98539.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96147.3-96249.6" + attribute \src "libresoc.v:97098.3-97200.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96559.3-96661.6" + attribute \src "libresoc.v:97510.3-97612.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94808.3-94910.6" + attribute \src "libresoc.v:95656.3-95758.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94911.3-95013.6" + attribute \src "libresoc.v:95759.3-95861.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96044.3-96146.6" + attribute \src "libresoc.v:96995.3-97097.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96456.3-96558.6" + attribute \src "libresoc.v:97407.3-97509.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96971.3-97073.6" + attribute \src "libresoc.v:97819.3-97921.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:94705.3-94807.6" + attribute \src "libresoc.v:95553.3-95655.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:97589.3-97691.6" + attribute \src "libresoc.v:98540.3-98642.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97692.3-97794.6" + attribute \src "libresoc.v:98643.3-98745.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97795.3-97897.6" + attribute \src "libresoc.v:98746.3-98848.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95838.3-95940.6" + attribute \src "libresoc.v:96686.3-96788.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96250.3-96352.6" + attribute \src "libresoc.v:97201.3-97303.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96353.3-96455.6" + attribute \src "libresoc.v:97304.3-97406.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96868.3-96970.6" + attribute \src "libresoc.v:97922.3-98024.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:95632.3-95734.6" + attribute \src "libresoc.v:96583.3-96685.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:97177.3-97279.6" + attribute \src "libresoc.v:98128.3-98230.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97898.3-98000.6" + attribute \src "libresoc.v:98849.3-98951.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:95941.3-96043.6" + attribute \src "libresoc.v:96892.3-96994.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96765.3-96867.6" + attribute \src "libresoc.v:97716.3-97818.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97280.3-97382.6" + attribute \src "libresoc.v:98231.3-98333.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97074.3-97176.6" + attribute \src "libresoc.v:98025.3-98127.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:96662.3-96764.6" + attribute \src "libresoc.v:97613.3-97715.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95426.3-95528.6" + attribute \src "libresoc.v:96377.3-96479.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95529.3-95631.6" + attribute \src "libresoc.v:96480.3-96582.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95014.3-95116.6" + attribute \src "libresoc.v:95862.3-95964.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95117.3-95219.6" + attribute \src "libresoc.v:95965.3-96067.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95220.3-95322.6" + attribute \src "libresoc.v:96068.3-96170.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95323.3-95425.6" + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95735.3-95837.6" + attribute \src "libresoc.v:96789.3-96891.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:94367.7-94367.20" + attribute \src "libresoc.v:95205.7-95205.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97383.3-97485.6" + attribute \src "libresoc.v:98334.3-98436.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97486.3-97588.6" + attribute \src "libresoc.v:98437.3-98539.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96147.3-96249.6" + attribute \src "libresoc.v:97098.3-97200.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96559.3-96661.6" + attribute \src "libresoc.v:97510.3-97612.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94808.3-94910.6" + attribute \src "libresoc.v:95656.3-95758.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94911.3-95013.6" + attribute \src "libresoc.v:95759.3-95861.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96044.3-96146.6" + attribute \src "libresoc.v:96995.3-97097.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96456.3-96558.6" + attribute \src "libresoc.v:97407.3-97509.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96971.3-97073.6" + attribute \src "libresoc.v:97819.3-97921.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:94705.3-94807.6" + attribute \src "libresoc.v:95553.3-95655.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:97589.3-97691.6" + attribute \src "libresoc.v:98540.3-98642.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97692.3-97794.6" + attribute \src "libresoc.v:98643.3-98745.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97795.3-97897.6" + attribute \src "libresoc.v:98746.3-98848.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95838.3-95940.6" + attribute \src "libresoc.v:96686.3-96788.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96250.3-96352.6" + attribute \src "libresoc.v:97201.3-97303.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96353.3-96455.6" + attribute \src "libresoc.v:97304.3-97406.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96868.3-96970.6" + attribute \src "libresoc.v:97922.3-98024.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:95632.3-95734.6" + attribute \src "libresoc.v:96583.3-96685.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:97177.3-97279.6" + attribute \src "libresoc.v:98128.3-98230.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97898.3-98000.6" + attribute \src "libresoc.v:98849.3-98951.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:95941.3-96043.6" + attribute \src "libresoc.v:96892.3-96994.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96765.3-96867.6" + attribute \src "libresoc.v:97716.3-97818.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97280.3-97382.6" + attribute \src "libresoc.v:98231.3-98333.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97074.3-97176.6" + attribute \src "libresoc.v:98025.3-98127.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:96662.3-96764.6" + attribute \src "libresoc.v:97613.3-97715.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95426.3-95528.6" + attribute \src "libresoc.v:96377.3-96479.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95529.3-95631.6" + attribute \src "libresoc.v:96480.3-96582.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95014.3-95116.6" + attribute \src "libresoc.v:95862.3-95964.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95117.3-95219.6" + attribute \src "libresoc.v:95965.3-96067.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95220.3-95322.6" + attribute \src "libresoc.v:96068.3-96170.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95323.3-95425.6" + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95735.3-95837.6" + attribute \src "libresoc.v:96789.3-96891.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub15_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub15_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub15_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -147657,7 +148897,7 @@ module \dec31_dec_sub15 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147666,16 +148906,16 @@ module \dec31_dec_sub15 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub15_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -147707,7 +148947,7 @@ module \dec31_dec_sub15 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -147724,7 +148964,7 @@ module \dec31_dec_sub15 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -147732,7 +148972,7 @@ module \dec31_dec_sub15 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147749,13 +148989,13 @@ module \dec31_dec_sub15 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -147832,46 +149072,46 @@ module \dec31_dec_sub15 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub15_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub15_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub15_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub15_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147879,8 +149119,8 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub15_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub15_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147888,8 +149128,8 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub15_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub15_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147897,7 +149137,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub15_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147906,7 +149146,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub15_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147915,7 +149155,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub15_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147924,41 +149164,50 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub15_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub15_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub15_upd - attribute \src "libresoc.v:94367.7-94367.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub15_upd + attribute \src "libresoc.v:95205.7-95205.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:94367.7-94367.20" - process $proc$libresoc.v:94367$3961 + attribute \src "libresoc.v:95205.7-95205.20" + process $proc$libresoc.v:95205$3986 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:94705.3-94807.6" - process $proc$libresoc.v:94705$3929 + attribute \src "libresoc.v:95553.3-95655.6" + process $proc$libresoc.v:95553$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:94706.5-94706.29" + attribute \src "libresoc.v:95554.5-95554.29" switch \initial - attribute \src "libresoc.v:94706.9-94706.17" + attribute \src "libresoc.v:95554.9-95554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148094,18 +149343,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:94808.3-94910.6" - process $proc$libresoc.v:94808$3930 + attribute \src "libresoc.v:95656.3-95758.6" + process $proc$libresoc.v:95656$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94809.5-94809.29" + attribute \src "libresoc.v:95657.5-95657.29" switch \initial - attribute \src "libresoc.v:94809.9-94809.17" + attribute \src "libresoc.v:95657.9-95657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148241,18 +149490,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:94911.3-95013.6" - process $proc$libresoc.v:94911$3931 + attribute \src "libresoc.v:95759.3-95861.6" + process $proc$libresoc.v:95759$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:94912.5-94912.29" + attribute \src "libresoc.v:95760.5-95760.29" switch \initial - attribute \src "libresoc.v:94912.9-94912.17" + attribute \src "libresoc.v:95760.9-95760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148388,18 +149637,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:95014.3-95116.6" - process $proc$libresoc.v:95014$3932 + attribute \src "libresoc.v:95862.3-95964.6" + process $proc$libresoc.v:95862$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95015.5-95015.29" + attribute \src "libresoc.v:95863.5-95863.29" switch \initial - attribute \src "libresoc.v:95015.9-95015.17" + attribute \src "libresoc.v:95863.9-95863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148535,18 +149784,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:95117.3-95219.6" - process $proc$libresoc.v:95117$3933 + attribute \src "libresoc.v:95965.3-96067.6" + process $proc$libresoc.v:95965$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95118.5-95118.29" + attribute \src "libresoc.v:95966.5-95966.29" switch \initial - attribute \src "libresoc.v:95118.9-95118.17" + attribute \src "libresoc.v:95966.9-95966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148682,18 +149931,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:95220.3-95322.6" - process $proc$libresoc.v:95220$3934 + attribute \src "libresoc.v:96068.3-96170.6" + process $proc$libresoc.v:96068$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95221.5-95221.29" + attribute \src "libresoc.v:96069.5-96069.29" switch \initial - attribute \src "libresoc.v:95221.9-95221.17" + attribute \src "libresoc.v:96069.9-96069.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148829,18 +150078,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:95323.3-95425.6" - process $proc$libresoc.v:95323$3935 + attribute \src "libresoc.v:96171.3-96273.6" + process $proc$libresoc.v:96171$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95324.5-95324.29" + attribute \src "libresoc.v:96172.5-96172.29" switch \initial - attribute \src "libresoc.v:95324.9-95324.17" + attribute \src "libresoc.v:96172.9-96172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148976,18 +150225,165 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:95426.3-95528.6" - process $proc$libresoc.v:95426$3936 + attribute \src "libresoc.v:96274.3-96376.6" + process $proc$libresoc.v:96274$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96275.5-96275.29" + switch \initial + attribute \src "libresoc.v:96275.9-96275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] + end + attribute \src "libresoc.v:96377.3-96479.6" + process $proc$libresoc.v:96377$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95427.5-95427.29" + attribute \src "libresoc.v:96378.5-96378.29" switch \initial - attribute \src "libresoc.v:95427.9-95427.17" + attribute \src "libresoc.v:96378.9-96378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149123,18 +150519,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:95529.3-95631.6" - process $proc$libresoc.v:95529$3937 + attribute \src "libresoc.v:96480.3-96582.6" + process $proc$libresoc.v:96480$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95530.5-95530.29" + attribute \src "libresoc.v:96481.5-96481.29" switch \initial - attribute \src "libresoc.v:95530.9-95530.17" + attribute \src "libresoc.v:96481.9-96481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149270,18 +150666,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:95632.3-95734.6" - process $proc$libresoc.v:95632$3938 + attribute \src "libresoc.v:96583.3-96685.6" + process $proc$libresoc.v:96583$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:95633.5-95633.29" + attribute \src "libresoc.v:96584.5-96584.29" switch \initial - attribute \src "libresoc.v:95633.9-95633.17" + attribute \src "libresoc.v:96584.9-96584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149417,312 +150813,312 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:95735.3-95837.6" - process $proc$libresoc.v:95735$3939 + attribute \src "libresoc.v:96686.3-96788.6" + process $proc$libresoc.v:96686$3964 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95736.5-95736.29" + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:96687.5-96687.29" switch \initial - attribute \src "libresoc.v:95736.9-95736.17" + attribute \src "libresoc.v:96687.9-96687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:95838.3-95940.6" - process $proc$libresoc.v:95838$3940 + attribute \src "libresoc.v:96789.3-96891.6" + process $proc$libresoc.v:96789$3965 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:95839.5-95839.29" + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:96790.5-96790.29" switch \initial - attribute \src "libresoc.v:95839.9-95839.17" + attribute \src "libresoc.v:96790.9-96790.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 end sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:95941.3-96043.6" - process $proc$libresoc.v:95941$3941 + attribute \src "libresoc.v:96892.3-96994.6" + process $proc$libresoc.v:96892$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:95942.5-95942.29" + attribute \src "libresoc.v:96893.5-96893.29" switch \initial - attribute \src "libresoc.v:95942.9-95942.17" + attribute \src "libresoc.v:96893.9-96893.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149858,18 +151254,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:96044.3-96146.6" - process $proc$libresoc.v:96044$3942 + attribute \src "libresoc.v:96995.3-97097.6" + process $proc$libresoc.v:96995$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96045.5-96045.29" + attribute \src "libresoc.v:96996.5-96996.29" switch \initial - attribute \src "libresoc.v:96045.9-96045.17" + attribute \src "libresoc.v:96996.9-96996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150005,18 +151401,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:96147.3-96249.6" - process $proc$libresoc.v:96147$3943 + attribute \src "libresoc.v:97098.3-97200.6" + process $proc$libresoc.v:97098$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96148.5-96148.29" + attribute \src "libresoc.v:97099.5-97099.29" switch \initial - attribute \src "libresoc.v:96148.9-96148.17" + attribute \src "libresoc.v:97099.9-97099.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150152,18 +151548,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:96250.3-96352.6" - process $proc$libresoc.v:96250$3944 + attribute \src "libresoc.v:97201.3-97303.6" + process $proc$libresoc.v:97201$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96251.5-96251.29" + attribute \src "libresoc.v:97202.5-97202.29" switch \initial - attribute \src "libresoc.v:96251.9-96251.17" + attribute \src "libresoc.v:97202.9-97202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150299,18 +151695,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:96353.3-96455.6" - process $proc$libresoc.v:96353$3945 + attribute \src "libresoc.v:97304.3-97406.6" + process $proc$libresoc.v:97304$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96354.5-96354.29" + attribute \src "libresoc.v:97305.5-97305.29" switch \initial - attribute \src "libresoc.v:96354.9-96354.17" + attribute \src "libresoc.v:97305.9-97305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150446,18 +151842,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:96456.3-96558.6" - process $proc$libresoc.v:96456$3946 + attribute \src "libresoc.v:97407.3-97509.6" + process $proc$libresoc.v:97407$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96457.5-96457.29" + attribute \src "libresoc.v:97408.5-97408.29" switch \initial - attribute \src "libresoc.v:96457.9-96457.17" + attribute \src "libresoc.v:97408.9-97408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150593,18 +151989,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:96559.3-96661.6" - process $proc$libresoc.v:96559$3947 + attribute \src "libresoc.v:97510.3-97612.6" + process $proc$libresoc.v:97510$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:96560.5-96560.29" + attribute \src "libresoc.v:97511.5-97511.29" switch \initial - attribute \src "libresoc.v:96560.9-96560.17" + attribute \src "libresoc.v:97511.9-97511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150740,18 +152136,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:96662.3-96764.6" - process $proc$libresoc.v:96662$3948 + attribute \src "libresoc.v:97613.3-97715.6" + process $proc$libresoc.v:97613$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96663.5-96663.29" + attribute \src "libresoc.v:97614.5-97614.29" switch \initial - attribute \src "libresoc.v:96663.9-96663.17" + attribute \src "libresoc.v:97614.9-97614.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150887,18 +152283,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:96765.3-96867.6" - process $proc$libresoc.v:96765$3949 + attribute \src "libresoc.v:97716.3-97818.6" + process $proc$libresoc.v:97716$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:96766.5-96766.29" + attribute \src "libresoc.v:97717.5-97717.29" switch \initial - attribute \src "libresoc.v:96766.9-96766.17" + attribute \src "libresoc.v:97717.9-97717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151034,312 +152430,312 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:96868.3-96970.6" - process $proc$libresoc.v:96868$3950 + attribute \src "libresoc.v:97819.3-97921.6" + process $proc$libresoc.v:97819$3975 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96869.5-96869.29" + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:97820.5-97820.29" switch \initial - attribute \src "libresoc.v:96869.9-96869.17" + attribute \src "libresoc.v:97820.9-97820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'00000 end sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:96971.3-97073.6" - process $proc$libresoc.v:96971$3951 + attribute \src "libresoc.v:97922.3-98024.6" + process $proc$libresoc.v:97922$3976 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:96972.5-96972.29" + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:97923.5-97923.29" switch \initial - attribute \src "libresoc.v:96972.9-96972.17" + attribute \src "libresoc.v:97923.9-97923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:97074.3-97176.6" - process $proc$libresoc.v:97074$3952 + attribute \src "libresoc.v:98025.3-98127.6" + process $proc$libresoc.v:98025$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97075.5-97075.29" + attribute \src "libresoc.v:98026.5-98026.29" switch \initial - attribute \src "libresoc.v:97075.9-97075.17" + attribute \src "libresoc.v:98026.9-98026.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151475,18 +152871,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:97177.3-97279.6" - process $proc$libresoc.v:97177$3953 + attribute \src "libresoc.v:98128.3-98230.6" + process $proc$libresoc.v:98128$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97178.5-97178.29" + attribute \src "libresoc.v:98129.5-98129.29" switch \initial - attribute \src "libresoc.v:97178.9-97178.17" + attribute \src "libresoc.v:98129.9-98129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151622,18 +153018,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:97280.3-97382.6" - process $proc$libresoc.v:97280$3954 + attribute \src "libresoc.v:98231.3-98333.6" + process $proc$libresoc.v:98231$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97281.5-97281.29" + attribute \src "libresoc.v:98232.5-98232.29" switch \initial - attribute \src "libresoc.v:97281.9-97281.17" + attribute \src "libresoc.v:98232.9-98232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151769,18 +153165,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:97383.3-97485.6" - process $proc$libresoc.v:97383$3955 + attribute \src "libresoc.v:98334.3-98436.6" + process $proc$libresoc.v:98334$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97384.5-97384.29" + attribute \src "libresoc.v:98335.5-98335.29" switch \initial - attribute \src "libresoc.v:97384.9-97384.17" + attribute \src "libresoc.v:98335.9-98335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151916,18 +153312,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:97486.3-97588.6" - process $proc$libresoc.v:97486$3956 + attribute \src "libresoc.v:98437.3-98539.6" + process $proc$libresoc.v:98437$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97487.5-97487.29" + attribute \src "libresoc.v:98438.5-98438.29" switch \initial - attribute \src "libresoc.v:97487.9-97487.17" + attribute \src "libresoc.v:98438.9-98438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152063,18 +153459,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:97589.3-97691.6" - process $proc$libresoc.v:97589$3957 + attribute \src "libresoc.v:98540.3-98642.6" + process $proc$libresoc.v:98540$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97590.5-97590.29" + attribute \src "libresoc.v:98541.5-98541.29" switch \initial - attribute \src "libresoc.v:97590.9-97590.17" + attribute \src "libresoc.v:98541.9-98541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152210,18 +153606,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:97692.3-97794.6" - process $proc$libresoc.v:97692$3958 + attribute \src "libresoc.v:98643.3-98745.6" + process $proc$libresoc.v:98643$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97693.5-97693.29" + attribute \src "libresoc.v:98644.5-98644.29" switch \initial - attribute \src "libresoc.v:97693.9-97693.17" + attribute \src "libresoc.v:98644.9-98644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152357,18 +153753,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:97795.3-97897.6" - process $proc$libresoc.v:97795$3959 + attribute \src "libresoc.v:98746.3-98848.6" + process $proc$libresoc.v:98746$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:97796.5-97796.29" + attribute \src "libresoc.v:98747.5-98747.29" switch \initial - attribute \src "libresoc.v:97796.9-97796.17" + attribute \src "libresoc.v:98747.9-98747.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152504,18 +153900,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:97898.3-98000.6" - process $proc$libresoc.v:97898$3960 + attribute \src "libresoc.v:98849.3-98951.6" + process $proc$libresoc.v:98849$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:97899.5-97899.29" + attribute \src "libresoc.v:98850.5-98850.29" switch \initial - attribute \src "libresoc.v:97899.9-97899.17" + attribute \src "libresoc.v:98850.9-98850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152653,157 +154049,161 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98006.1-98666.10" +attribute \src "libresoc.v:98957.1-99637.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:98605.3-98614.6" + attribute \src "libresoc.v:99576.3-99585.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98615.3-98624.6" + attribute \src "libresoc.v:99586.3-99595.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98485.3-98494.6" + attribute \src "libresoc.v:99456.3-99465.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98525.3-98534.6" + attribute \src "libresoc.v:99496.3-99505.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98355.3-98364.6" + attribute \src "libresoc.v:99316.3-99325.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98365.3-98374.6" + attribute \src "libresoc.v:99326.3-99335.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98475.3-98484.6" + attribute \src "libresoc.v:99446.3-99455.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98515.3-98524.6" + attribute \src "libresoc.v:99486.3-99495.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98565.3-98574.6" + attribute \src "libresoc.v:99526.3-99535.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98345.3-98354.6" + attribute \src "libresoc.v:99306.3-99315.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98625.3-98634.6" + attribute \src "libresoc.v:99596.3-99605.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98635.3-98644.6" + attribute \src "libresoc.v:99606.3-99615.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98645.3-98654.6" + attribute \src "libresoc.v:99616.3-99625.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98455.3-98464.6" + attribute \src "libresoc.v:99416.3-99425.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98495.3-98504.6" + attribute \src "libresoc.v:99466.3-99475.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98505.3-98514.6" + attribute \src "libresoc.v:99476.3-99485.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98555.3-98564.6" + attribute \src "libresoc.v:99536.3-99545.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98435.3-98444.6" + attribute \src "libresoc.v:99406.3-99415.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98585.3-98594.6" + attribute \src "libresoc.v:99556.3-99565.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98655.3-98664.6" + attribute \src "libresoc.v:99626.3-99635.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98465.3-98474.6" + attribute \src "libresoc.v:99436.3-99445.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98545.3-98554.6" + attribute \src "libresoc.v:99516.3-99525.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98595.3-98604.6" + attribute \src "libresoc.v:99566.3-99575.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98575.3-98584.6" + attribute \src "libresoc.v:99546.3-99555.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98535.3-98544.6" + attribute \src "libresoc.v:99506.3-99515.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98415.3-98424.6" + attribute \src "libresoc.v:99386.3-99395.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98425.3-98434.6" + attribute \src "libresoc.v:99396.3-99405.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98375.3-98384.6" + attribute \src "libresoc.v:99336.3-99345.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98385.3-98394.6" + attribute \src "libresoc.v:99346.3-99355.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98395.3-98404.6" + attribute \src "libresoc.v:99356.3-99365.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98405.3-98414.6" + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98445.3-98454.6" + attribute \src "libresoc.v:99426.3-99435.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98007.7-98007.20" + attribute \src "libresoc.v:98958.7-98958.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98605.3-98614.6" + attribute \src "libresoc.v:99576.3-99585.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98615.3-98624.6" + attribute \src "libresoc.v:99586.3-99595.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98485.3-98494.6" + attribute \src "libresoc.v:99456.3-99465.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98525.3-98534.6" + attribute \src "libresoc.v:99496.3-99505.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98355.3-98364.6" + attribute \src "libresoc.v:99316.3-99325.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98365.3-98374.6" + attribute \src "libresoc.v:99326.3-99335.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98475.3-98484.6" + attribute \src "libresoc.v:99446.3-99455.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98515.3-98524.6" + attribute \src "libresoc.v:99486.3-99495.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98565.3-98574.6" + attribute \src "libresoc.v:99526.3-99535.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98345.3-98354.6" + attribute \src "libresoc.v:99306.3-99315.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98625.3-98634.6" + attribute \src "libresoc.v:99596.3-99605.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98635.3-98644.6" + attribute \src "libresoc.v:99606.3-99615.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98645.3-98654.6" + attribute \src "libresoc.v:99616.3-99625.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98455.3-98464.6" + attribute \src "libresoc.v:99416.3-99425.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98495.3-98504.6" + attribute \src "libresoc.v:99466.3-99475.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98505.3-98514.6" + attribute \src "libresoc.v:99476.3-99485.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98555.3-98564.6" + attribute \src "libresoc.v:99536.3-99545.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98435.3-98444.6" + attribute \src "libresoc.v:99406.3-99415.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98585.3-98594.6" + attribute \src "libresoc.v:99556.3-99565.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98655.3-98664.6" + attribute \src "libresoc.v:99626.3-99635.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98465.3-98474.6" + attribute \src "libresoc.v:99436.3-99445.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98545.3-98554.6" + attribute \src "libresoc.v:99516.3-99525.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98595.3-98604.6" + attribute \src "libresoc.v:99566.3-99575.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98575.3-98584.6" + attribute \src "libresoc.v:99546.3-99555.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98535.3-98544.6" + attribute \src "libresoc.v:99506.3-99515.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98415.3-98424.6" + attribute \src "libresoc.v:99386.3-99395.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98425.3-98434.6" + attribute \src "libresoc.v:99396.3-99405.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98375.3-98384.6" + attribute \src "libresoc.v:99336.3-99345.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98385.3-98394.6" + attribute \src "libresoc.v:99346.3-99355.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98395.3-98404.6" + attribute \src "libresoc.v:99356.3-99365.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98405.3-98414.6" + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98445.3-98454.6" + attribute \src "libresoc.v:99426.3-99435.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub16_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub16_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub16_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -152813,7 +154213,7 @@ module \dec31_dec_sub16 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -152822,16 +154222,16 @@ module \dec31_dec_sub16 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub16_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -152863,7 +154263,7 @@ module \dec31_dec_sub16 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -152880,7 +154280,7 @@ module \dec31_dec_sub16 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -152888,7 +154288,7 @@ module \dec31_dec_sub16 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -152905,13 +154305,13 @@ module \dec31_dec_sub16 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -152988,46 +154388,46 @@ module \dec31_dec_sub16 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub16_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub16_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub16_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub16_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153035,8 +154435,8 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub16_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub16_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153044,8 +154444,8 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub16_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub16_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153053,7 +154453,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub16_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153062,7 +154462,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub16_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153071,7 +154471,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub16_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153080,41 +154480,50 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub16_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub16_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub16_upd - attribute \src "libresoc.v:98007.7-98007.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub16_upd + attribute \src "libresoc.v:98958.7-98958.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98007.7-98007.20" - process $proc$libresoc.v:98007$3994 + attribute \src "libresoc.v:98958.7-98958.20" + process $proc$libresoc.v:98958$4020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:98345.3-98354.6" - process $proc$libresoc.v:98345$3962 + attribute \src "libresoc.v:99306.3-99315.6" + process $proc$libresoc.v:99306$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98346.5-98346.29" + attribute \src "libresoc.v:99307.5-99307.29" switch \initial - attribute \src "libresoc.v:98346.9-98346.17" + attribute \src "libresoc.v:99307.9-99307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153126,18 +154535,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:98355.3-98364.6" - process $proc$libresoc.v:98355$3963 + attribute \src "libresoc.v:99316.3-99325.6" + process $proc$libresoc.v:99316$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98356.5-98356.29" + attribute \src "libresoc.v:99317.5-99317.29" switch \initial - attribute \src "libresoc.v:98356.9-98356.17" + attribute \src "libresoc.v:99317.9-99317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153149,18 +154558,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:98365.3-98374.6" - process $proc$libresoc.v:98365$3964 + attribute \src "libresoc.v:99326.3-99335.6" + process $proc$libresoc.v:99326$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98366.5-98366.29" + attribute \src "libresoc.v:99327.5-99327.29" switch \initial - attribute \src "libresoc.v:98366.9-98366.17" + attribute \src "libresoc.v:99327.9-99327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153172,18 +154581,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:98375.3-98384.6" - process $proc$libresoc.v:98375$3965 + attribute \src "libresoc.v:99336.3-99345.6" + process $proc$libresoc.v:99336$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98376.5-98376.29" + attribute \src "libresoc.v:99337.5-99337.29" switch \initial - attribute \src "libresoc.v:98376.9-98376.17" + attribute \src "libresoc.v:99337.9-99337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153195,18 +154604,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:98385.3-98394.6" - process $proc$libresoc.v:98385$3966 + attribute \src "libresoc.v:99346.3-99355.6" + process $proc$libresoc.v:99346$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98386.5-98386.29" + attribute \src "libresoc.v:99347.5-99347.29" switch \initial - attribute \src "libresoc.v:98386.9-98386.17" + attribute \src "libresoc.v:99347.9-99347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153218,18 +154627,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:98395.3-98404.6" - process $proc$libresoc.v:98395$3967 + attribute \src "libresoc.v:99356.3-99365.6" + process $proc$libresoc.v:99356$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98396.5-98396.29" + attribute \src "libresoc.v:99357.5-99357.29" switch \initial - attribute \src "libresoc.v:98396.9-98396.17" + attribute \src "libresoc.v:99357.9-99357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153241,18 +154650,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:98405.3-98414.6" - process $proc$libresoc.v:98405$3968 + attribute \src "libresoc.v:99366.3-99375.6" + process $proc$libresoc.v:99366$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98406.5-98406.29" + attribute \src "libresoc.v:99367.5-99367.29" switch \initial - attribute \src "libresoc.v:98406.9-98406.17" + attribute \src "libresoc.v:99367.9-99367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153264,18 +154673,41 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:98415.3-98424.6" - process $proc$libresoc.v:98415$3969 + attribute \src "libresoc.v:99376.3-99385.6" + process $proc$libresoc.v:99376$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99377.5-99377.29" + switch \initial + attribute \src "libresoc.v:99377.9-99377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] + end + attribute \src "libresoc.v:99386.3-99395.6" + process $proc$libresoc.v:99386$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98416.5-98416.29" + attribute \src "libresoc.v:99387.5-99387.29" switch \initial - attribute \src "libresoc.v:98416.9-98416.17" + attribute \src "libresoc.v:99387.9-99387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153287,18 +154719,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:98425.3-98434.6" - process $proc$libresoc.v:98425$3970 + attribute \src "libresoc.v:99396.3-99405.6" + process $proc$libresoc.v:99396$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98426.5-98426.29" + attribute \src "libresoc.v:99397.5-99397.29" switch \initial - attribute \src "libresoc.v:98426.9-98426.17" + attribute \src "libresoc.v:99397.9-99397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153310,18 +154742,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:98435.3-98444.6" - process $proc$libresoc.v:98435$3971 + attribute \src "libresoc.v:99406.3-99415.6" + process $proc$libresoc.v:99406$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98436.5-98436.29" + attribute \src "libresoc.v:99407.5-99407.29" switch \initial - attribute \src "libresoc.v:98436.9-98436.17" + attribute \src "libresoc.v:99407.9-99407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153333,64 +154765,64 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:98445.3-98454.6" - process $proc$libresoc.v:98445$3972 + attribute \src "libresoc.v:99416.3-99425.6" + process $proc$libresoc.v:99416$3998 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98446.5-98446.29" + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:99417.5-99417.29" switch \initial - attribute \src "libresoc.v:98446.9-98446.17" + attribute \src "libresoc.v:99417.9-99417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:98455.3-98464.6" - process $proc$libresoc.v:98455$3973 + attribute \src "libresoc.v:99426.3-99435.6" + process $proc$libresoc.v:99426$3999 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98456.5-98456.29" + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:99427.5-99427.29" switch \initial - attribute \src "libresoc.v:98456.9-98456.17" + attribute \src "libresoc.v:99427.9-99427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 end sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:98465.3-98474.6" - process $proc$libresoc.v:98465$3974 + attribute \src "libresoc.v:99436.3-99445.6" + process $proc$libresoc.v:99436$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98466.5-98466.29" + attribute \src "libresoc.v:99437.5-99437.29" switch \initial - attribute \src "libresoc.v:98466.9-98466.17" + attribute \src "libresoc.v:99437.9-99437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153402,18 +154834,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:98475.3-98484.6" - process $proc$libresoc.v:98475$3975 + attribute \src "libresoc.v:99446.3-99455.6" + process $proc$libresoc.v:99446$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98476.5-98476.29" + attribute \src "libresoc.v:99447.5-99447.29" switch \initial - attribute \src "libresoc.v:98476.9-98476.17" + attribute \src "libresoc.v:99447.9-99447.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153425,18 +154857,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:98485.3-98494.6" - process $proc$libresoc.v:98485$3976 + attribute \src "libresoc.v:99456.3-99465.6" + process $proc$libresoc.v:99456$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98486.5-98486.29" + attribute \src "libresoc.v:99457.5-99457.29" switch \initial - attribute \src "libresoc.v:98486.9-98486.17" + attribute \src "libresoc.v:99457.9-99457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153448,18 +154880,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:98495.3-98504.6" - process $proc$libresoc.v:98495$3977 + attribute \src "libresoc.v:99466.3-99475.6" + process $proc$libresoc.v:99466$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98496.5-98496.29" + attribute \src "libresoc.v:99467.5-99467.29" switch \initial - attribute \src "libresoc.v:98496.9-98496.17" + attribute \src "libresoc.v:99467.9-99467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153471,18 +154903,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:98505.3-98514.6" - process $proc$libresoc.v:98505$3978 + attribute \src "libresoc.v:99476.3-99485.6" + process $proc$libresoc.v:99476$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98506.5-98506.29" + attribute \src "libresoc.v:99477.5-99477.29" switch \initial - attribute \src "libresoc.v:98506.9-98506.17" + attribute \src "libresoc.v:99477.9-99477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153494,18 +154926,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:98515.3-98524.6" - process $proc$libresoc.v:98515$3979 + attribute \src "libresoc.v:99486.3-99495.6" + process $proc$libresoc.v:99486$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98516.5-98516.29" + attribute \src "libresoc.v:99487.5-99487.29" switch \initial - attribute \src "libresoc.v:98516.9-98516.17" + attribute \src "libresoc.v:99487.9-99487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153517,18 +154949,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:98525.3-98534.6" - process $proc$libresoc.v:98525$3980 + attribute \src "libresoc.v:99496.3-99505.6" + process $proc$libresoc.v:99496$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98526.5-98526.29" + attribute \src "libresoc.v:99497.5-99497.29" switch \initial - attribute \src "libresoc.v:98526.9-98526.17" + attribute \src "libresoc.v:99497.9-99497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153540,18 +154972,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:98535.3-98544.6" - process $proc$libresoc.v:98535$3981 + attribute \src "libresoc.v:99506.3-99515.6" + process $proc$libresoc.v:99506$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98536.5-98536.29" + attribute \src "libresoc.v:99507.5-99507.29" switch \initial - attribute \src "libresoc.v:98536.9-98536.17" + attribute \src "libresoc.v:99507.9-99507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153563,18 +154995,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:98545.3-98554.6" - process $proc$libresoc.v:98545$3982 + attribute \src "libresoc.v:99516.3-99525.6" + process $proc$libresoc.v:99516$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98546.5-98546.29" + attribute \src "libresoc.v:99517.5-99517.29" switch \initial - attribute \src "libresoc.v:98546.9-98546.17" + attribute \src "libresoc.v:99517.9-99517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153586,64 +155018,64 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:98555.3-98564.6" - process $proc$libresoc.v:98555$3983 + attribute \src "libresoc.v:99526.3-99535.6" + process $proc$libresoc.v:99526$4009 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98556.5-98556.29" + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:99527.5-99527.29" switch \initial - attribute \src "libresoc.v:98556.9-98556.17" + attribute \src "libresoc.v:99527.9-99527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_form[4:0] 5'01010 case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_form[4:0] 5'00000 end sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:98565.3-98574.6" - process $proc$libresoc.v:98565$3984 + attribute \src "libresoc.v:99536.3-99545.6" + process $proc$libresoc.v:99536$4010 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98566.5-98566.29" + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:99537.5-99537.29" switch \initial - attribute \src "libresoc.v:98566.9-98566.17" + attribute \src "libresoc.v:99537.9-99537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:98575.3-98584.6" - process $proc$libresoc.v:98575$3985 + attribute \src "libresoc.v:99546.3-99555.6" + process $proc$libresoc.v:99546$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98576.5-98576.29" + attribute \src "libresoc.v:99547.5-99547.29" switch \initial - attribute \src "libresoc.v:98576.9-98576.17" + attribute \src "libresoc.v:99547.9-99547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153655,18 +155087,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:98585.3-98594.6" - process $proc$libresoc.v:98585$3986 + attribute \src "libresoc.v:99556.3-99565.6" + process $proc$libresoc.v:99556$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98586.5-98586.29" + attribute \src "libresoc.v:99557.5-99557.29" switch \initial - attribute \src "libresoc.v:98586.9-98586.17" + attribute \src "libresoc.v:99557.9-99557.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153678,18 +155110,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:98595.3-98604.6" - process $proc$libresoc.v:98595$3987 + attribute \src "libresoc.v:99566.3-99575.6" + process $proc$libresoc.v:99566$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98596.5-98596.29" + attribute \src "libresoc.v:99567.5-99567.29" switch \initial - attribute \src "libresoc.v:98596.9-98596.17" + attribute \src "libresoc.v:99567.9-99567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153701,18 +155133,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:98605.3-98614.6" - process $proc$libresoc.v:98605$3988 + attribute \src "libresoc.v:99576.3-99585.6" + process $proc$libresoc.v:99576$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98606.5-98606.29" + attribute \src "libresoc.v:99577.5-99577.29" switch \initial - attribute \src "libresoc.v:98606.9-98606.17" + attribute \src "libresoc.v:99577.9-99577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153724,18 +155156,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:98615.3-98624.6" - process $proc$libresoc.v:98615$3989 + attribute \src "libresoc.v:99586.3-99595.6" + process $proc$libresoc.v:99586$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98616.5-98616.29" + attribute \src "libresoc.v:99587.5-99587.29" switch \initial - attribute \src "libresoc.v:98616.9-98616.17" + attribute \src "libresoc.v:99587.9-99587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153747,18 +155179,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:98625.3-98634.6" - process $proc$libresoc.v:98625$3990 + attribute \src "libresoc.v:99596.3-99605.6" + process $proc$libresoc.v:99596$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98626.5-98626.29" + attribute \src "libresoc.v:99597.5-99597.29" switch \initial - attribute \src "libresoc.v:98626.9-98626.17" + attribute \src "libresoc.v:99597.9-99597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153770,18 +155202,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:98635.3-98644.6" - process $proc$libresoc.v:98635$3991 + attribute \src "libresoc.v:99606.3-99615.6" + process $proc$libresoc.v:99606$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98636.5-98636.29" + attribute \src "libresoc.v:99607.5-99607.29" switch \initial - attribute \src "libresoc.v:98636.9-98636.17" + attribute \src "libresoc.v:99607.9-99607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153793,18 +155225,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:98645.3-98654.6" - process $proc$libresoc.v:98645$3992 + attribute \src "libresoc.v:99616.3-99625.6" + process $proc$libresoc.v:99616$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98646.5-98646.29" + attribute \src "libresoc.v:99617.5-99617.29" switch \initial - attribute \src "libresoc.v:98646.9-98646.17" + attribute \src "libresoc.v:99617.9-99617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153816,18 +155248,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:98655.3-98664.6" - process $proc$libresoc.v:98655$3993 + attribute \src "libresoc.v:99626.3-99635.6" + process $proc$libresoc.v:99626$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98656.5-98656.29" + attribute \src "libresoc.v:99627.5-99627.29" switch \initial - attribute \src "libresoc.v:98656.9-98656.17" + attribute \src "libresoc.v:99627.9-99627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153841,157 +155273,161 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98670.1-99714.10" +attribute \src "libresoc.v:99641.1-100717.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:99581.3-99602.6" + attribute \src "libresoc.v:100584.3-100605.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99603.3-99624.6" + attribute \src "libresoc.v:100606.3-100627.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99317.3-99338.6" + attribute \src "libresoc.v:100320.3-100341.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99426.6" + attribute \src "libresoc.v:100408.3-100429.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99031.3-99052.6" + attribute \src "libresoc.v:100012.3-100033.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99053.3-99074.6" + attribute \src "libresoc.v:100034.3-100055.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99295.3-99316.6" + attribute \src "libresoc.v:100298.3-100319.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99383.3-99404.6" + attribute \src "libresoc.v:100386.3-100407.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99493.3-99514.6" + attribute \src "libresoc.v:100474.3-100495.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99009.3-99030.6" + attribute \src "libresoc.v:99990.3-100011.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99625.3-99646.6" + attribute \src "libresoc.v:100628.3-100649.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99647.3-99668.6" + attribute \src "libresoc.v:100650.3-100671.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99669.3-99690.6" + attribute \src "libresoc.v:100672.3-100693.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99251.3-99272.6" + attribute \src "libresoc.v:100232.3-100253.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99339.3-99360.6" + attribute \src "libresoc.v:100342.3-100363.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99361.3-99382.6" + attribute \src "libresoc.v:100364.3-100385.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99471.3-99492.6" + attribute \src "libresoc.v:100496.3-100517.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99207.3-99228.6" + attribute \src "libresoc.v:100210.3-100231.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99537.3-99558.6" + attribute \src "libresoc.v:100540.3-100561.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99691.3-99712.6" + attribute \src "libresoc.v:100694.3-100715.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99273.3-99294.6" + attribute \src "libresoc.v:100276.3-100297.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99449.3-99470.6" + attribute \src "libresoc.v:100452.3-100473.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99559.3-99580.6" + attribute \src "libresoc.v:100562.3-100583.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99515.3-99536.6" + attribute \src "libresoc.v:100518.3-100539.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99427.3-99448.6" + attribute \src "libresoc.v:100430.3-100451.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99163.3-99184.6" + attribute \src "libresoc.v:100166.3-100187.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99185.3-99206.6" + attribute \src "libresoc.v:100188.3-100209.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99075.3-99096.6" + attribute \src "libresoc.v:100056.3-100077.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99097.3-99118.6" + attribute \src "libresoc.v:100078.3-100099.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99119.3-99140.6" + attribute \src "libresoc.v:100100.3-100121.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99141.3-99162.6" + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99229.3-99250.6" + attribute \src "libresoc.v:100254.3-100275.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:98671.7-98671.20" + attribute \src "libresoc.v:99642.7-99642.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99581.3-99602.6" + attribute \src "libresoc.v:100584.3-100605.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99603.3-99624.6" + attribute \src "libresoc.v:100606.3-100627.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99317.3-99338.6" + attribute \src "libresoc.v:100320.3-100341.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99426.6" + attribute \src "libresoc.v:100408.3-100429.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99031.3-99052.6" + attribute \src "libresoc.v:100012.3-100033.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99053.3-99074.6" + attribute \src "libresoc.v:100034.3-100055.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99295.3-99316.6" + attribute \src "libresoc.v:100298.3-100319.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99383.3-99404.6" + attribute \src "libresoc.v:100386.3-100407.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99493.3-99514.6" + attribute \src "libresoc.v:100474.3-100495.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99009.3-99030.6" + attribute \src "libresoc.v:99990.3-100011.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99625.3-99646.6" + attribute \src "libresoc.v:100628.3-100649.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99647.3-99668.6" + attribute \src "libresoc.v:100650.3-100671.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99669.3-99690.6" + attribute \src "libresoc.v:100672.3-100693.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99251.3-99272.6" + attribute \src "libresoc.v:100232.3-100253.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99339.3-99360.6" + attribute \src "libresoc.v:100342.3-100363.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99361.3-99382.6" + attribute \src "libresoc.v:100364.3-100385.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99471.3-99492.6" + attribute \src "libresoc.v:100496.3-100517.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99207.3-99228.6" + attribute \src "libresoc.v:100210.3-100231.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99537.3-99558.6" + attribute \src "libresoc.v:100540.3-100561.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99691.3-99712.6" + attribute \src "libresoc.v:100694.3-100715.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99273.3-99294.6" + attribute \src "libresoc.v:100276.3-100297.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99449.3-99470.6" + attribute \src "libresoc.v:100452.3-100473.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99559.3-99580.6" + attribute \src "libresoc.v:100562.3-100583.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99515.3-99536.6" + attribute \src "libresoc.v:100518.3-100539.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99427.3-99448.6" + attribute \src "libresoc.v:100430.3-100451.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99163.3-99184.6" + attribute \src "libresoc.v:100166.3-100187.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99185.3-99206.6" + attribute \src "libresoc.v:100188.3-100209.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99075.3-99096.6" + attribute \src "libresoc.v:100056.3-100077.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99097.3-99118.6" + attribute \src "libresoc.v:100078.3-100099.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99119.3-99140.6" + attribute \src "libresoc.v:100100.3-100121.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99141.3-99162.6" + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99229.3-99250.6" + attribute \src "libresoc.v:100254.3-100275.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub18_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub18_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub18_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -154001,7 +155437,7 @@ module \dec31_dec_sub18 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -154010,16 +155446,16 @@ module \dec31_dec_sub18 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub18_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -154051,7 +155487,7 @@ module \dec31_dec_sub18 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -154068,7 +155504,7 @@ module \dec31_dec_sub18 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -154076,7 +155512,7 @@ module \dec31_dec_sub18 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -154093,13 +155529,13 @@ module \dec31_dec_sub18 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -154176,46 +155612,46 @@ module \dec31_dec_sub18 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub18_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub18_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub18_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154223,8 +155659,8 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub18_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub18_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154232,8 +155668,8 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub18_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub18_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154241,7 +155677,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub18_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154250,7 +155686,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub18_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154259,7 +155695,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub18_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154268,80 +155704,42 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub18_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub18_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub18_upd - attribute \src "libresoc.v:98671.7-98671.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub18_upd + attribute \src "libresoc.v:99642.7-99642.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98671.7-98671.20" - process $proc$libresoc.v:98671$4027 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99009.3-99030.6" - process $proc$libresoc.v:99009$3995 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99010.5-99010.29" - switch \initial - attribute \src "libresoc.v:99010.9-99010.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - case - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] - end - attribute \src "libresoc.v:99031.3-99052.6" - process $proc$libresoc.v:99031$3996 + attribute \src "libresoc.v:100012.3-100033.6" + process $proc$libresoc.v:100012$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99032.5-99032.29" + attribute \src "libresoc.v:100013.5-100013.29" switch \initial - attribute \src "libresoc.v:99032.9-99032.17" + attribute \src "libresoc.v:100013.9-100013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154369,18 +155767,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:99053.3-99074.6" - process $proc$libresoc.v:99053$3997 + attribute \src "libresoc.v:100034.3-100055.6" + process $proc$libresoc.v:100034$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99054.5-99054.29" + attribute \src "libresoc.v:100035.5-100035.29" switch \initial - attribute \src "libresoc.v:99054.9-99054.17" + attribute \src "libresoc.v:100035.9-100035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154408,18 +155806,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:99075.3-99096.6" - process $proc$libresoc.v:99075$3998 + attribute \src "libresoc.v:100056.3-100077.6" + process $proc$libresoc.v:100056$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99076.5-99076.29" + attribute \src "libresoc.v:100057.5-100057.29" switch \initial - attribute \src "libresoc.v:99076.9-99076.17" + attribute \src "libresoc.v:100057.9-100057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154447,18 +155845,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:99097.3-99118.6" - process $proc$libresoc.v:99097$3999 + attribute \src "libresoc.v:100078.3-100099.6" + process $proc$libresoc.v:100078$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99098.5-99098.29" + attribute \src "libresoc.v:100079.5-100079.29" switch \initial - attribute \src "libresoc.v:99098.9-99098.17" + attribute \src "libresoc.v:100079.9-100079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154486,18 +155884,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:99119.3-99140.6" - process $proc$libresoc.v:99119$4000 + attribute \src "libresoc.v:100100.3-100121.6" + process $proc$libresoc.v:100100$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99120.5-99120.29" + attribute \src "libresoc.v:100101.5-100101.29" switch \initial - attribute \src "libresoc.v:99120.9-99120.17" + attribute \src "libresoc.v:100101.9-100101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154525,18 +155923,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:99141.3-99162.6" - process $proc$libresoc.v:99141$4001 + attribute \src "libresoc.v:100122.3-100143.6" + process $proc$libresoc.v:100122$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99142.5-99142.29" + attribute \src "libresoc.v:100123.5-100123.29" switch \initial - attribute \src "libresoc.v:99142.9-99142.17" + attribute \src "libresoc.v:100123.9-100123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154564,18 +155962,57 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:99163.3-99184.6" - process $proc$libresoc.v:99163$4002 + attribute \src "libresoc.v:100144.3-100165.6" + process $proc$libresoc.v:100144$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100145.5-100145.29" + switch \initial + attribute \src "libresoc.v:100145.9-100145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] + end + attribute \src "libresoc.v:100166.3-100187.6" + process $proc$libresoc.v:100166$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99164.5-99164.29" + attribute \src "libresoc.v:100167.5-100167.29" switch \initial - attribute \src "libresoc.v:99164.9-99164.17" + attribute \src "libresoc.v:100167.9-100167.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154603,18 +156040,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:99185.3-99206.6" - process $proc$libresoc.v:99185$4003 + attribute \src "libresoc.v:100188.3-100209.6" + process $proc$libresoc.v:100188$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99186.5-99186.29" + attribute \src "libresoc.v:100189.5-100189.29" switch \initial - attribute \src "libresoc.v:99186.9-99186.17" + attribute \src "libresoc.v:100189.9-100189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154642,18 +156079,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:99207.3-99228.6" - process $proc$libresoc.v:99207$4004 + attribute \src "libresoc.v:100210.3-100231.6" + process $proc$libresoc.v:100210$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99208.5-99208.29" + attribute \src "libresoc.v:100211.5-100211.29" switch \initial - attribute \src "libresoc.v:99208.9-99208.17" + attribute \src "libresoc.v:100211.9-100211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154681,96 +156118,96 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:99229.3-99250.6" - process $proc$libresoc.v:99229$4005 + attribute \src "libresoc.v:100232.3-100253.6" + process $proc$libresoc.v:100232$4032 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:99230.5-99230.29" + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:100233.5-100233.29" switch \initial - attribute \src "libresoc.v:99230.9-99230.17" + attribute \src "libresoc.v:100233.9-100233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:99251.3-99272.6" - process $proc$libresoc.v:99251$4006 + attribute \src "libresoc.v:100254.3-100275.6" + process $proc$libresoc.v:100254$4033 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99252.5-99252.29" + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:100255.5-100255.29" switch \initial - attribute \src "libresoc.v:99252.9-99252.17" + attribute \src "libresoc.v:100255.9-100255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 end sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:99273.3-99294.6" - process $proc$libresoc.v:99273$4007 + attribute \src "libresoc.v:100276.3-100297.6" + process $proc$libresoc.v:100276$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99274.5-99274.29" + attribute \src "libresoc.v:100277.5-100277.29" switch \initial - attribute \src "libresoc.v:99274.9-99274.17" + attribute \src "libresoc.v:100277.9-100277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154798,18 +156235,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:99295.3-99316.6" - process $proc$libresoc.v:99295$4008 + attribute \src "libresoc.v:100298.3-100319.6" + process $proc$libresoc.v:100298$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99296.5-99296.29" + attribute \src "libresoc.v:100299.5-100299.29" switch \initial - attribute \src "libresoc.v:99296.9-99296.17" + attribute \src "libresoc.v:100299.9-100299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154837,18 +156274,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:99317.3-99338.6" - process $proc$libresoc.v:99317$4009 + attribute \src "libresoc.v:100320.3-100341.6" + process $proc$libresoc.v:100320$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99318.5-99318.29" + attribute \src "libresoc.v:100321.5-100321.29" switch \initial - attribute \src "libresoc.v:99318.9-99318.17" + attribute \src "libresoc.v:100321.9-100321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154876,18 +156313,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:99339.3-99360.6" - process $proc$libresoc.v:99339$4010 + attribute \src "libresoc.v:100342.3-100363.6" + process $proc$libresoc.v:100342$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99340.5-99340.29" + attribute \src "libresoc.v:100343.5-100343.29" switch \initial - attribute \src "libresoc.v:99340.9-99340.17" + attribute \src "libresoc.v:100343.9-100343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154915,18 +156352,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:99361.3-99382.6" - process $proc$libresoc.v:99361$4011 + attribute \src "libresoc.v:100364.3-100385.6" + process $proc$libresoc.v:100364$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99362.5-99362.29" + attribute \src "libresoc.v:100365.5-100365.29" switch \initial - attribute \src "libresoc.v:99362.9-99362.17" + attribute \src "libresoc.v:100365.9-100365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154954,18 +156391,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:99383.3-99404.6" - process $proc$libresoc.v:99383$4012 + attribute \src "libresoc.v:100386.3-100407.6" + process $proc$libresoc.v:100386$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99384.5-99384.29" + attribute \src "libresoc.v:100387.5-100387.29" switch \initial - attribute \src "libresoc.v:99384.9-99384.17" + attribute \src "libresoc.v:100387.9-100387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154993,18 +156430,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:99405.3-99426.6" - process $proc$libresoc.v:99405$4013 + attribute \src "libresoc.v:100408.3-100429.6" + process $proc$libresoc.v:100408$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99406.5-99406.29" + attribute \src "libresoc.v:100409.5-100409.29" switch \initial - attribute \src "libresoc.v:99406.9-99406.17" + attribute \src "libresoc.v:100409.9-100409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155032,18 +156469,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:99427.3-99448.6" - process $proc$libresoc.v:99427$4014 + attribute \src "libresoc.v:100430.3-100451.6" + process $proc$libresoc.v:100430$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99428.5-99428.29" + attribute \src "libresoc.v:100431.5-100431.29" switch \initial - attribute \src "libresoc.v:99428.9-99428.17" + attribute \src "libresoc.v:100431.9-100431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155071,18 +156508,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:99449.3-99470.6" - process $proc$libresoc.v:99449$4015 + attribute \src "libresoc.v:100452.3-100473.6" + process $proc$libresoc.v:100452$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99450.5-99450.29" + attribute \src "libresoc.v:100453.5-100453.29" switch \initial - attribute \src "libresoc.v:99450.9-99450.17" + attribute \src "libresoc.v:100453.9-100453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155110,96 +156547,96 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:99471.3-99492.6" - process $proc$libresoc.v:99471$4016 + attribute \src "libresoc.v:100474.3-100495.6" + process $proc$libresoc.v:100474$4043 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99472.5-99472.29" + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:100475.5-100475.29" switch \initial - attribute \src "libresoc.v:99472.9-99472.17" + attribute \src "libresoc.v:100475.9-100475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'00000 end sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:99493.3-99514.6" - process $proc$libresoc.v:99493$4017 + attribute \src "libresoc.v:100496.3-100517.6" + process $proc$libresoc.v:100496$4044 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99494.5-99494.29" + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:100497.5-100497.29" switch \initial - attribute \src "libresoc.v:99494.9-99494.17" + attribute \src "libresoc.v:100497.9-100497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:99515.3-99536.6" - process $proc$libresoc.v:99515$4018 + attribute \src "libresoc.v:100518.3-100539.6" + process $proc$libresoc.v:100518$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99516.5-99516.29" + attribute \src "libresoc.v:100519.5-100519.29" switch \initial - attribute \src "libresoc.v:99516.9-99516.17" + attribute \src "libresoc.v:100519.9-100519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155227,18 +156664,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:99537.3-99558.6" - process $proc$libresoc.v:99537$4019 + attribute \src "libresoc.v:100540.3-100561.6" + process $proc$libresoc.v:100540$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99538.5-99538.29" + attribute \src "libresoc.v:100541.5-100541.29" switch \initial - attribute \src "libresoc.v:99538.9-99538.17" + attribute \src "libresoc.v:100541.9-100541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155266,18 +156703,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:99559.3-99580.6" - process $proc$libresoc.v:99559$4020 + attribute \src "libresoc.v:100562.3-100583.6" + process $proc$libresoc.v:100562$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99560.5-99560.29" + attribute \src "libresoc.v:100563.5-100563.29" switch \initial - attribute \src "libresoc.v:99560.9-99560.17" + attribute \src "libresoc.v:100563.9-100563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155305,18 +156742,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:99581.3-99602.6" - process $proc$libresoc.v:99581$4021 + attribute \src "libresoc.v:100584.3-100605.6" + process $proc$libresoc.v:100584$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99582.5-99582.29" + attribute \src "libresoc.v:100585.5-100585.29" switch \initial - attribute \src "libresoc.v:99582.9-99582.17" + attribute \src "libresoc.v:100585.9-100585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155344,18 +156781,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:99603.3-99624.6" - process $proc$libresoc.v:99603$4022 + attribute \src "libresoc.v:100606.3-100627.6" + process $proc$libresoc.v:100606$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99604.5-99604.29" + attribute \src "libresoc.v:100607.5-100607.29" switch \initial - attribute \src "libresoc.v:99604.9-99604.17" + attribute \src "libresoc.v:100607.9-100607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155383,18 +156820,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:99625.3-99646.6" - process $proc$libresoc.v:99625$4023 + attribute \src "libresoc.v:100628.3-100649.6" + process $proc$libresoc.v:100628$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99626.5-99626.29" + attribute \src "libresoc.v:100629.5-100629.29" switch \initial - attribute \src "libresoc.v:99626.9-99626.17" + attribute \src "libresoc.v:100629.9-100629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155422,18 +156859,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:99647.3-99668.6" - process $proc$libresoc.v:99647$4024 + attribute \src "libresoc.v:100650.3-100671.6" + process $proc$libresoc.v:100650$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99648.5-99648.29" + attribute \src "libresoc.v:100651.5-100651.29" switch \initial - attribute \src "libresoc.v:99648.9-99648.17" + attribute \src "libresoc.v:100651.9-100651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155461,18 +156898,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:99669.3-99690.6" - process $proc$libresoc.v:99669$4025 + attribute \src "libresoc.v:100672.3-100693.6" + process $proc$libresoc.v:100672$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99670.5-99670.29" + attribute \src "libresoc.v:100673.5-100673.29" switch \initial - attribute \src "libresoc.v:99670.9-99670.17" + attribute \src "libresoc.v:100673.9-100673.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155500,18 +156937,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:99691.3-99712.6" - process $proc$libresoc.v:99691$4026 + attribute \src "libresoc.v:100694.3-100715.6" + process $proc$libresoc.v:100694$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99692.5-99692.29" + attribute \src "libresoc.v:100695.5-100695.29" switch \initial - attribute \src "libresoc.v:99692.9-99692.17" + attribute \src "libresoc.v:100695.9-100695.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155539,159 +156976,210 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end + attribute \src "libresoc.v:99642.7-99642.20" + process $proc$libresoc.v:99642$4054 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99990.3-100011.6" + process $proc$libresoc.v:99990$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99991.5-99991.29" + switch \initial + attribute \src "libresoc.v:99991.9-99991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + case + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99718.1-100666.10" +attribute \src "libresoc.v:100721.1-101698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:100551.3-100569.6" + attribute \src "libresoc.v:101583.3-101601.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100570.3-100588.6" + attribute \src "libresoc.v:101602.3-101620.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100323.3-100341.6" + attribute \src "libresoc.v:101355.3-101373.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100399.3-100417.6" + attribute \src "libresoc.v:101431.3-101449.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100076.3-100094.6" + attribute \src "libresoc.v:101089.3-101107.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100095.3-100113.6" + attribute \src "libresoc.v:101108.3-101126.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100304.3-100322.6" + attribute \src "libresoc.v:101336.3-101354.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100380.3-100398.6" + attribute \src "libresoc.v:101412.3-101430.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100475.3-100493.6" + attribute \src "libresoc.v:101488.3-101506.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100057.3-100075.6" + attribute \src "libresoc.v:101070.3-101088.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100589.3-100607.6" + attribute \src "libresoc.v:101621.3-101639.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100608.3-100626.6" + attribute \src "libresoc.v:101640.3-101658.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100627.3-100645.6" + attribute \src "libresoc.v:101659.3-101677.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100266.3-100284.6" + attribute \src "libresoc.v:101279.3-101297.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100360.6" + attribute \src "libresoc.v:101374.3-101392.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100361.3-100379.6" + attribute \src "libresoc.v:101393.3-101411.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100456.3-100474.6" + attribute \src "libresoc.v:101507.3-101525.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100228.3-100246.6" + attribute \src "libresoc.v:101260.3-101278.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100513.3-100531.6" + attribute \src "libresoc.v:101545.3-101563.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100646.3-100664.6" + attribute \src "libresoc.v:101678.3-101696.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100285.3-100303.6" + attribute \src "libresoc.v:101317.3-101335.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100437.3-100455.6" + attribute \src "libresoc.v:101469.3-101487.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100532.3-100550.6" + attribute \src "libresoc.v:101564.3-101582.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100494.3-100512.6" + attribute \src "libresoc.v:101526.3-101544.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100418.3-100436.6" + attribute \src "libresoc.v:101450.3-101468.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100190.3-100208.6" + attribute \src "libresoc.v:101222.3-101240.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100209.3-100227.6" + attribute \src "libresoc.v:101241.3-101259.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100114.3-100132.6" + attribute \src "libresoc.v:101127.3-101145.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100133.3-100151.6" + attribute \src "libresoc.v:101146.3-101164.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100152.3-100170.6" + attribute \src "libresoc.v:101165.3-101183.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100171.3-100189.6" + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100247.3-100265.6" + attribute \src "libresoc.v:101298.3-101316.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:99719.7-99719.20" + attribute \src "libresoc.v:100722.7-100722.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100551.3-100569.6" + attribute \src "libresoc.v:101583.3-101601.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100570.3-100588.6" + attribute \src "libresoc.v:101602.3-101620.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100323.3-100341.6" + attribute \src "libresoc.v:101355.3-101373.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100399.3-100417.6" + attribute \src "libresoc.v:101431.3-101449.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100076.3-100094.6" + attribute \src "libresoc.v:101089.3-101107.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100095.3-100113.6" + attribute \src "libresoc.v:101108.3-101126.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100304.3-100322.6" + attribute \src "libresoc.v:101336.3-101354.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100380.3-100398.6" + attribute \src "libresoc.v:101412.3-101430.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100475.3-100493.6" + attribute \src "libresoc.v:101488.3-101506.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100057.3-100075.6" + attribute \src "libresoc.v:101070.3-101088.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100589.3-100607.6" + attribute \src "libresoc.v:101621.3-101639.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100608.3-100626.6" + attribute \src "libresoc.v:101640.3-101658.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100627.3-100645.6" + attribute \src "libresoc.v:101659.3-101677.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100266.3-100284.6" + attribute \src "libresoc.v:101279.3-101297.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100360.6" + attribute \src "libresoc.v:101374.3-101392.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100361.3-100379.6" + attribute \src "libresoc.v:101393.3-101411.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100456.3-100474.6" + attribute \src "libresoc.v:101507.3-101525.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100228.3-100246.6" + attribute \src "libresoc.v:101260.3-101278.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100513.3-100531.6" + attribute \src "libresoc.v:101545.3-101563.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100646.3-100664.6" + attribute \src "libresoc.v:101678.3-101696.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100285.3-100303.6" + attribute \src "libresoc.v:101317.3-101335.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100437.3-100455.6" + attribute \src "libresoc.v:101469.3-101487.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100532.3-100550.6" + attribute \src "libresoc.v:101564.3-101582.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100494.3-100512.6" + attribute \src "libresoc.v:101526.3-101544.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100418.3-100436.6" + attribute \src "libresoc.v:101450.3-101468.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100190.3-100208.6" + attribute \src "libresoc.v:101222.3-101240.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100209.3-100227.6" + attribute \src "libresoc.v:101241.3-101259.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100114.3-100132.6" + attribute \src "libresoc.v:101127.3-101145.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100133.3-100151.6" + attribute \src "libresoc.v:101146.3-101164.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100152.3-100170.6" + attribute \src "libresoc.v:101165.3-101183.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100171.3-100189.6" + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100247.3-100265.6" + attribute \src "libresoc.v:101298.3-101316.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -155701,7 +157189,7 @@ module \dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -155710,16 +157198,16 @@ module \dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -155751,7 +157239,7 @@ module \dec31_dec_sub19 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -155768,7 +157256,7 @@ module \dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -155776,7 +157264,7 @@ module \dec31_dec_sub19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -155793,13 +157281,13 @@ module \dec31_dec_sub19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -155876,46 +157364,46 @@ module \dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155923,8 +157411,8 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub19_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155932,8 +157420,8 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub19_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155941,7 +157429,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155950,7 +157438,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155959,7 +157447,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155968,33 +157456,50 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub19_upd - attribute \src "libresoc.v:99719.7-99719.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub19_upd + attribute \src "libresoc.v:100722.7-100722.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100057.3-100075.6" - process $proc$libresoc.v:100057$4028 + attribute \src "libresoc.v:100722.7-100722.20" + process $proc$libresoc.v:100722$4088 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101070.3-101088.6" + process $proc$libresoc.v:101070$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100058.5-100058.29" + attribute \src "libresoc.v:101071.5-101071.29" switch \initial - attribute \src "libresoc.v:100058.9-100058.17" + attribute \src "libresoc.v:101071.9-101071.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156018,18 +157523,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:100076.3-100094.6" - process $proc$libresoc.v:100076$4029 + attribute \src "libresoc.v:101089.3-101107.6" + process $proc$libresoc.v:101089$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100077.5-100077.29" + attribute \src "libresoc.v:101090.5-101090.29" switch \initial - attribute \src "libresoc.v:100077.9-100077.17" + attribute \src "libresoc.v:101090.9-101090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156053,18 +157558,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:100095.3-100113.6" - process $proc$libresoc.v:100095$4030 + attribute \src "libresoc.v:101108.3-101126.6" + process $proc$libresoc.v:101108$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100096.5-100096.29" + attribute \src "libresoc.v:101109.5-101109.29" switch \initial - attribute \src "libresoc.v:100096.9-100096.17" + attribute \src "libresoc.v:101109.9-101109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156088,18 +157593,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:100114.3-100132.6" - process $proc$libresoc.v:100114$4031 + attribute \src "libresoc.v:101127.3-101145.6" + process $proc$libresoc.v:101127$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100115.5-100115.29" + attribute \src "libresoc.v:101128.5-101128.29" switch \initial - attribute \src "libresoc.v:100115.9-100115.17" + attribute \src "libresoc.v:101128.9-101128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156123,18 +157628,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:100133.3-100151.6" - process $proc$libresoc.v:100133$4032 + attribute \src "libresoc.v:101146.3-101164.6" + process $proc$libresoc.v:101146$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100134.5-100134.29" + attribute \src "libresoc.v:101147.5-101147.29" switch \initial - attribute \src "libresoc.v:100134.9-100134.17" + attribute \src "libresoc.v:101147.9-101147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156158,18 +157663,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:100152.3-100170.6" - process $proc$libresoc.v:100152$4033 + attribute \src "libresoc.v:101165.3-101183.6" + process $proc$libresoc.v:101165$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100153.5-100153.29" + attribute \src "libresoc.v:101166.5-101166.29" switch \initial - attribute \src "libresoc.v:100153.9-100153.17" + attribute \src "libresoc.v:101166.9-101166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156193,18 +157698,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:100171.3-100189.6" - process $proc$libresoc.v:100171$4034 + attribute \src "libresoc.v:101184.3-101202.6" + process $proc$libresoc.v:101184$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100172.5-100172.29" + attribute \src "libresoc.v:101185.5-101185.29" switch \initial - attribute \src "libresoc.v:100172.9-100172.17" + attribute \src "libresoc.v:101185.9-101185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156228,18 +157733,53 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:100190.3-100208.6" - process $proc$libresoc.v:100190$4035 + attribute \src "libresoc.v:101203.3-101221.6" + process $proc$libresoc.v:101203$4062 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101204.5-101204.29" + switch \initial + attribute \src "libresoc.v:101204.9-101204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] + end + attribute \src "libresoc.v:101222.3-101240.6" + process $proc$libresoc.v:101222$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100191.5-100191.29" + attribute \src "libresoc.v:101223.5-101223.29" switch \initial - attribute \src "libresoc.v:100191.9-100191.17" + attribute \src "libresoc.v:101223.9-101223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156263,18 +157803,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:100209.3-100227.6" - process $proc$libresoc.v:100209$4036 + attribute \src "libresoc.v:101241.3-101259.6" + process $proc$libresoc.v:101241$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100210.5-100210.29" + attribute \src "libresoc.v:101242.5-101242.29" switch \initial - attribute \src "libresoc.v:100210.9-100210.17" + attribute \src "libresoc.v:101242.9-101242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156298,18 +157838,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:100228.3-100246.6" - process $proc$libresoc.v:100228$4037 + attribute \src "libresoc.v:101260.3-101278.6" + process $proc$libresoc.v:101260$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100229.5-100229.29" + attribute \src "libresoc.v:101261.5-101261.29" switch \initial - attribute \src "libresoc.v:100229.9-100229.17" + attribute \src "libresoc.v:101261.9-101261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156333,88 +157873,88 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:100247.3-100265.6" - process $proc$libresoc.v:100247$4038 + attribute \src "libresoc.v:101279.3-101297.6" + process $proc$libresoc.v:101279$4066 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:100248.5-100248.29" + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:101280.5-101280.29" switch \initial - attribute \src "libresoc.v:100248.9-100248.17" + attribute \src "libresoc.v:101280.9-101280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:100266.3-100284.6" - process $proc$libresoc.v:100266$4039 + attribute \src "libresoc.v:101298.3-101316.6" + process $proc$libresoc.v:101298$4067 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100267.5-100267.29" + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:101299.5-101299.29" switch \initial - attribute \src "libresoc.v:100267.9-100267.17" + attribute \src "libresoc.v:101299.9-101299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 end sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:100285.3-100303.6" - process $proc$libresoc.v:100285$4040 + attribute \src "libresoc.v:101317.3-101335.6" + process $proc$libresoc.v:101317$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100286.5-100286.29" + attribute \src "libresoc.v:101318.5-101318.29" switch \initial - attribute \src "libresoc.v:100286.9-100286.17" + attribute \src "libresoc.v:101318.9-101318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156438,18 +157978,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:100304.3-100322.6" - process $proc$libresoc.v:100304$4041 + attribute \src "libresoc.v:101336.3-101354.6" + process $proc$libresoc.v:101336$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100305.5-100305.29" + attribute \src "libresoc.v:101337.5-101337.29" switch \initial - attribute \src "libresoc.v:100305.9-100305.17" + attribute \src "libresoc.v:101337.9-101337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156473,18 +158013,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:100323.3-100341.6" - process $proc$libresoc.v:100323$4042 + attribute \src "libresoc.v:101355.3-101373.6" + process $proc$libresoc.v:101355$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100324.5-100324.29" + attribute \src "libresoc.v:101356.5-101356.29" switch \initial - attribute \src "libresoc.v:100324.9-100324.17" + attribute \src "libresoc.v:101356.9-101356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156508,18 +158048,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:100342.3-100360.6" - process $proc$libresoc.v:100342$4043 + attribute \src "libresoc.v:101374.3-101392.6" + process $proc$libresoc.v:101374$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100343.5-100343.29" + attribute \src "libresoc.v:101375.5-101375.29" switch \initial - attribute \src "libresoc.v:100343.9-100343.17" + attribute \src "libresoc.v:101375.9-101375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156543,18 +158083,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:100361.3-100379.6" - process $proc$libresoc.v:100361$4044 + attribute \src "libresoc.v:101393.3-101411.6" + process $proc$libresoc.v:101393$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100362.5-100362.29" + attribute \src "libresoc.v:101394.5-101394.29" switch \initial - attribute \src "libresoc.v:100362.9-100362.17" + attribute \src "libresoc.v:101394.9-101394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156578,18 +158118,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:100380.3-100398.6" - process $proc$libresoc.v:100380$4045 + attribute \src "libresoc.v:101412.3-101430.6" + process $proc$libresoc.v:101412$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100381.5-100381.29" + attribute \src "libresoc.v:101413.5-101413.29" switch \initial - attribute \src "libresoc.v:100381.9-100381.17" + attribute \src "libresoc.v:101413.9-101413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156613,18 +158153,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:100399.3-100417.6" - process $proc$libresoc.v:100399$4046 + attribute \src "libresoc.v:101431.3-101449.6" + process $proc$libresoc.v:101431$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100400.5-100400.29" + attribute \src "libresoc.v:101432.5-101432.29" switch \initial - attribute \src "libresoc.v:100400.9-100400.17" + attribute \src "libresoc.v:101432.9-101432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156648,18 +158188,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:100418.3-100436.6" - process $proc$libresoc.v:100418$4047 + attribute \src "libresoc.v:101450.3-101468.6" + process $proc$libresoc.v:101450$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100419.5-100419.29" + attribute \src "libresoc.v:101451.5-101451.29" switch \initial - attribute \src "libresoc.v:100419.9-100419.17" + attribute \src "libresoc.v:101451.9-101451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156683,18 +158223,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:100437.3-100455.6" - process $proc$libresoc.v:100437$4048 + attribute \src "libresoc.v:101469.3-101487.6" + process $proc$libresoc.v:101469$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100438.5-100438.29" + attribute \src "libresoc.v:101470.5-101470.29" switch \initial - attribute \src "libresoc.v:100438.9-100438.17" + attribute \src "libresoc.v:101470.9-101470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156718,88 +158258,88 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:100456.3-100474.6" - process $proc$libresoc.v:100456$4049 + attribute \src "libresoc.v:101488.3-101506.6" + process $proc$libresoc.v:101488$4077 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100457.5-100457.29" + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:101489.5-101489.29" switch \initial - attribute \src "libresoc.v:100457.9-100457.17" + attribute \src "libresoc.v:101489.9-101489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'00000 end sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:100475.3-100493.6" - process $proc$libresoc.v:100475$4050 + attribute \src "libresoc.v:101507.3-101525.6" + process $proc$libresoc.v:101507$4078 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100476.5-100476.29" + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:101508.5-101508.29" switch \initial - attribute \src "libresoc.v:100476.9-100476.17" + attribute \src "libresoc.v:101508.9-101508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:100494.3-100512.6" - process $proc$libresoc.v:100494$4051 + attribute \src "libresoc.v:101526.3-101544.6" + process $proc$libresoc.v:101526$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100495.5-100495.29" + attribute \src "libresoc.v:101527.5-101527.29" switch \initial - attribute \src "libresoc.v:100495.9-100495.17" + attribute \src "libresoc.v:101527.9-101527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156823,18 +158363,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:100513.3-100531.6" - process $proc$libresoc.v:100513$4052 + attribute \src "libresoc.v:101545.3-101563.6" + process $proc$libresoc.v:101545$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100514.5-100514.29" + attribute \src "libresoc.v:101546.5-101546.29" switch \initial - attribute \src "libresoc.v:100514.9-100514.17" + attribute \src "libresoc.v:101546.9-101546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156858,18 +158398,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:100532.3-100550.6" - process $proc$libresoc.v:100532$4053 + attribute \src "libresoc.v:101564.3-101582.6" + process $proc$libresoc.v:101564$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100533.5-100533.29" + attribute \src "libresoc.v:101565.5-101565.29" switch \initial - attribute \src "libresoc.v:100533.9-100533.17" + attribute \src "libresoc.v:101565.9-101565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156893,18 +158433,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:100551.3-100569.6" - process $proc$libresoc.v:100551$4054 + attribute \src "libresoc.v:101583.3-101601.6" + process $proc$libresoc.v:101583$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100552.5-100552.29" + attribute \src "libresoc.v:101584.5-101584.29" switch \initial - attribute \src "libresoc.v:100552.9-100552.17" + attribute \src "libresoc.v:101584.9-101584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156928,18 +158468,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:100570.3-100588.6" - process $proc$libresoc.v:100570$4055 + attribute \src "libresoc.v:101602.3-101620.6" + process $proc$libresoc.v:101602$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100571.5-100571.29" + attribute \src "libresoc.v:101603.5-101603.29" switch \initial - attribute \src "libresoc.v:100571.9-100571.17" + attribute \src "libresoc.v:101603.9-101603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156963,18 +158503,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:100589.3-100607.6" - process $proc$libresoc.v:100589$4056 + attribute \src "libresoc.v:101621.3-101639.6" + process $proc$libresoc.v:101621$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100590.5-100590.29" + attribute \src "libresoc.v:101622.5-101622.29" switch \initial - attribute \src "libresoc.v:100590.9-100590.17" + attribute \src "libresoc.v:101622.9-101622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156998,18 +158538,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:100608.3-100626.6" - process $proc$libresoc.v:100608$4057 + attribute \src "libresoc.v:101640.3-101658.6" + process $proc$libresoc.v:101640$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100609.5-100609.29" + attribute \src "libresoc.v:101641.5-101641.29" switch \initial - attribute \src "libresoc.v:100609.9-100609.17" + attribute \src "libresoc.v:101641.9-101641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157033,18 +158573,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:100627.3-100645.6" - process $proc$libresoc.v:100627$4058 + attribute \src "libresoc.v:101659.3-101677.6" + process $proc$libresoc.v:101659$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100628.5-100628.29" + attribute \src "libresoc.v:101660.5-101660.29" switch \initial - attribute \src "libresoc.v:100628.9-100628.17" + attribute \src "libresoc.v:101660.9-101660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157068,18 +158608,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:100646.3-100664.6" - process $proc$libresoc.v:100646$4059 + attribute \src "libresoc.v:101678.3-101696.6" + process $proc$libresoc.v:101678$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100647.5-100647.29" + attribute \src "libresoc.v:101679.5-101679.29" switch \initial - attribute \src "libresoc.v:100647.9-100647.17" + attribute \src "libresoc.v:101679.9-101679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157103,167 +158643,163 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] end - attribute \src "libresoc.v:99719.7-99719.20" - process $proc$libresoc.v:99719$4060 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100670.1-101810.10" +attribute \src "libresoc.v:101702.1-102877.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:101659.3-101683.6" + attribute \src "libresoc.v:102726.3-102750.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101684.3-101708.6" + attribute \src "libresoc.v:102751.3-102775.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101359.3-101383.6" + attribute \src "libresoc.v:102426.3-102450.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101459.3-101483.6" + attribute \src "libresoc.v:102526.3-102550.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101034.3-101058.6" + attribute \src "libresoc.v:102076.3-102100.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101059.3-101083.6" + attribute \src "libresoc.v:102101.3-102125.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101334.3-101358.6" + attribute \src "libresoc.v:102401.3-102425.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101434.3-101458.6" + attribute \src "libresoc.v:102501.3-102525.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101559.3-101583.6" + attribute \src "libresoc.v:102601.3-102625.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101009.3-101033.6" + attribute \src "libresoc.v:102051.3-102075.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101709.3-101733.6" + attribute \src "libresoc.v:102776.3-102800.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101734.3-101758.6" + attribute \src "libresoc.v:102801.3-102825.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101759.3-101783.6" + attribute \src "libresoc.v:102826.3-102850.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101284.3-101308.6" + attribute \src "libresoc.v:102326.3-102350.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101384.3-101408.6" + attribute \src "libresoc.v:102451.3-102475.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101409.3-101433.6" + attribute \src "libresoc.v:102476.3-102500.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101534.3-101558.6" + attribute \src "libresoc.v:102626.3-102650.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101234.3-101258.6" + attribute \src "libresoc.v:102301.3-102325.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101609.3-101633.6" + attribute \src "libresoc.v:102676.3-102700.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101784.3-101808.6" + attribute \src "libresoc.v:102851.3-102875.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101309.3-101333.6" + attribute \src "libresoc.v:102376.3-102400.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101509.3-101533.6" + attribute \src "libresoc.v:102576.3-102600.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101634.3-101658.6" + attribute \src "libresoc.v:102701.3-102725.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101584.3-101608.6" + attribute \src "libresoc.v:102651.3-102675.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101484.3-101508.6" + attribute \src "libresoc.v:102551.3-102575.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101184.3-101208.6" + attribute \src "libresoc.v:102251.3-102275.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101209.3-101233.6" + attribute \src "libresoc.v:102276.3-102300.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101084.3-101108.6" + attribute \src "libresoc.v:102126.3-102150.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101109.3-101133.6" + attribute \src "libresoc.v:102151.3-102175.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101134.3-101158.6" + attribute \src "libresoc.v:102176.3-102200.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101159.3-101183.6" + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101259.3-101283.6" + attribute \src "libresoc.v:102351.3-102375.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:100671.7-100671.20" + attribute \src "libresoc.v:101703.7-101703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101659.3-101683.6" + attribute \src "libresoc.v:102726.3-102750.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101684.3-101708.6" + attribute \src "libresoc.v:102751.3-102775.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101359.3-101383.6" + attribute \src "libresoc.v:102426.3-102450.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101459.3-101483.6" + attribute \src "libresoc.v:102526.3-102550.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101034.3-101058.6" + attribute \src "libresoc.v:102076.3-102100.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101059.3-101083.6" + attribute \src "libresoc.v:102101.3-102125.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101334.3-101358.6" + attribute \src "libresoc.v:102401.3-102425.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101434.3-101458.6" + attribute \src "libresoc.v:102501.3-102525.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101559.3-101583.6" + attribute \src "libresoc.v:102601.3-102625.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101009.3-101033.6" + attribute \src "libresoc.v:102051.3-102075.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101709.3-101733.6" + attribute \src "libresoc.v:102776.3-102800.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101734.3-101758.6" + attribute \src "libresoc.v:102801.3-102825.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101759.3-101783.6" + attribute \src "libresoc.v:102826.3-102850.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101284.3-101308.6" + attribute \src "libresoc.v:102326.3-102350.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101384.3-101408.6" + attribute \src "libresoc.v:102451.3-102475.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101409.3-101433.6" + attribute \src "libresoc.v:102476.3-102500.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101534.3-101558.6" + attribute \src "libresoc.v:102626.3-102650.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101234.3-101258.6" + attribute \src "libresoc.v:102301.3-102325.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101609.3-101633.6" + attribute \src "libresoc.v:102676.3-102700.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101784.3-101808.6" + attribute \src "libresoc.v:102851.3-102875.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101309.3-101333.6" + attribute \src "libresoc.v:102376.3-102400.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101509.3-101533.6" + attribute \src "libresoc.v:102576.3-102600.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101634.3-101658.6" + attribute \src "libresoc.v:102701.3-102725.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101584.3-101608.6" + attribute \src "libresoc.v:102651.3-102675.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101484.3-101508.6" + attribute \src "libresoc.v:102551.3-102575.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101184.3-101208.6" + attribute \src "libresoc.v:102251.3-102275.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101209.3-101233.6" + attribute \src "libresoc.v:102276.3-102300.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101084.3-101108.6" + attribute \src "libresoc.v:102126.3-102150.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101109.3-101133.6" + attribute \src "libresoc.v:102151.3-102175.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101134.3-101158.6" + attribute \src "libresoc.v:102176.3-102200.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101159.3-101183.6" + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101259.3-101283.6" + attribute \src "libresoc.v:102351.3-102375.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub20_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub20_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub20_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -157273,7 +158809,7 @@ module \dec31_dec_sub20 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -157282,16 +158818,16 @@ module \dec31_dec_sub20 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub20_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -157323,7 +158859,7 @@ module \dec31_dec_sub20 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -157340,7 +158876,7 @@ module \dec31_dec_sub20 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -157348,7 +158884,7 @@ module \dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -157365,13 +158901,13 @@ module \dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -157448,46 +158984,46 @@ module \dec31_dec_sub20 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub20_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub20_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub20_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub20_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157495,8 +159031,8 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub20_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub20_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157504,8 +159040,8 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub20_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub20_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157513,7 +159049,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub20_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157522,7 +159058,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub20_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157531,7 +159067,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub20_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157540,41 +159076,50 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub20_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub20_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub20_upd - attribute \src "libresoc.v:100671.7-100671.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub20_upd + attribute \src "libresoc.v:101703.7-101703.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100671.7-100671.20" - process $proc$libresoc.v:100671$4093 + attribute \src "libresoc.v:101703.7-101703.20" + process $proc$libresoc.v:101703$4122 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101009.3-101033.6" - process $proc$libresoc.v:101009$4061 + attribute \src "libresoc.v:102051.3-102075.6" + process $proc$libresoc.v:102051$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101010.5-101010.29" + attribute \src "libresoc.v:102052.5-102052.29" switch \initial - attribute \src "libresoc.v:101010.9-101010.17" + attribute \src "libresoc.v:102052.9-102052.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157606,18 +159151,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:101034.3-101058.6" - process $proc$libresoc.v:101034$4062 + attribute \src "libresoc.v:102076.3-102100.6" + process $proc$libresoc.v:102076$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101035.5-101035.29" + attribute \src "libresoc.v:102077.5-102077.29" switch \initial - attribute \src "libresoc.v:101035.9-101035.17" + attribute \src "libresoc.v:102077.9-102077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157649,18 +159194,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:101059.3-101083.6" - process $proc$libresoc.v:101059$4063 + attribute \src "libresoc.v:102101.3-102125.6" + process $proc$libresoc.v:102101$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101060.5-101060.29" + attribute \src "libresoc.v:102102.5-102102.29" switch \initial - attribute \src "libresoc.v:101060.9-101060.17" + attribute \src "libresoc.v:102102.9-102102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157692,18 +159237,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:101084.3-101108.6" - process $proc$libresoc.v:101084$4064 + attribute \src "libresoc.v:102126.3-102150.6" + process $proc$libresoc.v:102126$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101085.5-101085.29" + attribute \src "libresoc.v:102127.5-102127.29" switch \initial - attribute \src "libresoc.v:101085.9-101085.17" + attribute \src "libresoc.v:102127.9-102127.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157735,18 +159280,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:101109.3-101133.6" - process $proc$libresoc.v:101109$4065 + attribute \src "libresoc.v:102151.3-102175.6" + process $proc$libresoc.v:102151$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101110.5-101110.29" + attribute \src "libresoc.v:102152.5-102152.29" switch \initial - attribute \src "libresoc.v:101110.9-101110.17" + attribute \src "libresoc.v:102152.9-102152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157778,18 +159323,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:101134.3-101158.6" - process $proc$libresoc.v:101134$4066 + attribute \src "libresoc.v:102176.3-102200.6" + process $proc$libresoc.v:102176$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101135.5-101135.29" + attribute \src "libresoc.v:102177.5-102177.29" switch \initial - attribute \src "libresoc.v:101135.9-101135.17" + attribute \src "libresoc.v:102177.9-102177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157821,18 +159366,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:101159.3-101183.6" - process $proc$libresoc.v:101159$4067 + attribute \src "libresoc.v:102201.3-102225.6" + process $proc$libresoc.v:102201$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101160.5-101160.29" + attribute \src "libresoc.v:102202.5-102202.29" switch \initial - attribute \src "libresoc.v:101160.9-101160.17" + attribute \src "libresoc.v:102202.9-102202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157864,18 +159409,61 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:101184.3-101208.6" - process $proc$libresoc.v:101184$4068 + attribute \src "libresoc.v:102226.3-102250.6" + process $proc$libresoc.v:102226$4096 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102227.5-102227.29" + switch \initial + attribute \src "libresoc.v:102227.9-102227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] + end + attribute \src "libresoc.v:102251.3-102275.6" + process $proc$libresoc.v:102251$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101185.5-101185.29" + attribute \src "libresoc.v:102252.5-102252.29" switch \initial - attribute \src "libresoc.v:101185.9-101185.17" + attribute \src "libresoc.v:102252.9-102252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157907,18 +159495,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:101209.3-101233.6" - process $proc$libresoc.v:101209$4069 + attribute \src "libresoc.v:102276.3-102300.6" + process $proc$libresoc.v:102276$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101210.5-101210.29" + attribute \src "libresoc.v:102277.5-102277.29" switch \initial - attribute \src "libresoc.v:101210.9-101210.17" + attribute \src "libresoc.v:102277.9-102277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157950,18 +159538,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:101234.3-101258.6" - process $proc$libresoc.v:101234$4070 + attribute \src "libresoc.v:102301.3-102325.6" + process $proc$libresoc.v:102301$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101235.5-101235.29" + attribute \src "libresoc.v:102302.5-102302.29" switch \initial - attribute \src "libresoc.v:101235.9-101235.17" + attribute \src "libresoc.v:102302.9-102302.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157993,104 +159581,104 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:101259.3-101283.6" - process $proc$libresoc.v:101259$4071 + attribute \src "libresoc.v:102326.3-102350.6" + process $proc$libresoc.v:102326$4100 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:101260.5-101260.29" + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:102327.5-102327.29" switch \initial - attribute \src "libresoc.v:101260.9-101260.17" + attribute \src "libresoc.v:102327.9-102327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:101284.3-101308.6" - process $proc$libresoc.v:101284$4072 + attribute \src "libresoc.v:102351.3-102375.6" + process $proc$libresoc.v:102351$4101 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101285.5-101285.29" + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:102352.5-102352.29" switch \initial - attribute \src "libresoc.v:101285.9-101285.17" + attribute \src "libresoc.v:102352.9-102352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 end sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:101309.3-101333.6" - process $proc$libresoc.v:101309$4073 + attribute \src "libresoc.v:102376.3-102400.6" + process $proc$libresoc.v:102376$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101310.5-101310.29" + attribute \src "libresoc.v:102377.5-102377.29" switch \initial - attribute \src "libresoc.v:101310.9-101310.17" + attribute \src "libresoc.v:102377.9-102377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158122,18 +159710,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:101334.3-101358.6" - process $proc$libresoc.v:101334$4074 + attribute \src "libresoc.v:102401.3-102425.6" + process $proc$libresoc.v:102401$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101335.5-101335.29" + attribute \src "libresoc.v:102402.5-102402.29" switch \initial - attribute \src "libresoc.v:101335.9-101335.17" + attribute \src "libresoc.v:102402.9-102402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158165,18 +159753,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:101359.3-101383.6" - process $proc$libresoc.v:101359$4075 + attribute \src "libresoc.v:102426.3-102450.6" + process $proc$libresoc.v:102426$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101360.5-101360.29" + attribute \src "libresoc.v:102427.5-102427.29" switch \initial - attribute \src "libresoc.v:101360.9-101360.17" + attribute \src "libresoc.v:102427.9-102427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158208,18 +159796,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:101384.3-101408.6" - process $proc$libresoc.v:101384$4076 + attribute \src "libresoc.v:102451.3-102475.6" + process $proc$libresoc.v:102451$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101385.5-101385.29" + attribute \src "libresoc.v:102452.5-102452.29" switch \initial - attribute \src "libresoc.v:101385.9-101385.17" + attribute \src "libresoc.v:102452.9-102452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158251,18 +159839,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:101409.3-101433.6" - process $proc$libresoc.v:101409$4077 + attribute \src "libresoc.v:102476.3-102500.6" + process $proc$libresoc.v:102476$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101410.5-101410.29" + attribute \src "libresoc.v:102477.5-102477.29" switch \initial - attribute \src "libresoc.v:101410.9-101410.17" + attribute \src "libresoc.v:102477.9-102477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158294,18 +159882,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:101434.3-101458.6" - process $proc$libresoc.v:101434$4078 + attribute \src "libresoc.v:102501.3-102525.6" + process $proc$libresoc.v:102501$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101435.5-101435.29" + attribute \src "libresoc.v:102502.5-102502.29" switch \initial - attribute \src "libresoc.v:101435.9-101435.17" + attribute \src "libresoc.v:102502.9-102502.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158337,18 +159925,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:101459.3-101483.6" - process $proc$libresoc.v:101459$4079 + attribute \src "libresoc.v:102526.3-102550.6" + process $proc$libresoc.v:102526$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101460.5-101460.29" + attribute \src "libresoc.v:102527.5-102527.29" switch \initial - attribute \src "libresoc.v:101460.9-101460.17" + attribute \src "libresoc.v:102527.9-102527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158380,18 +159968,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:101484.3-101508.6" - process $proc$libresoc.v:101484$4080 + attribute \src "libresoc.v:102551.3-102575.6" + process $proc$libresoc.v:102551$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101485.5-101485.29" + attribute \src "libresoc.v:102552.5-102552.29" switch \initial - attribute \src "libresoc.v:101485.9-101485.17" + attribute \src "libresoc.v:102552.9-102552.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158423,18 +160011,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:101509.3-101533.6" - process $proc$libresoc.v:101509$4081 + attribute \src "libresoc.v:102576.3-102600.6" + process $proc$libresoc.v:102576$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101510.5-101510.29" + attribute \src "libresoc.v:102577.5-102577.29" switch \initial - attribute \src "libresoc.v:101510.9-101510.17" + attribute \src "libresoc.v:102577.9-102577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158466,104 +160054,104 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:101534.3-101558.6" - process $proc$libresoc.v:101534$4082 + attribute \src "libresoc.v:102601.3-102625.6" + process $proc$libresoc.v:102601$4111 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101535.5-101535.29" + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:102602.5-102602.29" switch \initial - attribute \src "libresoc.v:101535.9-101535.17" + attribute \src "libresoc.v:102602.9-102602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'00000 end sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:101559.3-101583.6" - process $proc$libresoc.v:101559$4083 + attribute \src "libresoc.v:102626.3-102650.6" + process $proc$libresoc.v:102626$4112 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101560.5-101560.29" + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:102627.5-102627.29" switch \initial - attribute \src "libresoc.v:101560.9-101560.17" + attribute \src "libresoc.v:102627.9-102627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:101584.3-101608.6" - process $proc$libresoc.v:101584$4084 + attribute \src "libresoc.v:102651.3-102675.6" + process $proc$libresoc.v:102651$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101585.5-101585.29" + attribute \src "libresoc.v:102652.5-102652.29" switch \initial - attribute \src "libresoc.v:101585.9-101585.17" + attribute \src "libresoc.v:102652.9-102652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158595,18 +160183,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:101609.3-101633.6" - process $proc$libresoc.v:101609$4085 + attribute \src "libresoc.v:102676.3-102700.6" + process $proc$libresoc.v:102676$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101610.5-101610.29" + attribute \src "libresoc.v:102677.5-102677.29" switch \initial - attribute \src "libresoc.v:101610.9-101610.17" + attribute \src "libresoc.v:102677.9-102677.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158638,18 +160226,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:101634.3-101658.6" - process $proc$libresoc.v:101634$4086 + attribute \src "libresoc.v:102701.3-102725.6" + process $proc$libresoc.v:102701$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101635.5-101635.29" + attribute \src "libresoc.v:102702.5-102702.29" switch \initial - attribute \src "libresoc.v:101635.9-101635.17" + attribute \src "libresoc.v:102702.9-102702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158681,18 +160269,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:101659.3-101683.6" - process $proc$libresoc.v:101659$4087 + attribute \src "libresoc.v:102726.3-102750.6" + process $proc$libresoc.v:102726$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101660.5-101660.29" + attribute \src "libresoc.v:102727.5-102727.29" switch \initial - attribute \src "libresoc.v:101660.9-101660.17" + attribute \src "libresoc.v:102727.9-102727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158724,18 +160312,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:101684.3-101708.6" - process $proc$libresoc.v:101684$4088 + attribute \src "libresoc.v:102751.3-102775.6" + process $proc$libresoc.v:102751$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101685.5-101685.29" + attribute \src "libresoc.v:102752.5-102752.29" switch \initial - attribute \src "libresoc.v:101685.9-101685.17" + attribute \src "libresoc.v:102752.9-102752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158767,18 +160355,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:101709.3-101733.6" - process $proc$libresoc.v:101709$4089 + attribute \src "libresoc.v:102776.3-102800.6" + process $proc$libresoc.v:102776$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101710.5-101710.29" + attribute \src "libresoc.v:102777.5-102777.29" switch \initial - attribute \src "libresoc.v:101710.9-101710.17" + attribute \src "libresoc.v:102777.9-102777.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158810,18 +160398,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:101734.3-101758.6" - process $proc$libresoc.v:101734$4090 + attribute \src "libresoc.v:102801.3-102825.6" + process $proc$libresoc.v:102801$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101735.5-101735.29" + attribute \src "libresoc.v:102802.5-102802.29" switch \initial - attribute \src "libresoc.v:101735.9-101735.17" + attribute \src "libresoc.v:102802.9-102802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158853,18 +160441,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:101759.3-101783.6" - process $proc$libresoc.v:101759$4091 + attribute \src "libresoc.v:102826.3-102850.6" + process $proc$libresoc.v:102826$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101760.5-101760.29" + attribute \src "libresoc.v:102827.5-102827.29" switch \initial - attribute \src "libresoc.v:101760.9-101760.17" + attribute \src "libresoc.v:102827.9-102827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158896,18 +160484,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:101784.3-101808.6" - process $proc$libresoc.v:101784$4092 + attribute \src "libresoc.v:102851.3-102875.6" + process $proc$libresoc.v:102851$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101785.5-101785.29" + attribute \src "libresoc.v:102852.5-102852.29" switch \initial - attribute \src "libresoc.v:101785.9-101785.17" + attribute \src "libresoc.v:102852.9-102852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158941,157 +160529,161 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101814.1-103704.10" +attribute \src "libresoc.v:102881.1-104830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:103409.3-103457.6" + attribute \src "libresoc.v:104535.3-104583.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103458.3-103506.6" + attribute \src "libresoc.v:104584.3-104632.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103378.3-103408.6" + attribute \src "libresoc.v:104504.3-104534.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102986.3-103034.6" + attribute \src "libresoc.v:104112.3-104160.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102202.3-102250.6" + attribute \src "libresoc.v:103279.3-103327.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102251.3-102299.6" + attribute \src "libresoc.v:103328.3-103376.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102790.3-102838.6" + attribute \src "libresoc.v:103916.3-103964.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102937.3-102985.6" + attribute \src "libresoc.v:104063.3-104111.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:103231.3-103279.6" + attribute \src "libresoc.v:104308.3-104356.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:102153.3-102201.6" + attribute \src "libresoc.v:103230.3-103278.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103507.3-103555.6" + attribute \src "libresoc.v:104633.3-104681.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103556.3-103604.6" + attribute \src "libresoc.v:104682.3-104730.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103605.3-103653.6" + attribute \src "libresoc.v:104731.3-104779.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102692.3-102740.6" + attribute \src "libresoc.v:103769.3-103817.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102839.3-102887.6" + attribute \src "libresoc.v:103965.3-104013.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102888.3-102936.6" + attribute \src "libresoc.v:104014.3-104062.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:103133.3-103181.6" + attribute \src "libresoc.v:104259.3-104307.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:102594.3-102642.6" + attribute \src "libresoc.v:103720.3-103768.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103280.3-103328.6" + attribute \src "libresoc.v:104406.3-104454.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103654.3-103702.6" + attribute \src "libresoc.v:104780.3-104828.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:102741.3-102789.6" + attribute \src "libresoc.v:103867.3-103915.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103084.3-103132.6" + attribute \src "libresoc.v:104210.3-104258.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103329.3-103377.6" + attribute \src "libresoc.v:104455.3-104503.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103182.3-103230.6" + attribute \src "libresoc.v:104357.3-104405.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103035.3-103083.6" + attribute \src "libresoc.v:104161.3-104209.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:102496.3-102544.6" + attribute \src "libresoc.v:103622.3-103670.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102545.3-102593.6" + attribute \src "libresoc.v:103671.3-103719.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102300.3-102348.6" + attribute \src "libresoc.v:103377.3-103425.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102349.3-102397.6" + attribute \src "libresoc.v:103426.3-103474.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102398.3-102446.6" + attribute \src "libresoc.v:103475.3-103523.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102447.3-102495.6" + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102643.3-102691.6" + attribute \src "libresoc.v:103818.3-103866.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:101815.7-101815.20" + attribute \src "libresoc.v:102882.7-102882.20" wire $0\initial[0:0] - attribute \src "libresoc.v:103409.3-103457.6" + attribute \src "libresoc.v:104535.3-104583.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103458.3-103506.6" + attribute \src "libresoc.v:104584.3-104632.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103378.3-103408.6" + attribute \src "libresoc.v:104504.3-104534.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102986.3-103034.6" + attribute \src "libresoc.v:104112.3-104160.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102202.3-102250.6" + attribute \src "libresoc.v:103279.3-103327.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102251.3-102299.6" + attribute \src "libresoc.v:103328.3-103376.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102790.3-102838.6" + attribute \src "libresoc.v:103916.3-103964.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102937.3-102985.6" + attribute \src "libresoc.v:104063.3-104111.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:103231.3-103279.6" + attribute \src "libresoc.v:104308.3-104356.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:102153.3-102201.6" + attribute \src "libresoc.v:103230.3-103278.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103507.3-103555.6" + attribute \src "libresoc.v:104633.3-104681.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103556.3-103604.6" + attribute \src "libresoc.v:104682.3-104730.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103605.3-103653.6" + attribute \src "libresoc.v:104731.3-104779.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102692.3-102740.6" + attribute \src "libresoc.v:103769.3-103817.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102839.3-102887.6" + attribute \src "libresoc.v:103965.3-104013.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102888.3-102936.6" + attribute \src "libresoc.v:104014.3-104062.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:103133.3-103181.6" + attribute \src "libresoc.v:104259.3-104307.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:102594.3-102642.6" + attribute \src "libresoc.v:103720.3-103768.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103280.3-103328.6" + attribute \src "libresoc.v:104406.3-104454.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103654.3-103702.6" + attribute \src "libresoc.v:104780.3-104828.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:102741.3-102789.6" + attribute \src "libresoc.v:103867.3-103915.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103084.3-103132.6" + attribute \src "libresoc.v:104210.3-104258.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103329.3-103377.6" + attribute \src "libresoc.v:104455.3-104503.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103182.3-103230.6" + attribute \src "libresoc.v:104357.3-104405.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103035.3-103083.6" + attribute \src "libresoc.v:104161.3-104209.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:102496.3-102544.6" + attribute \src "libresoc.v:103622.3-103670.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102545.3-102593.6" + attribute \src "libresoc.v:103671.3-103719.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102300.3-102348.6" + attribute \src "libresoc.v:103377.3-103425.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102349.3-102397.6" + attribute \src "libresoc.v:103426.3-103474.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102398.3-102446.6" + attribute \src "libresoc.v:103475.3-103523.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102447.3-102495.6" + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102643.3-102691.6" + attribute \src "libresoc.v:103818.3-103866.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub21_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub21_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub21_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -159101,7 +160693,7 @@ module \dec31_dec_sub21 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -159110,16 +160702,16 @@ module \dec31_dec_sub21 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub21_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -159151,7 +160743,7 @@ module \dec31_dec_sub21 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -159168,7 +160760,7 @@ module \dec31_dec_sub21 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -159176,7 +160768,7 @@ module \dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -159193,13 +160785,13 @@ module \dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -159276,46 +160868,46 @@ module \dec31_dec_sub21 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub21_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub21_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub21_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159323,8 +160915,8 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub21_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub21_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159332,8 +160924,8 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub21_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub21_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159341,7 +160933,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub21_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159350,7 +160942,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub21_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159359,7 +160951,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub21_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159368,41 +160960,50 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub21_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub21_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub21_upd - attribute \src "libresoc.v:101815.7-101815.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub21_upd + attribute \src "libresoc.v:102882.7-102882.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:101815.7-101815.20" - process $proc$libresoc.v:101815$4126 + attribute \src "libresoc.v:102882.7-102882.20" + process $proc$libresoc.v:102882$4156 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102153.3-102201.6" - process $proc$libresoc.v:102153$4094 + attribute \src "libresoc.v:103230.3-103278.6" + process $proc$libresoc.v:103230$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:102154.5-102154.29" + attribute \src "libresoc.v:103231.5-103231.29" switch \initial - attribute \src "libresoc.v:102154.9-102154.17" + attribute \src "libresoc.v:103231.9-103231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159466,18 +161067,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:102202.3-102250.6" - process $proc$libresoc.v:102202$4095 + attribute \src "libresoc.v:103279.3-103327.6" + process $proc$libresoc.v:103279$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102203.5-102203.29" + attribute \src "libresoc.v:103280.5-103280.29" switch \initial - attribute \src "libresoc.v:102203.9-102203.17" + attribute \src "libresoc.v:103280.9-103280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159541,18 +161142,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:102251.3-102299.6" - process $proc$libresoc.v:102251$4096 + attribute \src "libresoc.v:103328.3-103376.6" + process $proc$libresoc.v:103328$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102252.5-102252.29" + attribute \src "libresoc.v:103329.5-103329.29" switch \initial - attribute \src "libresoc.v:102252.9-102252.17" + attribute \src "libresoc.v:103329.9-103329.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159616,18 +161217,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:102300.3-102348.6" - process $proc$libresoc.v:102300$4097 + attribute \src "libresoc.v:103377.3-103425.6" + process $proc$libresoc.v:103377$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102301.5-102301.29" + attribute \src "libresoc.v:103378.5-103378.29" switch \initial - attribute \src "libresoc.v:102301.9-102301.17" + attribute \src "libresoc.v:103378.9-103378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159691,18 +161292,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:102349.3-102397.6" - process $proc$libresoc.v:102349$4098 + attribute \src "libresoc.v:103426.3-103474.6" + process $proc$libresoc.v:103426$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102350.5-102350.29" + attribute \src "libresoc.v:103427.5-103427.29" switch \initial - attribute \src "libresoc.v:102350.9-102350.17" + attribute \src "libresoc.v:103427.9-103427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159766,18 +161367,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:102398.3-102446.6" - process $proc$libresoc.v:102398$4099 + attribute \src "libresoc.v:103475.3-103523.6" + process $proc$libresoc.v:103475$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102399.5-102399.29" + attribute \src "libresoc.v:103476.5-103476.29" switch \initial - attribute \src "libresoc.v:102399.9-102399.17" + attribute \src "libresoc.v:103476.9-103476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159841,18 +161442,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:102447.3-102495.6" - process $proc$libresoc.v:102447$4100 + attribute \src "libresoc.v:103524.3-103572.6" + process $proc$libresoc.v:103524$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102448.5-102448.29" + attribute \src "libresoc.v:103525.5-103525.29" switch \initial - attribute \src "libresoc.v:102448.9-102448.17" + attribute \src "libresoc.v:103525.9-103525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159916,18 +161517,93 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:102496.3-102544.6" - process $proc$libresoc.v:102496$4101 + attribute \src "libresoc.v:103573.3-103621.6" + process $proc$libresoc.v:103573$4130 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103574.5-103574.29" + switch \initial + attribute \src "libresoc.v:103574.9-103574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] + end + attribute \src "libresoc.v:103622.3-103670.6" + process $proc$libresoc.v:103622$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102497.5-102497.29" + attribute \src "libresoc.v:103623.5-103623.29" switch \initial - attribute \src "libresoc.v:102497.9-102497.17" + attribute \src "libresoc.v:103623.9-103623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159991,18 +161667,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:102545.3-102593.6" - process $proc$libresoc.v:102545$4102 + attribute \src "libresoc.v:103671.3-103719.6" + process $proc$libresoc.v:103671$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102546.5-102546.29" + attribute \src "libresoc.v:103672.5-103672.29" switch \initial - attribute \src "libresoc.v:102546.9-102546.17" + attribute \src "libresoc.v:103672.9-103672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160066,18 +161742,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:102594.3-102642.6" - process $proc$libresoc.v:102594$4103 + attribute \src "libresoc.v:103720.3-103768.6" + process $proc$libresoc.v:103720$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:102595.5-102595.29" + attribute \src "libresoc.v:103721.5-103721.29" switch \initial - attribute \src "libresoc.v:102595.9-102595.17" + attribute \src "libresoc.v:103721.9-103721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160141,168 +161817,168 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:102643.3-102691.6" - process $proc$libresoc.v:102643$4104 + attribute \src "libresoc.v:103769.3-103817.6" + process $proc$libresoc.v:103769$4134 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:102644.5-102644.29" + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:103770.5-103770.29" switch \initial - attribute \src "libresoc.v:102644.9-102644.17" + attribute \src "libresoc.v:103770.9-103770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:102692.3-102740.6" - process $proc$libresoc.v:102692$4105 + attribute \src "libresoc.v:103818.3-103866.6" + process $proc$libresoc.v:103818$4135 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102693.5-102693.29" + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:103819.5-103819.29" switch \initial - attribute \src "libresoc.v:102693.9-102693.17" + attribute \src "libresoc.v:103819.9-103819.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 end sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:102741.3-102789.6" - process $proc$libresoc.v:102741$4106 + attribute \src "libresoc.v:103867.3-103915.6" + process $proc$libresoc.v:103867$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:102742.5-102742.29" + attribute \src "libresoc.v:103868.5-103868.29" switch \initial - attribute \src "libresoc.v:102742.9-102742.17" + attribute \src "libresoc.v:103868.9-103868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160366,18 +162042,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:102790.3-102838.6" - process $proc$libresoc.v:102790$4107 + attribute \src "libresoc.v:103916.3-103964.6" + process $proc$libresoc.v:103916$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102791.5-102791.29" + attribute \src "libresoc.v:103917.5-103917.29" switch \initial - attribute \src "libresoc.v:102791.9-102791.17" + attribute \src "libresoc.v:103917.9-103917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160441,18 +162117,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:102839.3-102887.6" - process $proc$libresoc.v:102839$4108 + attribute \src "libresoc.v:103965.3-104013.6" + process $proc$libresoc.v:103965$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102840.5-102840.29" + attribute \src "libresoc.v:103966.5-103966.29" switch \initial - attribute \src "libresoc.v:102840.9-102840.17" + attribute \src "libresoc.v:103966.9-103966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160516,18 +162192,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:102888.3-102936.6" - process $proc$libresoc.v:102888$4109 + attribute \src "libresoc.v:104014.3-104062.6" + process $proc$libresoc.v:104014$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:102889.5-102889.29" + attribute \src "libresoc.v:104015.5-104015.29" switch \initial - attribute \src "libresoc.v:102889.9-102889.17" + attribute \src "libresoc.v:104015.9-104015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160591,18 +162267,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:102937.3-102985.6" - process $proc$libresoc.v:102937$4110 + attribute \src "libresoc.v:104063.3-104111.6" + process $proc$libresoc.v:104063$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:102938.5-102938.29" + attribute \src "libresoc.v:104064.5-104064.29" switch \initial - attribute \src "libresoc.v:102938.9-102938.17" + attribute \src "libresoc.v:104064.9-104064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160666,18 +162342,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:102986.3-103034.6" - process $proc$libresoc.v:102986$4111 + attribute \src "libresoc.v:104112.3-104160.6" + process $proc$libresoc.v:104112$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102987.5-102987.29" + attribute \src "libresoc.v:104113.5-104113.29" switch \initial - attribute \src "libresoc.v:102987.9-102987.17" + attribute \src "libresoc.v:104113.9-104113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160741,18 +162417,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:103035.3-103083.6" - process $proc$libresoc.v:103035$4112 + attribute \src "libresoc.v:104161.3-104209.6" + process $proc$libresoc.v:104161$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103036.5-103036.29" + attribute \src "libresoc.v:104162.5-104162.29" switch \initial - attribute \src "libresoc.v:103036.9-103036.17" + attribute \src "libresoc.v:104162.9-104162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160816,18 +162492,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:103084.3-103132.6" - process $proc$libresoc.v:103084$4113 + attribute \src "libresoc.v:104210.3-104258.6" + process $proc$libresoc.v:104210$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103085.5-103085.29" + attribute \src "libresoc.v:104211.5-104211.29" switch \initial - attribute \src "libresoc.v:103085.9-103085.17" + attribute \src "libresoc.v:104211.9-104211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160891,18 +162567,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:103133.3-103181.6" - process $proc$libresoc.v:103133$4114 + attribute \src "libresoc.v:104259.3-104307.6" + process $proc$libresoc.v:104259$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103134.5-103134.29" + attribute \src "libresoc.v:104260.5-104260.29" switch \initial - attribute \src "libresoc.v:103134.9-103134.17" + attribute \src "libresoc.v:104260.9-104260.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160966,168 +162642,168 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:103182.3-103230.6" - process $proc$libresoc.v:103182$4115 + attribute \src "libresoc.v:104308.3-104356.6" + process $proc$libresoc.v:104308$4145 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103183.5-103183.29" + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:104309.5-104309.29" switch \initial - attribute \src "libresoc.v:103183.9-103183.17" + attribute \src "libresoc.v:104309.9-104309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'00000 end sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:103231.3-103279.6" - process $proc$libresoc.v:103231$4116 + attribute \src "libresoc.v:104357.3-104405.6" + process $proc$libresoc.v:104357$4146 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103232.5-103232.29" + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:104358.5-104358.29" switch \initial - attribute \src "libresoc.v:103232.9-103232.17" + attribute \src "libresoc.v:104358.9-104358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:103280.3-103328.6" - process $proc$libresoc.v:103280$4117 + attribute \src "libresoc.v:104406.3-104454.6" + process $proc$libresoc.v:104406$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103281.5-103281.29" + attribute \src "libresoc.v:104407.5-104407.29" switch \initial - attribute \src "libresoc.v:103281.9-103281.17" + attribute \src "libresoc.v:104407.9-104407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161191,18 +162867,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:103329.3-103377.6" - process $proc$libresoc.v:103329$4118 + attribute \src "libresoc.v:104455.3-104503.6" + process $proc$libresoc.v:104455$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103330.5-103330.29" + attribute \src "libresoc.v:104456.5-104456.29" switch \initial - attribute \src "libresoc.v:103330.9-103330.17" + attribute \src "libresoc.v:104456.9-104456.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161266,18 +162942,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:103378.3-103408.6" - process $proc$libresoc.v:103378$4119 + attribute \src "libresoc.v:104504.3-104534.6" + process $proc$libresoc.v:104504$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:103379.5-103379.29" + attribute \src "libresoc.v:104505.5-104505.29" switch \initial - attribute \src "libresoc.v:103379.9-103379.17" + attribute \src "libresoc.v:104505.9-104505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -161317,18 +162993,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:103409.3-103457.6" - process $proc$libresoc.v:103409$4120 + attribute \src "libresoc.v:104535.3-104583.6" + process $proc$libresoc.v:104535$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103410.5-103410.29" + attribute \src "libresoc.v:104536.5-104536.29" switch \initial - attribute \src "libresoc.v:103410.9-103410.17" + attribute \src "libresoc.v:104536.9-104536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161392,18 +163068,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:103458.3-103506.6" - process $proc$libresoc.v:103458$4121 + attribute \src "libresoc.v:104584.3-104632.6" + process $proc$libresoc.v:104584$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103459.5-103459.29" + attribute \src "libresoc.v:104585.5-104585.29" switch \initial - attribute \src "libresoc.v:103459.9-103459.17" + attribute \src "libresoc.v:104585.9-104585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161467,18 +163143,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:103507.3-103555.6" - process $proc$libresoc.v:103507$4122 + attribute \src "libresoc.v:104633.3-104681.6" + process $proc$libresoc.v:104633$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103508.5-103508.29" + attribute \src "libresoc.v:104634.5-104634.29" switch \initial - attribute \src "libresoc.v:103508.9-103508.17" + attribute \src "libresoc.v:104634.9-104634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161542,18 +163218,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:103556.3-103604.6" - process $proc$libresoc.v:103556$4123 + attribute \src "libresoc.v:104682.3-104730.6" + process $proc$libresoc.v:104682$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103557.5-103557.29" + attribute \src "libresoc.v:104683.5-104683.29" switch \initial - attribute \src "libresoc.v:103557.9-103557.17" + attribute \src "libresoc.v:104683.9-104683.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161617,18 +163293,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:103605.3-103653.6" - process $proc$libresoc.v:103605$4124 + attribute \src "libresoc.v:104731.3-104779.6" + process $proc$libresoc.v:104731$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103606.5-103606.29" + attribute \src "libresoc.v:104732.5-104732.29" switch \initial - attribute \src "libresoc.v:103606.9-103606.17" + attribute \src "libresoc.v:104732.9-104732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161692,18 +163368,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:103654.3-103702.6" - process $proc$libresoc.v:103654$4125 + attribute \src "libresoc.v:104780.3-104828.6" + process $proc$libresoc.v:104780$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103655.5-103655.29" + attribute \src "libresoc.v:104781.5-104781.29" switch \initial - attribute \src "libresoc.v:103655.9-103655.17" + attribute \src "libresoc.v:104781.9-104781.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161769,157 +163445,161 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:103708.1-105808.10" +attribute \src "libresoc.v:104834.1-106999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:105477.3-105531.6" + attribute \src "libresoc.v:106668.3-106722.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105532.3-105586.6" + attribute \src "libresoc.v:106723.3-106777.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104817.3-104871.6" + attribute \src "libresoc.v:106008.3-106062.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:105037.3-105091.6" + attribute \src "libresoc.v:106228.3-106282.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:104102.3-104156.6" + attribute \src "libresoc.v:105238.3-105292.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104157.3-104211.6" + attribute \src "libresoc.v:105293.3-105347.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104762.3-104816.6" + attribute \src "libresoc.v:105953.3-106007.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104982.3-105036.6" + attribute \src "libresoc.v:106173.3-106227.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:105257.3-105311.6" + attribute \src "libresoc.v:106393.3-106447.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:104047.3-104101.6" + attribute \src "libresoc.v:105183.3-105237.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105587.3-105641.6" + attribute \src "libresoc.v:106778.3-106832.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105642.3-105696.6" + attribute \src "libresoc.v:106833.3-106887.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105697.3-105751.6" + attribute \src "libresoc.v:106888.3-106942.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104652.3-104706.6" + attribute \src "libresoc.v:105788.3-105842.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104872.3-104926.6" + attribute \src "libresoc.v:106063.3-106117.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104927.3-104981.6" + attribute \src "libresoc.v:106118.3-106172.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:105202.3-105256.6" + attribute \src "libresoc.v:106448.3-106502.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:104542.3-104596.6" + attribute \src "libresoc.v:105733.3-105787.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105367.3-105421.6" + attribute \src "libresoc.v:106558.3-106612.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105752.3-105806.6" + attribute \src "libresoc.v:106943.3-106997.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:104707.3-104761.6" + attribute \src "libresoc.v:105898.3-105952.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105147.3-105201.6" + attribute \src "libresoc.v:106338.3-106392.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105422.3-105476.6" + attribute \src "libresoc.v:106613.3-106667.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105312.3-105366.6" + attribute \src "libresoc.v:106503.3-106557.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105092.3-105146.6" + attribute \src "libresoc.v:106283.3-106337.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:104432.3-104486.6" + attribute \src "libresoc.v:105623.3-105677.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104487.3-104541.6" + attribute \src "libresoc.v:105678.3-105732.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104212.3-104266.6" + attribute \src "libresoc.v:105348.3-105402.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104267.3-104321.6" + attribute \src "libresoc.v:105403.3-105457.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104322.3-104376.6" + attribute \src "libresoc.v:105458.3-105512.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104377.3-104431.6" + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104597.3-104651.6" + attribute \src "libresoc.v:105843.3-105897.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:103709.7-103709.20" + attribute \src "libresoc.v:104835.7-104835.20" wire $0\initial[0:0] - attribute \src "libresoc.v:105477.3-105531.6" + attribute \src "libresoc.v:106668.3-106722.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105532.3-105586.6" + attribute \src "libresoc.v:106723.3-106777.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104817.3-104871.6" + attribute \src "libresoc.v:106008.3-106062.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:105037.3-105091.6" + attribute \src "libresoc.v:106228.3-106282.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:104102.3-104156.6" + attribute \src "libresoc.v:105238.3-105292.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104157.3-104211.6" + attribute \src "libresoc.v:105293.3-105347.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104762.3-104816.6" + attribute \src "libresoc.v:105953.3-106007.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104982.3-105036.6" + attribute \src "libresoc.v:106173.3-106227.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:105257.3-105311.6" + attribute \src "libresoc.v:106393.3-106447.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:104047.3-104101.6" + attribute \src "libresoc.v:105183.3-105237.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105587.3-105641.6" + attribute \src "libresoc.v:106778.3-106832.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105642.3-105696.6" + attribute \src "libresoc.v:106833.3-106887.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105697.3-105751.6" + attribute \src "libresoc.v:106888.3-106942.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104652.3-104706.6" + attribute \src "libresoc.v:105788.3-105842.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104872.3-104926.6" + attribute \src "libresoc.v:106063.3-106117.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104927.3-104981.6" + attribute \src "libresoc.v:106118.3-106172.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:105202.3-105256.6" + attribute \src "libresoc.v:106448.3-106502.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:104542.3-104596.6" + attribute \src "libresoc.v:105733.3-105787.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105367.3-105421.6" + attribute \src "libresoc.v:106558.3-106612.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105752.3-105806.6" + attribute \src "libresoc.v:106943.3-106997.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:104707.3-104761.6" + attribute \src "libresoc.v:105898.3-105952.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105147.3-105201.6" + attribute \src "libresoc.v:106338.3-106392.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105422.3-105476.6" + attribute \src "libresoc.v:106613.3-106667.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105312.3-105366.6" + attribute \src "libresoc.v:106503.3-106557.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105092.3-105146.6" + attribute \src "libresoc.v:106283.3-106337.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:104432.3-104486.6" + attribute \src "libresoc.v:105623.3-105677.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104487.3-104541.6" + attribute \src "libresoc.v:105678.3-105732.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104212.3-104266.6" + attribute \src "libresoc.v:105348.3-105402.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104267.3-104321.6" + attribute \src "libresoc.v:105403.3-105457.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104322.3-104376.6" + attribute \src "libresoc.v:105458.3-105512.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104377.3-104431.6" + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104597.3-104651.6" + attribute \src "libresoc.v:105843.3-105897.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -161929,7 +163609,7 @@ module \dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -161938,16 +163618,16 @@ module \dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -161979,7 +163659,7 @@ module \dec31_dec_sub22 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -161996,7 +163676,7 @@ module \dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -162004,7 +163684,7 @@ module \dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -162021,13 +163701,13 @@ module \dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -162104,46 +163784,46 @@ module \dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162151,8 +163831,8 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub22_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162160,8 +163840,8 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub22_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162169,7 +163849,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162178,7 +163858,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162187,7 +163867,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162196,41 +163876,50 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub22_upd - attribute \src "libresoc.v:103709.7-103709.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub22_upd + attribute \src "libresoc.v:104835.7-104835.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:103709.7-103709.20" - process $proc$libresoc.v:103709$4159 + attribute \src "libresoc.v:104835.7-104835.20" + process $proc$libresoc.v:104835$4190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:104047.3-104101.6" - process $proc$libresoc.v:104047$4127 + attribute \src "libresoc.v:105183.3-105237.6" + process $proc$libresoc.v:105183$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:104048.5-104048.29" + attribute \src "libresoc.v:105184.5-105184.29" switch \initial - attribute \src "libresoc.v:104048.9-104048.17" + attribute \src "libresoc.v:105184.9-105184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162302,18 +163991,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:104102.3-104156.6" - process $proc$libresoc.v:104102$4128 + attribute \src "libresoc.v:105238.3-105292.6" + process $proc$libresoc.v:105238$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104103.5-104103.29" + attribute \src "libresoc.v:105239.5-105239.29" switch \initial - attribute \src "libresoc.v:104103.9-104103.17" + attribute \src "libresoc.v:105239.9-105239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162385,18 +164074,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:104157.3-104211.6" - process $proc$libresoc.v:104157$4129 + attribute \src "libresoc.v:105293.3-105347.6" + process $proc$libresoc.v:105293$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104158.5-104158.29" + attribute \src "libresoc.v:105294.5-105294.29" switch \initial - attribute \src "libresoc.v:104158.9-104158.17" + attribute \src "libresoc.v:105294.9-105294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162468,18 +164157,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:104212.3-104266.6" - process $proc$libresoc.v:104212$4130 + attribute \src "libresoc.v:105348.3-105402.6" + process $proc$libresoc.v:105348$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104213.5-104213.29" + attribute \src "libresoc.v:105349.5-105349.29" switch \initial - attribute \src "libresoc.v:104213.9-104213.17" + attribute \src "libresoc.v:105349.9-105349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162551,18 +164240,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:104267.3-104321.6" - process $proc$libresoc.v:104267$4131 + attribute \src "libresoc.v:105403.3-105457.6" + process $proc$libresoc.v:105403$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104268.5-104268.29" + attribute \src "libresoc.v:105404.5-105404.29" switch \initial - attribute \src "libresoc.v:104268.9-104268.17" + attribute \src "libresoc.v:105404.9-105404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162634,18 +164323,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:104322.3-104376.6" - process $proc$libresoc.v:104322$4132 + attribute \src "libresoc.v:105458.3-105512.6" + process $proc$libresoc.v:105458$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104323.5-104323.29" + attribute \src "libresoc.v:105459.5-105459.29" switch \initial - attribute \src "libresoc.v:104323.9-104323.17" + attribute \src "libresoc.v:105459.9-105459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162717,18 +164406,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:104377.3-104431.6" - process $proc$libresoc.v:104377$4133 + attribute \src "libresoc.v:105513.3-105567.6" + process $proc$libresoc.v:105513$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104378.5-104378.29" + attribute \src "libresoc.v:105514.5-105514.29" switch \initial - attribute \src "libresoc.v:104378.9-104378.17" + attribute \src "libresoc.v:105514.9-105514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162800,18 +164489,101 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:104432.3-104486.6" - process $proc$libresoc.v:104432$4134 + attribute \src "libresoc.v:105568.3-105622.6" + process $proc$libresoc.v:105568$4164 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105569.5-105569.29" + switch \initial + attribute \src "libresoc.v:105569.9-105569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] + end + attribute \src "libresoc.v:105623.3-105677.6" + process $proc$libresoc.v:105623$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104433.5-104433.29" + attribute \src "libresoc.v:105624.5-105624.29" switch \initial - attribute \src "libresoc.v:104433.9-104433.17" + attribute \src "libresoc.v:105624.9-105624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162883,18 +164655,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:104487.3-104541.6" - process $proc$libresoc.v:104487$4135 + attribute \src "libresoc.v:105678.3-105732.6" + process $proc$libresoc.v:105678$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104488.5-104488.29" + attribute \src "libresoc.v:105679.5-105679.29" switch \initial - attribute \src "libresoc.v:104488.9-104488.17" + attribute \src "libresoc.v:105679.9-105679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162966,18 +164738,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:104542.3-104596.6" - process $proc$libresoc.v:104542$4136 + attribute \src "libresoc.v:105733.3-105787.6" + process $proc$libresoc.v:105733$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:104543.5-104543.29" + attribute \src "libresoc.v:105734.5-105734.29" switch \initial - attribute \src "libresoc.v:104543.9-104543.17" + attribute \src "libresoc.v:105734.9-105734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163049,184 +164821,184 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:104597.3-104651.6" - process $proc$libresoc.v:104597$4137 + attribute \src "libresoc.v:105788.3-105842.6" + process $proc$libresoc.v:105788$4168 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:104598.5-104598.29" + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:105789.5-105789.29" switch \initial - attribute \src "libresoc.v:104598.9-104598.17" + attribute \src "libresoc.v:105789.9-105789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:104652.3-104706.6" - process $proc$libresoc.v:104652$4138 + attribute \src "libresoc.v:105843.3-105897.6" + process $proc$libresoc.v:105843$4169 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104653.5-104653.29" + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:105844.5-105844.29" switch \initial - attribute \src "libresoc.v:104653.9-104653.17" + attribute \src "libresoc.v:105844.9-105844.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 end sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:104707.3-104761.6" - process $proc$libresoc.v:104707$4139 + attribute \src "libresoc.v:105898.3-105952.6" + process $proc$libresoc.v:105898$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:104708.5-104708.29" + attribute \src "libresoc.v:105899.5-105899.29" switch \initial - attribute \src "libresoc.v:104708.9-104708.17" + attribute \src "libresoc.v:105899.9-105899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163298,18 +165070,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:104762.3-104816.6" - process $proc$libresoc.v:104762$4140 + attribute \src "libresoc.v:105953.3-106007.6" + process $proc$libresoc.v:105953$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104763.5-104763.29" + attribute \src "libresoc.v:105954.5-105954.29" switch \initial - attribute \src "libresoc.v:104763.9-104763.17" + attribute \src "libresoc.v:105954.9-105954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163381,18 +165153,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:104817.3-104871.6" - process $proc$libresoc.v:104817$4141 + attribute \src "libresoc.v:106008.3-106062.6" + process $proc$libresoc.v:106008$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:104818.5-104818.29" + attribute \src "libresoc.v:106009.5-106009.29" switch \initial - attribute \src "libresoc.v:104818.9-104818.17" + attribute \src "libresoc.v:106009.9-106009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163464,18 +165236,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:104872.3-104926.6" - process $proc$libresoc.v:104872$4142 + attribute \src "libresoc.v:106063.3-106117.6" + process $proc$libresoc.v:106063$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104873.5-104873.29" + attribute \src "libresoc.v:106064.5-106064.29" switch \initial - attribute \src "libresoc.v:104873.9-104873.17" + attribute \src "libresoc.v:106064.9-106064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163547,18 +165319,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:104927.3-104981.6" - process $proc$libresoc.v:104927$4143 + attribute \src "libresoc.v:106118.3-106172.6" + process $proc$libresoc.v:106118$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:104928.5-104928.29" + attribute \src "libresoc.v:106119.5-106119.29" switch \initial - attribute \src "libresoc.v:104928.9-104928.17" + attribute \src "libresoc.v:106119.9-106119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163630,18 +165402,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:104982.3-105036.6" - process $proc$libresoc.v:104982$4144 + attribute \src "libresoc.v:106173.3-106227.6" + process $proc$libresoc.v:106173$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:104983.5-104983.29" + attribute \src "libresoc.v:106174.5-106174.29" switch \initial - attribute \src "libresoc.v:104983.9-104983.17" + attribute \src "libresoc.v:106174.9-106174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163713,18 +165485,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:105037.3-105091.6" - process $proc$libresoc.v:105037$4145 + attribute \src "libresoc.v:106228.3-106282.6" + process $proc$libresoc.v:106228$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105038.5-105038.29" + attribute \src "libresoc.v:106229.5-106229.29" switch \initial - attribute \src "libresoc.v:105038.9-105038.17" + attribute \src "libresoc.v:106229.9-106229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163796,18 +165568,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:105092.3-105146.6" - process $proc$libresoc.v:105092$4146 + attribute \src "libresoc.v:106283.3-106337.6" + process $proc$libresoc.v:106283$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105093.5-105093.29" + attribute \src "libresoc.v:106284.5-106284.29" switch \initial - attribute \src "libresoc.v:105093.9-105093.17" + attribute \src "libresoc.v:106284.9-106284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163879,18 +165651,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:105147.3-105201.6" - process $proc$libresoc.v:105147$4147 + attribute \src "libresoc.v:106338.3-106392.6" + process $proc$libresoc.v:106338$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105148.5-105148.29" + attribute \src "libresoc.v:106339.5-106339.29" switch \initial - attribute \src "libresoc.v:105148.9-105148.17" + attribute \src "libresoc.v:106339.9-106339.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163962,184 +165734,184 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:105202.3-105256.6" - process $proc$libresoc.v:105202$4148 + attribute \src "libresoc.v:106393.3-106447.6" + process $proc$libresoc.v:106393$4179 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105203.5-105203.29" + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:106394.5-106394.29" switch \initial - attribute \src "libresoc.v:105203.9-105203.17" + attribute \src "libresoc.v:106394.9-106394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'00000 end sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:105257.3-105311.6" - process $proc$libresoc.v:105257$4149 + attribute \src "libresoc.v:106448.3-106502.6" + process $proc$libresoc.v:106448$4180 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105258.5-105258.29" + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:106449.5-106449.29" switch \initial - attribute \src "libresoc.v:105258.9-105258.17" + attribute \src "libresoc.v:106449.9-106449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:105312.3-105366.6" - process $proc$libresoc.v:105312$4150 + attribute \src "libresoc.v:106503.3-106557.6" + process $proc$libresoc.v:106503$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105313.5-105313.29" + attribute \src "libresoc.v:106504.5-106504.29" switch \initial - attribute \src "libresoc.v:105313.9-105313.17" + attribute \src "libresoc.v:106504.9-106504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164211,18 +165983,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:105367.3-105421.6" - process $proc$libresoc.v:105367$4151 + attribute \src "libresoc.v:106558.3-106612.6" + process $proc$libresoc.v:106558$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105368.5-105368.29" + attribute \src "libresoc.v:106559.5-106559.29" switch \initial - attribute \src "libresoc.v:105368.9-105368.17" + attribute \src "libresoc.v:106559.9-106559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164294,18 +166066,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:105422.3-105476.6" - process $proc$libresoc.v:105422$4152 + attribute \src "libresoc.v:106613.3-106667.6" + process $proc$libresoc.v:106613$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105423.5-105423.29" + attribute \src "libresoc.v:106614.5-106614.29" switch \initial - attribute \src "libresoc.v:105423.9-105423.17" + attribute \src "libresoc.v:106614.9-106614.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164377,18 +166149,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:105477.3-105531.6" - process $proc$libresoc.v:105477$4153 + attribute \src "libresoc.v:106668.3-106722.6" + process $proc$libresoc.v:106668$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105478.5-105478.29" + attribute \src "libresoc.v:106669.5-106669.29" switch \initial - attribute \src "libresoc.v:105478.9-105478.17" + attribute \src "libresoc.v:106669.9-106669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164460,18 +166232,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:105532.3-105586.6" - process $proc$libresoc.v:105532$4154 + attribute \src "libresoc.v:106723.3-106777.6" + process $proc$libresoc.v:106723$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:105533.5-105533.29" + attribute \src "libresoc.v:106724.5-106724.29" switch \initial - attribute \src "libresoc.v:105533.9-105533.17" + attribute \src "libresoc.v:106724.9-106724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164543,18 +166315,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:105587.3-105641.6" - process $proc$libresoc.v:105587$4155 + attribute \src "libresoc.v:106778.3-106832.6" + process $proc$libresoc.v:106778$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105588.5-105588.29" + attribute \src "libresoc.v:106779.5-106779.29" switch \initial - attribute \src "libresoc.v:105588.9-105588.17" + attribute \src "libresoc.v:106779.9-106779.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164626,18 +166398,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:105642.3-105696.6" - process $proc$libresoc.v:105642$4156 + attribute \src "libresoc.v:106833.3-106887.6" + process $proc$libresoc.v:106833$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105643.5-105643.29" + attribute \src "libresoc.v:106834.5-106834.29" switch \initial - attribute \src "libresoc.v:105643.9-105643.17" + attribute \src "libresoc.v:106834.9-106834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164709,18 +166481,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:105697.3-105751.6" - process $proc$libresoc.v:105697$4157 + attribute \src "libresoc.v:106888.3-106942.6" + process $proc$libresoc.v:106888$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105698.5-105698.29" + attribute \src "libresoc.v:106889.5-106889.29" switch \initial - attribute \src "libresoc.v:105698.9-105698.17" + attribute \src "libresoc.v:106889.9-106889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164792,18 +166564,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:105752.3-105806.6" - process $proc$libresoc.v:105752$4158 + attribute \src "libresoc.v:106943.3-106997.6" + process $proc$libresoc.v:106943$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105753.5-105753.29" + attribute \src "libresoc.v:106944.5-106944.29" switch \initial - attribute \src "libresoc.v:105753.9-105753.17" + attribute \src "libresoc.v:106944.9-106944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164877,157 +166649,161 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:105812.1-107720.10" +attribute \src "libresoc.v:107003.1-108970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:107425.3-107473.6" + attribute \src "libresoc.v:108675.3-108723.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107474.3-107522.6" + attribute \src "libresoc.v:108724.3-108772.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106837.3-106885.6" + attribute \src "libresoc.v:108087.3-108135.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:107033.3-107081.6" + attribute \src "libresoc.v:108283.3-108331.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:106200.3-106248.6" + attribute \src "libresoc.v:107401.3-107449.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106249.3-106297.6" + attribute \src "libresoc.v:107450.3-107498.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106788.3-106836.6" + attribute \src "libresoc.v:108038.3-108086.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106984.3-107032.6" + attribute \src "libresoc.v:108234.3-108282.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:107229.3-107277.6" + attribute \src "libresoc.v:108430.3-108478.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:106151.3-106199.6" + attribute \src "libresoc.v:107352.3-107400.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107523.3-107571.6" + attribute \src "libresoc.v:108773.3-108821.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107572.3-107620.6" + attribute \src "libresoc.v:108822.3-108870.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107621.3-107669.6" + attribute \src "libresoc.v:108871.3-108919.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106690.3-106738.6" + attribute \src "libresoc.v:107891.3-107939.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106886.3-106934.6" + attribute \src "libresoc.v:108136.3-108184.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106935.3-106983.6" + attribute \src "libresoc.v:108185.3-108233.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:107180.3-107228.6" + attribute \src "libresoc.v:108479.3-108527.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:106592.3-106640.6" + attribute \src "libresoc.v:107842.3-107890.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107327.3-107375.6" + attribute \src "libresoc.v:108577.3-108625.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107670.3-107718.6" + attribute \src "libresoc.v:108920.3-108968.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:106739.3-106787.6" + attribute \src "libresoc.v:107989.3-108037.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107131.3-107179.6" + attribute \src "libresoc.v:108381.3-108429.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107376.3-107424.6" + attribute \src "libresoc.v:108626.3-108674.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107278.3-107326.6" + attribute \src "libresoc.v:108528.3-108576.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107082.3-107130.6" + attribute \src "libresoc.v:108332.3-108380.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:106494.3-106542.6" + attribute \src "libresoc.v:107744.3-107792.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106543.3-106591.6" + attribute \src "libresoc.v:107793.3-107841.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106298.3-106346.6" + attribute \src "libresoc.v:107499.3-107547.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106347.3-106395.6" + attribute \src "libresoc.v:107548.3-107596.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106396.3-106444.6" + attribute \src "libresoc.v:107597.3-107645.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106445.3-106493.6" + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106641.3-106689.6" + attribute \src "libresoc.v:107940.3-107988.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:105813.7-105813.20" + attribute \src "libresoc.v:107004.7-107004.20" wire $0\initial[0:0] - attribute \src "libresoc.v:107425.3-107473.6" + attribute \src "libresoc.v:108675.3-108723.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107474.3-107522.6" + attribute \src "libresoc.v:108724.3-108772.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106837.3-106885.6" + attribute \src "libresoc.v:108087.3-108135.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:107033.3-107081.6" + attribute \src "libresoc.v:108283.3-108331.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:106200.3-106248.6" + attribute \src "libresoc.v:107401.3-107449.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106249.3-106297.6" + attribute \src "libresoc.v:107450.3-107498.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106788.3-106836.6" + attribute \src "libresoc.v:108038.3-108086.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106984.3-107032.6" + attribute \src "libresoc.v:108234.3-108282.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:107229.3-107277.6" + attribute \src "libresoc.v:108430.3-108478.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:106151.3-106199.6" + attribute \src "libresoc.v:107352.3-107400.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107523.3-107571.6" + attribute \src "libresoc.v:108773.3-108821.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107572.3-107620.6" + attribute \src "libresoc.v:108822.3-108870.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107621.3-107669.6" + attribute \src "libresoc.v:108871.3-108919.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106690.3-106738.6" + attribute \src "libresoc.v:107891.3-107939.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106886.3-106934.6" + attribute \src "libresoc.v:108136.3-108184.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106935.3-106983.6" + attribute \src "libresoc.v:108185.3-108233.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:107180.3-107228.6" + attribute \src "libresoc.v:108479.3-108527.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:106592.3-106640.6" + attribute \src "libresoc.v:107842.3-107890.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107327.3-107375.6" + attribute \src "libresoc.v:108577.3-108625.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107670.3-107718.6" + attribute \src "libresoc.v:108920.3-108968.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:106739.3-106787.6" + attribute \src "libresoc.v:107989.3-108037.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107131.3-107179.6" + attribute \src "libresoc.v:108381.3-108429.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107376.3-107424.6" + attribute \src "libresoc.v:108626.3-108674.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107278.3-107326.6" + attribute \src "libresoc.v:108528.3-108576.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107082.3-107130.6" + attribute \src "libresoc.v:108332.3-108380.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:106494.3-106542.6" + attribute \src "libresoc.v:107744.3-107792.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106543.3-106591.6" + attribute \src "libresoc.v:107793.3-107841.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106298.3-106346.6" + attribute \src "libresoc.v:107499.3-107547.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106347.3-106395.6" + attribute \src "libresoc.v:107548.3-107596.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106396.3-106444.6" + attribute \src "libresoc.v:107597.3-107645.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106445.3-106493.6" + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106641.3-106689.6" + attribute \src "libresoc.v:107940.3-107988.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub23_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub23_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub23_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -165037,7 +166813,7 @@ module \dec31_dec_sub23 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165046,16 +166822,16 @@ module \dec31_dec_sub23 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub23_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -165087,7 +166863,7 @@ module \dec31_dec_sub23 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -165104,7 +166880,7 @@ module \dec31_dec_sub23 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -165112,7 +166888,7 @@ module \dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -165129,13 +166905,13 @@ module \dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -165212,46 +166988,46 @@ module \dec31_dec_sub23 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub23_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub23_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub23_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165259,8 +167035,8 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub23_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub23_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165268,8 +167044,8 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub23_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub23_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165277,7 +167053,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub23_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165286,7 +167062,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub23_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165295,7 +167071,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub23_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165304,41 +167080,50 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub23_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub23_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub23_upd - attribute \src "libresoc.v:105813.7-105813.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub23_upd + attribute \src "libresoc.v:107004.7-107004.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:105813.7-105813.20" - process $proc$libresoc.v:105813$4192 + attribute \src "libresoc.v:107004.7-107004.20" + process $proc$libresoc.v:107004$4224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:106151.3-106199.6" - process $proc$libresoc.v:106151$4160 + attribute \src "libresoc.v:107352.3-107400.6" + process $proc$libresoc.v:107352$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:106152.5-106152.29" + attribute \src "libresoc.v:107353.5-107353.29" switch \initial - attribute \src "libresoc.v:106152.9-106152.17" + attribute \src "libresoc.v:107353.9-107353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165402,18 +167187,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:106200.3-106248.6" - process $proc$libresoc.v:106200$4161 + attribute \src "libresoc.v:107401.3-107449.6" + process $proc$libresoc.v:107401$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106201.5-106201.29" + attribute \src "libresoc.v:107402.5-107402.29" switch \initial - attribute \src "libresoc.v:106201.9-106201.17" + attribute \src "libresoc.v:107402.9-107402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165477,18 +167262,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:106249.3-106297.6" - process $proc$libresoc.v:106249$4162 + attribute \src "libresoc.v:107450.3-107498.6" + process $proc$libresoc.v:107450$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106250.5-106250.29" + attribute \src "libresoc.v:107451.5-107451.29" switch \initial - attribute \src "libresoc.v:106250.9-106250.17" + attribute \src "libresoc.v:107451.9-107451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165552,18 +167337,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:106298.3-106346.6" - process $proc$libresoc.v:106298$4163 + attribute \src "libresoc.v:107499.3-107547.6" + process $proc$libresoc.v:107499$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106299.5-106299.29" + attribute \src "libresoc.v:107500.5-107500.29" switch \initial - attribute \src "libresoc.v:106299.9-106299.17" + attribute \src "libresoc.v:107500.9-107500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165627,18 +167412,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:106347.3-106395.6" - process $proc$libresoc.v:106347$4164 + attribute \src "libresoc.v:107548.3-107596.6" + process $proc$libresoc.v:107548$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106348.5-106348.29" + attribute \src "libresoc.v:107549.5-107549.29" switch \initial - attribute \src "libresoc.v:106348.9-106348.17" + attribute \src "libresoc.v:107549.9-107549.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165702,18 +167487,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:106396.3-106444.6" - process $proc$libresoc.v:106396$4165 + attribute \src "libresoc.v:107597.3-107645.6" + process $proc$libresoc.v:107597$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106397.5-106397.29" + attribute \src "libresoc.v:107598.5-107598.29" switch \initial - attribute \src "libresoc.v:106397.9-106397.17" + attribute \src "libresoc.v:107598.9-107598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165777,18 +167562,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:106445.3-106493.6" - process $proc$libresoc.v:106445$4166 + attribute \src "libresoc.v:107646.3-107694.6" + process $proc$libresoc.v:107646$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106446.5-106446.29" + attribute \src "libresoc.v:107647.5-107647.29" switch \initial - attribute \src "libresoc.v:106446.9-106446.17" + attribute \src "libresoc.v:107647.9-107647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165852,18 +167637,93 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:106494.3-106542.6" - process $proc$libresoc.v:106494$4167 + attribute \src "libresoc.v:107695.3-107743.6" + process $proc$libresoc.v:107695$4198 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107696.5-107696.29" + switch \initial + attribute \src "libresoc.v:107696.9-107696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] + end + attribute \src "libresoc.v:107744.3-107792.6" + process $proc$libresoc.v:107744$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106495.5-106495.29" + attribute \src "libresoc.v:107745.5-107745.29" switch \initial - attribute \src "libresoc.v:106495.9-106495.17" + attribute \src "libresoc.v:107745.9-107745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165927,18 +167787,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:106543.3-106591.6" - process $proc$libresoc.v:106543$4168 + attribute \src "libresoc.v:107793.3-107841.6" + process $proc$libresoc.v:107793$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106544.5-106544.29" + attribute \src "libresoc.v:107794.5-107794.29" switch \initial - attribute \src "libresoc.v:106544.9-106544.17" + attribute \src "libresoc.v:107794.9-107794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166002,18 +167862,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:106592.3-106640.6" - process $proc$libresoc.v:106592$4169 + attribute \src "libresoc.v:107842.3-107890.6" + process $proc$libresoc.v:107842$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:106593.5-106593.29" + attribute \src "libresoc.v:107843.5-107843.29" switch \initial - attribute \src "libresoc.v:106593.9-106593.17" + attribute \src "libresoc.v:107843.9-107843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166077,168 +167937,168 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:106641.3-106689.6" - process $proc$libresoc.v:106641$4170 + attribute \src "libresoc.v:107891.3-107939.6" + process $proc$libresoc.v:107891$4202 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:106642.5-106642.29" + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:107892.5-107892.29" switch \initial - attribute \src "libresoc.v:106642.9-106642.17" + attribute \src "libresoc.v:107892.9-107892.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:106690.3-106738.6" - process $proc$libresoc.v:106690$4171 + attribute \src "libresoc.v:107940.3-107988.6" + process $proc$libresoc.v:107940$4203 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106691.5-106691.29" + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:107941.5-107941.29" switch \initial - attribute \src "libresoc.v:106691.9-106691.17" + attribute \src "libresoc.v:107941.9-107941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 end sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:106739.3-106787.6" - process $proc$libresoc.v:106739$4172 + attribute \src "libresoc.v:107989.3-108037.6" + process $proc$libresoc.v:107989$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:106740.5-106740.29" + attribute \src "libresoc.v:107990.5-107990.29" switch \initial - attribute \src "libresoc.v:106740.9-106740.17" + attribute \src "libresoc.v:107990.9-107990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166302,18 +168162,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:106788.3-106836.6" - process $proc$libresoc.v:106788$4173 + attribute \src "libresoc.v:108038.3-108086.6" + process $proc$libresoc.v:108038$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106789.5-106789.29" + attribute \src "libresoc.v:108039.5-108039.29" switch \initial - attribute \src "libresoc.v:106789.9-106789.17" + attribute \src "libresoc.v:108039.9-108039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166377,18 +168237,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:106837.3-106885.6" - process $proc$libresoc.v:106837$4174 + attribute \src "libresoc.v:108087.3-108135.6" + process $proc$libresoc.v:108087$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:106838.5-106838.29" + attribute \src "libresoc.v:108088.5-108088.29" switch \initial - attribute \src "libresoc.v:106838.9-106838.17" + attribute \src "libresoc.v:108088.9-108088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166452,18 +168312,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:106886.3-106934.6" - process $proc$libresoc.v:106886$4175 + attribute \src "libresoc.v:108136.3-108184.6" + process $proc$libresoc.v:108136$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106887.5-106887.29" + attribute \src "libresoc.v:108137.5-108137.29" switch \initial - attribute \src "libresoc.v:106887.9-106887.17" + attribute \src "libresoc.v:108137.9-108137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166527,18 +168387,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:106935.3-106983.6" - process $proc$libresoc.v:106935$4176 + attribute \src "libresoc.v:108185.3-108233.6" + process $proc$libresoc.v:108185$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:106936.5-106936.29" + attribute \src "libresoc.v:108186.5-108186.29" switch \initial - attribute \src "libresoc.v:106936.9-106936.17" + attribute \src "libresoc.v:108186.9-108186.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166602,18 +168462,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:106984.3-107032.6" - process $proc$libresoc.v:106984$4177 + attribute \src "libresoc.v:108234.3-108282.6" + process $proc$libresoc.v:108234$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:106985.5-106985.29" + attribute \src "libresoc.v:108235.5-108235.29" switch \initial - attribute \src "libresoc.v:106985.9-106985.17" + attribute \src "libresoc.v:108235.9-108235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166677,18 +168537,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:107033.3-107081.6" - process $proc$libresoc.v:107033$4178 + attribute \src "libresoc.v:108283.3-108331.6" + process $proc$libresoc.v:108283$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107034.5-107034.29" + attribute \src "libresoc.v:108284.5-108284.29" switch \initial - attribute \src "libresoc.v:107034.9-107034.17" + attribute \src "libresoc.v:108284.9-108284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166752,18 +168612,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:107082.3-107130.6" - process $proc$libresoc.v:107082$4179 + attribute \src "libresoc.v:108332.3-108380.6" + process $proc$libresoc.v:108332$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107083.5-107083.29" + attribute \src "libresoc.v:108333.5-108333.29" switch \initial - attribute \src "libresoc.v:107083.9-107083.17" + attribute \src "libresoc.v:108333.9-108333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166827,18 +168687,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:107131.3-107179.6" - process $proc$libresoc.v:107131$4180 + attribute \src "libresoc.v:108381.3-108429.6" + process $proc$libresoc.v:108381$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107132.5-107132.29" + attribute \src "libresoc.v:108382.5-108382.29" switch \initial - attribute \src "libresoc.v:107132.9-107132.17" + attribute \src "libresoc.v:108382.9-108382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166902,168 +168762,168 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:107180.3-107228.6" - process $proc$libresoc.v:107180$4181 + attribute \src "libresoc.v:108430.3-108478.6" + process $proc$libresoc.v:108430$4213 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107181.5-107181.29" + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:108431.5-108431.29" switch \initial - attribute \src "libresoc.v:107181.9-107181.17" + attribute \src "libresoc.v:108431.9-108431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'00000 end sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:107229.3-107277.6" - process $proc$libresoc.v:107229$4182 + attribute \src "libresoc.v:108479.3-108527.6" + process $proc$libresoc.v:108479$4214 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107230.5-107230.29" + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:108480.5-108480.29" switch \initial - attribute \src "libresoc.v:107230.9-107230.17" + attribute \src "libresoc.v:108480.9-108480.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:107278.3-107326.6" - process $proc$libresoc.v:107278$4183 + attribute \src "libresoc.v:108528.3-108576.6" + process $proc$libresoc.v:108528$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107279.5-107279.29" + attribute \src "libresoc.v:108529.5-108529.29" switch \initial - attribute \src "libresoc.v:107279.9-107279.17" + attribute \src "libresoc.v:108529.9-108529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167127,18 +168987,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:107327.3-107375.6" - process $proc$libresoc.v:107327$4184 + attribute \src "libresoc.v:108577.3-108625.6" + process $proc$libresoc.v:108577$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107328.5-107328.29" + attribute \src "libresoc.v:108578.5-108578.29" switch \initial - attribute \src "libresoc.v:107328.9-107328.17" + attribute \src "libresoc.v:108578.9-108578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167202,18 +169062,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:107376.3-107424.6" - process $proc$libresoc.v:107376$4185 + attribute \src "libresoc.v:108626.3-108674.6" + process $proc$libresoc.v:108626$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107377.5-107377.29" + attribute \src "libresoc.v:108627.5-108627.29" switch \initial - attribute \src "libresoc.v:107377.9-107377.17" + attribute \src "libresoc.v:108627.9-108627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167277,18 +169137,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:107425.3-107473.6" - process $proc$libresoc.v:107425$4186 + attribute \src "libresoc.v:108675.3-108723.6" + process $proc$libresoc.v:108675$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107426.5-107426.29" + attribute \src "libresoc.v:108676.5-108676.29" switch \initial - attribute \src "libresoc.v:107426.9-107426.17" + attribute \src "libresoc.v:108676.9-108676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167352,18 +169212,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:107474.3-107522.6" - process $proc$libresoc.v:107474$4187 + attribute \src "libresoc.v:108724.3-108772.6" + process $proc$libresoc.v:108724$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:107475.5-107475.29" + attribute \src "libresoc.v:108725.5-108725.29" switch \initial - attribute \src "libresoc.v:107475.9-107475.17" + attribute \src "libresoc.v:108725.9-108725.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167427,18 +169287,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:107523.3-107571.6" - process $proc$libresoc.v:107523$4188 + attribute \src "libresoc.v:108773.3-108821.6" + process $proc$libresoc.v:108773$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107524.5-107524.29" + attribute \src "libresoc.v:108774.5-108774.29" switch \initial - attribute \src "libresoc.v:107524.9-107524.17" + attribute \src "libresoc.v:108774.9-108774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167502,18 +169362,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:107572.3-107620.6" - process $proc$libresoc.v:107572$4189 + attribute \src "libresoc.v:108822.3-108870.6" + process $proc$libresoc.v:108822$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107573.5-107573.29" + attribute \src "libresoc.v:108823.5-108823.29" switch \initial - attribute \src "libresoc.v:107573.9-107573.17" + attribute \src "libresoc.v:108823.9-108823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167577,18 +169437,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:107621.3-107669.6" - process $proc$libresoc.v:107621$4190 + attribute \src "libresoc.v:108871.3-108919.6" + process $proc$libresoc.v:108871$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107622.5-107622.29" + attribute \src "libresoc.v:108872.5-108872.29" switch \initial - attribute \src "libresoc.v:107622.9-107622.17" + attribute \src "libresoc.v:108872.9-108872.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167652,18 +169512,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:107670.3-107718.6" - process $proc$libresoc.v:107670$4191 + attribute \src "libresoc.v:108920.3-108968.6" + process $proc$libresoc.v:108920$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107671.5-107671.29" + attribute \src "libresoc.v:108921.5-108921.29" switch \initial - attribute \src "libresoc.v:107671.9-107671.17" + attribute \src "libresoc.v:108921.9-108921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167729,157 +169589,161 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107724.1-108672.10" +attribute \src "libresoc.v:108974.1-109951.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:108557.3-108575.6" + attribute \src "libresoc.v:109836.3-109854.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108576.3-108594.6" + attribute \src "libresoc.v:109855.3-109873.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108329.3-108347.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108405.3-108423.6" + attribute \src "libresoc.v:109684.3-109702.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108082.3-108100.6" + attribute \src "libresoc.v:109342.3-109360.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108101.3-108119.6" + attribute \src "libresoc.v:109361.3-109379.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108310.3-108328.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108386.3-108404.6" + attribute \src "libresoc.v:109665.3-109683.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108481.3-108499.6" + attribute \src "libresoc.v:109741.3-109759.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108063.3-108081.6" + attribute \src "libresoc.v:109323.3-109341.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108595.3-108613.6" + attribute \src "libresoc.v:109874.3-109892.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108614.3-108632.6" + attribute \src "libresoc.v:109893.3-109911.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108633.3-108651.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108272.3-108290.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108348.3-108366.6" + attribute \src "libresoc.v:109627.3-109645.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108367.3-108385.6" + attribute \src "libresoc.v:109646.3-109664.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108462.3-108480.6" + attribute \src "libresoc.v:109760.3-109778.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108234.3-108252.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108519.3-108537.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108652.3-108670.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108291.3-108309.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108443.3-108461.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108538.3-108556.6" + attribute \src "libresoc.v:109817.3-109835.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108500.3-108518.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108424.3-108442.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108196.3-108214.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108215.3-108233.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108120.3-108138.6" + attribute \src "libresoc.v:109380.3-109398.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108139.3-108157.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108158.3-108176.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108177.3-108195.6" + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108253.3-108271.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:107725.7-107725.20" + attribute \src "libresoc.v:108975.7-108975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108557.3-108575.6" + attribute \src "libresoc.v:109836.3-109854.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108576.3-108594.6" + attribute \src "libresoc.v:109855.3-109873.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108329.3-108347.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108405.3-108423.6" + attribute \src "libresoc.v:109684.3-109702.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108082.3-108100.6" + attribute \src "libresoc.v:109342.3-109360.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108101.3-108119.6" + attribute \src "libresoc.v:109361.3-109379.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108310.3-108328.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108386.3-108404.6" + attribute \src "libresoc.v:109665.3-109683.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108481.3-108499.6" + attribute \src "libresoc.v:109741.3-109759.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108063.3-108081.6" + attribute \src "libresoc.v:109323.3-109341.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108595.3-108613.6" + attribute \src "libresoc.v:109874.3-109892.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108614.3-108632.6" + attribute \src "libresoc.v:109893.3-109911.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108633.3-108651.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108272.3-108290.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108348.3-108366.6" + attribute \src "libresoc.v:109627.3-109645.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108367.3-108385.6" + attribute \src "libresoc.v:109646.3-109664.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108462.3-108480.6" + attribute \src "libresoc.v:109760.3-109778.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108234.3-108252.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108519.3-108537.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108652.3-108670.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108291.3-108309.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108443.3-108461.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108538.3-108556.6" + attribute \src "libresoc.v:109817.3-109835.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108500.3-108518.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108424.3-108442.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108196.3-108214.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108215.3-108233.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108120.3-108138.6" + attribute \src "libresoc.v:109380.3-109398.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108139.3-108157.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108158.3-108176.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108177.3-108195.6" + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108253.3-108271.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub24_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub24_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub24_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -167889,7 +169753,7 @@ module \dec31_dec_sub24 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167898,16 +169762,16 @@ module \dec31_dec_sub24 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -167939,7 +169803,7 @@ module \dec31_dec_sub24 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -167956,7 +169820,7 @@ module \dec31_dec_sub24 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -167964,7 +169828,7 @@ module \dec31_dec_sub24 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167981,13 +169845,13 @@ module \dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -168064,46 +169928,46 @@ module \dec31_dec_sub24 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub24_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub24_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub24_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub24_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168111,8 +169975,8 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub24_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub24_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168120,8 +169984,8 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub24_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub24_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168129,7 +169993,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub24_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168138,7 +170002,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub24_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168147,7 +170011,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub24_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168156,41 +170020,50 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub24_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub24_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub24_upd - attribute \src "libresoc.v:107725.7-107725.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub24_upd + attribute \src "libresoc.v:108975.7-108975.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:107725.7-107725.20" - process $proc$libresoc.v:107725$4225 + attribute \src "libresoc.v:108975.7-108975.20" + process $proc$libresoc.v:108975$4258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:108063.3-108081.6" - process $proc$libresoc.v:108063$4193 + attribute \src "libresoc.v:109323.3-109341.6" + process $proc$libresoc.v:109323$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108064.5-108064.29" + attribute \src "libresoc.v:109324.5-109324.29" switch \initial - attribute \src "libresoc.v:108064.9-108064.17" + attribute \src "libresoc.v:109324.9-109324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168214,18 +170087,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:108082.3-108100.6" - process $proc$libresoc.v:108082$4194 + attribute \src "libresoc.v:109342.3-109360.6" + process $proc$libresoc.v:109342$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108083.5-108083.29" + attribute \src "libresoc.v:109343.5-109343.29" switch \initial - attribute \src "libresoc.v:108083.9-108083.17" + attribute \src "libresoc.v:109343.9-109343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168249,18 +170122,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:108101.3-108119.6" - process $proc$libresoc.v:108101$4195 + attribute \src "libresoc.v:109361.3-109379.6" + process $proc$libresoc.v:109361$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108102.5-108102.29" + attribute \src "libresoc.v:109362.5-109362.29" switch \initial - attribute \src "libresoc.v:108102.9-108102.17" + attribute \src "libresoc.v:109362.9-109362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168284,18 +170157,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:108120.3-108138.6" - process $proc$libresoc.v:108120$4196 + attribute \src "libresoc.v:109380.3-109398.6" + process $proc$libresoc.v:109380$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108121.5-108121.29" + attribute \src "libresoc.v:109381.5-109381.29" switch \initial - attribute \src "libresoc.v:108121.9-108121.17" + attribute \src "libresoc.v:109381.9-109381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168319,18 +170192,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:108139.3-108157.6" - process $proc$libresoc.v:108139$4197 + attribute \src "libresoc.v:109399.3-109417.6" + process $proc$libresoc.v:109399$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108140.5-108140.29" + attribute \src "libresoc.v:109400.5-109400.29" switch \initial - attribute \src "libresoc.v:108140.9-108140.17" + attribute \src "libresoc.v:109400.9-109400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168354,18 +170227,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:108158.3-108176.6" - process $proc$libresoc.v:108158$4198 + attribute \src "libresoc.v:109418.3-109436.6" + process $proc$libresoc.v:109418$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108159.5-108159.29" + attribute \src "libresoc.v:109419.5-109419.29" switch \initial - attribute \src "libresoc.v:108159.9-108159.17" + attribute \src "libresoc.v:109419.9-109419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168389,18 +170262,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:108177.3-108195.6" - process $proc$libresoc.v:108177$4199 + attribute \src "libresoc.v:109437.3-109455.6" + process $proc$libresoc.v:109437$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108178.5-108178.29" + attribute \src "libresoc.v:109438.5-109438.29" switch \initial - attribute \src "libresoc.v:108178.9-108178.17" + attribute \src "libresoc.v:109438.9-109438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168424,18 +170297,53 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:108196.3-108214.6" - process $proc$libresoc.v:108196$4200 + attribute \src "libresoc.v:109456.3-109474.6" + process $proc$libresoc.v:109456$4232 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109457.5-109457.29" + switch \initial + attribute \src "libresoc.v:109457.9-109457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] + end + attribute \src "libresoc.v:109475.3-109493.6" + process $proc$libresoc.v:109475$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108197.5-108197.29" + attribute \src "libresoc.v:109476.5-109476.29" switch \initial - attribute \src "libresoc.v:108197.9-108197.17" + attribute \src "libresoc.v:109476.9-109476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168459,18 +170367,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:108215.3-108233.6" - process $proc$libresoc.v:108215$4201 + attribute \src "libresoc.v:109494.3-109512.6" + process $proc$libresoc.v:109494$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108216.5-108216.29" + attribute \src "libresoc.v:109495.5-109495.29" switch \initial - attribute \src "libresoc.v:108216.9-108216.17" + attribute \src "libresoc.v:109495.9-109495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168494,18 +170402,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:108234.3-108252.6" - process $proc$libresoc.v:108234$4202 + attribute \src "libresoc.v:109513.3-109531.6" + process $proc$libresoc.v:109513$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108235.5-108235.29" + attribute \src "libresoc.v:109514.5-109514.29" switch \initial - attribute \src "libresoc.v:108235.9-108235.17" + attribute \src "libresoc.v:109514.9-109514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168529,88 +170437,88 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:108253.3-108271.6" - process $proc$libresoc.v:108253$4203 + attribute \src "libresoc.v:109532.3-109550.6" + process $proc$libresoc.v:109532$4236 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:108254.5-108254.29" + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:109533.5-109533.29" switch \initial - attribute \src "libresoc.v:108254.9-108254.17" + attribute \src "libresoc.v:109533.9-109533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:108272.3-108290.6" - process $proc$libresoc.v:108272$4204 + attribute \src "libresoc.v:109551.3-109569.6" + process $proc$libresoc.v:109551$4237 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108273.5-108273.29" + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:109552.5-109552.29" switch \initial - attribute \src "libresoc.v:108273.9-108273.17" + attribute \src "libresoc.v:109552.9-109552.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 end sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:108291.3-108309.6" - process $proc$libresoc.v:108291$4205 + attribute \src "libresoc.v:109570.3-109588.6" + process $proc$libresoc.v:109570$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108292.5-108292.29" + attribute \src "libresoc.v:109571.5-109571.29" switch \initial - attribute \src "libresoc.v:108292.9-108292.17" + attribute \src "libresoc.v:109571.9-109571.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168634,18 +170542,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:108310.3-108328.6" - process $proc$libresoc.v:108310$4206 + attribute \src "libresoc.v:109589.3-109607.6" + process $proc$libresoc.v:109589$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108311.5-108311.29" + attribute \src "libresoc.v:109590.5-109590.29" switch \initial - attribute \src "libresoc.v:108311.9-108311.17" + attribute \src "libresoc.v:109590.9-109590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168669,18 +170577,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:108329.3-108347.6" - process $proc$libresoc.v:108329$4207 + attribute \src "libresoc.v:109608.3-109626.6" + process $proc$libresoc.v:109608$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108330.5-108330.29" + attribute \src "libresoc.v:109609.5-109609.29" switch \initial - attribute \src "libresoc.v:108330.9-108330.17" + attribute \src "libresoc.v:109609.9-109609.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168704,18 +170612,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:108348.3-108366.6" - process $proc$libresoc.v:108348$4208 + attribute \src "libresoc.v:109627.3-109645.6" + process $proc$libresoc.v:109627$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108349.5-108349.29" + attribute \src "libresoc.v:109628.5-109628.29" switch \initial - attribute \src "libresoc.v:108349.9-108349.17" + attribute \src "libresoc.v:109628.9-109628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168739,18 +170647,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:108367.3-108385.6" - process $proc$libresoc.v:108367$4209 + attribute \src "libresoc.v:109646.3-109664.6" + process $proc$libresoc.v:109646$4242 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108368.5-108368.29" + attribute \src "libresoc.v:109647.5-109647.29" switch \initial - attribute \src "libresoc.v:108368.9-108368.17" + attribute \src "libresoc.v:109647.9-109647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168774,18 +170682,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:108386.3-108404.6" - process $proc$libresoc.v:108386$4210 + attribute \src "libresoc.v:109665.3-109683.6" + process $proc$libresoc.v:109665$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108387.5-108387.29" + attribute \src "libresoc.v:109666.5-109666.29" switch \initial - attribute \src "libresoc.v:108387.9-108387.17" + attribute \src "libresoc.v:109666.9-109666.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168809,18 +170717,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:108405.3-108423.6" - process $proc$libresoc.v:108405$4211 + attribute \src "libresoc.v:109684.3-109702.6" + process $proc$libresoc.v:109684$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108406.5-108406.29" + attribute \src "libresoc.v:109685.5-109685.29" switch \initial - attribute \src "libresoc.v:108406.9-108406.17" + attribute \src "libresoc.v:109685.9-109685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168844,18 +170752,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:108424.3-108442.6" - process $proc$libresoc.v:108424$4212 + attribute \src "libresoc.v:109703.3-109721.6" + process $proc$libresoc.v:109703$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108425.5-108425.29" + attribute \src "libresoc.v:109704.5-109704.29" switch \initial - attribute \src "libresoc.v:108425.9-108425.17" + attribute \src "libresoc.v:109704.9-109704.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168879,18 +170787,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:108443.3-108461.6" - process $proc$libresoc.v:108443$4213 + attribute \src "libresoc.v:109722.3-109740.6" + process $proc$libresoc.v:109722$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108444.5-108444.29" + attribute \src "libresoc.v:109723.5-109723.29" switch \initial - attribute \src "libresoc.v:108444.9-108444.17" + attribute \src "libresoc.v:109723.9-109723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168914,88 +170822,88 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:108462.3-108480.6" - process $proc$libresoc.v:108462$4214 + attribute \src "libresoc.v:109741.3-109759.6" + process $proc$libresoc.v:109741$4247 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108463.5-108463.29" + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:109742.5-109742.29" switch \initial - attribute \src "libresoc.v:108463.9-108463.17" + attribute \src "libresoc.v:109742.9-109742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_form[4:0] 5'00000 end sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:108481.3-108499.6" - process $proc$libresoc.v:108481$4215 + attribute \src "libresoc.v:109760.3-109778.6" + process $proc$libresoc.v:109760$4248 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108482.5-108482.29" + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:109761.5-109761.29" switch \initial - attribute \src "libresoc.v:108482.9-108482.17" + attribute \src "libresoc.v:109761.9-109761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:108500.3-108518.6" - process $proc$libresoc.v:108500$4216 + attribute \src "libresoc.v:109779.3-109797.6" + process $proc$libresoc.v:109779$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108501.5-108501.29" + attribute \src "libresoc.v:109780.5-109780.29" switch \initial - attribute \src "libresoc.v:108501.9-108501.17" + attribute \src "libresoc.v:109780.9-109780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169019,18 +170927,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:108519.3-108537.6" - process $proc$libresoc.v:108519$4217 + attribute \src "libresoc.v:109798.3-109816.6" + process $proc$libresoc.v:109798$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108520.5-108520.29" + attribute \src "libresoc.v:109799.5-109799.29" switch \initial - attribute \src "libresoc.v:108520.9-108520.17" + attribute \src "libresoc.v:109799.9-109799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169054,18 +170962,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:108538.3-108556.6" - process $proc$libresoc.v:108538$4218 + attribute \src "libresoc.v:109817.3-109835.6" + process $proc$libresoc.v:109817$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108539.5-108539.29" + attribute \src "libresoc.v:109818.5-109818.29" switch \initial - attribute \src "libresoc.v:108539.9-108539.17" + attribute \src "libresoc.v:109818.9-109818.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169089,18 +170997,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:108557.3-108575.6" - process $proc$libresoc.v:108557$4219 + attribute \src "libresoc.v:109836.3-109854.6" + process $proc$libresoc.v:109836$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108558.5-108558.29" + attribute \src "libresoc.v:109837.5-109837.29" switch \initial - attribute \src "libresoc.v:108558.9-108558.17" + attribute \src "libresoc.v:109837.9-109837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169124,18 +171032,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:108576.3-108594.6" - process $proc$libresoc.v:108576$4220 + attribute \src "libresoc.v:109855.3-109873.6" + process $proc$libresoc.v:109855$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108577.5-108577.29" + attribute \src "libresoc.v:109856.5-109856.29" switch \initial - attribute \src "libresoc.v:108577.9-108577.17" + attribute \src "libresoc.v:109856.9-109856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169159,18 +171067,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:108595.3-108613.6" - process $proc$libresoc.v:108595$4221 + attribute \src "libresoc.v:109874.3-109892.6" + process $proc$libresoc.v:109874$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108596.5-108596.29" + attribute \src "libresoc.v:109875.5-109875.29" switch \initial - attribute \src "libresoc.v:108596.9-108596.17" + attribute \src "libresoc.v:109875.9-109875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169194,18 +171102,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:108614.3-108632.6" - process $proc$libresoc.v:108614$4222 + attribute \src "libresoc.v:109893.3-109911.6" + process $proc$libresoc.v:109893$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108615.5-108615.29" + attribute \src "libresoc.v:109894.5-109894.29" switch \initial - attribute \src "libresoc.v:108615.9-108615.17" + attribute \src "libresoc.v:109894.9-109894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169229,18 +171137,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:108633.3-108651.6" - process $proc$libresoc.v:108633$4223 + attribute \src "libresoc.v:109912.3-109930.6" + process $proc$libresoc.v:109912$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108634.5-108634.29" + attribute \src "libresoc.v:109913.5-109913.29" switch \initial - attribute \src "libresoc.v:108634.9-108634.17" + attribute \src "libresoc.v:109913.9-109913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169264,18 +171172,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:108652.3-108670.6" - process $proc$libresoc.v:108652$4224 + attribute \src "libresoc.v:109931.3-109949.6" + process $proc$libresoc.v:109931$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108653.5-108653.29" + attribute \src "libresoc.v:109932.5-109932.29" switch \initial - attribute \src "libresoc.v:108653.9-108653.17" + attribute \src "libresoc.v:109932.9-109932.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169301,157 +171209,161 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108676.1-110680.10" +attribute \src "libresoc.v:109955.1-112021.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:110367.3-110418.6" + attribute \src "libresoc.v:111708.3-111759.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110419.3-110470.6" + attribute \src "libresoc.v:111760.3-111811.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:109743.3-109794.6" + attribute \src "libresoc.v:111084.3-111135.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109951.3-110002.6" + attribute \src "libresoc.v:111292.3-111343.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109067.3-109118.6" + attribute \src "libresoc.v:110356.3-110407.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109119.3-109170.6" + attribute \src "libresoc.v:110408.3-110459.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109691.3-109742.6" + attribute \src "libresoc.v:111032.3-111083.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109899.3-109950.6" + attribute \src "libresoc.v:111240.3-111291.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:110159.3-110210.6" + attribute \src "libresoc.v:111448.3-111499.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:109015.3-109066.6" + attribute \src "libresoc.v:110304.3-110355.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110471.3-110522.6" + attribute \src "libresoc.v:111812.3-111863.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110523.3-110574.6" + attribute \src "libresoc.v:111864.3-111915.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110575.3-110626.6" + attribute \src "libresoc.v:111916.3-111967.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:109587.3-109638.6" + attribute \src "libresoc.v:110876.3-110927.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109795.3-109846.6" + attribute \src "libresoc.v:111136.3-111187.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109847.3-109898.6" + attribute \src "libresoc.v:111188.3-111239.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:110107.3-110158.6" + attribute \src "libresoc.v:111500.3-111551.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:109483.3-109534.6" + attribute \src "libresoc.v:110824.3-110875.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110263.3-110314.6" + attribute \src "libresoc.v:111604.3-111655.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110627.3-110678.6" + attribute \src "libresoc.v:111968.3-112019.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:109639.3-109690.6" + attribute \src "libresoc.v:110980.3-111031.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110055.3-110106.6" + attribute \src "libresoc.v:111396.3-111447.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110315.3-110366.6" + attribute \src "libresoc.v:111656.3-111707.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110211.3-110262.6" + attribute \src "libresoc.v:111552.3-111603.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110003.3-110054.6" + attribute \src "libresoc.v:111344.3-111395.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:109379.3-109430.6" + attribute \src "libresoc.v:110720.3-110771.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109431.3-109482.6" + attribute \src "libresoc.v:110772.3-110823.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109171.3-109222.6" + attribute \src "libresoc.v:110460.3-110511.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109223.3-109274.6" + attribute \src "libresoc.v:110512.3-110563.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109275.3-109326.6" + attribute \src "libresoc.v:110564.3-110615.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109327.3-109378.6" + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109535.3-109586.6" + attribute \src "libresoc.v:110928.3-110979.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:108677.7-108677.20" + attribute \src "libresoc.v:109956.7-109956.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110367.3-110418.6" + attribute \src "libresoc.v:111708.3-111759.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110419.3-110470.6" + attribute \src "libresoc.v:111760.3-111811.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:109743.3-109794.6" + attribute \src "libresoc.v:111084.3-111135.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109951.3-110002.6" + attribute \src "libresoc.v:111292.3-111343.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109067.3-109118.6" + attribute \src "libresoc.v:110356.3-110407.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109119.3-109170.6" + attribute \src "libresoc.v:110408.3-110459.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109691.3-109742.6" + attribute \src "libresoc.v:111032.3-111083.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109899.3-109950.6" + attribute \src "libresoc.v:111240.3-111291.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:110159.3-110210.6" + attribute \src "libresoc.v:111448.3-111499.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:109015.3-109066.6" + attribute \src "libresoc.v:110304.3-110355.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110471.3-110522.6" + attribute \src "libresoc.v:111812.3-111863.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110523.3-110574.6" + attribute \src "libresoc.v:111864.3-111915.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110575.3-110626.6" + attribute \src "libresoc.v:111916.3-111967.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:109587.3-109638.6" + attribute \src "libresoc.v:110876.3-110927.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109795.3-109846.6" + attribute \src "libresoc.v:111136.3-111187.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109847.3-109898.6" + attribute \src "libresoc.v:111188.3-111239.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:110107.3-110158.6" + attribute \src "libresoc.v:111500.3-111551.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:109483.3-109534.6" + attribute \src "libresoc.v:110824.3-110875.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110263.3-110314.6" + attribute \src "libresoc.v:111604.3-111655.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110627.3-110678.6" + attribute \src "libresoc.v:111968.3-112019.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:109639.3-109690.6" + attribute \src "libresoc.v:110980.3-111031.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110055.3-110106.6" + attribute \src "libresoc.v:111396.3-111447.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110315.3-110366.6" + attribute \src "libresoc.v:111656.3-111707.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110211.3-110262.6" + attribute \src "libresoc.v:111552.3-111603.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110003.3-110054.6" + attribute \src "libresoc.v:111344.3-111395.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:109379.3-109430.6" + attribute \src "libresoc.v:110720.3-110771.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109431.3-109482.6" + attribute \src "libresoc.v:110772.3-110823.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109171.3-109222.6" + attribute \src "libresoc.v:110460.3-110511.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109223.3-109274.6" + attribute \src "libresoc.v:110512.3-110563.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109275.3-109326.6" + attribute \src "libresoc.v:110564.3-110615.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109327.3-109378.6" + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109535.3-109586.6" + attribute \src "libresoc.v:110928.3-110979.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub26_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub26_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub26_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -169461,7 +171373,7 @@ module \dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -169470,16 +171382,16 @@ module \dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -169511,7 +171423,7 @@ module \dec31_dec_sub26 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -169528,7 +171440,7 @@ module \dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169536,7 +171448,7 @@ module \dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -169553,13 +171465,13 @@ module \dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -169636,46 +171548,46 @@ module \dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub26_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub26_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub26_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub26_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169683,8 +171595,8 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub26_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub26_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169692,8 +171604,8 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub26_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub26_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169701,7 +171613,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub26_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169710,7 +171622,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub26_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169719,7 +171631,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub26_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169728,41 +171640,50 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub26_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub26_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub26_upd - attribute \src "libresoc.v:108677.7-108677.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub26_upd + attribute \src "libresoc.v:109956.7-109956.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:108677.7-108677.20" - process $proc$libresoc.v:108677$4258 + attribute \src "libresoc.v:109956.7-109956.20" + process $proc$libresoc.v:109956$4292 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109015.3-109066.6" - process $proc$libresoc.v:109015$4226 + attribute \src "libresoc.v:110304.3-110355.6" + process $proc$libresoc.v:110304$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:109016.5-109016.29" + attribute \src "libresoc.v:110305.5-110305.29" switch \initial - attribute \src "libresoc.v:109016.9-109016.17" + attribute \src "libresoc.v:110305.9-110305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169830,18 +171751,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:109067.3-109118.6" - process $proc$libresoc.v:109067$4227 + attribute \src "libresoc.v:110356.3-110407.6" + process $proc$libresoc.v:110356$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109068.5-109068.29" + attribute \src "libresoc.v:110357.5-110357.29" switch \initial - attribute \src "libresoc.v:109068.9-109068.17" + attribute \src "libresoc.v:110357.9-110357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169909,18 +171830,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:109119.3-109170.6" - process $proc$libresoc.v:109119$4228 + attribute \src "libresoc.v:110408.3-110459.6" + process $proc$libresoc.v:110408$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109120.5-109120.29" + attribute \src "libresoc.v:110409.5-110409.29" switch \initial - attribute \src "libresoc.v:109120.9-109120.17" + attribute \src "libresoc.v:110409.9-110409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169988,18 +171909,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:109171.3-109222.6" - process $proc$libresoc.v:109171$4229 + attribute \src "libresoc.v:110460.3-110511.6" + process $proc$libresoc.v:110460$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109172.5-109172.29" + attribute \src "libresoc.v:110461.5-110461.29" switch \initial - attribute \src "libresoc.v:109172.9-109172.17" + attribute \src "libresoc.v:110461.9-110461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170067,18 +171988,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:109223.3-109274.6" - process $proc$libresoc.v:109223$4230 + attribute \src "libresoc.v:110512.3-110563.6" + process $proc$libresoc.v:110512$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109224.5-109224.29" + attribute \src "libresoc.v:110513.5-110513.29" switch \initial - attribute \src "libresoc.v:109224.9-109224.17" + attribute \src "libresoc.v:110513.9-110513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170146,18 +172067,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:109275.3-109326.6" - process $proc$libresoc.v:109275$4231 + attribute \src "libresoc.v:110564.3-110615.6" + process $proc$libresoc.v:110564$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109276.5-109276.29" + attribute \src "libresoc.v:110565.5-110565.29" switch \initial - attribute \src "libresoc.v:109276.9-109276.17" + attribute \src "libresoc.v:110565.9-110565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170225,18 +172146,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:109327.3-109378.6" - process $proc$libresoc.v:109327$4232 + attribute \src "libresoc.v:110616.3-110667.6" + process $proc$libresoc.v:110616$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109328.5-109328.29" + attribute \src "libresoc.v:110617.5-110617.29" switch \initial - attribute \src "libresoc.v:109328.9-109328.17" + attribute \src "libresoc.v:110617.9-110617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170304,18 +172225,97 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:109379.3-109430.6" - process $proc$libresoc.v:109379$4233 + attribute \src "libresoc.v:110668.3-110719.6" + process $proc$libresoc.v:110668$4266 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110669.5-110669.29" + switch \initial + attribute \src "libresoc.v:110669.9-110669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] + end + attribute \src "libresoc.v:110720.3-110771.6" + process $proc$libresoc.v:110720$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109380.5-109380.29" + attribute \src "libresoc.v:110721.5-110721.29" switch \initial - attribute \src "libresoc.v:109380.9-109380.17" + attribute \src "libresoc.v:110721.9-110721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170383,18 +172383,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:109431.3-109482.6" - process $proc$libresoc.v:109431$4234 + attribute \src "libresoc.v:110772.3-110823.6" + process $proc$libresoc.v:110772$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109432.5-109432.29" + attribute \src "libresoc.v:110773.5-110773.29" switch \initial - attribute \src "libresoc.v:109432.9-109432.17" + attribute \src "libresoc.v:110773.9-110773.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170462,18 +172462,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:109483.3-109534.6" - process $proc$libresoc.v:109483$4235 + attribute \src "libresoc.v:110824.3-110875.6" + process $proc$libresoc.v:110824$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:109484.5-109484.29" + attribute \src "libresoc.v:110825.5-110825.29" switch \initial - attribute \src "libresoc.v:109484.9-109484.17" + attribute \src "libresoc.v:110825.9-110825.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170541,176 +172541,176 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:109535.3-109586.6" - process $proc$libresoc.v:109535$4236 + attribute \src "libresoc.v:110876.3-110927.6" + process $proc$libresoc.v:110876$4270 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:109536.5-109536.29" + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:110877.5-110877.29" switch \initial - attribute \src "libresoc.v:109536.9-109536.17" + attribute \src "libresoc.v:110877.9-110877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:109587.3-109638.6" - process $proc$libresoc.v:109587$4237 + attribute \src "libresoc.v:110928.3-110979.6" + process $proc$libresoc.v:110928$4271 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109588.5-109588.29" + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:110929.5-110929.29" switch \initial - attribute \src "libresoc.v:109588.9-109588.17" + attribute \src "libresoc.v:110929.9-110929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 end sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:109639.3-109690.6" - process $proc$libresoc.v:109639$4238 + attribute \src "libresoc.v:110980.3-111031.6" + process $proc$libresoc.v:110980$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:109640.5-109640.29" + attribute \src "libresoc.v:110981.5-110981.29" switch \initial - attribute \src "libresoc.v:109640.9-109640.17" + attribute \src "libresoc.v:110981.9-110981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170778,18 +172778,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:109691.3-109742.6" - process $proc$libresoc.v:109691$4239 + attribute \src "libresoc.v:111032.3-111083.6" + process $proc$libresoc.v:111032$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109692.5-109692.29" + attribute \src "libresoc.v:111033.5-111033.29" switch \initial - attribute \src "libresoc.v:109692.9-109692.17" + attribute \src "libresoc.v:111033.9-111033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170857,18 +172857,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:109743.3-109794.6" - process $proc$libresoc.v:109743$4240 + attribute \src "libresoc.v:111084.3-111135.6" + process $proc$libresoc.v:111084$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109744.5-109744.29" + attribute \src "libresoc.v:111085.5-111085.29" switch \initial - attribute \src "libresoc.v:109744.9-109744.17" + attribute \src "libresoc.v:111085.9-111085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170936,18 +172936,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:109795.3-109846.6" - process $proc$libresoc.v:109795$4241 + attribute \src "libresoc.v:111136.3-111187.6" + process $proc$libresoc.v:111136$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109796.5-109796.29" + attribute \src "libresoc.v:111137.5-111137.29" switch \initial - attribute \src "libresoc.v:109796.9-109796.17" + attribute \src "libresoc.v:111137.9-111137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171015,18 +173015,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:109847.3-109898.6" - process $proc$libresoc.v:109847$4242 + attribute \src "libresoc.v:111188.3-111239.6" + process $proc$libresoc.v:111188$4276 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:109848.5-109848.29" + attribute \src "libresoc.v:111189.5-111189.29" switch \initial - attribute \src "libresoc.v:109848.9-109848.17" + attribute \src "libresoc.v:111189.9-111189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171094,18 +173094,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:109899.3-109950.6" - process $proc$libresoc.v:109899$4243 + attribute \src "libresoc.v:111240.3-111291.6" + process $proc$libresoc.v:111240$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:109900.5-109900.29" + attribute \src "libresoc.v:111241.5-111241.29" switch \initial - attribute \src "libresoc.v:109900.9-109900.17" + attribute \src "libresoc.v:111241.9-111241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171173,18 +173173,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:109951.3-110002.6" - process $proc$libresoc.v:109951$4244 + attribute \src "libresoc.v:111292.3-111343.6" + process $proc$libresoc.v:111292$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109952.5-109952.29" + attribute \src "libresoc.v:111293.5-111293.29" switch \initial - attribute \src "libresoc.v:109952.9-109952.17" + attribute \src "libresoc.v:111293.9-111293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171252,18 +173252,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:110003.3-110054.6" - process $proc$libresoc.v:110003$4245 + attribute \src "libresoc.v:111344.3-111395.6" + process $proc$libresoc.v:111344$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110004.5-110004.29" + attribute \src "libresoc.v:111345.5-111345.29" switch \initial - attribute \src "libresoc.v:110004.9-110004.17" + attribute \src "libresoc.v:111345.9-111345.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171331,18 +173331,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:110055.3-110106.6" - process $proc$libresoc.v:110055$4246 + attribute \src "libresoc.v:111396.3-111447.6" + process $proc$libresoc.v:111396$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110056.5-110056.29" + attribute \src "libresoc.v:111397.5-111397.29" switch \initial - attribute \src "libresoc.v:110056.9-110056.17" + attribute \src "libresoc.v:111397.9-111397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171410,176 +173410,176 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:110107.3-110158.6" - process $proc$libresoc.v:110107$4247 + attribute \src "libresoc.v:111448.3-111499.6" + process $proc$libresoc.v:111448$4281 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110108.5-110108.29" + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:111449.5-111449.29" switch \initial - attribute \src "libresoc.v:110108.9-110108.17" + attribute \src "libresoc.v:111449.9-111449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'00000 end sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:110159.3-110210.6" - process $proc$libresoc.v:110159$4248 + attribute \src "libresoc.v:111500.3-111551.6" + process $proc$libresoc.v:111500$4282 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110160.5-110160.29" + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:111501.5-111501.29" switch \initial - attribute \src "libresoc.v:110160.9-110160.17" + attribute \src "libresoc.v:111501.9-111501.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:110211.3-110262.6" - process $proc$libresoc.v:110211$4249 + attribute \src "libresoc.v:111552.3-111603.6" + process $proc$libresoc.v:111552$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110212.5-110212.29" + attribute \src "libresoc.v:111553.5-111553.29" switch \initial - attribute \src "libresoc.v:110212.9-110212.17" + attribute \src "libresoc.v:111553.9-111553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171647,18 +173647,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:110263.3-110314.6" - process $proc$libresoc.v:110263$4250 + attribute \src "libresoc.v:111604.3-111655.6" + process $proc$libresoc.v:111604$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110264.5-110264.29" + attribute \src "libresoc.v:111605.5-111605.29" switch \initial - attribute \src "libresoc.v:110264.9-110264.17" + attribute \src "libresoc.v:111605.9-111605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171726,18 +173726,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:110315.3-110366.6" - process $proc$libresoc.v:110315$4251 + attribute \src "libresoc.v:111656.3-111707.6" + process $proc$libresoc.v:111656$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110316.5-110316.29" + attribute \src "libresoc.v:111657.5-111657.29" switch \initial - attribute \src "libresoc.v:110316.9-110316.17" + attribute \src "libresoc.v:111657.9-111657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171805,18 +173805,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:110367.3-110418.6" - process $proc$libresoc.v:110367$4252 + attribute \src "libresoc.v:111708.3-111759.6" + process $proc$libresoc.v:111708$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110368.5-110368.29" + attribute \src "libresoc.v:111709.5-111709.29" switch \initial - attribute \src "libresoc.v:110368.9-110368.17" + attribute \src "libresoc.v:111709.9-111709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171884,18 +173884,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:110419.3-110470.6" - process $proc$libresoc.v:110419$4253 + attribute \src "libresoc.v:111760.3-111811.6" + process $proc$libresoc.v:111760$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:110420.5-110420.29" + attribute \src "libresoc.v:111761.5-111761.29" switch \initial - attribute \src "libresoc.v:110420.9-110420.17" + attribute \src "libresoc.v:111761.9-111761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171963,18 +173963,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:110471.3-110522.6" - process $proc$libresoc.v:110471$4254 + attribute \src "libresoc.v:111812.3-111863.6" + process $proc$libresoc.v:111812$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110472.5-110472.29" + attribute \src "libresoc.v:111813.5-111813.29" switch \initial - attribute \src "libresoc.v:110472.9-110472.17" + attribute \src "libresoc.v:111813.9-111813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172042,18 +174042,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:110523.3-110574.6" - process $proc$libresoc.v:110523$4255 + attribute \src "libresoc.v:111864.3-111915.6" + process $proc$libresoc.v:111864$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110524.5-110524.29" + attribute \src "libresoc.v:111865.5-111865.29" switch \initial - attribute \src "libresoc.v:110524.9-110524.17" + attribute \src "libresoc.v:111865.9-111865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172121,18 +174121,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:110575.3-110626.6" - process $proc$libresoc.v:110575$4256 + attribute \src "libresoc.v:111916.3-111967.6" + process $proc$libresoc.v:111916$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110576.5-110576.29" + attribute \src "libresoc.v:111917.5-111917.29" switch \initial - attribute \src "libresoc.v:110576.9-110576.17" + attribute \src "libresoc.v:111917.9-111917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172200,18 +174200,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:110627.3-110678.6" - process $proc$libresoc.v:110627$4257 + attribute \src "libresoc.v:111968.3-112019.6" + process $proc$libresoc.v:111968$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110628.5-110628.29" + attribute \src "libresoc.v:111969.5-111969.29" switch \initial - attribute \src "libresoc.v:110628.9-110628.17" + attribute \src "libresoc.v:111969.9-111969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172281,157 +174281,161 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:110684.1-111632.10" +attribute \src "libresoc.v:112025.1-113002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:111517.3-111535.6" + attribute \src "libresoc.v:112887.3-112905.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111536.3-111554.6" + attribute \src "libresoc.v:112906.3-112924.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111289.3-111307.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111365.3-111383.6" + attribute \src "libresoc.v:112735.3-112753.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111042.3-111060.6" + attribute \src "libresoc.v:112393.3-112411.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111061.3-111079.6" + attribute \src "libresoc.v:112412.3-112430.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111270.3-111288.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111346.3-111364.6" + attribute \src "libresoc.v:112716.3-112734.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111441.3-111459.6" + attribute \src "libresoc.v:112792.3-112810.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111023.3-111041.6" + attribute \src "libresoc.v:112374.3-112392.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111555.3-111573.6" + attribute \src "libresoc.v:112925.3-112943.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111574.3-111592.6" + attribute \src "libresoc.v:112944.3-112962.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111593.3-111611.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111232.3-111250.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111308.3-111326.6" + attribute \src "libresoc.v:112678.3-112696.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111327.3-111345.6" + attribute \src "libresoc.v:112697.3-112715.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111422.3-111440.6" + attribute \src "libresoc.v:112811.3-112829.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111194.3-111212.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111479.3-111497.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111612.3-111630.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111251.3-111269.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111403.3-111421.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111498.3-111516.6" + attribute \src "libresoc.v:112868.3-112886.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111460.3-111478.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111384.3-111402.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111156.3-111174.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111175.3-111193.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111080.3-111098.6" + attribute \src "libresoc.v:112431.3-112449.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111099.3-111117.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111118.3-111136.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111137.3-111155.6" + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111213.3-111231.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:110685.7-110685.20" + attribute \src "libresoc.v:112026.7-112026.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111517.3-111535.6" + attribute \src "libresoc.v:112887.3-112905.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111536.3-111554.6" + attribute \src "libresoc.v:112906.3-112924.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111289.3-111307.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111365.3-111383.6" + attribute \src "libresoc.v:112735.3-112753.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111042.3-111060.6" + attribute \src "libresoc.v:112393.3-112411.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111061.3-111079.6" + attribute \src "libresoc.v:112412.3-112430.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111270.3-111288.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111346.3-111364.6" + attribute \src "libresoc.v:112716.3-112734.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111441.3-111459.6" + attribute \src "libresoc.v:112792.3-112810.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111023.3-111041.6" + attribute \src "libresoc.v:112374.3-112392.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111555.3-111573.6" + attribute \src "libresoc.v:112925.3-112943.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111574.3-111592.6" + attribute \src "libresoc.v:112944.3-112962.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111593.3-111611.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111232.3-111250.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111308.3-111326.6" + attribute \src "libresoc.v:112678.3-112696.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111327.3-111345.6" + attribute \src "libresoc.v:112697.3-112715.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111422.3-111440.6" + attribute \src "libresoc.v:112811.3-112829.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111194.3-111212.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111479.3-111497.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111612.3-111630.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111251.3-111269.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111403.3-111421.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111498.3-111516.6" + attribute \src "libresoc.v:112868.3-112886.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111460.3-111478.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111384.3-111402.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111156.3-111174.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111175.3-111193.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111080.3-111098.6" + attribute \src "libresoc.v:112431.3-112449.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111099.3-111117.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111118.3-111136.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111137.3-111155.6" + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111213.3-111231.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub27_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub27_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub27_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -172441,7 +174445,7 @@ module \dec31_dec_sub27 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -172450,16 +174454,16 @@ module \dec31_dec_sub27 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -172491,7 +174495,7 @@ module \dec31_dec_sub27 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -172508,7 +174512,7 @@ module \dec31_dec_sub27 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -172516,7 +174520,7 @@ module \dec31_dec_sub27 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -172533,13 +174537,13 @@ module \dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -172616,46 +174620,46 @@ module \dec31_dec_sub27 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub27_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub27_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub27_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub27_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172663,8 +174667,8 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub27_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub27_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172672,8 +174676,8 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub27_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub27_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172681,7 +174685,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub27_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172690,7 +174694,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub27_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172699,7 +174703,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub27_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172708,41 +174712,50 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub27_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub27_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub27_upd - attribute \src "libresoc.v:110685.7-110685.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub27_upd + attribute \src "libresoc.v:112026.7-112026.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:110685.7-110685.20" - process $proc$libresoc.v:110685$4291 + attribute \src "libresoc.v:112026.7-112026.20" + process $proc$libresoc.v:112026$4326 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111023.3-111041.6" - process $proc$libresoc.v:111023$4259 + attribute \src "libresoc.v:112374.3-112392.6" + process $proc$libresoc.v:112374$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111024.5-111024.29" + attribute \src "libresoc.v:112375.5-112375.29" switch \initial - attribute \src "libresoc.v:111024.9-111024.17" + attribute \src "libresoc.v:112375.9-112375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172766,18 +174779,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:111042.3-111060.6" - process $proc$libresoc.v:111042$4260 + attribute \src "libresoc.v:112393.3-112411.6" + process $proc$libresoc.v:112393$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111043.5-111043.29" + attribute \src "libresoc.v:112394.5-112394.29" switch \initial - attribute \src "libresoc.v:111043.9-111043.17" + attribute \src "libresoc.v:112394.9-112394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172801,18 +174814,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:111061.3-111079.6" - process $proc$libresoc.v:111061$4261 + attribute \src "libresoc.v:112412.3-112430.6" + process $proc$libresoc.v:112412$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111062.5-111062.29" + attribute \src "libresoc.v:112413.5-112413.29" switch \initial - attribute \src "libresoc.v:111062.9-111062.17" + attribute \src "libresoc.v:112413.9-112413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172836,18 +174849,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:111080.3-111098.6" - process $proc$libresoc.v:111080$4262 + attribute \src "libresoc.v:112431.3-112449.6" + process $proc$libresoc.v:112431$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111081.5-111081.29" + attribute \src "libresoc.v:112432.5-112432.29" switch \initial - attribute \src "libresoc.v:111081.9-111081.17" + attribute \src "libresoc.v:112432.9-112432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172871,18 +174884,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:111099.3-111117.6" - process $proc$libresoc.v:111099$4263 + attribute \src "libresoc.v:112450.3-112468.6" + process $proc$libresoc.v:112450$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111100.5-111100.29" + attribute \src "libresoc.v:112451.5-112451.29" switch \initial - attribute \src "libresoc.v:111100.9-111100.17" + attribute \src "libresoc.v:112451.9-112451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172906,18 +174919,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:111118.3-111136.6" - process $proc$libresoc.v:111118$4264 + attribute \src "libresoc.v:112469.3-112487.6" + process $proc$libresoc.v:112469$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111119.5-111119.29" + attribute \src "libresoc.v:112470.5-112470.29" switch \initial - attribute \src "libresoc.v:111119.9-111119.17" + attribute \src "libresoc.v:112470.9-112470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172941,18 +174954,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:111137.3-111155.6" - process $proc$libresoc.v:111137$4265 + attribute \src "libresoc.v:112488.3-112506.6" + process $proc$libresoc.v:112488$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111138.5-111138.29" + attribute \src "libresoc.v:112489.5-112489.29" switch \initial - attribute \src "libresoc.v:111138.9-111138.17" + attribute \src "libresoc.v:112489.9-112489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172976,18 +174989,53 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:111156.3-111174.6" - process $proc$libresoc.v:111156$4266 + attribute \src "libresoc.v:112507.3-112525.6" + process $proc$libresoc.v:112507$4300 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112508.5-112508.29" + switch \initial + attribute \src "libresoc.v:112508.9-112508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] + end + attribute \src "libresoc.v:112526.3-112544.6" + process $proc$libresoc.v:112526$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111157.5-111157.29" + attribute \src "libresoc.v:112527.5-112527.29" switch \initial - attribute \src "libresoc.v:111157.9-111157.17" + attribute \src "libresoc.v:112527.9-112527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173011,18 +175059,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:111175.3-111193.6" - process $proc$libresoc.v:111175$4267 + attribute \src "libresoc.v:112545.3-112563.6" + process $proc$libresoc.v:112545$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111176.5-111176.29" + attribute \src "libresoc.v:112546.5-112546.29" switch \initial - attribute \src "libresoc.v:111176.9-111176.17" + attribute \src "libresoc.v:112546.9-112546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173046,18 +175094,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:111194.3-111212.6" - process $proc$libresoc.v:111194$4268 + attribute \src "libresoc.v:112564.3-112582.6" + process $proc$libresoc.v:112564$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111195.5-111195.29" + attribute \src "libresoc.v:112565.5-112565.29" switch \initial - attribute \src "libresoc.v:111195.9-111195.17" + attribute \src "libresoc.v:112565.9-112565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173081,88 +175129,88 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:111213.3-111231.6" - process $proc$libresoc.v:111213$4269 + attribute \src "libresoc.v:112583.3-112601.6" + process $proc$libresoc.v:112583$4304 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:111214.5-111214.29" + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:112584.5-112584.29" switch \initial - attribute \src "libresoc.v:111214.9-111214.17" + attribute \src "libresoc.v:112584.9-112584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:111232.3-111250.6" - process $proc$libresoc.v:111232$4270 + attribute \src "libresoc.v:112602.3-112620.6" + process $proc$libresoc.v:112602$4305 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111233.5-111233.29" + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:112603.5-112603.29" switch \initial - attribute \src "libresoc.v:111233.9-111233.17" + attribute \src "libresoc.v:112603.9-112603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 end sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:111251.3-111269.6" - process $proc$libresoc.v:111251$4271 + attribute \src "libresoc.v:112621.3-112639.6" + process $proc$libresoc.v:112621$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111252.5-111252.29" + attribute \src "libresoc.v:112622.5-112622.29" switch \initial - attribute \src "libresoc.v:111252.9-111252.17" + attribute \src "libresoc.v:112622.9-112622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173186,18 +175234,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:111270.3-111288.6" - process $proc$libresoc.v:111270$4272 + attribute \src "libresoc.v:112640.3-112658.6" + process $proc$libresoc.v:112640$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111271.5-111271.29" + attribute \src "libresoc.v:112641.5-112641.29" switch \initial - attribute \src "libresoc.v:111271.9-111271.17" + attribute \src "libresoc.v:112641.9-112641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173221,18 +175269,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:111289.3-111307.6" - process $proc$libresoc.v:111289$4273 + attribute \src "libresoc.v:112659.3-112677.6" + process $proc$libresoc.v:112659$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111290.5-111290.29" + attribute \src "libresoc.v:112660.5-112660.29" switch \initial - attribute \src "libresoc.v:111290.9-111290.17" + attribute \src "libresoc.v:112660.9-112660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173256,18 +175304,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:111308.3-111326.6" - process $proc$libresoc.v:111308$4274 + attribute \src "libresoc.v:112678.3-112696.6" + process $proc$libresoc.v:112678$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111309.5-111309.29" + attribute \src "libresoc.v:112679.5-112679.29" switch \initial - attribute \src "libresoc.v:111309.9-111309.17" + attribute \src "libresoc.v:112679.9-112679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173291,18 +175339,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:111327.3-111345.6" - process $proc$libresoc.v:111327$4275 + attribute \src "libresoc.v:112697.3-112715.6" + process $proc$libresoc.v:112697$4310 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111328.5-111328.29" + attribute \src "libresoc.v:112698.5-112698.29" switch \initial - attribute \src "libresoc.v:111328.9-111328.17" + attribute \src "libresoc.v:112698.9-112698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173326,18 +175374,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:111346.3-111364.6" - process $proc$libresoc.v:111346$4276 + attribute \src "libresoc.v:112716.3-112734.6" + process $proc$libresoc.v:112716$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111347.5-111347.29" + attribute \src "libresoc.v:112717.5-112717.29" switch \initial - attribute \src "libresoc.v:111347.9-111347.17" + attribute \src "libresoc.v:112717.9-112717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173361,18 +175409,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:111365.3-111383.6" - process $proc$libresoc.v:111365$4277 + attribute \src "libresoc.v:112735.3-112753.6" + process $proc$libresoc.v:112735$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111366.5-111366.29" + attribute \src "libresoc.v:112736.5-112736.29" switch \initial - attribute \src "libresoc.v:111366.9-111366.17" + attribute \src "libresoc.v:112736.9-112736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173396,18 +175444,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:111384.3-111402.6" - process $proc$libresoc.v:111384$4278 + attribute \src "libresoc.v:112754.3-112772.6" + process $proc$libresoc.v:112754$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111385.5-111385.29" + attribute \src "libresoc.v:112755.5-112755.29" switch \initial - attribute \src "libresoc.v:111385.9-111385.17" + attribute \src "libresoc.v:112755.9-112755.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173431,18 +175479,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:111403.3-111421.6" - process $proc$libresoc.v:111403$4279 + attribute \src "libresoc.v:112773.3-112791.6" + process $proc$libresoc.v:112773$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111404.5-111404.29" + attribute \src "libresoc.v:112774.5-112774.29" switch \initial - attribute \src "libresoc.v:111404.9-111404.17" + attribute \src "libresoc.v:112774.9-112774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173466,88 +175514,88 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:111422.3-111440.6" - process $proc$libresoc.v:111422$4280 + attribute \src "libresoc.v:112792.3-112810.6" + process $proc$libresoc.v:112792$4315 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111423.5-111423.29" + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:112793.5-112793.29" switch \initial - attribute \src "libresoc.v:111423.9-111423.17" + attribute \src "libresoc.v:112793.9-112793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'00000 end sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:111441.3-111459.6" - process $proc$libresoc.v:111441$4281 + attribute \src "libresoc.v:112811.3-112829.6" + process $proc$libresoc.v:112811$4316 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111442.5-111442.29" + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:112812.5-112812.29" switch \initial - attribute \src "libresoc.v:111442.9-111442.17" + attribute \src "libresoc.v:112812.9-112812.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:111460.3-111478.6" - process $proc$libresoc.v:111460$4282 + attribute \src "libresoc.v:112830.3-112848.6" + process $proc$libresoc.v:112830$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111461.5-111461.29" + attribute \src "libresoc.v:112831.5-112831.29" switch \initial - attribute \src "libresoc.v:111461.9-111461.17" + attribute \src "libresoc.v:112831.9-112831.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173571,18 +175619,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:111479.3-111497.6" - process $proc$libresoc.v:111479$4283 + attribute \src "libresoc.v:112849.3-112867.6" + process $proc$libresoc.v:112849$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111480.5-111480.29" + attribute \src "libresoc.v:112850.5-112850.29" switch \initial - attribute \src "libresoc.v:111480.9-111480.17" + attribute \src "libresoc.v:112850.9-112850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173606,18 +175654,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:111498.3-111516.6" - process $proc$libresoc.v:111498$4284 + attribute \src "libresoc.v:112868.3-112886.6" + process $proc$libresoc.v:112868$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111499.5-111499.29" + attribute \src "libresoc.v:112869.5-112869.29" switch \initial - attribute \src "libresoc.v:111499.9-111499.17" + attribute \src "libresoc.v:112869.9-112869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173641,18 +175689,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:111517.3-111535.6" - process $proc$libresoc.v:111517$4285 + attribute \src "libresoc.v:112887.3-112905.6" + process $proc$libresoc.v:112887$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111518.5-111518.29" + attribute \src "libresoc.v:112888.5-112888.29" switch \initial - attribute \src "libresoc.v:111518.9-111518.17" + attribute \src "libresoc.v:112888.9-112888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173676,18 +175724,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:111536.3-111554.6" - process $proc$libresoc.v:111536$4286 + attribute \src "libresoc.v:112906.3-112924.6" + process $proc$libresoc.v:112906$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111537.5-111537.29" + attribute \src "libresoc.v:112907.5-112907.29" switch \initial - attribute \src "libresoc.v:111537.9-111537.17" + attribute \src "libresoc.v:112907.9-112907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173711,18 +175759,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:111555.3-111573.6" - process $proc$libresoc.v:111555$4287 + attribute \src "libresoc.v:112925.3-112943.6" + process $proc$libresoc.v:112925$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111556.5-111556.29" + attribute \src "libresoc.v:112926.5-112926.29" switch \initial - attribute \src "libresoc.v:111556.9-111556.17" + attribute \src "libresoc.v:112926.9-112926.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173746,18 +175794,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:111574.3-111592.6" - process $proc$libresoc.v:111574$4288 + attribute \src "libresoc.v:112944.3-112962.6" + process $proc$libresoc.v:112944$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111575.5-111575.29" + attribute \src "libresoc.v:112945.5-112945.29" switch \initial - attribute \src "libresoc.v:111575.9-111575.17" + attribute \src "libresoc.v:112945.9-112945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173781,18 +175829,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:111593.3-111611.6" - process $proc$libresoc.v:111593$4289 + attribute \src "libresoc.v:112963.3-112981.6" + process $proc$libresoc.v:112963$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111594.5-111594.29" + attribute \src "libresoc.v:112964.5-112964.29" switch \initial - attribute \src "libresoc.v:111594.9-111594.17" + attribute \src "libresoc.v:112964.9-112964.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173816,18 +175864,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:111612.3-111630.6" - process $proc$libresoc.v:111612$4290 + attribute \src "libresoc.v:112982.3-113000.6" + process $proc$libresoc.v:112982$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111613.5-111613.29" + attribute \src "libresoc.v:112983.5-112983.29" switch \initial - attribute \src "libresoc.v:111613.9-111613.17" + attribute \src "libresoc.v:112983.9-112983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173853,157 +175901,161 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:111636.1-113160.10" +attribute \src "libresoc.v:113006.1-114577.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:112937.3-112973.6" + attribute \src "libresoc.v:114354.3-114390.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112974.3-113010.6" + attribute \src "libresoc.v:114391.3-114427.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112493.3-112529.6" + attribute \src "libresoc.v:113910.3-113946.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112641.3-112677.6" + attribute \src "libresoc.v:114058.3-114094.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112012.3-112048.6" + attribute \src "libresoc.v:113392.3-113428.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112049.3-112085.6" + attribute \src "libresoc.v:113429.3-113465.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112456.3-112492.6" + attribute \src "libresoc.v:113873.3-113909.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112604.3-112640.6" + attribute \src "libresoc.v:114021.3-114057.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112789.3-112825.6" + attribute \src "libresoc.v:114169.3-114205.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111975.3-112011.6" + attribute \src "libresoc.v:113355.3-113391.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113011.3-113047.6" + attribute \src "libresoc.v:114428.3-114464.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113048.3-113084.6" + attribute \src "libresoc.v:114465.3-114501.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113085.3-113121.6" + attribute \src "libresoc.v:114502.3-114538.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:112382.3-112418.6" + attribute \src "libresoc.v:113762.3-113798.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112530.3-112566.6" + attribute \src "libresoc.v:113947.3-113983.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112567.3-112603.6" + attribute \src "libresoc.v:113984.3-114020.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112752.3-112788.6" + attribute \src "libresoc.v:114206.3-114242.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112308.3-112344.6" + attribute \src "libresoc.v:113725.3-113761.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112863.3-112899.6" + attribute \src "libresoc.v:114280.3-114316.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:113122.3-113158.6" + attribute \src "libresoc.v:114539.3-114575.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:112419.3-112455.6" + attribute \src "libresoc.v:113836.3-113872.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112715.3-112751.6" + attribute \src "libresoc.v:114132.3-114168.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112900.3-112936.6" + attribute \src "libresoc.v:114317.3-114353.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112826.3-112862.6" + attribute \src "libresoc.v:114243.3-114279.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112678.3-112714.6" + attribute \src "libresoc.v:114095.3-114131.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112234.3-112270.6" + attribute \src "libresoc.v:113651.3-113687.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112271.3-112307.6" + attribute \src "libresoc.v:113688.3-113724.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112086.3-112122.6" + attribute \src "libresoc.v:113466.3-113502.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112123.3-112159.6" + attribute \src "libresoc.v:113503.3-113539.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112160.3-112196.6" + attribute \src "libresoc.v:113540.3-113576.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112197.3-112233.6" + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112345.3-112381.6" + attribute \src "libresoc.v:113799.3-113835.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:111637.7-111637.20" + attribute \src "libresoc.v:113007.7-113007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112937.3-112973.6" + attribute \src "libresoc.v:114354.3-114390.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112974.3-113010.6" + attribute \src "libresoc.v:114391.3-114427.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112493.3-112529.6" + attribute \src "libresoc.v:113910.3-113946.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112641.3-112677.6" + attribute \src "libresoc.v:114058.3-114094.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112012.3-112048.6" + attribute \src "libresoc.v:113392.3-113428.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112049.3-112085.6" + attribute \src "libresoc.v:113429.3-113465.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112456.3-112492.6" + attribute \src "libresoc.v:113873.3-113909.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112604.3-112640.6" + attribute \src "libresoc.v:114021.3-114057.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112789.3-112825.6" + attribute \src "libresoc.v:114169.3-114205.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111975.3-112011.6" + attribute \src "libresoc.v:113355.3-113391.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113011.3-113047.6" + attribute \src "libresoc.v:114428.3-114464.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113048.3-113084.6" + attribute \src "libresoc.v:114465.3-114501.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113085.3-113121.6" + attribute \src "libresoc.v:114502.3-114538.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:112382.3-112418.6" + attribute \src "libresoc.v:113762.3-113798.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112530.3-112566.6" + attribute \src "libresoc.v:113947.3-113983.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112567.3-112603.6" + attribute \src "libresoc.v:113984.3-114020.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112752.3-112788.6" + attribute \src "libresoc.v:114206.3-114242.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112308.3-112344.6" + attribute \src "libresoc.v:113725.3-113761.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112863.3-112899.6" + attribute \src "libresoc.v:114280.3-114316.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:113122.3-113158.6" + attribute \src "libresoc.v:114539.3-114575.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:112419.3-112455.6" + attribute \src "libresoc.v:113836.3-113872.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112715.3-112751.6" + attribute \src "libresoc.v:114132.3-114168.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112900.3-112936.6" + attribute \src "libresoc.v:114317.3-114353.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112826.3-112862.6" + attribute \src "libresoc.v:114243.3-114279.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112678.3-112714.6" + attribute \src "libresoc.v:114095.3-114131.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112234.3-112270.6" + attribute \src "libresoc.v:113651.3-113687.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112271.3-112307.6" + attribute \src "libresoc.v:113688.3-113724.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112086.3-112122.6" + attribute \src "libresoc.v:113466.3-113502.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112123.3-112159.6" + attribute \src "libresoc.v:113503.3-113539.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112160.3-112196.6" + attribute \src "libresoc.v:113540.3-113576.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112197.3-112233.6" + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112345.3-112381.6" + attribute \src "libresoc.v:113799.3-113835.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub28_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub28_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub28_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -174013,7 +176065,7 @@ module \dec31_dec_sub28 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -174022,16 +176074,16 @@ module \dec31_dec_sub28 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub28_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -174063,7 +176115,7 @@ module \dec31_dec_sub28 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -174080,7 +176132,7 @@ module \dec31_dec_sub28 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -174088,7 +176140,7 @@ module \dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -174105,13 +176157,13 @@ module \dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -174188,46 +176240,46 @@ module \dec31_dec_sub28 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub28_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub28_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub28_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174235,8 +176287,8 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub28_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub28_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174244,8 +176296,8 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub28_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub28_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174253,7 +176305,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub28_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174262,7 +176314,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub28_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174271,7 +176323,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub28_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174280,41 +176332,50 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub28_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub28_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub28_upd - attribute \src "libresoc.v:111637.7-111637.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub28_upd + attribute \src "libresoc.v:113007.7-113007.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:111637.7-111637.20" - process $proc$libresoc.v:111637$4324 + attribute \src "libresoc.v:113007.7-113007.20" + process $proc$libresoc.v:113007$4360 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111975.3-112011.6" - process $proc$libresoc.v:111975$4292 + attribute \src "libresoc.v:113355.3-113391.6" + process $proc$libresoc.v:113355$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:111976.5-111976.29" + attribute \src "libresoc.v:113356.5-113356.29" switch \initial - attribute \src "libresoc.v:111976.9-111976.17" + attribute \src "libresoc.v:113356.9-113356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174362,18 +176423,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:112012.3-112048.6" - process $proc$libresoc.v:112012$4293 + attribute \src "libresoc.v:113392.3-113428.6" + process $proc$libresoc.v:113392$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112013.5-112013.29" + attribute \src "libresoc.v:113393.5-113393.29" switch \initial - attribute \src "libresoc.v:112013.9-112013.17" + attribute \src "libresoc.v:113393.9-113393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174421,18 +176482,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:112049.3-112085.6" - process $proc$libresoc.v:112049$4294 + attribute \src "libresoc.v:113429.3-113465.6" + process $proc$libresoc.v:113429$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112050.5-112050.29" + attribute \src "libresoc.v:113430.5-113430.29" switch \initial - attribute \src "libresoc.v:112050.9-112050.17" + attribute \src "libresoc.v:113430.9-113430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174480,18 +176541,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:112086.3-112122.6" - process $proc$libresoc.v:112086$4295 + attribute \src "libresoc.v:113466.3-113502.6" + process $proc$libresoc.v:113466$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112087.5-112087.29" + attribute \src "libresoc.v:113467.5-113467.29" switch \initial - attribute \src "libresoc.v:112087.9-112087.17" + attribute \src "libresoc.v:113467.9-113467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174539,18 +176600,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:112123.3-112159.6" - process $proc$libresoc.v:112123$4296 + attribute \src "libresoc.v:113503.3-113539.6" + process $proc$libresoc.v:113503$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112124.5-112124.29" + attribute \src "libresoc.v:113504.5-113504.29" switch \initial - attribute \src "libresoc.v:112124.9-112124.17" + attribute \src "libresoc.v:113504.9-113504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174598,18 +176659,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:112160.3-112196.6" - process $proc$libresoc.v:112160$4297 + attribute \src "libresoc.v:113540.3-113576.6" + process $proc$libresoc.v:113540$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112161.5-112161.29" + attribute \src "libresoc.v:113541.5-113541.29" switch \initial - attribute \src "libresoc.v:112161.9-112161.17" + attribute \src "libresoc.v:113541.9-113541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174657,18 +176718,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:112197.3-112233.6" - process $proc$libresoc.v:112197$4298 + attribute \src "libresoc.v:113577.3-113613.6" + process $proc$libresoc.v:113577$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112198.5-112198.29" + attribute \src "libresoc.v:113578.5-113578.29" switch \initial - attribute \src "libresoc.v:112198.9-112198.17" + attribute \src "libresoc.v:113578.9-113578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174716,18 +176777,77 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:112234.3-112270.6" - process $proc$libresoc.v:112234$4299 + attribute \src "libresoc.v:113614.3-113650.6" + process $proc$libresoc.v:113614$4334 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113615.5-113615.29" + switch \initial + attribute \src "libresoc.v:113615.9-113615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] + end + attribute \src "libresoc.v:113651.3-113687.6" + process $proc$libresoc.v:113651$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112235.5-112235.29" + attribute \src "libresoc.v:113652.5-113652.29" switch \initial - attribute \src "libresoc.v:112235.9-112235.17" + attribute \src "libresoc.v:113652.9-113652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174775,18 +176895,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:112271.3-112307.6" - process $proc$libresoc.v:112271$4300 + attribute \src "libresoc.v:113688.3-113724.6" + process $proc$libresoc.v:113688$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112272.5-112272.29" + attribute \src "libresoc.v:113689.5-113689.29" switch \initial - attribute \src "libresoc.v:112272.9-112272.17" + attribute \src "libresoc.v:113689.9-113689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174834,18 +176954,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:112308.3-112344.6" - process $proc$libresoc.v:112308$4301 + attribute \src "libresoc.v:113725.3-113761.6" + process $proc$libresoc.v:113725$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112309.5-112309.29" + attribute \src "libresoc.v:113726.5-113726.29" switch \initial - attribute \src "libresoc.v:112309.9-112309.17" + attribute \src "libresoc.v:113726.9-113726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174893,136 +177013,136 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:112345.3-112381.6" - process $proc$libresoc.v:112345$4302 + attribute \src "libresoc.v:113762.3-113798.6" + process $proc$libresoc.v:113762$4338 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:112346.5-112346.29" + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:113763.5-113763.29" switch \initial - attribute \src "libresoc.v:112346.9-112346.17" + attribute \src "libresoc.v:113763.9-113763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:112382.3-112418.6" - process $proc$libresoc.v:112382$4303 + attribute \src "libresoc.v:113799.3-113835.6" + process $proc$libresoc.v:113799$4339 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112383.5-112383.29" + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:113800.5-113800.29" switch \initial - attribute \src "libresoc.v:112383.9-112383.17" + attribute \src "libresoc.v:113800.9-113800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 end sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:112419.3-112455.6" - process $proc$libresoc.v:112419$4304 + attribute \src "libresoc.v:113836.3-113872.6" + process $proc$libresoc.v:113836$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112420.5-112420.29" + attribute \src "libresoc.v:113837.5-113837.29" switch \initial - attribute \src "libresoc.v:112420.9-112420.17" + attribute \src "libresoc.v:113837.9-113837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175070,18 +177190,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:112456.3-112492.6" - process $proc$libresoc.v:112456$4305 + attribute \src "libresoc.v:113873.3-113909.6" + process $proc$libresoc.v:113873$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112457.5-112457.29" + attribute \src "libresoc.v:113874.5-113874.29" switch \initial - attribute \src "libresoc.v:112457.9-112457.17" + attribute \src "libresoc.v:113874.9-113874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175129,18 +177249,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:112493.3-112529.6" - process $proc$libresoc.v:112493$4306 + attribute \src "libresoc.v:113910.3-113946.6" + process $proc$libresoc.v:113910$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112494.5-112494.29" + attribute \src "libresoc.v:113911.5-113911.29" switch \initial - attribute \src "libresoc.v:112494.9-112494.17" + attribute \src "libresoc.v:113911.9-113911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175188,18 +177308,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:112530.3-112566.6" - process $proc$libresoc.v:112530$4307 + attribute \src "libresoc.v:113947.3-113983.6" + process $proc$libresoc.v:113947$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112531.5-112531.29" + attribute \src "libresoc.v:113948.5-113948.29" switch \initial - attribute \src "libresoc.v:112531.9-112531.17" + attribute \src "libresoc.v:113948.9-113948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175247,18 +177367,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:112567.3-112603.6" - process $proc$libresoc.v:112567$4308 + attribute \src "libresoc.v:113984.3-114020.6" + process $proc$libresoc.v:113984$4344 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112568.5-112568.29" + attribute \src "libresoc.v:113985.5-113985.29" switch \initial - attribute \src "libresoc.v:112568.9-112568.17" + attribute \src "libresoc.v:113985.9-113985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175306,18 +177426,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:112604.3-112640.6" - process $proc$libresoc.v:112604$4309 + attribute \src "libresoc.v:114021.3-114057.6" + process $proc$libresoc.v:114021$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112605.5-112605.29" + attribute \src "libresoc.v:114022.5-114022.29" switch \initial - attribute \src "libresoc.v:112605.9-112605.17" + attribute \src "libresoc.v:114022.9-114022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175365,18 +177485,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:112641.3-112677.6" - process $proc$libresoc.v:112641$4310 + attribute \src "libresoc.v:114058.3-114094.6" + process $proc$libresoc.v:114058$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112642.5-112642.29" + attribute \src "libresoc.v:114059.5-114059.29" switch \initial - attribute \src "libresoc.v:112642.9-112642.17" + attribute \src "libresoc.v:114059.9-114059.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175424,18 +177544,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:112678.3-112714.6" - process $proc$libresoc.v:112678$4311 + attribute \src "libresoc.v:114095.3-114131.6" + process $proc$libresoc.v:114095$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112679.5-112679.29" + attribute \src "libresoc.v:114096.5-114096.29" switch \initial - attribute \src "libresoc.v:112679.9-112679.17" + attribute \src "libresoc.v:114096.9-114096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175483,18 +177603,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:112715.3-112751.6" - process $proc$libresoc.v:112715$4312 + attribute \src "libresoc.v:114132.3-114168.6" + process $proc$libresoc.v:114132$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112716.5-112716.29" + attribute \src "libresoc.v:114133.5-114133.29" switch \initial - attribute \src "libresoc.v:112716.9-112716.17" + attribute \src "libresoc.v:114133.9-114133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175542,136 +177662,136 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:112752.3-112788.6" - process $proc$libresoc.v:112752$4313 + attribute \src "libresoc.v:114169.3-114205.6" + process $proc$libresoc.v:114169$4349 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112753.5-112753.29" + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:114170.5-114170.29" switch \initial - attribute \src "libresoc.v:112753.9-112753.17" + attribute \src "libresoc.v:114170.9-114170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'00000 end sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:112789.3-112825.6" - process $proc$libresoc.v:112789$4314 + attribute \src "libresoc.v:114206.3-114242.6" + process $proc$libresoc.v:114206$4350 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:112790.5-112790.29" + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:114207.5-114207.29" switch \initial - attribute \src "libresoc.v:112790.9-112790.17" + attribute \src "libresoc.v:114207.9-114207.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:112826.3-112862.6" - process $proc$libresoc.v:112826$4315 + attribute \src "libresoc.v:114243.3-114279.6" + process $proc$libresoc.v:114243$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112827.5-112827.29" + attribute \src "libresoc.v:114244.5-114244.29" switch \initial - attribute \src "libresoc.v:112827.9-112827.17" + attribute \src "libresoc.v:114244.9-114244.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175719,18 +177839,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:112863.3-112899.6" - process $proc$libresoc.v:112863$4316 + attribute \src "libresoc.v:114280.3-114316.6" + process $proc$libresoc.v:114280$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:112864.5-112864.29" + attribute \src "libresoc.v:114281.5-114281.29" switch \initial - attribute \src "libresoc.v:112864.9-112864.17" + attribute \src "libresoc.v:114281.9-114281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175778,18 +177898,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:112900.3-112936.6" - process $proc$libresoc.v:112900$4317 + attribute \src "libresoc.v:114317.3-114353.6" + process $proc$libresoc.v:114317$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112901.5-112901.29" + attribute \src "libresoc.v:114318.5-114318.29" switch \initial - attribute \src "libresoc.v:112901.9-112901.17" + attribute \src "libresoc.v:114318.9-114318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175837,18 +177957,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:112937.3-112973.6" - process $proc$libresoc.v:112937$4318 + attribute \src "libresoc.v:114354.3-114390.6" + process $proc$libresoc.v:114354$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112938.5-112938.29" + attribute \src "libresoc.v:114355.5-114355.29" switch \initial - attribute \src "libresoc.v:112938.9-112938.17" + attribute \src "libresoc.v:114355.9-114355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175896,18 +178016,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:112974.3-113010.6" - process $proc$libresoc.v:112974$4319 + attribute \src "libresoc.v:114391.3-114427.6" + process $proc$libresoc.v:114391$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112975.5-112975.29" + attribute \src "libresoc.v:114392.5-114392.29" switch \initial - attribute \src "libresoc.v:112975.9-112975.17" + attribute \src "libresoc.v:114392.9-114392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175955,18 +178075,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:113011.3-113047.6" - process $proc$libresoc.v:113011$4320 + attribute \src "libresoc.v:114428.3-114464.6" + process $proc$libresoc.v:114428$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113012.5-113012.29" + attribute \src "libresoc.v:114429.5-114429.29" switch \initial - attribute \src "libresoc.v:113012.9-113012.17" + attribute \src "libresoc.v:114429.9-114429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176014,18 +178134,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:113048.3-113084.6" - process $proc$libresoc.v:113048$4321 + attribute \src "libresoc.v:114465.3-114501.6" + process $proc$libresoc.v:114465$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113049.5-113049.29" + attribute \src "libresoc.v:114466.5-114466.29" switch \initial - attribute \src "libresoc.v:113049.9-113049.17" + attribute \src "libresoc.v:114466.9-114466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176073,18 +178193,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:113085.3-113121.6" - process $proc$libresoc.v:113085$4322 + attribute \src "libresoc.v:114502.3-114538.6" + process $proc$libresoc.v:114502$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113086.5-113086.29" + attribute \src "libresoc.v:114503.5-114503.29" switch \initial - attribute \src "libresoc.v:113086.9-113086.17" + attribute \src "libresoc.v:114503.9-114503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176132,18 +178252,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:113122.3-113158.6" - process $proc$libresoc.v:113122$4323 + attribute \src "libresoc.v:114539.3-114575.6" + process $proc$libresoc.v:114539$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113123.5-113123.29" + attribute \src "libresoc.v:114540.5-114540.29" switch \initial - attribute \src "libresoc.v:113123.9-113123.17" + attribute \src "libresoc.v:114540.9-114540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176193,157 +178313,161 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113164.1-113920.10" +attribute \src "libresoc.v:114581.1-115360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:113841.3-113853.6" + attribute \src "libresoc.v:115281.3-115293.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113854.3-113866.6" + attribute \src "libresoc.v:115294.3-115306.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113685.3-113697.6" + attribute \src "libresoc.v:115125.3-115137.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113737.3-113749.6" + attribute \src "libresoc.v:115177.3-115189.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113516.3-113528.6" + attribute \src "libresoc.v:114943.3-114955.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113529.3-113541.6" + attribute \src "libresoc.v:114956.3-114968.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113672.3-113684.6" + attribute \src "libresoc.v:115112.3-115124.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113724.3-113736.6" + attribute \src "libresoc.v:115164.3-115176.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113789.3-113801.6" + attribute \src "libresoc.v:115216.3-115228.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113503.3-113515.6" + attribute \src "libresoc.v:114930.3-114942.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113867.3-113879.6" + attribute \src "libresoc.v:115307.3-115319.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113880.3-113892.6" + attribute \src "libresoc.v:115320.3-115332.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113893.3-113905.6" + attribute \src "libresoc.v:115333.3-115345.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113646.3-113658.6" + attribute \src "libresoc.v:115073.3-115085.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113698.3-113710.6" + attribute \src "libresoc.v:115138.3-115150.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113711.3-113723.6" + attribute \src "libresoc.v:115151.3-115163.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113776.3-113788.6" + attribute \src "libresoc.v:115229.3-115241.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113620.3-113632.6" + attribute \src "libresoc.v:115060.3-115072.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113815.3-113827.6" + attribute \src "libresoc.v:115255.3-115267.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113906.3-113918.6" + attribute \src "libresoc.v:115346.3-115358.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113659.3-113671.6" + attribute \src "libresoc.v:115099.3-115111.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113763.3-113775.6" + attribute \src "libresoc.v:115203.3-115215.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113828.3-113840.6" + attribute \src "libresoc.v:115268.3-115280.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113802.3-113814.6" + attribute \src "libresoc.v:115242.3-115254.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113750.3-113762.6" + attribute \src "libresoc.v:115190.3-115202.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113594.3-113606.6" + attribute \src "libresoc.v:115034.3-115046.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113607.3-113619.6" + attribute \src "libresoc.v:115047.3-115059.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113542.3-113554.6" + attribute \src "libresoc.v:114969.3-114981.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113555.3-113567.6" + attribute \src "libresoc.v:114982.3-114994.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113568.3-113580.6" + attribute \src "libresoc.v:114995.3-115007.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113581.3-113593.6" + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113633.3-113645.6" + attribute \src "libresoc.v:115086.3-115098.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:113165.7-113165.20" + attribute \src "libresoc.v:114582.7-114582.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113841.3-113853.6" + attribute \src "libresoc.v:115281.3-115293.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113854.3-113866.6" + attribute \src "libresoc.v:115294.3-115306.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113685.3-113697.6" + attribute \src "libresoc.v:115125.3-115137.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113737.3-113749.6" + attribute \src "libresoc.v:115177.3-115189.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113516.3-113528.6" + attribute \src "libresoc.v:114943.3-114955.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113529.3-113541.6" + attribute \src "libresoc.v:114956.3-114968.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113672.3-113684.6" + attribute \src "libresoc.v:115112.3-115124.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113724.3-113736.6" + attribute \src "libresoc.v:115164.3-115176.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113789.3-113801.6" + attribute \src "libresoc.v:115216.3-115228.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113503.3-113515.6" + attribute \src "libresoc.v:114930.3-114942.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113867.3-113879.6" + attribute \src "libresoc.v:115307.3-115319.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113880.3-113892.6" + attribute \src "libresoc.v:115320.3-115332.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113893.3-113905.6" + attribute \src "libresoc.v:115333.3-115345.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113646.3-113658.6" + attribute \src "libresoc.v:115073.3-115085.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113698.3-113710.6" + attribute \src "libresoc.v:115138.3-115150.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113711.3-113723.6" + attribute \src "libresoc.v:115151.3-115163.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113776.3-113788.6" + attribute \src "libresoc.v:115229.3-115241.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113620.3-113632.6" + attribute \src "libresoc.v:115060.3-115072.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113815.3-113827.6" + attribute \src "libresoc.v:115255.3-115267.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113906.3-113918.6" + attribute \src "libresoc.v:115346.3-115358.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113659.3-113671.6" + attribute \src "libresoc.v:115099.3-115111.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113763.3-113775.6" + attribute \src "libresoc.v:115203.3-115215.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113828.3-113840.6" + attribute \src "libresoc.v:115268.3-115280.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113802.3-113814.6" + attribute \src "libresoc.v:115242.3-115254.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113750.3-113762.6" + attribute \src "libresoc.v:115190.3-115202.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113594.3-113606.6" + attribute \src "libresoc.v:115034.3-115046.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113607.3-113619.6" + attribute \src "libresoc.v:115047.3-115059.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113542.3-113554.6" + attribute \src "libresoc.v:114969.3-114981.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113555.3-113567.6" + attribute \src "libresoc.v:114982.3-114994.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113568.3-113580.6" + attribute \src "libresoc.v:114995.3-115007.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113581.3-113593.6" + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113633.3-113645.6" + attribute \src "libresoc.v:115086.3-115098.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub4_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub4_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub4_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -176353,7 +178477,7 @@ module \dec31_dec_sub4 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -176362,16 +178486,16 @@ module \dec31_dec_sub4 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub4_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -176403,7 +178527,7 @@ module \dec31_dec_sub4 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -176420,7 +178544,7 @@ module \dec31_dec_sub4 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -176428,7 +178552,7 @@ module \dec31_dec_sub4 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -176445,13 +178569,13 @@ module \dec31_dec_sub4 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -176528,46 +178652,46 @@ module \dec31_dec_sub4 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub4_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub4_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub4_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub4_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176575,8 +178699,8 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub4_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub4_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176584,8 +178708,8 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub4_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub4_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176593,7 +178717,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub4_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176602,7 +178726,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub4_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176611,7 +178735,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub4_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176620,41 +178744,50 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub4_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub4_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub4_upd - attribute \src "libresoc.v:113165.7-113165.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub4_upd + attribute \src "libresoc.v:114582.7-114582.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113165.7-113165.20" - process $proc$libresoc.v:113165$4357 + attribute \src "libresoc.v:114582.7-114582.20" + process $proc$libresoc.v:114582$4394 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113503.3-113515.6" - process $proc$libresoc.v:113503$4325 + attribute \src "libresoc.v:114930.3-114942.6" + process $proc$libresoc.v:114930$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113504.5-113504.29" + attribute \src "libresoc.v:114931.5-114931.29" switch \initial - attribute \src "libresoc.v:113504.9-113504.17" + attribute \src "libresoc.v:114931.9-114931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176670,18 +178803,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:113516.3-113528.6" - process $proc$libresoc.v:113516$4326 + attribute \src "libresoc.v:114943.3-114955.6" + process $proc$libresoc.v:114943$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113517.5-113517.29" + attribute \src "libresoc.v:114944.5-114944.29" switch \initial - attribute \src "libresoc.v:113517.9-113517.17" + attribute \src "libresoc.v:114944.9-114944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176697,18 +178830,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:113529.3-113541.6" - process $proc$libresoc.v:113529$4327 + attribute \src "libresoc.v:114956.3-114968.6" + process $proc$libresoc.v:114956$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113530.5-113530.29" + attribute \src "libresoc.v:114957.5-114957.29" switch \initial - attribute \src "libresoc.v:113530.9-113530.17" + attribute \src "libresoc.v:114957.9-114957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176724,18 +178857,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:113542.3-113554.6" - process $proc$libresoc.v:113542$4328 + attribute \src "libresoc.v:114969.3-114981.6" + process $proc$libresoc.v:114969$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113543.5-113543.29" + attribute \src "libresoc.v:114970.5-114970.29" switch \initial - attribute \src "libresoc.v:113543.9-113543.17" + attribute \src "libresoc.v:114970.9-114970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176751,18 +178884,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:113555.3-113567.6" - process $proc$libresoc.v:113555$4329 + attribute \src "libresoc.v:114982.3-114994.6" + process $proc$libresoc.v:114982$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113556.5-113556.29" + attribute \src "libresoc.v:114983.5-114983.29" switch \initial - attribute \src "libresoc.v:113556.9-113556.17" + attribute \src "libresoc.v:114983.9-114983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176778,18 +178911,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:113568.3-113580.6" - process $proc$libresoc.v:113568$4330 + attribute \src "libresoc.v:114995.3-115007.6" + process $proc$libresoc.v:114995$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113569.5-113569.29" + attribute \src "libresoc.v:114996.5-114996.29" switch \initial - attribute \src "libresoc.v:113569.9-113569.17" + attribute \src "libresoc.v:114996.9-114996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176805,18 +178938,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:113581.3-113593.6" - process $proc$libresoc.v:113581$4331 + attribute \src "libresoc.v:115008.3-115020.6" + process $proc$libresoc.v:115008$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113582.5-113582.29" + attribute \src "libresoc.v:115009.5-115009.29" switch \initial - attribute \src "libresoc.v:113582.9-113582.17" + attribute \src "libresoc.v:115009.9-115009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176832,18 +178965,45 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:113594.3-113606.6" - process $proc$libresoc.v:113594$4332 + attribute \src "libresoc.v:115021.3-115033.6" + process $proc$libresoc.v:115021$4368 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115022.5-115022.29" + switch \initial + attribute \src "libresoc.v:115022.9-115022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] + end + attribute \src "libresoc.v:115034.3-115046.6" + process $proc$libresoc.v:115034$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113595.5-113595.29" + attribute \src "libresoc.v:115035.5-115035.29" switch \initial - attribute \src "libresoc.v:113595.9-113595.17" + attribute \src "libresoc.v:115035.9-115035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176859,18 +179019,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:113607.3-113619.6" - process $proc$libresoc.v:113607$4333 + attribute \src "libresoc.v:115047.3-115059.6" + process $proc$libresoc.v:115047$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113608.5-113608.29" + attribute \src "libresoc.v:115048.5-115048.29" switch \initial - attribute \src "libresoc.v:113608.9-113608.17" + attribute \src "libresoc.v:115048.9-115048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176886,18 +179046,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:113620.3-113632.6" - process $proc$libresoc.v:113620$4334 + attribute \src "libresoc.v:115060.3-115072.6" + process $proc$libresoc.v:115060$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113621.5-113621.29" + attribute \src "libresoc.v:115061.5-115061.29" switch \initial - attribute \src "libresoc.v:113621.9-113621.17" + attribute \src "libresoc.v:115061.9-115061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176913,72 +179073,72 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:113633.3-113645.6" - process $proc$libresoc.v:113633$4335 + attribute \src "libresoc.v:115073.3-115085.6" + process $proc$libresoc.v:115073$4372 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:113634.5-113634.29" + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:115074.5-115074.29" switch \initial - attribute \src "libresoc.v:113634.9-113634.17" + attribute \src "libresoc.v:115074.9-115074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:113646.3-113658.6" - process $proc$libresoc.v:113646$4336 + attribute \src "libresoc.v:115086.3-115098.6" + process $proc$libresoc.v:115086$4373 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113647.5-113647.29" + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:115087.5-115087.29" switch \initial - attribute \src "libresoc.v:113647.9-113647.17" + attribute \src "libresoc.v:115087.9-115087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 end sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:113659.3-113671.6" - process $proc$libresoc.v:113659$4337 + attribute \src "libresoc.v:115099.3-115111.6" + process $proc$libresoc.v:115099$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113660.5-113660.29" + attribute \src "libresoc.v:115100.5-115100.29" switch \initial - attribute \src "libresoc.v:113660.9-113660.17" + attribute \src "libresoc.v:115100.9-115100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176994,18 +179154,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:113672.3-113684.6" - process $proc$libresoc.v:113672$4338 + attribute \src "libresoc.v:115112.3-115124.6" + process $proc$libresoc.v:115112$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113673.5-113673.29" + attribute \src "libresoc.v:115113.5-115113.29" switch \initial - attribute \src "libresoc.v:113673.9-113673.17" + attribute \src "libresoc.v:115113.9-115113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177021,18 +179181,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:113685.3-113697.6" - process $proc$libresoc.v:113685$4339 + attribute \src "libresoc.v:115125.3-115137.6" + process $proc$libresoc.v:115125$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113686.5-113686.29" + attribute \src "libresoc.v:115126.5-115126.29" switch \initial - attribute \src "libresoc.v:113686.9-113686.17" + attribute \src "libresoc.v:115126.9-115126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177048,18 +179208,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:113698.3-113710.6" - process $proc$libresoc.v:113698$4340 + attribute \src "libresoc.v:115138.3-115150.6" + process $proc$libresoc.v:115138$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113699.5-113699.29" + attribute \src "libresoc.v:115139.5-115139.29" switch \initial - attribute \src "libresoc.v:113699.9-113699.17" + attribute \src "libresoc.v:115139.9-115139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177075,18 +179235,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:113711.3-113723.6" - process $proc$libresoc.v:113711$4341 + attribute \src "libresoc.v:115151.3-115163.6" + process $proc$libresoc.v:115151$4378 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113712.5-113712.29" + attribute \src "libresoc.v:115152.5-115152.29" switch \initial - attribute \src "libresoc.v:113712.9-113712.17" + attribute \src "libresoc.v:115152.9-115152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177102,18 +179262,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:113724.3-113736.6" - process $proc$libresoc.v:113724$4342 + attribute \src "libresoc.v:115164.3-115176.6" + process $proc$libresoc.v:115164$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113725.5-113725.29" + attribute \src "libresoc.v:115165.5-115165.29" switch \initial - attribute \src "libresoc.v:113725.9-113725.17" + attribute \src "libresoc.v:115165.9-115165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177129,18 +179289,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:113737.3-113749.6" - process $proc$libresoc.v:113737$4343 + attribute \src "libresoc.v:115177.3-115189.6" + process $proc$libresoc.v:115177$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113738.5-113738.29" + attribute \src "libresoc.v:115178.5-115178.29" switch \initial - attribute \src "libresoc.v:113738.9-113738.17" + attribute \src "libresoc.v:115178.9-115178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177156,18 +179316,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:113750.3-113762.6" - process $proc$libresoc.v:113750$4344 + attribute \src "libresoc.v:115190.3-115202.6" + process $proc$libresoc.v:115190$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113751.5-113751.29" + attribute \src "libresoc.v:115191.5-115191.29" switch \initial - attribute \src "libresoc.v:113751.9-113751.17" + attribute \src "libresoc.v:115191.9-115191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177183,18 +179343,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:113763.3-113775.6" - process $proc$libresoc.v:113763$4345 + attribute \src "libresoc.v:115203.3-115215.6" + process $proc$libresoc.v:115203$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113764.5-113764.29" + attribute \src "libresoc.v:115204.5-115204.29" switch \initial - attribute \src "libresoc.v:113764.9-113764.17" + attribute \src "libresoc.v:115204.9-115204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177210,72 +179370,72 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:113776.3-113788.6" - process $proc$libresoc.v:113776$4346 + attribute \src "libresoc.v:115216.3-115228.6" + process $proc$libresoc.v:115216$4383 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113777.5-113777.29" + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:115217.5-115217.29" switch \initial - attribute \src "libresoc.v:113777.9-113777.17" + attribute \src "libresoc.v:115217.9-115217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub4_form[4:0] 5'00000 end sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:113789.3-113801.6" - process $proc$libresoc.v:113789$4347 + attribute \src "libresoc.v:115229.3-115241.6" + process $proc$libresoc.v:115229$4384 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113790.5-113790.29" + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:115230.5-115230.29" switch \initial - attribute \src "libresoc.v:113790.9-113790.17" + attribute \src "libresoc.v:115230.9-115230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:113802.3-113814.6" - process $proc$libresoc.v:113802$4348 + attribute \src "libresoc.v:115242.3-115254.6" + process $proc$libresoc.v:115242$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113803.5-113803.29" + attribute \src "libresoc.v:115243.5-115243.29" switch \initial - attribute \src "libresoc.v:113803.9-113803.17" + attribute \src "libresoc.v:115243.9-115243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177291,18 +179451,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:113815.3-113827.6" - process $proc$libresoc.v:113815$4349 + attribute \src "libresoc.v:115255.3-115267.6" + process $proc$libresoc.v:115255$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113816.5-113816.29" + attribute \src "libresoc.v:115256.5-115256.29" switch \initial - attribute \src "libresoc.v:113816.9-113816.17" + attribute \src "libresoc.v:115256.9-115256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177318,18 +179478,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:113828.3-113840.6" - process $proc$libresoc.v:113828$4350 + attribute \src "libresoc.v:115268.3-115280.6" + process $proc$libresoc.v:115268$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113829.5-113829.29" + attribute \src "libresoc.v:115269.5-115269.29" switch \initial - attribute \src "libresoc.v:113829.9-113829.17" + attribute \src "libresoc.v:115269.9-115269.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177345,18 +179505,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:113841.3-113853.6" - process $proc$libresoc.v:113841$4351 + attribute \src "libresoc.v:115281.3-115293.6" + process $proc$libresoc.v:115281$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113842.5-113842.29" + attribute \src "libresoc.v:115282.5-115282.29" switch \initial - attribute \src "libresoc.v:113842.9-113842.17" + attribute \src "libresoc.v:115282.9-115282.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177372,18 +179532,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:113854.3-113866.6" - process $proc$libresoc.v:113854$4352 + attribute \src "libresoc.v:115294.3-115306.6" + process $proc$libresoc.v:115294$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113855.5-113855.29" + attribute \src "libresoc.v:115295.5-115295.29" switch \initial - attribute \src "libresoc.v:113855.9-113855.17" + attribute \src "libresoc.v:115295.9-115295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177399,18 +179559,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:113867.3-113879.6" - process $proc$libresoc.v:113867$4353 + attribute \src "libresoc.v:115307.3-115319.6" + process $proc$libresoc.v:115307$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113868.5-113868.29" + attribute \src "libresoc.v:115308.5-115308.29" switch \initial - attribute \src "libresoc.v:113868.9-113868.17" + attribute \src "libresoc.v:115308.9-115308.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177426,18 +179586,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:113880.3-113892.6" - process $proc$libresoc.v:113880$4354 + attribute \src "libresoc.v:115320.3-115332.6" + process $proc$libresoc.v:115320$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113881.5-113881.29" + attribute \src "libresoc.v:115321.5-115321.29" switch \initial - attribute \src "libresoc.v:113881.9-113881.17" + attribute \src "libresoc.v:115321.9-115321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177453,18 +179613,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:113893.3-113905.6" - process $proc$libresoc.v:113893$4355 + attribute \src "libresoc.v:115333.3-115345.6" + process $proc$libresoc.v:115333$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113894.5-113894.29" + attribute \src "libresoc.v:115334.5-115334.29" switch \initial - attribute \src "libresoc.v:113894.9-113894.17" + attribute \src "libresoc.v:115334.9-115334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177480,18 +179640,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:113906.3-113918.6" - process $proc$libresoc.v:113906$4356 + attribute \src "libresoc.v:115346.3-115358.6" + process $proc$libresoc.v:115346$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113907.5-113907.29" + attribute \src "libresoc.v:115347.5-115347.29" switch \initial - attribute \src "libresoc.v:113907.9-113907.17" + attribute \src "libresoc.v:115347.9-115347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177509,157 +179669,161 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113924.1-115640.10" +attribute \src "libresoc.v:115364.1-117133.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:115381.3-115423.6" + attribute \src "libresoc.v:116874.3-116916.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115424.3-115466.6" + attribute \src "libresoc.v:116917.3-116959.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114865.3-114907.6" + attribute \src "libresoc.v:116358.3-116400.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:115037.3-115079.6" + attribute \src "libresoc.v:116530.3-116572.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:114306.3-114348.6" + attribute \src "libresoc.v:115756.3-115798.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114349.3-114391.6" + attribute \src "libresoc.v:115799.3-115841.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114822.3-114864.6" + attribute \src "libresoc.v:116315.3-116357.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114994.3-115036.6" + attribute \src "libresoc.v:116487.3-116529.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:115209.3-115251.6" + attribute \src "libresoc.v:116659.3-116701.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:114263.3-114305.6" + attribute \src "libresoc.v:115713.3-115755.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115467.3-115509.6" + attribute \src "libresoc.v:116960.3-117002.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115510.3-115552.6" + attribute \src "libresoc.v:117003.3-117045.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115553.3-115595.6" + attribute \src "libresoc.v:117046.3-117088.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:114736.3-114778.6" + attribute \src "libresoc.v:116186.3-116228.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114908.3-114950.6" + attribute \src "libresoc.v:116401.3-116443.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114951.3-114993.6" + attribute \src "libresoc.v:116444.3-116486.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:115166.3-115208.6" + attribute \src "libresoc.v:116702.3-116744.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:114650.3-114692.6" + attribute \src "libresoc.v:116143.3-116185.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:115295.3-115337.6" + attribute \src "libresoc.v:116788.3-116830.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115596.3-115638.6" + attribute \src "libresoc.v:117089.3-117131.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:114779.3-114821.6" + attribute \src "libresoc.v:116272.3-116314.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:115123.3-115165.6" + attribute \src "libresoc.v:116616.3-116658.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115338.3-115380.6" + attribute \src "libresoc.v:116831.3-116873.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115252.3-115294.6" + attribute \src "libresoc.v:116745.3-116787.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115080.3-115122.6" + attribute \src "libresoc.v:116573.3-116615.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:114564.3-114606.6" + attribute \src "libresoc.v:116057.3-116099.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114607.3-114649.6" + attribute \src "libresoc.v:116100.3-116142.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114392.3-114434.6" + attribute \src "libresoc.v:115842.3-115884.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114435.3-114477.6" + attribute \src "libresoc.v:115885.3-115927.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114478.3-114520.6" + attribute \src "libresoc.v:115928.3-115970.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114521.3-114563.6" + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114693.3-114735.6" + attribute \src "libresoc.v:116229.3-116271.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:113925.7-113925.20" + attribute \src "libresoc.v:115365.7-115365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115381.3-115423.6" + attribute \src "libresoc.v:116874.3-116916.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115424.3-115466.6" + attribute \src "libresoc.v:116917.3-116959.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114865.3-114907.6" + attribute \src "libresoc.v:116358.3-116400.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:115037.3-115079.6" + attribute \src "libresoc.v:116530.3-116572.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:114306.3-114348.6" + attribute \src "libresoc.v:115756.3-115798.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114349.3-114391.6" + attribute \src "libresoc.v:115799.3-115841.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114822.3-114864.6" + attribute \src "libresoc.v:116315.3-116357.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114994.3-115036.6" + attribute \src "libresoc.v:116487.3-116529.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:115209.3-115251.6" + attribute \src "libresoc.v:116659.3-116701.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:114263.3-114305.6" + attribute \src "libresoc.v:115713.3-115755.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115467.3-115509.6" + attribute \src "libresoc.v:116960.3-117002.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115510.3-115552.6" + attribute \src "libresoc.v:117003.3-117045.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115553.3-115595.6" + attribute \src "libresoc.v:117046.3-117088.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:114736.3-114778.6" + attribute \src "libresoc.v:116186.3-116228.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114908.3-114950.6" + attribute \src "libresoc.v:116401.3-116443.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114951.3-114993.6" + attribute \src "libresoc.v:116444.3-116486.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:115166.3-115208.6" + attribute \src "libresoc.v:116702.3-116744.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:114650.3-114692.6" + attribute \src "libresoc.v:116143.3-116185.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:115295.3-115337.6" + attribute \src "libresoc.v:116788.3-116830.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115596.3-115638.6" + attribute \src "libresoc.v:117089.3-117131.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:114779.3-114821.6" + attribute \src "libresoc.v:116272.3-116314.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:115123.3-115165.6" + attribute \src "libresoc.v:116616.3-116658.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115338.3-115380.6" + attribute \src "libresoc.v:116831.3-116873.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115252.3-115294.6" + attribute \src "libresoc.v:116745.3-116787.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115080.3-115122.6" + attribute \src "libresoc.v:116573.3-116615.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:114564.3-114606.6" + attribute \src "libresoc.v:116057.3-116099.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114607.3-114649.6" + attribute \src "libresoc.v:116100.3-116142.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114392.3-114434.6" + attribute \src "libresoc.v:115842.3-115884.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114435.3-114477.6" + attribute \src "libresoc.v:115885.3-115927.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114478.3-114520.6" + attribute \src "libresoc.v:115928.3-115970.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114521.3-114563.6" + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114693.3-114735.6" + attribute \src "libresoc.v:116229.3-116271.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub8_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub8_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub8_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -177669,7 +179833,7 @@ module \dec31_dec_sub8 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -177678,16 +179842,16 @@ module \dec31_dec_sub8 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub8_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -177719,7 +179883,7 @@ module \dec31_dec_sub8 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -177736,7 +179900,7 @@ module \dec31_dec_sub8 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -177744,7 +179908,7 @@ module \dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -177761,13 +179925,13 @@ module \dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -177844,46 +180008,46 @@ module \dec31_dec_sub8 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub8_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub8_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub8_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub8_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177891,8 +180055,8 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub8_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub8_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177900,8 +180064,8 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub8_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub8_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177909,7 +180073,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub8_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177918,7 +180082,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub8_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177927,7 +180091,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub8_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177936,41 +180100,50 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub8_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub8_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub8_upd - attribute \src "libresoc.v:113925.7-113925.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub8_upd + attribute \src "libresoc.v:115365.7-115365.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113925.7-113925.20" - process $proc$libresoc.v:113925$4390 + attribute \src "libresoc.v:115365.7-115365.20" + process $proc$libresoc.v:115365$4428 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114263.3-114305.6" - process $proc$libresoc.v:114263$4358 + attribute \src "libresoc.v:115713.3-115755.6" + process $proc$libresoc.v:115713$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:114264.5-114264.29" + attribute \src "libresoc.v:115714.5-115714.29" switch \initial - attribute \src "libresoc.v:114264.9-114264.17" + attribute \src "libresoc.v:115714.9-115714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178026,18 +180199,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:114306.3-114348.6" - process $proc$libresoc.v:114306$4359 + attribute \src "libresoc.v:115756.3-115798.6" + process $proc$libresoc.v:115756$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114307.5-114307.29" + attribute \src "libresoc.v:115757.5-115757.29" switch \initial - attribute \src "libresoc.v:114307.9-114307.17" + attribute \src "libresoc.v:115757.9-115757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178093,18 +180266,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:114349.3-114391.6" - process $proc$libresoc.v:114349$4360 + attribute \src "libresoc.v:115799.3-115841.6" + process $proc$libresoc.v:115799$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114350.5-114350.29" + attribute \src "libresoc.v:115800.5-115800.29" switch \initial - attribute \src "libresoc.v:114350.9-114350.17" + attribute \src "libresoc.v:115800.9-115800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178160,18 +180333,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:114392.3-114434.6" - process $proc$libresoc.v:114392$4361 + attribute \src "libresoc.v:115842.3-115884.6" + process $proc$libresoc.v:115842$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114393.5-114393.29" + attribute \src "libresoc.v:115843.5-115843.29" switch \initial - attribute \src "libresoc.v:114393.9-114393.17" + attribute \src "libresoc.v:115843.9-115843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178227,18 +180400,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:114435.3-114477.6" - process $proc$libresoc.v:114435$4362 + attribute \src "libresoc.v:115885.3-115927.6" + process $proc$libresoc.v:115885$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114436.5-114436.29" + attribute \src "libresoc.v:115886.5-115886.29" switch \initial - attribute \src "libresoc.v:114436.9-114436.17" + attribute \src "libresoc.v:115886.9-115886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178294,18 +180467,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:114478.3-114520.6" - process $proc$libresoc.v:114478$4363 + attribute \src "libresoc.v:115928.3-115970.6" + process $proc$libresoc.v:115928$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114479.5-114479.29" + attribute \src "libresoc.v:115929.5-115929.29" switch \initial - attribute \src "libresoc.v:114479.9-114479.17" + attribute \src "libresoc.v:115929.9-115929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178361,18 +180534,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:114521.3-114563.6" - process $proc$libresoc.v:114521$4364 + attribute \src "libresoc.v:115971.3-116013.6" + process $proc$libresoc.v:115971$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114522.5-114522.29" + attribute \src "libresoc.v:115972.5-115972.29" switch \initial - attribute \src "libresoc.v:114522.9-114522.17" + attribute \src "libresoc.v:115972.9-115972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178428,18 +180601,85 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:114564.3-114606.6" - process $proc$libresoc.v:114564$4365 + attribute \src "libresoc.v:116014.3-116056.6" + process $proc$libresoc.v:116014$4402 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:116015.5-116015.29" + switch \initial + attribute \src "libresoc.v:116015.9-116015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] + end + attribute \src "libresoc.v:116057.3-116099.6" + process $proc$libresoc.v:116057$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114565.5-114565.29" + attribute \src "libresoc.v:116058.5-116058.29" switch \initial - attribute \src "libresoc.v:114565.9-114565.17" + attribute \src "libresoc.v:116058.9-116058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178495,18 +180735,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:114607.3-114649.6" - process $proc$libresoc.v:114607$4366 + attribute \src "libresoc.v:116100.3-116142.6" + process $proc$libresoc.v:116100$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114608.5-114608.29" + attribute \src "libresoc.v:116101.5-116101.29" switch \initial - attribute \src "libresoc.v:114608.9-114608.17" + attribute \src "libresoc.v:116101.9-116101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178562,18 +180802,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:114650.3-114692.6" - process $proc$libresoc.v:114650$4367 + attribute \src "libresoc.v:116143.3-116185.6" + process $proc$libresoc.v:116143$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:114651.5-114651.29" + attribute \src "libresoc.v:116144.5-116144.29" switch \initial - attribute \src "libresoc.v:114651.9-114651.17" + attribute \src "libresoc.v:116144.9-116144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178629,152 +180869,152 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:114693.3-114735.6" - process $proc$libresoc.v:114693$4368 + attribute \src "libresoc.v:116186.3-116228.6" + process $proc$libresoc.v:116186$4406 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:114694.5-114694.29" + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:116187.5-116187.29" switch \initial - attribute \src "libresoc.v:114694.9-114694.17" + attribute \src "libresoc.v:116187.9-116187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:114736.3-114778.6" - process $proc$libresoc.v:114736$4369 + attribute \src "libresoc.v:116229.3-116271.6" + process $proc$libresoc.v:116229$4407 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114737.5-114737.29" + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:116230.5-116230.29" switch \initial - attribute \src "libresoc.v:114737.9-114737.17" + attribute \src "libresoc.v:116230.9-116230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 end sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:114779.3-114821.6" - process $proc$libresoc.v:114779$4370 + attribute \src "libresoc.v:116272.3-116314.6" + process $proc$libresoc.v:116272$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:114780.5-114780.29" + attribute \src "libresoc.v:116273.5-116273.29" switch \initial - attribute \src "libresoc.v:114780.9-114780.17" + attribute \src "libresoc.v:116273.9-116273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178830,18 +181070,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:114822.3-114864.6" - process $proc$libresoc.v:114822$4371 + attribute \src "libresoc.v:116315.3-116357.6" + process $proc$libresoc.v:116315$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114823.5-114823.29" + attribute \src "libresoc.v:116316.5-116316.29" switch \initial - attribute \src "libresoc.v:114823.9-114823.17" + attribute \src "libresoc.v:116316.9-116316.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178897,18 +181137,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:114865.3-114907.6" - process $proc$libresoc.v:114865$4372 + attribute \src "libresoc.v:116358.3-116400.6" + process $proc$libresoc.v:116358$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:114866.5-114866.29" + attribute \src "libresoc.v:116359.5-116359.29" switch \initial - attribute \src "libresoc.v:114866.9-114866.17" + attribute \src "libresoc.v:116359.9-116359.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178964,18 +181204,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:114908.3-114950.6" - process $proc$libresoc.v:114908$4373 + attribute \src "libresoc.v:116401.3-116443.6" + process $proc$libresoc.v:116401$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114909.5-114909.29" + attribute \src "libresoc.v:116402.5-116402.29" switch \initial - attribute \src "libresoc.v:114909.9-114909.17" + attribute \src "libresoc.v:116402.9-116402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179031,18 +181271,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:114951.3-114993.6" - process $proc$libresoc.v:114951$4374 + attribute \src "libresoc.v:116444.3-116486.6" + process $proc$libresoc.v:116444$4412 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:114952.5-114952.29" + attribute \src "libresoc.v:116445.5-116445.29" switch \initial - attribute \src "libresoc.v:114952.9-114952.17" + attribute \src "libresoc.v:116445.9-116445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179098,18 +181338,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:114994.3-115036.6" - process $proc$libresoc.v:114994$4375 + attribute \src "libresoc.v:116487.3-116529.6" + process $proc$libresoc.v:116487$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:114995.5-114995.29" + attribute \src "libresoc.v:116488.5-116488.29" switch \initial - attribute \src "libresoc.v:114995.9-114995.17" + attribute \src "libresoc.v:116488.9-116488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179165,18 +181405,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:115037.3-115079.6" - process $proc$libresoc.v:115037$4376 + attribute \src "libresoc.v:116530.3-116572.6" + process $proc$libresoc.v:116530$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115038.5-115038.29" + attribute \src "libresoc.v:116531.5-116531.29" switch \initial - attribute \src "libresoc.v:115038.9-115038.17" + attribute \src "libresoc.v:116531.9-116531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179232,18 +181472,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:115080.3-115122.6" - process $proc$libresoc.v:115080$4377 + attribute \src "libresoc.v:116573.3-116615.6" + process $proc$libresoc.v:116573$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:115081.5-115081.29" + attribute \src "libresoc.v:116574.5-116574.29" switch \initial - attribute \src "libresoc.v:115081.9-115081.17" + attribute \src "libresoc.v:116574.9-116574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179299,18 +181539,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:115123.3-115165.6" - process $proc$libresoc.v:115123$4378 + attribute \src "libresoc.v:116616.3-116658.6" + process $proc$libresoc.v:116616$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115124.5-115124.29" + attribute \src "libresoc.v:116617.5-116617.29" switch \initial - attribute \src "libresoc.v:115124.9-115124.17" + attribute \src "libresoc.v:116617.9-116617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179366,152 +181606,152 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:115166.3-115208.6" - process $proc$libresoc.v:115166$4379 + attribute \src "libresoc.v:116659.3-116701.6" + process $proc$libresoc.v:116659$4417 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:115167.5-115167.29" + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:116660.5-116660.29" switch \initial - attribute \src "libresoc.v:115167.9-115167.17" + attribute \src "libresoc.v:116660.9-116660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'00000 end sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:115209.3-115251.6" - process $proc$libresoc.v:115209$4380 + attribute \src "libresoc.v:116702.3-116744.6" + process $proc$libresoc.v:116702$4418 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115210.5-115210.29" + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:116703.5-116703.29" switch \initial - attribute \src "libresoc.v:115210.9-115210.17" + attribute \src "libresoc.v:116703.9-116703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:115252.3-115294.6" - process $proc$libresoc.v:115252$4381 + attribute \src "libresoc.v:116745.3-116787.6" + process $proc$libresoc.v:116745$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115253.5-115253.29" + attribute \src "libresoc.v:116746.5-116746.29" switch \initial - attribute \src "libresoc.v:115253.9-115253.17" + attribute \src "libresoc.v:116746.9-116746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179567,18 +181807,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:115295.3-115337.6" - process $proc$libresoc.v:115295$4382 + attribute \src "libresoc.v:116788.3-116830.6" + process $proc$libresoc.v:116788$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115296.5-115296.29" + attribute \src "libresoc.v:116789.5-116789.29" switch \initial - attribute \src "libresoc.v:115296.9-115296.17" + attribute \src "libresoc.v:116789.9-116789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179634,18 +181874,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:115338.3-115380.6" - process $proc$libresoc.v:115338$4383 + attribute \src "libresoc.v:116831.3-116873.6" + process $proc$libresoc.v:116831$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115339.5-115339.29" + attribute \src "libresoc.v:116832.5-116832.29" switch \initial - attribute \src "libresoc.v:115339.9-115339.17" + attribute \src "libresoc.v:116832.9-116832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179701,18 +181941,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:115381.3-115423.6" - process $proc$libresoc.v:115381$4384 + attribute \src "libresoc.v:116874.3-116916.6" + process $proc$libresoc.v:116874$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115382.5-115382.29" + attribute \src "libresoc.v:116875.5-116875.29" switch \initial - attribute \src "libresoc.v:115382.9-115382.17" + attribute \src "libresoc.v:116875.9-116875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179768,18 +182008,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:115424.3-115466.6" - process $proc$libresoc.v:115424$4385 + attribute \src "libresoc.v:116917.3-116959.6" + process $proc$libresoc.v:116917$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:115425.5-115425.29" + attribute \src "libresoc.v:116918.5-116918.29" switch \initial - attribute \src "libresoc.v:115425.9-115425.17" + attribute \src "libresoc.v:116918.9-116918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179835,18 +182075,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:115467.3-115509.6" - process $proc$libresoc.v:115467$4386 + attribute \src "libresoc.v:116960.3-117002.6" + process $proc$libresoc.v:116960$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115468.5-115468.29" + attribute \src "libresoc.v:116961.5-116961.29" switch \initial - attribute \src "libresoc.v:115468.9-115468.17" + attribute \src "libresoc.v:116961.9-116961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179902,18 +182142,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:115510.3-115552.6" - process $proc$libresoc.v:115510$4387 + attribute \src "libresoc.v:117003.3-117045.6" + process $proc$libresoc.v:117003$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115511.5-115511.29" + attribute \src "libresoc.v:117004.5-117004.29" switch \initial - attribute \src "libresoc.v:115511.9-115511.17" + attribute \src "libresoc.v:117004.9-117004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179969,18 +182209,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:115553.3-115595.6" - process $proc$libresoc.v:115553$4388 + attribute \src "libresoc.v:117046.3-117088.6" + process $proc$libresoc.v:117046$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:115554.5-115554.29" + attribute \src "libresoc.v:117047.5-117047.29" switch \initial - attribute \src "libresoc.v:115554.9-115554.17" + attribute \src "libresoc.v:117047.9-117047.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -180036,18 +182276,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:115596.3-115638.6" - process $proc$libresoc.v:115596$4389 + attribute \src "libresoc.v:117089.3-117131.6" + process $proc$libresoc.v:117089$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:115597.5-115597.29" + attribute \src "libresoc.v:117090.5-117090.29" switch \initial - attribute \src "libresoc.v:115597.9-115597.17" + attribute \src "libresoc.v:117090.9-117090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -180105,157 +182345,161 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:115644.1-117744.10" +attribute \src "libresoc.v:117137.1-119302.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:117413.3-117467.6" + attribute \src "libresoc.v:118971.3-119025.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117468.3-117522.6" + attribute \src "libresoc.v:119026.3-119080.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:118311.3-118365.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116973.3-117027.6" + attribute \src "libresoc.v:118531.3-118585.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:117541.3-117595.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:117596.3-117650.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:118256.3-118310.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:118476.3-118530.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:117193.3-117247.6" + attribute \src "libresoc.v:118696.3-118750.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:117486.3-117540.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117523.3-117577.6" + attribute \src "libresoc.v:119081.3-119135.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117578.3-117632.6" + attribute \src "libresoc.v:119136.3-119190.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117633.3-117687.6" + attribute \src "libresoc.v:119191.3-119245.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:118091.3-118145.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:118366.3-118420.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:118421.3-118475.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:117138.3-117192.6" + attribute \src "libresoc.v:118751.3-118805.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:118036.3-118090.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:117303.3-117357.6" + attribute \src "libresoc.v:118861.3-118915.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117688.3-117742.6" + attribute \src "libresoc.v:119246.3-119300.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:118201.3-118255.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:117083.3-117137.6" + attribute \src "libresoc.v:118641.3-118695.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117358.3-117412.6" + attribute \src "libresoc.v:118916.3-118970.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117248.3-117302.6" + attribute \src "libresoc.v:118806.3-118860.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117028.3-117082.6" + attribute \src "libresoc.v:118586.3-118640.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:117926.3-117980.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:117981.3-118035.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:117651.3-117705.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:117706.3-117760.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:117761.3-117815.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:118146.3-118200.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:115645.7-115645.20" + attribute \src "libresoc.v:117138.7-117138.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117413.3-117467.6" + attribute \src "libresoc.v:118971.3-119025.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117468.3-117522.6" + attribute \src "libresoc.v:119026.3-119080.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:118311.3-118365.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116973.3-117027.6" + attribute \src "libresoc.v:118531.3-118585.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:117541.3-117595.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:117596.3-117650.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:118256.3-118310.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:118476.3-118530.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:117193.3-117247.6" + attribute \src "libresoc.v:118696.3-118750.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:117486.3-117540.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117523.3-117577.6" + attribute \src "libresoc.v:119081.3-119135.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117578.3-117632.6" + attribute \src "libresoc.v:119136.3-119190.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117633.3-117687.6" + attribute \src "libresoc.v:119191.3-119245.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:118091.3-118145.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:118366.3-118420.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:118421.3-118475.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:117138.3-117192.6" + attribute \src "libresoc.v:118751.3-118805.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:118036.3-118090.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:117303.3-117357.6" + attribute \src "libresoc.v:118861.3-118915.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117688.3-117742.6" + attribute \src "libresoc.v:119246.3-119300.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:118201.3-118255.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:117083.3-117137.6" + attribute \src "libresoc.v:118641.3-118695.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117358.3-117412.6" + attribute \src "libresoc.v:118916.3-118970.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117248.3-117302.6" + attribute \src "libresoc.v:118806.3-118860.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117028.3-117082.6" + attribute \src "libresoc.v:118586.3-118640.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:117926.3-117980.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:117981.3-118035.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:117651.3-117705.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:117706.3-117760.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:117761.3-117815.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:118146.3-118200.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub9_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub9_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub9_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -180265,7 +182509,7 @@ module \dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -180274,16 +182518,16 @@ module \dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub9_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -180315,7 +182559,7 @@ module \dec31_dec_sub9 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -180332,7 +182576,7 @@ module \dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -180340,7 +182584,7 @@ module \dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -180357,13 +182601,13 @@ module \dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -180440,46 +182684,46 @@ module \dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub9_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub9_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub9_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub9_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180487,8 +182731,8 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub9_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub9_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180496,8 +182740,8 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub9_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub9_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180505,7 +182749,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub9_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180514,7 +182758,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub9_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180523,7 +182767,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub9_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180532,41 +182776,50 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub9_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub9_upd - attribute \src "libresoc.v:115645.7-115645.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub9_upd + attribute \src "libresoc.v:117138.7-117138.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:115645.7-115645.20" - process $proc$libresoc.v:115645$4423 + attribute \src "libresoc.v:117138.7-117138.20" + process $proc$libresoc.v:117138$4462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115983.3-116037.6" - process $proc$libresoc.v:115983$4391 + attribute \src "libresoc.v:117486.3-117540.6" + process $proc$libresoc.v:117486$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:115984.5-115984.29" + attribute \src "libresoc.v:117487.5-117487.29" switch \initial - attribute \src "libresoc.v:115984.9-115984.17" + attribute \src "libresoc.v:117487.9-117487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180638,18 +182891,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:116038.3-116092.6" - process $proc$libresoc.v:116038$4392 + attribute \src "libresoc.v:117541.3-117595.6" + process $proc$libresoc.v:117541$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116039.5-116039.29" + attribute \src "libresoc.v:117542.5-117542.29" switch \initial - attribute \src "libresoc.v:116039.9-116039.17" + attribute \src "libresoc.v:117542.9-117542.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180721,18 +182974,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:116093.3-116147.6" - process $proc$libresoc.v:116093$4393 + attribute \src "libresoc.v:117596.3-117650.6" + process $proc$libresoc.v:117596$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116094.5-116094.29" + attribute \src "libresoc.v:117597.5-117597.29" switch \initial - attribute \src "libresoc.v:116094.9-116094.17" + attribute \src "libresoc.v:117597.9-117597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180804,18 +183057,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:116148.3-116202.6" - process $proc$libresoc.v:116148$4394 + attribute \src "libresoc.v:117651.3-117705.6" + process $proc$libresoc.v:117651$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116149.5-116149.29" + attribute \src "libresoc.v:117652.5-117652.29" switch \initial - attribute \src "libresoc.v:116149.9-116149.17" + attribute \src "libresoc.v:117652.9-117652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180887,18 +183140,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:116203.3-116257.6" - process $proc$libresoc.v:116203$4395 + attribute \src "libresoc.v:117706.3-117760.6" + process $proc$libresoc.v:117706$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116204.5-116204.29" + attribute \src "libresoc.v:117707.5-117707.29" switch \initial - attribute \src "libresoc.v:116204.9-116204.17" + attribute \src "libresoc.v:117707.9-117707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180970,18 +183223,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:116258.3-116312.6" - process $proc$libresoc.v:116258$4396 + attribute \src "libresoc.v:117761.3-117815.6" + process $proc$libresoc.v:117761$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116259.5-116259.29" + attribute \src "libresoc.v:117762.5-117762.29" switch \initial - attribute \src "libresoc.v:116259.9-116259.17" + attribute \src "libresoc.v:117762.9-117762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181053,18 +183306,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:116313.3-116367.6" - process $proc$libresoc.v:116313$4397 + attribute \src "libresoc.v:117816.3-117870.6" + process $proc$libresoc.v:117816$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116314.5-116314.29" + attribute \src "libresoc.v:117817.5-117817.29" switch \initial - attribute \src "libresoc.v:116314.9-116314.17" + attribute \src "libresoc.v:117817.9-117817.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181136,18 +183389,101 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:116368.3-116422.6" - process $proc$libresoc.v:116368$4398 + attribute \src "libresoc.v:117871.3-117925.6" + process $proc$libresoc.v:117871$4436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117872.5-117872.29" + switch \initial + attribute \src "libresoc.v:117872.9-117872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] + end + attribute \src "libresoc.v:117926.3-117980.6" + process $proc$libresoc.v:117926$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116369.5-116369.29" + attribute \src "libresoc.v:117927.5-117927.29" switch \initial - attribute \src "libresoc.v:116369.9-116369.17" + attribute \src "libresoc.v:117927.9-117927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181219,18 +183555,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:116423.3-116477.6" - process $proc$libresoc.v:116423$4399 + attribute \src "libresoc.v:117981.3-118035.6" + process $proc$libresoc.v:117981$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116424.5-116424.29" + attribute \src "libresoc.v:117982.5-117982.29" switch \initial - attribute \src "libresoc.v:116424.9-116424.17" + attribute \src "libresoc.v:117982.9-117982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181302,18 +183638,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:116478.3-116532.6" - process $proc$libresoc.v:116478$4400 + attribute \src "libresoc.v:118036.3-118090.6" + process $proc$libresoc.v:118036$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:116479.5-116479.29" + attribute \src "libresoc.v:118037.5-118037.29" switch \initial - attribute \src "libresoc.v:116479.9-116479.17" + attribute \src "libresoc.v:118037.9-118037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181385,184 +183721,184 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:116533.3-116587.6" - process $proc$libresoc.v:116533$4401 + attribute \src "libresoc.v:118091.3-118145.6" + process $proc$libresoc.v:118091$4440 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:116534.5-116534.29" + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:118092.5-118092.29" switch \initial - attribute \src "libresoc.v:116534.9-116534.17" + attribute \src "libresoc.v:118092.9-118092.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:116588.3-116642.6" - process $proc$libresoc.v:116588$4402 + attribute \src "libresoc.v:118146.3-118200.6" + process $proc$libresoc.v:118146$4441 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116589.5-116589.29" + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:118147.5-118147.29" switch \initial - attribute \src "libresoc.v:116589.9-116589.17" + attribute \src "libresoc.v:118147.9-118147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 end sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:116643.3-116697.6" - process $proc$libresoc.v:116643$4403 + attribute \src "libresoc.v:118201.3-118255.6" + process $proc$libresoc.v:118201$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:116644.5-116644.29" + attribute \src "libresoc.v:118202.5-118202.29" switch \initial - attribute \src "libresoc.v:116644.9-116644.17" + attribute \src "libresoc.v:118202.9-118202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181634,18 +183970,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:116698.3-116752.6" - process $proc$libresoc.v:116698$4404 + attribute \src "libresoc.v:118256.3-118310.6" + process $proc$libresoc.v:118256$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116699.5-116699.29" + attribute \src "libresoc.v:118257.5-118257.29" switch \initial - attribute \src "libresoc.v:116699.9-116699.17" + attribute \src "libresoc.v:118257.9-118257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181717,18 +184053,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:116753.3-116807.6" - process $proc$libresoc.v:116753$4405 + attribute \src "libresoc.v:118311.3-118365.6" + process $proc$libresoc.v:118311$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116754.5-116754.29" + attribute \src "libresoc.v:118312.5-118312.29" switch \initial - attribute \src "libresoc.v:116754.9-116754.17" + attribute \src "libresoc.v:118312.9-118312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181800,18 +184136,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:116808.3-116862.6" - process $proc$libresoc.v:116808$4406 + attribute \src "libresoc.v:118366.3-118420.6" + process $proc$libresoc.v:118366$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116809.5-116809.29" + attribute \src "libresoc.v:118367.5-118367.29" switch \initial - attribute \src "libresoc.v:116809.9-116809.17" + attribute \src "libresoc.v:118367.9-118367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181883,18 +184219,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:116863.3-116917.6" - process $proc$libresoc.v:116863$4407 + attribute \src "libresoc.v:118421.3-118475.6" + process $proc$libresoc.v:118421$4446 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:116864.5-116864.29" + attribute \src "libresoc.v:118422.5-118422.29" switch \initial - attribute \src "libresoc.v:116864.9-116864.17" + attribute \src "libresoc.v:118422.9-118422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181966,18 +184302,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:116918.3-116972.6" - process $proc$libresoc.v:116918$4408 + attribute \src "libresoc.v:118476.3-118530.6" + process $proc$libresoc.v:118476$4447 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:116919.5-116919.29" + attribute \src "libresoc.v:118477.5-118477.29" switch \initial - attribute \src "libresoc.v:116919.9-116919.17" + attribute \src "libresoc.v:118477.9-118477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182049,18 +184385,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:116973.3-117027.6" - process $proc$libresoc.v:116973$4409 + attribute \src "libresoc.v:118531.3-118585.6" + process $proc$libresoc.v:118531$4448 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116974.5-116974.29" + attribute \src "libresoc.v:118532.5-118532.29" switch \initial - attribute \src "libresoc.v:116974.9-116974.17" + attribute \src "libresoc.v:118532.9-118532.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182132,18 +184468,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:117028.3-117082.6" - process $proc$libresoc.v:117028$4410 + attribute \src "libresoc.v:118586.3-118640.6" + process $proc$libresoc.v:118586$4449 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117029.5-117029.29" + attribute \src "libresoc.v:118587.5-118587.29" switch \initial - attribute \src "libresoc.v:117029.9-117029.17" + attribute \src "libresoc.v:118587.9-118587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182215,18 +184551,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:117083.3-117137.6" - process $proc$libresoc.v:117083$4411 + attribute \src "libresoc.v:118641.3-118695.6" + process $proc$libresoc.v:118641$4450 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117084.5-117084.29" + attribute \src "libresoc.v:118642.5-118642.29" switch \initial - attribute \src "libresoc.v:117084.9-117084.17" + attribute \src "libresoc.v:118642.9-118642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182298,184 +184634,184 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:117138.3-117192.6" - process $proc$libresoc.v:117138$4412 + attribute \src "libresoc.v:118696.3-118750.6" + process $proc$libresoc.v:118696$4451 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:117139.5-117139.29" + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:118697.5-118697.29" switch \initial - attribute \src "libresoc.v:117139.9-117139.17" + attribute \src "libresoc.v:118697.9-118697.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'00000 end sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:117193.3-117247.6" - process $proc$libresoc.v:117193$4413 + attribute \src "libresoc.v:118751.3-118805.6" + process $proc$libresoc.v:118751$4452 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117194.5-117194.29" + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:118752.5-118752.29" switch \initial - attribute \src "libresoc.v:117194.9-117194.17" + attribute \src "libresoc.v:118752.9-118752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:117248.3-117302.6" - process $proc$libresoc.v:117248$4414 + attribute \src "libresoc.v:118806.3-118860.6" + process $proc$libresoc.v:118806$4453 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117249.5-117249.29" + attribute \src "libresoc.v:118807.5-118807.29" switch \initial - attribute \src "libresoc.v:117249.9-117249.17" + attribute \src "libresoc.v:118807.9-118807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182547,18 +184883,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:117303.3-117357.6" - process $proc$libresoc.v:117303$4415 + attribute \src "libresoc.v:118861.3-118915.6" + process $proc$libresoc.v:118861$4454 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117304.5-117304.29" + attribute \src "libresoc.v:118862.5-118862.29" switch \initial - attribute \src "libresoc.v:117304.9-117304.17" + attribute \src "libresoc.v:118862.9-118862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182630,18 +184966,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:117358.3-117412.6" - process $proc$libresoc.v:117358$4416 + attribute \src "libresoc.v:118916.3-118970.6" + process $proc$libresoc.v:118916$4455 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117359.5-117359.29" + attribute \src "libresoc.v:118917.5-118917.29" switch \initial - attribute \src "libresoc.v:117359.9-117359.17" + attribute \src "libresoc.v:118917.9-118917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182713,18 +185049,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:117413.3-117467.6" - process $proc$libresoc.v:117413$4417 + attribute \src "libresoc.v:118971.3-119025.6" + process $proc$libresoc.v:118971$4456 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117414.5-117414.29" + attribute \src "libresoc.v:118972.5-118972.29" switch \initial - attribute \src "libresoc.v:117414.9-117414.17" + attribute \src "libresoc.v:118972.9-118972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182796,18 +185132,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:117468.3-117522.6" - process $proc$libresoc.v:117468$4418 + attribute \src "libresoc.v:119026.3-119080.6" + process $proc$libresoc.v:119026$4457 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:117469.5-117469.29" + attribute \src "libresoc.v:119027.5-119027.29" switch \initial - attribute \src "libresoc.v:117469.9-117469.17" + attribute \src "libresoc.v:119027.9-119027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182879,18 +185215,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:117523.3-117577.6" - process $proc$libresoc.v:117523$4419 + attribute \src "libresoc.v:119081.3-119135.6" + process $proc$libresoc.v:119081$4458 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117524.5-117524.29" + attribute \src "libresoc.v:119082.5-119082.29" switch \initial - attribute \src "libresoc.v:117524.9-117524.17" + attribute \src "libresoc.v:119082.9-119082.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182962,18 +185298,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:117578.3-117632.6" - process $proc$libresoc.v:117578$4420 + attribute \src "libresoc.v:119136.3-119190.6" + process $proc$libresoc.v:119136$4459 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117579.5-117579.29" + attribute \src "libresoc.v:119137.5-119137.29" switch \initial - attribute \src "libresoc.v:117579.9-117579.17" + attribute \src "libresoc.v:119137.9-119137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183045,18 +185381,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:117633.3-117687.6" - process $proc$libresoc.v:117633$4421 + attribute \src "libresoc.v:119191.3-119245.6" + process $proc$libresoc.v:119191$4460 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:117634.5-117634.29" + attribute \src "libresoc.v:119192.5-119192.29" switch \initial - attribute \src "libresoc.v:117634.9-117634.17" + attribute \src "libresoc.v:119192.9-119192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183128,18 +185464,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:117688.3-117742.6" - process $proc$libresoc.v:117688$4422 + attribute \src "libresoc.v:119246.3-119300.6" + process $proc$libresoc.v:119246$4461 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:117689.5-117689.29" + attribute \src "libresoc.v:119247.5-119247.29" switch \initial - attribute \src "libresoc.v:117689.9-117689.17" + attribute \src "libresoc.v:119247.9-119247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183213,157 +185549,161 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:117748.1-118600.10" +attribute \src "libresoc.v:119306.1-120184.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:118503.3-118518.6" + attribute \src "libresoc.v:120087.3-120102.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118519.3-118534.6" + attribute \src "libresoc.v:120103.3-120118.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118326.6" + attribute \src "libresoc.v:119895.3-119910.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:118375.3-118390.6" + attribute \src "libresoc.v:119959.3-119974.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:118103.3-118118.6" + attribute \src "libresoc.v:119671.3-119686.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:118119.3-118134.6" + attribute \src "libresoc.v:119687.3-119702.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:118295.3-118310.6" + attribute \src "libresoc.v:119879.3-119894.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:118359.3-118374.6" + attribute \src "libresoc.v:119943.3-119958.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:118439.3-118454.6" + attribute \src "libresoc.v:120007.3-120022.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:118087.3-118102.6" + attribute \src "libresoc.v:119655.3-119670.6" wire width 14 $0\dec58_function_unit[13:0] - attribute \src "libresoc.v:118535.3-118550.6" + attribute \src "libresoc.v:120119.3-120134.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118551.3-118566.6" + attribute \src "libresoc.v:120135.3-120150.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118567.3-118582.6" + attribute \src "libresoc.v:120151.3-120166.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118263.3-118278.6" + attribute \src "libresoc.v:119831.3-119846.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:118327.3-118342.6" + attribute \src "libresoc.v:119911.3-119926.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:118343.3-118358.6" + attribute \src "libresoc.v:119927.3-119942.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:118423.3-118438.6" + attribute \src "libresoc.v:120023.3-120038.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:118231.3-118246.6" + attribute \src "libresoc.v:119815.3-119830.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118471.3-118486.6" + attribute \src "libresoc.v:120055.3-120070.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:118583.3-118598.6" + attribute \src "libresoc.v:120167.3-120182.6" wire width 3 $0\dec58_out_sel[2:0] - attribute \src "libresoc.v:118279.3-118294.6" + attribute \src "libresoc.v:119863.3-119878.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118407.3-118422.6" + attribute \src "libresoc.v:119991.3-120006.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:118487.3-118502.6" + attribute \src "libresoc.v:120071.3-120086.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118455.3-118470.6" + attribute \src "libresoc.v:120039.3-120054.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:118391.3-118406.6" + attribute \src "libresoc.v:119975.3-119990.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118199.3-118214.6" + attribute \src "libresoc.v:119783.3-119798.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118215.3-118230.6" + attribute \src "libresoc.v:119799.3-119814.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118135.3-118150.6" + attribute \src "libresoc.v:119703.3-119718.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118151.3-118166.6" + attribute \src "libresoc.v:119719.3-119734.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118167.3-118182.6" + attribute \src "libresoc.v:119735.3-119750.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118183.3-118198.6" + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $0\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:118247.3-118262.6" + attribute \src "libresoc.v:119847.3-119862.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:117749.7-117749.20" + attribute \src "libresoc.v:119307.7-119307.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118503.3-118518.6" + attribute \src "libresoc.v:120087.3-120102.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118519.3-118534.6" + attribute \src "libresoc.v:120103.3-120118.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118326.6" + attribute \src "libresoc.v:119895.3-119910.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:118375.3-118390.6" + attribute \src "libresoc.v:119959.3-119974.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:118103.3-118118.6" + attribute \src "libresoc.v:119671.3-119686.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:118119.3-118134.6" + attribute \src "libresoc.v:119687.3-119702.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:118295.3-118310.6" + attribute \src "libresoc.v:119879.3-119894.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:118359.3-118374.6" + attribute \src "libresoc.v:119943.3-119958.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:118439.3-118454.6" + attribute \src "libresoc.v:120007.3-120022.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:118087.3-118102.6" + attribute \src "libresoc.v:119655.3-119670.6" wire width 14 $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:118535.3-118550.6" + attribute \src "libresoc.v:120119.3-120134.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118551.3-118566.6" + attribute \src "libresoc.v:120135.3-120150.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118567.3-118582.6" + attribute \src "libresoc.v:120151.3-120166.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118263.3-118278.6" + attribute \src "libresoc.v:119831.3-119846.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:118327.3-118342.6" + attribute \src "libresoc.v:119911.3-119926.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:118343.3-118358.6" + attribute \src "libresoc.v:119927.3-119942.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:118423.3-118438.6" + attribute \src "libresoc.v:120023.3-120038.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:118231.3-118246.6" + attribute \src "libresoc.v:119815.3-119830.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118471.3-118486.6" + attribute \src "libresoc.v:120055.3-120070.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:118583.3-118598.6" + attribute \src "libresoc.v:120167.3-120182.6" wire width 3 $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:118279.3-118294.6" + attribute \src "libresoc.v:119863.3-119878.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118407.3-118422.6" + attribute \src "libresoc.v:119991.3-120006.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:118487.3-118502.6" + attribute \src "libresoc.v:120071.3-120086.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118455.3-118470.6" + attribute \src "libresoc.v:120039.3-120054.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:118391.3-118406.6" + attribute \src "libresoc.v:119975.3-119990.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118199.3-118214.6" + attribute \src "libresoc.v:119783.3-119798.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118215.3-118230.6" + attribute \src "libresoc.v:119799.3-119814.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118135.3-118150.6" + attribute \src "libresoc.v:119703.3-119718.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118151.3-118166.6" + attribute \src "libresoc.v:119719.3-119734.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118167.3-118182.6" + attribute \src "libresoc.v:119735.3-119750.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118183.3-118198.6" + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:118247.3-118262.6" + attribute \src "libresoc.v:119847.3-119862.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec58_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec58_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec58_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -183373,7 +185713,7 @@ module \dec58 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -183382,16 +185722,16 @@ module \dec58 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec58_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -183423,7 +185763,7 @@ module \dec58 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -183440,7 +185780,7 @@ module \dec58 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -183448,7 +185788,7 @@ module \dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -183465,13 +185805,13 @@ module \dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -183548,46 +185888,46 @@ module \dec58 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec58_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec58_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec58_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec58_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183595,8 +185935,8 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec58_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec58_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183604,8 +185944,8 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec58_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec58_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183613,7 +185953,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec58_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183622,7 +185962,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec58_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183631,7 +185971,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec58_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183640,41 +185980,50 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec58_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec58_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec58_upd - attribute \src "libresoc.v:117749.7-117749.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec58_upd + attribute \src "libresoc.v:119307.7-119307.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:117749.7-117749.20" - process $proc$libresoc.v:117749$4456 + attribute \src "libresoc.v:119307.7-119307.20" + process $proc$libresoc.v:119307$4496 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118087.3-118102.6" - process $proc$libresoc.v:118087$4424 + attribute \src "libresoc.v:119655.3-119670.6" + process $proc$libresoc.v:119655$4463 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:118088.5-118088.29" + attribute \src "libresoc.v:119656.5-119656.29" switch \initial - attribute \src "libresoc.v:118088.9-118088.17" + attribute \src "libresoc.v:119656.9-119656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183694,18 +186043,18 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:118103.3-118118.6" - process $proc$libresoc.v:118103$4425 + attribute \src "libresoc.v:119671.3-119686.6" + process $proc$libresoc.v:119671$4464 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:118104.5-118104.29" + attribute \src "libresoc.v:119672.5-119672.29" switch \initial - attribute \src "libresoc.v:118104.9-118104.17" + attribute \src "libresoc.v:119672.9-119672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183725,18 +186074,18 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:118119.3-118134.6" - process $proc$libresoc.v:118119$4426 + attribute \src "libresoc.v:119687.3-119702.6" + process $proc$libresoc.v:119687$4465 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:118120.5-118120.29" + attribute \src "libresoc.v:119688.5-119688.29" switch \initial - attribute \src "libresoc.v:118120.9-118120.17" + attribute \src "libresoc.v:119688.9-119688.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183756,18 +186105,18 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:118135.3-118150.6" - process $proc$libresoc.v:118135$4427 + attribute \src "libresoc.v:119703.3-119718.6" + process $proc$libresoc.v:119703$4466 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118136.5-118136.29" + attribute \src "libresoc.v:119704.5-119704.29" switch \initial - attribute \src "libresoc.v:118136.9-118136.17" + attribute \src "libresoc.v:119704.9-119704.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183787,18 +186136,18 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:118151.3-118166.6" - process $proc$libresoc.v:118151$4428 + attribute \src "libresoc.v:119719.3-119734.6" + process $proc$libresoc.v:119719$4467 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118152.5-118152.29" + attribute \src "libresoc.v:119720.5-119720.29" switch \initial - attribute \src "libresoc.v:118152.9-118152.17" + attribute \src "libresoc.v:119720.9-119720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183818,18 +186167,18 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:118167.3-118182.6" - process $proc$libresoc.v:118167$4429 + attribute \src "libresoc.v:119735.3-119750.6" + process $proc$libresoc.v:119735$4468 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118168.5-118168.29" + attribute \src "libresoc.v:119736.5-119736.29" switch \initial - attribute \src "libresoc.v:118168.9-118168.17" + attribute \src "libresoc.v:119736.9-119736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183849,18 +186198,18 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:118183.3-118198.6" - process $proc$libresoc.v:118183$4430 + attribute \src "libresoc.v:119751.3-119766.6" + process $proc$libresoc.v:119751$4469 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:118184.5-118184.29" + attribute \src "libresoc.v:119752.5-119752.29" switch \initial - attribute \src "libresoc.v:118184.9-118184.17" + attribute \src "libresoc.v:119752.9-119752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183880,18 +186229,49 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:118199.3-118214.6" - process $proc$libresoc.v:118199$4431 + attribute \src "libresoc.v:119767.3-119782.6" + process $proc$libresoc.v:119767$4470 + assign { } { } + assign { } { } + assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119768.5-119768.29" + switch \initial + attribute \src "libresoc.v:119768.9-119768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + case + assign $1\dec58_sv_out2[2:0] 3'000 + end + sync always + update \dec58_sv_out2 $0\dec58_sv_out2[2:0] + end + attribute \src "libresoc.v:119783.3-119798.6" + process $proc$libresoc.v:119783$4471 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118200.5-118200.29" + attribute \src "libresoc.v:119784.5-119784.29" switch \initial - attribute \src "libresoc.v:118200.9-118200.17" + attribute \src "libresoc.v:119784.9-119784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183911,18 +186291,18 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:118215.3-118230.6" - process $proc$libresoc.v:118215$4432 + attribute \src "libresoc.v:119799.3-119814.6" + process $proc$libresoc.v:119799$4472 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118216.5-118216.29" + attribute \src "libresoc.v:119800.5-119800.29" switch \initial - attribute \src "libresoc.v:118216.9-118216.17" + attribute \src "libresoc.v:119800.9-119800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183942,18 +186322,18 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:118231.3-118246.6" - process $proc$libresoc.v:118231$4433 + attribute \src "libresoc.v:119815.3-119830.6" + process $proc$libresoc.v:119815$4473 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118232.5-118232.29" + attribute \src "libresoc.v:119816.5-119816.29" switch \initial - attribute \src "libresoc.v:118232.9-118232.17" + attribute \src "libresoc.v:119816.9-119816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183973,80 +186353,80 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:118247.3-118262.6" - process $proc$libresoc.v:118247$4434 + attribute \src "libresoc.v:119831.3-119846.6" + process $proc$libresoc.v:119831$4474 assign { } { } assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:118248.5-118248.29" + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:119832.5-119832.29" switch \initial - attribute \src "libresoc.v:118248.9-118248.17" + attribute \src "libresoc.v:119832.9-119832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_upd[1:0] 2'01 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0100101 case - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0000000 end sync always - update \dec58_upd $0\dec58_upd[1:0] + update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:118263.3-118278.6" - process $proc$libresoc.v:118263$4435 + attribute \src "libresoc.v:119847.3-119862.6" + process $proc$libresoc.v:119847$4475 assign { } { } assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:118264.5-118264.29" + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:119848.5-119848.29" switch \initial - attribute \src "libresoc.v:118264.9-118264.17" + attribute \src "libresoc.v:119848.9-119848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'00 case - assign $1\dec58_internal_op[6:0] 7'0000000 + assign $1\dec58_upd[1:0] 2'00 end sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] + update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:118279.3-118294.6" - process $proc$libresoc.v:118279$4436 + attribute \src "libresoc.v:119863.3-119878.6" + process $proc$libresoc.v:119863$4476 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118280.5-118280.29" + attribute \src "libresoc.v:119864.5-119864.29" switch \initial - attribute \src "libresoc.v:118280.9-118280.17" + attribute \src "libresoc.v:119864.9-119864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184066,18 +186446,18 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:118295.3-118310.6" - process $proc$libresoc.v:118295$4437 + attribute \src "libresoc.v:119879.3-119894.6" + process $proc$libresoc.v:119879$4477 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:118296.5-118296.29" + attribute \src "libresoc.v:119880.5-119880.29" switch \initial - attribute \src "libresoc.v:118296.9-118296.17" + attribute \src "libresoc.v:119880.9-119880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184097,18 +186477,18 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:118311.3-118326.6" - process $proc$libresoc.v:118311$4438 + attribute \src "libresoc.v:119895.3-119910.6" + process $proc$libresoc.v:119895$4478 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:118312.5-118312.29" + attribute \src "libresoc.v:119896.5-119896.29" switch \initial - attribute \src "libresoc.v:118312.9-118312.17" + attribute \src "libresoc.v:119896.9-119896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184128,18 +186508,18 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:118327.3-118342.6" - process $proc$libresoc.v:118327$4439 + attribute \src "libresoc.v:119911.3-119926.6" + process $proc$libresoc.v:119911$4479 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:118328.5-118328.29" + attribute \src "libresoc.v:119912.5-119912.29" switch \initial - attribute \src "libresoc.v:118328.9-118328.17" + attribute \src "libresoc.v:119912.9-119912.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184159,18 +186539,18 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:118343.3-118358.6" - process $proc$libresoc.v:118343$4440 + attribute \src "libresoc.v:119927.3-119942.6" + process $proc$libresoc.v:119927$4480 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:118344.5-118344.29" + attribute \src "libresoc.v:119928.5-119928.29" switch \initial - attribute \src "libresoc.v:118344.9-118344.17" + attribute \src "libresoc.v:119928.9-119928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184190,18 +186570,18 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:118359.3-118374.6" - process $proc$libresoc.v:118359$4441 + attribute \src "libresoc.v:119943.3-119958.6" + process $proc$libresoc.v:119943$4481 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:118360.5-118360.29" + attribute \src "libresoc.v:119944.5-119944.29" switch \initial - attribute \src "libresoc.v:118360.9-118360.17" + attribute \src "libresoc.v:119944.9-119944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184221,18 +186601,18 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:118375.3-118390.6" - process $proc$libresoc.v:118375$4442 + attribute \src "libresoc.v:119959.3-119974.6" + process $proc$libresoc.v:119959$4482 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:118376.5-118376.29" + attribute \src "libresoc.v:119960.5-119960.29" switch \initial - attribute \src "libresoc.v:118376.9-118376.17" + attribute \src "libresoc.v:119960.9-119960.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184252,18 +186632,18 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:118391.3-118406.6" - process $proc$libresoc.v:118391$4443 + attribute \src "libresoc.v:119975.3-119990.6" + process $proc$libresoc.v:119975$4483 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118392.5-118392.29" + attribute \src "libresoc.v:119976.5-119976.29" switch \initial - attribute \src "libresoc.v:118392.9-118392.17" + attribute \src "libresoc.v:119976.9-119976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184283,18 +186663,18 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:118407.3-118422.6" - process $proc$libresoc.v:118407$4444 + attribute \src "libresoc.v:119991.3-120006.6" + process $proc$libresoc.v:119991$4484 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:118408.5-118408.29" + attribute \src "libresoc.v:119992.5-119992.29" switch \initial - attribute \src "libresoc.v:118408.9-118408.17" + attribute \src "libresoc.v:119992.9-119992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184314,80 +186694,80 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:118423.3-118438.6" - process $proc$libresoc.v:118423$4445 + attribute \src "libresoc.v:120007.3-120022.6" + process $proc$libresoc.v:120007$4485 assign { } { } assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:118424.5-118424.29" + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:120008.5-120008.29" switch \initial - attribute \src "libresoc.v:118424.9-118424.17" + attribute \src "libresoc.v:120008.9-120008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 case - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00000 end sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] + update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:118439.3-118454.6" - process $proc$libresoc.v:118439$4446 + attribute \src "libresoc.v:120023.3-120038.6" + process $proc$libresoc.v:120023$4486 assign { } { } assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:118440.5-118440.29" + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:120024.5-120024.29" switch \initial - attribute \src "libresoc.v:118440.9-118440.17" + attribute \src "libresoc.v:120024.9-120024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 case - assign $1\dec58_form[4:0] 5'00000 + assign $1\dec58_is_32b[0:0] 1'0 end sync always - update \dec58_form $0\dec58_form[4:0] + update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:118455.3-118470.6" - process $proc$libresoc.v:118455$4447 + attribute \src "libresoc.v:120039.3-120054.6" + process $proc$libresoc.v:120039$4487 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:118456.5-118456.29" + attribute \src "libresoc.v:120040.5-120040.29" switch \initial - attribute \src "libresoc.v:118456.9-118456.17" + attribute \src "libresoc.v:120040.9-120040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184407,18 +186787,18 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:118471.3-118486.6" - process $proc$libresoc.v:118471$4448 + attribute \src "libresoc.v:120055.3-120070.6" + process $proc$libresoc.v:120055$4488 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:118472.5-118472.29" + attribute \src "libresoc.v:120056.5-120056.29" switch \initial - attribute \src "libresoc.v:118472.9-118472.17" + attribute \src "libresoc.v:120056.9-120056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184438,18 +186818,18 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:118487.3-118502.6" - process $proc$libresoc.v:118487$4449 + attribute \src "libresoc.v:120071.3-120086.6" + process $proc$libresoc.v:120071$4489 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118488.5-118488.29" + attribute \src "libresoc.v:120072.5-120072.29" switch \initial - attribute \src "libresoc.v:118488.9-118488.17" + attribute \src "libresoc.v:120072.9-120072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184469,18 +186849,18 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:118503.3-118518.6" - process $proc$libresoc.v:118503$4450 + attribute \src "libresoc.v:120087.3-120102.6" + process $proc$libresoc.v:120087$4490 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118504.5-118504.29" + attribute \src "libresoc.v:120088.5-120088.29" switch \initial - attribute \src "libresoc.v:118504.9-118504.17" + attribute \src "libresoc.v:120088.9-120088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184500,18 +186880,18 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:118519.3-118534.6" - process $proc$libresoc.v:118519$4451 + attribute \src "libresoc.v:120103.3-120118.6" + process $proc$libresoc.v:120103$4491 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118520.5-118520.29" + attribute \src "libresoc.v:120104.5-120104.29" switch \initial - attribute \src "libresoc.v:118520.9-118520.17" + attribute \src "libresoc.v:120104.9-120104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184531,18 +186911,18 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:118535.3-118550.6" - process $proc$libresoc.v:118535$4452 + attribute \src "libresoc.v:120119.3-120134.6" + process $proc$libresoc.v:120119$4492 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118536.5-118536.29" + attribute \src "libresoc.v:120120.5-120120.29" switch \initial - attribute \src "libresoc.v:118536.9-118536.17" + attribute \src "libresoc.v:120120.9-120120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184562,18 +186942,18 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:118551.3-118566.6" - process $proc$libresoc.v:118551$4453 + attribute \src "libresoc.v:120135.3-120150.6" + process $proc$libresoc.v:120135$4493 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118552.5-118552.29" + attribute \src "libresoc.v:120136.5-120136.29" switch \initial - attribute \src "libresoc.v:118552.9-118552.17" + attribute \src "libresoc.v:120136.9-120136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184593,18 +186973,18 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:118567.3-118582.6" - process $proc$libresoc.v:118567$4454 + attribute \src "libresoc.v:120151.3-120166.6" + process $proc$libresoc.v:120151$4494 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118568.5-118568.29" + attribute \src "libresoc.v:120152.5-120152.29" switch \initial - attribute \src "libresoc.v:118568.9-118568.17" + attribute \src "libresoc.v:120152.9-120152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184624,18 +187004,18 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:118583.3-118598.6" - process $proc$libresoc.v:118583$4455 + attribute \src "libresoc.v:120167.3-120182.6" + process $proc$libresoc.v:120167$4495 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:118584.5-118584.29" + attribute \src "libresoc.v:120168.5-120168.29" switch \initial - attribute \src "libresoc.v:118584.9-118584.17" + attribute \src "libresoc.v:120168.9-120168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184657,157 +187037,161 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:118604.1-119360.10" +attribute \src "libresoc.v:120188.1-120967.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:119281.3-119293.6" + attribute \src "libresoc.v:120888.3-120900.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119294.3-119306.6" + attribute \src "libresoc.v:120901.3-120913.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119125.3-119137.6" + attribute \src "libresoc.v:120732.3-120744.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:119177.3-119189.6" + attribute \src "libresoc.v:120784.3-120796.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:118956.3-118968.6" + attribute \src "libresoc.v:120550.3-120562.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:118969.3-118981.6" + attribute \src "libresoc.v:120563.3-120575.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:119112.3-119124.6" + attribute \src "libresoc.v:120719.3-120731.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:119164.3-119176.6" + attribute \src "libresoc.v:120771.3-120783.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:119229.3-119241.6" + attribute \src "libresoc.v:120823.3-120835.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:118943.3-118955.6" + attribute \src "libresoc.v:120537.3-120549.6" wire width 14 $0\dec62_function_unit[13:0] - attribute \src "libresoc.v:119307.3-119319.6" + attribute \src "libresoc.v:120914.3-120926.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119320.3-119332.6" + attribute \src "libresoc.v:120927.3-120939.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119333.3-119345.6" + attribute \src "libresoc.v:120940.3-120952.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119086.3-119098.6" + attribute \src "libresoc.v:120680.3-120692.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:119138.3-119150.6" + attribute \src "libresoc.v:120745.3-120757.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:119151.3-119163.6" + attribute \src "libresoc.v:120758.3-120770.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:119216.3-119228.6" + attribute \src "libresoc.v:120836.3-120848.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:119060.3-119072.6" + attribute \src "libresoc.v:120667.3-120679.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119255.3-119267.6" + attribute \src "libresoc.v:120862.3-120874.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:119346.3-119358.6" + attribute \src "libresoc.v:120953.3-120965.6" wire width 3 $0\dec62_out_sel[2:0] - attribute \src "libresoc.v:119099.3-119111.6" + attribute \src "libresoc.v:120706.3-120718.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119203.3-119215.6" + attribute \src "libresoc.v:120810.3-120822.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:119268.3-119280.6" + attribute \src "libresoc.v:120875.3-120887.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119242.3-119254.6" + attribute \src "libresoc.v:120849.3-120861.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:119190.3-119202.6" + attribute \src "libresoc.v:120797.3-120809.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119034.3-119046.6" + attribute \src "libresoc.v:120641.3-120653.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119047.3-119059.6" + attribute \src "libresoc.v:120654.3-120666.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118982.3-118994.6" + attribute \src "libresoc.v:120576.3-120588.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118995.3-119007.6" + attribute \src "libresoc.v:120589.3-120601.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:119008.3-119020.6" + attribute \src "libresoc.v:120602.3-120614.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119021.3-119033.6" + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $0\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:119073.3-119085.6" + attribute \src "libresoc.v:120693.3-120705.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:118605.7-118605.20" + attribute \src "libresoc.v:120189.7-120189.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119281.3-119293.6" + attribute \src "libresoc.v:120888.3-120900.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119294.3-119306.6" + attribute \src "libresoc.v:120901.3-120913.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119125.3-119137.6" + attribute \src "libresoc.v:120732.3-120744.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:119177.3-119189.6" + attribute \src "libresoc.v:120784.3-120796.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:118956.3-118968.6" + attribute \src "libresoc.v:120550.3-120562.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118969.3-118981.6" + attribute \src "libresoc.v:120563.3-120575.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:119112.3-119124.6" + attribute \src "libresoc.v:120719.3-120731.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:119164.3-119176.6" + attribute \src "libresoc.v:120771.3-120783.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:119229.3-119241.6" + attribute \src "libresoc.v:120823.3-120835.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:118943.3-118955.6" + attribute \src "libresoc.v:120537.3-120549.6" wire width 14 $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:119307.3-119319.6" + attribute \src "libresoc.v:120914.3-120926.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119320.3-119332.6" + attribute \src "libresoc.v:120927.3-120939.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119333.3-119345.6" + attribute \src "libresoc.v:120940.3-120952.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119086.3-119098.6" + attribute \src "libresoc.v:120680.3-120692.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:119138.3-119150.6" + attribute \src "libresoc.v:120745.3-120757.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:119151.3-119163.6" + attribute \src "libresoc.v:120758.3-120770.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:119216.3-119228.6" + attribute \src "libresoc.v:120836.3-120848.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:119060.3-119072.6" + attribute \src "libresoc.v:120667.3-120679.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119255.3-119267.6" + attribute \src "libresoc.v:120862.3-120874.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:119346.3-119358.6" + attribute \src "libresoc.v:120953.3-120965.6" wire width 3 $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:119099.3-119111.6" + attribute \src "libresoc.v:120706.3-120718.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119203.3-119215.6" + attribute \src "libresoc.v:120810.3-120822.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:119268.3-119280.6" + attribute \src "libresoc.v:120875.3-120887.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119242.3-119254.6" + attribute \src "libresoc.v:120849.3-120861.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:119190.3-119202.6" + attribute \src "libresoc.v:120797.3-120809.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119034.3-119046.6" + attribute \src "libresoc.v:120641.3-120653.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119047.3-119059.6" + attribute \src "libresoc.v:120654.3-120666.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118982.3-118994.6" + attribute \src "libresoc.v:120576.3-120588.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118995.3-119007.6" + attribute \src "libresoc.v:120589.3-120601.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:119008.3-119020.6" + attribute \src "libresoc.v:120602.3-120614.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119021.3-119033.6" + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:119073.3-119085.6" + attribute \src "libresoc.v:120693.3-120705.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec62_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec62_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec62_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -184817,7 +187201,7 @@ module \dec62 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -184826,16 +187210,16 @@ module \dec62 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -184867,7 +187251,7 @@ module \dec62 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -184884,7 +187268,7 @@ module \dec62 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -184892,7 +187276,7 @@ module \dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -184909,13 +187293,13 @@ module \dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184992,46 +187376,46 @@ module \dec62 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec62_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec62_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec62_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec62_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185039,8 +187423,8 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec62_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec62_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185048,8 +187432,8 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec62_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec62_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185057,7 +187441,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec62_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185066,7 +187450,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec62_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185075,7 +187459,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec62_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185084,41 +187468,50 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec62_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec62_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec62_upd - attribute \src "libresoc.v:118605.7-118605.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec62_upd + attribute \src "libresoc.v:120189.7-120189.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:118605.7-118605.20" - process $proc$libresoc.v:118605$4489 + attribute \src "libresoc.v:120189.7-120189.20" + process $proc$libresoc.v:120189$4530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118943.3-118955.6" - process $proc$libresoc.v:118943$4457 + attribute \src "libresoc.v:120537.3-120549.6" + process $proc$libresoc.v:120537$4497 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:118944.5-118944.29" + attribute \src "libresoc.v:120538.5-120538.29" switch \initial - attribute \src "libresoc.v:118944.9-118944.17" + attribute \src "libresoc.v:120538.9-120538.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185134,18 +187527,18 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:118956.3-118968.6" - process $proc$libresoc.v:118956$4458 + attribute \src "libresoc.v:120550.3-120562.6" + process $proc$libresoc.v:120550$4498 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118957.5-118957.29" + attribute \src "libresoc.v:120551.5-120551.29" switch \initial - attribute \src "libresoc.v:118957.9-118957.17" + attribute \src "libresoc.v:120551.9-120551.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185161,18 +187554,18 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:118969.3-118981.6" - process $proc$libresoc.v:118969$4459 + attribute \src "libresoc.v:120563.3-120575.6" + process $proc$libresoc.v:120563$4499 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:118970.5-118970.29" + attribute \src "libresoc.v:120564.5-120564.29" switch \initial - attribute \src "libresoc.v:118970.9-118970.17" + attribute \src "libresoc.v:120564.9-120564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185188,18 +187581,18 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:118982.3-118994.6" - process $proc$libresoc.v:118982$4460 + attribute \src "libresoc.v:120576.3-120588.6" + process $proc$libresoc.v:120576$4500 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118983.5-118983.29" + attribute \src "libresoc.v:120577.5-120577.29" switch \initial - attribute \src "libresoc.v:118983.9-118983.17" + attribute \src "libresoc.v:120577.9-120577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185215,18 +187608,18 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:118995.3-119007.6" - process $proc$libresoc.v:118995$4461 + attribute \src "libresoc.v:120589.3-120601.6" + process $proc$libresoc.v:120589$4501 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:118996.5-118996.29" + attribute \src "libresoc.v:120590.5-120590.29" switch \initial - attribute \src "libresoc.v:118996.9-118996.17" + attribute \src "libresoc.v:120590.9-120590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185242,18 +187635,18 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:119008.3-119020.6" - process $proc$libresoc.v:119008$4462 + attribute \src "libresoc.v:120602.3-120614.6" + process $proc$libresoc.v:120602$4502 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119009.5-119009.29" + attribute \src "libresoc.v:120603.5-120603.29" switch \initial - attribute \src "libresoc.v:119009.9-119009.17" + attribute \src "libresoc.v:120603.9-120603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185269,18 +187662,18 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:119021.3-119033.6" - process $proc$libresoc.v:119021$4463 + attribute \src "libresoc.v:120615.3-120627.6" + process $proc$libresoc.v:120615$4503 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:119022.5-119022.29" + attribute \src "libresoc.v:120616.5-120616.29" switch \initial - attribute \src "libresoc.v:119022.9-119022.17" + attribute \src "libresoc.v:120616.9-120616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185296,18 +187689,45 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:119034.3-119046.6" - process $proc$libresoc.v:119034$4464 + attribute \src "libresoc.v:120628.3-120640.6" + process $proc$libresoc.v:120628$4504 + assign { } { } + assign { } { } + assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120629.5-120629.29" + switch \initial + attribute \src "libresoc.v:120629.9-120629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'001 + case + assign $1\dec62_sv_out2[2:0] 3'000 + end + sync always + update \dec62_sv_out2 $0\dec62_sv_out2[2:0] + end + attribute \src "libresoc.v:120641.3-120653.6" + process $proc$libresoc.v:120641$4505 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119035.5-119035.29" + attribute \src "libresoc.v:120642.5-120642.29" switch \initial - attribute \src "libresoc.v:119035.9-119035.17" + attribute \src "libresoc.v:120642.9-120642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185323,18 +187743,18 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:119047.3-119059.6" - process $proc$libresoc.v:119047$4465 + attribute \src "libresoc.v:120654.3-120666.6" + process $proc$libresoc.v:120654$4506 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:119048.5-119048.29" + attribute \src "libresoc.v:120655.5-120655.29" switch \initial - attribute \src "libresoc.v:119048.9-119048.17" + attribute \src "libresoc.v:120655.9-120655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185350,18 +187770,18 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:119060.3-119072.6" - process $proc$libresoc.v:119060$4466 + attribute \src "libresoc.v:120667.3-120679.6" + process $proc$libresoc.v:120667$4507 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119061.5-119061.29" + attribute \src "libresoc.v:120668.5-120668.29" switch \initial - attribute \src "libresoc.v:119061.9-119061.17" + attribute \src "libresoc.v:120668.9-120668.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185377,72 +187797,72 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:119073.3-119085.6" - process $proc$libresoc.v:119073$4467 + attribute \src "libresoc.v:120680.3-120692.6" + process $proc$libresoc.v:120680$4508 assign { } { } assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:119074.5-119074.29" + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:120681.5-120681.29" switch \initial - attribute \src "libresoc.v:119074.9-119074.17" + attribute \src "libresoc.v:120681.9-120681.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_upd[1:0] 2'00 + assign $1\dec62_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_upd[1:0] 2'01 + assign $1\dec62_internal_op[6:0] 7'0100110 case - assign $1\dec62_upd[1:0] 2'00 + assign $1\dec62_internal_op[6:0] 7'0000000 end sync always - update \dec62_upd $0\dec62_upd[1:0] + update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:119086.3-119098.6" - process $proc$libresoc.v:119086$4468 + attribute \src "libresoc.v:120693.3-120705.6" + process $proc$libresoc.v:120693$4509 assign { } { } assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:119087.5-119087.29" + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:120694.5-120694.29" switch \initial - attribute \src "libresoc.v:119087.9-119087.17" + attribute \src "libresoc.v:120694.9-120694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec62_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec62_upd[1:0] 2'01 case - assign $1\dec62_internal_op[6:0] 7'0000000 + assign $1\dec62_upd[1:0] 2'00 end sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] + update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:119099.3-119111.6" - process $proc$libresoc.v:119099$4469 + attribute \src "libresoc.v:120706.3-120718.6" + process $proc$libresoc.v:120706$4510 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119100.5-119100.29" + attribute \src "libresoc.v:120707.5-120707.29" switch \initial - attribute \src "libresoc.v:119100.9-119100.17" + attribute \src "libresoc.v:120707.9-120707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185458,18 +187878,18 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:119112.3-119124.6" - process $proc$libresoc.v:119112$4470 + attribute \src "libresoc.v:120719.3-120731.6" + process $proc$libresoc.v:120719$4511 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:119113.5-119113.29" + attribute \src "libresoc.v:120720.5-120720.29" switch \initial - attribute \src "libresoc.v:119113.9-119113.17" + attribute \src "libresoc.v:120720.9-120720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185485,18 +187905,18 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:119125.3-119137.6" - process $proc$libresoc.v:119125$4471 + attribute \src "libresoc.v:120732.3-120744.6" + process $proc$libresoc.v:120732$4512 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:119126.5-119126.29" + attribute \src "libresoc.v:120733.5-120733.29" switch \initial - attribute \src "libresoc.v:119126.9-119126.17" + attribute \src "libresoc.v:120733.9-120733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185512,18 +187932,18 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:119138.3-119150.6" - process $proc$libresoc.v:119138$4472 + attribute \src "libresoc.v:120745.3-120757.6" + process $proc$libresoc.v:120745$4513 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:119139.5-119139.29" + attribute \src "libresoc.v:120746.5-120746.29" switch \initial - attribute \src "libresoc.v:119139.9-119139.17" + attribute \src "libresoc.v:120746.9-120746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185539,18 +187959,18 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:119151.3-119163.6" - process $proc$libresoc.v:119151$4473 + attribute \src "libresoc.v:120758.3-120770.6" + process $proc$libresoc.v:120758$4514 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:119152.5-119152.29" + attribute \src "libresoc.v:120759.5-120759.29" switch \initial - attribute \src "libresoc.v:119152.9-119152.17" + attribute \src "libresoc.v:120759.9-120759.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185566,18 +187986,18 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:119164.3-119176.6" - process $proc$libresoc.v:119164$4474 + attribute \src "libresoc.v:120771.3-120783.6" + process $proc$libresoc.v:120771$4515 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:119165.5-119165.29" + attribute \src "libresoc.v:120772.5-120772.29" switch \initial - attribute \src "libresoc.v:119165.9-119165.17" + attribute \src "libresoc.v:120772.9-120772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185593,18 +188013,18 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:119177.3-119189.6" - process $proc$libresoc.v:119177$4475 + attribute \src "libresoc.v:120784.3-120796.6" + process $proc$libresoc.v:120784$4516 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:119178.5-119178.29" + attribute \src "libresoc.v:120785.5-120785.29" switch \initial - attribute \src "libresoc.v:119178.9-119178.17" + attribute \src "libresoc.v:120785.9-120785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185620,18 +188040,18 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:119190.3-119202.6" - process $proc$libresoc.v:119190$4476 + attribute \src "libresoc.v:120797.3-120809.6" + process $proc$libresoc.v:120797$4517 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119191.5-119191.29" + attribute \src "libresoc.v:120798.5-120798.29" switch \initial - attribute \src "libresoc.v:119191.9-119191.17" + attribute \src "libresoc.v:120798.9-120798.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185647,18 +188067,18 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:119203.3-119215.6" - process $proc$libresoc.v:119203$4477 + attribute \src "libresoc.v:120810.3-120822.6" + process $proc$libresoc.v:120810$4518 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:119204.5-119204.29" + attribute \src "libresoc.v:120811.5-120811.29" switch \initial - attribute \src "libresoc.v:119204.9-119204.17" + attribute \src "libresoc.v:120811.9-120811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185674,72 +188094,72 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:119216.3-119228.6" - process $proc$libresoc.v:119216$4478 + attribute \src "libresoc.v:120823.3-120835.6" + process $proc$libresoc.v:120823$4519 assign { } { } assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:119217.5-119217.29" + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:120824.5-120824.29" switch \initial - attribute \src "libresoc.v:119217.9-119217.17" + attribute \src "libresoc.v:120824.9-120824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00101 case - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00000 end sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] + update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:119229.3-119241.6" - process $proc$libresoc.v:119229$4479 + attribute \src "libresoc.v:120836.3-120848.6" + process $proc$libresoc.v:120836$4520 assign { } { } assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:119230.5-119230.29" + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:120837.5-120837.29" switch \initial - attribute \src "libresoc.v:119230.9-119230.17" + attribute \src "libresoc.v:120837.9-120837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec62_is_32b[0:0] 1'0 case - assign $1\dec62_form[4:0] 5'00000 + assign $1\dec62_is_32b[0:0] 1'0 end sync always - update \dec62_form $0\dec62_form[4:0] + update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:119242.3-119254.6" - process $proc$libresoc.v:119242$4480 + attribute \src "libresoc.v:120849.3-120861.6" + process $proc$libresoc.v:120849$4521 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:119243.5-119243.29" + attribute \src "libresoc.v:120850.5-120850.29" switch \initial - attribute \src "libresoc.v:119243.9-119243.17" + attribute \src "libresoc.v:120850.9-120850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185755,18 +188175,18 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:119255.3-119267.6" - process $proc$libresoc.v:119255$4481 + attribute \src "libresoc.v:120862.3-120874.6" + process $proc$libresoc.v:120862$4522 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:119256.5-119256.29" + attribute \src "libresoc.v:120863.5-120863.29" switch \initial - attribute \src "libresoc.v:119256.9-119256.17" + attribute \src "libresoc.v:120863.9-120863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185782,18 +188202,18 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:119268.3-119280.6" - process $proc$libresoc.v:119268$4482 + attribute \src "libresoc.v:120875.3-120887.6" + process $proc$libresoc.v:120875$4523 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119269.5-119269.29" + attribute \src "libresoc.v:120876.5-120876.29" switch \initial - attribute \src "libresoc.v:119269.9-119269.17" + attribute \src "libresoc.v:120876.9-120876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185809,18 +188229,18 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:119281.3-119293.6" - process $proc$libresoc.v:119281$4483 + attribute \src "libresoc.v:120888.3-120900.6" + process $proc$libresoc.v:120888$4524 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119282.5-119282.29" + attribute \src "libresoc.v:120889.5-120889.29" switch \initial - attribute \src "libresoc.v:119282.9-119282.17" + attribute \src "libresoc.v:120889.9-120889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185836,18 +188256,18 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:119294.3-119306.6" - process $proc$libresoc.v:119294$4484 + attribute \src "libresoc.v:120901.3-120913.6" + process $proc$libresoc.v:120901$4525 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119295.5-119295.29" + attribute \src "libresoc.v:120902.5-120902.29" switch \initial - attribute \src "libresoc.v:119295.9-119295.17" + attribute \src "libresoc.v:120902.9-120902.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185863,18 +188283,18 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:119307.3-119319.6" - process $proc$libresoc.v:119307$4485 + attribute \src "libresoc.v:120914.3-120926.6" + process $proc$libresoc.v:120914$4526 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119308.5-119308.29" + attribute \src "libresoc.v:120915.5-120915.29" switch \initial - attribute \src "libresoc.v:119308.9-119308.17" + attribute \src "libresoc.v:120915.9-120915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185890,18 +188310,18 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:119320.3-119332.6" - process $proc$libresoc.v:119320$4486 + attribute \src "libresoc.v:120927.3-120939.6" + process $proc$libresoc.v:120927$4527 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119321.5-119321.29" + attribute \src "libresoc.v:120928.5-120928.29" switch \initial - attribute \src "libresoc.v:119321.9-119321.17" + attribute \src "libresoc.v:120928.9-120928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185917,18 +188337,18 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:119333.3-119345.6" - process $proc$libresoc.v:119333$4487 + attribute \src "libresoc.v:120940.3-120952.6" + process $proc$libresoc.v:120940$4528 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119334.5-119334.29" + attribute \src "libresoc.v:120941.5-120941.29" switch \initial - attribute \src "libresoc.v:119334.9-119334.17" + attribute \src "libresoc.v:120941.9-120941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185944,18 +188364,18 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:119346.3-119358.6" - process $proc$libresoc.v:119346$4488 + attribute \src "libresoc.v:120953.3-120965.6" + process $proc$libresoc.v:120953$4529 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:119347.5-119347.29" + attribute \src "libresoc.v:120954.5-120954.29" switch \initial - attribute \src "libresoc.v:119347.9-119347.17" + attribute \src "libresoc.v:120954.9-120954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185973,120 +188393,120 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:119364.1-119947.10" +attribute \src "libresoc.v:120971.1-121554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:119910.3-119924.6" + attribute \src "libresoc.v:121517.3-121531.6" wire width 14 $0\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119897.3-119909.6" + attribute \src "libresoc.v:121504.3-121516.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:119882.3-119896.6" + attribute \src "libresoc.v:121489.3-121503.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119365.7-119365.20" + attribute \src "libresoc.v:120972.7-120972.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119910.3-119924.6" + attribute \src "libresoc.v:121517.3-121531.6" wire width 14 $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119897.3-119909.6" + attribute \src "libresoc.v:121504.3-121516.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:119882.3-119896.6" + attribute \src "libresoc.v:121489.3-121503.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119798.18-119798.113" - wire $and$libresoc.v:119798$4490_Y - attribute \src "libresoc.v:119800.18-119800.110" - wire $and$libresoc.v:119800$4492_Y - attribute \src "libresoc.v:119813.18-119813.114" - wire $and$libresoc.v:119813$4505_Y - attribute \src "libresoc.v:119814.18-119814.116" - wire $and$libresoc.v:119814$4506_Y - attribute \src "libresoc.v:119816.18-119816.114" - wire $and$libresoc.v:119816$4508_Y - attribute \src "libresoc.v:119818.18-119818.110" - wire $and$libresoc.v:119818$4510_Y - attribute \src "libresoc.v:119819.17-119819.112" - wire $and$libresoc.v:119819$4511_Y - attribute \src "libresoc.v:119820.17-119820.114" - wire $and$libresoc.v:119820$4512_Y - attribute \src "libresoc.v:119801.18-119801.126" - wire $eq$libresoc.v:119801$4493_Y - attribute \src "libresoc.v:119802.18-119802.126" - wire $eq$libresoc.v:119802$4494_Y - attribute \src "libresoc.v:119804.18-119804.110" - wire $eq$libresoc.v:119804$4496_Y - attribute \src "libresoc.v:119805.18-119805.110" - wire $eq$libresoc.v:119805$4497_Y - attribute \src "libresoc.v:119807.18-119807.112" - wire $eq$libresoc.v:119807$4499_Y - attribute \src "libresoc.v:119808.17-119808.130" - wire $eq$libresoc.v:119808$4500_Y - attribute \src "libresoc.v:119810.18-119810.110" - wire $eq$libresoc.v:119810$4502_Y - attribute \src "libresoc.v:119812.18-119812.131" - wire $eq$libresoc.v:119812$4504_Y - attribute \src "libresoc.v:119815.18-119815.131" - wire $eq$libresoc.v:119815$4507_Y - attribute \src "libresoc.v:119821.17-119821.130" - wire $eq$libresoc.v:119821$4513_Y - attribute \src "libresoc.v:119799.18-119799.110" - wire $not$libresoc.v:119799$4491_Y - attribute \src "libresoc.v:119817.18-119817.110" - wire $not$libresoc.v:119817$4509_Y - attribute \src "libresoc.v:119803.18-119803.110" - wire $or$libresoc.v:119803$4495_Y - attribute \src "libresoc.v:119806.18-119806.110" - wire $or$libresoc.v:119806$4498_Y - attribute \src "libresoc.v:119809.18-119809.110" - wire $or$libresoc.v:119809$4501_Y - attribute \src "libresoc.v:119811.18-119811.110" - wire $or$libresoc.v:119811$4503_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:121405.18-121405.113" + wire $and$libresoc.v:121405$4531_Y + attribute \src "libresoc.v:121407.18-121407.110" + wire $and$libresoc.v:121407$4533_Y + attribute \src "libresoc.v:121420.18-121420.114" + wire $and$libresoc.v:121420$4546_Y + attribute \src "libresoc.v:121421.18-121421.116" + wire $and$libresoc.v:121421$4547_Y + attribute \src "libresoc.v:121423.18-121423.114" + wire $and$libresoc.v:121423$4549_Y + attribute \src "libresoc.v:121425.18-121425.110" + wire $and$libresoc.v:121425$4551_Y + attribute \src "libresoc.v:121426.17-121426.112" + wire $and$libresoc.v:121426$4552_Y + attribute \src "libresoc.v:121427.17-121427.114" + wire $and$libresoc.v:121427$4553_Y + attribute \src "libresoc.v:121408.18-121408.126" + wire $eq$libresoc.v:121408$4534_Y + attribute \src "libresoc.v:121409.18-121409.126" + wire $eq$libresoc.v:121409$4535_Y + attribute \src "libresoc.v:121411.18-121411.110" + wire $eq$libresoc.v:121411$4537_Y + attribute \src "libresoc.v:121412.18-121412.110" + wire $eq$libresoc.v:121412$4538_Y + attribute \src "libresoc.v:121414.18-121414.112" + wire $eq$libresoc.v:121414$4540_Y + attribute \src "libresoc.v:121415.17-121415.130" + wire $eq$libresoc.v:121415$4541_Y + attribute \src "libresoc.v:121417.18-121417.110" + wire $eq$libresoc.v:121417$4543_Y + attribute \src "libresoc.v:121419.18-121419.131" + wire $eq$libresoc.v:121419$4545_Y + attribute \src "libresoc.v:121422.18-121422.131" + wire $eq$libresoc.v:121422$4548_Y + attribute \src "libresoc.v:121428.17-121428.130" + wire $eq$libresoc.v:121428$4554_Y + attribute \src "libresoc.v:121406.18-121406.110" + wire $not$libresoc.v:121406$4532_Y + attribute \src "libresoc.v:121424.18-121424.110" + wire $not$libresoc.v:121424$4550_Y + attribute \src "libresoc.v:121410.18-121410.110" + wire $or$libresoc.v:121410$4536_Y + attribute \src "libresoc.v:121413.18-121413.110" + wire $or$libresoc.v:121413$4539_Y + attribute \src "libresoc.v:121416.18-121416.110" + wire $or$libresoc.v:121416$4542_Y + attribute \src "libresoc.v:121418.18-121418.110" + wire $or$libresoc.v:121418$4544_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \ALU__data_len @@ -186218,27 +188638,27 @@ module \dec_ALU wire output 14 \ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -186247,15 +188667,15 @@ module \dec_ALU attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -186272,7 +188692,7 @@ module \dec_ALU attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -186280,7 +188700,7 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -186297,7 +188717,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186374,13 +188794,13 @@ module \dec_ALU attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -186388,19 +188808,19 @@ module \dec_ALU attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -186408,9 +188828,9 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -186431,7 +188851,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -186441,9 +188861,9 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -186453,26 +188873,26 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119365.7-119365.15" + attribute \src "libresoc.v:120972.7-120972.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119798$4490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121405$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186480,10 +188900,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:119798$4490_Y + connect \Y $and$libresoc.v:121405$4531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119800$4492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121407$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186491,10 +188911,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:119800$4492_Y + connect \Y $and$libresoc.v:121407$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119813$4505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121420$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186502,10 +188922,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:119813$4505_Y + connect \Y $and$libresoc.v:121420$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119814$4506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121421$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186513,10 +188933,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119814$4506_Y + connect \Y $and$libresoc.v:121421$4547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119816$4508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121423$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186524,10 +188944,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:119816$4508_Y + connect \Y $and$libresoc.v:121423$4549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119818$4510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121425$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186535,10 +188955,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:119818$4510_Y + connect \Y $and$libresoc.v:121425$4551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119819$4511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121426$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186546,10 +188966,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:119819$4511_Y + connect \Y $and$libresoc.v:121426$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119820$4512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121427$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186557,10 +188977,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119820$4512_Y + connect \Y $and$libresoc.v:121427$4553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:119801$4493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121408$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186568,10 +188988,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119801$4493_Y + connect \Y $eq$libresoc.v:121408$4534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:119802$4494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:121409$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186579,10 +188999,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119802$4494_Y + connect \Y $eq$libresoc.v:121409$4535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119804$4496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121411$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186590,10 +189010,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:119804$4496_Y + connect \Y $eq$libresoc.v:121411$4537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119805$4497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121412$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186601,10 +189021,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:119805$4497_Y + connect \Y $eq$libresoc.v:121412$4538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119807$4499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121414$4540 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186612,10 +189032,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119807$4499_Y + connect \Y $eq$libresoc.v:121414$4540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:119808$4500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121415$4541 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186623,10 +189043,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:119808$4500_Y + connect \Y $eq$libresoc.v:121415$4541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:119810$4502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:121417$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186634,10 +189054,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:119810$4502_Y + connect \Y $eq$libresoc.v:121417$4543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:119812$4504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121419$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186645,10 +189065,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:119812$4504_Y + connect \Y $eq$libresoc.v:121419$4545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:119815$4507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121422$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186656,10 +189076,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:119815$4507_Y + connect \Y $eq$libresoc.v:121422$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:119821$4513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121428$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186667,26 +189087,26 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:119821$4513_Y + connect \Y $eq$libresoc.v:121428$4554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:119799$4491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121406$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119799$4491_Y + connect \Y $not$libresoc.v:121406$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:119817$4509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121424$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119817$4509_Y + connect \Y $not$libresoc.v:121424$4550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:119803$4495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:121410$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186694,10 +189114,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:119803$4495_Y + connect \Y $or$libresoc.v:121410$4536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:119806$4498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121413$4539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186705,10 +189125,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:119806$4498_Y + connect \Y $or$libresoc.v:121413$4539_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:119809$4501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121416$4542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186716,10 +189136,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:119809$4501_Y + connect \Y $or$libresoc.v:121416$4542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:119811$4503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121418$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186727,10 +189147,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:119811$4503_Y + connect \Y $or$libresoc.v:121418$4544_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119822.7-119850.4" + attribute \src "libresoc.v:121429.7-121457.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -186761,7 +189181,7 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119851.10-119856.4" + attribute \src "libresoc.v:121458.10-121463.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out @@ -186769,7 +189189,7 @@ module \dec_ALU connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:119857.10-119868.4" + attribute \src "libresoc.v:121464.10-121475.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -186783,7 +189203,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119869.10-119875.4" + attribute \src "libresoc.v:121476.10-121482.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -186792,33 +189212,33 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119876.10-119881.4" + attribute \src "libresoc.v:121483.10-121488.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119365.7-119365.20" - process $proc$libresoc.v:119365$4517 + attribute \src "libresoc.v:120972.7-120972.20" + process $proc$libresoc.v:120972$4558 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119882.3-119896.6" - process $proc$libresoc.v:119882$4514 + attribute \src "libresoc.v:121489.3-121503.6" + process $proc$libresoc.v:121489$4555 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119883.5-119883.29" + attribute \src "libresoc.v:121490.5-121490.29" switch \initial - attribute \src "libresoc.v:119883.9-119883.17" + attribute \src "libresoc.v:121490.9-121490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -186834,18 +189254,18 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:119897.3-119909.6" - process $proc$libresoc.v:119897$4515 + attribute \src "libresoc.v:121504.3-121516.6" + process $proc$libresoc.v:121504$4556 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:119898.5-119898.29" + attribute \src "libresoc.v:121505.5-121505.29" switch \initial - attribute \src "libresoc.v:119898.9-119898.17" + attribute \src "libresoc.v:121505.9-121505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -186861,17 +189281,17 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:119910.3-119924.6" - process $proc$libresoc.v:119910$4516 + attribute \src "libresoc.v:121517.3-121531.6" + process $proc$libresoc.v:121517$4557 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119911.5-119911.29" + attribute \src "libresoc.v:121518.5-121518.29" switch \initial - attribute \src "libresoc.v:119911.9-119911.17" + attribute \src "libresoc.v:121518.9-121518.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -186889,30 +189309,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end - connect \$10 $and$libresoc.v:119798$4490_Y - connect \$12 $not$libresoc.v:119799$4491_Y - connect \$14 $and$libresoc.v:119800$4492_Y - connect \$16 $eq$libresoc.v:119801$4493_Y - connect \$18 $eq$libresoc.v:119802$4494_Y - connect \$20 $or$libresoc.v:119803$4495_Y - connect \$22 $eq$libresoc.v:119804$4496_Y - connect \$24 $eq$libresoc.v:119805$4497_Y - connect \$26 $or$libresoc.v:119806$4498_Y - connect \$28 $eq$libresoc.v:119807$4499_Y - connect \$2 $eq$libresoc.v:119808$4500_Y - connect \$30 $or$libresoc.v:119809$4501_Y - connect \$32 $eq$libresoc.v:119810$4502_Y - connect \$34 $or$libresoc.v:119811$4503_Y - connect \$36 $eq$libresoc.v:119812$4504_Y - connect \$38 $and$libresoc.v:119813$4505_Y - connect \$40 $and$libresoc.v:119814$4506_Y - connect \$42 $eq$libresoc.v:119815$4507_Y - connect \$44 $and$libresoc.v:119816$4508_Y - connect \$46 $not$libresoc.v:119817$4509_Y - connect \$48 $and$libresoc.v:119818$4510_Y - connect \$4 $and$libresoc.v:119819$4511_Y - connect \$6 $and$libresoc.v:119820$4512_Y - connect \$8 $eq$libresoc.v:119821$4513_Y + connect \$10 $and$libresoc.v:121405$4531_Y + connect \$12 $not$libresoc.v:121406$4532_Y + connect \$14 $and$libresoc.v:121407$4533_Y + connect \$16 $eq$libresoc.v:121408$4534_Y + connect \$18 $eq$libresoc.v:121409$4535_Y + connect \$20 $or$libresoc.v:121410$4536_Y + connect \$22 $eq$libresoc.v:121411$4537_Y + connect \$24 $eq$libresoc.v:121412$4538_Y + connect \$26 $or$libresoc.v:121413$4539_Y + connect \$28 $eq$libresoc.v:121414$4540_Y + connect \$2 $eq$libresoc.v:121415$4541_Y + connect \$30 $or$libresoc.v:121416$4542_Y + connect \$32 $eq$libresoc.v:121417$4543_Y + connect \$34 $or$libresoc.v:121418$4544_Y + connect \$36 $eq$libresoc.v:121419$4545_Y + connect \$38 $and$libresoc.v:121420$4546_Y + connect \$40 $and$libresoc.v:121421$4547_Y + connect \$42 $eq$libresoc.v:121422$4548_Y + connect \$44 $and$libresoc.v:121423$4549_Y + connect \$46 $not$libresoc.v:121424$4550_Y + connect \$48 $and$libresoc.v:121425$4551_Y + connect \$4 $and$libresoc.v:121426$4552_Y + connect \$6 $and$libresoc.v:121427$4553_Y + connect \$8 $eq$libresoc.v:121428$4554_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -186936,120 +189356,120 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:119951.1-120431.10" +attribute \src "libresoc.v:121558.1-122038.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:120381.3-120395.6" + attribute \src "libresoc.v:121988.3-122002.6" wire width 14 $0\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120406.3-120418.6" + attribute \src "libresoc.v:122013.3-122025.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120396.3-120405.6" + attribute \src "libresoc.v:122003.3-122012.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:119952.7-119952.20" + attribute \src "libresoc.v:121559.7-121559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120381.3-120395.6" + attribute \src "libresoc.v:121988.3-122002.6" wire width 14 $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120406.3-120418.6" + attribute \src "libresoc.v:122013.3-122025.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120396.3-120405.6" + attribute \src "libresoc.v:122003.3-122012.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:120313.18-120313.113" - wire $and$libresoc.v:120313$4518_Y - attribute \src "libresoc.v:120315.18-120315.110" - wire $and$libresoc.v:120315$4520_Y - attribute \src "libresoc.v:120328.18-120328.114" - wire $and$libresoc.v:120328$4533_Y - attribute \src "libresoc.v:120329.18-120329.116" - wire $and$libresoc.v:120329$4534_Y - attribute \src "libresoc.v:120331.18-120331.114" - wire $and$libresoc.v:120331$4536_Y - attribute \src "libresoc.v:120333.18-120333.110" - wire $and$libresoc.v:120333$4538_Y - attribute \src "libresoc.v:120334.17-120334.112" - wire $and$libresoc.v:120334$4539_Y - attribute \src "libresoc.v:120335.17-120335.114" - wire $and$libresoc.v:120335$4540_Y - attribute \src "libresoc.v:120316.18-120316.129" - wire $eq$libresoc.v:120316$4521_Y - attribute \src "libresoc.v:120317.18-120317.129" - wire $eq$libresoc.v:120317$4522_Y - attribute \src "libresoc.v:120319.18-120319.110" - wire $eq$libresoc.v:120319$4524_Y - attribute \src "libresoc.v:120320.18-120320.110" - wire $eq$libresoc.v:120320$4525_Y - attribute \src "libresoc.v:120322.18-120322.112" - wire $eq$libresoc.v:120322$4527_Y - attribute \src "libresoc.v:120323.17-120323.133" - wire $eq$libresoc.v:120323$4528_Y - attribute \src "libresoc.v:120325.18-120325.110" - wire $eq$libresoc.v:120325$4530_Y - attribute \src "libresoc.v:120327.18-120327.134" - wire $eq$libresoc.v:120327$4532_Y - attribute \src "libresoc.v:120330.18-120330.134" - wire $eq$libresoc.v:120330$4535_Y - attribute \src "libresoc.v:120336.17-120336.133" - wire $eq$libresoc.v:120336$4541_Y - attribute \src "libresoc.v:120314.18-120314.110" - wire $not$libresoc.v:120314$4519_Y - attribute \src "libresoc.v:120332.18-120332.110" - wire $not$libresoc.v:120332$4537_Y - attribute \src "libresoc.v:120318.18-120318.110" - wire $or$libresoc.v:120318$4523_Y - attribute \src "libresoc.v:120321.18-120321.110" - wire $or$libresoc.v:120321$4526_Y - attribute \src "libresoc.v:120324.18-120324.110" - wire $or$libresoc.v:120324$4529_Y - attribute \src "libresoc.v:120326.18-120326.110" - wire $or$libresoc.v:120326$4531_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:121920.18-121920.113" + wire $and$libresoc.v:121920$4559_Y + attribute \src "libresoc.v:121922.18-121922.110" + wire $and$libresoc.v:121922$4561_Y + attribute \src "libresoc.v:121935.18-121935.114" + wire $and$libresoc.v:121935$4574_Y + attribute \src "libresoc.v:121936.18-121936.116" + wire $and$libresoc.v:121936$4575_Y + attribute \src "libresoc.v:121938.18-121938.114" + wire $and$libresoc.v:121938$4577_Y + attribute \src "libresoc.v:121940.18-121940.110" + wire $and$libresoc.v:121940$4579_Y + attribute \src "libresoc.v:121941.17-121941.112" + wire $and$libresoc.v:121941$4580_Y + attribute \src "libresoc.v:121942.17-121942.114" + wire $and$libresoc.v:121942$4581_Y + attribute \src "libresoc.v:121923.18-121923.129" + wire $eq$libresoc.v:121923$4562_Y + attribute \src "libresoc.v:121924.18-121924.129" + wire $eq$libresoc.v:121924$4563_Y + attribute \src "libresoc.v:121926.18-121926.110" + wire $eq$libresoc.v:121926$4565_Y + attribute \src "libresoc.v:121927.18-121927.110" + wire $eq$libresoc.v:121927$4566_Y + attribute \src "libresoc.v:121929.18-121929.112" + wire $eq$libresoc.v:121929$4568_Y + attribute \src "libresoc.v:121930.17-121930.133" + wire $eq$libresoc.v:121930$4569_Y + attribute \src "libresoc.v:121932.18-121932.110" + wire $eq$libresoc.v:121932$4571_Y + attribute \src "libresoc.v:121934.18-121934.134" + wire $eq$libresoc.v:121934$4573_Y + attribute \src "libresoc.v:121937.18-121937.134" + wire $eq$libresoc.v:121937$4576_Y + attribute \src "libresoc.v:121943.17-121943.133" + wire $eq$libresoc.v:121943$4582_Y + attribute \src "libresoc.v:121921.18-121921.110" + wire $not$libresoc.v:121921$4560_Y + attribute \src "libresoc.v:121939.18-121939.110" + wire $not$libresoc.v:121939$4578_Y + attribute \src "libresoc.v:121925.18-121925.110" + wire $or$libresoc.v:121925$4564_Y + attribute \src "libresoc.v:121928.18-121928.110" + wire $or$libresoc.v:121928$4567_Y + attribute \src "libresoc.v:121931.18-121931.110" + wire $or$libresoc.v:121931$4570_Y + attribute \src "libresoc.v:121933.18-121933.110" + wire $or$libresoc.v:121933$4572_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia @@ -187157,29 +189577,29 @@ module \dec_BRANCH wire output 10 \BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 2 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -187188,7 +189608,7 @@ module \dec_BRANCH attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -187205,7 +189625,7 @@ module \dec_BRANCH attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -187222,7 +189642,7 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187299,19 +189719,19 @@ module \dec_BRANCH attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -187332,38 +189752,38 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119952.7-119952.15" + attribute \src "libresoc.v:121559.7-121559.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120313$4518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121920$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187371,10 +189791,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120313$4518_Y + connect \Y $and$libresoc.v:121920$4559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120315$4520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121922$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187382,10 +189802,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120315$4520_Y + connect \Y $and$libresoc.v:121922$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120328$4533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121935$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187393,10 +189813,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120328$4533_Y + connect \Y $and$libresoc.v:121935$4574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120329$4534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121936$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187404,10 +189824,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120329$4534_Y + connect \Y $and$libresoc.v:121936$4575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120331$4536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121938$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187415,10 +189835,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120331$4536_Y + connect \Y $and$libresoc.v:121938$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120333$4538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121940$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187426,10 +189846,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120333$4538_Y + connect \Y $and$libresoc.v:121940$4579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120334$4539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121941$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187437,10 +189857,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120334$4539_Y + connect \Y $and$libresoc.v:121941$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120335$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121942$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187448,10 +189868,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120335$4540_Y + connect \Y $and$libresoc.v:121942$4581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120316$4521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121923$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187459,10 +189879,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120316$4521_Y + connect \Y $eq$libresoc.v:121923$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:120317$4522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:121924$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187470,10 +189890,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120317$4522_Y + connect \Y $eq$libresoc.v:121924$4563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120319$4524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121926$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187481,10 +189901,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120319$4524_Y + connect \Y $eq$libresoc.v:121926$4565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120320$4525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121927$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187492,10 +189912,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120320$4525_Y + connect \Y $eq$libresoc.v:121927$4566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120322$4527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121929$4568 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187503,10 +189923,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120322$4527_Y + connect \Y $eq$libresoc.v:121929$4568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120323$4528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121930$4569 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187514,10 +189934,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120323$4528_Y + connect \Y $eq$libresoc.v:121930$4569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:120325$4530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:121932$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187525,10 +189945,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120325$4530_Y + connect \Y $eq$libresoc.v:121932$4571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120327$4532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121934$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187536,10 +189956,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120327$4532_Y + connect \Y $eq$libresoc.v:121934$4573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120330$4535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121937$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187547,10 +189967,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120330$4535_Y + connect \Y $eq$libresoc.v:121937$4576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120336$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121943$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187558,26 +189978,26 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120336$4541_Y + connect \Y $eq$libresoc.v:121943$4582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120314$4519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121921$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120314$4519_Y + connect \Y $not$libresoc.v:121921$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120332$4537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121939$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120332$4537_Y + connect \Y $not$libresoc.v:121939$4578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:120318$4523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:121925$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187585,10 +190005,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120318$4523_Y + connect \Y $or$libresoc.v:121925$4564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120321$4526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121928$4567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187596,10 +190016,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120321$4526_Y + connect \Y $or$libresoc.v:121928$4567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120324$4529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121931$4570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187607,10 +190027,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120324$4529_Y + connect \Y $or$libresoc.v:121931$4570_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:120326$4531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121933$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187618,10 +190038,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120326$4531_Y + connect \Y $or$libresoc.v:121933$4572_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120337.13-120359.4" + attribute \src "libresoc.v:121944.13-121966.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -187646,7 +190066,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120360.16-120371.4" + attribute \src "libresoc.v:121967.16-121978.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -187660,37 +190080,37 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120372.16-120376.4" + attribute \src "libresoc.v:121979.16-121983.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120377.16-120380.4" + attribute \src "libresoc.v:121984.16-121987.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119952.7-119952.20" - process $proc$libresoc.v:119952$4545 + attribute \src "libresoc.v:121559.7-121559.20" + process $proc$libresoc.v:121559$4586 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120381.3-120395.6" - process $proc$libresoc.v:120381$4542 + attribute \src "libresoc.v:121988.3-122002.6" + process $proc$libresoc.v:121988$4583 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120382.5-120382.29" + attribute \src "libresoc.v:121989.5-121989.29" switch \initial - attribute \src "libresoc.v:120382.9-120382.17" + attribute \src "libresoc.v:121989.9-121989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -187708,18 +190128,18 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:120396.3-120405.6" - process $proc$libresoc.v:120396$4543 + attribute \src "libresoc.v:122003.3-122012.6" + process $proc$libresoc.v:122003$4584 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:120397.5-120397.29" + attribute \src "libresoc.v:122004.5-122004.29" switch \initial - attribute \src "libresoc.v:120397.9-120397.17" + attribute \src "libresoc.v:122004.9-122004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -187731,18 +190151,18 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:120406.3-120418.6" - process $proc$libresoc.v:120406$4544 + attribute \src "libresoc.v:122013.3-122025.6" + process $proc$libresoc.v:122013$4585 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120407.5-120407.29" + attribute \src "libresoc.v:122014.5-122014.29" switch \initial - attribute \src "libresoc.v:120407.9-120407.17" + attribute \src "libresoc.v:122014.9-122014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -187758,30 +190178,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:120313$4518_Y - connect \$12 $not$libresoc.v:120314$4519_Y - connect \$14 $and$libresoc.v:120315$4520_Y - connect \$16 $eq$libresoc.v:120316$4521_Y - connect \$18 $eq$libresoc.v:120317$4522_Y - connect \$20 $or$libresoc.v:120318$4523_Y - connect \$22 $eq$libresoc.v:120319$4524_Y - connect \$24 $eq$libresoc.v:120320$4525_Y - connect \$26 $or$libresoc.v:120321$4526_Y - connect \$28 $eq$libresoc.v:120322$4527_Y - connect \$2 $eq$libresoc.v:120323$4528_Y - connect \$30 $or$libresoc.v:120324$4529_Y - connect \$32 $eq$libresoc.v:120325$4530_Y - connect \$34 $or$libresoc.v:120326$4531_Y - connect \$36 $eq$libresoc.v:120327$4532_Y - connect \$38 $and$libresoc.v:120328$4533_Y - connect \$40 $and$libresoc.v:120329$4534_Y - connect \$42 $eq$libresoc.v:120330$4535_Y - connect \$44 $and$libresoc.v:120331$4536_Y - connect \$46 $not$libresoc.v:120332$4537_Y - connect \$48 $and$libresoc.v:120333$4538_Y - connect \$4 $and$libresoc.v:120334$4539_Y - connect \$6 $and$libresoc.v:120335$4540_Y - connect \$8 $eq$libresoc.v:120336$4541_Y + connect \$10 $and$libresoc.v:121920$4559_Y + connect \$12 $not$libresoc.v:121921$4560_Y + connect \$14 $and$libresoc.v:121922$4561_Y + connect \$16 $eq$libresoc.v:121923$4562_Y + connect \$18 $eq$libresoc.v:121924$4563_Y + connect \$20 $or$libresoc.v:121925$4564_Y + connect \$22 $eq$libresoc.v:121926$4565_Y + connect \$24 $eq$libresoc.v:121927$4566_Y + connect \$26 $or$libresoc.v:121928$4567_Y + connect \$28 $eq$libresoc.v:121929$4568_Y + connect \$2 $eq$libresoc.v:121930$4569_Y + connect \$30 $or$libresoc.v:121931$4570_Y + connect \$32 $eq$libresoc.v:121932$4571_Y + connect \$34 $or$libresoc.v:121933$4572_Y + connect \$36 $eq$libresoc.v:121934$4573_Y + connect \$38 $and$libresoc.v:121935$4574_Y + connect \$40 $and$libresoc.v:121936$4575_Y + connect \$42 $eq$libresoc.v:121937$4576_Y + connect \$44 $and$libresoc.v:121938$4577_Y + connect \$46 $not$libresoc.v:121939$4578_Y + connect \$48 $and$libresoc.v:121940$4579_Y + connect \$4 $and$libresoc.v:121941$4580_Y + connect \$6 $and$libresoc.v:121942$4581_Y + connect \$8 $eq$libresoc.v:121943$4582_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -187795,116 +190215,116 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:120435.1-120807.10" +attribute \src "libresoc.v:122042.1-122414.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:120784.3-120798.6" + attribute \src "libresoc.v:122391.3-122405.6" wire width 14 $0\CR__fn_unit[13:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:122378.3-122390.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:120436.7-120436.20" + attribute \src "libresoc.v:122043.7-122043.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120784.3-120798.6" + attribute \src "libresoc.v:122391.3-122405.6" wire width 14 $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:122378.3-122390.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:120726.18-120726.113" - wire $and$libresoc.v:120726$4546_Y - attribute \src "libresoc.v:120728.18-120728.110" - wire $and$libresoc.v:120728$4548_Y - attribute \src "libresoc.v:120741.18-120741.114" - wire $and$libresoc.v:120741$4561_Y - attribute \src "libresoc.v:120742.18-120742.116" - wire $and$libresoc.v:120742$4562_Y - attribute \src "libresoc.v:120744.18-120744.114" - wire $and$libresoc.v:120744$4564_Y - attribute \src "libresoc.v:120746.18-120746.110" - wire $and$libresoc.v:120746$4566_Y - attribute \src "libresoc.v:120747.17-120747.112" - wire $and$libresoc.v:120747$4567_Y - attribute \src "libresoc.v:120748.17-120748.114" - wire $and$libresoc.v:120748$4568_Y - attribute \src "libresoc.v:120729.18-120729.125" - wire $eq$libresoc.v:120729$4549_Y - attribute \src "libresoc.v:120730.18-120730.125" - wire $eq$libresoc.v:120730$4550_Y - attribute \src "libresoc.v:120732.18-120732.110" - wire $eq$libresoc.v:120732$4552_Y - attribute \src "libresoc.v:120733.18-120733.110" - wire $eq$libresoc.v:120733$4553_Y - attribute \src "libresoc.v:120735.18-120735.112" - wire $eq$libresoc.v:120735$4555_Y - attribute \src "libresoc.v:120736.17-120736.129" - wire $eq$libresoc.v:120736$4556_Y - attribute \src "libresoc.v:120738.18-120738.110" - wire $eq$libresoc.v:120738$4558_Y - attribute \src "libresoc.v:120740.18-120740.130" - wire $eq$libresoc.v:120740$4560_Y - attribute \src "libresoc.v:120743.18-120743.130" - wire $eq$libresoc.v:120743$4563_Y - attribute \src "libresoc.v:120749.17-120749.129" - wire $eq$libresoc.v:120749$4569_Y - attribute \src "libresoc.v:120727.18-120727.110" - wire $not$libresoc.v:120727$4547_Y - attribute \src "libresoc.v:120745.18-120745.110" - wire $not$libresoc.v:120745$4565_Y - attribute \src "libresoc.v:120731.18-120731.110" - wire $or$libresoc.v:120731$4551_Y - attribute \src "libresoc.v:120734.18-120734.110" - wire $or$libresoc.v:120734$4554_Y - attribute \src "libresoc.v:120737.18-120737.110" - wire $or$libresoc.v:120737$4557_Y - attribute \src "libresoc.v:120739.18-120739.110" - wire $or$libresoc.v:120739$4559_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:122333.18-122333.113" + wire $and$libresoc.v:122333$4587_Y + attribute \src "libresoc.v:122335.18-122335.110" + wire $and$libresoc.v:122335$4589_Y + attribute \src "libresoc.v:122348.18-122348.114" + wire $and$libresoc.v:122348$4602_Y + attribute \src "libresoc.v:122349.18-122349.116" + wire $and$libresoc.v:122349$4603_Y + attribute \src "libresoc.v:122351.18-122351.114" + wire $and$libresoc.v:122351$4605_Y + attribute \src "libresoc.v:122353.18-122353.110" + wire $and$libresoc.v:122353$4607_Y + attribute \src "libresoc.v:122354.17-122354.112" + wire $and$libresoc.v:122354$4608_Y + attribute \src "libresoc.v:122355.17-122355.114" + wire $and$libresoc.v:122355$4609_Y + attribute \src "libresoc.v:122336.18-122336.125" + wire $eq$libresoc.v:122336$4590_Y + attribute \src "libresoc.v:122337.18-122337.125" + wire $eq$libresoc.v:122337$4591_Y + attribute \src "libresoc.v:122339.18-122339.110" + wire $eq$libresoc.v:122339$4593_Y + attribute \src "libresoc.v:122340.18-122340.110" + wire $eq$libresoc.v:122340$4594_Y + attribute \src "libresoc.v:122342.18-122342.112" + wire $eq$libresoc.v:122342$4596_Y + attribute \src "libresoc.v:122343.17-122343.129" + wire $eq$libresoc.v:122343$4597_Y + attribute \src "libresoc.v:122345.18-122345.110" + wire $eq$libresoc.v:122345$4599_Y + attribute \src "libresoc.v:122347.18-122347.130" + wire $eq$libresoc.v:122347$4601_Y + attribute \src "libresoc.v:122350.18-122350.130" + wire $eq$libresoc.v:122350$4604_Y + attribute \src "libresoc.v:122356.17-122356.129" + wire $eq$libresoc.v:122356$4610_Y + attribute \src "libresoc.v:122334.18-122334.110" + wire $not$libresoc.v:122334$4588_Y + attribute \src "libresoc.v:122352.18-122352.110" + wire $not$libresoc.v:122352$4606_Y + attribute \src "libresoc.v:122338.18-122338.110" + wire $or$libresoc.v:122338$4592_Y + attribute \src "libresoc.v:122341.18-122341.110" + wire $or$libresoc.v:122341$4595_Y + attribute \src "libresoc.v:122344.18-122344.110" + wire $or$libresoc.v:122344$4598_Y + attribute \src "libresoc.v:122346.18-122346.110" + wire $or$libresoc.v:122346$4600_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188002,13 +190422,13 @@ module \dec_CR attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_CR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -188017,7 +190437,7 @@ module \dec_CR attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188034,7 +190454,7 @@ module \dec_CR attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -188111,44 +190531,44 @@ module \dec_CR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_CR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120436.7-120436.15" + attribute \src "libresoc.v:122043.7-122043.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 5 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120726$4546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122333$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188156,10 +190576,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120726$4546_Y + connect \Y $and$libresoc.v:122333$4587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120728$4548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122335$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188167,10 +190587,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120728$4548_Y + connect \Y $and$libresoc.v:122335$4589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120741$4561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122348$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188178,10 +190598,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120741$4561_Y + connect \Y $and$libresoc.v:122348$4602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120742$4562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122349$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188189,10 +190609,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120742$4562_Y + connect \Y $and$libresoc.v:122349$4603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120744$4564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122351$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188200,10 +190620,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120744$4564_Y + connect \Y $and$libresoc.v:122351$4605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120746$4566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122353$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188211,10 +190631,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120746$4566_Y + connect \Y $and$libresoc.v:122353$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120747$4567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122354$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188222,10 +190642,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120747$4567_Y + connect \Y $and$libresoc.v:122354$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120748$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122355$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188233,10 +190653,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120748$4568_Y + connect \Y $and$libresoc.v:122355$4609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120729$4549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122336$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188244,10 +190664,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120729$4549_Y + connect \Y $eq$libresoc.v:122336$4590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:120730$4550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:122337$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188255,10 +190675,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120730$4550_Y + connect \Y $eq$libresoc.v:122337$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120732$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122339$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188266,10 +190686,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120732$4552_Y + connect \Y $eq$libresoc.v:122339$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120733$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122340$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188277,10 +190697,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120733$4553_Y + connect \Y $eq$libresoc.v:122340$4594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120735$4555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122342$4596 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188288,10 +190708,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120735$4555_Y + connect \Y $eq$libresoc.v:122342$4596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120736$4556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122343$4597 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188299,10 +190719,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120736$4556_Y + connect \Y $eq$libresoc.v:122343$4597_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:120738$4558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:122345$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188310,10 +190730,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120738$4558_Y + connect \Y $eq$libresoc.v:122345$4599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120740$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122347$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188321,10 +190741,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120740$4560_Y + connect \Y $eq$libresoc.v:122347$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120743$4563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122350$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188332,10 +190752,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120743$4563_Y + connect \Y $eq$libresoc.v:122350$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120749$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122356$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188343,26 +190763,26 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120749$4569_Y + connect \Y $eq$libresoc.v:122356$4610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120727$4547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122334$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120727$4547_Y + connect \Y $not$libresoc.v:122334$4588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120745$4565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122352$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120745$4565_Y + connect \Y $not$libresoc.v:122352$4606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:120731$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:122338$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188370,10 +190790,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120731$4551_Y + connect \Y $or$libresoc.v:122338$4592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120734$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122341$4595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188381,10 +190801,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120734$4554_Y + connect \Y $or$libresoc.v:122341$4595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120737$4557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122344$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188392,10 +190812,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120737$4557_Y + connect \Y $or$libresoc.v:122344$4598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:120739$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:122346$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188403,10 +190823,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120739$4559_Y + connect \Y $or$libresoc.v:122346$4600_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120750.13-120761.4" + attribute \src "libresoc.v:122357.13-122368.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -188420,38 +190840,38 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120762.16-120766.4" + attribute \src "libresoc.v:122369.16-122373.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120767.16-120770.4" + attribute \src "libresoc.v:122374.16-122377.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120436.7-120436.20" - process $proc$libresoc.v:120436$4572 + attribute \src "libresoc.v:122043.7-122043.20" + process $proc$libresoc.v:122043$4613 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120771.3-120783.6" - process $proc$libresoc.v:120771$4570 + attribute \src "libresoc.v:122378.3-122390.6" + process $proc$libresoc.v:122378$4611 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:120772.5-120772.29" + attribute \src "libresoc.v:122379.5-122379.29" switch \initial - attribute \src "libresoc.v:120772.9-120772.17" + attribute \src "libresoc.v:122379.9-122379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -188467,17 +190887,17 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:120784.3-120798.6" - process $proc$libresoc.v:120784$4571 + attribute \src "libresoc.v:122391.3-122405.6" + process $proc$libresoc.v:122391$4612 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:120785.5-120785.29" + attribute \src "libresoc.v:122392.5-122392.29" switch \initial - attribute \src "libresoc.v:120785.9-120785.17" + attribute \src "libresoc.v:122392.9-122392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -188495,30 +190915,30 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:120726$4546_Y - connect \$12 $not$libresoc.v:120727$4547_Y - connect \$14 $and$libresoc.v:120728$4548_Y - connect \$16 $eq$libresoc.v:120729$4549_Y - connect \$18 $eq$libresoc.v:120730$4550_Y - connect \$20 $or$libresoc.v:120731$4551_Y - connect \$22 $eq$libresoc.v:120732$4552_Y - connect \$24 $eq$libresoc.v:120733$4553_Y - connect \$26 $or$libresoc.v:120734$4554_Y - connect \$28 $eq$libresoc.v:120735$4555_Y - connect \$2 $eq$libresoc.v:120736$4556_Y - connect \$30 $or$libresoc.v:120737$4557_Y - connect \$32 $eq$libresoc.v:120738$4558_Y - connect \$34 $or$libresoc.v:120739$4559_Y - connect \$36 $eq$libresoc.v:120740$4560_Y - connect \$38 $and$libresoc.v:120741$4561_Y - connect \$40 $and$libresoc.v:120742$4562_Y - connect \$42 $eq$libresoc.v:120743$4563_Y - connect \$44 $and$libresoc.v:120744$4564_Y - connect \$46 $not$libresoc.v:120745$4565_Y - connect \$48 $and$libresoc.v:120746$4566_Y - connect \$4 $and$libresoc.v:120747$4567_Y - connect \$6 $and$libresoc.v:120748$4568_Y - connect \$8 $eq$libresoc.v:120749$4569_Y + connect \$10 $and$libresoc.v:122333$4587_Y + connect \$12 $not$libresoc.v:122334$4588_Y + connect \$14 $and$libresoc.v:122335$4589_Y + connect \$16 $eq$libresoc.v:122336$4590_Y + connect \$18 $eq$libresoc.v:122337$4591_Y + connect \$20 $or$libresoc.v:122338$4592_Y + connect \$22 $eq$libresoc.v:122339$4593_Y + connect \$24 $eq$libresoc.v:122340$4594_Y + connect \$26 $or$libresoc.v:122341$4595_Y + connect \$28 $eq$libresoc.v:122342$4596_Y + connect \$2 $eq$libresoc.v:122343$4597_Y + connect \$30 $or$libresoc.v:122344$4598_Y + connect \$32 $eq$libresoc.v:122345$4599_Y + connect \$34 $or$libresoc.v:122346$4600_Y + connect \$36 $eq$libresoc.v:122347$4601_Y + connect \$38 $and$libresoc.v:122348$4602_Y + connect \$40 $and$libresoc.v:122349$4603_Y + connect \$42 $eq$libresoc.v:122350$4604_Y + connect \$44 $and$libresoc.v:122351$4605_Y + connect \$46 $not$libresoc.v:122352$4606_Y + connect \$48 $and$libresoc.v:122353$4607_Y + connect \$4 $and$libresoc.v:122354$4608_Y + connect \$6 $and$libresoc.v:122355$4609_Y + connect \$8 $eq$libresoc.v:122356$4610_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -188528,120 +190948,120 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:120811.1-121394.10" +attribute \src "libresoc.v:122418.1-123001.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:121357.3-121371.6" + attribute \src "libresoc.v:122964.3-122978.6" wire width 14 $0\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121344.3-121356.6" + attribute \src "libresoc.v:122951.3-122963.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:121329.3-121343.6" + attribute \src "libresoc.v:122936.3-122950.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:120812.7-120812.20" + attribute \src "libresoc.v:122419.7-122419.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121357.3-121371.6" + attribute \src "libresoc.v:122964.3-122978.6" wire width 14 $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121344.3-121356.6" + attribute \src "libresoc.v:122951.3-122963.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:121329.3-121343.6" + attribute \src "libresoc.v:122936.3-122950.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:121245.18-121245.113" - wire $and$libresoc.v:121245$4573_Y - attribute \src "libresoc.v:121247.18-121247.110" - wire $and$libresoc.v:121247$4575_Y - attribute \src "libresoc.v:121260.18-121260.114" - wire $and$libresoc.v:121260$4588_Y - attribute \src "libresoc.v:121261.18-121261.116" - wire $and$libresoc.v:121261$4589_Y - attribute \src "libresoc.v:121263.18-121263.114" - wire $and$libresoc.v:121263$4591_Y - attribute \src "libresoc.v:121265.18-121265.110" - wire $and$libresoc.v:121265$4593_Y - attribute \src "libresoc.v:121266.17-121266.112" - wire $and$libresoc.v:121266$4594_Y - attribute \src "libresoc.v:121267.17-121267.114" - wire $and$libresoc.v:121267$4595_Y - attribute \src "libresoc.v:121248.18-121248.126" - wire $eq$libresoc.v:121248$4576_Y - attribute \src "libresoc.v:121249.18-121249.126" - wire $eq$libresoc.v:121249$4577_Y - attribute \src "libresoc.v:121251.18-121251.110" - wire $eq$libresoc.v:121251$4579_Y - attribute \src "libresoc.v:121252.18-121252.110" - wire $eq$libresoc.v:121252$4580_Y - attribute \src "libresoc.v:121254.18-121254.112" - wire $eq$libresoc.v:121254$4582_Y - attribute \src "libresoc.v:121255.17-121255.130" - wire $eq$libresoc.v:121255$4583_Y - attribute \src "libresoc.v:121257.18-121257.110" - wire $eq$libresoc.v:121257$4585_Y - attribute \src "libresoc.v:121259.18-121259.131" - wire $eq$libresoc.v:121259$4587_Y - attribute \src "libresoc.v:121262.18-121262.131" - wire $eq$libresoc.v:121262$4590_Y - attribute \src "libresoc.v:121268.17-121268.130" - wire $eq$libresoc.v:121268$4596_Y - attribute \src "libresoc.v:121246.18-121246.110" - wire $not$libresoc.v:121246$4574_Y - attribute \src "libresoc.v:121264.18-121264.110" - wire $not$libresoc.v:121264$4592_Y - attribute \src "libresoc.v:121250.18-121250.110" - wire $or$libresoc.v:121250$4578_Y - attribute \src "libresoc.v:121253.18-121253.110" - wire $or$libresoc.v:121253$4581_Y - attribute \src "libresoc.v:121256.18-121256.110" - wire $or$libresoc.v:121256$4584_Y - attribute \src "libresoc.v:121258.18-121258.110" - wire $or$libresoc.v:121258$4586_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:122852.18-122852.113" + wire $and$libresoc.v:122852$4614_Y + attribute \src "libresoc.v:122854.18-122854.110" + wire $and$libresoc.v:122854$4616_Y + attribute \src "libresoc.v:122867.18-122867.114" + wire $and$libresoc.v:122867$4629_Y + attribute \src "libresoc.v:122868.18-122868.116" + wire $and$libresoc.v:122868$4630_Y + attribute \src "libresoc.v:122870.18-122870.114" + wire $and$libresoc.v:122870$4632_Y + attribute \src "libresoc.v:122872.18-122872.110" + wire $and$libresoc.v:122872$4634_Y + attribute \src "libresoc.v:122873.17-122873.112" + wire $and$libresoc.v:122873$4635_Y + attribute \src "libresoc.v:122874.17-122874.114" + wire $and$libresoc.v:122874$4636_Y + attribute \src "libresoc.v:122855.18-122855.126" + wire $eq$libresoc.v:122855$4617_Y + attribute \src "libresoc.v:122856.18-122856.126" + wire $eq$libresoc.v:122856$4618_Y + attribute \src "libresoc.v:122858.18-122858.110" + wire $eq$libresoc.v:122858$4620_Y + attribute \src "libresoc.v:122859.18-122859.110" + wire $eq$libresoc.v:122859$4621_Y + attribute \src "libresoc.v:122861.18-122861.112" + wire $eq$libresoc.v:122861$4623_Y + attribute \src "libresoc.v:122862.17-122862.130" + wire $eq$libresoc.v:122862$4624_Y + attribute \src "libresoc.v:122864.18-122864.110" + wire $eq$libresoc.v:122864$4626_Y + attribute \src "libresoc.v:122866.18-122866.131" + wire $eq$libresoc.v:122866$4628_Y + attribute \src "libresoc.v:122869.18-122869.131" + wire $eq$libresoc.v:122869$4631_Y + attribute \src "libresoc.v:122875.17-122875.130" + wire $eq$libresoc.v:122875$4637_Y + attribute \src "libresoc.v:122853.18-122853.110" + wire $not$libresoc.v:122853$4615_Y + attribute \src "libresoc.v:122871.18-122871.110" + wire $not$libresoc.v:122871$4633_Y + attribute \src "libresoc.v:122857.18-122857.110" + wire $or$libresoc.v:122857$4619_Y + attribute \src "libresoc.v:122860.18-122860.110" + wire $or$libresoc.v:122860$4622_Y + attribute \src "libresoc.v:122863.18-122863.110" + wire $or$libresoc.v:122863$4625_Y + attribute \src "libresoc.v:122865.18-122865.110" + wire $or$libresoc.v:122865$4627_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \DIV__data_len @@ -188773,27 +191193,27 @@ module \dec_DIV wire output 15 \DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -188802,15 +191222,15 @@ module \dec_DIV attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188827,7 +191247,7 @@ module \dec_DIV attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188835,7 +191255,7 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -188852,7 +191272,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -188929,13 +191349,13 @@ module \dec_DIV attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -188943,19 +191363,19 @@ module \dec_DIV attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188963,9 +191383,9 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -188986,7 +191406,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -188996,9 +191416,9 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -189008,26 +191428,26 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120812.7-120812.15" + attribute \src "libresoc.v:122419.7-122419.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121245$4573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122852$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189035,10 +191455,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121245$4573_Y + connect \Y $and$libresoc.v:122852$4614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121247$4575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122854$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189046,10 +191466,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121247$4575_Y + connect \Y $and$libresoc.v:122854$4616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121260$4588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122867$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189057,10 +191477,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121260$4588_Y + connect \Y $and$libresoc.v:122867$4629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121261$4589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122868$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189068,10 +191488,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121261$4589_Y + connect \Y $and$libresoc.v:122868$4630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121263$4591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122870$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189079,10 +191499,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121263$4591_Y + connect \Y $and$libresoc.v:122870$4632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121265$4593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122872$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189090,10 +191510,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121265$4593_Y + connect \Y $and$libresoc.v:122872$4634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121266$4594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122873$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189101,10 +191521,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121266$4594_Y + connect \Y $and$libresoc.v:122873$4635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121267$4595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122874$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189112,10 +191532,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121267$4595_Y + connect \Y $and$libresoc.v:122874$4636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121248$4576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122855$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189123,10 +191543,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121248$4576_Y + connect \Y $eq$libresoc.v:122855$4617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121249$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:122856$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189134,10 +191554,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121249$4577_Y + connect \Y $eq$libresoc.v:122856$4618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121251$4579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122858$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189145,10 +191565,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121251$4579_Y + connect \Y $eq$libresoc.v:122858$4620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121252$4580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122859$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189156,10 +191576,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121252$4580_Y + connect \Y $eq$libresoc.v:122859$4621_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121254$4582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122861$4623 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189167,10 +191587,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121254$4582_Y + connect \Y $eq$libresoc.v:122861$4623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121255$4583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122862$4624 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189178,10 +191598,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121255$4583_Y + connect \Y $eq$libresoc.v:122862$4624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121257$4585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:122864$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189189,10 +191609,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121257$4585_Y + connect \Y $eq$libresoc.v:122864$4626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121259$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122866$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189200,10 +191620,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121259$4587_Y + connect \Y $eq$libresoc.v:122866$4628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121262$4590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122869$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189211,10 +191631,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121262$4590_Y + connect \Y $eq$libresoc.v:122869$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121268$4596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122875$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189222,26 +191642,26 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121268$4596_Y + connect \Y $eq$libresoc.v:122875$4637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121246$4574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122853$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121246$4574_Y + connect \Y $not$libresoc.v:122853$4615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121264$4592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122871$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121264$4592_Y + connect \Y $not$libresoc.v:122871$4633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:121250$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:122857$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189249,10 +191669,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121250$4578_Y + connect \Y $or$libresoc.v:122857$4619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121253$4581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122860$4622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189260,10 +191680,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121253$4581_Y + connect \Y $or$libresoc.v:122860$4622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121256$4584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122863$4625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189271,10 +191691,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121256$4584_Y + connect \Y $or$libresoc.v:122863$4625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121258$4586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:122865$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189282,10 +191702,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121258$4586_Y + connect \Y $or$libresoc.v:122865$4627_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121269.13-121297.4" + attribute \src "libresoc.v:122876.13-122904.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -189316,7 +191736,7 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121298.16-121303.4" + attribute \src "libresoc.v:122905.16-122910.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out @@ -189324,7 +191744,7 @@ module \dec_DIV connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121304.16-121315.4" + attribute \src "libresoc.v:122911.16-122922.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -189338,7 +191758,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121316.16-121322.4" + attribute \src "libresoc.v:122923.16-122929.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -189347,33 +191767,33 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121323.16-121328.4" + attribute \src "libresoc.v:122930.16-122935.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120812.7-120812.20" - process $proc$libresoc.v:120812$4600 + attribute \src "libresoc.v:122419.7-122419.20" + process $proc$libresoc.v:122419$4641 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121329.3-121343.6" - process $proc$libresoc.v:121329$4597 + attribute \src "libresoc.v:122936.3-122950.6" + process $proc$libresoc.v:122936$4638 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:121330.5-121330.29" + attribute \src "libresoc.v:122937.5-122937.29" switch \initial - attribute \src "libresoc.v:121330.9-121330.17" + attribute \src "libresoc.v:122937.9-122937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -189389,18 +191809,18 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:121344.3-121356.6" - process $proc$libresoc.v:121344$4598 + attribute \src "libresoc.v:122951.3-122963.6" + process $proc$libresoc.v:122951$4639 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:121345.5-121345.29" + attribute \src "libresoc.v:122952.5-122952.29" switch \initial - attribute \src "libresoc.v:121345.9-121345.17" + attribute \src "libresoc.v:122952.9-122952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189416,17 +191836,17 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:121357.3-121371.6" - process $proc$libresoc.v:121357$4599 + attribute \src "libresoc.v:122964.3-122978.6" + process $proc$libresoc.v:122964$4640 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121358.5-121358.29" + attribute \src "libresoc.v:122965.5-122965.29" switch \initial - attribute \src "libresoc.v:121358.9-121358.17" + attribute \src "libresoc.v:122965.9-122965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189444,30 +191864,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121245$4573_Y - connect \$12 $not$libresoc.v:121246$4574_Y - connect \$14 $and$libresoc.v:121247$4575_Y - connect \$16 $eq$libresoc.v:121248$4576_Y - connect \$18 $eq$libresoc.v:121249$4577_Y - connect \$20 $or$libresoc.v:121250$4578_Y - connect \$22 $eq$libresoc.v:121251$4579_Y - connect \$24 $eq$libresoc.v:121252$4580_Y - connect \$26 $or$libresoc.v:121253$4581_Y - connect \$28 $eq$libresoc.v:121254$4582_Y - connect \$2 $eq$libresoc.v:121255$4583_Y - connect \$30 $or$libresoc.v:121256$4584_Y - connect \$32 $eq$libresoc.v:121257$4585_Y - connect \$34 $or$libresoc.v:121258$4586_Y - connect \$36 $eq$libresoc.v:121259$4587_Y - connect \$38 $and$libresoc.v:121260$4588_Y - connect \$40 $and$libresoc.v:121261$4589_Y - connect \$42 $eq$libresoc.v:121262$4590_Y - connect \$44 $and$libresoc.v:121263$4591_Y - connect \$46 $not$libresoc.v:121264$4592_Y - connect \$48 $and$libresoc.v:121265$4593_Y - connect \$4 $and$libresoc.v:121266$4594_Y - connect \$6 $and$libresoc.v:121267$4595_Y - connect \$8 $eq$libresoc.v:121268$4596_Y + connect \$10 $and$libresoc.v:122852$4614_Y + connect \$12 $not$libresoc.v:122853$4615_Y + connect \$14 $and$libresoc.v:122854$4616_Y + connect \$16 $eq$libresoc.v:122855$4617_Y + connect \$18 $eq$libresoc.v:122856$4618_Y + connect \$20 $or$libresoc.v:122857$4619_Y + connect \$22 $eq$libresoc.v:122858$4620_Y + connect \$24 $eq$libresoc.v:122859$4621_Y + connect \$26 $or$libresoc.v:122860$4622_Y + connect \$28 $eq$libresoc.v:122861$4623_Y + connect \$2 $eq$libresoc.v:122862$4624_Y + connect \$30 $or$libresoc.v:122863$4625_Y + connect \$32 $eq$libresoc.v:122864$4626_Y + connect \$34 $or$libresoc.v:122865$4627_Y + connect \$36 $eq$libresoc.v:122866$4628_Y + connect \$38 $and$libresoc.v:122867$4629_Y + connect \$40 $and$libresoc.v:122868$4630_Y + connect \$42 $eq$libresoc.v:122869$4631_Y + connect \$44 $and$libresoc.v:122870$4632_Y + connect \$46 $not$libresoc.v:122871$4633_Y + connect \$48 $and$libresoc.v:122872$4634_Y + connect \$4 $and$libresoc.v:122873$4635_Y + connect \$6 $and$libresoc.v:122874$4636_Y + connect \$8 $eq$libresoc.v:122875$4637_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -189491,116 +191911,116 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:121398.1-121959.10" +attribute \src "libresoc.v:123005.1-123566.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:121923.3-121937.6" + attribute \src "libresoc.v:123530.3-123544.6" wire width 14 $0\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121910.3-121922.6" + attribute \src "libresoc.v:123517.3-123529.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:121399.7-121399.20" + attribute \src "libresoc.v:123006.7-123006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121923.3-121937.6" + attribute \src "libresoc.v:123530.3-123544.6" wire width 14 $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121910.3-121922.6" + attribute \src "libresoc.v:123517.3-123529.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:121827.18-121827.113" - wire $and$libresoc.v:121827$4601_Y - attribute \src "libresoc.v:121829.18-121829.110" - wire $and$libresoc.v:121829$4603_Y - attribute \src "libresoc.v:121842.18-121842.114" - wire $and$libresoc.v:121842$4616_Y - attribute \src "libresoc.v:121843.18-121843.116" - wire $and$libresoc.v:121843$4617_Y - attribute \src "libresoc.v:121845.18-121845.114" - wire $and$libresoc.v:121845$4619_Y - attribute \src "libresoc.v:121847.18-121847.110" - wire $and$libresoc.v:121847$4621_Y - attribute \src "libresoc.v:121848.17-121848.112" - wire $and$libresoc.v:121848$4622_Y - attribute \src "libresoc.v:121849.17-121849.114" - wire $and$libresoc.v:121849$4623_Y - attribute \src "libresoc.v:121830.18-121830.127" - wire $eq$libresoc.v:121830$4604_Y - attribute \src "libresoc.v:121831.18-121831.127" - wire $eq$libresoc.v:121831$4605_Y - attribute \src "libresoc.v:121833.18-121833.110" - wire $eq$libresoc.v:121833$4607_Y - attribute \src "libresoc.v:121834.18-121834.110" - wire $eq$libresoc.v:121834$4608_Y - attribute \src "libresoc.v:121836.18-121836.112" - wire $eq$libresoc.v:121836$4610_Y - attribute \src "libresoc.v:121837.17-121837.131" - wire $eq$libresoc.v:121837$4611_Y - attribute \src "libresoc.v:121839.18-121839.110" - wire $eq$libresoc.v:121839$4613_Y - attribute \src "libresoc.v:121841.18-121841.132" - wire $eq$libresoc.v:121841$4615_Y - attribute \src "libresoc.v:121844.18-121844.132" - wire $eq$libresoc.v:121844$4618_Y - attribute \src "libresoc.v:121850.17-121850.131" - wire $eq$libresoc.v:121850$4624_Y - attribute \src "libresoc.v:121828.18-121828.110" - wire $not$libresoc.v:121828$4602_Y - attribute \src "libresoc.v:121846.18-121846.110" - wire $not$libresoc.v:121846$4620_Y - attribute \src "libresoc.v:121832.18-121832.110" - wire $or$libresoc.v:121832$4606_Y - attribute \src "libresoc.v:121835.18-121835.110" - wire $or$libresoc.v:121835$4609_Y - attribute \src "libresoc.v:121838.18-121838.110" - wire $or$libresoc.v:121838$4612_Y - attribute \src "libresoc.v:121840.18-121840.110" - wire $or$libresoc.v:121840$4614_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:123434.18-123434.113" + wire $and$libresoc.v:123434$4642_Y + attribute \src "libresoc.v:123436.18-123436.110" + wire $and$libresoc.v:123436$4644_Y + attribute \src "libresoc.v:123449.18-123449.114" + wire $and$libresoc.v:123449$4657_Y + attribute \src "libresoc.v:123450.18-123450.116" + wire $and$libresoc.v:123450$4658_Y + attribute \src "libresoc.v:123452.18-123452.114" + wire $and$libresoc.v:123452$4660_Y + attribute \src "libresoc.v:123454.18-123454.110" + wire $and$libresoc.v:123454$4662_Y + attribute \src "libresoc.v:123455.17-123455.112" + wire $and$libresoc.v:123455$4663_Y + attribute \src "libresoc.v:123456.17-123456.114" + wire $and$libresoc.v:123456$4664_Y + attribute \src "libresoc.v:123437.18-123437.127" + wire $eq$libresoc.v:123437$4645_Y + attribute \src "libresoc.v:123438.18-123438.127" + wire $eq$libresoc.v:123438$4646_Y + attribute \src "libresoc.v:123440.18-123440.110" + wire $eq$libresoc.v:123440$4648_Y + attribute \src "libresoc.v:123441.18-123441.110" + wire $eq$libresoc.v:123441$4649_Y + attribute \src "libresoc.v:123443.18-123443.112" + wire $eq$libresoc.v:123443$4651_Y + attribute \src "libresoc.v:123444.17-123444.131" + wire $eq$libresoc.v:123444$4652_Y + attribute \src "libresoc.v:123446.18-123446.110" + wire $eq$libresoc.v:123446$4654_Y + attribute \src "libresoc.v:123448.18-123448.132" + wire $eq$libresoc.v:123448$4656_Y + attribute \src "libresoc.v:123451.18-123451.132" + wire $eq$libresoc.v:123451$4659_Y + attribute \src "libresoc.v:123457.17-123457.131" + wire $eq$libresoc.v:123457$4665_Y + attribute \src "libresoc.v:123435.18-123435.110" + wire $not$libresoc.v:123435$4643_Y + attribute \src "libresoc.v:123453.18-123453.110" + wire $not$libresoc.v:123453$4661_Y + attribute \src "libresoc.v:123439.18-123439.110" + wire $or$libresoc.v:123439$4647_Y + attribute \src "libresoc.v:123442.18-123442.110" + wire $or$libresoc.v:123442$4650_Y + attribute \src "libresoc.v:123445.18-123445.110" + wire $or$libresoc.v:123445$4653_Y + attribute \src "libresoc.v:123447.18-123447.110" + wire $or$libresoc.v:123447$4655_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \LDST__byte_reverse @@ -189729,29 +192149,29 @@ module \dec_LDST wire output 16 \LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_br attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -189760,7 +192180,7 @@ module \dec_LDST attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -189777,7 +192197,7 @@ module \dec_LDST attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -189785,7 +192205,7 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -189802,7 +192222,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -189879,9 +192299,9 @@ module \dec_LDST attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -189889,28 +192309,28 @@ module \dec_LDST attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -189918,9 +192338,9 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -189941,7 +192361,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -189951,9 +192371,9 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -189963,26 +192383,26 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121399.7-121399.15" + attribute \src "libresoc.v:123006.7-123006.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121827$4601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123434$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189990,10 +192410,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121827$4601_Y + connect \Y $and$libresoc.v:123434$4642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121829$4603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123436$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190001,10 +192421,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121829$4603_Y + connect \Y $and$libresoc.v:123436$4644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121842$4616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123449$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190012,10 +192432,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121842$4616_Y + connect \Y $and$libresoc.v:123449$4657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121843$4617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123450$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190023,10 +192443,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121843$4617_Y + connect \Y $and$libresoc.v:123450$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121845$4619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123452$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190034,10 +192454,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121845$4619_Y + connect \Y $and$libresoc.v:123452$4660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121847$4621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123454$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190045,10 +192465,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121847$4621_Y + connect \Y $and$libresoc.v:123454$4662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121848$4622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123455$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190056,10 +192476,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121848$4622_Y + connect \Y $and$libresoc.v:123455$4663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121849$4623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123456$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190067,10 +192487,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121849$4623_Y + connect \Y $and$libresoc.v:123456$4664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121830$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123437$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190078,10 +192498,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121830$4604_Y + connect \Y $eq$libresoc.v:123437$4645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121831$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:123438$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190089,10 +192509,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121831$4605_Y + connect \Y $eq$libresoc.v:123438$4646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121833$4607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123440$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190100,10 +192520,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121833$4607_Y + connect \Y $eq$libresoc.v:123440$4648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121834$4608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123441$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190111,10 +192531,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121834$4608_Y + connect \Y $eq$libresoc.v:123441$4649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121836$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123443$4651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190122,10 +192542,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121836$4610_Y + connect \Y $eq$libresoc.v:123443$4651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121837$4611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123444$4652 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190133,10 +192553,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121837$4611_Y + connect \Y $eq$libresoc.v:123444$4652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121839$4613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:123446$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190144,10 +192564,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121839$4613_Y + connect \Y $eq$libresoc.v:123446$4654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121841$4615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123448$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190155,10 +192575,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121841$4615_Y + connect \Y $eq$libresoc.v:123448$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121844$4618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123451$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190166,10 +192586,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121844$4618_Y + connect \Y $eq$libresoc.v:123451$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121850$4624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123457$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190177,26 +192597,26 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121850$4624_Y + connect \Y $eq$libresoc.v:123457$4665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121828$4602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123435$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121828$4602_Y + connect \Y $not$libresoc.v:123435$4643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121846$4620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123453$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121846$4620_Y + connect \Y $not$libresoc.v:123453$4661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:121832$4606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:123439$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190204,10 +192624,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121832$4606_Y + connect \Y $or$libresoc.v:123439$4647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121835$4609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123442$4650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190215,10 +192635,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121835$4609_Y + connect \Y $or$libresoc.v:123442$4650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121838$4612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123445$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190226,10 +192646,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121838$4612_Y + connect \Y $or$libresoc.v:123445$4653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121840$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:123447$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190237,10 +192657,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121840$4614_Y + connect \Y $or$libresoc.v:123447$4655_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121851.13-121878.4" + attribute \src "libresoc.v:123458.13-123485.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -190270,7 +192690,7 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121879.16-121884.4" + attribute \src "libresoc.v:123486.16-123491.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out @@ -190278,7 +192698,7 @@ module \dec_LDST connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121885.16-121896.4" + attribute \src "libresoc.v:123492.16-123503.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -190292,7 +192712,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121897.16-121903.4" + attribute \src "libresoc.v:123504.16-123510.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -190301,33 +192721,33 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121904.16-121909.4" + attribute \src "libresoc.v:123511.16-123516.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121399.7-121399.20" - process $proc$libresoc.v:121399$4627 + attribute \src "libresoc.v:123006.7-123006.20" + process $proc$libresoc.v:123006$4668 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121910.3-121922.6" - process $proc$libresoc.v:121910$4625 + attribute \src "libresoc.v:123517.3-123529.6" + process $proc$libresoc.v:123517$4666 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:121911.5-121911.29" + attribute \src "libresoc.v:123518.5-123518.29" switch \initial - attribute \src "libresoc.v:121911.9-121911.17" + attribute \src "libresoc.v:123518.9-123518.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190343,17 +192763,17 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:121923.3-121937.6" - process $proc$libresoc.v:121923$4626 + attribute \src "libresoc.v:123530.3-123544.6" + process $proc$libresoc.v:123530$4667 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121924.5-121924.29" + attribute \src "libresoc.v:123531.5-123531.29" switch \initial - attribute \src "libresoc.v:121924.9-121924.17" + attribute \src "libresoc.v:123531.9-123531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190371,30 +192791,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121827$4601_Y - connect \$12 $not$libresoc.v:121828$4602_Y - connect \$14 $and$libresoc.v:121829$4603_Y - connect \$16 $eq$libresoc.v:121830$4604_Y - connect \$18 $eq$libresoc.v:121831$4605_Y - connect \$20 $or$libresoc.v:121832$4606_Y - connect \$22 $eq$libresoc.v:121833$4607_Y - connect \$24 $eq$libresoc.v:121834$4608_Y - connect \$26 $or$libresoc.v:121835$4609_Y - connect \$28 $eq$libresoc.v:121836$4610_Y - connect \$2 $eq$libresoc.v:121837$4611_Y - connect \$30 $or$libresoc.v:121838$4612_Y - connect \$32 $eq$libresoc.v:121839$4613_Y - connect \$34 $or$libresoc.v:121840$4614_Y - connect \$36 $eq$libresoc.v:121841$4615_Y - connect \$38 $and$libresoc.v:121842$4616_Y - connect \$40 $and$libresoc.v:121843$4617_Y - connect \$42 $eq$libresoc.v:121844$4618_Y - connect \$44 $and$libresoc.v:121845$4619_Y - connect \$46 $not$libresoc.v:121846$4620_Y - connect \$48 $and$libresoc.v:121847$4621_Y - connect \$4 $and$libresoc.v:121848$4622_Y - connect \$6 $and$libresoc.v:121849$4623_Y - connect \$8 $eq$libresoc.v:121850$4624_Y + connect \$10 $and$libresoc.v:123434$4642_Y + connect \$12 $not$libresoc.v:123435$4643_Y + connect \$14 $and$libresoc.v:123436$4644_Y + connect \$16 $eq$libresoc.v:123437$4645_Y + connect \$18 $eq$libresoc.v:123438$4646_Y + connect \$20 $or$libresoc.v:123439$4647_Y + connect \$22 $eq$libresoc.v:123440$4648_Y + connect \$24 $eq$libresoc.v:123441$4649_Y + connect \$26 $or$libresoc.v:123442$4650_Y + connect \$28 $eq$libresoc.v:123443$4651_Y + connect \$2 $eq$libresoc.v:123444$4652_Y + connect \$30 $or$libresoc.v:123445$4653_Y + connect \$32 $eq$libresoc.v:123446$4654_Y + connect \$34 $or$libresoc.v:123447$4655_Y + connect \$36 $eq$libresoc.v:123448$4656_Y + connect \$38 $and$libresoc.v:123449$4657_Y + connect \$40 $and$libresoc.v:123450$4658_Y + connect \$42 $eq$libresoc.v:123451$4659_Y + connect \$44 $and$libresoc.v:123452$4660_Y + connect \$46 $not$libresoc.v:123453$4661_Y + connect \$48 $and$libresoc.v:123454$4662_Y + connect \$4 $and$libresoc.v:123455$4663_Y + connect \$6 $and$libresoc.v:123456$4664_Y + connect \$8 $eq$libresoc.v:123457$4665_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -190417,120 +192837,120 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:121963.1-122546.10" +attribute \src "libresoc.v:123570.1-124153.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:122509.3-122523.6" + attribute \src "libresoc.v:124116.3-124130.6" wire width 14 $0\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122496.3-122508.6" + attribute \src "libresoc.v:124103.3-124115.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122481.3-122495.6" + attribute \src "libresoc.v:124088.3-124102.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:121964.7-121964.20" + attribute \src "libresoc.v:123571.7-123571.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122509.3-122523.6" + attribute \src "libresoc.v:124116.3-124130.6" wire width 14 $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122496.3-122508.6" + attribute \src "libresoc.v:124103.3-124115.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122481.3-122495.6" + attribute \src "libresoc.v:124088.3-124102.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:122397.18-122397.113" - wire $and$libresoc.v:122397$4628_Y - attribute \src "libresoc.v:122399.18-122399.110" - wire $and$libresoc.v:122399$4630_Y - attribute \src "libresoc.v:122412.18-122412.114" - wire $and$libresoc.v:122412$4643_Y - attribute \src "libresoc.v:122413.18-122413.116" - wire $and$libresoc.v:122413$4644_Y - attribute \src "libresoc.v:122415.18-122415.114" - wire $and$libresoc.v:122415$4646_Y - attribute \src "libresoc.v:122417.18-122417.110" - wire $and$libresoc.v:122417$4648_Y - attribute \src "libresoc.v:122418.17-122418.112" - wire $and$libresoc.v:122418$4649_Y - attribute \src "libresoc.v:122419.17-122419.114" - wire $and$libresoc.v:122419$4650_Y - attribute \src "libresoc.v:122400.18-122400.130" - wire $eq$libresoc.v:122400$4631_Y - attribute \src "libresoc.v:122401.18-122401.130" - wire $eq$libresoc.v:122401$4632_Y - attribute \src "libresoc.v:122403.18-122403.110" - wire $eq$libresoc.v:122403$4634_Y - attribute \src "libresoc.v:122404.18-122404.110" - wire $eq$libresoc.v:122404$4635_Y - attribute \src "libresoc.v:122406.18-122406.112" - wire $eq$libresoc.v:122406$4637_Y - attribute \src "libresoc.v:122407.17-122407.134" - wire $eq$libresoc.v:122407$4638_Y - attribute \src "libresoc.v:122409.18-122409.110" - wire $eq$libresoc.v:122409$4640_Y - attribute \src "libresoc.v:122411.18-122411.135" - wire $eq$libresoc.v:122411$4642_Y - attribute \src "libresoc.v:122414.18-122414.135" - wire $eq$libresoc.v:122414$4645_Y - attribute \src "libresoc.v:122420.17-122420.134" - wire $eq$libresoc.v:122420$4651_Y - attribute \src "libresoc.v:122398.18-122398.110" - wire $not$libresoc.v:122398$4629_Y - attribute \src "libresoc.v:122416.18-122416.110" - wire $not$libresoc.v:122416$4647_Y - attribute \src "libresoc.v:122402.18-122402.110" - wire $or$libresoc.v:122402$4633_Y - attribute \src "libresoc.v:122405.18-122405.110" - wire $or$libresoc.v:122405$4636_Y - attribute \src "libresoc.v:122408.18-122408.110" - wire $or$libresoc.v:122408$4639_Y - attribute \src "libresoc.v:122410.18-122410.110" - wire $or$libresoc.v:122410$4641_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:124004.18-124004.113" + wire $and$libresoc.v:124004$4669_Y + attribute \src "libresoc.v:124006.18-124006.110" + wire $and$libresoc.v:124006$4671_Y + attribute \src "libresoc.v:124019.18-124019.114" + wire $and$libresoc.v:124019$4684_Y + attribute \src "libresoc.v:124020.18-124020.116" + wire $and$libresoc.v:124020$4685_Y + attribute \src "libresoc.v:124022.18-124022.114" + wire $and$libresoc.v:124022$4687_Y + attribute \src "libresoc.v:124024.18-124024.110" + wire $and$libresoc.v:124024$4689_Y + attribute \src "libresoc.v:124025.17-124025.112" + wire $and$libresoc.v:124025$4690_Y + attribute \src "libresoc.v:124026.17-124026.114" + wire $and$libresoc.v:124026$4691_Y + attribute \src "libresoc.v:124007.18-124007.130" + wire $eq$libresoc.v:124007$4672_Y + attribute \src "libresoc.v:124008.18-124008.130" + wire $eq$libresoc.v:124008$4673_Y + attribute \src "libresoc.v:124010.18-124010.110" + wire $eq$libresoc.v:124010$4675_Y + attribute \src "libresoc.v:124011.18-124011.110" + wire $eq$libresoc.v:124011$4676_Y + attribute \src "libresoc.v:124013.18-124013.112" + wire $eq$libresoc.v:124013$4678_Y + attribute \src "libresoc.v:124014.17-124014.134" + wire $eq$libresoc.v:124014$4679_Y + attribute \src "libresoc.v:124016.18-124016.110" + wire $eq$libresoc.v:124016$4681_Y + attribute \src "libresoc.v:124018.18-124018.135" + wire $eq$libresoc.v:124018$4683_Y + attribute \src "libresoc.v:124021.18-124021.135" + wire $eq$libresoc.v:124021$4686_Y + attribute \src "libresoc.v:124027.17-124027.134" + wire $eq$libresoc.v:124027$4692_Y + attribute \src "libresoc.v:124005.18-124005.110" + wire $not$libresoc.v:124005$4670_Y + attribute \src "libresoc.v:124023.18-124023.110" + wire $not$libresoc.v:124023$4688_Y + attribute \src "libresoc.v:124009.18-124009.110" + wire $or$libresoc.v:124009$4674_Y + attribute \src "libresoc.v:124012.18-124012.110" + wire $or$libresoc.v:124012$4677_Y + attribute \src "libresoc.v:124015.18-124015.110" + wire $or$libresoc.v:124015$4680_Y + attribute \src "libresoc.v:124017.18-124017.110" + wire $or$libresoc.v:124017$4682_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \LOGICAL__data_len @@ -190662,27 +193082,27 @@ module \dec_LOGICAL wire output 15 \LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -190691,15 +193111,15 @@ module \dec_LOGICAL attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -190716,7 +193136,7 @@ module \dec_LOGICAL attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -190724,7 +193144,7 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -190741,7 +193161,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -190818,13 +193238,13 @@ module \dec_LOGICAL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -190832,19 +193252,19 @@ module \dec_LOGICAL attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -190852,9 +193272,9 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -190875,7 +193295,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -190885,9 +193305,9 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -190897,26 +193317,26 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121964.7-121964.15" + attribute \src "libresoc.v:123571.7-123571.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122397$4628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124004$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190924,10 +193344,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122397$4628_Y + connect \Y $and$libresoc.v:124004$4669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122399$4630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124006$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190935,10 +193355,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122399$4630_Y + connect \Y $and$libresoc.v:124006$4671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122412$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124019$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190946,10 +193366,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122412$4643_Y + connect \Y $and$libresoc.v:124019$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122413$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124020$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190957,10 +193377,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122413$4644_Y + connect \Y $and$libresoc.v:124020$4685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122415$4646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124022$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190968,10 +193388,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122415$4646_Y + connect \Y $and$libresoc.v:124022$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122417$4648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124024$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190979,10 +193399,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122417$4648_Y + connect \Y $and$libresoc.v:124024$4689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122418$4649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124025$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190990,10 +193410,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122418$4649_Y + connect \Y $and$libresoc.v:124025$4690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122419$4650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124026$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191001,10 +193421,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122419$4650_Y + connect \Y $and$libresoc.v:124026$4691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:122400$4631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124007$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191012,10 +193432,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122400$4631_Y + connect \Y $eq$libresoc.v:124007$4672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122401$4632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124008$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191023,10 +193443,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122401$4632_Y + connect \Y $eq$libresoc.v:124008$4673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122403$4634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124010$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191034,10 +193454,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122403$4634_Y + connect \Y $eq$libresoc.v:124010$4675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122404$4635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124011$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191045,10 +193465,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122404$4635_Y + connect \Y $eq$libresoc.v:124011$4676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122406$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124013$4678 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191056,10 +193476,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122406$4637_Y + connect \Y $eq$libresoc.v:124013$4678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122407$4638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124014$4679 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191067,10 +193487,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122407$4638_Y + connect \Y $eq$libresoc.v:124014$4679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122409$4640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124016$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191078,10 +193498,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122409$4640_Y + connect \Y $eq$libresoc.v:124016$4681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122411$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124018$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191089,10 +193509,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122411$4642_Y + connect \Y $eq$libresoc.v:124018$4683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122414$4645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124021$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191100,10 +193520,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122414$4645_Y + connect \Y $eq$libresoc.v:124021$4686_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122420$4651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124027$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191111,26 +193531,26 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122420$4651_Y + connect \Y $eq$libresoc.v:124027$4692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122398$4629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124005$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122398$4629_Y + connect \Y $not$libresoc.v:124005$4670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122416$4647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124023$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122416$4647_Y + connect \Y $not$libresoc.v:124023$4688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:122402$4633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124009$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191138,10 +193558,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122402$4633_Y + connect \Y $or$libresoc.v:124009$4674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122405$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124012$4677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191149,10 +193569,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122405$4636_Y + connect \Y $or$libresoc.v:124012$4677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122408$4639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124015$4680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191160,10 +193580,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122408$4639_Y + connect \Y $or$libresoc.v:124015$4680_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122410$4641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124017$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191171,10 +193591,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122410$4641_Y + connect \Y $or$libresoc.v:124017$4682_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122421.13-122449.4" + attribute \src "libresoc.v:124028.13-124056.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -191205,7 +193625,7 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122450.16-122455.4" + attribute \src "libresoc.v:124057.16-124062.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out @@ -191213,7 +193633,7 @@ module \dec_LOGICAL connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:122456.16-122467.4" + attribute \src "libresoc.v:124063.16-124074.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -191227,7 +193647,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122468.16-122474.4" + attribute \src "libresoc.v:124075.16-124081.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -191236,33 +193656,33 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122475.16-122480.4" + attribute \src "libresoc.v:124082.16-124087.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121964.7-121964.20" - process $proc$libresoc.v:121964$4655 + attribute \src "libresoc.v:123571.7-123571.20" + process $proc$libresoc.v:123571$4696 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122481.3-122495.6" - process $proc$libresoc.v:122481$4652 + attribute \src "libresoc.v:124088.3-124102.6" + process $proc$libresoc.v:124088$4693 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:122482.5-122482.29" + attribute \src "libresoc.v:124089.5-124089.29" switch \initial - attribute \src "libresoc.v:122482.9-122482.17" + attribute \src "libresoc.v:124089.9-124089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -191278,18 +193698,18 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:122496.3-122508.6" - process $proc$libresoc.v:122496$4653 + attribute \src "libresoc.v:124103.3-124115.6" + process $proc$libresoc.v:124103$4694 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122497.5-122497.29" + attribute \src "libresoc.v:124104.5-124104.29" switch \initial - attribute \src "libresoc.v:122497.9-122497.17" + attribute \src "libresoc.v:124104.9-124104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191305,17 +193725,17 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:122509.3-122523.6" - process $proc$libresoc.v:122509$4654 + attribute \src "libresoc.v:124116.3-124130.6" + process $proc$libresoc.v:124116$4695 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122510.5-122510.29" + attribute \src "libresoc.v:124117.5-124117.29" switch \initial - attribute \src "libresoc.v:122510.9-122510.17" + attribute \src "libresoc.v:124117.9-124117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191333,30 +193753,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122397$4628_Y - connect \$12 $not$libresoc.v:122398$4629_Y - connect \$14 $and$libresoc.v:122399$4630_Y - connect \$16 $eq$libresoc.v:122400$4631_Y - connect \$18 $eq$libresoc.v:122401$4632_Y - connect \$20 $or$libresoc.v:122402$4633_Y - connect \$22 $eq$libresoc.v:122403$4634_Y - connect \$24 $eq$libresoc.v:122404$4635_Y - connect \$26 $or$libresoc.v:122405$4636_Y - connect \$28 $eq$libresoc.v:122406$4637_Y - connect \$2 $eq$libresoc.v:122407$4638_Y - connect \$30 $or$libresoc.v:122408$4639_Y - connect \$32 $eq$libresoc.v:122409$4640_Y - connect \$34 $or$libresoc.v:122410$4641_Y - connect \$36 $eq$libresoc.v:122411$4642_Y - connect \$38 $and$libresoc.v:122412$4643_Y - connect \$40 $and$libresoc.v:122413$4644_Y - connect \$42 $eq$libresoc.v:122414$4645_Y - connect \$44 $and$libresoc.v:122415$4646_Y - connect \$46 $not$libresoc.v:122416$4647_Y - connect \$48 $and$libresoc.v:122417$4648_Y - connect \$4 $and$libresoc.v:122418$4649_Y - connect \$6 $and$libresoc.v:122419$4650_Y - connect \$8 $eq$libresoc.v:122420$4651_Y + connect \$10 $and$libresoc.v:124004$4669_Y + connect \$12 $not$libresoc.v:124005$4670_Y + connect \$14 $and$libresoc.v:124006$4671_Y + connect \$16 $eq$libresoc.v:124007$4672_Y + connect \$18 $eq$libresoc.v:124008$4673_Y + connect \$20 $or$libresoc.v:124009$4674_Y + connect \$22 $eq$libresoc.v:124010$4675_Y + connect \$24 $eq$libresoc.v:124011$4676_Y + connect \$26 $or$libresoc.v:124012$4677_Y + connect \$28 $eq$libresoc.v:124013$4678_Y + connect \$2 $eq$libresoc.v:124014$4679_Y + connect \$30 $or$libresoc.v:124015$4680_Y + connect \$32 $eq$libresoc.v:124016$4681_Y + connect \$34 $or$libresoc.v:124017$4682_Y + connect \$36 $eq$libresoc.v:124018$4683_Y + connect \$38 $and$libresoc.v:124019$4684_Y + connect \$40 $and$libresoc.v:124020$4685_Y + connect \$42 $eq$libresoc.v:124021$4686_Y + connect \$44 $and$libresoc.v:124022$4687_Y + connect \$46 $not$libresoc.v:124023$4688_Y + connect \$48 $and$libresoc.v:124024$4689_Y + connect \$4 $and$libresoc.v:124025$4690_Y + connect \$6 $and$libresoc.v:124026$4691_Y + connect \$8 $eq$libresoc.v:124027$4692_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -191380,120 +193800,120 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:122550.1-123052.10" +attribute \src "libresoc.v:124157.1-124659.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:123023.3-123037.6" + attribute \src "libresoc.v:124630.3-124644.6" wire width 14 $0\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123010.3-123022.6" + attribute \src "libresoc.v:124617.3-124629.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:122995.3-123009.6" + attribute \src "libresoc.v:124602.3-124616.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122551.7-122551.20" + attribute \src "libresoc.v:124158.7-124158.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123023.3-123037.6" + attribute \src "libresoc.v:124630.3-124644.6" wire width 14 $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123010.3-123022.6" + attribute \src "libresoc.v:124617.3-124629.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:122995.3-123009.6" + attribute \src "libresoc.v:124602.3-124616.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122924.18-122924.113" - wire $and$libresoc.v:122924$4656_Y - attribute \src "libresoc.v:122926.18-122926.110" - wire $and$libresoc.v:122926$4658_Y - attribute \src "libresoc.v:122939.18-122939.114" - wire $and$libresoc.v:122939$4671_Y - attribute \src "libresoc.v:122940.18-122940.116" - wire $and$libresoc.v:122940$4672_Y - attribute \src "libresoc.v:122942.18-122942.114" - wire $and$libresoc.v:122942$4674_Y - attribute \src "libresoc.v:122944.18-122944.110" - wire $and$libresoc.v:122944$4676_Y - attribute \src "libresoc.v:122945.17-122945.112" - wire $and$libresoc.v:122945$4677_Y - attribute \src "libresoc.v:122946.17-122946.114" - wire $and$libresoc.v:122946$4678_Y - attribute \src "libresoc.v:122927.18-122927.126" - wire $eq$libresoc.v:122927$4659_Y - attribute \src "libresoc.v:122928.18-122928.126" - wire $eq$libresoc.v:122928$4660_Y - attribute \src "libresoc.v:122930.18-122930.110" - wire $eq$libresoc.v:122930$4662_Y - attribute \src "libresoc.v:122931.18-122931.110" - wire $eq$libresoc.v:122931$4663_Y - attribute \src "libresoc.v:122933.18-122933.112" - wire $eq$libresoc.v:122933$4665_Y - attribute \src "libresoc.v:122934.17-122934.130" - wire $eq$libresoc.v:122934$4666_Y - attribute \src "libresoc.v:122936.18-122936.110" - wire $eq$libresoc.v:122936$4668_Y - attribute \src "libresoc.v:122938.18-122938.131" - wire $eq$libresoc.v:122938$4670_Y - attribute \src "libresoc.v:122941.18-122941.131" - wire $eq$libresoc.v:122941$4673_Y - attribute \src "libresoc.v:122947.17-122947.130" - wire $eq$libresoc.v:122947$4679_Y - attribute \src "libresoc.v:122925.18-122925.110" - wire $not$libresoc.v:122925$4657_Y - attribute \src "libresoc.v:122943.18-122943.110" - wire $not$libresoc.v:122943$4675_Y - attribute \src "libresoc.v:122929.18-122929.110" - wire $or$libresoc.v:122929$4661_Y - attribute \src "libresoc.v:122932.18-122932.110" - wire $or$libresoc.v:122932$4664_Y - attribute \src "libresoc.v:122935.18-122935.110" - wire $or$libresoc.v:122935$4667_Y - attribute \src "libresoc.v:122937.18-122937.110" - wire $or$libresoc.v:122937$4669_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:124531.18-124531.113" + wire $and$libresoc.v:124531$4697_Y + attribute \src "libresoc.v:124533.18-124533.110" + wire $and$libresoc.v:124533$4699_Y + attribute \src "libresoc.v:124546.18-124546.114" + wire $and$libresoc.v:124546$4712_Y + attribute \src "libresoc.v:124547.18-124547.116" + wire $and$libresoc.v:124547$4713_Y + attribute \src "libresoc.v:124549.18-124549.114" + wire $and$libresoc.v:124549$4715_Y + attribute \src "libresoc.v:124551.18-124551.110" + wire $and$libresoc.v:124551$4717_Y + attribute \src "libresoc.v:124552.17-124552.112" + wire $and$libresoc.v:124552$4718_Y + attribute \src "libresoc.v:124553.17-124553.114" + wire $and$libresoc.v:124553$4719_Y + attribute \src "libresoc.v:124534.18-124534.126" + wire $eq$libresoc.v:124534$4700_Y + attribute \src "libresoc.v:124535.18-124535.126" + wire $eq$libresoc.v:124535$4701_Y + attribute \src "libresoc.v:124537.18-124537.110" + wire $eq$libresoc.v:124537$4703_Y + attribute \src "libresoc.v:124538.18-124538.110" + wire $eq$libresoc.v:124538$4704_Y + attribute \src "libresoc.v:124540.18-124540.112" + wire $eq$libresoc.v:124540$4706_Y + attribute \src "libresoc.v:124541.17-124541.130" + wire $eq$libresoc.v:124541$4707_Y + attribute \src "libresoc.v:124543.18-124543.110" + wire $eq$libresoc.v:124543$4709_Y + attribute \src "libresoc.v:124545.18-124545.131" + wire $eq$libresoc.v:124545$4711_Y + attribute \src "libresoc.v:124548.18-124548.131" + wire $eq$libresoc.v:124548$4714_Y + attribute \src "libresoc.v:124554.17-124554.130" + wire $eq$libresoc.v:124554$4720_Y + attribute \src "libresoc.v:124532.18-124532.110" + wire $not$libresoc.v:124532$4698_Y + attribute \src "libresoc.v:124550.18-124550.110" + wire $not$libresoc.v:124550$4716_Y + attribute \src "libresoc.v:124536.18-124536.110" + wire $or$libresoc.v:124536$4702_Y + attribute \src "libresoc.v:124539.18-124539.110" + wire $or$libresoc.v:124539$4705_Y + attribute \src "libresoc.v:124542.18-124542.110" + wire $or$libresoc.v:124542$4708_Y + attribute \src "libresoc.v:124544.18-124544.110" + wire $or$libresoc.v:124544$4710_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -191609,25 +194029,25 @@ module \dec_MUL wire output 6 \MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -191636,7 +194056,7 @@ module \dec_MUL attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -191653,7 +194073,7 @@ module \dec_MUL attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -191670,7 +194090,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -191747,19 +194167,19 @@ module \dec_MUL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -191780,7 +194200,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -191790,9 +194210,9 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -191802,24 +194222,24 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122551.7-122551.15" + attribute \src "libresoc.v:124158.7-124158.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 14 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122924$4656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124531$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191827,10 +194247,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122924$4656_Y + connect \Y $and$libresoc.v:124531$4697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122926$4658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124533$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191838,10 +194258,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122926$4658_Y + connect \Y $and$libresoc.v:124533$4699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122939$4671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124546$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191849,10 +194269,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122939$4671_Y + connect \Y $and$libresoc.v:124546$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122940$4672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124547$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191860,10 +194280,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122940$4672_Y + connect \Y $and$libresoc.v:124547$4713_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122942$4674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124549$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191871,10 +194291,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122942$4674_Y + connect \Y $and$libresoc.v:124549$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122944$4676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124551$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191882,10 +194302,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122944$4676_Y + connect \Y $and$libresoc.v:124551$4717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122945$4677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124552$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191893,10 +194313,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122945$4677_Y + connect \Y $and$libresoc.v:124552$4718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122946$4678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124553$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191904,10 +194324,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122946$4678_Y + connect \Y $and$libresoc.v:124553$4719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:122927$4659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124534$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191915,10 +194335,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122927$4659_Y + connect \Y $eq$libresoc.v:124534$4700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122928$4660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124535$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191926,10 +194346,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122928$4660_Y + connect \Y $eq$libresoc.v:124535$4701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122930$4662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124537$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191937,10 +194357,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122930$4662_Y + connect \Y $eq$libresoc.v:124537$4703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122931$4663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124538$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191948,10 +194368,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122931$4663_Y + connect \Y $eq$libresoc.v:124538$4704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122933$4665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124540$4706 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191959,10 +194379,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122933$4665_Y + connect \Y $eq$libresoc.v:124540$4706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122934$4666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124541$4707 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191970,10 +194390,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122934$4666_Y + connect \Y $eq$libresoc.v:124541$4707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122936$4668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124543$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191981,10 +194401,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122936$4668_Y + connect \Y $eq$libresoc.v:124543$4709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122938$4670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124545$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191992,10 +194412,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122938$4670_Y + connect \Y $eq$libresoc.v:124545$4711_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122941$4673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124548$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192003,10 +194423,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122941$4673_Y + connect \Y $eq$libresoc.v:124548$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122947$4679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124554$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192014,26 +194434,26 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122947$4679_Y + connect \Y $eq$libresoc.v:124554$4720_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122925$4657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124532$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122925$4657_Y + connect \Y $not$libresoc.v:124532$4698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122943$4675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124550$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122943$4675_Y + connect \Y $not$libresoc.v:124550$4716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:122929$4661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124536$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192041,10 +194461,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122929$4661_Y + connect \Y $or$libresoc.v:124536$4702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122932$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124539$4705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192052,10 +194472,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122932$4664_Y + connect \Y $or$libresoc.v:124539$4705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122935$4667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124542$4708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192063,10 +194483,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122935$4667_Y + connect \Y $or$libresoc.v:124542$4708_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122937$4669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124544$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192074,10 +194494,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122937$4669_Y + connect \Y $or$libresoc.v:124544$4710_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122948.13-122969.4" + attribute \src "libresoc.v:124555.13-124576.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -192101,7 +194521,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122970.16-122981.4" + attribute \src "libresoc.v:124577.16-124588.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -192115,7 +194535,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122982.16-122988.4" + attribute \src "libresoc.v:124589.16-124595.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -192124,33 +194544,33 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122989.16-122994.4" + attribute \src "libresoc.v:124596.16-124601.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122551.7-122551.20" - process $proc$libresoc.v:122551$4683 + attribute \src "libresoc.v:124158.7-124158.20" + process $proc$libresoc.v:124158$4724 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122995.3-123009.6" - process $proc$libresoc.v:122995$4680 + attribute \src "libresoc.v:124602.3-124616.6" + process $proc$libresoc.v:124602$4721 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122996.5-122996.29" + attribute \src "libresoc.v:124603.5-124603.29" switch \initial - attribute \src "libresoc.v:122996.9-122996.17" + attribute \src "libresoc.v:124603.9-124603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -192166,18 +194586,18 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:123010.3-123022.6" - process $proc$libresoc.v:123010$4681 + attribute \src "libresoc.v:124617.3-124629.6" + process $proc$libresoc.v:124617$4722 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:123011.5-123011.29" + attribute \src "libresoc.v:124618.5-124618.29" switch \initial - attribute \src "libresoc.v:123011.9-123011.17" + attribute \src "libresoc.v:124618.9-124618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192193,17 +194613,17 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:123023.3-123037.6" - process $proc$libresoc.v:123023$4682 + attribute \src "libresoc.v:124630.3-124644.6" + process $proc$libresoc.v:124630$4723 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123024.5-123024.29" + attribute \src "libresoc.v:124631.5-124631.29" switch \initial - attribute \src "libresoc.v:123024.9-123024.17" + attribute \src "libresoc.v:124631.9-124631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192221,30 +194641,30 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122924$4656_Y - connect \$12 $not$libresoc.v:122925$4657_Y - connect \$14 $and$libresoc.v:122926$4658_Y - connect \$16 $eq$libresoc.v:122927$4659_Y - connect \$18 $eq$libresoc.v:122928$4660_Y - connect \$20 $or$libresoc.v:122929$4661_Y - connect \$22 $eq$libresoc.v:122930$4662_Y - connect \$24 $eq$libresoc.v:122931$4663_Y - connect \$26 $or$libresoc.v:122932$4664_Y - connect \$28 $eq$libresoc.v:122933$4665_Y - connect \$2 $eq$libresoc.v:122934$4666_Y - connect \$30 $or$libresoc.v:122935$4667_Y - connect \$32 $eq$libresoc.v:122936$4668_Y - connect \$34 $or$libresoc.v:122937$4669_Y - connect \$36 $eq$libresoc.v:122938$4670_Y - connect \$38 $and$libresoc.v:122939$4671_Y - connect \$40 $and$libresoc.v:122940$4672_Y - connect \$42 $eq$libresoc.v:122941$4673_Y - connect \$44 $and$libresoc.v:122942$4674_Y - connect \$46 $not$libresoc.v:122943$4675_Y - connect \$48 $and$libresoc.v:122944$4676_Y - connect \$4 $and$libresoc.v:122945$4677_Y - connect \$6 $and$libresoc.v:122946$4678_Y - connect \$8 $eq$libresoc.v:122947$4679_Y + connect \$10 $and$libresoc.v:124531$4697_Y + connect \$12 $not$libresoc.v:124532$4698_Y + connect \$14 $and$libresoc.v:124533$4699_Y + connect \$16 $eq$libresoc.v:124534$4700_Y + connect \$18 $eq$libresoc.v:124535$4701_Y + connect \$20 $or$libresoc.v:124536$4702_Y + connect \$22 $eq$libresoc.v:124537$4703_Y + connect \$24 $eq$libresoc.v:124538$4704_Y + connect \$26 $or$libresoc.v:124539$4705_Y + connect \$28 $eq$libresoc.v:124540$4706_Y + connect \$2 $eq$libresoc.v:124541$4707_Y + connect \$30 $or$libresoc.v:124542$4708_Y + connect \$32 $eq$libresoc.v:124543$4709_Y + connect \$34 $or$libresoc.v:124544$4710_Y + connect \$36 $eq$libresoc.v:124545$4711_Y + connect \$38 $and$libresoc.v:124546$4712_Y + connect \$40 $and$libresoc.v:124547$4713_Y + connect \$42 $eq$libresoc.v:124548$4714_Y + connect \$44 $and$libresoc.v:124549$4715_Y + connect \$46 $not$libresoc.v:124550$4716_Y + connect \$48 $and$libresoc.v:124551$4717_Y + connect \$4 $and$libresoc.v:124552$4718_Y + connect \$6 $and$libresoc.v:124553$4719_Y + connect \$8 $eq$libresoc.v:124554$4720_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -192260,120 +194680,120 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:123056.1-123602.10" +attribute \src "libresoc.v:124663.1-125209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:123568.3-123582.6" + attribute \src "libresoc.v:125175.3-125189.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123555.3-123567.6" + attribute \src "libresoc.v:125162.3-125174.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123540.3-123554.6" + attribute \src "libresoc.v:125147.3-125161.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123057.7-123057.20" + attribute \src "libresoc.v:124664.7-124664.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123568.3-123582.6" + attribute \src "libresoc.v:125175.3-125189.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123555.3-123567.6" + attribute \src "libresoc.v:125162.3-125174.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123540.3-123554.6" + attribute \src "libresoc.v:125147.3-125161.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123465.18-123465.113" - wire $and$libresoc.v:123465$4684_Y - attribute \src "libresoc.v:123467.18-123467.110" - wire $and$libresoc.v:123467$4686_Y - attribute \src "libresoc.v:123480.18-123480.114" - wire $and$libresoc.v:123480$4699_Y - attribute \src "libresoc.v:123481.18-123481.116" - wire $and$libresoc.v:123481$4700_Y - attribute \src "libresoc.v:123483.18-123483.114" - wire $and$libresoc.v:123483$4702_Y - attribute \src "libresoc.v:123485.18-123485.110" - wire $and$libresoc.v:123485$4704_Y - attribute \src "libresoc.v:123486.17-123486.112" - wire $and$libresoc.v:123486$4705_Y - attribute \src "libresoc.v:123487.17-123487.114" - wire $and$libresoc.v:123487$4706_Y - attribute \src "libresoc.v:123468.18-123468.132" - wire $eq$libresoc.v:123468$4687_Y - attribute \src "libresoc.v:123469.18-123469.132" - wire $eq$libresoc.v:123469$4688_Y - attribute \src "libresoc.v:123471.18-123471.110" - wire $eq$libresoc.v:123471$4690_Y - attribute \src "libresoc.v:123472.18-123472.110" - wire $eq$libresoc.v:123472$4691_Y - attribute \src "libresoc.v:123474.18-123474.112" - wire $eq$libresoc.v:123474$4693_Y - attribute \src "libresoc.v:123475.17-123475.136" - wire $eq$libresoc.v:123475$4694_Y - attribute \src "libresoc.v:123477.18-123477.110" - wire $eq$libresoc.v:123477$4696_Y - attribute \src "libresoc.v:123479.18-123479.137" - wire $eq$libresoc.v:123479$4698_Y - attribute \src "libresoc.v:123482.18-123482.137" - wire $eq$libresoc.v:123482$4701_Y - attribute \src "libresoc.v:123488.17-123488.136" - wire $eq$libresoc.v:123488$4707_Y - attribute \src "libresoc.v:123466.18-123466.110" - wire $not$libresoc.v:123466$4685_Y - attribute \src "libresoc.v:123484.18-123484.110" - wire $not$libresoc.v:123484$4703_Y - attribute \src "libresoc.v:123470.18-123470.110" - wire $or$libresoc.v:123470$4689_Y - attribute \src "libresoc.v:123473.18-123473.110" - wire $or$libresoc.v:123473$4692_Y - attribute \src "libresoc.v:123476.18-123476.110" - wire $or$libresoc.v:123476$4695_Y - attribute \src "libresoc.v:123478.18-123478.110" - wire $or$libresoc.v:123478$4697_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:125072.18-125072.113" + wire $and$libresoc.v:125072$4725_Y + attribute \src "libresoc.v:125074.18-125074.110" + wire $and$libresoc.v:125074$4727_Y + attribute \src "libresoc.v:125087.18-125087.114" + wire $and$libresoc.v:125087$4740_Y + attribute \src "libresoc.v:125088.18-125088.116" + wire $and$libresoc.v:125088$4741_Y + attribute \src "libresoc.v:125090.18-125090.114" + wire $and$libresoc.v:125090$4743_Y + attribute \src "libresoc.v:125092.18-125092.110" + wire $and$libresoc.v:125092$4745_Y + attribute \src "libresoc.v:125093.17-125093.112" + wire $and$libresoc.v:125093$4746_Y + attribute \src "libresoc.v:125094.17-125094.114" + wire $and$libresoc.v:125094$4747_Y + attribute \src "libresoc.v:125075.18-125075.132" + wire $eq$libresoc.v:125075$4728_Y + attribute \src "libresoc.v:125076.18-125076.132" + wire $eq$libresoc.v:125076$4729_Y + attribute \src "libresoc.v:125078.18-125078.110" + wire $eq$libresoc.v:125078$4731_Y + attribute \src "libresoc.v:125079.18-125079.110" + wire $eq$libresoc.v:125079$4732_Y + attribute \src "libresoc.v:125081.18-125081.112" + wire $eq$libresoc.v:125081$4734_Y + attribute \src "libresoc.v:125082.17-125082.136" + wire $eq$libresoc.v:125082$4735_Y + attribute \src "libresoc.v:125084.18-125084.110" + wire $eq$libresoc.v:125084$4737_Y + attribute \src "libresoc.v:125086.18-125086.137" + wire $eq$libresoc.v:125086$4739_Y + attribute \src "libresoc.v:125089.18-125089.137" + wire $eq$libresoc.v:125089$4742_Y + attribute \src "libresoc.v:125095.17-125095.136" + wire $eq$libresoc.v:125095$4748_Y + attribute \src "libresoc.v:125073.18-125073.110" + wire $not$libresoc.v:125073$4726_Y + attribute \src "libresoc.v:125091.18-125091.110" + wire $not$libresoc.v:125091$4744_Y + attribute \src "libresoc.v:125077.18-125077.110" + wire $or$libresoc.v:125077$4730_Y + attribute \src "libresoc.v:125080.18-125080.110" + wire $or$libresoc.v:125080$4733_Y + attribute \src "libresoc.v:125083.18-125083.110" + wire $or$libresoc.v:125083$4736_Y + attribute \src "libresoc.v:125085.18-125085.110" + wire $or$libresoc.v:125085$4738_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -192503,25 +194923,25 @@ module \dec_SHIFT_ROT wire output 6 \SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -192532,7 +194952,7 @@ module \dec_SHIFT_ROT attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -192541,15 +194961,15 @@ module \dec_SHIFT_ROT attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -192566,7 +194986,7 @@ module \dec_SHIFT_ROT attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -192583,7 +195003,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -192660,21 +195080,21 @@ module \dec_SHIFT_ROT attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_SHIFT_ROT_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -192695,7 +195115,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -192705,9 +195125,9 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -192717,24 +195137,24 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123057.7-123057.15" + attribute \src "libresoc.v:124664.7-124664.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123465$4684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125072$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192742,10 +195162,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123465$4684_Y + connect \Y $and$libresoc.v:125072$4725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123467$4686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125074$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192753,10 +195173,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123467$4686_Y + connect \Y $and$libresoc.v:125074$4727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123480$4699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125087$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192764,10 +195184,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123480$4699_Y + connect \Y $and$libresoc.v:125087$4740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123481$4700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125088$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192775,10 +195195,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123481$4700_Y + connect \Y $and$libresoc.v:125088$4741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123483$4702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125090$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192786,10 +195206,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123483$4702_Y + connect \Y $and$libresoc.v:125090$4743_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123485$4704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125092$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192797,10 +195217,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123485$4704_Y + connect \Y $and$libresoc.v:125092$4745_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123486$4705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125093$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192808,10 +195228,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123486$4705_Y + connect \Y $and$libresoc.v:125093$4746_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123487$4706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125094$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192819,10 +195239,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123487$4706_Y + connect \Y $and$libresoc.v:125094$4747_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:123468$4687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:125075$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192830,10 +195250,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123468$4687_Y + connect \Y $eq$libresoc.v:125075$4728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123469$4688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:125076$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192841,10 +195261,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123469$4688_Y + connect \Y $eq$libresoc.v:125076$4729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123471$4690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125078$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192852,10 +195272,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123471$4690_Y + connect \Y $eq$libresoc.v:125078$4731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123472$4691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125079$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192863,10 +195283,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123472$4691_Y + connect \Y $eq$libresoc.v:125079$4732_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123474$4693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125081$4734 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192874,10 +195294,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123474$4693_Y + connect \Y $eq$libresoc.v:125081$4734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123475$4694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125082$4735 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192885,10 +195305,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123475$4694_Y + connect \Y $eq$libresoc.v:125082$4735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123477$4696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:125084$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192896,10 +195316,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123477$4696_Y + connect \Y $eq$libresoc.v:125084$4737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123479$4698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125086$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192907,10 +195327,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123479$4698_Y + connect \Y $eq$libresoc.v:125086$4739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123482$4701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125089$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192918,10 +195338,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123482$4701_Y + connect \Y $eq$libresoc.v:125089$4742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123488$4707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125095$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192929,26 +195349,26 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123488$4707_Y + connect \Y $eq$libresoc.v:125095$4748_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123466$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125073$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123466$4685_Y + connect \Y $not$libresoc.v:125073$4726_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123484$4703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125091$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123484$4703_Y + connect \Y $not$libresoc.v:125091$4744_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:123470$4689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:125077$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192956,10 +195376,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123470$4689_Y + connect \Y $or$libresoc.v:125077$4730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123473$4692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125080$4733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192967,10 +195387,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123473$4692_Y + connect \Y $or$libresoc.v:125080$4733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123476$4695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125083$4736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192978,10 +195398,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123476$4695_Y + connect \Y $or$libresoc.v:125083$4736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123478$4697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125085$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192989,10 +195409,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123478$4697_Y + connect \Y $or$libresoc.v:125085$4738_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123489.13-123514.4" + attribute \src "libresoc.v:125096.13-125121.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -193020,7 +195440,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123515.16-123526.4" + attribute \src "libresoc.v:125122.16-125133.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -193034,7 +195454,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123527.16-123533.4" + attribute \src "libresoc.v:125134.16-125140.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -193043,33 +195463,33 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123534.16-123539.4" + attribute \src "libresoc.v:125141.16-125146.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123057.7-123057.20" - process $proc$libresoc.v:123057$4711 + attribute \src "libresoc.v:124664.7-124664.20" + process $proc$libresoc.v:124664$4752 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123540.3-123554.6" - process $proc$libresoc.v:123540$4708 + attribute \src "libresoc.v:125147.3-125161.6" + process $proc$libresoc.v:125147$4749 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123541.5-123541.29" + attribute \src "libresoc.v:125148.5-125148.29" switch \initial - attribute \src "libresoc.v:123541.9-123541.17" + attribute \src "libresoc.v:125148.9-125148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -193085,18 +195505,18 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:123555.3-123567.6" - process $proc$libresoc.v:123555$4709 + attribute \src "libresoc.v:125162.3-125174.6" + process $proc$libresoc.v:125162$4750 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123556.5-123556.29" + attribute \src "libresoc.v:125163.5-125163.29" switch \initial - attribute \src "libresoc.v:123556.9-123556.17" + attribute \src "libresoc.v:125163.9-125163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193112,17 +195532,17 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:123568.3-123582.6" - process $proc$libresoc.v:123568$4710 + attribute \src "libresoc.v:125175.3-125189.6" + process $proc$libresoc.v:125175$4751 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123569.5-123569.29" + attribute \src "libresoc.v:125176.5-125176.29" switch \initial - attribute \src "libresoc.v:123569.9-123569.17" + attribute \src "libresoc.v:125176.9-125176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193140,30 +195560,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123465$4684_Y - connect \$12 $not$libresoc.v:123466$4685_Y - connect \$14 $and$libresoc.v:123467$4686_Y - connect \$16 $eq$libresoc.v:123468$4687_Y - connect \$18 $eq$libresoc.v:123469$4688_Y - connect \$20 $or$libresoc.v:123470$4689_Y - connect \$22 $eq$libresoc.v:123471$4690_Y - connect \$24 $eq$libresoc.v:123472$4691_Y - connect \$26 $or$libresoc.v:123473$4692_Y - connect \$28 $eq$libresoc.v:123474$4693_Y - connect \$2 $eq$libresoc.v:123475$4694_Y - connect \$30 $or$libresoc.v:123476$4695_Y - connect \$32 $eq$libresoc.v:123477$4696_Y - connect \$34 $or$libresoc.v:123478$4697_Y - connect \$36 $eq$libresoc.v:123479$4698_Y - connect \$38 $and$libresoc.v:123480$4699_Y - connect \$40 $and$libresoc.v:123481$4700_Y - connect \$42 $eq$libresoc.v:123482$4701_Y - connect \$44 $and$libresoc.v:123483$4702_Y - connect \$46 $not$libresoc.v:123484$4703_Y - connect \$48 $and$libresoc.v:123485$4704_Y - connect \$4 $and$libresoc.v:123486$4705_Y - connect \$6 $and$libresoc.v:123487$4706_Y - connect \$8 $eq$libresoc.v:123488$4707_Y + connect \$10 $and$libresoc.v:125072$4725_Y + connect \$12 $not$libresoc.v:125073$4726_Y + connect \$14 $and$libresoc.v:125074$4727_Y + connect \$16 $eq$libresoc.v:125075$4728_Y + connect \$18 $eq$libresoc.v:125076$4729_Y + connect \$20 $or$libresoc.v:125077$4730_Y + connect \$22 $eq$libresoc.v:125078$4731_Y + connect \$24 $eq$libresoc.v:125079$4732_Y + connect \$26 $or$libresoc.v:125080$4733_Y + connect \$28 $eq$libresoc.v:125081$4734_Y + connect \$2 $eq$libresoc.v:125082$4735_Y + connect \$30 $or$libresoc.v:125083$4736_Y + connect \$32 $eq$libresoc.v:125084$4737_Y + connect \$34 $or$libresoc.v:125085$4738_Y + connect \$36 $eq$libresoc.v:125086$4739_Y + connect \$38 $and$libresoc.v:125087$4740_Y + connect \$40 $and$libresoc.v:125088$4741_Y + connect \$42 $eq$libresoc.v:125089$4742_Y + connect \$44 $and$libresoc.v:125090$4743_Y + connect \$46 $not$libresoc.v:125091$4744_Y + connect \$48 $and$libresoc.v:125092$4745_Y + connect \$4 $and$libresoc.v:125093$4746_Y + connect \$6 $and$libresoc.v:125094$4747_Y + connect \$8 $eq$libresoc.v:125095$4748_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -193184,116 +195604,116 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:123606.1-123984.10" +attribute \src "libresoc.v:125213.1-125591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:123960.3-123974.6" + attribute \src "libresoc.v:125567.3-125581.6" wire width 14 $0\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123947.3-123959.6" + attribute \src "libresoc.v:125554.3-125566.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:123607.7-123607.20" + attribute \src "libresoc.v:125214.7-125214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123960.3-123974.6" + attribute \src "libresoc.v:125567.3-125581.6" wire width 14 $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123947.3-123959.6" + attribute \src "libresoc.v:125554.3-125566.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:123901.18-123901.113" - wire $and$libresoc.v:123901$4712_Y - attribute \src "libresoc.v:123903.18-123903.110" - wire $and$libresoc.v:123903$4714_Y - attribute \src "libresoc.v:123916.18-123916.114" - wire $and$libresoc.v:123916$4727_Y - attribute \src "libresoc.v:123917.18-123917.116" - wire $and$libresoc.v:123917$4728_Y - attribute \src "libresoc.v:123919.18-123919.114" - wire $and$libresoc.v:123919$4730_Y - attribute \src "libresoc.v:123921.18-123921.110" - wire $and$libresoc.v:123921$4732_Y - attribute \src "libresoc.v:123922.17-123922.112" - wire $and$libresoc.v:123922$4733_Y - attribute \src "libresoc.v:123923.17-123923.114" - wire $and$libresoc.v:123923$4734_Y - attribute \src "libresoc.v:123904.18-123904.126" - wire $eq$libresoc.v:123904$4715_Y - attribute \src "libresoc.v:123905.18-123905.126" - wire $eq$libresoc.v:123905$4716_Y - attribute \src "libresoc.v:123907.18-123907.110" - wire $eq$libresoc.v:123907$4718_Y - attribute \src "libresoc.v:123908.18-123908.110" - wire $eq$libresoc.v:123908$4719_Y - attribute \src "libresoc.v:123910.18-123910.112" - wire $eq$libresoc.v:123910$4721_Y - attribute \src "libresoc.v:123911.17-123911.130" - wire $eq$libresoc.v:123911$4722_Y - attribute \src "libresoc.v:123913.18-123913.110" - wire $eq$libresoc.v:123913$4724_Y - attribute \src "libresoc.v:123915.18-123915.131" - wire $eq$libresoc.v:123915$4726_Y - attribute \src "libresoc.v:123918.18-123918.131" - wire $eq$libresoc.v:123918$4729_Y - attribute \src "libresoc.v:123924.17-123924.130" - wire $eq$libresoc.v:123924$4735_Y - attribute \src "libresoc.v:123902.18-123902.110" - wire $not$libresoc.v:123902$4713_Y - attribute \src "libresoc.v:123920.18-123920.110" - wire $not$libresoc.v:123920$4731_Y - attribute \src "libresoc.v:123906.18-123906.110" - wire $or$libresoc.v:123906$4717_Y - attribute \src "libresoc.v:123909.18-123909.110" - wire $or$libresoc.v:123909$4720_Y - attribute \src "libresoc.v:123912.18-123912.110" - wire $or$libresoc.v:123912$4723_Y - attribute \src "libresoc.v:123914.18-123914.110" - wire $or$libresoc.v:123914$4725_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:125508.18-125508.113" + wire $and$libresoc.v:125508$4753_Y + attribute \src "libresoc.v:125510.18-125510.110" + wire $and$libresoc.v:125510$4755_Y + attribute \src "libresoc.v:125523.18-125523.114" + wire $and$libresoc.v:125523$4768_Y + attribute \src "libresoc.v:125524.18-125524.116" + wire $and$libresoc.v:125524$4769_Y + attribute \src "libresoc.v:125526.18-125526.114" + wire $and$libresoc.v:125526$4771_Y + attribute \src "libresoc.v:125528.18-125528.110" + wire $and$libresoc.v:125528$4773_Y + attribute \src "libresoc.v:125529.17-125529.112" + wire $and$libresoc.v:125529$4774_Y + attribute \src "libresoc.v:125530.17-125530.114" + wire $and$libresoc.v:125530$4775_Y + attribute \src "libresoc.v:125511.18-125511.126" + wire $eq$libresoc.v:125511$4756_Y + attribute \src "libresoc.v:125512.18-125512.126" + wire $eq$libresoc.v:125512$4757_Y + attribute \src "libresoc.v:125514.18-125514.110" + wire $eq$libresoc.v:125514$4759_Y + attribute \src "libresoc.v:125515.18-125515.110" + wire $eq$libresoc.v:125515$4760_Y + attribute \src "libresoc.v:125517.18-125517.112" + wire $eq$libresoc.v:125517$4762_Y + attribute \src "libresoc.v:125518.17-125518.130" + wire $eq$libresoc.v:125518$4763_Y + attribute \src "libresoc.v:125520.18-125520.110" + wire $eq$libresoc.v:125520$4765_Y + attribute \src "libresoc.v:125522.18-125522.131" + wire $eq$libresoc.v:125522$4767_Y + attribute \src "libresoc.v:125525.18-125525.131" + wire $eq$libresoc.v:125525$4770_Y + attribute \src "libresoc.v:125531.17-125531.130" + wire $eq$libresoc.v:125531$4776_Y + attribute \src "libresoc.v:125509.18-125509.110" + wire $not$libresoc.v:125509$4754_Y + attribute \src "libresoc.v:125527.18-125527.110" + wire $not$libresoc.v:125527$4772_Y + attribute \src "libresoc.v:125513.18-125513.110" + wire $or$libresoc.v:125513$4758_Y + attribute \src "libresoc.v:125516.18-125516.110" + wire $or$libresoc.v:125516$4761_Y + attribute \src "libresoc.v:125519.18-125519.110" + wire $or$libresoc.v:125519$4764_Y + attribute \src "libresoc.v:125521.18-125521.110" + wire $or$libresoc.v:125521$4766_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -193393,13 +195813,13 @@ module \dec_SPR wire width 7 output 2 \SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 5 \SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -193408,7 +195828,7 @@ module \dec_SPR attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SPR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -193425,7 +195845,7 @@ module \dec_SPR attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -193502,46 +195922,46 @@ module \dec_SPR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SPR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123607.7-123607.15" + attribute \src "libresoc.v:125214.7-125214.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 6 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123901$4712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125508$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193549,10 +195969,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123901$4712_Y + connect \Y $and$libresoc.v:125508$4753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123903$4714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125510$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193560,10 +195980,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123903$4714_Y + connect \Y $and$libresoc.v:125510$4755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123916$4727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125523$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193571,10 +195991,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123916$4727_Y + connect \Y $and$libresoc.v:125523$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123917$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125524$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193582,10 +196002,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123917$4728_Y + connect \Y $and$libresoc.v:125524$4769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123919$4730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125526$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193593,10 +196013,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123919$4730_Y + connect \Y $and$libresoc.v:125526$4771_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123921$4732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125528$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193604,10 +196024,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123921$4732_Y + connect \Y $and$libresoc.v:125528$4773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123922$4733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125529$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193615,10 +196035,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123922$4733_Y + connect \Y $and$libresoc.v:125529$4774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123923$4734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125530$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193626,10 +196046,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123923$4734_Y + connect \Y $and$libresoc.v:125530$4775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:123904$4715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:125511$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193637,10 +196057,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123904$4715_Y + connect \Y $eq$libresoc.v:125511$4756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123905$4716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:125512$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193648,10 +196068,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123905$4716_Y + connect \Y $eq$libresoc.v:125512$4757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123907$4718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125514$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193659,10 +196079,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123907$4718_Y + connect \Y $eq$libresoc.v:125514$4759_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123908$4719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125515$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193670,10 +196090,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123908$4719_Y + connect \Y $eq$libresoc.v:125515$4760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123910$4721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125517$4762 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193681,10 +196101,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123910$4721_Y + connect \Y $eq$libresoc.v:125517$4762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123911$4722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125518$4763 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193692,10 +196112,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123911$4722_Y + connect \Y $eq$libresoc.v:125518$4763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123913$4724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:125520$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193703,10 +196123,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123913$4724_Y + connect \Y $eq$libresoc.v:125520$4765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123915$4726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125522$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193714,10 +196134,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123915$4726_Y + connect \Y $eq$libresoc.v:125522$4767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123918$4729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125525$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193725,10 +196145,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123918$4729_Y + connect \Y $eq$libresoc.v:125525$4770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123924$4735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125531$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193736,26 +196156,26 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123924$4735_Y + connect \Y $eq$libresoc.v:125531$4776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123902$4713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125509$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123902$4713_Y + connect \Y $not$libresoc.v:125509$4754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123920$4731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125527$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123920$4731_Y + connect \Y $not$libresoc.v:125527$4772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:123906$4717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:125513$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193763,10 +196183,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123906$4717_Y + connect \Y $or$libresoc.v:125513$4758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123909$4720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125516$4761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193774,10 +196194,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123909$4720_Y + connect \Y $or$libresoc.v:125516$4761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123912$4723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125519$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193785,10 +196205,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123912$4723_Y + connect \Y $or$libresoc.v:125519$4764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123914$4725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125521$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193796,10 +196216,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123914$4725_Y + connect \Y $or$libresoc.v:125521$4766_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123925.13-123937.4" + attribute \src "libresoc.v:125532.13-125544.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -193814,38 +196234,38 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123938.16-123942.4" + attribute \src "libresoc.v:125545.16-125549.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123943.16-123946.4" + attribute \src "libresoc.v:125550.16-125553.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123607.7-123607.20" - process $proc$libresoc.v:123607$4738 + attribute \src "libresoc.v:125214.7-125214.20" + process $proc$libresoc.v:125214$4779 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123947.3-123959.6" - process $proc$libresoc.v:123947$4736 + attribute \src "libresoc.v:125554.3-125566.6" + process $proc$libresoc.v:125554$4777 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:123948.5-123948.29" + attribute \src "libresoc.v:125555.5-125555.29" switch \initial - attribute \src "libresoc.v:123948.9-123948.17" + attribute \src "libresoc.v:125555.9-125555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193861,17 +196281,17 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:123960.3-123974.6" - process $proc$libresoc.v:123960$4737 + attribute \src "libresoc.v:125567.3-125581.6" + process $proc$libresoc.v:125567$4778 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123961.5-123961.29" + attribute \src "libresoc.v:125568.5-125568.29" switch \initial - attribute \src "libresoc.v:123961.9-123961.17" + attribute \src "libresoc.v:125568.9-125568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193889,30 +196309,30 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123901$4712_Y - connect \$12 $not$libresoc.v:123902$4713_Y - connect \$14 $and$libresoc.v:123903$4714_Y - connect \$16 $eq$libresoc.v:123904$4715_Y - connect \$18 $eq$libresoc.v:123905$4716_Y - connect \$20 $or$libresoc.v:123906$4717_Y - connect \$22 $eq$libresoc.v:123907$4718_Y - connect \$24 $eq$libresoc.v:123908$4719_Y - connect \$26 $or$libresoc.v:123909$4720_Y - connect \$28 $eq$libresoc.v:123910$4721_Y - connect \$2 $eq$libresoc.v:123911$4722_Y - connect \$30 $or$libresoc.v:123912$4723_Y - connect \$32 $eq$libresoc.v:123913$4724_Y - connect \$34 $or$libresoc.v:123914$4725_Y - connect \$36 $eq$libresoc.v:123915$4726_Y - connect \$38 $and$libresoc.v:123916$4727_Y - connect \$40 $and$libresoc.v:123917$4728_Y - connect \$42 $eq$libresoc.v:123918$4729_Y - connect \$44 $and$libresoc.v:123919$4730_Y - connect \$46 $not$libresoc.v:123920$4731_Y - connect \$48 $and$libresoc.v:123921$4732_Y - connect \$4 $and$libresoc.v:123922$4733_Y - connect \$6 $and$libresoc.v:123923$4734_Y - connect \$8 $eq$libresoc.v:123924$4735_Y + connect \$10 $and$libresoc.v:125508$4753_Y + connect \$12 $not$libresoc.v:125509$4754_Y + connect \$14 $and$libresoc.v:125510$4755_Y + connect \$16 $eq$libresoc.v:125511$4756_Y + connect \$18 $eq$libresoc.v:125512$4757_Y + connect \$20 $or$libresoc.v:125513$4758_Y + connect \$22 $eq$libresoc.v:125514$4759_Y + connect \$24 $eq$libresoc.v:125515$4760_Y + connect \$26 $or$libresoc.v:125516$4761_Y + connect \$28 $eq$libresoc.v:125517$4762_Y + connect \$2 $eq$libresoc.v:125518$4763_Y + connect \$30 $or$libresoc.v:125519$4764_Y + connect \$32 $eq$libresoc.v:125520$4765_Y + connect \$34 $or$libresoc.v:125521$4766_Y + connect \$36 $eq$libresoc.v:125522$4767_Y + connect \$38 $and$libresoc.v:125523$4768_Y + connect \$40 $and$libresoc.v:125524$4769_Y + connect \$42 $eq$libresoc.v:125525$4770_Y + connect \$44 $and$libresoc.v:125526$4771_Y + connect \$46 $not$libresoc.v:125527$4772_Y + connect \$48 $and$libresoc.v:125528$4773_Y + connect \$4 $and$libresoc.v:125529$4774_Y + connect \$6 $and$libresoc.v:125530$4775_Y + connect \$8 $eq$libresoc.v:125531$4776_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -193923,148 +196343,148 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:123988.1-124517.10" +attribute \src "libresoc.v:125595.1-126124.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:123989.7-123989.20" + attribute \src "libresoc.v:125596.7-125596.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:124481.3-124491.6" + attribute \src "libresoc.v:126088.3-126098.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:124492.3-124502.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:124481.3-124491.6" + attribute \src "libresoc.v:126088.3-126098.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:124492.3-124502.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:124388.18-124388.108" - wire $and$libresoc.v:124388$4740_Y - attribute \src "libresoc.v:124397.18-124397.110" - wire $and$libresoc.v:124397$4749_Y - attribute \src "libresoc.v:124402.18-124402.113" - wire $and$libresoc.v:124402$4754_Y - attribute \src "libresoc.v:124390.18-124390.112" - wire $eq$libresoc.v:124390$4742_Y - attribute \src "libresoc.v:124391.18-124391.112" - wire $eq$libresoc.v:124391$4743_Y - attribute \src "libresoc.v:124392.17-124392.111" - wire $eq$libresoc.v:124392$4744_Y - attribute \src "libresoc.v:124393.18-124393.112" - wire $eq$libresoc.v:124393$4745_Y - attribute \src "libresoc.v:124399.18-124399.112" - wire $eq$libresoc.v:124399$4751_Y - attribute \src "libresoc.v:124403.17-124403.111" - wire $eq$libresoc.v:124403$4755_Y - attribute \src "libresoc.v:124394.18-124394.109" - wire $ne$libresoc.v:124394$4746_Y - attribute \src "libresoc.v:124395.18-124395.111" - wire $ne$libresoc.v:124395$4747_Y - attribute \src "libresoc.v:124404.17-124404.108" - wire $ne$libresoc.v:124404$4756_Y - attribute \src "libresoc.v:124405.17-124405.110" - wire $ne$libresoc.v:124405$4757_Y - attribute \src "libresoc.v:124400.18-124400.105" - wire $not$libresoc.v:124400$4752_Y - attribute \src "libresoc.v:124401.18-124401.108" - wire $not$libresoc.v:124401$4753_Y - attribute \src "libresoc.v:124387.17-124387.107" - wire $or$libresoc.v:124387$4739_Y - attribute \src "libresoc.v:124389.18-124389.109" - wire $or$libresoc.v:124389$4741_Y - attribute \src "libresoc.v:124396.18-124396.110" - wire $or$libresoc.v:124396$4748_Y - attribute \src "libresoc.v:124398.18-124398.110" - wire $or$libresoc.v:124398$4750_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + attribute \src "libresoc.v:125995.18-125995.108" + wire $and$libresoc.v:125995$4781_Y + attribute \src "libresoc.v:126004.18-126004.110" + wire $and$libresoc.v:126004$4790_Y + attribute \src "libresoc.v:126009.18-126009.113" + wire $and$libresoc.v:126009$4795_Y + attribute \src "libresoc.v:125997.18-125997.112" + wire $eq$libresoc.v:125997$4783_Y + attribute \src "libresoc.v:125998.18-125998.112" + wire $eq$libresoc.v:125998$4784_Y + attribute \src "libresoc.v:125999.17-125999.111" + wire $eq$libresoc.v:125999$4785_Y + attribute \src "libresoc.v:126000.18-126000.112" + wire $eq$libresoc.v:126000$4786_Y + attribute \src "libresoc.v:126006.18-126006.112" + wire $eq$libresoc.v:126006$4792_Y + attribute \src "libresoc.v:126010.17-126010.111" + wire $eq$libresoc.v:126010$4796_Y + attribute \src "libresoc.v:126001.18-126001.109" + wire $ne$libresoc.v:126001$4787_Y + attribute \src "libresoc.v:126002.18-126002.111" + wire $ne$libresoc.v:126002$4788_Y + attribute \src "libresoc.v:126011.17-126011.108" + wire $ne$libresoc.v:126011$4797_Y + attribute \src "libresoc.v:126012.17-126012.110" + wire $ne$libresoc.v:126012$4798_Y + attribute \src "libresoc.v:126007.18-126007.105" + wire $not$libresoc.v:126007$4793_Y + attribute \src "libresoc.v:126008.18-126008.108" + wire $not$libresoc.v:126008$4794_Y + attribute \src "libresoc.v:125994.17-125994.107" + wire $or$libresoc.v:125994$4780_Y + attribute \src "libresoc.v:125996.18-125996.109" + wire $or$libresoc.v:125996$4782_Y + attribute \src "libresoc.v:126003.18-126003.110" + wire $or$libresoc.v:126003$4789_Y + attribute \src "libresoc.v:126005.18-126005.110" + wire $or$libresoc.v:126005$4791_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - wire \$19 + wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 13 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 9 \fast_a_ok - attribute \src "libresoc.v:123989.7-123989.15" + attribute \src "libresoc.v:125596.7-125596.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -194141,15 +196561,15 @@ module \dec_a attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 14 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 4 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -194157,9 +196577,9 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:145" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -194283,7 +196703,7 @@ module \dec_a wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -194403,10 +196823,10 @@ module \dec_a wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire input 2 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $and $and$libresoc.v:124388$4740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $and $and$libresoc.v:125995$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194414,10 +196834,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 - connect \Y $and$libresoc.v:124388$4740_Y + connect \Y $and$libresoc.v:125995$4781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $and $and$libresoc.v:124397$4749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $and $and$libresoc.v:126004$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194425,10 +196845,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 - connect \Y $and$libresoc.v:124397$4749_Y + connect \Y $and$libresoc.v:126004$4790_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" - cell $and $and$libresoc.v:124402$4754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $and $and$libresoc.v:126009$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194436,10 +196856,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 - connect \Y $and$libresoc.v:124402$4754_Y + connect \Y $and$libresoc.v:126009$4795_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $eq $eq$libresoc.v:124390$4742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + cell $eq $eq$libresoc.v:125997$4783 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194447,10 +196867,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:124390$4742_Y + connect \Y $eq$libresoc.v:125997$4783_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:124391$4743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:125998$4784 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194458,10 +196878,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:124391$4743_Y + connect \Y $eq$libresoc.v:125998$4784_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:124392$4744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:125999$4785 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194469,10 +196889,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:124392$4744_Y + connect \Y $eq$libresoc.v:125999$4785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:124393$4745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $eq $eq$libresoc.v:126000$4786 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194480,10 +196900,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124393$4745_Y + connect \Y $eq$libresoc.v:126000$4786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $eq $eq$libresoc.v:124399$4751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + cell $eq $eq$libresoc.v:126006$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194491,10 +196911,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:124399$4751_Y + connect \Y $eq$libresoc.v:126006$4792_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:124403$4755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $eq $eq$libresoc.v:126010$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194502,10 +196922,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124403$4755_Y + connect \Y $eq$libresoc.v:126010$4796_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124394$4746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126001$4787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194513,10 +196933,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:124394$4746_Y + connect \Y $ne$libresoc.v:126001$4787_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124395$4747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126002$4788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194524,10 +196944,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:124395$4747_Y + connect \Y $ne$libresoc.v:126002$4788_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124404$4756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126011$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194535,10 +196955,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:124404$4756_Y + connect \Y $ne$libresoc.v:126011$4797_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124405$4757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126012$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194546,26 +196966,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:124405$4757_Y + connect \Y $ne$libresoc.v:126012$4798_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $not $not$libresoc.v:124400$4752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + cell $not $not$libresoc.v:126007$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:124400$4752_Y + connect \Y $not$libresoc.v:126007$4793_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" - cell $not $not$libresoc.v:124401$4753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $not $not$libresoc.v:126008$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:124401$4753_Y + connect \Y $not$libresoc.v:126008$4794_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124387$4739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:125994$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194573,10 +196993,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:124387$4739_Y + connect \Y $or$libresoc.v:125994$4780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124389$4741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:125996$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194584,10 +197004,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 - connect \Y $or$libresoc.v:124389$4741_Y + connect \Y $or$libresoc.v:125996$4782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124396$4748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:126003$4789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194595,10 +197015,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 - connect \Y $or$libresoc.v:124396$4748_Y + connect \Y $or$libresoc.v:126003$4789_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124398$4750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:126005$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194606,10 +197026,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 - connect \Y $or$libresoc.v:124398$4750_Y + connect \Y $or$libresoc.v:126005$4791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124406.10-124412.4" + attribute \src "libresoc.v:126013.10-126019.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -194617,27 +197037,27 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:123989.7-123989.20" - process $proc$libresoc.v:123989$4764 + attribute \src "libresoc.v:125596.7-125596.20" + process $proc$libresoc.v:125596$4805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124413.3-124428.6" - process $proc$libresoc.v:124413$4758 + attribute \src "libresoc.v:126020.3-126035.6" + process $proc$libresoc.v:126020$4799 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:124414.5-124414.29" + attribute \src "libresoc.v:126021.5-126021.29" switch \initial - attribute \src "libresoc.v:124414.9-124414.17" + attribute \src "libresoc.v:126021.9-126021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194646,7 +197066,7 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194658,19 +197078,19 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:124429.3-124444.6" - process $proc$libresoc.v:124429$4759 + attribute \src "libresoc.v:126036.3-126051.6" + process $proc$libresoc.v:126036$4800 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:124430.5-124430.29" + attribute \src "libresoc.v:126037.5-126037.29" switch \initial - attribute \src "libresoc.v:124430.9-124430.17" + attribute \src "libresoc.v:126037.9-126037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194679,7 +197099,7 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194691,21 +197111,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:124445.3-124480.6" - process $proc$libresoc.v:124445$4760 + attribute \src "libresoc.v:126052.3-126087.6" + process $proc$libresoc.v:126052$4801 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:124446.5-124446.29" + attribute \src "libresoc.v:126053.5-126053.29" switch \initial - attribute \src "libresoc.v:124446.9-124446.17" + attribute \src "libresoc.v:126053.9-126053.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -194713,7 +197133,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194731,7 +197151,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194756,18 +197176,18 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:124481.3-124491.6" - process $proc$libresoc.v:124481$4761 + attribute \src "libresoc.v:126088.3-126098.6" + process $proc$libresoc.v:126088$4802 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:124482.5-124482.29" + attribute \src "libresoc.v:126089.5-126089.29" switch \initial - attribute \src "libresoc.v:124482.9-124482.17" + attribute \src "libresoc.v:126089.9-126089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194779,18 +197199,18 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:124492.3-124502.6" - process $proc$libresoc.v:124492$4762 + attribute \src "libresoc.v:126099.3-126109.6" + process $proc$libresoc.v:126099$4803 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124493.5-124493.29" + attribute \src "libresoc.v:126100.5-126100.29" switch \initial - attribute \src "libresoc.v:124493.9-124493.17" + attribute \src "libresoc.v:126100.9-126100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194802,21 +197222,21 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:124503.3-124514.6" - process $proc$libresoc.v:124503$4763 + attribute \src "libresoc.v:126110.3-126121.6" + process $proc$libresoc.v:126110$4804 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:124504.5-124504.29" + attribute \src "libresoc.v:126111.5-126111.29" switch \initial - attribute \src "libresoc.v:124504.9-124504.17" + attribute \src "libresoc.v:126111.9-126111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194831,66 +197251,66 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:124387$4739_Y - connect \$11 $and$libresoc.v:124388$4740_Y - connect \$13 $or$libresoc.v:124389$4741_Y - connect \$15 $eq$libresoc.v:124390$4742_Y - connect \$17 $eq$libresoc.v:124391$4743_Y - connect \$1 $eq$libresoc.v:124392$4744_Y - connect \$19 $eq$libresoc.v:124393$4745_Y - connect \$21 $ne$libresoc.v:124394$4746_Y - connect \$23 $ne$libresoc.v:124395$4747_Y - connect \$25 $or$libresoc.v:124396$4748_Y - connect \$27 $and$libresoc.v:124397$4749_Y - connect \$29 $or$libresoc.v:124398$4750_Y - connect \$31 $eq$libresoc.v:124399$4751_Y - connect \$33 $not$libresoc.v:124400$4752_Y - connect \$35 $not$libresoc.v:124401$4753_Y - connect \$37 $and$libresoc.v:124402$4754_Y - connect \$3 $eq$libresoc.v:124403$4755_Y - connect \$5 $ne$libresoc.v:124404$4756_Y - connect \$7 $ne$libresoc.v:124405$4757_Y + connect \$9 $or$libresoc.v:125994$4780_Y + connect \$11 $and$libresoc.v:125995$4781_Y + connect \$13 $or$libresoc.v:125996$4782_Y + connect \$15 $eq$libresoc.v:125997$4783_Y + connect \$17 $eq$libresoc.v:125998$4784_Y + connect \$1 $eq$libresoc.v:125999$4785_Y + connect \$19 $eq$libresoc.v:126000$4786_Y + connect \$21 $ne$libresoc.v:126001$4787_Y + connect \$23 $ne$libresoc.v:126002$4788_Y + connect \$25 $or$libresoc.v:126003$4789_Y + connect \$27 $and$libresoc.v:126004$4790_Y + connect \$29 $or$libresoc.v:126005$4791_Y + connect \$31 $eq$libresoc.v:126006$4792_Y + connect \$33 $not$libresoc.v:126007$4793_Y + connect \$35 $not$libresoc.v:126008$4794_Y + connect \$37 $and$libresoc.v:126009$4795_Y + connect \$3 $eq$libresoc.v:126010$4796_Y + connect \$5 $ne$libresoc.v:126011$4797_Y + connect \$7 $ne$libresoc.v:126012$4798_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:124521.1-124566.10" +attribute \src "libresoc.v:126128.1-126173.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:124555.3-124564.6" + attribute \src "libresoc.v:126162.3-126171.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124522.7-124522.20" + attribute \src "libresoc.v:126129.7-126129.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124555.3-124564.6" + attribute \src "libresoc.v:126162.3-126171.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124550.17-124550.107" - wire $and$libresoc.v:124550$4765_Y - attribute \src "libresoc.v:124553.17-124553.107" - wire $and$libresoc.v:124553$4768_Y - attribute \src "libresoc.v:124551.17-124551.111" - wire $eq$libresoc.v:124551$4766_Y - attribute \src "libresoc.v:124552.17-124552.108" - wire $eq$libresoc.v:124552$4767_Y - attribute \src "libresoc.v:124554.17-124554.110" - wire $eq$libresoc.v:124554$4769_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126157.17-126157.107" + wire $and$libresoc.v:126157$4806_Y + attribute \src "libresoc.v:126160.17-126160.107" + wire $and$libresoc.v:126160$4809_Y + attribute \src "libresoc.v:126158.17-126158.111" + wire $eq$libresoc.v:126158$4807_Y + attribute \src "libresoc.v:126159.17-126159.108" + wire $eq$libresoc.v:126159$4808_Y + attribute \src "libresoc.v:126161.17-126161.110" + wire $eq$libresoc.v:126161$4810_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124522.7-124522.15" + attribute \src "libresoc.v:126129.7-126129.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -194898,12 +197318,12 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124550$4765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126157$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194911,10 +197331,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124550$4765_Y + connect \Y $and$libresoc.v:126157$4806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124553$4768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126160$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194922,10 +197342,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124553$4768_Y + connect \Y $and$libresoc.v:126160$4809_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124551$4766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126158$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194933,10 +197353,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124551$4766_Y + connect \Y $eq$libresoc.v:126158$4807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124552$4767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126159$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194944,10 +197364,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124552$4767_Y + connect \Y $eq$libresoc.v:126159$4808_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124554$4769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126161$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194955,28 +197375,28 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124554$4769_Y + connect \Y $eq$libresoc.v:126161$4810_Y end - attribute \src "libresoc.v:124522.7-124522.20" - process $proc$libresoc.v:124522$4771 + attribute \src "libresoc.v:126129.7-126129.20" + process $proc$libresoc.v:126129$4812 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124555.3-124564.6" - process $proc$libresoc.v:124555$4770 + attribute \src "libresoc.v:126162.3-126171.6" + process $proc$libresoc.v:126162$4811 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124556.5-124556.29" + attribute \src "libresoc.v:126163.5-126163.29" switch \initial - attribute \src "libresoc.v:124556.9-124556.17" + attribute \src "libresoc.v:126163.9-126163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194988,51 +197408,51 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124550$4765_Y - connect \$1 $eq$libresoc.v:124551$4766_Y - connect \$3 $eq$libresoc.v:124552$4767_Y - connect \$5 $and$libresoc.v:124553$4768_Y - connect \$7 $eq$libresoc.v:124554$4769_Y + connect \$9 $and$libresoc.v:126157$4806_Y + connect \$1 $eq$libresoc.v:126158$4807_Y + connect \$3 $eq$libresoc.v:126159$4808_Y + connect \$5 $and$libresoc.v:126160$4809_Y + connect \$7 $eq$libresoc.v:126161$4810_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:124570.1-124615.10" +attribute \src "libresoc.v:126177.1-126222.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:124604.3-124613.6" + attribute \src "libresoc.v:126211.3-126220.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124571.7-124571.20" + attribute \src "libresoc.v:126178.7-126178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124604.3-124613.6" + attribute \src "libresoc.v:126211.3-126220.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124599.17-124599.107" - wire $and$libresoc.v:124599$4772_Y - attribute \src "libresoc.v:124602.17-124602.107" - wire $and$libresoc.v:124602$4775_Y - attribute \src "libresoc.v:124600.17-124600.111" - wire $eq$libresoc.v:124600$4773_Y - attribute \src "libresoc.v:124601.17-124601.108" - wire $eq$libresoc.v:124601$4774_Y - attribute \src "libresoc.v:124603.17-124603.110" - wire $eq$libresoc.v:124603$4776_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126206.17-126206.107" + wire $and$libresoc.v:126206$4813_Y + attribute \src "libresoc.v:126209.17-126209.107" + wire $and$libresoc.v:126209$4816_Y + attribute \src "libresoc.v:126207.17-126207.111" + wire $eq$libresoc.v:126207$4814_Y + attribute \src "libresoc.v:126208.17-126208.108" + wire $eq$libresoc.v:126208$4815_Y + attribute \src "libresoc.v:126210.17-126210.110" + wire $eq$libresoc.v:126210$4817_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124571.7-124571.15" + attribute \src "libresoc.v:126178.7-126178.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195040,12 +197460,12 @@ module \dec_ai$148 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124599$4772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126206$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195053,10 +197473,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124599$4772_Y + connect \Y $and$libresoc.v:126206$4813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124602$4775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126209$4816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195064,10 +197484,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124602$4775_Y + connect \Y $and$libresoc.v:126209$4816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124600$4773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126207$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195075,10 +197495,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124600$4773_Y + connect \Y $eq$libresoc.v:126207$4814_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124601$4774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126208$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195086,10 +197506,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124601$4774_Y + connect \Y $eq$libresoc.v:126208$4815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124603$4776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126210$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195097,28 +197517,28 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124603$4776_Y + connect \Y $eq$libresoc.v:126210$4817_Y end - attribute \src "libresoc.v:124571.7-124571.20" - process $proc$libresoc.v:124571$4778 + attribute \src "libresoc.v:126178.7-126178.20" + process $proc$libresoc.v:126178$4819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124604.3-124613.6" - process $proc$libresoc.v:124604$4777 + attribute \src "libresoc.v:126211.3-126220.6" + process $proc$libresoc.v:126211$4818 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124605.5-124605.29" + attribute \src "libresoc.v:126212.5-126212.29" switch \initial - attribute \src "libresoc.v:124605.9-124605.17" + attribute \src "libresoc.v:126212.9-126212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195130,51 +197550,51 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124599$4772_Y - connect \$1 $eq$libresoc.v:124600$4773_Y - connect \$3 $eq$libresoc.v:124601$4774_Y - connect \$5 $and$libresoc.v:124602$4775_Y - connect \$7 $eq$libresoc.v:124603$4776_Y + connect \$9 $and$libresoc.v:126206$4813_Y + connect \$1 $eq$libresoc.v:126207$4814_Y + connect \$3 $eq$libresoc.v:126208$4815_Y + connect \$5 $and$libresoc.v:126209$4816_Y + connect \$7 $eq$libresoc.v:126210$4817_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:124619.1-124664.10" +attribute \src "libresoc.v:126226.1-126271.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:124653.3-124662.6" + attribute \src "libresoc.v:126260.3-126269.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124620.7-124620.20" + attribute \src "libresoc.v:126227.7-126227.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124653.3-124662.6" + attribute \src "libresoc.v:126260.3-126269.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124648.17-124648.107" - wire $and$libresoc.v:124648$4779_Y - attribute \src "libresoc.v:124651.17-124651.107" - wire $and$libresoc.v:124651$4782_Y - attribute \src "libresoc.v:124649.17-124649.111" - wire $eq$libresoc.v:124649$4780_Y - attribute \src "libresoc.v:124650.17-124650.108" - wire $eq$libresoc.v:124650$4781_Y - attribute \src "libresoc.v:124652.17-124652.110" - wire $eq$libresoc.v:124652$4783_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126255.17-126255.107" + wire $and$libresoc.v:126255$4820_Y + attribute \src "libresoc.v:126258.17-126258.107" + wire $and$libresoc.v:126258$4823_Y + attribute \src "libresoc.v:126256.17-126256.111" + wire $eq$libresoc.v:126256$4821_Y + attribute \src "libresoc.v:126257.17-126257.108" + wire $eq$libresoc.v:126257$4822_Y + attribute \src "libresoc.v:126259.17-126259.110" + wire $eq$libresoc.v:126259$4824_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124620.7-124620.15" + attribute \src "libresoc.v:126227.7-126227.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195182,12 +197602,12 @@ module \dec_ai$156 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124648$4779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126255$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195195,10 +197615,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124648$4779_Y + connect \Y $and$libresoc.v:126255$4820_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124651$4782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126258$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195206,10 +197626,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124651$4782_Y + connect \Y $and$libresoc.v:126258$4823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124649$4780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126256$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195217,10 +197637,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124649$4780_Y + connect \Y $eq$libresoc.v:126256$4821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124650$4781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126257$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195228,10 +197648,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124650$4781_Y + connect \Y $eq$libresoc.v:126257$4822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124652$4783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126259$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195239,28 +197659,28 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124652$4783_Y + connect \Y $eq$libresoc.v:126259$4824_Y end - attribute \src "libresoc.v:124620.7-124620.20" - process $proc$libresoc.v:124620$4785 + attribute \src "libresoc.v:126227.7-126227.20" + process $proc$libresoc.v:126227$4826 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124653.3-124662.6" - process $proc$libresoc.v:124653$4784 + attribute \src "libresoc.v:126260.3-126269.6" + process $proc$libresoc.v:126260$4825 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124654.5-124654.29" + attribute \src "libresoc.v:126261.5-126261.29" switch \initial - attribute \src "libresoc.v:124654.9-124654.17" + attribute \src "libresoc.v:126261.9-126261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195272,51 +197692,51 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124648$4779_Y - connect \$1 $eq$libresoc.v:124649$4780_Y - connect \$3 $eq$libresoc.v:124650$4781_Y - connect \$5 $and$libresoc.v:124651$4782_Y - connect \$7 $eq$libresoc.v:124652$4783_Y + connect \$9 $and$libresoc.v:126255$4820_Y + connect \$1 $eq$libresoc.v:126256$4821_Y + connect \$3 $eq$libresoc.v:126257$4822_Y + connect \$5 $and$libresoc.v:126258$4823_Y + connect \$7 $eq$libresoc.v:126259$4824_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:124668.1-124713.10" +attribute \src "libresoc.v:126275.1-126320.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:124702.3-124711.6" + attribute \src "libresoc.v:126309.3-126318.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124669.7-124669.20" + attribute \src "libresoc.v:126276.7-126276.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124702.3-124711.6" + attribute \src "libresoc.v:126309.3-126318.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124697.17-124697.107" - wire $and$libresoc.v:124697$4786_Y - attribute \src "libresoc.v:124700.17-124700.107" - wire $and$libresoc.v:124700$4789_Y - attribute \src "libresoc.v:124698.17-124698.111" - wire $eq$libresoc.v:124698$4787_Y - attribute \src "libresoc.v:124699.17-124699.108" - wire $eq$libresoc.v:124699$4788_Y - attribute \src "libresoc.v:124701.17-124701.110" - wire $eq$libresoc.v:124701$4790_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126304.17-126304.107" + wire $and$libresoc.v:126304$4827_Y + attribute \src "libresoc.v:126307.17-126307.107" + wire $and$libresoc.v:126307$4830_Y + attribute \src "libresoc.v:126305.17-126305.111" + wire $eq$libresoc.v:126305$4828_Y + attribute \src "libresoc.v:126306.17-126306.108" + wire $eq$libresoc.v:126306$4829_Y + attribute \src "libresoc.v:126308.17-126308.110" + wire $eq$libresoc.v:126308$4831_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124669.7-124669.15" + attribute \src "libresoc.v:126276.7-126276.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195324,12 +197744,12 @@ module \dec_ai$169 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124697$4786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126304$4827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195337,10 +197757,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124697$4786_Y + connect \Y $and$libresoc.v:126304$4827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124700$4789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126307$4830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195348,10 +197768,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124700$4789_Y + connect \Y $and$libresoc.v:126307$4830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124698$4787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126305$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195359,10 +197779,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124698$4787_Y + connect \Y $eq$libresoc.v:126305$4828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124699$4788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126306$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195370,10 +197790,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124699$4788_Y + connect \Y $eq$libresoc.v:126306$4829_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124701$4790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126308$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195381,28 +197801,28 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124701$4790_Y + connect \Y $eq$libresoc.v:126308$4831_Y end - attribute \src "libresoc.v:124669.7-124669.20" - process $proc$libresoc.v:124669$4792 + attribute \src "libresoc.v:126276.7-126276.20" + process $proc$libresoc.v:126276$4833 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124702.3-124711.6" - process $proc$libresoc.v:124702$4791 + attribute \src "libresoc.v:126309.3-126318.6" + process $proc$libresoc.v:126309$4832 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124703.5-124703.29" + attribute \src "libresoc.v:126310.5-126310.29" switch \initial - attribute \src "libresoc.v:124703.9-124703.17" + attribute \src "libresoc.v:126310.9-126310.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195414,79 +197834,79 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124697$4786_Y - connect \$1 $eq$libresoc.v:124698$4787_Y - connect \$3 $eq$libresoc.v:124699$4788_Y - connect \$5 $and$libresoc.v:124700$4789_Y - connect \$7 $eq$libresoc.v:124701$4790_Y + connect \$9 $and$libresoc.v:126304$4827_Y + connect \$1 $eq$libresoc.v:126305$4828_Y + connect \$3 $eq$libresoc.v:126306$4829_Y + connect \$5 $and$libresoc.v:126307$4830_Y + connect \$7 $eq$libresoc.v:126308$4831_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:124717.1-124915.10" +attribute \src "libresoc.v:126324.1-126522.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:124718.7-124718.20" + attribute \src "libresoc.v:126325.7-126325.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124849.3-124863.6" + attribute \src "libresoc.v:126456.3-126470.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:124864.3-124878.6" + attribute \src "libresoc.v:126471.3-126485.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124849.3-124863.6" + attribute \src "libresoc.v:126456.3-126470.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:124864.3-124878.6" + attribute \src "libresoc.v:126471.3-126485.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:124843.17-124843.117" - wire $eq$libresoc.v:124843$4793_Y - attribute \src "libresoc.v:124847.17-124847.117" - wire $eq$libresoc.v:124847$4799_Y - attribute \src "libresoc.v:124845.17-124845.100" - wire width 7 $extend$libresoc.v:124845$4795_Y - attribute \src "libresoc.v:124846.17-124846.100" - wire width 7 $extend$libresoc.v:124846$4797_Y - attribute \src "libresoc.v:124844.18-124844.108" - wire $not$libresoc.v:124844$4794_Y - attribute \src "libresoc.v:124848.17-124848.107" - wire $not$libresoc.v:124848$4800_Y - attribute \src "libresoc.v:124845.17-124845.100" - wire width 7 $pos$libresoc.v:124845$4796_Y - attribute \src "libresoc.v:124846.17-124846.100" - wire width 7 $pos$libresoc.v:124846$4798_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126450.17-126450.117" + wire $eq$libresoc.v:126450$4834_Y + attribute \src "libresoc.v:126454.17-126454.117" + wire $eq$libresoc.v:126454$4840_Y + attribute \src "libresoc.v:126452.17-126452.100" + wire width 7 $extend$libresoc.v:126452$4836_Y + attribute \src "libresoc.v:126453.17-126453.100" + wire width 7 $extend$libresoc.v:126453$4838_Y + attribute \src "libresoc.v:126451.18-126451.108" + wire $not$libresoc.v:126451$4835_Y + attribute \src "libresoc.v:126455.17-126455.107" + wire $not$libresoc.v:126455$4841_Y + attribute \src "libresoc.v:126452.17-126452.100" + wire width 7 $pos$libresoc.v:126452$4837_Y + attribute \src "libresoc.v:126453.17-126453.100" + wire width 7 $pos$libresoc.v:126453$4839_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 8 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:124718.7-124718.15" + attribute \src "libresoc.v:126325.7-126325.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -195563,7 +197983,7 @@ module \dec_b attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 9 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 2 \reg_b @@ -195584,10 +198004,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - cell $eq $eq$libresoc.v:124843$4793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + cell $eq $eq$libresoc.v:126450$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195595,10 +198015,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124843$4793_Y + connect \Y $eq$libresoc.v:126450$4834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - cell $eq $eq$libresoc.v:124847$4799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + cell $eq $eq$libresoc.v:126454$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195606,76 +198026,76 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124847$4799_Y + connect \Y $eq$libresoc.v:126454$4840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124845$4795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126452$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:124845$4795_Y + connect \Y $extend$libresoc.v:126452$4836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124846$4797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126453$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:124846$4797_Y + connect \Y $extend$libresoc.v:126453$4838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" - cell $not $not$libresoc.v:124844$4794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + cell $not $not$libresoc.v:126451$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124844$4794_Y + connect \Y $not$libresoc.v:126451$4835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" - cell $not $not$libresoc.v:124848$4800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + cell $not $not$libresoc.v:126455$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124848$4800_Y + connect \Y $not$libresoc.v:126455$4841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124845$4796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126452$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124845$4795_Y - connect \Y $pos$libresoc.v:124845$4796_Y + connect \A $extend$libresoc.v:126452$4836_Y + connect \Y $pos$libresoc.v:126452$4837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124846$4798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126453$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124846$4797_Y - connect \Y $pos$libresoc.v:124846$4798_Y + connect \A $extend$libresoc.v:126453$4838_Y + connect \Y $pos$libresoc.v:126453$4839_Y end - attribute \src "libresoc.v:124718.7-124718.20" - process $proc$libresoc.v:124718$4805 + attribute \src "libresoc.v:126325.7-126325.20" + process $proc$libresoc.v:126325$4846 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124849.3-124863.6" - process $proc$libresoc.v:124849$4801 + attribute \src "libresoc.v:126456.3-126470.6" + process $proc$libresoc.v:126456$4842 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:124850.5-124850.29" + attribute \src "libresoc.v:126457.5-126457.29" switch \initial - attribute \src "libresoc.v:124850.9-124850.17" + attribute \src "libresoc.v:126457.9-126457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -195691,18 +198111,18 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:124864.3-124878.6" - process $proc$libresoc.v:124864$4802 + attribute \src "libresoc.v:126471.3-126485.6" + process $proc$libresoc.v:126471$4843 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124865.5-124865.29" + attribute \src "libresoc.v:126472.5-126472.29" switch \initial - attribute \src "libresoc.v:124865.9-124865.17" + attribute \src "libresoc.v:126472.9-126472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -195718,24 +198138,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:124879.3-124896.6" - process $proc$libresoc.v:124879$4803 + attribute \src "libresoc.v:126486.3-126503.6" + process $proc$libresoc.v:126486$4844 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:124880.5-124880.29" + attribute \src "libresoc.v:126487.5-126487.29" switch \initial - attribute \src "libresoc.v:124880.9-124880.17" + attribute \src "libresoc.v:126487.9-126487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195754,24 +198174,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:124897.3-124914.6" - process $proc$libresoc.v:124897$4804 + attribute \src "libresoc.v:126504.3-126521.6" + process $proc$libresoc.v:126504$4845 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124898.5-124898.29" + attribute \src "libresoc.v:126505.5-126505.29" switch \initial - attribute \src "libresoc.v:124898.9-124898.17" + attribute \src "libresoc.v:126505.9-126505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195790,131 +198210,131 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:124843$4793_Y - connect \$11 $not$libresoc.v:124844$4794_Y - connect \$1 $pos$libresoc.v:124845$4796_Y - connect \$3 $pos$libresoc.v:124846$4798_Y - connect \$5 $eq$libresoc.v:124847$4799_Y - connect \$7 $not$libresoc.v:124848$4800_Y + connect \$9 $eq$libresoc.v:126450$4834_Y + connect \$11 $not$libresoc.v:126451$4835_Y + connect \$1 $pos$libresoc.v:126452$4837_Y + connect \$3 $pos$libresoc.v:126453$4839_Y + connect \$5 $eq$libresoc.v:126454$4840_Y + connect \$7 $not$libresoc.v:126455$4841_Y end -attribute \src "libresoc.v:124919.1-125172.10" +attribute \src "libresoc.v:126526.1-126779.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:125146.3-125156.6" + attribute \src "libresoc.v:126753.3-126763.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125157.3-125167.6" + attribute \src "libresoc.v:126764.3-126774.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125008.3-125054.6" + attribute \src "libresoc.v:126615.3-126661.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125055.3-125101.6" + attribute \src "libresoc.v:126662.3-126708.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124920.7-124920.20" + attribute \src "libresoc.v:126527.7-126527.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125135.3-125145.6" + attribute \src "libresoc.v:126742.3-126752.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125102.3-125112.6" + attribute \src "libresoc.v:126709.3-126719.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125113.3-125123.6" + attribute \src "libresoc.v:126720.3-126730.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125124.3-125134.6" + attribute \src "libresoc.v:126731.3-126741.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125146.3-125156.6" + attribute \src "libresoc.v:126753.3-126763.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125157.3-125167.6" + attribute \src "libresoc.v:126764.3-126774.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125008.3-125054.6" + attribute \src "libresoc.v:126615.3-126661.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125055.3-125101.6" + attribute \src "libresoc.v:126662.3-126708.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125135.3-125145.6" + attribute \src "libresoc.v:126742.3-126752.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125102.3-125112.6" + attribute \src "libresoc.v:126709.3-126719.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125113.3-125123.6" + attribute \src "libresoc.v:126720.3-126730.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125124.3-125134.6" + attribute \src "libresoc.v:126731.3-126741.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124998.17-124998.104" - wire width 64 $extend$libresoc.v:124998$4806_Y - attribute \src "libresoc.v:124999.18-124999.107" - wire width 64 $extend$libresoc.v:124999$4808_Y - attribute \src "libresoc.v:125002.17-125002.104" - wire width 64 $extend$libresoc.v:125002$4812_Y - attribute \src "libresoc.v:125006.17-125006.102" - wire width 64 $extend$libresoc.v:125006$4817_Y - attribute \src "libresoc.v:124998.17-124998.104" - wire width 64 $pos$libresoc.v:124998$4807_Y - attribute \src "libresoc.v:124999.18-124999.107" - wire width 64 $pos$libresoc.v:124999$4809_Y - attribute \src "libresoc.v:125002.17-125002.104" - wire width 64 $pos$libresoc.v:125002$4813_Y - attribute \src "libresoc.v:125006.17-125006.102" - wire width 64 $pos$libresoc.v:125006$4818_Y - attribute \src "libresoc.v:125000.18-125000.114" - wire width 47 $sshl$libresoc.v:125000$4810_Y - attribute \src "libresoc.v:125001.18-125001.113" - wire width 27 $sshl$libresoc.v:125001$4811_Y - attribute \src "libresoc.v:125003.18-125003.113" - wire width 17 $sshl$libresoc.v:125003$4814_Y - attribute \src "libresoc.v:125004.18-125004.113" - wire width 17 $sshl$libresoc.v:125004$4815_Y - attribute \src "libresoc.v:125005.17-125005.109" - wire width 47 $sshl$libresoc.v:125005$4816_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126605.17-126605.104" + wire width 64 $extend$libresoc.v:126605$4847_Y + attribute \src "libresoc.v:126606.18-126606.107" + wire width 64 $extend$libresoc.v:126606$4849_Y + attribute \src "libresoc.v:126609.17-126609.104" + wire width 64 $extend$libresoc.v:126609$4853_Y + attribute \src "libresoc.v:126613.17-126613.102" + wire width 64 $extend$libresoc.v:126613$4858_Y + attribute \src "libresoc.v:126605.17-126605.104" + wire width 64 $pos$libresoc.v:126605$4848_Y + attribute \src "libresoc.v:126606.18-126606.107" + wire width 64 $pos$libresoc.v:126606$4850_Y + attribute \src "libresoc.v:126609.17-126609.104" + wire width 64 $pos$libresoc.v:126609$4854_Y + attribute \src "libresoc.v:126613.17-126613.102" + wire width 64 $pos$libresoc.v:126613$4859_Y + attribute \src "libresoc.v:126607.18-126607.114" + wire width 47 $sshl$libresoc.v:126607$4851_Y + attribute \src "libresoc.v:126608.18-126608.113" + wire width 27 $sshl$libresoc.v:126608$4852_Y + attribute \src "libresoc.v:126610.18-126610.113" + wire width 17 $sshl$libresoc.v:126610$4855_Y + attribute \src "libresoc.v:126611.18-126611.113" + wire width 17 $sshl$libresoc.v:126611$4856_Y + attribute \src "libresoc.v:126612.17-126612.109" + wire width 47 $sshl$libresoc.v:126612$4857_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124920.7-124920.15" + attribute \src "libresoc.v:126527.7-126527.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195931,80 +198351,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124998$4806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126605$4847 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:124998$4806_Y + connect \Y $extend$libresoc.v:126605$4847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124999$4808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126606$4849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:124999$4808_Y + connect \Y $extend$libresoc.v:126606$4849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125002$4812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126609$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:125002$4812_Y + connect \Y $extend$libresoc.v:126609$4853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125006$4817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:126613$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125006$4817_Y + connect \Y $extend$libresoc.v:126613$4858_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124998$4807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126605$4848 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124998$4806_Y - connect \Y $pos$libresoc.v:124998$4807_Y + connect \A $extend$libresoc.v:126605$4847_Y + connect \Y $pos$libresoc.v:126605$4848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124999$4809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126606$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124999$4808_Y - connect \Y $pos$libresoc.v:124999$4809_Y + connect \A $extend$libresoc.v:126606$4849_Y + connect \Y $pos$libresoc.v:126606$4850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125002$4813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126609$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125002$4812_Y - connect \Y $pos$libresoc.v:125002$4813_Y + connect \A $extend$libresoc.v:126609$4853_Y + connect \Y $pos$libresoc.v:126609$4854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125006$4818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126613$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125006$4817_Y - connect \Y $pos$libresoc.v:125006$4818_Y + connect \A $extend$libresoc.v:126613$4858_Y + connect \Y $pos$libresoc.v:126613$4859_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125000$4810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126607$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196012,10 +198432,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125000$4810_Y + connect \Y $sshl$libresoc.v:126607$4851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125001$4811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126608$4852 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196023,10 +198443,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125001$4811_Y + connect \Y $sshl$libresoc.v:126608$4852_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125003$4814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126610$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196034,10 +198454,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125003$4814_Y + connect \Y $sshl$libresoc.v:126610$4855_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125004$4815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126611$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196045,10 +198465,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125004$4815_Y + connect \Y $sshl$libresoc.v:126611$4856_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125005$4816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126612$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196056,28 +198476,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125005$4816_Y + connect \Y $sshl$libresoc.v:126612$4857_Y end - attribute \src "libresoc.v:124920.7-124920.20" - process $proc$libresoc.v:124920$4827 + attribute \src "libresoc.v:126527.7-126527.20" + process $proc$libresoc.v:126527$4868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125008.3-125054.6" - process $proc$libresoc.v:125008$4819 + attribute \src "libresoc.v:126615.3-126661.6" + process $proc$libresoc.v:126615$4860 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125009.5-125009.29" + attribute \src "libresoc.v:126616.5-126616.29" switch \initial - attribute \src "libresoc.v:125009.9-125009.17" + attribute \src "libresoc.v:126616.9-126616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196125,18 +198545,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125055.3-125101.6" - process $proc$libresoc.v:125055$4820 + attribute \src "libresoc.v:126662.3-126708.6" + process $proc$libresoc.v:126662$4861 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125056.5-125056.29" + attribute \src "libresoc.v:126663.5-126663.29" switch \initial - attribute \src "libresoc.v:125056.9-125056.17" + attribute \src "libresoc.v:126663.9-126663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196184,18 +198604,18 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125102.3-125112.6" - process $proc$libresoc.v:125102$4821 + attribute \src "libresoc.v:126709.3-126719.6" + process $proc$libresoc.v:126709$4862 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125103.5-125103.29" + attribute \src "libresoc.v:126710.5-126710.29" switch \initial - attribute \src "libresoc.v:125103.9-125103.17" + attribute \src "libresoc.v:126710.9-126710.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196207,18 +198627,18 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125113.3-125123.6" - process $proc$libresoc.v:125113$4822 + attribute \src "libresoc.v:126720.3-126730.6" + process $proc$libresoc.v:126720$4863 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125114.5-125114.29" + attribute \src "libresoc.v:126721.5-126721.29" switch \initial - attribute \src "libresoc.v:125114.9-125114.17" + attribute \src "libresoc.v:126721.9-126721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196230,18 +198650,18 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125124.3-125134.6" - process $proc$libresoc.v:125124$4823 + attribute \src "libresoc.v:126731.3-126741.6" + process $proc$libresoc.v:126731$4864 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125125.5-125125.29" + attribute \src "libresoc.v:126732.5-126732.29" switch \initial - attribute \src "libresoc.v:125125.9-125125.17" + attribute \src "libresoc.v:126732.9-126732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196253,18 +198673,18 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125135.3-125145.6" - process $proc$libresoc.v:125135$4824 + attribute \src "libresoc.v:126742.3-126752.6" + process $proc$libresoc.v:126742$4865 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125136.5-125136.29" + attribute \src "libresoc.v:126743.5-126743.29" switch \initial - attribute \src "libresoc.v:125136.9-125136.17" + attribute \src "libresoc.v:126743.9-126743.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196276,18 +198696,18 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125146.3-125156.6" - process $proc$libresoc.v:125146$4825 + attribute \src "libresoc.v:126753.3-126763.6" + process $proc$libresoc.v:126753$4866 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125147.5-125147.29" + attribute \src "libresoc.v:126754.5-126754.29" switch \initial - attribute \src "libresoc.v:125147.9-125147.17" + attribute \src "libresoc.v:126754.9-126754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196299,18 +198719,18 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125157.3-125167.6" - process $proc$libresoc.v:125157$4826 + attribute \src "libresoc.v:126764.3-126774.6" + process $proc$libresoc.v:126764$4867 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125158.5-125158.29" + attribute \src "libresoc.v:126765.5-126765.29" switch \initial - attribute \src "libresoc.v:125158.9-125158.17" + attribute \src "libresoc.v:126765.9-126765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196322,139 +198742,139 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124998$4807_Y - connect \$11 $pos$libresoc.v:124999$4809_Y - connect \$14 $sshl$libresoc.v:125000$4810_Y - connect \$17 $sshl$libresoc.v:125001$4811_Y - connect \$1 $pos$libresoc.v:125002$4813_Y - connect \$20 $sshl$libresoc.v:125003$4814_Y - connect \$23 $sshl$libresoc.v:125004$4815_Y - connect \$4 $sshl$libresoc.v:125005$4816_Y - connect \$3 $pos$libresoc.v:125006$4818_Y + connect \$9 $pos$libresoc.v:126605$4848_Y + connect \$11 $pos$libresoc.v:126606$4850_Y + connect \$14 $sshl$libresoc.v:126607$4851_Y + connect \$17 $sshl$libresoc.v:126608$4852_Y + connect \$1 $pos$libresoc.v:126609$4854_Y + connect \$20 $sshl$libresoc.v:126610$4855_Y + connect \$23 $sshl$libresoc.v:126611$4856_Y + connect \$4 $sshl$libresoc.v:126612$4857_Y + connect \$3 $pos$libresoc.v:126613$4859_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125176.1-125429.10" +attribute \src "libresoc.v:126783.1-127036.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:125403.3-125413.6" + attribute \src "libresoc.v:127010.3-127020.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125414.3-125424.6" + attribute \src "libresoc.v:127021.3-127031.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125265.3-125311.6" + attribute \src "libresoc.v:126872.3-126918.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125312.3-125358.6" + attribute \src "libresoc.v:126919.3-126965.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125177.7-125177.20" + attribute \src "libresoc.v:126784.7-126784.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125392.3-125402.6" + attribute \src "libresoc.v:126999.3-127009.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125359.3-125369.6" + attribute \src "libresoc.v:126966.3-126976.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125370.3-125380.6" + attribute \src "libresoc.v:126977.3-126987.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125381.3-125391.6" + attribute \src "libresoc.v:126988.3-126998.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125403.3-125413.6" + attribute \src "libresoc.v:127010.3-127020.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125414.3-125424.6" + attribute \src "libresoc.v:127021.3-127031.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125265.3-125311.6" + attribute \src "libresoc.v:126872.3-126918.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125312.3-125358.6" + attribute \src "libresoc.v:126919.3-126965.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125392.3-125402.6" + attribute \src "libresoc.v:126999.3-127009.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125359.3-125369.6" + attribute \src "libresoc.v:126966.3-126976.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125370.3-125380.6" + attribute \src "libresoc.v:126977.3-126987.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125381.3-125391.6" + attribute \src "libresoc.v:126988.3-126998.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125255.17-125255.107" - wire width 64 $extend$libresoc.v:125255$4828_Y - attribute \src "libresoc.v:125256.18-125256.110" - wire width 64 $extend$libresoc.v:125256$4830_Y - attribute \src "libresoc.v:125259.17-125259.107" - wire width 64 $extend$libresoc.v:125259$4834_Y - attribute \src "libresoc.v:125263.17-125263.102" - wire width 64 $extend$libresoc.v:125263$4839_Y - attribute \src "libresoc.v:125255.17-125255.107" - wire width 64 $pos$libresoc.v:125255$4829_Y - attribute \src "libresoc.v:125256.18-125256.110" - wire width 64 $pos$libresoc.v:125256$4831_Y - attribute \src "libresoc.v:125259.17-125259.107" - wire width 64 $pos$libresoc.v:125259$4835_Y - attribute \src "libresoc.v:125263.17-125263.102" - wire width 64 $pos$libresoc.v:125263$4840_Y - attribute \src "libresoc.v:125257.18-125257.117" - wire width 47 $sshl$libresoc.v:125257$4832_Y - attribute \src "libresoc.v:125258.18-125258.116" - wire width 27 $sshl$libresoc.v:125258$4833_Y - attribute \src "libresoc.v:125260.18-125260.116" - wire width 17 $sshl$libresoc.v:125260$4836_Y - attribute \src "libresoc.v:125261.18-125261.116" - wire width 17 $sshl$libresoc.v:125261$4837_Y - attribute \src "libresoc.v:125262.17-125262.109" - wire width 47 $sshl$libresoc.v:125262$4838_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126862.17-126862.107" + wire width 64 $extend$libresoc.v:126862$4869_Y + attribute \src "libresoc.v:126863.18-126863.110" + wire width 64 $extend$libresoc.v:126863$4871_Y + attribute \src "libresoc.v:126866.17-126866.107" + wire width 64 $extend$libresoc.v:126866$4875_Y + attribute \src "libresoc.v:126870.17-126870.102" + wire width 64 $extend$libresoc.v:126870$4880_Y + attribute \src "libresoc.v:126862.17-126862.107" + wire width 64 $pos$libresoc.v:126862$4870_Y + attribute \src "libresoc.v:126863.18-126863.110" + wire width 64 $pos$libresoc.v:126863$4872_Y + attribute \src "libresoc.v:126866.17-126866.107" + wire width 64 $pos$libresoc.v:126866$4876_Y + attribute \src "libresoc.v:126870.17-126870.102" + wire width 64 $pos$libresoc.v:126870$4881_Y + attribute \src "libresoc.v:126864.18-126864.117" + wire width 47 $sshl$libresoc.v:126864$4873_Y + attribute \src "libresoc.v:126865.18-126865.116" + wire width 27 $sshl$libresoc.v:126865$4874_Y + attribute \src "libresoc.v:126867.18-126867.116" + wire width 17 $sshl$libresoc.v:126867$4877_Y + attribute \src "libresoc.v:126868.18-126868.116" + wire width 17 $sshl$libresoc.v:126868$4878_Y + attribute \src "libresoc.v:126869.17-126869.109" + wire width 47 $sshl$libresoc.v:126869$4879_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125177.7-125177.15" + attribute \src "libresoc.v:126784.7-126784.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -196471,80 +198891,80 @@ module \dec_bi$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125255$4828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126862$4869 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:125255$4828_Y + connect \Y $extend$libresoc.v:126862$4869_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125256$4830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126863$4871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:125256$4830_Y + connect \Y $extend$libresoc.v:126863$4871_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125259$4834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126866$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:125259$4834_Y + connect \Y $extend$libresoc.v:126866$4875_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125263$4839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:126870$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125263$4839_Y + connect \Y $extend$libresoc.v:126870$4880_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125255$4829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126862$4870 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125255$4828_Y - connect \Y $pos$libresoc.v:125255$4829_Y + connect \A $extend$libresoc.v:126862$4869_Y + connect \Y $pos$libresoc.v:126862$4870_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125256$4831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126863$4872 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125256$4830_Y - connect \Y $pos$libresoc.v:125256$4831_Y + connect \A $extend$libresoc.v:126863$4871_Y + connect \Y $pos$libresoc.v:126863$4872_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125259$4835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126866$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125259$4834_Y - connect \Y $pos$libresoc.v:125259$4835_Y + connect \A $extend$libresoc.v:126866$4875_Y + connect \Y $pos$libresoc.v:126866$4876_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125263$4840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126870$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125263$4839_Y - connect \Y $pos$libresoc.v:125263$4840_Y + connect \A $extend$libresoc.v:126870$4880_Y + connect \Y $pos$libresoc.v:126870$4881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125257$4832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126864$4873 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196552,10 +198972,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125257$4832_Y + connect \Y $sshl$libresoc.v:126864$4873_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125258$4833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126865$4874 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196563,10 +198983,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125258$4833_Y + connect \Y $sshl$libresoc.v:126865$4874_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125260$4836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126867$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196574,10 +198994,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125260$4836_Y + connect \Y $sshl$libresoc.v:126867$4877_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125261$4837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126868$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196585,10 +199005,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125261$4837_Y + connect \Y $sshl$libresoc.v:126868$4878_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125262$4838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126869$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196596,28 +199016,28 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125262$4838_Y + connect \Y $sshl$libresoc.v:126869$4879_Y end - attribute \src "libresoc.v:125177.7-125177.20" - process $proc$libresoc.v:125177$4849 + attribute \src "libresoc.v:126784.7-126784.20" + process $proc$libresoc.v:126784$4890 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125265.3-125311.6" - process $proc$libresoc.v:125265$4841 + attribute \src "libresoc.v:126872.3-126918.6" + process $proc$libresoc.v:126872$4882 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125266.5-125266.29" + attribute \src "libresoc.v:126873.5-126873.29" switch \initial - attribute \src "libresoc.v:125266.9-125266.17" + attribute \src "libresoc.v:126873.9-126873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196665,18 +199085,18 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125312.3-125358.6" - process $proc$libresoc.v:125312$4842 + attribute \src "libresoc.v:126919.3-126965.6" + process $proc$libresoc.v:126919$4883 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125313.5-125313.29" + attribute \src "libresoc.v:126920.5-126920.29" switch \initial - attribute \src "libresoc.v:125313.9-125313.17" + attribute \src "libresoc.v:126920.9-126920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196724,18 +199144,18 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125359.3-125369.6" - process $proc$libresoc.v:125359$4843 + attribute \src "libresoc.v:126966.3-126976.6" + process $proc$libresoc.v:126966$4884 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125360.5-125360.29" + attribute \src "libresoc.v:126967.5-126967.29" switch \initial - attribute \src "libresoc.v:125360.9-125360.17" + attribute \src "libresoc.v:126967.9-126967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196747,18 +199167,18 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125370.3-125380.6" - process $proc$libresoc.v:125370$4844 + attribute \src "libresoc.v:126977.3-126987.6" + process $proc$libresoc.v:126977$4885 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125371.5-125371.29" + attribute \src "libresoc.v:126978.5-126978.29" switch \initial - attribute \src "libresoc.v:125371.9-125371.17" + attribute \src "libresoc.v:126978.9-126978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196770,18 +199190,18 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125381.3-125391.6" - process $proc$libresoc.v:125381$4845 + attribute \src "libresoc.v:126988.3-126998.6" + process $proc$libresoc.v:126988$4886 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125382.5-125382.29" + attribute \src "libresoc.v:126989.5-126989.29" switch \initial - attribute \src "libresoc.v:125382.9-125382.17" + attribute \src "libresoc.v:126989.9-126989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196793,18 +199213,18 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125392.3-125402.6" - process $proc$libresoc.v:125392$4846 + attribute \src "libresoc.v:126999.3-127009.6" + process $proc$libresoc.v:126999$4887 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125393.5-125393.29" + attribute \src "libresoc.v:127000.5-127000.29" switch \initial - attribute \src "libresoc.v:125393.9-125393.17" + attribute \src "libresoc.v:127000.9-127000.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196816,18 +199236,18 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125403.3-125413.6" - process $proc$libresoc.v:125403$4847 + attribute \src "libresoc.v:127010.3-127020.6" + process $proc$libresoc.v:127010$4888 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125404.5-125404.29" + attribute \src "libresoc.v:127011.5-127011.29" switch \initial - attribute \src "libresoc.v:125404.9-125404.17" + attribute \src "libresoc.v:127011.9-127011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196839,18 +199259,18 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125414.3-125424.6" - process $proc$libresoc.v:125414$4848 + attribute \src "libresoc.v:127021.3-127031.6" + process $proc$libresoc.v:127021$4889 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125415.5-125415.29" + attribute \src "libresoc.v:127022.5-127022.29" switch \initial - attribute \src "libresoc.v:125415.9-125415.17" + attribute \src "libresoc.v:127022.9-127022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196862,139 +199282,139 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125255$4829_Y - connect \$11 $pos$libresoc.v:125256$4831_Y - connect \$14 $sshl$libresoc.v:125257$4832_Y - connect \$17 $sshl$libresoc.v:125258$4833_Y - connect \$1 $pos$libresoc.v:125259$4835_Y - connect \$20 $sshl$libresoc.v:125260$4836_Y - connect \$23 $sshl$libresoc.v:125261$4837_Y - connect \$4 $sshl$libresoc.v:125262$4838_Y - connect \$3 $pos$libresoc.v:125263$4840_Y + connect \$9 $pos$libresoc.v:126862$4870_Y + connect \$11 $pos$libresoc.v:126863$4872_Y + connect \$14 $sshl$libresoc.v:126864$4873_Y + connect \$17 $sshl$libresoc.v:126865$4874_Y + connect \$1 $pos$libresoc.v:126866$4876_Y + connect \$20 $sshl$libresoc.v:126867$4877_Y + connect \$23 $sshl$libresoc.v:126868$4878_Y + connect \$4 $sshl$libresoc.v:126869$4879_Y + connect \$3 $pos$libresoc.v:126870$4881_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125433.1-125686.10" +attribute \src "libresoc.v:127040.1-127293.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:125660.3-125670.6" + attribute \src "libresoc.v:127267.3-127277.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125671.3-125681.6" + attribute \src "libresoc.v:127278.3-127288.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125522.3-125568.6" + attribute \src "libresoc.v:127129.3-127175.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125569.3-125615.6" + attribute \src "libresoc.v:127176.3-127222.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125434.7-125434.20" + attribute \src "libresoc.v:127041.7-127041.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125649.3-125659.6" + attribute \src "libresoc.v:127256.3-127266.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125616.3-125626.6" + attribute \src "libresoc.v:127223.3-127233.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125627.3-125637.6" + attribute \src "libresoc.v:127234.3-127244.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125638.3-125648.6" + attribute \src "libresoc.v:127245.3-127255.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125660.3-125670.6" + attribute \src "libresoc.v:127267.3-127277.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125671.3-125681.6" + attribute \src "libresoc.v:127278.3-127288.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125522.3-125568.6" + attribute \src "libresoc.v:127129.3-127175.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125569.3-125615.6" + attribute \src "libresoc.v:127176.3-127222.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125649.3-125659.6" + attribute \src "libresoc.v:127256.3-127266.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125616.3-125626.6" + attribute \src "libresoc.v:127223.3-127233.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125627.3-125637.6" + attribute \src "libresoc.v:127234.3-127244.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125638.3-125648.6" + attribute \src "libresoc.v:127245.3-127255.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125512.17-125512.108" - wire width 64 $extend$libresoc.v:125512$4850_Y - attribute \src "libresoc.v:125513.18-125513.111" - wire width 64 $extend$libresoc.v:125513$4852_Y - attribute \src "libresoc.v:125516.17-125516.108" - wire width 64 $extend$libresoc.v:125516$4856_Y - attribute \src "libresoc.v:125520.17-125520.102" - wire width 64 $extend$libresoc.v:125520$4861_Y - attribute \src "libresoc.v:125512.17-125512.108" - wire width 64 $pos$libresoc.v:125512$4851_Y - attribute \src "libresoc.v:125513.18-125513.111" - wire width 64 $pos$libresoc.v:125513$4853_Y - attribute \src "libresoc.v:125516.17-125516.108" - wire width 64 $pos$libresoc.v:125516$4857_Y - attribute \src "libresoc.v:125520.17-125520.102" - wire width 64 $pos$libresoc.v:125520$4862_Y - attribute \src "libresoc.v:125514.18-125514.118" - wire width 47 $sshl$libresoc.v:125514$4854_Y - attribute \src "libresoc.v:125515.18-125515.117" - wire width 27 $sshl$libresoc.v:125515$4855_Y - attribute \src "libresoc.v:125517.18-125517.117" - wire width 17 $sshl$libresoc.v:125517$4858_Y - attribute \src "libresoc.v:125518.18-125518.117" - wire width 17 $sshl$libresoc.v:125518$4859_Y - attribute \src "libresoc.v:125519.17-125519.109" - wire width 47 $sshl$libresoc.v:125519$4860_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127119.17-127119.108" + wire width 64 $extend$libresoc.v:127119$4891_Y + attribute \src "libresoc.v:127120.18-127120.111" + wire width 64 $extend$libresoc.v:127120$4893_Y + attribute \src "libresoc.v:127123.17-127123.108" + wire width 64 $extend$libresoc.v:127123$4897_Y + attribute \src "libresoc.v:127127.17-127127.102" + wire width 64 $extend$libresoc.v:127127$4902_Y + attribute \src "libresoc.v:127119.17-127119.108" + wire width 64 $pos$libresoc.v:127119$4892_Y + attribute \src "libresoc.v:127120.18-127120.111" + wire width 64 $pos$libresoc.v:127120$4894_Y + attribute \src "libresoc.v:127123.17-127123.108" + wire width 64 $pos$libresoc.v:127123$4898_Y + attribute \src "libresoc.v:127127.17-127127.102" + wire width 64 $pos$libresoc.v:127127$4903_Y + attribute \src "libresoc.v:127121.18-127121.118" + wire width 47 $sshl$libresoc.v:127121$4895_Y + attribute \src "libresoc.v:127122.18-127122.117" + wire width 27 $sshl$libresoc.v:127122$4896_Y + attribute \src "libresoc.v:127124.18-127124.117" + wire width 17 $sshl$libresoc.v:127124$4899_Y + attribute \src "libresoc.v:127125.18-127125.117" + wire width 17 $sshl$libresoc.v:127125$4900_Y + attribute \src "libresoc.v:127126.17-127126.109" + wire width 47 $sshl$libresoc.v:127126$4901_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125434.7-125434.15" + attribute \src "libresoc.v:127041.7-127041.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -197011,80 +199431,80 @@ module \dec_bi$149 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125512$4850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127119$4891 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:125512$4850_Y + connect \Y $extend$libresoc.v:127119$4891_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125513$4852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127120$4893 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:125513$4852_Y + connect \Y $extend$libresoc.v:127120$4893_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125516$4856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127123$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:125516$4856_Y + connect \Y $extend$libresoc.v:127123$4897_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125520$4861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127127$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125520$4861_Y + connect \Y $extend$libresoc.v:127127$4902_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125512$4851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127119$4892 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125512$4850_Y - connect \Y $pos$libresoc.v:125512$4851_Y + connect \A $extend$libresoc.v:127119$4891_Y + connect \Y $pos$libresoc.v:127119$4892_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125513$4853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127120$4894 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125513$4852_Y - connect \Y $pos$libresoc.v:125513$4853_Y + connect \A $extend$libresoc.v:127120$4893_Y + connect \Y $pos$libresoc.v:127120$4894_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125516$4857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127123$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125516$4856_Y - connect \Y $pos$libresoc.v:125516$4857_Y + connect \A $extend$libresoc.v:127123$4897_Y + connect \Y $pos$libresoc.v:127123$4898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125520$4862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127127$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125520$4861_Y - connect \Y $pos$libresoc.v:125520$4862_Y + connect \A $extend$libresoc.v:127127$4902_Y + connect \Y $pos$libresoc.v:127127$4903_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125514$4854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127121$4895 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197092,10 +199512,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125514$4854_Y + connect \Y $sshl$libresoc.v:127121$4895_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125515$4855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127122$4896 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -197103,10 +199523,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125515$4855_Y + connect \Y $sshl$libresoc.v:127122$4896_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125517$4858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127124$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197114,10 +199534,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125517$4858_Y + connect \Y $sshl$libresoc.v:127124$4899_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125518$4859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127125$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197125,10 +199545,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125518$4859_Y + connect \Y $sshl$libresoc.v:127125$4900_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125519$4860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127126$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197136,28 +199556,28 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125519$4860_Y + connect \Y $sshl$libresoc.v:127126$4901_Y end - attribute \src "libresoc.v:125434.7-125434.20" - process $proc$libresoc.v:125434$4871 + attribute \src "libresoc.v:127041.7-127041.20" + process $proc$libresoc.v:127041$4912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125522.3-125568.6" - process $proc$libresoc.v:125522$4863 + attribute \src "libresoc.v:127129.3-127175.6" + process $proc$libresoc.v:127129$4904 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125523.5-125523.29" + attribute \src "libresoc.v:127130.5-127130.29" switch \initial - attribute \src "libresoc.v:125523.9-125523.17" + attribute \src "libresoc.v:127130.9-127130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197205,18 +199625,18 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125569.3-125615.6" - process $proc$libresoc.v:125569$4864 + attribute \src "libresoc.v:127176.3-127222.6" + process $proc$libresoc.v:127176$4905 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125570.5-125570.29" + attribute \src "libresoc.v:127177.5-127177.29" switch \initial - attribute \src "libresoc.v:125570.9-125570.17" + attribute \src "libresoc.v:127177.9-127177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197264,18 +199684,18 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125616.3-125626.6" - process $proc$libresoc.v:125616$4865 + attribute \src "libresoc.v:127223.3-127233.6" + process $proc$libresoc.v:127223$4906 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125617.5-125617.29" + attribute \src "libresoc.v:127224.5-127224.29" switch \initial - attribute \src "libresoc.v:125617.9-125617.17" + attribute \src "libresoc.v:127224.9-127224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -197287,18 +199707,18 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125627.3-125637.6" - process $proc$libresoc.v:125627$4866 + attribute \src "libresoc.v:127234.3-127244.6" + process $proc$libresoc.v:127234$4907 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125628.5-125628.29" + attribute \src "libresoc.v:127235.5-127235.29" switch \initial - attribute \src "libresoc.v:125628.9-125628.17" + attribute \src "libresoc.v:127235.9-127235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -197310,18 +199730,18 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125638.3-125648.6" - process $proc$libresoc.v:125638$4867 + attribute \src "libresoc.v:127245.3-127255.6" + process $proc$libresoc.v:127245$4908 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125639.5-125639.29" + attribute \src "libresoc.v:127246.5-127246.29" switch \initial - attribute \src "libresoc.v:125639.9-125639.17" + attribute \src "libresoc.v:127246.9-127246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -197333,18 +199753,18 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125649.3-125659.6" - process $proc$libresoc.v:125649$4868 + attribute \src "libresoc.v:127256.3-127266.6" + process $proc$libresoc.v:127256$4909 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125650.5-125650.29" + attribute \src "libresoc.v:127257.5-127257.29" switch \initial - attribute \src "libresoc.v:125650.9-125650.17" + attribute \src "libresoc.v:127257.9-127257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -197356,18 +199776,18 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125660.3-125670.6" - process $proc$libresoc.v:125660$4869 + attribute \src "libresoc.v:127267.3-127277.6" + process $proc$libresoc.v:127267$4910 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125661.5-125661.29" + attribute \src "libresoc.v:127268.5-127268.29" switch \initial - attribute \src "libresoc.v:125661.9-125661.17" + attribute \src "libresoc.v:127268.9-127268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -197379,18 +199799,18 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125671.3-125681.6" - process $proc$libresoc.v:125671$4870 + attribute \src "libresoc.v:127278.3-127288.6" + process $proc$libresoc.v:127278$4911 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125672.5-125672.29" + attribute \src "libresoc.v:127279.5-127279.29" switch \initial - attribute \src "libresoc.v:125672.9-125672.17" + attribute \src "libresoc.v:127279.9-127279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -197402,139 +199822,139 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125512$4851_Y - connect \$11 $pos$libresoc.v:125513$4853_Y - connect \$14 $sshl$libresoc.v:125514$4854_Y - connect \$17 $sshl$libresoc.v:125515$4855_Y - connect \$1 $pos$libresoc.v:125516$4857_Y - connect \$20 $sshl$libresoc.v:125517$4858_Y - connect \$23 $sshl$libresoc.v:125518$4859_Y - connect \$4 $sshl$libresoc.v:125519$4860_Y - connect \$3 $pos$libresoc.v:125520$4862_Y + connect \$9 $pos$libresoc.v:127119$4892_Y + connect \$11 $pos$libresoc.v:127120$4894_Y + connect \$14 $sshl$libresoc.v:127121$4895_Y + connect \$17 $sshl$libresoc.v:127122$4896_Y + connect \$1 $pos$libresoc.v:127123$4898_Y + connect \$20 $sshl$libresoc.v:127124$4899_Y + connect \$23 $sshl$libresoc.v:127125$4900_Y + connect \$4 $sshl$libresoc.v:127126$4901_Y + connect \$3 $pos$libresoc.v:127127$4903_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125690.1-125943.10" +attribute \src "libresoc.v:127297.1-127550.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:125917.3-125927.6" + attribute \src "libresoc.v:127524.3-127534.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125928.3-125938.6" + attribute \src "libresoc.v:127535.3-127545.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125779.3-125825.6" + attribute \src "libresoc.v:127386.3-127432.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125826.3-125872.6" + attribute \src "libresoc.v:127433.3-127479.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125691.7-125691.20" + attribute \src "libresoc.v:127298.7-127298.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125906.3-125916.6" + attribute \src "libresoc.v:127513.3-127523.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125873.3-125883.6" + attribute \src "libresoc.v:127480.3-127490.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125884.3-125894.6" + attribute \src "libresoc.v:127491.3-127501.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125895.3-125905.6" + attribute \src "libresoc.v:127502.3-127512.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125917.3-125927.6" + attribute \src "libresoc.v:127524.3-127534.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125928.3-125938.6" + attribute \src "libresoc.v:127535.3-127545.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125779.3-125825.6" + attribute \src "libresoc.v:127386.3-127432.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125826.3-125872.6" + attribute \src "libresoc.v:127433.3-127479.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125906.3-125916.6" + attribute \src "libresoc.v:127513.3-127523.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125873.3-125883.6" + attribute \src "libresoc.v:127480.3-127490.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125884.3-125894.6" + attribute \src "libresoc.v:127491.3-127501.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125895.3-125905.6" + attribute \src "libresoc.v:127502.3-127512.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125769.17-125769.104" - wire width 64 $extend$libresoc.v:125769$4872_Y - attribute \src "libresoc.v:125770.18-125770.107" - wire width 64 $extend$libresoc.v:125770$4874_Y - attribute \src "libresoc.v:125773.17-125773.104" - wire width 64 $extend$libresoc.v:125773$4878_Y - attribute \src "libresoc.v:125777.17-125777.102" - wire width 64 $extend$libresoc.v:125777$4883_Y - attribute \src "libresoc.v:125769.17-125769.104" - wire width 64 $pos$libresoc.v:125769$4873_Y - attribute \src "libresoc.v:125770.18-125770.107" - wire width 64 $pos$libresoc.v:125770$4875_Y - attribute \src "libresoc.v:125773.17-125773.104" - wire width 64 $pos$libresoc.v:125773$4879_Y - attribute \src "libresoc.v:125777.17-125777.102" - wire width 64 $pos$libresoc.v:125777$4884_Y - attribute \src "libresoc.v:125771.18-125771.114" - wire width 47 $sshl$libresoc.v:125771$4876_Y - attribute \src "libresoc.v:125772.18-125772.113" - wire width 27 $sshl$libresoc.v:125772$4877_Y - attribute \src "libresoc.v:125774.18-125774.113" - wire width 17 $sshl$libresoc.v:125774$4880_Y - attribute \src "libresoc.v:125775.18-125775.113" - wire width 17 $sshl$libresoc.v:125775$4881_Y - attribute \src "libresoc.v:125776.17-125776.109" - wire width 47 $sshl$libresoc.v:125776$4882_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $extend$libresoc.v:127376$4913_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $extend$libresoc.v:127377$4915_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $extend$libresoc.v:127380$4919_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $extend$libresoc.v:127384$4924_Y + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $pos$libresoc.v:127376$4914_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $pos$libresoc.v:127377$4916_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $pos$libresoc.v:127380$4920_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $pos$libresoc.v:127384$4925_Y + attribute \src "libresoc.v:127378.18-127378.114" + wire width 47 $sshl$libresoc.v:127378$4917_Y + attribute \src "libresoc.v:127379.18-127379.113" + wire width 27 $sshl$libresoc.v:127379$4918_Y + attribute \src "libresoc.v:127381.18-127381.113" + wire width 17 $sshl$libresoc.v:127381$4921_Y + attribute \src "libresoc.v:127382.18-127382.113" + wire width 17 $sshl$libresoc.v:127382$4922_Y + attribute \src "libresoc.v:127383.17-127383.109" + wire width 47 $sshl$libresoc.v:127383$4923_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125691.7-125691.15" + attribute \src "libresoc.v:127298.7-127298.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -197551,80 +199971,80 @@ module \dec_bi$157 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125769$4872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127376$4913 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:125769$4872_Y + connect \Y $extend$libresoc.v:127376$4913_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125770$4874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127377$4915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:125770$4874_Y + connect \Y $extend$libresoc.v:127377$4915_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125773$4878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127380$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:125773$4878_Y + connect \Y $extend$libresoc.v:127380$4919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125777$4883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127384$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125777$4883_Y + connect \Y $extend$libresoc.v:127384$4924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125769$4873 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127376$4914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125769$4872_Y - connect \Y $pos$libresoc.v:125769$4873_Y + connect \A $extend$libresoc.v:127376$4913_Y + connect \Y $pos$libresoc.v:127376$4914_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125770$4875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127377$4916 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125770$4874_Y - connect \Y $pos$libresoc.v:125770$4875_Y + connect \A $extend$libresoc.v:127377$4915_Y + connect \Y $pos$libresoc.v:127377$4916_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125773$4879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127380$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125773$4878_Y - connect \Y $pos$libresoc.v:125773$4879_Y + connect \A $extend$libresoc.v:127380$4919_Y + connect \Y $pos$libresoc.v:127380$4920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125777$4884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127384$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125777$4883_Y - connect \Y $pos$libresoc.v:125777$4884_Y + connect \A $extend$libresoc.v:127384$4924_Y + connect \Y $pos$libresoc.v:127384$4925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125771$4876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127378$4917 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197632,10 +200052,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125771$4876_Y + connect \Y $sshl$libresoc.v:127378$4917_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125772$4877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127379$4918 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -197643,10 +200063,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125772$4877_Y + connect \Y $sshl$libresoc.v:127379$4918_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125774$4880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127381$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197654,10 +200074,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125774$4880_Y + connect \Y $sshl$libresoc.v:127381$4921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125775$4881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127382$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197665,10 +200085,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125775$4881_Y + connect \Y $sshl$libresoc.v:127382$4922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125776$4882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127383$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197676,28 +200096,28 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125776$4882_Y + connect \Y $sshl$libresoc.v:127383$4923_Y end - attribute \src "libresoc.v:125691.7-125691.20" - process $proc$libresoc.v:125691$4893 + attribute \src "libresoc.v:127298.7-127298.20" + process $proc$libresoc.v:127298$4934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125779.3-125825.6" - process $proc$libresoc.v:125779$4885 + attribute \src "libresoc.v:127386.3-127432.6" + process $proc$libresoc.v:127386$4926 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125780.5-125780.29" + attribute \src "libresoc.v:127387.5-127387.29" switch \initial - attribute \src "libresoc.v:125780.9-125780.17" + attribute \src "libresoc.v:127387.9-127387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197745,18 +200165,18 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125826.3-125872.6" - process $proc$libresoc.v:125826$4886 + attribute \src "libresoc.v:127433.3-127479.6" + process $proc$libresoc.v:127433$4927 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125827.5-125827.29" + attribute \src "libresoc.v:127434.5-127434.29" switch \initial - attribute \src "libresoc.v:125827.9-125827.17" + attribute \src "libresoc.v:127434.9-127434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197804,18 +200224,18 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125873.3-125883.6" - process $proc$libresoc.v:125873$4887 + attribute \src "libresoc.v:127480.3-127490.6" + process $proc$libresoc.v:127480$4928 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125874.5-125874.29" + attribute \src "libresoc.v:127481.5-127481.29" switch \initial - attribute \src "libresoc.v:125874.9-125874.17" + attribute \src "libresoc.v:127481.9-127481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -197827,18 +200247,18 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125884.3-125894.6" - process $proc$libresoc.v:125884$4888 + attribute \src "libresoc.v:127491.3-127501.6" + process $proc$libresoc.v:127491$4929 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125885.5-125885.29" + attribute \src "libresoc.v:127492.5-127492.29" switch \initial - attribute \src "libresoc.v:125885.9-125885.17" + attribute \src "libresoc.v:127492.9-127492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -197850,18 +200270,18 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125895.3-125905.6" - process $proc$libresoc.v:125895$4889 + attribute \src "libresoc.v:127502.3-127512.6" + process $proc$libresoc.v:127502$4930 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125896.5-125896.29" + attribute \src "libresoc.v:127503.5-127503.29" switch \initial - attribute \src "libresoc.v:125896.9-125896.17" + attribute \src "libresoc.v:127503.9-127503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -197873,18 +200293,18 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125906.3-125916.6" - process $proc$libresoc.v:125906$4890 + attribute \src "libresoc.v:127513.3-127523.6" + process $proc$libresoc.v:127513$4931 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125907.5-125907.29" + attribute \src "libresoc.v:127514.5-127514.29" switch \initial - attribute \src "libresoc.v:125907.9-125907.17" + attribute \src "libresoc.v:127514.9-127514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -197896,18 +200316,18 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125917.3-125927.6" - process $proc$libresoc.v:125917$4891 + attribute \src "libresoc.v:127524.3-127534.6" + process $proc$libresoc.v:127524$4932 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125918.5-125918.29" + attribute \src "libresoc.v:127525.5-127525.29" switch \initial - attribute \src "libresoc.v:125918.9-125918.17" + attribute \src "libresoc.v:127525.9-127525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -197919,18 +200339,18 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125928.3-125938.6" - process $proc$libresoc.v:125928$4892 + attribute \src "libresoc.v:127535.3-127545.6" + process $proc$libresoc.v:127535$4933 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125929.5-125929.29" + attribute \src "libresoc.v:127536.5-127536.29" switch \initial - attribute \src "libresoc.v:125929.9-125929.17" + attribute \src "libresoc.v:127536.9-127536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -197942,139 +200362,139 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125769$4873_Y - connect \$11 $pos$libresoc.v:125770$4875_Y - connect \$14 $sshl$libresoc.v:125771$4876_Y - connect \$17 $sshl$libresoc.v:125772$4877_Y - connect \$1 $pos$libresoc.v:125773$4879_Y - connect \$20 $sshl$libresoc.v:125774$4880_Y - connect \$23 $sshl$libresoc.v:125775$4881_Y - connect \$4 $sshl$libresoc.v:125776$4882_Y - connect \$3 $pos$libresoc.v:125777$4884_Y + connect \$9 $pos$libresoc.v:127376$4914_Y + connect \$11 $pos$libresoc.v:127377$4916_Y + connect \$14 $sshl$libresoc.v:127378$4917_Y + connect \$17 $sshl$libresoc.v:127379$4918_Y + connect \$1 $pos$libresoc.v:127380$4920_Y + connect \$20 $sshl$libresoc.v:127381$4921_Y + connect \$23 $sshl$libresoc.v:127382$4922_Y + connect \$4 $sshl$libresoc.v:127383$4923_Y + connect \$3 $pos$libresoc.v:127384$4925_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125947.1-126200.10" +attribute \src "libresoc.v:127554.1-127807.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:126174.3-126184.6" + attribute \src "libresoc.v:127781.3-127791.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126185.3-126195.6" + attribute \src "libresoc.v:127792.3-127802.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126036.3-126082.6" + attribute \src "libresoc.v:127643.3-127689.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126083.3-126129.6" + attribute \src "libresoc.v:127690.3-127736.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125948.7-125948.20" + attribute \src "libresoc.v:127555.7-127555.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126163.3-126173.6" + attribute \src "libresoc.v:127770.3-127780.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126130.3-126140.6" + attribute \src "libresoc.v:127737.3-127747.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126141.3-126151.6" + attribute \src "libresoc.v:127748.3-127758.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126152.3-126162.6" + attribute \src "libresoc.v:127759.3-127769.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126174.3-126184.6" + attribute \src "libresoc.v:127781.3-127791.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126185.3-126195.6" + attribute \src "libresoc.v:127792.3-127802.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126036.3-126082.6" + attribute \src "libresoc.v:127643.3-127689.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126083.3-126129.6" + attribute \src "libresoc.v:127690.3-127736.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126163.3-126173.6" + attribute \src "libresoc.v:127770.3-127780.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126130.3-126140.6" + attribute \src "libresoc.v:127737.3-127747.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126141.3-126151.6" + attribute \src "libresoc.v:127748.3-127758.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126152.3-126162.6" + attribute \src "libresoc.v:127759.3-127769.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126026.17-126026.104" - wire width 64 $extend$libresoc.v:126026$4894_Y - attribute \src "libresoc.v:126027.18-126027.107" - wire width 64 $extend$libresoc.v:126027$4896_Y - attribute \src "libresoc.v:126030.17-126030.104" - wire width 64 $extend$libresoc.v:126030$4900_Y - attribute \src "libresoc.v:126034.17-126034.102" - wire width 64 $extend$libresoc.v:126034$4905_Y - attribute \src "libresoc.v:126026.17-126026.104" - wire width 64 $pos$libresoc.v:126026$4895_Y - attribute \src "libresoc.v:126027.18-126027.107" - wire width 64 $pos$libresoc.v:126027$4897_Y - attribute \src "libresoc.v:126030.17-126030.104" - wire width 64 $pos$libresoc.v:126030$4901_Y - attribute \src "libresoc.v:126034.17-126034.102" - wire width 64 $pos$libresoc.v:126034$4906_Y - attribute \src "libresoc.v:126028.18-126028.114" - wire width 47 $sshl$libresoc.v:126028$4898_Y - attribute \src "libresoc.v:126029.18-126029.113" - wire width 27 $sshl$libresoc.v:126029$4899_Y - attribute \src "libresoc.v:126031.18-126031.113" - wire width 17 $sshl$libresoc.v:126031$4902_Y - attribute \src "libresoc.v:126032.18-126032.113" - wire width 17 $sshl$libresoc.v:126032$4903_Y - attribute \src "libresoc.v:126033.17-126033.109" - wire width 47 $sshl$libresoc.v:126033$4904_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $extend$libresoc.v:127633$4935_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $extend$libresoc.v:127634$4937_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $extend$libresoc.v:127637$4941_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $extend$libresoc.v:127641$4946_Y + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $pos$libresoc.v:127633$4936_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $pos$libresoc.v:127634$4938_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $pos$libresoc.v:127637$4942_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $pos$libresoc.v:127641$4947_Y + attribute \src "libresoc.v:127635.18-127635.114" + wire width 47 $sshl$libresoc.v:127635$4939_Y + attribute \src "libresoc.v:127636.18-127636.113" + wire width 27 $sshl$libresoc.v:127636$4940_Y + attribute \src "libresoc.v:127638.18-127638.113" + wire width 17 $sshl$libresoc.v:127638$4943_Y + attribute \src "libresoc.v:127639.18-127639.113" + wire width 17 $sshl$libresoc.v:127639$4944_Y + attribute \src "libresoc.v:127640.17-127640.109" + wire width 47 $sshl$libresoc.v:127640$4945_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125948.7-125948.15" + attribute \src "libresoc.v:127555.7-127555.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198091,80 +200511,80 @@ module \dec_bi$161 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126026$4894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127633$4935 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:126026$4894_Y + connect \Y $extend$libresoc.v:127633$4935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126027$4896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127634$4937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:126027$4896_Y + connect \Y $extend$libresoc.v:127634$4937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126030$4900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127637$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:126030$4900_Y + connect \Y $extend$libresoc.v:127637$4941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126034$4905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127641$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126034$4905_Y + connect \Y $extend$libresoc.v:127641$4946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126026$4895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127633$4936 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126026$4894_Y - connect \Y $pos$libresoc.v:126026$4895_Y + connect \A $extend$libresoc.v:127633$4935_Y + connect \Y $pos$libresoc.v:127633$4936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126027$4897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127634$4938 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126027$4896_Y - connect \Y $pos$libresoc.v:126027$4897_Y + connect \A $extend$libresoc.v:127634$4937_Y + connect \Y $pos$libresoc.v:127634$4938_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126030$4901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127637$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126030$4900_Y - connect \Y $pos$libresoc.v:126030$4901_Y + connect \A $extend$libresoc.v:127637$4941_Y + connect \Y $pos$libresoc.v:127637$4942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126034$4906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127641$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126034$4905_Y - connect \Y $pos$libresoc.v:126034$4906_Y + connect \A $extend$libresoc.v:127641$4946_Y + connect \Y $pos$libresoc.v:127641$4947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126028$4898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127635$4939 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198172,10 +200592,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126028$4898_Y + connect \Y $sshl$libresoc.v:127635$4939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126029$4899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127636$4940 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198183,10 +200603,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126029$4899_Y + connect \Y $sshl$libresoc.v:127636$4940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126031$4902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127638$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198194,10 +200614,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126031$4902_Y + connect \Y $sshl$libresoc.v:127638$4943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126032$4903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127639$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198205,10 +200625,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126032$4903_Y + connect \Y $sshl$libresoc.v:127639$4944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126033$4904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127640$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198216,28 +200636,28 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126033$4904_Y + connect \Y $sshl$libresoc.v:127640$4945_Y end - attribute \src "libresoc.v:125948.7-125948.20" - process $proc$libresoc.v:125948$4915 + attribute \src "libresoc.v:127555.7-127555.20" + process $proc$libresoc.v:127555$4956 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126036.3-126082.6" - process $proc$libresoc.v:126036$4907 + attribute \src "libresoc.v:127643.3-127689.6" + process $proc$libresoc.v:127643$4948 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126037.5-126037.29" + attribute \src "libresoc.v:127644.5-127644.29" switch \initial - attribute \src "libresoc.v:126037.9-126037.17" + attribute \src "libresoc.v:127644.9-127644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198285,18 +200705,18 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126083.3-126129.6" - process $proc$libresoc.v:126083$4908 + attribute \src "libresoc.v:127690.3-127736.6" + process $proc$libresoc.v:127690$4949 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126084.5-126084.29" + attribute \src "libresoc.v:127691.5-127691.29" switch \initial - attribute \src "libresoc.v:126084.9-126084.17" + attribute \src "libresoc.v:127691.9-127691.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198344,18 +200764,18 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126130.3-126140.6" - process $proc$libresoc.v:126130$4909 + attribute \src "libresoc.v:127737.3-127747.6" + process $proc$libresoc.v:127737$4950 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126131.5-126131.29" + attribute \src "libresoc.v:127738.5-127738.29" switch \initial - attribute \src "libresoc.v:126131.9-126131.17" + attribute \src "libresoc.v:127738.9-127738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -198367,18 +200787,18 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126141.3-126151.6" - process $proc$libresoc.v:126141$4910 + attribute \src "libresoc.v:127748.3-127758.6" + process $proc$libresoc.v:127748$4951 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126142.5-126142.29" + attribute \src "libresoc.v:127749.5-127749.29" switch \initial - attribute \src "libresoc.v:126142.9-126142.17" + attribute \src "libresoc.v:127749.9-127749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -198390,18 +200810,18 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126152.3-126162.6" - process $proc$libresoc.v:126152$4911 + attribute \src "libresoc.v:127759.3-127769.6" + process $proc$libresoc.v:127759$4952 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126153.5-126153.29" + attribute \src "libresoc.v:127760.5-127760.29" switch \initial - attribute \src "libresoc.v:126153.9-126153.17" + attribute \src "libresoc.v:127760.9-127760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -198413,18 +200833,18 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126163.3-126173.6" - process $proc$libresoc.v:126163$4912 + attribute \src "libresoc.v:127770.3-127780.6" + process $proc$libresoc.v:127770$4953 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126164.5-126164.29" + attribute \src "libresoc.v:127771.5-127771.29" switch \initial - attribute \src "libresoc.v:126164.9-126164.17" + attribute \src "libresoc.v:127771.9-127771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -198436,18 +200856,18 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126174.3-126184.6" - process $proc$libresoc.v:126174$4913 + attribute \src "libresoc.v:127781.3-127791.6" + process $proc$libresoc.v:127781$4954 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126175.5-126175.29" + attribute \src "libresoc.v:127782.5-127782.29" switch \initial - attribute \src "libresoc.v:126175.9-126175.17" + attribute \src "libresoc.v:127782.9-127782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -198459,18 +200879,18 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126185.3-126195.6" - process $proc$libresoc.v:126185$4914 + attribute \src "libresoc.v:127792.3-127802.6" + process $proc$libresoc.v:127792$4955 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126186.5-126186.29" + attribute \src "libresoc.v:127793.5-127793.29" switch \initial - attribute \src "libresoc.v:126186.9-126186.17" + attribute \src "libresoc.v:127793.9-127793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -198482,139 +200902,139 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126026$4895_Y - connect \$11 $pos$libresoc.v:126027$4897_Y - connect \$14 $sshl$libresoc.v:126028$4898_Y - connect \$17 $sshl$libresoc.v:126029$4899_Y - connect \$1 $pos$libresoc.v:126030$4901_Y - connect \$20 $sshl$libresoc.v:126031$4902_Y - connect \$23 $sshl$libresoc.v:126032$4903_Y - connect \$4 $sshl$libresoc.v:126033$4904_Y - connect \$3 $pos$libresoc.v:126034$4906_Y + connect \$9 $pos$libresoc.v:127633$4936_Y + connect \$11 $pos$libresoc.v:127634$4938_Y + connect \$14 $sshl$libresoc.v:127635$4939_Y + connect \$17 $sshl$libresoc.v:127636$4940_Y + connect \$1 $pos$libresoc.v:127637$4942_Y + connect \$20 $sshl$libresoc.v:127638$4943_Y + connect \$23 $sshl$libresoc.v:127639$4944_Y + connect \$4 $sshl$libresoc.v:127640$4945_Y + connect \$3 $pos$libresoc.v:127641$4947_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126204.1-126457.10" +attribute \src "libresoc.v:127811.1-128064.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:126431.3-126441.6" + attribute \src "libresoc.v:128038.3-128048.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126442.3-126452.6" + attribute \src "libresoc.v:128049.3-128059.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126293.3-126339.6" + attribute \src "libresoc.v:127900.3-127946.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126340.3-126386.6" + attribute \src "libresoc.v:127947.3-127993.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126205.7-126205.20" + attribute \src "libresoc.v:127812.7-127812.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126420.3-126430.6" + attribute \src "libresoc.v:128027.3-128037.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126387.3-126397.6" + attribute \src "libresoc.v:127994.3-128004.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126398.3-126408.6" + attribute \src "libresoc.v:128005.3-128015.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126409.3-126419.6" + attribute \src "libresoc.v:128016.3-128026.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126431.3-126441.6" + attribute \src "libresoc.v:128038.3-128048.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126442.3-126452.6" + attribute \src "libresoc.v:128049.3-128059.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126293.3-126339.6" + attribute \src "libresoc.v:127900.3-127946.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126340.3-126386.6" + attribute \src "libresoc.v:127947.3-127993.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126420.3-126430.6" + attribute \src "libresoc.v:128027.3-128037.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126387.3-126397.6" + attribute \src "libresoc.v:127994.3-128004.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126398.3-126408.6" + attribute \src "libresoc.v:128005.3-128015.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126409.3-126419.6" + attribute \src "libresoc.v:128016.3-128026.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126283.17-126283.110" - wire width 64 $extend$libresoc.v:126283$4916_Y - attribute \src "libresoc.v:126284.18-126284.113" - wire width 64 $extend$libresoc.v:126284$4918_Y - attribute \src "libresoc.v:126287.17-126287.110" - wire width 64 $extend$libresoc.v:126287$4922_Y - attribute \src "libresoc.v:126291.17-126291.102" - wire width 64 $extend$libresoc.v:126291$4927_Y - attribute \src "libresoc.v:126283.17-126283.110" - wire width 64 $pos$libresoc.v:126283$4917_Y - attribute \src "libresoc.v:126284.18-126284.113" - wire width 64 $pos$libresoc.v:126284$4919_Y - attribute \src "libresoc.v:126287.17-126287.110" - wire width 64 $pos$libresoc.v:126287$4923_Y - attribute \src "libresoc.v:126291.17-126291.102" - wire width 64 $pos$libresoc.v:126291$4928_Y - attribute \src "libresoc.v:126285.18-126285.120" - wire width 47 $sshl$libresoc.v:126285$4920_Y - attribute \src "libresoc.v:126286.18-126286.119" - wire width 27 $sshl$libresoc.v:126286$4921_Y - attribute \src "libresoc.v:126288.18-126288.119" - wire width 17 $sshl$libresoc.v:126288$4924_Y - attribute \src "libresoc.v:126289.18-126289.119" - wire width 17 $sshl$libresoc.v:126289$4925_Y - attribute \src "libresoc.v:126290.17-126290.109" - wire width 47 $sshl$libresoc.v:126290$4926_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $extend$libresoc.v:127890$4957_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $extend$libresoc.v:127891$4959_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $extend$libresoc.v:127894$4963_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $extend$libresoc.v:127898$4968_Y + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $pos$libresoc.v:127890$4958_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $pos$libresoc.v:127891$4960_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $pos$libresoc.v:127894$4964_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $pos$libresoc.v:127898$4969_Y + attribute \src "libresoc.v:127892.18-127892.120" + wire width 47 $sshl$libresoc.v:127892$4961_Y + attribute \src "libresoc.v:127893.18-127893.119" + wire width 27 $sshl$libresoc.v:127893$4962_Y + attribute \src "libresoc.v:127895.18-127895.119" + wire width 17 $sshl$libresoc.v:127895$4965_Y + attribute \src "libresoc.v:127896.18-127896.119" + wire width 17 $sshl$libresoc.v:127896$4966_Y + attribute \src "libresoc.v:127897.17-127897.109" + wire width 47 $sshl$libresoc.v:127897$4967_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126205.7-126205.15" + attribute \src "libresoc.v:127812.7-127812.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198631,80 +201051,80 @@ module \dec_bi$165 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126283$4916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127890$4957 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:126283$4916_Y + connect \Y $extend$libresoc.v:127890$4957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126284$4918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127891$4959 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:126284$4918_Y + connect \Y $extend$libresoc.v:127891$4959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126287$4922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127894$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:126287$4922_Y + connect \Y $extend$libresoc.v:127894$4963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126291$4927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127898$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126291$4927_Y + connect \Y $extend$libresoc.v:127898$4968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126283$4917 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127890$4958 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126283$4916_Y - connect \Y $pos$libresoc.v:126283$4917_Y + connect \A $extend$libresoc.v:127890$4957_Y + connect \Y $pos$libresoc.v:127890$4958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126284$4919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127891$4960 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126284$4918_Y - connect \Y $pos$libresoc.v:126284$4919_Y + connect \A $extend$libresoc.v:127891$4959_Y + connect \Y $pos$libresoc.v:127891$4960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126287$4923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127894$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126287$4922_Y - connect \Y $pos$libresoc.v:126287$4923_Y + connect \A $extend$libresoc.v:127894$4963_Y + connect \Y $pos$libresoc.v:127894$4964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126291$4928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127898$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126291$4927_Y - connect \Y $pos$libresoc.v:126291$4928_Y + connect \A $extend$libresoc.v:127898$4968_Y + connect \Y $pos$libresoc.v:127898$4969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126285$4920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127892$4961 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198712,10 +201132,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126285$4920_Y + connect \Y $sshl$libresoc.v:127892$4961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126286$4921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127893$4962 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198723,10 +201143,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126286$4921_Y + connect \Y $sshl$libresoc.v:127893$4962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126288$4924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127895$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198734,10 +201154,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126288$4924_Y + connect \Y $sshl$libresoc.v:127895$4965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126289$4925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127896$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198745,10 +201165,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126289$4925_Y + connect \Y $sshl$libresoc.v:127896$4966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126290$4926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127897$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198756,28 +201176,28 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126290$4926_Y + connect \Y $sshl$libresoc.v:127897$4967_Y end - attribute \src "libresoc.v:126205.7-126205.20" - process $proc$libresoc.v:126205$4937 + attribute \src "libresoc.v:127812.7-127812.20" + process $proc$libresoc.v:127812$4978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126293.3-126339.6" - process $proc$libresoc.v:126293$4929 + attribute \src "libresoc.v:127900.3-127946.6" + process $proc$libresoc.v:127900$4970 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126294.5-126294.29" + attribute \src "libresoc.v:127901.5-127901.29" switch \initial - attribute \src "libresoc.v:126294.9-126294.17" + attribute \src "libresoc.v:127901.9-127901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198825,18 +201245,18 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126340.3-126386.6" - process $proc$libresoc.v:126340$4930 + attribute \src "libresoc.v:127947.3-127993.6" + process $proc$libresoc.v:127947$4971 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126341.5-126341.29" + attribute \src "libresoc.v:127948.5-127948.29" switch \initial - attribute \src "libresoc.v:126341.9-126341.17" + attribute \src "libresoc.v:127948.9-127948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198884,18 +201304,18 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126387.3-126397.6" - process $proc$libresoc.v:126387$4931 + attribute \src "libresoc.v:127994.3-128004.6" + process $proc$libresoc.v:127994$4972 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126388.5-126388.29" + attribute \src "libresoc.v:127995.5-127995.29" switch \initial - attribute \src "libresoc.v:126388.9-126388.17" + attribute \src "libresoc.v:127995.9-127995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -198907,18 +201327,18 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126398.3-126408.6" - process $proc$libresoc.v:126398$4932 + attribute \src "libresoc.v:128005.3-128015.6" + process $proc$libresoc.v:128005$4973 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126399.5-126399.29" + attribute \src "libresoc.v:128006.5-128006.29" switch \initial - attribute \src "libresoc.v:126399.9-126399.17" + attribute \src "libresoc.v:128006.9-128006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -198930,18 +201350,18 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126409.3-126419.6" - process $proc$libresoc.v:126409$4933 + attribute \src "libresoc.v:128016.3-128026.6" + process $proc$libresoc.v:128016$4974 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126410.5-126410.29" + attribute \src "libresoc.v:128017.5-128017.29" switch \initial - attribute \src "libresoc.v:126410.9-126410.17" + attribute \src "libresoc.v:128017.9-128017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -198953,18 +201373,18 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126420.3-126430.6" - process $proc$libresoc.v:126420$4934 + attribute \src "libresoc.v:128027.3-128037.6" + process $proc$libresoc.v:128027$4975 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126421.5-126421.29" + attribute \src "libresoc.v:128028.5-128028.29" switch \initial - attribute \src "libresoc.v:126421.9-126421.17" + attribute \src "libresoc.v:128028.9-128028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -198976,18 +201396,18 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126431.3-126441.6" - process $proc$libresoc.v:126431$4935 + attribute \src "libresoc.v:128038.3-128048.6" + process $proc$libresoc.v:128038$4976 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126432.5-126432.29" + attribute \src "libresoc.v:128039.5-128039.29" switch \initial - attribute \src "libresoc.v:126432.9-126432.17" + attribute \src "libresoc.v:128039.9-128039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -198999,18 +201419,18 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126442.3-126452.6" - process $proc$libresoc.v:126442$4936 + attribute \src "libresoc.v:128049.3-128059.6" + process $proc$libresoc.v:128049$4977 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126443.5-126443.29" + attribute \src "libresoc.v:128050.5-128050.29" switch \initial - attribute \src "libresoc.v:126443.9-126443.17" + attribute \src "libresoc.v:128050.9-128050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -199022,139 +201442,139 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126283$4917_Y - connect \$11 $pos$libresoc.v:126284$4919_Y - connect \$14 $sshl$libresoc.v:126285$4920_Y - connect \$17 $sshl$libresoc.v:126286$4921_Y - connect \$1 $pos$libresoc.v:126287$4923_Y - connect \$20 $sshl$libresoc.v:126288$4924_Y - connect \$23 $sshl$libresoc.v:126289$4925_Y - connect \$4 $sshl$libresoc.v:126290$4926_Y - connect \$3 $pos$libresoc.v:126291$4928_Y + connect \$9 $pos$libresoc.v:127890$4958_Y + connect \$11 $pos$libresoc.v:127891$4960_Y + connect \$14 $sshl$libresoc.v:127892$4961_Y + connect \$17 $sshl$libresoc.v:127893$4962_Y + connect \$1 $pos$libresoc.v:127894$4964_Y + connect \$20 $sshl$libresoc.v:127895$4965_Y + connect \$23 $sshl$libresoc.v:127896$4966_Y + connect \$4 $sshl$libresoc.v:127897$4967_Y + connect \$3 $pos$libresoc.v:127898$4969_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126461.1-126714.10" +attribute \src "libresoc.v:128068.1-128321.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:126688.3-126698.6" + attribute \src "libresoc.v:128295.3-128305.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126699.3-126709.6" + attribute \src "libresoc.v:128306.3-128316.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126550.3-126596.6" + attribute \src "libresoc.v:128157.3-128203.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126597.3-126643.6" + attribute \src "libresoc.v:128204.3-128250.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126462.7-126462.20" + attribute \src "libresoc.v:128069.7-128069.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126677.3-126687.6" + attribute \src "libresoc.v:128284.3-128294.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126644.3-126654.6" + attribute \src "libresoc.v:128251.3-128261.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126655.3-126665.6" + attribute \src "libresoc.v:128262.3-128272.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126666.3-126676.6" + attribute \src "libresoc.v:128273.3-128283.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126688.3-126698.6" + attribute \src "libresoc.v:128295.3-128305.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126699.3-126709.6" + attribute \src "libresoc.v:128306.3-128316.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126550.3-126596.6" + attribute \src "libresoc.v:128157.3-128203.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126597.3-126643.6" + attribute \src "libresoc.v:128204.3-128250.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126677.3-126687.6" + attribute \src "libresoc.v:128284.3-128294.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126644.3-126654.6" + attribute \src "libresoc.v:128251.3-128261.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126655.3-126665.6" + attribute \src "libresoc.v:128262.3-128272.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126666.3-126676.6" + attribute \src "libresoc.v:128273.3-128283.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126540.17-126540.105" - wire width 64 $extend$libresoc.v:126540$4938_Y - attribute \src "libresoc.v:126541.18-126541.108" - wire width 64 $extend$libresoc.v:126541$4940_Y - attribute \src "libresoc.v:126544.17-126544.105" - wire width 64 $extend$libresoc.v:126544$4944_Y - attribute \src "libresoc.v:126548.17-126548.102" - wire width 64 $extend$libresoc.v:126548$4949_Y - attribute \src "libresoc.v:126540.17-126540.105" - wire width 64 $pos$libresoc.v:126540$4939_Y - attribute \src "libresoc.v:126541.18-126541.108" - wire width 64 $pos$libresoc.v:126541$4941_Y - attribute \src "libresoc.v:126544.17-126544.105" - wire width 64 $pos$libresoc.v:126544$4945_Y - attribute \src "libresoc.v:126548.17-126548.102" - wire width 64 $pos$libresoc.v:126548$4950_Y - attribute \src "libresoc.v:126542.18-126542.115" - wire width 47 $sshl$libresoc.v:126542$4942_Y - attribute \src "libresoc.v:126543.18-126543.114" - wire width 27 $sshl$libresoc.v:126543$4943_Y - attribute \src "libresoc.v:126545.18-126545.114" - wire width 17 $sshl$libresoc.v:126545$4946_Y - attribute \src "libresoc.v:126546.18-126546.114" - wire width 17 $sshl$libresoc.v:126546$4947_Y - attribute \src "libresoc.v:126547.17-126547.109" - wire width 47 $sshl$libresoc.v:126547$4948_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $extend$libresoc.v:128147$4979_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $extend$libresoc.v:128148$4981_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $extend$libresoc.v:128151$4985_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $extend$libresoc.v:128155$4990_Y + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $pos$libresoc.v:128147$4980_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $pos$libresoc.v:128148$4982_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $pos$libresoc.v:128151$4986_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $pos$libresoc.v:128155$4991_Y + attribute \src "libresoc.v:128149.18-128149.115" + wire width 47 $sshl$libresoc.v:128149$4983_Y + attribute \src "libresoc.v:128150.18-128150.114" + wire width 27 $sshl$libresoc.v:128150$4984_Y + attribute \src "libresoc.v:128152.18-128152.114" + wire width 17 $sshl$libresoc.v:128152$4987_Y + attribute \src "libresoc.v:128153.18-128153.114" + wire width 17 $sshl$libresoc.v:128153$4988_Y + attribute \src "libresoc.v:128154.17-128154.109" + wire width 47 $sshl$libresoc.v:128154$4989_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126462.7-126462.15" + attribute \src "libresoc.v:128069.7-128069.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -199171,80 +201591,80 @@ module \dec_bi$170 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126540$4938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128147$4979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:126540$4938_Y + connect \Y $extend$libresoc.v:128147$4979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126541$4940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128148$4981 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:126541$4940_Y + connect \Y $extend$libresoc.v:128148$4981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126544$4944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128151$4985 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:126544$4944_Y + connect \Y $extend$libresoc.v:128151$4985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126548$4949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:128155$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126548$4949_Y + connect \Y $extend$libresoc.v:128155$4990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126540$4939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128147$4980 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126540$4938_Y - connect \Y $pos$libresoc.v:126540$4939_Y + connect \A $extend$libresoc.v:128147$4979_Y + connect \Y $pos$libresoc.v:128147$4980_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126541$4941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128148$4982 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126541$4940_Y - connect \Y $pos$libresoc.v:126541$4941_Y + connect \A $extend$libresoc.v:128148$4981_Y + connect \Y $pos$libresoc.v:128148$4982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126544$4945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128151$4986 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126544$4944_Y - connect \Y $pos$libresoc.v:126544$4945_Y + connect \A $extend$libresoc.v:128151$4985_Y + connect \Y $pos$libresoc.v:128151$4986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126548$4950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:128155$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126548$4949_Y - connect \Y $pos$libresoc.v:126548$4950_Y + connect \A $extend$libresoc.v:128155$4990_Y + connect \Y $pos$libresoc.v:128155$4991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126542$4942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:128149$4983 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199252,10 +201672,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126542$4942_Y + connect \Y $sshl$libresoc.v:128149$4983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126543$4943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:128150$4984 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -199263,10 +201683,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126543$4943_Y + connect \Y $sshl$libresoc.v:128150$4984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126545$4946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:128152$4987 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199274,10 +201694,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126545$4946_Y + connect \Y $sshl$libresoc.v:128152$4987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126546$4947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:128153$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199285,10 +201705,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126546$4947_Y + connect \Y $sshl$libresoc.v:128153$4988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126547$4948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:128154$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199296,28 +201716,28 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126547$4948_Y + connect \Y $sshl$libresoc.v:128154$4989_Y end - attribute \src "libresoc.v:126462.7-126462.20" - process $proc$libresoc.v:126462$4959 + attribute \src "libresoc.v:128069.7-128069.20" + process $proc$libresoc.v:128069$5000 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126550.3-126596.6" - process $proc$libresoc.v:126550$4951 + attribute \src "libresoc.v:128157.3-128203.6" + process $proc$libresoc.v:128157$4992 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126551.5-126551.29" + attribute \src "libresoc.v:128158.5-128158.29" switch \initial - attribute \src "libresoc.v:126551.9-126551.17" + attribute \src "libresoc.v:128158.9-128158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199365,18 +201785,18 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126597.3-126643.6" - process $proc$libresoc.v:126597$4952 + attribute \src "libresoc.v:128204.3-128250.6" + process $proc$libresoc.v:128204$4993 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126598.5-126598.29" + attribute \src "libresoc.v:128205.5-128205.29" switch \initial - attribute \src "libresoc.v:126598.9-126598.17" + attribute \src "libresoc.v:128205.9-128205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199424,18 +201844,18 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126644.3-126654.6" - process $proc$libresoc.v:126644$4953 + attribute \src "libresoc.v:128251.3-128261.6" + process $proc$libresoc.v:128251$4994 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126645.5-126645.29" + attribute \src "libresoc.v:128252.5-128252.29" switch \initial - attribute \src "libresoc.v:126645.9-126645.17" + attribute \src "libresoc.v:128252.9-128252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -199447,18 +201867,18 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126655.3-126665.6" - process $proc$libresoc.v:126655$4954 + attribute \src "libresoc.v:128262.3-128272.6" + process $proc$libresoc.v:128262$4995 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126656.5-126656.29" + attribute \src "libresoc.v:128263.5-128263.29" switch \initial - attribute \src "libresoc.v:126656.9-126656.17" + attribute \src "libresoc.v:128263.9-128263.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -199470,18 +201890,18 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126666.3-126676.6" - process $proc$libresoc.v:126666$4955 + attribute \src "libresoc.v:128273.3-128283.6" + process $proc$libresoc.v:128273$4996 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126667.5-126667.29" + attribute \src "libresoc.v:128274.5-128274.29" switch \initial - attribute \src "libresoc.v:126667.9-126667.17" + attribute \src "libresoc.v:128274.9-128274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -199493,18 +201913,18 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126677.3-126687.6" - process $proc$libresoc.v:126677$4956 + attribute \src "libresoc.v:128284.3-128294.6" + process $proc$libresoc.v:128284$4997 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126678.5-126678.29" + attribute \src "libresoc.v:128285.5-128285.29" switch \initial - attribute \src "libresoc.v:126678.9-126678.17" + attribute \src "libresoc.v:128285.9-128285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -199516,18 +201936,18 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126688.3-126698.6" - process $proc$libresoc.v:126688$4957 + attribute \src "libresoc.v:128295.3-128305.6" + process $proc$libresoc.v:128295$4998 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126689.5-126689.29" + attribute \src "libresoc.v:128296.5-128296.29" switch \initial - attribute \src "libresoc.v:126689.9-126689.17" + attribute \src "libresoc.v:128296.9-128296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -199539,18 +201959,18 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126699.3-126709.6" - process $proc$libresoc.v:126699$4958 + attribute \src "libresoc.v:128306.3-128316.6" + process $proc$libresoc.v:128306$4999 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126700.5-126700.29" + attribute \src "libresoc.v:128307.5-128307.29" switch \initial - attribute \src "libresoc.v:126700.9-126700.17" + attribute \src "libresoc.v:128307.9-128307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -199562,41 +201982,41 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126540$4939_Y - connect \$11 $pos$libresoc.v:126541$4941_Y - connect \$14 $sshl$libresoc.v:126542$4942_Y - connect \$17 $sshl$libresoc.v:126543$4943_Y - connect \$1 $pos$libresoc.v:126544$4945_Y - connect \$20 $sshl$libresoc.v:126545$4946_Y - connect \$23 $sshl$libresoc.v:126546$4947_Y - connect \$4 $sshl$libresoc.v:126547$4948_Y - connect \$3 $pos$libresoc.v:126548$4950_Y + connect \$9 $pos$libresoc.v:128147$4980_Y + connect \$11 $pos$libresoc.v:128148$4982_Y + connect \$14 $sshl$libresoc.v:128149$4983_Y + connect \$17 $sshl$libresoc.v:128150$4984_Y + connect \$1 $pos$libresoc.v:128151$4986_Y + connect \$20 $sshl$libresoc.v:128152$4987_Y + connect \$23 $sshl$libresoc.v:128153$4988_Y + connect \$4 $sshl$libresoc.v:128154$4989_Y + connect \$3 $pos$libresoc.v:128155$4991_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126718.1-126766.10" +attribute \src "libresoc.v:128325.1-128373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:126719.7-126719.20" + attribute \src "libresoc.v:128326.7-128326.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126736.3-126750.6" + attribute \src "libresoc.v:128343.3-128357.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:126751.3-126765.6" + attribute \src "libresoc.v:128358.3-128372.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:126736.3-126750.6" + attribute \src "libresoc.v:128343.3-128357.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:126751.3-126765.6" + attribute \src "libresoc.v:128358.3-128372.6" wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS - attribute \src "libresoc.v:126719.7-126719.15" + attribute \src "libresoc.v:128326.7-128326.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c @@ -199606,28 +202026,28 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:126719.7-126719.20" - process $proc$libresoc.v:126719$4962 + attribute \src "libresoc.v:128326.7-128326.20" + process $proc$libresoc.v:128326$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126736.3-126750.6" - process $proc$libresoc.v:126736$4960 + attribute \src "libresoc.v:128343.3-128357.6" + process $proc$libresoc.v:128343$5001 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:126737.5-126737.29" + attribute \src "libresoc.v:128344.5-128344.29" switch \initial - attribute \src "libresoc.v:126737.9-126737.17" + attribute \src "libresoc.v:128344.9-128344.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199643,18 +202063,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:126751.3-126765.6" - process $proc$libresoc.v:126751$4961 + attribute \src "libresoc.v:128358.3-128372.6" + process $proc$libresoc.v:128358$5002 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:126752.5-126752.29" + attribute \src "libresoc.v:128359.5-128359.29" switch \initial - attribute \src "libresoc.v:126752.9-126752.17" + attribute \src "libresoc.v:128359.9-128359.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199671,90 +202091,90 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:126770.1-127102.10" +attribute \src "libresoc.v:128377.1-128709.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:127022.3-127052.6" + attribute \src "libresoc.v:128629.3-128659.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127053.3-127063.6" + attribute \src "libresoc.v:128660.3-128670.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126955.3-126965.6" + attribute \src "libresoc.v:128562.3-128572.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127064.3-127074.6" + attribute \src "libresoc.v:128671.3-128681.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126985.3-126995.6" + attribute \src "libresoc.v:128592.3-128602.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126924.3-126954.6" + attribute \src "libresoc.v:128531.3-128561.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:126996.3-127006.6" + attribute \src "libresoc.v:128603.3-128613.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126771.7-126771.20" + attribute \src "libresoc.v:128378.7-128378.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127075.3-127085.6" + attribute \src "libresoc.v:128682.3-128692.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127007.3-127021.6" + attribute \src "libresoc.v:128614.3-128628.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:127022.3-127052.6" + attribute \src "libresoc.v:128629.3-128659.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127053.3-127063.6" + attribute \src "libresoc.v:128660.3-128670.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126955.3-126965.6" + attribute \src "libresoc.v:128562.3-128572.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127064.3-127074.6" + attribute \src "libresoc.v:128671.3-128681.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126985.3-126995.6" + attribute \src "libresoc.v:128592.3-128602.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126924.3-126954.6" + attribute \src "libresoc.v:128531.3-128561.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:126996.3-127006.6" + attribute \src "libresoc.v:128603.3-128613.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127075.3-127085.6" + attribute \src "libresoc.v:128682.3-128692.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127007.3-127021.6" + attribute \src "libresoc.v:128614.3-128628.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:126917.17-126917.112" - wire $and$libresoc.v:126917$4964_Y - attribute \src "libresoc.v:126919.17-126919.112" - wire $and$libresoc.v:126919$4966_Y - attribute \src "libresoc.v:126916.17-126916.117" - wire $eq$libresoc.v:126916$4963_Y - attribute \src "libresoc.v:126918.17-126918.117" - wire $eq$libresoc.v:126918$4965_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "libresoc.v:128524.17-128524.112" + wire $and$libresoc.v:128524$5005_Y + attribute \src "libresoc.v:128526.17-128526.112" + wire $and$libresoc.v:128526$5007_Y + attribute \src "libresoc.v:128523.17-128523.117" + wire $eq$libresoc.v:128523$5004_Y + attribute \src "libresoc.v:128525.17-128525.117" + wire $eq$libresoc.v:128525$5006_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 17 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 5 \cr_bitfield @@ -199772,9 +202192,9 @@ module \dec_cr_in wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:126771.7-126771.15" + attribute \src "libresoc.v:128378.7-128378.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -199851,9 +202271,9 @@ module \dec_cr_in attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 18 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i @@ -199868,12 +202288,12 @@ module \dec_cr_in attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $and $and$libresoc.v:126917$4964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128524$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199881,10 +202301,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:126917$4964_Y + connect \Y $and$libresoc.v:128524$5005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $and $and$libresoc.v:126919$4966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128526$5007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199892,10 +202312,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:126919$4966_Y + connect \Y $and$libresoc.v:128526$5007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $eq $eq$libresoc.v:126916$4963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128523$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -199903,10 +202323,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126916$4963_Y + connect \Y $eq$libresoc.v:128523$5004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $eq $eq$libresoc.v:126918$4965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128525$5006 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -199914,34 +202334,34 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126918$4965_Y + connect \Y $eq$libresoc.v:128525$5006_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126920.9-126923.4" + attribute \src "libresoc.v:128527.9-128530.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:126771.7-126771.20" - process $proc$libresoc.v:126771$4978 + attribute \src "libresoc.v:128378.7-128378.20" + process $proc$libresoc.v:128378$5019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126924.3-126954.6" - process $proc$libresoc.v:126924$4967 + attribute \src "libresoc.v:128531.3-128561.6" + process $proc$libresoc.v:128531$5008 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126925.5-126925.29" + attribute \src "libresoc.v:128532.5-128532.29" switch \initial - attribute \src "libresoc.v:126925.9-126925.17" + attribute \src "libresoc.v:128532.9-128532.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -199973,18 +202393,18 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:126955.3-126965.6" - process $proc$libresoc.v:126955$4968 + attribute \src "libresoc.v:128562.3-128572.6" + process $proc$libresoc.v:128562$5009 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126956.5-126956.29" + attribute \src "libresoc.v:128563.5-128563.29" switch \initial - attribute \src "libresoc.v:126956.9-126956.17" + attribute \src "libresoc.v:128563.9-128563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -199996,24 +202416,24 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:126966.3-126984.6" - process $proc$libresoc.v:126966$4969 + attribute \src "libresoc.v:128573.3-128591.6" + process $proc$libresoc.v:128573$5010 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:126967.5-126967.29" + attribute \src "libresoc.v:128574.5-128574.29" switch \initial - attribute \src "libresoc.v:126967.9-126967.17" + attribute \src "libresoc.v:128574.9-128574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200030,18 +202450,18 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:126985.3-126995.6" - process $proc$libresoc.v:126985$4970 + attribute \src "libresoc.v:128592.3-128602.6" + process $proc$libresoc.v:128592$5011 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126986.5-126986.29" + attribute \src "libresoc.v:128593.5-128593.29" switch \initial - attribute \src "libresoc.v:126986.9-126986.17" + attribute \src "libresoc.v:128593.9-128593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200053,18 +202473,18 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:126996.3-127006.6" - process $proc$libresoc.v:126996$4971 + attribute \src "libresoc.v:128603.3-128613.6" + process $proc$libresoc.v:128603$5012 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126997.5-126997.29" + attribute \src "libresoc.v:128604.5-128604.29" switch \initial - attribute \src "libresoc.v:126997.9-126997.17" + attribute \src "libresoc.v:128604.9-128604.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -200076,18 +202496,18 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:127007.3-127021.6" - process $proc$libresoc.v:127007$4972 + attribute \src "libresoc.v:128614.3-128628.6" + process $proc$libresoc.v:128614$5013 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:127008.5-127008.29" + attribute \src "libresoc.v:128615.5-128615.29" switch \initial - attribute \src "libresoc.v:127008.9-127008.17" + attribute \src "libresoc.v:128615.9-128615.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200103,18 +202523,18 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:127022.3-127052.6" - process $proc$libresoc.v:127022$4973 + attribute \src "libresoc.v:128629.3-128659.6" + process $proc$libresoc.v:128629$5014 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127023.5-127023.29" + attribute \src "libresoc.v:128630.5-128630.29" switch \initial - attribute \src "libresoc.v:127023.9-127023.17" + attribute \src "libresoc.v:128630.9-128630.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200146,18 +202566,18 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:127053.3-127063.6" - process $proc$libresoc.v:127053$4974 + attribute \src "libresoc.v:128660.3-128670.6" + process $proc$libresoc.v:128660$5015 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127054.5-127054.29" + attribute \src "libresoc.v:128661.5-128661.29" switch \initial - attribute \src "libresoc.v:127054.9-127054.17" + attribute \src "libresoc.v:128661.9-128661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200169,18 +202589,18 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:127064.3-127074.6" - process $proc$libresoc.v:127064$4975 + attribute \src "libresoc.v:128671.3-128681.6" + process $proc$libresoc.v:128671$5016 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127065.5-127065.29" + attribute \src "libresoc.v:128672.5-128672.29" switch \initial - attribute \src "libresoc.v:127065.9-127065.17" + attribute \src "libresoc.v:128672.9-128672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200192,18 +202612,18 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:127075.3-127085.6" - process $proc$libresoc.v:127075$4976 + attribute \src "libresoc.v:128682.3-128692.6" + process $proc$libresoc.v:128682$5017 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127076.5-127076.29" + attribute \src "libresoc.v:128683.5-128683.29" switch \initial - attribute \src "libresoc.v:127076.9-127076.17" + attribute \src "libresoc.v:128683.9-128683.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -200215,24 +202635,24 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:127086.3-127101.6" - process $proc$libresoc.v:127086$4977 + attribute \src "libresoc.v:128693.3-128708.6" + process $proc$libresoc.v:128693$5018 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127087.5-127087.29" + attribute \src "libresoc.v:128694.5-128694.29" switch \initial - attribute \src "libresoc.v:127087.9-127087.17" + attribute \src "libresoc.v:128694.9-128694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200247,69 +202667,69 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:126916$4963_Y - connect \$3 $and$libresoc.v:126917$4964_Y - connect \$5 $eq$libresoc.v:126918$4965_Y - connect \$7 $and$libresoc.v:126919$4966_Y + connect \$1 $eq$libresoc.v:128523$5004_Y + connect \$3 $and$libresoc.v:128524$5005_Y + connect \$5 $eq$libresoc.v:128525$5006_Y + connect \$7 $and$libresoc.v:128526$5007_Y end -attribute \src "libresoc.v:127106.1-127376.10" +attribute \src "libresoc.v:128713.1-128983.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:127286.3-127308.6" + attribute \src "libresoc.v:128893.3-128915.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127237.3-127259.6" + attribute \src "libresoc.v:128844.3-128866.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:127260.3-127270.6" + attribute \src "libresoc.v:128867.3-128877.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127107.7-127107.20" + attribute \src "libresoc.v:128714.7-128714.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127309.3-127319.6" + attribute \src "libresoc.v:128916.3-128926.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127271.3-127285.6" + attribute \src "libresoc.v:128878.3-128892.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:127286.3-127308.6" + attribute \src "libresoc.v:128893.3-128915.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127237.3-127259.6" + attribute \src "libresoc.v:128844.3-128866.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:127260.3-127270.6" + attribute \src "libresoc.v:128867.3-128877.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127309.3-127319.6" + attribute \src "libresoc.v:128916.3-128926.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127271.3-127285.6" + attribute \src "libresoc.v:128878.3-128892.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:127230.17-127230.117" - wire $eq$libresoc.v:127230$4979_Y - attribute \src "libresoc.v:127231.17-127231.117" - wire $eq$libresoc.v:127231$4980_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "libresoc.v:128837.17-128837.117" + wire $eq$libresoc.v:128837$5020_Y + attribute \src "libresoc.v:128838.17-128838.117" + wire $eq$libresoc.v:128838$5021_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 9 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \cr_bitfield @@ -200319,9 +202739,9 @@ module \dec_cr_out wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:127107.7-127107.15" + attribute \src "libresoc.v:128714.7-128714.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -200398,9 +202818,9 @@ module \dec_cr_out attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 11 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:637" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:638" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o @@ -200408,7 +202828,7 @@ module \dec_cr_out wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -200417,12 +202837,12 @@ module \dec_cr_out attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:599" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" - cell $eq $eq$libresoc.v:127230$4979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128837$5020 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -200430,10 +202850,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:127230$4979_Y + connect \Y $eq$libresoc.v:128837$5020_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" - cell $eq $eq$libresoc.v:127231$4980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128838$5021 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -200441,35 +202861,35 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:127231$4980_Y + connect \Y $eq$libresoc.v:128838$5021_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127232.15-127236.4" + attribute \src "libresoc.v:128839.15-128843.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:127107.7-127107.20" - process $proc$libresoc.v:127107$4988 + attribute \src "libresoc.v:128714.7-128714.20" + process $proc$libresoc.v:128714$5029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127237.3-127259.6" - process $proc$libresoc.v:127237$4981 + attribute \src "libresoc.v:128844.3-128866.6" + process $proc$libresoc.v:128844$5022 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127238.5-127238.29" + attribute \src "libresoc.v:128845.5-128845.29" switch \initial - attribute \src "libresoc.v:127238.9-127238.17" + attribute \src "libresoc.v:128845.9-128845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200493,18 +202913,18 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:127260.3-127270.6" - process $proc$libresoc.v:127260$4982 + attribute \src "libresoc.v:128867.3-128877.6" + process $proc$libresoc.v:128867$5023 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127261.5-127261.29" + attribute \src "libresoc.v:128868.5-128868.29" switch \initial - attribute \src "libresoc.v:127261.9-127261.17" + attribute \src "libresoc.v:128868.9-128868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200516,18 +202936,18 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:127271.3-127285.6" - process $proc$libresoc.v:127271$4983 + attribute \src "libresoc.v:128878.3-128892.6" + process $proc$libresoc.v:128878$5024 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:127272.5-127272.29" + attribute \src "libresoc.v:128879.5-128879.29" switch \initial - attribute \src "libresoc.v:127272.9-127272.17" + attribute \src "libresoc.v:128879.9-128879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200543,18 +202963,18 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:127286.3-127308.6" - process $proc$libresoc.v:127286$4984 + attribute \src "libresoc.v:128893.3-128915.6" + process $proc$libresoc.v:128893$5025 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127287.5-127287.29" + attribute \src "libresoc.v:128894.5-128894.29" switch \initial - attribute \src "libresoc.v:127287.9-127287.17" + attribute \src "libresoc.v:128894.9-128894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200578,18 +202998,18 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:127309.3-127319.6" - process $proc$libresoc.v:127309$4985 + attribute \src "libresoc.v:128916.3-128926.6" + process $proc$libresoc.v:128916$5026 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127310.5-127310.29" + attribute \src "libresoc.v:128917.5-128917.29" switch \initial - attribute \src "libresoc.v:127310.9-127310.17" + attribute \src "libresoc.v:128917.9-128917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200601,30 +203021,30 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:127320.3-127340.6" - process $proc$libresoc.v:127320$4986 + attribute \src "libresoc.v:128927.3-128947.6" + process $proc$libresoc.v:128927$5027 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127321.5-127321.29" + attribute \src "libresoc.v:128928.5-128928.29" switch \initial - attribute \src "libresoc.v:127321.9-127321.17" + attribute \src "libresoc.v:128928.9-128928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200642,36 +203062,36 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:127341.3-127375.6" - process $proc$libresoc.v:127341$4987 + attribute \src "libresoc.v:128948.3-128982.6" + process $proc$libresoc.v:128948$5028 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:127342.5-127342.29" + attribute \src "libresoc.v:128949.5-128949.29" switch \initial - attribute \src "libresoc.v:127342.9-127342.17" + attribute \src "libresoc.v:128949.9-128949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:644" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200698,95 +203118,95 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:127230$4979_Y - connect \$3 $eq$libresoc.v:127231$4980_Y + connect \$1 $eq$libresoc.v:128837$5020_Y + connect \$3 $eq$libresoc.v:128838$5021_Y end -attribute \src "libresoc.v:127380.1-127865.10" +attribute \src "libresoc.v:128987.1-129472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:127381.7-127381.20" + attribute \src "libresoc.v:128988.7-128988.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127752.3-127766.6" + attribute \src "libresoc.v:129359.3-129373.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:127767.3-127781.6" + attribute \src "libresoc.v:129374.3-129388.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:127782.3-127792.6" + attribute \src "libresoc.v:129389.3-129399.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:127752.3-127766.6" + attribute \src "libresoc.v:129359.3-129373.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:127767.3-127781.6" + attribute \src "libresoc.v:129374.3-129388.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:127782.3-127792.6" + attribute \src "libresoc.v:129389.3-129399.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:127741.17-127741.117" - wire $eq$libresoc.v:127741$4989_Y - attribute \src "libresoc.v:127742.17-127742.117" - wire $eq$libresoc.v:127742$4990_Y - attribute \src "libresoc.v:127743.17-127743.117" - wire $eq$libresoc.v:127743$4991_Y - attribute \src "libresoc.v:127744.17-127744.104" - wire $not$libresoc.v:127744$4992_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "libresoc.v:129348.17-129348.117" + wire $eq$libresoc.v:129348$5030_Y + attribute \src "libresoc.v:129349.17-129349.117" + wire $eq$libresoc.v:129349$5031_Y + attribute \src "libresoc.v:129350.17-129350.117" + wire $eq$libresoc.v:129350$5032_Y + attribute \src "libresoc.v:129351.17-129351.104" + wire $not$libresoc.v:129351$5033_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 9 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \fast_o_ok - attribute \src "libresoc.v:127381.7-127381.15" + attribute \src "libresoc.v:128988.7-128988.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -200863,7 +203283,7 @@ module \dec_o attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 3 \reg_o @@ -200875,9 +203295,9 @@ module \dec_o attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -201001,7 +203421,7 @@ module \dec_o wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -201121,8 +203541,8 @@ module \dec_o wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127741$4989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129348$5030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201130,10 +203550,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127741$4989_Y + connect \Y $eq$libresoc.v:129348$5030_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127742$4990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129349$5031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201141,10 +203561,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127742$4990_Y + connect \Y $eq$libresoc.v:129349$5031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127743$4991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129350$5032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201152,18 +203572,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127743$4991_Y + connect \Y $eq$libresoc.v:129350$5032_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - cell $not $not$libresoc.v:127744$4992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + cell $not $not$libresoc.v:129351$5033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:127744$4992_Y + connect \Y $not$libresoc.v:129351$5033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127745.16-127751.4" + attribute \src "libresoc.v:129352.16-129358.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -201171,26 +203591,26 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:127381.7-127381.20" - process $proc$libresoc.v:127381$4999 + attribute \src "libresoc.v:128988.7-128988.20" + process $proc$libresoc.v:128988$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127752.3-127766.6" - process $proc$libresoc.v:127752$4993 + attribute \src "libresoc.v:129359.3-129373.6" + process $proc$libresoc.v:129359$5034 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:127753.5-127753.29" + attribute \src "libresoc.v:129360.5-129360.29" switch \initial - attribute \src "libresoc.v:127753.9-127753.17" + attribute \src "libresoc.v:129360.9-129360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -201206,18 +203626,18 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:127767.3-127781.6" - process $proc$libresoc.v:127767$4994 + attribute \src "libresoc.v:129374.3-129388.6" + process $proc$libresoc.v:129374$5035 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:127768.5-127768.29" + attribute \src "libresoc.v:129375.5-129375.29" switch \initial - attribute \src "libresoc.v:127768.9-127768.17" + attribute \src "libresoc.v:129375.9-129375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -201233,18 +203653,18 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:127782.3-127792.6" - process $proc$libresoc.v:127782$4995 + attribute \src "libresoc.v:129389.3-129399.6" + process $proc$libresoc.v:129389$5036 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:127783.5-127783.29" + attribute \src "libresoc.v:129390.5-129390.29" switch \initial - attribute \src "libresoc.v:127783.9-127783.17" + attribute \src "libresoc.v:129390.9-129390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201256,24 +203676,24 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:127793.3-127808.6" - process $proc$libresoc.v:127793$4996 + attribute \src "libresoc.v:129400.3-129415.6" + process $proc$libresoc.v:129400$5037 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127794.5-127794.29" + attribute \src "libresoc.v:129401.5-129401.29" switch \initial - attribute \src "libresoc.v:127794.9-127794.17" + attribute \src "libresoc.v:129401.9-129401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201288,21 +203708,21 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:127809.3-127825.6" - process $proc$libresoc.v:127809$4997 + attribute \src "libresoc.v:129416.3-129432.6" + process $proc$libresoc.v:129416$5038 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:127810.5-127810.29" + attribute \src "libresoc.v:129417.5-129417.29" switch \initial - attribute \src "libresoc.v:127810.9-127810.17" + attribute \src "libresoc.v:129417.9-129417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201310,7 +203730,7 @@ module \dec_o assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201329,8 +203749,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:127826.3-127864.6" - process $proc$libresoc.v:127826$4998 + attribute \src "libresoc.v:129433.3-129471.6" + process $proc$libresoc.v:129433$5039 assign { } { } assign { } { } assign { } { } @@ -201339,13 +203759,13 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:127827.5-127827.29" + attribute \src "libresoc.v:129434.5-129434.29" switch \initial - attribute \src "libresoc.v:127827.9-127827.17" + attribute \src "libresoc.v:129434.9-129434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201353,7 +203773,7 @@ module \dec_o assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201368,7 +203788,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -201376,7 +203796,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201402,53 +203822,53 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:127741$4989_Y - connect \$3 $eq$libresoc.v:127742$4990_Y - connect \$5 $eq$libresoc.v:127743$4991_Y - connect \$7 $not$libresoc.v:127744$4992_Y + connect \$1 $eq$libresoc.v:129348$5030_Y + connect \$3 $eq$libresoc.v:129349$5031_Y + connect \$5 $eq$libresoc.v:129350$5032_Y + connect \$7 $not$libresoc.v:129351$5033_Y end -attribute \src "libresoc.v:127869.1-128037.10" +attribute \src "libresoc.v:129476.1-129644.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:127870.7-127870.20" + attribute \src "libresoc.v:129477.7-129477.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127977.3-127986.6" + attribute \src "libresoc.v:129584.3-129593.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:127987.3-127996.6" + attribute \src "libresoc.v:129594.3-129603.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:127977.3-127986.6" + attribute \src "libresoc.v:129584.3-129593.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:127987.3-127996.6" + attribute \src "libresoc.v:129594.3-129603.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:127975.17-127975.108" - wire $eq$libresoc.v:127975$5000_Y - attribute \src "libresoc.v:127976.17-127976.108" - wire $eq$libresoc.v:127976$5001_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "libresoc.v:129582.17-129582.108" + wire $eq$libresoc.v:129582$5041_Y + attribute \src "libresoc.v:129583.17-129583.108" + wire $eq$libresoc.v:129583$5042_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:127870.7-127870.15" + attribute \src "libresoc.v:129477.7-129477.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201525,9 +203945,9 @@ module \dec_o2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_o2 @@ -201538,10 +203958,10 @@ module \dec_o2 attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" - cell $eq $eq$libresoc.v:127975$5000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129582$5041 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -201549,10 +203969,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:127975$5000_Y + connect \Y $eq$libresoc.v:129582$5041_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" - cell $eq $eq$libresoc.v:127976$5001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129583$5042 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -201560,28 +203980,28 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:127976$5001_Y + connect \Y $eq$libresoc.v:129583$5042_Y end - attribute \src "libresoc.v:127870.7-127870.20" - process $proc$libresoc.v:127870$5006 + attribute \src "libresoc.v:129477.7-129477.20" + process $proc$libresoc.v:129477$5047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127977.3-127986.6" - process $proc$libresoc.v:127977$5002 + attribute \src "libresoc.v:129584.3-129593.6" + process $proc$libresoc.v:129584$5043 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:127978.5-127978.29" + attribute \src "libresoc.v:129585.5-129585.29" switch \initial - attribute \src "libresoc.v:127978.9-127978.17" + attribute \src "libresoc.v:129585.9-129585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201593,18 +204013,18 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:127987.3-127996.6" - process $proc$libresoc.v:127987$5003 + attribute \src "libresoc.v:129594.3-129603.6" + process $proc$libresoc.v:129594$5044 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:127988.5-127988.29" + attribute \src "libresoc.v:129595.5-129595.29" switch \initial - attribute \src "libresoc.v:127988.9-127988.17" + attribute \src "libresoc.v:129595.9-129595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201616,24 +204036,24 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:127997.3-128016.6" - process $proc$libresoc.v:127997$5004 + attribute \src "libresoc.v:129604.3-129623.6" + process $proc$libresoc.v:129604$5045 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:127998.5-127998.29" + attribute \src "libresoc.v:129605.5-129605.29" switch \initial - attribute \src "libresoc.v:127998.9-127998.17" + attribute \src "libresoc.v:129605.9-129605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2[2:0] $2\fast_o2[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201652,24 +204072,24 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:128017.3-128036.6" - process $proc$libresoc.v:128017$5005 + attribute \src "libresoc.v:129624.3-129643.6" + process $proc$libresoc.v:129624$5046 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:128018.5-128018.29" + attribute \src "libresoc.v:129625.5-129625.29" switch \initial - attribute \src "libresoc.v:128018.9-128018.17" + attribute \src "libresoc.v:129625.9-129625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201688,29 +204108,29 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:127975$5000_Y - connect \$3 $eq$libresoc.v:127976$5001_Y + connect \$1 $eq$libresoc.v:129582$5041_Y + connect \$3 $eq$libresoc.v:129583$5042_Y end -attribute \src "libresoc.v:128041.1-128176.10" +attribute \src "libresoc.v:129648.1-129783.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:128042.7-128042.20" + attribute \src "libresoc.v:129649.7-129649.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201787,9 +204207,9 @@ module \dec_oe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:128042.7-128042.15" + attribute \src "libresoc.v:129649.7-129649.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -201799,28 +204219,28 @@ module \dec_oe attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128042.7-128042.20" - process $proc$libresoc.v:128042$5009 + attribute \src "libresoc.v:129649.7-129649.20" + process $proc$libresoc.v:129649$5050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128134.3-128154.6" - process $proc$libresoc.v:128134$5007 + attribute \src "libresoc.v:129741.3-129761.6" + process $proc$libresoc.v:129741$5048 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128135.5-128135.29" + attribute \src "libresoc.v:129742.5-129742.29" switch \initial - attribute \src "libresoc.v:128135.9-128135.17" + attribute \src "libresoc.v:129742.9-129742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201829,7 +204249,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201842,18 +204262,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128155.3-128175.6" - process $proc$libresoc.v:128155$5008 + attribute \src "libresoc.v:129762.3-129782.6" + process $proc$libresoc.v:129762$5049 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128156.5-128156.29" + attribute \src "libresoc.v:129763.5-129763.29" switch \initial - attribute \src "libresoc.v:128156.9-128156.17" + attribute \src "libresoc.v:129763.9-129763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201862,7 +204282,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201876,26 +204296,26 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128180.1-128313.10" +attribute \src "libresoc.v:129787.1-129920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:128181.7-128181.20" + attribute \src "libresoc.v:129788.7-129788.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201972,9 +204392,9 @@ module \dec_oe$140 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:128181.7-128181.15" + attribute \src "libresoc.v:129788.7-129788.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -201984,28 +204404,28 @@ module \dec_oe$140 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128181.7-128181.20" - process $proc$libresoc.v:128181$5012 + attribute \src "libresoc.v:129788.7-129788.20" + process $proc$libresoc.v:129788$5053 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128271.3-128291.6" - process $proc$libresoc.v:128271$5010 + attribute \src "libresoc.v:129878.3-129898.6" + process $proc$libresoc.v:129878$5051 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128272.5-128272.29" + attribute \src "libresoc.v:129879.5-129879.29" switch \initial - attribute \src "libresoc.v:128272.9-128272.17" + attribute \src "libresoc.v:129879.9-129879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202014,7 +204434,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202027,18 +204447,18 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128292.3-128312.6" - process $proc$libresoc.v:128292$5011 + attribute \src "libresoc.v:129899.3-129919.6" + process $proc$libresoc.v:129899$5052 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128293.5-128293.29" + attribute \src "libresoc.v:129900.5-129900.29" switch \initial - attribute \src "libresoc.v:128293.9-128293.17" + attribute \src "libresoc.v:129900.9-129900.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202047,7 +204467,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202061,26 +204481,26 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128317.1-128450.10" +attribute \src "libresoc.v:129924.1-130057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:128318.7-128318.20" + attribute \src "libresoc.v:129925.7-129925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202157,9 +204577,9 @@ module \dec_oe$143 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:128318.7-128318.15" + attribute \src "libresoc.v:129925.7-129925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -202169,28 +204589,28 @@ module \dec_oe$143 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128318.7-128318.20" - process $proc$libresoc.v:128318$5015 + attribute \src "libresoc.v:129925.7-129925.20" + process $proc$libresoc.v:129925$5056 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128408.3-128428.6" - process $proc$libresoc.v:128408$5013 + attribute \src "libresoc.v:130015.3-130035.6" + process $proc$libresoc.v:130015$5054 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128409.5-128409.29" + attribute \src "libresoc.v:130016.5-130016.29" switch \initial - attribute \src "libresoc.v:128409.9-128409.17" + attribute \src "libresoc.v:130016.9-130016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202199,7 +204619,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202212,18 +204632,18 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128429.3-128449.6" - process $proc$libresoc.v:128429$5014 + attribute \src "libresoc.v:130036.3-130056.6" + process $proc$libresoc.v:130036$5055 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128430.5-128430.29" + attribute \src "libresoc.v:130037.5-130037.29" switch \initial - attribute \src "libresoc.v:128430.9-128430.17" + attribute \src "libresoc.v:130037.9-130037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202232,7 +204652,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202246,26 +204666,26 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128454.1-128589.10" +attribute \src "libresoc.v:130061.1-130196.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:128455.7-128455.20" + attribute \src "libresoc.v:130062.7-130062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202342,9 +204762,9 @@ module \dec_oe$147 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:128455.7-128455.15" + attribute \src "libresoc.v:130062.7-130062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202354,28 +204774,28 @@ module \dec_oe$147 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128455.7-128455.20" - process $proc$libresoc.v:128455$5018 + attribute \src "libresoc.v:130062.7-130062.20" + process $proc$libresoc.v:130062$5059 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128547.3-128567.6" - process $proc$libresoc.v:128547$5016 + attribute \src "libresoc.v:130154.3-130174.6" + process $proc$libresoc.v:130154$5057 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128548.5-128548.29" + attribute \src "libresoc.v:130155.5-130155.29" switch \initial - attribute \src "libresoc.v:128548.9-128548.17" + attribute \src "libresoc.v:130155.9-130155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202384,7 +204804,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202397,18 +204817,18 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128568.3-128588.6" - process $proc$libresoc.v:128568$5017 + attribute \src "libresoc.v:130175.3-130195.6" + process $proc$libresoc.v:130175$5058 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128569.5-128569.29" + attribute \src "libresoc.v:130176.5-130176.29" switch \initial - attribute \src "libresoc.v:128569.9-128569.17" + attribute \src "libresoc.v:130176.9-130176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202417,7 +204837,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202431,26 +204851,26 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128593.1-128726.10" +attribute \src "libresoc.v:130200.1-130333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:128594.7-128594.20" + attribute \src "libresoc.v:130201.7-130201.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202527,9 +204947,9 @@ module \dec_oe$152 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:128594.7-128594.15" + attribute \src "libresoc.v:130201.7-130201.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -202539,28 +204959,28 @@ module \dec_oe$152 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128594.7-128594.20" - process $proc$libresoc.v:128594$5021 + attribute \src "libresoc.v:130201.7-130201.20" + process $proc$libresoc.v:130201$5062 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128684.3-128704.6" - process $proc$libresoc.v:128684$5019 + attribute \src "libresoc.v:130291.3-130311.6" + process $proc$libresoc.v:130291$5060 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128685.5-128685.29" + attribute \src "libresoc.v:130292.5-130292.29" switch \initial - attribute \src "libresoc.v:128685.9-128685.17" + attribute \src "libresoc.v:130292.9-130292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202569,7 +204989,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202582,18 +205002,18 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128705.3-128725.6" - process $proc$libresoc.v:128705$5020 + attribute \src "libresoc.v:130312.3-130332.6" + process $proc$libresoc.v:130312$5061 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128706.5-128706.29" + attribute \src "libresoc.v:130313.5-130313.29" switch \initial - attribute \src "libresoc.v:128706.9-128706.17" + attribute \src "libresoc.v:130313.9-130313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202602,7 +205022,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202616,26 +205036,26 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128730.1-128865.10" +attribute \src "libresoc.v:130337.1-130472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:128731.7-128731.20" + attribute \src "libresoc.v:130338.7-130338.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202712,9 +205132,9 @@ module \dec_oe$155 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:128731.7-128731.15" + attribute \src "libresoc.v:130338.7-130338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202724,28 +205144,28 @@ module \dec_oe$155 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128731.7-128731.20" - process $proc$libresoc.v:128731$5024 + attribute \src "libresoc.v:130338.7-130338.20" + process $proc$libresoc.v:130338$5065 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128823.3-128843.6" - process $proc$libresoc.v:128823$5022 + attribute \src "libresoc.v:130430.3-130450.6" + process $proc$libresoc.v:130430$5063 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128824.5-128824.29" + attribute \src "libresoc.v:130431.5-130431.29" switch \initial - attribute \src "libresoc.v:128824.9-128824.17" + attribute \src "libresoc.v:130431.9-130431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202754,7 +205174,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202767,18 +205187,18 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128844.3-128864.6" - process $proc$libresoc.v:128844$5023 + attribute \src "libresoc.v:130451.3-130471.6" + process $proc$libresoc.v:130451$5064 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128845.5-128845.29" + attribute \src "libresoc.v:130452.5-130452.29" switch \initial - attribute \src "libresoc.v:128845.9-128845.17" + attribute \src "libresoc.v:130452.9-130452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202787,7 +205207,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202801,26 +205221,26 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128869.1-129004.10" +attribute \src "libresoc.v:130476.1-130611.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:128870.7-128870.20" + attribute \src "libresoc.v:130477.7-130477.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202897,9 +205317,9 @@ module \dec_oe$160 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:128870.7-128870.15" + attribute \src "libresoc.v:130477.7-130477.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202909,28 +205329,28 @@ module \dec_oe$160 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128870.7-128870.20" - process $proc$libresoc.v:128870$5027 + attribute \src "libresoc.v:130477.7-130477.20" + process $proc$libresoc.v:130477$5068 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128962.3-128982.6" - process $proc$libresoc.v:128962$5025 + attribute \src "libresoc.v:130569.3-130589.6" + process $proc$libresoc.v:130569$5066 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128963.5-128963.29" + attribute \src "libresoc.v:130570.5-130570.29" switch \initial - attribute \src "libresoc.v:128963.9-128963.17" + attribute \src "libresoc.v:130570.9-130570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202939,7 +205359,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202952,18 +205372,18 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128983.3-129003.6" - process $proc$libresoc.v:128983$5026 + attribute \src "libresoc.v:130590.3-130610.6" + process $proc$libresoc.v:130590$5067 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128984.5-128984.29" + attribute \src "libresoc.v:130591.5-130591.29" switch \initial - attribute \src "libresoc.v:128984.9-128984.17" + attribute \src "libresoc.v:130591.9-130591.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202972,7 +205392,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202986,26 +205406,26 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129008.1-129143.10" +attribute \src "libresoc.v:130615.1-130750.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:129009.7-129009.20" + attribute \src "libresoc.v:130616.7-130616.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203082,9 +205502,9 @@ module \dec_oe$164 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:129009.7-129009.15" + attribute \src "libresoc.v:130616.7-130616.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203094,28 +205514,28 @@ module \dec_oe$164 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129009.7-129009.20" - process $proc$libresoc.v:129009$5030 + attribute \src "libresoc.v:130616.7-130616.20" + process $proc$libresoc.v:130616$5071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129101.3-129121.6" - process $proc$libresoc.v:129101$5028 + attribute \src "libresoc.v:130708.3-130728.6" + process $proc$libresoc.v:130708$5069 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129102.5-129102.29" + attribute \src "libresoc.v:130709.5-130709.29" switch \initial - attribute \src "libresoc.v:129102.9-129102.17" + attribute \src "libresoc.v:130709.9-130709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203124,7 +205544,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203137,18 +205557,18 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129122.3-129142.6" - process $proc$libresoc.v:129122$5029 + attribute \src "libresoc.v:130729.3-130749.6" + process $proc$libresoc.v:130729$5070 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129123.5-129123.29" + attribute \src "libresoc.v:130730.5-130730.29" switch \initial - attribute \src "libresoc.v:129123.9-129123.17" + attribute \src "libresoc.v:130730.9-130730.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203157,7 +205577,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203171,26 +205591,26 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129147.1-129282.10" +attribute \src "libresoc.v:130754.1-130889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:129148.7-129148.20" + attribute \src "libresoc.v:130755.7-130755.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203267,9 +205687,9 @@ module \dec_oe$168 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:129148.7-129148.15" + attribute \src "libresoc.v:130755.7-130755.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203279,28 +205699,28 @@ module \dec_oe$168 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129148.7-129148.20" - process $proc$libresoc.v:129148$5033 + attribute \src "libresoc.v:130755.7-130755.20" + process $proc$libresoc.v:130755$5074 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129240.3-129260.6" - process $proc$libresoc.v:129240$5031 + attribute \src "libresoc.v:130847.3-130867.6" + process $proc$libresoc.v:130847$5072 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129241.5-129241.29" + attribute \src "libresoc.v:130848.5-130848.29" switch \initial - attribute \src "libresoc.v:129241.9-129241.17" + attribute \src "libresoc.v:130848.9-130848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203309,7 +205729,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203322,18 +205742,18 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129261.3-129281.6" - process $proc$libresoc.v:129261$5032 + attribute \src "libresoc.v:130868.3-130888.6" + process $proc$libresoc.v:130868$5073 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129262.5-129262.29" + attribute \src "libresoc.v:130869.5-130869.29" switch \initial - attribute \src "libresoc.v:129262.9-129262.17" + attribute \src "libresoc.v:130869.9-130869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203342,7 +205762,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203356,28 +205776,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129286.1-129421.10" +attribute \src "libresoc.v:130893.1-131028.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:129287.7-129287.20" + attribute \src "libresoc.v:130894.7-130894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE - attribute \src "libresoc.v:129287.7-129287.15" + attribute \src "libresoc.v:130894.7-130894.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203454,7 +205874,7 @@ module \dec_oe$173 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203464,28 +205884,28 @@ module \dec_oe$173 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129287.7-129287.20" - process $proc$libresoc.v:129287$5036 + attribute \src "libresoc.v:130894.7-130894.20" + process $proc$libresoc.v:130894$5077 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129379.3-129399.6" - process $proc$libresoc.v:129379$5034 + attribute \src "libresoc.v:130986.3-131006.6" + process $proc$libresoc.v:130986$5075 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129380.5-129380.29" + attribute \src "libresoc.v:130987.5-130987.29" switch \initial - attribute \src "libresoc.v:129380.9-129380.17" + attribute \src "libresoc.v:130987.9-130987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203494,7 +205914,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203507,18 +205927,18 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129400.3-129420.6" - process $proc$libresoc.v:129400$5035 + attribute \src "libresoc.v:131007.3-131027.6" + process $proc$libresoc.v:131007$5076 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129401.5-129401.29" + attribute \src "libresoc.v:131008.5-131008.29" switch \initial - attribute \src "libresoc.v:129401.9-129401.17" + attribute \src "libresoc.v:131008.9-131008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203527,7 +205947,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203541,24 +205961,24 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129425.1-129479.10" +attribute \src "libresoc.v:131032.1-131086.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:129426.7-129426.20" + attribute \src "libresoc.v:131033.7-131033.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129441.3-129459.6" + attribute \src "libresoc.v:131048.3-131066.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129460.3-129478.6" + attribute \src "libresoc.v:131067.3-131085.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129441.3-129459.6" + attribute \src "libresoc.v:131048.3-131066.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129460.3-129478.6" + attribute \src "libresoc.v:131067.3-131085.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc - attribute \src "libresoc.v:129426.7-129426.15" + attribute \src "libresoc.v:131033.7-131033.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -203568,28 +205988,28 @@ module \dec_rc attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129426.7-129426.20" - process $proc$libresoc.v:129426$5039 + attribute \src "libresoc.v:131033.7-131033.20" + process $proc$libresoc.v:131033$5080 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129441.3-129459.6" - process $proc$libresoc.v:129441$5037 + attribute \src "libresoc.v:131048.3-131066.6" + process $proc$libresoc.v:131048$5078 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129442.5-129442.29" + attribute \src "libresoc.v:131049.5-131049.29" switch \initial - attribute \src "libresoc.v:129442.9-129442.17" + attribute \src "libresoc.v:131049.9-131049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203609,18 +206029,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129460.3-129478.6" - process $proc$libresoc.v:129460$5038 + attribute \src "libresoc.v:131067.3-131085.6" + process $proc$libresoc.v:131067$5079 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129461.5-129461.29" + attribute \src "libresoc.v:131068.5-131068.29" switch \initial - attribute \src "libresoc.v:129461.9-129461.17" + attribute \src "libresoc.v:131068.9-131068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203641,24 +206061,24 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129483.1-129535.10" +attribute \src "libresoc.v:131090.1-131142.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:129484.7-129484.20" + attribute \src "libresoc.v:131091.7-131091.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129497.3-129515.6" + attribute \src "libresoc.v:131104.3-131122.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129516.3-129534.6" + attribute \src "libresoc.v:131123.3-131141.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129497.3-129515.6" + attribute \src "libresoc.v:131104.3-131122.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129516.3-129534.6" + attribute \src "libresoc.v:131123.3-131141.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc - attribute \src "libresoc.v:129484.7-129484.15" + attribute \src "libresoc.v:131091.7-131091.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203668,28 +206088,28 @@ module \dec_rc$139 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129484.7-129484.20" - process $proc$libresoc.v:129484$5042 + attribute \src "libresoc.v:131091.7-131091.20" + process $proc$libresoc.v:131091$5083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129497.3-129515.6" - process $proc$libresoc.v:129497$5040 + attribute \src "libresoc.v:131104.3-131122.6" + process $proc$libresoc.v:131104$5081 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129498.5-129498.29" + attribute \src "libresoc.v:131105.5-131105.29" switch \initial - attribute \src "libresoc.v:129498.9-129498.17" + attribute \src "libresoc.v:131105.9-131105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203709,18 +206129,18 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129516.3-129534.6" - process $proc$libresoc.v:129516$5041 + attribute \src "libresoc.v:131123.3-131141.6" + process $proc$libresoc.v:131123$5082 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129517.5-129517.29" + attribute \src "libresoc.v:131124.5-131124.29" switch \initial - attribute \src "libresoc.v:129517.9-129517.17" + attribute \src "libresoc.v:131124.9-131124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203741,24 +206161,24 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129539.1-129591.10" +attribute \src "libresoc.v:131146.1-131198.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:129540.7-129540.20" + attribute \src "libresoc.v:131147.7-131147.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129553.3-129571.6" + attribute \src "libresoc.v:131160.3-131178.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129572.3-129590.6" + attribute \src "libresoc.v:131179.3-131197.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129553.3-129571.6" + attribute \src "libresoc.v:131160.3-131178.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129572.3-129590.6" + attribute \src "libresoc.v:131179.3-131197.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:129540.7-129540.15" + attribute \src "libresoc.v:131147.7-131147.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203768,28 +206188,28 @@ module \dec_rc$142 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129540.7-129540.20" - process $proc$libresoc.v:129540$5045 + attribute \src "libresoc.v:131147.7-131147.20" + process $proc$libresoc.v:131147$5086 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129553.3-129571.6" - process $proc$libresoc.v:129553$5043 + attribute \src "libresoc.v:131160.3-131178.6" + process $proc$libresoc.v:131160$5084 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129554.5-129554.29" + attribute \src "libresoc.v:131161.5-131161.29" switch \initial - attribute \src "libresoc.v:129554.9-129554.17" + attribute \src "libresoc.v:131161.9-131161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203809,18 +206229,18 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129572.3-129590.6" - process $proc$libresoc.v:129572$5044 + attribute \src "libresoc.v:131179.3-131197.6" + process $proc$libresoc.v:131179$5085 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129573.5-129573.29" + attribute \src "libresoc.v:131180.5-131180.29" switch \initial - attribute \src "libresoc.v:129573.9-129573.17" + attribute \src "libresoc.v:131180.9-131180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203841,24 +206261,24 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129595.1-129649.10" +attribute \src "libresoc.v:131202.1-131256.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:129596.7-129596.20" + attribute \src "libresoc.v:131203.7-131203.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129611.3-129629.6" + attribute \src "libresoc.v:131218.3-131236.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129630.3-129648.6" + attribute \src "libresoc.v:131237.3-131255.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129611.3-129629.6" + attribute \src "libresoc.v:131218.3-131236.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129630.3-129648.6" + attribute \src "libresoc.v:131237.3-131255.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:129596.7-129596.15" + attribute \src "libresoc.v:131203.7-131203.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -203868,28 +206288,28 @@ module \dec_rc$146 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129596.7-129596.20" - process $proc$libresoc.v:129596$5048 + attribute \src "libresoc.v:131203.7-131203.20" + process $proc$libresoc.v:131203$5089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129611.3-129629.6" - process $proc$libresoc.v:129611$5046 + attribute \src "libresoc.v:131218.3-131236.6" + process $proc$libresoc.v:131218$5087 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129612.5-129612.29" + attribute \src "libresoc.v:131219.5-131219.29" switch \initial - attribute \src "libresoc.v:129612.9-129612.17" + attribute \src "libresoc.v:131219.9-131219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203909,18 +206329,18 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129630.3-129648.6" - process $proc$libresoc.v:129630$5047 + attribute \src "libresoc.v:131237.3-131255.6" + process $proc$libresoc.v:131237$5088 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129631.5-129631.29" + attribute \src "libresoc.v:131238.5-131238.29" switch \initial - attribute \src "libresoc.v:129631.9-129631.17" + attribute \src "libresoc.v:131238.9-131238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203941,24 +206361,24 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129653.1-129705.10" +attribute \src "libresoc.v:131260.1-131312.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:129654.7-129654.20" + attribute \src "libresoc.v:131261.7-131261.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129667.3-129685.6" + attribute \src "libresoc.v:131274.3-131292.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129686.3-129704.6" + attribute \src "libresoc.v:131293.3-131311.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129667.3-129685.6" + attribute \src "libresoc.v:131274.3-131292.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129686.3-129704.6" + attribute \src "libresoc.v:131293.3-131311.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc - attribute \src "libresoc.v:129654.7-129654.15" + attribute \src "libresoc.v:131261.7-131261.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203968,28 +206388,28 @@ module \dec_rc$151 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129654.7-129654.20" - process $proc$libresoc.v:129654$5051 + attribute \src "libresoc.v:131261.7-131261.20" + process $proc$libresoc.v:131261$5092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129667.3-129685.6" - process $proc$libresoc.v:129667$5049 + attribute \src "libresoc.v:131274.3-131292.6" + process $proc$libresoc.v:131274$5090 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129668.5-129668.29" + attribute \src "libresoc.v:131275.5-131275.29" switch \initial - attribute \src "libresoc.v:129668.9-129668.17" + attribute \src "libresoc.v:131275.9-131275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204009,18 +206429,18 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129686.3-129704.6" - process $proc$libresoc.v:129686$5050 + attribute \src "libresoc.v:131293.3-131311.6" + process $proc$libresoc.v:131293$5091 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129687.5-129687.29" + attribute \src "libresoc.v:131294.5-131294.29" switch \initial - attribute \src "libresoc.v:129687.9-129687.17" + attribute \src "libresoc.v:131294.9-131294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204041,24 +206461,24 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129709.1-129763.10" +attribute \src "libresoc.v:131316.1-131370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:129710.7-129710.20" + attribute \src "libresoc.v:131317.7-131317.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129725.3-129743.6" + attribute \src "libresoc.v:131332.3-131350.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129744.3-129762.6" + attribute \src "libresoc.v:131351.3-131369.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129725.3-129743.6" + attribute \src "libresoc.v:131332.3-131350.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129744.3-129762.6" + attribute \src "libresoc.v:131351.3-131369.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc - attribute \src "libresoc.v:129710.7-129710.15" + attribute \src "libresoc.v:131317.7-131317.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204068,28 +206488,28 @@ module \dec_rc$154 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129710.7-129710.20" - process $proc$libresoc.v:129710$5054 + attribute \src "libresoc.v:131317.7-131317.20" + process $proc$libresoc.v:131317$5095 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129725.3-129743.6" - process $proc$libresoc.v:129725$5052 + attribute \src "libresoc.v:131332.3-131350.6" + process $proc$libresoc.v:131332$5093 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129726.5-129726.29" + attribute \src "libresoc.v:131333.5-131333.29" switch \initial - attribute \src "libresoc.v:129726.9-129726.17" + attribute \src "libresoc.v:131333.9-131333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204109,18 +206529,18 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129744.3-129762.6" - process $proc$libresoc.v:129744$5053 + attribute \src "libresoc.v:131351.3-131369.6" + process $proc$libresoc.v:131351$5094 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129745.5-129745.29" + attribute \src "libresoc.v:131352.5-131352.29" switch \initial - attribute \src "libresoc.v:129745.9-129745.17" + attribute \src "libresoc.v:131352.9-131352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204141,24 +206561,24 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129767.1-129821.10" +attribute \src "libresoc.v:131374.1-131428.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:129768.7-129768.20" + attribute \src "libresoc.v:131375.7-131375.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129783.3-129801.6" + attribute \src "libresoc.v:131390.3-131408.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129802.3-129820.6" + attribute \src "libresoc.v:131409.3-131427.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129783.3-129801.6" + attribute \src "libresoc.v:131390.3-131408.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129802.3-129820.6" + attribute \src "libresoc.v:131409.3-131427.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc - attribute \src "libresoc.v:129768.7-129768.15" + attribute \src "libresoc.v:131375.7-131375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204168,28 +206588,28 @@ module \dec_rc$159 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129768.7-129768.20" - process $proc$libresoc.v:129768$5057 + attribute \src "libresoc.v:131375.7-131375.20" + process $proc$libresoc.v:131375$5098 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129783.3-129801.6" - process $proc$libresoc.v:129783$5055 + attribute \src "libresoc.v:131390.3-131408.6" + process $proc$libresoc.v:131390$5096 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129784.5-129784.29" + attribute \src "libresoc.v:131391.5-131391.29" switch \initial - attribute \src "libresoc.v:129784.9-129784.17" + attribute \src "libresoc.v:131391.9-131391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204209,18 +206629,18 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129802.3-129820.6" - process $proc$libresoc.v:129802$5056 + attribute \src "libresoc.v:131409.3-131427.6" + process $proc$libresoc.v:131409$5097 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129803.5-129803.29" + attribute \src "libresoc.v:131410.5-131410.29" switch \initial - attribute \src "libresoc.v:129803.9-129803.17" + attribute \src "libresoc.v:131410.9-131410.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204241,24 +206661,24 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129825.1-129879.10" +attribute \src "libresoc.v:131432.1-131486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:129826.7-129826.20" + attribute \src "libresoc.v:131433.7-131433.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129841.3-129859.6" + attribute \src "libresoc.v:131448.3-131466.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129860.3-129878.6" + attribute \src "libresoc.v:131467.3-131485.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129841.3-129859.6" + attribute \src "libresoc.v:131448.3-131466.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129860.3-129878.6" + attribute \src "libresoc.v:131467.3-131485.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:129826.7-129826.15" + attribute \src "libresoc.v:131433.7-131433.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204268,28 +206688,28 @@ module \dec_rc$163 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129826.7-129826.20" - process $proc$libresoc.v:129826$5060 + attribute \src "libresoc.v:131433.7-131433.20" + process $proc$libresoc.v:131433$5101 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129841.3-129859.6" - process $proc$libresoc.v:129841$5058 + attribute \src "libresoc.v:131448.3-131466.6" + process $proc$libresoc.v:131448$5099 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129842.5-129842.29" + attribute \src "libresoc.v:131449.5-131449.29" switch \initial - attribute \src "libresoc.v:129842.9-129842.17" + attribute \src "libresoc.v:131449.9-131449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204309,18 +206729,18 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129860.3-129878.6" - process $proc$libresoc.v:129860$5059 + attribute \src "libresoc.v:131467.3-131485.6" + process $proc$libresoc.v:131467$5100 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129861.5-129861.29" + attribute \src "libresoc.v:131468.5-131468.29" switch \initial - attribute \src "libresoc.v:129861.9-129861.17" + attribute \src "libresoc.v:131468.9-131468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204341,24 +206761,24 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129883.1-129937.10" +attribute \src "libresoc.v:131490.1-131544.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:129884.7-129884.20" + attribute \src "libresoc.v:131491.7-131491.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129899.3-129917.6" + attribute \src "libresoc.v:131506.3-131524.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129918.3-129936.6" + attribute \src "libresoc.v:131525.3-131543.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129899.3-129917.6" + attribute \src "libresoc.v:131506.3-131524.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129918.3-129936.6" + attribute \src "libresoc.v:131525.3-131543.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc - attribute \src "libresoc.v:129884.7-129884.15" + attribute \src "libresoc.v:131491.7-131491.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204368,28 +206788,28 @@ module \dec_rc$167 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129884.7-129884.20" - process $proc$libresoc.v:129884$5063 + attribute \src "libresoc.v:131491.7-131491.20" + process $proc$libresoc.v:131491$5104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129899.3-129917.6" - process $proc$libresoc.v:129899$5061 + attribute \src "libresoc.v:131506.3-131524.6" + process $proc$libresoc.v:131506$5102 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129900.5-129900.29" + attribute \src "libresoc.v:131507.5-131507.29" switch \initial - attribute \src "libresoc.v:129900.9-129900.17" + attribute \src "libresoc.v:131507.9-131507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204409,18 +206829,18 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129918.3-129936.6" - process $proc$libresoc.v:129918$5062 + attribute \src "libresoc.v:131525.3-131543.6" + process $proc$libresoc.v:131525$5103 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129919.5-129919.29" + attribute \src "libresoc.v:131526.5-131526.29" switch \initial - attribute \src "libresoc.v:129919.9-129919.17" + attribute \src "libresoc.v:131526.9-131526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204441,24 +206861,24 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129941.1-129995.10" +attribute \src "libresoc.v:131548.1-131602.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:129942.7-129942.20" + attribute \src "libresoc.v:131549.7-131549.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129957.3-129975.6" + attribute \src "libresoc.v:131564.3-131582.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129976.3-129994.6" + attribute \src "libresoc.v:131583.3-131601.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129957.3-129975.6" + attribute \src "libresoc.v:131564.3-131582.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129976.3-129994.6" + attribute \src "libresoc.v:131583.3-131601.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc - attribute \src "libresoc.v:129942.7-129942.15" + attribute \src "libresoc.v:131549.7-131549.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204468,28 +206888,28 @@ module \dec_rc$172 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129942.7-129942.20" - process $proc$libresoc.v:129942$5066 + attribute \src "libresoc.v:131549.7-131549.20" + process $proc$libresoc.v:131549$5107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129957.3-129975.6" - process $proc$libresoc.v:129957$5064 + attribute \src "libresoc.v:131564.3-131582.6" + process $proc$libresoc.v:131564$5105 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129958.5-129958.29" + attribute \src "libresoc.v:131565.5-131565.29" switch \initial - attribute \src "libresoc.v:129958.9-129958.17" + attribute \src "libresoc.v:131565.9-131565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204509,18 +206929,18 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129976.3-129994.6" - process $proc$libresoc.v:129976$5065 + attribute \src "libresoc.v:131583.3-131601.6" + process $proc$libresoc.v:131583$5106 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129977.5-129977.29" + attribute \src "libresoc.v:131584.5-131584.29" switch \initial - attribute \src "libresoc.v:129977.9-129977.17" + attribute \src "libresoc.v:131584.9-131584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204541,539 +206961,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129999.1-131243.10" +attribute \src "libresoc.v:131606.1-132850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:130800.3-130801.25" + attribute \src "libresoc.v:132407.3-132408.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5206 - attribute \src "libresoc.v:130772.3-130773.75" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247 + attribute \src "libresoc.v:132379.3-132380.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 - attribute \src "libresoc.v:130742.3-130743.73" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + attribute \src "libresoc.v:132349.3-132350.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 - attribute \src "libresoc.v:130744.3-130745.87" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + attribute \src "libresoc.v:132351.3-132352.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 - attribute \src "libresoc.v:130746.3-130747.83" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + attribute \src "libresoc.v:132353.3-132354.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5210 - attribute \src "libresoc.v:130760.3-130761.81" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + attribute \src "libresoc.v:132367.3-132368.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5211 - attribute \src "libresoc.v:130774.3-130775.67" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252 + attribute \src "libresoc.v:132381.3-132382.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5212 - attribute \src "libresoc.v:130740.3-130741.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + attribute \src "libresoc.v:132347.3-132348.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$5213 - attribute \src "libresoc.v:130756.3-130757.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + attribute \src "libresoc.v:132363.3-132364.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$5214 - attribute \src "libresoc.v:130762.3-130763.79" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + attribute \src "libresoc.v:132369.3-132370.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 - attribute \src "libresoc.v:130768.3-130769.75" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + attribute \src "libresoc.v:132375.3-132376.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$5216 - attribute \src "libresoc.v:130770.3-130771.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + attribute \src "libresoc.v:132377.3-132378.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 - attribute \src "libresoc.v:130752.3-130753.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + attribute \src "libresoc.v:132359.3-132360.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 - attribute \src "libresoc.v:130754.3-130755.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + attribute \src "libresoc.v:132361.3-132362.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$5219 - attribute \src "libresoc.v:130766.3-130767.83" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + attribute \src "libresoc.v:132373.3-132374.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 - attribute \src "libresoc.v:130750.3-130751.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + attribute \src "libresoc.v:132357.3-132358.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 - attribute \src "libresoc.v:130748.3-130749.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + attribute \src "libresoc.v:132355.3-132356.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 - attribute \src "libresoc.v:130764.3-130765.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + attribute \src "libresoc.v:132371.3-132372.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$5223 - attribute \src "libresoc.v:130758.3-130759.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264 + attribute \src "libresoc.v:132365.3-132366.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130798.3-130799.40" + attribute \src "libresoc.v:132405.3-132406.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:131153.3-131161.6" - wire $0\alu_l_r_alu$next[0:0]$5293 - attribute \src "libresoc.v:130714.3-130715.39" + attribute \src "libresoc.v:132760.3-132768.6" + wire $0\alu_l_r_alu$next[0:0]$5334 + attribute \src "libresoc.v:132321.3-132322.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:131144.3-131152.6" - wire $0\alui_l_r_alui$next[0:0]$5290 - attribute \src "libresoc.v:130716.3-130717.43" + attribute \src "libresoc.v:132751.3-132759.6" + wire $0\alui_l_r_alui$next[0:0]$5331 + attribute \src "libresoc.v:132323.3-132324.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $0\data_r0__o$next[63:0]$5249 - attribute \src "libresoc.v:130736.3-130737.37" + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $0\data_r0__o$next[63:0]$5290 + attribute \src "libresoc.v:132343.3-132344.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire $0\data_r0__o_ok$next[0:0]$5250 - attribute \src "libresoc.v:130738.3-130739.43" + attribute \src "libresoc.v:132633.3-132654.6" + wire $0\data_r0__o_ok$next[0:0]$5291 + attribute \src "libresoc.v:132345.3-132346.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5257 - attribute \src "libresoc.v:130732.3-130733.43" + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5298 + attribute \src "libresoc.v:132339.3-132340.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5258 - attribute \src "libresoc.v:130734.3-130735.49" + attribute \src "libresoc.v:132655.3-132676.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5299 + attribute \src "libresoc.v:132341.3-132342.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$5265 - attribute \src "libresoc.v:130728.3-130729.47" + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5306 + attribute \src "libresoc.v:132335.3-132336.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$5266 - attribute \src "libresoc.v:130730.3-130731.53" + attribute \src "libresoc.v:132677.3-132698.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5307 + attribute \src "libresoc.v:132337.3-132338.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $0\data_r3__xer_so$next[0:0]$5273 - attribute \src "libresoc.v:130724.3-130725.47" + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so$next[0:0]$5314 + attribute \src "libresoc.v:132331.3-132332.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $0\data_r3__xer_so_ok$next[0:0]$5274 - attribute \src "libresoc.v:130726.3-130727.53" + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5315 + attribute \src "libresoc.v:132333.3-132334.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:131162.3-131171.6" + attribute \src "libresoc.v:132769.3-132778.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:131172.3-131181.6" + attribute \src "libresoc.v:132779.3-132788.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:131182.3-131191.6" + attribute \src "libresoc.v:132789.3-132798.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:131192.3-131201.6" + attribute \src "libresoc.v:132799.3-132808.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:130000.7-130000.20" + attribute \src "libresoc.v:131607.7-131607.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130942.3-130950.6" - wire $0\opc_l_r_opc$next[0:0]$5191 - attribute \src "libresoc.v:130784.3-130785.39" + attribute \src "libresoc.v:132549.3-132557.6" + wire $0\opc_l_r_opc$next[0:0]$5232 + attribute \src "libresoc.v:132391.3-132392.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130933.3-130941.6" - wire $0\opc_l_s_opc$next[0:0]$5188 - attribute \src "libresoc.v:130786.3-130787.39" + attribute \src "libresoc.v:132540.3-132548.6" + wire $0\opc_l_s_opc$next[0:0]$5229 + attribute \src "libresoc.v:132393.3-132394.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:131202.3-131210.6" - wire width 4 $0\prev_wr_go$next[3:0]$5300 - attribute \src "libresoc.v:130796.3-130797.37" + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $0\prev_wr_go$next[3:0]$5341 + attribute \src "libresoc.v:132403.3-132404.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:130887.3-130896.6" + attribute \src "libresoc.v:132494.3-132503.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:130978.3-130986.6" - wire width 4 $0\req_l_r_req$next[3:0]$5203 - attribute \src "libresoc.v:130776.3-130777.39" + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $0\req_l_r_req$next[3:0]$5244 + attribute \src "libresoc.v:132383.3-132384.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:130969.3-130977.6" - wire width 4 $0\req_l_s_req$next[3:0]$5200 - attribute \src "libresoc.v:130778.3-130779.39" + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $0\req_l_s_req$next[3:0]$5241 + attribute \src "libresoc.v:132385.3-132386.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:130906.3-130914.6" - wire $0\rok_l_r_rdok$next[0:0]$5179 - attribute \src "libresoc.v:130792.3-130793.41" + attribute \src "libresoc.v:132513.3-132521.6" + wire $0\rok_l_r_rdok$next[0:0]$5220 + attribute \src "libresoc.v:132399.3-132400.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130897.3-130905.6" - wire $0\rok_l_s_rdok$next[0:0]$5176 - attribute \src "libresoc.v:130794.3-130795.41" + attribute \src "libresoc.v:132504.3-132512.6" + wire $0\rok_l_s_rdok$next[0:0]$5217 + attribute \src "libresoc.v:132401.3-132402.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130924.3-130932.6" - wire $0\rst_l_r_rst$next[0:0]$5185 - attribute \src "libresoc.v:130788.3-130789.39" + attribute \src "libresoc.v:132531.3-132539.6" + wire $0\rst_l_r_rst$next[0:0]$5226 + attribute \src "libresoc.v:132395.3-132396.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130915.3-130923.6" - wire $0\rst_l_s_rst$next[0:0]$5182 - attribute \src "libresoc.v:130790.3-130791.39" + attribute \src "libresoc.v:132522.3-132530.6" + wire $0\rst_l_s_rst$next[0:0]$5223 + attribute \src "libresoc.v:132397.3-132398.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130960.3-130968.6" - wire width 3 $0\src_l_r_src$next[2:0]$5197 - attribute \src "libresoc.v:130780.3-130781.39" + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $0\src_l_r_src$next[2:0]$5238 + attribute \src "libresoc.v:132387.3-132388.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:130951.3-130959.6" - wire width 3 $0\src_l_s_src$next[2:0]$5194 - attribute \src "libresoc.v:130782.3-130783.39" + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $0\src_l_s_src$next[2:0]$5235 + attribute \src "libresoc.v:132389.3-132390.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:131114.3-131123.6" - wire width 64 $0\src_r0$next[63:0]$5281 - attribute \src "libresoc.v:130722.3-130723.29" + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $0\src_r0$next[63:0]$5322 + attribute \src "libresoc.v:132329.3-132330.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:131124.3-131133.6" - wire width 64 $0\src_r1$next[63:0]$5284 - attribute \src "libresoc.v:130720.3-130721.29" + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $0\src_r1$next[63:0]$5325 + attribute \src "libresoc.v:132327.3-132328.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:131134.3-131143.6" - wire $0\src_r2$next[0:0]$5287 - attribute \src "libresoc.v:130718.3-130719.29" + attribute \src "libresoc.v:132741.3-132750.6" + wire $0\src_r2$next[0:0]$5328 + attribute \src "libresoc.v:132325.3-132326.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:130130.7-130130.24" + attribute \src "libresoc.v:131737.7-131737.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5224 - attribute \src "libresoc.v:130140.13-130140.49" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + attribute \src "libresoc.v:131747.13-131747.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 - attribute \src "libresoc.v:130159.14-130159.53" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 + attribute \src "libresoc.v:131766.14-131766.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 - attribute \src "libresoc.v:130163.14-130163.72" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + attribute \src "libresoc.v:131770.14-131770.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 - attribute \src "libresoc.v:130167.7-130167.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + attribute \src "libresoc.v:131774.7-131774.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 - attribute \src "libresoc.v:130175.13-130175.52" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + attribute \src "libresoc.v:131782.13-131782.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5229 - attribute \src "libresoc.v:130179.14-130179.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270 + attribute \src "libresoc.v:131786.14-131786.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 - attribute \src "libresoc.v:130258.13-130258.51" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + attribute \src "libresoc.v:131865.13-131865.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$5231 - attribute \src "libresoc.v:130262.7-130262.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + attribute \src "libresoc.v:131869.7-131869.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$5232 - attribute \src "libresoc.v:130266.7-130266.45" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + attribute \src "libresoc.v:131873.7-131873.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 - attribute \src "libresoc.v:130270.7-130270.43" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + attribute \src "libresoc.v:131877.7-131877.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$5234 - attribute \src "libresoc.v:130274.7-130274.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275 + attribute \src "libresoc.v:131881.7-131881.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 - attribute \src "libresoc.v:130278.7-130278.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + attribute \src "libresoc.v:131885.7-131885.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 - attribute \src "libresoc.v:130282.7-130282.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + attribute \src "libresoc.v:131889.7-131889.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$5237 - attribute \src "libresoc.v:130286.7-130286.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278 + attribute \src "libresoc.v:131893.7-131893.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 - attribute \src "libresoc.v:130290.7-130290.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + attribute \src "libresoc.v:131897.7-131897.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 - attribute \src "libresoc.v:130294.7-130294.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 + attribute \src "libresoc.v:131901.7-131901.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 - attribute \src "libresoc.v:130298.7-130298.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + attribute \src "libresoc.v:131905.7-131905.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$5241 - attribute \src "libresoc.v:130302.7-130302.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + attribute \src "libresoc.v:131909.7-131909.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130328.7-130328.26" + attribute \src "libresoc.v:131935.7-131935.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:131153.3-131161.6" - wire $1\alu_l_r_alu$next[0:0]$5294 - attribute \src "libresoc.v:130336.7-130336.25" + attribute \src "libresoc.v:132760.3-132768.6" + wire $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:131943.7-131943.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:131144.3-131152.6" - wire $1\alui_l_r_alui$next[0:0]$5291 - attribute \src "libresoc.v:130348.7-130348.27" + attribute \src "libresoc.v:132751.3-132759.6" + wire $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:131955.7-131955.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $1\data_r0__o$next[63:0]$5251 - attribute \src "libresoc.v:130382.14-130382.47" + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $1\data_r0__o$next[63:0]$5292 + attribute \src "libresoc.v:131989.14-131989.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire $1\data_r0__o_ok$next[0:0]$5252 - attribute \src "libresoc.v:130386.7-130386.27" + attribute \src "libresoc.v:132633.3-132654.6" + wire $1\data_r0__o_ok$next[0:0]$5293 + attribute \src "libresoc.v:131993.7-131993.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5259 - attribute \src "libresoc.v:130390.13-130390.33" + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5300 + attribute \src "libresoc.v:131997.13-131997.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5260 - attribute \src "libresoc.v:130394.7-130394.30" + attribute \src "libresoc.v:132655.3-132676.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5301 + attribute \src "libresoc.v:132001.7-132001.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$5267 - attribute \src "libresoc.v:130398.13-130398.35" + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5308 + attribute \src "libresoc.v:132005.13-132005.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$5268 - attribute \src "libresoc.v:130402.7-130402.32" + attribute \src "libresoc.v:132677.3-132698.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5309 + attribute \src "libresoc.v:132009.7-132009.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $1\data_r3__xer_so$next[0:0]$5275 - attribute \src "libresoc.v:130406.7-130406.29" + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so$next[0:0]$5316 + attribute \src "libresoc.v:132013.7-132013.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $1\data_r3__xer_so_ok$next[0:0]$5276 - attribute \src "libresoc.v:130410.7-130410.32" + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5317 + attribute \src "libresoc.v:132017.7-132017.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:131162.3-131171.6" + attribute \src "libresoc.v:132769.3-132778.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:131172.3-131181.6" + attribute \src "libresoc.v:132779.3-132788.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:131182.3-131191.6" + attribute \src "libresoc.v:132789.3-132798.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:131192.3-131201.6" + attribute \src "libresoc.v:132799.3-132808.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:130942.3-130950.6" - wire $1\opc_l_r_opc$next[0:0]$5192 - attribute \src "libresoc.v:130430.7-130430.25" + attribute \src "libresoc.v:132549.3-132557.6" + wire $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132037.7-132037.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130933.3-130941.6" - wire $1\opc_l_s_opc$next[0:0]$5189 - attribute \src "libresoc.v:130434.7-130434.25" + attribute \src "libresoc.v:132540.3-132548.6" + wire $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132041.7-132041.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:131202.3-131210.6" - wire width 4 $1\prev_wr_go$next[3:0]$5301 - attribute \src "libresoc.v:130568.13-130568.30" + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $1\prev_wr_go$next[3:0]$5342 + attribute \src "libresoc.v:132175.13-132175.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:130887.3-130896.6" + attribute \src "libresoc.v:132494.3-132503.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:130978.3-130986.6" - wire width 4 $1\req_l_r_req$next[3:0]$5204 - attribute \src "libresoc.v:130576.13-130576.31" + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132183.13-132183.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:130969.3-130977.6" - wire width 4 $1\req_l_s_req$next[3:0]$5201 - attribute \src "libresoc.v:130580.13-130580.31" + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132187.13-132187.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:130906.3-130914.6" - wire $1\rok_l_r_rdok$next[0:0]$5180 - attribute \src "libresoc.v:130592.7-130592.26" + attribute \src "libresoc.v:132513.3-132521.6" + wire $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132199.7-132199.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130897.3-130905.6" - wire $1\rok_l_s_rdok$next[0:0]$5177 - attribute \src "libresoc.v:130596.7-130596.26" + attribute \src "libresoc.v:132504.3-132512.6" + wire $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132203.7-132203.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130924.3-130932.6" - wire $1\rst_l_r_rst$next[0:0]$5186 - attribute \src "libresoc.v:130600.7-130600.25" + attribute \src "libresoc.v:132531.3-132539.6" + wire $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132207.7-132207.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130915.3-130923.6" - wire $1\rst_l_s_rst$next[0:0]$5183 - attribute \src "libresoc.v:130604.7-130604.25" + attribute \src "libresoc.v:132522.3-132530.6" + wire $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132211.7-132211.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130960.3-130968.6" - wire width 3 $1\src_l_r_src$next[2:0]$5198 - attribute \src "libresoc.v:130618.13-130618.31" + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132225.13-132225.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:130951.3-130959.6" - wire width 3 $1\src_l_s_src$next[2:0]$5195 - attribute \src "libresoc.v:130622.13-130622.31" + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132229.13-132229.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:131114.3-131123.6" - wire width 64 $1\src_r0$next[63:0]$5282 - attribute \src "libresoc.v:130630.14-130630.43" + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132237.14-132237.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:131124.3-131133.6" - wire width 64 $1\src_r1$next[63:0]$5285 - attribute \src "libresoc.v:130634.14-130634.43" + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132241.14-132241.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:131134.3-131143.6" - wire $1\src_r2$next[0:0]$5288 - attribute \src "libresoc.v:130638.7-130638.20" + attribute \src "libresoc.v:132741.3-132750.6" + wire $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132245.7-132245.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $2\data_r0__o$next[63:0]$5253 - attribute \src "libresoc.v:131026.3-131047.6" - wire $2\data_r0__o_ok$next[0:0]$5254 - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$5261 - attribute \src "libresoc.v:131048.3-131069.6" - wire $2\data_r1__cr_a_ok$next[0:0]$5262 - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$5269 - attribute \src "libresoc.v:131070.3-131091.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$5270 - attribute \src "libresoc.v:131092.3-131113.6" - wire $2\data_r3__xer_so$next[0:0]$5277 - attribute \src "libresoc.v:131092.3-131113.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5278 - attribute \src "libresoc.v:131026.3-131047.6" - wire $3\data_r0__o_ok$next[0:0]$5255 - attribute \src "libresoc.v:131048.3-131069.6" - wire $3\data_r1__cr_a_ok$next[0:0]$5263 - attribute \src "libresoc.v:131070.3-131091.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$5271 - attribute \src "libresoc.v:131092.3-131113.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5279 - attribute \src "libresoc.v:130653.19-130653.133" - wire width 3 $and$libresoc.v:130653$5069_Y - attribute \src "libresoc.v:130655.19-130655.115" - wire width 3 $and$libresoc.v:130655$5071_Y - attribute \src "libresoc.v:130656.18-130656.110" - wire $and$libresoc.v:130656$5072_Y - attribute \src "libresoc.v:130657.19-130657.125" - wire $and$libresoc.v:130657$5073_Y - attribute \src "libresoc.v:130658.19-130658.125" - wire $and$libresoc.v:130658$5074_Y - attribute \src "libresoc.v:130659.19-130659.125" - wire $and$libresoc.v:130659$5075_Y - attribute \src "libresoc.v:130660.19-130660.125" - wire $and$libresoc.v:130660$5076_Y - attribute \src "libresoc.v:130661.19-130661.149" - wire width 4 $and$libresoc.v:130661$5077_Y - attribute \src "libresoc.v:130662.19-130662.121" - wire width 4 $and$libresoc.v:130662$5078_Y - attribute \src "libresoc.v:130663.19-130663.127" - wire $and$libresoc.v:130663$5079_Y - attribute \src "libresoc.v:130664.19-130664.127" - wire $and$libresoc.v:130664$5080_Y - attribute \src "libresoc.v:130665.19-130665.127" - wire $and$libresoc.v:130665$5081_Y - attribute \src "libresoc.v:130666.19-130666.127" - wire $and$libresoc.v:130666$5082_Y - attribute \src "libresoc.v:130668.18-130668.98" - wire $and$libresoc.v:130668$5084_Y - attribute \src "libresoc.v:130670.18-130670.100" - wire $and$libresoc.v:130670$5086_Y - attribute \src "libresoc.v:130671.18-130671.160" - wire width 4 $and$libresoc.v:130671$5087_Y - attribute \src "libresoc.v:130673.18-130673.119" - wire width 4 $and$libresoc.v:130673$5089_Y - attribute \src "libresoc.v:130676.17-130676.123" - wire $and$libresoc.v:130676$5092_Y - attribute \src "libresoc.v:130677.18-130677.116" - wire $and$libresoc.v:130677$5093_Y - attribute \src "libresoc.v:130682.18-130682.113" - wire $and$libresoc.v:130682$5098_Y - attribute \src "libresoc.v:130683.18-130683.125" - wire width 4 $and$libresoc.v:130683$5099_Y - attribute \src "libresoc.v:130685.18-130685.112" - wire $and$libresoc.v:130685$5101_Y - attribute \src "libresoc.v:130687.18-130687.126" - wire $and$libresoc.v:130687$5103_Y - attribute \src "libresoc.v:130688.18-130688.126" - wire $and$libresoc.v:130688$5104_Y - attribute \src "libresoc.v:130689.18-130689.117" - wire $and$libresoc.v:130689$5105_Y - attribute \src "libresoc.v:130695.18-130695.130" - wire $and$libresoc.v:130695$5111_Y - attribute \src "libresoc.v:130696.18-130696.124" - wire width 4 $and$libresoc.v:130696$5112_Y - attribute \src "libresoc.v:130698.18-130698.116" - wire $and$libresoc.v:130698$5114_Y - attribute \src "libresoc.v:130699.18-130699.119" - wire $and$libresoc.v:130699$5115_Y - attribute \src "libresoc.v:130700.18-130700.121" - wire $and$libresoc.v:130700$5116_Y - attribute \src "libresoc.v:130701.18-130701.121" - wire $and$libresoc.v:130701$5117_Y - attribute \src "libresoc.v:130711.18-130711.134" - wire $and$libresoc.v:130711$5127_Y - attribute \src "libresoc.v:130712.18-130712.132" - wire $and$libresoc.v:130712$5128_Y - attribute \src "libresoc.v:130713.18-130713.149" - wire width 3 $and$libresoc.v:130713$5129_Y - attribute \src "libresoc.v:130684.18-130684.113" - wire $eq$libresoc.v:130684$5100_Y - attribute \src "libresoc.v:130686.18-130686.119" - wire $eq$libresoc.v:130686$5102_Y - attribute \src "libresoc.v:130651.19-130651.130" - wire $not$libresoc.v:130651$5067_Y - attribute \src "libresoc.v:130652.19-130652.136" - wire $not$libresoc.v:130652$5068_Y - attribute \src "libresoc.v:130654.19-130654.115" - wire width 3 $not$libresoc.v:130654$5070_Y - attribute \src "libresoc.v:130667.18-130667.97" - wire $not$libresoc.v:130667$5083_Y - attribute \src "libresoc.v:130669.18-130669.99" - wire $not$libresoc.v:130669$5085_Y - attribute \src "libresoc.v:130672.18-130672.113" - wire width 4 $not$libresoc.v:130672$5088_Y - attribute \src "libresoc.v:130675.18-130675.106" - wire $not$libresoc.v:130675$5091_Y - attribute \src "libresoc.v:130681.18-130681.120" - wire $not$libresoc.v:130681$5097_Y - attribute \src "libresoc.v:130692.17-130692.113" - wire width 3 $not$libresoc.v:130692$5108_Y - attribute \src "libresoc.v:130680.18-130680.112" - wire $or$libresoc.v:130680$5096_Y - attribute \src "libresoc.v:130690.18-130690.122" - wire $or$libresoc.v:130690$5106_Y - attribute \src "libresoc.v:130691.18-130691.124" - wire $or$libresoc.v:130691$5107_Y - attribute \src "libresoc.v:130693.18-130693.168" - wire width 4 $or$libresoc.v:130693$5109_Y - attribute \src "libresoc.v:130694.18-130694.155" - wire width 3 $or$libresoc.v:130694$5110_Y - attribute \src "libresoc.v:130697.18-130697.120" - wire width 4 $or$libresoc.v:130697$5113_Y - attribute \src "libresoc.v:130703.17-130703.117" - wire width 3 $or$libresoc.v:130703$5119_Y - attribute \src "libresoc.v:130708.17-130708.104" - wire $reduce_and$libresoc.v:130708$5124_Y - attribute \src "libresoc.v:130674.18-130674.106" - wire $reduce_or$libresoc.v:130674$5090_Y - attribute \src "libresoc.v:130678.18-130678.113" - wire $reduce_or$libresoc.v:130678$5094_Y - attribute \src "libresoc.v:130679.18-130679.112" - wire $reduce_or$libresoc.v:130679$5095_Y - attribute \src "libresoc.v:130702.18-130702.158" - wire $ternary$libresoc.v:130702$5118_Y - attribute \src "libresoc.v:130704.18-130704.159" - wire width 64 $ternary$libresoc.v:130704$5120_Y - attribute \src "libresoc.v:130705.18-130705.164" - wire $ternary$libresoc.v:130705$5121_Y - attribute \src "libresoc.v:130706.18-130706.180" - wire width 64 $ternary$libresoc.v:130706$5122_Y - attribute \src "libresoc.v:130707.18-130707.115" - wire width 64 $ternary$libresoc.v:130707$5123_Y - attribute \src "libresoc.v:130709.18-130709.125" - wire width 64 $ternary$libresoc.v:130709$5125_Y - attribute \src "libresoc.v:130710.18-130710.118" - wire $ternary$libresoc.v:130710$5126_Y + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $2\data_r0__o$next[63:0]$5294 + attribute \src "libresoc.v:132633.3-132654.6" + wire $2\data_r0__o_ok$next[0:0]$5295 + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5302 + attribute \src "libresoc.v:132655.3-132676.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5303 + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5310 + attribute \src "libresoc.v:132677.3-132698.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5311 + attribute \src "libresoc.v:132699.3-132720.6" + wire $2\data_r3__xer_so$next[0:0]$5318 + attribute \src "libresoc.v:132699.3-132720.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5319 + attribute \src "libresoc.v:132633.3-132654.6" + wire $3\data_r0__o_ok$next[0:0]$5296 + attribute \src "libresoc.v:132655.3-132676.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5304 + attribute \src "libresoc.v:132677.3-132698.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5312 + attribute \src "libresoc.v:132699.3-132720.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5320 + attribute \src "libresoc.v:132260.19-132260.133" + wire width 3 $and$libresoc.v:132260$5110_Y + attribute \src "libresoc.v:132262.19-132262.115" + wire width 3 $and$libresoc.v:132262$5112_Y + attribute \src "libresoc.v:132263.18-132263.110" + wire $and$libresoc.v:132263$5113_Y + attribute \src "libresoc.v:132264.19-132264.125" + wire $and$libresoc.v:132264$5114_Y + attribute \src "libresoc.v:132265.19-132265.125" + wire $and$libresoc.v:132265$5115_Y + attribute \src "libresoc.v:132266.19-132266.125" + wire $and$libresoc.v:132266$5116_Y + attribute \src "libresoc.v:132267.19-132267.125" + wire $and$libresoc.v:132267$5117_Y + attribute \src "libresoc.v:132268.19-132268.149" + wire width 4 $and$libresoc.v:132268$5118_Y + attribute \src "libresoc.v:132269.19-132269.121" + wire width 4 $and$libresoc.v:132269$5119_Y + attribute \src "libresoc.v:132270.19-132270.127" + wire $and$libresoc.v:132270$5120_Y + attribute \src "libresoc.v:132271.19-132271.127" + wire $and$libresoc.v:132271$5121_Y + attribute \src "libresoc.v:132272.19-132272.127" + wire $and$libresoc.v:132272$5122_Y + attribute \src "libresoc.v:132273.19-132273.127" + wire $and$libresoc.v:132273$5123_Y + attribute \src "libresoc.v:132275.18-132275.98" + wire $and$libresoc.v:132275$5125_Y + attribute \src "libresoc.v:132277.18-132277.100" + wire $and$libresoc.v:132277$5127_Y + attribute \src "libresoc.v:132278.18-132278.160" + wire width 4 $and$libresoc.v:132278$5128_Y + attribute \src "libresoc.v:132280.18-132280.119" + wire width 4 $and$libresoc.v:132280$5130_Y + attribute \src "libresoc.v:132283.17-132283.123" + wire $and$libresoc.v:132283$5133_Y + attribute \src "libresoc.v:132284.18-132284.116" + wire $and$libresoc.v:132284$5134_Y + attribute \src "libresoc.v:132289.18-132289.113" + wire $and$libresoc.v:132289$5139_Y + attribute \src "libresoc.v:132290.18-132290.125" + wire width 4 $and$libresoc.v:132290$5140_Y + attribute \src "libresoc.v:132292.18-132292.112" + wire $and$libresoc.v:132292$5142_Y + attribute \src "libresoc.v:132294.18-132294.126" + wire $and$libresoc.v:132294$5144_Y + attribute \src "libresoc.v:132295.18-132295.126" + wire $and$libresoc.v:132295$5145_Y + attribute \src "libresoc.v:132296.18-132296.117" + wire $and$libresoc.v:132296$5146_Y + attribute \src "libresoc.v:132302.18-132302.130" + wire $and$libresoc.v:132302$5152_Y + attribute \src "libresoc.v:132303.18-132303.124" + wire width 4 $and$libresoc.v:132303$5153_Y + attribute \src "libresoc.v:132305.18-132305.116" + wire $and$libresoc.v:132305$5155_Y + attribute \src "libresoc.v:132306.18-132306.119" + wire $and$libresoc.v:132306$5156_Y + attribute \src "libresoc.v:132307.18-132307.121" + wire $and$libresoc.v:132307$5157_Y + attribute \src "libresoc.v:132308.18-132308.121" + wire $and$libresoc.v:132308$5158_Y + attribute \src "libresoc.v:132318.18-132318.134" + wire $and$libresoc.v:132318$5168_Y + attribute \src "libresoc.v:132319.18-132319.132" + wire $and$libresoc.v:132319$5169_Y + attribute \src "libresoc.v:132320.18-132320.149" + wire width 3 $and$libresoc.v:132320$5170_Y + attribute \src "libresoc.v:132291.18-132291.113" + wire $eq$libresoc.v:132291$5141_Y + attribute \src "libresoc.v:132293.18-132293.119" + wire $eq$libresoc.v:132293$5143_Y + attribute \src "libresoc.v:132258.19-132258.130" + wire $not$libresoc.v:132258$5108_Y + attribute \src "libresoc.v:132259.19-132259.136" + wire $not$libresoc.v:132259$5109_Y + attribute \src "libresoc.v:132261.19-132261.115" + wire width 3 $not$libresoc.v:132261$5111_Y + attribute \src "libresoc.v:132274.18-132274.97" + wire $not$libresoc.v:132274$5124_Y + attribute \src "libresoc.v:132276.18-132276.99" + wire $not$libresoc.v:132276$5126_Y + attribute \src "libresoc.v:132279.18-132279.113" + wire width 4 $not$libresoc.v:132279$5129_Y + attribute \src "libresoc.v:132282.18-132282.106" + wire $not$libresoc.v:132282$5132_Y + attribute \src "libresoc.v:132288.18-132288.120" + wire $not$libresoc.v:132288$5138_Y + attribute \src "libresoc.v:132299.17-132299.113" + wire width 3 $not$libresoc.v:132299$5149_Y + attribute \src "libresoc.v:132287.18-132287.112" + wire $or$libresoc.v:132287$5137_Y + attribute \src "libresoc.v:132297.18-132297.122" + wire $or$libresoc.v:132297$5147_Y + attribute \src "libresoc.v:132298.18-132298.124" + wire $or$libresoc.v:132298$5148_Y + attribute \src "libresoc.v:132300.18-132300.168" + wire width 4 $or$libresoc.v:132300$5150_Y + attribute \src "libresoc.v:132301.18-132301.155" + wire width 3 $or$libresoc.v:132301$5151_Y + attribute \src "libresoc.v:132304.18-132304.120" + wire width 4 $or$libresoc.v:132304$5154_Y + attribute \src "libresoc.v:132310.17-132310.117" + wire width 3 $or$libresoc.v:132310$5160_Y + attribute \src "libresoc.v:132315.17-132315.104" + wire $reduce_and$libresoc.v:132315$5165_Y + attribute \src "libresoc.v:132281.18-132281.106" + wire $reduce_or$libresoc.v:132281$5131_Y + attribute \src "libresoc.v:132285.18-132285.113" + wire $reduce_or$libresoc.v:132285$5135_Y + attribute \src "libresoc.v:132286.18-132286.112" + wire $reduce_or$libresoc.v:132286$5136_Y + attribute \src "libresoc.v:132309.18-132309.158" + wire $ternary$libresoc.v:132309$5159_Y + attribute \src "libresoc.v:132311.18-132311.159" + wire width 64 $ternary$libresoc.v:132311$5161_Y + attribute \src "libresoc.v:132312.18-132312.164" + wire $ternary$libresoc.v:132312$5162_Y + attribute \src "libresoc.v:132313.18-132313.180" + wire width 64 $ternary$libresoc.v:132313$5163_Y + attribute \src "libresoc.v:132314.18-132314.115" + wire width 64 $ternary$libresoc.v:132314$5164_Y + attribute \src "libresoc.v:132316.18-132316.125" + wire width 64 $ternary$libresoc.v:132316$5166_Y + attribute \src "libresoc.v:132317.18-132317.118" + wire $ternary$libresoc.v:132317$5167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -205426,9 +207846,9 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -205494,7 +207914,7 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:130000.7-130000.15" + attribute \src "libresoc.v:131607.7-131607.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -205723,7 +208143,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130653$5069 + cell $and $and$libresoc.v:132260$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -205731,10 +208151,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:130653$5069_Y + connect \Y $and$libresoc.v:132260$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130655$5071 + cell $and $and$libresoc.v:132262$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -205742,10 +208162,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:130655$5071_Y + connect \Y $and$libresoc.v:132262$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:130656$5072 + cell $and $and$libresoc.v:132263$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205753,10 +208173,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:130656$5072_Y + connect \Y $and$libresoc.v:132263$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130657$5073 + cell $and $and$libresoc.v:132264$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205764,10 +208184,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130657$5073_Y + connect \Y $and$libresoc.v:132264$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130658$5074 + cell $and $and$libresoc.v:132265$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205775,10 +208195,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130658$5074_Y + connect \Y $and$libresoc.v:132265$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130659$5075 + cell $and $and$libresoc.v:132266$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205786,10 +208206,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130659$5075_Y + connect \Y $and$libresoc.v:132266$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130660$5076 + cell $and $and$libresoc.v:132267$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205797,10 +208217,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130660$5076_Y + connect \Y $and$libresoc.v:132267$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130661$5077 + cell $and $and$libresoc.v:132268$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205808,10 +208228,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:130661$5077_Y + connect \Y $and$libresoc.v:132268$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130662$5078 + cell $and $and$libresoc.v:132269$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205819,10 +208239,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130662$5078_Y + connect \Y $and$libresoc.v:132269$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130663$5079 + cell $and $and$libresoc.v:132270$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205830,10 +208250,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130663$5079_Y + connect \Y $and$libresoc.v:132270$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130664$5080 + cell $and $and$libresoc.v:132271$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205841,10 +208261,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130664$5080_Y + connect \Y $and$libresoc.v:132271$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130665$5081 + cell $and $and$libresoc.v:132272$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205852,10 +208272,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130665$5081_Y + connect \Y $and$libresoc.v:132272$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130666$5082 + cell $and $and$libresoc.v:132273$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205863,10 +208283,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130666$5082_Y + connect \Y $and$libresoc.v:132273$5123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:130668$5084 + cell $and $and$libresoc.v:132275$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205874,10 +208294,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:130668$5084_Y + connect \Y $and$libresoc.v:132275$5125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:130670$5086 + cell $and $and$libresoc.v:132277$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205885,10 +208305,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:130670$5086_Y + connect \Y $and$libresoc.v:132277$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:130671$5087 + cell $and $and$libresoc.v:132278$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205896,10 +208316,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130671$5087_Y + connect \Y $and$libresoc.v:132278$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130673$5089 + cell $and $and$libresoc.v:132280$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205907,10 +208327,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:130673$5089_Y + connect \Y $and$libresoc.v:132280$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:130676$5092 + cell $and $and$libresoc.v:132283$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205918,10 +208338,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:130676$5092_Y + connect \Y $and$libresoc.v:132283$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130677$5093 + cell $and $and$libresoc.v:132284$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205929,10 +208349,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:130677$5093_Y + connect \Y $and$libresoc.v:132284$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:130682$5098 + cell $and $and$libresoc.v:132289$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205940,10 +208360,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:130682$5098_Y + connect \Y $and$libresoc.v:132289$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130683$5099 + cell $and $and$libresoc.v:132290$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205951,10 +208371,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130683$5099_Y + connect \Y $and$libresoc.v:132290$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130685$5101 + cell $and $and$libresoc.v:132292$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205962,10 +208382,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:130685$5101_Y + connect \Y $and$libresoc.v:132292$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130687$5103 + cell $and $and$libresoc.v:132294$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205973,10 +208393,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:130687$5103_Y + connect \Y $and$libresoc.v:132294$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130688$5104 + cell $and $and$libresoc.v:132295$5145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205984,10 +208404,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:130688$5104_Y + connect \Y $and$libresoc.v:132295$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130689$5105 + cell $and $and$libresoc.v:132296$5146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205995,10 +208415,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:130689$5105_Y + connect \Y $and$libresoc.v:132296$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:130695$5111 + cell $and $and$libresoc.v:132302$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206006,10 +208426,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:130695$5111_Y + connect \Y $and$libresoc.v:132302$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:130696$5112 + cell $and $and$libresoc.v:132303$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206017,10 +208437,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130696$5112_Y + connect \Y $and$libresoc.v:132303$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130698$5114 + cell $and $and$libresoc.v:132305$5155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206028,10 +208448,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130698$5114_Y + connect \Y $and$libresoc.v:132305$5155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130699$5115 + cell $and $and$libresoc.v:132306$5156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206039,10 +208459,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130699$5115_Y + connect \Y $and$libresoc.v:132306$5156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130700$5116 + cell $and $and$libresoc.v:132307$5157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206050,10 +208470,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130700$5116_Y + connect \Y $and$libresoc.v:132307$5157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130701$5117 + cell $and $and$libresoc.v:132308$5158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206061,10 +208481,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130701$5117_Y + connect \Y $and$libresoc.v:132308$5158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:130711$5127 + cell $and $and$libresoc.v:132318$5168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206072,10 +208492,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:130711$5127_Y + connect \Y $and$libresoc.v:132318$5168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:130712$5128 + cell $and $and$libresoc.v:132319$5169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206083,10 +208503,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:130712$5128_Y + connect \Y $and$libresoc.v:132319$5169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130713$5129 + cell $and $and$libresoc.v:132320$5170 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206094,10 +208514,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130713$5129_Y + connect \Y $and$libresoc.v:132320$5170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:130684$5100 + cell $eq $eq$libresoc.v:132291$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206105,10 +208525,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:130684$5100_Y + connect \Y $eq$libresoc.v:132291$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:130686$5102 + cell $eq $eq$libresoc.v:132293$5143 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206116,82 +208536,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:130686$5102_Y + connect \Y $eq$libresoc.v:132293$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130651$5067 + cell $not $not$libresoc.v:132258$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:130651$5067_Y + connect \Y $not$libresoc.v:132258$5108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130652$5068 + cell $not $not$libresoc.v:132259$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:130652$5068_Y + connect \Y $not$libresoc.v:132259$5109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:130654$5070 + cell $not $not$libresoc.v:132261$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:130654$5070_Y + connect \Y $not$libresoc.v:132261$5111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:130667$5083 + cell $not $not$libresoc.v:132274$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:130667$5083_Y + connect \Y $not$libresoc.v:132274$5124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:130669$5085 + cell $not $not$libresoc.v:132276$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:130669$5085_Y + connect \Y $not$libresoc.v:132276$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130672$5088 + cell $not $not$libresoc.v:132279$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:130672$5088_Y + connect \Y $not$libresoc.v:132279$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130675$5091 + cell $not $not$libresoc.v:132282$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:130675$5091_Y + connect \Y $not$libresoc.v:132282$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:130681$5097 + cell $not $not$libresoc.v:132288$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:130681$5097_Y + connect \Y $not$libresoc.v:132288$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:130692$5108 + cell $not $not$libresoc.v:132299$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:130692$5108_Y + connect \Y $not$libresoc.v:132299$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:130680$5096 + cell $or $or$libresoc.v:132287$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206199,10 +208619,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:130680$5096_Y + connect \Y $or$libresoc.v:132287$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:130690$5106 + cell $or $or$libresoc.v:132297$5147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206210,10 +208630,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130690$5106_Y + connect \Y $or$libresoc.v:132297$5147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:130691$5107 + cell $or $or$libresoc.v:132298$5148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206221,10 +208641,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130691$5107_Y + connect \Y $or$libresoc.v:132298$5148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:130693$5109 + cell $or $or$libresoc.v:132300$5150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206232,10 +208652,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130693$5109_Y + connect \Y $or$libresoc.v:132300$5150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:130694$5110 + cell $or $or$libresoc.v:132301$5151 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206243,10 +208663,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130694$5110_Y + connect \Y $or$libresoc.v:132301$5151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:130697$5113 + cell $or $or$libresoc.v:132304$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206254,10 +208674,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:130697$5113_Y + connect \Y $or$libresoc.v:132304$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:130703$5119 + cell $or $or$libresoc.v:132310$5160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206265,98 +208685,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:130703$5119_Y + connect \Y $or$libresoc.v:132310$5160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:130708$5124 + cell $reduce_and $reduce_and$libresoc.v:132315$5165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:130708$5124_Y + connect \Y $reduce_and$libresoc.v:132315$5165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:130674$5090 + cell $reduce_or $reduce_or$libresoc.v:132281$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:130674$5090_Y + connect \Y $reduce_or$libresoc.v:132281$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130678$5094 + cell $reduce_or $reduce_or$libresoc.v:132285$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:130678$5094_Y + connect \Y $reduce_or$libresoc.v:132285$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130679$5095 + cell $reduce_or $reduce_or$libresoc.v:132286$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:130679$5095_Y + connect \Y $reduce_or$libresoc.v:132286$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130702$5118 + cell $mux $ternary$libresoc.v:132309$5159 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130702$5118_Y + connect \Y $ternary$libresoc.v:132309$5159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130704$5120 + cell $mux $ternary$libresoc.v:132311$5161 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130704$5120_Y + connect \Y $ternary$libresoc.v:132311$5161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130705$5121 + cell $mux $ternary$libresoc.v:132312$5162 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130705$5121_Y + connect \Y $ternary$libresoc.v:132312$5162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130706$5122 + cell $mux $ternary$libresoc.v:132313$5163 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130706$5122_Y + connect \Y $ternary$libresoc.v:132313$5163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130707$5123 + cell $mux $ternary$libresoc.v:132314$5164 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:130707$5123_Y + connect \Y $ternary$libresoc.v:132314$5164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130709$5125 + cell $mux $ternary$libresoc.v:132316$5166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:130709$5125_Y + connect \Y $ternary$libresoc.v:132316$5166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130710$5126 + cell $mux $ternary$libresoc.v:132317$5167 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:130710$5126_Y + connect \Y $ternary$libresoc.v:132317$5167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:130802.12-130838.4" + attribute \src "libresoc.v:132409.12-132445.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206395,7 +208815,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:130839.14-130845.4" + attribute \src "libresoc.v:132446.14-132452.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206404,7 +208824,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:130846.15-130852.4" + attribute \src "libresoc.v:132453.15-132459.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206413,7 +208833,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:130853.14-130859.4" + attribute \src "libresoc.v:132460.14-132466.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206422,7 +208842,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:130860.14-130866.4" + attribute \src "libresoc.v:132467.14-132473.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206431,7 +208851,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:130867.14-130873.4" + attribute \src "libresoc.v:132474.14-132480.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206440,7 +208860,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:130874.14-130879.4" + attribute \src "libresoc.v:132481.14-132486.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206448,7 +208868,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:130880.14-130886.4" + attribute \src "libresoc.v:132487.14-132493.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206456,682 +208876,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:130000.7-130000.20" - process $proc$libresoc.v:130000$5302 + attribute \src "libresoc.v:131607.7-131607.20" + process $proc$libresoc.v:131607$5343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130130.7-130130.24" - process $proc$libresoc.v:130130$5303 + attribute \src "libresoc.v:131737.7-131737.24" + process $proc$libresoc.v:131737$5344 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:130140.13-130140.49" - process $proc$libresoc.v:130140$5304 + attribute \src "libresoc.v:131747.13-131747.49" + process $proc$libresoc.v:131747$5345 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:130159.14-130159.53" - process $proc$libresoc.v:130159$5305 + attribute \src "libresoc.v:131766.14-131766.53" + process $proc$libresoc.v:131766$5346 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:130163.14-130163.72" - process $proc$libresoc.v:130163$5306 + attribute \src "libresoc.v:131770.14-131770.72" + process $proc$libresoc.v:131770$5347 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130167.7-130167.47" - process $proc$libresoc.v:130167$5307 + attribute \src "libresoc.v:131774.7-131774.47" + process $proc$libresoc.v:131774$5348 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130175.13-130175.52" - process $proc$libresoc.v:130175$5308 + attribute \src "libresoc.v:131782.13-131782.52" + process $proc$libresoc.v:131782$5349 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:130179.14-130179.47" - process $proc$libresoc.v:130179$5309 + attribute \src "libresoc.v:131786.14-131786.47" + process $proc$libresoc.v:131786$5350 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:130258.13-130258.51" - process $proc$libresoc.v:130258$5310 + attribute \src "libresoc.v:131865.13-131865.51" + process $proc$libresoc.v:131865$5351 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:130262.7-130262.44" - process $proc$libresoc.v:130262$5311 + attribute \src "libresoc.v:131869.7-131869.44" + process $proc$libresoc.v:131869$5352 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:130266.7-130266.45" - process $proc$libresoc.v:130266$5312 + attribute \src "libresoc.v:131873.7-131873.45" + process $proc$libresoc.v:131873$5353 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:130270.7-130270.43" - process $proc$libresoc.v:130270$5313 + attribute \src "libresoc.v:131877.7-131877.43" + process $proc$libresoc.v:131877$5354 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:130274.7-130274.44" - process $proc$libresoc.v:130274$5314 + attribute \src "libresoc.v:131881.7-131881.44" + process $proc$libresoc.v:131881$5355 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:130278.7-130278.41" - process $proc$libresoc.v:130278$5315 + attribute \src "libresoc.v:131885.7-131885.41" + process $proc$libresoc.v:131885$5356 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:130282.7-130282.41" - process $proc$libresoc.v:130282$5316 + attribute \src "libresoc.v:131889.7-131889.41" + process $proc$libresoc.v:131889$5357 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:130286.7-130286.47" - process $proc$libresoc.v:130286$5317 + attribute \src "libresoc.v:131893.7-131893.47" + process $proc$libresoc.v:131893$5358 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:130290.7-130290.41" - process $proc$libresoc.v:130290$5318 + attribute \src "libresoc.v:131897.7-131897.41" + process $proc$libresoc.v:131897$5359 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:130294.7-130294.41" - process $proc$libresoc.v:130294$5319 + attribute \src "libresoc.v:131901.7-131901.41" + process $proc$libresoc.v:131901$5360 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:130298.7-130298.44" - process $proc$libresoc.v:130298$5320 + attribute \src "libresoc.v:131905.7-131905.44" + process $proc$libresoc.v:131905$5361 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:130302.7-130302.41" - process $proc$libresoc.v:130302$5321 + attribute \src "libresoc.v:131909.7-131909.41" + process $proc$libresoc.v:131909$5362 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:130328.7-130328.26" - process $proc$libresoc.v:130328$5322 + attribute \src "libresoc.v:131935.7-131935.26" + process $proc$libresoc.v:131935$5363 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:130336.7-130336.25" - process $proc$libresoc.v:130336$5323 + attribute \src "libresoc.v:131943.7-131943.25" + process $proc$libresoc.v:131943$5364 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:130348.7-130348.27" - process $proc$libresoc.v:130348$5324 + attribute \src "libresoc.v:131955.7-131955.27" + process $proc$libresoc.v:131955$5365 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:130382.14-130382.47" - process $proc$libresoc.v:130382$5325 + attribute \src "libresoc.v:131989.14-131989.47" + process $proc$libresoc.v:131989$5366 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:130386.7-130386.27" - process $proc$libresoc.v:130386$5326 + attribute \src "libresoc.v:131993.7-131993.27" + process $proc$libresoc.v:131993$5367 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:130390.13-130390.33" - process $proc$libresoc.v:130390$5327 + attribute \src "libresoc.v:131997.13-131997.33" + process $proc$libresoc.v:131997$5368 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:130394.7-130394.30" - process $proc$libresoc.v:130394$5328 + attribute \src "libresoc.v:132001.7-132001.30" + process $proc$libresoc.v:132001$5369 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:130398.13-130398.35" - process $proc$libresoc.v:130398$5329 + attribute \src "libresoc.v:132005.13-132005.35" + process $proc$libresoc.v:132005$5370 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:130402.7-130402.32" - process $proc$libresoc.v:130402$5330 + attribute \src "libresoc.v:132009.7-132009.32" + process $proc$libresoc.v:132009$5371 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:130406.7-130406.29" - process $proc$libresoc.v:130406$5331 + attribute \src "libresoc.v:132013.7-132013.29" + process $proc$libresoc.v:132013$5372 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:130410.7-130410.32" - process $proc$libresoc.v:130410$5332 + attribute \src "libresoc.v:132017.7-132017.32" + process $proc$libresoc.v:132017$5373 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:130430.7-130430.25" - process $proc$libresoc.v:130430$5333 + attribute \src "libresoc.v:132037.7-132037.25" + process $proc$libresoc.v:132037$5374 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130434.7-130434.25" - process $proc$libresoc.v:130434$5334 + attribute \src "libresoc.v:132041.7-132041.25" + process $proc$libresoc.v:132041$5375 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130568.13-130568.30" - process $proc$libresoc.v:130568$5335 + attribute \src "libresoc.v:132175.13-132175.30" + process $proc$libresoc.v:132175$5376 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:130576.13-130576.31" - process $proc$libresoc.v:130576$5336 + attribute \src "libresoc.v:132183.13-132183.31" + process $proc$libresoc.v:132183$5377 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:130580.13-130580.31" - process $proc$libresoc.v:130580$5337 + attribute \src "libresoc.v:132187.13-132187.31" + process $proc$libresoc.v:132187$5378 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:130592.7-130592.26" - process $proc$libresoc.v:130592$5338 + attribute \src "libresoc.v:132199.7-132199.26" + process $proc$libresoc.v:132199$5379 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130596.7-130596.26" - process $proc$libresoc.v:130596$5339 + attribute \src "libresoc.v:132203.7-132203.26" + process $proc$libresoc.v:132203$5380 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130600.7-130600.25" - process $proc$libresoc.v:130600$5340 + attribute \src "libresoc.v:132207.7-132207.25" + process $proc$libresoc.v:132207$5381 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130604.7-130604.25" - process $proc$libresoc.v:130604$5341 + attribute \src "libresoc.v:132211.7-132211.25" + process $proc$libresoc.v:132211$5382 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130618.13-130618.31" - process $proc$libresoc.v:130618$5342 + attribute \src "libresoc.v:132225.13-132225.31" + process $proc$libresoc.v:132225$5383 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:130622.13-130622.31" - process $proc$libresoc.v:130622$5343 + attribute \src "libresoc.v:132229.13-132229.31" + process $proc$libresoc.v:132229$5384 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:130630.14-130630.43" - process $proc$libresoc.v:130630$5344 + attribute \src "libresoc.v:132237.14-132237.43" + process $proc$libresoc.v:132237$5385 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:130634.14-130634.43" - process $proc$libresoc.v:130634$5345 + attribute \src "libresoc.v:132241.14-132241.43" + process $proc$libresoc.v:132241$5386 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:130638.7-130638.20" - process $proc$libresoc.v:130638$5346 + attribute \src "libresoc.v:132245.7-132245.20" + process $proc$libresoc.v:132245$5387 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:130714.3-130715.39" - process $proc$libresoc.v:130714$5130 + attribute \src "libresoc.v:132321.3-132322.39" + process $proc$libresoc.v:132321$5171 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:130716.3-130717.43" - process $proc$libresoc.v:130716$5131 + attribute \src "libresoc.v:132323.3-132324.43" + process $proc$libresoc.v:132323$5172 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:130718.3-130719.29" - process $proc$libresoc.v:130718$5132 + attribute \src "libresoc.v:132325.3-132326.29" + process $proc$libresoc.v:132325$5173 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:130720.3-130721.29" - process $proc$libresoc.v:130720$5133 + attribute \src "libresoc.v:132327.3-132328.29" + process $proc$libresoc.v:132327$5174 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:130722.3-130723.29" - process $proc$libresoc.v:130722$5134 + attribute \src "libresoc.v:132329.3-132330.29" + process $proc$libresoc.v:132329$5175 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:130724.3-130725.47" - process $proc$libresoc.v:130724$5135 + attribute \src "libresoc.v:132331.3-132332.47" + process $proc$libresoc.v:132331$5176 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:130726.3-130727.53" - process $proc$libresoc.v:130726$5136 + attribute \src "libresoc.v:132333.3-132334.53" + process $proc$libresoc.v:132333$5177 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:130728.3-130729.47" - process $proc$libresoc.v:130728$5137 + attribute \src "libresoc.v:132335.3-132336.47" + process $proc$libresoc.v:132335$5178 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:130730.3-130731.53" - process $proc$libresoc.v:130730$5138 + attribute \src "libresoc.v:132337.3-132338.53" + process $proc$libresoc.v:132337$5179 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:130732.3-130733.43" - process $proc$libresoc.v:130732$5139 + attribute \src "libresoc.v:132339.3-132340.43" + process $proc$libresoc.v:132339$5180 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:130734.3-130735.49" - process $proc$libresoc.v:130734$5140 + attribute \src "libresoc.v:132341.3-132342.49" + process $proc$libresoc.v:132341$5181 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:130736.3-130737.37" - process $proc$libresoc.v:130736$5141 + attribute \src "libresoc.v:132343.3-132344.37" + process $proc$libresoc.v:132343$5182 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:130738.3-130739.43" - process $proc$libresoc.v:130738$5142 + attribute \src "libresoc.v:132345.3-132346.43" + process $proc$libresoc.v:132345$5183 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:130740.3-130741.77" - process $proc$libresoc.v:130740$5143 + attribute \src "libresoc.v:132347.3-132348.77" + process $proc$libresoc.v:132347$5184 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:130742.3-130743.73" - process $proc$libresoc.v:130742$5144 + attribute \src "libresoc.v:132349.3-132350.73" + process $proc$libresoc.v:132349$5185 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:130744.3-130745.87" - process $proc$libresoc.v:130744$5145 + attribute \src "libresoc.v:132351.3-132352.87" + process $proc$libresoc.v:132351$5186 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130746.3-130747.83" - process $proc$libresoc.v:130746$5146 + attribute \src "libresoc.v:132353.3-132354.83" + process $proc$libresoc.v:132353$5187 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130748.3-130749.71" - process $proc$libresoc.v:130748$5147 + attribute \src "libresoc.v:132355.3-132356.71" + process $proc$libresoc.v:132355$5188 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:130750.3-130751.71" - process $proc$libresoc.v:130750$5148 + attribute \src "libresoc.v:132357.3-132358.71" + process $proc$libresoc.v:132357$5189 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:130752.3-130753.71" - process $proc$libresoc.v:130752$5149 + attribute \src "libresoc.v:132359.3-132360.71" + process $proc$libresoc.v:132359$5190 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:130754.3-130755.71" - process $proc$libresoc.v:130754$5150 + attribute \src "libresoc.v:132361.3-132362.71" + process $proc$libresoc.v:132361$5191 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:130756.3-130757.77" - process $proc$libresoc.v:130756$5151 + attribute \src "libresoc.v:132363.3-132364.77" + process $proc$libresoc.v:132363$5192 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:130758.3-130759.71" - process $proc$libresoc.v:130758$5152 + attribute \src "libresoc.v:132365.3-132366.71" + process $proc$libresoc.v:132365$5193 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:130760.3-130761.81" - process $proc$libresoc.v:130760$5153 + attribute \src "libresoc.v:132367.3-132368.81" + process $proc$libresoc.v:132367$5194 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:130762.3-130763.79" - process $proc$libresoc.v:130762$5154 + attribute \src "libresoc.v:132369.3-132370.79" + process $proc$libresoc.v:132369$5195 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:130764.3-130765.77" - process $proc$libresoc.v:130764$5155 + attribute \src "libresoc.v:132371.3-132372.77" + process $proc$libresoc.v:132371$5196 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:130766.3-130767.83" - process $proc$libresoc.v:130766$5156 + attribute \src "libresoc.v:132373.3-132374.83" + process $proc$libresoc.v:132373$5197 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:130768.3-130769.75" - process $proc$libresoc.v:130768$5157 + attribute \src "libresoc.v:132375.3-132376.75" + process $proc$libresoc.v:132375$5198 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:130770.3-130771.77" - process $proc$libresoc.v:130770$5158 + attribute \src "libresoc.v:132377.3-132378.77" + process $proc$libresoc.v:132377$5199 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:130772.3-130773.75" - process $proc$libresoc.v:130772$5159 + attribute \src "libresoc.v:132379.3-132380.75" + process $proc$libresoc.v:132379$5200 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:130774.3-130775.67" - process $proc$libresoc.v:130774$5160 + attribute \src "libresoc.v:132381.3-132382.67" + process $proc$libresoc.v:132381$5201 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:130776.3-130777.39" - process $proc$libresoc.v:130776$5161 + attribute \src "libresoc.v:132383.3-132384.39" + process $proc$libresoc.v:132383$5202 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:130778.3-130779.39" - process $proc$libresoc.v:130778$5162 + attribute \src "libresoc.v:132385.3-132386.39" + process $proc$libresoc.v:132385$5203 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:130780.3-130781.39" - process $proc$libresoc.v:130780$5163 + attribute \src "libresoc.v:132387.3-132388.39" + process $proc$libresoc.v:132387$5204 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:130782.3-130783.39" - process $proc$libresoc.v:130782$5164 + attribute \src "libresoc.v:132389.3-132390.39" + process $proc$libresoc.v:132389$5205 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:130784.3-130785.39" - process $proc$libresoc.v:130784$5165 + attribute \src "libresoc.v:132391.3-132392.39" + process $proc$libresoc.v:132391$5206 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130786.3-130787.39" - process $proc$libresoc.v:130786$5166 + attribute \src "libresoc.v:132393.3-132394.39" + process $proc$libresoc.v:132393$5207 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130788.3-130789.39" - process $proc$libresoc.v:130788$5167 + attribute \src "libresoc.v:132395.3-132396.39" + process $proc$libresoc.v:132395$5208 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130790.3-130791.39" - process $proc$libresoc.v:130790$5168 + attribute \src "libresoc.v:132397.3-132398.39" + process $proc$libresoc.v:132397$5209 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130792.3-130793.41" - process $proc$libresoc.v:130792$5169 + attribute \src "libresoc.v:132399.3-132400.41" + process $proc$libresoc.v:132399$5210 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130794.3-130795.41" - process $proc$libresoc.v:130794$5170 + attribute \src "libresoc.v:132401.3-132402.41" + process $proc$libresoc.v:132401$5211 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130796.3-130797.37" - process $proc$libresoc.v:130796$5171 + attribute \src "libresoc.v:132403.3-132404.37" + process $proc$libresoc.v:132403$5212 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:130798.3-130799.40" - process $proc$libresoc.v:130798$5172 + attribute \src "libresoc.v:132405.3-132406.40" + process $proc$libresoc.v:132405$5213 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:130800.3-130801.25" - process $proc$libresoc.v:130800$5173 + attribute \src "libresoc.v:132407.3-132408.25" + process $proc$libresoc.v:132407$5214 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:130887.3-130896.6" - process $proc$libresoc.v:130887$5174 + attribute \src "libresoc.v:132494.3-132503.6" + process $proc$libresoc.v:132494$5215 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:130888.5-130888.29" + attribute \src "libresoc.v:132495.5-132495.29" switch \initial - attribute \src "libresoc.v:130888.9-130888.17" + attribute \src "libresoc.v:132495.9-132495.17" case 1'1 case end @@ -207147,14 +209567,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:130897.3-130905.6" - process $proc$libresoc.v:130897$5175 + attribute \src "libresoc.v:132504.3-132512.6" + process $proc$libresoc.v:132504$5216 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5176 $1\rok_l_s_rdok$next[0:0]$5177 - attribute \src "libresoc.v:130898.5-130898.29" + assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132505.5-132505.29" switch \initial - attribute \src "libresoc.v:130898.9-130898.17" + attribute \src "libresoc.v:132505.9-132505.17" case 1'1 case end @@ -207163,21 +209583,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5177 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5218 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$5177 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$5218 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5176 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217 end - attribute \src "libresoc.v:130906.3-130914.6" - process $proc$libresoc.v:130906$5178 + attribute \src "libresoc.v:132513.3-132521.6" + process $proc$libresoc.v:132513$5219 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5179 $1\rok_l_r_rdok$next[0:0]$5180 - attribute \src "libresoc.v:130907.5-130907.29" + assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132514.5-132514.29" switch \initial - attribute \src "libresoc.v:130907.9-130907.17" + attribute \src "libresoc.v:132514.9-132514.17" case 1'1 case end @@ -207186,21 +209606,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5180 1'1 + assign $1\rok_l_r_rdok$next[0:0]$5221 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$5180 \$64 + assign $1\rok_l_r_rdok$next[0:0]$5221 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5179 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220 end - attribute \src "libresoc.v:130915.3-130923.6" - process $proc$libresoc.v:130915$5181 + attribute \src "libresoc.v:132522.3-132530.6" + process $proc$libresoc.v:132522$5222 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5182 $1\rst_l_s_rst$next[0:0]$5183 - attribute \src "libresoc.v:130916.5-130916.29" + assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132523.5-132523.29" switch \initial - attribute \src "libresoc.v:130916.9-130916.17" + attribute \src "libresoc.v:132523.9-132523.17" case 1'1 case end @@ -207209,21 +209629,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5183 1'0 + assign $1\rst_l_s_rst$next[0:0]$5224 1'0 case - assign $1\rst_l_s_rst$next[0:0]$5183 \all_rd + assign $1\rst_l_s_rst$next[0:0]$5224 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5182 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223 end - attribute \src "libresoc.v:130924.3-130932.6" - process $proc$libresoc.v:130924$5184 + attribute \src "libresoc.v:132531.3-132539.6" + process $proc$libresoc.v:132531$5225 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5185 $1\rst_l_r_rst$next[0:0]$5186 - attribute \src "libresoc.v:130925.5-130925.29" + assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132532.5-132532.29" switch \initial - attribute \src "libresoc.v:130925.9-130925.17" + attribute \src "libresoc.v:132532.9-132532.17" case 1'1 case end @@ -207232,21 +209652,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5186 1'1 + assign $1\rst_l_r_rst$next[0:0]$5227 1'1 case - assign $1\rst_l_r_rst$next[0:0]$5186 \rst_r + assign $1\rst_l_r_rst$next[0:0]$5227 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5185 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226 end - attribute \src "libresoc.v:130933.3-130941.6" - process $proc$libresoc.v:130933$5187 + attribute \src "libresoc.v:132540.3-132548.6" + process $proc$libresoc.v:132540$5228 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5188 $1\opc_l_s_opc$next[0:0]$5189 - attribute \src "libresoc.v:130934.5-130934.29" + assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132541.5-132541.29" switch \initial - attribute \src "libresoc.v:130934.9-130934.17" + attribute \src "libresoc.v:132541.9-132541.17" case 1'1 case end @@ -207255,21 +209675,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5189 1'0 + assign $1\opc_l_s_opc$next[0:0]$5230 1'0 case - assign $1\opc_l_s_opc$next[0:0]$5189 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$5230 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5188 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229 end - attribute \src "libresoc.v:130942.3-130950.6" - process $proc$libresoc.v:130942$5190 + attribute \src "libresoc.v:132549.3-132557.6" + process $proc$libresoc.v:132549$5231 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5191 $1\opc_l_r_opc$next[0:0]$5192 - attribute \src "libresoc.v:130943.5-130943.29" + assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132550.5-132550.29" switch \initial - attribute \src "libresoc.v:130943.9-130943.17" + attribute \src "libresoc.v:132550.9-132550.17" case 1'1 case end @@ -207278,21 +209698,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5192 1'1 + assign $1\opc_l_r_opc$next[0:0]$5233 1'1 case - assign $1\opc_l_r_opc$next[0:0]$5192 \req_done + assign $1\opc_l_r_opc$next[0:0]$5233 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5191 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232 end - attribute \src "libresoc.v:130951.3-130959.6" - process $proc$libresoc.v:130951$5193 + attribute \src "libresoc.v:132558.3-132566.6" + process $proc$libresoc.v:132558$5234 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$5194 $1\src_l_s_src$next[2:0]$5195 - attribute \src "libresoc.v:130952.5-130952.29" + assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132559.5-132559.29" switch \initial - attribute \src "libresoc.v:130952.9-130952.17" + attribute \src "libresoc.v:132559.9-132559.17" case 1'1 case end @@ -207301,21 +209721,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$5195 3'000 + assign $1\src_l_s_src$next[2:0]$5236 3'000 case - assign $1\src_l_s_src$next[2:0]$5195 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$5236 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5194 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235 end - attribute \src "libresoc.v:130960.3-130968.6" - process $proc$libresoc.v:130960$5196 + attribute \src "libresoc.v:132567.3-132575.6" + process $proc$libresoc.v:132567$5237 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$5197 $1\src_l_r_src$next[2:0]$5198 - attribute \src "libresoc.v:130961.5-130961.29" + assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132568.5-132568.29" switch \initial - attribute \src "libresoc.v:130961.9-130961.17" + attribute \src "libresoc.v:132568.9-132568.17" case 1'1 case end @@ -207324,21 +209744,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$5198 3'111 + assign $1\src_l_r_src$next[2:0]$5239 3'111 case - assign $1\src_l_r_src$next[2:0]$5198 \reset_r + assign $1\src_l_r_src$next[2:0]$5239 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5197 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238 end - attribute \src "libresoc.v:130969.3-130977.6" - process $proc$libresoc.v:130969$5199 + attribute \src "libresoc.v:132576.3-132584.6" + process $proc$libresoc.v:132576$5240 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$5200 $1\req_l_s_req$next[3:0]$5201 - attribute \src "libresoc.v:130970.5-130970.29" + assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132577.5-132577.29" switch \initial - attribute \src "libresoc.v:130970.9-130970.17" + attribute \src "libresoc.v:132577.9-132577.17" case 1'1 case end @@ -207347,21 +209767,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$5201 4'0000 + assign $1\req_l_s_req$next[3:0]$5242 4'0000 case - assign $1\req_l_s_req$next[3:0]$5201 \$66 + assign $1\req_l_s_req$next[3:0]$5242 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5200 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241 end - attribute \src "libresoc.v:130978.3-130986.6" - process $proc$libresoc.v:130978$5202 + attribute \src "libresoc.v:132585.3-132593.6" + process $proc$libresoc.v:132585$5243 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$5203 $1\req_l_r_req$next[3:0]$5204 - attribute \src "libresoc.v:130979.5-130979.29" + assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132586.5-132586.29" switch \initial - attribute \src "libresoc.v:130979.9-130979.17" + attribute \src "libresoc.v:132586.9-132586.17" case 1'1 case end @@ -207370,15 +209790,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$5204 4'1111 + assign $1\req_l_r_req$next[3:0]$5245 4'1111 case - assign $1\req_l_r_req$next[3:0]$5204 \$68 + assign $1\req_l_r_req$next[3:0]$5245 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5203 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244 end - attribute \src "libresoc.v:130987.3-131025.6" - process $proc$libresoc.v:130987$5205 + attribute \src "libresoc.v:132594.3-132632.6" + process $proc$libresoc.v:132594$5246 assign { } { } assign { } { } assign { } { } @@ -207415,33 +209835,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$5206 $1\alu_div0_logical_op__data_len$next[3:0]$5224 - assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 + assign $0\alu_div0_logical_op__data_len$next[3:0]$5247 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$5210 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 - assign $0\alu_div0_logical_op__insn$next[31:0]$5211 $1\alu_div0_logical_op__insn$next[31:0]$5229 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$5212 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$5213 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$5214 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$5216 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5251 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + assign $0\alu_div0_logical_op__insn$next[31:0]$5252 $1\alu_div0_logical_op__insn$next[31:0]$5270 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5253 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5254 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5255 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5257 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$5219 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5260 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$5223 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 - attribute \src "libresoc.v:130988.5-130988.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5264 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132595.5-132595.29" switch \initial - attribute \src "libresoc.v:130988.9-130988.17" + attribute \src "libresoc.v:132595.9-132595.17" case 1'1 case end @@ -207467,26 +209887,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$5229 $1\alu_div0_logical_op__data_len$next[3:0]$5224 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5270 $1\alu_div0_logical_op__data_len$next[3:0]$5265 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$5224 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$5228 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$5229 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$5230 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$5231 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$5232 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$5234 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$5237 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$5241 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$5265 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5269 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5270 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5271 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5272 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5273 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5275 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5278 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5282 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -207498,54 +209918,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5206 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5210 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5211 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5212 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5213 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5214 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5216 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5219 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5223 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5247 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5252 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264 end - attribute \src "libresoc.v:131026.3-131047.6" - process $proc$libresoc.v:131026$5248 + attribute \src "libresoc.v:132633.3-132654.6" + process $proc$libresoc.v:132633$5289 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$5249 $2\data_r0__o$next[63:0]$5253 + assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5250 $3\data_r0__o_ok$next[0:0]$5255 - attribute \src "libresoc.v:131027.5-131027.29" + assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296 + attribute \src "libresoc.v:132634.5-132634.29" switch \initial - attribute \src "libresoc.v:131027.9-131027.17" + attribute \src "libresoc.v:132634.9-132634.17" case 1'1 case end @@ -207555,10 +209975,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5252 $1\data_r0__o$next[63:0]$5251 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$5293 $1\data_r0__o$next[63:0]$5292 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$5251 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5252 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$5292 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5293 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207566,38 +209986,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5254 $2\data_r0__o$next[63:0]$5253 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o$next[63:0]$5294 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$5253 $1\data_r0__o$next[63:0]$5251 - assign $2\data_r0__o_ok$next[0:0]$5254 $1\data_r0__o_ok$next[0:0]$5252 + assign $2\data_r0__o$next[63:0]$5294 $1\data_r0__o$next[63:0]$5292 + assign $2\data_r0__o_ok$next[0:0]$5295 $1\data_r0__o_ok$next[0:0]$5293 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5255 1'0 + assign $3\data_r0__o_ok$next[0:0]$5296 1'0 case - assign $3\data_r0__o_ok$next[0:0]$5255 $2\data_r0__o_ok$next[0:0]$5254 + assign $3\data_r0__o_ok$next[0:0]$5296 $2\data_r0__o_ok$next[0:0]$5295 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5249 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5250 + update \data_r0__o$next $0\data_r0__o$next[63:0]$5290 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291 end - attribute \src "libresoc.v:131048.3-131069.6" - process $proc$libresoc.v:131048$5256 + attribute \src "libresoc.v:132655.3-132676.6" + process $proc$libresoc.v:132655$5297 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5257 $2\data_r1__cr_a$next[3:0]$5261 + assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5258 $3\data_r1__cr_a_ok$next[0:0]$5263 - attribute \src "libresoc.v:131049.5-131049.29" + assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304 + attribute \src "libresoc.v:132656.5-132656.29" switch \initial - attribute \src "libresoc.v:131049.9-131049.17" + attribute \src "libresoc.v:132656.9-132656.17" case 1'1 case end @@ -207607,10 +210027,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5260 $1\data_r1__cr_a$next[3:0]$5259 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$5301 $1\data_r1__cr_a$next[3:0]$5300 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$5259 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5260 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$5300 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5301 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207618,38 +210038,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5262 $2\data_r1__cr_a$next[3:0]$5261 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a$next[3:0]$5302 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$5261 $1\data_r1__cr_a$next[3:0]$5259 - assign $2\data_r1__cr_a_ok$next[0:0]$5262 $1\data_r1__cr_a_ok$next[0:0]$5260 + assign $2\data_r1__cr_a$next[3:0]$5302 $1\data_r1__cr_a$next[3:0]$5300 + assign $2\data_r1__cr_a_ok$next[0:0]$5303 $1\data_r1__cr_a_ok$next[0:0]$5301 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5263 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$5304 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$5263 $2\data_r1__cr_a_ok$next[0:0]$5262 + assign $3\data_r1__cr_a_ok$next[0:0]$5304 $2\data_r1__cr_a_ok$next[0:0]$5303 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5257 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5258 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299 end - attribute \src "libresoc.v:131070.3-131091.6" - process $proc$libresoc.v:131070$5264 + attribute \src "libresoc.v:132677.3-132698.6" + process $proc$libresoc.v:132677$5305 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$5265 $2\data_r2__xer_ov$next[1:0]$5269 + assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$5266 $3\data_r2__xer_ov_ok$next[0:0]$5271 - attribute \src "libresoc.v:131071.5-131071.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312 + attribute \src "libresoc.v:132678.5-132678.29" switch \initial - attribute \src "libresoc.v:131071.9-131071.17" + attribute \src "libresoc.v:132678.9-132678.17" case 1'1 case end @@ -207659,10 +210079,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$5268 $1\data_r2__xer_ov$next[1:0]$5267 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5309 $1\data_r2__xer_ov$next[1:0]$5308 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$5267 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$5268 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$5308 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5309 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207670,38 +210090,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$5270 $2\data_r2__xer_ov$next[1:0]$5269 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov$next[1:0]$5310 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$5269 $1\data_r2__xer_ov$next[1:0]$5267 - assign $2\data_r2__xer_ov_ok$next[0:0]$5270 $1\data_r2__xer_ov_ok$next[0:0]$5268 + assign $2\data_r2__xer_ov$next[1:0]$5310 $1\data_r2__xer_ov$next[1:0]$5308 + assign $2\data_r2__xer_ov_ok$next[0:0]$5311 $1\data_r2__xer_ov_ok$next[0:0]$5309 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$5271 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$5271 $2\data_r2__xer_ov_ok$next[0:0]$5270 + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 $2\data_r2__xer_ov_ok$next[0:0]$5311 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5265 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5266 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307 end - attribute \src "libresoc.v:131092.3-131113.6" - process $proc$libresoc.v:131092$5272 + attribute \src "libresoc.v:132699.3-132720.6" + process $proc$libresoc.v:132699$5313 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$5273 $2\data_r3__xer_so$next[0:0]$5277 + assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$5274 $3\data_r3__xer_so_ok$next[0:0]$5279 - attribute \src "libresoc.v:131093.5-131093.29" + assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320 + attribute \src "libresoc.v:132700.5-132700.29" switch \initial - attribute \src "libresoc.v:131093.9-131093.17" + attribute \src "libresoc.v:132700.9-132700.17" case 1'1 case end @@ -207711,10 +210131,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$5276 $1\data_r3__xer_so$next[0:0]$5275 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5316 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$5275 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$5276 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$5316 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5317 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207722,32 +210142,32 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5278 $2\data_r3__xer_so$next[0:0]$5277 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so$next[0:0]$5318 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$5277 $1\data_r3__xer_so$next[0:0]$5275 - assign $2\data_r3__xer_so_ok$next[0:0]$5278 $1\data_r3__xer_so_ok$next[0:0]$5276 + assign $2\data_r3__xer_so$next[0:0]$5318 $1\data_r3__xer_so$next[0:0]$5316 + assign $2\data_r3__xer_so_ok$next[0:0]$5319 $1\data_r3__xer_so_ok$next[0:0]$5317 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5279 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5320 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$5279 $2\data_r3__xer_so_ok$next[0:0]$5278 + assign $3\data_r3__xer_so_ok$next[0:0]$5320 $2\data_r3__xer_so_ok$next[0:0]$5319 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5273 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5274 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315 end - attribute \src "libresoc.v:131114.3-131123.6" - process $proc$libresoc.v:131114$5280 + attribute \src "libresoc.v:132721.3-132730.6" + process $proc$libresoc.v:132721$5321 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$5281 $1\src_r0$next[63:0]$5282 - attribute \src "libresoc.v:131115.5-131115.29" + assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132722.5-132722.29" switch \initial - attribute \src "libresoc.v:131115.9-131115.17" + attribute \src "libresoc.v:132722.9-132722.17" case 1'1 case end @@ -207756,21 +210176,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$5282 \src_or_imm + assign $1\src_r0$next[63:0]$5323 \src_or_imm case - assign $1\src_r0$next[63:0]$5282 \src_r0 + assign $1\src_r0$next[63:0]$5323 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$5281 + update \src_r0$next $0\src_r0$next[63:0]$5322 end - attribute \src "libresoc.v:131124.3-131133.6" - process $proc$libresoc.v:131124$5283 + attribute \src "libresoc.v:132731.3-132740.6" + process $proc$libresoc.v:132731$5324 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$5284 $1\src_r1$next[63:0]$5285 - attribute \src "libresoc.v:131125.5-131125.29" + assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132732.5-132732.29" switch \initial - attribute \src "libresoc.v:131125.9-131125.17" + attribute \src "libresoc.v:132732.9-132732.17" case 1'1 case end @@ -207779,21 +210199,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$5285 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5326 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$5285 \src_r1 + assign $1\src_r1$next[63:0]$5326 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$5284 + update \src_r1$next $0\src_r1$next[63:0]$5325 end - attribute \src "libresoc.v:131134.3-131143.6" - process $proc$libresoc.v:131134$5286 + attribute \src "libresoc.v:132741.3-132750.6" + process $proc$libresoc.v:132741$5327 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$5287 $1\src_r2$next[0:0]$5288 - attribute \src "libresoc.v:131135.5-131135.29" + assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132742.5-132742.29" switch \initial - attribute \src "libresoc.v:131135.9-131135.17" + attribute \src "libresoc.v:132742.9-132742.17" case 1'1 case end @@ -207802,21 +210222,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$5288 \src3_i + assign $1\src_r2$next[0:0]$5329 \src3_i case - assign $1\src_r2$next[0:0]$5288 \src_r2 + assign $1\src_r2$next[0:0]$5329 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$5287 + update \src_r2$next $0\src_r2$next[0:0]$5328 end - attribute \src "libresoc.v:131144.3-131152.6" - process $proc$libresoc.v:131144$5289 + attribute \src "libresoc.v:132751.3-132759.6" + process $proc$libresoc.v:132751$5330 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5290 $1\alui_l_r_alui$next[0:0]$5291 - attribute \src "libresoc.v:131145.5-131145.29" + assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:132752.5-132752.29" switch \initial - attribute \src "libresoc.v:131145.9-131145.17" + attribute \src "libresoc.v:132752.9-132752.17" case 1'1 case end @@ -207825,21 +210245,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5291 1'1 + assign $1\alui_l_r_alui$next[0:0]$5332 1'1 case - assign $1\alui_l_r_alui$next[0:0]$5291 \$94 + assign $1\alui_l_r_alui$next[0:0]$5332 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5290 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331 end - attribute \src "libresoc.v:131153.3-131161.6" - process $proc$libresoc.v:131153$5292 + attribute \src "libresoc.v:132760.3-132768.6" + process $proc$libresoc.v:132760$5333 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5293 $1\alu_l_r_alu$next[0:0]$5294 - attribute \src "libresoc.v:131154.5-131154.29" + assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:132761.5-132761.29" switch \initial - attribute \src "libresoc.v:131154.9-131154.17" + attribute \src "libresoc.v:132761.9-132761.17" case 1'1 case end @@ -207848,21 +210268,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5294 1'1 + assign $1\alu_l_r_alu$next[0:0]$5335 1'1 case - assign $1\alu_l_r_alu$next[0:0]$5294 \$96 + assign $1\alu_l_r_alu$next[0:0]$5335 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5293 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5334 end - attribute \src "libresoc.v:131162.3-131171.6" - process $proc$libresoc.v:131162$5295 + attribute \src "libresoc.v:132769.3-132778.6" + process $proc$libresoc.v:132769$5336 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:131163.5-131163.29" + attribute \src "libresoc.v:132770.5-132770.29" switch \initial - attribute \src "libresoc.v:131163.9-131163.17" + attribute \src "libresoc.v:132770.9-132770.17" case 1'1 case end @@ -207878,14 +210298,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:131172.3-131181.6" - process $proc$libresoc.v:131172$5296 + attribute \src "libresoc.v:132779.3-132788.6" + process $proc$libresoc.v:132779$5337 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:131173.5-131173.29" + attribute \src "libresoc.v:132780.5-132780.29" switch \initial - attribute \src "libresoc.v:131173.9-131173.17" + attribute \src "libresoc.v:132780.9-132780.17" case 1'1 case end @@ -207901,14 +210321,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:131182.3-131191.6" - process $proc$libresoc.v:131182$5297 + attribute \src "libresoc.v:132789.3-132798.6" + process $proc$libresoc.v:132789$5338 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:131183.5-131183.29" + attribute \src "libresoc.v:132790.5-132790.29" switch \initial - attribute \src "libresoc.v:131183.9-131183.17" + attribute \src "libresoc.v:132790.9-132790.17" case 1'1 case end @@ -207924,14 +210344,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:131192.3-131201.6" - process $proc$libresoc.v:131192$5298 + attribute \src "libresoc.v:132799.3-132808.6" + process $proc$libresoc.v:132799$5339 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:131193.5-131193.29" + attribute \src "libresoc.v:132800.5-132800.29" switch \initial - attribute \src "libresoc.v:131193.9-131193.17" + attribute \src "libresoc.v:132800.9-132800.17" case 1'1 case end @@ -207947,14 +210367,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:131202.3-131210.6" - process $proc$libresoc.v:131202$5299 + attribute \src "libresoc.v:132809.3-132817.6" + process $proc$libresoc.v:132809$5340 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$5300 $1\prev_wr_go$next[3:0]$5301 - attribute \src "libresoc.v:131203.5-131203.29" + assign $0\prev_wr_go$next[3:0]$5341 $1\prev_wr_go$next[3:0]$5342 + attribute \src "libresoc.v:132810.5-132810.29" switch \initial - attribute \src "libresoc.v:131203.9-131203.17" + attribute \src "libresoc.v:132810.9-132810.17" case 1'1 case end @@ -207963,76 +210383,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$5301 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5301 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5300 - end - connect \$100 $not$libresoc.v:130651$5067_Y - connect \$102 $not$libresoc.v:130652$5068_Y - connect \$104 $and$libresoc.v:130653$5069_Y - connect \$106 $not$libresoc.v:130654$5070_Y - connect \$108 $and$libresoc.v:130655$5071_Y - connect \$10 $and$libresoc.v:130656$5072_Y - connect \$110 $and$libresoc.v:130657$5073_Y - connect \$112 $and$libresoc.v:130658$5074_Y - connect \$114 $and$libresoc.v:130659$5075_Y - connect \$116 $and$libresoc.v:130660$5076_Y - connect \$118 $and$libresoc.v:130661$5077_Y - connect \$120 $and$libresoc.v:130662$5078_Y - connect \$122 $and$libresoc.v:130663$5079_Y - connect \$124 $and$libresoc.v:130664$5080_Y - connect \$126 $and$libresoc.v:130665$5081_Y - connect \$128 $and$libresoc.v:130666$5082_Y - connect \$12 $not$libresoc.v:130667$5083_Y - connect \$14 $and$libresoc.v:130668$5084_Y - connect \$16 $not$libresoc.v:130669$5085_Y - connect \$18 $and$libresoc.v:130670$5086_Y - connect \$20 $and$libresoc.v:130671$5087_Y - connect \$24 $not$libresoc.v:130672$5088_Y - connect \$26 $and$libresoc.v:130673$5089_Y - connect \$23 $reduce_or$libresoc.v:130674$5090_Y - connect \$22 $not$libresoc.v:130675$5091_Y - connect \$2 $and$libresoc.v:130676$5092_Y - connect \$30 $and$libresoc.v:130677$5093_Y - connect \$32 $reduce_or$libresoc.v:130678$5094_Y - connect \$34 $reduce_or$libresoc.v:130679$5095_Y - connect \$36 $or$libresoc.v:130680$5096_Y - connect \$38 $not$libresoc.v:130681$5097_Y - connect \$40 $and$libresoc.v:130682$5098_Y - connect \$42 $and$libresoc.v:130683$5099_Y - connect \$44 $eq$libresoc.v:130684$5100_Y - connect \$46 $and$libresoc.v:130685$5101_Y - connect \$48 $eq$libresoc.v:130686$5102_Y - connect \$50 $and$libresoc.v:130687$5103_Y - connect \$52 $and$libresoc.v:130688$5104_Y - connect \$54 $and$libresoc.v:130689$5105_Y - connect \$56 $or$libresoc.v:130690$5106_Y - connect \$58 $or$libresoc.v:130691$5107_Y - connect \$5 $not$libresoc.v:130692$5108_Y - connect \$60 $or$libresoc.v:130693$5109_Y - connect \$62 $or$libresoc.v:130694$5110_Y - connect \$64 $and$libresoc.v:130695$5111_Y - connect \$66 $and$libresoc.v:130696$5112_Y - connect \$68 $or$libresoc.v:130697$5113_Y - connect \$70 $and$libresoc.v:130698$5114_Y - connect \$72 $and$libresoc.v:130699$5115_Y - connect \$74 $and$libresoc.v:130700$5116_Y - connect \$76 $and$libresoc.v:130701$5117_Y - connect \$78 $ternary$libresoc.v:130702$5118_Y - connect \$7 $or$libresoc.v:130703$5119_Y - connect \$80 $ternary$libresoc.v:130704$5120_Y - connect \$83 $ternary$libresoc.v:130705$5121_Y - connect \$86 $ternary$libresoc.v:130706$5122_Y - connect \$88 $ternary$libresoc.v:130707$5123_Y - connect \$4 $reduce_and$libresoc.v:130708$5124_Y - connect \$90 $ternary$libresoc.v:130709$5125_Y - connect \$92 $ternary$libresoc.v:130710$5126_Y - connect \$94 $and$libresoc.v:130711$5127_Y - connect \$96 $and$libresoc.v:130712$5128_Y - connect \$98 $and$libresoc.v:130713$5129_Y + assign $1\prev_wr_go$next[3:0]$5342 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5342 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5341 + end + connect \$100 $not$libresoc.v:132258$5108_Y + connect \$102 $not$libresoc.v:132259$5109_Y + connect \$104 $and$libresoc.v:132260$5110_Y + connect \$106 $not$libresoc.v:132261$5111_Y + connect \$108 $and$libresoc.v:132262$5112_Y + connect \$10 $and$libresoc.v:132263$5113_Y + connect \$110 $and$libresoc.v:132264$5114_Y + connect \$112 $and$libresoc.v:132265$5115_Y + connect \$114 $and$libresoc.v:132266$5116_Y + connect \$116 $and$libresoc.v:132267$5117_Y + connect \$118 $and$libresoc.v:132268$5118_Y + connect \$120 $and$libresoc.v:132269$5119_Y + connect \$122 $and$libresoc.v:132270$5120_Y + connect \$124 $and$libresoc.v:132271$5121_Y + connect \$126 $and$libresoc.v:132272$5122_Y + connect \$128 $and$libresoc.v:132273$5123_Y + connect \$12 $not$libresoc.v:132274$5124_Y + connect \$14 $and$libresoc.v:132275$5125_Y + connect \$16 $not$libresoc.v:132276$5126_Y + connect \$18 $and$libresoc.v:132277$5127_Y + connect \$20 $and$libresoc.v:132278$5128_Y + connect \$24 $not$libresoc.v:132279$5129_Y + connect \$26 $and$libresoc.v:132280$5130_Y + connect \$23 $reduce_or$libresoc.v:132281$5131_Y + connect \$22 $not$libresoc.v:132282$5132_Y + connect \$2 $and$libresoc.v:132283$5133_Y + connect \$30 $and$libresoc.v:132284$5134_Y + connect \$32 $reduce_or$libresoc.v:132285$5135_Y + connect \$34 $reduce_or$libresoc.v:132286$5136_Y + connect \$36 $or$libresoc.v:132287$5137_Y + connect \$38 $not$libresoc.v:132288$5138_Y + connect \$40 $and$libresoc.v:132289$5139_Y + connect \$42 $and$libresoc.v:132290$5140_Y + connect \$44 $eq$libresoc.v:132291$5141_Y + connect \$46 $and$libresoc.v:132292$5142_Y + connect \$48 $eq$libresoc.v:132293$5143_Y + connect \$50 $and$libresoc.v:132294$5144_Y + connect \$52 $and$libresoc.v:132295$5145_Y + connect \$54 $and$libresoc.v:132296$5146_Y + connect \$56 $or$libresoc.v:132297$5147_Y + connect \$58 $or$libresoc.v:132298$5148_Y + connect \$5 $not$libresoc.v:132299$5149_Y + connect \$60 $or$libresoc.v:132300$5150_Y + connect \$62 $or$libresoc.v:132301$5151_Y + connect \$64 $and$libresoc.v:132302$5152_Y + connect \$66 $and$libresoc.v:132303$5153_Y + connect \$68 $or$libresoc.v:132304$5154_Y + connect \$70 $and$libresoc.v:132305$5155_Y + connect \$72 $and$libresoc.v:132306$5156_Y + connect \$74 $and$libresoc.v:132307$5157_Y + connect \$76 $and$libresoc.v:132308$5158_Y + connect \$78 $ternary$libresoc.v:132309$5159_Y + connect \$7 $or$libresoc.v:132310$5160_Y + connect \$80 $ternary$libresoc.v:132311$5161_Y + connect \$83 $ternary$libresoc.v:132312$5162_Y + connect \$86 $ternary$libresoc.v:132313$5163_Y + connect \$88 $ternary$libresoc.v:132314$5164_Y + connect \$4 $reduce_and$libresoc.v:132315$5165_Y + connect \$90 $ternary$libresoc.v:132316$5166_Y + connect \$92 $ternary$libresoc.v:132317$5167_Y + connect \$94 $and$libresoc.v:132318$5168_Y + connect \$96 $and$libresoc.v:132319$5169_Y + connect \$98 $and$libresoc.v:132320$5170_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -208066,7 +210486,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:131247.1-131256.10" +attribute \src "libresoc.v:132854.1-132863.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -208080,37 +210500,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:131260.1-131342.10" +attribute \src "libresoc.v:132867.1-132949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:131261.7-131261.20" + attribute \src "libresoc.v:132868.7-132868.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131326.3-131337.6" + attribute \src "libresoc.v:132933.3-132944.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131314.3-131325.6" + attribute \src "libresoc.v:132921.3-132932.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:131302.3-131313.6" + attribute \src "libresoc.v:132909.3-132920.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:131326.3-131337.6" + attribute \src "libresoc.v:132933.3-132944.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131314.3-131325.6" + attribute \src "libresoc.v:132921.3-132932.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:131302.3-131313.6" + attribute \src "libresoc.v:132909.3-132920.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:131296.18-131296.106" - wire width 8 $add$libresoc.v:131296$5347_Y - attribute \src "libresoc.v:131297.18-131297.109" - wire $ge$libresoc.v:131297$5348_Y - attribute \src "libresoc.v:131301.17-131301.108" - wire $ge$libresoc.v:131301$5352_Y - attribute \src "libresoc.v:131300.17-131300.101" - wire $not$libresoc.v:131300$5351_Y - attribute \src "libresoc.v:131298.17-131298.101" - wire width 127 $sshl$libresoc.v:131298$5349_Y - attribute \src "libresoc.v:131299.17-131299.109" - wire width 129 $sub$libresoc.v:131299$5350_Y + attribute \src "libresoc.v:132903.18-132903.106" + wire width 8 $add$libresoc.v:132903$5388_Y + attribute \src "libresoc.v:132904.18-132904.109" + wire $ge$libresoc.v:132904$5389_Y + attribute \src "libresoc.v:132908.17-132908.108" + wire $ge$libresoc.v:132908$5393_Y + attribute \src "libresoc.v:132907.17-132907.101" + wire $not$libresoc.v:132907$5392_Y + attribute \src "libresoc.v:132905.17-132905.101" + wire width 127 $sshl$libresoc.v:132905$5390_Y + attribute \src "libresoc.v:132906.17-132906.109" + wire width 129 $sub$libresoc.v:132906$5391_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -208135,7 +210555,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:131261.7-131261.15" + attribute \src "libresoc.v:132868.7-132868.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -208146,7 +210566,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:131296$5347 + cell $add $add$libresoc.v:132903$5388 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208154,10 +210574,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:131296$5347_Y + connect \Y $add$libresoc.v:132903$5388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:131297$5348 + cell $ge $ge$libresoc.v:132904$5389 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208165,10 +210585,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:131297$5348_Y + connect \Y $ge$libresoc.v:132904$5389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:131301$5352 + cell $ge $ge$libresoc.v:132908$5393 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208176,18 +210596,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:131301$5352_Y + connect \Y $ge$libresoc.v:132908$5393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:131300$5351 + cell $not $not$libresoc.v:132907$5392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:131300$5351_Y + connect \Y $not$libresoc.v:132907$5392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:131298$5349 + cell $sshl $sshl$libresoc.v:132905$5390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -208195,10 +210615,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:131298$5349_Y + connect \Y $sshl$libresoc.v:132905$5390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:131299$5350 + cell $sub $sub$libresoc.v:132906$5391 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -208206,23 +210626,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:131299$5350_Y + connect \Y $sub$libresoc.v:132906$5391_Y end - attribute \src "libresoc.v:131261.7-131261.20" - process $proc$libresoc.v:131261$5356 + attribute \src "libresoc.v:132868.7-132868.20" + process $proc$libresoc.v:132868$5397 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131302.3-131313.6" - process $proc$libresoc.v:131302$5353 + attribute \src "libresoc.v:132909.3-132920.6" + process $proc$libresoc.v:132909$5394 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:131303.5-131303.29" + attribute \src "libresoc.v:132910.5-132910.29" switch \initial - attribute \src "libresoc.v:131303.9-131303.17" + attribute \src "libresoc.v:132910.9-132910.17" case 1'1 case end @@ -208240,13 +210660,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:131314.3-131325.6" - process $proc$libresoc.v:131314$5354 + attribute \src "libresoc.v:132921.3-132932.6" + process $proc$libresoc.v:132921$5395 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:131315.5-131315.29" + attribute \src "libresoc.v:132922.5-132922.29" switch \initial - attribute \src "libresoc.v:131315.9-131315.17" + attribute \src "libresoc.v:132922.9-132922.17" case 1'1 case end @@ -208264,13 +210684,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:131326.3-131337.6" - process $proc$libresoc.v:131326$5355 + attribute \src "libresoc.v:132933.3-132944.6" + process $proc$libresoc.v:132933$5396 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131327.5-131327.29" + attribute \src "libresoc.v:132934.5-132934.29" switch \initial - attribute \src "libresoc.v:131327.9-131327.17" + attribute \src "libresoc.v:132934.9-132934.17" case 1'1 case end @@ -208288,18 +210708,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:131296$5347_Y - connect \$13 $ge$libresoc.v:131297$5348_Y - connect \$2 $sshl$libresoc.v:131298$5349_Y - connect \$4 $sub$libresoc.v:131299$5350_Y - connect \$6 $not$libresoc.v:131300$5351_Y - connect \$8 $ge$libresoc.v:131301$5352_Y + connect \$11 $add$libresoc.v:132903$5388_Y + connect \$13 $ge$libresoc.v:132904$5389_Y + connect \$2 $sshl$libresoc.v:132905$5390_Y + connect \$4 $sub$libresoc.v:132906$5391_Y + connect \$6 $not$libresoc.v:132907$5392_Y + connect \$8 $ge$libresoc.v:132908$5393_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:131346.1-131589.10" +attribute \src "libresoc.v:132953.1-133196.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -208547,94 +210967,94 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:131593.1-131764.10" +attribute \src "libresoc.v:133200.1-133371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:131688.3-131694.6" - wire width 3 $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 3 $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" + wire width 3 $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 3 $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:131594.7-131594.20" + attribute \src "libresoc.v:133201.7-133201.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131745.3-131754.6" + attribute \src "libresoc.v:133352.3-133361.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:131717.3-131725.6" - wire $0\ren_delay$10$next[0:0]$5387 - attribute \src "libresoc.v:131670.3-131671.43" - wire $0\ren_delay$10[0:0]$5370 - attribute \src "libresoc.v:131645.7-131645.28" - wire $0\ren_delay$10[0:0]$5407 - attribute \src "libresoc.v:131736.3-131744.6" - wire $0\ren_delay$11$next[0:0]$5391 - attribute \src "libresoc.v:131668.3-131669.43" - wire $0\ren_delay$11[0:0]$5368 - attribute \src "libresoc.v:131649.7-131649.28" + attribute \src "libresoc.v:133324.3-133332.6" + wire $0\ren_delay$10$next[0:0]$5428 + attribute \src "libresoc.v:133277.3-133278.43" + wire $0\ren_delay$10[0:0]$5411 + attribute \src "libresoc.v:133252.7-133252.28" + wire $0\ren_delay$10[0:0]$5448 + attribute \src "libresoc.v:133343.3-133351.6" + wire $0\ren_delay$11$next[0:0]$5432 + attribute \src "libresoc.v:133275.3-133276.43" wire $0\ren_delay$11[0:0]$5409 - attribute \src "libresoc.v:131698.3-131706.6" - wire $0\ren_delay$next[0:0]$5383 - attribute \src "libresoc.v:131672.3-131673.35" + attribute \src "libresoc.v:133256.7-133256.28" + wire $0\ren_delay$11[0:0]$5450 + attribute \src "libresoc.v:133305.3-133313.6" + wire $0\ren_delay$next[0:0]$5424 + attribute \src "libresoc.v:133279.3-133280.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:131707.3-131716.6" + attribute \src "libresoc.v:133314.3-133323.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:131726.3-131735.6" + attribute \src "libresoc.v:133333.3-133342.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:131745.3-131754.6" + attribute \src "libresoc.v:133352.3-133361.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:131717.3-131725.6" - wire $1\ren_delay$10$next[0:0]$5388 - attribute \src "libresoc.v:131736.3-131744.6" - wire $1\ren_delay$11$next[0:0]$5392 - attribute \src "libresoc.v:131698.3-131706.6" - wire $1\ren_delay$next[0:0]$5384 - attribute \src "libresoc.v:131643.7-131643.23" + attribute \src "libresoc.v:133324.3-133332.6" + wire $1\ren_delay$10$next[0:0]$5429 + attribute \src "libresoc.v:133343.3-133351.6" + wire $1\ren_delay$11$next[0:0]$5433 + attribute \src "libresoc.v:133305.3-133313.6" + wire $1\ren_delay$next[0:0]$5425 + attribute \src "libresoc.v:133250.7-133250.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:131707.3-131716.6" + attribute \src "libresoc.v:133314.3-133323.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:131726.3-131735.6" + attribute \src "libresoc.v:133333.3-133342.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:131695.26-131695.32" - wire width 64 $memrd$\memory$libresoc.v:131695$5379_DATA - attribute \src "libresoc.v:131696.30-131696.36" - wire width 64 $memrd$\memory$libresoc.v:131696$5380_DATA - attribute \src "libresoc.v:131697.30-131697.36" - wire width 64 $memrd$\memory$libresoc.v:131697$5381_DATA + attribute \src "libresoc.v:133302.26-133302.32" + wire width 64 $memrd$\memory$libresoc.v:133302$5420_DATA + attribute \src "libresoc.v:133303.30-133303.36" + wire width 64 $memrd$\memory$libresoc.v:133303$5421_DATA + attribute \src "libresoc.v:133304.30-133304.36" + wire width 64 $memrd$\memory$libresoc.v:133304$5422_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:131692$5365_ADDR + wire width 3 $memwr$\memory$libresoc.v:133299$5406_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131692$5365_DATA + wire width 64 $memwr$\memory$libresoc.v:133299$5406_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131692$5365_EN + wire width 64 $memwr$\memory$libresoc.v:133299$5406_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:131693$5366_ADDR + wire width 3 $memwr$\memory$libresoc.v:133300$5407_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131693$5366_DATA + wire width 64 $memwr$\memory$libresoc.v:133300$5407_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131693$5366_EN - attribute \src "libresoc.v:131685.13-131685.16" + wire width 64 $memwr$\memory$libresoc.v:133300$5407_EN + attribute \src "libresoc.v:133292.13-133292.16" wire width 3 \_0_ - attribute \src "libresoc.v:131686.13-131686.16" + attribute \src "libresoc.v:133293.13-133293.16" wire width 3 \_1_ - attribute \src "libresoc.v:131687.13-131687.16" + attribute \src "libresoc.v:133294.13-133294.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \dest1__addr @@ -208642,7 +211062,7 @@ module \fast wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "libresoc.v:131594.7-131594.15" + attribute \src "libresoc.v:133201.7-133201.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -208704,90 +211124,90 @@ module \fast wire width 64 output 11 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src2__ren - attribute \src "libresoc.v:131674.14-131674.20" + attribute \src "libresoc.v:133281.14-133281.20" memory width 64 size 8 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5394 + cell $meminit $meminit$\memory$libresoc.v:0$5435 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5394 + parameter \PRIORITY 5435 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5395 + cell $meminit $meminit$\memory$libresoc.v:0$5436 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5395 + parameter \PRIORITY 5436 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5396 + cell $meminit $meminit$\memory$libresoc.v:0$5437 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5396 + parameter \PRIORITY 5437 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5397 + cell $meminit $meminit$\memory$libresoc.v:0$5438 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5397 + parameter \PRIORITY 5438 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5398 + cell $meminit $meminit$\memory$libresoc.v:0$5439 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5398 + parameter \PRIORITY 5439 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5399 + cell $meminit $meminit$\memory$libresoc.v:0$5440 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5399 + parameter \PRIORITY 5440 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5400 + cell $meminit $meminit$\memory$libresoc.v:0$5441 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5400 + parameter \PRIORITY 5441 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5401 + cell $meminit $meminit$\memory$libresoc.v:0$5442 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5401 + parameter \PRIORITY 5442 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:131695.26-131695.32" - cell $memrd $memrd$\memory$libresoc.v:131695$5379 + attribute \src "libresoc.v:133302.26-133302.32" + cell $memrd $memrd$\memory$libresoc.v:133302$5420 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208796,11 +211216,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131695$5379_DATA + connect \DATA $memrd$\memory$libresoc.v:133302$5420_DATA connect \EN 1'x end - attribute \src "libresoc.v:131696.30-131696.36" - cell $memrd $memrd$\memory$libresoc.v:131696$5380 + attribute \src "libresoc.v:133303.30-133303.36" + cell $memrd $memrd$\memory$libresoc.v:133303$5421 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208809,11 +211229,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131696$5380_DATA + connect \DATA $memrd$\memory$libresoc.v:133303$5421_DATA connect \EN 1'x end - attribute \src "libresoc.v:131697.30-131697.36" - cell $memrd $memrd$\memory$libresoc.v:131697$5381 + attribute \src "libresoc.v:133304.30-133304.36" + cell $memrd $memrd$\memory$libresoc.v:133304$5422 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208822,95 +211242,95 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131697$5381_DATA + connect \DATA $memrd$\memory$libresoc.v:133304$5422_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5402 + cell $memwr $memwr$\memory$libresoc.v:0$5443 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5402 + parameter \PRIORITY 5443 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:131692$5365_ADDR + connect \ADDR $memwr$\memory$libresoc.v:133299$5406_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:131692$5365_DATA - connect \EN $memwr$\memory$libresoc.v:131692$5365_EN + connect \DATA $memwr$\memory$libresoc.v:133299$5406_DATA + connect \EN $memwr$\memory$libresoc.v:133299$5406_EN end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5403 + cell $memwr $memwr$\memory$libresoc.v:0$5444 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5403 + parameter \PRIORITY 5444 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:131693$5366_ADDR + connect \ADDR $memwr$\memory$libresoc.v:133300$5407_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:131693$5366_DATA - connect \EN $memwr$\memory$libresoc.v:131693$5366_EN + connect \DATA $memwr$\memory$libresoc.v:133300$5407_DATA + connect \EN $memwr$\memory$libresoc.v:133300$5407_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5410 + process $proc$libresoc.v:0$5451 sync always sync init end - attribute \src "libresoc.v:131594.7-131594.20" - process $proc$libresoc.v:131594$5404 + attribute \src "libresoc.v:133201.7-133201.20" + process $proc$libresoc.v:133201$5445 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131643.7-131643.23" - process $proc$libresoc.v:131643$5405 + attribute \src "libresoc.v:133250.7-133250.23" + process $proc$libresoc.v:133250$5446 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:131645.7-131645.28" - process $proc$libresoc.v:131645$5406 + attribute \src "libresoc.v:133252.7-133252.28" + process $proc$libresoc.v:133252$5447 assign { } { } - assign $0\ren_delay$10[0:0]$5407 1'0 + assign $0\ren_delay$10[0:0]$5448 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5407 + update \ren_delay$10 $0\ren_delay$10[0:0]$5448 end - attribute \src "libresoc.v:131649.7-131649.28" - process $proc$libresoc.v:131649$5408 + attribute \src "libresoc.v:133256.7-133256.28" + process $proc$libresoc.v:133256$5449 assign { } { } - assign $0\ren_delay$11[0:0]$5409 1'0 + assign $0\ren_delay$11[0:0]$5450 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5409 + update \ren_delay$11 $0\ren_delay$11[0:0]$5450 end - attribute \src "libresoc.v:131668.3-131669.43" - process $proc$libresoc.v:131668$5367 + attribute \src "libresoc.v:133275.3-133276.43" + process $proc$libresoc.v:133275$5408 assign { } { } - assign $0\ren_delay$11[0:0]$5368 \ren_delay$11$next + assign $0\ren_delay$11[0:0]$5409 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5368 + update \ren_delay$11 $0\ren_delay$11[0:0]$5409 end - attribute \src "libresoc.v:131670.3-131671.43" - process $proc$libresoc.v:131670$5369 + attribute \src "libresoc.v:133277.3-133278.43" + process $proc$libresoc.v:133277$5410 assign { } { } - assign $0\ren_delay$10[0:0]$5370 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5411 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5370 + update \ren_delay$10 $0\ren_delay$10[0:0]$5411 end - attribute \src "libresoc.v:131672.3-131673.35" - process $proc$libresoc.v:131672$5371 + attribute \src "libresoc.v:133279.3-133280.35" + process $proc$libresoc.v:133279$5412 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:131688.3-131694.6" - process $proc$libresoc.v:131688$5372 + attribute \src "libresoc.v:133295.3-133301.6" + process $proc$libresoc.v:133295$5413 assign { } { } assign { } { } assign { } { } @@ -208920,52 +211340,52 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 3'xxx - assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 3'xxx - assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 3'xxx + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 3'xxx + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[2:0] \src1__addr assign $0\_1_[2:0] \src2__addr assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:131692.5-131692.62" + attribute \src "libresoc.v:133299.5-133299.62" switch \issue__wen - attribute \src "libresoc.v:131692.9-131692.19" + attribute \src "libresoc.v:133299.9-133299.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 \issue__data_i - assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 \issue__data_i + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "libresoc.v:131693.5-131693.58" + attribute \src "libresoc.v:133300.5-133300.58" switch \dest1__wen - attribute \src "libresoc.v:131693.9-131693.19" + attribute \src "libresoc.v:133300.9-133300.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 \dest1__addr - assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 \dest1__addr + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:131692$5365_ADDR $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 - update $memwr$\memory$libresoc.v:131692$5365_DATA $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 - update $memwr$\memory$libresoc.v:131692$5365_EN $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 - update $memwr$\memory$libresoc.v:131693$5366_ADDR $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 - update $memwr$\memory$libresoc.v:131693$5366_DATA $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 - update $memwr$\memory$libresoc.v:131693$5366_EN $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 + update $memwr$\memory$libresoc.v:133299$5406_ADDR $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 + update $memwr$\memory$libresoc.v:133299$5406_DATA $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 + update $memwr$\memory$libresoc.v:133299$5406_EN $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 + update $memwr$\memory$libresoc.v:133300$5407_ADDR $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 + update $memwr$\memory$libresoc.v:133300$5407_DATA $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 + update $memwr$\memory$libresoc.v:133300$5407_EN $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 end - attribute \src "libresoc.v:131698.3-131706.6" - process $proc$libresoc.v:131698$5382 + attribute \src "libresoc.v:133305.3-133313.6" + process $proc$libresoc.v:133305$5423 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5383 $1\ren_delay$next[0:0]$5384 - attribute \src "libresoc.v:131699.5-131699.29" + assign $0\ren_delay$next[0:0]$5424 $1\ren_delay$next[0:0]$5425 + attribute \src "libresoc.v:133306.5-133306.29" switch \initial - attribute \src "libresoc.v:131699.9-131699.17" + attribute \src "libresoc.v:133306.9-133306.17" case 1'1 case end @@ -208974,21 +211394,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5384 1'0 + assign $1\ren_delay$next[0:0]$5425 1'0 case - assign $1\ren_delay$next[0:0]$5384 \src1__ren + assign $1\ren_delay$next[0:0]$5425 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5383 + update \ren_delay$next $0\ren_delay$next[0:0]$5424 end - attribute \src "libresoc.v:131707.3-131716.6" - process $proc$libresoc.v:131707$5385 + attribute \src "libresoc.v:133314.3-133323.6" + process $proc$libresoc.v:133314$5426 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:131708.5-131708.29" + attribute \src "libresoc.v:133315.5-133315.29" switch \initial - attribute \src "libresoc.v:131708.9-131708.17" + attribute \src "libresoc.v:133315.9-133315.17" case 1'1 case end @@ -209004,14 +211424,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:131717.3-131725.6" - process $proc$libresoc.v:131717$5386 + attribute \src "libresoc.v:133324.3-133332.6" + process $proc$libresoc.v:133324$5427 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5387 $1\ren_delay$10$next[0:0]$5388 - attribute \src "libresoc.v:131718.5-131718.29" + assign $0\ren_delay$10$next[0:0]$5428 $1\ren_delay$10$next[0:0]$5429 + attribute \src "libresoc.v:133325.5-133325.29" switch \initial - attribute \src "libresoc.v:131718.9-131718.17" + attribute \src "libresoc.v:133325.9-133325.17" case 1'1 case end @@ -209020,21 +211440,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5388 1'0 + assign $1\ren_delay$10$next[0:0]$5429 1'0 case - assign $1\ren_delay$10$next[0:0]$5388 \src2__ren + assign $1\ren_delay$10$next[0:0]$5429 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5387 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5428 end - attribute \src "libresoc.v:131726.3-131735.6" - process $proc$libresoc.v:131726$5389 + attribute \src "libresoc.v:133333.3-133342.6" + process $proc$libresoc.v:133333$5430 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:131727.5-131727.29" + attribute \src "libresoc.v:133334.5-133334.29" switch \initial - attribute \src "libresoc.v:131727.9-131727.17" + attribute \src "libresoc.v:133334.9-133334.17" case 1'1 case end @@ -209050,14 +211470,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:131736.3-131744.6" - process $proc$libresoc.v:131736$5390 + attribute \src "libresoc.v:133343.3-133351.6" + process $proc$libresoc.v:133343$5431 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5391 $1\ren_delay$11$next[0:0]$5392 - attribute \src "libresoc.v:131737.5-131737.29" + assign $0\ren_delay$11$next[0:0]$5432 $1\ren_delay$11$next[0:0]$5433 + attribute \src "libresoc.v:133344.5-133344.29" switch \initial - attribute \src "libresoc.v:131737.9-131737.17" + attribute \src "libresoc.v:133344.9-133344.17" case 1'1 case end @@ -209066,21 +211486,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5392 1'0 + assign $1\ren_delay$11$next[0:0]$5433 1'0 case - assign $1\ren_delay$11$next[0:0]$5392 \issue__ren + assign $1\ren_delay$11$next[0:0]$5433 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5391 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5432 end - attribute \src "libresoc.v:131745.3-131754.6" - process $proc$libresoc.v:131745$5393 + attribute \src "libresoc.v:133352.3-133361.6" + process $proc$libresoc.v:133352$5434 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:131746.5-131746.29" + attribute \src "libresoc.v:133353.5-133353.29" switch \initial - attribute \src "libresoc.v:131746.9-131746.17" + attribute \src "libresoc.v:133353.9-133353.17" case 1'1 case end @@ -209096,9 +211516,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:131695$5379_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:131696$5380_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:131697$5381_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:133302$5420_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:133303$5421_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:133304$5422_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -209109,14 +211529,14 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:131768.1-133718.10" +attribute \src "libresoc.v:133375.1-135325.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 257 \cr_a_ok @@ -210696,7 +213116,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:133350.8-133392.4" + attribute \src "libresoc.v:134957.8-134999.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210741,7 +213161,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:133393.11-133420.4" + attribute \src "libresoc.v:135000.11-135027.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210771,7 +213191,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133421.7-133446.4" + attribute \src "libresoc.v:135028.7-135053.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210799,7 +213219,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133447.8-133486.4" + attribute \src "libresoc.v:135054.8-135093.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210841,7 +213261,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133487.9-133541.4" + attribute \src "libresoc.v:135094.9-135148.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210898,7 +213318,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133542.12-133577.4" + attribute \src "libresoc.v:135149.12-135184.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210936,7 +213356,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133578.8-133611.4" + attribute \src "libresoc.v:135185.8-135218.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210972,7 +213392,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133612.13-133650.4" + attribute \src "libresoc.v:135219.13-135257.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211013,7 +213433,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133651.8-133683.4" + attribute \src "libresoc.v:135258.8-135290.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211048,7 +213468,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133684.9-133717.4" + attribute \src "libresoc.v:135291.9-135324.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211084,37 +213504,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:133722.1-133780.10" +attribute \src "libresoc.v:135329.1-135387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:133723.7-133723.20" + attribute \src "libresoc.v:135330.7-135330.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133768.3-133776.6" - wire $0\q_int$next[0:0]$5421 - attribute \src "libresoc.v:133766.3-133767.27" + attribute \src "libresoc.v:135375.3-135383.6" + wire $0\q_int$next[0:0]$5462 + attribute \src "libresoc.v:135373.3-135374.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:133768.3-133776.6" - wire $1\q_int$next[0:0]$5422 - attribute \src "libresoc.v:133747.7-133747.19" + attribute \src "libresoc.v:135375.3-135383.6" + wire $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135354.7-135354.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:133758.17-133758.96" - wire $and$libresoc.v:133758$5411_Y - attribute \src "libresoc.v:133763.17-133763.96" - wire $and$libresoc.v:133763$5416_Y - attribute \src "libresoc.v:133760.18-133760.95" - wire $not$libresoc.v:133760$5413_Y - attribute \src "libresoc.v:133762.17-133762.94" - wire $not$libresoc.v:133762$5415_Y - attribute \src "libresoc.v:133765.17-133765.94" - wire $not$libresoc.v:133765$5418_Y - attribute \src "libresoc.v:133759.18-133759.100" - wire $or$libresoc.v:133759$5412_Y - attribute \src "libresoc.v:133761.18-133761.101" - wire $or$libresoc.v:133761$5414_Y - attribute \src "libresoc.v:133764.17-133764.99" - wire $or$libresoc.v:133764$5417_Y + attribute \src "libresoc.v:135365.17-135365.96" + wire $and$libresoc.v:135365$5452_Y + attribute \src "libresoc.v:135370.17-135370.96" + wire $and$libresoc.v:135370$5457_Y + attribute \src "libresoc.v:135367.18-135367.95" + wire $not$libresoc.v:135367$5454_Y + attribute \src "libresoc.v:135369.17-135369.94" + wire $not$libresoc.v:135369$5456_Y + attribute \src "libresoc.v:135372.17-135372.94" + wire $not$libresoc.v:135372$5459_Y + attribute \src "libresoc.v:135366.18-135366.100" + wire $or$libresoc.v:135366$5453_Y + attribute \src "libresoc.v:135368.18-135368.101" + wire $or$libresoc.v:135368$5455_Y + attribute \src "libresoc.v:135371.17-135371.99" + wire $or$libresoc.v:135371$5458_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -211131,11 +213551,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:133723.7-133723.15" + attribute \src "libresoc.v:135330.7-135330.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -211152,7 +213572,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:133758$5411 + cell $and $and$libresoc.v:135365$5452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211160,10 +213580,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:133758$5411_Y + connect \Y $and$libresoc.v:135365$5452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:133763$5416 + cell $and $and$libresoc.v:135370$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211171,34 +213591,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:133763$5416_Y + connect \Y $and$libresoc.v:135370$5457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:133760$5413 + cell $not $not$libresoc.v:135367$5454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:133760$5413_Y + connect \Y $not$libresoc.v:135367$5454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:133762$5415 + cell $not $not$libresoc.v:135369$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:133762$5415_Y + connect \Y $not$libresoc.v:135369$5456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:133765$5418 + cell $not $not$libresoc.v:135372$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:133765$5418_Y + connect \Y $not$libresoc.v:135372$5459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:133759$5412 + cell $or $or$libresoc.v:135366$5453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211206,10 +213626,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:133759$5412_Y + connect \Y $or$libresoc.v:135366$5453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:133761$5414 + cell $or $or$libresoc.v:135368$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211217,10 +213637,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:133761$5414_Y + connect \Y $or$libresoc.v:135368$5455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:133764$5417 + cell $or $or$libresoc.v:135371$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211228,39 +213648,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:133764$5417_Y + connect \Y $or$libresoc.v:135371$5458_Y end - attribute \src "libresoc.v:133723.7-133723.20" - process $proc$libresoc.v:133723$5423 + attribute \src "libresoc.v:135330.7-135330.20" + process $proc$libresoc.v:135330$5464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133747.7-133747.19" - process $proc$libresoc.v:133747$5424 + attribute \src "libresoc.v:135354.7-135354.19" + process $proc$libresoc.v:135354$5465 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:133766.3-133767.27" - process $proc$libresoc.v:133766$5419 + attribute \src "libresoc.v:135373.3-135374.27" + process $proc$libresoc.v:135373$5460 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:133768.3-133776.6" - process $proc$libresoc.v:133768$5420 + attribute \src "libresoc.v:135375.3-135383.6" + process $proc$libresoc.v:135375$5461 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5421 $1\q_int$next[0:0]$5422 - attribute \src "libresoc.v:133769.5-133769.29" + assign $0\q_int$next[0:0]$5462 $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135376.5-135376.29" switch \initial - attribute \src "libresoc.v:133769.9-133769.17" + attribute \src "libresoc.v:135376.9-135376.17" case 1'1 case end @@ -211269,192 +213689,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5422 1'0 + assign $1\q_int$next[0:0]$5463 1'0 case - assign $1\q_int$next[0:0]$5422 \$5 + assign $1\q_int$next[0:0]$5463 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5421 + update \q_int$next $0\q_int$next[0:0]$5462 end - connect \$9 $and$libresoc.v:133758$5411_Y - connect \$11 $or$libresoc.v:133759$5412_Y - connect \$13 $not$libresoc.v:133760$5413_Y - connect \$15 $or$libresoc.v:133761$5414_Y - connect \$1 $not$libresoc.v:133762$5415_Y - connect \$3 $and$libresoc.v:133763$5416_Y - connect \$5 $or$libresoc.v:133764$5417_Y - connect \$7 $not$libresoc.v:133765$5418_Y + connect \$9 $and$libresoc.v:135365$5452_Y + connect \$11 $or$libresoc.v:135366$5453_Y + connect \$13 $not$libresoc.v:135367$5454_Y + connect \$15 $or$libresoc.v:135368$5455_Y + connect \$1 $not$libresoc.v:135369$5456_Y + connect \$3 $and$libresoc.v:135370$5457_Y + connect \$5 $or$libresoc.v:135371$5458_Y + connect \$7 $not$libresoc.v:135372$5459_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:133784.1-134163.10" +attribute \src "libresoc.v:135391.1-135770.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:134115.3-134124.6" + attribute \src "libresoc.v:135722.3-135731.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5493 - attribute \src "libresoc.v:133926.3-133927.39" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5534 + attribute \src "libresoc.v:135533.3-135534.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135732.3-135749.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $0\f_fetch_err_o$next[0:0]$5488 - attribute \src "libresoc.v:133928.3-133929.43" + attribute \src "libresoc.v:135679.3-135701.6" + wire $0\f_fetch_err_o$next[0:0]$5529 + attribute \src "libresoc.v:135535.3-135536.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $0\ibus__adr$next[44:0]$5483 - attribute \src "libresoc.v:133930.3-133931.35" + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $0\ibus__adr$next[44:0]$5524 + attribute \src "libresoc.v:135537.3-135538.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:133940.3-133967.6" - wire $0\ibus__cyc$next[0:0]$5459 - attribute \src "libresoc.v:133938.3-133939.35" + attribute \src "libresoc.v:135547.3-135574.6" + wire $0\ibus__cyc$next[0:0]$5500 + attribute \src "libresoc.v:135545.3-135546.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $0\ibus__sel$next[7:0]$5471 - attribute \src "libresoc.v:133934.3-133935.35" + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $0\ibus__sel$next[7:0]$5512 + attribute \src "libresoc.v:135541.3-135542.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:133968.3-133995.6" - wire $0\ibus__stb$next[0:0]$5465 - attribute \src "libresoc.v:133936.3-133937.35" + attribute \src "libresoc.v:135575.3-135602.6" + wire $0\ibus__stb$next[0:0]$5506 + attribute \src "libresoc.v:135543.3-135544.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $0\ibus_rdata$next[63:0]$5477 - attribute \src "libresoc.v:133932.3-133933.37" + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $0\ibus_rdata$next[63:0]$5518 + attribute \src "libresoc.v:135539.3-135540.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:133785.7-133785.20" + attribute \src "libresoc.v:135392.7-135392.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134115.3-134124.6" + attribute \src "libresoc.v:135722.3-135731.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5494 - attribute \src "libresoc.v:133849.14-133849.44" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5535 + attribute \src "libresoc.v:135456.14-135456.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135732.3-135749.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $1\f_fetch_err_o$next[0:0]$5489 - attribute \src "libresoc.v:133856.7-133856.27" + attribute \src "libresoc.v:135679.3-135701.6" + wire $1\f_fetch_err_o$next[0:0]$5530 + attribute \src "libresoc.v:135463.7-135463.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $1\ibus__adr$next[44:0]$5484 - attribute \src "libresoc.v:133870.14-133870.42" + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $1\ibus__adr$next[44:0]$5525 + attribute \src "libresoc.v:135477.14-135477.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:133940.3-133967.6" - wire $1\ibus__cyc$next[0:0]$5460 - attribute \src "libresoc.v:133875.7-133875.23" + attribute \src "libresoc.v:135547.3-135574.6" + wire $1\ibus__cyc$next[0:0]$5501 + attribute \src "libresoc.v:135482.7-135482.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $1\ibus__sel$next[7:0]$5472 - attribute \src "libresoc.v:133884.13-133884.30" + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $1\ibus__sel$next[7:0]$5513 + attribute \src "libresoc.v:135491.13-135491.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:133968.3-133995.6" - wire $1\ibus__stb$next[0:0]$5466 - attribute \src "libresoc.v:133889.7-133889.23" + attribute \src "libresoc.v:135575.3-135602.6" + wire $1\ibus__stb$next[0:0]$5507 + attribute \src "libresoc.v:135496.7-135496.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $1\ibus_rdata$next[63:0]$5478 - attribute \src "libresoc.v:133893.14-133893.47" + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $1\ibus_rdata$next[63:0]$5519 + attribute \src "libresoc.v:135500.14-135500.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5495 - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5536 + attribute \src "libresoc.v:135732.3-135749.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $2\f_fetch_err_o$next[0:0]$5490 - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135679.3-135701.6" + wire $2\f_fetch_err_o$next[0:0]$5531 + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $2\ibus__adr$next[44:0]$5485 - attribute \src "libresoc.v:133940.3-133967.6" - wire $2\ibus__cyc$next[0:0]$5461 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $2\ibus__sel$next[7:0]$5473 - attribute \src "libresoc.v:133968.3-133995.6" - wire $2\ibus__stb$next[0:0]$5467 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $2\ibus_rdata$next[63:0]$5479 - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5496 - attribute \src "libresoc.v:134072.3-134094.6" - wire $3\f_fetch_err_o$next[0:0]$5491 - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $3\ibus__adr$next[44:0]$5486 - attribute \src "libresoc.v:133940.3-133967.6" - wire $3\ibus__cyc$next[0:0]$5462 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $3\ibus__sel$next[7:0]$5474 - attribute \src "libresoc.v:133968.3-133995.6" - wire $3\ibus__stb$next[0:0]$5468 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $3\ibus_rdata$next[63:0]$5480 - attribute \src "libresoc.v:133940.3-133967.6" - wire $4\ibus__cyc$next[0:0]$5463 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $4\ibus__sel$next[7:0]$5475 - attribute \src "libresoc.v:133968.3-133995.6" - wire $4\ibus__stb$next[0:0]$5469 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $4\ibus_rdata$next[63:0]$5481 - attribute \src "libresoc.v:133902.18-133902.110" - wire $and$libresoc.v:133902$5427_Y - attribute \src "libresoc.v:133908.18-133908.110" - wire $and$libresoc.v:133908$5433_Y - attribute \src "libresoc.v:133913.18-133913.110" - wire $and$libresoc.v:133913$5438_Y - attribute \src "libresoc.v:133916.17-133916.108" - wire $and$libresoc.v:133916$5441_Y - attribute \src "libresoc.v:133919.18-133919.110" - wire $and$libresoc.v:133919$5444_Y - attribute \src "libresoc.v:133920.18-133920.115" - wire $and$libresoc.v:133920$5445_Y - attribute \src "libresoc.v:133922.18-133922.115" - wire $and$libresoc.v:133922$5447_Y - attribute \src "libresoc.v:133901.18-133901.105" - wire $not$libresoc.v:133901$5426_Y - attribute \src "libresoc.v:133904.18-133904.105" - wire $not$libresoc.v:133904$5429_Y - attribute \src "libresoc.v:133905.17-133905.104" - wire $not$libresoc.v:133905$5430_Y - attribute \src "libresoc.v:133907.18-133907.105" - wire $not$libresoc.v:133907$5432_Y - attribute \src "libresoc.v:133910.18-133910.105" - wire $not$libresoc.v:133910$5435_Y - attribute \src "libresoc.v:133912.18-133912.105" - wire $not$libresoc.v:133912$5437_Y - attribute \src "libresoc.v:133915.18-133915.105" - wire $not$libresoc.v:133915$5440_Y - attribute \src "libresoc.v:133918.18-133918.105" - wire $not$libresoc.v:133918$5443_Y - attribute \src "libresoc.v:133921.18-133921.105" - wire $not$libresoc.v:133921$5446_Y - attribute \src "libresoc.v:133923.18-133923.105" - wire $not$libresoc.v:133923$5448_Y - attribute \src "libresoc.v:133925.17-133925.104" - wire $not$libresoc.v:133925$5450_Y - attribute \src "libresoc.v:133900.17-133900.103" - wire $or$libresoc.v:133900$5425_Y - attribute \src "libresoc.v:133903.18-133903.115" - wire $or$libresoc.v:133903$5428_Y - attribute \src "libresoc.v:133906.18-133906.106" - wire $or$libresoc.v:133906$5431_Y - attribute \src "libresoc.v:133909.18-133909.115" - wire $or$libresoc.v:133909$5434_Y - attribute \src "libresoc.v:133911.18-133911.106" - wire $or$libresoc.v:133911$5436_Y - attribute \src "libresoc.v:133914.18-133914.115" - wire $or$libresoc.v:133914$5439_Y - attribute \src "libresoc.v:133917.18-133917.106" - wire $or$libresoc.v:133917$5442_Y - attribute \src "libresoc.v:133924.17-133924.114" - wire $or$libresoc.v:133924$5449_Y + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $2\ibus__adr$next[44:0]$5526 + attribute \src "libresoc.v:135547.3-135574.6" + wire $2\ibus__cyc$next[0:0]$5502 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $2\ibus__sel$next[7:0]$5514 + attribute \src "libresoc.v:135575.3-135602.6" + wire $2\ibus__stb$next[0:0]$5508 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $2\ibus_rdata$next[63:0]$5520 + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5537 + attribute \src "libresoc.v:135679.3-135701.6" + wire $3\f_fetch_err_o$next[0:0]$5532 + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $3\ibus__adr$next[44:0]$5527 + attribute \src "libresoc.v:135547.3-135574.6" + wire $3\ibus__cyc$next[0:0]$5503 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $3\ibus__sel$next[7:0]$5515 + attribute \src "libresoc.v:135575.3-135602.6" + wire $3\ibus__stb$next[0:0]$5509 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $3\ibus_rdata$next[63:0]$5521 + attribute \src "libresoc.v:135547.3-135574.6" + wire $4\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $4\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:135575.3-135602.6" + wire $4\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $4\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:135509.18-135509.110" + wire $and$libresoc.v:135509$5468_Y + attribute \src "libresoc.v:135515.18-135515.110" + wire $and$libresoc.v:135515$5474_Y + attribute \src "libresoc.v:135520.18-135520.110" + wire $and$libresoc.v:135520$5479_Y + attribute \src "libresoc.v:135523.17-135523.108" + wire $and$libresoc.v:135523$5482_Y + attribute \src "libresoc.v:135526.18-135526.110" + wire $and$libresoc.v:135526$5485_Y + attribute \src "libresoc.v:135527.18-135527.115" + wire $and$libresoc.v:135527$5486_Y + attribute \src "libresoc.v:135529.18-135529.115" + wire $and$libresoc.v:135529$5488_Y + attribute \src "libresoc.v:135508.18-135508.105" + wire $not$libresoc.v:135508$5467_Y + attribute \src "libresoc.v:135511.18-135511.105" + wire $not$libresoc.v:135511$5470_Y + attribute \src "libresoc.v:135512.17-135512.104" + wire $not$libresoc.v:135512$5471_Y + attribute \src "libresoc.v:135514.18-135514.105" + wire $not$libresoc.v:135514$5473_Y + attribute \src "libresoc.v:135517.18-135517.105" + wire $not$libresoc.v:135517$5476_Y + attribute \src "libresoc.v:135519.18-135519.105" + wire $not$libresoc.v:135519$5478_Y + attribute \src "libresoc.v:135522.18-135522.105" + wire $not$libresoc.v:135522$5481_Y + attribute \src "libresoc.v:135525.18-135525.105" + wire $not$libresoc.v:135525$5484_Y + attribute \src "libresoc.v:135528.18-135528.105" + wire $not$libresoc.v:135528$5487_Y + attribute \src "libresoc.v:135530.18-135530.105" + wire $not$libresoc.v:135530$5489_Y + attribute \src "libresoc.v:135532.17-135532.104" + wire $not$libresoc.v:135532$5491_Y + attribute \src "libresoc.v:135507.17-135507.103" + wire $or$libresoc.v:135507$5466_Y + attribute \src "libresoc.v:135510.18-135510.115" + wire $or$libresoc.v:135510$5469_Y + attribute \src "libresoc.v:135513.18-135513.106" + wire $or$libresoc.v:135513$5472_Y + attribute \src "libresoc.v:135516.18-135516.115" + wire $or$libresoc.v:135516$5475_Y + attribute \src "libresoc.v:135518.18-135518.106" + wire $or$libresoc.v:135518$5477_Y + attribute \src "libresoc.v:135521.18-135521.115" + wire $or$libresoc.v:135521$5480_Y + attribute \src "libresoc.v:135524.18-135524.106" + wire $or$libresoc.v:135524$5483_Y + attribute \src "libresoc.v:135531.17-135531.114" + wire $or$libresoc.v:135531$5490_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -211515,7 +213935,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -211559,14 +213979,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:133785.7-133785.15" + attribute \src "libresoc.v:135392.7-135392.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133902$5427 + cell $and $and$libresoc.v:135509$5468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211574,10 +213994,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:133902$5427_Y + connect \Y $and$libresoc.v:135509$5468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133908$5433 + cell $and $and$libresoc.v:135515$5474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211585,10 +214005,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:133908$5433_Y + connect \Y $and$libresoc.v:135515$5474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133913$5438 + cell $and $and$libresoc.v:135520$5479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211596,10 +214016,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:133913$5438_Y + connect \Y $and$libresoc.v:135520$5479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133916$5441 + cell $and $and$libresoc.v:135523$5482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211607,10 +214027,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:133916$5441_Y + connect \Y $and$libresoc.v:135523$5482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133919$5444 + cell $and $and$libresoc.v:135526$5485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211618,10 +214038,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:133919$5444_Y + connect \Y $and$libresoc.v:135526$5485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:133920$5445 + cell $and $and$libresoc.v:135527$5486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211629,10 +214049,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:133920$5445_Y + connect \Y $and$libresoc.v:135527$5486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:133922$5447 + cell $and $and$libresoc.v:135529$5488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211640,98 +214060,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:133922$5447_Y + connect \Y $and$libresoc.v:135529$5488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133901$5426 + cell $not $not$libresoc.v:135508$5467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133901$5426_Y + connect \Y $not$libresoc.v:135508$5467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133904$5429 + cell $not $not$libresoc.v:135511$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133904$5429_Y + connect \Y $not$libresoc.v:135511$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133905$5430 + cell $not $not$libresoc.v:135512$5471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133905$5430_Y + connect \Y $not$libresoc.v:135512$5471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133907$5432 + cell $not $not$libresoc.v:135514$5473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133907$5432_Y + connect \Y $not$libresoc.v:135514$5473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133910$5435 + cell $not $not$libresoc.v:135517$5476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133910$5435_Y + connect \Y $not$libresoc.v:135517$5476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133912$5437 + cell $not $not$libresoc.v:135519$5478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133912$5437_Y + connect \Y $not$libresoc.v:135519$5478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133915$5440 + cell $not $not$libresoc.v:135522$5481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133915$5440_Y + connect \Y $not$libresoc.v:135522$5481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133918$5443 + cell $not $not$libresoc.v:135525$5484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133918$5443_Y + connect \Y $not$libresoc.v:135525$5484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:133921$5446 + cell $not $not$libresoc.v:135528$5487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:133921$5446_Y + connect \Y $not$libresoc.v:135528$5487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:133923$5448 + cell $not $not$libresoc.v:135530$5489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:133923$5448_Y + connect \Y $not$libresoc.v:135530$5489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133925$5450 + cell $not $not$libresoc.v:135532$5491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133925$5450_Y + connect \Y $not$libresoc.v:135532$5491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133900$5425 + cell $or $or$libresoc.v:135507$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211739,10 +214159,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:133900$5425_Y + connect \Y $or$libresoc.v:135507$5466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133903$5428 + cell $or $or$libresoc.v:135510$5469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211750,10 +214170,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133903$5428_Y + connect \Y $or$libresoc.v:135510$5469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133906$5431 + cell $or $or$libresoc.v:135513$5472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211761,10 +214181,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:133906$5431_Y + connect \Y $or$libresoc.v:135513$5472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133909$5434 + cell $or $or$libresoc.v:135516$5475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211772,10 +214192,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133909$5434_Y + connect \Y $or$libresoc.v:135516$5475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133911$5436 + cell $or $or$libresoc.v:135518$5477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211783,10 +214203,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:133911$5436_Y + connect \Y $or$libresoc.v:135518$5477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133914$5439 + cell $or $or$libresoc.v:135521$5480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211794,10 +214214,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133914$5439_Y + connect \Y $or$libresoc.v:135521$5480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133917$5442 + cell $or $or$libresoc.v:135524$5483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211805,10 +214225,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:133917$5442_Y + connect \Y $or$libresoc.v:135524$5483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133924$5449 + cell $or $or$libresoc.v:135531$5490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211816,130 +214236,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133924$5449_Y + connect \Y $or$libresoc.v:135531$5490_Y end - attribute \src "libresoc.v:133785.7-133785.20" - process $proc$libresoc.v:133785$5500 + attribute \src "libresoc.v:135392.7-135392.20" + process $proc$libresoc.v:135392$5541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133849.14-133849.44" - process $proc$libresoc.v:133849$5501 + attribute \src "libresoc.v:135456.14-135456.44" + process $proc$libresoc.v:135456$5542 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:133856.7-133856.27" - process $proc$libresoc.v:133856$5502 + attribute \src "libresoc.v:135463.7-135463.27" + process $proc$libresoc.v:135463$5543 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:133870.14-133870.42" - process $proc$libresoc.v:133870$5503 + attribute \src "libresoc.v:135477.14-135477.42" + process $proc$libresoc.v:135477$5544 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:133875.7-133875.23" - process $proc$libresoc.v:133875$5504 + attribute \src "libresoc.v:135482.7-135482.23" + process $proc$libresoc.v:135482$5545 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:133884.13-133884.30" - process $proc$libresoc.v:133884$5505 + attribute \src "libresoc.v:135491.13-135491.30" + process $proc$libresoc.v:135491$5546 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:133889.7-133889.23" - process $proc$libresoc.v:133889$5506 + attribute \src "libresoc.v:135496.7-135496.23" + process $proc$libresoc.v:135496$5547 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:133893.14-133893.47" - process $proc$libresoc.v:133893$5507 + attribute \src "libresoc.v:135500.14-135500.47" + process $proc$libresoc.v:135500$5548 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:133926.3-133927.39" - process $proc$libresoc.v:133926$5451 + attribute \src "libresoc.v:135533.3-135534.39" + process $proc$libresoc.v:135533$5492 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:133928.3-133929.43" - process $proc$libresoc.v:133928$5452 + attribute \src "libresoc.v:135535.3-135536.43" + process $proc$libresoc.v:135535$5493 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:133930.3-133931.35" - process $proc$libresoc.v:133930$5453 + attribute \src "libresoc.v:135537.3-135538.35" + process $proc$libresoc.v:135537$5494 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:133932.3-133933.37" - process $proc$libresoc.v:133932$5454 + attribute \src "libresoc.v:135539.3-135540.37" + process $proc$libresoc.v:135539$5495 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:133934.3-133935.35" - process $proc$libresoc.v:133934$5455 + attribute \src "libresoc.v:135541.3-135542.35" + process $proc$libresoc.v:135541$5496 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:133936.3-133937.35" - process $proc$libresoc.v:133936$5456 + attribute \src "libresoc.v:135543.3-135544.35" + process $proc$libresoc.v:135543$5497 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:133938.3-133939.35" - process $proc$libresoc.v:133938$5457 + attribute \src "libresoc.v:135545.3-135546.35" + process $proc$libresoc.v:135545$5498 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:133940.3-133967.6" - process $proc$libresoc.v:133940$5458 + attribute \src "libresoc.v:135547.3-135574.6" + process $proc$libresoc.v:135547$5499 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5459 $4\ibus__cyc$next[0:0]$5463 - attribute \src "libresoc.v:133941.5-133941.29" + assign $0\ibus__cyc$next[0:0]$5500 $4\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:135548.5-135548.29" switch \initial - attribute \src "libresoc.v:133941.9-133941.17" + attribute \src "libresoc.v:135548.9-135548.17" case 1'1 case end @@ -211948,53 +214368,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5460 $2\ibus__cyc$next[0:0]$5461 + assign $1\ibus__cyc$next[0:0]$5501 $2\ibus__cyc$next[0:0]$5502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5461 $3\ibus__cyc$next[0:0]$5462 + assign $2\ibus__cyc$next[0:0]$5502 $3\ibus__cyc$next[0:0]$5503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5462 1'0 + assign $3\ibus__cyc$next[0:0]$5503 1'0 case - assign $3\ibus__cyc$next[0:0]$5462 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5503 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5461 1'1 + assign $2\ibus__cyc$next[0:0]$5502 1'1 case - assign $2\ibus__cyc$next[0:0]$5461 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5502 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5460 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5501 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5463 1'0 + assign $4\ibus__cyc$next[0:0]$5504 1'0 case - assign $4\ibus__cyc$next[0:0]$5463 $1\ibus__cyc$next[0:0]$5460 + assign $4\ibus__cyc$next[0:0]$5504 $1\ibus__cyc$next[0:0]$5501 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5459 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5500 end - attribute \src "libresoc.v:133968.3-133995.6" - process $proc$libresoc.v:133968$5464 + attribute \src "libresoc.v:135575.3-135602.6" + process $proc$libresoc.v:135575$5505 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5465 $4\ibus__stb$next[0:0]$5469 - attribute \src "libresoc.v:133969.5-133969.29" + assign $0\ibus__stb$next[0:0]$5506 $4\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:135576.5-135576.29" switch \initial - attribute \src "libresoc.v:133969.9-133969.17" + attribute \src "libresoc.v:135576.9-135576.17" case 1'1 case end @@ -212003,53 +214423,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5466 $2\ibus__stb$next[0:0]$5467 + assign $1\ibus__stb$next[0:0]$5507 $2\ibus__stb$next[0:0]$5508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5467 $3\ibus__stb$next[0:0]$5468 + assign $2\ibus__stb$next[0:0]$5508 $3\ibus__stb$next[0:0]$5509 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5468 1'0 + assign $3\ibus__stb$next[0:0]$5509 1'0 case - assign $3\ibus__stb$next[0:0]$5468 \ibus__stb + assign $3\ibus__stb$next[0:0]$5509 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5467 1'1 + assign $2\ibus__stb$next[0:0]$5508 1'1 case - assign $2\ibus__stb$next[0:0]$5467 \ibus__stb + assign $2\ibus__stb$next[0:0]$5508 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5466 \ibus__stb + assign $1\ibus__stb$next[0:0]$5507 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5469 1'0 + assign $4\ibus__stb$next[0:0]$5510 1'0 case - assign $4\ibus__stb$next[0:0]$5469 $1\ibus__stb$next[0:0]$5466 + assign $4\ibus__stb$next[0:0]$5510 $1\ibus__stb$next[0:0]$5507 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5465 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5506 end - attribute \src "libresoc.v:133996.3-134023.6" - process $proc$libresoc.v:133996$5470 + attribute \src "libresoc.v:135603.3-135630.6" + process $proc$libresoc.v:135603$5511 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5471 $4\ibus__sel$next[7:0]$5475 - attribute \src "libresoc.v:133997.5-133997.29" + assign $0\ibus__sel$next[7:0]$5512 $4\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:135604.5-135604.29" switch \initial - attribute \src "libresoc.v:133997.9-133997.17" + attribute \src "libresoc.v:135604.9-135604.17" case 1'1 case end @@ -212058,53 +214478,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5472 $2\ibus__sel$next[7:0]$5473 + assign $1\ibus__sel$next[7:0]$5513 $2\ibus__sel$next[7:0]$5514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5473 $3\ibus__sel$next[7:0]$5474 + assign $2\ibus__sel$next[7:0]$5514 $3\ibus__sel$next[7:0]$5515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5474 8'00000000 + assign $3\ibus__sel$next[7:0]$5515 8'00000000 case - assign $3\ibus__sel$next[7:0]$5474 \ibus__sel + assign $3\ibus__sel$next[7:0]$5515 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5473 8'11111111 + assign $2\ibus__sel$next[7:0]$5514 8'11111111 case - assign $2\ibus__sel$next[7:0]$5473 \ibus__sel + assign $2\ibus__sel$next[7:0]$5514 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5472 \ibus__sel + assign $1\ibus__sel$next[7:0]$5513 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5475 8'00000000 + assign $4\ibus__sel$next[7:0]$5516 8'00000000 case - assign $4\ibus__sel$next[7:0]$5475 $1\ibus__sel$next[7:0]$5472 + assign $4\ibus__sel$next[7:0]$5516 $1\ibus__sel$next[7:0]$5513 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5471 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5512 end - attribute \src "libresoc.v:134024.3-134048.6" - process $proc$libresoc.v:134024$5476 + attribute \src "libresoc.v:135631.3-135655.6" + process $proc$libresoc.v:135631$5517 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5477 $4\ibus_rdata$next[63:0]$5481 - attribute \src "libresoc.v:134025.5-134025.29" + assign $0\ibus_rdata$next[63:0]$5518 $4\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:135632.5-135632.29" switch \initial - attribute \src "libresoc.v:134025.9-134025.17" + attribute \src "libresoc.v:135632.9-135632.17" case 1'1 case end @@ -212113,49 +214533,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5478 $2\ibus_rdata$next[63:0]$5479 + assign $1\ibus_rdata$next[63:0]$5519 $2\ibus_rdata$next[63:0]$5520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5479 $3\ibus_rdata$next[63:0]$5480 + assign $2\ibus_rdata$next[63:0]$5520 $3\ibus_rdata$next[63:0]$5521 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5480 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5521 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5480 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5521 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5479 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5520 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5478 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5519 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5481 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5522 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5481 $1\ibus_rdata$next[63:0]$5478 + assign $4\ibus_rdata$next[63:0]$5522 $1\ibus_rdata$next[63:0]$5519 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5477 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5518 end - attribute \src "libresoc.v:134049.3-134071.6" - process $proc$libresoc.v:134049$5482 + attribute \src "libresoc.v:135656.3-135678.6" + process $proc$libresoc.v:135656$5523 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5483 $3\ibus__adr$next[44:0]$5486 - attribute \src "libresoc.v:134050.5-134050.29" + assign $0\ibus__adr$next[44:0]$5524 $3\ibus__adr$next[44:0]$5527 + attribute \src "libresoc.v:135657.5-135657.29" switch \initial - attribute \src "libresoc.v:134050.9-134050.17" + attribute \src "libresoc.v:135657.9-135657.17" case 1'1 case end @@ -212164,43 +214584,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5484 $2\ibus__adr$next[44:0]$5485 + assign $1\ibus__adr$next[44:0]$5525 $2\ibus__adr$next[44:0]$5526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5485 \ibus__adr + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5485 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5526 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5485 \ibus__adr + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5484 \ibus__adr + assign $1\ibus__adr$next[44:0]$5525 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5486 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5527 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5486 $1\ibus__adr$next[44:0]$5484 + assign $3\ibus__adr$next[44:0]$5527 $1\ibus__adr$next[44:0]$5525 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5483 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5524 end - attribute \src "libresoc.v:134072.3-134094.6" - process $proc$libresoc.v:134072$5487 + attribute \src "libresoc.v:135679.3-135701.6" + process $proc$libresoc.v:135679$5528 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5488 $3\f_fetch_err_o$next[0:0]$5491 - attribute \src "libresoc.v:134073.5-134073.29" + assign $0\f_fetch_err_o$next[0:0]$5529 $3\f_fetch_err_o$next[0:0]$5532 + attribute \src "libresoc.v:135680.5-135680.29" switch \initial - attribute \src "libresoc.v:134073.9-134073.17" + attribute \src "libresoc.v:135680.9-135680.17" case 1'1 case end @@ -212209,44 +214629,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5489 $2\f_fetch_err_o$next[0:0]$5490 + assign $1\f_fetch_err_o$next[0:0]$5530 $2\f_fetch_err_o$next[0:0]$5531 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5490 1'1 + assign $2\f_fetch_err_o$next[0:0]$5531 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5490 1'0 + assign $2\f_fetch_err_o$next[0:0]$5531 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5490 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5531 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5489 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5491 1'0 + assign $3\f_fetch_err_o$next[0:0]$5532 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5491 $1\f_fetch_err_o$next[0:0]$5489 + assign $3\f_fetch_err_o$next[0:0]$5532 $1\f_fetch_err_o$next[0:0]$5530 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5488 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5529 end - attribute \src "libresoc.v:134095.3-134114.6" - process $proc$libresoc.v:134095$5492 + attribute \src "libresoc.v:135702.3-135721.6" + process $proc$libresoc.v:135702$5533 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5493 $3\f_badaddr_o$next[44:0]$5496 - attribute \src "libresoc.v:134096.5-134096.29" + assign $0\f_badaddr_o$next[44:0]$5534 $3\f_badaddr_o$next[44:0]$5537 + attribute \src "libresoc.v:135703.5-135703.29" switch \initial - attribute \src "libresoc.v:134096.9-134096.17" + attribute \src "libresoc.v:135703.9-135703.17" case 1'1 case end @@ -212255,39 +214675,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5494 $2\f_badaddr_o$next[44:0]$5495 + assign $1\f_badaddr_o$next[44:0]$5535 $2\f_badaddr_o$next[44:0]$5536 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5495 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5536 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5495 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5536 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5494 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5535 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5496 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5537 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5496 $1\f_badaddr_o$next[44:0]$5494 + assign $3\f_badaddr_o$next[44:0]$5537 $1\f_badaddr_o$next[44:0]$5535 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5493 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5534 end - attribute \src "libresoc.v:134115.3-134124.6" - process $proc$libresoc.v:134115$5497 + attribute \src "libresoc.v:135722.3-135731.6" + process $proc$libresoc.v:135722$5538 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:134116.5-134116.29" + attribute \src "libresoc.v:135723.5-135723.29" switch \initial - attribute \src "libresoc.v:134116.9-134116.17" + attribute \src "libresoc.v:135723.9-135723.17" case 1'1 case end @@ -212303,14 +214723,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:134125.3-134142.6" - process $proc$libresoc.v:134125$5498 + attribute \src "libresoc.v:135732.3-135749.6" + process $proc$libresoc.v:135732$5539 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:134126.5-134126.29" + attribute \src "libresoc.v:135733.5-135733.29" switch \initial - attribute \src "libresoc.v:134126.9-134126.17" + attribute \src "libresoc.v:135733.9-135733.17" case 1'1 case end @@ -212337,14 +214757,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:134143.3-134160.6" - process $proc$libresoc.v:134143$5499 + attribute \src "libresoc.v:135750.3-135767.6" + process $proc$libresoc.v:135750$5540 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:134144.5-134144.29" + attribute \src "libresoc.v:135751.5-135751.29" switch \initial - attribute \src "libresoc.v:134144.9-134144.17" + attribute \src "libresoc.v:135751.9-135751.17" case 1'1 case end @@ -212370,52 +214790,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:133900$5425_Y - connect \$11 $not$libresoc.v:133901$5426_Y - connect \$13 $and$libresoc.v:133902$5427_Y - connect \$15 $or$libresoc.v:133903$5428_Y - connect \$17 $not$libresoc.v:133904$5429_Y - connect \$1 $not$libresoc.v:133905$5430_Y - connect \$19 $or$libresoc.v:133906$5431_Y - connect \$21 $not$libresoc.v:133907$5432_Y - connect \$23 $and$libresoc.v:133908$5433_Y - connect \$25 $or$libresoc.v:133909$5434_Y - connect \$27 $not$libresoc.v:133910$5435_Y - connect \$29 $or$libresoc.v:133911$5436_Y - connect \$31 $not$libresoc.v:133912$5437_Y - connect \$33 $and$libresoc.v:133913$5438_Y - connect \$35 $or$libresoc.v:133914$5439_Y - connect \$37 $not$libresoc.v:133915$5440_Y - connect \$3 $and$libresoc.v:133916$5441_Y - connect \$39 $or$libresoc.v:133917$5442_Y - connect \$41 $not$libresoc.v:133918$5443_Y - connect \$43 $and$libresoc.v:133919$5444_Y - connect \$45 $and$libresoc.v:133920$5445_Y - connect \$47 $not$libresoc.v:133921$5446_Y - connect \$49 $and$libresoc.v:133922$5447_Y - connect \$51 $not$libresoc.v:133923$5448_Y - connect \$5 $or$libresoc.v:133924$5449_Y - connect \$7 $not$libresoc.v:133925$5450_Y + connect \$9 $or$libresoc.v:135507$5466_Y + connect \$11 $not$libresoc.v:135508$5467_Y + connect \$13 $and$libresoc.v:135509$5468_Y + connect \$15 $or$libresoc.v:135510$5469_Y + connect \$17 $not$libresoc.v:135511$5470_Y + connect \$1 $not$libresoc.v:135512$5471_Y + connect \$19 $or$libresoc.v:135513$5472_Y + connect \$21 $not$libresoc.v:135514$5473_Y + connect \$23 $and$libresoc.v:135515$5474_Y + connect \$25 $or$libresoc.v:135516$5475_Y + connect \$27 $not$libresoc.v:135517$5476_Y + connect \$29 $or$libresoc.v:135518$5477_Y + connect \$31 $not$libresoc.v:135519$5478_Y + connect \$33 $and$libresoc.v:135520$5479_Y + connect \$35 $or$libresoc.v:135521$5480_Y + connect \$37 $not$libresoc.v:135522$5481_Y + connect \$3 $and$libresoc.v:135523$5482_Y + connect \$39 $or$libresoc.v:135524$5483_Y + connect \$41 $not$libresoc.v:135525$5484_Y + connect \$43 $and$libresoc.v:135526$5485_Y + connect \$45 $and$libresoc.v:135527$5486_Y + connect \$47 $not$libresoc.v:135528$5487_Y + connect \$49 $and$libresoc.v:135529$5488_Y + connect \$51 $not$libresoc.v:135530$5489_Y + connect \$5 $or$libresoc.v:135531$5490_Y + connect \$7 $not$libresoc.v:135532$5491_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:134167.1-134494.10" +attribute \src "libresoc.v:135774.1-136101.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:134457.3-134468.6" + attribute \src "libresoc.v:136064.3-136075.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:134168.7-134168.20" + attribute \src "libresoc.v:135775.7-135775.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134469.3-134487.6" - wire width 2 $0\xer_ca$23[1:0]$5511 - attribute \src "libresoc.v:134457.3-134468.6" + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $0\xer_ca$23[1:0]$5552 + attribute \src "libresoc.v:136064.3-136075.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:134469.3-134487.6" - wire width 2 $1\xer_ca$23[1:0]$5512 - attribute \src "libresoc.v:134456.18-134456.100" - wire width 64 $not$libresoc.v:134456$5508_Y + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136063.18-136063.100" + wire width 64 $not$libresoc.v:136063$5549_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -212682,7 +215102,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134168.7-134168.15" + attribute \src "libresoc.v:135775.7-135775.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -212705,28 +215125,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:134456$5508 + cell $not $not$libresoc.v:136063$5549 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:134456$5508_Y + connect \Y $not$libresoc.v:136063$5549_Y end - attribute \src "libresoc.v:134168.7-134168.20" - process $proc$libresoc.v:134168$5513 + attribute \src "libresoc.v:135775.7-135775.20" + process $proc$libresoc.v:135775$5554 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134457.3-134468.6" - process $proc$libresoc.v:134457$5509 + attribute \src "libresoc.v:136064.3-136075.6" + process $proc$libresoc.v:136064$5550 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:134458.5-134458.29" + attribute \src "libresoc.v:136065.5-136065.29" switch \initial - attribute \src "libresoc.v:134458.9-134458.17" + attribute \src "libresoc.v:136065.9-136065.17" case 1'1 case end @@ -212744,14 +215164,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:134469.3-134487.6" - process $proc$libresoc.v:134469$5510 + attribute \src "libresoc.v:136076.3-136094.6" + process $proc$libresoc.v:136076$5551 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5511 $1\xer_ca$23[1:0]$5512 - attribute \src "libresoc.v:134470.5-134470.29" + assign $0\xer_ca$23[1:0]$5552 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136077.5-136077.29" switch \initial - attribute \src "libresoc.v:134470.9-134470.17" + attribute \src "libresoc.v:136077.9-136077.17" case 1'1 case end @@ -212760,22 +215180,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5512 2'00 + assign $1\xer_ca$23[1:0]$5553 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5512 2'11 + assign $1\xer_ca$23[1:0]$5553 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5512 \xer_ca + assign $1\xer_ca$23[1:0]$5553 \xer_ca case - assign $1\xer_ca$23[1:0]$5512 2'00 + assign $1\xer_ca$23[1:0]$5553 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5511 + update \xer_ca$23 $0\xer_ca$23[1:0]$5552 end - connect \$24 $not$libresoc.v:134456$5508_Y + connect \$24 $not$libresoc.v:136063$5549_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -212783,30 +215203,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:134498.1-134826.10" +attribute \src "libresoc.v:136105.1-136433.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:134788.3-134799.6" + attribute \src "libresoc.v:136395.3-136406.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:134499.7-134499.20" + attribute \src "libresoc.v:136106.7-136106.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134800.3-134818.6" - wire width 2 $0\xer_ca$23[1:0]$5517 - attribute \src "libresoc.v:134788.3-134799.6" + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $0\xer_ca$23[1:0]$5558 + attribute \src "libresoc.v:136395.3-136406.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:134800.3-134818.6" - wire width 2 $1\xer_ca$23[1:0]$5518 - attribute \src "libresoc.v:134787.18-134787.100" - wire width 64 $not$libresoc.v:134787$5514_Y + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136394.18-136394.100" + wire width 64 $not$libresoc.v:136394$5555_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134499.7-134499.15" + attribute \src "libresoc.v:136106.7-136106.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -213089,28 +215509,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:134787$5514 + cell $not $not$libresoc.v:136394$5555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:134787$5514_Y + connect \Y $not$libresoc.v:136394$5555_Y end - attribute \src "libresoc.v:134499.7-134499.20" - process $proc$libresoc.v:134499$5519 + attribute \src "libresoc.v:136106.7-136106.20" + process $proc$libresoc.v:136106$5560 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134788.3-134799.6" - process $proc$libresoc.v:134788$5515 + attribute \src "libresoc.v:136395.3-136406.6" + process $proc$libresoc.v:136395$5556 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:134789.5-134789.29" + attribute \src "libresoc.v:136396.5-136396.29" switch \initial - attribute \src "libresoc.v:134789.9-134789.17" + attribute \src "libresoc.v:136396.9-136396.17" case 1'1 case end @@ -213128,14 +215548,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:134800.3-134818.6" - process $proc$libresoc.v:134800$5516 + attribute \src "libresoc.v:136407.3-136425.6" + process $proc$libresoc.v:136407$5557 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5517 $1\xer_ca$23[1:0]$5518 - attribute \src "libresoc.v:134801.5-134801.29" + assign $0\xer_ca$23[1:0]$5558 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136408.5-136408.29" switch \initial - attribute \src "libresoc.v:134801.9-134801.17" + attribute \src "libresoc.v:136408.9-136408.17" case 1'1 case end @@ -213144,22 +215564,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5518 2'00 + assign $1\xer_ca$23[1:0]$5559 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5518 2'11 + assign $1\xer_ca$23[1:0]$5559 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5518 \xer_ca + assign $1\xer_ca$23[1:0]$5559 \xer_ca case - assign $1\xer_ca$23[1:0]$5518 2'00 + assign $1\xer_ca$23[1:0]$5559 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5517 + update \xer_ca$23 $0\xer_ca$23[1:0]$5558 end - connect \$24 $not$libresoc.v:134787$5514_Y + connect \$24 $not$libresoc.v:136394$5555_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -213168,26 +215588,26 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:134830.1-135133.10" +attribute \src "libresoc.v:136437.1-136740.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:135115.3-135126.6" + attribute \src "libresoc.v:136722.3-136733.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:134831.7-134831.20" + attribute \src "libresoc.v:136438.7-136438.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135115.3-135126.6" + attribute \src "libresoc.v:136722.3-136733.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:135114.18-135114.100" - wire width 64 $not$libresoc.v:135114$5520_Y + attribute \src "libresoc.v:136721.18-136721.100" + wire width 64 $not$libresoc.v:136721$5561_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134831.7-134831.15" + attribute \src "libresoc.v:136438.7-136438.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -213466,28 +215886,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:135114$5520 + cell $not $not$libresoc.v:136721$5561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:135114$5520_Y + connect \Y $not$libresoc.v:136721$5561_Y end - attribute \src "libresoc.v:134831.7-134831.20" - process $proc$libresoc.v:134831$5522 + attribute \src "libresoc.v:136438.7-136438.20" + process $proc$libresoc.v:136438$5563 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135115.3-135126.6" - process $proc$libresoc.v:135115$5521 + attribute \src "libresoc.v:136722.3-136733.6" + process $proc$libresoc.v:136722$5562 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:135116.5-135116.29" + attribute \src "libresoc.v:136723.5-136723.29" switch \initial - attribute \src "libresoc.v:135116.9-135116.17" + attribute \src "libresoc.v:136723.9-136723.17" case 1'1 case end @@ -213505,7 +215925,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:135114$5520_Y + connect \$23 $not$libresoc.v:136721$5561_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -213513,26 +215933,26 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:135137.1-135440.10" +attribute \src "libresoc.v:136744.1-137047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:135422.3-135433.6" + attribute \src "libresoc.v:137029.3-137040.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:135138.7-135138.20" + attribute \src "libresoc.v:136745.7-136745.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135422.3-135433.6" + attribute \src "libresoc.v:137029.3-137040.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:135421.18-135421.100" - wire width 64 $not$libresoc.v:135421$5523_Y + attribute \src "libresoc.v:137028.18-137028.100" + wire width 64 $not$libresoc.v:137028$5564_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:135138.7-135138.15" + attribute \src "libresoc.v:136745.7-136745.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -213811,28 +216231,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:135421$5523 + cell $not $not$libresoc.v:137028$5564 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:135421$5523_Y + connect \Y $not$libresoc.v:137028$5564_Y end - attribute \src "libresoc.v:135138.7-135138.20" - process $proc$libresoc.v:135138$5525 + attribute \src "libresoc.v:136745.7-136745.20" + process $proc$libresoc.v:136745$5566 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135422.3-135433.6" - process $proc$libresoc.v:135422$5524 + attribute \src "libresoc.v:137029.3-137040.6" + process $proc$libresoc.v:137029$5565 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:135423.5-135423.29" + attribute \src "libresoc.v:137030.5-137030.29" switch \initial - attribute \src "libresoc.v:135423.9-135423.17" + attribute \src "libresoc.v:137030.9-137030.17" case 1'1 case end @@ -213850,7 +216270,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:135421$5523_Y + connect \$23 $not$libresoc.v:137028$5564_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -213858,7 +216278,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:135444.1-135700.10" +attribute \src "libresoc.v:137051.1-137307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -214119,100 +216539,118 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:135704.1-135923.10" +attribute \src "libresoc.v:137311.1-137571.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:135829.3-135835.6" - wire width 5 $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 - attribute \src "libresoc.v:135829.3-135835.6" - wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 - attribute \src "libresoc.v:135829.3-135835.6" - wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:135858.3-135867.6" + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_4_[4:0] + attribute \src "libresoc.v:137503.3-137512.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:135705.7-135705.20" + attribute \src "libresoc.v:137312.7-137312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135849.3-135857.6" - wire $0\ren_delay$10$next[0:0]$5578 - attribute \src "libresoc.v:135782.3-135783.43" - wire $0\ren_delay$10[0:0]$5560 - attribute \src "libresoc.v:135748.7-135748.28" - wire $0\ren_delay$10[0:0]$5626 - attribute \src "libresoc.v:135878.3-135886.6" - wire $0\ren_delay$8$next[0:0]$5583 - attribute \src "libresoc.v:135786.3-135787.41" - wire $0\ren_delay$8[0:0]$5564 - attribute \src "libresoc.v:135752.7-135752.27" - wire $0\ren_delay$8[0:0]$5628 - attribute \src "libresoc.v:135897.3-135905.6" - wire $0\ren_delay$9$next[0:0]$5587 - attribute \src "libresoc.v:135784.3-135785.41" - wire $0\ren_delay$9[0:0]$5562 - attribute \src "libresoc.v:135756.7-135756.27" - wire $0\ren_delay$9[0:0]$5630 - attribute \src "libresoc.v:135840.3-135848.6" - wire $0\ren_delay$next[0:0]$5575 - attribute \src "libresoc.v:135788.3-135789.35" + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $0\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $0\ren_delay$10$next[0:0]$5631 + attribute \src "libresoc.v:137409.3-137410.43" + wire $0\ren_delay$10[0:0]$5607 + attribute \src "libresoc.v:137365.7-137365.28" + wire $0\ren_delay$10[0:0]$5674 + attribute \src "libresoc.v:137542.3-137550.6" + wire $0\ren_delay$11$next[0:0]$5635 + attribute \src "libresoc.v:137407.3-137408.43" + wire $0\ren_delay$11[0:0]$5605 + attribute \src "libresoc.v:137369.7-137369.28" + wire $0\ren_delay$11[0:0]$5676 + attribute \src "libresoc.v:137475.3-137483.6" + wire $0\ren_delay$12$next[0:0]$5622 + attribute \src "libresoc.v:137405.3-137406.43" + wire $0\ren_delay$12[0:0]$5603 + attribute \src "libresoc.v:137373.7-137373.28" + wire $0\ren_delay$12[0:0]$5678 + attribute \src "libresoc.v:137494.3-137502.6" + wire $0\ren_delay$13$next[0:0]$5626 + attribute \src "libresoc.v:137403.3-137404.43" + wire $0\ren_delay$13[0:0]$5601 + attribute \src "libresoc.v:137377.7-137377.28" + wire $0\ren_delay$13[0:0]$5680 + attribute \src "libresoc.v:137466.3-137474.6" + wire $0\ren_delay$next[0:0]$5619 + attribute \src "libresoc.v:137411.3-137412.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:135868.3-135877.6" + attribute \src "libresoc.v:137513.3-137522.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:135887.3-135896.6" + attribute \src "libresoc.v:137532.3-137541.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:135906.3-135915.6" + attribute \src "libresoc.v:137551.3-137560.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:135858.3-135867.6" + attribute \src "libresoc.v:137503.3-137512.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:135849.3-135857.6" - wire $1\ren_delay$10$next[0:0]$5579 - attribute \src "libresoc.v:135878.3-135886.6" - wire $1\ren_delay$8$next[0:0]$5584 - attribute \src "libresoc.v:135897.3-135905.6" - wire $1\ren_delay$9$next[0:0]$5588 - attribute \src "libresoc.v:135840.3-135848.6" - wire $1\ren_delay$next[0:0]$5576 - attribute \src "libresoc.v:135746.7-135746.23" + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $1\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137542.3-137550.6" + wire $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137475.3-137483.6" + wire $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137494.3-137502.6" + wire $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137466.3-137474.6" + wire $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137363.7-137363.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:135868.3-135877.6" + attribute \src "libresoc.v:137513.3-137522.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:135887.3-135896.6" + attribute \src "libresoc.v:137532.3-137541.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:135906.3-135915.6" + attribute \src "libresoc.v:137551.3-137560.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:135836.26-135836.32" - wire width 64 $memrd$\memory$libresoc.v:135836$5570_DATA - attribute \src "libresoc.v:135837.30-135837.36" - wire width 64 $memrd$\memory$libresoc.v:135837$5571_DATA - attribute \src "libresoc.v:135838.30-135838.36" - wire width 64 $memrd$\memory$libresoc.v:135838$5572_DATA - attribute \src "libresoc.v:135839.30-135839.36" - wire width 64 $memrd$\memory$libresoc.v:135839$5573_DATA + attribute \src "libresoc.v:137461.26-137461.32" + wire width 64 $memrd$\memory$libresoc.v:137461$5613_DATA + attribute \src "libresoc.v:137462.30-137462.36" + wire width 64 $memrd$\memory$libresoc.v:137462$5614_DATA + attribute \src "libresoc.v:137463.30-137463.36" + wire width 64 $memrd$\memory$libresoc.v:137463$5615_DATA + attribute \src "libresoc.v:137464.30-137464.36" + wire width 64 $memrd$\memory$libresoc.v:137464$5616_DATA + attribute \src "libresoc.v:137465.30-137465.36" + wire width 64 $memrd$\memory$libresoc.v:137465$5617_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:135834$5558_ADDR + wire width 5 $memwr$\memory$libresoc.v:137459$5599_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:135834$5558_DATA + wire width 64 $memwr$\memory$libresoc.v:137459$5599_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:135834$5558_EN - attribute \src "libresoc.v:135825.13-135825.16" + wire width 64 $memwr$\memory$libresoc.v:137459$5599_EN + attribute \src "libresoc.v:137448.13-137448.16" wire width 5 \_0_ - attribute \src "libresoc.v:135826.13-135826.16" + attribute \src "libresoc.v:137449.13-137449.16" wire width 5 \_1_ - attribute \src "libresoc.v:135827.13-135827.16" + attribute \src "libresoc.v:137450.13-137450.16" wire width 5 \_2_ - attribute \src "libresoc.v:135828.13-135828.16" + attribute \src "libresoc.v:137451.13-137451.16" wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "libresoc.v:137452.13-137452.16" + wire width 5 \_4_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 15 \dest1__addr @@ -214226,7 +216664,7 @@ module \int wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:135705.7-135705.15" + attribute \src "libresoc.v:137312.7-137312.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -214237,6 +216675,8 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$3 @@ -214244,12 +216684,20 @@ module \int wire width 64 \memory_r_data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 5 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 \pred__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \pred__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \pred__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" @@ -214257,13 +216705,17 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8 + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8$next + wire \ren_delay$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9 + wire \ren_delay$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9$next + wire \ren_delay$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -214284,330 +216736,330 @@ module \int wire width 64 output 11 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src3__ren - attribute \src "libresoc.v:135790.14-135790.20" + attribute \src "libresoc.v:137413.14-137413.20" memory width 64 size 32 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5590 + cell $meminit $meminit$\memory$libresoc.v:0$5638 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5590 + parameter \PRIORITY 5638 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5591 + cell $meminit $meminit$\memory$libresoc.v:0$5639 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5591 + parameter \PRIORITY 5639 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5592 + cell $meminit $meminit$\memory$libresoc.v:0$5640 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5592 + parameter \PRIORITY 5640 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5593 + cell $meminit $meminit$\memory$libresoc.v:0$5641 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5593 + parameter \PRIORITY 5641 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5594 + cell $meminit $meminit$\memory$libresoc.v:0$5642 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5594 + parameter \PRIORITY 5642 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5595 + cell $meminit $meminit$\memory$libresoc.v:0$5643 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5595 + parameter \PRIORITY 5643 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5596 + cell $meminit $meminit$\memory$libresoc.v:0$5644 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5596 + parameter \PRIORITY 5644 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5597 + cell $meminit $meminit$\memory$libresoc.v:0$5645 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5597 + parameter \PRIORITY 5645 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5598 + cell $meminit $meminit$\memory$libresoc.v:0$5646 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5598 + parameter \PRIORITY 5646 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5599 + cell $meminit $meminit$\memory$libresoc.v:0$5647 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5599 + parameter \PRIORITY 5647 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5600 + cell $meminit $meminit$\memory$libresoc.v:0$5648 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5600 + parameter \PRIORITY 5648 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5601 + cell $meminit $meminit$\memory$libresoc.v:0$5649 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5601 + parameter \PRIORITY 5649 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5602 + cell $meminit $meminit$\memory$libresoc.v:0$5650 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5602 + parameter \PRIORITY 5650 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5603 + cell $meminit $meminit$\memory$libresoc.v:0$5651 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5603 + parameter \PRIORITY 5651 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5604 + cell $meminit $meminit$\memory$libresoc.v:0$5652 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5604 + parameter \PRIORITY 5652 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5605 + cell $meminit $meminit$\memory$libresoc.v:0$5653 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5605 + parameter \PRIORITY 5653 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5606 + cell $meminit $meminit$\memory$libresoc.v:0$5654 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5606 + parameter \PRIORITY 5654 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5607 + cell $meminit $meminit$\memory$libresoc.v:0$5655 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5607 + parameter \PRIORITY 5655 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5608 + cell $meminit $meminit$\memory$libresoc.v:0$5656 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5608 + parameter \PRIORITY 5656 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5609 + cell $meminit $meminit$\memory$libresoc.v:0$5657 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5609 + parameter \PRIORITY 5657 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5610 + cell $meminit $meminit$\memory$libresoc.v:0$5658 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5610 + parameter \PRIORITY 5658 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5611 + cell $meminit $meminit$\memory$libresoc.v:0$5659 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5611 + parameter \PRIORITY 5659 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5612 + cell $meminit $meminit$\memory$libresoc.v:0$5660 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5612 + parameter \PRIORITY 5660 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5613 + cell $meminit $meminit$\memory$libresoc.v:0$5661 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5613 + parameter \PRIORITY 5661 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5614 + cell $meminit $meminit$\memory$libresoc.v:0$5662 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5614 + parameter \PRIORITY 5662 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5615 + cell $meminit $meminit$\memory$libresoc.v:0$5663 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5615 + parameter \PRIORITY 5663 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5616 + cell $meminit $meminit$\memory$libresoc.v:0$5664 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5616 + parameter \PRIORITY 5664 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5617 + cell $meminit $meminit$\memory$libresoc.v:0$5665 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5617 + parameter \PRIORITY 5665 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5618 + cell $meminit $meminit$\memory$libresoc.v:0$5666 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5618 + parameter \PRIORITY 5666 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5619 + cell $meminit $meminit$\memory$libresoc.v:0$5667 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5619 + parameter \PRIORITY 5667 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5620 + cell $meminit $meminit$\memory$libresoc.v:0$5668 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5620 + parameter \PRIORITY 5668 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5621 + cell $meminit $meminit$\memory$libresoc.v:0$5669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5621 + parameter \PRIORITY 5669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:135836.26-135836.32" - cell $memrd $memrd$\memory$libresoc.v:135836$5570 + attribute \src "libresoc.v:137461.26-137461.32" + cell $memrd $memrd$\memory$libresoc.v:137461$5613 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214616,11 +217068,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135836$5570_DATA + connect \DATA $memrd$\memory$libresoc.v:137461$5613_DATA connect \EN 1'x end - attribute \src "libresoc.v:135837.30-135837.36" - cell $memrd $memrd$\memory$libresoc.v:135837$5571 + attribute \src "libresoc.v:137462.30-137462.36" + cell $memrd $memrd$\memory$libresoc.v:137462$5614 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214629,11 +217081,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135837$5571_DATA + connect \DATA $memrd$\memory$libresoc.v:137462$5614_DATA connect \EN 1'x end - attribute \src "libresoc.v:135838.30-135838.36" - cell $memrd $memrd$\memory$libresoc.v:135838$5572 + attribute \src "libresoc.v:137463.30-137463.36" + cell $memrd $memrd$\memory$libresoc.v:137463$5615 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214642,11 +217094,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135838$5572_DATA + connect \DATA $memrd$\memory$libresoc.v:137463$5615_DATA connect \EN 1'x end - attribute \src "libresoc.v:135839.30-135839.36" - cell $memrd $memrd$\memory$libresoc.v:135839$5573 + attribute \src "libresoc.v:137464.30-137464.36" + cell $memrd $memrd$\memory$libresoc.v:137464$5616 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214655,97 +217107,126 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135839$5573_DATA + connect \DATA $memrd$\memory$libresoc.v:137464$5616_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137465.30-137465.36" + cell $memrd $memrd$\memory$libresoc.v:137465$5617 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_4_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137465$5617_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5622 + cell $memwr $memwr$\memory$libresoc.v:0$5670 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5622 + parameter \PRIORITY 5670 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:135834$5558_ADDR + connect \ADDR $memwr$\memory$libresoc.v:137459$5599_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:135834$5558_DATA - connect \EN $memwr$\memory$libresoc.v:135834$5558_EN + connect \DATA $memwr$\memory$libresoc.v:137459$5599_DATA + connect \EN $memwr$\memory$libresoc.v:137459$5599_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5631 + process $proc$libresoc.v:0$5681 sync always sync init end - attribute \src "libresoc.v:135705.7-135705.20" - process $proc$libresoc.v:135705$5623 + attribute \src "libresoc.v:137312.7-137312.20" + process $proc$libresoc.v:137312$5671 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135746.7-135746.23" - process $proc$libresoc.v:135746$5624 + attribute \src "libresoc.v:137363.7-137363.23" + process $proc$libresoc.v:137363$5672 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:135748.7-135748.28" - process $proc$libresoc.v:135748$5625 + attribute \src "libresoc.v:137365.7-137365.28" + process $proc$libresoc.v:137365$5673 assign { } { } - assign $0\ren_delay$10[0:0]$5626 1'0 + assign $0\ren_delay$10[0:0]$5674 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5626 + update \ren_delay$10 $0\ren_delay$10[0:0]$5674 end - attribute \src "libresoc.v:135752.7-135752.27" - process $proc$libresoc.v:135752$5627 + attribute \src "libresoc.v:137369.7-137369.28" + process $proc$libresoc.v:137369$5675 assign { } { } - assign $0\ren_delay$8[0:0]$5628 1'0 + assign $0\ren_delay$11[0:0]$5676 1'0 sync always sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5628 + update \ren_delay$11 $0\ren_delay$11[0:0]$5676 end - attribute \src "libresoc.v:135756.7-135756.27" - process $proc$libresoc.v:135756$5629 + attribute \src "libresoc.v:137373.7-137373.28" + process $proc$libresoc.v:137373$5677 assign { } { } - assign $0\ren_delay$9[0:0]$5630 1'0 + assign $0\ren_delay$12[0:0]$5678 1'0 sync always sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5630 + update \ren_delay$12 $0\ren_delay$12[0:0]$5678 end - attribute \src "libresoc.v:135782.3-135783.43" - process $proc$libresoc.v:135782$5559 + attribute \src "libresoc.v:137377.7-137377.28" + process $proc$libresoc.v:137377$5679 assign { } { } - assign $0\ren_delay$10[0:0]$5560 \ren_delay$10$next + assign $0\ren_delay$13[0:0]$5680 1'0 + sync always + sync init + update \ren_delay$13 $0\ren_delay$13[0:0]$5680 + end + attribute \src "libresoc.v:137403.3-137404.43" + process $proc$libresoc.v:137403$5600 + assign { } { } + assign $0\ren_delay$13[0:0]$5601 \ren_delay$13$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5560 + update \ren_delay$13 $0\ren_delay$13[0:0]$5601 end - attribute \src "libresoc.v:135784.3-135785.41" - process $proc$libresoc.v:135784$5561 + attribute \src "libresoc.v:137405.3-137406.43" + process $proc$libresoc.v:137405$5602 assign { } { } - assign $0\ren_delay$9[0:0]$5562 \ren_delay$9$next + assign $0\ren_delay$12[0:0]$5603 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5562 + update \ren_delay$12 $0\ren_delay$12[0:0]$5603 end - attribute \src "libresoc.v:135786.3-135787.41" - process $proc$libresoc.v:135786$5563 + attribute \src "libresoc.v:137407.3-137408.43" + process $proc$libresoc.v:137407$5604 assign { } { } - assign $0\ren_delay$8[0:0]$5564 \ren_delay$8$next + assign $0\ren_delay$11[0:0]$5605 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5564 + update \ren_delay$11 $0\ren_delay$11[0:0]$5605 end - attribute \src "libresoc.v:135788.3-135789.35" - process $proc$libresoc.v:135788$5565 + attribute \src "libresoc.v:137409.3-137410.43" + process $proc$libresoc.v:137409$5606 + assign { } { } + assign $0\ren_delay$10[0:0]$5607 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5607 + end + attribute \src "libresoc.v:137411.3-137412.35" + process $proc$libresoc.v:137411$5608 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:135829.3-135835.6" - process $proc$libresoc.v:135829$5566 + attribute \src "libresoc.v:137453.3-137460.6" + process $proc$libresoc.v:137453$5609 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -214753,20 +217234,21 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 5'xxxxx - assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 5'xxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[4:0] \src1__addr assign $0\_1_[4:0] \src2__addr assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:135834.5-135834.58" + assign $0\_3_[4:0] 5'00000 + assign $0\_4_[4:0] \dmi__addr + attribute \src "libresoc.v:137459.5-137459.58" switch \dest1__wen - attribute \src "libresoc.v:135834.9-135834.19" + attribute \src "libresoc.v:137459.9-137459.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 \dest1__addr - assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 \dest1__addr + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk @@ -214774,18 +217256,19 @@ module \int update \_1_ $0\_1_[4:0] update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:135834$5558_ADDR $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 - update $memwr$\memory$libresoc.v:135834$5558_DATA $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 - update $memwr$\memory$libresoc.v:135834$5558_EN $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 + update \_4_ $0\_4_[4:0] + update $memwr$\memory$libresoc.v:137459$5599_ADDR $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + update $memwr$\memory$libresoc.v:137459$5599_DATA $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + update $memwr$\memory$libresoc.v:137459$5599_EN $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 end - attribute \src "libresoc.v:135840.3-135848.6" - process $proc$libresoc.v:135840$5574 + attribute \src "libresoc.v:137466.3-137474.6" + process $proc$libresoc.v:137466$5618 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5575 $1\ren_delay$next[0:0]$5576 - attribute \src "libresoc.v:135841.5-135841.29" + assign $0\ren_delay$next[0:0]$5619 $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137467.5-137467.29" switch \initial - attribute \src "libresoc.v:135841.9-135841.17" + attribute \src "libresoc.v:137467.9-137467.17" case 1'1 case end @@ -214794,21 +217277,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5576 1'0 + assign $1\ren_delay$next[0:0]$5620 1'0 case - assign $1\ren_delay$next[0:0]$5576 \src1__ren + assign $1\ren_delay$next[0:0]$5620 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5575 + update \ren_delay$next $0\ren_delay$next[0:0]$5619 end - attribute \src "libresoc.v:135849.3-135857.6" - process $proc$libresoc.v:135849$5577 + attribute \src "libresoc.v:137475.3-137483.6" + process $proc$libresoc.v:137475$5621 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5578 $1\ren_delay$10$next[0:0]$5579 - attribute \src "libresoc.v:135850.5-135850.29" + assign $0\ren_delay$12$next[0:0]$5622 $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137476.5-137476.29" switch \initial - attribute \src "libresoc.v:135850.9-135850.17" + attribute \src "libresoc.v:137476.9-137476.17" case 1'1 case end @@ -214817,44 +217300,90 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5579 1'0 + assign $1\ren_delay$12$next[0:0]$5623 1'0 case - assign $1\ren_delay$10$next[0:0]$5579 \dmi__ren + assign $1\ren_delay$12$next[0:0]$5623 \pred__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5578 + update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5622 end - attribute \src "libresoc.v:135858.3-135867.6" - process $proc$libresoc.v:135858$5580 + attribute \src "libresoc.v:137484.3-137493.6" + process $proc$libresoc.v:137484$5624 + assign { } { } + assign { } { } + assign $0\pred__data_o[63:0] $1\pred__data_o[63:0] + attribute \src "libresoc.v:137485.5-137485.29" + switch \initial + attribute \src "libresoc.v:137485.9-137485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pred__data_o[63:0] \memory_r_data$7 + case + assign $1\pred__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \pred__data_o $0\pred__data_o[63:0] + end + attribute \src "libresoc.v:137494.3-137502.6" + process $proc$libresoc.v:137494$5625 + assign { } { } + assign { } { } + assign $0\ren_delay$13$next[0:0]$5626 $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137495.5-137495.29" + switch \initial + attribute \src "libresoc.v:137495.9-137495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$13$next[0:0]$5627 1'0 + case + assign $1\ren_delay$13$next[0:0]$5627 \dmi__ren + end + sync always + update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5626 + end + attribute \src "libresoc.v:137503.3-137512.6" + process $proc$libresoc.v:137503$5628 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:135859.5-135859.29" + attribute \src "libresoc.v:137504.5-137504.29" switch \initial - attribute \src "libresoc.v:135859.9-135859.17" + attribute \src "libresoc.v:137504.9-137504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 + switch \ren_delay$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$7 + assign $1\dmi__data_o[63:0] \memory_r_data$9 case assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:135868.3-135877.6" - process $proc$libresoc.v:135868$5581 + attribute \src "libresoc.v:137513.3-137522.6" + process $proc$libresoc.v:137513$5629 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:135869.5-135869.29" + attribute \src "libresoc.v:137514.5-137514.29" switch \initial - attribute \src "libresoc.v:135869.9-135869.17" + attribute \src "libresoc.v:137514.9-137514.17" case 1'1 case end @@ -214870,14 +217399,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:135878.3-135886.6" - process $proc$libresoc.v:135878$5582 + attribute \src "libresoc.v:137523.3-137531.6" + process $proc$libresoc.v:137523$5630 assign { } { } assign { } { } - assign $0\ren_delay$8$next[0:0]$5583 $1\ren_delay$8$next[0:0]$5584 - attribute \src "libresoc.v:135879.5-135879.29" + assign $0\ren_delay$10$next[0:0]$5631 $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137524.5-137524.29" switch \initial - attribute \src "libresoc.v:135879.9-135879.17" + attribute \src "libresoc.v:137524.9-137524.17" case 1'1 case end @@ -214886,26 +217415,26 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$8$next[0:0]$5584 1'0 + assign $1\ren_delay$10$next[0:0]$5632 1'0 case - assign $1\ren_delay$8$next[0:0]$5584 \src2__ren + assign $1\ren_delay$10$next[0:0]$5632 \src2__ren end sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5583 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5631 end - attribute \src "libresoc.v:135887.3-135896.6" - process $proc$libresoc.v:135887$5585 + attribute \src "libresoc.v:137532.3-137541.6" + process $proc$libresoc.v:137532$5633 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:135888.5-135888.29" + attribute \src "libresoc.v:137533.5-137533.29" switch \initial - attribute \src "libresoc.v:135888.9-135888.17" + attribute \src "libresoc.v:137533.9-137533.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$8 + switch \ren_delay$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -214916,14 +217445,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:135897.3-135905.6" - process $proc$libresoc.v:135897$5586 + attribute \src "libresoc.v:137542.3-137550.6" + process $proc$libresoc.v:137542$5634 assign { } { } assign { } { } - assign $0\ren_delay$9$next[0:0]$5587 $1\ren_delay$9$next[0:0]$5588 - attribute \src "libresoc.v:135898.5-135898.29" + assign $0\ren_delay$11$next[0:0]$5635 $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137543.5-137543.29" switch \initial - attribute \src "libresoc.v:135898.9-135898.17" + attribute \src "libresoc.v:137543.9-137543.17" case 1'1 case end @@ -214932,26 +217461,26 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$9$next[0:0]$5588 1'0 + assign $1\ren_delay$11$next[0:0]$5636 1'0 case - assign $1\ren_delay$9$next[0:0]$5588 \src3__ren + assign $1\ren_delay$11$next[0:0]$5636 \src3__ren end sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5587 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5635 end - attribute \src "libresoc.v:135906.3-135915.6" - process $proc$libresoc.v:135906$5589 + attribute \src "libresoc.v:137551.3-137560.6" + process $proc$libresoc.v:137551$5637 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:135907.5-135907.29" + attribute \src "libresoc.v:137552.5-137552.29" switch \initial - attribute \src "libresoc.v:135907.9-135907.17" + attribute \src "libresoc.v:137552.9-137552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$9 + switch \ren_delay$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -214962,937 +217491,937 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:135836$5570_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:135837$5571_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:135838$5572_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:135839$5573_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:137461$5613_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:137462$5614_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:137463$5615_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:137464$5616_DATA + connect \memory_r_data$9 $memrd$\memory$libresoc.v:137465$5617_DATA + connect \pred__addr 5'00000 + connect \pred__ren 1'0 connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr - connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$8 \dmi__addr + connect \memory_r_addr$6 5'00000 connect \memory_r_addr$4 \src3__addr connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:135927.1-138650.10" +attribute \src "libresoc.v:137575.1-140282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:138080.3-138106.6" + attribute \src "libresoc.v:139714.3-139740.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:137728.3-137743.6" + attribute \src "libresoc.v:139362.3-139377.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$6043 - attribute \src "libresoc.v:137631.3-137632.41" + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6091 + attribute \src "libresoc.v:139265.3-139266.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $0\dmi0__din$next[63:0]$6056 - attribute \src "libresoc.v:137627.3-137628.35" + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $0\dmi0__din$next[63:0]$6104 + attribute \src "libresoc.v:139261.3-139262.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:137930.3-137946.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5980 - attribute \src "libresoc.v:137659.3-137660.47" + attribute \src "libresoc.v:139564.3-139580.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6028 + attribute \src "libresoc.v:139293.3-139294.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5984 - attribute \src "libresoc.v:137657.3-137658.47" + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 + attribute \src "libresoc.v:139291.3-139292.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:137912.3-137920.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5974 - attribute \src "libresoc.v:137663.3-137664.63" + attribute \src "libresoc.v:139546.3-139554.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:139297.3-139298.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:137921.3-137929.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 - attribute \src "libresoc.v:137661.3-137662.73" + attribute \src "libresoc.v:139555.3-139563.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:139295.3-139296.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6061 - attribute \src "libresoc.v:137625.3-137626.45" + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 + attribute \src "libresoc.v:139259.3-139260.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5995 - attribute \src "libresoc.v:137651.3-137652.47" + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 + attribute \src "libresoc.v:139285.3-139286.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5999 - attribute \src "libresoc.v:137649.3-137650.47" + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 + attribute \src "libresoc.v:139283.3-139284.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:137968.3-137976.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5989 - attribute \src "libresoc.v:137655.3-137656.63" + attribute \src "libresoc.v:139602.3-139610.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6037 + attribute \src "libresoc.v:139289.3-139290.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:137977.3-137985.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5992 - attribute \src "libresoc.v:137653.3-137654.73" + attribute \src "libresoc.v:139611.3-139619.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:139287.3-139288.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $0\fsm_state$503$next[2:0]$6049 - attribute \src "libresoc.v:137629.3-137630.45" - wire width 3 $0\fsm_state$503[2:0]$5895 - attribute \src "libresoc.v:136573.13-136573.35" - wire width 3 $0\fsm_state$503[2:0]$6098 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $0\fsm_state$next[2:0]$6026 - attribute \src "libresoc.v:137637.3-137638.35" + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $0\fsm_state$499$next[2:0]$6097 + attribute \src "libresoc.v:139263.3-139264.45" + wire width 3 $0\fsm_state$499[2:0]$5943 + attribute \src "libresoc.v:138217.13-138217.35" + wire width 3 $0\fsm_state$499[2:0]$6146 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $0\fsm_state$next[2:0]$6074 + attribute \src "libresoc.v:139271.3-139272.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:135928.7-135928.20" + attribute \src "libresoc.v:137576.7-137576.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $0\io_bd$next[153:0]$6081 - attribute \src "libresoc.v:137689.3-137690.27" - wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $0\io_sr$next[153:0]$6077 - attribute \src "libresoc.v:137691.3-137692.27" - wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$6020 - attribute \src "libresoc.v:137639.3-137640.41" + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $0\io_bd$next[151:0]$6129 + attribute \src "libresoc.v:139323.3-139324.27" + wire width 152 $0\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $0\io_sr$next[151:0]$6125 + attribute \src "libresoc.v:139325.3-139326.27" + wire width 152 $0\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6068 + attribute \src "libresoc.v:139273.3-139274.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$6033 - attribute \src "libresoc.v:137635.3-137636.45" + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 + attribute \src "libresoc.v:139269.3-139270.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:137818.3-137834.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5950 - attribute \src "libresoc.v:137675.3-137676.53" + attribute \src "libresoc.v:139452.3-139468.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 + attribute \src "libresoc.v:139309.3-139310.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5954 - attribute \src "libresoc.v:137673.3-137674.53" + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 + attribute \src "libresoc.v:139307.3-139308.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:137800.3-137808.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5944 - attribute \src "libresoc.v:137679.3-137680.69" + attribute \src "libresoc.v:139434.3-139442.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:139313.3-139314.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:137809.3-137817.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 - attribute \src "libresoc.v:137677.3-137678.79" + attribute \src "libresoc.v:139443.3-139451.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:139311.3-139312.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6038 - attribute \src "libresoc.v:137633.3-137634.51" + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 + attribute \src "libresoc.v:139267.3-139268.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5965 - attribute \src "libresoc.v:137667.3-137668.53" + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 + attribute \src "libresoc.v:139301.3-139302.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5969 - attribute \src "libresoc.v:137665.3-137666.53" + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 + attribute \src "libresoc.v:139299.3-139300.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:137856.3-137864.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5959 - attribute \src "libresoc.v:137671.3-137672.69" + attribute \src "libresoc.v:139490.3-139498.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:139305.3-139306.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:137865.3-137873.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 - attribute \src "libresoc.v:137669.3-137670.79" + attribute \src "libresoc.v:139499.3-139507.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:139303.3-139304.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:137762.3-137778.6" - wire $0\sr0__oe$next[0:0]$5935 - attribute \src "libresoc.v:137683.3-137684.31" + attribute \src "libresoc.v:139396.3-139412.6" + wire $0\sr0__oe$next[0:0]$5983 + attribute \src "libresoc.v:139317.3-139318.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $0\sr0_reg$next[2:0]$5939 - attribute \src "libresoc.v:137681.3-137682.31" + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $0\sr0_reg$next[2:0]$5987 + attribute \src "libresoc.v:139315.3-139316.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:137744.3-137752.6" - wire $0\sr0_update_core$next[0:0]$5929 - attribute \src "libresoc.v:137687.3-137688.47" + attribute \src "libresoc.v:139378.3-139386.6" + wire $0\sr0_update_core$next[0:0]$5977 + attribute \src "libresoc.v:139321.3-139322.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:137753.3-137761.6" - wire $0\sr0_update_core_prev$next[0:0]$5932 - attribute \src "libresoc.v:137685.3-137686.57" + attribute \src "libresoc.v:139387.3-139395.6" + wire $0\sr0_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:139319.3-139320.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:138396.3-138405.6" + attribute \src "libresoc.v:140030.3-140039.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:138042.3-138058.6" - wire $0\sr5__oe$next[0:0]$6010 - attribute \src "libresoc.v:137643.3-137644.31" + attribute \src "libresoc.v:139676.3-139692.6" + wire $0\sr5__oe$next[0:0]$6058 + attribute \src "libresoc.v:139277.3-139278.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $0\sr5_reg$next[2:0]$6014 - attribute \src "libresoc.v:137641.3-137642.31" + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $0\sr5_reg$next[2:0]$6062 + attribute \src "libresoc.v:139275.3-139276.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:138024.3-138032.6" - wire $0\sr5_update_core$next[0:0]$6004 - attribute \src "libresoc.v:137647.3-137648.47" + attribute \src "libresoc.v:139658.3-139666.6" + wire $0\sr5_update_core$next[0:0]$6052 + attribute \src "libresoc.v:139281.3-139282.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:138033.3-138041.6" - wire $0\sr5_update_core_prev$next[0:0]$6007 - attribute \src "libresoc.v:137645.3-137646.57" + attribute \src "libresoc.v:139667.3-139675.6" + wire $0\sr5_update_core_prev$next[0:0]$6055 + attribute \src "libresoc.v:139279.3-139280.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_dcache_en$next[0:0]$6066 - attribute \src "libresoc.v:137621.3-137622.41" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_dcache_en$next[0:0]$6114 + attribute \src "libresoc.v:139255.3-139256.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_icache_en$next[0:0]$6067 - attribute \src "libresoc.v:137619.3-137620.41" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_icache_en$next[0:0]$6115 + attribute \src "libresoc.v:139253.3-139254.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_sram_en$next[0:0]$6068 - attribute \src "libresoc.v:137623.3-137624.37" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_sram_en$next[0:0]$6116 + attribute \src "libresoc.v:139257.3-139258.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:138080.3-138106.6" + attribute \src "libresoc.v:139714.3-139740.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:137728.3-137743.6" + attribute \src "libresoc.v:139362.3-139377.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$6044 - attribute \src "libresoc.v:136486.13-136486.32" + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6092 + attribute \src "libresoc.v:138130.13-138130.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $1\dmi0__din$next[63:0]$6057 - attribute \src "libresoc.v:136491.14-136491.46" + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $1\dmi0__din$next[63:0]$6105 + attribute \src "libresoc.v:138135.14-138135.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:137930.3-137946.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5981 - attribute \src "libresoc.v:136505.7-136505.29" + attribute \src "libresoc.v:139564.3-139580.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6029 + attribute \src "libresoc.v:138149.7-138149.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5985 - attribute \src "libresoc.v:136513.13-136513.36" + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 + attribute \src "libresoc.v:138157.13-138157.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:137912.3-137920.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5975 - attribute \src "libresoc.v:136521.7-136521.37" + attribute \src "libresoc.v:139546.3-139554.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:138165.7-138165.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:137921.3-137929.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 - attribute \src "libresoc.v:136525.7-136525.42" + attribute \src "libresoc.v:139555.3-139563.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:138169.7-138169.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6062 - attribute \src "libresoc.v:136529.14-136529.51" + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 + attribute \src "libresoc.v:138173.14-138173.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5996 - attribute \src "libresoc.v:136535.13-136535.35" + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 + attribute \src "libresoc.v:138179.13-138179.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$6000 - attribute \src "libresoc.v:136543.14-136543.52" + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 + attribute \src "libresoc.v:138187.14-138187.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:137968.3-137976.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5990 - attribute \src "libresoc.v:136551.7-136551.37" + attribute \src "libresoc.v:139602.3-139610.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:138195.7-138195.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:137977.3-137985.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5993 - attribute \src "libresoc.v:136555.7-136555.42" + attribute \src "libresoc.v:139611.3-139619.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:138199.7-138199.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $1\fsm_state$503$next[2:0]$6050 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $1\fsm_state$next[2:0]$6027 - attribute \src "libresoc.v:136571.13-136571.29" + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $1\fsm_state$499$next[2:0]$6098 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $1\fsm_state$next[2:0]$6075 + attribute \src "libresoc.v:138215.13-138215.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $1\io_bd$next[153:0]$6082 - attribute \src "libresoc.v:136771.15-136771.67" - wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $1\io_sr$next[153:0]$6078 - attribute \src "libresoc.v:136783.15-136783.67" - wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$6021 - attribute \src "libresoc.v:136792.14-136792.41" + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $1\io_bd$next[151:0]$6130 + attribute \src "libresoc.v:138415.15-138415.66" + wire width 152 $1\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $1\io_sr$next[151:0]$6126 + attribute \src "libresoc.v:138427.15-138427.66" + wire width 152 $1\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6069 + attribute \src "libresoc.v:138436.14-138436.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$6034 - attribute \src "libresoc.v:136801.14-136801.51" + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 + attribute \src "libresoc.v:138445.14-138445.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:137818.3-137834.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5951 - attribute \src "libresoc.v:136815.7-136815.32" + attribute \src "libresoc.v:139452.3-139468.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 + attribute \src "libresoc.v:138459.7-138459.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5955 - attribute \src "libresoc.v:136823.14-136823.47" + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + attribute \src "libresoc.v:138467.14-138467.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:137800.3-137808.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:136831.7-136831.40" + attribute \src "libresoc.v:139434.3-139442.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:138475.7-138475.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:137809.3-137817.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:136835.7-136835.45" + attribute \src "libresoc.v:139443.3-139451.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:138479.7-138479.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6039 - attribute \src "libresoc.v:136839.14-136839.54" + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 + attribute \src "libresoc.v:138483.14-138483.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5966 - attribute \src "libresoc.v:136845.13-136845.38" + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 + attribute \src "libresoc.v:138489.13-138489.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5970 - attribute \src "libresoc.v:136853.14-136853.55" + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 + attribute \src "libresoc.v:138497.14-138497.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:137856.3-137864.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5960 - attribute \src "libresoc.v:136861.7-136861.40" + attribute \src "libresoc.v:139490.3-139498.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:138505.7-138505.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:137865.3-137873.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:136865.7-136865.45" + attribute \src "libresoc.v:139499.3-139507.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:138509.7-138509.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:137762.3-137778.6" - wire $1\sr0__oe$next[0:0]$5936 - attribute \src "libresoc.v:137295.7-137295.21" + attribute \src "libresoc.v:139396.3-139412.6" + wire $1\sr0__oe$next[0:0]$5984 + attribute \src "libresoc.v:138931.7-138931.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $1\sr0_reg$next[2:0]$5940 - attribute \src "libresoc.v:137303.13-137303.27" + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $1\sr0_reg$next[2:0]$5988 + attribute \src "libresoc.v:138939.13-138939.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:137744.3-137752.6" - wire $1\sr0_update_core$next[0:0]$5930 - attribute \src "libresoc.v:137311.7-137311.29" + attribute \src "libresoc.v:139378.3-139386.6" + wire $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:138947.7-138947.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:137753.3-137761.6" - wire $1\sr0_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:137315.7-137315.34" + attribute \src "libresoc.v:139387.3-139395.6" + wire $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:138951.7-138951.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:138396.3-138405.6" + attribute \src "libresoc.v:140030.3-140039.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:138042.3-138058.6" - wire $1\sr5__oe$next[0:0]$6011 - attribute \src "libresoc.v:137325.7-137325.21" + attribute \src "libresoc.v:139676.3-139692.6" + wire $1\sr5__oe$next[0:0]$6059 + attribute \src "libresoc.v:138961.7-138961.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $1\sr5_reg$next[2:0]$6015 - attribute \src "libresoc.v:137333.13-137333.27" + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $1\sr5_reg$next[2:0]$6063 + attribute \src "libresoc.v:138969.13-138969.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:138024.3-138032.6" - wire $1\sr5_update_core$next[0:0]$6005 - attribute \src "libresoc.v:137341.7-137341.29" + attribute \src "libresoc.v:139658.3-139666.6" + wire $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:138977.7-138977.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:138033.3-138041.6" - wire $1\sr5_update_core_prev$next[0:0]$6008 - attribute \src "libresoc.v:137345.7-137345.34" + attribute \src "libresoc.v:139667.3-139675.6" + wire $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:138981.7-138981.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_dcache_en$next[0:0]$6069 - attribute \src "libresoc.v:137350.7-137350.26" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_dcache_en$next[0:0]$6117 + attribute \src "libresoc.v:138986.7-138986.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_icache_en$next[0:0]$6070 - attribute \src "libresoc.v:137355.7-137355.26" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_icache_en$next[0:0]$6118 + attribute \src "libresoc.v:138991.7-138991.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_sram_en$next[0:0]$6071 - attribute \src "libresoc.v:137360.7-137360.24" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_sram_en$next[0:0]$6119 + attribute \src "libresoc.v:138996.7-138996.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6045 - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $2\dmi0__din$next[63:0]$6058 - attribute \src "libresoc.v:137930.3-137946.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5982 - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5986 - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6063 - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5997 - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$6001 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $2\fsm_state$503$next[2:0]$6051 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $2\fsm_state$next[2:0]$6028 - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $2\io_bd$next[153:0]$6083 - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $2\io_sr$next[153:0]$6079 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$6022 - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$6035 - attribute \src "libresoc.v:137818.3-137834.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5952 - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5956 - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6040 - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5967 - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5971 - attribute \src "libresoc.v:137762.3-137778.6" - wire $2\sr0__oe$next[0:0]$5937 - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $2\sr0_reg$next[2:0]$5941 - attribute \src "libresoc.v:138042.3-138058.6" - wire $2\sr5__oe$next[0:0]$6012 - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $2\sr5_reg$next[2:0]$6016 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_dcache_en$next[0:0]$6072 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_icache_en$next[0:0]$6073 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_sram_en$next[0:0]$6074 - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6046 - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $3\dmi0__din$next[63:0]$6059 - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5987 - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6064 - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$6002 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $3\fsm_state$503$next[2:0]$6052 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $3\fsm_state$next[2:0]$6029 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$6023 - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$6036 - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5957 - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6041 - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5972 - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $3\sr0_reg$next[2:0]$5942 - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $3\sr5_reg$next[2:0]$6017 - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6047 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $4\fsm_state$503$next[2:0]$6053 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $4\fsm_state$next[2:0]$6030 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$6024 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $5\fsm_state$503$next[2:0]$6054 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $5\fsm_state$next[2:0]$6031 - attribute \src "libresoc.v:137583.19-137583.112" - wire width 30 $add$libresoc.v:137583$5852_Y - attribute \src "libresoc.v:137585.19-137585.112" - wire width 30 $add$libresoc.v:137585$5854_Y - attribute \src "libresoc.v:137591.19-137591.112" - wire width 5 $add$libresoc.v:137591$5861_Y - attribute \src "libresoc.v:137592.19-137592.112" - wire width 5 $add$libresoc.v:137592$5862_Y - attribute \src "libresoc.v:137407.18-137407.112" - wire $and$libresoc.v:137407$5676_Y - attribute \src "libresoc.v:137474.18-137474.108" - wire $and$libresoc.v:137474$5743_Y - attribute \src "libresoc.v:137485.18-137485.110" - wire $and$libresoc.v:137485$5754_Y - attribute \src "libresoc.v:137513.19-137513.110" - wire $and$libresoc.v:137513$5782_Y - attribute \src "libresoc.v:137516.19-137516.114" - wire $and$libresoc.v:137516$5785_Y - attribute \src "libresoc.v:137519.19-137519.112" - wire $and$libresoc.v:137519$5788_Y - attribute \src "libresoc.v:137521.19-137521.113" - wire $and$libresoc.v:137521$5790_Y - attribute \src "libresoc.v:137523.19-137523.121" - wire $and$libresoc.v:137523$5792_Y - attribute \src "libresoc.v:137526.19-137526.114" - wire $and$libresoc.v:137526$5795_Y - attribute \src "libresoc.v:137528.19-137528.112" - wire $and$libresoc.v:137528$5797_Y - attribute \src "libresoc.v:137532.19-137532.113" - wire $and$libresoc.v:137532$5801_Y - attribute \src "libresoc.v:137534.19-137534.132" - wire $and$libresoc.v:137534$5803_Y - attribute \src "libresoc.v:137538.19-137538.114" - wire $and$libresoc.v:137538$5807_Y - attribute \src "libresoc.v:137540.19-137540.112" - wire $and$libresoc.v:137540$5809_Y - attribute \src "libresoc.v:137543.19-137543.113" - wire $and$libresoc.v:137543$5812_Y - attribute \src "libresoc.v:137545.19-137545.132" - wire $and$libresoc.v:137545$5814_Y - attribute \src "libresoc.v:137548.19-137548.114" - wire $and$libresoc.v:137548$5817_Y - attribute \src "libresoc.v:137550.19-137550.112" - wire $and$libresoc.v:137550$5819_Y - attribute \src "libresoc.v:137552.18-137552.108" - wire $and$libresoc.v:137552$5821_Y - attribute \src "libresoc.v:137553.19-137553.113" - wire $and$libresoc.v:137553$5822_Y - attribute \src "libresoc.v:137555.19-137555.129" - wire $and$libresoc.v:137555$5824_Y - attribute \src "libresoc.v:137559.19-137559.114" - wire $and$libresoc.v:137559$5828_Y - attribute \src "libresoc.v:137561.19-137561.112" - wire $and$libresoc.v:137561$5830_Y - attribute \src "libresoc.v:137563.18-137563.111" - wire $and$libresoc.v:137563$5832_Y - attribute \src "libresoc.v:137564.19-137564.113" - wire $and$libresoc.v:137564$5833_Y - attribute \src "libresoc.v:137566.19-137566.129" - wire $and$libresoc.v:137566$5835_Y - attribute \src "libresoc.v:137569.19-137569.114" - wire $and$libresoc.v:137569$5838_Y - attribute \src "libresoc.v:137571.19-137571.112" - wire $and$libresoc.v:137571$5840_Y - attribute \src "libresoc.v:137573.19-137573.113" - wire $and$libresoc.v:137573$5842_Y - attribute \src "libresoc.v:137576.19-137576.121" - wire $and$libresoc.v:137576$5845_Y - attribute \src "libresoc.v:137608.17-137608.106" - wire $and$libresoc.v:137608$5878_Y - attribute \src "libresoc.v:137363.17-137363.110" - wire $eq$libresoc.v:137363$5632_Y - attribute \src "libresoc.v:137374.18-137374.111" - wire $eq$libresoc.v:137374$5643_Y - attribute \src "libresoc.v:137385.18-137385.111" - wire $eq$libresoc.v:137385$5654_Y - attribute \src "libresoc.v:137418.17-137418.110" - wire $eq$libresoc.v:137418$5687_Y - attribute \src "libresoc.v:137419.18-137419.111" - wire $eq$libresoc.v:137419$5688_Y - attribute \src "libresoc.v:137430.18-137430.111" - wire $eq$libresoc.v:137430$5699_Y - attribute \src "libresoc.v:137452.18-137452.111" - wire $eq$libresoc.v:137452$5721_Y - attribute \src "libresoc.v:137496.18-137496.111" - wire $eq$libresoc.v:137496$5765_Y - attribute \src "libresoc.v:137507.18-137507.111" - wire $eq$libresoc.v:137507$5776_Y - attribute \src "libresoc.v:137508.19-137508.112" - wire $eq$libresoc.v:137508$5777_Y - attribute \src "libresoc.v:137509.19-137509.112" - wire $eq$libresoc.v:137509$5778_Y - attribute \src "libresoc.v:137511.19-137511.112" - wire $eq$libresoc.v:137511$5780_Y - attribute \src "libresoc.v:137514.19-137514.112" - wire $eq$libresoc.v:137514$5783_Y - attribute \src "libresoc.v:137524.19-137524.112" - wire $eq$libresoc.v:137524$5793_Y - attribute \src "libresoc.v:137529.17-137529.110" - wire $eq$libresoc.v:137529$5798_Y - attribute \src "libresoc.v:137530.18-137530.111" - wire $eq$libresoc.v:137530$5799_Y - attribute \src "libresoc.v:137535.19-137535.112" - wire $eq$libresoc.v:137535$5804_Y - attribute \src "libresoc.v:137536.19-137536.112" - wire $eq$libresoc.v:137536$5805_Y - attribute \src "libresoc.v:137546.19-137546.112" - wire $eq$libresoc.v:137546$5815_Y - attribute \src "libresoc.v:137556.19-137556.112" - wire $eq$libresoc.v:137556$5825_Y - attribute \src "libresoc.v:137557.19-137557.112" - wire $eq$libresoc.v:137557$5826_Y - attribute \src "libresoc.v:137567.19-137567.112" - wire $eq$libresoc.v:137567$5836_Y - attribute \src "libresoc.v:137574.18-137574.111" - wire $eq$libresoc.v:137574$5843_Y - attribute \src "libresoc.v:137577.19-137577.110" - wire $eq$libresoc.v:137577$5846_Y - attribute \src "libresoc.v:137579.19-137579.110" - wire $eq$libresoc.v:137579$5848_Y - attribute \src "libresoc.v:137580.19-137580.110" - wire $eq$libresoc.v:137580$5849_Y - attribute \src "libresoc.v:137582.19-137582.110" - wire $eq$libresoc.v:137582$5851_Y - attribute \src "libresoc.v:137584.18-137584.111" - wire $eq$libresoc.v:137584$5853_Y - attribute \src "libresoc.v:137587.19-137587.116" - wire $eq$libresoc.v:137587$5857_Y - attribute \src "libresoc.v:137588.19-137588.116" - wire $eq$libresoc.v:137588$5858_Y - attribute \src "libresoc.v:137590.19-137590.116" - wire $eq$libresoc.v:137590$5860_Y - attribute \src "libresoc.v:137586.19-137586.106" - wire width 8 $extend$libresoc.v:137586$5855_Y - attribute \src "libresoc.v:137515.19-137515.109" - wire $ne$libresoc.v:137515$5784_Y - attribute \src "libresoc.v:137517.19-137517.109" - wire $ne$libresoc.v:137517$5786_Y - attribute \src "libresoc.v:137520.19-137520.109" - wire $ne$libresoc.v:137520$5789_Y - attribute \src "libresoc.v:137525.19-137525.120" - wire $ne$libresoc.v:137525$5794_Y - attribute \src "libresoc.v:137527.19-137527.120" - wire $ne$libresoc.v:137527$5796_Y - attribute \src "libresoc.v:137531.19-137531.120" - wire $ne$libresoc.v:137531$5800_Y - attribute \src "libresoc.v:137537.19-137537.120" - wire $ne$libresoc.v:137537$5806_Y - attribute \src "libresoc.v:137539.19-137539.120" - wire $ne$libresoc.v:137539$5808_Y - attribute \src "libresoc.v:137542.19-137542.120" - wire $ne$libresoc.v:137542$5811_Y - attribute \src "libresoc.v:137547.19-137547.117" - wire $ne$libresoc.v:137547$5816_Y - attribute \src "libresoc.v:137549.19-137549.117" - wire $ne$libresoc.v:137549$5818_Y - attribute \src "libresoc.v:137551.19-137551.117" - wire $ne$libresoc.v:137551$5820_Y - attribute \src "libresoc.v:137558.19-137558.117" - wire $ne$libresoc.v:137558$5827_Y - attribute \src "libresoc.v:137560.19-137560.117" - wire $ne$libresoc.v:137560$5829_Y - attribute \src "libresoc.v:137562.19-137562.117" - wire $ne$libresoc.v:137562$5831_Y - attribute \src "libresoc.v:137568.19-137568.109" - wire $ne$libresoc.v:137568$5837_Y - attribute \src "libresoc.v:137570.19-137570.109" - wire $ne$libresoc.v:137570$5839_Y - attribute \src "libresoc.v:137572.19-137572.109" - wire $ne$libresoc.v:137572$5841_Y - attribute \src "libresoc.v:137522.19-137522.110" - wire $not$libresoc.v:137522$5791_Y - attribute \src "libresoc.v:137533.19-137533.121" - wire $not$libresoc.v:137533$5802_Y - attribute \src "libresoc.v:137544.19-137544.121" - wire $not$libresoc.v:137544$5813_Y - attribute \src "libresoc.v:137554.19-137554.118" - wire $not$libresoc.v:137554$5823_Y - attribute \src "libresoc.v:137565.19-137565.118" - wire $not$libresoc.v:137565$5834_Y - attribute \src "libresoc.v:137575.19-137575.110" - wire $not$libresoc.v:137575$5844_Y - attribute \src "libresoc.v:137578.19-137578.100" - wire $not$libresoc.v:137578$5847_Y - attribute \src "libresoc.v:137396.18-137396.104" - wire $or$libresoc.v:137396$5665_Y - attribute \src "libresoc.v:137441.18-137441.104" - wire $or$libresoc.v:137441$5710_Y - attribute \src "libresoc.v:137463.18-137463.104" - wire $or$libresoc.v:137463$5732_Y - attribute \src "libresoc.v:137510.19-137510.107" - wire $or$libresoc.v:137510$5779_Y - attribute \src "libresoc.v:137512.19-137512.107" - wire $or$libresoc.v:137512$5781_Y - attribute \src "libresoc.v:137518.18-137518.104" - wire $or$libresoc.v:137518$5787_Y - attribute \src "libresoc.v:137541.18-137541.104" - wire $or$libresoc.v:137541$5810_Y - attribute \src "libresoc.v:137581.19-137581.107" - wire $or$libresoc.v:137581$5850_Y - attribute \src "libresoc.v:137589.19-137589.107" - wire $or$libresoc.v:137589$5859_Y - attribute \src "libresoc.v:137597.17-137597.101" - wire $or$libresoc.v:137597$5867_Y - attribute \src "libresoc.v:137586.19-137586.106" - wire width 8 $pos$libresoc.v:137586$5856_Y - attribute \src "libresoc.v:137364.18-137364.133" - wire $ternary$libresoc.v:137364$5633_Y - attribute \src "libresoc.v:137365.19-137365.133" - wire $ternary$libresoc.v:137365$5634_Y - attribute \src "libresoc.v:137366.19-137366.134" - wire $ternary$libresoc.v:137366$5635_Y - attribute \src "libresoc.v:137367.19-137367.133" - wire $ternary$libresoc.v:137367$5636_Y - attribute \src "libresoc.v:137368.19-137368.132" - wire $ternary$libresoc.v:137368$5637_Y - attribute \src "libresoc.v:137369.19-137369.133" - wire $ternary$libresoc.v:137369$5638_Y - attribute \src "libresoc.v:137370.19-137370.133" - wire $ternary$libresoc.v:137370$5639_Y - attribute \src "libresoc.v:137371.19-137371.132" - wire $ternary$libresoc.v:137371$5640_Y - attribute \src "libresoc.v:137372.19-137372.133" - wire $ternary$libresoc.v:137372$5641_Y - attribute \src "libresoc.v:137373.19-137373.133" - wire $ternary$libresoc.v:137373$5642_Y - attribute \src "libresoc.v:137375.19-137375.132" - wire $ternary$libresoc.v:137375$5644_Y - attribute \src "libresoc.v:137376.19-137376.133" - wire $ternary$libresoc.v:137376$5645_Y - attribute \src "libresoc.v:137377.19-137377.133" - wire $ternary$libresoc.v:137377$5646_Y - attribute \src "libresoc.v:137378.19-137378.132" - wire $ternary$libresoc.v:137378$5647_Y - attribute \src "libresoc.v:137379.19-137379.133" - wire $ternary$libresoc.v:137379$5648_Y - attribute \src "libresoc.v:137380.19-137380.133" - wire $ternary$libresoc.v:137380$5649_Y - attribute \src "libresoc.v:137381.19-137381.132" - wire $ternary$libresoc.v:137381$5650_Y - attribute \src "libresoc.v:137382.19-137382.133" - wire $ternary$libresoc.v:137382$5651_Y - attribute \src "libresoc.v:137383.19-137383.133" - wire $ternary$libresoc.v:137383$5652_Y - attribute \src "libresoc.v:137384.19-137384.132" - wire $ternary$libresoc.v:137384$5653_Y - attribute \src "libresoc.v:137386.19-137386.133" - wire $ternary$libresoc.v:137386$5655_Y - attribute \src "libresoc.v:137387.19-137387.133" - wire $ternary$libresoc.v:137387$5656_Y - attribute \src "libresoc.v:137388.19-137388.132" - wire $ternary$libresoc.v:137388$5657_Y - attribute \src "libresoc.v:137389.19-137389.133" - wire $ternary$libresoc.v:137389$5658_Y - attribute \src "libresoc.v:137390.19-137390.133" - wire $ternary$libresoc.v:137390$5659_Y - attribute \src "libresoc.v:137391.19-137391.132" - wire $ternary$libresoc.v:137391$5660_Y - attribute \src "libresoc.v:137392.19-137392.133" - wire $ternary$libresoc.v:137392$5661_Y - attribute \src "libresoc.v:137393.19-137393.134" - wire $ternary$libresoc.v:137393$5662_Y - attribute \src "libresoc.v:137394.19-137394.135" - wire $ternary$libresoc.v:137394$5663_Y - attribute \src "libresoc.v:137395.19-137395.135" - wire $ternary$libresoc.v:137395$5664_Y - attribute \src "libresoc.v:137397.19-137397.136" - wire $ternary$libresoc.v:137397$5666_Y - attribute \src "libresoc.v:137398.19-137398.134" - wire $ternary$libresoc.v:137398$5667_Y - attribute \src "libresoc.v:137399.19-137399.135" - wire $ternary$libresoc.v:137399$5668_Y - attribute \src "libresoc.v:137400.19-137400.135" - wire $ternary$libresoc.v:137400$5669_Y - attribute \src "libresoc.v:137401.19-137401.136" - wire $ternary$libresoc.v:137401$5670_Y - attribute \src "libresoc.v:137402.19-137402.134" - wire $ternary$libresoc.v:137402$5671_Y - attribute \src "libresoc.v:137403.19-137403.133" - wire $ternary$libresoc.v:137403$5672_Y - attribute \src "libresoc.v:137404.19-137404.134" - wire $ternary$libresoc.v:137404$5673_Y - attribute \src "libresoc.v:137405.19-137405.133" - wire $ternary$libresoc.v:137405$5674_Y - attribute \src "libresoc.v:137406.19-137406.130" - wire $ternary$libresoc.v:137406$5675_Y - attribute \src "libresoc.v:137408.19-137408.130" - wire $ternary$libresoc.v:137408$5677_Y - attribute \src "libresoc.v:137409.19-137409.133" - wire $ternary$libresoc.v:137409$5678_Y - attribute \src "libresoc.v:137410.19-137410.132" - wire $ternary$libresoc.v:137410$5679_Y - attribute \src "libresoc.v:137411.19-137411.133" - wire $ternary$libresoc.v:137411$5680_Y - attribute \src "libresoc.v:137412.19-137412.132" - wire $ternary$libresoc.v:137412$5681_Y - attribute \src "libresoc.v:137413.19-137413.135" - wire $ternary$libresoc.v:137413$5682_Y - attribute \src "libresoc.v:137414.19-137414.134" - wire $ternary$libresoc.v:137414$5683_Y - attribute \src "libresoc.v:137415.19-137415.135" - wire $ternary$libresoc.v:137415$5684_Y - attribute \src "libresoc.v:137416.19-137416.135" - wire $ternary$libresoc.v:137416$5685_Y - attribute \src "libresoc.v:137417.19-137417.134" - wire $ternary$libresoc.v:137417$5686_Y - attribute \src "libresoc.v:137420.19-137420.135" - wire $ternary$libresoc.v:137420$5689_Y - attribute \src "libresoc.v:137421.19-137421.135" - wire $ternary$libresoc.v:137421$5690_Y - attribute \src "libresoc.v:137422.19-137422.134" - wire $ternary$libresoc.v:137422$5691_Y - attribute \src "libresoc.v:137423.19-137423.135" - wire $ternary$libresoc.v:137423$5692_Y - attribute \src "libresoc.v:137424.19-137424.135" - wire $ternary$libresoc.v:137424$5693_Y - attribute \src "libresoc.v:137425.19-137425.134" - wire $ternary$libresoc.v:137425$5694_Y - attribute \src "libresoc.v:137426.19-137426.135" - wire $ternary$libresoc.v:137426$5695_Y - attribute \src "libresoc.v:137427.19-137427.133" - wire $ternary$libresoc.v:137427$5696_Y - attribute \src "libresoc.v:137428.19-137428.134" - wire $ternary$libresoc.v:137428$5697_Y - attribute \src "libresoc.v:137429.19-137429.133" - wire $ternary$libresoc.v:137429$5698_Y - attribute \src "libresoc.v:137431.19-137431.134" - wire $ternary$libresoc.v:137431$5700_Y - attribute \src "libresoc.v:137432.19-137432.134" - wire $ternary$libresoc.v:137432$5701_Y - attribute \src "libresoc.v:137433.19-137433.133" - wire $ternary$libresoc.v:137433$5702_Y - attribute \src "libresoc.v:137434.19-137434.134" - wire $ternary$libresoc.v:137434$5703_Y - attribute \src "libresoc.v:137435.19-137435.134" - wire $ternary$libresoc.v:137435$5704_Y - attribute \src "libresoc.v:137436.19-137436.133" - wire $ternary$libresoc.v:137436$5705_Y - attribute \src "libresoc.v:137437.19-137437.134" - wire $ternary$libresoc.v:137437$5706_Y - attribute \src "libresoc.v:137438.19-137438.134" - wire $ternary$libresoc.v:137438$5707_Y - attribute \src "libresoc.v:137439.19-137439.133" - wire $ternary$libresoc.v:137439$5708_Y - attribute \src "libresoc.v:137440.19-137440.134" - wire $ternary$libresoc.v:137440$5709_Y - attribute \src "libresoc.v:137442.19-137442.134" - wire $ternary$libresoc.v:137442$5711_Y - attribute \src "libresoc.v:137443.19-137443.133" - wire $ternary$libresoc.v:137443$5712_Y - attribute \src "libresoc.v:137444.19-137444.134" - wire $ternary$libresoc.v:137444$5713_Y - attribute \src "libresoc.v:137445.19-137445.134" - wire $ternary$libresoc.v:137445$5714_Y - attribute \src "libresoc.v:137446.19-137446.133" - wire $ternary$libresoc.v:137446$5715_Y - attribute \src "libresoc.v:137447.19-137447.134" - wire $ternary$libresoc.v:137447$5716_Y - attribute \src "libresoc.v:137448.19-137448.135" - wire $ternary$libresoc.v:137448$5717_Y - attribute \src "libresoc.v:137449.19-137449.134" - wire $ternary$libresoc.v:137449$5718_Y - attribute \src "libresoc.v:137450.19-137450.135" - wire $ternary$libresoc.v:137450$5719_Y - attribute \src "libresoc.v:137451.19-137451.135" - wire $ternary$libresoc.v:137451$5720_Y - attribute \src "libresoc.v:137453.19-137453.134" - wire $ternary$libresoc.v:137453$5722_Y - attribute \src "libresoc.v:137454.19-137454.135" - wire $ternary$libresoc.v:137454$5723_Y - attribute \src "libresoc.v:137455.19-137455.133" - wire $ternary$libresoc.v:137455$5724_Y - attribute \src "libresoc.v:137456.19-137456.133" - wire $ternary$libresoc.v:137456$5725_Y - attribute \src "libresoc.v:137457.19-137457.133" - wire $ternary$libresoc.v:137457$5726_Y - attribute \src "libresoc.v:137458.19-137458.133" - wire $ternary$libresoc.v:137458$5727_Y - attribute \src "libresoc.v:137459.19-137459.133" - wire $ternary$libresoc.v:137459$5728_Y - attribute \src "libresoc.v:137460.19-137460.133" - wire $ternary$libresoc.v:137460$5729_Y - attribute \src "libresoc.v:137461.19-137461.133" - wire $ternary$libresoc.v:137461$5730_Y - attribute \src "libresoc.v:137462.19-137462.133" - wire $ternary$libresoc.v:137462$5731_Y - attribute \src "libresoc.v:137464.19-137464.133" - wire $ternary$libresoc.v:137464$5733_Y - attribute \src "libresoc.v:137465.19-137465.133" - wire $ternary$libresoc.v:137465$5734_Y - attribute \src "libresoc.v:137466.19-137466.134" - wire $ternary$libresoc.v:137466$5735_Y - attribute \src "libresoc.v:137467.19-137467.134" - wire $ternary$libresoc.v:137467$5736_Y - attribute \src "libresoc.v:137468.19-137468.135" - wire $ternary$libresoc.v:137468$5737_Y - attribute \src "libresoc.v:137469.19-137469.133" - wire $ternary$libresoc.v:137469$5738_Y - attribute \src "libresoc.v:137470.19-137470.135" - wire $ternary$libresoc.v:137470$5739_Y - attribute \src "libresoc.v:137471.19-137471.135" - wire $ternary$libresoc.v:137471$5740_Y - attribute \src "libresoc.v:137472.19-137472.134" - wire $ternary$libresoc.v:137472$5741_Y - attribute \src "libresoc.v:137473.19-137473.134" - wire $ternary$libresoc.v:137473$5742_Y - attribute \src "libresoc.v:137475.19-137475.134" - wire $ternary$libresoc.v:137475$5744_Y - attribute \src "libresoc.v:137476.19-137476.134" - wire $ternary$libresoc.v:137476$5745_Y - attribute \src "libresoc.v:137477.19-137477.134" - wire $ternary$libresoc.v:137477$5746_Y - attribute \src "libresoc.v:137478.19-137478.135" - wire $ternary$libresoc.v:137478$5747_Y - attribute \src "libresoc.v:137479.19-137479.134" - wire $ternary$libresoc.v:137479$5748_Y - attribute \src "libresoc.v:137480.19-137480.135" - wire $ternary$libresoc.v:137480$5749_Y - attribute \src "libresoc.v:137481.19-137481.135" - wire $ternary$libresoc.v:137481$5750_Y - attribute \src "libresoc.v:137482.19-137482.134" - wire $ternary$libresoc.v:137482$5751_Y - attribute \src "libresoc.v:137483.19-137483.135" - wire $ternary$libresoc.v:137483$5752_Y - attribute \src "libresoc.v:137484.19-137484.135" - wire $ternary$libresoc.v:137484$5753_Y - attribute \src "libresoc.v:137486.19-137486.134" - wire $ternary$libresoc.v:137486$5755_Y - attribute \src "libresoc.v:137487.19-137487.135" - wire $ternary$libresoc.v:137487$5756_Y - attribute \src "libresoc.v:137488.19-137488.136" - wire $ternary$libresoc.v:137488$5757_Y - attribute \src "libresoc.v:137489.19-137489.135" - wire $ternary$libresoc.v:137489$5758_Y - attribute \src "libresoc.v:137490.19-137490.136" - wire $ternary$libresoc.v:137490$5759_Y - attribute \src "libresoc.v:137491.19-137491.136" - wire $ternary$libresoc.v:137491$5760_Y - attribute \src "libresoc.v:137492.19-137492.135" - wire $ternary$libresoc.v:137492$5761_Y - attribute \src "libresoc.v:137493.19-137493.136" - wire $ternary$libresoc.v:137493$5762_Y - attribute \src "libresoc.v:137494.19-137494.136" - wire $ternary$libresoc.v:137494$5763_Y - attribute \src "libresoc.v:137495.19-137495.135" - wire $ternary$libresoc.v:137495$5764_Y - attribute \src "libresoc.v:137497.19-137497.136" - wire $ternary$libresoc.v:137497$5766_Y - attribute \src "libresoc.v:137498.19-137498.136" - wire $ternary$libresoc.v:137498$5767_Y - attribute \src "libresoc.v:137499.19-137499.135" - wire $ternary$libresoc.v:137499$5768_Y - attribute \src "libresoc.v:137500.19-137500.136" - wire $ternary$libresoc.v:137500$5769_Y - attribute \src "libresoc.v:137501.19-137501.136" - wire $ternary$libresoc.v:137501$5770_Y - attribute \src "libresoc.v:137502.19-137502.135" - wire $ternary$libresoc.v:137502$5771_Y - attribute \src "libresoc.v:137503.19-137503.136" - wire $ternary$libresoc.v:137503$5772_Y - attribute \src "libresoc.v:137504.19-137504.136" - wire $ternary$libresoc.v:137504$5773_Y - attribute \src "libresoc.v:137505.19-137505.135" - wire $ternary$libresoc.v:137505$5774_Y - attribute \src "libresoc.v:137506.19-137506.136" - wire $ternary$libresoc.v:137506$5775_Y - attribute \src "libresoc.v:137593.18-137593.130" - wire $ternary$libresoc.v:137593$5863_Y - attribute \src "libresoc.v:137594.18-137594.130" - wire $ternary$libresoc.v:137594$5864_Y - attribute \src "libresoc.v:137595.18-137595.130" - wire $ternary$libresoc.v:137595$5865_Y - attribute \src "libresoc.v:137596.18-137596.131" - wire $ternary$libresoc.v:137596$5866_Y - attribute \src "libresoc.v:137598.18-137598.130" - wire $ternary$libresoc.v:137598$5868_Y - attribute \src "libresoc.v:137599.18-137599.131" - wire $ternary$libresoc.v:137599$5869_Y - attribute \src "libresoc.v:137600.18-137600.131" - wire $ternary$libresoc.v:137600$5870_Y - attribute \src "libresoc.v:137601.18-137601.130" - wire $ternary$libresoc.v:137601$5871_Y - attribute \src "libresoc.v:137602.18-137602.131" - wire $ternary$libresoc.v:137602$5872_Y - attribute \src "libresoc.v:137603.18-137603.132" - wire $ternary$libresoc.v:137603$5873_Y - attribute \src "libresoc.v:137604.18-137604.132" - wire $ternary$libresoc.v:137604$5874_Y - attribute \src "libresoc.v:137605.18-137605.133" - wire $ternary$libresoc.v:137605$5875_Y - attribute \src "libresoc.v:137606.18-137606.133" - wire $ternary$libresoc.v:137606$5876_Y - attribute \src "libresoc.v:137607.18-137607.132" - wire $ternary$libresoc.v:137607$5877_Y - attribute \src "libresoc.v:137609.18-137609.133" - wire $ternary$libresoc.v:137609$5879_Y - attribute \src "libresoc.v:137610.18-137610.133" - wire $ternary$libresoc.v:137610$5880_Y - attribute \src "libresoc.v:137611.18-137611.132" - wire $ternary$libresoc.v:137611$5881_Y - attribute \src "libresoc.v:137612.18-137612.133" - wire $ternary$libresoc.v:137612$5882_Y - attribute \src "libresoc.v:137613.18-137613.133" - wire $ternary$libresoc.v:137613$5883_Y - attribute \src "libresoc.v:137614.18-137614.132" - wire $ternary$libresoc.v:137614$5884_Y - attribute \src "libresoc.v:137615.18-137615.133" - wire $ternary$libresoc.v:137615$5885_Y - attribute \src "libresoc.v:137616.18-137616.133" - wire $ternary$libresoc.v:137616$5886_Y - attribute \src "libresoc.v:137617.18-137617.132" - wire $ternary$libresoc.v:137617$5887_Y - attribute \src "libresoc.v:137618.18-137618.133" - wire $ternary$libresoc.v:137618$5888_Y + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $2\dmi0__din$next[63:0]$6106 + attribute \src "libresoc.v:139564.3-139580.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $2\fsm_state$499$next[2:0]$6099 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $2\fsm_state$next[2:0]$6076 + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "libresoc.v:139452.3-139468.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 + attribute \src "libresoc.v:139396.3-139412.6" + wire $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $2\sr0_reg$next[2:0]$5989 + attribute \src "libresoc.v:139676.3-139692.6" + wire $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $2\sr5_reg$next[2:0]$6064 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_dcache_en$next[0:0]$6120 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_icache_en$next[0:0]$6121 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $3\fsm_state$499$next[2:0]$6100 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $3\fsm_state$next[2:0]$6077 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $4\fsm_state$499$next[2:0]$6101 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $4\fsm_state$next[2:0]$6078 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139217.19-139217.112" + wire width 30 $add$libresoc.v:139217$5900_Y + attribute \src "libresoc.v:139218.19-139218.112" + wire width 30 $add$libresoc.v:139218$5901_Y + attribute \src "libresoc.v:139225.19-139225.112" + wire width 5 $add$libresoc.v:139225$5909_Y + attribute \src "libresoc.v:139226.19-139226.112" + wire width 5 $add$libresoc.v:139226$5910_Y + attribute \src "libresoc.v:139043.18-139043.112" + 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$and$libresoc.v:139168$5851_Y + attribute \src "libresoc.v:139172.19-139172.114" + wire $and$libresoc.v:139172$5855_Y + attribute \src "libresoc.v:139174.19-139174.112" + wire $and$libresoc.v:139174$5857_Y + attribute \src "libresoc.v:139176.19-139176.113" + wire $and$libresoc.v:139176$5859_Y + attribute \src "libresoc.v:139179.19-139179.132" + wire $and$libresoc.v:139179$5862_Y + attribute \src "libresoc.v:139182.19-139182.114" + wire $and$libresoc.v:139182$5865_Y + attribute \src "libresoc.v:139184.19-139184.112" + wire $and$libresoc.v:139184$5867_Y + attribute \src "libresoc.v:139186.19-139186.113" + wire $and$libresoc.v:139186$5869_Y + attribute \src "libresoc.v:139188.18-139188.108" + wire $and$libresoc.v:139188$5871_Y + attribute \src "libresoc.v:139189.19-139189.129" + wire $and$libresoc.v:139189$5872_Y + attribute \src "libresoc.v:139193.19-139193.114" + wire $and$libresoc.v:139193$5876_Y + attribute \src "libresoc.v:139195.19-139195.112" + wire $and$libresoc.v:139195$5878_Y + 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$eq$libresoc.v:139165$5848_Y + attribute \src "libresoc.v:139166.18-139166.111" + wire $eq$libresoc.v:139166$5849_Y + attribute \src "libresoc.v:139169.19-139169.112" + wire $eq$libresoc.v:139169$5852_Y + attribute \src "libresoc.v:139170.19-139170.112" + wire $eq$libresoc.v:139170$5853_Y + attribute \src "libresoc.v:139180.19-139180.112" + wire $eq$libresoc.v:139180$5863_Y + attribute \src "libresoc.v:139190.19-139190.112" + wire $eq$libresoc.v:139190$5873_Y + attribute \src "libresoc.v:139191.19-139191.112" + wire $eq$libresoc.v:139191$5874_Y + attribute \src "libresoc.v:139201.19-139201.112" + wire $eq$libresoc.v:139201$5884_Y + attribute \src "libresoc.v:139210.18-139210.111" + wire $eq$libresoc.v:139210$5893_Y + attribute \src "libresoc.v:139211.19-139211.110" + wire $eq$libresoc.v:139211$5894_Y + attribute \src "libresoc.v:139213.19-139213.110" + wire $eq$libresoc.v:139213$5896_Y + attribute \src "libresoc.v:139214.19-139214.110" + wire $eq$libresoc.v:139214$5897_Y + attribute \src "libresoc.v:139216.19-139216.110" + wire $eq$libresoc.v:139216$5899_Y + attribute \src "libresoc.v:139220.18-139220.111" + wire $eq$libresoc.v:139220$5904_Y + attribute \src "libresoc.v:139221.19-139221.116" + wire $eq$libresoc.v:139221$5905_Y + attribute \src "libresoc.v:139222.19-139222.116" + wire $eq$libresoc.v:139222$5906_Y + attribute \src "libresoc.v:139224.19-139224.116" + wire $eq$libresoc.v:139224$5908_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $extend$libresoc.v:139219$5902_Y + attribute \src "libresoc.v:139149.19-139149.109" + wire $ne$libresoc.v:139149$5832_Y + attribute \src "libresoc.v:139151.19-139151.109" + wire $ne$libresoc.v:139151$5834_Y + attribute \src "libresoc.v:139153.19-139153.109" + wire $ne$libresoc.v:139153$5836_Y + attribute \src "libresoc.v:139159.19-139159.120" + wire $ne$libresoc.v:139159$5842_Y + attribute \src "libresoc.v:139161.19-139161.120" + wire $ne$libresoc.v:139161$5844_Y + attribute \src "libresoc.v:139163.19-139163.120" + wire $ne$libresoc.v:139163$5846_Y + attribute \src "libresoc.v:139171.19-139171.120" + wire $ne$libresoc.v:139171$5854_Y + attribute \src "libresoc.v:139173.19-139173.120" + wire $ne$libresoc.v:139173$5856_Y + attribute \src "libresoc.v:139175.19-139175.120" + wire $ne$libresoc.v:139175$5858_Y + attribute \src "libresoc.v:139181.19-139181.117" + wire $ne$libresoc.v:139181$5864_Y + attribute \src "libresoc.v:139183.19-139183.117" + wire $ne$libresoc.v:139183$5866_Y + attribute \src "libresoc.v:139185.19-139185.117" + wire $ne$libresoc.v:139185$5868_Y + attribute \src "libresoc.v:139192.19-139192.117" + wire $ne$libresoc.v:139192$5875_Y + attribute \src "libresoc.v:139194.19-139194.117" + wire $ne$libresoc.v:139194$5877_Y + attribute \src "libresoc.v:139196.19-139196.117" + wire $ne$libresoc.v:139196$5879_Y + attribute \src "libresoc.v:139202.19-139202.109" + wire $ne$libresoc.v:139202$5885_Y + attribute \src "libresoc.v:139204.19-139204.109" + wire $ne$libresoc.v:139204$5887_Y + attribute \src "libresoc.v:139206.19-139206.109" + wire $ne$libresoc.v:139206$5889_Y + attribute \src "libresoc.v:139156.19-139156.110" + wire $not$libresoc.v:139156$5839_Y + attribute \src "libresoc.v:139167.19-139167.121" + wire $not$libresoc.v:139167$5850_Y + attribute \src "libresoc.v:139178.19-139178.121" + wire $not$libresoc.v:139178$5861_Y + attribute \src "libresoc.v:139187.19-139187.118" + wire $not$libresoc.v:139187$5870_Y + attribute \src "libresoc.v:139198.19-139198.118" + wire $not$libresoc.v:139198$5881_Y + attribute \src "libresoc.v:139208.19-139208.110" + wire $not$libresoc.v:139208$5891_Y + attribute \src "libresoc.v:139212.19-139212.100" + wire $not$libresoc.v:139212$5895_Y + attribute \src "libresoc.v:139032.18-139032.104" + wire $or$libresoc.v:139032$5715_Y + attribute \src "libresoc.v:139077.18-139077.104" + wire $or$libresoc.v:139077$5760_Y + attribute \src "libresoc.v:139099.18-139099.104" + wire $or$libresoc.v:139099$5782_Y + attribute \src "libresoc.v:139144.19-139144.107" + wire $or$libresoc.v:139144$5827_Y + attribute \src "libresoc.v:139146.19-139146.107" + wire $or$libresoc.v:139146$5829_Y + attribute \src "libresoc.v:139154.18-139154.104" + wire $or$libresoc.v:139154$5837_Y + attribute \src "libresoc.v:139177.18-139177.104" + wire $or$libresoc.v:139177$5860_Y + attribute \src "libresoc.v:139215.19-139215.107" + wire $or$libresoc.v:139215$5898_Y + attribute \src "libresoc.v:139223.19-139223.107" + wire $or$libresoc.v:139223$5907_Y + attribute \src "libresoc.v:139231.17-139231.101" + wire $or$libresoc.v:139231$5915_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $pos$libresoc.v:139219$5903_Y + attribute \src "libresoc.v:139000.18-139000.133" + wire $ternary$libresoc.v:139000$5683_Y + attribute \src "libresoc.v:139001.19-139001.133" + wire $ternary$libresoc.v:139001$5684_Y + attribute \src "libresoc.v:139002.19-139002.134" + wire $ternary$libresoc.v:139002$5685_Y + attribute \src "libresoc.v:139003.19-139003.133" + wire $ternary$libresoc.v:139003$5686_Y + attribute \src "libresoc.v:139004.19-139004.132" + wire $ternary$libresoc.v:139004$5687_Y + attribute \src "libresoc.v:139005.19-139005.133" + wire $ternary$libresoc.v:139005$5688_Y + attribute \src "libresoc.v:139006.19-139006.133" + wire $ternary$libresoc.v:139006$5689_Y + attribute \src "libresoc.v:139007.19-139007.132" + wire $ternary$libresoc.v:139007$5690_Y + attribute \src "libresoc.v:139008.19-139008.133" + wire $ternary$libresoc.v:139008$5691_Y + attribute \src "libresoc.v:139009.19-139009.133" + wire $ternary$libresoc.v:139009$5692_Y + attribute \src "libresoc.v:139011.19-139011.132" + wire $ternary$libresoc.v:139011$5694_Y + attribute \src "libresoc.v:139012.19-139012.133" + wire $ternary$libresoc.v:139012$5695_Y + attribute \src "libresoc.v:139013.19-139013.133" + wire $ternary$libresoc.v:139013$5696_Y + attribute \src "libresoc.v:139014.19-139014.132" + wire $ternary$libresoc.v:139014$5697_Y + attribute \src "libresoc.v:139015.19-139015.133" + wire $ternary$libresoc.v:139015$5698_Y + attribute \src "libresoc.v:139016.19-139016.133" + wire $ternary$libresoc.v:139016$5699_Y + attribute \src "libresoc.v:139017.19-139017.132" + wire $ternary$libresoc.v:139017$5700_Y + attribute \src "libresoc.v:139018.19-139018.133" + wire $ternary$libresoc.v:139018$5701_Y + attribute \src "libresoc.v:139019.19-139019.133" + wire $ternary$libresoc.v:139019$5702_Y + attribute \src "libresoc.v:139020.19-139020.132" + wire $ternary$libresoc.v:139020$5703_Y + attribute \src "libresoc.v:139022.19-139022.133" + wire $ternary$libresoc.v:139022$5705_Y + attribute \src "libresoc.v:139023.19-139023.133" + wire $ternary$libresoc.v:139023$5706_Y + attribute \src "libresoc.v:139024.19-139024.132" + wire $ternary$libresoc.v:139024$5707_Y + attribute \src "libresoc.v:139025.19-139025.133" + wire $ternary$libresoc.v:139025$5708_Y + attribute \src "libresoc.v:139026.19-139026.133" + wire $ternary$libresoc.v:139026$5709_Y + attribute \src "libresoc.v:139027.19-139027.132" + wire $ternary$libresoc.v:139027$5710_Y + attribute \src "libresoc.v:139028.19-139028.133" + wire $ternary$libresoc.v:139028$5711_Y + attribute \src "libresoc.v:139029.19-139029.134" + wire $ternary$libresoc.v:139029$5712_Y + attribute \src "libresoc.v:139030.19-139030.135" + wire $ternary$libresoc.v:139030$5713_Y + attribute \src "libresoc.v:139031.19-139031.135" + wire $ternary$libresoc.v:139031$5714_Y + attribute \src "libresoc.v:139033.19-139033.136" + wire $ternary$libresoc.v:139033$5716_Y + attribute \src "libresoc.v:139034.19-139034.134" + wire $ternary$libresoc.v:139034$5717_Y + attribute \src "libresoc.v:139035.19-139035.135" + wire $ternary$libresoc.v:139035$5718_Y + attribute \src "libresoc.v:139036.19-139036.135" + wire $ternary$libresoc.v:139036$5719_Y + attribute \src "libresoc.v:139037.19-139037.136" + wire $ternary$libresoc.v:139037$5720_Y + attribute \src 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attribute \src "libresoc.v:139050.19-139050.134" + wire $ternary$libresoc.v:139050$5733_Y + attribute \src "libresoc.v:139051.19-139051.135" + wire $ternary$libresoc.v:139051$5734_Y + attribute \src "libresoc.v:139052.19-139052.135" + wire $ternary$libresoc.v:139052$5735_Y + attribute \src "libresoc.v:139053.19-139053.134" + wire $ternary$libresoc.v:139053$5736_Y + attribute \src "libresoc.v:139056.19-139056.135" + wire $ternary$libresoc.v:139056$5739_Y + attribute \src "libresoc.v:139057.19-139057.135" + wire $ternary$libresoc.v:139057$5740_Y + attribute \src "libresoc.v:139058.19-139058.134" + wire $ternary$libresoc.v:139058$5741_Y + attribute \src "libresoc.v:139059.19-139059.135" + wire $ternary$libresoc.v:139059$5742_Y + attribute \src "libresoc.v:139060.19-139060.135" + wire $ternary$libresoc.v:139060$5743_Y + attribute \src "libresoc.v:139061.19-139061.134" + wire $ternary$libresoc.v:139061$5744_Y + attribute \src "libresoc.v:139062.19-139062.135" + wire $ternary$libresoc.v:139062$5745_Y + attribute \src "libresoc.v:139063.19-139063.133" + wire $ternary$libresoc.v:139063$5746_Y + attribute \src "libresoc.v:139064.19-139064.134" + wire $ternary$libresoc.v:139064$5747_Y + attribute \src "libresoc.v:139065.19-139065.133" + wire $ternary$libresoc.v:139065$5748_Y + attribute \src "libresoc.v:139067.19-139067.134" + wire $ternary$libresoc.v:139067$5750_Y + attribute \src "libresoc.v:139068.19-139068.134" + wire $ternary$libresoc.v:139068$5751_Y + attribute \src "libresoc.v:139069.19-139069.133" + wire $ternary$libresoc.v:139069$5752_Y + attribute \src "libresoc.v:139070.19-139070.134" + wire $ternary$libresoc.v:139070$5753_Y + attribute \src "libresoc.v:139071.19-139071.134" + wire $ternary$libresoc.v:139071$5754_Y + attribute \src "libresoc.v:139072.19-139072.133" + wire $ternary$libresoc.v:139072$5755_Y + attribute \src "libresoc.v:139073.19-139073.134" + wire $ternary$libresoc.v:139073$5756_Y + attribute \src "libresoc.v:139074.19-139074.134" + wire $ternary$libresoc.v:139074$5757_Y + attribute \src "libresoc.v:139075.19-139075.133" + wire $ternary$libresoc.v:139075$5758_Y + attribute \src "libresoc.v:139076.19-139076.134" + wire $ternary$libresoc.v:139076$5759_Y + attribute \src "libresoc.v:139078.19-139078.134" + wire $ternary$libresoc.v:139078$5761_Y + attribute \src "libresoc.v:139079.19-139079.133" + wire $ternary$libresoc.v:139079$5762_Y + attribute \src "libresoc.v:139080.19-139080.134" + wire $ternary$libresoc.v:139080$5763_Y + attribute \src "libresoc.v:139081.19-139081.134" + wire $ternary$libresoc.v:139081$5764_Y + attribute \src "libresoc.v:139082.19-139082.133" + wire $ternary$libresoc.v:139082$5765_Y + attribute \src "libresoc.v:139083.19-139083.134" + wire $ternary$libresoc.v:139083$5766_Y + attribute \src "libresoc.v:139084.19-139084.135" + wire $ternary$libresoc.v:139084$5767_Y + attribute \src "libresoc.v:139085.19-139085.134" + wire $ternary$libresoc.v:139085$5768_Y + attribute \src "libresoc.v:139086.19-139086.135" + wire $ternary$libresoc.v:139086$5769_Y + attribute \src "libresoc.v:139087.19-139087.135" + wire $ternary$libresoc.v:139087$5770_Y + attribute \src "libresoc.v:139089.19-139089.134" + wire $ternary$libresoc.v:139089$5772_Y + attribute \src "libresoc.v:139090.19-139090.135" + wire $ternary$libresoc.v:139090$5773_Y + attribute \src "libresoc.v:139091.19-139091.133" + wire $ternary$libresoc.v:139091$5774_Y + attribute \src "libresoc.v:139092.19-139092.133" + wire $ternary$libresoc.v:139092$5775_Y + attribute \src "libresoc.v:139093.19-139093.133" + wire $ternary$libresoc.v:139093$5776_Y + attribute \src "libresoc.v:139094.19-139094.133" + wire $ternary$libresoc.v:139094$5777_Y + attribute \src "libresoc.v:139095.19-139095.133" + wire $ternary$libresoc.v:139095$5778_Y + attribute \src "libresoc.v:139096.19-139096.133" + wire $ternary$libresoc.v:139096$5779_Y + attribute \src "libresoc.v:139097.19-139097.133" + wire $ternary$libresoc.v:139097$5780_Y + attribute \src "libresoc.v:139098.19-139098.133" + wire $ternary$libresoc.v:139098$5781_Y + attribute \src "libresoc.v:139100.19-139100.133" + wire $ternary$libresoc.v:139100$5783_Y + attribute \src "libresoc.v:139101.19-139101.133" + wire $ternary$libresoc.v:139101$5784_Y + attribute \src "libresoc.v:139102.19-139102.134" + wire $ternary$libresoc.v:139102$5785_Y + attribute \src "libresoc.v:139103.19-139103.134" + wire $ternary$libresoc.v:139103$5786_Y + attribute \src "libresoc.v:139104.19-139104.135" + wire $ternary$libresoc.v:139104$5787_Y + attribute \src "libresoc.v:139105.19-139105.133" + wire $ternary$libresoc.v:139105$5788_Y + attribute \src "libresoc.v:139106.19-139106.135" + wire $ternary$libresoc.v:139106$5789_Y + attribute \src "libresoc.v:139107.19-139107.135" + wire $ternary$libresoc.v:139107$5790_Y + attribute \src "libresoc.v:139108.19-139108.134" + wire $ternary$libresoc.v:139108$5791_Y + attribute \src "libresoc.v:139109.19-139109.134" + wire $ternary$libresoc.v:139109$5792_Y + attribute \src "libresoc.v:139111.19-139111.134" + wire $ternary$libresoc.v:139111$5794_Y + attribute \src "libresoc.v:139112.19-139112.134" + wire $ternary$libresoc.v:139112$5795_Y + attribute \src "libresoc.v:139113.19-139113.134" + wire $ternary$libresoc.v:139113$5796_Y + attribute \src "libresoc.v:139114.19-139114.134" + wire $ternary$libresoc.v:139114$5797_Y + attribute \src "libresoc.v:139115.19-139115.135" + wire $ternary$libresoc.v:139115$5798_Y + attribute \src "libresoc.v:139116.19-139116.134" + wire $ternary$libresoc.v:139116$5799_Y + attribute \src "libresoc.v:139117.19-139117.135" + wire $ternary$libresoc.v:139117$5800_Y + attribute \src "libresoc.v:139118.19-139118.135" + wire $ternary$libresoc.v:139118$5801_Y + attribute \src "libresoc.v:139119.19-139119.134" + wire $ternary$libresoc.v:139119$5802_Y + attribute \src "libresoc.v:139120.19-139120.135" + wire $ternary$libresoc.v:139120$5803_Y + attribute \src "libresoc.v:139122.19-139122.136" + wire $ternary$libresoc.v:139122$5805_Y + attribute \src "libresoc.v:139123.19-139123.135" + wire $ternary$libresoc.v:139123$5806_Y + attribute \src "libresoc.v:139124.19-139124.136" + wire $ternary$libresoc.v:139124$5807_Y + attribute \src "libresoc.v:139125.19-139125.136" + wire $ternary$libresoc.v:139125$5808_Y + attribute \src "libresoc.v:139126.19-139126.135" + wire $ternary$libresoc.v:139126$5809_Y + attribute \src "libresoc.v:139127.19-139127.136" + wire $ternary$libresoc.v:139127$5810_Y + attribute \src "libresoc.v:139128.19-139128.136" + wire $ternary$libresoc.v:139128$5811_Y + attribute \src "libresoc.v:139129.19-139129.135" + wire $ternary$libresoc.v:139129$5812_Y + attribute \src "libresoc.v:139130.19-139130.136" + wire $ternary$libresoc.v:139130$5813_Y + attribute \src "libresoc.v:139131.19-139131.136" + wire $ternary$libresoc.v:139131$5814_Y + attribute \src "libresoc.v:139133.19-139133.135" + wire $ternary$libresoc.v:139133$5816_Y + attribute \src "libresoc.v:139134.19-139134.136" + wire $ternary$libresoc.v:139134$5817_Y + attribute \src "libresoc.v:139135.19-139135.136" + wire $ternary$libresoc.v:139135$5818_Y + attribute \src "libresoc.v:139136.19-139136.135" + wire $ternary$libresoc.v:139136$5819_Y + attribute \src "libresoc.v:139137.19-139137.136" + wire $ternary$libresoc.v:139137$5820_Y + attribute \src "libresoc.v:139138.19-139138.136" + wire $ternary$libresoc.v:139138$5821_Y + attribute \src "libresoc.v:139139.19-139139.135" + wire $ternary$libresoc.v:139139$5822_Y + attribute \src "libresoc.v:139140.19-139140.136" + wire $ternary$libresoc.v:139140$5823_Y + attribute \src "libresoc.v:139227.18-139227.130" + wire $ternary$libresoc.v:139227$5911_Y + attribute \src "libresoc.v:139228.18-139228.130" + wire $ternary$libresoc.v:139228$5912_Y + attribute \src "libresoc.v:139229.18-139229.130" + wire $ternary$libresoc.v:139229$5913_Y + attribute \src "libresoc.v:139230.18-139230.131" + wire $ternary$libresoc.v:139230$5914_Y + attribute \src "libresoc.v:139232.18-139232.130" + wire $ternary$libresoc.v:139232$5916_Y + attribute \src "libresoc.v:139233.18-139233.131" + wire $ternary$libresoc.v:139233$5917_Y + attribute \src "libresoc.v:139234.18-139234.131" + wire $ternary$libresoc.v:139234$5918_Y + attribute \src "libresoc.v:139235.18-139235.130" + wire $ternary$libresoc.v:139235$5919_Y + attribute \src "libresoc.v:139236.18-139236.131" + wire $ternary$libresoc.v:139236$5920_Y + attribute \src "libresoc.v:139237.18-139237.132" + wire $ternary$libresoc.v:139237$5921_Y + attribute \src "libresoc.v:139238.18-139238.132" + wire $ternary$libresoc.v:139238$5922_Y + attribute \src "libresoc.v:139239.18-139239.133" + wire $ternary$libresoc.v:139239$5923_Y + attribute \src "libresoc.v:139240.18-139240.133" + wire $ternary$libresoc.v:139240$5924_Y + attribute \src "libresoc.v:139241.18-139241.132" + wire $ternary$libresoc.v:139241$5925_Y + attribute \src "libresoc.v:139243.18-139243.133" + wire $ternary$libresoc.v:139243$5927_Y + attribute \src "libresoc.v:139244.18-139244.133" + wire $ternary$libresoc.v:139244$5928_Y + attribute \src "libresoc.v:139245.18-139245.132" + wire $ternary$libresoc.v:139245$5929_Y + attribute \src "libresoc.v:139246.18-139246.133" + wire $ternary$libresoc.v:139246$5930_Y + attribute \src "libresoc.v:139247.18-139247.133" + wire $ternary$libresoc.v:139247$5931_Y + attribute \src "libresoc.v:139248.18-139248.132" + wire $ternary$libresoc.v:139248$5932_Y + attribute \src "libresoc.v:139249.18-139249.133" + wire $ternary$libresoc.v:139249$5933_Y + attribute \src "libresoc.v:139250.18-139250.133" + wire $ternary$libresoc.v:139250$5934_Y + attribute \src "libresoc.v:139251.18-139251.132" + wire $ternary$libresoc.v:139251$5935_Y + attribute \src "libresoc.v:139252.18-139252.133" + wire $ternary$libresoc.v:139252$5936_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -216121,246 +218650,242 @@ module \jtag wire \$301 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$305 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$307 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$329 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$349 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$357 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$365 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$369 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$371 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$375 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$379 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$383 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$389 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$393 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$397 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$401 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$405 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$409 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$413 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$413 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$417 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$417 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$421 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$421 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$427 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$427 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$429 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$431 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$435 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$439 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$443 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$447 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$449 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$451 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$455 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$459 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$465 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$469 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$473 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$477 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" wire \$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$481 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$480 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" wire \$483 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$484 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 + wire \$485 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" wire \$489 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$493 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$495 + wire width 30 \$491 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$496 + wire width 30 \$492 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$498 + wire width 30 \$494 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$499 + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$497 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$501 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 + wire \$500 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$506 + wire \$502 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$508 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 + wire \$504 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$510 + wire \$506 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$512 + wire width 5 \$508 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$513 + wire width 5 \$509 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$515 + wire width 5 \$511 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$516 + wire width 5 \$512 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$53 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" @@ -216414,13 +218939,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tck + wire input 325 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 165 \TAP_bus__tdi + wire input 163 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 320 \TAP_bus__tdo + wire output 316 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 330 \TAP_bus__tms + wire input 326 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -216443,8 +218968,8 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 331 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 327 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -216520,27 +219045,27 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_0__core__i + wire output 164 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 11 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_1__core__i + wire output 165 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 12 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \eint_2__core__i + wire output 166 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 13 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503 + wire width 3 \fsm_state$499 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503$next + wire width 3 \fsm_state$499$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__core__i + wire output 173 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 21 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216548,11 +219073,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 20 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__o + wire output 174 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e10__pad__oe + wire output 175 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__core__i + wire output 176 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216560,11 +219085,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__o + wire output 177 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e11__pad__oe + wire output 178 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__core__i + wire output 179 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216572,11 +219097,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__o + wire output 180 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e12__pad__oe + wire output 181 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__core__i + wire output 182 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216584,11 +219109,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__o + wire output 183 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e13__pad__oe + wire output 184 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__core__i + wire output 185 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216596,11 +219121,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__o + wire output 186 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e14__pad__oe + wire output 187 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__core__i + wire output 188 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216608,11 +219133,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__o + wire output 189 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e15__pad__oe + wire output 190 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__core__i + wire output 167 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 15 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216620,11 +219145,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 14 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__o + wire output 168 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e8__pad__oe + wire output 169 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__core__i + wire output 170 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 18 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216632,11 +219157,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 17 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__o + wire output 171 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e9__pad__oe + wire output 172 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__core__i + wire output 191 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216644,11 +219169,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__o + wire output 192 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s0__pad__oe + wire output 193 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__core__i + wire output 194 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216656,11 +219181,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__o + wire output 195 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s1__pad__oe + wire output 196 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__core__i + wire output 197 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216668,11 +219193,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__o + wire output 198 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s2__pad__oe + wire output 199 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__core__i + wire output 200 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216680,11 +219205,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__o + wire output 201 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s3__pad__oe + wire output 202 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__core__i + wire output 203 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216692,11 +219217,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__o + wire output 204 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s4__pad__oe + wire output 205 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__core__i + wire output 206 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216704,11 +219229,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__o + wire output 207 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s5__pad__oe + wire output 208 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__core__i + wire output 209 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216716,11 +219241,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__o + wire output 210 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s6__pad__oe + wire output 211 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__core__i + wire output 212 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216728,15 +219253,15 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__o + wire output 213 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s7__pad__oe - attribute \src "libresoc.v:135928.7-135928.15" + wire output 214 \gpio_s7__pad__oe + attribute \src "libresoc.v:137576.7-137576.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd + wire width 152 \io_bd attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd$next + wire width 152 \io_bd$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" @@ -216746,31 +219271,31 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr + wire width 152 \io_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr$next + wire width 152 \io_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 327 \jtag_wb__ack + wire input 323 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 321 \jtag_wb__adr + wire width 29 output 317 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__cyc + wire output 319 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 328 \jtag_wb__dat_r + wire width 64 input 324 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 326 \jtag_wb__dat_w + wire width 64 output 322 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__sel + wire output 318 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__stb + wire output 320 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 325 \jtag_wb__we + wire output 321 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -216832,41 +219357,41 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_clk__pad__o + wire output 215 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_cs_n__pad__o + wire output 216 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi0_miso__core__i + wire output 218 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 65 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_mosi__pad__o + wire output 217 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_clk__pad__o + wire output 219 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_cs_n__pad__o + wire output 220 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mspi1_miso__core__i + wire output 222 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 68 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_mosi__pad__o + wire output 221 \mspi1_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \mtwi_scl__pad__o + wire output 226 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__core__i + wire output 223 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 71 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216874,9 +219399,9 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__o + wire output 224 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_sda__pad__oe + wire output 225 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -216888,19 +219413,19 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 74 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_0__pad__o + wire output 227 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire output 228 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_clk__pad__o + wire output 232 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__core__i + wire output 229 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216908,11 +219433,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__o + wire output 230 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_cmd__pad__oe + wire output 231 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__core__i + wire output 233 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216920,11 +219445,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__o + wire output 234 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data0__pad__oe + wire output 235 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__core__i + wire output 236 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216932,11 +219457,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__o + wire output 237 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data1__pad__oe + wire output 238 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__core__i + wire output 239 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216944,11 +219469,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__o + wire output 240 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data2__pad__oe + wire output 241 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__core__i + wire output 242 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216956,103 +219481,95 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__o + wire output 243 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_data3__pad__oe + wire output 244 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 117 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_0__pad__o + wire output 270 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_10__pad__o + wire output 288 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_11__pad__o + wire output 289 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_12__pad__o + wire output 290 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_1__pad__o + wire output 271 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_2__pad__o + wire output 272 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 120 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_3__pad__o + wire output 273 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_4__pad__o + wire output 274 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_5__pad__o + wire output 275 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 123 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_6__pad__o + wire output 276 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_7__pad__o + wire output 277 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_8__pad__o + wire output 278 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 126 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_a_9__pad__o + wire output 279 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_0__pad__o + wire output 280 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_ba_1__pad__o + wire output 281 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_cas_n__pad__o + wire output 285 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_cke__pad__o + wire output 283 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 129 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_clock__pad__o + wire output 282 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_cs_n__pad__o + wire output 287 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__core__i + wire output 245 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__o + wire input 138 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dm_1__core__oe + wire output 291 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__core__i + wire output 246 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217060,83 +219577,83 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__o + wire output 247 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_0__pad__oe + wire output 248 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__core__i + wire output 298 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__o + wire input 146 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_10__core__oe + wire input 147 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__pad__i + wire input 145 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__o + wire output 299 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_10__pad__oe + wire output 300 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__core__i + wire output 301 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__o + wire input 149 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_11__core__oe + wire input 150 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__pad__i + wire input 148 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__o + wire output 302 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_11__pad__oe + wire output 303 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__core__i + wire output 304 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__o + wire input 152 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_12__core__oe + wire input 153 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__pad__i + wire input 151 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__o + wire output 305 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_12__pad__oe + wire output 306 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__core__i + wire output 307 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__o + wire input 155 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_13__core__oe + wire input 156 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__pad__i + wire input 154 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__o + wire output 308 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__oe + wire output 309 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__core__i + wire output 310 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__o + wire input 158 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_14__core__oe + wire input 159 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__pad__i + wire input 157 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__o + wire output 311 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_14__pad__oe + wire output 312 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__core__i + wire output 313 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__o + wire input 161 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_15__core__oe + wire input 162 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__pad__i + wire input 160 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__o + wire output 314 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_15__pad__oe + wire output 315 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__core__i + wire output 249 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217144,11 +219661,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__o + wire output 250 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_1__pad__oe + wire output 251 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__core__i + wire output 252 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217156,11 +219673,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__o + wire output 253 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_2__pad__oe + wire output 254 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__core__i + wire output 255 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217168,11 +219685,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__o + wire output 256 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_3__pad__oe + wire output 257 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__core__i + wire output 258 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217180,11 +219697,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__o + wire output 259 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_4__pad__oe + wire output 260 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__core__i + wire output 261 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217192,11 +219709,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 108 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__o + wire output 262 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_5__pad__oe + wire output 263 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__core__i + wire output 264 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217204,11 +219721,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 111 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__o + wire output 265 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_6__pad__oe + wire output 266 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__core__i + wire output 267 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217216,41 +219733,41 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 114 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__o + wire output 268 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_7__pad__oe + wire output 269 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__core__i + wire output 292 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__o + wire input 140 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_8__core__oe + wire input 141 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__pad__i + wire input 139 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__o + wire output 293 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_8__pad__oe + wire output 294 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__core__i + wire output 295 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__o + wire input 143 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_9__core__oe + wire input 144 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__pad__i + wire input 142 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__o + wire output 296 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_9__pad__oe + wire output 297 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_ras_n__pad__o + wire output 284 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_we_n__pad__o + wire output 286 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -217322,7 +219839,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:137583$5852 + cell $add $add$libresoc.v:139217$5900 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -217330,10 +219847,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:137583$5852_Y + connect \Y $add$libresoc.v:139217$5900_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:137585$5854 + cell $add $add$libresoc.v:139218$5901 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -217341,10 +219858,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:137585$5854_Y + connect \Y $add$libresoc.v:139218$5901_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:137591$5861 + cell $add $add$libresoc.v:139225$5909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217352,10 +219869,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:137591$5861_Y + connect \Y $add$libresoc.v:139225$5909_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:137592$5862 + cell $add $add$libresoc.v:139226$5910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217363,10 +219880,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:137592$5862_Y + connect \Y $add$libresoc.v:139226$5910_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:137407$5676 + cell $and $and$libresoc.v:139043$5726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217374,10 +219891,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137407$5676_Y + connect \Y $and$libresoc.v:139043$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137474$5743 + cell $and $and$libresoc.v:139110$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217385,10 +219902,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:137474$5743_Y + connect \Y $and$libresoc.v:139110$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:137485$5754 + cell $and $and$libresoc.v:139121$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217396,307 +219913,307 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137485$5754_Y + connect \Y $and$libresoc.v:139121$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137513$5782 + cell $and $and$libresoc.v:139147$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$367 - connect \Y $and$libresoc.v:137513$5782_Y + connect \B \$363 + connect \Y $and$libresoc.v:139147$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137516$5785 + cell $and $and$libresoc.v:139150$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$373 + connect \A \$369 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137516$5785_Y + connect \Y $and$libresoc.v:139150$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137519$5788 + cell $and $and$libresoc.v:139152$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$377 + connect \A \$373 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137519$5788_Y + connect \Y $and$libresoc.v:139152$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137521$5790 + cell $and $and$libresoc.v:139155$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$381 + connect \A \$377 connect \B \_fsm_update - connect \Y $and$libresoc.v:137521$5790_Y + connect \Y $and$libresoc.v:139155$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137523$5792 + cell $and $and$libresoc.v:139157$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev - connect \B \$385 - connect \Y $and$libresoc.v:137523$5792_Y + connect \B \$381 + connect \Y $and$libresoc.v:139157$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137526$5795 + cell $and $and$libresoc.v:139160$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$391 + connect \A \$387 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137526$5795_Y + connect \Y $and$libresoc.v:139160$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137528$5797 + cell $and $and$libresoc.v:139162$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 + connect \A \$391 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137528$5797_Y + connect \Y $and$libresoc.v:139162$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137532$5801 + cell $and $and$libresoc.v:139164$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$399 + connect \A \$395 connect \B \_fsm_update - connect \Y $and$libresoc.v:137532$5801_Y + connect \Y $and$libresoc.v:139164$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137534$5803 + cell $and $and$libresoc.v:139168$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$403 - connect \Y $and$libresoc.v:137534$5803_Y + connect \B \$399 + connect \Y $and$libresoc.v:139168$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137538$5807 + cell $and $and$libresoc.v:139172$5855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$411 + connect \A \$407 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137538$5807_Y + connect \Y $and$libresoc.v:139172$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137540$5809 + cell $and $and$libresoc.v:139174$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$415 + connect \A \$411 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137540$5809_Y + connect \Y $and$libresoc.v:139174$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137543$5812 + cell $and $and$libresoc.v:139176$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$419 + connect \A \$415 connect \B \_fsm_update - connect \Y $and$libresoc.v:137543$5812_Y + connect \Y $and$libresoc.v:139176$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137545$5814 + cell $and $and$libresoc.v:139179$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev - connect \B \$423 - connect \Y $and$libresoc.v:137545$5814_Y + connect \B \$419 + connect \Y $and$libresoc.v:139179$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137548$5817 + cell $and $and$libresoc.v:139182$5865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 + connect \A \$425 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137548$5817_Y + connect \Y $and$libresoc.v:139182$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137550$5819 + cell $and $and$libresoc.v:139184$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 + connect \A \$429 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137550$5819_Y + connect \Y $and$libresoc.v:139184$5867_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137552$5821 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139186$5869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:137552$5821_Y + connect \A \$433 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139186$5869_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137553$5822 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139188$5871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$437 - connect \B \_fsm_update - connect \Y $and$libresoc.v:137553$5822_Y + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:139188$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137555$5824 + cell $and $and$libresoc.v:139189$5872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev - connect \B \$441 - connect \Y $and$libresoc.v:137555$5824_Y + connect \B \$437 + connect \Y $and$libresoc.v:139189$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137559$5828 + cell $and $and$libresoc.v:139193$5876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$449 + connect \A \$445 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137559$5828_Y + connect \Y $and$libresoc.v:139193$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137561$5830 + cell $and $and$libresoc.v:139195$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$453 + connect \A \$449 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137561$5830_Y + connect \Y $and$libresoc.v:139195$5878_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:137563$5832 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139197$5880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$43 + connect \A \$453 connect \B \_fsm_update - connect \Y $and$libresoc.v:137563$5832_Y + connect \Y $and$libresoc.v:139197$5880_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137564$5833 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:139199$5882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$457 + connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:137564$5833_Y + connect \Y $and$libresoc.v:139199$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137566$5835 + cell $and $and$libresoc.v:139200$5883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev - connect \B \$461 - connect \Y $and$libresoc.v:137566$5835_Y + connect \B \$457 + connect \Y $and$libresoc.v:139200$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137569$5838 + cell $and $and$libresoc.v:139203$5886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$467 + connect \A \$463 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137569$5838_Y + connect \Y $and$libresoc.v:139203$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137571$5840 + cell $and $and$libresoc.v:139205$5888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 + connect \A \$467 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137571$5840_Y + connect \Y $and$libresoc.v:139205$5888_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137573$5842 + cell $and $and$libresoc.v:139207$5890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$475 + connect \A \$471 connect \B \_fsm_update - connect \Y $and$libresoc.v:137573$5842_Y + connect \Y $and$libresoc.v:139207$5890_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137576$5845 + cell $and $and$libresoc.v:139209$5892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev - connect \B \$479 - connect \Y $and$libresoc.v:137576$5845_Y + connect \B \$475 + connect \Y $and$libresoc.v:139209$5892_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:137608$5878 + cell $and $and$libresoc.v:139242$5926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217704,10 +220221,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:137608$5878_Y + connect \Y $and$libresoc.v:139242$5926_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:137363$5632 + cell $eq $eq$libresoc.v:138999$5682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217715,10 +220232,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:137363$5632_Y + connect \Y $eq$libresoc.v:138999$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137374$5643 + cell $eq $eq$libresoc.v:139010$5693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217726,10 +220243,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137374$5643_Y + connect \Y $eq$libresoc.v:139010$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137385$5654 + cell $eq $eq$libresoc.v:139021$5704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217737,10 +220254,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137385$5654_Y + connect \Y $eq$libresoc.v:139021$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:137418$5687 + cell $eq $eq$libresoc.v:139054$5737 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217748,10 +220265,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:137418$5687_Y + connect \Y $eq$libresoc.v:139054$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137419$5688 + cell $eq $eq$libresoc.v:139055$5738 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217759,10 +220276,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137419$5688_Y + connect \Y $eq$libresoc.v:139055$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137430$5699 + cell $eq $eq$libresoc.v:139066$5749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217770,10 +220287,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137430$5699_Y + connect \Y $eq$libresoc.v:139066$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137452$5721 + cell $eq $eq$libresoc.v:139088$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217781,10 +220298,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137452$5721_Y + connect \Y $eq$libresoc.v:139088$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137496$5765 + cell $eq $eq$libresoc.v:139132$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217792,32 +220309,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137496$5765_Y + connect \Y $eq$libresoc.v:139132$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137507$5776 + cell $eq $eq$libresoc.v:139141$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:137507$5776_Y + connect \B 1'0 + connect \Y $eq$libresoc.v:139141$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137508$5777 + cell $eq $eq$libresoc.v:139142$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:137508$5777_Y + connect \B 2'10 + connect \Y $eq$libresoc.v:139142$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137509$5778 + cell $eq $eq$libresoc.v:139143$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217825,10 +220342,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137509$5778_Y + connect \Y $eq$libresoc.v:139143$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137511$5780 + cell $eq $eq$libresoc.v:139145$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217836,10 +220353,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137511$5780_Y + connect \Y $eq$libresoc.v:139145$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137514$5783 + cell $eq $eq$libresoc.v:139148$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217847,10 +220364,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:137514$5783_Y + connect \Y $eq$libresoc.v:139148$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137524$5793 + cell $eq $eq$libresoc.v:139158$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217858,10 +220375,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:137524$5793_Y + connect \Y $eq$libresoc.v:139158$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:137529$5798 + cell $eq $eq$libresoc.v:139165$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217869,10 +220386,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:137529$5798_Y + connect \Y $eq$libresoc.v:139165$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137530$5799 + cell $eq $eq$libresoc.v:139166$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217880,10 +220397,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137530$5799_Y + connect \Y $eq$libresoc.v:139166$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137535$5804 + cell $eq $eq$libresoc.v:139169$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217891,10 +220408,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:137535$5804_Y + connect \Y $eq$libresoc.v:139169$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137536$5805 + cell $eq $eq$libresoc.v:139170$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217902,10 +220419,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:137536$5805_Y + connect \Y $eq$libresoc.v:139170$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137546$5815 + cell $eq $eq$libresoc.v:139180$5863 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217913,10 +220430,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:137546$5815_Y + connect \Y $eq$libresoc.v:139180$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137556$5825 + cell $eq $eq$libresoc.v:139190$5873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217924,10 +220441,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:137556$5825_Y + connect \Y $eq$libresoc.v:139190$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137557$5826 + cell $eq $eq$libresoc.v:139191$5874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217935,10 +220452,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:137557$5826_Y + connect \Y $eq$libresoc.v:139191$5874_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137567$5836 + cell $eq $eq$libresoc.v:139201$5884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217946,10 +220463,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:137567$5836_Y + connect \Y $eq$libresoc.v:139201$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:137574$5843 + cell $eq $eq$libresoc.v:139210$5893 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217957,10 +220474,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137574$5843_Y + connect \Y $eq$libresoc.v:139210$5893_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:137577$5846 + cell $eq $eq$libresoc.v:139211$5894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217968,10 +220485,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:137577$5846_Y + connect \Y $eq$libresoc.v:139211$5894_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:137579$5848 + cell $eq $eq$libresoc.v:139213$5896 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217979,10 +220496,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:137579$5848_Y + connect \Y $eq$libresoc.v:139213$5896_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:137580$5849 + cell $eq $eq$libresoc.v:139214$5897 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217990,10 +220507,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:137580$5849_Y + connect \Y $eq$libresoc.v:139214$5897_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:137582$5851 + cell $eq $eq$libresoc.v:139216$5899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -218001,10 +220518,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:137582$5851_Y + connect \Y $eq$libresoc.v:139216$5899_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:137584$5853 + cell $eq $eq$libresoc.v:139220$5904 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -218012,51 +220529,51 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137584$5853_Y + connect \Y $eq$libresoc.v:139220$5904_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:137587$5857 + cell $eq $eq$libresoc.v:139221$5905 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 1'1 - connect \Y $eq$libresoc.v:137587$5857_Y + connect \Y $eq$libresoc.v:139221$5905_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:137588$5858 + cell $eq $eq$libresoc.v:139222$5906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:137588$5858_Y + connect \Y $eq$libresoc.v:139222$5906_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:137590$5860 + cell $eq $eq$libresoc.v:139224$5908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:137590$5860_Y + connect \Y $eq$libresoc.v:139224$5908_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:137586$5855 + cell $pos $extend$libresoc.v:139219$5902 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:137586$5855_Y + connect \Y $extend$libresoc.v:139219$5902_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137515$5784 + cell $ne $ne$libresoc.v:139149$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218064,10 +220581,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137515$5784_Y + connect \Y $ne$libresoc.v:139149$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137517$5786 + cell $ne $ne$libresoc.v:139151$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218075,10 +220592,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137517$5786_Y + connect \Y $ne$libresoc.v:139151$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137520$5789 + cell $ne $ne$libresoc.v:139153$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218086,10 +220603,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137520$5789_Y + connect \Y $ne$libresoc.v:139153$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137525$5794 + cell $ne $ne$libresoc.v:139159$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218097,10 +220614,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137525$5794_Y + connect \Y $ne$libresoc.v:139159$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137527$5796 + cell $ne $ne$libresoc.v:139161$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218108,10 +220625,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137527$5796_Y + connect \Y $ne$libresoc.v:139161$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137531$5800 + cell $ne $ne$libresoc.v:139163$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218119,10 +220636,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137531$5800_Y + connect \Y $ne$libresoc.v:139163$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137537$5806 + cell $ne $ne$libresoc.v:139171$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218130,10 +220647,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137537$5806_Y + connect \Y $ne$libresoc.v:139171$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137539$5808 + cell $ne $ne$libresoc.v:139173$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218141,10 +220658,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137539$5808_Y + connect \Y $ne$libresoc.v:139173$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137542$5811 + cell $ne $ne$libresoc.v:139175$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218152,10 +220669,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137542$5811_Y + connect \Y $ne$libresoc.v:139175$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137547$5816 + cell $ne $ne$libresoc.v:139181$5864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218163,10 +220680,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137547$5816_Y + connect \Y $ne$libresoc.v:139181$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137549$5818 + cell $ne $ne$libresoc.v:139183$5866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218174,10 +220691,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137549$5818_Y + connect \Y $ne$libresoc.v:139183$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137551$5820 + cell $ne $ne$libresoc.v:139185$5868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218185,10 +220702,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137551$5820_Y + connect \Y $ne$libresoc.v:139185$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137558$5827 + cell $ne $ne$libresoc.v:139192$5875 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218196,10 +220713,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137558$5827_Y + connect \Y $ne$libresoc.v:139192$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137560$5829 + cell $ne $ne$libresoc.v:139194$5877 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218207,10 +220724,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137560$5829_Y + connect \Y $ne$libresoc.v:139194$5877_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137562$5831 + cell $ne $ne$libresoc.v:139196$5879 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218218,10 +220735,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137562$5831_Y + connect \Y $ne$libresoc.v:139196$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137568$5837 + cell $ne $ne$libresoc.v:139202$5885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218229,10 +220746,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137568$5837_Y + connect \Y $ne$libresoc.v:139202$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137570$5839 + cell $ne $ne$libresoc.v:139204$5887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218240,10 +220757,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137570$5839_Y + connect \Y $ne$libresoc.v:139204$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137572$5841 + cell $ne $ne$libresoc.v:139206$5889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218251,66 +220768,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137572$5841_Y + connect \Y $ne$libresoc.v:139206$5889_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137522$5791 + cell $not $not$libresoc.v:139156$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:137522$5791_Y + connect \Y $not$libresoc.v:139156$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137533$5802 + cell $not $not$libresoc.v:139167$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:137533$5802_Y + connect \Y $not$libresoc.v:139167$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137544$5813 + cell $not $not$libresoc.v:139178$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:137544$5813_Y + connect \Y $not$libresoc.v:139178$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137554$5823 + cell $not $not$libresoc.v:139187$5870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:137554$5823_Y + connect \Y $not$libresoc.v:139187$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137565$5834 + cell $not $not$libresoc.v:139198$5881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:137565$5834_Y + connect \Y $not$libresoc.v:139198$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137575$5844 + cell $not $not$libresoc.v:139208$5891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:137575$5844_Y + connect \Y $not$libresoc.v:139208$5891_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:137578$5847 + cell $not $not$libresoc.v:139212$5895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$484 - connect \Y $not$libresoc.v:137578$5847_Y + connect \A \$480 + connect \Y $not$libresoc.v:139212$5895_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137396$5665 + cell $or $or$libresoc.v:139032$5715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218318,10 +220835,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:137396$5665_Y + connect \Y $or$libresoc.v:139032$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137441$5710 + cell $or $or$libresoc.v:139077$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218329,10 +220846,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:137441$5710_Y + connect \Y $or$libresoc.v:139077$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137463$5732 + cell $or $or$libresoc.v:139099$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218340,32 +220857,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:137463$5732_Y + connect \Y $or$libresoc.v:139099$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137510$5779 + cell $or $or$libresoc.v:139144$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:137510$5779_Y + connect \A \$355 + connect \B \$357 + connect \Y $or$libresoc.v:139144$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137512$5781 + cell $or $or$libresoc.v:139146$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$363 - connect \B \$365 - connect \Y $or$libresoc.v:137512$5781_Y + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:139146$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137518$5787 + cell $or $or$libresoc.v:139154$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218373,10 +220890,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:137518$5787_Y + connect \Y $or$libresoc.v:139154$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137541$5810 + cell $or $or$libresoc.v:139177$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218384,32 +220901,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:137541$5810_Y + connect \Y $or$libresoc.v:139177$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:137581$5850 + cell $or $or$libresoc.v:139215$5898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$487 - connect \B \$489 - connect \Y $or$libresoc.v:137581$5850_Y + connect \A \$483 + connect \B \$485 + connect \Y $or$libresoc.v:139215$5898_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:137589$5859 + cell $or $or$libresoc.v:139223$5907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$504 - connect \B \$506 - connect \Y $or$libresoc.v:137589$5859_Y + connect \A \$500 + connect \B \$502 + connect \Y $or$libresoc.v:139223$5907_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:137597$5867 + cell $or $or$libresoc.v:139231$5915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218417,1250 +220934,1234 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:137597$5867_Y + connect \Y $or$libresoc.v:139231$5915_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:137586$5856 + cell $pos $pos$libresoc.v:139219$5903 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:137586$5855_Y - connect \Y $pos$libresoc.v:137586$5856_Y + connect \A $extend$libresoc.v:139219$5902_Y + connect \Y $pos$libresoc.v:139219$5903_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137364$5633 + cell $mux $ternary$libresoc.v:139000$5683 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137364$5633_Y + connect \Y $ternary$libresoc.v:139000$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137365$5634 + cell $mux $ternary$libresoc.v:139001$5684 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137365$5634_Y + connect \Y $ternary$libresoc.v:139001$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137366$5635 + cell $mux $ternary$libresoc.v:139002$5685 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137366$5635_Y + connect \Y $ternary$libresoc.v:139002$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137367$5636 + cell $mux $ternary$libresoc.v:139003$5686 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137367$5636_Y + connect \Y $ternary$libresoc.v:139003$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137368$5637 + cell $mux $ternary$libresoc.v:139004$5687 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137368$5637_Y + connect \Y $ternary$libresoc.v:139004$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137369$5638 + cell $mux $ternary$libresoc.v:139005$5688 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137369$5638_Y + connect \Y $ternary$libresoc.v:139005$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137370$5639 + cell $mux $ternary$libresoc.v:139006$5689 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137370$5639_Y + connect \Y $ternary$libresoc.v:139006$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137371$5640 + cell $mux $ternary$libresoc.v:139007$5690 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137371$5640_Y + connect \Y $ternary$libresoc.v:139007$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137372$5641 + cell $mux $ternary$libresoc.v:139008$5691 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137372$5641_Y + connect \Y $ternary$libresoc.v:139008$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137373$5642 + cell $mux $ternary$libresoc.v:139009$5692 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137373$5642_Y + connect \Y $ternary$libresoc.v:139009$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137375$5644 + cell $mux $ternary$libresoc.v:139011$5694 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137375$5644_Y + connect \Y $ternary$libresoc.v:139011$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137376$5645 + cell $mux $ternary$libresoc.v:139012$5695 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137376$5645_Y + connect \Y $ternary$libresoc.v:139012$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137377$5646 + cell $mux $ternary$libresoc.v:139013$5696 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137377$5646_Y + connect \Y $ternary$libresoc.v:139013$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137378$5647 + cell $mux $ternary$libresoc.v:139014$5697 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137378$5647_Y + connect \Y $ternary$libresoc.v:139014$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137379$5648 + cell $mux $ternary$libresoc.v:139015$5698 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137379$5648_Y + connect \Y $ternary$libresoc.v:139015$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137380$5649 + cell $mux $ternary$libresoc.v:139016$5699 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137380$5649_Y + connect \Y $ternary$libresoc.v:139016$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137381$5650 + cell $mux $ternary$libresoc.v:139017$5700 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137381$5650_Y + connect \Y $ternary$libresoc.v:139017$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137382$5651 + cell $mux $ternary$libresoc.v:139018$5701 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137382$5651_Y + connect \Y $ternary$libresoc.v:139018$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137383$5652 + cell $mux $ternary$libresoc.v:139019$5702 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137383$5652_Y + connect \Y $ternary$libresoc.v:139019$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137384$5653 + cell $mux $ternary$libresoc.v:139020$5703 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137384$5653_Y + connect \Y $ternary$libresoc.v:139020$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137386$5655 + cell $mux $ternary$libresoc.v:139022$5705 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137386$5655_Y + connect \Y $ternary$libresoc.v:139022$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137387$5656 + cell $mux $ternary$libresoc.v:139023$5706 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137387$5656_Y + connect \Y $ternary$libresoc.v:139023$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137388$5657 + cell $mux $ternary$libresoc.v:139024$5707 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137388$5657_Y + connect \Y $ternary$libresoc.v:139024$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137389$5658 + cell $mux $ternary$libresoc.v:139025$5708 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137389$5658_Y + connect \Y $ternary$libresoc.v:139025$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137390$5659 + cell $mux $ternary$libresoc.v:139026$5709 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137390$5659_Y + connect \Y $ternary$libresoc.v:139026$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137391$5660 + cell $mux $ternary$libresoc.v:139027$5710 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137391$5660_Y + connect \Y $ternary$libresoc.v:139027$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137392$5661 + cell $mux $ternary$libresoc.v:139028$5711 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137392$5661_Y + connect \Y $ternary$libresoc.v:139028$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137393$5662 + cell $mux $ternary$libresoc.v:139029$5712 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137393$5662_Y + connect \Y $ternary$libresoc.v:139029$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137394$5663 + cell $mux $ternary$libresoc.v:139030$5713 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137394$5663_Y + connect \Y $ternary$libresoc.v:139030$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137395$5664 + cell $mux $ternary$libresoc.v:139031$5714 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137395$5664_Y + connect \Y $ternary$libresoc.v:139031$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137397$5666 + cell $mux $ternary$libresoc.v:139033$5716 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137397$5666_Y + connect \Y $ternary$libresoc.v:139033$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137398$5667 + cell $mux $ternary$libresoc.v:139034$5717 parameter \WIDTH 1 connect \A \mspi1_clk__core__o connect \B \io_bd [55] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137398$5667_Y + connect \Y $ternary$libresoc.v:139034$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137399$5668 + cell $mux $ternary$libresoc.v:139035$5718 parameter \WIDTH 1 connect \A \mspi1_cs_n__core__o connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137399$5668_Y + connect \Y $ternary$libresoc.v:139035$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137400$5669 + cell $mux $ternary$libresoc.v:139036$5719 parameter \WIDTH 1 connect \A \mspi1_mosi__core__o connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137400$5669_Y + connect \Y $ternary$libresoc.v:139036$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137401$5670 + cell $mux $ternary$libresoc.v:139037$5720 parameter \WIDTH 1 connect \A \mspi1_miso__pad__i connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137401$5670_Y + connect \Y $ternary$libresoc.v:139037$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137402$5671 + cell $mux $ternary$libresoc.v:139038$5721 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [59] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137402$5671_Y + connect \Y $ternary$libresoc.v:139038$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137403$5672 + cell $mux $ternary$libresoc.v:139039$5722 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137403$5672_Y + connect \Y $ternary$libresoc.v:139039$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137404$5673 + cell $mux $ternary$libresoc.v:139040$5723 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137404$5673_Y + connect \Y $ternary$libresoc.v:139040$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137405$5674 + cell $mux $ternary$libresoc.v:139041$5724 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137405$5674_Y + connect \Y $ternary$libresoc.v:139041$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137406$5675 + cell $mux $ternary$libresoc.v:139042$5725 parameter \WIDTH 1 connect \A \pwm_0__core__o connect \B \io_bd [63] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137406$5675_Y + connect \Y $ternary$libresoc.v:139042$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137408$5677 + cell $mux $ternary$libresoc.v:139044$5727 parameter \WIDTH 1 connect \A \pwm_1__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137408$5677_Y + connect \Y $ternary$libresoc.v:139044$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137409$5678 + cell $mux $ternary$libresoc.v:139045$5728 parameter \WIDTH 1 connect \A \sd0_cmd__pad__i connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137409$5678_Y + connect \Y $ternary$libresoc.v:139045$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137410$5679 + cell $mux $ternary$libresoc.v:139046$5729 parameter \WIDTH 1 connect \A \sd0_cmd__core__o connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137410$5679_Y + connect \Y $ternary$libresoc.v:139046$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137411$5680 + cell $mux $ternary$libresoc.v:139047$5730 parameter \WIDTH 1 connect \A \sd0_cmd__core__oe connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137411$5680_Y + connect \Y $ternary$libresoc.v:139047$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137412$5681 + cell $mux $ternary$libresoc.v:139048$5731 parameter \WIDTH 1 connect \A \sd0_clk__core__o connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137412$5681_Y + connect \Y $ternary$libresoc.v:139048$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137413$5682 + cell $mux $ternary$libresoc.v:139049$5732 parameter \WIDTH 1 connect \A \sd0_data0__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137413$5682_Y + connect \Y $ternary$libresoc.v:139049$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137414$5683 + cell $mux $ternary$libresoc.v:139050$5733 parameter \WIDTH 1 connect \A \sd0_data0__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137414$5683_Y + connect \Y $ternary$libresoc.v:139050$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137415$5684 + cell $mux $ternary$libresoc.v:139051$5734 parameter \WIDTH 1 connect \A \sd0_data0__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137415$5684_Y + connect \Y $ternary$libresoc.v:139051$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137416$5685 + cell $mux $ternary$libresoc.v:139052$5735 parameter \WIDTH 1 connect \A \sd0_data1__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137416$5685_Y + connect \Y $ternary$libresoc.v:139052$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137417$5686 + cell $mux $ternary$libresoc.v:139053$5736 parameter \WIDTH 1 connect \A \sd0_data1__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137417$5686_Y + connect \Y $ternary$libresoc.v:139053$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137420$5689 + cell $mux $ternary$libresoc.v:139056$5739 parameter \WIDTH 1 connect \A \sd0_data1__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137420$5689_Y + connect \Y $ternary$libresoc.v:139056$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137421$5690 + cell $mux $ternary$libresoc.v:139057$5740 parameter \WIDTH 1 connect \A \sd0_data2__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137421$5690_Y + connect \Y $ternary$libresoc.v:139057$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137422$5691 + cell $mux $ternary$libresoc.v:139058$5741 parameter \WIDTH 1 connect \A \sd0_data2__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137422$5691_Y + connect \Y $ternary$libresoc.v:139058$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137423$5692 + cell $mux $ternary$libresoc.v:139059$5742 parameter \WIDTH 1 connect \A \sd0_data2__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137423$5692_Y + connect \Y $ternary$libresoc.v:139059$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137424$5693 + cell $mux $ternary$libresoc.v:139060$5743 parameter \WIDTH 1 connect \A \sd0_data3__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137424$5693_Y + connect \Y $ternary$libresoc.v:139060$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137425$5694 + cell $mux $ternary$libresoc.v:139061$5744 parameter \WIDTH 1 connect \A \sd0_data3__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137425$5694_Y + connect \Y $ternary$libresoc.v:139061$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137426$5695 + cell $mux $ternary$libresoc.v:139062$5745 parameter \WIDTH 1 connect \A \sd0_data3__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137426$5695_Y + connect \Y $ternary$libresoc.v:139062$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137427$5696 + cell $mux $ternary$libresoc.v:139063$5746 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [81] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137427$5696_Y + connect \Y $ternary$libresoc.v:139063$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137428$5697 + cell $mux $ternary$libresoc.v:139064$5747 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137428$5697_Y + connect \Y $ternary$libresoc.v:139064$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137429$5698 + cell $mux $ternary$libresoc.v:139065$5748 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137429$5698_Y + connect \Y $ternary$libresoc.v:139065$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137431$5700 + cell $mux $ternary$libresoc.v:139067$5750 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137431$5700_Y + connect \Y $ternary$libresoc.v:139067$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137432$5701 + cell $mux $ternary$libresoc.v:139068$5751 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137432$5701_Y + connect \Y $ternary$libresoc.v:139068$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137433$5702 + cell $mux $ternary$libresoc.v:139069$5752 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137433$5702_Y + connect \Y $ternary$libresoc.v:139069$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137434$5703 + cell $mux $ternary$libresoc.v:139070$5753 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137434$5703_Y + connect \Y $ternary$libresoc.v:139070$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137435$5704 + cell $mux $ternary$libresoc.v:139071$5754 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137435$5704_Y + connect \Y $ternary$libresoc.v:139071$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137436$5705 + cell $mux $ternary$libresoc.v:139072$5755 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137436$5705_Y + connect \Y $ternary$libresoc.v:139072$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137437$5706 + cell $mux $ternary$libresoc.v:139073$5756 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137437$5706_Y + connect \Y $ternary$libresoc.v:139073$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137438$5707 + cell $mux $ternary$libresoc.v:139074$5757 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [91] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137438$5707_Y + connect \Y $ternary$libresoc.v:139074$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137439$5708 + cell $mux $ternary$libresoc.v:139075$5758 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137439$5708_Y + connect \Y $ternary$libresoc.v:139075$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137440$5709 + cell $mux $ternary$libresoc.v:139076$5759 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137440$5709_Y + connect \Y $ternary$libresoc.v:139076$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137442$5711 + cell $mux $ternary$libresoc.v:139078$5761 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [94] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137442$5711_Y + connect \Y $ternary$libresoc.v:139078$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137443$5712 + cell $mux $ternary$libresoc.v:139079$5762 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137443$5712_Y + connect \Y $ternary$libresoc.v:139079$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137444$5713 + cell $mux $ternary$libresoc.v:139080$5763 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137444$5713_Y + connect \Y $ternary$libresoc.v:139080$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137445$5714 + cell $mux $ternary$libresoc.v:139081$5764 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [97] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137445$5714_Y + connect \Y $ternary$libresoc.v:139081$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137446$5715 + cell $mux $ternary$libresoc.v:139082$5765 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137446$5715_Y + connect \Y $ternary$libresoc.v:139082$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137447$5716 + cell $mux $ternary$libresoc.v:139083$5766 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137447$5716_Y + connect \Y $ternary$libresoc.v:139083$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137448$5717 + cell $mux $ternary$libresoc.v:139084$5767 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [100] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137448$5717_Y + connect \Y $ternary$libresoc.v:139084$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137449$5718 + cell $mux $ternary$libresoc.v:139085$5768 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137449$5718_Y + connect \Y $ternary$libresoc.v:139085$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137450$5719 + cell $mux $ternary$libresoc.v:139086$5769 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137450$5719_Y + connect \Y $ternary$libresoc.v:139086$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137451$5720 + cell $mux $ternary$libresoc.v:139087$5770 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [103] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137451$5720_Y + connect \Y $ternary$libresoc.v:139087$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137453$5722 + cell $mux $ternary$libresoc.v:139089$5772 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137453$5722_Y + connect \Y $ternary$libresoc.v:139089$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137454$5723 + cell $mux $ternary$libresoc.v:139090$5773 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137454$5723_Y + connect \Y $ternary$libresoc.v:139090$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137455$5724 + cell $mux $ternary$libresoc.v:139091$5774 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137455$5724_Y + connect \Y $ternary$libresoc.v:139091$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137456$5725 + cell $mux $ternary$libresoc.v:139092$5775 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137456$5725_Y + connect \Y $ternary$libresoc.v:139092$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137457$5726 + cell $mux $ternary$libresoc.v:139093$5776 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137457$5726_Y + connect \Y $ternary$libresoc.v:139093$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137458$5727 + cell $mux $ternary$libresoc.v:139094$5777 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137458$5727_Y + connect \Y $ternary$libresoc.v:139094$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137459$5728 + cell $mux $ternary$libresoc.v:139095$5778 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137459$5728_Y + connect \Y $ternary$libresoc.v:139095$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137460$5729 + cell $mux $ternary$libresoc.v:139096$5779 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137460$5729_Y + connect \Y $ternary$libresoc.v:139096$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137461$5730 + cell $mux $ternary$libresoc.v:139097$5780 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137461$5730_Y + connect \Y $ternary$libresoc.v:139097$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137462$5731 + cell $mux $ternary$libresoc.v:139098$5781 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137462$5731_Y + connect \Y $ternary$libresoc.v:139098$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137464$5733 + cell $mux $ternary$libresoc.v:139100$5783 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137464$5733_Y + connect \Y $ternary$libresoc.v:139100$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137465$5734 + cell $mux $ternary$libresoc.v:139101$5784 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137465$5734_Y + connect \Y $ternary$libresoc.v:139101$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137466$5735 + cell $mux $ternary$libresoc.v:139102$5785 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137466$5735_Y + connect \Y $ternary$libresoc.v:139102$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137467$5736 + cell $mux $ternary$libresoc.v:139103$5786 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137467$5736_Y + connect \Y $ternary$libresoc.v:139103$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137468$5737 + cell $mux $ternary$libresoc.v:139104$5787 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137468$5737_Y + connect \Y $ternary$libresoc.v:139104$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137469$5738 + cell $mux $ternary$libresoc.v:139105$5788 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137469$5738_Y + connect \Y $ternary$libresoc.v:139105$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137470$5739 + cell $mux $ternary$libresoc.v:139106$5789 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137470$5739_Y + connect \Y $ternary$libresoc.v:139106$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137471$5740 + cell $mux $ternary$libresoc.v:139107$5790 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137471$5740_Y + connect \Y $ternary$libresoc.v:139107$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137472$5741 + cell $mux $ternary$libresoc.v:139108$5791 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137472$5741_Y + connect \Y $ternary$libresoc.v:139108$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137473$5742 + cell $mux $ternary$libresoc.v:139109$5792 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137473$5742_Y + connect \Y $ternary$libresoc.v:139109$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137475$5744 + cell $mux $ternary$libresoc.v:139111$5794 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137475$5744_Y + connect \Y $ternary$libresoc.v:139111$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137476$5745 + cell $mux $ternary$libresoc.v:139112$5795 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137476$5745_Y + connect \Y $ternary$libresoc.v:139112$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137477$5746 + cell $mux $ternary$libresoc.v:139113$5796 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137477$5746_Y + connect \Y $ternary$libresoc.v:139113$5796_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137478$5747 - parameter \WIDTH 1 - connect \A \sdr_dm_1__pad__i - connect \B \io_bd [127] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137478$5747_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137479$5748 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139114$5797 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o - connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137479$5748_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137480$5749 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__oe - connect \B \io_bd [129] + connect \B \io_bd [127] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137480$5749_Y + connect \Y $ternary$libresoc.v:139114$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137481$5750 + cell $mux $ternary$libresoc.v:139115$5798 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i - connect \B \io_bd [130] + connect \B \io_bd [128] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137481$5750_Y + connect \Y $ternary$libresoc.v:139115$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137482$5751 + cell $mux $ternary$libresoc.v:139116$5799 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o - connect \B \io_bd [131] + connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137482$5751_Y + connect \Y $ternary$libresoc.v:139116$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137483$5752 + cell $mux $ternary$libresoc.v:139117$5800 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe - connect \B \io_bd [132] + connect \B \io_bd [130] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137483$5752_Y + connect \Y $ternary$libresoc.v:139117$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137484$5753 + cell $mux $ternary$libresoc.v:139118$5801 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i - connect \B \io_bd [133] + connect \B \io_bd [131] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137484$5753_Y + connect \Y $ternary$libresoc.v:139118$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137486$5755 + cell $mux $ternary$libresoc.v:139119$5802 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o - connect \B \io_bd [134] + connect \B \io_bd [132] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137486$5755_Y + connect \Y $ternary$libresoc.v:139119$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137487$5756 + cell $mux $ternary$libresoc.v:139120$5803 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe - connect \B \io_bd [135] + connect \B \io_bd [133] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137487$5756_Y + connect \Y $ternary$libresoc.v:139120$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137488$5757 + cell $mux $ternary$libresoc.v:139122$5805 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i - connect \B \io_bd [136] + connect \B \io_bd [134] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137488$5757_Y + connect \Y $ternary$libresoc.v:139122$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137489$5758 + cell $mux $ternary$libresoc.v:139123$5806 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o - connect \B \io_bd [137] + connect \B \io_bd [135] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137489$5758_Y + connect \Y $ternary$libresoc.v:139123$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137490$5759 + cell $mux $ternary$libresoc.v:139124$5807 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe - connect \B \io_bd [138] + connect \B \io_bd [136] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137490$5759_Y + connect \Y $ternary$libresoc.v:139124$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137491$5760 + cell $mux $ternary$libresoc.v:139125$5808 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i - connect \B \io_bd [139] + connect \B \io_bd [137] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137491$5760_Y + connect \Y $ternary$libresoc.v:139125$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137492$5761 + cell $mux $ternary$libresoc.v:139126$5809 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o - connect \B \io_bd [140] + connect \B \io_bd [138] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137492$5761_Y + connect \Y $ternary$libresoc.v:139126$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137493$5762 + cell $mux $ternary$libresoc.v:139127$5810 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe - connect \B \io_bd [141] + connect \B \io_bd [139] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137493$5762_Y + connect \Y $ternary$libresoc.v:139127$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137494$5763 + cell $mux $ternary$libresoc.v:139128$5811 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i - connect \B \io_bd [142] + connect \B \io_bd [140] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137494$5763_Y + connect \Y $ternary$libresoc.v:139128$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137495$5764 + cell $mux $ternary$libresoc.v:139129$5812 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o - connect \B \io_bd [143] + connect \B \io_bd [141] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137495$5764_Y + connect \Y $ternary$libresoc.v:139129$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137497$5766 + cell $mux $ternary$libresoc.v:139130$5813 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe - connect \B \io_bd [144] + connect \B \io_bd [142] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137497$5766_Y + connect \Y $ternary$libresoc.v:139130$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137498$5767 + cell $mux $ternary$libresoc.v:139131$5814 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i - connect \B \io_bd [145] + connect \B \io_bd [143] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137498$5767_Y + connect \Y $ternary$libresoc.v:139131$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137499$5768 + cell $mux $ternary$libresoc.v:139133$5816 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o - connect \B \io_bd [146] + connect \B \io_bd [144] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137499$5768_Y + connect \Y $ternary$libresoc.v:139133$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137500$5769 + cell $mux $ternary$libresoc.v:139134$5817 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe - connect \B \io_bd [147] + connect \B \io_bd [145] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137500$5769_Y + connect \Y $ternary$libresoc.v:139134$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137501$5770 + cell $mux $ternary$libresoc.v:139135$5818 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i - connect \B \io_bd [148] + connect \B \io_bd [146] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137501$5770_Y + connect \Y $ternary$libresoc.v:139135$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137502$5771 + cell $mux $ternary$libresoc.v:139136$5819 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o - connect \B \io_bd [149] + connect \B \io_bd [147] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137502$5771_Y + connect \Y $ternary$libresoc.v:139136$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137503$5772 + cell $mux $ternary$libresoc.v:139137$5820 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe - connect \B \io_bd [150] + connect \B \io_bd [148] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137503$5772_Y + connect \Y $ternary$libresoc.v:139137$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137504$5773 + cell $mux $ternary$libresoc.v:139138$5821 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i - connect \B \io_bd [151] + connect \B \io_bd [149] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137504$5773_Y + connect \Y $ternary$libresoc.v:139138$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137505$5774 + cell $mux $ternary$libresoc.v:139139$5822 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o - connect \B \io_bd [152] + connect \B \io_bd [150] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137505$5774_Y + connect \Y $ternary$libresoc.v:139139$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137506$5775 + cell $mux $ternary$libresoc.v:139140$5823 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe - connect \B \io_bd [153] + connect \B \io_bd [151] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137506$5775_Y + connect \Y $ternary$libresoc.v:139140$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137593$5863 + cell $mux $ternary$libresoc.v:139227$5911 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137593$5863_Y + connect \Y $ternary$libresoc.v:139227$5911_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137594$5864 + cell $mux $ternary$libresoc.v:139228$5912 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137594$5864_Y + connect \Y $ternary$libresoc.v:139228$5912_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137595$5865 + cell $mux $ternary$libresoc.v:139229$5913 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137595$5865_Y + connect \Y $ternary$libresoc.v:139229$5913_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137596$5866 + cell $mux $ternary$libresoc.v:139230$5914 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137596$5866_Y + connect \Y $ternary$libresoc.v:139230$5914_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137598$5868 + cell $mux $ternary$libresoc.v:139232$5916 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137598$5868_Y + connect \Y $ternary$libresoc.v:139232$5916_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137599$5869 + cell $mux $ternary$libresoc.v:139233$5917 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137599$5869_Y + connect \Y $ternary$libresoc.v:139233$5917_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137600$5870 + cell $mux $ternary$libresoc.v:139234$5918 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137600$5870_Y + connect \Y $ternary$libresoc.v:139234$5918_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137601$5871 + cell $mux $ternary$libresoc.v:139235$5919 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137601$5871_Y + connect \Y $ternary$libresoc.v:139235$5919_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137602$5872 + cell $mux $ternary$libresoc.v:139236$5920 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137602$5872_Y + connect \Y $ternary$libresoc.v:139236$5920_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137603$5873 + cell $mux $ternary$libresoc.v:139237$5921 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137603$5873_Y + connect \Y $ternary$libresoc.v:139237$5921_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137604$5874 + cell $mux $ternary$libresoc.v:139238$5922 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137604$5874_Y + connect \Y $ternary$libresoc.v:139238$5922_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137605$5875 + cell $mux $ternary$libresoc.v:139239$5923 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137605$5875_Y + connect \Y $ternary$libresoc.v:139239$5923_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137606$5876 + cell $mux $ternary$libresoc.v:139240$5924 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137606$5876_Y + connect \Y $ternary$libresoc.v:139240$5924_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137607$5877 + cell $mux $ternary$libresoc.v:139241$5925 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137607$5877_Y + connect \Y $ternary$libresoc.v:139241$5925_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137609$5879 + cell $mux $ternary$libresoc.v:139243$5927 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137609$5879_Y + connect \Y $ternary$libresoc.v:139243$5927_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137610$5880 + cell $mux $ternary$libresoc.v:139244$5928 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137610$5880_Y + connect \Y $ternary$libresoc.v:139244$5928_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137611$5881 + cell $mux $ternary$libresoc.v:139245$5929 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137611$5881_Y + connect \Y $ternary$libresoc.v:139245$5929_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137612$5882 + cell $mux $ternary$libresoc.v:139246$5930 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137612$5882_Y + connect \Y $ternary$libresoc.v:139246$5930_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137613$5883 + cell $mux $ternary$libresoc.v:139247$5931 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137613$5883_Y + connect \Y $ternary$libresoc.v:139247$5931_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137614$5884 + cell $mux $ternary$libresoc.v:139248$5932 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137614$5884_Y + connect \Y $ternary$libresoc.v:139248$5932_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137615$5885 + cell $mux $ternary$libresoc.v:139249$5933 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137615$5885_Y + connect \Y $ternary$libresoc.v:139249$5933_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137616$5886 + cell $mux $ternary$libresoc.v:139250$5934 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137616$5886_Y + connect \Y $ternary$libresoc.v:139250$5934_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137617$5887 + cell $mux $ternary$libresoc.v:139251$5935 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137617$5887_Y + connect \Y $ternary$libresoc.v:139251$5935_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137618$5888 + cell $mux $ternary$libresoc.v:139252$5936 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137618$5888_Y + connect \Y $ternary$libresoc.v:139252$5936_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:137693.8-137705.4" + attribute \src "libresoc.v:139327.8-139339.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -219675,7 +222176,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:137706.12-137716.4" + attribute \src "libresoc.v:139340.12-139350.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -219688,7 +222189,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:137717.12-137727.4" + attribute \src "libresoc.v:139351.12-139361.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -219700,582 +222201,582 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:135928.7-135928.20" - process $proc$libresoc.v:135928$6084 + attribute \src "libresoc.v:137576.7-137576.20" + process $proc$libresoc.v:137576$6132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136486.13-136486.32" - process $proc$libresoc.v:136486$6085 + attribute \src "libresoc.v:138130.13-138130.32" + process $proc$libresoc.v:138130$6133 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:136491.14-136491.46" - process $proc$libresoc.v:136491$6086 + attribute \src "libresoc.v:138135.14-138135.46" + process $proc$libresoc.v:138135$6134 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:136505.7-136505.29" - process $proc$libresoc.v:136505$6087 + attribute \src "libresoc.v:138149.7-138149.29" + process $proc$libresoc.v:138149$6135 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:136513.13-136513.36" - process $proc$libresoc.v:136513$6088 + attribute \src "libresoc.v:138157.13-138157.36" + process $proc$libresoc.v:138157$6136 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:136521.7-136521.37" - process $proc$libresoc.v:136521$6089 + attribute \src "libresoc.v:138165.7-138165.37" + process $proc$libresoc.v:138165$6137 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:136525.7-136525.42" - process $proc$libresoc.v:136525$6090 + attribute \src "libresoc.v:138169.7-138169.42" + process $proc$libresoc.v:138169$6138 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:136529.14-136529.51" - process $proc$libresoc.v:136529$6091 + attribute \src "libresoc.v:138173.14-138173.51" + process $proc$libresoc.v:138173$6139 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:136535.13-136535.35" - process $proc$libresoc.v:136535$6092 + attribute \src "libresoc.v:138179.13-138179.35" + process $proc$libresoc.v:138179$6140 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:136543.14-136543.52" - process $proc$libresoc.v:136543$6093 + attribute \src "libresoc.v:138187.14-138187.52" + process $proc$libresoc.v:138187$6141 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:136551.7-136551.37" - process $proc$libresoc.v:136551$6094 + attribute \src "libresoc.v:138195.7-138195.37" + process $proc$libresoc.v:138195$6142 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:136555.7-136555.42" - process $proc$libresoc.v:136555$6095 + attribute \src "libresoc.v:138199.7-138199.42" + process $proc$libresoc.v:138199$6143 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:136571.13-136571.29" - process $proc$libresoc.v:136571$6096 + attribute \src "libresoc.v:138215.13-138215.29" + process $proc$libresoc.v:138215$6144 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:136573.13-136573.35" - process $proc$libresoc.v:136573$6097 + attribute \src "libresoc.v:138217.13-138217.35" + process $proc$libresoc.v:138217$6145 assign { } { } - assign $0\fsm_state$503[2:0]$6098 3'000 + assign $0\fsm_state$499[2:0]$6146 3'000 sync always sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$6098 + update \fsm_state$499 $0\fsm_state$499[2:0]$6146 end - attribute \src "libresoc.v:136771.15-136771.67" - process $proc$libresoc.v:136771$6099 + attribute \src "libresoc.v:138415.15-138415.66" + process $proc$libresoc.v:138415$6147 assign { } { } - assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_bd[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_bd $1\io_bd[153:0] + update \io_bd $1\io_bd[151:0] end - attribute \src "libresoc.v:136783.15-136783.67" - process $proc$libresoc.v:136783$6100 + attribute \src "libresoc.v:138427.15-138427.66" + process $proc$libresoc.v:138427$6148 assign { } { } - assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_sr[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[153:0] + update \io_sr $1\io_sr[151:0] end - attribute \src "libresoc.v:136792.14-136792.41" - process $proc$libresoc.v:136792$6101 + attribute \src "libresoc.v:138436.14-138436.41" + process $proc$libresoc.v:138436$6149 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:136801.14-136801.51" - process $proc$libresoc.v:136801$6102 + attribute \src "libresoc.v:138445.14-138445.51" + process $proc$libresoc.v:138445$6150 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:136815.7-136815.32" - process $proc$libresoc.v:136815$6103 + attribute \src "libresoc.v:138459.7-138459.32" + process $proc$libresoc.v:138459$6151 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:136823.14-136823.47" - process $proc$libresoc.v:136823$6104 + attribute \src "libresoc.v:138467.14-138467.47" + process $proc$libresoc.v:138467$6152 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:136831.7-136831.40" - process $proc$libresoc.v:136831$6105 + attribute \src "libresoc.v:138475.7-138475.40" + process $proc$libresoc.v:138475$6153 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:136835.7-136835.45" - process $proc$libresoc.v:136835$6106 + attribute \src "libresoc.v:138479.7-138479.45" + process $proc$libresoc.v:138479$6154 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:136839.14-136839.54" - process $proc$libresoc.v:136839$6107 + attribute \src "libresoc.v:138483.14-138483.54" + process $proc$libresoc.v:138483$6155 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:136845.13-136845.38" - process $proc$libresoc.v:136845$6108 + attribute \src "libresoc.v:138489.13-138489.38" + process $proc$libresoc.v:138489$6156 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:136853.14-136853.55" - process $proc$libresoc.v:136853$6109 + attribute \src "libresoc.v:138497.14-138497.55" + process $proc$libresoc.v:138497$6157 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:136861.7-136861.40" - process $proc$libresoc.v:136861$6110 + attribute \src "libresoc.v:138505.7-138505.40" + process $proc$libresoc.v:138505$6158 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:136865.7-136865.45" - process $proc$libresoc.v:136865$6111 + attribute \src "libresoc.v:138509.7-138509.45" + process $proc$libresoc.v:138509$6159 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137295.7-137295.21" - process $proc$libresoc.v:137295$6112 + attribute \src "libresoc.v:138931.7-138931.21" + process $proc$libresoc.v:138931$6160 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:137303.13-137303.27" - process $proc$libresoc.v:137303$6113 + attribute \src "libresoc.v:138939.13-138939.27" + process $proc$libresoc.v:138939$6161 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:137311.7-137311.29" - process $proc$libresoc.v:137311$6114 + attribute \src "libresoc.v:138947.7-138947.29" + process $proc$libresoc.v:138947$6162 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:137315.7-137315.34" - process $proc$libresoc.v:137315$6115 + attribute \src "libresoc.v:138951.7-138951.34" + process $proc$libresoc.v:138951$6163 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:137325.7-137325.21" - process $proc$libresoc.v:137325$6116 + attribute \src "libresoc.v:138961.7-138961.21" + process $proc$libresoc.v:138961$6164 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:137333.13-137333.27" - process $proc$libresoc.v:137333$6117 + attribute \src "libresoc.v:138969.13-138969.27" + process $proc$libresoc.v:138969$6165 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:137341.7-137341.29" - process $proc$libresoc.v:137341$6118 + attribute \src "libresoc.v:138977.7-138977.29" + process $proc$libresoc.v:138977$6166 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:137345.7-137345.34" - process $proc$libresoc.v:137345$6119 + attribute \src "libresoc.v:138981.7-138981.34" + process $proc$libresoc.v:138981$6167 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:137350.7-137350.26" - process $proc$libresoc.v:137350$6120 + attribute \src "libresoc.v:138986.7-138986.26" + process $proc$libresoc.v:138986$6168 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:137355.7-137355.26" - process $proc$libresoc.v:137355$6121 + attribute \src "libresoc.v:138991.7-138991.26" + process $proc$libresoc.v:138991$6169 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:137360.7-137360.24" - process $proc$libresoc.v:137360$6122 + attribute \src "libresoc.v:138996.7-138996.24" + process $proc$libresoc.v:138996$6170 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:137619.3-137620.41" - process $proc$libresoc.v:137619$5889 + attribute \src "libresoc.v:139253.3-139254.41" + process $proc$libresoc.v:139253$5937 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:137621.3-137622.41" - process $proc$libresoc.v:137621$5890 + attribute \src "libresoc.v:139255.3-139256.41" + process $proc$libresoc.v:139255$5938 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:137623.3-137624.37" - process $proc$libresoc.v:137623$5891 + attribute \src "libresoc.v:139257.3-139258.37" + process $proc$libresoc.v:139257$5939 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:137625.3-137626.45" - process $proc$libresoc.v:137625$5892 + attribute \src "libresoc.v:139259.3-139260.45" + process $proc$libresoc.v:139259$5940 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:137627.3-137628.35" - process $proc$libresoc.v:137627$5893 + attribute \src "libresoc.v:139261.3-139262.35" + process $proc$libresoc.v:139261$5941 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:137629.3-137630.45" - process $proc$libresoc.v:137629$5894 + attribute \src "libresoc.v:139263.3-139264.45" + process $proc$libresoc.v:139263$5942 assign { } { } - assign $0\fsm_state$503[2:0]$5895 \fsm_state$503$next + assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5895 + update \fsm_state$499 $0\fsm_state$499[2:0]$5943 end - attribute \src "libresoc.v:137631.3-137632.41" - process $proc$libresoc.v:137631$5896 + attribute \src "libresoc.v:139265.3-139266.41" + process $proc$libresoc.v:139265$5944 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:137633.3-137634.51" - process $proc$libresoc.v:137633$5897 + attribute \src "libresoc.v:139267.3-139268.51" + process $proc$libresoc.v:139267$5945 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:137635.3-137636.45" - process $proc$libresoc.v:137635$5898 + attribute \src "libresoc.v:139269.3-139270.45" + process $proc$libresoc.v:139269$5946 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:137637.3-137638.35" - process $proc$libresoc.v:137637$5899 + attribute \src "libresoc.v:139271.3-139272.35" + process $proc$libresoc.v:139271$5947 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:137639.3-137640.41" - process $proc$libresoc.v:137639$5900 + attribute \src "libresoc.v:139273.3-139274.41" + process $proc$libresoc.v:139273$5948 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:137641.3-137642.31" - process $proc$libresoc.v:137641$5901 + attribute \src "libresoc.v:139275.3-139276.31" + process $proc$libresoc.v:139275$5949 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:137643.3-137644.31" - process $proc$libresoc.v:137643$5902 + attribute \src "libresoc.v:139277.3-139278.31" + process $proc$libresoc.v:139277$5950 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:137645.3-137646.57" - process $proc$libresoc.v:137645$5903 + attribute \src "libresoc.v:139279.3-139280.57" + process $proc$libresoc.v:139279$5951 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:137647.3-137648.47" - process $proc$libresoc.v:137647$5904 + attribute \src "libresoc.v:139281.3-139282.47" + process $proc$libresoc.v:139281$5952 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:137649.3-137650.47" - process $proc$libresoc.v:137649$5905 + attribute \src "libresoc.v:139283.3-139284.47" + process $proc$libresoc.v:139283$5953 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:137651.3-137652.47" - process $proc$libresoc.v:137651$5906 + attribute \src "libresoc.v:139285.3-139286.47" + process $proc$libresoc.v:139285$5954 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:137653.3-137654.73" - process $proc$libresoc.v:137653$5907 + attribute \src "libresoc.v:139287.3-139288.73" + process $proc$libresoc.v:139287$5955 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137655.3-137656.63" - process $proc$libresoc.v:137655$5908 + attribute \src "libresoc.v:139289.3-139290.63" + process $proc$libresoc.v:139289$5956 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:137657.3-137658.47" - process $proc$libresoc.v:137657$5909 + attribute \src "libresoc.v:139291.3-139292.47" + process $proc$libresoc.v:139291$5957 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:137659.3-137660.47" - process $proc$libresoc.v:137659$5910 + attribute \src "libresoc.v:139293.3-139294.47" + process $proc$libresoc.v:139293$5958 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:137661.3-137662.73" - process $proc$libresoc.v:137661$5911 + attribute \src "libresoc.v:139295.3-139296.73" + process $proc$libresoc.v:139295$5959 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:137663.3-137664.63" - process $proc$libresoc.v:137663$5912 + attribute \src "libresoc.v:139297.3-139298.63" + process $proc$libresoc.v:139297$5960 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:137665.3-137666.53" - process $proc$libresoc.v:137665$5913 + attribute \src "libresoc.v:139299.3-139300.53" + process $proc$libresoc.v:139299$5961 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:137667.3-137668.53" - process $proc$libresoc.v:137667$5914 + attribute \src "libresoc.v:139301.3-139302.53" + process $proc$libresoc.v:139301$5962 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:137669.3-137670.79" - process $proc$libresoc.v:137669$5915 + attribute \src "libresoc.v:139303.3-139304.79" + process $proc$libresoc.v:139303$5963 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137671.3-137672.69" - process $proc$libresoc.v:137671$5916 + attribute \src "libresoc.v:139305.3-139306.69" + process $proc$libresoc.v:139305$5964 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:137673.3-137674.53" - process $proc$libresoc.v:137673$5917 + attribute \src "libresoc.v:139307.3-139308.53" + process $proc$libresoc.v:139307$5965 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:137675.3-137676.53" - process $proc$libresoc.v:137675$5918 + attribute \src "libresoc.v:139309.3-139310.53" + process $proc$libresoc.v:139309$5966 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:137677.3-137678.79" - process $proc$libresoc.v:137677$5919 + attribute \src "libresoc.v:139311.3-139312.79" + process $proc$libresoc.v:139311$5967 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:137679.3-137680.69" - process $proc$libresoc.v:137679$5920 + attribute \src "libresoc.v:139313.3-139314.69" + process $proc$libresoc.v:139313$5968 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:137681.3-137682.31" - process $proc$libresoc.v:137681$5921 + attribute \src "libresoc.v:139315.3-139316.31" + process $proc$libresoc.v:139315$5969 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:137683.3-137684.31" - process $proc$libresoc.v:137683$5922 + attribute \src "libresoc.v:139317.3-139318.31" + process $proc$libresoc.v:139317$5970 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:137685.3-137686.57" - process $proc$libresoc.v:137685$5923 + attribute \src "libresoc.v:139319.3-139320.57" + process $proc$libresoc.v:139319$5971 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:137687.3-137688.47" - process $proc$libresoc.v:137687$5924 + attribute \src "libresoc.v:139321.3-139322.47" + process $proc$libresoc.v:139321$5972 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:137689.3-137690.27" - process $proc$libresoc.v:137689$5925 + attribute \src "libresoc.v:139323.3-139324.27" + process $proc$libresoc.v:139323$5973 assign { } { } - assign $0\io_bd[153:0] \io_bd$next + assign $0\io_bd[151:0] \io_bd$next sync negedge \negjtag_clk - update \io_bd $0\io_bd[153:0] + update \io_bd $0\io_bd[151:0] end - attribute \src "libresoc.v:137691.3-137692.27" - process $proc$libresoc.v:137691$5926 + attribute \src "libresoc.v:139325.3-139326.27" + process $proc$libresoc.v:139325$5974 assign { } { } - assign $0\io_sr[153:0] \io_sr$next + assign $0\io_sr[151:0] \io_sr$next sync posedge \posjtag_clk - update \io_sr $0\io_sr[153:0] + update \io_sr $0\io_sr[151:0] end - attribute \src "libresoc.v:137728.3-137743.6" - process $proc$libresoc.v:137728$5927 + attribute \src "libresoc.v:139362.3-139377.6" + process $proc$libresoc.v:139362$5975 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:137729.5-137729.29" + attribute \src "libresoc.v:139363.5-139363.29" switch \initial - attribute \src "libresoc.v:137729.9-137729.17" + attribute \src "libresoc.v:139363.9-139363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$369 \_idblock_select_id \_fsm_isir } + switch { \$365 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } @@ -220287,21 +222788,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [153] + assign $1\TAP_tdo[0:0] \io_sr [151] case assign $1\TAP_tdo[0:0] 1'0 end sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:137744.3-137752.6" - process $proc$libresoc.v:137744$5928 + attribute \src "libresoc.v:139378.3-139386.6" + process $proc$libresoc.v:139378$5976 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5929 $1\sr0_update_core$next[0:0]$5930 - attribute \src "libresoc.v:137745.5-137745.29" + assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:139379.5-139379.29" switch \initial - attribute \src "libresoc.v:137745.9-137745.17" + attribute \src "libresoc.v:139379.9-139379.17" case 1'1 case end @@ -220310,21 +222811,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5930 1'0 + assign $1\sr0_update_core$next[0:0]$5978 1'0 case - assign $1\sr0_update_core$next[0:0]$5930 \sr0_update + assign $1\sr0_update_core$next[0:0]$5978 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5929 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 end - attribute \src "libresoc.v:137753.3-137761.6" - process $proc$libresoc.v:137753$5931 + attribute \src "libresoc.v:139387.3-139395.6" + process $proc$libresoc.v:139387$5979 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5932 $1\sr0_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:137754.5-137754.29" + assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:139388.5-139388.29" switch \initial - attribute \src "libresoc.v:137754.9-137754.17" + attribute \src "libresoc.v:139388.9-139388.17" case 1'1 case end @@ -220333,57 +222834,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5933 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5933 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5932 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 end - attribute \src "libresoc.v:137762.3-137778.6" - process $proc$libresoc.v:137762$5934 + attribute \src "libresoc.v:139396.3-139412.6" + process $proc$libresoc.v:139396$5982 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5935 $2\sr0__oe$next[0:0]$5937 - attribute \src "libresoc.v:137763.5-137763.29" + assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139397.5-139397.29" switch \initial - attribute \src "libresoc.v:137763.9-137763.17" + attribute \src "libresoc.v:139397.9-139397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$387 + switch \$383 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5936 \sr0_isir + assign $1\sr0__oe$next[0:0]$5984 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5936 1'0 + assign $1\sr0__oe$next[0:0]$5984 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5937 1'0 + assign $2\sr0__oe$next[0:0]$5985 1'0 case - assign $2\sr0__oe$next[0:0]$5937 $1\sr0__oe$next[0:0]$5936 + assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5935 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 end - attribute \src "libresoc.v:137779.3-137799.6" - process $proc$libresoc.v:137779$5938 + attribute \src "libresoc.v:139413.3-139433.6" + process $proc$libresoc.v:139413$5986 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5939 $3\sr0_reg$next[2:0]$5942 - attribute \src "libresoc.v:137780.5-137780.29" + assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139414.5-139414.29" switch \initial - attribute \src "libresoc.v:137780.9-137780.17" + attribute \src "libresoc.v:139414.9-139414.17" case 1'1 case end @@ -220392,39 +222893,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5940 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5940 \sr0_reg + assign $1\sr0_reg$next[2:0]$5988 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5941 \sr0__i + assign $2\sr0_reg$next[2:0]$5989 \sr0__i case - assign $2\sr0_reg$next[2:0]$5941 $1\sr0_reg$next[2:0]$5940 + assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5942 3'000 + assign $3\sr0_reg$next[2:0]$5990 3'000 case - assign $3\sr0_reg$next[2:0]$5942 $2\sr0_reg$next[2:0]$5941 + assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5939 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 end - attribute \src "libresoc.v:137800.3-137808.6" - process $proc$libresoc.v:137800$5943 + attribute \src "libresoc.v:139434.3-139442.6" + process $proc$libresoc.v:139434$5991 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5944 $1\jtag_wb_addrsr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:137801.5-137801.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:139435.5-139435.29" switch \initial - attribute \src "libresoc.v:137801.9-137801.17" + attribute \src "libresoc.v:139435.9-139435.17" case 1'1 case end @@ -220433,21 +222934,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5944 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 end - attribute \src "libresoc.v:137809.3-137817.6" - process $proc$libresoc.v:137809$5946 + attribute \src "libresoc.v:139443.3-139451.6" + process $proc$libresoc.v:139443$5994 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:137810.5-137810.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:139444.5-139444.29" switch \initial - attribute \src "libresoc.v:137810.9-137810.17" + attribute \src "libresoc.v:139444.9-139444.17" case 1'1 case end @@ -220456,57 +222957,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 end - attribute \src "libresoc.v:137818.3-137834.6" - process $proc$libresoc.v:137818$5949 + attribute \src "libresoc.v:139452.3-139468.6" + process $proc$libresoc.v:139452$5997 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5950 $2\jtag_wb_addrsr__oe$next[0:0]$5952 - attribute \src "libresoc.v:137819.5-137819.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139453.5-139453.29" switch \initial - attribute \src "libresoc.v:137819.9-137819.17" + attribute \src "libresoc.v:139453.9-139453.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$405 + switch \$401 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 $1\jtag_wb_addrsr__oe$next[0:0]$5951 + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5950 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 end - attribute \src "libresoc.v:137835.3-137855.6" - process $proc$libresoc.v:137835$5953 + attribute \src "libresoc.v:139469.3-139489.6" + process $proc$libresoc.v:139469$6001 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5954 $3\jtag_wb_addrsr_reg$next[28:0]$5957 - attribute \src "libresoc.v:137836.5-137836.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139470.5-139470.29" switch \initial - attribute \src "libresoc.v:137836.9-137836.17" + attribute \src "libresoc.v:139470.9-139470.17" case 1'1 case end @@ -220515,39 +223016,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 $1\jtag_wb_addrsr_reg$next[28:0]$5955 + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 $2\jtag_wb_addrsr_reg$next[28:0]$5956 + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5954 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 end - attribute \src "libresoc.v:137856.3-137864.6" - process $proc$libresoc.v:137856$5958 + attribute \src "libresoc.v:139490.3-139498.6" + process $proc$libresoc.v:139490$6006 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5959 $1\jtag_wb_datasr_update_core$next[0:0]$5960 - attribute \src "libresoc.v:137857.5-137857.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:139491.5-139491.29" switch \initial - attribute \src "libresoc.v:137857.9-137857.17" + attribute \src "libresoc.v:139491.9-139491.17" case 1'1 case end @@ -220556,21 +223057,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5959 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 end - attribute \src "libresoc.v:137865.3-137873.6" - process $proc$libresoc.v:137865$5961 + attribute \src "libresoc.v:139499.3-139507.6" + process $proc$libresoc.v:139499$6009 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:137866.5-137866.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:139500.5-139500.29" switch \initial - attribute \src "libresoc.v:137866.9-137866.17" + attribute \src "libresoc.v:139500.9-139500.17" case 1'1 case end @@ -220579,57 +223080,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 end - attribute \src "libresoc.v:137874.3-137890.6" - process $proc$libresoc.v:137874$5964 + attribute \src "libresoc.v:139508.3-139524.6" + process $proc$libresoc.v:139508$6012 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5965 $2\jtag_wb_datasr__oe$next[1:0]$5967 - attribute \src "libresoc.v:137875.5-137875.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139509.5-139509.29" switch \initial - attribute \src "libresoc.v:137875.9-137875.17" + attribute \src "libresoc.v:139509.9-139509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$425 + switch \$421 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5966 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5966 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5967 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$5967 $1\jtag_wb_datasr__oe$next[1:0]$5966 + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5965 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 end - attribute \src "libresoc.v:137891.3-137911.6" - process $proc$libresoc.v:137891$5968 + attribute \src "libresoc.v:139525.3-139545.6" + process $proc$libresoc.v:139525$6016 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5969 $3\jtag_wb_datasr_reg$next[63:0]$5972 - attribute \src "libresoc.v:137892.5-137892.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139526.5-139526.29" switch \initial - attribute \src "libresoc.v:137892.9-137892.17" + attribute \src "libresoc.v:139526.9-139526.17" case 1'1 case end @@ -220638,39 +223139,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5970 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$5970 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5971 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$5971 $1\jtag_wb_datasr_reg$next[63:0]$5970 + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$5972 $2\jtag_wb_datasr_reg$next[63:0]$5971 + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5969 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 end - attribute \src "libresoc.v:137912.3-137920.6" - process $proc$libresoc.v:137912$5973 + attribute \src "libresoc.v:139546.3-139554.6" + process $proc$libresoc.v:139546$6021 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5974 $1\dmi0_addrsr_update_core$next[0:0]$5975 - attribute \src "libresoc.v:137913.5-137913.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:139547.5-139547.29" switch \initial - attribute \src "libresoc.v:137913.9-137913.17" + attribute \src "libresoc.v:139547.9-139547.17" case 1'1 case end @@ -220679,21 +223180,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5975 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$5975 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5974 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 end - attribute \src "libresoc.v:137921.3-137929.6" - process $proc$libresoc.v:137921$5976 + attribute \src "libresoc.v:139555.3-139563.6" + process $proc$libresoc.v:139555$6024 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 - attribute \src "libresoc.v:137922.5-137922.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:139556.5-139556.29" switch \initial - attribute \src "libresoc.v:137922.9-137922.17" + attribute \src "libresoc.v:139556.9-139556.17" case 1'1 case end @@ -220702,57 +223203,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 end - attribute \src "libresoc.v:137930.3-137946.6" - process $proc$libresoc.v:137930$5979 + attribute \src "libresoc.v:139564.3-139580.6" + process $proc$libresoc.v:139564$6027 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5980 $2\dmi0_addrsr__oe$next[0:0]$5982 - attribute \src "libresoc.v:137931.5-137931.29" + assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139565.5-139565.29" switch \initial - attribute \src "libresoc.v:137931.9-137931.17" + attribute \src "libresoc.v:139565.9-139565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$443 + switch \$439 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5981 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5981 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5982 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$5982 $1\dmi0_addrsr__oe$next[0:0]$5981 + assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5980 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 end - attribute \src "libresoc.v:137947.3-137967.6" - process $proc$libresoc.v:137947$5983 + attribute \src "libresoc.v:139581.3-139601.6" + process $proc$libresoc.v:139581$6031 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5984 $3\dmi0_addrsr_reg$next[7:0]$5987 - attribute \src "libresoc.v:137948.5-137948.29" + assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139582.5-139582.29" switch \initial - attribute \src "libresoc.v:137948.9-137948.17" + attribute \src "libresoc.v:139582.9-139582.17" case 1'1 case end @@ -220761,39 +223262,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5985 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$5985 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5986 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$5986 $1\dmi0_addrsr_reg$next[7:0]$5985 + assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5987 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$5987 $2\dmi0_addrsr_reg$next[7:0]$5986 + assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5984 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 end - attribute \src "libresoc.v:137968.3-137976.6" - process $proc$libresoc.v:137968$5988 + attribute \src "libresoc.v:139602.3-139610.6" + process $proc$libresoc.v:139602$6036 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5989 $1\dmi0_datasr_update_core$next[0:0]$5990 - attribute \src "libresoc.v:137969.5-137969.29" + assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:139603.5-139603.29" switch \initial - attribute \src "libresoc.v:137969.9-137969.17" + attribute \src "libresoc.v:139603.9-139603.17" case 1'1 case end @@ -220802,21 +223303,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5990 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$5990 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5989 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 end - attribute \src "libresoc.v:137977.3-137985.6" - process $proc$libresoc.v:137977$5991 + attribute \src "libresoc.v:139611.3-139619.6" + process $proc$libresoc.v:139611$6039 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5992 $1\dmi0_datasr_update_core_prev$next[0:0]$5993 - attribute \src "libresoc.v:137978.5-137978.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:139612.5-139612.29" switch \initial - attribute \src "libresoc.v:137978.9-137978.17" + attribute \src "libresoc.v:139612.9-139612.17" case 1'1 case end @@ -220825,57 +223326,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5992 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 end - attribute \src "libresoc.v:137986.3-138002.6" - process $proc$libresoc.v:137986$5994 + attribute \src "libresoc.v:139620.3-139636.6" + process $proc$libresoc.v:139620$6042 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5995 $2\dmi0_datasr__oe$next[1:0]$5997 - attribute \src "libresoc.v:137987.5-137987.29" + assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139621.5-139621.29" switch \initial - attribute \src "libresoc.v:137987.9-137987.17" + attribute \src "libresoc.v:139621.9-139621.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$463 + switch \$459 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5996 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5996 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5997 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$5997 $1\dmi0_datasr__oe$next[1:0]$5996 + assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5995 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 end - attribute \src "libresoc.v:138003.3-138023.6" - process $proc$libresoc.v:138003$5998 + attribute \src "libresoc.v:139637.3-139657.6" + process $proc$libresoc.v:139637$6046 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5999 $3\dmi0_datasr_reg$next[63:0]$6002 - attribute \src "libresoc.v:138004.5-138004.29" + assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139638.5-139638.29" switch \initial - attribute \src "libresoc.v:138004.9-138004.17" + attribute \src "libresoc.v:139638.9-139638.17" case 1'1 case end @@ -220884,39 +223385,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$6000 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$6000 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$6001 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$6001 $1\dmi0_datasr_reg$next[63:0]$6000 + assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$6002 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$6002 $2\dmi0_datasr_reg$next[63:0]$6001 + assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5999 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 end - attribute \src "libresoc.v:138024.3-138032.6" - process $proc$libresoc.v:138024$6003 + attribute \src "libresoc.v:139658.3-139666.6" + process $proc$libresoc.v:139658$6051 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$6004 $1\sr5_update_core$next[0:0]$6005 - attribute \src "libresoc.v:138025.5-138025.29" + assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:139659.5-139659.29" switch \initial - attribute \src "libresoc.v:138025.9-138025.17" + attribute \src "libresoc.v:139659.9-139659.17" case 1'1 case end @@ -220925,21 +223426,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$6005 1'0 + assign $1\sr5_update_core$next[0:0]$6053 1'0 case - assign $1\sr5_update_core$next[0:0]$6005 \sr5_update + assign $1\sr5_update_core$next[0:0]$6053 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6004 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 end - attribute \src "libresoc.v:138033.3-138041.6" - process $proc$libresoc.v:138033$6006 + attribute \src "libresoc.v:139667.3-139675.6" + process $proc$libresoc.v:139667$6054 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$6007 $1\sr5_update_core_prev$next[0:0]$6008 - attribute \src "libresoc.v:138034.5-138034.29" + assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:139668.5-139668.29" switch \initial - attribute \src "libresoc.v:138034.9-138034.17" + attribute \src "libresoc.v:139668.9-139668.17" case 1'1 case end @@ -220948,57 +223449,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$6008 1'0 + assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$6008 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6007 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 end - attribute \src "libresoc.v:138042.3-138058.6" - process $proc$libresoc.v:138042$6009 + attribute \src "libresoc.v:139676.3-139692.6" + process $proc$libresoc.v:139676$6057 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$6010 $2\sr5__oe$next[0:0]$6012 - attribute \src "libresoc.v:138043.5-138043.29" + assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139677.5-139677.29" switch \initial - attribute \src "libresoc.v:138043.9-138043.17" + attribute \src "libresoc.v:139677.9-139677.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$481 + switch \$477 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$6011 \sr5_isir + assign $1\sr5__oe$next[0:0]$6059 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$6011 1'0 + assign $1\sr5__oe$next[0:0]$6059 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$6012 1'0 + assign $2\sr5__oe$next[0:0]$6060 1'0 case - assign $2\sr5__oe$next[0:0]$6012 $1\sr5__oe$next[0:0]$6011 + assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$6010 + update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 end - attribute \src "libresoc.v:138059.3-138079.6" - process $proc$libresoc.v:138059$6013 + attribute \src "libresoc.v:139693.3-139713.6" + process $proc$libresoc.v:139693$6061 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[2:0]$6014 $3\sr5_reg$next[2:0]$6017 - attribute \src "libresoc.v:138060.5-138060.29" + assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139694.5-139694.29" switch \initial - attribute \src "libresoc.v:138060.9-138060.17" + attribute \src "libresoc.v:139694.9-139694.17" case 1'1 case end @@ -221007,38 +223508,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[2:0]$6015 { \TAP_bus__tdi \sr5_reg [2:1] } + assign $1\sr5_reg$next[2:0]$6063 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[2:0]$6015 \sr5_reg + assign $1\sr5_reg$next[2:0]$6063 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[2:0]$6016 \sr5__i + assign $2\sr5_reg$next[2:0]$6064 \sr5__i case - assign $2\sr5_reg$next[2:0]$6016 $1\sr5_reg$next[2:0]$6015 + assign $2\sr5_reg$next[2:0]$6064 $1\sr5_reg$next[2:0]$6063 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[2:0]$6017 3'000 + assign $3\sr5_reg$next[2:0]$6065 3'000 case - assign $3\sr5_reg$next[2:0]$6017 $2\sr5_reg$next[2:0]$6016 + assign $3\sr5_reg$next[2:0]$6065 $2\sr5_reg$next[2:0]$6064 end sync always - update \sr5_reg$next $0\sr5_reg$next[2:0]$6014 + update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 end - attribute \src "libresoc.v:138080.3-138106.6" - process $proc$libresoc.v:138080$6018 + attribute \src "libresoc.v:139714.3-139740.6" + process $proc$libresoc.v:139714$6066 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:138081.5-138081.29" + attribute \src "libresoc.v:139715.5-139715.29" switch \initial - attribute \src "libresoc.v:138081.9-138081.17" + attribute \src "libresoc.v:139715.9-139715.17" case 1'1 case end @@ -221076,15 +223577,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:138107.3-138139.6" - process $proc$libresoc.v:138107$6019 + attribute \src "libresoc.v:139741.3-139773.6" + process $proc$libresoc.v:139741$6067 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$6020 $4\jtag_wb__adr$next[28:0]$6024 - attribute \src "libresoc.v:138108.5-138108.29" + assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139742.5-139742.29" switch \initial - attribute \src "libresoc.v:138108.9-138108.17" + attribute \src "libresoc.v:139742.9-139742.17" case 1'1 case end @@ -221093,57 +223594,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6021 $2\jtag_wb__adr$next[28:0]$6022 + assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6022 \$495 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6070 \$491 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6021 $3\jtag_wb__adr$next[28:0]$6023 + assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$6023 \$498 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6071 \$494 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$6023 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$6021 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$6024 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$6024 $1\jtag_wb__adr$next[28:0]$6021 + assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6020 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 end - attribute \src "libresoc.v:138140.3-138192.6" - process $proc$libresoc.v:138140$6025 + attribute \src "libresoc.v:139774.3-139826.6" + process $proc$libresoc.v:139774$6073 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$6026 $5\fsm_state$next[2:0]$6031 - attribute \src "libresoc.v:138141.5-138141.29" + assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139775.5-139775.29" switch \initial - attribute \src "libresoc.v:138141.9-138141.17" + attribute \src "libresoc.v:139775.9-139775.17" case 1'1 case end @@ -221152,82 +223653,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $2\fsm_state$next[2:0]$6028 + assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'001 + assign $2\fsm_state$next[2:0]$6076 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'001 + assign $2\fsm_state$next[2:0]$6076 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'010 + assign $2\fsm_state$next[2:0]$6076 3'010 case - assign $2\fsm_state$next[2:0]$6028 \fsm_state + assign $2\fsm_state$next[2:0]$6076 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$6027 3'011 + assign $1\fsm_state$next[2:0]$6075 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $3\fsm_state$next[2:0]$6029 + assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$6029 3'000 + assign $3\fsm_state$next[2:0]$6077 3'000 case - assign $3\fsm_state$next[2:0]$6029 \fsm_state + assign $3\fsm_state$next[2:0]$6077 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$6027 3'100 + assign $1\fsm_state$next[2:0]$6075 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $4\fsm_state$next[2:0]$6030 + assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$6030 3'001 + assign $4\fsm_state$next[2:0]$6078 3'001 case - assign $4\fsm_state$next[2:0]$6030 \fsm_state + assign $4\fsm_state$next[2:0]$6078 \fsm_state end case - assign $1\fsm_state$next[2:0]$6027 \fsm_state + assign $1\fsm_state$next[2:0]$6075 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$6031 3'000 + assign $5\fsm_state$next[2:0]$6079 3'000 case - assign $5\fsm_state$next[2:0]$6031 $1\fsm_state$next[2:0]$6027 + assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$6026 + update \fsm_state$next $0\fsm_state$next[2:0]$6074 end - attribute \src "libresoc.v:138193.3-138219.6" - process $proc$libresoc.v:138193$6032 + attribute \src "libresoc.v:139827.3-139853.6" + process $proc$libresoc.v:139827$6080 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$6033 $3\jtag_wb__dat_w$next[63:0]$6036 - attribute \src "libresoc.v:138194.5-138194.29" + assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139828.5-139828.29" switch \initial - attribute \src "libresoc.v:138194.9-138194.17" + attribute \src "libresoc.v:139828.9-139828.17" case 1'1 case end @@ -221236,46 +223737,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$6034 $2\jtag_wb__dat_w$next[63:0]$6035 + assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$6034 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$6036 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$6036 $1\jtag_wb__dat_w$next[63:0]$6034 + assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6033 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 end - attribute \src "libresoc.v:138220.3-138240.6" - process $proc$libresoc.v:138220$6037 + attribute \src "libresoc.v:139854.3-139874.6" + process $proc$libresoc.v:139854$6085 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$6038 $3\jtag_wb_datasr__i$next[63:0]$6041 - attribute \src "libresoc.v:138221.5-138221.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139855.5-139855.29" switch \initial - attribute \src "libresoc.v:138221.9-138221.17" + attribute \src "libresoc.v:139855.9-139855.17" case 1'1 case end @@ -221284,266 +223785,266 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$6039 $2\jtag_wb_datasr__i$next[63:0]$6040 + assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$6039 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$6041 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$6041 $1\jtag_wb_datasr__i$next[63:0]$6039 + assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6038 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 end - attribute \src "libresoc.v:138241.3-138273.6" - process $proc$libresoc.v:138241$6042 + attribute \src "libresoc.v:139875.3-139907.6" + process $proc$libresoc.v:139875$6090 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$6043 $4\dmi0__addr_i$next[3:0]$6047 - attribute \src "libresoc.v:138242.5-138242.29" + assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139876.5-139876.29" switch \initial - attribute \src "libresoc.v:138242.9-138242.17" + attribute \src "libresoc.v:139876.9-139876.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6044 $2\dmi0__addr_i$next[3:0]$6045 + assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6045 \$512 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6093 \$508 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6044 $3\dmi0__addr_i$next[3:0]$6046 + assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6046 \$515 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6094 \$511 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$6046 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$6044 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6047 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$6047 $1\dmi0__addr_i$next[3:0]$6044 + assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6043 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 end - attribute \src "libresoc.v:138274.3-138326.6" - process $proc$libresoc.v:138274$6048 + attribute \src "libresoc.v:139908.3-139960.6" + process $proc$libresoc.v:139908$6096 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$6049 $5\fsm_state$503$next[2:0]$6054 - attribute \src "libresoc.v:138275.5-138275.29" + assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139909.5-139909.29" switch \initial - attribute \src "libresoc.v:138275.9-138275.17" + attribute \src "libresoc.v:139909.9-139909.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $2\fsm_state$503$next[2:0]$6051 + assign $1\fsm_state$499$next[2:0]$6098 $2\fsm_state$499$next[2:0]$6099 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'001 + assign $2\fsm_state$499$next[2:0]$6099 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'001 + assign $2\fsm_state$499$next[2:0]$6099 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'010 + assign $2\fsm_state$499$next[2:0]$6099 3'010 case - assign $2\fsm_state$503$next[2:0]$6051 \fsm_state$503 + assign $2\fsm_state$499$next[2:0]$6099 \fsm_state$499 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 3'011 + assign $1\fsm_state$499$next[2:0]$6098 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $3\fsm_state$503$next[2:0]$6052 + assign $1\fsm_state$499$next[2:0]$6098 $3\fsm_state$499$next[2:0]$6100 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$503$next[2:0]$6052 3'000 + assign $3\fsm_state$499$next[2:0]$6100 3'000 case - assign $3\fsm_state$503$next[2:0]$6052 \fsm_state$503 + assign $3\fsm_state$499$next[2:0]$6100 \fsm_state$499 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 3'100 + assign $1\fsm_state$499$next[2:0]$6098 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $4\fsm_state$503$next[2:0]$6053 + assign $1\fsm_state$499$next[2:0]$6098 $4\fsm_state$499$next[2:0]$6101 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$503$next[2:0]$6053 3'001 + assign $4\fsm_state$499$next[2:0]$6101 3'001 case - assign $4\fsm_state$503$next[2:0]$6053 \fsm_state$503 + assign $4\fsm_state$499$next[2:0]$6101 \fsm_state$499 end case - assign $1\fsm_state$503$next[2:0]$6050 \fsm_state$503 + assign $1\fsm_state$499$next[2:0]$6098 \fsm_state$499 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$6054 3'000 + assign $5\fsm_state$499$next[2:0]$6102 3'000 case - assign $5\fsm_state$503$next[2:0]$6054 $1\fsm_state$503$next[2:0]$6050 + assign $5\fsm_state$499$next[2:0]$6102 $1\fsm_state$499$next[2:0]$6098 end sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6049 + update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 end - attribute \src "libresoc.v:138327.3-138353.6" - process $proc$libresoc.v:138327$6055 + attribute \src "libresoc.v:139961.3-139987.6" + process $proc$libresoc.v:139961$6103 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6056 $3\dmi0__din$next[63:0]$6059 - attribute \src "libresoc.v:138328.5-138328.29" + assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139962.5-139962.29" switch \initial - attribute \src "libresoc.v:138328.9-138328.17" + attribute \src "libresoc.v:139962.9-139962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$6057 $2\dmi0__din$next[63:0]$6058 + assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$6058 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$6057 \dmi0__din + assign $1\dmi0__din$next[63:0]$6105 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6059 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6059 $1\dmi0__din$next[63:0]$6057 + assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6056 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 end - attribute \src "libresoc.v:138354.3-138374.6" - process $proc$libresoc.v:138354$6060 + attribute \src "libresoc.v:139988.3-140008.6" + process $proc$libresoc.v:139988$6108 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6061 $3\dmi0_datasr__i$next[63:0]$6064 - attribute \src "libresoc.v:138355.5-138355.29" + assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139989.5-139989.29" switch \initial - attribute \src "libresoc.v:138355.9-138355.17" + attribute \src "libresoc.v:139989.9-139989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6062 $2\dmi0_datasr__i$next[63:0]$6063 + assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$6062 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6064 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$6064 $1\dmi0_datasr__i$next[63:0]$6062 + assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6061 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 end - attribute \src "libresoc.v:138375.3-138395.6" - process $proc$libresoc.v:138375$6065 + attribute \src "libresoc.v:140009.3-140029.6" + process $proc$libresoc.v:140009$6113 assign { } { } assign { } { } assign { } { } @@ -221553,12 +224054,12 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$6066 $2\wb_dcache_en$next[0:0]$6072 - assign $0\wb_icache_en$next[0:0]$6067 $2\wb_icache_en$next[0:0]$6073 - assign $0\wb_sram_en$next[0:0]$6068 $2\wb_sram_en$next[0:0]$6074 - attribute \src "libresoc.v:138376.5-138376.29" + assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 + assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 + assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:140010.5-140010.29" switch \initial - attribute \src "libresoc.v:138376.9-138376.17" + attribute \src "libresoc.v:140010.9-140010.17" case 1'1 case end @@ -221569,11 +224070,11 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign { $1\wb_sram_en$next[0:0]$6071 $1\wb_dcache_en$next[0:0]$6069 $1\wb_icache_en$next[0:0]$6070 } \sr5__o + assign { $1\wb_sram_en$next[0:0]$6119 $1\wb_dcache_en$next[0:0]$6117 $1\wb_icache_en$next[0:0]$6118 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$6069 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6070 \wb_icache_en - assign $1\wb_sram_en$next[0:0]$6071 \wb_sram_en + assign $1\wb_dcache_en$next[0:0]$6117 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6118 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6119 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -221582,27 +224083,27 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$6073 1'1 - assign $2\wb_dcache_en$next[0:0]$6072 1'1 - assign $2\wb_sram_en$next[0:0]$6074 1'1 + assign $2\wb_icache_en$next[0:0]$6121 1'1 + assign $2\wb_dcache_en$next[0:0]$6120 1'1 + assign $2\wb_sram_en$next[0:0]$6122 1'1 case - assign $2\wb_dcache_en$next[0:0]$6072 $1\wb_dcache_en$next[0:0]$6069 - assign $2\wb_icache_en$next[0:0]$6073 $1\wb_icache_en$next[0:0]$6070 - assign $2\wb_sram_en$next[0:0]$6074 $1\wb_sram_en$next[0:0]$6071 + assign $2\wb_dcache_en$next[0:0]$6120 $1\wb_dcache_en$next[0:0]$6117 + assign $2\wb_icache_en$next[0:0]$6121 $1\wb_icache_en$next[0:0]$6118 + assign $2\wb_sram_en$next[0:0]$6122 $1\wb_sram_en$next[0:0]$6119 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6066 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6067 - update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6068 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 end - attribute \src "libresoc.v:138396.3-138405.6" - process $proc$libresoc.v:138396$6075 + attribute \src "libresoc.v:140030.3-140039.6" + process $proc$libresoc.v:140030$6123 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:138397.5-138397.29" + attribute \src "libresoc.v:140031.5-140031.29" switch \initial - attribute \src "libresoc.v:138397.9-138397.17" + attribute \src "libresoc.v:140031.9-140031.17" case 1'1 case end @@ -221618,15 +224119,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:138406.3-138423.6" - process $proc$libresoc.v:138406$6076 + attribute \src "libresoc.v:140040.3-140057.6" + process $proc$libresoc.v:140040$6124 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[153:0]$6077 $2\io_sr$next[153:0]$6079 - attribute \src "libresoc.v:138407.5-138407.29" + assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:140041.5-140041.29" switch \initial - attribute \src "libresoc.v:138407.9-138407.17" + attribute \src "libresoc.v:140041.9-140041.17" case 1'1 case end @@ -221635,35 +224136,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[153:0]$6078 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[151:0]$6126 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[153:0]$6078 { \io_sr [152:0] \TAP_bus__tdi } + assign $1\io_sr$next[151:0]$6126 { \io_sr [150:0] \TAP_bus__tdi } case - assign $1\io_sr$next[153:0]$6078 \io_sr + assign $1\io_sr$next[151:0]$6126 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$6079 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[151:0]$6127 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[153:0]$6079 $1\io_sr$next[153:0]$6078 + assign $2\io_sr$next[151:0]$6127 $1\io_sr$next[151:0]$6126 end sync always - update \io_sr$next $0\io_sr$next[153:0]$6077 + update \io_sr$next $0\io_sr$next[151:0]$6125 end - attribute \src "libresoc.v:138424.3-138444.6" - process $proc$libresoc.v:138424$6080 + attribute \src "libresoc.v:140058.3-140078.6" + process $proc$libresoc.v:140058$6128 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[153:0]$6081 $2\io_bd$next[153:0]$6083 - attribute \src "libresoc.v:138425.5-138425.29" + assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140059.5-140059.29" switch \initial - attribute \src "libresoc.v:138425.9-138425.17" + attribute \src "libresoc.v:140059.9-140059.17" case 1'1 case end @@ -221671,356 +224172,352 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[153:0]$6082 \io_sr + assign $1\io_bd$next[151:0]$6130 \io_sr case - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[153:0]$6083 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$6083 $1\io_bd$next[153:0]$6082 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$6081 - end - connect \$9 $eq$libresoc.v:137363$5632_Y - connect \$99 $ternary$libresoc.v:137364$5633_Y - connect \$101 $ternary$libresoc.v:137365$5634_Y - connect \$103 $ternary$libresoc.v:137366$5635_Y - connect \$105 $ternary$libresoc.v:137367$5636_Y - connect \$107 $ternary$libresoc.v:137368$5637_Y - connect \$109 $ternary$libresoc.v:137369$5638_Y - connect \$111 $ternary$libresoc.v:137370$5639_Y - connect \$113 $ternary$libresoc.v:137371$5640_Y - connect \$115 $ternary$libresoc.v:137372$5641_Y - connect \$117 $ternary$libresoc.v:137373$5642_Y - connect \$11 $eq$libresoc.v:137374$5643_Y - connect \$119 $ternary$libresoc.v:137375$5644_Y - connect \$121 $ternary$libresoc.v:137376$5645_Y - connect \$123 $ternary$libresoc.v:137377$5646_Y - connect \$125 $ternary$libresoc.v:137378$5647_Y - connect \$127 $ternary$libresoc.v:137379$5648_Y - connect \$129 $ternary$libresoc.v:137380$5649_Y - connect \$131 $ternary$libresoc.v:137381$5650_Y - connect \$133 $ternary$libresoc.v:137382$5651_Y - connect \$135 $ternary$libresoc.v:137383$5652_Y - connect \$137 $ternary$libresoc.v:137384$5653_Y - connect \$13 $eq$libresoc.v:137385$5654_Y - connect \$139 $ternary$libresoc.v:137386$5655_Y - connect \$141 $ternary$libresoc.v:137387$5656_Y - connect \$143 $ternary$libresoc.v:137388$5657_Y - connect \$145 $ternary$libresoc.v:137389$5658_Y - connect \$147 $ternary$libresoc.v:137390$5659_Y - connect \$149 $ternary$libresoc.v:137391$5660_Y - connect \$151 $ternary$libresoc.v:137392$5661_Y - connect \$153 $ternary$libresoc.v:137393$5662_Y - connect \$155 $ternary$libresoc.v:137394$5663_Y - connect \$157 $ternary$libresoc.v:137395$5664_Y - connect \$15 $or$libresoc.v:137396$5665_Y - connect \$159 $ternary$libresoc.v:137397$5666_Y - connect \$161 $ternary$libresoc.v:137398$5667_Y - connect \$163 $ternary$libresoc.v:137399$5668_Y - connect \$165 $ternary$libresoc.v:137400$5669_Y - connect \$167 $ternary$libresoc.v:137401$5670_Y - connect \$169 $ternary$libresoc.v:137402$5671_Y - connect \$171 $ternary$libresoc.v:137403$5672_Y - connect \$173 $ternary$libresoc.v:137404$5673_Y - connect \$175 $ternary$libresoc.v:137405$5674_Y - connect \$177 $ternary$libresoc.v:137406$5675_Y - connect \$17 $and$libresoc.v:137407$5676_Y - connect \$179 $ternary$libresoc.v:137408$5677_Y - connect \$181 $ternary$libresoc.v:137409$5678_Y - connect \$183 $ternary$libresoc.v:137410$5679_Y - connect \$185 $ternary$libresoc.v:137411$5680_Y - connect \$187 $ternary$libresoc.v:137412$5681_Y - connect \$189 $ternary$libresoc.v:137413$5682_Y - connect \$191 $ternary$libresoc.v:137414$5683_Y - connect \$193 $ternary$libresoc.v:137415$5684_Y - connect \$195 $ternary$libresoc.v:137416$5685_Y - connect \$197 $ternary$libresoc.v:137417$5686_Y - connect \$1 $eq$libresoc.v:137418$5687_Y - connect \$19 $eq$libresoc.v:137419$5688_Y - connect \$199 $ternary$libresoc.v:137420$5689_Y - connect \$201 $ternary$libresoc.v:137421$5690_Y - connect \$203 $ternary$libresoc.v:137422$5691_Y - connect \$205 $ternary$libresoc.v:137423$5692_Y - connect \$207 $ternary$libresoc.v:137424$5693_Y - connect \$209 $ternary$libresoc.v:137425$5694_Y - connect \$211 $ternary$libresoc.v:137426$5695_Y - connect \$213 $ternary$libresoc.v:137427$5696_Y - connect \$215 $ternary$libresoc.v:137428$5697_Y - connect \$217 $ternary$libresoc.v:137429$5698_Y - connect \$21 $eq$libresoc.v:137430$5699_Y - connect \$219 $ternary$libresoc.v:137431$5700_Y - connect \$221 $ternary$libresoc.v:137432$5701_Y - connect \$223 $ternary$libresoc.v:137433$5702_Y - connect \$225 $ternary$libresoc.v:137434$5703_Y - connect \$227 $ternary$libresoc.v:137435$5704_Y - connect \$229 $ternary$libresoc.v:137436$5705_Y - connect \$231 $ternary$libresoc.v:137437$5706_Y - connect \$233 $ternary$libresoc.v:137438$5707_Y - connect \$235 $ternary$libresoc.v:137439$5708_Y - connect \$237 $ternary$libresoc.v:137440$5709_Y - connect \$23 $or$libresoc.v:137441$5710_Y - connect \$239 $ternary$libresoc.v:137442$5711_Y - connect \$241 $ternary$libresoc.v:137443$5712_Y - connect \$243 $ternary$libresoc.v:137444$5713_Y - connect \$245 $ternary$libresoc.v:137445$5714_Y - connect \$247 $ternary$libresoc.v:137446$5715_Y - connect \$249 $ternary$libresoc.v:137447$5716_Y - connect \$251 $ternary$libresoc.v:137448$5717_Y - connect \$253 $ternary$libresoc.v:137449$5718_Y - connect \$255 $ternary$libresoc.v:137450$5719_Y - connect \$257 $ternary$libresoc.v:137451$5720_Y - connect \$25 $eq$libresoc.v:137452$5721_Y - connect \$259 $ternary$libresoc.v:137453$5722_Y - connect \$261 $ternary$libresoc.v:137454$5723_Y - connect \$263 $ternary$libresoc.v:137455$5724_Y - connect \$265 $ternary$libresoc.v:137456$5725_Y - connect \$267 $ternary$libresoc.v:137457$5726_Y - connect \$269 $ternary$libresoc.v:137458$5727_Y - connect \$271 $ternary$libresoc.v:137459$5728_Y - connect \$273 $ternary$libresoc.v:137460$5729_Y - connect \$275 $ternary$libresoc.v:137461$5730_Y - connect \$277 $ternary$libresoc.v:137462$5731_Y - connect \$27 $or$libresoc.v:137463$5732_Y - connect \$279 $ternary$libresoc.v:137464$5733_Y - connect \$281 $ternary$libresoc.v:137465$5734_Y - connect \$283 $ternary$libresoc.v:137466$5735_Y - connect \$285 $ternary$libresoc.v:137467$5736_Y - connect \$287 $ternary$libresoc.v:137468$5737_Y - connect \$289 $ternary$libresoc.v:137469$5738_Y - connect \$291 $ternary$libresoc.v:137470$5739_Y - connect \$293 $ternary$libresoc.v:137471$5740_Y - connect \$295 $ternary$libresoc.v:137472$5741_Y - connect \$297 $ternary$libresoc.v:137473$5742_Y - connect \$29 $and$libresoc.v:137474$5743_Y - connect \$299 $ternary$libresoc.v:137475$5744_Y - connect \$301 $ternary$libresoc.v:137476$5745_Y - connect \$303 $ternary$libresoc.v:137477$5746_Y - connect \$305 $ternary$libresoc.v:137478$5747_Y - connect \$307 $ternary$libresoc.v:137479$5748_Y - connect \$309 $ternary$libresoc.v:137480$5749_Y - connect \$311 $ternary$libresoc.v:137481$5750_Y - connect \$313 $ternary$libresoc.v:137482$5751_Y - connect \$315 $ternary$libresoc.v:137483$5752_Y - connect \$317 $ternary$libresoc.v:137484$5753_Y - connect \$31 $and$libresoc.v:137485$5754_Y - connect \$319 $ternary$libresoc.v:137486$5755_Y - connect \$321 $ternary$libresoc.v:137487$5756_Y - connect \$323 $ternary$libresoc.v:137488$5757_Y - connect \$325 $ternary$libresoc.v:137489$5758_Y - connect \$327 $ternary$libresoc.v:137490$5759_Y - connect \$329 $ternary$libresoc.v:137491$5760_Y - connect \$331 $ternary$libresoc.v:137492$5761_Y - connect \$333 $ternary$libresoc.v:137493$5762_Y - connect \$335 $ternary$libresoc.v:137494$5763_Y - connect \$337 $ternary$libresoc.v:137495$5764_Y - connect \$33 $eq$libresoc.v:137496$5765_Y - connect \$339 $ternary$libresoc.v:137497$5766_Y - connect \$341 $ternary$libresoc.v:137498$5767_Y - connect \$343 $ternary$libresoc.v:137499$5768_Y - connect \$345 $ternary$libresoc.v:137500$5769_Y - connect \$347 $ternary$libresoc.v:137501$5770_Y - connect \$349 $ternary$libresoc.v:137502$5771_Y - connect \$351 $ternary$libresoc.v:137503$5772_Y - connect \$353 $ternary$libresoc.v:137504$5773_Y - connect \$355 $ternary$libresoc.v:137505$5774_Y - connect \$357 $ternary$libresoc.v:137506$5775_Y - connect \$35 $eq$libresoc.v:137507$5776_Y - connect \$359 $eq$libresoc.v:137508$5777_Y - connect \$361 $eq$libresoc.v:137509$5778_Y - connect \$363 $or$libresoc.v:137510$5779_Y - connect \$365 $eq$libresoc.v:137511$5780_Y - connect \$367 $or$libresoc.v:137512$5781_Y - connect \$369 $and$libresoc.v:137513$5782_Y - connect \$371 $eq$libresoc.v:137514$5783_Y - connect \$373 $ne$libresoc.v:137515$5784_Y - connect \$375 $and$libresoc.v:137516$5785_Y - connect \$377 $ne$libresoc.v:137517$5786_Y - connect \$37 $or$libresoc.v:137518$5787_Y - connect \$379 $and$libresoc.v:137519$5788_Y - connect \$381 $ne$libresoc.v:137520$5789_Y - connect \$383 $and$libresoc.v:137521$5790_Y - connect \$385 $not$libresoc.v:137522$5791_Y - connect \$387 $and$libresoc.v:137523$5792_Y - connect \$389 $eq$libresoc.v:137524$5793_Y - connect \$391 $ne$libresoc.v:137525$5794_Y - connect \$393 $and$libresoc.v:137526$5795_Y - connect \$395 $ne$libresoc.v:137527$5796_Y - connect \$397 $and$libresoc.v:137528$5797_Y - connect \$3 $eq$libresoc.v:137529$5798_Y - connect \$39 $eq$libresoc.v:137530$5799_Y - connect \$399 $ne$libresoc.v:137531$5800_Y - connect \$401 $and$libresoc.v:137532$5801_Y - connect \$403 $not$libresoc.v:137533$5802_Y - connect \$405 $and$libresoc.v:137534$5803_Y - connect \$407 $eq$libresoc.v:137535$5804_Y - connect \$409 $eq$libresoc.v:137536$5805_Y - connect \$411 $ne$libresoc.v:137537$5806_Y - connect \$413 $and$libresoc.v:137538$5807_Y - connect \$415 $ne$libresoc.v:137539$5808_Y - connect \$417 $and$libresoc.v:137540$5809_Y - connect \$41 $or$libresoc.v:137541$5810_Y - connect \$419 $ne$libresoc.v:137542$5811_Y - connect \$421 $and$libresoc.v:137543$5812_Y - connect \$423 $not$libresoc.v:137544$5813_Y - connect \$425 $and$libresoc.v:137545$5814_Y - connect \$427 $eq$libresoc.v:137546$5815_Y - connect \$429 $ne$libresoc.v:137547$5816_Y - connect \$431 $and$libresoc.v:137548$5817_Y - connect \$433 $ne$libresoc.v:137549$5818_Y - connect \$435 $and$libresoc.v:137550$5819_Y - connect \$437 $ne$libresoc.v:137551$5820_Y - connect \$43 $and$libresoc.v:137552$5821_Y - connect \$439 $and$libresoc.v:137553$5822_Y - connect \$441 $not$libresoc.v:137554$5823_Y - connect \$443 $and$libresoc.v:137555$5824_Y - connect \$445 $eq$libresoc.v:137556$5825_Y - connect \$447 $eq$libresoc.v:137557$5826_Y - connect \$449 $ne$libresoc.v:137558$5827_Y - connect \$451 $and$libresoc.v:137559$5828_Y - connect \$453 $ne$libresoc.v:137560$5829_Y - connect \$455 $and$libresoc.v:137561$5830_Y - connect \$457 $ne$libresoc.v:137562$5831_Y - connect \$45 $and$libresoc.v:137563$5832_Y - connect \$459 $and$libresoc.v:137564$5833_Y - connect \$461 $not$libresoc.v:137565$5834_Y - connect \$463 $and$libresoc.v:137566$5835_Y - connect \$465 $eq$libresoc.v:137567$5836_Y - connect \$467 $ne$libresoc.v:137568$5837_Y - connect \$469 $and$libresoc.v:137569$5838_Y - connect \$471 $ne$libresoc.v:137570$5839_Y - connect \$473 $and$libresoc.v:137571$5840_Y - connect \$475 $ne$libresoc.v:137572$5841_Y - connect \$477 $and$libresoc.v:137573$5842_Y - connect \$47 $eq$libresoc.v:137574$5843_Y - connect \$479 $not$libresoc.v:137575$5844_Y - connect \$481 $and$libresoc.v:137576$5845_Y - connect \$484 $eq$libresoc.v:137577$5846_Y - connect \$483 $not$libresoc.v:137578$5847_Y - connect \$487 $eq$libresoc.v:137579$5848_Y - connect \$489 $eq$libresoc.v:137580$5849_Y - connect \$491 $or$libresoc.v:137581$5850_Y - connect \$493 $eq$libresoc.v:137582$5851_Y - connect \$496 $add$libresoc.v:137583$5852_Y - connect \$49 $eq$libresoc.v:137584$5853_Y - connect \$499 $add$libresoc.v:137585$5854_Y - connect \$501 $pos$libresoc.v:137586$5856_Y - connect \$504 $eq$libresoc.v:137587$5857_Y - connect \$506 $eq$libresoc.v:137588$5858_Y - connect \$508 $or$libresoc.v:137589$5859_Y - connect \$510 $eq$libresoc.v:137590$5860_Y - connect \$513 $add$libresoc.v:137591$5861_Y - connect \$516 $add$libresoc.v:137592$5862_Y - connect \$51 $ternary$libresoc.v:137593$5863_Y - connect \$53 $ternary$libresoc.v:137594$5864_Y - connect \$55 $ternary$libresoc.v:137595$5865_Y - connect \$57 $ternary$libresoc.v:137596$5866_Y - connect \$5 $or$libresoc.v:137597$5867_Y - connect \$59 $ternary$libresoc.v:137598$5868_Y - connect \$61 $ternary$libresoc.v:137599$5869_Y - connect \$63 $ternary$libresoc.v:137600$5870_Y - connect \$65 $ternary$libresoc.v:137601$5871_Y - connect \$67 $ternary$libresoc.v:137602$5872_Y - connect \$69 $ternary$libresoc.v:137603$5873_Y - connect \$71 $ternary$libresoc.v:137604$5874_Y - connect \$73 $ternary$libresoc.v:137605$5875_Y - connect \$75 $ternary$libresoc.v:137606$5876_Y - connect \$77 $ternary$libresoc.v:137607$5877_Y - connect \$7 $and$libresoc.v:137608$5878_Y - connect \$79 $ternary$libresoc.v:137609$5879_Y - connect \$81 $ternary$libresoc.v:137610$5880_Y - connect \$83 $ternary$libresoc.v:137611$5881_Y - connect \$85 $ternary$libresoc.v:137612$5882_Y - connect \$87 $ternary$libresoc.v:137613$5883_Y - connect \$89 $ternary$libresoc.v:137614$5884_Y - connect \$91 $ternary$libresoc.v:137615$5885_Y - connect \$93 $ternary$libresoc.v:137616$5886_Y - connect \$95 $ternary$libresoc.v:137617$5887_Y - connect \$97 $ternary$libresoc.v:137618$5888_Y - connect \$495 \$496 - connect \$498 \$499 - connect \$512 \$513 - connect \$515 \$516 + assign $2\io_bd$next[151:0]$6131 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[151:0]$6131 $1\io_bd$next[151:0]$6130 + end + sync always + update \io_bd$next $0\io_bd$next[151:0]$6129 + end + connect \$9 $eq$libresoc.v:138999$5682_Y + connect \$99 $ternary$libresoc.v:139000$5683_Y + connect \$101 $ternary$libresoc.v:139001$5684_Y + connect \$103 $ternary$libresoc.v:139002$5685_Y + connect \$105 $ternary$libresoc.v:139003$5686_Y + connect \$107 $ternary$libresoc.v:139004$5687_Y + connect \$109 $ternary$libresoc.v:139005$5688_Y + connect \$111 $ternary$libresoc.v:139006$5689_Y + connect \$113 $ternary$libresoc.v:139007$5690_Y + connect \$115 $ternary$libresoc.v:139008$5691_Y + connect \$117 $ternary$libresoc.v:139009$5692_Y + connect \$11 $eq$libresoc.v:139010$5693_Y + connect \$119 $ternary$libresoc.v:139011$5694_Y + connect \$121 $ternary$libresoc.v:139012$5695_Y + connect \$123 $ternary$libresoc.v:139013$5696_Y + connect \$125 $ternary$libresoc.v:139014$5697_Y + connect \$127 $ternary$libresoc.v:139015$5698_Y + connect \$129 $ternary$libresoc.v:139016$5699_Y + connect \$131 $ternary$libresoc.v:139017$5700_Y + connect \$133 $ternary$libresoc.v:139018$5701_Y + connect \$135 $ternary$libresoc.v:139019$5702_Y + connect \$137 $ternary$libresoc.v:139020$5703_Y + connect \$13 $eq$libresoc.v:139021$5704_Y + connect \$139 $ternary$libresoc.v:139022$5705_Y + connect \$141 $ternary$libresoc.v:139023$5706_Y + connect \$143 $ternary$libresoc.v:139024$5707_Y + connect \$145 $ternary$libresoc.v:139025$5708_Y + connect \$147 $ternary$libresoc.v:139026$5709_Y + connect \$149 $ternary$libresoc.v:139027$5710_Y + connect \$151 $ternary$libresoc.v:139028$5711_Y + connect \$153 $ternary$libresoc.v:139029$5712_Y + connect \$155 $ternary$libresoc.v:139030$5713_Y + connect \$157 $ternary$libresoc.v:139031$5714_Y + connect \$15 $or$libresoc.v:139032$5715_Y + connect \$159 $ternary$libresoc.v:139033$5716_Y + connect \$161 $ternary$libresoc.v:139034$5717_Y + connect \$163 $ternary$libresoc.v:139035$5718_Y + connect \$165 $ternary$libresoc.v:139036$5719_Y + connect \$167 $ternary$libresoc.v:139037$5720_Y + connect \$169 $ternary$libresoc.v:139038$5721_Y + connect \$171 $ternary$libresoc.v:139039$5722_Y + connect \$173 $ternary$libresoc.v:139040$5723_Y + connect \$175 $ternary$libresoc.v:139041$5724_Y + connect \$177 $ternary$libresoc.v:139042$5725_Y + connect \$17 $and$libresoc.v:139043$5726_Y + connect \$179 $ternary$libresoc.v:139044$5727_Y + connect \$181 $ternary$libresoc.v:139045$5728_Y + connect \$183 $ternary$libresoc.v:139046$5729_Y + connect \$185 $ternary$libresoc.v:139047$5730_Y + connect \$187 $ternary$libresoc.v:139048$5731_Y + connect \$189 $ternary$libresoc.v:139049$5732_Y + connect \$191 $ternary$libresoc.v:139050$5733_Y + connect \$193 $ternary$libresoc.v:139051$5734_Y + connect \$195 $ternary$libresoc.v:139052$5735_Y + connect \$197 $ternary$libresoc.v:139053$5736_Y + connect \$1 $eq$libresoc.v:139054$5737_Y + connect \$19 $eq$libresoc.v:139055$5738_Y + connect \$199 $ternary$libresoc.v:139056$5739_Y + connect \$201 $ternary$libresoc.v:139057$5740_Y + connect \$203 $ternary$libresoc.v:139058$5741_Y + connect \$205 $ternary$libresoc.v:139059$5742_Y + connect \$207 $ternary$libresoc.v:139060$5743_Y + connect \$209 $ternary$libresoc.v:139061$5744_Y + connect \$211 $ternary$libresoc.v:139062$5745_Y + connect \$213 $ternary$libresoc.v:139063$5746_Y + connect \$215 $ternary$libresoc.v:139064$5747_Y + connect \$217 $ternary$libresoc.v:139065$5748_Y + connect \$21 $eq$libresoc.v:139066$5749_Y + connect \$219 $ternary$libresoc.v:139067$5750_Y + connect \$221 $ternary$libresoc.v:139068$5751_Y + connect \$223 $ternary$libresoc.v:139069$5752_Y + connect \$225 $ternary$libresoc.v:139070$5753_Y + connect \$227 $ternary$libresoc.v:139071$5754_Y + connect \$229 $ternary$libresoc.v:139072$5755_Y + connect \$231 $ternary$libresoc.v:139073$5756_Y + connect \$233 $ternary$libresoc.v:139074$5757_Y + connect \$235 $ternary$libresoc.v:139075$5758_Y + connect \$237 $ternary$libresoc.v:139076$5759_Y + connect \$23 $or$libresoc.v:139077$5760_Y + connect \$239 $ternary$libresoc.v:139078$5761_Y + connect \$241 $ternary$libresoc.v:139079$5762_Y + connect \$243 $ternary$libresoc.v:139080$5763_Y + connect \$245 $ternary$libresoc.v:139081$5764_Y + connect \$247 $ternary$libresoc.v:139082$5765_Y + connect \$249 $ternary$libresoc.v:139083$5766_Y + connect \$251 $ternary$libresoc.v:139084$5767_Y + connect \$253 $ternary$libresoc.v:139085$5768_Y + connect \$255 $ternary$libresoc.v:139086$5769_Y + connect \$257 $ternary$libresoc.v:139087$5770_Y + connect \$25 $eq$libresoc.v:139088$5771_Y + connect \$259 $ternary$libresoc.v:139089$5772_Y + connect \$261 $ternary$libresoc.v:139090$5773_Y + connect \$263 $ternary$libresoc.v:139091$5774_Y + connect \$265 $ternary$libresoc.v:139092$5775_Y + connect \$267 $ternary$libresoc.v:139093$5776_Y + connect \$269 $ternary$libresoc.v:139094$5777_Y + connect \$271 $ternary$libresoc.v:139095$5778_Y + connect \$273 $ternary$libresoc.v:139096$5779_Y + connect \$275 $ternary$libresoc.v:139097$5780_Y + connect \$277 $ternary$libresoc.v:139098$5781_Y + connect \$27 $or$libresoc.v:139099$5782_Y + connect \$279 $ternary$libresoc.v:139100$5783_Y + connect \$281 $ternary$libresoc.v:139101$5784_Y + connect \$283 $ternary$libresoc.v:139102$5785_Y + connect \$285 $ternary$libresoc.v:139103$5786_Y + connect \$287 $ternary$libresoc.v:139104$5787_Y + connect \$289 $ternary$libresoc.v:139105$5788_Y + connect \$291 $ternary$libresoc.v:139106$5789_Y + connect \$293 $ternary$libresoc.v:139107$5790_Y + connect \$295 $ternary$libresoc.v:139108$5791_Y + connect \$297 $ternary$libresoc.v:139109$5792_Y + connect \$29 $and$libresoc.v:139110$5793_Y + connect \$299 $ternary$libresoc.v:139111$5794_Y + connect \$301 $ternary$libresoc.v:139112$5795_Y + connect \$303 $ternary$libresoc.v:139113$5796_Y + connect \$305 $ternary$libresoc.v:139114$5797_Y + connect \$307 $ternary$libresoc.v:139115$5798_Y + connect \$309 $ternary$libresoc.v:139116$5799_Y + connect \$311 $ternary$libresoc.v:139117$5800_Y + connect \$313 $ternary$libresoc.v:139118$5801_Y + connect \$315 $ternary$libresoc.v:139119$5802_Y + connect \$317 $ternary$libresoc.v:139120$5803_Y + connect \$31 $and$libresoc.v:139121$5804_Y + connect \$319 $ternary$libresoc.v:139122$5805_Y + connect \$321 $ternary$libresoc.v:139123$5806_Y + connect \$323 $ternary$libresoc.v:139124$5807_Y + connect \$325 $ternary$libresoc.v:139125$5808_Y + connect \$327 $ternary$libresoc.v:139126$5809_Y + connect \$329 $ternary$libresoc.v:139127$5810_Y + connect \$331 $ternary$libresoc.v:139128$5811_Y + connect \$333 $ternary$libresoc.v:139129$5812_Y + connect \$335 $ternary$libresoc.v:139130$5813_Y + connect \$337 $ternary$libresoc.v:139131$5814_Y + connect \$33 $eq$libresoc.v:139132$5815_Y + connect \$339 $ternary$libresoc.v:139133$5816_Y + connect \$341 $ternary$libresoc.v:139134$5817_Y + connect \$343 $ternary$libresoc.v:139135$5818_Y + connect \$345 $ternary$libresoc.v:139136$5819_Y + connect \$347 $ternary$libresoc.v:139137$5820_Y + connect \$349 $ternary$libresoc.v:139138$5821_Y + connect \$351 $ternary$libresoc.v:139139$5822_Y + connect \$353 $ternary$libresoc.v:139140$5823_Y + connect \$355 $eq$libresoc.v:139141$5824_Y + connect \$357 $eq$libresoc.v:139142$5825_Y + connect \$35 $eq$libresoc.v:139143$5826_Y + connect \$359 $or$libresoc.v:139144$5827_Y + connect \$361 $eq$libresoc.v:139145$5828_Y + connect \$363 $or$libresoc.v:139146$5829_Y + connect \$365 $and$libresoc.v:139147$5830_Y + connect \$367 $eq$libresoc.v:139148$5831_Y + connect \$369 $ne$libresoc.v:139149$5832_Y + connect \$371 $and$libresoc.v:139150$5833_Y + connect \$373 $ne$libresoc.v:139151$5834_Y + connect \$375 $and$libresoc.v:139152$5835_Y + connect \$377 $ne$libresoc.v:139153$5836_Y + connect \$37 $or$libresoc.v:139154$5837_Y + connect \$379 $and$libresoc.v:139155$5838_Y + connect \$381 $not$libresoc.v:139156$5839_Y + connect \$383 $and$libresoc.v:139157$5840_Y + connect \$385 $eq$libresoc.v:139158$5841_Y + connect \$387 $ne$libresoc.v:139159$5842_Y + connect \$389 $and$libresoc.v:139160$5843_Y + connect \$391 $ne$libresoc.v:139161$5844_Y + connect \$393 $and$libresoc.v:139162$5845_Y + connect \$395 $ne$libresoc.v:139163$5846_Y + connect \$397 $and$libresoc.v:139164$5847_Y + connect \$3 $eq$libresoc.v:139165$5848_Y + connect \$39 $eq$libresoc.v:139166$5849_Y + connect \$399 $not$libresoc.v:139167$5850_Y + connect \$401 $and$libresoc.v:139168$5851_Y + connect \$403 $eq$libresoc.v:139169$5852_Y + connect \$405 $eq$libresoc.v:139170$5853_Y + connect \$407 $ne$libresoc.v:139171$5854_Y + connect \$409 $and$libresoc.v:139172$5855_Y + connect \$411 $ne$libresoc.v:139173$5856_Y + connect \$413 $and$libresoc.v:139174$5857_Y + connect \$415 $ne$libresoc.v:139175$5858_Y + connect \$417 $and$libresoc.v:139176$5859_Y + connect \$41 $or$libresoc.v:139177$5860_Y + connect \$419 $not$libresoc.v:139178$5861_Y + connect \$421 $and$libresoc.v:139179$5862_Y + connect \$423 $eq$libresoc.v:139180$5863_Y + connect \$425 $ne$libresoc.v:139181$5864_Y + connect \$427 $and$libresoc.v:139182$5865_Y + connect \$429 $ne$libresoc.v:139183$5866_Y + connect \$431 $and$libresoc.v:139184$5867_Y + connect \$433 $ne$libresoc.v:139185$5868_Y + connect \$435 $and$libresoc.v:139186$5869_Y + connect \$437 $not$libresoc.v:139187$5870_Y + connect \$43 $and$libresoc.v:139188$5871_Y + connect \$439 $and$libresoc.v:139189$5872_Y + connect \$441 $eq$libresoc.v:139190$5873_Y + connect \$443 $eq$libresoc.v:139191$5874_Y + connect \$445 $ne$libresoc.v:139192$5875_Y + connect \$447 $and$libresoc.v:139193$5876_Y + connect \$449 $ne$libresoc.v:139194$5877_Y + connect \$451 $and$libresoc.v:139195$5878_Y + connect \$453 $ne$libresoc.v:139196$5879_Y + connect \$455 $and$libresoc.v:139197$5880_Y + connect \$457 $not$libresoc.v:139198$5881_Y + connect \$45 $and$libresoc.v:139199$5882_Y + connect \$459 $and$libresoc.v:139200$5883_Y + connect \$461 $eq$libresoc.v:139201$5884_Y + connect \$463 $ne$libresoc.v:139202$5885_Y + connect \$465 $and$libresoc.v:139203$5886_Y + connect \$467 $ne$libresoc.v:139204$5887_Y + connect \$469 $and$libresoc.v:139205$5888_Y + connect \$471 $ne$libresoc.v:139206$5889_Y + connect \$473 $and$libresoc.v:139207$5890_Y + connect \$475 $not$libresoc.v:139208$5891_Y + connect \$477 $and$libresoc.v:139209$5892_Y + connect \$47 $eq$libresoc.v:139210$5893_Y + connect \$480 $eq$libresoc.v:139211$5894_Y + connect \$479 $not$libresoc.v:139212$5895_Y + connect \$483 $eq$libresoc.v:139213$5896_Y + connect \$485 $eq$libresoc.v:139214$5897_Y + connect \$487 $or$libresoc.v:139215$5898_Y + connect \$489 $eq$libresoc.v:139216$5899_Y + connect \$492 $add$libresoc.v:139217$5900_Y + connect \$495 $add$libresoc.v:139218$5901_Y + connect \$497 $pos$libresoc.v:139219$5903_Y + connect \$49 $eq$libresoc.v:139220$5904_Y + connect \$500 $eq$libresoc.v:139221$5905_Y + connect \$502 $eq$libresoc.v:139222$5906_Y + connect \$504 $or$libresoc.v:139223$5907_Y + connect \$506 $eq$libresoc.v:139224$5908_Y + connect \$509 $add$libresoc.v:139225$5909_Y + connect \$512 $add$libresoc.v:139226$5910_Y + connect \$51 $ternary$libresoc.v:139227$5911_Y + connect \$53 $ternary$libresoc.v:139228$5912_Y + connect \$55 $ternary$libresoc.v:139229$5913_Y + connect \$57 $ternary$libresoc.v:139230$5914_Y + connect \$5 $or$libresoc.v:139231$5915_Y + connect \$59 $ternary$libresoc.v:139232$5916_Y + connect \$61 $ternary$libresoc.v:139233$5917_Y + connect \$63 $ternary$libresoc.v:139234$5918_Y + connect \$65 $ternary$libresoc.v:139235$5919_Y + connect \$67 $ternary$libresoc.v:139236$5920_Y + connect \$69 $ternary$libresoc.v:139237$5921_Y + connect \$71 $ternary$libresoc.v:139238$5922_Y + connect \$73 $ternary$libresoc.v:139239$5923_Y + connect \$75 $ternary$libresoc.v:139240$5924_Y + connect \$77 $ternary$libresoc.v:139241$5925_Y + connect \$7 $and$libresoc.v:139242$5926_Y + connect \$79 $ternary$libresoc.v:139243$5927_Y + connect \$81 $ternary$libresoc.v:139244$5928_Y + connect \$83 $ternary$libresoc.v:139245$5929_Y + connect \$85 $ternary$libresoc.v:139246$5930_Y + connect \$87 $ternary$libresoc.v:139247$5931_Y + connect \$89 $ternary$libresoc.v:139248$5932_Y + connect \$91 $ternary$libresoc.v:139249$5933_Y + connect \$93 $ternary$libresoc.v:139250$5934_Y + connect \$95 $ternary$libresoc.v:139251$5935_Y + connect \$97 $ternary$libresoc.v:139252$5936_Y + connect \$491 \$492 + connect \$494 \$495 + connect \$508 \$509 + connect \$511 \$512 connect \sr5__ie 1'0 connect \sr0__i \sr0__o - connect \dmi0__we_i \$510 - connect \dmi0__req_i \$508 - connect \dmi0_addrsr__i \$501 - connect \jtag_wb__we \$493 - connect \jtag_wb__stb \$491 - connect \jtag_wb__cyc \$483 + connect \dmi0__we_i \$506 + connect \dmi0__req_i \$504 + connect \dmi0_addrsr__i \$497 + connect \jtag_wb__we \$489 + connect \jtag_wb__stb \$487 + connect \jtag_wb__cyc \$479 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$477 - connect \sr5_shift \$473 - connect \sr5_capture \$469 - connect \sr5_isir \$465 + connect \sr5_update \$473 + connect \sr5_shift \$469 + connect \sr5_capture \$465 + connect \sr5_isir \$461 connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$459 - connect \dmi0_datasr_shift \$455 - connect \dmi0_datasr_capture \$451 - connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr_update \$455 + connect \dmi0_datasr_shift \$451 + connect \dmi0_datasr_capture \$447 + connect \dmi0_datasr_isir { \$443 \$441 } connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$439 - connect \dmi0_addrsr_shift \$435 - connect \dmi0_addrsr_capture \$431 - connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr_update \$435 + connect \dmi0_addrsr_shift \$431 + connect \dmi0_addrsr_capture \$427 + connect \dmi0_addrsr_isir \$423 connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$421 - connect \jtag_wb_datasr_shift \$417 - connect \jtag_wb_datasr_capture \$413 - connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr_update \$417 + connect \jtag_wb_datasr_shift \$413 + connect \jtag_wb_datasr_capture \$409 + connect \jtag_wb_datasr_isir { \$405 \$403 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$401 - connect \jtag_wb_addrsr_shift \$397 - connect \jtag_wb_addrsr_capture \$393 - connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr_update \$397 + connect \jtag_wb_addrsr_shift \$393 + connect \jtag_wb_addrsr_capture \$389 + connect \jtag_wb_addrsr_isir \$385 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$383 - connect \sr0_shift \$379 - connect \sr0_capture \$375 - connect \sr0_isir \$371 + connect \sr0_update \$379 + connect \sr0_shift \$375 + connect \sr0_capture \$371 + connect \sr0_isir \$367 connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$357 - connect \sdr_dq_15__pad__o \$355 - connect \sdr_dq_15__core__i \$353 - connect \sdr_dq_14__pad__oe \$351 - connect \sdr_dq_14__pad__o \$349 - connect \sdr_dq_14__core__i \$347 - connect \sdr_dq_13__pad__oe \$345 - connect \sdr_dq_13__pad__o \$343 - connect \sdr_dq_13__core__i \$341 - connect \sdr_dq_12__pad__oe \$339 - connect \sdr_dq_12__pad__o \$337 - connect \sdr_dq_12__core__i \$335 - connect \sdr_dq_11__pad__oe \$333 - connect \sdr_dq_11__pad__o \$331 - connect \sdr_dq_11__core__i \$329 - connect \sdr_dq_10__pad__oe \$327 - connect \sdr_dq_10__pad__o \$325 - connect \sdr_dq_10__core__i \$323 - connect \sdr_dq_9__pad__oe \$321 - connect \sdr_dq_9__pad__o \$319 - connect \sdr_dq_9__core__i \$317 - connect \sdr_dq_8__pad__oe \$315 - connect \sdr_dq_8__pad__o \$313 - connect \sdr_dq_8__core__i \$311 - connect \sdr_dm_1__pad__oe \$309 - connect \sdr_dm_1__pad__o \$307 - connect \sdr_dm_1__core__i \$305 + connect \sdr_dq_15__pad__oe \$353 + connect \sdr_dq_15__pad__o \$351 + connect \sdr_dq_15__core__i \$349 + connect \sdr_dq_14__pad__oe \$347 + connect \sdr_dq_14__pad__o \$345 + connect \sdr_dq_14__core__i \$343 + connect \sdr_dq_13__pad__oe \$341 + connect \sdr_dq_13__pad__o \$339 + connect \sdr_dq_13__core__i \$337 + connect \sdr_dq_12__pad__oe \$335 + connect \sdr_dq_12__pad__o \$333 + connect \sdr_dq_12__core__i \$331 + connect \sdr_dq_11__pad__oe \$329 + connect \sdr_dq_11__pad__o \$327 + connect \sdr_dq_11__core__i \$325 + connect \sdr_dq_10__pad__oe \$323 + connect \sdr_dq_10__pad__o \$321 + connect \sdr_dq_10__core__i \$319 + connect \sdr_dq_9__pad__oe \$317 + connect \sdr_dq_9__pad__o \$315 + connect \sdr_dq_9__core__i \$313 + connect \sdr_dq_8__pad__oe \$311 + connect \sdr_dq_8__pad__o \$309 + connect \sdr_dq_8__core__i \$307 + connect \sdr_dm_1__pad__o \$305 connect \sdr_a_12__pad__o \$303 connect \sdr_a_11__pad__o \$301 connect \sdr_a_10__pad__o \$299 @@ -222156,14 +224653,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:138654.1-138843.10" +attribute \src "libresoc.v:140286.1-140475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -222266,7 +224763,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:138759.12-138793.4" + attribute \src "libresoc.v:140391.12-140425.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222303,7 +224800,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:138794.9-138816.4" + attribute \src "libresoc.v:140426.9-140448.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222328,7 +224825,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:138817.9-138841.4" + attribute \src "libresoc.v:140449.9-140473.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222356,145 +224853,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:138847.1-139255.10" +attribute \src "libresoc.v:140479.1-140887.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:139110.3-139124.6" - wire $0\idx_l$23$next[0:0]$6162 - attribute \src "libresoc.v:139010.3-139011.35" - wire $0\idx_l$23[0:0]$6129 - attribute \src "libresoc.v:138868.7-138868.24" - wire $0\idx_l$23[0:0]$6184 - attribute \src "libresoc.v:139165.3-139174.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $0\idx_l$23$next[0:0]$6210 + attribute \src "libresoc.v:140642.3-140643.35" + wire $0\idx_l$23[0:0]$6177 + attribute \src "libresoc.v:140500.7-140500.24" + wire $0\idx_l$23[0:0]$6232 + attribute \src "libresoc.v:140797.3-140806.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139155.3-139164.6" + attribute \src "libresoc.v:140787.3-140796.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:138848.7-138848.20" + attribute \src "libresoc.v:140480.7-140480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139031.3-139040.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6131 - attribute \src "libresoc.v:139041.3-139050.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6134 - attribute \src "libresoc.v:139083.3-139092.6" + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 + attribute \src "libresoc.v:140673.3-140682.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 + attribute \src "libresoc.v:140715.3-140724.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139073.3-139082.6" + attribute \src "libresoc.v:140705.3-140714.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139145.3-139154.6" + attribute \src "libresoc.v:140777.3-140786.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139220.3-139229.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6179 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6146 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6147 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6148 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6149 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6150 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6151 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6152 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal[0:0]$6145 - attribute \src "libresoc.v:139230.3-139239.6" + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6194 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6195 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6196 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6197 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6198 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6199 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6200 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal[0:0]$6193 + attribute \src "libresoc.v:140862.3-140871.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139200.3-139209.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6173 - attribute \src "libresoc.v:139210.3-139219.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6176 - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140832.3-140841.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6221 + attribute \src "libresoc.v:140842.3-140851.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6224 + attribute \src "libresoc.v:140694.3-140704.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140694.3-140704.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139135.3-139144.6" + attribute \src "libresoc.v:140767.3-140776.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139125.3-139134.6" + attribute \src "libresoc.v:140757.3-140766.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139051.3-139061.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6137 - attribute \src "libresoc.v:139051.3-139061.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6138 - attribute \src "libresoc.v:139008.3-139009.36" + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 + attribute \src "libresoc.v:140683.3-140693.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + attribute \src "libresoc.v:140640.3-140641.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:139190.3-139199.6" + attribute \src "libresoc.v:140822.3-140831.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140807.3-140821.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139110.3-139124.6" - wire $1\idx_l$23$next[0:0]$6163 - attribute \src "libresoc.v:139165.3-139174.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $1\idx_l$23$next[0:0]$6211 + attribute \src "libresoc.v:140797.3-140806.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139155.3-139164.6" + attribute \src "libresoc.v:140787.3-140796.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:139031.3-139040.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6132 - attribute \src "libresoc.v:139041.3-139050.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6135 - attribute \src "libresoc.v:139083.3-139092.6" + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140673.3-140682.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140715.3-140724.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139073.3-139082.6" + attribute \src "libresoc.v:140705.3-140714.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139145.3-139154.6" + attribute \src "libresoc.v:140777.3-140786.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139220.3-139229.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6180 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6154 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6155 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6156 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6157 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6158 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6159 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6160 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal[0:0]$6153 - attribute \src "libresoc.v:139230.3-139239.6" + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6202 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6203 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6204 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6205 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6206 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6207 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal[0:0]$6201 + attribute \src "libresoc.v:140862.3-140871.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139200.3-139209.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6174 - attribute \src "libresoc.v:139210.3-139219.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6177 - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140832.3-140841.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140842.3-140851.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140694.3-140704.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140694.3-140704.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139135.3-139144.6" + attribute \src "libresoc.v:140767.3-140776.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139125.3-139134.6" + attribute \src "libresoc.v:140757.3-140766.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139051.3-139061.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6139 - attribute \src "libresoc.v:139051.3-139061.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6140 - attribute \src "libresoc.v:138995.7-138995.25" + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 + attribute \src "libresoc.v:140683.3-140693.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140627.7-140627.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:139190.3-139199.6" + attribute \src "libresoc.v:140822.3-140831.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140807.3-140821.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139110.3-139124.6" - wire $2\idx_l$23$next[0:0]$6164 - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140807.3-140821.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139006.18-139006.103" - wire $not$libresoc.v:139006$6125_Y - attribute \src "libresoc.v:139007.18-139007.118" - wire $not$libresoc.v:139007$6126_Y - attribute \src "libresoc.v:139004.18-139004.134" - wire $or$libresoc.v:139004$6123_Y - attribute \src "libresoc.v:139005.18-139005.120" - wire $ternary$libresoc.v:139005$6124_Y + attribute \src "libresoc.v:140638.18-140638.103" + wire $not$libresoc.v:140638$6173_Y + attribute \src "libresoc.v:140639.18-140639.118" + wire $not$libresoc.v:140639$6174_Y + attribute \src "libresoc.v:140636.18-140636.134" + wire $or$libresoc.v:140636$6171_Y + attribute \src "libresoc.v:140637.18-140637.120" + wire $ternary$libresoc.v:140637$6172_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -222509,9 +225006,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -222523,7 +225020,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:138848.7-138848.15" + attribute \src "libresoc.v:140480.7-140480.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -222634,23 +225131,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:139006$6125 + cell $not $not$libresoc.v:140638$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:139006$6125_Y + connect \Y $not$libresoc.v:140638$6173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:139007$6126 + cell $not $not$libresoc.v:140639$6174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:139007$6126_Y + connect \Y $not$libresoc.v:140639$6174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:139004$6123 + cell $or $or$libresoc.v:140636$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222658,18 +225155,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:139004$6123_Y + connect \Y $or$libresoc.v:140636$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:139005$6124 + cell $mux $ternary$libresoc.v:140637$6172 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:139005$6124_Y + connect \Y $ternary$libresoc.v:140637$6172_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139012.9-139018.4" + attribute \src "libresoc.v:140644.9-140650.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222678,14 +225175,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:139019.8-139023.4" + attribute \src "libresoc.v:140651.8-140655.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:139024.17-139030.4" + attribute \src "libresoc.v:140656.17-140662.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222693,52 +225190,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:138848.7-138848.20" - process $proc$libresoc.v:138848$6182 + attribute \src "libresoc.v:140480.7-140480.20" + process $proc$libresoc.v:140480$6230 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138868.7-138868.24" - process $proc$libresoc.v:138868$6183 + attribute \src "libresoc.v:140500.7-140500.24" + process $proc$libresoc.v:140500$6231 assign { } { } - assign $0\idx_l$23[0:0]$6184 1'0 + assign $0\idx_l$23[0:0]$6232 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$6184 + update \idx_l$23 $0\idx_l$23[0:0]$6232 end - attribute \src "libresoc.v:138995.7-138995.25" - process $proc$libresoc.v:138995$6185 + attribute \src "libresoc.v:140627.7-140627.25" + process $proc$libresoc.v:140627$6233 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:139008.3-139009.36" - process $proc$libresoc.v:139008$6127 + attribute \src "libresoc.v:140640.3-140641.36" + process $proc$libresoc.v:140640$6175 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:139010.3-139011.35" - process $proc$libresoc.v:139010$6128 + attribute \src "libresoc.v:140642.3-140643.35" + process $proc$libresoc.v:140642$6176 assign { } { } - assign $0\idx_l$23[0:0]$6129 \idx_l$23$next + assign $0\idx_l$23[0:0]$6177 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6129 + update \idx_l$23 $0\idx_l$23[0:0]$6177 end - attribute \src "libresoc.v:139031.3-139040.6" - process $proc$libresoc.v:139031$6130 + attribute \src "libresoc.v:140663.3-140672.6" + process $proc$libresoc.v:140663$6178 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6131 $1\ldst_port0_addr_i$12[47:0]$6132 - attribute \src "libresoc.v:139032.5-139032.29" + assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140664.5-140664.29" switch \initial - attribute \src "libresoc.v:139032.9-139032.17" + attribute \src "libresoc.v:140664.9-140664.17" case 1'1 case end @@ -222747,21 +225244,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6132 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6180 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$6132 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6180 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6131 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 end - attribute \src "libresoc.v:139041.3-139050.6" - process $proc$libresoc.v:139041$6133 + attribute \src "libresoc.v:140673.3-140682.6" + process $proc$libresoc.v:140673$6181 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6134 $1\ldst_port0_addr_i_ok$13[0:0]$6135 - attribute \src "libresoc.v:139042.5-139042.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140674.5-140674.29" switch \initial - attribute \src "libresoc.v:139042.9-139042.17" + attribute \src "libresoc.v:140674.9-140674.17" case 1'1 case end @@ -222770,24 +225267,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6134 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 end - attribute \src "libresoc.v:139051.3-139061.6" - process $proc$libresoc.v:139051$6136 + attribute \src "libresoc.v:140683.3-140693.6" + process $proc$libresoc.v:140683$6184 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6137 $1\ldst_port0_st_data_i$18[63:0]$6139 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6138 $1\ldst_port0_st_data_i_ok$17[0:0]$6140 - attribute \src "libresoc.v:139052.5-139052.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140684.5-140684.29" switch \initial - attribute \src "libresoc.v:139052.9-139052.17" + attribute \src "libresoc.v:140684.9-140684.17" case 1'1 case end @@ -222797,26 +225294,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6140 $1\ldst_port0_st_data_i$18[63:0]$6139 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6188 $1\ldst_port0_st_data_i$18[63:0]$6187 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$6139 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6140 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6188 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6137 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6138 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 end - attribute \src "libresoc.v:139062.3-139072.6" - process $proc$libresoc.v:139062$6141 + attribute \src "libresoc.v:140694.3-140704.6" + process $proc$libresoc.v:140694$6189 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139063.5-139063.29" + attribute \src "libresoc.v:140695.5-140695.29" switch \initial - attribute \src "libresoc.v:139063.9-139063.17" + attribute \src "libresoc.v:140695.9-140695.17" case 1'1 case end @@ -222835,14 +225332,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:139073.3-139082.6" - process $proc$libresoc.v:139073$6142 + attribute \src "libresoc.v:140705.3-140714.6" + process $proc$libresoc.v:140705$6190 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139074.5-139074.29" + attribute \src "libresoc.v:140706.5-140706.29" switch \initial - attribute \src "libresoc.v:139074.9-139074.17" + attribute \src "libresoc.v:140706.9-140706.17" case 1'1 case end @@ -222858,14 +225355,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:139083.3-139092.6" - process $proc$libresoc.v:139083$6143 + attribute \src "libresoc.v:140715.3-140724.6" + process $proc$libresoc.v:140715$6191 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139084.5-139084.29" + attribute \src "libresoc.v:140716.5-140716.29" switch \initial - attribute \src "libresoc.v:139084.9-139084.17" + attribute \src "libresoc.v:140716.9-140716.17" case 1'1 case end @@ -222881,8 +225378,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:139093.3-139109.6" - process $proc$libresoc.v:139093$6144 + attribute \src "libresoc.v:140725.3-140741.6" + process $proc$libresoc.v:140725$6192 assign { } { } assign { } { } assign { } { } @@ -222899,17 +225396,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6145 $1\ldst_port0_exc_$signal[0:0]$6153 - assign $0\ldst_port0_exc_$signal$1[0:0]$6146 $1\ldst_port0_exc_$signal$1[0:0]$6154 - assign $0\ldst_port0_exc_$signal$2[0:0]$6147 $1\ldst_port0_exc_$signal$2[0:0]$6155 - assign $0\ldst_port0_exc_$signal$3[0:0]$6148 $1\ldst_port0_exc_$signal$3[0:0]$6156 - assign $0\ldst_port0_exc_$signal$4[0:0]$6149 $1\ldst_port0_exc_$signal$4[0:0]$6157 - assign $0\ldst_port0_exc_$signal$5[0:0]$6150 $1\ldst_port0_exc_$signal$5[0:0]$6158 - assign $0\ldst_port0_exc_$signal$6[0:0]$6151 $1\ldst_port0_exc_$signal$6[0:0]$6159 - assign $0\ldst_port0_exc_$signal$7[0:0]$6152 $1\ldst_port0_exc_$signal$7[0:0]$6160 - attribute \src "libresoc.v:139094.5-139094.29" + assign $0\ldst_port0_exc_$signal[0:0]$6193 $1\ldst_port0_exc_$signal[0:0]$6201 + assign $0\ldst_port0_exc_$signal$1[0:0]$6194 $1\ldst_port0_exc_$signal$1[0:0]$6202 + assign $0\ldst_port0_exc_$signal$2[0:0]$6195 $1\ldst_port0_exc_$signal$2[0:0]$6203 + assign $0\ldst_port0_exc_$signal$3[0:0]$6196 $1\ldst_port0_exc_$signal$3[0:0]$6204 + assign $0\ldst_port0_exc_$signal$4[0:0]$6197 $1\ldst_port0_exc_$signal$4[0:0]$6205 + assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 + assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 + assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140726.5-140726.29" switch \initial - attribute \src "libresoc.v:139094.9-139094.17" + attribute \src "libresoc.v:140726.9-140726.17" case 1'1 case end @@ -222925,36 +225422,36 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6160 $1\ldst_port0_exc_$signal$6[0:0]$6159 $1\ldst_port0_exc_$signal$5[0:0]$6158 $1\ldst_port0_exc_$signal$4[0:0]$6157 $1\ldst_port0_exc_$signal$3[0:0]$6156 $1\ldst_port0_exc_$signal$2[0:0]$6155 $1\ldst_port0_exc_$signal$1[0:0]$6154 $1\ldst_port0_exc_$signal[0:0]$6153 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6208 $1\ldst_port0_exc_$signal$6[0:0]$6207 $1\ldst_port0_exc_$signal$5[0:0]$6206 $1\ldst_port0_exc_$signal$4[0:0]$6205 $1\ldst_port0_exc_$signal$3[0:0]$6204 $1\ldst_port0_exc_$signal$2[0:0]$6203 $1\ldst_port0_exc_$signal$1[0:0]$6202 $1\ldst_port0_exc_$signal[0:0]$6201 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$6153 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6154 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6155 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6156 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6157 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6158 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6159 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6160 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6201 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6202 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6203 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6204 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6205 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6206 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6207 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6208 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6145 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6146 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6147 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6148 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6149 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6150 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6151 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6152 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6193 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6194 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6195 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6196 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6197 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6198 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 end - attribute \src "libresoc.v:139110.3-139124.6" - process $proc$libresoc.v:139110$6161 + attribute \src "libresoc.v:140742.3-140756.6" + process $proc$libresoc.v:140742$6209 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$6162 $2\idx_l$23$next[0:0]$6164 - attribute \src "libresoc.v:139111.5-139111.29" + assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140743.5-140743.29" switch \initial - attribute \src "libresoc.v:139111.9-139111.17" + attribute \src "libresoc.v:140743.9-140743.17" case 1'1 case end @@ -222963,30 +225460,30 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$6163 \pick_o + assign $1\idx_l$23$next[0:0]$6211 \pick_o case - assign $1\idx_l$23$next[0:0]$6163 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6211 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$6164 1'0 + assign $2\idx_l$23$next[0:0]$6212 1'0 case - assign $2\idx_l$23$next[0:0]$6164 $1\idx_l$23$next[0:0]$6163 + assign $2\idx_l$23$next[0:0]$6212 $1\idx_l$23$next[0:0]$6211 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6162 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 end - attribute \src "libresoc.v:139125.3-139134.6" - process $proc$libresoc.v:139125$6165 + attribute \src "libresoc.v:140757.3-140766.6" + process $proc$libresoc.v:140757$6213 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139126.5-139126.29" + attribute \src "libresoc.v:140758.5-140758.29" switch \initial - attribute \src "libresoc.v:139126.9-139126.17" + attribute \src "libresoc.v:140758.9-140758.17" case 1'1 case end @@ -223002,14 +225499,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:139135.3-139144.6" - process $proc$libresoc.v:139135$6166 + attribute \src "libresoc.v:140767.3-140776.6" + process $proc$libresoc.v:140767$6214 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139136.5-139136.29" + attribute \src "libresoc.v:140768.5-140768.29" switch \initial - attribute \src "libresoc.v:139136.9-139136.17" + attribute \src "libresoc.v:140768.9-140768.17" case 1'1 case end @@ -223025,14 +225522,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:139145.3-139154.6" - process $proc$libresoc.v:139145$6167 + attribute \src "libresoc.v:140777.3-140786.6" + process $proc$libresoc.v:140777$6215 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139146.5-139146.29" + attribute \src "libresoc.v:140778.5-140778.29" switch \initial - attribute \src "libresoc.v:139146.9-139146.17" + attribute \src "libresoc.v:140778.9-140778.17" case 1'1 case end @@ -223048,14 +225545,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:139155.3-139164.6" - process $proc$libresoc.v:139155$6168 + attribute \src "libresoc.v:140787.3-140796.6" + process $proc$libresoc.v:140787$6216 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:139156.5-139156.29" + attribute \src "libresoc.v:140788.5-140788.29" switch \initial - attribute \src "libresoc.v:139156.9-139156.17" + attribute \src "libresoc.v:140788.9-140788.17" case 1'1 case end @@ -223071,14 +225568,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:139165.3-139174.6" - process $proc$libresoc.v:139165$6169 + attribute \src "libresoc.v:140797.3-140806.6" + process $proc$libresoc.v:140797$6217 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139166.5-139166.29" + attribute \src "libresoc.v:140798.5-140798.29" switch \initial - attribute \src "libresoc.v:139166.9-139166.17" + attribute \src "libresoc.v:140798.9-140798.17" case 1'1 case end @@ -223094,14 +225591,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:139175.3-139189.6" - process $proc$libresoc.v:139175$6170 + attribute \src "libresoc.v:140807.3-140821.6" + process $proc$libresoc.v:140807$6218 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139176.5-139176.29" + attribute \src "libresoc.v:140808.5-140808.29" switch \initial - attribute \src "libresoc.v:139176.9-139176.17" + attribute \src "libresoc.v:140808.9-140808.17" case 1'1 case end @@ -223126,14 +225623,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:139190.3-139199.6" - process $proc$libresoc.v:139190$6171 + attribute \src "libresoc.v:140822.3-140831.6" + process $proc$libresoc.v:140822$6219 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139191.5-139191.29" + attribute \src "libresoc.v:140823.5-140823.29" switch \initial - attribute \src "libresoc.v:139191.9-139191.17" + attribute \src "libresoc.v:140823.9-140823.17" case 1'1 case end @@ -223149,14 +225646,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:139200.3-139209.6" - process $proc$libresoc.v:139200$6172 + attribute \src "libresoc.v:140832.3-140841.6" + process $proc$libresoc.v:140832$6220 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6173 $1\ldst_port0_is_ld_i$8[0:0]$6174 - attribute \src "libresoc.v:139201.5-139201.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140833.5-140833.29" switch \initial - attribute \src "libresoc.v:139201.9-139201.17" + attribute \src "libresoc.v:140833.9-140833.17" case 1'1 case end @@ -223165,21 +225662,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6174 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$6174 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6173 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 end - attribute \src "libresoc.v:139210.3-139219.6" - process $proc$libresoc.v:139210$6175 + attribute \src "libresoc.v:140842.3-140851.6" + process $proc$libresoc.v:140842$6223 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6176 $1\ldst_port0_is_st_i$9[0:0]$6177 - attribute \src "libresoc.v:139211.5-139211.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140843.5-140843.29" switch \initial - attribute \src "libresoc.v:139211.9-139211.17" + attribute \src "libresoc.v:140843.9-140843.17" case 1'1 case end @@ -223188,21 +225685,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6177 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6225 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$6177 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6225 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6176 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 end - attribute \src "libresoc.v:139220.3-139229.6" - process $proc$libresoc.v:139220$6178 + attribute \src "libresoc.v:140852.3-140861.6" + process $proc$libresoc.v:140852$6226 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6179 $1\ldst_port0_data_len$11[3:0]$6180 - attribute \src "libresoc.v:139221.5-139221.29" + assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140853.5-140853.29" switch \initial - attribute \src "libresoc.v:139221.9-139221.17" + attribute \src "libresoc.v:140853.9-140853.17" case 1'1 case end @@ -223211,21 +225708,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6180 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6228 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$6180 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6228 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6179 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 end - attribute \src "libresoc.v:139230.3-139239.6" - process $proc$libresoc.v:139230$6181 + attribute \src "libresoc.v:140862.3-140871.6" + process $proc$libresoc.v:140862$6229 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139231.5-139231.29" + attribute \src "libresoc.v:140863.5-140863.29" switch \initial - attribute \src "libresoc.v:139231.9-139231.17" + attribute \src "libresoc.v:140863.9-140863.17" case 1'1 case end @@ -223241,10 +225738,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:139004$6123_Y - connect \$24 $ternary$libresoc.v:139005$6124_Y - connect \$26 $not$libresoc.v:139006$6125_Y - connect \$28 $not$libresoc.v:139007$6126_Y + connect \$20 $or$libresoc.v:140636$6171_Y + connect \$24 $ternary$libresoc.v:140637$6172_Y + connect \$26 $not$libresoc.v:140638$6173_Y + connect \$28 $not$libresoc.v:140639$6174_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -223261,37 +225758,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:139259.1-139317.10" +attribute \src "libresoc.v:140891.1-140949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:139260.7-139260.20" + attribute \src "libresoc.v:140892.7-140892.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139305.3-139313.6" - wire $0\q_int$next[0:0]$6196 - attribute \src "libresoc.v:139303.3-139304.27" + attribute \src "libresoc.v:140937.3-140945.6" + wire $0\q_int$next[0:0]$6244 + attribute \src "libresoc.v:140935.3-140936.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:139305.3-139313.6" - wire $1\q_int$next[0:0]$6197 - attribute \src "libresoc.v:139282.7-139282.19" + attribute \src "libresoc.v:140937.3-140945.6" + wire $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140914.7-140914.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:139295.17-139295.96" - wire $and$libresoc.v:139295$6186_Y - attribute \src "libresoc.v:139300.17-139300.96" - wire $and$libresoc.v:139300$6191_Y - attribute \src "libresoc.v:139297.18-139297.99" - wire $not$libresoc.v:139297$6188_Y - attribute \src "libresoc.v:139299.17-139299.98" - wire $not$libresoc.v:139299$6190_Y - attribute \src "libresoc.v:139302.17-139302.98" - wire $not$libresoc.v:139302$6193_Y - attribute \src "libresoc.v:139296.18-139296.104" - wire $or$libresoc.v:139296$6187_Y - attribute \src "libresoc.v:139298.18-139298.105" - wire $or$libresoc.v:139298$6189_Y - attribute \src "libresoc.v:139301.17-139301.103" - wire $or$libresoc.v:139301$6192_Y + attribute \src "libresoc.v:140927.17-140927.96" + wire $and$libresoc.v:140927$6234_Y + attribute \src "libresoc.v:140932.17-140932.96" + wire $and$libresoc.v:140932$6239_Y + attribute \src "libresoc.v:140929.18-140929.99" + wire $not$libresoc.v:140929$6236_Y + attribute \src "libresoc.v:140931.17-140931.98" + wire $not$libresoc.v:140931$6238_Y + attribute \src "libresoc.v:140934.17-140934.98" + wire $not$libresoc.v:140934$6241_Y + attribute \src "libresoc.v:140928.18-140928.104" + wire $or$libresoc.v:140928$6235_Y + attribute \src "libresoc.v:140930.18-140930.105" + wire $or$libresoc.v:140930$6237_Y + attribute \src "libresoc.v:140933.17-140933.103" + wire $or$libresoc.v:140933$6240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -223308,11 +225805,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:139260.7-139260.15" + attribute \src "libresoc.v:140892.7-140892.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -223329,7 +225826,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:139295$6186 + cell $and $and$libresoc.v:140927$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223337,10 +225834,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:139295$6186_Y + connect \Y $and$libresoc.v:140927$6234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:139300$6191 + cell $and $and$libresoc.v:140932$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223348,34 +225845,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:139300$6191_Y + connect \Y $and$libresoc.v:140932$6239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:139297$6188 + cell $not $not$libresoc.v:140929$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:139297$6188_Y + connect \Y $not$libresoc.v:140929$6236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:139299$6190 + cell $not $not$libresoc.v:140931$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:139299$6190_Y + connect \Y $not$libresoc.v:140931$6238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:139302$6193 + cell $not $not$libresoc.v:140934$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:139302$6193_Y + connect \Y $not$libresoc.v:140934$6241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:139296$6187 + cell $or $or$libresoc.v:140928$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223383,10 +225880,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:139296$6187_Y + connect \Y $or$libresoc.v:140928$6235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:139298$6189 + cell $or $or$libresoc.v:140930$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223394,10 +225891,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:139298$6189_Y + connect \Y $or$libresoc.v:140930$6237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:139301$6192 + cell $or $or$libresoc.v:140933$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223405,39 +225902,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:139301$6192_Y + connect \Y $or$libresoc.v:140933$6240_Y end - attribute \src "libresoc.v:139260.7-139260.20" - process $proc$libresoc.v:139260$6198 + attribute \src "libresoc.v:140892.7-140892.20" + process $proc$libresoc.v:140892$6246 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139282.7-139282.19" - process $proc$libresoc.v:139282$6199 + attribute \src "libresoc.v:140914.7-140914.19" + process $proc$libresoc.v:140914$6247 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:139303.3-139304.27" - process $proc$libresoc.v:139303$6194 + attribute \src "libresoc.v:140935.3-140936.27" + process $proc$libresoc.v:140935$6242 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:139305.3-139313.6" - process $proc$libresoc.v:139305$6195 + attribute \src "libresoc.v:140937.3-140945.6" + process $proc$libresoc.v:140937$6243 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6196 $1\q_int$next[0:0]$6197 - attribute \src "libresoc.v:139306.5-139306.29" + assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140938.5-140938.29" switch \initial - attribute \src "libresoc.v:139306.9-139306.17" + attribute \src "libresoc.v:140938.9-140938.17" case 1'1 case end @@ -223446,572 +225943,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6197 1'0 + assign $1\q_int$next[0:0]$6245 1'0 case - assign $1\q_int$next[0:0]$6197 \$5 + assign $1\q_int$next[0:0]$6245 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6196 + update \q_int$next $0\q_int$next[0:0]$6244 end - connect \$9 $and$libresoc.v:139295$6186_Y - connect \$11 $or$libresoc.v:139296$6187_Y - connect \$13 $not$libresoc.v:139297$6188_Y - connect \$15 $or$libresoc.v:139298$6189_Y - connect \$1 $not$libresoc.v:139299$6190_Y - connect \$3 $and$libresoc.v:139300$6191_Y - connect \$5 $or$libresoc.v:139301$6192_Y - connect \$7 $not$libresoc.v:139302$6193_Y + connect \$9 $and$libresoc.v:140927$6234_Y + connect \$11 $or$libresoc.v:140928$6235_Y + connect \$13 $not$libresoc.v:140929$6236_Y + connect \$15 $or$libresoc.v:140930$6237_Y + connect \$1 $not$libresoc.v:140931$6238_Y + connect \$3 $and$libresoc.v:140932$6239_Y + connect \$5 $or$libresoc.v:140933$6240_Y + connect \$7 $not$libresoc.v:140934$6241_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:139321.1-140684.10" +attribute \src "libresoc.v:140953.1-142316.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:140339.3-140347.6" - wire $0\adr_l_r_adr$next[0:0]$6342 - attribute \src "libresoc.v:140221.3-140222.39" + attribute \src "libresoc.v:141971.3-141979.6" + wire $0\adr_l_r_adr$next[0:0]$6390 + attribute \src "libresoc.v:141853.3-141854.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:140167.3-140168.21" + attribute \src "libresoc.v:141799.3-141800.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:140504.3-140513.6" + attribute \src "libresoc.v:142136.3-142145.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:140514.3-140523.6" + attribute \src "libresoc.v:142146.3-142155.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:140494.3-140503.6" - wire width 64 $0\ea_r$next[63:0]$6430 - attribute \src "libresoc.v:140169.3-140170.25" + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $0\ea_r$next[63:0]$6478 + attribute \src "libresoc.v:141801.3-141802.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:139322.7-139322.20" + attribute \src "libresoc.v:140954.7-140954.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:140436.3-140445.6" - wire width 64 $0\ldo_r$next[63:0]$6415 - attribute \src "libresoc.v:140177.3-140178.27" + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $0\ldo_r$next[63:0]$6463 + attribute \src "libresoc.v:141809.3-141810.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:140165.3-140166.33" + attribute \src "libresoc.v:141797.3-141798.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:140524.3-140532.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6435 - attribute \src "libresoc.v:140163.3-140164.57" + attribute \src "libresoc.v:142156.3-142164.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 + attribute \src "libresoc.v:141795.3-141796.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:140613.3-140624.6" + attribute \src "libresoc.v:142245.3-142256.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140384.3-140392.6" - wire $0\lsd_l_r_lsd$next[0:0]$6357 - attribute \src "libresoc.v:140211.3-140212.39" + attribute \src "libresoc.v:142016.3-142024.6" + wire $0\lsd_l_r_lsd$next[0:0]$6405 + attribute \src "libresoc.v:141843.3-141844.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:140312.3-140320.6" - wire $0\opc_l_r_opc$next[0:0]$6333 - attribute \src "libresoc.v:140227.3-140228.39" + attribute \src "libresoc.v:141944.3-141952.6" + wire $0\opc_l_r_opc$next[0:0]$6381 + attribute \src "libresoc.v:141859.3-141860.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140303.3-140311.6" - wire $0\opc_l_s_opc$next[0:0]$6330 - attribute \src "libresoc.v:140229.3-140230.39" + attribute \src "libresoc.v:141935.3-141943.6" + wire $0\opc_l_s_opc$next[0:0]$6378 + attribute \src "libresoc.v:141861.3-141862.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__byte_reverse$next[0:0]$6360 - attribute \src "libresoc.v:140203.3-140204.57" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__byte_reverse$next[0:0]$6408 + attribute \src "libresoc.v:141835.3-141836.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6361 - attribute \src "libresoc.v:140201.3-140202.49" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6409 + attribute \src "libresoc.v:141833.3-141834.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $0\oper_r__fn_unit$next[13:0]$6362 - attribute \src "libresoc.v:140181.3-140182.47" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 + attribute \src "libresoc.v:141813.3-141814.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6363 - attribute \src "libresoc.v:140183.3-140184.61" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 + attribute \src "libresoc.v:141815.3-141816.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6364 - attribute \src "libresoc.v:140185.3-140186.57" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6412 + attribute \src "libresoc.v:141817.3-141818.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $0\oper_r__insn$next[31:0]$6365 - attribute \src "libresoc.v:140209.3-140210.41" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $0\oper_r__insn$next[31:0]$6413 + attribute \src "libresoc.v:141841.3-141842.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6366 - attribute \src "libresoc.v:140179.3-140180.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6414 + attribute \src "libresoc.v:141811.3-141812.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__is_32bit$next[0:0]$6367 - attribute \src "libresoc.v:140197.3-140198.49" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_32bit$next[0:0]$6415 + attribute \src "libresoc.v:141829.3-141830.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__is_signed$next[0:0]$6368 - attribute \src "libresoc.v:140199.3-140200.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_signed$next[0:0]$6416 + attribute \src "libresoc.v:141831.3-141832.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6369 - attribute \src "libresoc.v:140207.3-140208.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 + attribute \src "libresoc.v:141839.3-141840.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__oe__oe$next[0:0]$6370 - attribute \src "libresoc.v:140193.3-140194.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__oe$next[0:0]$6418 + attribute \src "libresoc.v:141825.3-141826.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__oe__ok$next[0:0]$6371 - attribute \src "libresoc.v:140195.3-140196.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__ok$next[0:0]$6419 + attribute \src "libresoc.v:141827.3-141828.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__rc__ok$next[0:0]$6372 - attribute \src "libresoc.v:140191.3-140192.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__ok$next[0:0]$6420 + attribute \src "libresoc.v:141823.3-141824.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__rc__rc$next[0:0]$6373 - attribute \src "libresoc.v:140189.3-140190.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__rc$next[0:0]$6421 + attribute \src "libresoc.v:141821.3-141822.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__sign_extend$next[0:0]$6374 - attribute \src "libresoc.v:140205.3-140206.55" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__sign_extend$next[0:0]$6422 + attribute \src "libresoc.v:141837.3-141838.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__zero_a$next[0:0]$6375 - attribute \src "libresoc.v:140187.3-140188.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__zero_a$next[0:0]$6423 + attribute \src "libresoc.v:141819.3-141820.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:140231.3-140232.28" + attribute \src "libresoc.v:141863.3-141864.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:140557.3-140568.6" + attribute \src "libresoc.v:142189.3-142200.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:140330.3-140338.6" - wire width 3 $0\src_l_r_src$next[2:0]$6339 - attribute \src "libresoc.v:140223.3-140224.39" + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $0\src_l_r_src$next[2:0]$6387 + attribute \src "libresoc.v:141855.3-141856.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:140321.3-140329.6" - wire width 3 $0\src_l_s_src$next[2:0]$6336 - attribute \src "libresoc.v:140225.3-140226.39" + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $0\src_l_s_src$next[2:0]$6384 + attribute \src "libresoc.v:141857.3-141858.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $0\src_r0$next[63:0]$6418 - attribute \src "libresoc.v:140175.3-140176.29" + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $0\src_r0$next[63:0]$6466 + attribute \src "libresoc.v:141807.3-141808.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $0\src_r1$next[63:0]$6422 - attribute \src "libresoc.v:140173.3-140174.29" + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $0\src_r1$next[63:0]$6470 + attribute \src "libresoc.v:141805.3-141806.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $0\src_r2$next[63:0]$6426 - attribute \src "libresoc.v:140171.3-140172.29" + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $0\src_r2$next[63:0]$6474 + attribute \src "libresoc.v:141803.3-141804.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:140375.3-140383.6" - wire $0\sto_l_r_sto$next[0:0]$6354 - attribute \src "libresoc.v:140213.3-140214.39" + attribute \src "libresoc.v:142007.3-142015.6" + wire $0\sto_l_r_sto$next[0:0]$6402 + attribute \src "libresoc.v:141845.3-141846.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:140366.3-140374.6" - wire $0\upd_l_r_upd$next[0:0]$6351 - attribute \src "libresoc.v:140215.3-140216.39" + attribute \src "libresoc.v:141998.3-142006.6" + wire $0\upd_l_r_upd$next[0:0]$6399 + attribute \src "libresoc.v:141847.3-141848.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:140357.3-140365.6" - wire $0\upd_l_s_upd$next[0:0]$6348 - attribute \src "libresoc.v:140217.3-140218.39" + attribute \src "libresoc.v:141989.3-141997.6" + wire $0\upd_l_s_upd$next[0:0]$6396 + attribute \src "libresoc.v:141849.3-141850.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:140348.3-140356.6" - wire $0\wri_l_r_wri$next[0:0]$6345 - attribute \src "libresoc.v:140219.3-140220.39" + attribute \src "libresoc.v:141980.3-141988.6" + wire $0\wri_l_r_wri$next[0:0]$6393 + attribute \src "libresoc.v:141851.3-141852.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:140339.3-140347.6" - wire $1\adr_l_r_adr$next[0:0]$6343 - attribute \src "libresoc.v:139518.7-139518.25" + attribute \src "libresoc.v:141971.3-141979.6" + wire $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141150.7-141150.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:139532.7-139532.20" + attribute \src "libresoc.v:141164.7-141164.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:140504.3-140513.6" + attribute \src "libresoc.v:142136.3-142145.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:140514.3-140523.6" + attribute \src "libresoc.v:142146.3-142155.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:140494.3-140503.6" - wire width 64 $1\ea_r$next[63:0]$6431 - attribute \src "libresoc.v:139578.14-139578.41" + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:141210.14-141210.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:140436.3-140445.6" - wire width 64 $1\ldo_r$next[63:0]$6416 - attribute \src "libresoc.v:139608.14-139608.42" + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:141240.14-141240.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:139613.14-139613.62" + attribute \src "libresoc.v:141245.14-141245.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:140524.3-140532.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6436 - attribute \src "libresoc.v:139618.7-139618.34" + attribute \src "libresoc.v:142156.3-142164.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:141250.7-141250.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:140613.3-140624.6" + attribute \src "libresoc.v:142245.3-142256.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140384.3-140392.6" - wire $1\lsd_l_r_lsd$next[0:0]$6358 - attribute \src "libresoc.v:139667.7-139667.25" + attribute \src "libresoc.v:142016.3-142024.6" + wire $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:141299.7-141299.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:140312.3-140320.6" - wire $1\opc_l_r_opc$next[0:0]$6334 - attribute \src "libresoc.v:139681.7-139681.25" + attribute \src "libresoc.v:141944.3-141952.6" + wire $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141313.7-141313.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140303.3-140311.6" - wire $1\opc_l_s_opc$next[0:0]$6331 - attribute \src "libresoc.v:139685.7-139685.25" + attribute \src "libresoc.v:141935.3-141943.6" + wire $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141317.7-141317.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__byte_reverse$next[0:0]$6376 - attribute \src "libresoc.v:139816.7-139816.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__byte_reverse$next[0:0]$6424 + attribute \src "libresoc.v:141448.7-141448.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6377 - attribute \src "libresoc.v:139820.13-139820.36" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6425 + attribute \src "libresoc.v:141452.13-141452.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $1\oper_r__fn_unit$next[13:0]$6378 - attribute \src "libresoc.v:139839.14-139839.40" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 + attribute \src "libresoc.v:141471.14-141471.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6379 - attribute \src "libresoc.v:139843.14-139843.59" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 + attribute \src "libresoc.v:141475.14-141475.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6380 - attribute \src "libresoc.v:139847.7-139847.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6428 + attribute \src "libresoc.v:141479.7-141479.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $1\oper_r__insn$next[31:0]$6381 - attribute \src "libresoc.v:139851.14-139851.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $1\oper_r__insn$next[31:0]$6429 + attribute \src "libresoc.v:141483.14-141483.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6382 - attribute \src "libresoc.v:139930.13-139930.38" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6430 + attribute \src "libresoc.v:141562.13-141562.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__is_32bit$next[0:0]$6383 - attribute \src "libresoc.v:139934.7-139934.30" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_32bit$next[0:0]$6431 + attribute \src "libresoc.v:141566.7-141566.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__is_signed$next[0:0]$6384 - attribute \src "libresoc.v:139938.7-139938.31" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_signed$next[0:0]$6432 + attribute \src "libresoc.v:141570.7-141570.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6385 - attribute \src "libresoc.v:139947.13-139947.37" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 + attribute \src "libresoc.v:141579.13-141579.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__oe__oe$next[0:0]$6386 - attribute \src "libresoc.v:139951.7-139951.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__oe$next[0:0]$6434 + attribute \src "libresoc.v:141583.7-141583.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__oe__ok$next[0:0]$6387 - attribute \src "libresoc.v:139955.7-139955.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__ok$next[0:0]$6435 + attribute \src "libresoc.v:141587.7-141587.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__rc__ok$next[0:0]$6388 - attribute \src "libresoc.v:139959.7-139959.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__ok$next[0:0]$6436 + attribute \src "libresoc.v:141591.7-141591.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__rc__rc$next[0:0]$6389 - attribute \src "libresoc.v:139963.7-139963.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__rc$next[0:0]$6437 + attribute \src "libresoc.v:141595.7-141595.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__sign_extend$next[0:0]$6390 - attribute \src "libresoc.v:139967.7-139967.33" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__sign_extend$next[0:0]$6438 + attribute \src "libresoc.v:141599.7-141599.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__zero_a$next[0:0]$6391 - attribute \src "libresoc.v:139971.7-139971.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__zero_a$next[0:0]$6439 + attribute \src "libresoc.v:141603.7-141603.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:139975.7-139975.21" + attribute \src "libresoc.v:141607.7-141607.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:140557.3-140568.6" + attribute \src "libresoc.v:142189.3-142200.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:140330.3-140338.6" - wire width 3 $1\src_l_r_src$next[2:0]$6340 - attribute \src "libresoc.v:140017.13-140017.31" + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141649.13-141649.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:140321.3-140329.6" - wire width 3 $1\src_l_s_src$next[2:0]$6337 - attribute \src "libresoc.v:140021.13-140021.31" + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141653.13-141653.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $1\src_r0$next[63:0]$6419 - attribute \src "libresoc.v:140025.14-140025.43" + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $1\src_r0$next[63:0]$6467 + attribute \src "libresoc.v:141657.14-141657.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $1\src_r1$next[63:0]$6423 - attribute \src "libresoc.v:140029.14-140029.43" + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $1\src_r1$next[63:0]$6471 + attribute \src "libresoc.v:141661.14-141661.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $1\src_r2$next[63:0]$6427 - attribute \src "libresoc.v:140033.14-140033.43" + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $1\src_r2$next[63:0]$6475 + attribute \src "libresoc.v:141665.14-141665.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:140375.3-140383.6" - wire $1\sto_l_r_sto$next[0:0]$6355 - attribute \src "libresoc.v:140043.7-140043.25" + attribute \src "libresoc.v:142007.3-142015.6" + wire $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:141675.7-141675.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:140366.3-140374.6" - wire $1\upd_l_r_upd$next[0:0]$6352 - attribute \src "libresoc.v:140053.7-140053.25" + attribute \src "libresoc.v:141998.3-142006.6" + wire $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141685.7-141685.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:140357.3-140365.6" - wire $1\upd_l_s_upd$next[0:0]$6349 - attribute \src "libresoc.v:140057.7-140057.25" + attribute \src "libresoc.v:141989.3-141997.6" + wire $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141689.7-141689.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:140348.3-140356.6" - wire $1\wri_l_r_wri$next[0:0]$6346 - attribute \src "libresoc.v:140067.7-140067.25" + attribute \src "libresoc.v:141980.3-141988.6" + wire $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141699.7-141699.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__byte_reverse$next[0:0]$6392 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6393 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $2\oper_r__fn_unit$next[13:0]$6394 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6395 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6396 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $2\oper_r__insn$next[31:0]$6397 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6398 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__is_32bit$next[0:0]$6399 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__is_signed$next[0:0]$6400 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6401 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__oe__oe$next[0:0]$6402 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__oe__ok$next[0:0]$6403 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__rc__ok$next[0:0]$6404 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__rc__rc$next[0:0]$6405 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__sign_extend$next[0:0]$6406 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__zero_a$next[0:0]$6407 - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $2\src_r0$next[63:0]$6420 - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $2\src_r1$next[63:0]$6424 - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $2\src_r2$next[63:0]$6428 - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__byte_reverse$next[0:0]$6440 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6441 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6444 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $2\oper_r__insn$next[31:0]$6445 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6446 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_32bit$next[0:0]$6447 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_signed$next[0:0]$6448 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__oe$next[0:0]$6450 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__ok$next[0:0]$6451 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__ok$next[0:0]$6452 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__rc$next[0:0]$6453 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__sign_extend$next[0:0]$6454 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__zero_a$next[0:0]$6455 + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6408 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6409 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__oe__oe$next[0:0]$6410 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__oe__ok$next[0:0]$6411 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__rc__ok$next[0:0]$6412 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__rc__rc$next[0:0]$6413 - attribute \src "libresoc.v:140149.18-140149.124" - wire width 65 $add$libresoc.v:140149$6280_Y - attribute \src "libresoc.v:140072.19-140072.118" - wire $and$libresoc.v:140072$6200_Y - attribute \src "libresoc.v:140073.19-140073.125" - wire $and$libresoc.v:140073$6201_Y - attribute \src "libresoc.v:140074.19-140074.120" - wire $and$libresoc.v:140074$6202_Y - attribute \src "libresoc.v:140075.19-140075.125" - wire $and$libresoc.v:140075$6203_Y - attribute \src "libresoc.v:140076.19-140076.118" - wire $and$libresoc.v:140076$6204_Y - attribute \src "libresoc.v:140078.19-140078.119" - wire $and$libresoc.v:140078$6206_Y - attribute \src "libresoc.v:140079.19-140079.123" - wire $and$libresoc.v:140079$6207_Y - attribute \src "libresoc.v:140080.19-140080.123" - wire $and$libresoc.v:140080$6208_Y - attribute \src "libresoc.v:140081.19-140081.120" - wire $and$libresoc.v:140081$6209_Y - attribute \src "libresoc.v:140082.19-140082.123" - wire $and$libresoc.v:140082$6210_Y - attribute \src "libresoc.v:140083.19-140083.119" - wire $and$libresoc.v:140083$6211_Y - attribute \src "libresoc.v:140084.19-140084.123" - wire $and$libresoc.v:140084$6212_Y - attribute \src "libresoc.v:140085.19-140085.125" - wire $and$libresoc.v:140085$6213_Y - attribute \src "libresoc.v:140087.19-140087.116" - wire $and$libresoc.v:140087$6215_Y - attribute \src "libresoc.v:140089.19-140089.120" - wire $and$libresoc.v:140089$6217_Y - attribute \src "libresoc.v:140090.19-140090.123" - wire $and$libresoc.v:140090$6218_Y - attribute \src "libresoc.v:140094.19-140094.125" - wire $and$libresoc.v:140094$6222_Y - attribute \src "libresoc.v:140095.19-140095.123" - wire $and$libresoc.v:140095$6223_Y - attribute \src "libresoc.v:140100.19-140100.116" - wire $and$libresoc.v:140100$6228_Y - attribute \src "libresoc.v:140102.19-140102.116" - wire $and$libresoc.v:140102$6230_Y - attribute \src "libresoc.v:140105.19-140105.118" - wire $and$libresoc.v:140105$6233_Y - attribute \src "libresoc.v:140107.19-140107.125" - wire $and$libresoc.v:140107$6235_Y - attribute \src "libresoc.v:140110.19-140110.160" - wire width 3 $and$libresoc.v:140110$6238_Y - attribute \src "libresoc.v:140111.19-140111.122" - wire $and$libresoc.v:140111$6239_Y - attribute \src "libresoc.v:140112.19-140112.122" - wire $and$libresoc.v:140112$6240_Y - attribute \src "libresoc.v:140114.19-140114.122" - wire $and$libresoc.v:140114$6243_Y - attribute \src "libresoc.v:140126.18-140126.123" - wire $and$libresoc.v:140126$6257_Y - attribute \src "libresoc.v:140127.18-140127.123" - wire $and$libresoc.v:140127$6258_Y - attribute \src "libresoc.v:140129.18-140129.114" - wire $and$libresoc.v:140129$6260_Y - attribute \src "libresoc.v:140131.18-140131.113" - wire $and$libresoc.v:140131$6262_Y - attribute \src "libresoc.v:140134.18-140134.113" - wire $and$libresoc.v:140134$6265_Y - attribute \src "libresoc.v:140138.18-140138.113" - wire $and$libresoc.v:140138$6269_Y - attribute \src "libresoc.v:140141.18-140141.119" - wire $and$libresoc.v:140141$6272_Y - attribute \src "libresoc.v:140150.18-140150.150" - wire width 3 $and$libresoc.v:140150$6281_Y - attribute \src "libresoc.v:140152.18-140152.113" - wire width 3 $and$libresoc.v:140152$6283_Y - attribute \src "libresoc.v:140154.18-140154.113" - wire width 3 $and$libresoc.v:140154$6285_Y - attribute \src "libresoc.v:140155.18-140155.127" - wire $and$libresoc.v:140155$6286_Y - attribute \src "libresoc.v:140156.18-140156.117" - wire $and$libresoc.v:140156$6287_Y - attribute \src "libresoc.v:140161.18-140161.117" - wire $and$libresoc.v:140161$6292_Y - attribute \src "libresoc.v:140086.19-140086.127" - wire $eq$libresoc.v:140086$6214_Y - attribute \src "libresoc.v:140106.19-140106.127" - wire $eq$libresoc.v:140106$6234_Y - attribute \src "libresoc.v:140108.19-140108.127" - wire $eq$libresoc.v:140108$6236_Y - attribute \src "libresoc.v:140119.19-140119.126" - wire $eq$libresoc.v:140119$6249_Y - attribute \src "libresoc.v:140124.18-140124.127" - wire $eq$libresoc.v:140124$6255_Y - attribute \src "libresoc.v:140125.18-140125.127" - wire $eq$libresoc.v:140125$6256_Y - attribute \src "libresoc.v:140133.18-140133.126" - wire $eq$libresoc.v:140133$6264_Y - attribute \src "libresoc.v:140137.18-140137.126" - wire $eq$libresoc.v:140137$6268_Y - attribute \src "libresoc.v:140113.19-140113.110" - wire width 96 $extend$libresoc.v:140113$6241_Y - attribute \src "libresoc.v:140115.19-140115.116" - wire width 64 $extend$libresoc.v:140115$6244_Y - attribute \src "libresoc.v:140120.19-140120.102" - wire width 64 $extend$libresoc.v:140120$6250_Y - attribute \src "libresoc.v:140098.19-140098.109" - wire $not$libresoc.v:140098$6226_Y - attribute \src "libresoc.v:140103.19-140103.121" - wire $not$libresoc.v:140103$6231_Y - attribute \src "libresoc.v:140128.18-140128.112" - wire $not$libresoc.v:140128$6259_Y - attribute \src "libresoc.v:140130.18-140130.110" - wire $not$libresoc.v:140130$6261_Y - attribute \src "libresoc.v:140132.18-140132.120" - wire $not$libresoc.v:140132$6263_Y - attribute \src "libresoc.v:140136.18-140136.120" - wire $not$libresoc.v:140136$6267_Y - attribute \src "libresoc.v:140151.18-140151.143" - wire width 2 $not$libresoc.v:140151$6282_Y - attribute \src "libresoc.v:140153.18-140153.115" - wire width 3 $not$libresoc.v:140153$6284_Y - attribute \src "libresoc.v:140160.18-140160.107" - wire $not$libresoc.v:140160$6291_Y - attribute \src "libresoc.v:140162.18-140162.118" - wire $not$libresoc.v:140162$6293_Y - attribute \src "libresoc.v:140077.18-140077.124" - wire $or$libresoc.v:140077$6205_Y - attribute \src "libresoc.v:140088.18-140088.129" - wire $or$libresoc.v:140088$6216_Y - attribute \src "libresoc.v:140091.19-140091.123" - wire $or$libresoc.v:140091$6219_Y - attribute \src "libresoc.v:140092.19-140092.125" - wire $or$libresoc.v:140092$6220_Y - attribute \src "libresoc.v:140093.19-140093.125" - wire $or$libresoc.v:140093$6221_Y - attribute \src "libresoc.v:140096.19-140096.132" - wire $or$libresoc.v:140096$6224_Y - attribute \src "libresoc.v:140097.19-140097.126" - wire $or$libresoc.v:140097$6225_Y - attribute \src "libresoc.v:140099.18-140099.129" - wire $or$libresoc.v:140099$6227_Y - attribute \src "libresoc.v:140101.19-140101.125" - wire $or$libresoc.v:140101$6229_Y - attribute \src "libresoc.v:140104.19-140104.119" - wire $or$libresoc.v:140104$6232_Y - attribute \src "libresoc.v:140109.18-140109.126" - wire $or$libresoc.v:140109$6237_Y - attribute \src "libresoc.v:140117.18-140117.156" - wire width 3 $or$libresoc.v:140117$6247_Y - attribute \src "libresoc.v:140123.18-140123.126" - wire $or$libresoc.v:140123$6254_Y - attribute \src "libresoc.v:140135.18-140135.116" - wire $or$libresoc.v:140135$6266_Y - attribute \src "libresoc.v:140139.18-140139.116" - wire $or$libresoc.v:140139$6270_Y - attribute \src "libresoc.v:140140.18-140140.127" - wire width 2 $or$libresoc.v:140140$6271_Y - attribute \src "libresoc.v:140142.18-140142.118" - wire $or$libresoc.v:140142$6273_Y - attribute \src "libresoc.v:140143.18-140143.118" - wire $or$libresoc.v:140143$6274_Y - attribute \src "libresoc.v:140144.18-140144.114" - wire $or$libresoc.v:140144$6275_Y - attribute \src "libresoc.v:140157.17-140157.124" - wire $or$libresoc.v:140157$6288_Y - attribute \src "libresoc.v:140158.18-140158.132" - wire $or$libresoc.v:140158$6289_Y - attribute \src "libresoc.v:140159.18-140159.134" - wire $or$libresoc.v:140159$6290_Y - attribute \src "libresoc.v:140113.19-140113.110" - wire width 96 $pos$libresoc.v:140113$6242_Y - attribute \src "libresoc.v:140115.19-140115.116" - wire width 64 $pos$libresoc.v:140115$6245_Y - attribute \src "libresoc.v:140116.19-140116.148" - wire width 64 $pos$libresoc.v:140116$6246_Y - attribute \src "libresoc.v:140118.19-140118.206" - wire width 64 $pos$libresoc.v:140118$6248_Y - attribute \src "libresoc.v:140120.19-140120.102" - wire width 64 $pos$libresoc.v:140120$6251_Y - attribute \src "libresoc.v:140121.19-140121.120" - wire width 64 $pos$libresoc.v:140121$6252_Y - attribute \src "libresoc.v:140122.19-140122.150" - wire width 64 $pos$libresoc.v:140122$6253_Y - attribute \src "libresoc.v:140145.18-140145.107" - wire width 64 $ternary$libresoc.v:140145$6276_Y - attribute \src "libresoc.v:140146.18-140146.112" - wire width 64 $ternary$libresoc.v:140146$6277_Y - attribute \src "libresoc.v:140147.18-140147.147" - wire width 64 $ternary$libresoc.v:140147$6278_Y - attribute \src "libresoc.v:140148.18-140148.155" - wire width 64 $ternary$libresoc.v:140148$6279_Y + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6457 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__oe$next[0:0]$6458 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__ok$next[0:0]$6459 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__ok$next[0:0]$6460 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:141781.18-141781.124" + wire width 65 $add$libresoc.v:141781$6328_Y + attribute \src "libresoc.v:141704.19-141704.118" + wire $and$libresoc.v:141704$6248_Y + attribute \src "libresoc.v:141705.19-141705.125" + wire $and$libresoc.v:141705$6249_Y + attribute \src "libresoc.v:141706.19-141706.120" + wire $and$libresoc.v:141706$6250_Y + attribute \src "libresoc.v:141707.19-141707.125" + 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$or$libresoc.v:141790$6337_Y + attribute \src "libresoc.v:141791.18-141791.134" + wire $or$libresoc.v:141791$6338_Y + attribute \src "libresoc.v:141745.19-141745.110" + wire width 96 $pos$libresoc.v:141745$6290_Y + attribute \src "libresoc.v:141747.19-141747.116" + wire width 64 $pos$libresoc.v:141747$6293_Y + attribute \src "libresoc.v:141748.19-141748.148" + wire width 64 $pos$libresoc.v:141748$6294_Y + attribute \src "libresoc.v:141750.19-141750.206" + wire width 64 $pos$libresoc.v:141750$6296_Y + attribute \src "libresoc.v:141752.19-141752.102" + wire width 64 $pos$libresoc.v:141752$6299_Y + attribute \src "libresoc.v:141753.19-141753.120" + wire width 64 $pos$libresoc.v:141753$6300_Y + attribute \src "libresoc.v:141754.19-141754.150" + wire width 64 $pos$libresoc.v:141754$6301_Y + attribute \src "libresoc.v:141777.18-141777.107" + wire width 64 $ternary$libresoc.v:141777$6324_Y + attribute \src "libresoc.v:141778.18-141778.112" + wire width 64 $ternary$libresoc.v:141778$6325_Y + attribute \src "libresoc.v:141779.18-141779.147" + wire width 64 $ternary$libresoc.v:141779$6326_Y + attribute \src "libresoc.v:141780.18-141780.155" + wire width 64 $ternary$libresoc.v:141780$6327_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -224226,9 +226723,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -224286,7 +226783,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:139322.7-139322.15" + attribute \src "libresoc.v:140954.7-140954.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -224761,7 +227258,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:140149$6280 + cell $add $add$libresoc.v:141781$6328 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -224769,10 +227266,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:140149$6280_Y + connect \Y $add$libresoc.v:141781$6328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:140072$6200 + cell $and $and$libresoc.v:141704$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224780,10 +227277,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:140072$6200_Y + connect \Y $and$libresoc.v:141704$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:140073$6201 + cell $and $and$libresoc.v:141705$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224791,10 +227288,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:140073$6201_Y + connect \Y $and$libresoc.v:141705$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:140074$6202 + cell $and $and$libresoc.v:141706$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224802,10 +227299,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140074$6202_Y + connect \Y $and$libresoc.v:141706$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140075$6203 + cell $and $and$libresoc.v:141707$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224813,10 +227310,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:140075$6203_Y + connect \Y $and$libresoc.v:141707$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140076$6204 + cell $and $and$libresoc.v:141708$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224824,10 +227321,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:140076$6204_Y + connect \Y $and$libresoc.v:141708$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140078$6206 + cell $and $and$libresoc.v:141710$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224835,10 +227332,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:140078$6206_Y + connect \Y $and$libresoc.v:141710$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:140079$6207 + cell $and $and$libresoc.v:141711$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224846,10 +227343,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140079$6207_Y + connect \Y $and$libresoc.v:141711$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140080$6208 + cell $and $and$libresoc.v:141712$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224857,10 +227354,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:140080$6208_Y + connect \Y $and$libresoc.v:141712$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140081$6209 + cell $and $and$libresoc.v:141713$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224868,10 +227365,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140081$6209_Y + connect \Y $and$libresoc.v:141713$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140082$6210 + cell $and $and$libresoc.v:141714$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224879,10 +227376,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:140082$6210_Y + connect \Y $and$libresoc.v:141714$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140083$6211 + cell $and $and$libresoc.v:141715$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224890,10 +227387,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:140083$6211_Y + connect \Y $and$libresoc.v:141715$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140084$6212 + cell $and $and$libresoc.v:141716$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224901,10 +227398,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140084$6212_Y + connect \Y $and$libresoc.v:141716$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140085$6213 + cell $and $and$libresoc.v:141717$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224912,10 +227409,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:140085$6213_Y + connect \Y $and$libresoc.v:141717$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140087$6215 + cell $and $and$libresoc.v:141719$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224923,10 +227420,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:140087$6215_Y + connect \Y $and$libresoc.v:141719$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140089$6217 + cell $and $and$libresoc.v:141721$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224934,10 +227431,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:140089$6217_Y + connect \Y $and$libresoc.v:141721$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140090$6218 + cell $and $and$libresoc.v:141722$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224945,10 +227442,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140090$6218_Y + connect \Y $and$libresoc.v:141722$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140094$6222 + cell $and $and$libresoc.v:141726$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224956,10 +227453,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:140094$6222_Y + connect \Y $and$libresoc.v:141726$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140095$6223 + cell $and $and$libresoc.v:141727$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224967,10 +227464,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140095$6223_Y + connect \Y $and$libresoc.v:141727$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140100$6228 + cell $and $and$libresoc.v:141732$6276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224978,10 +227475,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:140100$6228_Y + connect \Y $and$libresoc.v:141732$6276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:140102$6230 + cell $and $and$libresoc.v:141734$6278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224989,10 +227486,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:140102$6230_Y + connect \Y $and$libresoc.v:141734$6278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:140105$6233 + cell $and $and$libresoc.v:141737$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225000,10 +227497,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:140105$6233_Y + connect \Y $and$libresoc.v:141737$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:140107$6235 + cell $and $and$libresoc.v:141739$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225011,10 +227508,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:140107$6235_Y + connect \Y $and$libresoc.v:141739$6283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:140110$6238 + cell $and $and$libresoc.v:141742$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225022,10 +227519,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:140110$6238_Y + connect \Y $and$libresoc.v:141742$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:140111$6239 + cell $and $and$libresoc.v:141743$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225033,10 +227530,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:140111$6239_Y + connect \Y $and$libresoc.v:141743$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:140112$6240 + cell $and $and$libresoc.v:141744$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225044,10 +227541,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:140112$6240_Y + connect \Y $and$libresoc.v:141744$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:140114$6243 + cell $and $and$libresoc.v:141746$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225055,10 +227552,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:140114$6243_Y + connect \Y $and$libresoc.v:141746$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:140126$6257 + cell $and $and$libresoc.v:141758$6305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225066,10 +227563,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:140126$6257_Y + connect \Y $and$libresoc.v:141758$6305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:140127$6258 + cell $and $and$libresoc.v:141759$6306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225077,10 +227574,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:140127$6258_Y + connect \Y $and$libresoc.v:141759$6306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:140129$6260 + cell $and $and$libresoc.v:141761$6308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225088,10 +227585,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:140129$6260_Y + connect \Y $and$libresoc.v:141761$6308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:140131$6262 + cell $and $and$libresoc.v:141763$6310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225099,10 +227596,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:140131$6262_Y + connect \Y $and$libresoc.v:141763$6310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:140134$6265 + cell $and $and$libresoc.v:141766$6313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225110,10 +227607,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:140134$6265_Y + connect \Y $and$libresoc.v:141766$6313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:140138$6269 + cell $and $and$libresoc.v:141770$6317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225121,10 +227618,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:140138$6269_Y + connect \Y $and$libresoc.v:141770$6317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:140141$6272 + cell $and $and$libresoc.v:141773$6320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225132,10 +227629,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:140141$6272_Y + connect \Y $and$libresoc.v:141773$6320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140150$6281 + cell $and $and$libresoc.v:141782$6329 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225143,10 +227640,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140150$6281_Y + connect \Y $and$libresoc.v:141782$6329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140152$6283 + cell $and $and$libresoc.v:141784$6331 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225154,10 +227651,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:140152$6283_Y + connect \Y $and$libresoc.v:141784$6331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140154$6285 + cell $and $and$libresoc.v:141786$6333 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225165,10 +227662,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:140154$6285_Y + connect \Y $and$libresoc.v:141786$6333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:140155$6286 + cell $and $and$libresoc.v:141787$6334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225176,10 +227673,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140155$6286_Y + connect \Y $and$libresoc.v:141787$6334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:140156$6287 + cell $and $and$libresoc.v:141788$6335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225187,10 +227684,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:140156$6287_Y + connect \Y $and$libresoc.v:141788$6335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:140161$6292 + cell $and $and$libresoc.v:141793$6340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225198,10 +227695,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:140161$6292_Y + connect \Y $and$libresoc.v:141793$6340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140086$6214 + cell $eq $eq$libresoc.v:141718$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225209,10 +227706,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140086$6214_Y + connect \Y $eq$libresoc.v:141718$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140106$6234 + cell $eq $eq$libresoc.v:141738$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225220,10 +227717,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140106$6234_Y + connect \Y $eq$libresoc.v:141738$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140108$6236 + cell $eq $eq$libresoc.v:141740$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225231,10 +227728,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140108$6236_Y + connect \Y $eq$libresoc.v:141740$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:140119$6249 + cell $eq $eq$libresoc.v:141751$6297 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -225242,10 +227739,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:140119$6249_Y + connect \Y $eq$libresoc.v:141751$6297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:140124$6255 + cell $eq $eq$libresoc.v:141756$6303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225253,10 +227750,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:140124$6255_Y + connect \Y $eq$libresoc.v:141756$6303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:140125$6256 + cell $eq $eq$libresoc.v:141757$6304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225264,10 +227761,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:140125$6256_Y + connect \Y $eq$libresoc.v:141757$6304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140133$6264 + cell $eq $eq$libresoc.v:141765$6312 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225275,10 +227772,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140133$6264_Y + connect \Y $eq$libresoc.v:141765$6312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140137$6268 + cell $eq $eq$libresoc.v:141769$6316 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225286,114 +227783,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140137$6268_Y + connect \Y $eq$libresoc.v:141769$6316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:140113$6241 + cell $pos $extend$libresoc.v:141745$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:140113$6241_Y + connect \Y $extend$libresoc.v:141745$6289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:140115$6244 + cell $pos $extend$libresoc.v:141747$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:140115$6244_Y + connect \Y $extend$libresoc.v:141747$6292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:140120$6250 + cell $pos $extend$libresoc.v:141752$6298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:140120$6250_Y + connect \Y $extend$libresoc.v:141752$6298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:140098$6226 + cell $not $not$libresoc.v:141730$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:140098$6226_Y + connect \Y $not$libresoc.v:141730$6274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:140103$6231 + cell $not $not$libresoc.v:141735$6279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140103$6231_Y + connect \Y $not$libresoc.v:141735$6279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:140128$6259 + cell $not $not$libresoc.v:141760$6307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:140128$6259_Y + connect \Y $not$libresoc.v:141760$6307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:140130$6261 + cell $not $not$libresoc.v:141762$6309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:140130$6261_Y + connect \Y $not$libresoc.v:141762$6309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:140132$6263 + cell $not $not$libresoc.v:141764$6311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140132$6263_Y + connect \Y $not$libresoc.v:141764$6311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:140136$6267 + cell $not $not$libresoc.v:141768$6315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140136$6267_Y + connect \Y $not$libresoc.v:141768$6315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:140151$6282 + cell $not $not$libresoc.v:141783$6330 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:140151$6282_Y + connect \Y $not$libresoc.v:141783$6330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:140153$6284 + cell $not $not$libresoc.v:141785$6332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:140153$6284_Y + connect \Y $not$libresoc.v:141785$6332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:140160$6291 + cell $not $not$libresoc.v:141792$6339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:140160$6291_Y + connect \Y $not$libresoc.v:141792$6339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:140162$6293 + cell $not $not$libresoc.v:141794$6341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:140162$6293_Y + connect \Y $not$libresoc.v:141794$6341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:140077$6205 + cell $or $or$libresoc.v:141709$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225401,10 +227898,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140077$6205_Y + connect \Y $or$libresoc.v:141709$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:140088$6216 + cell $or $or$libresoc.v:141720$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225412,10 +227909,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140088$6216_Y + connect \Y $or$libresoc.v:141720$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140091$6219 + cell $or $or$libresoc.v:141723$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225423,10 +227920,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:140091$6219_Y + connect \Y $or$libresoc.v:141723$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140092$6220 + cell $or $or$libresoc.v:141724$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225434,10 +227931,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:140092$6220_Y + connect \Y $or$libresoc.v:141724$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140093$6221 + cell $or $or$libresoc.v:141725$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225445,10 +227942,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:140093$6221_Y + connect \Y $or$libresoc.v:141725$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:140096$6224 + cell $or $or$libresoc.v:141728$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225456,10 +227953,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:140096$6224_Y + connect \Y $or$libresoc.v:141728$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:140097$6225 + cell $or $or$libresoc.v:141729$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225467,10 +227964,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:140097$6225_Y + connect \Y $or$libresoc.v:141729$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:140099$6227 + cell $or $or$libresoc.v:141731$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225478,10 +227975,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140099$6227_Y + connect \Y $or$libresoc.v:141731$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:140101$6229 + cell $or $or$libresoc.v:141733$6277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225489,10 +227986,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:140101$6229_Y + connect \Y $or$libresoc.v:141733$6277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:140104$6232 + cell $or $or$libresoc.v:141736$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225500,10 +227997,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:140104$6232_Y + connect \Y $or$libresoc.v:141736$6280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:140109$6237 + cell $or $or$libresoc.v:141741$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225511,10 +228008,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140109$6237_Y + connect \Y $or$libresoc.v:141741$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:140117$6247 + cell $or $or$libresoc.v:141749$6295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225522,10 +228019,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140117$6247_Y + connect \Y $or$libresoc.v:141749$6295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:140123$6254 + cell $or $or$libresoc.v:141755$6302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225533,10 +228030,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140123$6254_Y + connect \Y $or$libresoc.v:141755$6302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:140135$6266 + cell $or $or$libresoc.v:141767$6314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225544,10 +228041,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:140135$6266_Y + connect \Y $or$libresoc.v:141767$6314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:140139$6270 + cell $or $or$libresoc.v:141771$6318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225555,10 +228052,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:140139$6270_Y + connect \Y $or$libresoc.v:141771$6318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:140140$6271 + cell $or $or$libresoc.v:141772$6319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225566,10 +228063,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:140140$6271_Y + connect \Y $or$libresoc.v:141772$6319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:140142$6273 + cell $or $or$libresoc.v:141774$6321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225577,10 +228074,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:140142$6273_Y + connect \Y $or$libresoc.v:141774$6321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:140143$6274 + cell $or $or$libresoc.v:141775$6322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225588,10 +228085,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:140143$6274_Y + connect \Y $or$libresoc.v:141775$6322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:140144$6275 + cell $or $or$libresoc.v:141776$6323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225599,10 +228096,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:140144$6275_Y + connect \Y $or$libresoc.v:141776$6323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:140157$6288 + cell $or $or$libresoc.v:141789$6336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225610,10 +228107,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140157$6288_Y + connect \Y $or$libresoc.v:141789$6336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:140158$6289 + cell $or $or$libresoc.v:141790$6337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225621,10 +228118,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:140158$6289_Y + connect \Y $or$libresoc.v:141790$6337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:140159$6290 + cell $or $or$libresoc.v:141791$6338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225632,98 +228129,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:140159$6290_Y + connect \Y $or$libresoc.v:141791$6338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:140113$6242 + cell $pos $pos$libresoc.v:141745$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:140113$6241_Y - connect \Y $pos$libresoc.v:140113$6242_Y + connect \A $extend$libresoc.v:141745$6289_Y + connect \Y $pos$libresoc.v:141745$6290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140115$6245 + cell $pos $pos$libresoc.v:141747$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:140115$6244_Y - connect \Y $pos$libresoc.v:140115$6245_Y + connect \A $extend$libresoc.v:141747$6292_Y + connect \Y $pos$libresoc.v:141747$6293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140116$6246 + cell $pos $pos$libresoc.v:141748$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:140116$6246_Y + connect \Y $pos$libresoc.v:141748$6294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140118$6248 + cell $pos $pos$libresoc.v:141750$6296 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:140118$6248_Y + connect \Y $pos$libresoc.v:141750$6296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140120$6251 + cell $pos $pos$libresoc.v:141752$6299 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:140120$6250_Y - connect \Y $pos$libresoc.v:140120$6251_Y + connect \A $extend$libresoc.v:141752$6298_Y + connect \Y $pos$libresoc.v:141752$6299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140121$6252 + cell $pos $pos$libresoc.v:141753$6300 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:140121$6252_Y + connect \Y $pos$libresoc.v:141753$6300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140122$6253 + cell $pos $pos$libresoc.v:141754$6301 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:140122$6253_Y + connect \Y $pos$libresoc.v:141754$6301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140145$6276 + cell $mux $ternary$libresoc.v:141777$6324 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:140145$6276_Y + connect \Y $ternary$libresoc.v:141777$6324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140146$6277 + cell $mux $ternary$libresoc.v:141778$6325 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:140146$6277_Y + connect \Y $ternary$libresoc.v:141778$6325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:140147$6278 + cell $mux $ternary$libresoc.v:141779$6326 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:140147$6278_Y + connect \Y $ternary$libresoc.v:141779$6326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:140148$6279 + cell $mux $ternary$libresoc.v:141780$6327 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:140148$6279_Y + connect \Y $ternary$libresoc.v:141780$6327_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140233.9-140239.4" + attribute \src "libresoc.v:141865.9-141871.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225732,7 +228229,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:140240.15-140246.4" + attribute \src "libresoc.v:141872.15-141878.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225741,7 +228238,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:140247.9-140253.4" + attribute \src "libresoc.v:141879.9-141885.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225750,7 +228247,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:140254.9-140260.4" + attribute \src "libresoc.v:141886.9-141892.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225759,7 +228256,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:140261.15-140267.4" + attribute \src "libresoc.v:141893.15-141899.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225768,7 +228265,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:140268.15-140274.4" + attribute \src "libresoc.v:141900.15-141906.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225777,7 +228274,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:140275.15-140281.4" + attribute \src "libresoc.v:141907.15-141913.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225786,7 +228283,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:140282.9-140288.4" + attribute \src "libresoc.v:141914.9-141920.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225795,7 +228292,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:140289.9-140295.4" + attribute \src "libresoc.v:141921.9-141927.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225804,7 +228301,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:140296.9-140302.4" + attribute \src "libresoc.v:141928.9-141934.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225812,547 +228309,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:139322.7-139322.20" - process $proc$libresoc.v:139322$6442 + attribute \src "libresoc.v:140954.7-140954.20" + process $proc$libresoc.v:140954$6490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139518.7-139518.25" - process $proc$libresoc.v:139518$6443 + attribute \src "libresoc.v:141150.7-141150.25" + process $proc$libresoc.v:141150$6491 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:139532.7-139532.20" - process $proc$libresoc.v:139532$6444 + attribute \src "libresoc.v:141164.7-141164.20" + process $proc$libresoc.v:141164$6492 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:139578.14-139578.41" - process $proc$libresoc.v:139578$6445 + attribute \src "libresoc.v:141210.14-141210.41" + process $proc$libresoc.v:141210$6493 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:139608.14-139608.42" - process $proc$libresoc.v:139608$6446 + attribute \src "libresoc.v:141240.14-141240.42" + process $proc$libresoc.v:141240$6494 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:139613.14-139613.62" - process $proc$libresoc.v:139613$6447 + attribute \src "libresoc.v:141245.14-141245.62" + process $proc$libresoc.v:141245$6495 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:139618.7-139618.34" - process $proc$libresoc.v:139618$6448 + attribute \src "libresoc.v:141250.7-141250.34" + process $proc$libresoc.v:141250$6496 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:139667.7-139667.25" - process $proc$libresoc.v:139667$6449 + attribute \src "libresoc.v:141299.7-141299.25" + process $proc$libresoc.v:141299$6497 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:139681.7-139681.25" - process $proc$libresoc.v:139681$6450 + attribute \src "libresoc.v:141313.7-141313.25" + process $proc$libresoc.v:141313$6498 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:139685.7-139685.25" - process $proc$libresoc.v:139685$6451 + attribute \src "libresoc.v:141317.7-141317.25" + process $proc$libresoc.v:141317$6499 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:139816.7-139816.34" - process $proc$libresoc.v:139816$6452 + attribute \src "libresoc.v:141448.7-141448.34" + process $proc$libresoc.v:141448$6500 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:139820.13-139820.36" - process $proc$libresoc.v:139820$6453 + attribute \src "libresoc.v:141452.13-141452.36" + process $proc$libresoc.v:141452$6501 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:139839.14-139839.40" - process $proc$libresoc.v:139839$6454 + attribute \src "libresoc.v:141471.14-141471.40" + process $proc$libresoc.v:141471$6502 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:139843.14-139843.59" - process $proc$libresoc.v:139843$6455 + attribute \src "libresoc.v:141475.14-141475.59" + process $proc$libresoc.v:141475$6503 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:139847.7-139847.34" - process $proc$libresoc.v:139847$6456 + attribute \src "libresoc.v:141479.7-141479.34" + process $proc$libresoc.v:141479$6504 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:139851.14-139851.34" - process $proc$libresoc.v:139851$6457 + attribute \src "libresoc.v:141483.14-141483.34" + process $proc$libresoc.v:141483$6505 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:139930.13-139930.38" - process $proc$libresoc.v:139930$6458 + attribute \src "libresoc.v:141562.13-141562.38" + process $proc$libresoc.v:141562$6506 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:139934.7-139934.30" - process $proc$libresoc.v:139934$6459 + attribute \src "libresoc.v:141566.7-141566.30" + process $proc$libresoc.v:141566$6507 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:139938.7-139938.31" - process $proc$libresoc.v:139938$6460 + attribute \src "libresoc.v:141570.7-141570.31" + process $proc$libresoc.v:141570$6508 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:139947.13-139947.37" - process $proc$libresoc.v:139947$6461 + attribute \src "libresoc.v:141579.13-141579.37" + process $proc$libresoc.v:141579$6509 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:139951.7-139951.28" - process $proc$libresoc.v:139951$6462 + attribute \src "libresoc.v:141583.7-141583.28" + process $proc$libresoc.v:141583$6510 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:139955.7-139955.28" - process $proc$libresoc.v:139955$6463 + attribute \src "libresoc.v:141587.7-141587.28" + process $proc$libresoc.v:141587$6511 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:139959.7-139959.28" - process $proc$libresoc.v:139959$6464 + attribute \src "libresoc.v:141591.7-141591.28" + process $proc$libresoc.v:141591$6512 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:139963.7-139963.28" - process $proc$libresoc.v:139963$6465 + attribute \src "libresoc.v:141595.7-141595.28" + process $proc$libresoc.v:141595$6513 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:139967.7-139967.33" - process $proc$libresoc.v:139967$6466 + attribute \src "libresoc.v:141599.7-141599.33" + process $proc$libresoc.v:141599$6514 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:139971.7-139971.28" - process $proc$libresoc.v:139971$6467 + attribute \src "libresoc.v:141603.7-141603.28" + process $proc$libresoc.v:141603$6515 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:139975.7-139975.21" - process $proc$libresoc.v:139975$6468 + attribute \src "libresoc.v:141607.7-141607.21" + process $proc$libresoc.v:141607$6516 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:140017.13-140017.31" - process $proc$libresoc.v:140017$6469 + attribute \src "libresoc.v:141649.13-141649.31" + process $proc$libresoc.v:141649$6517 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:140021.13-140021.31" - process $proc$libresoc.v:140021$6470 + attribute \src "libresoc.v:141653.13-141653.31" + process $proc$libresoc.v:141653$6518 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:140025.14-140025.43" - process $proc$libresoc.v:140025$6471 + attribute \src "libresoc.v:141657.14-141657.43" + process $proc$libresoc.v:141657$6519 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:140029.14-140029.43" - process $proc$libresoc.v:140029$6472 + attribute \src "libresoc.v:141661.14-141661.43" + process $proc$libresoc.v:141661$6520 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:140033.14-140033.43" - process $proc$libresoc.v:140033$6473 + attribute \src "libresoc.v:141665.14-141665.43" + process $proc$libresoc.v:141665$6521 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:140043.7-140043.25" - process $proc$libresoc.v:140043$6474 + attribute \src "libresoc.v:141675.7-141675.25" + process $proc$libresoc.v:141675$6522 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:140053.7-140053.25" - process $proc$libresoc.v:140053$6475 + attribute \src "libresoc.v:141685.7-141685.25" + process $proc$libresoc.v:141685$6523 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:140057.7-140057.25" - process $proc$libresoc.v:140057$6476 + attribute \src "libresoc.v:141689.7-141689.25" + process $proc$libresoc.v:141689$6524 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:140067.7-140067.25" - process $proc$libresoc.v:140067$6477 + attribute \src "libresoc.v:141699.7-141699.25" + process $proc$libresoc.v:141699$6525 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:140163.3-140164.57" - process $proc$libresoc.v:140163$6294 + attribute \src "libresoc.v:141795.3-141796.57" + process $proc$libresoc.v:141795$6342 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:140165.3-140166.33" - process $proc$libresoc.v:140165$6295 + attribute \src "libresoc.v:141797.3-141798.33" + process $proc$libresoc.v:141797$6343 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:140167.3-140168.21" - process $proc$libresoc.v:140167$6296 + attribute \src "libresoc.v:141799.3-141800.21" + process $proc$libresoc.v:141799$6344 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:140169.3-140170.25" - process $proc$libresoc.v:140169$6297 + attribute \src "libresoc.v:141801.3-141802.25" + process $proc$libresoc.v:141801$6345 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:140171.3-140172.29" - process $proc$libresoc.v:140171$6298 + attribute \src "libresoc.v:141803.3-141804.29" + process $proc$libresoc.v:141803$6346 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:140173.3-140174.29" - process $proc$libresoc.v:140173$6299 + attribute \src "libresoc.v:141805.3-141806.29" + process $proc$libresoc.v:141805$6347 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:140175.3-140176.29" - process $proc$libresoc.v:140175$6300 + attribute \src "libresoc.v:141807.3-141808.29" + process $proc$libresoc.v:141807$6348 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:140177.3-140178.27" - process $proc$libresoc.v:140177$6301 + attribute \src "libresoc.v:141809.3-141810.27" + process $proc$libresoc.v:141809$6349 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:140179.3-140180.51" - process $proc$libresoc.v:140179$6302 + attribute \src "libresoc.v:141811.3-141812.51" + process $proc$libresoc.v:141811$6350 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:140181.3-140182.47" - process $proc$libresoc.v:140181$6303 + attribute \src "libresoc.v:141813.3-141814.47" + process $proc$libresoc.v:141813$6351 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:140183.3-140184.61" - process $proc$libresoc.v:140183$6304 + attribute \src "libresoc.v:141815.3-141816.61" + process $proc$libresoc.v:141815$6352 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:140185.3-140186.57" - process $proc$libresoc.v:140185$6305 + attribute \src "libresoc.v:141817.3-141818.57" + process $proc$libresoc.v:141817$6353 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:140187.3-140188.45" - process $proc$libresoc.v:140187$6306 + attribute \src "libresoc.v:141819.3-141820.45" + process $proc$libresoc.v:141819$6354 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:140189.3-140190.45" - process $proc$libresoc.v:140189$6307 + attribute \src "libresoc.v:141821.3-141822.45" + process $proc$libresoc.v:141821$6355 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:140191.3-140192.45" - process $proc$libresoc.v:140191$6308 + attribute \src "libresoc.v:141823.3-141824.45" + process $proc$libresoc.v:141823$6356 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:140193.3-140194.45" - process $proc$libresoc.v:140193$6309 + attribute \src "libresoc.v:141825.3-141826.45" + process $proc$libresoc.v:141825$6357 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:140195.3-140196.45" - process $proc$libresoc.v:140195$6310 + attribute \src "libresoc.v:141827.3-141828.45" + process $proc$libresoc.v:141827$6358 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:140197.3-140198.49" - process $proc$libresoc.v:140197$6311 + attribute \src "libresoc.v:141829.3-141830.49" + process $proc$libresoc.v:141829$6359 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:140199.3-140200.51" - process $proc$libresoc.v:140199$6312 + attribute \src "libresoc.v:141831.3-141832.51" + process $proc$libresoc.v:141831$6360 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:140201.3-140202.49" - process $proc$libresoc.v:140201$6313 + attribute \src "libresoc.v:141833.3-141834.49" + process $proc$libresoc.v:141833$6361 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:140203.3-140204.57" - process $proc$libresoc.v:140203$6314 + attribute \src "libresoc.v:141835.3-141836.57" + process $proc$libresoc.v:141835$6362 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:140205.3-140206.55" - process $proc$libresoc.v:140205$6315 + attribute \src "libresoc.v:141837.3-141838.55" + process $proc$libresoc.v:141837$6363 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:140207.3-140208.51" - process $proc$libresoc.v:140207$6316 + attribute \src "libresoc.v:141839.3-141840.51" + process $proc$libresoc.v:141839$6364 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:140209.3-140210.41" - process $proc$libresoc.v:140209$6317 + attribute \src "libresoc.v:141841.3-141842.41" + process $proc$libresoc.v:141841$6365 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:140211.3-140212.39" - process $proc$libresoc.v:140211$6318 + attribute \src "libresoc.v:141843.3-141844.39" + process $proc$libresoc.v:141843$6366 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:140213.3-140214.39" - process $proc$libresoc.v:140213$6319 + attribute \src "libresoc.v:141845.3-141846.39" + process $proc$libresoc.v:141845$6367 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:140215.3-140216.39" - process $proc$libresoc.v:140215$6320 + attribute \src "libresoc.v:141847.3-141848.39" + process $proc$libresoc.v:141847$6368 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:140217.3-140218.39" - process $proc$libresoc.v:140217$6321 + attribute \src "libresoc.v:141849.3-141850.39" + process $proc$libresoc.v:141849$6369 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:140219.3-140220.39" - process $proc$libresoc.v:140219$6322 + attribute \src "libresoc.v:141851.3-141852.39" + process $proc$libresoc.v:141851$6370 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:140221.3-140222.39" - process $proc$libresoc.v:140221$6323 + attribute \src "libresoc.v:141853.3-141854.39" + process $proc$libresoc.v:141853$6371 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:140223.3-140224.39" - process $proc$libresoc.v:140223$6324 + attribute \src "libresoc.v:141855.3-141856.39" + process $proc$libresoc.v:141855$6372 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:140225.3-140226.39" - process $proc$libresoc.v:140225$6325 + attribute \src "libresoc.v:141857.3-141858.39" + process $proc$libresoc.v:141857$6373 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:140227.3-140228.39" - process $proc$libresoc.v:140227$6326 + attribute \src "libresoc.v:141859.3-141860.39" + process $proc$libresoc.v:141859$6374 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:140229.3-140230.39" - process $proc$libresoc.v:140229$6327 + attribute \src "libresoc.v:141861.3-141862.39" + process $proc$libresoc.v:141861$6375 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140231.3-140232.28" - process $proc$libresoc.v:140231$6328 + attribute \src "libresoc.v:141863.3-141864.28" + process $proc$libresoc.v:141863$6376 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:140303.3-140311.6" - process $proc$libresoc.v:140303$6329 + attribute \src "libresoc.v:141935.3-141943.6" + process $proc$libresoc.v:141935$6377 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6330 $1\opc_l_s_opc$next[0:0]$6331 - attribute \src "libresoc.v:140304.5-140304.29" + assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141936.5-141936.29" switch \initial - attribute \src "libresoc.v:140304.9-140304.17" + attribute \src "libresoc.v:141936.9-141936.17" case 1'1 case end @@ -226361,21 +228858,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6331 1'0 + assign $1\opc_l_s_opc$next[0:0]$6379 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6331 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6379 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6330 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 end - attribute \src "libresoc.v:140312.3-140320.6" - process $proc$libresoc.v:140312$6332 + attribute \src "libresoc.v:141944.3-141952.6" + process $proc$libresoc.v:141944$6380 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6333 $1\opc_l_r_opc$next[0:0]$6334 - attribute \src "libresoc.v:140313.5-140313.29" + assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141945.5-141945.29" switch \initial - attribute \src "libresoc.v:140313.9-140313.17" + attribute \src "libresoc.v:141945.9-141945.17" case 1'1 case end @@ -226384,21 +228881,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6334 1'1 + assign $1\opc_l_r_opc$next[0:0]$6382 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6334 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6382 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6333 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 end - attribute \src "libresoc.v:140321.3-140329.6" - process $proc$libresoc.v:140321$6335 + attribute \src "libresoc.v:141953.3-141961.6" + process $proc$libresoc.v:141953$6383 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6336 $1\src_l_s_src$next[2:0]$6337 - attribute \src "libresoc.v:140322.5-140322.29" + assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141954.5-141954.29" switch \initial - attribute \src "libresoc.v:140322.9-140322.17" + attribute \src "libresoc.v:141954.9-141954.17" case 1'1 case end @@ -226407,21 +228904,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6337 3'000 + assign $1\src_l_s_src$next[2:0]$6385 3'000 case - assign $1\src_l_s_src$next[2:0]$6337 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6385 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6336 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 end - attribute \src "libresoc.v:140330.3-140338.6" - process $proc$libresoc.v:140330$6338 + attribute \src "libresoc.v:141962.3-141970.6" + process $proc$libresoc.v:141962$6386 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6339 $1\src_l_r_src$next[2:0]$6340 - attribute \src "libresoc.v:140331.5-140331.29" + assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141963.5-141963.29" switch \initial - attribute \src "libresoc.v:140331.9-140331.17" + attribute \src "libresoc.v:141963.9-141963.17" case 1'1 case end @@ -226430,21 +228927,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6340 3'111 + assign $1\src_l_r_src$next[2:0]$6388 3'111 case - assign $1\src_l_r_src$next[2:0]$6340 \reset_r + assign $1\src_l_r_src$next[2:0]$6388 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6339 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 end - attribute \src "libresoc.v:140339.3-140347.6" - process $proc$libresoc.v:140339$6341 + attribute \src "libresoc.v:141971.3-141979.6" + process $proc$libresoc.v:141971$6389 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6342 $1\adr_l_r_adr$next[0:0]$6343 - attribute \src "libresoc.v:140340.5-140340.29" + assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141972.5-141972.29" switch \initial - attribute \src "libresoc.v:140340.9-140340.17" + attribute \src "libresoc.v:141972.9-141972.17" case 1'1 case end @@ -226453,21 +228950,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6343 1'1 + assign $1\adr_l_r_adr$next[0:0]$6391 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6343 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6391 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6342 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 end - attribute \src "libresoc.v:140348.3-140356.6" - process $proc$libresoc.v:140348$6344 + attribute \src "libresoc.v:141980.3-141988.6" + process $proc$libresoc.v:141980$6392 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6345 $1\wri_l_r_wri$next[0:0]$6346 - attribute \src "libresoc.v:140349.5-140349.29" + assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141981.5-141981.29" switch \initial - attribute \src "libresoc.v:140349.9-140349.17" + attribute \src "libresoc.v:141981.9-141981.17" case 1'1 case end @@ -226476,21 +228973,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6346 1'1 + assign $1\wri_l_r_wri$next[0:0]$6394 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6346 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6394 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6345 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 end - attribute \src "libresoc.v:140357.3-140365.6" - process $proc$libresoc.v:140357$6347 + attribute \src "libresoc.v:141989.3-141997.6" + process $proc$libresoc.v:141989$6395 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6348 $1\upd_l_s_upd$next[0:0]$6349 - attribute \src "libresoc.v:140358.5-140358.29" + assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141990.5-141990.29" switch \initial - attribute \src "libresoc.v:140358.9-140358.17" + attribute \src "libresoc.v:141990.9-141990.17" case 1'1 case end @@ -226499,21 +228996,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6349 1'0 + assign $1\upd_l_s_upd$next[0:0]$6397 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6349 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6397 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6348 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 end - attribute \src "libresoc.v:140366.3-140374.6" - process $proc$libresoc.v:140366$6350 + attribute \src "libresoc.v:141998.3-142006.6" + process $proc$libresoc.v:141998$6398 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6351 $1\upd_l_r_upd$next[0:0]$6352 - attribute \src "libresoc.v:140367.5-140367.29" + assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141999.5-141999.29" switch \initial - attribute \src "libresoc.v:140367.9-140367.17" + attribute \src "libresoc.v:141999.9-141999.17" case 1'1 case end @@ -226522,21 +229019,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6352 1'1 + assign $1\upd_l_r_upd$next[0:0]$6400 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6352 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6400 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6351 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 end - attribute \src "libresoc.v:140375.3-140383.6" - process $proc$libresoc.v:140375$6353 + attribute \src "libresoc.v:142007.3-142015.6" + process $proc$libresoc.v:142007$6401 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6354 $1\sto_l_r_sto$next[0:0]$6355 - attribute \src "libresoc.v:140376.5-140376.29" + assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:142008.5-142008.29" switch \initial - attribute \src "libresoc.v:140376.9-140376.17" + attribute \src "libresoc.v:142008.9-142008.17" case 1'1 case end @@ -226545,21 +229042,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6355 1'1 + assign $1\sto_l_r_sto$next[0:0]$6403 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6355 \$59 + assign $1\sto_l_r_sto$next[0:0]$6403 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6354 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 end - attribute \src "libresoc.v:140384.3-140392.6" - process $proc$libresoc.v:140384$6356 + attribute \src "libresoc.v:142016.3-142024.6" + process $proc$libresoc.v:142016$6404 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6357 $1\lsd_l_r_lsd$next[0:0]$6358 - attribute \src "libresoc.v:140385.5-140385.29" + assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:142017.5-142017.29" switch \initial - attribute \src "libresoc.v:140385.9-140385.17" + attribute \src "libresoc.v:142017.9-142017.17" case 1'1 case end @@ -226568,15 +229065,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6358 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6406 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6358 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6406 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6357 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 end - attribute \src "libresoc.v:140393.3-140435.6" - process $proc$libresoc.v:140393$6359 + attribute \src "libresoc.v:142025.3-142067.6" + process $proc$libresoc.v:142025$6407 assign { } { } assign { } { } assign { } { } @@ -226625,31 +229122,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6360 $2\oper_r__byte_reverse$next[0:0]$6392 - assign $0\oper_r__data_len$next[3:0]$6361 $2\oper_r__data_len$next[3:0]$6393 - assign $0\oper_r__fn_unit$next[13:0]$6362 $2\oper_r__fn_unit$next[13:0]$6394 + assign $0\oper_r__byte_reverse$next[0:0]$6408 $2\oper_r__byte_reverse$next[0:0]$6440 + assign $0\oper_r__data_len$next[3:0]$6409 $2\oper_r__data_len$next[3:0]$6441 + assign $0\oper_r__fn_unit$next[13:0]$6410 $2\oper_r__fn_unit$next[13:0]$6442 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6365 $2\oper_r__insn$next[31:0]$6397 - assign $0\oper_r__insn_type$next[6:0]$6366 $2\oper_r__insn_type$next[6:0]$6398 - assign $0\oper_r__is_32bit$next[0:0]$6367 $2\oper_r__is_32bit$next[0:0]$6399 - assign $0\oper_r__is_signed$next[0:0]$6368 $2\oper_r__is_signed$next[0:0]$6400 - assign $0\oper_r__ldst_mode$next[1:0]$6369 $2\oper_r__ldst_mode$next[1:0]$6401 + assign $0\oper_r__insn$next[31:0]$6413 $2\oper_r__insn$next[31:0]$6445 + assign $0\oper_r__insn_type$next[6:0]$6414 $2\oper_r__insn_type$next[6:0]$6446 + assign $0\oper_r__is_32bit$next[0:0]$6415 $2\oper_r__is_32bit$next[0:0]$6447 + assign $0\oper_r__is_signed$next[0:0]$6416 $2\oper_r__is_signed$next[0:0]$6448 + assign $0\oper_r__ldst_mode$next[1:0]$6417 $2\oper_r__ldst_mode$next[1:0]$6449 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6374 $2\oper_r__sign_extend$next[0:0]$6406 - assign $0\oper_r__zero_a$next[0:0]$6375 $2\oper_r__zero_a$next[0:0]$6407 - assign $0\oper_r__imm_data__data$next[63:0]$6363 $3\oper_r__imm_data__data$next[63:0]$6408 - assign $0\oper_r__imm_data__ok$next[0:0]$6364 $3\oper_r__imm_data__ok$next[0:0]$6409 - assign $0\oper_r__oe__oe$next[0:0]$6370 $3\oper_r__oe__oe$next[0:0]$6410 - assign $0\oper_r__oe__ok$next[0:0]$6371 $3\oper_r__oe__ok$next[0:0]$6411 - assign $0\oper_r__rc__ok$next[0:0]$6372 $3\oper_r__rc__ok$next[0:0]$6412 - assign $0\oper_r__rc__rc$next[0:0]$6373 $3\oper_r__rc__rc$next[0:0]$6413 - attribute \src "libresoc.v:140394.5-140394.29" + assign $0\oper_r__sign_extend$next[0:0]$6422 $2\oper_r__sign_extend$next[0:0]$6454 + assign $0\oper_r__zero_a$next[0:0]$6423 $2\oper_r__zero_a$next[0:0]$6455 + assign $0\oper_r__imm_data__data$next[63:0]$6411 $3\oper_r__imm_data__data$next[63:0]$6456 + assign $0\oper_r__imm_data__ok$next[0:0]$6412 $3\oper_r__imm_data__ok$next[0:0]$6457 + assign $0\oper_r__oe__oe$next[0:0]$6418 $3\oper_r__oe__oe$next[0:0]$6458 + assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 + assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 + assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:142026.5-142026.29" switch \initial - attribute \src "libresoc.v:140394.9-140394.17" + attribute \src "libresoc.v:142026.9-142026.17" case 1'1 case end @@ -226673,24 +229170,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6385 $1\oper_r__sign_extend$next[0:0]$6390 $1\oper_r__byte_reverse$next[0:0]$6376 $1\oper_r__data_len$next[3:0]$6377 $1\oper_r__is_signed$next[0:0]$6384 $1\oper_r__is_32bit$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6387 $1\oper_r__oe__oe$next[0:0]$6386 $1\oper_r__rc__ok$next[0:0]$6388 $1\oper_r__rc__rc$next[0:0]$6389 $1\oper_r__zero_a$next[0:0]$6391 $1\oper_r__imm_data__ok$next[0:0]$6380 $1\oper_r__imm_data__data$next[63:0]$6379 $1\oper_r__fn_unit$next[13:0]$6378 $1\oper_r__insn_type$next[6:0]$6382 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6429 $1\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__data_len$next[3:0]$6425 $1\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__zero_a$next[0:0]$6439 $1\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__insn_type$next[6:0]$6430 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6376 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6377 \oper_r__data_len - assign $1\oper_r__fn_unit$next[13:0]$6378 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6379 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6380 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6381 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6382 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6383 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6384 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6385 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6386 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6387 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6388 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6389 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6390 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6391 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6424 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6425 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6426 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6427 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6428 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6429 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6430 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6431 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6432 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6433 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6434 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6435 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6436 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6437 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6438 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6439 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -226712,24 +229209,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6397 $2\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__data_len$next[3:0]$6393 $2\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__oe__ok$next[0:0]$6403 $2\oper_r__oe__oe$next[0:0]$6402 $2\oper_r__rc__ok$next[0:0]$6404 $2\oper_r__rc__rc$next[0:0]$6405 $2\oper_r__zero_a$next[0:0]$6407 $2\oper_r__imm_data__ok$next[0:0]$6396 $2\oper_r__imm_data__data$next[63:0]$6395 $2\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__insn_type$next[6:0]$6398 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6445 $2\oper_r__ldst_mode$next[1:0]$6449 $2\oper_r__sign_extend$next[0:0]$6454 $2\oper_r__byte_reverse$next[0:0]$6440 $2\oper_r__data_len$next[3:0]$6441 $2\oper_r__is_signed$next[0:0]$6448 $2\oper_r__is_32bit$next[0:0]$6447 $2\oper_r__oe__ok$next[0:0]$6451 $2\oper_r__oe__oe$next[0:0]$6450 $2\oper_r__rc__ok$next[0:0]$6452 $2\oper_r__rc__rc$next[0:0]$6453 $2\oper_r__zero_a$next[0:0]$6455 $2\oper_r__imm_data__ok$next[0:0]$6444 $2\oper_r__imm_data__data$next[63:0]$6443 $2\oper_r__fn_unit$next[13:0]$6442 $2\oper_r__insn_type$next[6:0]$6446 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6392 $1\oper_r__byte_reverse$next[0:0]$6376 - assign $2\oper_r__data_len$next[3:0]$6393 $1\oper_r__data_len$next[3:0]$6377 - assign $2\oper_r__fn_unit$next[13:0]$6394 $1\oper_r__fn_unit$next[13:0]$6378 - assign $2\oper_r__imm_data__data$next[63:0]$6395 $1\oper_r__imm_data__data$next[63:0]$6379 - assign $2\oper_r__imm_data__ok$next[0:0]$6396 $1\oper_r__imm_data__ok$next[0:0]$6380 - assign $2\oper_r__insn$next[31:0]$6397 $1\oper_r__insn$next[31:0]$6381 - assign $2\oper_r__insn_type$next[6:0]$6398 $1\oper_r__insn_type$next[6:0]$6382 - assign $2\oper_r__is_32bit$next[0:0]$6399 $1\oper_r__is_32bit$next[0:0]$6383 - assign $2\oper_r__is_signed$next[0:0]$6400 $1\oper_r__is_signed$next[0:0]$6384 - assign $2\oper_r__ldst_mode$next[1:0]$6401 $1\oper_r__ldst_mode$next[1:0]$6385 - assign $2\oper_r__oe__oe$next[0:0]$6402 $1\oper_r__oe__oe$next[0:0]$6386 - assign $2\oper_r__oe__ok$next[0:0]$6403 $1\oper_r__oe__ok$next[0:0]$6387 - assign $2\oper_r__rc__ok$next[0:0]$6404 $1\oper_r__rc__ok$next[0:0]$6388 - assign $2\oper_r__rc__rc$next[0:0]$6405 $1\oper_r__rc__rc$next[0:0]$6389 - assign $2\oper_r__sign_extend$next[0:0]$6406 $1\oper_r__sign_extend$next[0:0]$6390 - assign $2\oper_r__zero_a$next[0:0]$6407 $1\oper_r__zero_a$next[0:0]$6391 + assign $2\oper_r__byte_reverse$next[0:0]$6440 $1\oper_r__byte_reverse$next[0:0]$6424 + assign $2\oper_r__data_len$next[3:0]$6441 $1\oper_r__data_len$next[3:0]$6425 + assign $2\oper_r__fn_unit$next[13:0]$6442 $1\oper_r__fn_unit$next[13:0]$6426 + assign $2\oper_r__imm_data__data$next[63:0]$6443 $1\oper_r__imm_data__data$next[63:0]$6427 + assign $2\oper_r__imm_data__ok$next[0:0]$6444 $1\oper_r__imm_data__ok$next[0:0]$6428 + assign $2\oper_r__insn$next[31:0]$6445 $1\oper_r__insn$next[31:0]$6429 + assign $2\oper_r__insn_type$next[6:0]$6446 $1\oper_r__insn_type$next[6:0]$6430 + assign $2\oper_r__is_32bit$next[0:0]$6447 $1\oper_r__is_32bit$next[0:0]$6431 + assign $2\oper_r__is_signed$next[0:0]$6448 $1\oper_r__is_signed$next[0:0]$6432 + assign $2\oper_r__ldst_mode$next[1:0]$6449 $1\oper_r__ldst_mode$next[1:0]$6433 + assign $2\oper_r__oe__oe$next[0:0]$6450 $1\oper_r__oe__oe$next[0:0]$6434 + assign $2\oper_r__oe__ok$next[0:0]$6451 $1\oper_r__oe__ok$next[0:0]$6435 + assign $2\oper_r__rc__ok$next[0:0]$6452 $1\oper_r__rc__ok$next[0:0]$6436 + assign $2\oper_r__rc__rc$next[0:0]$6453 $1\oper_r__rc__rc$next[0:0]$6437 + assign $2\oper_r__sign_extend$next[0:0]$6454 $1\oper_r__sign_extend$next[0:0]$6438 + assign $2\oper_r__zero_a$next[0:0]$6455 $1\oper_r__zero_a$next[0:0]$6439 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -226741,46 +229238,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6409 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6413 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6412 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6410 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6411 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6461 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6460 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6458 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6459 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6408 $2\oper_r__imm_data__data$next[63:0]$6395 - assign $3\oper_r__imm_data__ok$next[0:0]$6409 $2\oper_r__imm_data__ok$next[0:0]$6396 - assign $3\oper_r__oe__oe$next[0:0]$6410 $2\oper_r__oe__oe$next[0:0]$6402 - assign $3\oper_r__oe__ok$next[0:0]$6411 $2\oper_r__oe__ok$next[0:0]$6403 - assign $3\oper_r__rc__ok$next[0:0]$6412 $2\oper_r__rc__ok$next[0:0]$6404 - assign $3\oper_r__rc__rc$next[0:0]$6413 $2\oper_r__rc__rc$next[0:0]$6405 + assign $3\oper_r__imm_data__data$next[63:0]$6456 $2\oper_r__imm_data__data$next[63:0]$6443 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 $2\oper_r__imm_data__ok$next[0:0]$6444 + assign $3\oper_r__oe__oe$next[0:0]$6458 $2\oper_r__oe__oe$next[0:0]$6450 + assign $3\oper_r__oe__ok$next[0:0]$6459 $2\oper_r__oe__ok$next[0:0]$6451 + assign $3\oper_r__rc__ok$next[0:0]$6460 $2\oper_r__rc__ok$next[0:0]$6452 + assign $3\oper_r__rc__rc$next[0:0]$6461 $2\oper_r__rc__rc$next[0:0]$6453 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6360 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6361 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6362 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6363 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6364 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6365 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6366 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6367 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6368 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6369 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6370 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6371 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6372 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6373 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6374 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6375 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6408 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6409 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6410 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6411 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6412 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6413 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6414 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6415 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6416 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6417 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6418 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6419 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6420 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6421 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 end - attribute \src "libresoc.v:140436.3-140445.6" - process $proc$libresoc.v:140436$6414 + attribute \src "libresoc.v:142068.3-142077.6" + process $proc$libresoc.v:142068$6462 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6415 $1\ldo_r$next[63:0]$6416 - attribute \src "libresoc.v:140437.5-140437.29" + assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:142069.5-142069.29" switch \initial - attribute \src "libresoc.v:140437.9-140437.17" + attribute \src "libresoc.v:142069.9-142069.17" case 1'1 case end @@ -226789,22 +229286,22 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6416 \ldd_o + assign $1\ldo_r$next[63:0]$6464 \ldd_o case - assign $1\ldo_r$next[63:0]$6416 \ldo_r + assign $1\ldo_r$next[63:0]$6464 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6415 + update \ldo_r$next $0\ldo_r$next[63:0]$6463 end - attribute \src "libresoc.v:140446.3-140461.6" - process $proc$libresoc.v:140446$6417 + attribute \src "libresoc.v:142078.3-142093.6" + process $proc$libresoc.v:142078$6465 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6418 $2\src_r0$next[63:0]$6420 - attribute \src "libresoc.v:140447.5-140447.29" + assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142079.5-142079.29" switch \initial - attribute \src "libresoc.v:140447.9-140447.17" + attribute \src "libresoc.v:142079.9-142079.17" case 1'1 case end @@ -226813,31 +229310,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6419 \src1_i + assign $1\src_r0$next[63:0]$6467 \src1_i case - assign $1\src_r0$next[63:0]$6419 \src_r0 + assign $1\src_r0$next[63:0]$6467 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6420 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6420 $1\src_r0$next[63:0]$6419 + assign $2\src_r0$next[63:0]$6468 $1\src_r0$next[63:0]$6467 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6418 + update \src_r0$next $0\src_r0$next[63:0]$6466 end - attribute \src "libresoc.v:140462.3-140477.6" - process $proc$libresoc.v:140462$6421 + attribute \src "libresoc.v:142094.3-142109.6" + process $proc$libresoc.v:142094$6469 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6422 $2\src_r1$next[63:0]$6424 - attribute \src "libresoc.v:140463.5-140463.29" + assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142095.5-142095.29" switch \initial - attribute \src "libresoc.v:140463.9-140463.17" + attribute \src "libresoc.v:142095.9-142095.17" case 1'1 case end @@ -226846,31 +229343,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6423 \src2_i + assign $1\src_r1$next[63:0]$6471 \src2_i case - assign $1\src_r1$next[63:0]$6423 \src_r1 + assign $1\src_r1$next[63:0]$6471 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6424 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6424 $1\src_r1$next[63:0]$6423 + assign $2\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6471 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6422 + update \src_r1$next $0\src_r1$next[63:0]$6470 end - attribute \src "libresoc.v:140478.3-140493.6" - process $proc$libresoc.v:140478$6425 + attribute \src "libresoc.v:142110.3-142125.6" + process $proc$libresoc.v:142110$6473 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6426 $2\src_r2$next[63:0]$6428 - attribute \src "libresoc.v:140479.5-140479.29" + assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142111.5-142111.29" switch \initial - attribute \src "libresoc.v:140479.9-140479.17" + attribute \src "libresoc.v:142111.9-142111.17" case 1'1 case end @@ -226879,30 +229376,30 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6427 \src3_i + assign $1\src_r2$next[63:0]$6475 \src3_i case - assign $1\src_r2$next[63:0]$6427 \src_r2 + assign $1\src_r2$next[63:0]$6475 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6428 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6476 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6428 $1\src_r2$next[63:0]$6427 + assign $2\src_r2$next[63:0]$6476 $1\src_r2$next[63:0]$6475 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6426 + update \src_r2$next $0\src_r2$next[63:0]$6474 end - attribute \src "libresoc.v:140494.3-140503.6" - process $proc$libresoc.v:140494$6429 + attribute \src "libresoc.v:142126.3-142135.6" + process $proc$libresoc.v:142126$6477 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6430 $1\ea_r$next[63:0]$6431 - attribute \src "libresoc.v:140495.5-140495.29" + assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:142127.5-142127.29" switch \initial - attribute \src "libresoc.v:140495.9-140495.17" + attribute \src "libresoc.v:142127.9-142127.17" case 1'1 case end @@ -226911,21 +229408,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6431 \alu_o + assign $1\ea_r$next[63:0]$6479 \alu_o case - assign $1\ea_r$next[63:0]$6431 \ea_r + assign $1\ea_r$next[63:0]$6479 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6430 + update \ea_r$next $0\ea_r$next[63:0]$6478 end - attribute \src "libresoc.v:140504.3-140513.6" - process $proc$libresoc.v:140504$6432 + attribute \src "libresoc.v:142136.3-142145.6" + process $proc$libresoc.v:142136$6480 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:140505.5-140505.29" + attribute \src "libresoc.v:142137.5-142137.29" switch \initial - attribute \src "libresoc.v:140505.9-140505.17" + attribute \src "libresoc.v:142137.9-142137.17" case 1'1 case end @@ -226941,14 +229438,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:140514.3-140523.6" - process $proc$libresoc.v:140514$6433 + attribute \src "libresoc.v:142146.3-142155.6" + process $proc$libresoc.v:142146$6481 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:140515.5-140515.29" + attribute \src "libresoc.v:142147.5-142147.29" switch \initial - attribute \src "libresoc.v:140515.9-140515.17" + attribute \src "libresoc.v:142147.9-142147.17" case 1'1 case end @@ -226964,14 +229461,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:140524.3-140532.6" - process $proc$libresoc.v:140524$6434 + attribute \src "libresoc.v:142156.3-142164.6" + process $proc$libresoc.v:142156$6482 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6435 $1\ldst_port0_addr_i_ok$next[0:0]$6436 - attribute \src "libresoc.v:140525.5-140525.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:142157.5-142157.29" switch \initial - attribute \src "libresoc.v:140525.9-140525.17" + attribute \src "libresoc.v:142157.9-142157.17" case 1'1 case end @@ -226980,21 +229477,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6435 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 end - attribute \src "libresoc.v:140533.3-140556.6" - process $proc$libresoc.v:140533$6437 + attribute \src "libresoc.v:142165.3-142188.6" + process $proc$libresoc.v:142165$6485 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:140534.5-140534.29" + attribute \src "libresoc.v:142166.5-142166.29" switch \initial - attribute \src "libresoc.v:140534.9-140534.17" + attribute \src "libresoc.v:142166.9-142166.17" case 1'1 case end @@ -227031,13 +229528,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:140557.3-140568.6" - process $proc$libresoc.v:140557$6438 + attribute \src "libresoc.v:142189.3-142200.6" + process $proc$libresoc.v:142189$6486 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:140558.5-140558.29" + attribute \src "libresoc.v:142190.5-142190.29" switch \initial - attribute \src "libresoc.v:140558.9-140558.17" + attribute \src "libresoc.v:142190.9-142190.17" case 1'1 case end @@ -227055,13 +229552,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:140569.3-140588.6" - process $proc$libresoc.v:140569$6439 + attribute \src "libresoc.v:142201.3-142220.6" + process $proc$libresoc.v:142201$6487 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:140570.5-140570.29" + attribute \src "libresoc.v:142202.5-142202.29" switch \initial - attribute \src "libresoc.v:140570.9-140570.17" + attribute \src "libresoc.v:142202.9-142202.17" case 1'1 case end @@ -227090,14 +229587,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:140589.3-140612.6" - process $proc$libresoc.v:140589$6440 + attribute \src "libresoc.v:142221.3-142244.6" + process $proc$libresoc.v:142221$6488 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:140590.5-140590.29" + attribute \src "libresoc.v:142222.5-142222.29" switch \initial - attribute \src "libresoc.v:140590.9-140590.17" + attribute \src "libresoc.v:142222.9-142222.17" case 1'1 case end @@ -227134,13 +229631,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:140613.3-140624.6" - process $proc$libresoc.v:140613$6441 + attribute \src "libresoc.v:142245.3-142256.6" + process $proc$libresoc.v:142245$6489 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140614.5-140614.29" + attribute \src "libresoc.v:142246.5-142246.29" switch \initial - attribute \src "libresoc.v:140614.9-140614.17" + attribute \src "libresoc.v:142246.9-142246.17" case 1'1 case end @@ -227158,97 +229655,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:140072$6200_Y - connect \$102 $and$libresoc.v:140073$6201_Y - connect \$104 $and$libresoc.v:140074$6202_Y - connect \$106 $and$libresoc.v:140075$6203_Y - connect \$108 $and$libresoc.v:140076$6204_Y - connect \$10 $or$libresoc.v:140077$6205_Y - connect \$110 $and$libresoc.v:140078$6206_Y - connect \$112 $and$libresoc.v:140079$6207_Y - connect \$114 $and$libresoc.v:140080$6208_Y - connect \$116 $and$libresoc.v:140081$6209_Y - connect \$118 $and$libresoc.v:140082$6210_Y - connect \$120 $and$libresoc.v:140083$6211_Y - connect \$122 $and$libresoc.v:140084$6212_Y - connect \$124 $and$libresoc.v:140085$6213_Y - connect \$126 $eq$libresoc.v:140086$6214_Y - connect \$128 $and$libresoc.v:140087$6215_Y - connect \$12 $or$libresoc.v:140088$6216_Y - connect \$130 $and$libresoc.v:140089$6217_Y - connect \$132 $and$libresoc.v:140090$6218_Y - connect \$134 $or$libresoc.v:140091$6219_Y - connect \$136 $or$libresoc.v:140092$6220_Y - connect \$138 $or$libresoc.v:140093$6221_Y - connect \$140 $and$libresoc.v:140094$6222_Y - connect \$142 $and$libresoc.v:140095$6223_Y - connect \$145 $or$libresoc.v:140096$6224_Y - connect \$147 $or$libresoc.v:140097$6225_Y - connect \$144 $not$libresoc.v:140098$6226_Y - connect \$14 $or$libresoc.v:140099$6227_Y - connect \$150 $and$libresoc.v:140100$6228_Y - connect \$152 $or$libresoc.v:140101$6229_Y - connect \$154 $and$libresoc.v:140102$6230_Y - connect \$156 $not$libresoc.v:140103$6231_Y - connect \$158 $or$libresoc.v:140104$6232_Y - connect \$160 $and$libresoc.v:140105$6233_Y - connect \$162 $eq$libresoc.v:140106$6234_Y - connect \$164 $and$libresoc.v:140107$6235_Y - connect \$167 $eq$libresoc.v:140108$6236_Y - connect \$16 $or$libresoc.v:140109$6237_Y - connect \$169 $and$libresoc.v:140110$6238_Y - connect \$171 $and$libresoc.v:140111$6239_Y - connect \$173 $and$libresoc.v:140112$6240_Y - connect \$175 $pos$libresoc.v:140113$6242_Y - connect \$177 $and$libresoc.v:140114$6243_Y - connect \$186 $pos$libresoc.v:140115$6245_Y - connect \$188 $pos$libresoc.v:140116$6246_Y - connect \$18 $or$libresoc.v:140117$6247_Y - connect \$190 $pos$libresoc.v:140118$6248_Y - connect \$192 $eq$libresoc.v:140119$6249_Y - connect \$194 $pos$libresoc.v:140120$6251_Y - connect \$196 $pos$libresoc.v:140121$6252_Y - connect \$198 $pos$libresoc.v:140122$6253_Y - connect \$20 $or$libresoc.v:140123$6254_Y - connect \$22 $eq$libresoc.v:140124$6255_Y - connect \$24 $eq$libresoc.v:140125$6256_Y - connect \$26 $and$libresoc.v:140126$6257_Y - connect \$28 $and$libresoc.v:140127$6258_Y - connect \$30 $not$libresoc.v:140128$6259_Y - connect \$32 $and$libresoc.v:140129$6260_Y - connect \$34 $not$libresoc.v:140130$6261_Y - connect \$36 $and$libresoc.v:140131$6262_Y - connect \$39 $not$libresoc.v:140132$6263_Y - connect \$41 $eq$libresoc.v:140133$6264_Y - connect \$43 $and$libresoc.v:140134$6265_Y - connect \$45 $or$libresoc.v:140135$6266_Y - connect \$47 $not$libresoc.v:140136$6267_Y - connect \$49 $eq$libresoc.v:140137$6268_Y - connect \$51 $and$libresoc.v:140138$6269_Y - connect \$53 $or$libresoc.v:140139$6270_Y - connect \$55 $or$libresoc.v:140140$6271_Y - connect \$57 $and$libresoc.v:140141$6272_Y - connect \$59 $or$libresoc.v:140142$6273_Y - connect \$61 $or$libresoc.v:140143$6274_Y - connect \$63 $or$libresoc.v:140144$6275_Y - connect \$65 $ternary$libresoc.v:140145$6276_Y - connect \$67 $ternary$libresoc.v:140146$6277_Y - connect \$69 $ternary$libresoc.v:140147$6278_Y - connect \$71 $ternary$libresoc.v:140148$6279_Y - connect \$74 $add$libresoc.v:140149$6280_Y - connect \$76 $and$libresoc.v:140150$6281_Y - connect \$78 $not$libresoc.v:140151$6282_Y - connect \$80 $and$libresoc.v:140152$6283_Y - connect \$82 $not$libresoc.v:140153$6284_Y - connect \$84 $and$libresoc.v:140154$6285_Y - connect \$86 $and$libresoc.v:140155$6286_Y - connect \$88 $and$libresoc.v:140156$6287_Y - connect \$8 $or$libresoc.v:140157$6288_Y - connect \$90 $or$libresoc.v:140158$6289_Y - connect \$93 $or$libresoc.v:140159$6290_Y - connect \$92 $not$libresoc.v:140160$6291_Y - connect \$96 $and$libresoc.v:140161$6292_Y - connect \$98 $not$libresoc.v:140162$6293_Y + connect \$100 $and$libresoc.v:141704$6248_Y + connect \$102 $and$libresoc.v:141705$6249_Y + connect \$104 $and$libresoc.v:141706$6250_Y + connect \$106 $and$libresoc.v:141707$6251_Y + connect \$108 $and$libresoc.v:141708$6252_Y + connect \$10 $or$libresoc.v:141709$6253_Y + connect \$110 $and$libresoc.v:141710$6254_Y + connect \$112 $and$libresoc.v:141711$6255_Y + connect \$114 $and$libresoc.v:141712$6256_Y + connect \$116 $and$libresoc.v:141713$6257_Y + connect \$118 $and$libresoc.v:141714$6258_Y + connect \$120 $and$libresoc.v:141715$6259_Y + connect \$122 $and$libresoc.v:141716$6260_Y + connect \$124 $and$libresoc.v:141717$6261_Y + connect \$126 $eq$libresoc.v:141718$6262_Y + connect \$128 $and$libresoc.v:141719$6263_Y + connect \$12 $or$libresoc.v:141720$6264_Y + connect \$130 $and$libresoc.v:141721$6265_Y + connect \$132 $and$libresoc.v:141722$6266_Y + connect \$134 $or$libresoc.v:141723$6267_Y + connect \$136 $or$libresoc.v:141724$6268_Y + connect \$138 $or$libresoc.v:141725$6269_Y + connect \$140 $and$libresoc.v:141726$6270_Y + connect \$142 $and$libresoc.v:141727$6271_Y + connect \$145 $or$libresoc.v:141728$6272_Y + connect \$147 $or$libresoc.v:141729$6273_Y + connect \$144 $not$libresoc.v:141730$6274_Y + connect \$14 $or$libresoc.v:141731$6275_Y + connect \$150 $and$libresoc.v:141732$6276_Y + connect \$152 $or$libresoc.v:141733$6277_Y + connect \$154 $and$libresoc.v:141734$6278_Y + connect \$156 $not$libresoc.v:141735$6279_Y + connect \$158 $or$libresoc.v:141736$6280_Y + connect \$160 $and$libresoc.v:141737$6281_Y + connect \$162 $eq$libresoc.v:141738$6282_Y + connect \$164 $and$libresoc.v:141739$6283_Y + connect \$167 $eq$libresoc.v:141740$6284_Y + connect \$16 $or$libresoc.v:141741$6285_Y + connect \$169 $and$libresoc.v:141742$6286_Y + connect \$171 $and$libresoc.v:141743$6287_Y + connect \$173 $and$libresoc.v:141744$6288_Y + connect \$175 $pos$libresoc.v:141745$6290_Y + connect \$177 $and$libresoc.v:141746$6291_Y + connect \$186 $pos$libresoc.v:141747$6293_Y + connect \$188 $pos$libresoc.v:141748$6294_Y + connect \$18 $or$libresoc.v:141749$6295_Y + connect \$190 $pos$libresoc.v:141750$6296_Y + connect \$192 $eq$libresoc.v:141751$6297_Y + connect \$194 $pos$libresoc.v:141752$6299_Y + connect \$196 $pos$libresoc.v:141753$6300_Y + connect \$198 $pos$libresoc.v:141754$6301_Y + connect \$20 $or$libresoc.v:141755$6302_Y + connect \$22 $eq$libresoc.v:141756$6303_Y + connect \$24 $eq$libresoc.v:141757$6304_Y + connect \$26 $and$libresoc.v:141758$6305_Y + connect \$28 $and$libresoc.v:141759$6306_Y + connect \$30 $not$libresoc.v:141760$6307_Y + connect \$32 $and$libresoc.v:141761$6308_Y + connect \$34 $not$libresoc.v:141762$6309_Y + connect \$36 $and$libresoc.v:141763$6310_Y + connect \$39 $not$libresoc.v:141764$6311_Y + connect \$41 $eq$libresoc.v:141765$6312_Y + connect \$43 $and$libresoc.v:141766$6313_Y + connect \$45 $or$libresoc.v:141767$6314_Y + connect \$47 $not$libresoc.v:141768$6315_Y + connect \$49 $eq$libresoc.v:141769$6316_Y + connect \$51 $and$libresoc.v:141770$6317_Y + connect \$53 $or$libresoc.v:141771$6318_Y + connect \$55 $or$libresoc.v:141772$6319_Y + connect \$57 $and$libresoc.v:141773$6320_Y + connect \$59 $or$libresoc.v:141774$6321_Y + connect \$61 $or$libresoc.v:141775$6322_Y + connect \$63 $or$libresoc.v:141776$6323_Y + connect \$65 $ternary$libresoc.v:141777$6324_Y + connect \$67 $ternary$libresoc.v:141778$6325_Y + connect \$69 $ternary$libresoc.v:141779$6326_Y + connect \$71 $ternary$libresoc.v:141780$6327_Y + connect \$74 $add$libresoc.v:141781$6328_Y + connect \$76 $and$libresoc.v:141782$6329_Y + connect \$78 $not$libresoc.v:141783$6330_Y + connect \$80 $and$libresoc.v:141784$6331_Y + connect \$82 $not$libresoc.v:141785$6332_Y + connect \$84 $and$libresoc.v:141786$6333_Y + connect \$86 $and$libresoc.v:141787$6334_Y + connect \$88 $and$libresoc.v:141788$6335_Y + connect \$8 $or$libresoc.v:141789$6336_Y + connect \$90 $or$libresoc.v:141790$6337_Y + connect \$93 $or$libresoc.v:141791$6338_Y + connect \$92 $not$libresoc.v:141792$6339_Y + connect \$96 $and$libresoc.v:141793$6340_Y + connect \$98 $not$libresoc.v:141794$6341_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -227309,271 +229806,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:140688.1-141275.10" +attribute \src "libresoc.v:142320.1-142907.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:140689.7-140689.20" + attribute \src "libresoc.v:142321.7-142321.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $10\mask[9:9] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $11\mask[10:10] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $12\mask[11:11] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $13\mask[12:12] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $14\mask[13:13] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $15\mask[14:14] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $16\mask[15:15] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $17\mask[16:16] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $18\mask[17:17] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $19\mask[18:18] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $1\mask[0:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $20\mask[19:19] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $21\mask[20:20] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $22\mask[21:21] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $23\mask[22:22] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $24\mask[23:23] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $25\mask[24:24] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $26\mask[25:25] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $27\mask[26:26] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $28\mask[27:27] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $29\mask[28:28] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $2\mask[1:1] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $30\mask[29:29] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $31\mask[30:30] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $32\mask[31:31] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $33\mask[32:32] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $34\mask[33:33] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $35\mask[34:34] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $36\mask[35:35] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $37\mask[36:36] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $38\mask[37:37] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $39\mask[38:38] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $3\mask[2:2] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $40\mask[39:39] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $41\mask[40:40] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $42\mask[41:41] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $43\mask[42:42] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $44\mask[43:43] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $45\mask[44:44] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $46\mask[45:45] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $47\mask[46:46] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $48\mask[47:47] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $49\mask[48:48] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $4\mask[3:3] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $50\mask[49:49] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $51\mask[50:50] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $52\mask[51:51] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $53\mask[52:52] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $54\mask[53:53] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $55\mask[54:54] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $56\mask[55:55] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $57\mask[56:56] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $58\mask[57:57] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $59\mask[58:58] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $5\mask[4:4] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $60\mask[59:59] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $61\mask[60:60] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $62\mask[61:61] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $63\mask[62:62] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $64\mask[63:63] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $6\mask[5:5] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $7\mask[6:6] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $8\mask[7:7] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $9\mask[8:8] - attribute \src "libresoc.v:140823.17-140823.96" - wire $gt$libresoc.v:140823$6478_Y - attribute \src "libresoc.v:140824.18-140824.98" - wire $gt$libresoc.v:140824$6479_Y - attribute \src "libresoc.v:140825.19-140825.99" - wire $gt$libresoc.v:140825$6480_Y - attribute \src "libresoc.v:140826.19-140826.99" - wire $gt$libresoc.v:140826$6481_Y - attribute \src "libresoc.v:140827.19-140827.99" - wire $gt$libresoc.v:140827$6482_Y - attribute \src "libresoc.v:140828.19-140828.99" - wire $gt$libresoc.v:140828$6483_Y - attribute \src "libresoc.v:140829.19-140829.99" - wire $gt$libresoc.v:140829$6484_Y - attribute \src "libresoc.v:140830.19-140830.99" - wire $gt$libresoc.v:140830$6485_Y - attribute \src "libresoc.v:140831.19-140831.99" - wire $gt$libresoc.v:140831$6486_Y - attribute \src "libresoc.v:140832.19-140832.99" - wire $gt$libresoc.v:140832$6487_Y - attribute \src "libresoc.v:140833.19-140833.99" - wire $gt$libresoc.v:140833$6488_Y - attribute \src "libresoc.v:140834.18-140834.97" - wire $gt$libresoc.v:140834$6489_Y - attribute \src "libresoc.v:140835.19-140835.99" - wire $gt$libresoc.v:140835$6490_Y - attribute \src "libresoc.v:140836.19-140836.99" - wire $gt$libresoc.v:140836$6491_Y - attribute \src "libresoc.v:140837.19-140837.99" - wire $gt$libresoc.v:140837$6492_Y - attribute \src "libresoc.v:140838.19-140838.99" - wire $gt$libresoc.v:140838$6493_Y - attribute \src "libresoc.v:140839.19-140839.99" - wire $gt$libresoc.v:140839$6494_Y - attribute \src "libresoc.v:140840.18-140840.97" - wire $gt$libresoc.v:140840$6495_Y - attribute \src "libresoc.v:140841.18-140841.97" - wire $gt$libresoc.v:140841$6496_Y - attribute \src "libresoc.v:140842.18-140842.97" - wire $gt$libresoc.v:140842$6497_Y - attribute \src "libresoc.v:140843.17-140843.96" - wire $gt$libresoc.v:140843$6498_Y - attribute \src "libresoc.v:140844.18-140844.97" - wire $gt$libresoc.v:140844$6499_Y - attribute \src "libresoc.v:140845.18-140845.97" - wire $gt$libresoc.v:140845$6500_Y - attribute \src "libresoc.v:140846.18-140846.97" - wire $gt$libresoc.v:140846$6501_Y - attribute \src "libresoc.v:140847.18-140847.97" - wire $gt$libresoc.v:140847$6502_Y - attribute \src "libresoc.v:140848.18-140848.97" - wire $gt$libresoc.v:140848$6503_Y - attribute \src "libresoc.v:140849.18-140849.97" - wire $gt$libresoc.v:140849$6504_Y - attribute \src "libresoc.v:140850.18-140850.97" - wire $gt$libresoc.v:140850$6505_Y - attribute \src "libresoc.v:140851.18-140851.98" - wire $gt$libresoc.v:140851$6506_Y - attribute \src "libresoc.v:140852.18-140852.98" - wire $gt$libresoc.v:140852$6507_Y - attribute \src "libresoc.v:140853.18-140853.98" - wire $gt$libresoc.v:140853$6508_Y - attribute \src "libresoc.v:140854.17-140854.96" - wire $gt$libresoc.v:140854$6509_Y - attribute \src "libresoc.v:140855.18-140855.98" - wire $gt$libresoc.v:140855$6510_Y - attribute \src "libresoc.v:140856.18-140856.98" - wire $gt$libresoc.v:140856$6511_Y - attribute \src "libresoc.v:140857.18-140857.98" - wire $gt$libresoc.v:140857$6512_Y - attribute \src "libresoc.v:140858.18-140858.98" - wire $gt$libresoc.v:140858$6513_Y - attribute \src "libresoc.v:140859.18-140859.98" - wire $gt$libresoc.v:140859$6514_Y - attribute \src "libresoc.v:140860.18-140860.98" - wire $gt$libresoc.v:140860$6515_Y - attribute \src "libresoc.v:140861.18-140861.98" - wire $gt$libresoc.v:140861$6516_Y - attribute \src "libresoc.v:140862.18-140862.98" - wire $gt$libresoc.v:140862$6517_Y - attribute \src "libresoc.v:140863.18-140863.98" - wire $gt$libresoc.v:140863$6518_Y - attribute \src "libresoc.v:140864.18-140864.98" - wire $gt$libresoc.v:140864$6519_Y - attribute \src "libresoc.v:140865.17-140865.96" - wire $gt$libresoc.v:140865$6520_Y - attribute \src "libresoc.v:140866.18-140866.98" - wire $gt$libresoc.v:140866$6521_Y - attribute \src "libresoc.v:140867.18-140867.98" - wire $gt$libresoc.v:140867$6522_Y - attribute \src "libresoc.v:140868.18-140868.98" - wire $gt$libresoc.v:140868$6523_Y - attribute \src "libresoc.v:140869.18-140869.98" - wire $gt$libresoc.v:140869$6524_Y - attribute \src "libresoc.v:140870.18-140870.98" - wire $gt$libresoc.v:140870$6525_Y - attribute \src "libresoc.v:140871.18-140871.98" - wire $gt$libresoc.v:140871$6526_Y - attribute \src "libresoc.v:140872.18-140872.98" - wire $gt$libresoc.v:140872$6527_Y - attribute \src "libresoc.v:140873.18-140873.98" - wire $gt$libresoc.v:140873$6528_Y - attribute \src "libresoc.v:140874.18-140874.98" - wire $gt$libresoc.v:140874$6529_Y - attribute \src "libresoc.v:140875.18-140875.98" - wire $gt$libresoc.v:140875$6530_Y - attribute \src "libresoc.v:140876.17-140876.96" - wire $gt$libresoc.v:140876$6531_Y - attribute \src "libresoc.v:140877.18-140877.98" - wire $gt$libresoc.v:140877$6532_Y - attribute \src "libresoc.v:140878.18-140878.98" - wire $gt$libresoc.v:140878$6533_Y - attribute \src "libresoc.v:140879.18-140879.98" - wire $gt$libresoc.v:140879$6534_Y - attribute \src "libresoc.v:140880.18-140880.98" - wire $gt$libresoc.v:140880$6535_Y - attribute \src "libresoc.v:140881.18-140881.98" - wire $gt$libresoc.v:140881$6536_Y - attribute \src "libresoc.v:140882.18-140882.98" - wire $gt$libresoc.v:140882$6537_Y - attribute \src "libresoc.v:140883.18-140883.98" - wire $gt$libresoc.v:140883$6538_Y - attribute \src "libresoc.v:140884.18-140884.98" - wire $gt$libresoc.v:140884$6539_Y - attribute \src "libresoc.v:140885.18-140885.98" - wire $gt$libresoc.v:140885$6540_Y - attribute \src "libresoc.v:140886.18-140886.98" - wire $gt$libresoc.v:140886$6541_Y + attribute \src "libresoc.v:142455.17-142455.96" + wire $gt$libresoc.v:142455$6526_Y + attribute \src "libresoc.v:142456.18-142456.98" + wire $gt$libresoc.v:142456$6527_Y + attribute \src "libresoc.v:142457.19-142457.99" + wire $gt$libresoc.v:142457$6528_Y + attribute \src "libresoc.v:142458.19-142458.99" + wire $gt$libresoc.v:142458$6529_Y + attribute \src "libresoc.v:142459.19-142459.99" + wire $gt$libresoc.v:142459$6530_Y + attribute \src "libresoc.v:142460.19-142460.99" + wire $gt$libresoc.v:142460$6531_Y + attribute \src "libresoc.v:142461.19-142461.99" + wire $gt$libresoc.v:142461$6532_Y + attribute \src "libresoc.v:142462.19-142462.99" + wire $gt$libresoc.v:142462$6533_Y + attribute \src "libresoc.v:142463.19-142463.99" + wire $gt$libresoc.v:142463$6534_Y + attribute \src "libresoc.v:142464.19-142464.99" + wire $gt$libresoc.v:142464$6535_Y + attribute \src "libresoc.v:142465.19-142465.99" + wire $gt$libresoc.v:142465$6536_Y + attribute \src "libresoc.v:142466.18-142466.97" + wire $gt$libresoc.v:142466$6537_Y + attribute \src "libresoc.v:142467.19-142467.99" + wire $gt$libresoc.v:142467$6538_Y + attribute \src "libresoc.v:142468.19-142468.99" + wire $gt$libresoc.v:142468$6539_Y + attribute \src "libresoc.v:142469.19-142469.99" + wire $gt$libresoc.v:142469$6540_Y + attribute \src "libresoc.v:142470.19-142470.99" + wire $gt$libresoc.v:142470$6541_Y + attribute \src "libresoc.v:142471.19-142471.99" + wire $gt$libresoc.v:142471$6542_Y + attribute \src "libresoc.v:142472.18-142472.97" + wire $gt$libresoc.v:142472$6543_Y + attribute \src "libresoc.v:142473.18-142473.97" + wire $gt$libresoc.v:142473$6544_Y + attribute \src "libresoc.v:142474.18-142474.97" + wire $gt$libresoc.v:142474$6545_Y + attribute \src "libresoc.v:142475.17-142475.96" + wire $gt$libresoc.v:142475$6546_Y + attribute \src "libresoc.v:142476.18-142476.97" + wire $gt$libresoc.v:142476$6547_Y + attribute \src "libresoc.v:142477.18-142477.97" + wire $gt$libresoc.v:142477$6548_Y + attribute \src "libresoc.v:142478.18-142478.97" + wire $gt$libresoc.v:142478$6549_Y + attribute \src "libresoc.v:142479.18-142479.97" + wire $gt$libresoc.v:142479$6550_Y + attribute \src "libresoc.v:142480.18-142480.97" + wire $gt$libresoc.v:142480$6551_Y + attribute \src "libresoc.v:142481.18-142481.97" + wire $gt$libresoc.v:142481$6552_Y + attribute \src "libresoc.v:142482.18-142482.97" + wire $gt$libresoc.v:142482$6553_Y + attribute \src "libresoc.v:142483.18-142483.98" + wire $gt$libresoc.v:142483$6554_Y + attribute \src "libresoc.v:142484.18-142484.98" + wire $gt$libresoc.v:142484$6555_Y + attribute \src "libresoc.v:142485.18-142485.98" + wire $gt$libresoc.v:142485$6556_Y + attribute \src "libresoc.v:142486.17-142486.96" + wire $gt$libresoc.v:142486$6557_Y + attribute \src "libresoc.v:142487.18-142487.98" + wire $gt$libresoc.v:142487$6558_Y + attribute \src "libresoc.v:142488.18-142488.98" + wire $gt$libresoc.v:142488$6559_Y + attribute \src "libresoc.v:142489.18-142489.98" + wire $gt$libresoc.v:142489$6560_Y + attribute \src "libresoc.v:142490.18-142490.98" + wire $gt$libresoc.v:142490$6561_Y + attribute \src "libresoc.v:142491.18-142491.98" + wire $gt$libresoc.v:142491$6562_Y + attribute \src "libresoc.v:142492.18-142492.98" + wire $gt$libresoc.v:142492$6563_Y + attribute \src "libresoc.v:142493.18-142493.98" + wire $gt$libresoc.v:142493$6564_Y + attribute \src "libresoc.v:142494.18-142494.98" + wire $gt$libresoc.v:142494$6565_Y + attribute \src "libresoc.v:142495.18-142495.98" + wire $gt$libresoc.v:142495$6566_Y + attribute \src "libresoc.v:142496.18-142496.98" + wire $gt$libresoc.v:142496$6567_Y + attribute \src "libresoc.v:142497.17-142497.96" + wire $gt$libresoc.v:142497$6568_Y + attribute \src "libresoc.v:142498.18-142498.98" + wire $gt$libresoc.v:142498$6569_Y + attribute \src "libresoc.v:142499.18-142499.98" + wire $gt$libresoc.v:142499$6570_Y + attribute \src "libresoc.v:142500.18-142500.98" + wire $gt$libresoc.v:142500$6571_Y + attribute \src "libresoc.v:142501.18-142501.98" + wire $gt$libresoc.v:142501$6572_Y + attribute \src "libresoc.v:142502.18-142502.98" + wire $gt$libresoc.v:142502$6573_Y + attribute \src "libresoc.v:142503.18-142503.98" + wire $gt$libresoc.v:142503$6574_Y + attribute \src "libresoc.v:142504.18-142504.98" + wire $gt$libresoc.v:142504$6575_Y + attribute \src "libresoc.v:142505.18-142505.98" + wire $gt$libresoc.v:142505$6576_Y + attribute \src "libresoc.v:142506.18-142506.98" + wire $gt$libresoc.v:142506$6577_Y + attribute \src "libresoc.v:142507.18-142507.98" + wire $gt$libresoc.v:142507$6578_Y + attribute \src "libresoc.v:142508.17-142508.96" + wire $gt$libresoc.v:142508$6579_Y + attribute \src "libresoc.v:142509.18-142509.98" + wire $gt$libresoc.v:142509$6580_Y + attribute \src "libresoc.v:142510.18-142510.98" + wire $gt$libresoc.v:142510$6581_Y + attribute \src "libresoc.v:142511.18-142511.98" + wire $gt$libresoc.v:142511$6582_Y + attribute \src "libresoc.v:142512.18-142512.98" + wire $gt$libresoc.v:142512$6583_Y + attribute \src "libresoc.v:142513.18-142513.98" + wire $gt$libresoc.v:142513$6584_Y + attribute \src "libresoc.v:142514.18-142514.98" + wire $gt$libresoc.v:142514$6585_Y + attribute \src "libresoc.v:142515.18-142515.98" + wire $gt$libresoc.v:142515$6586_Y + attribute \src "libresoc.v:142516.18-142516.98" + wire $gt$libresoc.v:142516$6587_Y + attribute \src "libresoc.v:142517.18-142517.98" + wire $gt$libresoc.v:142517$6588_Y + attribute \src "libresoc.v:142518.18-142518.98" + wire $gt$libresoc.v:142518$6589_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -227702,14 +230199,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:140689.7-140689.15" + attribute \src "libresoc.v:142321.7-142321.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140823$6478 + cell $gt $gt$libresoc.v:142455$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227717,10 +230214,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:140823$6478_Y + connect \Y $gt$libresoc.v:142455$6526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140824$6479 + cell $gt $gt$libresoc.v:142456$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227728,10 +230225,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:140824$6479_Y + connect \Y $gt$libresoc.v:142456$6527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140825$6480 + cell $gt $gt$libresoc.v:142457$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227739,10 +230236,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:140825$6480_Y + connect \Y $gt$libresoc.v:142457$6528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140826$6481 + cell $gt $gt$libresoc.v:142458$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227750,10 +230247,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:140826$6481_Y + connect \Y $gt$libresoc.v:142458$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140827$6482 + cell $gt $gt$libresoc.v:142459$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227761,10 +230258,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:140827$6482_Y + connect \Y $gt$libresoc.v:142459$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140828$6483 + cell $gt $gt$libresoc.v:142460$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227772,10 +230269,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:140828$6483_Y + connect \Y $gt$libresoc.v:142460$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140829$6484 + cell $gt $gt$libresoc.v:142461$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227783,10 +230280,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:140829$6484_Y + connect \Y $gt$libresoc.v:142461$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140830$6485 + cell $gt $gt$libresoc.v:142462$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227794,10 +230291,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:140830$6485_Y + connect \Y $gt$libresoc.v:142462$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140831$6486 + cell $gt $gt$libresoc.v:142463$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227805,10 +230302,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:140831$6486_Y + connect \Y $gt$libresoc.v:142463$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140832$6487 + cell $gt $gt$libresoc.v:142464$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227816,10 +230313,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:140832$6487_Y + connect \Y $gt$libresoc.v:142464$6535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140833$6488 + cell $gt $gt$libresoc.v:142465$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227827,10 +230324,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:140833$6488_Y + connect \Y $gt$libresoc.v:142465$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140834$6489 + cell $gt $gt$libresoc.v:142466$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227838,10 +230335,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:140834$6489_Y + connect \Y $gt$libresoc.v:142466$6537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140835$6490 + cell $gt $gt$libresoc.v:142467$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227849,10 +230346,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:140835$6490_Y + connect \Y $gt$libresoc.v:142467$6538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140836$6491 + cell $gt $gt$libresoc.v:142468$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227860,10 +230357,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:140836$6491_Y + connect \Y $gt$libresoc.v:142468$6539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140837$6492 + cell $gt $gt$libresoc.v:142469$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227871,10 +230368,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:140837$6492_Y + connect \Y $gt$libresoc.v:142469$6540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140838$6493 + cell $gt $gt$libresoc.v:142470$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227882,10 +230379,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:140838$6493_Y + connect \Y $gt$libresoc.v:142470$6541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140839$6494 + cell $gt $gt$libresoc.v:142471$6542 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227893,10 +230390,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:140839$6494_Y + connect \Y $gt$libresoc.v:142471$6542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140840$6495 + cell $gt $gt$libresoc.v:142472$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227904,10 +230401,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:140840$6495_Y + connect \Y $gt$libresoc.v:142472$6543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140841$6496 + cell $gt $gt$libresoc.v:142473$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227915,10 +230412,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:140841$6496_Y + connect \Y $gt$libresoc.v:142473$6544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140842$6497 + cell $gt $gt$libresoc.v:142474$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227926,10 +230423,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:140842$6497_Y + connect \Y $gt$libresoc.v:142474$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140843$6498 + cell $gt $gt$libresoc.v:142475$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227937,10 +230434,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:140843$6498_Y + connect \Y $gt$libresoc.v:142475$6546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140844$6499 + cell $gt $gt$libresoc.v:142476$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227948,10 +230445,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:140844$6499_Y + connect \Y $gt$libresoc.v:142476$6547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140845$6500 + cell $gt $gt$libresoc.v:142477$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227959,10 +230456,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:140845$6500_Y + connect \Y $gt$libresoc.v:142477$6548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140846$6501 + cell $gt $gt$libresoc.v:142478$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227970,10 +230467,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:140846$6501_Y + connect \Y $gt$libresoc.v:142478$6549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140847$6502 + cell $gt $gt$libresoc.v:142479$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227981,10 +230478,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:140847$6502_Y + connect \Y $gt$libresoc.v:142479$6550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140848$6503 + cell $gt $gt$libresoc.v:142480$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227992,10 +230489,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:140848$6503_Y + connect \Y $gt$libresoc.v:142480$6551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140849$6504 + cell $gt $gt$libresoc.v:142481$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228003,10 +230500,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:140849$6504_Y + connect \Y $gt$libresoc.v:142481$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140850$6505 + cell $gt $gt$libresoc.v:142482$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228014,10 +230511,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:140850$6505_Y + connect \Y $gt$libresoc.v:142482$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140851$6506 + cell $gt $gt$libresoc.v:142483$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228025,10 +230522,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:140851$6506_Y + connect \Y $gt$libresoc.v:142483$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140852$6507 + cell $gt $gt$libresoc.v:142484$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228036,10 +230533,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:140852$6507_Y + connect \Y $gt$libresoc.v:142484$6555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140853$6508 + cell $gt $gt$libresoc.v:142485$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228047,10 +230544,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:140853$6508_Y + connect \Y $gt$libresoc.v:142485$6556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140854$6509 + cell $gt $gt$libresoc.v:142486$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228058,10 +230555,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:140854$6509_Y + connect \Y $gt$libresoc.v:142486$6557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140855$6510 + cell $gt $gt$libresoc.v:142487$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228069,10 +230566,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:140855$6510_Y + connect \Y $gt$libresoc.v:142487$6558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140856$6511 + cell $gt $gt$libresoc.v:142488$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228080,10 +230577,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:140856$6511_Y + connect \Y $gt$libresoc.v:142488$6559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140857$6512 + cell $gt $gt$libresoc.v:142489$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228091,10 +230588,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:140857$6512_Y + connect \Y $gt$libresoc.v:142489$6560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140858$6513 + cell $gt $gt$libresoc.v:142490$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228102,10 +230599,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:140858$6513_Y + connect \Y $gt$libresoc.v:142490$6561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140859$6514 + cell $gt $gt$libresoc.v:142491$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228113,10 +230610,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:140859$6514_Y + connect \Y $gt$libresoc.v:142491$6562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140860$6515 + cell $gt $gt$libresoc.v:142492$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228124,10 +230621,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:140860$6515_Y + connect \Y $gt$libresoc.v:142492$6563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140861$6516 + cell $gt $gt$libresoc.v:142493$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228135,10 +230632,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:140861$6516_Y + connect \Y $gt$libresoc.v:142493$6564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140862$6517 + cell $gt $gt$libresoc.v:142494$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228146,10 +230643,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:140862$6517_Y + connect \Y $gt$libresoc.v:142494$6565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140863$6518 + cell $gt $gt$libresoc.v:142495$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228157,10 +230654,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:140863$6518_Y + connect \Y $gt$libresoc.v:142495$6566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140864$6519 + cell $gt $gt$libresoc.v:142496$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228168,10 +230665,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:140864$6519_Y + connect \Y $gt$libresoc.v:142496$6567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140865$6520 + cell $gt $gt$libresoc.v:142497$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228179,10 +230676,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:140865$6520_Y + connect \Y $gt$libresoc.v:142497$6568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140866$6521 + cell $gt $gt$libresoc.v:142498$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228190,10 +230687,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:140866$6521_Y + connect \Y $gt$libresoc.v:142498$6569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140867$6522 + cell $gt $gt$libresoc.v:142499$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228201,10 +230698,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:140867$6522_Y + connect \Y $gt$libresoc.v:142499$6570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140868$6523 + cell $gt $gt$libresoc.v:142500$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228212,10 +230709,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:140868$6523_Y + connect \Y $gt$libresoc.v:142500$6571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140869$6524 + cell $gt $gt$libresoc.v:142501$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228223,10 +230720,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:140869$6524_Y + connect \Y $gt$libresoc.v:142501$6572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140870$6525 + cell $gt $gt$libresoc.v:142502$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228234,10 +230731,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:140870$6525_Y + connect \Y $gt$libresoc.v:142502$6573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140871$6526 + cell $gt $gt$libresoc.v:142503$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228245,10 +230742,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:140871$6526_Y + connect \Y $gt$libresoc.v:142503$6574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140872$6527 + cell $gt $gt$libresoc.v:142504$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228256,10 +230753,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:140872$6527_Y + connect \Y $gt$libresoc.v:142504$6575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140873$6528 + cell $gt $gt$libresoc.v:142505$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228267,10 +230764,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:140873$6528_Y + connect \Y $gt$libresoc.v:142505$6576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140874$6529 + cell $gt $gt$libresoc.v:142506$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228278,10 +230775,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:140874$6529_Y + connect \Y $gt$libresoc.v:142506$6577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140875$6530 + cell $gt $gt$libresoc.v:142507$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228289,10 +230786,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:140875$6530_Y + connect \Y $gt$libresoc.v:142507$6578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140876$6531 + cell $gt $gt$libresoc.v:142508$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228300,10 +230797,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:140876$6531_Y + connect \Y $gt$libresoc.v:142508$6579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140877$6532 + cell $gt $gt$libresoc.v:142509$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228311,10 +230808,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:140877$6532_Y + connect \Y $gt$libresoc.v:142509$6580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140878$6533 + cell $gt $gt$libresoc.v:142510$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228322,10 +230819,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:140878$6533_Y + connect \Y $gt$libresoc.v:142510$6581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140879$6534 + cell $gt $gt$libresoc.v:142511$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228333,10 +230830,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:140879$6534_Y + connect \Y $gt$libresoc.v:142511$6582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140880$6535 + cell $gt $gt$libresoc.v:142512$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228344,10 +230841,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:140880$6535_Y + connect \Y $gt$libresoc.v:142512$6583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140881$6536 + cell $gt $gt$libresoc.v:142513$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228355,10 +230852,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:140881$6536_Y + connect \Y $gt$libresoc.v:142513$6584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140882$6537 + cell $gt $gt$libresoc.v:142514$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228366,10 +230863,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:140882$6537_Y + connect \Y $gt$libresoc.v:142514$6585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140883$6538 + cell $gt $gt$libresoc.v:142515$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228377,10 +230874,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:140883$6538_Y + connect \Y $gt$libresoc.v:142515$6586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140884$6539 + cell $gt $gt$libresoc.v:142516$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228388,10 +230885,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:140884$6539_Y + connect \Y $gt$libresoc.v:142516$6587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140885$6540 + cell $gt $gt$libresoc.v:142517$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228399,10 +230896,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:140885$6540_Y + connect \Y $gt$libresoc.v:142517$6588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140886$6541 + cell $gt $gt$libresoc.v:142518$6589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228410,18 +230907,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:140886$6541_Y + connect \Y $gt$libresoc.v:142518$6589_Y end - attribute \src "libresoc.v:140689.7-140689.20" - process $proc$libresoc.v:140689$6543 + attribute \src "libresoc.v:142321.7-142321.20" + process $proc$libresoc.v:142321$6591 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140887.3-141274.6" - process $proc$libresoc.v:140887$6542 + attribute \src "libresoc.v:142519.3-142906.6" + process $proc$libresoc.v:142519$6590 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -228488,9 +230985,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:140888.5-140888.29" + attribute \src "libresoc.v:142520.5-142520.29" switch \initial - attribute \src "libresoc.v:140888.9-140888.17" + attribute \src "libresoc.v:142520.9-142520.17" case 1'1 case end @@ -229073,86 +231570,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:140823$6478_Y - connect \$99 $gt$libresoc.v:140824$6479_Y - connect \$101 $gt$libresoc.v:140825$6480_Y - connect \$103 $gt$libresoc.v:140826$6481_Y - connect \$105 $gt$libresoc.v:140827$6482_Y - connect \$107 $gt$libresoc.v:140828$6483_Y - connect \$109 $gt$libresoc.v:140829$6484_Y - connect \$111 $gt$libresoc.v:140830$6485_Y - connect \$113 $gt$libresoc.v:140831$6486_Y - connect \$115 $gt$libresoc.v:140832$6487_Y - connect \$117 $gt$libresoc.v:140833$6488_Y - connect \$11 $gt$libresoc.v:140834$6489_Y - connect \$119 $gt$libresoc.v:140835$6490_Y - connect \$121 $gt$libresoc.v:140836$6491_Y - connect \$123 $gt$libresoc.v:140837$6492_Y - connect \$125 $gt$libresoc.v:140838$6493_Y - connect \$127 $gt$libresoc.v:140839$6494_Y - connect \$13 $gt$libresoc.v:140840$6495_Y - connect \$15 $gt$libresoc.v:140841$6496_Y - connect \$17 $gt$libresoc.v:140842$6497_Y - connect \$1 $gt$libresoc.v:140843$6498_Y - connect \$19 $gt$libresoc.v:140844$6499_Y - connect \$21 $gt$libresoc.v:140845$6500_Y - connect \$23 $gt$libresoc.v:140846$6501_Y - connect \$25 $gt$libresoc.v:140847$6502_Y - connect \$27 $gt$libresoc.v:140848$6503_Y - connect \$29 $gt$libresoc.v:140849$6504_Y - connect \$31 $gt$libresoc.v:140850$6505_Y - connect \$33 $gt$libresoc.v:140851$6506_Y - connect \$35 $gt$libresoc.v:140852$6507_Y - connect \$37 $gt$libresoc.v:140853$6508_Y - connect \$3 $gt$libresoc.v:140854$6509_Y - connect \$39 $gt$libresoc.v:140855$6510_Y - connect \$41 $gt$libresoc.v:140856$6511_Y - connect \$43 $gt$libresoc.v:140857$6512_Y - connect \$45 $gt$libresoc.v:140858$6513_Y - connect \$47 $gt$libresoc.v:140859$6514_Y - connect \$49 $gt$libresoc.v:140860$6515_Y - connect \$51 $gt$libresoc.v:140861$6516_Y - connect \$53 $gt$libresoc.v:140862$6517_Y - connect \$55 $gt$libresoc.v:140863$6518_Y - connect \$57 $gt$libresoc.v:140864$6519_Y - connect \$5 $gt$libresoc.v:140865$6520_Y - connect \$59 $gt$libresoc.v:140866$6521_Y - connect \$61 $gt$libresoc.v:140867$6522_Y - connect \$63 $gt$libresoc.v:140868$6523_Y - connect \$65 $gt$libresoc.v:140869$6524_Y - connect \$67 $gt$libresoc.v:140870$6525_Y - connect \$69 $gt$libresoc.v:140871$6526_Y - connect \$71 $gt$libresoc.v:140872$6527_Y - connect \$73 $gt$libresoc.v:140873$6528_Y - connect \$75 $gt$libresoc.v:140874$6529_Y - connect \$77 $gt$libresoc.v:140875$6530_Y - connect \$7 $gt$libresoc.v:140876$6531_Y - connect \$79 $gt$libresoc.v:140877$6532_Y - connect \$81 $gt$libresoc.v:140878$6533_Y - connect \$83 $gt$libresoc.v:140879$6534_Y - connect \$85 $gt$libresoc.v:140880$6535_Y - connect \$87 $gt$libresoc.v:140881$6536_Y - connect \$89 $gt$libresoc.v:140882$6537_Y - connect \$91 $gt$libresoc.v:140883$6538_Y - connect \$93 $gt$libresoc.v:140884$6539_Y - connect \$95 $gt$libresoc.v:140885$6540_Y - connect \$97 $gt$libresoc.v:140886$6541_Y + connect \$9 $gt$libresoc.v:142455$6526_Y + connect \$99 $gt$libresoc.v:142456$6527_Y + connect \$101 $gt$libresoc.v:142457$6528_Y + connect \$103 $gt$libresoc.v:142458$6529_Y + connect \$105 $gt$libresoc.v:142459$6530_Y + connect \$107 $gt$libresoc.v:142460$6531_Y + connect \$109 $gt$libresoc.v:142461$6532_Y + connect \$111 $gt$libresoc.v:142462$6533_Y + connect \$113 $gt$libresoc.v:142463$6534_Y + connect \$115 $gt$libresoc.v:142464$6535_Y + connect \$117 $gt$libresoc.v:142465$6536_Y + connect \$11 $gt$libresoc.v:142466$6537_Y + connect \$119 $gt$libresoc.v:142467$6538_Y + connect \$121 $gt$libresoc.v:142468$6539_Y + connect \$123 $gt$libresoc.v:142469$6540_Y + connect \$125 $gt$libresoc.v:142470$6541_Y + connect \$127 $gt$libresoc.v:142471$6542_Y + connect \$13 $gt$libresoc.v:142472$6543_Y + connect \$15 $gt$libresoc.v:142473$6544_Y + connect \$17 $gt$libresoc.v:142474$6545_Y + connect \$1 $gt$libresoc.v:142475$6546_Y + connect \$19 $gt$libresoc.v:142476$6547_Y + connect \$21 $gt$libresoc.v:142477$6548_Y + connect \$23 $gt$libresoc.v:142478$6549_Y + connect \$25 $gt$libresoc.v:142479$6550_Y + connect \$27 $gt$libresoc.v:142480$6551_Y + connect \$29 $gt$libresoc.v:142481$6552_Y + connect \$31 $gt$libresoc.v:142482$6553_Y + connect \$33 $gt$libresoc.v:142483$6554_Y + connect \$35 $gt$libresoc.v:142484$6555_Y + connect \$37 $gt$libresoc.v:142485$6556_Y + connect \$3 $gt$libresoc.v:142486$6557_Y + connect \$39 $gt$libresoc.v:142487$6558_Y + connect \$41 $gt$libresoc.v:142488$6559_Y + connect \$43 $gt$libresoc.v:142489$6560_Y + connect \$45 $gt$libresoc.v:142490$6561_Y + connect \$47 $gt$libresoc.v:142491$6562_Y + connect \$49 $gt$libresoc.v:142492$6563_Y + connect \$51 $gt$libresoc.v:142493$6564_Y + connect \$53 $gt$libresoc.v:142494$6565_Y + connect \$55 $gt$libresoc.v:142495$6566_Y + connect \$57 $gt$libresoc.v:142496$6567_Y + connect \$5 $gt$libresoc.v:142497$6568_Y + connect \$59 $gt$libresoc.v:142498$6569_Y + connect \$61 $gt$libresoc.v:142499$6570_Y + connect \$63 $gt$libresoc.v:142500$6571_Y + connect \$65 $gt$libresoc.v:142501$6572_Y + connect \$67 $gt$libresoc.v:142502$6573_Y + connect \$69 $gt$libresoc.v:142503$6574_Y + connect \$71 $gt$libresoc.v:142504$6575_Y + connect \$73 $gt$libresoc.v:142505$6576_Y + connect \$75 $gt$libresoc.v:142506$6577_Y + connect \$77 $gt$libresoc.v:142507$6578_Y + connect \$7 $gt$libresoc.v:142508$6579_Y + connect \$79 $gt$libresoc.v:142509$6580_Y + connect \$81 $gt$libresoc.v:142510$6581_Y + connect \$83 $gt$libresoc.v:142511$6582_Y + connect \$85 $gt$libresoc.v:142512$6583_Y + connect \$87 $gt$libresoc.v:142513$6584_Y + connect \$89 $gt$libresoc.v:142514$6585_Y + connect \$91 $gt$libresoc.v:142515$6586_Y + connect \$93 $gt$libresoc.v:142516$6587_Y + connect \$95 $gt$libresoc.v:142517$6588_Y + connect \$97 $gt$libresoc.v:142518$6589_Y end -attribute \src "libresoc.v:141279.1-141308.10" +attribute \src "libresoc.v:142911.1-142940.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:141303.17-141303.101" - wire width 64 $extend$libresoc.v:141303$6547_Y - attribute \src "libresoc.v:141303.17-141303.101" - wire width 64 $pos$libresoc.v:141303$6548_Y - attribute \src "libresoc.v:141300.17-141300.111" - wire width 20 $sshl$libresoc.v:141300$6544_Y - attribute \src "libresoc.v:141302.17-141302.113" - wire width 32 $sshl$libresoc.v:141302$6546_Y - attribute \src "libresoc.v:141301.17-141301.107" - wire width 21 $sub$libresoc.v:141301$6545_Y + attribute \src "libresoc.v:142935.17-142935.101" + wire width 64 $extend$libresoc.v:142935$6595_Y + attribute \src "libresoc.v:142935.17-142935.101" + wire width 64 $pos$libresoc.v:142935$6596_Y + attribute \src "libresoc.v:142932.17-142932.111" + wire width 20 $sshl$libresoc.v:142932$6592_Y + attribute \src "libresoc.v:142934.17-142934.113" + wire width 32 $sshl$libresoc.v:142934$6594_Y + attribute \src "libresoc.v:142933.17-142933.107" + wire width 21 $sub$libresoc.v:142933$6593_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -229174,23 +231671,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:141303$6547 + cell $pos $extend$libresoc.v:142935$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:141303$6547_Y + connect \Y $extend$libresoc.v:142935$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:141303$6548 + cell $pos $pos$libresoc.v:142935$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141303$6547_Y - connect \Y $pos$libresoc.v:141303$6548_Y + connect \A $extend$libresoc.v:142935$6595_Y + connect \Y $pos$libresoc.v:142935$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:141300$6544 + cell $sshl $sshl$libresoc.v:142932$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -229198,10 +231695,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:141300$6544_Y + connect \Y $sshl$libresoc.v:142932$6592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:141302$6546 + cell $sshl $sshl$libresoc.v:142934$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -229209,10 +231706,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:141302$6546_Y + connect \Y $sshl$libresoc.v:142934$6594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:141301$6545 + cell $sub $sub$libresoc.v:142933$6593 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -229220,48 +231717,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:141301$6545_Y + connect \Y $sub$libresoc.v:142933$6593_Y end - connect \$2 $sshl$libresoc.v:141300$6544_Y - connect \$4 $sub$libresoc.v:141301$6545_Y - connect \$7 $sshl$libresoc.v:141302$6546_Y - connect \$6 $pos$libresoc.v:141303$6548_Y + connect \$2 $sshl$libresoc.v:142932$6592_Y + connect \$4 $sub$libresoc.v:142933$6593_Y + connect \$7 $sshl$libresoc.v:142934$6594_Y + connect \$6 $pos$libresoc.v:142935$6596_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:141312.1-141370.10" +attribute \src "libresoc.v:142944.1-143002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:141313.7-141313.20" + attribute \src "libresoc.v:142945.7-142945.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141358.3-141366.6" - wire $0\q_int$next[0:0]$6559 - attribute \src "libresoc.v:141356.3-141357.27" + attribute \src "libresoc.v:142990.3-142998.6" + wire $0\q_int$next[0:0]$6607 + attribute \src "libresoc.v:142988.3-142989.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:141358.3-141366.6" - wire $1\q_int$next[0:0]$6560 - attribute \src "libresoc.v:141335.7-141335.19" + attribute \src "libresoc.v:142990.3-142998.6" + wire $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142967.7-142967.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:141348.17-141348.96" - wire $and$libresoc.v:141348$6549_Y - attribute \src "libresoc.v:141353.17-141353.96" - wire $and$libresoc.v:141353$6554_Y - attribute \src "libresoc.v:141350.18-141350.93" - wire $not$libresoc.v:141350$6551_Y - attribute \src "libresoc.v:141352.17-141352.92" - wire $not$libresoc.v:141352$6553_Y - attribute \src "libresoc.v:141355.17-141355.92" - wire $not$libresoc.v:141355$6556_Y - attribute \src "libresoc.v:141349.18-141349.98" - wire $or$libresoc.v:141349$6550_Y - attribute \src "libresoc.v:141351.18-141351.99" - wire $or$libresoc.v:141351$6552_Y - attribute \src "libresoc.v:141354.17-141354.97" - wire $or$libresoc.v:141354$6555_Y + attribute \src "libresoc.v:142980.17-142980.96" + wire $and$libresoc.v:142980$6597_Y + attribute \src "libresoc.v:142985.17-142985.96" + wire $and$libresoc.v:142985$6602_Y + attribute \src "libresoc.v:142982.18-142982.93" + wire $not$libresoc.v:142982$6599_Y + attribute \src "libresoc.v:142984.17-142984.92" + wire $not$libresoc.v:142984$6601_Y + attribute \src "libresoc.v:142987.17-142987.92" + wire $not$libresoc.v:142987$6604_Y + attribute \src "libresoc.v:142981.18-142981.98" + wire $or$libresoc.v:142981$6598_Y + attribute \src "libresoc.v:142983.18-142983.99" + wire $or$libresoc.v:142983$6600_Y + attribute \src "libresoc.v:142986.17-142986.97" + wire $or$libresoc.v:142986$6603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -229278,11 +231775,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:141313.7-141313.15" + attribute \src "libresoc.v:142945.7-142945.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -229299,7 +231796,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:141348$6549 + cell $and $and$libresoc.v:142980$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229307,10 +231804,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:141348$6549_Y + connect \Y $and$libresoc.v:142980$6597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:141353$6554 + cell $and $and$libresoc.v:142985$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229318,34 +231815,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:141353$6554_Y + connect \Y $and$libresoc.v:142985$6602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:141350$6551 + cell $not $not$libresoc.v:142982$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:141350$6551_Y + connect \Y $not$libresoc.v:142982$6599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:141352$6553 + cell $not $not$libresoc.v:142984$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:141352$6553_Y + connect \Y $not$libresoc.v:142984$6601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:141355$6556 + cell $not $not$libresoc.v:142987$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:141355$6556_Y + connect \Y $not$libresoc.v:142987$6604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:141349$6550 + cell $or $or$libresoc.v:142981$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229353,10 +231850,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:141349$6550_Y + connect \Y $or$libresoc.v:142981$6598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:141351$6552 + cell $or $or$libresoc.v:142983$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229364,10 +231861,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:141351$6552_Y + connect \Y $or$libresoc.v:142983$6600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:141354$6555 + cell $or $or$libresoc.v:142986$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229375,39 +231872,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:141354$6555_Y + connect \Y $or$libresoc.v:142986$6603_Y end - attribute \src "libresoc.v:141313.7-141313.20" - process $proc$libresoc.v:141313$6561 + attribute \src "libresoc.v:142945.7-142945.20" + process $proc$libresoc.v:142945$6609 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141335.7-141335.19" - process $proc$libresoc.v:141335$6562 + attribute \src "libresoc.v:142967.7-142967.19" + process $proc$libresoc.v:142967$6610 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:141356.3-141357.27" - process $proc$libresoc.v:141356$6557 + attribute \src "libresoc.v:142988.3-142989.27" + process $proc$libresoc.v:142988$6605 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:141358.3-141366.6" - process $proc$libresoc.v:141358$6558 + attribute \src "libresoc.v:142990.3-142998.6" + process $proc$libresoc.v:142990$6606 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6559 $1\q_int$next[0:0]$6560 - attribute \src "libresoc.v:141359.5-141359.29" + assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142991.5-142991.29" switch \initial - attribute \src "libresoc.v:141359.9-141359.17" + attribute \src "libresoc.v:142991.9-142991.17" case 1'1 case end @@ -229416,494 +231913,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6560 1'0 + assign $1\q_int$next[0:0]$6608 1'0 case - assign $1\q_int$next[0:0]$6560 \$5 + assign $1\q_int$next[0:0]$6608 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6559 + update \q_int$next $0\q_int$next[0:0]$6607 end - connect \$9 $and$libresoc.v:141348$6549_Y - connect \$11 $or$libresoc.v:141349$6550_Y - connect \$13 $not$libresoc.v:141350$6551_Y - connect \$15 $or$libresoc.v:141351$6552_Y - connect \$1 $not$libresoc.v:141352$6553_Y - connect \$3 $and$libresoc.v:141353$6554_Y - connect \$5 $or$libresoc.v:141354$6555_Y - connect \$7 $not$libresoc.v:141355$6556_Y + connect \$9 $and$libresoc.v:142980$6597_Y + connect \$11 $or$libresoc.v:142981$6598_Y + connect \$13 $not$libresoc.v:142982$6599_Y + connect \$15 $or$libresoc.v:142983$6600_Y + connect \$1 $not$libresoc.v:142984$6601_Y + connect \$3 $and$libresoc.v:142985$6602_Y + connect \$5 $or$libresoc.v:142986$6603_Y + connect \$7 $not$libresoc.v:142987$6604_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:141374.1-142494.10" +attribute \src "libresoc.v:143006.1-144126.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:142119.3-142120.24" + attribute \src "libresoc.v:143751.3-143752.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:142117.3-142118.44" + attribute \src "libresoc.v:143749.3-143750.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:142424.3-142432.6" - wire $0\alu_l_r_alu$next[0:0]$6763 - attribute \src "libresoc.v:142041.3-142042.39" + attribute \src "libresoc.v:144056.3-144064.6" + wire $0\alu_l_r_alu$next[0:0]$6811 + attribute \src "libresoc.v:143673.3-143674.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6692 - attribute \src "libresoc.v:142091.3-142092.83" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + attribute \src "libresoc.v:143723.3-143724.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 - attribute \src "libresoc.v:142061.3-142062.81" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + attribute \src "libresoc.v:143693.3-143694.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 - attribute \src "libresoc.v:142063.3-142064.95" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + attribute \src "libresoc.v:143695.3-143696.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 - attribute \src "libresoc.v:142065.3-142066.91" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + attribute \src "libresoc.v:143697.3-143698.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 - attribute \src "libresoc.v:142079.3-142080.89" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + attribute \src "libresoc.v:143711.3-143712.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6697 - attribute \src "libresoc.v:142093.3-142094.75" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 + attribute \src "libresoc.v:143725.3-143726.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 - attribute \src "libresoc.v:142059.3-142060.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + attribute \src "libresoc.v:143691.3-143692.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 - attribute \src "libresoc.v:142075.3-142076.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + attribute \src "libresoc.v:143707.3-143708.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 - attribute \src "libresoc.v:142081.3-142082.87" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + attribute \src "libresoc.v:143713.3-143714.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 - attribute \src "libresoc.v:142087.3-142088.83" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + attribute \src "libresoc.v:143719.3-143720.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 - attribute \src "libresoc.v:142089.3-142090.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + attribute \src "libresoc.v:143721.3-143722.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 - attribute \src "libresoc.v:142071.3-142072.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + attribute \src "libresoc.v:143703.3-143704.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 - attribute \src "libresoc.v:142073.3-142074.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + attribute \src "libresoc.v:143705.3-143706.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 - attribute \src "libresoc.v:142085.3-142086.91" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + attribute \src "libresoc.v:143717.3-143718.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 - attribute \src "libresoc.v:142069.3-142070.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + attribute \src "libresoc.v:143701.3-143702.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 - attribute \src "libresoc.v:142067.3-142068.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + attribute \src "libresoc.v:143699.3-143700.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 - attribute \src "libresoc.v:142083.3-142084.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + attribute \src "libresoc.v:143715.3-143716.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 - attribute \src "libresoc.v:142077.3-142078.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + attribute \src "libresoc.v:143709.3-143710.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:142415.3-142423.6" - wire $0\alui_l_r_alui$next[0:0]$6760 - attribute \src "libresoc.v:142043.3-142044.43" + attribute \src "libresoc.v:144047.3-144055.6" + wire $0\alui_l_r_alui$next[0:0]$6808 + attribute \src "libresoc.v:143675.3-143676.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $0\data_r0__o$next[63:0]$6735 - attribute \src "libresoc.v:142055.3-142056.37" + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $0\data_r0__o$next[63:0]$6783 + attribute \src "libresoc.v:143687.3-143688.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire $0\data_r0__o_ok$next[0:0]$6736 - attribute \src "libresoc.v:142057.3-142058.43" + attribute \src "libresoc.v:143973.3-143994.6" + wire $0\data_r0__o_ok$next[0:0]$6784 + attribute \src "libresoc.v:143689.3-143690.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6743 - attribute \src "libresoc.v:142051.3-142052.43" + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6791 + attribute \src "libresoc.v:143683.3-143684.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6744 - attribute \src "libresoc.v:142053.3-142054.49" + attribute \src "libresoc.v:143995.3-144016.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6792 + attribute \src "libresoc.v:143685.3-143686.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:142433.3-142442.6" + attribute \src "libresoc.v:144065.3-144074.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142443.3-142452.6" + attribute \src "libresoc.v:144075.3-144084.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:141375.7-141375.20" + attribute \src "libresoc.v:143007.7-143007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142257.3-142265.6" - wire $0\opc_l_r_opc$next[0:0]$6677 - attribute \src "libresoc.v:142103.3-142104.39" + attribute \src "libresoc.v:143889.3-143897.6" + wire $0\opc_l_r_opc$next[0:0]$6725 + attribute \src "libresoc.v:143735.3-143736.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142248.3-142256.6" - wire $0\opc_l_s_opc$next[0:0]$6674 - attribute \src "libresoc.v:142105.3-142106.39" + attribute \src "libresoc.v:143880.3-143888.6" + wire $0\opc_l_s_opc$next[0:0]$6722 + attribute \src "libresoc.v:143737.3-143738.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142453.3-142461.6" - wire width 2 $0\prev_wr_go$next[1:0]$6768 - attribute \src "libresoc.v:142115.3-142116.37" + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $0\prev_wr_go$next[1:0]$6816 + attribute \src "libresoc.v:143747.3-143748.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:142202.3-142211.6" + attribute \src "libresoc.v:143834.3-143843.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:142293.3-142301.6" - wire width 2 $0\req_l_r_req$next[1:0]$6689 - attribute \src "libresoc.v:142095.3-142096.39" + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $0\req_l_r_req$next[1:0]$6737 + attribute \src "libresoc.v:143727.3-143728.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:142284.3-142292.6" - wire width 2 $0\req_l_s_req$next[1:0]$6686 - attribute \src "libresoc.v:142097.3-142098.39" + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $0\req_l_s_req$next[1:0]$6734 + attribute \src "libresoc.v:143729.3-143730.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:142221.3-142229.6" - wire $0\rok_l_r_rdok$next[0:0]$6665 - attribute \src "libresoc.v:142111.3-142112.41" + attribute \src "libresoc.v:143853.3-143861.6" + wire $0\rok_l_r_rdok$next[0:0]$6713 + attribute \src "libresoc.v:143743.3-143744.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:142212.3-142220.6" - wire $0\rok_l_s_rdok$next[0:0]$6662 - attribute \src "libresoc.v:142113.3-142114.41" + attribute \src "libresoc.v:143844.3-143852.6" + wire $0\rok_l_s_rdok$next[0:0]$6710 + attribute \src "libresoc.v:143745.3-143746.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:142239.3-142247.6" - wire $0\rst_l_r_rst$next[0:0]$6671 - attribute \src "libresoc.v:142107.3-142108.39" + attribute \src "libresoc.v:143871.3-143879.6" + wire $0\rst_l_r_rst$next[0:0]$6719 + attribute \src "libresoc.v:143739.3-143740.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:142230.3-142238.6" - wire $0\rst_l_s_rst$next[0:0]$6668 - attribute \src "libresoc.v:142109.3-142110.39" + attribute \src "libresoc.v:143862.3-143870.6" + wire $0\rst_l_s_rst$next[0:0]$6716 + attribute \src "libresoc.v:143741.3-143742.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:142275.3-142283.6" - wire width 3 $0\src_l_r_src$next[2:0]$6683 - attribute \src "libresoc.v:142099.3-142100.39" + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $0\src_l_r_src$next[2:0]$6731 + attribute \src "libresoc.v:143731.3-143732.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:142266.3-142274.6" - wire width 3 $0\src_l_s_src$next[2:0]$6680 - attribute \src "libresoc.v:142101.3-142102.39" + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $0\src_l_s_src$next[2:0]$6728 + attribute \src "libresoc.v:143733.3-143734.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142385.3-142394.6" - wire width 64 $0\src_r0$next[63:0]$6751 - attribute \src "libresoc.v:142049.3-142050.29" + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $0\src_r0$next[63:0]$6799 + attribute \src "libresoc.v:143681.3-143682.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142395.3-142404.6" - wire width 64 $0\src_r1$next[63:0]$6754 - attribute \src "libresoc.v:142047.3-142048.29" + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $0\src_r1$next[63:0]$6802 + attribute \src "libresoc.v:143679.3-143680.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142405.3-142414.6" - wire $0\src_r2$next[0:0]$6757 - attribute \src "libresoc.v:142045.3-142046.29" + attribute \src "libresoc.v:144037.3-144046.6" + wire $0\src_r2$next[0:0]$6805 + attribute \src "libresoc.v:143677.3-143678.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:141493.7-141493.24" + attribute \src "libresoc.v:143125.7-143125.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:141503.7-141503.26" + attribute \src "libresoc.v:143135.7-143135.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:142424.3-142432.6" - wire $1\alu_l_r_alu$next[0:0]$6764 - attribute \src "libresoc.v:141511.7-141511.25" + attribute \src "libresoc.v:144056.3-144064.6" + wire $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:143143.7-143143.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 - attribute \src "libresoc.v:141519.13-141519.53" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + attribute \src "libresoc.v:143151.13-143151.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 - attribute \src "libresoc.v:141538.14-141538.57" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + attribute \src "libresoc.v:143170.14-143170.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 - attribute \src "libresoc.v:141542.14-141542.76" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + attribute \src "libresoc.v:143174.14-143174.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 - attribute \src "libresoc.v:141546.7-141546.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + attribute \src "libresoc.v:143178.7-143178.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 - attribute \src "libresoc.v:141554.13-141554.56" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + attribute \src "libresoc.v:143186.13-143186.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6715 - attribute \src "libresoc.v:141558.14-141558.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + attribute \src "libresoc.v:143190.14-143190.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 - attribute \src "libresoc.v:141637.13-141637.55" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + attribute \src "libresoc.v:143269.13-143269.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 - attribute \src "libresoc.v:141641.7-141641.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + attribute \src "libresoc.v:143273.7-143273.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 - attribute \src "libresoc.v:141645.7-141645.49" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + attribute \src "libresoc.v:143277.7-143277.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 - attribute \src "libresoc.v:141649.7-141649.47" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + attribute \src "libresoc.v:143281.7-143281.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 - attribute \src "libresoc.v:141653.7-141653.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + attribute \src "libresoc.v:143285.7-143285.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 - attribute \src "libresoc.v:141657.7-141657.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + attribute \src "libresoc.v:143289.7-143289.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 - attribute \src "libresoc.v:141661.7-141661.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + attribute \src "libresoc.v:143293.7-143293.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 - attribute \src "libresoc.v:141665.7-141665.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + attribute \src "libresoc.v:143297.7-143297.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 - attribute \src "libresoc.v:141669.7-141669.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + attribute \src "libresoc.v:143301.7-143301.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 - attribute \src "libresoc.v:141673.7-141673.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + attribute \src "libresoc.v:143305.7-143305.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 - attribute \src "libresoc.v:141677.7-141677.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + attribute \src "libresoc.v:143309.7-143309.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 - attribute \src "libresoc.v:141681.7-141681.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + attribute \src "libresoc.v:143313.7-143313.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:142415.3-142423.6" - wire $1\alui_l_r_alui$next[0:0]$6761 - attribute \src "libresoc.v:141707.7-141707.27" + attribute \src "libresoc.v:144047.3-144055.6" + wire $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:143339.7-143339.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $1\data_r0__o$next[63:0]$6737 - attribute \src "libresoc.v:141741.14-141741.47" + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $1\data_r0__o$next[63:0]$6785 + attribute \src "libresoc.v:143373.14-143373.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire $1\data_r0__o_ok$next[0:0]$6738 - attribute \src "libresoc.v:141745.7-141745.27" + attribute \src "libresoc.v:143973.3-143994.6" + wire $1\data_r0__o_ok$next[0:0]$6786 + attribute \src "libresoc.v:143377.7-143377.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6745 - attribute \src "libresoc.v:141749.13-141749.33" + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6793 + attribute \src "libresoc.v:143381.13-143381.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6746 - attribute \src "libresoc.v:141753.7-141753.30" + attribute \src "libresoc.v:143995.3-144016.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6794 + attribute \src "libresoc.v:143385.7-143385.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:142433.3-142442.6" + attribute \src "libresoc.v:144065.3-144074.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142443.3-142452.6" + attribute \src "libresoc.v:144075.3-144084.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:142257.3-142265.6" - wire $1\opc_l_r_opc$next[0:0]$6678 - attribute \src "libresoc.v:141767.7-141767.25" + attribute \src "libresoc.v:143889.3-143897.6" + wire $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143399.7-143399.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142248.3-142256.6" - wire $1\opc_l_s_opc$next[0:0]$6675 - attribute \src "libresoc.v:141771.7-141771.25" + attribute \src "libresoc.v:143880.3-143888.6" + wire $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143403.7-143403.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142453.3-142461.6" - wire width 2 $1\prev_wr_go$next[1:0]$6769 - attribute \src "libresoc.v:141905.13-141905.30" + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:143537.13-143537.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:142202.3-142211.6" + attribute \src "libresoc.v:143834.3-143843.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:142293.3-142301.6" - wire width 2 $1\req_l_r_req$next[1:0]$6690 - attribute \src "libresoc.v:141913.13-141913.31" + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143545.13-143545.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:142284.3-142292.6" - wire width 2 $1\req_l_s_req$next[1:0]$6687 - attribute \src "libresoc.v:141917.13-141917.31" + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143549.13-143549.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:142221.3-142229.6" - wire $1\rok_l_r_rdok$next[0:0]$6666 - attribute \src "libresoc.v:141929.7-141929.26" + attribute \src "libresoc.v:143853.3-143861.6" + wire $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143561.7-143561.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:142212.3-142220.6" - wire $1\rok_l_s_rdok$next[0:0]$6663 - attribute \src "libresoc.v:141933.7-141933.26" + attribute \src "libresoc.v:143844.3-143852.6" + wire $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143565.7-143565.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:142239.3-142247.6" - wire $1\rst_l_r_rst$next[0:0]$6672 - attribute \src "libresoc.v:141937.7-141937.25" + attribute \src "libresoc.v:143871.3-143879.6" + wire $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143569.7-143569.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:142230.3-142238.6" - wire $1\rst_l_s_rst$next[0:0]$6669 - attribute \src "libresoc.v:141941.7-141941.25" + attribute \src "libresoc.v:143862.3-143870.6" + wire $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143573.7-143573.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:142275.3-142283.6" - wire width 3 $1\src_l_r_src$next[2:0]$6684 - attribute \src "libresoc.v:141955.13-141955.31" + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143587.13-143587.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:142266.3-142274.6" - wire width 3 $1\src_l_s_src$next[2:0]$6681 - attribute \src "libresoc.v:141959.13-141959.31" + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143591.13-143591.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142385.3-142394.6" - wire width 64 $1\src_r0$next[63:0]$6752 - attribute \src "libresoc.v:141967.14-141967.43" + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:143599.14-143599.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142395.3-142404.6" - wire width 64 $1\src_r1$next[63:0]$6755 - attribute \src "libresoc.v:141971.14-141971.43" + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:143603.14-143603.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142405.3-142414.6" - wire $1\src_r2$next[0:0]$6758 - attribute \src "libresoc.v:141975.7-141975.20" + attribute \src "libresoc.v:144037.3-144046.6" + wire $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:143607.7-143607.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $2\data_r0__o$next[63:0]$6739 - attribute \src "libresoc.v:142341.3-142362.6" - wire $2\data_r0__o_ok$next[0:0]$6740 - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6747 - attribute \src "libresoc.v:142363.3-142384.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6748 - attribute \src "libresoc.v:142341.3-142362.6" - wire $3\data_r0__o_ok$next[0:0]$6741 - attribute \src "libresoc.v:142363.3-142384.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6749 - attribute \src "libresoc.v:141984.17-141984.109" - wire $and$libresoc.v:141984$6563_Y - attribute \src "libresoc.v:141985.18-141985.130" - wire width 3 $and$libresoc.v:141985$6564_Y - attribute \src "libresoc.v:141987.19-141987.114" - wire width 3 $and$libresoc.v:141987$6566_Y - attribute \src "libresoc.v:141988.19-141988.125" - wire $and$libresoc.v:141988$6567_Y - attribute \src "libresoc.v:141989.19-141989.125" - wire $and$libresoc.v:141989$6568_Y - attribute \src "libresoc.v:141990.19-141990.133" - wire width 2 $and$libresoc.v:141990$6569_Y - attribute \src "libresoc.v:141991.19-141991.121" - wire width 2 $and$libresoc.v:141991$6570_Y - attribute \src "libresoc.v:141992.19-141992.127" - wire $and$libresoc.v:141992$6571_Y - attribute \src "libresoc.v:141993.19-141993.127" - wire $and$libresoc.v:141993$6572_Y - attribute \src "libresoc.v:141995.18-141995.98" - wire $and$libresoc.v:141995$6574_Y - attribute \src "libresoc.v:141997.18-141997.100" - wire $and$libresoc.v:141997$6576_Y - attribute \src "libresoc.v:141998.17-141998.123" - wire $and$libresoc.v:141998$6577_Y - attribute \src "libresoc.v:141999.18-141999.138" - wire width 2 $and$libresoc.v:141999$6578_Y - attribute \src "libresoc.v:142001.18-142001.119" - wire width 2 $and$libresoc.v:142001$6580_Y - attribute \src "libresoc.v:142004.18-142004.116" - wire $and$libresoc.v:142004$6583_Y - attribute \src "libresoc.v:142009.18-142009.113" - wire $and$libresoc.v:142009$6588_Y - attribute \src "libresoc.v:142010.18-142010.125" - wire width 2 $and$libresoc.v:142010$6589_Y - attribute \src "libresoc.v:142012.18-142012.112" - wire $and$libresoc.v:142012$6591_Y - attribute \src "libresoc.v:142015.18-142015.130" - wire $and$libresoc.v:142015$6594_Y - attribute \src "libresoc.v:142016.18-142016.130" - wire $and$libresoc.v:142016$6595_Y - attribute \src "libresoc.v:142017.18-142017.117" - wire $and$libresoc.v:142017$6596_Y - attribute \src "libresoc.v:142022.18-142022.134" - wire $and$libresoc.v:142022$6601_Y - attribute \src "libresoc.v:142023.18-142023.124" - wire width 2 $and$libresoc.v:142023$6602_Y - attribute \src "libresoc.v:142026.18-142026.116" - wire $and$libresoc.v:142026$6605_Y - attribute \src "libresoc.v:142027.18-142027.119" - wire $and$libresoc.v:142027$6606_Y - attribute \src "libresoc.v:142036.18-142036.138" - wire $and$libresoc.v:142036$6615_Y - attribute \src "libresoc.v:142037.18-142037.136" - wire $and$libresoc.v:142037$6616_Y - attribute \src "libresoc.v:142038.18-142038.149" - wire width 3 $and$libresoc.v:142038$6617_Y - attribute \src "libresoc.v:142011.18-142011.113" - wire $eq$libresoc.v:142011$6590_Y - attribute \src "libresoc.v:142013.18-142013.119" - wire $eq$libresoc.v:142013$6592_Y - attribute \src "libresoc.v:141986.19-141986.115" - wire width 3 $not$libresoc.v:141986$6565_Y - attribute \src "libresoc.v:141994.18-141994.97" - wire $not$libresoc.v:141994$6573_Y - attribute \src "libresoc.v:141996.18-141996.99" - wire $not$libresoc.v:141996$6575_Y - attribute \src "libresoc.v:142000.18-142000.113" - wire width 2 $not$libresoc.v:142000$6579_Y - attribute \src "libresoc.v:142003.18-142003.106" - wire $not$libresoc.v:142003$6582_Y - attribute \src "libresoc.v:142008.18-142008.124" - wire $not$libresoc.v:142008$6587_Y - attribute \src "libresoc.v:142014.17-142014.113" - wire width 3 $not$libresoc.v:142014$6593_Y - attribute \src "libresoc.v:142039.18-142039.133" - wire $not$libresoc.v:142039$6618_Y - attribute \src "libresoc.v:142040.18-142040.139" - wire $not$libresoc.v:142040$6619_Y - attribute \src "libresoc.v:142007.18-142007.112" - wire $or$libresoc.v:142007$6586_Y - attribute \src "libresoc.v:142018.18-142018.122" - wire $or$libresoc.v:142018$6597_Y - attribute \src "libresoc.v:142019.18-142019.124" - wire $or$libresoc.v:142019$6598_Y - attribute \src "libresoc.v:142020.18-142020.142" - wire width 2 $or$libresoc.v:142020$6599_Y - attribute \src "libresoc.v:142021.18-142021.155" - wire width 3 $or$libresoc.v:142021$6600_Y - attribute \src "libresoc.v:142024.18-142024.120" - wire width 2 $or$libresoc.v:142024$6603_Y - attribute \src "libresoc.v:142025.17-142025.117" - wire width 3 $or$libresoc.v:142025$6604_Y - attribute \src "libresoc.v:142031.17-142031.104" - wire $reduce_and$libresoc.v:142031$6610_Y - attribute \src "libresoc.v:142002.18-142002.106" - wire $reduce_or$libresoc.v:142002$6581_Y - attribute \src "libresoc.v:142005.18-142005.113" - wire $reduce_or$libresoc.v:142005$6584_Y - attribute \src "libresoc.v:142006.18-142006.112" - wire $reduce_or$libresoc.v:142006$6585_Y - attribute \src "libresoc.v:142028.18-142028.162" - wire $ternary$libresoc.v:142028$6607_Y - attribute \src "libresoc.v:142029.18-142029.163" - wire width 64 $ternary$libresoc.v:142029$6608_Y - attribute \src "libresoc.v:142030.18-142030.168" - wire $ternary$libresoc.v:142030$6609_Y - attribute \src "libresoc.v:142032.18-142032.188" - wire width 64 $ternary$libresoc.v:142032$6611_Y - attribute \src "libresoc.v:142033.18-142033.115" - wire width 64 $ternary$libresoc.v:142033$6612_Y - attribute \src "libresoc.v:142034.18-142034.125" - wire width 64 $ternary$libresoc.v:142034$6613_Y - attribute \src "libresoc.v:142035.18-142035.118" - wire $ternary$libresoc.v:142035$6614_Y + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $2\data_r0__o$next[63:0]$6787 + attribute \src "libresoc.v:143973.3-143994.6" + wire $2\data_r0__o_ok$next[0:0]$6788 + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6795 + attribute \src "libresoc.v:143995.3-144016.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6796 + attribute \src "libresoc.v:143973.3-143994.6" + wire $3\data_r0__o_ok$next[0:0]$6789 + attribute \src "libresoc.v:143995.3-144016.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6797 + attribute \src "libresoc.v:143616.17-143616.109" + wire $and$libresoc.v:143616$6611_Y + attribute \src "libresoc.v:143617.18-143617.130" + wire width 3 $and$libresoc.v:143617$6612_Y + attribute \src "libresoc.v:143619.19-143619.114" + wire width 3 $and$libresoc.v:143619$6614_Y + attribute \src "libresoc.v:143620.19-143620.125" + wire $and$libresoc.v:143620$6615_Y + attribute \src "libresoc.v:143621.19-143621.125" + wire $and$libresoc.v:143621$6616_Y + attribute \src "libresoc.v:143622.19-143622.133" + wire width 2 $and$libresoc.v:143622$6617_Y + attribute \src "libresoc.v:143623.19-143623.121" + wire width 2 $and$libresoc.v:143623$6618_Y + attribute \src "libresoc.v:143624.19-143624.127" + wire $and$libresoc.v:143624$6619_Y + attribute \src "libresoc.v:143625.19-143625.127" + wire $and$libresoc.v:143625$6620_Y + attribute \src "libresoc.v:143627.18-143627.98" + wire $and$libresoc.v:143627$6622_Y + attribute \src "libresoc.v:143629.18-143629.100" + wire $and$libresoc.v:143629$6624_Y + attribute \src "libresoc.v:143630.17-143630.123" + wire $and$libresoc.v:143630$6625_Y + attribute \src "libresoc.v:143631.18-143631.138" + wire width 2 $and$libresoc.v:143631$6626_Y + attribute \src "libresoc.v:143633.18-143633.119" + wire width 2 $and$libresoc.v:143633$6628_Y + attribute \src "libresoc.v:143636.18-143636.116" + wire $and$libresoc.v:143636$6631_Y + attribute \src "libresoc.v:143641.18-143641.113" + wire $and$libresoc.v:143641$6636_Y + attribute \src "libresoc.v:143642.18-143642.125" + wire width 2 $and$libresoc.v:143642$6637_Y + attribute \src "libresoc.v:143644.18-143644.112" + wire $and$libresoc.v:143644$6639_Y + attribute \src "libresoc.v:143647.18-143647.130" + wire $and$libresoc.v:143647$6642_Y + attribute \src "libresoc.v:143648.18-143648.130" + wire $and$libresoc.v:143648$6643_Y + attribute \src "libresoc.v:143649.18-143649.117" + wire $and$libresoc.v:143649$6644_Y + attribute \src "libresoc.v:143654.18-143654.134" + wire $and$libresoc.v:143654$6649_Y + attribute \src "libresoc.v:143655.18-143655.124" + wire width 2 $and$libresoc.v:143655$6650_Y + attribute \src "libresoc.v:143658.18-143658.116" + wire $and$libresoc.v:143658$6653_Y + attribute \src "libresoc.v:143659.18-143659.119" + wire $and$libresoc.v:143659$6654_Y + attribute \src "libresoc.v:143668.18-143668.138" + wire $and$libresoc.v:143668$6663_Y + attribute \src "libresoc.v:143669.18-143669.136" + wire $and$libresoc.v:143669$6664_Y + attribute \src "libresoc.v:143670.18-143670.149" + wire width 3 $and$libresoc.v:143670$6665_Y + attribute \src "libresoc.v:143643.18-143643.113" + wire $eq$libresoc.v:143643$6638_Y + attribute \src "libresoc.v:143645.18-143645.119" + wire $eq$libresoc.v:143645$6640_Y + attribute \src "libresoc.v:143618.19-143618.115" + wire width 3 $not$libresoc.v:143618$6613_Y + attribute \src "libresoc.v:143626.18-143626.97" + wire $not$libresoc.v:143626$6621_Y + attribute \src "libresoc.v:143628.18-143628.99" + wire $not$libresoc.v:143628$6623_Y + attribute \src "libresoc.v:143632.18-143632.113" + wire width 2 $not$libresoc.v:143632$6627_Y + attribute \src "libresoc.v:143635.18-143635.106" + wire $not$libresoc.v:143635$6630_Y + attribute \src "libresoc.v:143640.18-143640.124" + wire $not$libresoc.v:143640$6635_Y + attribute \src "libresoc.v:143646.17-143646.113" + wire width 3 $not$libresoc.v:143646$6641_Y + attribute \src "libresoc.v:143671.18-143671.133" + wire $not$libresoc.v:143671$6666_Y + attribute \src "libresoc.v:143672.18-143672.139" + wire $not$libresoc.v:143672$6667_Y + attribute \src "libresoc.v:143639.18-143639.112" + wire $or$libresoc.v:143639$6634_Y + attribute \src "libresoc.v:143650.18-143650.122" + wire $or$libresoc.v:143650$6645_Y + attribute \src "libresoc.v:143651.18-143651.124" + wire $or$libresoc.v:143651$6646_Y + attribute \src "libresoc.v:143652.18-143652.142" + wire width 2 $or$libresoc.v:143652$6647_Y + attribute \src "libresoc.v:143653.18-143653.155" + wire width 3 $or$libresoc.v:143653$6648_Y + attribute \src "libresoc.v:143656.18-143656.120" + wire width 2 $or$libresoc.v:143656$6651_Y + attribute \src "libresoc.v:143657.17-143657.117" + wire width 3 $or$libresoc.v:143657$6652_Y + attribute \src "libresoc.v:143663.17-143663.104" + wire $reduce_and$libresoc.v:143663$6658_Y + attribute \src "libresoc.v:143634.18-143634.106" + wire $reduce_or$libresoc.v:143634$6629_Y + attribute \src "libresoc.v:143637.18-143637.113" + wire $reduce_or$libresoc.v:143637$6632_Y + attribute \src "libresoc.v:143638.18-143638.112" + wire $reduce_or$libresoc.v:143638$6633_Y + attribute \src "libresoc.v:143660.18-143660.162" + wire $ternary$libresoc.v:143660$6655_Y + attribute \src "libresoc.v:143661.18-143661.163" + wire width 64 $ternary$libresoc.v:143661$6656_Y + attribute \src "libresoc.v:143662.18-143662.168" + wire $ternary$libresoc.v:143662$6657_Y + attribute \src "libresoc.v:143664.18-143664.188" + wire width 64 $ternary$libresoc.v:143664$6659_Y + attribute \src "libresoc.v:143665.18-143665.115" + wire width 64 $ternary$libresoc.v:143665$6660_Y + attribute \src "libresoc.v:143666.18-143666.125" + wire width 64 $ternary$libresoc.v:143666$6661_Y + attribute \src "libresoc.v:143667.18-143667.118" + wire $ternary$libresoc.v:143667$6662_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -230240,9 +232737,9 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -230288,7 +232785,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:141375.7-141375.15" + attribute \src "libresoc.v:143007.7-143007.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -230513,7 +233010,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:141984$6563 + cell $and $and$libresoc.v:143616$6611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230521,10 +233018,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:141984$6563_Y + connect \Y $and$libresoc.v:143616$6611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:141985$6564 + cell $and $and$libresoc.v:143617$6612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230532,10 +233029,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:141985$6564_Y + connect \Y $and$libresoc.v:143617$6612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:141987$6566 + cell $and $and$libresoc.v:143619$6614 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230543,10 +233040,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:141987$6566_Y + connect \Y $and$libresoc.v:143619$6614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:141988$6567 + cell $and $and$libresoc.v:143620$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230554,10 +233051,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141988$6567_Y + connect \Y $and$libresoc.v:143620$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:141989$6568 + cell $and $and$libresoc.v:143621$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230565,10 +233062,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141989$6568_Y + connect \Y $and$libresoc.v:143621$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:141990$6569 + cell $and $and$libresoc.v:143622$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230576,10 +233073,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:141990$6569_Y + connect \Y $and$libresoc.v:143622$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:141991$6570 + cell $and $and$libresoc.v:143623$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230587,10 +233084,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:141991$6570_Y + connect \Y $and$libresoc.v:143623$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:141992$6571 + cell $and $and$libresoc.v:143624$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230598,10 +233095,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141992$6571_Y + connect \Y $and$libresoc.v:143624$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:141993$6572 + cell $and $and$libresoc.v:143625$6620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230609,10 +233106,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141993$6572_Y + connect \Y $and$libresoc.v:143625$6620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:141995$6574 + cell $and $and$libresoc.v:143627$6622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230620,10 +233117,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:141995$6574_Y + connect \Y $and$libresoc.v:143627$6622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:141997$6576 + cell $and $and$libresoc.v:143629$6624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230631,10 +233128,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:141997$6576_Y + connect \Y $and$libresoc.v:143629$6624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:141998$6577 + cell $and $and$libresoc.v:143630$6625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230642,10 +233139,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:141998$6577_Y + connect \Y $and$libresoc.v:143630$6625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:141999$6578 + cell $and $and$libresoc.v:143631$6626 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230653,10 +233150,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:141999$6578_Y + connect \Y $and$libresoc.v:143631$6626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:142001$6580 + cell $and $and$libresoc.v:143633$6628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230664,10 +233161,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:142001$6580_Y + connect \Y $and$libresoc.v:143633$6628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:142004$6583 + cell $and $and$libresoc.v:143636$6631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230675,10 +233172,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:142004$6583_Y + connect \Y $and$libresoc.v:143636$6631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:142009$6588 + cell $and $and$libresoc.v:143641$6636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230686,10 +233183,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:142009$6588_Y + connect \Y $and$libresoc.v:143641$6636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:142010$6589 + cell $and $and$libresoc.v:143642$6637 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230697,10 +233194,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:142010$6589_Y + connect \Y $and$libresoc.v:143642$6637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:142012$6591 + cell $and $and$libresoc.v:143644$6639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230708,10 +233205,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:142012$6591_Y + connect \Y $and$libresoc.v:143644$6639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142015$6594 + cell $and $and$libresoc.v:143647$6642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230719,10 +233216,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:142015$6594_Y + connect \Y $and$libresoc.v:143647$6642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142016$6595 + cell $and $and$libresoc.v:143648$6643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230730,10 +233227,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:142016$6595_Y + connect \Y $and$libresoc.v:143648$6643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142017$6596 + cell $and $and$libresoc.v:143649$6644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230741,10 +233238,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:142017$6596_Y + connect \Y $and$libresoc.v:143649$6644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:142022$6601 + cell $and $and$libresoc.v:143654$6649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230752,10 +233249,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:142022$6601_Y + connect \Y $and$libresoc.v:143654$6649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:142023$6602 + cell $and $and$libresoc.v:143655$6650 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230763,10 +233260,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:142023$6602_Y + connect \Y $and$libresoc.v:143655$6650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:142026$6605 + cell $and $and$libresoc.v:143658$6653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230774,10 +233271,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:142026$6605_Y + connect \Y $and$libresoc.v:143658$6653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:142027$6606 + cell $and $and$libresoc.v:143659$6654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230785,10 +233282,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:142027$6606_Y + connect \Y $and$libresoc.v:143659$6654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:142036$6615 + cell $and $and$libresoc.v:143668$6663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230796,10 +233293,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:142036$6615_Y + connect \Y $and$libresoc.v:143668$6663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:142037$6616 + cell $and $and$libresoc.v:143669$6664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230807,10 +233304,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:142037$6616_Y + connect \Y $and$libresoc.v:143669$6664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:142038$6617 + cell $and $and$libresoc.v:143670$6665 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230818,10 +233315,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:142038$6617_Y + connect \Y $and$libresoc.v:143670$6665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:142011$6590 + cell $eq $eq$libresoc.v:143643$6638 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230829,10 +233326,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:142011$6590_Y + connect \Y $eq$libresoc.v:143643$6638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:142013$6592 + cell $eq $eq$libresoc.v:143645$6640 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230840,82 +233337,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:142013$6592_Y + connect \Y $eq$libresoc.v:143645$6640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:141986$6565 + cell $not $not$libresoc.v:143618$6613 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:141986$6565_Y + connect \Y $not$libresoc.v:143618$6613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:141994$6573 + cell $not $not$libresoc.v:143626$6621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:141994$6573_Y + connect \Y $not$libresoc.v:143626$6621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:141996$6575 + cell $not $not$libresoc.v:143628$6623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:141996$6575_Y + connect \Y $not$libresoc.v:143628$6623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:142000$6579 + cell $not $not$libresoc.v:143632$6627 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:142000$6579_Y + connect \Y $not$libresoc.v:143632$6627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:142003$6582 + cell $not $not$libresoc.v:143635$6630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:142003$6582_Y + connect \Y $not$libresoc.v:143635$6630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:142008$6587 + cell $not $not$libresoc.v:143640$6635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:142008$6587_Y + connect \Y $not$libresoc.v:143640$6635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:142014$6593 + cell $not $not$libresoc.v:143646$6641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:142014$6593_Y + connect \Y $not$libresoc.v:143646$6641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:142039$6618 + cell $not $not$libresoc.v:143671$6666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:142039$6618_Y + connect \Y $not$libresoc.v:143671$6666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:142040$6619 + cell $not $not$libresoc.v:143672$6667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:142040$6619_Y + connect \Y $not$libresoc.v:143672$6667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:142007$6586 + cell $or $or$libresoc.v:143639$6634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230923,10 +233420,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:142007$6586_Y + connect \Y $or$libresoc.v:143639$6634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:142018$6597 + cell $or $or$libresoc.v:143650$6645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230934,10 +233431,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142018$6597_Y + connect \Y $or$libresoc.v:143650$6645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:142019$6598 + cell $or $or$libresoc.v:143651$6646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230945,10 +233442,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142019$6598_Y + connect \Y $or$libresoc.v:143651$6646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:142020$6599 + cell $or $or$libresoc.v:143652$6647 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230956,10 +233453,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:142020$6599_Y + connect \Y $or$libresoc.v:143652$6647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:142021$6600 + cell $or $or$libresoc.v:143653$6648 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230967,10 +233464,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:142021$6600_Y + connect \Y $or$libresoc.v:143653$6648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:142024$6603 + cell $or $or$libresoc.v:143656$6651 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230978,10 +233475,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:142024$6603_Y + connect \Y $or$libresoc.v:143656$6651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:142025$6604 + cell $or $or$libresoc.v:143657$6652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230989,98 +233486,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:142025$6604_Y + connect \Y $or$libresoc.v:143657$6652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:142031$6610 + cell $reduce_and $reduce_and$libresoc.v:143663$6658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:142031$6610_Y + connect \Y $reduce_and$libresoc.v:143663$6658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:142002$6581 + cell $reduce_or $reduce_or$libresoc.v:143634$6629 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:142002$6581_Y + connect \Y $reduce_or$libresoc.v:143634$6629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:142005$6584 + cell $reduce_or $reduce_or$libresoc.v:143637$6632 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:142005$6584_Y + connect \Y $reduce_or$libresoc.v:143637$6632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:142006$6585 + cell $reduce_or $reduce_or$libresoc.v:143638$6633 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:142006$6585_Y + connect \Y $reduce_or$libresoc.v:143638$6633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:142028$6607 + cell $mux $ternary$libresoc.v:143660$6655 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:142028$6607_Y + connect \Y $ternary$libresoc.v:143660$6655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:142029$6608 + cell $mux $ternary$libresoc.v:143661$6656 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:142029$6608_Y + connect \Y $ternary$libresoc.v:143661$6656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:142030$6609 + cell $mux $ternary$libresoc.v:143662$6657 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:142030$6609_Y + connect \Y $ternary$libresoc.v:143662$6657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:142032$6611 + cell $mux $ternary$libresoc.v:143664$6659 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:142032$6611_Y + connect \Y $ternary$libresoc.v:143664$6659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142033$6612 + cell $mux $ternary$libresoc.v:143665$6660 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:142033$6612_Y + connect \Y $ternary$libresoc.v:143665$6660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142034$6613 + cell $mux $ternary$libresoc.v:143666$6661 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:142034$6613_Y + connect \Y $ternary$libresoc.v:143666$6661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142035$6614 + cell $mux $ternary$libresoc.v:143667$6662 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:142035$6614_Y + connect \Y $ternary$libresoc.v:143667$6662_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142121.14-142127.4" + attribute \src "libresoc.v:143753.14-143759.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231089,7 +233586,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:142128.16-142160.4" + attribute \src "libresoc.v:143760.16-143792.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231124,7 +233621,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:142161.15-142167.4" + attribute \src "libresoc.v:143793.15-143799.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231133,7 +233630,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:142168.14-142174.4" + attribute \src "libresoc.v:143800.14-143806.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231142,7 +233639,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:142175.14-142181.4" + attribute \src "libresoc.v:143807.14-143813.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231151,7 +233648,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:142182.14-142188.4" + attribute \src "libresoc.v:143814.14-143820.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231160,7 +233657,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:142189.14-142194.4" + attribute \src "libresoc.v:143821.14-143826.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231168,7 +233665,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:142195.14-142201.4" + attribute \src "libresoc.v:143827.14-143833.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231176,622 +233673,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:141375.7-141375.20" - process $proc$libresoc.v:141375$6770 + attribute \src "libresoc.v:143007.7-143007.20" + process $proc$libresoc.v:143007$6818 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141493.7-141493.24" - process $proc$libresoc.v:141493$6771 + attribute \src "libresoc.v:143125.7-143125.24" + process $proc$libresoc.v:143125$6819 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:141503.7-141503.26" - process $proc$libresoc.v:141503$6772 + attribute \src "libresoc.v:143135.7-143135.26" + process $proc$libresoc.v:143135$6820 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:141511.7-141511.25" - process $proc$libresoc.v:141511$6773 + attribute \src "libresoc.v:143143.7-143143.25" + process $proc$libresoc.v:143143$6821 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:141519.13-141519.53" - process $proc$libresoc.v:141519$6774 + attribute \src "libresoc.v:143151.13-143151.53" + process $proc$libresoc.v:143151$6822 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:141538.14-141538.57" - process $proc$libresoc.v:141538$6775 + attribute \src "libresoc.v:143170.14-143170.57" + process $proc$libresoc.v:143170$6823 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:141542.14-141542.76" - process $proc$libresoc.v:141542$6776 + attribute \src "libresoc.v:143174.14-143174.76" + process $proc$libresoc.v:143174$6824 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:141546.7-141546.51" - process $proc$libresoc.v:141546$6777 + attribute \src "libresoc.v:143178.7-143178.51" + process $proc$libresoc.v:143178$6825 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:141554.13-141554.56" - process $proc$libresoc.v:141554$6778 + attribute \src "libresoc.v:143186.13-143186.56" + process $proc$libresoc.v:143186$6826 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:141558.14-141558.51" - process $proc$libresoc.v:141558$6779 + attribute \src "libresoc.v:143190.14-143190.51" + process $proc$libresoc.v:143190$6827 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:141637.13-141637.55" - process $proc$libresoc.v:141637$6780 + attribute \src "libresoc.v:143269.13-143269.55" + process $proc$libresoc.v:143269$6828 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:141641.7-141641.48" - process $proc$libresoc.v:141641$6781 + attribute \src "libresoc.v:143273.7-143273.48" + process $proc$libresoc.v:143273$6829 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:141645.7-141645.49" - process $proc$libresoc.v:141645$6782 + attribute \src "libresoc.v:143277.7-143277.49" + process $proc$libresoc.v:143277$6830 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:141649.7-141649.47" - process $proc$libresoc.v:141649$6783 + attribute \src "libresoc.v:143281.7-143281.47" + process $proc$libresoc.v:143281$6831 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:141653.7-141653.48" - process $proc$libresoc.v:141653$6784 + attribute \src "libresoc.v:143285.7-143285.48" + process $proc$libresoc.v:143285$6832 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:141657.7-141657.45" - process $proc$libresoc.v:141657$6785 + attribute \src "libresoc.v:143289.7-143289.45" + process $proc$libresoc.v:143289$6833 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:141661.7-141661.45" - process $proc$libresoc.v:141661$6786 + attribute \src "libresoc.v:143293.7-143293.45" + process $proc$libresoc.v:143293$6834 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:141665.7-141665.51" - process $proc$libresoc.v:141665$6787 + attribute \src "libresoc.v:143297.7-143297.51" + process $proc$libresoc.v:143297$6835 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:141669.7-141669.45" - process $proc$libresoc.v:141669$6788 + attribute \src "libresoc.v:143301.7-143301.45" + process $proc$libresoc.v:143301$6836 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:141673.7-141673.45" - process $proc$libresoc.v:141673$6789 + attribute \src "libresoc.v:143305.7-143305.45" + process $proc$libresoc.v:143305$6837 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:141677.7-141677.48" - process $proc$libresoc.v:141677$6790 + attribute \src "libresoc.v:143309.7-143309.48" + process $proc$libresoc.v:143309$6838 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:141681.7-141681.45" - process $proc$libresoc.v:141681$6791 + attribute \src "libresoc.v:143313.7-143313.45" + process $proc$libresoc.v:143313$6839 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:141707.7-141707.27" - process $proc$libresoc.v:141707$6792 + attribute \src "libresoc.v:143339.7-143339.27" + process $proc$libresoc.v:143339$6840 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:141741.14-141741.47" - process $proc$libresoc.v:141741$6793 + attribute \src "libresoc.v:143373.14-143373.47" + process $proc$libresoc.v:143373$6841 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:141745.7-141745.27" - process $proc$libresoc.v:141745$6794 + attribute \src "libresoc.v:143377.7-143377.27" + process $proc$libresoc.v:143377$6842 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:141749.13-141749.33" - process $proc$libresoc.v:141749$6795 + attribute \src "libresoc.v:143381.13-143381.33" + process $proc$libresoc.v:143381$6843 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:141753.7-141753.30" - process $proc$libresoc.v:141753$6796 + attribute \src "libresoc.v:143385.7-143385.30" + process $proc$libresoc.v:143385$6844 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:141767.7-141767.25" - process $proc$libresoc.v:141767$6797 + attribute \src "libresoc.v:143399.7-143399.25" + process $proc$libresoc.v:143399$6845 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141771.7-141771.25" - process $proc$libresoc.v:141771$6798 + attribute \src "libresoc.v:143403.7-143403.25" + process $proc$libresoc.v:143403$6846 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141905.13-141905.30" - process $proc$libresoc.v:141905$6799 + attribute \src "libresoc.v:143537.13-143537.30" + process $proc$libresoc.v:143537$6847 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:141913.13-141913.31" - process $proc$libresoc.v:141913$6800 + attribute \src "libresoc.v:143545.13-143545.31" + process $proc$libresoc.v:143545$6848 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:141917.13-141917.31" - process $proc$libresoc.v:141917$6801 + attribute \src "libresoc.v:143549.13-143549.31" + process $proc$libresoc.v:143549$6849 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:141929.7-141929.26" - process $proc$libresoc.v:141929$6802 + attribute \src "libresoc.v:143561.7-143561.26" + process $proc$libresoc.v:143561$6850 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:141933.7-141933.26" - process $proc$libresoc.v:141933$6803 + attribute \src "libresoc.v:143565.7-143565.26" + process $proc$libresoc.v:143565$6851 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:141937.7-141937.25" - process $proc$libresoc.v:141937$6804 + attribute \src "libresoc.v:143569.7-143569.25" + process $proc$libresoc.v:143569$6852 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:141941.7-141941.25" - process $proc$libresoc.v:141941$6805 + attribute \src "libresoc.v:143573.7-143573.25" + process $proc$libresoc.v:143573$6853 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:141955.13-141955.31" - process $proc$libresoc.v:141955$6806 + attribute \src "libresoc.v:143587.13-143587.31" + process $proc$libresoc.v:143587$6854 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:141959.13-141959.31" - process $proc$libresoc.v:141959$6807 + attribute \src "libresoc.v:143591.13-143591.31" + process $proc$libresoc.v:143591$6855 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:141967.14-141967.43" - process $proc$libresoc.v:141967$6808 + attribute \src "libresoc.v:143599.14-143599.43" + process $proc$libresoc.v:143599$6856 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:141971.14-141971.43" - process $proc$libresoc.v:141971$6809 + attribute \src "libresoc.v:143603.14-143603.43" + process $proc$libresoc.v:143603$6857 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:141975.7-141975.20" - process $proc$libresoc.v:141975$6810 + attribute \src "libresoc.v:143607.7-143607.20" + process $proc$libresoc.v:143607$6858 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:142041.3-142042.39" - process $proc$libresoc.v:142041$6620 + attribute \src "libresoc.v:143673.3-143674.39" + process $proc$libresoc.v:143673$6668 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:142043.3-142044.43" - process $proc$libresoc.v:142043$6621 + attribute \src "libresoc.v:143675.3-143676.43" + process $proc$libresoc.v:143675$6669 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:142045.3-142046.29" - process $proc$libresoc.v:142045$6622 + attribute \src "libresoc.v:143677.3-143678.29" + process $proc$libresoc.v:143677$6670 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:142047.3-142048.29" - process $proc$libresoc.v:142047$6623 + attribute \src "libresoc.v:143679.3-143680.29" + process $proc$libresoc.v:143679$6671 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:142049.3-142050.29" - process $proc$libresoc.v:142049$6624 + attribute \src "libresoc.v:143681.3-143682.29" + process $proc$libresoc.v:143681$6672 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:142051.3-142052.43" - process $proc$libresoc.v:142051$6625 + attribute \src "libresoc.v:143683.3-143684.43" + process $proc$libresoc.v:143683$6673 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:142053.3-142054.49" - process $proc$libresoc.v:142053$6626 + attribute \src "libresoc.v:143685.3-143686.49" + process $proc$libresoc.v:143685$6674 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:142055.3-142056.37" - process $proc$libresoc.v:142055$6627 + attribute \src "libresoc.v:143687.3-143688.37" + process $proc$libresoc.v:143687$6675 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:142057.3-142058.43" - process $proc$libresoc.v:142057$6628 + attribute \src "libresoc.v:143689.3-143690.43" + process $proc$libresoc.v:143689$6676 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:142059.3-142060.85" - process $proc$libresoc.v:142059$6629 + attribute \src "libresoc.v:143691.3-143692.85" + process $proc$libresoc.v:143691$6677 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:142061.3-142062.81" - process $proc$libresoc.v:142061$6630 + attribute \src "libresoc.v:143693.3-143694.81" + process $proc$libresoc.v:143693$6678 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:142063.3-142064.95" - process $proc$libresoc.v:142063$6631 + attribute \src "libresoc.v:143695.3-143696.95" + process $proc$libresoc.v:143695$6679 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142065.3-142066.91" - process $proc$libresoc.v:142065$6632 + attribute \src "libresoc.v:143697.3-143698.91" + process $proc$libresoc.v:143697$6680 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142067.3-142068.79" - process $proc$libresoc.v:142067$6633 + attribute \src "libresoc.v:143699.3-143700.79" + process $proc$libresoc.v:143699$6681 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:142069.3-142070.79" - process $proc$libresoc.v:142069$6634 + attribute \src "libresoc.v:143701.3-143702.79" + process $proc$libresoc.v:143701$6682 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:142071.3-142072.79" - process $proc$libresoc.v:142071$6635 + attribute \src "libresoc.v:143703.3-143704.79" + process $proc$libresoc.v:143703$6683 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:142073.3-142074.79" - process $proc$libresoc.v:142073$6636 + attribute \src "libresoc.v:143705.3-143706.79" + process $proc$libresoc.v:143705$6684 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:142075.3-142076.85" - process $proc$libresoc.v:142075$6637 + attribute \src "libresoc.v:143707.3-143708.85" + process $proc$libresoc.v:143707$6685 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:142077.3-142078.79" - process $proc$libresoc.v:142077$6638 + attribute \src "libresoc.v:143709.3-143710.79" + process $proc$libresoc.v:143709$6686 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:142079.3-142080.89" - process $proc$libresoc.v:142079$6639 + attribute \src "libresoc.v:143711.3-143712.89" + process $proc$libresoc.v:143711$6687 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:142081.3-142082.87" - process $proc$libresoc.v:142081$6640 + attribute \src "libresoc.v:143713.3-143714.87" + process $proc$libresoc.v:143713$6688 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:142083.3-142084.85" - process $proc$libresoc.v:142083$6641 + attribute \src "libresoc.v:143715.3-143716.85" + process $proc$libresoc.v:143715$6689 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:142085.3-142086.91" - process $proc$libresoc.v:142085$6642 + attribute \src "libresoc.v:143717.3-143718.91" + process $proc$libresoc.v:143717$6690 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:142087.3-142088.83" - process $proc$libresoc.v:142087$6643 + attribute \src "libresoc.v:143719.3-143720.83" + process $proc$libresoc.v:143719$6691 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:142089.3-142090.85" - process $proc$libresoc.v:142089$6644 + attribute \src "libresoc.v:143721.3-143722.85" + process $proc$libresoc.v:143721$6692 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:142091.3-142092.83" - process $proc$libresoc.v:142091$6645 + attribute \src "libresoc.v:143723.3-143724.83" + process $proc$libresoc.v:143723$6693 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:142093.3-142094.75" - process $proc$libresoc.v:142093$6646 + attribute \src "libresoc.v:143725.3-143726.75" + process $proc$libresoc.v:143725$6694 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:142095.3-142096.39" - process $proc$libresoc.v:142095$6647 + attribute \src "libresoc.v:143727.3-143728.39" + process $proc$libresoc.v:143727$6695 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:142097.3-142098.39" - process $proc$libresoc.v:142097$6648 + attribute \src "libresoc.v:143729.3-143730.39" + process $proc$libresoc.v:143729$6696 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:142099.3-142100.39" - process $proc$libresoc.v:142099$6649 + attribute \src "libresoc.v:143731.3-143732.39" + process $proc$libresoc.v:143731$6697 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:142101.3-142102.39" - process $proc$libresoc.v:142101$6650 + attribute \src "libresoc.v:143733.3-143734.39" + process $proc$libresoc.v:143733$6698 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:142103.3-142104.39" - process $proc$libresoc.v:142103$6651 + attribute \src "libresoc.v:143735.3-143736.39" + process $proc$libresoc.v:143735$6699 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:142105.3-142106.39" - process $proc$libresoc.v:142105$6652 + attribute \src "libresoc.v:143737.3-143738.39" + process $proc$libresoc.v:143737$6700 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:142107.3-142108.39" - process $proc$libresoc.v:142107$6653 + attribute \src "libresoc.v:143739.3-143740.39" + process $proc$libresoc.v:143739$6701 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:142109.3-142110.39" - process $proc$libresoc.v:142109$6654 + attribute \src "libresoc.v:143741.3-143742.39" + process $proc$libresoc.v:143741$6702 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:142111.3-142112.41" - process $proc$libresoc.v:142111$6655 + attribute \src "libresoc.v:143743.3-143744.41" + process $proc$libresoc.v:143743$6703 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:142113.3-142114.41" - process $proc$libresoc.v:142113$6656 + attribute \src "libresoc.v:143745.3-143746.41" + process $proc$libresoc.v:143745$6704 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:142115.3-142116.37" - process $proc$libresoc.v:142115$6657 + attribute \src "libresoc.v:143747.3-143748.37" + process $proc$libresoc.v:143747$6705 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:142117.3-142118.44" - process $proc$libresoc.v:142117$6658 + attribute \src "libresoc.v:143749.3-143750.44" + process $proc$libresoc.v:143749$6706 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:142119.3-142120.24" - process $proc$libresoc.v:142119$6659 + attribute \src "libresoc.v:143751.3-143752.24" + process $proc$libresoc.v:143751$6707 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:142202.3-142211.6" - process $proc$libresoc.v:142202$6660 + attribute \src "libresoc.v:143834.3-143843.6" + process $proc$libresoc.v:143834$6708 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:142203.5-142203.29" + attribute \src "libresoc.v:143835.5-143835.29" switch \initial - attribute \src "libresoc.v:142203.9-142203.17" + attribute \src "libresoc.v:143835.9-143835.17" case 1'1 case end @@ -231807,14 +234304,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:142212.3-142220.6" - process $proc$libresoc.v:142212$6661 + attribute \src "libresoc.v:143844.3-143852.6" + process $proc$libresoc.v:143844$6709 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6662 $1\rok_l_s_rdok$next[0:0]$6663 - attribute \src "libresoc.v:142213.5-142213.29" + assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143845.5-143845.29" switch \initial - attribute \src "libresoc.v:142213.9-142213.17" + attribute \src "libresoc.v:143845.9-143845.17" case 1'1 case end @@ -231823,21 +234320,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6663 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6711 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6663 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6711 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6662 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 end - attribute \src "libresoc.v:142221.3-142229.6" - process $proc$libresoc.v:142221$6664 + attribute \src "libresoc.v:143853.3-143861.6" + process $proc$libresoc.v:143853$6712 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6665 $1\rok_l_r_rdok$next[0:0]$6666 - attribute \src "libresoc.v:142222.5-142222.29" + assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143854.5-143854.29" switch \initial - attribute \src "libresoc.v:142222.9-142222.17" + attribute \src "libresoc.v:143854.9-143854.17" case 1'1 case end @@ -231846,21 +234343,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6666 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6714 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6666 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6714 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6665 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 end - attribute \src "libresoc.v:142230.3-142238.6" - process $proc$libresoc.v:142230$6667 + attribute \src "libresoc.v:143862.3-143870.6" + process $proc$libresoc.v:143862$6715 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6668 $1\rst_l_s_rst$next[0:0]$6669 - attribute \src "libresoc.v:142231.5-142231.29" + assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143863.5-143863.29" switch \initial - attribute \src "libresoc.v:142231.9-142231.17" + attribute \src "libresoc.v:143863.9-143863.17" case 1'1 case end @@ -231869,21 +234366,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6669 1'0 + assign $1\rst_l_s_rst$next[0:0]$6717 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6669 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6717 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6668 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 end - attribute \src "libresoc.v:142239.3-142247.6" - process $proc$libresoc.v:142239$6670 + attribute \src "libresoc.v:143871.3-143879.6" + process $proc$libresoc.v:143871$6718 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6671 $1\rst_l_r_rst$next[0:0]$6672 - attribute \src "libresoc.v:142240.5-142240.29" + assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143872.5-143872.29" switch \initial - attribute \src "libresoc.v:142240.9-142240.17" + attribute \src "libresoc.v:143872.9-143872.17" case 1'1 case end @@ -231892,21 +234389,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6672 1'1 + assign $1\rst_l_r_rst$next[0:0]$6720 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6672 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6720 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6671 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 end - attribute \src "libresoc.v:142248.3-142256.6" - process $proc$libresoc.v:142248$6673 + attribute \src "libresoc.v:143880.3-143888.6" + process $proc$libresoc.v:143880$6721 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6674 $1\opc_l_s_opc$next[0:0]$6675 - attribute \src "libresoc.v:142249.5-142249.29" + assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143881.5-143881.29" switch \initial - attribute \src "libresoc.v:142249.9-142249.17" + attribute \src "libresoc.v:143881.9-143881.17" case 1'1 case end @@ -231915,21 +234412,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6675 1'0 + assign $1\opc_l_s_opc$next[0:0]$6723 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6675 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6723 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6674 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 end - attribute \src "libresoc.v:142257.3-142265.6" - process $proc$libresoc.v:142257$6676 + attribute \src "libresoc.v:143889.3-143897.6" + process $proc$libresoc.v:143889$6724 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6677 $1\opc_l_r_opc$next[0:0]$6678 - attribute \src "libresoc.v:142258.5-142258.29" + assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143890.5-143890.29" switch \initial - attribute \src "libresoc.v:142258.9-142258.17" + attribute \src "libresoc.v:143890.9-143890.17" case 1'1 case end @@ -231938,21 +234435,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6678 1'1 + assign $1\opc_l_r_opc$next[0:0]$6726 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6678 \req_done + assign $1\opc_l_r_opc$next[0:0]$6726 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6677 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 end - attribute \src "libresoc.v:142266.3-142274.6" - process $proc$libresoc.v:142266$6679 + attribute \src "libresoc.v:143898.3-143906.6" + process $proc$libresoc.v:143898$6727 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6680 $1\src_l_s_src$next[2:0]$6681 - attribute \src "libresoc.v:142267.5-142267.29" + assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143899.5-143899.29" switch \initial - attribute \src "libresoc.v:142267.9-142267.17" + attribute \src "libresoc.v:143899.9-143899.17" case 1'1 case end @@ -231961,21 +234458,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6681 3'000 + assign $1\src_l_s_src$next[2:0]$6729 3'000 case - assign $1\src_l_s_src$next[2:0]$6681 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6729 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6680 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 end - attribute \src "libresoc.v:142275.3-142283.6" - process $proc$libresoc.v:142275$6682 + attribute \src "libresoc.v:143907.3-143915.6" + process $proc$libresoc.v:143907$6730 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6683 $1\src_l_r_src$next[2:0]$6684 - attribute \src "libresoc.v:142276.5-142276.29" + assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143908.5-143908.29" switch \initial - attribute \src "libresoc.v:142276.9-142276.17" + attribute \src "libresoc.v:143908.9-143908.17" case 1'1 case end @@ -231984,21 +234481,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6684 3'111 + assign $1\src_l_r_src$next[2:0]$6732 3'111 case - assign $1\src_l_r_src$next[2:0]$6684 \reset_r + assign $1\src_l_r_src$next[2:0]$6732 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6683 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 end - attribute \src "libresoc.v:142284.3-142292.6" - process $proc$libresoc.v:142284$6685 + attribute \src "libresoc.v:143916.3-143924.6" + process $proc$libresoc.v:143916$6733 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6686 $1\req_l_s_req$next[1:0]$6687 - attribute \src "libresoc.v:142285.5-142285.29" + assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143917.5-143917.29" switch \initial - attribute \src "libresoc.v:142285.9-142285.17" + attribute \src "libresoc.v:143917.9-143917.17" case 1'1 case end @@ -232007,21 +234504,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6687 2'00 + assign $1\req_l_s_req$next[1:0]$6735 2'00 case - assign $1\req_l_s_req$next[1:0]$6687 \$65 + assign $1\req_l_s_req$next[1:0]$6735 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6686 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 end - attribute \src "libresoc.v:142293.3-142301.6" - process $proc$libresoc.v:142293$6688 + attribute \src "libresoc.v:143925.3-143933.6" + process $proc$libresoc.v:143925$6736 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6689 $1\req_l_r_req$next[1:0]$6690 - attribute \src "libresoc.v:142294.5-142294.29" + assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143926.5-143926.29" switch \initial - attribute \src "libresoc.v:142294.9-142294.17" + attribute \src "libresoc.v:143926.9-143926.17" case 1'1 case end @@ -232030,15 +234527,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6690 2'11 + assign $1\req_l_r_req$next[1:0]$6738 2'11 case - assign $1\req_l_r_req$next[1:0]$6690 \$67 + assign $1\req_l_r_req$next[1:0]$6738 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6689 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 end - attribute \src "libresoc.v:142302.3-142340.6" - process $proc$libresoc.v:142302$6691 + attribute \src "libresoc.v:143934.3-143972.6" + process $proc$libresoc.v:143934$6739 assign { } { } assign { } { } assign { } { } @@ -232075,33 +234572,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6692 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 - assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6740 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6697 $1\alu_logical0_logical_op__insn$next[31:0]$6715 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6745 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 - attribute \src "libresoc.v:142303.5-142303.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143935.5-143935.29" switch \initial - attribute \src "libresoc.v:142303.9-142303.17" + attribute \src "libresoc.v:143935.9-143935.17" case 1'1 case end @@ -232127,26 +234624,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6715 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6763 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6710 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6715 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6758 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6763 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -232158,54 +234655,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6692 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6697 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6745 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 end - attribute \src "libresoc.v:142341.3-142362.6" - process $proc$libresoc.v:142341$6734 + attribute \src "libresoc.v:143973.3-143994.6" + process $proc$libresoc.v:143973$6782 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6735 $2\data_r0__o$next[63:0]$6739 + assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6736 $3\data_r0__o_ok$next[0:0]$6741 - attribute \src "libresoc.v:142342.5-142342.29" + assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 + attribute \src "libresoc.v:143974.5-143974.29" switch \initial - attribute \src "libresoc.v:142342.9-142342.17" + attribute \src "libresoc.v:143974.9-143974.17" case 1'1 case end @@ -232215,10 +234712,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6738 $1\data_r0__o$next[63:0]$6737 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6786 $1\data_r0__o$next[63:0]$6785 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6737 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6738 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6785 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6786 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -232226,38 +234723,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6740 $2\data_r0__o$next[63:0]$6739 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6788 $2\data_r0__o$next[63:0]$6787 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6739 $1\data_r0__o$next[63:0]$6737 - assign $2\data_r0__o_ok$next[0:0]$6740 $1\data_r0__o_ok$next[0:0]$6738 + assign $2\data_r0__o$next[63:0]$6787 $1\data_r0__o$next[63:0]$6785 + assign $2\data_r0__o_ok$next[0:0]$6788 $1\data_r0__o_ok$next[0:0]$6786 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6741 1'0 + assign $3\data_r0__o_ok$next[0:0]$6789 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6741 $2\data_r0__o_ok$next[0:0]$6740 + assign $3\data_r0__o_ok$next[0:0]$6789 $2\data_r0__o_ok$next[0:0]$6788 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6735 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6736 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 end - attribute \src "libresoc.v:142363.3-142384.6" - process $proc$libresoc.v:142363$6742 + attribute \src "libresoc.v:143995.3-144016.6" + process $proc$libresoc.v:143995$6790 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6743 $2\data_r1__cr_a$next[3:0]$6747 + assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6744 $3\data_r1__cr_a_ok$next[0:0]$6749 - attribute \src "libresoc.v:142364.5-142364.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 + attribute \src "libresoc.v:143996.5-143996.29" switch \initial - attribute \src "libresoc.v:142364.9-142364.17" + attribute \src "libresoc.v:143996.9-143996.17" case 1'1 case end @@ -232267,10 +234764,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6746 $1\data_r1__cr_a$next[3:0]$6745 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6794 $1\data_r1__cr_a$next[3:0]$6793 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6745 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6746 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6793 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6794 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -232278,32 +234775,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6748 $2\data_r1__cr_a$next[3:0]$6747 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6796 $2\data_r1__cr_a$next[3:0]$6795 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6747 $1\data_r1__cr_a$next[3:0]$6745 - assign $2\data_r1__cr_a_ok$next[0:0]$6748 $1\data_r1__cr_a_ok$next[0:0]$6746 + assign $2\data_r1__cr_a$next[3:0]$6795 $1\data_r1__cr_a$next[3:0]$6793 + assign $2\data_r1__cr_a_ok$next[0:0]$6796 $1\data_r1__cr_a_ok$next[0:0]$6794 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6749 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6797 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6749 $2\data_r1__cr_a_ok$next[0:0]$6748 + assign $3\data_r1__cr_a_ok$next[0:0]$6797 $2\data_r1__cr_a_ok$next[0:0]$6796 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6743 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6744 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 end - attribute \src "libresoc.v:142385.3-142394.6" - process $proc$libresoc.v:142385$6750 + attribute \src "libresoc.v:144017.3-144026.6" + process $proc$libresoc.v:144017$6798 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6751 $1\src_r0$next[63:0]$6752 - attribute \src "libresoc.v:142386.5-142386.29" + assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:144018.5-144018.29" switch \initial - attribute \src "libresoc.v:142386.9-142386.17" + attribute \src "libresoc.v:144018.9-144018.17" case 1'1 case end @@ -232312,21 +234809,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6752 \src_or_imm + assign $1\src_r0$next[63:0]$6800 \src_or_imm case - assign $1\src_r0$next[63:0]$6752 \src_r0 + assign $1\src_r0$next[63:0]$6800 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6751 + update \src_r0$next $0\src_r0$next[63:0]$6799 end - attribute \src "libresoc.v:142395.3-142404.6" - process $proc$libresoc.v:142395$6753 + attribute \src "libresoc.v:144027.3-144036.6" + process $proc$libresoc.v:144027$6801 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6754 $1\src_r1$next[63:0]$6755 - attribute \src "libresoc.v:142396.5-142396.29" + assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:144028.5-144028.29" switch \initial - attribute \src "libresoc.v:142396.9-142396.17" + attribute \src "libresoc.v:144028.9-144028.17" case 1'1 case end @@ -232335,21 +234832,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6755 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6803 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6755 \src_r1 + assign $1\src_r1$next[63:0]$6803 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6754 + update \src_r1$next $0\src_r1$next[63:0]$6802 end - attribute \src "libresoc.v:142405.3-142414.6" - process $proc$libresoc.v:142405$6756 + attribute \src "libresoc.v:144037.3-144046.6" + process $proc$libresoc.v:144037$6804 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6757 $1\src_r2$next[0:0]$6758 - attribute \src "libresoc.v:142406.5-142406.29" + assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:144038.5-144038.29" switch \initial - attribute \src "libresoc.v:142406.9-142406.17" + attribute \src "libresoc.v:144038.9-144038.17" case 1'1 case end @@ -232358,21 +234855,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6758 \src3_i + assign $1\src_r2$next[0:0]$6806 \src3_i case - assign $1\src_r2$next[0:0]$6758 \src_r2 + assign $1\src_r2$next[0:0]$6806 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6757 + update \src_r2$next $0\src_r2$next[0:0]$6805 end - attribute \src "libresoc.v:142415.3-142423.6" - process $proc$libresoc.v:142415$6759 + attribute \src "libresoc.v:144047.3-144055.6" + process $proc$libresoc.v:144047$6807 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6760 $1\alui_l_r_alui$next[0:0]$6761 - attribute \src "libresoc.v:142416.5-142416.29" + assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:144048.5-144048.29" switch \initial - attribute \src "libresoc.v:142416.9-142416.17" + attribute \src "libresoc.v:144048.9-144048.17" case 1'1 case end @@ -232381,21 +234878,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6761 1'1 + assign $1\alui_l_r_alui$next[0:0]$6809 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6761 \$89 + assign $1\alui_l_r_alui$next[0:0]$6809 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6760 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 end - attribute \src "libresoc.v:142424.3-142432.6" - process $proc$libresoc.v:142424$6762 + attribute \src "libresoc.v:144056.3-144064.6" + process $proc$libresoc.v:144056$6810 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6763 $1\alu_l_r_alu$next[0:0]$6764 - attribute \src "libresoc.v:142425.5-142425.29" + assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:144057.5-144057.29" switch \initial - attribute \src "libresoc.v:142425.9-142425.17" + attribute \src "libresoc.v:144057.9-144057.17" case 1'1 case end @@ -232404,21 +234901,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6764 1'1 + assign $1\alu_l_r_alu$next[0:0]$6812 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6764 \$91 + assign $1\alu_l_r_alu$next[0:0]$6812 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6763 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 end - attribute \src "libresoc.v:142433.3-142442.6" - process $proc$libresoc.v:142433$6765 + attribute \src "libresoc.v:144065.3-144074.6" + process $proc$libresoc.v:144065$6813 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142434.5-142434.29" + attribute \src "libresoc.v:144066.5-144066.29" switch \initial - attribute \src "libresoc.v:142434.9-142434.17" + attribute \src "libresoc.v:144066.9-144066.17" case 1'1 case end @@ -232434,14 +234931,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142443.3-142452.6" - process $proc$libresoc.v:142443$6766 + attribute \src "libresoc.v:144075.3-144084.6" + process $proc$libresoc.v:144075$6814 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:142444.5-142444.29" + attribute \src "libresoc.v:144076.5-144076.29" switch \initial - attribute \src "libresoc.v:142444.9-142444.17" + attribute \src "libresoc.v:144076.9-144076.17" case 1'1 case end @@ -232457,14 +234954,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:142453.3-142461.6" - process $proc$libresoc.v:142453$6767 + attribute \src "libresoc.v:144085.3-144093.6" + process $proc$libresoc.v:144085$6815 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6768 $1\prev_wr_go$next[1:0]$6769 - attribute \src "libresoc.v:142454.5-142454.29" + assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:144086.5-144086.29" switch \initial - attribute \src "libresoc.v:142454.9-142454.17" + attribute \src "libresoc.v:144086.9-144086.17" case 1'1 case end @@ -232473,70 +234970,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6769 2'00 - case - assign $1\prev_wr_go$next[1:0]$6769 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6768 - end - connect \$9 $and$libresoc.v:141984$6563_Y - connect \$99 $and$libresoc.v:141985$6564_Y - connect \$101 $not$libresoc.v:141986$6565_Y - connect \$103 $and$libresoc.v:141987$6566_Y - connect \$105 $and$libresoc.v:141988$6567_Y - connect \$107 $and$libresoc.v:141989$6568_Y - connect \$109 $and$libresoc.v:141990$6569_Y - connect \$111 $and$libresoc.v:141991$6570_Y - connect \$113 $and$libresoc.v:141992$6571_Y - connect \$115 $and$libresoc.v:141993$6572_Y - connect \$11 $not$libresoc.v:141994$6573_Y - connect \$13 $and$libresoc.v:141995$6574_Y - connect \$15 $not$libresoc.v:141996$6575_Y - connect \$17 $and$libresoc.v:141997$6576_Y - connect \$1 $and$libresoc.v:141998$6577_Y - connect \$19 $and$libresoc.v:141999$6578_Y - connect \$23 $not$libresoc.v:142000$6579_Y - connect \$25 $and$libresoc.v:142001$6580_Y - connect \$22 $reduce_or$libresoc.v:142002$6581_Y - connect \$21 $not$libresoc.v:142003$6582_Y - connect \$29 $and$libresoc.v:142004$6583_Y - connect \$31 $reduce_or$libresoc.v:142005$6584_Y - connect \$33 $reduce_or$libresoc.v:142006$6585_Y - connect \$35 $or$libresoc.v:142007$6586_Y - connect \$37 $not$libresoc.v:142008$6587_Y - connect \$39 $and$libresoc.v:142009$6588_Y - connect \$41 $and$libresoc.v:142010$6589_Y - connect \$43 $eq$libresoc.v:142011$6590_Y - connect \$45 $and$libresoc.v:142012$6591_Y - connect \$47 $eq$libresoc.v:142013$6592_Y - connect \$4 $not$libresoc.v:142014$6593_Y - connect \$49 $and$libresoc.v:142015$6594_Y - connect \$51 $and$libresoc.v:142016$6595_Y - connect \$53 $and$libresoc.v:142017$6596_Y - connect \$55 $or$libresoc.v:142018$6597_Y - connect \$57 $or$libresoc.v:142019$6598_Y - connect \$59 $or$libresoc.v:142020$6599_Y - connect \$61 $or$libresoc.v:142021$6600_Y - connect \$63 $and$libresoc.v:142022$6601_Y - connect \$65 $and$libresoc.v:142023$6602_Y - connect \$67 $or$libresoc.v:142024$6603_Y - connect \$6 $or$libresoc.v:142025$6604_Y - connect \$69 $and$libresoc.v:142026$6605_Y - connect \$71 $and$libresoc.v:142027$6606_Y - connect \$73 $ternary$libresoc.v:142028$6607_Y - connect \$75 $ternary$libresoc.v:142029$6608_Y - connect \$78 $ternary$libresoc.v:142030$6609_Y - connect \$3 $reduce_and$libresoc.v:142031$6610_Y - connect \$81 $ternary$libresoc.v:142032$6611_Y - connect \$83 $ternary$libresoc.v:142033$6612_Y - connect \$85 $ternary$libresoc.v:142034$6613_Y - connect \$87 $ternary$libresoc.v:142035$6614_Y - connect \$89 $and$libresoc.v:142036$6615_Y - connect \$91 $and$libresoc.v:142037$6616_Y - connect \$93 $and$libresoc.v:142038$6617_Y - connect \$95 $not$libresoc.v:142039$6618_Y - connect \$97 $not$libresoc.v:142040$6619_Y + assign $1\prev_wr_go$next[1:0]$6817 2'00 + case + assign $1\prev_wr_go$next[1:0]$6817 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 + end + connect \$9 $and$libresoc.v:143616$6611_Y + connect \$99 $and$libresoc.v:143617$6612_Y + connect \$101 $not$libresoc.v:143618$6613_Y + connect \$103 $and$libresoc.v:143619$6614_Y + connect \$105 $and$libresoc.v:143620$6615_Y + connect \$107 $and$libresoc.v:143621$6616_Y + connect \$109 $and$libresoc.v:143622$6617_Y + connect \$111 $and$libresoc.v:143623$6618_Y + connect \$113 $and$libresoc.v:143624$6619_Y + connect \$115 $and$libresoc.v:143625$6620_Y + connect \$11 $not$libresoc.v:143626$6621_Y + connect \$13 $and$libresoc.v:143627$6622_Y + connect \$15 $not$libresoc.v:143628$6623_Y + connect \$17 $and$libresoc.v:143629$6624_Y + connect \$1 $and$libresoc.v:143630$6625_Y + connect \$19 $and$libresoc.v:143631$6626_Y + connect \$23 $not$libresoc.v:143632$6627_Y + connect \$25 $and$libresoc.v:143633$6628_Y + connect \$22 $reduce_or$libresoc.v:143634$6629_Y + connect \$21 $not$libresoc.v:143635$6630_Y + connect \$29 $and$libresoc.v:143636$6631_Y + connect \$31 $reduce_or$libresoc.v:143637$6632_Y + connect \$33 $reduce_or$libresoc.v:143638$6633_Y + connect \$35 $or$libresoc.v:143639$6634_Y + connect \$37 $not$libresoc.v:143640$6635_Y + connect \$39 $and$libresoc.v:143641$6636_Y + connect \$41 $and$libresoc.v:143642$6637_Y + connect \$43 $eq$libresoc.v:143643$6638_Y + connect \$45 $and$libresoc.v:143644$6639_Y + connect \$47 $eq$libresoc.v:143645$6640_Y + connect \$4 $not$libresoc.v:143646$6641_Y + connect \$49 $and$libresoc.v:143647$6642_Y + connect \$51 $and$libresoc.v:143648$6643_Y + connect \$53 $and$libresoc.v:143649$6644_Y + connect \$55 $or$libresoc.v:143650$6645_Y + connect \$57 $or$libresoc.v:143651$6646_Y + connect \$59 $or$libresoc.v:143652$6647_Y + connect \$61 $or$libresoc.v:143653$6648_Y + connect \$63 $and$libresoc.v:143654$6649_Y + connect \$65 $and$libresoc.v:143655$6650_Y + connect \$67 $or$libresoc.v:143656$6651_Y + connect \$6 $or$libresoc.v:143657$6652_Y + connect \$69 $and$libresoc.v:143658$6653_Y + connect \$71 $and$libresoc.v:143659$6654_Y + connect \$73 $ternary$libresoc.v:143660$6655_Y + connect \$75 $ternary$libresoc.v:143661$6656_Y + connect \$78 $ternary$libresoc.v:143662$6657_Y + connect \$3 $reduce_and$libresoc.v:143663$6658_Y + connect \$81 $ternary$libresoc.v:143664$6659_Y + connect \$83 $ternary$libresoc.v:143665$6660_Y + connect \$85 $ternary$libresoc.v:143666$6661_Y + connect \$87 $ternary$libresoc.v:143667$6662_Y + connect \$89 $and$libresoc.v:143668$6663_Y + connect \$91 $and$libresoc.v:143669$6664_Y + connect \$93 $and$libresoc.v:143670$6665_Y + connect \$95 $not$libresoc.v:143671$6666_Y + connect \$97 $not$libresoc.v:143672$6667_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -232570,248 +235067,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:142498.1-143889.10" +attribute \src "libresoc.v:144130.1-145521.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:143828.3-143846.6" - wire width 4 $0\cr_a$next[3:0]$6895 - attribute \src "libresoc.v:143588.3-143589.25" + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $0\cr_a$next[3:0]$6943 + attribute \src "libresoc.v:145220.3-145221.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $0\cr_a_ok$next[0:0]$6896 - attribute \src "libresoc.v:143590.3-143591.31" + attribute \src "libresoc.v:145460.3-145478.6" + wire $0\cr_a_ok$next[0:0]$6944 + attribute \src "libresoc.v:145222.3-145223.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:142499.7-142499.20" + attribute \src "libresoc.v:144131.7-144131.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6846 - attribute \src "libresoc.v:143628.3-143629.57" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6894 + attribute \src "libresoc.v:145260.3-145261.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$6847 - attribute \src "libresoc.v:143598.3-143599.55" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 + attribute \src "libresoc.v:145230.3-145231.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6848 - attribute \src "libresoc.v:143600.3-143601.69" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 + attribute \src "libresoc.v:145232.3-145233.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6849 - attribute \src "libresoc.v:143602.3-143603.65" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6897 + attribute \src "libresoc.v:145234.3-145235.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6850 - attribute \src "libresoc.v:143616.3-143617.63" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6898 + attribute \src "libresoc.v:145248.3-145249.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 32 $0\logical_op__insn$next[31:0]$6851 - attribute \src "libresoc.v:143630.3-143631.49" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $0\logical_op__insn$next[31:0]$6899 + attribute \src "libresoc.v:145262.3-145263.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6852 - attribute \src "libresoc.v:143596.3-143597.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6900 + attribute \src "libresoc.v:145228.3-145229.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__invert_in$next[0:0]$6853 - attribute \src "libresoc.v:143612.3-143613.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_in$next[0:0]$6901 + attribute \src "libresoc.v:145244.3-145245.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__invert_out$next[0:0]$6854 - attribute \src "libresoc.v:143618.3-143619.61" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_out$next[0:0]$6902 + attribute \src "libresoc.v:145250.3-145251.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__is_32bit$next[0:0]$6855 - attribute \src "libresoc.v:143624.3-143625.57" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_32bit$next[0:0]$6903 + attribute \src "libresoc.v:145256.3-145257.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__is_signed$next[0:0]$6856 - attribute \src "libresoc.v:143626.3-143627.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_signed$next[0:0]$6904 + attribute \src "libresoc.v:145258.3-145259.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__oe__oe$next[0:0]$6857 - attribute \src "libresoc.v:143608.3-143609.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__oe$next[0:0]$6905 + attribute \src "libresoc.v:145240.3-145241.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__oe__ok$next[0:0]$6858 - attribute \src "libresoc.v:143610.3-143611.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__ok$next[0:0]$6906 + attribute \src "libresoc.v:145242.3-145243.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__output_carry$next[0:0]$6859 - attribute \src "libresoc.v:143622.3-143623.65" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__output_carry$next[0:0]$6907 + attribute \src "libresoc.v:145254.3-145255.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__rc__ok$next[0:0]$6860 - attribute \src "libresoc.v:143606.3-143607.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__ok$next[0:0]$6908 + attribute \src "libresoc.v:145238.3-145239.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__rc__rc$next[0:0]$6861 - attribute \src "libresoc.v:143604.3-143605.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__rc$next[0:0]$6909 + attribute \src "libresoc.v:145236.3-145237.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__write_cr0$next[0:0]$6862 - attribute \src "libresoc.v:143620.3-143621.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__write_cr0$next[0:0]$6910 + attribute \src "libresoc.v:145252.3-145253.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__zero_a$next[0:0]$6863 - attribute \src "libresoc.v:143614.3-143615.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__zero_a$next[0:0]$6911 + attribute \src "libresoc.v:145246.3-145247.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:143754.3-143766.6" - wire width 2 $0\muxid$next[1:0]$6843 - attribute \src "libresoc.v:143632.3-143633.27" + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $0\muxid$next[1:0]$6891 + attribute \src "libresoc.v:145264.3-145265.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire width 64 $0\o$next[63:0]$6889 - attribute \src "libresoc.v:143592.3-143593.19" + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $0\o$next[63:0]$6937 + attribute \src "libresoc.v:145224.3-145225.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire $0\o_ok$next[0:0]$6890 - attribute \src "libresoc.v:143594.3-143595.25" + attribute \src "libresoc.v:145441.3-145459.6" + wire $0\o_ok$next[0:0]$6938 + attribute \src "libresoc.v:145226.3-145227.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:143736.3-143753.6" - wire $0\r_busy$next[0:0]$6839 - attribute \src "libresoc.v:143634.3-143635.29" + attribute \src "libresoc.v:145368.3-145385.6" + wire $0\r_busy$next[0:0]$6887 + attribute \src "libresoc.v:145266.3-145267.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $0\xer_so$next[0:0]$6901 - attribute \src "libresoc.v:143584.3-143585.29" + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so$next[0:0]$6949 + attribute \src "libresoc.v:145216.3-145217.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $0\xer_so_ok$next[0:0]$6902 - attribute \src "libresoc.v:143586.3-143587.35" + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so_ok$next[0:0]$6950 + attribute \src "libresoc.v:145218.3-145219.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire width 4 $1\cr_a$next[3:0]$6897 - attribute \src "libresoc.v:142508.13-142508.24" + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $1\cr_a$next[3:0]$6945 + attribute \src "libresoc.v:144140.13-144140.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $1\cr_a_ok$next[0:0]$6898 - attribute \src "libresoc.v:142517.7-142517.21" + attribute \src "libresoc.v:145460.3-145478.6" + wire $1\cr_a_ok$next[0:0]$6946 + attribute \src "libresoc.v:144149.7-144149.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6864 - attribute \src "libresoc.v:142802.13-142802.40" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6912 + attribute \src "libresoc.v:144434.13-144434.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$6865 - attribute \src "libresoc.v:142826.14-142826.44" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 + attribute \src "libresoc.v:144458.14-144458.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6866 - attribute \src "libresoc.v:142865.14-142865.63" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 + attribute \src "libresoc.v:144497.14-144497.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6867 - attribute \src "libresoc.v:142874.7-142874.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6915 + attribute \src "libresoc.v:144506.7-144506.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6868 - attribute \src "libresoc.v:142887.13-142887.43" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6916 + attribute \src "libresoc.v:144519.13-144519.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 32 $1\logical_op__insn$next[31:0]$6869 - attribute \src "libresoc.v:142904.14-142904.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $1\logical_op__insn$next[31:0]$6917 + attribute \src "libresoc.v:144536.14-144536.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6870 - attribute \src "libresoc.v:142988.13-142988.42" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6918 + attribute \src "libresoc.v:144620.13-144620.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__invert_in$next[0:0]$6871 - attribute \src "libresoc.v:143147.7-143147.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_in$next[0:0]$6919 + attribute \src "libresoc.v:144779.7-144779.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__invert_out$next[0:0]$6872 - attribute \src "libresoc.v:143156.7-143156.36" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_out$next[0:0]$6920 + attribute \src "libresoc.v:144788.7-144788.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__is_32bit$next[0:0]$6873 - attribute \src "libresoc.v:143165.7-143165.34" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_32bit$next[0:0]$6921 + attribute \src "libresoc.v:144797.7-144797.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__is_signed$next[0:0]$6874 - attribute \src "libresoc.v:143174.7-143174.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_signed$next[0:0]$6922 + attribute \src "libresoc.v:144806.7-144806.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__oe__oe$next[0:0]$6875 - attribute \src "libresoc.v:143183.7-143183.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__oe$next[0:0]$6923 + attribute \src "libresoc.v:144815.7-144815.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__oe__ok$next[0:0]$6876 - attribute \src "libresoc.v:143192.7-143192.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__ok$next[0:0]$6924 + attribute \src "libresoc.v:144824.7-144824.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__output_carry$next[0:0]$6877 - attribute \src "libresoc.v:143201.7-143201.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__output_carry$next[0:0]$6925 + attribute \src "libresoc.v:144833.7-144833.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__rc__ok$next[0:0]$6878 - attribute \src "libresoc.v:143210.7-143210.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__ok$next[0:0]$6926 + attribute \src "libresoc.v:144842.7-144842.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__rc__rc$next[0:0]$6879 - attribute \src "libresoc.v:143219.7-143219.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__rc$next[0:0]$6927 + attribute \src "libresoc.v:144851.7-144851.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__write_cr0$next[0:0]$6880 - attribute \src "libresoc.v:143228.7-143228.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__write_cr0$next[0:0]$6928 + attribute \src "libresoc.v:144860.7-144860.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__zero_a$next[0:0]$6881 - attribute \src "libresoc.v:143237.7-143237.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__zero_a$next[0:0]$6929 + attribute \src "libresoc.v:144869.7-144869.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:143754.3-143766.6" - wire width 2 $1\muxid$next[1:0]$6844 - attribute \src "libresoc.v:143522.13-143522.25" + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145154.13-145154.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire width 64 $1\o$next[63:0]$6891 - attribute \src "libresoc.v:143537.14-143537.38" + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $1\o$next[63:0]$6939 + attribute \src "libresoc.v:145169.14-145169.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire $1\o_ok$next[0:0]$6892 - attribute \src "libresoc.v:143544.7-143544.18" + attribute \src "libresoc.v:145441.3-145459.6" + wire $1\o_ok$next[0:0]$6940 + attribute \src "libresoc.v:145176.7-145176.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:143736.3-143753.6" - wire $1\r_busy$next[0:0]$6840 - attribute \src "libresoc.v:143558.7-143558.20" + attribute \src "libresoc.v:145368.3-145385.6" + wire $1\r_busy$next[0:0]$6888 + attribute \src "libresoc.v:145190.7-145190.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $1\xer_so$next[0:0]$6903 - attribute \src "libresoc.v:143567.7-143567.20" + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so$next[0:0]$6951 + attribute \src "libresoc.v:145199.7-145199.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $1\xer_so_ok$next[0:0]$6904 - attribute \src "libresoc.v:143576.7-143576.23" + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so_ok$next[0:0]$6952 + attribute \src "libresoc.v:145208.7-145208.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $2\cr_a_ok$next[0:0]$6899 - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6882 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6883 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__oe__oe$next[0:0]$6884 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__oe__ok$next[0:0]$6885 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__rc__ok$next[0:0]$6886 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__rc__rc$next[0:0]$6887 - attribute \src "libresoc.v:143809.3-143827.6" - wire $2\o_ok$next[0:0]$6893 - attribute \src "libresoc.v:143736.3-143753.6" - wire $2\r_busy$next[0:0]$6841 - attribute \src "libresoc.v:143847.3-143865.6" - wire $2\xer_so_ok$next[0:0]$6905 - attribute \src "libresoc.v:143583.18-143583.118" - wire $and$libresoc.v:143583$6811_Y + attribute \src "libresoc.v:145460.3-145478.6" + wire $2\cr_a_ok$next[0:0]$6947 + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6930 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6931 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__oe__oe$next[0:0]$6932 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__oe__ok$next[0:0]$6933 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__rc__ok$next[0:0]$6934 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__rc__rc$next[0:0]$6935 + attribute \src "libresoc.v:145441.3-145459.6" + wire $2\o_ok$next[0:0]$6941 + attribute \src "libresoc.v:145368.3-145385.6" + wire $2\r_busy$next[0:0]$6889 + attribute \src "libresoc.v:145479.3-145497.6" + wire $2\xer_so_ok$next[0:0]$6953 + attribute \src "libresoc.v:145215.18-145215.118" + wire $and$libresoc.v:145215$6859_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -232829,7 +235326,7 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:142499.7-142499.15" + attribute \src "libresoc.v:144131.7-144131.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -233868,7 +236365,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:143583$6811 + cell $and $and$libresoc.v:145215$6859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233876,10 +236373,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:143583$6811_Y + connect \Y $and$libresoc.v:145215$6859_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143636.14-143681.4" + attribute \src "libresoc.v:145268.14-145313.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -233927,7 +236424,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143682.13-143727.4" + attribute \src "libresoc.v:145314.13-145359.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -233975,424 +236472,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143728.10-143731.4" + attribute \src "libresoc.v:145360.10-145363.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:143732.10-143735.4" + attribute \src "libresoc.v:145364.10-145367.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:142499.7-142499.20" - process $proc$libresoc.v:142499$6906 + attribute \src "libresoc.v:144131.7-144131.20" + process $proc$libresoc.v:144131$6954 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142508.13-142508.24" - process $proc$libresoc.v:142508$6907 + attribute \src "libresoc.v:144140.13-144140.24" + process $proc$libresoc.v:144140$6955 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:142517.7-142517.21" - process $proc$libresoc.v:142517$6908 + attribute \src "libresoc.v:144149.7-144149.21" + process $proc$libresoc.v:144149$6956 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:142802.13-142802.40" - process $proc$libresoc.v:142802$6909 + attribute \src "libresoc.v:144434.13-144434.40" + process $proc$libresoc.v:144434$6957 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:142826.14-142826.44" - process $proc$libresoc.v:142826$6910 + attribute \src "libresoc.v:144458.14-144458.44" + process $proc$libresoc.v:144458$6958 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:142865.14-142865.63" - process $proc$libresoc.v:142865$6911 + attribute \src "libresoc.v:144497.14-144497.63" + process $proc$libresoc.v:144497$6959 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142874.7-142874.38" - process $proc$libresoc.v:142874$6912 + attribute \src "libresoc.v:144506.7-144506.38" + process $proc$libresoc.v:144506$6960 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142887.13-142887.43" - process $proc$libresoc.v:142887$6913 + attribute \src "libresoc.v:144519.13-144519.43" + process $proc$libresoc.v:144519$6961 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:142904.14-142904.38" - process $proc$libresoc.v:142904$6914 + attribute \src "libresoc.v:144536.14-144536.38" + process $proc$libresoc.v:144536$6962 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:142988.13-142988.42" - process $proc$libresoc.v:142988$6915 + attribute \src "libresoc.v:144620.13-144620.42" + process $proc$libresoc.v:144620$6963 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143147.7-143147.35" - process $proc$libresoc.v:143147$6916 + attribute \src "libresoc.v:144779.7-144779.35" + process $proc$libresoc.v:144779$6964 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143156.7-143156.36" - process $proc$libresoc.v:143156$6917 + attribute \src "libresoc.v:144788.7-144788.36" + process $proc$libresoc.v:144788$6965 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143165.7-143165.34" - process $proc$libresoc.v:143165$6918 + attribute \src "libresoc.v:144797.7-144797.34" + process $proc$libresoc.v:144797$6966 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143174.7-143174.35" - process $proc$libresoc.v:143174$6919 + attribute \src "libresoc.v:144806.7-144806.35" + process $proc$libresoc.v:144806$6967 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143183.7-143183.32" - process $proc$libresoc.v:143183$6920 + attribute \src "libresoc.v:144815.7-144815.32" + process $proc$libresoc.v:144815$6968 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143192.7-143192.32" - process $proc$libresoc.v:143192$6921 + attribute \src "libresoc.v:144824.7-144824.32" + process $proc$libresoc.v:144824$6969 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143201.7-143201.38" - process $proc$libresoc.v:143201$6922 + attribute \src "libresoc.v:144833.7-144833.38" + process $proc$libresoc.v:144833$6970 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143210.7-143210.32" - process $proc$libresoc.v:143210$6923 + attribute \src "libresoc.v:144842.7-144842.32" + process $proc$libresoc.v:144842$6971 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143219.7-143219.32" - process $proc$libresoc.v:143219$6924 + attribute \src "libresoc.v:144851.7-144851.32" + process $proc$libresoc.v:144851$6972 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143228.7-143228.35" - process $proc$libresoc.v:143228$6925 + attribute \src "libresoc.v:144860.7-144860.35" + process $proc$libresoc.v:144860$6973 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143237.7-143237.32" - process $proc$libresoc.v:143237$6926 + attribute \src "libresoc.v:144869.7-144869.32" + process $proc$libresoc.v:144869$6974 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143522.13-143522.25" - process $proc$libresoc.v:143522$6927 + attribute \src "libresoc.v:145154.13-145154.25" + process $proc$libresoc.v:145154$6975 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:143537.14-143537.38" - process $proc$libresoc.v:143537$6928 + attribute \src "libresoc.v:145169.14-145169.38" + process $proc$libresoc.v:145169$6976 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:143544.7-143544.18" - process $proc$libresoc.v:143544$6929 + attribute \src "libresoc.v:145176.7-145176.18" + process $proc$libresoc.v:145176$6977 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:143558.7-143558.20" - process $proc$libresoc.v:143558$6930 + attribute \src "libresoc.v:145190.7-145190.20" + process $proc$libresoc.v:145190$6978 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:143567.7-143567.20" - process $proc$libresoc.v:143567$6931 + attribute \src "libresoc.v:145199.7-145199.20" + process $proc$libresoc.v:145199$6979 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:143576.7-143576.23" - process $proc$libresoc.v:143576$6932 + attribute \src "libresoc.v:145208.7-145208.23" + process $proc$libresoc.v:145208$6980 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:143584.3-143585.29" - process $proc$libresoc.v:143584$6812 + attribute \src "libresoc.v:145216.3-145217.29" + process $proc$libresoc.v:145216$6860 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:143586.3-143587.35" - process $proc$libresoc.v:143586$6813 + attribute \src "libresoc.v:145218.3-145219.35" + process $proc$libresoc.v:145218$6861 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:143588.3-143589.25" - process $proc$libresoc.v:143588$6814 + attribute \src "libresoc.v:145220.3-145221.25" + process $proc$libresoc.v:145220$6862 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:143590.3-143591.31" - process $proc$libresoc.v:143590$6815 + attribute \src "libresoc.v:145222.3-145223.31" + process $proc$libresoc.v:145222$6863 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:143592.3-143593.19" - process $proc$libresoc.v:143592$6816 + attribute \src "libresoc.v:145224.3-145225.19" + process $proc$libresoc.v:145224$6864 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:143594.3-143595.25" - process $proc$libresoc.v:143594$6817 + attribute \src "libresoc.v:145226.3-145227.25" + process $proc$libresoc.v:145226$6865 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:143596.3-143597.59" - process $proc$libresoc.v:143596$6818 + attribute \src "libresoc.v:145228.3-145229.59" + process $proc$libresoc.v:145228$6866 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143598.3-143599.55" - process $proc$libresoc.v:143598$6819 + attribute \src "libresoc.v:145230.3-145231.55" + process $proc$libresoc.v:145230$6867 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143600.3-143601.69" - process $proc$libresoc.v:143600$6820 + attribute \src "libresoc.v:145232.3-145233.69" + process $proc$libresoc.v:145232$6868 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143602.3-143603.65" - process $proc$libresoc.v:143602$6821 + attribute \src "libresoc.v:145234.3-145235.65" + process $proc$libresoc.v:145234$6869 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143604.3-143605.53" - process $proc$libresoc.v:143604$6822 + attribute \src "libresoc.v:145236.3-145237.53" + process $proc$libresoc.v:145236$6870 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143606.3-143607.53" - process $proc$libresoc.v:143606$6823 + attribute \src "libresoc.v:145238.3-145239.53" + process $proc$libresoc.v:145238$6871 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143608.3-143609.53" - process $proc$libresoc.v:143608$6824 + attribute \src "libresoc.v:145240.3-145241.53" + process $proc$libresoc.v:145240$6872 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143610.3-143611.53" - process $proc$libresoc.v:143610$6825 + attribute \src "libresoc.v:145242.3-145243.53" + process $proc$libresoc.v:145242$6873 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143612.3-143613.59" - process $proc$libresoc.v:143612$6826 + attribute \src "libresoc.v:145244.3-145245.59" + process $proc$libresoc.v:145244$6874 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143614.3-143615.53" - process $proc$libresoc.v:143614$6827 + attribute \src "libresoc.v:145246.3-145247.53" + process $proc$libresoc.v:145246$6875 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143616.3-143617.63" - process $proc$libresoc.v:143616$6828 + attribute \src "libresoc.v:145248.3-145249.63" + process $proc$libresoc.v:145248$6876 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143618.3-143619.61" - process $proc$libresoc.v:143618$6829 + attribute \src "libresoc.v:145250.3-145251.61" + process $proc$libresoc.v:145250$6877 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143620.3-143621.59" - process $proc$libresoc.v:143620$6830 + attribute \src "libresoc.v:145252.3-145253.59" + process $proc$libresoc.v:145252$6878 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143622.3-143623.65" - process $proc$libresoc.v:143622$6831 + attribute \src "libresoc.v:145254.3-145255.65" + process $proc$libresoc.v:145254$6879 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143624.3-143625.57" - process $proc$libresoc.v:143624$6832 + attribute \src "libresoc.v:145256.3-145257.57" + process $proc$libresoc.v:145256$6880 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143626.3-143627.59" - process $proc$libresoc.v:143626$6833 + attribute \src "libresoc.v:145258.3-145259.59" + process $proc$libresoc.v:145258$6881 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143628.3-143629.57" - process $proc$libresoc.v:143628$6834 + attribute \src "libresoc.v:145260.3-145261.57" + process $proc$libresoc.v:145260$6882 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:143630.3-143631.49" - process $proc$libresoc.v:143630$6835 + attribute \src "libresoc.v:145262.3-145263.49" + process $proc$libresoc.v:145262$6883 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:143632.3-143633.27" - process $proc$libresoc.v:143632$6836 + attribute \src "libresoc.v:145264.3-145265.27" + process $proc$libresoc.v:145264$6884 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:143634.3-143635.29" - process $proc$libresoc.v:143634$6837 + attribute \src "libresoc.v:145266.3-145267.29" + process $proc$libresoc.v:145266$6885 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:143736.3-143753.6" - process $proc$libresoc.v:143736$6838 + attribute \src "libresoc.v:145368.3-145385.6" + process $proc$libresoc.v:145368$6886 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6839 $2\r_busy$next[0:0]$6841 - attribute \src "libresoc.v:143737.5-143737.29" + assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 + attribute \src "libresoc.v:145369.5-145369.29" switch \initial - attribute \src "libresoc.v:143737.9-143737.17" + attribute \src "libresoc.v:145369.9-145369.17" case 1'1 case end @@ -234401,34 +236898,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6840 1'1 + assign $1\r_busy$next[0:0]$6888 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6840 1'0 + assign $1\r_busy$next[0:0]$6888 1'0 case - assign $1\r_busy$next[0:0]$6840 \r_busy + assign $1\r_busy$next[0:0]$6888 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6841 1'0 + assign $2\r_busy$next[0:0]$6889 1'0 case - assign $2\r_busy$next[0:0]$6841 $1\r_busy$next[0:0]$6840 + assign $2\r_busy$next[0:0]$6889 $1\r_busy$next[0:0]$6888 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6839 + update \r_busy$next $0\r_busy$next[0:0]$6887 end - attribute \src "libresoc.v:143754.3-143766.6" - process $proc$libresoc.v:143754$6842 + attribute \src "libresoc.v:145386.3-145398.6" + process $proc$libresoc.v:145386$6890 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6843 $1\muxid$next[1:0]$6844 - attribute \src "libresoc.v:143755.5-143755.29" + assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145387.5-145387.29" switch \initial - attribute \src "libresoc.v:143755.9-143755.17" + attribute \src "libresoc.v:145387.9-145387.17" case 1'1 case end @@ -234437,19 +236934,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6844 \muxid$66 + assign $1\muxid$next[1:0]$6892 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6844 \muxid$66 + assign $1\muxid$next[1:0]$6892 \muxid$66 case - assign $1\muxid$next[1:0]$6844 \muxid + assign $1\muxid$next[1:0]$6892 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6843 + update \muxid$next $0\muxid$next[1:0]$6891 end - attribute \src "libresoc.v:143767.3-143808.6" - process $proc$libresoc.v:143767$6845 + attribute \src "libresoc.v:145399.3-145440.6" + process $proc$libresoc.v:145399$6893 assign { } { } assign { } { } assign { } { } @@ -234486,33 +236983,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6846 $1\logical_op__data_len$next[3:0]$6864 - assign $0\logical_op__fn_unit$next[13:0]$6847 $1\logical_op__fn_unit$next[13:0]$6865 + assign $0\logical_op__data_len$next[3:0]$6894 $1\logical_op__data_len$next[3:0]$6912 + assign $0\logical_op__fn_unit$next[13:0]$6895 $1\logical_op__fn_unit$next[13:0]$6913 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6850 $1\logical_op__input_carry$next[1:0]$6868 - assign $0\logical_op__insn$next[31:0]$6851 $1\logical_op__insn$next[31:0]$6869 - assign $0\logical_op__insn_type$next[6:0]$6852 $1\logical_op__insn_type$next[6:0]$6870 - assign $0\logical_op__invert_in$next[0:0]$6853 $1\logical_op__invert_in$next[0:0]$6871 - assign $0\logical_op__invert_out$next[0:0]$6854 $1\logical_op__invert_out$next[0:0]$6872 - assign $0\logical_op__is_32bit$next[0:0]$6855 $1\logical_op__is_32bit$next[0:0]$6873 - assign $0\logical_op__is_signed$next[0:0]$6856 $1\logical_op__is_signed$next[0:0]$6874 + assign $0\logical_op__input_carry$next[1:0]$6898 $1\logical_op__input_carry$next[1:0]$6916 + assign $0\logical_op__insn$next[31:0]$6899 $1\logical_op__insn$next[31:0]$6917 + assign $0\logical_op__insn_type$next[6:0]$6900 $1\logical_op__insn_type$next[6:0]$6918 + assign $0\logical_op__invert_in$next[0:0]$6901 $1\logical_op__invert_in$next[0:0]$6919 + assign $0\logical_op__invert_out$next[0:0]$6902 $1\logical_op__invert_out$next[0:0]$6920 + assign $0\logical_op__is_32bit$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6921 + assign $0\logical_op__is_signed$next[0:0]$6904 $1\logical_op__is_signed$next[0:0]$6922 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6859 $1\logical_op__output_carry$next[0:0]$6877 + assign $0\logical_op__output_carry$next[0:0]$6907 $1\logical_op__output_carry$next[0:0]$6925 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6862 $1\logical_op__write_cr0$next[0:0]$6880 - assign $0\logical_op__zero_a$next[0:0]$6863 $1\logical_op__zero_a$next[0:0]$6881 - assign $0\logical_op__imm_data__data$next[63:0]$6848 $2\logical_op__imm_data__data$next[63:0]$6882 - assign $0\logical_op__imm_data__ok$next[0:0]$6849 $2\logical_op__imm_data__ok$next[0:0]$6883 - assign $0\logical_op__oe__oe$next[0:0]$6857 $2\logical_op__oe__oe$next[0:0]$6884 - assign $0\logical_op__oe__ok$next[0:0]$6858 $2\logical_op__oe__ok$next[0:0]$6885 - assign $0\logical_op__rc__ok$next[0:0]$6860 $2\logical_op__rc__ok$next[0:0]$6886 - assign $0\logical_op__rc__rc$next[0:0]$6861 $2\logical_op__rc__rc$next[0:0]$6887 - attribute \src "libresoc.v:143768.5-143768.29" + assign $0\logical_op__write_cr0$next[0:0]$6910 $1\logical_op__write_cr0$next[0:0]$6928 + assign $0\logical_op__zero_a$next[0:0]$6911 $1\logical_op__zero_a$next[0:0]$6929 + assign $0\logical_op__imm_data__data$next[63:0]$6896 $2\logical_op__imm_data__data$next[63:0]$6930 + assign $0\logical_op__imm_data__ok$next[0:0]$6897 $2\logical_op__imm_data__ok$next[0:0]$6931 + assign $0\logical_op__oe__oe$next[0:0]$6905 $2\logical_op__oe__oe$next[0:0]$6932 + assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 + assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 + assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 + attribute \src "libresoc.v:145400.5-145400.29" switch \initial - attribute \src "libresoc.v:143768.9-143768.17" + attribute \src "libresoc.v:145400.9-145400.17" case 1'1 case end @@ -234538,7 +237035,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -234559,26 +237056,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6864 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$6865 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6866 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6867 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6868 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6869 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6870 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6871 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6872 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6873 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6874 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6875 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6876 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6877 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6878 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6879 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6880 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6881 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6912 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6913 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6914 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6915 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6916 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6917 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6918 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6919 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6920 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6921 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6922 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6923 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6924 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6925 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6926 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6927 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6928 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6929 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -234590,52 +237087,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6882 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6883 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6887 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6886 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6884 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6885 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6935 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6934 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6932 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6933 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6882 $1\logical_op__imm_data__data$next[63:0]$6866 - assign $2\logical_op__imm_data__ok$next[0:0]$6883 $1\logical_op__imm_data__ok$next[0:0]$6867 - assign $2\logical_op__oe__oe$next[0:0]$6884 $1\logical_op__oe__oe$next[0:0]$6875 - assign $2\logical_op__oe__ok$next[0:0]$6885 $1\logical_op__oe__ok$next[0:0]$6876 - assign $2\logical_op__rc__ok$next[0:0]$6886 $1\logical_op__rc__ok$next[0:0]$6878 - assign $2\logical_op__rc__rc$next[0:0]$6887 $1\logical_op__rc__rc$next[0:0]$6879 + assign $2\logical_op__imm_data__data$next[63:0]$6930 $1\logical_op__imm_data__data$next[63:0]$6914 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 $1\logical_op__imm_data__ok$next[0:0]$6915 + assign $2\logical_op__oe__oe$next[0:0]$6932 $1\logical_op__oe__oe$next[0:0]$6923 + assign $2\logical_op__oe__ok$next[0:0]$6933 $1\logical_op__oe__ok$next[0:0]$6924 + assign $2\logical_op__rc__ok$next[0:0]$6934 $1\logical_op__rc__ok$next[0:0]$6926 + assign $2\logical_op__rc__rc$next[0:0]$6935 $1\logical_op__rc__rc$next[0:0]$6927 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6846 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6847 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6848 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6849 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6850 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6851 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6852 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6853 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6854 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6855 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6856 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6857 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6858 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6859 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6860 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6861 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6862 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6863 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6894 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6895 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6896 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6897 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6898 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6899 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6900 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6901 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6902 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6903 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6904 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6905 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6906 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6907 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6908 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6909 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 end - attribute \src "libresoc.v:143809.3-143827.6" - process $proc$libresoc.v:143809$6888 + attribute \src "libresoc.v:145441.3-145459.6" + process $proc$libresoc.v:145441$6936 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6889 $1\o$next[63:0]$6891 + assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 assign { } { } - assign $0\o_ok$next[0:0]$6890 $2\o_ok$next[0:0]$6893 - attribute \src "libresoc.v:143810.5-143810.29" + assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 + attribute \src "libresoc.v:145442.5-145442.29" switch \initial - attribute \src "libresoc.v:143810.9-143810.17" + attribute \src "libresoc.v:145442.9-145442.17" case 1'1 case end @@ -234645,41 +237142,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6891 \o - assign $1\o_ok$next[0:0]$6892 \o_ok + assign $1\o$next[63:0]$6939 \o + assign $1\o_ok$next[0:0]$6940 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6893 1'0 + assign $2\o_ok$next[0:0]$6941 1'0 case - assign $2\o_ok$next[0:0]$6893 $1\o_ok$next[0:0]$6892 + assign $2\o_ok$next[0:0]$6941 $1\o_ok$next[0:0]$6940 end sync always - update \o$next $0\o$next[63:0]$6889 - update \o_ok$next $0\o_ok$next[0:0]$6890 + update \o$next $0\o$next[63:0]$6937 + update \o_ok$next $0\o_ok$next[0:0]$6938 end - attribute \src "libresoc.v:143828.3-143846.6" - process $proc$libresoc.v:143828$6894 + attribute \src "libresoc.v:145460.3-145478.6" + process $proc$libresoc.v:145460$6942 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6895 $1\cr_a$next[3:0]$6897 + assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 assign { } { } - assign $0\cr_a_ok$next[0:0]$6896 $2\cr_a_ok$next[0:0]$6899 - attribute \src "libresoc.v:143829.5-143829.29" + assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 + attribute \src "libresoc.v:145461.5-145461.29" switch \initial - attribute \src "libresoc.v:143829.9-143829.17" + attribute \src "libresoc.v:145461.9-145461.17" case 1'1 case end @@ -234689,41 +237186,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6897 \cr_a - assign $1\cr_a_ok$next[0:0]$6898 \cr_a_ok + assign $1\cr_a$next[3:0]$6945 \cr_a + assign $1\cr_a_ok$next[0:0]$6946 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6899 1'0 + assign $2\cr_a_ok$next[0:0]$6947 1'0 case - assign $2\cr_a_ok$next[0:0]$6899 $1\cr_a_ok$next[0:0]$6898 + assign $2\cr_a_ok$next[0:0]$6947 $1\cr_a_ok$next[0:0]$6946 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6895 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6896 + update \cr_a$next $0\cr_a$next[3:0]$6943 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 end - attribute \src "libresoc.v:143847.3-143865.6" - process $proc$libresoc.v:143847$6900 + attribute \src "libresoc.v:145479.3-145497.6" + process $proc$libresoc.v:145479$6948 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6901 $1\xer_so$next[0:0]$6903 + assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 assign { } { } - assign $0\xer_so_ok$next[0:0]$6902 $2\xer_so_ok$next[0:0]$6905 - attribute \src "libresoc.v:143848.5-143848.29" + assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 + attribute \src "libresoc.v:145480.5-145480.29" switch \initial - attribute \src "libresoc.v:143848.9-143848.17" + attribute \src "libresoc.v:145480.9-145480.17" case 1'1 case end @@ -234733,30 +237230,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6903 \xer_so - assign $1\xer_so_ok$next[0:0]$6904 \xer_so_ok + assign $1\xer_so$next[0:0]$6951 \xer_so + assign $1\xer_so_ok$next[0:0]$6952 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6905 1'0 + assign $2\xer_so_ok$next[0:0]$6953 1'0 case - assign $2\xer_so_ok$next[0:0]$6905 $1\xer_so_ok$next[0:0]$6904 + assign $2\xer_so_ok$next[0:0]$6953 $1\xer_so_ok$next[0:0]$6952 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6901 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6902 + update \xer_so$next $0\xer_so$next[0:0]$6949 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 end - connect \$64 $and$libresoc.v:143583$6811_Y + connect \$64 $and$libresoc.v:145215$6859_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -234781,230 +237278,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:143893.1-144926.10" +attribute \src "libresoc.v:145525.1-146558.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:144893.3-144911.6" - wire width 4 $0\cr_a$22$next[3:0]$7038 - attribute \src "libresoc.v:144697.3-144698.33" - wire width 4 $0\cr_a$22[3:0]$6935 - attribute \src "libresoc.v:143905.13-143905.29" - wire width 4 $0\cr_a$22[3:0]$7045 - attribute \src "libresoc.v:144893.3-144911.6" - wire $0\cr_a_ok$23$next[0:0]$7039 - attribute \src "libresoc.v:144699.3-144700.39" - wire $0\cr_a_ok$23[0:0]$6937 - attribute \src "libresoc.v:143914.7-143914.26" - wire $0\cr_a_ok$23[0:0]$7047 - attribute \src "libresoc.v:143894.7-143894.20" + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $0\cr_a$22$next[3:0]$7086 + attribute \src "libresoc.v:146329.3-146330.33" + wire width 4 $0\cr_a$22[3:0]$6983 + attribute \src "libresoc.v:145537.13-145537.29" + wire width 4 $0\cr_a$22[3:0]$7093 + attribute \src "libresoc.v:146525.3-146543.6" + wire $0\cr_a_ok$23$next[0:0]$7087 + attribute \src "libresoc.v:146331.3-146332.39" + wire $0\cr_a_ok$23[0:0]$6985 + attribute \src "libresoc.v:145546.7-145546.26" + wire $0\cr_a_ok$23[0:0]$7095 + attribute \src "libresoc.v:145526.7-145526.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144832.3-144873.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6989 - attribute \src "libresoc.v:144737.3-144738.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6975 - attribute \src "libresoc.v:143925.13-143925.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7049 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6990 - attribute \src "libresoc.v:144707.3-144708.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$6945 - attribute \src "libresoc.v:143964.14-143964.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$7051 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6991 - attribute \src "libresoc.v:144709.3-144710.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6947 - attribute \src "libresoc.v:143988.14-143988.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7053 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6992 - attribute \src "libresoc.v:144711.3-144712.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6949 - attribute \src "libresoc.v:143997.7-143997.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7055 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6993 - attribute \src "libresoc.v:144725.3-144726.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6963 - attribute \src "libresoc.v:144014.13-144014.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7057 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6994 - attribute \src "libresoc.v:144739.3-144740.57" - wire width 32 $0\logical_op__insn$19[31:0]$6977 - attribute \src "libresoc.v:144027.14-144027.43" - wire width 32 $0\logical_op__insn$19[31:0]$7059 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6995 - attribute \src "libresoc.v:144705.3-144706.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6943 - attribute \src "libresoc.v:144186.13-144186.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7061 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__invert_in$10$next[0:0]$6996 - attribute \src "libresoc.v:144721.3-144722.67" - wire $0\logical_op__invert_in$10[0:0]$6959 - attribute \src "libresoc.v:144270.7-144270.40" - wire $0\logical_op__invert_in$10[0:0]$7063 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__invert_out$13$next[0:0]$6997 - attribute \src "libresoc.v:144727.3-144728.69" - wire $0\logical_op__invert_out$13[0:0]$6965 - attribute \src "libresoc.v:144279.7-144279.41" - wire $0\logical_op__invert_out$13[0:0]$7065 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6998 - attribute \src "libresoc.v:144733.3-144734.65" - wire $0\logical_op__is_32bit$16[0:0]$6971 - attribute \src "libresoc.v:144288.7-144288.39" - wire $0\logical_op__is_32bit$16[0:0]$7067 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__is_signed$17$next[0:0]$6999 - attribute \src "libresoc.v:144735.3-144736.67" - wire $0\logical_op__is_signed$17[0:0]$6973 - attribute \src "libresoc.v:144297.7-144297.40" - wire $0\logical_op__is_signed$17[0:0]$7069 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__oe__oe$8$next[0:0]$7000 - attribute \src "libresoc.v:144717.3-144718.59" - wire $0\logical_op__oe__oe$8[0:0]$6955 - attribute \src "libresoc.v:144308.7-144308.36" - wire $0\logical_op__oe__oe$8[0:0]$7071 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__oe__ok$9$next[0:0]$7001 - attribute \src "libresoc.v:144719.3-144720.59" - wire $0\logical_op__oe__ok$9[0:0]$6957 - attribute \src "libresoc.v:144317.7-144317.36" - wire $0\logical_op__oe__ok$9[0:0]$7073 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__output_carry$15$next[0:0]$7002 - attribute \src "libresoc.v:144731.3-144732.73" - wire $0\logical_op__output_carry$15[0:0]$6969 - attribute \src "libresoc.v:144324.7-144324.43" - wire $0\logical_op__output_carry$15[0:0]$7075 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__rc__ok$7$next[0:0]$7003 - attribute \src "libresoc.v:144715.3-144716.59" - wire $0\logical_op__rc__ok$7[0:0]$6953 - attribute \src "libresoc.v:144335.7-144335.36" - wire $0\logical_op__rc__ok$7[0:0]$7077 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__rc__rc$6$next[0:0]$7004 - attribute \src "libresoc.v:144713.3-144714.59" - wire $0\logical_op__rc__rc$6[0:0]$6951 - attribute \src "libresoc.v:144344.7-144344.36" - wire $0\logical_op__rc__rc$6[0:0]$7079 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__write_cr0$14$next[0:0]$7005 - attribute \src "libresoc.v:144729.3-144730.67" - wire $0\logical_op__write_cr0$14[0:0]$6967 - attribute \src "libresoc.v:144351.7-144351.40" - wire $0\logical_op__write_cr0$14[0:0]$7081 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__zero_a$11$next[0:0]$7006 - attribute \src "libresoc.v:144723.3-144724.61" - wire $0\logical_op__zero_a$11[0:0]$6961 - attribute \src "libresoc.v:144360.7-144360.37" - wire $0\logical_op__zero_a$11[0:0]$7083 - attribute \src "libresoc.v:144819.3-144831.6" - wire width 2 $0\muxid$1$next[1:0]$6986 - attribute \src "libresoc.v:144741.3-144742.33" - wire width 2 $0\muxid$1[1:0]$6979 - attribute \src "libresoc.v:144369.13-144369.29" - wire width 2 $0\muxid$1[1:0]$7085 - attribute \src "libresoc.v:144874.3-144892.6" - wire width 64 $0\o$20$next[63:0]$7032 - attribute \src "libresoc.v:144701.3-144702.27" - wire width 64 $0\o$20[63:0]$6939 - attribute \src "libresoc.v:144384.14-144384.43" - wire width 64 $0\o$20[63:0]$7087 - attribute \src "libresoc.v:144874.3-144892.6" - wire $0\o_ok$21$next[0:0]$7033 - attribute \src "libresoc.v:144703.3-144704.33" - wire $0\o_ok$21[0:0]$6941 - attribute \src "libresoc.v:144393.7-144393.23" - wire $0\o_ok$21[0:0]$7089 - attribute \src "libresoc.v:144801.3-144818.6" - wire $0\r_busy$next[0:0]$6982 - attribute \src "libresoc.v:144743.3-144744.29" + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 + attribute \src "libresoc.v:146369.3-146370.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7023 + attribute \src "libresoc.v:145557.13-145557.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7097 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 + attribute \src "libresoc.v:146339.3-146340.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 + attribute \src "libresoc.v:145596.14-145596.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 + attribute \src "libresoc.v:146341.3-146342.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 + attribute \src "libresoc.v:145620.14-145620.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 + attribute \src "libresoc.v:146343.3-146344.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6997 + attribute \src "libresoc.v:145629.7-145629.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7103 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 + attribute \src "libresoc.v:146357.3-146358.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$7011 + attribute \src "libresoc.v:145646.13-145646.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7105 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7042 + attribute \src "libresoc.v:146371.3-146372.57" + wire width 32 $0\logical_op__insn$19[31:0]$7025 + attribute \src "libresoc.v:145659.14-145659.43" + wire width 32 $0\logical_op__insn$19[31:0]$7107 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 + attribute \src "libresoc.v:146337.3-146338.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6991 + attribute \src "libresoc.v:145818.13-145818.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7109 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_in$10$next[0:0]$7044 + attribute \src "libresoc.v:146353.3-146354.67" + wire $0\logical_op__invert_in$10[0:0]$7007 + attribute \src "libresoc.v:145902.7-145902.40" + wire $0\logical_op__invert_in$10[0:0]$7111 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_out$13$next[0:0]$7045 + attribute \src "libresoc.v:146359.3-146360.69" + wire $0\logical_op__invert_out$13[0:0]$7013 + attribute \src "libresoc.v:145911.7-145911.41" + wire $0\logical_op__invert_out$13[0:0]$7113 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7046 + attribute \src "libresoc.v:146365.3-146366.65" + wire $0\logical_op__is_32bit$16[0:0]$7019 + attribute \src "libresoc.v:145920.7-145920.39" + wire $0\logical_op__is_32bit$16[0:0]$7115 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_signed$17$next[0:0]$7047 + attribute \src "libresoc.v:146367.3-146368.67" + wire $0\logical_op__is_signed$17[0:0]$7021 + attribute \src "libresoc.v:145929.7-145929.40" + wire $0\logical_op__is_signed$17[0:0]$7117 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7048 + attribute \src "libresoc.v:146349.3-146350.59" + wire $0\logical_op__oe__oe$8[0:0]$7003 + attribute \src "libresoc.v:145940.7-145940.36" + wire $0\logical_op__oe__oe$8[0:0]$7119 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7049 + attribute \src "libresoc.v:146351.3-146352.59" + wire $0\logical_op__oe__ok$9[0:0]$7005 + attribute \src "libresoc.v:145949.7-145949.36" + wire $0\logical_op__oe__ok$9[0:0]$7121 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__output_carry$15$next[0:0]$7050 + attribute \src "libresoc.v:146363.3-146364.73" + wire $0\logical_op__output_carry$15[0:0]$7017 + attribute \src "libresoc.v:145956.7-145956.43" + wire $0\logical_op__output_carry$15[0:0]$7123 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7051 + attribute \src "libresoc.v:146347.3-146348.59" + wire $0\logical_op__rc__ok$7[0:0]$7001 + attribute \src "libresoc.v:145967.7-145967.36" + wire $0\logical_op__rc__ok$7[0:0]$7125 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7052 + attribute \src "libresoc.v:146345.3-146346.59" + wire $0\logical_op__rc__rc$6[0:0]$6999 + attribute \src "libresoc.v:145976.7-145976.36" + wire $0\logical_op__rc__rc$6[0:0]$7127 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7053 + attribute \src "libresoc.v:146361.3-146362.67" + wire $0\logical_op__write_cr0$14[0:0]$7015 + attribute \src "libresoc.v:145983.7-145983.40" + wire $0\logical_op__write_cr0$14[0:0]$7129 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__zero_a$11$next[0:0]$7054 + attribute \src "libresoc.v:146355.3-146356.61" + wire $0\logical_op__zero_a$11[0:0]$7009 + attribute \src "libresoc.v:145992.7-145992.37" + wire $0\logical_op__zero_a$11[0:0]$7131 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $0\muxid$1$next[1:0]$7034 + attribute \src "libresoc.v:146373.3-146374.33" + wire width 2 $0\muxid$1[1:0]$7027 + attribute \src "libresoc.v:146001.13-146001.29" + wire width 2 $0\muxid$1[1:0]$7133 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $0\o$20$next[63:0]$7080 + attribute \src "libresoc.v:146333.3-146334.27" + wire width 64 $0\o$20[63:0]$6987 + attribute \src "libresoc.v:146016.14-146016.43" + wire width 64 $0\o$20[63:0]$7135 + attribute \src "libresoc.v:146506.3-146524.6" + wire $0\o_ok$21$next[0:0]$7081 + attribute \src "libresoc.v:146335.3-146336.33" + wire $0\o_ok$21[0:0]$6989 + attribute \src "libresoc.v:146025.7-146025.23" + wire $0\o_ok$21[0:0]$7137 + attribute \src "libresoc.v:146433.3-146450.6" + wire $0\r_busy$next[0:0]$7030 + attribute \src "libresoc.v:146375.3-146376.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:144893.3-144911.6" - wire width 4 $1\cr_a$22$next[3:0]$7040 - attribute \src "libresoc.v:144893.3-144911.6" - wire $1\cr_a_ok$23$next[0:0]$7041 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$7007 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7008 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7009 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$7010 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$7011 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$7012 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$7013 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__invert_in$10$next[0:0]$7014 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__invert_out$13$next[0:0]$7015 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__is_32bit$16$next[0:0]$7016 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__is_signed$17$next[0:0]$7017 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__oe__oe$8$next[0:0]$7018 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__oe__ok$9$next[0:0]$7019 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__output_carry$15$next[0:0]$7020 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__rc__ok$7$next[0:0]$7021 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__rc__rc$6$next[0:0]$7022 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__write_cr0$14$next[0:0]$7023 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__zero_a$11$next[0:0]$7024 - attribute \src "libresoc.v:144819.3-144831.6" - wire width 2 $1\muxid$1$next[1:0]$6987 - attribute \src "libresoc.v:144874.3-144892.6" - wire width 64 $1\o$20$next[63:0]$7034 - attribute \src "libresoc.v:144874.3-144892.6" - wire $1\o_ok$21$next[0:0]$7035 - attribute \src "libresoc.v:144801.3-144818.6" - wire $1\r_busy$next[0:0]$6983 - attribute \src "libresoc.v:144687.7-144687.20" + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $1\cr_a$22$next[3:0]$7088 + attribute \src "libresoc.v:146525.3-146543.6" + wire $1\cr_a_ok$23$next[0:0]$7089 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7060 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_in$10$next[0:0]$7062 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_out$13$next[0:0]$7063 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7064 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_signed$17$next[0:0]$7065 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7066 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7067 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__output_carry$15$next[0:0]$7068 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7069 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7070 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7071 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__zero_a$11$next[0:0]$7072 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $1\o$20$next[63:0]$7082 + attribute \src "libresoc.v:146506.3-146524.6" + wire $1\o_ok$21$next[0:0]$7083 + attribute \src "libresoc.v:146433.3-146450.6" + wire $1\r_busy$next[0:0]$7031 + attribute \src "libresoc.v:146319.7-146319.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:144893.3-144911.6" - wire $2\cr_a_ok$23$next[0:0]$7042 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7025 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$7026 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__oe__oe$8$next[0:0]$7027 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__oe__ok$9$next[0:0]$7028 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__rc__ok$7$next[0:0]$7029 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__rc__rc$6$next[0:0]$7030 - attribute \src "libresoc.v:144874.3-144892.6" - wire $2\o_ok$21$next[0:0]$7036 - attribute \src "libresoc.v:144801.3-144818.6" - wire $2\r_busy$next[0:0]$6984 - attribute \src "libresoc.v:144696.18-144696.118" - wire $and$libresoc.v:144696$6933_Y + attribute \src "libresoc.v:146525.3-146543.6" + wire $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7075 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7076 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7077 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146506.3-146524.6" + wire $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146433.3-146450.6" + wire $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146328.18-146328.118" + wire $and$libresoc.v:146328$6981_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -235024,7 +237521,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:143894.7-143894.15" + attribute \src "libresoc.v:145526.7-145526.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -235781,7 +238278,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:144696$6933 + cell $and $and$libresoc.v:146328$6981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235789,16 +238286,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:144696$6933_Y + connect \Y $and$libresoc.v:146328$6981_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:144745.10-144748.4" + attribute \src "libresoc.v:146377.10-146380.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:144749.15-144796.4" + attribute \src "libresoc.v:146381.15-146428.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -235848,388 +238345,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:144797.10-144800.4" + attribute \src "libresoc.v:146429.10-146432.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:143894.7-143894.20" - process $proc$libresoc.v:143894$7043 + attribute \src "libresoc.v:145526.7-145526.20" + process $proc$libresoc.v:145526$7091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143905.13-143905.29" - process $proc$libresoc.v:143905$7044 + attribute \src "libresoc.v:145537.13-145537.29" + process $proc$libresoc.v:145537$7092 assign { } { } - assign $0\cr_a$22[3:0]$7045 4'0000 + assign $0\cr_a$22[3:0]$7093 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$7045 + update \cr_a$22 $0\cr_a$22[3:0]$7093 end - attribute \src "libresoc.v:143914.7-143914.26" - process $proc$libresoc.v:143914$7046 + attribute \src "libresoc.v:145546.7-145546.26" + process $proc$libresoc.v:145546$7094 assign { } { } - assign $0\cr_a_ok$23[0:0]$7047 1'0 + assign $0\cr_a_ok$23[0:0]$7095 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7047 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 end - attribute \src "libresoc.v:143925.13-143925.45" - process $proc$libresoc.v:143925$7048 + attribute \src "libresoc.v:145557.13-145557.45" + process $proc$libresoc.v:145557$7096 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7049 4'0000 + assign $0\logical_op__data_len$18[3:0]$7097 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7049 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 end - attribute \src "libresoc.v:143964.14-143964.48" - process $proc$libresoc.v:143964$7050 + attribute \src "libresoc.v:145596.14-145596.48" + process $proc$libresoc.v:145596$7098 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$7051 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7051 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 end - attribute \src "libresoc.v:143988.14-143988.67" - process $proc$libresoc.v:143988$7052 + attribute \src "libresoc.v:145620.14-145620.67" + process $proc$libresoc.v:145620$7100 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7053 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7053 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 end - attribute \src "libresoc.v:143997.7-143997.42" - process $proc$libresoc.v:143997$7054 + attribute \src "libresoc.v:145629.7-145629.42" + process $proc$libresoc.v:145629$7102 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7055 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7055 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 end - attribute \src "libresoc.v:144014.13-144014.48" - process $proc$libresoc.v:144014$7056 + attribute \src "libresoc.v:145646.13-145646.48" + process $proc$libresoc.v:145646$7104 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7057 2'00 + assign $0\logical_op__input_carry$12[1:0]$7105 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7057 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 end - attribute \src "libresoc.v:144027.14-144027.43" - process $proc$libresoc.v:144027$7058 + attribute \src "libresoc.v:145659.14-145659.43" + process $proc$libresoc.v:145659$7106 assign { } { } - assign $0\logical_op__insn$19[31:0]$7059 0 + assign $0\logical_op__insn$19[31:0]$7107 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7059 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 end - attribute \src "libresoc.v:144186.13-144186.46" - process $proc$libresoc.v:144186$7060 + attribute \src "libresoc.v:145818.13-145818.46" + process $proc$libresoc.v:145818$7108 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7061 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7061 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 end - attribute \src "libresoc.v:144270.7-144270.40" - process $proc$libresoc.v:144270$7062 + attribute \src "libresoc.v:145902.7-145902.40" + process $proc$libresoc.v:145902$7110 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7063 1'0 + assign $0\logical_op__invert_in$10[0:0]$7111 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7063 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 end - attribute \src "libresoc.v:144279.7-144279.41" - process $proc$libresoc.v:144279$7064 + attribute \src "libresoc.v:145911.7-145911.41" + process $proc$libresoc.v:145911$7112 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7065 1'0 + assign $0\logical_op__invert_out$13[0:0]$7113 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7065 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 end - attribute \src "libresoc.v:144288.7-144288.39" - process $proc$libresoc.v:144288$7066 + attribute \src "libresoc.v:145920.7-145920.39" + process $proc$libresoc.v:145920$7114 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7067 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7067 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 end - attribute \src "libresoc.v:144297.7-144297.40" - process $proc$libresoc.v:144297$7068 + attribute \src "libresoc.v:145929.7-145929.40" + process $proc$libresoc.v:145929$7116 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7069 1'0 + assign $0\logical_op__is_signed$17[0:0]$7117 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7069 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 end - attribute \src "libresoc.v:144308.7-144308.36" - process $proc$libresoc.v:144308$7070 + attribute \src "libresoc.v:145940.7-145940.36" + process $proc$libresoc.v:145940$7118 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7071 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7071 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 end - attribute \src "libresoc.v:144317.7-144317.36" - process $proc$libresoc.v:144317$7072 + attribute \src "libresoc.v:145949.7-145949.36" + process $proc$libresoc.v:145949$7120 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7073 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7073 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 end - attribute \src "libresoc.v:144324.7-144324.43" - process $proc$libresoc.v:144324$7074 + attribute \src "libresoc.v:145956.7-145956.43" + process $proc$libresoc.v:145956$7122 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7075 1'0 + assign $0\logical_op__output_carry$15[0:0]$7123 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7075 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 end - attribute \src "libresoc.v:144335.7-144335.36" - process $proc$libresoc.v:144335$7076 + attribute \src "libresoc.v:145967.7-145967.36" + process $proc$libresoc.v:145967$7124 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7077 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7077 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 end - attribute \src "libresoc.v:144344.7-144344.36" - process $proc$libresoc.v:144344$7078 + attribute \src "libresoc.v:145976.7-145976.36" + process $proc$libresoc.v:145976$7126 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7079 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7079 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 end - attribute \src "libresoc.v:144351.7-144351.40" - process $proc$libresoc.v:144351$7080 + attribute \src "libresoc.v:145983.7-145983.40" + process $proc$libresoc.v:145983$7128 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7081 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7081 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 end - attribute \src "libresoc.v:144360.7-144360.37" - process $proc$libresoc.v:144360$7082 + attribute \src "libresoc.v:145992.7-145992.37" + process $proc$libresoc.v:145992$7130 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7083 1'0 + assign $0\logical_op__zero_a$11[0:0]$7131 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7083 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 end - attribute \src "libresoc.v:144369.13-144369.29" - process $proc$libresoc.v:144369$7084 + attribute \src "libresoc.v:146001.13-146001.29" + process $proc$libresoc.v:146001$7132 assign { } { } - assign $0\muxid$1[1:0]$7085 2'00 + assign $0\muxid$1[1:0]$7133 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7085 + update \muxid$1 $0\muxid$1[1:0]$7133 end - attribute \src "libresoc.v:144384.14-144384.43" - process $proc$libresoc.v:144384$7086 + attribute \src "libresoc.v:146016.14-146016.43" + process $proc$libresoc.v:146016$7134 assign { } { } - assign $0\o$20[63:0]$7087 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$7087 + update \o$20 $0\o$20[63:0]$7135 end - attribute \src "libresoc.v:144393.7-144393.23" - process $proc$libresoc.v:144393$7088 + attribute \src "libresoc.v:146025.7-146025.23" + process $proc$libresoc.v:146025$7136 assign { } { } - assign $0\o_ok$21[0:0]$7089 1'0 + assign $0\o_ok$21[0:0]$7137 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$7089 + update \o_ok$21 $0\o_ok$21[0:0]$7137 end - attribute \src "libresoc.v:144687.7-144687.20" - process $proc$libresoc.v:144687$7090 + attribute \src "libresoc.v:146319.7-146319.20" + process $proc$libresoc.v:146319$7138 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:144697.3-144698.33" - process $proc$libresoc.v:144697$6934 + attribute \src "libresoc.v:146329.3-146330.33" + process $proc$libresoc.v:146329$6982 assign { } { } - assign $0\cr_a$22[3:0]$6935 \cr_a$22$next + assign $0\cr_a$22[3:0]$6983 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6935 + update \cr_a$22 $0\cr_a$22[3:0]$6983 end - attribute \src "libresoc.v:144699.3-144700.39" - process $proc$libresoc.v:144699$6936 + attribute \src "libresoc.v:146331.3-146332.39" + process $proc$libresoc.v:146331$6984 assign { } { } - assign $0\cr_a_ok$23[0:0]$6937 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6937 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 end - attribute \src "libresoc.v:144701.3-144702.27" - process $proc$libresoc.v:144701$6938 + attribute \src "libresoc.v:146333.3-146334.27" + process $proc$libresoc.v:146333$6986 assign { } { } - assign $0\o$20[63:0]$6939 \o$20$next + assign $0\o$20[63:0]$6987 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6939 + update \o$20 $0\o$20[63:0]$6987 end - attribute \src "libresoc.v:144703.3-144704.33" - process $proc$libresoc.v:144703$6940 + attribute \src "libresoc.v:146335.3-146336.33" + process $proc$libresoc.v:146335$6988 assign { } { } - assign $0\o_ok$21[0:0]$6941 \o_ok$21$next + assign $0\o_ok$21[0:0]$6989 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6941 + update \o_ok$21 $0\o_ok$21[0:0]$6989 end - attribute \src "libresoc.v:144705.3-144706.65" - process $proc$libresoc.v:144705$6942 + attribute \src "libresoc.v:146337.3-146338.65" + process $proc$libresoc.v:146337$6990 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6943 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6943 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 end - attribute \src "libresoc.v:144707.3-144708.61" - process $proc$libresoc.v:144707$6944 + attribute \src "libresoc.v:146339.3-146340.61" + process $proc$libresoc.v:146339$6992 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$6945 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6945 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 end - attribute \src "libresoc.v:144709.3-144710.75" - process $proc$libresoc.v:144709$6946 + attribute \src "libresoc.v:146341.3-146342.75" + process $proc$libresoc.v:146341$6994 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6947 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6947 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 end - attribute \src "libresoc.v:144711.3-144712.71" - process $proc$libresoc.v:144711$6948 + attribute \src "libresoc.v:146343.3-146344.71" + process $proc$libresoc.v:146343$6996 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6949 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6949 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 end - attribute \src "libresoc.v:144713.3-144714.59" - process $proc$libresoc.v:144713$6950 + attribute \src "libresoc.v:146345.3-146346.59" + process $proc$libresoc.v:146345$6998 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6951 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6951 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 end - attribute \src "libresoc.v:144715.3-144716.59" - process $proc$libresoc.v:144715$6952 + attribute \src "libresoc.v:146347.3-146348.59" + process $proc$libresoc.v:146347$7000 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6953 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6953 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 end - attribute \src "libresoc.v:144717.3-144718.59" - process $proc$libresoc.v:144717$6954 + attribute \src "libresoc.v:146349.3-146350.59" + process $proc$libresoc.v:146349$7002 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6955 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6955 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 end - attribute \src "libresoc.v:144719.3-144720.59" - process $proc$libresoc.v:144719$6956 + attribute \src "libresoc.v:146351.3-146352.59" + process $proc$libresoc.v:146351$7004 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6957 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6957 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 end - attribute \src "libresoc.v:144721.3-144722.67" - process $proc$libresoc.v:144721$6958 + attribute \src "libresoc.v:146353.3-146354.67" + process $proc$libresoc.v:146353$7006 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6959 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6959 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 end - attribute \src "libresoc.v:144723.3-144724.61" - process $proc$libresoc.v:144723$6960 + attribute \src "libresoc.v:146355.3-146356.61" + process $proc$libresoc.v:146355$7008 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6961 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6961 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 end - attribute \src "libresoc.v:144725.3-144726.71" - process $proc$libresoc.v:144725$6962 + attribute \src "libresoc.v:146357.3-146358.71" + process $proc$libresoc.v:146357$7010 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6963 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6963 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 end - attribute \src "libresoc.v:144727.3-144728.69" - process $proc$libresoc.v:144727$6964 + attribute \src "libresoc.v:146359.3-146360.69" + process $proc$libresoc.v:146359$7012 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6965 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6965 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 end - attribute \src "libresoc.v:144729.3-144730.67" - process $proc$libresoc.v:144729$6966 + attribute \src "libresoc.v:146361.3-146362.67" + process $proc$libresoc.v:146361$7014 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6967 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6967 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 end - attribute \src "libresoc.v:144731.3-144732.73" - process $proc$libresoc.v:144731$6968 + attribute \src "libresoc.v:146363.3-146364.73" + process $proc$libresoc.v:146363$7016 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6969 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6969 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 end - attribute \src "libresoc.v:144733.3-144734.65" - process $proc$libresoc.v:144733$6970 + attribute \src "libresoc.v:146365.3-146366.65" + process $proc$libresoc.v:146365$7018 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6971 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6971 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 end - attribute \src "libresoc.v:144735.3-144736.67" - process $proc$libresoc.v:144735$6972 + attribute \src "libresoc.v:146367.3-146368.67" + process $proc$libresoc.v:146367$7020 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6973 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6973 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 end - attribute \src "libresoc.v:144737.3-144738.65" - process $proc$libresoc.v:144737$6974 + attribute \src "libresoc.v:146369.3-146370.65" + process $proc$libresoc.v:146369$7022 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6975 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6975 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 end - attribute \src "libresoc.v:144739.3-144740.57" - process $proc$libresoc.v:144739$6976 + attribute \src "libresoc.v:146371.3-146372.57" + process $proc$libresoc.v:146371$7024 assign { } { } - assign $0\logical_op__insn$19[31:0]$6977 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6977 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 end - attribute \src "libresoc.v:144741.3-144742.33" - process $proc$libresoc.v:144741$6978 + attribute \src "libresoc.v:146373.3-146374.33" + process $proc$libresoc.v:146373$7026 assign { } { } - assign $0\muxid$1[1:0]$6979 \muxid$1$next + assign $0\muxid$1[1:0]$7027 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6979 + update \muxid$1 $0\muxid$1[1:0]$7027 end - attribute \src "libresoc.v:144743.3-144744.29" - process $proc$libresoc.v:144743$6980 + attribute \src "libresoc.v:146375.3-146376.29" + process $proc$libresoc.v:146375$7028 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:144801.3-144818.6" - process $proc$libresoc.v:144801$6981 + attribute \src "libresoc.v:146433.3-146450.6" + process $proc$libresoc.v:146433$7029 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6982 $2\r_busy$next[0:0]$6984 - attribute \src "libresoc.v:144802.5-144802.29" + assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146434.5-146434.29" switch \initial - attribute \src "libresoc.v:144802.9-144802.17" + attribute \src "libresoc.v:146434.9-146434.17" case 1'1 case end @@ -236238,34 +238735,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6983 1'1 + assign $1\r_busy$next[0:0]$7031 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6983 1'0 + assign $1\r_busy$next[0:0]$7031 1'0 case - assign $1\r_busy$next[0:0]$6983 \r_busy + assign $1\r_busy$next[0:0]$7031 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6984 1'0 + assign $2\r_busy$next[0:0]$7032 1'0 case - assign $2\r_busy$next[0:0]$6984 $1\r_busy$next[0:0]$6983 + assign $2\r_busy$next[0:0]$7032 $1\r_busy$next[0:0]$7031 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6982 + update \r_busy$next $0\r_busy$next[0:0]$7030 end - attribute \src "libresoc.v:144819.3-144831.6" - process $proc$libresoc.v:144819$6985 + attribute \src "libresoc.v:146451.3-146463.6" + process $proc$libresoc.v:146451$7033 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$6986 $1\muxid$1$next[1:0]$6987 - attribute \src "libresoc.v:144820.5-144820.29" + assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146452.5-146452.29" switch \initial - attribute \src "libresoc.v:144820.9-144820.17" + attribute \src "libresoc.v:146452.9-146452.17" case 1'1 case end @@ -236274,19 +238771,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$6987 \muxid$51 + assign $1\muxid$1$next[1:0]$7035 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$6987 \muxid$51 + assign $1\muxid$1$next[1:0]$7035 \muxid$51 case - assign $1\muxid$1$next[1:0]$6987 \muxid$1 + assign $1\muxid$1$next[1:0]$7035 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6986 + update \muxid$1$next $0\muxid$1$next[1:0]$7034 end - attribute \src "libresoc.v:144832.3-144873.6" - process $proc$libresoc.v:144832$6988 + attribute \src "libresoc.v:146464.3-146505.6" + process $proc$libresoc.v:146464$7036 assign { } { } assign { } { } assign { } { } @@ -236323,33 +238820,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6989 $1\logical_op__data_len$18$next[3:0]$7007 - assign $0\logical_op__fn_unit$3$next[13:0]$6990 $1\logical_op__fn_unit$3$next[13:0]$7008 + assign $0\logical_op__data_len$18$next[3:0]$7037 $1\logical_op__data_len$18$next[3:0]$7055 + assign $0\logical_op__fn_unit$3$next[13:0]$7038 $1\logical_op__fn_unit$3$next[13:0]$7056 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6993 $1\logical_op__input_carry$12$next[1:0]$7011 - assign $0\logical_op__insn$19$next[31:0]$6994 $1\logical_op__insn$19$next[31:0]$7012 - assign $0\logical_op__insn_type$2$next[6:0]$6995 $1\logical_op__insn_type$2$next[6:0]$7013 - assign $0\logical_op__invert_in$10$next[0:0]$6996 $1\logical_op__invert_in$10$next[0:0]$7014 - assign $0\logical_op__invert_out$13$next[0:0]$6997 $1\logical_op__invert_out$13$next[0:0]$7015 - assign $0\logical_op__is_32bit$16$next[0:0]$6998 $1\logical_op__is_32bit$16$next[0:0]$7016 - assign $0\logical_op__is_signed$17$next[0:0]$6999 $1\logical_op__is_signed$17$next[0:0]$7017 + assign $0\logical_op__input_carry$12$next[1:0]$7041 $1\logical_op__input_carry$12$next[1:0]$7059 + assign $0\logical_op__insn$19$next[31:0]$7042 $1\logical_op__insn$19$next[31:0]$7060 + assign $0\logical_op__insn_type$2$next[6:0]$7043 $1\logical_op__insn_type$2$next[6:0]$7061 + assign $0\logical_op__invert_in$10$next[0:0]$7044 $1\logical_op__invert_in$10$next[0:0]$7062 + assign $0\logical_op__invert_out$13$next[0:0]$7045 $1\logical_op__invert_out$13$next[0:0]$7063 + assign $0\logical_op__is_32bit$16$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7064 + assign $0\logical_op__is_signed$17$next[0:0]$7047 $1\logical_op__is_signed$17$next[0:0]$7065 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$7002 $1\logical_op__output_carry$15$next[0:0]$7020 + assign $0\logical_op__output_carry$15$next[0:0]$7050 $1\logical_op__output_carry$15$next[0:0]$7068 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$7005 $1\logical_op__write_cr0$14$next[0:0]$7023 - assign $0\logical_op__zero_a$11$next[0:0]$7006 $1\logical_op__zero_a$11$next[0:0]$7024 - assign $0\logical_op__imm_data__data$4$next[63:0]$6991 $2\logical_op__imm_data__data$4$next[63:0]$7025 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6992 $2\logical_op__imm_data__ok$5$next[0:0]$7026 - assign $0\logical_op__oe__oe$8$next[0:0]$7000 $2\logical_op__oe__oe$8$next[0:0]$7027 - assign $0\logical_op__oe__ok$9$next[0:0]$7001 $2\logical_op__oe__ok$9$next[0:0]$7028 - assign $0\logical_op__rc__ok$7$next[0:0]$7003 $2\logical_op__rc__ok$7$next[0:0]$7029 - assign $0\logical_op__rc__rc$6$next[0:0]$7004 $2\logical_op__rc__rc$6$next[0:0]$7030 - attribute \src "libresoc.v:144833.5-144833.29" + assign $0\logical_op__write_cr0$14$next[0:0]$7053 $1\logical_op__write_cr0$14$next[0:0]$7071 + assign $0\logical_op__zero_a$11$next[0:0]$7054 $1\logical_op__zero_a$11$next[0:0]$7072 + assign $0\logical_op__imm_data__data$4$next[63:0]$7039 $2\logical_op__imm_data__data$4$next[63:0]$7073 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7040 $2\logical_op__imm_data__ok$5$next[0:0]$7074 + assign $0\logical_op__oe__oe$8$next[0:0]$7048 $2\logical_op__oe__oe$8$next[0:0]$7075 + assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 + assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 + assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146465.5-146465.29" switch \initial - attribute \src "libresoc.v:144833.9-144833.17" + attribute \src "libresoc.v:146465.9-146465.17" case 1'1 case end @@ -236375,7 +238872,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -236396,26 +238893,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$7007 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$7008 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$7009 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$7010 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$7011 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$7012 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$7013 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$7014 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$7015 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$7016 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$7017 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$7018 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$7019 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$7020 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$7021 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$7022 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$7023 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$7024 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$7055 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7056 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7057 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7058 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7059 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7060 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7061 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7062 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7063 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7064 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7065 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7066 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7067 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7068 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7069 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7070 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7071 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7072 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -236427,52 +238924,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$7025 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$7030 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$7029 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$7027 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$7028 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$7025 $1\logical_op__imm_data__data$4$next[63:0]$7009 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 $1\logical_op__imm_data__ok$5$next[0:0]$7010 - assign $2\logical_op__oe__oe$8$next[0:0]$7027 $1\logical_op__oe__oe$8$next[0:0]$7018 - assign $2\logical_op__oe__ok$9$next[0:0]$7028 $1\logical_op__oe__ok$9$next[0:0]$7019 - assign $2\logical_op__rc__ok$7$next[0:0]$7029 $1\logical_op__rc__ok$7$next[0:0]$7021 - assign $2\logical_op__rc__rc$6$next[0:0]$7030 $1\logical_op__rc__rc$6$next[0:0]$7022 + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 $1\logical_op__imm_data__data$4$next[63:0]$7057 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 $1\logical_op__imm_data__ok$5$next[0:0]$7058 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 $1\logical_op__oe__oe$8$next[0:0]$7066 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 $1\logical_op__oe__ok$9$next[0:0]$7067 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 $1\logical_op__rc__ok$7$next[0:0]$7069 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 $1\logical_op__rc__rc$6$next[0:0]$7070 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6989 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6990 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6991 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6992 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6993 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6994 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6995 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6996 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6997 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6998 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6999 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7000 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7001 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7002 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7003 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7004 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7005 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7006 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7037 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7038 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7039 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7040 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7041 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7042 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7043 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7044 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7045 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7046 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7047 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7048 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7049 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7050 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7051 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7052 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 end - attribute \src "libresoc.v:144874.3-144892.6" - process $proc$libresoc.v:144874$7031 + attribute \src "libresoc.v:146506.3-146524.6" + process $proc$libresoc.v:146506$7079 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$7032 $1\o$20$next[63:0]$7034 + assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 assign { } { } - assign $0\o_ok$21$next[0:0]$7033 $2\o_ok$21$next[0:0]$7036 - attribute \src "libresoc.v:144875.5-144875.29" + assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146507.5-146507.29" switch \initial - attribute \src "libresoc.v:144875.9-144875.17" + attribute \src "libresoc.v:146507.9-146507.17" case 1'1 case end @@ -236482,41 +238979,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$7034 \o$20 - assign $1\o_ok$21$next[0:0]$7035 \o_ok$21 + assign $1\o$20$next[63:0]$7082 \o$20 + assign $1\o_ok$21$next[0:0]$7083 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$7036 1'0 + assign $2\o_ok$21$next[0:0]$7084 1'0 case - assign $2\o_ok$21$next[0:0]$7036 $1\o_ok$21$next[0:0]$7035 + assign $2\o_ok$21$next[0:0]$7084 $1\o_ok$21$next[0:0]$7083 end sync always - update \o$20$next $0\o$20$next[63:0]$7032 - update \o_ok$21$next $0\o_ok$21$next[0:0]$7033 + update \o$20$next $0\o$20$next[63:0]$7080 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 end - attribute \src "libresoc.v:144893.3-144911.6" - process $proc$libresoc.v:144893$7037 + attribute \src "libresoc.v:146525.3-146543.6" + process $proc$libresoc.v:146525$7085 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$7038 $1\cr_a$22$next[3:0]$7040 + assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$7039 $2\cr_a_ok$23$next[0:0]$7042 - attribute \src "libresoc.v:144894.5-144894.29" + assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146526.5-146526.29" switch \initial - attribute \src "libresoc.v:144894.9-144894.17" + attribute \src "libresoc.v:146526.9-146526.17" case 1'1 case end @@ -236526,30 +239023,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$7040 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$7041 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7088 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7089 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$7042 1'0 + assign $2\cr_a_ok$23$next[0:0]$7090 1'0 case - assign $2\cr_a_ok$23$next[0:0]$7042 $1\cr_a_ok$23$next[0:0]$7041 + assign $2\cr_a_ok$23$next[0:0]$7090 $1\cr_a_ok$23$next[0:0]$7089 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$7038 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7039 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 end - connect \$49 $and$libresoc.v:144696$6933_Y + connect \$49 $and$libresoc.v:146328$6981_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -237334,15 +239831,15 @@ module \ls180 wire $0\main_libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:182.12-182.74" + attribute \src "ls180.v:204.12-204.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:179.5-179.69" + attribute \src "ls180.v:176.5-176.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:172.5-172.72" + attribute \src "ls180.v:181.5-181.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:175.11-175.79" + attribute \src "ls180.v:184.11-184.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:195.12-195.78" + attribute \src "ls180.v:188.12-188.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -248066,24 +250563,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:42.19-42.23" - wire width 3 input 38 \eint - attribute \src "ls180.v:206.12-206.18" + attribute \src "ls180.v:13.19-13.23" + wire width 3 input 9 \eint + attribute \src "ls180.v:179.12-179.18" wire width 3 \eint_1 - attribute \src "ls180.v:18.21-18.27" - wire width 16 output 14 \gpio_i - attribute \src "ls180.v:19.20-19.26" - wire width 16 output 15 \gpio_o - attribute \src "ls180.v:20.20-20.27" - wire width 16 output 16 \gpio_oe - attribute \src "ls180.v:14.14-14.21" - wire output 10 \i2c_scl - attribute \src "ls180.v:15.14-15.23" - wire output 11 \i2c_sda_i - attribute \src "ls180.v:16.14-16.23" - wire output 12 \i2c_sda_o - attribute \src "ls180.v:17.14-17.24" - wire output 13 \i2c_sda_oe + attribute \src "ls180.v:40.21-40.27" + wire width 16 output 36 \gpio_i + attribute \src "ls180.v:41.20-41.26" + wire width 16 output 37 \gpio_o + attribute \src "ls180.v:42.20-42.27" + wire width 16 output 38 \gpio_oe + attribute \src "ls180.v:9.14-9.21" + wire output 5 \i2c_scl + attribute \src "ls180.v:10.14-10.23" + wire output 6 \i2c_sda_i + attribute \src "ls180.v:11.14-11.23" + wire output 7 \i2c_sda_o + attribute \src "ls180.v:12.14-12.24" + wire output 8 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -248442,71 +250939,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:182.12-182.66" + attribute \src "ls180.v:204.12-204.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:183.13-183.67" + attribute \src "ls180.v:205.13-205.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:184.13-184.68" + attribute \src "ls180.v:206.13-206.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:178.6-178.61" + attribute \src "ls180.v:175.6-175.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:179.5-179.62" + attribute \src "ls180.v:176.5-176.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:180.6-180.63" + attribute \src "ls180.v:177.6-177.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:181.6-181.64" + attribute \src "ls180.v:178.6-178.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:171.6-171.64" + attribute \src "ls180.v:180.6-180.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:172.5-172.65" + attribute \src "ls180.v:181.5-181.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:173.6-173.66" + attribute \src "ls180.v:182.6-182.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:174.6-174.67" + attribute \src "ls180.v:183.6-183.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:175.11-175.72" + attribute \src "ls180.v:184.11-184.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:176.12-176.73" + attribute \src "ls180.v:185.12-185.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:177.6-177.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:194.13-194.68" + attribute \src "ls180.v:187.13-187.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:203.12-203.68" + attribute \src "ls180.v:196.12-196.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:200.6-200.65" + attribute \src "ls180.v:193.6-193.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:202.6-202.63" + attribute \src "ls180.v:195.6-195.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:201.6-201.64" + attribute \src "ls180.v:194.6-194.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:204.12-204.68" + attribute \src "ls180.v:197.12-197.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:195.12-195.70" + attribute \src "ls180.v:188.12-188.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:196.13-196.71" + attribute \src "ls180.v:189.13-189.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:197.6-197.65" + attribute \src "ls180.v:190.6-190.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:199.6-199.65" + attribute \src "ls180.v:192.6-192.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:198.6-198.64" + attribute \src "ls180.v:191.6-191.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:185.6-185.67" + attribute \src "ls180.v:171.6-171.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:187.6-187.68" + attribute \src "ls180.v:173.6-173.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:188.6-188.68" + attribute \src "ls180.v:174.6-174.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:186.6-186.68" + attribute \src "ls180.v:172.6-172.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:189.6-189.67" + attribute \src "ls180.v:199.6-199.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:191.6-191.68" + attribute \src "ls180.v:201.6-201.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:192.6-192.68" + attribute \src "ls180.v:202.6-202.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:190.6-190.68" + attribute \src "ls180.v:200.6-200.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -251836,50 +254333,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:29.19-29.22" - wire width 2 output 25 \pwm - attribute \src "ls180.v:193.12-193.17" + attribute \src "ls180.v:39.19-39.22" + wire width 2 output 35 \pwm + attribute \src "ls180.v:203.12-203.17" wire width 2 \pwm_1 - attribute \src "ls180.v:5.13-5.23" - wire output 1 \sdcard_clk - attribute \src "ls180.v:6.14-6.26" - wire output 2 \sdcard_cmd_i - attribute \src "ls180.v:7.13-7.25" - wire output 3 \sdcard_cmd_o - attribute \src "ls180.v:8.13-8.26" - wire output 4 \sdcard_cmd_oe - attribute \src "ls180.v:9.20-9.33" - wire width 4 output 5 \sdcard_data_i - attribute \src "ls180.v:10.19-10.32" - wire width 4 output 6 \sdcard_data_o - attribute \src "ls180.v:11.13-11.27" - wire output 7 \sdcard_data_oe - attribute \src "ls180.v:30.20-30.27" - wire width 13 output 26 \sdram_a - attribute \src "ls180.v:39.19-39.27" - wire width 2 output 35 \sdram_ba - attribute \src "ls180.v:36.13-36.24" - wire output 32 \sdram_cas_n - attribute \src "ls180.v:38.13-38.22" - wire output 34 \sdram_cke - attribute \src "ls180.v:41.13-41.24" - wire output 37 \sdram_clock - attribute \src "ls180.v:205.6-205.19" + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdcard_clk + attribute \src "ls180.v:15.14-15.26" + wire output 11 \sdcard_cmd_i + attribute \src "ls180.v:16.13-16.25" + wire output 12 \sdcard_cmd_o + attribute \src "ls180.v:17.13-17.26" + wire output 13 \sdcard_cmd_oe + attribute \src "ls180.v:18.20-18.33" + wire width 4 output 14 \sdcard_data_i + attribute \src "ls180.v:19.19-19.32" + wire width 4 output 15 \sdcard_data_o + attribute \src "ls180.v:20.13-20.27" + wire output 16 \sdcard_data_oe + attribute \src "ls180.v:21.20-21.27" + wire width 13 output 17 \sdram_a + attribute \src "ls180.v:30.19-30.27" + wire width 2 output 26 \sdram_ba + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_cas_n + attribute \src "ls180.v:29.13-29.22" + wire output 25 \sdram_cke + attribute \src "ls180.v:32.13-32.24" + wire output 28 \sdram_clock + attribute \src "ls180.v:198.6-198.19" wire \sdram_clock_1 - attribute \src "ls180.v:37.13-37.23" - wire output 33 \sdram_cs_n - attribute \src "ls180.v:40.19-40.27" - wire width 2 output 36 \sdram_dm - attribute \src "ls180.v:31.21-31.31" - wire width 16 output 27 \sdram_dq_i - attribute \src "ls180.v:32.20-32.30" - wire width 16 output 28 \sdram_dq_o - attribute \src "ls180.v:33.13-33.24" - wire output 29 \sdram_dq_oe - attribute \src "ls180.v:35.13-35.24" - wire output 31 \sdram_ras_n - attribute \src "ls180.v:34.13-34.23" - wire output 30 \sdram_we_n + attribute \src "ls180.v:28.13-28.23" + wire output 24 \sdram_cs_n + attribute \src "ls180.v:31.19-31.27" + wire width 2 output 27 \sdram_dm + attribute \src "ls180.v:22.21-22.31" + wire width 16 output 18 \sdram_dq_i + attribute \src "ls180.v:23.20-23.30" + wire width 16 output 19 \sdram_dq_o + attribute \src "ls180.v:24.13-24.24" + wire output 20 \sdram_dq_oe + attribute \src "ls180.v:26.13-26.24" + wire output 22 \sdram_ras_n + attribute \src "ls180.v:25.13-25.23" + wire output 21 \sdram_we_n attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk attribute \src "ls180.v:2764.6-2764.17" @@ -252018,22 +254515,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:21.13-21.26" - wire output 17 \spimaster_clk - attribute \src "ls180.v:23.13-23.27" - wire output 19 \spimaster_cs_n - attribute \src "ls180.v:24.13-24.27" - wire input 20 \spimaster_miso - attribute \src "ls180.v:22.13-22.27" - wire output 18 \spimaster_mosi - attribute \src "ls180.v:25.13-25.26" - wire output 21 \spisdcard_clk - attribute \src "ls180.v:27.13-27.27" - wire output 23 \spisdcard_cs_n - attribute \src "ls180.v:28.13-28.27" - wire input 24 \spisdcard_miso - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spisdcard_mosi + attribute \src "ls180.v:5.13-5.26" + wire output 1 \spimaster_clk + attribute \src "ls180.v:7.13-7.27" + wire output 3 \spimaster_cs_n + attribute \src "ls180.v:8.13-8.27" + wire input 4 \spimaster_miso + attribute \src "ls180.v:6.13-6.27" + wire output 2 \spimaster_mosi + attribute \src "ls180.v:33.13-33.26" + wire output 29 \spisdcard_clk + attribute \src "ls180.v:35.13-35.27" + wire output 31 \spisdcard_cs_n + attribute \src "ls180.v:36.13-36.27" + wire input 32 \spisdcard_miso + attribute \src "ls180.v:34.13-34.27" + wire output 30 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:339.6-339.15" @@ -252048,10 +254545,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:13.13-13.20" - wire input 9 \uart_rx - attribute \src "ls180.v:12.13-12.20" - wire output 8 \uart_tx + attribute \src "ls180.v:38.13-38.20" + wire input 34 \uart_rx + attribute \src "ls180.v:37.13-37.20" + wire output 33 \uart_tx attribute \src "ls180.v:10351.12-10351.15" memory width 64 size 64 \mem attribute \src "ls180.v:10379.12-10379.17" @@ -285618,14 +288115,6 @@ module \ls180 sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:172.5-172.72" - process $proc$ls180.v:172$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end attribute \src "ls180.v:1725.5-1725.45" process $proc$ls180.v:1725$3797 assign { } { } @@ -285754,14 +288243,6 @@ module \ls180 update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:175.11-175.79" - process $proc$ls180.v:175$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end attribute \src "ls180.v:1751.11-1751.41" process $proc$ls180.v:1751$3813 assign { } { } @@ -285810,6 +288291,14 @@ module \ls180 update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end + attribute \src "ls180.v:176.5-176.69" + process $proc$ls180.v:176$3150 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end attribute \src "ls180.v:1764.5-1764.43" process $proc$ls180.v:1764$3819 assign { } { } @@ -285962,14 +288451,6 @@ module \ls180 sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:179.5-179.69" - process $proc$ls180.v:179$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end attribute \src "ls180.v:1799.11-1799.64" process $proc$ls180.v:1799$3838 assign { } { } @@ -285986,12 +288467,12 @@ module \ls180 sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:182.12-182.74" - process $proc$ls180.v:182$3153 + attribute \src "ls180.v:181.5-181.72" + process $proc$ls180.v:181$3151 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init end attribute \src "ls180.v:1825.11-1825.45" @@ -286034,6 +288515,14 @@ module \ls180 sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end + attribute \src "ls180.v:184.11-184.79" + process $proc$ls180.v:184$3152 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end attribute \src "ls180.v:1842.5-1842.36" process $proc$ls180.v:1842$3845 assign { } { } @@ -286242,6 +288731,14 @@ module \ls180 update \builder_locked1 $0\builder_locked1[0:0] sync init end + attribute \src "ls180.v:188.12-188.78" + process $proc$ls180.v:188$3153 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end attribute \src "ls180.v:1880.5-1880.27" process $proc$ls180.v:1880$3871 assign { } { } @@ -286802,14 +289299,6 @@ module \ls180 sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:195.12-195.78" - process $proc$ls180.v:195$3154 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end attribute \src "ls180.v:1950.5-1950.59" process $proc$ls180.v:1950$3941 assign { } { } @@ -287186,6 +289675,14 @@ module \ls180 sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end + attribute \src "ls180.v:204.12-204.74" + process $proc$ls180.v:204$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end attribute \src "ls180.v:2061.11-2061.51" process $proc$ls180.v:2061$3988 assign { } { } @@ -288370,16 +290867,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 assign $0\main_converter1_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state attribute \src "ls180.v:2978.2-3011.9" switch \builder_converter1_state @@ -288483,8 +290980,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 assign $0\main_wb_sdram_sel[3:0] 4'0000 assign $0\main_wb_sdram_cyc[0:0] 1'0 @@ -288492,7 +290990,6 @@ module \ls180 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state @@ -288807,10 +291304,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re attribute \src "ls180.v:3254.6-3254.33" @@ -288846,10 +291343,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign { } { } assign $0\builder_refresher_next_state[1:0] \builder_refresher_state attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state @@ -288998,6 +291495,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 @@ -289010,8 +291509,6 @@ module \ls180 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state attribute \src "ls180.v:3418.2-3494.9" switch \builder_bankmachine0_state @@ -289235,6 +291732,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 @@ -289247,8 +291746,6 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state attribute \src "ls180.v:3575.2-3651.9" switch \builder_bankmachine1_state @@ -289528,20 +292025,20 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state @@ -289773,20 +292270,20 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state @@ -290268,8 +292765,8 @@ module \ls180 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\main_sdram_en0[0:0] 1'0 assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed @@ -290414,8 +292911,8 @@ module \ls180 process $proc$ls180.v:4187$676 assign { } { } assign { } { } - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 attribute \src "ls180.v:4190.2-4199.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" @@ -290484,6 +292981,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign { } { } assign $0\main_litedram_wb_stb[0:0] 1'0 @@ -290493,7 +292991,6 @@ module \ls180 assign $0\main_converter_skip[0:0] 1'0 assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\builder_converter_next_state[0:0] \builder_converter_state attribute \src "ls180.v:4231.2-4264.9" switch \builder_converter_state @@ -290707,6 +293204,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spimaster25_clk_enable[0:0] 1'0 @@ -290715,7 +293213,6 @@ module \ls180 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 - assign { } { } assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state attribute \src "ls180.v:4431.2-4467.9" switch \builder_spimaster0_state @@ -290936,6 +293433,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 @@ -290943,7 +293441,6 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state @@ -291203,6 +293700,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 @@ -291218,7 +293716,6 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:4751.2-4825.9" switch \builder_sdphy_sdphycmdr_state @@ -291442,12 +293939,12 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state @@ -291496,6 +293993,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 @@ -291504,7 +294002,6 @@ module \ls180 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state attribute \src "ls180.v:4899.2-4959.9" switch \builder_sdphy_fsm_state @@ -291686,21 +294183,21 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state @@ -292053,21 +294550,21 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:5230.2-5291.9" switch \builder_sdcore_crcupstreaminserter_state @@ -292412,6 +294909,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 @@ -292450,7 +294948,6 @@ module \ls180 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state @@ -293018,13 +295515,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state @@ -293176,6 +295673,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 @@ -293183,8 +295682,6 @@ module \ls180 assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign { } { } assign $0\builder_next_state[1:0] \builder_state attribute \src "ls180.v:5859.2-5883.9" switch \builder_state @@ -295119,13 +297616,13 @@ module \ls180 end attribute \src "ls180.v:7705.1-10349.4" process $proc$ls180.v:7705$2573 - assign $0\uart_tx[0:0] \uart_tx assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } + assign $0\uart_tx[0:0] \uart_tx assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } @@ -299699,13 +302196,13 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\uart_tx[0:0] 1'1 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 assign $0\pwm[1:0] 2'00 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 @@ -299994,13 +302491,13 @@ module \ls180 case end sync posedge \sys_clk_1 - update \uart_tx $0\uart_tx[0:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] @@ -303083,37 +305580,37 @@ module \ls180 connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA end -attribute \src "libresoc.v:144930.1-144988.10" +attribute \src "libresoc.v:146562.1-146620.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:144931.7-144931.20" + attribute \src "libresoc.v:146563.7-146563.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144976.3-144984.6" - wire $0\q_int$next[0:0]$7101 - attribute \src "libresoc.v:144974.3-144975.27" + attribute \src "libresoc.v:146608.3-146616.6" + wire $0\q_int$next[0:0]$7149 + attribute \src "libresoc.v:146606.3-146607.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:144976.3-144984.6" - wire $1\q_int$next[0:0]$7102 - attribute \src "libresoc.v:144953.7-144953.19" + attribute \src "libresoc.v:146608.3-146616.6" + wire $1\q_int$next[0:0]$7150 + attribute \src "libresoc.v:146585.7-146585.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:144966.17-144966.96" - wire $and$libresoc.v:144966$7091_Y - attribute \src "libresoc.v:144971.17-144971.96" - wire $and$libresoc.v:144971$7096_Y - attribute \src "libresoc.v:144968.18-144968.93" - wire $not$libresoc.v:144968$7093_Y - attribute \src "libresoc.v:144970.17-144970.92" - wire $not$libresoc.v:144970$7095_Y - attribute \src "libresoc.v:144973.17-144973.92" - wire $not$libresoc.v:144973$7098_Y - attribute \src "libresoc.v:144967.18-144967.98" - wire $or$libresoc.v:144967$7092_Y - attribute \src "libresoc.v:144969.18-144969.99" - wire $or$libresoc.v:144969$7094_Y - attribute \src "libresoc.v:144972.17-144972.97" - wire $or$libresoc.v:144972$7097_Y + attribute \src "libresoc.v:146598.17-146598.96" + wire $and$libresoc.v:146598$7139_Y + attribute \src "libresoc.v:146603.17-146603.96" + wire $and$libresoc.v:146603$7144_Y + attribute \src "libresoc.v:146600.18-146600.93" + wire $not$libresoc.v:146600$7141_Y + attribute \src "libresoc.v:146602.17-146602.92" + wire $not$libresoc.v:146602$7143_Y + attribute \src "libresoc.v:146605.17-146605.92" + wire $not$libresoc.v:146605$7146_Y + attribute \src "libresoc.v:146599.18-146599.98" + wire $or$libresoc.v:146599$7140_Y + attribute \src "libresoc.v:146601.18-146601.99" + wire $or$libresoc.v:146601$7142_Y + attribute \src "libresoc.v:146604.17-146604.97" + wire $or$libresoc.v:146604$7145_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -303130,11 +305627,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:144931.7-144931.15" + attribute \src "libresoc.v:146563.7-146563.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -303151,7 +305648,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:144966$7091 + cell $and $and$libresoc.v:146598$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303159,10 +305656,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:144966$7091_Y + connect \Y $and$libresoc.v:146598$7139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:144971$7096 + cell $and $and$libresoc.v:146603$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303170,34 +305667,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:144971$7096_Y + connect \Y $and$libresoc.v:146603$7144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:144968$7093 + cell $not $not$libresoc.v:146600$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:144968$7093_Y + connect \Y $not$libresoc.v:146600$7141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:144970$7095 + cell $not $not$libresoc.v:146602$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:144970$7095_Y + connect \Y $not$libresoc.v:146602$7143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:144973$7098 + cell $not $not$libresoc.v:146605$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:144973$7098_Y + connect \Y $not$libresoc.v:146605$7146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:144967$7092 + cell $or $or$libresoc.v:146599$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303205,10 +305702,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:144967$7092_Y + connect \Y $or$libresoc.v:146599$7140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:144969$7094 + cell $or $or$libresoc.v:146601$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303216,10 +305713,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:144969$7094_Y + connect \Y $or$libresoc.v:146601$7142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:144972$7097 + cell $or $or$libresoc.v:146604$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303227,39 +305724,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:144972$7097_Y + connect \Y $or$libresoc.v:146604$7145_Y end - attribute \src "libresoc.v:144931.7-144931.20" - process $proc$libresoc.v:144931$7103 + attribute \src "libresoc.v:146563.7-146563.20" + process $proc$libresoc.v:146563$7151 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144953.7-144953.19" - process $proc$libresoc.v:144953$7104 + attribute \src "libresoc.v:146585.7-146585.19" + process $proc$libresoc.v:146585$7152 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:144974.3-144975.27" - process $proc$libresoc.v:144974$7099 + attribute \src "libresoc.v:146606.3-146607.27" + process $proc$libresoc.v:146606$7147 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:144976.3-144984.6" - process $proc$libresoc.v:144976$7100 + attribute \src "libresoc.v:146608.3-146616.6" + process $proc$libresoc.v:146608$7148 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7101 $1\q_int$next[0:0]$7102 - attribute \src "libresoc.v:144977.5-144977.29" + assign $0\q_int$next[0:0]$7149 $1\q_int$next[0:0]$7150 + attribute \src "libresoc.v:146609.5-146609.29" switch \initial - attribute \src "libresoc.v:144977.9-144977.17" + attribute \src "libresoc.v:146609.9-146609.17" case 1'1 case end @@ -303268,266 +305765,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7102 1'0 + assign $1\q_int$next[0:0]$7150 1'0 case - assign $1\q_int$next[0:0]$7102 \$5 + assign $1\q_int$next[0:0]$7150 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7101 + update \q_int$next $0\q_int$next[0:0]$7149 end - connect \$9 $and$libresoc.v:144966$7091_Y - connect \$11 $or$libresoc.v:144967$7092_Y - connect \$13 $not$libresoc.v:144968$7093_Y - connect \$15 $or$libresoc.v:144969$7094_Y - connect \$1 $not$libresoc.v:144970$7095_Y - connect \$3 $and$libresoc.v:144971$7096_Y - connect \$5 $or$libresoc.v:144972$7097_Y - connect \$7 $not$libresoc.v:144973$7098_Y + connect \$9 $and$libresoc.v:146598$7139_Y + connect \$11 $or$libresoc.v:146599$7140_Y + connect \$13 $not$libresoc.v:146600$7141_Y + connect \$15 $or$libresoc.v:146601$7142_Y + connect \$1 $not$libresoc.v:146602$7143_Y + connect \$3 $and$libresoc.v:146603$7144_Y + connect \$5 $or$libresoc.v:146604$7145_Y + connect \$7 $not$libresoc.v:146605$7146_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:144992.1-145526.10" +attribute \src "libresoc.v:146624.1-147158.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $0\dbus__adr$next[44:0]$7190 - attribute \src "libresoc.v:145230.3-145231.35" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $0\dbus__adr$next[44:0]$7238 + attribute \src "libresoc.v:146862.3-146863.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:145240.3-145267.6" - wire $0\dbus__cyc$next[0:0]$7164 - attribute \src "libresoc.v:145238.3-145239.35" + attribute \src "libresoc.v:146872.3-146899.6" + wire $0\dbus__cyc$next[0:0]$7212 + attribute \src "libresoc.v:146870.3-146871.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7200 - attribute \src "libresoc.v:145226.3-145227.39" + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7248 + attribute \src "libresoc.v:146858.3-146859.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $0\dbus__sel$next[7:0]$7178 - attribute \src "libresoc.v:145234.3-145235.35" + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $0\dbus__sel$next[7:0]$7226 + attribute \src "libresoc.v:146866.3-146867.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:145268.3-145295.6" - wire $0\dbus__stb$next[0:0]$7170 - attribute \src "libresoc.v:145236.3-145237.35" + attribute \src "libresoc.v:146900.3-146927.6" + wire $0\dbus__stb$next[0:0]$7218 + attribute \src "libresoc.v:146868.3-146869.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:145406.3-145431.6" - wire $0\dbus__we$next[0:0]$7195 - attribute \src "libresoc.v:145228.3-145229.33" + attribute \src "libresoc.v:147038.3-147063.6" + wire $0\dbus__we$next[0:0]$7243 + attribute \src "libresoc.v:146860.3-146861.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:144993.7-144993.20" + attribute \src "libresoc.v:146625.7-146625.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7215 - attribute \src "libresoc.v:145220.3-145221.39" + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7263 + attribute \src "libresoc.v:146852.3-146853.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:146938.3-146955.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7184 - attribute \src "libresoc.v:145232.3-145233.39" + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7232 + attribute \src "libresoc.v:146864.3-146865.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:145458.3-145480.6" - wire $0\m_load_err_o$next[0:0]$7205 - attribute \src "libresoc.v:145224.3-145225.41" + attribute \src "libresoc.v:147090.3-147112.6" + wire $0\m_load_err_o$next[0:0]$7253 + attribute \src "libresoc.v:146856.3-146857.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:145481.3-145503.6" - wire $0\m_store_err_o$next[0:0]$7210 - attribute \src "libresoc.v:145222.3-145223.43" + attribute \src "libresoc.v:147113.3-147135.6" + wire $0\m_store_err_o$next[0:0]$7258 + attribute \src "libresoc.v:146854.3-146855.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:145296.3-145305.6" + attribute \src "libresoc.v:146928.3-146937.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $1\dbus__adr$next[44:0]$7191 - attribute \src "libresoc.v:145098.14-145098.42" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $1\dbus__adr$next[44:0]$7239 + attribute \src "libresoc.v:146730.14-146730.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:145240.3-145267.6" - wire $1\dbus__cyc$next[0:0]$7165 - attribute \src "libresoc.v:145103.7-145103.23" + attribute \src "libresoc.v:146872.3-146899.6" + wire $1\dbus__cyc$next[0:0]$7213 + attribute \src "libresoc.v:146735.7-146735.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7201 - attribute \src "libresoc.v:145110.14-145110.48" + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7249 + attribute \src "libresoc.v:146742.14-146742.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $1\dbus__sel$next[7:0]$7179 - attribute \src "libresoc.v:145117.13-145117.30" + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $1\dbus__sel$next[7:0]$7227 + attribute \src "libresoc.v:146749.13-146749.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:145268.3-145295.6" - wire $1\dbus__stb$next[0:0]$7171 - attribute \src "libresoc.v:145122.7-145122.23" + attribute \src "libresoc.v:146900.3-146927.6" + wire $1\dbus__stb$next[0:0]$7219 + attribute \src "libresoc.v:146754.7-146754.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:145406.3-145431.6" - wire $1\dbus__we$next[0:0]$7196 - attribute \src "libresoc.v:145127.7-145127.22" + attribute \src "libresoc.v:147038.3-147063.6" + wire $1\dbus__we$next[0:0]$7244 + attribute \src "libresoc.v:146759.7-146759.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7216 - attribute \src "libresoc.v:145131.14-145131.44" + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7264 + attribute \src "libresoc.v:146763.14-146763.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:146938.3-146955.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7185 - attribute \src "libresoc.v:145138.14-145138.48" + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7233 + attribute \src "libresoc.v:146770.14-146770.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:145458.3-145480.6" - wire $1\m_load_err_o$next[0:0]$7206 - attribute \src "libresoc.v:145142.7-145142.26" + attribute \src "libresoc.v:147090.3-147112.6" + wire $1\m_load_err_o$next[0:0]$7254 + attribute \src "libresoc.v:146774.7-146774.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:145481.3-145503.6" - wire $1\m_store_err_o$next[0:0]$7211 - attribute \src "libresoc.v:145148.7-145148.27" + attribute \src "libresoc.v:147113.3-147135.6" + wire $1\m_store_err_o$next[0:0]$7259 + attribute \src "libresoc.v:146780.7-146780.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:145296.3-145305.6" + attribute \src "libresoc.v:146928.3-146937.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $2\dbus__adr$next[44:0]$7192 - attribute \src "libresoc.v:145240.3-145267.6" - wire $2\dbus__cyc$next[0:0]$7166 - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7202 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $2\dbus__sel$next[7:0]$7180 - attribute \src "libresoc.v:145268.3-145295.6" - wire $2\dbus__stb$next[0:0]$7172 - attribute \src "libresoc.v:145406.3-145431.6" - wire $2\dbus__we$next[0:0]$7197 - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7217 - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $2\dbus__adr$next[44:0]$7240 + attribute \src "libresoc.v:146872.3-146899.6" + wire $2\dbus__cyc$next[0:0]$7214 + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7250 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $2\dbus__sel$next[7:0]$7228 + attribute \src "libresoc.v:146900.3-146927.6" + wire $2\dbus__stb$next[0:0]$7220 + attribute \src "libresoc.v:147038.3-147063.6" + wire $2\dbus__we$next[0:0]$7245 + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7265 + attribute \src "libresoc.v:146938.3-146955.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7186 - attribute \src "libresoc.v:145458.3-145480.6" - wire $2\m_load_err_o$next[0:0]$7207 - attribute \src "libresoc.v:145481.3-145503.6" - wire $2\m_store_err_o$next[0:0]$7212 - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $3\dbus__adr$next[44:0]$7193 - attribute \src "libresoc.v:145240.3-145267.6" - wire $3\dbus__cyc$next[0:0]$7167 - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7203 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $3\dbus__sel$next[7:0]$7181 - attribute \src "libresoc.v:145268.3-145295.6" - wire $3\dbus__stb$next[0:0]$7173 - attribute \src "libresoc.v:145406.3-145431.6" - wire $3\dbus__we$next[0:0]$7198 - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7218 - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7187 - attribute \src "libresoc.v:145458.3-145480.6" - wire $3\m_load_err_o$next[0:0]$7208 - attribute \src "libresoc.v:145481.3-145503.6" - wire $3\m_store_err_o$next[0:0]$7213 - attribute \src "libresoc.v:145240.3-145267.6" - wire $4\dbus__cyc$next[0:0]$7168 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $4\dbus__sel$next[7:0]$7182 - attribute \src "libresoc.v:145268.3-145295.6" - wire $4\dbus__stb$next[0:0]$7174 - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7188 - attribute \src "libresoc.v:145176.18-145176.116" - wire $and$libresoc.v:145176$7109_Y - attribute \src "libresoc.v:145179.18-145179.111" - wire $and$libresoc.v:145179$7112_Y - attribute \src "libresoc.v:145184.18-145184.116" - wire $and$libresoc.v:145184$7117_Y - attribute \src "libresoc.v:145186.18-145186.111" - wire $and$libresoc.v:145186$7119_Y - attribute \src "libresoc.v:145188.17-145188.114" - wire $and$libresoc.v:145188$7121_Y - attribute \src "libresoc.v:145192.18-145192.116" - wire $and$libresoc.v:145192$7125_Y - attribute \src "libresoc.v:145194.18-145194.111" - wire $and$libresoc.v:145194$7127_Y - attribute \src "libresoc.v:145200.18-145200.116" - wire $and$libresoc.v:145200$7133_Y - attribute \src "libresoc.v:145202.18-145202.111" - wire $and$libresoc.v:145202$7135_Y - attribute \src "libresoc.v:145204.18-145204.116" - wire $and$libresoc.v:145204$7137_Y - attribute \src "libresoc.v:145206.18-145206.111" - wire $and$libresoc.v:145206$7139_Y - attribute \src "libresoc.v:145208.18-145208.116" - wire $and$libresoc.v:145208$7141_Y - attribute \src "libresoc.v:145210.17-145210.108" - wire $and$libresoc.v:145210$7143_Y - attribute \src "libresoc.v:145211.18-145211.111" - wire $and$libresoc.v:145211$7144_Y - attribute \src "libresoc.v:145212.18-145212.120" - wire $and$libresoc.v:145212$7145_Y - attribute \src "libresoc.v:145215.18-145215.120" - wire $and$libresoc.v:145215$7148_Y - attribute \src "libresoc.v:145217.18-145217.120" - wire $and$libresoc.v:145217$7150_Y - attribute \src "libresoc.v:145173.18-145173.110" - wire $not$libresoc.v:145173$7106_Y - attribute \src "libresoc.v:145178.18-145178.110" - wire $not$libresoc.v:145178$7111_Y - attribute \src "libresoc.v:145181.18-145181.110" - wire $not$libresoc.v:145181$7114_Y - attribute \src "libresoc.v:145185.18-145185.110" - wire $not$libresoc.v:145185$7118_Y - attribute \src "libresoc.v:145189.18-145189.110" - wire $not$libresoc.v:145189$7122_Y - attribute \src "libresoc.v:145193.18-145193.110" - wire $not$libresoc.v:145193$7126_Y - attribute \src "libresoc.v:145196.18-145196.110" - wire $not$libresoc.v:145196$7129_Y - attribute \src "libresoc.v:145199.17-145199.109" - wire $not$libresoc.v:145199$7132_Y - attribute \src "libresoc.v:145201.18-145201.110" - wire $not$libresoc.v:145201$7134_Y - attribute \src "libresoc.v:145205.18-145205.110" - wire $not$libresoc.v:145205$7138_Y - attribute \src "libresoc.v:145209.18-145209.110" - wire $not$libresoc.v:145209$7142_Y - attribute \src "libresoc.v:145213.18-145213.110" - wire $not$libresoc.v:145213$7146_Y - attribute \src "libresoc.v:145214.18-145214.109" - wire $not$libresoc.v:145214$7147_Y - attribute \src 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$or$libresoc.v:145191$7124_Y - attribute \src "libresoc.v:145195.18-145195.120" - wire $or$libresoc.v:145195$7128_Y - attribute \src "libresoc.v:145197.18-145197.111" - wire $or$libresoc.v:145197$7130_Y - attribute \src "libresoc.v:145198.18-145198.114" - wire $or$libresoc.v:145198$7131_Y - attribute \src "libresoc.v:145203.18-145203.114" - wire $or$libresoc.v:145203$7136_Y - attribute \src "libresoc.v:145207.18-145207.114" - wire $or$libresoc.v:145207$7140_Y - attribute \src "libresoc.v:145219.18-145219.127" - wire $or$libresoc.v:145219$7152_Y + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7234 + attribute \src "libresoc.v:147090.3-147112.6" + wire $2\m_load_err_o$next[0:0]$7255 + attribute \src "libresoc.v:147113.3-147135.6" + wire $2\m_store_err_o$next[0:0]$7260 + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $3\dbus__adr$next[44:0]$7241 + attribute \src "libresoc.v:146872.3-146899.6" + wire $3\dbus__cyc$next[0:0]$7215 + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7251 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $3\dbus__sel$next[7:0]$7229 + attribute \src "libresoc.v:146900.3-146927.6" + wire $3\dbus__stb$next[0:0]$7221 + attribute \src "libresoc.v:147038.3-147063.6" + wire $3\dbus__we$next[0:0]$7246 + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7266 + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7235 + attribute \src "libresoc.v:147090.3-147112.6" + wire $3\m_load_err_o$next[0:0]$7256 + attribute \src "libresoc.v:147113.3-147135.6" + wire $3\m_store_err_o$next[0:0]$7261 + attribute \src "libresoc.v:146872.3-146899.6" + wire $4\dbus__cyc$next[0:0]$7216 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $4\dbus__sel$next[7:0]$7230 + attribute \src "libresoc.v:146900.3-146927.6" + wire $4\dbus__stb$next[0:0]$7222 + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7236 + attribute \src "libresoc.v:146808.18-146808.116" + wire $and$libresoc.v:146808$7157_Y + attribute \src "libresoc.v:146811.18-146811.111" + wire $and$libresoc.v:146811$7160_Y + attribute \src "libresoc.v:146816.18-146816.116" + wire $and$libresoc.v:146816$7165_Y + attribute \src "libresoc.v:146818.18-146818.111" + wire $and$libresoc.v:146818$7167_Y + attribute \src "libresoc.v:146820.17-146820.114" + wire $and$libresoc.v:146820$7169_Y + attribute \src "libresoc.v:146824.18-146824.116" + wire $and$libresoc.v:146824$7173_Y + attribute \src "libresoc.v:146826.18-146826.111" + wire $and$libresoc.v:146826$7175_Y + attribute \src "libresoc.v:146832.18-146832.116" + wire $and$libresoc.v:146832$7181_Y + attribute \src "libresoc.v:146834.18-146834.111" + wire $and$libresoc.v:146834$7183_Y + attribute \src "libresoc.v:146836.18-146836.116" + wire $and$libresoc.v:146836$7185_Y + attribute \src "libresoc.v:146838.18-146838.111" + wire $and$libresoc.v:146838$7187_Y + attribute \src "libresoc.v:146840.18-146840.116" + wire $and$libresoc.v:146840$7189_Y + attribute \src "libresoc.v:146842.17-146842.108" + wire $and$libresoc.v:146842$7191_Y + attribute \src "libresoc.v:146843.18-146843.111" + wire $and$libresoc.v:146843$7192_Y + attribute \src "libresoc.v:146844.18-146844.120" + wire $and$libresoc.v:146844$7193_Y + attribute \src "libresoc.v:146847.18-146847.120" + wire $and$libresoc.v:146847$7196_Y + attribute \src "libresoc.v:146849.18-146849.120" + wire $and$libresoc.v:146849$7198_Y + attribute \src "libresoc.v:146805.18-146805.110" + wire $not$libresoc.v:146805$7154_Y + attribute \src "libresoc.v:146810.18-146810.110" + wire $not$libresoc.v:146810$7159_Y + attribute \src "libresoc.v:146813.18-146813.110" + wire $not$libresoc.v:146813$7162_Y + attribute \src "libresoc.v:146817.18-146817.110" + wire $not$libresoc.v:146817$7166_Y + attribute \src "libresoc.v:146821.18-146821.110" + wire $not$libresoc.v:146821$7170_Y + attribute \src "libresoc.v:146825.18-146825.110" + wire $not$libresoc.v:146825$7174_Y + attribute \src "libresoc.v:146828.18-146828.110" + wire $not$libresoc.v:146828$7177_Y + attribute \src "libresoc.v:146831.17-146831.109" + wire $not$libresoc.v:146831$7180_Y + attribute \src "libresoc.v:146833.18-146833.110" + wire $not$libresoc.v:146833$7182_Y + attribute \src "libresoc.v:146837.18-146837.110" + wire $not$libresoc.v:146837$7186_Y + attribute \src "libresoc.v:146841.18-146841.110" + wire $not$libresoc.v:146841$7190_Y + attribute \src "libresoc.v:146845.18-146845.110" + wire $not$libresoc.v:146845$7194_Y + attribute \src "libresoc.v:146846.18-146846.109" + wire $not$libresoc.v:146846$7195_Y + attribute \src "libresoc.v:146848.18-146848.110" + wire $not$libresoc.v:146848$7197_Y + attribute \src "libresoc.v:146850.18-146850.110" + wire $not$libresoc.v:146850$7199_Y + attribute \src "libresoc.v:146804.17-146804.119" + wire $or$libresoc.v:146804$7153_Y + attribute \src "libresoc.v:146806.18-146806.110" + wire $or$libresoc.v:146806$7155_Y + attribute \src "libresoc.v:146807.18-146807.114" + wire $or$libresoc.v:146807$7156_Y + attribute \src "libresoc.v:146809.17-146809.113" + wire $or$libresoc.v:146809$7158_Y + attribute \src "libresoc.v:146812.18-146812.120" + wire $or$libresoc.v:146812$7161_Y + attribute \src "libresoc.v:146814.18-146814.111" + wire $or$libresoc.v:146814$7163_Y + attribute \src "libresoc.v:146815.18-146815.114" + wire $or$libresoc.v:146815$7164_Y + attribute \src "libresoc.v:146819.18-146819.120" + wire $or$libresoc.v:146819$7168_Y + attribute \src "libresoc.v:146822.18-146822.111" + wire $or$libresoc.v:146822$7171_Y + attribute \src "libresoc.v:146823.18-146823.114" + wire $or$libresoc.v:146823$7172_Y + attribute \src "libresoc.v:146827.18-146827.120" + wire $or$libresoc.v:146827$7176_Y + attribute \src "libresoc.v:146829.18-146829.111" + wire $or$libresoc.v:146829$7178_Y + attribute \src "libresoc.v:146830.18-146830.114" + wire $or$libresoc.v:146830$7179_Y + attribute \src "libresoc.v:146835.18-146835.114" + wire $or$libresoc.v:146835$7184_Y + attribute \src "libresoc.v:146839.18-146839.114" + wire $or$libresoc.v:146839$7188_Y + attribute \src "libresoc.v:146851.18-146851.127" + wire $or$libresoc.v:146851$7200_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -303624,9 +306121,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -303658,7 +306155,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:144993.7-144993.15" + attribute \src "libresoc.v:146625.7-146625.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -303701,7 +306198,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145176$7109 + cell $and $and$libresoc.v:146808$7157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303709,10 +306206,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:145176$7109_Y + connect \Y $and$libresoc.v:146808$7157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145179$7112 + cell $and $and$libresoc.v:146811$7160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303720,10 +306217,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:145179$7112_Y + connect \Y $and$libresoc.v:146811$7160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145184$7117 + cell $and $and$libresoc.v:146816$7165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303731,10 +306228,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:145184$7117_Y + connect \Y $and$libresoc.v:146816$7165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145186$7119 + cell $and $and$libresoc.v:146818$7167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303742,10 +306239,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:145186$7119_Y + connect \Y $and$libresoc.v:146818$7167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145188$7121 + cell $and $and$libresoc.v:146820$7169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303753,10 +306250,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:145188$7121_Y + connect \Y $and$libresoc.v:146820$7169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145192$7125 + cell $and $and$libresoc.v:146824$7173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303764,10 +306261,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:145192$7125_Y + connect \Y $and$libresoc.v:146824$7173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145194$7127 + cell $and $and$libresoc.v:146826$7175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303775,10 +306272,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:145194$7127_Y + connect \Y $and$libresoc.v:146826$7175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145200$7133 + cell $and $and$libresoc.v:146832$7181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303786,10 +306283,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:145200$7133_Y + connect \Y $and$libresoc.v:146832$7181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145202$7135 + cell $and $and$libresoc.v:146834$7183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303797,10 +306294,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:145202$7135_Y + connect \Y $and$libresoc.v:146834$7183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145204$7137 + cell $and $and$libresoc.v:146836$7185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303808,10 +306305,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:145204$7137_Y + connect \Y $and$libresoc.v:146836$7185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145206$7139 + cell $and $and$libresoc.v:146838$7187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303819,10 +306316,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:145206$7139_Y + connect \Y $and$libresoc.v:146838$7187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145208$7141 + cell $and $and$libresoc.v:146840$7189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303830,10 +306327,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:145208$7141_Y + connect \Y $and$libresoc.v:146840$7189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145210$7143 + cell $and $and$libresoc.v:146842$7191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303841,10 +306338,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:145210$7143_Y + connect \Y $and$libresoc.v:146842$7191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145211$7144 + cell $and $and$libresoc.v:146843$7192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303852,10 +306349,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:145211$7144_Y + connect \Y $and$libresoc.v:146843$7192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145212$7145 + cell $and $and$libresoc.v:146844$7193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303863,10 +306360,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145212$7145_Y + connect \Y $and$libresoc.v:146844$7193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145215$7148 + cell $and $and$libresoc.v:146847$7196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303874,10 +306371,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145215$7148_Y + connect \Y $and$libresoc.v:146847$7196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145217$7150 + cell $and $and$libresoc.v:146849$7198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303885,130 +306382,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145217$7150_Y + connect \Y $and$libresoc.v:146849$7198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145173$7106 + cell $not $not$libresoc.v:146805$7154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145173$7106_Y + connect \Y $not$libresoc.v:146805$7154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145178$7111 + cell $not $not$libresoc.v:146810$7159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145178$7111_Y + connect \Y $not$libresoc.v:146810$7159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145181$7114 + cell $not $not$libresoc.v:146813$7162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145181$7114_Y + connect \Y $not$libresoc.v:146813$7162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145185$7118 + cell $not $not$libresoc.v:146817$7166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145185$7118_Y + connect \Y $not$libresoc.v:146817$7166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145189$7122 + cell $not $not$libresoc.v:146821$7170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145189$7122_Y + connect \Y $not$libresoc.v:146821$7170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145193$7126 + cell $not $not$libresoc.v:146825$7174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145193$7126_Y + connect \Y $not$libresoc.v:146825$7174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145196$7129 + cell $not $not$libresoc.v:146828$7177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145196$7129_Y + connect \Y $not$libresoc.v:146828$7177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145199$7132 + cell $not $not$libresoc.v:146831$7180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145199$7132_Y + connect \Y $not$libresoc.v:146831$7180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145201$7134 + cell $not $not$libresoc.v:146833$7182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145201$7134_Y + connect \Y $not$libresoc.v:146833$7182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145205$7138 + cell $not $not$libresoc.v:146837$7186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145205$7138_Y + connect \Y $not$libresoc.v:146837$7186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145209$7142 + cell $not $not$libresoc.v:146841$7190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145209$7142_Y + connect \Y $not$libresoc.v:146841$7190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145213$7146 + cell $not $not$libresoc.v:146845$7194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145213$7146_Y + connect \Y $not$libresoc.v:146845$7194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:145214$7147 + cell $not $not$libresoc.v:146846$7195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:145214$7147_Y + connect \Y $not$libresoc.v:146846$7195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145216$7149 + cell $not $not$libresoc.v:146848$7197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145216$7149_Y + connect \Y $not$libresoc.v:146848$7197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145218$7151 + cell $not $not$libresoc.v:146850$7199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145218$7151_Y + connect \Y $not$libresoc.v:146850$7199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145172$7105 + cell $or $or$libresoc.v:146804$7153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304016,10 +306513,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145172$7105_Y + connect \Y $or$libresoc.v:146804$7153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145174$7107 + cell $or $or$libresoc.v:146806$7155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304027,10 +306524,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:145174$7107_Y + connect \Y $or$libresoc.v:146806$7155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145175$7108 + cell $or $or$libresoc.v:146807$7156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304038,10 +306535,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145175$7108_Y + connect \Y $or$libresoc.v:146807$7156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145177$7110 + cell $or $or$libresoc.v:146809$7158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304049,10 +306546,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145177$7110_Y + connect \Y $or$libresoc.v:146809$7158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145180$7113 + cell $or $or$libresoc.v:146812$7161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304060,10 +306557,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145180$7113_Y + connect \Y $or$libresoc.v:146812$7161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145182$7115 + cell $or $or$libresoc.v:146814$7163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304071,10 +306568,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:145182$7115_Y + connect \Y $or$libresoc.v:146814$7163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145183$7116 + cell $or $or$libresoc.v:146815$7164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304082,10 +306579,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145183$7116_Y + connect \Y $or$libresoc.v:146815$7164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145187$7120 + cell $or $or$libresoc.v:146819$7168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304093,10 +306590,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145187$7120_Y + connect \Y $or$libresoc.v:146819$7168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145190$7123 + cell $or $or$libresoc.v:146822$7171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304104,10 +306601,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:145190$7123_Y + connect \Y $or$libresoc.v:146822$7171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145191$7124 + cell $or $or$libresoc.v:146823$7172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304115,10 +306612,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145191$7124_Y + connect \Y $or$libresoc.v:146823$7172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145195$7128 + cell $or $or$libresoc.v:146827$7176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304126,10 +306623,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145195$7128_Y + connect \Y $or$libresoc.v:146827$7176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145197$7130 + cell $or $or$libresoc.v:146829$7178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304137,10 +306634,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:145197$7130_Y + connect \Y $or$libresoc.v:146829$7178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145198$7131 + cell $or $or$libresoc.v:146830$7179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304148,10 +306645,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145198$7131_Y + connect \Y $or$libresoc.v:146830$7179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145203$7136 + cell $or $or$libresoc.v:146835$7184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304159,10 +306656,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145203$7136_Y + connect \Y $or$libresoc.v:146835$7184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145207$7140 + cell $or $or$libresoc.v:146839$7188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304170,10 +306667,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145207$7140_Y + connect \Y $or$libresoc.v:146839$7188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:145219$7152 + cell $or $or$libresoc.v:146851$7200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304181,175 +306678,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:145219$7152_Y + connect \Y $or$libresoc.v:146851$7200_Y end - attribute \src "libresoc.v:144993.7-144993.20" - process $proc$libresoc.v:144993$7219 + attribute \src "libresoc.v:146625.7-146625.20" + process $proc$libresoc.v:146625$7267 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145098.14-145098.42" - process $proc$libresoc.v:145098$7220 + attribute \src "libresoc.v:146730.14-146730.42" + process $proc$libresoc.v:146730$7268 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:145103.7-145103.23" - process $proc$libresoc.v:145103$7221 + attribute \src "libresoc.v:146735.7-146735.23" + process $proc$libresoc.v:146735$7269 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:145110.14-145110.48" - process $proc$libresoc.v:145110$7222 + attribute \src "libresoc.v:146742.14-146742.48" + process $proc$libresoc.v:146742$7270 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:145117.13-145117.30" - process $proc$libresoc.v:145117$7223 + attribute \src "libresoc.v:146749.13-146749.30" + process $proc$libresoc.v:146749$7271 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:145122.7-145122.23" - process $proc$libresoc.v:145122$7224 + attribute \src "libresoc.v:146754.7-146754.23" + process $proc$libresoc.v:146754$7272 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:145127.7-145127.22" - process $proc$libresoc.v:145127$7225 + attribute \src "libresoc.v:146759.7-146759.22" + process $proc$libresoc.v:146759$7273 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:145131.14-145131.44" - process $proc$libresoc.v:145131$7226 + attribute \src "libresoc.v:146763.14-146763.44" + process $proc$libresoc.v:146763$7274 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:145138.14-145138.48" - process $proc$libresoc.v:145138$7227 + attribute \src "libresoc.v:146770.14-146770.48" + process $proc$libresoc.v:146770$7275 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:145142.7-145142.26" - process $proc$libresoc.v:145142$7228 + attribute \src "libresoc.v:146774.7-146774.26" + process $proc$libresoc.v:146774$7276 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:145148.7-145148.27" - process $proc$libresoc.v:145148$7229 + attribute \src "libresoc.v:146780.7-146780.27" + process $proc$libresoc.v:146780$7277 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:145220.3-145221.39" - process $proc$libresoc.v:145220$7153 + attribute \src "libresoc.v:146852.3-146853.39" + process $proc$libresoc.v:146852$7201 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:145222.3-145223.43" - process $proc$libresoc.v:145222$7154 + attribute \src "libresoc.v:146854.3-146855.43" + process $proc$libresoc.v:146854$7202 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:145224.3-145225.41" - process $proc$libresoc.v:145224$7155 + attribute \src "libresoc.v:146856.3-146857.41" + process $proc$libresoc.v:146856$7203 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:145226.3-145227.39" - process $proc$libresoc.v:145226$7156 + attribute \src "libresoc.v:146858.3-146859.39" + process $proc$libresoc.v:146858$7204 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:145228.3-145229.33" - process $proc$libresoc.v:145228$7157 + attribute \src "libresoc.v:146860.3-146861.33" + process $proc$libresoc.v:146860$7205 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:145230.3-145231.35" - process $proc$libresoc.v:145230$7158 + attribute \src "libresoc.v:146862.3-146863.35" + process $proc$libresoc.v:146862$7206 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:145232.3-145233.39" - process $proc$libresoc.v:145232$7159 + attribute \src "libresoc.v:146864.3-146865.39" + process $proc$libresoc.v:146864$7207 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:145234.3-145235.35" - process $proc$libresoc.v:145234$7160 + attribute \src "libresoc.v:146866.3-146867.35" + process $proc$libresoc.v:146866$7208 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:145236.3-145237.35" - process $proc$libresoc.v:145236$7161 + attribute \src "libresoc.v:146868.3-146869.35" + process $proc$libresoc.v:146868$7209 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:145238.3-145239.35" - process $proc$libresoc.v:145238$7162 + attribute \src "libresoc.v:146870.3-146871.35" + process $proc$libresoc.v:146870$7210 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:145240.3-145267.6" - process $proc$libresoc.v:145240$7163 + attribute \src "libresoc.v:146872.3-146899.6" + process $proc$libresoc.v:146872$7211 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$7164 $4\dbus__cyc$next[0:0]$7168 - attribute \src "libresoc.v:145241.5-145241.29" + assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 + attribute \src "libresoc.v:146873.5-146873.29" switch \initial - attribute \src "libresoc.v:145241.9-145241.17" + attribute \src "libresoc.v:146873.9-146873.17" case 1'1 case end @@ -304358,53 +306855,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$7165 $2\dbus__cyc$next[0:0]$7166 + assign $1\dbus__cyc$next[0:0]$7213 $2\dbus__cyc$next[0:0]$7214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$7166 $3\dbus__cyc$next[0:0]$7167 + assign $2\dbus__cyc$next[0:0]$7214 $3\dbus__cyc$next[0:0]$7215 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$7167 1'0 + assign $3\dbus__cyc$next[0:0]$7215 1'0 case - assign $3\dbus__cyc$next[0:0]$7167 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7215 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$7166 1'1 + assign $2\dbus__cyc$next[0:0]$7214 1'1 case - assign $2\dbus__cyc$next[0:0]$7166 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7214 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$7165 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7213 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$7168 1'0 + assign $4\dbus__cyc$next[0:0]$7216 1'0 case - assign $4\dbus__cyc$next[0:0]$7168 $1\dbus__cyc$next[0:0]$7165 + assign $4\dbus__cyc$next[0:0]$7216 $1\dbus__cyc$next[0:0]$7213 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7164 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 end - attribute \src "libresoc.v:145268.3-145295.6" - process $proc$libresoc.v:145268$7169 + attribute \src "libresoc.v:146900.3-146927.6" + process $proc$libresoc.v:146900$7217 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$7170 $4\dbus__stb$next[0:0]$7174 - attribute \src "libresoc.v:145269.5-145269.29" + assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 + attribute \src "libresoc.v:146901.5-146901.29" switch \initial - attribute \src "libresoc.v:145269.9-145269.17" + attribute \src "libresoc.v:146901.9-146901.17" case 1'1 case end @@ -304413,52 +306910,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$7171 $2\dbus__stb$next[0:0]$7172 + assign $1\dbus__stb$next[0:0]$7219 $2\dbus__stb$next[0:0]$7220 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$7172 $3\dbus__stb$next[0:0]$7173 + assign $2\dbus__stb$next[0:0]$7220 $3\dbus__stb$next[0:0]$7221 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$7173 1'0 + assign $3\dbus__stb$next[0:0]$7221 1'0 case - assign $3\dbus__stb$next[0:0]$7173 \dbus__stb + assign $3\dbus__stb$next[0:0]$7221 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$7172 1'1 + assign $2\dbus__stb$next[0:0]$7220 1'1 case - assign $2\dbus__stb$next[0:0]$7172 \dbus__stb + assign $2\dbus__stb$next[0:0]$7220 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$7171 \dbus__stb + assign $1\dbus__stb$next[0:0]$7219 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$7174 1'0 + assign $4\dbus__stb$next[0:0]$7222 1'0 case - assign $4\dbus__stb$next[0:0]$7174 $1\dbus__stb$next[0:0]$7171 + assign $4\dbus__stb$next[0:0]$7222 $1\dbus__stb$next[0:0]$7219 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7170 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 end - attribute \src "libresoc.v:145296.3-145305.6" - process $proc$libresoc.v:145296$7175 + attribute \src "libresoc.v:146928.3-146937.6" + process $proc$libresoc.v:146928$7223 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:145297.5-145297.29" + attribute \src "libresoc.v:146929.5-146929.29" switch \initial - attribute \src "libresoc.v:145297.9-145297.17" + attribute \src "libresoc.v:146929.9-146929.17" case 1'1 case end @@ -304474,14 +306971,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:145306.3-145323.6" - process $proc$libresoc.v:145306$7176 + attribute \src "libresoc.v:146938.3-146955.6" + process $proc$libresoc.v:146938$7224 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:145307.5-145307.29" + attribute \src "libresoc.v:146939.5-146939.29" switch \initial - attribute \src "libresoc.v:145307.9-145307.17" + attribute \src "libresoc.v:146939.9-146939.17" case 1'1 case end @@ -304508,15 +307005,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:145324.3-145354.6" - process $proc$libresoc.v:145324$7177 + attribute \src "libresoc.v:146956.3-146986.6" + process $proc$libresoc.v:146956$7225 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$7178 $4\dbus__sel$next[7:0]$7182 - attribute \src "libresoc.v:145325.5-145325.29" + assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 + attribute \src "libresoc.v:146957.5-146957.29" switch \initial - attribute \src "libresoc.v:145325.9-145325.17" + attribute \src "libresoc.v:146957.9-146957.17" case 1'1 case end @@ -304525,55 +307022,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$7179 $2\dbus__sel$next[7:0]$7180 + assign $1\dbus__sel$next[7:0]$7227 $2\dbus__sel$next[7:0]$7228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$7180 $3\dbus__sel$next[7:0]$7181 + assign $2\dbus__sel$next[7:0]$7228 $3\dbus__sel$next[7:0]$7229 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$7181 8'00000000 + assign $3\dbus__sel$next[7:0]$7229 8'00000000 case - assign $3\dbus__sel$next[7:0]$7181 \dbus__sel + assign $3\dbus__sel$next[7:0]$7229 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$7180 \x_mask_i + assign $2\dbus__sel$next[7:0]$7228 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$7180 8'00000000 + assign $2\dbus__sel$next[7:0]$7228 8'00000000 end case - assign $1\dbus__sel$next[7:0]$7179 \dbus__sel + assign $1\dbus__sel$next[7:0]$7227 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$7182 8'00000000 + assign $4\dbus__sel$next[7:0]$7230 8'00000000 case - assign $4\dbus__sel$next[7:0]$7182 $1\dbus__sel$next[7:0]$7179 + assign $4\dbus__sel$next[7:0]$7230 $1\dbus__sel$next[7:0]$7227 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7178 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 end - attribute \src "libresoc.v:145355.3-145379.6" - process $proc$libresoc.v:145355$7183 + attribute \src "libresoc.v:146987.3-147011.6" + process $proc$libresoc.v:146987$7231 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7184 $4\m_ld_data_o$next[63:0]$7188 - attribute \src "libresoc.v:145356.5-145356.29" + assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 + attribute \src "libresoc.v:146988.5-146988.29" switch \initial - attribute \src "libresoc.v:145356.9-145356.17" + attribute \src "libresoc.v:146988.9-146988.17" case 1'1 case end @@ -304582,49 +307079,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$7185 $2\m_ld_data_o$next[63:0]$7186 + assign $1\m_ld_data_o$next[63:0]$7233 $2\m_ld_data_o$next[63:0]$7234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$7186 $3\m_ld_data_o$next[63:0]$7187 + assign $2\m_ld_data_o$next[63:0]$7234 $3\m_ld_data_o$next[63:0]$7235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$7187 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7235 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$7187 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7235 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7186 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7234 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$7185 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7233 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$7188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7236 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$7188 $1\m_ld_data_o$next[63:0]$7185 + assign $4\m_ld_data_o$next[63:0]$7236 $1\m_ld_data_o$next[63:0]$7233 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7184 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 end - attribute \src "libresoc.v:145380.3-145405.6" - process $proc$libresoc.v:145380$7189 + attribute \src "libresoc.v:147012.3-147037.6" + process $proc$libresoc.v:147012$7237 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$7190 $3\dbus__adr$next[44:0]$7193 - attribute \src "libresoc.v:145381.5-145381.29" + assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 + attribute \src "libresoc.v:147013.5-147013.29" switch \initial - attribute \src "libresoc.v:145381.9-145381.17" + attribute \src "libresoc.v:147013.9-147013.17" case 1'1 case end @@ -304633,45 +307130,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$7191 $2\dbus__adr$next[44:0]$7192 + assign $1\dbus__adr$next[44:0]$7239 $2\dbus__adr$next[44:0]$7240 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$7192 \dbus__adr + assign $2\dbus__adr$next[44:0]$7240 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$7192 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7240 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$7192 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7240 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$7191 \dbus__adr + assign $1\dbus__adr$next[44:0]$7239 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$7193 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7241 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$7193 $1\dbus__adr$next[44:0]$7191 + assign $3\dbus__adr$next[44:0]$7241 $1\dbus__adr$next[44:0]$7239 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7190 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 end - attribute \src "libresoc.v:145406.3-145431.6" - process $proc$libresoc.v:145406$7194 + attribute \src "libresoc.v:147038.3-147063.6" + process $proc$libresoc.v:147038$7242 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$7195 $3\dbus__we$next[0:0]$7198 - attribute \src "libresoc.v:145407.5-145407.29" + assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 + attribute \src "libresoc.v:147039.5-147039.29" switch \initial - attribute \src "libresoc.v:145407.9-145407.17" + attribute \src "libresoc.v:147039.9-147039.17" case 1'1 case end @@ -304680,45 +307177,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$7196 $2\dbus__we$next[0:0]$7197 + assign $1\dbus__we$next[0:0]$7244 $2\dbus__we$next[0:0]$7245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$7197 \dbus__we + assign $2\dbus__we$next[0:0]$7245 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$7197 \x_st_i + assign $2\dbus__we$next[0:0]$7245 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$7197 1'0 + assign $2\dbus__we$next[0:0]$7245 1'0 end case - assign $1\dbus__we$next[0:0]$7196 \dbus__we + assign $1\dbus__we$next[0:0]$7244 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$7198 1'0 + assign $3\dbus__we$next[0:0]$7246 1'0 case - assign $3\dbus__we$next[0:0]$7198 $1\dbus__we$next[0:0]$7196 + assign $3\dbus__we$next[0:0]$7246 $1\dbus__we$next[0:0]$7244 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7195 + update \dbus__we$next $0\dbus__we$next[0:0]$7243 end - attribute \src "libresoc.v:145432.3-145457.6" - process $proc$libresoc.v:145432$7199 + attribute \src "libresoc.v:147064.3-147089.6" + process $proc$libresoc.v:147064$7247 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$7200 $3\dbus__dat_w$next[63:0]$7203 - attribute \src "libresoc.v:145433.5-145433.29" + assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 + attribute \src "libresoc.v:147065.5-147065.29" switch \initial - attribute \src "libresoc.v:145433.9-145433.17" + attribute \src "libresoc.v:147065.9-147065.17" case 1'1 case end @@ -304727,45 +307224,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$7201 $2\dbus__dat_w$next[63:0]$7202 + assign $1\dbus__dat_w$next[63:0]$7249 $2\dbus__dat_w$next[63:0]$7250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7202 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7250 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$7202 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7250 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$7202 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7250 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$7201 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7249 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$7203 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7251 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$7203 $1\dbus__dat_w$next[63:0]$7201 + assign $3\dbus__dat_w$next[63:0]$7251 $1\dbus__dat_w$next[63:0]$7249 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7200 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 end - attribute \src "libresoc.v:145458.3-145480.6" - process $proc$libresoc.v:145458$7204 + attribute \src "libresoc.v:147090.3-147112.6" + process $proc$libresoc.v:147090$7252 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$7205 $3\m_load_err_o$next[0:0]$7208 - attribute \src "libresoc.v:145459.5-145459.29" + assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 + attribute \src "libresoc.v:147091.5-147091.29" switch \initial - attribute \src "libresoc.v:145459.9-145459.17" + attribute \src "libresoc.v:147091.9-147091.17" case 1'1 case end @@ -304774,44 +307271,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$7206 $2\m_load_err_o$next[0:0]$7207 + assign $1\m_load_err_o$next[0:0]$7254 $2\m_load_err_o$next[0:0]$7255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$7207 \$85 + assign $2\m_load_err_o$next[0:0]$7255 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$7207 1'0 + assign $2\m_load_err_o$next[0:0]$7255 1'0 case - assign $2\m_load_err_o$next[0:0]$7207 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7255 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$7206 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7254 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$7208 1'0 + assign $3\m_load_err_o$next[0:0]$7256 1'0 case - assign $3\m_load_err_o$next[0:0]$7208 $1\m_load_err_o$next[0:0]$7206 + assign $3\m_load_err_o$next[0:0]$7256 $1\m_load_err_o$next[0:0]$7254 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7205 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 end - attribute \src "libresoc.v:145481.3-145503.6" - process $proc$libresoc.v:145481$7209 + attribute \src "libresoc.v:147113.3-147135.6" + process $proc$libresoc.v:147113$7257 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7210 $3\m_store_err_o$next[0:0]$7213 - attribute \src "libresoc.v:145482.5-145482.29" + assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 + attribute \src "libresoc.v:147114.5-147114.29" switch \initial - attribute \src "libresoc.v:145482.9-145482.17" + attribute \src "libresoc.v:147114.9-147114.17" case 1'1 case end @@ -304820,44 +307317,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$7211 $2\m_store_err_o$next[0:0]$7212 + assign $1\m_store_err_o$next[0:0]$7259 $2\m_store_err_o$next[0:0]$7260 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$7212 \dbus__we + assign $2\m_store_err_o$next[0:0]$7260 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$7212 1'0 + assign $2\m_store_err_o$next[0:0]$7260 1'0 case - assign $2\m_store_err_o$next[0:0]$7212 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7260 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$7211 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7259 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$7213 1'0 + assign $3\m_store_err_o$next[0:0]$7261 1'0 case - assign $3\m_store_err_o$next[0:0]$7213 $1\m_store_err_o$next[0:0]$7211 + assign $3\m_store_err_o$next[0:0]$7261 $1\m_store_err_o$next[0:0]$7259 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7210 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 end - attribute \src "libresoc.v:145504.3-145523.6" - process $proc$libresoc.v:145504$7214 + attribute \src "libresoc.v:147136.3-147155.6" + process $proc$libresoc.v:147136$7262 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7215 $3\m_badaddr_o$next[44:0]$7218 - attribute \src "libresoc.v:145505.5-145505.29" + assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 + attribute \src "libresoc.v:147137.5-147137.29" switch \initial - attribute \src "libresoc.v:145505.9-145505.17" + attribute \src "libresoc.v:147137.9-147137.17" case 1'1 case end @@ -304866,343 +307363,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$7216 $2\m_badaddr_o$next[44:0]$7217 + assign $1\m_badaddr_o$next[44:0]$7264 $2\m_badaddr_o$next[44:0]$7265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$7217 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7265 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$7217 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7265 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$7216 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7264 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$7218 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7218 $1\m_badaddr_o$next[44:0]$7216 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7215 - end - connect \$9 $or$libresoc.v:145172$7105_Y - connect \$11 $not$libresoc.v:145173$7106_Y - connect \$13 $or$libresoc.v:145174$7107_Y - connect \$15 $or$libresoc.v:145175$7108_Y - connect \$17 $and$libresoc.v:145176$7109_Y - connect \$1 $or$libresoc.v:145177$7110_Y - connect \$19 $not$libresoc.v:145178$7111_Y - connect \$21 $and$libresoc.v:145179$7112_Y - connect \$23 $or$libresoc.v:145180$7113_Y - connect \$25 $not$libresoc.v:145181$7114_Y - connect \$27 $or$libresoc.v:145182$7115_Y - connect \$29 $or$libresoc.v:145183$7116_Y - connect \$31 $and$libresoc.v:145184$7117_Y - connect \$33 $not$libresoc.v:145185$7118_Y - connect \$35 $and$libresoc.v:145186$7119_Y - connect \$37 $or$libresoc.v:145187$7120_Y - connect \$3 $and$libresoc.v:145188$7121_Y - connect \$39 $not$libresoc.v:145189$7122_Y - connect \$41 $or$libresoc.v:145190$7123_Y - connect \$43 $or$libresoc.v:145191$7124_Y - connect \$45 $and$libresoc.v:145192$7125_Y - connect \$47 $not$libresoc.v:145193$7126_Y - connect \$49 $and$libresoc.v:145194$7127_Y - connect \$51 $or$libresoc.v:145195$7128_Y - connect \$53 $not$libresoc.v:145196$7129_Y - connect \$55 $or$libresoc.v:145197$7130_Y - connect \$57 $or$libresoc.v:145198$7131_Y - connect \$5 $not$libresoc.v:145199$7132_Y - connect \$59 $and$libresoc.v:145200$7133_Y - connect \$61 $not$libresoc.v:145201$7134_Y - connect \$63 $and$libresoc.v:145202$7135_Y - connect \$65 $or$libresoc.v:145203$7136_Y - connect \$67 $and$libresoc.v:145204$7137_Y - connect \$69 $not$libresoc.v:145205$7138_Y - connect \$71 $and$libresoc.v:145206$7139_Y - connect \$73 $or$libresoc.v:145207$7140_Y - connect \$75 $and$libresoc.v:145208$7141_Y - connect \$77 $not$libresoc.v:145209$7142_Y - connect \$7 $and$libresoc.v:145210$7143_Y - connect \$79 $and$libresoc.v:145211$7144_Y - connect \$81 $and$libresoc.v:145212$7145_Y - connect \$83 $not$libresoc.v:145213$7146_Y - connect \$85 $not$libresoc.v:145214$7147_Y - connect \$87 $and$libresoc.v:145215$7148_Y - connect \$89 $not$libresoc.v:145216$7149_Y - connect \$91 $and$libresoc.v:145217$7150_Y - connect \$93 $not$libresoc.v:145218$7151_Y - connect \$95 $or$libresoc.v:145219$7152_Y + assign $3\m_badaddr_o$next[44:0]$7266 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7266 $1\m_badaddr_o$next[44:0]$7264 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 + end + connect \$9 $or$libresoc.v:146804$7153_Y + connect \$11 $not$libresoc.v:146805$7154_Y + connect \$13 $or$libresoc.v:146806$7155_Y + connect \$15 $or$libresoc.v:146807$7156_Y + connect \$17 $and$libresoc.v:146808$7157_Y + connect \$1 $or$libresoc.v:146809$7158_Y + connect \$19 $not$libresoc.v:146810$7159_Y + connect \$21 $and$libresoc.v:146811$7160_Y + connect \$23 $or$libresoc.v:146812$7161_Y + connect \$25 $not$libresoc.v:146813$7162_Y + connect \$27 $or$libresoc.v:146814$7163_Y + connect \$29 $or$libresoc.v:146815$7164_Y + connect \$31 $and$libresoc.v:146816$7165_Y + connect \$33 $not$libresoc.v:146817$7166_Y + connect \$35 $and$libresoc.v:146818$7167_Y + connect \$37 $or$libresoc.v:146819$7168_Y + connect \$3 $and$libresoc.v:146820$7169_Y + connect \$39 $not$libresoc.v:146821$7170_Y + connect \$41 $or$libresoc.v:146822$7171_Y + connect \$43 $or$libresoc.v:146823$7172_Y + connect \$45 $and$libresoc.v:146824$7173_Y + connect \$47 $not$libresoc.v:146825$7174_Y + connect \$49 $and$libresoc.v:146826$7175_Y + connect \$51 $or$libresoc.v:146827$7176_Y + connect \$53 $not$libresoc.v:146828$7177_Y + connect \$55 $or$libresoc.v:146829$7178_Y + connect \$57 $or$libresoc.v:146830$7179_Y + connect \$5 $not$libresoc.v:146831$7180_Y + connect \$59 $and$libresoc.v:146832$7181_Y + connect \$61 $not$libresoc.v:146833$7182_Y + connect \$63 $and$libresoc.v:146834$7183_Y + connect \$65 $or$libresoc.v:146835$7184_Y + connect \$67 $and$libresoc.v:146836$7185_Y + connect \$69 $not$libresoc.v:146837$7186_Y + connect \$71 $and$libresoc.v:146838$7187_Y + connect \$73 $or$libresoc.v:146839$7188_Y + connect \$75 $and$libresoc.v:146840$7189_Y + connect \$77 $not$libresoc.v:146841$7190_Y + connect \$7 $and$libresoc.v:146842$7191_Y + connect \$79 $and$libresoc.v:146843$7192_Y + connect \$81 $and$libresoc.v:146844$7193_Y + connect \$83 $not$libresoc.v:146845$7194_Y + connect \$85 $not$libresoc.v:146846$7195_Y + connect \$87 $and$libresoc.v:146847$7196_Y + connect \$89 $not$libresoc.v:146848$7197_Y + connect \$91 $and$libresoc.v:146849$7198_Y + connect \$93 $not$libresoc.v:146850$7199_Y + connect \$95 $or$libresoc.v:146851$7200_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:145530.1-146491.10" +attribute \src "libresoc.v:147162.1-148123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:146443.3-146453.6" + attribute \src "libresoc.v:148075.3-148085.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:146413.3-146422.6" + attribute \src "libresoc.v:148045.3-148054.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:146423.3-146432.6" + attribute \src "libresoc.v:148055.3-148064.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:146433.3-146442.6" + attribute \src "libresoc.v:148065.3-148074.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:146287.3-146300.6" + attribute \src "libresoc.v:147919.3-147932.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:146454.3-146464.6" + attribute \src "libresoc.v:148086.3-148096.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:146465.3-146475.6" + attribute \src "libresoc.v:148097.3-148107.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:146215.3-146229.6" + attribute \src "libresoc.v:147847.3-147861.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:146393.3-146412.6" + attribute \src "libresoc.v:148025.3-148044.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:145531.7-145531.20" + attribute \src "libresoc.v:147163.7-147163.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146053.3-146062.6" + attribute \src "libresoc.v:147685.3-147694.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:146268.3-146286.6" + attribute \src "libresoc.v:147900.3-147918.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:146346.3-146359.6" + attribute \src "libresoc.v:147978.3-147991.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:146382.3-146392.6" + attribute \src "libresoc.v:148014.3-148024.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:146324.3-146334.6" - wire width 2 $0\xer_ca$20[1:0]$7305 - attribute \src "libresoc.v:146335.3-146345.6" + attribute \src "libresoc.v:147956.3-147966.6" + wire width 2 $0\xer_ca$20[1:0]$7353 + attribute \src "libresoc.v:147967.3-147977.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:146360.3-146370.6" + attribute \src "libresoc.v:147992.3-148002.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:146371.3-146381.6" + attribute \src "libresoc.v:148003.3-148013.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:146086.3-146096.6" + attribute \src "libresoc.v:147718.3-147728.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:146476.3-146486.6" + attribute \src "libresoc.v:148108.3-148118.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:146443.3-146453.6" + attribute \src "libresoc.v:148075.3-148085.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:146413.3-146422.6" + attribute \src "libresoc.v:148045.3-148054.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:146423.3-146432.6" + attribute \src "libresoc.v:148055.3-148064.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:146433.3-146442.6" + attribute \src "libresoc.v:148065.3-148074.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:146287.3-146300.6" + attribute \src "libresoc.v:147919.3-147932.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:146454.3-146464.6" + attribute \src "libresoc.v:148086.3-148096.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:146465.3-146475.6" + attribute \src "libresoc.v:148097.3-148107.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:146215.3-146229.6" + attribute \src "libresoc.v:147847.3-147861.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:146393.3-146412.6" + attribute \src "libresoc.v:148025.3-148044.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:146053.3-146062.6" + attribute \src "libresoc.v:147685.3-147694.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:146268.3-146286.6" + attribute \src "libresoc.v:147900.3-147918.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:146346.3-146359.6" + attribute \src "libresoc.v:147978.3-147991.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:146382.3-146392.6" + attribute \src "libresoc.v:148014.3-148024.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:146324.3-146334.6" - wire width 2 $1\xer_ca$20[1:0]$7306 - attribute \src "libresoc.v:146335.3-146345.6" + attribute \src "libresoc.v:147956.3-147966.6" + wire width 2 $1\xer_ca$20[1:0]$7354 + attribute \src "libresoc.v:147967.3-147977.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:146360.3-146370.6" + attribute \src "libresoc.v:147992.3-148002.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:146371.3-146381.6" + attribute \src "libresoc.v:148003.3-148013.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146086.3-146096.6" + attribute \src "libresoc.v:147718.3-147728.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:146476.3-146486.6" + attribute \src "libresoc.v:148108.3-148118.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:146028.18-146028.105" - wire width 67 $add$libresoc.v:146028$7266_Y - attribute \src "libresoc.v:146002.19-146002.107" - wire $and$libresoc.v:146002$7240_Y - attribute \src "libresoc.v:146006.19-146006.107" - wire $and$libresoc.v:146006$7244_Y - attribute \src "libresoc.v:146039.18-146039.106" - wire $and$libresoc.v:146039$7277_Y - attribute \src "libresoc.v:146044.18-146044.106" - wire $and$libresoc.v:146044$7282_Y - attribute \src "libresoc.v:146047.18-146047.106" - wire $and$libresoc.v:146047$7285_Y - attribute \src "libresoc.v:146050.18-146050.106" - wire $and$libresoc.v:146050$7288_Y - attribute \src "libresoc.v:145993.19-145993.118" - wire $eq$libresoc.v:145993$7231_Y - attribute \src "libresoc.v:145994.19-145994.118" - wire $eq$libresoc.v:145994$7232_Y - attribute \src "libresoc.v:145995.19-145995.118" - wire $eq$libresoc.v:145995$7233_Y - attribute \src "libresoc.v:146007.19-146007.109" - wire $eq$libresoc.v:146007$7245_Y - attribute \src "libresoc.v:146008.19-146008.110" - wire $eq$libresoc.v:146008$7246_Y - attribute \src "libresoc.v:146009.19-146009.111" - wire $eq$libresoc.v:146009$7247_Y - attribute \src "libresoc.v:146010.19-146010.111" - wire $eq$libresoc.v:146010$7248_Y - attribute \src "libresoc.v:146011.19-146011.111" - wire $eq$libresoc.v:146011$7249_Y - attribute \src "libresoc.v:146012.19-146012.111" - wire $eq$libresoc.v:146012$7250_Y - attribute \src "libresoc.v:146013.19-146013.111" - wire $eq$libresoc.v:146013$7251_Y - attribute \src "libresoc.v:146014.19-146014.111" - wire $eq$libresoc.v:146014$7252_Y - attribute \src "libresoc.v:146015.18-146015.118" - wire $eq$libresoc.v:146015$7253_Y - attribute \src "libresoc.v:146017.18-146017.118" - wire $eq$libresoc.v:146017$7255_Y - attribute \src "libresoc.v:146018.18-146018.118" - wire $eq$libresoc.v:146018$7256_Y - attribute \src "libresoc.v:146019.18-146019.118" - wire $eq$libresoc.v:146019$7257_Y - attribute \src "libresoc.v:146020.18-146020.118" - wire $eq$libresoc.v:146020$7258_Y - attribute \src "libresoc.v:146022.18-146022.118" - wire $eq$libresoc.v:146022$7260_Y - attribute \src "libresoc.v:146023.18-146023.118" - wire $eq$libresoc.v:146023$7261_Y - attribute \src "libresoc.v:146025.18-146025.118" - wire $eq$libresoc.v:146025$7263_Y - attribute \src "libresoc.v:146026.18-146026.118" - wire $eq$libresoc.v:146026$7264_Y - attribute \src "libresoc.v:146040.18-146040.107" - wire $ne$libresoc.v:146040$7278_Y - attribute \src "libresoc.v:146051.18-146051.107" - wire $ne$libresoc.v:146051$7289_Y - attribute \src "libresoc.v:146001.19-146001.100" - wire $not$libresoc.v:146001$7239_Y - attribute \src "libresoc.v:146005.19-146005.100" - wire $not$libresoc.v:146005$7243_Y - attribute \src "libresoc.v:146016.18-146016.110" - wire $not$libresoc.v:146016$7254_Y - attribute \src "libresoc.v:146029.18-146029.97" - wire width 64 $not$libresoc.v:146029$7267_Y - attribute \src "libresoc.v:146034.18-146034.99" - wire $not$libresoc.v:146034$7272_Y - attribute \src "libresoc.v:146037.18-146037.99" - wire $not$libresoc.v:146037$7275_Y - attribute \src "libresoc.v:146041.18-146041.99" - wire $not$libresoc.v:146041$7279_Y - attribute \src "libresoc.v:146042.18-146042.99" - wire $not$libresoc.v:146042$7280_Y - attribute \src "libresoc.v:146021.18-146021.104" - wire $or$libresoc.v:146021$7259_Y - attribute \src "libresoc.v:146024.18-146024.104" - wire $or$libresoc.v:146024$7262_Y - attribute \src "libresoc.v:146027.18-146027.104" - wire $or$libresoc.v:146027$7265_Y - attribute \src "libresoc.v:146038.18-146038.110" - wire $or$libresoc.v:146038$7276_Y - attribute \src "libresoc.v:146043.18-146043.110" - wire $or$libresoc.v:146043$7281_Y - attribute \src "libresoc.v:146046.18-146046.110" - wire $or$libresoc.v:146046$7284_Y - attribute \src "libresoc.v:146049.18-146049.110" - wire $or$libresoc.v:146049$7287_Y - attribute \src "libresoc.v:145992.18-145992.98" - wire $reduce_or$libresoc.v:145992$7230_Y - attribute \src "libresoc.v:145996.19-145996.99" - wire $reduce_or$libresoc.v:145996$7234_Y - attribute \src "libresoc.v:146033.18-146033.99" - wire $reduce_or$libresoc.v:146033$7271_Y - attribute \src "libresoc.v:146036.18-146036.99" - wire $reduce_or$libresoc.v:146036$7274_Y - attribute \src "libresoc.v:146045.18-146045.121" - wire $ternary$libresoc.v:146045$7283_Y - attribute \src "libresoc.v:146048.18-146048.119" - wire $ternary$libresoc.v:146048$7286_Y - attribute \src "libresoc.v:146052.18-146052.123" - wire $ternary$libresoc.v:146052$7290_Y - attribute \src "libresoc.v:145997.19-145997.111" - wire $xor$libresoc.v:145997$7235_Y - attribute \src "libresoc.v:145998.19-145998.111" - wire $xor$libresoc.v:145998$7236_Y - attribute \src "libresoc.v:145999.19-145999.110" - wire $xor$libresoc.v:145999$7237_Y - attribute \src "libresoc.v:146000.19-146000.110" - wire $xor$libresoc.v:146000$7238_Y - attribute \src "libresoc.v:146003.19-146003.110" - wire $xor$libresoc.v:146003$7241_Y - attribute \src "libresoc.v:146004.19-146004.110" - wire $xor$libresoc.v:146004$7242_Y - attribute \src "libresoc.v:146030.18-146030.111" - wire $xor$libresoc.v:146030$7268_Y - attribute \src "libresoc.v:146031.18-146031.107" - wire $xor$libresoc.v:146031$7269_Y - attribute \src "libresoc.v:146032.18-146032.113" - wire width 32 $xor$libresoc.v:146032$7270_Y - attribute \src "libresoc.v:146035.18-146035.115" - wire width 32 $xor$libresoc.v:146035$7273_Y + attribute \src "libresoc.v:147660.18-147660.105" + wire width 67 $add$libresoc.v:147660$7314_Y + attribute \src "libresoc.v:147634.19-147634.107" + wire $and$libresoc.v:147634$7288_Y + attribute \src "libresoc.v:147638.19-147638.107" + wire $and$libresoc.v:147638$7292_Y + attribute \src "libresoc.v:147671.18-147671.106" + wire $and$libresoc.v:147671$7325_Y + attribute \src "libresoc.v:147676.18-147676.106" + wire $and$libresoc.v:147676$7330_Y + attribute \src "libresoc.v:147679.18-147679.106" + wire $and$libresoc.v:147679$7333_Y + attribute \src "libresoc.v:147682.18-147682.106" + wire $and$libresoc.v:147682$7336_Y + attribute \src "libresoc.v:147625.19-147625.118" + wire $eq$libresoc.v:147625$7279_Y + attribute \src "libresoc.v:147626.19-147626.118" + wire $eq$libresoc.v:147626$7280_Y + attribute \src "libresoc.v:147627.19-147627.118" + wire $eq$libresoc.v:147627$7281_Y + attribute \src "libresoc.v:147639.19-147639.109" + wire $eq$libresoc.v:147639$7293_Y + attribute \src "libresoc.v:147640.19-147640.110" + wire $eq$libresoc.v:147640$7294_Y + attribute \src "libresoc.v:147641.19-147641.111" + wire $eq$libresoc.v:147641$7295_Y + attribute \src "libresoc.v:147642.19-147642.111" + wire $eq$libresoc.v:147642$7296_Y + attribute \src "libresoc.v:147643.19-147643.111" + wire $eq$libresoc.v:147643$7297_Y + attribute \src "libresoc.v:147644.19-147644.111" + wire $eq$libresoc.v:147644$7298_Y + attribute \src "libresoc.v:147645.19-147645.111" + wire $eq$libresoc.v:147645$7299_Y + attribute \src "libresoc.v:147646.19-147646.111" + wire $eq$libresoc.v:147646$7300_Y + attribute \src "libresoc.v:147647.18-147647.118" + wire $eq$libresoc.v:147647$7301_Y + attribute \src "libresoc.v:147649.18-147649.118" + wire $eq$libresoc.v:147649$7303_Y + attribute \src "libresoc.v:147650.18-147650.118" + wire $eq$libresoc.v:147650$7304_Y + attribute \src "libresoc.v:147651.18-147651.118" + wire $eq$libresoc.v:147651$7305_Y + attribute \src "libresoc.v:147652.18-147652.118" + wire $eq$libresoc.v:147652$7306_Y + attribute \src "libresoc.v:147654.18-147654.118" + wire $eq$libresoc.v:147654$7308_Y + attribute \src "libresoc.v:147655.18-147655.118" + wire $eq$libresoc.v:147655$7309_Y + attribute \src "libresoc.v:147657.18-147657.118" + wire $eq$libresoc.v:147657$7311_Y + attribute \src "libresoc.v:147658.18-147658.118" + wire $eq$libresoc.v:147658$7312_Y + attribute \src "libresoc.v:147672.18-147672.107" + wire $ne$libresoc.v:147672$7326_Y + attribute \src "libresoc.v:147683.18-147683.107" + wire $ne$libresoc.v:147683$7337_Y + attribute \src "libresoc.v:147633.19-147633.100" + wire $not$libresoc.v:147633$7287_Y + attribute \src "libresoc.v:147637.19-147637.100" + wire $not$libresoc.v:147637$7291_Y + attribute \src "libresoc.v:147648.18-147648.110" + wire $not$libresoc.v:147648$7302_Y + attribute \src "libresoc.v:147661.18-147661.97" + wire width 64 $not$libresoc.v:147661$7315_Y + attribute \src "libresoc.v:147666.18-147666.99" + wire $not$libresoc.v:147666$7320_Y + attribute \src "libresoc.v:147669.18-147669.99" + wire $not$libresoc.v:147669$7323_Y + attribute \src "libresoc.v:147673.18-147673.99" + wire $not$libresoc.v:147673$7327_Y + attribute \src "libresoc.v:147674.18-147674.99" + wire $not$libresoc.v:147674$7328_Y + attribute \src "libresoc.v:147653.18-147653.104" + wire $or$libresoc.v:147653$7307_Y + attribute \src "libresoc.v:147656.18-147656.104" + wire $or$libresoc.v:147656$7310_Y + attribute \src "libresoc.v:147659.18-147659.104" + wire $or$libresoc.v:147659$7313_Y + attribute \src "libresoc.v:147670.18-147670.110" + wire $or$libresoc.v:147670$7324_Y + attribute \src "libresoc.v:147675.18-147675.110" + wire $or$libresoc.v:147675$7329_Y + attribute \src "libresoc.v:147678.18-147678.110" + wire $or$libresoc.v:147678$7332_Y + attribute \src "libresoc.v:147681.18-147681.110" + wire $or$libresoc.v:147681$7335_Y + attribute \src "libresoc.v:147624.18-147624.98" + wire $reduce_or$libresoc.v:147624$7278_Y + attribute \src "libresoc.v:147628.19-147628.99" + wire $reduce_or$libresoc.v:147628$7282_Y + attribute \src "libresoc.v:147665.18-147665.99" + wire $reduce_or$libresoc.v:147665$7319_Y + attribute \src "libresoc.v:147668.18-147668.99" + wire $reduce_or$libresoc.v:147668$7322_Y + attribute \src "libresoc.v:147677.18-147677.121" + wire $ternary$libresoc.v:147677$7331_Y + attribute \src "libresoc.v:147680.18-147680.119" + wire $ternary$libresoc.v:147680$7334_Y + attribute \src "libresoc.v:147684.18-147684.123" + wire $ternary$libresoc.v:147684$7338_Y + attribute \src "libresoc.v:147629.19-147629.111" + wire $xor$libresoc.v:147629$7283_Y + attribute \src "libresoc.v:147630.19-147630.111" + wire $xor$libresoc.v:147630$7284_Y + attribute \src "libresoc.v:147631.19-147631.110" + wire $xor$libresoc.v:147631$7285_Y + attribute \src "libresoc.v:147632.19-147632.110" + wire $xor$libresoc.v:147632$7286_Y + attribute \src "libresoc.v:147635.19-147635.110" + wire $xor$libresoc.v:147635$7289_Y + attribute \src "libresoc.v:147636.19-147636.110" + wire $xor$libresoc.v:147636$7290_Y + attribute \src "libresoc.v:147662.18-147662.111" + wire $xor$libresoc.v:147662$7316_Y + attribute \src "libresoc.v:147663.18-147663.107" + wire $xor$libresoc.v:147663$7317_Y + attribute \src "libresoc.v:147664.18-147664.113" + wire width 32 $xor$libresoc.v:147664$7318_Y + attribute \src "libresoc.v:147667.18-147667.115" + wire width 32 $xor$libresoc.v:147667$7321_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -305613,7 +308110,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:145531.7-145531.15" + attribute \src "libresoc.v:147163.7-147163.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -305658,7 +308155,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:146028$7266 + cell $add $add$libresoc.v:147660$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -305666,10 +308163,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:146028$7266_Y + connect \Y $add$libresoc.v:147660$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:146002$7240 + cell $and $and$libresoc.v:147634$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305677,10 +308174,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:146002$7240_Y + connect \Y $and$libresoc.v:147634$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:146006$7244 + cell $and $and$libresoc.v:147638$7292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305688,10 +308185,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:146006$7244_Y + connect \Y $and$libresoc.v:147638$7292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146039$7277 + cell $and $and$libresoc.v:147671$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305699,10 +308196,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:146039$7277_Y + connect \Y $and$libresoc.v:147671$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146044$7282 + cell $and $and$libresoc.v:147676$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305710,10 +308207,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:146044$7282_Y + connect \Y $and$libresoc.v:147676$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146047$7285 + cell $and $and$libresoc.v:147679$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305721,10 +308218,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:146047$7285_Y + connect \Y $and$libresoc.v:147679$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146050$7288 + cell $and $and$libresoc.v:147682$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305732,10 +308229,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:146050$7288_Y + connect \Y $and$libresoc.v:147682$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:145993$7231 + cell $eq $eq$libresoc.v:147625$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305743,10 +308240,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:145993$7231_Y + connect \Y $eq$libresoc.v:147625$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:145994$7232 + cell $eq $eq$libresoc.v:147626$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305754,10 +308251,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:145994$7232_Y + connect \Y $eq$libresoc.v:147626$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:145995$7233 + cell $eq $eq$libresoc.v:147627$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305765,10 +308262,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:145995$7233_Y + connect \Y $eq$libresoc.v:147627$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146007$7245 + cell $eq $eq$libresoc.v:147639$7293 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305776,10 +308273,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:146007$7245_Y + connect \Y $eq$libresoc.v:147639$7293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146008$7246 + cell $eq $eq$libresoc.v:147640$7294 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305787,10 +308284,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:146008$7246_Y + connect \Y $eq$libresoc.v:147640$7294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146009$7247 + cell $eq $eq$libresoc.v:147641$7295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305798,10 +308295,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:146009$7247_Y + connect \Y $eq$libresoc.v:147641$7295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146010$7248 + cell $eq $eq$libresoc.v:147642$7296 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305809,10 +308306,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:146010$7248_Y + connect \Y $eq$libresoc.v:147642$7296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146011$7249 + cell $eq $eq$libresoc.v:147643$7297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305820,10 +308317,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:146011$7249_Y + connect \Y $eq$libresoc.v:147643$7297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146012$7250 + cell $eq $eq$libresoc.v:147644$7298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305831,10 +308328,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:146012$7250_Y + connect \Y $eq$libresoc.v:147644$7298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146013$7251 + cell $eq $eq$libresoc.v:147645$7299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305842,10 +308339,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:146013$7251_Y + connect \Y $eq$libresoc.v:147645$7299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146014$7252 + cell $eq $eq$libresoc.v:147646$7300 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305853,10 +308350,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:146014$7252_Y + connect \Y $eq$libresoc.v:147646$7300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:146015$7253 + cell $eq $eq$libresoc.v:147647$7301 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305864,10 +308361,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146015$7253_Y + connect \Y $eq$libresoc.v:147647$7301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:146017$7255 + cell $eq $eq$libresoc.v:147649$7303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305875,10 +308372,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146017$7255_Y + connect \Y $eq$libresoc.v:147649$7303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:146018$7256 + cell $eq $eq$libresoc.v:147650$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305886,10 +308383,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146018$7256_Y + connect \Y $eq$libresoc.v:147650$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146019$7257 + cell $eq $eq$libresoc.v:147651$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305897,10 +308394,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146019$7257_Y + connect \Y $eq$libresoc.v:147651$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146020$7258 + cell $eq $eq$libresoc.v:147652$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305908,10 +308405,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146020$7258_Y + connect \Y $eq$libresoc.v:147652$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146022$7260 + cell $eq $eq$libresoc.v:147654$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305919,10 +308416,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146022$7260_Y + connect \Y $eq$libresoc.v:147654$7308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146023$7261 + cell $eq $eq$libresoc.v:147655$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305930,10 +308427,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146023$7261_Y + connect \Y $eq$libresoc.v:147655$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146025$7263 + cell $eq $eq$libresoc.v:147657$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305941,10 +308438,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146025$7263_Y + connect \Y $eq$libresoc.v:147657$7311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146026$7264 + cell $eq $eq$libresoc.v:147658$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305952,10 +308449,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146026$7264_Y + connect \Y $eq$libresoc.v:147658$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:146040$7278 + cell $ne $ne$libresoc.v:147672$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305963,10 +308460,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:146040$7278_Y + connect \Y $ne$libresoc.v:147672$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:146051$7289 + cell $ne $ne$libresoc.v:147683$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305974,74 +308471,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:146051$7289_Y + connect \Y $ne$libresoc.v:147683$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:146001$7239 + cell $not $not$libresoc.v:147633$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:146001$7239_Y + connect \Y $not$libresoc.v:147633$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:146005$7243 + cell $not $not$libresoc.v:147637$7291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:146005$7243_Y + connect \Y $not$libresoc.v:147637$7291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:146016$7254 + cell $not $not$libresoc.v:147648$7302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:146016$7254_Y + connect \Y $not$libresoc.v:147648$7302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:146029$7267 + cell $not $not$libresoc.v:147661$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:146029$7267_Y + connect \Y $not$libresoc.v:147661$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:146034$7272 + cell $not $not$libresoc.v:147666$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:146034$7272_Y + connect \Y $not$libresoc.v:147666$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:146037$7275 + cell $not $not$libresoc.v:147669$7323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:146037$7275_Y + connect \Y $not$libresoc.v:147669$7323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:146041$7279 + cell $not $not$libresoc.v:147673$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:146041$7279_Y + connect \Y $not$libresoc.v:147673$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:146042$7280 + cell $not $not$libresoc.v:147674$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:146042$7280_Y + connect \Y $not$libresoc.v:147674$7328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146021$7259 + cell $or $or$libresoc.v:147653$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306049,10 +308546,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:146021$7259_Y + connect \Y $or$libresoc.v:147653$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146024$7262 + cell $or $or$libresoc.v:147656$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306060,10 +308557,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:146024$7262_Y + connect \Y $or$libresoc.v:147656$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146027$7265 + cell $or $or$libresoc.v:147659$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306071,10 +308568,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:146027$7265_Y + connect \Y $or$libresoc.v:147659$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146038$7276 + cell $or $or$libresoc.v:147670$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306082,10 +308579,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146038$7276_Y + connect \Y $or$libresoc.v:147670$7324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146043$7281 + cell $or $or$libresoc.v:147675$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306093,10 +308590,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146043$7281_Y + connect \Y $or$libresoc.v:147675$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146046$7284 + cell $or $or$libresoc.v:147678$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306104,10 +308601,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146046$7284_Y + connect \Y $or$libresoc.v:147678$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146049$7287 + cell $or $or$libresoc.v:147681$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306115,66 +308612,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146049$7287_Y + connect \Y $or$libresoc.v:147681$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:145992$7230 + cell $reduce_or $reduce_or$libresoc.v:147624$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:145992$7230_Y + connect \Y $reduce_or$libresoc.v:147624$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:145996$7234 + cell $reduce_or $reduce_or$libresoc.v:147628$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:145996$7234_Y + connect \Y $reduce_or$libresoc.v:147628$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:146033$7271 + cell $reduce_or $reduce_or$libresoc.v:147665$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:146033$7271_Y + connect \Y $reduce_or$libresoc.v:147665$7319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:146036$7274 + cell $reduce_or $reduce_or$libresoc.v:147668$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:146036$7274_Y + connect \Y $reduce_or$libresoc.v:147668$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:146045$7283 + cell $mux $ternary$libresoc.v:147677$7331 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:146045$7283_Y + connect \Y $ternary$libresoc.v:147677$7331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:146048$7286 + cell $mux $ternary$libresoc.v:147680$7334 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:146048$7286_Y + connect \Y $ternary$libresoc.v:147680$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:146052$7290 + cell $mux $ternary$libresoc.v:147684$7338 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:146052$7290_Y + connect \Y $ternary$libresoc.v:147684$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:145997$7235 + cell $xor $xor$libresoc.v:147629$7283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306182,10 +308679,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:145997$7235_Y + connect \Y $xor$libresoc.v:147629$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:145998$7236 + cell $xor $xor$libresoc.v:147630$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306193,10 +308690,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:145998$7236_Y + connect \Y $xor$libresoc.v:147630$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:145999$7237 + cell $xor $xor$libresoc.v:147631$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306204,10 +308701,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:145999$7237_Y + connect \Y $xor$libresoc.v:147631$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146000$7238 + cell $xor $xor$libresoc.v:147632$7286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306215,10 +308712,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:146000$7238_Y + connect \Y $xor$libresoc.v:147632$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146003$7241 + cell $xor $xor$libresoc.v:147635$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306226,10 +308723,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:146003$7241_Y + connect \Y $xor$libresoc.v:147635$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146004$7242 + cell $xor $xor$libresoc.v:147636$7290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306237,10 +308734,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:146004$7242_Y + connect \Y $xor$libresoc.v:147636$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:146030$7268 + cell $xor $xor$libresoc.v:147662$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306248,10 +308745,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:146030$7268_Y + connect \Y $xor$libresoc.v:147662$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:146031$7269 + cell $xor $xor$libresoc.v:147663$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306259,10 +308756,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:146031$7269_Y + connect \Y $xor$libresoc.v:147663$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:146032$7270 + cell $xor $xor$libresoc.v:147664$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -306270,10 +308767,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:146032$7270_Y + connect \Y $xor$libresoc.v:147664$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:146035$7273 + cell $xor $xor$libresoc.v:147667$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -306281,24 +308778,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:146035$7273_Y + connect \Y $xor$libresoc.v:147667$7321_Y end - attribute \src "libresoc.v:145531.7-145531.20" - process $proc$libresoc.v:145531$7320 + attribute \src "libresoc.v:147163.7-147163.20" + process $proc$libresoc.v:147163$7368 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146053.3-146062.6" - process $proc$libresoc.v:146053$7291 + attribute \src "libresoc.v:147685.3-147694.6" + process $proc$libresoc.v:147685$7339 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:146054.5-146054.29" + attribute \src "libresoc.v:147686.5-147686.29" switch \initial - attribute \src "libresoc.v:146054.9-146054.17" + attribute \src "libresoc.v:147686.9-147686.17" case 1'1 case end @@ -306314,13 +308811,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:146063.3-146085.6" - process $proc$libresoc.v:146063$7292 + attribute \src "libresoc.v:147695.3-147717.6" + process $proc$libresoc.v:147695$7340 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:146064.5-146064.29" + attribute \src "libresoc.v:147696.5-147696.29" switch \initial - attribute \src "libresoc.v:146064.9-146064.17" + attribute \src "libresoc.v:147696.9-147696.17" case 1'1 case end @@ -306353,14 +308850,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:146086.3-146096.6" - process $proc$libresoc.v:146086$7293 + attribute \src "libresoc.v:147718.3-147728.6" + process $proc$libresoc.v:147718$7341 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:146087.5-146087.29" + attribute \src "libresoc.v:147719.5-147719.29" switch \initial - attribute \src "libresoc.v:146087.9-146087.17" + attribute \src "libresoc.v:147719.9-147719.17" case 1'1 case end @@ -306376,14 +308873,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:146097.3-146123.6" - process $proc$libresoc.v:146097$7294 + attribute \src "libresoc.v:147729.3-147755.6" + process $proc$libresoc.v:147729$7342 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:146098.5-146098.29" + attribute \src "libresoc.v:147730.5-147730.29" switch \initial - attribute \src "libresoc.v:146098.9-146098.17" + attribute \src "libresoc.v:147730.9-147730.17" case 1'1 case end @@ -306421,14 +308918,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:146124.3-146142.6" - process $proc$libresoc.v:146124$7295 + attribute \src "libresoc.v:147756.3-147774.6" + process $proc$libresoc.v:147756$7343 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:146125.5-146125.29" + attribute \src "libresoc.v:147757.5-147757.29" switch \initial - attribute \src "libresoc.v:146125.9-146125.17" + attribute \src "libresoc.v:147757.9-147757.17" case 1'1 case end @@ -306454,14 +308951,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:146143.3-146161.6" - process $proc$libresoc.v:146143$7296 + attribute \src "libresoc.v:147775.3-147793.6" + process $proc$libresoc.v:147775$7344 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:146144.5-146144.29" + attribute \src "libresoc.v:147776.5-147776.29" switch \initial - attribute \src "libresoc.v:146144.9-146144.17" + attribute \src "libresoc.v:147776.9-147776.17" case 1'1 case end @@ -306487,14 +308984,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:146162.3-146188.6" - process $proc$libresoc.v:146162$7297 + attribute \src "libresoc.v:147794.3-147820.6" + process $proc$libresoc.v:147794$7345 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:146163.5-146163.29" + attribute \src "libresoc.v:147795.5-147795.29" switch \initial - attribute \src "libresoc.v:146163.9-146163.17" + attribute \src "libresoc.v:147795.9-147795.17" case 1'1 case end @@ -306530,14 +309027,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:146189.3-146214.6" - process $proc$libresoc.v:146189$7298 + attribute \src "libresoc.v:147821.3-147846.6" + process $proc$libresoc.v:147821$7346 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:146190.5-146190.29" + attribute \src "libresoc.v:147822.5-147822.29" switch \initial - attribute \src "libresoc.v:146190.9-146190.17" + attribute \src "libresoc.v:147822.9-147822.17" case 1'1 case end @@ -306569,14 +309066,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:146215.3-146229.6" - process $proc$libresoc.v:146215$7299 + attribute \src "libresoc.v:147847.3-147861.6" + process $proc$libresoc.v:147847$7347 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:146216.5-146216.29" + attribute \src "libresoc.v:147848.5-147848.29" switch \initial - attribute \src "libresoc.v:146216.9-146216.17" + attribute \src "libresoc.v:147848.9-147848.17" case 1'1 case end @@ -306596,14 +309093,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:146230.3-146267.6" - process $proc$libresoc.v:146230$7300 + attribute \src "libresoc.v:147862.3-147899.6" + process $proc$libresoc.v:147862$7348 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:146231.5-146231.29" + attribute \src "libresoc.v:147863.5-147863.29" switch \initial - attribute \src "libresoc.v:146231.9-146231.17" + attribute \src "libresoc.v:147863.9-147863.17" case 1'1 case end @@ -306656,14 +309153,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:146268.3-146286.6" - process $proc$libresoc.v:146268$7301 + attribute \src "libresoc.v:147900.3-147918.6" + process $proc$libresoc.v:147900$7349 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:146269.5-146269.29" + attribute \src "libresoc.v:147901.5-147901.29" switch \initial - attribute \src "libresoc.v:146269.9-146269.17" + attribute \src "libresoc.v:147901.9-147901.17" case 1'1 case end @@ -306687,14 +309184,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:146287.3-146300.6" - process $proc$libresoc.v:146287$7302 + attribute \src "libresoc.v:147919.3-147932.6" + process $proc$libresoc.v:147919$7350 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:146288.5-146288.29" + attribute \src "libresoc.v:147920.5-147920.29" switch \initial - attribute \src "libresoc.v:146288.9-146288.17" + attribute \src "libresoc.v:147920.9-147920.17" case 1'1 case end @@ -306711,13 +309208,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:146301.3-146323.6" - process $proc$libresoc.v:146301$7303 + attribute \src "libresoc.v:147933.3-147955.6" + process $proc$libresoc.v:147933$7351 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:146302.5-146302.29" + attribute \src "libresoc.v:147934.5-147934.29" switch \initial - attribute \src "libresoc.v:146302.9-146302.17" + attribute \src "libresoc.v:147934.9-147934.17" case 1'1 case end @@ -306750,14 +309247,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:146324.3-146334.6" - process $proc$libresoc.v:146324$7304 + attribute \src "libresoc.v:147956.3-147966.6" + process $proc$libresoc.v:147956$7352 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$7305 $1\xer_ca$20[1:0]$7306 - attribute \src "libresoc.v:146325.5-146325.29" + assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 + attribute \src "libresoc.v:147957.5-147957.29" switch \initial - attribute \src "libresoc.v:146325.9-146325.17" + attribute \src "libresoc.v:147957.9-147957.17" case 1'1 case end @@ -306766,21 +309263,21 @@ module \main attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$7306 \ca + assign $1\xer_ca$20[1:0]$7354 \ca case - assign $1\xer_ca$20[1:0]$7306 2'00 + assign $1\xer_ca$20[1:0]$7354 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7305 + update \xer_ca$20 $0\xer_ca$20[1:0]$7353 end - attribute \src "libresoc.v:146335.3-146345.6" - process $proc$libresoc.v:146335$7307 + attribute \src "libresoc.v:147967.3-147977.6" + process $proc$libresoc.v:147967$7355 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:146336.5-146336.29" + attribute \src "libresoc.v:147968.5-147968.29" switch \initial - attribute \src "libresoc.v:146336.9-146336.17" + attribute \src "libresoc.v:147968.9-147968.17" case 1'1 case end @@ -306796,14 +309293,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:146346.3-146359.6" - process $proc$libresoc.v:146346$7308 + attribute \src "libresoc.v:147978.3-147991.6" + process $proc$libresoc.v:147978$7356 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:146347.5-146347.29" + attribute \src "libresoc.v:147979.5-147979.29" switch \initial - attribute \src "libresoc.v:146347.9-146347.17" + attribute \src "libresoc.v:147979.9-147979.17" case 1'1 case end @@ -306820,14 +309317,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:146360.3-146370.6" - process $proc$libresoc.v:146360$7309 + attribute \src "libresoc.v:147992.3-148002.6" + process $proc$libresoc.v:147992$7357 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:146361.5-146361.29" + attribute \src "libresoc.v:147993.5-147993.29" switch \initial - attribute \src "libresoc.v:146361.9-146361.17" + attribute \src "libresoc.v:147993.9-147993.17" case 1'1 case end @@ -306843,14 +309340,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:146371.3-146381.6" - process $proc$libresoc.v:146371$7310 + attribute \src "libresoc.v:148003.3-148013.6" + process $proc$libresoc.v:148003$7358 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146372.5-146372.29" + attribute \src "libresoc.v:148004.5-148004.29" switch \initial - attribute \src "libresoc.v:146372.9-146372.17" + attribute \src "libresoc.v:148004.9-148004.17" case 1'1 case end @@ -306866,14 +309363,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:146382.3-146392.6" - process $proc$libresoc.v:146382$7311 + attribute \src "libresoc.v:148014.3-148024.6" + process $proc$libresoc.v:148014$7359 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:146383.5-146383.29" + attribute \src "libresoc.v:148015.5-148015.29" switch \initial - attribute \src "libresoc.v:146383.9-146383.17" + attribute \src "libresoc.v:148015.9-148015.17" case 1'1 case end @@ -306889,14 +309386,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:146393.3-146412.6" - process $proc$libresoc.v:146393$7312 + attribute \src "libresoc.v:148025.3-148044.6" + process $proc$libresoc.v:148025$7360 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:146394.5-146394.29" + attribute \src "libresoc.v:148026.5-148026.29" switch \initial - attribute \src "libresoc.v:146394.9-146394.17" + attribute \src "libresoc.v:148026.9-148026.17" case 1'1 case end @@ -306919,14 +309416,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:146413.3-146422.6" - process $proc$libresoc.v:146413$7313 + attribute \src "libresoc.v:148045.3-148054.6" + process $proc$libresoc.v:148045$7361 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:146414.5-146414.29" + attribute \src "libresoc.v:148046.5-148046.29" switch \initial - attribute \src "libresoc.v:146414.9-146414.17" + attribute \src "libresoc.v:148046.9-148046.17" case 1'1 case end @@ -306942,14 +309439,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:146423.3-146432.6" - process $proc$libresoc.v:146423$7314 + attribute \src "libresoc.v:148055.3-148064.6" + process $proc$libresoc.v:148055$7362 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:146424.5-146424.29" + attribute \src "libresoc.v:148056.5-148056.29" switch \initial - attribute \src "libresoc.v:146424.9-146424.17" + attribute \src "libresoc.v:148056.9-148056.17" case 1'1 case end @@ -306965,14 +309462,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:146433.3-146442.6" - process $proc$libresoc.v:146433$7315 + attribute \src "libresoc.v:148065.3-148074.6" + process $proc$libresoc.v:148065$7363 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:146434.5-146434.29" + attribute \src "libresoc.v:148066.5-148066.29" switch \initial - attribute \src "libresoc.v:146434.9-146434.17" + attribute \src "libresoc.v:148066.9-148066.17" case 1'1 case end @@ -306988,14 +309485,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:146443.3-146453.6" - process $proc$libresoc.v:146443$7316 + attribute \src "libresoc.v:148075.3-148085.6" + process $proc$libresoc.v:148075$7364 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:146444.5-146444.29" + attribute \src "libresoc.v:148076.5-148076.29" switch \initial - attribute \src "libresoc.v:146444.9-146444.17" + attribute \src "libresoc.v:148076.9-148076.17" case 1'1 case end @@ -307011,14 +309508,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:146454.3-146464.6" - process $proc$libresoc.v:146454$7317 + attribute \src "libresoc.v:148086.3-148096.6" + process $proc$libresoc.v:148086$7365 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:146455.5-146455.29" + attribute \src "libresoc.v:148087.5-148087.29" switch \initial - attribute \src "libresoc.v:146455.9-146455.17" + attribute \src "libresoc.v:148087.9-148087.17" case 1'1 case end @@ -307034,14 +309531,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:146465.3-146475.6" - process $proc$libresoc.v:146465$7318 + attribute \src "libresoc.v:148097.3-148107.6" + process $proc$libresoc.v:148097$7366 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:146466.5-146466.29" + attribute \src "libresoc.v:148098.5-148098.29" switch \initial - attribute \src "libresoc.v:146466.9-146466.17" + attribute \src "libresoc.v:148098.9-148098.17" case 1'1 case end @@ -307057,14 +309554,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:146476.3-146486.6" - process $proc$libresoc.v:146476$7319 + attribute \src "libresoc.v:148108.3-148118.6" + process $proc$libresoc.v:148108$7367 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:146477.5-146477.29" + attribute \src "libresoc.v:148109.5-148109.29" switch \initial - attribute \src "libresoc.v:146477.9-146477.17" + attribute \src "libresoc.v:148109.9-148109.17" case 1'1 case end @@ -307080,88 +309577,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:145992$7230_Y - connect \$101 $eq$libresoc.v:145993$7231_Y - connect \$103 $eq$libresoc.v:145994$7232_Y - connect \$105 $eq$libresoc.v:145995$7233_Y - connect \$107 $reduce_or$libresoc.v:145996$7234_Y - connect \$109 $xor$libresoc.v:145997$7235_Y - connect \$111 $xor$libresoc.v:145998$7236_Y - connect \$113 $xor$libresoc.v:145999$7237_Y - connect \$116 $xor$libresoc.v:146000$7238_Y - connect \$115 $not$libresoc.v:146001$7239_Y - connect \$119 $and$libresoc.v:146002$7240_Y - connect \$121 $xor$libresoc.v:146003$7241_Y - connect \$124 $xor$libresoc.v:146004$7242_Y - connect \$123 $not$libresoc.v:146005$7243_Y - connect \$127 $and$libresoc.v:146006$7244_Y - connect \$129 $eq$libresoc.v:146007$7245_Y - connect \$131 $eq$libresoc.v:146008$7246_Y - connect \$133 $eq$libresoc.v:146009$7247_Y - connect \$135 $eq$libresoc.v:146010$7248_Y - connect \$137 $eq$libresoc.v:146011$7249_Y - connect \$139 $eq$libresoc.v:146012$7250_Y - connect \$141 $eq$libresoc.v:146013$7251_Y - connect \$143 $eq$libresoc.v:146014$7252_Y - connect \$22 $eq$libresoc.v:146015$7253_Y - connect \$24 $not$libresoc.v:146016$7254_Y - connect \$26 $eq$libresoc.v:146017$7255_Y - connect \$28 $eq$libresoc.v:146018$7256_Y - connect \$30 $eq$libresoc.v:146019$7257_Y - connect \$32 $eq$libresoc.v:146020$7258_Y - connect \$34 $or$libresoc.v:146021$7259_Y - connect \$36 $eq$libresoc.v:146022$7260_Y - connect \$38 $eq$libresoc.v:146023$7261_Y - connect \$40 $or$libresoc.v:146024$7262_Y - connect \$42 $eq$libresoc.v:146025$7263_Y - connect \$44 $eq$libresoc.v:146026$7264_Y - connect \$46 $or$libresoc.v:146027$7265_Y - connect \$49 $add$libresoc.v:146028$7266_Y - connect \$51 $not$libresoc.v:146029$7267_Y - connect \$53 $xor$libresoc.v:146030$7268_Y - connect \$55 $xor$libresoc.v:146031$7269_Y - connect \$59 $xor$libresoc.v:146032$7270_Y - connect \$58 $reduce_or$libresoc.v:146033$7271_Y - connect \$57 $not$libresoc.v:146034$7272_Y - connect \$65 $xor$libresoc.v:146035$7273_Y - connect \$64 $reduce_or$libresoc.v:146036$7274_Y - connect \$63 $not$libresoc.v:146037$7275_Y - connect \$69 $or$libresoc.v:146038$7276_Y - connect \$71 $and$libresoc.v:146039$7277_Y - connect \$73 $ne$libresoc.v:146040$7278_Y - connect \$75 $not$libresoc.v:146041$7279_Y - connect \$77 $not$libresoc.v:146042$7280_Y - connect \$79 $or$libresoc.v:146043$7281_Y - connect \$81 $and$libresoc.v:146044$7282_Y - connect \$83 $ternary$libresoc.v:146045$7283_Y - connect \$85 $or$libresoc.v:146046$7284_Y - connect \$87 $and$libresoc.v:146047$7285_Y - connect \$89 $ternary$libresoc.v:146048$7286_Y - connect \$91 $or$libresoc.v:146049$7287_Y - connect \$93 $and$libresoc.v:146050$7288_Y - connect \$95 $ne$libresoc.v:146051$7289_Y - connect \$97 $ternary$libresoc.v:146052$7290_Y + connect \$99 $reduce_or$libresoc.v:147624$7278_Y + connect \$101 $eq$libresoc.v:147625$7279_Y + connect \$103 $eq$libresoc.v:147626$7280_Y + connect \$105 $eq$libresoc.v:147627$7281_Y + connect \$107 $reduce_or$libresoc.v:147628$7282_Y + connect \$109 $xor$libresoc.v:147629$7283_Y + connect \$111 $xor$libresoc.v:147630$7284_Y + connect \$113 $xor$libresoc.v:147631$7285_Y + connect \$116 $xor$libresoc.v:147632$7286_Y + connect \$115 $not$libresoc.v:147633$7287_Y + connect \$119 $and$libresoc.v:147634$7288_Y + connect \$121 $xor$libresoc.v:147635$7289_Y + connect \$124 $xor$libresoc.v:147636$7290_Y + connect \$123 $not$libresoc.v:147637$7291_Y + connect \$127 $and$libresoc.v:147638$7292_Y + connect \$129 $eq$libresoc.v:147639$7293_Y + connect \$131 $eq$libresoc.v:147640$7294_Y + connect \$133 $eq$libresoc.v:147641$7295_Y + connect \$135 $eq$libresoc.v:147642$7296_Y + connect \$137 $eq$libresoc.v:147643$7297_Y + connect \$139 $eq$libresoc.v:147644$7298_Y + connect \$141 $eq$libresoc.v:147645$7299_Y + connect \$143 $eq$libresoc.v:147646$7300_Y + connect \$22 $eq$libresoc.v:147647$7301_Y + connect \$24 $not$libresoc.v:147648$7302_Y + connect \$26 $eq$libresoc.v:147649$7303_Y + connect \$28 $eq$libresoc.v:147650$7304_Y + connect \$30 $eq$libresoc.v:147651$7305_Y + connect \$32 $eq$libresoc.v:147652$7306_Y + connect \$34 $or$libresoc.v:147653$7307_Y + connect \$36 $eq$libresoc.v:147654$7308_Y + connect \$38 $eq$libresoc.v:147655$7309_Y + connect \$40 $or$libresoc.v:147656$7310_Y + connect \$42 $eq$libresoc.v:147657$7311_Y + connect \$44 $eq$libresoc.v:147658$7312_Y + connect \$46 $or$libresoc.v:147659$7313_Y + connect \$49 $add$libresoc.v:147660$7314_Y + connect \$51 $not$libresoc.v:147661$7315_Y + connect \$53 $xor$libresoc.v:147662$7316_Y + connect \$55 $xor$libresoc.v:147663$7317_Y + connect \$59 $xor$libresoc.v:147664$7318_Y + connect \$58 $reduce_or$libresoc.v:147665$7319_Y + connect \$57 $not$libresoc.v:147666$7320_Y + connect \$65 $xor$libresoc.v:147667$7321_Y + connect \$64 $reduce_or$libresoc.v:147668$7322_Y + connect \$63 $not$libresoc.v:147669$7323_Y + connect \$69 $or$libresoc.v:147670$7324_Y + connect \$71 $and$libresoc.v:147671$7325_Y + connect \$73 $ne$libresoc.v:147672$7326_Y + connect \$75 $not$libresoc.v:147673$7327_Y + connect \$77 $not$libresoc.v:147674$7328_Y + connect \$79 $or$libresoc.v:147675$7329_Y + connect \$81 $and$libresoc.v:147676$7330_Y + connect \$83 $ternary$libresoc.v:147677$7331_Y + connect \$85 $or$libresoc.v:147678$7332_Y + connect \$87 $and$libresoc.v:147679$7333_Y + connect \$89 $ternary$libresoc.v:147680$7334_Y + connect \$91 $or$libresoc.v:147681$7335_Y + connect \$93 $and$libresoc.v:147682$7336_Y + connect \$95 $ne$libresoc.v:147683$7337_Y + connect \$97 $ternary$libresoc.v:147684$7338_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:146495.1-146909.10" +attribute \src "libresoc.v:148127.1-148541.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:146496.7-146496.20" + attribute \src "libresoc.v:148128.7-148128.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146861.3-146891.6" + attribute \src "libresoc.v:148493.3-148523.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:146826.3-146860.6" + attribute \src "libresoc.v:148458.3-148492.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:146861.3-146891.6" + attribute \src "libresoc.v:148493.3-148523.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:146826.3-146860.6" + attribute \src "libresoc.v:148458.3-148492.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:146496.7-146496.15" + attribute \src "libresoc.v:148128.7-148128.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -307476,7 +309973,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:146810.11-146825.4" + attribute \src "libresoc.v:148442.11-148457.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -307493,22 +309990,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:146496.7-146496.20" - process $proc$libresoc.v:146496$7323 + attribute \src "libresoc.v:148128.7-148128.20" + process $proc$libresoc.v:148128$7371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146826.3-146860.6" - process $proc$libresoc.v:146826$7321 + attribute \src "libresoc.v:148458.3-148492.6" + process $proc$libresoc.v:148458$7369 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:146827.5-146827.29" + attribute \src "libresoc.v:148459.5-148459.29" switch \initial - attribute \src "libresoc.v:146827.9-146827.17" + attribute \src "libresoc.v:148459.9-148459.17" case 1'1 case end @@ -307540,14 +310037,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:146861.3-146891.6" - process $proc$libresoc.v:146861$7322 + attribute \src "libresoc.v:148493.3-148523.6" + process $proc$libresoc.v:148493$7370 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:146862.5-146862.29" + attribute \src "libresoc.v:148494.5-148494.29" switch \initial - attribute \src "libresoc.v:146862.9-146862.17" + attribute \src "libresoc.v:148494.9-148494.17" case 1'1 case end @@ -307601,109 +310098,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:146913.1-147449.10" +attribute \src "libresoc.v:148545.1-149081.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:147235.3-147246.6" + attribute \src "libresoc.v:148867.3-148878.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:147274.3-147292.6" + attribute \src "libresoc.v:148906.3-148924.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:147328.3-147342.6" + attribute \src "libresoc.v:148960.3-148974.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:147380.3-147392.6" + attribute \src "libresoc.v:149012.3-149024.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:147343.3-147355.6" + attribute \src "libresoc.v:148975.3-148987.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:147427.3-147439.6" + attribute \src "libresoc.v:149059.3-149071.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147393.3-147405.6" - wire width 64 $0\fast1$10[63:0]$7356 - attribute \src "libresoc.v:147293.3-147307.6" + attribute \src "libresoc.v:149025.3-149037.6" + wire width 64 $0\fast1$10[63:0]$7404 + attribute \src "libresoc.v:148925.3-148939.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:147308.3-147317.6" - wire width 64 $0\fast2$11[63:0]$7348 - attribute \src "libresoc.v:147318.3-147327.6" + attribute \src "libresoc.v:148940.3-148949.6" + wire width 64 $0\fast2$11[63:0]$7396 + attribute \src "libresoc.v:148950.3-148959.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:146914.7-146914.20" + attribute \src "libresoc.v:148546.7-148546.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:147235.3-147246.6" + attribute \src "libresoc.v:148867.3-148878.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:147274.3-147292.6" + attribute \src "libresoc.v:148906.3-148924.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:147328.3-147342.6" + attribute \src "libresoc.v:148960.3-148974.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:147380.3-147392.6" + attribute \src "libresoc.v:149012.3-149024.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:147343.3-147355.6" + attribute \src "libresoc.v:148975.3-148987.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:147427.3-147439.6" + attribute \src "libresoc.v:149059.3-149071.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147393.3-147405.6" - wire width 64 $1\fast1$10[63:0]$7357 - attribute \src "libresoc.v:147293.3-147307.6" + attribute \src "libresoc.v:149025.3-149037.6" + wire width 64 $1\fast1$10[63:0]$7405 + attribute \src "libresoc.v:148925.3-148939.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:147308.3-147317.6" - wire width 64 $1\fast2$11[63:0]$7349 - attribute \src "libresoc.v:147318.3-147327.6" + attribute \src "libresoc.v:148940.3-148949.6" + wire width 64 $1\fast2$11[63:0]$7397 + attribute \src "libresoc.v:148950.3-148959.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:147219.18-147219.119" - wire width 65 $add$libresoc.v:147219$7326_Y - attribute \src "libresoc.v:147234.18-147234.113" - wire width 65 $add$libresoc.v:147234$7342_Y - attribute \src "libresoc.v:147226.18-147226.115" - wire $and$libresoc.v:147226$7333_Y - attribute \src "libresoc.v:147227.18-147227.117" - wire $and$libresoc.v:147227$7334_Y - attribute \src "libresoc.v:147233.18-147233.118" - wire $and$libresoc.v:147233$7341_Y - attribute \src "libresoc.v:147217.18-147217.120" - wire $eq$libresoc.v:147217$7324_Y - attribute \src "libresoc.v:147220.18-147220.111" - wire $eq$libresoc.v:147220$7327_Y - attribute \src "libresoc.v:147222.18-147222.111" - wire $eq$libresoc.v:147222$7329_Y - attribute \src "libresoc.v:147223.18-147223.111" - wire $eq$libresoc.v:147223$7330_Y - attribute \src "libresoc.v:147224.18-147224.109" - wire $eq$libresoc.v:147224$7331_Y - attribute \src "libresoc.v:147229.18-147229.98" - wire width 64 $extend$libresoc.v:147229$7336_Y - attribute \src "libresoc.v:147225.18-147225.104" - wire $not$libresoc.v:147225$7332_Y - attribute \src "libresoc.v:147232.18-147232.112" - wire $not$libresoc.v:147232$7340_Y - attribute \src "libresoc.v:147218.18-147218.116" - wire $or$libresoc.v:147218$7325_Y - attribute \src "libresoc.v:147221.18-147221.109" - wire $or$libresoc.v:147221$7328_Y - attribute \src "libresoc.v:147229.18-147229.98" - wire width 64 $pos$libresoc.v:147229$7337_Y - attribute \src "libresoc.v:147230.18-147230.103" - wire $reduce_or$libresoc.v:147230$7338_Y - attribute \src "libresoc.v:147228.18-147228.108" - wire width 65 $sub$libresoc.v:147228$7335_Y - attribute \src "libresoc.v:147231.18-147231.108" - wire $xor$libresoc.v:147231$7339_Y + attribute \src "libresoc.v:148851.18-148851.119" + wire width 65 $add$libresoc.v:148851$7374_Y + attribute \src "libresoc.v:148866.18-148866.113" + wire width 65 $add$libresoc.v:148866$7390_Y + attribute \src "libresoc.v:148858.18-148858.115" + wire $and$libresoc.v:148858$7381_Y + attribute \src "libresoc.v:148859.18-148859.117" + wire $and$libresoc.v:148859$7382_Y + attribute \src "libresoc.v:148865.18-148865.118" + wire $and$libresoc.v:148865$7389_Y + attribute \src "libresoc.v:148849.18-148849.120" + wire $eq$libresoc.v:148849$7372_Y + attribute \src "libresoc.v:148852.18-148852.111" + wire $eq$libresoc.v:148852$7375_Y + attribute \src "libresoc.v:148854.18-148854.111" + wire $eq$libresoc.v:148854$7377_Y + attribute \src "libresoc.v:148855.18-148855.111" + wire $eq$libresoc.v:148855$7378_Y + attribute \src "libresoc.v:148856.18-148856.109" + wire $eq$libresoc.v:148856$7379_Y + attribute \src "libresoc.v:148861.18-148861.98" + wire width 64 $extend$libresoc.v:148861$7384_Y + attribute \src "libresoc.v:148857.18-148857.104" + wire $not$libresoc.v:148857$7380_Y + attribute \src "libresoc.v:148864.18-148864.112" + wire $not$libresoc.v:148864$7388_Y + attribute \src "libresoc.v:148850.18-148850.116" + wire $or$libresoc.v:148850$7373_Y + attribute \src "libresoc.v:148853.18-148853.109" + wire $or$libresoc.v:148853$7376_Y + attribute \src "libresoc.v:148861.18-148861.98" + wire width 64 $pos$libresoc.v:148861$7385_Y + attribute \src "libresoc.v:148862.18-148862.103" + wire $reduce_or$libresoc.v:148862$7386_Y + attribute \src "libresoc.v:148860.18-148860.108" + wire width 65 $sub$libresoc.v:148860$7383_Y + attribute \src "libresoc.v:148863.18-148863.108" + wire $xor$libresoc.v:148863$7387_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -307994,7 +310491,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:146914.7-146914.15" + attribute \src "libresoc.v:148546.7-148546.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -308005,7 +310502,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:147219$7326 + cell $add $add$libresoc.v:148851$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308013,10 +310510,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:147219$7326_Y + connect \Y $add$libresoc.v:148851$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:147234$7342 + cell $add $add$libresoc.v:148866$7390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308024,10 +310521,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:147234$7342_Y + connect \Y $add$libresoc.v:148866$7390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:147226$7333 + cell $and $and$libresoc.v:148858$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308035,10 +310532,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:147226$7333_Y + connect \Y $and$libresoc.v:148858$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:147227$7334 + cell $and $and$libresoc.v:148859$7382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308046,10 +310543,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:147227$7334_Y + connect \Y $and$libresoc.v:148859$7382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:147233$7341 + cell $and $and$libresoc.v:148865$7389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308057,10 +310554,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:147233$7341_Y + connect \Y $and$libresoc.v:148865$7389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:147217$7324 + cell $eq $eq$libresoc.v:148849$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308068,10 +310565,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:147217$7324_Y + connect \Y $eq$libresoc.v:148849$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:147220$7327 + cell $eq $eq$libresoc.v:148852$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308079,10 +310576,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:147220$7327_Y + connect \Y $eq$libresoc.v:148852$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:147222$7329 + cell $eq $eq$libresoc.v:148854$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -308090,10 +310587,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:147222$7329_Y + connect \Y $eq$libresoc.v:148854$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:147223$7330 + cell $eq $eq$libresoc.v:148855$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -308101,10 +310598,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:147223$7330_Y + connect \Y $eq$libresoc.v:148855$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:147224$7331 + cell $eq $eq$libresoc.v:148856$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308112,34 +310609,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:147224$7331_Y + connect \Y $eq$libresoc.v:148856$7379_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147229$7336 + cell $pos $extend$libresoc.v:148861$7384 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:147229$7336_Y + connect \Y $extend$libresoc.v:148861$7384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:147225$7332 + cell $not $not$libresoc.v:148857$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:147225$7332_Y + connect \Y $not$libresoc.v:148857$7380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:147232$7340 + cell $not $not$libresoc.v:148864$7388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:147232$7340_Y + connect \Y $not$libresoc.v:148864$7388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:147218$7325 + cell $or $or$libresoc.v:148850$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308147,10 +310644,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:147218$7325_Y + connect \Y $or$libresoc.v:148850$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:147221$7328 + cell $or $or$libresoc.v:148853$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308158,26 +310655,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:147221$7328_Y + connect \Y $or$libresoc.v:148853$7376_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147229$7337 + cell $pos $pos$libresoc.v:148861$7385 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147229$7336_Y - connect \Y $pos$libresoc.v:147229$7337_Y + connect \A $extend$libresoc.v:148861$7384_Y + connect \Y $pos$libresoc.v:148861$7385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:147230$7338 + cell $reduce_or $reduce_or$libresoc.v:148862$7386 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:147230$7338_Y + connect \Y $reduce_or$libresoc.v:148862$7386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:147228$7335 + cell $sub $sub$libresoc.v:148860$7383 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308185,10 +310682,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:147228$7335_Y + connect \Y $sub$libresoc.v:148860$7383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:147231$7339 + cell $xor $xor$libresoc.v:148863$7387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308196,23 +310693,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:147231$7339_Y + connect \Y $xor$libresoc.v:148863$7387_Y end - attribute \src "libresoc.v:146914.7-146914.20" - process $proc$libresoc.v:146914$7360 + attribute \src "libresoc.v:148546.7-148546.20" + process $proc$libresoc.v:148546$7408 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147235.3-147246.6" - process $proc$libresoc.v:147235$7343 + attribute \src "libresoc.v:148867.3-148878.6" + process $proc$libresoc.v:148867$7391 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:147236.5-147236.29" + attribute \src "libresoc.v:148868.5-148868.29" switch \initial - attribute \src "libresoc.v:147236.9-147236.17" + attribute \src "libresoc.v:148868.9-148868.17" case 1'1 case end @@ -308230,14 +310727,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:147247.3-147273.6" - process $proc$libresoc.v:147247$7344 + attribute \src "libresoc.v:148879.3-148905.6" + process $proc$libresoc.v:148879$7392 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:147248.5-147248.29" + attribute \src "libresoc.v:148880.5-148880.29" switch \initial - attribute \src "libresoc.v:147248.9-147248.17" + attribute \src "libresoc.v:148880.9-148880.17" case 1'1 case end @@ -308272,14 +310769,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:147274.3-147292.6" - process $proc$libresoc.v:147274$7345 + attribute \src "libresoc.v:148906.3-148924.6" + process $proc$libresoc.v:148906$7393 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:147275.5-147275.29" + attribute \src "libresoc.v:148907.5-148907.29" switch \initial - attribute \src "libresoc.v:147275.9-147275.17" + attribute \src "libresoc.v:148907.9-148907.17" case 1'1 case end @@ -308303,14 +310800,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:147293.3-147307.6" - process $proc$libresoc.v:147293$7346 + attribute \src "libresoc.v:148925.3-148939.6" + process $proc$libresoc.v:148925$7394 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:147294.5-147294.29" + attribute \src "libresoc.v:148926.5-148926.29" switch \initial - attribute \src "libresoc.v:147294.9-147294.17" + attribute \src "libresoc.v:148926.9-148926.17" case 1'1 case end @@ -308330,14 +310827,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:147308.3-147317.6" - process $proc$libresoc.v:147308$7347 + attribute \src "libresoc.v:148940.3-148949.6" + process $proc$libresoc.v:148940$7395 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7348 $1\fast2$11[63:0]$7349 - attribute \src "libresoc.v:147309.5-147309.29" + assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 + attribute \src "libresoc.v:148941.5-148941.29" switch \initial - attribute \src "libresoc.v:147309.9-147309.17" + attribute \src "libresoc.v:148941.9-148941.17" case 1'1 case end @@ -308346,21 +310843,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7349 \$48 [63:0] + assign $1\fast2$11[63:0]$7397 \$48 [63:0] case - assign $1\fast2$11[63:0]$7349 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7397 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7348 + update \fast2$11 $0\fast2$11[63:0]$7396 end - attribute \src "libresoc.v:147318.3-147327.6" - process $proc$libresoc.v:147318$7350 + attribute \src "libresoc.v:148950.3-148959.6" + process $proc$libresoc.v:148950$7398 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:147319.5-147319.29" + attribute \src "libresoc.v:148951.5-148951.29" switch \initial - attribute \src "libresoc.v:147319.9-147319.17" + attribute \src "libresoc.v:148951.9-148951.17" case 1'1 case end @@ -308376,14 +310873,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:147328.3-147342.6" - process $proc$libresoc.v:147328$7351 + attribute \src "libresoc.v:148960.3-148974.6" + process $proc$libresoc.v:148960$7399 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:147329.5-147329.29" + attribute \src "libresoc.v:148961.5-148961.29" switch \initial - attribute \src "libresoc.v:147329.9-147329.17" + attribute \src "libresoc.v:148961.9-148961.17" case 1'1 case end @@ -308411,14 +310908,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:147343.3-147355.6" - process $proc$libresoc.v:147343$7352 + attribute \src "libresoc.v:148975.3-148987.6" + process $proc$libresoc.v:148975$7400 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:147344.5-147344.29" + attribute \src "libresoc.v:148976.5-148976.29" switch \initial - attribute \src "libresoc.v:147344.9-147344.17" + attribute \src "libresoc.v:148976.9-148976.17" case 1'1 case end @@ -308435,14 +310932,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:147356.3-147379.6" - process $proc$libresoc.v:147356$7353 + attribute \src "libresoc.v:148988.3-149011.6" + process $proc$libresoc.v:148988$7401 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:147357.5-147357.29" + attribute \src "libresoc.v:148989.5-148989.29" switch \initial - attribute \src "libresoc.v:147357.9-147357.17" + attribute \src "libresoc.v:148989.9-148989.17" case 1'1 case end @@ -308477,14 +310974,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:147380.3-147392.6" - process $proc$libresoc.v:147380$7354 + attribute \src "libresoc.v:149012.3-149024.6" + process $proc$libresoc.v:149012$7402 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:147381.5-147381.29" + attribute \src "libresoc.v:149013.5-149013.29" switch \initial - attribute \src "libresoc.v:147381.9-147381.17" + attribute \src "libresoc.v:149013.9-149013.17" case 1'1 case end @@ -308501,14 +310998,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:147393.3-147405.6" - process $proc$libresoc.v:147393$7355 + attribute \src "libresoc.v:149025.3-149037.6" + process $proc$libresoc.v:149025$7403 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7356 $1\fast1$10[63:0]$7357 - attribute \src "libresoc.v:147394.5-147394.29" + assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 + attribute \src "libresoc.v:149026.5-149026.29" switch \initial - attribute \src "libresoc.v:147394.9-147394.17" + attribute \src "libresoc.v:149026.9-149026.17" case 1'1 case end @@ -308516,23 +311013,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7357 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7405 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7357 \ctr_n + assign $1\fast1$10[63:0]$7405 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7356 + update \fast1$10 $0\fast1$10[63:0]$7404 end - attribute \src "libresoc.v:147406.3-147426.6" - process $proc$libresoc.v:147406$7358 + attribute \src "libresoc.v:149038.3-149058.6" + process $proc$libresoc.v:149038$7406 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:147407.5-147407.29" + attribute \src "libresoc.v:149039.5-149039.29" switch \initial - attribute \src "libresoc.v:147407.9-147407.17" + attribute \src "libresoc.v:149039.9-149039.17" case 1'1 case end @@ -308560,14 +311057,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:147427.3-147439.6" - process $proc$libresoc.v:147427$7359 + attribute \src "libresoc.v:149059.3-149071.6" + process $proc$libresoc.v:149059$7407 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147428.5-147428.29" + attribute \src "libresoc.v:149060.5-149060.29" switch \initial - attribute \src "libresoc.v:147428.9-147428.17" + attribute \src "libresoc.v:149060.9-149060.17" case 1'1 case end @@ -308584,24 +311081,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:147217$7324_Y - connect \$14 $or$libresoc.v:147218$7325_Y - connect \$17 $add$libresoc.v:147219$7326_Y - connect \$19 $eq$libresoc.v:147220$7327_Y - connect \$21 $or$libresoc.v:147221$7328_Y - connect \$23 $eq$libresoc.v:147222$7329_Y - connect \$25 $eq$libresoc.v:147223$7330_Y - connect \$27 $eq$libresoc.v:147224$7331_Y - connect \$29 $not$libresoc.v:147225$7332_Y - connect \$31 $and$libresoc.v:147226$7333_Y - connect \$33 $and$libresoc.v:147227$7334_Y - connect \$36 $sub$libresoc.v:147228$7335_Y - connect \$38 $pos$libresoc.v:147229$7337_Y - connect \$40 $reduce_or$libresoc.v:147230$7338_Y - connect \$42 $xor$libresoc.v:147231$7339_Y - connect \$44 $not$libresoc.v:147232$7340_Y - connect \$46 $and$libresoc.v:147233$7341_Y - connect \$49 $add$libresoc.v:147234$7342_Y + connect \$12 $eq$libresoc.v:148849$7372_Y + connect \$14 $or$libresoc.v:148850$7373_Y + connect \$17 $add$libresoc.v:148851$7374_Y + connect \$19 $eq$libresoc.v:148852$7375_Y + connect \$21 $or$libresoc.v:148853$7376_Y + connect \$23 $eq$libresoc.v:148854$7377_Y + connect \$25 $eq$libresoc.v:148855$7378_Y + connect \$27 $eq$libresoc.v:148856$7379_Y + connect \$29 $not$libresoc.v:148857$7380_Y + connect \$31 $and$libresoc.v:148858$7381_Y + connect \$33 $and$libresoc.v:148859$7382_Y + connect \$36 $sub$libresoc.v:148860$7383_Y + connect \$38 $pos$libresoc.v:148861$7385_Y + connect \$40 $reduce_or$libresoc.v:148862$7386_Y + connect \$42 $xor$libresoc.v:148863$7387_Y + connect \$44 $not$libresoc.v:148864$7388_Y + connect \$46 $and$libresoc.v:148865$7389_Y + connect \$49 $add$libresoc.v:148866$7390_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -308612,279 +311109,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:147453.1-148403.10" +attribute \src "libresoc.v:149085.1-150035.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:148368.3-148379.6" + attribute \src "libresoc.v:150000.3-150011.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:147866.3-147877.6" + attribute \src "libresoc.v:149498.3-149509.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:148380.3-148391.6" + attribute \src "libresoc.v:150012.3-150023.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:148149.3-148160.6" + attribute \src "libresoc.v:149781.3-149792.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $0\fast1$11[63:0]$7406 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $0\fast1$11[63:0]$7454 + attribute \src "libresoc.v:149606.3-149637.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $0\fast2$12[63:0]$7411 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $0\fast2$12[63:0]$7459 + attribute \src "libresoc.v:149721.3-149752.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:147454.7-147454.20" + attribute \src "libresoc.v:149086.7-149086.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:148330.3-148348.6" + attribute \src "libresoc.v:149962.3-149980.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148349.3-148367.6" + attribute \src "libresoc.v:149981.3-149999.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$60[0:0]$7425 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$61[0:0]$7426 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$62[0:0]$7427 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$67[0:0]$7428 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$68[0:0]$7429 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$69[0:0]$7430 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$70[0:0]$7431 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal[0:0]$7424 - attribute \src "libresoc.v:148006.3-148088.6" - wire $10\fast2$12[19:19]$7421 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$60[0:0]$7473 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$61[0:0]$7474 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$62[0:0]$7475 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$67[0:0]$7476 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$68[0:0]$7477 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$69[0:0]$7478 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$70[0:0]$7479 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal[0:0]$7472 + attribute \src "libresoc.v:149638.3-149720.6" + wire $10\fast2$12[19:19]$7469 + attribute \src "libresoc.v:149793.3-149961.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $11\msr[15:15] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $12\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $13\msr[60:60] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $14\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $15\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $17\msr[15:15] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:148368.3-148379.6" + attribute \src "libresoc.v:150000.3-150011.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:147866.3-147877.6" + attribute \src "libresoc.v:149498.3-149509.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:148380.3-148391.6" + attribute \src "libresoc.v:150012.3-150023.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:148149.3-148160.6" + attribute \src "libresoc.v:149781.3-149792.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $1\fast1$11[63:0]$7407 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $1\fast1$11[63:0]$7455 + attribute \src "libresoc.v:149606.3-149637.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $1\fast2$12[63:0]$7412 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $1\fast2$12[63:0]$7460 + attribute \src "libresoc.v:149721.3-149752.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:148330.3-148348.6" + attribute \src "libresoc.v:149962.3-149980.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148349.3-148367.6" + attribute \src "libresoc.v:149981.3-149999.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$60[0:0]$7433 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$61[0:0]$7434 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$62[0:0]$7435 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$67[0:0]$7436 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$68[0:0]$7437 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$69[0:0]$7438 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$70[0:0]$7439 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal[0:0]$7432 - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $2\fast1$11[63:0]$7408 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$60[0:0]$7481 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$61[0:0]$7482 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$62[0:0]$7483 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$67[0:0]$7484 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$68[0:0]$7485 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$69[0:0]$7486 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal[0:0]$7480 + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $2\fast1$11[63:0]$7456 + attribute \src "libresoc.v:149606.3-149637.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $2\fast2$12[63:0]$7413 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $2\fast2$12[63:0]$7461 + attribute \src "libresoc.v:149721.3-149752.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$60[0:0]$7441 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$61[0:0]$7442 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$62[0:0]$7443 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$67[0:0]$7444 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$68[0:0]$7445 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$69[0:0]$7446 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$70[0:0]$7447 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal[0:0]$7440 - attribute \src "libresoc.v:148006.3-148088.6" - wire $3\fast2$12[17:17]$7414 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$60[0:0]$7489 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$61[0:0]$7490 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$62[0:0]$7491 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$67[0:0]$7492 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$68[0:0]$7493 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$69[0:0]$7494 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$70[0:0]$7495 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal[0:0]$7488 + attribute \src "libresoc.v:149638.3-149720.6" + wire $3\fast2$12[17:17]$7462 + attribute \src "libresoc.v:149793.3-149961.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$60[0:0]$7449 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$61[0:0]$7450 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$62[0:0]$7451 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$67[0:0]$7452 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$68[0:0]$7453 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$69[0:0]$7454 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$70[0:0]$7455 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal[0:0]$7448 - attribute \src "libresoc.v:148006.3-148088.6" - wire $4\fast2$12[18:18]$7415 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$60[0:0]$7497 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$61[0:0]$7498 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$62[0:0]$7499 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$67[0:0]$7500 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$68[0:0]$7501 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$69[0:0]$7502 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$70[0:0]$7503 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal[0:0]$7496 + attribute \src "libresoc.v:149638.3-149720.6" + wire $4\fast2$12[18:18]$7463 + attribute \src "libresoc.v:149793.3-149961.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:148006.3-148088.6" - wire $5\fast2$12[20:20]$7416 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $5\fast2$12[20:20]$7464 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:148006.3-148088.6" - wire $6\fast2$12[16:16]$7417 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $6\fast2$12[16:16]$7465 + attribute \src "libresoc.v:149793.3-149961.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 2 $7\fast2$12[19:18]$7418 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 2 $7\fast2$12[19:18]$7466 + attribute \src "libresoc.v:149793.3-149961.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:148006.3-148088.6" - wire $8\fast2$12[28:28]$7419 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $8\fast2$12[28:28]$7467 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:148006.3-148088.6" - wire $9\fast2$12[30:30]$7420 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $9\fast2$12[30:30]$7468 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:147842.18-147842.113" - wire width 65 $add$libresoc.v:147842$7377_Y - attribute \src "libresoc.v:147836.18-147836.108" - wire width 5 $and$libresoc.v:147836$7370_Y - attribute \src "libresoc.v:147844.18-147844.118" - wire width 8 $and$libresoc.v:147844$7379_Y - attribute \src "libresoc.v:147846.18-147846.118" - wire width 8 $and$libresoc.v:147846$7381_Y - attribute \src "libresoc.v:147848.18-147848.118" - wire width 8 $and$libresoc.v:147848$7383_Y - attribute \src "libresoc.v:147850.18-147850.119" - wire width 8 $and$libresoc.v:147850$7385_Y - attribute \src "libresoc.v:147852.18-147852.119" - wire width 8 $and$libresoc.v:147852$7387_Y - attribute \src "libresoc.v:147854.18-147854.119" - wire width 8 $and$libresoc.v:147854$7389_Y - attribute \src "libresoc.v:147860.18-147860.106" - wire $and$libresoc.v:147860$7396_Y - attribute \src "libresoc.v:147865.18-147865.106" - wire $and$libresoc.v:147865$7401_Y - attribute \src "libresoc.v:147835.18-147835.100" - wire $eq$libresoc.v:147835$7369_Y - attribute \src "libresoc.v:147843.18-147843.119" - wire $eq$libresoc.v:147843$7378_Y - attribute \src "libresoc.v:147857.18-147857.121" - wire $eq$libresoc.v:147857$7393_Y - attribute \src "libresoc.v:147858.18-147858.121" - wire $eq$libresoc.v:147858$7394_Y - attribute \src "libresoc.v:147859.18-147859.111" - wire $eq$libresoc.v:147859$7395_Y - attribute \src "libresoc.v:147863.18-147863.121" - wire $eq$libresoc.v:147863$7399_Y - attribute \src "libresoc.v:147864.18-147864.114" - wire $eq$libresoc.v:147864$7400_Y - attribute \src "libresoc.v:147829.18-147829.95" - wire width 64 $extend$libresoc.v:147829$7361_Y - attribute \src "libresoc.v:147830.18-147830.95" - wire width 64 $extend$libresoc.v:147830$7363_Y - attribute \src "libresoc.v:147841.18-147841.100" - wire width 64 $extend$libresoc.v:147841$7375_Y - attribute \src "libresoc.v:147856.18-147856.109" - wire width 65 $extend$libresoc.v:147856$7391_Y - attribute \src "libresoc.v:147832.18-147832.121" - wire $gt$libresoc.v:147832$7366_Y - attribute \src "libresoc.v:147834.18-147834.99" - wire $gt$libresoc.v:147834$7368_Y - attribute \src "libresoc.v:147831.18-147831.121" - wire $lt$libresoc.v:147831$7365_Y - attribute \src "libresoc.v:147833.18-147833.99" - wire $lt$libresoc.v:147833$7367_Y - attribute \src "libresoc.v:147861.18-147861.112" - wire $not$libresoc.v:147861$7397_Y - attribute \src "libresoc.v:147862.18-147862.112" - wire $not$libresoc.v:147862$7398_Y - attribute \src "libresoc.v:147839.18-147839.106" - wire $or$libresoc.v:147839$7373_Y - attribute \src "libresoc.v:147829.18-147829.95" - wire width 64 $pos$libresoc.v:147829$7362_Y - attribute \src "libresoc.v:147830.18-147830.95" - wire width 64 $pos$libresoc.v:147830$7364_Y - attribute \src "libresoc.v:147841.18-147841.100" - wire width 64 $pos$libresoc.v:147841$7376_Y - attribute \src "libresoc.v:147856.18-147856.109" - wire width 65 $pos$libresoc.v:147856$7392_Y - attribute \src "libresoc.v:147837.18-147837.100" - wire $reduce_or$libresoc.v:147837$7371_Y - attribute \src "libresoc.v:147838.18-147838.113" - wire $reduce_or$libresoc.v:147838$7372_Y - attribute \src "libresoc.v:147845.18-147845.91" - wire $reduce_or$libresoc.v:147845$7380_Y - attribute \src "libresoc.v:147847.18-147847.91" - wire $reduce_or$libresoc.v:147847$7382_Y - attribute \src "libresoc.v:147849.18-147849.91" - wire $reduce_or$libresoc.v:147849$7384_Y - attribute \src "libresoc.v:147851.18-147851.91" - wire $reduce_or$libresoc.v:147851$7386_Y - attribute \src "libresoc.v:147853.18-147853.91" - wire $reduce_or$libresoc.v:147853$7388_Y - attribute \src "libresoc.v:147855.18-147855.91" - wire $reduce_or$libresoc.v:147855$7390_Y - attribute \src "libresoc.v:147840.18-147840.120" - wire width 20 $sshl$libresoc.v:147840$7374_Y + attribute \src "libresoc.v:149474.18-149474.113" + wire width 65 $add$libresoc.v:149474$7425_Y + attribute \src "libresoc.v:149468.18-149468.108" + wire width 5 $and$libresoc.v:149468$7418_Y + attribute \src "libresoc.v:149476.18-149476.118" + wire width 8 $and$libresoc.v:149476$7427_Y + attribute \src "libresoc.v:149478.18-149478.118" + wire width 8 $and$libresoc.v:149478$7429_Y + attribute \src "libresoc.v:149480.18-149480.118" + wire width 8 $and$libresoc.v:149480$7431_Y + attribute \src "libresoc.v:149482.18-149482.119" + wire width 8 $and$libresoc.v:149482$7433_Y + attribute \src "libresoc.v:149484.18-149484.119" + wire width 8 $and$libresoc.v:149484$7435_Y + attribute \src "libresoc.v:149486.18-149486.119" + wire width 8 $and$libresoc.v:149486$7437_Y + attribute \src "libresoc.v:149492.18-149492.106" + wire $and$libresoc.v:149492$7444_Y + attribute \src "libresoc.v:149497.18-149497.106" + wire $and$libresoc.v:149497$7449_Y + attribute \src "libresoc.v:149467.18-149467.100" + wire $eq$libresoc.v:149467$7417_Y + attribute \src "libresoc.v:149475.18-149475.119" + wire $eq$libresoc.v:149475$7426_Y + attribute \src "libresoc.v:149489.18-149489.121" + wire $eq$libresoc.v:149489$7441_Y + attribute \src "libresoc.v:149490.18-149490.121" + wire $eq$libresoc.v:149490$7442_Y + attribute \src "libresoc.v:149491.18-149491.111" + wire $eq$libresoc.v:149491$7443_Y + attribute \src "libresoc.v:149495.18-149495.121" + wire $eq$libresoc.v:149495$7447_Y + attribute \src "libresoc.v:149496.18-149496.114" + wire $eq$libresoc.v:149496$7448_Y + attribute \src "libresoc.v:149461.18-149461.95" + wire width 64 $extend$libresoc.v:149461$7409_Y + attribute \src "libresoc.v:149462.18-149462.95" + wire width 64 $extend$libresoc.v:149462$7411_Y + attribute \src "libresoc.v:149473.18-149473.100" + wire width 64 $extend$libresoc.v:149473$7423_Y + attribute \src "libresoc.v:149488.18-149488.109" + wire width 65 $extend$libresoc.v:149488$7439_Y + attribute \src "libresoc.v:149464.18-149464.121" + wire $gt$libresoc.v:149464$7414_Y + attribute \src "libresoc.v:149466.18-149466.99" + wire $gt$libresoc.v:149466$7416_Y + attribute \src "libresoc.v:149463.18-149463.121" + wire $lt$libresoc.v:149463$7413_Y + attribute \src "libresoc.v:149465.18-149465.99" + wire $lt$libresoc.v:149465$7415_Y + attribute \src "libresoc.v:149493.18-149493.112" + wire $not$libresoc.v:149493$7445_Y + attribute \src "libresoc.v:149494.18-149494.112" + wire $not$libresoc.v:149494$7446_Y + attribute \src "libresoc.v:149471.18-149471.106" + wire $or$libresoc.v:149471$7421_Y + attribute \src "libresoc.v:149461.18-149461.95" + wire width 64 $pos$libresoc.v:149461$7410_Y + attribute \src "libresoc.v:149462.18-149462.95" + wire width 64 $pos$libresoc.v:149462$7412_Y + attribute \src "libresoc.v:149473.18-149473.100" + wire width 64 $pos$libresoc.v:149473$7424_Y + attribute \src "libresoc.v:149488.18-149488.109" + wire width 65 $pos$libresoc.v:149488$7440_Y + attribute \src "libresoc.v:149469.18-149469.100" + wire $reduce_or$libresoc.v:149469$7419_Y + attribute \src "libresoc.v:149470.18-149470.113" + wire $reduce_or$libresoc.v:149470$7420_Y + attribute \src "libresoc.v:149477.18-149477.91" + wire $reduce_or$libresoc.v:149477$7428_Y + attribute \src "libresoc.v:149479.18-149479.91" + wire $reduce_or$libresoc.v:149479$7430_Y + attribute \src "libresoc.v:149481.18-149481.91" + wire $reduce_or$libresoc.v:149481$7432_Y + attribute \src "libresoc.v:149483.18-149483.91" + wire $reduce_or$libresoc.v:149483$7434_Y + attribute \src "libresoc.v:149485.18-149485.91" + wire $reduce_or$libresoc.v:149485$7436_Y + attribute \src "libresoc.v:149487.18-149487.91" + wire $reduce_or$libresoc.v:149487$7438_Y + attribute \src "libresoc.v:149472.18-149472.120" + wire width 20 $sshl$libresoc.v:149472$7422_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -308987,7 +311484,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:147454.7-147454.15" + attribute \src "libresoc.v:149086.7-149086.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -309252,7 +311749,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:147842$7377 + cell $add $add$libresoc.v:149474$7425 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309260,10 +311757,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:147842$7377_Y + connect \Y $add$libresoc.v:149474$7425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:147836$7370 + cell $and $and$libresoc.v:149468$7418 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -309271,10 +311768,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:147836$7370_Y + connect \Y $and$libresoc.v:149468$7418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:147844$7379 + cell $and $and$libresoc.v:149476$7427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309282,10 +311779,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:147844$7379_Y + connect \Y $and$libresoc.v:149476$7427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:147846$7381 + cell $and $and$libresoc.v:149478$7429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309293,10 +311790,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:147846$7381_Y + connect \Y $and$libresoc.v:149478$7429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:147848$7383 + cell $and $and$libresoc.v:149480$7431 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309304,10 +311801,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:147848$7383_Y + connect \Y $and$libresoc.v:149480$7431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:147850$7385 + cell $and $and$libresoc.v:149482$7433 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309315,10 +311812,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:147850$7385_Y + connect \Y $and$libresoc.v:149482$7433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:147852$7387 + cell $and $and$libresoc.v:149484$7435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309326,10 +311823,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:147852$7387_Y + connect \Y $and$libresoc.v:149484$7435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:147854$7389 + cell $and $and$libresoc.v:149486$7437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309337,10 +311834,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:147854$7389_Y + connect \Y $and$libresoc.v:149486$7437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:147860$7396 + cell $and $and$libresoc.v:149492$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309348,10 +311845,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:147860$7396_Y + connect \Y $and$libresoc.v:149492$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:147865$7401 + cell $and $and$libresoc.v:149497$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309359,10 +311856,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:147865$7401_Y + connect \Y $and$libresoc.v:149497$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:147835$7369 + cell $eq $eq$libresoc.v:149467$7417 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309370,10 +311867,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:147835$7369_Y + connect \Y $eq$libresoc.v:149467$7417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:147843$7378 + cell $eq $eq$libresoc.v:149475$7426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309381,10 +311878,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:147843$7378_Y + connect \Y $eq$libresoc.v:149475$7426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:147857$7393 + cell $eq $eq$libresoc.v:149489$7441 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309392,10 +311889,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:147857$7393_Y + connect \Y $eq$libresoc.v:149489$7441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:147858$7394 + cell $eq $eq$libresoc.v:149490$7442 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309403,10 +311900,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:147858$7394_Y + connect \Y $eq$libresoc.v:149490$7442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:147859$7395 + cell $eq $eq$libresoc.v:149491$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309414,10 +311911,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:147859$7395_Y + connect \Y $eq$libresoc.v:149491$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:147863$7399 + cell $eq $eq$libresoc.v:149495$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309425,10 +311922,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:147863$7399_Y + connect \Y $eq$libresoc.v:149495$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:147864$7400 + cell $eq $eq$libresoc.v:149496$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309436,42 +311933,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:147864$7400_Y + connect \Y $eq$libresoc.v:149496$7448_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147829$7361 + cell $pos $extend$libresoc.v:149461$7409 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:147829$7361_Y + connect \Y $extend$libresoc.v:149461$7409_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147830$7363 + cell $pos $extend$libresoc.v:149462$7411 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:147830$7363_Y + connect \Y $extend$libresoc.v:149462$7411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:147841$7375 + cell $pos $extend$libresoc.v:149473$7423 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:147841$7375_Y + connect \Y $extend$libresoc.v:149473$7423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:147856$7391 + cell $pos $extend$libresoc.v:149488$7439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:147856$7391_Y + connect \Y $extend$libresoc.v:149488$7439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:147832$7366 + cell $gt $gt$libresoc.v:149464$7414 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -309479,10 +311976,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:147832$7366_Y + connect \Y $gt$libresoc.v:149464$7414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:147834$7368 + cell $gt $gt$libresoc.v:149466$7416 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309490,10 +311987,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:147834$7368_Y + connect \Y $gt$libresoc.v:149466$7416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:147831$7365 + cell $lt $lt$libresoc.v:149463$7413 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -309501,10 +311998,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:147831$7365_Y + connect \Y $lt$libresoc.v:149463$7413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:147833$7367 + cell $lt $lt$libresoc.v:149465$7415 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309512,26 +312009,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:147833$7367_Y + connect \Y $lt$libresoc.v:149465$7415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:147861$7397 + cell $not $not$libresoc.v:149493$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:147861$7397_Y + connect \Y $not$libresoc.v:149493$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:147862$7398 + cell $not $not$libresoc.v:149494$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:147862$7398_Y + connect \Y $not$libresoc.v:149494$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:147839$7373 + cell $or $or$libresoc.v:149471$7421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309539,106 +312036,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:147839$7373_Y + connect \Y $or$libresoc.v:149471$7421_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147829$7362 + cell $pos $pos$libresoc.v:149461$7410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147829$7361_Y - connect \Y $pos$libresoc.v:147829$7362_Y + connect \A $extend$libresoc.v:149461$7409_Y + connect \Y $pos$libresoc.v:149461$7410_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147830$7364 + cell $pos $pos$libresoc.v:149462$7412 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147830$7363_Y - connect \Y $pos$libresoc.v:147830$7364_Y + connect \A $extend$libresoc.v:149462$7411_Y + connect \Y $pos$libresoc.v:149462$7412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:147841$7376 + cell $pos $pos$libresoc.v:149473$7424 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147841$7375_Y - connect \Y $pos$libresoc.v:147841$7376_Y + connect \A $extend$libresoc.v:149473$7423_Y + connect \Y $pos$libresoc.v:149473$7424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:147856$7392 + cell $pos $pos$libresoc.v:149488$7440 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147856$7391_Y - connect \Y $pos$libresoc.v:147856$7392_Y + connect \A $extend$libresoc.v:149488$7439_Y + connect \Y $pos$libresoc.v:149488$7440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:147837$7371 + cell $reduce_or $reduce_or$libresoc.v:149469$7419 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:147837$7371_Y + connect \Y $reduce_or$libresoc.v:149469$7419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:147838$7372 + cell $reduce_or $reduce_or$libresoc.v:149470$7420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:147838$7372_Y + connect \Y $reduce_or$libresoc.v:149470$7420_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147845$7380 + cell $reduce_or $reduce_or$libresoc.v:149477$7428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:147845$7380_Y + connect \Y $reduce_or$libresoc.v:149477$7428_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147847$7382 + cell $reduce_or $reduce_or$libresoc.v:149479$7430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:147847$7382_Y + connect \Y $reduce_or$libresoc.v:149479$7430_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147849$7384 + cell $reduce_or $reduce_or$libresoc.v:149481$7432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:147849$7384_Y + connect \Y $reduce_or$libresoc.v:149481$7432_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147851$7386 + cell $reduce_or $reduce_or$libresoc.v:149483$7434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:147851$7386_Y + connect \Y $reduce_or$libresoc.v:149483$7434_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147853$7388 + cell $reduce_or $reduce_or$libresoc.v:149485$7436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:147853$7388_Y + connect \Y $reduce_or$libresoc.v:149485$7436_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147855$7390 + cell $reduce_or $reduce_or$libresoc.v:149487$7438 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:147855$7390_Y + connect \Y $reduce_or$libresoc.v:149487$7438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:147840$7374 + cell $sshl $sshl$libresoc.v:149472$7422 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -309646,23 +312143,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:147840$7374_Y + connect \Y $sshl$libresoc.v:149472$7422_Y end - attribute \src "libresoc.v:147454.7-147454.20" - process $proc$libresoc.v:147454$7462 + attribute \src "libresoc.v:149086.7-149086.20" + process $proc$libresoc.v:149086$7510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147866.3-147877.6" - process $proc$libresoc.v:147866$7402 + attribute \src "libresoc.v:149498.3-149509.6" + process $proc$libresoc.v:149498$7450 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:147867.5-147867.29" + attribute \src "libresoc.v:149499.5-149499.29" switch \initial - attribute \src "libresoc.v:147867.9-147867.17" + attribute \src "libresoc.v:149499.9-149499.17" case 1'1 case end @@ -309680,14 +312177,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:147878.3-147909.6" - process $proc$libresoc.v:147878$7403 + attribute \src "libresoc.v:149510.3-149541.6" + process $proc$libresoc.v:149510$7451 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:147879.5-147879.29" + attribute \src "libresoc.v:149511.5-149511.29" switch \initial - attribute \src "libresoc.v:147879.9-147879.17" + attribute \src "libresoc.v:149511.9-149511.17" case 1'1 case end @@ -309726,14 +312223,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:147910.3-147941.6" - process $proc$libresoc.v:147910$7404 + attribute \src "libresoc.v:149542.3-149573.6" + process $proc$libresoc.v:149542$7452 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:147911.5-147911.29" + attribute \src "libresoc.v:149543.5-149543.29" switch \initial - attribute \src "libresoc.v:147911.9-147911.17" + attribute \src "libresoc.v:149543.9-149543.17" case 1'1 case end @@ -309772,14 +312269,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:147942.3-147973.6" - process $proc$libresoc.v:147942$7405 + attribute \src "libresoc.v:149574.3-149605.6" + process $proc$libresoc.v:149574$7453 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7406 $1\fast1$11[63:0]$7407 - attribute \src "libresoc.v:147943.5-147943.29" + assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 + attribute \src "libresoc.v:149575.5-149575.29" switch \initial - attribute \src "libresoc.v:147943.9-147943.17" + attribute \src "libresoc.v:149575.9-149575.17" case 1'1 case end @@ -309788,43 +312285,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7407 $2\fast1$11[63:0]$7408 + assign $1\fast1$11[63:0]$7455 $2\fast1$11[63:0]$7456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7408 \trap_op__cia + assign $2\fast1$11[63:0]$7456 \trap_op__cia case - assign $2\fast1$11[63:0]$7408 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7407 \$39 [63:0] + assign $1\fast1$11[63:0]$7455 \$39 [63:0] case - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7406 + update \fast1$11 $0\fast1$11[63:0]$7454 end - attribute \src "libresoc.v:147974.3-148005.6" - process $proc$libresoc.v:147974$7409 + attribute \src "libresoc.v:149606.3-149637.6" + process $proc$libresoc.v:149606$7457 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:147975.5-147975.29" + attribute \src "libresoc.v:149607.5-149607.29" switch \initial - attribute \src "libresoc.v:147975.9-147975.17" + attribute \src "libresoc.v:149607.9-149607.17" case 1'1 case end @@ -309862,14 +312359,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:148006.3-148088.6" - process $proc$libresoc.v:148006$7410 + attribute \src "libresoc.v:149638.3-149720.6" + process $proc$libresoc.v:149638$7458 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7411 $1\fast2$12[63:0]$7412 - attribute \src "libresoc.v:148007.5-148007.29" + assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 + attribute \src "libresoc.v:149639.5-149639.29" switch \initial - attribute \src "libresoc.v:148007.9-148007.17" + attribute \src "libresoc.v:149639.9-149639.17" case 1'1 case end @@ -309878,59 +312375,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7412 $2\fast2$12[63:0]$7413 + assign $1\fast2$12[63:0]$7460 $2\fast2$12[63:0]$7461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7413 [29] $2\fast2$12[63:0]$7413 [27] $2\fast2$12[63:0]$7413 [21] } 3'000 - assign $2\fast2$12[63:0]$7413 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7413 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7413 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7413 [17] $3\fast2$12[17:17]$7414 - assign { } { } - assign $2\fast2$12[63:0]$7413 [20] $5\fast2$12[20:20]$7416 - assign $2\fast2$12[63:0]$7413 [16] $6\fast2$12[16:16]$7417 - assign $2\fast2$12[63:0]$7413 [18] $7\fast2$12[19:18]$7418 [0] - assign $2\fast2$12[63:0]$7413 [28] $8\fast2$12[28:28]$7419 - assign $2\fast2$12[63:0]$7413 [30] $9\fast2$12[30:30]$7420 - assign $2\fast2$12[63:0]$7413 [19] $10\fast2$12[19:19]$7421 + assign { $2\fast2$12[63:0]$7461 [29] $2\fast2$12[63:0]$7461 [27] $2\fast2$12[63:0]$7461 [21] } 3'000 + assign $2\fast2$12[63:0]$7461 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7461 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7461 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7461 [17] $3\fast2$12[17:17]$7462 + assign { } { } + assign $2\fast2$12[63:0]$7461 [20] $5\fast2$12[20:20]$7464 + assign $2\fast2$12[63:0]$7461 [16] $6\fast2$12[16:16]$7465 + assign $2\fast2$12[63:0]$7461 [18] $7\fast2$12[19:18]$7466 [0] + assign $2\fast2$12[63:0]$7461 [28] $8\fast2$12[28:28]$7467 + assign $2\fast2$12[63:0]$7461 [30] $9\fast2$12[30:30]$7468 + assign $2\fast2$12[63:0]$7461 [19] $10\fast2$12[19:19]$7469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7414 1'1 + assign $3\fast2$12[17:17]$7462 1'1 case - assign $3\fast2$12[17:17]$7414 1'0 + assign $3\fast2$12[17:17]$7462 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7415 1'1 + assign $4\fast2$12[18:18]$7463 1'1 case - assign $4\fast2$12[18:18]$7415 1'0 + assign $4\fast2$12[18:18]$7463 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7416 1'1 + assign $5\fast2$12[20:20]$7464 1'1 case - assign $5\fast2$12[20:20]$7416 1'0 + assign $5\fast2$12[20:20]$7464 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7417 1'1 + assign $6\fast2$12[16:16]$7465 1'1 case - assign $6\fast2$12[16:16]$7417 1'0 + assign $6\fast2$12[16:16]$7465 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -309939,57 +312436,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7420 \trapexc_$signal - assign $8\fast2$12[28:28]$7419 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7418 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7418 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7468 \trapexc_$signal + assign $8\fast2$12[28:28]$7467 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7466 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7466 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7418 { 1'0 $4\fast2$12[18:18]$7415 } - assign $8\fast2$12[28:28]$7419 1'0 - assign $9\fast2$12[30:30]$7420 1'0 + assign $7\fast2$12[19:18]$7466 { 1'0 $4\fast2$12[18:18]$7463 } + assign $8\fast2$12[28:28]$7467 1'0 + assign $9\fast2$12[30:30]$7468 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7421 1'1 + assign $10\fast2$12[19:19]$7469 1'1 case - assign $10\fast2$12[19:19]$7421 $7\fast2$12[19:18]$7418 [1] + assign $10\fast2$12[19:19]$7469 $7\fast2$12[19:18]$7466 [1] end case - assign $2\fast2$12[63:0]$7413 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7461 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7412 [30:27] $1\fast2$12[63:0]$7412 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7412 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7412 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7412 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7460 [30:27] $1\fast2$12[63:0]$7460 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7460 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7460 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7460 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7411 + update \fast2$12 $0\fast2$12[63:0]$7459 end - attribute \src "libresoc.v:148089.3-148120.6" - process $proc$libresoc.v:148089$7422 + attribute \src "libresoc.v:149721.3-149752.6" + process $proc$libresoc.v:149721$7470 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:148090.5-148090.29" + attribute \src "libresoc.v:149722.5-149722.29" switch \initial - attribute \src "libresoc.v:148090.9-148090.17" + attribute \src "libresoc.v:149722.9-149722.17" case 1'1 case end @@ -310027,8 +312524,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:148121.3-148148.6" - process $proc$libresoc.v:148121$7423 + attribute \src "libresoc.v:149753.3-149780.6" + process $proc$libresoc.v:149753$7471 assign { } { } assign { } { } assign { } { } @@ -310045,17 +312542,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7424 $1\trapexc_$signal[0:0]$7432 - assign $0\trapexc_$signal$60[0:0]$7425 $1\trapexc_$signal$60[0:0]$7433 - assign $0\trapexc_$signal$61[0:0]$7426 $1\trapexc_$signal$61[0:0]$7434 - assign $0\trapexc_$signal$62[0:0]$7427 $1\trapexc_$signal$62[0:0]$7435 - assign $0\trapexc_$signal$67[0:0]$7428 $1\trapexc_$signal$67[0:0]$7436 - assign $0\trapexc_$signal$68[0:0]$7429 $1\trapexc_$signal$68[0:0]$7437 - assign $0\trapexc_$signal$69[0:0]$7430 $1\trapexc_$signal$69[0:0]$7438 - assign $0\trapexc_$signal$70[0:0]$7431 $1\trapexc_$signal$70[0:0]$7439 - attribute \src "libresoc.v:148122.5-148122.29" + assign $0\trapexc_$signal[0:0]$7472 $1\trapexc_$signal[0:0]$7480 + assign $0\trapexc_$signal$60[0:0]$7473 $1\trapexc_$signal$60[0:0]$7481 + assign $0\trapexc_$signal$61[0:0]$7474 $1\trapexc_$signal$61[0:0]$7482 + assign $0\trapexc_$signal$62[0:0]$7475 $1\trapexc_$signal$62[0:0]$7483 + assign $0\trapexc_$signal$67[0:0]$7476 $1\trapexc_$signal$67[0:0]$7484 + assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 + assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 + assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:149754.5-149754.29" switch \initial - attribute \src "libresoc.v:148122.9-148122.17" + attribute \src "libresoc.v:149754.9-149754.17" case 1'1 case end @@ -310071,14 +312568,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7432 $2\trapexc_$signal[0:0]$7440 - assign $1\trapexc_$signal$60[0:0]$7433 $2\trapexc_$signal$60[0:0]$7441 - assign $1\trapexc_$signal$61[0:0]$7434 $2\trapexc_$signal$61[0:0]$7442 - assign $1\trapexc_$signal$62[0:0]$7435 $2\trapexc_$signal$62[0:0]$7443 - assign $1\trapexc_$signal$67[0:0]$7436 $2\trapexc_$signal$67[0:0]$7444 - assign $1\trapexc_$signal$68[0:0]$7437 $2\trapexc_$signal$68[0:0]$7445 - assign $1\trapexc_$signal$69[0:0]$7438 $2\trapexc_$signal$69[0:0]$7446 - assign $1\trapexc_$signal$70[0:0]$7439 $2\trapexc_$signal$70[0:0]$7447 + assign $1\trapexc_$signal[0:0]$7480 $2\trapexc_$signal[0:0]$7488 + assign $1\trapexc_$signal$60[0:0]$7481 $2\trapexc_$signal$60[0:0]$7489 + assign $1\trapexc_$signal$61[0:0]$7482 $2\trapexc_$signal$61[0:0]$7490 + assign $1\trapexc_$signal$62[0:0]$7483 $2\trapexc_$signal$62[0:0]$7491 + assign $1\trapexc_$signal$67[0:0]$7484 $2\trapexc_$signal$67[0:0]$7492 + assign $1\trapexc_$signal$68[0:0]$7485 $2\trapexc_$signal$68[0:0]$7493 + assign $1\trapexc_$signal$69[0:0]$7486 $2\trapexc_$signal$69[0:0]$7494 + assign $1\trapexc_$signal$70[0:0]$7487 $2\trapexc_$signal$70[0:0]$7495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -310091,14 +312588,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7440 $3\trapexc_$signal[0:0]$7448 - assign $2\trapexc_$signal$60[0:0]$7441 $3\trapexc_$signal$60[0:0]$7449 - assign $2\trapexc_$signal$61[0:0]$7442 $3\trapexc_$signal$61[0:0]$7450 - assign $2\trapexc_$signal$62[0:0]$7443 $3\trapexc_$signal$62[0:0]$7451 - assign $2\trapexc_$signal$67[0:0]$7444 $3\trapexc_$signal$67[0:0]$7452 - assign $2\trapexc_$signal$68[0:0]$7445 $3\trapexc_$signal$68[0:0]$7453 - assign $2\trapexc_$signal$69[0:0]$7446 $3\trapexc_$signal$69[0:0]$7454 - assign $2\trapexc_$signal$70[0:0]$7447 $3\trapexc_$signal$70[0:0]$7455 + assign $2\trapexc_$signal[0:0]$7488 $3\trapexc_$signal[0:0]$7496 + assign $2\trapexc_$signal$60[0:0]$7489 $3\trapexc_$signal$60[0:0]$7497 + assign $2\trapexc_$signal$61[0:0]$7490 $3\trapexc_$signal$61[0:0]$7498 + assign $2\trapexc_$signal$62[0:0]$7491 $3\trapexc_$signal$62[0:0]$7499 + assign $2\trapexc_$signal$67[0:0]$7492 $3\trapexc_$signal$67[0:0]$7500 + assign $2\trapexc_$signal$68[0:0]$7493 $3\trapexc_$signal$68[0:0]$7501 + assign $2\trapexc_$signal$69[0:0]$7494 $3\trapexc_$signal$69[0:0]$7502 + assign $2\trapexc_$signal$70[0:0]$7495 $3\trapexc_$signal$70[0:0]$7503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -310111,54 +312608,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7455 $3\trapexc_$signal$62[0:0]$7451 $3\trapexc_$signal$60[0:0]$7449 $3\trapexc_$signal$61[0:0]$7450 $3\trapexc_$signal[0:0]$7448 $3\trapexc_$signal$69[0:0]$7454 $3\trapexc_$signal$68[0:0]$7453 $3\trapexc_$signal$67[0:0]$7452 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7503 $3\trapexc_$signal$62[0:0]$7499 $3\trapexc_$signal$60[0:0]$7497 $3\trapexc_$signal$61[0:0]$7498 $3\trapexc_$signal[0:0]$7496 $3\trapexc_$signal$69[0:0]$7502 $3\trapexc_$signal$68[0:0]$7501 $3\trapexc_$signal$67[0:0]$7500 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7448 1'0 - assign $3\trapexc_$signal$60[0:0]$7449 1'0 - assign $3\trapexc_$signal$61[0:0]$7450 1'0 - assign $3\trapexc_$signal$62[0:0]$7451 1'0 - assign $3\trapexc_$signal$67[0:0]$7452 1'0 - assign $3\trapexc_$signal$68[0:0]$7453 1'0 - assign $3\trapexc_$signal$69[0:0]$7454 1'0 - assign $3\trapexc_$signal$70[0:0]$7455 1'0 + assign $3\trapexc_$signal[0:0]$7496 1'0 + assign $3\trapexc_$signal$60[0:0]$7497 1'0 + assign $3\trapexc_$signal$61[0:0]$7498 1'0 + assign $3\trapexc_$signal$62[0:0]$7499 1'0 + assign $3\trapexc_$signal$67[0:0]$7500 1'0 + assign $3\trapexc_$signal$68[0:0]$7501 1'0 + assign $3\trapexc_$signal$69[0:0]$7502 1'0 + assign $3\trapexc_$signal$70[0:0]$7503 1'0 end case - assign $2\trapexc_$signal[0:0]$7440 1'0 - assign $2\trapexc_$signal$60[0:0]$7441 1'0 - assign $2\trapexc_$signal$61[0:0]$7442 1'0 - assign $2\trapexc_$signal$62[0:0]$7443 1'0 - assign $2\trapexc_$signal$67[0:0]$7444 1'0 - assign $2\trapexc_$signal$68[0:0]$7445 1'0 - assign $2\trapexc_$signal$69[0:0]$7446 1'0 - assign $2\trapexc_$signal$70[0:0]$7447 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7432 1'0 - assign $1\trapexc_$signal$60[0:0]$7433 1'0 - assign $1\trapexc_$signal$61[0:0]$7434 1'0 - assign $1\trapexc_$signal$62[0:0]$7435 1'0 - assign $1\trapexc_$signal$67[0:0]$7436 1'0 - assign $1\trapexc_$signal$68[0:0]$7437 1'0 - assign $1\trapexc_$signal$69[0:0]$7438 1'0 - assign $1\trapexc_$signal$70[0:0]$7439 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7424 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7425 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7426 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7427 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7428 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7429 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7430 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7431 - end - attribute \src "libresoc.v:148149.3-148160.6" - process $proc$libresoc.v:148149$7456 + assign $2\trapexc_$signal[0:0]$7488 1'0 + assign $2\trapexc_$signal$60[0:0]$7489 1'0 + assign $2\trapexc_$signal$61[0:0]$7490 1'0 + assign $2\trapexc_$signal$62[0:0]$7491 1'0 + assign $2\trapexc_$signal$67[0:0]$7492 1'0 + assign $2\trapexc_$signal$68[0:0]$7493 1'0 + assign $2\trapexc_$signal$69[0:0]$7494 1'0 + assign $2\trapexc_$signal$70[0:0]$7495 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7480 1'0 + assign $1\trapexc_$signal$60[0:0]$7481 1'0 + assign $1\trapexc_$signal$61[0:0]$7482 1'0 + assign $1\trapexc_$signal$62[0:0]$7483 1'0 + assign $1\trapexc_$signal$67[0:0]$7484 1'0 + assign $1\trapexc_$signal$68[0:0]$7485 1'0 + assign $1\trapexc_$signal$69[0:0]$7486 1'0 + assign $1\trapexc_$signal$70[0:0]$7487 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7472 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7473 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7474 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7475 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7476 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7477 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 + end + attribute \src "libresoc.v:149781.3-149792.6" + process $proc$libresoc.v:149781$7504 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:148150.5-148150.29" + attribute \src "libresoc.v:149782.5-149782.29" switch \initial - attribute \src "libresoc.v:148150.9-148150.17" + attribute \src "libresoc.v:149782.9-149782.17" case 1'1 case end @@ -310176,17 +312673,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:148161.3-148329.6" - process $proc$libresoc.v:148161$7457 + attribute \src "libresoc.v:149793.3-149961.6" + process $proc$libresoc.v:149793$7505 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:148162.5-148162.29" + attribute \src "libresoc.v:149794.5-149794.29" switch \initial - attribute \src "libresoc.v:148162.9-148162.17" + attribute \src "libresoc.v:149794.9-149794.17" case 1'1 case end @@ -310400,14 +312897,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:148330.3-148348.6" - process $proc$libresoc.v:148330$7458 + attribute \src "libresoc.v:149962.3-149980.6" + process $proc$libresoc.v:149962$7506 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148331.5-148331.29" + attribute \src "libresoc.v:149963.5-149963.29" switch \initial - attribute \src "libresoc.v:148331.9-148331.17" + attribute \src "libresoc.v:149963.9-149963.17" case 1'1 case end @@ -310429,14 +312926,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:148349.3-148367.6" - process $proc$libresoc.v:148349$7459 + attribute \src "libresoc.v:149981.3-149999.6" + process $proc$libresoc.v:149981$7507 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148350.5-148350.29" + attribute \src "libresoc.v:149982.5-149982.29" switch \initial - attribute \src "libresoc.v:148350.9-148350.17" + attribute \src "libresoc.v:149982.9-149982.17" case 1'1 case end @@ -310458,13 +312955,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148368.3-148379.6" - process $proc$libresoc.v:148368$7460 + attribute \src "libresoc.v:150000.3-150011.6" + process $proc$libresoc.v:150000$7508 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:148369.5-148369.29" + attribute \src "libresoc.v:150001.5-150001.29" switch \initial - attribute \src "libresoc.v:148369.9-148369.17" + attribute \src "libresoc.v:150001.9-150001.17" case 1'1 case end @@ -310482,13 +312979,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:148380.3-148391.6" - process $proc$libresoc.v:148380$7461 + attribute \src "libresoc.v:150012.3-150023.6" + process $proc$libresoc.v:150012$7509 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:148381.5-148381.29" + attribute \src "libresoc.v:150013.5-150013.29" switch \initial - attribute \src "libresoc.v:148381.9-148381.17" + attribute \src "libresoc.v:150013.9-150013.17" case 1'1 case end @@ -310506,43 +313003,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:147829$7362_Y - connect \$15 $pos$libresoc.v:147830$7364_Y - connect \$17 $lt$libresoc.v:147831$7365_Y - connect \$19 $gt$libresoc.v:147832$7366_Y - connect \$21 $lt$libresoc.v:147833$7367_Y - connect \$23 $gt$libresoc.v:147834$7368_Y - connect \$25 $eq$libresoc.v:147835$7369_Y - connect \$28 $and$libresoc.v:147836$7370_Y - connect \$27 $reduce_or$libresoc.v:147837$7371_Y - connect \$31 $reduce_or$libresoc.v:147838$7372_Y - connect \$33 $or$libresoc.v:147839$7373_Y - connect \$36 $sshl$libresoc.v:147840$7374_Y - connect \$35 $pos$libresoc.v:147841$7376_Y - connect \$40 $add$libresoc.v:147842$7377_Y - connect \$42 $eq$libresoc.v:147843$7378_Y - connect \$45 $and$libresoc.v:147844$7379_Y - connect \$44 $reduce_or$libresoc.v:147845$7380_Y - connect \$49 $and$libresoc.v:147846$7381_Y - connect \$48 $reduce_or$libresoc.v:147847$7382_Y - connect \$53 $and$libresoc.v:147848$7383_Y - connect \$52 $reduce_or$libresoc.v:147849$7384_Y - connect \$57 $and$libresoc.v:147850$7385_Y - connect \$56 $reduce_or$libresoc.v:147851$7386_Y - connect \$64 $and$libresoc.v:147852$7387_Y - connect \$63 $reduce_or$libresoc.v:147853$7388_Y - connect \$72 $and$libresoc.v:147854$7389_Y - connect \$71 $reduce_or$libresoc.v:147855$7390_Y - connect \$75 $pos$libresoc.v:147856$7392_Y - connect \$77 $eq$libresoc.v:147857$7393_Y - connect \$79 $eq$libresoc.v:147858$7394_Y - connect \$81 $eq$libresoc.v:147859$7395_Y - connect \$83 $and$libresoc.v:147860$7396_Y - connect \$85 $not$libresoc.v:147861$7397_Y - connect \$87 $not$libresoc.v:147862$7398_Y - connect \$89 $eq$libresoc.v:147863$7399_Y - connect \$91 $eq$libresoc.v:147864$7400_Y - connect \$93 $and$libresoc.v:147865$7401_Y + connect \$13 $pos$libresoc.v:149461$7410_Y + connect \$15 $pos$libresoc.v:149462$7412_Y + connect \$17 $lt$libresoc.v:149463$7413_Y + connect \$19 $gt$libresoc.v:149464$7414_Y + connect \$21 $lt$libresoc.v:149465$7415_Y + connect \$23 $gt$libresoc.v:149466$7416_Y + connect \$25 $eq$libresoc.v:149467$7417_Y + connect \$28 $and$libresoc.v:149468$7418_Y + connect \$27 $reduce_or$libresoc.v:149469$7419_Y + connect \$31 $reduce_or$libresoc.v:149470$7420_Y + connect \$33 $or$libresoc.v:149471$7421_Y + connect \$36 $sshl$libresoc.v:149472$7422_Y + connect \$35 $pos$libresoc.v:149473$7424_Y + connect \$40 $add$libresoc.v:149474$7425_Y + connect \$42 $eq$libresoc.v:149475$7426_Y + connect \$45 $and$libresoc.v:149476$7427_Y + connect \$44 $reduce_or$libresoc.v:149477$7428_Y + connect \$49 $and$libresoc.v:149478$7429_Y + connect \$48 $reduce_or$libresoc.v:149479$7430_Y + connect \$53 $and$libresoc.v:149480$7431_Y + connect \$52 $reduce_or$libresoc.v:149481$7432_Y + connect \$57 $and$libresoc.v:149482$7433_Y + connect \$56 $reduce_or$libresoc.v:149483$7434_Y + connect \$64 $and$libresoc.v:149484$7435_Y + connect \$63 $reduce_or$libresoc.v:149485$7436_Y + connect \$72 $and$libresoc.v:149486$7437_Y + connect \$71 $reduce_or$libresoc.v:149487$7438_Y + connect \$75 $pos$libresoc.v:149488$7440_Y + connect \$77 $eq$libresoc.v:149489$7441_Y + connect \$79 $eq$libresoc.v:149490$7442_Y + connect \$81 $eq$libresoc.v:149491$7443_Y + connect \$83 $and$libresoc.v:149492$7444_Y + connect \$85 $not$libresoc.v:149493$7445_Y + connect \$87 $not$libresoc.v:149494$7446_Y + connect \$89 $eq$libresoc.v:149495$7447_Y + connect \$91 $eq$libresoc.v:149496$7448_Y + connect \$93 $and$libresoc.v:149497$7449_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -310555,239 +313052,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:148407.1-149156.10" +attribute \src "libresoc.v:150039.1-150788.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:149123.3-149133.6" + attribute \src "libresoc.v:150755.3-150765.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:149068.3-149078.6" + attribute \src "libresoc.v:150700.3-150710.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:149046.3-149056.6" + attribute \src "libresoc.v:150678.3-150688.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:149035.3-149045.6" + attribute \src "libresoc.v:150667.3-150677.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:149024.3-149034.6" + attribute \src "libresoc.v:150656.3-150666.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:149112.3-149122.6" + attribute \src "libresoc.v:150744.3-150754.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:148408.7-148408.20" + attribute \src "libresoc.v:150040.7-150040.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149090.3-149100.6" + attribute \src "libresoc.v:150722.3-150732.6" wire $0\par0[0:0] - attribute \src "libresoc.v:149101.3-149111.6" + attribute \src "libresoc.v:150733.3-150743.6" wire $0\par1[0:0] - attribute \src "libresoc.v:149057.3-149067.6" + attribute \src "libresoc.v:150689.3-150699.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:149079.3-149089.6" + attribute \src "libresoc.v:150711.3-150721.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:149123.3-149133.6" + attribute \src "libresoc.v:150755.3-150765.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:149068.3-149078.6" + attribute \src "libresoc.v:150700.3-150710.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:149046.3-149056.6" + attribute \src "libresoc.v:150678.3-150688.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:149035.3-149045.6" + attribute \src "libresoc.v:150667.3-150677.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:149024.3-149034.6" + attribute \src "libresoc.v:150656.3-150666.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:149112.3-149122.6" + attribute \src "libresoc.v:150744.3-150754.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149090.3-149100.6" + attribute \src "libresoc.v:150722.3-150732.6" wire $1\par0[0:0] - attribute \src "libresoc.v:149101.3-149111.6" + attribute \src "libresoc.v:150733.3-150743.6" wire $1\par1[0:0] - attribute \src "libresoc.v:149057.3-149067.6" + attribute \src "libresoc.v:150689.3-150699.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:149079.3-149089.6" + attribute \src "libresoc.v:150711.3-150721.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:148916.18-148916.103" - wire width 64 $and$libresoc.v:148916$7509_Y - attribute \src "libresoc.v:148875.18-148875.118" - wire $eq$libresoc.v:148875$7463_Y - attribute \src "libresoc.v:148876.19-148876.119" - wire $eq$libresoc.v:148876$7464_Y - attribute \src "libresoc.v:148877.19-148877.119" - wire $eq$libresoc.v:148877$7465_Y - attribute \src "libresoc.v:148878.19-148878.119" - wire $eq$libresoc.v:148878$7466_Y - attribute \src "libresoc.v:148879.19-148879.119" - wire $eq$libresoc.v:148879$7467_Y - attribute \src "libresoc.v:148880.19-148880.119" - wire $eq$libresoc.v:148880$7468_Y - attribute \src "libresoc.v:148881.19-148881.119" - wire $eq$libresoc.v:148881$7469_Y - attribute \src "libresoc.v:148882.19-148882.119" - wire $eq$libresoc.v:148882$7470_Y - attribute \src "libresoc.v:148883.19-148883.119" - wire $eq$libresoc.v:148883$7471_Y - attribute \src "libresoc.v:148884.19-148884.119" - wire $eq$libresoc.v:148884$7472_Y - attribute \src "libresoc.v:148885.19-148885.119" - wire $eq$libresoc.v:148885$7473_Y - attribute \src "libresoc.v:148886.19-148886.119" - wire $eq$libresoc.v:148886$7474_Y - attribute \src "libresoc.v:148887.19-148887.119" - wire $eq$libresoc.v:148887$7475_Y - attribute \src "libresoc.v:148888.19-148888.119" - wire $eq$libresoc.v:148888$7476_Y - attribute \src "libresoc.v:148889.19-148889.119" - wire $eq$libresoc.v:148889$7477_Y - attribute \src "libresoc.v:148890.19-148890.119" - wire $eq$libresoc.v:148890$7478_Y - attribute \src "libresoc.v:148891.19-148891.119" - wire $eq$libresoc.v:148891$7479_Y - attribute \src "libresoc.v:148892.19-148892.119" - wire $eq$libresoc.v:148892$7480_Y - attribute \src "libresoc.v:148893.19-148893.119" - wire $eq$libresoc.v:148893$7481_Y - attribute \src "libresoc.v:148894.19-148894.119" - wire $eq$libresoc.v:148894$7482_Y - attribute \src "libresoc.v:148895.19-148895.119" - wire $eq$libresoc.v:148895$7483_Y - attribute \src "libresoc.v:148896.19-148896.119" - wire $eq$libresoc.v:148896$7484_Y - attribute \src "libresoc.v:148897.19-148897.119" - wire $eq$libresoc.v:148897$7485_Y - attribute \src "libresoc.v:148898.19-148898.119" - wire $eq$libresoc.v:148898$7486_Y - attribute \src "libresoc.v:148899.19-148899.119" - wire $eq$libresoc.v:148899$7487_Y - attribute \src "libresoc.v:148900.19-148900.119" - wire $eq$libresoc.v:148900$7488_Y - attribute \src "libresoc.v:148901.19-148901.119" - wire $eq$libresoc.v:148901$7489_Y - attribute \src "libresoc.v:148902.19-148902.119" - wire $eq$libresoc.v:148902$7490_Y - attribute \src "libresoc.v:148903.19-148903.128" - wire $eq$libresoc.v:148903$7491_Y - attribute \src "libresoc.v:148919.18-148919.114" - wire $eq$libresoc.v:148919$7512_Y - attribute \src "libresoc.v:148920.18-148920.114" - wire $eq$libresoc.v:148920$7513_Y - attribute \src "libresoc.v:148921.18-148921.114" - wire $eq$libresoc.v:148921$7514_Y - attribute \src "libresoc.v:148922.18-148922.114" - wire $eq$libresoc.v:148922$7515_Y - attribute \src "libresoc.v:148923.18-148923.114" - wire $eq$libresoc.v:148923$7516_Y - attribute \src "libresoc.v:148924.18-148924.114" - wire $eq$libresoc.v:148924$7517_Y - attribute \src "libresoc.v:148925.18-148925.114" - wire $eq$libresoc.v:148925$7518_Y - attribute \src "libresoc.v:148926.18-148926.114" - wire $eq$libresoc.v:148926$7519_Y - attribute \src "libresoc.v:148927.18-148927.116" - wire $eq$libresoc.v:148927$7520_Y - attribute \src "libresoc.v:148928.18-148928.116" - wire $eq$libresoc.v:148928$7521_Y - attribute \src "libresoc.v:148929.18-148929.116" - wire $eq$libresoc.v:148929$7522_Y - attribute \src "libresoc.v:148930.18-148930.116" - wire $eq$libresoc.v:148930$7523_Y - attribute \src "libresoc.v:148931.18-148931.116" - wire $eq$libresoc.v:148931$7524_Y - attribute \src "libresoc.v:148932.18-148932.116" - wire $eq$libresoc.v:148932$7525_Y - attribute \src "libresoc.v:148933.18-148933.116" - wire $eq$libresoc.v:148933$7526_Y - attribute \src "libresoc.v:148934.18-148934.116" - wire $eq$libresoc.v:148934$7527_Y - attribute \src "libresoc.v:148935.18-148935.118" - wire $eq$libresoc.v:148935$7528_Y - attribute \src "libresoc.v:148936.18-148936.118" - wire $eq$libresoc.v:148936$7529_Y - attribute \src "libresoc.v:148937.18-148937.118" - wire $eq$libresoc.v:148937$7530_Y - attribute \src "libresoc.v:148938.18-148938.118" - wire $eq$libresoc.v:148938$7531_Y - attribute \src "libresoc.v:148939.18-148939.118" - wire $eq$libresoc.v:148939$7532_Y - attribute \src "libresoc.v:148940.18-148940.118" - wire $eq$libresoc.v:148940$7533_Y - attribute \src "libresoc.v:148941.18-148941.118" - wire $eq$libresoc.v:148941$7534_Y - attribute \src "libresoc.v:148942.18-148942.118" - wire $eq$libresoc.v:148942$7535_Y - attribute \src "libresoc.v:148943.18-148943.118" - wire $eq$libresoc.v:148943$7536_Y - attribute \src "libresoc.v:148944.18-148944.118" - wire $eq$libresoc.v:148944$7537_Y - attribute \src "libresoc.v:148945.18-148945.118" - wire $eq$libresoc.v:148945$7538_Y - attribute \src "libresoc.v:148946.18-148946.118" - wire $eq$libresoc.v:148946$7539_Y - attribute \src "libresoc.v:148947.18-148947.118" - wire $eq$libresoc.v:148947$7540_Y - attribute \src "libresoc.v:148948.18-148948.118" - wire $eq$libresoc.v:148948$7541_Y - attribute \src "libresoc.v:148949.18-148949.118" - wire $eq$libresoc.v:148949$7542_Y - attribute \src "libresoc.v:148950.18-148950.118" - wire $eq$libresoc.v:148950$7543_Y - attribute \src "libresoc.v:148951.18-148951.118" - wire $eq$libresoc.v:148951$7544_Y - attribute \src "libresoc.v:148952.18-148952.118" - wire $eq$libresoc.v:148952$7545_Y - attribute \src "libresoc.v:148953.18-148953.118" - wire $eq$libresoc.v:148953$7546_Y - attribute \src "libresoc.v:148954.18-148954.118" - wire $eq$libresoc.v:148954$7547_Y - attribute \src "libresoc.v:148905.19-148905.104" - wire width 64 $extend$libresoc.v:148905$7493_Y - attribute \src "libresoc.v:148907.19-148907.93" - wire width 8 $extend$libresoc.v:148907$7496_Y - attribute \src "libresoc.v:148909.19-148909.105" - wire width 64 $extend$libresoc.v:148909$7499_Y - attribute \src "libresoc.v:148910.19-148910.118" - wire width 64 $extend$libresoc.v:148910$7501_Y - attribute \src "libresoc.v:148914.19-148914.105" - wire width 64 $extend$libresoc.v:148914$7506_Y - attribute \src "libresoc.v:148917.18-148917.103" - wire width 64 $or$libresoc.v:148917$7510_Y - attribute \src "libresoc.v:148905.19-148905.104" - wire width 64 $pos$libresoc.v:148905$7494_Y - attribute \src "libresoc.v:148907.19-148907.93" - wire width 8 $pos$libresoc.v:148907$7497_Y - attribute \src "libresoc.v:148909.19-148909.105" - wire width 64 $pos$libresoc.v:148909$7500_Y - attribute \src "libresoc.v:148910.19-148910.118" - wire width 64 $pos$libresoc.v:148910$7502_Y - attribute \src "libresoc.v:148914.19-148914.105" - wire width 64 $pos$libresoc.v:148914$7507_Y - attribute \src "libresoc.v:148911.19-148911.131" - wire $reduce_xor$libresoc.v:148911$7503_Y - attribute \src "libresoc.v:148912.19-148912.133" - wire $reduce_xor$libresoc.v:148912$7504_Y - attribute \src "libresoc.v:148906.19-148906.112" - wire width 8 $sub$libresoc.v:148906$7495_Y - attribute \src "libresoc.v:148908.19-148908.135" - wire width 8 $ternary$libresoc.v:148908$7498_Y - attribute \src "libresoc.v:148913.19-148913.398" - wire width 32 $ternary$libresoc.v:148913$7505_Y - attribute \src "libresoc.v:148915.19-148915.621" - wire width 64 $ternary$libresoc.v:148915$7508_Y - attribute \src "libresoc.v:148904.19-148904.108" - wire $xor$libresoc.v:148904$7492_Y - attribute \src "libresoc.v:148918.18-148918.103" - wire width 64 $xor$libresoc.v:148918$7511_Y + attribute \src "libresoc.v:150548.18-150548.103" + wire width 64 $and$libresoc.v:150548$7557_Y + attribute \src "libresoc.v:150507.18-150507.118" + wire $eq$libresoc.v:150507$7511_Y + attribute \src "libresoc.v:150508.19-150508.119" + wire $eq$libresoc.v:150508$7512_Y + attribute \src "libresoc.v:150509.19-150509.119" + wire $eq$libresoc.v:150509$7513_Y + attribute \src "libresoc.v:150510.19-150510.119" + wire $eq$libresoc.v:150510$7514_Y + attribute \src "libresoc.v:150511.19-150511.119" + wire $eq$libresoc.v:150511$7515_Y + attribute \src "libresoc.v:150512.19-150512.119" + wire $eq$libresoc.v:150512$7516_Y + attribute \src "libresoc.v:150513.19-150513.119" + wire $eq$libresoc.v:150513$7517_Y + attribute \src "libresoc.v:150514.19-150514.119" + wire $eq$libresoc.v:150514$7518_Y + attribute \src "libresoc.v:150515.19-150515.119" + wire $eq$libresoc.v:150515$7519_Y + attribute \src "libresoc.v:150516.19-150516.119" + wire $eq$libresoc.v:150516$7520_Y + attribute \src "libresoc.v:150517.19-150517.119" + wire $eq$libresoc.v:150517$7521_Y + attribute \src "libresoc.v:150518.19-150518.119" + wire $eq$libresoc.v:150518$7522_Y + attribute \src "libresoc.v:150519.19-150519.119" + wire $eq$libresoc.v:150519$7523_Y + attribute \src "libresoc.v:150520.19-150520.119" + wire $eq$libresoc.v:150520$7524_Y + attribute \src "libresoc.v:150521.19-150521.119" + wire $eq$libresoc.v:150521$7525_Y + attribute \src "libresoc.v:150522.19-150522.119" + wire $eq$libresoc.v:150522$7526_Y + attribute \src "libresoc.v:150523.19-150523.119" + wire $eq$libresoc.v:150523$7527_Y + attribute \src "libresoc.v:150524.19-150524.119" + wire $eq$libresoc.v:150524$7528_Y + attribute \src "libresoc.v:150525.19-150525.119" + wire $eq$libresoc.v:150525$7529_Y + attribute \src "libresoc.v:150526.19-150526.119" + wire $eq$libresoc.v:150526$7530_Y + attribute \src "libresoc.v:150527.19-150527.119" + wire $eq$libresoc.v:150527$7531_Y + attribute \src "libresoc.v:150528.19-150528.119" + wire $eq$libresoc.v:150528$7532_Y + attribute \src "libresoc.v:150529.19-150529.119" + wire $eq$libresoc.v:150529$7533_Y + attribute \src "libresoc.v:150530.19-150530.119" + wire $eq$libresoc.v:150530$7534_Y + attribute \src "libresoc.v:150531.19-150531.119" + wire $eq$libresoc.v:150531$7535_Y + attribute \src "libresoc.v:150532.19-150532.119" + wire $eq$libresoc.v:150532$7536_Y + attribute \src "libresoc.v:150533.19-150533.119" + wire $eq$libresoc.v:150533$7537_Y + attribute \src "libresoc.v:150534.19-150534.119" + wire $eq$libresoc.v:150534$7538_Y + attribute \src "libresoc.v:150535.19-150535.128" + wire $eq$libresoc.v:150535$7539_Y + attribute \src "libresoc.v:150551.18-150551.114" + wire $eq$libresoc.v:150551$7560_Y + attribute \src "libresoc.v:150552.18-150552.114" + wire $eq$libresoc.v:150552$7561_Y + attribute \src "libresoc.v:150553.18-150553.114" + wire $eq$libresoc.v:150553$7562_Y + attribute \src "libresoc.v:150554.18-150554.114" + wire $eq$libresoc.v:150554$7563_Y + attribute \src "libresoc.v:150555.18-150555.114" + wire $eq$libresoc.v:150555$7564_Y + attribute \src "libresoc.v:150556.18-150556.114" + wire $eq$libresoc.v:150556$7565_Y + attribute \src "libresoc.v:150557.18-150557.114" + wire $eq$libresoc.v:150557$7566_Y + attribute \src "libresoc.v:150558.18-150558.114" + wire $eq$libresoc.v:150558$7567_Y + attribute \src "libresoc.v:150559.18-150559.116" + wire $eq$libresoc.v:150559$7568_Y + attribute \src "libresoc.v:150560.18-150560.116" + wire $eq$libresoc.v:150560$7569_Y + attribute \src "libresoc.v:150561.18-150561.116" + wire $eq$libresoc.v:150561$7570_Y + attribute \src "libresoc.v:150562.18-150562.116" + wire $eq$libresoc.v:150562$7571_Y + attribute \src "libresoc.v:150563.18-150563.116" + wire $eq$libresoc.v:150563$7572_Y + attribute \src "libresoc.v:150564.18-150564.116" + wire $eq$libresoc.v:150564$7573_Y + attribute \src "libresoc.v:150565.18-150565.116" + wire $eq$libresoc.v:150565$7574_Y + attribute \src "libresoc.v:150566.18-150566.116" + wire $eq$libresoc.v:150566$7575_Y + attribute \src "libresoc.v:150567.18-150567.118" + wire $eq$libresoc.v:150567$7576_Y + attribute \src "libresoc.v:150568.18-150568.118" + wire $eq$libresoc.v:150568$7577_Y + attribute \src "libresoc.v:150569.18-150569.118" + wire $eq$libresoc.v:150569$7578_Y + attribute \src "libresoc.v:150570.18-150570.118" + wire $eq$libresoc.v:150570$7579_Y + attribute \src "libresoc.v:150571.18-150571.118" + wire $eq$libresoc.v:150571$7580_Y + attribute \src "libresoc.v:150572.18-150572.118" + wire $eq$libresoc.v:150572$7581_Y + attribute \src "libresoc.v:150573.18-150573.118" + wire $eq$libresoc.v:150573$7582_Y + attribute \src "libresoc.v:150574.18-150574.118" + wire $eq$libresoc.v:150574$7583_Y + attribute \src "libresoc.v:150575.18-150575.118" + wire $eq$libresoc.v:150575$7584_Y + attribute \src "libresoc.v:150576.18-150576.118" + wire $eq$libresoc.v:150576$7585_Y + attribute \src "libresoc.v:150577.18-150577.118" + wire $eq$libresoc.v:150577$7586_Y + attribute \src "libresoc.v:150578.18-150578.118" + wire $eq$libresoc.v:150578$7587_Y + attribute \src "libresoc.v:150579.18-150579.118" + wire $eq$libresoc.v:150579$7588_Y + attribute \src "libresoc.v:150580.18-150580.118" + wire $eq$libresoc.v:150580$7589_Y + attribute \src "libresoc.v:150581.18-150581.118" + wire $eq$libresoc.v:150581$7590_Y + attribute \src "libresoc.v:150582.18-150582.118" + wire $eq$libresoc.v:150582$7591_Y + attribute \src "libresoc.v:150583.18-150583.118" + wire $eq$libresoc.v:150583$7592_Y + attribute \src "libresoc.v:150584.18-150584.118" + wire $eq$libresoc.v:150584$7593_Y + attribute \src "libresoc.v:150585.18-150585.118" + wire $eq$libresoc.v:150585$7594_Y + attribute \src "libresoc.v:150586.18-150586.118" + wire $eq$libresoc.v:150586$7595_Y + attribute \src "libresoc.v:150537.19-150537.104" + wire width 64 $extend$libresoc.v:150537$7541_Y + attribute \src "libresoc.v:150539.19-150539.93" + wire width 8 $extend$libresoc.v:150539$7544_Y + attribute \src "libresoc.v:150541.19-150541.105" + wire width 64 $extend$libresoc.v:150541$7547_Y + attribute \src "libresoc.v:150542.19-150542.118" + wire width 64 $extend$libresoc.v:150542$7549_Y + attribute \src "libresoc.v:150546.19-150546.105" + wire width 64 $extend$libresoc.v:150546$7554_Y + attribute \src "libresoc.v:150549.18-150549.103" + wire width 64 $or$libresoc.v:150549$7558_Y + attribute \src "libresoc.v:150537.19-150537.104" + wire width 64 $pos$libresoc.v:150537$7542_Y + attribute \src "libresoc.v:150539.19-150539.93" + wire width 8 $pos$libresoc.v:150539$7545_Y + attribute \src "libresoc.v:150541.19-150541.105" + wire width 64 $pos$libresoc.v:150541$7548_Y + attribute \src "libresoc.v:150542.19-150542.118" + wire width 64 $pos$libresoc.v:150542$7550_Y + attribute \src "libresoc.v:150546.19-150546.105" + wire width 64 $pos$libresoc.v:150546$7555_Y + attribute \src "libresoc.v:150543.19-150543.131" + wire $reduce_xor$libresoc.v:150543$7551_Y + attribute \src "libresoc.v:150544.19-150544.133" + wire $reduce_xor$libresoc.v:150544$7552_Y + attribute \src "libresoc.v:150538.19-150538.112" + wire width 8 $sub$libresoc.v:150538$7543_Y + attribute \src "libresoc.v:150540.19-150540.135" + wire width 8 $ternary$libresoc.v:150540$7546_Y + attribute \src "libresoc.v:150545.19-150545.398" + wire width 32 $ternary$libresoc.v:150545$7553_Y + attribute \src "libresoc.v:150547.19-150547.621" + wire width 64 $ternary$libresoc.v:150547$7556_Y + attribute \src "libresoc.v:150536.19-150536.108" + wire $xor$libresoc.v:150536$7540_Y + attribute \src "libresoc.v:150550.18-150550.103" + wire width 64 $xor$libresoc.v:150550$7559_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -310966,7 +313463,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:148408.7-148408.15" + attribute \src "libresoc.v:150040.7-150040.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -311255,7 +313752,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:148916$7509 + cell $and $and$libresoc.v:150548$7557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311263,10 +313760,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:148916$7509_Y + connect \Y $and$libresoc.v:150548$7557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148875$7463 + cell $eq $eq$libresoc.v:150507$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311274,10 +313771,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148875$7463_Y + connect \Y $eq$libresoc.v:150507$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148876$7464 + cell $eq $eq$libresoc.v:150508$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311285,10 +313782,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148876$7464_Y + connect \Y $eq$libresoc.v:150508$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148877$7465 + cell $eq $eq$libresoc.v:150509$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311296,10 +313793,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148877$7465_Y + connect \Y $eq$libresoc.v:150509$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148878$7466 + cell $eq $eq$libresoc.v:150510$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311307,10 +313804,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148878$7466_Y + connect \Y $eq$libresoc.v:150510$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148879$7467 + cell $eq $eq$libresoc.v:150511$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311318,10 +313815,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148879$7467_Y + connect \Y $eq$libresoc.v:150511$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148880$7468 + cell $eq $eq$libresoc.v:150512$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311329,10 +313826,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148880$7468_Y + connect \Y $eq$libresoc.v:150512$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148881$7469 + cell $eq $eq$libresoc.v:150513$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311340,10 +313837,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148881$7469_Y + connect \Y $eq$libresoc.v:150513$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148882$7470 + cell $eq $eq$libresoc.v:150514$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311351,10 +313848,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148882$7470_Y + connect \Y $eq$libresoc.v:150514$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148883$7471 + cell $eq $eq$libresoc.v:150515$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311362,10 +313859,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148883$7471_Y + connect \Y $eq$libresoc.v:150515$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148884$7472 + cell $eq $eq$libresoc.v:150516$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311373,10 +313870,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148884$7472_Y + connect \Y $eq$libresoc.v:150516$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148885$7473 + cell $eq $eq$libresoc.v:150517$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311384,10 +313881,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148885$7473_Y + connect \Y $eq$libresoc.v:150517$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148886$7474 + cell $eq $eq$libresoc.v:150518$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311395,10 +313892,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148886$7474_Y + connect \Y $eq$libresoc.v:150518$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148887$7475 + cell $eq $eq$libresoc.v:150519$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311406,10 +313903,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148887$7475_Y + connect \Y $eq$libresoc.v:150519$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148888$7476 + cell $eq $eq$libresoc.v:150520$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311417,10 +313914,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148888$7476_Y + connect \Y $eq$libresoc.v:150520$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148889$7477 + cell $eq $eq$libresoc.v:150521$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311428,10 +313925,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148889$7477_Y + connect \Y $eq$libresoc.v:150521$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148890$7478 + cell $eq $eq$libresoc.v:150522$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311439,10 +313936,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148890$7478_Y + connect \Y $eq$libresoc.v:150522$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148891$7479 + cell $eq $eq$libresoc.v:150523$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311450,10 +313947,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148891$7479_Y + connect \Y $eq$libresoc.v:150523$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148892$7480 + cell $eq $eq$libresoc.v:150524$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311461,10 +313958,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148892$7480_Y + connect \Y $eq$libresoc.v:150524$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148893$7481 + cell $eq $eq$libresoc.v:150525$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311472,10 +313969,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148893$7481_Y + connect \Y $eq$libresoc.v:150525$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148894$7482 + cell $eq $eq$libresoc.v:150526$7530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311483,10 +313980,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148894$7482_Y + connect \Y $eq$libresoc.v:150526$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148895$7483 + cell $eq $eq$libresoc.v:150527$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311494,10 +313991,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148895$7483_Y + connect \Y $eq$libresoc.v:150527$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148896$7484 + cell $eq $eq$libresoc.v:150528$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311505,10 +314002,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148896$7484_Y + connect \Y $eq$libresoc.v:150528$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148897$7485 + cell $eq $eq$libresoc.v:150529$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311516,10 +314013,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148897$7485_Y + connect \Y $eq$libresoc.v:150529$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148898$7486 + cell $eq $eq$libresoc.v:150530$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311527,10 +314024,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148898$7486_Y + connect \Y $eq$libresoc.v:150530$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148899$7487 + cell $eq $eq$libresoc.v:150531$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311538,10 +314035,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148899$7487_Y + connect \Y $eq$libresoc.v:150531$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148900$7488 + cell $eq $eq$libresoc.v:150532$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311549,10 +314046,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148900$7488_Y + connect \Y $eq$libresoc.v:150532$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148901$7489 + cell $eq $eq$libresoc.v:150533$7537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311560,10 +314057,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148901$7489_Y + connect \Y $eq$libresoc.v:150533$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148902$7490 + cell $eq $eq$libresoc.v:150534$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311571,10 +314068,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148902$7490_Y + connect \Y $eq$libresoc.v:150534$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:148903$7491 + cell $eq $eq$libresoc.v:150535$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311582,10 +314079,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:148903$7491_Y + connect \Y $eq$libresoc.v:150535$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148919$7512 + cell $eq $eq$libresoc.v:150551$7560 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311593,10 +314090,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148919$7512_Y + connect \Y $eq$libresoc.v:150551$7560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148920$7513 + cell $eq $eq$libresoc.v:150552$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311604,10 +314101,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148920$7513_Y + connect \Y $eq$libresoc.v:150552$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148921$7514 + cell $eq $eq$libresoc.v:150553$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311615,10 +314112,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148921$7514_Y + connect \Y $eq$libresoc.v:150553$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148922$7515 + cell $eq $eq$libresoc.v:150554$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311626,10 +314123,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148922$7515_Y + connect \Y $eq$libresoc.v:150554$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148923$7516 + cell $eq $eq$libresoc.v:150555$7564 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311637,10 +314134,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148923$7516_Y + connect \Y $eq$libresoc.v:150555$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148924$7517 + cell $eq $eq$libresoc.v:150556$7565 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311648,10 +314145,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148924$7517_Y + connect \Y $eq$libresoc.v:150556$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148925$7518 + cell $eq $eq$libresoc.v:150557$7566 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311659,10 +314156,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148925$7518_Y + connect \Y $eq$libresoc.v:150557$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148926$7519 + cell $eq $eq$libresoc.v:150558$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311670,10 +314167,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148926$7519_Y + connect \Y $eq$libresoc.v:150558$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148927$7520 + cell $eq $eq$libresoc.v:150559$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311681,10 +314178,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148927$7520_Y + connect \Y $eq$libresoc.v:150559$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148928$7521 + cell $eq $eq$libresoc.v:150560$7569 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311692,10 +314189,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148928$7521_Y + connect \Y $eq$libresoc.v:150560$7569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148929$7522 + cell $eq $eq$libresoc.v:150561$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311703,10 +314200,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148929$7522_Y + connect \Y $eq$libresoc.v:150561$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148930$7523 + cell $eq $eq$libresoc.v:150562$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311714,10 +314211,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148930$7523_Y + connect \Y $eq$libresoc.v:150562$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148931$7524 + cell $eq $eq$libresoc.v:150563$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311725,10 +314222,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148931$7524_Y + connect \Y $eq$libresoc.v:150563$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148932$7525 + cell $eq $eq$libresoc.v:150564$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311736,10 +314233,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148932$7525_Y + connect \Y $eq$libresoc.v:150564$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148933$7526 + cell $eq $eq$libresoc.v:150565$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311747,10 +314244,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148933$7526_Y + connect \Y $eq$libresoc.v:150565$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148934$7527 + cell $eq $eq$libresoc.v:150566$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311758,10 +314255,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148934$7527_Y + connect \Y $eq$libresoc.v:150566$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148935$7528 + cell $eq $eq$libresoc.v:150567$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311769,10 +314266,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148935$7528_Y + connect \Y $eq$libresoc.v:150567$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148936$7529 + cell $eq $eq$libresoc.v:150568$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311780,10 +314277,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148936$7529_Y + connect \Y $eq$libresoc.v:150568$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148937$7530 + cell $eq $eq$libresoc.v:150569$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311791,10 +314288,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148937$7530_Y + connect \Y $eq$libresoc.v:150569$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148938$7531 + cell $eq $eq$libresoc.v:150570$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311802,10 +314299,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148938$7531_Y + connect \Y $eq$libresoc.v:150570$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148939$7532 + cell $eq $eq$libresoc.v:150571$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311813,10 +314310,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148939$7532_Y + connect \Y $eq$libresoc.v:150571$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148940$7533 + cell $eq $eq$libresoc.v:150572$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311824,10 +314321,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148940$7533_Y + connect \Y $eq$libresoc.v:150572$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148941$7534 + cell $eq $eq$libresoc.v:150573$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311835,10 +314332,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148941$7534_Y + connect \Y $eq$libresoc.v:150573$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148942$7535 + cell $eq $eq$libresoc.v:150574$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311846,10 +314343,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148942$7535_Y + connect \Y $eq$libresoc.v:150574$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148943$7536 + cell $eq $eq$libresoc.v:150575$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311857,10 +314354,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148943$7536_Y + connect \Y $eq$libresoc.v:150575$7584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148944$7537 + cell $eq $eq$libresoc.v:150576$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311868,10 +314365,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148944$7537_Y + connect \Y $eq$libresoc.v:150576$7585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148945$7538 + cell $eq $eq$libresoc.v:150577$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311879,10 +314376,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148945$7538_Y + connect \Y $eq$libresoc.v:150577$7586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148946$7539 + cell $eq $eq$libresoc.v:150578$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311890,10 +314387,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148946$7539_Y + connect \Y $eq$libresoc.v:150578$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148947$7540 + cell $eq $eq$libresoc.v:150579$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311901,10 +314398,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148947$7540_Y + connect \Y $eq$libresoc.v:150579$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148948$7541 + cell $eq $eq$libresoc.v:150580$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311912,10 +314409,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148948$7541_Y + connect \Y $eq$libresoc.v:150580$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148949$7542 + cell $eq $eq$libresoc.v:150581$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311923,10 +314420,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148949$7542_Y + connect \Y $eq$libresoc.v:150581$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148950$7543 + cell $eq $eq$libresoc.v:150582$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311934,10 +314431,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148950$7543_Y + connect \Y $eq$libresoc.v:150582$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148951$7544 + cell $eq $eq$libresoc.v:150583$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311945,10 +314442,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148951$7544_Y + connect \Y $eq$libresoc.v:150583$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148952$7545 + cell $eq $eq$libresoc.v:150584$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311956,10 +314453,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148952$7545_Y + connect \Y $eq$libresoc.v:150584$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148953$7546 + cell $eq $eq$libresoc.v:150585$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311967,10 +314464,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148953$7546_Y + connect \Y $eq$libresoc.v:150585$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148954$7547 + cell $eq $eq$libresoc.v:150586$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311978,50 +314475,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148954$7547_Y + connect \Y $eq$libresoc.v:150586$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:148905$7493 + cell $pos $extend$libresoc.v:150537$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:148905$7493_Y + connect \Y $extend$libresoc.v:150537$7541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:148907$7496 + cell $pos $extend$libresoc.v:150539$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:148907$7496_Y + connect \Y $extend$libresoc.v:150539$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:148909$7499 + cell $pos $extend$libresoc.v:150541$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:148909$7499_Y + connect \Y $extend$libresoc.v:150541$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:148910$7501 + cell $pos $extend$libresoc.v:150542$7549 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:148910$7501_Y + connect \Y $extend$libresoc.v:150542$7549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:148914$7506 + cell $pos $extend$libresoc.v:150546$7554 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:148914$7506_Y + connect \Y $extend$libresoc.v:150546$7554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:148917$7510 + cell $or $or$libresoc.v:150549$7558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312029,66 +314526,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:148917$7510_Y + connect \Y $or$libresoc.v:150549$7558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:148905$7494 + cell $pos $pos$libresoc.v:150537$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148905$7493_Y - connect \Y $pos$libresoc.v:148905$7494_Y + connect \A $extend$libresoc.v:150537$7541_Y + connect \Y $pos$libresoc.v:150537$7542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:148907$7497 + cell $pos $pos$libresoc.v:150539$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:148907$7496_Y - connect \Y $pos$libresoc.v:148907$7497_Y + connect \A $extend$libresoc.v:150539$7544_Y + connect \Y $pos$libresoc.v:150539$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:148909$7500 + cell $pos $pos$libresoc.v:150541$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148909$7499_Y - connect \Y $pos$libresoc.v:148909$7500_Y + connect \A $extend$libresoc.v:150541$7547_Y + connect \Y $pos$libresoc.v:150541$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:148910$7502 + cell $pos $pos$libresoc.v:150542$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148910$7501_Y - connect \Y $pos$libresoc.v:148910$7502_Y + connect \A $extend$libresoc.v:150542$7549_Y + connect \Y $pos$libresoc.v:150542$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:148914$7507 + cell $pos $pos$libresoc.v:150546$7555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148914$7506_Y - connect \Y $pos$libresoc.v:148914$7507_Y + connect \A $extend$libresoc.v:150546$7554_Y + connect \Y $pos$libresoc.v:150546$7555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:148911$7503 + cell $reduce_xor $reduce_xor$libresoc.v:150543$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:148911$7503_Y + connect \Y $reduce_xor$libresoc.v:150543$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:148912$7504 + cell $reduce_xor $reduce_xor$libresoc.v:150544$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:148912$7504_Y + connect \Y $reduce_xor$libresoc.v:150544$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:148906$7495 + cell $sub $sub$libresoc.v:150538$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -312096,34 +314593,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:148906$7495_Y + connect \Y $sub$libresoc.v:150538$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:148908$7498 + cell $mux $ternary$libresoc.v:150540$7546 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:148908$7498_Y + connect \Y $ternary$libresoc.v:150540$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:148913$7505 + cell $mux $ternary$libresoc.v:150545$7553 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:148913$7505_Y + connect \Y $ternary$libresoc.v:150545$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:148915$7508 + cell $mux $ternary$libresoc.v:150547$7556 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:148915$7508_Y + connect \Y $ternary$libresoc.v:150547$7556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:148904$7492 + cell $xor $xor$libresoc.v:150536$7540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312131,10 +314628,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:148904$7492_Y + connect \Y $xor$libresoc.v:150536$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:148918$7511 + cell $xor $xor$libresoc.v:150550$7559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312142,47 +314639,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:148918$7511_Y + connect \Y $xor$libresoc.v:150550$7559_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:148955.10-148959.4" + attribute \src "libresoc.v:150587.10-150591.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:148960.7-148963.4" + attribute \src "libresoc.v:150592.7-150595.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:148964.12-148968.4" + attribute \src "libresoc.v:150596.12-150600.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:148408.7-148408.20" - process $proc$libresoc.v:148408$7560 + attribute \src "libresoc.v:150040.7-150040.20" + process $proc$libresoc.v:150040$7608 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148969.3-149023.6" - process $proc$libresoc.v:148969$7548 + attribute \src "libresoc.v:150601.3-150655.6" + process $proc$libresoc.v:150601$7596 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148970.5-148970.29" + attribute \src "libresoc.v:150602.5-150602.29" switch \initial - attribute \src "libresoc.v:148970.9-148970.17" + attribute \src "libresoc.v:150602.9-150602.17" case 1'1 case end @@ -312250,14 +314747,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:149024.3-149034.6" - process $proc$libresoc.v:149024$7549 + attribute \src "libresoc.v:150656.3-150666.6" + process $proc$libresoc.v:150656$7597 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:149025.5-149025.29" + attribute \src "libresoc.v:150657.5-150657.29" switch \initial - attribute \src "libresoc.v:149025.9-149025.17" + attribute \src "libresoc.v:150657.9-150657.17" case 1'1 case end @@ -312273,14 +314770,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:149035.3-149045.6" - process $proc$libresoc.v:149035$7550 + attribute \src "libresoc.v:150667.3-150677.6" + process $proc$libresoc.v:150667$7598 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:149036.5-149036.29" + attribute \src "libresoc.v:150668.5-150668.29" switch \initial - attribute \src "libresoc.v:149036.9-149036.17" + attribute \src "libresoc.v:150668.9-150668.17" case 1'1 case end @@ -312296,14 +314793,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:149046.3-149056.6" - process $proc$libresoc.v:149046$7551 + attribute \src "libresoc.v:150678.3-150688.6" + process $proc$libresoc.v:150678$7599 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:149047.5-149047.29" + attribute \src "libresoc.v:150679.5-150679.29" switch \initial - attribute \src "libresoc.v:149047.9-149047.17" + attribute \src "libresoc.v:150679.9-150679.17" case 1'1 case end @@ -312319,14 +314816,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:149057.3-149067.6" - process $proc$libresoc.v:149057$7552 + attribute \src "libresoc.v:150689.3-150699.6" + process $proc$libresoc.v:150689$7600 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:149058.5-149058.29" + attribute \src "libresoc.v:150690.5-150690.29" switch \initial - attribute \src "libresoc.v:149058.9-149058.17" + attribute \src "libresoc.v:150690.9-150690.17" case 1'1 case end @@ -312342,14 +314839,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:149068.3-149078.6" - process $proc$libresoc.v:149068$7553 + attribute \src "libresoc.v:150700.3-150710.6" + process $proc$libresoc.v:150700$7601 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:149069.5-149069.29" + attribute \src "libresoc.v:150701.5-150701.29" switch \initial - attribute \src "libresoc.v:149069.9-149069.17" + attribute \src "libresoc.v:150701.9-150701.17" case 1'1 case end @@ -312365,14 +314862,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:149079.3-149089.6" - process $proc$libresoc.v:149079$7554 + attribute \src "libresoc.v:150711.3-150721.6" + process $proc$libresoc.v:150711$7602 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:149080.5-149080.29" + attribute \src "libresoc.v:150712.5-150712.29" switch \initial - attribute \src "libresoc.v:149080.9-149080.17" + attribute \src "libresoc.v:150712.9-150712.17" case 1'1 case end @@ -312388,14 +314885,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:149090.3-149100.6" - process $proc$libresoc.v:149090$7555 + attribute \src "libresoc.v:150722.3-150732.6" + process $proc$libresoc.v:150722$7603 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:149091.5-149091.29" + attribute \src "libresoc.v:150723.5-150723.29" switch \initial - attribute \src "libresoc.v:149091.9-149091.17" + attribute \src "libresoc.v:150723.9-150723.17" case 1'1 case end @@ -312411,14 +314908,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:149101.3-149111.6" - process $proc$libresoc.v:149101$7556 + attribute \src "libresoc.v:150733.3-150743.6" + process $proc$libresoc.v:150733$7604 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:149102.5-149102.29" + attribute \src "libresoc.v:150734.5-150734.29" switch \initial - attribute \src "libresoc.v:149102.9-149102.17" + attribute \src "libresoc.v:150734.9-150734.17" case 1'1 case end @@ -312434,14 +314931,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:149112.3-149122.6" - process $proc$libresoc.v:149112$7557 + attribute \src "libresoc.v:150744.3-150754.6" + process $proc$libresoc.v:150744$7605 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:149113.5-149113.29" + attribute \src "libresoc.v:150745.5-150745.29" switch \initial - attribute \src "libresoc.v:149113.9-149113.17" + attribute \src "libresoc.v:150745.9-150745.17" case 1'1 case end @@ -312457,14 +314954,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:149123.3-149133.6" - process $proc$libresoc.v:149123$7558 + attribute \src "libresoc.v:150755.3-150765.6" + process $proc$libresoc.v:150755$7606 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:149124.5-149124.29" + attribute \src "libresoc.v:150756.5-150756.29" switch \initial - attribute \src "libresoc.v:149124.9-149124.17" + attribute \src "libresoc.v:150756.9-150756.17" case 1'1 case end @@ -312480,14 +314977,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:149134.3-149152.6" - process $proc$libresoc.v:149134$7559 + attribute \src "libresoc.v:150766.3-150784.6" + process $proc$libresoc.v:150766$7607 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:149135.5-149135.29" + attribute \src "libresoc.v:150767.5-150767.29" switch \initial - attribute \src "libresoc.v:149135.9-149135.17" + attribute \src "libresoc.v:150767.9-150767.17" case 1'1 case end @@ -312514,193 +315011,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:148875$7463_Y - connect \$101 $eq$libresoc.v:148876$7464_Y - connect \$103 $eq$libresoc.v:148877$7465_Y - connect \$105 $eq$libresoc.v:148878$7466_Y - connect \$107 $eq$libresoc.v:148879$7467_Y - connect \$109 $eq$libresoc.v:148880$7468_Y - connect \$111 $eq$libresoc.v:148881$7469_Y - connect \$113 $eq$libresoc.v:148882$7470_Y - connect \$115 $eq$libresoc.v:148883$7471_Y - connect \$117 $eq$libresoc.v:148884$7472_Y - connect \$119 $eq$libresoc.v:148885$7473_Y - connect \$121 $eq$libresoc.v:148886$7474_Y - connect \$123 $eq$libresoc.v:148887$7475_Y - connect \$125 $eq$libresoc.v:148888$7476_Y - connect \$127 $eq$libresoc.v:148889$7477_Y - connect \$129 $eq$libresoc.v:148890$7478_Y - connect \$131 $eq$libresoc.v:148891$7479_Y - connect \$133 $eq$libresoc.v:148892$7480_Y - connect \$135 $eq$libresoc.v:148893$7481_Y - connect \$137 $eq$libresoc.v:148894$7482_Y - connect \$139 $eq$libresoc.v:148895$7483_Y - connect \$141 $eq$libresoc.v:148896$7484_Y - connect \$143 $eq$libresoc.v:148897$7485_Y - connect \$145 $eq$libresoc.v:148898$7486_Y - connect \$147 $eq$libresoc.v:148899$7487_Y - connect \$149 $eq$libresoc.v:148900$7488_Y - connect \$151 $eq$libresoc.v:148901$7489_Y - connect \$153 $eq$libresoc.v:148902$7490_Y - connect \$155 $eq$libresoc.v:148903$7491_Y - connect \$158 $xor$libresoc.v:148904$7492_Y - connect \$157 $pos$libresoc.v:148905$7494_Y - connect \$162 $sub$libresoc.v:148906$7495_Y - connect \$164 $pos$libresoc.v:148907$7497_Y - connect \$166 $ternary$libresoc.v:148908$7498_Y - connect \$161 $pos$libresoc.v:148909$7500_Y - connect \$169 $pos$libresoc.v:148910$7502_Y - connect \$171 $reduce_xor$libresoc.v:148911$7503_Y - connect \$173 $reduce_xor$libresoc.v:148912$7504_Y - connect \$176 $ternary$libresoc.v:148913$7505_Y - connect \$175 $pos$libresoc.v:148914$7507_Y - connect \$179 $ternary$libresoc.v:148915$7508_Y - connect \$21 $and$libresoc.v:148916$7509_Y - connect \$23 $or$libresoc.v:148917$7510_Y - connect \$25 $xor$libresoc.v:148918$7511_Y - connect \$27 $eq$libresoc.v:148919$7512_Y - connect \$29 $eq$libresoc.v:148920$7513_Y - connect \$31 $eq$libresoc.v:148921$7514_Y - connect \$33 $eq$libresoc.v:148922$7515_Y - connect \$35 $eq$libresoc.v:148923$7516_Y - connect \$37 $eq$libresoc.v:148924$7517_Y - connect \$39 $eq$libresoc.v:148925$7518_Y - connect \$41 $eq$libresoc.v:148926$7519_Y - connect \$43 $eq$libresoc.v:148927$7520_Y - connect \$45 $eq$libresoc.v:148928$7521_Y - connect \$47 $eq$libresoc.v:148929$7522_Y - connect \$49 $eq$libresoc.v:148930$7523_Y - connect \$51 $eq$libresoc.v:148931$7524_Y - connect \$53 $eq$libresoc.v:148932$7525_Y - connect \$55 $eq$libresoc.v:148933$7526_Y - connect \$57 $eq$libresoc.v:148934$7527_Y - connect \$59 $eq$libresoc.v:148935$7528_Y - connect \$61 $eq$libresoc.v:148936$7529_Y - connect \$63 $eq$libresoc.v:148937$7530_Y - connect \$65 $eq$libresoc.v:148938$7531_Y - connect \$67 $eq$libresoc.v:148939$7532_Y - connect \$69 $eq$libresoc.v:148940$7533_Y - connect \$71 $eq$libresoc.v:148941$7534_Y - connect \$73 $eq$libresoc.v:148942$7535_Y - connect \$75 $eq$libresoc.v:148943$7536_Y - connect \$77 $eq$libresoc.v:148944$7537_Y - connect \$79 $eq$libresoc.v:148945$7538_Y - connect \$81 $eq$libresoc.v:148946$7539_Y - connect \$83 $eq$libresoc.v:148947$7540_Y - connect \$85 $eq$libresoc.v:148948$7541_Y - connect \$87 $eq$libresoc.v:148949$7542_Y - connect \$89 $eq$libresoc.v:148950$7543_Y - connect \$91 $eq$libresoc.v:148951$7544_Y - connect \$93 $eq$libresoc.v:148952$7545_Y - connect \$95 $eq$libresoc.v:148953$7546_Y - connect \$97 $eq$libresoc.v:148954$7547_Y + connect \$99 $eq$libresoc.v:150507$7511_Y + connect \$101 $eq$libresoc.v:150508$7512_Y + connect \$103 $eq$libresoc.v:150509$7513_Y + connect \$105 $eq$libresoc.v:150510$7514_Y + connect \$107 $eq$libresoc.v:150511$7515_Y + connect \$109 $eq$libresoc.v:150512$7516_Y + connect \$111 $eq$libresoc.v:150513$7517_Y + connect \$113 $eq$libresoc.v:150514$7518_Y + connect \$115 $eq$libresoc.v:150515$7519_Y + connect \$117 $eq$libresoc.v:150516$7520_Y + connect \$119 $eq$libresoc.v:150517$7521_Y + connect \$121 $eq$libresoc.v:150518$7522_Y + connect \$123 $eq$libresoc.v:150519$7523_Y + connect \$125 $eq$libresoc.v:150520$7524_Y + connect \$127 $eq$libresoc.v:150521$7525_Y + connect \$129 $eq$libresoc.v:150522$7526_Y + connect \$131 $eq$libresoc.v:150523$7527_Y + connect \$133 $eq$libresoc.v:150524$7528_Y + connect \$135 $eq$libresoc.v:150525$7529_Y + connect \$137 $eq$libresoc.v:150526$7530_Y + connect \$139 $eq$libresoc.v:150527$7531_Y + connect \$141 $eq$libresoc.v:150528$7532_Y + connect \$143 $eq$libresoc.v:150529$7533_Y + connect \$145 $eq$libresoc.v:150530$7534_Y + connect \$147 $eq$libresoc.v:150531$7535_Y + connect \$149 $eq$libresoc.v:150532$7536_Y + connect \$151 $eq$libresoc.v:150533$7537_Y + connect \$153 $eq$libresoc.v:150534$7538_Y + connect \$155 $eq$libresoc.v:150535$7539_Y + connect \$158 $xor$libresoc.v:150536$7540_Y + connect \$157 $pos$libresoc.v:150537$7542_Y + connect \$162 $sub$libresoc.v:150538$7543_Y + connect \$164 $pos$libresoc.v:150539$7545_Y + connect \$166 $ternary$libresoc.v:150540$7546_Y + connect \$161 $pos$libresoc.v:150541$7548_Y + connect \$169 $pos$libresoc.v:150542$7550_Y + connect \$171 $reduce_xor$libresoc.v:150543$7551_Y + connect \$173 $reduce_xor$libresoc.v:150544$7552_Y + connect \$176 $ternary$libresoc.v:150545$7553_Y + connect \$175 $pos$libresoc.v:150546$7555_Y + connect \$179 $ternary$libresoc.v:150547$7556_Y + connect \$21 $and$libresoc.v:150548$7557_Y + connect \$23 $or$libresoc.v:150549$7558_Y + connect \$25 $xor$libresoc.v:150550$7559_Y + connect \$27 $eq$libresoc.v:150551$7560_Y + connect \$29 $eq$libresoc.v:150552$7561_Y + connect \$31 $eq$libresoc.v:150553$7562_Y + connect \$33 $eq$libresoc.v:150554$7563_Y + connect \$35 $eq$libresoc.v:150555$7564_Y + connect \$37 $eq$libresoc.v:150556$7565_Y + connect \$39 $eq$libresoc.v:150557$7566_Y + connect \$41 $eq$libresoc.v:150558$7567_Y + connect \$43 $eq$libresoc.v:150559$7568_Y + connect \$45 $eq$libresoc.v:150560$7569_Y + connect \$47 $eq$libresoc.v:150561$7570_Y + connect \$49 $eq$libresoc.v:150562$7571_Y + connect \$51 $eq$libresoc.v:150563$7572_Y + connect \$53 $eq$libresoc.v:150564$7573_Y + connect \$55 $eq$libresoc.v:150565$7574_Y + connect \$57 $eq$libresoc.v:150566$7575_Y + connect \$59 $eq$libresoc.v:150567$7576_Y + connect \$61 $eq$libresoc.v:150568$7577_Y + connect \$63 $eq$libresoc.v:150569$7578_Y + connect \$65 $eq$libresoc.v:150570$7579_Y + connect \$67 $eq$libresoc.v:150571$7580_Y + connect \$69 $eq$libresoc.v:150572$7581_Y + connect \$71 $eq$libresoc.v:150573$7582_Y + connect \$73 $eq$libresoc.v:150574$7583_Y + connect \$75 $eq$libresoc.v:150575$7584_Y + connect \$77 $eq$libresoc.v:150576$7585_Y + connect \$79 $eq$libresoc.v:150577$7586_Y + connect \$81 $eq$libresoc.v:150578$7587_Y + connect \$83 $eq$libresoc.v:150579$7588_Y + connect \$85 $eq$libresoc.v:150580$7589_Y + connect \$87 $eq$libresoc.v:150581$7590_Y + connect \$89 $eq$libresoc.v:150582$7591_Y + connect \$91 $eq$libresoc.v:150583$7592_Y + connect \$93 $eq$libresoc.v:150584$7593_Y + connect \$95 $eq$libresoc.v:150585$7594_Y + connect \$97 $eq$libresoc.v:150586$7595_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:149160.1-149675.10" +attribute \src "libresoc.v:150792.1-151307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:149530.3-149540.6" + attribute \src "libresoc.v:151162.3-151172.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:149584.3-149594.6" + attribute \src "libresoc.v:151216.3-151226.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:149595.3-149605.6" + attribute \src "libresoc.v:151227.3-151237.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:149648.3-149658.6" + attribute \src "libresoc.v:151280.3-151290.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:149573.3-149583.6" + attribute \src "libresoc.v:151205.3-151215.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $0\cr_a$6[3:0]$7575 - attribute \src "libresoc.v:149442.3-149476.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $0\cr_a$6[3:0]$7623 + attribute \src "libresoc.v:151074.3-151108.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151173.3-151193.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149659.3-149669.6" - wire width 32 $0\full_cr$5[31:0]$7590 - attribute \src "libresoc.v:149477.3-149487.6" + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $0\full_cr$5[31:0]$7638 + attribute \src "libresoc.v:151109.3-151119.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:149161.7-149161.20" + attribute \src "libresoc.v:150793.7-150793.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149562.3-149572.6" + attribute \src "libresoc.v:151194.3-151204.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149530.3-149540.6" + attribute \src "libresoc.v:151162.3-151172.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:149584.3-149594.6" + attribute \src "libresoc.v:151216.3-151226.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:149595.3-149605.6" + attribute \src "libresoc.v:151227.3-151237.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:149648.3-149658.6" + attribute \src "libresoc.v:151280.3-151290.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:149573.3-149583.6" + attribute \src "libresoc.v:151205.3-151215.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $1\cr_a$6[3:0]$7576 - attribute \src "libresoc.v:149442.3-149476.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151074.3-151108.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151173.3-151193.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149659.3-149669.6" - wire width 32 $1\full_cr$5[31:0]$7591 - attribute \src "libresoc.v:149477.3-149487.6" + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151109.3-151119.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:149562.3-149572.6" + attribute \src "libresoc.v:151194.3-151204.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $2\cr_a$6[3:0]$7577 - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $2\cr_a$6[3:0]$7625 + attribute \src "libresoc.v:151173.3-151193.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:149438.18-149438.96" - wire width 64 $extend$libresoc.v:149438$7567_Y - attribute \src "libresoc.v:149440.18-149440.98" - wire width 65 $extend$libresoc.v:149440$7570_Y - attribute \src "libresoc.v:149441.17-149441.92" - wire width 5 $extend$libresoc.v:149441$7572_Y - attribute \src "libresoc.v:149438.18-149438.96" - wire width 64 $pos$libresoc.v:149438$7568_Y - attribute \src "libresoc.v:149440.18-149440.98" - wire width 65 $pos$libresoc.v:149440$7571_Y - attribute \src "libresoc.v:149441.17-149441.92" - wire width 5 $pos$libresoc.v:149441$7573_Y - attribute \src "libresoc.v:149432.18-149432.116" - wire width 3 $sub$libresoc.v:149432$7561_Y - attribute \src "libresoc.v:149433.18-149433.116" - wire width 3 $sub$libresoc.v:149433$7562_Y - attribute \src "libresoc.v:149434.18-149434.116" - wire width 3 $sub$libresoc.v:149434$7563_Y - attribute \src "libresoc.v:149435.18-149435.114" - wire $ternary$libresoc.v:149435$7564_Y - attribute \src "libresoc.v:149436.18-149436.115" - wire $ternary$libresoc.v:149436$7565_Y - attribute \src "libresoc.v:149437.18-149437.112" - wire $ternary$libresoc.v:149437$7566_Y - attribute \src "libresoc.v:149439.18-149439.108" - wire width 64 $ternary$libresoc.v:149439$7569_Y + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $extend$libresoc.v:151070$7615_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $extend$libresoc.v:151072$7618_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $extend$libresoc.v:151073$7620_Y + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $pos$libresoc.v:151070$7616_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $pos$libresoc.v:151072$7619_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $pos$libresoc.v:151073$7621_Y + attribute \src "libresoc.v:151064.18-151064.116" + wire width 3 $sub$libresoc.v:151064$7609_Y + attribute \src "libresoc.v:151065.18-151065.116" + wire width 3 $sub$libresoc.v:151065$7610_Y + attribute \src "libresoc.v:151066.18-151066.116" + wire width 3 $sub$libresoc.v:151066$7611_Y + attribute \src "libresoc.v:151067.18-151067.114" + wire $ternary$libresoc.v:151067$7612_Y + attribute \src "libresoc.v:151068.18-151068.115" + wire $ternary$libresoc.v:151068$7613_Y + attribute \src "libresoc.v:151069.18-151069.112" + wire $ternary$libresoc.v:151069$7614_Y + attribute \src "libresoc.v:151071.18-151071.108" + wire width 64 $ternary$libresoc.v:151071$7617_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -312951,7 +315448,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:149161.7-149161.15" + attribute \src "libresoc.v:150793.7-150793.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -312968,55 +315465,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149438$7567 + cell $pos $extend$libresoc.v:151070$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:149438$7567_Y + connect \Y $extend$libresoc.v:151070$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:149440$7570 + cell $pos $extend$libresoc.v:151072$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:149440$7570_Y + connect \Y $extend$libresoc.v:151072$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149441$7572 + cell $pos $extend$libresoc.v:151073$7620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:149441$7572_Y + connect \Y $extend$libresoc.v:151073$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149438$7568 + cell $pos $pos$libresoc.v:151070$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149438$7567_Y - connect \Y $pos$libresoc.v:149438$7568_Y + connect \A $extend$libresoc.v:151070$7615_Y + connect \Y $pos$libresoc.v:151070$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:149440$7571 + cell $pos $pos$libresoc.v:151072$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149440$7570_Y - connect \Y $pos$libresoc.v:149440$7571_Y + connect \A $extend$libresoc.v:151072$7618_Y + connect \Y $pos$libresoc.v:151072$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149441$7573 + cell $pos $pos$libresoc.v:151073$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:149441$7572_Y - connect \Y $pos$libresoc.v:149441$7573_Y + connect \A $extend$libresoc.v:151073$7620_Y + connect \Y $pos$libresoc.v:151073$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:149432$7561 + cell $sub $sub$libresoc.v:151064$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313024,10 +315521,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:149432$7561_Y + connect \Y $sub$libresoc.v:151064$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:149433$7562 + cell $sub $sub$libresoc.v:151065$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313035,10 +315532,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:149433$7562_Y + connect \Y $sub$libresoc.v:151065$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:149434$7563 + cell $sub $sub$libresoc.v:151066$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313046,59 +315543,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:149434$7563_Y + connect \Y $sub$libresoc.v:151066$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:149435$7564 + cell $mux $ternary$libresoc.v:151067$7612 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:149435$7564_Y + connect \Y $ternary$libresoc.v:151067$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:149436$7565 + cell $mux $ternary$libresoc.v:151068$7613 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:149436$7565_Y + connect \Y $ternary$libresoc.v:151068$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:149437$7566 + cell $mux $ternary$libresoc.v:151069$7614 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:149437$7566_Y + connect \Y $ternary$libresoc.v:151069$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:149439$7569 + cell $mux $ternary$libresoc.v:151071$7617 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:149439$7569_Y + connect \Y $ternary$libresoc.v:151071$7617_Y end - attribute \src "libresoc.v:149161.7-149161.20" - process $proc$libresoc.v:149161$7592 + attribute \src "libresoc.v:150793.7-150793.20" + process $proc$libresoc.v:150793$7640 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149442.3-149476.6" - process $proc$libresoc.v:149442$7574 + attribute \src "libresoc.v:151074.3-151108.6" + process $proc$libresoc.v:151074$7622 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7575 $1\cr_a$6[3:0]$7576 - attribute \src "libresoc.v:149443.5-149443.29" + assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151075.5-151075.29" switch \initial - attribute \src "libresoc.v:149443.9-149443.17" + attribute \src "libresoc.v:151075.9-151075.17" case 1'1 case end @@ -313108,52 +315605,52 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7576 \$7 [3:0] + assign $1\cr_a$6[3:0]$7624 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7576 $2\cr_a$6[3:0]$7577 + assign $1\cr_a$6[3:0]$7624 $2\cr_a$6[3:0]$7625 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7577 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7577 [0] \bit_o + assign $2\cr_a$6[3:0]$7625 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7625 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7577 [3:2] $2\cr_a$6[3:0]$7577 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7577 [1] \bit_o + assign { $2\cr_a$6[3:0]$7625 [3:2] $2\cr_a$6[3:0]$7625 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7625 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7577 [3] $2\cr_a$6[3:0]$7577 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7577 [2] \bit_o + assign { $2\cr_a$6[3:0]$7625 [3] $2\cr_a$6[3:0]$7625 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7625 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7577 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7577 [3] \bit_o + assign $2\cr_a$6[3:0]$7625 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7625 [3] \bit_o case - assign $2\cr_a$6[3:0]$7577 \cr_c + assign $2\cr_a$6[3:0]$7625 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7576 4'0000 + assign $1\cr_a$6[3:0]$7624 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7575 + update \cr_a$6 $0\cr_a$6[3:0]$7623 end - attribute \src "libresoc.v:149477.3-149487.6" - process $proc$libresoc.v:149477$7578 + attribute \src "libresoc.v:151109.3-151119.6" + process $proc$libresoc.v:151109$7626 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:149478.5-149478.29" + attribute \src "libresoc.v:151110.5-151110.29" switch \initial - attribute \src "libresoc.v:149478.9-149478.17" + attribute \src "libresoc.v:151110.9-151110.17" case 1'1 case end @@ -313169,17 +315666,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:149488.3-149529.6" - process $proc$libresoc.v:149488$7579 + attribute \src "libresoc.v:151120.3-151161.6" + process $proc$libresoc.v:151120$7627 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:149489.5-149489.29" + attribute \src "libresoc.v:151121.5-151121.29" switch \initial - attribute \src "libresoc.v:149489.9-149489.17" + attribute \src "libresoc.v:151121.9-151121.17" case 1'1 case end @@ -313226,14 +315723,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:149530.3-149540.6" - process $proc$libresoc.v:149530$7580 + attribute \src "libresoc.v:151162.3-151172.6" + process $proc$libresoc.v:151162$7628 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:149531.5-149531.29" + attribute \src "libresoc.v:151163.5-151163.29" switch \initial - attribute \src "libresoc.v:149531.9-149531.17" + attribute \src "libresoc.v:151163.9-151163.17" case 1'1 case end @@ -313249,14 +315746,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:149541.3-149561.6" - process $proc$libresoc.v:149541$7581 + attribute \src "libresoc.v:151173.3-151193.6" + process $proc$libresoc.v:151173$7629 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:149542.5-149542.29" + attribute \src "libresoc.v:151174.5-151174.29" switch \initial - attribute \src "libresoc.v:149542.9-149542.17" + attribute \src "libresoc.v:151174.9-151174.17" case 1'1 case end @@ -313293,14 +315790,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:149562.3-149572.6" - process $proc$libresoc.v:149562$7582 + attribute \src "libresoc.v:151194.3-151204.6" + process $proc$libresoc.v:151194$7630 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:149563.5-149563.29" + attribute \src "libresoc.v:151195.5-151195.29" switch \initial - attribute \src "libresoc.v:149563.9-149563.17" + attribute \src "libresoc.v:151195.9-151195.17" case 1'1 case end @@ -313316,14 +315813,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:149573.3-149583.6" - process $proc$libresoc.v:149573$7583 + attribute \src "libresoc.v:151205.3-151215.6" + process $proc$libresoc.v:151205$7631 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:149574.5-149574.29" + attribute \src "libresoc.v:151206.5-151206.29" switch \initial - attribute \src "libresoc.v:149574.9-149574.17" + attribute \src "libresoc.v:151206.9-151206.17" case 1'1 case end @@ -313339,14 +315836,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:149584.3-149594.6" - process $proc$libresoc.v:149584$7584 + attribute \src "libresoc.v:151216.3-151226.6" + process $proc$libresoc.v:151216$7632 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:149585.5-149585.29" + attribute \src "libresoc.v:151217.5-151217.29" switch \initial - attribute \src "libresoc.v:149585.9-149585.17" + attribute \src "libresoc.v:151217.9-151217.17" case 1'1 case end @@ -313362,14 +315859,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:149595.3-149605.6" - process $proc$libresoc.v:149595$7585 + attribute \src "libresoc.v:151227.3-151237.6" + process $proc$libresoc.v:151227$7633 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:149596.5-149596.29" + attribute \src "libresoc.v:151228.5-151228.29" switch \initial - attribute \src "libresoc.v:149596.9-149596.17" + attribute \src "libresoc.v:151228.9-151228.17" case 1'1 case end @@ -313385,14 +315882,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:149606.3-149626.6" - process $proc$libresoc.v:149606$7586 + attribute \src "libresoc.v:151238.3-151258.6" + process $proc$libresoc.v:151238$7634 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:149607.5-149607.29" + attribute \src "libresoc.v:151239.5-151239.29" switch \initial - attribute \src "libresoc.v:149607.9-149607.17" + attribute \src "libresoc.v:151239.9-151239.17" case 1'1 case end @@ -313429,14 +315926,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:149627.3-149647.6" - process $proc$libresoc.v:149627$7587 + attribute \src "libresoc.v:151259.3-151279.6" + process $proc$libresoc.v:151259$7635 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:149628.5-149628.29" + attribute \src "libresoc.v:151260.5-151260.29" switch \initial - attribute \src "libresoc.v:149628.9-149628.17" + attribute \src "libresoc.v:151260.9-151260.17" case 1'1 case end @@ -313473,14 +315970,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:149648.3-149658.6" - process $proc$libresoc.v:149648$7588 + attribute \src "libresoc.v:151280.3-151290.6" + process $proc$libresoc.v:151280$7636 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:149649.5-149649.29" + attribute \src "libresoc.v:151281.5-151281.29" switch \initial - attribute \src "libresoc.v:149649.9-149649.17" + attribute \src "libresoc.v:151281.9-151281.17" case 1'1 case end @@ -313496,14 +315993,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:149659.3-149669.6" - process $proc$libresoc.v:149659$7589 + attribute \src "libresoc.v:151291.3-151301.6" + process $proc$libresoc.v:151291$7637 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7590 $1\full_cr$5[31:0]$7591 - attribute \src "libresoc.v:149660.5-149660.29" + assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151292.5-151292.29" switch \initial - attribute \src "libresoc.v:149660.9-149660.17" + attribute \src "libresoc.v:151292.9-151292.17" case 1'1 case end @@ -313512,508 +316009,508 @@ module \main$9 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7591 \ra [31:0] + assign $1\full_cr$5[31:0]$7639 \ra [31:0] case - assign $1\full_cr$5[31:0]$7591 0 + assign $1\full_cr$5[31:0]$7639 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7590 + update \full_cr$5 $0\full_cr$5[31:0]$7638 end - connect \$10 $sub$libresoc.v:149432$7561_Y - connect \$13 $sub$libresoc.v:149433$7562_Y - connect \$16 $sub$libresoc.v:149434$7563_Y - connect \$18 $ternary$libresoc.v:149435$7564_Y - connect \$20 $ternary$libresoc.v:149436$7565_Y - connect \$22 $ternary$libresoc.v:149437$7566_Y - connect \$24 $pos$libresoc.v:149438$7568_Y - connect \$27 $ternary$libresoc.v:149439$7569_Y - connect \$26 $pos$libresoc.v:149440$7571_Y - connect \$7 $pos$libresoc.v:149441$7573_Y + connect \$10 $sub$libresoc.v:151064$7609_Y + connect \$13 $sub$libresoc.v:151065$7610_Y + connect \$16 $sub$libresoc.v:151066$7611_Y + connect \$18 $ternary$libresoc.v:151067$7612_Y + connect \$20 $ternary$libresoc.v:151068$7613_Y + connect \$22 $ternary$libresoc.v:151069$7614_Y + connect \$24 $pos$libresoc.v:151070$7616_Y + connect \$27 $ternary$libresoc.v:151071$7617_Y + connect \$26 $pos$libresoc.v:151072$7619_Y + connect \$7 $pos$libresoc.v:151073$7621_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:149679.1-150840.10" +attribute \src "libresoc.v:151311.1-152472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:150411.3-150412.25" + attribute \src "libresoc.v:152043.3-152044.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:150409.3-150410.40" + attribute \src "libresoc.v:152041.3-152042.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:150752.3-150760.6" - wire $0\alu_l_r_alu$next[0:0]$7798 - attribute \src "libresoc.v:150337.3-150338.39" + attribute \src "libresoc.v:152384.3-152392.6" + wire $0\alu_l_r_alu$next[0:0]$7846 + attribute \src "libresoc.v:151969.3-151970.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 - attribute \src "libresoc.v:150365.3-150366.65" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + attribute \src "libresoc.v:151997.3-151998.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 - attribute \src "libresoc.v:150367.3-150368.79" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + attribute \src "libresoc.v:151999.3-152000.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 - attribute \src "libresoc.v:150369.3-150370.75" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + attribute \src "libresoc.v:152001.3-152002.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7726 - attribute \src "libresoc.v:150385.3-150386.59" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 + attribute \src "libresoc.v:152017.3-152018.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 - attribute \src "libresoc.v:150363.3-150364.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + attribute \src "libresoc.v:151995.3-151996.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 - attribute \src "libresoc.v:150381.3-150382.67" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + attribute \src "libresoc.v:152013.3-152014.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 - attribute \src "libresoc.v:150383.3-150384.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + attribute \src "libresoc.v:152015.3-152016.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 - attribute \src "libresoc.v:150375.3-150376.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + attribute \src "libresoc.v:152007.3-152008.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 - attribute \src "libresoc.v:150377.3-150378.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + attribute \src "libresoc.v:152009.3-152010.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 - attribute \src "libresoc.v:150373.3-150374.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + attribute \src "libresoc.v:152005.3-152006.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 - attribute \src "libresoc.v:150371.3-150372.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + attribute \src "libresoc.v:152003.3-152004.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 - attribute \src "libresoc.v:150379.3-150380.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + attribute \src "libresoc.v:152011.3-152012.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:150743.3-150751.6" - wire $0\alui_l_r_alui$next[0:0]$7795 - attribute \src "libresoc.v:150339.3-150340.43" + attribute \src "libresoc.v:152375.3-152383.6" + wire $0\alui_l_r_alui$next[0:0]$7843 + attribute \src "libresoc.v:151971.3-151972.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $0\data_r0__o$next[63:0]$7754 - attribute \src "libresoc.v:150359.3-150360.37" + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $0\data_r0__o$next[63:0]$7802 + attribute \src "libresoc.v:151991.3-151992.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire $0\data_r0__o_ok$next[0:0]$7755 - attribute \src "libresoc.v:150361.3-150362.43" + attribute \src "libresoc.v:152257.3-152278.6" + wire $0\data_r0__o_ok$next[0:0]$7803 + attribute \src "libresoc.v:151993.3-151994.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7762 - attribute \src "libresoc.v:150355.3-150356.43" + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7810 + attribute \src "libresoc.v:151987.3-151988.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7763 - attribute \src "libresoc.v:150357.3-150358.49" + attribute \src "libresoc.v:152279.3-152300.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7811 + attribute \src "libresoc.v:151989.3-151990.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7770 - attribute \src "libresoc.v:150351.3-150352.47" + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 + attribute \src "libresoc.v:151983.3-151984.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7771 - attribute \src "libresoc.v:150353.3-150354.53" + attribute \src "libresoc.v:152301.3-152322.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7819 + attribute \src "libresoc.v:151985.3-151986.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $0\data_r3__xer_so$next[0:0]$7778 - attribute \src "libresoc.v:150347.3-150348.47" + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so$next[0:0]$7826 + attribute \src "libresoc.v:151979.3-151980.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7779 - attribute \src "libresoc.v:150349.3-150350.53" + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7827 + attribute \src "libresoc.v:151981.3-151982.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:150761.3-150770.6" + attribute \src "libresoc.v:152393.3-152402.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:150771.3-150780.6" + attribute \src "libresoc.v:152403.3-152412.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:150781.3-150790.6" + attribute \src "libresoc.v:152413.3-152422.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:150791.3-150800.6" + attribute \src "libresoc.v:152423.3-152432.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:149680.7-149680.20" + attribute \src "libresoc.v:151312.7-151312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150547.3-150555.6" - wire $0\opc_l_r_opc$next[0:0]$7708 - attribute \src "libresoc.v:150395.3-150396.39" + attribute \src "libresoc.v:152179.3-152187.6" + wire $0\opc_l_r_opc$next[0:0]$7756 + attribute \src "libresoc.v:152027.3-152028.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:150538.3-150546.6" - wire $0\opc_l_s_opc$next[0:0]$7705 - attribute \src "libresoc.v:150397.3-150398.39" + attribute \src "libresoc.v:152170.3-152178.6" + wire $0\opc_l_s_opc$next[0:0]$7753 + attribute \src "libresoc.v:152029.3-152030.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:150801.3-150809.6" - wire width 4 $0\prev_wr_go$next[3:0]$7805 - attribute \src "libresoc.v:150407.3-150408.37" + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $0\prev_wr_go$next[3:0]$7853 + attribute \src "libresoc.v:152039.3-152040.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:150492.3-150501.6" + attribute \src "libresoc.v:152124.3-152133.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:150583.3-150591.6" - wire width 4 $0\req_l_r_req$next[3:0]$7720 - attribute \src "libresoc.v:150387.3-150388.39" + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $0\req_l_r_req$next[3:0]$7768 + attribute \src "libresoc.v:152019.3-152020.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:150574.3-150582.6" - wire width 4 $0\req_l_s_req$next[3:0]$7717 - attribute \src "libresoc.v:150389.3-150390.39" + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $0\req_l_s_req$next[3:0]$7765 + attribute \src "libresoc.v:152021.3-152022.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:150511.3-150519.6" - wire $0\rok_l_r_rdok$next[0:0]$7696 - attribute \src "libresoc.v:150403.3-150404.41" + attribute \src "libresoc.v:152143.3-152151.6" + wire $0\rok_l_r_rdok$next[0:0]$7744 + attribute \src "libresoc.v:152035.3-152036.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:150502.3-150510.6" - wire $0\rok_l_s_rdok$next[0:0]$7693 - attribute \src "libresoc.v:150405.3-150406.41" + attribute \src "libresoc.v:152134.3-152142.6" + wire $0\rok_l_s_rdok$next[0:0]$7741 + attribute \src "libresoc.v:152037.3-152038.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:150529.3-150537.6" - wire $0\rst_l_r_rst$next[0:0]$7702 - attribute \src "libresoc.v:150399.3-150400.39" + attribute \src "libresoc.v:152161.3-152169.6" + wire $0\rst_l_r_rst$next[0:0]$7750 + attribute \src "libresoc.v:152031.3-152032.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:150520.3-150528.6" - wire $0\rst_l_s_rst$next[0:0]$7699 - attribute \src "libresoc.v:150401.3-150402.39" + attribute \src "libresoc.v:152152.3-152160.6" + wire $0\rst_l_s_rst$next[0:0]$7747 + attribute \src "libresoc.v:152033.3-152034.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:150565.3-150573.6" - wire width 3 $0\src_l_r_src$next[2:0]$7714 - attribute \src "libresoc.v:150391.3-150392.39" + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $0\src_l_r_src$next[2:0]$7762 + attribute \src "libresoc.v:152023.3-152024.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:150556.3-150564.6" - wire width 3 $0\src_l_s_src$next[2:0]$7711 - attribute \src "libresoc.v:150393.3-150394.39" + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $0\src_l_s_src$next[2:0]$7759 + attribute \src "libresoc.v:152025.3-152026.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:150713.3-150722.6" - wire width 64 $0\src_r0$next[63:0]$7786 - attribute \src "libresoc.v:150345.3-150346.29" + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $0\src_r0$next[63:0]$7834 + attribute \src "libresoc.v:151977.3-151978.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:150723.3-150732.6" - wire width 64 $0\src_r1$next[63:0]$7789 - attribute \src "libresoc.v:150343.3-150344.29" + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $0\src_r1$next[63:0]$7837 + attribute \src "libresoc.v:151975.3-151976.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:150733.3-150742.6" - wire $0\src_r2$next[0:0]$7792 - attribute \src "libresoc.v:150341.3-150342.29" + attribute \src "libresoc.v:152365.3-152374.6" + wire $0\src_r2$next[0:0]$7840 + attribute \src "libresoc.v:151973.3-151974.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:149804.7-149804.24" + attribute \src "libresoc.v:151436.7-151436.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:149814.7-149814.26" + attribute \src "libresoc.v:151446.7-151446.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:150752.3-150760.6" - wire $1\alu_l_r_alu$next[0:0]$7799 - attribute \src "libresoc.v:149822.7-149822.25" + attribute \src "libresoc.v:152384.3-152392.6" + wire $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:151454.7-151454.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 - attribute \src "libresoc.v:149845.14-149845.49" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + attribute \src "libresoc.v:151477.14-151477.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 - attribute \src "libresoc.v:149849.14-149849.68" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + attribute \src "libresoc.v:151481.14-151481.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 - attribute \src "libresoc.v:149853.7-149853.43" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + attribute \src "libresoc.v:151485.7-151485.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7738 - attribute \src "libresoc.v:149857.14-149857.43" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + attribute \src "libresoc.v:151489.14-151489.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 - attribute \src "libresoc.v:149936.13-149936.47" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + attribute \src "libresoc.v:151568.13-151568.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 - attribute \src "libresoc.v:149940.7-149940.39" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + attribute \src "libresoc.v:151572.7-151572.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 - attribute \src "libresoc.v:149944.7-149944.40" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + attribute \src "libresoc.v:151576.7-151576.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 - attribute \src "libresoc.v:149948.7-149948.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + attribute \src "libresoc.v:151580.7-151580.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 - attribute \src "libresoc.v:149952.7-149952.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + attribute \src "libresoc.v:151584.7-151584.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 - attribute \src "libresoc.v:149956.7-149956.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + attribute \src "libresoc.v:151588.7-151588.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 - attribute \src "libresoc.v:149960.7-149960.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + attribute \src "libresoc.v:151592.7-151592.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 - attribute \src "libresoc.v:149964.7-149964.40" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + attribute \src "libresoc.v:151596.7-151596.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:150743.3-150751.6" - wire $1\alui_l_r_alui$next[0:0]$7796 - attribute \src "libresoc.v:149994.7-149994.27" + attribute \src "libresoc.v:152375.3-152383.6" + wire $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:151626.7-151626.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $1\data_r0__o$next[63:0]$7756 - attribute \src "libresoc.v:150028.14-150028.47" + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $1\data_r0__o$next[63:0]$7804 + attribute \src "libresoc.v:151660.14-151660.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire $1\data_r0__o_ok$next[0:0]$7757 - attribute \src "libresoc.v:150032.7-150032.27" + attribute \src "libresoc.v:152257.3-152278.6" + wire $1\data_r0__o_ok$next[0:0]$7805 + attribute \src "libresoc.v:151664.7-151664.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7764 - attribute \src "libresoc.v:150036.13-150036.33" + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7812 + attribute \src "libresoc.v:151668.13-151668.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7765 - attribute \src "libresoc.v:150040.7-150040.30" + attribute \src "libresoc.v:152279.3-152300.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7813 + attribute \src "libresoc.v:151672.7-151672.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7772 - attribute \src "libresoc.v:150044.13-150044.35" + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 + attribute \src "libresoc.v:151676.13-151676.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7773 - attribute \src "libresoc.v:150048.7-150048.32" + attribute \src "libresoc.v:152301.3-152322.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7821 + attribute \src "libresoc.v:151680.7-151680.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $1\data_r3__xer_so$next[0:0]$7780 - attribute \src "libresoc.v:150052.7-150052.29" + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so$next[0:0]$7828 + attribute \src "libresoc.v:151684.7-151684.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7781 - attribute \src "libresoc.v:150056.7-150056.32" + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7829 + attribute \src "libresoc.v:151688.7-151688.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:150761.3-150770.6" + attribute \src "libresoc.v:152393.3-152402.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:150771.3-150780.6" + attribute \src "libresoc.v:152403.3-152412.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:150781.3-150790.6" + attribute \src "libresoc.v:152413.3-152422.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:150791.3-150800.6" + attribute \src "libresoc.v:152423.3-152432.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:150547.3-150555.6" - wire $1\opc_l_r_opc$next[0:0]$7709 - attribute \src "libresoc.v:150076.7-150076.25" + attribute \src "libresoc.v:152179.3-152187.6" + wire $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:151708.7-151708.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:150538.3-150546.6" - wire $1\opc_l_s_opc$next[0:0]$7706 - attribute \src "libresoc.v:150080.7-150080.25" + attribute \src "libresoc.v:152170.3-152178.6" + wire $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:151712.7-151712.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:150801.3-150809.6" - wire width 4 $1\prev_wr_go$next[3:0]$7806 - attribute \src "libresoc.v:150198.13-150198.30" + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $1\prev_wr_go$next[3:0]$7854 + attribute \src "libresoc.v:151830.13-151830.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:150492.3-150501.6" + attribute \src "libresoc.v:152124.3-152133.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:150583.3-150591.6" - wire width 4 $1\req_l_r_req$next[3:0]$7721 - attribute \src "libresoc.v:150206.13-150206.31" + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:151838.13-151838.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:150574.3-150582.6" - wire width 4 $1\req_l_s_req$next[3:0]$7718 - attribute \src "libresoc.v:150210.13-150210.31" + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:151842.13-151842.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:150511.3-150519.6" - wire $1\rok_l_r_rdok$next[0:0]$7697 - attribute \src "libresoc.v:150222.7-150222.26" + attribute \src "libresoc.v:152143.3-152151.6" + wire $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:151854.7-151854.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:150502.3-150510.6" - wire $1\rok_l_s_rdok$next[0:0]$7694 - attribute \src "libresoc.v:150226.7-150226.26" + attribute \src "libresoc.v:152134.3-152142.6" + wire $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:151858.7-151858.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:150529.3-150537.6" - wire $1\rst_l_r_rst$next[0:0]$7703 - attribute \src "libresoc.v:150230.7-150230.25" + attribute \src "libresoc.v:152161.3-152169.6" + wire $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:151862.7-151862.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:150520.3-150528.6" - wire $1\rst_l_s_rst$next[0:0]$7700 - attribute \src "libresoc.v:150234.7-150234.25" + attribute \src "libresoc.v:152152.3-152160.6" + wire $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:151866.7-151866.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:150565.3-150573.6" - wire width 3 $1\src_l_r_src$next[2:0]$7715 - attribute \src "libresoc.v:150248.13-150248.31" + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:151880.13-151880.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:150556.3-150564.6" - wire width 3 $1\src_l_s_src$next[2:0]$7712 - attribute \src "libresoc.v:150252.13-150252.31" + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:151884.13-151884.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:150713.3-150722.6" - wire width 64 $1\src_r0$next[63:0]$7787 - attribute \src "libresoc.v:150258.14-150258.43" + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:151890.14-151890.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:150723.3-150732.6" - wire width 64 $1\src_r1$next[63:0]$7790 - attribute \src "libresoc.v:150262.14-150262.43" + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:151894.14-151894.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:150733.3-150742.6" - wire $1\src_r2$next[0:0]$7793 - attribute \src "libresoc.v:150266.7-150266.20" + attribute \src "libresoc.v:152365.3-152374.6" + wire $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:151898.7-151898.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $2\data_r0__o$next[63:0]$7758 - attribute \src "libresoc.v:150625.3-150646.6" - wire $2\data_r0__o_ok$next[0:0]$7759 - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7766 - attribute \src "libresoc.v:150647.3-150668.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7767 - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7774 - attribute \src "libresoc.v:150669.3-150690.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7775 - attribute \src "libresoc.v:150691.3-150712.6" - wire $2\data_r3__xer_so$next[0:0]$7782 - attribute \src "libresoc.v:150691.3-150712.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7783 - attribute \src "libresoc.v:150625.3-150646.6" - wire $3\data_r0__o_ok$next[0:0]$7760 - attribute \src "libresoc.v:150647.3-150668.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7768 - attribute \src "libresoc.v:150669.3-150690.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7776 - attribute \src "libresoc.v:150691.3-150712.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7784 - attribute \src "libresoc.v:150277.19-150277.113" - wire width 3 $and$libresoc.v:150277$7593_Y - attribute \src "libresoc.v:150278.19-150278.125" - wire $and$libresoc.v:150278$7594_Y - attribute \src "libresoc.v:150279.19-150279.125" - wire $and$libresoc.v:150279$7595_Y - attribute \src "libresoc.v:150280.19-150280.125" - wire $and$libresoc.v:150280$7596_Y - attribute \src "libresoc.v:150281.19-150281.125" - wire $and$libresoc.v:150281$7597_Y - attribute \src "libresoc.v:150282.18-150282.110" - wire $and$libresoc.v:150282$7598_Y - attribute \src "libresoc.v:150283.19-150283.149" - wire width 4 $and$libresoc.v:150283$7599_Y - attribute \src "libresoc.v:150284.19-150284.121" - wire width 4 $and$libresoc.v:150284$7600_Y - attribute \src "libresoc.v:150285.19-150285.127" - wire $and$libresoc.v:150285$7601_Y - attribute \src "libresoc.v:150286.19-150286.127" - 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$and$libresoc.v:150307$7623_Y - attribute \src "libresoc.v:150309.18-150309.126" - wire $and$libresoc.v:150309$7625_Y - attribute \src "libresoc.v:150310.18-150310.126" - wire $and$libresoc.v:150310$7626_Y - attribute \src "libresoc.v:150311.18-150311.117" - wire $and$libresoc.v:150311$7627_Y - attribute \src "libresoc.v:150317.18-150317.130" - wire $and$libresoc.v:150317$7633_Y - attribute \src "libresoc.v:150318.18-150318.124" - wire width 4 $and$libresoc.v:150318$7634_Y - attribute \src "libresoc.v:150320.18-150320.116" - wire $and$libresoc.v:150320$7636_Y - attribute \src "libresoc.v:150321.18-150321.119" - wire $and$libresoc.v:150321$7637_Y - attribute \src "libresoc.v:150322.18-150322.121" - wire $and$libresoc.v:150322$7638_Y - attribute \src "libresoc.v:150323.18-150323.121" - wire $and$libresoc.v:150323$7639_Y - attribute \src "libresoc.v:150330.18-150330.134" - wire $and$libresoc.v:150330$7646_Y - attribute \src "libresoc.v:150332.18-150332.132" - wire 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$and$libresoc.v:151931$7663_Y + attribute \src "libresoc.v:151936.18-151936.113" + wire $and$libresoc.v:151936$7668_Y + attribute \src "libresoc.v:151937.18-151937.125" + wire width 4 $and$libresoc.v:151937$7669_Y + attribute \src "libresoc.v:151939.18-151939.112" + wire $and$libresoc.v:151939$7671_Y + attribute \src "libresoc.v:151941.18-151941.126" + wire $and$libresoc.v:151941$7673_Y + attribute \src "libresoc.v:151942.18-151942.126" + wire $and$libresoc.v:151942$7674_Y + attribute \src "libresoc.v:151943.18-151943.117" + wire $and$libresoc.v:151943$7675_Y + attribute \src "libresoc.v:151949.18-151949.130" + wire $and$libresoc.v:151949$7681_Y + attribute \src "libresoc.v:151950.18-151950.124" + wire width 4 $and$libresoc.v:151950$7682_Y + attribute \src "libresoc.v:151952.18-151952.116" + wire $and$libresoc.v:151952$7684_Y + attribute \src "libresoc.v:151953.18-151953.119" + wire $and$libresoc.v:151953$7685_Y + attribute \src "libresoc.v:151954.18-151954.121" + wire $and$libresoc.v:151954$7686_Y + attribute \src "libresoc.v:151955.18-151955.121" + wire $and$libresoc.v:151955$7687_Y + attribute \src "libresoc.v:151962.18-151962.134" + wire $and$libresoc.v:151962$7694_Y + attribute \src "libresoc.v:151964.18-151964.132" + wire $and$libresoc.v:151964$7696_Y + attribute \src "libresoc.v:151965.18-151965.149" + wire width 3 $and$libresoc.v:151965$7697_Y + attribute \src "libresoc.v:151967.18-151967.129" + wire width 3 $and$libresoc.v:151967$7699_Y + attribute \src "libresoc.v:151938.18-151938.113" + wire $eq$libresoc.v:151938$7670_Y + attribute \src "libresoc.v:151940.18-151940.119" + wire $eq$libresoc.v:151940$7672_Y + attribute \src "libresoc.v:151921.18-151921.97" + wire $not$libresoc.v:151921$7653_Y + attribute \src "libresoc.v:151923.18-151923.99" + wire $not$libresoc.v:151923$7655_Y + attribute \src "libresoc.v:151926.18-151926.113" + wire width 4 $not$libresoc.v:151926$7658_Y + attribute \src "libresoc.v:151929.18-151929.106" + wire $not$libresoc.v:151929$7661_Y + attribute \src "libresoc.v:151935.18-151935.120" + wire $not$libresoc.v:151935$7667_Y + attribute \src "libresoc.v:151946.17-151946.113" + wire width 3 $not$libresoc.v:151946$7678_Y + attribute \src "libresoc.v:151966.18-151966.131" + wire $not$libresoc.v:151966$7698_Y + attribute \src "libresoc.v:151968.18-151968.114" + wire width 3 $not$libresoc.v:151968$7700_Y + attribute \src "libresoc.v:151934.18-151934.112" + wire $or$libresoc.v:151934$7666_Y + attribute \src "libresoc.v:151944.18-151944.122" + wire $or$libresoc.v:151944$7676_Y + attribute \src "libresoc.v:151945.18-151945.124" + wire $or$libresoc.v:151945$7677_Y + attribute \src "libresoc.v:151947.18-151947.168" + wire width 4 $or$libresoc.v:151947$7679_Y + attribute \src "libresoc.v:151948.18-151948.155" + wire width 3 $or$libresoc.v:151948$7680_Y + attribute \src "libresoc.v:151951.18-151951.120" + wire width 4 $or$libresoc.v:151951$7683_Y + attribute \src "libresoc.v:151957.17-151957.117" + wire width 3 $or$libresoc.v:151957$7689_Y + attribute \src "libresoc.v:151963.17-151963.104" + wire $reduce_and$libresoc.v:151963$7695_Y + attribute \src "libresoc.v:151928.18-151928.106" + wire $reduce_or$libresoc.v:151928$7660_Y + attribute \src "libresoc.v:151932.18-151932.113" + wire $reduce_or$libresoc.v:151932$7664_Y + attribute \src "libresoc.v:151933.18-151933.112" + wire $reduce_or$libresoc.v:151933$7665_Y + attribute \src "libresoc.v:151956.18-151956.160" + wire $ternary$libresoc.v:151956$7688_Y + attribute \src "libresoc.v:151958.18-151958.172" + wire width 64 $ternary$libresoc.v:151958$7690_Y + attribute \src "libresoc.v:151959.18-151959.118" + wire width 64 $ternary$libresoc.v:151959$7691_Y + attribute \src "libresoc.v:151960.18-151960.115" + wire width 64 $ternary$libresoc.v:151960$7692_Y + attribute \src "libresoc.v:151961.18-151961.118" + wire $ternary$libresoc.v:151961$7693_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -314332,9 +316829,9 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok @@ -314400,7 +316897,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:149680.7-149680.15" + attribute \src "libresoc.v:151312.7-151312.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok @@ -314609,7 +317106,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150277$7593 + cell $and $and$libresoc.v:151909$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314617,10 +317114,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:150277$7593_Y + connect \Y $and$libresoc.v:151909$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150278$7594 + cell $and $and$libresoc.v:151910$7642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314628,10 +317125,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150278$7594_Y + connect \Y $and$libresoc.v:151910$7642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150279$7595 + cell $and $and$libresoc.v:151911$7643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314639,10 +317136,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150279$7595_Y + connect \Y $and$libresoc.v:151911$7643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150280$7596 + cell $and $and$libresoc.v:151912$7644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314650,10 +317147,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150280$7596_Y + connect \Y $and$libresoc.v:151912$7644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150281$7597 + cell $and $and$libresoc.v:151913$7645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314661,10 +317158,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150281$7597_Y + connect \Y $and$libresoc.v:151913$7645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:150282$7598 + cell $and $and$libresoc.v:151914$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314672,10 +317169,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:150282$7598_Y + connect \Y $and$libresoc.v:151914$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:150283$7599 + cell $and $and$libresoc.v:151915$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314683,10 +317180,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:150283$7599_Y + connect \Y $and$libresoc.v:151915$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:150284$7600 + cell $and $and$libresoc.v:151916$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314694,10 +317191,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150284$7600_Y + connect \Y $and$libresoc.v:151916$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150285$7601 + cell $and $and$libresoc.v:151917$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314705,10 +317202,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150285$7601_Y + connect \Y $and$libresoc.v:151917$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150286$7602 + cell $and $and$libresoc.v:151918$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314716,10 +317213,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150286$7602_Y + connect \Y $and$libresoc.v:151918$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150287$7603 + cell $and $and$libresoc.v:151919$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314727,10 +317224,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150287$7603_Y + connect \Y $and$libresoc.v:151919$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150288$7604 + cell $and $and$libresoc.v:151920$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314738,10 +317235,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150288$7604_Y + connect \Y $and$libresoc.v:151920$7652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:150290$7606 + cell $and $and$libresoc.v:151922$7654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314749,10 +317246,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:150290$7606_Y + connect \Y $and$libresoc.v:151922$7654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:150292$7608 + cell $and $and$libresoc.v:151924$7656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314760,10 +317257,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:150292$7608_Y + connect \Y $and$libresoc.v:151924$7656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:150293$7609 + cell $and $and$libresoc.v:151925$7657 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314771,10 +317268,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:150293$7609_Y + connect \Y $and$libresoc.v:151925$7657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:150295$7611 + cell $and $and$libresoc.v:151927$7659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314782,10 +317279,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:150295$7611_Y + connect \Y $and$libresoc.v:151927$7659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:150298$7614 + cell $and $and$libresoc.v:151930$7662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314793,10 +317290,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:150298$7614_Y + connect \Y $and$libresoc.v:151930$7662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:150299$7615 + cell $and $and$libresoc.v:151931$7663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314804,10 +317301,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:150299$7615_Y + connect \Y $and$libresoc.v:151931$7663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:150304$7620 + cell $and $and$libresoc.v:151936$7668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314815,10 +317312,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:150304$7620_Y + connect \Y $and$libresoc.v:151936$7668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:150305$7621 + cell $and $and$libresoc.v:151937$7669 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314826,10 +317323,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150305$7621_Y + connect \Y $and$libresoc.v:151937$7669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:150307$7623 + cell $and $and$libresoc.v:151939$7671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314837,10 +317334,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:150307$7623_Y + connect \Y $and$libresoc.v:151939$7671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150309$7625 + cell $and $and$libresoc.v:151941$7673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314848,10 +317345,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:150309$7625_Y + connect \Y $and$libresoc.v:151941$7673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150310$7626 + cell $and $and$libresoc.v:151942$7674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314859,10 +317356,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:150310$7626_Y + connect \Y $and$libresoc.v:151942$7674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150311$7627 + cell $and $and$libresoc.v:151943$7675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314870,10 +317367,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:150311$7627_Y + connect \Y $and$libresoc.v:151943$7675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:150317$7633 + cell $and $and$libresoc.v:151949$7681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314881,10 +317378,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:150317$7633_Y + connect \Y $and$libresoc.v:151949$7681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:150318$7634 + cell $and $and$libresoc.v:151950$7682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314892,10 +317389,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150318$7634_Y + connect \Y $and$libresoc.v:151950$7682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150320$7636 + cell $and $and$libresoc.v:151952$7684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314903,10 +317400,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150320$7636_Y + connect \Y $and$libresoc.v:151952$7684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150321$7637 + cell $and $and$libresoc.v:151953$7685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314914,10 +317411,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150321$7637_Y + connect \Y $and$libresoc.v:151953$7685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150322$7638 + cell $and $and$libresoc.v:151954$7686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314925,10 +317422,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150322$7638_Y + connect \Y $and$libresoc.v:151954$7686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150323$7639 + cell $and $and$libresoc.v:151955$7687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314936,10 +317433,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150323$7639_Y + connect \Y $and$libresoc.v:151955$7687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:150330$7646 + cell $and $and$libresoc.v:151962$7694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314947,10 +317444,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:150330$7646_Y + connect \Y $and$libresoc.v:151962$7694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:150332$7648 + cell $and $and$libresoc.v:151964$7696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314958,10 +317455,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:150332$7648_Y + connect \Y $and$libresoc.v:151964$7696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150333$7649 + cell $and $and$libresoc.v:151965$7697 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314969,10 +317466,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:150333$7649_Y + connect \Y $and$libresoc.v:151965$7697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150335$7651 + cell $and $and$libresoc.v:151967$7699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314980,10 +317477,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:150335$7651_Y + connect \Y $and$libresoc.v:151967$7699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:150306$7622 + cell $eq $eq$libresoc.v:151938$7670 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314991,10 +317488,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:150306$7622_Y + connect \Y $eq$libresoc.v:151938$7670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:150308$7624 + cell $eq $eq$libresoc.v:151940$7672 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315002,74 +317499,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:150308$7624_Y + connect \Y $eq$libresoc.v:151940$7672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:150289$7605 + cell $not $not$libresoc.v:151921$7653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:150289$7605_Y + connect \Y $not$libresoc.v:151921$7653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:150291$7607 + cell $not $not$libresoc.v:151923$7655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:150291$7607_Y + connect \Y $not$libresoc.v:151923$7655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:150294$7610 + cell $not $not$libresoc.v:151926$7658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:150294$7610_Y + connect \Y $not$libresoc.v:151926$7658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:150297$7613 + cell $not $not$libresoc.v:151929$7661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:150297$7613_Y + connect \Y $not$libresoc.v:151929$7661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:150303$7619 + cell $not $not$libresoc.v:151935$7667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:150303$7619_Y + connect \Y $not$libresoc.v:151935$7667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:150314$7630 + cell $not $not$libresoc.v:151946$7678 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:150314$7630_Y + connect \Y $not$libresoc.v:151946$7678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:150334$7650 + cell $not $not$libresoc.v:151966$7698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:150334$7650_Y + connect \Y $not$libresoc.v:151966$7698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:150336$7652 + cell $not $not$libresoc.v:151968$7700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:150336$7652_Y + connect \Y $not$libresoc.v:151968$7700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:150302$7618 + cell $or $or$libresoc.v:151934$7666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315077,10 +317574,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:150302$7618_Y + connect \Y $or$libresoc.v:151934$7666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:150312$7628 + cell $or $or$libresoc.v:151944$7676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315088,10 +317585,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:150312$7628_Y + connect \Y $or$libresoc.v:151944$7676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:150313$7629 + cell $or $or$libresoc.v:151945$7677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315099,10 +317596,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:150313$7629_Y + connect \Y $or$libresoc.v:151945$7677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:150315$7631 + cell $or $or$libresoc.v:151947$7679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315110,10 +317607,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:150315$7631_Y + connect \Y $or$libresoc.v:151947$7679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:150316$7632 + cell $or $or$libresoc.v:151948$7680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -315121,10 +317618,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:150316$7632_Y + connect \Y $or$libresoc.v:151948$7680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:150319$7635 + cell $or $or$libresoc.v:151951$7683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315132,10 +317629,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:150319$7635_Y + connect \Y $or$libresoc.v:151951$7683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:150325$7641 + cell $or $or$libresoc.v:151957$7689 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -315143,82 +317640,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:150325$7641_Y + connect \Y $or$libresoc.v:151957$7689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:150331$7647 + cell $reduce_and $reduce_and$libresoc.v:151963$7695 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:150331$7647_Y + connect \Y $reduce_and$libresoc.v:151963$7695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:150296$7612 + cell $reduce_or $reduce_or$libresoc.v:151928$7660 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:150296$7612_Y + connect \Y $reduce_or$libresoc.v:151928$7660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:150300$7616 + cell $reduce_or $reduce_or$libresoc.v:151932$7664 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:150300$7616_Y + connect \Y $reduce_or$libresoc.v:151932$7664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:150301$7617 + cell $reduce_or $reduce_or$libresoc.v:151933$7665 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:150301$7617_Y + connect \Y $reduce_or$libresoc.v:151933$7665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:150324$7640 + cell $mux $ternary$libresoc.v:151956$7688 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:150324$7640_Y + connect \Y $ternary$libresoc.v:151956$7688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:150326$7642 + cell $mux $ternary$libresoc.v:151958$7690 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:150326$7642_Y + connect \Y $ternary$libresoc.v:151958$7690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150327$7643 + cell $mux $ternary$libresoc.v:151959$7691 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:150327$7643_Y + connect \Y $ternary$libresoc.v:151959$7691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150328$7644 + cell $mux $ternary$libresoc.v:151960$7692 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:150328$7644_Y + connect \Y $ternary$libresoc.v:151960$7692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150329$7645 + cell $mux $ternary$libresoc.v:151961$7693 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:150329$7645_Y + connect \Y $ternary$libresoc.v:151961$7693_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150413.15-150419.4" + attribute \src "libresoc.v:152045.15-152051.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315227,7 +317724,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:150420.12-150450.4" + attribute \src "libresoc.v:152052.12-152082.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315260,7 +317757,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:150451.16-150457.4" + attribute \src "libresoc.v:152083.16-152089.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315269,7 +317766,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:150458.15-150464.4" + attribute \src "libresoc.v:152090.15-152096.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315278,7 +317775,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:150465.15-150471.4" + attribute \src "libresoc.v:152097.15-152103.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315287,7 +317784,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:150472.15-150478.4" + attribute \src "libresoc.v:152104.15-152110.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315296,7 +317793,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:150479.15-150484.4" + attribute \src "libresoc.v:152111.15-152116.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315304,7 +317801,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:150485.15-150491.4" + attribute \src "libresoc.v:152117.15-152123.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315312,592 +317809,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:149680.7-149680.20" - process $proc$libresoc.v:149680$7807 + attribute \src "libresoc.v:151312.7-151312.20" + process $proc$libresoc.v:151312$7855 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149804.7-149804.24" - process $proc$libresoc.v:149804$7808 + attribute \src "libresoc.v:151436.7-151436.24" + process $proc$libresoc.v:151436$7856 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:149814.7-149814.26" - process $proc$libresoc.v:149814$7809 + attribute \src "libresoc.v:151446.7-151446.26" + process $proc$libresoc.v:151446$7857 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:149822.7-149822.25" - process $proc$libresoc.v:149822$7810 + attribute \src "libresoc.v:151454.7-151454.25" + process $proc$libresoc.v:151454$7858 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:149845.14-149845.49" - process $proc$libresoc.v:149845$7811 + attribute \src "libresoc.v:151477.14-151477.49" + process $proc$libresoc.v:151477$7859 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:149849.14-149849.68" - process $proc$libresoc.v:149849$7812 + attribute \src "libresoc.v:151481.14-151481.68" + process $proc$libresoc.v:151481$7860 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:149853.7-149853.43" - process $proc$libresoc.v:149853$7813 + attribute \src "libresoc.v:151485.7-151485.43" + process $proc$libresoc.v:151485$7861 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:149857.14-149857.43" - process $proc$libresoc.v:149857$7814 + attribute \src "libresoc.v:151489.14-151489.43" + process $proc$libresoc.v:151489$7862 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:149936.13-149936.47" - process $proc$libresoc.v:149936$7815 + attribute \src "libresoc.v:151568.13-151568.47" + process $proc$libresoc.v:151568$7863 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:149940.7-149940.39" - process $proc$libresoc.v:149940$7816 + attribute \src "libresoc.v:151572.7-151572.39" + process $proc$libresoc.v:151572$7864 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:149944.7-149944.40" - process $proc$libresoc.v:149944$7817 + attribute \src "libresoc.v:151576.7-151576.40" + process $proc$libresoc.v:151576$7865 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:149948.7-149948.37" - process $proc$libresoc.v:149948$7818 + attribute \src "libresoc.v:151580.7-151580.37" + process $proc$libresoc.v:151580$7866 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:149952.7-149952.37" - process $proc$libresoc.v:149952$7819 + attribute \src "libresoc.v:151584.7-151584.37" + process $proc$libresoc.v:151584$7867 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:149956.7-149956.37" - process $proc$libresoc.v:149956$7820 + attribute \src "libresoc.v:151588.7-151588.37" + process $proc$libresoc.v:151588$7868 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:149960.7-149960.37" - process $proc$libresoc.v:149960$7821 + attribute \src "libresoc.v:151592.7-151592.37" + process $proc$libresoc.v:151592$7869 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:149964.7-149964.40" - process $proc$libresoc.v:149964$7822 + attribute \src "libresoc.v:151596.7-151596.40" + process $proc$libresoc.v:151596$7870 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:149994.7-149994.27" - process $proc$libresoc.v:149994$7823 + attribute \src "libresoc.v:151626.7-151626.27" + process $proc$libresoc.v:151626$7871 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:150028.14-150028.47" - process $proc$libresoc.v:150028$7824 + attribute \src "libresoc.v:151660.14-151660.47" + process $proc$libresoc.v:151660$7872 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:150032.7-150032.27" - process $proc$libresoc.v:150032$7825 + attribute \src "libresoc.v:151664.7-151664.27" + process $proc$libresoc.v:151664$7873 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:150036.13-150036.33" - process $proc$libresoc.v:150036$7826 + attribute \src "libresoc.v:151668.13-151668.33" + process $proc$libresoc.v:151668$7874 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:150040.7-150040.30" - process $proc$libresoc.v:150040$7827 + attribute \src "libresoc.v:151672.7-151672.30" + process $proc$libresoc.v:151672$7875 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:150044.13-150044.35" - process $proc$libresoc.v:150044$7828 + attribute \src "libresoc.v:151676.13-151676.35" + process $proc$libresoc.v:151676$7876 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:150048.7-150048.32" - process $proc$libresoc.v:150048$7829 + attribute \src "libresoc.v:151680.7-151680.32" + process $proc$libresoc.v:151680$7877 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:150052.7-150052.29" - process $proc$libresoc.v:150052$7830 + attribute \src "libresoc.v:151684.7-151684.29" + process $proc$libresoc.v:151684$7878 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:150056.7-150056.32" - process $proc$libresoc.v:150056$7831 + attribute \src "libresoc.v:151688.7-151688.32" + process $proc$libresoc.v:151688$7879 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:150076.7-150076.25" - process $proc$libresoc.v:150076$7832 + attribute \src "libresoc.v:151708.7-151708.25" + process $proc$libresoc.v:151708$7880 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:150080.7-150080.25" - process $proc$libresoc.v:150080$7833 + attribute \src "libresoc.v:151712.7-151712.25" + process $proc$libresoc.v:151712$7881 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:150198.13-150198.30" - process $proc$libresoc.v:150198$7834 + attribute \src "libresoc.v:151830.13-151830.30" + process $proc$libresoc.v:151830$7882 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:150206.13-150206.31" - process $proc$libresoc.v:150206$7835 + attribute \src "libresoc.v:151838.13-151838.31" + process $proc$libresoc.v:151838$7883 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:150210.13-150210.31" - process $proc$libresoc.v:150210$7836 + attribute \src "libresoc.v:151842.13-151842.31" + process $proc$libresoc.v:151842$7884 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:150222.7-150222.26" - process $proc$libresoc.v:150222$7837 + attribute \src "libresoc.v:151854.7-151854.26" + process $proc$libresoc.v:151854$7885 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:150226.7-150226.26" - process $proc$libresoc.v:150226$7838 + attribute \src "libresoc.v:151858.7-151858.26" + process $proc$libresoc.v:151858$7886 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:150230.7-150230.25" - process $proc$libresoc.v:150230$7839 + attribute \src "libresoc.v:151862.7-151862.25" + process $proc$libresoc.v:151862$7887 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:150234.7-150234.25" - process $proc$libresoc.v:150234$7840 + attribute \src "libresoc.v:151866.7-151866.25" + process $proc$libresoc.v:151866$7888 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:150248.13-150248.31" - process $proc$libresoc.v:150248$7841 + attribute \src "libresoc.v:151880.13-151880.31" + process $proc$libresoc.v:151880$7889 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:150252.13-150252.31" - process $proc$libresoc.v:150252$7842 + attribute \src "libresoc.v:151884.13-151884.31" + process $proc$libresoc.v:151884$7890 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:150258.14-150258.43" - process $proc$libresoc.v:150258$7843 + attribute \src "libresoc.v:151890.14-151890.43" + process $proc$libresoc.v:151890$7891 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:150262.14-150262.43" - process $proc$libresoc.v:150262$7844 + attribute \src "libresoc.v:151894.14-151894.43" + process $proc$libresoc.v:151894$7892 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:150266.7-150266.20" - process $proc$libresoc.v:150266$7845 + attribute \src "libresoc.v:151898.7-151898.20" + process $proc$libresoc.v:151898$7893 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:150337.3-150338.39" - process $proc$libresoc.v:150337$7653 + attribute \src "libresoc.v:151969.3-151970.39" + process $proc$libresoc.v:151969$7701 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:150339.3-150340.43" - process $proc$libresoc.v:150339$7654 + attribute \src "libresoc.v:151971.3-151972.43" + process $proc$libresoc.v:151971$7702 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:150341.3-150342.29" - process $proc$libresoc.v:150341$7655 + attribute \src "libresoc.v:151973.3-151974.29" + process $proc$libresoc.v:151973$7703 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:150343.3-150344.29" - process $proc$libresoc.v:150343$7656 + attribute \src "libresoc.v:151975.3-151976.29" + process $proc$libresoc.v:151975$7704 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:150345.3-150346.29" - process $proc$libresoc.v:150345$7657 + attribute \src "libresoc.v:151977.3-151978.29" + process $proc$libresoc.v:151977$7705 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:150347.3-150348.47" - process $proc$libresoc.v:150347$7658 + attribute \src "libresoc.v:151979.3-151980.47" + process $proc$libresoc.v:151979$7706 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:150349.3-150350.53" - process $proc$libresoc.v:150349$7659 + attribute \src "libresoc.v:151981.3-151982.53" + process $proc$libresoc.v:151981$7707 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:150351.3-150352.47" - process $proc$libresoc.v:150351$7660 + attribute \src "libresoc.v:151983.3-151984.47" + process $proc$libresoc.v:151983$7708 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:150353.3-150354.53" - process $proc$libresoc.v:150353$7661 + attribute \src "libresoc.v:151985.3-151986.53" + process $proc$libresoc.v:151985$7709 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:150355.3-150356.43" - process $proc$libresoc.v:150355$7662 + attribute \src "libresoc.v:151987.3-151988.43" + process $proc$libresoc.v:151987$7710 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:150357.3-150358.49" - process $proc$libresoc.v:150357$7663 + attribute \src "libresoc.v:151989.3-151990.49" + process $proc$libresoc.v:151989$7711 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:150359.3-150360.37" - process $proc$libresoc.v:150359$7664 + attribute \src "libresoc.v:151991.3-151992.37" + process $proc$libresoc.v:151991$7712 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:150361.3-150362.43" - process $proc$libresoc.v:150361$7665 + attribute \src "libresoc.v:151993.3-151994.43" + process $proc$libresoc.v:151993$7713 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:150363.3-150364.69" - process $proc$libresoc.v:150363$7666 + attribute \src "libresoc.v:151995.3-151996.69" + process $proc$libresoc.v:151995$7714 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:150365.3-150366.65" - process $proc$libresoc.v:150365$7667 + attribute \src "libresoc.v:151997.3-151998.65" + process $proc$libresoc.v:151997$7715 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:150367.3-150368.79" - process $proc$libresoc.v:150367$7668 + attribute \src "libresoc.v:151999.3-152000.79" + process $proc$libresoc.v:151999$7716 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:150369.3-150370.75" - process $proc$libresoc.v:150369$7669 + attribute \src "libresoc.v:152001.3-152002.75" + process $proc$libresoc.v:152001$7717 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:150371.3-150372.63" - process $proc$libresoc.v:150371$7670 + attribute \src "libresoc.v:152003.3-152004.63" + process $proc$libresoc.v:152003$7718 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:150373.3-150374.63" - process $proc$libresoc.v:150373$7671 + attribute \src "libresoc.v:152005.3-152006.63" + process $proc$libresoc.v:152005$7719 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:150375.3-150376.63" - process $proc$libresoc.v:150375$7672 + attribute \src "libresoc.v:152007.3-152008.63" + process $proc$libresoc.v:152007$7720 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:150377.3-150378.63" - process $proc$libresoc.v:150377$7673 + attribute \src "libresoc.v:152009.3-152010.63" + process $proc$libresoc.v:152009$7721 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:150379.3-150380.69" - process $proc$libresoc.v:150379$7674 + attribute \src "libresoc.v:152011.3-152012.69" + process $proc$libresoc.v:152011$7722 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:150381.3-150382.67" - process $proc$libresoc.v:150381$7675 + attribute \src "libresoc.v:152013.3-152014.67" + process $proc$libresoc.v:152013$7723 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:150383.3-150384.69" - process $proc$libresoc.v:150383$7676 + attribute \src "libresoc.v:152015.3-152016.69" + process $proc$libresoc.v:152015$7724 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:150385.3-150386.59" - process $proc$libresoc.v:150385$7677 + attribute \src "libresoc.v:152017.3-152018.59" + process $proc$libresoc.v:152017$7725 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:150387.3-150388.39" - process $proc$libresoc.v:150387$7678 + attribute \src "libresoc.v:152019.3-152020.39" + process $proc$libresoc.v:152019$7726 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:150389.3-150390.39" - process $proc$libresoc.v:150389$7679 + attribute \src "libresoc.v:152021.3-152022.39" + process $proc$libresoc.v:152021$7727 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:150391.3-150392.39" - process $proc$libresoc.v:150391$7680 + attribute \src "libresoc.v:152023.3-152024.39" + process $proc$libresoc.v:152023$7728 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:150393.3-150394.39" - process $proc$libresoc.v:150393$7681 + attribute \src "libresoc.v:152025.3-152026.39" + process $proc$libresoc.v:152025$7729 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:150395.3-150396.39" - process $proc$libresoc.v:150395$7682 + attribute \src "libresoc.v:152027.3-152028.39" + process $proc$libresoc.v:152027$7730 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:150397.3-150398.39" - process $proc$libresoc.v:150397$7683 + attribute \src "libresoc.v:152029.3-152030.39" + process $proc$libresoc.v:152029$7731 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:150399.3-150400.39" - process $proc$libresoc.v:150399$7684 + attribute \src "libresoc.v:152031.3-152032.39" + process $proc$libresoc.v:152031$7732 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:150401.3-150402.39" - process $proc$libresoc.v:150401$7685 + attribute \src "libresoc.v:152033.3-152034.39" + process $proc$libresoc.v:152033$7733 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:150403.3-150404.41" - process $proc$libresoc.v:150403$7686 + attribute \src "libresoc.v:152035.3-152036.41" + process $proc$libresoc.v:152035$7734 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:150405.3-150406.41" - process $proc$libresoc.v:150405$7687 + attribute \src "libresoc.v:152037.3-152038.41" + process $proc$libresoc.v:152037$7735 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:150407.3-150408.37" - process $proc$libresoc.v:150407$7688 + attribute \src "libresoc.v:152039.3-152040.37" + process $proc$libresoc.v:152039$7736 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:150409.3-150410.40" - process $proc$libresoc.v:150409$7689 + attribute \src "libresoc.v:152041.3-152042.40" + process $proc$libresoc.v:152041$7737 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:150411.3-150412.25" - process $proc$libresoc.v:150411$7690 + attribute \src "libresoc.v:152043.3-152044.25" + process $proc$libresoc.v:152043$7738 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:150492.3-150501.6" - process $proc$libresoc.v:150492$7691 + attribute \src "libresoc.v:152124.3-152133.6" + process $proc$libresoc.v:152124$7739 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:150493.5-150493.29" + attribute \src "libresoc.v:152125.5-152125.29" switch \initial - attribute \src "libresoc.v:150493.9-150493.17" + attribute \src "libresoc.v:152125.9-152125.17" case 1'1 case end @@ -315913,14 +318410,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:150502.3-150510.6" - process $proc$libresoc.v:150502$7692 + attribute \src "libresoc.v:152134.3-152142.6" + process $proc$libresoc.v:152134$7740 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7693 $1\rok_l_s_rdok$next[0:0]$7694 - attribute \src "libresoc.v:150503.5-150503.29" + assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:152135.5-152135.29" switch \initial - attribute \src "libresoc.v:150503.9-150503.17" + attribute \src "libresoc.v:152135.9-152135.17" case 1'1 case end @@ -315929,21 +318426,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7694 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7742 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7694 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7742 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7693 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 end - attribute \src "libresoc.v:150511.3-150519.6" - process $proc$libresoc.v:150511$7695 + attribute \src "libresoc.v:152143.3-152151.6" + process $proc$libresoc.v:152143$7743 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7696 $1\rok_l_r_rdok$next[0:0]$7697 - attribute \src "libresoc.v:150512.5-150512.29" + assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:152144.5-152144.29" switch \initial - attribute \src "libresoc.v:150512.9-150512.17" + attribute \src "libresoc.v:152144.9-152144.17" case 1'1 case end @@ -315952,21 +318449,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7697 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7745 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7697 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7745 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7696 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 end - attribute \src "libresoc.v:150520.3-150528.6" - process $proc$libresoc.v:150520$7698 + attribute \src "libresoc.v:152152.3-152160.6" + process $proc$libresoc.v:152152$7746 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7699 $1\rst_l_s_rst$next[0:0]$7700 - attribute \src "libresoc.v:150521.5-150521.29" + assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:152153.5-152153.29" switch \initial - attribute \src "libresoc.v:150521.9-150521.17" + attribute \src "libresoc.v:152153.9-152153.17" case 1'1 case end @@ -315975,21 +318472,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7700 1'0 + assign $1\rst_l_s_rst$next[0:0]$7748 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7700 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7748 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7699 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 end - attribute \src "libresoc.v:150529.3-150537.6" - process $proc$libresoc.v:150529$7701 + attribute \src "libresoc.v:152161.3-152169.6" + process $proc$libresoc.v:152161$7749 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7702 $1\rst_l_r_rst$next[0:0]$7703 - attribute \src "libresoc.v:150530.5-150530.29" + assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:152162.5-152162.29" switch \initial - attribute \src "libresoc.v:150530.9-150530.17" + attribute \src "libresoc.v:152162.9-152162.17" case 1'1 case end @@ -315998,21 +318495,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7703 1'1 + assign $1\rst_l_r_rst$next[0:0]$7751 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7703 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7751 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7702 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 end - attribute \src "libresoc.v:150538.3-150546.6" - process $proc$libresoc.v:150538$7704 + attribute \src "libresoc.v:152170.3-152178.6" + process $proc$libresoc.v:152170$7752 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7705 $1\opc_l_s_opc$next[0:0]$7706 - attribute \src "libresoc.v:150539.5-150539.29" + assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:152171.5-152171.29" switch \initial - attribute \src "libresoc.v:150539.9-150539.17" + attribute \src "libresoc.v:152171.9-152171.17" case 1'1 case end @@ -316021,21 +318518,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7706 1'0 + assign $1\opc_l_s_opc$next[0:0]$7754 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7706 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7754 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7705 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 end - attribute \src "libresoc.v:150547.3-150555.6" - process $proc$libresoc.v:150547$7707 + attribute \src "libresoc.v:152179.3-152187.6" + process $proc$libresoc.v:152179$7755 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7708 $1\opc_l_r_opc$next[0:0]$7709 - attribute \src "libresoc.v:150548.5-150548.29" + assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:152180.5-152180.29" switch \initial - attribute \src "libresoc.v:150548.9-150548.17" + attribute \src "libresoc.v:152180.9-152180.17" case 1'1 case end @@ -316044,21 +318541,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7709 1'1 + assign $1\opc_l_r_opc$next[0:0]$7757 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7709 \req_done + assign $1\opc_l_r_opc$next[0:0]$7757 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7708 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 end - attribute \src "libresoc.v:150556.3-150564.6" - process $proc$libresoc.v:150556$7710 + attribute \src "libresoc.v:152188.3-152196.6" + process $proc$libresoc.v:152188$7758 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7711 $1\src_l_s_src$next[2:0]$7712 - attribute \src "libresoc.v:150557.5-150557.29" + assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:152189.5-152189.29" switch \initial - attribute \src "libresoc.v:150557.9-150557.17" + attribute \src "libresoc.v:152189.9-152189.17" case 1'1 case end @@ -316067,21 +318564,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7712 3'000 + assign $1\src_l_s_src$next[2:0]$7760 3'000 case - assign $1\src_l_s_src$next[2:0]$7712 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7760 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7711 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 end - attribute \src "libresoc.v:150565.3-150573.6" - process $proc$libresoc.v:150565$7713 + attribute \src "libresoc.v:152197.3-152205.6" + process $proc$libresoc.v:152197$7761 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7714 $1\src_l_r_src$next[2:0]$7715 - attribute \src "libresoc.v:150566.5-150566.29" + assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:152198.5-152198.29" switch \initial - attribute \src "libresoc.v:150566.9-150566.17" + attribute \src "libresoc.v:152198.9-152198.17" case 1'1 case end @@ -316090,21 +318587,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7715 3'111 + assign $1\src_l_r_src$next[2:0]$7763 3'111 case - assign $1\src_l_r_src$next[2:0]$7715 \reset_r + assign $1\src_l_r_src$next[2:0]$7763 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7714 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 end - attribute \src "libresoc.v:150574.3-150582.6" - process $proc$libresoc.v:150574$7716 + attribute \src "libresoc.v:152206.3-152214.6" + process $proc$libresoc.v:152206$7764 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7717 $1\req_l_s_req$next[3:0]$7718 - attribute \src "libresoc.v:150575.5-150575.29" + assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:152207.5-152207.29" switch \initial - attribute \src "libresoc.v:150575.9-150575.17" + attribute \src "libresoc.v:152207.9-152207.17" case 1'1 case end @@ -316113,21 +318610,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7718 4'0000 + assign $1\req_l_s_req$next[3:0]$7766 4'0000 case - assign $1\req_l_s_req$next[3:0]$7718 \$66 + assign $1\req_l_s_req$next[3:0]$7766 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7717 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 end - attribute \src "libresoc.v:150583.3-150591.6" - process $proc$libresoc.v:150583$7719 + attribute \src "libresoc.v:152215.3-152223.6" + process $proc$libresoc.v:152215$7767 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7720 $1\req_l_r_req$next[3:0]$7721 - attribute \src "libresoc.v:150584.5-150584.29" + assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:152216.5-152216.29" switch \initial - attribute \src "libresoc.v:150584.9-150584.17" + attribute \src "libresoc.v:152216.9-152216.17" case 1'1 case end @@ -316136,15 +318633,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7721 4'1111 + assign $1\req_l_r_req$next[3:0]$7769 4'1111 case - assign $1\req_l_r_req$next[3:0]$7721 \$68 + assign $1\req_l_r_req$next[3:0]$7769 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7720 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 end - attribute \src "libresoc.v:150592.3-150624.6" - process $proc$libresoc.v:150592$7722 + attribute \src "libresoc.v:152224.3-152256.6" + process $proc$libresoc.v:152224$7770 assign { } { } assign { } { } assign { } { } @@ -316169,27 +318666,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7726 $1\alu_mul0_mul_op__insn$next[31:0]$7738 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7774 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 - attribute \src "libresoc.v:150593.5-150593.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 + attribute \src "libresoc.v:152225.5-152225.29" switch \initial - attribute \src "libresoc.v:150593.9-150593.17" + attribute \src "libresoc.v:152225.9-152225.17" case 1'1 case end @@ -316209,20 +318706,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7738 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7786 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7738 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7786 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -316234,48 +318731,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7726 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7774 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 end - attribute \src "libresoc.v:150625.3-150646.6" - process $proc$libresoc.v:150625$7753 + attribute \src "libresoc.v:152257.3-152278.6" + process $proc$libresoc.v:152257$7801 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7754 $2\data_r0__o$next[63:0]$7758 + assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7755 $3\data_r0__o_ok$next[0:0]$7760 - attribute \src "libresoc.v:150626.5-150626.29" + assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 + attribute \src "libresoc.v:152258.5-152258.29" switch \initial - attribute \src "libresoc.v:150626.9-150626.17" + attribute \src "libresoc.v:152258.9-152258.17" case 1'1 case end @@ -316285,10 +318782,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7757 $1\data_r0__o$next[63:0]$7756 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7805 $1\data_r0__o$next[63:0]$7804 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7756 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7757 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7804 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7805 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316296,38 +318793,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7759 $2\data_r0__o$next[63:0]$7758 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7807 $2\data_r0__o$next[63:0]$7806 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7758 $1\data_r0__o$next[63:0]$7756 - assign $2\data_r0__o_ok$next[0:0]$7759 $1\data_r0__o_ok$next[0:0]$7757 + assign $2\data_r0__o$next[63:0]$7806 $1\data_r0__o$next[63:0]$7804 + assign $2\data_r0__o_ok$next[0:0]$7807 $1\data_r0__o_ok$next[0:0]$7805 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7760 1'0 + assign $3\data_r0__o_ok$next[0:0]$7808 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7760 $2\data_r0__o_ok$next[0:0]$7759 + assign $3\data_r0__o_ok$next[0:0]$7808 $2\data_r0__o_ok$next[0:0]$7807 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7754 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7755 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 end - attribute \src "libresoc.v:150647.3-150668.6" - process $proc$libresoc.v:150647$7761 + attribute \src "libresoc.v:152279.3-152300.6" + process $proc$libresoc.v:152279$7809 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7762 $2\data_r1__cr_a$next[3:0]$7766 + assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7763 $3\data_r1__cr_a_ok$next[0:0]$7768 - attribute \src "libresoc.v:150648.5-150648.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 + attribute \src "libresoc.v:152280.5-152280.29" switch \initial - attribute \src "libresoc.v:150648.9-150648.17" + attribute \src "libresoc.v:152280.9-152280.17" case 1'1 case end @@ -316337,10 +318834,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7765 $1\data_r1__cr_a$next[3:0]$7764 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7813 $1\data_r1__cr_a$next[3:0]$7812 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7764 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7765 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7812 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7813 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316348,38 +318845,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7767 $2\data_r1__cr_a$next[3:0]$7766 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7815 $2\data_r1__cr_a$next[3:0]$7814 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7766 $1\data_r1__cr_a$next[3:0]$7764 - assign $2\data_r1__cr_a_ok$next[0:0]$7767 $1\data_r1__cr_a_ok$next[0:0]$7765 + assign $2\data_r1__cr_a$next[3:0]$7814 $1\data_r1__cr_a$next[3:0]$7812 + assign $2\data_r1__cr_a_ok$next[0:0]$7815 $1\data_r1__cr_a_ok$next[0:0]$7813 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7768 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7816 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7768 $2\data_r1__cr_a_ok$next[0:0]$7767 + assign $3\data_r1__cr_a_ok$next[0:0]$7816 $2\data_r1__cr_a_ok$next[0:0]$7815 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7762 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7763 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 end - attribute \src "libresoc.v:150669.3-150690.6" - process $proc$libresoc.v:150669$7769 + attribute \src "libresoc.v:152301.3-152322.6" + process $proc$libresoc.v:152301$7817 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7770 $2\data_r2__xer_ov$next[1:0]$7774 + assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7771 $3\data_r2__xer_ov_ok$next[0:0]$7776 - attribute \src "libresoc.v:150670.5-150670.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 + attribute \src "libresoc.v:152302.5-152302.29" switch \initial - attribute \src "libresoc.v:150670.9-150670.17" + attribute \src "libresoc.v:152302.9-152302.17" case 1'1 case end @@ -316389,10 +318886,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7773 $1\data_r2__xer_ov$next[1:0]$7772 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7821 $1\data_r2__xer_ov$next[1:0]$7820 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7772 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7773 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7820 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7821 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316400,38 +318897,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7775 $2\data_r2__xer_ov$next[1:0]$7774 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7823 $2\data_r2__xer_ov$next[1:0]$7822 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7774 $1\data_r2__xer_ov$next[1:0]$7772 - assign $2\data_r2__xer_ov_ok$next[0:0]$7775 $1\data_r2__xer_ov_ok$next[0:0]$7773 + assign $2\data_r2__xer_ov$next[1:0]$7822 $1\data_r2__xer_ov$next[1:0]$7820 + assign $2\data_r2__xer_ov_ok$next[0:0]$7823 $1\data_r2__xer_ov_ok$next[0:0]$7821 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7776 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7776 $2\data_r2__xer_ov_ok$next[0:0]$7775 + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 $2\data_r2__xer_ov_ok$next[0:0]$7823 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7770 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7771 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 end - attribute \src "libresoc.v:150691.3-150712.6" - process $proc$libresoc.v:150691$7777 + attribute \src "libresoc.v:152323.3-152344.6" + process $proc$libresoc.v:152323$7825 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7778 $2\data_r3__xer_so$next[0:0]$7782 + assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7779 $3\data_r3__xer_so_ok$next[0:0]$7784 - attribute \src "libresoc.v:150692.5-150692.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 + attribute \src "libresoc.v:152324.5-152324.29" switch \initial - attribute \src "libresoc.v:150692.9-150692.17" + attribute \src "libresoc.v:152324.9-152324.17" case 1'1 case end @@ -316441,10 +318938,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7781 $1\data_r3__xer_so$next[0:0]$7780 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7829 $1\data_r3__xer_so$next[0:0]$7828 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7780 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7781 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7828 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7829 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316452,32 +318949,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7783 $2\data_r3__xer_so$next[0:0]$7782 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7831 $2\data_r3__xer_so$next[0:0]$7830 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7782 $1\data_r3__xer_so$next[0:0]$7780 - assign $2\data_r3__xer_so_ok$next[0:0]$7783 $1\data_r3__xer_so_ok$next[0:0]$7781 + assign $2\data_r3__xer_so$next[0:0]$7830 $1\data_r3__xer_so$next[0:0]$7828 + assign $2\data_r3__xer_so_ok$next[0:0]$7831 $1\data_r3__xer_so_ok$next[0:0]$7829 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7784 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7832 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7784 $2\data_r3__xer_so_ok$next[0:0]$7783 + assign $3\data_r3__xer_so_ok$next[0:0]$7832 $2\data_r3__xer_so_ok$next[0:0]$7831 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7778 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7779 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 end - attribute \src "libresoc.v:150713.3-150722.6" - process $proc$libresoc.v:150713$7785 + attribute \src "libresoc.v:152345.3-152354.6" + process $proc$libresoc.v:152345$7833 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7786 $1\src_r0$next[63:0]$7787 - attribute \src "libresoc.v:150714.5-150714.29" + assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:152346.5-152346.29" switch \initial - attribute \src "libresoc.v:150714.9-150714.17" + attribute \src "libresoc.v:152346.9-152346.17" case 1'1 case end @@ -316486,21 +318983,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7787 \src1_i + assign $1\src_r0$next[63:0]$7835 \src1_i case - assign $1\src_r0$next[63:0]$7787 \src_r0 + assign $1\src_r0$next[63:0]$7835 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7786 + update \src_r0$next $0\src_r0$next[63:0]$7834 end - attribute \src "libresoc.v:150723.3-150732.6" - process $proc$libresoc.v:150723$7788 + attribute \src "libresoc.v:152355.3-152364.6" + process $proc$libresoc.v:152355$7836 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7789 $1\src_r1$next[63:0]$7790 - attribute \src "libresoc.v:150724.5-150724.29" + assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:152356.5-152356.29" switch \initial - attribute \src "libresoc.v:150724.9-150724.17" + attribute \src "libresoc.v:152356.9-152356.17" case 1'1 case end @@ -316509,21 +319006,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7790 \src_or_imm + assign $1\src_r1$next[63:0]$7838 \src_or_imm case - assign $1\src_r1$next[63:0]$7790 \src_r1 + assign $1\src_r1$next[63:0]$7838 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7789 + update \src_r1$next $0\src_r1$next[63:0]$7837 end - attribute \src "libresoc.v:150733.3-150742.6" - process $proc$libresoc.v:150733$7791 + attribute \src "libresoc.v:152365.3-152374.6" + process $proc$libresoc.v:152365$7839 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7792 $1\src_r2$next[0:0]$7793 - attribute \src "libresoc.v:150734.5-150734.29" + assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:152366.5-152366.29" switch \initial - attribute \src "libresoc.v:150734.9-150734.17" + attribute \src "libresoc.v:152366.9-152366.17" case 1'1 case end @@ -316532,21 +319029,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7793 \src3_i + assign $1\src_r2$next[0:0]$7841 \src3_i case - assign $1\src_r2$next[0:0]$7793 \src_r2 + assign $1\src_r2$next[0:0]$7841 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7792 + update \src_r2$next $0\src_r2$next[0:0]$7840 end - attribute \src "libresoc.v:150743.3-150751.6" - process $proc$libresoc.v:150743$7794 + attribute \src "libresoc.v:152375.3-152383.6" + process $proc$libresoc.v:152375$7842 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7795 $1\alui_l_r_alui$next[0:0]$7796 - attribute \src "libresoc.v:150744.5-150744.29" + assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:152376.5-152376.29" switch \initial - attribute \src "libresoc.v:150744.9-150744.17" + attribute \src "libresoc.v:152376.9-152376.17" case 1'1 case end @@ -316555,21 +319052,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7796 1'1 + assign $1\alui_l_r_alui$next[0:0]$7844 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7796 \$88 + assign $1\alui_l_r_alui$next[0:0]$7844 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7795 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 end - attribute \src "libresoc.v:150752.3-150760.6" - process $proc$libresoc.v:150752$7797 + attribute \src "libresoc.v:152384.3-152392.6" + process $proc$libresoc.v:152384$7845 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7798 $1\alu_l_r_alu$next[0:0]$7799 - attribute \src "libresoc.v:150753.5-150753.29" + assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:152385.5-152385.29" switch \initial - attribute \src "libresoc.v:150753.9-150753.17" + attribute \src "libresoc.v:152385.9-152385.17" case 1'1 case end @@ -316578,21 +319075,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7799 1'1 + assign $1\alu_l_r_alu$next[0:0]$7847 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7799 \$90 + assign $1\alu_l_r_alu$next[0:0]$7847 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7798 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 end - attribute \src "libresoc.v:150761.3-150770.6" - process $proc$libresoc.v:150761$7800 + attribute \src "libresoc.v:152393.3-152402.6" + process $proc$libresoc.v:152393$7848 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:150762.5-150762.29" + attribute \src "libresoc.v:152394.5-152394.29" switch \initial - attribute \src "libresoc.v:150762.9-150762.17" + attribute \src "libresoc.v:152394.9-152394.17" case 1'1 case end @@ -316608,14 +319105,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:150771.3-150780.6" - process $proc$libresoc.v:150771$7801 + attribute \src "libresoc.v:152403.3-152412.6" + process $proc$libresoc.v:152403$7849 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:150772.5-150772.29" + attribute \src "libresoc.v:152404.5-152404.29" switch \initial - attribute \src "libresoc.v:150772.9-150772.17" + attribute \src "libresoc.v:152404.9-152404.17" case 1'1 case end @@ -316631,14 +319128,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:150781.3-150790.6" - process $proc$libresoc.v:150781$7802 + attribute \src "libresoc.v:152413.3-152422.6" + process $proc$libresoc.v:152413$7850 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:150782.5-150782.29" + attribute \src "libresoc.v:152414.5-152414.29" switch \initial - attribute \src "libresoc.v:150782.9-150782.17" + attribute \src "libresoc.v:152414.9-152414.17" case 1'1 case end @@ -316654,14 +319151,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:150791.3-150800.6" - process $proc$libresoc.v:150791$7803 + attribute \src "libresoc.v:152423.3-152432.6" + process $proc$libresoc.v:152423$7851 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:150792.5-150792.29" + attribute \src "libresoc.v:152424.5-152424.29" switch \initial - attribute \src "libresoc.v:150792.9-150792.17" + attribute \src "libresoc.v:152424.9-152424.17" case 1'1 case end @@ -316677,14 +319174,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:150801.3-150809.6" - process $proc$libresoc.v:150801$7804 + attribute \src "libresoc.v:152433.3-152441.6" + process $proc$libresoc.v:152433$7852 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7805 $1\prev_wr_go$next[3:0]$7806 - attribute \src "libresoc.v:150802.5-150802.29" + assign $0\prev_wr_go$next[3:0]$7853 $1\prev_wr_go$next[3:0]$7854 + attribute \src "libresoc.v:152434.5-152434.29" switch \initial - attribute \src "libresoc.v:150802.9-150802.17" + attribute \src "libresoc.v:152434.9-152434.17" case 1'1 case end @@ -316693,73 +319190,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7806 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7806 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7805 - end - connect \$100 $and$libresoc.v:150277$7593_Y - connect \$102 $and$libresoc.v:150278$7594_Y - connect \$104 $and$libresoc.v:150279$7595_Y - connect \$106 $and$libresoc.v:150280$7596_Y - connect \$108 $and$libresoc.v:150281$7597_Y - connect \$10 $and$libresoc.v:150282$7598_Y - connect \$110 $and$libresoc.v:150283$7599_Y - connect \$112 $and$libresoc.v:150284$7600_Y - connect \$114 $and$libresoc.v:150285$7601_Y - connect \$116 $and$libresoc.v:150286$7602_Y - connect \$118 $and$libresoc.v:150287$7603_Y - connect \$120 $and$libresoc.v:150288$7604_Y - connect \$12 $not$libresoc.v:150289$7605_Y - connect \$14 $and$libresoc.v:150290$7606_Y - connect \$16 $not$libresoc.v:150291$7607_Y - connect \$18 $and$libresoc.v:150292$7608_Y - connect \$20 $and$libresoc.v:150293$7609_Y - connect \$24 $not$libresoc.v:150294$7610_Y - connect \$26 $and$libresoc.v:150295$7611_Y - connect \$23 $reduce_or$libresoc.v:150296$7612_Y - connect \$22 $not$libresoc.v:150297$7613_Y - connect \$2 $and$libresoc.v:150298$7614_Y - connect \$30 $and$libresoc.v:150299$7615_Y - connect \$32 $reduce_or$libresoc.v:150300$7616_Y - connect \$34 $reduce_or$libresoc.v:150301$7617_Y - connect \$36 $or$libresoc.v:150302$7618_Y - connect \$38 $not$libresoc.v:150303$7619_Y - connect \$40 $and$libresoc.v:150304$7620_Y - connect \$42 $and$libresoc.v:150305$7621_Y - connect \$44 $eq$libresoc.v:150306$7622_Y - connect \$46 $and$libresoc.v:150307$7623_Y - connect \$48 $eq$libresoc.v:150308$7624_Y - connect \$50 $and$libresoc.v:150309$7625_Y - connect \$52 $and$libresoc.v:150310$7626_Y - connect \$54 $and$libresoc.v:150311$7627_Y - connect \$56 $or$libresoc.v:150312$7628_Y - connect \$58 $or$libresoc.v:150313$7629_Y - connect \$5 $not$libresoc.v:150314$7630_Y - connect \$60 $or$libresoc.v:150315$7631_Y - connect \$62 $or$libresoc.v:150316$7632_Y - connect \$64 $and$libresoc.v:150317$7633_Y - connect \$66 $and$libresoc.v:150318$7634_Y - connect \$68 $or$libresoc.v:150319$7635_Y - connect \$70 $and$libresoc.v:150320$7636_Y - connect \$72 $and$libresoc.v:150321$7637_Y - connect \$74 $and$libresoc.v:150322$7638_Y - connect \$76 $and$libresoc.v:150323$7639_Y - connect \$78 $ternary$libresoc.v:150324$7640_Y - connect \$7 $or$libresoc.v:150325$7641_Y - connect \$80 $ternary$libresoc.v:150326$7642_Y - connect \$82 $ternary$libresoc.v:150327$7643_Y - connect \$84 $ternary$libresoc.v:150328$7644_Y - connect \$86 $ternary$libresoc.v:150329$7645_Y - connect \$88 $and$libresoc.v:150330$7646_Y - connect \$4 $reduce_and$libresoc.v:150331$7647_Y - connect \$90 $and$libresoc.v:150332$7648_Y - connect \$92 $and$libresoc.v:150333$7649_Y - connect \$94 $not$libresoc.v:150334$7650_Y - connect \$96 $and$libresoc.v:150335$7651_Y - connect \$98 $not$libresoc.v:150336$7652_Y + assign $1\prev_wr_go$next[3:0]$7854 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7854 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7853 + end + connect \$100 $and$libresoc.v:151909$7641_Y + connect \$102 $and$libresoc.v:151910$7642_Y + connect \$104 $and$libresoc.v:151911$7643_Y + connect \$106 $and$libresoc.v:151912$7644_Y + connect \$108 $and$libresoc.v:151913$7645_Y + connect \$10 $and$libresoc.v:151914$7646_Y + connect \$110 $and$libresoc.v:151915$7647_Y + connect \$112 $and$libresoc.v:151916$7648_Y + connect \$114 $and$libresoc.v:151917$7649_Y + connect \$116 $and$libresoc.v:151918$7650_Y + connect \$118 $and$libresoc.v:151919$7651_Y + connect \$120 $and$libresoc.v:151920$7652_Y + connect \$12 $not$libresoc.v:151921$7653_Y + connect \$14 $and$libresoc.v:151922$7654_Y + connect \$16 $not$libresoc.v:151923$7655_Y + connect \$18 $and$libresoc.v:151924$7656_Y + connect \$20 $and$libresoc.v:151925$7657_Y + connect \$24 $not$libresoc.v:151926$7658_Y + connect \$26 $and$libresoc.v:151927$7659_Y + connect \$23 $reduce_or$libresoc.v:151928$7660_Y + connect \$22 $not$libresoc.v:151929$7661_Y + connect \$2 $and$libresoc.v:151930$7662_Y + connect \$30 $and$libresoc.v:151931$7663_Y + connect \$32 $reduce_or$libresoc.v:151932$7664_Y + connect \$34 $reduce_or$libresoc.v:151933$7665_Y + connect \$36 $or$libresoc.v:151934$7666_Y + connect \$38 $not$libresoc.v:151935$7667_Y + connect \$40 $and$libresoc.v:151936$7668_Y + connect \$42 $and$libresoc.v:151937$7669_Y + connect \$44 $eq$libresoc.v:151938$7670_Y + connect \$46 $and$libresoc.v:151939$7671_Y + connect \$48 $eq$libresoc.v:151940$7672_Y + connect \$50 $and$libresoc.v:151941$7673_Y + connect \$52 $and$libresoc.v:151942$7674_Y + connect \$54 $and$libresoc.v:151943$7675_Y + connect \$56 $or$libresoc.v:151944$7676_Y + connect \$58 $or$libresoc.v:151945$7677_Y + connect \$5 $not$libresoc.v:151946$7678_Y + connect \$60 $or$libresoc.v:151947$7679_Y + connect \$62 $or$libresoc.v:151948$7680_Y + connect \$64 $and$libresoc.v:151949$7681_Y + connect \$66 $and$libresoc.v:151950$7682_Y + connect \$68 $or$libresoc.v:151951$7683_Y + connect \$70 $and$libresoc.v:151952$7684_Y + connect \$72 $and$libresoc.v:151953$7685_Y + connect \$74 $and$libresoc.v:151954$7686_Y + connect \$76 $and$libresoc.v:151955$7687_Y + connect \$78 $ternary$libresoc.v:151956$7688_Y + connect \$7 $or$libresoc.v:151957$7689_Y + connect \$80 $ternary$libresoc.v:151958$7690_Y + connect \$82 $ternary$libresoc.v:151959$7691_Y + connect \$84 $ternary$libresoc.v:151960$7692_Y + connect \$86 $ternary$libresoc.v:151961$7693_Y + connect \$88 $and$libresoc.v:151962$7694_Y + connect \$4 $reduce_and$libresoc.v:151963$7695_Y + connect \$90 $and$libresoc.v:151964$7696_Y + connect \$92 $and$libresoc.v:151965$7697_Y + connect \$94 $not$libresoc.v:151966$7698_Y + connect \$96 $and$libresoc.v:151967$7699_Y + connect \$98 $not$libresoc.v:151968$7700_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -316791,51 +319288,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:150844.1-151177.10" +attribute \src "libresoc.v:152476.1-152809.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:151144.18-151144.116" - wire $and$libresoc.v:151144$7847_Y - attribute \src "libresoc.v:151146.18-151146.116" - wire $and$libresoc.v:151146$7849_Y - attribute \src "libresoc.v:151147.18-151147.117" - wire $and$libresoc.v:151147$7850_Y - attribute \src "libresoc.v:151148.18-151148.117" - wire $and$libresoc.v:151148$7851_Y - attribute \src "libresoc.v:151151.18-151151.95" - wire width 65 $extend$libresoc.v:151151$7854_Y - attribute \src "libresoc.v:151152.18-151152.91" - wire width 65 $extend$libresoc.v:151152$7856_Y - attribute \src "libresoc.v:151154.18-151154.95" - wire width 65 $extend$libresoc.v:151154$7859_Y - attribute \src "libresoc.v:151155.18-151155.91" - wire width 65 $extend$libresoc.v:151155$7861_Y - attribute \src "libresoc.v:151151.18-151151.95" - wire width 65 $neg$libresoc.v:151151$7855_Y - attribute \src "libresoc.v:151154.18-151154.95" - wire width 65 $neg$libresoc.v:151154$7860_Y - attribute \src "libresoc.v:151152.18-151152.91" - wire width 65 $pos$libresoc.v:151152$7857_Y - attribute \src "libresoc.v:151155.18-151155.91" - wire width 65 $pos$libresoc.v:151155$7862_Y - attribute \src "libresoc.v:151143.18-151143.125" - wire $ternary$libresoc.v:151143$7846_Y - attribute \src "libresoc.v:151145.18-151145.125" - wire $ternary$libresoc.v:151145$7848_Y - attribute \src "libresoc.v:151153.18-151153.112" - wire width 65 $ternary$libresoc.v:151153$7858_Y - attribute \src "libresoc.v:151156.18-151156.112" - wire width 65 $ternary$libresoc.v:151156$7863_Y - attribute \src "libresoc.v:151157.18-151157.116" - wire width 32 $ternary$libresoc.v:151157$7864_Y - attribute \src "libresoc.v:151158.18-151158.116" - wire width 32 $ternary$libresoc.v:151158$7865_Y - attribute \src "libresoc.v:151149.18-151149.106" - wire $xor$libresoc.v:151149$7852_Y - attribute \src "libresoc.v:151150.18-151150.110" - wire $xor$libresoc.v:151150$7853_Y + attribute \src "libresoc.v:152776.18-152776.116" + wire $and$libresoc.v:152776$7895_Y + attribute \src "libresoc.v:152778.18-152778.116" + wire $and$libresoc.v:152778$7897_Y + attribute \src "libresoc.v:152779.18-152779.117" + wire $and$libresoc.v:152779$7898_Y + attribute \src "libresoc.v:152780.18-152780.117" + wire $and$libresoc.v:152780$7899_Y + attribute \src "libresoc.v:152783.18-152783.95" + wire width 65 $extend$libresoc.v:152783$7902_Y + attribute \src "libresoc.v:152784.18-152784.91" + wire width 65 $extend$libresoc.v:152784$7904_Y + attribute \src "libresoc.v:152786.18-152786.95" + wire width 65 $extend$libresoc.v:152786$7907_Y + attribute \src "libresoc.v:152787.18-152787.91" + wire width 65 $extend$libresoc.v:152787$7909_Y + attribute \src "libresoc.v:152783.18-152783.95" + wire width 65 $neg$libresoc.v:152783$7903_Y + attribute \src "libresoc.v:152786.18-152786.95" + wire width 65 $neg$libresoc.v:152786$7908_Y + attribute \src "libresoc.v:152784.18-152784.91" + wire width 65 $pos$libresoc.v:152784$7905_Y + attribute \src "libresoc.v:152787.18-152787.91" + wire width 65 $pos$libresoc.v:152787$7910_Y + attribute \src "libresoc.v:152775.18-152775.125" + wire $ternary$libresoc.v:152775$7894_Y + attribute \src "libresoc.v:152777.18-152777.125" + wire $ternary$libresoc.v:152777$7896_Y + attribute \src "libresoc.v:152785.18-152785.112" + wire width 65 $ternary$libresoc.v:152785$7906_Y + attribute \src "libresoc.v:152788.18-152788.112" + wire width 65 $ternary$libresoc.v:152788$7911_Y + attribute \src "libresoc.v:152789.18-152789.116" + wire width 32 $ternary$libresoc.v:152789$7912_Y + attribute \src "libresoc.v:152790.18-152790.116" + wire width 32 $ternary$libresoc.v:152790$7913_Y + attribute \src "libresoc.v:152781.18-152781.106" + wire $xor$libresoc.v:152781$7900_Y + attribute \src "libresoc.v:152782.18-152782.110" + wire $xor$libresoc.v:152782$7901_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -317135,7 +319632,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:151144$7847 + cell $and $and$libresoc.v:152776$7895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317143,10 +319640,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151144$7847_Y + connect \Y $and$libresoc.v:152776$7895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:151146$7849 + cell $and $and$libresoc.v:152778$7897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317154,10 +319651,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151146$7849_Y + connect \Y $and$libresoc.v:152778$7897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:151147$7850 + cell $and $and$libresoc.v:152779$7898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317165,10 +319662,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151147$7850_Y + connect \Y $and$libresoc.v:152779$7898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:151148$7851 + cell $and $and$libresoc.v:152780$7899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317176,122 +319673,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151148$7851_Y + connect \Y $and$libresoc.v:152780$7899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:151151$7854 + cell $pos $extend$libresoc.v:152783$7902 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:151151$7854_Y + connect \Y $extend$libresoc.v:152783$7902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151152$7856 + cell $pos $extend$libresoc.v:152784$7904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:151152$7856_Y + connect \Y $extend$libresoc.v:152784$7904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:151154$7859 + cell $pos $extend$libresoc.v:152786$7907 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:151154$7859_Y + connect \Y $extend$libresoc.v:152786$7907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151155$7861 + cell $pos $extend$libresoc.v:152787$7909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:151155$7861_Y + connect \Y $extend$libresoc.v:152787$7909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:151151$7855 + cell $neg $neg$libresoc.v:152783$7903 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151151$7854_Y - connect \Y $neg$libresoc.v:151151$7855_Y + connect \A $extend$libresoc.v:152783$7902_Y + connect \Y $neg$libresoc.v:152783$7903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:151154$7860 + cell $neg $neg$libresoc.v:152786$7908 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151154$7859_Y - connect \Y $neg$libresoc.v:151154$7860_Y + connect \A $extend$libresoc.v:152786$7907_Y + connect \Y $neg$libresoc.v:152786$7908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151152$7857 + cell $pos $pos$libresoc.v:152784$7905 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151152$7856_Y - connect \Y $pos$libresoc.v:151152$7857_Y + connect \A $extend$libresoc.v:152784$7904_Y + connect \Y $pos$libresoc.v:152784$7905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151155$7862 + cell $pos $pos$libresoc.v:152787$7910 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151155$7861_Y - connect \Y $pos$libresoc.v:151155$7862_Y + connect \A $extend$libresoc.v:152787$7909_Y + connect \Y $pos$libresoc.v:152787$7910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:151143$7846 + cell $mux $ternary$libresoc.v:152775$7894 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:151143$7846_Y + connect \Y $ternary$libresoc.v:152775$7894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:151145$7848 + cell $mux $ternary$libresoc.v:152777$7896 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:151145$7848_Y + connect \Y $ternary$libresoc.v:152777$7896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:151153$7858 + cell $mux $ternary$libresoc.v:152785$7906 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:151153$7858_Y + connect \Y $ternary$libresoc.v:152785$7906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:151156$7863 + cell $mux $ternary$libresoc.v:152788$7911 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:151156$7863_Y + connect \Y $ternary$libresoc.v:152788$7911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:151157$7864 + cell $mux $ternary$libresoc.v:152789$7912 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:151157$7864_Y + connect \Y $ternary$libresoc.v:152789$7912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:151158$7865 + cell $mux $ternary$libresoc.v:152790$7913 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:151158$7865_Y + connect \Y $ternary$libresoc.v:152790$7913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:151149$7852 + cell $xor $xor$libresoc.v:152781$7900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317299,10 +319796,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:151149$7852_Y + connect \Y $xor$libresoc.v:152781$7900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:151150$7853 + cell $xor $xor$libresoc.v:152782$7901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317310,24 +319807,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:151150$7853_Y - end - connect \$17 $ternary$libresoc.v:151143$7846_Y - connect \$19 $and$libresoc.v:151144$7847_Y - connect \$21 $ternary$libresoc.v:151145$7848_Y - connect \$23 $and$libresoc.v:151146$7849_Y - connect \$25 $and$libresoc.v:151147$7850_Y - connect \$27 $and$libresoc.v:151148$7851_Y - connect \$29 $xor$libresoc.v:151149$7852_Y - connect \$31 $xor$libresoc.v:151150$7853_Y - connect \$34 $neg$libresoc.v:151151$7855_Y - connect \$36 $pos$libresoc.v:151152$7857_Y - connect \$38 $ternary$libresoc.v:151153$7858_Y - connect \$41 $neg$libresoc.v:151154$7860_Y - connect \$43 $pos$libresoc.v:151155$7862_Y - connect \$45 $ternary$libresoc.v:151156$7863_Y - connect \$47 $ternary$libresoc.v:151157$7864_Y - connect \$49 $ternary$libresoc.v:151158$7865_Y + connect \Y $xor$libresoc.v:152782$7901_Y + end + connect \$17 $ternary$libresoc.v:152775$7894_Y + connect \$19 $and$libresoc.v:152776$7895_Y + connect \$21 $ternary$libresoc.v:152777$7896_Y + connect \$23 $and$libresoc.v:152778$7897_Y + connect \$25 $and$libresoc.v:152779$7898_Y + connect \$27 $and$libresoc.v:152780$7899_Y + connect \$29 $xor$libresoc.v:152781$7900_Y + connect \$31 $xor$libresoc.v:152782$7901_Y + connect \$34 $neg$libresoc.v:152783$7903_Y + connect \$36 $pos$libresoc.v:152784$7905_Y + connect \$38 $ternary$libresoc.v:152785$7906_Y + connect \$41 $neg$libresoc.v:152786$7908_Y + connect \$43 $pos$libresoc.v:152787$7910_Y + connect \$45 $ternary$libresoc.v:152788$7911_Y + connect \$47 $ternary$libresoc.v:152789$7912_Y + connect \$49 $ternary$libresoc.v:152790$7913_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -317347,17 +319844,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:151181.1-151444.10" +attribute \src "libresoc.v:152813.1-153076.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:151437.18-151437.98" - wire width 129 $extend$libresoc.v:151437$7867_Y - attribute \src "libresoc.v:151436.18-151436.99" - wire width 128 $mul$libresoc.v:151436$7866_Y - attribute \src "libresoc.v:151437.18-151437.98" - wire width 129 $pos$libresoc.v:151437$7868_Y + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $extend$libresoc.v:153069$7915_Y + attribute \src "libresoc.v:153068.18-153068.99" + wire width 128 $mul$libresoc.v:153068$7914_Y + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $pos$libresoc.v:153069$7916_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -317613,15 +320110,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:151437$7867 + cell $pos $extend$libresoc.v:153069$7915 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:151437$7867_Y + connect \Y $extend$libresoc.v:153069$7915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:151436$7866 + cell $mul $mul$libresoc.v:153068$7914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -317629,18 +320126,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:151436$7866_Y + connect \Y $mul$libresoc.v:153068$7914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:151437$7868 + cell $pos $pos$libresoc.v:153069$7916 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:151437$7867_Y - connect \Y $pos$libresoc.v:151437$7868_Y + connect \A $extend$libresoc.v:153069$7915_Y + connect \Y $pos$libresoc.v:153069$7916_Y end - connect \$18 $mul$libresoc.v:151436$7866_Y - connect \$17 $pos$libresoc.v:151437$7868_Y + connect \$18 $mul$libresoc.v:153068$7914_Y + connect \$17 $pos$libresoc.v:153069$7916_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -317648,65 +320145,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:151448.1-151833.10" +attribute \src "libresoc.v:153080.1-153465.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:151449.7-151449.20" + attribute \src "libresoc.v:153081.7-153081.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:151748.3-151766.6" - wire width 64 $0\o$14[63:0]$7885 - attribute \src "libresoc.v:151767.3-151785.6" + attribute \src "libresoc.v:153380.3-153398.6" + wire width 64 $0\o$14[63:0]$7933 + attribute \src "libresoc.v:153399.3-153417.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151805.3-151815.6" + attribute \src "libresoc.v:153437.3-153447.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:151816.3-151826.6" + attribute \src "libresoc.v:153448.3-153458.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:151748.3-151766.6" - wire width 64 $1\o$14[63:0]$7886 - attribute \src "libresoc.v:151767.3-151785.6" + attribute \src "libresoc.v:153380.3-153398.6" + wire width 64 $1\o$14[63:0]$7934 + attribute \src "libresoc.v:153399.3-153417.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151805.3-151815.6" + attribute \src "libresoc.v:153437.3-153447.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:151816.3-151826.6" + attribute \src "libresoc.v:153448.3-153458.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:151742.18-151742.104" - wire $and$libresoc.v:151742$7877_Y - attribute \src "libresoc.v:151746.18-151746.104" - wire $and$libresoc.v:151746$7881_Y - attribute \src "libresoc.v:151736.18-151736.95" - wire width 130 $extend$libresoc.v:151736$7869_Y - attribute \src "libresoc.v:151737.18-151737.90" - wire width 130 $extend$libresoc.v:151737$7871_Y - attribute \src "libresoc.v:151747.18-151747.95" - wire width 2 $extend$libresoc.v:151747$7882_Y - attribute \src "libresoc.v:151736.18-151736.95" - wire width 130 $neg$libresoc.v:151736$7870_Y - attribute \src "libresoc.v:151741.18-151741.98" - wire $not$libresoc.v:151741$7876_Y - attribute \src "libresoc.v:151745.18-151745.98" - wire $not$libresoc.v:151745$7880_Y - attribute \src "libresoc.v:151737.18-151737.90" - wire width 130 $pos$libresoc.v:151737$7872_Y - attribute \src "libresoc.v:151747.18-151747.95" - wire width 2 $pos$libresoc.v:151747$7883_Y - attribute \src "libresoc.v:151740.18-151740.106" - wire $reduce_and$libresoc.v:151740$7875_Y - attribute \src "libresoc.v:151744.18-151744.107" - wire $reduce_and$libresoc.v:151744$7879_Y - attribute \src "libresoc.v:151739.18-151739.106" - wire $reduce_or$libresoc.v:151739$7874_Y - attribute \src "libresoc.v:151743.18-151743.107" - wire $reduce_or$libresoc.v:151743$7878_Y - attribute \src "libresoc.v:151738.18-151738.114" - wire width 130 $ternary$libresoc.v:151738$7873_Y + attribute \src "libresoc.v:153374.18-153374.104" + wire $and$libresoc.v:153374$7925_Y + attribute \src "libresoc.v:153378.18-153378.104" + wire $and$libresoc.v:153378$7929_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $extend$libresoc.v:153368$7917_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $extend$libresoc.v:153369$7919_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $extend$libresoc.v:153379$7930_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $neg$libresoc.v:153368$7918_Y + attribute \src "libresoc.v:153373.18-153373.98" + wire $not$libresoc.v:153373$7924_Y + attribute \src "libresoc.v:153377.18-153377.98" + wire $not$libresoc.v:153377$7928_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $pos$libresoc.v:153369$7920_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $pos$libresoc.v:153379$7931_Y + attribute \src "libresoc.v:153372.18-153372.106" + wire $reduce_and$libresoc.v:153372$7923_Y + attribute \src "libresoc.v:153376.18-153376.107" + wire $reduce_and$libresoc.v:153376$7927_Y + attribute \src "libresoc.v:153371.18-153371.106" + wire $reduce_or$libresoc.v:153371$7922_Y + attribute \src "libresoc.v:153375.18-153375.107" + wire $reduce_or$libresoc.v:153375$7926_Y + attribute \src "libresoc.v:153370.18-153370.114" + wire width 130 $ternary$libresoc.v:153370$7921_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -317733,7 +320230,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:151449.7-151449.15" + attribute \src "libresoc.v:153081.7-153081.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -317992,7 +320489,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:151742$7877 + cell $and $and$libresoc.v:153374$7925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318000,10 +320497,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:151742$7877_Y + connect \Y $and$libresoc.v:153374$7925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:151746$7881 + cell $and $and$libresoc.v:153378$7929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318011,128 +320508,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:151746$7881_Y + connect \Y $and$libresoc.v:153378$7929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:151736$7869 + cell $pos $extend$libresoc.v:153368$7917 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:151736$7869_Y + connect \Y $extend$libresoc.v:153368$7917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151737$7871 + cell $pos $extend$libresoc.v:153369$7919 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:151737$7871_Y + connect \Y $extend$libresoc.v:153369$7919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151747$7882 + cell $pos $extend$libresoc.v:153379$7930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:151747$7882_Y + connect \Y $extend$libresoc.v:153379$7930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:151736$7870 + cell $neg $neg$libresoc.v:153368$7918 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:151736$7869_Y - connect \Y $neg$libresoc.v:151736$7870_Y + connect \A $extend$libresoc.v:153368$7917_Y + connect \Y $neg$libresoc.v:153368$7918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:151741$7876 + cell $not $not$libresoc.v:153373$7924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:151741$7876_Y + connect \Y $not$libresoc.v:153373$7924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:151745$7880 + cell $not $not$libresoc.v:153377$7928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:151745$7880_Y + connect \Y $not$libresoc.v:153377$7928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151737$7872 + cell $pos $pos$libresoc.v:153369$7920 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:151737$7871_Y - connect \Y $pos$libresoc.v:151737$7872_Y + connect \A $extend$libresoc.v:153369$7919_Y + connect \Y $pos$libresoc.v:153369$7920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151747$7883 + cell $pos $pos$libresoc.v:153379$7931 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:151747$7882_Y - connect \Y $pos$libresoc.v:151747$7883_Y + connect \A $extend$libresoc.v:153379$7930_Y + connect \Y $pos$libresoc.v:153379$7931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:151740$7875 + cell $reduce_and $reduce_and$libresoc.v:153372$7923 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:151740$7875_Y + connect \Y $reduce_and$libresoc.v:153372$7923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:151744$7879 + cell $reduce_and $reduce_and$libresoc.v:153376$7927 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:151744$7879_Y + connect \Y $reduce_and$libresoc.v:153376$7927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:151739$7874 + cell $reduce_or $reduce_or$libresoc.v:153371$7922 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:151739$7874_Y + connect \Y $reduce_or$libresoc.v:153371$7922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:151743$7878 + cell $reduce_or $reduce_or$libresoc.v:153375$7926 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:151743$7878_Y + connect \Y $reduce_or$libresoc.v:153375$7926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:151738$7873 + cell $mux $ternary$libresoc.v:153370$7921 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:151738$7873_Y + connect \Y $ternary$libresoc.v:153370$7921_Y end - attribute \src "libresoc.v:151449.7-151449.20" - process $proc$libresoc.v:151449$7891 + attribute \src "libresoc.v:153081.7-153081.20" + process $proc$libresoc.v:153081$7939 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151748.3-151766.6" - process $proc$libresoc.v:151748$7884 + attribute \src "libresoc.v:153380.3-153398.6" + process $proc$libresoc.v:153380$7932 assign { } { } assign { } { } - assign $0\o$14[63:0]$7885 $1\o$14[63:0]$7886 - attribute \src "libresoc.v:151749.5-151749.29" + assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 + attribute \src "libresoc.v:153381.5-153381.29" switch \initial - attribute \src "libresoc.v:151749.9-151749.17" + attribute \src "libresoc.v:153381.9-153381.17" case 1'1 case end @@ -318141,29 +320638,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7886 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7934 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7886 \mul_o [127:64] + assign $1\o$14[63:0]$7934 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7886 \mul_o [63:0] + assign $1\o$14[63:0]$7934 \mul_o [63:0] case - assign $1\o$14[63:0]$7886 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7934 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7885 + update \o$14 $0\o$14[63:0]$7933 end - attribute \src "libresoc.v:151767.3-151785.6" - process $proc$libresoc.v:151767$7887 + attribute \src "libresoc.v:153399.3-153417.6" + process $proc$libresoc.v:153399$7935 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:151768.5-151768.29" + attribute \src "libresoc.v:153400.5-153400.29" switch \initial - attribute \src "libresoc.v:151768.9-151768.17" + attribute \src "libresoc.v:153400.9-153400.17" case 1'1 case end @@ -318187,14 +320684,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:151786.3-151804.6" - process $proc$libresoc.v:151786$7888 + attribute \src "libresoc.v:153418.3-153436.6" + process $proc$libresoc.v:153418$7936 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:151787.5-151787.29" + attribute \src "libresoc.v:153419.5-153419.29" switch \initial - attribute \src "libresoc.v:151787.9-151787.17" + attribute \src "libresoc.v:153419.9-153419.17" case 1'1 case end @@ -318221,14 +320718,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:151805.3-151815.6" - process $proc$libresoc.v:151805$7889 + attribute \src "libresoc.v:153437.3-153447.6" + process $proc$libresoc.v:153437$7937 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:151806.5-151806.29" + attribute \src "libresoc.v:153438.5-153438.29" switch \initial - attribute \src "libresoc.v:151806.9-151806.17" + attribute \src "libresoc.v:153438.9-153438.17" case 1'1 case end @@ -318244,14 +320741,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:151816.3-151826.6" - process $proc$libresoc.v:151816$7890 + attribute \src "libresoc.v:153448.3-153458.6" + process $proc$libresoc.v:153448$7938 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:151817.5-151817.29" + attribute \src "libresoc.v:153449.5-153449.29" switch \initial - attribute \src "libresoc.v:151817.9-151817.17" + attribute \src "libresoc.v:153449.9-153449.17" case 1'1 case end @@ -318267,18 +320764,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:151736$7870_Y - connect \$19 $pos$libresoc.v:151737$7872_Y - connect \$21 $ternary$libresoc.v:151738$7873_Y - connect \$23 $reduce_or$libresoc.v:151739$7874_Y - connect \$26 $reduce_and$libresoc.v:151740$7875_Y - connect \$25 $not$libresoc.v:151741$7876_Y - connect \$29 $and$libresoc.v:151742$7877_Y - connect \$31 $reduce_or$libresoc.v:151743$7878_Y - connect \$34 $reduce_and$libresoc.v:151744$7879_Y - connect \$33 $not$libresoc.v:151745$7880_Y - connect \$37 $and$libresoc.v:151746$7881_Y - connect \$39 $pos$libresoc.v:151747$7883_Y + connect \$17 $neg$libresoc.v:153368$7918_Y + connect \$19 $pos$libresoc.v:153369$7920_Y + connect \$21 $ternary$libresoc.v:153370$7921_Y + connect \$23 $reduce_or$libresoc.v:153371$7922_Y + connect \$26 $reduce_and$libresoc.v:153372$7923_Y + connect \$25 $not$libresoc.v:153373$7924_Y + connect \$29 $and$libresoc.v:153374$7925_Y + connect \$31 $reduce_or$libresoc.v:153375$7926_Y + connect \$34 $reduce_and$libresoc.v:153376$7927_Y + connect \$33 $not$libresoc.v:153377$7928_Y + connect \$37 $and$libresoc.v:153378$7929_Y + connect \$39 $pos$libresoc.v:153379$7931_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -318286,188 +320783,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:151837.1-153054.10" +attribute \src "libresoc.v:153469.1-154686.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:151838.7-151838.20" + attribute \src "libresoc.v:153470.7-153470.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 14 $0\mul_op__fn_unit$next[13:0]$7920 - attribute \src "libresoc.v:152796.3-152797.47" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 + attribute \src "libresoc.v:154428.3-154429.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7921 - attribute \src "libresoc.v:152798.3-152799.61" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 + attribute \src "libresoc.v:154430.3-154431.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7922 - attribute \src "libresoc.v:152800.3-152801.57" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7970 + attribute \src "libresoc.v:154432.3-154433.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 32 $0\mul_op__insn$next[31:0]$7923 - attribute \src "libresoc.v:152816.3-152817.41" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $0\mul_op__insn$next[31:0]$7971 + attribute \src "libresoc.v:154448.3-154449.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7924 - attribute \src "libresoc.v:152794.3-152795.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7972 + attribute \src "libresoc.v:154426.3-154427.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__is_32bit$next[0:0]$7925 - attribute \src "libresoc.v:152812.3-152813.49" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_32bit$next[0:0]$7973 + attribute \src "libresoc.v:154444.3-154445.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__is_signed$next[0:0]$7926 - attribute \src "libresoc.v:152814.3-152815.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_signed$next[0:0]$7974 + attribute \src "libresoc.v:154446.3-154447.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__oe__oe$next[0:0]$7927 - attribute \src "libresoc.v:152806.3-152807.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__oe$next[0:0]$7975 + attribute \src "libresoc.v:154438.3-154439.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__oe__ok$next[0:0]$7928 - attribute \src "libresoc.v:152808.3-152809.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__ok$next[0:0]$7976 + attribute \src "libresoc.v:154440.3-154441.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__rc__ok$next[0:0]$7929 - attribute \src "libresoc.v:152804.3-152805.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__ok$next[0:0]$7977 + attribute \src "libresoc.v:154436.3-154437.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__rc__rc$next[0:0]$7930 - attribute \src "libresoc.v:152802.3-152803.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__rc$next[0:0]$7978 + attribute \src "libresoc.v:154434.3-154435.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__write_cr0$next[0:0]$7931 - attribute \src "libresoc.v:152810.3-152811.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__write_cr0$next[0:0]$7979 + attribute \src "libresoc.v:154442.3-154443.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152918.3-152930.6" - wire width 2 $0\muxid$next[1:0]$7917 - attribute \src "libresoc.v:152818.3-152819.27" + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $0\muxid$next[1:0]$7965 + attribute \src "libresoc.v:154450.3-154451.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:153006.3-153018.6" - wire $0\neg_res$next[0:0]$7960 - attribute \src "libresoc.v:153019.3-153031.6" - wire $0\neg_res32$next[0:0]$7963 - attribute \src "libresoc.v:152784.3-152785.35" + attribute \src "libresoc.v:154638.3-154650.6" + wire $0\neg_res$next[0:0]$8008 + attribute \src "libresoc.v:154651.3-154663.6" + wire $0\neg_res32$next[0:0]$8011 + attribute \src "libresoc.v:154416.3-154417.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:152786.3-152787.31" + attribute \src "libresoc.v:154418.3-154419.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:152900.3-152917.6" - wire $0\r_busy$next[0:0]$7913 - attribute \src "libresoc.v:152820.3-152821.29" + attribute \src "libresoc.v:154532.3-154549.6" + wire $0\r_busy$next[0:0]$7961 + attribute \src "libresoc.v:154452.3-154453.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:152967.3-152979.6" - wire width 64 $0\ra$next[63:0]$7951 - attribute \src "libresoc.v:152792.3-152793.21" + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $0\ra$next[63:0]$7999 + attribute \src "libresoc.v:154424.3-154425.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:152980.3-152992.6" - wire width 64 $0\rb$next[63:0]$7954 - attribute \src "libresoc.v:152790.3-152791.21" + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $0\rb$next[63:0]$8002 + attribute \src "libresoc.v:154422.3-154423.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:152993.3-153005.6" - wire $0\xer_so$next[0:0]$7957 - attribute \src "libresoc.v:152788.3-152789.29" + attribute \src "libresoc.v:154625.3-154637.6" + wire $0\xer_so$next[0:0]$8005 + attribute \src "libresoc.v:154420.3-154421.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 14 $1\mul_op__fn_unit$next[13:0]$7932 - attribute \src "libresoc.v:152354.14-152354.40" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 + attribute \src "libresoc.v:153986.14-153986.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7933 - attribute \src "libresoc.v:152393.14-152393.59" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 + attribute \src "libresoc.v:154025.14-154025.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7934 - attribute \src "libresoc.v:152402.7-152402.34" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7982 + attribute \src "libresoc.v:154034.7-154034.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 32 $1\mul_op__insn$next[31:0]$7935 - attribute \src "libresoc.v:152411.14-152411.34" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $1\mul_op__insn$next[31:0]$7983 + attribute \src "libresoc.v:154043.14-154043.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7936 - attribute \src "libresoc.v:152495.13-152495.38" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7984 + attribute \src "libresoc.v:154127.13-154127.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__is_32bit$next[0:0]$7937 - attribute \src "libresoc.v:152654.7-152654.30" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_32bit$next[0:0]$7985 + attribute \src "libresoc.v:154286.7-154286.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__is_signed$next[0:0]$7938 - attribute \src "libresoc.v:152663.7-152663.31" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_signed$next[0:0]$7986 + attribute \src "libresoc.v:154295.7-154295.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__oe__oe$next[0:0]$7939 - attribute \src "libresoc.v:152672.7-152672.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__oe$next[0:0]$7987 + attribute \src "libresoc.v:154304.7-154304.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__oe__ok$next[0:0]$7940 - attribute \src "libresoc.v:152681.7-152681.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__ok$next[0:0]$7988 + attribute \src "libresoc.v:154313.7-154313.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__rc__ok$next[0:0]$7941 - attribute \src "libresoc.v:152690.7-152690.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__ok$next[0:0]$7989 + attribute \src "libresoc.v:154322.7-154322.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__rc__rc$next[0:0]$7942 - attribute \src "libresoc.v:152699.7-152699.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__rc$next[0:0]$7990 + attribute \src "libresoc.v:154331.7-154331.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__write_cr0$next[0:0]$7943 - attribute \src "libresoc.v:152708.7-152708.31" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__write_cr0$next[0:0]$7991 + attribute \src "libresoc.v:154340.7-154340.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152918.3-152930.6" - wire width 2 $1\muxid$next[1:0]$7918 - attribute \src "libresoc.v:152717.13-152717.25" + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154349.13-154349.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:153006.3-153018.6" - wire $1\neg_res$next[0:0]$7961 - attribute \src "libresoc.v:153019.3-153031.6" - wire $1\neg_res32$next[0:0]$7964 - attribute \src "libresoc.v:152739.7-152739.23" + attribute \src "libresoc.v:154638.3-154650.6" + wire $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154651.3-154663.6" + wire $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154371.7-154371.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:152732.7-152732.21" + attribute \src "libresoc.v:154364.7-154364.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:152900.3-152917.6" - wire $1\r_busy$next[0:0]$7914 - attribute \src "libresoc.v:152753.7-152753.20" + attribute \src "libresoc.v:154532.3-154549.6" + wire $1\r_busy$next[0:0]$7962 + attribute \src "libresoc.v:154385.7-154385.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:152967.3-152979.6" - wire width 64 $1\ra$next[63:0]$7952 - attribute \src "libresoc.v:152758.14-152758.39" + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154390.14-154390.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:152980.3-152992.6" - wire width 64 $1\rb$next[63:0]$7955 - attribute \src "libresoc.v:152767.14-152767.39" + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154399.14-154399.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:152993.3-153005.6" - wire $1\xer_so$next[0:0]$7958 - attribute \src "libresoc.v:152776.7-152776.20" + attribute \src "libresoc.v:154625.3-154637.6" + wire $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154408.7-154408.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7944 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7945 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__oe__oe$next[0:0]$7946 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__oe__ok$next[0:0]$7947 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__rc__ok$next[0:0]$7948 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__rc__rc$next[0:0]$7949 - attribute \src "libresoc.v:152900.3-152917.6" - wire $2\r_busy$next[0:0]$7915 - attribute \src "libresoc.v:152783.18-152783.118" - wire $and$libresoc.v:152783$7892_Y + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7993 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__oe$next[0:0]$7994 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__ok$next[0:0]$7995 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__ok$next[0:0]$7996 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154532.3-154549.6" + wire $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154415.18-154415.118" + wire $and$libresoc.v:154415$7940_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:151838.7-151838.15" + attribute \src "libresoc.v:153470.7-153470.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -319390,7 +321887,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:152783$7892 + cell $and $and$libresoc.v:154415$7940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319398,10 +321895,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:152783$7892_Y + connect \Y $and$libresoc.v:154415$7940_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152822.14-152855.4" + attribute \src "libresoc.v:154454.14-154487.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -319437,7 +321934,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:152856.8-152891.4" + attribute \src "libresoc.v:154488.8-154523.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -319475,319 +321972,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:152892.10-152895.4" + attribute \src "libresoc.v:154524.10-154527.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:152896.10-152899.4" + attribute \src "libresoc.v:154528.10-154531.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:151838.7-151838.20" - process $proc$libresoc.v:151838$7965 + attribute \src "libresoc.v:153470.7-153470.20" + process $proc$libresoc.v:153470$8013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152354.14-152354.40" - process $proc$libresoc.v:152354$7966 + attribute \src "libresoc.v:153986.14-153986.40" + process $proc$libresoc.v:153986$8014 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152393.14-152393.59" - process $proc$libresoc.v:152393$7967 + attribute \src "libresoc.v:154025.14-154025.59" + process $proc$libresoc.v:154025$8015 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152402.7-152402.34" - process $proc$libresoc.v:152402$7968 + attribute \src "libresoc.v:154034.7-154034.34" + process $proc$libresoc.v:154034$8016 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152411.14-152411.34" - process $proc$libresoc.v:152411$7969 + attribute \src "libresoc.v:154043.14-154043.34" + process $proc$libresoc.v:154043$8017 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:152495.13-152495.38" - process $proc$libresoc.v:152495$7970 + attribute \src "libresoc.v:154127.13-154127.38" + process $proc$libresoc.v:154127$8018 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152654.7-152654.30" - process $proc$libresoc.v:152654$7971 + attribute \src "libresoc.v:154286.7-154286.30" + process $proc$libresoc.v:154286$8019 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152663.7-152663.31" - process $proc$libresoc.v:152663$7972 + attribute \src "libresoc.v:154295.7-154295.31" + process $proc$libresoc.v:154295$8020 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152672.7-152672.28" - process $proc$libresoc.v:152672$7973 + attribute \src "libresoc.v:154304.7-154304.28" + process $proc$libresoc.v:154304$8021 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152681.7-152681.28" - process $proc$libresoc.v:152681$7974 + attribute \src "libresoc.v:154313.7-154313.28" + process $proc$libresoc.v:154313$8022 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152690.7-152690.28" - process $proc$libresoc.v:152690$7975 + attribute \src "libresoc.v:154322.7-154322.28" + process $proc$libresoc.v:154322$8023 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152699.7-152699.28" - process $proc$libresoc.v:152699$7976 + attribute \src "libresoc.v:154331.7-154331.28" + process $proc$libresoc.v:154331$8024 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152708.7-152708.31" - process $proc$libresoc.v:152708$7977 + attribute \src "libresoc.v:154340.7-154340.31" + process $proc$libresoc.v:154340$8025 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152717.13-152717.25" - process $proc$libresoc.v:152717$7978 + attribute \src "libresoc.v:154349.13-154349.25" + process $proc$libresoc.v:154349$8026 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:152732.7-152732.21" - process $proc$libresoc.v:152732$7979 + attribute \src "libresoc.v:154364.7-154364.21" + process $proc$libresoc.v:154364$8027 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:152739.7-152739.23" - process $proc$libresoc.v:152739$7980 + attribute \src "libresoc.v:154371.7-154371.23" + process $proc$libresoc.v:154371$8028 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:152753.7-152753.20" - process $proc$libresoc.v:152753$7981 + attribute \src "libresoc.v:154385.7-154385.20" + process $proc$libresoc.v:154385$8029 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:152758.14-152758.39" - process $proc$libresoc.v:152758$7982 + attribute \src "libresoc.v:154390.14-154390.39" + process $proc$libresoc.v:154390$8030 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:152767.14-152767.39" - process $proc$libresoc.v:152767$7983 + attribute \src "libresoc.v:154399.14-154399.39" + process $proc$libresoc.v:154399$8031 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:152776.7-152776.20" - process $proc$libresoc.v:152776$7984 + attribute \src "libresoc.v:154408.7-154408.20" + process $proc$libresoc.v:154408$8032 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:152784.3-152785.35" - process $proc$libresoc.v:152784$7893 + attribute \src "libresoc.v:154416.3-154417.35" + process $proc$libresoc.v:154416$7941 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:152786.3-152787.31" - process $proc$libresoc.v:152786$7894 + attribute \src "libresoc.v:154418.3-154419.31" + process $proc$libresoc.v:154418$7942 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:152788.3-152789.29" - process $proc$libresoc.v:152788$7895 + attribute \src "libresoc.v:154420.3-154421.29" + process $proc$libresoc.v:154420$7943 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:152790.3-152791.21" - process $proc$libresoc.v:152790$7896 + attribute \src "libresoc.v:154422.3-154423.21" + process $proc$libresoc.v:154422$7944 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:152792.3-152793.21" - process $proc$libresoc.v:152792$7897 + attribute \src "libresoc.v:154424.3-154425.21" + process $proc$libresoc.v:154424$7945 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:152794.3-152795.51" - process $proc$libresoc.v:152794$7898 + attribute \src "libresoc.v:154426.3-154427.51" + process $proc$libresoc.v:154426$7946 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152796.3-152797.47" - process $proc$libresoc.v:152796$7899 + attribute \src "libresoc.v:154428.3-154429.47" + process $proc$libresoc.v:154428$7947 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152798.3-152799.61" - process $proc$libresoc.v:152798$7900 + attribute \src "libresoc.v:154430.3-154431.61" + process $proc$libresoc.v:154430$7948 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152800.3-152801.57" - process $proc$libresoc.v:152800$7901 + attribute \src "libresoc.v:154432.3-154433.57" + process $proc$libresoc.v:154432$7949 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152802.3-152803.45" - process $proc$libresoc.v:152802$7902 + attribute \src "libresoc.v:154434.3-154435.45" + process $proc$libresoc.v:154434$7950 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152804.3-152805.45" - process $proc$libresoc.v:152804$7903 + attribute \src "libresoc.v:154436.3-154437.45" + process $proc$libresoc.v:154436$7951 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152806.3-152807.45" - process $proc$libresoc.v:152806$7904 + attribute \src "libresoc.v:154438.3-154439.45" + process $proc$libresoc.v:154438$7952 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152808.3-152809.45" - process $proc$libresoc.v:152808$7905 + attribute \src "libresoc.v:154440.3-154441.45" + process $proc$libresoc.v:154440$7953 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152810.3-152811.51" - process $proc$libresoc.v:152810$7906 + attribute \src "libresoc.v:154442.3-154443.51" + process $proc$libresoc.v:154442$7954 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152812.3-152813.49" - process $proc$libresoc.v:152812$7907 + attribute \src "libresoc.v:154444.3-154445.49" + process $proc$libresoc.v:154444$7955 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152814.3-152815.51" - process $proc$libresoc.v:152814$7908 + attribute \src "libresoc.v:154446.3-154447.51" + process $proc$libresoc.v:154446$7956 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152816.3-152817.41" - process $proc$libresoc.v:152816$7909 + attribute \src "libresoc.v:154448.3-154449.41" + process $proc$libresoc.v:154448$7957 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:152818.3-152819.27" - process $proc$libresoc.v:152818$7910 + attribute \src "libresoc.v:154450.3-154451.27" + process $proc$libresoc.v:154450$7958 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:152820.3-152821.29" - process $proc$libresoc.v:152820$7911 + attribute \src "libresoc.v:154452.3-154453.29" + process $proc$libresoc.v:154452$7959 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:152900.3-152917.6" - process $proc$libresoc.v:152900$7912 + attribute \src "libresoc.v:154532.3-154549.6" + process $proc$libresoc.v:154532$7960 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7913 $2\r_busy$next[0:0]$7915 - attribute \src "libresoc.v:152901.5-152901.29" + assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154533.5-154533.29" switch \initial - attribute \src "libresoc.v:152901.9-152901.17" + attribute \src "libresoc.v:154533.9-154533.17" case 1'1 case end @@ -319796,34 +322293,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7914 1'1 + assign $1\r_busy$next[0:0]$7962 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7914 1'0 + assign $1\r_busy$next[0:0]$7962 1'0 case - assign $1\r_busy$next[0:0]$7914 \r_busy + assign $1\r_busy$next[0:0]$7962 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7915 1'0 + assign $2\r_busy$next[0:0]$7963 1'0 case - assign $2\r_busy$next[0:0]$7915 $1\r_busy$next[0:0]$7914 + assign $2\r_busy$next[0:0]$7963 $1\r_busy$next[0:0]$7962 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7913 + update \r_busy$next $0\r_busy$next[0:0]$7961 end - attribute \src "libresoc.v:152918.3-152930.6" - process $proc$libresoc.v:152918$7916 + attribute \src "libresoc.v:154550.3-154562.6" + process $proc$libresoc.v:154550$7964 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7917 $1\muxid$next[1:0]$7918 - attribute \src "libresoc.v:152919.5-152919.29" + assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154551.5-154551.29" switch \initial - attribute \src "libresoc.v:152919.9-152919.17" + attribute \src "libresoc.v:154551.9-154551.17" case 1'1 case end @@ -319832,19 +322329,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7918 \muxid$52 + assign $1\muxid$next[1:0]$7966 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7918 \muxid$52 + assign $1\muxid$next[1:0]$7966 \muxid$52 case - assign $1\muxid$next[1:0]$7918 \muxid + assign $1\muxid$next[1:0]$7966 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7917 + update \muxid$next $0\muxid$next[1:0]$7965 end - attribute \src "libresoc.v:152931.3-152966.6" - process $proc$libresoc.v:152931$7919 + attribute \src "libresoc.v:154563.3-154598.6" + process $proc$libresoc.v:154563$7967 assign { } { } assign { } { } assign { } { } @@ -319869,27 +322366,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[13:0]$7920 $1\mul_op__fn_unit$next[13:0]$7932 + assign $0\mul_op__fn_unit$next[13:0]$7968 $1\mul_op__fn_unit$next[13:0]$7980 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7923 $1\mul_op__insn$next[31:0]$7935 - assign $0\mul_op__insn_type$next[6:0]$7924 $1\mul_op__insn_type$next[6:0]$7936 - assign $0\mul_op__is_32bit$next[0:0]$7925 $1\mul_op__is_32bit$next[0:0]$7937 - assign $0\mul_op__is_signed$next[0:0]$7926 $1\mul_op__is_signed$next[0:0]$7938 + assign $0\mul_op__insn$next[31:0]$7971 $1\mul_op__insn$next[31:0]$7983 + assign $0\mul_op__insn_type$next[6:0]$7972 $1\mul_op__insn_type$next[6:0]$7984 + assign $0\mul_op__is_32bit$next[0:0]$7973 $1\mul_op__is_32bit$next[0:0]$7985 + assign $0\mul_op__is_signed$next[0:0]$7974 $1\mul_op__is_signed$next[0:0]$7986 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7931 $1\mul_op__write_cr0$next[0:0]$7943 - assign $0\mul_op__imm_data__data$next[63:0]$7921 $2\mul_op__imm_data__data$next[63:0]$7944 - assign $0\mul_op__imm_data__ok$next[0:0]$7922 $2\mul_op__imm_data__ok$next[0:0]$7945 - assign $0\mul_op__oe__oe$next[0:0]$7927 $2\mul_op__oe__oe$next[0:0]$7946 - assign $0\mul_op__oe__ok$next[0:0]$7928 $2\mul_op__oe__ok$next[0:0]$7947 - assign $0\mul_op__rc__ok$next[0:0]$7929 $2\mul_op__rc__ok$next[0:0]$7948 - assign $0\mul_op__rc__rc$next[0:0]$7930 $2\mul_op__rc__rc$next[0:0]$7949 - attribute \src "libresoc.v:152932.5-152932.29" + assign $0\mul_op__write_cr0$next[0:0]$7979 $1\mul_op__write_cr0$next[0:0]$7991 + assign $0\mul_op__imm_data__data$next[63:0]$7969 $2\mul_op__imm_data__data$next[63:0]$7992 + assign $0\mul_op__imm_data__ok$next[0:0]$7970 $2\mul_op__imm_data__ok$next[0:0]$7993 + assign $0\mul_op__oe__oe$next[0:0]$7975 $2\mul_op__oe__oe$next[0:0]$7994 + assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 + assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 + assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154564.5-154564.29" switch \initial - attribute \src "libresoc.v:152932.9-152932.17" + attribute \src "libresoc.v:154564.9-154564.17" case 1'1 case end @@ -319909,7 +322406,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -319924,20 +322421,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[13:0]$7932 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7933 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7934 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7935 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7936 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7937 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7938 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7939 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7940 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7941 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7942 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7943 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7980 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7981 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7982 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7983 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7984 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7985 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7986 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7987 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7988 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7989 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7990 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7991 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -319949,42 +322446,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7944 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7945 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7949 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7948 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7946 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7947 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7992 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7997 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7996 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7994 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7995 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7944 $1\mul_op__imm_data__data$next[63:0]$7933 - assign $2\mul_op__imm_data__ok$next[0:0]$7945 $1\mul_op__imm_data__ok$next[0:0]$7934 - assign $2\mul_op__oe__oe$next[0:0]$7946 $1\mul_op__oe__oe$next[0:0]$7939 - assign $2\mul_op__oe__ok$next[0:0]$7947 $1\mul_op__oe__ok$next[0:0]$7940 - assign $2\mul_op__rc__ok$next[0:0]$7948 $1\mul_op__rc__ok$next[0:0]$7941 - assign $2\mul_op__rc__rc$next[0:0]$7949 $1\mul_op__rc__rc$next[0:0]$7942 + assign $2\mul_op__imm_data__data$next[63:0]$7992 $1\mul_op__imm_data__data$next[63:0]$7981 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 $1\mul_op__imm_data__ok$next[0:0]$7982 + assign $2\mul_op__oe__oe$next[0:0]$7994 $1\mul_op__oe__oe$next[0:0]$7987 + assign $2\mul_op__oe__ok$next[0:0]$7995 $1\mul_op__oe__ok$next[0:0]$7988 + assign $2\mul_op__rc__ok$next[0:0]$7996 $1\mul_op__rc__ok$next[0:0]$7989 + assign $2\mul_op__rc__rc$next[0:0]$7997 $1\mul_op__rc__rc$next[0:0]$7990 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7920 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7921 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7922 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7923 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7924 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7925 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7926 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7927 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7928 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7929 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7930 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7931 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7968 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7969 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7970 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7971 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7972 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7973 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7974 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7975 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7976 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7977 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 end - attribute \src "libresoc.v:152967.3-152979.6" - process $proc$libresoc.v:152967$7950 + attribute \src "libresoc.v:154599.3-154611.6" + process $proc$libresoc.v:154599$7998 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7951 $1\ra$next[63:0]$7952 - attribute \src "libresoc.v:152968.5-152968.29" + assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154600.5-154600.29" switch \initial - attribute \src "libresoc.v:152968.9-152968.17" + attribute \src "libresoc.v:154600.9-154600.17" case 1'1 case end @@ -319993,25 +322490,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$7952 \ra$65 + assign $1\ra$next[63:0]$8000 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$7952 \ra$65 + assign $1\ra$next[63:0]$8000 \ra$65 case - assign $1\ra$next[63:0]$7952 \ra + assign $1\ra$next[63:0]$8000 \ra end sync always - update \ra$next $0\ra$next[63:0]$7951 + update \ra$next $0\ra$next[63:0]$7999 end - attribute \src "libresoc.v:152980.3-152992.6" - process $proc$libresoc.v:152980$7953 + attribute \src "libresoc.v:154612.3-154624.6" + process $proc$libresoc.v:154612$8001 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7954 $1\rb$next[63:0]$7955 - attribute \src "libresoc.v:152981.5-152981.29" + assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154613.5-154613.29" switch \initial - attribute \src "libresoc.v:152981.9-152981.17" + attribute \src "libresoc.v:154613.9-154613.17" case 1'1 case end @@ -320020,25 +322517,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$7955 \rb$66 + assign $1\rb$next[63:0]$8003 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$7955 \rb$66 + assign $1\rb$next[63:0]$8003 \rb$66 case - assign $1\rb$next[63:0]$7955 \rb + assign $1\rb$next[63:0]$8003 \rb end sync always - update \rb$next $0\rb$next[63:0]$7954 + update \rb$next $0\rb$next[63:0]$8002 end - attribute \src "libresoc.v:152993.3-153005.6" - process $proc$libresoc.v:152993$7956 + attribute \src "libresoc.v:154625.3-154637.6" + process $proc$libresoc.v:154625$8004 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$7957 $1\xer_so$next[0:0]$7958 - attribute \src "libresoc.v:152994.5-152994.29" + assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154626.5-154626.29" switch \initial - attribute \src "libresoc.v:152994.9-152994.17" + attribute \src "libresoc.v:154626.9-154626.17" case 1'1 case end @@ -320047,25 +322544,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$7958 \xer_so$67 + assign $1\xer_so$next[0:0]$8006 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$7958 \xer_so$67 + assign $1\xer_so$next[0:0]$8006 \xer_so$67 case - assign $1\xer_so$next[0:0]$7958 \xer_so + assign $1\xer_so$next[0:0]$8006 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$7957 + update \xer_so$next $0\xer_so$next[0:0]$8005 end - attribute \src "libresoc.v:153006.3-153018.6" - process $proc$libresoc.v:153006$7959 + attribute \src "libresoc.v:154638.3-154650.6" + process $proc$libresoc.v:154638$8007 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$7960 $1\neg_res$next[0:0]$7961 - attribute \src "libresoc.v:153007.5-153007.29" + assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154639.5-154639.29" switch \initial - attribute \src "libresoc.v:153007.9-153007.17" + attribute \src "libresoc.v:154639.9-154639.17" case 1'1 case end @@ -320074,25 +322571,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$7961 \neg_res$68 + assign $1\neg_res$next[0:0]$8009 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$7961 \neg_res$68 + assign $1\neg_res$next[0:0]$8009 \neg_res$68 case - assign $1\neg_res$next[0:0]$7961 \neg_res + assign $1\neg_res$next[0:0]$8009 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$7960 + update \neg_res$next $0\neg_res$next[0:0]$8008 end - attribute \src "libresoc.v:153019.3-153031.6" - process $proc$libresoc.v:153019$7962 + attribute \src "libresoc.v:154651.3-154663.6" + process $proc$libresoc.v:154651$8010 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$7963 $1\neg_res32$next[0:0]$7964 - attribute \src "libresoc.v:153020.5-153020.29" + assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154652.5-154652.29" switch \initial - attribute \src "libresoc.v:153020.9-153020.17" + attribute \src "libresoc.v:154652.9-154652.17" case 1'1 case end @@ -320101,18 +322598,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$7964 \neg_res32 + assign $1\neg_res32$next[0:0]$8012 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7963 + update \neg_res32$next $0\neg_res32$next[0:0]$8011 end - connect \$50 $and$libresoc.v:152783$7892_Y + connect \$50 $and$libresoc.v:154415$7940_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -320136,180 +322633,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:153058.1-153978.10" +attribute \src "libresoc.v:154690.1-155610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:153059.7-153059.20" + attribute \src "libresoc.v:154691.7-154691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153872.3-153907.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8028 - attribute \src "libresoc.v:153770.3-153771.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$7996 - attribute \src "libresoc.v:153350.14-153350.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8072 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8029 - attribute \src "libresoc.v:153772.3-153773.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7998 - attribute \src "libresoc.v:153376.14-153376.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8074 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8030 - attribute \src "libresoc.v:153774.3-153775.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8000 - attribute \src "libresoc.v:153385.7-153385.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8076 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8031 - attribute \src "libresoc.v:153790.3-153791.49" - wire width 32 $0\mul_op__insn$13[31:0]$8016 - attribute \src "libresoc.v:153392.14-153392.39" - wire width 32 $0\mul_op__insn$13[31:0]$8078 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8032 - attribute \src "libresoc.v:153768.3-153769.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7994 - attribute \src "libresoc.v:153551.13-153551.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8080 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8033 - attribute \src "libresoc.v:153786.3-153787.57" - wire $0\mul_op__is_32bit$11[0:0]$8012 - attribute \src "libresoc.v:153635.7-153635.35" - wire $0\mul_op__is_32bit$11[0:0]$8082 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__is_signed$12$next[0:0]$8034 - attribute \src "libresoc.v:153788.3-153789.59" - wire $0\mul_op__is_signed$12[0:0]$8014 - attribute \src "libresoc.v:153644.7-153644.36" - wire $0\mul_op__is_signed$12[0:0]$8084 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8035 - attribute \src "libresoc.v:153780.3-153781.51" - wire $0\mul_op__oe__oe$8[0:0]$8006 - attribute \src "libresoc.v:153655.7-153655.32" - wire $0\mul_op__oe__oe$8[0:0]$8086 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8036 - attribute \src "libresoc.v:153782.3-153783.51" - wire $0\mul_op__oe__ok$9[0:0]$8008 - attribute \src "libresoc.v:153664.7-153664.32" - wire $0\mul_op__oe__ok$9[0:0]$8088 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8037 - attribute \src "libresoc.v:153778.3-153779.51" - wire $0\mul_op__rc__ok$7[0:0]$8004 - attribute \src "libresoc.v:153673.7-153673.32" - wire $0\mul_op__rc__ok$7[0:0]$8090 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8038 - attribute \src "libresoc.v:153776.3-153777.51" - wire $0\mul_op__rc__rc$6[0:0]$8002 - attribute \src "libresoc.v:153682.7-153682.32" - wire $0\mul_op__rc__rc$6[0:0]$8092 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8039 - attribute \src "libresoc.v:153784.3-153785.59" - wire $0\mul_op__write_cr0$10[0:0]$8010 - attribute \src "libresoc.v:153689.7-153689.36" - wire $0\mul_op__write_cr0$10[0:0]$8094 - attribute \src "libresoc.v:153859.3-153871.6" - wire width 2 $0\muxid$1$next[1:0]$8025 - attribute \src "libresoc.v:153792.3-153793.33" - wire width 2 $0\muxid$1[1:0]$8018 - attribute \src "libresoc.v:153698.13-153698.29" - wire width 2 $0\muxid$1[1:0]$8096 - attribute \src "libresoc.v:153934.3-153946.6" - wire $0\neg_res$15$next[0:0]$8065 - attribute \src "libresoc.v:153762.3-153763.39" - wire $0\neg_res$15[0:0]$7989 - attribute \src "libresoc.v:153713.7-153713.26" - wire $0\neg_res$15[0:0]$8098 - attribute \src "libresoc.v:153947.3-153959.6" - wire $0\neg_res32$16$next[0:0]$8068 - attribute \src "libresoc.v:153760.3-153761.43" - wire $0\neg_res32$16[0:0]$7987 - attribute \src "libresoc.v:153722.7-153722.28" - wire $0\neg_res32$16[0:0]$8100 - attribute \src "libresoc.v:153908.3-153920.6" - wire width 129 $0\o$next[128:0]$8059 - attribute \src "libresoc.v:153766.3-153767.19" + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 + attribute \src "libresoc.v:155402.3-155403.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 + attribute \src "libresoc.v:154982.14-154982.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 + attribute \src "libresoc.v:155404.3-155405.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 + attribute \src "libresoc.v:155008.14-155008.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 + attribute \src "libresoc.v:155406.3-155407.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8048 + attribute \src "libresoc.v:155017.7-155017.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8124 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8079 + attribute \src "libresoc.v:155422.3-155423.49" + wire width 32 $0\mul_op__insn$13[31:0]$8064 + attribute \src "libresoc.v:155024.14-155024.39" + wire width 32 $0\mul_op__insn$13[31:0]$8126 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 + attribute \src "libresoc.v:155400.3-155401.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8042 + attribute \src "libresoc.v:155183.13-155183.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8128 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8081 + attribute \src "libresoc.v:155418.3-155419.57" + wire $0\mul_op__is_32bit$11[0:0]$8060 + attribute \src "libresoc.v:155267.7-155267.35" + wire $0\mul_op__is_32bit$11[0:0]$8130 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_signed$12$next[0:0]$8082 + attribute \src "libresoc.v:155420.3-155421.59" + wire $0\mul_op__is_signed$12[0:0]$8062 + attribute \src "libresoc.v:155276.7-155276.36" + wire $0\mul_op__is_signed$12[0:0]$8132 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8083 + attribute \src "libresoc.v:155412.3-155413.51" + wire $0\mul_op__oe__oe$8[0:0]$8054 + attribute \src "libresoc.v:155287.7-155287.32" + wire $0\mul_op__oe__oe$8[0:0]$8134 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8084 + attribute \src "libresoc.v:155414.3-155415.51" + wire $0\mul_op__oe__ok$9[0:0]$8056 + attribute \src "libresoc.v:155296.7-155296.32" + wire $0\mul_op__oe__ok$9[0:0]$8136 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8085 + attribute \src "libresoc.v:155410.3-155411.51" + wire $0\mul_op__rc__ok$7[0:0]$8052 + attribute \src "libresoc.v:155305.7-155305.32" + wire $0\mul_op__rc__ok$7[0:0]$8138 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8086 + attribute \src "libresoc.v:155408.3-155409.51" + wire $0\mul_op__rc__rc$6[0:0]$8050 + attribute \src "libresoc.v:155314.7-155314.32" + wire $0\mul_op__rc__rc$6[0:0]$8140 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8087 + attribute \src "libresoc.v:155416.3-155417.59" + wire $0\mul_op__write_cr0$10[0:0]$8058 + attribute \src "libresoc.v:155321.7-155321.36" + wire $0\mul_op__write_cr0$10[0:0]$8142 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $0\muxid$1$next[1:0]$8073 + attribute \src "libresoc.v:155424.3-155425.33" + wire width 2 $0\muxid$1[1:0]$8066 + attribute \src "libresoc.v:155330.13-155330.29" + wire width 2 $0\muxid$1[1:0]$8144 + attribute \src "libresoc.v:155566.3-155578.6" + wire $0\neg_res$15$next[0:0]$8113 + attribute \src "libresoc.v:155394.3-155395.39" + wire $0\neg_res$15[0:0]$8037 + attribute \src "libresoc.v:155345.7-155345.26" + wire $0\neg_res$15[0:0]$8146 + attribute \src "libresoc.v:155579.3-155591.6" + wire $0\neg_res32$16$next[0:0]$8116 + attribute \src "libresoc.v:155392.3-155393.43" + wire $0\neg_res32$16[0:0]$8035 + attribute \src "libresoc.v:155354.7-155354.28" + wire $0\neg_res32$16[0:0]$8148 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $0\o$next[128:0]$8107 + attribute \src "libresoc.v:155398.3-155399.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:153841.3-153858.6" - wire $0\r_busy$next[0:0]$8021 - attribute \src "libresoc.v:153794.3-153795.29" + attribute \src "libresoc.v:155473.3-155490.6" + wire $0\r_busy$next[0:0]$8069 + attribute \src "libresoc.v:155426.3-155427.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:153921.3-153933.6" - wire $0\xer_so$14$next[0:0]$8062 - attribute \src "libresoc.v:153764.3-153765.37" - wire $0\xer_so$14[0:0]$7991 - attribute \src "libresoc.v:153754.7-153754.25" - wire $0\xer_so$14[0:0]$8104 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8040 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8041 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8042 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8043 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8044 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8045 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__is_signed$12$next[0:0]$8046 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8047 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8048 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8049 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8050 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8051 - attribute \src "libresoc.v:153859.3-153871.6" - wire width 2 $1\muxid$1$next[1:0]$8026 - attribute \src "libresoc.v:153934.3-153946.6" - wire $1\neg_res$15$next[0:0]$8066 - attribute \src "libresoc.v:153947.3-153959.6" - wire $1\neg_res32$16$next[0:0]$8069 - attribute \src "libresoc.v:153908.3-153920.6" - wire width 129 $1\o$next[128:0]$8060 - attribute \src "libresoc.v:153729.15-153729.57" + attribute \src "libresoc.v:155553.3-155565.6" + wire $0\xer_so$14$next[0:0]$8110 + attribute \src "libresoc.v:155396.3-155397.37" + wire $0\xer_so$14[0:0]$8039 + attribute \src "libresoc.v:155386.7-155386.25" + wire $0\xer_so$14[0:0]$8152 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8091 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8093 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_signed$12$next[0:0]$8094 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8095 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8096 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8097 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8098 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8099 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155566.3-155578.6" + wire $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155579.3-155591.6" + wire $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155361.15-155361.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:153841.3-153858.6" - wire $1\r_busy$next[0:0]$8022 - attribute \src "libresoc.v:153743.7-153743.20" + attribute \src "libresoc.v:155473.3-155490.6" + wire $1\r_busy$next[0:0]$8070 + attribute \src "libresoc.v:155375.7-155375.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:153921.3-153933.6" - wire $1\xer_so$14$next[0:0]$8063 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8052 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8053 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8054 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8055 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8056 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8057 - attribute \src "libresoc.v:153841.3-153858.6" - wire $2\r_busy$next[0:0]$8023 - attribute \src "libresoc.v:153759.18-153759.118" - wire $and$libresoc.v:153759$7985_Y + attribute \src "libresoc.v:155553.3-155565.6" + wire $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8102 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8103 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8104 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155473.3-155490.6" + wire $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155391.18-155391.118" + wire $and$libresoc.v:155391$8033_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:153059.7-153059.15" + attribute \src "libresoc.v:154691.7-154691.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -320988,7 +323485,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:153759$7985 + cell $and $and$libresoc.v:155391$8033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320996,10 +323493,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:153759$7985_Y + connect \Y $and$libresoc.v:155391$8033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:153796.8-153832.4" + attribute \src "libresoc.v:155428.8-155464.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -321038,304 +323535,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:153833.10-153836.4" + attribute \src "libresoc.v:155465.10-155468.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:153837.10-153840.4" + attribute \src "libresoc.v:155469.10-155472.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153059.7-153059.20" - process $proc$libresoc.v:153059$8070 + attribute \src "libresoc.v:154691.7-154691.20" + process $proc$libresoc.v:154691$8118 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153350.14-153350.44" - process $proc$libresoc.v:153350$8071 + attribute \src "libresoc.v:154982.14-154982.44" + process $proc$libresoc.v:154982$8119 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8072 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8072 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 end - attribute \src "libresoc.v:153376.14-153376.63" - process $proc$libresoc.v:153376$8073 + attribute \src "libresoc.v:155008.14-155008.63" + process $proc$libresoc.v:155008$8121 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8074 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8074 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 end - attribute \src "libresoc.v:153385.7-153385.38" - process $proc$libresoc.v:153385$8075 + attribute \src "libresoc.v:155017.7-155017.38" + process $proc$libresoc.v:155017$8123 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8076 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8076 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 end - attribute \src "libresoc.v:153392.14-153392.39" - process $proc$libresoc.v:153392$8077 + attribute \src "libresoc.v:155024.14-155024.39" + process $proc$libresoc.v:155024$8125 assign { } { } - assign $0\mul_op__insn$13[31:0]$8078 0 + assign $0\mul_op__insn$13[31:0]$8126 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8078 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 end - attribute \src "libresoc.v:153551.13-153551.42" - process $proc$libresoc.v:153551$8079 + attribute \src "libresoc.v:155183.13-155183.42" + process $proc$libresoc.v:155183$8127 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8080 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8080 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 end - attribute \src "libresoc.v:153635.7-153635.35" - process $proc$libresoc.v:153635$8081 + attribute \src "libresoc.v:155267.7-155267.35" + process $proc$libresoc.v:155267$8129 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8082 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8082 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 end - attribute \src "libresoc.v:153644.7-153644.36" - process $proc$libresoc.v:153644$8083 + attribute \src "libresoc.v:155276.7-155276.36" + process $proc$libresoc.v:155276$8131 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8084 1'0 + assign $0\mul_op__is_signed$12[0:0]$8132 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8084 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 end - attribute \src "libresoc.v:153655.7-153655.32" - process $proc$libresoc.v:153655$8085 + attribute \src "libresoc.v:155287.7-155287.32" + process $proc$libresoc.v:155287$8133 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8086 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8086 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 end - attribute \src "libresoc.v:153664.7-153664.32" - process $proc$libresoc.v:153664$8087 + attribute \src "libresoc.v:155296.7-155296.32" + process $proc$libresoc.v:155296$8135 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8088 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8088 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 end - attribute \src "libresoc.v:153673.7-153673.32" - process $proc$libresoc.v:153673$8089 + attribute \src "libresoc.v:155305.7-155305.32" + process $proc$libresoc.v:155305$8137 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8090 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8090 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 end - attribute \src "libresoc.v:153682.7-153682.32" - process $proc$libresoc.v:153682$8091 + attribute \src "libresoc.v:155314.7-155314.32" + process $proc$libresoc.v:155314$8139 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8092 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8092 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 end - attribute \src "libresoc.v:153689.7-153689.36" - process $proc$libresoc.v:153689$8093 + attribute \src "libresoc.v:155321.7-155321.36" + process $proc$libresoc.v:155321$8141 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8094 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8094 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 end - attribute \src "libresoc.v:153698.13-153698.29" - process $proc$libresoc.v:153698$8095 + attribute \src "libresoc.v:155330.13-155330.29" + process $proc$libresoc.v:155330$8143 assign { } { } - assign $0\muxid$1[1:0]$8096 2'00 + assign $0\muxid$1[1:0]$8144 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8096 + update \muxid$1 $0\muxid$1[1:0]$8144 end - attribute \src "libresoc.v:153713.7-153713.26" - process $proc$libresoc.v:153713$8097 + attribute \src "libresoc.v:155345.7-155345.26" + process $proc$libresoc.v:155345$8145 assign { } { } - assign $0\neg_res$15[0:0]$8098 1'0 + assign $0\neg_res$15[0:0]$8146 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$8098 + update \neg_res$15 $0\neg_res$15[0:0]$8146 end - attribute \src "libresoc.v:153722.7-153722.28" - process $proc$libresoc.v:153722$8099 + attribute \src "libresoc.v:155354.7-155354.28" + process $proc$libresoc.v:155354$8147 assign { } { } - assign $0\neg_res32$16[0:0]$8100 1'0 + assign $0\neg_res32$16[0:0]$8148 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8100 + update \neg_res32$16 $0\neg_res32$16[0:0]$8148 end - attribute \src "libresoc.v:153729.15-153729.57" - process $proc$libresoc.v:153729$8101 + attribute \src "libresoc.v:155361.15-155361.57" + process $proc$libresoc.v:155361$8149 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:153743.7-153743.20" - process $proc$libresoc.v:153743$8102 + attribute \src "libresoc.v:155375.7-155375.20" + process $proc$libresoc.v:155375$8150 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:153754.7-153754.25" - process $proc$libresoc.v:153754$8103 + attribute \src "libresoc.v:155386.7-155386.25" + process $proc$libresoc.v:155386$8151 assign { } { } - assign $0\xer_so$14[0:0]$8104 1'0 + assign $0\xer_so$14[0:0]$8152 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$8104 + update \xer_so$14 $0\xer_so$14[0:0]$8152 end - attribute \src "libresoc.v:153760.3-153761.43" - process $proc$libresoc.v:153760$7986 + attribute \src "libresoc.v:155392.3-155393.43" + process $proc$libresoc.v:155392$8034 assign { } { } - assign $0\neg_res32$16[0:0]$7987 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7987 + update \neg_res32$16 $0\neg_res32$16[0:0]$8035 end - attribute \src "libresoc.v:153762.3-153763.39" - process $proc$libresoc.v:153762$7988 + attribute \src "libresoc.v:155394.3-155395.39" + process $proc$libresoc.v:155394$8036 assign { } { } - assign $0\neg_res$15[0:0]$7989 \neg_res$15$next + assign $0\neg_res$15[0:0]$8037 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7989 + update \neg_res$15 $0\neg_res$15[0:0]$8037 end - attribute \src "libresoc.v:153764.3-153765.37" - process $proc$libresoc.v:153764$7990 + attribute \src "libresoc.v:155396.3-155397.37" + process $proc$libresoc.v:155396$8038 assign { } { } - assign $0\xer_so$14[0:0]$7991 \xer_so$14$next + assign $0\xer_so$14[0:0]$8039 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7991 + update \xer_so$14 $0\xer_so$14[0:0]$8039 end - attribute \src "libresoc.v:153766.3-153767.19" - process $proc$libresoc.v:153766$7992 + attribute \src "libresoc.v:155398.3-155399.19" + process $proc$libresoc.v:155398$8040 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:153768.3-153769.57" - process $proc$libresoc.v:153768$7993 + attribute \src "libresoc.v:155400.3-155401.57" + process $proc$libresoc.v:155400$8041 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7994 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7994 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 end - attribute \src "libresoc.v:153770.3-153771.53" - process $proc$libresoc.v:153770$7995 + attribute \src "libresoc.v:155402.3-155403.53" + process $proc$libresoc.v:155402$8043 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$7996 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7996 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 end - attribute \src "libresoc.v:153772.3-153773.67" - process $proc$libresoc.v:153772$7997 + attribute \src "libresoc.v:155404.3-155405.67" + process $proc$libresoc.v:155404$8045 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7998 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7998 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 end - attribute \src "libresoc.v:153774.3-153775.63" - process $proc$libresoc.v:153774$7999 + attribute \src "libresoc.v:155406.3-155407.63" + process $proc$libresoc.v:155406$8047 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8000 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8000 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 end - attribute \src "libresoc.v:153776.3-153777.51" - process $proc$libresoc.v:153776$8001 + attribute \src "libresoc.v:155408.3-155409.51" + process $proc$libresoc.v:155408$8049 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8002 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8002 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 end - attribute \src "libresoc.v:153778.3-153779.51" - process $proc$libresoc.v:153778$8003 + attribute \src "libresoc.v:155410.3-155411.51" + process $proc$libresoc.v:155410$8051 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8004 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8004 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 end - attribute \src "libresoc.v:153780.3-153781.51" - process $proc$libresoc.v:153780$8005 + attribute \src "libresoc.v:155412.3-155413.51" + process $proc$libresoc.v:155412$8053 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8006 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8006 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 end - attribute \src "libresoc.v:153782.3-153783.51" - process $proc$libresoc.v:153782$8007 + attribute \src "libresoc.v:155414.3-155415.51" + process $proc$libresoc.v:155414$8055 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8008 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8008 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 end - attribute \src "libresoc.v:153784.3-153785.59" - process $proc$libresoc.v:153784$8009 + attribute \src "libresoc.v:155416.3-155417.59" + process $proc$libresoc.v:155416$8057 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8010 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8010 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 end - attribute \src "libresoc.v:153786.3-153787.57" - process $proc$libresoc.v:153786$8011 + attribute \src "libresoc.v:155418.3-155419.57" + process $proc$libresoc.v:155418$8059 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8012 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8012 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 end - attribute \src "libresoc.v:153788.3-153789.59" - process $proc$libresoc.v:153788$8013 + attribute \src "libresoc.v:155420.3-155421.59" + process $proc$libresoc.v:155420$8061 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8014 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8014 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 end - attribute \src "libresoc.v:153790.3-153791.49" - process $proc$libresoc.v:153790$8015 + attribute \src "libresoc.v:155422.3-155423.49" + process $proc$libresoc.v:155422$8063 assign { } { } - assign $0\mul_op__insn$13[31:0]$8016 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8016 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 end - attribute \src "libresoc.v:153792.3-153793.33" - process $proc$libresoc.v:153792$8017 + attribute \src "libresoc.v:155424.3-155425.33" + process $proc$libresoc.v:155424$8065 assign { } { } - assign $0\muxid$1[1:0]$8018 \muxid$1$next + assign $0\muxid$1[1:0]$8066 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8018 + update \muxid$1 $0\muxid$1[1:0]$8066 end - attribute \src "libresoc.v:153794.3-153795.29" - process $proc$libresoc.v:153794$8019 + attribute \src "libresoc.v:155426.3-155427.29" + process $proc$libresoc.v:155426$8067 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:153841.3-153858.6" - process $proc$libresoc.v:153841$8020 + attribute \src "libresoc.v:155473.3-155490.6" + process $proc$libresoc.v:155473$8068 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8021 $2\r_busy$next[0:0]$8023 - attribute \src "libresoc.v:153842.5-153842.29" + assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155474.5-155474.29" switch \initial - attribute \src "libresoc.v:153842.9-153842.17" + attribute \src "libresoc.v:155474.9-155474.17" case 1'1 case end @@ -321344,34 +323841,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8022 1'1 + assign $1\r_busy$next[0:0]$8070 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8022 1'0 + assign $1\r_busy$next[0:0]$8070 1'0 case - assign $1\r_busy$next[0:0]$8022 \r_busy + assign $1\r_busy$next[0:0]$8070 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8023 1'0 + assign $2\r_busy$next[0:0]$8071 1'0 case - assign $2\r_busy$next[0:0]$8023 $1\r_busy$next[0:0]$8022 + assign $2\r_busy$next[0:0]$8071 $1\r_busy$next[0:0]$8070 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8021 + update \r_busy$next $0\r_busy$next[0:0]$8069 end - attribute \src "libresoc.v:153859.3-153871.6" - process $proc$libresoc.v:153859$8024 + attribute \src "libresoc.v:155491.3-155503.6" + process $proc$libresoc.v:155491$8072 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8025 $1\muxid$1$next[1:0]$8026 - attribute \src "libresoc.v:153860.5-153860.29" + assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155492.5-155492.29" switch \initial - attribute \src "libresoc.v:153860.9-153860.17" + attribute \src "libresoc.v:155492.9-155492.17" case 1'1 case end @@ -321380,19 +323877,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8026 \muxid$36 + assign $1\muxid$1$next[1:0]$8074 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8026 \muxid$36 + assign $1\muxid$1$next[1:0]$8074 \muxid$36 case - assign $1\muxid$1$next[1:0]$8026 \muxid$1 + assign $1\muxid$1$next[1:0]$8074 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8025 + update \muxid$1$next $0\muxid$1$next[1:0]$8073 end - attribute \src "libresoc.v:153872.3-153907.6" - process $proc$libresoc.v:153872$8027 + attribute \src "libresoc.v:155504.3-155539.6" + process $proc$libresoc.v:155504$8075 assign { } { } assign { } { } assign { } { } @@ -321417,27 +323914,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8028 $1\mul_op__fn_unit$3$next[13:0]$8040 + assign $0\mul_op__fn_unit$3$next[13:0]$8076 $1\mul_op__fn_unit$3$next[13:0]$8088 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8031 $1\mul_op__insn$13$next[31:0]$8043 - assign $0\mul_op__insn_type$2$next[6:0]$8032 $1\mul_op__insn_type$2$next[6:0]$8044 - assign $0\mul_op__is_32bit$11$next[0:0]$8033 $1\mul_op__is_32bit$11$next[0:0]$8045 - assign $0\mul_op__is_signed$12$next[0:0]$8034 $1\mul_op__is_signed$12$next[0:0]$8046 + assign $0\mul_op__insn$13$next[31:0]$8079 $1\mul_op__insn$13$next[31:0]$8091 + assign $0\mul_op__insn_type$2$next[6:0]$8080 $1\mul_op__insn_type$2$next[6:0]$8092 + assign $0\mul_op__is_32bit$11$next[0:0]$8081 $1\mul_op__is_32bit$11$next[0:0]$8093 + assign $0\mul_op__is_signed$12$next[0:0]$8082 $1\mul_op__is_signed$12$next[0:0]$8094 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8039 $1\mul_op__write_cr0$10$next[0:0]$8051 - assign $0\mul_op__imm_data__data$4$next[63:0]$8029 $2\mul_op__imm_data__data$4$next[63:0]$8052 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8030 $2\mul_op__imm_data__ok$5$next[0:0]$8053 - assign $0\mul_op__oe__oe$8$next[0:0]$8035 $2\mul_op__oe__oe$8$next[0:0]$8054 - assign $0\mul_op__oe__ok$9$next[0:0]$8036 $2\mul_op__oe__ok$9$next[0:0]$8055 - assign $0\mul_op__rc__ok$7$next[0:0]$8037 $2\mul_op__rc__ok$7$next[0:0]$8056 - assign $0\mul_op__rc__rc$6$next[0:0]$8038 $2\mul_op__rc__rc$6$next[0:0]$8057 - attribute \src "libresoc.v:153873.5-153873.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8087 $1\mul_op__write_cr0$10$next[0:0]$8099 + assign $0\mul_op__imm_data__data$4$next[63:0]$8077 $2\mul_op__imm_data__data$4$next[63:0]$8100 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8078 $2\mul_op__imm_data__ok$5$next[0:0]$8101 + assign $0\mul_op__oe__oe$8$next[0:0]$8083 $2\mul_op__oe__oe$8$next[0:0]$8102 + assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 + assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 + assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155505.5-155505.29" switch \initial - attribute \src "libresoc.v:153873.9-153873.17" + attribute \src "libresoc.v:155505.9-155505.17" case 1'1 case end @@ -321457,7 +323954,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -321472,20 +323969,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8040 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8041 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8042 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8043 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8044 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8045 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8046 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8047 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8048 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8049 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8050 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8051 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8088 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8089 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8090 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8091 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8092 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8093 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8094 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8095 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8096 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8097 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8098 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8099 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -321497,42 +323994,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8052 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8057 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8056 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8054 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8055 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8052 $1\mul_op__imm_data__data$4$next[63:0]$8041 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 $1\mul_op__imm_data__ok$5$next[0:0]$8042 - assign $2\mul_op__oe__oe$8$next[0:0]$8054 $1\mul_op__oe__oe$8$next[0:0]$8047 - assign $2\mul_op__oe__ok$9$next[0:0]$8055 $1\mul_op__oe__ok$9$next[0:0]$8048 - assign $2\mul_op__rc__ok$7$next[0:0]$8056 $1\mul_op__rc__ok$7$next[0:0]$8049 - assign $2\mul_op__rc__rc$6$next[0:0]$8057 $1\mul_op__rc__rc$6$next[0:0]$8050 + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 $1\mul_op__imm_data__data$4$next[63:0]$8089 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 $1\mul_op__imm_data__ok$5$next[0:0]$8090 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 $1\mul_op__oe__oe$8$next[0:0]$8095 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 $1\mul_op__oe__ok$9$next[0:0]$8096 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 $1\mul_op__rc__ok$7$next[0:0]$8097 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 $1\mul_op__rc__rc$6$next[0:0]$8098 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8028 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8029 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8030 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8031 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8032 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8033 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8034 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8035 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8036 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8037 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8038 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8039 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8076 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8077 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8078 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8079 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8080 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8081 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8082 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8083 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8084 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8085 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 end - attribute \src "libresoc.v:153908.3-153920.6" - process $proc$libresoc.v:153908$8058 + attribute \src "libresoc.v:155540.3-155552.6" + process $proc$libresoc.v:155540$8106 assign { } { } assign { } { } - assign $0\o$next[128:0]$8059 $1\o$next[128:0]$8060 - attribute \src "libresoc.v:153909.5-153909.29" + assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155541.5-155541.29" switch \initial - attribute \src "libresoc.v:153909.9-153909.17" + attribute \src "libresoc.v:155541.9-155541.17" case 1'1 case end @@ -321541,25 +324038,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$8060 \o$49 + assign $1\o$next[128:0]$8108 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$8060 \o$49 + assign $1\o$next[128:0]$8108 \o$49 case - assign $1\o$next[128:0]$8060 \o + assign $1\o$next[128:0]$8108 \o end sync always - update \o$next $0\o$next[128:0]$8059 + update \o$next $0\o$next[128:0]$8107 end - attribute \src "libresoc.v:153921.3-153933.6" - process $proc$libresoc.v:153921$8061 + attribute \src "libresoc.v:155553.3-155565.6" + process $proc$libresoc.v:155553$8109 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8062 $1\xer_so$14$next[0:0]$8063 - attribute \src "libresoc.v:153922.5-153922.29" + assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155554.5-155554.29" switch \initial - attribute \src "libresoc.v:153922.9-153922.17" + attribute \src "libresoc.v:155554.9-155554.17" case 1'1 case end @@ -321568,25 +324065,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$8063 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8062 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 end - attribute \src "libresoc.v:153934.3-153946.6" - process $proc$libresoc.v:153934$8064 + attribute \src "libresoc.v:155566.3-155578.6" + process $proc$libresoc.v:155566$8112 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8065 $1\neg_res$15$next[0:0]$8066 - attribute \src "libresoc.v:153935.5-153935.29" + assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155567.5-155567.29" switch \initial - attribute \src "libresoc.v:153935.9-153935.17" + attribute \src "libresoc.v:155567.9-155567.17" case 1'1 case end @@ -321595,25 +324092,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$8066 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8065 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 end - attribute \src "libresoc.v:153947.3-153959.6" - process $proc$libresoc.v:153947$8067 + attribute \src "libresoc.v:155579.3-155591.6" + process $proc$libresoc.v:155579$8115 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8068 $1\neg_res32$16$next[0:0]$8069 - attribute \src "libresoc.v:153948.5-153948.29" + assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155580.5-155580.29" switch \initial - attribute \src "libresoc.v:153948.9-153948.17" + attribute \src "libresoc.v:155580.9-155580.17" case 1'1 case end @@ -321622,18 +324119,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8068 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 end - connect \$34 $and$libresoc.v:153759$7985_Y + connect \$34 $and$libresoc.v:155391$8033_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -321653,218 +324150,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:153982.1-155278.10" +attribute \src "libresoc.v:155614.1-156910.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:155196.3-155214.6" - wire width 4 $0\cr_a$next[3:0]$8188 - attribute \src "libresoc.v:154988.3-154989.25" + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $0\cr_a$next[3:0]$8236 + attribute \src "libresoc.v:156620.3-156621.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $0\cr_a_ok$next[0:0]$8189 - attribute \src "libresoc.v:154990.3-154991.31" + attribute \src "libresoc.v:156828.3-156846.6" + wire $0\cr_a_ok$next[0:0]$8237 + attribute \src "libresoc.v:156622.3-156623.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:153983.7-153983.20" + attribute \src "libresoc.v:155615.7-155615.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155141.3-155176.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8151 - attribute \src "libresoc.v:154998.3-154999.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8119 - attribute \src "libresoc.v:154294.14-154294.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8209 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8152 - attribute \src "libresoc.v:155000.3-155001.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8121 - attribute \src "libresoc.v:154318.14-154318.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8211 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8153 - attribute \src "libresoc.v:155002.3-155003.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8123 - attribute \src "libresoc.v:154327.7-154327.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8213 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8154 - attribute \src "libresoc.v:155018.3-155019.49" - wire width 32 $0\mul_op__insn$13[31:0]$8139 - attribute \src "libresoc.v:154336.14-154336.39" - wire width 32 $0\mul_op__insn$13[31:0]$8215 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8155 - attribute \src "libresoc.v:154996.3-154997.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8117 - attribute \src "libresoc.v:154495.13-154495.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8217 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8156 - attribute \src "libresoc.v:155014.3-155015.57" - wire $0\mul_op__is_32bit$11[0:0]$8135 - attribute \src "libresoc.v:154579.7-154579.35" - wire $0\mul_op__is_32bit$11[0:0]$8219 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__is_signed$12$next[0:0]$8157 - attribute \src "libresoc.v:155016.3-155017.59" - wire $0\mul_op__is_signed$12[0:0]$8137 - attribute \src "libresoc.v:154588.7-154588.36" - wire $0\mul_op__is_signed$12[0:0]$8221 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8158 - attribute \src "libresoc.v:155008.3-155009.51" - wire $0\mul_op__oe__oe$8[0:0]$8129 - attribute \src "libresoc.v:154599.7-154599.32" - wire $0\mul_op__oe__oe$8[0:0]$8223 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8159 - attribute \src "libresoc.v:155010.3-155011.51" - wire $0\mul_op__oe__ok$9[0:0]$8131 - attribute \src "libresoc.v:154608.7-154608.32" - wire $0\mul_op__oe__ok$9[0:0]$8225 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8160 - attribute \src "libresoc.v:155006.3-155007.51" - wire $0\mul_op__rc__ok$7[0:0]$8127 - attribute \src "libresoc.v:154617.7-154617.32" - wire $0\mul_op__rc__ok$7[0:0]$8227 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8161 - attribute \src "libresoc.v:155004.3-155005.51" - wire $0\mul_op__rc__rc$6[0:0]$8125 - attribute \src "libresoc.v:154624.7-154624.32" - wire $0\mul_op__rc__rc$6[0:0]$8229 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8162 - attribute \src "libresoc.v:155012.3-155013.59" - wire $0\mul_op__write_cr0$10[0:0]$8133 - attribute \src "libresoc.v:154633.7-154633.36" - wire $0\mul_op__write_cr0$10[0:0]$8231 - attribute \src "libresoc.v:155128.3-155140.6" - wire width 2 $0\muxid$1$next[1:0]$8148 - attribute \src "libresoc.v:155020.3-155021.33" - wire width 2 $0\muxid$1[1:0]$8141 - attribute \src "libresoc.v:154642.13-154642.29" - wire width 2 $0\muxid$1[1:0]$8233 - attribute \src "libresoc.v:155177.3-155195.6" - wire width 64 $0\o$14$next[63:0]$8183 - attribute \src "libresoc.v:154992.3-154993.27" - wire width 64 $0\o$14[63:0]$8114 - attribute \src "libresoc.v:154663.14-154663.43" - wire width 64 $0\o$14[63:0]$8235 - attribute \src "libresoc.v:155177.3-155195.6" - wire $0\o_ok$next[0:0]$8182 - attribute \src "libresoc.v:154994.3-154995.25" + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 + attribute \src "libresoc.v:156630.3-156631.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 + attribute \src "libresoc.v:155926.14-155926.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 + attribute \src "libresoc.v:156632.3-156633.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 + attribute \src "libresoc.v:155950.14-155950.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 + attribute \src "libresoc.v:156634.3-156635.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8171 + attribute \src "libresoc.v:155959.7-155959.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8261 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8202 + attribute \src "libresoc.v:156650.3-156651.49" + wire width 32 $0\mul_op__insn$13[31:0]$8187 + attribute \src "libresoc.v:155968.14-155968.39" + wire width 32 $0\mul_op__insn$13[31:0]$8263 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 + attribute \src "libresoc.v:156628.3-156629.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8165 + attribute \src "libresoc.v:156127.13-156127.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8265 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8204 + attribute \src "libresoc.v:156646.3-156647.57" + wire $0\mul_op__is_32bit$11[0:0]$8183 + attribute \src "libresoc.v:156211.7-156211.35" + wire $0\mul_op__is_32bit$11[0:0]$8267 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_signed$12$next[0:0]$8205 + attribute \src "libresoc.v:156648.3-156649.59" + wire $0\mul_op__is_signed$12[0:0]$8185 + attribute \src "libresoc.v:156220.7-156220.36" + wire $0\mul_op__is_signed$12[0:0]$8269 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8206 + attribute \src "libresoc.v:156640.3-156641.51" + wire $0\mul_op__oe__oe$8[0:0]$8177 + attribute \src "libresoc.v:156231.7-156231.32" + wire $0\mul_op__oe__oe$8[0:0]$8271 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8207 + attribute \src "libresoc.v:156642.3-156643.51" + wire $0\mul_op__oe__ok$9[0:0]$8179 + attribute \src "libresoc.v:156240.7-156240.32" + wire $0\mul_op__oe__ok$9[0:0]$8273 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8208 + attribute \src "libresoc.v:156638.3-156639.51" + wire $0\mul_op__rc__ok$7[0:0]$8175 + attribute \src "libresoc.v:156249.7-156249.32" + wire $0\mul_op__rc__ok$7[0:0]$8275 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8209 + attribute \src "libresoc.v:156636.3-156637.51" + wire $0\mul_op__rc__rc$6[0:0]$8173 + attribute \src "libresoc.v:156256.7-156256.32" + wire $0\mul_op__rc__rc$6[0:0]$8277 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8210 + attribute \src "libresoc.v:156644.3-156645.59" + wire $0\mul_op__write_cr0$10[0:0]$8181 + attribute \src "libresoc.v:156265.7-156265.36" + wire $0\mul_op__write_cr0$10[0:0]$8279 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $0\muxid$1$next[1:0]$8196 + attribute \src "libresoc.v:156652.3-156653.33" + wire width 2 $0\muxid$1[1:0]$8189 + attribute \src "libresoc.v:156274.13-156274.29" + wire width 2 $0\muxid$1[1:0]$8281 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $0\o$14$next[63:0]$8231 + attribute \src "libresoc.v:156624.3-156625.27" + wire width 64 $0\o$14[63:0]$8162 + attribute \src "libresoc.v:156295.14-156295.43" + wire width 64 $0\o$14[63:0]$8283 + attribute \src "libresoc.v:156809.3-156827.6" + wire $0\o_ok$next[0:0]$8230 + attribute \src "libresoc.v:156626.3-156627.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:155110.3-155127.6" - wire $0\r_busy$next[0:0]$8144 - attribute \src "libresoc.v:155022.3-155023.29" + attribute \src "libresoc.v:156742.3-156759.6" + wire $0\r_busy$next[0:0]$8192 + attribute \src "libresoc.v:156654.3-156655.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire width 2 $0\xer_ov$next[1:0]$8194 - attribute \src "libresoc.v:154984.3-154985.29" + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $0\xer_ov$next[1:0]$8242 + attribute \src "libresoc.v:156616.3-156617.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire $0\xer_ov_ok$next[0:0]$8195 - attribute \src "libresoc.v:154986.3-154987.35" + attribute \src "libresoc.v:156847.3-156865.6" + wire $0\xer_ov_ok$next[0:0]$8243 + attribute \src "libresoc.v:156618.3-156619.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:155234.3-155252.6" - wire $0\xer_so$15$next[0:0]$8201 - attribute \src "libresoc.v:154980.3-154981.37" - wire $0\xer_so$15[0:0]$8107 - attribute \src "libresoc.v:154965.7-154965.25" - wire $0\xer_so$15[0:0]$8241 - attribute \src "libresoc.v:155234.3-155252.6" - wire $0\xer_so_ok$next[0:0]$8200 - attribute \src "libresoc.v:154982.3-154983.35" + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so$15$next[0:0]$8249 + attribute \src "libresoc.v:156612.3-156613.37" + wire $0\xer_so$15[0:0]$8155 + attribute \src "libresoc.v:156597.7-156597.25" + wire $0\xer_so$15[0:0]$8289 + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so_ok$next[0:0]$8248 + attribute \src "libresoc.v:156614.3-156615.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire width 4 $1\cr_a$next[3:0]$8190 - attribute \src "libresoc.v:153992.13-153992.24" + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $1\cr_a$next[3:0]$8238 + attribute \src "libresoc.v:155624.13-155624.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $1\cr_a_ok$next[0:0]$8191 - attribute \src "libresoc.v:154001.7-154001.21" + attribute \src "libresoc.v:156828.3-156846.6" + wire $1\cr_a_ok$next[0:0]$8239 + attribute \src "libresoc.v:155633.7-155633.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:155141.3-155176.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8163 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8164 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8165 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8166 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8167 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8168 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__is_signed$12$next[0:0]$8169 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8170 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8171 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8172 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8173 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8174 - attribute \src "libresoc.v:155128.3-155140.6" - wire width 2 $1\muxid$1$next[1:0]$8149 - attribute \src "libresoc.v:155177.3-155195.6" - wire width 64 $1\o$14$next[63:0]$8185 - attribute \src "libresoc.v:155177.3-155195.6" - wire $1\o_ok$next[0:0]$8184 - attribute \src "libresoc.v:154670.7-154670.18" + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8214 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8216 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_signed$12$next[0:0]$8217 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8218 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8219 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8220 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8221 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8222 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $1\o$14$next[63:0]$8233 + attribute \src "libresoc.v:156809.3-156827.6" + wire $1\o_ok$next[0:0]$8232 + attribute \src "libresoc.v:156302.7-156302.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:155110.3-155127.6" - wire $1\r_busy$next[0:0]$8145 - attribute \src "libresoc.v:154942.7-154942.20" + attribute \src "libresoc.v:156742.3-156759.6" + wire $1\r_busy$next[0:0]$8193 + attribute \src "libresoc.v:156574.7-156574.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire width 2 $1\xer_ov$next[1:0]$8196 - attribute \src "libresoc.v:154947.13-154947.26" + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $1\xer_ov$next[1:0]$8244 + attribute \src "libresoc.v:156579.13-156579.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire $1\xer_ov_ok$next[0:0]$8197 - attribute \src "libresoc.v:154954.7-154954.23" + attribute \src "libresoc.v:156847.3-156865.6" + wire $1\xer_ov_ok$next[0:0]$8245 + attribute \src "libresoc.v:156586.7-156586.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:155234.3-155252.6" - wire $1\xer_so$15$next[0:0]$8203 - attribute \src "libresoc.v:155234.3-155252.6" - wire $1\xer_so_ok$next[0:0]$8202 - attribute \src "libresoc.v:154972.7-154972.23" + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so$15$next[0:0]$8251 + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so_ok$next[0:0]$8250 + attribute \src "libresoc.v:156604.7-156604.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $2\cr_a_ok$next[0:0]$8192 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8175 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8176 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8177 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8178 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8179 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8180 - attribute \src "libresoc.v:155177.3-155195.6" - wire $2\o_ok$next[0:0]$8186 - attribute \src "libresoc.v:155110.3-155127.6" - wire $2\r_busy$next[0:0]$8146 - attribute \src "libresoc.v:155215.3-155233.6" - wire $2\xer_ov_ok$next[0:0]$8198 - attribute \src "libresoc.v:155234.3-155252.6" - wire $2\xer_so_ok$next[0:0]$8204 - attribute \src "libresoc.v:154979.18-154979.118" - wire $and$libresoc.v:154979$8105_Y + attribute \src "libresoc.v:156828.3-156846.6" + wire $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8225 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8226 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8227 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156809.3-156827.6" + wire $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156742.3-156759.6" + wire $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156847.3-156865.6" + wire $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156866.3-156884.6" + wire $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156611.18-156611.118" + wire $and$libresoc.v:156611$8153_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a @@ -321884,7 +324381,7 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:153983.7-153983.15" + attribute \src "libresoc.v:155615.7-155615.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -322837,7 +325334,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:154979$8105 + cell $and $and$libresoc.v:156611$8153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322845,10 +325342,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:154979$8105_Y + connect \Y $and$libresoc.v:156611$8153_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155024.8-155060.4" + attribute \src "libresoc.v:156656.8-156692.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -322887,13 +325384,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:155061.10-155064.4" + attribute \src "libresoc.v:156693.10-156696.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155065.16-155105.4" + attribute \src "libresoc.v:156697.16-156737.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -322936,358 +325433,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:155106.10-155109.4" + attribute \src "libresoc.v:156738.10-156741.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153983.7-153983.20" - process $proc$libresoc.v:153983$8205 + attribute \src "libresoc.v:155615.7-155615.20" + process $proc$libresoc.v:155615$8253 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153992.13-153992.24" - process $proc$libresoc.v:153992$8206 + attribute \src "libresoc.v:155624.13-155624.24" + process $proc$libresoc.v:155624$8254 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:154001.7-154001.21" - process $proc$libresoc.v:154001$8207 + attribute \src "libresoc.v:155633.7-155633.21" + process $proc$libresoc.v:155633$8255 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:154294.14-154294.44" - process $proc$libresoc.v:154294$8208 + attribute \src "libresoc.v:155926.14-155926.44" + process $proc$libresoc.v:155926$8256 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8209 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8209 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 end - attribute \src "libresoc.v:154318.14-154318.63" - process $proc$libresoc.v:154318$8210 + attribute \src "libresoc.v:155950.14-155950.63" + process $proc$libresoc.v:155950$8258 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8211 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8211 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 end - attribute \src "libresoc.v:154327.7-154327.38" - process $proc$libresoc.v:154327$8212 + attribute \src "libresoc.v:155959.7-155959.38" + process $proc$libresoc.v:155959$8260 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8213 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8213 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 end - attribute \src "libresoc.v:154336.14-154336.39" - process $proc$libresoc.v:154336$8214 + attribute \src "libresoc.v:155968.14-155968.39" + process $proc$libresoc.v:155968$8262 assign { } { } - assign $0\mul_op__insn$13[31:0]$8215 0 + assign $0\mul_op__insn$13[31:0]$8263 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8215 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 end - attribute \src "libresoc.v:154495.13-154495.42" - process $proc$libresoc.v:154495$8216 + attribute \src "libresoc.v:156127.13-156127.42" + process $proc$libresoc.v:156127$8264 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8217 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8217 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 end - attribute \src "libresoc.v:154579.7-154579.35" - process $proc$libresoc.v:154579$8218 + attribute \src "libresoc.v:156211.7-156211.35" + process $proc$libresoc.v:156211$8266 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8219 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8219 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 end - attribute \src "libresoc.v:154588.7-154588.36" - process $proc$libresoc.v:154588$8220 + attribute \src "libresoc.v:156220.7-156220.36" + process $proc$libresoc.v:156220$8268 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8221 1'0 + assign $0\mul_op__is_signed$12[0:0]$8269 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8221 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 end - attribute \src "libresoc.v:154599.7-154599.32" - process $proc$libresoc.v:154599$8222 + attribute \src "libresoc.v:156231.7-156231.32" + process $proc$libresoc.v:156231$8270 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8223 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8223 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 end - attribute \src "libresoc.v:154608.7-154608.32" - process $proc$libresoc.v:154608$8224 + attribute \src "libresoc.v:156240.7-156240.32" + process $proc$libresoc.v:156240$8272 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8225 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8225 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 end - attribute \src "libresoc.v:154617.7-154617.32" - process $proc$libresoc.v:154617$8226 + attribute \src "libresoc.v:156249.7-156249.32" + process $proc$libresoc.v:156249$8274 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8227 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8227 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 end - attribute \src "libresoc.v:154624.7-154624.32" - process $proc$libresoc.v:154624$8228 + attribute \src "libresoc.v:156256.7-156256.32" + process $proc$libresoc.v:156256$8276 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8229 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8229 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 end - attribute \src "libresoc.v:154633.7-154633.36" - process $proc$libresoc.v:154633$8230 + attribute \src "libresoc.v:156265.7-156265.36" + process $proc$libresoc.v:156265$8278 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8231 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8231 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 end - attribute \src "libresoc.v:154642.13-154642.29" - process $proc$libresoc.v:154642$8232 + attribute \src "libresoc.v:156274.13-156274.29" + process $proc$libresoc.v:156274$8280 assign { } { } - assign $0\muxid$1[1:0]$8233 2'00 + assign $0\muxid$1[1:0]$8281 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8233 + update \muxid$1 $0\muxid$1[1:0]$8281 end - attribute \src "libresoc.v:154663.14-154663.43" - process $proc$libresoc.v:154663$8234 + attribute \src "libresoc.v:156295.14-156295.43" + process $proc$libresoc.v:156295$8282 assign { } { } - assign $0\o$14[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$8235 + update \o$14 $0\o$14[63:0]$8283 end - attribute \src "libresoc.v:154670.7-154670.18" - process $proc$libresoc.v:154670$8236 + attribute \src "libresoc.v:156302.7-156302.18" + process $proc$libresoc.v:156302$8284 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:154942.7-154942.20" - process $proc$libresoc.v:154942$8237 + attribute \src "libresoc.v:156574.7-156574.20" + process $proc$libresoc.v:156574$8285 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154947.13-154947.26" - process $proc$libresoc.v:154947$8238 + attribute \src "libresoc.v:156579.13-156579.26" + process $proc$libresoc.v:156579$8286 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:154954.7-154954.23" - process $proc$libresoc.v:154954$8239 + attribute \src "libresoc.v:156586.7-156586.23" + process $proc$libresoc.v:156586$8287 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:154965.7-154965.25" - process $proc$libresoc.v:154965$8240 + attribute \src "libresoc.v:156597.7-156597.25" + process $proc$libresoc.v:156597$8288 assign { } { } - assign $0\xer_so$15[0:0]$8241 1'0 + assign $0\xer_so$15[0:0]$8289 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8241 + update \xer_so$15 $0\xer_so$15[0:0]$8289 end - attribute \src "libresoc.v:154972.7-154972.23" - process $proc$libresoc.v:154972$8242 + attribute \src "libresoc.v:156604.7-156604.23" + process $proc$libresoc.v:156604$8290 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:154980.3-154981.37" - process $proc$libresoc.v:154980$8106 + attribute \src "libresoc.v:156612.3-156613.37" + process $proc$libresoc.v:156612$8154 assign { } { } - assign $0\xer_so$15[0:0]$8107 \xer_so$15$next + assign $0\xer_so$15[0:0]$8155 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8107 + update \xer_so$15 $0\xer_so$15[0:0]$8155 end - attribute \src "libresoc.v:154982.3-154983.35" - process $proc$libresoc.v:154982$8108 + attribute \src "libresoc.v:156614.3-156615.35" + process $proc$libresoc.v:156614$8156 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:154984.3-154985.29" - process $proc$libresoc.v:154984$8109 + attribute \src "libresoc.v:156616.3-156617.29" + process $proc$libresoc.v:156616$8157 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:154986.3-154987.35" - process $proc$libresoc.v:154986$8110 + attribute \src "libresoc.v:156618.3-156619.35" + process $proc$libresoc.v:156618$8158 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:154988.3-154989.25" - process $proc$libresoc.v:154988$8111 + attribute \src "libresoc.v:156620.3-156621.25" + process $proc$libresoc.v:156620$8159 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:154990.3-154991.31" - process $proc$libresoc.v:154990$8112 + attribute \src "libresoc.v:156622.3-156623.31" + process $proc$libresoc.v:156622$8160 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:154992.3-154993.27" - process $proc$libresoc.v:154992$8113 + attribute \src "libresoc.v:156624.3-156625.27" + process $proc$libresoc.v:156624$8161 assign { } { } - assign $0\o$14[63:0]$8114 \o$14$next + assign $0\o$14[63:0]$8162 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8114 + update \o$14 $0\o$14[63:0]$8162 end - attribute \src "libresoc.v:154994.3-154995.25" - process $proc$libresoc.v:154994$8115 + attribute \src "libresoc.v:156626.3-156627.25" + process $proc$libresoc.v:156626$8163 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:154996.3-154997.57" - process $proc$libresoc.v:154996$8116 + attribute \src "libresoc.v:156628.3-156629.57" + process $proc$libresoc.v:156628$8164 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8117 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8117 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 end - attribute \src "libresoc.v:154998.3-154999.53" - process $proc$libresoc.v:154998$8118 + attribute \src "libresoc.v:156630.3-156631.53" + process $proc$libresoc.v:156630$8166 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8119 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8119 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 end - attribute \src "libresoc.v:155000.3-155001.67" - process $proc$libresoc.v:155000$8120 + attribute \src "libresoc.v:156632.3-156633.67" + process $proc$libresoc.v:156632$8168 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8121 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8121 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 end - attribute \src "libresoc.v:155002.3-155003.63" - process $proc$libresoc.v:155002$8122 + attribute \src "libresoc.v:156634.3-156635.63" + process $proc$libresoc.v:156634$8170 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8123 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8123 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 end - attribute \src "libresoc.v:155004.3-155005.51" - process $proc$libresoc.v:155004$8124 + attribute \src "libresoc.v:156636.3-156637.51" + process $proc$libresoc.v:156636$8172 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8125 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8125 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 end - attribute \src "libresoc.v:155006.3-155007.51" - process $proc$libresoc.v:155006$8126 + attribute \src "libresoc.v:156638.3-156639.51" + process $proc$libresoc.v:156638$8174 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8127 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8127 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 end - attribute \src "libresoc.v:155008.3-155009.51" - process $proc$libresoc.v:155008$8128 + attribute \src "libresoc.v:156640.3-156641.51" + process $proc$libresoc.v:156640$8176 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8129 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8129 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 end - attribute \src "libresoc.v:155010.3-155011.51" - process $proc$libresoc.v:155010$8130 + attribute \src "libresoc.v:156642.3-156643.51" + process $proc$libresoc.v:156642$8178 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8131 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8131 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 end - attribute \src "libresoc.v:155012.3-155013.59" - process $proc$libresoc.v:155012$8132 + attribute \src "libresoc.v:156644.3-156645.59" + process $proc$libresoc.v:156644$8180 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8133 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8133 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 end - attribute \src "libresoc.v:155014.3-155015.57" - process $proc$libresoc.v:155014$8134 + attribute \src "libresoc.v:156646.3-156647.57" + process $proc$libresoc.v:156646$8182 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8135 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8135 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 end - attribute \src "libresoc.v:155016.3-155017.59" - process $proc$libresoc.v:155016$8136 + attribute \src "libresoc.v:156648.3-156649.59" + process $proc$libresoc.v:156648$8184 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8137 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8137 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 end - attribute \src "libresoc.v:155018.3-155019.49" - process $proc$libresoc.v:155018$8138 + attribute \src "libresoc.v:156650.3-156651.49" + process $proc$libresoc.v:156650$8186 assign { } { } - assign $0\mul_op__insn$13[31:0]$8139 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8139 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 end - attribute \src "libresoc.v:155020.3-155021.33" - process $proc$libresoc.v:155020$8140 + attribute \src "libresoc.v:156652.3-156653.33" + process $proc$libresoc.v:156652$8188 assign { } { } - assign $0\muxid$1[1:0]$8141 \muxid$1$next + assign $0\muxid$1[1:0]$8189 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8141 + update \muxid$1 $0\muxid$1[1:0]$8189 end - attribute \src "libresoc.v:155022.3-155023.29" - process $proc$libresoc.v:155022$8142 + attribute \src "libresoc.v:156654.3-156655.29" + process $proc$libresoc.v:156654$8190 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155110.3-155127.6" - process $proc$libresoc.v:155110$8143 + attribute \src "libresoc.v:156742.3-156759.6" + process $proc$libresoc.v:156742$8191 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8144 $2\r_busy$next[0:0]$8146 - attribute \src "libresoc.v:155111.5-155111.29" + assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156743.5-156743.29" switch \initial - attribute \src "libresoc.v:155111.9-155111.17" + attribute \src "libresoc.v:156743.9-156743.17" case 1'1 case end @@ -323296,34 +325793,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8145 1'1 + assign $1\r_busy$next[0:0]$8193 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8145 1'0 + assign $1\r_busy$next[0:0]$8193 1'0 case - assign $1\r_busy$next[0:0]$8145 \r_busy + assign $1\r_busy$next[0:0]$8193 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8146 1'0 + assign $2\r_busy$next[0:0]$8194 1'0 case - assign $2\r_busy$next[0:0]$8146 $1\r_busy$next[0:0]$8145 + assign $2\r_busy$next[0:0]$8194 $1\r_busy$next[0:0]$8193 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8144 + update \r_busy$next $0\r_busy$next[0:0]$8192 end - attribute \src "libresoc.v:155128.3-155140.6" - process $proc$libresoc.v:155128$8147 + attribute \src "libresoc.v:156760.3-156772.6" + process $proc$libresoc.v:156760$8195 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8148 $1\muxid$1$next[1:0]$8149 - attribute \src "libresoc.v:155129.5-155129.29" + assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156761.5-156761.29" switch \initial - attribute \src "libresoc.v:155129.9-155129.17" + attribute \src "libresoc.v:156761.9-156761.17" case 1'1 case end @@ -323332,19 +325829,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8149 \muxid$58 + assign $1\muxid$1$next[1:0]$8197 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8149 \muxid$58 + assign $1\muxid$1$next[1:0]$8197 \muxid$58 case - assign $1\muxid$1$next[1:0]$8149 \muxid$1 + assign $1\muxid$1$next[1:0]$8197 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8148 + update \muxid$1$next $0\muxid$1$next[1:0]$8196 end - attribute \src "libresoc.v:155141.3-155176.6" - process $proc$libresoc.v:155141$8150 + attribute \src "libresoc.v:156773.3-156808.6" + process $proc$libresoc.v:156773$8198 assign { } { } assign { } { } assign { } { } @@ -323369,27 +325866,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8151 $1\mul_op__fn_unit$3$next[13:0]$8163 + assign $0\mul_op__fn_unit$3$next[13:0]$8199 $1\mul_op__fn_unit$3$next[13:0]$8211 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8154 $1\mul_op__insn$13$next[31:0]$8166 - assign $0\mul_op__insn_type$2$next[6:0]$8155 $1\mul_op__insn_type$2$next[6:0]$8167 - assign $0\mul_op__is_32bit$11$next[0:0]$8156 $1\mul_op__is_32bit$11$next[0:0]$8168 - assign $0\mul_op__is_signed$12$next[0:0]$8157 $1\mul_op__is_signed$12$next[0:0]$8169 + assign $0\mul_op__insn$13$next[31:0]$8202 $1\mul_op__insn$13$next[31:0]$8214 + assign $0\mul_op__insn_type$2$next[6:0]$8203 $1\mul_op__insn_type$2$next[6:0]$8215 + assign $0\mul_op__is_32bit$11$next[0:0]$8204 $1\mul_op__is_32bit$11$next[0:0]$8216 + assign $0\mul_op__is_signed$12$next[0:0]$8205 $1\mul_op__is_signed$12$next[0:0]$8217 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8162 $1\mul_op__write_cr0$10$next[0:0]$8174 - assign $0\mul_op__imm_data__data$4$next[63:0]$8152 $2\mul_op__imm_data__data$4$next[63:0]$8175 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8153 $2\mul_op__imm_data__ok$5$next[0:0]$8176 - assign $0\mul_op__oe__oe$8$next[0:0]$8158 $2\mul_op__oe__oe$8$next[0:0]$8177 - assign $0\mul_op__oe__ok$9$next[0:0]$8159 $2\mul_op__oe__ok$9$next[0:0]$8178 - assign $0\mul_op__rc__ok$7$next[0:0]$8160 $2\mul_op__rc__ok$7$next[0:0]$8179 - assign $0\mul_op__rc__rc$6$next[0:0]$8161 $2\mul_op__rc__rc$6$next[0:0]$8180 - attribute \src "libresoc.v:155142.5-155142.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8210 $1\mul_op__write_cr0$10$next[0:0]$8222 + assign $0\mul_op__imm_data__data$4$next[63:0]$8200 $2\mul_op__imm_data__data$4$next[63:0]$8223 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8201 $2\mul_op__imm_data__ok$5$next[0:0]$8224 + assign $0\mul_op__oe__oe$8$next[0:0]$8206 $2\mul_op__oe__oe$8$next[0:0]$8225 + assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 + assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 + assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156774.5-156774.29" switch \initial - attribute \src "libresoc.v:155142.9-155142.17" + attribute \src "libresoc.v:156774.9-156774.17" case 1'1 case end @@ -323409,7 +325906,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -323424,20 +325921,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8163 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8164 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8165 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8166 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8167 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8168 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8169 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8170 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8171 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8172 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8173 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8174 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8211 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8212 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8213 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8214 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8215 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8216 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8217 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8218 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8219 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8220 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8221 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8222 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -323449,46 +325946,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8175 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8180 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8179 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8177 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8178 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8175 $1\mul_op__imm_data__data$4$next[63:0]$8164 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 $1\mul_op__imm_data__ok$5$next[0:0]$8165 - assign $2\mul_op__oe__oe$8$next[0:0]$8177 $1\mul_op__oe__oe$8$next[0:0]$8170 - assign $2\mul_op__oe__ok$9$next[0:0]$8178 $1\mul_op__oe__ok$9$next[0:0]$8171 - assign $2\mul_op__rc__ok$7$next[0:0]$8179 $1\mul_op__rc__ok$7$next[0:0]$8172 - assign $2\mul_op__rc__rc$6$next[0:0]$8180 $1\mul_op__rc__rc$6$next[0:0]$8173 + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 $1\mul_op__imm_data__data$4$next[63:0]$8212 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 $1\mul_op__imm_data__ok$5$next[0:0]$8213 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 $1\mul_op__oe__oe$8$next[0:0]$8218 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 $1\mul_op__oe__ok$9$next[0:0]$8219 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 $1\mul_op__rc__ok$7$next[0:0]$8220 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 $1\mul_op__rc__rc$6$next[0:0]$8221 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8151 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8152 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8153 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8154 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8155 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8156 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8157 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8158 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8159 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8160 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8161 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8162 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8199 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8200 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8201 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8202 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8203 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8204 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8205 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8206 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8207 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8208 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 end - attribute \src "libresoc.v:155177.3-155195.6" - process $proc$libresoc.v:155177$8181 + attribute \src "libresoc.v:156809.3-156827.6" + process $proc$libresoc.v:156809$8229 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$8183 $1\o$14$next[63:0]$8185 - assign $0\o_ok$next[0:0]$8182 $2\o_ok$next[0:0]$8186 - attribute \src "libresoc.v:155178.5-155178.29" + assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 + assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156810.5-156810.29" switch \initial - attribute \src "libresoc.v:155178.9-155178.17" + attribute \src "libresoc.v:156810.9-156810.17" case 1'1 case end @@ -323498,41 +325995,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$8184 \o_ok - assign $1\o$14$next[63:0]$8185 \o$14 + assign $1\o_ok$next[0:0]$8232 \o_ok + assign $1\o$14$next[63:0]$8233 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8186 1'0 + assign $2\o_ok$next[0:0]$8234 1'0 case - assign $2\o_ok$next[0:0]$8186 $1\o_ok$next[0:0]$8184 + assign $2\o_ok$next[0:0]$8234 $1\o_ok$next[0:0]$8232 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8182 - update \o$14$next $0\o$14$next[63:0]$8183 + update \o_ok$next $0\o_ok$next[0:0]$8230 + update \o$14$next $0\o$14$next[63:0]$8231 end - attribute \src "libresoc.v:155196.3-155214.6" - process $proc$libresoc.v:155196$8187 + attribute \src "libresoc.v:156828.3-156846.6" + process $proc$libresoc.v:156828$8235 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8188 $1\cr_a$next[3:0]$8190 + assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 assign { } { } - assign $0\cr_a_ok$next[0:0]$8189 $2\cr_a_ok$next[0:0]$8192 - attribute \src "libresoc.v:155197.5-155197.29" + assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156829.5-156829.29" switch \initial - attribute \src "libresoc.v:155197.9-155197.17" + attribute \src "libresoc.v:156829.9-156829.17" case 1'1 case end @@ -323542,41 +326039,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$8190 \cr_a - assign $1\cr_a_ok$next[0:0]$8191 \cr_a_ok + assign $1\cr_a$next[3:0]$8238 \cr_a + assign $1\cr_a_ok$next[0:0]$8239 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8192 1'0 + assign $2\cr_a_ok$next[0:0]$8240 1'0 case - assign $2\cr_a_ok$next[0:0]$8192 $1\cr_a_ok$next[0:0]$8191 + assign $2\cr_a_ok$next[0:0]$8240 $1\cr_a_ok$next[0:0]$8239 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8188 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8189 + update \cr_a$next $0\cr_a$next[3:0]$8236 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 end - attribute \src "libresoc.v:155215.3-155233.6" - process $proc$libresoc.v:155215$8193 + attribute \src "libresoc.v:156847.3-156865.6" + process $proc$libresoc.v:156847$8241 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8194 $1\xer_ov$next[1:0]$8196 + assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8195 $2\xer_ov_ok$next[0:0]$8198 - attribute \src "libresoc.v:155216.5-155216.29" + assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156848.5-156848.29" switch \initial - attribute \src "libresoc.v:155216.9-155216.17" + attribute \src "libresoc.v:156848.9-156848.17" case 1'1 case end @@ -323586,41 +326083,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$8196 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8197 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8244 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8245 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8198 1'0 + assign $2\xer_ov_ok$next[0:0]$8246 1'0 case - assign $2\xer_ov_ok$next[0:0]$8198 $1\xer_ov_ok$next[0:0]$8197 + assign $2\xer_ov_ok$next[0:0]$8246 $1\xer_ov_ok$next[0:0]$8245 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8194 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8195 + update \xer_ov$next $0\xer_ov$next[1:0]$8242 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 end - attribute \src "libresoc.v:155234.3-155252.6" - process $proc$libresoc.v:155234$8199 + attribute \src "libresoc.v:156866.3-156884.6" + process $proc$libresoc.v:156866$8247 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8201 $1\xer_so$15$next[0:0]$8203 - assign $0\xer_so_ok$next[0:0]$8200 $2\xer_so_ok$next[0:0]$8204 - attribute \src "libresoc.v:155235.5-155235.29" + assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 + assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156867.5-156867.29" switch \initial - attribute \src "libresoc.v:155235.9-155235.17" + attribute \src "libresoc.v:156867.9-156867.17" case 1'1 case end @@ -323630,30 +326127,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$8202 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8203 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8250 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8251 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8204 1'0 + assign $2\xer_so_ok$next[0:0]$8252 1'0 case - assign $2\xer_so_ok$next[0:0]$8204 $1\xer_so_ok$next[0:0]$8202 + assign $2\xer_so_ok$next[0:0]$8252 $1\xer_so_ok$next[0:0]$8250 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8200 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8201 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 end - connect \$56 $and$libresoc.v:154979$8105_Y + connect \$56 $and$libresoc.v:156611$8153_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -323680,13 +326177,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:155282.1-155293.10" +attribute \src "libresoc.v:156914.1-156925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:155291.17-155291.111" - wire $and$libresoc.v:155291$8243_Y + attribute \src "libresoc.v:156923.17-156923.111" + wire $and$libresoc.v:156923$8291_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323696,7 +326193,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155291$8243 + cell $and $and$libresoc.v:156923$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323704,18 +326201,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155291$8243_Y + connect \Y $and$libresoc.v:156923$8291_Y end - connect \$1 $and$libresoc.v:155291$8243_Y + connect \$1 $and$libresoc.v:156923$8291_Y connect \trigger \$1 end -attribute \src "libresoc.v:155297.1-155308.10" +attribute \src "libresoc.v:156929.1-156940.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:155306.17-155306.111" - wire $and$libresoc.v:155306$8244_Y + attribute \src "libresoc.v:156938.17-156938.111" + wire $and$libresoc.v:156938$8292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323725,7 +326222,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155306$8244 + cell $and $and$libresoc.v:156938$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323733,18 +326230,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155306$8244_Y + connect \Y $and$libresoc.v:156938$8292_Y end - connect \$1 $and$libresoc.v:155306$8244_Y + connect \$1 $and$libresoc.v:156938$8292_Y connect \trigger \$1 end -attribute \src "libresoc.v:155312.1-155323.10" +attribute \src "libresoc.v:156944.1-156955.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:155321.17-155321.111" - wire $and$libresoc.v:155321$8245_Y + attribute \src "libresoc.v:156953.17-156953.111" + wire $and$libresoc.v:156953$8293_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323754,7 +326251,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155321$8245 + cell $and $and$libresoc.v:156953$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323762,18 +326259,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155321$8245_Y + connect \Y $and$libresoc.v:156953$8293_Y end - connect \$1 $and$libresoc.v:155321$8245_Y + connect \$1 $and$libresoc.v:156953$8293_Y connect \trigger \$1 end -attribute \src "libresoc.v:155327.1-155338.10" +attribute \src "libresoc.v:156959.1-156970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:155336.17-155336.111" - wire $and$libresoc.v:155336$8246_Y + attribute \src "libresoc.v:156968.17-156968.111" + wire $and$libresoc.v:156968$8294_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323783,7 +326280,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155336$8246 + cell $and $and$libresoc.v:156968$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323791,18 +326288,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155336$8246_Y + connect \Y $and$libresoc.v:156968$8294_Y end - connect \$1 $and$libresoc.v:155336$8246_Y + connect \$1 $and$libresoc.v:156968$8294_Y connect \trigger \$1 end -attribute \src "libresoc.v:155342.1-155353.10" +attribute \src "libresoc.v:156974.1-156985.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:155351.17-155351.111" - wire $and$libresoc.v:155351$8247_Y + attribute \src "libresoc.v:156983.17-156983.111" + wire $and$libresoc.v:156983$8295_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323812,7 +326309,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155351$8247 + cell $and $and$libresoc.v:156983$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323820,18 +326317,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155351$8247_Y + connect \Y $and$libresoc.v:156983$8295_Y end - connect \$1 $and$libresoc.v:155351$8247_Y + connect \$1 $and$libresoc.v:156983$8295_Y connect \trigger \$1 end -attribute \src "libresoc.v:155357.1-155368.10" +attribute \src "libresoc.v:156989.1-157000.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:155366.17-155366.111" - wire $and$libresoc.v:155366$8248_Y + attribute \src "libresoc.v:156998.17-156998.111" + wire $and$libresoc.v:156998$8296_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323841,7 +326338,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155366$8248 + cell $and $and$libresoc.v:156998$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323849,18 +326346,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155366$8248_Y + connect \Y $and$libresoc.v:156998$8296_Y end - connect \$1 $and$libresoc.v:155366$8248_Y + connect \$1 $and$libresoc.v:156998$8296_Y connect \trigger \$1 end -attribute \src "libresoc.v:155372.1-155383.10" +attribute \src "libresoc.v:157004.1-157015.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:155381.17-155381.111" - wire $and$libresoc.v:155381$8249_Y + attribute \src "libresoc.v:157013.17-157013.111" + wire $and$libresoc.v:157013$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323870,7 +326367,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155381$8249 + cell $and $and$libresoc.v:157013$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323878,18 +326375,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155381$8249_Y + connect \Y $and$libresoc.v:157013$8297_Y end - connect \$1 $and$libresoc.v:155381$8249_Y + connect \$1 $and$libresoc.v:157013$8297_Y connect \trigger \$1 end -attribute \src "libresoc.v:155387.1-155398.10" +attribute \src "libresoc.v:157019.1-157030.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:155396.17-155396.111" - wire $and$libresoc.v:155396$8250_Y + attribute \src "libresoc.v:157028.17-157028.111" + wire $and$libresoc.v:157028$8298_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323899,7 +326396,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155396$8250 + cell $and $and$libresoc.v:157028$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323907,18 +326404,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155396$8250_Y + connect \Y $and$libresoc.v:157028$8298_Y end - connect \$1 $and$libresoc.v:155396$8250_Y + connect \$1 $and$libresoc.v:157028$8298_Y connect \trigger \$1 end -attribute \src "libresoc.v:155402.1-155413.10" +attribute \src "libresoc.v:157034.1-157045.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:155411.17-155411.111" - wire $and$libresoc.v:155411$8251_Y + attribute \src "libresoc.v:157043.17-157043.111" + wire $and$libresoc.v:157043$8299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323928,7 +326425,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155411$8251 + cell $and $and$libresoc.v:157043$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323936,18 +326433,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155411$8251_Y + connect \Y $and$libresoc.v:157043$8299_Y end - connect \$1 $and$libresoc.v:155411$8251_Y + connect \$1 $and$libresoc.v:157043$8299_Y connect \trigger \$1 end -attribute \src "libresoc.v:155417.1-155428.10" +attribute \src "libresoc.v:157049.1-157060.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:155426.17-155426.111" - wire $and$libresoc.v:155426$8252_Y + attribute \src "libresoc.v:157058.17-157058.111" + wire $and$libresoc.v:157058$8300_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323957,7 +326454,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155426$8252 + cell $and $and$libresoc.v:157058$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323965,18 +326462,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155426$8252_Y + connect \Y $and$libresoc.v:157058$8300_Y end - connect \$1 $and$libresoc.v:155426$8252_Y + connect \$1 $and$libresoc.v:157058$8300_Y connect \trigger \$1 end -attribute \src "libresoc.v:155432.1-155443.10" +attribute \src "libresoc.v:157064.1-157075.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:155441.17-155441.111" - wire $and$libresoc.v:155441$8253_Y + attribute \src "libresoc.v:157073.17-157073.111" + wire $and$libresoc.v:157073$8301_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323986,7 +326483,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155441$8253 + cell $and $and$libresoc.v:157073$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323994,18 +326491,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155441$8253_Y + connect \Y $and$libresoc.v:157073$8301_Y end - connect \$1 $and$libresoc.v:155441$8253_Y + connect \$1 $and$libresoc.v:157073$8301_Y connect \trigger \$1 end -attribute \src "libresoc.v:155447.1-155458.10" +attribute \src "libresoc.v:157079.1-157090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:155456.17-155456.111" - wire $and$libresoc.v:155456$8254_Y + attribute \src "libresoc.v:157088.17-157088.111" + wire $and$libresoc.v:157088$8302_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324015,7 +326512,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155456$8254 + cell $and $and$libresoc.v:157088$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324023,18 +326520,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155456$8254_Y + connect \Y $and$libresoc.v:157088$8302_Y end - connect \$1 $and$libresoc.v:155456$8254_Y + connect \$1 $and$libresoc.v:157088$8302_Y connect \trigger \$1 end -attribute \src "libresoc.v:155462.1-155473.10" +attribute \src "libresoc.v:157094.1-157105.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:155471.17-155471.111" - wire $and$libresoc.v:155471$8255_Y + attribute \src "libresoc.v:157103.17-157103.111" + wire $and$libresoc.v:157103$8303_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324044,7 +326541,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155471$8255 + cell $and $and$libresoc.v:157103$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324052,18 +326549,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155471$8255_Y + connect \Y $and$libresoc.v:157103$8303_Y end - connect \$1 $and$libresoc.v:155471$8255_Y + connect \$1 $and$libresoc.v:157103$8303_Y connect \trigger \$1 end -attribute \src "libresoc.v:155477.1-155488.10" +attribute \src "libresoc.v:157109.1-157120.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:155486.17-155486.111" - wire $and$libresoc.v:155486$8256_Y + attribute \src "libresoc.v:157118.17-157118.111" + wire $and$libresoc.v:157118$8304_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324073,7 +326570,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155486$8256 + cell $and $and$libresoc.v:157118$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324081,18 +326578,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155486$8256_Y + connect \Y $and$libresoc.v:157118$8304_Y end - connect \$1 $and$libresoc.v:155486$8256_Y + connect \$1 $and$libresoc.v:157118$8304_Y connect \trigger \$1 end -attribute \src "libresoc.v:155492.1-155503.10" +attribute \src "libresoc.v:157124.1-157135.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:155501.17-155501.111" - wire $and$libresoc.v:155501$8257_Y + attribute \src "libresoc.v:157133.17-157133.111" + wire $and$libresoc.v:157133$8305_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324102,7 +326599,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155501$8257 + cell $and $and$libresoc.v:157133$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324110,18 +326607,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155501$8257_Y + connect \Y $and$libresoc.v:157133$8305_Y end - connect \$1 $and$libresoc.v:155501$8257_Y + connect \$1 $and$libresoc.v:157133$8305_Y connect \trigger \$1 end -attribute \src "libresoc.v:155507.1-155518.10" +attribute \src "libresoc.v:157139.1-157150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:155516.17-155516.111" - wire $and$libresoc.v:155516$8258_Y + attribute \src "libresoc.v:157148.17-157148.111" + wire $and$libresoc.v:157148$8306_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324131,7 +326628,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155516$8258 + cell $and $and$libresoc.v:157148$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324139,18 +326636,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155516$8258_Y + connect \Y $and$libresoc.v:157148$8306_Y end - connect \$1 $and$libresoc.v:155516$8258_Y + connect \$1 $and$libresoc.v:157148$8306_Y connect \trigger \$1 end -attribute \src "libresoc.v:155522.1-155533.10" +attribute \src "libresoc.v:157154.1-157165.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:155531.17-155531.111" - wire $and$libresoc.v:155531$8259_Y + attribute \src "libresoc.v:157163.17-157163.111" + wire $and$libresoc.v:157163$8307_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324160,7 +326657,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155531$8259 + cell $and $and$libresoc.v:157163$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324168,18 +326665,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155531$8259_Y + connect \Y $and$libresoc.v:157163$8307_Y end - connect \$1 $and$libresoc.v:155531$8259_Y + connect \$1 $and$libresoc.v:157163$8307_Y connect \trigger \$1 end -attribute \src "libresoc.v:155537.1-155548.10" +attribute \src "libresoc.v:157169.1-157180.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:155546.17-155546.111" - wire $and$libresoc.v:155546$8260_Y + attribute \src "libresoc.v:157178.17-157178.111" + wire $and$libresoc.v:157178$8308_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324189,7 +326686,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155546$8260 + cell $and $and$libresoc.v:157178$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324197,18 +326694,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155546$8260_Y + connect \Y $and$libresoc.v:157178$8308_Y end - connect \$1 $and$libresoc.v:155546$8260_Y + connect \$1 $and$libresoc.v:157178$8308_Y connect \trigger \$1 end -attribute \src "libresoc.v:155552.1-155563.10" +attribute \src "libresoc.v:157184.1-157195.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:155561.17-155561.111" - wire $and$libresoc.v:155561$8261_Y + attribute \src "libresoc.v:157193.17-157193.111" + wire $and$libresoc.v:157193$8309_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324218,7 +326715,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155561$8261 + cell $and $and$libresoc.v:157193$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324226,18 +326723,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155561$8261_Y + connect \Y $and$libresoc.v:157193$8309_Y end - connect \$1 $and$libresoc.v:155561$8261_Y + connect \$1 $and$libresoc.v:157193$8309_Y connect \trigger \$1 end -attribute \src "libresoc.v:155567.1-155578.10" +attribute \src "libresoc.v:157199.1-157210.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:155576.17-155576.111" - wire $and$libresoc.v:155576$8262_Y + attribute \src "libresoc.v:157208.17-157208.111" + wire $and$libresoc.v:157208$8310_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324247,7 +326744,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155576$8262 + cell $and $and$libresoc.v:157208$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324255,18 +326752,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155576$8262_Y + connect \Y $and$libresoc.v:157208$8310_Y end - connect \$1 $and$libresoc.v:155576$8262_Y + connect \$1 $and$libresoc.v:157208$8310_Y connect \trigger \$1 end -attribute \src "libresoc.v:155582.1-155593.10" +attribute \src "libresoc.v:157214.1-157225.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:155591.17-155591.111" - wire $and$libresoc.v:155591$8263_Y + attribute \src "libresoc.v:157223.17-157223.111" + wire $and$libresoc.v:157223$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324276,7 +326773,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155591$8263 + cell $and $and$libresoc.v:157223$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324284,18 +326781,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155591$8263_Y + connect \Y $and$libresoc.v:157223$8311_Y end - connect \$1 $and$libresoc.v:155591$8263_Y + connect \$1 $and$libresoc.v:157223$8311_Y connect \trigger \$1 end -attribute \src "libresoc.v:155597.1-155608.10" +attribute \src "libresoc.v:157229.1-157240.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:155606.17-155606.111" - wire $and$libresoc.v:155606$8264_Y + attribute \src "libresoc.v:157238.17-157238.111" + wire $and$libresoc.v:157238$8312_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324305,7 +326802,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155606$8264 + cell $and $and$libresoc.v:157238$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324313,18 +326810,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155606$8264_Y + connect \Y $and$libresoc.v:157238$8312_Y end - connect \$1 $and$libresoc.v:155606$8264_Y + connect \$1 $and$libresoc.v:157238$8312_Y connect \trigger \$1 end -attribute \src "libresoc.v:155612.1-155623.10" +attribute \src "libresoc.v:157244.1-157255.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:155621.17-155621.111" - wire $and$libresoc.v:155621$8265_Y + attribute \src "libresoc.v:157253.17-157253.111" + wire $and$libresoc.v:157253$8313_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324334,7 +326831,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155621$8265 + cell $and $and$libresoc.v:157253$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324342,18 +326839,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155621$8265_Y + connect \Y $and$libresoc.v:157253$8313_Y end - connect \$1 $and$libresoc.v:155621$8265_Y + connect \$1 $and$libresoc.v:157253$8313_Y connect \trigger \$1 end -attribute \src "libresoc.v:155627.1-155638.10" +attribute \src "libresoc.v:157259.1-157270.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:155636.17-155636.111" - wire $and$libresoc.v:155636$8266_Y + attribute \src "libresoc.v:157268.17-157268.111" + wire $and$libresoc.v:157268$8314_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324363,7 +326860,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155636$8266 + cell $and $and$libresoc.v:157268$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324371,18 +326868,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155636$8266_Y + connect \Y $and$libresoc.v:157268$8314_Y end - connect \$1 $and$libresoc.v:155636$8266_Y + connect \$1 $and$libresoc.v:157268$8314_Y connect \trigger \$1 end -attribute \src "libresoc.v:155642.1-155653.10" +attribute \src "libresoc.v:157274.1-157285.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:155651.17-155651.111" - wire $and$libresoc.v:155651$8267_Y + attribute \src "libresoc.v:157283.17-157283.111" + wire $and$libresoc.v:157283$8315_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324392,7 +326889,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155651$8267 + cell $and $and$libresoc.v:157283$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324400,18 +326897,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155651$8267_Y + connect \Y $and$libresoc.v:157283$8315_Y end - connect \$1 $and$libresoc.v:155651$8267_Y + connect \$1 $and$libresoc.v:157283$8315_Y connect \trigger \$1 end -attribute \src "libresoc.v:155657.1-155668.10" +attribute \src "libresoc.v:157289.1-157300.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:155666.17-155666.111" - wire $and$libresoc.v:155666$8268_Y + attribute \src "libresoc.v:157298.17-157298.111" + wire $and$libresoc.v:157298$8316_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324421,7 +326918,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155666$8268 + cell $and $and$libresoc.v:157298$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324429,42 +326926,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155666$8268_Y + connect \Y $and$libresoc.v:157298$8316_Y end - connect \$1 $and$libresoc.v:155666$8268_Y + connect \$1 $and$libresoc.v:157298$8316_Y connect \trigger \$1 end -attribute \src "libresoc.v:155672.1-155730.10" +attribute \src "libresoc.v:157304.1-157362.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:155673.7-155673.20" + attribute \src "libresoc.v:157305.7-157305.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155718.3-155726.6" - wire $0\q_int$next[0:0]$8279 - attribute \src "libresoc.v:155716.3-155717.27" + attribute \src "libresoc.v:157350.3-157358.6" + wire $0\q_int$next[0:0]$8327 + attribute \src "libresoc.v:157348.3-157349.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155718.3-155726.6" - wire $1\q_int$next[0:0]$8280 - attribute \src "libresoc.v:155695.7-155695.19" + attribute \src "libresoc.v:157350.3-157358.6" + wire $1\q_int$next[0:0]$8328 + attribute \src "libresoc.v:157327.7-157327.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155708.17-155708.96" - wire $and$libresoc.v:155708$8269_Y - attribute \src "libresoc.v:155713.17-155713.96" - wire $and$libresoc.v:155713$8274_Y - attribute \src "libresoc.v:155710.18-155710.93" - wire $not$libresoc.v:155710$8271_Y - attribute \src "libresoc.v:155712.17-155712.92" - wire $not$libresoc.v:155712$8273_Y - attribute \src "libresoc.v:155715.17-155715.92" - wire $not$libresoc.v:155715$8276_Y - attribute \src "libresoc.v:155709.18-155709.98" - wire $or$libresoc.v:155709$8270_Y - attribute \src "libresoc.v:155711.18-155711.99" - wire $or$libresoc.v:155711$8272_Y - attribute \src "libresoc.v:155714.17-155714.97" - wire $or$libresoc.v:155714$8275_Y + attribute \src "libresoc.v:157340.17-157340.96" + wire $and$libresoc.v:157340$8317_Y + attribute \src "libresoc.v:157345.17-157345.96" + wire $and$libresoc.v:157345$8322_Y + attribute \src "libresoc.v:157342.18-157342.93" + wire $not$libresoc.v:157342$8319_Y + attribute \src "libresoc.v:157344.17-157344.92" + wire $not$libresoc.v:157344$8321_Y + attribute \src "libresoc.v:157347.17-157347.92" + wire $not$libresoc.v:157347$8324_Y + attribute \src "libresoc.v:157341.18-157341.98" + wire $or$libresoc.v:157341$8318_Y + attribute \src "libresoc.v:157343.18-157343.99" + wire $or$libresoc.v:157343$8320_Y + attribute \src "libresoc.v:157346.17-157346.97" + wire $or$libresoc.v:157346$8323_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324481,11 +326978,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155673.7-155673.15" + attribute \src "libresoc.v:157305.7-157305.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324502,7 +326999,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155708$8269 + cell $and $and$libresoc.v:157340$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324510,10 +327007,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155708$8269_Y + connect \Y $and$libresoc.v:157340$8317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155713$8274 + cell $and $and$libresoc.v:157345$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324521,34 +327018,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155713$8274_Y + connect \Y $and$libresoc.v:157345$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155710$8271 + cell $not $not$libresoc.v:157342$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155710$8271_Y + connect \Y $not$libresoc.v:157342$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155712$8273 + cell $not $not$libresoc.v:157344$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155712$8273_Y + connect \Y $not$libresoc.v:157344$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155715$8276 + cell $not $not$libresoc.v:157347$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155715$8276_Y + connect \Y $not$libresoc.v:157347$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155709$8270 + cell $or $or$libresoc.v:157341$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324556,10 +327053,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155709$8270_Y + connect \Y $or$libresoc.v:157341$8318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155711$8272 + cell $or $or$libresoc.v:157343$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324567,10 +327064,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155711$8272_Y + connect \Y $or$libresoc.v:157343$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155714$8275 + cell $or $or$libresoc.v:157346$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324578,39 +327075,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155714$8275_Y + connect \Y $or$libresoc.v:157346$8323_Y end - attribute \src "libresoc.v:155673.7-155673.20" - process $proc$libresoc.v:155673$8281 + attribute \src "libresoc.v:157305.7-157305.20" + process $proc$libresoc.v:157305$8329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155695.7-155695.19" - process $proc$libresoc.v:155695$8282 + attribute \src "libresoc.v:157327.7-157327.19" + process $proc$libresoc.v:157327$8330 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155716.3-155717.27" - process $proc$libresoc.v:155716$8277 + attribute \src "libresoc.v:157348.3-157349.27" + process $proc$libresoc.v:157348$8325 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155718.3-155726.6" - process $proc$libresoc.v:155718$8278 + attribute \src "libresoc.v:157350.3-157358.6" + process $proc$libresoc.v:157350$8326 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8279 $1\q_int$next[0:0]$8280 - attribute \src "libresoc.v:155719.5-155719.29" + assign $0\q_int$next[0:0]$8327 $1\q_int$next[0:0]$8328 + attribute \src "libresoc.v:157351.5-157351.29" switch \initial - attribute \src "libresoc.v:155719.9-155719.17" + attribute \src "libresoc.v:157351.9-157351.17" case 1'1 case end @@ -324619,56 +327116,56 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8280 1'0 + assign $1\q_int$next[0:0]$8328 1'0 case - assign $1\q_int$next[0:0]$8280 \$5 + assign $1\q_int$next[0:0]$8328 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8279 + update \q_int$next $0\q_int$next[0:0]$8327 end - connect \$9 $and$libresoc.v:155708$8269_Y - connect \$11 $or$libresoc.v:155709$8270_Y - connect \$13 $not$libresoc.v:155710$8271_Y - connect \$15 $or$libresoc.v:155711$8272_Y - connect \$1 $not$libresoc.v:155712$8273_Y - connect \$3 $and$libresoc.v:155713$8274_Y - connect \$5 $or$libresoc.v:155714$8275_Y - connect \$7 $not$libresoc.v:155715$8276_Y + connect \$9 $and$libresoc.v:157340$8317_Y + connect \$11 $or$libresoc.v:157341$8318_Y + connect \$13 $not$libresoc.v:157342$8319_Y + connect \$15 $or$libresoc.v:157343$8320_Y + connect \$1 $not$libresoc.v:157344$8321_Y + connect \$3 $and$libresoc.v:157345$8322_Y + connect \$5 $or$libresoc.v:157346$8323_Y + connect \$7 $not$libresoc.v:157347$8324_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155734.1-155792.10" +attribute \src "libresoc.v:157366.1-157424.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:155735.7-155735.20" + attribute \src "libresoc.v:157367.7-157367.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155780.3-155788.6" - wire $0\q_int$next[0:0]$8293 - attribute \src "libresoc.v:155778.3-155779.27" + attribute \src "libresoc.v:157412.3-157420.6" + wire $0\q_int$next[0:0]$8341 + attribute \src "libresoc.v:157410.3-157411.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155780.3-155788.6" - wire $1\q_int$next[0:0]$8294 - attribute \src "libresoc.v:155757.7-155757.19" + attribute \src "libresoc.v:157412.3-157420.6" + wire $1\q_int$next[0:0]$8342 + attribute \src "libresoc.v:157389.7-157389.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155770.17-155770.96" - wire $and$libresoc.v:155770$8283_Y - attribute \src "libresoc.v:155775.17-155775.96" - wire $and$libresoc.v:155775$8288_Y - attribute \src "libresoc.v:155772.18-155772.93" - wire $not$libresoc.v:155772$8285_Y - attribute \src "libresoc.v:155774.17-155774.92" - wire $not$libresoc.v:155774$8287_Y - attribute \src "libresoc.v:155777.17-155777.92" - wire $not$libresoc.v:155777$8290_Y - attribute \src "libresoc.v:155771.18-155771.98" - wire $or$libresoc.v:155771$8284_Y - attribute \src "libresoc.v:155773.18-155773.99" - wire $or$libresoc.v:155773$8286_Y - attribute \src "libresoc.v:155776.17-155776.97" - wire $or$libresoc.v:155776$8289_Y + attribute \src "libresoc.v:157402.17-157402.96" + wire $and$libresoc.v:157402$8331_Y + attribute \src "libresoc.v:157407.17-157407.96" + wire $and$libresoc.v:157407$8336_Y + attribute \src "libresoc.v:157404.18-157404.93" + wire $not$libresoc.v:157404$8333_Y + attribute \src "libresoc.v:157406.17-157406.92" + wire $not$libresoc.v:157406$8335_Y + attribute \src "libresoc.v:157409.17-157409.92" + wire $not$libresoc.v:157409$8338_Y + attribute \src "libresoc.v:157403.18-157403.98" + wire $or$libresoc.v:157403$8332_Y + attribute \src "libresoc.v:157405.18-157405.99" + wire $or$libresoc.v:157405$8334_Y + attribute \src "libresoc.v:157408.17-157408.97" + wire $or$libresoc.v:157408$8337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324685,11 +327182,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155735.7-155735.15" + attribute \src "libresoc.v:157367.7-157367.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324706,7 +327203,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155770$8283 + cell $and $and$libresoc.v:157402$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324714,10 +327211,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155770$8283_Y + connect \Y $and$libresoc.v:157402$8331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155775$8288 + cell $and $and$libresoc.v:157407$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324725,34 +327222,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155775$8288_Y + connect \Y $and$libresoc.v:157407$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155772$8285 + cell $not $not$libresoc.v:157404$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155772$8285_Y + connect \Y $not$libresoc.v:157404$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155774$8287 + cell $not $not$libresoc.v:157406$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155774$8287_Y + connect \Y $not$libresoc.v:157406$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155777$8290 + cell $not $not$libresoc.v:157409$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155777$8290_Y + connect \Y $not$libresoc.v:157409$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155771$8284 + cell $or $or$libresoc.v:157403$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324760,10 +327257,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155771$8284_Y + connect \Y $or$libresoc.v:157403$8332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155773$8286 + cell $or $or$libresoc.v:157405$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324771,10 +327268,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155773$8286_Y + connect \Y $or$libresoc.v:157405$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155776$8289 + cell $or $or$libresoc.v:157408$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324782,39 +327279,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155776$8289_Y + connect \Y $or$libresoc.v:157408$8337_Y end - attribute \src "libresoc.v:155735.7-155735.20" - process $proc$libresoc.v:155735$8295 + attribute \src "libresoc.v:157367.7-157367.20" + process $proc$libresoc.v:157367$8343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155757.7-155757.19" - process $proc$libresoc.v:155757$8296 + attribute \src "libresoc.v:157389.7-157389.19" + process $proc$libresoc.v:157389$8344 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155778.3-155779.27" - process $proc$libresoc.v:155778$8291 + attribute \src "libresoc.v:157410.3-157411.27" + process $proc$libresoc.v:157410$8339 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155780.3-155788.6" - process $proc$libresoc.v:155780$8292 + attribute \src "libresoc.v:157412.3-157420.6" + process $proc$libresoc.v:157412$8340 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8293 $1\q_int$next[0:0]$8294 - attribute \src "libresoc.v:155781.5-155781.29" + assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 + attribute \src "libresoc.v:157413.5-157413.29" switch \initial - attribute \src "libresoc.v:155781.9-155781.17" + attribute \src "libresoc.v:157413.9-157413.17" case 1'1 case end @@ -324823,56 +327320,56 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8294 1'0 + assign $1\q_int$next[0:0]$8342 1'0 case - assign $1\q_int$next[0:0]$8294 \$5 + assign $1\q_int$next[0:0]$8342 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8293 + update \q_int$next $0\q_int$next[0:0]$8341 end - connect \$9 $and$libresoc.v:155770$8283_Y - connect \$11 $or$libresoc.v:155771$8284_Y - connect \$13 $not$libresoc.v:155772$8285_Y - connect \$15 $or$libresoc.v:155773$8286_Y - connect \$1 $not$libresoc.v:155774$8287_Y - connect \$3 $and$libresoc.v:155775$8288_Y - connect \$5 $or$libresoc.v:155776$8289_Y - connect \$7 $not$libresoc.v:155777$8290_Y + connect \$9 $and$libresoc.v:157402$8331_Y + connect \$11 $or$libresoc.v:157403$8332_Y + connect \$13 $not$libresoc.v:157404$8333_Y + connect \$15 $or$libresoc.v:157405$8334_Y + connect \$1 $not$libresoc.v:157406$8335_Y + connect \$3 $and$libresoc.v:157407$8336_Y + connect \$5 $or$libresoc.v:157408$8337_Y + connect \$7 $not$libresoc.v:157409$8338_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155796.1-155854.10" +attribute \src "libresoc.v:157428.1-157486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:155797.7-155797.20" + attribute \src "libresoc.v:157429.7-157429.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155842.3-155850.6" - wire $0\q_int$next[0:0]$8307 - attribute \src "libresoc.v:155840.3-155841.27" + attribute \src "libresoc.v:157474.3-157482.6" + wire $0\q_int$next[0:0]$8355 + attribute \src "libresoc.v:157472.3-157473.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155842.3-155850.6" - wire $1\q_int$next[0:0]$8308 - attribute \src "libresoc.v:155819.7-155819.19" + attribute \src "libresoc.v:157474.3-157482.6" + wire $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157451.7-157451.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155832.17-155832.96" - wire $and$libresoc.v:155832$8297_Y - attribute \src "libresoc.v:155837.17-155837.96" - wire $and$libresoc.v:155837$8302_Y - attribute \src "libresoc.v:155834.18-155834.93" - wire $not$libresoc.v:155834$8299_Y - attribute \src "libresoc.v:155836.17-155836.92" - wire $not$libresoc.v:155836$8301_Y - attribute \src "libresoc.v:155839.17-155839.92" - wire $not$libresoc.v:155839$8304_Y - attribute \src "libresoc.v:155833.18-155833.98" - wire $or$libresoc.v:155833$8298_Y - attribute \src "libresoc.v:155835.18-155835.99" - wire $or$libresoc.v:155835$8300_Y - attribute \src "libresoc.v:155838.17-155838.97" - wire $or$libresoc.v:155838$8303_Y + attribute \src "libresoc.v:157464.17-157464.96" + wire $and$libresoc.v:157464$8345_Y + attribute \src "libresoc.v:157469.17-157469.96" + wire $and$libresoc.v:157469$8350_Y + attribute \src "libresoc.v:157466.18-157466.93" + wire $not$libresoc.v:157466$8347_Y + attribute \src "libresoc.v:157468.17-157468.92" + wire $not$libresoc.v:157468$8349_Y + attribute \src "libresoc.v:157471.17-157471.92" + wire $not$libresoc.v:157471$8352_Y + attribute \src "libresoc.v:157465.18-157465.98" + wire $or$libresoc.v:157465$8346_Y + attribute \src "libresoc.v:157467.18-157467.99" + wire $or$libresoc.v:157467$8348_Y + attribute \src "libresoc.v:157470.17-157470.97" + wire $or$libresoc.v:157470$8351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324889,11 +327386,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155797.7-155797.15" + attribute \src "libresoc.v:157429.7-157429.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324910,7 +327407,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155832$8297 + cell $and $and$libresoc.v:157464$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324918,10 +327415,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155832$8297_Y + connect \Y $and$libresoc.v:157464$8345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155837$8302 + cell $and $and$libresoc.v:157469$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324929,34 +327426,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155837$8302_Y + connect \Y $and$libresoc.v:157469$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155834$8299 + cell $not $not$libresoc.v:157466$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155834$8299_Y + connect \Y $not$libresoc.v:157466$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155836$8301 + cell $not $not$libresoc.v:157468$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155836$8301_Y + connect \Y $not$libresoc.v:157468$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155839$8304 + cell $not $not$libresoc.v:157471$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155839$8304_Y + connect \Y $not$libresoc.v:157471$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155833$8298 + cell $or $or$libresoc.v:157465$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324964,10 +327461,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155833$8298_Y + connect \Y $or$libresoc.v:157465$8346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155835$8300 + cell $or $or$libresoc.v:157467$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324975,10 +327472,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155835$8300_Y + connect \Y $or$libresoc.v:157467$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155838$8303 + cell $or $or$libresoc.v:157470$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324986,39 +327483,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155838$8303_Y + connect \Y $or$libresoc.v:157470$8351_Y end - attribute \src "libresoc.v:155797.7-155797.20" - process $proc$libresoc.v:155797$8309 + attribute \src "libresoc.v:157429.7-157429.20" + process $proc$libresoc.v:157429$8357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155819.7-155819.19" - process $proc$libresoc.v:155819$8310 + attribute \src "libresoc.v:157451.7-157451.19" + process $proc$libresoc.v:157451$8358 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155840.3-155841.27" - process $proc$libresoc.v:155840$8305 + attribute \src "libresoc.v:157472.3-157473.27" + process $proc$libresoc.v:157472$8353 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155842.3-155850.6" - process $proc$libresoc.v:155842$8306 + attribute \src "libresoc.v:157474.3-157482.6" + process $proc$libresoc.v:157474$8354 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8307 $1\q_int$next[0:0]$8308 - attribute \src "libresoc.v:155843.5-155843.29" + assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157475.5-157475.29" switch \initial - attribute \src "libresoc.v:155843.9-155843.17" + attribute \src "libresoc.v:157475.9-157475.17" case 1'1 case end @@ -325027,56 +327524,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8308 1'0 + assign $1\q_int$next[0:0]$8356 1'0 case - assign $1\q_int$next[0:0]$8308 \$5 + assign $1\q_int$next[0:0]$8356 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8307 + update \q_int$next $0\q_int$next[0:0]$8355 end - connect \$9 $and$libresoc.v:155832$8297_Y - connect \$11 $or$libresoc.v:155833$8298_Y - connect \$13 $not$libresoc.v:155834$8299_Y - connect \$15 $or$libresoc.v:155835$8300_Y - connect \$1 $not$libresoc.v:155836$8301_Y - connect \$3 $and$libresoc.v:155837$8302_Y - connect \$5 $or$libresoc.v:155838$8303_Y - connect \$7 $not$libresoc.v:155839$8304_Y + connect \$9 $and$libresoc.v:157464$8345_Y + connect \$11 $or$libresoc.v:157465$8346_Y + connect \$13 $not$libresoc.v:157466$8347_Y + connect \$15 $or$libresoc.v:157467$8348_Y + connect \$1 $not$libresoc.v:157468$8349_Y + connect \$3 $and$libresoc.v:157469$8350_Y + connect \$5 $or$libresoc.v:157470$8351_Y + connect \$7 $not$libresoc.v:157471$8352_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155858.1-155916.10" +attribute \src "libresoc.v:157490.1-157548.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:155859.7-155859.20" + attribute \src "libresoc.v:157491.7-157491.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155904.3-155912.6" - wire $0\q_int$next[0:0]$8321 - attribute \src "libresoc.v:155902.3-155903.27" + attribute \src "libresoc.v:157536.3-157544.6" + wire $0\q_int$next[0:0]$8369 + attribute \src "libresoc.v:157534.3-157535.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155904.3-155912.6" - wire $1\q_int$next[0:0]$8322 - attribute \src "libresoc.v:155881.7-155881.19" + attribute \src "libresoc.v:157536.3-157544.6" + wire $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157513.7-157513.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155894.17-155894.96" - wire $and$libresoc.v:155894$8311_Y - attribute \src "libresoc.v:155899.17-155899.96" - wire $and$libresoc.v:155899$8316_Y - attribute \src "libresoc.v:155896.18-155896.93" - wire $not$libresoc.v:155896$8313_Y - attribute \src "libresoc.v:155898.17-155898.92" - wire $not$libresoc.v:155898$8315_Y - attribute \src "libresoc.v:155901.17-155901.92" - wire $not$libresoc.v:155901$8318_Y - attribute \src "libresoc.v:155895.18-155895.98" - wire $or$libresoc.v:155895$8312_Y - attribute \src "libresoc.v:155897.18-155897.99" - wire $or$libresoc.v:155897$8314_Y - attribute \src "libresoc.v:155900.17-155900.97" - wire $or$libresoc.v:155900$8317_Y + attribute \src "libresoc.v:157526.17-157526.96" + wire $and$libresoc.v:157526$8359_Y + attribute \src "libresoc.v:157531.17-157531.96" + wire $and$libresoc.v:157531$8364_Y + attribute \src "libresoc.v:157528.18-157528.93" + wire $not$libresoc.v:157528$8361_Y + attribute \src "libresoc.v:157530.17-157530.92" + wire $not$libresoc.v:157530$8363_Y + attribute \src "libresoc.v:157533.17-157533.92" + wire $not$libresoc.v:157533$8366_Y + attribute \src "libresoc.v:157527.18-157527.98" + wire $or$libresoc.v:157527$8360_Y + attribute \src "libresoc.v:157529.18-157529.99" + wire $or$libresoc.v:157529$8362_Y + attribute \src "libresoc.v:157532.17-157532.97" + wire $or$libresoc.v:157532$8365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325093,11 +327590,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155859.7-155859.15" + attribute \src "libresoc.v:157491.7-157491.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325114,7 +327611,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155894$8311 + cell $and $and$libresoc.v:157526$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325122,10 +327619,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155894$8311_Y + connect \Y $and$libresoc.v:157526$8359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155899$8316 + cell $and $and$libresoc.v:157531$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325133,34 +327630,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155899$8316_Y + connect \Y $and$libresoc.v:157531$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155896$8313 + cell $not $not$libresoc.v:157528$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155896$8313_Y + connect \Y $not$libresoc.v:157528$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155898$8315 + cell $not $not$libresoc.v:157530$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155898$8315_Y + connect \Y $not$libresoc.v:157530$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155901$8318 + cell $not $not$libresoc.v:157533$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155901$8318_Y + connect \Y $not$libresoc.v:157533$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155895$8312 + cell $or $or$libresoc.v:157527$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325168,10 +327665,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155895$8312_Y + connect \Y $or$libresoc.v:157527$8360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155897$8314 + cell $or $or$libresoc.v:157529$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325179,10 +327676,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155897$8314_Y + connect \Y $or$libresoc.v:157529$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155900$8317 + cell $or $or$libresoc.v:157532$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325190,39 +327687,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155900$8317_Y + connect \Y $or$libresoc.v:157532$8365_Y end - attribute \src "libresoc.v:155859.7-155859.20" - process $proc$libresoc.v:155859$8323 + attribute \src "libresoc.v:157491.7-157491.20" + process $proc$libresoc.v:157491$8371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155881.7-155881.19" - process $proc$libresoc.v:155881$8324 + attribute \src "libresoc.v:157513.7-157513.19" + process $proc$libresoc.v:157513$8372 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155902.3-155903.27" - process $proc$libresoc.v:155902$8319 + attribute \src "libresoc.v:157534.3-157535.27" + process $proc$libresoc.v:157534$8367 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155904.3-155912.6" - process $proc$libresoc.v:155904$8320 + attribute \src "libresoc.v:157536.3-157544.6" + process $proc$libresoc.v:157536$8368 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8321 $1\q_int$next[0:0]$8322 - attribute \src "libresoc.v:155905.5-155905.29" + assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157537.5-157537.29" switch \initial - attribute \src "libresoc.v:155905.9-155905.17" + attribute \src "libresoc.v:157537.9-157537.17" case 1'1 case end @@ -325231,56 +327728,56 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8322 1'0 + assign $1\q_int$next[0:0]$8370 1'0 case - assign $1\q_int$next[0:0]$8322 \$5 + assign $1\q_int$next[0:0]$8370 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8321 + update \q_int$next $0\q_int$next[0:0]$8369 end - connect \$9 $and$libresoc.v:155894$8311_Y - connect \$11 $or$libresoc.v:155895$8312_Y - connect \$13 $not$libresoc.v:155896$8313_Y - connect \$15 $or$libresoc.v:155897$8314_Y - connect \$1 $not$libresoc.v:155898$8315_Y - connect \$3 $and$libresoc.v:155899$8316_Y - connect \$5 $or$libresoc.v:155900$8317_Y - connect \$7 $not$libresoc.v:155901$8318_Y + connect \$9 $and$libresoc.v:157526$8359_Y + connect \$11 $or$libresoc.v:157527$8360_Y + connect \$13 $not$libresoc.v:157528$8361_Y + connect \$15 $or$libresoc.v:157529$8362_Y + connect \$1 $not$libresoc.v:157530$8363_Y + connect \$3 $and$libresoc.v:157531$8364_Y + connect \$5 $or$libresoc.v:157532$8365_Y + connect \$7 $not$libresoc.v:157533$8366_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155920.1-155978.10" +attribute \src "libresoc.v:157552.1-157610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:155921.7-155921.20" + attribute \src "libresoc.v:157553.7-157553.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155966.3-155974.6" - wire $0\q_int$next[0:0]$8335 - attribute \src "libresoc.v:155964.3-155965.27" + attribute \src "libresoc.v:157598.3-157606.6" + wire $0\q_int$next[0:0]$8383 + attribute \src "libresoc.v:157596.3-157597.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155966.3-155974.6" - wire $1\q_int$next[0:0]$8336 - attribute \src "libresoc.v:155943.7-155943.19" + attribute \src "libresoc.v:157598.3-157606.6" + wire $1\q_int$next[0:0]$8384 + attribute \src "libresoc.v:157575.7-157575.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155956.17-155956.96" - wire $and$libresoc.v:155956$8325_Y - attribute \src "libresoc.v:155961.17-155961.96" - wire $and$libresoc.v:155961$8330_Y - attribute \src "libresoc.v:155958.18-155958.93" - wire $not$libresoc.v:155958$8327_Y - attribute \src "libresoc.v:155960.17-155960.92" - wire $not$libresoc.v:155960$8329_Y - attribute \src "libresoc.v:155963.17-155963.92" - wire $not$libresoc.v:155963$8332_Y - attribute \src "libresoc.v:155957.18-155957.98" - wire $or$libresoc.v:155957$8326_Y - attribute \src "libresoc.v:155959.18-155959.99" - wire $or$libresoc.v:155959$8328_Y - attribute \src "libresoc.v:155962.17-155962.97" - wire $or$libresoc.v:155962$8331_Y + attribute \src "libresoc.v:157588.17-157588.96" + wire $and$libresoc.v:157588$8373_Y + attribute \src "libresoc.v:157593.17-157593.96" + wire $and$libresoc.v:157593$8378_Y + attribute \src "libresoc.v:157590.18-157590.93" + wire $not$libresoc.v:157590$8375_Y + attribute \src "libresoc.v:157592.17-157592.92" + wire $not$libresoc.v:157592$8377_Y + attribute \src "libresoc.v:157595.17-157595.92" + wire $not$libresoc.v:157595$8380_Y + attribute \src "libresoc.v:157589.18-157589.98" + wire $or$libresoc.v:157589$8374_Y + attribute \src "libresoc.v:157591.18-157591.99" + wire $or$libresoc.v:157591$8376_Y + attribute \src "libresoc.v:157594.17-157594.97" + wire $or$libresoc.v:157594$8379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325297,11 +327794,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155921.7-155921.15" + attribute \src "libresoc.v:157553.7-157553.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325318,7 +327815,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155956$8325 + cell $and $and$libresoc.v:157588$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325326,10 +327823,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155956$8325_Y + connect \Y $and$libresoc.v:157588$8373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155961$8330 + cell $and $and$libresoc.v:157593$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325337,34 +327834,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155961$8330_Y + connect \Y $and$libresoc.v:157593$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155958$8327 + cell $not $not$libresoc.v:157590$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155958$8327_Y + connect \Y $not$libresoc.v:157590$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155960$8329 + cell $not $not$libresoc.v:157592$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155960$8329_Y + connect \Y $not$libresoc.v:157592$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155963$8332 + cell $not $not$libresoc.v:157595$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155963$8332_Y + connect \Y $not$libresoc.v:157595$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155957$8326 + cell $or $or$libresoc.v:157589$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325372,10 +327869,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155957$8326_Y + connect \Y $or$libresoc.v:157589$8374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155959$8328 + cell $or $or$libresoc.v:157591$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325383,10 +327880,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155959$8328_Y + connect \Y $or$libresoc.v:157591$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155962$8331 + cell $or $or$libresoc.v:157594$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325394,39 +327891,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155962$8331_Y + connect \Y $or$libresoc.v:157594$8379_Y end - attribute \src "libresoc.v:155921.7-155921.20" - process $proc$libresoc.v:155921$8337 + attribute \src "libresoc.v:157553.7-157553.20" + process $proc$libresoc.v:157553$8385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155943.7-155943.19" - process $proc$libresoc.v:155943$8338 + attribute \src "libresoc.v:157575.7-157575.19" + process $proc$libresoc.v:157575$8386 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155964.3-155965.27" - process $proc$libresoc.v:155964$8333 + attribute \src "libresoc.v:157596.3-157597.27" + process $proc$libresoc.v:157596$8381 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155966.3-155974.6" - process $proc$libresoc.v:155966$8334 + attribute \src "libresoc.v:157598.3-157606.6" + process $proc$libresoc.v:157598$8382 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8335 $1\q_int$next[0:0]$8336 - attribute \src "libresoc.v:155967.5-155967.29" + assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 + attribute \src "libresoc.v:157599.5-157599.29" switch \initial - attribute \src "libresoc.v:155967.9-155967.17" + attribute \src "libresoc.v:157599.9-157599.17" case 1'1 case end @@ -325435,56 +327932,56 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8336 1'0 + assign $1\q_int$next[0:0]$8384 1'0 case - assign $1\q_int$next[0:0]$8336 \$5 + assign $1\q_int$next[0:0]$8384 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8335 + update \q_int$next $0\q_int$next[0:0]$8383 end - connect \$9 $and$libresoc.v:155956$8325_Y - connect \$11 $or$libresoc.v:155957$8326_Y - connect \$13 $not$libresoc.v:155958$8327_Y - connect \$15 $or$libresoc.v:155959$8328_Y - connect \$1 $not$libresoc.v:155960$8329_Y - connect \$3 $and$libresoc.v:155961$8330_Y - connect \$5 $or$libresoc.v:155962$8331_Y - connect \$7 $not$libresoc.v:155963$8332_Y + connect \$9 $and$libresoc.v:157588$8373_Y + connect \$11 $or$libresoc.v:157589$8374_Y + connect \$13 $not$libresoc.v:157590$8375_Y + connect \$15 $or$libresoc.v:157591$8376_Y + connect \$1 $not$libresoc.v:157592$8377_Y + connect \$3 $and$libresoc.v:157593$8378_Y + connect \$5 $or$libresoc.v:157594$8379_Y + connect \$7 $not$libresoc.v:157595$8380_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155982.1-156040.10" +attribute \src "libresoc.v:157614.1-157672.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:155983.7-155983.20" + attribute \src "libresoc.v:157615.7-157615.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156028.3-156036.6" - wire $0\q_int$next[0:0]$8349 - attribute \src "libresoc.v:156026.3-156027.27" + attribute \src "libresoc.v:157660.3-157668.6" + wire $0\q_int$next[0:0]$8397 + attribute \src "libresoc.v:157658.3-157659.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156028.3-156036.6" - wire $1\q_int$next[0:0]$8350 - attribute \src "libresoc.v:156005.7-156005.19" + attribute \src "libresoc.v:157660.3-157668.6" + wire $1\q_int$next[0:0]$8398 + attribute \src "libresoc.v:157637.7-157637.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156018.17-156018.96" - wire $and$libresoc.v:156018$8339_Y - attribute \src "libresoc.v:156023.17-156023.96" - wire $and$libresoc.v:156023$8344_Y - attribute \src "libresoc.v:156020.18-156020.93" - wire $not$libresoc.v:156020$8341_Y - attribute \src "libresoc.v:156022.17-156022.92" - wire $not$libresoc.v:156022$8343_Y - attribute \src "libresoc.v:156025.17-156025.92" - wire $not$libresoc.v:156025$8346_Y - attribute \src "libresoc.v:156019.18-156019.98" - wire $or$libresoc.v:156019$8340_Y - attribute \src "libresoc.v:156021.18-156021.99" - wire $or$libresoc.v:156021$8342_Y - attribute \src "libresoc.v:156024.17-156024.97" - wire $or$libresoc.v:156024$8345_Y + attribute \src "libresoc.v:157650.17-157650.96" + wire $and$libresoc.v:157650$8387_Y + attribute \src "libresoc.v:157655.17-157655.96" + wire $and$libresoc.v:157655$8392_Y + attribute \src "libresoc.v:157652.18-157652.93" + wire $not$libresoc.v:157652$8389_Y + attribute \src "libresoc.v:157654.17-157654.92" + wire $not$libresoc.v:157654$8391_Y + attribute \src "libresoc.v:157657.17-157657.92" + wire $not$libresoc.v:157657$8394_Y + attribute \src "libresoc.v:157651.18-157651.98" + wire $or$libresoc.v:157651$8388_Y + attribute \src "libresoc.v:157653.18-157653.99" + wire $or$libresoc.v:157653$8390_Y + attribute \src "libresoc.v:157656.17-157656.97" + wire $or$libresoc.v:157656$8393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325501,11 +327998,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155983.7-155983.15" + attribute \src "libresoc.v:157615.7-157615.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325522,7 +328019,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156018$8339 + cell $and $and$libresoc.v:157650$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325530,10 +328027,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156018$8339_Y + connect \Y $and$libresoc.v:157650$8387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156023$8344 + cell $and $and$libresoc.v:157655$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325541,34 +328038,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156023$8344_Y + connect \Y $and$libresoc.v:157655$8392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156020$8341 + cell $not $not$libresoc.v:157652$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156020$8341_Y + connect \Y $not$libresoc.v:157652$8389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156022$8343 + cell $not $not$libresoc.v:157654$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156022$8343_Y + connect \Y $not$libresoc.v:157654$8391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156025$8346 + cell $not $not$libresoc.v:157657$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156025$8346_Y + connect \Y $not$libresoc.v:157657$8394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156019$8340 + cell $or $or$libresoc.v:157651$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325576,10 +328073,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156019$8340_Y + connect \Y $or$libresoc.v:157651$8388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156021$8342 + cell $or $or$libresoc.v:157653$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325587,10 +328084,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156021$8342_Y + connect \Y $or$libresoc.v:157653$8390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156024$8345 + cell $or $or$libresoc.v:157656$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325598,39 +328095,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156024$8345_Y + connect \Y $or$libresoc.v:157656$8393_Y end - attribute \src "libresoc.v:155983.7-155983.20" - process $proc$libresoc.v:155983$8351 + attribute \src "libresoc.v:157615.7-157615.20" + process $proc$libresoc.v:157615$8399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156005.7-156005.19" - process $proc$libresoc.v:156005$8352 + attribute \src "libresoc.v:157637.7-157637.19" + process $proc$libresoc.v:157637$8400 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156026.3-156027.27" - process $proc$libresoc.v:156026$8347 + attribute \src "libresoc.v:157658.3-157659.27" + process $proc$libresoc.v:157658$8395 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156028.3-156036.6" - process $proc$libresoc.v:156028$8348 + attribute \src "libresoc.v:157660.3-157668.6" + process $proc$libresoc.v:157660$8396 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8349 $1\q_int$next[0:0]$8350 - attribute \src "libresoc.v:156029.5-156029.29" + assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 + attribute \src "libresoc.v:157661.5-157661.29" switch \initial - attribute \src "libresoc.v:156029.9-156029.17" + attribute \src "libresoc.v:157661.9-157661.17" case 1'1 case end @@ -325639,56 +328136,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8350 1'0 + assign $1\q_int$next[0:0]$8398 1'0 case - assign $1\q_int$next[0:0]$8350 \$5 + assign $1\q_int$next[0:0]$8398 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8349 + update \q_int$next $0\q_int$next[0:0]$8397 end - connect \$9 $and$libresoc.v:156018$8339_Y - connect \$11 $or$libresoc.v:156019$8340_Y - connect \$13 $not$libresoc.v:156020$8341_Y - connect \$15 $or$libresoc.v:156021$8342_Y - connect \$1 $not$libresoc.v:156022$8343_Y - connect \$3 $and$libresoc.v:156023$8344_Y - connect \$5 $or$libresoc.v:156024$8345_Y - connect \$7 $not$libresoc.v:156025$8346_Y + connect \$9 $and$libresoc.v:157650$8387_Y + connect \$11 $or$libresoc.v:157651$8388_Y + connect \$13 $not$libresoc.v:157652$8389_Y + connect \$15 $or$libresoc.v:157653$8390_Y + connect \$1 $not$libresoc.v:157654$8391_Y + connect \$3 $and$libresoc.v:157655$8392_Y + connect \$5 $or$libresoc.v:157656$8393_Y + connect \$7 $not$libresoc.v:157657$8394_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156044.1-156102.10" +attribute \src "libresoc.v:157676.1-157734.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:156045.7-156045.20" + attribute \src "libresoc.v:157677.7-157677.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156090.3-156098.6" - wire $0\q_int$next[0:0]$8363 - attribute \src "libresoc.v:156088.3-156089.27" + attribute \src "libresoc.v:157722.3-157730.6" + wire $0\q_int$next[0:0]$8411 + attribute \src "libresoc.v:157720.3-157721.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156090.3-156098.6" - wire $1\q_int$next[0:0]$8364 - attribute \src "libresoc.v:156067.7-156067.19" + attribute \src "libresoc.v:157722.3-157730.6" + wire $1\q_int$next[0:0]$8412 + attribute \src "libresoc.v:157699.7-157699.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156080.17-156080.96" - wire $and$libresoc.v:156080$8353_Y - attribute \src "libresoc.v:156085.17-156085.96" - wire $and$libresoc.v:156085$8358_Y - attribute \src "libresoc.v:156082.18-156082.93" - wire $not$libresoc.v:156082$8355_Y - attribute \src "libresoc.v:156084.17-156084.92" - wire $not$libresoc.v:156084$8357_Y - attribute \src "libresoc.v:156087.17-156087.92" - wire $not$libresoc.v:156087$8360_Y - attribute \src "libresoc.v:156081.18-156081.98" - wire $or$libresoc.v:156081$8354_Y - attribute \src "libresoc.v:156083.18-156083.99" - wire $or$libresoc.v:156083$8356_Y - attribute \src "libresoc.v:156086.17-156086.97" - wire $or$libresoc.v:156086$8359_Y + attribute \src "libresoc.v:157712.17-157712.96" + wire $and$libresoc.v:157712$8401_Y + attribute \src "libresoc.v:157717.17-157717.96" + wire $and$libresoc.v:157717$8406_Y + attribute \src "libresoc.v:157714.18-157714.93" + wire $not$libresoc.v:157714$8403_Y + attribute \src "libresoc.v:157716.17-157716.92" + wire $not$libresoc.v:157716$8405_Y + attribute \src "libresoc.v:157719.17-157719.92" + wire $not$libresoc.v:157719$8408_Y + attribute \src "libresoc.v:157713.18-157713.98" + wire $or$libresoc.v:157713$8402_Y + attribute \src "libresoc.v:157715.18-157715.99" + wire $or$libresoc.v:157715$8404_Y + attribute \src "libresoc.v:157718.17-157718.97" + wire $or$libresoc.v:157718$8407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325705,11 +328202,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156045.7-156045.15" + attribute \src "libresoc.v:157677.7-157677.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325726,7 +328223,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156080$8353 + cell $and $and$libresoc.v:157712$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325734,10 +328231,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156080$8353_Y + connect \Y $and$libresoc.v:157712$8401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156085$8358 + cell $and $and$libresoc.v:157717$8406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325745,34 +328242,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156085$8358_Y + connect \Y $and$libresoc.v:157717$8406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156082$8355 + cell $not $not$libresoc.v:157714$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156082$8355_Y + connect \Y $not$libresoc.v:157714$8403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156084$8357 + cell $not $not$libresoc.v:157716$8405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156084$8357_Y + connect \Y $not$libresoc.v:157716$8405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156087$8360 + cell $not $not$libresoc.v:157719$8408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156087$8360_Y + connect \Y $not$libresoc.v:157719$8408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156081$8354 + cell $or $or$libresoc.v:157713$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325780,10 +328277,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156081$8354_Y + connect \Y $or$libresoc.v:157713$8402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156083$8356 + cell $or $or$libresoc.v:157715$8404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325791,10 +328288,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156083$8356_Y + connect \Y $or$libresoc.v:157715$8404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156086$8359 + cell $or $or$libresoc.v:157718$8407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325802,39 +328299,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156086$8359_Y + connect \Y $or$libresoc.v:157718$8407_Y end - attribute \src "libresoc.v:156045.7-156045.20" - process $proc$libresoc.v:156045$8365 + attribute \src "libresoc.v:157677.7-157677.20" + process $proc$libresoc.v:157677$8413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156067.7-156067.19" - process $proc$libresoc.v:156067$8366 + attribute \src "libresoc.v:157699.7-157699.19" + process $proc$libresoc.v:157699$8414 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156088.3-156089.27" - process $proc$libresoc.v:156088$8361 + attribute \src "libresoc.v:157720.3-157721.27" + process $proc$libresoc.v:157720$8409 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156090.3-156098.6" - process $proc$libresoc.v:156090$8362 + attribute \src "libresoc.v:157722.3-157730.6" + process $proc$libresoc.v:157722$8410 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8363 $1\q_int$next[0:0]$8364 - attribute \src "libresoc.v:156091.5-156091.29" + assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 + attribute \src "libresoc.v:157723.5-157723.29" switch \initial - attribute \src "libresoc.v:156091.9-156091.17" + attribute \src "libresoc.v:157723.9-157723.17" case 1'1 case end @@ -325843,56 +328340,56 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8364 1'0 + assign $1\q_int$next[0:0]$8412 1'0 case - assign $1\q_int$next[0:0]$8364 \$5 + assign $1\q_int$next[0:0]$8412 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8363 + update \q_int$next $0\q_int$next[0:0]$8411 end - connect \$9 $and$libresoc.v:156080$8353_Y - connect \$11 $or$libresoc.v:156081$8354_Y - connect \$13 $not$libresoc.v:156082$8355_Y - connect \$15 $or$libresoc.v:156083$8356_Y - connect \$1 $not$libresoc.v:156084$8357_Y - connect \$3 $and$libresoc.v:156085$8358_Y - connect \$5 $or$libresoc.v:156086$8359_Y - connect \$7 $not$libresoc.v:156087$8360_Y + connect \$9 $and$libresoc.v:157712$8401_Y + connect \$11 $or$libresoc.v:157713$8402_Y + connect \$13 $not$libresoc.v:157714$8403_Y + connect \$15 $or$libresoc.v:157715$8404_Y + connect \$1 $not$libresoc.v:157716$8405_Y + connect \$3 $and$libresoc.v:157717$8406_Y + connect \$5 $or$libresoc.v:157718$8407_Y + connect \$7 $not$libresoc.v:157719$8408_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156106.1-156164.10" +attribute \src "libresoc.v:157738.1-157796.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:156107.7-156107.20" + attribute \src "libresoc.v:157739.7-157739.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156152.3-156160.6" - wire $0\q_int$next[0:0]$8377 - attribute \src "libresoc.v:156150.3-156151.27" + attribute \src "libresoc.v:157784.3-157792.6" + wire $0\q_int$next[0:0]$8425 + attribute \src "libresoc.v:157782.3-157783.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156152.3-156160.6" - wire $1\q_int$next[0:0]$8378 - attribute \src "libresoc.v:156129.7-156129.19" + attribute \src "libresoc.v:157784.3-157792.6" + wire $1\q_int$next[0:0]$8426 + attribute \src "libresoc.v:157761.7-157761.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156142.17-156142.96" - wire $and$libresoc.v:156142$8367_Y - attribute \src "libresoc.v:156147.17-156147.96" - wire $and$libresoc.v:156147$8372_Y - attribute \src "libresoc.v:156144.18-156144.93" - wire $not$libresoc.v:156144$8369_Y - attribute \src "libresoc.v:156146.17-156146.92" - wire $not$libresoc.v:156146$8371_Y - attribute \src "libresoc.v:156149.17-156149.92" - wire $not$libresoc.v:156149$8374_Y - attribute \src "libresoc.v:156143.18-156143.98" - wire $or$libresoc.v:156143$8368_Y - attribute \src "libresoc.v:156145.18-156145.99" - wire $or$libresoc.v:156145$8370_Y - attribute \src "libresoc.v:156148.17-156148.97" - wire $or$libresoc.v:156148$8373_Y + attribute \src "libresoc.v:157774.17-157774.96" + wire $and$libresoc.v:157774$8415_Y + attribute \src "libresoc.v:157779.17-157779.96" + wire $and$libresoc.v:157779$8420_Y + attribute \src "libresoc.v:157776.18-157776.93" + wire $not$libresoc.v:157776$8417_Y + attribute \src "libresoc.v:157778.17-157778.92" + wire $not$libresoc.v:157778$8419_Y + attribute \src "libresoc.v:157781.17-157781.92" + wire $not$libresoc.v:157781$8422_Y + attribute \src "libresoc.v:157775.18-157775.98" + wire $or$libresoc.v:157775$8416_Y + attribute \src "libresoc.v:157777.18-157777.99" + wire $or$libresoc.v:157777$8418_Y + attribute \src "libresoc.v:157780.17-157780.97" + wire $or$libresoc.v:157780$8421_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325909,11 +328406,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156107.7-156107.15" + attribute \src "libresoc.v:157739.7-157739.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325930,7 +328427,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156142$8367 + cell $and $and$libresoc.v:157774$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325938,10 +328435,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156142$8367_Y + connect \Y $and$libresoc.v:157774$8415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156147$8372 + cell $and $and$libresoc.v:157779$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325949,34 +328446,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156147$8372_Y + connect \Y $and$libresoc.v:157779$8420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156144$8369 + cell $not $not$libresoc.v:157776$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156144$8369_Y + connect \Y $not$libresoc.v:157776$8417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156146$8371 + cell $not $not$libresoc.v:157778$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156146$8371_Y + connect \Y $not$libresoc.v:157778$8419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156149$8374 + cell $not $not$libresoc.v:157781$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156149$8374_Y + connect \Y $not$libresoc.v:157781$8422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156143$8368 + cell $or $or$libresoc.v:157775$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325984,10 +328481,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156143$8368_Y + connect \Y $or$libresoc.v:157775$8416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156145$8370 + cell $or $or$libresoc.v:157777$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325995,10 +328492,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156145$8370_Y + connect \Y $or$libresoc.v:157777$8418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156148$8373 + cell $or $or$libresoc.v:157780$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326006,39 +328503,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156148$8373_Y + connect \Y $or$libresoc.v:157780$8421_Y end - attribute \src "libresoc.v:156107.7-156107.20" - process $proc$libresoc.v:156107$8379 + attribute \src "libresoc.v:157739.7-157739.20" + process $proc$libresoc.v:157739$8427 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156129.7-156129.19" - process $proc$libresoc.v:156129$8380 + attribute \src "libresoc.v:157761.7-157761.19" + process $proc$libresoc.v:157761$8428 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156150.3-156151.27" - process $proc$libresoc.v:156150$8375 + attribute \src "libresoc.v:157782.3-157783.27" + process $proc$libresoc.v:157782$8423 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156152.3-156160.6" - process $proc$libresoc.v:156152$8376 + attribute \src "libresoc.v:157784.3-157792.6" + process $proc$libresoc.v:157784$8424 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8377 $1\q_int$next[0:0]$8378 - attribute \src "libresoc.v:156153.5-156153.29" + assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 + attribute \src "libresoc.v:157785.5-157785.29" switch \initial - attribute \src "libresoc.v:156153.9-156153.17" + attribute \src "libresoc.v:157785.9-157785.17" case 1'1 case end @@ -326047,56 +328544,56 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8378 1'0 + assign $1\q_int$next[0:0]$8426 1'0 case - assign $1\q_int$next[0:0]$8378 \$5 + assign $1\q_int$next[0:0]$8426 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8377 + update \q_int$next $0\q_int$next[0:0]$8425 end - connect \$9 $and$libresoc.v:156142$8367_Y - connect \$11 $or$libresoc.v:156143$8368_Y - connect \$13 $not$libresoc.v:156144$8369_Y - connect \$15 $or$libresoc.v:156145$8370_Y - connect \$1 $not$libresoc.v:156146$8371_Y - connect \$3 $and$libresoc.v:156147$8372_Y - connect \$5 $or$libresoc.v:156148$8373_Y - connect \$7 $not$libresoc.v:156149$8374_Y + connect \$9 $and$libresoc.v:157774$8415_Y + connect \$11 $or$libresoc.v:157775$8416_Y + connect \$13 $not$libresoc.v:157776$8417_Y + connect \$15 $or$libresoc.v:157777$8418_Y + connect \$1 $not$libresoc.v:157778$8419_Y + connect \$3 $and$libresoc.v:157779$8420_Y + connect \$5 $or$libresoc.v:157780$8421_Y + connect \$7 $not$libresoc.v:157781$8422_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156168.1-156226.10" +attribute \src "libresoc.v:157800.1-157858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:156169.7-156169.20" + attribute \src "libresoc.v:157801.7-157801.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156214.3-156222.6" - wire $0\q_int$next[0:0]$8391 - attribute \src "libresoc.v:156212.3-156213.27" + attribute \src "libresoc.v:157846.3-157854.6" + wire $0\q_int$next[0:0]$8439 + attribute \src "libresoc.v:157844.3-157845.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156214.3-156222.6" - wire $1\q_int$next[0:0]$8392 - attribute \src "libresoc.v:156191.7-156191.19" + attribute \src "libresoc.v:157846.3-157854.6" + wire $1\q_int$next[0:0]$8440 + attribute \src "libresoc.v:157823.7-157823.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156204.17-156204.96" - wire $and$libresoc.v:156204$8381_Y - attribute \src "libresoc.v:156209.17-156209.96" - wire $and$libresoc.v:156209$8386_Y - attribute \src "libresoc.v:156206.18-156206.93" - wire $not$libresoc.v:156206$8383_Y - attribute \src "libresoc.v:156208.17-156208.92" - wire $not$libresoc.v:156208$8385_Y - attribute \src "libresoc.v:156211.17-156211.92" - wire $not$libresoc.v:156211$8388_Y - attribute \src "libresoc.v:156205.18-156205.98" - wire $or$libresoc.v:156205$8382_Y - attribute \src "libresoc.v:156207.18-156207.99" - wire $or$libresoc.v:156207$8384_Y - attribute \src "libresoc.v:156210.17-156210.97" - wire $or$libresoc.v:156210$8387_Y + attribute \src "libresoc.v:157836.17-157836.96" + wire $and$libresoc.v:157836$8429_Y + attribute \src "libresoc.v:157841.17-157841.96" + wire $and$libresoc.v:157841$8434_Y + attribute \src "libresoc.v:157838.18-157838.93" + wire $not$libresoc.v:157838$8431_Y + attribute \src "libresoc.v:157840.17-157840.92" + wire $not$libresoc.v:157840$8433_Y + attribute \src "libresoc.v:157843.17-157843.92" + wire $not$libresoc.v:157843$8436_Y + attribute \src "libresoc.v:157837.18-157837.98" + wire $or$libresoc.v:157837$8430_Y + attribute \src "libresoc.v:157839.18-157839.99" + wire $or$libresoc.v:157839$8432_Y + attribute \src "libresoc.v:157842.17-157842.97" + wire $or$libresoc.v:157842$8435_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -326113,11 +328610,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156169.7-156169.15" + attribute \src "libresoc.v:157801.7-157801.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -326134,7 +328631,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156204$8381 + cell $and $and$libresoc.v:157836$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326142,10 +328639,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156204$8381_Y + connect \Y $and$libresoc.v:157836$8429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156209$8386 + cell $and $and$libresoc.v:157841$8434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326153,34 +328650,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156209$8386_Y + connect \Y $and$libresoc.v:157841$8434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156206$8383 + cell $not $not$libresoc.v:157838$8431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156206$8383_Y + connect \Y $not$libresoc.v:157838$8431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156208$8385 + cell $not $not$libresoc.v:157840$8433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156208$8385_Y + connect \Y $not$libresoc.v:157840$8433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156211$8388 + cell $not $not$libresoc.v:157843$8436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156211$8388_Y + connect \Y $not$libresoc.v:157843$8436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156205$8382 + cell $or $or$libresoc.v:157837$8430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326188,10 +328685,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156205$8382_Y + connect \Y $or$libresoc.v:157837$8430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156207$8384 + cell $or $or$libresoc.v:157839$8432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326199,10 +328696,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156207$8384_Y + connect \Y $or$libresoc.v:157839$8432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156210$8387 + cell $or $or$libresoc.v:157842$8435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326210,39 +328707,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156210$8387_Y + connect \Y $or$libresoc.v:157842$8435_Y end - attribute \src "libresoc.v:156169.7-156169.20" - process $proc$libresoc.v:156169$8393 + attribute \src "libresoc.v:157801.7-157801.20" + process $proc$libresoc.v:157801$8441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156191.7-156191.19" - process $proc$libresoc.v:156191$8394 + attribute \src "libresoc.v:157823.7-157823.19" + process $proc$libresoc.v:157823$8442 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156212.3-156213.27" - process $proc$libresoc.v:156212$8389 + attribute \src "libresoc.v:157844.3-157845.27" + process $proc$libresoc.v:157844$8437 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156214.3-156222.6" - process $proc$libresoc.v:156214$8390 + attribute \src "libresoc.v:157846.3-157854.6" + process $proc$libresoc.v:157846$8438 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8391 $1\q_int$next[0:0]$8392 - attribute \src "libresoc.v:156215.5-156215.29" + assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 + attribute \src "libresoc.v:157847.5-157847.29" switch \initial - attribute \src "libresoc.v:156215.9-156215.17" + attribute \src "libresoc.v:157847.9-157847.17" case 1'1 case end @@ -326251,56 +328748,56 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8392 1'0 + assign $1\q_int$next[0:0]$8440 1'0 case - assign $1\q_int$next[0:0]$8392 \$5 + assign $1\q_int$next[0:0]$8440 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8391 + update \q_int$next $0\q_int$next[0:0]$8439 end - connect \$9 $and$libresoc.v:156204$8381_Y - connect \$11 $or$libresoc.v:156205$8382_Y - connect \$13 $not$libresoc.v:156206$8383_Y - connect \$15 $or$libresoc.v:156207$8384_Y - connect \$1 $not$libresoc.v:156208$8385_Y - connect \$3 $and$libresoc.v:156209$8386_Y - connect \$5 $or$libresoc.v:156210$8387_Y - connect \$7 $not$libresoc.v:156211$8388_Y + connect \$9 $and$libresoc.v:157836$8429_Y + connect \$11 $or$libresoc.v:157837$8430_Y + connect \$13 $not$libresoc.v:157838$8431_Y + connect \$15 $or$libresoc.v:157839$8432_Y + connect \$1 $not$libresoc.v:157840$8433_Y + connect \$3 $and$libresoc.v:157841$8434_Y + connect \$5 $or$libresoc.v:157842$8435_Y + connect \$7 $not$libresoc.v:157843$8436_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156230.1-156288.10" +attribute \src "libresoc.v:157862.1-157920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:156231.7-156231.20" + attribute \src "libresoc.v:157863.7-157863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156276.3-156284.6" - wire $0\q_int$next[0:0]$8405 - attribute \src "libresoc.v:156274.3-156275.27" + attribute \src "libresoc.v:157908.3-157916.6" + wire $0\q_int$next[0:0]$8453 + attribute \src "libresoc.v:157906.3-157907.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156276.3-156284.6" - wire $1\q_int$next[0:0]$8406 - attribute \src "libresoc.v:156253.7-156253.19" + attribute \src "libresoc.v:157908.3-157916.6" + wire $1\q_int$next[0:0]$8454 + attribute \src "libresoc.v:157885.7-157885.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156266.17-156266.96" - wire $and$libresoc.v:156266$8395_Y - attribute \src "libresoc.v:156271.17-156271.96" - wire $and$libresoc.v:156271$8400_Y - attribute \src "libresoc.v:156268.18-156268.93" - wire $not$libresoc.v:156268$8397_Y - attribute \src "libresoc.v:156270.17-156270.92" - wire $not$libresoc.v:156270$8399_Y - attribute \src "libresoc.v:156273.17-156273.92" - wire $not$libresoc.v:156273$8402_Y - attribute \src "libresoc.v:156267.18-156267.98" - wire $or$libresoc.v:156267$8396_Y - attribute \src "libresoc.v:156269.18-156269.99" - wire $or$libresoc.v:156269$8398_Y - attribute \src "libresoc.v:156272.17-156272.97" - wire $or$libresoc.v:156272$8401_Y + attribute \src "libresoc.v:157898.17-157898.96" + wire $and$libresoc.v:157898$8443_Y + attribute \src "libresoc.v:157903.17-157903.96" + wire $and$libresoc.v:157903$8448_Y + attribute \src "libresoc.v:157900.18-157900.93" + wire $not$libresoc.v:157900$8445_Y + attribute \src "libresoc.v:157902.17-157902.92" + wire $not$libresoc.v:157902$8447_Y + attribute \src "libresoc.v:157905.17-157905.92" + wire $not$libresoc.v:157905$8450_Y + attribute \src "libresoc.v:157899.18-157899.98" + wire $or$libresoc.v:157899$8444_Y + attribute \src "libresoc.v:157901.18-157901.99" + wire $or$libresoc.v:157901$8446_Y + attribute \src "libresoc.v:157904.17-157904.97" + wire $or$libresoc.v:157904$8449_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -326317,11 +328814,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156231.7-156231.15" + attribute \src "libresoc.v:157863.7-157863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -326338,7 +328835,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156266$8395 + cell $and $and$libresoc.v:157898$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326346,10 +328843,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156266$8395_Y + connect \Y $and$libresoc.v:157898$8443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156271$8400 + cell $and $and$libresoc.v:157903$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326357,34 +328854,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156271$8400_Y + connect \Y $and$libresoc.v:157903$8448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156268$8397 + cell $not $not$libresoc.v:157900$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156268$8397_Y + connect \Y $not$libresoc.v:157900$8445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156270$8399 + cell $not $not$libresoc.v:157902$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156270$8399_Y + connect \Y $not$libresoc.v:157902$8447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156273$8402 + cell $not $not$libresoc.v:157905$8450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156273$8402_Y + connect \Y $not$libresoc.v:157905$8450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156267$8396 + cell $or $or$libresoc.v:157899$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326392,10 +328889,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156267$8396_Y + connect \Y $or$libresoc.v:157899$8444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156269$8398 + cell $or $or$libresoc.v:157901$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326403,10 +328900,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156269$8398_Y + connect \Y $or$libresoc.v:157901$8446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156272$8401 + cell $or $or$libresoc.v:157904$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326414,39 +328911,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156272$8401_Y + connect \Y $or$libresoc.v:157904$8449_Y end - attribute \src "libresoc.v:156231.7-156231.20" - process $proc$libresoc.v:156231$8407 + attribute \src "libresoc.v:157863.7-157863.20" + process $proc$libresoc.v:157863$8455 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156253.7-156253.19" - process $proc$libresoc.v:156253$8408 + attribute \src "libresoc.v:157885.7-157885.19" + process $proc$libresoc.v:157885$8456 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156274.3-156275.27" - process $proc$libresoc.v:156274$8403 + attribute \src "libresoc.v:157906.3-157907.27" + process $proc$libresoc.v:157906$8451 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156276.3-156284.6" - process $proc$libresoc.v:156276$8404 + attribute \src "libresoc.v:157908.3-157916.6" + process $proc$libresoc.v:157908$8452 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8405 $1\q_int$next[0:0]$8406 - attribute \src "libresoc.v:156277.5-156277.29" + assign $0\q_int$next[0:0]$8453 $1\q_int$next[0:0]$8454 + attribute \src "libresoc.v:157909.5-157909.29" switch \initial - attribute \src "libresoc.v:156277.9-156277.17" + attribute \src "libresoc.v:157909.9-157909.17" case 1'1 case end @@ -326455,90 +328952,90 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8406 1'0 + assign $1\q_int$next[0:0]$8454 1'0 case - assign $1\q_int$next[0:0]$8406 \$5 + assign $1\q_int$next[0:0]$8454 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8405 + update \q_int$next $0\q_int$next[0:0]$8453 end - connect \$9 $and$libresoc.v:156266$8395_Y - connect \$11 $or$libresoc.v:156267$8396_Y - connect \$13 $not$libresoc.v:156268$8397_Y - connect \$15 $or$libresoc.v:156269$8398_Y - connect \$1 $not$libresoc.v:156270$8399_Y - connect \$3 $and$libresoc.v:156271$8400_Y - connect \$5 $or$libresoc.v:156272$8401_Y - connect \$7 $not$libresoc.v:156273$8402_Y + connect \$9 $and$libresoc.v:157898$8443_Y + connect \$11 $or$libresoc.v:157899$8444_Y + connect \$13 $not$libresoc.v:157900$8445_Y + connect \$15 $or$libresoc.v:157901$8446_Y + connect \$1 $not$libresoc.v:157902$8447_Y + connect \$3 $and$libresoc.v:157903$8448_Y + connect \$5 $or$libresoc.v:157904$8449_Y + connect \$7 $not$libresoc.v:157905$8450_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156292.1-156750.10" +attribute \src "libresoc.v:157924.1-158382.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:156669.3-156680.6" + attribute \src "libresoc.v:158301.3-158312.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:156293.7-156293.20" + attribute \src "libresoc.v:157925.7-157925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156681.3-156692.6" - wire width 65 $0\o$28[64:0]$8427 - attribute \src "libresoc.v:156657.3-156668.6" + attribute \src "libresoc.v:158313.3-158324.6" + wire width 65 $0\o$28[64:0]$8475 + attribute \src "libresoc.v:158289.3-158300.6" wire $0\so[0:0] - attribute \src "libresoc.v:156713.3-156722.6" - wire width 2 $0\xer_ov$24[1:0]$8434 - attribute \src "libresoc.v:156723.3-156732.6" + attribute \src "libresoc.v:158345.3-158354.6" + wire width 2 $0\xer_ov$24[1:0]$8482 + attribute \src "libresoc.v:158355.3-158364.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156693.3-156702.6" - wire $0\xer_so$25[0:0]$8430 - attribute \src "libresoc.v:156703.3-156712.6" + attribute \src "libresoc.v:158325.3-158334.6" + wire $0\xer_so$25[0:0]$8478 + attribute \src "libresoc.v:158335.3-158344.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156669.3-156680.6" + attribute \src "libresoc.v:158301.3-158312.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:156681.3-156692.6" - wire width 65 $1\o$28[64:0]$8428 - attribute \src "libresoc.v:156657.3-156668.6" + attribute \src "libresoc.v:158313.3-158324.6" + wire width 65 $1\o$28[64:0]$8476 + attribute \src "libresoc.v:158289.3-158300.6" wire $1\so[0:0] - attribute \src "libresoc.v:156713.3-156722.6" - wire width 2 $1\xer_ov$24[1:0]$8435 - attribute \src "libresoc.v:156723.3-156732.6" + attribute \src "libresoc.v:158345.3-158354.6" + wire width 2 $1\xer_ov$24[1:0]$8483 + attribute \src "libresoc.v:158355.3-158364.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156693.3-156702.6" - wire $1\xer_so$25[0:0]$8431 - attribute \src "libresoc.v:156703.3-156712.6" + attribute \src "libresoc.v:158325.3-158334.6" + wire $1\xer_so$25[0:0]$8479 + attribute \src "libresoc.v:158335.3-158344.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156644.18-156644.128" - wire $and$libresoc.v:156644$8409_Y - attribute \src "libresoc.v:156652.18-156652.112" - wire $and$libresoc.v:156652$8419_Y - attribute \src "libresoc.v:156655.18-156655.125" - wire $and$libresoc.v:156655$8422_Y - attribute \src "libresoc.v:156648.18-156648.123" - wire $eq$libresoc.v:156648$8415_Y - attribute \src "libresoc.v:156649.18-156649.123" - wire $eq$libresoc.v:156649$8416_Y - attribute \src "libresoc.v:156646.18-156646.103" - wire width 65 $extend$libresoc.v:156646$8411_Y - attribute \src "libresoc.v:156647.18-156647.101" - wire width 65 $extend$libresoc.v:156647$8413_Y - attribute \src "libresoc.v:156645.18-156645.100" - wire width 64 $not$libresoc.v:156645$8410_Y - attribute \src "libresoc.v:156651.18-156651.107" - wire $not$libresoc.v:156651$8418_Y - attribute \src "libresoc.v:156654.18-156654.107" - wire $not$libresoc.v:156654$8421_Y - attribute \src "libresoc.v:156653.18-156653.115" - wire $or$libresoc.v:156653$8420_Y - attribute \src "libresoc.v:156656.18-156656.112" - wire $or$libresoc.v:156656$8423_Y - attribute \src "libresoc.v:156646.18-156646.103" - wire width 65 $pos$libresoc.v:156646$8412_Y - attribute \src "libresoc.v:156647.18-156647.101" - wire width 65 $pos$libresoc.v:156647$8414_Y - attribute \src "libresoc.v:156650.18-156650.105" - wire $reduce_or$libresoc.v:156650$8417_Y + attribute \src "libresoc.v:158276.18-158276.128" + wire $and$libresoc.v:158276$8457_Y + attribute \src "libresoc.v:158284.18-158284.112" + wire $and$libresoc.v:158284$8467_Y + attribute \src "libresoc.v:158287.18-158287.125" + wire $and$libresoc.v:158287$8470_Y + attribute \src "libresoc.v:158280.18-158280.123" + wire $eq$libresoc.v:158280$8463_Y + attribute \src "libresoc.v:158281.18-158281.123" + wire $eq$libresoc.v:158281$8464_Y + attribute \src "libresoc.v:158278.18-158278.103" + wire width 65 $extend$libresoc.v:158278$8459_Y + attribute \src "libresoc.v:158279.18-158279.101" + wire width 65 $extend$libresoc.v:158279$8461_Y + attribute \src "libresoc.v:158277.18-158277.100" + wire width 64 $not$libresoc.v:158277$8458_Y + attribute \src "libresoc.v:158283.18-158283.107" + wire $not$libresoc.v:158283$8466_Y + attribute \src "libresoc.v:158286.18-158286.107" + wire $not$libresoc.v:158286$8469_Y + attribute \src "libresoc.v:158285.18-158285.115" + wire $or$libresoc.v:158285$8468_Y + attribute \src "libresoc.v:158288.18-158288.112" + wire $or$libresoc.v:158288$8471_Y + attribute \src "libresoc.v:158278.18-158278.103" + wire width 65 $pos$libresoc.v:158278$8460_Y + attribute \src "libresoc.v:158279.18-158279.101" + wire width 65 $pos$libresoc.v:158279$8462_Y + attribute \src "libresoc.v:158282.18-158282.105" + wire $reduce_or$libresoc.v:158282$8465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -326833,7 +329330,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:156293.7-156293.15" + attribute \src "libresoc.v:157925.7-157925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -326888,7 +329385,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:156644$8409 + cell $and $and$libresoc.v:158276$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326896,10 +329393,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:156644$8409_Y + connect \Y $and$libresoc.v:158276$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:156652$8419 + cell $and $and$libresoc.v:158284$8467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326907,10 +329404,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:156652$8419_Y + connect \Y $and$libresoc.v:158284$8467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:156655$8422 + cell $and $and$libresoc.v:158287$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326918,10 +329415,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:156655$8422_Y + connect \Y $and$libresoc.v:158287$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:156648$8415 + cell $eq $eq$libresoc.v:158280$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326929,10 +329426,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:156648$8415_Y + connect \Y $eq$libresoc.v:158280$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:156649$8416 + cell $eq $eq$libresoc.v:158281$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326940,50 +329437,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:156649$8416_Y + connect \Y $eq$libresoc.v:158281$8464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:156646$8411 + cell $pos $extend$libresoc.v:158278$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:156646$8411_Y + connect \Y $extend$libresoc.v:158278$8459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:156647$8413 + cell $pos $extend$libresoc.v:158279$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:156647$8413_Y + connect \Y $extend$libresoc.v:158279$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:156645$8410 + cell $not $not$libresoc.v:158277$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:156645$8410_Y + connect \Y $not$libresoc.v:158277$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:156651$8418 + cell $not $not$libresoc.v:158283$8466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:156651$8418_Y + connect \Y $not$libresoc.v:158283$8466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:156654$8421 + cell $not $not$libresoc.v:158286$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:156654$8421_Y + connect \Y $not$libresoc.v:158286$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:156653$8420 + cell $or $or$libresoc.v:158285$8468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326991,10 +329488,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:156653$8420_Y + connect \Y $or$libresoc.v:158285$8468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:156656$8423 + cell $or $or$libresoc.v:158288$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327002,47 +329499,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:156656$8423_Y + connect \Y $or$libresoc.v:158288$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:156646$8412 + cell $pos $pos$libresoc.v:158278$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156646$8411_Y - connect \Y $pos$libresoc.v:156646$8412_Y + connect \A $extend$libresoc.v:158278$8459_Y + connect \Y $pos$libresoc.v:158278$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:156647$8414 + cell $pos $pos$libresoc.v:158279$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156647$8413_Y - connect \Y $pos$libresoc.v:156647$8414_Y + connect \A $extend$libresoc.v:158279$8461_Y + connect \Y $pos$libresoc.v:158279$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:156650$8417 + cell $reduce_or $reduce_or$libresoc.v:158282$8465 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:156650$8417_Y + connect \Y $reduce_or$libresoc.v:158282$8465_Y end - attribute \src "libresoc.v:156293.7-156293.20" - process $proc$libresoc.v:156293$8437 + attribute \src "libresoc.v:157925.7-157925.20" + process $proc$libresoc.v:157925$8485 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156657.3-156668.6" - process $proc$libresoc.v:156657$8424 + attribute \src "libresoc.v:158289.3-158300.6" + process $proc$libresoc.v:158289$8472 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:156658.5-156658.29" + attribute \src "libresoc.v:158290.5-158290.29" switch \initial - attribute \src "libresoc.v:156658.9-156658.17" + attribute \src "libresoc.v:158290.9-158290.17" case 1'1 case end @@ -327060,13 +329557,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:156669.3-156680.6" - process $proc$libresoc.v:156669$8425 + attribute \src "libresoc.v:158301.3-158312.6" + process $proc$libresoc.v:158301$8473 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:156670.5-156670.29" + attribute \src "libresoc.v:158302.5-158302.29" switch \initial - attribute \src "libresoc.v:156670.9-156670.17" + attribute \src "libresoc.v:158302.9-158302.17" case 1'1 case end @@ -327084,13 +329581,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:156681.3-156692.6" - process $proc$libresoc.v:156681$8426 + attribute \src "libresoc.v:158313.3-158324.6" + process $proc$libresoc.v:158313$8474 assign { } { } - assign $0\o$28[64:0]$8427 $1\o$28[64:0]$8428 - attribute \src "libresoc.v:156682.5-156682.29" + assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 + attribute \src "libresoc.v:158314.5-158314.29" switch \initial - attribute \src "libresoc.v:156682.9-156682.17" + attribute \src "libresoc.v:158314.9-158314.17" case 1'1 case end @@ -327099,23 +329596,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8428 \$29 + assign $1\o$28[64:0]$8476 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8428 \$33 + assign $1\o$28[64:0]$8476 \$33 end sync always - update \o$28 $0\o$28[64:0]$8427 + update \o$28 $0\o$28[64:0]$8475 end - attribute \src "libresoc.v:156693.3-156702.6" - process $proc$libresoc.v:156693$8429 + attribute \src "libresoc.v:158325.3-158334.6" + process $proc$libresoc.v:158325$8477 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8430 $1\xer_so$25[0:0]$8431 - attribute \src "libresoc.v:156694.5-156694.29" + assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 + attribute \src "libresoc.v:158326.5-158326.29" switch \initial - attribute \src "libresoc.v:156694.9-156694.17" + attribute \src "libresoc.v:158326.9-158326.17" case 1'1 case end @@ -327124,21 +329621,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8431 \$52 + assign $1\xer_so$25[0:0]$8479 \$52 case - assign $1\xer_so$25[0:0]$8431 1'0 + assign $1\xer_so$25[0:0]$8479 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8430 + update \xer_so$25 $0\xer_so$25[0:0]$8478 end - attribute \src "libresoc.v:156703.3-156712.6" - process $proc$libresoc.v:156703$8432 + attribute \src "libresoc.v:158335.3-158344.6" + process $proc$libresoc.v:158335$8480 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156704.5-156704.29" + attribute \src "libresoc.v:158336.5-158336.29" switch \initial - attribute \src "libresoc.v:156704.9-156704.17" + attribute \src "libresoc.v:158336.9-158336.17" case 1'1 case end @@ -327154,14 +329651,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156713.3-156722.6" - process $proc$libresoc.v:156713$8433 + attribute \src "libresoc.v:158345.3-158354.6" + process $proc$libresoc.v:158345$8481 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8434 $1\xer_ov$24[1:0]$8435 - attribute \src "libresoc.v:156714.5-156714.29" + assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 + attribute \src "libresoc.v:158346.5-158346.29" switch \initial - attribute \src "libresoc.v:156714.9-156714.17" + attribute \src "libresoc.v:158346.9-158346.17" case 1'1 case end @@ -327170,21 +329667,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8435 \xer_ov + assign $1\xer_ov$24[1:0]$8483 \xer_ov case - assign $1\xer_ov$24[1:0]$8435 2'00 + assign $1\xer_ov$24[1:0]$8483 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8434 + update \xer_ov$24 $0\xer_ov$24[1:0]$8482 end - attribute \src "libresoc.v:156723.3-156732.6" - process $proc$libresoc.v:156723$8436 + attribute \src "libresoc.v:158355.3-158364.6" + process $proc$libresoc.v:158355$8484 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156724.5-156724.29" + attribute \src "libresoc.v:158356.5-158356.29" switch \initial - attribute \src "libresoc.v:156724.9-156724.17" + attribute \src "libresoc.v:158356.9-158356.17" case 1'1 case end @@ -327200,19 +329697,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:156644$8409_Y - connect \$30 $not$libresoc.v:156645$8410_Y - connect \$29 $pos$libresoc.v:156646$8412_Y - connect \$33 $pos$libresoc.v:156647$8414_Y - connect \$35 $eq$libresoc.v:156648$8415_Y - connect \$37 $eq$libresoc.v:156649$8416_Y - connect \$39 $reduce_or$libresoc.v:156650$8417_Y - connect \$41 $not$libresoc.v:156651$8418_Y - connect \$43 $and$libresoc.v:156652$8419_Y - connect \$45 $or$libresoc.v:156653$8420_Y - connect \$47 $not$libresoc.v:156654$8421_Y - connect \$50 $and$libresoc.v:156655$8422_Y - connect \$52 $or$libresoc.v:156656$8423_Y + connect \$26 $and$libresoc.v:158276$8457_Y + connect \$30 $not$libresoc.v:158277$8458_Y + connect \$29 $pos$libresoc.v:158278$8460_Y + connect \$33 $pos$libresoc.v:158279$8462_Y + connect \$35 $eq$libresoc.v:158280$8463_Y + connect \$37 $eq$libresoc.v:158281$8464_Y + connect \$39 $reduce_or$libresoc.v:158282$8465_Y + connect \$41 $not$libresoc.v:158283$8466_Y + connect \$43 $and$libresoc.v:158284$8467_Y + connect \$45 $or$libresoc.v:158285$8468_Y + connect \$47 $not$libresoc.v:158286$8469_Y + connect \$50 $and$libresoc.v:158287$8470_Y + connect \$52 $or$libresoc.v:158288$8471_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -327231,61 +329728,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:156754.1-157155.10" +attribute \src "libresoc.v:158386.1-158787.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:157087.3-157098.6" + attribute \src "libresoc.v:158719.3-158730.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:156755.7-156755.20" + attribute \src "libresoc.v:158387.7-158387.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157075.3-157086.6" + attribute \src "libresoc.v:158707.3-158718.6" wire $0\so[0:0] - attribute \src "libresoc.v:157119.3-157128.6" - wire width 2 $0\xer_ov$17[1:0]$8457 - attribute \src "libresoc.v:157129.3-157138.6" + attribute \src "libresoc.v:158751.3-158760.6" + wire width 2 $0\xer_ov$17[1:0]$8505 + attribute \src "libresoc.v:158761.3-158770.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:157099.3-157108.6" - wire $0\xer_so$18[0:0]$8453 - attribute \src "libresoc.v:157109.3-157118.6" + attribute \src "libresoc.v:158731.3-158740.6" + wire $0\xer_so$18[0:0]$8501 + attribute \src "libresoc.v:158741.3-158750.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:157087.3-157098.6" + attribute \src "libresoc.v:158719.3-158730.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157075.3-157086.6" + attribute \src "libresoc.v:158707.3-158718.6" wire $1\so[0:0] - attribute \src "libresoc.v:157119.3-157128.6" - wire width 2 $1\xer_ov$17[1:0]$8458 - attribute \src "libresoc.v:157129.3-157138.6" + attribute \src "libresoc.v:158751.3-158760.6" + wire width 2 $1\xer_ov$17[1:0]$8506 + attribute \src "libresoc.v:158761.3-158770.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157099.3-157108.6" - wire $1\xer_so$18[0:0]$8454 - attribute \src "libresoc.v:157109.3-157118.6" + attribute \src "libresoc.v:158731.3-158740.6" + wire $1\xer_so$18[0:0]$8502 + attribute \src "libresoc.v:158741.3-158750.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157064.18-157064.128" - wire $and$libresoc.v:157064$8438_Y - attribute \src "libresoc.v:157070.18-157070.112" - wire $and$libresoc.v:157070$8445_Y - attribute \src "libresoc.v:157073.18-157073.125" - wire $and$libresoc.v:157073$8448_Y - attribute \src "libresoc.v:157066.18-157066.123" - wire $eq$libresoc.v:157066$8441_Y - attribute \src "libresoc.v:157067.18-157067.123" - wire $eq$libresoc.v:157067$8442_Y - attribute \src "libresoc.v:157065.18-157065.101" - wire width 65 $extend$libresoc.v:157065$8439_Y - attribute \src "libresoc.v:157069.18-157069.107" - wire $not$libresoc.v:157069$8444_Y - attribute \src "libresoc.v:157072.18-157072.107" - wire $not$libresoc.v:157072$8447_Y - attribute \src "libresoc.v:157071.18-157071.115" - wire $or$libresoc.v:157071$8446_Y - attribute \src "libresoc.v:157074.18-157074.112" - wire $or$libresoc.v:157074$8449_Y - attribute \src "libresoc.v:157065.18-157065.101" - wire width 65 $pos$libresoc.v:157065$8440_Y - attribute \src "libresoc.v:157068.18-157068.105" - wire $reduce_or$libresoc.v:157068$8443_Y + attribute \src "libresoc.v:158696.18-158696.128" + wire $and$libresoc.v:158696$8486_Y + attribute \src "libresoc.v:158702.18-158702.112" + wire $and$libresoc.v:158702$8493_Y + attribute \src "libresoc.v:158705.18-158705.125" + wire $and$libresoc.v:158705$8496_Y + attribute \src "libresoc.v:158698.18-158698.123" + wire $eq$libresoc.v:158698$8489_Y + attribute \src "libresoc.v:158699.18-158699.123" + wire $eq$libresoc.v:158699$8490_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $extend$libresoc.v:158697$8487_Y + attribute \src "libresoc.v:158701.18-158701.107" + wire $not$libresoc.v:158701$8492_Y + attribute \src "libresoc.v:158704.18-158704.107" + wire $not$libresoc.v:158704$8495_Y + attribute \src "libresoc.v:158703.18-158703.115" + wire $or$libresoc.v:158703$8494_Y + attribute \src "libresoc.v:158706.18-158706.112" + wire $or$libresoc.v:158706$8497_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $pos$libresoc.v:158697$8488_Y + attribute \src "libresoc.v:158700.18-158700.105" + wire $reduce_or$libresoc.v:158700$8491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -327316,7 +329813,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:156755.7-156755.15" + attribute \src "libresoc.v:158387.7-158387.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -327593,7 +330090,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:157064$8438 + cell $and $and$libresoc.v:158696$8486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327601,10 +330098,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:157064$8438_Y + connect \Y $and$libresoc.v:158696$8486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157070$8445 + cell $and $and$libresoc.v:158702$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327612,10 +330109,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:157070$8445_Y + connect \Y $and$libresoc.v:158702$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:157073$8448 + cell $and $and$libresoc.v:158705$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327623,10 +330120,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:157073$8448_Y + connect \Y $and$libresoc.v:158705$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157066$8441 + cell $eq $eq$libresoc.v:158698$8489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327634,10 +330131,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157066$8441_Y + connect \Y $eq$libresoc.v:158698$8489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157067$8442 + cell $eq $eq$libresoc.v:158699$8490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327645,34 +330142,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157067$8442_Y + connect \Y $eq$libresoc.v:158699$8490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157065$8439 + cell $pos $extend$libresoc.v:158697$8487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157065$8439_Y + connect \Y $extend$libresoc.v:158697$8487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157069$8444 + cell $not $not$libresoc.v:158701$8492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157069$8444_Y + connect \Y $not$libresoc.v:158701$8492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157072$8447 + cell $not $not$libresoc.v:158704$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157072$8447_Y + connect \Y $not$libresoc.v:158704$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157071$8446 + cell $or $or$libresoc.v:158703$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327680,10 +330177,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157071$8446_Y + connect \Y $or$libresoc.v:158703$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:157074$8449 + cell $or $or$libresoc.v:158706$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327691,39 +330188,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:157074$8449_Y + connect \Y $or$libresoc.v:158706$8497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157065$8440 + cell $pos $pos$libresoc.v:158697$8488 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157065$8439_Y - connect \Y $pos$libresoc.v:157065$8440_Y + connect \A $extend$libresoc.v:158697$8487_Y + connect \Y $pos$libresoc.v:158697$8488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157068$8443 + cell $reduce_or $reduce_or$libresoc.v:158700$8491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157068$8443_Y + connect \Y $reduce_or$libresoc.v:158700$8491_Y end - attribute \src "libresoc.v:156755.7-156755.20" - process $proc$libresoc.v:156755$8460 + attribute \src "libresoc.v:158387.7-158387.20" + process $proc$libresoc.v:158387$8508 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157075.3-157086.6" - process $proc$libresoc.v:157075$8450 + attribute \src "libresoc.v:158707.3-158718.6" + process $proc$libresoc.v:158707$8498 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:157076.5-157076.29" + attribute \src "libresoc.v:158708.5-158708.29" switch \initial - attribute \src "libresoc.v:157076.9-157076.17" + attribute \src "libresoc.v:158708.9-158708.17" case 1'1 case end @@ -327741,13 +330238,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:157087.3-157098.6" - process $proc$libresoc.v:157087$8451 + attribute \src "libresoc.v:158719.3-158730.6" + process $proc$libresoc.v:158719$8499 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157088.5-157088.29" + attribute \src "libresoc.v:158720.5-158720.29" switch \initial - attribute \src "libresoc.v:157088.9-157088.17" + attribute \src "libresoc.v:158720.9-158720.17" case 1'1 case end @@ -327765,14 +330262,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:157099.3-157108.6" - process $proc$libresoc.v:157099$8452 + attribute \src "libresoc.v:158731.3-158740.6" + process $proc$libresoc.v:158731$8500 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8453 $1\xer_so$18[0:0]$8454 - attribute \src "libresoc.v:157100.5-157100.29" + assign $0\xer_so$18[0:0]$8501 $1\xer_so$18[0:0]$8502 + attribute \src "libresoc.v:158732.5-158732.29" switch \initial - attribute \src "libresoc.v:157100.9-157100.17" + attribute \src "libresoc.v:158732.9-158732.17" case 1'1 case end @@ -327781,21 +330278,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8454 \$41 + assign $1\xer_so$18[0:0]$8502 \$41 case - assign $1\xer_so$18[0:0]$8454 1'0 + assign $1\xer_so$18[0:0]$8502 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8453 + update \xer_so$18 $0\xer_so$18[0:0]$8501 end - attribute \src "libresoc.v:157109.3-157118.6" - process $proc$libresoc.v:157109$8455 + attribute \src "libresoc.v:158741.3-158750.6" + process $proc$libresoc.v:158741$8503 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157110.5-157110.29" + attribute \src "libresoc.v:158742.5-158742.29" switch \initial - attribute \src "libresoc.v:157110.9-157110.17" + attribute \src "libresoc.v:158742.9-158742.17" case 1'1 case end @@ -327811,14 +330308,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:157119.3-157128.6" - process $proc$libresoc.v:157119$8456 + attribute \src "libresoc.v:158751.3-158760.6" + process $proc$libresoc.v:158751$8504 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8457 $1\xer_ov$17[1:0]$8458 - attribute \src "libresoc.v:157120.5-157120.29" + assign $0\xer_ov$17[1:0]$8505 $1\xer_ov$17[1:0]$8506 + attribute \src "libresoc.v:158752.5-158752.29" switch \initial - attribute \src "libresoc.v:157120.9-157120.17" + attribute \src "libresoc.v:158752.9-158752.17" case 1'1 case end @@ -327827,21 +330324,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8458 \xer_ov + assign $1\xer_ov$17[1:0]$8506 \xer_ov case - assign $1\xer_ov$17[1:0]$8458 2'00 + assign $1\xer_ov$17[1:0]$8506 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8457 + update \xer_ov$17 $0\xer_ov$17[1:0]$8505 end - attribute \src "libresoc.v:157129.3-157138.6" - process $proc$libresoc.v:157129$8459 + attribute \src "libresoc.v:158761.3-158770.6" + process $proc$libresoc.v:158761$8507 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157130.5-157130.29" + attribute \src "libresoc.v:158762.5-158762.29" switch \initial - attribute \src "libresoc.v:157130.9-157130.17" + attribute \src "libresoc.v:158762.9-158762.17" case 1'1 case end @@ -327857,17 +330354,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:157064$8438_Y - connect \$22 $pos$libresoc.v:157065$8440_Y - connect \$24 $eq$libresoc.v:157066$8441_Y - connect \$26 $eq$libresoc.v:157067$8442_Y - connect \$28 $reduce_or$libresoc.v:157068$8443_Y - connect \$30 $not$libresoc.v:157069$8444_Y - connect \$32 $and$libresoc.v:157070$8445_Y - connect \$34 $or$libresoc.v:157071$8446_Y - connect \$36 $not$libresoc.v:157072$8447_Y - connect \$39 $and$libresoc.v:157073$8448_Y - connect \$41 $or$libresoc.v:157074$8449_Y + connect \$19 $and$libresoc.v:158696$8486_Y + connect \$22 $pos$libresoc.v:158697$8488_Y + connect \$24 $eq$libresoc.v:158698$8489_Y + connect \$26 $eq$libresoc.v:158699$8490_Y + connect \$28 $reduce_or$libresoc.v:158700$8491_Y + connect \$30 $not$libresoc.v:158701$8492_Y + connect \$32 $and$libresoc.v:158702$8493_Y + connect \$34 $or$libresoc.v:158703$8494_Y + connect \$36 $not$libresoc.v:158704$8495_Y + connect \$39 $and$libresoc.v:158705$8496_Y + connect \$41 $or$libresoc.v:158706$8497_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -327885,35 +330382,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:157159.1-157513.10" +attribute \src "libresoc.v:158791.1-159145.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:157485.3-157496.6" + attribute \src "libresoc.v:159117.3-159128.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157160.7-157160.20" + attribute \src "libresoc.v:158792.7-158792.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157485.3-157496.6" + attribute \src "libresoc.v:159117.3-159128.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157482.18-157482.112" - wire $and$libresoc.v:157482$8467_Y - attribute \src "libresoc.v:157478.18-157478.122" - wire $eq$libresoc.v:157478$8463_Y - attribute \src "libresoc.v:157479.18-157479.122" - wire $eq$libresoc.v:157479$8464_Y - attribute \src "libresoc.v:157477.18-157477.101" - wire width 65 $extend$libresoc.v:157477$8461_Y - attribute \src "libresoc.v:157481.18-157481.107" - wire $not$libresoc.v:157481$8466_Y - attribute \src "libresoc.v:157484.18-157484.107" - wire $not$libresoc.v:157484$8469_Y - attribute \src "libresoc.v:157483.18-157483.115" - wire $or$libresoc.v:157483$8468_Y - attribute \src "libresoc.v:157477.18-157477.101" - wire width 65 $pos$libresoc.v:157477$8462_Y - attribute \src "libresoc.v:157480.18-157480.105" - wire $reduce_or$libresoc.v:157480$8465_Y + attribute \src "libresoc.v:159114.18-159114.112" + wire $and$libresoc.v:159114$8515_Y + attribute \src "libresoc.v:159110.18-159110.122" + wire $eq$libresoc.v:159110$8511_Y + attribute \src "libresoc.v:159111.18-159111.122" + wire $eq$libresoc.v:159111$8512_Y + attribute \src "libresoc.v:159109.18-159109.101" + wire width 65 $extend$libresoc.v:159109$8509_Y + attribute \src "libresoc.v:159113.18-159113.107" + wire $not$libresoc.v:159113$8514_Y + attribute \src "libresoc.v:159116.18-159116.107" + wire $not$libresoc.v:159116$8517_Y + attribute \src "libresoc.v:159115.18-159115.115" + wire $or$libresoc.v:159115$8516_Y + attribute \src "libresoc.v:159109.18-159109.101" + wire width 65 $pos$libresoc.v:159109$8510_Y + attribute \src "libresoc.v:159112.18-159112.105" + wire $reduce_or$libresoc.v:159112$8513_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -327938,7 +330435,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:157160.7-157160.15" + attribute \src "libresoc.v:158792.7-158792.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328233,7 +330730,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157482$8467 + cell $and $and$libresoc.v:159114$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328241,10 +330738,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:157482$8467_Y + connect \Y $and$libresoc.v:159114$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157478$8463 + cell $eq $eq$libresoc.v:159110$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328252,10 +330749,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157478$8463_Y + connect \Y $eq$libresoc.v:159110$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157479$8464 + cell $eq $eq$libresoc.v:159111$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328263,34 +330760,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157479$8464_Y + connect \Y $eq$libresoc.v:159111$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157477$8461 + cell $pos $extend$libresoc.v:159109$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157477$8461_Y + connect \Y $extend$libresoc.v:159109$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157481$8466 + cell $not $not$libresoc.v:159113$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157481$8466_Y + connect \Y $not$libresoc.v:159113$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157484$8469 + cell $not $not$libresoc.v:159116$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157484$8469_Y + connect \Y $not$libresoc.v:159116$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157483$8468 + cell $or $or$libresoc.v:159115$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328298,39 +330795,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157483$8468_Y + connect \Y $or$libresoc.v:159115$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157477$8462 + cell $pos $pos$libresoc.v:159109$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157477$8461_Y - connect \Y $pos$libresoc.v:157477$8462_Y + connect \A $extend$libresoc.v:159109$8509_Y + connect \Y $pos$libresoc.v:159109$8510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157480$8465 + cell $reduce_or $reduce_or$libresoc.v:159112$8513 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157480$8465_Y + connect \Y $reduce_or$libresoc.v:159112$8513_Y end - attribute \src "libresoc.v:157160.7-157160.20" - process $proc$libresoc.v:157160$8471 + attribute \src "libresoc.v:158792.7-158792.20" + process $proc$libresoc.v:158792$8519 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157485.3-157496.6" - process $proc$libresoc.v:157485$8470 + attribute \src "libresoc.v:159117.3-159128.6" + process $proc$libresoc.v:159117$8518 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157486.5-157486.29" + attribute \src "libresoc.v:159118.5-159118.29" switch \initial - attribute \src "libresoc.v:157486.9-157486.17" + attribute \src "libresoc.v:159118.9-159118.17" case 1'1 case end @@ -328348,14 +330845,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:157477$8462_Y - connect \$26 $eq$libresoc.v:157478$8463_Y - connect \$28 $eq$libresoc.v:157479$8464_Y - connect \$30 $reduce_or$libresoc.v:157480$8465_Y - connect \$32 $not$libresoc.v:157481$8466_Y - connect \$34 $and$libresoc.v:157482$8467_Y - connect \$36 $or$libresoc.v:157483$8468_Y - connect \$38 $not$libresoc.v:157484$8469_Y + connect \$24 $pos$libresoc.v:159109$8510_Y + connect \$26 $eq$libresoc.v:159110$8511_Y + connect \$28 $eq$libresoc.v:159111$8512_Y + connect \$30 $reduce_or$libresoc.v:159112$8513_Y + connect \$32 $not$libresoc.v:159113$8514_Y + connect \$34 $and$libresoc.v:159114$8515_Y + connect \$36 $or$libresoc.v:159115$8516_Y + connect \$38 $not$libresoc.v:159116$8517_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -328373,45 +330870,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:157517.1-157884.10" +attribute \src "libresoc.v:159149.1-159516.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:157859.3-157870.6" + attribute \src "libresoc.v:159491.3-159502.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157518.7-157518.20" + attribute \src "libresoc.v:159150.7-159150.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157847.3-157858.6" - wire width 65 $0\o$23[64:0]$8485 - attribute \src "libresoc.v:157859.3-157870.6" + attribute \src "libresoc.v:159479.3-159490.6" + wire width 65 $0\o$23[64:0]$8533 + attribute \src "libresoc.v:159491.3-159502.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157847.3-157858.6" - wire width 65 $1\o$23[64:0]$8486 - attribute \src "libresoc.v:157844.18-157844.112" - wire $and$libresoc.v:157844$8481_Y - attribute \src "libresoc.v:157840.18-157840.127" - wire $eq$libresoc.v:157840$8477_Y - attribute \src "libresoc.v:157841.18-157841.127" - wire $eq$libresoc.v:157841$8478_Y - attribute \src "libresoc.v:157838.18-157838.103" - wire width 65 $extend$libresoc.v:157838$8473_Y - attribute \src "libresoc.v:157839.18-157839.101" - wire width 65 $extend$libresoc.v:157839$8475_Y - attribute \src "libresoc.v:157837.18-157837.100" - wire width 64 $not$libresoc.v:157837$8472_Y - attribute \src "libresoc.v:157843.18-157843.107" - wire $not$libresoc.v:157843$8480_Y - attribute \src "libresoc.v:157846.18-157846.107" - wire $not$libresoc.v:157846$8483_Y - attribute \src "libresoc.v:157845.18-157845.115" - wire $or$libresoc.v:157845$8482_Y - attribute \src "libresoc.v:157838.18-157838.103" - wire width 65 $pos$libresoc.v:157838$8474_Y - attribute \src "libresoc.v:157839.18-157839.101" - wire width 65 $pos$libresoc.v:157839$8476_Y - attribute \src "libresoc.v:157842.18-157842.105" - wire $reduce_or$libresoc.v:157842$8479_Y + attribute \src "libresoc.v:159479.3-159490.6" + wire width 65 $1\o$23[64:0]$8534 + attribute \src "libresoc.v:159476.18-159476.112" + wire $and$libresoc.v:159476$8529_Y + attribute \src "libresoc.v:159472.18-159472.127" + wire $eq$libresoc.v:159472$8525_Y + attribute \src "libresoc.v:159473.18-159473.127" + wire $eq$libresoc.v:159473$8526_Y + attribute \src "libresoc.v:159470.18-159470.103" + wire width 65 $extend$libresoc.v:159470$8521_Y + attribute \src "libresoc.v:159471.18-159471.101" + wire width 65 $extend$libresoc.v:159471$8523_Y + attribute \src "libresoc.v:159469.18-159469.100" + wire width 64 $not$libresoc.v:159469$8520_Y + attribute \src "libresoc.v:159475.18-159475.107" + wire $not$libresoc.v:159475$8528_Y + attribute \src "libresoc.v:159478.18-159478.107" + wire $not$libresoc.v:159478$8531_Y + attribute \src "libresoc.v:159477.18-159477.115" + wire $or$libresoc.v:159477$8530_Y + attribute \src "libresoc.v:159470.18-159470.103" + wire width 65 $pos$libresoc.v:159470$8522_Y + attribute \src "libresoc.v:159471.18-159471.101" + wire width 65 $pos$libresoc.v:159471$8524_Y + attribute \src "libresoc.v:159474.18-159474.105" + wire $reduce_or$libresoc.v:159474$8527_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -328440,7 +330937,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:157518.7-157518.15" + attribute \src "libresoc.v:159150.7-159150.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328733,7 +331230,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157844$8481 + cell $and $and$libresoc.v:159476$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328741,10 +331238,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:157844$8481_Y + connect \Y $and$libresoc.v:159476$8529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157840$8477 + cell $eq $eq$libresoc.v:159472$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328752,10 +331249,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157840$8477_Y + connect \Y $eq$libresoc.v:159472$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157841$8478 + cell $eq $eq$libresoc.v:159473$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328763,50 +331260,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157841$8478_Y + connect \Y $eq$libresoc.v:159473$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:157838$8473 + cell $pos $extend$libresoc.v:159470$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:157838$8473_Y + connect \Y $extend$libresoc.v:159470$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157839$8475 + cell $pos $extend$libresoc.v:159471$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157839$8475_Y + connect \Y $extend$libresoc.v:159471$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:157837$8472 + cell $not $not$libresoc.v:159469$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:157837$8472_Y + connect \Y $not$libresoc.v:159469$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157843$8480 + cell $not $not$libresoc.v:159475$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157843$8480_Y + connect \Y $not$libresoc.v:159475$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157846$8483 + cell $not $not$libresoc.v:159478$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157846$8483_Y + connect \Y $not$libresoc.v:159478$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157845$8482 + cell $or $or$libresoc.v:159477$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328814,47 +331311,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157845$8482_Y + connect \Y $or$libresoc.v:159477$8530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:157838$8474 + cell $pos $pos$libresoc.v:159470$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157838$8473_Y - connect \Y $pos$libresoc.v:157838$8474_Y + connect \A $extend$libresoc.v:159470$8521_Y + connect \Y $pos$libresoc.v:159470$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157839$8476 + cell $pos $pos$libresoc.v:159471$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157839$8475_Y - connect \Y $pos$libresoc.v:157839$8476_Y + connect \A $extend$libresoc.v:159471$8523_Y + connect \Y $pos$libresoc.v:159471$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157842$8479 + cell $reduce_or $reduce_or$libresoc.v:159474$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157842$8479_Y + connect \Y $reduce_or$libresoc.v:159474$8527_Y end - attribute \src "libresoc.v:157518.7-157518.20" - process $proc$libresoc.v:157518$8488 + attribute \src "libresoc.v:159150.7-159150.20" + process $proc$libresoc.v:159150$8536 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157847.3-157858.6" - process $proc$libresoc.v:157847$8484 + attribute \src "libresoc.v:159479.3-159490.6" + process $proc$libresoc.v:159479$8532 assign { } { } - assign $0\o$23[64:0]$8485 $1\o$23[64:0]$8486 - attribute \src "libresoc.v:157848.5-157848.29" + assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 + attribute \src "libresoc.v:159480.5-159480.29" switch \initial - attribute \src "libresoc.v:157848.9-157848.17" + attribute \src "libresoc.v:159480.9-159480.17" case 1'1 case end @@ -328863,22 +331360,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8486 \$24 + assign $1\o$23[64:0]$8534 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8486 \$28 + assign $1\o$23[64:0]$8534 \$28 end sync always - update \o$23 $0\o$23[64:0]$8485 + update \o$23 $0\o$23[64:0]$8533 end - attribute \src "libresoc.v:157859.3-157870.6" - process $proc$libresoc.v:157859$8487 + attribute \src "libresoc.v:159491.3-159502.6" + process $proc$libresoc.v:159491$8535 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157860.5-157860.29" + attribute \src "libresoc.v:159492.5-159492.29" switch \initial - attribute \src "libresoc.v:157860.9-157860.17" + attribute \src "libresoc.v:159492.9-159492.17" case 1'1 case end @@ -328896,16 +331393,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:157837$8472_Y - connect \$24 $pos$libresoc.v:157838$8474_Y - connect \$28 $pos$libresoc.v:157839$8476_Y - connect \$30 $eq$libresoc.v:157840$8477_Y - connect \$32 $eq$libresoc.v:157841$8478_Y - connect \$34 $reduce_or$libresoc.v:157842$8479_Y - connect \$36 $not$libresoc.v:157843$8480_Y - connect \$38 $and$libresoc.v:157844$8481_Y - connect \$40 $or$libresoc.v:157845$8482_Y - connect \$42 $not$libresoc.v:157846$8483_Y + connect \$25 $not$libresoc.v:159469$8520_Y + connect \$24 $pos$libresoc.v:159470$8522_Y + connect \$28 $pos$libresoc.v:159471$8524_Y + connect \$30 $eq$libresoc.v:159472$8525_Y + connect \$32 $eq$libresoc.v:159473$8526_Y + connect \$34 $reduce_or$libresoc.v:159474$8527_Y + connect \$36 $not$libresoc.v:159475$8528_Y + connect \$38 $and$libresoc.v:159476$8529_Y + connect \$40 $or$libresoc.v:159477$8530_Y + connect \$42 $not$libresoc.v:159478$8531_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -328920,71 +331417,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:157888.1-158338.10" +attribute \src "libresoc.v:159520.1-159970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:158259.3-158270.6" + attribute \src "libresoc.v:159891.3-159902.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157889.7-157889.20" + attribute \src "libresoc.v:159521.7-159521.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158271.3-158282.6" - wire width 65 $0\o$27[64:0]$8507 - attribute \src "libresoc.v:158247.3-158258.6" + attribute \src "libresoc.v:159903.3-159914.6" + wire width 65 $0\o$27[64:0]$8555 + attribute \src "libresoc.v:159879.3-159890.6" wire $0\so[0:0] - attribute \src "libresoc.v:158303.3-158312.6" - wire width 2 $0\xer_ov$23[1:0]$8514 - attribute \src "libresoc.v:158313.3-158322.6" + attribute \src "libresoc.v:159935.3-159944.6" + wire width 2 $0\xer_ov$23[1:0]$8562 + attribute \src "libresoc.v:159945.3-159954.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158283.3-158292.6" - wire $0\xer_so$24[0:0]$8510 - attribute \src "libresoc.v:158293.3-158302.6" + attribute \src "libresoc.v:159915.3-159924.6" + wire $0\xer_so$24[0:0]$8558 + attribute \src "libresoc.v:159925.3-159934.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158259.3-158270.6" + attribute \src "libresoc.v:159891.3-159902.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158271.3-158282.6" - wire width 65 $1\o$27[64:0]$8508 - attribute \src "libresoc.v:158247.3-158258.6" + attribute \src "libresoc.v:159903.3-159914.6" + wire width 65 $1\o$27[64:0]$8556 + attribute \src "libresoc.v:159879.3-159890.6" wire $1\so[0:0] - attribute \src "libresoc.v:158303.3-158312.6" - wire width 2 $1\xer_ov$23[1:0]$8515 - attribute \src "libresoc.v:158313.3-158322.6" + attribute \src "libresoc.v:159935.3-159944.6" + wire width 2 $1\xer_ov$23[1:0]$8563 + attribute \src "libresoc.v:159945.3-159954.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158283.3-158292.6" - wire $1\xer_so$24[0:0]$8511 - attribute \src "libresoc.v:158293.3-158302.6" + attribute \src "libresoc.v:159915.3-159924.6" + wire $1\xer_so$24[0:0]$8559 + attribute \src "libresoc.v:159925.3-159934.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158234.18-158234.136" - wire $and$libresoc.v:158234$8489_Y - attribute \src "libresoc.v:158242.18-158242.112" - wire $and$libresoc.v:158242$8499_Y - attribute \src "libresoc.v:158245.18-158245.133" - wire $and$libresoc.v:158245$8502_Y - attribute \src "libresoc.v:158238.18-158238.127" - wire $eq$libresoc.v:158238$8495_Y - attribute \src "libresoc.v:158239.18-158239.127" - wire $eq$libresoc.v:158239$8496_Y - attribute \src "libresoc.v:158236.18-158236.103" - wire width 65 $extend$libresoc.v:158236$8491_Y - attribute \src "libresoc.v:158237.18-158237.101" - wire width 65 $extend$libresoc.v:158237$8493_Y - attribute \src "libresoc.v:158235.18-158235.100" - wire width 64 $not$libresoc.v:158235$8490_Y - attribute \src "libresoc.v:158241.18-158241.107" - wire $not$libresoc.v:158241$8498_Y - attribute \src "libresoc.v:158244.18-158244.107" - wire $not$libresoc.v:158244$8501_Y - attribute \src "libresoc.v:158243.18-158243.115" - wire $or$libresoc.v:158243$8500_Y - attribute \src "libresoc.v:158246.18-158246.112" - wire $or$libresoc.v:158246$8503_Y - attribute \src "libresoc.v:158236.18-158236.103" - wire width 65 $pos$libresoc.v:158236$8492_Y - attribute \src "libresoc.v:158237.18-158237.101" - wire width 65 $pos$libresoc.v:158237$8494_Y - attribute \src "libresoc.v:158240.18-158240.105" - wire $reduce_or$libresoc.v:158240$8497_Y + attribute \src "libresoc.v:159866.18-159866.136" + wire $and$libresoc.v:159866$8537_Y + attribute \src "libresoc.v:159874.18-159874.112" + wire $and$libresoc.v:159874$8547_Y + attribute \src "libresoc.v:159877.18-159877.133" + wire $and$libresoc.v:159877$8550_Y + attribute \src "libresoc.v:159870.18-159870.127" + wire $eq$libresoc.v:159870$8543_Y + attribute \src "libresoc.v:159871.18-159871.127" + wire $eq$libresoc.v:159871$8544_Y + attribute \src "libresoc.v:159868.18-159868.103" + wire width 65 $extend$libresoc.v:159868$8539_Y + attribute \src "libresoc.v:159869.18-159869.101" + wire width 65 $extend$libresoc.v:159869$8541_Y + attribute \src "libresoc.v:159867.18-159867.100" + wire width 64 $not$libresoc.v:159867$8538_Y + attribute \src "libresoc.v:159873.18-159873.107" + wire $not$libresoc.v:159873$8546_Y + attribute \src "libresoc.v:159876.18-159876.107" + wire $not$libresoc.v:159876$8549_Y + attribute \src "libresoc.v:159875.18-159875.115" + wire $or$libresoc.v:159875$8548_Y + attribute \src "libresoc.v:159878.18-159878.112" + wire $or$libresoc.v:159878$8551_Y + attribute \src "libresoc.v:159868.18-159868.103" + wire width 65 $pos$libresoc.v:159868$8540_Y + attribute \src "libresoc.v:159869.18-159869.101" + wire width 65 $pos$libresoc.v:159869$8542_Y + attribute \src "libresoc.v:159872.18-159872.105" + wire $reduce_or$libresoc.v:159872$8545_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -329019,7 +331516,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:157889.7-157889.15" + attribute \src "libresoc.v:159521.7-159521.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -329328,7 +331825,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158234$8489 + cell $and $and$libresoc.v:159866$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329336,10 +331833,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:158234$8489_Y + connect \Y $and$libresoc.v:159866$8537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158242$8499 + cell $and $and$libresoc.v:159874$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329347,10 +331844,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:158242$8499_Y + connect \Y $and$libresoc.v:159874$8547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158245$8502 + cell $and $and$libresoc.v:159877$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329358,10 +331855,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:158245$8502_Y + connect \Y $and$libresoc.v:159877$8550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158238$8495 + cell $eq $eq$libresoc.v:159870$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329369,10 +331866,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158238$8495_Y + connect \Y $eq$libresoc.v:159870$8543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158239$8496 + cell $eq $eq$libresoc.v:159871$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329380,50 +331877,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158239$8496_Y + connect \Y $eq$libresoc.v:159871$8544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:158236$8491 + cell $pos $extend$libresoc.v:159868$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:158236$8491_Y + connect \Y $extend$libresoc.v:159868$8539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158237$8493 + cell $pos $extend$libresoc.v:159869$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158237$8493_Y + connect \Y $extend$libresoc.v:159869$8541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:158235$8490 + cell $not $not$libresoc.v:159867$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:158235$8490_Y + connect \Y $not$libresoc.v:159867$8538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158241$8498 + cell $not $not$libresoc.v:159873$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158241$8498_Y + connect \Y $not$libresoc.v:159873$8546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158244$8501 + cell $not $not$libresoc.v:159876$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158244$8501_Y + connect \Y $not$libresoc.v:159876$8549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158243$8500 + cell $or $or$libresoc.v:159875$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329431,10 +331928,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158243$8500_Y + connect \Y $or$libresoc.v:159875$8548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158246$8503 + cell $or $or$libresoc.v:159878$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329442,47 +331939,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158246$8503_Y + connect \Y $or$libresoc.v:159878$8551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:158236$8492 + cell $pos $pos$libresoc.v:159868$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158236$8491_Y - connect \Y $pos$libresoc.v:158236$8492_Y + connect \A $extend$libresoc.v:159868$8539_Y + connect \Y $pos$libresoc.v:159868$8540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158237$8494 + cell $pos $pos$libresoc.v:159869$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158237$8493_Y - connect \Y $pos$libresoc.v:158237$8494_Y + connect \A $extend$libresoc.v:159869$8541_Y + connect \Y $pos$libresoc.v:159869$8542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158240$8497 + cell $reduce_or $reduce_or$libresoc.v:159872$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158240$8497_Y + connect \Y $reduce_or$libresoc.v:159872$8545_Y end - attribute \src "libresoc.v:157889.7-157889.20" - process $proc$libresoc.v:157889$8517 + attribute \src "libresoc.v:159521.7-159521.20" + process $proc$libresoc.v:159521$8565 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158247.3-158258.6" - process $proc$libresoc.v:158247$8504 + attribute \src "libresoc.v:159879.3-159890.6" + process $proc$libresoc.v:159879$8552 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158248.5-158248.29" + attribute \src "libresoc.v:159880.5-159880.29" switch \initial - attribute \src "libresoc.v:158248.9-158248.17" + attribute \src "libresoc.v:159880.9-159880.17" case 1'1 case end @@ -329500,13 +331997,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158259.3-158270.6" - process $proc$libresoc.v:158259$8505 + attribute \src "libresoc.v:159891.3-159902.6" + process $proc$libresoc.v:159891$8553 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158260.5-158260.29" + attribute \src "libresoc.v:159892.5-159892.29" switch \initial - attribute \src "libresoc.v:158260.9-158260.17" + attribute \src "libresoc.v:159892.9-159892.17" case 1'1 case end @@ -329524,13 +332021,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158271.3-158282.6" - process $proc$libresoc.v:158271$8506 + attribute \src "libresoc.v:159903.3-159914.6" + process $proc$libresoc.v:159903$8554 assign { } { } - assign $0\o$27[64:0]$8507 $1\o$27[64:0]$8508 - attribute \src "libresoc.v:158272.5-158272.29" + assign $0\o$27[64:0]$8555 $1\o$27[64:0]$8556 + attribute \src "libresoc.v:159904.5-159904.29" switch \initial - attribute \src "libresoc.v:158272.9-158272.17" + attribute \src "libresoc.v:159904.9-159904.17" case 1'1 case end @@ -329539,23 +332036,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8508 \$28 + assign $1\o$27[64:0]$8556 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8508 \$32 + assign $1\o$27[64:0]$8556 \$32 end sync always - update \o$27 $0\o$27[64:0]$8507 + update \o$27 $0\o$27[64:0]$8555 end - attribute \src "libresoc.v:158283.3-158292.6" - process $proc$libresoc.v:158283$8509 + attribute \src "libresoc.v:159915.3-159924.6" + process $proc$libresoc.v:159915$8557 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8510 $1\xer_so$24[0:0]$8511 - attribute \src "libresoc.v:158284.5-158284.29" + assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 + attribute \src "libresoc.v:159916.5-159916.29" switch \initial - attribute \src "libresoc.v:158284.9-158284.17" + attribute \src "libresoc.v:159916.9-159916.17" case 1'1 case end @@ -329564,21 +332061,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8511 \$51 + assign $1\xer_so$24[0:0]$8559 \$51 case - assign $1\xer_so$24[0:0]$8511 1'0 + assign $1\xer_so$24[0:0]$8559 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8510 + update \xer_so$24 $0\xer_so$24[0:0]$8558 end - attribute \src "libresoc.v:158293.3-158302.6" - process $proc$libresoc.v:158293$8512 + attribute \src "libresoc.v:159925.3-159934.6" + process $proc$libresoc.v:159925$8560 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158294.5-158294.29" + attribute \src "libresoc.v:159926.5-159926.29" switch \initial - attribute \src "libresoc.v:158294.9-158294.17" + attribute \src "libresoc.v:159926.9-159926.17" case 1'1 case end @@ -329594,14 +332091,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158303.3-158312.6" - process $proc$libresoc.v:158303$8513 + attribute \src "libresoc.v:159935.3-159944.6" + process $proc$libresoc.v:159935$8561 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8514 $1\xer_ov$23[1:0]$8515 - attribute \src "libresoc.v:158304.5-158304.29" + assign $0\xer_ov$23[1:0]$8562 $1\xer_ov$23[1:0]$8563 + attribute \src "libresoc.v:159936.5-159936.29" switch \initial - attribute \src "libresoc.v:158304.9-158304.17" + attribute \src "libresoc.v:159936.9-159936.17" case 1'1 case end @@ -329610,21 +332107,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8515 \xer_ov + assign $1\xer_ov$23[1:0]$8563 \xer_ov case - assign $1\xer_ov$23[1:0]$8515 2'00 + assign $1\xer_ov$23[1:0]$8563 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8514 + update \xer_ov$23 $0\xer_ov$23[1:0]$8562 end - attribute \src "libresoc.v:158313.3-158322.6" - process $proc$libresoc.v:158313$8516 + attribute \src "libresoc.v:159945.3-159954.6" + process $proc$libresoc.v:159945$8564 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158314.5-158314.29" + attribute \src "libresoc.v:159946.5-159946.29" switch \initial - attribute \src "libresoc.v:158314.9-158314.17" + attribute \src "libresoc.v:159946.9-159946.17" case 1'1 case end @@ -329640,19 +332137,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:158234$8489_Y - connect \$29 $not$libresoc.v:158235$8490_Y - connect \$28 $pos$libresoc.v:158236$8492_Y - connect \$32 $pos$libresoc.v:158237$8494_Y - connect \$34 $eq$libresoc.v:158238$8495_Y - connect \$36 $eq$libresoc.v:158239$8496_Y - connect \$38 $reduce_or$libresoc.v:158240$8497_Y - connect \$40 $not$libresoc.v:158241$8498_Y - connect \$42 $and$libresoc.v:158242$8499_Y - connect \$44 $or$libresoc.v:158243$8500_Y - connect \$46 $not$libresoc.v:158244$8501_Y - connect \$49 $and$libresoc.v:158245$8502_Y - connect \$51 $or$libresoc.v:158246$8503_Y + connect \$25 $and$libresoc.v:159866$8537_Y + connect \$29 $not$libresoc.v:159867$8538_Y + connect \$28 $pos$libresoc.v:159868$8540_Y + connect \$32 $pos$libresoc.v:159869$8542_Y + connect \$34 $eq$libresoc.v:159870$8543_Y + connect \$36 $eq$libresoc.v:159871$8544_Y + connect \$38 $reduce_or$libresoc.v:159872$8545_Y + connect \$40 $not$libresoc.v:159873$8546_Y + connect \$42 $and$libresoc.v:159874$8547_Y + connect \$44 $or$libresoc.v:159875$8548_Y + connect \$46 $not$libresoc.v:159876$8549_Y + connect \$49 $and$libresoc.v:159877$8550_Y + connect \$51 $or$libresoc.v:159878$8551_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -329669,93 +332166,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:158342.1-158824.10" +attribute \src "libresoc.v:159974.1-160456.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:158343.7-158343.20" + attribute \src "libresoc.v:159975.7-159975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $0\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $1\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $2\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $3\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:158696.18-158696.122" - wire $and$libresoc.v:158696$8531_Y - attribute \src "libresoc.v:158688.18-158688.109" - wire width 65 $extend$libresoc.v:158688$8519_Y - attribute \src "libresoc.v:158689.18-158689.100" - wire width 65 $extend$libresoc.v:158689$8521_Y - attribute \src "libresoc.v:158691.18-158691.113" - wire width 65 $extend$libresoc.v:158691$8524_Y - attribute \src "libresoc.v:158692.18-158692.104" - wire width 65 $extend$libresoc.v:158692$8526_Y - attribute \src "libresoc.v:158700.18-158700.114" - wire width 64 $extend$libresoc.v:158700$8535_Y - attribute \src "libresoc.v:158701.18-158701.114" - wire width 64 $extend$libresoc.v:158701$8537_Y - attribute \src "libresoc.v:158702.18-158702.114" - wire width 64 $extend$libresoc.v:158702$8539_Y - attribute \src "libresoc.v:158703.18-158703.114" - wire width 64 $extend$libresoc.v:158703$8541_Y - attribute \src "libresoc.v:158704.18-158704.115" - wire width 64 $extend$libresoc.v:158704$8543_Y - attribute \src "libresoc.v:158697.18-158697.128" - wire $ne$libresoc.v:158697$8532_Y - attribute \src "libresoc.v:158688.18-158688.109" - wire width 65 $neg$libresoc.v:158688$8520_Y - attribute \src "libresoc.v:158691.18-158691.113" - wire width 65 $neg$libresoc.v:158691$8525_Y - attribute \src "libresoc.v:158694.18-158694.116" - wire $not$libresoc.v:158694$8529_Y - attribute \src "libresoc.v:158699.18-158699.99" - wire $not$libresoc.v:158699$8534_Y - attribute \src "libresoc.v:158689.18-158689.100" - wire width 65 $pos$libresoc.v:158689$8522_Y - attribute \src "libresoc.v:158692.18-158692.104" - wire width 65 $pos$libresoc.v:158692$8527_Y - attribute \src "libresoc.v:158698.18-158698.118" - wire width 64 $pos$libresoc.v:158698$8533_Y - attribute \src "libresoc.v:158700.18-158700.114" - wire width 64 $pos$libresoc.v:158700$8536_Y - attribute \src "libresoc.v:158701.18-158701.114" - wire width 64 $pos$libresoc.v:158701$8538_Y - attribute \src "libresoc.v:158702.18-158702.114" - wire width 64 $pos$libresoc.v:158702$8540_Y - attribute \src "libresoc.v:158703.18-158703.114" - wire width 64 $pos$libresoc.v:158703$8542_Y - attribute \src "libresoc.v:158704.18-158704.115" - wire width 64 $pos$libresoc.v:158704$8544_Y - attribute \src "libresoc.v:158690.18-158690.121" - wire width 65 $ternary$libresoc.v:158690$8523_Y - attribute \src "libresoc.v:158693.18-158693.122" - wire width 65 $ternary$libresoc.v:158693$8528_Y - attribute \src "libresoc.v:158687.18-158687.120" - wire $xor$libresoc.v:158687$8518_Y - attribute \src "libresoc.v:158695.18-158695.127" - wire $xor$libresoc.v:158695$8530_Y + attribute \src "libresoc.v:160328.18-160328.122" + wire $and$libresoc.v:160328$8579_Y + attribute \src "libresoc.v:160320.18-160320.109" + wire width 65 $extend$libresoc.v:160320$8567_Y + attribute \src "libresoc.v:160321.18-160321.100" + wire width 65 $extend$libresoc.v:160321$8569_Y + attribute \src "libresoc.v:160323.18-160323.113" + wire width 65 $extend$libresoc.v:160323$8572_Y + attribute \src "libresoc.v:160324.18-160324.104" + wire width 65 $extend$libresoc.v:160324$8574_Y + attribute \src "libresoc.v:160332.18-160332.114" + wire width 64 $extend$libresoc.v:160332$8583_Y + attribute \src "libresoc.v:160333.18-160333.114" + wire width 64 $extend$libresoc.v:160333$8585_Y + attribute \src "libresoc.v:160334.18-160334.114" + wire width 64 $extend$libresoc.v:160334$8587_Y + attribute \src "libresoc.v:160335.18-160335.114" + wire width 64 $extend$libresoc.v:160335$8589_Y + attribute \src "libresoc.v:160336.18-160336.115" + wire width 64 $extend$libresoc.v:160336$8591_Y + attribute \src "libresoc.v:160329.18-160329.128" + wire $ne$libresoc.v:160329$8580_Y + attribute \src "libresoc.v:160320.18-160320.109" + wire width 65 $neg$libresoc.v:160320$8568_Y + attribute \src "libresoc.v:160323.18-160323.113" + wire width 65 $neg$libresoc.v:160323$8573_Y + attribute \src "libresoc.v:160326.18-160326.116" + wire $not$libresoc.v:160326$8577_Y + attribute \src "libresoc.v:160331.18-160331.99" + wire $not$libresoc.v:160331$8582_Y + attribute \src "libresoc.v:160321.18-160321.100" + wire width 65 $pos$libresoc.v:160321$8570_Y + attribute \src "libresoc.v:160324.18-160324.104" + wire width 65 $pos$libresoc.v:160324$8575_Y + attribute \src "libresoc.v:160330.18-160330.118" + wire width 64 $pos$libresoc.v:160330$8581_Y + attribute \src "libresoc.v:160332.18-160332.114" + wire width 64 $pos$libresoc.v:160332$8584_Y + attribute \src "libresoc.v:160333.18-160333.114" + wire width 64 $pos$libresoc.v:160333$8586_Y + attribute \src "libresoc.v:160334.18-160334.114" + wire width 64 $pos$libresoc.v:160334$8588_Y + attribute \src "libresoc.v:160335.18-160335.114" + wire width 64 $pos$libresoc.v:160335$8590_Y + attribute \src "libresoc.v:160336.18-160336.115" + wire width 64 $pos$libresoc.v:160336$8592_Y + attribute \src "libresoc.v:160322.18-160322.121" + wire width 65 $ternary$libresoc.v:160322$8571_Y + attribute \src "libresoc.v:160325.18-160325.122" + wire width 65 $ternary$libresoc.v:160325$8576_Y + attribute \src "libresoc.v:160319.18-160319.120" + wire $xor$libresoc.v:160319$8566_Y + attribute \src "libresoc.v:160327.18-160327.127" + wire $xor$libresoc.v:160327$8578_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -329804,7 +332301,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:158343.7-158343.15" + attribute \src "libresoc.v:159975.7-159975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -330101,7 +332598,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:158696$8531 + cell $and $and$libresoc.v:160328$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330109,82 +332606,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:158696$8531_Y + connect \Y $and$libresoc.v:160328$8579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:158688$8519 + cell $pos $extend$libresoc.v:160320$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:158688$8519_Y + connect \Y $extend$libresoc.v:160320$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:158689$8521 + cell $pos $extend$libresoc.v:160321$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:158689$8521_Y + connect \Y $extend$libresoc.v:160321$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:158691$8524 + cell $pos $extend$libresoc.v:160323$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:158691$8524_Y + connect \Y $extend$libresoc.v:160323$8572_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:158692$8526 + cell $pos $extend$libresoc.v:160324$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:158692$8526_Y + connect \Y $extend$libresoc.v:160324$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:158700$8535 + cell $pos $extend$libresoc.v:160332$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158700$8535_Y + connect \Y $extend$libresoc.v:160332$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:158701$8537 + cell $pos $extend$libresoc.v:160333$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158701$8537_Y + connect \Y $extend$libresoc.v:160333$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:158702$8539 + cell $pos $extend$libresoc.v:160334$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158702$8539_Y + connect \Y $extend$libresoc.v:160334$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:158703$8541 + cell $pos $extend$libresoc.v:160335$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158703$8541_Y + connect \Y $extend$libresoc.v:160335$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:158704$8543 + cell $pos $extend$libresoc.v:160336$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:158704$8543_Y + connect \Y $extend$libresoc.v:160336$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:158697$8532 + cell $ne $ne$libresoc.v:160329$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330192,122 +332689,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:158697$8532_Y + connect \Y $ne$libresoc.v:160329$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:158688$8520 + cell $neg $neg$libresoc.v:160320$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158688$8519_Y - connect \Y $neg$libresoc.v:158688$8520_Y + connect \A $extend$libresoc.v:160320$8567_Y + connect \Y $neg$libresoc.v:160320$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:158691$8525 + cell $neg $neg$libresoc.v:160323$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158691$8524_Y - connect \Y $neg$libresoc.v:158691$8525_Y + connect \A $extend$libresoc.v:160323$8572_Y + connect \Y $neg$libresoc.v:160323$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:158694$8529 + cell $not $not$libresoc.v:160326$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:158694$8529_Y + connect \Y $not$libresoc.v:160326$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:158699$8534 + cell $not $not$libresoc.v:160331$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:158699$8534_Y + connect \Y $not$libresoc.v:160331$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:158689$8522 + cell $pos $pos$libresoc.v:160321$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158689$8521_Y - connect \Y $pos$libresoc.v:158689$8522_Y + connect \A $extend$libresoc.v:160321$8569_Y + connect \Y $pos$libresoc.v:160321$8570_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:158692$8527 + cell $pos $pos$libresoc.v:160324$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158692$8526_Y - connect \Y $pos$libresoc.v:158692$8527_Y + connect \A $extend$libresoc.v:160324$8574_Y + connect \Y $pos$libresoc.v:160324$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:158698$8533 + cell $pos $pos$libresoc.v:160330$8581 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:158698$8533_Y + connect \Y $pos$libresoc.v:160330$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:158700$8536 + cell $pos $pos$libresoc.v:160332$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158700$8535_Y - connect \Y $pos$libresoc.v:158700$8536_Y + connect \A $extend$libresoc.v:160332$8583_Y + connect \Y $pos$libresoc.v:160332$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:158701$8538 + cell $pos $pos$libresoc.v:160333$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158701$8537_Y - connect \Y $pos$libresoc.v:158701$8538_Y + connect \A $extend$libresoc.v:160333$8585_Y + connect \Y $pos$libresoc.v:160333$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:158702$8540 + cell $pos $pos$libresoc.v:160334$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158702$8539_Y - connect \Y $pos$libresoc.v:158702$8540_Y + connect \A $extend$libresoc.v:160334$8587_Y + connect \Y $pos$libresoc.v:160334$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:158703$8542 + cell $pos $pos$libresoc.v:160335$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158703$8541_Y - connect \Y $pos$libresoc.v:158703$8542_Y + connect \A $extend$libresoc.v:160335$8589_Y + connect \Y $pos$libresoc.v:160335$8590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:158704$8544 + cell $pos $pos$libresoc.v:160336$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158704$8543_Y - connect \Y $pos$libresoc.v:158704$8544_Y + connect \A $extend$libresoc.v:160336$8591_Y + connect \Y $pos$libresoc.v:160336$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:158690$8523 + cell $mux $ternary$libresoc.v:160322$8571 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:158690$8523_Y + connect \Y $ternary$libresoc.v:160322$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:158693$8528 + cell $mux $ternary$libresoc.v:160325$8576 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:158693$8528_Y + connect \Y $ternary$libresoc.v:160325$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:158687$8518 + cell $xor $xor$libresoc.v:160319$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330315,10 +332812,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:158687$8518_Y + connect \Y $xor$libresoc.v:160319$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:158695$8530 + cell $xor $xor$libresoc.v:160327$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330326,24 +332823,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:158695$8530_Y + connect \Y $xor$libresoc.v:160327$8578_Y end - attribute \src "libresoc.v:158343.7-158343.20" - process $proc$libresoc.v:158343$8547 + attribute \src "libresoc.v:159975.7-159975.20" + process $proc$libresoc.v:159975$8595 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158705.3-158776.6" - process $proc$libresoc.v:158705$8545 + attribute \src "libresoc.v:160337.3-160408.6" + process $proc$libresoc.v:160337$8593 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:158706.5-158706.29" + attribute \src "libresoc.v:160338.5-160338.29" switch \initial - attribute \src "libresoc.v:158706.9-158706.17" + attribute \src "libresoc.v:160338.9-160338.17" case 1'1 case end @@ -330442,13 +332939,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:158777.3-158810.6" - process $proc$libresoc.v:158777$8546 + attribute \src "libresoc.v:160409.3-160442.6" + process $proc$libresoc.v:160409$8594 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:158778.5-158778.29" + attribute \src "libresoc.v:160410.5-160410.29" switch \initial - attribute \src "libresoc.v:158778.9-158778.17" + attribute \src "libresoc.v:160410.9-160410.17" case 1'1 case end @@ -330494,24 +332991,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:158687$8518_Y - connect \$23 $neg$libresoc.v:158688$8520_Y - connect \$25 $pos$libresoc.v:158689$8522_Y - connect \$27 $ternary$libresoc.v:158690$8523_Y - connect \$30 $neg$libresoc.v:158691$8525_Y - connect \$32 $pos$libresoc.v:158692$8527_Y - connect \$34 $ternary$libresoc.v:158693$8528_Y - connect \$36 $not$libresoc.v:158694$8529_Y - connect \$38 $xor$libresoc.v:158695$8530_Y - connect \$40 $and$libresoc.v:158696$8531_Y - connect \$42 $ne$libresoc.v:158697$8532_Y - connect \$44 $pos$libresoc.v:158698$8533_Y - connect \$46 $not$libresoc.v:158699$8534_Y - connect \$48 $pos$libresoc.v:158700$8536_Y - connect \$50 $pos$libresoc.v:158701$8538_Y - connect \$52 $pos$libresoc.v:158702$8540_Y - connect \$54 $pos$libresoc.v:158703$8542_Y - connect \$56 $pos$libresoc.v:158704$8544_Y + connect \$21 $xor$libresoc.v:160319$8566_Y + connect \$23 $neg$libresoc.v:160320$8568_Y + connect \$25 $pos$libresoc.v:160321$8570_Y + connect \$27 $ternary$libresoc.v:160322$8571_Y + connect \$30 $neg$libresoc.v:160323$8573_Y + connect \$32 $pos$libresoc.v:160324$8575_Y + connect \$34 $ternary$libresoc.v:160325$8576_Y + connect \$36 $not$libresoc.v:160326$8577_Y + connect \$38 $xor$libresoc.v:160327$8578_Y + connect \$40 $and$libresoc.v:160328$8579_Y + connect \$42 $ne$libresoc.v:160329$8580_Y + connect \$44 $pos$libresoc.v:160330$8581_Y + connect \$46 $not$libresoc.v:160331$8582_Y + connect \$48 $pos$libresoc.v:160332$8584_Y + connect \$50 $pos$libresoc.v:160333$8586_Y + connect \$52 $pos$libresoc.v:160334$8588_Y + connect \$54 $pos$libresoc.v:160335$8590_Y + connect \$56 $pos$libresoc.v:160336$8592_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -330526,13 +333023,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:158828.1-158839.10" +attribute \src "libresoc.v:160460.1-160471.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:158837.17-158837.111" - wire $and$libresoc.v:158837$8548_Y + attribute \src "libresoc.v:160469.17-160469.111" + wire $and$libresoc.v:160469$8596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330542,7 +333039,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158837$8548 + cell $and $and$libresoc.v:160469$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330550,18 +333047,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158837$8548_Y + connect \Y $and$libresoc.v:160469$8596_Y end - connect \$1 $and$libresoc.v:158837$8548_Y + connect \$1 $and$libresoc.v:160469$8596_Y connect \trigger \$1 end -attribute \src "libresoc.v:158843.1-158854.10" +attribute \src "libresoc.v:160475.1-160486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:158852.17-158852.111" - wire $and$libresoc.v:158852$8549_Y + attribute \src "libresoc.v:160484.17-160484.111" + wire $and$libresoc.v:160484$8597_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330571,7 +333068,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158852$8549 + cell $and $and$libresoc.v:160484$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330579,18 +333076,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158852$8549_Y + connect \Y $and$libresoc.v:160484$8597_Y end - connect \$1 $and$libresoc.v:158852$8549_Y + connect \$1 $and$libresoc.v:160484$8597_Y connect \trigger \$1 end -attribute \src "libresoc.v:158858.1-158869.10" +attribute \src "libresoc.v:160490.1-160501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:158867.17-158867.111" - wire $and$libresoc.v:158867$8550_Y + attribute \src "libresoc.v:160499.17-160499.111" + wire $and$libresoc.v:160499$8598_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330600,7 +333097,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158867$8550 + cell $and $and$libresoc.v:160499$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330608,18 +333105,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158867$8550_Y + connect \Y $and$libresoc.v:160499$8598_Y end - connect \$1 $and$libresoc.v:158867$8550_Y + connect \$1 $and$libresoc.v:160499$8598_Y connect \trigger \$1 end -attribute \src "libresoc.v:158873.1-158884.10" +attribute \src "libresoc.v:160505.1-160516.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:158882.17-158882.111" - wire $and$libresoc.v:158882$8551_Y + attribute \src "libresoc.v:160514.17-160514.111" + wire $and$libresoc.v:160514$8599_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330629,7 +333126,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158882$8551 + cell $and $and$libresoc.v:160514$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330637,18 +333134,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158882$8551_Y + connect \Y $and$libresoc.v:160514$8599_Y end - connect \$1 $and$libresoc.v:158882$8551_Y + connect \$1 $and$libresoc.v:160514$8599_Y connect \trigger \$1 end -attribute \src "libresoc.v:158888.1-158899.10" +attribute \src "libresoc.v:160520.1-160531.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:158897.17-158897.111" - wire $and$libresoc.v:158897$8552_Y + attribute \src "libresoc.v:160529.17-160529.111" + wire $and$libresoc.v:160529$8600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330658,7 +333155,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158897$8552 + cell $and $and$libresoc.v:160529$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330666,18 +333163,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158897$8552_Y + connect \Y $and$libresoc.v:160529$8600_Y end - connect \$1 $and$libresoc.v:158897$8552_Y + connect \$1 $and$libresoc.v:160529$8600_Y connect \trigger \$1 end -attribute \src "libresoc.v:158903.1-158914.10" +attribute \src "libresoc.v:160535.1-160546.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:158912.17-158912.111" - wire $and$libresoc.v:158912$8553_Y + attribute \src "libresoc.v:160544.17-160544.111" + wire $and$libresoc.v:160544$8601_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330687,7 +333184,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158912$8553 + cell $and $and$libresoc.v:160544$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330695,18 +333192,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158912$8553_Y + connect \Y $and$libresoc.v:160544$8601_Y end - connect \$1 $and$libresoc.v:158912$8553_Y + connect \$1 $and$libresoc.v:160544$8601_Y connect \trigger \$1 end -attribute \src "libresoc.v:158918.1-158929.10" +attribute \src "libresoc.v:160550.1-160561.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:158927.17-158927.111" - wire $and$libresoc.v:158927$8554_Y + attribute \src "libresoc.v:160559.17-160559.111" + wire $and$libresoc.v:160559$8602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330716,7 +333213,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158927$8554 + cell $and $and$libresoc.v:160559$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330724,18 +333221,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158927$8554_Y + connect \Y $and$libresoc.v:160559$8602_Y end - connect \$1 $and$libresoc.v:158927$8554_Y + connect \$1 $and$libresoc.v:160559$8602_Y connect \trigger \$1 end -attribute \src "libresoc.v:158933.1-158944.10" +attribute \src "libresoc.v:160565.1-160576.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:158942.17-158942.111" - wire $and$libresoc.v:158942$8555_Y + attribute \src "libresoc.v:160574.17-160574.111" + wire $and$libresoc.v:160574$8603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330745,7 +333242,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158942$8555 + cell $and $and$libresoc.v:160574$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330753,18 +333250,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158942$8555_Y + connect \Y $and$libresoc.v:160574$8603_Y end - connect \$1 $and$libresoc.v:158942$8555_Y + connect \$1 $and$libresoc.v:160574$8603_Y connect \trigger \$1 end -attribute \src "libresoc.v:158948.1-158959.10" +attribute \src "libresoc.v:160580.1-160591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:158957.17-158957.111" - wire $and$libresoc.v:158957$8556_Y + attribute \src "libresoc.v:160589.17-160589.111" + wire $and$libresoc.v:160589$8604_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330774,7 +333271,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158957$8556 + cell $and $and$libresoc.v:160589$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330782,18 +333279,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158957$8556_Y + connect \Y $and$libresoc.v:160589$8604_Y end - connect \$1 $and$libresoc.v:158957$8556_Y + connect \$1 $and$libresoc.v:160589$8604_Y connect \trigger \$1 end -attribute \src "libresoc.v:158963.1-158974.10" +attribute \src "libresoc.v:160595.1-160606.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:158972.17-158972.111" - wire $and$libresoc.v:158972$8557_Y + attribute \src "libresoc.v:160604.17-160604.111" + wire $and$libresoc.v:160604$8605_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330803,7 +333300,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158972$8557 + cell $and $and$libresoc.v:160604$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330811,18 +333308,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158972$8557_Y + connect \Y $and$libresoc.v:160604$8605_Y end - connect \$1 $and$libresoc.v:158972$8557_Y + connect \$1 $and$libresoc.v:160604$8605_Y connect \trigger \$1 end -attribute \src "libresoc.v:158978.1-158989.10" +attribute \src "libresoc.v:160610.1-160621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:158987.17-158987.111" - wire $and$libresoc.v:158987$8558_Y + attribute \src "libresoc.v:160619.17-160619.111" + wire $and$libresoc.v:160619$8606_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330832,7 +333329,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158987$8558 + cell $and $and$libresoc.v:160619$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330840,18 +333337,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158987$8558_Y + connect \Y $and$libresoc.v:160619$8606_Y end - connect \$1 $and$libresoc.v:158987$8558_Y + connect \$1 $and$libresoc.v:160619$8606_Y connect \trigger \$1 end -attribute \src "libresoc.v:158993.1-159004.10" +attribute \src "libresoc.v:160625.1-160636.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:159002.17-159002.111" - wire $and$libresoc.v:159002$8559_Y + attribute \src "libresoc.v:160634.17-160634.111" + wire $and$libresoc.v:160634$8607_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330861,7 +333358,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159002$8559 + cell $and $and$libresoc.v:160634$8607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330869,18 +333366,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159002$8559_Y + connect \Y $and$libresoc.v:160634$8607_Y end - connect \$1 $and$libresoc.v:159002$8559_Y + connect \$1 $and$libresoc.v:160634$8607_Y connect \trigger \$1 end -attribute \src "libresoc.v:159008.1-159019.10" +attribute \src "libresoc.v:160640.1-160651.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:159017.17-159017.111" - wire $and$libresoc.v:159017$8560_Y + attribute \src "libresoc.v:160649.17-160649.111" + wire $and$libresoc.v:160649$8608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330890,7 +333387,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159017$8560 + cell $and $and$libresoc.v:160649$8608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330898,18 +333395,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159017$8560_Y + connect \Y $and$libresoc.v:160649$8608_Y end - connect \$1 $and$libresoc.v:159017$8560_Y + connect \$1 $and$libresoc.v:160649$8608_Y connect \trigger \$1 end -attribute \src "libresoc.v:159023.1-159034.10" +attribute \src "libresoc.v:160655.1-160666.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:159032.17-159032.111" - wire $and$libresoc.v:159032$8561_Y + attribute \src "libresoc.v:160664.17-160664.111" + wire $and$libresoc.v:160664$8609_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330919,7 +333416,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159032$8561 + cell $and $and$libresoc.v:160664$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330927,18 +333424,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159032$8561_Y + connect \Y $and$libresoc.v:160664$8609_Y end - connect \$1 $and$libresoc.v:159032$8561_Y + connect \$1 $and$libresoc.v:160664$8609_Y connect \trigger \$1 end -attribute \src "libresoc.v:159038.1-159049.10" +attribute \src "libresoc.v:160670.1-160681.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:159047.17-159047.111" - wire $and$libresoc.v:159047$8562_Y + attribute \src "libresoc.v:160679.17-160679.111" + wire $and$libresoc.v:160679$8610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330948,7 +333445,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159047$8562 + cell $and $and$libresoc.v:160679$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330956,18 +333453,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159047$8562_Y + connect \Y $and$libresoc.v:160679$8610_Y end - connect \$1 $and$libresoc.v:159047$8562_Y + connect \$1 $and$libresoc.v:160679$8610_Y connect \trigger \$1 end -attribute \src "libresoc.v:159053.1-159064.10" +attribute \src "libresoc.v:160685.1-160696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:159062.17-159062.111" - wire $and$libresoc.v:159062$8563_Y + attribute \src "libresoc.v:160694.17-160694.111" + wire $and$libresoc.v:160694$8611_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330977,7 +333474,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159062$8563 + cell $and $and$libresoc.v:160694$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330985,18 +333482,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159062$8563_Y + connect \Y $and$libresoc.v:160694$8611_Y end - connect \$1 $and$libresoc.v:159062$8563_Y + connect \$1 $and$libresoc.v:160694$8611_Y connect \trigger \$1 end -attribute \src "libresoc.v:159068.1-159079.10" +attribute \src "libresoc.v:160700.1-160711.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:159077.17-159077.111" - wire $and$libresoc.v:159077$8564_Y + attribute \src "libresoc.v:160709.17-160709.111" + wire $and$libresoc.v:160709$8612_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331006,7 +333503,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159077$8564 + cell $and $and$libresoc.v:160709$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331014,18 +333511,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159077$8564_Y + connect \Y $and$libresoc.v:160709$8612_Y end - connect \$1 $and$libresoc.v:159077$8564_Y + connect \$1 $and$libresoc.v:160709$8612_Y connect \trigger \$1 end -attribute \src "libresoc.v:159083.1-159094.10" +attribute \src "libresoc.v:160715.1-160726.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:159092.17-159092.111" - wire $and$libresoc.v:159092$8565_Y + attribute \src "libresoc.v:160724.17-160724.111" + wire $and$libresoc.v:160724$8613_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331035,7 +333532,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159092$8565 + cell $and $and$libresoc.v:160724$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331043,18 +333540,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159092$8565_Y + connect \Y $and$libresoc.v:160724$8613_Y end - connect \$1 $and$libresoc.v:159092$8565_Y + connect \$1 $and$libresoc.v:160724$8613_Y connect \trigger \$1 end -attribute \src "libresoc.v:159098.1-159109.10" +attribute \src "libresoc.v:160730.1-160741.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:159107.17-159107.111" - wire $and$libresoc.v:159107$8566_Y + attribute \src "libresoc.v:160739.17-160739.111" + wire $and$libresoc.v:160739$8614_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331064,7 +333561,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159107$8566 + cell $and $and$libresoc.v:160739$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331072,18 +333569,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159107$8566_Y + connect \Y $and$libresoc.v:160739$8614_Y end - connect \$1 $and$libresoc.v:159107$8566_Y + connect \$1 $and$libresoc.v:160739$8614_Y connect \trigger \$1 end -attribute \src "libresoc.v:159113.1-159124.10" +attribute \src "libresoc.v:160745.1-160756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:159122.17-159122.111" - wire $and$libresoc.v:159122$8567_Y + attribute \src "libresoc.v:160754.17-160754.111" + wire $and$libresoc.v:160754$8615_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331093,7 +333590,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159122$8567 + cell $and $and$libresoc.v:160754$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331101,18 +333598,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159122$8567_Y + connect \Y $and$libresoc.v:160754$8615_Y end - connect \$1 $and$libresoc.v:159122$8567_Y + connect \$1 $and$libresoc.v:160754$8615_Y connect \trigger \$1 end -attribute \src "libresoc.v:159128.1-159139.10" +attribute \src "libresoc.v:160760.1-160771.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:159137.17-159137.111" - wire $and$libresoc.v:159137$8568_Y + attribute \src "libresoc.v:160769.17-160769.111" + wire $and$libresoc.v:160769$8616_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331122,7 +333619,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159137$8568 + cell $and $and$libresoc.v:160769$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331130,18 +333627,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159137$8568_Y + connect \Y $and$libresoc.v:160769$8616_Y end - connect \$1 $and$libresoc.v:159137$8568_Y + connect \$1 $and$libresoc.v:160769$8616_Y connect \trigger \$1 end -attribute \src "libresoc.v:159143.1-159154.10" +attribute \src "libresoc.v:160775.1-160786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:159152.17-159152.111" - wire $and$libresoc.v:159152$8569_Y + attribute \src "libresoc.v:160784.17-160784.111" + wire $and$libresoc.v:160784$8617_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331151,7 +333648,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159152$8569 + cell $and $and$libresoc.v:160784$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331159,18 +333656,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159152$8569_Y + connect \Y $and$libresoc.v:160784$8617_Y end - connect \$1 $and$libresoc.v:159152$8569_Y + connect \$1 $and$libresoc.v:160784$8617_Y connect \trigger \$1 end -attribute \src "libresoc.v:159158.1-159169.10" +attribute \src "libresoc.v:160790.1-160801.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:159167.17-159167.111" - wire $and$libresoc.v:159167$8570_Y + attribute \src "libresoc.v:160799.17-160799.111" + wire $and$libresoc.v:160799$8618_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331180,7 +333677,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159167$8570 + cell $and $and$libresoc.v:160799$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331188,18 +333685,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159167$8570_Y + connect \Y $and$libresoc.v:160799$8618_Y end - connect \$1 $and$libresoc.v:159167$8570_Y + connect \$1 $and$libresoc.v:160799$8618_Y connect \trigger \$1 end -attribute \src "libresoc.v:159173.1-159184.10" +attribute \src "libresoc.v:160805.1-160816.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:159182.17-159182.111" - wire $and$libresoc.v:159182$8571_Y + attribute \src "libresoc.v:160814.17-160814.111" + wire $and$libresoc.v:160814$8619_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331209,7 +333706,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159182$8571 + cell $and $and$libresoc.v:160814$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331217,18 +333714,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159182$8571_Y + connect \Y $and$libresoc.v:160814$8619_Y end - connect \$1 $and$libresoc.v:159182$8571_Y + connect \$1 $and$libresoc.v:160814$8619_Y connect \trigger \$1 end -attribute \src "libresoc.v:159188.1-159199.10" +attribute \src "libresoc.v:160820.1-160831.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:159197.17-159197.111" - wire $and$libresoc.v:159197$8572_Y + attribute \src "libresoc.v:160829.17-160829.111" + wire $and$libresoc.v:160829$8620_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331238,7 +333735,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159197$8572 + cell $and $and$libresoc.v:160829$8620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331246,18 +333743,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159197$8572_Y + connect \Y $and$libresoc.v:160829$8620_Y end - connect \$1 $and$libresoc.v:159197$8572_Y + connect \$1 $and$libresoc.v:160829$8620_Y connect \trigger \$1 end -attribute \src "libresoc.v:159203.1-159214.10" +attribute \src "libresoc.v:160835.1-160846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:159212.17-159212.111" - wire $and$libresoc.v:159212$8573_Y + attribute \src "libresoc.v:160844.17-160844.111" + wire $and$libresoc.v:160844$8621_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331267,7 +333764,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159212$8573 + cell $and $and$libresoc.v:160844$8621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331275,36 +333772,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159212$8573_Y + connect \Y $and$libresoc.v:160844$8621_Y end - connect \$1 $and$libresoc.v:159212$8573_Y + connect \$1 $and$libresoc.v:160844$8621_Y connect \trigger \$1 end -attribute \src "libresoc.v:159218.1-159241.10" +attribute \src "libresoc.v:160850.1-160873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:159219.7-159219.20" + attribute \src "libresoc.v:160851.7-160851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159230.3-159239.6" + attribute \src "libresoc.v:160862.3-160871.6" wire $0\o[0:0] - attribute \src "libresoc.v:159230.3-159239.6" + attribute \src "libresoc.v:160862.3-160871.6" wire $1\o[0:0] - attribute \src "libresoc.v:159229.17-159229.95" - wire $eq$libresoc.v:159229$8574_Y + attribute \src "libresoc.v:160861.17-160861.95" + wire $eq$libresoc.v:160861$8622_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:159219.7-159219.15" + attribute \src "libresoc.v:160851.7-160851.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:159229$8574 + cell $eq $eq$libresoc.v:160861$8622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331312,24 +333809,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:159229$8574_Y + connect \Y $eq$libresoc.v:160861$8622_Y end - attribute \src "libresoc.v:159219.7-159219.20" - process $proc$libresoc.v:159219$8576 + attribute \src "libresoc.v:160851.7-160851.20" + process $proc$libresoc.v:160851$8624 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159230.3-159239.6" - process $proc$libresoc.v:159230$8575 + attribute \src "libresoc.v:160862.3-160871.6" + process $proc$libresoc.v:160862$8623 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:159231.5-159231.29" + attribute \src "libresoc.v:160863.5-160863.29" switch \initial - attribute \src "libresoc.v:159231.9-159231.17" + attribute \src "libresoc.v:160863.9-160863.17" case 1'1 case end @@ -331345,296 +333842,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:159229$8574_Y + connect \$1 $eq$libresoc.v:160861$8622_Y connect \n \$1 end -attribute \src "libresoc.v:159245.1-160059.10" +attribute \src "libresoc.v:160877.1-161691.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8666 - attribute \src "libresoc.v:159544.3-159545.57" + attribute \src "libresoc.v:161618.3-161653.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8714 + attribute \src "libresoc.v:161176.3-161177.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:159636.3-159644.6" - wire $0\busy_delay$next[0:0]$8634 - attribute \src "libresoc.v:159542.3-159543.37" + attribute \src "libresoc.v:161268.3-161276.6" + wire $0\busy_delay$next[0:0]$8682 + attribute \src "libresoc.v:161174.3-161175.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161602.3-161617.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159960.3-159969.6" + attribute \src "libresoc.v:161592.3-161601.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159950.3-159959.6" + attribute \src "libresoc.v:161582.3-161591.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159931.3-159940.6" + attribute \src "libresoc.v:161563.3-161572.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $0\fsm_state$next[1:0]$8652 - attribute \src "libresoc.v:159534.3-159535.35" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $0\fsm_state$next[1:0]$8700 + attribute \src "libresoc.v:161166.3-161167.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:159246.7-159246.20" + attribute \src "libresoc.v:160878.7-160878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159832.3-159841.6" + attribute \src "libresoc.v:161464.3-161473.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159540.3-159541.35" + attribute \src "libresoc.v:161172.3-161173.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161397.3-161427.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159822.3-159831.6" + attribute \src "libresoc.v:161454.3-161463.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159842.3-159851.6" + attribute \src "libresoc.v:161474.3-161483.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:159941.3-159949.6" - wire $0\lsui_active_dly$next[0:0]$8660 - attribute \src "libresoc.v:159532.3-159533.47" + attribute \src "libresoc.v:161573.3-161581.6" + wire $0\lsui_active_dly$next[0:0]$8708 + attribute \src "libresoc.v:161164.3-161165.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:159536.3-159537.36" + attribute \src "libresoc.v:161168.3-161169.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:159812.3-159821.6" + attribute \src "libresoc.v:161444.3-161453.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159645.3-159654.6" + attribute \src "libresoc.v:161277.3-161286.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159626.3-159635.6" + attribute \src "libresoc.v:161258.3-161267.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $0\st_done_s_st_done$next[0:0]$8629 - attribute \src "libresoc.v:159546.3-159547.51" + attribute \src "libresoc.v:161243.3-161257.6" + wire $0\st_done_s_st_done$next[0:0]$8677 + attribute \src "libresoc.v:161178.3-161179.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:159852.3-159861.6" + attribute \src "libresoc.v:161484.3-161493.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:159538.3-159539.35" + attribute \src "libresoc.v:161170.3-161171.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:159862.3-159871.6" + attribute \src "libresoc.v:161494.3-161503.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8667 - attribute \src "libresoc.v:159340.7-159340.34" + attribute \src "libresoc.v:161618.3-161653.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8715 + attribute \src "libresoc.v:160972.7-160972.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:159636.3-159644.6" - wire $1\busy_delay$next[0:0]$8635 - attribute \src "libresoc.v:159344.7-159344.24" + attribute \src "libresoc.v:161268.3-161276.6" + wire $1\busy_delay$next[0:0]$8683 + attribute \src "libresoc.v:160976.7-160976.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161602.3-161617.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159960.3-159969.6" + attribute \src "libresoc.v:161592.3-161601.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159950.3-159959.6" + attribute \src "libresoc.v:161582.3-161591.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159931.3-159940.6" + attribute \src "libresoc.v:161563.3-161572.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $1\fsm_state$next[1:0]$8653 - attribute \src "libresoc.v:159366.13-159366.29" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $1\fsm_state$next[1:0]$8701 + attribute \src "libresoc.v:160998.13-160998.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:159832.3-159841.6" + attribute \src "libresoc.v:161464.3-161473.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159380.7-159380.21" + attribute \src "libresoc.v:161012.7-161012.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161397.3-161427.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159822.3-159831.6" + attribute \src "libresoc.v:161454.3-161463.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159842.3-159851.6" + attribute \src "libresoc.v:161474.3-161483.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:159941.3-159949.6" - wire $1\lsui_active_dly$next[0:0]$8661 - attribute \src "libresoc.v:159423.7-159423.29" + attribute \src "libresoc.v:161573.3-161581.6" + wire $1\lsui_active_dly$next[0:0]$8709 + attribute \src "libresoc.v:161055.7-161055.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:159435.7-159435.25" + attribute \src "libresoc.v:161067.7-161067.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:159812.3-159821.6" + attribute \src "libresoc.v:161444.3-161453.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159645.3-159654.6" + attribute \src "libresoc.v:161277.3-161286.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159626.3-159635.6" + attribute \src "libresoc.v:161258.3-161267.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $1\st_done_s_st_done$next[0:0]$8630 - attribute \src "libresoc.v:159455.7-159455.31" + attribute \src "libresoc.v:161243.3-161257.6" + wire $1\st_done_s_st_done$next[0:0]$8678 + attribute \src "libresoc.v:161087.7-161087.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:159852.3-159861.6" + attribute \src "libresoc.v:161484.3-161493.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:159463.7-159463.21" + attribute \src "libresoc.v:161095.7-161095.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:159862.3-159871.6" + attribute \src "libresoc.v:161494.3-161503.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8668 - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8716 + attribute \src "libresoc.v:161602.3-161617.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $2\fsm_state$next[1:0]$8654 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $2\fsm_state$next[1:0]$8702 + attribute \src "libresoc.v:161397.3-161427.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $2\st_done_s_st_done$next[0:0]$8631 - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161243.3-161257.6" + wire $2\st_done_s_st_done$next[0:0]$8679 + attribute \src "libresoc.v:161319.3-161344.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8669 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $3\fsm_state$next[1:0]$8655 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8717 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $3\fsm_state$next[1:0]$8703 + attribute \src "libresoc.v:161397.3-161427.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8670 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $4\fsm_state$next[1:0]$8656 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8718 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $4\fsm_state$next[1:0]$8704 + attribute \src "libresoc.v:161397.3-161427.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8671 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $5\fsm_state$next[1:0]$8657 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8719 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $5\fsm_state$next[1:0]$8705 + attribute \src "libresoc.v:161397.3-161427.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8672 - attribute \src "libresoc.v:159492.18-159492.115" - wire $and$libresoc.v:159492$8578_Y - attribute \src "libresoc.v:159494.18-159494.95" - wire $and$libresoc.v:159494$8580_Y - attribute \src "libresoc.v:159496.17-159496.138" - wire $and$libresoc.v:159496$8582_Y - attribute \src "libresoc.v:159497.18-159497.95" - wire $and$libresoc.v:159497$8583_Y - attribute \src "libresoc.v:159500.18-159500.136" - wire $and$libresoc.v:159500$8588_Y - attribute \src "libresoc.v:159501.18-159501.136" - wire $and$libresoc.v:159501$8589_Y - attribute \src "libresoc.v:159502.18-159502.136" - wire $and$libresoc.v:159502$8590_Y - attribute \src "libresoc.v:159503.18-159503.136" - wire $and$libresoc.v:159503$8591_Y - attribute \src "libresoc.v:159504.18-159504.136" - wire $and$libresoc.v:159504$8592_Y - attribute \src "libresoc.v:159509.18-159509.119" - wire width 176 $and$libresoc.v:159509$8597_Y - attribute \src "libresoc.v:159512.18-159512.136" - wire $and$libresoc.v:159512$8600_Y - attribute \src "libresoc.v:159513.18-159513.136" - wire $and$libresoc.v:159513$8601_Y - attribute \src "libresoc.v:159515.18-159515.139" - wire $and$libresoc.v:159515$8603_Y - attribute \src "libresoc.v:159519.18-159519.139" - wire $and$libresoc.v:159519$8607_Y - attribute \src "libresoc.v:159521.18-159521.114" - wire $and$libresoc.v:159521$8609_Y - attribute \src "libresoc.v:159523.18-159523.114" - wire $and$libresoc.v:159523$8611_Y - attribute \src "libresoc.v:159527.18-159527.103" - wire $and$libresoc.v:159527$8615_Y - attribute \src "libresoc.v:159528.17-159528.135" - wire $and$libresoc.v:159528$8616_Y - attribute \src "libresoc.v:159531.18-159531.103" - wire $and$libresoc.v:159531$8619_Y - attribute \src "libresoc.v:159498.18-159498.109" - wire width 4 $extend$libresoc.v:159498$8584_Y - attribute \src "libresoc.v:159499.18-159499.109" - wire width 4 $extend$libresoc.v:159499$8586_Y - attribute \src "libresoc.v:159510.18-159510.112" - wire width 8 $mul$libresoc.v:159510$8598_Y - attribute \src "libresoc.v:159516.18-159516.112" - wire width 8 $mul$libresoc.v:159516$8604_Y - attribute \src "libresoc.v:159491.17-159491.103" - wire $not$libresoc.v:159491$8577_Y - attribute \src "libresoc.v:159493.18-159493.94" - wire $not$libresoc.v:159493$8579_Y - attribute \src "libresoc.v:159495.18-159495.94" - wire $not$libresoc.v:159495$8581_Y - attribute \src "libresoc.v:159505.18-159505.102" - wire $not$libresoc.v:159505$8593_Y - attribute \src "libresoc.v:159508.18-159508.97" - wire $not$libresoc.v:159508$8596_Y - attribute \src "libresoc.v:159514.18-159514.102" - wire $not$libresoc.v:159514$8602_Y - attribute \src "libresoc.v:159517.17-159517.103" - wire $not$libresoc.v:159517$8605_Y - attribute \src "libresoc.v:159524.18-159524.101" - wire $not$libresoc.v:159524$8612_Y - attribute \src "libresoc.v:159525.18-159525.111" - wire $not$libresoc.v:159525$8613_Y - attribute \src "libresoc.v:159526.18-159526.110" - wire $not$libresoc.v:159526$8614_Y - attribute \src "libresoc.v:159529.18-159529.102" - wire $not$libresoc.v:159529$8617_Y - attribute \src "libresoc.v:159530.18-159530.102" - wire $not$libresoc.v:159530$8618_Y - attribute \src "libresoc.v:159506.18-159506.111" - wire $or$libresoc.v:159506$8594_Y - attribute \src "libresoc.v:159507.17-159507.130" - wire $or$libresoc.v:159507$8595_Y - attribute \src "libresoc.v:159520.18-159520.130" - wire $or$libresoc.v:159520$8608_Y - attribute \src "libresoc.v:159522.18-159522.130" - wire $or$libresoc.v:159522$8610_Y - attribute \src "libresoc.v:159498.18-159498.109" - wire width 4 $pos$libresoc.v:159498$8585_Y - attribute \src "libresoc.v:159499.18-159499.109" - wire width 4 $pos$libresoc.v:159499$8587_Y - attribute \src "libresoc.v:159518.18-159518.121" - wire width 319 $sshl$libresoc.v:159518$8606_Y - attribute \src "libresoc.v:159511.18-159511.106" - wire width 176 $sshr$libresoc.v:159511$8599_Y + attribute \src "libresoc.v:161618.3-161653.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "libresoc.v:161124.18-161124.115" + wire $and$libresoc.v:161124$8626_Y + attribute \src "libresoc.v:161126.18-161126.95" + wire $and$libresoc.v:161126$8628_Y + attribute \src "libresoc.v:161128.17-161128.138" + wire $and$libresoc.v:161128$8630_Y + attribute \src "libresoc.v:161129.18-161129.95" + wire $and$libresoc.v:161129$8631_Y + attribute \src "libresoc.v:161132.18-161132.136" + wire $and$libresoc.v:161132$8636_Y + attribute \src "libresoc.v:161133.18-161133.136" + wire $and$libresoc.v:161133$8637_Y + attribute \src "libresoc.v:161134.18-161134.136" + wire $and$libresoc.v:161134$8638_Y + attribute \src "libresoc.v:161135.18-161135.136" + wire $and$libresoc.v:161135$8639_Y + attribute \src "libresoc.v:161136.18-161136.136" + wire $and$libresoc.v:161136$8640_Y + attribute \src "libresoc.v:161141.18-161141.119" + wire width 176 $and$libresoc.v:161141$8645_Y + attribute \src "libresoc.v:161144.18-161144.136" + wire $and$libresoc.v:161144$8648_Y + attribute \src "libresoc.v:161145.18-161145.136" + wire $and$libresoc.v:161145$8649_Y + attribute \src "libresoc.v:161147.18-161147.139" + wire $and$libresoc.v:161147$8651_Y + attribute \src "libresoc.v:161151.18-161151.139" + wire $and$libresoc.v:161151$8655_Y + attribute \src "libresoc.v:161153.18-161153.114" + wire $and$libresoc.v:161153$8657_Y + attribute \src "libresoc.v:161155.18-161155.114" + wire $and$libresoc.v:161155$8659_Y + attribute \src "libresoc.v:161159.18-161159.103" + wire $and$libresoc.v:161159$8663_Y + attribute \src "libresoc.v:161160.17-161160.135" + wire $and$libresoc.v:161160$8664_Y + attribute \src "libresoc.v:161163.18-161163.103" + wire $and$libresoc.v:161163$8667_Y + attribute \src "libresoc.v:161130.18-161130.109" + wire width 4 $extend$libresoc.v:161130$8632_Y + attribute \src "libresoc.v:161131.18-161131.109" + wire width 4 $extend$libresoc.v:161131$8634_Y + attribute \src "libresoc.v:161142.18-161142.112" + wire width 8 $mul$libresoc.v:161142$8646_Y + attribute \src "libresoc.v:161148.18-161148.112" + wire width 8 $mul$libresoc.v:161148$8652_Y + attribute \src "libresoc.v:161123.17-161123.103" + wire $not$libresoc.v:161123$8625_Y + attribute \src "libresoc.v:161125.18-161125.94" + wire $not$libresoc.v:161125$8627_Y + attribute \src "libresoc.v:161127.18-161127.94" + wire $not$libresoc.v:161127$8629_Y + attribute \src "libresoc.v:161137.18-161137.102" + wire $not$libresoc.v:161137$8641_Y + attribute \src "libresoc.v:161140.18-161140.97" + wire $not$libresoc.v:161140$8644_Y + attribute \src "libresoc.v:161146.18-161146.102" + wire $not$libresoc.v:161146$8650_Y + attribute \src "libresoc.v:161149.17-161149.103" + wire $not$libresoc.v:161149$8653_Y + attribute \src "libresoc.v:161156.18-161156.101" + wire $not$libresoc.v:161156$8660_Y + attribute \src "libresoc.v:161157.18-161157.111" + wire $not$libresoc.v:161157$8661_Y + attribute \src "libresoc.v:161158.18-161158.110" + wire $not$libresoc.v:161158$8662_Y + attribute \src "libresoc.v:161161.18-161161.102" + wire $not$libresoc.v:161161$8665_Y + attribute \src "libresoc.v:161162.18-161162.102" + wire $not$libresoc.v:161162$8666_Y + attribute \src "libresoc.v:161138.18-161138.111" + wire $or$libresoc.v:161138$8642_Y + attribute \src "libresoc.v:161139.17-161139.130" + wire $or$libresoc.v:161139$8643_Y + attribute \src "libresoc.v:161152.18-161152.130" + wire $or$libresoc.v:161152$8656_Y + attribute \src "libresoc.v:161154.18-161154.130" + wire $or$libresoc.v:161154$8658_Y + attribute \src "libresoc.v:161130.18-161130.109" + wire width 4 $pos$libresoc.v:161130$8633_Y + attribute \src "libresoc.v:161131.18-161131.109" + wire width 4 $pos$libresoc.v:161131$8635_Y + attribute \src "libresoc.v:161150.18-161150.121" + wire width 319 $sshl$libresoc.v:161150$8654_Y + attribute \src "libresoc.v:161143.18-161143.106" + wire width 176 $sshr$libresoc.v:161143$8647_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -331743,9 +334240,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -331757,7 +334254,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:159246.7-159246.15" + attribute \src "libresoc.v:160878.7-160878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -331876,7 +334373,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:159492$8578 + cell $and $and$libresoc.v:161124$8626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331884,10 +334381,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:159492$8578_Y + connect \Y $and$libresoc.v:161124$8626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159494$8580 + cell $and $and$libresoc.v:161126$8628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331895,10 +334392,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:159494$8580_Y + connect \Y $and$libresoc.v:161126$8628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159496$8582 + cell $and $and$libresoc.v:161128$8630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331906,10 +334403,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159496$8582_Y + connect \Y $and$libresoc.v:161128$8630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159497$8583 + cell $and $and$libresoc.v:161129$8631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331917,10 +334414,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:159497$8583_Y + connect \Y $and$libresoc.v:161129$8631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159500$8588 + cell $and $and$libresoc.v:161132$8636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331928,10 +334425,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159500$8588_Y + connect \Y $and$libresoc.v:161132$8636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159501$8589 + cell $and $and$libresoc.v:161133$8637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331939,10 +334436,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159501$8589_Y + connect \Y $and$libresoc.v:161133$8637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159502$8590 + cell $and $and$libresoc.v:161134$8638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331950,10 +334447,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159502$8590_Y + connect \Y $and$libresoc.v:161134$8638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159503$8591 + cell $and $and$libresoc.v:161135$8639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331961,10 +334458,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159503$8591_Y + connect \Y $and$libresoc.v:161135$8639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159504$8592 + cell $and $and$libresoc.v:161136$8640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331972,10 +334469,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159504$8592_Y + connect \Y $and$libresoc.v:161136$8640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:159509$8597 + cell $and $and$libresoc.v:161141$8645 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -331983,10 +334480,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:159509$8597_Y + connect \Y $and$libresoc.v:161141$8645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159512$8600 + cell $and $and$libresoc.v:161144$8648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331994,10 +334491,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159512$8600_Y + connect \Y $and$libresoc.v:161144$8648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159513$8601 + cell $and $and$libresoc.v:161145$8649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332005,10 +334502,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159513$8601_Y + connect \Y $and$libresoc.v:161145$8649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159515$8603 + cell $and $and$libresoc.v:161147$8651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332016,10 +334513,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159515$8603_Y + connect \Y $and$libresoc.v:161147$8651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159519$8607 + cell $and $and$libresoc.v:161151$8655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332027,10 +334524,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159519$8607_Y + connect \Y $and$libresoc.v:161151$8655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:159521$8609 + cell $and $and$libresoc.v:161153$8657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332038,10 +334535,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:159521$8609_Y + connect \Y $and$libresoc.v:161153$8657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:159523$8611 + cell $and $and$libresoc.v:161155$8659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332049,10 +334546,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:159523$8611_Y + connect \Y $and$libresoc.v:161155$8659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:159527$8615 + cell $and $and$libresoc.v:161159$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332060,10 +334557,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:159527$8615_Y + connect \Y $and$libresoc.v:161159$8663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159528$8616 + cell $and $and$libresoc.v:161160$8664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332071,10 +334568,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159528$8616_Y + connect \Y $and$libresoc.v:161160$8664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159531$8619 + cell $and $and$libresoc.v:161163$8667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332082,26 +334579,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:159531$8619_Y + connect \Y $and$libresoc.v:161163$8667_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:159498$8584 + cell $pos $extend$libresoc.v:161130$8632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:159498$8584_Y + connect \Y $extend$libresoc.v:161130$8632_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:159499$8586 + cell $pos $extend$libresoc.v:161131$8634 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:159499$8586_Y + connect \Y $extend$libresoc.v:161131$8634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:159510$8598 + cell $mul $mul$libresoc.v:161142$8646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -332109,10 +334606,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:159510$8598_Y + connect \Y $mul$libresoc.v:161142$8646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:159516$8604 + cell $mul $mul$libresoc.v:161148$8652 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -332120,106 +334617,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:159516$8604_Y + connect \Y $mul$libresoc.v:161148$8652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:159491$8577 + cell $not $not$libresoc.v:161123$8625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:159491$8577_Y + connect \Y $not$libresoc.v:161123$8625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159493$8579 + cell $not $not$libresoc.v:161125$8627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:159493$8579_Y + connect \Y $not$libresoc.v:161125$8627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159495$8581 + cell $not $not$libresoc.v:161127$8629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:159495$8581_Y + connect \Y $not$libresoc.v:161127$8629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:159505$8593 + cell $not $not$libresoc.v:161137$8641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:159505$8593_Y + connect \Y $not$libresoc.v:161137$8641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:159508$8596 + cell $not $not$libresoc.v:161140$8644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:159508$8596_Y + connect \Y $not$libresoc.v:161140$8644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:159514$8602 + cell $not $not$libresoc.v:161146$8650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:159514$8602_Y + connect \Y $not$libresoc.v:161146$8650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:159517$8605 + cell $not $not$libresoc.v:161149$8653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:159517$8605_Y + connect \Y $not$libresoc.v:161149$8653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:159524$8612 + cell $not $not$libresoc.v:161156$8660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:159524$8612_Y + connect \Y $not$libresoc.v:161156$8660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:159525$8613 + cell $not $not$libresoc.v:161157$8661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:159525$8613_Y + connect \Y $not$libresoc.v:161157$8661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:159526$8614 + cell $not $not$libresoc.v:161158$8662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:159526$8614_Y + connect \Y $not$libresoc.v:161158$8662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:159529$8617 + cell $not $not$libresoc.v:161161$8665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:159529$8617_Y + connect \Y $not$libresoc.v:161161$8665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159530$8618 + cell $not $not$libresoc.v:161162$8666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:159530$8618_Y + connect \Y $not$libresoc.v:161162$8666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:159506$8594 + cell $or $or$libresoc.v:161138$8642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332227,10 +334724,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:159506$8594_Y + connect \Y $or$libresoc.v:161138$8642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:159507$8595 + cell $or $or$libresoc.v:161139$8643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332238,10 +334735,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159507$8595_Y + connect \Y $or$libresoc.v:161139$8643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:159520$8608 + cell $or $or$libresoc.v:161152$8656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332249,10 +334746,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159520$8608_Y + connect \Y $or$libresoc.v:161152$8656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:159522$8610 + cell $or $or$libresoc.v:161154$8658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332260,26 +334757,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159522$8610_Y + connect \Y $or$libresoc.v:161154$8658_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:159498$8585 + cell $pos $pos$libresoc.v:161130$8633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:159498$8584_Y - connect \Y $pos$libresoc.v:159498$8585_Y + connect \A $extend$libresoc.v:161130$8632_Y + connect \Y $pos$libresoc.v:161130$8633_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:159499$8587 + cell $pos $pos$libresoc.v:161131$8635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:159499$8586_Y - connect \Y $pos$libresoc.v:159499$8587_Y + connect \A $extend$libresoc.v:161131$8634_Y + connect \Y $pos$libresoc.v:161131$8635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:159518$8606 + cell $sshl $sshl$libresoc.v:161150$8654 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -332287,10 +334784,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:159518$8606_Y + connect \Y $sshl$libresoc.v:161150$8654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:159511$8599 + cell $sshr $sshr$libresoc.v:161143$8647 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -332298,10 +334795,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:159511$8599_Y + connect \Y $sshr$libresoc.v:161143$8647_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:159548.11-159555.4" + attribute \src "libresoc.v:161180.11-161187.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332311,7 +334808,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:159556.10-159562.4" + attribute \src "libresoc.v:161188.10-161194.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332320,7 +334817,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:159563.9-159569.4" + attribute \src "libresoc.v:161195.9-161201.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332329,7 +334826,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:159570.13-159576.4" + attribute \src "libresoc.v:161202.13-161208.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332338,7 +334835,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:159577.10-159582.4" + attribute \src "libresoc.v:161209.10-161214.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -332346,7 +334843,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:159583.11-159589.4" + attribute \src "libresoc.v:161215.11-161221.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332355,7 +334852,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:159590.13-159596.4" + attribute \src "libresoc.v:161222.13-161228.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332364,7 +334861,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:159597.11-159603.4" + attribute \src "libresoc.v:161229.11-161235.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332373,7 +334870,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:159604.11-159610.4" + attribute \src "libresoc.v:161236.11-161242.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332381,143 +334878,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:159246.7-159246.20" - process $proc$libresoc.v:159246$8674 + attribute \src "libresoc.v:160878.7-160878.20" + process $proc$libresoc.v:160878$8722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159340.7-159340.34" - process $proc$libresoc.v:159340$8675 + attribute \src "libresoc.v:160972.7-160972.34" + process $proc$libresoc.v:160972$8723 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:159344.7-159344.24" - process $proc$libresoc.v:159344$8676 + attribute \src "libresoc.v:160976.7-160976.24" + process $proc$libresoc.v:160976$8724 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:159366.13-159366.29" - process $proc$libresoc.v:159366$8677 + attribute \src "libresoc.v:160998.13-160998.29" + process $proc$libresoc.v:160998$8725 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:159380.7-159380.21" - process $proc$libresoc.v:159380$8678 + attribute \src "libresoc.v:161012.7-161012.21" + process $proc$libresoc.v:161012$8726 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:159423.7-159423.29" - process $proc$libresoc.v:159423$8679 + attribute \src "libresoc.v:161055.7-161055.29" + process $proc$libresoc.v:161055$8727 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:159435.7-159435.25" - process $proc$libresoc.v:159435$8680 + attribute \src "libresoc.v:161067.7-161067.25" + process $proc$libresoc.v:161067$8728 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:159455.7-159455.31" - process $proc$libresoc.v:159455$8681 + attribute \src "libresoc.v:161087.7-161087.31" + process $proc$libresoc.v:161087$8729 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:159463.7-159463.21" - process $proc$libresoc.v:159463$8682 + attribute \src "libresoc.v:161095.7-161095.21" + process $proc$libresoc.v:161095$8730 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:159532.3-159533.47" - process $proc$libresoc.v:159532$8620 + attribute \src "libresoc.v:161164.3-161165.47" + process $proc$libresoc.v:161164$8668 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:159534.3-159535.35" - process $proc$libresoc.v:159534$8621 + attribute \src "libresoc.v:161166.3-161167.35" + process $proc$libresoc.v:161166$8669 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:159536.3-159537.36" - process $proc$libresoc.v:159536$8622 + attribute \src "libresoc.v:161168.3-161169.36" + process $proc$libresoc.v:161168$8670 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:159538.3-159539.35" - process $proc$libresoc.v:159538$8623 + attribute \src "libresoc.v:161170.3-161171.35" + process $proc$libresoc.v:161170$8671 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:159540.3-159541.35" - process $proc$libresoc.v:159540$8624 + attribute \src "libresoc.v:161172.3-161173.35" + process $proc$libresoc.v:161172$8672 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:159542.3-159543.37" - process $proc$libresoc.v:159542$8625 + attribute \src "libresoc.v:161174.3-161175.37" + process $proc$libresoc.v:161174$8673 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:159544.3-159545.57" - process $proc$libresoc.v:159544$8626 + attribute \src "libresoc.v:161176.3-161177.57" + process $proc$libresoc.v:161176$8674 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:159546.3-159547.51" - process $proc$libresoc.v:159546$8627 + attribute \src "libresoc.v:161178.3-161179.51" + process $proc$libresoc.v:161178$8675 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:159611.3-159625.6" - process $proc$libresoc.v:159611$8628 + attribute \src "libresoc.v:161243.3-161257.6" + process $proc$libresoc.v:161243$8676 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8629 $2\st_done_s_st_done$next[0:0]$8631 - attribute \src "libresoc.v:159612.5-159612.29" + assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 + attribute \src "libresoc.v:161244.5-161244.29" switch \initial - attribute \src "libresoc.v:159612.9-159612.17" + attribute \src "libresoc.v:161244.9-161244.17" case 1'1 case end @@ -332526,30 +335023,30 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8630 1'1 + assign $1\st_done_s_st_done$next[0:0]$8678 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8630 1'0 + assign $1\st_done_s_st_done$next[0:0]$8678 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8631 1'0 + assign $2\st_done_s_st_done$next[0:0]$8679 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8631 $1\st_done_s_st_done$next[0:0]$8630 + assign $2\st_done_s_st_done$next[0:0]$8679 $1\st_done_s_st_done$next[0:0]$8678 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8629 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 end - attribute \src "libresoc.v:159626.3-159635.6" - process $proc$libresoc.v:159626$8632 + attribute \src "libresoc.v:161258.3-161267.6" + process $proc$libresoc.v:161258$8680 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159627.5-159627.29" + attribute \src "libresoc.v:161259.5-161259.29" switch \initial - attribute \src "libresoc.v:159627.9-159627.17" + attribute \src "libresoc.v:161259.9-161259.17" case 1'1 case end @@ -332565,14 +335062,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:159636.3-159644.6" - process $proc$libresoc.v:159636$8633 + attribute \src "libresoc.v:161268.3-161276.6" + process $proc$libresoc.v:161268$8681 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8634 $1\busy_delay$next[0:0]$8635 - attribute \src "libresoc.v:159637.5-159637.29" + assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 + attribute \src "libresoc.v:161269.5-161269.29" switch \initial - attribute \src "libresoc.v:159637.9-159637.17" + attribute \src "libresoc.v:161269.9-161269.17" case 1'1 case end @@ -332581,21 +335078,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8635 1'0 + assign $1\busy_delay$next[0:0]$8683 1'0 case - assign $1\busy_delay$next[0:0]$8635 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8683 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8634 + update \busy_delay$next $0\busy_delay$next[0:0]$8682 end - attribute \src "libresoc.v:159645.3-159654.6" - process $proc$libresoc.v:159645$8636 + attribute \src "libresoc.v:161277.3-161286.6" + process $proc$libresoc.v:161277$8684 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159646.5-159646.29" + attribute \src "libresoc.v:161278.5-161278.29" switch \initial - attribute \src "libresoc.v:159646.9-159646.17" + attribute \src "libresoc.v:161278.9-161278.17" case 1'1 case end @@ -332611,15 +335108,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:159655.3-159670.6" - process $proc$libresoc.v:159655$8637 + attribute \src "libresoc.v:161287.3-161302.6" + process $proc$libresoc.v:161287$8685 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:159656.5-159656.29" + attribute \src "libresoc.v:161288.5-161288.29" switch \initial - attribute \src "libresoc.v:159656.9-159656.17" + attribute \src "libresoc.v:161288.9-161288.17" case 1'1 case end @@ -332644,15 +335141,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:159671.3-159686.6" - process $proc$libresoc.v:159671$8638 + attribute \src "libresoc.v:161303.3-161318.6" + process $proc$libresoc.v:161303$8686 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159672.5-159672.29" + attribute \src "libresoc.v:161304.5-161304.29" switch \initial - attribute \src "libresoc.v:159672.9-159672.17" + attribute \src "libresoc.v:161304.9-161304.17" case 1'1 case end @@ -332677,15 +335174,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:159687.3-159712.6" - process $proc$libresoc.v:159687$8639 + attribute \src "libresoc.v:161319.3-161344.6" + process $proc$libresoc.v:161319$8687 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159688.5-159688.29" + attribute \src "libresoc.v:161320.5-161320.29" switch \initial - attribute \src "libresoc.v:159688.9-159688.17" + attribute \src "libresoc.v:161320.9-161320.17" case 1'1 case end @@ -332728,15 +335225,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:159713.3-159738.6" - process $proc$libresoc.v:159713$8640 + attribute \src "libresoc.v:161345.3-161370.6" + process $proc$libresoc.v:161345$8688 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:159714.5-159714.29" + attribute \src "libresoc.v:161346.5-161346.29" switch \initial - attribute \src "libresoc.v:159714.9-159714.17" + attribute \src "libresoc.v:161346.9-161346.17" case 1'1 case end @@ -332779,15 +335276,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:159739.3-159764.6" - process $proc$libresoc.v:159739$8641 + attribute \src "libresoc.v:161371.3-161396.6" + process $proc$libresoc.v:161371$8689 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:159740.5-159740.29" + attribute \src "libresoc.v:161372.5-161372.29" switch \initial - attribute \src "libresoc.v:159740.9-159740.17" + attribute \src "libresoc.v:161372.9-161372.17" case 1'1 case end @@ -332830,15 +335327,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:159765.3-159795.6" - process $proc$libresoc.v:159765$8642 + attribute \src "libresoc.v:161397.3-161427.6" + process $proc$libresoc.v:161397$8690 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159766.5-159766.29" + attribute \src "libresoc.v:161398.5-161398.29" switch \initial - attribute \src "libresoc.v:159766.9-159766.17" + attribute \src "libresoc.v:161398.9-161398.17" case 1'1 case end @@ -332890,15 +335387,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:159796.3-159811.6" - process $proc$libresoc.v:159796$8643 + attribute \src "libresoc.v:161428.3-161443.6" + process $proc$libresoc.v:161428$8691 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159797.5-159797.29" + attribute \src "libresoc.v:161429.5-161429.29" switch \initial - attribute \src "libresoc.v:159797.9-159797.17" + attribute \src "libresoc.v:161429.9-161429.17" case 1'1 case end @@ -332923,14 +335420,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:159812.3-159821.6" - process $proc$libresoc.v:159812$8644 + attribute \src "libresoc.v:161444.3-161453.6" + process $proc$libresoc.v:161444$8692 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159813.5-159813.29" + attribute \src "libresoc.v:161445.5-161445.29" switch \initial - attribute \src "libresoc.v:159813.9-159813.17" + attribute \src "libresoc.v:161445.9-161445.17" case 1'1 case end @@ -332946,14 +335443,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:159822.3-159831.6" - process $proc$libresoc.v:159822$8645 + attribute \src "libresoc.v:161454.3-161463.6" + process $proc$libresoc.v:161454$8693 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159823.5-159823.29" + attribute \src "libresoc.v:161455.5-161455.29" switch \initial - attribute \src "libresoc.v:159823.9-159823.17" + attribute \src "libresoc.v:161455.9-161455.17" case 1'1 case end @@ -332969,14 +335466,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:159832.3-159841.6" - process $proc$libresoc.v:159832$8646 + attribute \src "libresoc.v:161464.3-161473.6" + process $proc$libresoc.v:161464$8694 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159833.5-159833.29" + attribute \src "libresoc.v:161465.5-161465.29" switch \initial - attribute \src "libresoc.v:159833.9-159833.17" + attribute \src "libresoc.v:161465.9-161465.17" case 1'1 case end @@ -332992,14 +335489,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:159842.3-159851.6" - process $proc$libresoc.v:159842$8647 + attribute \src "libresoc.v:161474.3-161483.6" + process $proc$libresoc.v:161474$8695 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159843.5-159843.29" + attribute \src "libresoc.v:161475.5-161475.29" switch \initial - attribute \src "libresoc.v:159843.9-159843.17" + attribute \src "libresoc.v:161475.9-161475.17" case 1'1 case end @@ -333015,14 +335512,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:159852.3-159861.6" - process $proc$libresoc.v:159852$8648 + attribute \src "libresoc.v:161484.3-161493.6" + process $proc$libresoc.v:161484$8696 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:159853.5-159853.29" + attribute \src "libresoc.v:161485.5-161485.29" switch \initial - attribute \src "libresoc.v:159853.9-159853.17" + attribute \src "libresoc.v:161485.9-161485.17" case 1'1 case end @@ -333038,14 +335535,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:159862.3-159871.6" - process $proc$libresoc.v:159862$8649 + attribute \src "libresoc.v:161494.3-161503.6" + process $proc$libresoc.v:161494$8697 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:159863.5-159863.29" + attribute \src "libresoc.v:161495.5-161495.29" switch \initial - attribute \src "libresoc.v:159863.9-159863.17" + attribute \src "libresoc.v:161495.9-161495.17" case 1'1 case end @@ -333061,14 +335558,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:159872.3-159891.6" - process $proc$libresoc.v:159872$8650 + attribute \src "libresoc.v:161504.3-161523.6" + process $proc$libresoc.v:161504$8698 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:159873.5-159873.29" + attribute \src "libresoc.v:161505.5-161505.29" switch \initial - attribute \src "libresoc.v:159873.9-159873.17" + attribute \src "libresoc.v:161505.9-161505.17" case 1'1 case end @@ -333097,15 +335594,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:159892.3-159930.6" - process $proc$libresoc.v:159892$8651 + attribute \src "libresoc.v:161524.3-161562.6" + process $proc$libresoc.v:161524$8699 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8652 $5\fsm_state$next[1:0]$8657 - attribute \src "libresoc.v:159893.5-159893.29" + assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 + attribute \src "libresoc.v:161525.5-161525.29" switch \initial - attribute \src "libresoc.v:159893.9-159893.17" + attribute \src "libresoc.v:161525.9-161525.17" case 1'1 case end @@ -333114,65 +335611,65 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $2\fsm_state$next[1:0]$8654 + assign $1\fsm_state$next[1:0]$8701 $2\fsm_state$next[1:0]$8702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8654 2'01 + assign $2\fsm_state$next[1:0]$8702 2'01 case - assign $2\fsm_state$next[1:0]$8654 \fsm_state + assign $2\fsm_state$next[1:0]$8702 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $3\fsm_state$next[1:0]$8655 + assign $1\fsm_state$next[1:0]$8701 $3\fsm_state$next[1:0]$8703 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8655 2'10 + assign $3\fsm_state$next[1:0]$8703 2'10 case - assign $3\fsm_state$next[1:0]$8655 \fsm_state + assign $3\fsm_state$next[1:0]$8703 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $4\fsm_state$next[1:0]$8656 + assign $1\fsm_state$next[1:0]$8701 $4\fsm_state$next[1:0]$8704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8656 2'00 + assign $4\fsm_state$next[1:0]$8704 2'00 case - assign $4\fsm_state$next[1:0]$8656 \fsm_state + assign $4\fsm_state$next[1:0]$8704 \fsm_state end case - assign $1\fsm_state$next[1:0]$8653 \fsm_state + assign $1\fsm_state$next[1:0]$8701 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8657 2'00 + assign $5\fsm_state$next[1:0]$8705 2'00 case - assign $5\fsm_state$next[1:0]$8657 $1\fsm_state$next[1:0]$8653 + assign $5\fsm_state$next[1:0]$8705 $1\fsm_state$next[1:0]$8701 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8652 + update \fsm_state$next $0\fsm_state$next[1:0]$8700 end - attribute \src "libresoc.v:159931.3-159940.6" - process $proc$libresoc.v:159931$8658 + attribute \src "libresoc.v:161563.3-161572.6" + process $proc$libresoc.v:161563$8706 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159932.5-159932.29" + attribute \src "libresoc.v:161564.5-161564.29" switch \initial - attribute \src "libresoc.v:159932.9-159932.17" + attribute \src "libresoc.v:161564.9-161564.17" case 1'1 case end @@ -333188,14 +335685,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:159941.3-159949.6" - process $proc$libresoc.v:159941$8659 + attribute \src "libresoc.v:161573.3-161581.6" + process $proc$libresoc.v:161573$8707 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8660 $1\lsui_active_dly$next[0:0]$8661 - attribute \src "libresoc.v:159942.5-159942.29" + assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 + attribute \src "libresoc.v:161574.5-161574.29" switch \initial - attribute \src "libresoc.v:159942.9-159942.17" + attribute \src "libresoc.v:161574.9-161574.17" case 1'1 case end @@ -333204,21 +335701,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8661 1'0 + assign $1\lsui_active_dly$next[0:0]$8709 1'0 case - assign $1\lsui_active_dly$next[0:0]$8661 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8709 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8660 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 end - attribute \src "libresoc.v:159950.3-159959.6" - process $proc$libresoc.v:159950$8662 + attribute \src "libresoc.v:161582.3-161591.6" + process $proc$libresoc.v:161582$8710 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159951.5-159951.29" + attribute \src "libresoc.v:161583.5-161583.29" switch \initial - attribute \src "libresoc.v:159951.9-159951.17" + attribute \src "libresoc.v:161583.9-161583.17" case 1'1 case end @@ -333234,14 +335731,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:159960.3-159969.6" - process $proc$libresoc.v:159960$8663 + attribute \src "libresoc.v:161592.3-161601.6" + process $proc$libresoc.v:161592$8711 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159961.5-159961.29" + attribute \src "libresoc.v:161593.5-161593.29" switch \initial - attribute \src "libresoc.v:159961.9-159961.17" + attribute \src "libresoc.v:161593.9-161593.17" case 1'1 case end @@ -333257,15 +335754,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:159970.3-159985.6" - process $proc$libresoc.v:159970$8664 + attribute \src "libresoc.v:161602.3-161617.6" + process $proc$libresoc.v:161602$8712 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159971.5-159971.29" + attribute \src "libresoc.v:161603.5-161603.29" switch \initial - attribute \src "libresoc.v:159971.9-159971.17" + attribute \src "libresoc.v:161603.9-161603.17" case 1'1 case end @@ -333290,16 +335787,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:159986.3-160021.6" - process $proc$libresoc.v:159986$8665 + attribute \src "libresoc.v:161618.3-161653.6" + process $proc$libresoc.v:161618$8713 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8666 $6\adrok_l_s_addr_acked$next[0:0]$8672 - attribute \src "libresoc.v:159987.5-159987.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "libresoc.v:161619.5-161619.29" switch \initial - attribute \src "libresoc.v:159987.9-159987.17" + attribute \src "libresoc.v:161619.9-161619.17" case 1'1 case end @@ -333308,67 +335805,67 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8667 $2\adrok_l_s_addr_acked$next[0:0]$8668 + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 $2\adrok_l_s_addr_acked$next[0:0]$8716 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8667 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $4\adrok_l_s_addr_acked$next[0:0]$8670 + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $4\adrok_l_s_addr_acked$next[0:0]$8718 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $5\adrok_l_s_addr_acked$next[0:0]$8671 + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $5\adrok_l_s_addr_acked$next[0:0]$8719 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8671 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8671 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8715 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $1\adrok_l_s_addr_acked$next[0:0]$8715 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $1\adrok_l_s_addr_acked$next[0:0]$8715 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8672 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8672 $3\adrok_l_s_addr_acked$next[0:0]$8669 + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 $3\adrok_l_s_addr_acked$next[0:0]$8717 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8666 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 end - attribute \src "libresoc.v:160022.3-160037.6" - process $proc$libresoc.v:160022$8673 + attribute \src "libresoc.v:161654.3-161669.6" + process $proc$libresoc.v:161654$8721 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:160023.5-160023.29" + attribute \src "libresoc.v:161655.5-161655.29" switch \initial - attribute \src "libresoc.v:160023.9-160023.17" + attribute \src "libresoc.v:161655.9-161655.17" case 1'1 case end @@ -333393,47 +335890,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:159491$8577_Y - connect \$11 $and$libresoc.v:159492$8578_Y - connect \$13 $not$libresoc.v:159493$8579_Y - connect \$15 $and$libresoc.v:159494$8580_Y - connect \$17 $not$libresoc.v:159495$8581_Y - connect \$1 $and$libresoc.v:159496$8582_Y - connect \$19 $and$libresoc.v:159497$8583_Y - connect \$21 $pos$libresoc.v:159498$8585_Y - connect \$23 $pos$libresoc.v:159499$8587_Y - connect \$25 $and$libresoc.v:159500$8588_Y - connect \$27 $and$libresoc.v:159501$8589_Y - connect \$29 $and$libresoc.v:159502$8590_Y - connect \$31 $and$libresoc.v:159503$8591_Y - connect \$33 $and$libresoc.v:159504$8592_Y - connect \$35 $not$libresoc.v:159505$8593_Y - connect \$38 $or$libresoc.v:159506$8594_Y - connect \$3 $or$libresoc.v:159507$8595_Y - connect \$37 $not$libresoc.v:159508$8596_Y - connect \$42 $and$libresoc.v:159509$8597_Y - connect \$44 $mul$libresoc.v:159510$8598_Y - connect \$46 $sshr$libresoc.v:159511$8599_Y - connect \$48 $and$libresoc.v:159512$8600_Y - connect \$50 $and$libresoc.v:159513$8601_Y - connect \$52 $not$libresoc.v:159514$8602_Y - connect \$54 $and$libresoc.v:159515$8603_Y - connect \$57 $mul$libresoc.v:159516$8604_Y - connect \$5 $not$libresoc.v:159517$8605_Y - connect \$59 $sshl$libresoc.v:159518$8606_Y - connect \$61 $and$libresoc.v:159519$8607_Y - connect \$63 $or$libresoc.v:159520$8608_Y - connect \$65 $and$libresoc.v:159521$8609_Y - connect \$67 $or$libresoc.v:159522$8610_Y - connect \$69 $and$libresoc.v:159523$8611_Y - connect \$71 $not$libresoc.v:159524$8612_Y - connect \$73 $not$libresoc.v:159525$8613_Y - connect \$75 $not$libresoc.v:159526$8614_Y - connect \$77 $and$libresoc.v:159527$8615_Y - connect \$7 $and$libresoc.v:159528$8616_Y - connect \$79 $not$libresoc.v:159529$8617_Y - connect \$81 $not$libresoc.v:159530$8618_Y - connect \$83 $and$libresoc.v:159531$8619_Y + connect \$9 $not$libresoc.v:161123$8625_Y + connect \$11 $and$libresoc.v:161124$8626_Y + connect \$13 $not$libresoc.v:161125$8627_Y + connect \$15 $and$libresoc.v:161126$8628_Y + connect \$17 $not$libresoc.v:161127$8629_Y + connect \$1 $and$libresoc.v:161128$8630_Y + connect \$19 $and$libresoc.v:161129$8631_Y + connect \$21 $pos$libresoc.v:161130$8633_Y + connect \$23 $pos$libresoc.v:161131$8635_Y + connect \$25 $and$libresoc.v:161132$8636_Y + connect \$27 $and$libresoc.v:161133$8637_Y + connect \$29 $and$libresoc.v:161134$8638_Y + connect \$31 $and$libresoc.v:161135$8639_Y + connect \$33 $and$libresoc.v:161136$8640_Y + connect \$35 $not$libresoc.v:161137$8641_Y + connect \$38 $or$libresoc.v:161138$8642_Y + connect \$3 $or$libresoc.v:161139$8643_Y + connect \$37 $not$libresoc.v:161140$8644_Y + connect \$42 $and$libresoc.v:161141$8645_Y + connect \$44 $mul$libresoc.v:161142$8646_Y + connect \$46 $sshr$libresoc.v:161143$8647_Y + connect \$48 $and$libresoc.v:161144$8648_Y + connect \$50 $and$libresoc.v:161145$8649_Y + connect \$52 $not$libresoc.v:161146$8650_Y + connect \$54 $and$libresoc.v:161147$8651_Y + connect \$57 $mul$libresoc.v:161148$8652_Y + connect \$5 $not$libresoc.v:161149$8653_Y + connect \$59 $sshl$libresoc.v:161150$8654_Y + connect \$61 $and$libresoc.v:161151$8655_Y + connect \$63 $or$libresoc.v:161152$8656_Y + connect \$65 $and$libresoc.v:161153$8657_Y + connect \$67 $or$libresoc.v:161154$8658_Y + connect \$69 $and$libresoc.v:161155$8659_Y + connect \$71 $not$libresoc.v:161156$8660_Y + connect \$73 $not$libresoc.v:161157$8661_Y + connect \$75 $not$libresoc.v:161158$8662_Y + connect \$77 $and$libresoc.v:161159$8663_Y + connect \$7 $and$libresoc.v:161160$8664_Y + connect \$79 $not$libresoc.v:161161$8665_Y + connect \$81 $not$libresoc.v:161162$8666_Y + connect \$83 $and$libresoc.v:161163$8667_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -333456,116 +335953,116 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:160063.1-160843.10" +attribute \src "libresoc.v:161695.1-162475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:160806.3-160824.6" - wire width 4 $0\cr_a$6$next[3:0]$8729 - attribute \src "libresoc.v:160670.3-160671.31" - wire width 4 $0\cr_a$6[3:0]$8685 - attribute \src "libresoc.v:160077.13-160077.28" - wire width 4 $0\cr_a$6[3:0]$8735 - attribute \src "libresoc.v:160806.3-160824.6" - wire $0\cr_a_ok$next[0:0]$8728 - attribute \src "libresoc.v:160672.3-160673.31" + attribute \src "libresoc.v:162438.3-162456.6" + wire width 4 $0\cr_a$6$next[3:0]$8777 + attribute \src "libresoc.v:162302.3-162303.31" + wire width 4 $0\cr_a$6[3:0]$8733 + attribute \src "libresoc.v:161709.13-161709.28" + wire width 4 $0\cr_a$6[3:0]$8783 + attribute \src "libresoc.v:162438.3-162456.6" + wire $0\cr_a_ok$next[0:0]$8776 + attribute \src "libresoc.v:162304.3-162305.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:160753.3-160767.6" - wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8709 - attribute \src "libresoc.v:160684.3-160685.51" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8695 - attribute \src "libresoc.v:160142.14-160142.43" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8738 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8710 - attribute \src "libresoc.v:160686.3-160687.45" - wire width 32 $0\cr_op__insn$4[31:0]$8697 - attribute \src "libresoc.v:160151.14-160151.37" - wire width 32 $0\cr_op__insn$4[31:0]$8740 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8711 - attribute \src "libresoc.v:160682.3-160683.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8693 - attribute \src "libresoc.v:160385.13-160385.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8742 - attribute \src "libresoc.v:160787.3-160805.6" - wire width 32 $0\full_cr$5$next[31:0]$8722 - attribute \src "libresoc.v:160674.3-160675.37" - wire width 32 $0\full_cr$5[31:0]$8688 - attribute \src "libresoc.v:160394.14-160394.33" - wire width 32 $0\full_cr$5[31:0]$8744 - attribute \src "libresoc.v:160787.3-160805.6" - wire $0\full_cr_ok$next[0:0]$8723 - attribute \src "libresoc.v:160676.3-160677.37" + attribute \src "libresoc.v:162385.3-162399.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 + attribute \src "libresoc.v:162316.3-162317.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 + attribute \src "libresoc.v:161774.14-161774.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8758 + attribute \src "libresoc.v:162318.3-162319.45" + wire width 32 $0\cr_op__insn$4[31:0]$8745 + attribute \src "libresoc.v:161783.14-161783.37" + wire width 32 $0\cr_op__insn$4[31:0]$8788 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8759 + attribute \src "libresoc.v:162314.3-162315.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8741 + attribute \src "libresoc.v:162017.13-162017.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8790 + attribute \src "libresoc.v:162419.3-162437.6" + wire width 32 $0\full_cr$5$next[31:0]$8770 + attribute \src "libresoc.v:162306.3-162307.37" + wire width 32 $0\full_cr$5[31:0]$8736 + attribute \src "libresoc.v:162026.14-162026.33" + wire width 32 $0\full_cr$5[31:0]$8792 + attribute \src "libresoc.v:162419.3-162437.6" + wire $0\full_cr_ok$next[0:0]$8771 + attribute \src "libresoc.v:162308.3-162309.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:160064.7-160064.20" + attribute \src "libresoc.v:161696.7-161696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160740.3-160752.6" - wire width 2 $0\muxid$1$next[1:0]$8706 - attribute \src "libresoc.v:160688.3-160689.33" - wire width 2 $0\muxid$1[1:0]$8699 - attribute \src "libresoc.v:160628.13-160628.29" + attribute \src "libresoc.v:162372.3-162384.6" + wire width 2 $0\muxid$1$next[1:0]$8754 + attribute \src "libresoc.v:162320.3-162321.33" wire width 2 $0\muxid$1[1:0]$8747 - attribute \src "libresoc.v:160768.3-160786.6" - wire width 64 $0\o$next[63:0]$8716 - attribute \src "libresoc.v:160678.3-160679.19" + attribute \src "libresoc.v:162260.13-162260.29" + wire width 2 $0\muxid$1[1:0]$8795 + attribute \src "libresoc.v:162400.3-162418.6" + wire width 64 $0\o$next[63:0]$8764 + attribute \src "libresoc.v:162310.3-162311.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160768.3-160786.6" - wire $0\o_ok$next[0:0]$8717 - attribute \src "libresoc.v:160680.3-160681.25" + attribute \src "libresoc.v:162400.3-162418.6" + wire $0\o_ok$next[0:0]$8765 + attribute \src "libresoc.v:162312.3-162313.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:160722.3-160739.6" - wire $0\r_busy$next[0:0]$8702 - attribute \src "libresoc.v:160690.3-160691.29" + attribute \src "libresoc.v:162354.3-162371.6" + wire $0\r_busy$next[0:0]$8750 + attribute \src "libresoc.v:162322.3-162323.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:160806.3-160824.6" - wire width 4 $1\cr_a$6$next[3:0]$8731 - attribute \src "libresoc.v:160806.3-160824.6" - wire $1\cr_a_ok$next[0:0]$8730 - attribute \src "libresoc.v:160082.7-160082.21" + attribute \src "libresoc.v:162438.3-162456.6" + wire width 4 $1\cr_a$6$next[3:0]$8779 + attribute \src "libresoc.v:162438.3-162456.6" + wire $1\cr_a_ok$next[0:0]$8778 + attribute \src "libresoc.v:161714.7-161714.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:160753.3-160767.6" - wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8712 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8713 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8714 - attribute \src "libresoc.v:160787.3-160805.6" - wire width 32 $1\full_cr$5$next[31:0]$8724 - attribute \src "libresoc.v:160787.3-160805.6" - wire $1\full_cr_ok$next[0:0]$8725 - attribute \src "libresoc.v:160399.7-160399.24" + attribute \src "libresoc.v:162385.3-162399.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8760 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8761 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8762 + attribute \src "libresoc.v:162419.3-162437.6" + wire width 32 $1\full_cr$5$next[31:0]$8772 + attribute \src "libresoc.v:162419.3-162437.6" + wire $1\full_cr_ok$next[0:0]$8773 + attribute \src "libresoc.v:162031.7-162031.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:160740.3-160752.6" - wire width 2 $1\muxid$1$next[1:0]$8707 - attribute \src "libresoc.v:160768.3-160786.6" - wire width 64 $1\o$next[63:0]$8718 - attribute \src "libresoc.v:160641.14-160641.38" + attribute \src "libresoc.v:162372.3-162384.6" + wire width 2 $1\muxid$1$next[1:0]$8755 + attribute \src "libresoc.v:162400.3-162418.6" + wire width 64 $1\o$next[63:0]$8766 + attribute \src "libresoc.v:162273.14-162273.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160768.3-160786.6" - wire $1\o_ok$next[0:0]$8719 - attribute \src "libresoc.v:160648.7-160648.18" + attribute \src "libresoc.v:162400.3-162418.6" + wire $1\o_ok$next[0:0]$8767 + attribute \src "libresoc.v:162280.7-162280.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:160722.3-160739.6" - wire $1\r_busy$next[0:0]$8703 - attribute \src "libresoc.v:160662.7-160662.20" + attribute \src "libresoc.v:162354.3-162371.6" + wire $1\r_busy$next[0:0]$8751 + attribute \src "libresoc.v:162294.7-162294.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:160806.3-160824.6" - wire $2\cr_a_ok$next[0:0]$8732 - attribute \src "libresoc.v:160787.3-160805.6" - wire $2\full_cr_ok$next[0:0]$8726 - attribute \src "libresoc.v:160768.3-160786.6" - wire $2\o_ok$next[0:0]$8720 - attribute \src "libresoc.v:160722.3-160739.6" - wire $2\r_busy$next[0:0]$8704 - attribute \src "libresoc.v:160669.18-160669.118" - wire $and$libresoc.v:160669$8683_Y + attribute \src "libresoc.v:162438.3-162456.6" + wire $2\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:162419.3-162437.6" + wire $2\full_cr_ok$next[0:0]$8774 + attribute \src "libresoc.v:162400.3-162418.6" + wire $2\o_ok$next[0:0]$8768 + attribute \src "libresoc.v:162354.3-162371.6" + wire $2\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:162301.18-162301.118" + wire $and$libresoc.v:162301$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a @@ -333893,7 +336390,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:160064.7-160064.15" + attribute \src "libresoc.v:161696.7-161696.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -334158,7 +336655,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:160669$8683 + cell $and $and$libresoc.v:162301$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334166,10 +336663,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:160669$8683_Y + connect \Y $and$libresoc.v:162301$8731_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:160692.12-160713.4" + attribute \src "libresoc.v:162324.12-162345.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -334193,199 +336690,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:160714.9-160717.4" + attribute \src "libresoc.v:162346.9-162349.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:160718.9-160721.4" + attribute \src "libresoc.v:162350.9-162353.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160064.7-160064.20" - process $proc$libresoc.v:160064$8733 + attribute \src "libresoc.v:161696.7-161696.20" + process $proc$libresoc.v:161696$8781 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160077.13-160077.28" - process $proc$libresoc.v:160077$8734 + attribute \src "libresoc.v:161709.13-161709.28" + process $proc$libresoc.v:161709$8782 assign { } { } - assign $0\cr_a$6[3:0]$8735 4'0000 + assign $0\cr_a$6[3:0]$8783 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8735 + update \cr_a$6 $0\cr_a$6[3:0]$8783 end - attribute \src "libresoc.v:160082.7-160082.21" - process $proc$libresoc.v:160082$8736 + attribute \src "libresoc.v:161714.7-161714.21" + process $proc$libresoc.v:161714$8784 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:160142.14-160142.43" - process $proc$libresoc.v:160142$8737 + attribute \src "libresoc.v:161774.14-161774.43" + process $proc$libresoc.v:161774$8785 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8738 14'00000000000000 + assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8738 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 end - attribute \src "libresoc.v:160151.14-160151.37" - process $proc$libresoc.v:160151$8739 + attribute \src "libresoc.v:161783.14-161783.37" + process $proc$libresoc.v:161783$8787 assign { } { } - assign $0\cr_op__insn$4[31:0]$8740 0 + assign $0\cr_op__insn$4[31:0]$8788 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8740 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 end - attribute \src "libresoc.v:160385.13-160385.41" - process $proc$libresoc.v:160385$8741 + attribute \src "libresoc.v:162017.13-162017.41" + process $proc$libresoc.v:162017$8789 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8742 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8742 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 end - attribute \src "libresoc.v:160394.14-160394.33" - process $proc$libresoc.v:160394$8743 + attribute \src "libresoc.v:162026.14-162026.33" + process $proc$libresoc.v:162026$8791 assign { } { } - assign $0\full_cr$5[31:0]$8744 0 + assign $0\full_cr$5[31:0]$8792 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8744 + update \full_cr$5 $0\full_cr$5[31:0]$8792 end - attribute \src "libresoc.v:160399.7-160399.24" - process $proc$libresoc.v:160399$8745 + attribute \src "libresoc.v:162031.7-162031.24" + process $proc$libresoc.v:162031$8793 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:160628.13-160628.29" - process $proc$libresoc.v:160628$8746 + attribute \src "libresoc.v:162260.13-162260.29" + process $proc$libresoc.v:162260$8794 assign { } { } - assign $0\muxid$1[1:0]$8747 2'00 + assign $0\muxid$1[1:0]$8795 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8747 + update \muxid$1 $0\muxid$1[1:0]$8795 end - attribute \src "libresoc.v:160641.14-160641.38" - process $proc$libresoc.v:160641$8748 + attribute \src "libresoc.v:162273.14-162273.38" + process $proc$libresoc.v:162273$8796 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:160648.7-160648.18" - process $proc$libresoc.v:160648$8749 + attribute \src "libresoc.v:162280.7-162280.18" + process $proc$libresoc.v:162280$8797 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:160662.7-160662.20" - process $proc$libresoc.v:160662$8750 + attribute \src "libresoc.v:162294.7-162294.20" + process $proc$libresoc.v:162294$8798 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:160670.3-160671.31" - process $proc$libresoc.v:160670$8684 + attribute \src "libresoc.v:162302.3-162303.31" + process $proc$libresoc.v:162302$8732 assign { } { } - assign $0\cr_a$6[3:0]$8685 \cr_a$6$next + assign $0\cr_a$6[3:0]$8733 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8685 + update \cr_a$6 $0\cr_a$6[3:0]$8733 end - attribute \src "libresoc.v:160672.3-160673.31" - process $proc$libresoc.v:160672$8686 + attribute \src "libresoc.v:162304.3-162305.31" + process $proc$libresoc.v:162304$8734 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:160674.3-160675.37" - process $proc$libresoc.v:160674$8687 + attribute \src "libresoc.v:162306.3-162307.37" + process $proc$libresoc.v:162306$8735 assign { } { } - assign $0\full_cr$5[31:0]$8688 \full_cr$5$next + assign $0\full_cr$5[31:0]$8736 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8688 + update \full_cr$5 $0\full_cr$5[31:0]$8736 end - attribute \src "libresoc.v:160676.3-160677.37" - process $proc$libresoc.v:160676$8689 + attribute \src "libresoc.v:162308.3-162309.37" + process $proc$libresoc.v:162308$8737 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:160678.3-160679.19" - process $proc$libresoc.v:160678$8690 + attribute \src "libresoc.v:162310.3-162311.19" + process $proc$libresoc.v:162310$8738 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:160680.3-160681.25" - process $proc$libresoc.v:160680$8691 + attribute \src "libresoc.v:162312.3-162313.25" + process $proc$libresoc.v:162312$8739 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:160682.3-160683.55" - process $proc$libresoc.v:160682$8692 + attribute \src "libresoc.v:162314.3-162315.55" + process $proc$libresoc.v:162314$8740 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8693 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8693 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 end - attribute \src "libresoc.v:160684.3-160685.51" - process $proc$libresoc.v:160684$8694 + attribute \src "libresoc.v:162316.3-162317.51" + process $proc$libresoc.v:162316$8742 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8695 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8695 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 end - attribute \src "libresoc.v:160686.3-160687.45" - process $proc$libresoc.v:160686$8696 + attribute \src "libresoc.v:162318.3-162319.45" + process $proc$libresoc.v:162318$8744 assign { } { } - assign $0\cr_op__insn$4[31:0]$8697 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8697 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 end - attribute \src "libresoc.v:160688.3-160689.33" - process $proc$libresoc.v:160688$8698 + attribute \src "libresoc.v:162320.3-162321.33" + process $proc$libresoc.v:162320$8746 assign { } { } - assign $0\muxid$1[1:0]$8699 \muxid$1$next + assign $0\muxid$1[1:0]$8747 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8699 + update \muxid$1 $0\muxid$1[1:0]$8747 end - attribute \src "libresoc.v:160690.3-160691.29" - process $proc$libresoc.v:160690$8700 + attribute \src "libresoc.v:162322.3-162323.29" + process $proc$libresoc.v:162322$8748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160722.3-160739.6" - process $proc$libresoc.v:160722$8701 + attribute \src "libresoc.v:162354.3-162371.6" + process $proc$libresoc.v:162354$8749 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8702 $2\r_busy$next[0:0]$8704 - attribute \src "libresoc.v:160723.5-160723.29" + assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:162355.5-162355.29" switch \initial - attribute \src "libresoc.v:160723.9-160723.17" + attribute \src "libresoc.v:162355.9-162355.17" case 1'1 case end @@ -334394,34 +336891,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8703 1'1 + assign $1\r_busy$next[0:0]$8751 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8703 1'0 + assign $1\r_busy$next[0:0]$8751 1'0 case - assign $1\r_busy$next[0:0]$8703 \r_busy + assign $1\r_busy$next[0:0]$8751 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8704 1'0 + assign $2\r_busy$next[0:0]$8752 1'0 case - assign $2\r_busy$next[0:0]$8704 $1\r_busy$next[0:0]$8703 + assign $2\r_busy$next[0:0]$8752 $1\r_busy$next[0:0]$8751 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8702 + update \r_busy$next $0\r_busy$next[0:0]$8750 end - attribute \src "libresoc.v:160740.3-160752.6" - process $proc$libresoc.v:160740$8705 + attribute \src "libresoc.v:162372.3-162384.6" + process $proc$libresoc.v:162372$8753 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8706 $1\muxid$1$next[1:0]$8707 - attribute \src "libresoc.v:160741.5-160741.29" + assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 + attribute \src "libresoc.v:162373.5-162373.29" switch \initial - attribute \src "libresoc.v:160741.9-160741.17" + attribute \src "libresoc.v:162373.9-162373.17" case 1'1 case end @@ -334430,31 +336927,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8707 \muxid$16 + assign $1\muxid$1$next[1:0]$8755 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8707 \muxid$16 + assign $1\muxid$1$next[1:0]$8755 \muxid$16 case - assign $1\muxid$1$next[1:0]$8707 \muxid$1 + assign $1\muxid$1$next[1:0]$8755 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8706 + update \muxid$1$next $0\muxid$1$next[1:0]$8754 end - attribute \src "libresoc.v:160753.3-160767.6" - process $proc$libresoc.v:160753$8708 + attribute \src "libresoc.v:162385.3-162399.6" + process $proc$libresoc.v:162385$8756 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[13:0]$8709 $1\cr_op__fn_unit$3$next[13:0]$8712 - assign $0\cr_op__insn$4$next[31:0]$8710 $1\cr_op__insn$4$next[31:0]$8713 - assign $0\cr_op__insn_type$2$next[6:0]$8711 $1\cr_op__insn_type$2$next[6:0]$8714 - attribute \src "libresoc.v:160754.5-160754.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 + assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 + assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 + attribute \src "libresoc.v:162386.5-162386.29" switch \initial - attribute \src "libresoc.v:160754.9-160754.17" + attribute \src "libresoc.v:162386.9-162386.17" case 1'1 case end @@ -334465,35 +336962,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[13:0]$8712 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8713 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8714 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[13:0]$8760 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8761 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8762 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8709 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8710 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8711 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8757 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 end - attribute \src "libresoc.v:160768.3-160786.6" - process $proc$libresoc.v:160768$8715 + attribute \src "libresoc.v:162400.3-162418.6" + process $proc$libresoc.v:162400$8763 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8716 $1\o$next[63:0]$8718 + assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 assign { } { } - assign $0\o_ok$next[0:0]$8717 $2\o_ok$next[0:0]$8720 - attribute \src "libresoc.v:160769.5-160769.29" + assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 + attribute \src "libresoc.v:162401.5-162401.29" switch \initial - attribute \src "libresoc.v:160769.9-160769.17" + attribute \src "libresoc.v:162401.9-162401.17" case 1'1 case end @@ -334503,41 +337000,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8718 \o - assign $1\o_ok$next[0:0]$8719 \o_ok + assign $1\o$next[63:0]$8766 \o + assign $1\o_ok$next[0:0]$8767 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8720 1'0 + assign $2\o_ok$next[0:0]$8768 1'0 case - assign $2\o_ok$next[0:0]$8720 $1\o_ok$next[0:0]$8719 + assign $2\o_ok$next[0:0]$8768 $1\o_ok$next[0:0]$8767 end sync always - update \o$next $0\o$next[63:0]$8716 - update \o_ok$next $0\o_ok$next[0:0]$8717 + update \o$next $0\o$next[63:0]$8764 + update \o_ok$next $0\o_ok$next[0:0]$8765 end - attribute \src "libresoc.v:160787.3-160805.6" - process $proc$libresoc.v:160787$8721 + attribute \src "libresoc.v:162419.3-162437.6" + process $proc$libresoc.v:162419$8769 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8722 $1\full_cr$5$next[31:0]$8724 + assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 assign { } { } - assign $0\full_cr_ok$next[0:0]$8723 $2\full_cr_ok$next[0:0]$8726 - attribute \src "libresoc.v:160788.5-160788.29" + assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 + attribute \src "libresoc.v:162420.5-162420.29" switch \initial - attribute \src "libresoc.v:160788.9-160788.17" + attribute \src "libresoc.v:162420.9-162420.17" case 1'1 case end @@ -334547,41 +337044,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8724 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8725 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8772 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8773 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8726 1'0 + assign $2\full_cr_ok$next[0:0]$8774 1'0 case - assign $2\full_cr_ok$next[0:0]$8726 $1\full_cr_ok$next[0:0]$8725 + assign $2\full_cr_ok$next[0:0]$8774 $1\full_cr_ok$next[0:0]$8773 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8722 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8723 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 end - attribute \src "libresoc.v:160806.3-160824.6" - process $proc$libresoc.v:160806$8727 + attribute \src "libresoc.v:162438.3-162456.6" + process $proc$libresoc.v:162438$8775 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8729 $1\cr_a$6$next[3:0]$8731 - assign $0\cr_a_ok$next[0:0]$8728 $2\cr_a_ok$next[0:0]$8732 - attribute \src "libresoc.v:160807.5-160807.29" + assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 + assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:162439.5-162439.29" switch \initial - attribute \src "libresoc.v:160807.9-160807.17" + attribute \src "libresoc.v:162439.9-162439.17" case 1'1 case end @@ -334591,30 +337088,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8730 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8731 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8778 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8779 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8732 1'0 + assign $2\cr_a_ok$next[0:0]$8780 1'0 case - assign $2\cr_a_ok$next[0:0]$8732 $1\cr_a_ok$next[0:0]$8730 + assign $2\cr_a_ok$next[0:0]$8780 $1\cr_a_ok$next[0:0]$8778 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8728 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8729 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 end - connect \$14 $and$libresoc.v:160669$8683_Y + connect \$14 $and$libresoc.v:162301$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -334634,155 +337131,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:160847.1-161707.10" +attribute \src "libresoc.v:162479.1-163339.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8787 - attribute \src "libresoc.v:161519.3-161520.43" - wire width 64 $0\br_op__cia$2[63:0]$8761 - attribute \src "libresoc.v:160855.14-160855.51" - wire width 64 $0\br_op__cia$2[63:0]$8825 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 14 $0\br_op__fn_unit$4$next[13:0]$8788 - attribute \src "libresoc.v:161523.3-161524.51" - wire width 14 $0\br_op__fn_unit$4[13:0]$8765 - attribute \src "libresoc.v:160911.14-160911.43" - wire width 14 $0\br_op__fn_unit$4[13:0]$8827 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8789 - attribute \src "libresoc.v:161527.3-161528.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8769 - attribute \src "libresoc.v:160920.14-160920.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8829 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8790 - attribute \src "libresoc.v:161529.3-161530.61" - wire $0\br_op__imm_data__ok$7[0:0]$8771 - attribute \src "libresoc.v:160929.7-160929.37" - wire $0\br_op__imm_data__ok$7[0:0]$8831 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8791 - attribute \src "libresoc.v:161525.3-161526.45" - wire width 32 $0\br_op__insn$5[31:0]$8767 - attribute \src "libresoc.v:160938.14-160938.37" - wire width 32 $0\br_op__insn$5[31:0]$8833 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8792 - attribute \src "libresoc.v:161521.3-161522.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8763 - attribute \src "libresoc.v:161172.13-161172.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8835 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__is_32bit$9$next[0:0]$8793 - attribute \src "libresoc.v:161533.3-161534.53" - wire $0\br_op__is_32bit$9[0:0]$8775 - attribute \src "libresoc.v:161181.7-161181.33" - wire $0\br_op__is_32bit$9[0:0]$8837 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__lk$8$next[0:0]$8794 - attribute \src "libresoc.v:161531.3-161532.41" - wire $0\br_op__lk$8[0:0]$8773 - attribute \src "libresoc.v:161190.7-161190.27" - wire $0\br_op__lk$8[0:0]$8839 - attribute \src "libresoc.v:161635.3-161653.6" - wire width 64 $0\fast1$10$next[63:0]$8806 - attribute \src "libresoc.v:161515.3-161516.35" - wire width 64 $0\fast1$10[63:0]$8758 - attribute \src "libresoc.v:161203.14-161203.47" - wire width 64 $0\fast1$10[63:0]$8841 - attribute \src "libresoc.v:161635.3-161653.6" - wire $0\fast1_ok$next[0:0]$8807 - attribute \src "libresoc.v:161517.3-161518.33" + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8835 + attribute \src "libresoc.v:163151.3-163152.43" + wire width 64 $0\br_op__cia$2[63:0]$8809 + attribute \src "libresoc.v:162487.14-162487.51" + wire width 64 $0\br_op__cia$2[63:0]$8873 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 + attribute \src "libresoc.v:163155.3-163156.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8813 + attribute \src "libresoc.v:162543.14-162543.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8875 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 + attribute \src "libresoc.v:163159.3-163160.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 + attribute \src "libresoc.v:162552.14-162552.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8838 + attribute \src "libresoc.v:163161.3-163162.61" + wire $0\br_op__imm_data__ok$7[0:0]$8819 + attribute \src "libresoc.v:162561.7-162561.37" + wire $0\br_op__imm_data__ok$7[0:0]$8879 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8839 + attribute \src "libresoc.v:163157.3-163158.45" + wire width 32 $0\br_op__insn$5[31:0]$8815 + attribute \src "libresoc.v:162570.14-162570.37" + wire width 32 $0\br_op__insn$5[31:0]$8881 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 + attribute \src "libresoc.v:163153.3-163154.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8811 + attribute \src "libresoc.v:162804.13-162804.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8883 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__is_32bit$9$next[0:0]$8841 + attribute \src "libresoc.v:163165.3-163166.53" + wire $0\br_op__is_32bit$9[0:0]$8823 + attribute \src "libresoc.v:162813.7-162813.33" + wire $0\br_op__is_32bit$9[0:0]$8885 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__lk$8$next[0:0]$8842 + attribute \src "libresoc.v:163163.3-163164.41" + wire $0\br_op__lk$8[0:0]$8821 + attribute \src "libresoc.v:162822.7-162822.27" + wire $0\br_op__lk$8[0:0]$8887 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $0\fast1$10$next[63:0]$8854 + attribute \src "libresoc.v:163147.3-163148.35" + wire width 64 $0\fast1$10[63:0]$8806 + attribute \src "libresoc.v:162835.14-162835.47" + wire width 64 $0\fast1$10[63:0]$8889 + attribute \src "libresoc.v:163267.3-163285.6" + wire $0\fast1_ok$next[0:0]$8855 + attribute \src "libresoc.v:163149.3-163150.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:161654.3-161672.6" - wire width 64 $0\fast2$11$next[63:0]$8812 - attribute \src "libresoc.v:161511.3-161512.35" - wire width 64 $0\fast2$11[63:0]$8755 - attribute \src "libresoc.v:161219.14-161219.47" - wire width 64 $0\fast2$11[63:0]$8844 - attribute \src "libresoc.v:161654.3-161672.6" - wire $0\fast2_ok$next[0:0]$8813 - attribute \src "libresoc.v:161513.3-161514.33" + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $0\fast2$11$next[63:0]$8860 + attribute \src "libresoc.v:163143.3-163144.35" + wire width 64 $0\fast2$11[63:0]$8803 + attribute \src "libresoc.v:162851.14-162851.47" + wire width 64 $0\fast2$11[63:0]$8892 + attribute \src "libresoc.v:163286.3-163304.6" + wire $0\fast2_ok$next[0:0]$8861 + attribute \src "libresoc.v:163145.3-163146.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:160848.7-160848.20" + attribute \src "libresoc.v:162480.7-162480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161594.3-161606.6" - wire width 2 $0\muxid$1$next[1:0]$8784 - attribute \src "libresoc.v:161535.3-161536.33" - wire width 2 $0\muxid$1[1:0]$8777 - attribute \src "libresoc.v:161469.13-161469.29" - wire width 2 $0\muxid$1[1:0]$8847 - attribute \src "libresoc.v:161673.3-161691.6" - wire width 64 $0\nia$next[63:0]$8818 - attribute \src "libresoc.v:161507.3-161508.23" + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $0\muxid$1$next[1:0]$8832 + attribute \src "libresoc.v:163167.3-163168.33" + wire width 2 $0\muxid$1[1:0]$8825 + attribute \src "libresoc.v:163101.13-163101.29" + wire width 2 $0\muxid$1[1:0]$8895 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $0\nia$next[63:0]$8866 + attribute \src "libresoc.v:163139.3-163140.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:161673.3-161691.6" - wire $0\nia_ok$next[0:0]$8819 - attribute \src "libresoc.v:161509.3-161510.29" + attribute \src "libresoc.v:163305.3-163323.6" + wire $0\nia_ok$next[0:0]$8867 + attribute \src "libresoc.v:163141.3-163142.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:161576.3-161593.6" - wire $0\r_busy$next[0:0]$8780 - attribute \src "libresoc.v:161537.3-161538.29" + attribute \src "libresoc.v:163208.3-163225.6" + wire $0\r_busy$next[0:0]$8828 + attribute \src "libresoc.v:163169.3-163170.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8795 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 14 $1\br_op__fn_unit$4$next[13:0]$8796 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8797 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8798 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8799 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8800 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__is_32bit$9$next[0:0]$8801 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__lk$8$next[0:0]$8802 - attribute \src "libresoc.v:161635.3-161653.6" - wire width 64 $1\fast1$10$next[63:0]$8808 - attribute \src "libresoc.v:161635.3-161653.6" - wire $1\fast1_ok$next[0:0]$8809 - attribute \src "libresoc.v:161210.7-161210.22" + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8843 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8846 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8847 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__is_32bit$9$next[0:0]$8849 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__lk$8$next[0:0]$8850 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $1\fast1$10$next[63:0]$8856 + attribute \src "libresoc.v:163267.3-163285.6" + wire $1\fast1_ok$next[0:0]$8857 + attribute \src "libresoc.v:162842.7-162842.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:161654.3-161672.6" - wire width 64 $1\fast2$11$next[63:0]$8814 - attribute \src "libresoc.v:161654.3-161672.6" - wire $1\fast2_ok$next[0:0]$8815 - attribute \src "libresoc.v:161226.7-161226.22" + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $1\fast2$11$next[63:0]$8862 + attribute \src "libresoc.v:163286.3-163304.6" + wire $1\fast2_ok$next[0:0]$8863 + attribute \src "libresoc.v:162858.7-162858.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:161594.3-161606.6" - wire width 2 $1\muxid$1$next[1:0]$8785 - attribute \src "libresoc.v:161673.3-161691.6" - wire width 64 $1\nia$next[63:0]$8820 - attribute \src "libresoc.v:161482.14-161482.40" + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $1\nia$next[63:0]$8868 + attribute \src "libresoc.v:163114.14-163114.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:161673.3-161691.6" - wire $1\nia_ok$next[0:0]$8821 - attribute \src "libresoc.v:161489.7-161489.20" + attribute \src "libresoc.v:163305.3-163323.6" + wire $1\nia_ok$next[0:0]$8869 + attribute \src "libresoc.v:163121.7-163121.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:161576.3-161593.6" - wire $1\r_busy$next[0:0]$8781 - attribute \src "libresoc.v:161503.7-161503.20" + attribute \src "libresoc.v:163208.3-163225.6" + wire $1\r_busy$next[0:0]$8829 + attribute \src "libresoc.v:163135.7-163135.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8803 - attribute \src "libresoc.v:161607.3-161634.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8804 - attribute \src "libresoc.v:161635.3-161653.6" - wire $2\fast1_ok$next[0:0]$8810 - attribute \src "libresoc.v:161654.3-161672.6" - wire $2\fast2_ok$next[0:0]$8816 - attribute \src "libresoc.v:161673.3-161691.6" - wire $2\nia_ok$next[0:0]$8822 - attribute \src "libresoc.v:161576.3-161593.6" - wire $2\r_busy$next[0:0]$8782 - attribute \src "libresoc.v:161506.18-161506.118" - wire $and$libresoc.v:161506$8751_Y + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 + attribute \src "libresoc.v:163239.3-163266.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163267.3-163285.6" + wire $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163286.3-163304.6" + wire $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163305.3-163323.6" + wire $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163208.3-163225.6" + wire $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163138.18-163138.118" + wire $and$libresoc.v:163138$8799_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335119,9 +337616,9 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a @@ -335153,7 +337650,7 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:160848.7-160848.15" + attribute \src "libresoc.v:162480.7-162480.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -335428,7 +337925,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:161506$8751 + cell $and $and$libresoc.v:163138$8799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -335436,10 +337933,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:161506$8751_Y + connect \Y $and$libresoc.v:163138$8799_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161539.13-161567.4" + attribute \src "libresoc.v:163171.13-163199.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -335470,274 +337967,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:161568.10-161571.4" + attribute \src "libresoc.v:163200.10-163203.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161572.10-161575.4" + attribute \src "libresoc.v:163204.10-163207.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160848.7-160848.20" - process $proc$libresoc.v:160848$8823 + attribute \src "libresoc.v:162480.7-162480.20" + process $proc$libresoc.v:162480$8871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160855.14-160855.51" - process $proc$libresoc.v:160855$8824 + attribute \src "libresoc.v:162487.14-162487.51" + process $proc$libresoc.v:162487$8872 assign { } { } - assign $0\br_op__cia$2[63:0]$8825 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8825 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 end - attribute \src "libresoc.v:160911.14-160911.43" - process $proc$libresoc.v:160911$8826 + attribute \src "libresoc.v:162543.14-162543.43" + process $proc$libresoc.v:162543$8874 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8827 14'00000000000000 + assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8827 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 end - attribute \src "libresoc.v:160920.14-160920.62" - process $proc$libresoc.v:160920$8828 + attribute \src "libresoc.v:162552.14-162552.62" + process $proc$libresoc.v:162552$8876 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8829 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8829 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 end - attribute \src "libresoc.v:160929.7-160929.37" - process $proc$libresoc.v:160929$8830 + attribute \src "libresoc.v:162561.7-162561.37" + process $proc$libresoc.v:162561$8878 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8831 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8831 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 end - attribute \src "libresoc.v:160938.14-160938.37" - process $proc$libresoc.v:160938$8832 + attribute \src "libresoc.v:162570.14-162570.37" + process $proc$libresoc.v:162570$8880 assign { } { } - assign $0\br_op__insn$5[31:0]$8833 0 + assign $0\br_op__insn$5[31:0]$8881 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8833 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 end - attribute \src "libresoc.v:161172.13-161172.41" - process $proc$libresoc.v:161172$8834 + attribute \src "libresoc.v:162804.13-162804.41" + process $proc$libresoc.v:162804$8882 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8835 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8835 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 end - attribute \src "libresoc.v:161181.7-161181.33" - process $proc$libresoc.v:161181$8836 + attribute \src "libresoc.v:162813.7-162813.33" + process $proc$libresoc.v:162813$8884 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8837 1'0 + assign $0\br_op__is_32bit$9[0:0]$8885 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8837 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 end - attribute \src "libresoc.v:161190.7-161190.27" - process $proc$libresoc.v:161190$8838 + attribute \src "libresoc.v:162822.7-162822.27" + process $proc$libresoc.v:162822$8886 assign { } { } - assign $0\br_op__lk$8[0:0]$8839 1'0 + assign $0\br_op__lk$8[0:0]$8887 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8839 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 end - attribute \src "libresoc.v:161203.14-161203.47" - process $proc$libresoc.v:161203$8840 + attribute \src "libresoc.v:162835.14-162835.47" + process $proc$libresoc.v:162835$8888 assign { } { } - assign $0\fast1$10[63:0]$8841 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8841 + update \fast1$10 $0\fast1$10[63:0]$8889 end - attribute \src "libresoc.v:161210.7-161210.22" - process $proc$libresoc.v:161210$8842 + attribute \src "libresoc.v:162842.7-162842.22" + process $proc$libresoc.v:162842$8890 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:161219.14-161219.47" - process $proc$libresoc.v:161219$8843 + attribute \src "libresoc.v:162851.14-162851.47" + process $proc$libresoc.v:162851$8891 assign { } { } - assign $0\fast2$11[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8844 + update \fast2$11 $0\fast2$11[63:0]$8892 end - attribute \src "libresoc.v:161226.7-161226.22" - process $proc$libresoc.v:161226$8845 + attribute \src "libresoc.v:162858.7-162858.22" + process $proc$libresoc.v:162858$8893 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:161469.13-161469.29" - process $proc$libresoc.v:161469$8846 + attribute \src "libresoc.v:163101.13-163101.29" + process $proc$libresoc.v:163101$8894 assign { } { } - assign $0\muxid$1[1:0]$8847 2'00 + assign $0\muxid$1[1:0]$8895 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8847 + update \muxid$1 $0\muxid$1[1:0]$8895 end - attribute \src "libresoc.v:161482.14-161482.40" - process $proc$libresoc.v:161482$8848 + attribute \src "libresoc.v:163114.14-163114.40" + process $proc$libresoc.v:163114$8896 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:161489.7-161489.20" - process $proc$libresoc.v:161489$8849 + attribute \src "libresoc.v:163121.7-163121.20" + process $proc$libresoc.v:163121$8897 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:161503.7-161503.20" - process $proc$libresoc.v:161503$8850 + attribute \src "libresoc.v:163135.7-163135.20" + process $proc$libresoc.v:163135$8898 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161507.3-161508.23" - process $proc$libresoc.v:161507$8752 + attribute \src "libresoc.v:163139.3-163140.23" + process $proc$libresoc.v:163139$8800 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:161509.3-161510.29" - process $proc$libresoc.v:161509$8753 + attribute \src "libresoc.v:163141.3-163142.29" + process $proc$libresoc.v:163141$8801 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:161511.3-161512.35" - process $proc$libresoc.v:161511$8754 + attribute \src "libresoc.v:163143.3-163144.35" + process $proc$libresoc.v:163143$8802 assign { } { } - assign $0\fast2$11[63:0]$8755 \fast2$11$next + assign $0\fast2$11[63:0]$8803 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8755 + update \fast2$11 $0\fast2$11[63:0]$8803 end - attribute \src "libresoc.v:161513.3-161514.33" - process $proc$libresoc.v:161513$8756 + attribute \src "libresoc.v:163145.3-163146.33" + process $proc$libresoc.v:163145$8804 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:161515.3-161516.35" - process $proc$libresoc.v:161515$8757 + attribute \src "libresoc.v:163147.3-163148.35" + process $proc$libresoc.v:163147$8805 assign { } { } - assign $0\fast1$10[63:0]$8758 \fast1$10$next + assign $0\fast1$10[63:0]$8806 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8758 + update \fast1$10 $0\fast1$10[63:0]$8806 end - attribute \src "libresoc.v:161517.3-161518.33" - process $proc$libresoc.v:161517$8759 + attribute \src "libresoc.v:163149.3-163150.33" + process $proc$libresoc.v:163149$8807 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:161519.3-161520.43" - process $proc$libresoc.v:161519$8760 + attribute \src "libresoc.v:163151.3-163152.43" + process $proc$libresoc.v:163151$8808 assign { } { } - assign $0\br_op__cia$2[63:0]$8761 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8761 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 end - attribute \src "libresoc.v:161521.3-161522.55" - process $proc$libresoc.v:161521$8762 + attribute \src "libresoc.v:163153.3-163154.55" + process $proc$libresoc.v:163153$8810 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8763 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8763 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 end - attribute \src "libresoc.v:161523.3-161524.51" - process $proc$libresoc.v:161523$8764 + attribute \src "libresoc.v:163155.3-163156.51" + process $proc$libresoc.v:163155$8812 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8765 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8765 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 end - attribute \src "libresoc.v:161525.3-161526.45" - process $proc$libresoc.v:161525$8766 + attribute \src "libresoc.v:163157.3-163158.45" + process $proc$libresoc.v:163157$8814 assign { } { } - assign $0\br_op__insn$5[31:0]$8767 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8767 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 end - attribute \src "libresoc.v:161527.3-161528.65" - process $proc$libresoc.v:161527$8768 + attribute \src "libresoc.v:163159.3-163160.65" + process $proc$libresoc.v:163159$8816 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8769 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8769 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 end - attribute \src "libresoc.v:161529.3-161530.61" - process $proc$libresoc.v:161529$8770 + attribute \src "libresoc.v:163161.3-163162.61" + process $proc$libresoc.v:163161$8818 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8771 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8771 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 end - attribute \src "libresoc.v:161531.3-161532.41" - process $proc$libresoc.v:161531$8772 + attribute \src "libresoc.v:163163.3-163164.41" + process $proc$libresoc.v:163163$8820 assign { } { } - assign $0\br_op__lk$8[0:0]$8773 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8773 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 end - attribute \src "libresoc.v:161533.3-161534.53" - process $proc$libresoc.v:161533$8774 + attribute \src "libresoc.v:163165.3-163166.53" + process $proc$libresoc.v:163165$8822 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8775 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8775 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 end - attribute \src "libresoc.v:161535.3-161536.33" - process $proc$libresoc.v:161535$8776 + attribute \src "libresoc.v:163167.3-163168.33" + process $proc$libresoc.v:163167$8824 assign { } { } - assign $0\muxid$1[1:0]$8777 \muxid$1$next + assign $0\muxid$1[1:0]$8825 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8777 + update \muxid$1 $0\muxid$1[1:0]$8825 end - attribute \src "libresoc.v:161537.3-161538.29" - process $proc$libresoc.v:161537$8778 + attribute \src "libresoc.v:163169.3-163170.29" + process $proc$libresoc.v:163169$8826 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:161576.3-161593.6" - process $proc$libresoc.v:161576$8779 + attribute \src "libresoc.v:163208.3-163225.6" + process $proc$libresoc.v:163208$8827 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8780 $2\r_busy$next[0:0]$8782 - attribute \src "libresoc.v:161577.5-161577.29" + assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163209.5-163209.29" switch \initial - attribute \src "libresoc.v:161577.9-161577.17" + attribute \src "libresoc.v:163209.9-163209.17" case 1'1 case end @@ -335746,34 +338243,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8781 1'1 + assign $1\r_busy$next[0:0]$8829 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8781 1'0 + assign $1\r_busy$next[0:0]$8829 1'0 case - assign $1\r_busy$next[0:0]$8781 \r_busy + assign $1\r_busy$next[0:0]$8829 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8782 1'0 + assign $2\r_busy$next[0:0]$8830 1'0 case - assign $2\r_busy$next[0:0]$8782 $1\r_busy$next[0:0]$8781 + assign $2\r_busy$next[0:0]$8830 $1\r_busy$next[0:0]$8829 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8780 + update \r_busy$next $0\r_busy$next[0:0]$8828 end - attribute \src "libresoc.v:161594.3-161606.6" - process $proc$libresoc.v:161594$8783 + attribute \src "libresoc.v:163226.3-163238.6" + process $proc$libresoc.v:163226$8831 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8784 $1\muxid$1$next[1:0]$8785 - attribute \src "libresoc.v:161595.5-161595.29" + assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163227.5-163227.29" switch \initial - attribute \src "libresoc.v:161595.9-161595.17" + attribute \src "libresoc.v:163227.9-163227.17" case 1'1 case end @@ -335782,19 +338279,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8785 \muxid$26 + assign $1\muxid$1$next[1:0]$8833 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8785 \muxid$26 + assign $1\muxid$1$next[1:0]$8833 \muxid$26 case - assign $1\muxid$1$next[1:0]$8785 \muxid$1 + assign $1\muxid$1$next[1:0]$8833 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8784 + update \muxid$1$next $0\muxid$1$next[1:0]$8832 end - attribute \src "libresoc.v:161607.3-161634.6" - process $proc$libresoc.v:161607$8786 + attribute \src "libresoc.v:163239.3-163266.6" + process $proc$libresoc.v:163239$8834 assign { } { } assign { } { } assign { } { } @@ -335811,19 +338308,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8787 $1\br_op__cia$2$next[63:0]$8795 - assign $0\br_op__fn_unit$4$next[13:0]$8788 $1\br_op__fn_unit$4$next[13:0]$8796 + assign $0\br_op__cia$2$next[63:0]$8835 $1\br_op__cia$2$next[63:0]$8843 + assign $0\br_op__fn_unit$4$next[13:0]$8836 $1\br_op__fn_unit$4$next[13:0]$8844 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8791 $1\br_op__insn$5$next[31:0]$8799 - assign $0\br_op__insn_type$3$next[6:0]$8792 $1\br_op__insn_type$3$next[6:0]$8800 - assign $0\br_op__is_32bit$9$next[0:0]$8793 $1\br_op__is_32bit$9$next[0:0]$8801 - assign $0\br_op__lk$8$next[0:0]$8794 $1\br_op__lk$8$next[0:0]$8802 - assign $0\br_op__imm_data__data$6$next[63:0]$8789 $2\br_op__imm_data__data$6$next[63:0]$8803 - assign $0\br_op__imm_data__ok$7$next[0:0]$8790 $2\br_op__imm_data__ok$7$next[0:0]$8804 - attribute \src "libresoc.v:161608.5-161608.29" + assign $0\br_op__insn$5$next[31:0]$8839 $1\br_op__insn$5$next[31:0]$8847 + assign $0\br_op__insn_type$3$next[6:0]$8840 $1\br_op__insn_type$3$next[6:0]$8848 + assign $0\br_op__is_32bit$9$next[0:0]$8841 $1\br_op__is_32bit$9$next[0:0]$8849 + assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 + assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 + assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163240.5-163240.29" switch \initial - attribute \src "libresoc.v:161608.9-161608.17" + attribute \src "libresoc.v:163240.9-163240.17" case 1'1 case end @@ -335839,7 +338336,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -335850,16 +338347,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8795 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[13:0]$8796 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8797 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8798 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8799 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8800 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8801 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8802 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8843 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8844 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8845 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8846 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8847 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8848 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8849 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8850 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -335867,34 +338364,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8803 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8804 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8803 $1\br_op__imm_data__data$6$next[63:0]$8797 - assign $2\br_op__imm_data__ok$7$next[0:0]$8804 $1\br_op__imm_data__ok$7$next[0:0]$8798 + assign $2\br_op__imm_data__data$6$next[63:0]$8851 $1\br_op__imm_data__data$6$next[63:0]$8845 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8846 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8787 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8788 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8789 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8790 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8791 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8792 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8793 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8794 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8835 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8836 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8837 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8838 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8839 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8840 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 end - attribute \src "libresoc.v:161635.3-161653.6" - process $proc$libresoc.v:161635$8805 + attribute \src "libresoc.v:163267.3-163285.6" + process $proc$libresoc.v:163267$8853 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8806 $1\fast1$10$next[63:0]$8808 + assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 assign { } { } - assign $0\fast1_ok$next[0:0]$8807 $2\fast1_ok$next[0:0]$8810 - attribute \src "libresoc.v:161636.5-161636.29" + assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163268.5-163268.29" switch \initial - attribute \src "libresoc.v:161636.9-161636.17" + attribute \src "libresoc.v:163268.9-163268.17" case 1'1 case end @@ -335904,41 +338401,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8808 \fast1$10 - assign $1\fast1_ok$next[0:0]$8809 \fast1_ok + assign $1\fast1$10$next[63:0]$8856 \fast1$10 + assign $1\fast1_ok$next[0:0]$8857 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8810 1'0 + assign $2\fast1_ok$next[0:0]$8858 1'0 case - assign $2\fast1_ok$next[0:0]$8810 $1\fast1_ok$next[0:0]$8809 + assign $2\fast1_ok$next[0:0]$8858 $1\fast1_ok$next[0:0]$8857 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8806 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8807 + update \fast1$10$next $0\fast1$10$next[63:0]$8854 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 end - attribute \src "libresoc.v:161654.3-161672.6" - process $proc$libresoc.v:161654$8811 + attribute \src "libresoc.v:163286.3-163304.6" + process $proc$libresoc.v:163286$8859 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8812 $1\fast2$11$next[63:0]$8814 + assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 assign { } { } - assign $0\fast2_ok$next[0:0]$8813 $2\fast2_ok$next[0:0]$8816 - attribute \src "libresoc.v:161655.5-161655.29" + assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163287.5-163287.29" switch \initial - attribute \src "libresoc.v:161655.9-161655.17" + attribute \src "libresoc.v:163287.9-163287.17" case 1'1 case end @@ -335948,41 +338445,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8814 \fast2$11 - assign $1\fast2_ok$next[0:0]$8815 \fast2_ok + assign $1\fast2$11$next[63:0]$8862 \fast2$11 + assign $1\fast2_ok$next[0:0]$8863 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8816 1'0 + assign $2\fast2_ok$next[0:0]$8864 1'0 case - assign $2\fast2_ok$next[0:0]$8816 $1\fast2_ok$next[0:0]$8815 + assign $2\fast2_ok$next[0:0]$8864 $1\fast2_ok$next[0:0]$8863 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8812 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8813 + update \fast2$11$next $0\fast2$11$next[63:0]$8860 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 end - attribute \src "libresoc.v:161673.3-161691.6" - process $proc$libresoc.v:161673$8817 + attribute \src "libresoc.v:163305.3-163323.6" + process $proc$libresoc.v:163305$8865 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8818 $1\nia$next[63:0]$8820 + assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 assign { } { } - assign $0\nia_ok$next[0:0]$8819 $2\nia_ok$next[0:0]$8822 - attribute \src "libresoc.v:161674.5-161674.29" + assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163306.5-163306.29" switch \initial - attribute \src "libresoc.v:161674.9-161674.17" + attribute \src "libresoc.v:163306.9-163306.17" case 1'1 case end @@ -335992,30 +338489,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8820 \nia - assign $1\nia_ok$next[0:0]$8821 \nia_ok + assign $1\nia$next[63:0]$8868 \nia + assign $1\nia_ok$next[0:0]$8869 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8822 1'0 + assign $2\nia_ok$next[0:0]$8870 1'0 case - assign $2\nia_ok$next[0:0]$8822 $1\nia_ok$next[0:0]$8821 + assign $2\nia_ok$next[0:0]$8870 $1\nia_ok$next[0:0]$8869 end sync always - update \nia$next $0\nia$next[63:0]$8818 - update \nia_ok$next $0\nia_ok$next[0:0]$8819 + update \nia$next $0\nia$next[63:0]$8866 + update \nia_ok$next $0\nia_ok$next[0:0]$8867 end - connect \$24 $and$libresoc.v:161506$8751_Y + connect \$24 $and$libresoc.v:163138$8799_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -336032,178 +338529,178 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:161711.1-162641.10" +attribute \src "libresoc.v:163343.1-164273.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:162544.3-162562.6" - wire width 64 $0\fast1$7$next[63:0]$8910 - attribute \src "libresoc.v:162397.3-162398.33" - wire width 64 $0\fast1$7[63:0]$8862 - attribute \src "libresoc.v:161725.14-161725.46" - wire width 64 $0\fast1$7[63:0]$8934 - attribute \src "libresoc.v:162544.3-162562.6" - wire $0\fast1_ok$next[0:0]$8909 - attribute \src "libresoc.v:162399.3-162400.33" + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $0\fast1$7$next[63:0]$8958 + attribute \src "libresoc.v:164029.3-164030.33" + wire width 64 $0\fast1$7[63:0]$8910 + attribute \src "libresoc.v:163357.14-163357.46" + wire width 64 $0\fast1$7[63:0]$8982 + attribute \src "libresoc.v:164176.3-164194.6" + wire $0\fast1_ok$next[0:0]$8957 + attribute \src "libresoc.v:164031.3-164032.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:161712.7-161712.20" + attribute \src "libresoc.v:163344.7-163344.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162477.3-162489.6" - wire width 2 $0\muxid$1$next[1:0]$8885 - attribute \src "libresoc.v:162417.3-162418.33" - wire width 2 $0\muxid$1[1:0]$8878 - attribute \src "libresoc.v:161739.13-161739.29" - wire width 2 $0\muxid$1[1:0]$8937 - attribute \src "libresoc.v:162506.3-162524.6" - wire width 64 $0\o$next[63:0]$8897 - attribute \src "libresoc.v:162405.3-162406.19" + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $0\muxid$1$next[1:0]$8933 + attribute \src "libresoc.v:164049.3-164050.33" + wire width 2 $0\muxid$1[1:0]$8926 + attribute \src "libresoc.v:163371.13-163371.29" + wire width 2 $0\muxid$1[1:0]$8985 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $0\o$next[63:0]$8945 + attribute \src "libresoc.v:164037.3-164038.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162506.3-162524.6" - wire $0\o_ok$next[0:0]$8898 - attribute \src "libresoc.v:162407.3-162408.25" + attribute \src "libresoc.v:164138.3-164156.6" + wire $0\o_ok$next[0:0]$8946 + attribute \src "libresoc.v:164039.3-164040.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162459.3-162476.6" - wire $0\r_busy$next[0:0]$8881 - attribute \src "libresoc.v:162419.3-162420.29" + attribute \src "libresoc.v:164091.3-164108.6" + wire $0\r_busy$next[0:0]$8929 + attribute \src "libresoc.v:164051.3-164052.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162525.3-162543.6" - wire width 64 $0\spr1$6$next[63:0]$8903 - attribute \src "libresoc.v:162401.3-162402.31" - wire width 64 $0\spr1$6[63:0]$8865 - attribute \src "libresoc.v:161784.14-161784.45" - wire width 64 $0\spr1$6[63:0]$8942 - attribute \src "libresoc.v:162525.3-162543.6" - wire $0\spr1_ok$next[0:0]$8904 - attribute \src "libresoc.v:162403.3-162404.31" + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $0\spr1$6$next[63:0]$8951 + attribute \src "libresoc.v:164033.3-164034.31" + wire width 64 $0\spr1$6[63:0]$8913 + attribute \src "libresoc.v:163416.14-163416.45" + wire width 64 $0\spr1$6[63:0]$8990 + attribute \src "libresoc.v:164157.3-164175.6" + wire $0\spr1_ok$next[0:0]$8952 + attribute \src "libresoc.v:164035.3-164036.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:162490.3-162505.6" - wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8888 - attribute \src "libresoc.v:162411.3-162412.53" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8872 - attribute \src "libresoc.v:162081.14-162081.44" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8945 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8889 - attribute \src "libresoc.v:162413.3-162414.47" - wire width 32 $0\spr_op__insn$4[31:0]$8874 - attribute \src "libresoc.v:162090.14-162090.38" - wire width 32 $0\spr_op__insn$4[31:0]$8947 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8890 - attribute \src "libresoc.v:162409.3-162410.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8870 - attribute \src "libresoc.v:162247.13-162247.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8949 - attribute \src "libresoc.v:162490.3-162505.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8891 - attribute \src "libresoc.v:162415.3-162416.55" - wire $0\spr_op__is_32bit$5[0:0]$8876 - attribute \src "libresoc.v:162333.7-162333.34" - wire $0\spr_op__is_32bit$5[0:0]$8951 - attribute \src "libresoc.v:162601.3-162619.6" - wire width 2 $0\xer_ca$10$next[1:0]$8927 - attribute \src "libresoc.v:162385.3-162386.37" - wire width 2 $0\xer_ca$10[1:0]$8853 - attribute \src "libresoc.v:162340.13-162340.31" - wire width 2 $0\xer_ca$10[1:0]$8953 - attribute \src "libresoc.v:162601.3-162619.6" - wire $0\xer_ca_ok$next[0:0]$8928 - attribute \src "libresoc.v:162387.3-162388.35" + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 + attribute \src "libresoc.v:164043.3-164044.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 + attribute \src "libresoc.v:163713.14-163713.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8937 + attribute \src "libresoc.v:164045.3-164046.47" + wire width 32 $0\spr_op__insn$4[31:0]$8922 + attribute \src "libresoc.v:163722.14-163722.38" + wire width 32 $0\spr_op__insn$4[31:0]$8995 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 + attribute \src "libresoc.v:164041.3-164042.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8918 + attribute \src "libresoc.v:163879.13-163879.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8997 + attribute \src "libresoc.v:164122.3-164137.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8939 + attribute \src "libresoc.v:164047.3-164048.55" + wire $0\spr_op__is_32bit$5[0:0]$8924 + attribute \src "libresoc.v:163965.7-163965.34" + wire $0\spr_op__is_32bit$5[0:0]$8999 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $0\xer_ca$10$next[1:0]$8975 + attribute \src "libresoc.v:164017.3-164018.37" + wire width 2 $0\xer_ca$10[1:0]$8901 + attribute \src "libresoc.v:163972.13-163972.31" + wire width 2 $0\xer_ca$10[1:0]$9001 + attribute \src "libresoc.v:164233.3-164251.6" + wire $0\xer_ca_ok$next[0:0]$8976 + attribute \src "libresoc.v:164019.3-164020.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:162582.3-162600.6" - wire width 2 $0\xer_ov$9$next[1:0]$8922 - attribute \src "libresoc.v:162389.3-162390.35" - wire width 2 $0\xer_ov$9[1:0]$8856 - attribute \src "libresoc.v:162358.13-162358.30" - wire width 2 $0\xer_ov$9[1:0]$8956 - attribute \src "libresoc.v:162582.3-162600.6" - wire $0\xer_ov_ok$next[0:0]$8921 - attribute \src "libresoc.v:162391.3-162392.35" + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $0\xer_ov$9$next[1:0]$8970 + attribute \src "libresoc.v:164021.3-164022.35" + wire width 2 $0\xer_ov$9[1:0]$8904 + attribute \src "libresoc.v:163990.13-163990.30" + wire width 2 $0\xer_ov$9[1:0]$9004 + attribute \src "libresoc.v:164214.3-164232.6" + wire $0\xer_ov_ok$next[0:0]$8969 + attribute \src "libresoc.v:164023.3-164024.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:162563.3-162581.6" - wire $0\xer_so$8$next[0:0]$8916 - attribute \src "libresoc.v:162393.3-162394.35" - wire $0\xer_so$8[0:0]$8859 - attribute \src "libresoc.v:162374.7-162374.24" - wire $0\xer_so$8[0:0]$8959 - attribute \src "libresoc.v:162563.3-162581.6" - wire $0\xer_so_ok$next[0:0]$8915 - attribute \src "libresoc.v:162395.3-162396.35" + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so$8$next[0:0]$8964 + attribute \src "libresoc.v:164025.3-164026.35" + wire $0\xer_so$8[0:0]$8907 + attribute \src "libresoc.v:164006.7-164006.24" + wire $0\xer_so$8[0:0]$9007 + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so_ok$next[0:0]$8963 + attribute \src "libresoc.v:164027.3-164028.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:162544.3-162562.6" - wire width 64 $1\fast1$7$next[63:0]$8912 - attribute \src "libresoc.v:162544.3-162562.6" - wire $1\fast1_ok$next[0:0]$8911 - attribute \src "libresoc.v:161730.7-161730.22" + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $1\fast1$7$next[63:0]$8960 + attribute \src "libresoc.v:164176.3-164194.6" + wire $1\fast1_ok$next[0:0]$8959 + attribute \src "libresoc.v:163362.7-163362.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:162477.3-162489.6" - wire width 2 $1\muxid$1$next[1:0]$8886 - attribute \src "libresoc.v:162506.3-162524.6" - wire width 64 $1\o$next[63:0]$8899 - attribute \src "libresoc.v:161752.14-161752.38" + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $1\o$next[63:0]$8947 + attribute \src "libresoc.v:163384.14-163384.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162506.3-162524.6" - wire $1\o_ok$next[0:0]$8900 - attribute \src "libresoc.v:161759.7-161759.18" + attribute \src "libresoc.v:164138.3-164156.6" + wire $1\o_ok$next[0:0]$8948 + attribute \src "libresoc.v:163391.7-163391.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162459.3-162476.6" - wire $1\r_busy$next[0:0]$8882 - attribute \src "libresoc.v:161773.7-161773.20" + attribute \src "libresoc.v:164091.3-164108.6" + wire $1\r_busy$next[0:0]$8930 + attribute \src "libresoc.v:163405.7-163405.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162525.3-162543.6" - wire width 64 $1\spr1$6$next[63:0]$8905 - attribute \src "libresoc.v:162525.3-162543.6" - wire $1\spr1_ok$next[0:0]$8906 - attribute \src "libresoc.v:161789.7-161789.21" + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $1\spr1$6$next[63:0]$8953 + attribute \src "libresoc.v:164157.3-164175.6" + wire $1\spr1_ok$next[0:0]$8954 + attribute \src "libresoc.v:163421.7-163421.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:162490.3-162505.6" - wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8892 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8893 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8894 - attribute \src "libresoc.v:162490.3-162505.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8895 - attribute \src "libresoc.v:162601.3-162619.6" - wire width 2 $1\xer_ca$10$next[1:0]$8929 - attribute \src "libresoc.v:162601.3-162619.6" - wire $1\xer_ca_ok$next[0:0]$8930 - attribute \src "libresoc.v:162347.7-162347.23" + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8941 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 + attribute \src "libresoc.v:164122.3-164137.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $1\xer_ca$10$next[1:0]$8977 + attribute \src "libresoc.v:164233.3-164251.6" + wire $1\xer_ca_ok$next[0:0]$8978 + attribute \src "libresoc.v:163979.7-163979.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:162582.3-162600.6" - wire width 2 $1\xer_ov$9$next[1:0]$8924 - attribute \src "libresoc.v:162582.3-162600.6" - wire $1\xer_ov_ok$next[0:0]$8923 - attribute \src "libresoc.v:162363.7-162363.23" + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $1\xer_ov$9$next[1:0]$8972 + attribute \src "libresoc.v:164214.3-164232.6" + wire $1\xer_ov_ok$next[0:0]$8971 + attribute \src "libresoc.v:163995.7-163995.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:162563.3-162581.6" - wire $1\xer_so$8$next[0:0]$8918 - attribute \src "libresoc.v:162563.3-162581.6" - wire $1\xer_so_ok$next[0:0]$8917 - attribute \src "libresoc.v:162379.7-162379.23" + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so$8$next[0:0]$8966 + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so_ok$next[0:0]$8965 + attribute \src "libresoc.v:164011.7-164011.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:162544.3-162562.6" - wire $2\fast1_ok$next[0:0]$8913 - attribute \src "libresoc.v:162506.3-162524.6" - wire $2\o_ok$next[0:0]$8901 - attribute \src "libresoc.v:162459.3-162476.6" - wire $2\r_busy$next[0:0]$8883 - attribute \src "libresoc.v:162525.3-162543.6" - wire $2\spr1_ok$next[0:0]$8907 - attribute \src "libresoc.v:162601.3-162619.6" - wire $2\xer_ca_ok$next[0:0]$8931 - attribute \src "libresoc.v:162582.3-162600.6" - wire $2\xer_ov_ok$next[0:0]$8925 - attribute \src "libresoc.v:162563.3-162581.6" - wire $2\xer_so_ok$next[0:0]$8919 - attribute \src "libresoc.v:162384.18-162384.118" - wire $and$libresoc.v:162384$8851_Y + attribute \src "libresoc.v:164176.3-164194.6" + wire $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164138.3-164156.6" + wire $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164091.3-164108.6" + wire $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164157.3-164175.6" + wire $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164233.3-164251.6" + wire $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164214.3-164232.6" + wire $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164195.3-164213.6" + wire $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164016.18-164016.118" + wire $and$libresoc.v:164016$8899_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 @@ -336219,7 +338716,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "libresoc.v:161712.7-161712.15" + attribute \src "libresoc.v:163344.7-163344.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -336856,7 +339353,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:162384$8851 + cell $and $and$libresoc.v:164016$8899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336864,22 +339361,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:162384$8851_Y + connect \Y $and$libresoc.v:164016$8899_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162421.10-162424.4" + attribute \src "libresoc.v:164053.10-164056.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162425.10-162428.4" + attribute \src "libresoc.v:164057.10-164060.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:162429.12-162458.4" + attribute \src "libresoc.v:164061.12-164090.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -336910,293 +339407,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:161712.7-161712.20" - process $proc$libresoc.v:161712$8932 + attribute \src "libresoc.v:163344.7-163344.20" + process $proc$libresoc.v:163344$8980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161725.14-161725.46" - process $proc$libresoc.v:161725$8933 + attribute \src "libresoc.v:163357.14-163357.46" + process $proc$libresoc.v:163357$8981 assign { } { } - assign $0\fast1$7[63:0]$8934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8934 + update \fast1$7 $0\fast1$7[63:0]$8982 end - attribute \src "libresoc.v:161730.7-161730.22" - process $proc$libresoc.v:161730$8935 + attribute \src "libresoc.v:163362.7-163362.22" + process $proc$libresoc.v:163362$8983 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:161739.13-161739.29" - process $proc$libresoc.v:161739$8936 + attribute \src "libresoc.v:163371.13-163371.29" + process $proc$libresoc.v:163371$8984 assign { } { } - assign $0\muxid$1[1:0]$8937 2'00 + assign $0\muxid$1[1:0]$8985 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8937 + update \muxid$1 $0\muxid$1[1:0]$8985 end - attribute \src "libresoc.v:161752.14-161752.38" - process $proc$libresoc.v:161752$8938 + attribute \src "libresoc.v:163384.14-163384.38" + process $proc$libresoc.v:163384$8986 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:161759.7-161759.18" - process $proc$libresoc.v:161759$8939 + attribute \src "libresoc.v:163391.7-163391.18" + process $proc$libresoc.v:163391$8987 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:161773.7-161773.20" - process $proc$libresoc.v:161773$8940 + attribute \src "libresoc.v:163405.7-163405.20" + process $proc$libresoc.v:163405$8988 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161784.14-161784.45" - process $proc$libresoc.v:161784$8941 + attribute \src "libresoc.v:163416.14-163416.45" + process $proc$libresoc.v:163416$8989 assign { } { } - assign $0\spr1$6[63:0]$8942 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8942 + update \spr1$6 $0\spr1$6[63:0]$8990 end - attribute \src "libresoc.v:161789.7-161789.21" - process $proc$libresoc.v:161789$8943 + attribute \src "libresoc.v:163421.7-163421.21" + process $proc$libresoc.v:163421$8991 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:162081.14-162081.44" - process $proc$libresoc.v:162081$8944 + attribute \src "libresoc.v:163713.14-163713.44" + process $proc$libresoc.v:163713$8992 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8945 14'00000000000000 + assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8945 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 end - attribute \src "libresoc.v:162090.14-162090.38" - process $proc$libresoc.v:162090$8946 + attribute \src "libresoc.v:163722.14-163722.38" + process $proc$libresoc.v:163722$8994 assign { } { } - assign $0\spr_op__insn$4[31:0]$8947 0 + assign $0\spr_op__insn$4[31:0]$8995 0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8947 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 end - attribute \src "libresoc.v:162247.13-162247.42" - process $proc$libresoc.v:162247$8948 + attribute \src "libresoc.v:163879.13-163879.42" + process $proc$libresoc.v:163879$8996 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8949 7'0000000 + assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8949 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 end - attribute \src "libresoc.v:162333.7-162333.34" - process $proc$libresoc.v:162333$8950 + attribute \src "libresoc.v:163965.7-163965.34" + process $proc$libresoc.v:163965$8998 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8951 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8951 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 end - attribute \src "libresoc.v:162340.13-162340.31" - process $proc$libresoc.v:162340$8952 + attribute \src "libresoc.v:163972.13-163972.31" + process $proc$libresoc.v:163972$9000 assign { } { } - assign $0\xer_ca$10[1:0]$8953 2'00 + assign $0\xer_ca$10[1:0]$9001 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8953 + update \xer_ca$10 $0\xer_ca$10[1:0]$9001 end - attribute \src "libresoc.v:162347.7-162347.23" - process $proc$libresoc.v:162347$8954 + attribute \src "libresoc.v:163979.7-163979.23" + process $proc$libresoc.v:163979$9002 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:162358.13-162358.30" - process $proc$libresoc.v:162358$8955 + attribute \src "libresoc.v:163990.13-163990.30" + process $proc$libresoc.v:163990$9003 assign { } { } - assign $0\xer_ov$9[1:0]$8956 2'00 + assign $0\xer_ov$9[1:0]$9004 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8956 + update \xer_ov$9 $0\xer_ov$9[1:0]$9004 end - attribute \src "libresoc.v:162363.7-162363.23" - process $proc$libresoc.v:162363$8957 + attribute \src "libresoc.v:163995.7-163995.23" + process $proc$libresoc.v:163995$9005 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:162374.7-162374.24" - process $proc$libresoc.v:162374$8958 + attribute \src "libresoc.v:164006.7-164006.24" + process $proc$libresoc.v:164006$9006 assign { } { } - assign $0\xer_so$8[0:0]$8959 1'0 + assign $0\xer_so$8[0:0]$9007 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$8959 + update \xer_so$8 $0\xer_so$8[0:0]$9007 end - attribute \src "libresoc.v:162379.7-162379.23" - process $proc$libresoc.v:162379$8960 + attribute \src "libresoc.v:164011.7-164011.23" + process $proc$libresoc.v:164011$9008 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:162385.3-162386.37" - process $proc$libresoc.v:162385$8852 + attribute \src "libresoc.v:164017.3-164018.37" + process $proc$libresoc.v:164017$8900 assign { } { } - assign $0\xer_ca$10[1:0]$8853 \xer_ca$10$next + assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8853 + update \xer_ca$10 $0\xer_ca$10[1:0]$8901 end - attribute \src "libresoc.v:162387.3-162388.35" - process $proc$libresoc.v:162387$8854 + attribute \src "libresoc.v:164019.3-164020.35" + process $proc$libresoc.v:164019$8902 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:162389.3-162390.35" - process $proc$libresoc.v:162389$8855 + attribute \src "libresoc.v:164021.3-164022.35" + process $proc$libresoc.v:164021$8903 assign { } { } - assign $0\xer_ov$9[1:0]$8856 \xer_ov$9$next + assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8856 + update \xer_ov$9 $0\xer_ov$9[1:0]$8904 end - attribute \src "libresoc.v:162391.3-162392.35" - process $proc$libresoc.v:162391$8857 + attribute \src "libresoc.v:164023.3-164024.35" + process $proc$libresoc.v:164023$8905 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:162393.3-162394.35" - process $proc$libresoc.v:162393$8858 + attribute \src "libresoc.v:164025.3-164026.35" + process $proc$libresoc.v:164025$8906 assign { } { } - assign $0\xer_so$8[0:0]$8859 \xer_so$8$next + assign $0\xer_so$8[0:0]$8907 \xer_so$8$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8859 + update \xer_so$8 $0\xer_so$8[0:0]$8907 end - attribute \src "libresoc.v:162395.3-162396.35" - process $proc$libresoc.v:162395$8860 + attribute \src "libresoc.v:164027.3-164028.35" + process $proc$libresoc.v:164027$8908 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:162397.3-162398.33" - process $proc$libresoc.v:162397$8861 + attribute \src "libresoc.v:164029.3-164030.33" + process $proc$libresoc.v:164029$8909 assign { } { } - assign $0\fast1$7[63:0]$8862 \fast1$7$next + assign $0\fast1$7[63:0]$8910 \fast1$7$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8862 + update \fast1$7 $0\fast1$7[63:0]$8910 end - attribute \src "libresoc.v:162399.3-162400.33" - process $proc$libresoc.v:162399$8863 + attribute \src "libresoc.v:164031.3-164032.33" + process $proc$libresoc.v:164031$8911 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:162401.3-162402.31" - process $proc$libresoc.v:162401$8864 + attribute \src "libresoc.v:164033.3-164034.31" + process $proc$libresoc.v:164033$8912 assign { } { } - assign $0\spr1$6[63:0]$8865 \spr1$6$next + assign $0\spr1$6[63:0]$8913 \spr1$6$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8865 + update \spr1$6 $0\spr1$6[63:0]$8913 end - attribute \src "libresoc.v:162403.3-162404.31" - process $proc$libresoc.v:162403$8866 + attribute \src "libresoc.v:164035.3-164036.31" + process $proc$libresoc.v:164035$8914 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:162405.3-162406.19" - process $proc$libresoc.v:162405$8867 + attribute \src "libresoc.v:164037.3-164038.19" + process $proc$libresoc.v:164037$8915 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:162407.3-162408.25" - process $proc$libresoc.v:162407$8868 + attribute \src "libresoc.v:164039.3-164040.25" + process $proc$libresoc.v:164039$8916 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:162409.3-162410.57" - process $proc$libresoc.v:162409$8869 + attribute \src "libresoc.v:164041.3-164042.57" + process $proc$libresoc.v:164041$8917 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8870 \spr_op__insn_type$2$next + assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8870 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 end - attribute \src "libresoc.v:162411.3-162412.53" - process $proc$libresoc.v:162411$8871 + attribute \src "libresoc.v:164043.3-164044.53" + process $proc$libresoc.v:164043$8919 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8872 \spr_op__fn_unit$3$next + assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8872 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 end - attribute \src "libresoc.v:162413.3-162414.47" - process $proc$libresoc.v:162413$8873 + attribute \src "libresoc.v:164045.3-164046.47" + process $proc$libresoc.v:164045$8921 assign { } { } - assign $0\spr_op__insn$4[31:0]$8874 \spr_op__insn$4$next + assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8874 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 end - attribute \src "libresoc.v:162415.3-162416.55" - process $proc$libresoc.v:162415$8875 + attribute \src "libresoc.v:164047.3-164048.55" + process $proc$libresoc.v:164047$8923 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8876 \spr_op__is_32bit$5$next + assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8876 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 end - attribute \src "libresoc.v:162417.3-162418.33" - process $proc$libresoc.v:162417$8877 + attribute \src "libresoc.v:164049.3-164050.33" + process $proc$libresoc.v:164049$8925 assign { } { } - assign $0\muxid$1[1:0]$8878 \muxid$1$next + assign $0\muxid$1[1:0]$8926 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8878 + update \muxid$1 $0\muxid$1[1:0]$8926 end - attribute \src "libresoc.v:162419.3-162420.29" - process $proc$libresoc.v:162419$8879 + attribute \src "libresoc.v:164051.3-164052.29" + process $proc$libresoc.v:164051$8927 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:162459.3-162476.6" - process $proc$libresoc.v:162459$8880 + attribute \src "libresoc.v:164091.3-164108.6" + process $proc$libresoc.v:164091$8928 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8881 $2\r_busy$next[0:0]$8883 - attribute \src "libresoc.v:162460.5-162460.29" + assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164092.5-164092.29" switch \initial - attribute \src "libresoc.v:162460.9-162460.17" + attribute \src "libresoc.v:164092.9-164092.17" case 1'1 case end @@ -337205,34 +339702,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8882 1'1 + assign $1\r_busy$next[0:0]$8930 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8882 1'0 + assign $1\r_busy$next[0:0]$8930 1'0 case - assign $1\r_busy$next[0:0]$8882 \r_busy + assign $1\r_busy$next[0:0]$8930 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8883 1'0 + assign $2\r_busy$next[0:0]$8931 1'0 case - assign $2\r_busy$next[0:0]$8883 $1\r_busy$next[0:0]$8882 + assign $2\r_busy$next[0:0]$8931 $1\r_busy$next[0:0]$8930 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8881 + update \r_busy$next $0\r_busy$next[0:0]$8929 end - attribute \src "libresoc.v:162477.3-162489.6" - process $proc$libresoc.v:162477$8884 + attribute \src "libresoc.v:164109.3-164121.6" + process $proc$libresoc.v:164109$8932 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8885 $1\muxid$1$next[1:0]$8886 - attribute \src "libresoc.v:162478.5-162478.29" + assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164110.5-164110.29" switch \initial - attribute \src "libresoc.v:162478.9-162478.17" + attribute \src "libresoc.v:164110.9-164110.17" case 1'1 case end @@ -337241,19 +339738,19 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8886 \muxid$24 + assign $1\muxid$1$next[1:0]$8934 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8886 \muxid$24 + assign $1\muxid$1$next[1:0]$8934 \muxid$24 case - assign $1\muxid$1$next[1:0]$8886 \muxid$1 + assign $1\muxid$1$next[1:0]$8934 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8885 + update \muxid$1$next $0\muxid$1$next[1:0]$8933 end - attribute \src "libresoc.v:162490.3-162505.6" - process $proc$libresoc.v:162490$8887 + attribute \src "libresoc.v:164122.3-164137.6" + process $proc$libresoc.v:164122$8935 assign { } { } assign { } { } assign { } { } @@ -337262,13 +339759,13 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[13:0]$8888 $1\spr_op__fn_unit$3$next[13:0]$8892 - assign $0\spr_op__insn$4$next[31:0]$8889 $1\spr_op__insn$4$next[31:0]$8893 - assign $0\spr_op__insn_type$2$next[6:0]$8890 $1\spr_op__insn_type$2$next[6:0]$8894 - assign $0\spr_op__is_32bit$5$next[0:0]$8891 $1\spr_op__is_32bit$5$next[0:0]$8895 - attribute \src "libresoc.v:162491.5-162491.29" + assign $0\spr_op__fn_unit$3$next[13:0]$8936 $1\spr_op__fn_unit$3$next[13:0]$8940 + assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 + assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 + assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164123.5-164123.29" switch \initial - attribute \src "libresoc.v:162491.9-162491.17" + attribute \src "libresoc.v:164123.9-164123.17" case 1'1 case end @@ -337280,38 +339777,38 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\spr_op__fn_unit$3$next[13:0]$8892 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8893 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8894 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8895 \spr_op__is_32bit$5 + assign $1\spr_op__fn_unit$3$next[13:0]$8940 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8941 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8942 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8943 \spr_op__is_32bit$5 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8888 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8889 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8890 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8891 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8936 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8937 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 end - attribute \src "libresoc.v:162506.3-162524.6" - process $proc$libresoc.v:162506$8896 + attribute \src "libresoc.v:164138.3-164156.6" + process $proc$libresoc.v:164138$8944 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8897 $1\o$next[63:0]$8899 + assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 assign { } { } - assign $0\o_ok$next[0:0]$8898 $2\o_ok$next[0:0]$8901 - attribute \src "libresoc.v:162507.5-162507.29" + assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164139.5-164139.29" switch \initial - attribute \src "libresoc.v:162507.9-162507.17" + attribute \src "libresoc.v:164139.9-164139.17" case 1'1 case end @@ -337321,41 +339818,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } case - assign $1\o$next[63:0]$8899 \o - assign $1\o_ok$next[0:0]$8900 \o_ok + assign $1\o$next[63:0]$8947 \o + assign $1\o_ok$next[0:0]$8948 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8901 1'0 + assign $2\o_ok$next[0:0]$8949 1'0 case - assign $2\o_ok$next[0:0]$8901 $1\o_ok$next[0:0]$8900 + assign $2\o_ok$next[0:0]$8949 $1\o_ok$next[0:0]$8948 end sync always - update \o$next $0\o$next[63:0]$8897 - update \o_ok$next $0\o_ok$next[0:0]$8898 + update \o$next $0\o$next[63:0]$8945 + update \o_ok$next $0\o_ok$next[0:0]$8946 end - attribute \src "libresoc.v:162525.3-162543.6" - process $proc$libresoc.v:162525$8902 + attribute \src "libresoc.v:164157.3-164175.6" + process $proc$libresoc.v:164157$8950 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8903 $1\spr1$6$next[63:0]$8905 + assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 assign { } { } - assign $0\spr1_ok$next[0:0]$8904 $2\spr1_ok$next[0:0]$8907 - attribute \src "libresoc.v:162526.5-162526.29" + assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164158.5-164158.29" switch \initial - attribute \src "libresoc.v:162526.9-162526.17" + attribute \src "libresoc.v:164158.9-164158.17" case 1'1 case end @@ -337365,41 +339862,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } case - assign $1\spr1$6$next[63:0]$8905 \spr1$6 - assign $1\spr1_ok$next[0:0]$8906 \spr1_ok + assign $1\spr1$6$next[63:0]$8953 \spr1$6 + assign $1\spr1_ok$next[0:0]$8954 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\spr1_ok$next[0:0]$8907 1'0 + assign $2\spr1_ok$next[0:0]$8955 1'0 case - assign $2\spr1_ok$next[0:0]$8907 $1\spr1_ok$next[0:0]$8906 + assign $2\spr1_ok$next[0:0]$8955 $1\spr1_ok$next[0:0]$8954 end sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8903 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8904 + update \spr1$6$next $0\spr1$6$next[63:0]$8951 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 end - attribute \src "libresoc.v:162544.3-162562.6" - process $proc$libresoc.v:162544$8908 + attribute \src "libresoc.v:164176.3-164194.6" + process $proc$libresoc.v:164176$8956 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8910 $1\fast1$7$next[63:0]$8912 - assign $0\fast1_ok$next[0:0]$8909 $2\fast1_ok$next[0:0]$8913 - attribute \src "libresoc.v:162545.5-162545.29" + assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 + assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164177.5-164177.29" switch \initial - attribute \src "libresoc.v:162545.9-162545.17" + attribute \src "libresoc.v:164177.9-164177.17" case 1'1 case end @@ -337409,41 +339906,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1_ok$next[0:0]$8911 \fast1_ok - assign $1\fast1$7$next[63:0]$8912 \fast1$7 + assign $1\fast1_ok$next[0:0]$8959 \fast1_ok + assign $1\fast1$7$next[63:0]$8960 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8913 1'0 + assign $2\fast1_ok$next[0:0]$8961 1'0 case - assign $2\fast1_ok$next[0:0]$8913 $1\fast1_ok$next[0:0]$8911 + assign $2\fast1_ok$next[0:0]$8961 $1\fast1_ok$next[0:0]$8959 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8909 - update \fast1$7$next $0\fast1$7$next[63:0]$8910 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 + update \fast1$7$next $0\fast1$7$next[63:0]$8958 end - attribute \src "libresoc.v:162563.3-162581.6" - process $proc$libresoc.v:162563$8914 + attribute \src "libresoc.v:164195.3-164213.6" + process $proc$libresoc.v:164195$8962 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$8$next[0:0]$8916 $1\xer_so$8$next[0:0]$8918 - assign $0\xer_so_ok$next[0:0]$8915 $2\xer_so_ok$next[0:0]$8919 - attribute \src "libresoc.v:162564.5-162564.29" + assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 + assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164196.5-164196.29" switch \initial - attribute \src "libresoc.v:162564.9-162564.17" + attribute \src "libresoc.v:164196.9-164196.17" case 1'1 case end @@ -337453,41 +339950,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\xer_so_ok$next[0:0]$8917 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8918 \xer_so$8 + assign $1\xer_so_ok$next[0:0]$8965 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8966 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8919 1'0 + assign $2\xer_so_ok$next[0:0]$8967 1'0 case - assign $2\xer_so_ok$next[0:0]$8919 $1\xer_so_ok$next[0:0]$8917 + assign $2\xer_so_ok$next[0:0]$8967 $1\xer_so_ok$next[0:0]$8965 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8915 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8916 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 end - attribute \src "libresoc.v:162582.3-162600.6" - process $proc$libresoc.v:162582$8920 + attribute \src "libresoc.v:164214.3-164232.6" + process $proc$libresoc.v:164214$8968 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$9$next[1:0]$8922 $1\xer_ov$9$next[1:0]$8924 - assign $0\xer_ov_ok$next[0:0]$8921 $2\xer_ov_ok$next[0:0]$8925 - attribute \src "libresoc.v:162583.5-162583.29" + assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 + assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164215.5-164215.29" switch \initial - attribute \src "libresoc.v:162583.9-162583.17" + attribute \src "libresoc.v:164215.9-164215.17" case 1'1 case end @@ -337497,41 +339994,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\xer_ov_ok$next[0:0]$8923 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8924 \xer_ov$9 + assign $1\xer_ov_ok$next[0:0]$8971 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8972 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8925 1'0 + assign $2\xer_ov_ok$next[0:0]$8973 1'0 case - assign $2\xer_ov_ok$next[0:0]$8925 $1\xer_ov_ok$next[0:0]$8923 + assign $2\xer_ov_ok$next[0:0]$8973 $1\xer_ov_ok$next[0:0]$8971 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8921 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8922 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 end - attribute \src "libresoc.v:162601.3-162619.6" - process $proc$libresoc.v:162601$8926 + attribute \src "libresoc.v:164233.3-164251.6" + process $proc$libresoc.v:164233$8974 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8927 $1\xer_ca$10$next[1:0]$8929 + assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8928 $2\xer_ca_ok$next[0:0]$8931 - attribute \src "libresoc.v:162602.5-162602.29" + assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164234.5-164234.29" switch \initial - attribute \src "libresoc.v:162602.9-162602.17" + attribute \src "libresoc.v:164234.9-164234.17" case 1'1 case end @@ -337541,30 +340038,30 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_ca$10$next[1:0]$8929 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8930 \xer_ca_ok + assign $1\xer_ca$10$next[1:0]$8977 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8978 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8931 1'0 + assign $2\xer_ca_ok$next[0:0]$8979 1'0 case - assign $2\xer_ca_ok$next[0:0]$8931 $1\xer_ca_ok$next[0:0]$8930 + assign $2\xer_ca_ok$next[0:0]$8979 $1\xer_ca_ok$next[0:0]$8978 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8927 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8928 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 end - connect \$22 $and$libresoc.v:162384$8851_Y + connect \$22 $and$libresoc.v:164016$8899_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -337587,279 +340084,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:162645.1-164137.10" +attribute \src "libresoc.v:164277.1-165769.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:164051.3-164092.6" - wire width 4 $0\alu_op__data_len$next[3:0]$9024 - attribute \src "libresoc.v:163827.3-163828.49" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9072 + attribute \src "libresoc.v:165459.3-165460.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 14 $0\alu_op__fn_unit$next[13:0]$9025 - attribute \src "libresoc.v:163797.3-163798.47" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 + attribute \src "libresoc.v:165429.3-165430.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$9026 - attribute \src "libresoc.v:163799.3-163800.61" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 + attribute \src "libresoc.v:165431.3-165432.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__imm_data__ok$next[0:0]$9027 - attribute \src "libresoc.v:163801.3-163802.57" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9075 + attribute \src "libresoc.v:165433.3-165434.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$9028 - attribute \src "libresoc.v:163819.3-163820.55" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9076 + attribute \src "libresoc.v:165451.3-165452.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 32 $0\alu_op__insn$next[31:0]$9029 - attribute \src "libresoc.v:163829.3-163830.41" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $0\alu_op__insn$next[31:0]$9077 + attribute \src "libresoc.v:165461.3-165462.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$9030 - attribute \src "libresoc.v:163795.3-163796.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9078 + attribute \src "libresoc.v:165427.3-165428.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__invert_in$next[0:0]$9031 - attribute \src "libresoc.v:163811.3-163812.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_in$next[0:0]$9079 + attribute \src "libresoc.v:165443.3-165444.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__invert_out$next[0:0]$9032 - attribute \src "libresoc.v:163815.3-163816.53" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_out$next[0:0]$9080 + attribute \src "libresoc.v:165447.3-165448.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__is_32bit$next[0:0]$9033 - attribute \src "libresoc.v:163823.3-163824.49" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_32bit$next[0:0]$9081 + attribute \src "libresoc.v:165455.3-165456.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__is_signed$next[0:0]$9034 - attribute \src "libresoc.v:163825.3-163826.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_signed$next[0:0]$9082 + attribute \src "libresoc.v:165457.3-165458.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__oe__oe$next[0:0]$9035 - attribute \src "libresoc.v:163807.3-163808.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__oe$next[0:0]$9083 + attribute \src "libresoc.v:165439.3-165440.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__oe__ok$next[0:0]$9036 - attribute \src "libresoc.v:163809.3-163810.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__ok$next[0:0]$9084 + attribute \src "libresoc.v:165441.3-165442.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__output_carry$next[0:0]$9037 - attribute \src "libresoc.v:163821.3-163822.57" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__output_carry$next[0:0]$9085 + attribute \src "libresoc.v:165453.3-165454.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__rc__ok$next[0:0]$9038 - attribute \src "libresoc.v:163805.3-163806.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__ok$next[0:0]$9086 + attribute \src "libresoc.v:165437.3-165438.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__rc__rc$next[0:0]$9039 - attribute \src "libresoc.v:163803.3-163804.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__rc$next[0:0]$9087 + attribute \src "libresoc.v:165435.3-165436.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__write_cr0$next[0:0]$9040 - attribute \src "libresoc.v:163817.3-163818.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__write_cr0$next[0:0]$9088 + attribute \src "libresoc.v:165449.3-165450.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__zero_a$next[0:0]$9041 - attribute \src "libresoc.v:163813.3-163814.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__zero_a$next[0:0]$9089 + attribute \src "libresoc.v:165445.3-165446.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire width 4 $0\cr_a$next[3:0]$8993 - attribute \src "libresoc.v:163787.3-163788.25" + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $0\cr_a$next[3:0]$9041 + attribute \src "libresoc.v:165419.3-165420.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire $0\cr_a_ok$next[0:0]$8994 - attribute \src "libresoc.v:163789.3-163790.31" + attribute \src "libresoc.v:165576.3-165594.6" + wire $0\cr_a_ok$next[0:0]$9042 + attribute \src "libresoc.v:165421.3-165422.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162646.7-162646.20" + attribute \src "libresoc.v:164278.7-164278.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164038.3-164050.6" - wire width 2 $0\muxid$next[1:0]$9021 - attribute \src "libresoc.v:163831.3-163832.27" + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $0\muxid$next[1:0]$9069 + attribute \src "libresoc.v:165463.3-165464.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire width 64 $0\o$next[63:0]$9067 - attribute \src "libresoc.v:163791.3-163792.19" + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $0\o$next[63:0]$9115 + attribute \src "libresoc.v:165423.3-165424.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire $0\o_ok$next[0:0]$9068 - attribute \src "libresoc.v:163793.3-163794.25" + attribute \src "libresoc.v:165725.3-165743.6" + wire $0\o_ok$next[0:0]$9116 + attribute \src "libresoc.v:165425.3-165426.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:164020.3-164037.6" - wire $0\r_busy$next[0:0]$9017 - attribute \src "libresoc.v:163833.3-163834.29" + attribute \src "libresoc.v:165652.3-165669.6" + wire $0\r_busy$next[0:0]$9065 + attribute \src "libresoc.v:165465.3-165466.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire width 2 $0\xer_ca$next[1:0]$9000 - attribute \src "libresoc.v:163783.3-163784.29" + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $0\xer_ca$next[1:0]$9048 + attribute \src "libresoc.v:165415.3-165416.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire $0\xer_ca_ok$next[0:0]$8999 - attribute \src "libresoc.v:163785.3-163786.35" + attribute \src "libresoc.v:165595.3-165613.6" + wire $0\xer_ca_ok$next[0:0]$9047 + attribute \src "libresoc.v:165417.3-165418.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire width 2 $0\xer_ov$next[1:0]$9005 - attribute \src "libresoc.v:163779.3-163780.29" + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $0\xer_ov$next[1:0]$9053 + attribute \src "libresoc.v:165411.3-165412.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire $0\xer_ov_ok$next[0:0]$9006 - attribute \src "libresoc.v:163781.3-163782.35" + attribute \src "libresoc.v:165614.3-165632.6" + wire $0\xer_ov_ok$next[0:0]$9054 + attribute \src "libresoc.v:165413.3-165414.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $0\xer_so$next[0:0]$9011 - attribute \src "libresoc.v:163775.3-163776.29" + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so$next[0:0]$9059 + attribute \src "libresoc.v:165407.3-165408.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $0\xer_so_ok$next[0:0]$9012 - attribute \src "libresoc.v:163777.3-163778.35" + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so_ok$next[0:0]$9060 + attribute \src "libresoc.v:165409.3-165410.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 4 $1\alu_op__data_len$next[3:0]$9042 - attribute \src "libresoc.v:162651.13-162651.36" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9090 + attribute \src "libresoc.v:164283.13-164283.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 14 $1\alu_op__fn_unit$next[13:0]$9043 - attribute \src "libresoc.v:162675.14-162675.40" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 + attribute \src "libresoc.v:164307.14-164307.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$9044 - attribute \src "libresoc.v:162714.14-162714.59" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 + attribute \src "libresoc.v:164346.14-164346.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9045 - attribute \src "libresoc.v:162723.7-162723.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9093 + attribute \src "libresoc.v:164355.7-164355.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9046 - attribute \src "libresoc.v:162736.13-162736.39" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9094 + attribute \src "libresoc.v:164368.13-164368.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 32 $1\alu_op__insn$next[31:0]$9047 - attribute \src "libresoc.v:162753.14-162753.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $1\alu_op__insn$next[31:0]$9095 + attribute \src "libresoc.v:164385.14-164385.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9048 - attribute \src "libresoc.v:162837.13-162837.38" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9096 + attribute \src "libresoc.v:164469.13-164469.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__invert_in$next[0:0]$9049 - attribute \src "libresoc.v:162996.7-162996.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_in$next[0:0]$9097 + attribute \src "libresoc.v:164628.7-164628.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__invert_out$next[0:0]$9050 - attribute \src "libresoc.v:163005.7-163005.32" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_out$next[0:0]$9098 + attribute \src "libresoc.v:164637.7-164637.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__is_32bit$next[0:0]$9051 - attribute \src "libresoc.v:163014.7-163014.30" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_32bit$next[0:0]$9099 + attribute \src "libresoc.v:164646.7-164646.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__is_signed$next[0:0]$9052 - attribute \src "libresoc.v:163023.7-163023.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_signed$next[0:0]$9100 + attribute \src "libresoc.v:164655.7-164655.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__oe__oe$next[0:0]$9053 - attribute \src "libresoc.v:163032.7-163032.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__oe$next[0:0]$9101 + attribute \src "libresoc.v:164664.7-164664.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__oe__ok$next[0:0]$9054 - attribute \src "libresoc.v:163041.7-163041.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__ok$next[0:0]$9102 + attribute \src "libresoc.v:164673.7-164673.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__output_carry$next[0:0]$9055 - attribute \src "libresoc.v:163050.7-163050.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__output_carry$next[0:0]$9103 + attribute \src "libresoc.v:164682.7-164682.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__rc__ok$next[0:0]$9056 - attribute \src "libresoc.v:163059.7-163059.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__ok$next[0:0]$9104 + attribute \src "libresoc.v:164691.7-164691.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__rc__rc$next[0:0]$9057 - attribute \src "libresoc.v:163068.7-163068.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__rc$next[0:0]$9105 + attribute \src "libresoc.v:164700.7-164700.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__write_cr0$next[0:0]$9058 - attribute \src "libresoc.v:163077.7-163077.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__write_cr0$next[0:0]$9106 + attribute \src "libresoc.v:164709.7-164709.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__zero_a$next[0:0]$9059 - attribute \src "libresoc.v:163086.7-163086.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__zero_a$next[0:0]$9107 + attribute \src "libresoc.v:164718.7-164718.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire width 4 $1\cr_a$next[3:0]$8995 - attribute \src "libresoc.v:163099.13-163099.24" + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $1\cr_a$next[3:0]$9043 + attribute \src "libresoc.v:164731.13-164731.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire $1\cr_a_ok$next[0:0]$8996 - attribute \src "libresoc.v:163106.7-163106.21" + attribute \src "libresoc.v:165576.3-165594.6" + wire $1\cr_a_ok$next[0:0]$9044 + attribute \src "libresoc.v:164738.7-164738.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:164038.3-164050.6" - wire width 2 $1\muxid$next[1:0]$9022 - attribute \src "libresoc.v:163683.13-163683.25" + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165315.13-165315.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire width 64 $1\o$next[63:0]$9069 - attribute \src "libresoc.v:163698.14-163698.38" + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $1\o$next[63:0]$9117 + attribute \src "libresoc.v:165330.14-165330.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire $1\o_ok$next[0:0]$9070 - attribute \src "libresoc.v:163705.7-163705.18" + attribute \src "libresoc.v:165725.3-165743.6" + wire $1\o_ok$next[0:0]$9118 + attribute \src "libresoc.v:165337.7-165337.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:164020.3-164037.6" - wire $1\r_busy$next[0:0]$9018 - attribute \src "libresoc.v:163719.7-163719.20" + attribute \src "libresoc.v:165652.3-165669.6" + wire $1\r_busy$next[0:0]$9066 + attribute \src "libresoc.v:165351.7-165351.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire width 2 $1\xer_ca$next[1:0]$9002 - attribute \src "libresoc.v:163728.13-163728.26" + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $1\xer_ca$next[1:0]$9050 + attribute \src "libresoc.v:165360.13-165360.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire $1\xer_ca_ok$next[0:0]$9001 - attribute \src "libresoc.v:163737.7-163737.23" + attribute \src "libresoc.v:165595.3-165613.6" + wire $1\xer_ca_ok$next[0:0]$9049 + attribute \src "libresoc.v:165369.7-165369.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire width 2 $1\xer_ov$next[1:0]$9007 - attribute \src "libresoc.v:163744.13-163744.26" + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $1\xer_ov$next[1:0]$9055 + attribute \src "libresoc.v:165376.13-165376.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire $1\xer_ov_ok$next[0:0]$9008 - attribute \src "libresoc.v:163751.7-163751.23" + attribute \src "libresoc.v:165614.3-165632.6" + wire $1\xer_ov_ok$next[0:0]$9056 + attribute \src "libresoc.v:165383.7-165383.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $1\xer_so$next[0:0]$9013 - attribute \src "libresoc.v:163758.7-163758.20" + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so$next[0:0]$9061 + attribute \src "libresoc.v:165390.7-165390.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $1\xer_so_ok$next[0:0]$9014 - attribute \src "libresoc.v:163767.7-163767.23" + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so_ok$next[0:0]$9062 + attribute \src "libresoc.v:165399.7-165399.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9060 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9061 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__oe__oe$next[0:0]$9062 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__oe__ok$next[0:0]$9063 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__rc__ok$next[0:0]$9064 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__rc__rc$next[0:0]$9065 - attribute \src "libresoc.v:163944.3-163962.6" - wire $2\cr_a_ok$next[0:0]$8997 - attribute \src "libresoc.v:164093.3-164111.6" - wire $2\o_ok$next[0:0]$9071 - attribute \src "libresoc.v:164020.3-164037.6" - wire $2\r_busy$next[0:0]$9019 - attribute \src "libresoc.v:163963.3-163981.6" - wire $2\xer_ca_ok$next[0:0]$9003 - attribute \src "libresoc.v:163982.3-164000.6" - wire $2\xer_ov_ok$next[0:0]$9009 - attribute \src "libresoc.v:164001.3-164019.6" - wire $2\xer_so_ok$next[0:0]$9015 - attribute \src "libresoc.v:163774.18-163774.118" - wire $and$libresoc.v:163774$8961_Y + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9109 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__oe$next[0:0]$9110 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__ok$next[0:0]$9111 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__ok$next[0:0]$9112 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165576.3-165594.6" + wire $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165725.3-165743.6" + wire $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165652.3-165669.6" + wire $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165595.3-165613.6" + wire $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165614.3-165632.6" + wire $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165633.3-165651.6" + wire $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165406.18-165406.118" + wire $and$libresoc.v:165406$9009_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338288,9 +340785,9 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -338304,7 +340801,7 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:162646.7-162646.15" + attribute \src "libresoc.v:164278.7-164278.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -338961,7 +341458,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163774$8961 + cell $and $and$libresoc.v:165406$9009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -338969,10 +341466,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:163774$8961_Y + connect \Y $and$libresoc.v:165406$9009_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163835.11-163882.4" + attribute \src "libresoc.v:165467.11-165514.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -339022,7 +341519,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163883.8-163935.4" + attribute \src "libresoc.v:165515.8-165567.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -339077,487 +341574,487 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163936.9-163939.4" + attribute \src "libresoc.v:165568.9-165571.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163940.9-163943.4" + attribute \src "libresoc.v:165572.9-165575.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162646.7-162646.20" - process $proc$libresoc.v:162646$9072 + attribute \src "libresoc.v:164278.7-164278.20" + process $proc$libresoc.v:164278$9120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162651.13-162651.36" - process $proc$libresoc.v:162651$9073 + attribute \src "libresoc.v:164283.13-164283.36" + process $proc$libresoc.v:164283$9121 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:162675.14-162675.40" - process $proc$libresoc.v:162675$9074 + attribute \src "libresoc.v:164307.14-164307.40" + process $proc$libresoc.v:164307$9122 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:162714.14-162714.59" - process $proc$libresoc.v:162714$9075 + attribute \src "libresoc.v:164346.14-164346.59" + process $proc$libresoc.v:164346$9123 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:162723.7-162723.34" - process $proc$libresoc.v:162723$9076 + attribute \src "libresoc.v:164355.7-164355.34" + process $proc$libresoc.v:164355$9124 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:162736.13-162736.39" - process $proc$libresoc.v:162736$9077 + attribute \src "libresoc.v:164368.13-164368.39" + process $proc$libresoc.v:164368$9125 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:162753.14-162753.34" - process $proc$libresoc.v:162753$9078 + attribute \src "libresoc.v:164385.14-164385.34" + process $proc$libresoc.v:164385$9126 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:162837.13-162837.38" - process $proc$libresoc.v:162837$9079 + attribute \src "libresoc.v:164469.13-164469.38" + process $proc$libresoc.v:164469$9127 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:162996.7-162996.31" - process $proc$libresoc.v:162996$9080 + attribute \src "libresoc.v:164628.7-164628.31" + process $proc$libresoc.v:164628$9128 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:163005.7-163005.32" - process $proc$libresoc.v:163005$9081 + attribute \src "libresoc.v:164637.7-164637.32" + process $proc$libresoc.v:164637$9129 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:163014.7-163014.30" - process $proc$libresoc.v:163014$9082 + attribute \src "libresoc.v:164646.7-164646.30" + process $proc$libresoc.v:164646$9130 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:163023.7-163023.31" - process $proc$libresoc.v:163023$9083 + attribute \src "libresoc.v:164655.7-164655.31" + process $proc$libresoc.v:164655$9131 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:163032.7-163032.28" - process $proc$libresoc.v:163032$9084 + attribute \src "libresoc.v:164664.7-164664.28" + process $proc$libresoc.v:164664$9132 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:163041.7-163041.28" - process $proc$libresoc.v:163041$9085 + attribute \src "libresoc.v:164673.7-164673.28" + process $proc$libresoc.v:164673$9133 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:163050.7-163050.34" - process $proc$libresoc.v:163050$9086 + attribute \src "libresoc.v:164682.7-164682.34" + process $proc$libresoc.v:164682$9134 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:163059.7-163059.28" - process $proc$libresoc.v:163059$9087 + attribute \src "libresoc.v:164691.7-164691.28" + process $proc$libresoc.v:164691$9135 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:163068.7-163068.28" - process $proc$libresoc.v:163068$9088 + attribute \src "libresoc.v:164700.7-164700.28" + process $proc$libresoc.v:164700$9136 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:163077.7-163077.31" - process $proc$libresoc.v:163077$9089 + attribute \src "libresoc.v:164709.7-164709.31" + process $proc$libresoc.v:164709$9137 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:163086.7-163086.28" - process $proc$libresoc.v:163086$9090 + attribute \src "libresoc.v:164718.7-164718.28" + process $proc$libresoc.v:164718$9138 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:163099.13-163099.24" - process $proc$libresoc.v:163099$9091 + attribute \src "libresoc.v:164731.13-164731.24" + process $proc$libresoc.v:164731$9139 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:163106.7-163106.21" - process $proc$libresoc.v:163106$9092 + attribute \src "libresoc.v:164738.7-164738.21" + process $proc$libresoc.v:164738$9140 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:163683.13-163683.25" - process $proc$libresoc.v:163683$9093 + attribute \src "libresoc.v:165315.13-165315.25" + process $proc$libresoc.v:165315$9141 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:163698.14-163698.38" - process $proc$libresoc.v:163698$9094 + attribute \src "libresoc.v:165330.14-165330.38" + process $proc$libresoc.v:165330$9142 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163705.7-163705.18" - process $proc$libresoc.v:163705$9095 + attribute \src "libresoc.v:165337.7-165337.18" + process $proc$libresoc.v:165337$9143 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163719.7-163719.20" - process $proc$libresoc.v:163719$9096 + attribute \src "libresoc.v:165351.7-165351.20" + process $proc$libresoc.v:165351$9144 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163728.13-163728.26" - process $proc$libresoc.v:163728$9097 + attribute \src "libresoc.v:165360.13-165360.26" + process $proc$libresoc.v:165360$9145 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:163737.7-163737.23" - process $proc$libresoc.v:163737$9098 + attribute \src "libresoc.v:165369.7-165369.23" + process $proc$libresoc.v:165369$9146 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163744.13-163744.26" - process $proc$libresoc.v:163744$9099 + attribute \src "libresoc.v:165376.13-165376.26" + process $proc$libresoc.v:165376$9147 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:163751.7-163751.23" - process $proc$libresoc.v:163751$9100 + attribute \src "libresoc.v:165383.7-165383.23" + process $proc$libresoc.v:165383$9148 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:163758.7-163758.20" - process $proc$libresoc.v:163758$9101 + attribute \src "libresoc.v:165390.7-165390.20" + process $proc$libresoc.v:165390$9149 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:163767.7-163767.23" - process $proc$libresoc.v:163767$9102 + attribute \src "libresoc.v:165399.7-165399.23" + process $proc$libresoc.v:165399$9150 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:163775.3-163776.29" - process $proc$libresoc.v:163775$8962 + attribute \src "libresoc.v:165407.3-165408.29" + process $proc$libresoc.v:165407$9010 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:163777.3-163778.35" - process $proc$libresoc.v:163777$8963 + attribute \src "libresoc.v:165409.3-165410.35" + process $proc$libresoc.v:165409$9011 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:163779.3-163780.29" - process $proc$libresoc.v:163779$8964 + attribute \src "libresoc.v:165411.3-165412.29" + process $proc$libresoc.v:165411$9012 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:163781.3-163782.35" - process $proc$libresoc.v:163781$8965 + attribute \src "libresoc.v:165413.3-165414.35" + process $proc$libresoc.v:165413$9013 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:163783.3-163784.29" - process $proc$libresoc.v:163783$8966 + attribute \src "libresoc.v:165415.3-165416.29" + process $proc$libresoc.v:165415$9014 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:163785.3-163786.35" - process $proc$libresoc.v:163785$8967 + attribute \src "libresoc.v:165417.3-165418.35" + process $proc$libresoc.v:165417$9015 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163787.3-163788.25" - process $proc$libresoc.v:163787$8968 + attribute \src "libresoc.v:165419.3-165420.25" + process $proc$libresoc.v:165419$9016 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:163789.3-163790.31" - process $proc$libresoc.v:163789$8969 + attribute \src "libresoc.v:165421.3-165422.31" + process $proc$libresoc.v:165421$9017 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:163791.3-163792.19" - process $proc$libresoc.v:163791$8970 + attribute \src "libresoc.v:165423.3-165424.19" + process $proc$libresoc.v:165423$9018 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:163793.3-163794.25" - process $proc$libresoc.v:163793$8971 + attribute \src "libresoc.v:165425.3-165426.25" + process $proc$libresoc.v:165425$9019 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:163795.3-163796.51" - process $proc$libresoc.v:163795$8972 + attribute \src "libresoc.v:165427.3-165428.51" + process $proc$libresoc.v:165427$9020 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:163797.3-163798.47" - process $proc$libresoc.v:163797$8973 + attribute \src "libresoc.v:165429.3-165430.47" + process $proc$libresoc.v:165429$9021 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:163799.3-163800.61" - process $proc$libresoc.v:163799$8974 + attribute \src "libresoc.v:165431.3-165432.61" + process $proc$libresoc.v:165431$9022 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:163801.3-163802.57" - process $proc$libresoc.v:163801$8975 + attribute \src "libresoc.v:165433.3-165434.57" + process $proc$libresoc.v:165433$9023 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:163803.3-163804.45" - process $proc$libresoc.v:163803$8976 + attribute \src "libresoc.v:165435.3-165436.45" + process $proc$libresoc.v:165435$9024 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:163805.3-163806.45" - process $proc$libresoc.v:163805$8977 + attribute \src "libresoc.v:165437.3-165438.45" + process $proc$libresoc.v:165437$9025 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:163807.3-163808.45" - process $proc$libresoc.v:163807$8978 + attribute \src "libresoc.v:165439.3-165440.45" + process $proc$libresoc.v:165439$9026 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:163809.3-163810.45" - process $proc$libresoc.v:163809$8979 + attribute \src "libresoc.v:165441.3-165442.45" + process $proc$libresoc.v:165441$9027 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:163811.3-163812.51" - process $proc$libresoc.v:163811$8980 + attribute \src "libresoc.v:165443.3-165444.51" + process $proc$libresoc.v:165443$9028 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:163813.3-163814.45" - process $proc$libresoc.v:163813$8981 + attribute \src "libresoc.v:165445.3-165446.45" + process $proc$libresoc.v:165445$9029 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:163815.3-163816.53" - process $proc$libresoc.v:163815$8982 + attribute \src "libresoc.v:165447.3-165448.53" + process $proc$libresoc.v:165447$9030 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:163817.3-163818.51" - process $proc$libresoc.v:163817$8983 + attribute \src "libresoc.v:165449.3-165450.51" + process $proc$libresoc.v:165449$9031 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:163819.3-163820.55" - process $proc$libresoc.v:163819$8984 + attribute \src "libresoc.v:165451.3-165452.55" + process $proc$libresoc.v:165451$9032 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:163821.3-163822.57" - process $proc$libresoc.v:163821$8985 + attribute \src "libresoc.v:165453.3-165454.57" + process $proc$libresoc.v:165453$9033 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:163823.3-163824.49" - process $proc$libresoc.v:163823$8986 + attribute \src "libresoc.v:165455.3-165456.49" + process $proc$libresoc.v:165455$9034 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:163825.3-163826.51" - process $proc$libresoc.v:163825$8987 + attribute \src "libresoc.v:165457.3-165458.51" + process $proc$libresoc.v:165457$9035 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:163827.3-163828.49" - process $proc$libresoc.v:163827$8988 + attribute \src "libresoc.v:165459.3-165460.49" + process $proc$libresoc.v:165459$9036 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:163829.3-163830.41" - process $proc$libresoc.v:163829$8989 + attribute \src "libresoc.v:165461.3-165462.41" + process $proc$libresoc.v:165461$9037 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:163831.3-163832.27" - process $proc$libresoc.v:163831$8990 + attribute \src "libresoc.v:165463.3-165464.27" + process $proc$libresoc.v:165463$9038 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:163833.3-163834.29" - process $proc$libresoc.v:163833$8991 + attribute \src "libresoc.v:165465.3-165466.29" + process $proc$libresoc.v:165465$9039 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163944.3-163962.6" - process $proc$libresoc.v:163944$8992 + attribute \src "libresoc.v:165576.3-165594.6" + process $proc$libresoc.v:165576$9040 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8993 $1\cr_a$next[3:0]$8995 + assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 assign { } { } - assign $0\cr_a_ok$next[0:0]$8994 $2\cr_a_ok$next[0:0]$8997 - attribute \src "libresoc.v:163945.5-163945.29" + assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165577.5-165577.29" switch \initial - attribute \src "libresoc.v:163945.9-163945.17" + attribute \src "libresoc.v:165577.9-165577.17" case 1'1 case end @@ -339567,41 +342064,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\cr_a$next[3:0]$8995 \cr_a - assign $1\cr_a_ok$next[0:0]$8996 \cr_a_ok + assign $1\cr_a$next[3:0]$9043 \cr_a + assign $1\cr_a_ok$next[0:0]$9044 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8997 1'0 + assign $2\cr_a_ok$next[0:0]$9045 1'0 case - assign $2\cr_a_ok$next[0:0]$8997 $1\cr_a_ok$next[0:0]$8996 + assign $2\cr_a_ok$next[0:0]$9045 $1\cr_a_ok$next[0:0]$9044 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8993 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8994 + update \cr_a$next $0\cr_a$next[3:0]$9041 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 end - attribute \src "libresoc.v:163963.3-163981.6" - process $proc$libresoc.v:163963$8998 + attribute \src "libresoc.v:165595.3-165613.6" + process $proc$libresoc.v:165595$9046 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9000 $1\xer_ca$next[1:0]$9002 - assign $0\xer_ca_ok$next[0:0]$8999 $2\xer_ca_ok$next[0:0]$9003 - attribute \src "libresoc.v:163964.5-163964.29" + assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 + assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165596.5-165596.29" switch \initial - attribute \src "libresoc.v:163964.9-163964.17" + attribute \src "libresoc.v:165596.9-165596.17" case 1'1 case end @@ -339611,41 +342108,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } case - assign $1\xer_ca_ok$next[0:0]$9001 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9002 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9049 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9050 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9003 1'0 + assign $2\xer_ca_ok$next[0:0]$9051 1'0 case - assign $2\xer_ca_ok$next[0:0]$9003 $1\xer_ca_ok$next[0:0]$9001 + assign $2\xer_ca_ok$next[0:0]$9051 $1\xer_ca_ok$next[0:0]$9049 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8999 - update \xer_ca$next $0\xer_ca$next[1:0]$9000 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 + update \xer_ca$next $0\xer_ca$next[1:0]$9048 end - attribute \src "libresoc.v:163982.3-164000.6" - process $proc$libresoc.v:163982$9004 + attribute \src "libresoc.v:165614.3-165632.6" + process $proc$libresoc.v:165614$9052 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9005 $1\xer_ov$next[1:0]$9007 + assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9006 $2\xer_ov_ok$next[0:0]$9009 - attribute \src "libresoc.v:163983.5-163983.29" + assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165615.5-165615.29" switch \initial - attribute \src "libresoc.v:163983.9-163983.17" + attribute \src "libresoc.v:165615.9-165615.17" case 1'1 case end @@ -339655,41 +342152,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } case - assign $1\xer_ov$next[1:0]$9007 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9008 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9055 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9056 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9009 1'0 + assign $2\xer_ov_ok$next[0:0]$9057 1'0 case - assign $2\xer_ov_ok$next[0:0]$9009 $1\xer_ov_ok$next[0:0]$9008 + assign $2\xer_ov_ok$next[0:0]$9057 $1\xer_ov_ok$next[0:0]$9056 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9005 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9006 + update \xer_ov$next $0\xer_ov$next[1:0]$9053 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 end - attribute \src "libresoc.v:164001.3-164019.6" - process $proc$libresoc.v:164001$9010 + attribute \src "libresoc.v:165633.3-165651.6" + process $proc$libresoc.v:165633$9058 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9011 $1\xer_so$next[0:0]$9013 + assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 assign { } { } - assign $0\xer_so_ok$next[0:0]$9012 $2\xer_so_ok$next[0:0]$9015 - attribute \src "libresoc.v:164002.5-164002.29" + assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165634.5-165634.29" switch \initial - attribute \src "libresoc.v:164002.9-164002.17" + attribute \src "libresoc.v:165634.9-165634.17" case 1'1 case end @@ -339699,38 +342196,38 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } case - assign $1\xer_so$next[0:0]$9013 \xer_so - assign $1\xer_so_ok$next[0:0]$9014 \xer_so_ok + assign $1\xer_so$next[0:0]$9061 \xer_so + assign $1\xer_so_ok$next[0:0]$9062 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9015 1'0 + assign $2\xer_so_ok$next[0:0]$9063 1'0 case - assign $2\xer_so_ok$next[0:0]$9015 $1\xer_so_ok$next[0:0]$9014 + assign $2\xer_so_ok$next[0:0]$9063 $1\xer_so_ok$next[0:0]$9062 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9011 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9012 + update \xer_so$next $0\xer_so$next[0:0]$9059 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 end - attribute \src "libresoc.v:164020.3-164037.6" - process $proc$libresoc.v:164020$9016 + attribute \src "libresoc.v:165652.3-165669.6" + process $proc$libresoc.v:165652$9064 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9017 $2\r_busy$next[0:0]$9019 - attribute \src "libresoc.v:164021.5-164021.29" + assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165653.5-165653.29" switch \initial - attribute \src "libresoc.v:164021.9-164021.17" + attribute \src "libresoc.v:165653.9-165653.17" case 1'1 case end @@ -339739,34 +342236,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9018 1'1 + assign $1\r_busy$next[0:0]$9066 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9018 1'0 + assign $1\r_busy$next[0:0]$9066 1'0 case - assign $1\r_busy$next[0:0]$9018 \r_busy + assign $1\r_busy$next[0:0]$9066 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9019 1'0 + assign $2\r_busy$next[0:0]$9067 1'0 case - assign $2\r_busy$next[0:0]$9019 $1\r_busy$next[0:0]$9018 + assign $2\r_busy$next[0:0]$9067 $1\r_busy$next[0:0]$9066 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9017 + update \r_busy$next $0\r_busy$next[0:0]$9065 end - attribute \src "libresoc.v:164038.3-164050.6" - process $proc$libresoc.v:164038$9020 + attribute \src "libresoc.v:165670.3-165682.6" + process $proc$libresoc.v:165670$9068 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9021 $1\muxid$next[1:0]$9022 - attribute \src "libresoc.v:164039.5-164039.29" + assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165671.5-165671.29" switch \initial - attribute \src "libresoc.v:164039.9-164039.17" + attribute \src "libresoc.v:165671.9-165671.17" case 1'1 case end @@ -339775,19 +342272,19 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9022 \muxid$69 + assign $1\muxid$next[1:0]$9070 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9022 \muxid$69 + assign $1\muxid$next[1:0]$9070 \muxid$69 case - assign $1\muxid$next[1:0]$9022 \muxid + assign $1\muxid$next[1:0]$9070 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9021 + update \muxid$next $0\muxid$next[1:0]$9069 end - attribute \src "libresoc.v:164051.3-164092.6" - process $proc$libresoc.v:164051$9023 + attribute \src "libresoc.v:165683.3-165724.6" + process $proc$libresoc.v:165683$9071 assign { } { } assign { } { } assign { } { } @@ -339824,33 +342321,33 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$next[3:0]$9024 $1\alu_op__data_len$next[3:0]$9042 - assign $0\alu_op__fn_unit$next[13:0]$9025 $1\alu_op__fn_unit$next[13:0]$9043 + assign $0\alu_op__data_len$next[3:0]$9072 $1\alu_op__data_len$next[3:0]$9090 + assign $0\alu_op__fn_unit$next[13:0]$9073 $1\alu_op__fn_unit$next[13:0]$9091 assign { } { } assign { } { } - assign $0\alu_op__input_carry$next[1:0]$9028 $1\alu_op__input_carry$next[1:0]$9046 - assign $0\alu_op__insn$next[31:0]$9029 $1\alu_op__insn$next[31:0]$9047 - assign $0\alu_op__insn_type$next[6:0]$9030 $1\alu_op__insn_type$next[6:0]$9048 - assign $0\alu_op__invert_in$next[0:0]$9031 $1\alu_op__invert_in$next[0:0]$9049 - assign $0\alu_op__invert_out$next[0:0]$9032 $1\alu_op__invert_out$next[0:0]$9050 - assign $0\alu_op__is_32bit$next[0:0]$9033 $1\alu_op__is_32bit$next[0:0]$9051 - assign $0\alu_op__is_signed$next[0:0]$9034 $1\alu_op__is_signed$next[0:0]$9052 + assign $0\alu_op__input_carry$next[1:0]$9076 $1\alu_op__input_carry$next[1:0]$9094 + assign $0\alu_op__insn$next[31:0]$9077 $1\alu_op__insn$next[31:0]$9095 + assign $0\alu_op__insn_type$next[6:0]$9078 $1\alu_op__insn_type$next[6:0]$9096 + assign $0\alu_op__invert_in$next[0:0]$9079 $1\alu_op__invert_in$next[0:0]$9097 + assign $0\alu_op__invert_out$next[0:0]$9080 $1\alu_op__invert_out$next[0:0]$9098 + assign $0\alu_op__is_32bit$next[0:0]$9081 $1\alu_op__is_32bit$next[0:0]$9099 + assign $0\alu_op__is_signed$next[0:0]$9082 $1\alu_op__is_signed$next[0:0]$9100 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$9037 $1\alu_op__output_carry$next[0:0]$9055 + assign $0\alu_op__output_carry$next[0:0]$9085 $1\alu_op__output_carry$next[0:0]$9103 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$9040 $1\alu_op__write_cr0$next[0:0]$9058 - assign $0\alu_op__zero_a$next[0:0]$9041 $1\alu_op__zero_a$next[0:0]$9059 - assign $0\alu_op__imm_data__data$next[63:0]$9026 $2\alu_op__imm_data__data$next[63:0]$9060 - assign $0\alu_op__imm_data__ok$next[0:0]$9027 $2\alu_op__imm_data__ok$next[0:0]$9061 - assign $0\alu_op__oe__oe$next[0:0]$9035 $2\alu_op__oe__oe$next[0:0]$9062 - assign $0\alu_op__oe__ok$next[0:0]$9036 $2\alu_op__oe__ok$next[0:0]$9063 - assign $0\alu_op__rc__ok$next[0:0]$9038 $2\alu_op__rc__ok$next[0:0]$9064 - assign $0\alu_op__rc__rc$next[0:0]$9039 $2\alu_op__rc__rc$next[0:0]$9065 - attribute \src "libresoc.v:164052.5-164052.29" + assign $0\alu_op__write_cr0$next[0:0]$9088 $1\alu_op__write_cr0$next[0:0]$9106 + assign $0\alu_op__zero_a$next[0:0]$9089 $1\alu_op__zero_a$next[0:0]$9107 + assign $0\alu_op__imm_data__data$next[63:0]$9074 $2\alu_op__imm_data__data$next[63:0]$9108 + assign $0\alu_op__imm_data__ok$next[0:0]$9075 $2\alu_op__imm_data__ok$next[0:0]$9109 + assign $0\alu_op__oe__oe$next[0:0]$9083 $2\alu_op__oe__oe$next[0:0]$9110 + assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 + assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 + assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165684.5-165684.29" switch \initial - attribute \src "libresoc.v:164052.9-164052.17" + attribute \src "libresoc.v:165684.9-165684.17" case 1'1 case end @@ -339876,7 +342373,7 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -339897,26 +342394,26 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case - assign $1\alu_op__data_len$next[3:0]$9042 \alu_op__data_len - assign $1\alu_op__fn_unit$next[13:0]$9043 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$9044 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9045 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9046 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9047 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9048 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9049 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9050 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9051 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9052 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9053 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9054 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9055 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9056 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9057 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9058 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9059 \alu_op__zero_a + assign $1\alu_op__data_len$next[3:0]$9090 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9091 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9092 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9093 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9094 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9095 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9096 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9097 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9098 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9099 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9100 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9101 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9102 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9103 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9104 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9105 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9106 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9107 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -339928,52 +342425,52 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9060 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9061 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9065 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9064 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9062 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9063 1'0 + assign $2\alu_op__imm_data__data$next[63:0]$9108 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9113 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9112 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9110 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9111 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9060 $1\alu_op__imm_data__data$next[63:0]$9044 - assign $2\alu_op__imm_data__ok$next[0:0]$9061 $1\alu_op__imm_data__ok$next[0:0]$9045 - assign $2\alu_op__oe__oe$next[0:0]$9062 $1\alu_op__oe__oe$next[0:0]$9053 - assign $2\alu_op__oe__ok$next[0:0]$9063 $1\alu_op__oe__ok$next[0:0]$9054 - assign $2\alu_op__rc__ok$next[0:0]$9064 $1\alu_op__rc__ok$next[0:0]$9056 - assign $2\alu_op__rc__rc$next[0:0]$9065 $1\alu_op__rc__rc$next[0:0]$9057 + assign $2\alu_op__imm_data__data$next[63:0]$9108 $1\alu_op__imm_data__data$next[63:0]$9092 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 $1\alu_op__imm_data__ok$next[0:0]$9093 + assign $2\alu_op__oe__oe$next[0:0]$9110 $1\alu_op__oe__oe$next[0:0]$9101 + assign $2\alu_op__oe__ok$next[0:0]$9111 $1\alu_op__oe__ok$next[0:0]$9102 + assign $2\alu_op__rc__ok$next[0:0]$9112 $1\alu_op__rc__ok$next[0:0]$9104 + assign $2\alu_op__rc__rc$next[0:0]$9113 $1\alu_op__rc__rc$next[0:0]$9105 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9024 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9025 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9026 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9027 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9028 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9029 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9030 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9031 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9032 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9033 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9034 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9035 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9036 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9037 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9038 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9039 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9040 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9041 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9072 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9073 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9074 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9075 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9076 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9077 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9078 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9079 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9080 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9081 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9082 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9083 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9084 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9085 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9086 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9087 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 end - attribute \src "libresoc.v:164093.3-164111.6" - process $proc$libresoc.v:164093$9066 + attribute \src "libresoc.v:165725.3-165743.6" + process $proc$libresoc.v:165725$9114 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9067 $1\o$next[63:0]$9069 + assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 assign { } { } - assign $0\o_ok$next[0:0]$9068 $2\o_ok$next[0:0]$9071 - attribute \src "libresoc.v:164094.5-164094.29" + assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165726.5-165726.29" switch \initial - attribute \src "libresoc.v:164094.9-164094.17" + attribute \src "libresoc.v:165726.9-165726.17" case 1'1 case end @@ -339983,30 +342480,30 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } case - assign $1\o$next[63:0]$9069 \o - assign $1\o_ok$next[0:0]$9070 \o_ok + assign $1\o$next[63:0]$9117 \o + assign $1\o_ok$next[0:0]$9118 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9071 1'0 + assign $2\o_ok$next[0:0]$9119 1'0 case - assign $2\o_ok$next[0:0]$9071 $1\o_ok$next[0:0]$9070 + assign $2\o_ok$next[0:0]$9119 $1\o_ok$next[0:0]$9118 end sync always - update \o$next $0\o$next[63:0]$9067 - update \o_ok$next $0\o_ok$next[0:0]$9068 + update \o$next $0\o$next[63:0]$9115 + update \o_ok$next $0\o_ok$next[0:0]$9116 end - connect \$67 $and$libresoc.v:163774$8961_Y + connect \$67 $and$libresoc.v:165406$9009_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -340033,258 +342530,258 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:164141.1-165577.10" +attribute \src "libresoc.v:165773.1-167209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:165510.3-165528.6" - wire width 4 $0\cr_a$next[3:0]$9192 - attribute \src "libresoc.v:165252.3-165253.25" + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $0\cr_a$next[3:0]$9240 + attribute \src "libresoc.v:166884.3-166885.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $0\cr_a_ok$next[0:0]$9193 - attribute \src "libresoc.v:165254.3-165255.31" + attribute \src "libresoc.v:167142.3-167160.6" + wire $0\cr_a_ok$next[0:0]$9241 + attribute \src "libresoc.v:166886.3-166887.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:164142.7-164142.20" + attribute \src "libresoc.v:165774.7-165774.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165437.3-165449.6" - wire width 2 $0\muxid$next[1:0]$9142 - attribute \src "libresoc.v:165294.3-165295.27" + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $0\muxid$next[1:0]$9190 + attribute \src "libresoc.v:166926.3-166927.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire width 64 $0\o$next[63:0]$9186 - attribute \src "libresoc.v:165256.3-165257.19" + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $0\o$next[63:0]$9234 + attribute \src "libresoc.v:166888.3-166889.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire $0\o_ok$next[0:0]$9187 - attribute \src "libresoc.v:165258.3-165259.25" + attribute \src "libresoc.v:167123.3-167141.6" + wire $0\o_ok$next[0:0]$9235 + attribute \src "libresoc.v:166890.3-166891.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165419.3-165436.6" - wire $0\r_busy$next[0:0]$9138 - attribute \src "libresoc.v:165296.3-165297.29" + attribute \src "libresoc.v:167051.3-167068.6" + wire $0\r_busy$next[0:0]$9186 + attribute \src "libresoc.v:166928.3-166929.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 14 $0\sr_op__fn_unit$next[13:0]$9145 - attribute \src "libresoc.v:165262.3-165263.45" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 + attribute \src "libresoc.v:166894.3-166895.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9146 - attribute \src "libresoc.v:165264.3-165265.59" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 + attribute \src "libresoc.v:166896.3-166897.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9147 - attribute \src "libresoc.v:165266.3-165267.55" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9195 + attribute \src "libresoc.v:166898.3-166899.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9148 - attribute \src "libresoc.v:165280.3-165281.53" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9196 + attribute \src "libresoc.v:166912.3-166913.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__input_cr$next[0:0]$9149 - attribute \src "libresoc.v:165284.3-165285.47" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__input_cr$next[0:0]$9197 + attribute \src "libresoc.v:166916.3-166917.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 32 $0\sr_op__insn$next[31:0]$9150 - attribute \src "libresoc.v:165292.3-165293.39" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $0\sr_op__insn$next[31:0]$9198 + attribute \src "libresoc.v:166924.3-166925.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9151 - attribute \src "libresoc.v:165260.3-165261.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9199 + attribute \src "libresoc.v:166892.3-166893.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__invert_in$next[0:0]$9152 - attribute \src "libresoc.v:165278.3-165279.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__invert_in$next[0:0]$9200 + attribute \src "libresoc.v:166910.3-166911.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__is_32bit$next[0:0]$9153 - attribute \src "libresoc.v:165288.3-165289.47" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_32bit$next[0:0]$9201 + attribute \src "libresoc.v:166920.3-166921.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__is_signed$next[0:0]$9154 - attribute \src "libresoc.v:165290.3-165291.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_signed$next[0:0]$9202 + attribute \src "libresoc.v:166922.3-166923.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__oe__oe$next[0:0]$9155 - attribute \src "libresoc.v:165272.3-165273.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__oe$next[0:0]$9203 + attribute \src "libresoc.v:166904.3-166905.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__oe__ok$next[0:0]$9156 - attribute \src "libresoc.v:165274.3-165275.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__ok$next[0:0]$9204 + attribute \src "libresoc.v:166906.3-166907.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__output_carry$next[0:0]$9157 - attribute \src "libresoc.v:165282.3-165283.55" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_carry$next[0:0]$9205 + attribute \src "libresoc.v:166914.3-166915.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__output_cr$next[0:0]$9158 - attribute \src "libresoc.v:165286.3-165287.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_cr$next[0:0]$9206 + attribute \src "libresoc.v:166918.3-166919.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__rc__ok$next[0:0]$9159 - attribute \src "libresoc.v:165270.3-165271.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__ok$next[0:0]$9207 + attribute \src "libresoc.v:166902.3-166903.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__rc__rc$next[0:0]$9160 - attribute \src "libresoc.v:165268.3-165269.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__rc$next[0:0]$9208 + attribute \src "libresoc.v:166900.3-166901.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__write_cr0$next[0:0]$9161 - attribute \src "libresoc.v:165276.3-165277.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__write_cr0$next[0:0]$9209 + attribute \src "libresoc.v:166908.3-166909.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire width 2 $0\xer_ca$next[1:0]$9133 - attribute \src "libresoc.v:165244.3-165245.29" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $0\xer_ca$next[1:0]$9181 + attribute \src "libresoc.v:166876.3-166877.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire $0\xer_ca_ok$next[0:0]$9132 - attribute \src "libresoc.v:165246.3-165247.35" + attribute \src "libresoc.v:167032.3-167050.6" + wire $0\xer_ca_ok$next[0:0]$9180 + attribute \src "libresoc.v:166878.3-166879.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $0\xer_so$next[0:0]$9198 - attribute \src "libresoc.v:165248.3-165249.29" + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so$next[0:0]$9246 + attribute \src "libresoc.v:166880.3-166881.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $0\xer_so_ok$next[0:0]$9199 - attribute \src "libresoc.v:165250.3-165251.35" + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so_ok$next[0:0]$9247 + attribute \src "libresoc.v:166882.3-166883.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire width 4 $1\cr_a$next[3:0]$9194 - attribute \src "libresoc.v:164151.13-164151.24" + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $1\cr_a$next[3:0]$9242 + attribute \src "libresoc.v:165783.13-165783.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $1\cr_a_ok$next[0:0]$9195 - attribute \src "libresoc.v:164160.7-164160.21" + attribute \src "libresoc.v:167142.3-167160.6" + wire $1\cr_a_ok$next[0:0]$9243 + attribute \src "libresoc.v:165792.7-165792.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:165437.3-165449.6" - wire width 2 $1\muxid$next[1:0]$9143 - attribute \src "libresoc.v:164725.13-164725.25" + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:166357.13-166357.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire width 64 $1\o$next[63:0]$9188 - attribute \src "libresoc.v:164740.14-164740.38" + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $1\o$next[63:0]$9236 + attribute \src "libresoc.v:166372.14-166372.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire $1\o_ok$next[0:0]$9189 - attribute \src "libresoc.v:164747.7-164747.18" + attribute \src "libresoc.v:167123.3-167141.6" + wire $1\o_ok$next[0:0]$9237 + attribute \src "libresoc.v:166379.7-166379.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165419.3-165436.6" - wire $1\r_busy$next[0:0]$9139 - attribute \src "libresoc.v:164761.7-164761.20" + attribute \src "libresoc.v:167051.3-167068.6" + wire $1\r_busy$next[0:0]$9187 + attribute \src "libresoc.v:166393.7-166393.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 14 $1\sr_op__fn_unit$next[13:0]$9162 - attribute \src "libresoc.v:164787.14-164787.39" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 + attribute \src "libresoc.v:166419.14-166419.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9163 - attribute \src "libresoc.v:164826.14-164826.58" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 + attribute \src "libresoc.v:166458.14-166458.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9164 - attribute \src "libresoc.v:164835.7-164835.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9212 + attribute \src "libresoc.v:166467.7-166467.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9165 - attribute \src "libresoc.v:164848.13-164848.38" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9213 + attribute \src "libresoc.v:166480.13-166480.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__input_cr$next[0:0]$9166 - attribute \src "libresoc.v:164865.7-164865.29" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__input_cr$next[0:0]$9214 + attribute \src "libresoc.v:166497.7-166497.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 32 $1\sr_op__insn$next[31:0]$9167 - attribute \src "libresoc.v:164874.14-164874.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $1\sr_op__insn$next[31:0]$9215 + attribute \src "libresoc.v:166506.14-166506.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9168 - attribute \src "libresoc.v:164958.13-164958.37" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9216 + attribute \src "libresoc.v:166590.13-166590.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__invert_in$next[0:0]$9169 - attribute \src "libresoc.v:165117.7-165117.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__invert_in$next[0:0]$9217 + attribute \src "libresoc.v:166749.7-166749.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__is_32bit$next[0:0]$9170 - attribute \src "libresoc.v:165126.7-165126.29" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_32bit$next[0:0]$9218 + attribute \src "libresoc.v:166758.7-166758.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__is_signed$next[0:0]$9171 - attribute \src "libresoc.v:165135.7-165135.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_signed$next[0:0]$9219 + attribute \src "libresoc.v:166767.7-166767.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__oe__oe$next[0:0]$9172 - attribute \src "libresoc.v:165144.7-165144.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__oe$next[0:0]$9220 + attribute \src "libresoc.v:166776.7-166776.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__oe__ok$next[0:0]$9173 - attribute \src "libresoc.v:165153.7-165153.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__ok$next[0:0]$9221 + attribute \src "libresoc.v:166785.7-166785.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__output_carry$next[0:0]$9174 - attribute \src "libresoc.v:165162.7-165162.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_carry$next[0:0]$9222 + attribute \src "libresoc.v:166794.7-166794.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__output_cr$next[0:0]$9175 - attribute \src "libresoc.v:165171.7-165171.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_cr$next[0:0]$9223 + attribute \src "libresoc.v:166803.7-166803.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__rc__ok$next[0:0]$9176 - attribute \src "libresoc.v:165180.7-165180.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__ok$next[0:0]$9224 + attribute \src "libresoc.v:166812.7-166812.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__rc__rc$next[0:0]$9177 - attribute \src "libresoc.v:165189.7-165189.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__rc$next[0:0]$9225 + attribute \src "libresoc.v:166821.7-166821.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__write_cr0$next[0:0]$9178 - attribute \src "libresoc.v:165198.7-165198.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__write_cr0$next[0:0]$9226 + attribute \src "libresoc.v:166830.7-166830.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire width 2 $1\xer_ca$next[1:0]$9135 - attribute \src "libresoc.v:165207.13-165207.26" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $1\xer_ca$next[1:0]$9183 + attribute \src "libresoc.v:166839.13-166839.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire $1\xer_ca_ok$next[0:0]$9134 - attribute \src "libresoc.v:165218.7-165218.23" + attribute \src "libresoc.v:167032.3-167050.6" + wire $1\xer_ca_ok$next[0:0]$9182 + attribute \src "libresoc.v:166850.7-166850.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $1\xer_so$next[0:0]$9200 - attribute \src "libresoc.v:165227.7-165227.20" + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so$next[0:0]$9248 + attribute \src "libresoc.v:166859.7-166859.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $1\xer_so_ok$next[0:0]$9201 - attribute \src "libresoc.v:165236.7-165236.23" + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so_ok$next[0:0]$9249 + attribute \src "libresoc.v:166868.7-166868.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $2\cr_a_ok$next[0:0]$9196 - attribute \src "libresoc.v:165491.3-165509.6" - wire $2\o_ok$next[0:0]$9190 - attribute \src "libresoc.v:165419.3-165436.6" - wire $2\r_busy$next[0:0]$9140 - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9179 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9180 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__oe__oe$next[0:0]$9181 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__oe__ok$next[0:0]$9182 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__rc__ok$next[0:0]$9183 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__rc__rc$next[0:0]$9184 - attribute \src "libresoc.v:165400.3-165418.6" - wire $2\xer_ca_ok$next[0:0]$9136 - attribute \src "libresoc.v:165529.3-165547.6" - wire $2\xer_so_ok$next[0:0]$9202 - attribute \src "libresoc.v:165243.18-165243.118" - wire $and$libresoc.v:165243$9103_Y + attribute \src "libresoc.v:167142.3-167160.6" + wire $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167123.3-167141.6" + wire $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167051.3-167068.6" + wire $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9228 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__oe$next[0:0]$9229 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__ok$next[0:0]$9230 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__ok$next[0:0]$9231 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167032.3-167050.6" + wire $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167161.3-167179.6" + wire $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:166875.18-166875.118" + wire $and$libresoc.v:166875$9151_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 24 \cr_a @@ -340302,7 +342799,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:164142.7-164142.15" + attribute \src "libresoc.v:165774.7-165774.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -341357,7 +343854,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165243$9103 + cell $and $and$libresoc.v:166875$9151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -341365,10 +343862,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:165243$9103_Y + connect \Y $and$libresoc.v:166875$9151_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165298.15-165345.4" + attribute \src "libresoc.v:166930.15-166977.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -341418,7 +343915,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165346.14-165391.4" + attribute \src "libresoc.v:166978.14-167023.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -341466,442 +343963,442 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165392.11-165395.4" + attribute \src "libresoc.v:167024.11-167027.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165396.11-165399.4" + attribute \src "libresoc.v:167028.11-167031.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164142.7-164142.20" - process $proc$libresoc.v:164142$9203 + attribute \src "libresoc.v:165774.7-165774.20" + process $proc$libresoc.v:165774$9251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164151.13-164151.24" - process $proc$libresoc.v:164151$9204 + attribute \src "libresoc.v:165783.13-165783.24" + process $proc$libresoc.v:165783$9252 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:164160.7-164160.21" - process $proc$libresoc.v:164160$9205 + attribute \src "libresoc.v:165792.7-165792.21" + process $proc$libresoc.v:165792$9253 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:164725.13-164725.25" - process $proc$libresoc.v:164725$9206 + attribute \src "libresoc.v:166357.13-166357.25" + process $proc$libresoc.v:166357$9254 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:164740.14-164740.38" - process $proc$libresoc.v:164740$9207 + attribute \src "libresoc.v:166372.14-166372.38" + process $proc$libresoc.v:166372$9255 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:164747.7-164747.18" - process $proc$libresoc.v:164747$9208 + attribute \src "libresoc.v:166379.7-166379.18" + process $proc$libresoc.v:166379$9256 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:164761.7-164761.20" - process $proc$libresoc.v:164761$9209 + attribute \src "libresoc.v:166393.7-166393.20" + process $proc$libresoc.v:166393$9257 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:164787.14-164787.39" - process $proc$libresoc.v:164787$9210 + attribute \src "libresoc.v:166419.14-166419.39" + process $proc$libresoc.v:166419$9258 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:164826.14-164826.58" - process $proc$libresoc.v:164826$9211 + attribute \src "libresoc.v:166458.14-166458.58" + process $proc$libresoc.v:166458$9259 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:164835.7-164835.33" - process $proc$libresoc.v:164835$9212 + attribute \src "libresoc.v:166467.7-166467.33" + process $proc$libresoc.v:166467$9260 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:164848.13-164848.38" - process $proc$libresoc.v:164848$9213 + attribute \src "libresoc.v:166480.13-166480.38" + process $proc$libresoc.v:166480$9261 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:164865.7-164865.29" - process $proc$libresoc.v:164865$9214 + attribute \src "libresoc.v:166497.7-166497.29" + process $proc$libresoc.v:166497$9262 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:164874.14-164874.33" - process $proc$libresoc.v:164874$9215 + attribute \src "libresoc.v:166506.14-166506.33" + process $proc$libresoc.v:166506$9263 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:164958.13-164958.37" - process $proc$libresoc.v:164958$9216 + attribute \src "libresoc.v:166590.13-166590.37" + process $proc$libresoc.v:166590$9264 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:165117.7-165117.30" - process $proc$libresoc.v:165117$9217 + attribute \src "libresoc.v:166749.7-166749.30" + process $proc$libresoc.v:166749$9265 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:165126.7-165126.29" - process $proc$libresoc.v:165126$9218 + attribute \src "libresoc.v:166758.7-166758.29" + process $proc$libresoc.v:166758$9266 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:165135.7-165135.30" - process $proc$libresoc.v:165135$9219 + attribute \src "libresoc.v:166767.7-166767.30" + process $proc$libresoc.v:166767$9267 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:165144.7-165144.27" - process $proc$libresoc.v:165144$9220 + attribute \src "libresoc.v:166776.7-166776.27" + process $proc$libresoc.v:166776$9268 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:165153.7-165153.27" - process $proc$libresoc.v:165153$9221 + attribute \src "libresoc.v:166785.7-166785.27" + process $proc$libresoc.v:166785$9269 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:165162.7-165162.33" - process $proc$libresoc.v:165162$9222 + attribute \src "libresoc.v:166794.7-166794.33" + process $proc$libresoc.v:166794$9270 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:165171.7-165171.30" - process $proc$libresoc.v:165171$9223 + attribute \src "libresoc.v:166803.7-166803.30" + process $proc$libresoc.v:166803$9271 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:165180.7-165180.27" - process $proc$libresoc.v:165180$9224 + attribute \src "libresoc.v:166812.7-166812.27" + process $proc$libresoc.v:166812$9272 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:165189.7-165189.27" - process $proc$libresoc.v:165189$9225 + attribute \src "libresoc.v:166821.7-166821.27" + process $proc$libresoc.v:166821$9273 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:165198.7-165198.30" - process $proc$libresoc.v:165198$9226 + attribute \src "libresoc.v:166830.7-166830.30" + process $proc$libresoc.v:166830$9274 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:165207.13-165207.26" - process $proc$libresoc.v:165207$9227 + attribute \src "libresoc.v:166839.13-166839.26" + process $proc$libresoc.v:166839$9275 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:165218.7-165218.23" - process $proc$libresoc.v:165218$9228 + attribute \src "libresoc.v:166850.7-166850.23" + process $proc$libresoc.v:166850$9276 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165227.7-165227.20" - process $proc$libresoc.v:165227$9229 + attribute \src "libresoc.v:166859.7-166859.20" + process $proc$libresoc.v:166859$9277 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:165236.7-165236.23" - process $proc$libresoc.v:165236$9230 + attribute \src "libresoc.v:166868.7-166868.23" + process $proc$libresoc.v:166868$9278 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:165244.3-165245.29" - process $proc$libresoc.v:165244$9104 + attribute \src "libresoc.v:166876.3-166877.29" + process $proc$libresoc.v:166876$9152 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:165246.3-165247.35" - process $proc$libresoc.v:165246$9105 + attribute \src "libresoc.v:166878.3-166879.35" + process $proc$libresoc.v:166878$9153 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165248.3-165249.29" - process $proc$libresoc.v:165248$9106 + attribute \src "libresoc.v:166880.3-166881.29" + process $proc$libresoc.v:166880$9154 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:165250.3-165251.35" - process $proc$libresoc.v:165250$9107 + attribute \src "libresoc.v:166882.3-166883.35" + process $proc$libresoc.v:166882$9155 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165252.3-165253.25" - process $proc$libresoc.v:165252$9108 + attribute \src "libresoc.v:166884.3-166885.25" + process $proc$libresoc.v:166884$9156 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:165254.3-165255.31" - process $proc$libresoc.v:165254$9109 + attribute \src "libresoc.v:166886.3-166887.31" + process $proc$libresoc.v:166886$9157 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:165256.3-165257.19" - process $proc$libresoc.v:165256$9110 + attribute \src "libresoc.v:166888.3-166889.19" + process $proc$libresoc.v:166888$9158 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165258.3-165259.25" - process $proc$libresoc.v:165258$9111 + attribute \src "libresoc.v:166890.3-166891.25" + process $proc$libresoc.v:166890$9159 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165260.3-165261.49" - process $proc$libresoc.v:165260$9112 + attribute \src "libresoc.v:166892.3-166893.49" + process $proc$libresoc.v:166892$9160 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:165262.3-165263.45" - process $proc$libresoc.v:165262$9113 + attribute \src "libresoc.v:166894.3-166895.45" + process $proc$libresoc.v:166894$9161 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:165264.3-165265.59" - process $proc$libresoc.v:165264$9114 + attribute \src "libresoc.v:166896.3-166897.59" + process $proc$libresoc.v:166896$9162 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165266.3-165267.55" - process $proc$libresoc.v:165266$9115 + attribute \src "libresoc.v:166898.3-166899.55" + process $proc$libresoc.v:166898$9163 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165268.3-165269.43" - process $proc$libresoc.v:165268$9116 + attribute \src "libresoc.v:166900.3-166901.43" + process $proc$libresoc.v:166900$9164 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:165270.3-165271.43" - process $proc$libresoc.v:165270$9117 + attribute \src "libresoc.v:166902.3-166903.43" + process $proc$libresoc.v:166902$9165 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:165272.3-165273.43" - process $proc$libresoc.v:165272$9118 + attribute \src "libresoc.v:166904.3-166905.43" + process $proc$libresoc.v:166904$9166 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:165274.3-165275.43" - process $proc$libresoc.v:165274$9119 + attribute \src "libresoc.v:166906.3-166907.43" + process $proc$libresoc.v:166906$9167 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:165276.3-165277.49" - process $proc$libresoc.v:165276$9120 + attribute \src "libresoc.v:166908.3-166909.49" + process $proc$libresoc.v:166908$9168 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:165278.3-165279.49" - process $proc$libresoc.v:165278$9121 + attribute \src "libresoc.v:166910.3-166911.49" + process $proc$libresoc.v:166910$9169 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:165280.3-165281.53" - process $proc$libresoc.v:165280$9122 + attribute \src "libresoc.v:166912.3-166913.53" + process $proc$libresoc.v:166912$9170 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:165282.3-165283.55" - process $proc$libresoc.v:165282$9123 + attribute \src "libresoc.v:166914.3-166915.55" + process $proc$libresoc.v:166914$9171 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:165284.3-165285.47" - process $proc$libresoc.v:165284$9124 + attribute \src "libresoc.v:166916.3-166917.47" + process $proc$libresoc.v:166916$9172 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:165286.3-165287.49" - process $proc$libresoc.v:165286$9125 + attribute \src "libresoc.v:166918.3-166919.49" + process $proc$libresoc.v:166918$9173 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:165288.3-165289.47" - process $proc$libresoc.v:165288$9126 + attribute \src "libresoc.v:166920.3-166921.47" + process $proc$libresoc.v:166920$9174 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:165290.3-165291.49" - process $proc$libresoc.v:165290$9127 + attribute \src "libresoc.v:166922.3-166923.49" + process $proc$libresoc.v:166922$9175 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:165292.3-165293.39" - process $proc$libresoc.v:165292$9128 + attribute \src "libresoc.v:166924.3-166925.39" + process $proc$libresoc.v:166924$9176 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:165294.3-165295.27" - process $proc$libresoc.v:165294$9129 + attribute \src "libresoc.v:166926.3-166927.27" + process $proc$libresoc.v:166926$9177 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:165296.3-165297.29" - process $proc$libresoc.v:165296$9130 + attribute \src "libresoc.v:166928.3-166929.29" + process $proc$libresoc.v:166928$9178 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165400.3-165418.6" - process $proc$libresoc.v:165400$9131 + attribute \src "libresoc.v:167032.3-167050.6" + process $proc$libresoc.v:167032$9179 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9133 $1\xer_ca$next[1:0]$9135 - assign $0\xer_ca_ok$next[0:0]$9132 $2\xer_ca_ok$next[0:0]$9136 - attribute \src "libresoc.v:165401.5-165401.29" + assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 + assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167033.5-167033.29" switch \initial - attribute \src "libresoc.v:165401.9-165401.17" + attribute \src "libresoc.v:167033.9-167033.17" case 1'1 case end @@ -341911,38 +344408,38 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\xer_ca_ok$next[0:0]$9134 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9135 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9182 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9183 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9136 1'0 + assign $2\xer_ca_ok$next[0:0]$9184 1'0 case - assign $2\xer_ca_ok$next[0:0]$9136 $1\xer_ca_ok$next[0:0]$9134 + assign $2\xer_ca_ok$next[0:0]$9184 $1\xer_ca_ok$next[0:0]$9182 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9132 - update \xer_ca$next $0\xer_ca$next[1:0]$9133 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 + update \xer_ca$next $0\xer_ca$next[1:0]$9181 end - attribute \src "libresoc.v:165419.3-165436.6" - process $proc$libresoc.v:165419$9137 + attribute \src "libresoc.v:167051.3-167068.6" + process $proc$libresoc.v:167051$9185 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9138 $2\r_busy$next[0:0]$9140 - attribute \src "libresoc.v:165420.5-165420.29" + assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167052.5-167052.29" switch \initial - attribute \src "libresoc.v:165420.9-165420.17" + attribute \src "libresoc.v:167052.9-167052.17" case 1'1 case end @@ -341951,34 +344448,34 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9139 1'1 + assign $1\r_busy$next[0:0]$9187 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9139 1'0 + assign $1\r_busy$next[0:0]$9187 1'0 case - assign $1\r_busy$next[0:0]$9139 \r_busy + assign $1\r_busy$next[0:0]$9187 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9140 1'0 + assign $2\r_busy$next[0:0]$9188 1'0 case - assign $2\r_busy$next[0:0]$9140 $1\r_busy$next[0:0]$9139 + assign $2\r_busy$next[0:0]$9188 $1\r_busy$next[0:0]$9187 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9138 + update \r_busy$next $0\r_busy$next[0:0]$9186 end - attribute \src "libresoc.v:165437.3-165449.6" - process $proc$libresoc.v:165437$9141 + attribute \src "libresoc.v:167069.3-167081.6" + process $proc$libresoc.v:167069$9189 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9142 $1\muxid$next[1:0]$9143 - attribute \src "libresoc.v:165438.5-165438.29" + assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:167070.5-167070.29" switch \initial - attribute \src "libresoc.v:165438.9-165438.17" + attribute \src "libresoc.v:167070.9-167070.17" case 1'1 case end @@ -341987,19 +344484,19 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9143 \muxid$67 + assign $1\muxid$next[1:0]$9191 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9143 \muxid$67 + assign $1\muxid$next[1:0]$9191 \muxid$67 case - assign $1\muxid$next[1:0]$9143 \muxid + assign $1\muxid$next[1:0]$9191 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9142 + update \muxid$next $0\muxid$next[1:0]$9190 end - attribute \src "libresoc.v:165450.3-165490.6" - process $proc$libresoc.v:165450$9144 + attribute \src "libresoc.v:167082.3-167122.6" + process $proc$libresoc.v:167082$9192 assign { } { } assign { } { } assign { } { } @@ -342034,32 +344531,32 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[13:0]$9145 $1\sr_op__fn_unit$next[13:0]$9162 + assign $0\sr_op__fn_unit$next[13:0]$9193 $1\sr_op__fn_unit$next[13:0]$9210 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9148 $1\sr_op__input_carry$next[1:0]$9165 - assign $0\sr_op__input_cr$next[0:0]$9149 $1\sr_op__input_cr$next[0:0]$9166 - assign $0\sr_op__insn$next[31:0]$9150 $1\sr_op__insn$next[31:0]$9167 - assign $0\sr_op__insn_type$next[6:0]$9151 $1\sr_op__insn_type$next[6:0]$9168 - assign $0\sr_op__invert_in$next[0:0]$9152 $1\sr_op__invert_in$next[0:0]$9169 - assign $0\sr_op__is_32bit$next[0:0]$9153 $1\sr_op__is_32bit$next[0:0]$9170 - assign $0\sr_op__is_signed$next[0:0]$9154 $1\sr_op__is_signed$next[0:0]$9171 + assign $0\sr_op__input_carry$next[1:0]$9196 $1\sr_op__input_carry$next[1:0]$9213 + assign $0\sr_op__input_cr$next[0:0]$9197 $1\sr_op__input_cr$next[0:0]$9214 + assign $0\sr_op__insn$next[31:0]$9198 $1\sr_op__insn$next[31:0]$9215 + assign $0\sr_op__insn_type$next[6:0]$9199 $1\sr_op__insn_type$next[6:0]$9216 + assign $0\sr_op__invert_in$next[0:0]$9200 $1\sr_op__invert_in$next[0:0]$9217 + assign $0\sr_op__is_32bit$next[0:0]$9201 $1\sr_op__is_32bit$next[0:0]$9218 + assign $0\sr_op__is_signed$next[0:0]$9202 $1\sr_op__is_signed$next[0:0]$9219 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9157 $1\sr_op__output_carry$next[0:0]$9174 - assign $0\sr_op__output_cr$next[0:0]$9158 $1\sr_op__output_cr$next[0:0]$9175 + assign $0\sr_op__output_carry$next[0:0]$9205 $1\sr_op__output_carry$next[0:0]$9222 + assign $0\sr_op__output_cr$next[0:0]$9206 $1\sr_op__output_cr$next[0:0]$9223 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9161 $1\sr_op__write_cr0$next[0:0]$9178 - assign $0\sr_op__imm_data__data$next[63:0]$9146 $2\sr_op__imm_data__data$next[63:0]$9179 - assign $0\sr_op__imm_data__ok$next[0:0]$9147 $2\sr_op__imm_data__ok$next[0:0]$9180 - assign $0\sr_op__oe__oe$next[0:0]$9155 $2\sr_op__oe__oe$next[0:0]$9181 - assign $0\sr_op__oe__ok$next[0:0]$9156 $2\sr_op__oe__ok$next[0:0]$9182 - assign $0\sr_op__rc__ok$next[0:0]$9159 $2\sr_op__rc__ok$next[0:0]$9183 - assign $0\sr_op__rc__rc$next[0:0]$9160 $2\sr_op__rc__rc$next[0:0]$9184 - attribute \src "libresoc.v:165451.5-165451.29" + assign $0\sr_op__write_cr0$next[0:0]$9209 $1\sr_op__write_cr0$next[0:0]$9226 + assign $0\sr_op__imm_data__data$next[63:0]$9194 $2\sr_op__imm_data__data$next[63:0]$9227 + assign $0\sr_op__imm_data__ok$next[0:0]$9195 $2\sr_op__imm_data__ok$next[0:0]$9228 + assign $0\sr_op__oe__oe$next[0:0]$9203 $2\sr_op__oe__oe$next[0:0]$9229 + assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 + assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 + assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167083.5-167083.29" switch \initial - attribute \src "libresoc.v:165451.9-165451.17" + attribute \src "libresoc.v:167083.9-167083.17" case 1'1 case end @@ -342084,7 +344581,7 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -342104,25 +344601,25 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\sr_op__fn_unit$next[13:0]$9162 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9163 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9164 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9165 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9166 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9167 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9168 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9169 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9170 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9171 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9172 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9173 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9174 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9175 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9176 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9177 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9178 \sr_op__write_cr0 + assign $1\sr_op__fn_unit$next[13:0]$9210 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9211 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9212 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9213 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9214 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9215 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9216 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9217 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9218 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9219 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9220 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9221 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9222 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9223 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9224 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9225 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9226 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -342134,51 +344631,51 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9179 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9180 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9184 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9183 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9181 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9182 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9227 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9232 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9231 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9229 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9230 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9179 $1\sr_op__imm_data__data$next[63:0]$9163 - assign $2\sr_op__imm_data__ok$next[0:0]$9180 $1\sr_op__imm_data__ok$next[0:0]$9164 - assign $2\sr_op__oe__oe$next[0:0]$9181 $1\sr_op__oe__oe$next[0:0]$9172 - assign $2\sr_op__oe__ok$next[0:0]$9182 $1\sr_op__oe__ok$next[0:0]$9173 - assign $2\sr_op__rc__ok$next[0:0]$9183 $1\sr_op__rc__ok$next[0:0]$9176 - assign $2\sr_op__rc__rc$next[0:0]$9184 $1\sr_op__rc__rc$next[0:0]$9177 + assign $2\sr_op__imm_data__data$next[63:0]$9227 $1\sr_op__imm_data__data$next[63:0]$9211 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 $1\sr_op__imm_data__ok$next[0:0]$9212 + assign $2\sr_op__oe__oe$next[0:0]$9229 $1\sr_op__oe__oe$next[0:0]$9220 + assign $2\sr_op__oe__ok$next[0:0]$9230 $1\sr_op__oe__ok$next[0:0]$9221 + assign $2\sr_op__rc__ok$next[0:0]$9231 $1\sr_op__rc__ok$next[0:0]$9224 + assign $2\sr_op__rc__rc$next[0:0]$9232 $1\sr_op__rc__rc$next[0:0]$9225 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9145 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9146 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9147 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9148 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9149 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9150 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9151 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9152 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9153 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9154 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9155 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9156 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9157 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9158 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9159 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9160 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9161 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9193 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9194 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9195 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9196 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9197 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9198 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9199 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9200 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9201 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9202 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9203 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9204 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9205 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9206 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9207 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 end - attribute \src "libresoc.v:165491.3-165509.6" - process $proc$libresoc.v:165491$9185 + attribute \src "libresoc.v:167123.3-167141.6" + process $proc$libresoc.v:167123$9233 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9186 $1\o$next[63:0]$9188 + assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 assign { } { } - assign $0\o_ok$next[0:0]$9187 $2\o_ok$next[0:0]$9190 - attribute \src "libresoc.v:165492.5-165492.29" + assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167124.5-167124.29" switch \initial - attribute \src "libresoc.v:165492.9-165492.17" + attribute \src "libresoc.v:167124.9-167124.17" case 1'1 case end @@ -342188,41 +344685,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$9188 \o - assign $1\o_ok$next[0:0]$9189 \o_ok + assign $1\o$next[63:0]$9236 \o + assign $1\o_ok$next[0:0]$9237 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9190 1'0 + assign $2\o_ok$next[0:0]$9238 1'0 case - assign $2\o_ok$next[0:0]$9190 $1\o_ok$next[0:0]$9189 + assign $2\o_ok$next[0:0]$9238 $1\o_ok$next[0:0]$9237 end sync always - update \o$next $0\o$next[63:0]$9186 - update \o_ok$next $0\o_ok$next[0:0]$9187 + update \o$next $0\o$next[63:0]$9234 + update \o_ok$next $0\o_ok$next[0:0]$9235 end - attribute \src "libresoc.v:165510.3-165528.6" - process $proc$libresoc.v:165510$9191 + attribute \src "libresoc.v:167142.3-167160.6" + process $proc$libresoc.v:167142$9239 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9192 $1\cr_a$next[3:0]$9194 + assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 assign { } { } - assign $0\cr_a_ok$next[0:0]$9193 $2\cr_a_ok$next[0:0]$9196 - attribute \src "libresoc.v:165511.5-165511.29" + assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167143.5-167143.29" switch \initial - attribute \src "libresoc.v:165511.9-165511.17" + attribute \src "libresoc.v:167143.9-167143.17" case 1'1 case end @@ -342232,41 +344729,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$9194 \cr_a - assign $1\cr_a_ok$next[0:0]$9195 \cr_a_ok + assign $1\cr_a$next[3:0]$9242 \cr_a + assign $1\cr_a_ok$next[0:0]$9243 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9196 1'0 + assign $2\cr_a_ok$next[0:0]$9244 1'0 case - assign $2\cr_a_ok$next[0:0]$9196 $1\cr_a_ok$next[0:0]$9195 + assign $2\cr_a_ok$next[0:0]$9244 $1\cr_a_ok$next[0:0]$9243 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9192 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9193 + update \cr_a$next $0\cr_a$next[3:0]$9240 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 end - attribute \src "libresoc.v:165529.3-165547.6" - process $proc$libresoc.v:165529$9197 + attribute \src "libresoc.v:167161.3-167179.6" + process $proc$libresoc.v:167161$9245 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9198 $1\xer_so$next[0:0]$9200 + assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 assign { } { } - assign $0\xer_so_ok$next[0:0]$9199 $2\xer_so_ok$next[0:0]$9202 - attribute \src "libresoc.v:165530.5-165530.29" + assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:167162.5-167162.29" switch \initial - attribute \src "libresoc.v:165530.9-165530.17" + attribute \src "libresoc.v:167162.9-167162.17" case 1'1 case end @@ -342276,30 +344773,30 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$9200 \xer_so - assign $1\xer_so_ok$next[0:0]$9201 \xer_so_ok + assign $1\xer_so$next[0:0]$9248 \xer_so + assign $1\xer_so_ok$next[0:0]$9249 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9202 1'0 + assign $2\xer_so_ok$next[0:0]$9250 1'0 case - assign $2\xer_so_ok$next[0:0]$9202 $1\xer_so_ok$next[0:0]$9201 + assign $2\xer_so_ok$next[0:0]$9250 $1\xer_so_ok$next[0:0]$9249 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9198 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9199 + update \xer_so$next $0\xer_so$next[0:0]$9246 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 end - connect \$65 $and$libresoc.v:165243$9103_Y + connect \$65 $and$libresoc.v:166875$9151_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -342330,142 +344827,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165581.1-166429.10" +attribute \src "libresoc.v:167213.1-168061.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:166386.3-166398.6" - wire width 64 $0\fast1$next[63:0]$9280 - attribute \src "libresoc.v:166242.3-166243.27" + attribute \src "libresoc.v:168018.3-168030.6" + wire width 64 $0\fast1$next[63:0]$9328 + attribute \src "libresoc.v:167874.3-167875.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:166399.3-166411.6" - wire width 64 $0\fast2$next[63:0]$9283 - attribute \src "libresoc.v:166240.3-166241.27" + attribute \src "libresoc.v:168031.3-168043.6" + wire width 64 $0\fast2$next[63:0]$9331 + attribute \src "libresoc.v:167872.3-167873.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:165582.7-165582.20" + attribute \src "libresoc.v:167214.7-167214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166326.3-166338.6" - wire width 2 $0\muxid$next[1:0]$9252 - attribute \src "libresoc.v:166266.3-166267.27" + attribute \src "libresoc.v:167958.3-167970.6" + wire width 2 $0\muxid$next[1:0]$9300 + attribute \src "libresoc.v:167898.3-167899.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $0\r_busy$next[0:0]$9248 - attribute \src "libresoc.v:166268.3-166269.29" + attribute \src "libresoc.v:167940.3-167957.6" + wire $0\r_busy$next[0:0]$9296 + attribute \src "libresoc.v:167900.3-167901.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:166360.3-166372.6" - wire width 64 $0\ra$next[63:0]$9274 - attribute \src "libresoc.v:166246.3-166247.21" + attribute \src "libresoc.v:167992.3-168004.6" + wire width 64 $0\ra$next[63:0]$9322 + attribute \src "libresoc.v:167878.3-167879.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:166373.3-166385.6" - wire width 64 $0\rb$next[63:0]$9277 - attribute \src "libresoc.v:166244.3-166245.21" + attribute \src "libresoc.v:168005.3-168017.6" + wire width 64 $0\rb$next[63:0]$9325 + attribute \src "libresoc.v:167876.3-167877.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $0\trap_op__cia$next[63:0]$9255 - attribute \src "libresoc.v:166256.3-166257.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $0\trap_op__cia$next[63:0]$9303 + attribute \src "libresoc.v:167888.3-167889.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 14 $0\trap_op__fn_unit$next[13:0]$9256 - attribute \src "libresoc.v:166250.3-166251.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 + attribute \src "libresoc.v:167882.3-167883.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 32 $0\trap_op__insn$next[31:0]$9257 - attribute \src "libresoc.v:166252.3-166253.43" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 32 $0\trap_op__insn$next[31:0]$9305 + attribute \src "libresoc.v:167884.3-167885.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9258 - attribute \src "libresoc.v:166248.3-166249.53" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9306 + attribute \src "libresoc.v:167880.3-167881.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire $0\trap_op__is_32bit$next[0:0]$9259 - attribute \src "libresoc.v:166258.3-166259.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire $0\trap_op__is_32bit$next[0:0]$9307 + attribute \src "libresoc.v:167890.3-167891.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9260 - attribute \src "libresoc.v:166264.3-166265.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 + attribute \src "libresoc.v:167896.3-167897.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $0\trap_op__msr$next[63:0]$9261 - attribute \src "libresoc.v:166254.3-166255.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $0\trap_op__msr$next[63:0]$9309 + attribute \src "libresoc.v:167886.3-167887.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9262 - attribute \src "libresoc.v:166262.3-166263.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9310 + attribute \src "libresoc.v:167894.3-167895.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9263 - attribute \src "libresoc.v:166260.3-166261.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9311 + attribute \src "libresoc.v:167892.3-167893.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:166386.3-166398.6" - wire width 64 $1\fast1$next[63:0]$9281 - attribute \src "libresoc.v:165827.14-165827.42" + attribute \src "libresoc.v:168018.3-168030.6" + wire width 64 $1\fast1$next[63:0]$9329 + attribute \src "libresoc.v:167459.14-167459.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:166399.3-166411.6" - wire width 64 $1\fast2$next[63:0]$9284 - attribute \src "libresoc.v:165836.14-165836.42" + attribute \src "libresoc.v:168031.3-168043.6" + wire width 64 $1\fast2$next[63:0]$9332 + attribute \src "libresoc.v:167468.14-167468.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:166326.3-166338.6" - wire width 2 $1\muxid$next[1:0]$9253 - attribute \src "libresoc.v:165845.13-165845.25" + attribute \src "libresoc.v:167958.3-167970.6" + wire width 2 $1\muxid$next[1:0]$9301 + attribute \src "libresoc.v:167477.13-167477.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $1\r_busy$next[0:0]$9249 - attribute \src "libresoc.v:165867.7-165867.20" + attribute \src "libresoc.v:167940.3-167957.6" + wire $1\r_busy$next[0:0]$9297 + attribute \src "libresoc.v:167499.7-167499.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:166360.3-166372.6" - wire width 64 $1\ra$next[63:0]$9275 - attribute \src "libresoc.v:165872.14-165872.39" + attribute \src "libresoc.v:167992.3-168004.6" + wire width 64 $1\ra$next[63:0]$9323 + attribute \src "libresoc.v:167504.14-167504.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:166373.3-166385.6" - wire width 64 $1\rb$next[63:0]$9278 - attribute \src "libresoc.v:165881.14-165881.39" + attribute \src "libresoc.v:168005.3-168017.6" + wire width 64 $1\rb$next[63:0]$9326 + attribute \src "libresoc.v:167513.14-167513.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $1\trap_op__cia$next[63:0]$9264 - attribute \src "libresoc.v:165890.14-165890.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $1\trap_op__cia$next[63:0]$9312 + attribute \src "libresoc.v:167522.14-167522.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 14 $1\trap_op__fn_unit$next[13:0]$9265 - attribute \src "libresoc.v:165914.14-165914.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 14 $1\trap_op__fn_unit$next[13:0]$9313 + attribute \src "libresoc.v:167546.14-167546.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 32 $1\trap_op__insn$next[31:0]$9266 - attribute \src "libresoc.v:165953.14-165953.35" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 32 $1\trap_op__insn$next[31:0]$9314 + attribute \src "libresoc.v:167585.14-167585.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9267 - attribute \src "libresoc.v:166037.13-166037.39" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9315 + attribute \src "libresoc.v:167669.13-167669.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire $1\trap_op__is_32bit$next[0:0]$9268 - attribute \src "libresoc.v:166196.7-166196.31" + attribute \src "libresoc.v:167971.3-167991.6" + wire $1\trap_op__is_32bit$next[0:0]$9316 + attribute \src "libresoc.v:167828.7-167828.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9269 - attribute \src "libresoc.v:166205.13-166205.38" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9317 + attribute \src "libresoc.v:167837.13-167837.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $1\trap_op__msr$next[63:0]$9270 - attribute \src "libresoc.v:166214.14-166214.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $1\trap_op__msr$next[63:0]$9318 + attribute \src "libresoc.v:167846.14-167846.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9271 - attribute \src "libresoc.v:166223.14-166223.42" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9319 + attribute \src "libresoc.v:167855.14-167855.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9272 - attribute \src "libresoc.v:166232.13-166232.38" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9320 + attribute \src "libresoc.v:167864.13-167864.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $2\r_busy$next[0:0]$9250 - attribute \src "libresoc.v:166239.18-166239.118" - wire $and$libresoc.v:166239$9231_Y + attribute \src "libresoc.v:167940.3-167957.6" + wire $2\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:167871.18-167871.118" + wire $and$libresoc.v:167871$9279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -342719,7 +345216,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:165582.7-165582.15" + attribute \src "libresoc.v:167214.7-167214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -343106,7 +345603,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166239$9231 + cell $and $and$libresoc.v:167871$9279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -343114,10 +345611,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:166239$9231_Y + connect \Y $and$libresoc.v:167871$9279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166270.9-166299.4" + attribute \src "libresoc.v:167902.9-167931.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -343149,259 +345646,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166300.10-166303.4" + attribute \src "libresoc.v:167932.10-167935.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:166304.10-166307.4" + attribute \src "libresoc.v:167936.10-167939.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165582.7-165582.20" - process $proc$libresoc.v:165582$9285 + attribute \src "libresoc.v:167214.7-167214.20" + process $proc$libresoc.v:167214$9333 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165827.14-165827.42" - process $proc$libresoc.v:165827$9286 + attribute \src "libresoc.v:167459.14-167459.42" + process $proc$libresoc.v:167459$9334 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:165836.14-165836.42" - process $proc$libresoc.v:165836$9287 + attribute \src "libresoc.v:167468.14-167468.42" + process $proc$libresoc.v:167468$9335 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:165845.13-165845.25" - process $proc$libresoc.v:165845$9288 + attribute \src "libresoc.v:167477.13-167477.25" + process $proc$libresoc.v:167477$9336 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:165867.7-165867.20" - process $proc$libresoc.v:165867$9289 + attribute \src "libresoc.v:167499.7-167499.20" + process $proc$libresoc.v:167499$9337 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165872.14-165872.39" - process $proc$libresoc.v:165872$9290 + attribute \src "libresoc.v:167504.14-167504.39" + process $proc$libresoc.v:167504$9338 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:165881.14-165881.39" - process $proc$libresoc.v:165881$9291 + attribute \src "libresoc.v:167513.14-167513.39" + process $proc$libresoc.v:167513$9339 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:165890.14-165890.49" - process $proc$libresoc.v:165890$9292 + attribute \src "libresoc.v:167522.14-167522.49" + process $proc$libresoc.v:167522$9340 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:165914.14-165914.41" - process $proc$libresoc.v:165914$9293 + attribute \src "libresoc.v:167546.14-167546.41" + process $proc$libresoc.v:167546$9341 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:165953.14-165953.35" - process $proc$libresoc.v:165953$9294 + attribute \src "libresoc.v:167585.14-167585.35" + process $proc$libresoc.v:167585$9342 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:166037.13-166037.39" - process $proc$libresoc.v:166037$9295 + attribute \src "libresoc.v:167669.13-167669.39" + process $proc$libresoc.v:167669$9343 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:166196.7-166196.31" - process $proc$libresoc.v:166196$9296 + attribute \src "libresoc.v:167828.7-167828.31" + process $proc$libresoc.v:167828$9344 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:166205.13-166205.38" - process $proc$libresoc.v:166205$9297 + attribute \src "libresoc.v:167837.13-167837.38" + process $proc$libresoc.v:167837$9345 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:166214.14-166214.49" - process $proc$libresoc.v:166214$9298 + attribute \src "libresoc.v:167846.14-167846.49" + process $proc$libresoc.v:167846$9346 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:166223.14-166223.42" - process $proc$libresoc.v:166223$9299 + attribute \src "libresoc.v:167855.14-167855.42" + process $proc$libresoc.v:167855$9347 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:166232.13-166232.38" - process $proc$libresoc.v:166232$9300 + attribute \src "libresoc.v:167864.13-167864.38" + process $proc$libresoc.v:167864$9348 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:166240.3-166241.27" - process $proc$libresoc.v:166240$9232 + attribute \src "libresoc.v:167872.3-167873.27" + process $proc$libresoc.v:167872$9280 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:166242.3-166243.27" - process $proc$libresoc.v:166242$9233 + attribute \src "libresoc.v:167874.3-167875.27" + process $proc$libresoc.v:167874$9281 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:166244.3-166245.21" - process $proc$libresoc.v:166244$9234 + attribute \src "libresoc.v:167876.3-167877.21" + process $proc$libresoc.v:167876$9282 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:166246.3-166247.21" - process $proc$libresoc.v:166246$9235 + attribute \src "libresoc.v:167878.3-167879.21" + process $proc$libresoc.v:167878$9283 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:166248.3-166249.53" - process $proc$libresoc.v:166248$9236 + attribute \src "libresoc.v:167880.3-167881.53" + process $proc$libresoc.v:167880$9284 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:166250.3-166251.49" - process $proc$libresoc.v:166250$9237 + attribute \src "libresoc.v:167882.3-167883.49" + process $proc$libresoc.v:167882$9285 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:166252.3-166253.43" - process $proc$libresoc.v:166252$9238 + attribute \src "libresoc.v:167884.3-167885.43" + process $proc$libresoc.v:167884$9286 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:166254.3-166255.41" - process $proc$libresoc.v:166254$9239 + attribute \src "libresoc.v:167886.3-167887.41" + process $proc$libresoc.v:167886$9287 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:166256.3-166257.41" - process $proc$libresoc.v:166256$9240 + attribute \src "libresoc.v:167888.3-167889.41" + process $proc$libresoc.v:167888$9288 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:166258.3-166259.51" - process $proc$libresoc.v:166258$9241 + attribute \src "libresoc.v:167890.3-167891.51" + process $proc$libresoc.v:167890$9289 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:166260.3-166261.51" - process $proc$libresoc.v:166260$9242 + attribute \src "libresoc.v:167892.3-167893.51" + process $proc$libresoc.v:167892$9290 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:166262.3-166263.51" - process $proc$libresoc.v:166262$9243 + attribute \src "libresoc.v:167894.3-167895.51" + process $proc$libresoc.v:167894$9291 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:166264.3-166265.51" - process $proc$libresoc.v:166264$9244 + attribute \src "libresoc.v:167896.3-167897.51" + process $proc$libresoc.v:167896$9292 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:166266.3-166267.27" - process $proc$libresoc.v:166266$9245 + attribute \src "libresoc.v:167898.3-167899.27" + process $proc$libresoc.v:167898$9293 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166268.3-166269.29" - process $proc$libresoc.v:166268$9246 + attribute \src "libresoc.v:167900.3-167901.29" + process $proc$libresoc.v:167900$9294 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:166308.3-166325.6" - process $proc$libresoc.v:166308$9247 + attribute \src "libresoc.v:167940.3-167957.6" + process $proc$libresoc.v:167940$9295 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9248 $2\r_busy$next[0:0]$9250 - attribute \src "libresoc.v:166309.5-166309.29" + assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:167941.5-167941.29" switch \initial - attribute \src "libresoc.v:166309.9-166309.17" + attribute \src "libresoc.v:167941.9-167941.17" case 1'1 case end @@ -343410,34 +345907,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9249 1'1 + assign $1\r_busy$next[0:0]$9297 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9249 1'0 + assign $1\r_busy$next[0:0]$9297 1'0 case - assign $1\r_busy$next[0:0]$9249 \r_busy + assign $1\r_busy$next[0:0]$9297 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9250 1'0 + assign $2\r_busy$next[0:0]$9298 1'0 case - assign $2\r_busy$next[0:0]$9250 $1\r_busy$next[0:0]$9249 + assign $2\r_busy$next[0:0]$9298 $1\r_busy$next[0:0]$9297 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9248 + update \r_busy$next $0\r_busy$next[0:0]$9296 end - attribute \src "libresoc.v:166326.3-166338.6" - process $proc$libresoc.v:166326$9251 + attribute \src "libresoc.v:167958.3-167970.6" + process $proc$libresoc.v:167958$9299 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9252 $1\muxid$next[1:0]$9253 - attribute \src "libresoc.v:166327.5-166327.29" + assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 + attribute \src "libresoc.v:167959.5-167959.29" switch \initial - attribute \src "libresoc.v:166327.9-166327.17" + attribute \src "libresoc.v:167959.9-167959.17" case 1'1 case end @@ -343446,19 +345943,19 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9253 \muxid$32 + assign $1\muxid$next[1:0]$9301 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9253 \muxid$32 + assign $1\muxid$next[1:0]$9301 \muxid$32 case - assign $1\muxid$next[1:0]$9253 \muxid + assign $1\muxid$next[1:0]$9301 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9252 + update \muxid$next $0\muxid$next[1:0]$9300 end - attribute \src "libresoc.v:166339.3-166359.6" - process $proc$libresoc.v:166339$9254 + attribute \src "libresoc.v:167971.3-167991.6" + process $proc$libresoc.v:167971$9302 assign { } { } assign { } { } assign { } { } @@ -343477,18 +345974,18 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9255 $1\trap_op__cia$next[63:0]$9264 - assign $0\trap_op__fn_unit$next[13:0]$9256 $1\trap_op__fn_unit$next[13:0]$9265 - assign $0\trap_op__insn$next[31:0]$9257 $1\trap_op__insn$next[31:0]$9266 - assign $0\trap_op__insn_type$next[6:0]$9258 $1\trap_op__insn_type$next[6:0]$9267 - assign $0\trap_op__is_32bit$next[0:0]$9259 $1\trap_op__is_32bit$next[0:0]$9268 - assign $0\trap_op__ldst_exc$next[7:0]$9260 $1\trap_op__ldst_exc$next[7:0]$9269 - assign $0\trap_op__msr$next[63:0]$9261 $1\trap_op__msr$next[63:0]$9270 - assign $0\trap_op__trapaddr$next[12:0]$9262 $1\trap_op__trapaddr$next[12:0]$9271 - assign $0\trap_op__traptype$next[7:0]$9263 $1\trap_op__traptype$next[7:0]$9272 - attribute \src "libresoc.v:166340.5-166340.29" + assign $0\trap_op__cia$next[63:0]$9303 $1\trap_op__cia$next[63:0]$9312 + assign $0\trap_op__fn_unit$next[13:0]$9304 $1\trap_op__fn_unit$next[13:0]$9313 + assign $0\trap_op__insn$next[31:0]$9305 $1\trap_op__insn$next[31:0]$9314 + assign $0\trap_op__insn_type$next[6:0]$9306 $1\trap_op__insn_type$next[6:0]$9315 + assign $0\trap_op__is_32bit$next[0:0]$9307 $1\trap_op__is_32bit$next[0:0]$9316 + assign $0\trap_op__ldst_exc$next[7:0]$9308 $1\trap_op__ldst_exc$next[7:0]$9317 + assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 + assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 + assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 + attribute \src "libresoc.v:167972.5-167972.29" switch \initial - attribute \src "libresoc.v:166340.9-166340.17" + attribute \src "libresoc.v:167972.9-167972.17" case 1'1 case end @@ -343505,7 +346002,7 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -343517,37 +346014,37 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\trap_op__cia$next[63:0]$9264 \trap_op__cia - assign $1\trap_op__fn_unit$next[13:0]$9265 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9266 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9267 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9268 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9269 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9270 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9271 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9272 \trap_op__traptype + assign $1\trap_op__cia$next[63:0]$9312 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9313 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9314 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9315 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9316 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9317 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9318 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9319 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9320 \trap_op__traptype end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9255 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9256 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9257 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9258 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9259 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9260 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9261 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9262 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9263 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9303 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9304 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9305 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9306 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9307 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9308 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9309 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 end - attribute \src "libresoc.v:166360.3-166372.6" - process $proc$libresoc.v:166360$9273 + attribute \src "libresoc.v:167992.3-168004.6" + process $proc$libresoc.v:167992$9321 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9274 $1\ra$next[63:0]$9275 - attribute \src "libresoc.v:166361.5-166361.29" + assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 + attribute \src "libresoc.v:167993.5-167993.29" switch \initial - attribute \src "libresoc.v:166361.9-166361.17" + attribute \src "libresoc.v:167993.9-167993.17" case 1'1 case end @@ -343556,25 +346053,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9275 \ra$42 + assign $1\ra$next[63:0]$9323 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9275 \ra$42 + assign $1\ra$next[63:0]$9323 \ra$42 case - assign $1\ra$next[63:0]$9275 \ra + assign $1\ra$next[63:0]$9323 \ra end sync always - update \ra$next $0\ra$next[63:0]$9274 + update \ra$next $0\ra$next[63:0]$9322 end - attribute \src "libresoc.v:166373.3-166385.6" - process $proc$libresoc.v:166373$9276 + attribute \src "libresoc.v:168005.3-168017.6" + process $proc$libresoc.v:168005$9324 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9277 $1\rb$next[63:0]$9278 - attribute \src "libresoc.v:166374.5-166374.29" + assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 + attribute \src "libresoc.v:168006.5-168006.29" switch \initial - attribute \src "libresoc.v:166374.9-166374.17" + attribute \src "libresoc.v:168006.9-168006.17" case 1'1 case end @@ -343583,25 +346080,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9278 \rb$43 + assign $1\rb$next[63:0]$9326 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9278 \rb$43 + assign $1\rb$next[63:0]$9326 \rb$43 case - assign $1\rb$next[63:0]$9278 \rb + assign $1\rb$next[63:0]$9326 \rb end sync always - update \rb$next $0\rb$next[63:0]$9277 + update \rb$next $0\rb$next[63:0]$9325 end - attribute \src "libresoc.v:166386.3-166398.6" - process $proc$libresoc.v:166386$9279 + attribute \src "libresoc.v:168018.3-168030.6" + process $proc$libresoc.v:168018$9327 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9280 $1\fast1$next[63:0]$9281 - attribute \src "libresoc.v:166387.5-166387.29" + assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 + attribute \src "libresoc.v:168019.5-168019.29" switch \initial - attribute \src "libresoc.v:166387.9-166387.17" + attribute \src "libresoc.v:168019.9-168019.17" case 1'1 case end @@ -343610,25 +346107,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9281 \fast1$44 + assign $1\fast1$next[63:0]$9329 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9281 \fast1$44 + assign $1\fast1$next[63:0]$9329 \fast1$44 case - assign $1\fast1$next[63:0]$9281 \fast1 + assign $1\fast1$next[63:0]$9329 \fast1 end sync always - update \fast1$next $0\fast1$next[63:0]$9280 + update \fast1$next $0\fast1$next[63:0]$9328 end - attribute \src "libresoc.v:166399.3-166411.6" - process $proc$libresoc.v:166399$9282 + attribute \src "libresoc.v:168031.3-168043.6" + process $proc$libresoc.v:168031$9330 assign { } { } assign { } { } - assign $0\fast2$next[63:0]$9283 $1\fast2$next[63:0]$9284 - attribute \src "libresoc.v:166400.5-166400.29" + assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 + attribute \src "libresoc.v:168032.5-168032.29" switch \initial - attribute \src "libresoc.v:166400.9-166400.17" + attribute \src "libresoc.v:168032.9-168032.17" case 1'1 case end @@ -343637,18 +346134,18 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$9284 \fast2$45 + assign $1\fast2$next[63:0]$9332 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$9284 \fast2$45 + assign $1\fast2$next[63:0]$9332 \fast2$45 case - assign $1\fast2$next[63:0]$9284 \fast2 + assign $1\fast2$next[63:0]$9332 \fast2 end sync always - update \fast2$next $0\fast2$next[63:0]$9283 + update \fast2$next $0\fast2$next[63:0]$9331 end - connect \$30 $and$libresoc.v:166239$9231_Y + connect \$30 $and$libresoc.v:167871$9279_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -343667,279 +346164,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:166433.1-167618.10" +attribute \src "libresoc.v:168065.1-169250.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9369 - attribute \src "libresoc.v:167359.3-167360.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9355 - attribute \src "libresoc.v:166441.13-166441.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9443 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9370 - attribute \src "libresoc.v:167329.3-167330.53" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9325 - attribute \src "libresoc.v:166480.14-166480.44" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9445 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9371 - attribute \src "libresoc.v:167331.3-167332.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9327 - attribute \src "libresoc.v:166504.14-166504.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9447 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9372 - attribute \src "libresoc.v:167333.3-167334.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9329 - attribute \src "libresoc.v:166513.7-166513.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9449 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9373 - attribute \src "libresoc.v:167351.3-167352.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9347 - attribute \src "libresoc.v:166530.13-166530.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9451 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9374 - attribute \src "libresoc.v:167361.3-167362.49" - wire width 32 $0\alu_op__insn$19[31:0]$9357 - attribute \src "libresoc.v:166543.14-166543.39" - wire width 32 $0\alu_op__insn$19[31:0]$9453 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9375 - attribute \src "libresoc.v:167327.3-167328.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9323 - attribute \src "libresoc.v:166702.13-166702.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9455 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__invert_in$10$next[0:0]$9376 - attribute \src "libresoc.v:167343.3-167344.59" - wire $0\alu_op__invert_in$10[0:0]$9339 - attribute \src "libresoc.v:166786.7-166786.36" - wire $0\alu_op__invert_in$10[0:0]$9457 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__invert_out$12$next[0:0]$9377 - attribute \src "libresoc.v:167347.3-167348.61" - wire $0\alu_op__invert_out$12[0:0]$9343 - attribute \src "libresoc.v:166795.7-166795.37" - wire $0\alu_op__invert_out$12[0:0]$9459 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9378 - attribute \src "libresoc.v:167355.3-167356.57" - wire $0\alu_op__is_32bit$16[0:0]$9351 - attribute \src "libresoc.v:166804.7-166804.35" - wire $0\alu_op__is_32bit$16[0:0]$9461 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__is_signed$17$next[0:0]$9379 - attribute \src "libresoc.v:167357.3-167358.59" - wire $0\alu_op__is_signed$17[0:0]$9353 - attribute \src "libresoc.v:166813.7-166813.36" - wire $0\alu_op__is_signed$17[0:0]$9463 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9380 - attribute \src "libresoc.v:167339.3-167340.51" - wire $0\alu_op__oe__oe$8[0:0]$9335 - attribute \src "libresoc.v:166824.7-166824.32" - wire $0\alu_op__oe__oe$8[0:0]$9465 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9381 - attribute \src "libresoc.v:167341.3-167342.51" - wire $0\alu_op__oe__ok$9[0:0]$9337 - attribute \src "libresoc.v:166833.7-166833.32" - wire $0\alu_op__oe__ok$9[0:0]$9467 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__output_carry$15$next[0:0]$9382 - attribute \src "libresoc.v:167353.3-167354.65" - wire $0\alu_op__output_carry$15[0:0]$9349 - attribute \src "libresoc.v:166840.7-166840.39" - wire $0\alu_op__output_carry$15[0:0]$9469 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9383 - attribute \src "libresoc.v:167337.3-167338.51" - wire $0\alu_op__rc__ok$7[0:0]$9333 - attribute \src "libresoc.v:166851.7-166851.32" - wire $0\alu_op__rc__ok$7[0:0]$9471 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9384 - attribute \src "libresoc.v:167335.3-167336.51" - wire $0\alu_op__rc__rc$6[0:0]$9331 - attribute \src "libresoc.v:166858.7-166858.32" - wire $0\alu_op__rc__rc$6[0:0]$9473 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9385 - attribute \src "libresoc.v:167349.3-167350.59" - wire $0\alu_op__write_cr0$13[0:0]$9345 - attribute \src "libresoc.v:166867.7-166867.36" - wire $0\alu_op__write_cr0$13[0:0]$9475 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__zero_a$11$next[0:0]$9386 - attribute \src "libresoc.v:167345.3-167346.53" - wire $0\alu_op__zero_a$11[0:0]$9341 - attribute \src "libresoc.v:166876.7-166876.33" - wire $0\alu_op__zero_a$11[0:0]$9477 - attribute \src "libresoc.v:167523.3-167541.6" - wire width 4 $0\cr_a$22$next[3:0]$9418 - attribute \src "libresoc.v:167319.3-167320.33" - wire width 4 $0\cr_a$22[3:0]$9315 - attribute \src "libresoc.v:166889.13-166889.29" - wire width 4 $0\cr_a$22[3:0]$9479 - attribute \src "libresoc.v:167523.3-167541.6" - wire $0\cr_a_ok$23$next[0:0]$9419 - attribute \src "libresoc.v:167321.3-167322.39" - wire $0\cr_a_ok$23[0:0]$9317 - attribute \src "libresoc.v:166898.7-166898.26" - wire $0\cr_a_ok$23[0:0]$9481 - attribute \src "libresoc.v:166434.7-166434.20" + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 + attribute \src "libresoc.v:168991.3-168992.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9403 + attribute \src "libresoc.v:168073.13-168073.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9491 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 + attribute \src "libresoc.v:168961.3-168962.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 + attribute \src "libresoc.v:168112.14-168112.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 + attribute \src "libresoc.v:168963.3-168964.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 + attribute \src "libresoc.v:168136.14-168136.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 + attribute \src "libresoc.v:168965.3-168966.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9377 + attribute \src "libresoc.v:168145.7-168145.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9497 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 + attribute \src "libresoc.v:168983.3-168984.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9395 + attribute \src "libresoc.v:168162.13-168162.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9499 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9422 + attribute \src "libresoc.v:168993.3-168994.49" + wire width 32 $0\alu_op__insn$19[31:0]$9405 + attribute \src "libresoc.v:168175.14-168175.39" + wire width 32 $0\alu_op__insn$19[31:0]$9501 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 + attribute \src "libresoc.v:168959.3-168960.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9371 + attribute \src "libresoc.v:168334.13-168334.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9503 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_in$10$next[0:0]$9424 + attribute \src "libresoc.v:168975.3-168976.59" + wire $0\alu_op__invert_in$10[0:0]$9387 + attribute \src "libresoc.v:168418.7-168418.36" + wire $0\alu_op__invert_in$10[0:0]$9505 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_out$12$next[0:0]$9425 + attribute \src "libresoc.v:168979.3-168980.61" + wire $0\alu_op__invert_out$12[0:0]$9391 + attribute \src "libresoc.v:168427.7-168427.37" + wire $0\alu_op__invert_out$12[0:0]$9507 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9426 + attribute \src "libresoc.v:168987.3-168988.57" + wire $0\alu_op__is_32bit$16[0:0]$9399 + attribute \src "libresoc.v:168436.7-168436.35" + wire $0\alu_op__is_32bit$16[0:0]$9509 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_signed$17$next[0:0]$9427 + attribute \src "libresoc.v:168989.3-168990.59" + wire $0\alu_op__is_signed$17[0:0]$9401 + attribute \src "libresoc.v:168445.7-168445.36" + wire $0\alu_op__is_signed$17[0:0]$9511 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9428 + attribute \src "libresoc.v:168971.3-168972.51" + wire $0\alu_op__oe__oe$8[0:0]$9383 + attribute \src "libresoc.v:168456.7-168456.32" + wire $0\alu_op__oe__oe$8[0:0]$9513 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9429 + attribute \src "libresoc.v:168973.3-168974.51" + wire $0\alu_op__oe__ok$9[0:0]$9385 + attribute \src "libresoc.v:168465.7-168465.32" + wire $0\alu_op__oe__ok$9[0:0]$9515 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__output_carry$15$next[0:0]$9430 + attribute \src "libresoc.v:168985.3-168986.65" + wire $0\alu_op__output_carry$15[0:0]$9397 + attribute \src "libresoc.v:168472.7-168472.39" + wire $0\alu_op__output_carry$15[0:0]$9517 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9431 + attribute \src "libresoc.v:168969.3-168970.51" + wire $0\alu_op__rc__ok$7[0:0]$9381 + attribute \src "libresoc.v:168483.7-168483.32" + wire $0\alu_op__rc__ok$7[0:0]$9519 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9432 + attribute \src "libresoc.v:168967.3-168968.51" + wire $0\alu_op__rc__rc$6[0:0]$9379 + attribute \src "libresoc.v:168490.7-168490.32" + wire $0\alu_op__rc__rc$6[0:0]$9521 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9433 + attribute \src "libresoc.v:168981.3-168982.59" + wire $0\alu_op__write_cr0$13[0:0]$9393 + attribute \src "libresoc.v:168499.7-168499.36" + wire $0\alu_op__write_cr0$13[0:0]$9523 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__zero_a$11$next[0:0]$9434 + attribute \src "libresoc.v:168977.3-168978.53" + wire $0\alu_op__zero_a$11[0:0]$9389 + attribute \src "libresoc.v:168508.7-168508.33" + wire $0\alu_op__zero_a$11[0:0]$9525 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $0\cr_a$22$next[3:0]$9466 + attribute \src "libresoc.v:168951.3-168952.33" + wire width 4 $0\cr_a$22[3:0]$9363 + attribute \src "libresoc.v:168521.13-168521.29" + wire width 4 $0\cr_a$22[3:0]$9527 + attribute \src "libresoc.v:169155.3-169173.6" + wire $0\cr_a_ok$23$next[0:0]$9467 + attribute \src "libresoc.v:168953.3-168954.39" + wire $0\cr_a_ok$23[0:0]$9365 + attribute \src "libresoc.v:168530.7-168530.26" + wire $0\cr_a_ok$23[0:0]$9529 + attribute \src "libresoc.v:168066.7-168066.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167449.3-167461.6" - wire width 2 $0\muxid$1$next[1:0]$9366 - attribute \src "libresoc.v:167363.3-167364.33" - wire width 2 $0\muxid$1[1:0]$9359 - attribute \src "libresoc.v:166909.13-166909.29" - wire width 2 $0\muxid$1[1:0]$9483 - attribute \src "libresoc.v:167504.3-167522.6" - wire width 64 $0\o$20$next[63:0]$9412 - attribute \src "libresoc.v:167323.3-167324.27" - wire width 64 $0\o$20[63:0]$9319 - attribute \src "libresoc.v:166924.14-166924.43" - wire width 64 $0\o$20[63:0]$9485 - attribute \src "libresoc.v:167504.3-167522.6" - wire $0\o_ok$21$next[0:0]$9413 - attribute \src "libresoc.v:167325.3-167326.33" - wire $0\o_ok$21[0:0]$9321 - attribute \src "libresoc.v:166933.7-166933.23" - wire $0\o_ok$21[0:0]$9487 - attribute \src "libresoc.v:167431.3-167448.6" - wire $0\r_busy$next[0:0]$9362 - attribute \src "libresoc.v:167365.3-167366.29" + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $0\muxid$1$next[1:0]$9414 + attribute \src "libresoc.v:168995.3-168996.33" + wire width 2 $0\muxid$1[1:0]$9407 + attribute \src "libresoc.v:168541.13-168541.29" + wire width 2 $0\muxid$1[1:0]$9531 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $0\o$20$next[63:0]$9460 + attribute \src "libresoc.v:168955.3-168956.27" + wire width 64 $0\o$20[63:0]$9367 + attribute \src "libresoc.v:168556.14-168556.43" + wire width 64 $0\o$20[63:0]$9533 + attribute \src "libresoc.v:169136.3-169154.6" + wire $0\o_ok$21$next[0:0]$9461 + attribute \src "libresoc.v:168957.3-168958.33" + wire $0\o_ok$21[0:0]$9369 + attribute \src "libresoc.v:168565.7-168565.23" + wire $0\o_ok$21[0:0]$9535 + attribute \src "libresoc.v:169063.3-169080.6" + wire $0\r_busy$next[0:0]$9410 + attribute \src "libresoc.v:168997.3-168998.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167542.3-167560.6" - wire width 2 $0\xer_ca$24$next[1:0]$9424 - attribute \src "libresoc.v:167315.3-167316.37" - wire width 2 $0\xer_ca$24[1:0]$9311 - attribute \src "libresoc.v:167250.13-167250.31" - wire width 2 $0\xer_ca$24[1:0]$9490 - attribute \src "libresoc.v:167542.3-167560.6" - wire $0\xer_ca_ok$25$next[0:0]$9425 - attribute \src "libresoc.v:167317.3-167318.43" - wire $0\xer_ca_ok$25[0:0]$9313 - attribute \src "libresoc.v:167259.7-167259.28" - wire $0\xer_ca_ok$25[0:0]$9492 - attribute \src "libresoc.v:167561.3-167579.6" - wire width 2 $0\xer_ov$26$next[1:0]$9430 - attribute \src "libresoc.v:167311.3-167312.37" - wire width 2 $0\xer_ov$26[1:0]$9307 - attribute \src "libresoc.v:167270.13-167270.31" - wire width 2 $0\xer_ov$26[1:0]$9494 - attribute \src "libresoc.v:167561.3-167579.6" - wire $0\xer_ov_ok$27$next[0:0]$9431 - attribute \src "libresoc.v:167313.3-167314.43" - wire $0\xer_ov_ok$27[0:0]$9309 - attribute \src "libresoc.v:167279.7-167279.28" - wire $0\xer_ov_ok$27[0:0]$9496 - attribute \src "libresoc.v:167580.3-167598.6" - wire $0\xer_so$28$next[0:0]$9436 - attribute \src "libresoc.v:167307.3-167308.37" - wire $0\xer_so$28[0:0]$9303 - attribute \src "libresoc.v:167290.7-167290.25" - wire $0\xer_so$28[0:0]$9498 - attribute \src "libresoc.v:167580.3-167598.6" - wire $0\xer_so_ok$29$next[0:0]$9437 - attribute \src "libresoc.v:167309.3-167310.43" - wire $0\xer_so_ok$29[0:0]$9305 - attribute \src "libresoc.v:167299.7-167299.28" - wire $0\xer_so_ok$29[0:0]$9500 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9387 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9388 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9389 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9390 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9391 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9392 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9393 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__invert_in$10$next[0:0]$9394 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__invert_out$12$next[0:0]$9395 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9396 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__is_signed$17$next[0:0]$9397 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9398 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9399 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__output_carry$15$next[0:0]$9400 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9401 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9402 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9403 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__zero_a$11$next[0:0]$9404 - attribute \src "libresoc.v:167523.3-167541.6" - wire width 4 $1\cr_a$22$next[3:0]$9420 - attribute \src "libresoc.v:167523.3-167541.6" - wire $1\cr_a_ok$23$next[0:0]$9421 - attribute \src "libresoc.v:167449.3-167461.6" - wire width 2 $1\muxid$1$next[1:0]$9367 - attribute \src "libresoc.v:167504.3-167522.6" - wire width 64 $1\o$20$next[63:0]$9414 - attribute \src "libresoc.v:167504.3-167522.6" - wire $1\o_ok$21$next[0:0]$9415 - attribute \src "libresoc.v:167431.3-167448.6" - wire $1\r_busy$next[0:0]$9363 - attribute \src "libresoc.v:167243.7-167243.20" + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $0\xer_ca$24$next[1:0]$9472 + attribute \src "libresoc.v:168947.3-168948.37" + wire width 2 $0\xer_ca$24[1:0]$9359 + attribute \src "libresoc.v:168882.13-168882.31" + wire width 2 $0\xer_ca$24[1:0]$9538 + attribute \src "libresoc.v:169174.3-169192.6" + wire $0\xer_ca_ok$25$next[0:0]$9473 + attribute \src "libresoc.v:168949.3-168950.43" + wire $0\xer_ca_ok$25[0:0]$9361 + attribute \src "libresoc.v:168891.7-168891.28" + wire $0\xer_ca_ok$25[0:0]$9540 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $0\xer_ov$26$next[1:0]$9478 + attribute \src "libresoc.v:168943.3-168944.37" + wire width 2 $0\xer_ov$26[1:0]$9355 + attribute \src "libresoc.v:168902.13-168902.31" + wire width 2 $0\xer_ov$26[1:0]$9542 + attribute \src "libresoc.v:169193.3-169211.6" + wire $0\xer_ov_ok$27$next[0:0]$9479 + attribute \src "libresoc.v:168945.3-168946.43" + wire $0\xer_ov_ok$27[0:0]$9357 + attribute \src "libresoc.v:168911.7-168911.28" + wire $0\xer_ov_ok$27[0:0]$9544 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so$28$next[0:0]$9484 + attribute \src "libresoc.v:168939.3-168940.37" + wire $0\xer_so$28[0:0]$9351 + attribute \src "libresoc.v:168922.7-168922.25" + wire $0\xer_so$28[0:0]$9546 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so_ok$29$next[0:0]$9485 + attribute \src "libresoc.v:168941.3-168942.43" + wire $0\xer_so_ok$29[0:0]$9353 + attribute \src "libresoc.v:168931.7-168931.28" + wire $0\xer_so_ok$29[0:0]$9548 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9440 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_in$10$next[0:0]$9442 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_out$12$next[0:0]$9443 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9444 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_signed$17$next[0:0]$9445 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9446 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9447 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__output_carry$15$next[0:0]$9448 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9449 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9450 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9451 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__zero_a$11$next[0:0]$9452 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $1\cr_a$22$next[3:0]$9468 + attribute \src "libresoc.v:169155.3-169173.6" + wire $1\cr_a_ok$23$next[0:0]$9469 + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $1\o$20$next[63:0]$9462 + attribute \src "libresoc.v:169136.3-169154.6" + wire $1\o_ok$21$next[0:0]$9463 + attribute \src "libresoc.v:169063.3-169080.6" + wire $1\r_busy$next[0:0]$9411 + attribute \src "libresoc.v:168875.7-168875.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167542.3-167560.6" - wire width 2 $1\xer_ca$24$next[1:0]$9426 - attribute \src "libresoc.v:167542.3-167560.6" - wire $1\xer_ca_ok$25$next[0:0]$9427 - attribute \src "libresoc.v:167561.3-167579.6" - wire width 2 $1\xer_ov$26$next[1:0]$9432 - attribute \src "libresoc.v:167561.3-167579.6" - wire $1\xer_ov_ok$27$next[0:0]$9433 - attribute \src "libresoc.v:167580.3-167598.6" - wire $1\xer_so$28$next[0:0]$9438 - attribute \src "libresoc.v:167580.3-167598.6" - wire $1\xer_so_ok$29$next[0:0]$9439 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9405 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9406 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9407 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9408 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9409 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9410 - attribute \src "libresoc.v:167523.3-167541.6" - wire $2\cr_a_ok$23$next[0:0]$9422 - attribute \src "libresoc.v:167504.3-167522.6" - wire $2\o_ok$21$next[0:0]$9416 - attribute \src "libresoc.v:167431.3-167448.6" - wire $2\r_busy$next[0:0]$9364 - attribute \src "libresoc.v:167542.3-167560.6" - wire $2\xer_ca_ok$25$next[0:0]$9428 - attribute \src "libresoc.v:167561.3-167579.6" - wire $2\xer_ov_ok$27$next[0:0]$9434 - attribute \src "libresoc.v:167580.3-167598.6" - wire $2\xer_so_ok$29$next[0:0]$9440 - attribute \src "libresoc.v:167306.18-167306.118" - wire $and$libresoc.v:167306$9301_Y + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $1\xer_ca$24$next[1:0]$9474 + attribute \src "libresoc.v:169174.3-169192.6" + wire $1\xer_ca_ok$25$next[0:0]$9475 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $1\xer_ov$26$next[1:0]$9480 + attribute \src "libresoc.v:169193.3-169211.6" + wire $1\xer_ov_ok$27$next[0:0]$9481 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so$28$next[0:0]$9486 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so_ok$29$next[0:0]$9487 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9455 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9456 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9457 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169155.3-169173.6" + wire $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169136.3-169154.6" + wire $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169063.3-169080.6" + wire $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169174.3-169192.6" + wire $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169193.3-169211.6" + wire $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169212.3-169230.6" + wire $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:168938.18-168938.118" + wire $and$libresoc.v:168938$9349_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -344368,9 +346865,9 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -344390,7 +346887,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$84 - attribute \src "libresoc.v:166434.7-166434.15" + attribute \src "libresoc.v:168066.7-168066.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -344785,7 +347282,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167306$9301 + cell $and $and$libresoc.v:168938$9349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -344793,16 +347290,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:167306$9301_Y + connect \Y $and$libresoc.v:168938$9349_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167367.9-167370.4" + attribute \src "libresoc.v:168999.9-169002.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167371.12-167426.4" + attribute \src "libresoc.v:169003.12-169058.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -344860,478 +347357,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:167427.9-167430.4" + attribute \src "libresoc.v:169059.9-169062.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:166434.7-166434.20" - process $proc$libresoc.v:166434$9441 + attribute \src "libresoc.v:168066.7-168066.20" + process $proc$libresoc.v:168066$9489 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166441.13-166441.41" - process $proc$libresoc.v:166441$9442 + attribute \src "libresoc.v:168073.13-168073.41" + process $proc$libresoc.v:168073$9490 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9443 4'0000 + assign $0\alu_op__data_len$18[3:0]$9491 4'0000 sync always sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9443 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 end - attribute \src "libresoc.v:166480.14-166480.44" - process $proc$libresoc.v:166480$9444 + attribute \src "libresoc.v:168112.14-168112.44" + process $proc$libresoc.v:168112$9492 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9445 14'00000000000000 + assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 sync always sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9445 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 end - attribute \src "libresoc.v:166504.14-166504.63" - process $proc$libresoc.v:166504$9446 + attribute \src "libresoc.v:168136.14-168136.63" + process $proc$libresoc.v:168136$9494 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9447 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9447 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 end - attribute \src "libresoc.v:166513.7-166513.38" - process $proc$libresoc.v:166513$9448 + attribute \src "libresoc.v:168145.7-168145.38" + process $proc$libresoc.v:168145$9496 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9449 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9449 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 end - attribute \src "libresoc.v:166530.13-166530.44" - process $proc$libresoc.v:166530$9450 + attribute \src "libresoc.v:168162.13-168162.44" + process $proc$libresoc.v:168162$9498 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9451 2'00 + assign $0\alu_op__input_carry$14[1:0]$9499 2'00 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9451 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 end - attribute \src "libresoc.v:166543.14-166543.39" - process $proc$libresoc.v:166543$9452 + attribute \src "libresoc.v:168175.14-168175.39" + process $proc$libresoc.v:168175$9500 assign { } { } - assign $0\alu_op__insn$19[31:0]$9453 0 + assign $0\alu_op__insn$19[31:0]$9501 0 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9453 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 end - attribute \src "libresoc.v:166702.13-166702.42" - process $proc$libresoc.v:166702$9454 + attribute \src "libresoc.v:168334.13-168334.42" + process $proc$libresoc.v:168334$9502 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9455 7'0000000 + assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9455 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 end - attribute \src "libresoc.v:166786.7-166786.36" - process $proc$libresoc.v:166786$9456 + attribute \src "libresoc.v:168418.7-168418.36" + process $proc$libresoc.v:168418$9504 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9457 1'0 + assign $0\alu_op__invert_in$10[0:0]$9505 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9457 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 end - attribute \src "libresoc.v:166795.7-166795.37" - process $proc$libresoc.v:166795$9458 + attribute \src "libresoc.v:168427.7-168427.37" + process $proc$libresoc.v:168427$9506 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9459 1'0 + assign $0\alu_op__invert_out$12[0:0]$9507 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9459 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 end - attribute \src "libresoc.v:166804.7-166804.35" - process $proc$libresoc.v:166804$9460 + attribute \src "libresoc.v:168436.7-168436.35" + process $proc$libresoc.v:168436$9508 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9461 1'0 + assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9461 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 end - attribute \src "libresoc.v:166813.7-166813.36" - process $proc$libresoc.v:166813$9462 + attribute \src "libresoc.v:168445.7-168445.36" + process $proc$libresoc.v:168445$9510 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9463 1'0 + assign $0\alu_op__is_signed$17[0:0]$9511 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9463 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 end - attribute \src "libresoc.v:166824.7-166824.32" - process $proc$libresoc.v:166824$9464 + attribute \src "libresoc.v:168456.7-168456.32" + process $proc$libresoc.v:168456$9512 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9465 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9465 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 end - attribute \src "libresoc.v:166833.7-166833.32" - process $proc$libresoc.v:166833$9466 + attribute \src "libresoc.v:168465.7-168465.32" + process $proc$libresoc.v:168465$9514 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9467 1'0 + assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9467 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 end - attribute \src "libresoc.v:166840.7-166840.39" - process $proc$libresoc.v:166840$9468 + attribute \src "libresoc.v:168472.7-168472.39" + process $proc$libresoc.v:168472$9516 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9469 1'0 + assign $0\alu_op__output_carry$15[0:0]$9517 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9469 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 end - attribute \src "libresoc.v:166851.7-166851.32" - process $proc$libresoc.v:166851$9470 + attribute \src "libresoc.v:168483.7-168483.32" + process $proc$libresoc.v:168483$9518 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9471 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9471 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 end - attribute \src "libresoc.v:166858.7-166858.32" - process $proc$libresoc.v:166858$9472 + attribute \src "libresoc.v:168490.7-168490.32" + process $proc$libresoc.v:168490$9520 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9473 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9473 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 end - attribute \src "libresoc.v:166867.7-166867.36" - process $proc$libresoc.v:166867$9474 + attribute \src "libresoc.v:168499.7-168499.36" + process $proc$libresoc.v:168499$9522 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9475 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9475 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 end - attribute \src "libresoc.v:166876.7-166876.33" - process $proc$libresoc.v:166876$9476 + attribute \src "libresoc.v:168508.7-168508.33" + process $proc$libresoc.v:168508$9524 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9477 1'0 + assign $0\alu_op__zero_a$11[0:0]$9525 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9477 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 end - attribute \src "libresoc.v:166889.13-166889.29" - process $proc$libresoc.v:166889$9478 + attribute \src "libresoc.v:168521.13-168521.29" + process $proc$libresoc.v:168521$9526 assign { } { } - assign $0\cr_a$22[3:0]$9479 4'0000 + assign $0\cr_a$22[3:0]$9527 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9479 + update \cr_a$22 $0\cr_a$22[3:0]$9527 end - attribute \src "libresoc.v:166898.7-166898.26" - process $proc$libresoc.v:166898$9480 + attribute \src "libresoc.v:168530.7-168530.26" + process $proc$libresoc.v:168530$9528 assign { } { } - assign $0\cr_a_ok$23[0:0]$9481 1'0 + assign $0\cr_a_ok$23[0:0]$9529 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9481 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 end - attribute \src "libresoc.v:166909.13-166909.29" - process $proc$libresoc.v:166909$9482 + attribute \src "libresoc.v:168541.13-168541.29" + process $proc$libresoc.v:168541$9530 assign { } { } - assign $0\muxid$1[1:0]$9483 2'00 + assign $0\muxid$1[1:0]$9531 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9483 + update \muxid$1 $0\muxid$1[1:0]$9531 end - attribute \src "libresoc.v:166924.14-166924.43" - process $proc$libresoc.v:166924$9484 + attribute \src "libresoc.v:168556.14-168556.43" + process $proc$libresoc.v:168556$9532 assign { } { } - assign $0\o$20[63:0]$9485 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$9485 + update \o$20 $0\o$20[63:0]$9533 end - attribute \src "libresoc.v:166933.7-166933.23" - process $proc$libresoc.v:166933$9486 + attribute \src "libresoc.v:168565.7-168565.23" + process $proc$libresoc.v:168565$9534 assign { } { } - assign $0\o_ok$21[0:0]$9487 1'0 + assign $0\o_ok$21[0:0]$9535 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9487 + update \o_ok$21 $0\o_ok$21[0:0]$9535 end - attribute \src "libresoc.v:167243.7-167243.20" - process $proc$libresoc.v:167243$9488 + attribute \src "libresoc.v:168875.7-168875.20" + process $proc$libresoc.v:168875$9536 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167250.13-167250.31" - process $proc$libresoc.v:167250$9489 + attribute \src "libresoc.v:168882.13-168882.31" + process $proc$libresoc.v:168882$9537 assign { } { } - assign $0\xer_ca$24[1:0]$9490 2'00 + assign $0\xer_ca$24[1:0]$9538 2'00 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9490 + update \xer_ca$24 $0\xer_ca$24[1:0]$9538 end - attribute \src "libresoc.v:167259.7-167259.28" - process $proc$libresoc.v:167259$9491 + attribute \src "libresoc.v:168891.7-168891.28" + process $proc$libresoc.v:168891$9539 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9492 1'0 + assign $0\xer_ca_ok$25[0:0]$9540 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9492 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 end - attribute \src "libresoc.v:167270.13-167270.31" - process $proc$libresoc.v:167270$9493 + attribute \src "libresoc.v:168902.13-168902.31" + process $proc$libresoc.v:168902$9541 assign { } { } - assign $0\xer_ov$26[1:0]$9494 2'00 + assign $0\xer_ov$26[1:0]$9542 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9494 + update \xer_ov$26 $0\xer_ov$26[1:0]$9542 end - attribute \src "libresoc.v:167279.7-167279.28" - process $proc$libresoc.v:167279$9495 + attribute \src "libresoc.v:168911.7-168911.28" + process $proc$libresoc.v:168911$9543 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9496 1'0 + assign $0\xer_ov_ok$27[0:0]$9544 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9496 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 end - attribute \src "libresoc.v:167290.7-167290.25" - process $proc$libresoc.v:167290$9497 + attribute \src "libresoc.v:168922.7-168922.25" + process $proc$libresoc.v:168922$9545 assign { } { } - assign $0\xer_so$28[0:0]$9498 1'0 + assign $0\xer_so$28[0:0]$9546 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9498 + update \xer_so$28 $0\xer_so$28[0:0]$9546 end - attribute \src "libresoc.v:167299.7-167299.28" - process $proc$libresoc.v:167299$9499 + attribute \src "libresoc.v:168931.7-168931.28" + process $proc$libresoc.v:168931$9547 assign { } { } - assign $0\xer_so_ok$29[0:0]$9500 1'0 + assign $0\xer_so_ok$29[0:0]$9548 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9500 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 end - attribute \src "libresoc.v:167307.3-167308.37" - process $proc$libresoc.v:167307$9302 + attribute \src "libresoc.v:168939.3-168940.37" + process $proc$libresoc.v:168939$9350 assign { } { } - assign $0\xer_so$28[0:0]$9303 \xer_so$28$next + assign $0\xer_so$28[0:0]$9351 \xer_so$28$next sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9303 + update \xer_so$28 $0\xer_so$28[0:0]$9351 end - attribute \src "libresoc.v:167309.3-167310.43" - process $proc$libresoc.v:167309$9304 + attribute \src "libresoc.v:168941.3-168942.43" + process $proc$libresoc.v:168941$9352 assign { } { } - assign $0\xer_so_ok$29[0:0]$9305 \xer_so_ok$29$next + assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9305 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 end - attribute \src "libresoc.v:167311.3-167312.37" - process $proc$libresoc.v:167311$9306 + attribute \src "libresoc.v:168943.3-168944.37" + process $proc$libresoc.v:168943$9354 assign { } { } - assign $0\xer_ov$26[1:0]$9307 \xer_ov$26$next + assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9307 + update \xer_ov$26 $0\xer_ov$26[1:0]$9355 end - attribute \src "libresoc.v:167313.3-167314.43" - process $proc$libresoc.v:167313$9308 + attribute \src "libresoc.v:168945.3-168946.43" + process $proc$libresoc.v:168945$9356 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9309 \xer_ov_ok$27$next + assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9309 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 end - attribute \src "libresoc.v:167315.3-167316.37" - process $proc$libresoc.v:167315$9310 + attribute \src "libresoc.v:168947.3-168948.37" + process $proc$libresoc.v:168947$9358 assign { } { } - assign $0\xer_ca$24[1:0]$9311 \xer_ca$24$next + assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9311 + update \xer_ca$24 $0\xer_ca$24[1:0]$9359 end - attribute \src "libresoc.v:167317.3-167318.43" - process $proc$libresoc.v:167317$9312 + attribute \src "libresoc.v:168949.3-168950.43" + process $proc$libresoc.v:168949$9360 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9313 \xer_ca_ok$25$next + assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9313 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 end - attribute \src "libresoc.v:167319.3-167320.33" - process $proc$libresoc.v:167319$9314 + attribute \src "libresoc.v:168951.3-168952.33" + process $proc$libresoc.v:168951$9362 assign { } { } - assign $0\cr_a$22[3:0]$9315 \cr_a$22$next + assign $0\cr_a$22[3:0]$9363 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9315 + update \cr_a$22 $0\cr_a$22[3:0]$9363 end - attribute \src "libresoc.v:167321.3-167322.39" - process $proc$libresoc.v:167321$9316 + attribute \src "libresoc.v:168953.3-168954.39" + process $proc$libresoc.v:168953$9364 assign { } { } - assign $0\cr_a_ok$23[0:0]$9317 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9317 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 end - attribute \src "libresoc.v:167323.3-167324.27" - process $proc$libresoc.v:167323$9318 + attribute \src "libresoc.v:168955.3-168956.27" + process $proc$libresoc.v:168955$9366 assign { } { } - assign $0\o$20[63:0]$9319 \o$20$next + assign $0\o$20[63:0]$9367 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9319 + update \o$20 $0\o$20[63:0]$9367 end - attribute \src "libresoc.v:167325.3-167326.33" - process $proc$libresoc.v:167325$9320 + attribute \src "libresoc.v:168957.3-168958.33" + process $proc$libresoc.v:168957$9368 assign { } { } - assign $0\o_ok$21[0:0]$9321 \o_ok$21$next + assign $0\o_ok$21[0:0]$9369 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9321 + update \o_ok$21 $0\o_ok$21[0:0]$9369 end - attribute \src "libresoc.v:167327.3-167328.57" - process $proc$libresoc.v:167327$9322 + attribute \src "libresoc.v:168959.3-168960.57" + process $proc$libresoc.v:168959$9370 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9323 \alu_op__insn_type$2$next + assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9323 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 end - attribute \src "libresoc.v:167329.3-167330.53" - process $proc$libresoc.v:167329$9324 + attribute \src "libresoc.v:168961.3-168962.53" + process $proc$libresoc.v:168961$9372 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9325 \alu_op__fn_unit$3$next + assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9325 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 end - attribute \src "libresoc.v:167331.3-167332.67" - process $proc$libresoc.v:167331$9326 + attribute \src "libresoc.v:168963.3-168964.67" + process $proc$libresoc.v:168963$9374 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9327 \alu_op__imm_data__data$4$next + assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9327 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 end - attribute \src "libresoc.v:167333.3-167334.63" - process $proc$libresoc.v:167333$9328 + attribute \src "libresoc.v:168965.3-168966.63" + process $proc$libresoc.v:168965$9376 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9329 \alu_op__imm_data__ok$5$next + assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9329 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 end - attribute \src "libresoc.v:167335.3-167336.51" - process $proc$libresoc.v:167335$9330 + attribute \src "libresoc.v:168967.3-168968.51" + process $proc$libresoc.v:168967$9378 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9331 \alu_op__rc__rc$6$next + assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9331 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 end - attribute \src "libresoc.v:167337.3-167338.51" - process $proc$libresoc.v:167337$9332 + attribute \src "libresoc.v:168969.3-168970.51" + process $proc$libresoc.v:168969$9380 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9333 \alu_op__rc__ok$7$next + assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9333 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 end - attribute \src "libresoc.v:167339.3-167340.51" - process $proc$libresoc.v:167339$9334 + attribute \src "libresoc.v:168971.3-168972.51" + process $proc$libresoc.v:168971$9382 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9335 \alu_op__oe__oe$8$next + assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9335 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 end - attribute \src "libresoc.v:167341.3-167342.51" - process $proc$libresoc.v:167341$9336 + attribute \src "libresoc.v:168973.3-168974.51" + process $proc$libresoc.v:168973$9384 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9337 \alu_op__oe__ok$9$next + assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9337 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 end - attribute \src "libresoc.v:167343.3-167344.59" - process $proc$libresoc.v:167343$9338 + attribute \src "libresoc.v:168975.3-168976.59" + process $proc$libresoc.v:168975$9386 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9339 \alu_op__invert_in$10$next + assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9339 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 end - attribute \src "libresoc.v:167345.3-167346.53" - process $proc$libresoc.v:167345$9340 + attribute \src "libresoc.v:168977.3-168978.53" + process $proc$libresoc.v:168977$9388 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9341 \alu_op__zero_a$11$next + assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9341 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 end - attribute \src "libresoc.v:167347.3-167348.61" - process $proc$libresoc.v:167347$9342 + attribute \src "libresoc.v:168979.3-168980.61" + process $proc$libresoc.v:168979$9390 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9343 \alu_op__invert_out$12$next + assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9343 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 end - attribute \src "libresoc.v:167349.3-167350.59" - process $proc$libresoc.v:167349$9344 + attribute \src "libresoc.v:168981.3-168982.59" + process $proc$libresoc.v:168981$9392 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9345 \alu_op__write_cr0$13$next + assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9345 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 end - attribute \src "libresoc.v:167351.3-167352.63" - process $proc$libresoc.v:167351$9346 + attribute \src "libresoc.v:168983.3-168984.63" + process $proc$libresoc.v:168983$9394 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9347 \alu_op__input_carry$14$next + assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9347 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 end - attribute \src "libresoc.v:167353.3-167354.65" - process $proc$libresoc.v:167353$9348 + attribute \src "libresoc.v:168985.3-168986.65" + process $proc$libresoc.v:168985$9396 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9349 \alu_op__output_carry$15$next + assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9349 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 end - attribute \src "libresoc.v:167355.3-167356.57" - process $proc$libresoc.v:167355$9350 + attribute \src "libresoc.v:168987.3-168988.57" + process $proc$libresoc.v:168987$9398 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9351 \alu_op__is_32bit$16$next + assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9351 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 end - attribute \src "libresoc.v:167357.3-167358.59" - process $proc$libresoc.v:167357$9352 + attribute \src "libresoc.v:168989.3-168990.59" + process $proc$libresoc.v:168989$9400 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9353 \alu_op__is_signed$17$next + assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9353 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 end - attribute \src "libresoc.v:167359.3-167360.57" - process $proc$libresoc.v:167359$9354 + attribute \src "libresoc.v:168991.3-168992.57" + process $proc$libresoc.v:168991$9402 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9355 \alu_op__data_len$18$next + assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9355 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 end - attribute \src "libresoc.v:167361.3-167362.49" - process $proc$libresoc.v:167361$9356 + attribute \src "libresoc.v:168993.3-168994.49" + process $proc$libresoc.v:168993$9404 assign { } { } - assign $0\alu_op__insn$19[31:0]$9357 \alu_op__insn$19$next + assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9357 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 end - attribute \src "libresoc.v:167363.3-167364.33" - process $proc$libresoc.v:167363$9358 + attribute \src "libresoc.v:168995.3-168996.33" + process $proc$libresoc.v:168995$9406 assign { } { } - assign $0\muxid$1[1:0]$9359 \muxid$1$next + assign $0\muxid$1[1:0]$9407 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9359 + update \muxid$1 $0\muxid$1[1:0]$9407 end - attribute \src "libresoc.v:167365.3-167366.29" - process $proc$libresoc.v:167365$9360 + attribute \src "libresoc.v:168997.3-168998.29" + process $proc$libresoc.v:168997$9408 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167431.3-167448.6" - process $proc$libresoc.v:167431$9361 + attribute \src "libresoc.v:169063.3-169080.6" + process $proc$libresoc.v:169063$9409 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9362 $2\r_busy$next[0:0]$9364 - attribute \src "libresoc.v:167432.5-167432.29" + assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169064.5-169064.29" switch \initial - attribute \src "libresoc.v:167432.9-167432.17" + attribute \src "libresoc.v:169064.9-169064.17" case 1'1 case end @@ -345340,34 +347837,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9363 1'1 + assign $1\r_busy$next[0:0]$9411 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9363 1'0 + assign $1\r_busy$next[0:0]$9411 1'0 case - assign $1\r_busy$next[0:0]$9363 \r_busy + assign $1\r_busy$next[0:0]$9411 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9364 1'0 + assign $2\r_busy$next[0:0]$9412 1'0 case - assign $2\r_busy$next[0:0]$9364 $1\r_busy$next[0:0]$9363 + assign $2\r_busy$next[0:0]$9412 $1\r_busy$next[0:0]$9411 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9362 + update \r_busy$next $0\r_busy$next[0:0]$9410 end - attribute \src "libresoc.v:167449.3-167461.6" - process $proc$libresoc.v:167449$9365 + attribute \src "libresoc.v:169081.3-169093.6" + process $proc$libresoc.v:169081$9413 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9366 $1\muxid$1$next[1:0]$9367 - attribute \src "libresoc.v:167450.5-167450.29" + assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169082.5-169082.29" switch \initial - attribute \src "libresoc.v:167450.9-167450.17" + attribute \src "libresoc.v:169082.9-169082.17" case 1'1 case end @@ -345376,19 +347873,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9367 \muxid$62 + assign $1\muxid$1$next[1:0]$9415 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9367 \muxid$62 + assign $1\muxid$1$next[1:0]$9415 \muxid$62 case - assign $1\muxid$1$next[1:0]$9367 \muxid$1 + assign $1\muxid$1$next[1:0]$9415 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9366 + update \muxid$1$next $0\muxid$1$next[1:0]$9414 end - attribute \src "libresoc.v:167462.3-167503.6" - process $proc$libresoc.v:167462$9368 + attribute \src "libresoc.v:169094.3-169135.6" + process $proc$libresoc.v:169094$9416 assign { } { } assign { } { } assign { } { } @@ -345425,33 +347922,33 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9369 $1\alu_op__data_len$18$next[3:0]$9387 - assign $0\alu_op__fn_unit$3$next[13:0]$9370 $1\alu_op__fn_unit$3$next[13:0]$9388 + assign $0\alu_op__data_len$18$next[3:0]$9417 $1\alu_op__data_len$18$next[3:0]$9435 + assign $0\alu_op__fn_unit$3$next[13:0]$9418 $1\alu_op__fn_unit$3$next[13:0]$9436 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9373 $1\alu_op__input_carry$14$next[1:0]$9391 - assign $0\alu_op__insn$19$next[31:0]$9374 $1\alu_op__insn$19$next[31:0]$9392 - assign $0\alu_op__insn_type$2$next[6:0]$9375 $1\alu_op__insn_type$2$next[6:0]$9393 - assign $0\alu_op__invert_in$10$next[0:0]$9376 $1\alu_op__invert_in$10$next[0:0]$9394 - assign $0\alu_op__invert_out$12$next[0:0]$9377 $1\alu_op__invert_out$12$next[0:0]$9395 - assign $0\alu_op__is_32bit$16$next[0:0]$9378 $1\alu_op__is_32bit$16$next[0:0]$9396 - assign $0\alu_op__is_signed$17$next[0:0]$9379 $1\alu_op__is_signed$17$next[0:0]$9397 + assign $0\alu_op__input_carry$14$next[1:0]$9421 $1\alu_op__input_carry$14$next[1:0]$9439 + assign $0\alu_op__insn$19$next[31:0]$9422 $1\alu_op__insn$19$next[31:0]$9440 + assign $0\alu_op__insn_type$2$next[6:0]$9423 $1\alu_op__insn_type$2$next[6:0]$9441 + assign $0\alu_op__invert_in$10$next[0:0]$9424 $1\alu_op__invert_in$10$next[0:0]$9442 + assign $0\alu_op__invert_out$12$next[0:0]$9425 $1\alu_op__invert_out$12$next[0:0]$9443 + assign $0\alu_op__is_32bit$16$next[0:0]$9426 $1\alu_op__is_32bit$16$next[0:0]$9444 + assign $0\alu_op__is_signed$17$next[0:0]$9427 $1\alu_op__is_signed$17$next[0:0]$9445 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9382 $1\alu_op__output_carry$15$next[0:0]$9400 + assign $0\alu_op__output_carry$15$next[0:0]$9430 $1\alu_op__output_carry$15$next[0:0]$9448 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9385 $1\alu_op__write_cr0$13$next[0:0]$9403 - assign $0\alu_op__zero_a$11$next[0:0]$9386 $1\alu_op__zero_a$11$next[0:0]$9404 - assign $0\alu_op__imm_data__data$4$next[63:0]$9371 $2\alu_op__imm_data__data$4$next[63:0]$9405 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9372 $2\alu_op__imm_data__ok$5$next[0:0]$9406 - assign $0\alu_op__oe__oe$8$next[0:0]$9380 $2\alu_op__oe__oe$8$next[0:0]$9407 - assign $0\alu_op__oe__ok$9$next[0:0]$9381 $2\alu_op__oe__ok$9$next[0:0]$9408 - assign $0\alu_op__rc__ok$7$next[0:0]$9383 $2\alu_op__rc__ok$7$next[0:0]$9409 - assign $0\alu_op__rc__rc$6$next[0:0]$9384 $2\alu_op__rc__rc$6$next[0:0]$9410 - attribute \src "libresoc.v:167463.5-167463.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9433 $1\alu_op__write_cr0$13$next[0:0]$9451 + assign $0\alu_op__zero_a$11$next[0:0]$9434 $1\alu_op__zero_a$11$next[0:0]$9452 + assign $0\alu_op__imm_data__data$4$next[63:0]$9419 $2\alu_op__imm_data__data$4$next[63:0]$9453 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9420 $2\alu_op__imm_data__ok$5$next[0:0]$9454 + assign $0\alu_op__oe__oe$8$next[0:0]$9428 $2\alu_op__oe__oe$8$next[0:0]$9455 + assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 + assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 + assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169095.5-169095.29" switch \initial - attribute \src "libresoc.v:167463.9-167463.17" + attribute \src "libresoc.v:169095.9-169095.17" case 1'1 case end @@ -345477,7 +347974,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -345498,26 +347995,26 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\alu_op__data_len$18$next[3:0]$9387 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[13:0]$9388 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9389 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9390 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9391 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9392 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9393 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9394 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9395 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9396 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9397 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9398 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9399 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9400 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9401 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9402 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9403 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9404 \alu_op__zero_a$11 + assign $1\alu_op__data_len$18$next[3:0]$9435 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9436 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9437 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9438 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9439 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9440 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9441 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9442 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9443 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9444 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9445 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9446 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9447 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9448 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9449 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9450 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9451 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9452 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -345529,52 +348026,52 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9405 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9410 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9409 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9407 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9408 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 1'0 case - assign $2\alu_op__imm_data__data$4$next[63:0]$9405 $1\alu_op__imm_data__data$4$next[63:0]$9389 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 $1\alu_op__imm_data__ok$5$next[0:0]$9390 - assign $2\alu_op__oe__oe$8$next[0:0]$9407 $1\alu_op__oe__oe$8$next[0:0]$9398 - assign $2\alu_op__oe__ok$9$next[0:0]$9408 $1\alu_op__oe__ok$9$next[0:0]$9399 - assign $2\alu_op__rc__ok$7$next[0:0]$9409 $1\alu_op__rc__ok$7$next[0:0]$9401 - assign $2\alu_op__rc__rc$6$next[0:0]$9410 $1\alu_op__rc__rc$6$next[0:0]$9402 + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 $1\alu_op__imm_data__data$4$next[63:0]$9437 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 $1\alu_op__imm_data__ok$5$next[0:0]$9438 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 $1\alu_op__oe__oe$8$next[0:0]$9446 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 $1\alu_op__oe__ok$9$next[0:0]$9447 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 $1\alu_op__rc__ok$7$next[0:0]$9449 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 $1\alu_op__rc__rc$6$next[0:0]$9450 end sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9369 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9370 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9371 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9372 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9373 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9374 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9375 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9376 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9377 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9378 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9379 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9380 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9381 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9382 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9383 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9384 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9385 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9386 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9417 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9418 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9419 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9420 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9421 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9422 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9423 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9424 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9425 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9426 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9427 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9428 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9429 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9430 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9431 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9432 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 end - attribute \src "libresoc.v:167504.3-167522.6" - process $proc$libresoc.v:167504$9411 + attribute \src "libresoc.v:169136.3-169154.6" + process $proc$libresoc.v:169136$9459 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$9412 $1\o$20$next[63:0]$9414 + assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 assign { } { } - assign $0\o_ok$21$next[0:0]$9413 $2\o_ok$21$next[0:0]$9416 - attribute \src "libresoc.v:167505.5-167505.29" + assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169137.5-169137.29" switch \initial - attribute \src "libresoc.v:167505.9-167505.17" + attribute \src "libresoc.v:169137.9-169137.17" case 1'1 case end @@ -345584,41 +348081,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } case - assign $1\o$20$next[63:0]$9414 \o$20 - assign $1\o_ok$21$next[0:0]$9415 \o_ok$21 + assign $1\o$20$next[63:0]$9462 \o$20 + assign $1\o_ok$21$next[0:0]$9463 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9416 1'0 + assign $2\o_ok$21$next[0:0]$9464 1'0 case - assign $2\o_ok$21$next[0:0]$9416 $1\o_ok$21$next[0:0]$9415 + assign $2\o_ok$21$next[0:0]$9464 $1\o_ok$21$next[0:0]$9463 end sync always - update \o$20$next $0\o$20$next[63:0]$9412 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9413 + update \o$20$next $0\o$20$next[63:0]$9460 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 end - attribute \src "libresoc.v:167523.3-167541.6" - process $proc$libresoc.v:167523$9417 + attribute \src "libresoc.v:169155.3-169173.6" + process $proc$libresoc.v:169155$9465 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$9418 $1\cr_a$22$next[3:0]$9420 + assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9419 $2\cr_a_ok$23$next[0:0]$9422 - attribute \src "libresoc.v:167524.5-167524.29" + assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169156.5-169156.29" switch \initial - attribute \src "libresoc.v:167524.9-167524.17" + attribute \src "libresoc.v:169156.9-169156.17" case 1'1 case end @@ -345628,41 +348125,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\cr_a$22$next[3:0]$9420 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9421 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$9468 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9469 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9422 1'0 + assign $2\cr_a_ok$23$next[0:0]$9470 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9422 $1\cr_a_ok$23$next[0:0]$9421 + assign $2\cr_a_ok$23$next[0:0]$9470 $1\cr_a_ok$23$next[0:0]$9469 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9418 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9419 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 end - attribute \src "libresoc.v:167542.3-167560.6" - process $proc$libresoc.v:167542$9423 + attribute \src "libresoc.v:169174.3-169192.6" + process $proc$libresoc.v:169174$9471 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9424 $1\xer_ca$24$next[1:0]$9426 + assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9425 $2\xer_ca_ok$25$next[0:0]$9428 - attribute \src "libresoc.v:167543.5-167543.29" + assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169175.5-169175.29" switch \initial - attribute \src "libresoc.v:167543.9-167543.17" + attribute \src "libresoc.v:169175.9-169175.17" case 1'1 case end @@ -345672,41 +348169,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\xer_ca$24$next[1:0]$9426 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9427 \xer_ca_ok$25 + assign $1\xer_ca$24$next[1:0]$9474 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9475 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9428 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9476 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9428 $1\xer_ca_ok$25$next[0:0]$9427 + assign $2\xer_ca_ok$25$next[0:0]$9476 $1\xer_ca_ok$25$next[0:0]$9475 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9424 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9425 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 end - attribute \src "libresoc.v:167561.3-167579.6" - process $proc$libresoc.v:167561$9429 + attribute \src "libresoc.v:169193.3-169211.6" + process $proc$libresoc.v:169193$9477 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9430 $1\xer_ov$26$next[1:0]$9432 + assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9431 $2\xer_ov_ok$27$next[0:0]$9434 - attribute \src "libresoc.v:167562.5-167562.29" + assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169194.5-169194.29" switch \initial - attribute \src "libresoc.v:167562.9-167562.17" + attribute \src "libresoc.v:169194.9-169194.17" case 1'1 case end @@ -345716,41 +348213,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_ov$26$next[1:0]$9432 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9433 \xer_ov_ok$27 + assign $1\xer_ov$26$next[1:0]$9480 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9481 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9434 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9482 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9434 $1\xer_ov_ok$27$next[0:0]$9433 + assign $2\xer_ov_ok$27$next[0:0]$9482 $1\xer_ov_ok$27$next[0:0]$9481 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9430 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9431 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 end - attribute \src "libresoc.v:167580.3-167598.6" - process $proc$libresoc.v:167580$9435 + attribute \src "libresoc.v:169212.3-169230.6" + process $proc$libresoc.v:169212$9483 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9436 $1\xer_so$28$next[0:0]$9438 + assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9437 $2\xer_so_ok$29$next[0:0]$9440 - attribute \src "libresoc.v:167581.5-167581.29" + assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:169213.5-169213.29" switch \initial - attribute \src "libresoc.v:167581.9-167581.17" + attribute \src "libresoc.v:169213.9-169213.17" case 1'1 case end @@ -345760,30 +348257,30 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_so$28$next[0:0]$9438 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9439 \xer_so_ok$29 + assign $1\xer_so$28$next[0:0]$9486 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9487 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9440 1'0 + assign $2\xer_so_ok$29$next[0:0]$9488 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9440 $1\xer_so_ok$29$next[0:0]$9439 + assign $2\xer_so_ok$29$next[0:0]$9488 $1\xer_so_ok$29$next[0:0]$9487 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9436 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9437 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 end - connect \$60 $and$libresoc.v:167306$9301_Y + connect \$60 $and$libresoc.v:168938$9349_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -345804,240 +348301,240 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:167622.1-168691.10" +attribute \src "libresoc.v:169254.1-170323.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:168637.3-168655.6" - wire width 4 $0\cr_a$21$next[3:0]$9606 - attribute \src "libresoc.v:168443.3-168444.33" - wire width 4 $0\cr_a$21[3:0]$9507 - attribute \src "libresoc.v:167634.13-167634.29" - wire width 4 $0\cr_a$21[3:0]$9619 - attribute \src "libresoc.v:168637.3-168655.6" - wire $0\cr_a_ok$22$next[0:0]$9607 - attribute \src "libresoc.v:168445.3-168446.39" - wire $0\cr_a_ok$22[0:0]$9509 - attribute \src "libresoc.v:167643.7-167643.26" - wire $0\cr_a_ok$22[0:0]$9621 - attribute \src "libresoc.v:167623.7-167623.20" + attribute \src "libresoc.v:170269.3-170287.6" + wire width 4 $0\cr_a$21$next[3:0]$9654 + attribute \src "libresoc.v:170075.3-170076.33" + wire width 4 $0\cr_a$21[3:0]$9555 + attribute \src "libresoc.v:169266.13-169266.29" + wire width 4 $0\cr_a$21[3:0]$9667 + attribute \src "libresoc.v:170269.3-170287.6" + wire $0\cr_a_ok$22$next[0:0]$9655 + attribute \src "libresoc.v:170077.3-170078.39" + wire $0\cr_a_ok$22[0:0]$9557 + attribute \src "libresoc.v:169275.7-169275.26" + wire $0\cr_a_ok$22[0:0]$9669 + attribute \src "libresoc.v:169255.7-169255.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168564.3-168576.6" - wire width 2 $0\muxid$1$next[1:0]$9556 - attribute \src "libresoc.v:168485.3-168486.33" - wire width 2 $0\muxid$1[1:0]$9549 - attribute \src "libresoc.v:167654.13-167654.29" - wire width 2 $0\muxid$1[1:0]$9623 - attribute \src "libresoc.v:168618.3-168636.6" - wire width 64 $0\o$19$next[63:0]$9600 - attribute \src "libresoc.v:168447.3-168448.27" - wire width 64 $0\o$19[63:0]$9511 - attribute \src "libresoc.v:167669.14-167669.43" - wire width 64 $0\o$19[63:0]$9625 - attribute \src "libresoc.v:168618.3-168636.6" - wire $0\o_ok$20$next[0:0]$9601 - attribute \src "libresoc.v:168449.3-168450.33" - wire $0\o_ok$20[0:0]$9513 - attribute \src "libresoc.v:167678.7-167678.23" - wire $0\o_ok$20[0:0]$9627 - attribute \src "libresoc.v:168546.3-168563.6" - wire $0\r_busy$next[0:0]$9552 - attribute \src "libresoc.v:168487.3-168488.29" + attribute \src "libresoc.v:170196.3-170208.6" + wire width 2 $0\muxid$1$next[1:0]$9604 + attribute \src "libresoc.v:170117.3-170118.33" + wire width 2 $0\muxid$1[1:0]$9597 + attribute \src "libresoc.v:169286.13-169286.29" + wire width 2 $0\muxid$1[1:0]$9671 + attribute \src "libresoc.v:170250.3-170268.6" + wire width 64 $0\o$19$next[63:0]$9648 + attribute \src "libresoc.v:170079.3-170080.27" + wire width 64 $0\o$19[63:0]$9559 + attribute \src "libresoc.v:169301.14-169301.43" + wire width 64 $0\o$19[63:0]$9673 + attribute \src "libresoc.v:170250.3-170268.6" + wire $0\o_ok$20$next[0:0]$9649 + attribute \src "libresoc.v:170081.3-170082.33" + wire $0\o_ok$20[0:0]$9561 + attribute \src "libresoc.v:169310.7-169310.23" + wire $0\o_ok$20[0:0]$9675 + attribute \src "libresoc.v:170178.3-170195.6" + wire $0\r_busy$next[0:0]$9600 + attribute \src "libresoc.v:170119.3-170120.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168577.3-168617.6" - wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9559 - attribute \src "libresoc.v:168453.3-168454.51" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9517 - attribute \src "libresoc.v:168011.14-168011.43" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9630 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9560 - attribute \src "libresoc.v:168455.3-168456.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9519 - attribute \src "libresoc.v:168035.14-168035.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9632 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9561 - attribute \src "libresoc.v:168457.3-168458.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9521 - attribute \src "libresoc.v:168044.7-168044.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9634 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9562 - attribute \src "libresoc.v:168471.3-168472.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9535 - attribute \src "libresoc.v:168061.13-168061.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9636 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__input_cr$14$next[0:0]$9563 - attribute \src "libresoc.v:168475.3-168476.55" - wire $0\sr_op__input_cr$14[0:0]$9539 - attribute \src "libresoc.v:168074.7-168074.34" - wire $0\sr_op__input_cr$14[0:0]$9638 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9564 - attribute \src "libresoc.v:168483.3-168484.47" - wire width 32 $0\sr_op__insn$18[31:0]$9547 - attribute \src "libresoc.v:168083.14-168083.38" - wire width 32 $0\sr_op__insn$18[31:0]$9640 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9565 - attribute \src "libresoc.v:168451.3-168452.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9515 - attribute \src "libresoc.v:168242.13-168242.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9642 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__invert_in$11$next[0:0]$9566 - attribute \src "libresoc.v:168469.3-168470.57" - wire $0\sr_op__invert_in$11[0:0]$9533 - attribute \src "libresoc.v:168326.7-168326.35" - wire $0\sr_op__invert_in$11[0:0]$9644 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9567 - attribute \src "libresoc.v:168479.3-168480.55" - wire $0\sr_op__is_32bit$16[0:0]$9543 - attribute \src "libresoc.v:168335.7-168335.34" - wire $0\sr_op__is_32bit$16[0:0]$9646 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__is_signed$17$next[0:0]$9568 - attribute \src "libresoc.v:168481.3-168482.57" - wire $0\sr_op__is_signed$17[0:0]$9545 - attribute \src "libresoc.v:168344.7-168344.35" - wire $0\sr_op__is_signed$17[0:0]$9648 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9569 - attribute \src "libresoc.v:168463.3-168464.49" - wire $0\sr_op__oe__oe$8[0:0]$9527 - attribute \src "libresoc.v:168355.7-168355.31" - wire $0\sr_op__oe__oe$8[0:0]$9650 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9570 - attribute \src "libresoc.v:168465.3-168466.49" - wire $0\sr_op__oe__ok$9[0:0]$9529 - attribute \src "libresoc.v:168364.7-168364.31" - wire $0\sr_op__oe__ok$9[0:0]$9652 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__output_carry$13$next[0:0]$9571 - attribute \src "libresoc.v:168473.3-168474.63" - wire $0\sr_op__output_carry$13[0:0]$9537 - attribute \src "libresoc.v:168371.7-168371.38" - wire $0\sr_op__output_carry$13[0:0]$9654 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__output_cr$15$next[0:0]$9572 - attribute \src "libresoc.v:168477.3-168478.57" - wire $0\sr_op__output_cr$15[0:0]$9541 - attribute \src "libresoc.v:168380.7-168380.35" - wire $0\sr_op__output_cr$15[0:0]$9656 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9573 - attribute \src "libresoc.v:168461.3-168462.49" - wire $0\sr_op__rc__ok$7[0:0]$9525 - attribute \src "libresoc.v:168391.7-168391.31" - wire $0\sr_op__rc__ok$7[0:0]$9658 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9574 - attribute \src "libresoc.v:168459.3-168460.49" - wire $0\sr_op__rc__rc$6[0:0]$9523 - attribute \src "libresoc.v:168400.7-168400.31" - wire $0\sr_op__rc__rc$6[0:0]$9660 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9575 - attribute \src "libresoc.v:168467.3-168468.57" - wire $0\sr_op__write_cr0$10[0:0]$9531 - attribute \src "libresoc.v:168407.7-168407.35" - wire $0\sr_op__write_cr0$10[0:0]$9662 - attribute \src "libresoc.v:168656.3-168674.6" - wire width 2 $0\xer_ca$23$next[1:0]$9612 - attribute \src "libresoc.v:168439.3-168440.37" - wire width 2 $0\xer_ca$23[1:0]$9503 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attribute \src "libresoc.v:170085.3-170086.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 + attribute \src "libresoc.v:169643.14-169643.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 + attribute \src "libresoc.v:170087.3-170088.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 + attribute \src "libresoc.v:169667.14-169667.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 + attribute \src "libresoc.v:170089.3-170090.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9569 + attribute \src "libresoc.v:169676.7-169676.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9682 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 + attribute \src "libresoc.v:170103.3-170104.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9583 + attribute \src "libresoc.v:169693.13-169693.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9684 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__input_cr$14$next[0:0]$9611 + attribute \src "libresoc.v:170107.3-170108.55" + wire $0\sr_op__input_cr$14[0:0]$9587 + attribute \src "libresoc.v:169706.7-169706.34" + wire $0\sr_op__input_cr$14[0:0]$9686 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9612 + attribute \src "libresoc.v:170115.3-170116.47" + wire width 32 $0\sr_op__insn$18[31:0]$9595 + attribute \src "libresoc.v:169715.14-169715.38" + wire width 32 $0\sr_op__insn$18[31:0]$9688 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9613 + attribute \src "libresoc.v:170083.3-170084.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9563 + attribute \src "libresoc.v:169874.13-169874.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9690 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__invert_in$11$next[0:0]$9614 + attribute \src "libresoc.v:170101.3-170102.57" + wire $0\sr_op__invert_in$11[0:0]$9581 + attribute \src "libresoc.v:169958.7-169958.35" + wire $0\sr_op__invert_in$11[0:0]$9692 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9615 + attribute \src "libresoc.v:170111.3-170112.55" + wire $0\sr_op__is_32bit$16[0:0]$9591 + attribute \src "libresoc.v:169967.7-169967.34" + wire $0\sr_op__is_32bit$16[0:0]$9694 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__is_signed$17$next[0:0]$9616 + attribute \src "libresoc.v:170113.3-170114.57" + wire $0\sr_op__is_signed$17[0:0]$9593 + attribute \src "libresoc.v:169976.7-169976.35" + wire $0\sr_op__is_signed$17[0:0]$9696 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9617 + attribute \src "libresoc.v:170095.3-170096.49" + wire $0\sr_op__oe__oe$8[0:0]$9575 + attribute \src "libresoc.v:169987.7-169987.31" + wire $0\sr_op__oe__oe$8[0:0]$9698 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9618 + attribute \src "libresoc.v:170097.3-170098.49" + wire $0\sr_op__oe__ok$9[0:0]$9577 + attribute \src "libresoc.v:169996.7-169996.31" + wire $0\sr_op__oe__ok$9[0:0]$9700 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__output_carry$13$next[0:0]$9619 + attribute \src "libresoc.v:170105.3-170106.63" + wire $0\sr_op__output_carry$13[0:0]$9585 + attribute \src "libresoc.v:170003.7-170003.38" + wire $0\sr_op__output_carry$13[0:0]$9702 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__output_cr$15$next[0:0]$9620 + attribute \src "libresoc.v:170109.3-170110.57" + wire $0\sr_op__output_cr$15[0:0]$9589 + attribute \src "libresoc.v:170012.7-170012.35" + wire $0\sr_op__output_cr$15[0:0]$9704 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9621 + attribute \src "libresoc.v:170093.3-170094.49" + wire $0\sr_op__rc__ok$7[0:0]$9573 + attribute \src "libresoc.v:170023.7-170023.31" + wire $0\sr_op__rc__ok$7[0:0]$9706 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9622 + attribute \src "libresoc.v:170091.3-170092.49" + wire $0\sr_op__rc__rc$6[0:0]$9571 + attribute \src "libresoc.v:170032.7-170032.31" + wire $0\sr_op__rc__rc$6[0:0]$9708 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9623 + attribute \src "libresoc.v:170099.3-170100.57" + wire $0\sr_op__write_cr0$10[0:0]$9579 + attribute \src "libresoc.v:170039.7-170039.35" + wire $0\sr_op__write_cr0$10[0:0]$9710 + attribute \src "libresoc.v:170288.3-170306.6" + wire width 2 $0\xer_ca$23$next[1:0]$9660 + attribute \src "libresoc.v:170071.3-170072.37" + wire width 2 $0\xer_ca$23[1:0]$9551 + attribute \src "libresoc.v:170048.13-170048.31" + wire width 2 $0\xer_ca$23[1:0]$9712 + attribute \src "libresoc.v:170288.3-170306.6" + wire $0\xer_ca_ok$24$next[0:0]$9661 + attribute \src "libresoc.v:170073.3-170074.43" + wire $0\xer_ca_ok$24[0:0]$9553 + attribute \src "libresoc.v:170057.7-170057.28" + wire $0\xer_ca_ok$24[0:0]$9714 + attribute \src "libresoc.v:170269.3-170287.6" + wire width 4 $1\cr_a$21$next[3:0]$9656 + attribute \src "libresoc.v:170269.3-170287.6" + wire $1\cr_a_ok$22$next[0:0]$9657 + attribute \src "libresoc.v:170196.3-170208.6" + wire width 2 $1\muxid$1$next[1:0]$9605 + attribute \src "libresoc.v:170250.3-170268.6" + wire width 64 $1\o$19$next[63:0]$9650 + attribute \src "libresoc.v:170250.3-170268.6" + wire $1\o_ok$20$next[0:0]$9651 + attribute \src "libresoc.v:170178.3-170195.6" + wire $1\r_busy$next[0:0]$9601 + attribute \src "libresoc.v:169606.7-169606.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168577.3-168617.6" - wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9576 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9577 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9578 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9579 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__input_cr$14$next[0:0]$9580 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9581 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9582 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__invert_in$11$next[0:0]$9583 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9584 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__is_signed$17$next[0:0]$9585 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9586 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9587 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__output_carry$13$next[0:0]$9588 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__output_cr$15$next[0:0]$9589 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9590 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9591 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9592 - attribute \src "libresoc.v:168656.3-168674.6" - wire width 2 $1\xer_ca$23$next[1:0]$9614 - attribute \src "libresoc.v:168656.3-168674.6" - wire $1\xer_ca_ok$24$next[0:0]$9615 - attribute \src "libresoc.v:168637.3-168655.6" - wire $2\cr_a_ok$22$next[0:0]$9610 - attribute \src "libresoc.v:168618.3-168636.6" - wire $2\o_ok$20$next[0:0]$9604 - attribute \src "libresoc.v:168546.3-168563.6" - wire $2\r_busy$next[0:0]$9554 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9593 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9594 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9595 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9596 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9597 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9598 - attribute \src "libresoc.v:168656.3-168674.6" - wire $2\xer_ca_ok$24$next[0:0]$9616 - attribute \src "libresoc.v:168438.18-168438.118" - wire $and$libresoc.v:168438$9501_Y + attribute \src "libresoc.v:170209.3-170249.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9624 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9625 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9626 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9627 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__input_cr$14$next[0:0]$9628 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9629 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9630 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__invert_in$11$next[0:0]$9631 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9632 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__is_signed$17$next[0:0]$9633 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9634 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9635 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__output_carry$13$next[0:0]$9636 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__output_cr$15$next[0:0]$9637 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9638 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9639 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9640 + attribute \src "libresoc.v:170288.3-170306.6" + wire width 2 $1\xer_ca$23$next[1:0]$9662 + attribute \src "libresoc.v:170288.3-170306.6" + wire $1\xer_ca_ok$24$next[0:0]$9663 + attribute \src "libresoc.v:170269.3-170287.6" + wire $2\cr_a_ok$22$next[0:0]$9658 + attribute \src "libresoc.v:170250.3-170268.6" + wire $2\o_ok$20$next[0:0]$9652 + attribute \src "libresoc.v:170178.3-170195.6" + wire $2\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9641 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9642 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9643 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9644 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9645 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9646 + attribute \src "libresoc.v:170288.3-170306.6" + wire $2\xer_ca_ok$24$next[0:0]$9664 + attribute \src "libresoc.v:170070.18-170070.118" + wire $and$libresoc.v:170070$9549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 24 \cr_a @@ -346057,7 +348554,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "libresoc.v:167623.7-167623.15" + attribute \src "libresoc.v:169255.7-169255.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -346826,7 +349323,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168438$9501 + cell $and $and$libresoc.v:170070$9549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -346834,16 +349331,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:168438$9501_Y + connect \Y $and$libresoc.v:170070$9549_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168489.11-168492.4" + attribute \src "libresoc.v:170121.11-170124.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:168493.16-168541.4" + attribute \src "libresoc.v:170125.16-170173.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -346894,403 +349391,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:168542.11-168545.4" + attribute \src "libresoc.v:170174.11-170177.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167623.7-167623.20" - process $proc$libresoc.v:167623$9617 + attribute \src "libresoc.v:169255.7-169255.20" + process $proc$libresoc.v:169255$9665 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167634.13-167634.29" - process $proc$libresoc.v:167634$9618 + attribute \src "libresoc.v:169266.13-169266.29" + process $proc$libresoc.v:169266$9666 assign { } { } - assign $0\cr_a$21[3:0]$9619 4'0000 + assign $0\cr_a$21[3:0]$9667 4'0000 sync always sync init - update \cr_a$21 $0\cr_a$21[3:0]$9619 + update \cr_a$21 $0\cr_a$21[3:0]$9667 end - attribute \src "libresoc.v:167643.7-167643.26" - process $proc$libresoc.v:167643$9620 + attribute \src "libresoc.v:169275.7-169275.26" + process $proc$libresoc.v:169275$9668 assign { } { } - assign $0\cr_a_ok$22[0:0]$9621 1'0 + assign $0\cr_a_ok$22[0:0]$9669 1'0 sync always sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9621 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 end - attribute \src "libresoc.v:167654.13-167654.29" - process $proc$libresoc.v:167654$9622 + attribute \src "libresoc.v:169286.13-169286.29" + process $proc$libresoc.v:169286$9670 assign { } { } - assign $0\muxid$1[1:0]$9623 2'00 + assign $0\muxid$1[1:0]$9671 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9623 + update \muxid$1 $0\muxid$1[1:0]$9671 end - attribute \src "libresoc.v:167669.14-167669.43" - process $proc$libresoc.v:167669$9624 + attribute \src "libresoc.v:169301.14-169301.43" + process $proc$libresoc.v:169301$9672 assign { } { } - assign $0\o$19[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9625 + update \o$19 $0\o$19[63:0]$9673 end - attribute \src "libresoc.v:167678.7-167678.23" - process $proc$libresoc.v:167678$9626 + attribute \src "libresoc.v:169310.7-169310.23" + process $proc$libresoc.v:169310$9674 assign { } { } - assign $0\o_ok$20[0:0]$9627 1'0 + assign $0\o_ok$20[0:0]$9675 1'0 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9627 + update \o_ok$20 $0\o_ok$20[0:0]$9675 end - attribute \src "libresoc.v:167974.7-167974.20" - process $proc$libresoc.v:167974$9628 + attribute \src "libresoc.v:169606.7-169606.20" + process $proc$libresoc.v:169606$9676 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168011.14-168011.43" - process $proc$libresoc.v:168011$9629 + attribute \src "libresoc.v:169643.14-169643.43" + process $proc$libresoc.v:169643$9677 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9630 14'00000000000000 + assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9630 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 end - attribute \src "libresoc.v:168035.14-168035.62" - process $proc$libresoc.v:168035$9631 + attribute \src "libresoc.v:169667.14-169667.62" + process $proc$libresoc.v:169667$9679 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9632 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9632 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 end - attribute \src "libresoc.v:168044.7-168044.37" - process $proc$libresoc.v:168044$9633 + attribute \src "libresoc.v:169676.7-169676.37" + process $proc$libresoc.v:169676$9681 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9634 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9634 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 end - attribute \src "libresoc.v:168061.13-168061.43" - process $proc$libresoc.v:168061$9635 + attribute \src "libresoc.v:169693.13-169693.43" + process $proc$libresoc.v:169693$9683 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9636 2'00 + assign $0\sr_op__input_carry$12[1:0]$9684 2'00 sync always sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9636 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 end - attribute \src "libresoc.v:168074.7-168074.34" - process $proc$libresoc.v:168074$9637 + attribute \src "libresoc.v:169706.7-169706.34" + process $proc$libresoc.v:169706$9685 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9638 1'0 + assign $0\sr_op__input_cr$14[0:0]$9686 1'0 sync always sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9638 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 end - attribute \src "libresoc.v:168083.14-168083.38" - process $proc$libresoc.v:168083$9639 + attribute \src "libresoc.v:169715.14-169715.38" + process $proc$libresoc.v:169715$9687 assign { } { } - assign $0\sr_op__insn$18[31:0]$9640 0 + assign $0\sr_op__insn$18[31:0]$9688 0 sync always sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9640 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 end - attribute \src "libresoc.v:168242.13-168242.41" - process $proc$libresoc.v:168242$9641 + attribute \src "libresoc.v:169874.13-169874.41" + process $proc$libresoc.v:169874$9689 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9642 7'0000000 + assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9642 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 end - attribute \src "libresoc.v:168326.7-168326.35" - process $proc$libresoc.v:168326$9643 + attribute \src "libresoc.v:169958.7-169958.35" + process $proc$libresoc.v:169958$9691 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9644 1'0 + assign $0\sr_op__invert_in$11[0:0]$9692 1'0 sync always sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9644 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 end - attribute \src "libresoc.v:168335.7-168335.34" - process $proc$libresoc.v:168335$9645 + attribute \src "libresoc.v:169967.7-169967.34" + process $proc$libresoc.v:169967$9693 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9646 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9646 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 end - attribute \src "libresoc.v:168344.7-168344.35" - process $proc$libresoc.v:168344$9647 + attribute \src "libresoc.v:169976.7-169976.35" + process $proc$libresoc.v:169976$9695 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9648 1'0 + assign $0\sr_op__is_signed$17[0:0]$9696 1'0 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9648 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 end - attribute \src "libresoc.v:168355.7-168355.31" - process $proc$libresoc.v:168355$9649 + attribute \src "libresoc.v:169987.7-169987.31" + process $proc$libresoc.v:169987$9697 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9650 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9650 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 end - attribute \src "libresoc.v:168364.7-168364.31" - process $proc$libresoc.v:168364$9651 + attribute \src "libresoc.v:169996.7-169996.31" + process $proc$libresoc.v:169996$9699 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9652 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9652 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 end - attribute \src "libresoc.v:168371.7-168371.38" - process $proc$libresoc.v:168371$9653 + attribute \src "libresoc.v:170003.7-170003.38" + process $proc$libresoc.v:170003$9701 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9654 1'0 + assign $0\sr_op__output_carry$13[0:0]$9702 1'0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9654 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 end - attribute \src "libresoc.v:168380.7-168380.35" - process $proc$libresoc.v:168380$9655 + attribute \src "libresoc.v:170012.7-170012.35" + process $proc$libresoc.v:170012$9703 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9656 1'0 + assign $0\sr_op__output_cr$15[0:0]$9704 1'0 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9656 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 end - attribute \src "libresoc.v:168391.7-168391.31" - process $proc$libresoc.v:168391$9657 + attribute \src "libresoc.v:170023.7-170023.31" + process $proc$libresoc.v:170023$9705 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9658 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9658 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 end - attribute \src "libresoc.v:168400.7-168400.31" - process $proc$libresoc.v:168400$9659 + attribute \src "libresoc.v:170032.7-170032.31" + process $proc$libresoc.v:170032$9707 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9660 1'0 + assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9660 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 end - attribute \src "libresoc.v:168407.7-168407.35" - process $proc$libresoc.v:168407$9661 + attribute \src "libresoc.v:170039.7-170039.35" + process $proc$libresoc.v:170039$9709 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9662 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9662 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 end - attribute \src "libresoc.v:168416.13-168416.31" - process $proc$libresoc.v:168416$9663 + attribute \src "libresoc.v:170048.13-170048.31" + process $proc$libresoc.v:170048$9711 assign { } { } - assign $0\xer_ca$23[1:0]$9664 2'00 + assign $0\xer_ca$23[1:0]$9712 2'00 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9664 + update \xer_ca$23 $0\xer_ca$23[1:0]$9712 end - attribute \src "libresoc.v:168425.7-168425.28" - process $proc$libresoc.v:168425$9665 + attribute \src "libresoc.v:170057.7-170057.28" + process $proc$libresoc.v:170057$9713 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9666 1'0 + assign $0\xer_ca_ok$24[0:0]$9714 1'0 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9666 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 end - attribute \src "libresoc.v:168439.3-168440.37" - process $proc$libresoc.v:168439$9502 + attribute \src "libresoc.v:170071.3-170072.37" + process $proc$libresoc.v:170071$9550 assign { } { } - assign $0\xer_ca$23[1:0]$9503 \xer_ca$23$next + assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9503 + update \xer_ca$23 $0\xer_ca$23[1:0]$9551 end - attribute \src "libresoc.v:168441.3-168442.43" - process $proc$libresoc.v:168441$9504 + attribute \src "libresoc.v:170073.3-170074.43" + process $proc$libresoc.v:170073$9552 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9505 \xer_ca_ok$24$next + assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9505 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 end - attribute \src "libresoc.v:168443.3-168444.33" - process $proc$libresoc.v:168443$9506 + attribute \src "libresoc.v:170075.3-170076.33" + process $proc$libresoc.v:170075$9554 assign { } { } - assign $0\cr_a$21[3:0]$9507 \cr_a$21$next + assign $0\cr_a$21[3:0]$9555 \cr_a$21$next sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9507 + update \cr_a$21 $0\cr_a$21[3:0]$9555 end - attribute \src "libresoc.v:168445.3-168446.39" - process $proc$libresoc.v:168445$9508 + attribute \src "libresoc.v:170077.3-170078.39" + process $proc$libresoc.v:170077$9556 assign { } { } - assign $0\cr_a_ok$22[0:0]$9509 \cr_a_ok$22$next + assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9509 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 end - attribute \src "libresoc.v:168447.3-168448.27" - process $proc$libresoc.v:168447$9510 + attribute \src "libresoc.v:170079.3-170080.27" + process $proc$libresoc.v:170079$9558 assign { } { } - assign $0\o$19[63:0]$9511 \o$19$next + assign $0\o$19[63:0]$9559 \o$19$next sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9511 + update \o$19 $0\o$19[63:0]$9559 end - attribute \src "libresoc.v:168449.3-168450.33" - process $proc$libresoc.v:168449$9512 + attribute \src "libresoc.v:170081.3-170082.33" + process $proc$libresoc.v:170081$9560 assign { } { } - assign $0\o_ok$20[0:0]$9513 \o_ok$20$next + assign $0\o_ok$20[0:0]$9561 \o_ok$20$next sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9513 + update \o_ok$20 $0\o_ok$20[0:0]$9561 end - attribute \src "libresoc.v:168451.3-168452.55" - process $proc$libresoc.v:168451$9514 + attribute \src "libresoc.v:170083.3-170084.55" + process $proc$libresoc.v:170083$9562 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9515 \sr_op__insn_type$2$next + assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9515 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 end - attribute \src "libresoc.v:168453.3-168454.51" - process $proc$libresoc.v:168453$9516 + attribute \src "libresoc.v:170085.3-170086.51" + process $proc$libresoc.v:170085$9564 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9517 \sr_op__fn_unit$3$next + assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9517 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 end - attribute \src "libresoc.v:168455.3-168456.65" - process $proc$libresoc.v:168455$9518 + attribute \src "libresoc.v:170087.3-170088.65" + process $proc$libresoc.v:170087$9566 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9519 \sr_op__imm_data__data$4$next + assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9519 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 end - attribute \src "libresoc.v:168457.3-168458.61" - process $proc$libresoc.v:168457$9520 + attribute \src "libresoc.v:170089.3-170090.61" + process $proc$libresoc.v:170089$9568 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9521 \sr_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9521 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 end - attribute \src "libresoc.v:168459.3-168460.49" - process $proc$libresoc.v:168459$9522 + attribute \src "libresoc.v:170091.3-170092.49" + process $proc$libresoc.v:170091$9570 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9523 \sr_op__rc__rc$6$next + assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9523 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 end - attribute \src "libresoc.v:168461.3-168462.49" - process $proc$libresoc.v:168461$9524 + attribute \src "libresoc.v:170093.3-170094.49" + process $proc$libresoc.v:170093$9572 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9525 \sr_op__rc__ok$7$next + assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9525 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 end - attribute \src "libresoc.v:168463.3-168464.49" - process $proc$libresoc.v:168463$9526 + attribute \src "libresoc.v:170095.3-170096.49" + process $proc$libresoc.v:170095$9574 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9527 \sr_op__oe__oe$8$next + assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9527 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 end - attribute \src "libresoc.v:168465.3-168466.49" - process $proc$libresoc.v:168465$9528 + attribute \src "libresoc.v:170097.3-170098.49" + process $proc$libresoc.v:170097$9576 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9529 \sr_op__oe__ok$9$next + assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9529 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 end - attribute \src "libresoc.v:168467.3-168468.57" - process $proc$libresoc.v:168467$9530 + attribute \src "libresoc.v:170099.3-170100.57" + process $proc$libresoc.v:170099$9578 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9531 \sr_op__write_cr0$10$next + assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9531 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 end - attribute \src "libresoc.v:168469.3-168470.57" - process $proc$libresoc.v:168469$9532 + attribute \src "libresoc.v:170101.3-170102.57" + process $proc$libresoc.v:170101$9580 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9533 \sr_op__invert_in$11$next + assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9533 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 end - attribute \src "libresoc.v:168471.3-168472.61" - process $proc$libresoc.v:168471$9534 + attribute \src "libresoc.v:170103.3-170104.61" + process $proc$libresoc.v:170103$9582 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9535 \sr_op__input_carry$12$next + assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9535 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 end - attribute \src "libresoc.v:168473.3-168474.63" - process $proc$libresoc.v:168473$9536 + attribute \src "libresoc.v:170105.3-170106.63" + process $proc$libresoc.v:170105$9584 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9537 \sr_op__output_carry$13$next + assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9537 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 end - attribute \src "libresoc.v:168475.3-168476.55" - process $proc$libresoc.v:168475$9538 + attribute \src "libresoc.v:170107.3-170108.55" + process $proc$libresoc.v:170107$9586 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9539 \sr_op__input_cr$14$next + assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9539 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 end - attribute \src "libresoc.v:168477.3-168478.57" - process $proc$libresoc.v:168477$9540 + attribute \src "libresoc.v:170109.3-170110.57" + process $proc$libresoc.v:170109$9588 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9541 \sr_op__output_cr$15$next + assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9541 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 end - attribute \src "libresoc.v:168479.3-168480.55" - process $proc$libresoc.v:168479$9542 + attribute \src "libresoc.v:170111.3-170112.55" + process $proc$libresoc.v:170111$9590 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9543 \sr_op__is_32bit$16$next + assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9543 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 end - attribute \src "libresoc.v:168481.3-168482.57" - process $proc$libresoc.v:168481$9544 + attribute \src "libresoc.v:170113.3-170114.57" + process $proc$libresoc.v:170113$9592 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9545 \sr_op__is_signed$17$next + assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9545 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 end - attribute \src "libresoc.v:168483.3-168484.47" - process $proc$libresoc.v:168483$9546 + attribute \src "libresoc.v:170115.3-170116.47" + process $proc$libresoc.v:170115$9594 assign { } { } - assign $0\sr_op__insn$18[31:0]$9547 \sr_op__insn$18$next + assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9547 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 end - attribute \src "libresoc.v:168485.3-168486.33" - process $proc$libresoc.v:168485$9548 + attribute \src "libresoc.v:170117.3-170118.33" + process $proc$libresoc.v:170117$9596 assign { } { } - assign $0\muxid$1[1:0]$9549 \muxid$1$next + assign $0\muxid$1[1:0]$9597 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9549 + update \muxid$1 $0\muxid$1[1:0]$9597 end - attribute \src "libresoc.v:168487.3-168488.29" - process $proc$libresoc.v:168487$9550 + attribute \src "libresoc.v:170119.3-170120.29" + process $proc$libresoc.v:170119$9598 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168546.3-168563.6" - process $proc$libresoc.v:168546$9551 + attribute \src "libresoc.v:170178.3-170195.6" + process $proc$libresoc.v:170178$9599 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9552 $2\r_busy$next[0:0]$9554 - attribute \src "libresoc.v:168547.5-168547.29" + assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:170179.5-170179.29" switch \initial - attribute \src "libresoc.v:168547.9-168547.17" + attribute \src "libresoc.v:170179.9-170179.17" case 1'1 case end @@ -347299,34 +349796,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9553 1'1 + assign $1\r_busy$next[0:0]$9601 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9553 1'0 + assign $1\r_busy$next[0:0]$9601 1'0 case - assign $1\r_busy$next[0:0]$9553 \r_busy + assign $1\r_busy$next[0:0]$9601 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9554 1'0 + assign $2\r_busy$next[0:0]$9602 1'0 case - assign $2\r_busy$next[0:0]$9554 $1\r_busy$next[0:0]$9553 + assign $2\r_busy$next[0:0]$9602 $1\r_busy$next[0:0]$9601 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9552 + update \r_busy$next $0\r_busy$next[0:0]$9600 end - attribute \src "libresoc.v:168564.3-168576.6" - process $proc$libresoc.v:168564$9555 + attribute \src "libresoc.v:170196.3-170208.6" + process $proc$libresoc.v:170196$9603 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9556 $1\muxid$1$next[1:0]$9557 - attribute \src "libresoc.v:168565.5-168565.29" + assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 + attribute \src "libresoc.v:170197.5-170197.29" switch \initial - attribute \src "libresoc.v:168565.9-168565.17" + attribute \src "libresoc.v:170197.9-170197.17" case 1'1 case end @@ -347335,19 +349832,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9557 \muxid$53 + assign $1\muxid$1$next[1:0]$9605 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9557 \muxid$53 + assign $1\muxid$1$next[1:0]$9605 \muxid$53 case - assign $1\muxid$1$next[1:0]$9557 \muxid$1 + assign $1\muxid$1$next[1:0]$9605 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9556 + update \muxid$1$next $0\muxid$1$next[1:0]$9604 end - attribute \src "libresoc.v:168577.3-168617.6" - process $proc$libresoc.v:168577$9558 + attribute \src "libresoc.v:170209.3-170249.6" + process $proc$libresoc.v:170209$9606 assign { } { } assign { } { } assign { } { } @@ -347382,32 +349879,32 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[13:0]$9559 $1\sr_op__fn_unit$3$next[13:0]$9576 + assign $0\sr_op__fn_unit$3$next[13:0]$9607 $1\sr_op__fn_unit$3$next[13:0]$9624 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9562 $1\sr_op__input_carry$12$next[1:0]$9579 - assign $0\sr_op__input_cr$14$next[0:0]$9563 $1\sr_op__input_cr$14$next[0:0]$9580 - assign $0\sr_op__insn$18$next[31:0]$9564 $1\sr_op__insn$18$next[31:0]$9581 - assign $0\sr_op__insn_type$2$next[6:0]$9565 $1\sr_op__insn_type$2$next[6:0]$9582 - assign $0\sr_op__invert_in$11$next[0:0]$9566 $1\sr_op__invert_in$11$next[0:0]$9583 - assign $0\sr_op__is_32bit$16$next[0:0]$9567 $1\sr_op__is_32bit$16$next[0:0]$9584 - assign $0\sr_op__is_signed$17$next[0:0]$9568 $1\sr_op__is_signed$17$next[0:0]$9585 + assign $0\sr_op__input_carry$12$next[1:0]$9610 $1\sr_op__input_carry$12$next[1:0]$9627 + assign $0\sr_op__input_cr$14$next[0:0]$9611 $1\sr_op__input_cr$14$next[0:0]$9628 + assign $0\sr_op__insn$18$next[31:0]$9612 $1\sr_op__insn$18$next[31:0]$9629 + assign $0\sr_op__insn_type$2$next[6:0]$9613 $1\sr_op__insn_type$2$next[6:0]$9630 + assign $0\sr_op__invert_in$11$next[0:0]$9614 $1\sr_op__invert_in$11$next[0:0]$9631 + assign $0\sr_op__is_32bit$16$next[0:0]$9615 $1\sr_op__is_32bit$16$next[0:0]$9632 + assign $0\sr_op__is_signed$17$next[0:0]$9616 $1\sr_op__is_signed$17$next[0:0]$9633 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9571 $1\sr_op__output_carry$13$next[0:0]$9588 - assign $0\sr_op__output_cr$15$next[0:0]$9572 $1\sr_op__output_cr$15$next[0:0]$9589 + assign $0\sr_op__output_carry$13$next[0:0]$9619 $1\sr_op__output_carry$13$next[0:0]$9636 + assign $0\sr_op__output_cr$15$next[0:0]$9620 $1\sr_op__output_cr$15$next[0:0]$9637 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9575 $1\sr_op__write_cr0$10$next[0:0]$9592 - assign $0\sr_op__imm_data__data$4$next[63:0]$9560 $2\sr_op__imm_data__data$4$next[63:0]$9593 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9561 $2\sr_op__imm_data__ok$5$next[0:0]$9594 - assign $0\sr_op__oe__oe$8$next[0:0]$9569 $2\sr_op__oe__oe$8$next[0:0]$9595 - assign $0\sr_op__oe__ok$9$next[0:0]$9570 $2\sr_op__oe__ok$9$next[0:0]$9596 - assign $0\sr_op__rc__ok$7$next[0:0]$9573 $2\sr_op__rc__ok$7$next[0:0]$9597 - assign $0\sr_op__rc__rc$6$next[0:0]$9574 $2\sr_op__rc__rc$6$next[0:0]$9598 - attribute \src "libresoc.v:168578.5-168578.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9623 $1\sr_op__write_cr0$10$next[0:0]$9640 + assign $0\sr_op__imm_data__data$4$next[63:0]$9608 $2\sr_op__imm_data__data$4$next[63:0]$9641 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9609 $2\sr_op__imm_data__ok$5$next[0:0]$9642 + assign $0\sr_op__oe__oe$8$next[0:0]$9617 $2\sr_op__oe__oe$8$next[0:0]$9643 + assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 + assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 + assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 + attribute \src "libresoc.v:170210.5-170210.29" switch \initial - attribute \src "libresoc.v:168578.9-168578.17" + attribute \src "libresoc.v:170210.9-170210.17" case 1'1 case end @@ -347432,7 +349929,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -347452,25 +349949,25 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\sr_op__fn_unit$3$next[13:0]$9576 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9577 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9578 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9579 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9580 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9581 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9582 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9583 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9584 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9585 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9586 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9587 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9588 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9589 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9590 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9591 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9592 \sr_op__write_cr0$10 + assign $1\sr_op__fn_unit$3$next[13:0]$9624 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9625 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9626 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9627 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9628 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9629 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9630 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9631 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9632 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9633 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9634 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9635 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9636 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9637 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9638 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9639 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9640 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -347482,51 +349979,51 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9593 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9598 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9597 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9595 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9596 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9593 $1\sr_op__imm_data__data$4$next[63:0]$9577 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 $1\sr_op__imm_data__ok$5$next[0:0]$9578 - assign $2\sr_op__oe__oe$8$next[0:0]$9595 $1\sr_op__oe__oe$8$next[0:0]$9586 - assign $2\sr_op__oe__ok$9$next[0:0]$9596 $1\sr_op__oe__ok$9$next[0:0]$9587 - assign $2\sr_op__rc__ok$7$next[0:0]$9597 $1\sr_op__rc__ok$7$next[0:0]$9590 - assign $2\sr_op__rc__rc$6$next[0:0]$9598 $1\sr_op__rc__rc$6$next[0:0]$9591 + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 $1\sr_op__imm_data__data$4$next[63:0]$9625 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 $1\sr_op__imm_data__ok$5$next[0:0]$9626 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 $1\sr_op__oe__oe$8$next[0:0]$9634 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 $1\sr_op__oe__ok$9$next[0:0]$9635 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 $1\sr_op__rc__ok$7$next[0:0]$9638 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 $1\sr_op__rc__rc$6$next[0:0]$9639 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9559 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9560 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9561 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9562 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9563 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9564 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9565 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9566 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9567 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9568 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9569 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9570 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9571 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9572 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9573 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9574 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9575 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9607 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9608 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9609 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9610 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9611 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9612 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9613 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9614 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9615 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9616 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9617 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9618 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9619 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9620 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9621 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 end - attribute \src "libresoc.v:168618.3-168636.6" - process $proc$libresoc.v:168618$9599 + attribute \src "libresoc.v:170250.3-170268.6" + process $proc$libresoc.v:170250$9647 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$19$next[63:0]$9600 $1\o$19$next[63:0]$9602 + assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 assign { } { } - assign $0\o_ok$20$next[0:0]$9601 $2\o_ok$20$next[0:0]$9604 - attribute \src "libresoc.v:168619.5-168619.29" + assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 + attribute \src "libresoc.v:170251.5-170251.29" switch \initial - attribute \src "libresoc.v:168619.9-168619.17" + attribute \src "libresoc.v:170251.9-170251.17" case 1'1 case end @@ -347536,41 +350033,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } case - assign $1\o$19$next[63:0]$9602 \o$19 - assign $1\o_ok$20$next[0:0]$9603 \o_ok$20 + assign $1\o$19$next[63:0]$9650 \o$19 + assign $1\o_ok$20$next[0:0]$9651 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$20$next[0:0]$9604 1'0 + assign $2\o_ok$20$next[0:0]$9652 1'0 case - assign $2\o_ok$20$next[0:0]$9604 $1\o_ok$20$next[0:0]$9603 + assign $2\o_ok$20$next[0:0]$9652 $1\o_ok$20$next[0:0]$9651 end sync always - update \o$19$next $0\o$19$next[63:0]$9600 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9601 + update \o$19$next $0\o$19$next[63:0]$9648 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 end - attribute \src "libresoc.v:168637.3-168655.6" - process $proc$libresoc.v:168637$9605 + attribute \src "libresoc.v:170269.3-170287.6" + process $proc$libresoc.v:170269$9653 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$21$next[3:0]$9606 $1\cr_a$21$next[3:0]$9608 + assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9607 $2\cr_a_ok$22$next[0:0]$9610 - attribute \src "libresoc.v:168638.5-168638.29" + assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 + attribute \src "libresoc.v:170270.5-170270.29" switch \initial - attribute \src "libresoc.v:168638.9-168638.17" + attribute \src "libresoc.v:170270.9-170270.17" case 1'1 case end @@ -347580,41 +350077,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$21$next[3:0]$9608 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9609 \cr_a_ok$22 + assign $1\cr_a$21$next[3:0]$9656 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9657 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9610 1'0 + assign $2\cr_a_ok$22$next[0:0]$9658 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9610 $1\cr_a_ok$22$next[0:0]$9609 + assign $2\cr_a_ok$22$next[0:0]$9658 $1\cr_a_ok$22$next[0:0]$9657 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9606 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9607 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 end - attribute \src "libresoc.v:168656.3-168674.6" - process $proc$libresoc.v:168656$9611 + attribute \src "libresoc.v:170288.3-170306.6" + process $proc$libresoc.v:170288$9659 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$23$next[1:0]$9612 $1\xer_ca$23$next[1:0]$9614 + assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9613 $2\xer_ca_ok$24$next[0:0]$9616 - attribute \src "libresoc.v:168657.5-168657.29" + assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 + attribute \src "libresoc.v:170289.5-170289.29" switch \initial - attribute \src "libresoc.v:168657.9-168657.17" + attribute \src "libresoc.v:170289.9-170289.17" case 1'1 case end @@ -347624,30 +350121,30 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_ca$23$next[1:0]$9614 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9615 \xer_ca_ok$24 + assign $1\xer_ca$23$next[1:0]$9662 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9663 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9616 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9664 1'0 case - assign $2\xer_ca_ok$24$next[0:0]$9616 $1\xer_ca_ok$24$next[0:0]$9615 + assign $2\xer_ca_ok$24$next[0:0]$9664 $1\xer_ca_ok$24$next[0:0]$9663 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9612 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9613 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 end - connect \$51 $and$libresoc.v:168438$9501_Y + connect \$51 $and$libresoc.v:170070$9549_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -347665,200 +350162,200 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:168695.1-169659.10" +attribute \src "libresoc.v:170327.1-171291.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:169565.3-169583.6" - wire width 64 $0\fast1$11$next[63:0]$9735 - attribute \src "libresoc.v:169414.3-169415.35" - wire width 64 $0\fast1$11[63:0]$9673 - attribute \src "libresoc.v:168707.14-168707.47" - wire width 64 $0\fast1$11[63:0]$9759 - attribute \src "libresoc.v:169565.3-169583.6" - wire $0\fast1_ok$next[0:0]$9734 - attribute \src "libresoc.v:169416.3-169417.33" + attribute \src "libresoc.v:171197.3-171215.6" + wire width 64 $0\fast1$11$next[63:0]$9783 + attribute \src "libresoc.v:171052.3-171053.35" + wire width 64 $0\fast1$11[63:0]$9724 + attribute \src "libresoc.v:170339.14-170339.47" + wire width 64 $0\fast1$11[63:0]$9807 + attribute \src "libresoc.v:171197.3-171215.6" + wire $0\fast1_ok$next[0:0]$9782 + attribute \src "libresoc.v:171054.3-171055.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:169584.3-169602.6" - wire width 64 $0\fast2$12$next[63:0]$9741 - attribute \src "libresoc.v:169410.3-169411.35" - wire width 64 $0\fast2$12[63:0]$9670 - attribute \src "libresoc.v:168723.14-168723.47" - wire width 64 $0\fast2$12[63:0]$9762 - attribute \src "libresoc.v:169584.3-169602.6" - wire $0\fast2_ok$next[0:0]$9740 - attribute \src "libresoc.v:169412.3-169413.33" + attribute \src "libresoc.v:171216.3-171234.6" + wire width 64 $0\fast2$12$next[63:0]$9789 + attribute \src "libresoc.v:171048.3-171049.35" + wire width 64 $0\fast2$12[63:0]$9721 + attribute \src "libresoc.v:170355.14-170355.47" + wire width 64 $0\fast2$12[63:0]$9810 + attribute \src "libresoc.v:171216.3-171234.6" + wire $0\fast2_ok$next[0:0]$9788 + attribute \src "libresoc.v:171050.3-171051.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:168696.7-168696.20" + attribute \src "libresoc.v:170328.7-170328.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169622.3-169640.6" - wire width 64 $0\msr$next[63:0]$9752 - attribute \src "libresoc.v:169444.3-169445.23" + attribute \src "libresoc.v:171254.3-171272.6" + wire width 64 $0\msr$next[63:0]$9800 + attribute \src "libresoc.v:171040.3-171041.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:169622.3-169640.6" - wire $0\msr_ok$next[0:0]$9753 - attribute \src "libresoc.v:169446.3-169447.29" + attribute \src "libresoc.v:171254.3-171272.6" + wire $0\msr_ok$next[0:0]$9801 + attribute \src "libresoc.v:171042.3-171043.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:169512.3-169524.6" - wire width 2 $0\muxid$1$next[1:0]$9706 - attribute \src "libresoc.v:169440.3-169441.33" - wire width 2 $0\muxid$1[1:0]$9696 - attribute \src "libresoc.v:169001.13-169001.29" - wire width 2 $0\muxid$1[1:0]$9767 - attribute \src "libresoc.v:169603.3-169621.6" - wire width 64 $0\nia$next[63:0]$9746 - attribute \src "libresoc.v:169448.3-169449.23" + attribute \src "libresoc.v:171144.3-171156.6" + wire width 2 $0\muxid$1$next[1:0]$9754 + attribute \src "libresoc.v:171078.3-171079.33" + wire width 2 $0\muxid$1[1:0]$9747 + attribute \src "libresoc.v:170633.13-170633.29" + wire width 2 $0\muxid$1[1:0]$9815 + attribute \src "libresoc.v:171235.3-171253.6" + wire width 64 $0\nia$next[63:0]$9794 + attribute \src "libresoc.v:171044.3-171045.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:169603.3-169621.6" - wire $0\nia_ok$next[0:0]$9747 - attribute \src "libresoc.v:169408.3-169409.29" + attribute \src "libresoc.v:171235.3-171253.6" + wire $0\nia_ok$next[0:0]$9795 + attribute \src "libresoc.v:171046.3-171047.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:169546.3-169564.6" - wire width 64 $0\o$next[63:0]$9728 - attribute \src "libresoc.v:169418.3-169419.19" + attribute \src "libresoc.v:171178.3-171196.6" + wire width 64 $0\o$next[63:0]$9776 + attribute \src "libresoc.v:171056.3-171057.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:169546.3-169564.6" - wire $0\o_ok$next[0:0]$9729 - attribute \src "libresoc.v:169420.3-169421.25" + attribute \src "libresoc.v:171178.3-171196.6" + wire $0\o_ok$next[0:0]$9777 + attribute \src "libresoc.v:171058.3-171059.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:169494.3-169511.6" - wire $0\r_busy$next[0:0]$9702 - attribute \src "libresoc.v:169442.3-169443.29" + attribute \src "libresoc.v:171126.3-171143.6" + wire $0\r_busy$next[0:0]$9750 + attribute \src "libresoc.v:171080.3-171081.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169525.3-169545.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9709 - attribute \src "libresoc.v:169430.3-169431.47" - wire width 64 $0\trap_op__cia$6[63:0]$9686 - attribute \src "libresoc.v:169062.14-169062.53" - wire width 64 $0\trap_op__cia$6[63:0]$9774 - attribute \src "libresoc.v:169525.3-169545.6" - wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9710 - attribute \src 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$0\trap_op__traptype$8$next[7:0]$9717 - attribute \src "libresoc.v:169434.3-169435.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9690 - attribute \src "libresoc.v:169404.13-169404.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9790 - attribute \src "libresoc.v:169565.3-169583.6" - wire width 64 $1\fast1$11$next[63:0]$9737 - attribute \src "libresoc.v:169565.3-169583.6" - wire $1\fast1_ok$next[0:0]$9736 - attribute \src "libresoc.v:168714.7-168714.22" + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9757 + attribute \src "libresoc.v:171068.3-171069.47" + wire width 64 $0\trap_op__cia$6[63:0]$9737 + attribute \src "libresoc.v:170694.14-170694.53" + wire width 64 $0\trap_op__cia$6[63:0]$9822 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 + attribute \src "libresoc.v:171062.3-171063.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 + attribute \src "libresoc.v:170731.14-170731.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9759 + attribute \src "libresoc.v:171064.3-171065.49" + wire width 32 $0\trap_op__insn$4[31:0]$9733 + attribute \src "libresoc.v:170757.14-170757.39" + wire width 32 $0\trap_op__insn$4[31:0]$9826 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 + attribute \src "libresoc.v:171060.3-171061.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9729 + attribute \src "libresoc.v:170914.13-170914.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9828 + attribute \src "libresoc.v:171157.3-171177.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9761 + attribute \src "libresoc.v:171070.3-171071.57" + wire $0\trap_op__is_32bit$7[0:0]$9739 + attribute \src "libresoc.v:171000.7-171000.35" + wire $0\trap_op__is_32bit$7[0:0]$9830 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9762 + attribute \src "libresoc.v:171076.3-171077.59" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9745 + attribute \src "libresoc.v:171007.13-171007.43" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9832 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$9763 + attribute \src "libresoc.v:171066.3-171067.47" + wire width 64 $0\trap_op__msr$5[63:0]$9735 + attribute \src "libresoc.v:171018.14-171018.53" + wire width 64 $0\trap_op__msr$5[63:0]$9834 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9764 + attribute \src "libresoc.v:171074.3-171075.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 + attribute \src "libresoc.v:171027.14-171027.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9836 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $0\trap_op__traptype$8$next[7:0]$9765 + attribute \src "libresoc.v:171072.3-171073.57" + wire width 8 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wire $2\fast1_ok$next[0:0]$9738 - attribute \src "libresoc.v:169584.3-169602.6" - wire $2\fast2_ok$next[0:0]$9744 - attribute \src "libresoc.v:169622.3-169640.6" - wire $2\msr_ok$next[0:0]$9756 - attribute \src "libresoc.v:169603.3-169621.6" - wire $2\nia_ok$next[0:0]$9750 - attribute \src "libresoc.v:169546.3-169564.6" - wire $2\o_ok$next[0:0]$9732 - attribute \src "libresoc.v:169494.3-169511.6" - wire $2\r_busy$next[0:0]$9704 - attribute \src "libresoc.v:169407.18-169407.118" - wire $and$libresoc.v:169407$9667_Y + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$9766 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9767 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$9768 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$9769 + attribute \src "libresoc.v:171157.3-171177.6" + wire $1\trap_op__is_32bit$7$next[0:0]$9770 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9771 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$9772 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9773 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $1\trap_op__traptype$8$next[7:0]$9774 + attribute \src "libresoc.v:171197.3-171215.6" + wire $2\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:171216.3-171234.6" + wire $2\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:171254.3-171272.6" + wire $2\msr_ok$next[0:0]$9804 + attribute \src "libresoc.v:171235.3-171253.6" + wire $2\nia_ok$next[0:0]$9798 + attribute \src "libresoc.v:171178.3-171196.6" + wire $2\o_ok$next[0:0]$9780 + attribute \src "libresoc.v:171126.3-171143.6" + wire $2\r_busy$next[0:0]$9752 + attribute \src "libresoc.v:171039.18-171039.118" + wire $and$libresoc.v:171039$9715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 @@ -347888,7 +350385,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:168696.7-168696.15" + attribute \src "libresoc.v:170328.7-170328.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -348547,7 +351044,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:169407$9667 + cell $and $and$libresoc.v:171039$9715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348555,10 +351052,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:169407$9667_Y + connect \Y $and$libresoc.v:171039$9715_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:169450.13-169485.4" + attribute \src "libresoc.v:171082.13-171117.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -348596,349 +351093,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:169486.10-169489.4" + attribute \src "libresoc.v:171118.10-171121.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169490.10-169493.4" + attribute \src "libresoc.v:171122.10-171125.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168696.7-168696.20" - process $proc$libresoc.v:168696$9757 + attribute \src "libresoc.v:170328.7-170328.20" + process $proc$libresoc.v:170328$9805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168707.14-168707.47" - process $proc$libresoc.v:168707$9758 + attribute \src "libresoc.v:170339.14-170339.47" + process $proc$libresoc.v:170339$9806 assign { } { } - assign $0\fast1$11[63:0]$9759 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9759 + update \fast1$11 $0\fast1$11[63:0]$9807 end - attribute \src "libresoc.v:168714.7-168714.22" - process $proc$libresoc.v:168714$9760 + attribute \src "libresoc.v:170346.7-170346.22" + process $proc$libresoc.v:170346$9808 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:168723.14-168723.47" - process $proc$libresoc.v:168723$9761 + attribute \src "libresoc.v:170355.14-170355.47" + process $proc$libresoc.v:170355$9809 assign { } { } - assign $0\fast2$12[63:0]$9762 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9762 + update \fast2$12 $0\fast2$12[63:0]$9810 end - attribute \src "libresoc.v:168730.7-168730.22" - process $proc$libresoc.v:168730$9763 + attribute \src "libresoc.v:170362.7-170362.22" + process $proc$libresoc.v:170362$9811 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:168985.14-168985.40" - process $proc$libresoc.v:168985$9764 + attribute \src "libresoc.v:170617.14-170617.40" + process $proc$libresoc.v:170617$9812 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:168992.7-168992.20" - process $proc$libresoc.v:168992$9765 + attribute \src "libresoc.v:170624.7-170624.20" + process $proc$libresoc.v:170624$9813 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:169001.13-169001.29" - process $proc$libresoc.v:169001$9766 + attribute \src "libresoc.v:170633.13-170633.29" + process $proc$libresoc.v:170633$9814 assign { } { } - assign $0\muxid$1[1:0]$9767 2'00 + assign $0\muxid$1[1:0]$9815 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9767 + update \muxid$1 $0\muxid$1[1:0]$9815 end - attribute \src "libresoc.v:169014.14-169014.40" - process $proc$libresoc.v:169014$9768 + attribute \src "libresoc.v:170646.14-170646.40" + process $proc$libresoc.v:170646$9816 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:169021.7-169021.20" - process $proc$libresoc.v:169021$9769 + attribute \src "libresoc.v:170653.7-170653.20" + process $proc$libresoc.v:170653$9817 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:169028.14-169028.38" - process $proc$libresoc.v:169028$9770 + attribute \src "libresoc.v:170660.14-170660.38" + process $proc$libresoc.v:170660$9818 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:169035.7-169035.18" - process $proc$libresoc.v:169035$9771 + attribute \src "libresoc.v:170667.7-170667.18" + process $proc$libresoc.v:170667$9819 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:169049.7-169049.20" - process $proc$libresoc.v:169049$9772 + attribute \src "libresoc.v:170681.7-170681.20" + process $proc$libresoc.v:170681$9820 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169062.14-169062.53" - process $proc$libresoc.v:169062$9773 + attribute \src "libresoc.v:170694.14-170694.53" + process $proc$libresoc.v:170694$9821 assign { } { } - assign $0\trap_op__cia$6[63:0]$9774 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9774 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 end - attribute \src "libresoc.v:169099.14-169099.45" - process $proc$libresoc.v:169099$9775 + attribute \src "libresoc.v:170731.14-170731.45" + process $proc$libresoc.v:170731$9823 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9776 14'00000000000000 + assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9776 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 end - attribute \src "libresoc.v:169125.14-169125.39" - process $proc$libresoc.v:169125$9777 + attribute \src "libresoc.v:170757.14-170757.39" + process $proc$libresoc.v:170757$9825 assign { } { } - assign $0\trap_op__insn$4[31:0]$9778 0 + assign $0\trap_op__insn$4[31:0]$9826 0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9778 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 end - attribute \src "libresoc.v:169282.13-169282.43" - process $proc$libresoc.v:169282$9779 + attribute \src "libresoc.v:170914.13-170914.43" + process $proc$libresoc.v:170914$9827 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9780 7'0000000 + assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9780 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 end - attribute \src "libresoc.v:169368.7-169368.35" - process $proc$libresoc.v:169368$9781 + attribute \src "libresoc.v:171000.7-171000.35" + process $proc$libresoc.v:171000$9829 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9782 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9782 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 end - attribute \src "libresoc.v:169375.13-169375.43" - process $proc$libresoc.v:169375$9783 + attribute \src "libresoc.v:171007.13-171007.43" + process $proc$libresoc.v:171007$9831 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9784 8'00000000 + assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9784 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 end - attribute \src "libresoc.v:169386.14-169386.53" - process $proc$libresoc.v:169386$9785 + attribute \src "libresoc.v:171018.14-171018.53" + process $proc$libresoc.v:171018$9833 assign { } { } - assign $0\trap_op__msr$5[63:0]$9786 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9786 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 end - attribute \src "libresoc.v:169395.14-169395.46" - process $proc$libresoc.v:169395$9787 + attribute \src "libresoc.v:171027.14-171027.46" + process $proc$libresoc.v:171027$9835 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9788 13'0000000000000 + assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9788 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 end - attribute \src "libresoc.v:169404.13-169404.42" - process $proc$libresoc.v:169404$9789 + attribute \src "libresoc.v:171036.13-171036.42" + process $proc$libresoc.v:171036$9837 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9790 8'00000000 + assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9790 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 end - attribute \src "libresoc.v:169408.3-169409.29" - process $proc$libresoc.v:169408$9668 + attribute \src "libresoc.v:171040.3-171041.23" + process $proc$libresoc.v:171040$9716 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:171042.3-171043.29" + process $proc$libresoc.v:171042$9717 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:171044.3-171045.23" + process $proc$libresoc.v:171044$9718 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:171046.3-171047.29" + process $proc$libresoc.v:171046$9719 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:169410.3-169411.35" - process $proc$libresoc.v:169410$9669 + attribute \src "libresoc.v:171048.3-171049.35" + process $proc$libresoc.v:171048$9720 assign { } { } - assign $0\fast2$12[63:0]$9670 \fast2$12$next + assign $0\fast2$12[63:0]$9721 \fast2$12$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9670 + update \fast2$12 $0\fast2$12[63:0]$9721 end - attribute \src "libresoc.v:169412.3-169413.33" - process $proc$libresoc.v:169412$9671 + attribute \src "libresoc.v:171050.3-171051.33" + process $proc$libresoc.v:171050$9722 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:169414.3-169415.35" - process $proc$libresoc.v:169414$9672 + attribute \src "libresoc.v:171052.3-171053.35" + process $proc$libresoc.v:171052$9723 assign { } { } - assign $0\fast1$11[63:0]$9673 \fast1$11$next + assign $0\fast1$11[63:0]$9724 \fast1$11$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9673 + update \fast1$11 $0\fast1$11[63:0]$9724 end - attribute \src "libresoc.v:169416.3-169417.33" - process $proc$libresoc.v:169416$9674 + attribute \src "libresoc.v:171054.3-171055.33" + process $proc$libresoc.v:171054$9725 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:169418.3-169419.19" - process $proc$libresoc.v:169418$9675 + attribute \src "libresoc.v:171056.3-171057.19" + process $proc$libresoc.v:171056$9726 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:169420.3-169421.25" - process $proc$libresoc.v:169420$9676 + attribute \src "libresoc.v:171058.3-171059.25" + process $proc$libresoc.v:171058$9727 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:169422.3-169423.59" - process $proc$libresoc.v:169422$9677 + attribute \src "libresoc.v:171060.3-171061.59" + process $proc$libresoc.v:171060$9728 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9678 \trap_op__insn_type$2$next + assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9678 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 end - attribute \src "libresoc.v:169424.3-169425.55" - process $proc$libresoc.v:169424$9679 + attribute \src "libresoc.v:171062.3-171063.55" + process $proc$libresoc.v:171062$9730 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9680 \trap_op__fn_unit$3$next + assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9680 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 end - attribute \src "libresoc.v:169426.3-169427.49" - process $proc$libresoc.v:169426$9681 + attribute \src "libresoc.v:171064.3-171065.49" + process $proc$libresoc.v:171064$9732 assign { } { } - assign $0\trap_op__insn$4[31:0]$9682 \trap_op__insn$4$next + assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9682 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 end - attribute \src "libresoc.v:169428.3-169429.47" - process $proc$libresoc.v:169428$9683 + attribute \src "libresoc.v:171066.3-171067.47" + process $proc$libresoc.v:171066$9734 assign { } { } - assign $0\trap_op__msr$5[63:0]$9684 \trap_op__msr$5$next + assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9684 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 end - attribute \src "libresoc.v:169430.3-169431.47" - process $proc$libresoc.v:169430$9685 + attribute \src "libresoc.v:171068.3-171069.47" + process $proc$libresoc.v:171068$9736 assign { } { } - assign $0\trap_op__cia$6[63:0]$9686 \trap_op__cia$6$next + assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9686 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 end - attribute \src "libresoc.v:169432.3-169433.57" - process $proc$libresoc.v:169432$9687 + attribute \src "libresoc.v:171070.3-171071.57" + process $proc$libresoc.v:171070$9738 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9688 \trap_op__is_32bit$7$next + assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9688 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 end - attribute \src "libresoc.v:169434.3-169435.57" - process $proc$libresoc.v:169434$9689 + attribute \src "libresoc.v:171072.3-171073.57" + process $proc$libresoc.v:171072$9740 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9690 \trap_op__traptype$8$next + assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9690 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 end - attribute \src "libresoc.v:169436.3-169437.57" - process $proc$libresoc.v:169436$9691 + attribute \src "libresoc.v:171074.3-171075.57" + process $proc$libresoc.v:171074$9742 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9692 \trap_op__trapaddr$9$next + assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9692 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 end - attribute \src "libresoc.v:169438.3-169439.59" - process $proc$libresoc.v:169438$9693 + attribute \src "libresoc.v:171076.3-171077.59" + process $proc$libresoc.v:171076$9744 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9694 \trap_op__ldst_exc$10$next + assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9694 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 end - attribute \src "libresoc.v:169440.3-169441.33" - process $proc$libresoc.v:169440$9695 + attribute \src "libresoc.v:171078.3-171079.33" + process $proc$libresoc.v:171078$9746 assign { } { } - assign $0\muxid$1[1:0]$9696 \muxid$1$next + assign $0\muxid$1[1:0]$9747 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9696 + update \muxid$1 $0\muxid$1[1:0]$9747 end - attribute \src "libresoc.v:169442.3-169443.29" - process $proc$libresoc.v:169442$9697 + attribute \src "libresoc.v:171080.3-171081.29" + process $proc$libresoc.v:171080$9748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169444.3-169445.23" - process $proc$libresoc.v:169444$9698 - assign { } { } - assign $0\msr[63:0] \msr$next - sync posedge \coresync_clk - update \msr $0\msr[63:0] - end - attribute \src "libresoc.v:169446.3-169447.29" - process $proc$libresoc.v:169446$9699 + attribute \src "libresoc.v:171126.3-171143.6" + process $proc$libresoc.v:171126$9749 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next - sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "libresoc.v:169448.3-169449.23" - process $proc$libresoc.v:169448$9700 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:169494.3-169511.6" - process $proc$libresoc.v:169494$9701 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9702 $2\r_busy$next[0:0]$9704 - attribute \src "libresoc.v:169495.5-169495.29" + assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 + attribute \src "libresoc.v:171127.5-171127.29" switch \initial - attribute \src "libresoc.v:169495.9-169495.17" + attribute \src "libresoc.v:171127.9-171127.17" case 1'1 case end @@ -348947,34 +351444,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9703 1'1 + assign $1\r_busy$next[0:0]$9751 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9703 1'0 + assign $1\r_busy$next[0:0]$9751 1'0 case - assign $1\r_busy$next[0:0]$9703 \r_busy + assign $1\r_busy$next[0:0]$9751 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9704 1'0 + assign $2\r_busy$next[0:0]$9752 1'0 case - assign $2\r_busy$next[0:0]$9704 $1\r_busy$next[0:0]$9703 + assign $2\r_busy$next[0:0]$9752 $1\r_busy$next[0:0]$9751 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9702 + update \r_busy$next $0\r_busy$next[0:0]$9750 end - attribute \src "libresoc.v:169512.3-169524.6" - process $proc$libresoc.v:169512$9705 + attribute \src "libresoc.v:171144.3-171156.6" + process $proc$libresoc.v:171144$9753 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9706 $1\muxid$1$next[1:0]$9707 - attribute \src "libresoc.v:169513.5-169513.29" + assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 + attribute \src "libresoc.v:171145.5-171145.29" switch \initial - attribute \src "libresoc.v:169513.9-169513.17" + attribute \src "libresoc.v:171145.9-171145.17" case 1'1 case end @@ -348983,19 +351480,19 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9707 \muxid$28 + assign $1\muxid$1$next[1:0]$9755 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9707 \muxid$28 + assign $1\muxid$1$next[1:0]$9755 \muxid$28 case - assign $1\muxid$1$next[1:0]$9707 \muxid$1 + assign $1\muxid$1$next[1:0]$9755 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9706 + update \muxid$1$next $0\muxid$1$next[1:0]$9754 end - attribute \src "libresoc.v:169525.3-169545.6" - process $proc$libresoc.v:169525$9708 + attribute \src "libresoc.v:171157.3-171177.6" + process $proc$libresoc.v:171157$9756 assign { } { } assign { } { } assign { } { } @@ -349014,18 +351511,18 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9709 $1\trap_op__cia$6$next[63:0]$9718 - assign $0\trap_op__fn_unit$3$next[13:0]$9710 $1\trap_op__fn_unit$3$next[13:0]$9719 - assign $0\trap_op__insn$4$next[31:0]$9711 $1\trap_op__insn$4$next[31:0]$9720 - assign $0\trap_op__insn_type$2$next[6:0]$9712 $1\trap_op__insn_type$2$next[6:0]$9721 - assign $0\trap_op__is_32bit$7$next[0:0]$9713 $1\trap_op__is_32bit$7$next[0:0]$9722 - assign $0\trap_op__ldst_exc$10$next[7:0]$9714 $1\trap_op__ldst_exc$10$next[7:0]$9723 - assign $0\trap_op__msr$5$next[63:0]$9715 $1\trap_op__msr$5$next[63:0]$9724 - assign $0\trap_op__trapaddr$9$next[12:0]$9716 $1\trap_op__trapaddr$9$next[12:0]$9725 - assign $0\trap_op__traptype$8$next[7:0]$9717 $1\trap_op__traptype$8$next[7:0]$9726 - attribute \src "libresoc.v:169526.5-169526.29" + assign $0\trap_op__cia$6$next[63:0]$9757 $1\trap_op__cia$6$next[63:0]$9766 + assign $0\trap_op__fn_unit$3$next[13:0]$9758 $1\trap_op__fn_unit$3$next[13:0]$9767 + assign $0\trap_op__insn$4$next[31:0]$9759 $1\trap_op__insn$4$next[31:0]$9768 + assign $0\trap_op__insn_type$2$next[6:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9769 + assign $0\trap_op__is_32bit$7$next[0:0]$9761 $1\trap_op__is_32bit$7$next[0:0]$9770 + assign $0\trap_op__ldst_exc$10$next[7:0]$9762 $1\trap_op__ldst_exc$10$next[7:0]$9771 + assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 + assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 + assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 + attribute \src "libresoc.v:171158.5-171158.29" switch \initial - attribute \src "libresoc.v:169526.9-169526.17" + attribute \src "libresoc.v:171158.9-171158.17" case 1'1 case end @@ -349042,7 +351539,7 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -349054,41 +351551,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $1\trap_op__cia$6$next[63:0]$9718 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[13:0]$9719 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9720 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9721 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9722 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9723 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9724 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9725 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9726 \trap_op__traptype$8 + assign $1\trap_op__cia$6$next[63:0]$9766 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9767 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9768 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9769 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9770 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9771 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9772 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9773 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9774 \trap_op__traptype$8 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9709 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9710 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9711 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9712 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9713 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9714 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9715 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9716 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9717 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9757 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9758 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9759 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9760 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9761 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9762 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9763 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 end - attribute \src "libresoc.v:169546.3-169564.6" - process $proc$libresoc.v:169546$9727 + attribute \src "libresoc.v:171178.3-171196.6" + process $proc$libresoc.v:171178$9775 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9728 $1\o$next[63:0]$9730 + assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 assign { } { } - assign $0\o_ok$next[0:0]$9729 $2\o_ok$next[0:0]$9732 - attribute \src "libresoc.v:169547.5-169547.29" + assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 + attribute \src "libresoc.v:171179.5-171179.29" switch \initial - attribute \src "libresoc.v:169547.9-169547.17" + attribute \src "libresoc.v:171179.9-171179.17" case 1'1 case end @@ -349098,41 +351595,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } case - assign $1\o$next[63:0]$9730 \o - assign $1\o_ok$next[0:0]$9731 \o_ok + assign $1\o$next[63:0]$9778 \o + assign $1\o_ok$next[0:0]$9779 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9732 1'0 + assign $2\o_ok$next[0:0]$9780 1'0 case - assign $2\o_ok$next[0:0]$9732 $1\o_ok$next[0:0]$9731 + assign $2\o_ok$next[0:0]$9780 $1\o_ok$next[0:0]$9779 end sync always - update \o$next $0\o$next[63:0]$9728 - update \o_ok$next $0\o_ok$next[0:0]$9729 + update \o$next $0\o$next[63:0]$9776 + update \o_ok$next $0\o_ok$next[0:0]$9777 end - attribute \src "libresoc.v:169565.3-169583.6" - process $proc$libresoc.v:169565$9733 + attribute \src "libresoc.v:171197.3-171215.6" + process $proc$libresoc.v:171197$9781 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$11$next[63:0]$9735 $1\fast1$11$next[63:0]$9737 - assign $0\fast1_ok$next[0:0]$9734 $2\fast1_ok$next[0:0]$9738 - attribute \src "libresoc.v:169566.5-169566.29" + assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 + assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:171198.5-171198.29" switch \initial - attribute \src "libresoc.v:169566.9-169566.17" + attribute \src "libresoc.v:171198.9-171198.17" case 1'1 case end @@ -349142,41 +351639,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } case - assign $1\fast1_ok$next[0:0]$9736 \fast1_ok - assign $1\fast1$11$next[63:0]$9737 \fast1$11 + assign $1\fast1_ok$next[0:0]$9784 \fast1_ok + assign $1\fast1$11$next[63:0]$9785 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9738 1'0 + assign $2\fast1_ok$next[0:0]$9786 1'0 case - assign $2\fast1_ok$next[0:0]$9738 $1\fast1_ok$next[0:0]$9736 + assign $2\fast1_ok$next[0:0]$9786 $1\fast1_ok$next[0:0]$9784 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9734 - update \fast1$11$next $0\fast1$11$next[63:0]$9735 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 + update \fast1$11$next $0\fast1$11$next[63:0]$9783 end - attribute \src "libresoc.v:169584.3-169602.6" - process $proc$libresoc.v:169584$9739 + attribute \src "libresoc.v:171216.3-171234.6" + process $proc$libresoc.v:171216$9787 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$12$next[63:0]$9741 $1\fast2$12$next[63:0]$9743 - assign $0\fast2_ok$next[0:0]$9740 $2\fast2_ok$next[0:0]$9744 - attribute \src "libresoc.v:169585.5-169585.29" + assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 + assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:171217.5-171217.29" switch \initial - attribute \src "libresoc.v:169585.9-169585.17" + attribute \src "libresoc.v:171217.9-171217.17" case 1'1 case end @@ -349186,41 +351683,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } case - assign $1\fast2_ok$next[0:0]$9742 \fast2_ok - assign $1\fast2$12$next[63:0]$9743 \fast2$12 + assign $1\fast2_ok$next[0:0]$9790 \fast2_ok + assign $1\fast2$12$next[63:0]$9791 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9744 1'0 + assign $2\fast2_ok$next[0:0]$9792 1'0 case - assign $2\fast2_ok$next[0:0]$9744 $1\fast2_ok$next[0:0]$9742 + assign $2\fast2_ok$next[0:0]$9792 $1\fast2_ok$next[0:0]$9790 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9740 - update \fast2$12$next $0\fast2$12$next[63:0]$9741 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 + update \fast2$12$next $0\fast2$12$next[63:0]$9789 end - attribute \src "libresoc.v:169603.3-169621.6" - process $proc$libresoc.v:169603$9745 + attribute \src "libresoc.v:171235.3-171253.6" + process $proc$libresoc.v:171235$9793 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9746 $1\nia$next[63:0]$9748 + assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 assign { } { } - assign $0\nia_ok$next[0:0]$9747 $2\nia_ok$next[0:0]$9750 - attribute \src "libresoc.v:169604.5-169604.29" + assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 + attribute \src "libresoc.v:171236.5-171236.29" switch \initial - attribute \src "libresoc.v:169604.9-169604.17" + attribute \src "libresoc.v:171236.9-171236.17" case 1'1 case end @@ -349230,41 +351727,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } case - assign $1\nia$next[63:0]$9748 \nia - assign $1\nia_ok$next[0:0]$9749 \nia_ok + assign $1\nia$next[63:0]$9796 \nia + assign $1\nia_ok$next[0:0]$9797 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9750 1'0 + assign $2\nia_ok$next[0:0]$9798 1'0 case - assign $2\nia_ok$next[0:0]$9750 $1\nia_ok$next[0:0]$9749 + assign $2\nia_ok$next[0:0]$9798 $1\nia_ok$next[0:0]$9797 end sync always - update \nia$next $0\nia$next[63:0]$9746 - update \nia_ok$next $0\nia_ok$next[0:0]$9747 + update \nia$next $0\nia$next[63:0]$9794 + update \nia_ok$next $0\nia_ok$next[0:0]$9795 end - attribute \src "libresoc.v:169622.3-169640.6" - process $proc$libresoc.v:169622$9751 + attribute \src "libresoc.v:171254.3-171272.6" + process $proc$libresoc.v:171254$9799 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9752 $1\msr$next[63:0]$9754 + assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 assign { } { } - assign $0\msr_ok$next[0:0]$9753 $2\msr_ok$next[0:0]$9756 - attribute \src "libresoc.v:169623.5-169623.29" + assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 + attribute \src "libresoc.v:171255.5-171255.29" switch \initial - attribute \src "libresoc.v:169623.9-169623.17" + attribute \src "libresoc.v:171255.9-171255.17" case 1'1 case end @@ -349274,30 +351771,30 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } case - assign $1\msr$next[63:0]$9754 \msr - assign $1\msr_ok$next[0:0]$9755 \msr_ok + assign $1\msr$next[63:0]$9802 \msr + assign $1\msr_ok$next[0:0]$9803 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9756 1'0 + assign $2\msr_ok$next[0:0]$9804 1'0 case - assign $2\msr_ok$next[0:0]$9756 $1\msr_ok$next[0:0]$9755 + assign $2\msr_ok$next[0:0]$9804 $1\msr_ok$next[0:0]$9803 end sync always - update \msr$next $0\msr$next[63:0]$9752 - update \msr_ok$next $0\msr_ok$next[0:0]$9753 + update \msr$next $0\msr$next[63:0]$9800 + update \msr_ok$next $0\msr_ok$next[0:0]$9801 end - connect \$26 $and$libresoc.v:169407$9667_Y + connect \$26 $and$libresoc.v:171039$9715_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -349317,266 +351814,266 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:169663.1-171166.10" +attribute \src "libresoc.v:171295.1-172798.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:171004.3-171022.6" - wire width 4 $0\cr_a$next[3:0]$9847 - attribute \src "libresoc.v:170823.3-170824.25" + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $0\cr_a$next[3:0]$9895 + attribute \src "libresoc.v:172455.3-172456.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $0\cr_a_ok$next[0:0]$9848 - attribute \src "libresoc.v:170825.3-170826.31" + attribute \src "libresoc.v:172636.3-172654.6" + wire $0\cr_a_ok$next[0:0]$9896 + attribute \src "libresoc.v:172457.3-172458.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:169664.7-169664.20" + attribute \src "libresoc.v:171296.7-171296.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171092.3-171133.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9872 - attribute \src "libresoc.v:170863.3-170864.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9834 - attribute \src "libresoc.v:169705.13-169705.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9918 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9873 - attribute \src "libresoc.v:170833.3-170834.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9804 - attribute \src "libresoc.v:169744.14-169744.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9920 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9874 - attribute \src "libresoc.v:170835.3-170836.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9806 - attribute \src "libresoc.v:169768.14-169768.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9922 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9875 - attribute \src "libresoc.v:170837.3-170838.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9808 - attribute \src "libresoc.v:169777.7-169777.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9924 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9876 - attribute \src "libresoc.v:170851.3-170852.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9822 - attribute \src "libresoc.v:169794.13-169794.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9926 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9877 - attribute \src "libresoc.v:170865.3-170866.57" - wire width 32 $0\logical_op__insn$19[31:0]$9836 - attribute \src "libresoc.v:169807.14-169807.43" - wire width 32 $0\logical_op__insn$19[31:0]$9928 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9878 - attribute \src "libresoc.v:170831.3-170832.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9802 - attribute \src "libresoc.v:169966.13-169966.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9930 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__invert_in$10$next[0:0]$9879 - attribute \src "libresoc.v:170847.3-170848.67" - wire $0\logical_op__invert_in$10[0:0]$9818 - attribute \src "libresoc.v:170050.7-170050.40" - wire $0\logical_op__invert_in$10[0:0]$9932 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__invert_out$13$next[0:0]$9880 - attribute \src "libresoc.v:170853.3-170854.69" - wire $0\logical_op__invert_out$13[0:0]$9824 - attribute \src "libresoc.v:170059.7-170059.41" - wire $0\logical_op__invert_out$13[0:0]$9934 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9881 - attribute \src "libresoc.v:170859.3-170860.65" - wire $0\logical_op__is_32bit$16[0:0]$9830 - attribute \src "libresoc.v:170068.7-170068.39" - wire $0\logical_op__is_32bit$16[0:0]$9936 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__is_signed$17$next[0:0]$9882 - attribute \src "libresoc.v:170861.3-170862.67" - wire $0\logical_op__is_signed$17[0:0]$9832 - attribute \src "libresoc.v:170077.7-170077.40" - wire $0\logical_op__is_signed$17[0:0]$9938 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9883 - attribute \src "libresoc.v:170843.3-170844.59" - wire $0\logical_op__oe__oe$8[0:0]$9814 - attribute \src "libresoc.v:170086.7-170086.36" - wire $0\logical_op__oe__oe$8[0:0]$9940 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9884 - attribute \src "libresoc.v:170845.3-170846.59" - wire $0\logical_op__oe__ok$9[0:0]$9816 - attribute \src "libresoc.v:170097.7-170097.36" - wire $0\logical_op__oe__ok$9[0:0]$9942 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__output_carry$15$next[0:0]$9885 - attribute \src "libresoc.v:170857.3-170858.73" - wire $0\logical_op__output_carry$15[0:0]$9828 - attribute \src "libresoc.v:170104.7-170104.43" - wire $0\logical_op__output_carry$15[0:0]$9944 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9886 - attribute \src "libresoc.v:170841.3-170842.59" - wire $0\logical_op__rc__ok$7[0:0]$9812 - attribute \src "libresoc.v:170113.7-170113.36" - wire $0\logical_op__rc__ok$7[0:0]$9946 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9887 - attribute \src "libresoc.v:170839.3-170840.59" - wire $0\logical_op__rc__rc$6[0:0]$9810 - attribute \src "libresoc.v:170122.7-170122.36" - wire $0\logical_op__rc__rc$6[0:0]$9948 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9888 - attribute \src "libresoc.v:170855.3-170856.67" - wire $0\logical_op__write_cr0$14[0:0]$9826 - attribute \src "libresoc.v:170131.7-170131.40" - wire $0\logical_op__write_cr0$14[0:0]$9950 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__zero_a$11$next[0:0]$9889 - attribute \src "libresoc.v:170849.3-170850.61" - wire $0\logical_op__zero_a$11[0:0]$9820 - attribute \src "libresoc.v:170140.7-170140.37" - wire $0\logical_op__zero_a$11[0:0]$9952 - attribute \src "libresoc.v:171079.3-171091.6" - wire width 2 $0\muxid$1$next[1:0]$9869 - attribute \src "libresoc.v:170867.3-170868.33" - wire width 2 $0\muxid$1[1:0]$9838 - attribute \src "libresoc.v:170149.13-170149.29" - wire width 2 $0\muxid$1[1:0]$9954 - attribute \src "libresoc.v:170985.3-171003.6" - wire width 64 $0\o$next[63:0]$9841 - attribute \src "libresoc.v:170827.3-170828.19" + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 + attribute \src "libresoc.v:172495.3-172496.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9882 + attribute \src "libresoc.v:171337.13-171337.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9966 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 + attribute \src "libresoc.v:172465.3-172466.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 + attribute \src "libresoc.v:171376.14-171376.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 + attribute \src "libresoc.v:172467.3-172468.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 + attribute \src "libresoc.v:171400.14-171400.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 + attribute \src "libresoc.v:172469.3-172470.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9856 + attribute \src "libresoc.v:171409.7-171409.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9972 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 + attribute \src "libresoc.v:172483.3-172484.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9870 + attribute \src "libresoc.v:171426.13-171426.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9974 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9925 + attribute \src "libresoc.v:172497.3-172498.57" + wire width 32 $0\logical_op__insn$19[31:0]$9884 + attribute \src "libresoc.v:171439.14-171439.43" + wire width 32 $0\logical_op__insn$19[31:0]$9976 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 + attribute \src "libresoc.v:172463.3-172464.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9850 + attribute \src "libresoc.v:171598.13-171598.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9978 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_in$10$next[0:0]$9927 + attribute \src "libresoc.v:172479.3-172480.67" + wire $0\logical_op__invert_in$10[0:0]$9866 + attribute \src "libresoc.v:171682.7-171682.40" + wire $0\logical_op__invert_in$10[0:0]$9980 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_out$13$next[0:0]$9928 + attribute \src "libresoc.v:172485.3-172486.69" + wire $0\logical_op__invert_out$13[0:0]$9872 + attribute \src "libresoc.v:171691.7-171691.41" + wire $0\logical_op__invert_out$13[0:0]$9982 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9929 + attribute \src "libresoc.v:172491.3-172492.65" + wire $0\logical_op__is_32bit$16[0:0]$9878 + attribute \src "libresoc.v:171700.7-171700.39" + wire $0\logical_op__is_32bit$16[0:0]$9984 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_signed$17$next[0:0]$9930 + attribute \src "libresoc.v:172493.3-172494.67" + wire $0\logical_op__is_signed$17[0:0]$9880 + attribute \src "libresoc.v:171709.7-171709.40" + wire $0\logical_op__is_signed$17[0:0]$9986 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9931 + attribute \src "libresoc.v:172475.3-172476.59" + wire $0\logical_op__oe__oe$8[0:0]$9862 + attribute \src "libresoc.v:171718.7-171718.36" + wire $0\logical_op__oe__oe$8[0:0]$9988 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9932 + attribute \src "libresoc.v:172477.3-172478.59" + wire $0\logical_op__oe__ok$9[0:0]$9864 + attribute \src "libresoc.v:171729.7-171729.36" + wire $0\logical_op__oe__ok$9[0:0]$9990 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__output_carry$15$next[0:0]$9933 + attribute \src "libresoc.v:172489.3-172490.73" + wire $0\logical_op__output_carry$15[0:0]$9876 + attribute \src "libresoc.v:171736.7-171736.43" + wire $0\logical_op__output_carry$15[0:0]$9992 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9934 + attribute \src "libresoc.v:172473.3-172474.59" + wire $0\logical_op__rc__ok$7[0:0]$9860 + attribute \src "libresoc.v:171745.7-171745.36" + wire $0\logical_op__rc__ok$7[0:0]$9994 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9935 + attribute \src "libresoc.v:172471.3-172472.59" + wire $0\logical_op__rc__rc$6[0:0]$9858 + attribute \src "libresoc.v:171754.7-171754.36" + wire $0\logical_op__rc__rc$6[0:0]$9996 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9936 + attribute \src "libresoc.v:172487.3-172488.67" + wire $0\logical_op__write_cr0$14[0:0]$9874 + attribute \src "libresoc.v:171763.7-171763.40" + wire $0\logical_op__write_cr0$14[0:0]$9998 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__zero_a$11$next[0:0]$9937 + attribute \src "libresoc.v:171772.7-171772.37" + wire $0\logical_op__zero_a$11[0:0]$10000 + attribute \src "libresoc.v:172481.3-172482.61" + wire $0\logical_op__zero_a$11[0:0]$9868 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $0\muxid$1$next[1:0]$9917 + attribute \src "libresoc.v:171781.13-171781.29" + wire width 2 $0\muxid$1[1:0]$10002 + attribute \src "libresoc.v:172499.3-172500.33" + wire width 2 $0\muxid$1[1:0]$9886 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $0\o$next[63:0]$9889 + attribute \src "libresoc.v:172459.3-172460.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:170985.3-171003.6" - wire $0\o_ok$next[0:0]$9842 - attribute \src "libresoc.v:170829.3-170830.25" + attribute \src "libresoc.v:172617.3-172635.6" + wire $0\o_ok$next[0:0]$9890 + attribute \src "libresoc.v:172461.3-172462.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:171061.3-171078.6" - wire $0\r_busy$next[0:0]$9865 - attribute \src "libresoc.v:170869.3-170870.29" + attribute \src "libresoc.v:172693.3-172710.6" + wire $0\r_busy$next[0:0]$9913 + attribute \src "libresoc.v:172501.3-172502.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire width 2 $0\xer_ov$next[1:0]$9853 - attribute \src "libresoc.v:170819.3-170820.29" + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $0\xer_ov$next[1:0]$9901 + attribute \src "libresoc.v:172451.3-172452.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire $0\xer_ov_ok$next[0:0]$9854 - attribute \src "libresoc.v:170821.3-170822.35" + attribute \src "libresoc.v:172655.3-172673.6" + wire $0\xer_ov_ok$next[0:0]$9902 + attribute \src "libresoc.v:172453.3-172454.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:171042.3-171060.6" - wire $0\xer_so$20$next[0:0]$9860 - attribute \src "libresoc.v:170815.3-170816.37" - wire $0\xer_so$20[0:0]$9793 - attribute \src "libresoc.v:170800.7-170800.25" - wire $0\xer_so$20[0:0]$9961 - attribute \src "libresoc.v:171042.3-171060.6" - wire $0\xer_so_ok$next[0:0]$9859 - attribute \src "libresoc.v:170817.3-170818.35" + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so$20$next[0:0]$9908 + attribute \src "libresoc.v:172432.7-172432.25" + wire $0\xer_so$20[0:0]$10009 + attribute \src "libresoc.v:172447.3-172448.37" + wire $0\xer_so$20[0:0]$9841 + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so_ok$next[0:0]$9907 + attribute \src "libresoc.v:172449.3-172450.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire width 4 $1\cr_a$next[3:0]$9849 - attribute \src "libresoc.v:169673.13-169673.24" + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $1\cr_a$next[3:0]$9897 + attribute \src "libresoc.v:171305.13-171305.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $1\cr_a_ok$next[0:0]$9850 - attribute \src "libresoc.v:169682.7-169682.21" + attribute \src "libresoc.v:172636.3-172654.6" + wire $1\cr_a_ok$next[0:0]$9898 + attribute \src "libresoc.v:171314.7-171314.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:171092.3-171133.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9890 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9891 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9892 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9893 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9894 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9895 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9896 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__invert_in$10$next[0:0]$9897 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__invert_out$13$next[0:0]$9898 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9899 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__is_signed$17$next[0:0]$9900 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9901 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9902 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__output_carry$15$next[0:0]$9903 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9904 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9905 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9906 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__zero_a$11$next[0:0]$9907 - attribute \src "libresoc.v:171079.3-171091.6" - wire width 2 $1\muxid$1$next[1:0]$9870 - attribute \src "libresoc.v:170985.3-171003.6" - wire width 64 $1\o$next[63:0]$9843 - attribute \src "libresoc.v:170162.14-170162.38" + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9943 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_in$10$next[0:0]$9945 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_out$13$next[0:0]$9946 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9947 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_signed$17$next[0:0]$9948 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9949 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9950 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__output_carry$15$next[0:0]$9951 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9952 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9953 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9954 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__zero_a$11$next[0:0]$9955 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $1\o$next[63:0]$9891 + attribute \src "libresoc.v:171794.14-171794.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:170985.3-171003.6" - wire $1\o_ok$next[0:0]$9844 - attribute \src "libresoc.v:170169.7-170169.18" + attribute \src "libresoc.v:172617.3-172635.6" + wire $1\o_ok$next[0:0]$9892 + attribute \src "libresoc.v:171801.7-171801.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:171061.3-171078.6" - wire $1\r_busy$next[0:0]$9866 - attribute \src "libresoc.v:170765.7-170765.20" + attribute \src "libresoc.v:172693.3-172710.6" + wire $1\r_busy$next[0:0]$9914 + attribute \src "libresoc.v:172397.7-172397.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire width 2 $1\xer_ov$next[1:0]$9855 - attribute \src "libresoc.v:170780.13-170780.26" + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $1\xer_ov$next[1:0]$9903 + attribute \src "libresoc.v:172412.13-172412.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire $1\xer_ov_ok$next[0:0]$9856 - attribute \src "libresoc.v:170787.7-170787.23" + attribute \src "libresoc.v:172655.3-172673.6" + wire $1\xer_ov_ok$next[0:0]$9904 + attribute \src "libresoc.v:172419.7-172419.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:171042.3-171060.6" - wire $1\xer_so$20$next[0:0]$9862 - attribute \src "libresoc.v:171042.3-171060.6" - wire $1\xer_so_ok$next[0:0]$9861 - attribute \src "libresoc.v:170805.7-170805.23" + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so$20$next[0:0]$9910 + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so_ok$next[0:0]$9909 + attribute \src "libresoc.v:172437.7-172437.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $2\cr_a_ok$next[0:0]$9851 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9908 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9909 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9910 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9911 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9912 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9913 - attribute \src "libresoc.v:170985.3-171003.6" - wire $2\o_ok$next[0:0]$9845 - attribute \src "libresoc.v:171061.3-171078.6" - wire $2\r_busy$next[0:0]$9867 - attribute \src "libresoc.v:171023.3-171041.6" - wire $2\xer_ov_ok$next[0:0]$9857 - attribute \src "libresoc.v:171042.3-171060.6" - wire $2\xer_so_ok$next[0:0]$9863 - attribute \src "libresoc.v:170814.18-170814.118" - wire $and$libresoc.v:170814$9791_Y + attribute \src "libresoc.v:172636.3-172654.6" + wire $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9958 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9959 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9960 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172617.3-172635.6" + wire $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172693.3-172710.6" + wire $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172655.3-172673.6" + wire $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172674.3-172692.6" + wire $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172446.18-172446.118" + wire $and$libresoc.v:172446$9839_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 56 \cr_a @@ -349606,7 +352103,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:169664.7-169664.15" + attribute \src "libresoc.v:171296.7-171296.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -350697,7 +353194,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170814$9791 + cell $and $and$libresoc.v:172446$9839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350705,16 +353202,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:170814$9791_Y + connect \Y $and$libresoc.v:172446$9839_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170871.10-170874.4" + attribute \src "libresoc.v:172503.10-172506.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170875.15-170927.4" + attribute \src "libresoc.v:172507.15-172559.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -350769,7 +353266,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:170928.16-170980.4" + attribute \src "libresoc.v:172560.16-172612.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -350824,451 +353321,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:170981.10-170984.4" + attribute \src "libresoc.v:172613.10-172616.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169664.7-169664.20" - process $proc$libresoc.v:169664$9914 + attribute \src "libresoc.v:171296.7-171296.20" + process $proc$libresoc.v:171296$9962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169673.13-169673.24" - process $proc$libresoc.v:169673$9915 + attribute \src "libresoc.v:171305.13-171305.24" + process $proc$libresoc.v:171305$9963 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:169682.7-169682.21" - process $proc$libresoc.v:169682$9916 + attribute \src "libresoc.v:171314.7-171314.21" + process $proc$libresoc.v:171314$9964 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:169705.13-169705.45" - process $proc$libresoc.v:169705$9917 + attribute \src "libresoc.v:171337.13-171337.45" + process $proc$libresoc.v:171337$9965 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9918 4'0000 + assign $0\logical_op__data_len$18[3:0]$9966 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9918 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 end - attribute \src "libresoc.v:169744.14-169744.48" - process $proc$libresoc.v:169744$9919 + attribute \src "libresoc.v:171376.14-171376.48" + process $proc$libresoc.v:171376$9967 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9920 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9920 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 end - attribute \src "libresoc.v:169768.14-169768.67" - process $proc$libresoc.v:169768$9921 + attribute \src "libresoc.v:171400.14-171400.67" + process $proc$libresoc.v:171400$9969 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9922 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9922 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 end - attribute \src "libresoc.v:169777.7-169777.42" - process $proc$libresoc.v:169777$9923 + attribute \src "libresoc.v:171409.7-171409.42" + process $proc$libresoc.v:171409$9971 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9924 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9924 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 end - attribute \src "libresoc.v:169794.13-169794.48" - process $proc$libresoc.v:169794$9925 + attribute \src "libresoc.v:171426.13-171426.48" + process $proc$libresoc.v:171426$9973 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9926 2'00 + assign $0\logical_op__input_carry$12[1:0]$9974 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9926 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 end - attribute \src "libresoc.v:169807.14-169807.43" - process $proc$libresoc.v:169807$9927 + attribute \src "libresoc.v:171439.14-171439.43" + process $proc$libresoc.v:171439$9975 assign { } { } - assign $0\logical_op__insn$19[31:0]$9928 0 + assign $0\logical_op__insn$19[31:0]$9976 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9928 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 end - attribute \src "libresoc.v:169966.13-169966.46" - process $proc$libresoc.v:169966$9929 + attribute \src "libresoc.v:171598.13-171598.46" + process $proc$libresoc.v:171598$9977 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9930 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9930 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 end - attribute \src "libresoc.v:170050.7-170050.40" - process $proc$libresoc.v:170050$9931 + attribute \src "libresoc.v:171682.7-171682.40" + process $proc$libresoc.v:171682$9979 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9932 1'0 + assign $0\logical_op__invert_in$10[0:0]$9980 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9932 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 end - attribute \src "libresoc.v:170059.7-170059.41" - process $proc$libresoc.v:170059$9933 + attribute \src "libresoc.v:171691.7-171691.41" + process $proc$libresoc.v:171691$9981 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9934 1'0 + assign $0\logical_op__invert_out$13[0:0]$9982 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9934 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 end - attribute \src "libresoc.v:170068.7-170068.39" - process $proc$libresoc.v:170068$9935 + attribute \src "libresoc.v:171700.7-171700.39" + process $proc$libresoc.v:171700$9983 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9936 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9936 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 end - attribute \src "libresoc.v:170077.7-170077.40" - process $proc$libresoc.v:170077$9937 + attribute \src "libresoc.v:171709.7-171709.40" + process $proc$libresoc.v:171709$9985 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9938 1'0 + assign $0\logical_op__is_signed$17[0:0]$9986 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9938 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 end - attribute \src "libresoc.v:170086.7-170086.36" - process $proc$libresoc.v:170086$9939 + attribute \src "libresoc.v:171718.7-171718.36" + process $proc$libresoc.v:171718$9987 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9940 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9940 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 end - attribute \src "libresoc.v:170097.7-170097.36" - process $proc$libresoc.v:170097$9941 + attribute \src "libresoc.v:171729.7-171729.36" + process $proc$libresoc.v:171729$9989 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9942 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9942 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 end - attribute \src "libresoc.v:170104.7-170104.43" - process $proc$libresoc.v:170104$9943 + attribute \src "libresoc.v:171736.7-171736.43" + process $proc$libresoc.v:171736$9991 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9944 1'0 + assign $0\logical_op__output_carry$15[0:0]$9992 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9944 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 end - attribute \src "libresoc.v:170113.7-170113.36" - process $proc$libresoc.v:170113$9945 + attribute \src "libresoc.v:171745.7-171745.36" + process $proc$libresoc.v:171745$9993 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9946 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9946 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 end - attribute \src "libresoc.v:170122.7-170122.36" - process $proc$libresoc.v:170122$9947 + attribute \src "libresoc.v:171754.7-171754.36" + process $proc$libresoc.v:171754$9995 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9948 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9948 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 end - attribute \src "libresoc.v:170131.7-170131.40" - process $proc$libresoc.v:170131$9949 + attribute \src "libresoc.v:171763.7-171763.40" + process $proc$libresoc.v:171763$9997 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9950 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9950 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 end - attribute \src "libresoc.v:170140.7-170140.37" - process $proc$libresoc.v:170140$9951 + attribute \src "libresoc.v:171772.7-171772.37" + process $proc$libresoc.v:171772$9999 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9952 1'0 + assign $0\logical_op__zero_a$11[0:0]$10000 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9952 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 end - attribute \src "libresoc.v:170149.13-170149.29" - process $proc$libresoc.v:170149$9953 + attribute \src "libresoc.v:171781.13-171781.29" + process $proc$libresoc.v:171781$10001 assign { } { } - assign $0\muxid$1[1:0]$9954 2'00 + assign $0\muxid$1[1:0]$10002 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9954 + update \muxid$1 $0\muxid$1[1:0]$10002 end - attribute \src "libresoc.v:170162.14-170162.38" - process $proc$libresoc.v:170162$9955 + attribute \src "libresoc.v:171794.14-171794.38" + process $proc$libresoc.v:171794$10003 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:170169.7-170169.18" - process $proc$libresoc.v:170169$9956 + attribute \src "libresoc.v:171801.7-171801.18" + process $proc$libresoc.v:171801$10004 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:170765.7-170765.20" - process $proc$libresoc.v:170765$9957 + attribute \src "libresoc.v:172397.7-172397.20" + process $proc$libresoc.v:172397$10005 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170780.13-170780.26" - process $proc$libresoc.v:170780$9958 + attribute \src "libresoc.v:172412.13-172412.26" + process $proc$libresoc.v:172412$10006 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:170787.7-170787.23" - process $proc$libresoc.v:170787$9959 + attribute \src "libresoc.v:172419.7-172419.23" + process $proc$libresoc.v:172419$10007 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:170800.7-170800.25" - process $proc$libresoc.v:170800$9960 + attribute \src "libresoc.v:172432.7-172432.25" + process $proc$libresoc.v:172432$10008 assign { } { } - assign $0\xer_so$20[0:0]$9961 1'0 + assign $0\xer_so$20[0:0]$10009 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$9961 + update \xer_so$20 $0\xer_so$20[0:0]$10009 end - attribute \src "libresoc.v:170805.7-170805.23" - process $proc$libresoc.v:170805$9962 + attribute \src "libresoc.v:172437.7-172437.23" + process $proc$libresoc.v:172437$10010 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:170815.3-170816.37" - process $proc$libresoc.v:170815$9792 + attribute \src "libresoc.v:172447.3-172448.37" + process $proc$libresoc.v:172447$9840 assign { } { } - assign $0\xer_so$20[0:0]$9793 \xer_so$20$next + assign $0\xer_so$20[0:0]$9841 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9793 + update \xer_so$20 $0\xer_so$20[0:0]$9841 end - attribute \src "libresoc.v:170817.3-170818.35" - process $proc$libresoc.v:170817$9794 + attribute \src "libresoc.v:172449.3-172450.35" + process $proc$libresoc.v:172449$9842 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:170819.3-170820.29" - process $proc$libresoc.v:170819$9795 + attribute \src "libresoc.v:172451.3-172452.29" + process $proc$libresoc.v:172451$9843 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:170821.3-170822.35" - process $proc$libresoc.v:170821$9796 + attribute \src "libresoc.v:172453.3-172454.35" + process $proc$libresoc.v:172453$9844 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:170823.3-170824.25" - process $proc$libresoc.v:170823$9797 + attribute \src "libresoc.v:172455.3-172456.25" + process $proc$libresoc.v:172455$9845 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:170825.3-170826.31" - process $proc$libresoc.v:170825$9798 + attribute \src "libresoc.v:172457.3-172458.31" + process $proc$libresoc.v:172457$9846 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:170827.3-170828.19" - process $proc$libresoc.v:170827$9799 + attribute \src "libresoc.v:172459.3-172460.19" + process $proc$libresoc.v:172459$9847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:170829.3-170830.25" - process $proc$libresoc.v:170829$9800 + attribute \src "libresoc.v:172461.3-172462.25" + process $proc$libresoc.v:172461$9848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:170831.3-170832.65" - process $proc$libresoc.v:170831$9801 + attribute \src "libresoc.v:172463.3-172464.65" + process $proc$libresoc.v:172463$9849 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9802 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9802 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 end - attribute \src "libresoc.v:170833.3-170834.61" - process $proc$libresoc.v:170833$9803 + attribute \src "libresoc.v:172465.3-172466.61" + process $proc$libresoc.v:172465$9851 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9804 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9804 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 end - attribute \src "libresoc.v:170835.3-170836.75" - process $proc$libresoc.v:170835$9805 + attribute \src "libresoc.v:172467.3-172468.75" + process $proc$libresoc.v:172467$9853 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9806 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9806 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 end - attribute \src "libresoc.v:170837.3-170838.71" - process $proc$libresoc.v:170837$9807 + attribute \src "libresoc.v:172469.3-172470.71" + process $proc$libresoc.v:172469$9855 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9808 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9808 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 end - attribute \src "libresoc.v:170839.3-170840.59" - process $proc$libresoc.v:170839$9809 + attribute \src "libresoc.v:172471.3-172472.59" + process $proc$libresoc.v:172471$9857 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9810 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9810 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 end - attribute \src "libresoc.v:170841.3-170842.59" - process $proc$libresoc.v:170841$9811 + attribute \src "libresoc.v:172473.3-172474.59" + process $proc$libresoc.v:172473$9859 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9812 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9812 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 end - attribute \src "libresoc.v:170843.3-170844.59" - process $proc$libresoc.v:170843$9813 + attribute \src "libresoc.v:172475.3-172476.59" + process $proc$libresoc.v:172475$9861 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9814 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9814 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 end - attribute \src "libresoc.v:170845.3-170846.59" - process $proc$libresoc.v:170845$9815 + attribute \src "libresoc.v:172477.3-172478.59" + process $proc$libresoc.v:172477$9863 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9816 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9816 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 end - attribute \src "libresoc.v:170847.3-170848.67" - process $proc$libresoc.v:170847$9817 + attribute \src "libresoc.v:172479.3-172480.67" + process $proc$libresoc.v:172479$9865 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9818 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9818 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 end - attribute \src "libresoc.v:170849.3-170850.61" - process $proc$libresoc.v:170849$9819 + attribute \src "libresoc.v:172481.3-172482.61" + process $proc$libresoc.v:172481$9867 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9820 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9820 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 end - attribute \src "libresoc.v:170851.3-170852.71" - process $proc$libresoc.v:170851$9821 + attribute \src "libresoc.v:172483.3-172484.71" + process $proc$libresoc.v:172483$9869 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9822 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9822 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 end - attribute \src "libresoc.v:170853.3-170854.69" - process $proc$libresoc.v:170853$9823 + attribute \src "libresoc.v:172485.3-172486.69" + process $proc$libresoc.v:172485$9871 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9824 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9824 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 end - attribute \src "libresoc.v:170855.3-170856.67" - process $proc$libresoc.v:170855$9825 + attribute \src "libresoc.v:172487.3-172488.67" + process $proc$libresoc.v:172487$9873 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9826 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9826 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 end - attribute \src "libresoc.v:170857.3-170858.73" - process $proc$libresoc.v:170857$9827 + attribute \src "libresoc.v:172489.3-172490.73" + process $proc$libresoc.v:172489$9875 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9828 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9828 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 end - attribute \src "libresoc.v:170859.3-170860.65" - process $proc$libresoc.v:170859$9829 + attribute \src "libresoc.v:172491.3-172492.65" + process $proc$libresoc.v:172491$9877 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9830 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9830 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 end - attribute \src "libresoc.v:170861.3-170862.67" - process $proc$libresoc.v:170861$9831 + attribute \src "libresoc.v:172493.3-172494.67" + process $proc$libresoc.v:172493$9879 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9832 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9832 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 end - attribute \src "libresoc.v:170863.3-170864.65" - process $proc$libresoc.v:170863$9833 + attribute \src "libresoc.v:172495.3-172496.65" + process $proc$libresoc.v:172495$9881 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9834 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9834 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 end - attribute \src "libresoc.v:170865.3-170866.57" - process $proc$libresoc.v:170865$9835 + attribute \src "libresoc.v:172497.3-172498.57" + process $proc$libresoc.v:172497$9883 assign { } { } - assign $0\logical_op__insn$19[31:0]$9836 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9836 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 end - attribute \src "libresoc.v:170867.3-170868.33" - process $proc$libresoc.v:170867$9837 + attribute \src "libresoc.v:172499.3-172500.33" + process $proc$libresoc.v:172499$9885 assign { } { } - assign $0\muxid$1[1:0]$9838 \muxid$1$next + assign $0\muxid$1[1:0]$9886 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9838 + update \muxid$1 $0\muxid$1[1:0]$9886 end - attribute \src "libresoc.v:170869.3-170870.29" - process $proc$libresoc.v:170869$9839 + attribute \src "libresoc.v:172501.3-172502.29" + process $proc$libresoc.v:172501$9887 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170985.3-171003.6" - process $proc$libresoc.v:170985$9840 + attribute \src "libresoc.v:172617.3-172635.6" + process $proc$libresoc.v:172617$9888 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9841 $1\o$next[63:0]$9843 + assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 assign { } { } - assign $0\o_ok$next[0:0]$9842 $2\o_ok$next[0:0]$9845 - attribute \src "libresoc.v:170986.5-170986.29" + assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172618.5-172618.29" switch \initial - attribute \src "libresoc.v:170986.9-170986.17" + attribute \src "libresoc.v:172618.9-172618.17" case 1'1 case end @@ -351278,41 +353775,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9843 \o - assign $1\o_ok$next[0:0]$9844 \o_ok + assign $1\o$next[63:0]$9891 \o + assign $1\o_ok$next[0:0]$9892 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9845 1'0 + assign $2\o_ok$next[0:0]$9893 1'0 case - assign $2\o_ok$next[0:0]$9845 $1\o_ok$next[0:0]$9844 + assign $2\o_ok$next[0:0]$9893 $1\o_ok$next[0:0]$9892 end sync always - update \o$next $0\o$next[63:0]$9841 - update \o_ok$next $0\o_ok$next[0:0]$9842 + update \o$next $0\o$next[63:0]$9889 + update \o_ok$next $0\o_ok$next[0:0]$9890 end - attribute \src "libresoc.v:171004.3-171022.6" - process $proc$libresoc.v:171004$9846 + attribute \src "libresoc.v:172636.3-172654.6" + process $proc$libresoc.v:172636$9894 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9847 $1\cr_a$next[3:0]$9849 + assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 assign { } { } - assign $0\cr_a_ok$next[0:0]$9848 $2\cr_a_ok$next[0:0]$9851 - attribute \src "libresoc.v:171005.5-171005.29" + assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172637.5-172637.29" switch \initial - attribute \src "libresoc.v:171005.9-171005.17" + attribute \src "libresoc.v:172637.9-172637.17" case 1'1 case end @@ -351322,41 +353819,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9849 \cr_a - assign $1\cr_a_ok$next[0:0]$9850 \cr_a_ok + assign $1\cr_a$next[3:0]$9897 \cr_a + assign $1\cr_a_ok$next[0:0]$9898 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9851 1'0 + assign $2\cr_a_ok$next[0:0]$9899 1'0 case - assign $2\cr_a_ok$next[0:0]$9851 $1\cr_a_ok$next[0:0]$9850 + assign $2\cr_a_ok$next[0:0]$9899 $1\cr_a_ok$next[0:0]$9898 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9847 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9848 + update \cr_a$next $0\cr_a$next[3:0]$9895 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 end - attribute \src "libresoc.v:171023.3-171041.6" - process $proc$libresoc.v:171023$9852 + attribute \src "libresoc.v:172655.3-172673.6" + process $proc$libresoc.v:172655$9900 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9853 $1\xer_ov$next[1:0]$9855 + assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9854 $2\xer_ov_ok$next[0:0]$9857 - attribute \src "libresoc.v:171024.5-171024.29" + assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172656.5-172656.29" switch \initial - attribute \src "libresoc.v:171024.9-171024.17" + attribute \src "libresoc.v:172656.9-172656.17" case 1'1 case end @@ -351366,41 +353863,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9855 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9856 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9903 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9904 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9857 1'0 + assign $2\xer_ov_ok$next[0:0]$9905 1'0 case - assign $2\xer_ov_ok$next[0:0]$9857 $1\xer_ov_ok$next[0:0]$9856 + assign $2\xer_ov_ok$next[0:0]$9905 $1\xer_ov_ok$next[0:0]$9904 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9853 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9854 + update \xer_ov$next $0\xer_ov$next[1:0]$9901 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 end - attribute \src "libresoc.v:171042.3-171060.6" - process $proc$libresoc.v:171042$9858 + attribute \src "libresoc.v:172674.3-172692.6" + process $proc$libresoc.v:172674$9906 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9860 $1\xer_so$20$next[0:0]$9862 - assign $0\xer_so_ok$next[0:0]$9859 $2\xer_so_ok$next[0:0]$9863 - attribute \src "libresoc.v:171043.5-171043.29" + assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 + assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172675.5-172675.29" switch \initial - attribute \src "libresoc.v:171043.9-171043.17" + attribute \src "libresoc.v:172675.9-172675.17" case 1'1 case end @@ -351410,38 +353907,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9861 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9862 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9909 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9910 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9863 1'0 + assign $2\xer_so_ok$next[0:0]$9911 1'0 case - assign $2\xer_so_ok$next[0:0]$9863 $1\xer_so_ok$next[0:0]$9861 + assign $2\xer_so_ok$next[0:0]$9911 $1\xer_so_ok$next[0:0]$9909 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9859 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9860 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 end - attribute \src "libresoc.v:171061.3-171078.6" - process $proc$libresoc.v:171061$9864 + attribute \src "libresoc.v:172693.3-172710.6" + process $proc$libresoc.v:172693$9912 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9865 $2\r_busy$next[0:0]$9867 - attribute \src "libresoc.v:171062.5-171062.29" + assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172694.5-172694.29" switch \initial - attribute \src "libresoc.v:171062.9-171062.17" + attribute \src "libresoc.v:172694.9-172694.17" case 1'1 case end @@ -351450,34 +353947,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9866 1'1 + assign $1\r_busy$next[0:0]$9914 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9866 1'0 + assign $1\r_busy$next[0:0]$9914 1'0 case - assign $1\r_busy$next[0:0]$9866 \r_busy + assign $1\r_busy$next[0:0]$9914 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9867 1'0 + assign $2\r_busy$next[0:0]$9915 1'0 case - assign $2\r_busy$next[0:0]$9867 $1\r_busy$next[0:0]$9866 + assign $2\r_busy$next[0:0]$9915 $1\r_busy$next[0:0]$9914 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9865 + update \r_busy$next $0\r_busy$next[0:0]$9913 end - attribute \src "libresoc.v:171079.3-171091.6" - process $proc$libresoc.v:171079$9868 + attribute \src "libresoc.v:172711.3-172723.6" + process $proc$libresoc.v:172711$9916 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9869 $1\muxid$1$next[1:0]$9870 - attribute \src "libresoc.v:171080.5-171080.29" + assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172712.5-172712.29" switch \initial - attribute \src "libresoc.v:171080.9-171080.17" + attribute \src "libresoc.v:172712.9-172712.17" case 1'1 case end @@ -351486,19 +353983,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9870 \muxid$76 + assign $1\muxid$1$next[1:0]$9918 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9870 \muxid$76 + assign $1\muxid$1$next[1:0]$9918 \muxid$76 case - assign $1\muxid$1$next[1:0]$9870 \muxid$1 + assign $1\muxid$1$next[1:0]$9918 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9869 + update \muxid$1$next $0\muxid$1$next[1:0]$9917 end - attribute \src "libresoc.v:171092.3-171133.6" - process $proc$libresoc.v:171092$9871 + attribute \src "libresoc.v:172724.3-172765.6" + process $proc$libresoc.v:172724$9919 assign { } { } assign { } { } assign { } { } @@ -351535,33 +354032,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9872 $1\logical_op__data_len$18$next[3:0]$9890 - assign $0\logical_op__fn_unit$3$next[13:0]$9873 $1\logical_op__fn_unit$3$next[13:0]$9891 + assign $0\logical_op__data_len$18$next[3:0]$9920 $1\logical_op__data_len$18$next[3:0]$9938 + assign $0\logical_op__fn_unit$3$next[13:0]$9921 $1\logical_op__fn_unit$3$next[13:0]$9939 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9876 $1\logical_op__input_carry$12$next[1:0]$9894 - assign $0\logical_op__insn$19$next[31:0]$9877 $1\logical_op__insn$19$next[31:0]$9895 - assign $0\logical_op__insn_type$2$next[6:0]$9878 $1\logical_op__insn_type$2$next[6:0]$9896 - assign $0\logical_op__invert_in$10$next[0:0]$9879 $1\logical_op__invert_in$10$next[0:0]$9897 - assign $0\logical_op__invert_out$13$next[0:0]$9880 $1\logical_op__invert_out$13$next[0:0]$9898 - assign $0\logical_op__is_32bit$16$next[0:0]$9881 $1\logical_op__is_32bit$16$next[0:0]$9899 - assign $0\logical_op__is_signed$17$next[0:0]$9882 $1\logical_op__is_signed$17$next[0:0]$9900 + assign $0\logical_op__input_carry$12$next[1:0]$9924 $1\logical_op__input_carry$12$next[1:0]$9942 + assign $0\logical_op__insn$19$next[31:0]$9925 $1\logical_op__insn$19$next[31:0]$9943 + assign $0\logical_op__insn_type$2$next[6:0]$9926 $1\logical_op__insn_type$2$next[6:0]$9944 + assign $0\logical_op__invert_in$10$next[0:0]$9927 $1\logical_op__invert_in$10$next[0:0]$9945 + assign $0\logical_op__invert_out$13$next[0:0]$9928 $1\logical_op__invert_out$13$next[0:0]$9946 + assign $0\logical_op__is_32bit$16$next[0:0]$9929 $1\logical_op__is_32bit$16$next[0:0]$9947 + assign $0\logical_op__is_signed$17$next[0:0]$9930 $1\logical_op__is_signed$17$next[0:0]$9948 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9885 $1\logical_op__output_carry$15$next[0:0]$9903 + assign $0\logical_op__output_carry$15$next[0:0]$9933 $1\logical_op__output_carry$15$next[0:0]$9951 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9888 $1\logical_op__write_cr0$14$next[0:0]$9906 - assign $0\logical_op__zero_a$11$next[0:0]$9889 $1\logical_op__zero_a$11$next[0:0]$9907 - assign $0\logical_op__imm_data__data$4$next[63:0]$9874 $2\logical_op__imm_data__data$4$next[63:0]$9908 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9875 $2\logical_op__imm_data__ok$5$next[0:0]$9909 - assign $0\logical_op__oe__oe$8$next[0:0]$9883 $2\logical_op__oe__oe$8$next[0:0]$9910 - assign $0\logical_op__oe__ok$9$next[0:0]$9884 $2\logical_op__oe__ok$9$next[0:0]$9911 - assign $0\logical_op__rc__ok$7$next[0:0]$9886 $2\logical_op__rc__ok$7$next[0:0]$9912 - assign $0\logical_op__rc__rc$6$next[0:0]$9887 $2\logical_op__rc__rc$6$next[0:0]$9913 - attribute \src "libresoc.v:171093.5-171093.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9936 $1\logical_op__write_cr0$14$next[0:0]$9954 + assign $0\logical_op__zero_a$11$next[0:0]$9937 $1\logical_op__zero_a$11$next[0:0]$9955 + assign $0\logical_op__imm_data__data$4$next[63:0]$9922 $2\logical_op__imm_data__data$4$next[63:0]$9956 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9923 $2\logical_op__imm_data__ok$5$next[0:0]$9957 + assign $0\logical_op__oe__oe$8$next[0:0]$9931 $2\logical_op__oe__oe$8$next[0:0]$9958 + assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 + assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 + assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172725.5-172725.29" switch \initial - attribute \src "libresoc.v:171093.9-171093.17" + attribute \src "libresoc.v:172725.9-172725.17" case 1'1 case end @@ -351587,7 +354084,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -351608,26 +354105,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9890 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$9891 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9892 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9893 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9894 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9895 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9896 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9897 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9898 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9899 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9900 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9901 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9902 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9903 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9904 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9905 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9906 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9907 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9938 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9939 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9940 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9941 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9942 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9943 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9944 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9945 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9946 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9947 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9948 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9949 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9950 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9951 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9952 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9953 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9954 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9955 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -351639,41 +354136,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9908 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9913 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9912 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9910 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9911 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9908 $1\logical_op__imm_data__data$4$next[63:0]$9892 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 $1\logical_op__imm_data__ok$5$next[0:0]$9893 - assign $2\logical_op__oe__oe$8$next[0:0]$9910 $1\logical_op__oe__oe$8$next[0:0]$9901 - assign $2\logical_op__oe__ok$9$next[0:0]$9911 $1\logical_op__oe__ok$9$next[0:0]$9902 - assign $2\logical_op__rc__ok$7$next[0:0]$9912 $1\logical_op__rc__ok$7$next[0:0]$9904 - assign $2\logical_op__rc__rc$6$next[0:0]$9913 $1\logical_op__rc__rc$6$next[0:0]$9905 + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 $1\logical_op__imm_data__data$4$next[63:0]$9940 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 $1\logical_op__imm_data__ok$5$next[0:0]$9941 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 $1\logical_op__oe__oe$8$next[0:0]$9949 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 $1\logical_op__oe__ok$9$next[0:0]$9950 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 $1\logical_op__rc__ok$7$next[0:0]$9952 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 $1\logical_op__rc__rc$6$next[0:0]$9953 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9872 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9873 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9874 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9875 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9876 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9877 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9878 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9879 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9880 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9881 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9882 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9883 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9884 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9885 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9886 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9887 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9888 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9889 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9920 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9921 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9922 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9923 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9924 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9925 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9926 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9927 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9928 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9929 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9930 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9931 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9932 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9933 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9934 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9935 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 end - connect \$74 $and$libresoc.v:170814$9791_Y + connect \$74 $and$libresoc.v:172446$9839_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -351707,381 +354204,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:171170.1-172157.10" +attribute \src "libresoc.v:172802.1-173789.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:172082.3-172096.6" - wire $0\div_by_zero$54$next[0:0]$10142 - attribute \src "libresoc.v:171193.7-171193.30" - wire $0\div_by_zero$54[0:0]$10159 - attribute \src "libresoc.v:171756.3-171757.47" - wire $0\div_by_zero$54[0:0]$9977 - attribute \src "libresoc.v:171878.3-171889.6" + attribute \src "libresoc.v:173714.3-173728.6" + wire $0\div_by_zero$54$next[0:0]$10190 + attribute \src "libresoc.v:173388.3-173389.47" + wire $0\div_by_zero$54[0:0]$10025 + attribute \src "libresoc.v:172825.7-172825.30" + wire $0\div_by_zero$54[0:0]$10207 + attribute \src "libresoc.v:173510.3-173521.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171866.3-171877.6" + attribute \src "libresoc.v:173498.3-173509.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171854.3-171865.6" + attribute \src "libresoc.v:173486.3-173497.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:172052.3-172066.6" - wire $0\dive_abs_ov32$52$next[0:0]$10134 - attribute \src "libresoc.v:171217.7-171217.32" - wire $0\dive_abs_ov32$52[0:0]$10161 - attribute \src "libresoc.v:171760.3-171761.51" - wire $0\dive_abs_ov32$52[0:0]$9981 - attribute \src "libresoc.v:172067.3-172081.6" - wire $0\dive_abs_ov64$53$next[0:0]$10138 - attribute \src "libresoc.v:171225.7-171225.32" - wire $0\dive_abs_ov64$53[0:0]$10163 - attribute \src "libresoc.v:171758.3-171759.51" - wire $0\dive_abs_ov64$53[0:0]$9979 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $0\dividend$68$next[127:0]$10146 - attribute \src "libresoc.v:171231.15-171231.68" - wire width 128 $0\dividend$68[127:0]$10165 - attribute \src "libresoc.v:171754.3-171755.41" - wire width 128 $0\dividend$68[127:0]$9975 - attribute \src "libresoc.v:172037.3-172051.6" - wire $0\dividend_neg$51$next[0:0]$10130 - attribute \src "libresoc.v:171239.7-171239.31" - wire $0\dividend_neg$51[0:0]$10167 - attribute \src "libresoc.v:171762.3-171763.49" - wire $0\dividend_neg$51[0:0]$9983 - attribute \src "libresoc.v:172022.3-172036.6" - wire $0\divisor_neg$50$next[0:0]$10126 - attribute \src "libresoc.v:171247.7-171247.30" - wire $0\divisor_neg$50[0:0]$10169 - attribute \src "libresoc.v:171764.3-171765.47" - wire $0\divisor_neg$50[0:0]$9985 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10150 - attribute \src "libresoc.v:171253.14-171253.58" - wire width 64 $0\divisor_radicand$65[63:0]$10171 - attribute \src "libresoc.v:171752.3-171753.57" - wire width 64 $0\divisor_radicand$65[63:0]$9973 - attribute \src "libresoc.v:171890.3-171917.6" - wire $0\empty$next[0:0]$10043 - attribute \src "libresoc.v:171810.3-171811.27" + attribute \src "libresoc.v:173684.3-173698.6" + wire $0\dive_abs_ov32$52$next[0:0]$10182 + attribute \src "libresoc.v:173392.3-173393.51" + wire $0\dive_abs_ov32$52[0:0]$10029 + attribute \src "libresoc.v:172849.7-172849.32" + wire $0\dive_abs_ov32$52[0:0]$10209 + attribute \src "libresoc.v:173699.3-173713.6" + wire $0\dive_abs_ov64$53$next[0:0]$10186 + attribute \src "libresoc.v:173390.3-173391.51" + wire $0\dive_abs_ov64$53[0:0]$10027 + attribute \src "libresoc.v:172857.7-172857.32" + wire $0\dive_abs_ov64$53[0:0]$10211 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $0\dividend$68$next[127:0]$10194 + attribute \src "libresoc.v:173386.3-173387.41" + wire width 128 $0\dividend$68[127:0]$10023 + attribute \src "libresoc.v:172863.15-172863.68" + wire width 128 $0\dividend$68[127:0]$10213 + attribute \src "libresoc.v:173669.3-173683.6" + wire $0\dividend_neg$51$next[0:0]$10178 + attribute \src "libresoc.v:173394.3-173395.49" + wire $0\dividend_neg$51[0:0]$10031 + attribute \src "libresoc.v:172871.7-172871.31" + wire $0\dividend_neg$51[0:0]$10215 + attribute \src "libresoc.v:173654.3-173668.6" + wire $0\divisor_neg$50$next[0:0]$10174 + attribute \src "libresoc.v:173396.3-173397.47" + wire $0\divisor_neg$50[0:0]$10033 + attribute \src "libresoc.v:172879.7-172879.30" + wire $0\divisor_neg$50[0:0]$10217 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10198 + attribute \src "libresoc.v:173384.3-173385.57" + wire width 64 $0\divisor_radicand$65[63:0]$10021 + attribute \src "libresoc.v:172885.14-172885.58" + wire width 64 $0\divisor_radicand$65[63:0]$10219 + attribute \src "libresoc.v:173522.3-173549.6" + wire $0\empty$next[0:0]$10091 + attribute \src "libresoc.v:173442.3-173443.27" wire $0\empty[0:0] - attribute \src "libresoc.v:171171.7-171171.20" + attribute \src "libresoc.v:172803.7-172803.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10053 - attribute \src "libresoc.v:171804.3-171805.65" - wire width 4 $0\logical_op__data_len$45[3:0]$10025 - attribute \src "libresoc.v:171265.13-171265.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10174 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10054 - attribute \src "libresoc.v:171318.14-171318.49" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10176 - attribute \src "libresoc.v:171774.3-171775.63" - wire width 14 $0\logical_op__fn_unit$30[13:0]$9995 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10055 - attribute \src "libresoc.v:171324.14-171324.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10178 - attribute \src "libresoc.v:171776.3-171777.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9997 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10056 - attribute \src "libresoc.v:171332.7-171332.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10180 - attribute \src "libresoc.v:171778.3-171779.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9999 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10057 - attribute \src "libresoc.v:171792.3-171793.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$10013 - attribute \src "libresoc.v:171354.13-171354.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10182 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10058 - attribute \src "libresoc.v:171806.3-171807.57" - wire width 32 $0\logical_op__insn$46[31:0]$10027 - attribute \src "libresoc.v:171362.14-171362.43" - wire width 32 $0\logical_op__insn$46[31:0]$10184 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10059 - attribute \src "libresoc.v:171595.13-171595.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10186 - attribute \src "libresoc.v:171772.3-171773.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9993 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__invert_in$37$next[0:0]$10060 - attribute \src "libresoc.v:171788.3-171789.67" - wire $0\logical_op__invert_in$37[0:0]$10009 - attribute \src "libresoc.v:171603.7-171603.40" - wire $0\logical_op__invert_in$37[0:0]$10188 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__invert_out$40$next[0:0]$10061 - attribute \src "libresoc.v:171794.3-171795.69" - wire $0\logical_op__invert_out$40[0:0]$10015 - attribute \src "libresoc.v:171611.7-171611.41" - wire $0\logical_op__invert_out$40[0:0]$10190 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10062 - attribute \src "libresoc.v:171800.3-171801.65" - wire $0\logical_op__is_32bit$43[0:0]$10021 - attribute \src "libresoc.v:171619.7-171619.39" - wire $0\logical_op__is_32bit$43[0:0]$10192 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__is_signed$44$next[0:0]$10063 - attribute \src "libresoc.v:171802.3-171803.67" - wire $0\logical_op__is_signed$44[0:0]$10023 - attribute \src "libresoc.v:171627.7-171627.40" - wire $0\logical_op__is_signed$44[0:0]$10194 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10064 - attribute \src "libresoc.v:171784.3-171785.61" - wire $0\logical_op__oe__oe$35[0:0]$10005 - attribute \src "libresoc.v:171633.7-171633.37" - wire $0\logical_op__oe__oe$35[0:0]$10196 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10065 - attribute \src "libresoc.v:171786.3-171787.61" - wire $0\logical_op__oe__ok$36[0:0]$10007 - attribute \src "libresoc.v:171641.7-171641.37" - wire $0\logical_op__oe__ok$36[0:0]$10198 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__output_carry$42$next[0:0]$10066 - attribute \src "libresoc.v:171798.3-171799.73" - wire $0\logical_op__output_carry$42[0:0]$10019 - attribute \src "libresoc.v:171651.7-171651.43" - wire $0\logical_op__output_carry$42[0:0]$10200 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10067 - attribute \src "libresoc.v:171782.3-171783.61" - wire $0\logical_op__rc__ok$34[0:0]$10003 - attribute \src "libresoc.v:171657.7-171657.37" - wire $0\logical_op__rc__ok$34[0:0]$10202 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10068 - attribute \src "libresoc.v:171780.3-171781.61" - wire $0\logical_op__rc__rc$33[0:0]$10001 - attribute \src "libresoc.v:171665.7-171665.37" - wire $0\logical_op__rc__rc$33[0:0]$10204 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10069 - attribute \src "libresoc.v:171796.3-171797.67" - wire $0\logical_op__write_cr0$41[0:0]$10017 - attribute \src "libresoc.v:171675.7-171675.40" - wire $0\logical_op__write_cr0$41[0:0]$10206 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__zero_a$38$next[0:0]$10070 - attribute \src "libresoc.v:171790.3-171791.61" - wire $0\logical_op__zero_a$38[0:0]$10011 - attribute \src "libresoc.v:171683.7-171683.37" - wire $0\logical_op__zero_a$38[0:0]$10208 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $0\muxid$28$next[1:0]$10049 - attribute \src "libresoc.v:171808.3-171809.35" - wire width 2 $0\muxid$28[1:0]$10029 - attribute \src "libresoc.v:171691.13-171691.30" - wire width 2 $0\muxid$28[1:0]$10210 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $0\operation$69$next[1:0]$10154 - attribute \src "libresoc.v:171701.13-171701.34" - wire width 2 $0\operation$69[1:0]$10212 - attribute \src "libresoc.v:171750.3-171751.43" - wire width 2 $0\operation$69[1:0]$9971 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $0\ra$47$next[63:0]$10114 - attribute \src "libresoc.v:171715.14-171715.44" - wire width 64 $0\ra$47[63:0]$10214 - attribute \src "libresoc.v:171770.3-171771.29" - wire width 64 $0\ra$47[63:0]$9991 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $0\rb$48$next[63:0]$10118 - attribute \src "libresoc.v:171723.14-171723.44" - wire width 64 $0\rb$48[63:0]$10216 - attribute \src "libresoc.v:171768.3-171769.29" - wire width 64 $0\rb$48[63:0]$9989 - attribute \src "libresoc.v:171845.3-171853.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10037 - attribute \src "libresoc.v:171812.3-171813.75" + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 + attribute \src "libresoc.v:173436.3-173437.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10073 + attribute \src "libresoc.v:172897.13-172897.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10222 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 + attribute \src "libresoc.v:173406.3-173407.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 + attribute \src "libresoc.v:172950.14-172950.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 + attribute \src "libresoc.v:173408.3-173409.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 + attribute \src "libresoc.v:172956.14-172956.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 + attribute \src "libresoc.v:173410.3-173411.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10047 + attribute \src "libresoc.v:172964.7-172964.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10228 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 + attribute \src "libresoc.v:173424.3-173425.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10061 + attribute \src "libresoc.v:172986.13-172986.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10230 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10106 + attribute \src "libresoc.v:173438.3-173439.57" + wire width 32 $0\logical_op__insn$46[31:0]$10075 + attribute \src "libresoc.v:172994.14-172994.43" + wire width 32 $0\logical_op__insn$46[31:0]$10232 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 + attribute \src "libresoc.v:173404.3-173405.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10041 + attribute \src "libresoc.v:173227.13-173227.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10234 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_in$37$next[0:0]$10108 + attribute \src "libresoc.v:173420.3-173421.67" + wire $0\logical_op__invert_in$37[0:0]$10057 + attribute \src "libresoc.v:173235.7-173235.40" + wire $0\logical_op__invert_in$37[0:0]$10236 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_out$40$next[0:0]$10109 + attribute \src "libresoc.v:173426.3-173427.69" + wire $0\logical_op__invert_out$40[0:0]$10063 + attribute \src "libresoc.v:173243.7-173243.41" + wire $0\logical_op__invert_out$40[0:0]$10238 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10110 + attribute \src "libresoc.v:173432.3-173433.65" + wire $0\logical_op__is_32bit$43[0:0]$10069 + attribute \src "libresoc.v:173251.7-173251.39" + wire $0\logical_op__is_32bit$43[0:0]$10240 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_signed$44$next[0:0]$10111 + attribute \src "libresoc.v:173434.3-173435.67" + wire $0\logical_op__is_signed$44[0:0]$10071 + attribute \src "libresoc.v:173259.7-173259.40" + wire $0\logical_op__is_signed$44[0:0]$10242 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10112 + attribute \src "libresoc.v:173416.3-173417.61" + wire $0\logical_op__oe__oe$35[0:0]$10053 + attribute \src "libresoc.v:173265.7-173265.37" + wire $0\logical_op__oe__oe$35[0:0]$10244 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10113 + attribute \src "libresoc.v:173418.3-173419.61" + wire $0\logical_op__oe__ok$36[0:0]$10055 + attribute \src "libresoc.v:173273.7-173273.37" + wire $0\logical_op__oe__ok$36[0:0]$10246 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__output_carry$42$next[0:0]$10114 + attribute \src "libresoc.v:173430.3-173431.73" + wire $0\logical_op__output_carry$42[0:0]$10067 + attribute \src "libresoc.v:173283.7-173283.43" + wire $0\logical_op__output_carry$42[0:0]$10248 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10115 + attribute \src "libresoc.v:173414.3-173415.61" + wire $0\logical_op__rc__ok$34[0:0]$10051 + attribute \src "libresoc.v:173289.7-173289.37" + wire $0\logical_op__rc__ok$34[0:0]$10250 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10116 + attribute \src "libresoc.v:173412.3-173413.61" + wire $0\logical_op__rc__rc$33[0:0]$10049 + attribute \src "libresoc.v:173297.7-173297.37" + wire $0\logical_op__rc__rc$33[0:0]$10252 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10117 + attribute \src "libresoc.v:173428.3-173429.67" + wire $0\logical_op__write_cr0$41[0:0]$10065 + attribute \src "libresoc.v:173307.7-173307.40" + wire $0\logical_op__write_cr0$41[0:0]$10254 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__zero_a$38$next[0:0]$10118 + attribute \src "libresoc.v:173422.3-173423.61" + wire $0\logical_op__zero_a$38[0:0]$10059 + attribute \src "libresoc.v:173315.7-173315.37" + wire $0\logical_op__zero_a$38[0:0]$10256 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $0\muxid$28$next[1:0]$10097 + attribute \src "libresoc.v:173440.3-173441.35" + wire width 2 $0\muxid$28[1:0]$10077 + attribute \src "libresoc.v:173323.13-173323.30" + wire width 2 $0\muxid$28[1:0]$10258 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $0\operation$69$next[1:0]$10202 + attribute \src "libresoc.v:173382.3-173383.43" + wire width 2 $0\operation$69[1:0]$10019 + attribute \src "libresoc.v:173333.13-173333.34" + wire width 2 $0\operation$69[1:0]$10260 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $0\ra$47$next[63:0]$10162 + attribute \src "libresoc.v:173402.3-173403.29" + wire width 64 $0\ra$47[63:0]$10039 + attribute \src "libresoc.v:173347.14-173347.44" + wire width 64 $0\ra$47[63:0]$10262 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $0\rb$48$next[63:0]$10166 + attribute \src "libresoc.v:173400.3-173401.29" + wire width 64 $0\rb$48[63:0]$10037 + attribute \src "libresoc.v:173355.14-173355.44" + wire width 64 $0\rb$48[63:0]$10264 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 + attribute \src "libresoc.v:173444.3-173445.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:171836.3-171844.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$10034 - attribute \src "libresoc.v:171814.3-171815.65" + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 + attribute \src "libresoc.v:173446.3-173447.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:172007.3-172021.6" - wire $0\xer_so$49$next[0:0]$10122 - attribute \src "libresoc.v:171741.7-171741.25" - wire $0\xer_so$49[0:0]$10220 - attribute \src "libresoc.v:171766.3-171767.37" - wire $0\xer_so$49[0:0]$9987 - attribute \src "libresoc.v:172082.3-172096.6" - wire $1\div_by_zero$54$next[0:0]$10143 - attribute \src "libresoc.v:171878.3-171889.6" + attribute \src "libresoc.v:173639.3-173653.6" + wire $0\xer_so$49$next[0:0]$10170 + attribute \src "libresoc.v:173398.3-173399.37" + wire $0\xer_so$49[0:0]$10035 + attribute \src "libresoc.v:173373.7-173373.25" + wire $0\xer_so$49[0:0]$10268 + attribute \src "libresoc.v:173714.3-173728.6" + wire $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173510.3-173521.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171866.3-171877.6" + attribute \src "libresoc.v:173498.3-173509.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171854.3-171865.6" + attribute \src "libresoc.v:173486.3-173497.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:172052.3-172066.6" - wire $1\dive_abs_ov32$52$next[0:0]$10135 - attribute \src "libresoc.v:172067.3-172081.6" - wire $1\dive_abs_ov64$53$next[0:0]$10139 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $1\dividend$68$next[127:0]$10147 - attribute \src "libresoc.v:172037.3-172051.6" - wire $1\dividend_neg$51$next[0:0]$10131 - attribute \src "libresoc.v:172022.3-172036.6" - wire $1\divisor_neg$50$next[0:0]$10127 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10151 - attribute \src "libresoc.v:171890.3-171917.6" - wire $1\empty$next[0:0]$10044 - attribute \src "libresoc.v:171257.7-171257.19" + attribute \src "libresoc.v:173684.3-173698.6" + wire $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173699.3-173713.6" + wire $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173669.3-173683.6" + wire $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173654.3-173668.6" + wire $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173522.3-173549.6" + wire $1\empty$next[0:0]$10092 + attribute \src "libresoc.v:172889.7-172889.19" wire $1\empty[0:0] - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10071 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10072 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10073 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10074 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10075 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10076 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10077 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__invert_in$37$next[0:0]$10078 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__invert_out$40$next[0:0]$10079 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10080 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__is_signed$44$next[0:0]$10081 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10082 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10083 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__output_carry$42$next[0:0]$10084 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10085 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10086 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10087 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__zero_a$38$next[0:0]$10088 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $1\muxid$28$next[1:0]$10050 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $1\operation$69$next[1:0]$10155 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $1\ra$47$next[63:0]$10115 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $1\rb$48$next[63:0]$10119 - attribute \src "libresoc.v:171845.3-171853.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10038 - attribute \src "libresoc.v:171729.15-171729.84" + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10124 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_in$37$next[0:0]$10126 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_out$40$next[0:0]$10127 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10128 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_signed$44$next[0:0]$10129 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10130 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10131 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__output_carry$42$next[0:0]$10132 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10133 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10134 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10135 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__zero_a$38$next[0:0]$10136 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173361.15-173361.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:171836.3-171844.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$10035 - attribute \src "libresoc.v:171733.13-171733.45" + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173365.13-173365.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:172007.3-172021.6" - wire $1\xer_so$49$next[0:0]$10123 - attribute \src "libresoc.v:172082.3-172096.6" - wire $2\div_by_zero$54$next[0:0]$10144 - attribute \src "libresoc.v:172052.3-172066.6" - wire $2\dive_abs_ov32$52$next[0:0]$10136 - attribute \src "libresoc.v:172067.3-172081.6" - wire $2\dive_abs_ov64$53$next[0:0]$10140 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $2\dividend$68$next[127:0]$10148 - attribute \src "libresoc.v:172037.3-172051.6" - wire $2\dividend_neg$51$next[0:0]$10132 - attribute \src "libresoc.v:172022.3-172036.6" - wire $2\divisor_neg$50$next[0:0]$10128 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10152 - attribute \src "libresoc.v:171890.3-171917.6" - wire $2\empty$next[0:0]$10045 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10089 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10090 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10091 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10092 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$10093 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$10094 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$10095 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__invert_in$37$next[0:0]$10096 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__invert_out$40$next[0:0]$10097 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__is_32bit$43$next[0:0]$10098 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__is_signed$44$next[0:0]$10099 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__oe__oe$35$next[0:0]$10100 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__oe__ok$36$next[0:0]$10101 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__output_carry$42$next[0:0]$10102 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__rc__ok$34$next[0:0]$10103 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__rc__rc$33$next[0:0]$10104 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__write_cr0$41$next[0:0]$10105 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__zero_a$38$next[0:0]$10106 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $2\muxid$28$next[1:0]$10051 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $2\operation$69$next[1:0]$10156 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $2\ra$47$next[63:0]$10116 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $2\rb$48$next[63:0]$10120 - attribute \src "libresoc.v:172007.3-172021.6" - wire $2\xer_so$49$next[0:0]$10124 - attribute \src "libresoc.v:171890.3-171917.6" - wire $3\empty$next[0:0]$10046 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10107 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$10108 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__oe__oe$35$next[0:0]$10109 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__oe__ok$36$next[0:0]$10110 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__rc__ok$34$next[0:0]$10111 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__rc__rc$33$next[0:0]$10112 - attribute \src "libresoc.v:171890.3-171917.6" - wire $4\empty$next[0:0]$10047 - attribute \src "libresoc.v:171748.18-171748.98" - wire $and$libresoc.v:171748$9968_Y - attribute \src "libresoc.v:171749.18-171749.107" - wire $and$libresoc.v:171749$9969_Y - attribute \src "libresoc.v:171745.18-171745.92" - wire width 192 $extend$libresoc.v:171745$9964_Y - attribute \src "libresoc.v:171747.18-171747.119" - wire $ge$libresoc.v:171747$9967_Y - attribute \src "libresoc.v:171746.18-171746.93" - wire $not$libresoc.v:171746$9966_Y - attribute \src "libresoc.v:171745.18-171745.92" - wire width 192 $pos$libresoc.v:171745$9965_Y - attribute \src "libresoc.v:171744.18-171744.138" - wire width 191 $sshl$libresoc.v:171744$9963_Y + attribute \src "libresoc.v:173639.3-173653.6" + wire $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173714.3-173728.6" + wire $2\div_by_zero$54$next[0:0]$10192 + attribute \src "libresoc.v:173684.3-173698.6" + wire $2\dive_abs_ov32$52$next[0:0]$10184 + attribute \src "libresoc.v:173699.3-173713.6" + wire $2\dive_abs_ov64$53$next[0:0]$10188 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $2\dividend$68$next[127:0]$10196 + attribute \src "libresoc.v:173669.3-173683.6" + wire $2\dividend_neg$51$next[0:0]$10180 + attribute \src "libresoc.v:173654.3-173668.6" + wire $2\divisor_neg$50$next[0:0]$10176 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10200 + attribute \src "libresoc.v:173522.3-173549.6" + wire $2\empty$next[0:0]$10093 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10142 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_in$37$next[0:0]$10144 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_out$40$next[0:0]$10145 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10146 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_signed$44$next[0:0]$10147 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10148 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10149 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__output_carry$42$next[0:0]$10150 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10151 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10152 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10153 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__zero_a$38$next[0:0]$10154 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $2\muxid$28$next[1:0]$10099 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $2\operation$69$next[1:0]$10204 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $2\ra$47$next[63:0]$10164 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $2\rb$48$next[63:0]$10168 + attribute \src "libresoc.v:173639.3-173653.6" + wire $2\xer_so$49$next[0:0]$10172 + attribute \src "libresoc.v:173522.3-173549.6" + wire $3\empty$next[0:0]$10094 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10157 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10158 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10159 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173522.3-173549.6" + wire $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173380.18-173380.98" + wire $and$libresoc.v:173380$10016_Y + attribute \src "libresoc.v:173381.18-173381.107" + wire $and$libresoc.v:173381$10017_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $extend$libresoc.v:173377$10012_Y + attribute \src "libresoc.v:173379.18-173379.119" + wire $ge$libresoc.v:173379$10015_Y + attribute \src "libresoc.v:173378.18-173378.93" + wire $not$libresoc.v:173378$10014_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $pos$libresoc.v:173377$10013_Y + attribute \src "libresoc.v:173376.18-173376.138" + wire width 191 $sshl$libresoc.v:173376$10011_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -352094,9 +354591,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -352170,7 +354667,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:171171.7-171171.15" + attribute \src "libresoc.v:172803.7-172803.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -352657,7 +355154,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:171748$9968 + cell $and $and$libresoc.v:173380$10016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352665,10 +355162,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:171748$9968_Y + connect \Y $and$libresoc.v:173380$10016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:171749$9969 + cell $and $and$libresoc.v:173381$10017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352676,18 +355173,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:171749$9969_Y + connect \Y $and$libresoc.v:173381$10017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:171745$9964 + cell $pos $extend$libresoc.v:173377$10012 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:171745$9964_Y + connect \Y $extend$libresoc.v:173377$10012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:171747$9967 + cell $ge $ge$libresoc.v:173379$10015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352695,26 +355192,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:171747$9967_Y + connect \Y $ge$libresoc.v:173379$10015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:171746$9966 + cell $not $not$libresoc.v:173378$10014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:171746$9966_Y + connect \Y $not$libresoc.v:173378$10014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:171745$9965 + cell $pos $pos$libresoc.v:173377$10013 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:171745$9964_Y - connect \Y $pos$libresoc.v:171745$9965_Y + connect \A $extend$libresoc.v:173377$10012_Y + connect \Y $pos$libresoc.v:173377$10013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:171744$9963 + cell $sshl $sshl$libresoc.v:173376$10011 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352722,17 +355219,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:171744$9963_Y + connect \Y $sshl$libresoc.v:173376$10011_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171816.18-171820.4" + attribute \src "libresoc.v:173448.18-173452.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:171821.18-171827.4" + attribute \src "libresoc.v:173453.18-173459.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -352741,528 +355238,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:171828.10-171831.4" + attribute \src "libresoc.v:173460.10-173463.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171832.10-171835.4" + attribute \src "libresoc.v:173464.10-173467.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171171.7-171171.20" - process $proc$libresoc.v:171171$10157 + attribute \src "libresoc.v:172803.7-172803.20" + process $proc$libresoc.v:172803$10205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171193.7-171193.30" - process $proc$libresoc.v:171193$10158 + attribute \src "libresoc.v:172825.7-172825.30" + process $proc$libresoc.v:172825$10206 assign { } { } - assign $0\div_by_zero$54[0:0]$10159 1'0 + assign $0\div_by_zero$54[0:0]$10207 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10159 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 end - attribute \src "libresoc.v:171217.7-171217.32" - process $proc$libresoc.v:171217$10160 + attribute \src "libresoc.v:172849.7-172849.32" + process $proc$libresoc.v:172849$10208 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10161 1'0 + assign $0\dive_abs_ov32$52[0:0]$10209 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10161 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 end - attribute \src "libresoc.v:171225.7-171225.32" - process $proc$libresoc.v:171225$10162 + attribute \src "libresoc.v:172857.7-172857.32" + process $proc$libresoc.v:172857$10210 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10163 1'0 + assign $0\dive_abs_ov64$53[0:0]$10211 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10163 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 end - attribute \src "libresoc.v:171231.15-171231.68" - process $proc$libresoc.v:171231$10164 + attribute \src "libresoc.v:172863.15-172863.68" + process $proc$libresoc.v:172863$10212 assign { } { } - assign $0\dividend$68[127:0]$10165 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$10165 + update \dividend$68 $0\dividend$68[127:0]$10213 end - attribute \src "libresoc.v:171239.7-171239.31" - process $proc$libresoc.v:171239$10166 + attribute \src "libresoc.v:172871.7-172871.31" + process $proc$libresoc.v:172871$10214 assign { } { } - assign $0\dividend_neg$51[0:0]$10167 1'0 + assign $0\dividend_neg$51[0:0]$10215 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10167 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 end - attribute \src "libresoc.v:171247.7-171247.30" - process $proc$libresoc.v:171247$10168 + attribute \src "libresoc.v:172879.7-172879.30" + process $proc$libresoc.v:172879$10216 assign { } { } - assign $0\divisor_neg$50[0:0]$10169 1'0 + assign $0\divisor_neg$50[0:0]$10217 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10169 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 end - attribute \src "libresoc.v:171253.14-171253.58" - process $proc$libresoc.v:171253$10170 + attribute \src "libresoc.v:172885.14-172885.58" + process $proc$libresoc.v:172885$10218 assign { } { } - assign $0\divisor_radicand$65[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10171 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 end - attribute \src "libresoc.v:171257.7-171257.19" - process $proc$libresoc.v:171257$10172 + attribute \src "libresoc.v:172889.7-172889.19" + process $proc$libresoc.v:172889$10220 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:171265.13-171265.45" - process $proc$libresoc.v:171265$10173 + attribute \src "libresoc.v:172897.13-172897.45" + process $proc$libresoc.v:172897$10221 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10174 4'0000 + assign $0\logical_op__data_len$45[3:0]$10222 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10174 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 end - attribute \src "libresoc.v:171318.14-171318.49" - process $proc$libresoc.v:171318$10175 + attribute \src "libresoc.v:172950.14-172950.49" + process $proc$libresoc.v:172950$10223 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10176 14'00000000000000 + assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10176 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 end - attribute \src "libresoc.v:171324.14-171324.68" - process $proc$libresoc.v:171324$10177 + attribute \src "libresoc.v:172956.14-172956.68" + process $proc$libresoc.v:172956$10225 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10178 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 end - attribute \src "libresoc.v:171332.7-171332.43" - process $proc$libresoc.v:171332$10179 + attribute \src "libresoc.v:172964.7-172964.43" + process $proc$libresoc.v:172964$10227 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10180 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10180 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 end - attribute \src "libresoc.v:171354.13-171354.48" - process $proc$libresoc.v:171354$10181 + attribute \src "libresoc.v:172986.13-172986.48" + process $proc$libresoc.v:172986$10229 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10182 2'00 + assign $0\logical_op__input_carry$39[1:0]$10230 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10182 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 end - attribute \src "libresoc.v:171362.14-171362.43" - process $proc$libresoc.v:171362$10183 + attribute \src "libresoc.v:172994.14-172994.43" + process $proc$libresoc.v:172994$10231 assign { } { } - assign $0\logical_op__insn$46[31:0]$10184 0 + assign $0\logical_op__insn$46[31:0]$10232 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10184 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 end - attribute \src "libresoc.v:171595.13-171595.47" - process $proc$libresoc.v:171595$10185 + attribute \src "libresoc.v:173227.13-173227.47" + process $proc$libresoc.v:173227$10233 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10186 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10186 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 end - attribute \src "libresoc.v:171603.7-171603.40" - process $proc$libresoc.v:171603$10187 + attribute \src "libresoc.v:173235.7-173235.40" + process $proc$libresoc.v:173235$10235 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10188 1'0 + assign $0\logical_op__invert_in$37[0:0]$10236 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10188 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 end - attribute \src "libresoc.v:171611.7-171611.41" - process $proc$libresoc.v:171611$10189 + attribute \src "libresoc.v:173243.7-173243.41" + process $proc$libresoc.v:173243$10237 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10190 1'0 + assign $0\logical_op__invert_out$40[0:0]$10238 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10190 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 end - attribute \src "libresoc.v:171619.7-171619.39" - process $proc$libresoc.v:171619$10191 + attribute \src "libresoc.v:173251.7-173251.39" + process $proc$libresoc.v:173251$10239 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10192 1'0 + assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10192 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 end - attribute \src "libresoc.v:171627.7-171627.40" - process $proc$libresoc.v:171627$10193 + attribute \src "libresoc.v:173259.7-173259.40" + process $proc$libresoc.v:173259$10241 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10194 1'0 + assign $0\logical_op__is_signed$44[0:0]$10242 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10194 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 end - attribute \src "libresoc.v:171633.7-171633.37" - process $proc$libresoc.v:171633$10195 + attribute \src "libresoc.v:173265.7-173265.37" + process $proc$libresoc.v:173265$10243 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10196 1'0 + assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10196 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 end - attribute \src "libresoc.v:171641.7-171641.37" - process $proc$libresoc.v:171641$10197 + attribute \src "libresoc.v:173273.7-173273.37" + process $proc$libresoc.v:173273$10245 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10198 1'0 + assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10198 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 end - attribute \src "libresoc.v:171651.7-171651.43" - process $proc$libresoc.v:171651$10199 + attribute \src "libresoc.v:173283.7-173283.43" + process $proc$libresoc.v:173283$10247 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10200 1'0 + assign $0\logical_op__output_carry$42[0:0]$10248 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10200 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 end - attribute \src "libresoc.v:171657.7-171657.37" - process $proc$libresoc.v:171657$10201 + attribute \src "libresoc.v:173289.7-173289.37" + process $proc$libresoc.v:173289$10249 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10202 1'0 + assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10202 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 end - attribute \src "libresoc.v:171665.7-171665.37" - process $proc$libresoc.v:171665$10203 + attribute \src "libresoc.v:173297.7-173297.37" + process $proc$libresoc.v:173297$10251 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10204 1'0 + assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10204 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 end - attribute \src "libresoc.v:171675.7-171675.40" - process $proc$libresoc.v:171675$10205 + attribute \src "libresoc.v:173307.7-173307.40" + process $proc$libresoc.v:173307$10253 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10206 1'0 + assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10206 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 end - attribute \src "libresoc.v:171683.7-171683.37" - process $proc$libresoc.v:171683$10207 + attribute \src "libresoc.v:173315.7-173315.37" + process $proc$libresoc.v:173315$10255 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10208 1'0 + assign $0\logical_op__zero_a$38[0:0]$10256 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10208 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 end - attribute \src "libresoc.v:171691.13-171691.30" - process $proc$libresoc.v:171691$10209 + attribute \src "libresoc.v:173323.13-173323.30" + process $proc$libresoc.v:173323$10257 assign { } { } - assign $0\muxid$28[1:0]$10210 2'00 + assign $0\muxid$28[1:0]$10258 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10210 + update \muxid$28 $0\muxid$28[1:0]$10258 end - attribute \src "libresoc.v:171701.13-171701.34" - process $proc$libresoc.v:171701$10211 + attribute \src "libresoc.v:173333.13-173333.34" + process $proc$libresoc.v:173333$10259 assign { } { } - assign $0\operation$69[1:0]$10212 2'00 + assign $0\operation$69[1:0]$10260 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$10212 + update \operation$69 $0\operation$69[1:0]$10260 end - attribute \src "libresoc.v:171715.14-171715.44" - process $proc$libresoc.v:171715$10213 + attribute \src "libresoc.v:173347.14-173347.44" + process $proc$libresoc.v:173347$10261 assign { } { } - assign $0\ra$47[63:0]$10214 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$10214 + update \ra$47 $0\ra$47[63:0]$10262 end - attribute \src "libresoc.v:171723.14-171723.44" - process $proc$libresoc.v:171723$10215 + attribute \src "libresoc.v:173355.14-173355.44" + process $proc$libresoc.v:173355$10263 assign { } { } - assign $0\rb$48[63:0]$10216 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10216 + update \rb$48 $0\rb$48[63:0]$10264 end - attribute \src "libresoc.v:171729.15-171729.84" - process $proc$libresoc.v:171729$10217 + attribute \src "libresoc.v:173361.15-173361.84" + process $proc$libresoc.v:173361$10265 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:171733.13-171733.45" - process $proc$libresoc.v:171733$10218 + attribute \src "libresoc.v:173365.13-173365.45" + process $proc$libresoc.v:173365$10266 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:171741.7-171741.25" - process $proc$libresoc.v:171741$10219 + attribute \src "libresoc.v:173373.7-173373.25" + process $proc$libresoc.v:173373$10267 assign { } { } - assign $0\xer_so$49[0:0]$10220 1'0 + assign $0\xer_so$49[0:0]$10268 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10220 + update \xer_so$49 $0\xer_so$49[0:0]$10268 end - attribute \src "libresoc.v:171750.3-171751.43" - process $proc$libresoc.v:171750$9970 + attribute \src "libresoc.v:173382.3-173383.43" + process $proc$libresoc.v:173382$10018 assign { } { } - assign $0\operation$69[1:0]$9971 \operation$69$next + assign $0\operation$69[1:0]$10019 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9971 + update \operation$69 $0\operation$69[1:0]$10019 end - attribute \src "libresoc.v:171752.3-171753.57" - process $proc$libresoc.v:171752$9972 + attribute \src "libresoc.v:173384.3-173385.57" + process $proc$libresoc.v:173384$10020 assign { } { } - assign $0\divisor_radicand$65[63:0]$9973 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9973 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 end - attribute \src "libresoc.v:171754.3-171755.41" - process $proc$libresoc.v:171754$9974 + attribute \src "libresoc.v:173386.3-173387.41" + process $proc$libresoc.v:173386$10022 assign { } { } - assign $0\dividend$68[127:0]$9975 \dividend$68$next + assign $0\dividend$68[127:0]$10023 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9975 + update \dividend$68 $0\dividend$68[127:0]$10023 end - attribute \src "libresoc.v:171756.3-171757.47" - process $proc$libresoc.v:171756$9976 + attribute \src "libresoc.v:173388.3-173389.47" + process $proc$libresoc.v:173388$10024 assign { } { } - assign $0\div_by_zero$54[0:0]$9977 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9977 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 end - attribute \src "libresoc.v:171758.3-171759.51" - process $proc$libresoc.v:171758$9978 + attribute \src "libresoc.v:173390.3-173391.51" + process $proc$libresoc.v:173390$10026 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9979 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9979 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 end - attribute \src "libresoc.v:171760.3-171761.51" - process $proc$libresoc.v:171760$9980 + attribute \src "libresoc.v:173392.3-173393.51" + process $proc$libresoc.v:173392$10028 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9981 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9981 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 end - attribute \src "libresoc.v:171762.3-171763.49" - process $proc$libresoc.v:171762$9982 + attribute \src "libresoc.v:173394.3-173395.49" + process $proc$libresoc.v:173394$10030 assign { } { } - assign $0\dividend_neg$51[0:0]$9983 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9983 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 end - attribute \src "libresoc.v:171764.3-171765.47" - process $proc$libresoc.v:171764$9984 + attribute \src "libresoc.v:173396.3-173397.47" + process $proc$libresoc.v:173396$10032 assign { } { } - assign $0\divisor_neg$50[0:0]$9985 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9985 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 end - attribute \src "libresoc.v:171766.3-171767.37" - process $proc$libresoc.v:171766$9986 + attribute \src "libresoc.v:173398.3-173399.37" + process $proc$libresoc.v:173398$10034 assign { } { } - assign $0\xer_so$49[0:0]$9987 \xer_so$49$next + assign $0\xer_so$49[0:0]$10035 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9987 + update \xer_so$49 $0\xer_so$49[0:0]$10035 end - attribute \src "libresoc.v:171768.3-171769.29" - process $proc$libresoc.v:171768$9988 + attribute \src "libresoc.v:173400.3-173401.29" + process $proc$libresoc.v:173400$10036 assign { } { } - assign $0\rb$48[63:0]$9989 \rb$48$next + assign $0\rb$48[63:0]$10037 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9989 + update \rb$48 $0\rb$48[63:0]$10037 end - attribute \src "libresoc.v:171770.3-171771.29" - process $proc$libresoc.v:171770$9990 + attribute \src "libresoc.v:173402.3-173403.29" + process $proc$libresoc.v:173402$10038 assign { } { } - assign $0\ra$47[63:0]$9991 \ra$47$next + assign $0\ra$47[63:0]$10039 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9991 + update \ra$47 $0\ra$47[63:0]$10039 end - attribute \src "libresoc.v:171772.3-171773.67" - process $proc$libresoc.v:171772$9992 + attribute \src "libresoc.v:173404.3-173405.67" + process $proc$libresoc.v:173404$10040 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9993 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9993 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 end - attribute \src "libresoc.v:171774.3-171775.63" - process $proc$libresoc.v:171774$9994 + attribute \src "libresoc.v:173406.3-173407.63" + process $proc$libresoc.v:173406$10042 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$9995 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9995 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 end - attribute \src "libresoc.v:171776.3-171777.77" - process $proc$libresoc.v:171776$9996 + attribute \src "libresoc.v:173408.3-173409.77" + process $proc$libresoc.v:173408$10044 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9997 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9997 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 end - attribute \src "libresoc.v:171778.3-171779.73" - process $proc$libresoc.v:171778$9998 + attribute \src "libresoc.v:173410.3-173411.73" + process $proc$libresoc.v:173410$10046 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9999 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9999 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 end - attribute \src "libresoc.v:171780.3-171781.61" - process $proc$libresoc.v:171780$10000 + attribute \src "libresoc.v:173412.3-173413.61" + process $proc$libresoc.v:173412$10048 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10001 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10001 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 end - attribute \src "libresoc.v:171782.3-171783.61" - process $proc$libresoc.v:171782$10002 + attribute \src "libresoc.v:173414.3-173415.61" + process $proc$libresoc.v:173414$10050 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10003 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10003 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 end - attribute \src "libresoc.v:171784.3-171785.61" - process $proc$libresoc.v:171784$10004 + attribute \src "libresoc.v:173416.3-173417.61" + process $proc$libresoc.v:173416$10052 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10005 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10005 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 end - attribute \src "libresoc.v:171786.3-171787.61" - process $proc$libresoc.v:171786$10006 + attribute \src "libresoc.v:173418.3-173419.61" + process $proc$libresoc.v:173418$10054 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10007 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10007 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 end - attribute \src "libresoc.v:171788.3-171789.67" - process $proc$libresoc.v:171788$10008 + attribute \src "libresoc.v:173420.3-173421.67" + process $proc$libresoc.v:173420$10056 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10009 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10009 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 end - attribute \src "libresoc.v:171790.3-171791.61" - process $proc$libresoc.v:171790$10010 + attribute \src "libresoc.v:173422.3-173423.61" + process $proc$libresoc.v:173422$10058 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10011 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10011 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 end - attribute \src "libresoc.v:171792.3-171793.71" - process $proc$libresoc.v:171792$10012 + attribute \src "libresoc.v:173424.3-173425.71" + process $proc$libresoc.v:173424$10060 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10013 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10013 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 end - attribute \src "libresoc.v:171794.3-171795.69" - process $proc$libresoc.v:171794$10014 + attribute \src "libresoc.v:173426.3-173427.69" + process $proc$libresoc.v:173426$10062 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10015 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10015 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 end - attribute \src "libresoc.v:171796.3-171797.67" - process $proc$libresoc.v:171796$10016 + attribute \src "libresoc.v:173428.3-173429.67" + process $proc$libresoc.v:173428$10064 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10017 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10017 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 end - attribute \src "libresoc.v:171798.3-171799.73" - process $proc$libresoc.v:171798$10018 + attribute \src "libresoc.v:173430.3-173431.73" + process $proc$libresoc.v:173430$10066 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10019 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10019 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 end - attribute \src "libresoc.v:171800.3-171801.65" - process $proc$libresoc.v:171800$10020 + attribute \src "libresoc.v:173432.3-173433.65" + process $proc$libresoc.v:173432$10068 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10021 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10021 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 end - attribute \src "libresoc.v:171802.3-171803.67" - process $proc$libresoc.v:171802$10022 + attribute \src "libresoc.v:173434.3-173435.67" + process $proc$libresoc.v:173434$10070 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10023 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10023 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 end - attribute \src "libresoc.v:171804.3-171805.65" - process $proc$libresoc.v:171804$10024 + attribute \src "libresoc.v:173436.3-173437.65" + process $proc$libresoc.v:173436$10072 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10025 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10025 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 end - attribute \src "libresoc.v:171806.3-171807.57" - process $proc$libresoc.v:171806$10026 + attribute \src "libresoc.v:173438.3-173439.57" + process $proc$libresoc.v:173438$10074 assign { } { } - assign $0\logical_op__insn$46[31:0]$10027 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10027 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 end - attribute \src "libresoc.v:171808.3-171809.35" - process $proc$libresoc.v:171808$10028 + attribute \src "libresoc.v:173440.3-173441.35" + process $proc$libresoc.v:173440$10076 assign { } { } - assign $0\muxid$28[1:0]$10029 \muxid$28$next + assign $0\muxid$28[1:0]$10077 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$10029 + update \muxid$28 $0\muxid$28[1:0]$10077 end - attribute \src "libresoc.v:171810.3-171811.27" - process $proc$libresoc.v:171810$10030 + attribute \src "libresoc.v:173442.3-173443.27" + process $proc$libresoc.v:173442$10078 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:171812.3-171813.75" - process $proc$libresoc.v:171812$10031 + attribute \src "libresoc.v:173444.3-173445.75" + process $proc$libresoc.v:173444$10079 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:171814.3-171815.65" - process $proc$libresoc.v:171814$10032 + attribute \src "libresoc.v:173446.3-173447.65" + process $proc$libresoc.v:173446$10080 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:171836.3-171844.6" - process $proc$libresoc.v:171836$10033 + attribute \src "libresoc.v:173468.3-173476.6" + process $proc$libresoc.v:173468$10081 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$10034 $1\saved_state_q_bits_known$next[6:0]$10035 - attribute \src "libresoc.v:171837.5-171837.29" + assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173469.5-173469.29" switch \initial - attribute \src "libresoc.v:171837.9-171837.17" + attribute \src "libresoc.v:173469.9-173469.17" case 1'1 case end @@ -353271,21 +355768,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$10035 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$10083 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$10035 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$10083 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10034 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 end - attribute \src "libresoc.v:171845.3-171853.6" - process $proc$libresoc.v:171845$10036 + attribute \src "libresoc.v:173477.3-173485.6" + process $proc$libresoc.v:173477$10084 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$10037 $1\saved_state_dividend_quotient$next[127:0]$10038 - attribute \src "libresoc.v:171846.5-171846.29" + assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173478.5-173478.29" switch \initial - attribute \src "libresoc.v:171846.9-171846.17" + attribute \src "libresoc.v:173478.9-173478.17" case 1'1 case end @@ -353294,20 +355791,20 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$10038 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$10086 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$10038 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$10086 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10037 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 end - attribute \src "libresoc.v:171854.3-171865.6" - process $proc$libresoc.v:171854$10039 + attribute \src "libresoc.v:173486.3-173497.6" + process $proc$libresoc.v:173486$10087 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:171855.5-171855.29" + attribute \src "libresoc.v:173487.5-173487.29" switch \initial - attribute \src "libresoc.v:171855.9-171855.17" + attribute \src "libresoc.v:173487.9-173487.17" case 1'1 case end @@ -353325,13 +355822,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:171866.3-171877.6" - process $proc$libresoc.v:171866$10040 + attribute \src "libresoc.v:173498.3-173509.6" + process $proc$libresoc.v:173498$10088 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171867.5-171867.29" + attribute \src "libresoc.v:173499.5-173499.29" switch \initial - attribute \src "libresoc.v:171867.9-171867.17" + attribute \src "libresoc.v:173499.9-173499.17" case 1'1 case end @@ -353349,13 +355846,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:171878.3-171889.6" - process $proc$libresoc.v:171878$10041 + attribute \src "libresoc.v:173510.3-173521.6" + process $proc$libresoc.v:173510$10089 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171879.5-171879.29" + attribute \src "libresoc.v:173511.5-173511.29" switch \initial - attribute \src "libresoc.v:171879.9-171879.17" + attribute \src "libresoc.v:173511.9-173511.17" case 1'1 case end @@ -353373,15 +355870,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:171890.3-171917.6" - process $proc$libresoc.v:171890$10042 + attribute \src "libresoc.v:173522.3-173549.6" + process $proc$libresoc.v:173522$10090 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$10043 $4\empty$next[0:0]$10047 - attribute \src "libresoc.v:171891.5-171891.29" + assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173523.5-173523.29" switch \initial - attribute \src "libresoc.v:171891.9-171891.17" + attribute \src "libresoc.v:173523.9-173523.17" case 1'1 case end @@ -353390,28 +355887,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$10044 $2\empty$next[0:0]$10045 + assign $1\empty$next[0:0]$10092 $2\empty$next[0:0]$10093 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$10045 1'0 + assign $2\empty$next[0:0]$10093 1'0 case - assign $2\empty$next[0:0]$10045 \empty + assign $2\empty$next[0:0]$10093 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$10044 $3\empty$next[0:0]$10046 + assign $1\empty$next[0:0]$10092 $3\empty$next[0:0]$10094 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$10046 1'1 + assign $3\empty$next[0:0]$10094 1'1 case - assign $3\empty$next[0:0]$10046 \empty + assign $3\empty$next[0:0]$10094 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -353419,21 +355916,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10047 1'1 + assign $4\empty$next[0:0]$10095 1'1 case - assign $4\empty$next[0:0]$10047 $1\empty$next[0:0]$10044 + assign $4\empty$next[0:0]$10095 $1\empty$next[0:0]$10092 end sync always - update \empty$next $0\empty$next[0:0]$10043 + update \empty$next $0\empty$next[0:0]$10091 end - attribute \src "libresoc.v:171918.3-171932.6" - process $proc$libresoc.v:171918$10048 + attribute \src "libresoc.v:173550.3-173564.6" + process $proc$libresoc.v:173550$10096 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10049 $1\muxid$28$next[1:0]$10050 - attribute \src "libresoc.v:171919.5-171919.29" + assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173551.5-173551.29" switch \initial - attribute \src "libresoc.v:171919.9-171919.17" + attribute \src "libresoc.v:173551.9-173551.17" case 1'1 case end @@ -353442,24 +355939,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$10050 $2\muxid$28$next[1:0]$10051 + assign $1\muxid$28$next[1:0]$10098 $2\muxid$28$next[1:0]$10099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$10051 \muxid + assign $2\muxid$28$next[1:0]$10099 \muxid case - assign $2\muxid$28$next[1:0]$10051 \muxid$28 + assign $2\muxid$28$next[1:0]$10099 \muxid$28 end case - assign $1\muxid$28$next[1:0]$10050 \muxid$28 + assign $1\muxid$28$next[1:0]$10098 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10049 + update \muxid$28$next $0\muxid$28$next[1:0]$10097 end - attribute \src "libresoc.v:171933.3-171976.6" - process $proc$libresoc.v:171933$10052 + attribute \src "libresoc.v:173565.3-173608.6" + process $proc$libresoc.v:173565$10100 assign { } { } assign { } { } assign { } { } @@ -353496,33 +355993,33 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10053 $1\logical_op__data_len$45$next[3:0]$10071 - assign $0\logical_op__fn_unit$30$next[13:0]$10054 $1\logical_op__fn_unit$30$next[13:0]$10072 + assign $0\logical_op__data_len$45$next[3:0]$10101 $1\logical_op__data_len$45$next[3:0]$10119 + assign $0\logical_op__fn_unit$30$next[13:0]$10102 $1\logical_op__fn_unit$30$next[13:0]$10120 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10057 $1\logical_op__input_carry$39$next[1:0]$10075 - assign $0\logical_op__insn$46$next[31:0]$10058 $1\logical_op__insn$46$next[31:0]$10076 - assign $0\logical_op__insn_type$29$next[6:0]$10059 $1\logical_op__insn_type$29$next[6:0]$10077 - assign $0\logical_op__invert_in$37$next[0:0]$10060 $1\logical_op__invert_in$37$next[0:0]$10078 - assign $0\logical_op__invert_out$40$next[0:0]$10061 $1\logical_op__invert_out$40$next[0:0]$10079 - assign $0\logical_op__is_32bit$43$next[0:0]$10062 $1\logical_op__is_32bit$43$next[0:0]$10080 - assign $0\logical_op__is_signed$44$next[0:0]$10063 $1\logical_op__is_signed$44$next[0:0]$10081 + assign $0\logical_op__input_carry$39$next[1:0]$10105 $1\logical_op__input_carry$39$next[1:0]$10123 + assign $0\logical_op__insn$46$next[31:0]$10106 $1\logical_op__insn$46$next[31:0]$10124 + assign $0\logical_op__insn_type$29$next[6:0]$10107 $1\logical_op__insn_type$29$next[6:0]$10125 + assign $0\logical_op__invert_in$37$next[0:0]$10108 $1\logical_op__invert_in$37$next[0:0]$10126 + assign $0\logical_op__invert_out$40$next[0:0]$10109 $1\logical_op__invert_out$40$next[0:0]$10127 + assign $0\logical_op__is_32bit$43$next[0:0]$10110 $1\logical_op__is_32bit$43$next[0:0]$10128 + assign $0\logical_op__is_signed$44$next[0:0]$10111 $1\logical_op__is_signed$44$next[0:0]$10129 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10066 $1\logical_op__output_carry$42$next[0:0]$10084 + assign $0\logical_op__output_carry$42$next[0:0]$10114 $1\logical_op__output_carry$42$next[0:0]$10132 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10069 $1\logical_op__write_cr0$41$next[0:0]$10087 - assign $0\logical_op__zero_a$38$next[0:0]$10070 $1\logical_op__zero_a$38$next[0:0]$10088 - assign $0\logical_op__imm_data__data$31$next[63:0]$10055 $3\logical_op__imm_data__data$31$next[63:0]$10107 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10056 $3\logical_op__imm_data__ok$32$next[0:0]$10108 - assign $0\logical_op__oe__oe$35$next[0:0]$10064 $3\logical_op__oe__oe$35$next[0:0]$10109 - assign $0\logical_op__oe__ok$36$next[0:0]$10065 $3\logical_op__oe__ok$36$next[0:0]$10110 - assign $0\logical_op__rc__ok$34$next[0:0]$10067 $3\logical_op__rc__ok$34$next[0:0]$10111 - assign $0\logical_op__rc__rc$33$next[0:0]$10068 $3\logical_op__rc__rc$33$next[0:0]$10112 - attribute \src "libresoc.v:171934.5-171934.29" + assign $0\logical_op__write_cr0$41$next[0:0]$10117 $1\logical_op__write_cr0$41$next[0:0]$10135 + assign $0\logical_op__zero_a$38$next[0:0]$10118 $1\logical_op__zero_a$38$next[0:0]$10136 + assign $0\logical_op__imm_data__data$31$next[63:0]$10103 $3\logical_op__imm_data__data$31$next[63:0]$10155 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10104 $3\logical_op__imm_data__ok$32$next[0:0]$10156 + assign $0\logical_op__oe__oe$35$next[0:0]$10112 $3\logical_op__oe__oe$35$next[0:0]$10157 + assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 + assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 + assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173566.5-173566.29" switch \initial - attribute \src "libresoc.v:171934.9-171934.17" + attribute \src "libresoc.v:173566.9-173566.17" case 1'1 case end @@ -353548,24 +356045,24 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10071 $2\logical_op__data_len$45$next[3:0]$10089 - assign $1\logical_op__fn_unit$30$next[13:0]$10072 $2\logical_op__fn_unit$30$next[13:0]$10090 - assign $1\logical_op__imm_data__data$31$next[63:0]$10073 $2\logical_op__imm_data__data$31$next[63:0]$10091 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 $2\logical_op__imm_data__ok$32$next[0:0]$10092 - assign $1\logical_op__input_carry$39$next[1:0]$10075 $2\logical_op__input_carry$39$next[1:0]$10093 - assign $1\logical_op__insn$46$next[31:0]$10076 $2\logical_op__insn$46$next[31:0]$10094 - assign $1\logical_op__insn_type$29$next[6:0]$10077 $2\logical_op__insn_type$29$next[6:0]$10095 - assign $1\logical_op__invert_in$37$next[0:0]$10078 $2\logical_op__invert_in$37$next[0:0]$10096 - assign $1\logical_op__invert_out$40$next[0:0]$10079 $2\logical_op__invert_out$40$next[0:0]$10097 - assign $1\logical_op__is_32bit$43$next[0:0]$10080 $2\logical_op__is_32bit$43$next[0:0]$10098 - assign $1\logical_op__is_signed$44$next[0:0]$10081 $2\logical_op__is_signed$44$next[0:0]$10099 - assign $1\logical_op__oe__oe$35$next[0:0]$10082 $2\logical_op__oe__oe$35$next[0:0]$10100 - assign $1\logical_op__oe__ok$36$next[0:0]$10083 $2\logical_op__oe__ok$36$next[0:0]$10101 - assign $1\logical_op__output_carry$42$next[0:0]$10084 $2\logical_op__output_carry$42$next[0:0]$10102 - assign $1\logical_op__rc__ok$34$next[0:0]$10085 $2\logical_op__rc__ok$34$next[0:0]$10103 - assign $1\logical_op__rc__rc$33$next[0:0]$10086 $2\logical_op__rc__rc$33$next[0:0]$10104 - assign $1\logical_op__write_cr0$41$next[0:0]$10087 $2\logical_op__write_cr0$41$next[0:0]$10105 - assign $1\logical_op__zero_a$38$next[0:0]$10088 $2\logical_op__zero_a$38$next[0:0]$10106 + assign $1\logical_op__data_len$45$next[3:0]$10119 $2\logical_op__data_len$45$next[3:0]$10137 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 $2\logical_op__fn_unit$30$next[13:0]$10138 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 $2\logical_op__imm_data__data$31$next[63:0]$10139 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 $2\logical_op__imm_data__ok$32$next[0:0]$10140 + assign $1\logical_op__input_carry$39$next[1:0]$10123 $2\logical_op__input_carry$39$next[1:0]$10141 + assign $1\logical_op__insn$46$next[31:0]$10124 $2\logical_op__insn$46$next[31:0]$10142 + assign $1\logical_op__insn_type$29$next[6:0]$10125 $2\logical_op__insn_type$29$next[6:0]$10143 + assign $1\logical_op__invert_in$37$next[0:0]$10126 $2\logical_op__invert_in$37$next[0:0]$10144 + assign $1\logical_op__invert_out$40$next[0:0]$10127 $2\logical_op__invert_out$40$next[0:0]$10145 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 $2\logical_op__is_32bit$43$next[0:0]$10146 + assign $1\logical_op__is_signed$44$next[0:0]$10129 $2\logical_op__is_signed$44$next[0:0]$10147 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 $2\logical_op__oe__oe$35$next[0:0]$10148 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 $2\logical_op__oe__ok$36$next[0:0]$10149 + assign $1\logical_op__output_carry$42$next[0:0]$10132 $2\logical_op__output_carry$42$next[0:0]$10150 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 $2\logical_op__rc__ok$34$next[0:0]$10151 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 $2\logical_op__rc__rc$33$next[0:0]$10152 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 $2\logical_op__write_cr0$41$next[0:0]$10153 + assign $1\logical_op__zero_a$38$next[0:0]$10136 $2\logical_op__zero_a$38$next[0:0]$10154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -353588,46 +356085,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10094 $2\logical_op__data_len$45$next[3:0]$10089 $2\logical_op__is_signed$44$next[0:0]$10099 $2\logical_op__is_32bit$43$next[0:0]$10098 $2\logical_op__output_carry$42$next[0:0]$10102 $2\logical_op__write_cr0$41$next[0:0]$10105 $2\logical_op__invert_out$40$next[0:0]$10097 $2\logical_op__input_carry$39$next[1:0]$10093 $2\logical_op__zero_a$38$next[0:0]$10106 $2\logical_op__invert_in$37$next[0:0]$10096 $2\logical_op__oe__ok$36$next[0:0]$10101 $2\logical_op__oe__oe$35$next[0:0]$10100 $2\logical_op__rc__ok$34$next[0:0]$10103 $2\logical_op__rc__rc$33$next[0:0]$10104 $2\logical_op__imm_data__ok$32$next[0:0]$10092 $2\logical_op__imm_data__data$31$next[63:0]$10091 $2\logical_op__fn_unit$30$next[13:0]$10090 $2\logical_op__insn_type$29$next[6:0]$10095 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$10142 $2\logical_op__data_len$45$next[3:0]$10137 $2\logical_op__is_signed$44$next[0:0]$10147 $2\logical_op__is_32bit$43$next[0:0]$10146 $2\logical_op__output_carry$42$next[0:0]$10150 $2\logical_op__write_cr0$41$next[0:0]$10153 $2\logical_op__invert_out$40$next[0:0]$10145 $2\logical_op__input_carry$39$next[1:0]$10141 $2\logical_op__zero_a$38$next[0:0]$10154 $2\logical_op__invert_in$37$next[0:0]$10144 $2\logical_op__oe__ok$36$next[0:0]$10149 $2\logical_op__oe__oe$35$next[0:0]$10148 $2\logical_op__rc__ok$34$next[0:0]$10151 $2\logical_op__rc__rc$33$next[0:0]$10152 $2\logical_op__imm_data__ok$32$next[0:0]$10140 $2\logical_op__imm_data__data$31$next[63:0]$10139 $2\logical_op__fn_unit$30$next[13:0]$10138 $2\logical_op__insn_type$29$next[6:0]$10143 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$10089 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[13:0]$10090 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10091 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10092 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10093 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10094 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10095 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10096 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10097 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10098 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10099 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10100 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10101 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10102 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10103 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10104 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10105 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10106 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$10137 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10138 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10139 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10140 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10141 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10142 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10143 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10144 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10145 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10146 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10147 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10148 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10149 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10150 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10151 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10152 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10153 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10154 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$10071 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[13:0]$10072 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10073 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10075 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10076 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10077 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10078 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10079 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10080 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10081 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10082 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10083 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10084 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10085 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10086 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10087 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10088 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$10119 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10123 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10124 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10125 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10126 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10127 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10129 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10132 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10136 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -353639,48 +356136,48 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10107 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10112 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10111 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10109 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10110 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$10107 $1\logical_op__imm_data__data$31$next[63:0]$10073 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 $1\logical_op__imm_data__ok$32$next[0:0]$10074 - assign $3\logical_op__oe__oe$35$next[0:0]$10109 $1\logical_op__oe__oe$35$next[0:0]$10082 - assign $3\logical_op__oe__ok$36$next[0:0]$10110 $1\logical_op__oe__ok$36$next[0:0]$10083 - assign $3\logical_op__rc__ok$34$next[0:0]$10111 $1\logical_op__rc__ok$34$next[0:0]$10085 - assign $3\logical_op__rc__rc$33$next[0:0]$10112 $1\logical_op__rc__rc$33$next[0:0]$10086 + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 $1\logical_op__imm_data__data$31$next[63:0]$10121 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 $1\logical_op__imm_data__ok$32$next[0:0]$10122 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 $1\logical_op__oe__oe$35$next[0:0]$10130 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 $1\logical_op__oe__ok$36$next[0:0]$10131 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 $1\logical_op__rc__ok$34$next[0:0]$10133 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 $1\logical_op__rc__rc$33$next[0:0]$10134 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10053 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10054 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10055 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10056 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10057 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10058 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10059 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10060 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10061 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10062 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10063 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10064 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10065 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10066 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10067 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10068 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10069 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10070 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10101 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10102 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10103 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10104 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10105 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10106 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10107 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10108 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10109 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10110 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10111 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10112 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10113 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10114 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10115 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10116 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 end - attribute \src "libresoc.v:171977.3-171991.6" - process $proc$libresoc.v:171977$10113 + attribute \src "libresoc.v:173609.3-173623.6" + process $proc$libresoc.v:173609$10161 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10114 $1\ra$47$next[63:0]$10115 - attribute \src "libresoc.v:171978.5-171978.29" + assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173610.5-173610.29" switch \initial - attribute \src "libresoc.v:171978.9-171978.17" + attribute \src "libresoc.v:173610.9-173610.17" case 1'1 case end @@ -353689,30 +356186,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$10115 $2\ra$47$next[63:0]$10116 + assign $1\ra$47$next[63:0]$10163 $2\ra$47$next[63:0]$10164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$10116 \ra + assign $2\ra$47$next[63:0]$10164 \ra case - assign $2\ra$47$next[63:0]$10116 \ra$47 + assign $2\ra$47$next[63:0]$10164 \ra$47 end case - assign $1\ra$47$next[63:0]$10115 \ra$47 + assign $1\ra$47$next[63:0]$10163 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$10114 + update \ra$47$next $0\ra$47$next[63:0]$10162 end - attribute \src "libresoc.v:171992.3-172006.6" - process $proc$libresoc.v:171992$10117 + attribute \src "libresoc.v:173624.3-173638.6" + process $proc$libresoc.v:173624$10165 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$10118 $1\rb$48$next[63:0]$10119 - attribute \src "libresoc.v:171993.5-171993.29" + assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173625.5-173625.29" switch \initial - attribute \src "libresoc.v:171993.9-171993.17" + attribute \src "libresoc.v:173625.9-173625.17" case 1'1 case end @@ -353721,30 +356218,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$10119 $2\rb$48$next[63:0]$10120 + assign $1\rb$48$next[63:0]$10167 $2\rb$48$next[63:0]$10168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$10120 \rb + assign $2\rb$48$next[63:0]$10168 \rb case - assign $2\rb$48$next[63:0]$10120 \rb$48 + assign $2\rb$48$next[63:0]$10168 \rb$48 end case - assign $1\rb$48$next[63:0]$10119 \rb$48 + assign $1\rb$48$next[63:0]$10167 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$10118 + update \rb$48$next $0\rb$48$next[63:0]$10166 end - attribute \src "libresoc.v:172007.3-172021.6" - process $proc$libresoc.v:172007$10121 + attribute \src "libresoc.v:173639.3-173653.6" + process $proc$libresoc.v:173639$10169 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$10122 $1\xer_so$49$next[0:0]$10123 - attribute \src "libresoc.v:172008.5-172008.29" + assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173640.5-173640.29" switch \initial - attribute \src "libresoc.v:172008.9-172008.17" + attribute \src "libresoc.v:173640.9-173640.17" case 1'1 case end @@ -353753,30 +356250,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10123 $2\xer_so$49$next[0:0]$10124 + assign $1\xer_so$49$next[0:0]$10171 $2\xer_so$49$next[0:0]$10172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$10124 \xer_so + assign $2\xer_so$49$next[0:0]$10172 \xer_so case - assign $2\xer_so$49$next[0:0]$10124 \xer_so$49 + assign $2\xer_so$49$next[0:0]$10172 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$10123 \xer_so$49 + assign $1\xer_so$49$next[0:0]$10171 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10122 + update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 end - attribute \src "libresoc.v:172022.3-172036.6" - process $proc$libresoc.v:172022$10125 + attribute \src "libresoc.v:173654.3-173668.6" + process $proc$libresoc.v:173654$10173 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10126 $1\divisor_neg$50$next[0:0]$10127 - attribute \src "libresoc.v:172023.5-172023.29" + assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173655.5-173655.29" switch \initial - attribute \src "libresoc.v:172023.9-172023.17" + attribute \src "libresoc.v:173655.9-173655.17" case 1'1 case end @@ -353785,30 +356282,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10127 $2\divisor_neg$50$next[0:0]$10128 + assign $1\divisor_neg$50$next[0:0]$10175 $2\divisor_neg$50$next[0:0]$10176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$10127 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$10175 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10126 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 end - attribute \src "libresoc.v:172037.3-172051.6" - process $proc$libresoc.v:172037$10129 + attribute \src "libresoc.v:173669.3-173683.6" + process $proc$libresoc.v:173669$10177 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$10130 $1\dividend_neg$51$next[0:0]$10131 - attribute \src "libresoc.v:172038.5-172038.29" + assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173670.5-173670.29" switch \initial - attribute \src "libresoc.v:172038.9-172038.17" + attribute \src "libresoc.v:173670.9-173670.17" case 1'1 case end @@ -353817,30 +356314,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10131 $2\dividend_neg$51$next[0:0]$10132 + assign $1\dividend_neg$51$next[0:0]$10179 $2\dividend_neg$51$next[0:0]$10180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$10131 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$10179 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10130 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 end - attribute \src "libresoc.v:172052.3-172066.6" - process $proc$libresoc.v:172052$10133 + attribute \src "libresoc.v:173684.3-173698.6" + process $proc$libresoc.v:173684$10181 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10134 $1\dive_abs_ov32$52$next[0:0]$10135 - attribute \src "libresoc.v:172053.5-172053.29" + assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173685.5-173685.29" switch \initial - attribute \src "libresoc.v:172053.9-172053.17" + attribute \src "libresoc.v:173685.9-173685.17" case 1'1 case end @@ -353849,30 +356346,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10135 $2\dive_abs_ov32$52$next[0:0]$10136 + assign $1\dive_abs_ov32$52$next[0:0]$10183 $2\dive_abs_ov32$52$next[0:0]$10184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$10135 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$10183 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10134 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 end - attribute \src "libresoc.v:172067.3-172081.6" - process $proc$libresoc.v:172067$10137 + attribute \src "libresoc.v:173699.3-173713.6" + process $proc$libresoc.v:173699$10185 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10138 $1\dive_abs_ov64$53$next[0:0]$10139 - attribute \src "libresoc.v:172068.5-172068.29" + assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173700.5-173700.29" switch \initial - attribute \src "libresoc.v:172068.9-172068.17" + attribute \src "libresoc.v:173700.9-173700.17" case 1'1 case end @@ -353881,30 +356378,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10139 $2\dive_abs_ov64$53$next[0:0]$10140 + assign $1\dive_abs_ov64$53$next[0:0]$10187 $2\dive_abs_ov64$53$next[0:0]$10188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$10139 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$10187 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10138 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 end - attribute \src "libresoc.v:172082.3-172096.6" - process $proc$libresoc.v:172082$10141 + attribute \src "libresoc.v:173714.3-173728.6" + process $proc$libresoc.v:173714$10189 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10142 $1\div_by_zero$54$next[0:0]$10143 - attribute \src "libresoc.v:172083.5-172083.29" + assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173715.5-173715.29" switch \initial - attribute \src "libresoc.v:172083.9-172083.17" + attribute \src "libresoc.v:173715.9-173715.17" case 1'1 case end @@ -353913,30 +356410,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10143 $2\div_by_zero$54$next[0:0]$10144 + assign $1\div_by_zero$54$next[0:0]$10191 $2\div_by_zero$54$next[0:0]$10192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$10143 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$10191 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10142 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 end - attribute \src "libresoc.v:172097.3-172111.6" - process $proc$libresoc.v:172097$10145 + attribute \src "libresoc.v:173729.3-173743.6" + process $proc$libresoc.v:173729$10193 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$10146 $1\dividend$68$next[127:0]$10147 - attribute \src "libresoc.v:172098.5-172098.29" + assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173730.5-173730.29" switch \initial - attribute \src "libresoc.v:172098.9-172098.17" + attribute \src "libresoc.v:173730.9-173730.17" case 1'1 case end @@ -353945,30 +356442,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10147 $2\dividend$68$next[127:0]$10148 + assign $1\dividend$68$next[127:0]$10195 $2\dividend$68$next[127:0]$10196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$10148 \dividend + assign $2\dividend$68$next[127:0]$10196 \dividend case - assign $2\dividend$68$next[127:0]$10148 \dividend$68 + assign $2\dividend$68$next[127:0]$10196 \dividend$68 end case - assign $1\dividend$68$next[127:0]$10147 \dividend$68 + assign $1\dividend$68$next[127:0]$10195 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10146 + update \dividend$68$next $0\dividend$68$next[127:0]$10194 end - attribute \src "libresoc.v:172112.3-172126.6" - process $proc$libresoc.v:172112$10149 + attribute \src "libresoc.v:173744.3-173758.6" + process $proc$libresoc.v:173744$10197 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10150 $1\divisor_radicand$65$next[63:0]$10151 - attribute \src "libresoc.v:172113.5-172113.29" + assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173745.5-173745.29" switch \initial - attribute \src "libresoc.v:172113.9-172113.17" + attribute \src "libresoc.v:173745.9-173745.17" case 1'1 case end @@ -353977,30 +356474,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10151 $2\divisor_radicand$65$next[63:0]$10152 + assign $1\divisor_radicand$65$next[63:0]$10199 $2\divisor_radicand$65$next[63:0]$10200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$10151 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$10199 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10150 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 end - attribute \src "libresoc.v:172127.3-172141.6" - process $proc$libresoc.v:172127$10153 + attribute \src "libresoc.v:173759.3-173773.6" + process $proc$libresoc.v:173759$10201 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$10154 $1\operation$69$next[1:0]$10155 - attribute \src "libresoc.v:172128.5-172128.29" + assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173760.5-173760.29" switch \initial - attribute \src "libresoc.v:172128.9-172128.17" + attribute \src "libresoc.v:173760.9-173760.17" case 1'1 case end @@ -354009,28 +356506,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10155 $2\operation$69$next[1:0]$10156 + assign $1\operation$69$next[1:0]$10203 $2\operation$69$next[1:0]$10204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$10156 \operation + assign $2\operation$69$next[1:0]$10204 \operation case - assign $2\operation$69$next[1:0]$10156 \operation$69 + assign $2\operation$69$next[1:0]$10204 \operation$69 end case - assign $1\operation$69$next[1:0]$10155 \operation$69 + assign $1\operation$69$next[1:0]$10203 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10154 + update \operation$69$next $0\operation$69$next[1:0]$10202 end - connect \$56 $sshl$libresoc.v:171744$9963_Y - connect \$55 $pos$libresoc.v:171745$9965_Y - connect \$59 $not$libresoc.v:171746$9966_Y - connect \$61 $ge$libresoc.v:171747$9967_Y - connect \$63 $and$libresoc.v:171748$9968_Y - connect \$66 $and$libresoc.v:171749$9969_Y + connect \$56 $sshl$libresoc.v:173376$10011_Y + connect \$55 $pos$libresoc.v:173377$10013_Y + connect \$59 $not$libresoc.v:173378$10014_Y + connect \$61 $ge$libresoc.v:173379$10015_Y + connect \$63 $and$libresoc.v:173380$10016_Y + connect \$66 $and$libresoc.v:173381$10017_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -354047,282 +356544,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:172161.1-173706.10" +attribute \src "libresoc.v:173793.1-175338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:173512.3-173524.6" - wire $0\div_by_zero$next[0:0]$10266 - attribute \src "libresoc.v:173298.3-173299.39" + attribute \src "libresoc.v:175144.3-175156.6" + wire $0\div_by_zero$next[0:0]$10314 + attribute \src "libresoc.v:174930.3-174931.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:173486.3-173498.6" - wire $0\dive_abs_ov32$next[0:0]$10260 - attribute \src "libresoc.v:173302.3-173303.43" + attribute \src "libresoc.v:175118.3-175130.6" + wire $0\dive_abs_ov32$next[0:0]$10308 + attribute \src "libresoc.v:174934.3-174935.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:173499.3-173511.6" - wire $0\dive_abs_ov64$next[0:0]$10263 - attribute \src "libresoc.v:173300.3-173301.43" + attribute \src "libresoc.v:175131.3-175143.6" + wire $0\dive_abs_ov64$next[0:0]$10311 + attribute \src "libresoc.v:174932.3-174933.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:173525.3-173537.6" - wire width 128 $0\dividend$next[127:0]$10269 - attribute \src "libresoc.v:173296.3-173297.33" + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $0\dividend$next[127:0]$10317 + attribute \src "libresoc.v:174928.3-174929.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:173473.3-173485.6" - wire $0\dividend_neg$next[0:0]$10257 - attribute \src "libresoc.v:173304.3-173305.41" + attribute \src "libresoc.v:175105.3-175117.6" + wire $0\dividend_neg$next[0:0]$10305 + attribute \src "libresoc.v:174936.3-174937.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:173460.3-173472.6" - wire $0\divisor_neg$next[0:0]$10254 - attribute \src "libresoc.v:173306.3-173307.39" + attribute \src "libresoc.v:175092.3-175104.6" + wire $0\divisor_neg$next[0:0]$10302 + attribute \src "libresoc.v:174938.3-174939.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:173538.3-173550.6" - wire width 64 $0\divisor_radicand$next[63:0]$10272 - attribute \src "libresoc.v:173294.3-173295.49" + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $0\divisor_radicand$next[63:0]$10320 + attribute \src "libresoc.v:174926.3-174927.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:172162.7-172162.20" + attribute \src "libresoc.v:173794.7-173794.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10285 - attribute \src "libresoc.v:173346.3-173347.57" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10333 + attribute \src "libresoc.v:174978.3-174979.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$10286 - attribute \src "libresoc.v:173316.3-173317.55" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 + attribute \src "libresoc.v:174948.3-174949.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10287 - attribute \src "libresoc.v:173318.3-173319.69" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 + attribute \src "libresoc.v:174950.3-174951.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10288 - attribute \src "libresoc.v:173320.3-173321.65" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10336 + attribute \src "libresoc.v:174952.3-174953.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10289 - attribute \src "libresoc.v:173334.3-173335.63" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10337 + attribute \src "libresoc.v:174966.3-174967.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 32 $0\logical_op__insn$next[31:0]$10290 - attribute \src "libresoc.v:173348.3-173349.49" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $0\logical_op__insn$next[31:0]$10338 + attribute \src "libresoc.v:174980.3-174981.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10291 - attribute \src "libresoc.v:173314.3-173315.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10339 + attribute \src "libresoc.v:174946.3-174947.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__invert_in$next[0:0]$10292 - attribute \src "libresoc.v:173330.3-173331.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_in$next[0:0]$10340 + attribute \src "libresoc.v:174962.3-174963.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__invert_out$next[0:0]$10293 - attribute \src "libresoc.v:173336.3-173337.61" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_out$next[0:0]$10341 + attribute \src "libresoc.v:174968.3-174969.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__is_32bit$next[0:0]$10294 - attribute \src "libresoc.v:173342.3-173343.57" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_32bit$next[0:0]$10342 + attribute \src "libresoc.v:174974.3-174975.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__is_signed$next[0:0]$10295 - attribute \src "libresoc.v:173344.3-173345.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_signed$next[0:0]$10343 + attribute \src "libresoc.v:174976.3-174977.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__oe__oe$next[0:0]$10296 - attribute \src "libresoc.v:173326.3-173327.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__oe$next[0:0]$10344 + attribute \src "libresoc.v:174958.3-174959.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__oe__ok$next[0:0]$10297 - attribute \src "libresoc.v:173328.3-173329.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__ok$next[0:0]$10345 + attribute \src "libresoc.v:174960.3-174961.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__output_carry$next[0:0]$10298 - attribute \src "libresoc.v:173340.3-173341.65" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__output_carry$next[0:0]$10346 + attribute \src "libresoc.v:174972.3-174973.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__rc__ok$next[0:0]$10299 - attribute \src "libresoc.v:173324.3-173325.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__ok$next[0:0]$10347 + attribute \src "libresoc.v:174956.3-174957.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__rc__rc$next[0:0]$10300 - attribute \src "libresoc.v:173322.3-173323.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__rc$next[0:0]$10348 + attribute \src "libresoc.v:174954.3-174955.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__write_cr0$next[0:0]$10301 - attribute \src "libresoc.v:173338.3-173339.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__write_cr0$next[0:0]$10349 + attribute \src "libresoc.v:174970.3-174971.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__zero_a$next[0:0]$10302 - attribute \src "libresoc.v:173332.3-173333.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__zero_a$next[0:0]$10350 + attribute \src "libresoc.v:174964.3-174965.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:173582.3-173594.6" - wire width 2 $0\muxid$next[1:0]$10282 - attribute \src "libresoc.v:173350.3-173351.27" + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $0\muxid$next[1:0]$10330 + attribute \src "libresoc.v:174982.3-174983.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:173551.3-173563.6" - wire width 2 $0\operation$next[1:0]$10275 - attribute \src "libresoc.v:173292.3-173293.35" + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $0\operation$next[1:0]$10323 + attribute \src "libresoc.v:174924.3-174925.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:173564.3-173581.6" - wire $0\r_busy$next[0:0]$10278 - attribute \src "libresoc.v:173352.3-173353.29" + attribute \src "libresoc.v:175196.3-175213.6" + wire $0\r_busy$next[0:0]$10326 + attribute \src "libresoc.v:174984.3-174985.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:173637.3-173649.6" - wire width 64 $0\ra$next[63:0]$10328 - attribute \src "libresoc.v:173312.3-173313.21" + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $0\ra$next[63:0]$10376 + attribute \src "libresoc.v:174944.3-174945.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:173650.3-173662.6" - wire width 64 $0\rb$next[63:0]$10331 - attribute \src "libresoc.v:173310.3-173311.21" + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $0\rb$next[63:0]$10379 + attribute \src "libresoc.v:174942.3-174943.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:173663.3-173675.6" - wire $0\xer_so$next[0:0]$10334 - attribute \src "libresoc.v:173308.3-173309.29" + attribute \src "libresoc.v:175295.3-175307.6" + wire $0\xer_so$next[0:0]$10382 + attribute \src "libresoc.v:174940.3-174941.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:173512.3-173524.6" - wire $1\div_by_zero$next[0:0]$10267 - attribute \src "libresoc.v:172171.7-172171.25" + attribute \src "libresoc.v:175144.3-175156.6" + wire $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:173803.7-173803.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:173486.3-173498.6" - wire $1\dive_abs_ov32$next[0:0]$10261 - attribute \src "libresoc.v:172178.7-172178.27" + attribute \src "libresoc.v:175118.3-175130.6" + wire $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:173810.7-173810.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:173499.3-173511.6" - wire $1\dive_abs_ov64$next[0:0]$10264 - attribute \src "libresoc.v:172185.7-172185.27" + attribute \src "libresoc.v:175131.3-175143.6" + wire $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:173817.7-173817.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:173525.3-173537.6" - wire width 128 $1\dividend$next[127:0]$10270 - attribute \src "libresoc.v:172192.15-172192.63" + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:173824.15-173824.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:173473.3-173485.6" - wire $1\dividend_neg$next[0:0]$10258 - attribute \src "libresoc.v:172199.7-172199.26" + attribute \src "libresoc.v:175105.3-175117.6" + wire $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:173831.7-173831.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:173460.3-173472.6" - wire $1\divisor_neg$next[0:0]$10255 - attribute \src "libresoc.v:172206.7-172206.25" + attribute \src "libresoc.v:175092.3-175104.6" + wire $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:173838.7-173838.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:173538.3-173550.6" - wire width 64 $1\divisor_radicand$next[63:0]$10273 - attribute \src "libresoc.v:172213.14-172213.53" + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:173845.14-173845.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10303 - attribute \src "libresoc.v:172496.13-172496.40" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10351 + attribute \src "libresoc.v:174128.13-174128.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$10304 - attribute \src "libresoc.v:172520.14-172520.44" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 + attribute \src "libresoc.v:174152.14-174152.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10305 - attribute \src "libresoc.v:172559.14-172559.63" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 + attribute \src "libresoc.v:174191.14-174191.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10306 - attribute \src "libresoc.v:172568.7-172568.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10354 + attribute \src "libresoc.v:174200.7-174200.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10307 - attribute \src "libresoc.v:172581.13-172581.43" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10355 + attribute \src "libresoc.v:174213.13-174213.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 32 $1\logical_op__insn$next[31:0]$10308 - attribute \src "libresoc.v:172598.14-172598.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $1\logical_op__insn$next[31:0]$10356 + attribute \src "libresoc.v:174230.14-174230.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10309 - attribute \src "libresoc.v:172682.13-172682.42" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10357 + attribute \src "libresoc.v:174314.13-174314.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__invert_in$next[0:0]$10310 - attribute \src "libresoc.v:172841.7-172841.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_in$next[0:0]$10358 + attribute \src "libresoc.v:174473.7-174473.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__invert_out$next[0:0]$10311 - attribute \src "libresoc.v:172850.7-172850.36" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_out$next[0:0]$10359 + attribute \src "libresoc.v:174482.7-174482.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__is_32bit$next[0:0]$10312 - attribute \src "libresoc.v:172859.7-172859.34" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_32bit$next[0:0]$10360 + attribute \src "libresoc.v:174491.7-174491.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__is_signed$next[0:0]$10313 - attribute \src "libresoc.v:172868.7-172868.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_signed$next[0:0]$10361 + attribute \src "libresoc.v:174500.7-174500.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__oe__oe$next[0:0]$10314 - attribute \src "libresoc.v:172877.7-172877.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__oe$next[0:0]$10362 + attribute \src "libresoc.v:174509.7-174509.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__oe__ok$next[0:0]$10315 - attribute \src "libresoc.v:172886.7-172886.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__ok$next[0:0]$10363 + attribute \src "libresoc.v:174518.7-174518.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__output_carry$next[0:0]$10316 - attribute \src "libresoc.v:172895.7-172895.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__output_carry$next[0:0]$10364 + attribute \src "libresoc.v:174527.7-174527.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__rc__ok$next[0:0]$10317 - attribute \src "libresoc.v:172904.7-172904.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__ok$next[0:0]$10365 + attribute \src "libresoc.v:174536.7-174536.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__rc__rc$next[0:0]$10318 - attribute \src "libresoc.v:172913.7-172913.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__rc$next[0:0]$10366 + attribute \src "libresoc.v:174545.7-174545.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__write_cr0$next[0:0]$10319 - attribute \src "libresoc.v:172922.7-172922.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__write_cr0$next[0:0]$10367 + attribute \src "libresoc.v:174554.7-174554.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__zero_a$next[0:0]$10320 - attribute \src "libresoc.v:172931.7-172931.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__zero_a$next[0:0]$10368 + attribute \src "libresoc.v:174563.7-174563.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:173582.3-173594.6" - wire width 2 $1\muxid$next[1:0]$10283 - attribute \src "libresoc.v:172940.13-172940.25" + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:174572.13-174572.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:173551.3-173563.6" - wire width 2 $1\operation$next[1:0]$10276 - attribute \src "libresoc.v:172955.13-172955.29" + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:174587.13-174587.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:173564.3-173581.6" - wire $1\r_busy$next[0:0]$10279 - attribute \src "libresoc.v:172969.7-172969.20" + attribute \src "libresoc.v:175196.3-175213.6" + wire $1\r_busy$next[0:0]$10327 + attribute \src "libresoc.v:174601.7-174601.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:173637.3-173649.6" - wire width 64 $1\ra$next[63:0]$10329 - attribute \src "libresoc.v:172974.14-172974.39" + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:174606.14-174606.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:173650.3-173662.6" - wire width 64 $1\rb$next[63:0]$10332 - attribute \src "libresoc.v:172985.14-172985.39" + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:174617.14-174617.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:173663.3-173675.6" - wire $1\xer_so$next[0:0]$10335 - attribute \src "libresoc.v:173284.7-173284.20" + attribute \src "libresoc.v:175295.3-175307.6" + wire $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:174916.7-174916.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10321 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10322 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__oe__oe$next[0:0]$10323 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__oe__ok$next[0:0]$10324 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__rc__ok$next[0:0]$10325 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__rc__rc$next[0:0]$10326 - attribute \src "libresoc.v:173564.3-173581.6" - wire $2\r_busy$next[0:0]$10280 - attribute \src "libresoc.v:173291.18-173291.118" - wire $and$libresoc.v:173291$10221_Y + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10370 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__oe$next[0:0]$10371 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__ok$next[0:0]$10372 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__ok$next[0:0]$10373 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175196.3-175213.6" + wire $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:174923.18-174923.118" + wire $and$libresoc.v:174923$10269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -354366,7 +356863,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:172162.7-172162.15" + attribute \src "libresoc.v:173794.7-173794.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -355419,7 +357916,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:173291$10221 + cell $and $and$libresoc.v:174923$10269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355427,10 +357924,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:173291$10221_Y + connect \Y $and$libresoc.v:174923$10269_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173354.14-173399.4" + attribute \src "libresoc.v:174986.14-175031.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -355478,19 +357975,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:173400.10-173403.4" + attribute \src "libresoc.v:175032.10-175035.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173404.10-173407.4" + attribute \src "libresoc.v:175036.10-175039.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:173408.15-173459.4" + attribute \src "libresoc.v:175040.15-175091.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -355543,487 +358040,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:172162.7-172162.20" - process $proc$libresoc.v:172162$10336 + attribute \src "libresoc.v:173794.7-173794.20" + process $proc$libresoc.v:173794$10384 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172171.7-172171.25" - process $proc$libresoc.v:172171$10337 + attribute \src "libresoc.v:173803.7-173803.25" + process $proc$libresoc.v:173803$10385 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:172178.7-172178.27" - process $proc$libresoc.v:172178$10338 + attribute \src "libresoc.v:173810.7-173810.27" + process $proc$libresoc.v:173810$10386 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:172185.7-172185.27" - process $proc$libresoc.v:172185$10339 + attribute \src "libresoc.v:173817.7-173817.27" + process $proc$libresoc.v:173817$10387 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:172192.15-172192.63" - process $proc$libresoc.v:172192$10340 + attribute \src "libresoc.v:173824.15-173824.63" + process $proc$libresoc.v:173824$10388 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:172199.7-172199.26" - process $proc$libresoc.v:172199$10341 + attribute \src "libresoc.v:173831.7-173831.26" + process $proc$libresoc.v:173831$10389 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:172206.7-172206.25" - process $proc$libresoc.v:172206$10342 + attribute \src "libresoc.v:173838.7-173838.25" + process $proc$libresoc.v:173838$10390 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:172213.14-172213.53" - process $proc$libresoc.v:172213$10343 + attribute \src "libresoc.v:173845.14-173845.53" + process $proc$libresoc.v:173845$10391 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:172496.13-172496.40" - process $proc$libresoc.v:172496$10344 + attribute \src "libresoc.v:174128.13-174128.40" + process $proc$libresoc.v:174128$10392 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:172520.14-172520.44" - process $proc$libresoc.v:172520$10345 + attribute \src "libresoc.v:174152.14-174152.44" + process $proc$libresoc.v:174152$10393 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:172559.14-172559.63" - process $proc$libresoc.v:172559$10346 + attribute \src "libresoc.v:174191.14-174191.63" + process $proc$libresoc.v:174191$10394 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:172568.7-172568.38" - process $proc$libresoc.v:172568$10347 + attribute \src "libresoc.v:174200.7-174200.38" + process $proc$libresoc.v:174200$10395 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:172581.13-172581.43" - process $proc$libresoc.v:172581$10348 + attribute \src "libresoc.v:174213.13-174213.43" + process $proc$libresoc.v:174213$10396 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:172598.14-172598.38" - process $proc$libresoc.v:172598$10349 + attribute \src "libresoc.v:174230.14-174230.38" + process $proc$libresoc.v:174230$10397 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:172682.13-172682.42" - process $proc$libresoc.v:172682$10350 + attribute \src "libresoc.v:174314.13-174314.42" + process $proc$libresoc.v:174314$10398 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:172841.7-172841.35" - process $proc$libresoc.v:172841$10351 + attribute \src "libresoc.v:174473.7-174473.35" + process $proc$libresoc.v:174473$10399 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:172850.7-172850.36" - process $proc$libresoc.v:172850$10352 + attribute \src "libresoc.v:174482.7-174482.36" + process $proc$libresoc.v:174482$10400 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:172859.7-172859.34" - process $proc$libresoc.v:172859$10353 + attribute \src "libresoc.v:174491.7-174491.34" + process $proc$libresoc.v:174491$10401 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:172868.7-172868.35" - process $proc$libresoc.v:172868$10354 + attribute \src "libresoc.v:174500.7-174500.35" + process $proc$libresoc.v:174500$10402 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:172877.7-172877.32" - process $proc$libresoc.v:172877$10355 + attribute \src "libresoc.v:174509.7-174509.32" + process $proc$libresoc.v:174509$10403 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:172886.7-172886.32" - process $proc$libresoc.v:172886$10356 + attribute \src "libresoc.v:174518.7-174518.32" + process $proc$libresoc.v:174518$10404 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:172895.7-172895.38" - process $proc$libresoc.v:172895$10357 + attribute \src "libresoc.v:174527.7-174527.38" + process $proc$libresoc.v:174527$10405 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:172904.7-172904.32" - process $proc$libresoc.v:172904$10358 + attribute \src "libresoc.v:174536.7-174536.32" + process $proc$libresoc.v:174536$10406 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:172913.7-172913.32" - process $proc$libresoc.v:172913$10359 + attribute \src "libresoc.v:174545.7-174545.32" + process $proc$libresoc.v:174545$10407 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:172922.7-172922.35" - process $proc$libresoc.v:172922$10360 + attribute \src "libresoc.v:174554.7-174554.35" + process $proc$libresoc.v:174554$10408 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:172931.7-172931.32" - process $proc$libresoc.v:172931$10361 + attribute \src "libresoc.v:174563.7-174563.32" + process $proc$libresoc.v:174563$10409 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:172940.13-172940.25" - process $proc$libresoc.v:172940$10362 + attribute \src "libresoc.v:174572.13-174572.25" + process $proc$libresoc.v:174572$10410 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:172955.13-172955.29" - process $proc$libresoc.v:172955$10363 + attribute \src "libresoc.v:174587.13-174587.29" + process $proc$libresoc.v:174587$10411 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:172969.7-172969.20" - process $proc$libresoc.v:172969$10364 + attribute \src "libresoc.v:174601.7-174601.20" + process $proc$libresoc.v:174601$10412 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172974.14-172974.39" - process $proc$libresoc.v:172974$10365 + attribute \src "libresoc.v:174606.14-174606.39" + process $proc$libresoc.v:174606$10413 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:172985.14-172985.39" - process $proc$libresoc.v:172985$10366 + attribute \src "libresoc.v:174617.14-174617.39" + process $proc$libresoc.v:174617$10414 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:173284.7-173284.20" - process $proc$libresoc.v:173284$10367 + attribute \src "libresoc.v:174916.7-174916.20" + process $proc$libresoc.v:174916$10415 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:173292.3-173293.35" - process $proc$libresoc.v:173292$10222 + attribute \src "libresoc.v:174924.3-174925.35" + process $proc$libresoc.v:174924$10270 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:173294.3-173295.49" - process $proc$libresoc.v:173294$10223 + attribute \src "libresoc.v:174926.3-174927.49" + process $proc$libresoc.v:174926$10271 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:173296.3-173297.33" - process $proc$libresoc.v:173296$10224 + attribute \src "libresoc.v:174928.3-174929.33" + process $proc$libresoc.v:174928$10272 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:173298.3-173299.39" - process $proc$libresoc.v:173298$10225 + attribute \src "libresoc.v:174930.3-174931.39" + process $proc$libresoc.v:174930$10273 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:173300.3-173301.43" - process $proc$libresoc.v:173300$10226 + attribute \src "libresoc.v:174932.3-174933.43" + process $proc$libresoc.v:174932$10274 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:173302.3-173303.43" - process $proc$libresoc.v:173302$10227 + attribute \src "libresoc.v:174934.3-174935.43" + process $proc$libresoc.v:174934$10275 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:173304.3-173305.41" - process $proc$libresoc.v:173304$10228 + attribute \src "libresoc.v:174936.3-174937.41" + process $proc$libresoc.v:174936$10276 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:173306.3-173307.39" - process $proc$libresoc.v:173306$10229 + attribute \src "libresoc.v:174938.3-174939.39" + process $proc$libresoc.v:174938$10277 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:173308.3-173309.29" - process $proc$libresoc.v:173308$10230 + attribute \src "libresoc.v:174940.3-174941.29" + process $proc$libresoc.v:174940$10278 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:173310.3-173311.21" - process $proc$libresoc.v:173310$10231 + attribute \src "libresoc.v:174942.3-174943.21" + process $proc$libresoc.v:174942$10279 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:173312.3-173313.21" - process $proc$libresoc.v:173312$10232 + attribute \src "libresoc.v:174944.3-174945.21" + process $proc$libresoc.v:174944$10280 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:173314.3-173315.59" - process $proc$libresoc.v:173314$10233 + attribute \src "libresoc.v:174946.3-174947.59" + process $proc$libresoc.v:174946$10281 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:173316.3-173317.55" - process $proc$libresoc.v:173316$10234 + attribute \src "libresoc.v:174948.3-174949.55" + process $proc$libresoc.v:174948$10282 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:173318.3-173319.69" - process $proc$libresoc.v:173318$10235 + attribute \src "libresoc.v:174950.3-174951.69" + process $proc$libresoc.v:174950$10283 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:173320.3-173321.65" - process $proc$libresoc.v:173320$10236 + attribute \src "libresoc.v:174952.3-174953.65" + process $proc$libresoc.v:174952$10284 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:173322.3-173323.53" - process $proc$libresoc.v:173322$10237 + attribute \src "libresoc.v:174954.3-174955.53" + process $proc$libresoc.v:174954$10285 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:173324.3-173325.53" - process $proc$libresoc.v:173324$10238 + attribute \src "libresoc.v:174956.3-174957.53" + process $proc$libresoc.v:174956$10286 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:173326.3-173327.53" - process $proc$libresoc.v:173326$10239 + attribute \src "libresoc.v:174958.3-174959.53" + process $proc$libresoc.v:174958$10287 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:173328.3-173329.53" - process $proc$libresoc.v:173328$10240 + attribute \src "libresoc.v:174960.3-174961.53" + process $proc$libresoc.v:174960$10288 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:173330.3-173331.59" - process $proc$libresoc.v:173330$10241 + attribute \src "libresoc.v:174962.3-174963.59" + process $proc$libresoc.v:174962$10289 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:173332.3-173333.53" - process $proc$libresoc.v:173332$10242 + attribute \src "libresoc.v:174964.3-174965.53" + process $proc$libresoc.v:174964$10290 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:173334.3-173335.63" - process $proc$libresoc.v:173334$10243 + attribute \src "libresoc.v:174966.3-174967.63" + process $proc$libresoc.v:174966$10291 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:173336.3-173337.61" - process $proc$libresoc.v:173336$10244 + attribute \src "libresoc.v:174968.3-174969.61" + process $proc$libresoc.v:174968$10292 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:173338.3-173339.59" - process $proc$libresoc.v:173338$10245 + attribute \src "libresoc.v:174970.3-174971.59" + process $proc$libresoc.v:174970$10293 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:173340.3-173341.65" - process $proc$libresoc.v:173340$10246 + attribute \src "libresoc.v:174972.3-174973.65" + process $proc$libresoc.v:174972$10294 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:173342.3-173343.57" - process $proc$libresoc.v:173342$10247 + attribute \src "libresoc.v:174974.3-174975.57" + process $proc$libresoc.v:174974$10295 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:173344.3-173345.59" - process $proc$libresoc.v:173344$10248 + attribute \src "libresoc.v:174976.3-174977.59" + process $proc$libresoc.v:174976$10296 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:173346.3-173347.57" - process $proc$libresoc.v:173346$10249 + attribute \src "libresoc.v:174978.3-174979.57" + process $proc$libresoc.v:174978$10297 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:173348.3-173349.49" - process $proc$libresoc.v:173348$10250 + attribute \src "libresoc.v:174980.3-174981.49" + process $proc$libresoc.v:174980$10298 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:173350.3-173351.27" - process $proc$libresoc.v:173350$10251 + attribute \src "libresoc.v:174982.3-174983.27" + process $proc$libresoc.v:174982$10299 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:173352.3-173353.29" - process $proc$libresoc.v:173352$10252 + attribute \src "libresoc.v:174984.3-174985.29" + process $proc$libresoc.v:174984$10300 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:173460.3-173472.6" - process $proc$libresoc.v:173460$10253 + attribute \src "libresoc.v:175092.3-175104.6" + process $proc$libresoc.v:175092$10301 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$10254 $1\divisor_neg$next[0:0]$10255 - attribute \src "libresoc.v:173461.5-173461.29" + assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:175093.5-175093.29" switch \initial - attribute \src "libresoc.v:173461.9-173461.17" + attribute \src "libresoc.v:175093.9-175093.17" case 1'1 case end @@ -356032,25 +358529,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10254 + update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 end - attribute \src "libresoc.v:173473.3-173485.6" - process $proc$libresoc.v:173473$10256 + attribute \src "libresoc.v:175105.3-175117.6" + process $proc$libresoc.v:175105$10304 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$10257 $1\dividend_neg$next[0:0]$10258 - attribute \src "libresoc.v:173474.5-173474.29" + assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:175106.5-175106.29" switch \initial - attribute \src "libresoc.v:173474.9-173474.17" + attribute \src "libresoc.v:175106.9-175106.17" case 1'1 case end @@ -356059,25 +358556,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10257 + update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 end - attribute \src "libresoc.v:173486.3-173498.6" - process $proc$libresoc.v:173486$10259 + attribute \src "libresoc.v:175118.3-175130.6" + process $proc$libresoc.v:175118$10307 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10260 $1\dive_abs_ov32$next[0:0]$10261 - attribute \src "libresoc.v:173487.5-173487.29" + assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:175119.5-175119.29" switch \initial - attribute \src "libresoc.v:173487.9-173487.17" + attribute \src "libresoc.v:175119.9-175119.17" case 1'1 case end @@ -356086,25 +358583,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10260 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 end - attribute \src "libresoc.v:173499.3-173511.6" - process $proc$libresoc.v:173499$10262 + attribute \src "libresoc.v:175131.3-175143.6" + process $proc$libresoc.v:175131$10310 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10263 $1\dive_abs_ov64$next[0:0]$10264 - attribute \src "libresoc.v:173500.5-173500.29" + assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:175132.5-175132.29" switch \initial - attribute \src "libresoc.v:173500.9-173500.17" + attribute \src "libresoc.v:175132.9-175132.17" case 1'1 case end @@ -356113,25 +358610,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10263 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 end - attribute \src "libresoc.v:173512.3-173524.6" - process $proc$libresoc.v:173512$10265 + attribute \src "libresoc.v:175144.3-175156.6" + process $proc$libresoc.v:175144$10313 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$10266 $1\div_by_zero$next[0:0]$10267 - attribute \src "libresoc.v:173513.5-173513.29" + assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:175145.5-175145.29" switch \initial - attribute \src "libresoc.v:173513.9-173513.17" + attribute \src "libresoc.v:175145.9-175145.17" case 1'1 case end @@ -356140,25 +358637,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10266 + update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 end - attribute \src "libresoc.v:173525.3-173537.6" - process $proc$libresoc.v:173525$10268 + attribute \src "libresoc.v:175157.3-175169.6" + process $proc$libresoc.v:175157$10316 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$10269 $1\dividend$next[127:0]$10270 - attribute \src "libresoc.v:173526.5-173526.29" + assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:175158.5-175158.29" switch \initial - attribute \src "libresoc.v:173526.9-173526.17" + attribute \src "libresoc.v:175158.9-175158.17" case 1'1 case end @@ -356167,25 +358664,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$10270 \dividend$97 + assign $1\dividend$next[127:0]$10318 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$10270 \dividend$97 + assign $1\dividend$next[127:0]$10318 \dividend$97 case - assign $1\dividend$next[127:0]$10270 \dividend + assign $1\dividend$next[127:0]$10318 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$10269 + update \dividend$next $0\dividend$next[127:0]$10317 end - attribute \src "libresoc.v:173538.3-173550.6" - process $proc$libresoc.v:173538$10271 + attribute \src "libresoc.v:175170.3-175182.6" + process $proc$libresoc.v:175170$10319 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$10272 $1\divisor_radicand$next[63:0]$10273 - attribute \src "libresoc.v:173539.5-173539.29" + assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:175171.5-175171.29" switch \initial - attribute \src "libresoc.v:173539.9-173539.17" + attribute \src "libresoc.v:175171.9-175171.17" case 1'1 case end @@ -356194,25 +358691,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10272 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 end - attribute \src "libresoc.v:173551.3-173563.6" - process $proc$libresoc.v:173551$10274 + attribute \src "libresoc.v:175183.3-175195.6" + process $proc$libresoc.v:175183$10322 assign { } { } assign { } { } - assign $0\operation$next[1:0]$10275 $1\operation$next[1:0]$10276 - attribute \src "libresoc.v:173552.5-173552.29" + assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:175184.5-175184.29" switch \initial - attribute \src "libresoc.v:173552.9-173552.17" + attribute \src "libresoc.v:175184.9-175184.17" case 1'1 case end @@ -356221,26 +358718,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$10276 \operation$99 + assign $1\operation$next[1:0]$10324 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$10276 \operation$99 + assign $1\operation$next[1:0]$10324 \operation$99 case - assign $1\operation$next[1:0]$10276 \operation + assign $1\operation$next[1:0]$10324 \operation end sync always - update \operation$next $0\operation$next[1:0]$10275 + update \operation$next $0\operation$next[1:0]$10323 end - attribute \src "libresoc.v:173564.3-173581.6" - process $proc$libresoc.v:173564$10277 + attribute \src "libresoc.v:175196.3-175213.6" + process $proc$libresoc.v:175196$10325 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$10278 $2\r_busy$next[0:0]$10280 - attribute \src "libresoc.v:173565.5-173565.29" + assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:175197.5-175197.29" switch \initial - attribute \src "libresoc.v:173565.9-173565.17" + attribute \src "libresoc.v:175197.9-175197.17" case 1'1 case end @@ -356249,34 +358746,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$10279 1'1 + assign $1\r_busy$next[0:0]$10327 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$10279 1'0 + assign $1\r_busy$next[0:0]$10327 1'0 case - assign $1\r_busy$next[0:0]$10279 \r_busy + assign $1\r_busy$next[0:0]$10327 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$10280 1'0 + assign $2\r_busy$next[0:0]$10328 1'0 case - assign $2\r_busy$next[0:0]$10280 $1\r_busy$next[0:0]$10279 + assign $2\r_busy$next[0:0]$10328 $1\r_busy$next[0:0]$10327 end sync always - update \r_busy$next $0\r_busy$next[0:0]$10278 + update \r_busy$next $0\r_busy$next[0:0]$10326 end - attribute \src "libresoc.v:173582.3-173594.6" - process $proc$libresoc.v:173582$10281 + attribute \src "libresoc.v:175214.3-175226.6" + process $proc$libresoc.v:175214$10329 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10282 $1\muxid$next[1:0]$10283 - attribute \src "libresoc.v:173583.5-173583.29" + assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:175215.5-175215.29" switch \initial - attribute \src "libresoc.v:173583.9-173583.17" + attribute \src "libresoc.v:175215.9-175215.17" case 1'1 case end @@ -356285,19 +358782,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$10283 \muxid$68 + assign $1\muxid$next[1:0]$10331 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$10283 \muxid$68 + assign $1\muxid$next[1:0]$10331 \muxid$68 case - assign $1\muxid$next[1:0]$10283 \muxid + assign $1\muxid$next[1:0]$10331 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$10282 + update \muxid$next $0\muxid$next[1:0]$10330 end - attribute \src "libresoc.v:173595.3-173636.6" - process $proc$libresoc.v:173595$10284 + attribute \src "libresoc.v:175227.3-175268.6" + process $proc$libresoc.v:175227$10332 assign { } { } assign { } { } assign { } { } @@ -356334,33 +358831,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$10285 $1\logical_op__data_len$next[3:0]$10303 - assign $0\logical_op__fn_unit$next[13:0]$10286 $1\logical_op__fn_unit$next[13:0]$10304 + assign $0\logical_op__data_len$next[3:0]$10333 $1\logical_op__data_len$next[3:0]$10351 + assign $0\logical_op__fn_unit$next[13:0]$10334 $1\logical_op__fn_unit$next[13:0]$10352 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10289 $1\logical_op__input_carry$next[1:0]$10307 - assign $0\logical_op__insn$next[31:0]$10290 $1\logical_op__insn$next[31:0]$10308 - assign $0\logical_op__insn_type$next[6:0]$10291 $1\logical_op__insn_type$next[6:0]$10309 - assign $0\logical_op__invert_in$next[0:0]$10292 $1\logical_op__invert_in$next[0:0]$10310 - assign $0\logical_op__invert_out$next[0:0]$10293 $1\logical_op__invert_out$next[0:0]$10311 - assign $0\logical_op__is_32bit$next[0:0]$10294 $1\logical_op__is_32bit$next[0:0]$10312 - assign $0\logical_op__is_signed$next[0:0]$10295 $1\logical_op__is_signed$next[0:0]$10313 + assign $0\logical_op__input_carry$next[1:0]$10337 $1\logical_op__input_carry$next[1:0]$10355 + assign $0\logical_op__insn$next[31:0]$10338 $1\logical_op__insn$next[31:0]$10356 + assign $0\logical_op__insn_type$next[6:0]$10339 $1\logical_op__insn_type$next[6:0]$10357 + assign $0\logical_op__invert_in$next[0:0]$10340 $1\logical_op__invert_in$next[0:0]$10358 + assign $0\logical_op__invert_out$next[0:0]$10341 $1\logical_op__invert_out$next[0:0]$10359 + assign $0\logical_op__is_32bit$next[0:0]$10342 $1\logical_op__is_32bit$next[0:0]$10360 + assign $0\logical_op__is_signed$next[0:0]$10343 $1\logical_op__is_signed$next[0:0]$10361 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10298 $1\logical_op__output_carry$next[0:0]$10316 + assign $0\logical_op__output_carry$next[0:0]$10346 $1\logical_op__output_carry$next[0:0]$10364 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10301 $1\logical_op__write_cr0$next[0:0]$10319 - assign $0\logical_op__zero_a$next[0:0]$10302 $1\logical_op__zero_a$next[0:0]$10320 - assign $0\logical_op__imm_data__data$next[63:0]$10287 $2\logical_op__imm_data__data$next[63:0]$10321 - assign $0\logical_op__imm_data__ok$next[0:0]$10288 $2\logical_op__imm_data__ok$next[0:0]$10322 - assign $0\logical_op__oe__oe$next[0:0]$10296 $2\logical_op__oe__oe$next[0:0]$10323 - assign $0\logical_op__oe__ok$next[0:0]$10297 $2\logical_op__oe__ok$next[0:0]$10324 - assign $0\logical_op__rc__ok$next[0:0]$10299 $2\logical_op__rc__ok$next[0:0]$10325 - assign $0\logical_op__rc__rc$next[0:0]$10300 $2\logical_op__rc__rc$next[0:0]$10326 - attribute \src "libresoc.v:173596.5-173596.29" + assign $0\logical_op__write_cr0$next[0:0]$10349 $1\logical_op__write_cr0$next[0:0]$10367 + assign $0\logical_op__zero_a$next[0:0]$10350 $1\logical_op__zero_a$next[0:0]$10368 + assign $0\logical_op__imm_data__data$next[63:0]$10335 $2\logical_op__imm_data__data$next[63:0]$10369 + assign $0\logical_op__imm_data__ok$next[0:0]$10336 $2\logical_op__imm_data__ok$next[0:0]$10370 + assign $0\logical_op__oe__oe$next[0:0]$10344 $2\logical_op__oe__oe$next[0:0]$10371 + assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 + assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 + assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175228.5-175228.29" switch \initial - attribute \src "libresoc.v:173596.9-173596.17" + attribute \src "libresoc.v:175228.9-175228.17" case 1'1 case end @@ -356386,7 +358883,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -356407,26 +358904,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$10303 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$10304 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10305 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10306 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10307 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10308 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10309 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10310 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10311 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10312 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10313 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10314 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10315 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10316 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10317 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10318 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10319 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10320 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10351 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10352 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10353 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10354 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10355 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10356 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10357 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10358 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10359 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10360 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10361 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10362 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10363 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10364 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10365 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10366 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10367 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10368 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -356438,48 +358935,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10321 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10322 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10326 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10325 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10323 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10324 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10369 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10374 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10373 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10371 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10372 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10321 $1\logical_op__imm_data__data$next[63:0]$10305 - assign $2\logical_op__imm_data__ok$next[0:0]$10322 $1\logical_op__imm_data__ok$next[0:0]$10306 - assign $2\logical_op__oe__oe$next[0:0]$10323 $1\logical_op__oe__oe$next[0:0]$10314 - assign $2\logical_op__oe__ok$next[0:0]$10324 $1\logical_op__oe__ok$next[0:0]$10315 - assign $2\logical_op__rc__ok$next[0:0]$10325 $1\logical_op__rc__ok$next[0:0]$10317 - assign $2\logical_op__rc__rc$next[0:0]$10326 $1\logical_op__rc__rc$next[0:0]$10318 + assign $2\logical_op__imm_data__data$next[63:0]$10369 $1\logical_op__imm_data__data$next[63:0]$10353 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 $1\logical_op__imm_data__ok$next[0:0]$10354 + assign $2\logical_op__oe__oe$next[0:0]$10371 $1\logical_op__oe__oe$next[0:0]$10362 + assign $2\logical_op__oe__ok$next[0:0]$10372 $1\logical_op__oe__ok$next[0:0]$10363 + assign $2\logical_op__rc__ok$next[0:0]$10373 $1\logical_op__rc__ok$next[0:0]$10365 + assign $2\logical_op__rc__rc$next[0:0]$10374 $1\logical_op__rc__rc$next[0:0]$10366 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10285 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10286 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10287 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10288 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10289 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10290 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10291 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10292 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10293 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10294 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10295 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10296 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10297 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10298 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10299 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10300 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10301 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10302 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10333 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10334 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10335 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10336 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10337 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10338 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10339 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10340 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10341 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10342 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10343 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10344 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10345 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10346 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10347 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10348 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 end - attribute \src "libresoc.v:173637.3-173649.6" - process $proc$libresoc.v:173637$10327 + attribute \src "libresoc.v:175269.3-175281.6" + process $proc$libresoc.v:175269$10375 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10328 $1\ra$next[63:0]$10329 - attribute \src "libresoc.v:173638.5-173638.29" + assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:175270.5-175270.29" switch \initial - attribute \src "libresoc.v:173638.9-173638.17" + attribute \src "libresoc.v:175270.9-175270.17" case 1'1 case end @@ -356488,25 +358985,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$10329 \ra$87 + assign $1\ra$next[63:0]$10377 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$10329 \ra$87 + assign $1\ra$next[63:0]$10377 \ra$87 case - assign $1\ra$next[63:0]$10329 \ra + assign $1\ra$next[63:0]$10377 \ra end sync always - update \ra$next $0\ra$next[63:0]$10328 + update \ra$next $0\ra$next[63:0]$10376 end - attribute \src "libresoc.v:173650.3-173662.6" - process $proc$libresoc.v:173650$10330 + attribute \src "libresoc.v:175282.3-175294.6" + process $proc$libresoc.v:175282$10378 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10331 $1\rb$next[63:0]$10332 - attribute \src "libresoc.v:173651.5-173651.29" + assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:175283.5-175283.29" switch \initial - attribute \src "libresoc.v:173651.9-173651.17" + attribute \src "libresoc.v:175283.9-175283.17" case 1'1 case end @@ -356515,25 +359012,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$10332 \rb$89 + assign $1\rb$next[63:0]$10380 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$10332 \rb$89 + assign $1\rb$next[63:0]$10380 \rb$89 case - assign $1\rb$next[63:0]$10332 \rb + assign $1\rb$next[63:0]$10380 \rb end sync always - update \rb$next $0\rb$next[63:0]$10331 + update \rb$next $0\rb$next[63:0]$10379 end - attribute \src "libresoc.v:173663.3-173675.6" - process $proc$libresoc.v:173663$10333 + attribute \src "libresoc.v:175295.3-175307.6" + process $proc$libresoc.v:175295$10381 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10334 $1\xer_so$next[0:0]$10335 - attribute \src "libresoc.v:173664.5-173664.29" + assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:175296.5-175296.29" switch \initial - attribute \src "libresoc.v:173664.9-173664.17" + attribute \src "libresoc.v:175296.9-175296.17" case 1'1 case end @@ -356542,18 +359039,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$10335 \xer_so$91 + assign $1\xer_so$next[0:0]$10383 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$10335 \xer_so$91 + assign $1\xer_so$next[0:0]$10383 \xer_so$91 case - assign $1\xer_so$next[0:0]$10335 \xer_so + assign $1\xer_so$next[0:0]$10383 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$10334 + update \xer_so$next $0\xer_so$next[0:0]$10382 end - connect \$66 $and$libresoc.v:173291$10221_Y + connect \$66 $and$libresoc.v:174923$10269_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -356585,27 +359082,27 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:173710.1-173754.10" +attribute \src "libresoc.v:175342.1-175386.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" module \pll - attribute \src "libresoc.v:173711.7-173711.20" + attribute \src "libresoc.v:175343.7-175343.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173743.3-173752.6" + attribute \src "libresoc.v:175375.3-175384.6" wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:173733.3-173742.6" + attribute \src "libresoc.v:175365.3-175374.6" wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:173743.3-173752.6" + attribute \src "libresoc.v:175375.3-175384.6" wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:173733.3-173742.6" + attribute \src "libresoc.v:175365.3-175374.6" wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:173730.17-173730.105" - wire $eq$libresoc.v:173730$10368_Y - attribute \src "libresoc.v:173731.17-173731.105" - wire $eq$libresoc.v:173731$10369_Y - attribute \src "libresoc.v:173732.17-173732.98" - wire $not$libresoc.v:173732$10370_Y + attribute \src "libresoc.v:175362.17-175362.105" + wire $eq$libresoc.v:175362$10416_Y + attribute \src "libresoc.v:175363.17-175363.105" + wire $eq$libresoc.v:175363$10417_Y + attribute \src "libresoc.v:175364.17-175364.98" + wire $not$libresoc.v:175364$10418_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" @@ -356618,14 +359115,14 @@ module \pll wire output 5 \clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:173711.7-173711.15" + attribute \src "libresoc.v:175343.7-175343.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire output 2 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" wire output 4 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:173730$10368 + cell $eq $eq$libresoc.v:175362$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -356633,10 +359130,10 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:173730$10368_Y + connect \Y $eq$libresoc.v:175362$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:173731$10369 + cell $eq $eq$libresoc.v:175363$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -356644,32 +359141,32 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:173731$10369_Y + connect \Y $eq$libresoc.v:175363$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:173732$10370 + cell $not $not$libresoc.v:175364$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clk_24_i - connect \Y $not$libresoc.v:173732$10370_Y + connect \Y $not$libresoc.v:175364$10418_Y end - attribute \src "libresoc.v:173711.7-173711.20" - process $proc$libresoc.v:173711$10373 + attribute \src "libresoc.v:175343.7-175343.20" + process $proc$libresoc.v:175343$10421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173733.3-173742.6" - process $proc$libresoc.v:173733$10371 + attribute \src "libresoc.v:175365.3-175374.6" + process $proc$libresoc.v:175365$10419 assign { } { } assign { } { } assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:173734.5-173734.29" + attribute \src "libresoc.v:175366.5-175366.29" switch \initial - attribute \src "libresoc.v:173734.9-173734.17" + attribute \src "libresoc.v:175366.9-175366.17" case 1'1 case end @@ -356685,14 +359182,14 @@ module \pll sync always update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:173743.3-173752.6" - process $proc$libresoc.v:173743$10372 + attribute \src "libresoc.v:175375.3-175384.6" + process $proc$libresoc.v:175375$10420 assign { } { } assign { } { } assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:173744.5-173744.29" + attribute \src "libresoc.v:175376.5-175376.29" switch \initial - attribute \src "libresoc.v:173744.9-173744.17" + attribute \src "libresoc.v:175376.9-175376.17" case 1'1 case end @@ -356708,196 +359205,196 @@ module \pll sync always update \pll_18_o $0\pll_18_o[0:0] end - connect \$1 $eq$libresoc.v:173730$10368_Y - connect \$3 $eq$libresoc.v:173731$10369_Y - connect \$5 $not$libresoc.v:173732$10370_Y + connect \$1 $eq$libresoc.v:175362$10416_Y + connect \$3 $eq$libresoc.v:175363$10417_Y + connect \$5 $not$libresoc.v:175364$10418_Y connect \clk_pll_o \clk_24_i end -attribute \src "libresoc.v:173758.1-174400.10" +attribute \src "libresoc.v:175390.1-176032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:173759.7-173759.20" + attribute \src "libresoc.v:175391.7-175391.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174247.3-174273.6" + attribute \src "libresoc.v:175879.3-175905.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:174247.3-174273.6" + attribute \src "libresoc.v:175879.3-175905.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:174171.19-174171.132" - wire width 4 $add$libresoc.v:174171$10374_Y - attribute \src "libresoc.v:174172.19-174172.132" - wire width 4 $add$libresoc.v:174172$10375_Y - attribute \src "libresoc.v:174173.19-174173.132" - wire width 4 $add$libresoc.v:174173$10376_Y - attribute \src "libresoc.v:174174.19-174174.132" - wire width 4 $add$libresoc.v:174174$10377_Y - attribute \src "libresoc.v:174175.19-174175.134" - wire width 4 $add$libresoc.v:174175$10378_Y - attribute \src "libresoc.v:174176.19-174176.134" - wire width 4 $add$libresoc.v:174176$10379_Y - attribute \src "libresoc.v:174177.18-174177.125" - wire width 3 $add$libresoc.v:174177$10380_Y - attribute \src "libresoc.v:174178.19-174178.134" - wire width 4 $add$libresoc.v:174178$10381_Y - attribute \src "libresoc.v:174179.19-174179.134" - wire width 4 $add$libresoc.v:174179$10382_Y - attribute \src "libresoc.v:174180.19-174180.134" - wire width 4 $add$libresoc.v:174180$10383_Y - attribute \src "libresoc.v:174181.19-174181.134" - wire width 4 $add$libresoc.v:174181$10384_Y - attribute \src "libresoc.v:174182.19-174182.134" - wire width 4 $add$libresoc.v:174182$10385_Y - attribute \src "libresoc.v:174183.19-174183.134" - wire width 4 $add$libresoc.v:174183$10386_Y - attribute \src "libresoc.v:174184.19-174184.134" - wire width 4 $add$libresoc.v:174184$10387_Y - attribute \src "libresoc.v:174185.19-174185.134" - wire width 4 $add$libresoc.v:174185$10388_Y - attribute \src "libresoc.v:174186.19-174186.134" - wire width 4 $add$libresoc.v:174186$10389_Y - attribute \src "libresoc.v:174187.19-174187.132" - wire width 5 $add$libresoc.v:174187$10390_Y - attribute \src "libresoc.v:174188.18-174188.125" - wire width 3 $add$libresoc.v:174188$10391_Y - attribute \src "libresoc.v:174189.19-174189.132" - wire width 5 $add$libresoc.v:174189$10392_Y - attribute \src "libresoc.v:174190.19-174190.132" - wire width 5 $add$libresoc.v:174190$10393_Y - attribute \src "libresoc.v:174191.19-174191.132" - wire width 5 $add$libresoc.v:174191$10394_Y - attribute \src "libresoc.v:174192.19-174192.132" - wire width 5 $add$libresoc.v:174192$10395_Y - attribute \src "libresoc.v:174193.19-174193.134" - wire width 5 $add$libresoc.v:174193$10396_Y - attribute \src "libresoc.v:174194.19-174194.134" - wire width 5 $add$libresoc.v:174194$10397_Y - attribute \src "libresoc.v:174195.19-174195.134" - wire width 5 $add$libresoc.v:174195$10398_Y - attribute \src "libresoc.v:174196.19-174196.132" - wire width 6 $add$libresoc.v:174196$10399_Y - attribute \src "libresoc.v:174197.19-174197.132" - wire width 6 $add$libresoc.v:174197$10400_Y - attribute \src "libresoc.v:174198.19-174198.132" - wire width 6 $add$libresoc.v:174198$10401_Y - attribute \src "libresoc.v:174199.18-174199.127" - wire width 3 $add$libresoc.v:174199$10402_Y - attribute \src "libresoc.v:174200.19-174200.132" - wire width 6 $add$libresoc.v:174200$10403_Y - attribute \src "libresoc.v:174201.19-174201.132" - wire width 7 $add$libresoc.v:174201$10404_Y - attribute \src "libresoc.v:174202.19-174202.132" - wire width 7 $add$libresoc.v:174202$10405_Y - attribute \src "libresoc.v:174203.19-174203.132" - wire width 8 $add$libresoc.v:174203$10406_Y - attribute \src "libresoc.v:174214.18-174214.127" - wire width 3 $add$libresoc.v:174214$10425_Y - attribute \src "libresoc.v:174218.18-174218.127" - wire width 3 $add$libresoc.v:174218$10432_Y - attribute \src "libresoc.v:174219.18-174219.127" - wire width 3 $add$libresoc.v:174219$10433_Y - attribute \src "libresoc.v:174220.17-174220.124" - wire width 3 $add$libresoc.v:174220$10434_Y - attribute \src "libresoc.v:174221.18-174221.127" - wire width 3 $add$libresoc.v:174221$10435_Y - attribute \src "libresoc.v:174222.18-174222.127" - wire width 3 $add$libresoc.v:174222$10436_Y - attribute \src "libresoc.v:174223.18-174223.127" - wire width 3 $add$libresoc.v:174223$10437_Y - attribute \src "libresoc.v:174224.18-174224.127" - wire width 3 $add$libresoc.v:174224$10438_Y - attribute \src "libresoc.v:174225.18-174225.127" - wire width 3 $add$libresoc.v:174225$10439_Y - attribute \src "libresoc.v:174226.18-174226.127" - wire width 3 $add$libresoc.v:174226$10440_Y - attribute \src "libresoc.v:174227.18-174227.127" - wire width 3 $add$libresoc.v:174227$10441_Y - attribute \src "libresoc.v:174228.18-174228.127" - wire width 3 $add$libresoc.v:174228$10442_Y - attribute \src "libresoc.v:174229.18-174229.127" - wire width 3 $add$libresoc.v:174229$10443_Y - attribute \src "libresoc.v:174230.18-174230.127" - wire width 3 $add$libresoc.v:174230$10444_Y - attribute \src "libresoc.v:174231.17-174231.124" - wire width 3 $add$libresoc.v:174231$10445_Y - attribute \src "libresoc.v:174232.18-174232.127" - wire width 3 $add$libresoc.v:174232$10446_Y - attribute \src "libresoc.v:174233.18-174233.127" - wire width 3 $add$libresoc.v:174233$10447_Y - attribute \src "libresoc.v:174234.18-174234.127" - wire width 3 $add$libresoc.v:174234$10448_Y - attribute \src "libresoc.v:174235.18-174235.127" - wire width 3 $add$libresoc.v:174235$10449_Y - attribute \src "libresoc.v:174236.18-174236.127" - wire width 3 $add$libresoc.v:174236$10450_Y - attribute \src "libresoc.v:174237.18-174237.127" - wire width 3 $add$libresoc.v:174237$10451_Y - attribute \src "libresoc.v:174238.18-174238.127" - wire width 3 $add$libresoc.v:174238$10452_Y - attribute \src "libresoc.v:174239.18-174239.127" - wire width 3 $add$libresoc.v:174239$10453_Y - attribute \src "libresoc.v:174240.18-174240.127" - wire width 3 $add$libresoc.v:174240$10454_Y - attribute \src "libresoc.v:174241.18-174241.127" - wire width 3 $add$libresoc.v:174241$10455_Y - attribute \src "libresoc.v:174242.17-174242.124" - wire width 3 $add$libresoc.v:174242$10456_Y - attribute \src "libresoc.v:174243.18-174243.127" - wire width 3 $add$libresoc.v:174243$10457_Y - attribute \src "libresoc.v:174244.18-174244.127" - wire width 3 $add$libresoc.v:174244$10458_Y - attribute \src "libresoc.v:174245.18-174245.127" - wire width 3 $add$libresoc.v:174245$10459_Y - attribute \src "libresoc.v:174246.18-174246.131" - wire width 4 $add$libresoc.v:174246$10460_Y - attribute \src "libresoc.v:174204.19-174204.111" - wire $eq$libresoc.v:174204$10407_Y - attribute \src "libresoc.v:174205.19-174205.111" - wire $eq$libresoc.v:174205$10408_Y - attribute \src "libresoc.v:174206.19-174206.104" - wire width 8 $extend$libresoc.v:174206$10409_Y - attribute \src "libresoc.v:174207.19-174207.104" - wire width 8 $extend$libresoc.v:174207$10411_Y - attribute \src "libresoc.v:174208.19-174208.104" - wire width 8 $extend$libresoc.v:174208$10413_Y - attribute \src "libresoc.v:174209.19-174209.104" - wire width 8 $extend$libresoc.v:174209$10415_Y - attribute \src "libresoc.v:174210.19-174210.104" - wire width 8 $extend$libresoc.v:174210$10417_Y - attribute \src "libresoc.v:174211.19-174211.104" - wire width 8 $extend$libresoc.v:174211$10419_Y - attribute \src "libresoc.v:174212.19-174212.104" - wire width 8 $extend$libresoc.v:174212$10421_Y - attribute \src "libresoc.v:174213.19-174213.104" - wire width 8 $extend$libresoc.v:174213$10423_Y - attribute \src "libresoc.v:174215.19-174215.104" - wire width 32 $extend$libresoc.v:174215$10426_Y - attribute \src "libresoc.v:174216.19-174216.104" - wire width 32 $extend$libresoc.v:174216$10428_Y - attribute \src "libresoc.v:174217.19-174217.104" - wire width 64 $extend$libresoc.v:174217$10430_Y - attribute \src "libresoc.v:174206.19-174206.104" - wire width 8 $pos$libresoc.v:174206$10410_Y - attribute \src "libresoc.v:174207.19-174207.104" - wire width 8 $pos$libresoc.v:174207$10412_Y - attribute \src "libresoc.v:174208.19-174208.104" - wire width 8 $pos$libresoc.v:174208$10414_Y - attribute \src "libresoc.v:174209.19-174209.104" - wire width 8 $pos$libresoc.v:174209$10416_Y - attribute \src "libresoc.v:174210.19-174210.104" - wire width 8 $pos$libresoc.v:174210$10418_Y - attribute \src "libresoc.v:174211.19-174211.104" - wire width 8 $pos$libresoc.v:174211$10420_Y - attribute \src "libresoc.v:174212.19-174212.104" - wire width 8 $pos$libresoc.v:174212$10422_Y - attribute \src "libresoc.v:174213.19-174213.104" - wire width 8 $pos$libresoc.v:174213$10424_Y - attribute \src "libresoc.v:174215.19-174215.104" - wire width 32 $pos$libresoc.v:174215$10427_Y - attribute \src "libresoc.v:174216.19-174216.104" - wire width 32 $pos$libresoc.v:174216$10429_Y - attribute \src "libresoc.v:174217.19-174217.104" - wire width 64 $pos$libresoc.v:174217$10431_Y + attribute \src "libresoc.v:175803.19-175803.132" + wire width 4 $add$libresoc.v:175803$10422_Y + attribute \src "libresoc.v:175804.19-175804.132" + wire width 4 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"libresoc.v:175825.19-175825.134" + wire width 5 $add$libresoc.v:175825$10444_Y + attribute \src "libresoc.v:175826.19-175826.134" + wire width 5 $add$libresoc.v:175826$10445_Y + attribute \src "libresoc.v:175827.19-175827.134" + wire width 5 $add$libresoc.v:175827$10446_Y + attribute \src "libresoc.v:175828.19-175828.132" + wire width 6 $add$libresoc.v:175828$10447_Y + attribute \src "libresoc.v:175829.19-175829.132" + wire width 6 $add$libresoc.v:175829$10448_Y + attribute \src "libresoc.v:175830.19-175830.132" + wire width 6 $add$libresoc.v:175830$10449_Y + attribute \src "libresoc.v:175831.18-175831.127" + wire width 3 $add$libresoc.v:175831$10450_Y + attribute \src "libresoc.v:175832.19-175832.132" + wire width 6 $add$libresoc.v:175832$10451_Y + attribute \src "libresoc.v:175833.19-175833.132" + wire width 7 $add$libresoc.v:175833$10452_Y + attribute \src "libresoc.v:175834.19-175834.132" + wire width 7 $add$libresoc.v:175834$10453_Y + attribute \src "libresoc.v:175835.19-175835.132" + wire width 8 $add$libresoc.v:175835$10454_Y + attribute \src "libresoc.v:175846.18-175846.127" + wire width 3 $add$libresoc.v:175846$10473_Y + attribute \src "libresoc.v:175850.18-175850.127" + wire width 3 $add$libresoc.v:175850$10480_Y + attribute \src "libresoc.v:175851.18-175851.127" + wire width 3 $add$libresoc.v:175851$10481_Y + attribute \src "libresoc.v:175852.17-175852.124" + wire width 3 $add$libresoc.v:175852$10482_Y + attribute \src "libresoc.v:175853.18-175853.127" + wire width 3 $add$libresoc.v:175853$10483_Y + attribute \src "libresoc.v:175854.18-175854.127" + wire width 3 $add$libresoc.v:175854$10484_Y + attribute \src "libresoc.v:175855.18-175855.127" + wire width 3 $add$libresoc.v:175855$10485_Y + attribute \src "libresoc.v:175856.18-175856.127" + wire width 3 $add$libresoc.v:175856$10486_Y + attribute \src "libresoc.v:175857.18-175857.127" + wire width 3 $add$libresoc.v:175857$10487_Y + attribute \src "libresoc.v:175858.18-175858.127" + wire width 3 $add$libresoc.v:175858$10488_Y + attribute \src "libresoc.v:175859.18-175859.127" + wire width 3 $add$libresoc.v:175859$10489_Y + attribute \src "libresoc.v:175860.18-175860.127" + wire width 3 $add$libresoc.v:175860$10490_Y + attribute \src "libresoc.v:175861.18-175861.127" + wire width 3 $add$libresoc.v:175861$10491_Y + attribute \src "libresoc.v:175862.18-175862.127" + wire width 3 $add$libresoc.v:175862$10492_Y + attribute \src "libresoc.v:175863.17-175863.124" + wire width 3 $add$libresoc.v:175863$10493_Y + attribute \src "libresoc.v:175864.18-175864.127" + wire width 3 $add$libresoc.v:175864$10494_Y + attribute \src "libresoc.v:175865.18-175865.127" + wire width 3 $add$libresoc.v:175865$10495_Y + attribute \src "libresoc.v:175866.18-175866.127" + wire width 3 $add$libresoc.v:175866$10496_Y + attribute \src "libresoc.v:175867.18-175867.127" + wire width 3 $add$libresoc.v:175867$10497_Y + attribute \src "libresoc.v:175868.18-175868.127" + wire width 3 $add$libresoc.v:175868$10498_Y + attribute \src "libresoc.v:175869.18-175869.127" + wire width 3 $add$libresoc.v:175869$10499_Y + attribute \src "libresoc.v:175870.18-175870.127" + wire width 3 $add$libresoc.v:175870$10500_Y + attribute \src "libresoc.v:175871.18-175871.127" + wire width 3 $add$libresoc.v:175871$10501_Y + attribute \src "libresoc.v:175872.18-175872.127" + wire width 3 $add$libresoc.v:175872$10502_Y + attribute \src "libresoc.v:175873.18-175873.127" + wire width 3 $add$libresoc.v:175873$10503_Y + attribute \src "libresoc.v:175874.17-175874.124" + wire width 3 $add$libresoc.v:175874$10504_Y + attribute \src "libresoc.v:175875.18-175875.127" + wire width 3 $add$libresoc.v:175875$10505_Y + attribute \src "libresoc.v:175876.18-175876.127" + wire width 3 $add$libresoc.v:175876$10506_Y + attribute \src "libresoc.v:175877.18-175877.127" + wire width 3 $add$libresoc.v:175877$10507_Y + attribute \src "libresoc.v:175878.18-175878.131" + wire width 4 $add$libresoc.v:175878$10508_Y + attribute \src "libresoc.v:175836.19-175836.111" + wire $eq$libresoc.v:175836$10455_Y + attribute \src "libresoc.v:175837.19-175837.111" + wire $eq$libresoc.v:175837$10456_Y + attribute \src "libresoc.v:175838.19-175838.104" + wire width 8 $extend$libresoc.v:175838$10457_Y + attribute \src "libresoc.v:175839.19-175839.104" + wire width 8 $extend$libresoc.v:175839$10459_Y + attribute \src "libresoc.v:175840.19-175840.104" + wire width 8 $extend$libresoc.v:175840$10461_Y + attribute \src "libresoc.v:175841.19-175841.104" + wire width 8 $extend$libresoc.v:175841$10463_Y + attribute \src "libresoc.v:175842.19-175842.104" + wire width 8 $extend$libresoc.v:175842$10465_Y + attribute \src "libresoc.v:175843.19-175843.104" + wire width 8 $extend$libresoc.v:175843$10467_Y + attribute \src "libresoc.v:175844.19-175844.104" + wire width 8 $extend$libresoc.v:175844$10469_Y + attribute \src "libresoc.v:175845.19-175845.104" + wire width 8 $extend$libresoc.v:175845$10471_Y + attribute \src "libresoc.v:175847.19-175847.104" + wire width 32 $extend$libresoc.v:175847$10474_Y + attribute \src "libresoc.v:175848.19-175848.104" + wire width 32 $extend$libresoc.v:175848$10476_Y + attribute \src "libresoc.v:175849.19-175849.104" + wire width 64 $extend$libresoc.v:175849$10478_Y + attribute \src "libresoc.v:175838.19-175838.104" + wire width 8 $pos$libresoc.v:175838$10458_Y + attribute \src "libresoc.v:175839.19-175839.104" + wire width 8 $pos$libresoc.v:175839$10460_Y + attribute \src "libresoc.v:175840.19-175840.104" + wire width 8 $pos$libresoc.v:175840$10462_Y + attribute \src "libresoc.v:175841.19-175841.104" + wire width 8 $pos$libresoc.v:175841$10464_Y + attribute \src "libresoc.v:175842.19-175842.104" + wire width 8 $pos$libresoc.v:175842$10466_Y + attribute \src "libresoc.v:175843.19-175843.104" + wire width 8 $pos$libresoc.v:175843$10468_Y + attribute \src "libresoc.v:175844.19-175844.104" + wire width 8 $pos$libresoc.v:175844$10470_Y + attribute \src "libresoc.v:175845.19-175845.104" + wire width 8 $pos$libresoc.v:175845$10472_Y + attribute \src "libresoc.v:175847.19-175847.104" + wire width 32 $pos$libresoc.v:175847$10475_Y + attribute \src "libresoc.v:175848.19-175848.104" + wire width 32 $pos$libresoc.v:175848$10477_Y + attribute \src "libresoc.v:175849.19-175849.104" + wire width 64 $pos$libresoc.v:175849$10479_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -357180,7 +359677,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:173759.7-173759.15" + attribute \src "libresoc.v:175391.7-175391.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -357311,7 +359808,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174171$10374 + cell $add $add$libresoc.v:175803$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357319,10 +359816,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:174171$10374_Y + connect \Y $add$libresoc.v:175803$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174172$10375 + cell $add $add$libresoc.v:175804$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357330,10 +359827,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:174172$10375_Y + connect \Y $add$libresoc.v:175804$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174173$10376 + cell $add $add$libresoc.v:175805$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357341,10 +359838,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:174173$10376_Y + connect \Y $add$libresoc.v:175805$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174174$10377 + cell $add $add$libresoc.v:175806$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357352,10 +359849,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:174174$10377_Y + connect \Y $add$libresoc.v:175806$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174175$10378 + cell $add $add$libresoc.v:175807$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357363,10 +359860,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:174175$10378_Y + connect \Y $add$libresoc.v:175807$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174176$10379 + cell $add $add$libresoc.v:175808$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357374,10 +359871,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:174176$10379_Y + connect \Y $add$libresoc.v:175808$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174177$10380 + cell $add $add$libresoc.v:175809$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357385,10 +359882,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:174177$10380_Y + connect \Y $add$libresoc.v:175809$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174178$10381 + cell $add $add$libresoc.v:175810$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357396,10 +359893,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:174178$10381_Y + connect \Y $add$libresoc.v:175810$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174179$10382 + cell $add $add$libresoc.v:175811$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357407,10 +359904,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:174179$10382_Y + connect \Y $add$libresoc.v:175811$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174180$10383 + cell $add $add$libresoc.v:175812$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357418,10 +359915,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:174180$10383_Y + connect \Y $add$libresoc.v:175812$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174181$10384 + cell $add $add$libresoc.v:175813$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357429,10 +359926,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:174181$10384_Y + connect \Y $add$libresoc.v:175813$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174182$10385 + cell $add $add$libresoc.v:175814$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357440,10 +359937,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:174182$10385_Y + connect \Y $add$libresoc.v:175814$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174183$10386 + cell $add $add$libresoc.v:175815$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357451,10 +359948,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:174183$10386_Y + connect \Y $add$libresoc.v:175815$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174184$10387 + cell $add $add$libresoc.v:175816$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357462,10 +359959,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:174184$10387_Y + connect \Y $add$libresoc.v:175816$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174185$10388 + cell $add $add$libresoc.v:175817$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357473,10 +359970,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:174185$10388_Y + connect \Y $add$libresoc.v:175817$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174186$10389 + cell $add $add$libresoc.v:175818$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357484,10 +359981,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:174186$10389_Y + connect \Y $add$libresoc.v:175818$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174187$10390 + cell $add $add$libresoc.v:175819$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357495,10 +359992,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:174187$10390_Y + connect \Y $add$libresoc.v:175819$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174188$10391 + cell $add $add$libresoc.v:175820$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357506,10 +360003,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:174188$10391_Y + connect \Y $add$libresoc.v:175820$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174189$10392 + cell $add $add$libresoc.v:175821$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357517,10 +360014,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:174189$10392_Y + connect \Y $add$libresoc.v:175821$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174190$10393 + cell $add $add$libresoc.v:175822$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357528,10 +360025,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:174190$10393_Y + connect \Y $add$libresoc.v:175822$10441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174191$10394 + cell $add $add$libresoc.v:175823$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357539,10 +360036,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:174191$10394_Y + connect \Y $add$libresoc.v:175823$10442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174192$10395 + cell $add $add$libresoc.v:175824$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357550,10 +360047,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:174192$10395_Y + connect \Y $add$libresoc.v:175824$10443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174193$10396 + cell $add $add$libresoc.v:175825$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357561,10 +360058,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:174193$10396_Y + connect \Y $add$libresoc.v:175825$10444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174194$10397 + cell $add $add$libresoc.v:175826$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357572,10 +360069,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:174194$10397_Y + connect \Y $add$libresoc.v:175826$10445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174195$10398 + cell $add $add$libresoc.v:175827$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357583,10 +360080,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:174195$10398_Y + connect \Y $add$libresoc.v:175827$10446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174196$10399 + cell $add $add$libresoc.v:175828$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357594,10 +360091,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:174196$10399_Y + connect \Y $add$libresoc.v:175828$10447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174197$10400 + cell $add $add$libresoc.v:175829$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357605,10 +360102,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:174197$10400_Y + connect \Y $add$libresoc.v:175829$10448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174198$10401 + cell $add $add$libresoc.v:175830$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357616,10 +360113,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:174198$10401_Y + connect \Y $add$libresoc.v:175830$10449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174199$10402 + cell $add $add$libresoc.v:175831$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357627,10 +360124,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:174199$10402_Y + connect \Y $add$libresoc.v:175831$10450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174200$10403 + cell $add $add$libresoc.v:175832$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357638,10 +360135,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:174200$10403_Y + connect \Y $add$libresoc.v:175832$10451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174201$10404 + cell $add $add$libresoc.v:175833$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -357649,10 +360146,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:174201$10404_Y + connect \Y $add$libresoc.v:175833$10452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174202$10405 + cell $add $add$libresoc.v:175834$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -357660,10 +360157,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:174202$10405_Y + connect \Y $add$libresoc.v:175834$10453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174203$10406 + cell $add $add$libresoc.v:175835$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -357671,10 +360168,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:174203$10406_Y + connect \Y $add$libresoc.v:175835$10454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174214$10425 + cell $add $add$libresoc.v:175846$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357682,10 +360179,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:174214$10425_Y + connect \Y $add$libresoc.v:175846$10473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174218$10432 + cell $add $add$libresoc.v:175850$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357693,10 +360190,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:174218$10432_Y + connect \Y $add$libresoc.v:175850$10480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174219$10433 + cell $add $add$libresoc.v:175851$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357704,10 +360201,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:174219$10433_Y + connect \Y $add$libresoc.v:175851$10481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174220$10434 + cell $add $add$libresoc.v:175852$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357715,10 +360212,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:174220$10434_Y + connect \Y $add$libresoc.v:175852$10482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174221$10435 + cell $add $add$libresoc.v:175853$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357726,10 +360223,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:174221$10435_Y + connect \Y $add$libresoc.v:175853$10483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174222$10436 + cell $add $add$libresoc.v:175854$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357737,10 +360234,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:174222$10436_Y + connect \Y $add$libresoc.v:175854$10484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174223$10437 + cell $add $add$libresoc.v:175855$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357748,10 +360245,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:174223$10437_Y + connect \Y $add$libresoc.v:175855$10485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174224$10438 + cell $add $add$libresoc.v:175856$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357759,10 +360256,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:174224$10438_Y + connect \Y $add$libresoc.v:175856$10486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174225$10439 + cell $add $add$libresoc.v:175857$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357770,10 +360267,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:174225$10439_Y + connect \Y $add$libresoc.v:175857$10487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174226$10440 + cell $add $add$libresoc.v:175858$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357781,10 +360278,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:174226$10440_Y + connect \Y $add$libresoc.v:175858$10488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174227$10441 + cell $add $add$libresoc.v:175859$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357792,10 +360289,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:174227$10441_Y + connect \Y $add$libresoc.v:175859$10489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174228$10442 + cell $add $add$libresoc.v:175860$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357803,10 +360300,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:174228$10442_Y + connect \Y $add$libresoc.v:175860$10490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174229$10443 + cell $add $add$libresoc.v:175861$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357814,10 +360311,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:174229$10443_Y + connect \Y $add$libresoc.v:175861$10491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174230$10444 + cell $add $add$libresoc.v:175862$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357825,10 +360322,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:174230$10444_Y + connect \Y $add$libresoc.v:175862$10492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174231$10445 + cell $add $add$libresoc.v:175863$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357836,10 +360333,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:174231$10445_Y + connect \Y $add$libresoc.v:175863$10493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174232$10446 + cell $add $add$libresoc.v:175864$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357847,10 +360344,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:174232$10446_Y + connect \Y $add$libresoc.v:175864$10494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174233$10447 + cell $add $add$libresoc.v:175865$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357858,10 +360355,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:174233$10447_Y + connect \Y $add$libresoc.v:175865$10495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174234$10448 + cell $add $add$libresoc.v:175866$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357869,10 +360366,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:174234$10448_Y + connect \Y $add$libresoc.v:175866$10496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174235$10449 + cell $add $add$libresoc.v:175867$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357880,10 +360377,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:174235$10449_Y + connect \Y $add$libresoc.v:175867$10497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174236$10450 + cell $add $add$libresoc.v:175868$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357891,10 +360388,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:174236$10450_Y + connect \Y $add$libresoc.v:175868$10498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174237$10451 + cell $add $add$libresoc.v:175869$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357902,10 +360399,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:174237$10451_Y + connect \Y $add$libresoc.v:175869$10499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174238$10452 + cell $add $add$libresoc.v:175870$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357913,10 +360410,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:174238$10452_Y + connect \Y $add$libresoc.v:175870$10500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174239$10453 + cell $add $add$libresoc.v:175871$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357924,10 +360421,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:174239$10453_Y + connect \Y $add$libresoc.v:175871$10501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174240$10454 + cell $add $add$libresoc.v:175872$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357935,10 +360432,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:174240$10454_Y + connect \Y $add$libresoc.v:175872$10502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174241$10455 + cell $add $add$libresoc.v:175873$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357946,10 +360443,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:174241$10455_Y + connect \Y $add$libresoc.v:175873$10503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174242$10456 + cell $add $add$libresoc.v:175874$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357957,10 +360454,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:174242$10456_Y + connect \Y $add$libresoc.v:175874$10504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174243$10457 + cell $add $add$libresoc.v:175875$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357968,10 +360465,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:174243$10457_Y + connect \Y $add$libresoc.v:175875$10505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174244$10458 + cell $add $add$libresoc.v:175876$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357979,10 +360476,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:174244$10458_Y + connect \Y $add$libresoc.v:175876$10506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174245$10459 + cell $add $add$libresoc.v:175877$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357990,10 +360487,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:174245$10459_Y + connect \Y $add$libresoc.v:175877$10507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174246$10460 + cell $add $add$libresoc.v:175878$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -358001,10 +360498,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:174246$10460_Y + connect \Y $add$libresoc.v:175878$10508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:174204$10407 + cell $eq $eq$libresoc.v:175836$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -358012,10 +360509,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:174204$10407_Y + connect \Y $eq$libresoc.v:175836$10455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:174205$10408 + cell $eq $eq$libresoc.v:175837$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -358023,199 +360520,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:174205$10408_Y + connect \Y $eq$libresoc.v:175837$10456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174206$10409 + cell $pos $extend$libresoc.v:175838$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:174206$10409_Y + connect \Y $extend$libresoc.v:175838$10457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174207$10411 + cell $pos $extend$libresoc.v:175839$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:174207$10411_Y + connect \Y $extend$libresoc.v:175839$10459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174208$10413 + cell $pos $extend$libresoc.v:175840$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:174208$10413_Y + connect \Y $extend$libresoc.v:175840$10461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174209$10415 + cell $pos $extend$libresoc.v:175841$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:174209$10415_Y + connect \Y $extend$libresoc.v:175841$10463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174210$10417 + cell $pos $extend$libresoc.v:175842$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:174210$10417_Y + connect \Y $extend$libresoc.v:175842$10465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174211$10419 + cell $pos $extend$libresoc.v:175843$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:174211$10419_Y + connect \Y $extend$libresoc.v:175843$10467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174212$10421 + cell $pos $extend$libresoc.v:175844$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:174212$10421_Y + connect \Y $extend$libresoc.v:175844$10469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174213$10423 + cell $pos $extend$libresoc.v:175845$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:174213$10423_Y + connect \Y $extend$libresoc.v:175845$10471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174215$10426 + cell $pos $extend$libresoc.v:175847$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:174215$10426_Y + connect \Y $extend$libresoc.v:175847$10474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174216$10428 + cell $pos $extend$libresoc.v:175848$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:174216$10428_Y + connect \Y $extend$libresoc.v:175848$10476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174217$10430 + cell $pos $extend$libresoc.v:175849$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:174217$10430_Y + connect \Y $extend$libresoc.v:175849$10478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174206$10410 + cell $pos $pos$libresoc.v:175838$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174206$10409_Y - connect \Y $pos$libresoc.v:174206$10410_Y + connect \A $extend$libresoc.v:175838$10457_Y + connect \Y $pos$libresoc.v:175838$10458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174207$10412 + cell $pos $pos$libresoc.v:175839$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174207$10411_Y - connect \Y $pos$libresoc.v:174207$10412_Y + connect \A $extend$libresoc.v:175839$10459_Y + connect \Y $pos$libresoc.v:175839$10460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174208$10414 + cell $pos $pos$libresoc.v:175840$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174208$10413_Y - connect \Y $pos$libresoc.v:174208$10414_Y + connect \A $extend$libresoc.v:175840$10461_Y + connect \Y $pos$libresoc.v:175840$10462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174209$10416 + cell $pos $pos$libresoc.v:175841$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174209$10415_Y - connect \Y $pos$libresoc.v:174209$10416_Y + connect \A $extend$libresoc.v:175841$10463_Y + connect \Y $pos$libresoc.v:175841$10464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174210$10418 + cell $pos $pos$libresoc.v:175842$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174210$10417_Y - connect \Y $pos$libresoc.v:174210$10418_Y + connect \A $extend$libresoc.v:175842$10465_Y + connect \Y $pos$libresoc.v:175842$10466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174211$10420 + cell $pos $pos$libresoc.v:175843$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174211$10419_Y - connect \Y $pos$libresoc.v:174211$10420_Y + connect \A $extend$libresoc.v:175843$10467_Y + connect \Y $pos$libresoc.v:175843$10468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174212$10422 + cell $pos $pos$libresoc.v:175844$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174212$10421_Y - connect \Y $pos$libresoc.v:174212$10422_Y + connect \A $extend$libresoc.v:175844$10469_Y + connect \Y $pos$libresoc.v:175844$10470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174213$10424 + cell $pos $pos$libresoc.v:175845$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174213$10423_Y - connect \Y $pos$libresoc.v:174213$10424_Y + connect \A $extend$libresoc.v:175845$10471_Y + connect \Y $pos$libresoc.v:175845$10472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174215$10427 + cell $pos $pos$libresoc.v:175847$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:174215$10426_Y - connect \Y $pos$libresoc.v:174215$10427_Y + connect \A $extend$libresoc.v:175847$10474_Y + connect \Y $pos$libresoc.v:175847$10475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174216$10429 + cell $pos $pos$libresoc.v:175848$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:174216$10428_Y - connect \Y $pos$libresoc.v:174216$10429_Y + connect \A $extend$libresoc.v:175848$10476_Y + connect \Y $pos$libresoc.v:175848$10477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174217$10431 + cell $pos $pos$libresoc.v:175849$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:174217$10430_Y - connect \Y $pos$libresoc.v:174217$10431_Y + connect \A $extend$libresoc.v:175849$10478_Y + connect \Y $pos$libresoc.v:175849$10479_Y end - attribute \src "libresoc.v:173759.7-173759.20" - process $proc$libresoc.v:173759$10462 + attribute \src "libresoc.v:175391.7-175391.20" + process $proc$libresoc.v:175391$10510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174247.3-174273.6" - process $proc$libresoc.v:174247$10461 + attribute \src "libresoc.v:175879.3-175905.6" + process $proc$libresoc.v:175879$10509 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:174248.5-174248.29" + attribute \src "libresoc.v:175880.5-175880.29" switch \initial - attribute \src "libresoc.v:174248.9-174248.17" + attribute \src "libresoc.v:175880.9-175880.17" case 1'1 case end @@ -358245,82 +360742,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:174171$10374_Y - connect \$104 $add$libresoc.v:174172$10375_Y - connect \$107 $add$libresoc.v:174173$10376_Y - connect \$110 $add$libresoc.v:174174$10377_Y - connect \$113 $add$libresoc.v:174175$10378_Y - connect \$116 $add$libresoc.v:174176$10379_Y - connect \$11 $add$libresoc.v:174177$10380_Y - connect \$119 $add$libresoc.v:174178$10381_Y - connect \$122 $add$libresoc.v:174179$10382_Y - connect \$125 $add$libresoc.v:174180$10383_Y - connect \$128 $add$libresoc.v:174181$10384_Y - connect \$131 $add$libresoc.v:174182$10385_Y - connect \$134 $add$libresoc.v:174183$10386_Y - connect \$137 $add$libresoc.v:174184$10387_Y - connect \$140 $add$libresoc.v:174185$10388_Y - connect \$143 $add$libresoc.v:174186$10389_Y - connect \$146 $add$libresoc.v:174187$10390_Y - connect \$14 $add$libresoc.v:174188$10391_Y - connect \$149 $add$libresoc.v:174189$10392_Y - connect \$152 $add$libresoc.v:174190$10393_Y - connect \$155 $add$libresoc.v:174191$10394_Y - connect \$158 $add$libresoc.v:174192$10395_Y - connect \$161 $add$libresoc.v:174193$10396_Y - connect \$164 $add$libresoc.v:174194$10397_Y - connect \$167 $add$libresoc.v:174195$10398_Y - connect \$170 $add$libresoc.v:174196$10399_Y - connect \$173 $add$libresoc.v:174197$10400_Y - connect \$176 $add$libresoc.v:174198$10401_Y - connect \$17 $add$libresoc.v:174199$10402_Y - connect \$179 $add$libresoc.v:174200$10403_Y - connect \$182 $add$libresoc.v:174201$10404_Y - connect \$185 $add$libresoc.v:174202$10405_Y - connect \$188 $add$libresoc.v:174203$10406_Y - connect \$190 $eq$libresoc.v:174204$10407_Y - connect \$192 $eq$libresoc.v:174205$10408_Y - connect \$194 $pos$libresoc.v:174206$10410_Y - connect \$196 $pos$libresoc.v:174207$10412_Y - connect \$198 $pos$libresoc.v:174208$10414_Y - connect \$200 $pos$libresoc.v:174209$10416_Y - connect \$202 $pos$libresoc.v:174210$10418_Y - connect \$204 $pos$libresoc.v:174211$10420_Y - connect \$206 $pos$libresoc.v:174212$10422_Y - connect \$208 $pos$libresoc.v:174213$10424_Y - connect \$20 $add$libresoc.v:174214$10425_Y - connect \$210 $pos$libresoc.v:174215$10427_Y - connect \$212 $pos$libresoc.v:174216$10429_Y - connect \$214 $pos$libresoc.v:174217$10431_Y - connect \$23 $add$libresoc.v:174218$10432_Y - connect \$26 $add$libresoc.v:174219$10433_Y - connect \$2 $add$libresoc.v:174220$10434_Y - connect \$29 $add$libresoc.v:174221$10435_Y - connect \$32 $add$libresoc.v:174222$10436_Y - connect \$35 $add$libresoc.v:174223$10437_Y - connect \$38 $add$libresoc.v:174224$10438_Y - connect \$41 $add$libresoc.v:174225$10439_Y - connect \$44 $add$libresoc.v:174226$10440_Y - connect \$47 $add$libresoc.v:174227$10441_Y - connect \$50 $add$libresoc.v:174228$10442_Y - connect \$53 $add$libresoc.v:174229$10443_Y - connect \$56 $add$libresoc.v:174230$10444_Y - connect \$5 $add$libresoc.v:174231$10445_Y - connect \$59 $add$libresoc.v:174232$10446_Y - connect \$62 $add$libresoc.v:174233$10447_Y - connect \$65 $add$libresoc.v:174234$10448_Y - connect \$68 $add$libresoc.v:174235$10449_Y - connect \$71 $add$libresoc.v:174236$10450_Y - connect \$74 $add$libresoc.v:174237$10451_Y - connect \$77 $add$libresoc.v:174238$10452_Y - connect \$80 $add$libresoc.v:174239$10453_Y - connect \$83 $add$libresoc.v:174240$10454_Y - connect \$86 $add$libresoc.v:174241$10455_Y - connect \$8 $add$libresoc.v:174242$10456_Y - connect \$89 $add$libresoc.v:174243$10457_Y - connect \$92 $add$libresoc.v:174244$10458_Y - connect \$95 $add$libresoc.v:174245$10459_Y - connect \$98 $add$libresoc.v:174246$10460_Y + connect \$101 $add$libresoc.v:175803$10422_Y + connect \$104 $add$libresoc.v:175804$10423_Y + connect \$107 $add$libresoc.v:175805$10424_Y + connect \$110 $add$libresoc.v:175806$10425_Y + connect \$113 $add$libresoc.v:175807$10426_Y + connect \$116 $add$libresoc.v:175808$10427_Y + connect \$11 $add$libresoc.v:175809$10428_Y + connect \$119 $add$libresoc.v:175810$10429_Y + connect \$122 $add$libresoc.v:175811$10430_Y + connect \$125 $add$libresoc.v:175812$10431_Y + connect \$128 $add$libresoc.v:175813$10432_Y + connect \$131 $add$libresoc.v:175814$10433_Y + connect \$134 $add$libresoc.v:175815$10434_Y + connect \$137 $add$libresoc.v:175816$10435_Y + connect \$140 $add$libresoc.v:175817$10436_Y + connect \$143 $add$libresoc.v:175818$10437_Y + connect \$146 $add$libresoc.v:175819$10438_Y + connect \$14 $add$libresoc.v:175820$10439_Y + connect \$149 $add$libresoc.v:175821$10440_Y + connect \$152 $add$libresoc.v:175822$10441_Y + connect \$155 $add$libresoc.v:175823$10442_Y + connect \$158 $add$libresoc.v:175824$10443_Y + connect \$161 $add$libresoc.v:175825$10444_Y + connect \$164 $add$libresoc.v:175826$10445_Y + connect \$167 $add$libresoc.v:175827$10446_Y + connect \$170 $add$libresoc.v:175828$10447_Y + connect \$173 $add$libresoc.v:175829$10448_Y + connect \$176 $add$libresoc.v:175830$10449_Y + connect \$17 $add$libresoc.v:175831$10450_Y + connect \$179 $add$libresoc.v:175832$10451_Y + connect \$182 $add$libresoc.v:175833$10452_Y + connect \$185 $add$libresoc.v:175834$10453_Y + connect \$188 $add$libresoc.v:175835$10454_Y + connect \$190 $eq$libresoc.v:175836$10455_Y + connect \$192 $eq$libresoc.v:175837$10456_Y + connect \$194 $pos$libresoc.v:175838$10458_Y + connect \$196 $pos$libresoc.v:175839$10460_Y + connect \$198 $pos$libresoc.v:175840$10462_Y + connect \$200 $pos$libresoc.v:175841$10464_Y + connect \$202 $pos$libresoc.v:175842$10466_Y + connect \$204 $pos$libresoc.v:175843$10468_Y + connect \$206 $pos$libresoc.v:175844$10470_Y + connect \$208 $pos$libresoc.v:175845$10472_Y + connect \$20 $add$libresoc.v:175846$10473_Y + connect \$210 $pos$libresoc.v:175847$10475_Y + connect \$212 $pos$libresoc.v:175848$10477_Y + connect \$214 $pos$libresoc.v:175849$10479_Y + connect \$23 $add$libresoc.v:175850$10480_Y + connect \$26 $add$libresoc.v:175851$10481_Y + connect \$2 $add$libresoc.v:175852$10482_Y + connect \$29 $add$libresoc.v:175853$10483_Y + connect \$32 $add$libresoc.v:175854$10484_Y + connect \$35 $add$libresoc.v:175855$10485_Y + connect \$38 $add$libresoc.v:175856$10486_Y + connect \$41 $add$libresoc.v:175857$10487_Y + connect \$44 $add$libresoc.v:175858$10488_Y + connect \$47 $add$libresoc.v:175859$10489_Y + connect \$50 $add$libresoc.v:175860$10490_Y + connect \$53 $add$libresoc.v:175861$10491_Y + connect \$56 $add$libresoc.v:175862$10492_Y + connect \$5 $add$libresoc.v:175863$10493_Y + connect \$59 $add$libresoc.v:175864$10494_Y + connect \$62 $add$libresoc.v:175865$10495_Y + connect \$65 $add$libresoc.v:175866$10496_Y + connect \$68 $add$libresoc.v:175867$10497_Y + connect \$71 $add$libresoc.v:175868$10498_Y + connect \$74 $add$libresoc.v:175869$10499_Y + connect \$77 $add$libresoc.v:175870$10500_Y + connect \$80 $add$libresoc.v:175871$10501_Y + connect \$83 $add$libresoc.v:175872$10502_Y + connect \$86 $add$libresoc.v:175873$10503_Y + connect \$8 $add$libresoc.v:175874$10504_Y + connect \$89 $add$libresoc.v:175875$10505_Y + connect \$92 $add$libresoc.v:175876$10506_Y + connect \$95 $add$libresoc.v:175877$10507_Y + connect \$98 $add$libresoc.v:175878$10508_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -358448,43 +360945,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:174404.1-174488.10" +attribute \src "libresoc.v:176036.1-176120.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:174461.17-174461.91" - wire $not$libresoc.v:174461$10463_Y - attribute \src "libresoc.v:174463.18-174463.93" - wire $not$libresoc.v:174463$10465_Y - attribute \src "libresoc.v:174465.18-174465.93" - wire $not$libresoc.v:174465$10467_Y - attribute \src "libresoc.v:174466.17-174466.138" - wire width 8 $not$libresoc.v:174466$10468_Y - attribute \src "libresoc.v:174468.18-174468.93" - wire $not$libresoc.v:174468$10470_Y - attribute \src "libresoc.v:174470.18-174470.93" - wire $not$libresoc.v:174470$10472_Y - attribute \src "libresoc.v:174472.18-174472.93" - wire $not$libresoc.v:174472$10474_Y - attribute \src "libresoc.v:174475.17-174475.91" - wire $not$libresoc.v:174475$10477_Y - attribute \src "libresoc.v:174462.18-174462.116" - wire $reduce_or$libresoc.v:174462$10464_Y - attribute \src "libresoc.v:174464.18-174464.122" - wire $reduce_or$libresoc.v:174464$10466_Y - attribute \src "libresoc.v:174467.18-174467.128" - wire $reduce_or$libresoc.v:174467$10469_Y - attribute \src "libresoc.v:174469.18-174469.134" - wire $reduce_or$libresoc.v:174469$10471_Y - attribute \src "libresoc.v:174471.18-174471.140" - wire $reduce_or$libresoc.v:174471$10473_Y - attribute \src "libresoc.v:174473.18-174473.90" - wire $reduce_or$libresoc.v:174473$10475_Y - attribute \src "libresoc.v:174474.17-174474.103" - wire $reduce_or$libresoc.v:174474$10476_Y - attribute \src "libresoc.v:174476.17-174476.109" - wire $reduce_or$libresoc.v:174476$10478_Y + attribute \src "libresoc.v:176093.17-176093.91" + wire $not$libresoc.v:176093$10511_Y + attribute \src "libresoc.v:176095.18-176095.93" + wire $not$libresoc.v:176095$10513_Y + attribute \src "libresoc.v:176097.18-176097.93" + wire $not$libresoc.v:176097$10515_Y + attribute \src "libresoc.v:176098.17-176098.138" + wire width 8 $not$libresoc.v:176098$10516_Y + attribute \src "libresoc.v:176100.18-176100.93" + wire $not$libresoc.v:176100$10518_Y + attribute \src "libresoc.v:176102.18-176102.93" + wire $not$libresoc.v:176102$10520_Y + attribute \src "libresoc.v:176104.18-176104.93" + wire $not$libresoc.v:176104$10522_Y + attribute \src "libresoc.v:176107.17-176107.91" + wire $not$libresoc.v:176107$10525_Y + attribute \src "libresoc.v:176094.18-176094.116" + wire $reduce_or$libresoc.v:176094$10512_Y + attribute \src "libresoc.v:176096.18-176096.122" + wire $reduce_or$libresoc.v:176096$10514_Y + attribute \src "libresoc.v:176099.18-176099.128" + wire $reduce_or$libresoc.v:176099$10517_Y + attribute \src "libresoc.v:176101.18-176101.134" + wire $reduce_or$libresoc.v:176101$10519_Y + attribute \src "libresoc.v:176103.18-176103.140" + wire $reduce_or$libresoc.v:176103$10521_Y + attribute \src "libresoc.v:176105.18-176105.90" + wire $reduce_or$libresoc.v:176105$10523_Y + attribute \src "libresoc.v:176106.17-176106.103" + wire $reduce_or$libresoc.v:176106$10524_Y + attribute \src "libresoc.v:176108.17-176108.109" + wire $reduce_or$libresoc.v:176108$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358542,149 +361039,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174461$10463 + cell $not $not$libresoc.v:176093$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174461$10463_Y + connect \Y $not$libresoc.v:176093$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174463$10465 + cell $not $not$libresoc.v:176095$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174463$10465_Y + connect \Y $not$libresoc.v:176095$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174465$10467 + cell $not $not$libresoc.v:176097$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174465$10467_Y + connect \Y $not$libresoc.v:176097$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174466$10468 + cell $not $not$libresoc.v:176098$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:174466$10468_Y + connect \Y $not$libresoc.v:176098$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174468$10470 + cell $not $not$libresoc.v:176100$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174468$10470_Y + connect \Y $not$libresoc.v:176100$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174470$10472 + cell $not $not$libresoc.v:176102$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174470$10472_Y + connect \Y $not$libresoc.v:176102$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174472$10474 + cell $not $not$libresoc.v:176104$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174472$10474_Y + connect \Y $not$libresoc.v:176104$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174475$10477 + cell $not $not$libresoc.v:176107$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174475$10477_Y + connect \Y $not$libresoc.v:176107$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174462$10464 + cell $reduce_or $reduce_or$libresoc.v:176094$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:174462$10464_Y + connect \Y $reduce_or$libresoc.v:176094$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174464$10466 + cell $reduce_or $reduce_or$libresoc.v:176096$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:174464$10466_Y + connect \Y $reduce_or$libresoc.v:176096$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174467$10469 + cell $reduce_or $reduce_or$libresoc.v:176099$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:174467$10469_Y + connect \Y $reduce_or$libresoc.v:176099$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174469$10471 + cell $reduce_or $reduce_or$libresoc.v:176101$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:174469$10471_Y + connect \Y $reduce_or$libresoc.v:176101$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174471$10473 + cell $reduce_or $reduce_or$libresoc.v:176103$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:174471$10473_Y + connect \Y $reduce_or$libresoc.v:176103$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174473$10475 + cell $reduce_or $reduce_or$libresoc.v:176105$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174473$10475_Y + connect \Y $reduce_or$libresoc.v:176105$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174474$10476 + cell $reduce_or $reduce_or$libresoc.v:176106$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:174474$10476_Y + connect \Y $reduce_or$libresoc.v:176106$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174476$10478 + cell $reduce_or $reduce_or$libresoc.v:176108$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:174476$10478_Y - end - connect \$7 $not$libresoc.v:174461$10463_Y - connect \$12 $reduce_or$libresoc.v:174462$10464_Y - connect \$11 $not$libresoc.v:174463$10465_Y - connect \$16 $reduce_or$libresoc.v:174464$10466_Y - connect \$15 $not$libresoc.v:174465$10467_Y - connect \$1 $not$libresoc.v:174466$10468_Y - connect \$20 $reduce_or$libresoc.v:174467$10469_Y - connect \$19 $not$libresoc.v:174468$10470_Y - connect \$24 $reduce_or$libresoc.v:174469$10471_Y - connect \$23 $not$libresoc.v:174470$10472_Y - connect \$28 $reduce_or$libresoc.v:174471$10473_Y - connect \$27 $not$libresoc.v:174472$10474_Y - connect \$31 $reduce_or$libresoc.v:174473$10475_Y - connect \$4 $reduce_or$libresoc.v:174474$10476_Y - connect \$3 $not$libresoc.v:174475$10477_Y - connect \$8 $reduce_or$libresoc.v:174476$10478_Y + connect \Y $reduce_or$libresoc.v:176108$10526_Y + end + connect \$7 $not$libresoc.v:176093$10511_Y + connect \$12 $reduce_or$libresoc.v:176094$10512_Y + connect \$11 $not$libresoc.v:176095$10513_Y + connect \$16 $reduce_or$libresoc.v:176096$10514_Y + connect \$15 $not$libresoc.v:176097$10515_Y + connect \$1 $not$libresoc.v:176098$10516_Y + connect \$20 $reduce_or$libresoc.v:176099$10517_Y + connect \$19 $not$libresoc.v:176100$10518_Y + connect \$24 $reduce_or$libresoc.v:176101$10519_Y + connect \$23 $not$libresoc.v:176102$10520_Y + connect \$28 $reduce_or$libresoc.v:176103$10521_Y + connect \$27 $not$libresoc.v:176104$10522_Y + connect \$31 $reduce_or$libresoc.v:176105$10523_Y + connect \$4 $reduce_or$libresoc.v:176106$10524_Y + connect \$3 $not$libresoc.v:176107$10525_Y + connect \$8 $reduce_or$libresoc.v:176108$10526_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358697,43 +361194,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:174492.1-174576.10" +attribute \src "libresoc.v:176124.1-176208.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:174549.17-174549.91" - wire $not$libresoc.v:174549$10479_Y - attribute \src "libresoc.v:174551.18-174551.93" - wire $not$libresoc.v:174551$10481_Y - attribute \src "libresoc.v:174553.18-174553.93" - wire $not$libresoc.v:174553$10483_Y - attribute \src "libresoc.v:174554.17-174554.138" - wire width 8 $not$libresoc.v:174554$10484_Y - attribute \src "libresoc.v:174556.18-174556.93" - wire $not$libresoc.v:174556$10486_Y - attribute \src "libresoc.v:174558.18-174558.93" - wire $not$libresoc.v:174558$10488_Y - attribute \src "libresoc.v:174560.18-174560.93" - wire $not$libresoc.v:174560$10490_Y - attribute \src "libresoc.v:174563.17-174563.91" - wire $not$libresoc.v:174563$10493_Y - attribute \src "libresoc.v:174550.18-174550.116" - wire $reduce_or$libresoc.v:174550$10480_Y - attribute \src "libresoc.v:174552.18-174552.122" - wire $reduce_or$libresoc.v:174552$10482_Y - attribute \src "libresoc.v:174555.18-174555.128" - wire $reduce_or$libresoc.v:174555$10485_Y - attribute \src "libresoc.v:174557.18-174557.134" - wire $reduce_or$libresoc.v:174557$10487_Y - attribute \src "libresoc.v:174559.18-174559.140" - wire $reduce_or$libresoc.v:174559$10489_Y - attribute \src "libresoc.v:174561.18-174561.90" - wire $reduce_or$libresoc.v:174561$10491_Y - attribute \src "libresoc.v:174562.17-174562.103" - wire $reduce_or$libresoc.v:174562$10492_Y - attribute \src "libresoc.v:174564.17-174564.109" - wire $reduce_or$libresoc.v:174564$10494_Y + attribute \src "libresoc.v:176181.17-176181.91" + wire $not$libresoc.v:176181$10527_Y + attribute \src "libresoc.v:176183.18-176183.93" + wire $not$libresoc.v:176183$10529_Y + attribute \src "libresoc.v:176185.18-176185.93" + wire $not$libresoc.v:176185$10531_Y + attribute \src "libresoc.v:176186.17-176186.138" + wire width 8 $not$libresoc.v:176186$10532_Y + attribute \src "libresoc.v:176188.18-176188.93" + wire $not$libresoc.v:176188$10534_Y + attribute \src "libresoc.v:176190.18-176190.93" + wire $not$libresoc.v:176190$10536_Y + attribute \src "libresoc.v:176192.18-176192.93" + wire $not$libresoc.v:176192$10538_Y + attribute \src "libresoc.v:176195.17-176195.91" + wire $not$libresoc.v:176195$10541_Y + attribute \src "libresoc.v:176182.18-176182.116" + wire $reduce_or$libresoc.v:176182$10528_Y + attribute \src "libresoc.v:176184.18-176184.122" + wire $reduce_or$libresoc.v:176184$10530_Y + attribute \src "libresoc.v:176187.18-176187.128" + wire $reduce_or$libresoc.v:176187$10533_Y + attribute \src "libresoc.v:176189.18-176189.134" + wire $reduce_or$libresoc.v:176189$10535_Y + attribute \src "libresoc.v:176191.18-176191.140" + wire $reduce_or$libresoc.v:176191$10537_Y + attribute \src "libresoc.v:176193.18-176193.90" + wire $reduce_or$libresoc.v:176193$10539_Y + attribute \src "libresoc.v:176194.17-176194.103" + wire $reduce_or$libresoc.v:176194$10540_Y + attribute \src "libresoc.v:176196.17-176196.109" + wire $reduce_or$libresoc.v:176196$10542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358791,149 +361288,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174549$10479 + cell $not $not$libresoc.v:176181$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174549$10479_Y + connect \Y $not$libresoc.v:176181$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174551$10481 + cell $not $not$libresoc.v:176183$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174551$10481_Y + connect \Y $not$libresoc.v:176183$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174553$10483 + cell $not $not$libresoc.v:176185$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174553$10483_Y + connect \Y $not$libresoc.v:176185$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174554$10484 + cell $not $not$libresoc.v:176186$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:174554$10484_Y + connect \Y $not$libresoc.v:176186$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174556$10486 + cell $not $not$libresoc.v:176188$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174556$10486_Y + connect \Y $not$libresoc.v:176188$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174558$10488 + cell $not $not$libresoc.v:176190$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174558$10488_Y + connect \Y $not$libresoc.v:176190$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174560$10490 + cell $not $not$libresoc.v:176192$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174560$10490_Y + connect \Y $not$libresoc.v:176192$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174563$10493 + cell $not $not$libresoc.v:176195$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174563$10493_Y + connect \Y $not$libresoc.v:176195$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174550$10480 + cell $reduce_or $reduce_or$libresoc.v:176182$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:174550$10480_Y + connect \Y $reduce_or$libresoc.v:176182$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174552$10482 + cell $reduce_or $reduce_or$libresoc.v:176184$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:174552$10482_Y + connect \Y $reduce_or$libresoc.v:176184$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174555$10485 + cell $reduce_or $reduce_or$libresoc.v:176187$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:174555$10485_Y + connect \Y $reduce_or$libresoc.v:176187$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174557$10487 + cell $reduce_or $reduce_or$libresoc.v:176189$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:174557$10487_Y + connect \Y $reduce_or$libresoc.v:176189$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174559$10489 + cell $reduce_or $reduce_or$libresoc.v:176191$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:174559$10489_Y + connect \Y $reduce_or$libresoc.v:176191$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174561$10491 + cell $reduce_or $reduce_or$libresoc.v:176193$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174561$10491_Y + connect \Y $reduce_or$libresoc.v:176193$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174562$10492 + cell $reduce_or $reduce_or$libresoc.v:176194$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:174562$10492_Y + connect \Y $reduce_or$libresoc.v:176194$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174564$10494 + cell $reduce_or $reduce_or$libresoc.v:176196$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:174564$10494_Y - end - connect \$7 $not$libresoc.v:174549$10479_Y - connect \$12 $reduce_or$libresoc.v:174550$10480_Y - connect \$11 $not$libresoc.v:174551$10481_Y - connect \$16 $reduce_or$libresoc.v:174552$10482_Y - connect \$15 $not$libresoc.v:174553$10483_Y - connect \$1 $not$libresoc.v:174554$10484_Y - connect \$20 $reduce_or$libresoc.v:174555$10485_Y - connect \$19 $not$libresoc.v:174556$10486_Y - connect \$24 $reduce_or$libresoc.v:174557$10487_Y - connect \$23 $not$libresoc.v:174558$10488_Y - connect \$28 $reduce_or$libresoc.v:174559$10489_Y - connect \$27 $not$libresoc.v:174560$10490_Y - connect \$31 $reduce_or$libresoc.v:174561$10491_Y - connect \$4 $reduce_or$libresoc.v:174562$10492_Y - connect \$3 $not$libresoc.v:174563$10493_Y - connect \$8 $reduce_or$libresoc.v:174564$10494_Y + connect \Y $reduce_or$libresoc.v:176196$10542_Y + end + connect \$7 $not$libresoc.v:176181$10527_Y + connect \$12 $reduce_or$libresoc.v:176182$10528_Y + connect \$11 $not$libresoc.v:176183$10529_Y + connect \$16 $reduce_or$libresoc.v:176184$10530_Y + connect \$15 $not$libresoc.v:176185$10531_Y + connect \$1 $not$libresoc.v:176186$10532_Y + connect \$20 $reduce_or$libresoc.v:176187$10533_Y + connect \$19 $not$libresoc.v:176188$10534_Y + connect \$24 $reduce_or$libresoc.v:176189$10535_Y + connect \$23 $not$libresoc.v:176190$10536_Y + connect \$28 $reduce_or$libresoc.v:176191$10537_Y + connect \$27 $not$libresoc.v:176192$10538_Y + connect \$31 $reduce_or$libresoc.v:176193$10539_Y + connect \$4 $reduce_or$libresoc.v:176194$10540_Y + connect \$3 $not$libresoc.v:176195$10541_Y + connect \$8 $reduce_or$libresoc.v:176196$10542_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358946,19 +361443,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:174580.1-174610.10" +attribute \src "libresoc.v:176212.1-176242.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:174601.17-174601.89" - wire width 2 $not$libresoc.v:174601$10495_Y - attribute \src "libresoc.v:174603.17-174603.91" - wire $not$libresoc.v:174603$10497_Y - attribute \src "libresoc.v:174602.17-174602.103" - wire $reduce_or$libresoc.v:174602$10496_Y - attribute \src "libresoc.v:174604.17-174604.89" - wire $reduce_or$libresoc.v:174604$10498_Y + attribute \src "libresoc.v:176233.17-176233.89" + wire width 2 $not$libresoc.v:176233$10543_Y + attribute \src "libresoc.v:176235.17-176235.91" + wire $not$libresoc.v:176235$10545_Y + attribute \src "libresoc.v:176234.17-176234.103" + wire $reduce_or$libresoc.v:176234$10544_Y + attribute \src "libresoc.v:176236.17-176236.89" + wire $reduce_or$libresoc.v:176236$10546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358980,56 +361477,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174601$10495 + cell $not $not$libresoc.v:176233$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174601$10495_Y + connect \Y $not$libresoc.v:176233$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174603$10497 + cell $not $not$libresoc.v:176235$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174603$10497_Y + connect \Y $not$libresoc.v:176235$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174602$10496 + cell $reduce_or $reduce_or$libresoc.v:176234$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174602$10496_Y + connect \Y $reduce_or$libresoc.v:176234$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174604$10498 + cell $reduce_or $reduce_or$libresoc.v:176236$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174604$10498_Y + connect \Y $reduce_or$libresoc.v:176236$10546_Y end - connect \$1 $not$libresoc.v:174601$10495_Y - connect \$4 $reduce_or$libresoc.v:174602$10496_Y - connect \$3 $not$libresoc.v:174603$10497_Y - connect \$7 $reduce_or$libresoc.v:174604$10498_Y + connect \$1 $not$libresoc.v:176233$10543_Y + connect \$4 $reduce_or$libresoc.v:176234$10544_Y + connect \$3 $not$libresoc.v:176235$10545_Y + connect \$7 $reduce_or$libresoc.v:176236$10546_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174614.1-174635.10" +attribute \src "libresoc.v:176246.1-176267.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:174629.17-174629.89" - wire $not$libresoc.v:174629$10499_Y - attribute \src "libresoc.v:174630.17-174630.89" - wire $reduce_or$libresoc.v:174630$10500_Y + attribute \src "libresoc.v:176261.17-176261.89" + wire $not$libresoc.v:176261$10547_Y + attribute \src "libresoc.v:176262.17-176262.89" + wire $reduce_or$libresoc.v:176262$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359045,37 +361542,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174629$10499 + cell $not $not$libresoc.v:176261$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174629$10499_Y + connect \Y $not$libresoc.v:176261$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174630$10500 + cell $reduce_or $reduce_or$libresoc.v:176262$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174630$10500_Y + connect \Y $reduce_or$libresoc.v:176262$10548_Y end - connect \$1 $not$libresoc.v:174629$10499_Y - connect \$3 $reduce_or$libresoc.v:174630$10500_Y + connect \$1 $not$libresoc.v:176261$10547_Y + connect \$3 $reduce_or$libresoc.v:176262$10548_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174639.1-174660.10" +attribute \src "libresoc.v:176271.1-176292.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:174654.17-174654.89" - wire $not$libresoc.v:174654$10501_Y - attribute \src "libresoc.v:174655.17-174655.89" - wire $reduce_or$libresoc.v:174655$10502_Y + attribute \src "libresoc.v:176286.17-176286.89" + wire $not$libresoc.v:176286$10549_Y + attribute \src "libresoc.v:176287.17-176287.89" + wire $reduce_or$libresoc.v:176287$10550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359091,37 +361588,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174654$10501 + cell $not $not$libresoc.v:176286$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174654$10501_Y + connect \Y $not$libresoc.v:176286$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174655$10502 + cell $reduce_or $reduce_or$libresoc.v:176287$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174655$10502_Y + connect \Y $reduce_or$libresoc.v:176287$10550_Y end - connect \$1 $not$libresoc.v:174654$10501_Y - connect \$3 $reduce_or$libresoc.v:174655$10502_Y + connect \$1 $not$libresoc.v:176286$10549_Y + connect \$3 $reduce_or$libresoc.v:176287$10550_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174664.1-174685.10" +attribute \src "libresoc.v:176296.1-176317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:174679.17-174679.89" - wire $not$libresoc.v:174679$10503_Y - attribute \src "libresoc.v:174680.17-174680.89" - wire $reduce_or$libresoc.v:174680$10504_Y + attribute \src "libresoc.v:176311.17-176311.89" + wire $not$libresoc.v:176311$10551_Y + attribute \src "libresoc.v:176312.17-176312.89" + wire $reduce_or$libresoc.v:176312$10552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359137,45 +361634,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174679$10503 + cell $not $not$libresoc.v:176311$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174679$10503_Y + connect \Y $not$libresoc.v:176311$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174680$10504 + cell $reduce_or $reduce_or$libresoc.v:176312$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174680$10504_Y + connect \Y $reduce_or$libresoc.v:176312$10552_Y end - connect \$1 $not$libresoc.v:174679$10503_Y - connect \$3 $reduce_or$libresoc.v:174680$10504_Y + connect \$1 $not$libresoc.v:176311$10551_Y + connect \$3 $reduce_or$libresoc.v:176312$10552_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174689.1-174728.10" +attribute \src "libresoc.v:176321.1-176360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:174716.17-174716.91" - wire $not$libresoc.v:174716$10505_Y - attribute \src "libresoc.v:174718.17-174718.89" - wire width 3 $not$libresoc.v:174718$10507_Y - attribute \src "libresoc.v:174720.17-174720.91" - wire $not$libresoc.v:174720$10509_Y - attribute \src "libresoc.v:174717.18-174717.90" - wire $reduce_or$libresoc.v:174717$10506_Y - attribute \src "libresoc.v:174719.17-174719.103" - wire $reduce_or$libresoc.v:174719$10508_Y - attribute \src "libresoc.v:174721.17-174721.105" - wire $reduce_or$libresoc.v:174721$10510_Y + attribute \src "libresoc.v:176348.17-176348.91" + wire $not$libresoc.v:176348$10553_Y + attribute \src "libresoc.v:176350.17-176350.89" + wire width 3 $not$libresoc.v:176350$10555_Y + attribute \src "libresoc.v:176352.17-176352.91" + wire $not$libresoc.v:176352$10557_Y + attribute \src "libresoc.v:176349.18-176349.90" + wire $reduce_or$libresoc.v:176349$10554_Y + attribute \src "libresoc.v:176351.17-176351.103" + wire $reduce_or$libresoc.v:176351$10556_Y + attribute \src "libresoc.v:176353.17-176353.105" + wire $reduce_or$libresoc.v:176353$10558_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359203,59 +361700,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174716$10505 + cell $not $not$libresoc.v:176348$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174716$10505_Y + connect \Y $not$libresoc.v:176348$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174718$10507 + cell $not $not$libresoc.v:176350$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:174718$10507_Y + connect \Y $not$libresoc.v:176350$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174720$10509 + cell $not $not$libresoc.v:176352$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174720$10509_Y + connect \Y $not$libresoc.v:176352$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174717$10506 + cell $reduce_or $reduce_or$libresoc.v:176349$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174717$10506_Y + connect \Y $reduce_or$libresoc.v:176349$10554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174719$10508 + cell $reduce_or $reduce_or$libresoc.v:176351$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174719$10508_Y + connect \Y $reduce_or$libresoc.v:176351$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174721$10510 + cell $reduce_or $reduce_or$libresoc.v:176353$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174721$10510_Y - end - connect \$7 $not$libresoc.v:174716$10505_Y - connect \$11 $reduce_or$libresoc.v:174717$10506_Y - connect \$1 $not$libresoc.v:174718$10507_Y - connect \$4 $reduce_or$libresoc.v:174719$10508_Y - connect \$3 $not$libresoc.v:174720$10509_Y - connect \$8 $reduce_or$libresoc.v:174721$10510_Y + connect \Y $reduce_or$libresoc.v:176353$10558_Y + end + connect \$7 $not$libresoc.v:176348$10553_Y + connect \$11 $reduce_or$libresoc.v:176349$10554_Y + connect \$1 $not$libresoc.v:176350$10555_Y + connect \$4 $reduce_or$libresoc.v:176351$10556_Y + connect \$3 $not$libresoc.v:176352$10557_Y + connect \$8 $reduce_or$libresoc.v:176353$10558_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -359263,19 +361760,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174732.1-174762.10" +attribute \src "libresoc.v:176364.1-176394.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:174753.17-174753.89" - wire width 2 $not$libresoc.v:174753$10511_Y - attribute \src "libresoc.v:174755.17-174755.91" - wire $not$libresoc.v:174755$10513_Y - attribute \src "libresoc.v:174754.17-174754.103" - wire $reduce_or$libresoc.v:174754$10512_Y - attribute \src "libresoc.v:174756.17-174756.89" - wire $reduce_or$libresoc.v:174756$10514_Y + attribute \src "libresoc.v:176385.17-176385.89" + wire width 2 $not$libresoc.v:176385$10559_Y + attribute \src "libresoc.v:176387.17-176387.91" + wire $not$libresoc.v:176387$10561_Y + attribute \src "libresoc.v:176386.17-176386.103" + wire $reduce_or$libresoc.v:176386$10560_Y + attribute \src "libresoc.v:176388.17-176388.89" + wire $reduce_or$libresoc.v:176388$10562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359297,88 +361794,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174753$10511 + cell $not $not$libresoc.v:176385$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174753$10511_Y + connect \Y $not$libresoc.v:176385$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174755$10513 + cell $not $not$libresoc.v:176387$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174755$10513_Y + connect \Y $not$libresoc.v:176387$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174754$10512 + cell $reduce_or $reduce_or$libresoc.v:176386$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174754$10512_Y + connect \Y $reduce_or$libresoc.v:176386$10560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174756$10514 + cell $reduce_or $reduce_or$libresoc.v:176388$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174756$10514_Y + connect \Y $reduce_or$libresoc.v:176388$10562_Y end - connect \$1 $not$libresoc.v:174753$10511_Y - connect \$4 $reduce_or$libresoc.v:174754$10512_Y - connect \$3 $not$libresoc.v:174755$10513_Y - connect \$7 $reduce_or$libresoc.v:174756$10514_Y + connect \$1 $not$libresoc.v:176385$10559_Y + connect \$4 $reduce_or$libresoc.v:176386$10560_Y + connect \$3 $not$libresoc.v:176387$10561_Y + connect \$7 $reduce_or$libresoc.v:176388$10562_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174766.1-174859.10" +attribute \src "libresoc.v:176398.1-176491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:174829.17-174829.91" - wire $not$libresoc.v:174829$10515_Y - attribute \src "libresoc.v:174831.18-174831.93" - wire $not$libresoc.v:174831$10517_Y - attribute \src "libresoc.v:174833.18-174833.93" - wire $not$libresoc.v:174833$10519_Y - attribute \src "libresoc.v:174834.17-174834.89" - wire width 9 $not$libresoc.v:174834$10520_Y - attribute \src "libresoc.v:174836.18-174836.93" - wire $not$libresoc.v:174836$10522_Y - attribute \src "libresoc.v:174838.18-174838.93" - wire $not$libresoc.v:174838$10524_Y - attribute \src "libresoc.v:174840.18-174840.93" - wire $not$libresoc.v:174840$10526_Y - attribute \src "libresoc.v:174842.18-174842.93" - wire $not$libresoc.v:174842$10528_Y - attribute \src "libresoc.v:174845.17-174845.91" - wire $not$libresoc.v:174845$10531_Y - attribute \src "libresoc.v:174830.18-174830.106" - wire $reduce_or$libresoc.v:174830$10516_Y - attribute \src "libresoc.v:174832.18-174832.106" - wire $reduce_or$libresoc.v:174832$10518_Y - attribute \src "libresoc.v:174835.18-174835.106" - wire $reduce_or$libresoc.v:174835$10521_Y - attribute \src "libresoc.v:174837.18-174837.106" - wire $reduce_or$libresoc.v:174837$10523_Y - attribute \src "libresoc.v:174839.18-174839.106" - wire $reduce_or$libresoc.v:174839$10525_Y - attribute \src "libresoc.v:174841.18-174841.106" - wire $reduce_or$libresoc.v:174841$10527_Y - attribute \src "libresoc.v:174843.18-174843.90" - wire $reduce_or$libresoc.v:174843$10529_Y - attribute \src "libresoc.v:174844.17-174844.103" - wire $reduce_or$libresoc.v:174844$10530_Y - attribute \src "libresoc.v:174846.17-174846.105" - wire $reduce_or$libresoc.v:174846$10532_Y + attribute \src "libresoc.v:176461.17-176461.91" + wire $not$libresoc.v:176461$10563_Y + attribute \src "libresoc.v:176463.18-176463.93" + wire $not$libresoc.v:176463$10565_Y + attribute \src "libresoc.v:176465.18-176465.93" + wire $not$libresoc.v:176465$10567_Y + attribute \src "libresoc.v:176466.17-176466.89" + wire width 9 $not$libresoc.v:176466$10568_Y + attribute \src "libresoc.v:176468.18-176468.93" + wire $not$libresoc.v:176468$10570_Y + attribute \src "libresoc.v:176470.18-176470.93" + wire $not$libresoc.v:176470$10572_Y + attribute \src "libresoc.v:176472.18-176472.93" + wire $not$libresoc.v:176472$10574_Y + attribute \src "libresoc.v:176474.18-176474.93" + wire $not$libresoc.v:176474$10576_Y + attribute \src "libresoc.v:176477.17-176477.91" + wire $not$libresoc.v:176477$10579_Y + attribute \src "libresoc.v:176462.18-176462.106" + wire $reduce_or$libresoc.v:176462$10564_Y + attribute \src "libresoc.v:176464.18-176464.106" + wire $reduce_or$libresoc.v:176464$10566_Y + attribute \src "libresoc.v:176467.18-176467.106" + wire $reduce_or$libresoc.v:176467$10569_Y + attribute \src "libresoc.v:176469.18-176469.106" + wire $reduce_or$libresoc.v:176469$10571_Y + attribute \src "libresoc.v:176471.18-176471.106" + wire $reduce_or$libresoc.v:176471$10573_Y + attribute \src "libresoc.v:176473.18-176473.106" + wire $reduce_or$libresoc.v:176473$10575_Y + attribute \src "libresoc.v:176475.18-176475.90" + wire $reduce_or$libresoc.v:176475$10577_Y + attribute \src "libresoc.v:176476.17-176476.103" + wire $reduce_or$libresoc.v:176476$10578_Y + attribute \src "libresoc.v:176478.17-176478.105" + wire $reduce_or$libresoc.v:176478$10580_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359442,167 +361939,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174829$10515 + cell $not $not$libresoc.v:176461$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174829$10515_Y + connect \Y $not$libresoc.v:176461$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174831$10517 + cell $not $not$libresoc.v:176463$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174831$10517_Y + connect \Y $not$libresoc.v:176463$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174833$10519 + cell $not $not$libresoc.v:176465$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174833$10519_Y + connect \Y $not$libresoc.v:176465$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174834$10520 + cell $not $not$libresoc.v:176466$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:174834$10520_Y + connect \Y $not$libresoc.v:176466$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174836$10522 + cell $not $not$libresoc.v:176468$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174836$10522_Y + connect \Y $not$libresoc.v:176468$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174838$10524 + cell $not $not$libresoc.v:176470$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174838$10524_Y + connect \Y $not$libresoc.v:176470$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174840$10526 + cell $not $not$libresoc.v:176472$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174840$10526_Y + connect \Y $not$libresoc.v:176472$10574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174842$10528 + cell $not $not$libresoc.v:176474$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:174842$10528_Y + connect \Y $not$libresoc.v:176474$10576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174845$10531 + cell $not $not$libresoc.v:176477$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174845$10531_Y + connect \Y $not$libresoc.v:176477$10579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174830$10516 + cell $reduce_or $reduce_or$libresoc.v:176462$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:174830$10516_Y + connect \Y $reduce_or$libresoc.v:176462$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174832$10518 + cell $reduce_or $reduce_or$libresoc.v:176464$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:174832$10518_Y + connect \Y $reduce_or$libresoc.v:176464$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174835$10521 + cell $reduce_or $reduce_or$libresoc.v:176467$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:174835$10521_Y + connect \Y $reduce_or$libresoc.v:176467$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174837$10523 + cell $reduce_or $reduce_or$libresoc.v:176469$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:174837$10523_Y + connect \Y $reduce_or$libresoc.v:176469$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174839$10525 + cell $reduce_or $reduce_or$libresoc.v:176471$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:174839$10525_Y + connect \Y $reduce_or$libresoc.v:176471$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174841$10527 + cell $reduce_or $reduce_or$libresoc.v:176473$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:174841$10527_Y + connect \Y $reduce_or$libresoc.v:176473$10575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174843$10529 + cell $reduce_or $reduce_or$libresoc.v:176475$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174843$10529_Y + connect \Y $reduce_or$libresoc.v:176475$10577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174844$10530 + cell $reduce_or $reduce_or$libresoc.v:176476$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174844$10530_Y + connect \Y $reduce_or$libresoc.v:176476$10578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174846$10532 + cell $reduce_or $reduce_or$libresoc.v:176478$10580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174846$10532_Y - end - connect \$7 $not$libresoc.v:174829$10515_Y - connect \$12 $reduce_or$libresoc.v:174830$10516_Y - connect \$11 $not$libresoc.v:174831$10517_Y - connect \$16 $reduce_or$libresoc.v:174832$10518_Y - connect \$15 $not$libresoc.v:174833$10519_Y - connect \$1 $not$libresoc.v:174834$10520_Y - connect \$20 $reduce_or$libresoc.v:174835$10521_Y - connect \$19 $not$libresoc.v:174836$10522_Y - connect \$24 $reduce_or$libresoc.v:174837$10523_Y - connect \$23 $not$libresoc.v:174838$10524_Y - connect \$28 $reduce_or$libresoc.v:174839$10525_Y - connect \$27 $not$libresoc.v:174840$10526_Y - connect \$32 $reduce_or$libresoc.v:174841$10527_Y - connect \$31 $not$libresoc.v:174842$10528_Y - connect \$35 $reduce_or$libresoc.v:174843$10529_Y - connect \$4 $reduce_or$libresoc.v:174844$10530_Y - connect \$3 $not$libresoc.v:174845$10531_Y - connect \$8 $reduce_or$libresoc.v:174846$10532_Y + connect \Y $reduce_or$libresoc.v:176478$10580_Y + end + connect \$7 $not$libresoc.v:176461$10563_Y + connect \$12 $reduce_or$libresoc.v:176462$10564_Y + connect \$11 $not$libresoc.v:176463$10565_Y + connect \$16 $reduce_or$libresoc.v:176464$10566_Y + connect \$15 $not$libresoc.v:176465$10567_Y + connect \$1 $not$libresoc.v:176466$10568_Y + connect \$20 $reduce_or$libresoc.v:176467$10569_Y + connect \$19 $not$libresoc.v:176468$10570_Y + connect \$24 $reduce_or$libresoc.v:176469$10571_Y + connect \$23 $not$libresoc.v:176470$10572_Y + connect \$28 $reduce_or$libresoc.v:176471$10573_Y + connect \$27 $not$libresoc.v:176472$10574_Y + connect \$32 $reduce_or$libresoc.v:176473$10575_Y + connect \$31 $not$libresoc.v:176474$10576_Y + connect \$35 $reduce_or$libresoc.v:176475$10577_Y + connect \$4 $reduce_or$libresoc.v:176476$10578_Y + connect \$3 $not$libresoc.v:176477$10579_Y + connect \$8 $reduce_or$libresoc.v:176478$10580_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -359616,43 +362113,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174863.1-174947.10" +attribute \src "libresoc.v:176495.1-176579.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:174920.17-174920.91" - wire $not$libresoc.v:174920$10533_Y - attribute \src "libresoc.v:174922.18-174922.93" - wire $not$libresoc.v:174922$10535_Y - attribute \src "libresoc.v:174924.18-174924.93" - wire $not$libresoc.v:174924$10537_Y - attribute \src "libresoc.v:174925.17-174925.89" - wire width 8 $not$libresoc.v:174925$10538_Y - attribute \src "libresoc.v:174927.18-174927.93" - wire $not$libresoc.v:174927$10540_Y - attribute \src "libresoc.v:174929.18-174929.93" - wire $not$libresoc.v:174929$10542_Y - attribute \src "libresoc.v:174931.18-174931.93" - wire $not$libresoc.v:174931$10544_Y - attribute \src "libresoc.v:174934.17-174934.91" - wire $not$libresoc.v:174934$10547_Y - attribute \src "libresoc.v:174921.18-174921.106" - wire $reduce_or$libresoc.v:174921$10534_Y - attribute \src "libresoc.v:174923.18-174923.106" - wire $reduce_or$libresoc.v:174923$10536_Y - attribute \src "libresoc.v:174926.18-174926.106" - wire $reduce_or$libresoc.v:174926$10539_Y - attribute \src "libresoc.v:174928.18-174928.106" - wire $reduce_or$libresoc.v:174928$10541_Y - attribute \src "libresoc.v:174930.18-174930.106" - wire $reduce_or$libresoc.v:174930$10543_Y - attribute \src "libresoc.v:174932.18-174932.90" - wire $reduce_or$libresoc.v:174932$10545_Y - attribute \src "libresoc.v:174933.17-174933.103" - wire $reduce_or$libresoc.v:174933$10546_Y - attribute \src "libresoc.v:174935.17-174935.105" - wire $reduce_or$libresoc.v:174935$10548_Y + attribute \src "libresoc.v:176552.17-176552.91" + wire $not$libresoc.v:176552$10581_Y + attribute \src "libresoc.v:176554.18-176554.93" + wire $not$libresoc.v:176554$10583_Y + attribute \src "libresoc.v:176556.18-176556.93" + wire $not$libresoc.v:176556$10585_Y + attribute \src "libresoc.v:176557.17-176557.89" + wire width 8 $not$libresoc.v:176557$10586_Y + attribute \src "libresoc.v:176559.18-176559.93" + wire $not$libresoc.v:176559$10588_Y + attribute \src "libresoc.v:176561.18-176561.93" + wire $not$libresoc.v:176561$10590_Y + attribute \src "libresoc.v:176563.18-176563.93" + wire $not$libresoc.v:176563$10592_Y + attribute \src "libresoc.v:176566.17-176566.91" + wire $not$libresoc.v:176566$10595_Y + attribute \src "libresoc.v:176553.18-176553.106" + wire $reduce_or$libresoc.v:176553$10582_Y + attribute \src "libresoc.v:176555.18-176555.106" + wire $reduce_or$libresoc.v:176555$10584_Y + attribute \src "libresoc.v:176558.18-176558.106" + wire $reduce_or$libresoc.v:176558$10587_Y + attribute \src "libresoc.v:176560.18-176560.106" + wire $reduce_or$libresoc.v:176560$10589_Y + attribute \src "libresoc.v:176562.18-176562.106" + wire $reduce_or$libresoc.v:176562$10591_Y + attribute \src "libresoc.v:176564.18-176564.90" + wire $reduce_or$libresoc.v:176564$10593_Y + attribute \src "libresoc.v:176565.17-176565.103" + wire $reduce_or$libresoc.v:176565$10594_Y + attribute \src "libresoc.v:176567.17-176567.105" + wire $reduce_or$libresoc.v:176567$10596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359710,149 +362207,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174920$10533 + cell $not $not$libresoc.v:176552$10581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174920$10533_Y + connect \Y $not$libresoc.v:176552$10581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174922$10535 + cell $not $not$libresoc.v:176554$10583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174922$10535_Y + connect \Y $not$libresoc.v:176554$10583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174924$10537 + cell $not $not$libresoc.v:176556$10585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174924$10537_Y + connect \Y $not$libresoc.v:176556$10585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174925$10538 + cell $not $not$libresoc.v:176557$10586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:174925$10538_Y + connect \Y $not$libresoc.v:176557$10586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174927$10540 + cell $not $not$libresoc.v:176559$10588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174927$10540_Y + connect \Y $not$libresoc.v:176559$10588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174929$10542 + cell $not $not$libresoc.v:176561$10590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174929$10542_Y + connect \Y $not$libresoc.v:176561$10590_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174931$10544 + cell $not $not$libresoc.v:176563$10592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174931$10544_Y + connect \Y $not$libresoc.v:176563$10592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174934$10547 + cell $not $not$libresoc.v:176566$10595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174934$10547_Y + connect \Y $not$libresoc.v:176566$10595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174921$10534 + cell $reduce_or $reduce_or$libresoc.v:176553$10582 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:174921$10534_Y + connect \Y $reduce_or$libresoc.v:176553$10582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174923$10536 + cell $reduce_or $reduce_or$libresoc.v:176555$10584 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:174923$10536_Y + connect \Y $reduce_or$libresoc.v:176555$10584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174926$10539 + cell $reduce_or $reduce_or$libresoc.v:176558$10587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:174926$10539_Y + connect \Y $reduce_or$libresoc.v:176558$10587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174928$10541 + cell $reduce_or $reduce_or$libresoc.v:176560$10589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:174928$10541_Y + connect \Y $reduce_or$libresoc.v:176560$10589_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174930$10543 + cell $reduce_or $reduce_or$libresoc.v:176562$10591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:174930$10543_Y + connect \Y $reduce_or$libresoc.v:176562$10591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174932$10545 + cell $reduce_or $reduce_or$libresoc.v:176564$10593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174932$10545_Y + connect \Y $reduce_or$libresoc.v:176564$10593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174933$10546 + cell $reduce_or $reduce_or$libresoc.v:176565$10594 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174933$10546_Y + connect \Y $reduce_or$libresoc.v:176565$10594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174935$10548 + cell $reduce_or $reduce_or$libresoc.v:176567$10596 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174935$10548_Y - end - connect \$7 $not$libresoc.v:174920$10533_Y - connect \$12 $reduce_or$libresoc.v:174921$10534_Y - connect \$11 $not$libresoc.v:174922$10535_Y - connect \$16 $reduce_or$libresoc.v:174923$10536_Y - connect \$15 $not$libresoc.v:174924$10537_Y - connect \$1 $not$libresoc.v:174925$10538_Y - connect \$20 $reduce_or$libresoc.v:174926$10539_Y - connect \$19 $not$libresoc.v:174927$10540_Y - connect \$24 $reduce_or$libresoc.v:174928$10541_Y - connect \$23 $not$libresoc.v:174929$10542_Y - connect \$28 $reduce_or$libresoc.v:174930$10543_Y - connect \$27 $not$libresoc.v:174931$10544_Y - connect \$31 $reduce_or$libresoc.v:174932$10545_Y - connect \$4 $reduce_or$libresoc.v:174933$10546_Y - connect \$3 $not$libresoc.v:174934$10547_Y - connect \$8 $reduce_or$libresoc.v:174935$10548_Y + connect \Y $reduce_or$libresoc.v:176567$10596_Y + end + connect \$7 $not$libresoc.v:176552$10581_Y + connect \$12 $reduce_or$libresoc.v:176553$10582_Y + connect \$11 $not$libresoc.v:176554$10583_Y + connect \$16 $reduce_or$libresoc.v:176555$10584_Y + connect \$15 $not$libresoc.v:176556$10585_Y + connect \$1 $not$libresoc.v:176557$10586_Y + connect \$20 $reduce_or$libresoc.v:176558$10587_Y + connect \$19 $not$libresoc.v:176559$10588_Y + connect \$24 $reduce_or$libresoc.v:176560$10589_Y + connect \$23 $not$libresoc.v:176561$10590_Y + connect \$28 $reduce_or$libresoc.v:176562$10591_Y + connect \$27 $not$libresoc.v:176563$10592_Y + connect \$31 $reduce_or$libresoc.v:176564$10593_Y + connect \$4 $reduce_or$libresoc.v:176565$10594_Y + connect \$3 $not$libresoc.v:176566$10595_Y + connect \$8 $reduce_or$libresoc.v:176567$10596_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -359865,19 +362362,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174951.1-174981.10" +attribute \src "libresoc.v:176583.1-176613.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:174972.17-174972.89" - wire width 2 $not$libresoc.v:174972$10549_Y - attribute \src "libresoc.v:174974.17-174974.91" - wire $not$libresoc.v:174974$10551_Y - attribute \src "libresoc.v:174973.17-174973.103" - wire $reduce_or$libresoc.v:174973$10550_Y - attribute \src "libresoc.v:174975.17-174975.89" - wire $reduce_or$libresoc.v:174975$10552_Y + attribute \src "libresoc.v:176604.17-176604.89" + wire width 2 $not$libresoc.v:176604$10597_Y + attribute \src "libresoc.v:176606.17-176606.91" + wire $not$libresoc.v:176606$10599_Y + attribute \src "libresoc.v:176605.17-176605.103" + wire $reduce_or$libresoc.v:176605$10598_Y + attribute \src "libresoc.v:176607.17-176607.89" + wire $reduce_or$libresoc.v:176607$10600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359899,56 +362396,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174972$10549 + cell $not $not$libresoc.v:176604$10597 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174972$10549_Y + connect \Y $not$libresoc.v:176604$10597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174974$10551 + cell $not $not$libresoc.v:176606$10599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174974$10551_Y + connect \Y $not$libresoc.v:176606$10599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174973$10550 + cell $reduce_or $reduce_or$libresoc.v:176605$10598 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174973$10550_Y + connect \Y $reduce_or$libresoc.v:176605$10598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174975$10552 + cell $reduce_or $reduce_or$libresoc.v:176607$10600 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174975$10552_Y + connect \Y $reduce_or$libresoc.v:176607$10600_Y end - connect \$1 $not$libresoc.v:174972$10549_Y - connect \$4 $reduce_or$libresoc.v:174973$10550_Y - connect \$3 $not$libresoc.v:174974$10551_Y - connect \$7 $reduce_or$libresoc.v:174975$10552_Y + connect \$1 $not$libresoc.v:176604$10597_Y + connect \$4 $reduce_or$libresoc.v:176605$10598_Y + connect \$3 $not$libresoc.v:176606$10599_Y + connect \$7 $reduce_or$libresoc.v:176607$10600_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174985.1-175006.10" +attribute \src "libresoc.v:176617.1-176638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:175000.17-175000.89" - wire $not$libresoc.v:175000$10553_Y - attribute \src "libresoc.v:175001.17-175001.89" - wire $reduce_or$libresoc.v:175001$10554_Y + attribute \src "libresoc.v:176632.17-176632.89" + wire $not$libresoc.v:176632$10601_Y + attribute \src "libresoc.v:176633.17-176633.89" + wire $reduce_or$libresoc.v:176633$10602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359964,45 +362461,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175000$10553 + cell $not $not$libresoc.v:176632$10601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:175000$10553_Y + connect \Y $not$libresoc.v:176632$10601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175001$10554 + cell $reduce_or $reduce_or$libresoc.v:176633$10602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175001$10554_Y + connect \Y $reduce_or$libresoc.v:176633$10602_Y end - connect \$1 $not$libresoc.v:175000$10553_Y - connect \$3 $reduce_or$libresoc.v:175001$10554_Y + connect \$1 $not$libresoc.v:176632$10601_Y + connect \$3 $reduce_or$libresoc.v:176633$10602_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:175010.1-175049.10" +attribute \src "libresoc.v:176642.1-176681.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:175037.17-175037.91" - wire $not$libresoc.v:175037$10555_Y - attribute \src "libresoc.v:175039.17-175039.89" - wire width 3 $not$libresoc.v:175039$10557_Y - attribute \src "libresoc.v:175041.17-175041.91" - wire $not$libresoc.v:175041$10559_Y - attribute \src "libresoc.v:175038.18-175038.90" - wire $reduce_or$libresoc.v:175038$10556_Y - attribute \src "libresoc.v:175040.17-175040.103" - wire $reduce_or$libresoc.v:175040$10558_Y - attribute \src "libresoc.v:175042.17-175042.105" - wire $reduce_or$libresoc.v:175042$10560_Y + attribute \src "libresoc.v:176669.17-176669.91" + wire $not$libresoc.v:176669$10603_Y + attribute \src "libresoc.v:176671.17-176671.89" + wire width 3 $not$libresoc.v:176671$10605_Y + attribute \src "libresoc.v:176673.17-176673.91" + wire $not$libresoc.v:176673$10607_Y + attribute \src "libresoc.v:176670.18-176670.90" + wire $reduce_or$libresoc.v:176670$10604_Y + attribute \src "libresoc.v:176672.17-176672.103" + wire $reduce_or$libresoc.v:176672$10606_Y + attribute \src "libresoc.v:176674.17-176674.105" + wire $reduce_or$libresoc.v:176674$10608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -360030,59 +362527,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175037$10555 + cell $not $not$libresoc.v:176669$10603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:175037$10555_Y + connect \Y $not$libresoc.v:176669$10603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175039$10557 + cell $not $not$libresoc.v:176671$10605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:175039$10557_Y + connect \Y $not$libresoc.v:176671$10605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175041$10559 + cell $not $not$libresoc.v:176673$10607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:175041$10559_Y + connect \Y $not$libresoc.v:176673$10607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175038$10556 + cell $reduce_or $reduce_or$libresoc.v:176670$10604 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175038$10556_Y + connect \Y $reduce_or$libresoc.v:176670$10604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175040$10558 + cell $reduce_or $reduce_or$libresoc.v:176672$10606 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:175040$10558_Y + connect \Y $reduce_or$libresoc.v:176672$10606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175042$10560 + cell $reduce_or $reduce_or$libresoc.v:176674$10608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:175042$10560_Y - end - connect \$7 $not$libresoc.v:175037$10555_Y - connect \$11 $reduce_or$libresoc.v:175038$10556_Y - connect \$1 $not$libresoc.v:175039$10557_Y - connect \$4 $reduce_or$libresoc.v:175040$10558_Y - connect \$3 $not$libresoc.v:175041$10559_Y - connect \$8 $reduce_or$libresoc.v:175042$10560_Y + connect \Y $reduce_or$libresoc.v:176674$10608_Y + end + connect \$7 $not$libresoc.v:176669$10603_Y + connect \$11 $reduce_or$libresoc.v:176670$10604_Y + connect \$1 $not$libresoc.v:176671$10605_Y + connect \$4 $reduce_or$libresoc.v:176672$10606_Y + connect \$3 $not$libresoc.v:176673$10607_Y + connect \$8 $reduce_or$libresoc.v:176674$10608_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -360090,15 +362587,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:175053.1-175074.10" +attribute \src "libresoc.v:176685.1-176706.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:175068.17-175068.89" - wire $not$libresoc.v:175068$10561_Y - attribute \src "libresoc.v:175069.17-175069.89" - wire $reduce_or$libresoc.v:175069$10562_Y + attribute \src "libresoc.v:176700.17-176700.89" + wire $not$libresoc.v:176700$10609_Y + attribute \src "libresoc.v:176701.17-176701.89" + wire $reduce_or$libresoc.v:176701$10610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -360114,57 +362611,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175068$10561 + cell $not $not$libresoc.v:176700$10609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:175068$10561_Y + connect \Y $not$libresoc.v:176700$10609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175069$10562 + cell $reduce_or $reduce_or$libresoc.v:176701$10610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175069$10562_Y + connect \Y $reduce_or$libresoc.v:176701$10610_Y end - connect \$1 $not$libresoc.v:175068$10561_Y - connect \$3 $reduce_or$libresoc.v:175069$10562_Y + connect \$1 $not$libresoc.v:176700$10609_Y + connect \$3 $reduce_or$libresoc.v:176701$10610_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:175078.1-175144.10" +attribute \src "libresoc.v:176710.1-176776.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:175123.17-175123.91" - wire $not$libresoc.v:175123$10563_Y - attribute \src "libresoc.v:175125.18-175125.93" - wire $not$libresoc.v:175125$10565_Y - attribute \src "libresoc.v:175127.18-175127.93" - wire $not$libresoc.v:175127$10567_Y - attribute \src "libresoc.v:175128.17-175128.89" - wire width 6 $not$libresoc.v:175128$10568_Y - attribute \src "libresoc.v:175130.18-175130.93" - wire $not$libresoc.v:175130$10570_Y - attribute \src "libresoc.v:175133.17-175133.91" - wire $not$libresoc.v:175133$10573_Y - attribute \src "libresoc.v:175124.18-175124.106" - wire $reduce_or$libresoc.v:175124$10564_Y - attribute \src "libresoc.v:175126.18-175126.106" - wire $reduce_or$libresoc.v:175126$10566_Y - attribute \src "libresoc.v:175129.18-175129.106" - wire $reduce_or$libresoc.v:175129$10569_Y - attribute \src "libresoc.v:175131.18-175131.90" - wire $reduce_or$libresoc.v:175131$10571_Y - attribute \src "libresoc.v:175132.17-175132.103" - wire $reduce_or$libresoc.v:175132$10572_Y - attribute \src "libresoc.v:175134.17-175134.105" - wire $reduce_or$libresoc.v:175134$10574_Y + attribute \src "libresoc.v:176755.17-176755.91" + wire $not$libresoc.v:176755$10611_Y + attribute \src "libresoc.v:176757.18-176757.93" + wire $not$libresoc.v:176757$10613_Y + attribute \src "libresoc.v:176759.18-176759.93" + wire $not$libresoc.v:176759$10615_Y + attribute \src "libresoc.v:176760.17-176760.89" + wire width 6 $not$libresoc.v:176760$10616_Y + attribute \src "libresoc.v:176762.18-176762.93" + wire $not$libresoc.v:176762$10618_Y + attribute \src "libresoc.v:176765.17-176765.91" + wire $not$libresoc.v:176765$10621_Y + attribute \src "libresoc.v:176756.18-176756.106" + wire $reduce_or$libresoc.v:176756$10612_Y + attribute \src "libresoc.v:176758.18-176758.106" + wire $reduce_or$libresoc.v:176758$10614_Y + attribute \src "libresoc.v:176761.18-176761.106" + wire $reduce_or$libresoc.v:176761$10617_Y + attribute \src "libresoc.v:176763.18-176763.90" + wire $reduce_or$libresoc.v:176763$10619_Y + attribute \src "libresoc.v:176764.17-176764.103" + wire $reduce_or$libresoc.v:176764$10620_Y + attribute \src "libresoc.v:176766.17-176766.105" + wire $reduce_or$libresoc.v:176766$10622_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -360210,113 +362707,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175123$10563 + cell $not $not$libresoc.v:176755$10611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:175123$10563_Y + connect \Y $not$libresoc.v:176755$10611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175125$10565 + cell $not $not$libresoc.v:176757$10613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:175125$10565_Y + connect \Y $not$libresoc.v:176757$10613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175127$10567 + cell $not $not$libresoc.v:176759$10615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:175127$10567_Y + connect \Y $not$libresoc.v:176759$10615_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175128$10568 + cell $not $not$libresoc.v:176760$10616 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:175128$10568_Y + connect \Y $not$libresoc.v:176760$10616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175130$10570 + cell $not $not$libresoc.v:176762$10618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:175130$10570_Y + connect \Y $not$libresoc.v:176762$10618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175133$10573 + cell $not $not$libresoc.v:176765$10621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:175133$10573_Y + connect \Y $not$libresoc.v:176765$10621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175124$10564 + cell $reduce_or $reduce_or$libresoc.v:176756$10612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:175124$10564_Y + connect \Y $reduce_or$libresoc.v:176756$10612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175126$10566 + cell $reduce_or $reduce_or$libresoc.v:176758$10614 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:175126$10566_Y + connect \Y $reduce_or$libresoc.v:176758$10614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175129$10569 + cell $reduce_or $reduce_or$libresoc.v:176761$10617 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:175129$10569_Y + connect \Y $reduce_or$libresoc.v:176761$10617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175131$10571 + cell $reduce_or $reduce_or$libresoc.v:176763$10619 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175131$10571_Y + connect \Y $reduce_or$libresoc.v:176763$10619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175132$10572 + cell $reduce_or $reduce_or$libresoc.v:176764$10620 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:175132$10572_Y + connect \Y $reduce_or$libresoc.v:176764$10620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175134$10574 + cell $reduce_or $reduce_or$libresoc.v:176766$10622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:175134$10574_Y - end - connect \$7 $not$libresoc.v:175123$10563_Y - connect \$12 $reduce_or$libresoc.v:175124$10564_Y - connect \$11 $not$libresoc.v:175125$10565_Y - connect \$16 $reduce_or$libresoc.v:175126$10566_Y - connect \$15 $not$libresoc.v:175127$10567_Y - connect \$1 $not$libresoc.v:175128$10568_Y - connect \$20 $reduce_or$libresoc.v:175129$10569_Y - connect \$19 $not$libresoc.v:175130$10570_Y - connect \$23 $reduce_or$libresoc.v:175131$10571_Y - connect \$4 $reduce_or$libresoc.v:175132$10572_Y - connect \$3 $not$libresoc.v:175133$10573_Y - connect \$8 $reduce_or$libresoc.v:175134$10574_Y + connect \Y $reduce_or$libresoc.v:176766$10622_Y + end + connect \$7 $not$libresoc.v:176755$10611_Y + connect \$12 $reduce_or$libresoc.v:176756$10612_Y + connect \$11 $not$libresoc.v:176757$10613_Y + connect \$16 $reduce_or$libresoc.v:176758$10614_Y + connect \$15 $not$libresoc.v:176759$10615_Y + connect \$1 $not$libresoc.v:176760$10616_Y + connect \$20 $reduce_or$libresoc.v:176761$10617_Y + connect \$19 $not$libresoc.v:176762$10618_Y + connect \$23 $reduce_or$libresoc.v:176763$10619_Y + connect \$4 $reduce_or$libresoc.v:176764$10620_Y + connect \$3 $not$libresoc.v:176765$10621_Y + connect \$8 $reduce_or$libresoc.v:176766$10622_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -360327,239 +362824,277 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:175148.1-175619.10" +attribute \src "libresoc.v:176780.1-177335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:175149.7-175149.20" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 + attribute \src "libresoc.v:176886.3-176887.49" + wire width 4 $0\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:176781.7-176781.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $0\r0__data_o$next[3:0]$10630 - attribute \src "libresoc.v:175234.3-175235.37" + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $0\r0__data_o$next[3:0]$10708 + attribute \src "libresoc.v:176878.3-176879.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $0\r20__data_o$next[3:0]$10644 - attribute \src "libresoc.v:175232.3-175233.39" + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $0\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:176876.3-176877.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $0\reg$next[3:0]$10596 - attribute \src "libresoc.v:175230.3-175231.25" + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $0\reg$next[3:0]$10660 + attribute \src "libresoc.v:176874.3-176875.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $0\src10__data_o$next[3:0]$10587 - attribute \src "libresoc.v:175240.3-175241.43" + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $0\src10__data_o$next[3:0]$10666 + attribute \src "libresoc.v:176884.3-176885.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $0\src20__data_o$next[3:0]$10602 - attribute \src "libresoc.v:175238.3-175239.43" + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $0\src20__data_o$next[3:0]$10680 + attribute \src "libresoc.v:176882.3-176883.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $0\src30__data_o$next[3:0]$10616 - attribute \src "libresoc.v:175236.3-175237.43" + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $0\src30__data_o$next[3:0]$10694 + attribute \src "libresoc.v:176880.3-176881.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:175519.3-175548.6" - wire $0\wr_detect$10[0:0]$10638 - attribute \src "libresoc.v:175589.3-175618.6" - wire $0\wr_detect$13[0:0]$10652 - attribute \src "libresoc.v:175379.3-175408.6" - wire $0\wr_detect$4[0:0]$10610 - attribute \src "libresoc.v:175449.3-175478.6" - wire $0\wr_detect$7[0:0]$10624 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:177235.3-177264.6" + wire $0\wr_detect$10[0:0]$10702 + attribute \src "libresoc.v:177305.3-177334.6" + wire $0\wr_detect$13[0:0]$10716 + attribute \src "libresoc.v:176998.3-177027.6" + wire $0\wr_detect$16[0:0]$10654 + attribute \src "libresoc.v:177095.3-177124.6" + wire $0\wr_detect$4[0:0]$10674 + attribute \src "libresoc.v:177165.3-177194.6" + wire $0\wr_detect$7[0:0]$10688 + attribute \src "libresoc.v:176928.3-176957.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $1\r0__data_o$next[3:0]$10631 - attribute \src "libresoc.v:175174.13-175174.30" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 + attribute \src "libresoc.v:176800.13-176800.36" + wire width 4 $1\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $1\r0__data_o$next[3:0]$10709 + attribute \src "libresoc.v:176815.13-176815.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $1\r20__data_o$next[3:0]$10645 - attribute \src "libresoc.v:175181.13-175181.31" + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $1\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:176822.13-176822.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $1\reg$next[3:0]$10597 - attribute \src "libresoc.v:175187.13-175187.25" + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $1\reg$next[3:0]$10661 + attribute \src "libresoc.v:176828.13-176828.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $1\src10__data_o$next[3:0]$10588 - attribute \src "libresoc.v:175192.13-175192.33" + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $1\src10__data_o$next[3:0]$10667 + attribute \src "libresoc.v:176833.13-176833.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $1\src20__data_o$next[3:0]$10603 - attribute \src "libresoc.v:175199.13-175199.33" + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $1\src20__data_o$next[3:0]$10681 + attribute \src "libresoc.v:176840.13-176840.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $1\src30__data_o$next[3:0]$10617 - attribute \src "libresoc.v:175206.13-175206.33" + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $1\src30__data_o$next[3:0]$10695 + attribute \src "libresoc.v:176847.13-176847.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:175519.3-175548.6" - wire $1\wr_detect$10[0:0]$10639 - attribute \src "libresoc.v:175589.3-175618.6" - wire $1\wr_detect$13[0:0]$10653 - attribute \src "libresoc.v:175379.3-175408.6" - wire $1\wr_detect$4[0:0]$10611 - attribute \src "libresoc.v:175449.3-175478.6" - wire $1\wr_detect$7[0:0]$10625 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:177235.3-177264.6" + wire $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177305.3-177334.6" + wire $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:176998.3-177027.6" + wire $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:177095.3-177124.6" + wire $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177165.3-177194.6" + wire $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:176928.3-176957.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $2\r0__data_o$next[3:0]$10632 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $2\r20__data_o$next[3:0]$10646 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $2\reg$next[3:0]$10598 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $2\src10__data_o$next[3:0]$10589 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $2\src20__data_o$next[3:0]$10604 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $2\src30__data_o$next[3:0]$10618 - attribute \src "libresoc.v:175519.3-175548.6" - wire $2\wr_detect$10[0:0]$10640 - attribute \src "libresoc.v:175589.3-175618.6" - wire $2\wr_detect$13[0:0]$10654 - attribute \src "libresoc.v:175379.3-175408.6" - wire $2\wr_detect$4[0:0]$10612 - attribute \src "libresoc.v:175449.3-175478.6" - wire $2\wr_detect$7[0:0]$10626 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $2\r0__data_o$next[3:0]$10710 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $2\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $2\reg$next[3:0]$10662 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $2\src10__data_o$next[3:0]$10668 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $2\src20__data_o$next[3:0]$10682 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $2\src30__data_o$next[3:0]$10696 + attribute \src "libresoc.v:177235.3-177264.6" + wire $2\wr_detect$10[0:0]$10704 + attribute \src "libresoc.v:177305.3-177334.6" + wire $2\wr_detect$13[0:0]$10718 + attribute \src "libresoc.v:176998.3-177027.6" + wire $2\wr_detect$16[0:0]$10656 + attribute \src "libresoc.v:177095.3-177124.6" + wire $2\wr_detect$4[0:0]$10676 + attribute \src "libresoc.v:177165.3-177194.6" + wire $2\wr_detect$7[0:0]$10690 + attribute \src "libresoc.v:176928.3-176957.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $3\r0__data_o$next[3:0]$10633 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $3\r20__data_o$next[3:0]$10647 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $3\reg$next[3:0]$10599 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $3\src10__data_o$next[3:0]$10590 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $3\src20__data_o$next[3:0]$10605 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $3\src30__data_o$next[3:0]$10619 - attribute \src "libresoc.v:175519.3-175548.6" - wire $3\wr_detect$10[0:0]$10641 - attribute \src "libresoc.v:175589.3-175618.6" - wire $3\wr_detect$13[0:0]$10655 - attribute \src "libresoc.v:175379.3-175408.6" - wire $3\wr_detect$4[0:0]$10613 - attribute \src "libresoc.v:175449.3-175478.6" - wire $3\wr_detect$7[0:0]$10627 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $3\r0__data_o$next[3:0]$10711 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $3\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $3\reg$next[3:0]$10663 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $3\src10__data_o$next[3:0]$10669 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $3\src20__data_o$next[3:0]$10683 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $3\src30__data_o$next[3:0]$10697 + attribute \src "libresoc.v:177235.3-177264.6" + wire $3\wr_detect$10[0:0]$10705 + attribute \src "libresoc.v:177305.3-177334.6" + wire $3\wr_detect$13[0:0]$10719 + attribute \src "libresoc.v:176998.3-177027.6" + wire $3\wr_detect$16[0:0]$10657 + attribute \src "libresoc.v:177095.3-177124.6" + wire $3\wr_detect$4[0:0]$10677 + attribute \src "libresoc.v:177165.3-177194.6" + wire $3\wr_detect$7[0:0]$10691 + attribute \src "libresoc.v:176928.3-176957.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $4\r0__data_o$next[3:0]$10634 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $4\r20__data_o$next[3:0]$10648 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $4\reg$next[3:0]$10600 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $4\src10__data_o$next[3:0]$10591 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $4\src20__data_o$next[3:0]$10606 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $4\src30__data_o$next[3:0]$10620 - attribute \src "libresoc.v:175519.3-175548.6" - wire $4\wr_detect$10[0:0]$10642 - attribute \src "libresoc.v:175589.3-175618.6" - wire $4\wr_detect$13[0:0]$10656 - attribute \src "libresoc.v:175379.3-175408.6" - wire $4\wr_detect$4[0:0]$10614 - attribute \src "libresoc.v:175449.3-175478.6" - wire $4\wr_detect$7[0:0]$10628 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $4\r0__data_o$next[3:0]$10712 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $4\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $4\src10__data_o$next[3:0]$10670 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $4\src20__data_o$next[3:0]$10684 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $4\src30__data_o$next[3:0]$10698 + attribute \src "libresoc.v:177235.3-177264.6" + wire $4\wr_detect$10[0:0]$10706 + attribute \src "libresoc.v:177305.3-177334.6" + wire $4\wr_detect$13[0:0]$10720 + attribute \src "libresoc.v:176998.3-177027.6" + wire $4\wr_detect$16[0:0]$10658 + attribute \src "libresoc.v:177095.3-177124.6" + wire $4\wr_detect$4[0:0]$10678 + attribute \src "libresoc.v:177165.3-177194.6" + wire $4\wr_detect$7[0:0]$10692 + attribute \src "libresoc.v:176928.3-176957.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $5\r0__data_o$next[3:0]$10635 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $5\r20__data_o$next[3:0]$10649 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $5\src10__data_o$next[3:0]$10592 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $5\src20__data_o$next[3:0]$10607 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $5\src30__data_o$next[3:0]$10621 - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $6\r0__data_o$next[3:0]$10636 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $6\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $6\src10__data_o$next[3:0]$10593 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $6\src20__data_o$next[3:0]$10608 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $6\src30__data_o$next[3:0]$10622 - attribute \src "libresoc.v:175225.17-175225.104" - wire $not$libresoc.v:175225$10575_Y - attribute \src "libresoc.v:175226.18-175226.105" - wire $not$libresoc.v:175226$10576_Y - attribute \src "libresoc.v:175227.17-175227.100" - wire $not$libresoc.v:175227$10577_Y - attribute \src "libresoc.v:175228.17-175228.103" - wire $not$libresoc.v:175228$10578_Y - attribute \src "libresoc.v:175229.17-175229.103" - wire $not$libresoc.v:175229$10579_Y + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $5\r0__data_o$next[3:0]$10713 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $5\r20__data_o$next[3:0]$10651 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $5\src10__data_o$next[3:0]$10671 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $5\src20__data_o$next[3:0]$10685 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $5\src30__data_o$next[3:0]$10699 + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:176868.17-176868.104" + wire $not$libresoc.v:176868$10623_Y + attribute \src "libresoc.v:176869.18-176869.105" + wire $not$libresoc.v:176869$10624_Y + attribute \src "libresoc.v:176870.18-176870.105" + wire $not$libresoc.v:176870$10625_Y + attribute \src "libresoc.v:176871.17-176871.100" + wire $not$libresoc.v:176871$10626_Y + attribute \src "libresoc.v:176872.17-176872.103" + wire $not$libresoc.v:176872$10627_Y + attribute \src "libresoc.v:176873.17-176873.103" + wire $not$libresoc.v:176873$10628_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest10__data_i + wire width 4 output 3 \cr_pred0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest10__wen + wire width 4 \cr_pred0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest20__data_i + wire input 2 \cr_pred0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest20__wen - attribute \src "libresoc.v:175149.7-175149.15" + wire width 4 input 11 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest20__wen + attribute \src "libresoc.v:176781.7-176781.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r0__data_o + wire width 4 output 14 \r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r0__ren + wire input 15 \r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r20__data_o + wire width 4 output 16 \r20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r20__ren + wire input 17 \r20__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src10__data_o + wire width 4 output 5 \src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src10__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src10__ren + wire input 4 \src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src20__data_o + wire width 4 output 7 \src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src20__ren + wire input 6 \src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src30__data_o + wire width 4 output 9 \src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src30__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src30__ren + wire input 8 \src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w0__data_i + wire width 4 input 18 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w0__wen + wire input 19 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -360567,232 +363102,257 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175225$10575 + cell $not $not$libresoc.v:176868$10623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:175225$10575_Y + connect \Y $not$libresoc.v:176868$10623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175226$10576 + cell $not $not$libresoc.v:176869$10624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:175226$10576_Y + connect \Y $not$libresoc.v:176869$10624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175227$10577 + cell $not $not$libresoc.v:176870$10625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:176870$10625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176871$10626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175227$10577_Y + connect \Y $not$libresoc.v:176871$10626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175228$10578 + cell $not $not$libresoc.v:176872$10627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175228$10578_Y + connect \Y $not$libresoc.v:176872$10627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175229$10579 + cell $not $not$libresoc.v:176873$10628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175229$10579_Y + connect \Y $not$libresoc.v:176873$10628_Y end - attribute \src "libresoc.v:175149.7-175149.20" - process $proc$libresoc.v:175149$10657 + attribute \src "libresoc.v:176781.7-176781.20" + process $proc$libresoc.v:176781$10721 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175174.13-175174.30" - process $proc$libresoc.v:175174$10658 + attribute \src "libresoc.v:176800.13-176800.36" + process $proc$libresoc.v:176800$10722 + assign { } { } + assign $1\cr_pred0__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176815.13-176815.30" + process $proc$libresoc.v:176815$10723 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:175181.13-175181.31" - process $proc$libresoc.v:175181$10659 + attribute \src "libresoc.v:176822.13-176822.31" + process $proc$libresoc.v:176822$10724 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:175187.13-175187.25" - process $proc$libresoc.v:175187$10660 + attribute \src "libresoc.v:176828.13-176828.25" + process $proc$libresoc.v:176828$10725 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:175192.13-175192.33" - process $proc$libresoc.v:175192$10661 + attribute \src "libresoc.v:176833.13-176833.33" + process $proc$libresoc.v:176833$10726 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:175199.13-175199.33" - process $proc$libresoc.v:175199$10662 + attribute \src "libresoc.v:176840.13-176840.33" + process $proc$libresoc.v:176840$10727 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:175206.13-175206.33" - process $proc$libresoc.v:175206$10663 + attribute \src "libresoc.v:176847.13-176847.33" + process $proc$libresoc.v:176847$10728 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:175230.3-175231.25" - process $proc$libresoc.v:175230$10580 + attribute \src "libresoc.v:176874.3-176875.25" + process $proc$libresoc.v:176874$10629 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:175232.3-175233.39" - process $proc$libresoc.v:175232$10581 + attribute \src "libresoc.v:176876.3-176877.39" + process $proc$libresoc.v:176876$10630 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:175234.3-175235.37" - process $proc$libresoc.v:175234$10582 + attribute \src "libresoc.v:176878.3-176879.37" + process $proc$libresoc.v:176878$10631 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:175236.3-175237.43" - process $proc$libresoc.v:175236$10583 + attribute \src "libresoc.v:176880.3-176881.43" + process $proc$libresoc.v:176880$10632 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:175238.3-175239.43" - process $proc$libresoc.v:175238$10584 + attribute \src "libresoc.v:176882.3-176883.43" + process $proc$libresoc.v:176882$10633 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:175240.3-175241.43" - process $proc$libresoc.v:175240$10585 + attribute \src "libresoc.v:176884.3-176885.43" + process $proc$libresoc.v:176884$10634 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:175242.3-175281.6" - process $proc$libresoc.v:175242$10586 + attribute \src "libresoc.v:176886.3-176887.49" + process $proc$libresoc.v:176886$10635 + assign { } { } + assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next + sync posedge \coresync_clk + update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176888.3-176927.6" + process $proc$libresoc.v:176888$10636 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 - attribute \src "libresoc.v:175243.5-175243.29" + assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:176889.5-176889.29" switch \initial - attribute \src "libresoc.v:175243.9-175243.17" + attribute \src "libresoc.v:176889.9-176889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \cr_pred0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 + assign $1\cr_pred0__data_o$next[3:0]$10638 $5\cr_pred0__data_o$next[3:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i + assign $2\cr_pred0__data_o$next[3:0]$10639 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10589 4'0000 + assign $2\cr_pred0__data_o$next[3:0]$10639 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i + assign $3\cr_pred0__data_o$next[3:0]$10640 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 + assign $3\cr_pred0__data_o$next[3:0]$10640 $2\cr_pred0__data_o$next[3:0]$10639 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10591 \w0__data_i + assign $4\cr_pred0__data_o$next[3:0]$10641 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 + assign $4\cr_pred0__data_o$next[3:0]$10641 $3\cr_pred0__data_o$next[3:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10592 \reg + assign $5\cr_pred0__data_o$next[3:0]$10642 \reg case - assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 + assign $5\cr_pred0__data_o$next[3:0]$10642 $4\cr_pred0__data_o$next[3:0]$10641 end case - assign $1\src10__data_o$next[3:0]$10588 4'0000 + assign $1\cr_pred0__data_o$next[3:0]$10638 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10593 4'0000 + assign $6\cr_pred0__data_o$next[3:0]$10643 4'0000 case - assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 + assign $6\cr_pred0__data_o$next[3:0]$10643 $1\cr_pred0__data_o$next[3:0]$10638 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 + update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 end - attribute \src "libresoc.v:175282.3-175311.6" - process $proc$libresoc.v:175282$10594 + attribute \src "libresoc.v:176928.3-176957.6" + process $proc$libresoc.v:176928$10644 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175283.5-175283.29" + attribute \src "libresoc.v:176929.5-176929.29" switch \initial - attribute \src "libresoc.v:175283.9-175283.17" + attribute \src "libresoc.v:176929.9-176929.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \cr_pred0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -360833,724 +363393,850 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175312.3-175338.6" - process $proc$libresoc.v:175312$10595 - assign { } { } - assign { } { } + attribute \src "libresoc.v:176958.3-176997.6" + process $proc$libresoc.v:176958$10645 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 - attribute \src "libresoc.v:175313.5-175313.29" + assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:176959.5-176959.29" switch \initial - attribute \src "libresoc.v:175313.9-175313.17" + attribute \src "libresoc.v:176959.9-176959.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10597 \dest10__data_i - case - assign $1\reg$next[3:0]$10597 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$10598 \dest20__data_i - case - assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$10599 \w0__data_i + assign { } { } + assign $1\r20__data_o$next[3:0]$10647 $5\r20__data_o$next[3:0]$10651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10648 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10649 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10649 $2\r20__data_o$next[3:0]$10648 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10650 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10650 $3\r20__data_o$next[3:0]$10649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10651 \reg + case + assign $5\r20__data_o$next[3:0]$10651 $4\r20__data_o$next[3:0]$10650 + end case - assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 + assign $1\r20__data_o$next[3:0]$10647 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10600 4'0000 + assign $6\r20__data_o$next[3:0]$10652 4'0000 case - assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 + assign $6\r20__data_o$next[3:0]$10652 $1\r20__data_o$next[3:0]$10647 end sync always - update \reg$next $0\reg$next[3:0]$10596 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 end - attribute \src "libresoc.v:175339.3-175378.6" - process $proc$libresoc.v:175339$10601 - assign { } { } + attribute \src "libresoc.v:176998.3-177027.6" + process $proc$libresoc.v:176998$10653 assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 - attribute \src "libresoc.v:175340.5-175340.29" + assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:176999.5-176999.29" switch \initial - attribute \src "libresoc.v:175340.9-175340.17" + attribute \src "libresoc.v:176999.9-176999.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 + assign $1\wr_detect$16[0:0]$10655 $4\wr_detect$16[0:0]$10658 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i + assign $2\wr_detect$16[0:0]$10656 1'1 case - assign $2\src20__data_o$next[3:0]$10604 4'0000 + assign $2\wr_detect$16[0:0]$10656 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i + assign $3\wr_detect$16[0:0]$10657 1'1 case - assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 + assign $3\wr_detect$16[0:0]$10657 $2\wr_detect$16[0:0]$10656 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10606 \w0__data_i + assign $4\wr_detect$16[0:0]$10658 1'1 case - assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 + assign $4\wr_detect$16[0:0]$10658 $3\wr_detect$16[0:0]$10657 + end + case + assign $1\wr_detect$16[0:0]$10655 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10654 + end + attribute \src "libresoc.v:177028.3-177054.6" + process $proc$libresoc.v:177028$10659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177029.5-177029.29" + switch \initial + attribute \src "libresoc.v:177029.9-177029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10661 \dest10__data_i + case + assign $1\reg$next[3:0]$10661 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10662 \dest20__data_i + case + assign $2\reg$next[3:0]$10662 $1\reg$next[3:0]$10661 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10663 \w0__data_i + case + assign $3\reg$next[3:0]$10663 $2\reg$next[3:0]$10662 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10664 4'0000 + case + assign $4\reg$next[3:0]$10664 $3\reg$next[3:0]$10663 + end + sync always + update \reg$next $0\reg$next[3:0]$10660 + end + attribute \src "libresoc.v:177055.3-177094.6" + process $proc$libresoc.v:177055$10665 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177056.5-177056.29" + switch \initial + attribute \src "libresoc.v:177056.9-177056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10667 $5\src10__data_o$next[3:0]$10671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10668 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10668 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10669 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10669 $2\src10__data_o$next[3:0]$10668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10670 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10670 $3\src10__data_o$next[3:0]$10669 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10607 \reg + assign $5\src10__data_o$next[3:0]$10671 \reg case - assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 + assign $5\src10__data_o$next[3:0]$10671 $4\src10__data_o$next[3:0]$10670 end case - assign $1\src20__data_o$next[3:0]$10603 4'0000 + assign $1\src10__data_o$next[3:0]$10667 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10608 4'0000 + assign $6\src10__data_o$next[3:0]$10672 4'0000 case - assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 + assign $6\src10__data_o$next[3:0]$10672 $1\src10__data_o$next[3:0]$10667 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 end - attribute \src "libresoc.v:175379.3-175408.6" - process $proc$libresoc.v:175379$10609 + attribute \src "libresoc.v:177095.3-177124.6" + process $proc$libresoc.v:177095$10673 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 - attribute \src "libresoc.v:175380.5-175380.29" + assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177096.5-177096.29" switch \initial - attribute \src "libresoc.v:175380.9-175380.17" + attribute \src "libresoc.v:177096.9-177096.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 + assign $1\wr_detect$4[0:0]$10675 $4\wr_detect$4[0:0]$10678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10612 1'1 + assign $2\wr_detect$4[0:0]$10676 1'1 case - assign $2\wr_detect$4[0:0]$10612 1'0 + assign $2\wr_detect$4[0:0]$10676 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10613 1'1 + assign $3\wr_detect$4[0:0]$10677 1'1 case - assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 + assign $3\wr_detect$4[0:0]$10677 $2\wr_detect$4[0:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10614 1'1 + assign $4\wr_detect$4[0:0]$10678 1'1 case - assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 + assign $4\wr_detect$4[0:0]$10678 $3\wr_detect$4[0:0]$10677 end case - assign $1\wr_detect$4[0:0]$10611 1'0 + assign $1\wr_detect$4[0:0]$10675 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10610 + update \wr_detect$4 $0\wr_detect$4[0:0]$10674 end - attribute \src "libresoc.v:175409.3-175448.6" - process $proc$libresoc.v:175409$10615 + attribute \src "libresoc.v:177125.3-177164.6" + process $proc$libresoc.v:177125$10679 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 - attribute \src "libresoc.v:175410.5-175410.29" + assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177126.5-177126.29" switch \initial - attribute \src "libresoc.v:175410.9-175410.17" + attribute \src "libresoc.v:177126.9-177126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 + assign $1\src20__data_o$next[3:0]$10681 $5\src20__data_o$next[3:0]$10685 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10682 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10618 4'0000 + assign $2\src20__data_o$next[3:0]$10682 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10683 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 + assign $3\src20__data_o$next[3:0]$10683 $2\src20__data_o$next[3:0]$10682 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10620 \w0__data_i + assign $4\src20__data_o$next[3:0]$10684 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 + assign $4\src20__data_o$next[3:0]$10684 $3\src20__data_o$next[3:0]$10683 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10621 \reg + assign $5\src20__data_o$next[3:0]$10685 \reg case - assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 + assign $5\src20__data_o$next[3:0]$10685 $4\src20__data_o$next[3:0]$10684 end case - assign $1\src30__data_o$next[3:0]$10617 4'0000 + assign $1\src20__data_o$next[3:0]$10681 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10622 4'0000 + assign $6\src20__data_o$next[3:0]$10686 4'0000 case - assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 + assign $6\src20__data_o$next[3:0]$10686 $1\src20__data_o$next[3:0]$10681 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 end - attribute \src "libresoc.v:175449.3-175478.6" - process $proc$libresoc.v:175449$10623 + attribute \src "libresoc.v:177165.3-177194.6" + process $proc$libresoc.v:177165$10687 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 - attribute \src "libresoc.v:175450.5-175450.29" + assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:177166.5-177166.29" switch \initial - attribute \src "libresoc.v:175450.9-175450.17" + attribute \src "libresoc.v:177166.9-177166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 + assign $1\wr_detect$7[0:0]$10689 $4\wr_detect$7[0:0]$10692 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10626 1'1 + assign $2\wr_detect$7[0:0]$10690 1'1 case - assign $2\wr_detect$7[0:0]$10626 1'0 + assign $2\wr_detect$7[0:0]$10690 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10627 1'1 + assign $3\wr_detect$7[0:0]$10691 1'1 case - assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 + assign $3\wr_detect$7[0:0]$10691 $2\wr_detect$7[0:0]$10690 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10628 1'1 + assign $4\wr_detect$7[0:0]$10692 1'1 case - assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 + assign $4\wr_detect$7[0:0]$10692 $3\wr_detect$7[0:0]$10691 end case - assign $1\wr_detect$7[0:0]$10625 1'0 + assign $1\wr_detect$7[0:0]$10689 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10624 + update \wr_detect$7 $0\wr_detect$7[0:0]$10688 end - attribute \src "libresoc.v:175479.3-175518.6" - process $proc$libresoc.v:175479$10629 + attribute \src "libresoc.v:177195.3-177234.6" + process $proc$libresoc.v:177195$10693 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 - attribute \src "libresoc.v:175480.5-175480.29" + assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:177196.5-177196.29" switch \initial - attribute \src "libresoc.v:175480.9-175480.17" + attribute \src "libresoc.v:177196.9-177196.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 + assign $1\src30__data_o$next[3:0]$10695 $5\src30__data_o$next[3:0]$10699 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10696 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10632 4'0000 + assign $2\src30__data_o$next[3:0]$10696 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10697 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 + assign $3\src30__data_o$next[3:0]$10697 $2\src30__data_o$next[3:0]$10696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10634 \w0__data_i + assign $4\src30__data_o$next[3:0]$10698 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 + assign $4\src30__data_o$next[3:0]$10698 $3\src30__data_o$next[3:0]$10697 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10635 \reg + assign $5\src30__data_o$next[3:0]$10699 \reg case - assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 + assign $5\src30__data_o$next[3:0]$10699 $4\src30__data_o$next[3:0]$10698 end case - assign $1\r0__data_o$next[3:0]$10631 4'0000 + assign $1\src30__data_o$next[3:0]$10695 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10636 4'0000 + assign $6\src30__data_o$next[3:0]$10700 4'0000 case - assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 + assign $6\src30__data_o$next[3:0]$10700 $1\src30__data_o$next[3:0]$10695 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 end - attribute \src "libresoc.v:175519.3-175548.6" - process $proc$libresoc.v:175519$10637 + attribute \src "libresoc.v:177235.3-177264.6" + process $proc$libresoc.v:177235$10701 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 - attribute \src "libresoc.v:175520.5-175520.29" + assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177236.5-177236.29" switch \initial - attribute \src "libresoc.v:175520.9-175520.17" + attribute \src "libresoc.v:177236.9-177236.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 + assign $1\wr_detect$10[0:0]$10703 $4\wr_detect$10[0:0]$10706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10640 1'1 + assign $2\wr_detect$10[0:0]$10704 1'1 case - assign $2\wr_detect$10[0:0]$10640 1'0 + assign $2\wr_detect$10[0:0]$10704 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10641 1'1 + assign $3\wr_detect$10[0:0]$10705 1'1 case - assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 + assign $3\wr_detect$10[0:0]$10705 $2\wr_detect$10[0:0]$10704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10642 1'1 + assign $4\wr_detect$10[0:0]$10706 1'1 case - assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 + assign $4\wr_detect$10[0:0]$10706 $3\wr_detect$10[0:0]$10705 end case - assign $1\wr_detect$10[0:0]$10639 1'0 + assign $1\wr_detect$10[0:0]$10703 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10638 + update \wr_detect$10 $0\wr_detect$10[0:0]$10702 end - attribute \src "libresoc.v:175549.3-175588.6" - process $proc$libresoc.v:175549$10643 + attribute \src "libresoc.v:177265.3-177304.6" + process $proc$libresoc.v:177265$10707 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:175550.5-175550.29" + assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:177266.5-177266.29" switch \initial - attribute \src "libresoc.v:175550.9-175550.17" + attribute \src "libresoc.v:177266.9-177266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 + assign $1\r0__data_o$next[3:0]$10709 $5\r0__data_o$next[3:0]$10713 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10710 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10646 4'0000 + assign $2\r0__data_o$next[3:0]$10710 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10711 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 + assign $3\r0__data_o$next[3:0]$10711 $2\r0__data_o$next[3:0]$10710 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10648 \w0__data_i + assign $4\r0__data_o$next[3:0]$10712 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 + assign $4\r0__data_o$next[3:0]$10712 $3\r0__data_o$next[3:0]$10711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10649 \reg + assign $5\r0__data_o$next[3:0]$10713 \reg case - assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 + assign $5\r0__data_o$next[3:0]$10713 $4\r0__data_o$next[3:0]$10712 end case - assign $1\r20__data_o$next[3:0]$10645 4'0000 + assign $1\r0__data_o$next[3:0]$10709 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10650 4'0000 + assign $6\r0__data_o$next[3:0]$10714 4'0000 case - assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 + assign $6\r0__data_o$next[3:0]$10714 $1\r0__data_o$next[3:0]$10709 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 end - attribute \src "libresoc.v:175589.3-175618.6" - process $proc$libresoc.v:175589$10651 + attribute \src "libresoc.v:177305.3-177334.6" + process $proc$libresoc.v:177305$10715 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 - attribute \src "libresoc.v:175590.5-175590.29" + assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:177306.5-177306.29" switch \initial - attribute \src "libresoc.v:175590.9-175590.17" + attribute \src "libresoc.v:177306.9-177306.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 + assign $1\wr_detect$13[0:0]$10717 $4\wr_detect$13[0:0]$10720 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10654 1'1 + assign $2\wr_detect$13[0:0]$10718 1'1 case - assign $2\wr_detect$13[0:0]$10654 1'0 + assign $2\wr_detect$13[0:0]$10718 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10655 1'1 + assign $3\wr_detect$13[0:0]$10719 1'1 case - assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 + assign $3\wr_detect$13[0:0]$10719 $2\wr_detect$13[0:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10656 1'1 + assign $4\wr_detect$13[0:0]$10720 1'1 case - assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 + assign $4\wr_detect$13[0:0]$10720 $3\wr_detect$13[0:0]$10719 end case - assign $1\wr_detect$13[0:0]$10653 1'0 + assign $1\wr_detect$13[0:0]$10717 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10652 + update \wr_detect$13 $0\wr_detect$13[0:0]$10716 end - connect \$9 $not$libresoc.v:175225$10575_Y - connect \$12 $not$libresoc.v:175226$10576_Y - connect \$1 $not$libresoc.v:175227$10577_Y - connect \$3 $not$libresoc.v:175228$10578_Y - connect \$6 $not$libresoc.v:175229$10579_Y + connect \$9 $not$libresoc.v:176868$10623_Y + connect \$12 $not$libresoc.v:176869$10624_Y + connect \$15 $not$libresoc.v:176870$10625_Y + connect \$1 $not$libresoc.v:176871$10626_Y + connect \$3 $not$libresoc.v:176872$10627_Y + connect \$6 $not$libresoc.v:176873$10628_Y end -attribute \src "libresoc.v:175623.1-176068.10" +attribute \src "libresoc.v:177339.1-177784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:175624.7-175624.20" + attribute \src "libresoc.v:177340.7-177340.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $0\r0__data_o$next[1:0]$10716 - attribute \src "libresoc.v:175699.3-175700.37" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $0\r0__data_o$next[1:0]$10781 + attribute \src "libresoc.v:177415.3-177416.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $0\reg$next[1:0]$10732 - attribute \src "libresoc.v:175697.3-175698.25" + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $0\reg$next[1:0]$10797 + attribute \src "libresoc.v:177413.3-177414.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $0\src10__data_o$next[1:0]$10674 - attribute \src "libresoc.v:175705.3-175706.43" + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $0\src10__data_o$next[1:0]$10739 + attribute \src "libresoc.v:177421.3-177422.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $0\src20__data_o$next[1:0]$10684 - attribute \src "libresoc.v:175703.3-175704.43" + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $0\src20__data_o$next[1:0]$10749 + attribute \src "libresoc.v:177419.3-177420.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $0\src30__data_o$next[1:0]$10700 - attribute \src "libresoc.v:175701.3-175702.43" + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $0\src30__data_o$next[1:0]$10765 + attribute \src "libresoc.v:177417.3-177418.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:175999.3-176034.6" - wire $0\wr_detect$10[0:0]$10725 - attribute \src "libresoc.v:175835.3-175870.6" - wire $0\wr_detect$4[0:0]$10693 - attribute \src "libresoc.v:175917.3-175952.6" - wire $0\wr_detect$7[0:0]$10709 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177715.3-177750.6" + wire $0\wr_detect$10[0:0]$10790 + attribute \src "libresoc.v:177551.3-177586.6" + wire $0\wr_detect$4[0:0]$10758 + attribute \src "libresoc.v:177633.3-177668.6" + wire $0\wr_detect$7[0:0]$10774 + attribute \src "libresoc.v:177469.3-177504.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $1\r0__data_o$next[1:0]$10717 - attribute \src "libresoc.v:175651.13-175651.30" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $1\r0__data_o$next[1:0]$10782 + attribute \src "libresoc.v:177367.13-177367.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $1\reg$next[1:0]$10733 - attribute \src "libresoc.v:175657.13-175657.25" + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $1\reg$next[1:0]$10798 + attribute \src "libresoc.v:177373.13-177373.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $1\src10__data_o$next[1:0]$10675 - attribute \src "libresoc.v:175662.13-175662.33" + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $1\src10__data_o$next[1:0]$10740 + attribute \src "libresoc.v:177378.13-177378.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $1\src20__data_o$next[1:0]$10685 - attribute \src "libresoc.v:175669.13-175669.33" + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $1\src20__data_o$next[1:0]$10750 + attribute \src "libresoc.v:177385.13-177385.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $1\src30__data_o$next[1:0]$10701 - attribute \src "libresoc.v:175676.13-175676.33" + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $1\src30__data_o$next[1:0]$10766 + attribute \src "libresoc.v:177392.13-177392.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:175999.3-176034.6" - wire $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:175835.3-175870.6" - wire $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:175917.3-175952.6" - wire $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177715.3-177750.6" + wire $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177551.3-177586.6" + wire $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177633.3-177668.6" + wire $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177469.3-177504.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $2\r0__data_o$next[1:0]$10718 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $2\reg$next[1:0]$10734 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $2\src10__data_o$next[1:0]$10676 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $2\src20__data_o$next[1:0]$10686 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $2\src30__data_o$next[1:0]$10702 - attribute \src "libresoc.v:175999.3-176034.6" - wire $2\wr_detect$10[0:0]$10727 - attribute \src "libresoc.v:175835.3-175870.6" - wire $2\wr_detect$4[0:0]$10695 - attribute \src "libresoc.v:175917.3-175952.6" - wire $2\wr_detect$7[0:0]$10711 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $2\r0__data_o$next[1:0]$10783 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $2\reg$next[1:0]$10799 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $2\src10__data_o$next[1:0]$10741 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $2\src20__data_o$next[1:0]$10751 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $2\src30__data_o$next[1:0]$10767 + attribute \src "libresoc.v:177715.3-177750.6" + wire $2\wr_detect$10[0:0]$10792 + attribute \src "libresoc.v:177551.3-177586.6" + wire $2\wr_detect$4[0:0]$10760 + attribute \src "libresoc.v:177633.3-177668.6" + wire $2\wr_detect$7[0:0]$10776 + attribute \src "libresoc.v:177469.3-177504.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $3\r0__data_o$next[1:0]$10719 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $3\reg$next[1:0]$10735 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $3\src10__data_o$next[1:0]$10677 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $3\src20__data_o$next[1:0]$10687 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $3\src30__data_o$next[1:0]$10703 - attribute \src "libresoc.v:175999.3-176034.6" - wire $3\wr_detect$10[0:0]$10728 - attribute \src "libresoc.v:175835.3-175870.6" - wire $3\wr_detect$4[0:0]$10696 - attribute \src "libresoc.v:175917.3-175952.6" - wire $3\wr_detect$7[0:0]$10712 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $3\r0__data_o$next[1:0]$10784 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $3\reg$next[1:0]$10800 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $3\src10__data_o$next[1:0]$10742 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $3\src20__data_o$next[1:0]$10752 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $3\src30__data_o$next[1:0]$10768 + attribute \src "libresoc.v:177715.3-177750.6" + wire $3\wr_detect$10[0:0]$10793 + attribute \src "libresoc.v:177551.3-177586.6" + wire $3\wr_detect$4[0:0]$10761 + attribute \src "libresoc.v:177633.3-177668.6" + wire $3\wr_detect$7[0:0]$10777 + attribute \src "libresoc.v:177469.3-177504.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $4\r0__data_o$next[1:0]$10720 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $4\reg$next[1:0]$10736 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $4\src10__data_o$next[1:0]$10678 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $4\src20__data_o$next[1:0]$10688 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $4\src30__data_o$next[1:0]$10704 - attribute \src "libresoc.v:175999.3-176034.6" - wire $4\wr_detect$10[0:0]$10729 - attribute \src "libresoc.v:175835.3-175870.6" - wire $4\wr_detect$4[0:0]$10697 - attribute \src "libresoc.v:175917.3-175952.6" - wire $4\wr_detect$7[0:0]$10713 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $4\r0__data_o$next[1:0]$10785 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $4\reg$next[1:0]$10801 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $4\src10__data_o$next[1:0]$10743 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $4\src20__data_o$next[1:0]$10753 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $4\src30__data_o$next[1:0]$10769 + attribute \src "libresoc.v:177715.3-177750.6" + wire $4\wr_detect$10[0:0]$10794 + attribute \src "libresoc.v:177551.3-177586.6" + wire $4\wr_detect$4[0:0]$10762 + attribute \src "libresoc.v:177633.3-177668.6" + wire $4\wr_detect$7[0:0]$10778 + attribute \src "libresoc.v:177469.3-177504.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $5\r0__data_o$next[1:0]$10721 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $5\src10__data_o$next[1:0]$10679 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $5\src20__data_o$next[1:0]$10689 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $5\src30__data_o$next[1:0]$10705 - attribute \src "libresoc.v:175999.3-176034.6" - wire $5\wr_detect$10[0:0]$10730 - attribute \src "libresoc.v:175835.3-175870.6" - wire $5\wr_detect$4[0:0]$10698 - attribute \src "libresoc.v:175917.3-175952.6" - wire $5\wr_detect$7[0:0]$10714 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $5\r0__data_o$next[1:0]$10786 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $5\src10__data_o$next[1:0]$10744 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $5\src20__data_o$next[1:0]$10754 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $5\src30__data_o$next[1:0]$10770 + attribute \src "libresoc.v:177715.3-177750.6" + wire $5\wr_detect$10[0:0]$10795 + attribute \src "libresoc.v:177551.3-177586.6" + wire $5\wr_detect$4[0:0]$10763 + attribute \src "libresoc.v:177633.3-177668.6" + wire $5\wr_detect$7[0:0]$10779 + attribute \src "libresoc.v:177469.3-177504.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $6\r0__data_o$next[1:0]$10722 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $6\src10__data_o$next[1:0]$10680 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $6\src20__data_o$next[1:0]$10690 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $6\src30__data_o$next[1:0]$10706 - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:175693.17-175693.104" - wire $not$libresoc.v:175693$10664_Y - attribute \src "libresoc.v:175694.17-175694.100" - wire $not$libresoc.v:175694$10665_Y - attribute \src "libresoc.v:175695.17-175695.103" - wire $not$libresoc.v:175695$10666_Y - attribute \src "libresoc.v:175696.17-175696.103" - wire $not$libresoc.v:175696$10667_Y + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $6\r0__data_o$next[1:0]$10787 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $6\src10__data_o$next[1:0]$10745 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $6\src20__data_o$next[1:0]$10755 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $6\src30__data_o$next[1:0]$10771 + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177409.17-177409.104" + wire $not$libresoc.v:177409$10729_Y + attribute \src "libresoc.v:177410.17-177410.100" + wire $not$libresoc.v:177410$10730_Y + attribute \src "libresoc.v:177411.17-177411.103" + wire $not$libresoc.v:177411$10731_Y + attribute \src "libresoc.v:177412.17-177412.103" + wire $not$libresoc.v:177412$10732_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -361559,9 +364245,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -361575,7 +364261,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:175624.7-175624.15" + attribute \src "libresoc.v:177340.7-177340.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -361618,129 +364304,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175693$10664 + cell $not $not$libresoc.v:177409$10729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:175693$10664_Y + connect \Y $not$libresoc.v:177409$10729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175694$10665 + cell $not $not$libresoc.v:177410$10730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175694$10665_Y + connect \Y $not$libresoc.v:177410$10730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175695$10666 + cell $not $not$libresoc.v:177411$10731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175695$10666_Y + connect \Y $not$libresoc.v:177411$10731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175696$10667 + cell $not $not$libresoc.v:177412$10732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175696$10667_Y + connect \Y $not$libresoc.v:177412$10732_Y end - attribute \src "libresoc.v:175624.7-175624.20" - process $proc$libresoc.v:175624$10738 + attribute \src "libresoc.v:177340.7-177340.20" + process $proc$libresoc.v:177340$10803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175651.13-175651.30" - process $proc$libresoc.v:175651$10739 + attribute \src "libresoc.v:177367.13-177367.30" + process $proc$libresoc.v:177367$10804 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:175657.13-175657.25" - process $proc$libresoc.v:175657$10740 + attribute \src "libresoc.v:177373.13-177373.25" + process $proc$libresoc.v:177373$10805 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:175662.13-175662.33" - process $proc$libresoc.v:175662$10741 + attribute \src "libresoc.v:177378.13-177378.33" + process $proc$libresoc.v:177378$10806 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:175669.13-175669.33" - process $proc$libresoc.v:175669$10742 + attribute \src "libresoc.v:177385.13-177385.33" + process $proc$libresoc.v:177385$10807 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:175676.13-175676.33" - process $proc$libresoc.v:175676$10743 + attribute \src "libresoc.v:177392.13-177392.33" + process $proc$libresoc.v:177392$10808 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:175697.3-175698.25" - process $proc$libresoc.v:175697$10668 + attribute \src "libresoc.v:177413.3-177414.25" + process $proc$libresoc.v:177413$10733 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:175699.3-175700.37" - process $proc$libresoc.v:175699$10669 + attribute \src "libresoc.v:177415.3-177416.37" + process $proc$libresoc.v:177415$10734 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:175701.3-175702.43" - process $proc$libresoc.v:175701$10670 + attribute \src "libresoc.v:177417.3-177418.43" + process $proc$libresoc.v:177417$10735 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:175703.3-175704.43" - process $proc$libresoc.v:175703$10671 + attribute \src "libresoc.v:177419.3-177420.43" + process $proc$libresoc.v:177419$10736 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:175705.3-175706.43" - process $proc$libresoc.v:175705$10672 + attribute \src "libresoc.v:177421.3-177422.43" + process $proc$libresoc.v:177421$10737 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:175707.3-175752.6" - process $proc$libresoc.v:175707$10673 + attribute \src "libresoc.v:177423.3-177468.6" + process $proc$libresoc.v:177423$10738 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:175708.5-175708.29" + assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177424.5-177424.29" switch \initial - attribute \src "libresoc.v:175708.9-175708.17" + attribute \src "libresoc.v:177424.9-177424.17" case 1'1 case end @@ -361753,75 +364439,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 + assign $1\src10__data_o$next[1:0]$10740 $6\src10__data_o$next[1:0]$10745 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10741 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10676 2'00 + assign $2\src10__data_o$next[1:0]$10741 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10742 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 + assign $3\src10__data_o$next[1:0]$10742 $2\src10__data_o$next[1:0]$10741 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10743 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 + assign $4\src10__data_o$next[1:0]$10743 $3\src10__data_o$next[1:0]$10742 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10679 \w0__data_i + assign $5\src10__data_o$next[1:0]$10744 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 + assign $5\src10__data_o$next[1:0]$10744 $4\src10__data_o$next[1:0]$10743 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10680 \reg + assign $6\src10__data_o$next[1:0]$10745 \reg case - assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 + assign $6\src10__data_o$next[1:0]$10745 $5\src10__data_o$next[1:0]$10744 end case - assign $1\src10__data_o$next[1:0]$10675 2'00 + assign $1\src10__data_o$next[1:0]$10740 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10681 2'00 + assign $7\src10__data_o$next[1:0]$10746 2'00 case - assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 + assign $7\src10__data_o$next[1:0]$10746 $1\src10__data_o$next[1:0]$10740 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 end - attribute \src "libresoc.v:175753.3-175788.6" - process $proc$libresoc.v:175753$10682 + attribute \src "libresoc.v:177469.3-177504.6" + process $proc$libresoc.v:177469$10747 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175754.5-175754.29" + attribute \src "libresoc.v:177470.5-177470.29" switch \initial - attribute \src "libresoc.v:175754.9-175754.17" + attribute \src "libresoc.v:177470.9-177470.17" case 1'1 case end @@ -361877,15 +364563,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175789.3-175834.6" - process $proc$libresoc.v:175789$10683 + attribute \src "libresoc.v:177505.3-177550.6" + process $proc$libresoc.v:177505$10748 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:175790.5-175790.29" + assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177506.5-177506.29" switch \initial - attribute \src "libresoc.v:175790.9-175790.17" + attribute \src "libresoc.v:177506.9-177506.17" case 1'1 case end @@ -361898,75 +364584,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 + assign $1\src20__data_o$next[1:0]$10750 $6\src20__data_o$next[1:0]$10755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10751 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10686 2'00 + assign $2\src20__data_o$next[1:0]$10751 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10752 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 + assign $3\src20__data_o$next[1:0]$10752 $2\src20__data_o$next[1:0]$10751 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10753 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 + assign $4\src20__data_o$next[1:0]$10753 $3\src20__data_o$next[1:0]$10752 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10689 \w0__data_i + assign $5\src20__data_o$next[1:0]$10754 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 + assign $5\src20__data_o$next[1:0]$10754 $4\src20__data_o$next[1:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10690 \reg + assign $6\src20__data_o$next[1:0]$10755 \reg case - assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 + assign $6\src20__data_o$next[1:0]$10755 $5\src20__data_o$next[1:0]$10754 end case - assign $1\src20__data_o$next[1:0]$10685 2'00 + assign $1\src20__data_o$next[1:0]$10750 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10691 2'00 + assign $7\src20__data_o$next[1:0]$10756 2'00 case - assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 + assign $7\src20__data_o$next[1:0]$10756 $1\src20__data_o$next[1:0]$10750 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 end - attribute \src "libresoc.v:175835.3-175870.6" - process $proc$libresoc.v:175835$10692 + attribute \src "libresoc.v:177551.3-177586.6" + process $proc$libresoc.v:177551$10757 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:175836.5-175836.29" + assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177552.5-177552.29" switch \initial - attribute \src "libresoc.v:175836.9-175836.17" + attribute \src "libresoc.v:177552.9-177552.17" case 1'1 case end @@ -361979,58 +364665,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 + assign $1\wr_detect$4[0:0]$10759 $5\wr_detect$4[0:0]$10763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10695 1'1 + assign $2\wr_detect$4[0:0]$10760 1'1 case - assign $2\wr_detect$4[0:0]$10695 1'0 + assign $2\wr_detect$4[0:0]$10760 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10696 1'1 + assign $3\wr_detect$4[0:0]$10761 1'1 case - assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 + assign $3\wr_detect$4[0:0]$10761 $2\wr_detect$4[0:0]$10760 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10697 1'1 + assign $4\wr_detect$4[0:0]$10762 1'1 case - assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 + assign $4\wr_detect$4[0:0]$10762 $3\wr_detect$4[0:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10698 1'1 + assign $5\wr_detect$4[0:0]$10763 1'1 case - assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 + assign $5\wr_detect$4[0:0]$10763 $4\wr_detect$4[0:0]$10762 end case - assign $1\wr_detect$4[0:0]$10694 1'0 + assign $1\wr_detect$4[0:0]$10759 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10693 + update \wr_detect$4 $0\wr_detect$4[0:0]$10758 end - attribute \src "libresoc.v:175871.3-175916.6" - process $proc$libresoc.v:175871$10699 + attribute \src "libresoc.v:177587.3-177632.6" + process $proc$libresoc.v:177587$10764 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:175872.5-175872.29" + assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177588.5-177588.29" switch \initial - attribute \src "libresoc.v:175872.9-175872.17" + attribute \src "libresoc.v:177588.9-177588.17" case 1'1 case end @@ -362043,75 +364729,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 + assign $1\src30__data_o$next[1:0]$10766 $6\src30__data_o$next[1:0]$10771 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10767 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10702 2'00 + assign $2\src30__data_o$next[1:0]$10767 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10768 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 + assign $3\src30__data_o$next[1:0]$10768 $2\src30__data_o$next[1:0]$10767 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10769 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 + assign $4\src30__data_o$next[1:0]$10769 $3\src30__data_o$next[1:0]$10768 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10705 \w0__data_i + assign $5\src30__data_o$next[1:0]$10770 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 + assign $5\src30__data_o$next[1:0]$10770 $4\src30__data_o$next[1:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10706 \reg + assign $6\src30__data_o$next[1:0]$10771 \reg case - assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 + assign $6\src30__data_o$next[1:0]$10771 $5\src30__data_o$next[1:0]$10770 end case - assign $1\src30__data_o$next[1:0]$10701 2'00 + assign $1\src30__data_o$next[1:0]$10766 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10707 2'00 + assign $7\src30__data_o$next[1:0]$10772 2'00 case - assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 + assign $7\src30__data_o$next[1:0]$10772 $1\src30__data_o$next[1:0]$10766 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 end - attribute \src "libresoc.v:175917.3-175952.6" - process $proc$libresoc.v:175917$10708 + attribute \src "libresoc.v:177633.3-177668.6" + process $proc$libresoc.v:177633$10773 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:175918.5-175918.29" + assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177634.5-177634.29" switch \initial - attribute \src "libresoc.v:175918.9-175918.17" + attribute \src "libresoc.v:177634.9-177634.17" case 1'1 case end @@ -362124,58 +364810,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 + assign $1\wr_detect$7[0:0]$10775 $5\wr_detect$7[0:0]$10779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10711 1'1 + assign $2\wr_detect$7[0:0]$10776 1'1 case - assign $2\wr_detect$7[0:0]$10711 1'0 + assign $2\wr_detect$7[0:0]$10776 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10712 1'1 + assign $3\wr_detect$7[0:0]$10777 1'1 case - assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 + assign $3\wr_detect$7[0:0]$10777 $2\wr_detect$7[0:0]$10776 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10713 1'1 + assign $4\wr_detect$7[0:0]$10778 1'1 case - assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 + assign $4\wr_detect$7[0:0]$10778 $3\wr_detect$7[0:0]$10777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10714 1'1 + assign $5\wr_detect$7[0:0]$10779 1'1 case - assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 + assign $5\wr_detect$7[0:0]$10779 $4\wr_detect$7[0:0]$10778 end case - assign $1\wr_detect$7[0:0]$10710 1'0 + assign $1\wr_detect$7[0:0]$10775 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10709 + update \wr_detect$7 $0\wr_detect$7[0:0]$10774 end - attribute \src "libresoc.v:175953.3-175998.6" - process $proc$libresoc.v:175953$10715 + attribute \src "libresoc.v:177669.3-177714.6" + process $proc$libresoc.v:177669$10780 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:175954.5-175954.29" + assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177670.5-177670.29" switch \initial - attribute \src "libresoc.v:175954.9-175954.17" + attribute \src "libresoc.v:177670.9-177670.17" case 1'1 case end @@ -362188,75 +364874,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 + assign $1\r0__data_o$next[1:0]$10782 $6\r0__data_o$next[1:0]$10787 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10783 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10718 2'00 + assign $2\r0__data_o$next[1:0]$10783 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10784 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 + assign $3\r0__data_o$next[1:0]$10784 $2\r0__data_o$next[1:0]$10783 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10785 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 + assign $4\r0__data_o$next[1:0]$10785 $3\r0__data_o$next[1:0]$10784 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10721 \w0__data_i + assign $5\r0__data_o$next[1:0]$10786 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 + assign $5\r0__data_o$next[1:0]$10786 $4\r0__data_o$next[1:0]$10785 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10722 \reg + assign $6\r0__data_o$next[1:0]$10787 \reg case - assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 + assign $6\r0__data_o$next[1:0]$10787 $5\r0__data_o$next[1:0]$10786 end case - assign $1\r0__data_o$next[1:0]$10717 2'00 + assign $1\r0__data_o$next[1:0]$10782 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10723 2'00 + assign $7\r0__data_o$next[1:0]$10788 2'00 case - assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 + assign $7\r0__data_o$next[1:0]$10788 $1\r0__data_o$next[1:0]$10782 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 end - attribute \src "libresoc.v:175999.3-176034.6" - process $proc$libresoc.v:175999$10724 + attribute \src "libresoc.v:177715.3-177750.6" + process $proc$libresoc.v:177715$10789 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:176000.5-176000.29" + assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177716.5-177716.29" switch \initial - attribute \src "libresoc.v:176000.9-176000.17" + attribute \src "libresoc.v:177716.9-177716.17" case 1'1 case end @@ -362269,61 +364955,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 + assign $1\wr_detect$10[0:0]$10791 $5\wr_detect$10[0:0]$10795 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10727 1'1 + assign $2\wr_detect$10[0:0]$10792 1'1 case - assign $2\wr_detect$10[0:0]$10727 1'0 + assign $2\wr_detect$10[0:0]$10792 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10728 1'1 + assign $3\wr_detect$10[0:0]$10793 1'1 case - assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 + assign $3\wr_detect$10[0:0]$10793 $2\wr_detect$10[0:0]$10792 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10729 1'1 + assign $4\wr_detect$10[0:0]$10794 1'1 case - assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 + assign $4\wr_detect$10[0:0]$10794 $3\wr_detect$10[0:0]$10793 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10730 1'1 + assign $5\wr_detect$10[0:0]$10795 1'1 case - assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 + assign $5\wr_detect$10[0:0]$10795 $4\wr_detect$10[0:0]$10794 end case - assign $1\wr_detect$10[0:0]$10726 1'0 + assign $1\wr_detect$10[0:0]$10791 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10725 + update \wr_detect$10 $0\wr_detect$10[0:0]$10790 end - attribute \src "libresoc.v:176035.3-176067.6" - process $proc$libresoc.v:176035$10731 + attribute \src "libresoc.v:177751.3-177783.6" + process $proc$libresoc.v:177751$10796 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:176036.5-176036.29" + assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177752.5-177752.29" switch \initial - attribute \src "libresoc.v:176036.9-176036.17" + attribute \src "libresoc.v:177752.9-177752.17" case 1'1 case end @@ -362332,179 +365018,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10733 \dest10__data_i + assign $1\reg$next[1:0]$10798 \dest10__data_i case - assign $1\reg$next[1:0]$10733 \reg + assign $1\reg$next[1:0]$10798 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10734 \dest20__data_i + assign $2\reg$next[1:0]$10799 \dest20__data_i case - assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 + assign $2\reg$next[1:0]$10799 $1\reg$next[1:0]$10798 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10735 \dest30__data_i + assign $3\reg$next[1:0]$10800 \dest30__data_i case - assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 + assign $3\reg$next[1:0]$10800 $2\reg$next[1:0]$10799 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10736 \w0__data_i + assign $4\reg$next[1:0]$10801 \w0__data_i case - assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 + assign $4\reg$next[1:0]$10801 $3\reg$next[1:0]$10800 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10737 2'00 + assign $5\reg$next[1:0]$10802 2'00 case - assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 + assign $5\reg$next[1:0]$10802 $4\reg$next[1:0]$10801 end sync always - update \reg$next $0\reg$next[1:0]$10732 + update \reg$next $0\reg$next[1:0]$10797 end - connect \$9 $not$libresoc.v:175693$10664_Y - connect \$1 $not$libresoc.v:175694$10665_Y - connect \$3 $not$libresoc.v:175695$10666_Y - connect \$6 $not$libresoc.v:175696$10667_Y + connect \$9 $not$libresoc.v:177409$10729_Y + connect \$1 $not$libresoc.v:177410$10730_Y + connect \$3 $not$libresoc.v:177411$10731_Y + connect \$6 $not$libresoc.v:177412$10732_Y end -attribute \src "libresoc.v:176072.1-176421.10" +attribute \src "libresoc.v:177788.1-178137.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $0\cia0__data_o$next[63:0]$10752 - attribute \src "libresoc.v:176140.3-176141.41" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $0\cia0__data_o$next[63:0]$10817 + attribute \src "libresoc.v:177856.3-177857.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:176073.7-176073.20" + attribute \src "libresoc.v:177789.7-177789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $0\msr0__data_o$next[63:0]$10762 - attribute \src "libresoc.v:176138.3-176139.41" + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $0\msr0__data_o$next[63:0]$10827 + attribute \src "libresoc.v:177854.3-177855.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $0\reg$next[63:0]$10794 - attribute \src "libresoc.v:176134.3-176135.25" + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $0\reg$next[63:0]$10859 + attribute \src "libresoc.v:177850.3-177851.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $0\sv0__data_o$next[63:0]$10778 - attribute \src "libresoc.v:176136.3-176137.39" + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $0\sv0__data_o$next[63:0]$10843 + attribute \src "libresoc.v:177852.3-177853.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:176270.3-176305.6" - wire $0\wr_detect$4[0:0]$10771 - attribute \src "libresoc.v:176352.3-176387.6" - wire $0\wr_detect$7[0:0]$10787 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177986.3-178021.6" + wire $0\wr_detect$4[0:0]$10836 + attribute \src "libresoc.v:178068.3-178103.6" + wire $0\wr_detect$7[0:0]$10852 + attribute \src "libresoc.v:177904.3-177939.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $1\cia0__data_o$next[63:0]$10753 - attribute \src "libresoc.v:176082.14-176082.49" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $1\cia0__data_o$next[63:0]$10818 + attribute \src "libresoc.v:177798.14-177798.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $1\msr0__data_o$next[63:0]$10763 - attribute \src "libresoc.v:176099.14-176099.49" + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $1\msr0__data_o$next[63:0]$10828 + attribute \src "libresoc.v:177815.14-177815.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $1\reg$next[63:0]$10795 - attribute \src "libresoc.v:176111.14-176111.42" + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $1\reg$next[63:0]$10860 + attribute \src "libresoc.v:177827.14-177827.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $1\sv0__data_o$next[63:0]$10779 - attribute \src "libresoc.v:176118.14-176118.48" + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $1\sv0__data_o$next[63:0]$10844 + attribute \src "libresoc.v:177834.14-177834.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:176270.3-176305.6" - wire $1\wr_detect$4[0:0]$10772 - attribute \src "libresoc.v:176352.3-176387.6" - wire $1\wr_detect$7[0:0]$10788 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177986.3-178021.6" + wire $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:178068.3-178103.6" + wire $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:177904.3-177939.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $2\cia0__data_o$next[63:0]$10754 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $2\msr0__data_o$next[63:0]$10764 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $2\reg$next[63:0]$10796 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $2\sv0__data_o$next[63:0]$10780 - attribute \src "libresoc.v:176270.3-176305.6" - wire $2\wr_detect$4[0:0]$10773 - attribute \src "libresoc.v:176352.3-176387.6" - wire $2\wr_detect$7[0:0]$10789 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $2\cia0__data_o$next[63:0]$10819 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $2\msr0__data_o$next[63:0]$10829 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $2\reg$next[63:0]$10861 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $2\sv0__data_o$next[63:0]$10845 + attribute \src "libresoc.v:177986.3-178021.6" + wire $2\wr_detect$4[0:0]$10838 + attribute \src "libresoc.v:178068.3-178103.6" + wire $2\wr_detect$7[0:0]$10854 + attribute \src "libresoc.v:177904.3-177939.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $3\cia0__data_o$next[63:0]$10755 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $3\msr0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $3\reg$next[63:0]$10797 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $3\sv0__data_o$next[63:0]$10781 - attribute \src "libresoc.v:176270.3-176305.6" - wire $3\wr_detect$4[0:0]$10774 - attribute \src "libresoc.v:176352.3-176387.6" - wire $3\wr_detect$7[0:0]$10790 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $3\cia0__data_o$next[63:0]$10820 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $3\msr0__data_o$next[63:0]$10830 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $3\reg$next[63:0]$10862 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $3\sv0__data_o$next[63:0]$10846 + attribute \src "libresoc.v:177986.3-178021.6" + wire $3\wr_detect$4[0:0]$10839 + attribute \src "libresoc.v:178068.3-178103.6" + wire $3\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:177904.3-177939.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $4\cia0__data_o$next[63:0]$10756 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $4\msr0__data_o$next[63:0]$10766 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $4\reg$next[63:0]$10798 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $4\sv0__data_o$next[63:0]$10782 - attribute \src "libresoc.v:176270.3-176305.6" - wire $4\wr_detect$4[0:0]$10775 - attribute \src "libresoc.v:176352.3-176387.6" - wire $4\wr_detect$7[0:0]$10791 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $4\cia0__data_o$next[63:0]$10821 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $4\msr0__data_o$next[63:0]$10831 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $4\reg$next[63:0]$10863 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $4\sv0__data_o$next[63:0]$10847 + attribute \src "libresoc.v:177986.3-178021.6" + wire $4\wr_detect$4[0:0]$10840 + attribute \src "libresoc.v:178068.3-178103.6" + wire $4\wr_detect$7[0:0]$10856 + attribute \src "libresoc.v:177904.3-177939.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $5\cia0__data_o$next[63:0]$10757 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $5\msr0__data_o$next[63:0]$10767 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $5\reg$next[63:0]$10799 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $5\sv0__data_o$next[63:0]$10783 - attribute \src "libresoc.v:176270.3-176305.6" - wire $5\wr_detect$4[0:0]$10776 - attribute \src "libresoc.v:176352.3-176387.6" - wire $5\wr_detect$7[0:0]$10792 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $5\cia0__data_o$next[63:0]$10822 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $5\msr0__data_o$next[63:0]$10832 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $5\sv0__data_o$next[63:0]$10848 + attribute \src "libresoc.v:177986.3-178021.6" + wire $5\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:178068.3-178103.6" + wire $5\wr_detect$7[0:0]$10857 + attribute \src "libresoc.v:177904.3-177939.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $6\cia0__data_o$next[63:0]$10758 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $6\msr0__data_o$next[63:0]$10768 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $6\sv0__data_o$next[63:0]$10784 - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $7\cia0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $7\msr0__data_o$next[63:0]$10769 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $7\sv0__data_o$next[63:0]$10785 - attribute \src "libresoc.v:176131.17-176131.100" - wire $not$libresoc.v:176131$10744_Y - attribute \src "libresoc.v:176132.17-176132.103" - wire $not$libresoc.v:176132$10745_Y - attribute \src "libresoc.v:176133.17-176133.103" - wire $not$libresoc.v:176133$10746_Y + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $6\cia0__data_o$next[63:0]$10823 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $6\msr0__data_o$next[63:0]$10833 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $6\sv0__data_o$next[63:0]$10849 + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:177847.17-177847.100" + wire $not$libresoc.v:177847$10809_Y + attribute \src "libresoc.v:177848.17-177848.103" + wire $not$libresoc.v:177848$10810_Y + attribute \src "libresoc.v:177849.17-177849.103" + wire $not$libresoc.v:177849$10811_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -362517,15 +365203,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:176073.7-176073.15" + attribute \src "libresoc.v:177789.7-177789.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -362562,106 +365248,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176131$10744 + cell $not $not$libresoc.v:177847$10809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176131$10744_Y + connect \Y $not$libresoc.v:177847$10809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176132$10745 + cell $not $not$libresoc.v:177848$10810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176132$10745_Y + connect \Y $not$libresoc.v:177848$10810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176133$10746 + cell $not $not$libresoc.v:177849$10811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176133$10746_Y + connect \Y $not$libresoc.v:177849$10811_Y end - attribute \src "libresoc.v:176073.7-176073.20" - process $proc$libresoc.v:176073$10800 + attribute \src "libresoc.v:177789.7-177789.20" + process $proc$libresoc.v:177789$10865 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176082.14-176082.49" - process $proc$libresoc.v:176082$10801 + attribute \src "libresoc.v:177798.14-177798.49" + process $proc$libresoc.v:177798$10866 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:176099.14-176099.49" - process $proc$libresoc.v:176099$10802 + attribute \src "libresoc.v:177815.14-177815.49" + process $proc$libresoc.v:177815$10867 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:176111.14-176111.42" - process $proc$libresoc.v:176111$10803 + attribute \src "libresoc.v:177827.14-177827.42" + process $proc$libresoc.v:177827$10868 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:176118.14-176118.48" - process $proc$libresoc.v:176118$10804 + attribute \src "libresoc.v:177834.14-177834.48" + process $proc$libresoc.v:177834$10869 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:176134.3-176135.25" - process $proc$libresoc.v:176134$10747 + attribute \src "libresoc.v:177850.3-177851.25" + process $proc$libresoc.v:177850$10812 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:176136.3-176137.39" - process $proc$libresoc.v:176136$10748 + attribute \src "libresoc.v:177852.3-177853.39" + process $proc$libresoc.v:177852$10813 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:176138.3-176139.41" - process $proc$libresoc.v:176138$10749 + attribute \src "libresoc.v:177854.3-177855.41" + process $proc$libresoc.v:177854$10814 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:176140.3-176141.41" - process $proc$libresoc.v:176140$10750 + attribute \src "libresoc.v:177856.3-177857.41" + process $proc$libresoc.v:177856$10815 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:176142.3-176187.6" - process $proc$libresoc.v:176142$10751 + attribute \src "libresoc.v:177858.3-177903.6" + process $proc$libresoc.v:177858$10816 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10752 $7\cia0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:176143.5-176143.29" + assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177859.5-177859.29" switch \initial - attribute \src "libresoc.v:176143.9-176143.17" + attribute \src "libresoc.v:177859.9-177859.17" case 1'1 case end @@ -362674,75 +365360,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10753 $6\cia0__data_o$next[63:0]$10758 + assign $1\cia0__data_o$next[63:0]$10818 $6\cia0__data_o$next[63:0]$10823 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10754 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10819 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10819 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10755 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10820 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10755 $2\cia0__data_o$next[63:0]$10754 + assign $3\cia0__data_o$next[63:0]$10820 $2\cia0__data_o$next[63:0]$10819 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10756 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10821 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10756 $3\cia0__data_o$next[63:0]$10755 + assign $4\cia0__data_o$next[63:0]$10821 $3\cia0__data_o$next[63:0]$10820 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10757 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10822 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10757 $4\cia0__data_o$next[63:0]$10756 + assign $5\cia0__data_o$next[63:0]$10822 $4\cia0__data_o$next[63:0]$10821 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10758 \reg + assign $6\cia0__data_o$next[63:0]$10823 \reg case - assign $6\cia0__data_o$next[63:0]$10758 $5\cia0__data_o$next[63:0]$10757 + assign $6\cia0__data_o$next[63:0]$10823 $5\cia0__data_o$next[63:0]$10822 end case - assign $1\cia0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10824 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10759 $1\cia0__data_o$next[63:0]$10753 + assign $7\cia0__data_o$next[63:0]$10824 $1\cia0__data_o$next[63:0]$10818 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10752 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 end - attribute \src "libresoc.v:176188.3-176223.6" - process $proc$libresoc.v:176188$10760 + attribute \src "libresoc.v:177904.3-177939.6" + process $proc$libresoc.v:177904$10825 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176189.5-176189.29" + attribute \src "libresoc.v:177905.5-177905.29" switch \initial - attribute \src "libresoc.v:176189.9-176189.17" + attribute \src "libresoc.v:177905.9-177905.17" case 1'1 case end @@ -362798,15 +365484,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176224.3-176269.6" - process $proc$libresoc.v:176224$10761 + attribute \src "libresoc.v:177940.3-177985.6" + process $proc$libresoc.v:177940$10826 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10762 $7\msr0__data_o$next[63:0]$10769 - attribute \src "libresoc.v:176225.5-176225.29" + assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:177941.5-177941.29" switch \initial - attribute \src "libresoc.v:176225.9-176225.17" + attribute \src "libresoc.v:177941.9-177941.17" case 1'1 case end @@ -362819,75 +365505,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10763 $6\msr0__data_o$next[63:0]$10768 + assign $1\msr0__data_o$next[63:0]$10828 $6\msr0__data_o$next[63:0]$10833 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10764 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10829 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10764 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10765 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10830 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10765 $2\msr0__data_o$next[63:0]$10764 + assign $3\msr0__data_o$next[63:0]$10830 $2\msr0__data_o$next[63:0]$10829 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10766 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10831 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10766 $3\msr0__data_o$next[63:0]$10765 + assign $4\msr0__data_o$next[63:0]$10831 $3\msr0__data_o$next[63:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10767 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10832 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10767 $4\msr0__data_o$next[63:0]$10766 + assign $5\msr0__data_o$next[63:0]$10832 $4\msr0__data_o$next[63:0]$10831 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10768 \reg + assign $6\msr0__data_o$next[63:0]$10833 \reg case - assign $6\msr0__data_o$next[63:0]$10768 $5\msr0__data_o$next[63:0]$10767 + assign $6\msr0__data_o$next[63:0]$10833 $5\msr0__data_o$next[63:0]$10832 end case - assign $1\msr0__data_o$next[63:0]$10763 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10769 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10769 $1\msr0__data_o$next[63:0]$10763 + assign $7\msr0__data_o$next[63:0]$10834 $1\msr0__data_o$next[63:0]$10828 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10762 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 end - attribute \src "libresoc.v:176270.3-176305.6" - process $proc$libresoc.v:176270$10770 + attribute \src "libresoc.v:177986.3-178021.6" + process $proc$libresoc.v:177986$10835 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10771 $1\wr_detect$4[0:0]$10772 - attribute \src "libresoc.v:176271.5-176271.29" + assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:177987.5-177987.29" switch \initial - attribute \src "libresoc.v:176271.9-176271.17" + attribute \src "libresoc.v:177987.9-177987.17" case 1'1 case end @@ -362900,58 +365586,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10772 $5\wr_detect$4[0:0]$10776 + assign $1\wr_detect$4[0:0]$10837 $5\wr_detect$4[0:0]$10841 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10773 1'1 + assign $2\wr_detect$4[0:0]$10838 1'1 case - assign $2\wr_detect$4[0:0]$10773 1'0 + assign $2\wr_detect$4[0:0]$10838 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10774 1'1 + assign $3\wr_detect$4[0:0]$10839 1'1 case - assign $3\wr_detect$4[0:0]$10774 $2\wr_detect$4[0:0]$10773 + assign $3\wr_detect$4[0:0]$10839 $2\wr_detect$4[0:0]$10838 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10775 1'1 + assign $4\wr_detect$4[0:0]$10840 1'1 case - assign $4\wr_detect$4[0:0]$10775 $3\wr_detect$4[0:0]$10774 + assign $4\wr_detect$4[0:0]$10840 $3\wr_detect$4[0:0]$10839 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10776 1'1 + assign $5\wr_detect$4[0:0]$10841 1'1 case - assign $5\wr_detect$4[0:0]$10776 $4\wr_detect$4[0:0]$10775 + assign $5\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10840 end case - assign $1\wr_detect$4[0:0]$10772 1'0 + assign $1\wr_detect$4[0:0]$10837 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10771 + update \wr_detect$4 $0\wr_detect$4[0:0]$10836 end - attribute \src "libresoc.v:176306.3-176351.6" - process $proc$libresoc.v:176306$10777 + attribute \src "libresoc.v:178022.3-178067.6" + process $proc$libresoc.v:178022$10842 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10778 $7\sv0__data_o$next[63:0]$10785 - attribute \src "libresoc.v:176307.5-176307.29" + assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:178023.5-178023.29" switch \initial - attribute \src "libresoc.v:176307.9-176307.17" + attribute \src "libresoc.v:178023.9-178023.17" case 1'1 case end @@ -362964,75 +365650,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10779 $6\sv0__data_o$next[63:0]$10784 + assign $1\sv0__data_o$next[63:0]$10844 $6\sv0__data_o$next[63:0]$10849 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10780 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10845 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10780 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10845 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10781 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10846 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10781 $2\sv0__data_o$next[63:0]$10780 + assign $3\sv0__data_o$next[63:0]$10846 $2\sv0__data_o$next[63:0]$10845 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10782 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10847 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10782 $3\sv0__data_o$next[63:0]$10781 + assign $4\sv0__data_o$next[63:0]$10847 $3\sv0__data_o$next[63:0]$10846 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10783 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10848 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10783 $4\sv0__data_o$next[63:0]$10782 + assign $5\sv0__data_o$next[63:0]$10848 $4\sv0__data_o$next[63:0]$10847 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10784 \reg + assign $6\sv0__data_o$next[63:0]$10849 \reg case - assign $6\sv0__data_o$next[63:0]$10784 $5\sv0__data_o$next[63:0]$10783 + assign $6\sv0__data_o$next[63:0]$10849 $5\sv0__data_o$next[63:0]$10848 end case - assign $1\sv0__data_o$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10844 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10785 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10850 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10785 $1\sv0__data_o$next[63:0]$10779 + assign $7\sv0__data_o$next[63:0]$10850 $1\sv0__data_o$next[63:0]$10844 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10778 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 end - attribute \src "libresoc.v:176352.3-176387.6" - process $proc$libresoc.v:176352$10786 + attribute \src "libresoc.v:178068.3-178103.6" + process $proc$libresoc.v:178068$10851 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10787 $1\wr_detect$7[0:0]$10788 - attribute \src "libresoc.v:176353.5-176353.29" + assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:178069.5-178069.29" switch \initial - attribute \src "libresoc.v:176353.9-176353.17" + attribute \src "libresoc.v:178069.9-178069.17" case 1'1 case end @@ -363045,61 +365731,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10788 $5\wr_detect$7[0:0]$10792 + assign $1\wr_detect$7[0:0]$10853 $5\wr_detect$7[0:0]$10857 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10789 1'1 + assign $2\wr_detect$7[0:0]$10854 1'1 case - assign $2\wr_detect$7[0:0]$10789 1'0 + assign $2\wr_detect$7[0:0]$10854 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10790 1'1 + assign $3\wr_detect$7[0:0]$10855 1'1 case - assign $3\wr_detect$7[0:0]$10790 $2\wr_detect$7[0:0]$10789 + assign $3\wr_detect$7[0:0]$10855 $2\wr_detect$7[0:0]$10854 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10791 1'1 + assign $4\wr_detect$7[0:0]$10856 1'1 case - assign $4\wr_detect$7[0:0]$10791 $3\wr_detect$7[0:0]$10790 + assign $4\wr_detect$7[0:0]$10856 $3\wr_detect$7[0:0]$10855 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10792 1'1 + assign $5\wr_detect$7[0:0]$10857 1'1 case - assign $5\wr_detect$7[0:0]$10792 $4\wr_detect$7[0:0]$10791 + assign $5\wr_detect$7[0:0]$10857 $4\wr_detect$7[0:0]$10856 end case - assign $1\wr_detect$7[0:0]$10788 1'0 + assign $1\wr_detect$7[0:0]$10853 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10787 + update \wr_detect$7 $0\wr_detect$7[0:0]$10852 end - attribute \src "libresoc.v:176388.3-176420.6" - process $proc$libresoc.v:176388$10793 + attribute \src "libresoc.v:178104.3-178136.6" + process $proc$libresoc.v:178104$10858 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10794 $5\reg$next[63:0]$10799 - attribute \src "libresoc.v:176389.5-176389.29" + assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178105.5-178105.29" switch \initial - attribute \src "libresoc.v:176389.9-176389.17" + attribute \src "libresoc.v:178105.9-178105.17" case 1'1 case end @@ -363108,286 +365794,324 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10795 \nia0__data_i + assign $1\reg$next[63:0]$10860 \nia0__data_i case - assign $1\reg$next[63:0]$10795 \reg + assign $1\reg$next[63:0]$10860 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10796 \msr0__data_i + assign $2\reg$next[63:0]$10861 \msr0__data_i case - assign $2\reg$next[63:0]$10796 $1\reg$next[63:0]$10795 + assign $2\reg$next[63:0]$10861 $1\reg$next[63:0]$10860 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10797 \sv0__data_i + assign $3\reg$next[63:0]$10862 \sv0__data_i case - assign $3\reg$next[63:0]$10797 $2\reg$next[63:0]$10796 + assign $3\reg$next[63:0]$10862 $2\reg$next[63:0]$10861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10798 \d_wr10__data_i + assign $4\reg$next[63:0]$10863 \d_wr10__data_i case - assign $4\reg$next[63:0]$10798 $3\reg$next[63:0]$10797 + assign $4\reg$next[63:0]$10863 $3\reg$next[63:0]$10862 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10864 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10799 $4\reg$next[63:0]$10798 + assign $5\reg$next[63:0]$10864 $4\reg$next[63:0]$10863 end sync always - update \reg$next $0\reg$next[63:0]$10794 + update \reg$next $0\reg$next[63:0]$10859 end - connect \$1 $not$libresoc.v:176131$10744_Y - connect \$3 $not$libresoc.v:176132$10745_Y - connect \$6 $not$libresoc.v:176133$10746_Y + connect \$1 $not$libresoc.v:177847$10809_Y + connect \$3 $not$libresoc.v:177848$10810_Y + connect \$6 $not$libresoc.v:177849$10811_Y end -attribute \src "libresoc.v:176425.1-176896.10" +attribute \src "libresoc.v:178141.1-178696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:176426.7-176426.20" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 + attribute \src "libresoc.v:178247.3-178248.49" + wire width 4 $0\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178142.7-178142.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $0\r1__data_o$next[3:0]$10860 - attribute \src "libresoc.v:176511.3-176512.37" + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $0\r1__data_o$next[3:0]$10955 + attribute \src "libresoc.v:178239.3-178240.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $0\r21__data_o$next[3:0]$10874 - attribute \src "libresoc.v:176509.3-176510.39" + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $0\r21__data_o$next[3:0]$10893 + attribute \src "libresoc.v:178237.3-178238.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $0\reg$next[3:0]$10826 - attribute \src "libresoc.v:176507.3-176508.25" + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $0\reg$next[3:0]$10907 + attribute \src "libresoc.v:178235.3-178236.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $0\src11__data_o$next[3:0]$10817 - attribute \src "libresoc.v:176517.3-176518.43" + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $0\src11__data_o$next[3:0]$10913 + attribute \src "libresoc.v:178245.3-178246.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $0\src21__data_o$next[3:0]$10832 - attribute \src "libresoc.v:176515.3-176516.43" + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $0\src21__data_o$next[3:0]$10927 + attribute \src "libresoc.v:178243.3-178244.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $0\src31__data_o$next[3:0]$10846 - attribute \src "libresoc.v:176513.3-176514.43" + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $0\src31__data_o$next[3:0]$10941 + attribute \src "libresoc.v:178241.3-178242.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:176796.3-176825.6" - wire $0\wr_detect$10[0:0]$10868 - attribute \src "libresoc.v:176866.3-176895.6" - wire $0\wr_detect$13[0:0]$10882 - attribute \src "libresoc.v:176656.3-176685.6" - wire $0\wr_detect$4[0:0]$10840 - attribute \src "libresoc.v:176726.3-176755.6" - wire $0\wr_detect$7[0:0]$10854 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178596.3-178625.6" + wire $0\wr_detect$10[0:0]$10949 + attribute \src "libresoc.v:178666.3-178695.6" + wire $0\wr_detect$13[0:0]$10963 + attribute \src "libresoc.v:178359.3-178388.6" + wire $0\wr_detect$16[0:0]$10901 + attribute \src "libresoc.v:178456.3-178485.6" + wire $0\wr_detect$4[0:0]$10921 + attribute \src "libresoc.v:178526.3-178555.6" + wire $0\wr_detect$7[0:0]$10935 + attribute \src "libresoc.v:178289.3-178318.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $1\r1__data_o$next[3:0]$10861 - attribute \src "libresoc.v:176451.13-176451.30" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 + attribute \src "libresoc.v:178161.13-178161.36" + wire width 4 $1\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $1\r1__data_o$next[3:0]$10956 + attribute \src "libresoc.v:178176.13-178176.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $1\r21__data_o$next[3:0]$10875 - attribute \src "libresoc.v:176458.13-176458.31" + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $1\r21__data_o$next[3:0]$10894 + attribute \src "libresoc.v:178183.13-178183.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $1\reg$next[3:0]$10827 - attribute \src "libresoc.v:176464.13-176464.25" + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $1\reg$next[3:0]$10908 + attribute \src "libresoc.v:178189.13-178189.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $1\src11__data_o$next[3:0]$10818 - attribute \src "libresoc.v:176469.13-176469.33" + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $1\src11__data_o$next[3:0]$10914 + attribute \src "libresoc.v:178194.13-178194.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $1\src21__data_o$next[3:0]$10833 - attribute \src "libresoc.v:176476.13-176476.33" + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $1\src21__data_o$next[3:0]$10928 + attribute \src "libresoc.v:178201.13-178201.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $1\src31__data_o$next[3:0]$10847 - attribute \src "libresoc.v:176483.13-176483.33" + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $1\src31__data_o$next[3:0]$10942 + attribute \src "libresoc.v:178208.13-178208.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:176796.3-176825.6" - wire $1\wr_detect$10[0:0]$10869 - attribute \src "libresoc.v:176866.3-176895.6" - wire $1\wr_detect$13[0:0]$10883 - attribute \src "libresoc.v:176656.3-176685.6" - wire $1\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:176726.3-176755.6" - wire $1\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178596.3-178625.6" + wire $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178666.3-178695.6" + wire $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178359.3-178388.6" + wire $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178456.3-178485.6" + wire $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178526.3-178555.6" + wire $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178289.3-178318.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $2\r1__data_o$next[3:0]$10862 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $2\r21__data_o$next[3:0]$10876 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $2\reg$next[3:0]$10828 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $2\src11__data_o$next[3:0]$10819 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $2\src21__data_o$next[3:0]$10834 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $2\src31__data_o$next[3:0]$10848 - attribute \src "libresoc.v:176796.3-176825.6" - wire $2\wr_detect$10[0:0]$10870 - attribute \src "libresoc.v:176866.3-176895.6" - wire $2\wr_detect$13[0:0]$10884 - attribute \src "libresoc.v:176656.3-176685.6" - wire $2\wr_detect$4[0:0]$10842 - attribute \src "libresoc.v:176726.3-176755.6" - wire $2\wr_detect$7[0:0]$10856 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $2\r1__data_o$next[3:0]$10957 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $2\r21__data_o$next[3:0]$10895 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $2\reg$next[3:0]$10909 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $2\src11__data_o$next[3:0]$10915 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $2\src21__data_o$next[3:0]$10929 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $2\src31__data_o$next[3:0]$10943 + attribute \src "libresoc.v:178596.3-178625.6" + wire $2\wr_detect$10[0:0]$10951 + attribute \src "libresoc.v:178666.3-178695.6" + wire $2\wr_detect$13[0:0]$10965 + attribute \src "libresoc.v:178359.3-178388.6" + wire $2\wr_detect$16[0:0]$10903 + attribute \src "libresoc.v:178456.3-178485.6" + wire $2\wr_detect$4[0:0]$10923 + attribute \src "libresoc.v:178526.3-178555.6" + wire $2\wr_detect$7[0:0]$10937 + attribute \src "libresoc.v:178289.3-178318.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $3\r1__data_o$next[3:0]$10863 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $3\r21__data_o$next[3:0]$10877 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $3\reg$next[3:0]$10829 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $3\src11__data_o$next[3:0]$10820 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $3\src21__data_o$next[3:0]$10835 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $3\src31__data_o$next[3:0]$10849 - attribute \src "libresoc.v:176796.3-176825.6" - wire $3\wr_detect$10[0:0]$10871 - attribute \src "libresoc.v:176866.3-176895.6" - wire $3\wr_detect$13[0:0]$10885 - attribute \src "libresoc.v:176656.3-176685.6" - wire $3\wr_detect$4[0:0]$10843 - attribute \src "libresoc.v:176726.3-176755.6" - wire $3\wr_detect$7[0:0]$10857 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $3\r1__data_o$next[3:0]$10958 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $3\r21__data_o$next[3:0]$10896 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $3\reg$next[3:0]$10910 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $3\src11__data_o$next[3:0]$10916 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $3\src21__data_o$next[3:0]$10930 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $3\src31__data_o$next[3:0]$10944 + attribute \src "libresoc.v:178596.3-178625.6" + wire $3\wr_detect$10[0:0]$10952 + attribute \src "libresoc.v:178666.3-178695.6" + wire $3\wr_detect$13[0:0]$10966 + attribute \src "libresoc.v:178359.3-178388.6" + wire $3\wr_detect$16[0:0]$10904 + attribute \src "libresoc.v:178456.3-178485.6" + wire $3\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:178526.3-178555.6" + wire $3\wr_detect$7[0:0]$10938 + attribute \src "libresoc.v:178289.3-178318.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $4\r1__data_o$next[3:0]$10864 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $4\r21__data_o$next[3:0]$10878 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $4\reg$next[3:0]$10830 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $4\src11__data_o$next[3:0]$10821 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $4\src21__data_o$next[3:0]$10836 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $4\src31__data_o$next[3:0]$10850 - attribute \src "libresoc.v:176796.3-176825.6" - wire $4\wr_detect$10[0:0]$10872 - attribute \src "libresoc.v:176866.3-176895.6" - wire $4\wr_detect$13[0:0]$10886 - attribute \src "libresoc.v:176656.3-176685.6" - wire $4\wr_detect$4[0:0]$10844 - attribute \src "libresoc.v:176726.3-176755.6" - wire $4\wr_detect$7[0:0]$10858 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $4\r1__data_o$next[3:0]$10959 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $4\r21__data_o$next[3:0]$10897 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $4\src11__data_o$next[3:0]$10917 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $4\src21__data_o$next[3:0]$10931 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $4\src31__data_o$next[3:0]$10945 + attribute \src "libresoc.v:178596.3-178625.6" + wire $4\wr_detect$10[0:0]$10953 + attribute \src "libresoc.v:178666.3-178695.6" + wire $4\wr_detect$13[0:0]$10967 + attribute \src "libresoc.v:178359.3-178388.6" + wire $4\wr_detect$16[0:0]$10905 + attribute \src "libresoc.v:178456.3-178485.6" + wire $4\wr_detect$4[0:0]$10925 + attribute \src "libresoc.v:178526.3-178555.6" + wire $4\wr_detect$7[0:0]$10939 + attribute \src "libresoc.v:178289.3-178318.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $5\r1__data_o$next[3:0]$10865 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $5\r21__data_o$next[3:0]$10879 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $5\src11__data_o$next[3:0]$10822 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $5\src21__data_o$next[3:0]$10837 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $5\src31__data_o$next[3:0]$10851 - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $6\r1__data_o$next[3:0]$10866 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $6\r21__data_o$next[3:0]$10880 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $6\src11__data_o$next[3:0]$10823 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $6\src21__data_o$next[3:0]$10838 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $6\src31__data_o$next[3:0]$10852 - attribute \src "libresoc.v:176502.17-176502.104" - wire $not$libresoc.v:176502$10805_Y - attribute \src "libresoc.v:176503.18-176503.105" - wire $not$libresoc.v:176503$10806_Y - attribute \src "libresoc.v:176504.17-176504.100" - wire $not$libresoc.v:176504$10807_Y - attribute \src "libresoc.v:176505.17-176505.103" - wire $not$libresoc.v:176505$10808_Y - attribute \src "libresoc.v:176506.17-176506.103" - wire $not$libresoc.v:176506$10809_Y + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $5\r1__data_o$next[3:0]$10960 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $5\r21__data_o$next[3:0]$10898 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $5\src11__data_o$next[3:0]$10918 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $5\src21__data_o$next[3:0]$10932 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $5\src31__data_o$next[3:0]$10946 + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178229.17-178229.104" + wire $not$libresoc.v:178229$10870_Y + attribute \src "libresoc.v:178230.18-178230.105" + wire $not$libresoc.v:178230$10871_Y + attribute \src "libresoc.v:178231.18-178231.105" + wire $not$libresoc.v:178231$10872_Y + attribute \src "libresoc.v:178232.17-178232.100" + wire $not$libresoc.v:178232$10873_Y + attribute \src "libresoc.v:178233.17-178233.103" + wire $not$libresoc.v:178233$10874_Y + attribute \src "libresoc.v:178234.17-178234.103" + wire $not$libresoc.v:178234$10875_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest11__data_i + wire width 4 output 3 \cr_pred1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest11__wen + wire width 4 \cr_pred1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest21__data_i + wire input 2 \cr_pred1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest21__wen - attribute \src "libresoc.v:176426.7-176426.15" + wire width 4 input 11 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest21__wen + attribute \src "libresoc.v:178142.7-178142.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r1__data_o + wire width 4 output 14 \r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r1__ren + wire input 15 \r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r21__data_o + wire width 4 output 16 \r21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r21__ren + wire input 17 \r21__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src11__data_o + wire width 4 output 5 \src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src11__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src11__ren + wire input 4 \src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src21__data_o + wire width 4 output 7 \src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src21__ren + wire input 6 \src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src31__data_o + wire width 4 output 9 \src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src31__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src31__ren + wire input 8 \src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w1__data_i + wire width 4 input 18 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w1__wen + wire input 19 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -363395,232 +366119,257 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176502$10805 + cell $not $not$libresoc.v:178229$10870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176502$10805_Y + connect \Y $not$libresoc.v:178229$10870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176503$10806 + cell $not $not$libresoc.v:178230$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176503$10806_Y + connect \Y $not$libresoc.v:178230$10871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176504$10807 + cell $not $not$libresoc.v:178231$10872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:178231$10872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178232$10873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176504$10807_Y + connect \Y $not$libresoc.v:178232$10873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176505$10808 + cell $not $not$libresoc.v:178233$10874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176505$10808_Y + connect \Y $not$libresoc.v:178233$10874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176506$10809 + cell $not $not$libresoc.v:178234$10875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176506$10809_Y + connect \Y $not$libresoc.v:178234$10875_Y end - attribute \src "libresoc.v:176426.7-176426.20" - process $proc$libresoc.v:176426$10887 + attribute \src "libresoc.v:178142.7-178142.20" + process $proc$libresoc.v:178142$10968 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176451.13-176451.30" - process $proc$libresoc.v:176451$10888 + attribute \src "libresoc.v:178161.13-178161.36" + process $proc$libresoc.v:178161$10969 + assign { } { } + assign $1\cr_pred1__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178176.13-178176.30" + process $proc$libresoc.v:178176$10970 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:176458.13-176458.31" - process $proc$libresoc.v:176458$10889 + attribute \src "libresoc.v:178183.13-178183.31" + process $proc$libresoc.v:178183$10971 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:176464.13-176464.25" - process $proc$libresoc.v:176464$10890 + attribute \src "libresoc.v:178189.13-178189.25" + process $proc$libresoc.v:178189$10972 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176469.13-176469.33" - process $proc$libresoc.v:176469$10891 + attribute \src "libresoc.v:178194.13-178194.33" + process $proc$libresoc.v:178194$10973 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:176476.13-176476.33" - process $proc$libresoc.v:176476$10892 + attribute \src "libresoc.v:178201.13-178201.33" + process $proc$libresoc.v:178201$10974 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:176483.13-176483.33" - process $proc$libresoc.v:176483$10893 + attribute \src "libresoc.v:178208.13-178208.33" + process $proc$libresoc.v:178208$10975 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:176507.3-176508.25" - process $proc$libresoc.v:176507$10810 + attribute \src "libresoc.v:178235.3-178236.25" + process $proc$libresoc.v:178235$10876 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176509.3-176510.39" - process $proc$libresoc.v:176509$10811 + attribute \src "libresoc.v:178237.3-178238.39" + process $proc$libresoc.v:178237$10877 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:176511.3-176512.37" - process $proc$libresoc.v:176511$10812 + attribute \src "libresoc.v:178239.3-178240.37" + process $proc$libresoc.v:178239$10878 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:176513.3-176514.43" - process $proc$libresoc.v:176513$10813 + attribute \src "libresoc.v:178241.3-178242.43" + process $proc$libresoc.v:178241$10879 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:176515.3-176516.43" - process $proc$libresoc.v:176515$10814 + attribute \src "libresoc.v:178243.3-178244.43" + process $proc$libresoc.v:178243$10880 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:176517.3-176518.43" - process $proc$libresoc.v:176517$10815 + attribute \src "libresoc.v:178245.3-178246.43" + process $proc$libresoc.v:178245$10881 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:176519.3-176558.6" - process $proc$libresoc.v:176519$10816 + attribute \src "libresoc.v:178247.3-178248.49" + process $proc$libresoc.v:178247$10882 + assign { } { } + assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next + sync posedge \coresync_clk + update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178249.3-178288.6" + process $proc$libresoc.v:178249$10883 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10817 $6\src11__data_o$next[3:0]$10823 - attribute \src "libresoc.v:176520.5-176520.29" + assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178250.5-178250.29" switch \initial - attribute \src "libresoc.v:176520.9-176520.17" + attribute \src "libresoc.v:178250.9-178250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \cr_pred1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10818 $5\src11__data_o$next[3:0]$10822 + assign $1\cr_pred1__data_o$next[3:0]$10885 $5\cr_pred1__data_o$next[3:0]$10889 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10819 \dest11__data_i + assign $2\cr_pred1__data_o$next[3:0]$10886 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10819 4'0000 + assign $2\cr_pred1__data_o$next[3:0]$10886 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10820 \dest21__data_i + assign $3\cr_pred1__data_o$next[3:0]$10887 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10820 $2\src11__data_o$next[3:0]$10819 + assign $3\cr_pred1__data_o$next[3:0]$10887 $2\cr_pred1__data_o$next[3:0]$10886 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10821 \w1__data_i + assign $4\cr_pred1__data_o$next[3:0]$10888 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10821 $3\src11__data_o$next[3:0]$10820 + assign $4\cr_pred1__data_o$next[3:0]$10888 $3\cr_pred1__data_o$next[3:0]$10887 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10822 \reg + assign $5\cr_pred1__data_o$next[3:0]$10889 \reg case - assign $5\src11__data_o$next[3:0]$10822 $4\src11__data_o$next[3:0]$10821 + assign $5\cr_pred1__data_o$next[3:0]$10889 $4\cr_pred1__data_o$next[3:0]$10888 end case - assign $1\src11__data_o$next[3:0]$10818 4'0000 + assign $1\cr_pred1__data_o$next[3:0]$10885 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10823 4'0000 + assign $6\cr_pred1__data_o$next[3:0]$10890 4'0000 case - assign $6\src11__data_o$next[3:0]$10823 $1\src11__data_o$next[3:0]$10818 + assign $6\cr_pred1__data_o$next[3:0]$10890 $1\cr_pred1__data_o$next[3:0]$10885 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10817 + update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 end - attribute \src "libresoc.v:176559.3-176588.6" - process $proc$libresoc.v:176559$10824 + attribute \src "libresoc.v:178289.3-178318.6" + process $proc$libresoc.v:178289$10891 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176560.5-176560.29" + attribute \src "libresoc.v:178290.5-178290.29" switch \initial - attribute \src "libresoc.v:176560.9-176560.17" + attribute \src "libresoc.v:178290.9-178290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \cr_pred1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -363661,17 +366410,142 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176589.3-176615.6" - process $proc$libresoc.v:176589$10825 + attribute \src "libresoc.v:178319.3-178358.6" + process $proc$libresoc.v:178319$10892 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178320.5-178320.29" + switch \initial + attribute \src "libresoc.v:178320.9-178320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10894 $5\r21__data_o$next[3:0]$10898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10895 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10895 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10896 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10896 $2\r21__data_o$next[3:0]$10895 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10897 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10897 $3\r21__data_o$next[3:0]$10896 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10898 \reg + case + assign $5\r21__data_o$next[3:0]$10898 $4\r21__data_o$next[3:0]$10897 + end + case + assign $1\r21__data_o$next[3:0]$10894 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10899 4'0000 + case + assign $6\r21__data_o$next[3:0]$10899 $1\r21__data_o$next[3:0]$10894 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 + end + attribute \src "libresoc.v:178359.3-178388.6" + process $proc$libresoc.v:178359$10900 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178360.5-178360.29" + switch \initial + attribute \src "libresoc.v:178360.9-178360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$10902 $4\wr_detect$16[0:0]$10905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$10903 1'1 + case + assign $2\wr_detect$16[0:0]$10903 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$10904 1'1 + case + assign $3\wr_detect$16[0:0]$10904 $2\wr_detect$16[0:0]$10903 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$10905 1'1 + case + assign $4\wr_detect$16[0:0]$10905 $3\wr_detect$16[0:0]$10904 + end + case + assign $1\wr_detect$16[0:0]$10902 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10901 + end + attribute \src "libresoc.v:178389.3-178415.6" + process $proc$libresoc.v:178389$10906 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10826 $4\reg$next[3:0]$10830 - attribute \src "libresoc.v:176590.5-176590.29" + assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178390.5-178390.29" switch \initial - attribute \src "libresoc.v:176590.9-176590.17" + attribute \src "libresoc.v:178390.9-178390.17" case 1'1 case end @@ -363680,705 +366554,706 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10827 \dest11__data_i + assign $1\reg$next[3:0]$10908 \dest11__data_i case - assign $1\reg$next[3:0]$10827 \reg + assign $1\reg$next[3:0]$10908 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10828 \dest21__data_i + assign $2\reg$next[3:0]$10909 \dest21__data_i case - assign $2\reg$next[3:0]$10828 $1\reg$next[3:0]$10827 + assign $2\reg$next[3:0]$10909 $1\reg$next[3:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10829 \w1__data_i + assign $3\reg$next[3:0]$10910 \w1__data_i case - assign $3\reg$next[3:0]$10829 $2\reg$next[3:0]$10828 + assign $3\reg$next[3:0]$10910 $2\reg$next[3:0]$10909 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10830 4'0000 + assign $4\reg$next[3:0]$10911 4'0000 case - assign $4\reg$next[3:0]$10830 $3\reg$next[3:0]$10829 + assign $4\reg$next[3:0]$10911 $3\reg$next[3:0]$10910 end sync always - update \reg$next $0\reg$next[3:0]$10826 + update \reg$next $0\reg$next[3:0]$10907 end - attribute \src "libresoc.v:176616.3-176655.6" - process $proc$libresoc.v:176616$10831 + attribute \src "libresoc.v:178416.3-178455.6" + process $proc$libresoc.v:178416$10912 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10832 $6\src21__data_o$next[3:0]$10838 - attribute \src "libresoc.v:176617.5-176617.29" + assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178417.5-178417.29" switch \initial - attribute \src "libresoc.v:176617.9-176617.17" + attribute \src "libresoc.v:178417.9-178417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10833 $5\src21__data_o$next[3:0]$10837 + assign $1\src11__data_o$next[3:0]$10914 $5\src11__data_o$next[3:0]$10918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10834 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10915 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10834 4'0000 + assign $2\src11__data_o$next[3:0]$10915 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10835 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10916 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10835 $2\src21__data_o$next[3:0]$10834 + assign $3\src11__data_o$next[3:0]$10916 $2\src11__data_o$next[3:0]$10915 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10836 \w1__data_i + assign $4\src11__data_o$next[3:0]$10917 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10836 $3\src21__data_o$next[3:0]$10835 + assign $4\src11__data_o$next[3:0]$10917 $3\src11__data_o$next[3:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10837 \reg + assign $5\src11__data_o$next[3:0]$10918 \reg case - assign $5\src21__data_o$next[3:0]$10837 $4\src21__data_o$next[3:0]$10836 + assign $5\src11__data_o$next[3:0]$10918 $4\src11__data_o$next[3:0]$10917 end case - assign $1\src21__data_o$next[3:0]$10833 4'0000 + assign $1\src11__data_o$next[3:0]$10914 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10838 4'0000 + assign $6\src11__data_o$next[3:0]$10919 4'0000 case - assign $6\src21__data_o$next[3:0]$10838 $1\src21__data_o$next[3:0]$10833 + assign $6\src11__data_o$next[3:0]$10919 $1\src11__data_o$next[3:0]$10914 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10832 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 end - attribute \src "libresoc.v:176656.3-176685.6" - process $proc$libresoc.v:176656$10839 + attribute \src "libresoc.v:178456.3-178485.6" + process $proc$libresoc.v:178456$10920 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10840 $1\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:176657.5-176657.29" + assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178457.5-178457.29" switch \initial - attribute \src "libresoc.v:176657.9-176657.17" + attribute \src "libresoc.v:178457.9-178457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10844 + assign $1\wr_detect$4[0:0]$10922 $4\wr_detect$4[0:0]$10925 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10842 1'1 + assign $2\wr_detect$4[0:0]$10923 1'1 case - assign $2\wr_detect$4[0:0]$10842 1'0 + assign $2\wr_detect$4[0:0]$10923 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10843 1'1 + assign $3\wr_detect$4[0:0]$10924 1'1 case - assign $3\wr_detect$4[0:0]$10843 $2\wr_detect$4[0:0]$10842 + assign $3\wr_detect$4[0:0]$10924 $2\wr_detect$4[0:0]$10923 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10844 1'1 + assign $4\wr_detect$4[0:0]$10925 1'1 case - assign $4\wr_detect$4[0:0]$10844 $3\wr_detect$4[0:0]$10843 + assign $4\wr_detect$4[0:0]$10925 $3\wr_detect$4[0:0]$10924 end case - assign $1\wr_detect$4[0:0]$10841 1'0 + assign $1\wr_detect$4[0:0]$10922 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10840 + update \wr_detect$4 $0\wr_detect$4[0:0]$10921 end - attribute \src "libresoc.v:176686.3-176725.6" - process $proc$libresoc.v:176686$10845 + attribute \src "libresoc.v:178486.3-178525.6" + process $proc$libresoc.v:178486$10926 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10846 $6\src31__data_o$next[3:0]$10852 - attribute \src "libresoc.v:176687.5-176687.29" + assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178487.5-178487.29" switch \initial - attribute \src "libresoc.v:176687.9-176687.17" + attribute \src "libresoc.v:178487.9-178487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10847 $5\src31__data_o$next[3:0]$10851 + assign $1\src21__data_o$next[3:0]$10928 $5\src21__data_o$next[3:0]$10932 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10848 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10929 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10848 4'0000 + assign $2\src21__data_o$next[3:0]$10929 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10849 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10930 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10849 $2\src31__data_o$next[3:0]$10848 + assign $3\src21__data_o$next[3:0]$10930 $2\src21__data_o$next[3:0]$10929 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10850 \w1__data_i + assign $4\src21__data_o$next[3:0]$10931 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10850 $3\src31__data_o$next[3:0]$10849 + assign $4\src21__data_o$next[3:0]$10931 $3\src21__data_o$next[3:0]$10930 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10851 \reg + assign $5\src21__data_o$next[3:0]$10932 \reg case - assign $5\src31__data_o$next[3:0]$10851 $4\src31__data_o$next[3:0]$10850 + assign $5\src21__data_o$next[3:0]$10932 $4\src21__data_o$next[3:0]$10931 end case - assign $1\src31__data_o$next[3:0]$10847 4'0000 + assign $1\src21__data_o$next[3:0]$10928 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10852 4'0000 + assign $6\src21__data_o$next[3:0]$10933 4'0000 case - assign $6\src31__data_o$next[3:0]$10852 $1\src31__data_o$next[3:0]$10847 + assign $6\src21__data_o$next[3:0]$10933 $1\src21__data_o$next[3:0]$10928 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10846 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 end - attribute \src "libresoc.v:176726.3-176755.6" - process $proc$libresoc.v:176726$10853 + attribute \src "libresoc.v:178526.3-178555.6" + process $proc$libresoc.v:178526$10934 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10854 $1\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:176727.5-176727.29" + assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178527.5-178527.29" switch \initial - attribute \src "libresoc.v:176727.9-176727.17" + attribute \src "libresoc.v:178527.9-178527.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10855 $4\wr_detect$7[0:0]$10858 + assign $1\wr_detect$7[0:0]$10936 $4\wr_detect$7[0:0]$10939 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10856 1'1 + assign $2\wr_detect$7[0:0]$10937 1'1 case - assign $2\wr_detect$7[0:0]$10856 1'0 + assign $2\wr_detect$7[0:0]$10937 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10857 1'1 + assign $3\wr_detect$7[0:0]$10938 1'1 case - assign $3\wr_detect$7[0:0]$10857 $2\wr_detect$7[0:0]$10856 + assign $3\wr_detect$7[0:0]$10938 $2\wr_detect$7[0:0]$10937 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10858 1'1 + assign $4\wr_detect$7[0:0]$10939 1'1 case - assign $4\wr_detect$7[0:0]$10858 $3\wr_detect$7[0:0]$10857 + assign $4\wr_detect$7[0:0]$10939 $3\wr_detect$7[0:0]$10938 end case - assign $1\wr_detect$7[0:0]$10855 1'0 + assign $1\wr_detect$7[0:0]$10936 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10854 + update \wr_detect$7 $0\wr_detect$7[0:0]$10935 end - attribute \src "libresoc.v:176756.3-176795.6" - process $proc$libresoc.v:176756$10859 + attribute \src "libresoc.v:178556.3-178595.6" + process $proc$libresoc.v:178556$10940 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10860 $6\r1__data_o$next[3:0]$10866 - attribute \src "libresoc.v:176757.5-176757.29" + assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178557.5-178557.29" switch \initial - attribute \src "libresoc.v:176757.9-176757.17" + attribute \src "libresoc.v:178557.9-178557.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10861 $5\r1__data_o$next[3:0]$10865 + assign $1\src31__data_o$next[3:0]$10942 $5\src31__data_o$next[3:0]$10946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10862 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10943 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10862 4'0000 + assign $2\src31__data_o$next[3:0]$10943 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10863 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10944 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10863 $2\r1__data_o$next[3:0]$10862 + assign $3\src31__data_o$next[3:0]$10944 $2\src31__data_o$next[3:0]$10943 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10864 \w1__data_i + assign $4\src31__data_o$next[3:0]$10945 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10864 $3\r1__data_o$next[3:0]$10863 + assign $4\src31__data_o$next[3:0]$10945 $3\src31__data_o$next[3:0]$10944 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10865 \reg + assign $5\src31__data_o$next[3:0]$10946 \reg case - assign $5\r1__data_o$next[3:0]$10865 $4\r1__data_o$next[3:0]$10864 + assign $5\src31__data_o$next[3:0]$10946 $4\src31__data_o$next[3:0]$10945 end case - assign $1\r1__data_o$next[3:0]$10861 4'0000 + assign $1\src31__data_o$next[3:0]$10942 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10866 4'0000 + assign $6\src31__data_o$next[3:0]$10947 4'0000 case - assign $6\r1__data_o$next[3:0]$10866 $1\r1__data_o$next[3:0]$10861 + assign $6\src31__data_o$next[3:0]$10947 $1\src31__data_o$next[3:0]$10942 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10860 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 end - attribute \src "libresoc.v:176796.3-176825.6" - process $proc$libresoc.v:176796$10867 + attribute \src "libresoc.v:178596.3-178625.6" + process $proc$libresoc.v:178596$10948 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10868 $1\wr_detect$10[0:0]$10869 - attribute \src "libresoc.v:176797.5-176797.29" + assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178597.5-178597.29" switch \initial - attribute \src "libresoc.v:176797.9-176797.17" + attribute \src "libresoc.v:178597.9-178597.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10869 $4\wr_detect$10[0:0]$10872 + assign $1\wr_detect$10[0:0]$10950 $4\wr_detect$10[0:0]$10953 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10870 1'1 + assign $2\wr_detect$10[0:0]$10951 1'1 case - assign $2\wr_detect$10[0:0]$10870 1'0 + assign $2\wr_detect$10[0:0]$10951 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10871 1'1 + assign $3\wr_detect$10[0:0]$10952 1'1 case - assign $3\wr_detect$10[0:0]$10871 $2\wr_detect$10[0:0]$10870 + assign $3\wr_detect$10[0:0]$10952 $2\wr_detect$10[0:0]$10951 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10872 1'1 + assign $4\wr_detect$10[0:0]$10953 1'1 case - assign $4\wr_detect$10[0:0]$10872 $3\wr_detect$10[0:0]$10871 + assign $4\wr_detect$10[0:0]$10953 $3\wr_detect$10[0:0]$10952 end case - assign $1\wr_detect$10[0:0]$10869 1'0 + assign $1\wr_detect$10[0:0]$10950 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10868 + update \wr_detect$10 $0\wr_detect$10[0:0]$10949 end - attribute \src "libresoc.v:176826.3-176865.6" - process $proc$libresoc.v:176826$10873 + attribute \src "libresoc.v:178626.3-178665.6" + process $proc$libresoc.v:178626$10954 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10874 $6\r21__data_o$next[3:0]$10880 - attribute \src "libresoc.v:176827.5-176827.29" + assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178627.5-178627.29" switch \initial - attribute \src "libresoc.v:176827.9-176827.17" + attribute \src "libresoc.v:178627.9-178627.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10875 $5\r21__data_o$next[3:0]$10879 + assign $1\r1__data_o$next[3:0]$10956 $5\r1__data_o$next[3:0]$10960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10876 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10957 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10876 4'0000 + assign $2\r1__data_o$next[3:0]$10957 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10877 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10958 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10877 $2\r21__data_o$next[3:0]$10876 + assign $3\r1__data_o$next[3:0]$10958 $2\r1__data_o$next[3:0]$10957 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10878 \w1__data_i + assign $4\r1__data_o$next[3:0]$10959 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10878 $3\r21__data_o$next[3:0]$10877 + assign $4\r1__data_o$next[3:0]$10959 $3\r1__data_o$next[3:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10879 \reg + assign $5\r1__data_o$next[3:0]$10960 \reg case - assign $5\r21__data_o$next[3:0]$10879 $4\r21__data_o$next[3:0]$10878 + assign $5\r1__data_o$next[3:0]$10960 $4\r1__data_o$next[3:0]$10959 end case - assign $1\r21__data_o$next[3:0]$10875 4'0000 + assign $1\r1__data_o$next[3:0]$10956 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10880 4'0000 + assign $6\r1__data_o$next[3:0]$10961 4'0000 case - assign $6\r21__data_o$next[3:0]$10880 $1\r21__data_o$next[3:0]$10875 + assign $6\r1__data_o$next[3:0]$10961 $1\r1__data_o$next[3:0]$10956 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10874 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 end - attribute \src "libresoc.v:176866.3-176895.6" - process $proc$libresoc.v:176866$10881 + attribute \src "libresoc.v:178666.3-178695.6" + process $proc$libresoc.v:178666$10962 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10882 $1\wr_detect$13[0:0]$10883 - attribute \src "libresoc.v:176867.5-176867.29" + assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178667.5-178667.29" switch \initial - attribute \src "libresoc.v:176867.9-176867.17" + attribute \src "libresoc.v:178667.9-178667.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10883 $4\wr_detect$13[0:0]$10886 + assign $1\wr_detect$13[0:0]$10964 $4\wr_detect$13[0:0]$10967 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10884 1'1 + assign $2\wr_detect$13[0:0]$10965 1'1 case - assign $2\wr_detect$13[0:0]$10884 1'0 + assign $2\wr_detect$13[0:0]$10965 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10885 1'1 + assign $3\wr_detect$13[0:0]$10966 1'1 case - assign $3\wr_detect$13[0:0]$10885 $2\wr_detect$13[0:0]$10884 + assign $3\wr_detect$13[0:0]$10966 $2\wr_detect$13[0:0]$10965 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10886 1'1 + assign $4\wr_detect$13[0:0]$10967 1'1 case - assign $4\wr_detect$13[0:0]$10886 $3\wr_detect$13[0:0]$10885 + assign $4\wr_detect$13[0:0]$10967 $3\wr_detect$13[0:0]$10966 end case - assign $1\wr_detect$13[0:0]$10883 1'0 + assign $1\wr_detect$13[0:0]$10964 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10882 + update \wr_detect$13 $0\wr_detect$13[0:0]$10963 end - connect \$9 $not$libresoc.v:176502$10805_Y - connect \$12 $not$libresoc.v:176503$10806_Y - connect \$1 $not$libresoc.v:176504$10807_Y - connect \$3 $not$libresoc.v:176505$10808_Y - connect \$6 $not$libresoc.v:176506$10809_Y + connect \$9 $not$libresoc.v:178229$10870_Y + connect \$12 $not$libresoc.v:178230$10871_Y + connect \$15 $not$libresoc.v:178231$10872_Y + connect \$1 $not$libresoc.v:178232$10873_Y + connect \$3 $not$libresoc.v:178233$10874_Y + connect \$6 $not$libresoc.v:178234$10875_Y end -attribute \src "libresoc.v:176900.1-177345.10" +attribute \src "libresoc.v:178700.1-179145.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:176901.7-176901.20" + attribute \src "libresoc.v:178701.7-178701.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $0\r1__data_o$next[1:0]$10946 - attribute \src "libresoc.v:176976.3-176977.37" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $0\r1__data_o$next[1:0]$11028 + attribute \src "libresoc.v:178776.3-178777.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $0\reg$next[1:0]$10962 - attribute \src "libresoc.v:176974.3-176975.25" + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $0\reg$next[1:0]$11044 + attribute \src "libresoc.v:178774.3-178775.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $0\src11__data_o$next[1:0]$10904 - attribute \src "libresoc.v:176982.3-176983.43" + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $0\src11__data_o$next[1:0]$10986 + attribute \src "libresoc.v:178782.3-178783.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $0\src21__data_o$next[1:0]$10914 - attribute \src "libresoc.v:176980.3-176981.43" + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $0\src21__data_o$next[1:0]$10996 + attribute \src "libresoc.v:178780.3-178781.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $0\src31__data_o$next[1:0]$10930 - attribute \src "libresoc.v:176978.3-176979.43" + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $0\src31__data_o$next[1:0]$11012 + attribute \src "libresoc.v:178778.3-178779.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:177276.3-177311.6" - wire $0\wr_detect$10[0:0]$10955 - attribute \src "libresoc.v:177112.3-177147.6" - wire $0\wr_detect$4[0:0]$10923 - attribute \src "libresoc.v:177194.3-177229.6" - wire $0\wr_detect$7[0:0]$10939 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179076.3-179111.6" + wire $0\wr_detect$10[0:0]$11037 + attribute \src "libresoc.v:178912.3-178947.6" + wire $0\wr_detect$4[0:0]$11005 + attribute \src "libresoc.v:178994.3-179029.6" + wire $0\wr_detect$7[0:0]$11021 + attribute \src "libresoc.v:178830.3-178865.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $1\r1__data_o$next[1:0]$10947 - attribute \src "libresoc.v:176928.13-176928.30" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $1\r1__data_o$next[1:0]$11029 + attribute \src "libresoc.v:178728.13-178728.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $1\reg$next[1:0]$10963 - attribute \src "libresoc.v:176934.13-176934.25" + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $1\reg$next[1:0]$11045 + attribute \src "libresoc.v:178734.13-178734.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $1\src11__data_o$next[1:0]$10905 - attribute \src "libresoc.v:176939.13-176939.33" + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $1\src11__data_o$next[1:0]$10987 + attribute \src "libresoc.v:178739.13-178739.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $1\src21__data_o$next[1:0]$10915 - attribute \src "libresoc.v:176946.13-176946.33" + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $1\src21__data_o$next[1:0]$10997 + attribute \src "libresoc.v:178746.13-178746.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $1\src31__data_o$next[1:0]$10931 - attribute \src "libresoc.v:176953.13-176953.33" + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $1\src31__data_o$next[1:0]$11013 + attribute \src "libresoc.v:178753.13-178753.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:177276.3-177311.6" - wire $1\wr_detect$10[0:0]$10956 - attribute \src "libresoc.v:177112.3-177147.6" - wire $1\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:177194.3-177229.6" - wire $1\wr_detect$7[0:0]$10940 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179076.3-179111.6" + wire $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:178912.3-178947.6" + wire $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178994.3-179029.6" + wire $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178830.3-178865.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $2\r1__data_o$next[1:0]$10948 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $2\reg$next[1:0]$10964 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $2\src11__data_o$next[1:0]$10906 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $2\src21__data_o$next[1:0]$10916 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $2\src31__data_o$next[1:0]$10932 - attribute \src "libresoc.v:177276.3-177311.6" - wire $2\wr_detect$10[0:0]$10957 - attribute \src "libresoc.v:177112.3-177147.6" - wire $2\wr_detect$4[0:0]$10925 - attribute \src "libresoc.v:177194.3-177229.6" - wire $2\wr_detect$7[0:0]$10941 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $2\r1__data_o$next[1:0]$11030 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $2\reg$next[1:0]$11046 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $2\src11__data_o$next[1:0]$10988 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $2\src21__data_o$next[1:0]$10998 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $2\src31__data_o$next[1:0]$11014 + attribute \src "libresoc.v:179076.3-179111.6" + wire $2\wr_detect$10[0:0]$11039 + attribute \src "libresoc.v:178912.3-178947.6" + wire $2\wr_detect$4[0:0]$11007 + attribute \src "libresoc.v:178994.3-179029.6" + wire $2\wr_detect$7[0:0]$11023 + attribute \src "libresoc.v:178830.3-178865.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $3\r1__data_o$next[1:0]$10949 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $3\reg$next[1:0]$10965 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $3\src11__data_o$next[1:0]$10907 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $3\src21__data_o$next[1:0]$10917 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $3\src31__data_o$next[1:0]$10933 - attribute \src "libresoc.v:177276.3-177311.6" - wire $3\wr_detect$10[0:0]$10958 - attribute \src "libresoc.v:177112.3-177147.6" - wire $3\wr_detect$4[0:0]$10926 - attribute \src "libresoc.v:177194.3-177229.6" - wire $3\wr_detect$7[0:0]$10942 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $3\r1__data_o$next[1:0]$11031 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $3\reg$next[1:0]$11047 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $3\src11__data_o$next[1:0]$10989 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $3\src21__data_o$next[1:0]$10999 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $3\src31__data_o$next[1:0]$11015 + attribute \src "libresoc.v:179076.3-179111.6" + wire $3\wr_detect$10[0:0]$11040 + attribute \src "libresoc.v:178912.3-178947.6" + wire $3\wr_detect$4[0:0]$11008 + attribute \src "libresoc.v:178994.3-179029.6" + wire $3\wr_detect$7[0:0]$11024 + attribute \src "libresoc.v:178830.3-178865.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $4\r1__data_o$next[1:0]$10950 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $4\reg$next[1:0]$10966 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $4\src11__data_o$next[1:0]$10908 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $4\src21__data_o$next[1:0]$10918 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $4\src31__data_o$next[1:0]$10934 - attribute \src "libresoc.v:177276.3-177311.6" - wire $4\wr_detect$10[0:0]$10959 - attribute \src "libresoc.v:177112.3-177147.6" - wire $4\wr_detect$4[0:0]$10927 - attribute \src "libresoc.v:177194.3-177229.6" - wire $4\wr_detect$7[0:0]$10943 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $4\r1__data_o$next[1:0]$11032 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $4\reg$next[1:0]$11048 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $4\src11__data_o$next[1:0]$10990 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $4\src21__data_o$next[1:0]$11000 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $4\src31__data_o$next[1:0]$11016 + attribute \src "libresoc.v:179076.3-179111.6" + wire $4\wr_detect$10[0:0]$11041 + attribute \src "libresoc.v:178912.3-178947.6" + wire $4\wr_detect$4[0:0]$11009 + attribute \src "libresoc.v:178994.3-179029.6" + wire $4\wr_detect$7[0:0]$11025 + attribute \src "libresoc.v:178830.3-178865.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $5\r1__data_o$next[1:0]$10951 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $5\reg$next[1:0]$10967 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $5\src11__data_o$next[1:0]$10909 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $5\src21__data_o$next[1:0]$10919 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $5\src31__data_o$next[1:0]$10935 - attribute \src "libresoc.v:177276.3-177311.6" - wire $5\wr_detect$10[0:0]$10960 - attribute \src "libresoc.v:177112.3-177147.6" - wire $5\wr_detect$4[0:0]$10928 - attribute \src "libresoc.v:177194.3-177229.6" - wire $5\wr_detect$7[0:0]$10944 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $5\r1__data_o$next[1:0]$11033 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $5\src11__data_o$next[1:0]$10991 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $5\src21__data_o$next[1:0]$11001 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $5\src31__data_o$next[1:0]$11017 + attribute \src "libresoc.v:179076.3-179111.6" + wire $5\wr_detect$10[0:0]$11042 + attribute \src "libresoc.v:178912.3-178947.6" + wire $5\wr_detect$4[0:0]$11010 + attribute \src "libresoc.v:178994.3-179029.6" + wire $5\wr_detect$7[0:0]$11026 + attribute \src "libresoc.v:178830.3-178865.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $6\r1__data_o$next[1:0]$10952 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $6\src11__data_o$next[1:0]$10910 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $6\src21__data_o$next[1:0]$10920 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $6\src31__data_o$next[1:0]$10936 - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $7\r1__data_o$next[1:0]$10953 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $7\src11__data_o$next[1:0]$10911 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $7\src21__data_o$next[1:0]$10921 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $7\src31__data_o$next[1:0]$10937 - attribute \src "libresoc.v:176970.17-176970.104" - wire $not$libresoc.v:176970$10894_Y - attribute \src "libresoc.v:176971.17-176971.100" - wire $not$libresoc.v:176971$10895_Y - attribute \src "libresoc.v:176972.17-176972.103" - wire $not$libresoc.v:176972$10896_Y - attribute \src "libresoc.v:176973.17-176973.103" - wire $not$libresoc.v:176973$10897_Y + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $6\r1__data_o$next[1:0]$11034 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $6\src11__data_o$next[1:0]$10992 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $6\src21__data_o$next[1:0]$11002 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $6\src31__data_o$next[1:0]$11018 + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178770.17-178770.104" + wire $not$libresoc.v:178770$10976_Y + attribute \src "libresoc.v:178771.17-178771.100" + wire $not$libresoc.v:178771$10977_Y + attribute \src "libresoc.v:178772.17-178772.103" + wire $not$libresoc.v:178772$10978_Y + attribute \src "libresoc.v:178773.17-178773.103" + wire $not$libresoc.v:178773$10979_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364387,9 +367262,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -364403,7 +367278,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:176901.7-176901.15" + attribute \src "libresoc.v:178701.7-178701.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -364446,129 +367321,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176970$10894 + cell $not $not$libresoc.v:178770$10976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176970$10894_Y + connect \Y $not$libresoc.v:178770$10976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176971$10895 + cell $not $not$libresoc.v:178771$10977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176971$10895_Y + connect \Y $not$libresoc.v:178771$10977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176972$10896 + cell $not $not$libresoc.v:178772$10978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176972$10896_Y + connect \Y $not$libresoc.v:178772$10978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176973$10897 + cell $not $not$libresoc.v:178773$10979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176973$10897_Y + connect \Y $not$libresoc.v:178773$10979_Y end - attribute \src "libresoc.v:176901.7-176901.20" - process $proc$libresoc.v:176901$10968 + attribute \src "libresoc.v:178701.7-178701.20" + process $proc$libresoc.v:178701$11050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176928.13-176928.30" - process $proc$libresoc.v:176928$10969 + attribute \src "libresoc.v:178728.13-178728.30" + process $proc$libresoc.v:178728$11051 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:176934.13-176934.25" - process $proc$libresoc.v:176934$10970 + attribute \src "libresoc.v:178734.13-178734.25" + process $proc$libresoc.v:178734$11052 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:176939.13-176939.33" - process $proc$libresoc.v:176939$10971 + attribute \src "libresoc.v:178739.13-178739.33" + process $proc$libresoc.v:178739$11053 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:176946.13-176946.33" - process $proc$libresoc.v:176946$10972 + attribute \src "libresoc.v:178746.13-178746.33" + process $proc$libresoc.v:178746$11054 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:176953.13-176953.33" - process $proc$libresoc.v:176953$10973 + attribute \src "libresoc.v:178753.13-178753.33" + process $proc$libresoc.v:178753$11055 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:176974.3-176975.25" - process $proc$libresoc.v:176974$10898 + attribute \src "libresoc.v:178774.3-178775.25" + process $proc$libresoc.v:178774$10980 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:176976.3-176977.37" - process $proc$libresoc.v:176976$10899 + attribute \src "libresoc.v:178776.3-178777.37" + process $proc$libresoc.v:178776$10981 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:176978.3-176979.43" - process $proc$libresoc.v:176978$10900 + attribute \src "libresoc.v:178778.3-178779.43" + process $proc$libresoc.v:178778$10982 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:176980.3-176981.43" - process $proc$libresoc.v:176980$10901 + attribute \src "libresoc.v:178780.3-178781.43" + process $proc$libresoc.v:178780$10983 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:176982.3-176983.43" - process $proc$libresoc.v:176982$10902 + attribute \src "libresoc.v:178782.3-178783.43" + process $proc$libresoc.v:178782$10984 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:176984.3-177029.6" - process $proc$libresoc.v:176984$10903 + attribute \src "libresoc.v:178784.3-178829.6" + process $proc$libresoc.v:178784$10985 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10904 $7\src11__data_o$next[1:0]$10911 - attribute \src "libresoc.v:176985.5-176985.29" + assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178785.5-178785.29" switch \initial - attribute \src "libresoc.v:176985.9-176985.17" + attribute \src "libresoc.v:178785.9-178785.17" case 1'1 case end @@ -364581,75 +367456,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10905 $6\src11__data_o$next[1:0]$10910 + assign $1\src11__data_o$next[1:0]$10987 $6\src11__data_o$next[1:0]$10992 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10906 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10988 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10906 2'00 + assign $2\src11__data_o$next[1:0]$10988 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10907 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10989 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10907 $2\src11__data_o$next[1:0]$10906 + assign $3\src11__data_o$next[1:0]$10989 $2\src11__data_o$next[1:0]$10988 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10908 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10990 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10908 $3\src11__data_o$next[1:0]$10907 + assign $4\src11__data_o$next[1:0]$10990 $3\src11__data_o$next[1:0]$10989 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10909 \w1__data_i + assign $5\src11__data_o$next[1:0]$10991 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10909 $4\src11__data_o$next[1:0]$10908 + assign $5\src11__data_o$next[1:0]$10991 $4\src11__data_o$next[1:0]$10990 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10910 \reg + assign $6\src11__data_o$next[1:0]$10992 \reg case - assign $6\src11__data_o$next[1:0]$10910 $5\src11__data_o$next[1:0]$10909 + assign $6\src11__data_o$next[1:0]$10992 $5\src11__data_o$next[1:0]$10991 end case - assign $1\src11__data_o$next[1:0]$10905 2'00 + assign $1\src11__data_o$next[1:0]$10987 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10911 2'00 + assign $7\src11__data_o$next[1:0]$10993 2'00 case - assign $7\src11__data_o$next[1:0]$10911 $1\src11__data_o$next[1:0]$10905 + assign $7\src11__data_o$next[1:0]$10993 $1\src11__data_o$next[1:0]$10987 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10904 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 end - attribute \src "libresoc.v:177030.3-177065.6" - process $proc$libresoc.v:177030$10912 + attribute \src "libresoc.v:178830.3-178865.6" + process $proc$libresoc.v:178830$10994 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177031.5-177031.29" + attribute \src "libresoc.v:178831.5-178831.29" switch \initial - attribute \src "libresoc.v:177031.9-177031.17" + attribute \src "libresoc.v:178831.9-178831.17" case 1'1 case end @@ -364705,15 +367580,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177066.3-177111.6" - process $proc$libresoc.v:177066$10913 + attribute \src "libresoc.v:178866.3-178911.6" + process $proc$libresoc.v:178866$10995 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10914 $7\src21__data_o$next[1:0]$10921 - attribute \src "libresoc.v:177067.5-177067.29" + assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178867.5-178867.29" switch \initial - attribute \src "libresoc.v:177067.9-177067.17" + attribute \src "libresoc.v:178867.9-178867.17" case 1'1 case end @@ -364726,75 +367601,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10915 $6\src21__data_o$next[1:0]$10920 + assign $1\src21__data_o$next[1:0]$10997 $6\src21__data_o$next[1:0]$11002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10916 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10998 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10916 2'00 + assign $2\src21__data_o$next[1:0]$10998 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10917 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10999 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10917 $2\src21__data_o$next[1:0]$10916 + assign $3\src21__data_o$next[1:0]$10999 $2\src21__data_o$next[1:0]$10998 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10918 \dest31__data_i + assign $4\src21__data_o$next[1:0]$11000 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10918 $3\src21__data_o$next[1:0]$10917 + assign $4\src21__data_o$next[1:0]$11000 $3\src21__data_o$next[1:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10919 \w1__data_i + assign $5\src21__data_o$next[1:0]$11001 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10919 $4\src21__data_o$next[1:0]$10918 + assign $5\src21__data_o$next[1:0]$11001 $4\src21__data_o$next[1:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10920 \reg + assign $6\src21__data_o$next[1:0]$11002 \reg case - assign $6\src21__data_o$next[1:0]$10920 $5\src21__data_o$next[1:0]$10919 + assign $6\src21__data_o$next[1:0]$11002 $5\src21__data_o$next[1:0]$11001 end case - assign $1\src21__data_o$next[1:0]$10915 2'00 + assign $1\src21__data_o$next[1:0]$10997 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10921 2'00 + assign $7\src21__data_o$next[1:0]$11003 2'00 case - assign $7\src21__data_o$next[1:0]$10921 $1\src21__data_o$next[1:0]$10915 + assign $7\src21__data_o$next[1:0]$11003 $1\src21__data_o$next[1:0]$10997 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10914 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 end - attribute \src "libresoc.v:177112.3-177147.6" - process $proc$libresoc.v:177112$10922 + attribute \src "libresoc.v:178912.3-178947.6" + process $proc$libresoc.v:178912$11004 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10923 $1\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:177113.5-177113.29" + assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178913.5-178913.29" switch \initial - attribute \src "libresoc.v:177113.9-177113.17" + attribute \src "libresoc.v:178913.9-178913.17" case 1'1 case end @@ -364807,58 +367682,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10924 $5\wr_detect$4[0:0]$10928 + assign $1\wr_detect$4[0:0]$11006 $5\wr_detect$4[0:0]$11010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10925 1'1 + assign $2\wr_detect$4[0:0]$11007 1'1 case - assign $2\wr_detect$4[0:0]$10925 1'0 + assign $2\wr_detect$4[0:0]$11007 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10926 1'1 + assign $3\wr_detect$4[0:0]$11008 1'1 case - assign $3\wr_detect$4[0:0]$10926 $2\wr_detect$4[0:0]$10925 + assign $3\wr_detect$4[0:0]$11008 $2\wr_detect$4[0:0]$11007 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10927 1'1 + assign $4\wr_detect$4[0:0]$11009 1'1 case - assign $4\wr_detect$4[0:0]$10927 $3\wr_detect$4[0:0]$10926 + assign $4\wr_detect$4[0:0]$11009 $3\wr_detect$4[0:0]$11008 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10928 1'1 + assign $5\wr_detect$4[0:0]$11010 1'1 case - assign $5\wr_detect$4[0:0]$10928 $4\wr_detect$4[0:0]$10927 + assign $5\wr_detect$4[0:0]$11010 $4\wr_detect$4[0:0]$11009 end case - assign $1\wr_detect$4[0:0]$10924 1'0 + assign $1\wr_detect$4[0:0]$11006 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10923 + update \wr_detect$4 $0\wr_detect$4[0:0]$11005 end - attribute \src "libresoc.v:177148.3-177193.6" - process $proc$libresoc.v:177148$10929 + attribute \src "libresoc.v:178948.3-178993.6" + process $proc$libresoc.v:178948$11011 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10930 $7\src31__data_o$next[1:0]$10937 - attribute \src "libresoc.v:177149.5-177149.29" + assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178949.5-178949.29" switch \initial - attribute \src "libresoc.v:177149.9-177149.17" + attribute \src "libresoc.v:178949.9-178949.17" case 1'1 case end @@ -364871,75 +367746,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10931 $6\src31__data_o$next[1:0]$10936 + assign $1\src31__data_o$next[1:0]$11013 $6\src31__data_o$next[1:0]$11018 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10932 \dest11__data_i + assign $2\src31__data_o$next[1:0]$11014 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10932 2'00 + assign $2\src31__data_o$next[1:0]$11014 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10933 \dest21__data_i + assign $3\src31__data_o$next[1:0]$11015 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10933 $2\src31__data_o$next[1:0]$10932 + assign $3\src31__data_o$next[1:0]$11015 $2\src31__data_o$next[1:0]$11014 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10934 \dest31__data_i + assign $4\src31__data_o$next[1:0]$11016 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10934 $3\src31__data_o$next[1:0]$10933 + assign $4\src31__data_o$next[1:0]$11016 $3\src31__data_o$next[1:0]$11015 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10935 \w1__data_i + assign $5\src31__data_o$next[1:0]$11017 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10935 $4\src31__data_o$next[1:0]$10934 + assign $5\src31__data_o$next[1:0]$11017 $4\src31__data_o$next[1:0]$11016 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10936 \reg + assign $6\src31__data_o$next[1:0]$11018 \reg case - assign $6\src31__data_o$next[1:0]$10936 $5\src31__data_o$next[1:0]$10935 + assign $6\src31__data_o$next[1:0]$11018 $5\src31__data_o$next[1:0]$11017 end case - assign $1\src31__data_o$next[1:0]$10931 2'00 + assign $1\src31__data_o$next[1:0]$11013 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10937 2'00 + assign $7\src31__data_o$next[1:0]$11019 2'00 case - assign $7\src31__data_o$next[1:0]$10937 $1\src31__data_o$next[1:0]$10931 + assign $7\src31__data_o$next[1:0]$11019 $1\src31__data_o$next[1:0]$11013 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10930 + update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 end - attribute \src "libresoc.v:177194.3-177229.6" - process $proc$libresoc.v:177194$10938 + attribute \src "libresoc.v:178994.3-179029.6" + process $proc$libresoc.v:178994$11020 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10939 $1\wr_detect$7[0:0]$10940 - attribute \src "libresoc.v:177195.5-177195.29" + assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178995.5-178995.29" switch \initial - attribute \src "libresoc.v:177195.9-177195.17" + attribute \src "libresoc.v:178995.9-178995.17" case 1'1 case end @@ -364952,58 +367827,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10940 $5\wr_detect$7[0:0]$10944 + assign $1\wr_detect$7[0:0]$11022 $5\wr_detect$7[0:0]$11026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10941 1'1 + assign $2\wr_detect$7[0:0]$11023 1'1 case - assign $2\wr_detect$7[0:0]$10941 1'0 + assign $2\wr_detect$7[0:0]$11023 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10942 1'1 + assign $3\wr_detect$7[0:0]$11024 1'1 case - assign $3\wr_detect$7[0:0]$10942 $2\wr_detect$7[0:0]$10941 + assign $3\wr_detect$7[0:0]$11024 $2\wr_detect$7[0:0]$11023 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10943 1'1 + assign $4\wr_detect$7[0:0]$11025 1'1 case - assign $4\wr_detect$7[0:0]$10943 $3\wr_detect$7[0:0]$10942 + assign $4\wr_detect$7[0:0]$11025 $3\wr_detect$7[0:0]$11024 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10944 1'1 + assign $5\wr_detect$7[0:0]$11026 1'1 case - assign $5\wr_detect$7[0:0]$10944 $4\wr_detect$7[0:0]$10943 + assign $5\wr_detect$7[0:0]$11026 $4\wr_detect$7[0:0]$11025 end case - assign $1\wr_detect$7[0:0]$10940 1'0 + assign $1\wr_detect$7[0:0]$11022 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10939 + update \wr_detect$7 $0\wr_detect$7[0:0]$11021 end - attribute \src "libresoc.v:177230.3-177275.6" - process $proc$libresoc.v:177230$10945 + attribute \src "libresoc.v:179030.3-179075.6" + process $proc$libresoc.v:179030$11027 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10946 $7\r1__data_o$next[1:0]$10953 - attribute \src "libresoc.v:177231.5-177231.29" + assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:179031.5-179031.29" switch \initial - attribute \src "libresoc.v:177231.9-177231.17" + attribute \src "libresoc.v:179031.9-179031.17" case 1'1 case end @@ -365016,75 +367891,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10947 $6\r1__data_o$next[1:0]$10952 + assign $1\r1__data_o$next[1:0]$11029 $6\r1__data_o$next[1:0]$11034 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10948 \dest11__data_i + assign $2\r1__data_o$next[1:0]$11030 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10948 2'00 + assign $2\r1__data_o$next[1:0]$11030 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10949 \dest21__data_i + assign $3\r1__data_o$next[1:0]$11031 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10949 $2\r1__data_o$next[1:0]$10948 + assign $3\r1__data_o$next[1:0]$11031 $2\r1__data_o$next[1:0]$11030 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10950 \dest31__data_i + assign $4\r1__data_o$next[1:0]$11032 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10950 $3\r1__data_o$next[1:0]$10949 + assign $4\r1__data_o$next[1:0]$11032 $3\r1__data_o$next[1:0]$11031 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10951 \w1__data_i + assign $5\r1__data_o$next[1:0]$11033 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10951 $4\r1__data_o$next[1:0]$10950 + assign $5\r1__data_o$next[1:0]$11033 $4\r1__data_o$next[1:0]$11032 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10952 \reg + assign $6\r1__data_o$next[1:0]$11034 \reg case - assign $6\r1__data_o$next[1:0]$10952 $5\r1__data_o$next[1:0]$10951 + assign $6\r1__data_o$next[1:0]$11034 $5\r1__data_o$next[1:0]$11033 end case - assign $1\r1__data_o$next[1:0]$10947 2'00 + assign $1\r1__data_o$next[1:0]$11029 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10953 2'00 + assign $7\r1__data_o$next[1:0]$11035 2'00 case - assign $7\r1__data_o$next[1:0]$10953 $1\r1__data_o$next[1:0]$10947 + assign $7\r1__data_o$next[1:0]$11035 $1\r1__data_o$next[1:0]$11029 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10946 + update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 end - attribute \src "libresoc.v:177276.3-177311.6" - process $proc$libresoc.v:177276$10954 + attribute \src "libresoc.v:179076.3-179111.6" + process $proc$libresoc.v:179076$11036 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10955 $1\wr_detect$10[0:0]$10956 - attribute \src "libresoc.v:177277.5-177277.29" + assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:179077.5-179077.29" switch \initial - attribute \src "libresoc.v:177277.9-177277.17" + attribute \src "libresoc.v:179077.9-179077.17" case 1'1 case end @@ -365097,61 +367972,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10956 $5\wr_detect$10[0:0]$10960 + assign $1\wr_detect$10[0:0]$11038 $5\wr_detect$10[0:0]$11042 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10957 1'1 + assign $2\wr_detect$10[0:0]$11039 1'1 case - assign $2\wr_detect$10[0:0]$10957 1'0 + assign $2\wr_detect$10[0:0]$11039 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10958 1'1 + assign $3\wr_detect$10[0:0]$11040 1'1 case - assign $3\wr_detect$10[0:0]$10958 $2\wr_detect$10[0:0]$10957 + assign $3\wr_detect$10[0:0]$11040 $2\wr_detect$10[0:0]$11039 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10959 1'1 + assign $4\wr_detect$10[0:0]$11041 1'1 case - assign $4\wr_detect$10[0:0]$10959 $3\wr_detect$10[0:0]$10958 + assign $4\wr_detect$10[0:0]$11041 $3\wr_detect$10[0:0]$11040 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10960 1'1 + assign $5\wr_detect$10[0:0]$11042 1'1 case - assign $5\wr_detect$10[0:0]$10960 $4\wr_detect$10[0:0]$10959 + assign $5\wr_detect$10[0:0]$11042 $4\wr_detect$10[0:0]$11041 end case - assign $1\wr_detect$10[0:0]$10956 1'0 + assign $1\wr_detect$10[0:0]$11038 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10955 + update \wr_detect$10 $0\wr_detect$10[0:0]$11037 end - attribute \src "libresoc.v:177312.3-177344.6" - process $proc$libresoc.v:177312$10961 + attribute \src "libresoc.v:179112.3-179144.6" + process $proc$libresoc.v:179112$11043 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10962 $5\reg$next[1:0]$10967 - attribute \src "libresoc.v:177313.5-177313.29" + assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:179113.5-179113.29" switch \initial - attribute \src "libresoc.v:177313.9-177313.17" + attribute \src "libresoc.v:179113.9-179113.17" case 1'1 case end @@ -365160,179 +368035,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10963 \dest11__data_i + assign $1\reg$next[1:0]$11045 \dest11__data_i case - assign $1\reg$next[1:0]$10963 \reg + assign $1\reg$next[1:0]$11045 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10964 \dest21__data_i + assign $2\reg$next[1:0]$11046 \dest21__data_i case - assign $2\reg$next[1:0]$10964 $1\reg$next[1:0]$10963 + assign $2\reg$next[1:0]$11046 $1\reg$next[1:0]$11045 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10965 \dest31__data_i + assign $3\reg$next[1:0]$11047 \dest31__data_i case - assign $3\reg$next[1:0]$10965 $2\reg$next[1:0]$10964 + assign $3\reg$next[1:0]$11047 $2\reg$next[1:0]$11046 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10966 \w1__data_i + assign $4\reg$next[1:0]$11048 \w1__data_i case - assign $4\reg$next[1:0]$10966 $3\reg$next[1:0]$10965 + assign $4\reg$next[1:0]$11048 $3\reg$next[1:0]$11047 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10967 2'00 + assign $5\reg$next[1:0]$11049 2'00 case - assign $5\reg$next[1:0]$10967 $4\reg$next[1:0]$10966 + assign $5\reg$next[1:0]$11049 $4\reg$next[1:0]$11048 end sync always - update \reg$next $0\reg$next[1:0]$10962 + update \reg$next $0\reg$next[1:0]$11044 end - connect \$9 $not$libresoc.v:176970$10894_Y - connect \$1 $not$libresoc.v:176971$10895_Y - connect \$3 $not$libresoc.v:176972$10896_Y - connect \$6 $not$libresoc.v:176973$10897_Y + connect \$9 $not$libresoc.v:178770$10976_Y + connect \$1 $not$libresoc.v:178771$10977_Y + connect \$3 $not$libresoc.v:178772$10978_Y + connect \$6 $not$libresoc.v:178773$10979_Y end -attribute \src "libresoc.v:177349.1-177698.10" +attribute \src "libresoc.v:179149.1-179498.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $0\cia1__data_o$next[63:0]$10982 - attribute \src "libresoc.v:177417.3-177418.41" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $0\cia1__data_o$next[63:0]$11064 + attribute \src "libresoc.v:179217.3-179218.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:177350.7-177350.20" + attribute \src "libresoc.v:179150.7-179150.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $0\msr1__data_o$next[63:0]$10992 - attribute \src "libresoc.v:177415.3-177416.41" + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $0\msr1__data_o$next[63:0]$11074 + attribute \src "libresoc.v:179215.3-179216.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $0\reg$next[63:0]$11024 - attribute \src "libresoc.v:177411.3-177412.25" + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $0\reg$next[63:0]$11106 + attribute \src "libresoc.v:179211.3-179212.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $0\sv1__data_o$next[63:0]$11008 - attribute \src "libresoc.v:177413.3-177414.39" + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $0\sv1__data_o$next[63:0]$11090 + attribute \src "libresoc.v:179213.3-179214.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:177547.3-177582.6" - wire $0\wr_detect$4[0:0]$11001 - attribute \src "libresoc.v:177629.3-177664.6" - wire $0\wr_detect$7[0:0]$11017 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179347.3-179382.6" + wire $0\wr_detect$4[0:0]$11083 + attribute \src "libresoc.v:179429.3-179464.6" + wire $0\wr_detect$7[0:0]$11099 + attribute \src "libresoc.v:179265.3-179300.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $1\cia1__data_o$next[63:0]$10983 - attribute \src "libresoc.v:177359.14-177359.49" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $1\cia1__data_o$next[63:0]$11065 + attribute \src "libresoc.v:179159.14-179159.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $1\msr1__data_o$next[63:0]$10993 - attribute \src "libresoc.v:177376.14-177376.49" + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $1\msr1__data_o$next[63:0]$11075 + attribute \src "libresoc.v:179176.14-179176.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $1\reg$next[63:0]$11025 - attribute \src "libresoc.v:177388.14-177388.42" + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $1\reg$next[63:0]$11107 + attribute \src "libresoc.v:179188.14-179188.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $1\sv1__data_o$next[63:0]$11009 - attribute \src "libresoc.v:177395.14-177395.48" + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $1\sv1__data_o$next[63:0]$11091 + attribute \src "libresoc.v:179195.14-179195.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:177547.3-177582.6" - wire $1\wr_detect$4[0:0]$11002 - attribute \src "libresoc.v:177629.3-177664.6" - wire $1\wr_detect$7[0:0]$11018 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179347.3-179382.6" + wire $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179429.3-179464.6" + wire $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179265.3-179300.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $2\cia1__data_o$next[63:0]$10984 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $2\msr1__data_o$next[63:0]$10994 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $2\reg$next[63:0]$11026 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $2\sv1__data_o$next[63:0]$11010 - attribute \src "libresoc.v:177547.3-177582.6" - wire $2\wr_detect$4[0:0]$11003 - attribute \src "libresoc.v:177629.3-177664.6" - wire $2\wr_detect$7[0:0]$11019 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $2\cia1__data_o$next[63:0]$11066 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $2\msr1__data_o$next[63:0]$11076 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $2\reg$next[63:0]$11108 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $2\sv1__data_o$next[63:0]$11092 + attribute \src "libresoc.v:179347.3-179382.6" + wire $2\wr_detect$4[0:0]$11085 + attribute \src "libresoc.v:179429.3-179464.6" + wire $2\wr_detect$7[0:0]$11101 + attribute \src "libresoc.v:179265.3-179300.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $3\cia1__data_o$next[63:0]$10985 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $3\msr1__data_o$next[63:0]$10995 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $3\reg$next[63:0]$11027 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $3\sv1__data_o$next[63:0]$11011 - attribute \src "libresoc.v:177547.3-177582.6" - wire $3\wr_detect$4[0:0]$11004 - attribute \src "libresoc.v:177629.3-177664.6" - wire $3\wr_detect$7[0:0]$11020 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $3\cia1__data_o$next[63:0]$11067 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $3\msr1__data_o$next[63:0]$11077 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $3\reg$next[63:0]$11109 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $3\sv1__data_o$next[63:0]$11093 + attribute \src "libresoc.v:179347.3-179382.6" + wire $3\wr_detect$4[0:0]$11086 + attribute \src "libresoc.v:179429.3-179464.6" + wire $3\wr_detect$7[0:0]$11102 + attribute \src "libresoc.v:179265.3-179300.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $4\cia1__data_o$next[63:0]$10986 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $4\msr1__data_o$next[63:0]$10996 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $4\reg$next[63:0]$11028 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $4\sv1__data_o$next[63:0]$11012 - attribute \src "libresoc.v:177547.3-177582.6" - wire $4\wr_detect$4[0:0]$11005 - attribute \src "libresoc.v:177629.3-177664.6" - wire $4\wr_detect$7[0:0]$11021 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $4\cia1__data_o$next[63:0]$11068 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $4\msr1__data_o$next[63:0]$11078 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $4\reg$next[63:0]$11110 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $4\sv1__data_o$next[63:0]$11094 + attribute \src "libresoc.v:179347.3-179382.6" + wire $4\wr_detect$4[0:0]$11087 + attribute \src "libresoc.v:179429.3-179464.6" + wire $4\wr_detect$7[0:0]$11103 + attribute \src "libresoc.v:179265.3-179300.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $5\cia1__data_o$next[63:0]$10987 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $5\msr1__data_o$next[63:0]$10997 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $5\reg$next[63:0]$11029 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $5\sv1__data_o$next[63:0]$11013 - attribute \src "libresoc.v:177547.3-177582.6" - wire $5\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:177629.3-177664.6" - wire $5\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $5\cia1__data_o$next[63:0]$11069 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $5\msr1__data_o$next[63:0]$11079 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $5\sv1__data_o$next[63:0]$11095 + attribute \src "libresoc.v:179347.3-179382.6" + wire $5\wr_detect$4[0:0]$11088 + attribute \src "libresoc.v:179429.3-179464.6" + wire $5\wr_detect$7[0:0]$11104 + attribute \src "libresoc.v:179265.3-179300.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $6\cia1__data_o$next[63:0]$10988 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $6\msr1__data_o$next[63:0]$10998 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $6\sv1__data_o$next[63:0]$11014 - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $7\cia1__data_o$next[63:0]$10989 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $7\msr1__data_o$next[63:0]$10999 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $7\sv1__data_o$next[63:0]$11015 - attribute \src "libresoc.v:177408.17-177408.100" - wire $not$libresoc.v:177408$10974_Y - attribute \src "libresoc.v:177409.17-177409.103" - wire $not$libresoc.v:177409$10975_Y - attribute \src "libresoc.v:177410.17-177410.103" - wire $not$libresoc.v:177410$10976_Y + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $6\cia1__data_o$next[63:0]$11070 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $6\msr1__data_o$next[63:0]$11080 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $6\sv1__data_o$next[63:0]$11096 + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179208.17-179208.100" + wire $not$libresoc.v:179208$11056_Y + attribute \src "libresoc.v:179209.17-179209.103" + wire $not$libresoc.v:179209$11057_Y + attribute \src "libresoc.v:179210.17-179210.103" + wire $not$libresoc.v:179210$11058_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365345,15 +368220,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:177350.7-177350.15" + attribute \src "libresoc.v:179150.7-179150.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -365390,106 +368265,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177408$10974 + cell $not $not$libresoc.v:179208$11056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177408$10974_Y + connect \Y $not$libresoc.v:179208$11056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177409$10975 + cell $not $not$libresoc.v:179209$11057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177409$10975_Y + connect \Y $not$libresoc.v:179209$11057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177410$10976 + cell $not $not$libresoc.v:179210$11058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177410$10976_Y + connect \Y $not$libresoc.v:179210$11058_Y end - attribute \src "libresoc.v:177350.7-177350.20" - process $proc$libresoc.v:177350$11030 + attribute \src "libresoc.v:179150.7-179150.20" + process $proc$libresoc.v:179150$11112 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177359.14-177359.49" - process $proc$libresoc.v:177359$11031 + attribute \src "libresoc.v:179159.14-179159.49" + process $proc$libresoc.v:179159$11113 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:177376.14-177376.49" - process $proc$libresoc.v:177376$11032 + attribute \src "libresoc.v:179176.14-179176.49" + process $proc$libresoc.v:179176$11114 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:177388.14-177388.42" - process $proc$libresoc.v:177388$11033 + attribute \src "libresoc.v:179188.14-179188.42" + process $proc$libresoc.v:179188$11115 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:177395.14-177395.48" - process $proc$libresoc.v:177395$11034 + attribute \src "libresoc.v:179195.14-179195.48" + process $proc$libresoc.v:179195$11116 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:177411.3-177412.25" - process $proc$libresoc.v:177411$10977 + attribute \src "libresoc.v:179211.3-179212.25" + process $proc$libresoc.v:179211$11059 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:177413.3-177414.39" - process $proc$libresoc.v:177413$10978 + attribute \src "libresoc.v:179213.3-179214.39" + process $proc$libresoc.v:179213$11060 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:177415.3-177416.41" - process $proc$libresoc.v:177415$10979 + attribute \src "libresoc.v:179215.3-179216.41" + process $proc$libresoc.v:179215$11061 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:177417.3-177418.41" - process $proc$libresoc.v:177417$10980 + attribute \src "libresoc.v:179217.3-179218.41" + process $proc$libresoc.v:179217$11062 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:177419.3-177464.6" - process $proc$libresoc.v:177419$10981 + attribute \src "libresoc.v:179219.3-179264.6" + process $proc$libresoc.v:179219$11063 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10982 $7\cia1__data_o$next[63:0]$10989 - attribute \src "libresoc.v:177420.5-177420.29" + assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179220.5-179220.29" switch \initial - attribute \src "libresoc.v:177420.9-177420.17" + attribute \src "libresoc.v:179220.9-179220.17" case 1'1 case end @@ -365502,75 +368377,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10983 $6\cia1__data_o$next[63:0]$10988 + assign $1\cia1__data_o$next[63:0]$11065 $6\cia1__data_o$next[63:0]$11070 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10984 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$11066 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$11066 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10985 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$11067 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$10985 $2\cia1__data_o$next[63:0]$10984 + assign $3\cia1__data_o$next[63:0]$11067 $2\cia1__data_o$next[63:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10986 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$11068 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$10986 $3\cia1__data_o$next[63:0]$10985 + assign $4\cia1__data_o$next[63:0]$11068 $3\cia1__data_o$next[63:0]$11067 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10987 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$11069 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$10987 $4\cia1__data_o$next[63:0]$10986 + assign $5\cia1__data_o$next[63:0]$11069 $4\cia1__data_o$next[63:0]$11068 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10988 \reg + assign $6\cia1__data_o$next[63:0]$11070 \reg case - assign $6\cia1__data_o$next[63:0]$10988 $5\cia1__data_o$next[63:0]$10987 + assign $6\cia1__data_o$next[63:0]$11070 $5\cia1__data_o$next[63:0]$11069 end case - assign $1\cia1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$11071 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$10989 $1\cia1__data_o$next[63:0]$10983 + assign $7\cia1__data_o$next[63:0]$11071 $1\cia1__data_o$next[63:0]$11065 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10982 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 end - attribute \src "libresoc.v:177465.3-177500.6" - process $proc$libresoc.v:177465$10990 + attribute \src "libresoc.v:179265.3-179300.6" + process $proc$libresoc.v:179265$11072 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177466.5-177466.29" + attribute \src "libresoc.v:179266.5-179266.29" switch \initial - attribute \src "libresoc.v:177466.9-177466.17" + attribute \src "libresoc.v:179266.9-179266.17" case 1'1 case end @@ -365626,15 +368501,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177501.3-177546.6" - process $proc$libresoc.v:177501$10991 + attribute \src "libresoc.v:179301.3-179346.6" + process $proc$libresoc.v:179301$11073 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10992 $7\msr1__data_o$next[63:0]$10999 - attribute \src "libresoc.v:177502.5-177502.29" + assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179302.5-179302.29" switch \initial - attribute \src "libresoc.v:177502.9-177502.17" + attribute \src "libresoc.v:179302.9-179302.17" case 1'1 case end @@ -365647,75 +368522,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10993 $6\msr1__data_o$next[63:0]$10998 + assign $1\msr1__data_o$next[63:0]$11075 $6\msr1__data_o$next[63:0]$11080 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10994 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$11076 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10994 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10995 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$11077 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10995 $2\msr1__data_o$next[63:0]$10994 + assign $3\msr1__data_o$next[63:0]$11077 $2\msr1__data_o$next[63:0]$11076 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10996 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$11078 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$10996 $3\msr1__data_o$next[63:0]$10995 + assign $4\msr1__data_o$next[63:0]$11078 $3\msr1__data_o$next[63:0]$11077 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10997 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$11079 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$10997 $4\msr1__data_o$next[63:0]$10996 + assign $5\msr1__data_o$next[63:0]$11079 $4\msr1__data_o$next[63:0]$11078 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10998 \reg + assign $6\msr1__data_o$next[63:0]$11080 \reg case - assign $6\msr1__data_o$next[63:0]$10998 $5\msr1__data_o$next[63:0]$10997 + assign $6\msr1__data_o$next[63:0]$11080 $5\msr1__data_o$next[63:0]$11079 end case - assign $1\msr1__data_o$next[63:0]$10993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$10999 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$10999 $1\msr1__data_o$next[63:0]$10993 + assign $7\msr1__data_o$next[63:0]$11081 $1\msr1__data_o$next[63:0]$11075 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10992 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 end - attribute \src "libresoc.v:177547.3-177582.6" - process $proc$libresoc.v:177547$11000 + attribute \src "libresoc.v:179347.3-179382.6" + process $proc$libresoc.v:179347$11082 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11001 $1\wr_detect$4[0:0]$11002 - attribute \src "libresoc.v:177548.5-177548.29" + assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179348.5-179348.29" switch \initial - attribute \src "libresoc.v:177548.9-177548.17" + attribute \src "libresoc.v:179348.9-179348.17" case 1'1 case end @@ -365728,58 +368603,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11002 $5\wr_detect$4[0:0]$11006 + assign $1\wr_detect$4[0:0]$11084 $5\wr_detect$4[0:0]$11088 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11003 1'1 + assign $2\wr_detect$4[0:0]$11085 1'1 case - assign $2\wr_detect$4[0:0]$11003 1'0 + assign $2\wr_detect$4[0:0]$11085 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11004 1'1 + assign $3\wr_detect$4[0:0]$11086 1'1 case - assign $3\wr_detect$4[0:0]$11004 $2\wr_detect$4[0:0]$11003 + assign $3\wr_detect$4[0:0]$11086 $2\wr_detect$4[0:0]$11085 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11005 1'1 + assign $4\wr_detect$4[0:0]$11087 1'1 case - assign $4\wr_detect$4[0:0]$11005 $3\wr_detect$4[0:0]$11004 + assign $4\wr_detect$4[0:0]$11087 $3\wr_detect$4[0:0]$11086 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11006 1'1 + assign $5\wr_detect$4[0:0]$11088 1'1 case - assign $5\wr_detect$4[0:0]$11006 $4\wr_detect$4[0:0]$11005 + assign $5\wr_detect$4[0:0]$11088 $4\wr_detect$4[0:0]$11087 end case - assign $1\wr_detect$4[0:0]$11002 1'0 + assign $1\wr_detect$4[0:0]$11084 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11001 + update \wr_detect$4 $0\wr_detect$4[0:0]$11083 end - attribute \src "libresoc.v:177583.3-177628.6" - process $proc$libresoc.v:177583$11007 + attribute \src "libresoc.v:179383.3-179428.6" + process $proc$libresoc.v:179383$11089 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$11008 $7\sv1__data_o$next[63:0]$11015 - attribute \src "libresoc.v:177584.5-177584.29" + assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179384.5-179384.29" switch \initial - attribute \src "libresoc.v:177584.9-177584.17" + attribute \src "libresoc.v:179384.9-179384.17" case 1'1 case end @@ -365792,75 +368667,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$11009 $6\sv1__data_o$next[63:0]$11014 + assign $1\sv1__data_o$next[63:0]$11091 $6\sv1__data_o$next[63:0]$11096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$11010 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$11092 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$11010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$11011 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$11093 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$11011 $2\sv1__data_o$next[63:0]$11010 + assign $3\sv1__data_o$next[63:0]$11093 $2\sv1__data_o$next[63:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$11012 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$11094 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$11012 $3\sv1__data_o$next[63:0]$11011 + assign $4\sv1__data_o$next[63:0]$11094 $3\sv1__data_o$next[63:0]$11093 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$11013 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$11095 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$11013 $4\sv1__data_o$next[63:0]$11012 + assign $5\sv1__data_o$next[63:0]$11095 $4\sv1__data_o$next[63:0]$11094 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$11014 \reg + assign $6\sv1__data_o$next[63:0]$11096 \reg case - assign $6\sv1__data_o$next[63:0]$11014 $5\sv1__data_o$next[63:0]$11013 + assign $6\sv1__data_o$next[63:0]$11096 $5\sv1__data_o$next[63:0]$11095 end case - assign $1\sv1__data_o$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$11015 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$11015 $1\sv1__data_o$next[63:0]$11009 + assign $7\sv1__data_o$next[63:0]$11097 $1\sv1__data_o$next[63:0]$11091 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11008 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 end - attribute \src "libresoc.v:177629.3-177664.6" - process $proc$libresoc.v:177629$11016 + attribute \src "libresoc.v:179429.3-179464.6" + process $proc$libresoc.v:179429$11098 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11017 $1\wr_detect$7[0:0]$11018 - attribute \src "libresoc.v:177630.5-177630.29" + assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179430.5-179430.29" switch \initial - attribute \src "libresoc.v:177630.9-177630.17" + attribute \src "libresoc.v:179430.9-179430.17" case 1'1 case end @@ -365873,61 +368748,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11018 $5\wr_detect$7[0:0]$11022 + assign $1\wr_detect$7[0:0]$11100 $5\wr_detect$7[0:0]$11104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11019 1'1 + assign $2\wr_detect$7[0:0]$11101 1'1 case - assign $2\wr_detect$7[0:0]$11019 1'0 + assign $2\wr_detect$7[0:0]$11101 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11020 1'1 + assign $3\wr_detect$7[0:0]$11102 1'1 case - assign $3\wr_detect$7[0:0]$11020 $2\wr_detect$7[0:0]$11019 + assign $3\wr_detect$7[0:0]$11102 $2\wr_detect$7[0:0]$11101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11021 1'1 + assign $4\wr_detect$7[0:0]$11103 1'1 case - assign $4\wr_detect$7[0:0]$11021 $3\wr_detect$7[0:0]$11020 + assign $4\wr_detect$7[0:0]$11103 $3\wr_detect$7[0:0]$11102 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11022 1'1 + assign $5\wr_detect$7[0:0]$11104 1'1 case - assign $5\wr_detect$7[0:0]$11022 $4\wr_detect$7[0:0]$11021 + assign $5\wr_detect$7[0:0]$11104 $4\wr_detect$7[0:0]$11103 end case - assign $1\wr_detect$7[0:0]$11018 1'0 + assign $1\wr_detect$7[0:0]$11100 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11017 + update \wr_detect$7 $0\wr_detect$7[0:0]$11099 end - attribute \src "libresoc.v:177665.3-177697.6" - process $proc$libresoc.v:177665$11023 + attribute \src "libresoc.v:179465.3-179497.6" + process $proc$libresoc.v:179465$11105 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11024 $5\reg$next[63:0]$11029 - attribute \src "libresoc.v:177666.5-177666.29" + assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179466.5-179466.29" switch \initial - attribute \src "libresoc.v:177666.9-177666.17" + attribute \src "libresoc.v:179466.9-179466.17" case 1'1 case end @@ -365936,286 +368811,324 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11025 \nia1__data_i + assign $1\reg$next[63:0]$11107 \nia1__data_i case - assign $1\reg$next[63:0]$11025 \reg + assign $1\reg$next[63:0]$11107 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11026 \msr1__data_i + assign $2\reg$next[63:0]$11108 \msr1__data_i case - assign $2\reg$next[63:0]$11026 $1\reg$next[63:0]$11025 + assign $2\reg$next[63:0]$11108 $1\reg$next[63:0]$11107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11027 \sv1__data_i + assign $3\reg$next[63:0]$11109 \sv1__data_i case - assign $3\reg$next[63:0]$11027 $2\reg$next[63:0]$11026 + assign $3\reg$next[63:0]$11109 $2\reg$next[63:0]$11108 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11028 \d_wr11__data_i + assign $4\reg$next[63:0]$11110 \d_wr11__data_i case - assign $4\reg$next[63:0]$11028 $3\reg$next[63:0]$11027 + assign $4\reg$next[63:0]$11110 $3\reg$next[63:0]$11109 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11029 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11111 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11029 $4\reg$next[63:0]$11028 + assign $5\reg$next[63:0]$11111 $4\reg$next[63:0]$11110 end sync always - update \reg$next $0\reg$next[63:0]$11024 + update \reg$next $0\reg$next[63:0]$11106 end - connect \$1 $not$libresoc.v:177408$10974_Y - connect \$3 $not$libresoc.v:177409$10975_Y - connect \$6 $not$libresoc.v:177410$10976_Y + connect \$1 $not$libresoc.v:179208$11056_Y + connect \$3 $not$libresoc.v:179209$11057_Y + connect \$6 $not$libresoc.v:179210$11058_Y end -attribute \src "libresoc.v:177702.1-178173.10" +attribute \src "libresoc.v:179502.1-180057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:177703.7-177703.20" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 + attribute \src "libresoc.v:179608.3-179609.49" + wire width 4 $0\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179503.7-179503.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $0\r22__data_o$next[3:0]$11104 - attribute \src "libresoc.v:177786.3-177787.39" + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $0\r22__data_o$next[3:0]$11140 + attribute \src "libresoc.v:179598.3-179599.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $0\r2__data_o$next[3:0]$11090 - attribute \src "libresoc.v:177788.3-177789.37" + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $0\r2__data_o$next[3:0]$11202 + attribute \src "libresoc.v:179600.3-179601.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $0\reg$next[3:0]$11056 - attribute \src "libresoc.v:177784.3-177785.25" + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $0\reg$next[3:0]$11154 + attribute \src "libresoc.v:179596.3-179597.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $0\src12__data_o$next[3:0]$11047 - attribute \src "libresoc.v:177794.3-177795.43" + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $0\src12__data_o$next[3:0]$11160 + attribute \src "libresoc.v:179606.3-179607.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $0\src22__data_o$next[3:0]$11062 - attribute \src "libresoc.v:177792.3-177793.43" + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $0\src22__data_o$next[3:0]$11174 + attribute \src "libresoc.v:179604.3-179605.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $0\src32__data_o$next[3:0]$11076 - attribute \src "libresoc.v:177790.3-177791.43" + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $0\src32__data_o$next[3:0]$11188 + attribute \src "libresoc.v:179602.3-179603.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:178073.3-178102.6" - wire $0\wr_detect$10[0:0]$11098 - attribute \src "libresoc.v:178143.3-178172.6" - wire $0\wr_detect$13[0:0]$11112 - attribute \src "libresoc.v:177933.3-177962.6" - wire $0\wr_detect$4[0:0]$11070 - attribute \src "libresoc.v:178003.3-178032.6" - wire $0\wr_detect$7[0:0]$11084 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179957.3-179986.6" + wire $0\wr_detect$10[0:0]$11196 + attribute \src "libresoc.v:180027.3-180056.6" + wire $0\wr_detect$13[0:0]$11210 + attribute \src "libresoc.v:179720.3-179749.6" + wire $0\wr_detect$16[0:0]$11148 + attribute \src "libresoc.v:179817.3-179846.6" + wire $0\wr_detect$4[0:0]$11168 + attribute \src "libresoc.v:179887.3-179916.6" + wire $0\wr_detect$7[0:0]$11182 + attribute \src "libresoc.v:179650.3-179679.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $1\r22__data_o$next[3:0]$11105 - attribute \src "libresoc.v:177728.13-177728.31" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 + attribute \src "libresoc.v:179522.13-179522.36" + wire width 4 $1\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $1\r22__data_o$next[3:0]$11141 + attribute \src "libresoc.v:179537.13-179537.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $1\r2__data_o$next[3:0]$11091 - attribute \src "libresoc.v:177735.13-177735.30" + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $1\r2__data_o$next[3:0]$11203 + attribute \src "libresoc.v:179544.13-179544.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $1\reg$next[3:0]$11057 - attribute \src "libresoc.v:177741.13-177741.25" + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $1\reg$next[3:0]$11155 + attribute \src "libresoc.v:179550.13-179550.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $1\src12__data_o$next[3:0]$11048 - attribute \src "libresoc.v:177746.13-177746.33" + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $1\src12__data_o$next[3:0]$11161 + attribute \src "libresoc.v:179555.13-179555.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $1\src22__data_o$next[3:0]$11063 - attribute \src "libresoc.v:177753.13-177753.33" + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $1\src22__data_o$next[3:0]$11175 + attribute \src "libresoc.v:179562.13-179562.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $1\src32__data_o$next[3:0]$11077 - attribute \src "libresoc.v:177760.13-177760.33" + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $1\src32__data_o$next[3:0]$11189 + attribute \src "libresoc.v:179569.13-179569.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:178073.3-178102.6" - wire $1\wr_detect$10[0:0]$11099 - attribute \src "libresoc.v:178143.3-178172.6" - wire $1\wr_detect$13[0:0]$11113 - attribute \src "libresoc.v:177933.3-177962.6" - wire $1\wr_detect$4[0:0]$11071 - attribute \src "libresoc.v:178003.3-178032.6" - wire $1\wr_detect$7[0:0]$11085 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179957.3-179986.6" + wire $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:180027.3-180056.6" + wire $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:179720.3-179749.6" + wire $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179817.3-179846.6" + wire $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179887.3-179916.6" + wire $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179650.3-179679.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $2\r22__data_o$next[3:0]$11106 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $2\r2__data_o$next[3:0]$11092 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $2\reg$next[3:0]$11058 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $2\src12__data_o$next[3:0]$11049 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $2\src22__data_o$next[3:0]$11064 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $2\src32__data_o$next[3:0]$11078 - attribute \src "libresoc.v:178073.3-178102.6" - wire $2\wr_detect$10[0:0]$11100 - attribute \src "libresoc.v:178143.3-178172.6" - wire $2\wr_detect$13[0:0]$11114 - attribute \src "libresoc.v:177933.3-177962.6" - wire $2\wr_detect$4[0:0]$11072 - attribute \src "libresoc.v:178003.3-178032.6" - wire $2\wr_detect$7[0:0]$11086 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $2\r22__data_o$next[3:0]$11142 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $2\r2__data_o$next[3:0]$11204 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $2\reg$next[3:0]$11156 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $2\src12__data_o$next[3:0]$11162 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $2\src22__data_o$next[3:0]$11176 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $2\src32__data_o$next[3:0]$11190 + attribute \src "libresoc.v:179957.3-179986.6" + wire $2\wr_detect$10[0:0]$11198 + attribute \src "libresoc.v:180027.3-180056.6" + wire $2\wr_detect$13[0:0]$11212 + attribute \src "libresoc.v:179720.3-179749.6" + wire $2\wr_detect$16[0:0]$11150 + attribute \src "libresoc.v:179817.3-179846.6" + wire $2\wr_detect$4[0:0]$11170 + attribute \src "libresoc.v:179887.3-179916.6" + wire $2\wr_detect$7[0:0]$11184 + attribute \src "libresoc.v:179650.3-179679.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $3\r22__data_o$next[3:0]$11107 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $3\r2__data_o$next[3:0]$11093 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $3\reg$next[3:0]$11059 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $3\src12__data_o$next[3:0]$11050 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $3\src22__data_o$next[3:0]$11065 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $3\src32__data_o$next[3:0]$11079 - attribute \src "libresoc.v:178073.3-178102.6" - wire $3\wr_detect$10[0:0]$11101 - attribute \src "libresoc.v:178143.3-178172.6" - wire $3\wr_detect$13[0:0]$11115 - attribute \src "libresoc.v:177933.3-177962.6" - wire $3\wr_detect$4[0:0]$11073 - attribute \src "libresoc.v:178003.3-178032.6" - wire $3\wr_detect$7[0:0]$11087 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $3\cr_pred2__data_o$next[3:0]$11134 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $3\r22__data_o$next[3:0]$11143 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $3\r2__data_o$next[3:0]$11205 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $3\reg$next[3:0]$11157 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $3\src12__data_o$next[3:0]$11163 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $3\src22__data_o$next[3:0]$11177 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $3\src32__data_o$next[3:0]$11191 + attribute \src "libresoc.v:179957.3-179986.6" + wire $3\wr_detect$10[0:0]$11199 + attribute \src "libresoc.v:180027.3-180056.6" + wire $3\wr_detect$13[0:0]$11213 + attribute \src "libresoc.v:179720.3-179749.6" + wire $3\wr_detect$16[0:0]$11151 + attribute \src "libresoc.v:179817.3-179846.6" + wire $3\wr_detect$4[0:0]$11171 + attribute \src "libresoc.v:179887.3-179916.6" + wire $3\wr_detect$7[0:0]$11185 + attribute \src "libresoc.v:179650.3-179679.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $4\r22__data_o$next[3:0]$11108 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $4\r2__data_o$next[3:0]$11094 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $4\reg$next[3:0]$11060 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $4\src12__data_o$next[3:0]$11051 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $4\src22__data_o$next[3:0]$11066 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $4\src32__data_o$next[3:0]$11080 - attribute \src "libresoc.v:178073.3-178102.6" - wire $4\wr_detect$10[0:0]$11102 - attribute \src "libresoc.v:178143.3-178172.6" - wire $4\wr_detect$13[0:0]$11116 - attribute \src "libresoc.v:177933.3-177962.6" - wire $4\wr_detect$4[0:0]$11074 - attribute \src "libresoc.v:178003.3-178032.6" - wire $4\wr_detect$7[0:0]$11088 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $4\cr_pred2__data_o$next[3:0]$11135 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $4\r22__data_o$next[3:0]$11144 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $4\r2__data_o$next[3:0]$11206 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $4\src12__data_o$next[3:0]$11164 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $4\src22__data_o$next[3:0]$11178 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $4\src32__data_o$next[3:0]$11192 + attribute \src "libresoc.v:179957.3-179986.6" + wire $4\wr_detect$10[0:0]$11200 + attribute \src "libresoc.v:180027.3-180056.6" + wire $4\wr_detect$13[0:0]$11214 + attribute \src "libresoc.v:179720.3-179749.6" + wire $4\wr_detect$16[0:0]$11152 + attribute \src "libresoc.v:179817.3-179846.6" + wire $4\wr_detect$4[0:0]$11172 + attribute \src "libresoc.v:179887.3-179916.6" + wire $4\wr_detect$7[0:0]$11186 + attribute \src "libresoc.v:179650.3-179679.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $5\r22__data_o$next[3:0]$11109 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $5\r2__data_o$next[3:0]$11095 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $5\src12__data_o$next[3:0]$11052 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $5\src22__data_o$next[3:0]$11067 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $5\src32__data_o$next[3:0]$11081 - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $6\r22__data_o$next[3:0]$11110 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $6\r2__data_o$next[3:0]$11096 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $6\src12__data_o$next[3:0]$11053 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $6\src22__data_o$next[3:0]$11068 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $6\src32__data_o$next[3:0]$11082 - attribute \src "libresoc.v:177779.17-177779.104" - wire $not$libresoc.v:177779$11035_Y - attribute \src "libresoc.v:177780.18-177780.105" - wire $not$libresoc.v:177780$11036_Y - attribute \src "libresoc.v:177781.17-177781.100" - wire $not$libresoc.v:177781$11037_Y - attribute \src "libresoc.v:177782.17-177782.103" - wire $not$libresoc.v:177782$11038_Y - attribute \src "libresoc.v:177783.17-177783.103" - wire $not$libresoc.v:177783$11039_Y + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $5\cr_pred2__data_o$next[3:0]$11136 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $5\r22__data_o$next[3:0]$11145 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $5\r2__data_o$next[3:0]$11207 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $5\src12__data_o$next[3:0]$11165 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $5\src22__data_o$next[3:0]$11179 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $5\src32__data_o$next[3:0]$11193 + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179590.17-179590.104" + wire $not$libresoc.v:179590$11117_Y + attribute \src "libresoc.v:179591.18-179591.105" + wire $not$libresoc.v:179591$11118_Y + attribute \src "libresoc.v:179592.18-179592.105" + wire $not$libresoc.v:179592$11119_Y + attribute \src "libresoc.v:179593.17-179593.100" + wire $not$libresoc.v:179593$11120_Y + attribute \src "libresoc.v:179594.17-179594.103" + wire $not$libresoc.v:179594$11121_Y + attribute \src "libresoc.v:179595.17-179595.103" + wire $not$libresoc.v:179595$11122_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest12__data_i + wire width 4 output 3 \cr_pred2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest12__wen + wire width 4 \cr_pred2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest22__data_i + wire input 2 \cr_pred2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest22__wen - attribute \src "libresoc.v:177703.7-177703.15" + wire width 4 input 11 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest22__wen + attribute \src "libresoc.v:179503.7-179503.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r22__data_o + wire width 4 output 16 \r22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r22__ren + wire input 17 \r22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r2__data_o + wire width 4 output 14 \r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r2__ren + wire input 15 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src12__data_o + wire width 4 output 5 \src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src12__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src12__ren + wire input 4 \src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src22__data_o + wire width 4 output 7 \src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src22__ren + wire input 6 \src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src32__data_o + wire width 4 output 9 \src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src32__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src32__ren + wire input 8 \src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w2__data_i + wire width 4 input 18 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w2__wen + wire input 19 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -366223,232 +369136,257 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177779$11035 + cell $not $not$libresoc.v:179590$11117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177779$11035_Y + connect \Y $not$libresoc.v:179590$11117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177780$11036 + cell $not $not$libresoc.v:179591$11118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:177780$11036_Y + connect \Y $not$libresoc.v:179591$11118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179592$11119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:179592$11119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177781$11037 + cell $not $not$libresoc.v:179593$11120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177781$11037_Y + connect \Y $not$libresoc.v:179593$11120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177782$11038 + cell $not $not$libresoc.v:179594$11121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177782$11038_Y + connect \Y $not$libresoc.v:179594$11121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177783$11039 + cell $not $not$libresoc.v:179595$11122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177783$11039_Y + connect \Y $not$libresoc.v:179595$11122_Y end - attribute \src "libresoc.v:177703.7-177703.20" - process $proc$libresoc.v:177703$11117 + attribute \src "libresoc.v:179503.7-179503.20" + process $proc$libresoc.v:179503$11215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177728.13-177728.31" - process $proc$libresoc.v:177728$11118 + attribute \src "libresoc.v:179522.13-179522.36" + process $proc$libresoc.v:179522$11216 + assign { } { } + assign $1\cr_pred2__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179537.13-179537.31" + process $proc$libresoc.v:179537$11217 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:177735.13-177735.30" - process $proc$libresoc.v:177735$11119 + attribute \src "libresoc.v:179544.13-179544.30" + process $proc$libresoc.v:179544$11218 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:177741.13-177741.25" - process $proc$libresoc.v:177741$11120 + attribute \src "libresoc.v:179550.13-179550.25" + process $proc$libresoc.v:179550$11219 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:177746.13-177746.33" - process $proc$libresoc.v:177746$11121 + attribute \src "libresoc.v:179555.13-179555.33" + process $proc$libresoc.v:179555$11220 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:177753.13-177753.33" - process $proc$libresoc.v:177753$11122 + attribute \src "libresoc.v:179562.13-179562.33" + process $proc$libresoc.v:179562$11221 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:177760.13-177760.33" - process $proc$libresoc.v:177760$11123 + attribute \src "libresoc.v:179569.13-179569.33" + process $proc$libresoc.v:179569$11222 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:177784.3-177785.25" - process $proc$libresoc.v:177784$11040 + attribute \src "libresoc.v:179596.3-179597.25" + process $proc$libresoc.v:179596$11123 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:177786.3-177787.39" - process $proc$libresoc.v:177786$11041 + attribute \src "libresoc.v:179598.3-179599.39" + process $proc$libresoc.v:179598$11124 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:177788.3-177789.37" - process $proc$libresoc.v:177788$11042 + attribute \src "libresoc.v:179600.3-179601.37" + process $proc$libresoc.v:179600$11125 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:177790.3-177791.43" - process $proc$libresoc.v:177790$11043 + attribute \src "libresoc.v:179602.3-179603.43" + process $proc$libresoc.v:179602$11126 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:177792.3-177793.43" - process $proc$libresoc.v:177792$11044 + attribute \src "libresoc.v:179604.3-179605.43" + process $proc$libresoc.v:179604$11127 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:177794.3-177795.43" - process $proc$libresoc.v:177794$11045 + attribute \src "libresoc.v:179606.3-179607.43" + process $proc$libresoc.v:179606$11128 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:177796.3-177835.6" - process $proc$libresoc.v:177796$11046 + attribute \src "libresoc.v:179608.3-179609.49" + process $proc$libresoc.v:179608$11129 + assign { } { } + assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next + sync posedge \coresync_clk + update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179610.3-179649.6" + process $proc$libresoc.v:179610$11130 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$11047 $6\src12__data_o$next[3:0]$11053 - attribute \src "libresoc.v:177797.5-177797.29" + assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179611.5-179611.29" switch \initial - attribute \src "libresoc.v:177797.9-177797.17" + attribute \src "libresoc.v:179611.9-179611.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + switch \cr_pred2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$11048 $5\src12__data_o$next[3:0]$11052 + assign $1\cr_pred2__data_o$next[3:0]$11132 $5\cr_pred2__data_o$next[3:0]$11136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$11049 \dest12__data_i + assign $2\cr_pred2__data_o$next[3:0]$11133 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$11049 4'0000 + assign $2\cr_pred2__data_o$next[3:0]$11133 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$11050 \dest22__data_i + assign $3\cr_pred2__data_o$next[3:0]$11134 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$11050 $2\src12__data_o$next[3:0]$11049 + assign $3\cr_pred2__data_o$next[3:0]$11134 $2\cr_pred2__data_o$next[3:0]$11133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11051 \w2__data_i + assign $4\cr_pred2__data_o$next[3:0]$11135 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11051 $3\src12__data_o$next[3:0]$11050 + assign $4\cr_pred2__data_o$next[3:0]$11135 $3\cr_pred2__data_o$next[3:0]$11134 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11052 \reg + assign $5\cr_pred2__data_o$next[3:0]$11136 \reg case - assign $5\src12__data_o$next[3:0]$11052 $4\src12__data_o$next[3:0]$11051 + assign $5\cr_pred2__data_o$next[3:0]$11136 $4\cr_pred2__data_o$next[3:0]$11135 end case - assign $1\src12__data_o$next[3:0]$11048 4'0000 + assign $1\cr_pred2__data_o$next[3:0]$11132 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11053 4'0000 + assign $6\cr_pred2__data_o$next[3:0]$11137 4'0000 case - assign $6\src12__data_o$next[3:0]$11053 $1\src12__data_o$next[3:0]$11048 + assign $6\cr_pred2__data_o$next[3:0]$11137 $1\cr_pred2__data_o$next[3:0]$11132 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11047 + update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 end - attribute \src "libresoc.v:177836.3-177865.6" - process $proc$libresoc.v:177836$11054 + attribute \src "libresoc.v:179650.3-179679.6" + process $proc$libresoc.v:179650$11138 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177837.5-177837.29" + attribute \src "libresoc.v:179651.5-179651.29" switch \initial - attribute \src "libresoc.v:177837.9-177837.17" + attribute \src "libresoc.v:179651.9-179651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + switch \cr_pred2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -366489,724 +369427,850 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177866.3-177892.6" - process $proc$libresoc.v:177866$11055 - assign { } { } + attribute \src "libresoc.v:179680.3-179719.6" + process $proc$libresoc.v:179680$11139 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11056 $4\reg$next[3:0]$11060 - attribute \src "libresoc.v:177867.5-177867.29" + assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179681.5-179681.29" switch \initial - attribute \src "libresoc.v:177867.9-177867.17" + attribute \src "libresoc.v:179681.9-179681.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11057 \dest12__data_i - case - assign $1\reg$next[3:0]$11057 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11058 \dest22__data_i - case - assign $2\reg$next[3:0]$11058 $1\reg$next[3:0]$11057 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11059 \w2__data_i + assign { } { } + assign $1\r22__data_o$next[3:0]$11141 $5\r22__data_o$next[3:0]$11145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11142 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11142 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11143 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11143 $2\r22__data_o$next[3:0]$11142 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11144 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11144 $3\r22__data_o$next[3:0]$11143 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11145 \reg + case + assign $5\r22__data_o$next[3:0]$11145 $4\r22__data_o$next[3:0]$11144 + end case - assign $3\reg$next[3:0]$11059 $2\reg$next[3:0]$11058 + assign $1\r22__data_o$next[3:0]$11141 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11060 4'0000 + assign $6\r22__data_o$next[3:0]$11146 4'0000 case - assign $4\reg$next[3:0]$11060 $3\reg$next[3:0]$11059 + assign $6\r22__data_o$next[3:0]$11146 $1\r22__data_o$next[3:0]$11141 end sync always - update \reg$next $0\reg$next[3:0]$11056 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 end - attribute \src "libresoc.v:177893.3-177932.6" - process $proc$libresoc.v:177893$11061 - assign { } { } + attribute \src "libresoc.v:179720.3-179749.6" + process $proc$libresoc.v:179720$11147 assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11062 $6\src22__data_o$next[3:0]$11068 - attribute \src "libresoc.v:177894.5-177894.29" + assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179721.5-179721.29" switch \initial - attribute \src "libresoc.v:177894.9-177894.17" + attribute \src "libresoc.v:179721.9-179721.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11063 $5\src22__data_o$next[3:0]$11067 + assign $1\wr_detect$16[0:0]$11149 $4\wr_detect$16[0:0]$11152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11064 \dest12__data_i + assign $2\wr_detect$16[0:0]$11150 1'1 case - assign $2\src22__data_o$next[3:0]$11064 4'0000 + assign $2\wr_detect$16[0:0]$11150 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11065 \dest22__data_i + assign $3\wr_detect$16[0:0]$11151 1'1 case - assign $3\src22__data_o$next[3:0]$11065 $2\src22__data_o$next[3:0]$11064 + assign $3\wr_detect$16[0:0]$11151 $2\wr_detect$16[0:0]$11150 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11066 \w2__data_i + assign $4\wr_detect$16[0:0]$11152 1'1 case - assign $4\src22__data_o$next[3:0]$11066 $3\src22__data_o$next[3:0]$11065 + assign $4\wr_detect$16[0:0]$11152 $3\wr_detect$16[0:0]$11151 + end + case + assign $1\wr_detect$16[0:0]$11149 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11148 + end + attribute \src "libresoc.v:179750.3-179776.6" + process $proc$libresoc.v:179750$11153 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179751.5-179751.29" + switch \initial + attribute \src "libresoc.v:179751.9-179751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11155 \dest12__data_i + case + assign $1\reg$next[3:0]$11155 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11156 \dest22__data_i + case + assign $2\reg$next[3:0]$11156 $1\reg$next[3:0]$11155 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11157 \w2__data_i + case + assign $3\reg$next[3:0]$11157 $2\reg$next[3:0]$11156 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11158 4'0000 + case + assign $4\reg$next[3:0]$11158 $3\reg$next[3:0]$11157 + end + sync always + update \reg$next $0\reg$next[3:0]$11154 + end + attribute \src "libresoc.v:179777.3-179816.6" + process $proc$libresoc.v:179777$11159 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179778.5-179778.29" + switch \initial + attribute \src "libresoc.v:179778.9-179778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$11161 $5\src12__data_o$next[3:0]$11165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$11162 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$11162 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$11163 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$11163 $2\src12__data_o$next[3:0]$11162 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$11164 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$11164 $3\src12__data_o$next[3:0]$11163 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11067 \reg + assign $5\src12__data_o$next[3:0]$11165 \reg case - assign $5\src22__data_o$next[3:0]$11067 $4\src22__data_o$next[3:0]$11066 + assign $5\src12__data_o$next[3:0]$11165 $4\src12__data_o$next[3:0]$11164 end case - assign $1\src22__data_o$next[3:0]$11063 4'0000 + assign $1\src12__data_o$next[3:0]$11161 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11068 4'0000 + assign $6\src12__data_o$next[3:0]$11166 4'0000 case - assign $6\src22__data_o$next[3:0]$11068 $1\src22__data_o$next[3:0]$11063 + assign $6\src12__data_o$next[3:0]$11166 $1\src12__data_o$next[3:0]$11161 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11062 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 end - attribute \src "libresoc.v:177933.3-177962.6" - process $proc$libresoc.v:177933$11069 + attribute \src "libresoc.v:179817.3-179846.6" + process $proc$libresoc.v:179817$11167 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11070 $1\wr_detect$4[0:0]$11071 - attribute \src "libresoc.v:177934.5-177934.29" + assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179818.5-179818.29" switch \initial - attribute \src "libresoc.v:177934.9-177934.17" + attribute \src "libresoc.v:179818.9-179818.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11071 $4\wr_detect$4[0:0]$11074 + assign $1\wr_detect$4[0:0]$11169 $4\wr_detect$4[0:0]$11172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11072 1'1 + assign $2\wr_detect$4[0:0]$11170 1'1 case - assign $2\wr_detect$4[0:0]$11072 1'0 + assign $2\wr_detect$4[0:0]$11170 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11073 1'1 + assign $3\wr_detect$4[0:0]$11171 1'1 case - assign $3\wr_detect$4[0:0]$11073 $2\wr_detect$4[0:0]$11072 + assign $3\wr_detect$4[0:0]$11171 $2\wr_detect$4[0:0]$11170 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11074 1'1 + assign $4\wr_detect$4[0:0]$11172 1'1 case - assign $4\wr_detect$4[0:0]$11074 $3\wr_detect$4[0:0]$11073 + assign $4\wr_detect$4[0:0]$11172 $3\wr_detect$4[0:0]$11171 end case - assign $1\wr_detect$4[0:0]$11071 1'0 + assign $1\wr_detect$4[0:0]$11169 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11070 + update \wr_detect$4 $0\wr_detect$4[0:0]$11168 end - attribute \src "libresoc.v:177963.3-178002.6" - process $proc$libresoc.v:177963$11075 + attribute \src "libresoc.v:179847.3-179886.6" + process $proc$libresoc.v:179847$11173 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11076 $6\src32__data_o$next[3:0]$11082 - attribute \src "libresoc.v:177964.5-177964.29" + assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179848.5-179848.29" switch \initial - attribute \src "libresoc.v:177964.9-177964.17" + attribute \src "libresoc.v:179848.9-179848.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11077 $5\src32__data_o$next[3:0]$11081 + assign $1\src22__data_o$next[3:0]$11175 $5\src22__data_o$next[3:0]$11179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11078 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11176 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11078 4'0000 + assign $2\src22__data_o$next[3:0]$11176 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11079 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11177 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11079 $2\src32__data_o$next[3:0]$11078 + assign $3\src22__data_o$next[3:0]$11177 $2\src22__data_o$next[3:0]$11176 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11080 \w2__data_i + assign $4\src22__data_o$next[3:0]$11178 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11080 $3\src32__data_o$next[3:0]$11079 + assign $4\src22__data_o$next[3:0]$11178 $3\src22__data_o$next[3:0]$11177 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11081 \reg + assign $5\src22__data_o$next[3:0]$11179 \reg case - assign $5\src32__data_o$next[3:0]$11081 $4\src32__data_o$next[3:0]$11080 + assign $5\src22__data_o$next[3:0]$11179 $4\src22__data_o$next[3:0]$11178 end case - assign $1\src32__data_o$next[3:0]$11077 4'0000 + assign $1\src22__data_o$next[3:0]$11175 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11082 4'0000 + assign $6\src22__data_o$next[3:0]$11180 4'0000 case - assign $6\src32__data_o$next[3:0]$11082 $1\src32__data_o$next[3:0]$11077 + assign $6\src22__data_o$next[3:0]$11180 $1\src22__data_o$next[3:0]$11175 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11076 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 end - attribute \src "libresoc.v:178003.3-178032.6" - process $proc$libresoc.v:178003$11083 + attribute \src "libresoc.v:179887.3-179916.6" + process $proc$libresoc.v:179887$11181 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11084 $1\wr_detect$7[0:0]$11085 - attribute \src "libresoc.v:178004.5-178004.29" + assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179888.5-179888.29" switch \initial - attribute \src "libresoc.v:178004.9-178004.17" + attribute \src "libresoc.v:179888.9-179888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11085 $4\wr_detect$7[0:0]$11088 + assign $1\wr_detect$7[0:0]$11183 $4\wr_detect$7[0:0]$11186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11086 1'1 + assign $2\wr_detect$7[0:0]$11184 1'1 case - assign $2\wr_detect$7[0:0]$11086 1'0 + assign $2\wr_detect$7[0:0]$11184 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11087 1'1 + assign $3\wr_detect$7[0:0]$11185 1'1 case - assign $3\wr_detect$7[0:0]$11087 $2\wr_detect$7[0:0]$11086 + assign $3\wr_detect$7[0:0]$11185 $2\wr_detect$7[0:0]$11184 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11088 1'1 + assign $4\wr_detect$7[0:0]$11186 1'1 case - assign $4\wr_detect$7[0:0]$11088 $3\wr_detect$7[0:0]$11087 + assign $4\wr_detect$7[0:0]$11186 $3\wr_detect$7[0:0]$11185 end case - assign $1\wr_detect$7[0:0]$11085 1'0 + assign $1\wr_detect$7[0:0]$11183 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11084 + update \wr_detect$7 $0\wr_detect$7[0:0]$11182 end - attribute \src "libresoc.v:178033.3-178072.6" - process $proc$libresoc.v:178033$11089 + attribute \src "libresoc.v:179917.3-179956.6" + process $proc$libresoc.v:179917$11187 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11090 $6\r2__data_o$next[3:0]$11096 - attribute \src "libresoc.v:178034.5-178034.29" + assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179918.5-179918.29" switch \initial - attribute \src "libresoc.v:178034.9-178034.17" + attribute \src "libresoc.v:179918.9-179918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11091 $5\r2__data_o$next[3:0]$11095 + assign $1\src32__data_o$next[3:0]$11189 $5\src32__data_o$next[3:0]$11193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11092 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11190 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11092 4'0000 + assign $2\src32__data_o$next[3:0]$11190 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11093 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11191 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11093 $2\r2__data_o$next[3:0]$11092 + assign $3\src32__data_o$next[3:0]$11191 $2\src32__data_o$next[3:0]$11190 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11094 \w2__data_i + assign $4\src32__data_o$next[3:0]$11192 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11094 $3\r2__data_o$next[3:0]$11093 + assign $4\src32__data_o$next[3:0]$11192 $3\src32__data_o$next[3:0]$11191 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11095 \reg + assign $5\src32__data_o$next[3:0]$11193 \reg case - assign $5\r2__data_o$next[3:0]$11095 $4\r2__data_o$next[3:0]$11094 + assign $5\src32__data_o$next[3:0]$11193 $4\src32__data_o$next[3:0]$11192 end case - assign $1\r2__data_o$next[3:0]$11091 4'0000 + assign $1\src32__data_o$next[3:0]$11189 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11096 4'0000 + assign $6\src32__data_o$next[3:0]$11194 4'0000 case - assign $6\r2__data_o$next[3:0]$11096 $1\r2__data_o$next[3:0]$11091 + assign $6\src32__data_o$next[3:0]$11194 $1\src32__data_o$next[3:0]$11189 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11090 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 end - attribute \src "libresoc.v:178073.3-178102.6" - process $proc$libresoc.v:178073$11097 + attribute \src "libresoc.v:179957.3-179986.6" + process $proc$libresoc.v:179957$11195 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11098 $1\wr_detect$10[0:0]$11099 - attribute \src "libresoc.v:178074.5-178074.29" + assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:179958.5-179958.29" switch \initial - attribute \src "libresoc.v:178074.9-178074.17" + attribute \src "libresoc.v:179958.9-179958.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11099 $4\wr_detect$10[0:0]$11102 + assign $1\wr_detect$10[0:0]$11197 $4\wr_detect$10[0:0]$11200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11100 1'1 + assign $2\wr_detect$10[0:0]$11198 1'1 case - assign $2\wr_detect$10[0:0]$11100 1'0 + assign $2\wr_detect$10[0:0]$11198 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11101 1'1 + assign $3\wr_detect$10[0:0]$11199 1'1 case - assign $3\wr_detect$10[0:0]$11101 $2\wr_detect$10[0:0]$11100 + assign $3\wr_detect$10[0:0]$11199 $2\wr_detect$10[0:0]$11198 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11102 1'1 + assign $4\wr_detect$10[0:0]$11200 1'1 case - assign $4\wr_detect$10[0:0]$11102 $3\wr_detect$10[0:0]$11101 + assign $4\wr_detect$10[0:0]$11200 $3\wr_detect$10[0:0]$11199 end case - assign $1\wr_detect$10[0:0]$11099 1'0 + assign $1\wr_detect$10[0:0]$11197 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11098 + update \wr_detect$10 $0\wr_detect$10[0:0]$11196 end - attribute \src "libresoc.v:178103.3-178142.6" - process $proc$libresoc.v:178103$11103 + attribute \src "libresoc.v:179987.3-180026.6" + process $proc$libresoc.v:179987$11201 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11104 $6\r22__data_o$next[3:0]$11110 - attribute \src "libresoc.v:178104.5-178104.29" + assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179988.5-179988.29" switch \initial - attribute \src "libresoc.v:178104.9-178104.17" + attribute \src "libresoc.v:179988.9-179988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11105 $5\r22__data_o$next[3:0]$11109 + assign $1\r2__data_o$next[3:0]$11203 $5\r2__data_o$next[3:0]$11207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11106 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11204 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11106 4'0000 + assign $2\r2__data_o$next[3:0]$11204 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11107 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11205 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11107 $2\r22__data_o$next[3:0]$11106 + assign $3\r2__data_o$next[3:0]$11205 $2\r2__data_o$next[3:0]$11204 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11108 \w2__data_i + assign $4\r2__data_o$next[3:0]$11206 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11108 $3\r22__data_o$next[3:0]$11107 + assign $4\r2__data_o$next[3:0]$11206 $3\r2__data_o$next[3:0]$11205 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11109 \reg + assign $5\r2__data_o$next[3:0]$11207 \reg case - assign $5\r22__data_o$next[3:0]$11109 $4\r22__data_o$next[3:0]$11108 + assign $5\r2__data_o$next[3:0]$11207 $4\r2__data_o$next[3:0]$11206 end case - assign $1\r22__data_o$next[3:0]$11105 4'0000 + assign $1\r2__data_o$next[3:0]$11203 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11110 4'0000 + assign $6\r2__data_o$next[3:0]$11208 4'0000 case - assign $6\r22__data_o$next[3:0]$11110 $1\r22__data_o$next[3:0]$11105 + assign $6\r2__data_o$next[3:0]$11208 $1\r2__data_o$next[3:0]$11203 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11104 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 end - attribute \src "libresoc.v:178143.3-178172.6" - process $proc$libresoc.v:178143$11111 + attribute \src "libresoc.v:180027.3-180056.6" + process $proc$libresoc.v:180027$11209 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11112 $1\wr_detect$13[0:0]$11113 - attribute \src "libresoc.v:178144.5-178144.29" + assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:180028.5-180028.29" switch \initial - attribute \src "libresoc.v:178144.9-178144.17" + attribute \src "libresoc.v:180028.9-180028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11113 $4\wr_detect$13[0:0]$11116 + assign $1\wr_detect$13[0:0]$11211 $4\wr_detect$13[0:0]$11214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11114 1'1 + assign $2\wr_detect$13[0:0]$11212 1'1 case - assign $2\wr_detect$13[0:0]$11114 1'0 + assign $2\wr_detect$13[0:0]$11212 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11115 1'1 + assign $3\wr_detect$13[0:0]$11213 1'1 case - assign $3\wr_detect$13[0:0]$11115 $2\wr_detect$13[0:0]$11114 + assign $3\wr_detect$13[0:0]$11213 $2\wr_detect$13[0:0]$11212 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11116 1'1 + assign $4\wr_detect$13[0:0]$11214 1'1 case - assign $4\wr_detect$13[0:0]$11116 $3\wr_detect$13[0:0]$11115 + assign $4\wr_detect$13[0:0]$11214 $3\wr_detect$13[0:0]$11213 end case - assign $1\wr_detect$13[0:0]$11113 1'0 + assign $1\wr_detect$13[0:0]$11211 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11112 + update \wr_detect$13 $0\wr_detect$13[0:0]$11210 end - connect \$9 $not$libresoc.v:177779$11035_Y - connect \$12 $not$libresoc.v:177780$11036_Y - connect \$1 $not$libresoc.v:177781$11037_Y - connect \$3 $not$libresoc.v:177782$11038_Y - connect \$6 $not$libresoc.v:177783$11039_Y + connect \$9 $not$libresoc.v:179590$11117_Y + connect \$12 $not$libresoc.v:179591$11118_Y + connect \$15 $not$libresoc.v:179592$11119_Y + connect \$1 $not$libresoc.v:179593$11120_Y + connect \$3 $not$libresoc.v:179594$11121_Y + connect \$6 $not$libresoc.v:179595$11122_Y end -attribute \src "libresoc.v:178177.1-178622.10" +attribute \src "libresoc.v:180061.1-180506.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:178178.7-178178.20" + attribute \src "libresoc.v:180062.7-180062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $0\r2__data_o$next[1:0]$11176 - attribute \src "libresoc.v:178253.3-178254.37" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $0\r2__data_o$next[1:0]$11275 + attribute \src "libresoc.v:180137.3-180138.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $0\reg$next[1:0]$11192 - attribute \src "libresoc.v:178251.3-178252.25" + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $0\reg$next[1:0]$11291 + attribute \src "libresoc.v:180135.3-180136.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $0\src12__data_o$next[1:0]$11134 - attribute \src "libresoc.v:178259.3-178260.43" + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $0\src12__data_o$next[1:0]$11233 + attribute \src "libresoc.v:180143.3-180144.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $0\src22__data_o$next[1:0]$11144 - attribute \src "libresoc.v:178257.3-178258.43" + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $0\src22__data_o$next[1:0]$11243 + attribute \src "libresoc.v:180141.3-180142.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $0\src32__data_o$next[1:0]$11160 - attribute \src "libresoc.v:178255.3-178256.43" + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $0\src32__data_o$next[1:0]$11259 + attribute \src "libresoc.v:180139.3-180140.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:178553.3-178588.6" - wire $0\wr_detect$10[0:0]$11185 - attribute \src "libresoc.v:178389.3-178424.6" - wire $0\wr_detect$4[0:0]$11153 - attribute \src "libresoc.v:178471.3-178506.6" - wire $0\wr_detect$7[0:0]$11169 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180437.3-180472.6" + wire $0\wr_detect$10[0:0]$11284 + attribute \src "libresoc.v:180273.3-180308.6" + wire $0\wr_detect$4[0:0]$11252 + attribute \src "libresoc.v:180355.3-180390.6" + wire $0\wr_detect$7[0:0]$11268 + attribute \src "libresoc.v:180191.3-180226.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $1\r2__data_o$next[1:0]$11177 - attribute \src "libresoc.v:178205.13-178205.30" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $1\r2__data_o$next[1:0]$11276 + attribute \src "libresoc.v:180089.13-180089.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $1\reg$next[1:0]$11193 - attribute \src "libresoc.v:178211.13-178211.25" + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $1\reg$next[1:0]$11292 + attribute \src "libresoc.v:180095.13-180095.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $1\src12__data_o$next[1:0]$11135 - attribute \src "libresoc.v:178216.13-178216.33" + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $1\src12__data_o$next[1:0]$11234 + attribute \src "libresoc.v:180100.13-180100.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $1\src22__data_o$next[1:0]$11145 - attribute \src "libresoc.v:178223.13-178223.33" + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $1\src22__data_o$next[1:0]$11244 + attribute \src "libresoc.v:180107.13-180107.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $1\src32__data_o$next[1:0]$11161 - attribute \src "libresoc.v:178230.13-178230.33" + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $1\src32__data_o$next[1:0]$11260 + attribute \src "libresoc.v:180114.13-180114.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:178553.3-178588.6" - wire $1\wr_detect$10[0:0]$11186 - attribute \src "libresoc.v:178389.3-178424.6" - wire $1\wr_detect$4[0:0]$11154 - attribute \src "libresoc.v:178471.3-178506.6" - wire $1\wr_detect$7[0:0]$11170 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180437.3-180472.6" + wire $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180273.3-180308.6" + wire $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180355.3-180390.6" + wire $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180191.3-180226.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $2\r2__data_o$next[1:0]$11178 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $2\reg$next[1:0]$11194 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $2\src12__data_o$next[1:0]$11136 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $2\src22__data_o$next[1:0]$11146 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $2\src32__data_o$next[1:0]$11162 - attribute \src "libresoc.v:178553.3-178588.6" - wire $2\wr_detect$10[0:0]$11187 - attribute \src "libresoc.v:178389.3-178424.6" - wire $2\wr_detect$4[0:0]$11155 - attribute \src "libresoc.v:178471.3-178506.6" - wire $2\wr_detect$7[0:0]$11171 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $2\r2__data_o$next[1:0]$11277 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $2\reg$next[1:0]$11293 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $2\src12__data_o$next[1:0]$11235 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $2\src22__data_o$next[1:0]$11245 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $2\src32__data_o$next[1:0]$11261 + attribute \src "libresoc.v:180437.3-180472.6" + wire $2\wr_detect$10[0:0]$11286 + attribute \src "libresoc.v:180273.3-180308.6" + wire $2\wr_detect$4[0:0]$11254 + attribute \src "libresoc.v:180355.3-180390.6" + wire $2\wr_detect$7[0:0]$11270 + attribute \src "libresoc.v:180191.3-180226.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $3\r2__data_o$next[1:0]$11179 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $3\reg$next[1:0]$11195 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $3\src12__data_o$next[1:0]$11137 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $3\src22__data_o$next[1:0]$11147 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $3\src32__data_o$next[1:0]$11163 - attribute \src "libresoc.v:178553.3-178588.6" - wire $3\wr_detect$10[0:0]$11188 - attribute \src "libresoc.v:178389.3-178424.6" - wire $3\wr_detect$4[0:0]$11156 - attribute \src "libresoc.v:178471.3-178506.6" - wire $3\wr_detect$7[0:0]$11172 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $3\r2__data_o$next[1:0]$11278 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $3\reg$next[1:0]$11294 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $3\src12__data_o$next[1:0]$11236 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $3\src22__data_o$next[1:0]$11246 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $3\src32__data_o$next[1:0]$11262 + attribute \src "libresoc.v:180437.3-180472.6" + wire $3\wr_detect$10[0:0]$11287 + attribute \src "libresoc.v:180273.3-180308.6" + wire $3\wr_detect$4[0:0]$11255 + attribute \src "libresoc.v:180355.3-180390.6" + wire $3\wr_detect$7[0:0]$11271 + attribute \src "libresoc.v:180191.3-180226.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $4\r2__data_o$next[1:0]$11180 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $4\reg$next[1:0]$11196 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $4\src12__data_o$next[1:0]$11138 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $4\src22__data_o$next[1:0]$11148 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $4\src32__data_o$next[1:0]$11164 - attribute \src "libresoc.v:178553.3-178588.6" - wire $4\wr_detect$10[0:0]$11189 - attribute \src "libresoc.v:178389.3-178424.6" - wire $4\wr_detect$4[0:0]$11157 - attribute \src "libresoc.v:178471.3-178506.6" - wire $4\wr_detect$7[0:0]$11173 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $4\r2__data_o$next[1:0]$11279 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $4\reg$next[1:0]$11295 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $4\src12__data_o$next[1:0]$11237 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $4\src22__data_o$next[1:0]$11247 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $4\src32__data_o$next[1:0]$11263 + attribute \src "libresoc.v:180437.3-180472.6" + wire $4\wr_detect$10[0:0]$11288 + attribute \src "libresoc.v:180273.3-180308.6" + wire $4\wr_detect$4[0:0]$11256 + attribute \src "libresoc.v:180355.3-180390.6" + wire $4\wr_detect$7[0:0]$11272 + attribute \src "libresoc.v:180191.3-180226.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $5\r2__data_o$next[1:0]$11181 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $5\reg$next[1:0]$11197 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $5\src12__data_o$next[1:0]$11139 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $5\src22__data_o$next[1:0]$11149 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $5\src32__data_o$next[1:0]$11165 - attribute \src "libresoc.v:178553.3-178588.6" - wire $5\wr_detect$10[0:0]$11190 - attribute \src "libresoc.v:178389.3-178424.6" - wire $5\wr_detect$4[0:0]$11158 - attribute \src "libresoc.v:178471.3-178506.6" - wire $5\wr_detect$7[0:0]$11174 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $5\r2__data_o$next[1:0]$11280 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $5\src12__data_o$next[1:0]$11238 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $5\src22__data_o$next[1:0]$11248 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $5\src32__data_o$next[1:0]$11264 + attribute \src "libresoc.v:180437.3-180472.6" + wire $5\wr_detect$10[0:0]$11289 + attribute \src "libresoc.v:180273.3-180308.6" + wire $5\wr_detect$4[0:0]$11257 + attribute \src "libresoc.v:180355.3-180390.6" + wire $5\wr_detect$7[0:0]$11273 + attribute \src "libresoc.v:180191.3-180226.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $6\r2__data_o$next[1:0]$11182 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $6\src12__data_o$next[1:0]$11140 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $6\src22__data_o$next[1:0]$11150 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $6\src32__data_o$next[1:0]$11166 - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $7\r2__data_o$next[1:0]$11183 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $7\src12__data_o$next[1:0]$11141 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $7\src22__data_o$next[1:0]$11151 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $7\src32__data_o$next[1:0]$11167 - attribute \src "libresoc.v:178247.17-178247.104" - wire $not$libresoc.v:178247$11124_Y - attribute \src "libresoc.v:178248.17-178248.100" - wire $not$libresoc.v:178248$11125_Y - attribute \src "libresoc.v:178249.17-178249.103" - wire $not$libresoc.v:178249$11126_Y - attribute \src "libresoc.v:178250.17-178250.103" - wire $not$libresoc.v:178250$11127_Y + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $6\r2__data_o$next[1:0]$11281 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $6\src12__data_o$next[1:0]$11239 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $6\src22__data_o$next[1:0]$11249 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $6\src32__data_o$next[1:0]$11265 + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180131.17-180131.104" + wire $not$libresoc.v:180131$11223_Y + attribute \src "libresoc.v:180132.17-180132.100" + wire $not$libresoc.v:180132$11224_Y + attribute \src "libresoc.v:180133.17-180133.103" + wire $not$libresoc.v:180133$11225_Y + attribute \src "libresoc.v:180134.17-180134.103" + wire $not$libresoc.v:180134$11226_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367215,9 +370279,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -367231,7 +370295,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:178178.7-178178.15" + attribute \src "libresoc.v:180062.7-180062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -367274,129 +370338,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178247$11124 + cell $not $not$libresoc.v:180131$11223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178247$11124_Y + connect \Y $not$libresoc.v:180131$11223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178248$11125 + cell $not $not$libresoc.v:180132$11224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178248$11125_Y + connect \Y $not$libresoc.v:180132$11224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178249$11126 + cell $not $not$libresoc.v:180133$11225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178249$11126_Y + connect \Y $not$libresoc.v:180133$11225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178250$11127 + cell $not $not$libresoc.v:180134$11226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178250$11127_Y + connect \Y $not$libresoc.v:180134$11226_Y end - attribute \src "libresoc.v:178178.7-178178.20" - process $proc$libresoc.v:178178$11198 + attribute \src "libresoc.v:180062.7-180062.20" + process $proc$libresoc.v:180062$11297 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178205.13-178205.30" - process $proc$libresoc.v:178205$11199 + attribute \src "libresoc.v:180089.13-180089.30" + process $proc$libresoc.v:180089$11298 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:178211.13-178211.25" - process $proc$libresoc.v:178211$11200 + attribute \src "libresoc.v:180095.13-180095.25" + process $proc$libresoc.v:180095$11299 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178216.13-178216.33" - process $proc$libresoc.v:178216$11201 + attribute \src "libresoc.v:180100.13-180100.33" + process $proc$libresoc.v:180100$11300 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:178223.13-178223.33" - process $proc$libresoc.v:178223$11202 + attribute \src "libresoc.v:180107.13-180107.33" + process $proc$libresoc.v:180107$11301 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:178230.13-178230.33" - process $proc$libresoc.v:178230$11203 + attribute \src "libresoc.v:180114.13-180114.33" + process $proc$libresoc.v:180114$11302 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:178251.3-178252.25" - process $proc$libresoc.v:178251$11128 + attribute \src "libresoc.v:180135.3-180136.25" + process $proc$libresoc.v:180135$11227 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178253.3-178254.37" - process $proc$libresoc.v:178253$11129 + attribute \src "libresoc.v:180137.3-180138.37" + process $proc$libresoc.v:180137$11228 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:178255.3-178256.43" - process $proc$libresoc.v:178255$11130 + attribute \src "libresoc.v:180139.3-180140.43" + process $proc$libresoc.v:180139$11229 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:178257.3-178258.43" - process $proc$libresoc.v:178257$11131 + attribute \src "libresoc.v:180141.3-180142.43" + process $proc$libresoc.v:180141$11230 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:178259.3-178260.43" - process $proc$libresoc.v:178259$11132 + attribute \src "libresoc.v:180143.3-180144.43" + process $proc$libresoc.v:180143$11231 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:178261.3-178306.6" - process $proc$libresoc.v:178261$11133 + attribute \src "libresoc.v:180145.3-180190.6" + process $proc$libresoc.v:180145$11232 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11134 $7\src12__data_o$next[1:0]$11141 - attribute \src "libresoc.v:178262.5-178262.29" + assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180146.5-180146.29" switch \initial - attribute \src "libresoc.v:178262.9-178262.17" + attribute \src "libresoc.v:180146.9-180146.17" case 1'1 case end @@ -367409,75 +370473,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11135 $6\src12__data_o$next[1:0]$11140 + assign $1\src12__data_o$next[1:0]$11234 $6\src12__data_o$next[1:0]$11239 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11136 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11235 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11136 2'00 + assign $2\src12__data_o$next[1:0]$11235 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11137 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11236 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11137 $2\src12__data_o$next[1:0]$11136 + assign $3\src12__data_o$next[1:0]$11236 $2\src12__data_o$next[1:0]$11235 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11138 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11237 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11138 $3\src12__data_o$next[1:0]$11137 + assign $4\src12__data_o$next[1:0]$11237 $3\src12__data_o$next[1:0]$11236 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11139 \w2__data_i + assign $5\src12__data_o$next[1:0]$11238 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11139 $4\src12__data_o$next[1:0]$11138 + assign $5\src12__data_o$next[1:0]$11238 $4\src12__data_o$next[1:0]$11237 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11140 \reg + assign $6\src12__data_o$next[1:0]$11239 \reg case - assign $6\src12__data_o$next[1:0]$11140 $5\src12__data_o$next[1:0]$11139 + assign $6\src12__data_o$next[1:0]$11239 $5\src12__data_o$next[1:0]$11238 end case - assign $1\src12__data_o$next[1:0]$11135 2'00 + assign $1\src12__data_o$next[1:0]$11234 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11141 2'00 + assign $7\src12__data_o$next[1:0]$11240 2'00 case - assign $7\src12__data_o$next[1:0]$11141 $1\src12__data_o$next[1:0]$11135 + assign $7\src12__data_o$next[1:0]$11240 $1\src12__data_o$next[1:0]$11234 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11134 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 end - attribute \src "libresoc.v:178307.3-178342.6" - process $proc$libresoc.v:178307$11142 + attribute \src "libresoc.v:180191.3-180226.6" + process $proc$libresoc.v:180191$11241 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178308.5-178308.29" + attribute \src "libresoc.v:180192.5-180192.29" switch \initial - attribute \src "libresoc.v:178308.9-178308.17" + attribute \src "libresoc.v:180192.9-180192.17" case 1'1 case end @@ -367533,15 +370597,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178343.3-178388.6" - process $proc$libresoc.v:178343$11143 + attribute \src "libresoc.v:180227.3-180272.6" + process $proc$libresoc.v:180227$11242 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11144 $7\src22__data_o$next[1:0]$11151 - attribute \src "libresoc.v:178344.5-178344.29" + assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180228.5-180228.29" switch \initial - attribute \src "libresoc.v:178344.9-178344.17" + attribute \src "libresoc.v:180228.9-180228.17" case 1'1 case end @@ -367554,75 +370618,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11145 $6\src22__data_o$next[1:0]$11150 + assign $1\src22__data_o$next[1:0]$11244 $6\src22__data_o$next[1:0]$11249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11146 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11245 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11146 2'00 + assign $2\src22__data_o$next[1:0]$11245 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11147 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11246 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11147 $2\src22__data_o$next[1:0]$11146 + assign $3\src22__data_o$next[1:0]$11246 $2\src22__data_o$next[1:0]$11245 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11148 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11247 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11148 $3\src22__data_o$next[1:0]$11147 + assign $4\src22__data_o$next[1:0]$11247 $3\src22__data_o$next[1:0]$11246 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11149 \w2__data_i + assign $5\src22__data_o$next[1:0]$11248 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11149 $4\src22__data_o$next[1:0]$11148 + assign $5\src22__data_o$next[1:0]$11248 $4\src22__data_o$next[1:0]$11247 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11150 \reg + assign $6\src22__data_o$next[1:0]$11249 \reg case - assign $6\src22__data_o$next[1:0]$11150 $5\src22__data_o$next[1:0]$11149 + assign $6\src22__data_o$next[1:0]$11249 $5\src22__data_o$next[1:0]$11248 end case - assign $1\src22__data_o$next[1:0]$11145 2'00 + assign $1\src22__data_o$next[1:0]$11244 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11151 2'00 + assign $7\src22__data_o$next[1:0]$11250 2'00 case - assign $7\src22__data_o$next[1:0]$11151 $1\src22__data_o$next[1:0]$11145 + assign $7\src22__data_o$next[1:0]$11250 $1\src22__data_o$next[1:0]$11244 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11144 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 end - attribute \src "libresoc.v:178389.3-178424.6" - process $proc$libresoc.v:178389$11152 + attribute \src "libresoc.v:180273.3-180308.6" + process $proc$libresoc.v:180273$11251 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11153 $1\wr_detect$4[0:0]$11154 - attribute \src "libresoc.v:178390.5-178390.29" + assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180274.5-180274.29" switch \initial - attribute \src "libresoc.v:178390.9-178390.17" + attribute \src "libresoc.v:180274.9-180274.17" case 1'1 case end @@ -367635,58 +370699,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11154 $5\wr_detect$4[0:0]$11158 + assign $1\wr_detect$4[0:0]$11253 $5\wr_detect$4[0:0]$11257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11155 1'1 + assign $2\wr_detect$4[0:0]$11254 1'1 case - assign $2\wr_detect$4[0:0]$11155 1'0 + assign $2\wr_detect$4[0:0]$11254 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11156 1'1 + assign $3\wr_detect$4[0:0]$11255 1'1 case - assign $3\wr_detect$4[0:0]$11156 $2\wr_detect$4[0:0]$11155 + assign $3\wr_detect$4[0:0]$11255 $2\wr_detect$4[0:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11157 1'1 + assign $4\wr_detect$4[0:0]$11256 1'1 case - assign $4\wr_detect$4[0:0]$11157 $3\wr_detect$4[0:0]$11156 + assign $4\wr_detect$4[0:0]$11256 $3\wr_detect$4[0:0]$11255 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11158 1'1 + assign $5\wr_detect$4[0:0]$11257 1'1 case - assign $5\wr_detect$4[0:0]$11158 $4\wr_detect$4[0:0]$11157 + assign $5\wr_detect$4[0:0]$11257 $4\wr_detect$4[0:0]$11256 end case - assign $1\wr_detect$4[0:0]$11154 1'0 + assign $1\wr_detect$4[0:0]$11253 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11153 + update \wr_detect$4 $0\wr_detect$4[0:0]$11252 end - attribute \src "libresoc.v:178425.3-178470.6" - process $proc$libresoc.v:178425$11159 + attribute \src "libresoc.v:180309.3-180354.6" + process $proc$libresoc.v:180309$11258 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11160 $7\src32__data_o$next[1:0]$11167 - attribute \src "libresoc.v:178426.5-178426.29" + assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180310.5-180310.29" switch \initial - attribute \src "libresoc.v:178426.9-178426.17" + attribute \src "libresoc.v:180310.9-180310.17" case 1'1 case end @@ -367699,75 +370763,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11161 $6\src32__data_o$next[1:0]$11166 + assign $1\src32__data_o$next[1:0]$11260 $6\src32__data_o$next[1:0]$11265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11162 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11261 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11162 2'00 + assign $2\src32__data_o$next[1:0]$11261 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11163 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11262 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11163 $2\src32__data_o$next[1:0]$11162 + assign $3\src32__data_o$next[1:0]$11262 $2\src32__data_o$next[1:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11164 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11263 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11164 $3\src32__data_o$next[1:0]$11163 + assign $4\src32__data_o$next[1:0]$11263 $3\src32__data_o$next[1:0]$11262 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11165 \w2__data_i + assign $5\src32__data_o$next[1:0]$11264 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11165 $4\src32__data_o$next[1:0]$11164 + assign $5\src32__data_o$next[1:0]$11264 $4\src32__data_o$next[1:0]$11263 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11166 \reg + assign $6\src32__data_o$next[1:0]$11265 \reg case - assign $6\src32__data_o$next[1:0]$11166 $5\src32__data_o$next[1:0]$11165 + assign $6\src32__data_o$next[1:0]$11265 $5\src32__data_o$next[1:0]$11264 end case - assign $1\src32__data_o$next[1:0]$11161 2'00 + assign $1\src32__data_o$next[1:0]$11260 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11167 2'00 + assign $7\src32__data_o$next[1:0]$11266 2'00 case - assign $7\src32__data_o$next[1:0]$11167 $1\src32__data_o$next[1:0]$11161 + assign $7\src32__data_o$next[1:0]$11266 $1\src32__data_o$next[1:0]$11260 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11160 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 end - attribute \src "libresoc.v:178471.3-178506.6" - process $proc$libresoc.v:178471$11168 + attribute \src "libresoc.v:180355.3-180390.6" + process $proc$libresoc.v:180355$11267 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11169 $1\wr_detect$7[0:0]$11170 - attribute \src "libresoc.v:178472.5-178472.29" + assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180356.5-180356.29" switch \initial - attribute \src "libresoc.v:178472.9-178472.17" + attribute \src "libresoc.v:180356.9-180356.17" case 1'1 case end @@ -367780,58 +370844,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11170 $5\wr_detect$7[0:0]$11174 + assign $1\wr_detect$7[0:0]$11269 $5\wr_detect$7[0:0]$11273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11171 1'1 + assign $2\wr_detect$7[0:0]$11270 1'1 case - assign $2\wr_detect$7[0:0]$11171 1'0 + assign $2\wr_detect$7[0:0]$11270 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11172 1'1 + assign $3\wr_detect$7[0:0]$11271 1'1 case - assign $3\wr_detect$7[0:0]$11172 $2\wr_detect$7[0:0]$11171 + assign $3\wr_detect$7[0:0]$11271 $2\wr_detect$7[0:0]$11270 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11173 1'1 + assign $4\wr_detect$7[0:0]$11272 1'1 case - assign $4\wr_detect$7[0:0]$11173 $3\wr_detect$7[0:0]$11172 + assign $4\wr_detect$7[0:0]$11272 $3\wr_detect$7[0:0]$11271 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11174 1'1 + assign $5\wr_detect$7[0:0]$11273 1'1 case - assign $5\wr_detect$7[0:0]$11174 $4\wr_detect$7[0:0]$11173 + assign $5\wr_detect$7[0:0]$11273 $4\wr_detect$7[0:0]$11272 end case - assign $1\wr_detect$7[0:0]$11170 1'0 + assign $1\wr_detect$7[0:0]$11269 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11169 + update \wr_detect$7 $0\wr_detect$7[0:0]$11268 end - attribute \src "libresoc.v:178507.3-178552.6" - process $proc$libresoc.v:178507$11175 + attribute \src "libresoc.v:180391.3-180436.6" + process $proc$libresoc.v:180391$11274 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11176 $7\r2__data_o$next[1:0]$11183 - attribute \src "libresoc.v:178508.5-178508.29" + assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180392.5-180392.29" switch \initial - attribute \src "libresoc.v:178508.9-178508.17" + attribute \src "libresoc.v:180392.9-180392.17" case 1'1 case end @@ -367844,75 +370908,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11177 $6\r2__data_o$next[1:0]$11182 + assign $1\r2__data_o$next[1:0]$11276 $6\r2__data_o$next[1:0]$11281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11178 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11277 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11178 2'00 + assign $2\r2__data_o$next[1:0]$11277 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11179 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11278 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11179 $2\r2__data_o$next[1:0]$11178 + assign $3\r2__data_o$next[1:0]$11278 $2\r2__data_o$next[1:0]$11277 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11180 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11279 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11180 $3\r2__data_o$next[1:0]$11179 + assign $4\r2__data_o$next[1:0]$11279 $3\r2__data_o$next[1:0]$11278 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11181 \w2__data_i + assign $5\r2__data_o$next[1:0]$11280 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11181 $4\r2__data_o$next[1:0]$11180 + assign $5\r2__data_o$next[1:0]$11280 $4\r2__data_o$next[1:0]$11279 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11182 \reg + assign $6\r2__data_o$next[1:0]$11281 \reg case - assign $6\r2__data_o$next[1:0]$11182 $5\r2__data_o$next[1:0]$11181 + assign $6\r2__data_o$next[1:0]$11281 $5\r2__data_o$next[1:0]$11280 end case - assign $1\r2__data_o$next[1:0]$11177 2'00 + assign $1\r2__data_o$next[1:0]$11276 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11183 2'00 + assign $7\r2__data_o$next[1:0]$11282 2'00 case - assign $7\r2__data_o$next[1:0]$11183 $1\r2__data_o$next[1:0]$11177 + assign $7\r2__data_o$next[1:0]$11282 $1\r2__data_o$next[1:0]$11276 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11176 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 end - attribute \src "libresoc.v:178553.3-178588.6" - process $proc$libresoc.v:178553$11184 + attribute \src "libresoc.v:180437.3-180472.6" + process $proc$libresoc.v:180437$11283 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11185 $1\wr_detect$10[0:0]$11186 - attribute \src "libresoc.v:178554.5-178554.29" + assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180438.5-180438.29" switch \initial - attribute \src "libresoc.v:178554.9-178554.17" + attribute \src "libresoc.v:180438.9-180438.17" case 1'1 case end @@ -367925,61 +370989,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11186 $5\wr_detect$10[0:0]$11190 + assign $1\wr_detect$10[0:0]$11285 $5\wr_detect$10[0:0]$11289 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11187 1'1 + assign $2\wr_detect$10[0:0]$11286 1'1 case - assign $2\wr_detect$10[0:0]$11187 1'0 + assign $2\wr_detect$10[0:0]$11286 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11188 1'1 + assign $3\wr_detect$10[0:0]$11287 1'1 case - assign $3\wr_detect$10[0:0]$11188 $2\wr_detect$10[0:0]$11187 + assign $3\wr_detect$10[0:0]$11287 $2\wr_detect$10[0:0]$11286 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11189 1'1 + assign $4\wr_detect$10[0:0]$11288 1'1 case - assign $4\wr_detect$10[0:0]$11189 $3\wr_detect$10[0:0]$11188 + assign $4\wr_detect$10[0:0]$11288 $3\wr_detect$10[0:0]$11287 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11190 1'1 + assign $5\wr_detect$10[0:0]$11289 1'1 case - assign $5\wr_detect$10[0:0]$11190 $4\wr_detect$10[0:0]$11189 + assign $5\wr_detect$10[0:0]$11289 $4\wr_detect$10[0:0]$11288 end case - assign $1\wr_detect$10[0:0]$11186 1'0 + assign $1\wr_detect$10[0:0]$11285 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11185 + update \wr_detect$10 $0\wr_detect$10[0:0]$11284 end - attribute \src "libresoc.v:178589.3-178621.6" - process $proc$libresoc.v:178589$11191 + attribute \src "libresoc.v:180473.3-180505.6" + process $proc$libresoc.v:180473$11290 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11192 $5\reg$next[1:0]$11197 - attribute \src "libresoc.v:178590.5-178590.29" + assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180474.5-180474.29" switch \initial - attribute \src "libresoc.v:178590.9-178590.17" + attribute \src "libresoc.v:180474.9-180474.17" case 1'1 case end @@ -367988,179 +371052,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11193 \dest12__data_i + assign $1\reg$next[1:0]$11292 \dest12__data_i case - assign $1\reg$next[1:0]$11193 \reg + assign $1\reg$next[1:0]$11292 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11194 \dest22__data_i + assign $2\reg$next[1:0]$11293 \dest22__data_i case - assign $2\reg$next[1:0]$11194 $1\reg$next[1:0]$11193 + assign $2\reg$next[1:0]$11293 $1\reg$next[1:0]$11292 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11195 \dest32__data_i + assign $3\reg$next[1:0]$11294 \dest32__data_i case - assign $3\reg$next[1:0]$11195 $2\reg$next[1:0]$11194 + assign $3\reg$next[1:0]$11294 $2\reg$next[1:0]$11293 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11196 \w2__data_i + assign $4\reg$next[1:0]$11295 \w2__data_i case - assign $4\reg$next[1:0]$11196 $3\reg$next[1:0]$11195 + assign $4\reg$next[1:0]$11295 $3\reg$next[1:0]$11294 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11197 2'00 + assign $5\reg$next[1:0]$11296 2'00 case - assign $5\reg$next[1:0]$11197 $4\reg$next[1:0]$11196 + assign $5\reg$next[1:0]$11296 $4\reg$next[1:0]$11295 end sync always - update \reg$next $0\reg$next[1:0]$11192 + update \reg$next $0\reg$next[1:0]$11291 end - connect \$9 $not$libresoc.v:178247$11124_Y - connect \$1 $not$libresoc.v:178248$11125_Y - connect \$3 $not$libresoc.v:178249$11126_Y - connect \$6 $not$libresoc.v:178250$11127_Y + connect \$9 $not$libresoc.v:180131$11223_Y + connect \$1 $not$libresoc.v:180132$11224_Y + connect \$3 $not$libresoc.v:180133$11225_Y + connect \$6 $not$libresoc.v:180134$11226_Y end -attribute \src "libresoc.v:178626.1-178975.10" +attribute \src "libresoc.v:180510.1-180859.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $0\cia2__data_o$next[63:0]$11212 - attribute \src "libresoc.v:178694.3-178695.41" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $0\cia2__data_o$next[63:0]$11311 + attribute \src "libresoc.v:180578.3-180579.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:178627.7-178627.20" + attribute \src "libresoc.v:180511.7-180511.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $0\msr2__data_o$next[63:0]$11222 - attribute \src "libresoc.v:178692.3-178693.41" + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $0\msr2__data_o$next[63:0]$11321 + attribute \src "libresoc.v:180576.3-180577.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $0\reg$next[63:0]$11254 - attribute \src "libresoc.v:178688.3-178689.25" + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $0\reg$next[63:0]$11353 + attribute \src "libresoc.v:180572.3-180573.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $0\sv2__data_o$next[63:0]$11238 - attribute \src "libresoc.v:178690.3-178691.39" + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $0\sv2__data_o$next[63:0]$11337 + attribute \src "libresoc.v:180574.3-180575.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:178824.3-178859.6" - wire $0\wr_detect$4[0:0]$11231 - attribute \src "libresoc.v:178906.3-178941.6" - wire $0\wr_detect$7[0:0]$11247 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180708.3-180743.6" + wire $0\wr_detect$4[0:0]$11330 + attribute \src "libresoc.v:180790.3-180825.6" + wire $0\wr_detect$7[0:0]$11346 + attribute \src "libresoc.v:180626.3-180661.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $1\cia2__data_o$next[63:0]$11213 - attribute \src "libresoc.v:178636.14-178636.49" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $1\cia2__data_o$next[63:0]$11312 + attribute \src "libresoc.v:180520.14-180520.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $1\msr2__data_o$next[63:0]$11223 - attribute \src "libresoc.v:178653.14-178653.49" + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $1\msr2__data_o$next[63:0]$11322 + attribute \src "libresoc.v:180537.14-180537.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $1\reg$next[63:0]$11255 - attribute \src "libresoc.v:178665.14-178665.42" + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $1\reg$next[63:0]$11354 + attribute \src "libresoc.v:180549.14-180549.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $1\sv2__data_o$next[63:0]$11239 - attribute \src "libresoc.v:178672.14-178672.48" + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $1\sv2__data_o$next[63:0]$11338 + attribute \src "libresoc.v:180556.14-180556.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:178824.3-178859.6" - wire $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:178906.3-178941.6" - wire $1\wr_detect$7[0:0]$11248 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180708.3-180743.6" + wire $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180790.3-180825.6" + wire $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180626.3-180661.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $2\cia2__data_o$next[63:0]$11214 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $2\msr2__data_o$next[63:0]$11224 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $2\reg$next[63:0]$11256 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $2\sv2__data_o$next[63:0]$11240 - attribute \src "libresoc.v:178824.3-178859.6" - wire $2\wr_detect$4[0:0]$11233 - attribute \src "libresoc.v:178906.3-178941.6" - wire $2\wr_detect$7[0:0]$11249 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $2\cia2__data_o$next[63:0]$11313 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $2\msr2__data_o$next[63:0]$11323 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $2\reg$next[63:0]$11355 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $2\sv2__data_o$next[63:0]$11339 + attribute \src "libresoc.v:180708.3-180743.6" + wire $2\wr_detect$4[0:0]$11332 + attribute \src "libresoc.v:180790.3-180825.6" + wire $2\wr_detect$7[0:0]$11348 + attribute \src "libresoc.v:180626.3-180661.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $3\cia2__data_o$next[63:0]$11215 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $3\msr2__data_o$next[63:0]$11225 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $3\reg$next[63:0]$11257 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $3\sv2__data_o$next[63:0]$11241 - attribute \src "libresoc.v:178824.3-178859.6" - wire $3\wr_detect$4[0:0]$11234 - attribute \src "libresoc.v:178906.3-178941.6" - wire $3\wr_detect$7[0:0]$11250 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $3\cia2__data_o$next[63:0]$11314 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $3\msr2__data_o$next[63:0]$11324 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $3\reg$next[63:0]$11356 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $3\sv2__data_o$next[63:0]$11340 + attribute \src "libresoc.v:180708.3-180743.6" + wire $3\wr_detect$4[0:0]$11333 + attribute \src "libresoc.v:180790.3-180825.6" + wire $3\wr_detect$7[0:0]$11349 + attribute \src "libresoc.v:180626.3-180661.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $4\cia2__data_o$next[63:0]$11216 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $4\msr2__data_o$next[63:0]$11226 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $4\reg$next[63:0]$11258 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $4\sv2__data_o$next[63:0]$11242 - attribute \src "libresoc.v:178824.3-178859.6" - wire $4\wr_detect$4[0:0]$11235 - attribute \src "libresoc.v:178906.3-178941.6" - wire $4\wr_detect$7[0:0]$11251 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $4\cia2__data_o$next[63:0]$11315 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $4\msr2__data_o$next[63:0]$11325 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $4\reg$next[63:0]$11357 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $4\sv2__data_o$next[63:0]$11341 + attribute \src "libresoc.v:180708.3-180743.6" + wire $4\wr_detect$4[0:0]$11334 + attribute \src "libresoc.v:180790.3-180825.6" + wire $4\wr_detect$7[0:0]$11350 + attribute \src "libresoc.v:180626.3-180661.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $5\cia2__data_o$next[63:0]$11217 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $5\msr2__data_o$next[63:0]$11227 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $5\reg$next[63:0]$11259 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $5\sv2__data_o$next[63:0]$11243 - attribute \src "libresoc.v:178824.3-178859.6" - wire $5\wr_detect$4[0:0]$11236 - attribute \src "libresoc.v:178906.3-178941.6" - wire $5\wr_detect$7[0:0]$11252 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $5\cia2__data_o$next[63:0]$11316 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $5\msr2__data_o$next[63:0]$11326 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $5\sv2__data_o$next[63:0]$11342 + attribute \src "libresoc.v:180708.3-180743.6" + wire $5\wr_detect$4[0:0]$11335 + attribute \src "libresoc.v:180790.3-180825.6" + wire $5\wr_detect$7[0:0]$11351 + attribute \src "libresoc.v:180626.3-180661.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $6\cia2__data_o$next[63:0]$11218 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $6\msr2__data_o$next[63:0]$11228 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $6\sv2__data_o$next[63:0]$11244 - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $7\cia2__data_o$next[63:0]$11219 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $7\msr2__data_o$next[63:0]$11229 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $7\sv2__data_o$next[63:0]$11245 - attribute \src "libresoc.v:178685.17-178685.100" - wire $not$libresoc.v:178685$11204_Y - attribute \src "libresoc.v:178686.17-178686.103" - wire $not$libresoc.v:178686$11205_Y - attribute \src "libresoc.v:178687.17-178687.103" - wire $not$libresoc.v:178687$11206_Y + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $6\cia2__data_o$next[63:0]$11317 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $6\msr2__data_o$next[63:0]$11327 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $6\sv2__data_o$next[63:0]$11343 + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180569.17-180569.100" + wire $not$libresoc.v:180569$11303_Y + attribute \src "libresoc.v:180570.17-180570.103" + wire $not$libresoc.v:180570$11304_Y + attribute \src "libresoc.v:180571.17-180571.103" + wire $not$libresoc.v:180571$11305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368173,15 +371237,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:178627.7-178627.15" + attribute \src "libresoc.v:180511.7-180511.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -368218,106 +371282,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178685$11204 + cell $not $not$libresoc.v:180569$11303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178685$11204_Y + connect \Y $not$libresoc.v:180569$11303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178686$11205 + cell $not $not$libresoc.v:180570$11304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178686$11205_Y + connect \Y $not$libresoc.v:180570$11304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178687$11206 + cell $not $not$libresoc.v:180571$11305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178687$11206_Y + connect \Y $not$libresoc.v:180571$11305_Y end - attribute \src "libresoc.v:178627.7-178627.20" - process $proc$libresoc.v:178627$11260 + attribute \src "libresoc.v:180511.7-180511.20" + process $proc$libresoc.v:180511$11359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178636.14-178636.49" - process $proc$libresoc.v:178636$11261 + attribute \src "libresoc.v:180520.14-180520.49" + process $proc$libresoc.v:180520$11360 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:178653.14-178653.49" - process $proc$libresoc.v:178653$11262 + attribute \src "libresoc.v:180537.14-180537.49" + process $proc$libresoc.v:180537$11361 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:178665.14-178665.42" - process $proc$libresoc.v:178665$11263 + attribute \src "libresoc.v:180549.14-180549.42" + process $proc$libresoc.v:180549$11362 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:178672.14-178672.48" - process $proc$libresoc.v:178672$11264 + attribute \src "libresoc.v:180556.14-180556.48" + process $proc$libresoc.v:180556$11363 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:178688.3-178689.25" - process $proc$libresoc.v:178688$11207 + attribute \src "libresoc.v:180572.3-180573.25" + process $proc$libresoc.v:180572$11306 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:178690.3-178691.39" - process $proc$libresoc.v:178690$11208 + attribute \src "libresoc.v:180574.3-180575.39" + process $proc$libresoc.v:180574$11307 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:178692.3-178693.41" - process $proc$libresoc.v:178692$11209 + attribute \src "libresoc.v:180576.3-180577.41" + process $proc$libresoc.v:180576$11308 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:178694.3-178695.41" - process $proc$libresoc.v:178694$11210 + attribute \src "libresoc.v:180578.3-180579.41" + process $proc$libresoc.v:180578$11309 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:178696.3-178741.6" - process $proc$libresoc.v:178696$11211 + attribute \src "libresoc.v:180580.3-180625.6" + process $proc$libresoc.v:180580$11310 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11212 $7\cia2__data_o$next[63:0]$11219 - attribute \src "libresoc.v:178697.5-178697.29" + assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180581.5-180581.29" switch \initial - attribute \src "libresoc.v:178697.9-178697.17" + attribute \src "libresoc.v:180581.9-180581.17" case 1'1 case end @@ -368330,75 +371394,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11213 $6\cia2__data_o$next[63:0]$11218 + assign $1\cia2__data_o$next[63:0]$11312 $6\cia2__data_o$next[63:0]$11317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11214 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11313 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11313 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11215 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11314 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11215 $2\cia2__data_o$next[63:0]$11214 + assign $3\cia2__data_o$next[63:0]$11314 $2\cia2__data_o$next[63:0]$11313 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11216 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11315 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11216 $3\cia2__data_o$next[63:0]$11215 + assign $4\cia2__data_o$next[63:0]$11315 $3\cia2__data_o$next[63:0]$11314 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11217 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11316 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11217 $4\cia2__data_o$next[63:0]$11216 + assign $5\cia2__data_o$next[63:0]$11316 $4\cia2__data_o$next[63:0]$11315 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11218 \reg + assign $6\cia2__data_o$next[63:0]$11317 \reg case - assign $6\cia2__data_o$next[63:0]$11218 $5\cia2__data_o$next[63:0]$11217 + assign $6\cia2__data_o$next[63:0]$11317 $5\cia2__data_o$next[63:0]$11316 end case - assign $1\cia2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11219 $1\cia2__data_o$next[63:0]$11213 + assign $7\cia2__data_o$next[63:0]$11318 $1\cia2__data_o$next[63:0]$11312 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11212 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 end - attribute \src "libresoc.v:178742.3-178777.6" - process $proc$libresoc.v:178742$11220 + attribute \src "libresoc.v:180626.3-180661.6" + process $proc$libresoc.v:180626$11319 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178743.5-178743.29" + attribute \src "libresoc.v:180627.5-180627.29" switch \initial - attribute \src "libresoc.v:178743.9-178743.17" + attribute \src "libresoc.v:180627.9-180627.17" case 1'1 case end @@ -368454,15 +371518,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178778.3-178823.6" - process $proc$libresoc.v:178778$11221 + attribute \src "libresoc.v:180662.3-180707.6" + process $proc$libresoc.v:180662$11320 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11222 $7\msr2__data_o$next[63:0]$11229 - attribute \src "libresoc.v:178779.5-178779.29" + assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180663.5-180663.29" switch \initial - attribute \src "libresoc.v:178779.9-178779.17" + attribute \src "libresoc.v:180663.9-180663.17" case 1'1 case end @@ -368475,75 +371539,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11223 $6\msr2__data_o$next[63:0]$11228 + assign $1\msr2__data_o$next[63:0]$11322 $6\msr2__data_o$next[63:0]$11327 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11224 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11323 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11224 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11225 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11324 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11225 $2\msr2__data_o$next[63:0]$11224 + assign $3\msr2__data_o$next[63:0]$11324 $2\msr2__data_o$next[63:0]$11323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11226 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11325 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11226 $3\msr2__data_o$next[63:0]$11225 + assign $4\msr2__data_o$next[63:0]$11325 $3\msr2__data_o$next[63:0]$11324 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11227 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11326 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11227 $4\msr2__data_o$next[63:0]$11226 + assign $5\msr2__data_o$next[63:0]$11326 $4\msr2__data_o$next[63:0]$11325 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11228 \reg + assign $6\msr2__data_o$next[63:0]$11327 \reg case - assign $6\msr2__data_o$next[63:0]$11228 $5\msr2__data_o$next[63:0]$11227 + assign $6\msr2__data_o$next[63:0]$11327 $5\msr2__data_o$next[63:0]$11326 end case - assign $1\msr2__data_o$next[63:0]$11223 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11229 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11229 $1\msr2__data_o$next[63:0]$11223 + assign $7\msr2__data_o$next[63:0]$11328 $1\msr2__data_o$next[63:0]$11322 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11222 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 end - attribute \src "libresoc.v:178824.3-178859.6" - process $proc$libresoc.v:178824$11230 + attribute \src "libresoc.v:180708.3-180743.6" + process $proc$libresoc.v:180708$11329 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:178825.5-178825.29" + assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180709.5-180709.29" switch \initial - attribute \src "libresoc.v:178825.9-178825.17" + attribute \src "libresoc.v:180709.9-180709.17" case 1'1 case end @@ -368556,58 +371620,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11232 $5\wr_detect$4[0:0]$11236 + assign $1\wr_detect$4[0:0]$11331 $5\wr_detect$4[0:0]$11335 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11233 1'1 + assign $2\wr_detect$4[0:0]$11332 1'1 case - assign $2\wr_detect$4[0:0]$11233 1'0 + assign $2\wr_detect$4[0:0]$11332 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11234 1'1 + assign $3\wr_detect$4[0:0]$11333 1'1 case - assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 + assign $3\wr_detect$4[0:0]$11333 $2\wr_detect$4[0:0]$11332 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11235 1'1 + assign $4\wr_detect$4[0:0]$11334 1'1 case - assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 + assign $4\wr_detect$4[0:0]$11334 $3\wr_detect$4[0:0]$11333 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11236 1'1 + assign $5\wr_detect$4[0:0]$11335 1'1 case - assign $5\wr_detect$4[0:0]$11236 $4\wr_detect$4[0:0]$11235 + assign $5\wr_detect$4[0:0]$11335 $4\wr_detect$4[0:0]$11334 end case - assign $1\wr_detect$4[0:0]$11232 1'0 + assign $1\wr_detect$4[0:0]$11331 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11231 + update \wr_detect$4 $0\wr_detect$4[0:0]$11330 end - attribute \src "libresoc.v:178860.3-178905.6" - process $proc$libresoc.v:178860$11237 + attribute \src "libresoc.v:180744.3-180789.6" + process $proc$libresoc.v:180744$11336 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11238 $7\sv2__data_o$next[63:0]$11245 - attribute \src "libresoc.v:178861.5-178861.29" + assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180745.5-180745.29" switch \initial - attribute \src "libresoc.v:178861.9-178861.17" + attribute \src "libresoc.v:180745.9-180745.17" case 1'1 case end @@ -368620,75 +371684,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11239 $6\sv2__data_o$next[63:0]$11244 + assign $1\sv2__data_o$next[63:0]$11338 $6\sv2__data_o$next[63:0]$11343 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11240 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11339 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11240 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11339 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11241 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11340 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11241 $2\sv2__data_o$next[63:0]$11240 + assign $3\sv2__data_o$next[63:0]$11340 $2\sv2__data_o$next[63:0]$11339 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11242 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11341 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11242 $3\sv2__data_o$next[63:0]$11241 + assign $4\sv2__data_o$next[63:0]$11341 $3\sv2__data_o$next[63:0]$11340 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11243 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11342 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11243 $4\sv2__data_o$next[63:0]$11242 + assign $5\sv2__data_o$next[63:0]$11342 $4\sv2__data_o$next[63:0]$11341 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11244 \reg + assign $6\sv2__data_o$next[63:0]$11343 \reg case - assign $6\sv2__data_o$next[63:0]$11244 $5\sv2__data_o$next[63:0]$11243 + assign $6\sv2__data_o$next[63:0]$11343 $5\sv2__data_o$next[63:0]$11342 end case - assign $1\sv2__data_o$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11338 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11245 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11344 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11245 $1\sv2__data_o$next[63:0]$11239 + assign $7\sv2__data_o$next[63:0]$11344 $1\sv2__data_o$next[63:0]$11338 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11238 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 end - attribute \src "libresoc.v:178906.3-178941.6" - process $proc$libresoc.v:178906$11246 + attribute \src "libresoc.v:180790.3-180825.6" + process $proc$libresoc.v:180790$11345 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11247 $1\wr_detect$7[0:0]$11248 - attribute \src "libresoc.v:178907.5-178907.29" + assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180791.5-180791.29" switch \initial - attribute \src "libresoc.v:178907.9-178907.17" + attribute \src "libresoc.v:180791.9-180791.17" case 1'1 case end @@ -368701,61 +371765,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11248 $5\wr_detect$7[0:0]$11252 + assign $1\wr_detect$7[0:0]$11347 $5\wr_detect$7[0:0]$11351 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11249 1'1 + assign $2\wr_detect$7[0:0]$11348 1'1 case - assign $2\wr_detect$7[0:0]$11249 1'0 + assign $2\wr_detect$7[0:0]$11348 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11250 1'1 + assign $3\wr_detect$7[0:0]$11349 1'1 case - assign $3\wr_detect$7[0:0]$11250 $2\wr_detect$7[0:0]$11249 + assign $3\wr_detect$7[0:0]$11349 $2\wr_detect$7[0:0]$11348 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11251 1'1 + assign $4\wr_detect$7[0:0]$11350 1'1 case - assign $4\wr_detect$7[0:0]$11251 $3\wr_detect$7[0:0]$11250 + assign $4\wr_detect$7[0:0]$11350 $3\wr_detect$7[0:0]$11349 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11252 1'1 + assign $5\wr_detect$7[0:0]$11351 1'1 case - assign $5\wr_detect$7[0:0]$11252 $4\wr_detect$7[0:0]$11251 + assign $5\wr_detect$7[0:0]$11351 $4\wr_detect$7[0:0]$11350 end case - assign $1\wr_detect$7[0:0]$11248 1'0 + assign $1\wr_detect$7[0:0]$11347 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11247 + update \wr_detect$7 $0\wr_detect$7[0:0]$11346 end - attribute \src "libresoc.v:178942.3-178974.6" - process $proc$libresoc.v:178942$11253 + attribute \src "libresoc.v:180826.3-180858.6" + process $proc$libresoc.v:180826$11352 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11254 $5\reg$next[63:0]$11259 - attribute \src "libresoc.v:178943.5-178943.29" + assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180827.5-180827.29" switch \initial - attribute \src "libresoc.v:178943.9-178943.17" + attribute \src "libresoc.v:180827.9-180827.17" case 1'1 case end @@ -368764,286 +371828,324 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11255 \nia2__data_i + assign $1\reg$next[63:0]$11354 \nia2__data_i case - assign $1\reg$next[63:0]$11255 \reg + assign $1\reg$next[63:0]$11354 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11256 \msr2__data_i + assign $2\reg$next[63:0]$11355 \msr2__data_i case - assign $2\reg$next[63:0]$11256 $1\reg$next[63:0]$11255 + assign $2\reg$next[63:0]$11355 $1\reg$next[63:0]$11354 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11257 \sv2__data_i + assign $3\reg$next[63:0]$11356 \sv2__data_i case - assign $3\reg$next[63:0]$11257 $2\reg$next[63:0]$11256 + assign $3\reg$next[63:0]$11356 $2\reg$next[63:0]$11355 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11258 \d_wr12__data_i + assign $4\reg$next[63:0]$11357 \d_wr12__data_i case - assign $4\reg$next[63:0]$11258 $3\reg$next[63:0]$11257 + assign $4\reg$next[63:0]$11357 $3\reg$next[63:0]$11356 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11358 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11259 $4\reg$next[63:0]$11258 + assign $5\reg$next[63:0]$11358 $4\reg$next[63:0]$11357 end sync always - update \reg$next $0\reg$next[63:0]$11254 + update \reg$next $0\reg$next[63:0]$11353 end - connect \$1 $not$libresoc.v:178685$11204_Y - connect \$3 $not$libresoc.v:178686$11205_Y - connect \$6 $not$libresoc.v:178687$11206_Y + connect \$1 $not$libresoc.v:180569$11303_Y + connect \$3 $not$libresoc.v:180570$11304_Y + connect \$6 $not$libresoc.v:180571$11305_Y end -attribute \src "libresoc.v:178979.1-179450.10" +attribute \src "libresoc.v:180863.1-181418.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:178980.7-178980.20" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 + attribute \src "libresoc.v:180969.3-180970.49" + wire width 4 $0\cr_pred3__data_o[3:0] + attribute \src "libresoc.v:180864.7-180864.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $0\r23__data_o$next[3:0]$11334 - attribute \src "libresoc.v:179063.3-179064.39" + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $0\r23__data_o$next[3:0]$11387 + attribute \src "libresoc.v:180959.3-180960.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $0\r3__data_o$next[3:0]$11320 - attribute \src "libresoc.v:179065.3-179066.37" + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $0\r3__data_o$next[3:0]$11449 + attribute \src "libresoc.v:180961.3-180962.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $0\reg$next[3:0]$11286 - attribute \src "libresoc.v:179061.3-179062.25" + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $0\reg$next[3:0]$11401 + attribute \src "libresoc.v:180957.3-180958.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $0\src13__data_o$next[3:0]$11277 - attribute \src "libresoc.v:179071.3-179072.43" + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $0\src13__data_o$next[3:0]$11407 + attribute \src "libresoc.v:180967.3-180968.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $0\src23__data_o$next[3:0]$11292 - attribute \src "libresoc.v:179069.3-179070.43" + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $0\src23__data_o$next[3:0]$11421 + attribute \src "libresoc.v:180965.3-180966.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $0\src33__data_o$next[3:0]$11306 - attribute \src "libresoc.v:179067.3-179068.43" + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $0\src33__data_o$next[3:0]$11435 + attribute \src "libresoc.v:180963.3-180964.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:179350.3-179379.6" - wire $0\wr_detect$10[0:0]$11328 - attribute \src "libresoc.v:179420.3-179449.6" - wire $0\wr_detect$13[0:0]$11342 - attribute \src "libresoc.v:179210.3-179239.6" - wire $0\wr_detect$4[0:0]$11300 - attribute \src "libresoc.v:179280.3-179309.6" - wire $0\wr_detect$7[0:0]$11314 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:181318.3-181347.6" + wire $0\wr_detect$10[0:0]$11443 + attribute \src "libresoc.v:181388.3-181417.6" + wire $0\wr_detect$13[0:0]$11457 + attribute \src "libresoc.v:181081.3-181110.6" + wire $0\wr_detect$16[0:0]$11395 + attribute \src "libresoc.v:181178.3-181207.6" + wire $0\wr_detect$4[0:0]$11415 + attribute \src "libresoc.v:181248.3-181277.6" + wire $0\wr_detect$7[0:0]$11429 + attribute \src "libresoc.v:181011.3-181040.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $1\r23__data_o$next[3:0]$11335 - attribute \src "libresoc.v:179005.13-179005.31" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $1\cr_pred3__data_o$next[3:0]$11379 + attribute \src "libresoc.v:180883.13-180883.36" + wire width 4 $1\cr_pred3__data_o[3:0] + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $1\r23__data_o$next[3:0]$11388 + attribute \src "libresoc.v:180898.13-180898.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $1\r3__data_o$next[3:0]$11321 - attribute \src "libresoc.v:179012.13-179012.30" + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $1\r3__data_o$next[3:0]$11450 + attribute \src "libresoc.v:180905.13-180905.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $1\reg$next[3:0]$11287 - attribute \src "libresoc.v:179018.13-179018.25" + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $1\reg$next[3:0]$11402 + attribute \src "libresoc.v:180911.13-180911.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $1\src13__data_o$next[3:0]$11278 - attribute \src "libresoc.v:179023.13-179023.33" + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $1\src13__data_o$next[3:0]$11408 + attribute \src "libresoc.v:180916.13-180916.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $1\src23__data_o$next[3:0]$11293 - attribute \src "libresoc.v:179030.13-179030.33" + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $1\src23__data_o$next[3:0]$11422 + attribute \src "libresoc.v:180923.13-180923.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $1\src33__data_o$next[3:0]$11307 - attribute \src "libresoc.v:179037.13-179037.33" + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $1\src33__data_o$next[3:0]$11436 + attribute \src "libresoc.v:180930.13-180930.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:179350.3-179379.6" - wire $1\wr_detect$10[0:0]$11329 - attribute \src "libresoc.v:179420.3-179449.6" - wire $1\wr_detect$13[0:0]$11343 - attribute \src "libresoc.v:179210.3-179239.6" - wire $1\wr_detect$4[0:0]$11301 - attribute \src "libresoc.v:179280.3-179309.6" - wire $1\wr_detect$7[0:0]$11315 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:181318.3-181347.6" + wire $1\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:181388.3-181417.6" + wire $1\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:181081.3-181110.6" + wire $1\wr_detect$16[0:0]$11396 + attribute \src "libresoc.v:181178.3-181207.6" + wire $1\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:181248.3-181277.6" + wire $1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181011.3-181040.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $2\r23__data_o$next[3:0]$11336 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $2\r3__data_o$next[3:0]$11322 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $2\reg$next[3:0]$11288 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $2\src13__data_o$next[3:0]$11279 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $2\src23__data_o$next[3:0]$11294 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $2\src33__data_o$next[3:0]$11308 - attribute \src "libresoc.v:179350.3-179379.6" - wire $2\wr_detect$10[0:0]$11330 - attribute \src "libresoc.v:179420.3-179449.6" - wire $2\wr_detect$13[0:0]$11344 - attribute \src "libresoc.v:179210.3-179239.6" - wire $2\wr_detect$4[0:0]$11302 - attribute \src "libresoc.v:179280.3-179309.6" - wire $2\wr_detect$7[0:0]$11316 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $2\r23__data_o$next[3:0]$11389 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $2\r3__data_o$next[3:0]$11451 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $2\reg$next[3:0]$11403 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $2\src13__data_o$next[3:0]$11409 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $2\src23__data_o$next[3:0]$11423 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $2\src33__data_o$next[3:0]$11437 + attribute \src "libresoc.v:181318.3-181347.6" + wire $2\wr_detect$10[0:0]$11445 + attribute \src "libresoc.v:181388.3-181417.6" + wire $2\wr_detect$13[0:0]$11459 + attribute \src "libresoc.v:181081.3-181110.6" + wire $2\wr_detect$16[0:0]$11397 + attribute \src "libresoc.v:181178.3-181207.6" + wire $2\wr_detect$4[0:0]$11417 + attribute \src "libresoc.v:181248.3-181277.6" + wire $2\wr_detect$7[0:0]$11431 + attribute \src "libresoc.v:181011.3-181040.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $3\r23__data_o$next[3:0]$11337 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $3\r3__data_o$next[3:0]$11323 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $3\reg$next[3:0]$11289 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $3\src13__data_o$next[3:0]$11280 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $3\src23__data_o$next[3:0]$11295 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $3\src33__data_o$next[3:0]$11309 - attribute \src "libresoc.v:179350.3-179379.6" - wire $3\wr_detect$10[0:0]$11331 - attribute \src "libresoc.v:179420.3-179449.6" - wire $3\wr_detect$13[0:0]$11345 - attribute \src "libresoc.v:179210.3-179239.6" - wire $3\wr_detect$4[0:0]$11303 - attribute \src "libresoc.v:179280.3-179309.6" - wire $3\wr_detect$7[0:0]$11317 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $3\r23__data_o$next[3:0]$11390 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $3\r3__data_o$next[3:0]$11452 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $3\reg$next[3:0]$11404 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $3\src13__data_o$next[3:0]$11410 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $3\src23__data_o$next[3:0]$11424 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $3\src33__data_o$next[3:0]$11438 + attribute \src "libresoc.v:181318.3-181347.6" + wire $3\wr_detect$10[0:0]$11446 + attribute \src "libresoc.v:181388.3-181417.6" + wire $3\wr_detect$13[0:0]$11460 + attribute \src "libresoc.v:181081.3-181110.6" + wire $3\wr_detect$16[0:0]$11398 + attribute \src "libresoc.v:181178.3-181207.6" + wire $3\wr_detect$4[0:0]$11418 + attribute \src "libresoc.v:181248.3-181277.6" + wire $3\wr_detect$7[0:0]$11432 + attribute \src "libresoc.v:181011.3-181040.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $4\r23__data_o$next[3:0]$11338 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $4\r3__data_o$next[3:0]$11324 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $4\reg$next[3:0]$11290 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $4\src13__data_o$next[3:0]$11281 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $4\src23__data_o$next[3:0]$11296 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $4\src33__data_o$next[3:0]$11310 - attribute \src "libresoc.v:179350.3-179379.6" - wire $4\wr_detect$10[0:0]$11332 - attribute \src "libresoc.v:179420.3-179449.6" - wire $4\wr_detect$13[0:0]$11346 - attribute \src "libresoc.v:179210.3-179239.6" - wire $4\wr_detect$4[0:0]$11304 - attribute \src "libresoc.v:179280.3-179309.6" - wire $4\wr_detect$7[0:0]$11318 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $4\r23__data_o$next[3:0]$11391 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $4\r3__data_o$next[3:0]$11453 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $4\src13__data_o$next[3:0]$11411 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $4\src23__data_o$next[3:0]$11425 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $4\src33__data_o$next[3:0]$11439 + attribute \src "libresoc.v:181318.3-181347.6" + wire $4\wr_detect$10[0:0]$11447 + attribute \src "libresoc.v:181388.3-181417.6" + wire $4\wr_detect$13[0:0]$11461 + attribute \src "libresoc.v:181081.3-181110.6" + wire $4\wr_detect$16[0:0]$11399 + attribute \src "libresoc.v:181178.3-181207.6" + wire $4\wr_detect$4[0:0]$11419 + attribute \src "libresoc.v:181248.3-181277.6" + wire $4\wr_detect$7[0:0]$11433 + attribute \src "libresoc.v:181011.3-181040.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $5\r23__data_o$next[3:0]$11339 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $5\r3__data_o$next[3:0]$11325 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $5\src13__data_o$next[3:0]$11282 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $5\src23__data_o$next[3:0]$11297 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $5\src33__data_o$next[3:0]$11311 - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $6\r23__data_o$next[3:0]$11340 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $6\r3__data_o$next[3:0]$11326 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $6\src13__data_o$next[3:0]$11283 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $6\src23__data_o$next[3:0]$11298 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $6\src33__data_o$next[3:0]$11312 - attribute \src "libresoc.v:179056.17-179056.104" - wire $not$libresoc.v:179056$11265_Y - attribute \src "libresoc.v:179057.18-179057.105" - wire $not$libresoc.v:179057$11266_Y - attribute \src "libresoc.v:179058.17-179058.100" - wire $not$libresoc.v:179058$11267_Y - attribute \src "libresoc.v:179059.17-179059.103" - wire $not$libresoc.v:179059$11268_Y - attribute \src "libresoc.v:179060.17-179060.103" - wire $not$libresoc.v:179060$11269_Y + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $5\r23__data_o$next[3:0]$11392 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $5\r3__data_o$next[3:0]$11454 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $5\src13__data_o$next[3:0]$11412 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $5\src23__data_o$next[3:0]$11426 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $5\src33__data_o$next[3:0]$11440 + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:180951.17-180951.104" + wire $not$libresoc.v:180951$11364_Y + attribute \src "libresoc.v:180952.18-180952.105" + wire $not$libresoc.v:180952$11365_Y + attribute \src "libresoc.v:180953.18-180953.105" + wire $not$libresoc.v:180953$11366_Y + attribute \src "libresoc.v:180954.17-180954.100" + wire $not$libresoc.v:180954$11367_Y + attribute \src "libresoc.v:180955.17-180955.103" + wire $not$libresoc.v:180955$11368_Y + attribute \src "libresoc.v:180956.17-180956.103" + wire $not$libresoc.v:180956$11369_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest13__data_i + wire width 4 output 3 \cr_pred3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest13__wen + wire width 4 input 11 \dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest23__data_i + wire input 10 \dest13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest23__wen - attribute \src "libresoc.v:178980.7-178980.15" + wire width 4 input 13 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest23__wen + attribute \src "libresoc.v:180864.7-180864.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r23__data_o + wire width 4 output 16 \r23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r23__ren + wire input 17 \r23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r3__data_o + wire width 4 output 14 \r3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r3__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r3__ren + wire input 15 \r3__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src13__data_o + wire width 4 output 5 \src13__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src13__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src13__ren + wire input 4 \src13__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src23__data_o + wire width 4 output 7 \src23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src23__ren + wire input 6 \src23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src33__data_o + wire width 4 output 9 \src33__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src33__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src33__ren + wire input 8 \src33__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w3__data_i + wire width 4 input 18 \w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w3__wen + wire input 19 \w3__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -369051,232 +372153,257 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179056$11265 + cell $not $not$libresoc.v:180951$11364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179056$11265_Y + connect \Y $not$libresoc.v:180951$11364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179057$11266 + cell $not $not$libresoc.v:180952$11365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179057$11266_Y + connect \Y $not$libresoc.v:180952$11365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179058$11267 + cell $not $not$libresoc.v:180953$11366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:180953$11366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180954$11367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179058$11267_Y + connect \Y $not$libresoc.v:180954$11367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179059$11268 + cell $not $not$libresoc.v:180955$11368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179059$11268_Y + connect \Y $not$libresoc.v:180955$11368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179060$11269 + cell $not $not$libresoc.v:180956$11369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179060$11269_Y + connect \Y $not$libresoc.v:180956$11369_Y end - attribute \src "libresoc.v:178980.7-178980.20" - process $proc$libresoc.v:178980$11347 + attribute \src "libresoc.v:180864.7-180864.20" + process $proc$libresoc.v:180864$11462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179005.13-179005.31" - process $proc$libresoc.v:179005$11348 + attribute \src "libresoc.v:180883.13-180883.36" + process $proc$libresoc.v:180883$11463 + assign { } { } + assign $1\cr_pred3__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180898.13-180898.31" + process $proc$libresoc.v:180898$11464 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:179012.13-179012.30" - process $proc$libresoc.v:179012$11349 + attribute \src "libresoc.v:180905.13-180905.30" + process $proc$libresoc.v:180905$11465 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:179018.13-179018.25" - process $proc$libresoc.v:179018$11350 + attribute \src "libresoc.v:180911.13-180911.25" + process $proc$libresoc.v:180911$11466 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179023.13-179023.33" - process $proc$libresoc.v:179023$11351 + attribute \src "libresoc.v:180916.13-180916.33" + process $proc$libresoc.v:180916$11467 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:179030.13-179030.33" - process $proc$libresoc.v:179030$11352 + attribute \src "libresoc.v:180923.13-180923.33" + process $proc$libresoc.v:180923$11468 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:179037.13-179037.33" - process $proc$libresoc.v:179037$11353 + attribute \src "libresoc.v:180930.13-180930.33" + process $proc$libresoc.v:180930$11469 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:179061.3-179062.25" - process $proc$libresoc.v:179061$11270 + attribute \src "libresoc.v:180957.3-180958.25" + process $proc$libresoc.v:180957$11370 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179063.3-179064.39" - process $proc$libresoc.v:179063$11271 + attribute \src "libresoc.v:180959.3-180960.39" + process $proc$libresoc.v:180959$11371 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:179065.3-179066.37" - process $proc$libresoc.v:179065$11272 + attribute \src "libresoc.v:180961.3-180962.37" + process $proc$libresoc.v:180961$11372 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:179067.3-179068.43" - process $proc$libresoc.v:179067$11273 + attribute \src "libresoc.v:180963.3-180964.43" + process $proc$libresoc.v:180963$11373 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:179069.3-179070.43" - process $proc$libresoc.v:179069$11274 + attribute \src "libresoc.v:180965.3-180966.43" + process $proc$libresoc.v:180965$11374 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:179071.3-179072.43" - process $proc$libresoc.v:179071$11275 + attribute \src "libresoc.v:180967.3-180968.43" + process $proc$libresoc.v:180967$11375 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:179073.3-179112.6" - process $proc$libresoc.v:179073$11276 + attribute \src "libresoc.v:180969.3-180970.49" + process $proc$libresoc.v:180969$11376 + assign { } { } + assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next + sync posedge \coresync_clk + update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180971.3-181010.6" + process $proc$libresoc.v:180971$11377 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11277 $6\src13__data_o$next[3:0]$11283 - attribute \src "libresoc.v:179074.5-179074.29" + assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:180972.5-180972.29" switch \initial - attribute \src "libresoc.v:179074.9-179074.17" + attribute \src "libresoc.v:180972.9-180972.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \cr_pred3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11278 $5\src13__data_o$next[3:0]$11282 + assign $1\cr_pred3__data_o$next[3:0]$11379 $5\cr_pred3__data_o$next[3:0]$11383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11279 \dest13__data_i + assign $2\cr_pred3__data_o$next[3:0]$11380 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11279 4'0000 + assign $2\cr_pred3__data_o$next[3:0]$11380 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11280 \dest23__data_i + assign $3\cr_pred3__data_o$next[3:0]$11381 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11280 $2\src13__data_o$next[3:0]$11279 + assign $3\cr_pred3__data_o$next[3:0]$11381 $2\cr_pred3__data_o$next[3:0]$11380 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11281 \w3__data_i + assign $4\cr_pred3__data_o$next[3:0]$11382 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11281 $3\src13__data_o$next[3:0]$11280 + assign $4\cr_pred3__data_o$next[3:0]$11382 $3\cr_pred3__data_o$next[3:0]$11381 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11282 \reg + assign $5\cr_pred3__data_o$next[3:0]$11383 \reg case - assign $5\src13__data_o$next[3:0]$11282 $4\src13__data_o$next[3:0]$11281 + assign $5\cr_pred3__data_o$next[3:0]$11383 $4\cr_pred3__data_o$next[3:0]$11382 end case - assign $1\src13__data_o$next[3:0]$11278 4'0000 + assign $1\cr_pred3__data_o$next[3:0]$11379 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11283 4'0000 + assign $6\cr_pred3__data_o$next[3:0]$11384 4'0000 case - assign $6\src13__data_o$next[3:0]$11283 $1\src13__data_o$next[3:0]$11278 + assign $6\cr_pred3__data_o$next[3:0]$11384 $1\cr_pred3__data_o$next[3:0]$11379 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11277 + update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 end - attribute \src "libresoc.v:179113.3-179142.6" - process $proc$libresoc.v:179113$11284 + attribute \src "libresoc.v:181011.3-181040.6" + process $proc$libresoc.v:181011$11385 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179114.5-179114.29" + attribute \src "libresoc.v:181012.5-181012.29" switch \initial - attribute \src "libresoc.v:179114.9-179114.17" + attribute \src "libresoc.v:181012.9-181012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \cr_pred3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -369317,17 +372444,142 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179143.3-179169.6" - process $proc$libresoc.v:179143$11285 + attribute \src "libresoc.v:181041.3-181080.6" + process $proc$libresoc.v:181041$11386 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181042.5-181042.29" + switch \initial + attribute \src "libresoc.v:181042.9-181042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$11388 $5\r23__data_o$next[3:0]$11392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$11389 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$11389 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$11390 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$11390 $2\r23__data_o$next[3:0]$11389 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$11391 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$11391 $3\r23__data_o$next[3:0]$11390 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$11392 \reg + case + assign $5\r23__data_o$next[3:0]$11392 $4\r23__data_o$next[3:0]$11391 + end + case + assign $1\r23__data_o$next[3:0]$11388 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$11393 4'0000 + case + assign $6\r23__data_o$next[3:0]$11393 $1\r23__data_o$next[3:0]$11388 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 + end + attribute \src "libresoc.v:181081.3-181110.6" + process $proc$libresoc.v:181081$11394 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 + attribute \src "libresoc.v:181082.5-181082.29" + switch \initial + attribute \src "libresoc.v:181082.9-181082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11396 $4\wr_detect$16[0:0]$11399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11397 1'1 + case + assign $2\wr_detect$16[0:0]$11397 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11398 1'1 + case + assign $3\wr_detect$16[0:0]$11398 $2\wr_detect$16[0:0]$11397 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11399 1'1 + case + assign $4\wr_detect$16[0:0]$11399 $3\wr_detect$16[0:0]$11398 + end + case + assign $1\wr_detect$16[0:0]$11396 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11395 + end + attribute \src "libresoc.v:181111.3-181137.6" + process $proc$libresoc.v:181111$11400 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11286 $4\reg$next[3:0]$11290 - attribute \src "libresoc.v:179144.5-179144.29" + assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181112.5-181112.29" switch \initial - attribute \src "libresoc.v:179144.9-179144.17" + attribute \src "libresoc.v:181112.9-181112.17" case 1'1 case end @@ -369336,779 +372588,818 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11287 \dest13__data_i + assign $1\reg$next[3:0]$11402 \dest13__data_i case - assign $1\reg$next[3:0]$11287 \reg + assign $1\reg$next[3:0]$11402 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11288 \dest23__data_i + assign $2\reg$next[3:0]$11403 \dest23__data_i case - assign $2\reg$next[3:0]$11288 $1\reg$next[3:0]$11287 + assign $2\reg$next[3:0]$11403 $1\reg$next[3:0]$11402 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11289 \w3__data_i + assign $3\reg$next[3:0]$11404 \w3__data_i case - assign $3\reg$next[3:0]$11289 $2\reg$next[3:0]$11288 + assign $3\reg$next[3:0]$11404 $2\reg$next[3:0]$11403 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11290 4'0000 + assign $4\reg$next[3:0]$11405 4'0000 case - assign $4\reg$next[3:0]$11290 $3\reg$next[3:0]$11289 + assign $4\reg$next[3:0]$11405 $3\reg$next[3:0]$11404 end sync always - update \reg$next $0\reg$next[3:0]$11286 + update \reg$next $0\reg$next[3:0]$11401 end - attribute \src "libresoc.v:179170.3-179209.6" - process $proc$libresoc.v:179170$11291 + attribute \src "libresoc.v:181138.3-181177.6" + process $proc$libresoc.v:181138$11406 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11292 $6\src23__data_o$next[3:0]$11298 - attribute \src "libresoc.v:179171.5-179171.29" + assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181139.5-181139.29" switch \initial - attribute \src "libresoc.v:179171.9-179171.17" + attribute \src "libresoc.v:181139.9-181139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11293 $5\src23__data_o$next[3:0]$11297 + assign $1\src13__data_o$next[3:0]$11408 $5\src13__data_o$next[3:0]$11412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11294 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11409 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11294 4'0000 + assign $2\src13__data_o$next[3:0]$11409 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11295 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11410 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11295 $2\src23__data_o$next[3:0]$11294 + assign $3\src13__data_o$next[3:0]$11410 $2\src13__data_o$next[3:0]$11409 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11296 \w3__data_i + assign $4\src13__data_o$next[3:0]$11411 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11296 $3\src23__data_o$next[3:0]$11295 + assign $4\src13__data_o$next[3:0]$11411 $3\src13__data_o$next[3:0]$11410 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11297 \reg + assign $5\src13__data_o$next[3:0]$11412 \reg case - assign $5\src23__data_o$next[3:0]$11297 $4\src23__data_o$next[3:0]$11296 + assign $5\src13__data_o$next[3:0]$11412 $4\src13__data_o$next[3:0]$11411 end case - assign $1\src23__data_o$next[3:0]$11293 4'0000 + assign $1\src13__data_o$next[3:0]$11408 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11298 4'0000 + assign $6\src13__data_o$next[3:0]$11413 4'0000 case - assign $6\src23__data_o$next[3:0]$11298 $1\src23__data_o$next[3:0]$11293 + assign $6\src13__data_o$next[3:0]$11413 $1\src13__data_o$next[3:0]$11408 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11292 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 end - attribute \src "libresoc.v:179210.3-179239.6" - process $proc$libresoc.v:179210$11299 + attribute \src "libresoc.v:181178.3-181207.6" + process $proc$libresoc.v:181178$11414 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11300 $1\wr_detect$4[0:0]$11301 - attribute \src "libresoc.v:179211.5-179211.29" + assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:181179.5-181179.29" switch \initial - attribute \src "libresoc.v:179211.9-179211.17" + attribute \src "libresoc.v:181179.9-181179.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11301 $4\wr_detect$4[0:0]$11304 + assign $1\wr_detect$4[0:0]$11416 $4\wr_detect$4[0:0]$11419 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11302 1'1 + assign $2\wr_detect$4[0:0]$11417 1'1 case - assign $2\wr_detect$4[0:0]$11302 1'0 + assign $2\wr_detect$4[0:0]$11417 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11303 1'1 + assign $3\wr_detect$4[0:0]$11418 1'1 case - assign $3\wr_detect$4[0:0]$11303 $2\wr_detect$4[0:0]$11302 + assign $3\wr_detect$4[0:0]$11418 $2\wr_detect$4[0:0]$11417 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11304 1'1 + assign $4\wr_detect$4[0:0]$11419 1'1 case - assign $4\wr_detect$4[0:0]$11304 $3\wr_detect$4[0:0]$11303 + assign $4\wr_detect$4[0:0]$11419 $3\wr_detect$4[0:0]$11418 end case - assign $1\wr_detect$4[0:0]$11301 1'0 + assign $1\wr_detect$4[0:0]$11416 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11300 + update \wr_detect$4 $0\wr_detect$4[0:0]$11415 end - attribute \src "libresoc.v:179240.3-179279.6" - process $proc$libresoc.v:179240$11305 + attribute \src "libresoc.v:181208.3-181247.6" + process $proc$libresoc.v:181208$11420 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11306 $6\src33__data_o$next[3:0]$11312 - attribute \src "libresoc.v:179241.5-179241.29" + assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181209.5-181209.29" switch \initial - attribute \src "libresoc.v:179241.9-179241.17" + attribute \src "libresoc.v:181209.9-181209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11307 $5\src33__data_o$next[3:0]$11311 + assign $1\src23__data_o$next[3:0]$11422 $5\src23__data_o$next[3:0]$11426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11308 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11423 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11308 4'0000 + assign $2\src23__data_o$next[3:0]$11423 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11309 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11424 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11309 $2\src33__data_o$next[3:0]$11308 + assign $3\src23__data_o$next[3:0]$11424 $2\src23__data_o$next[3:0]$11423 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11310 \w3__data_i + assign $4\src23__data_o$next[3:0]$11425 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11310 $3\src33__data_o$next[3:0]$11309 + assign $4\src23__data_o$next[3:0]$11425 $3\src23__data_o$next[3:0]$11424 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11311 \reg + assign $5\src23__data_o$next[3:0]$11426 \reg case - assign $5\src33__data_o$next[3:0]$11311 $4\src33__data_o$next[3:0]$11310 + assign $5\src23__data_o$next[3:0]$11426 $4\src23__data_o$next[3:0]$11425 end case - assign $1\src33__data_o$next[3:0]$11307 4'0000 + assign $1\src23__data_o$next[3:0]$11422 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11312 4'0000 + assign $6\src23__data_o$next[3:0]$11427 4'0000 case - assign $6\src33__data_o$next[3:0]$11312 $1\src33__data_o$next[3:0]$11307 + assign $6\src23__data_o$next[3:0]$11427 $1\src23__data_o$next[3:0]$11422 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11306 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 end - attribute \src "libresoc.v:179280.3-179309.6" - process $proc$libresoc.v:179280$11313 + attribute \src "libresoc.v:181248.3-181277.6" + process $proc$libresoc.v:181248$11428 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11314 $1\wr_detect$7[0:0]$11315 - attribute \src "libresoc.v:179281.5-179281.29" + assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181249.5-181249.29" switch \initial - attribute \src "libresoc.v:179281.9-179281.17" + attribute \src "libresoc.v:181249.9-181249.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11315 $4\wr_detect$7[0:0]$11318 + assign $1\wr_detect$7[0:0]$11430 $4\wr_detect$7[0:0]$11433 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11316 1'1 + assign $2\wr_detect$7[0:0]$11431 1'1 case - assign $2\wr_detect$7[0:0]$11316 1'0 + assign $2\wr_detect$7[0:0]$11431 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11317 1'1 + assign $3\wr_detect$7[0:0]$11432 1'1 case - assign $3\wr_detect$7[0:0]$11317 $2\wr_detect$7[0:0]$11316 + assign $3\wr_detect$7[0:0]$11432 $2\wr_detect$7[0:0]$11431 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11318 1'1 + assign $4\wr_detect$7[0:0]$11433 1'1 case - assign $4\wr_detect$7[0:0]$11318 $3\wr_detect$7[0:0]$11317 + assign $4\wr_detect$7[0:0]$11433 $3\wr_detect$7[0:0]$11432 end case - assign $1\wr_detect$7[0:0]$11315 1'0 + assign $1\wr_detect$7[0:0]$11430 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11314 + update \wr_detect$7 $0\wr_detect$7[0:0]$11429 end - attribute \src "libresoc.v:179310.3-179349.6" - process $proc$libresoc.v:179310$11319 + attribute \src "libresoc.v:181278.3-181317.6" + process $proc$libresoc.v:181278$11434 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11320 $6\r3__data_o$next[3:0]$11326 - attribute \src "libresoc.v:179311.5-179311.29" + assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:181279.5-181279.29" switch \initial - attribute \src "libresoc.v:179311.9-179311.17" + attribute \src "libresoc.v:181279.9-181279.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11321 $5\r3__data_o$next[3:0]$11325 + assign $1\src33__data_o$next[3:0]$11436 $5\src33__data_o$next[3:0]$11440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11322 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11437 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11322 4'0000 + assign $2\src33__data_o$next[3:0]$11437 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11323 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11438 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11323 $2\r3__data_o$next[3:0]$11322 + assign $3\src33__data_o$next[3:0]$11438 $2\src33__data_o$next[3:0]$11437 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11324 \w3__data_i + assign $4\src33__data_o$next[3:0]$11439 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11324 $3\r3__data_o$next[3:0]$11323 + assign $4\src33__data_o$next[3:0]$11439 $3\src33__data_o$next[3:0]$11438 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11325 \reg + assign $5\src33__data_o$next[3:0]$11440 \reg case - assign $5\r3__data_o$next[3:0]$11325 $4\r3__data_o$next[3:0]$11324 + assign $5\src33__data_o$next[3:0]$11440 $4\src33__data_o$next[3:0]$11439 end case - assign $1\r3__data_o$next[3:0]$11321 4'0000 + assign $1\src33__data_o$next[3:0]$11436 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11326 4'0000 + assign $6\src33__data_o$next[3:0]$11441 4'0000 case - assign $6\r3__data_o$next[3:0]$11326 $1\r3__data_o$next[3:0]$11321 + assign $6\src33__data_o$next[3:0]$11441 $1\src33__data_o$next[3:0]$11436 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11320 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 end - attribute \src "libresoc.v:179350.3-179379.6" - process $proc$libresoc.v:179350$11327 + attribute \src "libresoc.v:181318.3-181347.6" + process $proc$libresoc.v:181318$11442 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11328 $1\wr_detect$10[0:0]$11329 - attribute \src "libresoc.v:179351.5-179351.29" + assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:181319.5-181319.29" switch \initial - attribute \src "libresoc.v:179351.9-179351.17" + attribute \src "libresoc.v:181319.9-181319.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11329 $4\wr_detect$10[0:0]$11332 + assign $1\wr_detect$10[0:0]$11444 $4\wr_detect$10[0:0]$11447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11330 1'1 + assign $2\wr_detect$10[0:0]$11445 1'1 case - assign $2\wr_detect$10[0:0]$11330 1'0 + assign $2\wr_detect$10[0:0]$11445 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11331 1'1 + assign $3\wr_detect$10[0:0]$11446 1'1 case - assign $3\wr_detect$10[0:0]$11331 $2\wr_detect$10[0:0]$11330 + assign $3\wr_detect$10[0:0]$11446 $2\wr_detect$10[0:0]$11445 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11332 1'1 + assign $4\wr_detect$10[0:0]$11447 1'1 case - assign $4\wr_detect$10[0:0]$11332 $3\wr_detect$10[0:0]$11331 + assign $4\wr_detect$10[0:0]$11447 $3\wr_detect$10[0:0]$11446 end case - assign $1\wr_detect$10[0:0]$11329 1'0 + assign $1\wr_detect$10[0:0]$11444 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11328 + update \wr_detect$10 $0\wr_detect$10[0:0]$11443 end - attribute \src "libresoc.v:179380.3-179419.6" - process $proc$libresoc.v:179380$11333 + attribute \src "libresoc.v:181348.3-181387.6" + process $proc$libresoc.v:181348$11448 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11334 $6\r23__data_o$next[3:0]$11340 - attribute \src "libresoc.v:179381.5-179381.29" + assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181349.5-181349.29" switch \initial - attribute \src "libresoc.v:179381.9-179381.17" + attribute \src "libresoc.v:181349.9-181349.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11335 $5\r23__data_o$next[3:0]$11339 + assign $1\r3__data_o$next[3:0]$11450 $5\r3__data_o$next[3:0]$11454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11336 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11451 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11336 4'0000 + assign $2\r3__data_o$next[3:0]$11451 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11337 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11452 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11337 $2\r23__data_o$next[3:0]$11336 + assign $3\r3__data_o$next[3:0]$11452 $2\r3__data_o$next[3:0]$11451 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11338 \w3__data_i + assign $4\r3__data_o$next[3:0]$11453 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11338 $3\r23__data_o$next[3:0]$11337 + assign $4\r3__data_o$next[3:0]$11453 $3\r3__data_o$next[3:0]$11452 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11339 \reg + assign $5\r3__data_o$next[3:0]$11454 \reg case - assign $5\r23__data_o$next[3:0]$11339 $4\r23__data_o$next[3:0]$11338 + assign $5\r3__data_o$next[3:0]$11454 $4\r3__data_o$next[3:0]$11453 end case - assign $1\r23__data_o$next[3:0]$11335 4'0000 + assign $1\r3__data_o$next[3:0]$11450 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11340 4'0000 + assign $6\r3__data_o$next[3:0]$11455 4'0000 case - assign $6\r23__data_o$next[3:0]$11340 $1\r23__data_o$next[3:0]$11335 + assign $6\r3__data_o$next[3:0]$11455 $1\r3__data_o$next[3:0]$11450 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11334 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 end - attribute \src "libresoc.v:179420.3-179449.6" - process $proc$libresoc.v:179420$11341 + attribute \src "libresoc.v:181388.3-181417.6" + process $proc$libresoc.v:181388$11456 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11342 $1\wr_detect$13[0:0]$11343 - attribute \src "libresoc.v:179421.5-179421.29" + assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:181389.5-181389.29" switch \initial - attribute \src "libresoc.v:179421.9-179421.17" + attribute \src "libresoc.v:181389.9-181389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11343 $4\wr_detect$13[0:0]$11346 + assign $1\wr_detect$13[0:0]$11458 $4\wr_detect$13[0:0]$11461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11344 1'1 + assign $2\wr_detect$13[0:0]$11459 1'1 case - assign $2\wr_detect$13[0:0]$11344 1'0 + assign $2\wr_detect$13[0:0]$11459 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11345 1'1 + assign $3\wr_detect$13[0:0]$11460 1'1 case - assign $3\wr_detect$13[0:0]$11345 $2\wr_detect$13[0:0]$11344 + assign $3\wr_detect$13[0:0]$11460 $2\wr_detect$13[0:0]$11459 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11346 1'1 + assign $4\wr_detect$13[0:0]$11461 1'1 case - assign $4\wr_detect$13[0:0]$11346 $3\wr_detect$13[0:0]$11345 + assign $4\wr_detect$13[0:0]$11461 $3\wr_detect$13[0:0]$11460 end case - assign $1\wr_detect$13[0:0]$11343 1'0 + assign $1\wr_detect$13[0:0]$11458 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11342 + update \wr_detect$13 $0\wr_detect$13[0:0]$11457 end - connect \$9 $not$libresoc.v:179056$11265_Y - connect \$12 $not$libresoc.v:179057$11266_Y - connect \$1 $not$libresoc.v:179058$11267_Y - connect \$3 $not$libresoc.v:179059$11268_Y - connect \$6 $not$libresoc.v:179060$11269_Y + connect \$9 $not$libresoc.v:180951$11364_Y + connect \$12 $not$libresoc.v:180952$11365_Y + connect \$15 $not$libresoc.v:180953$11366_Y + connect \$1 $not$libresoc.v:180954$11367_Y + connect \$3 $not$libresoc.v:180955$11368_Y + connect \$6 $not$libresoc.v:180956$11369_Y end -attribute \src "libresoc.v:179454.1-179925.10" +attribute \src "libresoc.v:181422.1-181977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:179455.7-179455.20" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 + attribute \src "libresoc.v:181528.3-181529.49" + wire width 4 $0\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181423.7-181423.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $0\r24__data_o$next[3:0]$11423 - attribute \src "libresoc.v:179538.3-179539.39" + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $0\r24__data_o$next[3:0]$11493 + attribute \src "libresoc.v:181518.3-181519.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $0\r4__data_o$next[3:0]$11409 - attribute \src "libresoc.v:179540.3-179541.37" + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $0\r4__data_o$next[3:0]$11555 + attribute \src "libresoc.v:181520.3-181521.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $0\reg$next[3:0]$11375 - attribute \src "libresoc.v:179536.3-179537.25" + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $0\reg$next[3:0]$11507 + attribute \src "libresoc.v:181516.3-181517.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $0\src14__data_o$next[3:0]$11366 - attribute \src "libresoc.v:179546.3-179547.43" + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $0\src14__data_o$next[3:0]$11513 + attribute \src "libresoc.v:181526.3-181527.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $0\src24__data_o$next[3:0]$11381 - attribute \src "libresoc.v:179544.3-179545.43" + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $0\src24__data_o$next[3:0]$11527 + attribute \src "libresoc.v:181524.3-181525.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $0\src34__data_o$next[3:0]$11395 - attribute \src "libresoc.v:179542.3-179543.43" + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $0\src34__data_o$next[3:0]$11541 + attribute \src "libresoc.v:181522.3-181523.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:179825.3-179854.6" - wire $0\wr_detect$10[0:0]$11417 - attribute \src "libresoc.v:179895.3-179924.6" - wire $0\wr_detect$13[0:0]$11431 - attribute \src "libresoc.v:179685.3-179714.6" - wire $0\wr_detect$4[0:0]$11389 - attribute \src "libresoc.v:179755.3-179784.6" - wire $0\wr_detect$7[0:0]$11403 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181877.3-181906.6" + wire $0\wr_detect$10[0:0]$11549 + attribute \src "libresoc.v:181947.3-181976.6" + wire $0\wr_detect$13[0:0]$11563 + attribute \src "libresoc.v:181640.3-181669.6" + wire $0\wr_detect$16[0:0]$11501 + attribute \src "libresoc.v:181737.3-181766.6" + wire $0\wr_detect$4[0:0]$11521 + attribute \src "libresoc.v:181807.3-181836.6" + wire $0\wr_detect$7[0:0]$11535 + attribute \src "libresoc.v:181570.3-181599.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $1\r24__data_o$next[3:0]$11424 - attribute \src "libresoc.v:179480.13-179480.31" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 + attribute \src "libresoc.v:181442.13-181442.36" + wire width 4 $1\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $1\r24__data_o$next[3:0]$11494 + attribute \src "libresoc.v:181457.13-181457.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $1\r4__data_o$next[3:0]$11410 - attribute \src "libresoc.v:179487.13-179487.30" + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $1\r4__data_o$next[3:0]$11556 + attribute \src "libresoc.v:181464.13-181464.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $1\reg$next[3:0]$11376 - attribute \src "libresoc.v:179493.13-179493.25" + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $1\reg$next[3:0]$11508 + attribute \src "libresoc.v:181470.13-181470.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $1\src14__data_o$next[3:0]$11367 - attribute \src "libresoc.v:179498.13-179498.33" + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $1\src14__data_o$next[3:0]$11514 + attribute \src "libresoc.v:181475.13-181475.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $1\src24__data_o$next[3:0]$11382 - attribute \src "libresoc.v:179505.13-179505.33" + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $1\src24__data_o$next[3:0]$11528 + attribute \src "libresoc.v:181482.13-181482.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $1\src34__data_o$next[3:0]$11396 - attribute \src "libresoc.v:179512.13-179512.33" + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $1\src34__data_o$next[3:0]$11542 + attribute \src "libresoc.v:181489.13-181489.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:179825.3-179854.6" - wire $1\wr_detect$10[0:0]$11418 - attribute \src "libresoc.v:179895.3-179924.6" - wire $1\wr_detect$13[0:0]$11432 - attribute \src "libresoc.v:179685.3-179714.6" - wire $1\wr_detect$4[0:0]$11390 - attribute \src "libresoc.v:179755.3-179784.6" - wire $1\wr_detect$7[0:0]$11404 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181877.3-181906.6" + wire $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181947.3-181976.6" + wire $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181640.3-181669.6" + wire $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181737.3-181766.6" + wire $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181807.3-181836.6" + wire $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181570.3-181599.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $2\r24__data_o$next[3:0]$11425 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $2\r4__data_o$next[3:0]$11411 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $2\reg$next[3:0]$11377 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $2\src14__data_o$next[3:0]$11368 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $2\src24__data_o$next[3:0]$11383 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $2\src34__data_o$next[3:0]$11397 - attribute \src "libresoc.v:179825.3-179854.6" - wire $2\wr_detect$10[0:0]$11419 - attribute \src "libresoc.v:179895.3-179924.6" - wire $2\wr_detect$13[0:0]$11433 - attribute \src "libresoc.v:179685.3-179714.6" - wire $2\wr_detect$4[0:0]$11391 - attribute \src "libresoc.v:179755.3-179784.6" - wire $2\wr_detect$7[0:0]$11405 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $2\r24__data_o$next[3:0]$11495 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $2\r4__data_o$next[3:0]$11557 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $2\reg$next[3:0]$11509 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $2\src14__data_o$next[3:0]$11515 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $2\src24__data_o$next[3:0]$11529 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $2\src34__data_o$next[3:0]$11543 + attribute \src "libresoc.v:181877.3-181906.6" + wire $2\wr_detect$10[0:0]$11551 + attribute \src "libresoc.v:181947.3-181976.6" + wire $2\wr_detect$13[0:0]$11565 + attribute \src "libresoc.v:181640.3-181669.6" + wire $2\wr_detect$16[0:0]$11503 + attribute \src "libresoc.v:181737.3-181766.6" + wire $2\wr_detect$4[0:0]$11523 + attribute \src "libresoc.v:181807.3-181836.6" + wire $2\wr_detect$7[0:0]$11537 + attribute \src "libresoc.v:181570.3-181599.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $3\r24__data_o$next[3:0]$11426 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $3\r4__data_o$next[3:0]$11412 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $3\reg$next[3:0]$11378 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $3\src14__data_o$next[3:0]$11369 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $3\src24__data_o$next[3:0]$11384 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $3\src34__data_o$next[3:0]$11398 - attribute \src "libresoc.v:179825.3-179854.6" - wire $3\wr_detect$10[0:0]$11420 - attribute \src "libresoc.v:179895.3-179924.6" - wire $3\wr_detect$13[0:0]$11434 - attribute \src "libresoc.v:179685.3-179714.6" - wire $3\wr_detect$4[0:0]$11392 - attribute \src "libresoc.v:179755.3-179784.6" - wire $3\wr_detect$7[0:0]$11406 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $3\r24__data_o$next[3:0]$11496 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $3\r4__data_o$next[3:0]$11558 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $3\reg$next[3:0]$11510 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $3\src14__data_o$next[3:0]$11516 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $3\src24__data_o$next[3:0]$11530 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $3\src34__data_o$next[3:0]$11544 + attribute \src "libresoc.v:181877.3-181906.6" + wire $3\wr_detect$10[0:0]$11552 + attribute \src "libresoc.v:181947.3-181976.6" + wire $3\wr_detect$13[0:0]$11566 + attribute \src "libresoc.v:181640.3-181669.6" + wire $3\wr_detect$16[0:0]$11504 + attribute \src "libresoc.v:181737.3-181766.6" + wire $3\wr_detect$4[0:0]$11524 + attribute \src "libresoc.v:181807.3-181836.6" + wire $3\wr_detect$7[0:0]$11538 + attribute \src "libresoc.v:181570.3-181599.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $4\r24__data_o$next[3:0]$11427 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $4\r4__data_o$next[3:0]$11413 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $4\reg$next[3:0]$11379 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $4\src14__data_o$next[3:0]$11370 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $4\src24__data_o$next[3:0]$11385 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $4\src34__data_o$next[3:0]$11399 - attribute \src "libresoc.v:179825.3-179854.6" - wire $4\wr_detect$10[0:0]$11421 - attribute \src "libresoc.v:179895.3-179924.6" - wire $4\wr_detect$13[0:0]$11435 - attribute \src "libresoc.v:179685.3-179714.6" - wire $4\wr_detect$4[0:0]$11393 - attribute \src "libresoc.v:179755.3-179784.6" - wire $4\wr_detect$7[0:0]$11407 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $4\r24__data_o$next[3:0]$11497 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $4\r4__data_o$next[3:0]$11559 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $4\src14__data_o$next[3:0]$11517 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $4\src24__data_o$next[3:0]$11531 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $4\src34__data_o$next[3:0]$11545 + attribute \src "libresoc.v:181877.3-181906.6" + wire $4\wr_detect$10[0:0]$11553 + attribute \src "libresoc.v:181947.3-181976.6" + wire $4\wr_detect$13[0:0]$11567 + attribute \src "libresoc.v:181640.3-181669.6" + wire $4\wr_detect$16[0:0]$11505 + attribute \src "libresoc.v:181737.3-181766.6" + wire $4\wr_detect$4[0:0]$11525 + attribute \src "libresoc.v:181807.3-181836.6" + wire $4\wr_detect$7[0:0]$11539 + attribute \src "libresoc.v:181570.3-181599.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $5\r24__data_o$next[3:0]$11428 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $5\r4__data_o$next[3:0]$11414 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $5\src14__data_o$next[3:0]$11371 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $5\src24__data_o$next[3:0]$11386 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $5\src34__data_o$next[3:0]$11400 - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $6\r24__data_o$next[3:0]$11429 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $6\r4__data_o$next[3:0]$11415 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $6\src14__data_o$next[3:0]$11372 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $6\src24__data_o$next[3:0]$11387 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $6\src34__data_o$next[3:0]$11401 - attribute \src "libresoc.v:179531.17-179531.104" - wire $not$libresoc.v:179531$11354_Y - attribute \src "libresoc.v:179532.18-179532.105" - wire $not$libresoc.v:179532$11355_Y - attribute \src "libresoc.v:179533.17-179533.100" - wire $not$libresoc.v:179533$11356_Y - attribute \src "libresoc.v:179534.17-179534.103" - wire $not$libresoc.v:179534$11357_Y - attribute \src "libresoc.v:179535.17-179535.103" - wire $not$libresoc.v:179535$11358_Y + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $5\r24__data_o$next[3:0]$11498 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $5\r4__data_o$next[3:0]$11560 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $5\src14__data_o$next[3:0]$11518 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $5\src24__data_o$next[3:0]$11532 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $5\src34__data_o$next[3:0]$11546 + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181510.17-181510.104" + wire $not$libresoc.v:181510$11470_Y + attribute \src "libresoc.v:181511.18-181511.105" + wire $not$libresoc.v:181511$11471_Y + attribute \src "libresoc.v:181512.18-181512.105" + wire $not$libresoc.v:181512$11472_Y + attribute \src "libresoc.v:181513.17-181513.100" + wire $not$libresoc.v:181513$11473_Y + attribute \src "libresoc.v:181514.17-181514.103" + wire $not$libresoc.v:181514$11474_Y + attribute \src "libresoc.v:181515.17-181515.103" + wire $not$libresoc.v:181515$11475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest14__data_i + wire width 4 output 3 \cr_pred4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest14__wen + wire input 10 \dest14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest24__data_i + wire width 4 input 13 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest24__wen - attribute \src "libresoc.v:179455.7-179455.15" + wire input 12 \dest24__wen + attribute \src "libresoc.v:181423.7-181423.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r24__data_o + wire width 4 output 16 \r24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r24__ren + wire input 17 \r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r4__data_o + wire width 4 output 14 \r4__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r4__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r4__ren + wire input 15 \r4__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src14__data_o + wire width 4 output 5 \src14__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src14__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src14__ren + wire input 4 \src14__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src24__data_o + wire width 4 output 7 \src24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src24__ren + wire input 6 \src24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src34__data_o + wire width 4 output 9 \src34__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src34__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src34__ren + wire input 8 \src34__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w4__data_i + wire width 4 input 18 \w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w4__wen + wire input 19 \w4__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -370116,232 +373407,257 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179531$11354 + cell $not $not$libresoc.v:181510$11470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179531$11354_Y + connect \Y $not$libresoc.v:181510$11470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179532$11355 + cell $not $not$libresoc.v:181511$11471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179532$11355_Y + connect \Y $not$libresoc.v:181511$11471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179533$11356 + cell $not $not$libresoc.v:181512$11472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:181512$11472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181513$11473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179533$11356_Y + connect \Y $not$libresoc.v:181513$11473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179534$11357 + cell $not $not$libresoc.v:181514$11474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179534$11357_Y + connect \Y $not$libresoc.v:181514$11474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179535$11358 + cell $not $not$libresoc.v:181515$11475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179535$11358_Y + connect \Y $not$libresoc.v:181515$11475_Y end - attribute \src "libresoc.v:179455.7-179455.20" - process $proc$libresoc.v:179455$11436 + attribute \src "libresoc.v:181423.7-181423.20" + process $proc$libresoc.v:181423$11568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179480.13-179480.31" - process $proc$libresoc.v:179480$11437 + attribute \src "libresoc.v:181442.13-181442.36" + process $proc$libresoc.v:181442$11569 + assign { } { } + assign $1\cr_pred4__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181457.13-181457.31" + process $proc$libresoc.v:181457$11570 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:179487.13-179487.30" - process $proc$libresoc.v:179487$11438 + attribute \src "libresoc.v:181464.13-181464.30" + process $proc$libresoc.v:181464$11571 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:179493.13-179493.25" - process $proc$libresoc.v:179493$11439 + attribute \src "libresoc.v:181470.13-181470.25" + process $proc$libresoc.v:181470$11572 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179498.13-179498.33" - process $proc$libresoc.v:179498$11440 + attribute \src "libresoc.v:181475.13-181475.33" + process $proc$libresoc.v:181475$11573 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:179505.13-179505.33" - process $proc$libresoc.v:179505$11441 + attribute \src "libresoc.v:181482.13-181482.33" + process $proc$libresoc.v:181482$11574 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:179512.13-179512.33" - process $proc$libresoc.v:179512$11442 + attribute \src "libresoc.v:181489.13-181489.33" + process $proc$libresoc.v:181489$11575 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:179536.3-179537.25" - process $proc$libresoc.v:179536$11359 + attribute \src "libresoc.v:181516.3-181517.25" + process $proc$libresoc.v:181516$11476 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179538.3-179539.39" - process $proc$libresoc.v:179538$11360 + attribute \src "libresoc.v:181518.3-181519.39" + process $proc$libresoc.v:181518$11477 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:179540.3-179541.37" - process $proc$libresoc.v:179540$11361 + attribute \src "libresoc.v:181520.3-181521.37" + process $proc$libresoc.v:181520$11478 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:179542.3-179543.43" - process $proc$libresoc.v:179542$11362 + attribute \src "libresoc.v:181522.3-181523.43" + process $proc$libresoc.v:181522$11479 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:179544.3-179545.43" - process $proc$libresoc.v:179544$11363 + attribute \src "libresoc.v:181524.3-181525.43" + process $proc$libresoc.v:181524$11480 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:179546.3-179547.43" - process $proc$libresoc.v:179546$11364 + attribute \src "libresoc.v:181526.3-181527.43" + process $proc$libresoc.v:181526$11481 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:179548.3-179587.6" - process $proc$libresoc.v:179548$11365 + attribute \src "libresoc.v:181528.3-181529.49" + process $proc$libresoc.v:181528$11482 assign { } { } + assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next + sync posedge \coresync_clk + update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181530.3-181569.6" + process $proc$libresoc.v:181530$11483 assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11366 $6\src14__data_o$next[3:0]$11372 - attribute \src "libresoc.v:179549.5-179549.29" + assign { } { } + assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181531.5-181531.29" switch \initial - attribute \src "libresoc.v:179549.9-179549.17" + attribute \src "libresoc.v:181531.9-181531.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + switch \cr_pred4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11367 $5\src14__data_o$next[3:0]$11371 + assign $1\cr_pred4__data_o$next[3:0]$11485 $5\cr_pred4__data_o$next[3:0]$11489 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11368 \dest14__data_i + assign $2\cr_pred4__data_o$next[3:0]$11486 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11368 4'0000 + assign $2\cr_pred4__data_o$next[3:0]$11486 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11369 \dest24__data_i + assign $3\cr_pred4__data_o$next[3:0]$11487 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11369 $2\src14__data_o$next[3:0]$11368 + assign $3\cr_pred4__data_o$next[3:0]$11487 $2\cr_pred4__data_o$next[3:0]$11486 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11370 \w4__data_i + assign $4\cr_pred4__data_o$next[3:0]$11488 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11370 $3\src14__data_o$next[3:0]$11369 + assign $4\cr_pred4__data_o$next[3:0]$11488 $3\cr_pred4__data_o$next[3:0]$11487 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11371 \reg + assign $5\cr_pred4__data_o$next[3:0]$11489 \reg case - assign $5\src14__data_o$next[3:0]$11371 $4\src14__data_o$next[3:0]$11370 + assign $5\cr_pred4__data_o$next[3:0]$11489 $4\cr_pred4__data_o$next[3:0]$11488 end case - assign $1\src14__data_o$next[3:0]$11367 4'0000 + assign $1\cr_pred4__data_o$next[3:0]$11485 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11372 4'0000 + assign $6\cr_pred4__data_o$next[3:0]$11490 4'0000 case - assign $6\src14__data_o$next[3:0]$11372 $1\src14__data_o$next[3:0]$11367 + assign $6\cr_pred4__data_o$next[3:0]$11490 $1\cr_pred4__data_o$next[3:0]$11485 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11366 + update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 end - attribute \src "libresoc.v:179588.3-179617.6" - process $proc$libresoc.v:179588$11373 + attribute \src "libresoc.v:181570.3-181599.6" + process $proc$libresoc.v:181570$11491 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179589.5-179589.29" + attribute \src "libresoc.v:181571.5-181571.29" switch \initial - attribute \src "libresoc.v:179589.9-179589.17" + attribute \src "libresoc.v:181571.9-181571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + switch \cr_pred4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -370382,798 +373698,962 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179618.3-179644.6" - process $proc$libresoc.v:179618$11374 - assign { } { } - assign { } { } + attribute \src "libresoc.v:181600.3-181639.6" + process $proc$libresoc.v:181600$11492 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11375 $4\reg$next[3:0]$11379 - attribute \src "libresoc.v:179619.5-179619.29" + assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181601.5-181601.29" switch \initial - attribute \src "libresoc.v:179619.9-179619.17" + attribute \src "libresoc.v:181601.9-181601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest14__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11376 \dest14__data_i - case - assign $1\reg$next[3:0]$11376 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11377 \dest24__data_i - case - assign $2\reg$next[3:0]$11377 $1\reg$next[3:0]$11376 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11378 \w4__data_i + assign { } { } + assign $1\r24__data_o$next[3:0]$11494 $5\r24__data_o$next[3:0]$11498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$11495 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$11495 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$11496 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$11496 $2\r24__data_o$next[3:0]$11495 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$11497 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$11497 $3\r24__data_o$next[3:0]$11496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$11498 \reg + case + assign $5\r24__data_o$next[3:0]$11498 $4\r24__data_o$next[3:0]$11497 + end case - assign $3\reg$next[3:0]$11378 $2\reg$next[3:0]$11377 + assign $1\r24__data_o$next[3:0]$11494 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11379 4'0000 + assign $6\r24__data_o$next[3:0]$11499 4'0000 case - assign $4\reg$next[3:0]$11379 $3\reg$next[3:0]$11378 + assign $6\r24__data_o$next[3:0]$11499 $1\r24__data_o$next[3:0]$11494 end sync always - update \reg$next $0\reg$next[3:0]$11375 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 end - attribute \src "libresoc.v:179645.3-179684.6" - process $proc$libresoc.v:179645$11380 - assign { } { } + attribute \src "libresoc.v:181640.3-181669.6" + process $proc$libresoc.v:181640$11500 assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11381 $6\src24__data_o$next[3:0]$11387 - attribute \src "libresoc.v:179646.5-179646.29" + assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181641.5-181641.29" switch \initial - attribute \src "libresoc.v:179646.9-179646.17" + attribute \src "libresoc.v:181641.9-181641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11382 $5\src24__data_o$next[3:0]$11386 + assign $1\wr_detect$16[0:0]$11502 $4\wr_detect$16[0:0]$11505 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11383 \dest14__data_i + assign $2\wr_detect$16[0:0]$11503 1'1 case - assign $2\src24__data_o$next[3:0]$11383 4'0000 + assign $2\wr_detect$16[0:0]$11503 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11384 \dest24__data_i + assign $3\wr_detect$16[0:0]$11504 1'1 case - assign $3\src24__data_o$next[3:0]$11384 $2\src24__data_o$next[3:0]$11383 + assign $3\wr_detect$16[0:0]$11504 $2\wr_detect$16[0:0]$11503 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11385 \w4__data_i + assign $4\wr_detect$16[0:0]$11505 1'1 case - assign $4\src24__data_o$next[3:0]$11385 $3\src24__data_o$next[3:0]$11384 + assign $4\wr_detect$16[0:0]$11505 $3\wr_detect$16[0:0]$11504 + end + case + assign $1\wr_detect$16[0:0]$11502 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11501 + end + attribute \src "libresoc.v:181670.3-181696.6" + process $proc$libresoc.v:181670$11506 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181671.5-181671.29" + switch \initial + attribute \src "libresoc.v:181671.9-181671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11508 \dest14__data_i + case + assign $1\reg$next[3:0]$11508 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11509 \dest24__data_i + case + assign $2\reg$next[3:0]$11509 $1\reg$next[3:0]$11508 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11510 \w4__data_i + case + assign $3\reg$next[3:0]$11510 $2\reg$next[3:0]$11509 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11511 4'0000 + case + assign $4\reg$next[3:0]$11511 $3\reg$next[3:0]$11510 + end + sync always + update \reg$next $0\reg$next[3:0]$11507 + end + attribute \src "libresoc.v:181697.3-181736.6" + process $proc$libresoc.v:181697$11512 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181698.5-181698.29" + switch \initial + attribute \src "libresoc.v:181698.9-181698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$11514 $5\src14__data_o$next[3:0]$11518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$11515 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$11515 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$11516 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$11516 $2\src14__data_o$next[3:0]$11515 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$11517 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$11517 $3\src14__data_o$next[3:0]$11516 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11386 \reg + assign $5\src14__data_o$next[3:0]$11518 \reg case - assign $5\src24__data_o$next[3:0]$11386 $4\src24__data_o$next[3:0]$11385 + assign $5\src14__data_o$next[3:0]$11518 $4\src14__data_o$next[3:0]$11517 end case - assign $1\src24__data_o$next[3:0]$11382 4'0000 + assign $1\src14__data_o$next[3:0]$11514 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11387 4'0000 + assign $6\src14__data_o$next[3:0]$11519 4'0000 case - assign $6\src24__data_o$next[3:0]$11387 $1\src24__data_o$next[3:0]$11382 + assign $6\src14__data_o$next[3:0]$11519 $1\src14__data_o$next[3:0]$11514 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11381 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 end - attribute \src "libresoc.v:179685.3-179714.6" - process $proc$libresoc.v:179685$11388 + attribute \src "libresoc.v:181737.3-181766.6" + process $proc$libresoc.v:181737$11520 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11389 $1\wr_detect$4[0:0]$11390 - attribute \src "libresoc.v:179686.5-179686.29" + assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181738.5-181738.29" switch \initial - attribute \src "libresoc.v:179686.9-179686.17" + attribute \src "libresoc.v:181738.9-181738.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11390 $4\wr_detect$4[0:0]$11393 + assign $1\wr_detect$4[0:0]$11522 $4\wr_detect$4[0:0]$11525 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11391 1'1 + assign $2\wr_detect$4[0:0]$11523 1'1 case - assign $2\wr_detect$4[0:0]$11391 1'0 + assign $2\wr_detect$4[0:0]$11523 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11392 1'1 + assign $3\wr_detect$4[0:0]$11524 1'1 case - assign $3\wr_detect$4[0:0]$11392 $2\wr_detect$4[0:0]$11391 + assign $3\wr_detect$4[0:0]$11524 $2\wr_detect$4[0:0]$11523 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11393 1'1 + assign $4\wr_detect$4[0:0]$11525 1'1 case - assign $4\wr_detect$4[0:0]$11393 $3\wr_detect$4[0:0]$11392 + assign $4\wr_detect$4[0:0]$11525 $3\wr_detect$4[0:0]$11524 end case - assign $1\wr_detect$4[0:0]$11390 1'0 + assign $1\wr_detect$4[0:0]$11522 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11389 + update \wr_detect$4 $0\wr_detect$4[0:0]$11521 end - attribute \src "libresoc.v:179715.3-179754.6" - process $proc$libresoc.v:179715$11394 + attribute \src "libresoc.v:181767.3-181806.6" + process $proc$libresoc.v:181767$11526 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11395 $6\src34__data_o$next[3:0]$11401 - attribute \src "libresoc.v:179716.5-179716.29" + assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181768.5-181768.29" switch \initial - attribute \src "libresoc.v:179716.9-179716.17" + attribute \src "libresoc.v:181768.9-181768.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11396 $5\src34__data_o$next[3:0]$11400 + assign $1\src24__data_o$next[3:0]$11528 $5\src24__data_o$next[3:0]$11532 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11397 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11529 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11397 4'0000 + assign $2\src24__data_o$next[3:0]$11529 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11398 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11530 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11398 $2\src34__data_o$next[3:0]$11397 + assign $3\src24__data_o$next[3:0]$11530 $2\src24__data_o$next[3:0]$11529 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11399 \w4__data_i + assign $4\src24__data_o$next[3:0]$11531 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11399 $3\src34__data_o$next[3:0]$11398 + assign $4\src24__data_o$next[3:0]$11531 $3\src24__data_o$next[3:0]$11530 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11400 \reg + assign $5\src24__data_o$next[3:0]$11532 \reg case - assign $5\src34__data_o$next[3:0]$11400 $4\src34__data_o$next[3:0]$11399 + assign $5\src24__data_o$next[3:0]$11532 $4\src24__data_o$next[3:0]$11531 end case - assign $1\src34__data_o$next[3:0]$11396 4'0000 + assign $1\src24__data_o$next[3:0]$11528 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11401 4'0000 + assign $6\src24__data_o$next[3:0]$11533 4'0000 case - assign $6\src34__data_o$next[3:0]$11401 $1\src34__data_o$next[3:0]$11396 + assign $6\src24__data_o$next[3:0]$11533 $1\src24__data_o$next[3:0]$11528 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11395 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 end - attribute \src "libresoc.v:179755.3-179784.6" - process $proc$libresoc.v:179755$11402 + attribute \src "libresoc.v:181807.3-181836.6" + process $proc$libresoc.v:181807$11534 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11403 $1\wr_detect$7[0:0]$11404 - attribute \src "libresoc.v:179756.5-179756.29" + assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181808.5-181808.29" switch \initial - attribute \src "libresoc.v:179756.9-179756.17" + attribute \src "libresoc.v:181808.9-181808.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11404 $4\wr_detect$7[0:0]$11407 + assign $1\wr_detect$7[0:0]$11536 $4\wr_detect$7[0:0]$11539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11405 1'1 + assign $2\wr_detect$7[0:0]$11537 1'1 case - assign $2\wr_detect$7[0:0]$11405 1'0 + assign $2\wr_detect$7[0:0]$11537 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11406 1'1 + assign $3\wr_detect$7[0:0]$11538 1'1 case - assign $3\wr_detect$7[0:0]$11406 $2\wr_detect$7[0:0]$11405 + assign $3\wr_detect$7[0:0]$11538 $2\wr_detect$7[0:0]$11537 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11407 1'1 + assign $4\wr_detect$7[0:0]$11539 1'1 case - assign $4\wr_detect$7[0:0]$11407 $3\wr_detect$7[0:0]$11406 + assign $4\wr_detect$7[0:0]$11539 $3\wr_detect$7[0:0]$11538 end case - assign $1\wr_detect$7[0:0]$11404 1'0 + assign $1\wr_detect$7[0:0]$11536 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11403 + update \wr_detect$7 $0\wr_detect$7[0:0]$11535 end - attribute \src "libresoc.v:179785.3-179824.6" - process $proc$libresoc.v:179785$11408 + attribute \src "libresoc.v:181837.3-181876.6" + process $proc$libresoc.v:181837$11540 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11409 $6\r4__data_o$next[3:0]$11415 - attribute \src "libresoc.v:179786.5-179786.29" + assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181838.5-181838.29" switch \initial - attribute \src "libresoc.v:179786.9-179786.17" + attribute \src "libresoc.v:181838.9-181838.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11410 $5\r4__data_o$next[3:0]$11414 + assign $1\src34__data_o$next[3:0]$11542 $5\src34__data_o$next[3:0]$11546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11411 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11543 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11411 4'0000 + assign $2\src34__data_o$next[3:0]$11543 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11412 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11544 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11412 $2\r4__data_o$next[3:0]$11411 + assign $3\src34__data_o$next[3:0]$11544 $2\src34__data_o$next[3:0]$11543 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11413 \w4__data_i + assign $4\src34__data_o$next[3:0]$11545 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11413 $3\r4__data_o$next[3:0]$11412 + assign $4\src34__data_o$next[3:0]$11545 $3\src34__data_o$next[3:0]$11544 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11414 \reg + assign $5\src34__data_o$next[3:0]$11546 \reg case - assign $5\r4__data_o$next[3:0]$11414 $4\r4__data_o$next[3:0]$11413 + assign $5\src34__data_o$next[3:0]$11546 $4\src34__data_o$next[3:0]$11545 end case - assign $1\r4__data_o$next[3:0]$11410 4'0000 + assign $1\src34__data_o$next[3:0]$11542 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11415 4'0000 + assign $6\src34__data_o$next[3:0]$11547 4'0000 case - assign $6\r4__data_o$next[3:0]$11415 $1\r4__data_o$next[3:0]$11410 + assign $6\src34__data_o$next[3:0]$11547 $1\src34__data_o$next[3:0]$11542 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11409 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 end - attribute \src "libresoc.v:179825.3-179854.6" - process $proc$libresoc.v:179825$11416 + attribute \src "libresoc.v:181877.3-181906.6" + process $proc$libresoc.v:181877$11548 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11417 $1\wr_detect$10[0:0]$11418 - attribute \src "libresoc.v:179826.5-179826.29" + assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181878.5-181878.29" switch \initial - attribute \src "libresoc.v:179826.9-179826.17" + attribute \src "libresoc.v:181878.9-181878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11418 $4\wr_detect$10[0:0]$11421 + assign $1\wr_detect$10[0:0]$11550 $4\wr_detect$10[0:0]$11553 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11419 1'1 + assign $2\wr_detect$10[0:0]$11551 1'1 case - assign $2\wr_detect$10[0:0]$11419 1'0 + assign $2\wr_detect$10[0:0]$11551 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11420 1'1 + assign $3\wr_detect$10[0:0]$11552 1'1 case - assign $3\wr_detect$10[0:0]$11420 $2\wr_detect$10[0:0]$11419 + assign $3\wr_detect$10[0:0]$11552 $2\wr_detect$10[0:0]$11551 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11421 1'1 + assign $4\wr_detect$10[0:0]$11553 1'1 case - assign $4\wr_detect$10[0:0]$11421 $3\wr_detect$10[0:0]$11420 + assign $4\wr_detect$10[0:0]$11553 $3\wr_detect$10[0:0]$11552 end case - assign $1\wr_detect$10[0:0]$11418 1'0 + assign $1\wr_detect$10[0:0]$11550 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11417 + update \wr_detect$10 $0\wr_detect$10[0:0]$11549 end - attribute \src "libresoc.v:179855.3-179894.6" - process $proc$libresoc.v:179855$11422 + attribute \src "libresoc.v:181907.3-181946.6" + process $proc$libresoc.v:181907$11554 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11423 $6\r24__data_o$next[3:0]$11429 - attribute \src "libresoc.v:179856.5-179856.29" + assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181908.5-181908.29" switch \initial - attribute \src "libresoc.v:179856.9-179856.17" + attribute \src "libresoc.v:181908.9-181908.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11424 $5\r24__data_o$next[3:0]$11428 + assign $1\r4__data_o$next[3:0]$11556 $5\r4__data_o$next[3:0]$11560 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11425 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11557 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11425 4'0000 + assign $2\r4__data_o$next[3:0]$11557 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11426 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11558 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11426 $2\r24__data_o$next[3:0]$11425 + assign $3\r4__data_o$next[3:0]$11558 $2\r4__data_o$next[3:0]$11557 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11427 \w4__data_i + assign $4\r4__data_o$next[3:0]$11559 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11427 $3\r24__data_o$next[3:0]$11426 + assign $4\r4__data_o$next[3:0]$11559 $3\r4__data_o$next[3:0]$11558 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11428 \reg + assign $5\r4__data_o$next[3:0]$11560 \reg case - assign $5\r24__data_o$next[3:0]$11428 $4\r24__data_o$next[3:0]$11427 + assign $5\r4__data_o$next[3:0]$11560 $4\r4__data_o$next[3:0]$11559 end case - assign $1\r24__data_o$next[3:0]$11424 4'0000 + assign $1\r4__data_o$next[3:0]$11556 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11429 4'0000 + assign $6\r4__data_o$next[3:0]$11561 4'0000 case - assign $6\r24__data_o$next[3:0]$11429 $1\r24__data_o$next[3:0]$11424 + assign $6\r4__data_o$next[3:0]$11561 $1\r4__data_o$next[3:0]$11556 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11423 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 end - attribute \src "libresoc.v:179895.3-179924.6" - process $proc$libresoc.v:179895$11430 + attribute \src "libresoc.v:181947.3-181976.6" + process $proc$libresoc.v:181947$11562 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11431 $1\wr_detect$13[0:0]$11432 - attribute \src "libresoc.v:179896.5-179896.29" + assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181948.5-181948.29" switch \initial - attribute \src "libresoc.v:179896.9-179896.17" + attribute \src "libresoc.v:181948.9-181948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11432 $4\wr_detect$13[0:0]$11435 + assign $1\wr_detect$13[0:0]$11564 $4\wr_detect$13[0:0]$11567 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11433 1'1 + assign $2\wr_detect$13[0:0]$11565 1'1 case - assign $2\wr_detect$13[0:0]$11433 1'0 + assign $2\wr_detect$13[0:0]$11565 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11434 1'1 + assign $3\wr_detect$13[0:0]$11566 1'1 case - assign $3\wr_detect$13[0:0]$11434 $2\wr_detect$13[0:0]$11433 + assign $3\wr_detect$13[0:0]$11566 $2\wr_detect$13[0:0]$11565 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11435 1'1 + assign $4\wr_detect$13[0:0]$11567 1'1 case - assign $4\wr_detect$13[0:0]$11435 $3\wr_detect$13[0:0]$11434 + assign $4\wr_detect$13[0:0]$11567 $3\wr_detect$13[0:0]$11566 end case - assign $1\wr_detect$13[0:0]$11432 1'0 + assign $1\wr_detect$13[0:0]$11564 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11431 + update \wr_detect$13 $0\wr_detect$13[0:0]$11563 end - connect \$9 $not$libresoc.v:179531$11354_Y - connect \$12 $not$libresoc.v:179532$11355_Y - connect \$1 $not$libresoc.v:179533$11356_Y - connect \$3 $not$libresoc.v:179534$11357_Y - connect \$6 $not$libresoc.v:179535$11358_Y + connect \$9 $not$libresoc.v:181510$11470_Y + connect \$12 $not$libresoc.v:181511$11471_Y + connect \$15 $not$libresoc.v:181512$11472_Y + connect \$1 $not$libresoc.v:181513$11473_Y + connect \$3 $not$libresoc.v:181514$11474_Y + connect \$6 $not$libresoc.v:181515$11475_Y end -attribute \src "libresoc.v:179929.1-180400.10" +attribute \src "libresoc.v:181981.1-182536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:179930.7-179930.20" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 + attribute \src "libresoc.v:182087.3-182088.49" + wire width 4 $0\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:181982.7-181982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $0\r25__data_o$next[3:0]$11512 - attribute \src "libresoc.v:180013.3-180014.39" + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $0\r25__data_o$next[3:0]$11599 + attribute \src "libresoc.v:182077.3-182078.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $0\r5__data_o$next[3:0]$11498 - attribute \src "libresoc.v:180015.3-180016.37" + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $0\r5__data_o$next[3:0]$11661 + attribute \src "libresoc.v:182079.3-182080.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $0\reg$next[3:0]$11464 - attribute \src "libresoc.v:180011.3-180012.25" + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $0\reg$next[3:0]$11613 + attribute \src "libresoc.v:182075.3-182076.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $0\src15__data_o$next[3:0]$11455 - attribute \src "libresoc.v:180021.3-180022.43" + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $0\src15__data_o$next[3:0]$11619 + attribute \src "libresoc.v:182085.3-182086.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $0\src25__data_o$next[3:0]$11470 - attribute \src "libresoc.v:180019.3-180020.43" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $0\src25__data_o$next[3:0]$11633 + attribute \src "libresoc.v:182083.3-182084.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $0\src35__data_o$next[3:0]$11484 - attribute \src "libresoc.v:180017.3-180018.43" + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $0\src35__data_o$next[3:0]$11647 + attribute \src "libresoc.v:182081.3-182082.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:180300.3-180329.6" - wire $0\wr_detect$10[0:0]$11506 - attribute \src "libresoc.v:180370.3-180399.6" - wire $0\wr_detect$13[0:0]$11520 - attribute \src "libresoc.v:180160.3-180189.6" - wire $0\wr_detect$4[0:0]$11478 - attribute \src "libresoc.v:180230.3-180259.6" - wire $0\wr_detect$7[0:0]$11492 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182436.3-182465.6" + wire $0\wr_detect$10[0:0]$11655 + attribute \src "libresoc.v:182506.3-182535.6" + wire $0\wr_detect$13[0:0]$11669 + attribute \src "libresoc.v:182199.3-182228.6" + wire $0\wr_detect$16[0:0]$11607 + attribute \src "libresoc.v:182296.3-182325.6" + wire $0\wr_detect$4[0:0]$11627 + attribute \src "libresoc.v:182366.3-182395.6" + wire $0\wr_detect$7[0:0]$11641 + attribute \src "libresoc.v:182129.3-182158.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $1\r25__data_o$next[3:0]$11513 - attribute \src "libresoc.v:179955.13-179955.31" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 + attribute \src "libresoc.v:182001.13-182001.36" + wire width 4 $1\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $1\r25__data_o$next[3:0]$11600 + attribute \src "libresoc.v:182016.13-182016.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $1\r5__data_o$next[3:0]$11499 - attribute \src "libresoc.v:179962.13-179962.30" + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $1\r5__data_o$next[3:0]$11662 + attribute \src "libresoc.v:182023.13-182023.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $1\reg$next[3:0]$11465 - attribute \src "libresoc.v:179968.13-179968.25" + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $1\reg$next[3:0]$11614 + attribute \src "libresoc.v:182029.13-182029.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $1\src15__data_o$next[3:0]$11456 - attribute \src "libresoc.v:179973.13-179973.33" + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $1\src15__data_o$next[3:0]$11620 + attribute \src "libresoc.v:182034.13-182034.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $1\src25__data_o$next[3:0]$11471 - attribute \src "libresoc.v:179980.13-179980.33" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $1\src25__data_o$next[3:0]$11634 + attribute \src "libresoc.v:182041.13-182041.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $1\src35__data_o$next[3:0]$11485 - attribute \src "libresoc.v:179987.13-179987.33" + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $1\src35__data_o$next[3:0]$11648 + attribute \src "libresoc.v:182048.13-182048.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:180300.3-180329.6" - wire $1\wr_detect$10[0:0]$11507 - attribute \src "libresoc.v:180370.3-180399.6" - wire $1\wr_detect$13[0:0]$11521 - attribute \src "libresoc.v:180160.3-180189.6" - wire $1\wr_detect$4[0:0]$11479 - attribute \src "libresoc.v:180230.3-180259.6" - wire $1\wr_detect$7[0:0]$11493 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182436.3-182465.6" + wire $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182506.3-182535.6" + wire $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182199.3-182228.6" + wire $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182296.3-182325.6" + wire $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182366.3-182395.6" + wire $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182129.3-182158.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $2\r25__data_o$next[3:0]$11514 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $2\r5__data_o$next[3:0]$11500 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $2\reg$next[3:0]$11466 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $2\src15__data_o$next[3:0]$11457 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $2\src25__data_o$next[3:0]$11472 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $2\src35__data_o$next[3:0]$11486 - attribute \src "libresoc.v:180300.3-180329.6" - wire $2\wr_detect$10[0:0]$11508 - attribute \src "libresoc.v:180370.3-180399.6" - wire $2\wr_detect$13[0:0]$11522 - attribute \src "libresoc.v:180160.3-180189.6" - wire $2\wr_detect$4[0:0]$11480 - attribute \src "libresoc.v:180230.3-180259.6" - wire $2\wr_detect$7[0:0]$11494 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $2\r25__data_o$next[3:0]$11601 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $2\r5__data_o$next[3:0]$11663 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $2\reg$next[3:0]$11615 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $2\src15__data_o$next[3:0]$11621 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $2\src25__data_o$next[3:0]$11635 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $2\src35__data_o$next[3:0]$11649 + attribute \src "libresoc.v:182436.3-182465.6" + wire $2\wr_detect$10[0:0]$11657 + attribute \src "libresoc.v:182506.3-182535.6" + wire $2\wr_detect$13[0:0]$11671 + attribute \src "libresoc.v:182199.3-182228.6" + wire $2\wr_detect$16[0:0]$11609 + attribute \src "libresoc.v:182296.3-182325.6" + wire $2\wr_detect$4[0:0]$11629 + attribute \src "libresoc.v:182366.3-182395.6" + wire $2\wr_detect$7[0:0]$11643 + attribute \src "libresoc.v:182129.3-182158.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $3\r25__data_o$next[3:0]$11515 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $3\r5__data_o$next[3:0]$11501 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $3\reg$next[3:0]$11467 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $3\src15__data_o$next[3:0]$11458 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $3\src25__data_o$next[3:0]$11473 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $3\src35__data_o$next[3:0]$11487 - attribute \src "libresoc.v:180300.3-180329.6" - wire $3\wr_detect$10[0:0]$11509 - attribute \src "libresoc.v:180370.3-180399.6" - wire $3\wr_detect$13[0:0]$11523 - attribute \src "libresoc.v:180160.3-180189.6" - wire $3\wr_detect$4[0:0]$11481 - attribute \src "libresoc.v:180230.3-180259.6" - wire $3\wr_detect$7[0:0]$11495 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $3\r25__data_o$next[3:0]$11602 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $3\r5__data_o$next[3:0]$11664 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $3\reg$next[3:0]$11616 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $3\src15__data_o$next[3:0]$11622 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $3\src25__data_o$next[3:0]$11636 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $3\src35__data_o$next[3:0]$11650 + attribute \src "libresoc.v:182436.3-182465.6" + wire $3\wr_detect$10[0:0]$11658 + attribute \src "libresoc.v:182506.3-182535.6" + wire $3\wr_detect$13[0:0]$11672 + attribute \src "libresoc.v:182199.3-182228.6" + wire $3\wr_detect$16[0:0]$11610 + attribute \src "libresoc.v:182296.3-182325.6" + wire $3\wr_detect$4[0:0]$11630 + attribute \src "libresoc.v:182366.3-182395.6" + wire $3\wr_detect$7[0:0]$11644 + attribute \src "libresoc.v:182129.3-182158.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $4\r25__data_o$next[3:0]$11516 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $4\r5__data_o$next[3:0]$11502 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $4\reg$next[3:0]$11468 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $4\src15__data_o$next[3:0]$11459 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $4\src25__data_o$next[3:0]$11474 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $4\src35__data_o$next[3:0]$11488 - attribute \src "libresoc.v:180300.3-180329.6" - wire $4\wr_detect$10[0:0]$11510 - attribute \src "libresoc.v:180370.3-180399.6" - wire $4\wr_detect$13[0:0]$11524 - attribute \src "libresoc.v:180160.3-180189.6" - wire $4\wr_detect$4[0:0]$11482 - attribute \src "libresoc.v:180230.3-180259.6" - wire $4\wr_detect$7[0:0]$11496 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $4\cr_pred5__data_o$next[3:0]$11594 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $4\r25__data_o$next[3:0]$11603 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $4\r5__data_o$next[3:0]$11665 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $4\src15__data_o$next[3:0]$11623 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $4\src25__data_o$next[3:0]$11637 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $4\src35__data_o$next[3:0]$11651 + attribute \src "libresoc.v:182436.3-182465.6" + wire $4\wr_detect$10[0:0]$11659 + attribute \src "libresoc.v:182506.3-182535.6" + wire $4\wr_detect$13[0:0]$11673 + attribute \src "libresoc.v:182199.3-182228.6" + wire $4\wr_detect$16[0:0]$11611 + attribute \src "libresoc.v:182296.3-182325.6" + wire $4\wr_detect$4[0:0]$11631 + attribute \src "libresoc.v:182366.3-182395.6" + wire $4\wr_detect$7[0:0]$11645 + attribute \src "libresoc.v:182129.3-182158.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $5\r25__data_o$next[3:0]$11517 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $5\r5__data_o$next[3:0]$11503 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $5\src15__data_o$next[3:0]$11460 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $5\src25__data_o$next[3:0]$11475 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $5\src35__data_o$next[3:0]$11489 - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $6\r25__data_o$next[3:0]$11518 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $6\r5__data_o$next[3:0]$11504 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $6\src15__data_o$next[3:0]$11461 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $6\src25__data_o$next[3:0]$11476 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $6\src35__data_o$next[3:0]$11490 - attribute \src "libresoc.v:180006.17-180006.104" - wire $not$libresoc.v:180006$11443_Y - attribute \src "libresoc.v:180007.18-180007.105" - wire $not$libresoc.v:180007$11444_Y - attribute \src "libresoc.v:180008.17-180008.100" - wire $not$libresoc.v:180008$11445_Y - attribute \src "libresoc.v:180009.17-180009.103" - wire $not$libresoc.v:180009$11446_Y - attribute \src "libresoc.v:180010.17-180010.103" - wire $not$libresoc.v:180010$11447_Y + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $5\cr_pred5__data_o$next[3:0]$11595 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $5\r25__data_o$next[3:0]$11604 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $5\r5__data_o$next[3:0]$11666 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $5\src15__data_o$next[3:0]$11624 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $5\src25__data_o$next[3:0]$11638 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $5\src35__data_o$next[3:0]$11652 + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182069.17-182069.104" + wire $not$libresoc.v:182069$11576_Y + attribute \src "libresoc.v:182070.18-182070.105" + wire $not$libresoc.v:182070$11577_Y + attribute \src "libresoc.v:182071.18-182071.105" + wire $not$libresoc.v:182071$11578_Y + attribute \src "libresoc.v:182072.17-182072.100" + wire $not$libresoc.v:182072$11579_Y + attribute \src "libresoc.v:182073.17-182073.103" + wire $not$libresoc.v:182073$11580_Y + attribute \src "libresoc.v:182074.17-182074.103" + wire $not$libresoc.v:182074$11581_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest15__data_i + wire width 4 output 3 \cr_pred5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred5__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest15__wen + wire width 4 input 11 \dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest25__data_i + wire input 10 \dest15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest25__wen - attribute \src "libresoc.v:179930.7-179930.15" + wire width 4 input 13 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest25__wen + attribute \src "libresoc.v:181982.7-181982.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r25__data_o + wire width 4 output 16 \r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r25__ren + wire input 17 \r25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r5__data_o + wire width 4 output 14 \r5__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r5__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r5__ren + wire input 15 \r5__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src15__data_o + wire width 4 output 5 \src15__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src15__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src15__ren + wire input 4 \src15__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src25__data_o + wire width 4 output 7 \src25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src25__ren + wire input 6 \src25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src35__data_o + wire width 4 output 9 \src35__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src35__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src35__ren + wire input 8 \src35__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w5__data_i + wire width 4 input 18 \w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w5__wen + wire input 19 \w5__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -371181,232 +374661,257 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180006$11443 + cell $not $not$libresoc.v:182069$11576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180006$11443_Y + connect \Y $not$libresoc.v:182069$11576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180007$11444 + cell $not $not$libresoc.v:182070$11577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180007$11444_Y + connect \Y $not$libresoc.v:182070$11577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182071$11578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182071$11578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180008$11445 + cell $not $not$libresoc.v:182072$11579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180008$11445_Y + connect \Y $not$libresoc.v:182072$11579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180009$11446 + cell $not $not$libresoc.v:182073$11580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180009$11446_Y + connect \Y $not$libresoc.v:182073$11580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180010$11447 + cell $not $not$libresoc.v:182074$11581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180010$11447_Y + connect \Y $not$libresoc.v:182074$11581_Y end - attribute \src "libresoc.v:179930.7-179930.20" - process $proc$libresoc.v:179930$11525 + attribute \src "libresoc.v:181982.7-181982.20" + process $proc$libresoc.v:181982$11674 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179955.13-179955.31" - process $proc$libresoc.v:179955$11526 + attribute \src "libresoc.v:182001.13-182001.36" + process $proc$libresoc.v:182001$11675 + assign { } { } + assign $1\cr_pred5__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182016.13-182016.31" + process $proc$libresoc.v:182016$11676 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:179962.13-179962.30" - process $proc$libresoc.v:179962$11527 + attribute \src "libresoc.v:182023.13-182023.30" + process $proc$libresoc.v:182023$11677 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:179968.13-179968.25" - process $proc$libresoc.v:179968$11528 + attribute \src "libresoc.v:182029.13-182029.25" + process $proc$libresoc.v:182029$11678 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179973.13-179973.33" - process $proc$libresoc.v:179973$11529 + attribute \src "libresoc.v:182034.13-182034.33" + process $proc$libresoc.v:182034$11679 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:179980.13-179980.33" - process $proc$libresoc.v:179980$11530 + attribute \src "libresoc.v:182041.13-182041.33" + process $proc$libresoc.v:182041$11680 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:179987.13-179987.33" - process $proc$libresoc.v:179987$11531 + attribute \src "libresoc.v:182048.13-182048.33" + process $proc$libresoc.v:182048$11681 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:180011.3-180012.25" - process $proc$libresoc.v:180011$11448 + attribute \src "libresoc.v:182075.3-182076.25" + process $proc$libresoc.v:182075$11582 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180013.3-180014.39" - process $proc$libresoc.v:180013$11449 + attribute \src "libresoc.v:182077.3-182078.39" + process $proc$libresoc.v:182077$11583 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:180015.3-180016.37" - process $proc$libresoc.v:180015$11450 + attribute \src "libresoc.v:182079.3-182080.37" + process $proc$libresoc.v:182079$11584 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:180017.3-180018.43" - process $proc$libresoc.v:180017$11451 + attribute \src "libresoc.v:182081.3-182082.43" + process $proc$libresoc.v:182081$11585 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:180019.3-180020.43" - process $proc$libresoc.v:180019$11452 + attribute \src "libresoc.v:182083.3-182084.43" + process $proc$libresoc.v:182083$11586 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:180021.3-180022.43" - process $proc$libresoc.v:180021$11453 + attribute \src "libresoc.v:182085.3-182086.43" + process $proc$libresoc.v:182085$11587 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:180023.3-180062.6" - process $proc$libresoc.v:180023$11454 + attribute \src "libresoc.v:182087.3-182088.49" + process $proc$libresoc.v:182087$11588 assign { } { } + assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next + sync posedge \coresync_clk + update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182089.3-182128.6" + process $proc$libresoc.v:182089$11589 assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11455 $6\src15__data_o$next[3:0]$11461 - attribute \src "libresoc.v:180024.5-180024.29" + assign { } { } + assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182090.5-182090.29" switch \initial - attribute \src "libresoc.v:180024.9-180024.17" + attribute \src "libresoc.v:182090.9-182090.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \cr_pred5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11456 $5\src15__data_o$next[3:0]$11460 + assign $1\cr_pred5__data_o$next[3:0]$11591 $5\cr_pred5__data_o$next[3:0]$11595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11457 \dest15__data_i + assign $2\cr_pred5__data_o$next[3:0]$11592 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11457 4'0000 + assign $2\cr_pred5__data_o$next[3:0]$11592 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11458 \dest25__data_i + assign $3\cr_pred5__data_o$next[3:0]$11593 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11458 $2\src15__data_o$next[3:0]$11457 + assign $3\cr_pred5__data_o$next[3:0]$11593 $2\cr_pred5__data_o$next[3:0]$11592 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11459 \w5__data_i + assign $4\cr_pred5__data_o$next[3:0]$11594 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11459 $3\src15__data_o$next[3:0]$11458 + assign $4\cr_pred5__data_o$next[3:0]$11594 $3\cr_pred5__data_o$next[3:0]$11593 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11460 \reg + assign $5\cr_pred5__data_o$next[3:0]$11595 \reg case - assign $5\src15__data_o$next[3:0]$11460 $4\src15__data_o$next[3:0]$11459 + assign $5\cr_pred5__data_o$next[3:0]$11595 $4\cr_pred5__data_o$next[3:0]$11594 end case - assign $1\src15__data_o$next[3:0]$11456 4'0000 + assign $1\cr_pred5__data_o$next[3:0]$11591 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11461 4'0000 + assign $6\cr_pred5__data_o$next[3:0]$11596 4'0000 case - assign $6\src15__data_o$next[3:0]$11461 $1\src15__data_o$next[3:0]$11456 + assign $6\cr_pred5__data_o$next[3:0]$11596 $1\cr_pred5__data_o$next[3:0]$11591 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11455 + update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 end - attribute \src "libresoc.v:180063.3-180092.6" - process $proc$libresoc.v:180063$11462 + attribute \src "libresoc.v:182129.3-182158.6" + process $proc$libresoc.v:182129$11597 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180064.5-180064.29" + attribute \src "libresoc.v:182130.5-182130.29" switch \initial - attribute \src "libresoc.v:180064.9-180064.17" + attribute \src "libresoc.v:182130.9-182130.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \cr_pred5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -371447,17 +374952,142 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180093.3-180119.6" - process $proc$libresoc.v:180093$11463 + attribute \src "libresoc.v:182159.3-182198.6" + process $proc$libresoc.v:182159$11598 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182160.5-182160.29" + switch \initial + attribute \src "libresoc.v:182160.9-182160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11600 $5\r25__data_o$next[3:0]$11604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11601 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11601 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11602 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11602 $2\r25__data_o$next[3:0]$11601 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11603 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11603 $3\r25__data_o$next[3:0]$11602 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11604 \reg + case + assign $5\r25__data_o$next[3:0]$11604 $4\r25__data_o$next[3:0]$11603 + end + case + assign $1\r25__data_o$next[3:0]$11600 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11605 4'0000 + case + assign $6\r25__data_o$next[3:0]$11605 $1\r25__data_o$next[3:0]$11600 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 + end + attribute \src "libresoc.v:182199.3-182228.6" + process $proc$libresoc.v:182199$11606 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182200.5-182200.29" + switch \initial + attribute \src "libresoc.v:182200.9-182200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11608 $4\wr_detect$16[0:0]$11611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11609 1'1 + case + assign $2\wr_detect$16[0:0]$11609 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11610 1'1 + case + assign $3\wr_detect$16[0:0]$11610 $2\wr_detect$16[0:0]$11609 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11611 1'1 + case + assign $4\wr_detect$16[0:0]$11611 $3\wr_detect$16[0:0]$11610 + end + case + assign $1\wr_detect$16[0:0]$11608 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11607 + end + attribute \src "libresoc.v:182229.3-182255.6" + process $proc$libresoc.v:182229$11612 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11464 $4\reg$next[3:0]$11468 - attribute \src "libresoc.v:180094.5-180094.29" + assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182230.5-182230.29" switch \initial - attribute \src "libresoc.v:180094.9-180094.17" + attribute \src "libresoc.v:182230.9-182230.17" case 1'1 case end @@ -371466,779 +375096,818 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11465 \dest15__data_i + assign $1\reg$next[3:0]$11614 \dest15__data_i case - assign $1\reg$next[3:0]$11465 \reg + assign $1\reg$next[3:0]$11614 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11466 \dest25__data_i + assign $2\reg$next[3:0]$11615 \dest25__data_i case - assign $2\reg$next[3:0]$11466 $1\reg$next[3:0]$11465 + assign $2\reg$next[3:0]$11615 $1\reg$next[3:0]$11614 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11467 \w5__data_i + assign $3\reg$next[3:0]$11616 \w5__data_i case - assign $3\reg$next[3:0]$11467 $2\reg$next[3:0]$11466 + assign $3\reg$next[3:0]$11616 $2\reg$next[3:0]$11615 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11468 4'0000 + assign $4\reg$next[3:0]$11617 4'0000 case - assign $4\reg$next[3:0]$11468 $3\reg$next[3:0]$11467 + assign $4\reg$next[3:0]$11617 $3\reg$next[3:0]$11616 end sync always - update \reg$next $0\reg$next[3:0]$11464 + update \reg$next $0\reg$next[3:0]$11613 end - attribute \src "libresoc.v:180120.3-180159.6" - process $proc$libresoc.v:180120$11469 + attribute \src "libresoc.v:182256.3-182295.6" + process $proc$libresoc.v:182256$11618 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11470 $6\src25__data_o$next[3:0]$11476 - attribute \src "libresoc.v:180121.5-180121.29" + assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182257.5-182257.29" switch \initial - attribute \src "libresoc.v:180121.9-180121.17" + attribute \src "libresoc.v:182257.9-182257.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11471 $5\src25__data_o$next[3:0]$11475 + assign $1\src15__data_o$next[3:0]$11620 $5\src15__data_o$next[3:0]$11624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11472 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11621 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11472 4'0000 + assign $2\src15__data_o$next[3:0]$11621 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11473 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11622 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11473 $2\src25__data_o$next[3:0]$11472 + assign $3\src15__data_o$next[3:0]$11622 $2\src15__data_o$next[3:0]$11621 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11474 \w5__data_i + assign $4\src15__data_o$next[3:0]$11623 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11474 $3\src25__data_o$next[3:0]$11473 + assign $4\src15__data_o$next[3:0]$11623 $3\src15__data_o$next[3:0]$11622 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11475 \reg + assign $5\src15__data_o$next[3:0]$11624 \reg case - assign $5\src25__data_o$next[3:0]$11475 $4\src25__data_o$next[3:0]$11474 + assign $5\src15__data_o$next[3:0]$11624 $4\src15__data_o$next[3:0]$11623 end case - assign $1\src25__data_o$next[3:0]$11471 4'0000 + assign $1\src15__data_o$next[3:0]$11620 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11476 4'0000 + assign $6\src15__data_o$next[3:0]$11625 4'0000 case - assign $6\src25__data_o$next[3:0]$11476 $1\src25__data_o$next[3:0]$11471 + assign $6\src15__data_o$next[3:0]$11625 $1\src15__data_o$next[3:0]$11620 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11470 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 end - attribute \src "libresoc.v:180160.3-180189.6" - process $proc$libresoc.v:180160$11477 + attribute \src "libresoc.v:182296.3-182325.6" + process $proc$libresoc.v:182296$11626 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11478 $1\wr_detect$4[0:0]$11479 - attribute \src "libresoc.v:180161.5-180161.29" + assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182297.5-182297.29" switch \initial - attribute \src "libresoc.v:180161.9-180161.17" + attribute \src "libresoc.v:182297.9-182297.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11479 $4\wr_detect$4[0:0]$11482 + assign $1\wr_detect$4[0:0]$11628 $4\wr_detect$4[0:0]$11631 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11480 1'1 + assign $2\wr_detect$4[0:0]$11629 1'1 case - assign $2\wr_detect$4[0:0]$11480 1'0 + assign $2\wr_detect$4[0:0]$11629 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11481 1'1 + assign $3\wr_detect$4[0:0]$11630 1'1 case - assign $3\wr_detect$4[0:0]$11481 $2\wr_detect$4[0:0]$11480 + assign $3\wr_detect$4[0:0]$11630 $2\wr_detect$4[0:0]$11629 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11482 1'1 + assign $4\wr_detect$4[0:0]$11631 1'1 case - assign $4\wr_detect$4[0:0]$11482 $3\wr_detect$4[0:0]$11481 + assign $4\wr_detect$4[0:0]$11631 $3\wr_detect$4[0:0]$11630 end case - assign $1\wr_detect$4[0:0]$11479 1'0 + assign $1\wr_detect$4[0:0]$11628 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11478 + update \wr_detect$4 $0\wr_detect$4[0:0]$11627 end - attribute \src "libresoc.v:180190.3-180229.6" - process $proc$libresoc.v:180190$11483 + attribute \src "libresoc.v:182326.3-182365.6" + process $proc$libresoc.v:182326$11632 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11484 $6\src35__data_o$next[3:0]$11490 - attribute \src "libresoc.v:180191.5-180191.29" + assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182327.5-182327.29" switch \initial - attribute \src "libresoc.v:180191.9-180191.17" + attribute \src "libresoc.v:182327.9-182327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11485 $5\src35__data_o$next[3:0]$11489 + assign $1\src25__data_o$next[3:0]$11634 $5\src25__data_o$next[3:0]$11638 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11486 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11635 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11486 4'0000 + assign $2\src25__data_o$next[3:0]$11635 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11487 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11636 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11487 $2\src35__data_o$next[3:0]$11486 + assign $3\src25__data_o$next[3:0]$11636 $2\src25__data_o$next[3:0]$11635 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11488 \w5__data_i + assign $4\src25__data_o$next[3:0]$11637 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11488 $3\src35__data_o$next[3:0]$11487 + assign $4\src25__data_o$next[3:0]$11637 $3\src25__data_o$next[3:0]$11636 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11489 \reg + assign $5\src25__data_o$next[3:0]$11638 \reg case - assign $5\src35__data_o$next[3:0]$11489 $4\src35__data_o$next[3:0]$11488 + assign $5\src25__data_o$next[3:0]$11638 $4\src25__data_o$next[3:0]$11637 end case - assign $1\src35__data_o$next[3:0]$11485 4'0000 + assign $1\src25__data_o$next[3:0]$11634 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11490 4'0000 + assign $6\src25__data_o$next[3:0]$11639 4'0000 case - assign $6\src35__data_o$next[3:0]$11490 $1\src35__data_o$next[3:0]$11485 + assign $6\src25__data_o$next[3:0]$11639 $1\src25__data_o$next[3:0]$11634 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11484 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 end - attribute \src "libresoc.v:180230.3-180259.6" - process $proc$libresoc.v:180230$11491 + attribute \src "libresoc.v:182366.3-182395.6" + process $proc$libresoc.v:182366$11640 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11492 $1\wr_detect$7[0:0]$11493 - attribute \src "libresoc.v:180231.5-180231.29" + assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182367.5-182367.29" switch \initial - attribute \src "libresoc.v:180231.9-180231.17" + attribute \src "libresoc.v:182367.9-182367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11493 $4\wr_detect$7[0:0]$11496 + assign $1\wr_detect$7[0:0]$11642 $4\wr_detect$7[0:0]$11645 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11494 1'1 + assign $2\wr_detect$7[0:0]$11643 1'1 case - assign $2\wr_detect$7[0:0]$11494 1'0 + assign $2\wr_detect$7[0:0]$11643 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11495 1'1 + assign $3\wr_detect$7[0:0]$11644 1'1 case - assign $3\wr_detect$7[0:0]$11495 $2\wr_detect$7[0:0]$11494 + assign $3\wr_detect$7[0:0]$11644 $2\wr_detect$7[0:0]$11643 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11496 1'1 + assign $4\wr_detect$7[0:0]$11645 1'1 case - assign $4\wr_detect$7[0:0]$11496 $3\wr_detect$7[0:0]$11495 + assign $4\wr_detect$7[0:0]$11645 $3\wr_detect$7[0:0]$11644 end case - assign $1\wr_detect$7[0:0]$11493 1'0 + assign $1\wr_detect$7[0:0]$11642 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11492 + update \wr_detect$7 $0\wr_detect$7[0:0]$11641 end - attribute \src "libresoc.v:180260.3-180299.6" - process $proc$libresoc.v:180260$11497 + attribute \src "libresoc.v:182396.3-182435.6" + process $proc$libresoc.v:182396$11646 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11498 $6\r5__data_o$next[3:0]$11504 - attribute \src "libresoc.v:180261.5-180261.29" + assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182397.5-182397.29" switch \initial - attribute \src "libresoc.v:180261.9-180261.17" + attribute \src "libresoc.v:182397.9-182397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11499 $5\r5__data_o$next[3:0]$11503 + assign $1\src35__data_o$next[3:0]$11648 $5\src35__data_o$next[3:0]$11652 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11500 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11649 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11500 4'0000 + assign $2\src35__data_o$next[3:0]$11649 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11501 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11650 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11501 $2\r5__data_o$next[3:0]$11500 + assign $3\src35__data_o$next[3:0]$11650 $2\src35__data_o$next[3:0]$11649 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11502 \w5__data_i + assign $4\src35__data_o$next[3:0]$11651 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11502 $3\r5__data_o$next[3:0]$11501 + assign $4\src35__data_o$next[3:0]$11651 $3\src35__data_o$next[3:0]$11650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11503 \reg + assign $5\src35__data_o$next[3:0]$11652 \reg case - assign $5\r5__data_o$next[3:0]$11503 $4\r5__data_o$next[3:0]$11502 + assign $5\src35__data_o$next[3:0]$11652 $4\src35__data_o$next[3:0]$11651 end case - assign $1\r5__data_o$next[3:0]$11499 4'0000 + assign $1\src35__data_o$next[3:0]$11648 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11504 4'0000 + assign $6\src35__data_o$next[3:0]$11653 4'0000 case - assign $6\r5__data_o$next[3:0]$11504 $1\r5__data_o$next[3:0]$11499 + assign $6\src35__data_o$next[3:0]$11653 $1\src35__data_o$next[3:0]$11648 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11498 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 end - attribute \src "libresoc.v:180300.3-180329.6" - process $proc$libresoc.v:180300$11505 + attribute \src "libresoc.v:182436.3-182465.6" + process $proc$libresoc.v:182436$11654 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11506 $1\wr_detect$10[0:0]$11507 - attribute \src "libresoc.v:180301.5-180301.29" + assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182437.5-182437.29" switch \initial - attribute \src "libresoc.v:180301.9-180301.17" + attribute \src "libresoc.v:182437.9-182437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11507 $4\wr_detect$10[0:0]$11510 + assign $1\wr_detect$10[0:0]$11656 $4\wr_detect$10[0:0]$11659 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11508 1'1 + assign $2\wr_detect$10[0:0]$11657 1'1 case - assign $2\wr_detect$10[0:0]$11508 1'0 + assign $2\wr_detect$10[0:0]$11657 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11509 1'1 + assign $3\wr_detect$10[0:0]$11658 1'1 case - assign $3\wr_detect$10[0:0]$11509 $2\wr_detect$10[0:0]$11508 + assign $3\wr_detect$10[0:0]$11658 $2\wr_detect$10[0:0]$11657 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11510 1'1 + assign $4\wr_detect$10[0:0]$11659 1'1 case - assign $4\wr_detect$10[0:0]$11510 $3\wr_detect$10[0:0]$11509 + assign $4\wr_detect$10[0:0]$11659 $3\wr_detect$10[0:0]$11658 end case - assign $1\wr_detect$10[0:0]$11507 1'0 + assign $1\wr_detect$10[0:0]$11656 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11506 + update \wr_detect$10 $0\wr_detect$10[0:0]$11655 end - attribute \src "libresoc.v:180330.3-180369.6" - process $proc$libresoc.v:180330$11511 + attribute \src "libresoc.v:182466.3-182505.6" + process $proc$libresoc.v:182466$11660 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11512 $6\r25__data_o$next[3:0]$11518 - attribute \src "libresoc.v:180331.5-180331.29" + assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182467.5-182467.29" switch \initial - attribute \src "libresoc.v:180331.9-180331.17" + attribute \src "libresoc.v:182467.9-182467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11513 $5\r25__data_o$next[3:0]$11517 + assign $1\r5__data_o$next[3:0]$11662 $5\r5__data_o$next[3:0]$11666 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11514 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11663 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11514 4'0000 + assign $2\r5__data_o$next[3:0]$11663 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11515 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11664 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11515 $2\r25__data_o$next[3:0]$11514 + assign $3\r5__data_o$next[3:0]$11664 $2\r5__data_o$next[3:0]$11663 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11516 \w5__data_i + assign $4\r5__data_o$next[3:0]$11665 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11516 $3\r25__data_o$next[3:0]$11515 + assign $4\r5__data_o$next[3:0]$11665 $3\r5__data_o$next[3:0]$11664 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11517 \reg + assign $5\r5__data_o$next[3:0]$11666 \reg case - assign $5\r25__data_o$next[3:0]$11517 $4\r25__data_o$next[3:0]$11516 + assign $5\r5__data_o$next[3:0]$11666 $4\r5__data_o$next[3:0]$11665 end case - assign $1\r25__data_o$next[3:0]$11513 4'0000 + assign $1\r5__data_o$next[3:0]$11662 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11518 4'0000 + assign $6\r5__data_o$next[3:0]$11667 4'0000 case - assign $6\r25__data_o$next[3:0]$11518 $1\r25__data_o$next[3:0]$11513 + assign $6\r5__data_o$next[3:0]$11667 $1\r5__data_o$next[3:0]$11662 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11512 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 end - attribute \src "libresoc.v:180370.3-180399.6" - process $proc$libresoc.v:180370$11519 + attribute \src "libresoc.v:182506.3-182535.6" + process $proc$libresoc.v:182506$11668 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11520 $1\wr_detect$13[0:0]$11521 - attribute \src "libresoc.v:180371.5-180371.29" + assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182507.5-182507.29" switch \initial - attribute \src "libresoc.v:180371.9-180371.17" + attribute \src "libresoc.v:182507.9-182507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11521 $4\wr_detect$13[0:0]$11524 + assign $1\wr_detect$13[0:0]$11670 $4\wr_detect$13[0:0]$11673 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11522 1'1 + assign $2\wr_detect$13[0:0]$11671 1'1 case - assign $2\wr_detect$13[0:0]$11522 1'0 + assign $2\wr_detect$13[0:0]$11671 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11523 1'1 + assign $3\wr_detect$13[0:0]$11672 1'1 case - assign $3\wr_detect$13[0:0]$11523 $2\wr_detect$13[0:0]$11522 + assign $3\wr_detect$13[0:0]$11672 $2\wr_detect$13[0:0]$11671 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11524 1'1 + assign $4\wr_detect$13[0:0]$11673 1'1 case - assign $4\wr_detect$13[0:0]$11524 $3\wr_detect$13[0:0]$11523 + assign $4\wr_detect$13[0:0]$11673 $3\wr_detect$13[0:0]$11672 end case - assign $1\wr_detect$13[0:0]$11521 1'0 + assign $1\wr_detect$13[0:0]$11670 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11520 + update \wr_detect$13 $0\wr_detect$13[0:0]$11669 end - connect \$9 $not$libresoc.v:180006$11443_Y - connect \$12 $not$libresoc.v:180007$11444_Y - connect \$1 $not$libresoc.v:180008$11445_Y - connect \$3 $not$libresoc.v:180009$11446_Y - connect \$6 $not$libresoc.v:180010$11447_Y + connect \$9 $not$libresoc.v:182069$11576_Y + connect \$12 $not$libresoc.v:182070$11577_Y + connect \$15 $not$libresoc.v:182071$11578_Y + connect \$1 $not$libresoc.v:182072$11579_Y + connect \$3 $not$libresoc.v:182073$11580_Y + connect \$6 $not$libresoc.v:182074$11581_Y end -attribute \src "libresoc.v:180404.1-180875.10" +attribute \src "libresoc.v:182540.1-183095.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:180405.7-180405.20" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 + attribute \src "libresoc.v:182646.3-182647.49" + wire width 4 $0\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182541.7-182541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $0\r26__data_o$next[3:0]$11601 - attribute \src "libresoc.v:180488.3-180489.39" + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $0\r26__data_o$next[3:0]$11705 + attribute \src "libresoc.v:182636.3-182637.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $0\r6__data_o$next[3:0]$11587 - attribute \src "libresoc.v:180490.3-180491.37" + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $0\r6__data_o$next[3:0]$11767 + attribute \src "libresoc.v:182638.3-182639.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $0\reg$next[3:0]$11553 - attribute \src "libresoc.v:180486.3-180487.25" + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $0\reg$next[3:0]$11719 + attribute \src "libresoc.v:182634.3-182635.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $0\src16__data_o$next[3:0]$11544 - attribute \src "libresoc.v:180496.3-180497.43" + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $0\src16__data_o$next[3:0]$11725 + attribute \src "libresoc.v:182644.3-182645.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $0\src26__data_o$next[3:0]$11559 - attribute \src "libresoc.v:180494.3-180495.43" + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $0\src26__data_o$next[3:0]$11739 + attribute \src "libresoc.v:182642.3-182643.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $0\src36__data_o$next[3:0]$11573 - attribute \src "libresoc.v:180492.3-180493.43" + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $0\src36__data_o$next[3:0]$11753 + attribute \src "libresoc.v:182640.3-182641.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:180775.3-180804.6" - wire $0\wr_detect$10[0:0]$11595 - attribute \src "libresoc.v:180845.3-180874.6" - wire $0\wr_detect$13[0:0]$11609 - attribute \src "libresoc.v:180635.3-180664.6" - wire $0\wr_detect$4[0:0]$11567 - attribute \src "libresoc.v:180705.3-180734.6" - wire $0\wr_detect$7[0:0]$11581 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182995.3-183024.6" + wire $0\wr_detect$10[0:0]$11761 + attribute \src "libresoc.v:183065.3-183094.6" + wire $0\wr_detect$13[0:0]$11775 + attribute \src "libresoc.v:182758.3-182787.6" + wire $0\wr_detect$16[0:0]$11713 + attribute \src "libresoc.v:182855.3-182884.6" + wire $0\wr_detect$4[0:0]$11733 + attribute \src "libresoc.v:182925.3-182954.6" + wire $0\wr_detect$7[0:0]$11747 + attribute \src "libresoc.v:182688.3-182717.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $1\r26__data_o$next[3:0]$11602 - attribute \src "libresoc.v:180430.13-180430.31" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 + attribute \src "libresoc.v:182560.13-182560.36" + wire width 4 $1\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $1\r26__data_o$next[3:0]$11706 + attribute \src "libresoc.v:182575.13-182575.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $1\r6__data_o$next[3:0]$11588 - attribute \src "libresoc.v:180437.13-180437.30" + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $1\r6__data_o$next[3:0]$11768 + attribute \src "libresoc.v:182582.13-182582.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $1\reg$next[3:0]$11554 - attribute \src "libresoc.v:180443.13-180443.25" + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $1\reg$next[3:0]$11720 + attribute \src "libresoc.v:182588.13-182588.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $1\src16__data_o$next[3:0]$11545 - attribute \src "libresoc.v:180448.13-180448.33" + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $1\src16__data_o$next[3:0]$11726 + attribute \src "libresoc.v:182593.13-182593.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $1\src26__data_o$next[3:0]$11560 - attribute \src "libresoc.v:180455.13-180455.33" + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $1\src26__data_o$next[3:0]$11740 + attribute \src "libresoc.v:182600.13-182600.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $1\src36__data_o$next[3:0]$11574 - attribute \src "libresoc.v:180462.13-180462.33" + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $1\src36__data_o$next[3:0]$11754 + attribute \src "libresoc.v:182607.13-182607.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:180775.3-180804.6" - wire $1\wr_detect$10[0:0]$11596 - attribute \src "libresoc.v:180845.3-180874.6" - wire $1\wr_detect$13[0:0]$11610 - attribute \src "libresoc.v:180635.3-180664.6" - wire $1\wr_detect$4[0:0]$11568 - attribute \src "libresoc.v:180705.3-180734.6" - wire $1\wr_detect$7[0:0]$11582 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182995.3-183024.6" + wire $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:183065.3-183094.6" + wire $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:182758.3-182787.6" + wire $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182855.3-182884.6" + wire $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182925.3-182954.6" + wire $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182688.3-182717.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $2\r26__data_o$next[3:0]$11603 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $2\r6__data_o$next[3:0]$11589 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $2\reg$next[3:0]$11555 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $2\src16__data_o$next[3:0]$11546 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $2\src26__data_o$next[3:0]$11561 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $2\src36__data_o$next[3:0]$11575 - attribute \src "libresoc.v:180775.3-180804.6" - wire $2\wr_detect$10[0:0]$11597 - attribute \src "libresoc.v:180845.3-180874.6" - wire $2\wr_detect$13[0:0]$11611 - attribute \src "libresoc.v:180635.3-180664.6" - wire $2\wr_detect$4[0:0]$11569 - attribute \src "libresoc.v:180705.3-180734.6" - wire $2\wr_detect$7[0:0]$11583 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $2\r26__data_o$next[3:0]$11707 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $2\r6__data_o$next[3:0]$11769 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $2\reg$next[3:0]$11721 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $2\src16__data_o$next[3:0]$11727 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $2\src26__data_o$next[3:0]$11741 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $2\src36__data_o$next[3:0]$11755 + attribute \src "libresoc.v:182995.3-183024.6" + wire $2\wr_detect$10[0:0]$11763 + attribute \src "libresoc.v:183065.3-183094.6" + wire $2\wr_detect$13[0:0]$11777 + attribute \src "libresoc.v:182758.3-182787.6" + wire $2\wr_detect$16[0:0]$11715 + attribute \src "libresoc.v:182855.3-182884.6" + wire $2\wr_detect$4[0:0]$11735 + attribute \src "libresoc.v:182925.3-182954.6" + wire $2\wr_detect$7[0:0]$11749 + attribute \src "libresoc.v:182688.3-182717.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $3\r26__data_o$next[3:0]$11604 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $3\r6__data_o$next[3:0]$11590 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $3\reg$next[3:0]$11556 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $3\src16__data_o$next[3:0]$11547 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $3\src26__data_o$next[3:0]$11562 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $3\src36__data_o$next[3:0]$11576 - attribute \src "libresoc.v:180775.3-180804.6" - wire $3\wr_detect$10[0:0]$11598 - attribute \src "libresoc.v:180845.3-180874.6" - wire $3\wr_detect$13[0:0]$11612 - attribute \src "libresoc.v:180635.3-180664.6" - wire $3\wr_detect$4[0:0]$11570 - attribute \src "libresoc.v:180705.3-180734.6" - wire $3\wr_detect$7[0:0]$11584 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $3\r26__data_o$next[3:0]$11708 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $3\r6__data_o$next[3:0]$11770 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $3\reg$next[3:0]$11722 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $3\src16__data_o$next[3:0]$11728 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $3\src26__data_o$next[3:0]$11742 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $3\src36__data_o$next[3:0]$11756 + attribute \src "libresoc.v:182995.3-183024.6" + wire $3\wr_detect$10[0:0]$11764 + attribute \src "libresoc.v:183065.3-183094.6" + wire $3\wr_detect$13[0:0]$11778 + attribute \src "libresoc.v:182758.3-182787.6" + wire $3\wr_detect$16[0:0]$11716 + attribute \src "libresoc.v:182855.3-182884.6" + wire $3\wr_detect$4[0:0]$11736 + attribute \src "libresoc.v:182925.3-182954.6" + wire $3\wr_detect$7[0:0]$11750 + attribute \src "libresoc.v:182688.3-182717.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $4\r26__data_o$next[3:0]$11605 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $4\r6__data_o$next[3:0]$11591 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $4\reg$next[3:0]$11557 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $4\src16__data_o$next[3:0]$11548 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $4\src26__data_o$next[3:0]$11563 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $4\src36__data_o$next[3:0]$11577 - attribute \src "libresoc.v:180775.3-180804.6" - wire $4\wr_detect$10[0:0]$11599 - attribute \src "libresoc.v:180845.3-180874.6" - wire $4\wr_detect$13[0:0]$11613 - attribute \src "libresoc.v:180635.3-180664.6" - wire $4\wr_detect$4[0:0]$11571 - attribute \src "libresoc.v:180705.3-180734.6" - wire $4\wr_detect$7[0:0]$11585 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $4\r26__data_o$next[3:0]$11709 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $4\r6__data_o$next[3:0]$11771 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $4\src16__data_o$next[3:0]$11729 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $4\src26__data_o$next[3:0]$11743 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $4\src36__data_o$next[3:0]$11757 + attribute \src "libresoc.v:182995.3-183024.6" + wire $4\wr_detect$10[0:0]$11765 + attribute \src "libresoc.v:183065.3-183094.6" + wire $4\wr_detect$13[0:0]$11779 + attribute \src "libresoc.v:182758.3-182787.6" + wire $4\wr_detect$16[0:0]$11717 + attribute \src "libresoc.v:182855.3-182884.6" + wire $4\wr_detect$4[0:0]$11737 + attribute \src "libresoc.v:182925.3-182954.6" + wire $4\wr_detect$7[0:0]$11751 + attribute \src "libresoc.v:182688.3-182717.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $5\r26__data_o$next[3:0]$11606 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $5\r6__data_o$next[3:0]$11592 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $5\src16__data_o$next[3:0]$11549 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $5\src26__data_o$next[3:0]$11564 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $5\src36__data_o$next[3:0]$11578 - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $6\r26__data_o$next[3:0]$11607 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $6\r6__data_o$next[3:0]$11593 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $6\src16__data_o$next[3:0]$11550 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $6\src26__data_o$next[3:0]$11565 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $6\src36__data_o$next[3:0]$11579 - attribute \src "libresoc.v:180481.17-180481.104" - wire $not$libresoc.v:180481$11532_Y - attribute \src "libresoc.v:180482.18-180482.105" - wire $not$libresoc.v:180482$11533_Y - attribute \src "libresoc.v:180483.17-180483.100" - wire $not$libresoc.v:180483$11534_Y - attribute \src "libresoc.v:180484.17-180484.103" - wire $not$libresoc.v:180484$11535_Y - attribute \src "libresoc.v:180485.17-180485.103" - wire $not$libresoc.v:180485$11536_Y + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $5\r26__data_o$next[3:0]$11710 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $5\r6__data_o$next[3:0]$11772 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $5\src16__data_o$next[3:0]$11730 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $5\src26__data_o$next[3:0]$11744 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $5\src36__data_o$next[3:0]$11758 + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182628.17-182628.104" + wire $not$libresoc.v:182628$11682_Y + attribute \src "libresoc.v:182629.18-182629.105" + wire $not$libresoc.v:182629$11683_Y + attribute \src "libresoc.v:182630.18-182630.105" + wire $not$libresoc.v:182630$11684_Y + attribute \src "libresoc.v:182631.17-182631.100" + wire $not$libresoc.v:182631$11685_Y + attribute \src "libresoc.v:182632.17-182632.103" + wire $not$libresoc.v:182632$11686_Y + attribute \src "libresoc.v:182633.17-182633.103" + wire $not$libresoc.v:182633$11687_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest16__data_i + wire width 4 output 3 \cr_pred6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest16__wen + wire width 4 \cr_pred6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest26__data_i + wire input 2 \cr_pred6__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest26__wen - attribute \src "libresoc.v:180405.7-180405.15" + wire width 4 input 11 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest26__wen + attribute \src "libresoc.v:182541.7-182541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r26__data_o + wire width 4 output 16 \r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r26__ren + wire input 17 \r26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r6__data_o + wire width 4 output 14 \r6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r6__ren + wire input 15 \r6__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src16__data_o + wire width 4 output 5 \src16__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src16__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src16__ren + wire input 4 \src16__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src26__data_o + wire width 4 output 7 \src26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src26__ren + wire input 6 \src26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src36__data_o + wire width 4 output 9 \src36__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src36__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src36__ren + wire input 8 \src36__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w6__data_i + wire width 4 input 18 \w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w6__wen + wire input 19 \w6__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -372246,232 +375915,257 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180481$11532 + cell $not $not$libresoc.v:182628$11682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180481$11532_Y + connect \Y $not$libresoc.v:182628$11682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180482$11533 + cell $not $not$libresoc.v:182629$11683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180482$11533_Y + connect \Y $not$libresoc.v:182629$11683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180483$11534 + cell $not $not$libresoc.v:182630$11684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182630$11684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182631$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180483$11534_Y + connect \Y $not$libresoc.v:182631$11685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180484$11535 + cell $not $not$libresoc.v:182632$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180484$11535_Y + connect \Y $not$libresoc.v:182632$11686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180485$11536 + cell $not $not$libresoc.v:182633$11687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180485$11536_Y + connect \Y $not$libresoc.v:182633$11687_Y end - attribute \src "libresoc.v:180405.7-180405.20" - process $proc$libresoc.v:180405$11614 + attribute \src "libresoc.v:182541.7-182541.20" + process $proc$libresoc.v:182541$11780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180430.13-180430.31" - process $proc$libresoc.v:180430$11615 + attribute \src "libresoc.v:182560.13-182560.36" + process $proc$libresoc.v:182560$11781 + assign { } { } + assign $1\cr_pred6__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182575.13-182575.31" + process $proc$libresoc.v:182575$11782 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:180437.13-180437.30" - process $proc$libresoc.v:180437$11616 + attribute \src "libresoc.v:182582.13-182582.30" + process $proc$libresoc.v:182582$11783 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:180443.13-180443.25" - process $proc$libresoc.v:180443$11617 + attribute \src "libresoc.v:182588.13-182588.25" + process $proc$libresoc.v:182588$11784 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180448.13-180448.33" - process $proc$libresoc.v:180448$11618 + attribute \src "libresoc.v:182593.13-182593.33" + process $proc$libresoc.v:182593$11785 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:180455.13-180455.33" - process $proc$libresoc.v:180455$11619 + attribute \src "libresoc.v:182600.13-182600.33" + process $proc$libresoc.v:182600$11786 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:180462.13-180462.33" - process $proc$libresoc.v:180462$11620 + attribute \src "libresoc.v:182607.13-182607.33" + process $proc$libresoc.v:182607$11787 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:180486.3-180487.25" - process $proc$libresoc.v:180486$11537 + attribute \src "libresoc.v:182634.3-182635.25" + process $proc$libresoc.v:182634$11688 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180488.3-180489.39" - process $proc$libresoc.v:180488$11538 + attribute \src "libresoc.v:182636.3-182637.39" + process $proc$libresoc.v:182636$11689 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:180490.3-180491.37" - process $proc$libresoc.v:180490$11539 + attribute \src "libresoc.v:182638.3-182639.37" + process $proc$libresoc.v:182638$11690 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:180492.3-180493.43" - process $proc$libresoc.v:180492$11540 + attribute \src "libresoc.v:182640.3-182641.43" + process $proc$libresoc.v:182640$11691 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:180494.3-180495.43" - process $proc$libresoc.v:180494$11541 + attribute \src "libresoc.v:182642.3-182643.43" + process $proc$libresoc.v:182642$11692 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:180496.3-180497.43" - process $proc$libresoc.v:180496$11542 + attribute \src "libresoc.v:182644.3-182645.43" + process $proc$libresoc.v:182644$11693 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:180498.3-180537.6" - process $proc$libresoc.v:180498$11543 + attribute \src "libresoc.v:182646.3-182647.49" + process $proc$libresoc.v:182646$11694 + assign { } { } + assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next + sync posedge \coresync_clk + update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182648.3-182687.6" + process $proc$libresoc.v:182648$11695 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11544 $6\src16__data_o$next[3:0]$11550 - attribute \src "libresoc.v:180499.5-180499.29" + assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182649.5-182649.29" switch \initial - attribute \src "libresoc.v:180499.9-180499.17" + attribute \src "libresoc.v:182649.9-182649.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + switch \cr_pred6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11545 $5\src16__data_o$next[3:0]$11549 + assign $1\cr_pred6__data_o$next[3:0]$11697 $5\cr_pred6__data_o$next[3:0]$11701 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11546 \dest16__data_i + assign $2\cr_pred6__data_o$next[3:0]$11698 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11546 4'0000 + assign $2\cr_pred6__data_o$next[3:0]$11698 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11547 \dest26__data_i + assign $3\cr_pred6__data_o$next[3:0]$11699 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11547 $2\src16__data_o$next[3:0]$11546 + assign $3\cr_pred6__data_o$next[3:0]$11699 $2\cr_pred6__data_o$next[3:0]$11698 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11548 \w6__data_i + assign $4\cr_pred6__data_o$next[3:0]$11700 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11548 $3\src16__data_o$next[3:0]$11547 + assign $4\cr_pred6__data_o$next[3:0]$11700 $3\cr_pred6__data_o$next[3:0]$11699 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11549 \reg + assign $5\cr_pred6__data_o$next[3:0]$11701 \reg case - assign $5\src16__data_o$next[3:0]$11549 $4\src16__data_o$next[3:0]$11548 + assign $5\cr_pred6__data_o$next[3:0]$11701 $4\cr_pred6__data_o$next[3:0]$11700 end case - assign $1\src16__data_o$next[3:0]$11545 4'0000 + assign $1\cr_pred6__data_o$next[3:0]$11697 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11550 4'0000 + assign $6\cr_pred6__data_o$next[3:0]$11702 4'0000 case - assign $6\src16__data_o$next[3:0]$11550 $1\src16__data_o$next[3:0]$11545 + assign $6\cr_pred6__data_o$next[3:0]$11702 $1\cr_pred6__data_o$next[3:0]$11697 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11544 + update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 end - attribute \src "libresoc.v:180538.3-180567.6" - process $proc$libresoc.v:180538$11551 + attribute \src "libresoc.v:182688.3-182717.6" + process $proc$libresoc.v:182688$11703 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180539.5-180539.29" + attribute \src "libresoc.v:182689.5-182689.29" switch \initial - attribute \src "libresoc.v:180539.9-180539.17" + attribute \src "libresoc.v:182689.9-182689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + switch \cr_pred6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -372512,798 +376206,962 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180568.3-180594.6" - process $proc$libresoc.v:180568$11552 - assign { } { } + attribute \src "libresoc.v:182718.3-182757.6" + process $proc$libresoc.v:182718$11704 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11553 $4\reg$next[3:0]$11557 - attribute \src "libresoc.v:180569.5-180569.29" + assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:182719.5-182719.29" switch \initial - attribute \src "libresoc.v:180569.9-180569.17" + attribute \src "libresoc.v:182719.9-182719.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest16__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11554 \dest16__data_i - case - assign $1\reg$next[3:0]$11554 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11555 \dest26__data_i - case - assign $2\reg$next[3:0]$11555 $1\reg$next[3:0]$11554 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11556 \w6__data_i + assign { } { } + assign $1\r26__data_o$next[3:0]$11706 $5\r26__data_o$next[3:0]$11710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11707 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11707 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11708 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11708 $2\r26__data_o$next[3:0]$11707 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11709 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11709 $3\r26__data_o$next[3:0]$11708 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11710 \reg + case + assign $5\r26__data_o$next[3:0]$11710 $4\r26__data_o$next[3:0]$11709 + end case - assign $3\reg$next[3:0]$11556 $2\reg$next[3:0]$11555 + assign $1\r26__data_o$next[3:0]$11706 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11557 4'0000 + assign $6\r26__data_o$next[3:0]$11711 4'0000 case - assign $4\reg$next[3:0]$11557 $3\reg$next[3:0]$11556 + assign $6\r26__data_o$next[3:0]$11711 $1\r26__data_o$next[3:0]$11706 end sync always - update \reg$next $0\reg$next[3:0]$11553 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 end - attribute \src "libresoc.v:180595.3-180634.6" - process $proc$libresoc.v:180595$11558 - assign { } { } + attribute \src "libresoc.v:182758.3-182787.6" + process $proc$libresoc.v:182758$11712 assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11559 $6\src26__data_o$next[3:0]$11565 - attribute \src "libresoc.v:180596.5-180596.29" + assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182759.5-182759.29" switch \initial - attribute \src "libresoc.v:180596.9-180596.17" + attribute \src "libresoc.v:182759.9-182759.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11560 $5\src26__data_o$next[3:0]$11564 + assign $1\wr_detect$16[0:0]$11714 $4\wr_detect$16[0:0]$11717 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11561 \dest16__data_i + assign $2\wr_detect$16[0:0]$11715 1'1 case - assign $2\src26__data_o$next[3:0]$11561 4'0000 + assign $2\wr_detect$16[0:0]$11715 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11562 \dest26__data_i + assign $3\wr_detect$16[0:0]$11716 1'1 case - assign $3\src26__data_o$next[3:0]$11562 $2\src26__data_o$next[3:0]$11561 + assign $3\wr_detect$16[0:0]$11716 $2\wr_detect$16[0:0]$11715 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11563 \w6__data_i + assign $4\wr_detect$16[0:0]$11717 1'1 case - assign $4\src26__data_o$next[3:0]$11563 $3\src26__data_o$next[3:0]$11562 + assign $4\wr_detect$16[0:0]$11717 $3\wr_detect$16[0:0]$11716 + end + case + assign $1\wr_detect$16[0:0]$11714 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11713 + end + attribute \src "libresoc.v:182788.3-182814.6" + process $proc$libresoc.v:182788$11718 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182789.5-182789.29" + switch \initial + attribute \src "libresoc.v:182789.9-182789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11720 \dest16__data_i + case + assign $1\reg$next[3:0]$11720 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11721 \dest26__data_i + case + assign $2\reg$next[3:0]$11721 $1\reg$next[3:0]$11720 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11722 \w6__data_i + case + assign $3\reg$next[3:0]$11722 $2\reg$next[3:0]$11721 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11723 4'0000 + case + assign $4\reg$next[3:0]$11723 $3\reg$next[3:0]$11722 + end + sync always + update \reg$next $0\reg$next[3:0]$11719 + end + attribute \src "libresoc.v:182815.3-182854.6" + process $proc$libresoc.v:182815$11724 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182816.5-182816.29" + switch \initial + attribute \src "libresoc.v:182816.9-182816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11726 $5\src16__data_o$next[3:0]$11730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11727 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11727 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11728 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11728 $2\src16__data_o$next[3:0]$11727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11729 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11729 $3\src16__data_o$next[3:0]$11728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11564 \reg + assign $5\src16__data_o$next[3:0]$11730 \reg case - assign $5\src26__data_o$next[3:0]$11564 $4\src26__data_o$next[3:0]$11563 + assign $5\src16__data_o$next[3:0]$11730 $4\src16__data_o$next[3:0]$11729 end case - assign $1\src26__data_o$next[3:0]$11560 4'0000 + assign $1\src16__data_o$next[3:0]$11726 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11565 4'0000 + assign $6\src16__data_o$next[3:0]$11731 4'0000 case - assign $6\src26__data_o$next[3:0]$11565 $1\src26__data_o$next[3:0]$11560 + assign $6\src16__data_o$next[3:0]$11731 $1\src16__data_o$next[3:0]$11726 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11559 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 end - attribute \src "libresoc.v:180635.3-180664.6" - process $proc$libresoc.v:180635$11566 + attribute \src "libresoc.v:182855.3-182884.6" + process $proc$libresoc.v:182855$11732 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11567 $1\wr_detect$4[0:0]$11568 - attribute \src "libresoc.v:180636.5-180636.29" + assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182856.5-182856.29" switch \initial - attribute \src "libresoc.v:180636.9-180636.17" + attribute \src "libresoc.v:182856.9-182856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11568 $4\wr_detect$4[0:0]$11571 + assign $1\wr_detect$4[0:0]$11734 $4\wr_detect$4[0:0]$11737 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11569 1'1 + assign $2\wr_detect$4[0:0]$11735 1'1 case - assign $2\wr_detect$4[0:0]$11569 1'0 + assign $2\wr_detect$4[0:0]$11735 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11570 1'1 + assign $3\wr_detect$4[0:0]$11736 1'1 case - assign $3\wr_detect$4[0:0]$11570 $2\wr_detect$4[0:0]$11569 + assign $3\wr_detect$4[0:0]$11736 $2\wr_detect$4[0:0]$11735 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11571 1'1 + assign $4\wr_detect$4[0:0]$11737 1'1 case - assign $4\wr_detect$4[0:0]$11571 $3\wr_detect$4[0:0]$11570 + assign $4\wr_detect$4[0:0]$11737 $3\wr_detect$4[0:0]$11736 end case - assign $1\wr_detect$4[0:0]$11568 1'0 + assign $1\wr_detect$4[0:0]$11734 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11567 + update \wr_detect$4 $0\wr_detect$4[0:0]$11733 end - attribute \src "libresoc.v:180665.3-180704.6" - process $proc$libresoc.v:180665$11572 + attribute \src "libresoc.v:182885.3-182924.6" + process $proc$libresoc.v:182885$11738 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11573 $6\src36__data_o$next[3:0]$11579 - attribute \src "libresoc.v:180666.5-180666.29" + assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182886.5-182886.29" switch \initial - attribute \src "libresoc.v:180666.9-180666.17" + attribute \src "libresoc.v:182886.9-182886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11574 $5\src36__data_o$next[3:0]$11578 + assign $1\src26__data_o$next[3:0]$11740 $5\src26__data_o$next[3:0]$11744 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11575 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11741 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11575 4'0000 + assign $2\src26__data_o$next[3:0]$11741 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11576 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11742 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11576 $2\src36__data_o$next[3:0]$11575 + assign $3\src26__data_o$next[3:0]$11742 $2\src26__data_o$next[3:0]$11741 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11577 \w6__data_i + assign $4\src26__data_o$next[3:0]$11743 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11577 $3\src36__data_o$next[3:0]$11576 + assign $4\src26__data_o$next[3:0]$11743 $3\src26__data_o$next[3:0]$11742 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11578 \reg + assign $5\src26__data_o$next[3:0]$11744 \reg case - assign $5\src36__data_o$next[3:0]$11578 $4\src36__data_o$next[3:0]$11577 + assign $5\src26__data_o$next[3:0]$11744 $4\src26__data_o$next[3:0]$11743 end case - assign $1\src36__data_o$next[3:0]$11574 4'0000 + assign $1\src26__data_o$next[3:0]$11740 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11579 4'0000 + assign $6\src26__data_o$next[3:0]$11745 4'0000 case - assign $6\src36__data_o$next[3:0]$11579 $1\src36__data_o$next[3:0]$11574 + assign $6\src26__data_o$next[3:0]$11745 $1\src26__data_o$next[3:0]$11740 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11573 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 end - attribute \src "libresoc.v:180705.3-180734.6" - process $proc$libresoc.v:180705$11580 + attribute \src "libresoc.v:182925.3-182954.6" + process $proc$libresoc.v:182925$11746 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11581 $1\wr_detect$7[0:0]$11582 - attribute \src "libresoc.v:180706.5-180706.29" + assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182926.5-182926.29" switch \initial - attribute \src "libresoc.v:180706.9-180706.17" + attribute \src "libresoc.v:182926.9-182926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11582 $4\wr_detect$7[0:0]$11585 + assign $1\wr_detect$7[0:0]$11748 $4\wr_detect$7[0:0]$11751 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11583 1'1 + assign $2\wr_detect$7[0:0]$11749 1'1 case - assign $2\wr_detect$7[0:0]$11583 1'0 + assign $2\wr_detect$7[0:0]$11749 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11584 1'1 + assign $3\wr_detect$7[0:0]$11750 1'1 case - assign $3\wr_detect$7[0:0]$11584 $2\wr_detect$7[0:0]$11583 + assign $3\wr_detect$7[0:0]$11750 $2\wr_detect$7[0:0]$11749 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11585 1'1 + assign $4\wr_detect$7[0:0]$11751 1'1 case - assign $4\wr_detect$7[0:0]$11585 $3\wr_detect$7[0:0]$11584 + assign $4\wr_detect$7[0:0]$11751 $3\wr_detect$7[0:0]$11750 end case - assign $1\wr_detect$7[0:0]$11582 1'0 + assign $1\wr_detect$7[0:0]$11748 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11581 + update \wr_detect$7 $0\wr_detect$7[0:0]$11747 end - attribute \src "libresoc.v:180735.3-180774.6" - process $proc$libresoc.v:180735$11586 + attribute \src "libresoc.v:182955.3-182994.6" + process $proc$libresoc.v:182955$11752 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11587 $6\r6__data_o$next[3:0]$11593 - attribute \src "libresoc.v:180736.5-180736.29" + assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182956.5-182956.29" switch \initial - attribute \src "libresoc.v:180736.9-180736.17" + attribute \src "libresoc.v:182956.9-182956.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11588 $5\r6__data_o$next[3:0]$11592 + assign $1\src36__data_o$next[3:0]$11754 $5\src36__data_o$next[3:0]$11758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11589 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11755 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11589 4'0000 + assign $2\src36__data_o$next[3:0]$11755 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11590 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11756 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11590 $2\r6__data_o$next[3:0]$11589 + assign $3\src36__data_o$next[3:0]$11756 $2\src36__data_o$next[3:0]$11755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11591 \w6__data_i + assign $4\src36__data_o$next[3:0]$11757 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11591 $3\r6__data_o$next[3:0]$11590 + assign $4\src36__data_o$next[3:0]$11757 $3\src36__data_o$next[3:0]$11756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11592 \reg + assign $5\src36__data_o$next[3:0]$11758 \reg case - assign $5\r6__data_o$next[3:0]$11592 $4\r6__data_o$next[3:0]$11591 + assign $5\src36__data_o$next[3:0]$11758 $4\src36__data_o$next[3:0]$11757 end case - assign $1\r6__data_o$next[3:0]$11588 4'0000 + assign $1\src36__data_o$next[3:0]$11754 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11593 4'0000 + assign $6\src36__data_o$next[3:0]$11759 4'0000 case - assign $6\r6__data_o$next[3:0]$11593 $1\r6__data_o$next[3:0]$11588 + assign $6\src36__data_o$next[3:0]$11759 $1\src36__data_o$next[3:0]$11754 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11587 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 end - attribute \src "libresoc.v:180775.3-180804.6" - process $proc$libresoc.v:180775$11594 + attribute \src "libresoc.v:182995.3-183024.6" + process $proc$libresoc.v:182995$11760 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11595 $1\wr_detect$10[0:0]$11596 - attribute \src "libresoc.v:180776.5-180776.29" + assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:182996.5-182996.29" switch \initial - attribute \src "libresoc.v:180776.9-180776.17" + attribute \src "libresoc.v:182996.9-182996.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11596 $4\wr_detect$10[0:0]$11599 + assign $1\wr_detect$10[0:0]$11762 $4\wr_detect$10[0:0]$11765 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11597 1'1 + assign $2\wr_detect$10[0:0]$11763 1'1 case - assign $2\wr_detect$10[0:0]$11597 1'0 + assign $2\wr_detect$10[0:0]$11763 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11598 1'1 + assign $3\wr_detect$10[0:0]$11764 1'1 case - assign $3\wr_detect$10[0:0]$11598 $2\wr_detect$10[0:0]$11597 + assign $3\wr_detect$10[0:0]$11764 $2\wr_detect$10[0:0]$11763 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11599 1'1 + assign $4\wr_detect$10[0:0]$11765 1'1 case - assign $4\wr_detect$10[0:0]$11599 $3\wr_detect$10[0:0]$11598 + assign $4\wr_detect$10[0:0]$11765 $3\wr_detect$10[0:0]$11764 end case - assign $1\wr_detect$10[0:0]$11596 1'0 + assign $1\wr_detect$10[0:0]$11762 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11595 + update \wr_detect$10 $0\wr_detect$10[0:0]$11761 end - attribute \src "libresoc.v:180805.3-180844.6" - process $proc$libresoc.v:180805$11600 + attribute \src "libresoc.v:183025.3-183064.6" + process $proc$libresoc.v:183025$11766 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11601 $6\r26__data_o$next[3:0]$11607 - attribute \src "libresoc.v:180806.5-180806.29" + assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:183026.5-183026.29" switch \initial - attribute \src "libresoc.v:180806.9-180806.17" + attribute \src "libresoc.v:183026.9-183026.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11602 $5\r26__data_o$next[3:0]$11606 + assign $1\r6__data_o$next[3:0]$11768 $5\r6__data_o$next[3:0]$11772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11603 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11769 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11603 4'0000 + assign $2\r6__data_o$next[3:0]$11769 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11604 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11770 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11604 $2\r26__data_o$next[3:0]$11603 + assign $3\r6__data_o$next[3:0]$11770 $2\r6__data_o$next[3:0]$11769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11605 \w6__data_i + assign $4\r6__data_o$next[3:0]$11771 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11605 $3\r26__data_o$next[3:0]$11604 + assign $4\r6__data_o$next[3:0]$11771 $3\r6__data_o$next[3:0]$11770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11606 \reg + assign $5\r6__data_o$next[3:0]$11772 \reg case - assign $5\r26__data_o$next[3:0]$11606 $4\r26__data_o$next[3:0]$11605 + assign $5\r6__data_o$next[3:0]$11772 $4\r6__data_o$next[3:0]$11771 end case - assign $1\r26__data_o$next[3:0]$11602 4'0000 + assign $1\r6__data_o$next[3:0]$11768 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11607 4'0000 + assign $6\r6__data_o$next[3:0]$11773 4'0000 case - assign $6\r26__data_o$next[3:0]$11607 $1\r26__data_o$next[3:0]$11602 + assign $6\r6__data_o$next[3:0]$11773 $1\r6__data_o$next[3:0]$11768 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11601 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 end - attribute \src "libresoc.v:180845.3-180874.6" - process $proc$libresoc.v:180845$11608 + attribute \src "libresoc.v:183065.3-183094.6" + process $proc$libresoc.v:183065$11774 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11609 $1\wr_detect$13[0:0]$11610 - attribute \src "libresoc.v:180846.5-180846.29" + assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:183066.5-183066.29" switch \initial - attribute \src "libresoc.v:180846.9-180846.17" + attribute \src "libresoc.v:183066.9-183066.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11610 $4\wr_detect$13[0:0]$11613 + assign $1\wr_detect$13[0:0]$11776 $4\wr_detect$13[0:0]$11779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11611 1'1 + assign $2\wr_detect$13[0:0]$11777 1'1 case - assign $2\wr_detect$13[0:0]$11611 1'0 + assign $2\wr_detect$13[0:0]$11777 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11612 1'1 + assign $3\wr_detect$13[0:0]$11778 1'1 case - assign $3\wr_detect$13[0:0]$11612 $2\wr_detect$13[0:0]$11611 + assign $3\wr_detect$13[0:0]$11778 $2\wr_detect$13[0:0]$11777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11613 1'1 + assign $4\wr_detect$13[0:0]$11779 1'1 case - assign $4\wr_detect$13[0:0]$11613 $3\wr_detect$13[0:0]$11612 + assign $4\wr_detect$13[0:0]$11779 $3\wr_detect$13[0:0]$11778 end case - assign $1\wr_detect$13[0:0]$11610 1'0 + assign $1\wr_detect$13[0:0]$11776 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11609 + update \wr_detect$13 $0\wr_detect$13[0:0]$11775 end - connect \$9 $not$libresoc.v:180481$11532_Y - connect \$12 $not$libresoc.v:180482$11533_Y - connect \$1 $not$libresoc.v:180483$11534_Y - connect \$3 $not$libresoc.v:180484$11535_Y - connect \$6 $not$libresoc.v:180485$11536_Y + connect \$9 $not$libresoc.v:182628$11682_Y + connect \$12 $not$libresoc.v:182629$11683_Y + connect \$15 $not$libresoc.v:182630$11684_Y + connect \$1 $not$libresoc.v:182631$11685_Y + connect \$3 $not$libresoc.v:182632$11686_Y + connect \$6 $not$libresoc.v:182633$11687_Y end -attribute \src "libresoc.v:180879.1-181350.10" +attribute \src "libresoc.v:183099.1-183654.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:180880.7-180880.20" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 + attribute \src "libresoc.v:183205.3-183206.49" + wire width 4 $0\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183100.7-183100.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $0\r27__data_o$next[3:0]$11690 - attribute \src "libresoc.v:180963.3-180964.39" + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $0\r27__data_o$next[3:0]$11811 + attribute \src "libresoc.v:183195.3-183196.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $0\r7__data_o$next[3:0]$11676 - attribute \src "libresoc.v:180965.3-180966.37" + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $0\r7__data_o$next[3:0]$11873 + attribute \src "libresoc.v:183197.3-183198.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $0\reg$next[3:0]$11642 - attribute \src "libresoc.v:180961.3-180962.25" + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $0\reg$next[3:0]$11825 + attribute \src "libresoc.v:183193.3-183194.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $0\src17__data_o$next[3:0]$11633 - attribute \src "libresoc.v:180971.3-180972.43" + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $0\src17__data_o$next[3:0]$11831 + attribute \src "libresoc.v:183203.3-183204.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $0\src27__data_o$next[3:0]$11648 - attribute \src "libresoc.v:180969.3-180970.43" + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $0\src27__data_o$next[3:0]$11845 + attribute \src "libresoc.v:183201.3-183202.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $0\src37__data_o$next[3:0]$11662 - attribute \src "libresoc.v:180967.3-180968.43" + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $0\src37__data_o$next[3:0]$11859 + attribute \src "libresoc.v:183199.3-183200.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:181250.3-181279.6" - wire $0\wr_detect$10[0:0]$11684 - attribute \src "libresoc.v:181320.3-181349.6" - wire $0\wr_detect$13[0:0]$11698 - attribute \src "libresoc.v:181110.3-181139.6" - wire $0\wr_detect$4[0:0]$11656 - attribute \src "libresoc.v:181180.3-181209.6" - wire $0\wr_detect$7[0:0]$11670 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183554.3-183583.6" + wire $0\wr_detect$10[0:0]$11867 + attribute \src "libresoc.v:183624.3-183653.6" + wire $0\wr_detect$13[0:0]$11881 + attribute \src "libresoc.v:183317.3-183346.6" + wire $0\wr_detect$16[0:0]$11819 + attribute \src "libresoc.v:183414.3-183443.6" + wire $0\wr_detect$4[0:0]$11839 + attribute \src "libresoc.v:183484.3-183513.6" + wire $0\wr_detect$7[0:0]$11853 + attribute \src "libresoc.v:183247.3-183276.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $1\r27__data_o$next[3:0]$11691 - attribute \src "libresoc.v:180905.13-180905.31" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 + attribute \src "libresoc.v:183119.13-183119.36" + wire width 4 $1\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $1\r27__data_o$next[3:0]$11812 + attribute \src "libresoc.v:183134.13-183134.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $1\r7__data_o$next[3:0]$11677 - attribute \src "libresoc.v:180912.13-180912.30" + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $1\r7__data_o$next[3:0]$11874 + attribute \src "libresoc.v:183141.13-183141.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $1\reg$next[3:0]$11643 - attribute \src "libresoc.v:180918.13-180918.25" + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $1\reg$next[3:0]$11826 + attribute \src "libresoc.v:183147.13-183147.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $1\src17__data_o$next[3:0]$11634 - attribute \src "libresoc.v:180923.13-180923.33" + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $1\src17__data_o$next[3:0]$11832 + attribute \src "libresoc.v:183152.13-183152.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $1\src27__data_o$next[3:0]$11649 - attribute \src "libresoc.v:180930.13-180930.33" + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $1\src27__data_o$next[3:0]$11846 + attribute \src "libresoc.v:183159.13-183159.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $1\src37__data_o$next[3:0]$11663 - attribute \src "libresoc.v:180937.13-180937.33" + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $1\src37__data_o$next[3:0]$11860 + attribute \src "libresoc.v:183166.13-183166.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:181250.3-181279.6" - wire $1\wr_detect$10[0:0]$11685 - attribute \src "libresoc.v:181320.3-181349.6" - wire $1\wr_detect$13[0:0]$11699 - attribute \src "libresoc.v:181110.3-181139.6" - wire $1\wr_detect$4[0:0]$11657 - attribute \src "libresoc.v:181180.3-181209.6" - wire $1\wr_detect$7[0:0]$11671 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183554.3-183583.6" + wire $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183624.3-183653.6" + wire $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183317.3-183346.6" + wire $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183414.3-183443.6" + wire $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183484.3-183513.6" + wire $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183247.3-183276.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $2\r27__data_o$next[3:0]$11692 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $2\r7__data_o$next[3:0]$11678 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $2\reg$next[3:0]$11644 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $2\src17__data_o$next[3:0]$11635 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $2\src27__data_o$next[3:0]$11650 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $2\src37__data_o$next[3:0]$11664 - attribute \src "libresoc.v:181250.3-181279.6" - wire $2\wr_detect$10[0:0]$11686 - attribute \src "libresoc.v:181320.3-181349.6" - wire $2\wr_detect$13[0:0]$11700 - attribute \src "libresoc.v:181110.3-181139.6" - wire $2\wr_detect$4[0:0]$11658 - attribute \src "libresoc.v:181180.3-181209.6" - wire $2\wr_detect$7[0:0]$11672 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $2\r27__data_o$next[3:0]$11813 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $2\r7__data_o$next[3:0]$11875 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $2\reg$next[3:0]$11827 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $2\src17__data_o$next[3:0]$11833 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $2\src27__data_o$next[3:0]$11847 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $2\src37__data_o$next[3:0]$11861 + attribute \src "libresoc.v:183554.3-183583.6" + wire $2\wr_detect$10[0:0]$11869 + attribute \src "libresoc.v:183624.3-183653.6" + wire $2\wr_detect$13[0:0]$11883 + attribute \src "libresoc.v:183317.3-183346.6" + wire $2\wr_detect$16[0:0]$11821 + attribute \src "libresoc.v:183414.3-183443.6" + wire $2\wr_detect$4[0:0]$11841 + attribute \src "libresoc.v:183484.3-183513.6" + wire $2\wr_detect$7[0:0]$11855 + attribute \src "libresoc.v:183247.3-183276.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $3\r27__data_o$next[3:0]$11693 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $3\r7__data_o$next[3:0]$11679 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $3\reg$next[3:0]$11645 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $3\src17__data_o$next[3:0]$11636 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $3\src27__data_o$next[3:0]$11651 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $3\src37__data_o$next[3:0]$11665 - attribute \src "libresoc.v:181250.3-181279.6" - wire $3\wr_detect$10[0:0]$11687 - attribute \src "libresoc.v:181320.3-181349.6" - wire $3\wr_detect$13[0:0]$11701 - attribute \src "libresoc.v:181110.3-181139.6" - wire $3\wr_detect$4[0:0]$11659 - attribute \src "libresoc.v:181180.3-181209.6" - wire $3\wr_detect$7[0:0]$11673 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $3\r27__data_o$next[3:0]$11814 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $3\r7__data_o$next[3:0]$11876 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $3\reg$next[3:0]$11828 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $3\src17__data_o$next[3:0]$11834 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $3\src27__data_o$next[3:0]$11848 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $3\src37__data_o$next[3:0]$11862 + attribute \src "libresoc.v:183554.3-183583.6" + wire $3\wr_detect$10[0:0]$11870 + attribute \src "libresoc.v:183624.3-183653.6" + wire $3\wr_detect$13[0:0]$11884 + attribute \src "libresoc.v:183317.3-183346.6" + wire $3\wr_detect$16[0:0]$11822 + attribute \src "libresoc.v:183414.3-183443.6" + wire $3\wr_detect$4[0:0]$11842 + attribute \src "libresoc.v:183484.3-183513.6" + wire $3\wr_detect$7[0:0]$11856 + attribute \src "libresoc.v:183247.3-183276.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $4\r27__data_o$next[3:0]$11694 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $4\r7__data_o$next[3:0]$11680 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $4\reg$next[3:0]$11646 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $4\src17__data_o$next[3:0]$11637 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $4\src27__data_o$next[3:0]$11652 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $4\src37__data_o$next[3:0]$11666 - attribute \src "libresoc.v:181250.3-181279.6" - wire $4\wr_detect$10[0:0]$11688 - attribute \src "libresoc.v:181320.3-181349.6" - wire $4\wr_detect$13[0:0]$11702 - attribute \src "libresoc.v:181110.3-181139.6" - wire $4\wr_detect$4[0:0]$11660 - attribute \src "libresoc.v:181180.3-181209.6" - wire $4\wr_detect$7[0:0]$11674 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $4\r27__data_o$next[3:0]$11815 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $4\r7__data_o$next[3:0]$11877 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $4\src17__data_o$next[3:0]$11835 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $4\src27__data_o$next[3:0]$11849 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $4\src37__data_o$next[3:0]$11863 + attribute \src "libresoc.v:183554.3-183583.6" + wire $4\wr_detect$10[0:0]$11871 + attribute \src "libresoc.v:183624.3-183653.6" + wire $4\wr_detect$13[0:0]$11885 + attribute \src "libresoc.v:183317.3-183346.6" + wire $4\wr_detect$16[0:0]$11823 + attribute \src "libresoc.v:183414.3-183443.6" + wire $4\wr_detect$4[0:0]$11843 + attribute \src "libresoc.v:183484.3-183513.6" + wire $4\wr_detect$7[0:0]$11857 + attribute \src "libresoc.v:183247.3-183276.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $5\r27__data_o$next[3:0]$11695 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $5\r7__data_o$next[3:0]$11681 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $5\src17__data_o$next[3:0]$11638 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $5\src27__data_o$next[3:0]$11653 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $5\src37__data_o$next[3:0]$11667 - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $6\r27__data_o$next[3:0]$11696 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $6\r7__data_o$next[3:0]$11682 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $6\src17__data_o$next[3:0]$11639 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $6\src27__data_o$next[3:0]$11654 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $6\src37__data_o$next[3:0]$11668 - attribute \src "libresoc.v:180956.17-180956.104" - wire $not$libresoc.v:180956$11621_Y - attribute \src "libresoc.v:180957.18-180957.105" - wire $not$libresoc.v:180957$11622_Y - attribute \src "libresoc.v:180958.17-180958.100" - wire $not$libresoc.v:180958$11623_Y - attribute \src "libresoc.v:180959.17-180959.103" - wire $not$libresoc.v:180959$11624_Y - attribute \src "libresoc.v:180960.17-180960.103" - wire $not$libresoc.v:180960$11625_Y + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $5\r27__data_o$next[3:0]$11816 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $5\r7__data_o$next[3:0]$11878 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $5\src17__data_o$next[3:0]$11836 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $5\src27__data_o$next[3:0]$11850 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $5\src37__data_o$next[3:0]$11864 + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183187.17-183187.104" + wire $not$libresoc.v:183187$11788_Y + attribute \src "libresoc.v:183188.18-183188.105" + wire $not$libresoc.v:183188$11789_Y + attribute \src "libresoc.v:183189.18-183189.105" + wire $not$libresoc.v:183189$11790_Y + attribute \src "libresoc.v:183190.17-183190.100" + wire $not$libresoc.v:183190$11791_Y + attribute \src "libresoc.v:183191.17-183191.103" + wire $not$libresoc.v:183191$11792_Y + attribute \src "libresoc.v:183192.17-183192.103" + wire $not$libresoc.v:183192$11793_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest17__data_i + wire width 4 output 3 \cr_pred7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest17__wen + wire width 4 \cr_pred7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest27__data_i + wire input 2 \cr_pred7__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest27__wen - attribute \src "libresoc.v:180880.7-180880.15" + wire width 4 input 11 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest27__wen + attribute \src "libresoc.v:183100.7-183100.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r27__data_o + wire width 4 output 16 \r27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r27__ren + wire input 17 \r27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r7__data_o + wire width 4 output 14 \r7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r7__ren + wire input 15 \r7__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src17__data_o + wire width 4 output 5 \src17__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src17__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src17__ren + wire input 4 \src17__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src27__data_o + wire width 4 output 7 \src27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src27__ren + wire input 6 \src27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src37__data_o + wire width 4 output 9 \src37__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src37__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src37__ren + wire input 8 \src37__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w7__data_i + wire width 4 input 18 \w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w7__wen + wire input 19 \w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -373311,232 +377169,257 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180956$11621 + cell $not $not$libresoc.v:183187$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180956$11621_Y + connect \Y $not$libresoc.v:183187$11788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180957$11622 + cell $not $not$libresoc.v:183188$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180957$11622_Y + connect \Y $not$libresoc.v:183188$11789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183189$11790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:183189$11790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180958$11623 + cell $not $not$libresoc.v:183190$11791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180958$11623_Y + connect \Y $not$libresoc.v:183190$11791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180959$11624 + cell $not $not$libresoc.v:183191$11792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180959$11624_Y + connect \Y $not$libresoc.v:183191$11792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180960$11625 + cell $not $not$libresoc.v:183192$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180960$11625_Y + connect \Y $not$libresoc.v:183192$11793_Y end - attribute \src "libresoc.v:180880.7-180880.20" - process $proc$libresoc.v:180880$11703 + attribute \src "libresoc.v:183100.7-183100.20" + process $proc$libresoc.v:183100$11886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180905.13-180905.31" - process $proc$libresoc.v:180905$11704 + attribute \src "libresoc.v:183119.13-183119.36" + process $proc$libresoc.v:183119$11887 + assign { } { } + assign $1\cr_pred7__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183134.13-183134.31" + process $proc$libresoc.v:183134$11888 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:180912.13-180912.30" - process $proc$libresoc.v:180912$11705 + attribute \src "libresoc.v:183141.13-183141.30" + process $proc$libresoc.v:183141$11889 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:180918.13-180918.25" - process $proc$libresoc.v:180918$11706 + attribute \src "libresoc.v:183147.13-183147.25" + process $proc$libresoc.v:183147$11890 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180923.13-180923.33" - process $proc$libresoc.v:180923$11707 + attribute \src "libresoc.v:183152.13-183152.33" + process $proc$libresoc.v:183152$11891 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:180930.13-180930.33" - process $proc$libresoc.v:180930$11708 + attribute \src "libresoc.v:183159.13-183159.33" + process $proc$libresoc.v:183159$11892 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:180937.13-180937.33" - process $proc$libresoc.v:180937$11709 + attribute \src "libresoc.v:183166.13-183166.33" + process $proc$libresoc.v:183166$11893 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:180961.3-180962.25" - process $proc$libresoc.v:180961$11626 + attribute \src "libresoc.v:183193.3-183194.25" + process $proc$libresoc.v:183193$11794 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180963.3-180964.39" - process $proc$libresoc.v:180963$11627 + attribute \src "libresoc.v:183195.3-183196.39" + process $proc$libresoc.v:183195$11795 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:180965.3-180966.37" - process $proc$libresoc.v:180965$11628 + attribute \src "libresoc.v:183197.3-183198.37" + process $proc$libresoc.v:183197$11796 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:180967.3-180968.43" - process $proc$libresoc.v:180967$11629 + attribute \src "libresoc.v:183199.3-183200.43" + process $proc$libresoc.v:183199$11797 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:180969.3-180970.43" - process $proc$libresoc.v:180969$11630 + attribute \src "libresoc.v:183201.3-183202.43" + process $proc$libresoc.v:183201$11798 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:180971.3-180972.43" - process $proc$libresoc.v:180971$11631 + attribute \src "libresoc.v:183203.3-183204.43" + process $proc$libresoc.v:183203$11799 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:180973.3-181012.6" - process $proc$libresoc.v:180973$11632 + attribute \src "libresoc.v:183205.3-183206.49" + process $proc$libresoc.v:183205$11800 + assign { } { } + assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next + sync posedge \coresync_clk + update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183207.3-183246.6" + process $proc$libresoc.v:183207$11801 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11633 $6\src17__data_o$next[3:0]$11639 - attribute \src "libresoc.v:180974.5-180974.29" + assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183208.5-183208.29" switch \initial - attribute \src "libresoc.v:180974.9-180974.17" + attribute \src "libresoc.v:183208.9-183208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \cr_pred7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11634 $5\src17__data_o$next[3:0]$11638 + assign $1\cr_pred7__data_o$next[3:0]$11803 $5\cr_pred7__data_o$next[3:0]$11807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11635 \dest17__data_i + assign $2\cr_pred7__data_o$next[3:0]$11804 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11635 4'0000 + assign $2\cr_pred7__data_o$next[3:0]$11804 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11636 \dest27__data_i + assign $3\cr_pred7__data_o$next[3:0]$11805 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11636 $2\src17__data_o$next[3:0]$11635 + assign $3\cr_pred7__data_o$next[3:0]$11805 $2\cr_pred7__data_o$next[3:0]$11804 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11637 \w7__data_i + assign $4\cr_pred7__data_o$next[3:0]$11806 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11637 $3\src17__data_o$next[3:0]$11636 + assign $4\cr_pred7__data_o$next[3:0]$11806 $3\cr_pred7__data_o$next[3:0]$11805 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11638 \reg + assign $5\cr_pred7__data_o$next[3:0]$11807 \reg case - assign $5\src17__data_o$next[3:0]$11638 $4\src17__data_o$next[3:0]$11637 + assign $5\cr_pred7__data_o$next[3:0]$11807 $4\cr_pred7__data_o$next[3:0]$11806 end case - assign $1\src17__data_o$next[3:0]$11634 4'0000 + assign $1\cr_pred7__data_o$next[3:0]$11803 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11639 4'0000 + assign $6\cr_pred7__data_o$next[3:0]$11808 4'0000 case - assign $6\src17__data_o$next[3:0]$11639 $1\src17__data_o$next[3:0]$11634 + assign $6\cr_pred7__data_o$next[3:0]$11808 $1\cr_pred7__data_o$next[3:0]$11803 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11633 + update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 end - attribute \src "libresoc.v:181013.3-181042.6" - process $proc$libresoc.v:181013$11640 + attribute \src "libresoc.v:183247.3-183276.6" + process $proc$libresoc.v:183247$11809 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181014.5-181014.29" + attribute \src "libresoc.v:183248.5-183248.29" switch \initial - attribute \src "libresoc.v:181014.9-181014.17" + attribute \src "libresoc.v:183248.9-183248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \cr_pred7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -373577,17 +377460,142 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181043.3-181069.6" - process $proc$libresoc.v:181043$11641 + attribute \src "libresoc.v:183277.3-183316.6" + process $proc$libresoc.v:183277$11810 assign { } { } assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183278.5-183278.29" + switch \initial + attribute \src "libresoc.v:183278.9-183278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$11812 $5\r27__data_o$next[3:0]$11816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$11813 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$11813 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$11814 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$11814 $2\r27__data_o$next[3:0]$11813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$11815 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$11815 $3\r27__data_o$next[3:0]$11814 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$11816 \reg + case + assign $5\r27__data_o$next[3:0]$11816 $4\r27__data_o$next[3:0]$11815 + end + case + assign $1\r27__data_o$next[3:0]$11812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$11817 4'0000 + case + assign $6\r27__data_o$next[3:0]$11817 $1\r27__data_o$next[3:0]$11812 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 + end + attribute \src "libresoc.v:183317.3-183346.6" + process $proc$libresoc.v:183317$11818 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183318.5-183318.29" + switch \initial + attribute \src "libresoc.v:183318.9-183318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11820 $4\wr_detect$16[0:0]$11823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11821 1'1 + case + assign $2\wr_detect$16[0:0]$11821 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11822 1'1 + case + assign $3\wr_detect$16[0:0]$11822 $2\wr_detect$16[0:0]$11821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11823 1'1 + case + assign $4\wr_detect$16[0:0]$11823 $3\wr_detect$16[0:0]$11822 + end + case + assign $1\wr_detect$16[0:0]$11820 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11819 + end + attribute \src "libresoc.v:183347.3-183373.6" + process $proc$libresoc.v:183347$11824 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11642 $4\reg$next[3:0]$11646 - attribute \src "libresoc.v:181044.5-181044.29" + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183348.5-183348.29" switch \initial - attribute \src "libresoc.v:181044.9-181044.17" + attribute \src "libresoc.v:183348.9-183348.17" case 1'1 case end @@ -373596,577 +377604,578 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11643 \dest17__data_i + assign $1\reg$next[3:0]$11826 \dest17__data_i case - assign $1\reg$next[3:0]$11643 \reg + assign $1\reg$next[3:0]$11826 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11644 \dest27__data_i + assign $2\reg$next[3:0]$11827 \dest27__data_i case - assign $2\reg$next[3:0]$11644 $1\reg$next[3:0]$11643 + assign $2\reg$next[3:0]$11827 $1\reg$next[3:0]$11826 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11645 \w7__data_i + assign $3\reg$next[3:0]$11828 \w7__data_i case - assign $3\reg$next[3:0]$11645 $2\reg$next[3:0]$11644 + assign $3\reg$next[3:0]$11828 $2\reg$next[3:0]$11827 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11646 4'0000 + assign $4\reg$next[3:0]$11829 4'0000 case - assign $4\reg$next[3:0]$11646 $3\reg$next[3:0]$11645 + assign $4\reg$next[3:0]$11829 $3\reg$next[3:0]$11828 end sync always - update \reg$next $0\reg$next[3:0]$11642 + update \reg$next $0\reg$next[3:0]$11825 end - attribute \src "libresoc.v:181070.3-181109.6" - process $proc$libresoc.v:181070$11647 + attribute \src "libresoc.v:183374.3-183413.6" + process $proc$libresoc.v:183374$11830 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11648 $6\src27__data_o$next[3:0]$11654 - attribute \src "libresoc.v:181071.5-181071.29" + assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183375.5-183375.29" switch \initial - attribute \src "libresoc.v:181071.9-181071.17" + attribute \src "libresoc.v:183375.9-183375.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11649 $5\src27__data_o$next[3:0]$11653 + assign $1\src17__data_o$next[3:0]$11832 $5\src17__data_o$next[3:0]$11836 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11650 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11833 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11650 4'0000 + assign $2\src17__data_o$next[3:0]$11833 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11651 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11834 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11651 $2\src27__data_o$next[3:0]$11650 + assign $3\src17__data_o$next[3:0]$11834 $2\src17__data_o$next[3:0]$11833 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11652 \w7__data_i + assign $4\src17__data_o$next[3:0]$11835 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11652 $3\src27__data_o$next[3:0]$11651 + assign $4\src17__data_o$next[3:0]$11835 $3\src17__data_o$next[3:0]$11834 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11653 \reg + assign $5\src17__data_o$next[3:0]$11836 \reg case - assign $5\src27__data_o$next[3:0]$11653 $4\src27__data_o$next[3:0]$11652 + assign $5\src17__data_o$next[3:0]$11836 $4\src17__data_o$next[3:0]$11835 end case - assign $1\src27__data_o$next[3:0]$11649 4'0000 + assign $1\src17__data_o$next[3:0]$11832 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11654 4'0000 + assign $6\src17__data_o$next[3:0]$11837 4'0000 case - assign $6\src27__data_o$next[3:0]$11654 $1\src27__data_o$next[3:0]$11649 + assign $6\src17__data_o$next[3:0]$11837 $1\src17__data_o$next[3:0]$11832 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11648 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 end - attribute \src "libresoc.v:181110.3-181139.6" - process $proc$libresoc.v:181110$11655 + attribute \src "libresoc.v:183414.3-183443.6" + process $proc$libresoc.v:183414$11838 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11656 $1\wr_detect$4[0:0]$11657 - attribute \src "libresoc.v:181111.5-181111.29" + assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183415.5-183415.29" switch \initial - attribute \src "libresoc.v:181111.9-181111.17" + attribute \src "libresoc.v:183415.9-183415.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11657 $4\wr_detect$4[0:0]$11660 + assign $1\wr_detect$4[0:0]$11840 $4\wr_detect$4[0:0]$11843 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11658 1'1 + assign $2\wr_detect$4[0:0]$11841 1'1 case - assign $2\wr_detect$4[0:0]$11658 1'0 + assign $2\wr_detect$4[0:0]$11841 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11659 1'1 + assign $3\wr_detect$4[0:0]$11842 1'1 case - assign $3\wr_detect$4[0:0]$11659 $2\wr_detect$4[0:0]$11658 + assign $3\wr_detect$4[0:0]$11842 $2\wr_detect$4[0:0]$11841 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11660 1'1 + assign $4\wr_detect$4[0:0]$11843 1'1 case - assign $4\wr_detect$4[0:0]$11660 $3\wr_detect$4[0:0]$11659 + assign $4\wr_detect$4[0:0]$11843 $3\wr_detect$4[0:0]$11842 end case - assign $1\wr_detect$4[0:0]$11657 1'0 + assign $1\wr_detect$4[0:0]$11840 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11656 + update \wr_detect$4 $0\wr_detect$4[0:0]$11839 end - attribute \src "libresoc.v:181140.3-181179.6" - process $proc$libresoc.v:181140$11661 + attribute \src "libresoc.v:183444.3-183483.6" + process $proc$libresoc.v:183444$11844 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11662 $6\src37__data_o$next[3:0]$11668 - attribute \src "libresoc.v:181141.5-181141.29" + assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183445.5-183445.29" switch \initial - attribute \src "libresoc.v:181141.9-181141.17" + attribute \src "libresoc.v:183445.9-183445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11663 $5\src37__data_o$next[3:0]$11667 + assign $1\src27__data_o$next[3:0]$11846 $5\src27__data_o$next[3:0]$11850 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11664 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11847 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11664 4'0000 + assign $2\src27__data_o$next[3:0]$11847 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11665 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11848 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11665 $2\src37__data_o$next[3:0]$11664 + assign $3\src27__data_o$next[3:0]$11848 $2\src27__data_o$next[3:0]$11847 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11666 \w7__data_i + assign $4\src27__data_o$next[3:0]$11849 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11666 $3\src37__data_o$next[3:0]$11665 + assign $4\src27__data_o$next[3:0]$11849 $3\src27__data_o$next[3:0]$11848 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11667 \reg + assign $5\src27__data_o$next[3:0]$11850 \reg case - assign $5\src37__data_o$next[3:0]$11667 $4\src37__data_o$next[3:0]$11666 + assign $5\src27__data_o$next[3:0]$11850 $4\src27__data_o$next[3:0]$11849 end case - assign $1\src37__data_o$next[3:0]$11663 4'0000 + assign $1\src27__data_o$next[3:0]$11846 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11668 4'0000 + assign $6\src27__data_o$next[3:0]$11851 4'0000 case - assign $6\src37__data_o$next[3:0]$11668 $1\src37__data_o$next[3:0]$11663 + assign $6\src27__data_o$next[3:0]$11851 $1\src27__data_o$next[3:0]$11846 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11662 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 end - attribute \src "libresoc.v:181180.3-181209.6" - process $proc$libresoc.v:181180$11669 + attribute \src "libresoc.v:183484.3-183513.6" + process $proc$libresoc.v:183484$11852 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11670 $1\wr_detect$7[0:0]$11671 - attribute \src "libresoc.v:181181.5-181181.29" + assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183485.5-183485.29" switch \initial - attribute \src "libresoc.v:181181.9-181181.17" + attribute \src "libresoc.v:183485.9-183485.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11671 $4\wr_detect$7[0:0]$11674 + assign $1\wr_detect$7[0:0]$11854 $4\wr_detect$7[0:0]$11857 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11672 1'1 + assign $2\wr_detect$7[0:0]$11855 1'1 case - assign $2\wr_detect$7[0:0]$11672 1'0 + assign $2\wr_detect$7[0:0]$11855 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11673 1'1 + assign $3\wr_detect$7[0:0]$11856 1'1 case - assign $3\wr_detect$7[0:0]$11673 $2\wr_detect$7[0:0]$11672 + assign $3\wr_detect$7[0:0]$11856 $2\wr_detect$7[0:0]$11855 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11674 1'1 + assign $4\wr_detect$7[0:0]$11857 1'1 case - assign $4\wr_detect$7[0:0]$11674 $3\wr_detect$7[0:0]$11673 + assign $4\wr_detect$7[0:0]$11857 $3\wr_detect$7[0:0]$11856 end case - assign $1\wr_detect$7[0:0]$11671 1'0 + assign $1\wr_detect$7[0:0]$11854 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11670 + update \wr_detect$7 $0\wr_detect$7[0:0]$11853 end - attribute \src "libresoc.v:181210.3-181249.6" - process $proc$libresoc.v:181210$11675 + attribute \src "libresoc.v:183514.3-183553.6" + process $proc$libresoc.v:183514$11858 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11676 $6\r7__data_o$next[3:0]$11682 - attribute \src "libresoc.v:181211.5-181211.29" + assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183515.5-183515.29" switch \initial - attribute \src "libresoc.v:181211.9-181211.17" + attribute \src "libresoc.v:183515.9-183515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11677 $5\r7__data_o$next[3:0]$11681 + assign $1\src37__data_o$next[3:0]$11860 $5\src37__data_o$next[3:0]$11864 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11678 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11861 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11678 4'0000 + assign $2\src37__data_o$next[3:0]$11861 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11679 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11862 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11679 $2\r7__data_o$next[3:0]$11678 + assign $3\src37__data_o$next[3:0]$11862 $2\src37__data_o$next[3:0]$11861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11680 \w7__data_i + assign $4\src37__data_o$next[3:0]$11863 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11680 $3\r7__data_o$next[3:0]$11679 + assign $4\src37__data_o$next[3:0]$11863 $3\src37__data_o$next[3:0]$11862 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11681 \reg + assign $5\src37__data_o$next[3:0]$11864 \reg case - assign $5\r7__data_o$next[3:0]$11681 $4\r7__data_o$next[3:0]$11680 + assign $5\src37__data_o$next[3:0]$11864 $4\src37__data_o$next[3:0]$11863 end case - assign $1\r7__data_o$next[3:0]$11677 4'0000 + assign $1\src37__data_o$next[3:0]$11860 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11682 4'0000 + assign $6\src37__data_o$next[3:0]$11865 4'0000 case - assign $6\r7__data_o$next[3:0]$11682 $1\r7__data_o$next[3:0]$11677 + assign $6\src37__data_o$next[3:0]$11865 $1\src37__data_o$next[3:0]$11860 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11676 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 end - attribute \src "libresoc.v:181250.3-181279.6" - process $proc$libresoc.v:181250$11683 + attribute \src "libresoc.v:183554.3-183583.6" + process $proc$libresoc.v:183554$11866 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11684 $1\wr_detect$10[0:0]$11685 - attribute \src "libresoc.v:181251.5-181251.29" + assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183555.5-183555.29" switch \initial - attribute \src "libresoc.v:181251.9-181251.17" + attribute \src "libresoc.v:183555.9-183555.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11685 $4\wr_detect$10[0:0]$11688 + assign $1\wr_detect$10[0:0]$11868 $4\wr_detect$10[0:0]$11871 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11686 1'1 + assign $2\wr_detect$10[0:0]$11869 1'1 case - assign $2\wr_detect$10[0:0]$11686 1'0 + assign $2\wr_detect$10[0:0]$11869 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11687 1'1 + assign $3\wr_detect$10[0:0]$11870 1'1 case - assign $3\wr_detect$10[0:0]$11687 $2\wr_detect$10[0:0]$11686 + assign $3\wr_detect$10[0:0]$11870 $2\wr_detect$10[0:0]$11869 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11688 1'1 + assign $4\wr_detect$10[0:0]$11871 1'1 case - assign $4\wr_detect$10[0:0]$11688 $3\wr_detect$10[0:0]$11687 + assign $4\wr_detect$10[0:0]$11871 $3\wr_detect$10[0:0]$11870 end case - assign $1\wr_detect$10[0:0]$11685 1'0 + assign $1\wr_detect$10[0:0]$11868 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11684 + update \wr_detect$10 $0\wr_detect$10[0:0]$11867 end - attribute \src "libresoc.v:181280.3-181319.6" - process $proc$libresoc.v:181280$11689 + attribute \src "libresoc.v:183584.3-183623.6" + process $proc$libresoc.v:183584$11872 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11690 $6\r27__data_o$next[3:0]$11696 - attribute \src "libresoc.v:181281.5-181281.29" + assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183585.5-183585.29" switch \initial - attribute \src "libresoc.v:181281.9-181281.17" + attribute \src "libresoc.v:183585.9-183585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11691 $5\r27__data_o$next[3:0]$11695 + assign $1\r7__data_o$next[3:0]$11874 $5\r7__data_o$next[3:0]$11878 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11692 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11875 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11692 4'0000 + assign $2\r7__data_o$next[3:0]$11875 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11693 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11876 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11693 $2\r27__data_o$next[3:0]$11692 + assign $3\r7__data_o$next[3:0]$11876 $2\r7__data_o$next[3:0]$11875 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11694 \w7__data_i + assign $4\r7__data_o$next[3:0]$11877 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11694 $3\r27__data_o$next[3:0]$11693 + assign $4\r7__data_o$next[3:0]$11877 $3\r7__data_o$next[3:0]$11876 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11695 \reg + assign $5\r7__data_o$next[3:0]$11878 \reg case - assign $5\r27__data_o$next[3:0]$11695 $4\r27__data_o$next[3:0]$11694 + assign $5\r7__data_o$next[3:0]$11878 $4\r7__data_o$next[3:0]$11877 end case - assign $1\r27__data_o$next[3:0]$11691 4'0000 + assign $1\r7__data_o$next[3:0]$11874 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11696 4'0000 + assign $6\r7__data_o$next[3:0]$11879 4'0000 case - assign $6\r27__data_o$next[3:0]$11696 $1\r27__data_o$next[3:0]$11691 + assign $6\r7__data_o$next[3:0]$11879 $1\r7__data_o$next[3:0]$11874 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11690 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 end - attribute \src "libresoc.v:181320.3-181349.6" - process $proc$libresoc.v:181320$11697 + attribute \src "libresoc.v:183624.3-183653.6" + process $proc$libresoc.v:183624$11880 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11698 $1\wr_detect$13[0:0]$11699 - attribute \src "libresoc.v:181321.5-181321.29" + assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183625.5-183625.29" switch \initial - attribute \src "libresoc.v:181321.9-181321.17" + attribute \src "libresoc.v:183625.9-183625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11699 $4\wr_detect$13[0:0]$11702 + assign $1\wr_detect$13[0:0]$11882 $4\wr_detect$13[0:0]$11885 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11700 1'1 + assign $2\wr_detect$13[0:0]$11883 1'1 case - assign $2\wr_detect$13[0:0]$11700 1'0 + assign $2\wr_detect$13[0:0]$11883 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11701 1'1 + assign $3\wr_detect$13[0:0]$11884 1'1 case - assign $3\wr_detect$13[0:0]$11701 $2\wr_detect$13[0:0]$11700 + assign $3\wr_detect$13[0:0]$11884 $2\wr_detect$13[0:0]$11883 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11702 1'1 + assign $4\wr_detect$13[0:0]$11885 1'1 case - assign $4\wr_detect$13[0:0]$11702 $3\wr_detect$13[0:0]$11701 + assign $4\wr_detect$13[0:0]$11885 $3\wr_detect$13[0:0]$11884 end case - assign $1\wr_detect$13[0:0]$11699 1'0 + assign $1\wr_detect$13[0:0]$11882 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11698 + update \wr_detect$13 $0\wr_detect$13[0:0]$11881 end - connect \$9 $not$libresoc.v:180956$11621_Y - connect \$12 $not$libresoc.v:180957$11622_Y - connect \$1 $not$libresoc.v:180958$11623_Y - connect \$3 $not$libresoc.v:180959$11624_Y - connect \$6 $not$libresoc.v:180960$11625_Y + connect \$9 $not$libresoc.v:183187$11788_Y + connect \$12 $not$libresoc.v:183188$11789_Y + connect \$15 $not$libresoc.v:183189$11790_Y + connect \$1 $not$libresoc.v:183190$11791_Y + connect \$3 $not$libresoc.v:183191$11792_Y + connect \$6 $not$libresoc.v:183192$11793_Y end -attribute \src "libresoc.v:181354.1-181412.10" +attribute \src "libresoc.v:183658.1-183716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:181355.7-181355.20" + attribute \src "libresoc.v:183659.7-183659.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181400.3-181408.6" - wire width 5 $0\q_int$next[4:0]$11720 - attribute \src "libresoc.v:181398.3-181399.27" + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $0\q_int$next[4:0]$11904 + attribute \src "libresoc.v:183702.3-183703.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:181400.3-181408.6" - wire width 5 $1\q_int$next[4:0]$11721 - attribute \src "libresoc.v:181377.13-181377.26" + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183681.13-183681.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:181390.17-181390.96" - wire width 5 $and$libresoc.v:181390$11710_Y - attribute \src "libresoc.v:181395.17-181395.96" - wire width 5 $and$libresoc.v:181395$11715_Y - attribute \src "libresoc.v:181392.18-181392.93" - wire width 5 $not$libresoc.v:181392$11712_Y - attribute \src "libresoc.v:181394.17-181394.92" - wire width 5 $not$libresoc.v:181394$11714_Y - attribute \src "libresoc.v:181397.17-181397.92" - wire width 5 $not$libresoc.v:181397$11717_Y - attribute \src "libresoc.v:181391.18-181391.98" - wire width 5 $or$libresoc.v:181391$11711_Y - attribute \src "libresoc.v:181393.18-181393.99" - wire width 5 $or$libresoc.v:181393$11713_Y - attribute \src "libresoc.v:181396.17-181396.97" - wire width 5 $or$libresoc.v:181396$11716_Y + attribute \src "libresoc.v:183694.17-183694.96" + wire width 5 $and$libresoc.v:183694$11894_Y + attribute \src "libresoc.v:183699.17-183699.96" + wire width 5 $and$libresoc.v:183699$11899_Y + attribute \src "libresoc.v:183696.18-183696.93" + wire width 5 $not$libresoc.v:183696$11896_Y + attribute \src "libresoc.v:183698.17-183698.92" + wire width 5 $not$libresoc.v:183698$11898_Y + attribute \src "libresoc.v:183701.17-183701.92" + wire width 5 $not$libresoc.v:183701$11901_Y + attribute \src "libresoc.v:183695.18-183695.98" + wire width 5 $or$libresoc.v:183695$11895_Y + attribute \src "libresoc.v:183697.18-183697.99" + wire width 5 $or$libresoc.v:183697$11897_Y + attribute \src "libresoc.v:183700.17-183700.97" + wire width 5 $or$libresoc.v:183700$11900_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374183,11 +378192,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181355.7-181355.15" + attribute \src "libresoc.v:183659.7-183659.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -374204,7 +378213,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181390$11710 + cell $and $and$libresoc.v:183694$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374212,10 +378221,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181390$11710_Y + connect \Y $and$libresoc.v:183694$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181395$11715 + cell $and $and$libresoc.v:183699$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374223,34 +378232,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181395$11715_Y + connect \Y $and$libresoc.v:183699$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181392$11712 + cell $not $not$libresoc.v:183696$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:181392$11712_Y + connect \Y $not$libresoc.v:183696$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181394$11714 + cell $not $not$libresoc.v:183698$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181394$11714_Y + connect \Y $not$libresoc.v:183698$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181397$11717 + cell $not $not$libresoc.v:183701$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181397$11717_Y + connect \Y $not$libresoc.v:183701$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181391$11711 + cell $or $or$libresoc.v:183695$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374258,10 +378267,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181391$11711_Y + connect \Y $or$libresoc.v:183695$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181393$11713 + cell $or $or$libresoc.v:183697$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374269,10 +378278,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181393$11713_Y + connect \Y $or$libresoc.v:183697$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181396$11716 + cell $or $or$libresoc.v:183700$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374280,39 +378289,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181396$11716_Y + connect \Y $or$libresoc.v:183700$11900_Y end - attribute \src "libresoc.v:181355.7-181355.20" - process $proc$libresoc.v:181355$11722 + attribute \src "libresoc.v:183659.7-183659.20" + process $proc$libresoc.v:183659$11906 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181377.13-181377.26" - process $proc$libresoc.v:181377$11723 + attribute \src "libresoc.v:183681.13-183681.26" + process $proc$libresoc.v:183681$11907 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:181398.3-181399.27" - process $proc$libresoc.v:181398$11718 + attribute \src "libresoc.v:183702.3-183703.27" + process $proc$libresoc.v:183702$11902 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:181400.3-181408.6" - process $proc$libresoc.v:181400$11719 + attribute \src "libresoc.v:183704.3-183712.6" + process $proc$libresoc.v:183704$11903 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11720 $1\q_int$next[4:0]$11721 - attribute \src "libresoc.v:181401.5-181401.29" + assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183705.5-183705.29" switch \initial - attribute \src "libresoc.v:181401.9-181401.17" + attribute \src "libresoc.v:183705.9-183705.17" case 1'1 case end @@ -374321,56 +378330,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11721 5'00000 + assign $1\q_int$next[4:0]$11905 5'00000 case - assign $1\q_int$next[4:0]$11721 \$5 + assign $1\q_int$next[4:0]$11905 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11720 + update \q_int$next $0\q_int$next[4:0]$11904 end - connect \$9 $and$libresoc.v:181390$11710_Y - connect \$11 $or$libresoc.v:181391$11711_Y - connect \$13 $not$libresoc.v:181392$11712_Y - connect \$15 $or$libresoc.v:181393$11713_Y - connect \$1 $not$libresoc.v:181394$11714_Y - connect \$3 $and$libresoc.v:181395$11715_Y - connect \$5 $or$libresoc.v:181396$11716_Y - connect \$7 $not$libresoc.v:181397$11717_Y + connect \$9 $and$libresoc.v:183694$11894_Y + connect \$11 $or$libresoc.v:183695$11895_Y + connect \$13 $not$libresoc.v:183696$11896_Y + connect \$15 $or$libresoc.v:183697$11897_Y + connect \$1 $not$libresoc.v:183698$11898_Y + connect \$3 $and$libresoc.v:183699$11899_Y + connect \$5 $or$libresoc.v:183700$11900_Y + connect \$7 $not$libresoc.v:183701$11901_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181416.1-181474.10" +attribute \src "libresoc.v:183720.1-183778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:181417.7-181417.20" + attribute \src "libresoc.v:183721.7-183721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181462.3-181470.6" - wire width 4 $0\q_int$next[3:0]$11734 - attribute \src "libresoc.v:181460.3-181461.27" + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $0\q_int$next[3:0]$11918 + attribute \src "libresoc.v:183764.3-183765.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181462.3-181470.6" - wire width 4 $1\q_int$next[3:0]$11735 - attribute \src "libresoc.v:181439.13-181439.25" + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183743.13-183743.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181452.17-181452.96" - wire width 4 $and$libresoc.v:181452$11724_Y - attribute \src "libresoc.v:181457.17-181457.96" - wire width 4 $and$libresoc.v:181457$11729_Y - attribute \src "libresoc.v:181454.18-181454.93" - wire width 4 $not$libresoc.v:181454$11726_Y - attribute \src "libresoc.v:181456.17-181456.92" - wire width 4 $not$libresoc.v:181456$11728_Y - attribute \src "libresoc.v:181459.17-181459.92" - wire width 4 $not$libresoc.v:181459$11731_Y - attribute \src "libresoc.v:181453.18-181453.98" - wire width 4 $or$libresoc.v:181453$11725_Y - attribute \src "libresoc.v:181455.18-181455.99" - wire width 4 $or$libresoc.v:181455$11727_Y - attribute \src "libresoc.v:181458.17-181458.97" - wire width 4 $or$libresoc.v:181458$11730_Y + attribute \src "libresoc.v:183756.17-183756.96" + wire width 4 $and$libresoc.v:183756$11908_Y + attribute \src "libresoc.v:183761.17-183761.96" + wire width 4 $and$libresoc.v:183761$11913_Y + attribute \src "libresoc.v:183758.18-183758.93" + wire width 4 $not$libresoc.v:183758$11910_Y + attribute \src "libresoc.v:183760.17-183760.92" + wire width 4 $not$libresoc.v:183760$11912_Y + attribute \src "libresoc.v:183763.17-183763.92" + wire width 4 $not$libresoc.v:183763$11915_Y + attribute \src "libresoc.v:183757.18-183757.98" + wire width 4 $or$libresoc.v:183757$11909_Y + attribute \src "libresoc.v:183759.18-183759.99" + wire width 4 $or$libresoc.v:183759$11911_Y + attribute \src "libresoc.v:183762.17-183762.97" + wire width 4 $or$libresoc.v:183762$11914_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374387,11 +378396,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181417.7-181417.15" + attribute \src "libresoc.v:183721.7-183721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -374408,7 +378417,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181452$11724 + cell $and $and$libresoc.v:183756$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374416,10 +378425,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181452$11724_Y + connect \Y $and$libresoc.v:183756$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181457$11729 + cell $and $and$libresoc.v:183761$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374427,34 +378436,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181457$11729_Y + connect \Y $and$libresoc.v:183761$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181454$11726 + cell $not $not$libresoc.v:183758$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:181454$11726_Y + connect \Y $not$libresoc.v:183758$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181456$11728 + cell $not $not$libresoc.v:183760$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181456$11728_Y + connect \Y $not$libresoc.v:183760$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181459$11731 + cell $not $not$libresoc.v:183763$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181459$11731_Y + connect \Y $not$libresoc.v:183763$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181453$11725 + cell $or $or$libresoc.v:183757$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374462,10 +378471,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181453$11725_Y + connect \Y $or$libresoc.v:183757$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181455$11727 + cell $or $or$libresoc.v:183759$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374473,10 +378482,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181455$11727_Y + connect \Y $or$libresoc.v:183759$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181458$11730 + cell $or $or$libresoc.v:183762$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374484,39 +378493,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181458$11730_Y + connect \Y $or$libresoc.v:183762$11914_Y end - attribute \src "libresoc.v:181417.7-181417.20" - process $proc$libresoc.v:181417$11736 + attribute \src "libresoc.v:183721.7-183721.20" + process $proc$libresoc.v:183721$11920 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181439.13-181439.25" - process $proc$libresoc.v:181439$11737 + attribute \src "libresoc.v:183743.13-183743.25" + process $proc$libresoc.v:183743$11921 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:181460.3-181461.27" - process $proc$libresoc.v:181460$11732 + attribute \src "libresoc.v:183764.3-183765.27" + process $proc$libresoc.v:183764$11916 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:181462.3-181470.6" - process $proc$libresoc.v:181462$11733 + attribute \src "libresoc.v:183766.3-183774.6" + process $proc$libresoc.v:183766$11917 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11734 $1\q_int$next[3:0]$11735 - attribute \src "libresoc.v:181463.5-181463.29" + assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183767.5-183767.29" switch \initial - attribute \src "libresoc.v:181463.9-181463.17" + attribute \src "libresoc.v:183767.9-183767.17" case 1'1 case end @@ -374525,56 +378534,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11735 4'0000 + assign $1\q_int$next[3:0]$11919 4'0000 case - assign $1\q_int$next[3:0]$11735 \$5 + assign $1\q_int$next[3:0]$11919 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11734 + update \q_int$next $0\q_int$next[3:0]$11918 end - connect \$9 $and$libresoc.v:181452$11724_Y - connect \$11 $or$libresoc.v:181453$11725_Y - connect \$13 $not$libresoc.v:181454$11726_Y - connect \$15 $or$libresoc.v:181455$11727_Y - connect \$1 $not$libresoc.v:181456$11728_Y - connect \$3 $and$libresoc.v:181457$11729_Y - connect \$5 $or$libresoc.v:181458$11730_Y - connect \$7 $not$libresoc.v:181459$11731_Y + connect \$9 $and$libresoc.v:183756$11908_Y + connect \$11 $or$libresoc.v:183757$11909_Y + connect \$13 $not$libresoc.v:183758$11910_Y + connect \$15 $or$libresoc.v:183759$11911_Y + connect \$1 $not$libresoc.v:183760$11912_Y + connect \$3 $and$libresoc.v:183761$11913_Y + connect \$5 $or$libresoc.v:183762$11914_Y + connect \$7 $not$libresoc.v:183763$11915_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181478.1-181536.10" +attribute \src "libresoc.v:183782.1-183840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:181479.7-181479.20" + attribute \src "libresoc.v:183783.7-183783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181524.3-181532.6" - wire width 3 $0\q_int$next[2:0]$11748 - attribute \src "libresoc.v:181522.3-181523.27" + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $0\q_int$next[2:0]$11932 + attribute \src "libresoc.v:183826.3-183827.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181524.3-181532.6" - wire width 3 $1\q_int$next[2:0]$11749 - attribute \src "libresoc.v:181501.13-181501.25" + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183805.13-183805.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181514.17-181514.96" - wire width 3 $and$libresoc.v:181514$11738_Y - attribute \src "libresoc.v:181519.17-181519.96" - wire width 3 $and$libresoc.v:181519$11743_Y - attribute \src "libresoc.v:181516.18-181516.93" - wire width 3 $not$libresoc.v:181516$11740_Y - attribute \src "libresoc.v:181518.17-181518.92" - wire width 3 $not$libresoc.v:181518$11742_Y - attribute \src "libresoc.v:181521.17-181521.92" - wire width 3 $not$libresoc.v:181521$11745_Y - attribute \src "libresoc.v:181515.18-181515.98" - wire width 3 $or$libresoc.v:181515$11739_Y - attribute \src "libresoc.v:181517.18-181517.99" - wire width 3 $or$libresoc.v:181517$11741_Y - attribute \src "libresoc.v:181520.17-181520.97" - wire width 3 $or$libresoc.v:181520$11744_Y + attribute \src "libresoc.v:183818.17-183818.96" + wire width 3 $and$libresoc.v:183818$11922_Y + attribute \src "libresoc.v:183823.17-183823.96" + wire width 3 $and$libresoc.v:183823$11927_Y + attribute \src "libresoc.v:183820.18-183820.93" + wire width 3 $not$libresoc.v:183820$11924_Y + attribute \src "libresoc.v:183822.17-183822.92" + wire width 3 $not$libresoc.v:183822$11926_Y + attribute \src "libresoc.v:183825.17-183825.92" + wire width 3 $not$libresoc.v:183825$11929_Y + attribute \src "libresoc.v:183819.18-183819.98" + wire width 3 $or$libresoc.v:183819$11923_Y + attribute \src "libresoc.v:183821.18-183821.99" + wire width 3 $or$libresoc.v:183821$11925_Y + attribute \src "libresoc.v:183824.17-183824.97" + wire width 3 $or$libresoc.v:183824$11928_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374591,11 +378600,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181479.7-181479.15" + attribute \src "libresoc.v:183783.7-183783.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -374612,7 +378621,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181514$11738 + cell $and $and$libresoc.v:183818$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374620,10 +378629,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181514$11738_Y + connect \Y $and$libresoc.v:183818$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181519$11743 + cell $and $and$libresoc.v:183823$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374631,34 +378640,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181519$11743_Y + connect \Y $and$libresoc.v:183823$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181516$11740 + cell $not $not$libresoc.v:183820$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181516$11740_Y + connect \Y $not$libresoc.v:183820$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181518$11742 + cell $not $not$libresoc.v:183822$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181518$11742_Y + connect \Y $not$libresoc.v:183822$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181521$11745 + cell $not $not$libresoc.v:183825$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181521$11745_Y + connect \Y $not$libresoc.v:183825$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181515$11739 + cell $or $or$libresoc.v:183819$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374666,10 +378675,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181515$11739_Y + connect \Y $or$libresoc.v:183819$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181517$11741 + cell $or $or$libresoc.v:183821$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374677,10 +378686,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181517$11741_Y + connect \Y $or$libresoc.v:183821$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181520$11744 + cell $or $or$libresoc.v:183824$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374688,39 +378697,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181520$11744_Y + connect \Y $or$libresoc.v:183824$11928_Y end - attribute \src "libresoc.v:181479.7-181479.20" - process $proc$libresoc.v:181479$11750 + attribute \src "libresoc.v:183783.7-183783.20" + process $proc$libresoc.v:183783$11934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181501.13-181501.25" - process $proc$libresoc.v:181501$11751 + attribute \src "libresoc.v:183805.13-183805.25" + process $proc$libresoc.v:183805$11935 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181522.3-181523.27" - process $proc$libresoc.v:181522$11746 + attribute \src "libresoc.v:183826.3-183827.27" + process $proc$libresoc.v:183826$11930 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181524.3-181532.6" - process $proc$libresoc.v:181524$11747 + attribute \src "libresoc.v:183828.3-183836.6" + process $proc$libresoc.v:183828$11931 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11748 $1\q_int$next[2:0]$11749 - attribute \src "libresoc.v:181525.5-181525.29" + assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183829.5-183829.29" switch \initial - attribute \src "libresoc.v:181525.9-181525.17" + attribute \src "libresoc.v:183829.9-183829.17" case 1'1 case end @@ -374729,56 +378738,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11749 3'000 + assign $1\q_int$next[2:0]$11933 3'000 case - assign $1\q_int$next[2:0]$11749 \$5 + assign $1\q_int$next[2:0]$11933 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11748 + update \q_int$next $0\q_int$next[2:0]$11932 end - connect \$9 $and$libresoc.v:181514$11738_Y - connect \$11 $or$libresoc.v:181515$11739_Y - connect \$13 $not$libresoc.v:181516$11740_Y - connect \$15 $or$libresoc.v:181517$11741_Y - connect \$1 $not$libresoc.v:181518$11742_Y - connect \$3 $and$libresoc.v:181519$11743_Y - connect \$5 $or$libresoc.v:181520$11744_Y - connect \$7 $not$libresoc.v:181521$11745_Y + connect \$9 $and$libresoc.v:183818$11922_Y + connect \$11 $or$libresoc.v:183819$11923_Y + connect \$13 $not$libresoc.v:183820$11924_Y + connect \$15 $or$libresoc.v:183821$11925_Y + connect \$1 $not$libresoc.v:183822$11926_Y + connect \$3 $and$libresoc.v:183823$11927_Y + connect \$5 $or$libresoc.v:183824$11928_Y + connect \$7 $not$libresoc.v:183825$11929_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181540.1-181598.10" +attribute \src "libresoc.v:183844.1-183902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:181541.7-181541.20" + attribute \src "libresoc.v:183845.7-183845.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181586.3-181594.6" - wire width 3 $0\q_int$next[2:0]$11762 - attribute \src "libresoc.v:181584.3-181585.27" + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $0\q_int$next[2:0]$11946 + attribute \src "libresoc.v:183888.3-183889.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181586.3-181594.6" - wire width 3 $1\q_int$next[2:0]$11763 - attribute \src "libresoc.v:181563.13-181563.25" + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183867.13-183867.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181576.17-181576.96" - wire width 3 $and$libresoc.v:181576$11752_Y - attribute \src "libresoc.v:181581.17-181581.96" - wire width 3 $and$libresoc.v:181581$11757_Y - attribute \src "libresoc.v:181578.18-181578.93" - wire width 3 $not$libresoc.v:181578$11754_Y - attribute \src "libresoc.v:181580.17-181580.92" - wire width 3 $not$libresoc.v:181580$11756_Y - attribute \src "libresoc.v:181583.17-181583.92" - wire width 3 $not$libresoc.v:181583$11759_Y - attribute \src "libresoc.v:181577.18-181577.98" - wire width 3 $or$libresoc.v:181577$11753_Y - attribute \src "libresoc.v:181579.18-181579.99" - wire width 3 $or$libresoc.v:181579$11755_Y - attribute \src "libresoc.v:181582.17-181582.97" - wire width 3 $or$libresoc.v:181582$11758_Y + attribute \src "libresoc.v:183880.17-183880.96" + wire width 3 $and$libresoc.v:183880$11936_Y + attribute \src "libresoc.v:183885.17-183885.96" + wire width 3 $and$libresoc.v:183885$11941_Y + attribute \src "libresoc.v:183882.18-183882.93" + wire width 3 $not$libresoc.v:183882$11938_Y + attribute \src "libresoc.v:183884.17-183884.92" + wire width 3 $not$libresoc.v:183884$11940_Y + attribute \src "libresoc.v:183887.17-183887.92" + wire width 3 $not$libresoc.v:183887$11943_Y + attribute \src "libresoc.v:183881.18-183881.98" + wire width 3 $or$libresoc.v:183881$11937_Y + attribute \src "libresoc.v:183883.18-183883.99" + wire width 3 $or$libresoc.v:183883$11939_Y + attribute \src "libresoc.v:183886.17-183886.97" + wire width 3 $or$libresoc.v:183886$11942_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374795,11 +378804,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181541.7-181541.15" + attribute \src "libresoc.v:183845.7-183845.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -374816,7 +378825,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181576$11752 + cell $and $and$libresoc.v:183880$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374824,10 +378833,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181576$11752_Y + connect \Y $and$libresoc.v:183880$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181581$11757 + cell $and $and$libresoc.v:183885$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374835,34 +378844,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181581$11757_Y + connect \Y $and$libresoc.v:183885$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181578$11754 + cell $not $not$libresoc.v:183882$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181578$11754_Y + connect \Y $not$libresoc.v:183882$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181580$11756 + cell $not $not$libresoc.v:183884$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181580$11756_Y + connect \Y $not$libresoc.v:183884$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181583$11759 + cell $not $not$libresoc.v:183887$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181583$11759_Y + connect \Y $not$libresoc.v:183887$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181577$11753 + cell $or $or$libresoc.v:183881$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374870,10 +378879,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181577$11753_Y + connect \Y $or$libresoc.v:183881$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181579$11755 + cell $or $or$libresoc.v:183883$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374881,10 +378890,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181579$11755_Y + connect \Y $or$libresoc.v:183883$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181582$11758 + cell $or $or$libresoc.v:183886$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374892,39 +378901,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181582$11758_Y + connect \Y $or$libresoc.v:183886$11942_Y end - attribute \src "libresoc.v:181541.7-181541.20" - process $proc$libresoc.v:181541$11764 + attribute \src "libresoc.v:183845.7-183845.20" + process $proc$libresoc.v:183845$11948 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181563.13-181563.25" - process $proc$libresoc.v:181563$11765 + attribute \src "libresoc.v:183867.13-183867.25" + process $proc$libresoc.v:183867$11949 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181584.3-181585.27" - process $proc$libresoc.v:181584$11760 + attribute \src "libresoc.v:183888.3-183889.27" + process $proc$libresoc.v:183888$11944 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181586.3-181594.6" - process $proc$libresoc.v:181586$11761 + attribute \src "libresoc.v:183890.3-183898.6" + process $proc$libresoc.v:183890$11945 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11762 $1\q_int$next[2:0]$11763 - attribute \src "libresoc.v:181587.5-181587.29" + assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183891.5-183891.29" switch \initial - attribute \src "libresoc.v:181587.9-181587.17" + attribute \src "libresoc.v:183891.9-183891.17" case 1'1 case end @@ -374933,56 +378942,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11763 3'000 + assign $1\q_int$next[2:0]$11947 3'000 case - assign $1\q_int$next[2:0]$11763 \$5 + assign $1\q_int$next[2:0]$11947 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11762 + update \q_int$next $0\q_int$next[2:0]$11946 end - connect \$9 $and$libresoc.v:181576$11752_Y - connect \$11 $or$libresoc.v:181577$11753_Y - connect \$13 $not$libresoc.v:181578$11754_Y - connect \$15 $or$libresoc.v:181579$11755_Y - connect \$1 $not$libresoc.v:181580$11756_Y - connect \$3 $and$libresoc.v:181581$11757_Y - connect \$5 $or$libresoc.v:181582$11758_Y - connect \$7 $not$libresoc.v:181583$11759_Y + connect \$9 $and$libresoc.v:183880$11936_Y + connect \$11 $or$libresoc.v:183881$11937_Y + connect \$13 $not$libresoc.v:183882$11938_Y + connect \$15 $or$libresoc.v:183883$11939_Y + connect \$1 $not$libresoc.v:183884$11940_Y + connect \$3 $and$libresoc.v:183885$11941_Y + connect \$5 $or$libresoc.v:183886$11942_Y + connect \$7 $not$libresoc.v:183887$11943_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181602.1-181660.10" +attribute \src "libresoc.v:183906.1-183964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:181603.7-181603.20" + attribute \src "libresoc.v:183907.7-183907.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181648.3-181656.6" - wire width 3 $0\q_int$next[2:0]$11776 - attribute \src "libresoc.v:181646.3-181647.27" + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $0\q_int$next[2:0]$11960 + attribute \src "libresoc.v:183950.3-183951.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181648.3-181656.6" - wire width 3 $1\q_int$next[2:0]$11777 - attribute \src "libresoc.v:181625.13-181625.25" + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $1\q_int$next[2:0]$11961 + attribute \src "libresoc.v:183929.13-183929.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181638.17-181638.96" - wire width 3 $and$libresoc.v:181638$11766_Y - attribute \src "libresoc.v:181643.17-181643.96" - wire width 3 $and$libresoc.v:181643$11771_Y - attribute \src "libresoc.v:181640.18-181640.93" - wire width 3 $not$libresoc.v:181640$11768_Y - attribute \src "libresoc.v:181642.17-181642.92" - wire width 3 $not$libresoc.v:181642$11770_Y - attribute \src "libresoc.v:181645.17-181645.92" - wire width 3 $not$libresoc.v:181645$11773_Y - attribute \src "libresoc.v:181639.18-181639.98" - wire width 3 $or$libresoc.v:181639$11767_Y - attribute \src "libresoc.v:181641.18-181641.99" - wire width 3 $or$libresoc.v:181641$11769_Y - attribute \src "libresoc.v:181644.17-181644.97" - wire width 3 $or$libresoc.v:181644$11772_Y + attribute \src "libresoc.v:183942.17-183942.96" + wire width 3 $and$libresoc.v:183942$11950_Y + attribute \src "libresoc.v:183947.17-183947.96" + wire width 3 $and$libresoc.v:183947$11955_Y + attribute \src "libresoc.v:183944.18-183944.93" + wire width 3 $not$libresoc.v:183944$11952_Y + attribute \src "libresoc.v:183946.17-183946.92" + wire width 3 $not$libresoc.v:183946$11954_Y + attribute \src "libresoc.v:183949.17-183949.92" + wire width 3 $not$libresoc.v:183949$11957_Y + attribute \src "libresoc.v:183943.18-183943.98" + wire width 3 $or$libresoc.v:183943$11951_Y + attribute \src "libresoc.v:183945.18-183945.99" + wire width 3 $or$libresoc.v:183945$11953_Y + attribute \src "libresoc.v:183948.17-183948.97" + wire width 3 $or$libresoc.v:183948$11956_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374999,11 +379008,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181603.7-181603.15" + attribute \src "libresoc.v:183907.7-183907.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -375020,7 +379029,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181638$11766 + cell $and $and$libresoc.v:183942$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375028,10 +379037,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181638$11766_Y + connect \Y $and$libresoc.v:183942$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181643$11771 + cell $and $and$libresoc.v:183947$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375039,34 +379048,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181643$11771_Y + connect \Y $and$libresoc.v:183947$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181640$11768 + cell $not $not$libresoc.v:183944$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181640$11768_Y + connect \Y $not$libresoc.v:183944$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181642$11770 + cell $not $not$libresoc.v:183946$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181642$11770_Y + connect \Y $not$libresoc.v:183946$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181645$11773 + cell $not $not$libresoc.v:183949$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181645$11773_Y + connect \Y $not$libresoc.v:183949$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181639$11767 + cell $or $or$libresoc.v:183943$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375074,10 +379083,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181639$11767_Y + connect \Y $or$libresoc.v:183943$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181641$11769 + cell $or $or$libresoc.v:183945$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375085,10 +379094,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181641$11769_Y + connect \Y $or$libresoc.v:183945$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181644$11772 + cell $or $or$libresoc.v:183948$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375096,39 +379105,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181644$11772_Y + connect \Y $or$libresoc.v:183948$11956_Y end - attribute \src "libresoc.v:181603.7-181603.20" - process $proc$libresoc.v:181603$11778 + attribute \src "libresoc.v:183907.7-183907.20" + process $proc$libresoc.v:183907$11962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181625.13-181625.25" - process $proc$libresoc.v:181625$11779 + attribute \src "libresoc.v:183929.13-183929.25" + process $proc$libresoc.v:183929$11963 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181646.3-181647.27" - process $proc$libresoc.v:181646$11774 + attribute \src "libresoc.v:183950.3-183951.27" + process $proc$libresoc.v:183950$11958 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181648.3-181656.6" - process $proc$libresoc.v:181648$11775 + attribute \src "libresoc.v:183952.3-183960.6" + process $proc$libresoc.v:183952$11959 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11776 $1\q_int$next[2:0]$11777 - attribute \src "libresoc.v:181649.5-181649.29" + assign $0\q_int$next[2:0]$11960 $1\q_int$next[2:0]$11961 + attribute \src "libresoc.v:183953.5-183953.29" switch \initial - attribute \src "libresoc.v:181649.9-181649.17" + attribute \src "libresoc.v:183953.9-183953.17" case 1'1 case end @@ -375137,56 +379146,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11777 3'000 + assign $1\q_int$next[2:0]$11961 3'000 case - assign $1\q_int$next[2:0]$11777 \$5 + assign $1\q_int$next[2:0]$11961 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11776 + update \q_int$next $0\q_int$next[2:0]$11960 end - connect \$9 $and$libresoc.v:181638$11766_Y - connect \$11 $or$libresoc.v:181639$11767_Y - connect \$13 $not$libresoc.v:181640$11768_Y - connect \$15 $or$libresoc.v:181641$11769_Y - connect \$1 $not$libresoc.v:181642$11770_Y - connect \$3 $and$libresoc.v:181643$11771_Y - connect \$5 $or$libresoc.v:181644$11772_Y - connect \$7 $not$libresoc.v:181645$11773_Y + connect \$9 $and$libresoc.v:183942$11950_Y + connect \$11 $or$libresoc.v:183943$11951_Y + connect \$13 $not$libresoc.v:183944$11952_Y + connect \$15 $or$libresoc.v:183945$11953_Y + connect \$1 $not$libresoc.v:183946$11954_Y + connect \$3 $and$libresoc.v:183947$11955_Y + connect \$5 $or$libresoc.v:183948$11956_Y + connect \$7 $not$libresoc.v:183949$11957_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181664.1-181722.10" +attribute \src "libresoc.v:183968.1-184026.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:181665.7-181665.20" + attribute \src "libresoc.v:183969.7-183969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181710.3-181718.6" - wire width 5 $0\q_int$next[4:0]$11790 - attribute \src "libresoc.v:181708.3-181709.27" + attribute \src "libresoc.v:184014.3-184022.6" + wire width 5 $0\q_int$next[4:0]$11974 + attribute \src "libresoc.v:184012.3-184013.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:181710.3-181718.6" - wire width 5 $1\q_int$next[4:0]$11791 - attribute \src "libresoc.v:181687.13-181687.26" + attribute \src "libresoc.v:184014.3-184022.6" + wire width 5 $1\q_int$next[4:0]$11975 + attribute \src "libresoc.v:183991.13-183991.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:181700.17-181700.96" - wire width 5 $and$libresoc.v:181700$11780_Y - attribute \src "libresoc.v:181705.17-181705.96" - wire width 5 $and$libresoc.v:181705$11785_Y - attribute \src "libresoc.v:181702.18-181702.93" - wire width 5 $not$libresoc.v:181702$11782_Y - attribute \src "libresoc.v:181704.17-181704.92" - wire width 5 $not$libresoc.v:181704$11784_Y - attribute \src "libresoc.v:181707.17-181707.92" - wire width 5 $not$libresoc.v:181707$11787_Y - attribute \src "libresoc.v:181701.18-181701.98" - wire width 5 $or$libresoc.v:181701$11781_Y - attribute \src "libresoc.v:181703.18-181703.99" - wire width 5 $or$libresoc.v:181703$11783_Y - attribute \src "libresoc.v:181706.17-181706.97" - wire width 5 $or$libresoc.v:181706$11786_Y + attribute \src "libresoc.v:184004.17-184004.96" + wire width 5 $and$libresoc.v:184004$11964_Y + attribute \src "libresoc.v:184009.17-184009.96" + wire width 5 $and$libresoc.v:184009$11969_Y + attribute \src "libresoc.v:184006.18-184006.93" + wire width 5 $not$libresoc.v:184006$11966_Y + attribute \src "libresoc.v:184008.17-184008.92" + wire width 5 $not$libresoc.v:184008$11968_Y + attribute \src "libresoc.v:184011.17-184011.92" + wire width 5 $not$libresoc.v:184011$11971_Y + attribute \src "libresoc.v:184005.18-184005.98" + wire width 5 $or$libresoc.v:184005$11965_Y + attribute \src "libresoc.v:184007.18-184007.99" + wire width 5 $or$libresoc.v:184007$11967_Y + attribute \src "libresoc.v:184010.17-184010.97" + wire width 5 $or$libresoc.v:184010$11970_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375203,11 +379212,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181665.7-181665.15" + attribute \src "libresoc.v:183969.7-183969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -375224,7 +379233,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181700$11780 + cell $and $and$libresoc.v:184004$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375232,10 +379241,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181700$11780_Y + connect \Y $and$libresoc.v:184004$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181705$11785 + cell $and $and$libresoc.v:184009$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375243,34 +379252,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181705$11785_Y + connect \Y $and$libresoc.v:184009$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181702$11782 + cell $not $not$libresoc.v:184006$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:181702$11782_Y + connect \Y $not$libresoc.v:184006$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181704$11784 + cell $not $not$libresoc.v:184008$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181704$11784_Y + connect \Y $not$libresoc.v:184008$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181707$11787 + cell $not $not$libresoc.v:184011$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181707$11787_Y + connect \Y $not$libresoc.v:184011$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181701$11781 + cell $or $or$libresoc.v:184005$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375278,10 +379287,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181701$11781_Y + connect \Y $or$libresoc.v:184005$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181703$11783 + cell $or $or$libresoc.v:184007$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375289,10 +379298,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181703$11783_Y + connect \Y $or$libresoc.v:184007$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181706$11786 + cell $or $or$libresoc.v:184010$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375300,39 +379309,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181706$11786_Y + connect \Y $or$libresoc.v:184010$11970_Y end - attribute \src "libresoc.v:181665.7-181665.20" - process $proc$libresoc.v:181665$11792 + attribute \src "libresoc.v:183969.7-183969.20" + process $proc$libresoc.v:183969$11976 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181687.13-181687.26" - process $proc$libresoc.v:181687$11793 + attribute \src "libresoc.v:183991.13-183991.26" + process $proc$libresoc.v:183991$11977 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:181708.3-181709.27" - process $proc$libresoc.v:181708$11788 + attribute \src "libresoc.v:184012.3-184013.27" + process $proc$libresoc.v:184012$11972 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:181710.3-181718.6" - process $proc$libresoc.v:181710$11789 + attribute \src "libresoc.v:184014.3-184022.6" + process $proc$libresoc.v:184014$11973 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11790 $1\q_int$next[4:0]$11791 - attribute \src "libresoc.v:181711.5-181711.29" + assign $0\q_int$next[4:0]$11974 $1\q_int$next[4:0]$11975 + attribute \src "libresoc.v:184015.5-184015.29" switch \initial - attribute \src "libresoc.v:181711.9-181711.17" + attribute \src "libresoc.v:184015.9-184015.17" case 1'1 case end @@ -375341,56 +379350,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11791 5'00000 + assign $1\q_int$next[4:0]$11975 5'00000 case - assign $1\q_int$next[4:0]$11791 \$5 + assign $1\q_int$next[4:0]$11975 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11790 + update \q_int$next $0\q_int$next[4:0]$11974 end - connect \$9 $and$libresoc.v:181700$11780_Y - connect \$11 $or$libresoc.v:181701$11781_Y - connect \$13 $not$libresoc.v:181702$11782_Y - connect \$15 $or$libresoc.v:181703$11783_Y - connect \$1 $not$libresoc.v:181704$11784_Y - connect \$3 $and$libresoc.v:181705$11785_Y - connect \$5 $or$libresoc.v:181706$11786_Y - connect \$7 $not$libresoc.v:181707$11787_Y + connect \$9 $and$libresoc.v:184004$11964_Y + connect \$11 $or$libresoc.v:184005$11965_Y + connect \$13 $not$libresoc.v:184006$11966_Y + connect \$15 $or$libresoc.v:184007$11967_Y + connect \$1 $not$libresoc.v:184008$11968_Y + connect \$3 $and$libresoc.v:184009$11969_Y + connect \$5 $or$libresoc.v:184010$11970_Y + connect \$7 $not$libresoc.v:184011$11971_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181726.1-181784.10" +attribute \src "libresoc.v:184030.1-184088.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:181727.7-181727.20" + attribute \src "libresoc.v:184031.7-184031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181772.3-181780.6" - wire width 2 $0\q_int$next[1:0]$11804 - attribute \src "libresoc.v:181770.3-181771.27" + attribute \src "libresoc.v:184076.3-184084.6" + wire width 2 $0\q_int$next[1:0]$11988 + attribute \src "libresoc.v:184074.3-184075.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:181772.3-181780.6" - wire width 2 $1\q_int$next[1:0]$11805 - attribute \src "libresoc.v:181749.13-181749.25" + attribute \src "libresoc.v:184076.3-184084.6" + wire width 2 $1\q_int$next[1:0]$11989 + attribute \src "libresoc.v:184053.13-184053.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:181762.17-181762.96" - wire width 2 $and$libresoc.v:181762$11794_Y - attribute \src "libresoc.v:181767.17-181767.96" - wire width 2 $and$libresoc.v:181767$11799_Y - attribute \src "libresoc.v:181764.18-181764.93" - wire width 2 $not$libresoc.v:181764$11796_Y - attribute \src "libresoc.v:181766.17-181766.92" - wire width 2 $not$libresoc.v:181766$11798_Y - attribute \src "libresoc.v:181769.17-181769.92" - wire width 2 $not$libresoc.v:181769$11801_Y - attribute \src "libresoc.v:181763.18-181763.98" - wire width 2 $or$libresoc.v:181763$11795_Y - attribute \src "libresoc.v:181765.18-181765.99" - wire width 2 $or$libresoc.v:181765$11797_Y - attribute \src "libresoc.v:181768.17-181768.97" - wire width 2 $or$libresoc.v:181768$11800_Y + attribute \src "libresoc.v:184066.17-184066.96" + wire width 2 $and$libresoc.v:184066$11978_Y + attribute \src "libresoc.v:184071.17-184071.96" + wire width 2 $and$libresoc.v:184071$11983_Y + attribute \src "libresoc.v:184068.18-184068.93" + wire width 2 $not$libresoc.v:184068$11980_Y + attribute \src "libresoc.v:184070.17-184070.92" + wire width 2 $not$libresoc.v:184070$11982_Y + attribute \src "libresoc.v:184073.17-184073.92" + wire width 2 $not$libresoc.v:184073$11985_Y + attribute \src "libresoc.v:184067.18-184067.98" + wire width 2 $or$libresoc.v:184067$11979_Y + attribute \src "libresoc.v:184069.18-184069.99" + wire width 2 $or$libresoc.v:184069$11981_Y + attribute \src "libresoc.v:184072.17-184072.97" + wire width 2 $or$libresoc.v:184072$11984_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375407,11 +379416,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181727.7-181727.15" + attribute \src "libresoc.v:184031.7-184031.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -375428,7 +379437,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181762$11794 + cell $and $and$libresoc.v:184066$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375436,10 +379445,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181762$11794_Y + connect \Y $and$libresoc.v:184066$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181767$11799 + cell $and $and$libresoc.v:184071$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375447,34 +379456,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181767$11799_Y + connect \Y $and$libresoc.v:184071$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181764$11796 + cell $not $not$libresoc.v:184068$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:181764$11796_Y + connect \Y $not$libresoc.v:184068$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181766$11798 + cell $not $not$libresoc.v:184070$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:181766$11798_Y + connect \Y $not$libresoc.v:184070$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181769$11801 + cell $not $not$libresoc.v:184073$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:181769$11801_Y + connect \Y $not$libresoc.v:184073$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181763$11795 + cell $or $or$libresoc.v:184067$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375482,10 +379491,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181763$11795_Y + connect \Y $or$libresoc.v:184067$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181765$11797 + cell $or $or$libresoc.v:184069$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375493,10 +379502,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181765$11797_Y + connect \Y $or$libresoc.v:184069$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181768$11800 + cell $or $or$libresoc.v:184072$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375504,39 +379513,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181768$11800_Y + connect \Y $or$libresoc.v:184072$11984_Y end - attribute \src "libresoc.v:181727.7-181727.20" - process $proc$libresoc.v:181727$11806 + attribute \src "libresoc.v:184031.7-184031.20" + process $proc$libresoc.v:184031$11990 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181749.13-181749.25" - process $proc$libresoc.v:181749$11807 + attribute \src "libresoc.v:184053.13-184053.25" + process $proc$libresoc.v:184053$11991 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:181770.3-181771.27" - process $proc$libresoc.v:181770$11802 + attribute \src "libresoc.v:184074.3-184075.27" + process $proc$libresoc.v:184074$11986 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:181772.3-181780.6" - process $proc$libresoc.v:181772$11803 + attribute \src "libresoc.v:184076.3-184084.6" + process $proc$libresoc.v:184076$11987 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11804 $1\q_int$next[1:0]$11805 - attribute \src "libresoc.v:181773.5-181773.29" + assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 + attribute \src "libresoc.v:184077.5-184077.29" switch \initial - attribute \src "libresoc.v:181773.9-181773.17" + attribute \src "libresoc.v:184077.9-184077.17" case 1'1 case end @@ -375545,56 +379554,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11805 2'00 + assign $1\q_int$next[1:0]$11989 2'00 case - assign $1\q_int$next[1:0]$11805 \$5 + assign $1\q_int$next[1:0]$11989 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11804 + update \q_int$next $0\q_int$next[1:0]$11988 end - connect \$9 $and$libresoc.v:181762$11794_Y - connect \$11 $or$libresoc.v:181763$11795_Y - connect \$13 $not$libresoc.v:181764$11796_Y - connect \$15 $or$libresoc.v:181765$11797_Y - connect \$1 $not$libresoc.v:181766$11798_Y - connect \$3 $and$libresoc.v:181767$11799_Y - connect \$5 $or$libresoc.v:181768$11800_Y - connect \$7 $not$libresoc.v:181769$11801_Y + connect \$9 $and$libresoc.v:184066$11978_Y + connect \$11 $or$libresoc.v:184067$11979_Y + connect \$13 $not$libresoc.v:184068$11980_Y + connect \$15 $or$libresoc.v:184069$11981_Y + connect \$1 $not$libresoc.v:184070$11982_Y + connect \$3 $and$libresoc.v:184071$11983_Y + connect \$5 $or$libresoc.v:184072$11984_Y + connect \$7 $not$libresoc.v:184073$11985_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181788.1-181846.10" +attribute \src "libresoc.v:184092.1-184150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:181789.7-181789.20" + attribute \src "libresoc.v:184093.7-184093.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181834.3-181842.6" - wire width 6 $0\q_int$next[5:0]$11818 - attribute \src "libresoc.v:181832.3-181833.27" + attribute \src "libresoc.v:184138.3-184146.6" + wire width 6 $0\q_int$next[5:0]$12002 + attribute \src "libresoc.v:184136.3-184137.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:181834.3-181842.6" - wire width 6 $1\q_int$next[5:0]$11819 - attribute \src "libresoc.v:181811.13-181811.26" + attribute \src "libresoc.v:184138.3-184146.6" + wire width 6 $1\q_int$next[5:0]$12003 + attribute \src "libresoc.v:184115.13-184115.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:181824.17-181824.96" - wire width 6 $and$libresoc.v:181824$11808_Y - attribute \src "libresoc.v:181829.17-181829.96" - wire width 6 $and$libresoc.v:181829$11813_Y - attribute \src "libresoc.v:181826.18-181826.93" - wire width 6 $not$libresoc.v:181826$11810_Y - attribute \src "libresoc.v:181828.17-181828.92" - wire width 6 $not$libresoc.v:181828$11812_Y - attribute \src "libresoc.v:181831.17-181831.92" - wire width 6 $not$libresoc.v:181831$11815_Y - attribute \src "libresoc.v:181825.18-181825.98" - wire width 6 $or$libresoc.v:181825$11809_Y - attribute \src "libresoc.v:181827.18-181827.99" - wire width 6 $or$libresoc.v:181827$11811_Y - attribute \src "libresoc.v:181830.17-181830.97" - wire width 6 $or$libresoc.v:181830$11814_Y + attribute \src "libresoc.v:184128.17-184128.96" + wire width 6 $and$libresoc.v:184128$11992_Y + attribute \src "libresoc.v:184133.17-184133.96" + wire width 6 $and$libresoc.v:184133$11997_Y + attribute \src "libresoc.v:184130.18-184130.93" + wire width 6 $not$libresoc.v:184130$11994_Y + attribute \src "libresoc.v:184132.17-184132.92" + wire width 6 $not$libresoc.v:184132$11996_Y + attribute \src "libresoc.v:184135.17-184135.92" + wire width 6 $not$libresoc.v:184135$11999_Y + attribute \src "libresoc.v:184129.18-184129.98" + wire width 6 $or$libresoc.v:184129$11993_Y + attribute \src "libresoc.v:184131.18-184131.99" + wire width 6 $or$libresoc.v:184131$11995_Y + attribute \src "libresoc.v:184134.17-184134.97" + wire width 6 $or$libresoc.v:184134$11998_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375611,11 +379620,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181789.7-181789.15" + attribute \src "libresoc.v:184093.7-184093.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -375632,7 +379641,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181824$11808 + cell $and $and$libresoc.v:184128$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375640,10 +379649,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181824$11808_Y + connect \Y $and$libresoc.v:184128$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181829$11813 + cell $and $and$libresoc.v:184133$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375651,34 +379660,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181829$11813_Y + connect \Y $and$libresoc.v:184133$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181826$11810 + cell $not $not$libresoc.v:184130$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:181826$11810_Y + connect \Y $not$libresoc.v:184130$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181828$11812 + cell $not $not$libresoc.v:184132$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:181828$11812_Y + connect \Y $not$libresoc.v:184132$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181831$11815 + cell $not $not$libresoc.v:184135$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:181831$11815_Y + connect \Y $not$libresoc.v:184135$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181825$11809 + cell $or $or$libresoc.v:184129$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375686,10 +379695,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181825$11809_Y + connect \Y $or$libresoc.v:184129$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181827$11811 + cell $or $or$libresoc.v:184131$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375697,10 +379706,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181827$11811_Y + connect \Y $or$libresoc.v:184131$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181830$11814 + cell $or $or$libresoc.v:184134$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375708,39 +379717,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181830$11814_Y + connect \Y $or$libresoc.v:184134$11998_Y end - attribute \src "libresoc.v:181789.7-181789.20" - process $proc$libresoc.v:181789$11820 + attribute \src "libresoc.v:184093.7-184093.20" + process $proc$libresoc.v:184093$12004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181811.13-181811.26" - process $proc$libresoc.v:181811$11821 + attribute \src "libresoc.v:184115.13-184115.26" + process $proc$libresoc.v:184115$12005 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:181832.3-181833.27" - process $proc$libresoc.v:181832$11816 + attribute \src "libresoc.v:184136.3-184137.27" + process $proc$libresoc.v:184136$12000 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:181834.3-181842.6" - process $proc$libresoc.v:181834$11817 + attribute \src "libresoc.v:184138.3-184146.6" + process $proc$libresoc.v:184138$12001 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11818 $1\q_int$next[5:0]$11819 - attribute \src "libresoc.v:181835.5-181835.29" + assign $0\q_int$next[5:0]$12002 $1\q_int$next[5:0]$12003 + attribute \src "libresoc.v:184139.5-184139.29" switch \initial - attribute \src "libresoc.v:181835.9-181835.17" + attribute \src "libresoc.v:184139.9-184139.17" case 1'1 case end @@ -375749,56 +379758,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11819 6'000000 + assign $1\q_int$next[5:0]$12003 6'000000 case - assign $1\q_int$next[5:0]$11819 \$5 + assign $1\q_int$next[5:0]$12003 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11818 + update \q_int$next $0\q_int$next[5:0]$12002 end - connect \$9 $and$libresoc.v:181824$11808_Y - connect \$11 $or$libresoc.v:181825$11809_Y - connect \$13 $not$libresoc.v:181826$11810_Y - connect \$15 $or$libresoc.v:181827$11811_Y - connect \$1 $not$libresoc.v:181828$11812_Y - connect \$3 $and$libresoc.v:181829$11813_Y - connect \$5 $or$libresoc.v:181830$11814_Y - connect \$7 $not$libresoc.v:181831$11815_Y + connect \$9 $and$libresoc.v:184128$11992_Y + connect \$11 $or$libresoc.v:184129$11993_Y + connect \$13 $not$libresoc.v:184130$11994_Y + connect \$15 $or$libresoc.v:184131$11995_Y + connect \$1 $not$libresoc.v:184132$11996_Y + connect \$3 $and$libresoc.v:184133$11997_Y + connect \$5 $or$libresoc.v:184134$11998_Y + connect \$7 $not$libresoc.v:184135$11999_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181850.1-181908.10" +attribute \src "libresoc.v:184154.1-184212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:181851.7-181851.20" + attribute \src "libresoc.v:184155.7-184155.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181896.3-181904.6" - wire width 4 $0\q_int$next[3:0]$11832 - attribute \src "libresoc.v:181894.3-181895.27" + attribute \src "libresoc.v:184200.3-184208.6" + wire width 4 $0\q_int$next[3:0]$12016 + attribute \src "libresoc.v:184198.3-184199.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181896.3-181904.6" - wire width 4 $1\q_int$next[3:0]$11833 - attribute \src "libresoc.v:181873.13-181873.25" + attribute \src "libresoc.v:184200.3-184208.6" + wire width 4 $1\q_int$next[3:0]$12017 + attribute \src "libresoc.v:184177.13-184177.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181886.17-181886.96" - wire width 4 $and$libresoc.v:181886$11822_Y - attribute \src "libresoc.v:181891.17-181891.96" - wire width 4 $and$libresoc.v:181891$11827_Y - attribute \src "libresoc.v:181888.18-181888.93" - wire width 4 $not$libresoc.v:181888$11824_Y - attribute \src "libresoc.v:181890.17-181890.92" - wire width 4 $not$libresoc.v:181890$11826_Y - attribute \src "libresoc.v:181893.17-181893.92" - wire width 4 $not$libresoc.v:181893$11829_Y - attribute \src "libresoc.v:181887.18-181887.98" - wire width 4 $or$libresoc.v:181887$11823_Y - attribute \src "libresoc.v:181889.18-181889.99" - wire width 4 $or$libresoc.v:181889$11825_Y - attribute \src "libresoc.v:181892.17-181892.97" - wire width 4 $or$libresoc.v:181892$11828_Y + attribute \src "libresoc.v:184190.17-184190.96" + wire width 4 $and$libresoc.v:184190$12006_Y + attribute \src "libresoc.v:184195.17-184195.96" + wire width 4 $and$libresoc.v:184195$12011_Y + attribute \src "libresoc.v:184192.18-184192.93" + wire width 4 $not$libresoc.v:184192$12008_Y + attribute \src "libresoc.v:184194.17-184194.92" + wire width 4 $not$libresoc.v:184194$12010_Y + attribute \src "libresoc.v:184197.17-184197.92" + wire width 4 $not$libresoc.v:184197$12013_Y + attribute \src "libresoc.v:184191.18-184191.98" + wire width 4 $or$libresoc.v:184191$12007_Y + attribute \src "libresoc.v:184193.18-184193.99" + wire width 4 $or$libresoc.v:184193$12009_Y + attribute \src "libresoc.v:184196.17-184196.97" + wire width 4 $or$libresoc.v:184196$12012_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375815,11 +379824,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181851.7-181851.15" + attribute \src "libresoc.v:184155.7-184155.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -375836,7 +379845,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181886$11822 + cell $and $and$libresoc.v:184190$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375844,10 +379853,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181886$11822_Y + connect \Y $and$libresoc.v:184190$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181891$11827 + cell $and $and$libresoc.v:184195$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375855,34 +379864,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181891$11827_Y + connect \Y $and$libresoc.v:184195$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181888$11824 + cell $not $not$libresoc.v:184192$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:181888$11824_Y + connect \Y $not$libresoc.v:184192$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181890$11826 + cell $not $not$libresoc.v:184194$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181890$11826_Y + connect \Y $not$libresoc.v:184194$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181893$11829 + cell $not $not$libresoc.v:184197$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181893$11829_Y + connect \Y $not$libresoc.v:184197$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181887$11823 + cell $or $or$libresoc.v:184191$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375890,10 +379899,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181887$11823_Y + connect \Y $or$libresoc.v:184191$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181889$11825 + cell $or $or$libresoc.v:184193$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375901,10 +379910,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181889$11825_Y + connect \Y $or$libresoc.v:184193$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181892$11828 + cell $or $or$libresoc.v:184196$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375912,39 +379921,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181892$11828_Y + connect \Y $or$libresoc.v:184196$12012_Y end - attribute \src "libresoc.v:181851.7-181851.20" - process $proc$libresoc.v:181851$11834 + attribute \src "libresoc.v:184155.7-184155.20" + process $proc$libresoc.v:184155$12018 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181873.13-181873.25" - process $proc$libresoc.v:181873$11835 + attribute \src "libresoc.v:184177.13-184177.25" + process $proc$libresoc.v:184177$12019 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:181894.3-181895.27" - process $proc$libresoc.v:181894$11830 + attribute \src "libresoc.v:184198.3-184199.27" + process $proc$libresoc.v:184198$12014 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:181896.3-181904.6" - process $proc$libresoc.v:181896$11831 + attribute \src "libresoc.v:184200.3-184208.6" + process $proc$libresoc.v:184200$12015 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11832 $1\q_int$next[3:0]$11833 - attribute \src "libresoc.v:181897.5-181897.29" + assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 + attribute \src "libresoc.v:184201.5-184201.29" switch \initial - attribute \src "libresoc.v:181897.9-181897.17" + attribute \src "libresoc.v:184201.9-184201.17" case 1'1 case end @@ -375953,50 +379962,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11833 4'0000 + assign $1\q_int$next[3:0]$12017 4'0000 case - assign $1\q_int$next[3:0]$11833 \$5 + assign $1\q_int$next[3:0]$12017 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11832 + update \q_int$next $0\q_int$next[3:0]$12016 end - connect \$9 $and$libresoc.v:181886$11822_Y - connect \$11 $or$libresoc.v:181887$11823_Y - connect \$13 $not$libresoc.v:181888$11824_Y - connect \$15 $or$libresoc.v:181889$11825_Y - connect \$1 $not$libresoc.v:181890$11826_Y - connect \$3 $and$libresoc.v:181891$11827_Y - connect \$5 $or$libresoc.v:181892$11828_Y - connect \$7 $not$libresoc.v:181893$11829_Y + connect \$9 $and$libresoc.v:184190$12006_Y + connect \$11 $or$libresoc.v:184191$12007_Y + connect \$13 $not$libresoc.v:184192$12008_Y + connect \$15 $or$libresoc.v:184193$12009_Y + connect \$1 $not$libresoc.v:184194$12010_Y + connect \$3 $and$libresoc.v:184195$12011_Y + connect \$5 $or$libresoc.v:184196$12012_Y + connect \$7 $not$libresoc.v:184197$12013_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181912.1-181961.10" +attribute \src "libresoc.v:184216.1-184265.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:181913.7-181913.20" + attribute \src "libresoc.v:184217.7-184217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181949.3-181957.6" - wire $0\q_int$next[0:0]$11843 - attribute \src "libresoc.v:181947.3-181948.27" + attribute \src "libresoc.v:184253.3-184261.6" + wire $0\q_int$next[0:0]$12027 + attribute \src "libresoc.v:184251.3-184252.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181949.3-181957.6" - wire $1\q_int$next[0:0]$11844 - attribute \src "libresoc.v:181929.7-181929.19" + attribute \src "libresoc.v:184253.3-184261.6" + wire $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184233.7-184233.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181944.17-181944.96" - wire $and$libresoc.v:181944$11838_Y - attribute \src "libresoc.v:181943.17-181943.94" - wire $not$libresoc.v:181943$11837_Y - attribute \src "libresoc.v:181946.17-181946.94" - wire $not$libresoc.v:181946$11840_Y - attribute \src "libresoc.v:181942.17-181942.100" - wire $or$libresoc.v:181942$11836_Y - attribute \src "libresoc.v:181945.17-181945.99" - wire $or$libresoc.v:181945$11839_Y + attribute \src "libresoc.v:184248.17-184248.96" + wire $and$libresoc.v:184248$12022_Y + attribute \src "libresoc.v:184247.17-184247.94" + wire $not$libresoc.v:184247$12021_Y + attribute \src "libresoc.v:184250.17-184250.94" + wire $not$libresoc.v:184250$12024_Y + attribute \src "libresoc.v:184246.17-184246.100" + wire $or$libresoc.v:184246$12020_Y + attribute \src "libresoc.v:184249.17-184249.99" + wire $or$libresoc.v:184249$12023_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -376007,11 +380016,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181913.7-181913.15" + attribute \src "libresoc.v:184217.7-184217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376028,7 +380037,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181944$11838 + cell $and $and$libresoc.v:184248$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376036,26 +380045,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181944$11838_Y + connect \Y $and$libresoc.v:184248$12022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181943$11837 + cell $not $not$libresoc.v:184247$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:181943$11837_Y + connect \Y $not$libresoc.v:184247$12021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181946$11840 + cell $not $not$libresoc.v:184250$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:181946$11840_Y + connect \Y $not$libresoc.v:184250$12024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181942$11836 + cell $or $or$libresoc.v:184246$12020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376063,10 +380072,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:181942$11836_Y + connect \Y $or$libresoc.v:184246$12020_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181945$11839 + cell $or $or$libresoc.v:184249$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376074,39 +380083,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:181945$11839_Y + connect \Y $or$libresoc.v:184249$12023_Y end - attribute \src "libresoc.v:181913.7-181913.20" - process $proc$libresoc.v:181913$11845 + attribute \src "libresoc.v:184217.7-184217.20" + process $proc$libresoc.v:184217$12029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181929.7-181929.19" - process $proc$libresoc.v:181929$11846 + attribute \src "libresoc.v:184233.7-184233.19" + process $proc$libresoc.v:184233$12030 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181947.3-181948.27" - process $proc$libresoc.v:181947$11841 + attribute \src "libresoc.v:184251.3-184252.27" + process $proc$libresoc.v:184251$12025 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181949.3-181957.6" - process $proc$libresoc.v:181949$11842 + attribute \src "libresoc.v:184253.3-184261.6" + process $proc$libresoc.v:184253$12026 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11843 $1\q_int$next[0:0]$11844 - attribute \src "libresoc.v:181950.5-181950.29" + assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184254.5-184254.29" switch \initial - attribute \src "libresoc.v:181950.9-181950.17" + attribute \src "libresoc.v:184254.9-184254.17" case 1'1 case end @@ -376115,47 +380124,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11844 1'0 + assign $1\q_int$next[0:0]$12028 1'0 case - assign $1\q_int$next[0:0]$11844 \$5 + assign $1\q_int$next[0:0]$12028 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11843 + update \q_int$next $0\q_int$next[0:0]$12027 end - connect \$9 $or$libresoc.v:181942$11836_Y - connect \$1 $not$libresoc.v:181943$11837_Y - connect \$3 $and$libresoc.v:181944$11838_Y - connect \$5 $or$libresoc.v:181945$11839_Y - connect \$7 $not$libresoc.v:181946$11840_Y + connect \$9 $or$libresoc.v:184246$12020_Y + connect \$1 $not$libresoc.v:184247$12021_Y + connect \$3 $and$libresoc.v:184248$12022_Y + connect \$5 $or$libresoc.v:184249$12023_Y + connect \$7 $not$libresoc.v:184250$12024_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:181965.1-182014.10" +attribute \src "libresoc.v:184269.1-184318.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:181966.7-181966.20" + attribute \src "libresoc.v:184270.7-184270.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182002.3-182010.6" - wire $0\q_int$next[0:0]$11854 - attribute \src "libresoc.v:182000.3-182001.27" + attribute \src "libresoc.v:184306.3-184314.6" + wire $0\q_int$next[0:0]$12038 + attribute \src "libresoc.v:184304.3-184305.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182002.3-182010.6" - wire $1\q_int$next[0:0]$11855 - attribute \src "libresoc.v:181982.7-181982.19" + attribute \src "libresoc.v:184306.3-184314.6" + wire $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184286.7-184286.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181997.17-181997.96" - wire $and$libresoc.v:181997$11849_Y - attribute \src "libresoc.v:181996.17-181996.94" - wire $not$libresoc.v:181996$11848_Y - attribute \src "libresoc.v:181999.17-181999.94" - wire $not$libresoc.v:181999$11851_Y - attribute \src "libresoc.v:181995.17-181995.100" - wire $or$libresoc.v:181995$11847_Y - attribute \src "libresoc.v:181998.17-181998.99" - wire $or$libresoc.v:181998$11850_Y + attribute \src "libresoc.v:184301.17-184301.96" + wire $and$libresoc.v:184301$12033_Y + attribute \src "libresoc.v:184300.17-184300.94" + wire $not$libresoc.v:184300$12032_Y + attribute \src "libresoc.v:184303.17-184303.94" + wire $not$libresoc.v:184303$12035_Y + attribute \src "libresoc.v:184299.17-184299.100" + wire $or$libresoc.v:184299$12031_Y + attribute \src "libresoc.v:184302.17-184302.99" + wire $or$libresoc.v:184302$12034_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -376166,11 +380175,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181966.7-181966.15" + attribute \src "libresoc.v:184270.7-184270.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376187,7 +380196,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181997$11849 + cell $and $and$libresoc.v:184301$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376195,26 +380204,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181997$11849_Y + connect \Y $and$libresoc.v:184301$12033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181996$11848 + cell $not $not$libresoc.v:184300$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:181996$11848_Y + connect \Y $not$libresoc.v:184300$12032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181999$11851 + cell $not $not$libresoc.v:184303$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:181999$11851_Y + connect \Y $not$libresoc.v:184303$12035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181995$11847 + cell $or $or$libresoc.v:184299$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376222,10 +380231,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:181995$11847_Y + connect \Y $or$libresoc.v:184299$12031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181998$11850 + cell $or $or$libresoc.v:184302$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376233,39 +380242,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:181998$11850_Y + connect \Y $or$libresoc.v:184302$12034_Y end - attribute \src "libresoc.v:181966.7-181966.20" - process $proc$libresoc.v:181966$11856 + attribute \src "libresoc.v:184270.7-184270.20" + process $proc$libresoc.v:184270$12040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181982.7-181982.19" - process $proc$libresoc.v:181982$11857 + attribute \src "libresoc.v:184286.7-184286.19" + process $proc$libresoc.v:184286$12041 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182000.3-182001.27" - process $proc$libresoc.v:182000$11852 + attribute \src "libresoc.v:184304.3-184305.27" + process $proc$libresoc.v:184304$12036 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182002.3-182010.6" - process $proc$libresoc.v:182002$11853 + attribute \src "libresoc.v:184306.3-184314.6" + process $proc$libresoc.v:184306$12037 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11854 $1\q_int$next[0:0]$11855 - attribute \src "libresoc.v:182003.5-182003.29" + assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184307.5-184307.29" switch \initial - attribute \src "libresoc.v:182003.9-182003.17" + attribute \src "libresoc.v:184307.9-184307.17" case 1'1 case end @@ -376274,287 +380283,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11855 1'0 + assign $1\q_int$next[0:0]$12039 1'0 case - assign $1\q_int$next[0:0]$11855 \$5 + assign $1\q_int$next[0:0]$12039 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11854 + update \q_int$next $0\q_int$next[0:0]$12038 end - connect \$9 $or$libresoc.v:181995$11847_Y - connect \$1 $not$libresoc.v:181996$11848_Y - connect \$3 $and$libresoc.v:181997$11849_Y - connect \$5 $or$libresoc.v:181998$11850_Y - connect \$7 $not$libresoc.v:181999$11851_Y + connect \$9 $or$libresoc.v:184299$12031_Y + connect \$1 $not$libresoc.v:184300$12032_Y + connect \$3 $and$libresoc.v:184301$12033_Y + connect \$5 $or$libresoc.v:184302$12034_Y + connect \$7 $not$libresoc.v:184303$12035_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:182018.1-182605.10" +attribute \src "libresoc.v:184322.1-184909.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:182019.7-182019.20" + attribute \src "libresoc.v:184323.7-184323.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $10\mask[9:9] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $11\mask[10:10] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $12\mask[11:11] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $13\mask[12:12] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $14\mask[13:13] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $15\mask[14:14] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $16\mask[15:15] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $17\mask[16:16] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $18\mask[17:17] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $19\mask[18:18] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $1\mask[0:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $20\mask[19:19] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $21\mask[20:20] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $22\mask[21:21] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $23\mask[22:22] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $24\mask[23:23] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $25\mask[24:24] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $26\mask[25:25] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $27\mask[26:26] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $28\mask[27:27] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $29\mask[28:28] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $2\mask[1:1] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $30\mask[29:29] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $31\mask[30:30] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $32\mask[31:31] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $33\mask[32:32] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $34\mask[33:33] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $35\mask[34:34] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $36\mask[35:35] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $37\mask[36:36] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $38\mask[37:37] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $39\mask[38:38] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $3\mask[2:2] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $40\mask[39:39] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $41\mask[40:40] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $42\mask[41:41] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $43\mask[42:42] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $44\mask[43:43] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $45\mask[44:44] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $46\mask[45:45] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $47\mask[46:46] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $48\mask[47:47] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $49\mask[48:48] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $4\mask[3:3] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $50\mask[49:49] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $51\mask[50:50] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $52\mask[51:51] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $53\mask[52:52] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $54\mask[53:53] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $55\mask[54:54] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $56\mask[55:55] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $57\mask[56:56] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $58\mask[57:57] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $59\mask[58:58] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $5\mask[4:4] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $60\mask[59:59] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $61\mask[60:60] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $62\mask[61:61] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $63\mask[62:62] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $64\mask[63:63] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $6\mask[5:5] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $7\mask[6:6] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $8\mask[7:7] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $9\mask[8:8] - attribute \src "libresoc.v:182153.17-182153.96" - wire $gt$libresoc.v:182153$11858_Y - attribute \src "libresoc.v:182154.18-182154.98" - wire $gt$libresoc.v:182154$11859_Y - attribute \src "libresoc.v:182155.19-182155.99" - wire $gt$libresoc.v:182155$11860_Y - attribute \src "libresoc.v:182156.19-182156.99" - wire $gt$libresoc.v:182156$11861_Y - attribute \src "libresoc.v:182157.19-182157.99" - wire $gt$libresoc.v:182157$11862_Y - attribute \src "libresoc.v:182158.19-182158.99" - wire $gt$libresoc.v:182158$11863_Y - attribute \src "libresoc.v:182159.19-182159.99" - wire $gt$libresoc.v:182159$11864_Y - attribute \src "libresoc.v:182160.19-182160.99" - wire $gt$libresoc.v:182160$11865_Y - attribute \src "libresoc.v:182161.19-182161.99" - wire $gt$libresoc.v:182161$11866_Y - attribute \src "libresoc.v:182162.19-182162.99" - wire $gt$libresoc.v:182162$11867_Y - attribute \src "libresoc.v:182163.19-182163.99" - wire $gt$libresoc.v:182163$11868_Y - attribute \src "libresoc.v:182164.18-182164.97" - wire $gt$libresoc.v:182164$11869_Y - attribute \src "libresoc.v:182165.19-182165.99" - wire $gt$libresoc.v:182165$11870_Y - attribute \src "libresoc.v:182166.19-182166.99" - wire $gt$libresoc.v:182166$11871_Y - attribute \src "libresoc.v:182167.19-182167.99" - wire $gt$libresoc.v:182167$11872_Y - attribute \src "libresoc.v:182168.19-182168.99" - wire $gt$libresoc.v:182168$11873_Y - attribute \src "libresoc.v:182169.19-182169.99" - wire $gt$libresoc.v:182169$11874_Y - attribute \src "libresoc.v:182170.18-182170.97" - wire $gt$libresoc.v:182170$11875_Y - attribute \src "libresoc.v:182171.18-182171.97" - wire $gt$libresoc.v:182171$11876_Y - attribute \src "libresoc.v:182172.18-182172.97" - wire $gt$libresoc.v:182172$11877_Y - attribute \src "libresoc.v:182173.17-182173.96" - wire $gt$libresoc.v:182173$11878_Y - attribute \src "libresoc.v:182174.18-182174.97" - wire $gt$libresoc.v:182174$11879_Y - attribute \src "libresoc.v:182175.18-182175.97" - wire $gt$libresoc.v:182175$11880_Y - attribute \src "libresoc.v:182176.18-182176.97" - wire $gt$libresoc.v:182176$11881_Y - attribute \src "libresoc.v:182177.18-182177.97" - wire $gt$libresoc.v:182177$11882_Y - attribute \src "libresoc.v:182178.18-182178.97" - wire $gt$libresoc.v:182178$11883_Y - attribute \src "libresoc.v:182179.18-182179.97" - wire $gt$libresoc.v:182179$11884_Y - attribute \src "libresoc.v:182180.18-182180.97" - wire $gt$libresoc.v:182180$11885_Y - attribute \src "libresoc.v:182181.18-182181.98" - wire $gt$libresoc.v:182181$11886_Y - attribute \src "libresoc.v:182182.18-182182.98" - wire $gt$libresoc.v:182182$11887_Y - attribute \src "libresoc.v:182183.18-182183.98" - wire $gt$libresoc.v:182183$11888_Y - attribute \src "libresoc.v:182184.17-182184.96" - wire $gt$libresoc.v:182184$11889_Y - attribute \src "libresoc.v:182185.18-182185.98" - wire $gt$libresoc.v:182185$11890_Y - attribute \src "libresoc.v:182186.18-182186.98" - wire $gt$libresoc.v:182186$11891_Y - attribute \src "libresoc.v:182187.18-182187.98" - wire $gt$libresoc.v:182187$11892_Y - attribute \src "libresoc.v:182188.18-182188.98" - wire $gt$libresoc.v:182188$11893_Y - attribute \src "libresoc.v:182189.18-182189.98" - wire $gt$libresoc.v:182189$11894_Y - attribute \src "libresoc.v:182190.18-182190.98" - wire $gt$libresoc.v:182190$11895_Y - attribute \src "libresoc.v:182191.18-182191.98" - wire $gt$libresoc.v:182191$11896_Y - attribute \src "libresoc.v:182192.18-182192.98" - wire $gt$libresoc.v:182192$11897_Y - attribute \src "libresoc.v:182193.18-182193.98" - wire $gt$libresoc.v:182193$11898_Y - attribute \src "libresoc.v:182194.18-182194.98" - wire $gt$libresoc.v:182194$11899_Y - attribute \src "libresoc.v:182195.17-182195.96" - wire $gt$libresoc.v:182195$11900_Y - attribute \src "libresoc.v:182196.18-182196.98" - wire $gt$libresoc.v:182196$11901_Y - attribute \src "libresoc.v:182197.18-182197.98" - wire $gt$libresoc.v:182197$11902_Y - attribute \src "libresoc.v:182198.18-182198.98" - wire $gt$libresoc.v:182198$11903_Y - attribute \src "libresoc.v:182199.18-182199.98" - wire $gt$libresoc.v:182199$11904_Y - attribute \src "libresoc.v:182200.18-182200.98" - wire $gt$libresoc.v:182200$11905_Y - attribute \src "libresoc.v:182201.18-182201.98" - wire $gt$libresoc.v:182201$11906_Y - attribute \src "libresoc.v:182202.18-182202.98" - wire $gt$libresoc.v:182202$11907_Y - attribute \src "libresoc.v:182203.18-182203.98" - wire $gt$libresoc.v:182203$11908_Y - attribute \src "libresoc.v:182204.18-182204.98" - wire $gt$libresoc.v:182204$11909_Y - attribute \src "libresoc.v:182205.18-182205.98" - wire $gt$libresoc.v:182205$11910_Y - attribute \src "libresoc.v:182206.17-182206.96" - wire $gt$libresoc.v:182206$11911_Y - attribute \src "libresoc.v:182207.18-182207.98" - wire $gt$libresoc.v:182207$11912_Y - attribute \src "libresoc.v:182208.18-182208.98" - wire $gt$libresoc.v:182208$11913_Y - attribute \src "libresoc.v:182209.18-182209.98" - wire $gt$libresoc.v:182209$11914_Y - attribute \src "libresoc.v:182210.18-182210.98" - wire $gt$libresoc.v:182210$11915_Y - attribute \src "libresoc.v:182211.18-182211.98" - wire $gt$libresoc.v:182211$11916_Y - attribute \src "libresoc.v:182212.18-182212.98" - wire $gt$libresoc.v:182212$11917_Y - attribute \src "libresoc.v:182213.18-182213.98" - wire $gt$libresoc.v:182213$11918_Y - attribute \src "libresoc.v:182214.18-182214.98" - wire $gt$libresoc.v:182214$11919_Y - attribute \src "libresoc.v:182215.18-182215.98" - wire $gt$libresoc.v:182215$11920_Y - attribute \src "libresoc.v:182216.18-182216.98" - wire $gt$libresoc.v:182216$11921_Y + attribute \src "libresoc.v:184457.17-184457.96" + wire $gt$libresoc.v:184457$12042_Y + attribute \src "libresoc.v:184458.18-184458.98" + wire $gt$libresoc.v:184458$12043_Y + attribute \src "libresoc.v:184459.19-184459.99" + wire $gt$libresoc.v:184459$12044_Y + attribute \src "libresoc.v:184460.19-184460.99" + wire $gt$libresoc.v:184460$12045_Y + attribute \src "libresoc.v:184461.19-184461.99" + wire $gt$libresoc.v:184461$12046_Y + attribute \src "libresoc.v:184462.19-184462.99" + wire $gt$libresoc.v:184462$12047_Y + attribute \src "libresoc.v:184463.19-184463.99" + wire $gt$libresoc.v:184463$12048_Y + attribute \src "libresoc.v:184464.19-184464.99" + wire $gt$libresoc.v:184464$12049_Y + attribute \src "libresoc.v:184465.19-184465.99" + wire $gt$libresoc.v:184465$12050_Y + attribute \src "libresoc.v:184466.19-184466.99" + wire $gt$libresoc.v:184466$12051_Y + attribute \src "libresoc.v:184467.19-184467.99" + wire $gt$libresoc.v:184467$12052_Y + attribute \src "libresoc.v:184468.18-184468.97" + wire $gt$libresoc.v:184468$12053_Y + attribute \src "libresoc.v:184469.19-184469.99" + wire $gt$libresoc.v:184469$12054_Y + attribute \src "libresoc.v:184470.19-184470.99" + wire $gt$libresoc.v:184470$12055_Y + attribute \src "libresoc.v:184471.19-184471.99" + wire $gt$libresoc.v:184471$12056_Y + attribute \src "libresoc.v:184472.19-184472.99" + wire $gt$libresoc.v:184472$12057_Y + attribute \src "libresoc.v:184473.19-184473.99" + wire $gt$libresoc.v:184473$12058_Y + attribute \src "libresoc.v:184474.18-184474.97" + wire $gt$libresoc.v:184474$12059_Y + attribute \src "libresoc.v:184475.18-184475.97" + wire $gt$libresoc.v:184475$12060_Y + attribute \src "libresoc.v:184476.18-184476.97" + wire $gt$libresoc.v:184476$12061_Y + attribute \src "libresoc.v:184477.17-184477.96" + wire $gt$libresoc.v:184477$12062_Y + attribute \src "libresoc.v:184478.18-184478.97" + wire $gt$libresoc.v:184478$12063_Y + attribute \src "libresoc.v:184479.18-184479.97" + wire $gt$libresoc.v:184479$12064_Y + attribute \src "libresoc.v:184480.18-184480.97" + wire $gt$libresoc.v:184480$12065_Y + attribute \src "libresoc.v:184481.18-184481.97" + wire $gt$libresoc.v:184481$12066_Y + attribute \src "libresoc.v:184482.18-184482.97" + wire $gt$libresoc.v:184482$12067_Y + attribute \src "libresoc.v:184483.18-184483.97" + wire $gt$libresoc.v:184483$12068_Y + attribute \src "libresoc.v:184484.18-184484.97" + wire $gt$libresoc.v:184484$12069_Y + attribute \src "libresoc.v:184485.18-184485.98" + wire $gt$libresoc.v:184485$12070_Y + attribute \src "libresoc.v:184486.18-184486.98" + wire $gt$libresoc.v:184486$12071_Y + attribute \src "libresoc.v:184487.18-184487.98" + wire $gt$libresoc.v:184487$12072_Y + attribute \src "libresoc.v:184488.17-184488.96" + wire $gt$libresoc.v:184488$12073_Y + attribute \src "libresoc.v:184489.18-184489.98" + wire $gt$libresoc.v:184489$12074_Y + attribute \src "libresoc.v:184490.18-184490.98" + wire $gt$libresoc.v:184490$12075_Y + attribute \src "libresoc.v:184491.18-184491.98" + wire $gt$libresoc.v:184491$12076_Y + attribute \src "libresoc.v:184492.18-184492.98" + wire $gt$libresoc.v:184492$12077_Y + attribute \src "libresoc.v:184493.18-184493.98" + wire $gt$libresoc.v:184493$12078_Y + attribute \src "libresoc.v:184494.18-184494.98" + wire $gt$libresoc.v:184494$12079_Y + attribute \src "libresoc.v:184495.18-184495.98" + wire $gt$libresoc.v:184495$12080_Y + attribute \src "libresoc.v:184496.18-184496.98" + wire $gt$libresoc.v:184496$12081_Y + attribute \src "libresoc.v:184497.18-184497.98" + wire $gt$libresoc.v:184497$12082_Y + attribute \src "libresoc.v:184498.18-184498.98" + wire $gt$libresoc.v:184498$12083_Y + attribute \src "libresoc.v:184499.17-184499.96" + wire $gt$libresoc.v:184499$12084_Y + attribute \src "libresoc.v:184500.18-184500.98" + wire $gt$libresoc.v:184500$12085_Y + attribute \src "libresoc.v:184501.18-184501.98" + wire $gt$libresoc.v:184501$12086_Y + attribute \src "libresoc.v:184502.18-184502.98" + wire $gt$libresoc.v:184502$12087_Y + attribute \src "libresoc.v:184503.18-184503.98" + wire $gt$libresoc.v:184503$12088_Y + attribute \src "libresoc.v:184504.18-184504.98" + wire $gt$libresoc.v:184504$12089_Y + attribute \src "libresoc.v:184505.18-184505.98" + wire $gt$libresoc.v:184505$12090_Y + attribute \src "libresoc.v:184506.18-184506.98" + wire $gt$libresoc.v:184506$12091_Y + attribute \src "libresoc.v:184507.18-184507.98" + wire $gt$libresoc.v:184507$12092_Y + attribute \src "libresoc.v:184508.18-184508.98" + wire $gt$libresoc.v:184508$12093_Y + attribute \src "libresoc.v:184509.18-184509.98" + wire $gt$libresoc.v:184509$12094_Y + attribute \src "libresoc.v:184510.17-184510.96" + wire $gt$libresoc.v:184510$12095_Y + attribute \src "libresoc.v:184511.18-184511.98" + wire $gt$libresoc.v:184511$12096_Y + attribute \src "libresoc.v:184512.18-184512.98" + wire $gt$libresoc.v:184512$12097_Y + attribute \src "libresoc.v:184513.18-184513.98" + wire $gt$libresoc.v:184513$12098_Y + attribute \src "libresoc.v:184514.18-184514.98" + wire $gt$libresoc.v:184514$12099_Y + attribute \src "libresoc.v:184515.18-184515.98" + wire $gt$libresoc.v:184515$12100_Y + attribute \src "libresoc.v:184516.18-184516.98" + wire $gt$libresoc.v:184516$12101_Y + attribute \src "libresoc.v:184517.18-184517.98" + wire $gt$libresoc.v:184517$12102_Y + attribute \src "libresoc.v:184518.18-184518.98" + wire $gt$libresoc.v:184518$12103_Y + attribute \src "libresoc.v:184519.18-184519.98" + wire $gt$libresoc.v:184519$12104_Y + attribute \src "libresoc.v:184520.18-184520.98" + wire $gt$libresoc.v:184520$12105_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -376683,14 +380692,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:182019.7-182019.15" + attribute \src "libresoc.v:184323.7-184323.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182153$11858 + cell $gt $gt$libresoc.v:184457$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376698,10 +380707,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:182153$11858_Y + connect \Y $gt$libresoc.v:184457$12042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182154$11859 + cell $gt $gt$libresoc.v:184458$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376709,10 +380718,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:182154$11859_Y + connect \Y $gt$libresoc.v:184458$12043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182155$11860 + cell $gt $gt$libresoc.v:184459$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376720,10 +380729,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:182155$11860_Y + connect \Y $gt$libresoc.v:184459$12044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182156$11861 + cell $gt $gt$libresoc.v:184460$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376731,10 +380740,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:182156$11861_Y + connect \Y $gt$libresoc.v:184460$12045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182157$11862 + cell $gt $gt$libresoc.v:184461$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376742,10 +380751,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:182157$11862_Y + connect \Y $gt$libresoc.v:184461$12046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182158$11863 + cell $gt $gt$libresoc.v:184462$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376753,10 +380762,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:182158$11863_Y + connect \Y $gt$libresoc.v:184462$12047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182159$11864 + cell $gt $gt$libresoc.v:184463$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376764,10 +380773,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:182159$11864_Y + connect \Y $gt$libresoc.v:184463$12048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182160$11865 + cell $gt $gt$libresoc.v:184464$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376775,10 +380784,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:182160$11865_Y + connect \Y $gt$libresoc.v:184464$12049_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182161$11866 + cell $gt $gt$libresoc.v:184465$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376786,10 +380795,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:182161$11866_Y + connect \Y $gt$libresoc.v:184465$12050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182162$11867 + cell $gt $gt$libresoc.v:184466$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376797,10 +380806,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:182162$11867_Y + connect \Y $gt$libresoc.v:184466$12051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182163$11868 + cell $gt $gt$libresoc.v:184467$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376808,10 +380817,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:182163$11868_Y + connect \Y $gt$libresoc.v:184467$12052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182164$11869 + cell $gt $gt$libresoc.v:184468$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376819,10 +380828,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:182164$11869_Y + connect \Y $gt$libresoc.v:184468$12053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182165$11870 + cell $gt $gt$libresoc.v:184469$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376830,10 +380839,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:182165$11870_Y + connect \Y $gt$libresoc.v:184469$12054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182166$11871 + cell $gt $gt$libresoc.v:184470$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376841,10 +380850,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:182166$11871_Y + connect \Y $gt$libresoc.v:184470$12055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182167$11872 + cell $gt $gt$libresoc.v:184471$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376852,10 +380861,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:182167$11872_Y + connect \Y $gt$libresoc.v:184471$12056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182168$11873 + cell $gt $gt$libresoc.v:184472$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376863,10 +380872,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:182168$11873_Y + connect \Y $gt$libresoc.v:184472$12057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182169$11874 + cell $gt $gt$libresoc.v:184473$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376874,10 +380883,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:182169$11874_Y + connect \Y $gt$libresoc.v:184473$12058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182170$11875 + cell $gt $gt$libresoc.v:184474$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376885,10 +380894,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:182170$11875_Y + connect \Y $gt$libresoc.v:184474$12059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182171$11876 + cell $gt $gt$libresoc.v:184475$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376896,10 +380905,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:182171$11876_Y + connect \Y $gt$libresoc.v:184475$12060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182172$11877 + cell $gt $gt$libresoc.v:184476$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376907,10 +380916,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:182172$11877_Y + connect \Y $gt$libresoc.v:184476$12061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182173$11878 + cell $gt $gt$libresoc.v:184477$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376918,10 +380927,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:182173$11878_Y + connect \Y $gt$libresoc.v:184477$12062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182174$11879 + cell $gt $gt$libresoc.v:184478$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376929,10 +380938,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:182174$11879_Y + connect \Y $gt$libresoc.v:184478$12063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182175$11880 + cell $gt $gt$libresoc.v:184479$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376940,10 +380949,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:182175$11880_Y + connect \Y $gt$libresoc.v:184479$12064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182176$11881 + cell $gt $gt$libresoc.v:184480$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376951,10 +380960,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:182176$11881_Y + connect \Y $gt$libresoc.v:184480$12065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182177$11882 + cell $gt $gt$libresoc.v:184481$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376962,10 +380971,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:182177$11882_Y + connect \Y $gt$libresoc.v:184481$12066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182178$11883 + cell $gt $gt$libresoc.v:184482$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376973,10 +380982,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:182178$11883_Y + connect \Y $gt$libresoc.v:184482$12067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182179$11884 + cell $gt $gt$libresoc.v:184483$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376984,10 +380993,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:182179$11884_Y + connect \Y $gt$libresoc.v:184483$12068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182180$11885 + cell $gt $gt$libresoc.v:184484$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376995,10 +381004,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:182180$11885_Y + connect \Y $gt$libresoc.v:184484$12069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182181$11886 + cell $gt $gt$libresoc.v:184485$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377006,10 +381015,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:182181$11886_Y + connect \Y $gt$libresoc.v:184485$12070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182182$11887 + cell $gt $gt$libresoc.v:184486$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377017,10 +381026,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:182182$11887_Y + connect \Y $gt$libresoc.v:184486$12071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182183$11888 + cell $gt $gt$libresoc.v:184487$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377028,10 +381037,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:182183$11888_Y + connect \Y $gt$libresoc.v:184487$12072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182184$11889 + cell $gt $gt$libresoc.v:184488$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377039,10 +381048,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:182184$11889_Y + connect \Y $gt$libresoc.v:184488$12073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182185$11890 + cell $gt $gt$libresoc.v:184489$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377050,10 +381059,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:182185$11890_Y + connect \Y $gt$libresoc.v:184489$12074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182186$11891 + cell $gt $gt$libresoc.v:184490$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377061,10 +381070,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:182186$11891_Y + connect \Y $gt$libresoc.v:184490$12075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182187$11892 + cell $gt $gt$libresoc.v:184491$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377072,10 +381081,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:182187$11892_Y + connect \Y $gt$libresoc.v:184491$12076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182188$11893 + cell $gt $gt$libresoc.v:184492$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377083,10 +381092,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:182188$11893_Y + connect \Y $gt$libresoc.v:184492$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182189$11894 + cell $gt $gt$libresoc.v:184493$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377094,10 +381103,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:182189$11894_Y + connect \Y $gt$libresoc.v:184493$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182190$11895 + cell $gt $gt$libresoc.v:184494$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377105,10 +381114,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:182190$11895_Y + connect \Y $gt$libresoc.v:184494$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182191$11896 + cell $gt $gt$libresoc.v:184495$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377116,10 +381125,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:182191$11896_Y + connect \Y $gt$libresoc.v:184495$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182192$11897 + cell $gt $gt$libresoc.v:184496$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377127,10 +381136,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:182192$11897_Y + connect \Y $gt$libresoc.v:184496$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182193$11898 + cell $gt $gt$libresoc.v:184497$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377138,10 +381147,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:182193$11898_Y + connect \Y $gt$libresoc.v:184497$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182194$11899 + cell $gt $gt$libresoc.v:184498$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377149,10 +381158,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:182194$11899_Y + connect \Y $gt$libresoc.v:184498$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182195$11900 + cell $gt $gt$libresoc.v:184499$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377160,10 +381169,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:182195$11900_Y + connect \Y $gt$libresoc.v:184499$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182196$11901 + cell $gt $gt$libresoc.v:184500$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377171,10 +381180,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:182196$11901_Y + connect \Y $gt$libresoc.v:184500$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182197$11902 + cell $gt $gt$libresoc.v:184501$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377182,10 +381191,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:182197$11902_Y + connect \Y $gt$libresoc.v:184501$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182198$11903 + cell $gt $gt$libresoc.v:184502$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377193,10 +381202,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:182198$11903_Y + connect \Y $gt$libresoc.v:184502$12087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182199$11904 + cell $gt $gt$libresoc.v:184503$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377204,10 +381213,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:182199$11904_Y + connect \Y $gt$libresoc.v:184503$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182200$11905 + cell $gt $gt$libresoc.v:184504$12089 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377215,10 +381224,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:182200$11905_Y + connect \Y $gt$libresoc.v:184504$12089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182201$11906 + cell $gt $gt$libresoc.v:184505$12090 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377226,10 +381235,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:182201$11906_Y + connect \Y $gt$libresoc.v:184505$12090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182202$11907 + cell $gt $gt$libresoc.v:184506$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377237,10 +381246,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:182202$11907_Y + connect \Y $gt$libresoc.v:184506$12091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182203$11908 + cell $gt $gt$libresoc.v:184507$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377248,10 +381257,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:182203$11908_Y + connect \Y $gt$libresoc.v:184507$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182204$11909 + cell $gt $gt$libresoc.v:184508$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377259,10 +381268,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:182204$11909_Y + connect \Y $gt$libresoc.v:184508$12093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182205$11910 + cell $gt $gt$libresoc.v:184509$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377270,10 +381279,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:182205$11910_Y + connect \Y $gt$libresoc.v:184509$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182206$11911 + cell $gt $gt$libresoc.v:184510$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377281,10 +381290,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:182206$11911_Y + connect \Y $gt$libresoc.v:184510$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182207$11912 + cell $gt $gt$libresoc.v:184511$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377292,10 +381301,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:182207$11912_Y + connect \Y $gt$libresoc.v:184511$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182208$11913 + cell $gt $gt$libresoc.v:184512$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377303,10 +381312,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:182208$11913_Y + connect \Y $gt$libresoc.v:184512$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182209$11914 + cell $gt $gt$libresoc.v:184513$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377314,10 +381323,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:182209$11914_Y + connect \Y $gt$libresoc.v:184513$12098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182210$11915 + cell $gt $gt$libresoc.v:184514$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377325,10 +381334,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:182210$11915_Y + connect \Y $gt$libresoc.v:184514$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182211$11916 + cell $gt $gt$libresoc.v:184515$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377336,10 +381345,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:182211$11916_Y + connect \Y $gt$libresoc.v:184515$12100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182212$11917 + cell $gt $gt$libresoc.v:184516$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377347,10 +381356,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:182212$11917_Y + connect \Y $gt$libresoc.v:184516$12101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182213$11918 + cell $gt $gt$libresoc.v:184517$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377358,10 +381367,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:182213$11918_Y + connect \Y $gt$libresoc.v:184517$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182214$11919 + cell $gt $gt$libresoc.v:184518$12103 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377369,10 +381378,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:182214$11919_Y + connect \Y $gt$libresoc.v:184518$12103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182215$11920 + cell $gt $gt$libresoc.v:184519$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377380,10 +381389,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:182215$11920_Y + connect \Y $gt$libresoc.v:184519$12104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182216$11921 + cell $gt $gt$libresoc.v:184520$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377391,18 +381400,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:182216$11921_Y + connect \Y $gt$libresoc.v:184520$12105_Y end - attribute \src "libresoc.v:182019.7-182019.20" - process $proc$libresoc.v:182019$11923 + attribute \src "libresoc.v:184323.7-184323.20" + process $proc$libresoc.v:184323$12107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182217.3-182604.6" - process $proc$libresoc.v:182217$11922 + attribute \src "libresoc.v:184521.3-184908.6" + process $proc$libresoc.v:184521$12106 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -377469,9 +381478,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:182218.5-182218.29" + attribute \src "libresoc.v:184522.5-184522.29" switch \initial - attribute \src "libresoc.v:182218.9-182218.17" + attribute \src "libresoc.v:184522.9-184522.17" case 1'1 case end @@ -378054,102 +382063,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:182153$11858_Y - connect \$99 $gt$libresoc.v:182154$11859_Y - connect \$101 $gt$libresoc.v:182155$11860_Y - connect \$103 $gt$libresoc.v:182156$11861_Y - connect \$105 $gt$libresoc.v:182157$11862_Y - connect \$107 $gt$libresoc.v:182158$11863_Y - connect \$109 $gt$libresoc.v:182159$11864_Y - connect \$111 $gt$libresoc.v:182160$11865_Y - connect \$113 $gt$libresoc.v:182161$11866_Y - connect \$115 $gt$libresoc.v:182162$11867_Y - connect \$117 $gt$libresoc.v:182163$11868_Y - connect \$11 $gt$libresoc.v:182164$11869_Y - connect \$119 $gt$libresoc.v:182165$11870_Y - connect \$121 $gt$libresoc.v:182166$11871_Y - connect \$123 $gt$libresoc.v:182167$11872_Y - connect \$125 $gt$libresoc.v:182168$11873_Y - connect \$127 $gt$libresoc.v:182169$11874_Y - connect \$13 $gt$libresoc.v:182170$11875_Y - connect \$15 $gt$libresoc.v:182171$11876_Y - connect \$17 $gt$libresoc.v:182172$11877_Y - connect \$1 $gt$libresoc.v:182173$11878_Y - connect \$19 $gt$libresoc.v:182174$11879_Y - connect \$21 $gt$libresoc.v:182175$11880_Y - connect \$23 $gt$libresoc.v:182176$11881_Y - connect \$25 $gt$libresoc.v:182177$11882_Y - connect \$27 $gt$libresoc.v:182178$11883_Y - connect \$29 $gt$libresoc.v:182179$11884_Y - connect \$31 $gt$libresoc.v:182180$11885_Y - connect \$33 $gt$libresoc.v:182181$11886_Y - connect \$35 $gt$libresoc.v:182182$11887_Y - connect \$37 $gt$libresoc.v:182183$11888_Y - connect \$3 $gt$libresoc.v:182184$11889_Y - connect \$39 $gt$libresoc.v:182185$11890_Y - connect \$41 $gt$libresoc.v:182186$11891_Y - connect \$43 $gt$libresoc.v:182187$11892_Y - connect \$45 $gt$libresoc.v:182188$11893_Y - connect \$47 $gt$libresoc.v:182189$11894_Y - connect \$49 $gt$libresoc.v:182190$11895_Y - connect \$51 $gt$libresoc.v:182191$11896_Y - connect \$53 $gt$libresoc.v:182192$11897_Y - connect \$55 $gt$libresoc.v:182193$11898_Y - connect \$57 $gt$libresoc.v:182194$11899_Y - connect \$5 $gt$libresoc.v:182195$11900_Y - connect \$59 $gt$libresoc.v:182196$11901_Y - connect \$61 $gt$libresoc.v:182197$11902_Y - connect \$63 $gt$libresoc.v:182198$11903_Y - connect \$65 $gt$libresoc.v:182199$11904_Y - connect \$67 $gt$libresoc.v:182200$11905_Y - connect \$69 $gt$libresoc.v:182201$11906_Y - connect \$71 $gt$libresoc.v:182202$11907_Y - connect \$73 $gt$libresoc.v:182203$11908_Y - connect \$75 $gt$libresoc.v:182204$11909_Y - connect \$77 $gt$libresoc.v:182205$11910_Y - connect \$7 $gt$libresoc.v:182206$11911_Y - connect \$79 $gt$libresoc.v:182207$11912_Y - connect \$81 $gt$libresoc.v:182208$11913_Y - connect \$83 $gt$libresoc.v:182209$11914_Y - connect \$85 $gt$libresoc.v:182210$11915_Y - connect \$87 $gt$libresoc.v:182211$11916_Y - connect \$89 $gt$libresoc.v:182212$11917_Y - connect \$91 $gt$libresoc.v:182213$11918_Y - connect \$93 $gt$libresoc.v:182214$11919_Y - connect \$95 $gt$libresoc.v:182215$11920_Y - connect \$97 $gt$libresoc.v:182216$11921_Y + connect \$9 $gt$libresoc.v:184457$12042_Y + connect \$99 $gt$libresoc.v:184458$12043_Y + connect \$101 $gt$libresoc.v:184459$12044_Y + connect \$103 $gt$libresoc.v:184460$12045_Y + connect \$105 $gt$libresoc.v:184461$12046_Y + connect \$107 $gt$libresoc.v:184462$12047_Y + connect \$109 $gt$libresoc.v:184463$12048_Y + connect \$111 $gt$libresoc.v:184464$12049_Y + connect \$113 $gt$libresoc.v:184465$12050_Y + connect \$115 $gt$libresoc.v:184466$12051_Y + connect \$117 $gt$libresoc.v:184467$12052_Y + connect \$11 $gt$libresoc.v:184468$12053_Y + connect \$119 $gt$libresoc.v:184469$12054_Y + connect \$121 $gt$libresoc.v:184470$12055_Y + connect \$123 $gt$libresoc.v:184471$12056_Y + connect \$125 $gt$libresoc.v:184472$12057_Y + connect \$127 $gt$libresoc.v:184473$12058_Y + connect \$13 $gt$libresoc.v:184474$12059_Y + connect \$15 $gt$libresoc.v:184475$12060_Y + connect \$17 $gt$libresoc.v:184476$12061_Y + connect \$1 $gt$libresoc.v:184477$12062_Y + connect \$19 $gt$libresoc.v:184478$12063_Y + connect \$21 $gt$libresoc.v:184479$12064_Y + connect \$23 $gt$libresoc.v:184480$12065_Y + connect \$25 $gt$libresoc.v:184481$12066_Y + connect \$27 $gt$libresoc.v:184482$12067_Y + connect \$29 $gt$libresoc.v:184483$12068_Y + connect \$31 $gt$libresoc.v:184484$12069_Y + connect \$33 $gt$libresoc.v:184485$12070_Y + connect \$35 $gt$libresoc.v:184486$12071_Y + connect \$37 $gt$libresoc.v:184487$12072_Y + connect \$3 $gt$libresoc.v:184488$12073_Y + connect \$39 $gt$libresoc.v:184489$12074_Y + connect \$41 $gt$libresoc.v:184490$12075_Y + connect \$43 $gt$libresoc.v:184491$12076_Y + connect \$45 $gt$libresoc.v:184492$12077_Y + connect \$47 $gt$libresoc.v:184493$12078_Y + connect \$49 $gt$libresoc.v:184494$12079_Y + connect \$51 $gt$libresoc.v:184495$12080_Y + connect \$53 $gt$libresoc.v:184496$12081_Y + connect \$55 $gt$libresoc.v:184497$12082_Y + connect \$57 $gt$libresoc.v:184498$12083_Y + connect \$5 $gt$libresoc.v:184499$12084_Y + connect \$59 $gt$libresoc.v:184500$12085_Y + connect \$61 $gt$libresoc.v:184501$12086_Y + connect \$63 $gt$libresoc.v:184502$12087_Y + connect \$65 $gt$libresoc.v:184503$12088_Y + connect \$67 $gt$libresoc.v:184504$12089_Y + connect \$69 $gt$libresoc.v:184505$12090_Y + connect \$71 $gt$libresoc.v:184506$12091_Y + connect \$73 $gt$libresoc.v:184507$12092_Y + connect \$75 $gt$libresoc.v:184508$12093_Y + connect \$77 $gt$libresoc.v:184509$12094_Y + connect \$7 $gt$libresoc.v:184510$12095_Y + connect \$79 $gt$libresoc.v:184511$12096_Y + connect \$81 $gt$libresoc.v:184512$12097_Y + connect \$83 $gt$libresoc.v:184513$12098_Y + connect \$85 $gt$libresoc.v:184514$12099_Y + connect \$87 $gt$libresoc.v:184515$12100_Y + connect \$89 $gt$libresoc.v:184516$12101_Y + connect \$91 $gt$libresoc.v:184517$12102_Y + connect \$93 $gt$libresoc.v:184518$12103_Y + connect \$95 $gt$libresoc.v:184519$12104_Y + connect \$97 $gt$libresoc.v:184520$12105_Y end -attribute \src "libresoc.v:182609.1-182667.10" +attribute \src "libresoc.v:184913.1-184971.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:182610.7-182610.20" + attribute \src "libresoc.v:184914.7-184914.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182655.3-182663.6" - wire $0\q_int$next[0:0]$11934 - attribute \src "libresoc.v:182653.3-182654.27" + attribute \src "libresoc.v:184959.3-184967.6" + wire $0\q_int$next[0:0]$12118 + attribute \src "libresoc.v:184957.3-184958.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182655.3-182663.6" - wire $1\q_int$next[0:0]$11935 - attribute \src "libresoc.v:182632.7-182632.19" + attribute \src "libresoc.v:184959.3-184967.6" + wire $1\q_int$next[0:0]$12119 + attribute \src "libresoc.v:184936.7-184936.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182645.17-182645.96" - wire $and$libresoc.v:182645$11924_Y - attribute \src "libresoc.v:182650.17-182650.96" - wire $and$libresoc.v:182650$11929_Y - attribute \src "libresoc.v:182647.18-182647.94" - wire $not$libresoc.v:182647$11926_Y - attribute \src "libresoc.v:182649.17-182649.93" - wire $not$libresoc.v:182649$11928_Y - attribute \src "libresoc.v:182652.17-182652.93" - wire $not$libresoc.v:182652$11931_Y - attribute \src "libresoc.v:182646.18-182646.99" - wire $or$libresoc.v:182646$11925_Y - attribute \src "libresoc.v:182648.18-182648.100" - wire $or$libresoc.v:182648$11927_Y - attribute \src "libresoc.v:182651.17-182651.98" - wire $or$libresoc.v:182651$11930_Y + attribute \src "libresoc.v:184949.17-184949.96" + wire $and$libresoc.v:184949$12108_Y + attribute \src "libresoc.v:184954.17-184954.96" + wire $and$libresoc.v:184954$12113_Y + attribute \src "libresoc.v:184951.18-184951.94" + wire $not$libresoc.v:184951$12110_Y + attribute \src "libresoc.v:184953.17-184953.93" + wire $not$libresoc.v:184953$12112_Y + attribute \src "libresoc.v:184956.17-184956.93" + wire $not$libresoc.v:184956$12115_Y + attribute \src "libresoc.v:184950.18-184950.99" + wire $or$libresoc.v:184950$12109_Y + attribute \src "libresoc.v:184952.18-184952.100" + wire $or$libresoc.v:184952$12111_Y + attribute \src "libresoc.v:184955.17-184955.98" + wire $or$libresoc.v:184955$12114_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378166,11 +382175,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182610.7-182610.15" + attribute \src "libresoc.v:184914.7-184914.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378187,7 +382196,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182645$11924 + cell $and $and$libresoc.v:184949$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378195,10 +382204,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182645$11924_Y + connect \Y $and$libresoc.v:184949$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182650$11929 + cell $and $and$libresoc.v:184954$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378206,34 +382215,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182650$11929_Y + connect \Y $and$libresoc.v:184954$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182647$11926 + cell $not $not$libresoc.v:184951$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182647$11926_Y + connect \Y $not$libresoc.v:184951$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182649$11928 + cell $not $not$libresoc.v:184953$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182649$11928_Y + connect \Y $not$libresoc.v:184953$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182652$11931 + cell $not $not$libresoc.v:184956$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182652$11931_Y + connect \Y $not$libresoc.v:184956$12115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182646$11925 + cell $or $or$libresoc.v:184950$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378241,10 +382250,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182646$11925_Y + connect \Y $or$libresoc.v:184950$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182648$11927 + cell $or $or$libresoc.v:184952$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378252,10 +382261,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182648$11927_Y + connect \Y $or$libresoc.v:184952$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182651$11930 + cell $or $or$libresoc.v:184955$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378263,39 +382272,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182651$11930_Y + connect \Y $or$libresoc.v:184955$12114_Y end - attribute \src "libresoc.v:182610.7-182610.20" - process $proc$libresoc.v:182610$11936 + attribute \src "libresoc.v:184914.7-184914.20" + process $proc$libresoc.v:184914$12120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182632.7-182632.19" - process $proc$libresoc.v:182632$11937 + attribute \src "libresoc.v:184936.7-184936.19" + process $proc$libresoc.v:184936$12121 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182653.3-182654.27" - process $proc$libresoc.v:182653$11932 + attribute \src "libresoc.v:184957.3-184958.27" + process $proc$libresoc.v:184957$12116 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182655.3-182663.6" - process $proc$libresoc.v:182655$11933 + attribute \src "libresoc.v:184959.3-184967.6" + process $proc$libresoc.v:184959$12117 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11934 $1\q_int$next[0:0]$11935 - attribute \src "libresoc.v:182656.5-182656.29" + assign $0\q_int$next[0:0]$12118 $1\q_int$next[0:0]$12119 + attribute \src "libresoc.v:184960.5-184960.29" switch \initial - attribute \src "libresoc.v:182656.9-182656.17" + attribute \src "libresoc.v:184960.9-184960.17" case 1'1 case end @@ -378304,56 +382313,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11935 1'0 + assign $1\q_int$next[0:0]$12119 1'0 case - assign $1\q_int$next[0:0]$11935 \$5 + assign $1\q_int$next[0:0]$12119 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11934 + update \q_int$next $0\q_int$next[0:0]$12118 end - connect \$9 $and$libresoc.v:182645$11924_Y - connect \$11 $or$libresoc.v:182646$11925_Y - connect \$13 $not$libresoc.v:182647$11926_Y - connect \$15 $or$libresoc.v:182648$11927_Y - connect \$1 $not$libresoc.v:182649$11928_Y - connect \$3 $and$libresoc.v:182650$11929_Y - connect \$5 $or$libresoc.v:182651$11930_Y - connect \$7 $not$libresoc.v:182652$11931_Y + connect \$9 $and$libresoc.v:184949$12108_Y + connect \$11 $or$libresoc.v:184950$12109_Y + connect \$13 $not$libresoc.v:184951$12110_Y + connect \$15 $or$libresoc.v:184952$12111_Y + connect \$1 $not$libresoc.v:184953$12112_Y + connect \$3 $and$libresoc.v:184954$12113_Y + connect \$5 $or$libresoc.v:184955$12114_Y + connect \$7 $not$libresoc.v:184956$12115_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182671.1-182729.10" +attribute \src "libresoc.v:184975.1-185033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:182672.7-182672.20" + attribute \src "libresoc.v:184976.7-184976.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182717.3-182725.6" - wire $0\q_int$next[0:0]$11948 - attribute \src "libresoc.v:182715.3-182716.27" + attribute \src "libresoc.v:185021.3-185029.6" + wire $0\q_int$next[0:0]$12132 + attribute \src "libresoc.v:185019.3-185020.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182717.3-182725.6" - wire $1\q_int$next[0:0]$11949 - attribute \src "libresoc.v:182694.7-182694.19" + attribute \src "libresoc.v:185021.3-185029.6" + wire $1\q_int$next[0:0]$12133 + attribute \src "libresoc.v:184998.7-184998.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182707.17-182707.96" - wire $and$libresoc.v:182707$11938_Y - attribute \src "libresoc.v:182712.17-182712.96" - wire $and$libresoc.v:182712$11943_Y - attribute \src "libresoc.v:182709.18-182709.94" - wire $not$libresoc.v:182709$11940_Y - attribute \src "libresoc.v:182711.17-182711.93" - wire $not$libresoc.v:182711$11942_Y - attribute \src "libresoc.v:182714.17-182714.93" - wire $not$libresoc.v:182714$11945_Y - attribute \src "libresoc.v:182708.18-182708.99" - wire $or$libresoc.v:182708$11939_Y - attribute \src "libresoc.v:182710.18-182710.100" - wire $or$libresoc.v:182710$11941_Y - attribute \src "libresoc.v:182713.17-182713.98" - wire $or$libresoc.v:182713$11944_Y + attribute \src "libresoc.v:185011.17-185011.96" + wire $and$libresoc.v:185011$12122_Y + attribute \src "libresoc.v:185016.17-185016.96" + wire $and$libresoc.v:185016$12127_Y + attribute \src "libresoc.v:185013.18-185013.94" + wire $not$libresoc.v:185013$12124_Y + attribute \src "libresoc.v:185015.17-185015.93" + wire $not$libresoc.v:185015$12126_Y + attribute \src "libresoc.v:185018.17-185018.93" + wire $not$libresoc.v:185018$12129_Y + attribute \src "libresoc.v:185012.18-185012.99" + wire $or$libresoc.v:185012$12123_Y + attribute \src "libresoc.v:185014.18-185014.100" + wire $or$libresoc.v:185014$12125_Y + attribute \src "libresoc.v:185017.17-185017.98" + wire $or$libresoc.v:185017$12128_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378370,11 +382379,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182672.7-182672.15" + attribute \src "libresoc.v:184976.7-184976.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378391,7 +382400,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182707$11938 + cell $and $and$libresoc.v:185011$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378399,10 +382408,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182707$11938_Y + connect \Y $and$libresoc.v:185011$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182712$11943 + cell $and $and$libresoc.v:185016$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378410,34 +382419,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182712$11943_Y + connect \Y $and$libresoc.v:185016$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182709$11940 + cell $not $not$libresoc.v:185013$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182709$11940_Y + connect \Y $not$libresoc.v:185013$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182711$11942 + cell $not $not$libresoc.v:185015$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182711$11942_Y + connect \Y $not$libresoc.v:185015$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182714$11945 + cell $not $not$libresoc.v:185018$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182714$11945_Y + connect \Y $not$libresoc.v:185018$12129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182708$11939 + cell $or $or$libresoc.v:185012$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378445,10 +382454,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182708$11939_Y + connect \Y $or$libresoc.v:185012$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182710$11941 + cell $or $or$libresoc.v:185014$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378456,10 +382465,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182710$11941_Y + connect \Y $or$libresoc.v:185014$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182713$11944 + cell $or $or$libresoc.v:185017$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378467,39 +382476,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182713$11944_Y + connect \Y $or$libresoc.v:185017$12128_Y end - attribute \src "libresoc.v:182672.7-182672.20" - process $proc$libresoc.v:182672$11950 + attribute \src "libresoc.v:184976.7-184976.20" + process $proc$libresoc.v:184976$12134 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182694.7-182694.19" - process $proc$libresoc.v:182694$11951 + attribute \src "libresoc.v:184998.7-184998.19" + process $proc$libresoc.v:184998$12135 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182715.3-182716.27" - process $proc$libresoc.v:182715$11946 + attribute \src "libresoc.v:185019.3-185020.27" + process $proc$libresoc.v:185019$12130 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182717.3-182725.6" - process $proc$libresoc.v:182717$11947 + attribute \src "libresoc.v:185021.3-185029.6" + process $proc$libresoc.v:185021$12131 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11948 $1\q_int$next[0:0]$11949 - attribute \src "libresoc.v:182718.5-182718.29" + assign $0\q_int$next[0:0]$12132 $1\q_int$next[0:0]$12133 + attribute \src "libresoc.v:185022.5-185022.29" switch \initial - attribute \src "libresoc.v:182718.9-182718.17" + attribute \src "libresoc.v:185022.9-185022.17" case 1'1 case end @@ -378508,56 +382517,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11949 1'0 + assign $1\q_int$next[0:0]$12133 1'0 case - assign $1\q_int$next[0:0]$11949 \$5 + assign $1\q_int$next[0:0]$12133 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11948 + update \q_int$next $0\q_int$next[0:0]$12132 end - connect \$9 $and$libresoc.v:182707$11938_Y - connect \$11 $or$libresoc.v:182708$11939_Y - connect \$13 $not$libresoc.v:182709$11940_Y - connect \$15 $or$libresoc.v:182710$11941_Y - connect \$1 $not$libresoc.v:182711$11942_Y - connect \$3 $and$libresoc.v:182712$11943_Y - connect \$5 $or$libresoc.v:182713$11944_Y - connect \$7 $not$libresoc.v:182714$11945_Y + connect \$9 $and$libresoc.v:185011$12122_Y + connect \$11 $or$libresoc.v:185012$12123_Y + connect \$13 $not$libresoc.v:185013$12124_Y + connect \$15 $or$libresoc.v:185014$12125_Y + connect \$1 $not$libresoc.v:185015$12126_Y + connect \$3 $and$libresoc.v:185016$12127_Y + connect \$5 $or$libresoc.v:185017$12128_Y + connect \$7 $not$libresoc.v:185018$12129_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182733.1-182791.10" +attribute \src "libresoc.v:185037.1-185095.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:182734.7-182734.20" + attribute \src "libresoc.v:185038.7-185038.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182779.3-182787.6" - wire $0\q_int$next[0:0]$11962 - attribute \src "libresoc.v:182777.3-182778.27" + attribute \src "libresoc.v:185083.3-185091.6" + wire $0\q_int$next[0:0]$12146 + attribute \src "libresoc.v:185081.3-185082.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182779.3-182787.6" - wire $1\q_int$next[0:0]$11963 - attribute \src "libresoc.v:182756.7-182756.19" + attribute \src "libresoc.v:185083.3-185091.6" + wire $1\q_int$next[0:0]$12147 + attribute \src "libresoc.v:185060.7-185060.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182769.17-182769.96" - wire $and$libresoc.v:182769$11952_Y - attribute \src "libresoc.v:182774.17-182774.96" - wire $and$libresoc.v:182774$11957_Y - attribute \src "libresoc.v:182771.18-182771.94" - wire $not$libresoc.v:182771$11954_Y - attribute \src "libresoc.v:182773.17-182773.93" - wire $not$libresoc.v:182773$11956_Y - attribute \src "libresoc.v:182776.17-182776.93" - wire $not$libresoc.v:182776$11959_Y - attribute \src "libresoc.v:182770.18-182770.99" - wire $or$libresoc.v:182770$11953_Y - attribute \src "libresoc.v:182772.18-182772.100" - wire $or$libresoc.v:182772$11955_Y - attribute \src "libresoc.v:182775.17-182775.98" - wire $or$libresoc.v:182775$11958_Y + attribute \src "libresoc.v:185073.17-185073.96" + wire $and$libresoc.v:185073$12136_Y + attribute \src "libresoc.v:185078.17-185078.96" + wire $and$libresoc.v:185078$12141_Y + attribute \src "libresoc.v:185075.18-185075.94" + wire $not$libresoc.v:185075$12138_Y + attribute \src "libresoc.v:185077.17-185077.93" + wire $not$libresoc.v:185077$12140_Y + attribute \src "libresoc.v:185080.17-185080.93" + wire $not$libresoc.v:185080$12143_Y + attribute \src "libresoc.v:185074.18-185074.99" + wire $or$libresoc.v:185074$12137_Y + attribute \src "libresoc.v:185076.18-185076.100" + wire $or$libresoc.v:185076$12139_Y + attribute \src "libresoc.v:185079.17-185079.98" + wire $or$libresoc.v:185079$12142_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378574,11 +382583,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182734.7-182734.15" + attribute \src "libresoc.v:185038.7-185038.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378595,7 +382604,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182769$11952 + cell $and $and$libresoc.v:185073$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378603,10 +382612,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182769$11952_Y + connect \Y $and$libresoc.v:185073$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182774$11957 + cell $and $and$libresoc.v:185078$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378614,34 +382623,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182774$11957_Y + connect \Y $and$libresoc.v:185078$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182771$11954 + cell $not $not$libresoc.v:185075$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182771$11954_Y + connect \Y $not$libresoc.v:185075$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182773$11956 + cell $not $not$libresoc.v:185077$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182773$11956_Y + connect \Y $not$libresoc.v:185077$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182776$11959 + cell $not $not$libresoc.v:185080$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182776$11959_Y + connect \Y $not$libresoc.v:185080$12143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182770$11953 + cell $or $or$libresoc.v:185074$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378649,10 +382658,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182770$11953_Y + connect \Y $or$libresoc.v:185074$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182772$11955 + cell $or $or$libresoc.v:185076$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378660,10 +382669,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182772$11955_Y + connect \Y $or$libresoc.v:185076$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182775$11958 + cell $or $or$libresoc.v:185079$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378671,39 +382680,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182775$11958_Y + connect \Y $or$libresoc.v:185079$12142_Y end - attribute \src "libresoc.v:182734.7-182734.20" - process $proc$libresoc.v:182734$11964 + attribute \src "libresoc.v:185038.7-185038.20" + process $proc$libresoc.v:185038$12148 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182756.7-182756.19" - process $proc$libresoc.v:182756$11965 + attribute \src "libresoc.v:185060.7-185060.19" + process $proc$libresoc.v:185060$12149 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182777.3-182778.27" - process $proc$libresoc.v:182777$11960 + attribute \src "libresoc.v:185081.3-185082.27" + process $proc$libresoc.v:185081$12144 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182779.3-182787.6" - process $proc$libresoc.v:182779$11961 + attribute \src "libresoc.v:185083.3-185091.6" + process $proc$libresoc.v:185083$12145 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11962 $1\q_int$next[0:0]$11963 - attribute \src "libresoc.v:182780.5-182780.29" + assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 + attribute \src "libresoc.v:185084.5-185084.29" switch \initial - attribute \src "libresoc.v:182780.9-182780.17" + attribute \src "libresoc.v:185084.9-185084.17" case 1'1 case end @@ -378712,56 +382721,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11963 1'0 + assign $1\q_int$next[0:0]$12147 1'0 case - assign $1\q_int$next[0:0]$11963 \$5 + assign $1\q_int$next[0:0]$12147 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11962 + update \q_int$next $0\q_int$next[0:0]$12146 end - connect \$9 $and$libresoc.v:182769$11952_Y - connect \$11 $or$libresoc.v:182770$11953_Y - connect \$13 $not$libresoc.v:182771$11954_Y - connect \$15 $or$libresoc.v:182772$11955_Y - connect \$1 $not$libresoc.v:182773$11956_Y - connect \$3 $and$libresoc.v:182774$11957_Y - connect \$5 $or$libresoc.v:182775$11958_Y - connect \$7 $not$libresoc.v:182776$11959_Y + connect \$9 $and$libresoc.v:185073$12136_Y + connect \$11 $or$libresoc.v:185074$12137_Y + connect \$13 $not$libresoc.v:185075$12138_Y + connect \$15 $or$libresoc.v:185076$12139_Y + connect \$1 $not$libresoc.v:185077$12140_Y + connect \$3 $and$libresoc.v:185078$12141_Y + connect \$5 $or$libresoc.v:185079$12142_Y + connect \$7 $not$libresoc.v:185080$12143_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182795.1-182853.10" +attribute \src "libresoc.v:185099.1-185157.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:182796.7-182796.20" + attribute \src "libresoc.v:185100.7-185100.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182841.3-182849.6" - wire $0\q_int$next[0:0]$11976 - attribute \src "libresoc.v:182839.3-182840.27" + attribute \src "libresoc.v:185145.3-185153.6" + wire $0\q_int$next[0:0]$12160 + attribute \src "libresoc.v:185143.3-185144.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182841.3-182849.6" - wire $1\q_int$next[0:0]$11977 - attribute \src "libresoc.v:182818.7-182818.19" + attribute \src "libresoc.v:185145.3-185153.6" + wire $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185122.7-185122.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182831.17-182831.96" - wire $and$libresoc.v:182831$11966_Y - attribute \src "libresoc.v:182836.17-182836.96" - wire $and$libresoc.v:182836$11971_Y - attribute \src "libresoc.v:182833.18-182833.94" - wire $not$libresoc.v:182833$11968_Y - attribute \src "libresoc.v:182835.17-182835.93" - wire $not$libresoc.v:182835$11970_Y - attribute \src "libresoc.v:182838.17-182838.93" - wire $not$libresoc.v:182838$11973_Y - attribute \src "libresoc.v:182832.18-182832.99" - wire $or$libresoc.v:182832$11967_Y - attribute \src "libresoc.v:182834.18-182834.100" - wire $or$libresoc.v:182834$11969_Y - attribute \src "libresoc.v:182837.17-182837.98" - wire $or$libresoc.v:182837$11972_Y + attribute \src "libresoc.v:185135.17-185135.96" + wire $and$libresoc.v:185135$12150_Y + attribute \src "libresoc.v:185140.17-185140.96" + wire $and$libresoc.v:185140$12155_Y + attribute \src "libresoc.v:185137.18-185137.94" + wire $not$libresoc.v:185137$12152_Y + attribute \src "libresoc.v:185139.17-185139.93" + wire $not$libresoc.v:185139$12154_Y + attribute \src "libresoc.v:185142.17-185142.93" + wire $not$libresoc.v:185142$12157_Y + attribute \src "libresoc.v:185136.18-185136.99" + wire $or$libresoc.v:185136$12151_Y + attribute \src "libresoc.v:185138.18-185138.100" + wire $or$libresoc.v:185138$12153_Y + attribute \src "libresoc.v:185141.17-185141.98" + wire $or$libresoc.v:185141$12156_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378778,11 +382787,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182796.7-182796.15" + attribute \src "libresoc.v:185100.7-185100.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378799,7 +382808,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182831$11966 + cell $and $and$libresoc.v:185135$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378807,10 +382816,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182831$11966_Y + connect \Y $and$libresoc.v:185135$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182836$11971 + cell $and $and$libresoc.v:185140$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378818,34 +382827,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182836$11971_Y + connect \Y $and$libresoc.v:185140$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182833$11968 + cell $not $not$libresoc.v:185137$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182833$11968_Y + connect \Y $not$libresoc.v:185137$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182835$11970 + cell $not $not$libresoc.v:185139$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182835$11970_Y + connect \Y $not$libresoc.v:185139$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182838$11973 + cell $not $not$libresoc.v:185142$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182838$11973_Y + connect \Y $not$libresoc.v:185142$12157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182832$11967 + cell $or $or$libresoc.v:185136$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378853,10 +382862,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182832$11967_Y + connect \Y $or$libresoc.v:185136$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182834$11969 + cell $or $or$libresoc.v:185138$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378864,10 +382873,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182834$11969_Y + connect \Y $or$libresoc.v:185138$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182837$11972 + cell $or $or$libresoc.v:185141$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378875,39 +382884,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182837$11972_Y + connect \Y $or$libresoc.v:185141$12156_Y end - attribute \src "libresoc.v:182796.7-182796.20" - process $proc$libresoc.v:182796$11978 + attribute \src "libresoc.v:185100.7-185100.20" + process $proc$libresoc.v:185100$12162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182818.7-182818.19" - process $proc$libresoc.v:182818$11979 + attribute \src "libresoc.v:185122.7-185122.19" + process $proc$libresoc.v:185122$12163 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182839.3-182840.27" - process $proc$libresoc.v:182839$11974 + attribute \src "libresoc.v:185143.3-185144.27" + process $proc$libresoc.v:185143$12158 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182841.3-182849.6" - process $proc$libresoc.v:182841$11975 + attribute \src "libresoc.v:185145.3-185153.6" + process $proc$libresoc.v:185145$12159 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11976 $1\q_int$next[0:0]$11977 - attribute \src "libresoc.v:182842.5-182842.29" + assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185146.5-185146.29" switch \initial - attribute \src "libresoc.v:182842.9-182842.17" + attribute \src "libresoc.v:185146.9-185146.17" case 1'1 case end @@ -378916,56 +382925,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11977 1'0 + assign $1\q_int$next[0:0]$12161 1'0 case - assign $1\q_int$next[0:0]$11977 \$5 + assign $1\q_int$next[0:0]$12161 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11976 + update \q_int$next $0\q_int$next[0:0]$12160 end - connect \$9 $and$libresoc.v:182831$11966_Y - connect \$11 $or$libresoc.v:182832$11967_Y - connect \$13 $not$libresoc.v:182833$11968_Y - connect \$15 $or$libresoc.v:182834$11969_Y - connect \$1 $not$libresoc.v:182835$11970_Y - connect \$3 $and$libresoc.v:182836$11971_Y - connect \$5 $or$libresoc.v:182837$11972_Y - connect \$7 $not$libresoc.v:182838$11973_Y + connect \$9 $and$libresoc.v:185135$12150_Y + connect \$11 $or$libresoc.v:185136$12151_Y + connect \$13 $not$libresoc.v:185137$12152_Y + connect \$15 $or$libresoc.v:185138$12153_Y + connect \$1 $not$libresoc.v:185139$12154_Y + connect \$3 $and$libresoc.v:185140$12155_Y + connect \$5 $or$libresoc.v:185141$12156_Y + connect \$7 $not$libresoc.v:185142$12157_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182857.1-182915.10" +attribute \src "libresoc.v:185161.1-185219.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:182858.7-182858.20" + attribute \src "libresoc.v:185162.7-185162.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182903.3-182911.6" - wire $0\q_int$next[0:0]$11990 - attribute \src "libresoc.v:182901.3-182902.27" + attribute \src "libresoc.v:185207.3-185215.6" + wire $0\q_int$next[0:0]$12174 + attribute \src "libresoc.v:185205.3-185206.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182903.3-182911.6" - wire $1\q_int$next[0:0]$11991 - attribute \src "libresoc.v:182880.7-182880.19" + attribute \src "libresoc.v:185207.3-185215.6" + wire $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185184.7-185184.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182893.17-182893.96" - wire $and$libresoc.v:182893$11980_Y - attribute \src "libresoc.v:182898.17-182898.96" - wire $and$libresoc.v:182898$11985_Y - attribute \src "libresoc.v:182895.18-182895.94" - wire $not$libresoc.v:182895$11982_Y - attribute \src "libresoc.v:182897.17-182897.93" - wire $not$libresoc.v:182897$11984_Y - attribute \src "libresoc.v:182900.17-182900.93" - wire $not$libresoc.v:182900$11987_Y - attribute \src "libresoc.v:182894.18-182894.99" - wire $or$libresoc.v:182894$11981_Y - attribute \src "libresoc.v:182896.18-182896.100" - wire $or$libresoc.v:182896$11983_Y - attribute \src "libresoc.v:182899.17-182899.98" - wire $or$libresoc.v:182899$11986_Y + attribute \src "libresoc.v:185197.17-185197.96" + wire $and$libresoc.v:185197$12164_Y + attribute \src "libresoc.v:185202.17-185202.96" + wire $and$libresoc.v:185202$12169_Y + attribute \src "libresoc.v:185199.18-185199.94" + wire $not$libresoc.v:185199$12166_Y + attribute \src "libresoc.v:185201.17-185201.93" + wire $not$libresoc.v:185201$12168_Y + attribute \src "libresoc.v:185204.17-185204.93" + wire $not$libresoc.v:185204$12171_Y + attribute \src "libresoc.v:185198.18-185198.99" + wire $or$libresoc.v:185198$12165_Y + attribute \src "libresoc.v:185200.18-185200.100" + wire $or$libresoc.v:185200$12167_Y + attribute \src "libresoc.v:185203.17-185203.98" + wire $or$libresoc.v:185203$12170_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378982,11 +382991,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182858.7-182858.15" + attribute \src "libresoc.v:185162.7-185162.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379003,7 +383012,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182893$11980 + cell $and $and$libresoc.v:185197$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379011,10 +383020,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182893$11980_Y + connect \Y $and$libresoc.v:185197$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182898$11985 + cell $and $and$libresoc.v:185202$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379022,34 +383031,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182898$11985_Y + connect \Y $and$libresoc.v:185202$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182895$11982 + cell $not $not$libresoc.v:185199$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182895$11982_Y + connect \Y $not$libresoc.v:185199$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182897$11984 + cell $not $not$libresoc.v:185201$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182897$11984_Y + connect \Y $not$libresoc.v:185201$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182900$11987 + cell $not $not$libresoc.v:185204$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182900$11987_Y + connect \Y $not$libresoc.v:185204$12171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182894$11981 + cell $or $or$libresoc.v:185198$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379057,10 +383066,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182894$11981_Y + connect \Y $or$libresoc.v:185198$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182896$11983 + cell $or $or$libresoc.v:185200$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379068,10 +383077,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182896$11983_Y + connect \Y $or$libresoc.v:185200$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182899$11986 + cell $or $or$libresoc.v:185203$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379079,39 +383088,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182899$11986_Y + connect \Y $or$libresoc.v:185203$12170_Y end - attribute \src "libresoc.v:182858.7-182858.20" - process $proc$libresoc.v:182858$11992 + attribute \src "libresoc.v:185162.7-185162.20" + process $proc$libresoc.v:185162$12176 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182880.7-182880.19" - process $proc$libresoc.v:182880$11993 + attribute \src "libresoc.v:185184.7-185184.19" + process $proc$libresoc.v:185184$12177 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182901.3-182902.27" - process $proc$libresoc.v:182901$11988 + attribute \src "libresoc.v:185205.3-185206.27" + process $proc$libresoc.v:185205$12172 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182903.3-182911.6" - process $proc$libresoc.v:182903$11989 + attribute \src "libresoc.v:185207.3-185215.6" + process $proc$libresoc.v:185207$12173 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11990 $1\q_int$next[0:0]$11991 - attribute \src "libresoc.v:182904.5-182904.29" + assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185208.5-185208.29" switch \initial - attribute \src "libresoc.v:182904.9-182904.17" + attribute \src "libresoc.v:185208.9-185208.17" case 1'1 case end @@ -379120,56 +383129,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11991 1'0 + assign $1\q_int$next[0:0]$12175 1'0 case - assign $1\q_int$next[0:0]$11991 \$5 + assign $1\q_int$next[0:0]$12175 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11990 + update \q_int$next $0\q_int$next[0:0]$12174 end - connect \$9 $and$libresoc.v:182893$11980_Y - connect \$11 $or$libresoc.v:182894$11981_Y - connect \$13 $not$libresoc.v:182895$11982_Y - connect \$15 $or$libresoc.v:182896$11983_Y - connect \$1 $not$libresoc.v:182897$11984_Y - connect \$3 $and$libresoc.v:182898$11985_Y - connect \$5 $or$libresoc.v:182899$11986_Y - connect \$7 $not$libresoc.v:182900$11987_Y + connect \$9 $and$libresoc.v:185197$12164_Y + connect \$11 $or$libresoc.v:185198$12165_Y + connect \$13 $not$libresoc.v:185199$12166_Y + connect \$15 $or$libresoc.v:185200$12167_Y + connect \$1 $not$libresoc.v:185201$12168_Y + connect \$3 $and$libresoc.v:185202$12169_Y + connect \$5 $or$libresoc.v:185203$12170_Y + connect \$7 $not$libresoc.v:185204$12171_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182919.1-182977.10" +attribute \src "libresoc.v:185223.1-185281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:182920.7-182920.20" + attribute \src "libresoc.v:185224.7-185224.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182965.3-182973.6" - wire $0\q_int$next[0:0]$12004 - attribute \src "libresoc.v:182963.3-182964.27" + attribute \src "libresoc.v:185269.3-185277.6" + wire $0\q_int$next[0:0]$12188 + attribute \src "libresoc.v:185267.3-185268.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182965.3-182973.6" - wire $1\q_int$next[0:0]$12005 - attribute \src "libresoc.v:182942.7-182942.19" + attribute \src "libresoc.v:185269.3-185277.6" + wire $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185246.7-185246.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182955.17-182955.96" - wire $and$libresoc.v:182955$11994_Y - attribute \src "libresoc.v:182960.17-182960.96" - wire $and$libresoc.v:182960$11999_Y - attribute \src "libresoc.v:182957.18-182957.94" - wire $not$libresoc.v:182957$11996_Y - attribute \src "libresoc.v:182959.17-182959.93" - wire $not$libresoc.v:182959$11998_Y - attribute \src "libresoc.v:182962.17-182962.93" - wire $not$libresoc.v:182962$12001_Y - attribute \src "libresoc.v:182956.18-182956.99" - wire $or$libresoc.v:182956$11995_Y - attribute \src "libresoc.v:182958.18-182958.100" - wire $or$libresoc.v:182958$11997_Y - attribute \src "libresoc.v:182961.17-182961.98" - wire $or$libresoc.v:182961$12000_Y + attribute \src "libresoc.v:185259.17-185259.96" + wire $and$libresoc.v:185259$12178_Y + attribute \src "libresoc.v:185264.17-185264.96" + wire $and$libresoc.v:185264$12183_Y + attribute \src "libresoc.v:185261.18-185261.94" + wire $not$libresoc.v:185261$12180_Y + attribute \src "libresoc.v:185263.17-185263.93" + wire $not$libresoc.v:185263$12182_Y + attribute \src "libresoc.v:185266.17-185266.93" + wire $not$libresoc.v:185266$12185_Y + attribute \src "libresoc.v:185260.18-185260.99" + wire $or$libresoc.v:185260$12179_Y + attribute \src "libresoc.v:185262.18-185262.100" + wire $or$libresoc.v:185262$12181_Y + attribute \src "libresoc.v:185265.17-185265.98" + wire $or$libresoc.v:185265$12184_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379186,11 +383195,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182920.7-182920.15" + attribute \src "libresoc.v:185224.7-185224.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379207,7 +383216,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182955$11994 + cell $and $and$libresoc.v:185259$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379215,10 +383224,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182955$11994_Y + connect \Y $and$libresoc.v:185259$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182960$11999 + cell $and $and$libresoc.v:185264$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379226,34 +383235,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182960$11999_Y + connect \Y $and$libresoc.v:185264$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182957$11996 + cell $not $not$libresoc.v:185261$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182957$11996_Y + connect \Y $not$libresoc.v:185261$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182959$11998 + cell $not $not$libresoc.v:185263$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182959$11998_Y + connect \Y $not$libresoc.v:185263$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182962$12001 + cell $not $not$libresoc.v:185266$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182962$12001_Y + connect \Y $not$libresoc.v:185266$12185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182956$11995 + cell $or $or$libresoc.v:185260$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379261,10 +383270,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182956$11995_Y + connect \Y $or$libresoc.v:185260$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182958$11997 + cell $or $or$libresoc.v:185262$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379272,10 +383281,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182958$11997_Y + connect \Y $or$libresoc.v:185262$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182961$12000 + cell $or $or$libresoc.v:185265$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379283,39 +383292,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182961$12000_Y + connect \Y $or$libresoc.v:185265$12184_Y end - attribute \src "libresoc.v:182920.7-182920.20" - process $proc$libresoc.v:182920$12006 + attribute \src "libresoc.v:185224.7-185224.20" + process $proc$libresoc.v:185224$12190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182942.7-182942.19" - process $proc$libresoc.v:182942$12007 + attribute \src "libresoc.v:185246.7-185246.19" + process $proc$libresoc.v:185246$12191 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182963.3-182964.27" - process $proc$libresoc.v:182963$12002 + attribute \src "libresoc.v:185267.3-185268.27" + process $proc$libresoc.v:185267$12186 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182965.3-182973.6" - process $proc$libresoc.v:182965$12003 + attribute \src "libresoc.v:185269.3-185277.6" + process $proc$libresoc.v:185269$12187 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12004 $1\q_int$next[0:0]$12005 - attribute \src "libresoc.v:182966.5-182966.29" + assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185270.5-185270.29" switch \initial - attribute \src "libresoc.v:182966.9-182966.17" + attribute \src "libresoc.v:185270.9-185270.17" case 1'1 case end @@ -379324,56 +383333,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12005 1'0 + assign $1\q_int$next[0:0]$12189 1'0 case - assign $1\q_int$next[0:0]$12005 \$5 + assign $1\q_int$next[0:0]$12189 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12004 + update \q_int$next $0\q_int$next[0:0]$12188 end - connect \$9 $and$libresoc.v:182955$11994_Y - connect \$11 $or$libresoc.v:182956$11995_Y - connect \$13 $not$libresoc.v:182957$11996_Y - connect \$15 $or$libresoc.v:182958$11997_Y - connect \$1 $not$libresoc.v:182959$11998_Y - connect \$3 $and$libresoc.v:182960$11999_Y - connect \$5 $or$libresoc.v:182961$12000_Y - connect \$7 $not$libresoc.v:182962$12001_Y + connect \$9 $and$libresoc.v:185259$12178_Y + connect \$11 $or$libresoc.v:185260$12179_Y + connect \$13 $not$libresoc.v:185261$12180_Y + connect \$15 $or$libresoc.v:185262$12181_Y + connect \$1 $not$libresoc.v:185263$12182_Y + connect \$3 $and$libresoc.v:185264$12183_Y + connect \$5 $or$libresoc.v:185265$12184_Y + connect \$7 $not$libresoc.v:185266$12185_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182981.1-183039.10" +attribute \src "libresoc.v:185285.1-185343.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:182982.7-182982.20" + attribute \src "libresoc.v:185286.7-185286.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183027.3-183035.6" - wire $0\q_int$next[0:0]$12018 - attribute \src "libresoc.v:183025.3-183026.27" + attribute \src "libresoc.v:185331.3-185339.6" + wire $0\q_int$next[0:0]$12202 + attribute \src "libresoc.v:185329.3-185330.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183027.3-183035.6" - wire $1\q_int$next[0:0]$12019 - attribute \src "libresoc.v:183004.7-183004.19" + attribute \src "libresoc.v:185331.3-185339.6" + wire $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185308.7-185308.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183017.17-183017.96" - wire $and$libresoc.v:183017$12008_Y - attribute \src "libresoc.v:183022.17-183022.96" - wire $and$libresoc.v:183022$12013_Y - attribute \src "libresoc.v:183019.18-183019.94" - wire $not$libresoc.v:183019$12010_Y - attribute \src "libresoc.v:183021.17-183021.93" - wire $not$libresoc.v:183021$12012_Y - attribute \src "libresoc.v:183024.17-183024.93" - wire $not$libresoc.v:183024$12015_Y - attribute \src "libresoc.v:183018.18-183018.99" - wire $or$libresoc.v:183018$12009_Y - attribute \src "libresoc.v:183020.18-183020.100" - wire $or$libresoc.v:183020$12011_Y - attribute \src "libresoc.v:183023.17-183023.98" - wire $or$libresoc.v:183023$12014_Y + attribute \src "libresoc.v:185321.17-185321.96" + wire $and$libresoc.v:185321$12192_Y + attribute \src "libresoc.v:185326.17-185326.96" + wire $and$libresoc.v:185326$12197_Y + attribute \src "libresoc.v:185323.18-185323.94" + wire $not$libresoc.v:185323$12194_Y + attribute \src "libresoc.v:185325.17-185325.93" + wire $not$libresoc.v:185325$12196_Y + attribute \src "libresoc.v:185328.17-185328.93" + wire $not$libresoc.v:185328$12199_Y + attribute \src "libresoc.v:185322.18-185322.99" + wire $or$libresoc.v:185322$12193_Y + attribute \src "libresoc.v:185324.18-185324.100" + wire $or$libresoc.v:185324$12195_Y + attribute \src "libresoc.v:185327.17-185327.98" + wire $or$libresoc.v:185327$12198_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379390,11 +383399,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182982.7-182982.15" + attribute \src "libresoc.v:185286.7-185286.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379411,7 +383420,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183017$12008 + cell $and $and$libresoc.v:185321$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379419,10 +383428,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183017$12008_Y + connect \Y $and$libresoc.v:185321$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183022$12013 + cell $and $and$libresoc.v:185326$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379430,34 +383439,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183022$12013_Y + connect \Y $and$libresoc.v:185326$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183019$12010 + cell $not $not$libresoc.v:185323$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183019$12010_Y + connect \Y $not$libresoc.v:185323$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183021$12012 + cell $not $not$libresoc.v:185325$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183021$12012_Y + connect \Y $not$libresoc.v:185325$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183024$12015 + cell $not $not$libresoc.v:185328$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183024$12015_Y + connect \Y $not$libresoc.v:185328$12199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183018$12009 + cell $or $or$libresoc.v:185322$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379465,10 +383474,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183018$12009_Y + connect \Y $or$libresoc.v:185322$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183020$12011 + cell $or $or$libresoc.v:185324$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379476,10 +383485,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183020$12011_Y + connect \Y $or$libresoc.v:185324$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183023$12014 + cell $or $or$libresoc.v:185327$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379487,39 +383496,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183023$12014_Y + connect \Y $or$libresoc.v:185327$12198_Y end - attribute \src "libresoc.v:182982.7-182982.20" - process $proc$libresoc.v:182982$12020 + attribute \src "libresoc.v:185286.7-185286.20" + process $proc$libresoc.v:185286$12204 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183004.7-183004.19" - process $proc$libresoc.v:183004$12021 + attribute \src "libresoc.v:185308.7-185308.19" + process $proc$libresoc.v:185308$12205 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183025.3-183026.27" - process $proc$libresoc.v:183025$12016 + attribute \src "libresoc.v:185329.3-185330.27" + process $proc$libresoc.v:185329$12200 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183027.3-183035.6" - process $proc$libresoc.v:183027$12017 + attribute \src "libresoc.v:185331.3-185339.6" + process $proc$libresoc.v:185331$12201 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12018 $1\q_int$next[0:0]$12019 - attribute \src "libresoc.v:183028.5-183028.29" + assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185332.5-185332.29" switch \initial - attribute \src "libresoc.v:183028.9-183028.17" + attribute \src "libresoc.v:185332.9-185332.17" case 1'1 case end @@ -379528,56 +383537,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12019 1'0 + assign $1\q_int$next[0:0]$12203 1'0 case - assign $1\q_int$next[0:0]$12019 \$5 + assign $1\q_int$next[0:0]$12203 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12018 + update \q_int$next $0\q_int$next[0:0]$12202 end - connect \$9 $and$libresoc.v:183017$12008_Y - connect \$11 $or$libresoc.v:183018$12009_Y - connect \$13 $not$libresoc.v:183019$12010_Y - connect \$15 $or$libresoc.v:183020$12011_Y - connect \$1 $not$libresoc.v:183021$12012_Y - connect \$3 $and$libresoc.v:183022$12013_Y - connect \$5 $or$libresoc.v:183023$12014_Y - connect \$7 $not$libresoc.v:183024$12015_Y + connect \$9 $and$libresoc.v:185321$12192_Y + connect \$11 $or$libresoc.v:185322$12193_Y + connect \$13 $not$libresoc.v:185323$12194_Y + connect \$15 $or$libresoc.v:185324$12195_Y + connect \$1 $not$libresoc.v:185325$12196_Y + connect \$3 $and$libresoc.v:185326$12197_Y + connect \$5 $or$libresoc.v:185327$12198_Y + connect \$7 $not$libresoc.v:185328$12199_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183043.1-183101.10" +attribute \src "libresoc.v:185347.1-185405.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:183044.7-183044.20" + attribute \src "libresoc.v:185348.7-185348.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183089.3-183097.6" - wire $0\q_int$next[0:0]$12032 - attribute \src "libresoc.v:183087.3-183088.27" + attribute \src "libresoc.v:185393.3-185401.6" + wire $0\q_int$next[0:0]$12216 + attribute \src "libresoc.v:185391.3-185392.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183089.3-183097.6" - wire $1\q_int$next[0:0]$12033 - attribute \src "libresoc.v:183066.7-183066.19" + attribute \src "libresoc.v:185393.3-185401.6" + wire $1\q_int$next[0:0]$12217 + attribute \src "libresoc.v:185370.7-185370.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183079.17-183079.96" - wire $and$libresoc.v:183079$12022_Y - attribute \src "libresoc.v:183084.17-183084.96" - wire $and$libresoc.v:183084$12027_Y - attribute \src "libresoc.v:183081.18-183081.94" - wire $not$libresoc.v:183081$12024_Y - attribute \src "libresoc.v:183083.17-183083.93" - wire $not$libresoc.v:183083$12026_Y - attribute \src "libresoc.v:183086.17-183086.93" - wire $not$libresoc.v:183086$12029_Y - attribute \src "libresoc.v:183080.18-183080.99" - wire $or$libresoc.v:183080$12023_Y - attribute \src "libresoc.v:183082.18-183082.100" - wire $or$libresoc.v:183082$12025_Y - attribute \src "libresoc.v:183085.17-183085.98" - wire $or$libresoc.v:183085$12028_Y + attribute \src "libresoc.v:185383.17-185383.96" + wire $and$libresoc.v:185383$12206_Y + attribute \src "libresoc.v:185388.17-185388.96" + wire $and$libresoc.v:185388$12211_Y + attribute \src "libresoc.v:185385.18-185385.94" + wire $not$libresoc.v:185385$12208_Y + attribute \src "libresoc.v:185387.17-185387.93" + wire $not$libresoc.v:185387$12210_Y + attribute \src "libresoc.v:185390.17-185390.93" + wire $not$libresoc.v:185390$12213_Y + attribute \src "libresoc.v:185384.18-185384.99" + wire $or$libresoc.v:185384$12207_Y + attribute \src "libresoc.v:185386.18-185386.100" + wire $or$libresoc.v:185386$12209_Y + attribute \src "libresoc.v:185389.17-185389.98" + wire $or$libresoc.v:185389$12212_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379594,11 +383603,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183044.7-183044.15" + attribute \src "libresoc.v:185348.7-185348.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379615,7 +383624,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183079$12022 + cell $and $and$libresoc.v:185383$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379623,10 +383632,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183079$12022_Y + connect \Y $and$libresoc.v:185383$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183084$12027 + cell $and $and$libresoc.v:185388$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379634,34 +383643,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183084$12027_Y + connect \Y $and$libresoc.v:185388$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183081$12024 + cell $not $not$libresoc.v:185385$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183081$12024_Y + connect \Y $not$libresoc.v:185385$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183083$12026 + cell $not $not$libresoc.v:185387$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183083$12026_Y + connect \Y $not$libresoc.v:185387$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183086$12029 + cell $not $not$libresoc.v:185390$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183086$12029_Y + connect \Y $not$libresoc.v:185390$12213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183080$12023 + cell $or $or$libresoc.v:185384$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379669,10 +383678,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183080$12023_Y + connect \Y $or$libresoc.v:185384$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183082$12025 + cell $or $or$libresoc.v:185386$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379680,10 +383689,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183082$12025_Y + connect \Y $or$libresoc.v:185386$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183085$12028 + cell $or $or$libresoc.v:185389$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379691,39 +383700,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183085$12028_Y + connect \Y $or$libresoc.v:185389$12212_Y end - attribute \src "libresoc.v:183044.7-183044.20" - process $proc$libresoc.v:183044$12034 + attribute \src "libresoc.v:185348.7-185348.20" + process $proc$libresoc.v:185348$12218 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183066.7-183066.19" - process $proc$libresoc.v:183066$12035 + attribute \src "libresoc.v:185370.7-185370.19" + process $proc$libresoc.v:185370$12219 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183087.3-183088.27" - process $proc$libresoc.v:183087$12030 + attribute \src "libresoc.v:185391.3-185392.27" + process $proc$libresoc.v:185391$12214 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183089.3-183097.6" - process $proc$libresoc.v:183089$12031 + attribute \src "libresoc.v:185393.3-185401.6" + process $proc$libresoc.v:185393$12215 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12032 $1\q_int$next[0:0]$12033 - attribute \src "libresoc.v:183090.5-183090.29" + assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 + attribute \src "libresoc.v:185394.5-185394.29" switch \initial - attribute \src "libresoc.v:183090.9-183090.17" + attribute \src "libresoc.v:185394.9-185394.17" case 1'1 case end @@ -379732,56 +383741,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12033 1'0 + assign $1\q_int$next[0:0]$12217 1'0 case - assign $1\q_int$next[0:0]$12033 \$5 + assign $1\q_int$next[0:0]$12217 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12032 + update \q_int$next $0\q_int$next[0:0]$12216 end - connect \$9 $and$libresoc.v:183079$12022_Y - connect \$11 $or$libresoc.v:183080$12023_Y - connect \$13 $not$libresoc.v:183081$12024_Y - connect \$15 $or$libresoc.v:183082$12025_Y - connect \$1 $not$libresoc.v:183083$12026_Y - connect \$3 $and$libresoc.v:183084$12027_Y - connect \$5 $or$libresoc.v:183085$12028_Y - connect \$7 $not$libresoc.v:183086$12029_Y + connect \$9 $and$libresoc.v:185383$12206_Y + connect \$11 $or$libresoc.v:185384$12207_Y + connect \$13 $not$libresoc.v:185385$12208_Y + connect \$15 $or$libresoc.v:185386$12209_Y + connect \$1 $not$libresoc.v:185387$12210_Y + connect \$3 $and$libresoc.v:185388$12211_Y + connect \$5 $or$libresoc.v:185389$12212_Y + connect \$7 $not$libresoc.v:185390$12213_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183105.1-183163.10" +attribute \src "libresoc.v:185409.1-185467.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:183106.7-183106.20" + attribute \src "libresoc.v:185410.7-185410.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183151.3-183159.6" - wire $0\q_int$next[0:0]$12046 - attribute \src "libresoc.v:183149.3-183150.27" + attribute \src "libresoc.v:185455.3-185463.6" + wire $0\q_int$next[0:0]$12230 + attribute \src "libresoc.v:185453.3-185454.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183151.3-183159.6" - wire $1\q_int$next[0:0]$12047 - attribute \src "libresoc.v:183128.7-183128.19" + attribute \src "libresoc.v:185455.3-185463.6" + wire $1\q_int$next[0:0]$12231 + attribute \src "libresoc.v:185432.7-185432.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183141.17-183141.96" - wire $and$libresoc.v:183141$12036_Y - attribute \src "libresoc.v:183146.17-183146.96" - wire $and$libresoc.v:183146$12041_Y - attribute \src "libresoc.v:183143.18-183143.94" - wire $not$libresoc.v:183143$12038_Y - attribute \src "libresoc.v:183145.17-183145.93" - wire $not$libresoc.v:183145$12040_Y - attribute \src "libresoc.v:183148.17-183148.93" - wire $not$libresoc.v:183148$12043_Y - attribute \src "libresoc.v:183142.18-183142.99" - wire $or$libresoc.v:183142$12037_Y - attribute \src "libresoc.v:183144.18-183144.100" - wire $or$libresoc.v:183144$12039_Y - attribute \src "libresoc.v:183147.17-183147.98" - wire $or$libresoc.v:183147$12042_Y + attribute \src "libresoc.v:185445.17-185445.96" + wire $and$libresoc.v:185445$12220_Y + attribute \src "libresoc.v:185450.17-185450.96" + wire $and$libresoc.v:185450$12225_Y + attribute \src "libresoc.v:185447.18-185447.94" + wire $not$libresoc.v:185447$12222_Y + attribute \src "libresoc.v:185449.17-185449.93" + wire $not$libresoc.v:185449$12224_Y + attribute \src "libresoc.v:185452.17-185452.93" + wire $not$libresoc.v:185452$12227_Y + attribute \src "libresoc.v:185446.18-185446.99" + wire $or$libresoc.v:185446$12221_Y + attribute \src "libresoc.v:185448.18-185448.100" + wire $or$libresoc.v:185448$12223_Y + attribute \src "libresoc.v:185451.17-185451.98" + wire $or$libresoc.v:185451$12226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379798,11 +383807,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183106.7-183106.15" + attribute \src "libresoc.v:185410.7-185410.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379819,7 +383828,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183141$12036 + cell $and $and$libresoc.v:185445$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379827,10 +383836,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183141$12036_Y + connect \Y $and$libresoc.v:185445$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183146$12041 + cell $and $and$libresoc.v:185450$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379838,34 +383847,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183146$12041_Y + connect \Y $and$libresoc.v:185450$12225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183143$12038 + cell $not $not$libresoc.v:185447$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183143$12038_Y + connect \Y $not$libresoc.v:185447$12222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183145$12040 + cell $not $not$libresoc.v:185449$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183145$12040_Y + connect \Y $not$libresoc.v:185449$12224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183148$12043 + cell $not $not$libresoc.v:185452$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183148$12043_Y + connect \Y $not$libresoc.v:185452$12227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183142$12037 + cell $or $or$libresoc.v:185446$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379873,10 +383882,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183142$12037_Y + connect \Y $or$libresoc.v:185446$12221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183144$12039 + cell $or $or$libresoc.v:185448$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379884,10 +383893,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183144$12039_Y + connect \Y $or$libresoc.v:185448$12223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183147$12042 + cell $or $or$libresoc.v:185451$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379895,39 +383904,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183147$12042_Y + connect \Y $or$libresoc.v:185451$12226_Y end - attribute \src "libresoc.v:183106.7-183106.20" - process $proc$libresoc.v:183106$12048 + attribute \src "libresoc.v:185410.7-185410.20" + process $proc$libresoc.v:185410$12232 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183128.7-183128.19" - process $proc$libresoc.v:183128$12049 + attribute \src "libresoc.v:185432.7-185432.19" + process $proc$libresoc.v:185432$12233 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183149.3-183150.27" - process $proc$libresoc.v:183149$12044 + attribute \src "libresoc.v:185453.3-185454.27" + process $proc$libresoc.v:185453$12228 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183151.3-183159.6" - process $proc$libresoc.v:183151$12045 + attribute \src "libresoc.v:185455.3-185463.6" + process $proc$libresoc.v:185455$12229 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12046 $1\q_int$next[0:0]$12047 - attribute \src "libresoc.v:183152.5-183152.29" + assign $0\q_int$next[0:0]$12230 $1\q_int$next[0:0]$12231 + attribute \src "libresoc.v:185456.5-185456.29" switch \initial - attribute \src "libresoc.v:183152.9-183152.17" + attribute \src "libresoc.v:185456.9-185456.17" case 1'1 case end @@ -379936,150 +383945,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12047 1'0 + assign $1\q_int$next[0:0]$12231 1'0 case - assign $1\q_int$next[0:0]$12047 \$5 + assign $1\q_int$next[0:0]$12231 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12046 + update \q_int$next $0\q_int$next[0:0]$12230 end - connect \$9 $and$libresoc.v:183141$12036_Y - connect \$11 $or$libresoc.v:183142$12037_Y - connect \$13 $not$libresoc.v:183143$12038_Y - connect \$15 $or$libresoc.v:183144$12039_Y - connect \$1 $not$libresoc.v:183145$12040_Y - connect \$3 $and$libresoc.v:183146$12041_Y - connect \$5 $or$libresoc.v:183147$12042_Y - connect \$7 $not$libresoc.v:183148$12043_Y + connect \$9 $and$libresoc.v:185445$12220_Y + connect \$11 $or$libresoc.v:185446$12221_Y + connect \$13 $not$libresoc.v:185447$12222_Y + connect \$15 $or$libresoc.v:185448$12223_Y + connect \$1 $not$libresoc.v:185449$12224_Y + connect \$3 $and$libresoc.v:185450$12225_Y + connect \$5 $or$libresoc.v:185451$12226_Y + connect \$7 $not$libresoc.v:185452$12227_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183167.1-183518.10" +attribute \src "libresoc.v:185471.1-185822.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:183436.3-183445.6" + attribute \src "libresoc.v:185740.3-185749.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:183368.3-183382.6" + attribute \src "libresoc.v:185672.3-185686.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:183168.7-183168.20" + attribute \src "libresoc.v:185472.7-185472.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 7 $0\mb$8[6:0]$12097 - attribute \src "libresoc.v:183492.3-183506.6" - wire width 7 $0\me$13[6:0]$12102 - attribute \src "libresoc.v:183393.3-183404.6" + attribute \src "libresoc.v:185762.3-185795.6" + wire width 7 $0\mb$8[6:0]$12281 + attribute \src "libresoc.v:185796.3-185810.6" + wire width 7 $0\me$13[6:0]$12286 + attribute \src "libresoc.v:185697.3-185708.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:183405.3-183416.6" + attribute \src "libresoc.v:185709.3-185720.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:183417.3-183435.6" + attribute \src "libresoc.v:185721.3-185739.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:183383.3-183392.6" + attribute \src "libresoc.v:185687.3-185696.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:183446.3-183457.6" + attribute \src "libresoc.v:185750.3-185761.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:183436.3-183445.6" + attribute \src "libresoc.v:185740.3-185749.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:183368.3-183382.6" + attribute \src "libresoc.v:185672.3-185686.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 7 $1\mb$8[6:0]$12098 - attribute \src "libresoc.v:183492.3-183506.6" - wire width 7 $1\me$13[6:0]$12103 - attribute \src "libresoc.v:183393.3-183404.6" + attribute \src "libresoc.v:185762.3-185795.6" + wire width 7 $1\mb$8[6:0]$12282 + attribute \src "libresoc.v:185796.3-185810.6" + wire width 7 $1\me$13[6:0]$12287 + attribute \src "libresoc.v:185697.3-185708.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:183405.3-183416.6" + attribute \src "libresoc.v:185709.3-185720.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:183417.3-183435.6" + attribute \src "libresoc.v:185721.3-185739.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:183383.3-183392.6" + attribute \src "libresoc.v:185687.3-185696.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:183446.3-183457.6" + attribute \src "libresoc.v:185750.3-185761.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 2 $2\mb$8[6:5]$12099 - attribute \src "libresoc.v:183458.3-183491.6" - wire width 2 $3\mb$8[6:5]$12100 - attribute \src "libresoc.v:183319.18-183319.118" - wire $and$libresoc.v:183319$12053_Y - attribute \src "libresoc.v:183321.18-183321.114" - wire $and$libresoc.v:183321$12055_Y - attribute \src "libresoc.v:183330.18-183330.113" - wire $and$libresoc.v:183330$12064_Y - attribute \src "libresoc.v:183332.18-183332.114" - wire $and$libresoc.v:183332$12066_Y - attribute \src "libresoc.v:183334.18-183334.114" - wire $and$libresoc.v:183334$12068_Y - attribute \src "libresoc.v:183335.18-183335.103" - wire width 64 $and$libresoc.v:183335$12069_Y - attribute \src "libresoc.v:183336.18-183336.106" - wire width 64 $and$libresoc.v:183336$12070_Y - attribute \src "libresoc.v:183338.18-183338.103" - wire width 64 $and$libresoc.v:183338$12072_Y - attribute \src "libresoc.v:183340.18-183340.105" - wire width 64 $and$libresoc.v:183340$12074_Y - attribute \src "libresoc.v:183343.18-183343.106" - wire width 64 $and$libresoc.v:183343$12077_Y - attribute \src "libresoc.v:183346.18-183346.105" - wire width 64 $and$libresoc.v:183346$12080_Y - attribute \src "libresoc.v:183348.17-183348.109" - wire $and$libresoc.v:183348$12082_Y - attribute \src "libresoc.v:183349.18-183349.104" - wire width 64 $and$libresoc.v:183349$12083_Y - attribute \src "libresoc.v:183353.18-183353.105" - wire width 64 $and$libresoc.v:183353$12087_Y - attribute \src "libresoc.v:183317.17-183317.98" - wire width 7 $extend$libresoc.v:183317$12050_Y - attribute \src "libresoc.v:183333.18-183333.122" - wire $gt$libresoc.v:183333$12067_Y - attribute \src "libresoc.v:183323.18-183323.111" - wire $le$libresoc.v:183323$12057_Y - attribute \src "libresoc.v:183325.18-183325.111" - wire $le$libresoc.v:183325$12059_Y - attribute \src "libresoc.v:183326.17-183326.117" - wire width 7 $neg$libresoc.v:183326$12060_Y - attribute \src "libresoc.v:183318.18-183318.103" - wire $not$libresoc.v:183318$12052_Y - attribute \src "libresoc.v:183320.18-183320.108" - wire $not$libresoc.v:183320$12054_Y - attribute \src "libresoc.v:183322.18-183322.105" - wire width 6 $not$libresoc.v:183322$12056_Y - attribute \src "libresoc.v:183328.18-183328.112" - wire width 64 $not$libresoc.v:183328$12062_Y - attribute \src "libresoc.v:183329.18-183329.109" - wire $not$libresoc.v:183329$12063_Y - attribute \src "libresoc.v:183337.17-183337.105" - wire $not$libresoc.v:183337$12071_Y - attribute \src "libresoc.v:183339.18-183339.102" - wire width 64 $not$libresoc.v:183339$12073_Y - attribute \src "libresoc.v:183345.18-183345.102" - wire width 64 $not$libresoc.v:183345$12079_Y - attribute \src "libresoc.v:183350.18-183350.100" - wire width 64 $not$libresoc.v:183350$12084_Y - attribute \src "libresoc.v:183352.18-183352.100" - wire width 64 $not$libresoc.v:183352$12086_Y - attribute \src "libresoc.v:183331.18-183331.115" - wire $or$libresoc.v:183331$12065_Y - attribute \src "libresoc.v:183341.18-183341.108" - wire width 64 $or$libresoc.v:183341$12075_Y - attribute \src "libresoc.v:183342.18-183342.103" - wire width 64 $or$libresoc.v:183342$12076_Y - attribute \src "libresoc.v:183344.18-183344.103" - wire width 64 $or$libresoc.v:183344$12078_Y - attribute \src "libresoc.v:183347.18-183347.108" - wire width 64 $or$libresoc.v:183347$12081_Y - attribute \src "libresoc.v:183351.18-183351.106" - wire width 64 $or$libresoc.v:183351$12085_Y - attribute \src "libresoc.v:183317.17-183317.98" - wire width 7 $pos$libresoc.v:183317$12051_Y - attribute \src "libresoc.v:183354.18-183354.102" - wire $reduce_or$libresoc.v:183354$12088_Y - attribute \src "libresoc.v:183324.18-183324.109" - wire width 8 $sub$libresoc.v:183324$12058_Y - attribute \src "libresoc.v:183327.18-183327.110" - wire width 8 $sub$libresoc.v:183327$12061_Y + attribute \src "libresoc.v:185762.3-185795.6" + wire width 2 $2\mb$8[6:5]$12283 + attribute \src "libresoc.v:185762.3-185795.6" + wire width 2 $3\mb$8[6:5]$12284 + attribute \src "libresoc.v:185623.18-185623.118" + wire $and$libresoc.v:185623$12237_Y + attribute \src "libresoc.v:185625.18-185625.114" + wire $and$libresoc.v:185625$12239_Y + attribute \src "libresoc.v:185634.18-185634.113" + wire $and$libresoc.v:185634$12248_Y + attribute \src "libresoc.v:185636.18-185636.114" + wire $and$libresoc.v:185636$12250_Y + attribute \src "libresoc.v:185638.18-185638.114" + wire $and$libresoc.v:185638$12252_Y + attribute \src "libresoc.v:185639.18-185639.103" + wire width 64 $and$libresoc.v:185639$12253_Y + attribute \src "libresoc.v:185640.18-185640.106" + wire width 64 $and$libresoc.v:185640$12254_Y + attribute \src "libresoc.v:185642.18-185642.103" + wire width 64 $and$libresoc.v:185642$12256_Y + attribute \src "libresoc.v:185644.18-185644.105" + wire width 64 $and$libresoc.v:185644$12258_Y + attribute \src "libresoc.v:185647.18-185647.106" + wire width 64 $and$libresoc.v:185647$12261_Y + attribute \src "libresoc.v:185650.18-185650.105" + wire width 64 $and$libresoc.v:185650$12264_Y + attribute \src "libresoc.v:185652.17-185652.109" + wire $and$libresoc.v:185652$12266_Y + attribute \src "libresoc.v:185653.18-185653.104" + wire width 64 $and$libresoc.v:185653$12267_Y + attribute \src "libresoc.v:185657.18-185657.105" + wire width 64 $and$libresoc.v:185657$12271_Y + attribute \src "libresoc.v:185621.17-185621.98" + wire width 7 $extend$libresoc.v:185621$12234_Y + attribute \src "libresoc.v:185637.18-185637.122" + wire $gt$libresoc.v:185637$12251_Y + attribute \src "libresoc.v:185627.18-185627.111" + wire $le$libresoc.v:185627$12241_Y + attribute \src "libresoc.v:185629.18-185629.111" + wire $le$libresoc.v:185629$12243_Y + attribute \src "libresoc.v:185630.17-185630.117" + wire width 7 $neg$libresoc.v:185630$12244_Y + attribute \src "libresoc.v:185622.18-185622.103" + wire $not$libresoc.v:185622$12236_Y + attribute \src "libresoc.v:185624.18-185624.108" + wire $not$libresoc.v:185624$12238_Y + attribute \src "libresoc.v:185626.18-185626.105" + wire width 6 $not$libresoc.v:185626$12240_Y + attribute \src "libresoc.v:185632.18-185632.112" + wire width 64 $not$libresoc.v:185632$12246_Y + attribute \src "libresoc.v:185633.18-185633.109" + wire $not$libresoc.v:185633$12247_Y + attribute \src "libresoc.v:185641.17-185641.105" + wire $not$libresoc.v:185641$12255_Y + attribute \src "libresoc.v:185643.18-185643.102" + wire width 64 $not$libresoc.v:185643$12257_Y + attribute \src "libresoc.v:185649.18-185649.102" + wire width 64 $not$libresoc.v:185649$12263_Y + attribute \src "libresoc.v:185654.18-185654.100" + wire width 64 $not$libresoc.v:185654$12268_Y + attribute \src "libresoc.v:185656.18-185656.100" + wire width 64 $not$libresoc.v:185656$12270_Y + attribute \src "libresoc.v:185635.18-185635.115" + wire $or$libresoc.v:185635$12249_Y + attribute \src "libresoc.v:185645.18-185645.108" + wire width 64 $or$libresoc.v:185645$12259_Y + attribute \src "libresoc.v:185646.18-185646.103" + wire width 64 $or$libresoc.v:185646$12260_Y + attribute \src "libresoc.v:185648.18-185648.103" + wire width 64 $or$libresoc.v:185648$12262_Y + attribute \src "libresoc.v:185651.18-185651.108" + wire width 64 $or$libresoc.v:185651$12265_Y + attribute \src "libresoc.v:185655.18-185655.106" + wire width 64 $or$libresoc.v:185655$12269_Y + attribute \src "libresoc.v:185621.17-185621.98" + wire width 7 $pos$libresoc.v:185621$12235_Y + attribute \src "libresoc.v:185658.18-185658.102" + wire $reduce_or$libresoc.v:185658$12272_Y + attribute \src "libresoc.v:185628.18-185628.109" + wire width 8 $sub$libresoc.v:185628$12242_Y + attribute \src "libresoc.v:185631.18-185631.110" + wire width 8 $sub$libresoc.v:185631$12245_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -380172,7 +384181,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:183168.7-183168.15" + attribute \src "libresoc.v:185472.7-185472.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -380229,7 +384238,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:183319$12053 + cell $and $and$libresoc.v:185623$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380237,10 +384246,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:183319$12053_Y + connect \Y $and$libresoc.v:185623$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:183321$12055 + cell $and $and$libresoc.v:185625$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380248,10 +384257,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:183321$12055_Y + connect \Y $and$libresoc.v:185625$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:183330$12064 + cell $and $and$libresoc.v:185634$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380259,10 +384268,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:183330$12064_Y + connect \Y $and$libresoc.v:185634$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:183332$12066 + cell $and $and$libresoc.v:185636$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380270,10 +384279,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:183332$12066_Y + connect \Y $and$libresoc.v:185636$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:183334$12068 + cell $and $and$libresoc.v:185638$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380281,10 +384290,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:183334$12068_Y + connect \Y $and$libresoc.v:185638$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183335$12069 + cell $and $and$libresoc.v:185639$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380292,10 +384301,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:183335$12069_Y + connect \Y $and$libresoc.v:185639$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183336$12070 + cell $and $and$libresoc.v:185640$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380303,10 +384312,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:183336$12070_Y + connect \Y $and$libresoc.v:185640$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183338$12072 + cell $and $and$libresoc.v:185642$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380314,10 +384323,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:183338$12072_Y + connect \Y $and$libresoc.v:185642$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183340$12074 + cell $and $and$libresoc.v:185644$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380325,10 +384334,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:183340$12074_Y + connect \Y $and$libresoc.v:185644$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:183343$12077 + cell $and $and$libresoc.v:185647$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380336,10 +384345,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:183343$12077_Y + connect \Y $and$libresoc.v:185647$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:183346$12080 + cell $and $and$libresoc.v:185650$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380347,10 +384356,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:183346$12080_Y + connect \Y $and$libresoc.v:185650$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:183348$12082 + cell $and $and$libresoc.v:185652$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380358,10 +384367,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:183348$12082_Y + connect \Y $and$libresoc.v:185652$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:183349$12083 + cell $and $and$libresoc.v:185653$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380369,10 +384378,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:183349$12083_Y + connect \Y $and$libresoc.v:185653$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:183353$12087 + cell $and $and$libresoc.v:185657$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380380,18 +384389,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:183353$12087_Y + connect \Y $and$libresoc.v:185657$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:183317$12050 + cell $pos $extend$libresoc.v:185621$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:183317$12050_Y + connect \Y $extend$libresoc.v:185621$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:183333$12067 + cell $gt $gt$libresoc.v:185637$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380399,10 +384408,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:183333$12067_Y + connect \Y $gt$libresoc.v:185637$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:183323$12057 + cell $le $le$libresoc.v:185627$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380410,10 +384419,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:183323$12057_Y + connect \Y $le$libresoc.v:185627$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:183325$12059 + cell $le $le$libresoc.v:185629$12243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380421,98 +384430,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:183325$12059_Y + connect \Y $le$libresoc.v:185629$12243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:183326$12060 + cell $neg $neg$libresoc.v:185630$12244 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:183326$12060_Y + connect \Y $neg$libresoc.v:185630$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:183318$12052 + cell $not $not$libresoc.v:185622$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:183318$12052_Y + connect \Y $not$libresoc.v:185622$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:183320$12054 + cell $not $not$libresoc.v:185624$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:183320$12054_Y + connect \Y $not$libresoc.v:185624$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:183322$12056 + cell $not $not$libresoc.v:185626$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:183322$12056_Y + connect \Y $not$libresoc.v:185626$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:183328$12062 + cell $not $not$libresoc.v:185632$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:183328$12062_Y + connect \Y $not$libresoc.v:185632$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:183329$12063 + cell $not $not$libresoc.v:185633$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:183329$12063_Y + connect \Y $not$libresoc.v:185633$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:183337$12071 + cell $not $not$libresoc.v:185641$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:183337$12071_Y + connect \Y $not$libresoc.v:185641$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:183339$12073 + cell $not $not$libresoc.v:185643$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:183339$12073_Y + connect \Y $not$libresoc.v:185643$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:183345$12079 + cell $not $not$libresoc.v:185649$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:183345$12079_Y + connect \Y $not$libresoc.v:185649$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:183350$12084 + cell $not $not$libresoc.v:185654$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:183350$12084_Y + connect \Y $not$libresoc.v:185654$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:183352$12086 + cell $not $not$libresoc.v:185656$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:183352$12086_Y + connect \Y $not$libresoc.v:185656$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:183331$12065 + cell $or $or$libresoc.v:185635$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380520,10 +384529,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:183331$12065_Y + connect \Y $or$libresoc.v:185635$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:183341$12075 + cell $or $or$libresoc.v:185645$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380531,10 +384540,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:183341$12075_Y + connect \Y $or$libresoc.v:185645$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183342$12076 + cell $or $or$libresoc.v:185646$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380542,10 +384551,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:183342$12076_Y + connect \Y $or$libresoc.v:185646$12260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183344$12078 + cell $or $or$libresoc.v:185648$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380553,10 +384562,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:183344$12078_Y + connect \Y $or$libresoc.v:185648$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183347$12081 + cell $or $or$libresoc.v:185651$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380564,10 +384573,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:183347$12081_Y + connect \Y $or$libresoc.v:185651$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:183351$12085 + cell $or $or$libresoc.v:185655$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380575,26 +384584,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:183351$12085_Y + connect \Y $or$libresoc.v:185655$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:183317$12051 + cell $pos $pos$libresoc.v:185621$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:183317$12050_Y - connect \Y $pos$libresoc.v:183317$12051_Y + connect \A $extend$libresoc.v:185621$12234_Y + connect \Y $pos$libresoc.v:185621$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:183354$12088 + cell $reduce_or $reduce_or$libresoc.v:185658$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:183354$12088_Y + connect \Y $reduce_or$libresoc.v:185658$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:183324$12058 + cell $sub $sub$libresoc.v:185628$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380602,10 +384611,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:183324$12058_Y + connect \Y $sub$libresoc.v:185628$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:183327$12061 + cell $sub $sub$libresoc.v:185631$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380613,42 +384622,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:183327$12061_Y + connect \Y $sub$libresoc.v:185631$12245_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:183355.13-183358.4" + attribute \src "libresoc.v:185659.13-185662.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:183359.14-183362.4" + attribute \src "libresoc.v:185663.14-185666.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:183363.8-183367.4" + attribute \src "libresoc.v:185667.8-185671.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:183168.7-183168.20" - process $proc$libresoc.v:183168$12104 + attribute \src "libresoc.v:185472.7-185472.20" + process $proc$libresoc.v:185472$12288 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183368.3-183382.6" - process $proc$libresoc.v:183368$12089 + attribute \src "libresoc.v:185672.3-185686.6" + process $proc$libresoc.v:185672$12273 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:183369.5-183369.29" + attribute \src "libresoc.v:185673.5-185673.29" switch \initial - attribute \src "libresoc.v:183369.9-183369.17" + attribute \src "libresoc.v:185673.9-185673.17" case 1'1 case end @@ -380670,14 +384679,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:183383.3-183392.6" - process $proc$libresoc.v:183383$12090 + attribute \src "libresoc.v:185687.3-185696.6" + process $proc$libresoc.v:185687$12274 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:183384.5-183384.29" + attribute \src "libresoc.v:185688.5-185688.29" switch \initial - attribute \src "libresoc.v:183384.9-183384.17" + attribute \src "libresoc.v:185688.9-185688.17" case 1'1 case end @@ -380693,13 +384702,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:183393.3-183404.6" - process $proc$libresoc.v:183393$12091 + attribute \src "libresoc.v:185697.3-185708.6" + process $proc$libresoc.v:185697$12275 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:183394.5-183394.29" + attribute \src "libresoc.v:185698.5-185698.29" switch \initial - attribute \src "libresoc.v:183394.9-183394.17" + attribute \src "libresoc.v:185698.9-185698.17" case 1'1 case end @@ -380717,13 +384726,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:183405.3-183416.6" - process $proc$libresoc.v:183405$12092 + attribute \src "libresoc.v:185709.3-185720.6" + process $proc$libresoc.v:185709$12276 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:183406.5-183406.29" + attribute \src "libresoc.v:185710.5-185710.29" switch \initial - attribute \src "libresoc.v:183406.9-183406.17" + attribute \src "libresoc.v:185710.9-185710.17" case 1'1 case end @@ -380741,14 +384750,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:183417.3-183435.6" - process $proc$libresoc.v:183417$12093 + attribute \src "libresoc.v:185721.3-185739.6" + process $proc$libresoc.v:185721$12277 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:183418.5-183418.29" + attribute \src "libresoc.v:185722.5-185722.29" switch \initial - attribute \src "libresoc.v:183418.9-183418.17" + attribute \src "libresoc.v:185722.9-185722.17" case 1'1 case end @@ -380776,14 +384785,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:183436.3-183445.6" - process $proc$libresoc.v:183436$12094 + attribute \src "libresoc.v:185740.3-185749.6" + process $proc$libresoc.v:185740$12278 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:183437.5-183437.29" + attribute \src "libresoc.v:185741.5-185741.29" switch \initial - attribute \src "libresoc.v:183437.9-183437.17" + attribute \src "libresoc.v:185741.9-185741.17" case 1'1 case end @@ -380799,13 +384808,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:183446.3-183457.6" - process $proc$libresoc.v:183446$12095 + attribute \src "libresoc.v:185750.3-185761.6" + process $proc$libresoc.v:185750$12279 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:183447.5-183447.29" + attribute \src "libresoc.v:185751.5-185751.29" switch \initial - attribute \src "libresoc.v:183447.9-183447.17" + attribute \src "libresoc.v:185751.9-185751.17" case 1'1 case end @@ -380823,13 +384832,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:183458.3-183491.6" - process $proc$libresoc.v:183458$12096 + attribute \src "libresoc.v:185762.3-185795.6" + process $proc$libresoc.v:185762$12280 assign { } { } - assign $0\mb$8[6:0]$12097 $1\mb$8[6:0]$12098 - attribute \src "libresoc.v:183459.5-183459.29" + assign $0\mb$8[6:0]$12281 $1\mb$8[6:0]$12282 + attribute \src "libresoc.v:185763.5-185763.29" switch \initial - attribute \src "libresoc.v:183459.9-183459.17" + attribute \src "libresoc.v:185763.9-185763.17" case 1'1 case end @@ -380838,48 +384847,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12098 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12098 [6:5] $2\mb$8[6:5]$12099 + assign $1\mb$8[6:0]$12282 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12282 [6:5] $2\mb$8[6:5]$12283 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12099 2'01 + assign $2\mb$8[6:5]$12283 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12099 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12283 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12098 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12098 [6:5] $3\mb$8[6:5]$12100 + assign $1\mb$8[6:0]$12282 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12282 [6:5] $3\mb$8[6:5]$12284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12100 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12284 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12100 \sh [6:5] + assign $3\mb$8[6:5]$12284 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12098 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12282 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12097 + update \mb$8 $0\mb$8[6:0]$12281 end - attribute \src "libresoc.v:183492.3-183506.6" - process $proc$libresoc.v:183492$12101 + attribute \src "libresoc.v:185796.3-185810.6" + process $proc$libresoc.v:185796$12285 assign { } { } - assign $0\me$13[6:0]$12102 $1\me$13[6:0]$12103 - attribute \src "libresoc.v:183493.5-183493.29" + assign $0\me$13[6:0]$12286 $1\me$13[6:0]$12287 + attribute \src "libresoc.v:185797.5-185797.29" switch \initial - attribute \src "libresoc.v:183493.9-183493.17" + attribute \src "libresoc.v:185797.9-185797.17" case 1'1 case end @@ -380888,57 +384897,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12103 { 2'01 \me } + assign $1\me$13[6:0]$12287 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12103 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12103 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12102 - end - connect \$9 $pos$libresoc.v:183317$12051_Y - connect \$11 $not$libresoc.v:183318$12052_Y - connect \$14 $and$libresoc.v:183319$12053_Y - connect \$16 $not$libresoc.v:183320$12054_Y - connect \$18 $and$libresoc.v:183321$12055_Y - connect \$20 $not$libresoc.v:183322$12056_Y - connect \$22 $le$libresoc.v:183323$12057_Y - connect \$25 $sub$libresoc.v:183324$12058_Y - connect \$27 $le$libresoc.v:183325$12059_Y - connect \$2 $neg$libresoc.v:183326$12060_Y - connect \$30 $sub$libresoc.v:183327$12061_Y - connect \$32 $not$libresoc.v:183328$12062_Y - connect \$34 $not$libresoc.v:183329$12063_Y - connect \$36 $and$libresoc.v:183330$12064_Y - connect \$38 $or$libresoc.v:183331$12065_Y - connect \$40 $and$libresoc.v:183332$12066_Y - connect \$42 $gt$libresoc.v:183333$12067_Y - connect \$44 $and$libresoc.v:183334$12068_Y - connect \$46 $and$libresoc.v:183335$12069_Y - connect \$48 $and$libresoc.v:183336$12070_Y - connect \$4 $not$libresoc.v:183337$12071_Y - connect \$51 $and$libresoc.v:183338$12072_Y - connect \$50 $not$libresoc.v:183339$12073_Y - connect \$54 $and$libresoc.v:183340$12074_Y - connect \$56 $or$libresoc.v:183341$12075_Y - connect \$58 $or$libresoc.v:183342$12076_Y - connect \$60 $and$libresoc.v:183343$12077_Y - connect \$63 $or$libresoc.v:183344$12078_Y - connect \$62 $not$libresoc.v:183345$12079_Y - connect \$66 $and$libresoc.v:183346$12080_Y - connect \$68 $or$libresoc.v:183347$12081_Y - connect \$6 $and$libresoc.v:183348$12082_Y - connect \$70 $and$libresoc.v:183349$12083_Y - connect \$72 $not$libresoc.v:183350$12084_Y - connect \$74 $or$libresoc.v:183351$12085_Y - connect \$77 $not$libresoc.v:183352$12086_Y - connect \$79 $and$libresoc.v:183353$12087_Y - connect \$76 $reduce_or$libresoc.v:183354$12088_Y + assign $1\me$13[6:0]$12287 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12287 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12286 + end + connect \$9 $pos$libresoc.v:185621$12235_Y + connect \$11 $not$libresoc.v:185622$12236_Y + connect \$14 $and$libresoc.v:185623$12237_Y + connect \$16 $not$libresoc.v:185624$12238_Y + connect \$18 $and$libresoc.v:185625$12239_Y + connect \$20 $not$libresoc.v:185626$12240_Y + connect \$22 $le$libresoc.v:185627$12241_Y + connect \$25 $sub$libresoc.v:185628$12242_Y + connect \$27 $le$libresoc.v:185629$12243_Y + connect \$2 $neg$libresoc.v:185630$12244_Y + connect \$30 $sub$libresoc.v:185631$12245_Y + connect \$32 $not$libresoc.v:185632$12246_Y + connect \$34 $not$libresoc.v:185633$12247_Y + connect \$36 $and$libresoc.v:185634$12248_Y + connect \$38 $or$libresoc.v:185635$12249_Y + connect \$40 $and$libresoc.v:185636$12250_Y + connect \$42 $gt$libresoc.v:185637$12251_Y + connect \$44 $and$libresoc.v:185638$12252_Y + connect \$46 $and$libresoc.v:185639$12253_Y + connect \$48 $and$libresoc.v:185640$12254_Y + connect \$4 $not$libresoc.v:185641$12255_Y + connect \$51 $and$libresoc.v:185642$12256_Y + connect \$50 $not$libresoc.v:185643$12257_Y + connect \$54 $and$libresoc.v:185644$12258_Y + connect \$56 $or$libresoc.v:185645$12259_Y + connect \$58 $or$libresoc.v:185646$12260_Y + connect \$60 $and$libresoc.v:185647$12261_Y + connect \$63 $or$libresoc.v:185648$12262_Y + connect \$62 $not$libresoc.v:185649$12263_Y + connect \$66 $and$libresoc.v:185650$12264_Y + connect \$68 $or$libresoc.v:185651$12265_Y + connect \$6 $and$libresoc.v:185652$12266_Y + connect \$70 $and$libresoc.v:185653$12267_Y + connect \$72 $not$libresoc.v:185654$12268_Y + connect \$74 $or$libresoc.v:185655$12269_Y + connect \$77 $not$libresoc.v:185656$12270_Y + connect \$79 $and$libresoc.v:185657$12271_Y + connect \$76 $reduce_or$libresoc.v:185658$12272_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -380951,15 +384960,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:183522.1-183536.10" +attribute \src "libresoc.v:185826.1-185840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:183534.17-183534.32" - wire width 128 $shr$libresoc.v:183534$12106_Y - attribute \src "libresoc.v:183533.17-183533.100" - wire width 8 $sub$libresoc.v:183533$12105_Y + attribute \src "libresoc.v:185838.17-185838.32" + wire width 128 $shr$libresoc.v:185838$12290_Y + attribute \src "libresoc.v:185837.17-185837.100" + wire width 8 $sub$libresoc.v:185837$12289_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -380970,8 +384979,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:183534.17-183534.32" - cell $shr $shr$libresoc.v:183534$12106 + attribute \src "libresoc.v:185838.17-185838.32" + cell $shr $shr$libresoc.v:185838$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -380979,10 +384988,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:183534$12106_Y + connect \Y $shr$libresoc.v:185838$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:183533$12105 + cell $sub $sub$libresoc.v:185837$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380990,43 +384999,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:183533$12105_Y + connect \Y $sub$libresoc.v:185837$12289_Y end - connect \$2 $sub$libresoc.v:183533$12105_Y - connect \$1 $shr$libresoc.v:183534$12106_Y [63:0] + connect \$2 $sub$libresoc.v:185837$12289_Y + connect \$1 $shr$libresoc.v:185838$12290_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:183540.1-183598.10" +attribute \src "libresoc.v:185844.1-185902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:183541.7-183541.20" + attribute \src "libresoc.v:185845.7-185845.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183586.3-183594.6" - wire $0\q_int$next[0:0]$12117 - attribute \src "libresoc.v:183584.3-183585.27" + attribute \src "libresoc.v:185890.3-185898.6" + wire $0\q_int$next[0:0]$12301 + attribute \src "libresoc.v:185888.3-185889.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183586.3-183594.6" - wire $1\q_int$next[0:0]$12118 - attribute \src "libresoc.v:183563.7-183563.19" + attribute \src "libresoc.v:185890.3-185898.6" + wire $1\q_int$next[0:0]$12302 + attribute \src "libresoc.v:185867.7-185867.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183576.17-183576.96" - wire $and$libresoc.v:183576$12107_Y - attribute \src "libresoc.v:183581.17-183581.96" - wire $and$libresoc.v:183581$12112_Y - attribute \src "libresoc.v:183578.18-183578.93" - wire $not$libresoc.v:183578$12109_Y - attribute \src "libresoc.v:183580.17-183580.92" - wire $not$libresoc.v:183580$12111_Y - attribute \src "libresoc.v:183583.17-183583.92" - wire $not$libresoc.v:183583$12114_Y - attribute \src "libresoc.v:183577.18-183577.98" - wire $or$libresoc.v:183577$12108_Y - attribute \src "libresoc.v:183579.18-183579.99" - wire $or$libresoc.v:183579$12110_Y - attribute \src "libresoc.v:183582.17-183582.97" - wire $or$libresoc.v:183582$12113_Y + attribute \src "libresoc.v:185880.17-185880.96" + wire $and$libresoc.v:185880$12291_Y + attribute \src "libresoc.v:185885.17-185885.96" + wire $and$libresoc.v:185885$12296_Y + attribute \src "libresoc.v:185882.18-185882.93" + wire $not$libresoc.v:185882$12293_Y + attribute \src "libresoc.v:185884.17-185884.92" + wire $not$libresoc.v:185884$12295_Y + attribute \src "libresoc.v:185887.17-185887.92" + wire $not$libresoc.v:185887$12298_Y + attribute \src "libresoc.v:185881.18-185881.98" + wire $or$libresoc.v:185881$12292_Y + attribute \src "libresoc.v:185883.18-185883.99" + wire $or$libresoc.v:185883$12294_Y + attribute \src "libresoc.v:185886.17-185886.97" + wire $or$libresoc.v:185886$12297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381043,11 +385052,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183541.7-183541.15" + attribute \src "libresoc.v:185845.7-185845.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381064,7 +385073,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183576$12107 + cell $and $and$libresoc.v:185880$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381072,10 +385081,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183576$12107_Y + connect \Y $and$libresoc.v:185880$12291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183581$12112 + cell $and $and$libresoc.v:185885$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381083,34 +385092,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183581$12112_Y + connect \Y $and$libresoc.v:185885$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183578$12109 + cell $not $not$libresoc.v:185882$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183578$12109_Y + connect \Y $not$libresoc.v:185882$12293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183580$12111 + cell $not $not$libresoc.v:185884$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183580$12111_Y + connect \Y $not$libresoc.v:185884$12295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183583$12114 + cell $not $not$libresoc.v:185887$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183583$12114_Y + connect \Y $not$libresoc.v:185887$12298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183577$12108 + cell $or $or$libresoc.v:185881$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381118,10 +385127,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183577$12108_Y + connect \Y $or$libresoc.v:185881$12292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183579$12110 + cell $or $or$libresoc.v:185883$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381129,10 +385138,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183579$12110_Y + connect \Y $or$libresoc.v:185883$12294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183582$12113 + cell $or $or$libresoc.v:185886$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381140,39 +385149,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183582$12113_Y + connect \Y $or$libresoc.v:185886$12297_Y end - attribute \src "libresoc.v:183541.7-183541.20" - process $proc$libresoc.v:183541$12119 + attribute \src "libresoc.v:185845.7-185845.20" + process $proc$libresoc.v:185845$12303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183563.7-183563.19" - process $proc$libresoc.v:183563$12120 + attribute \src "libresoc.v:185867.7-185867.19" + process $proc$libresoc.v:185867$12304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183584.3-183585.27" - process $proc$libresoc.v:183584$12115 + attribute \src "libresoc.v:185888.3-185889.27" + process $proc$libresoc.v:185888$12299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183586.3-183594.6" - process $proc$libresoc.v:183586$12116 + attribute \src "libresoc.v:185890.3-185898.6" + process $proc$libresoc.v:185890$12300 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12117 $1\q_int$next[0:0]$12118 - attribute \src "libresoc.v:183587.5-183587.29" + assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 + attribute \src "libresoc.v:185891.5-185891.29" switch \initial - attribute \src "libresoc.v:183587.9-183587.17" + attribute \src "libresoc.v:185891.9-185891.17" case 1'1 case end @@ -381181,56 +385190,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12118 1'0 + assign $1\q_int$next[0:0]$12302 1'0 case - assign $1\q_int$next[0:0]$12118 \$5 + assign $1\q_int$next[0:0]$12302 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12117 + update \q_int$next $0\q_int$next[0:0]$12301 end - connect \$9 $and$libresoc.v:183576$12107_Y - connect \$11 $or$libresoc.v:183577$12108_Y - connect \$13 $not$libresoc.v:183578$12109_Y - connect \$15 $or$libresoc.v:183579$12110_Y - connect \$1 $not$libresoc.v:183580$12111_Y - connect \$3 $and$libresoc.v:183581$12112_Y - connect \$5 $or$libresoc.v:183582$12113_Y - connect \$7 $not$libresoc.v:183583$12114_Y + connect \$9 $and$libresoc.v:185880$12291_Y + connect \$11 $or$libresoc.v:185881$12292_Y + connect \$13 $not$libresoc.v:185882$12293_Y + connect \$15 $or$libresoc.v:185883$12294_Y + connect \$1 $not$libresoc.v:185884$12295_Y + connect \$3 $and$libresoc.v:185885$12296_Y + connect \$5 $or$libresoc.v:185886$12297_Y + connect \$7 $not$libresoc.v:185887$12298_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183602.1-183660.10" +attribute \src "libresoc.v:185906.1-185964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:183603.7-183603.20" + attribute \src "libresoc.v:185907.7-185907.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183648.3-183656.6" - wire $0\q_int$next[0:0]$12131 - attribute \src "libresoc.v:183646.3-183647.27" + attribute \src "libresoc.v:185952.3-185960.6" + wire $0\q_int$next[0:0]$12315 + attribute \src "libresoc.v:185950.3-185951.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183648.3-183656.6" - wire $1\q_int$next[0:0]$12132 - attribute \src "libresoc.v:183625.7-183625.19" + attribute \src "libresoc.v:185952.3-185960.6" + wire $1\q_int$next[0:0]$12316 + attribute \src "libresoc.v:185929.7-185929.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183638.17-183638.96" - wire $and$libresoc.v:183638$12121_Y - attribute \src "libresoc.v:183643.17-183643.96" - wire $and$libresoc.v:183643$12126_Y - attribute \src "libresoc.v:183640.18-183640.93" - wire $not$libresoc.v:183640$12123_Y - attribute \src "libresoc.v:183642.17-183642.92" - wire $not$libresoc.v:183642$12125_Y - attribute \src "libresoc.v:183645.17-183645.92" - wire $not$libresoc.v:183645$12128_Y - attribute \src "libresoc.v:183639.18-183639.98" - wire $or$libresoc.v:183639$12122_Y - attribute \src "libresoc.v:183641.18-183641.99" - wire $or$libresoc.v:183641$12124_Y - attribute \src "libresoc.v:183644.17-183644.97" - wire $or$libresoc.v:183644$12127_Y + attribute \src "libresoc.v:185942.17-185942.96" + wire $and$libresoc.v:185942$12305_Y + attribute \src "libresoc.v:185947.17-185947.96" + wire $and$libresoc.v:185947$12310_Y + attribute \src "libresoc.v:185944.18-185944.93" + wire $not$libresoc.v:185944$12307_Y + attribute \src "libresoc.v:185946.17-185946.92" + wire $not$libresoc.v:185946$12309_Y + attribute \src "libresoc.v:185949.17-185949.92" + wire $not$libresoc.v:185949$12312_Y + attribute \src "libresoc.v:185943.18-185943.98" + wire $or$libresoc.v:185943$12306_Y + attribute \src "libresoc.v:185945.18-185945.99" + wire $or$libresoc.v:185945$12308_Y + attribute \src "libresoc.v:185948.17-185948.97" + wire $or$libresoc.v:185948$12311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381247,11 +385256,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183603.7-183603.15" + attribute \src "libresoc.v:185907.7-185907.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381268,7 +385277,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183638$12121 + cell $and $and$libresoc.v:185942$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381276,10 +385285,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183638$12121_Y + connect \Y $and$libresoc.v:185942$12305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183643$12126 + cell $and $and$libresoc.v:185947$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381287,34 +385296,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183643$12126_Y + connect \Y $and$libresoc.v:185947$12310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183640$12123 + cell $not $not$libresoc.v:185944$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183640$12123_Y + connect \Y $not$libresoc.v:185944$12307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183642$12125 + cell $not $not$libresoc.v:185946$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183642$12125_Y + connect \Y $not$libresoc.v:185946$12309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183645$12128 + cell $not $not$libresoc.v:185949$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183645$12128_Y + connect \Y $not$libresoc.v:185949$12312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183639$12122 + cell $or $or$libresoc.v:185943$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381322,10 +385331,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183639$12122_Y + connect \Y $or$libresoc.v:185943$12306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183641$12124 + cell $or $or$libresoc.v:185945$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381333,10 +385342,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183641$12124_Y + connect \Y $or$libresoc.v:185945$12308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183644$12127 + cell $or $or$libresoc.v:185948$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381344,39 +385353,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183644$12127_Y + connect \Y $or$libresoc.v:185948$12311_Y end - attribute \src "libresoc.v:183603.7-183603.20" - process $proc$libresoc.v:183603$12133 + attribute \src "libresoc.v:185907.7-185907.20" + process $proc$libresoc.v:185907$12317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183625.7-183625.19" - process $proc$libresoc.v:183625$12134 + attribute \src "libresoc.v:185929.7-185929.19" + process $proc$libresoc.v:185929$12318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183646.3-183647.27" - process $proc$libresoc.v:183646$12129 + attribute \src "libresoc.v:185950.3-185951.27" + process $proc$libresoc.v:185950$12313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183648.3-183656.6" - process $proc$libresoc.v:183648$12130 + attribute \src "libresoc.v:185952.3-185960.6" + process $proc$libresoc.v:185952$12314 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12131 $1\q_int$next[0:0]$12132 - attribute \src "libresoc.v:183649.5-183649.29" + assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 + attribute \src "libresoc.v:185953.5-185953.29" switch \initial - attribute \src "libresoc.v:183649.9-183649.17" + attribute \src "libresoc.v:185953.9-185953.17" case 1'1 case end @@ -381385,56 +385394,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12132 1'0 + assign $1\q_int$next[0:0]$12316 1'0 case - assign $1\q_int$next[0:0]$12132 \$5 + assign $1\q_int$next[0:0]$12316 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12131 + update \q_int$next $0\q_int$next[0:0]$12315 end - connect \$9 $and$libresoc.v:183638$12121_Y - connect \$11 $or$libresoc.v:183639$12122_Y - connect \$13 $not$libresoc.v:183640$12123_Y - connect \$15 $or$libresoc.v:183641$12124_Y - connect \$1 $not$libresoc.v:183642$12125_Y - connect \$3 $and$libresoc.v:183643$12126_Y - connect \$5 $or$libresoc.v:183644$12127_Y - connect \$7 $not$libresoc.v:183645$12128_Y + connect \$9 $and$libresoc.v:185942$12305_Y + connect \$11 $or$libresoc.v:185943$12306_Y + connect \$13 $not$libresoc.v:185944$12307_Y + connect \$15 $or$libresoc.v:185945$12308_Y + connect \$1 $not$libresoc.v:185946$12309_Y + connect \$3 $and$libresoc.v:185947$12310_Y + connect \$5 $or$libresoc.v:185948$12311_Y + connect \$7 $not$libresoc.v:185949$12312_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183664.1-183722.10" +attribute \src "libresoc.v:185968.1-186026.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:183665.7-183665.20" + attribute \src "libresoc.v:185969.7-185969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183710.3-183718.6" - wire $0\q_int$next[0:0]$12145 - attribute \src "libresoc.v:183708.3-183709.27" + attribute \src "libresoc.v:186014.3-186022.6" + wire $0\q_int$next[0:0]$12329 + attribute \src "libresoc.v:186012.3-186013.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183710.3-183718.6" - wire $1\q_int$next[0:0]$12146 - attribute \src "libresoc.v:183687.7-183687.19" + attribute \src "libresoc.v:186014.3-186022.6" + wire $1\q_int$next[0:0]$12330 + attribute \src "libresoc.v:185991.7-185991.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183700.17-183700.96" - wire $and$libresoc.v:183700$12135_Y - attribute \src "libresoc.v:183705.17-183705.96" - wire $and$libresoc.v:183705$12140_Y - attribute \src "libresoc.v:183702.18-183702.93" - wire $not$libresoc.v:183702$12137_Y - attribute \src "libresoc.v:183704.17-183704.92" - wire $not$libresoc.v:183704$12139_Y - attribute \src "libresoc.v:183707.17-183707.92" - wire $not$libresoc.v:183707$12142_Y - attribute \src "libresoc.v:183701.18-183701.98" - wire $or$libresoc.v:183701$12136_Y - attribute \src "libresoc.v:183703.18-183703.99" - wire $or$libresoc.v:183703$12138_Y - attribute \src "libresoc.v:183706.17-183706.97" - wire $or$libresoc.v:183706$12141_Y + attribute \src "libresoc.v:186004.17-186004.96" + wire $and$libresoc.v:186004$12319_Y + attribute \src "libresoc.v:186009.17-186009.96" + wire $and$libresoc.v:186009$12324_Y + attribute \src "libresoc.v:186006.18-186006.93" + wire $not$libresoc.v:186006$12321_Y + attribute \src "libresoc.v:186008.17-186008.92" + wire $not$libresoc.v:186008$12323_Y + attribute \src "libresoc.v:186011.17-186011.92" + wire $not$libresoc.v:186011$12326_Y + attribute \src "libresoc.v:186005.18-186005.98" + wire $or$libresoc.v:186005$12320_Y + attribute \src "libresoc.v:186007.18-186007.99" + wire $or$libresoc.v:186007$12322_Y + attribute \src "libresoc.v:186010.17-186010.97" + wire $or$libresoc.v:186010$12325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381451,11 +385460,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183665.7-183665.15" + attribute \src "libresoc.v:185969.7-185969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381472,7 +385481,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183700$12135 + cell $and $and$libresoc.v:186004$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381480,10 +385489,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183700$12135_Y + connect \Y $and$libresoc.v:186004$12319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183705$12140 + cell $and $and$libresoc.v:186009$12324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381491,34 +385500,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183705$12140_Y + connect \Y $and$libresoc.v:186009$12324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183702$12137 + cell $not $not$libresoc.v:186006$12321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183702$12137_Y + connect \Y $not$libresoc.v:186006$12321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183704$12139 + cell $not $not$libresoc.v:186008$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183704$12139_Y + connect \Y $not$libresoc.v:186008$12323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183707$12142 + cell $not $not$libresoc.v:186011$12326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183707$12142_Y + connect \Y $not$libresoc.v:186011$12326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183701$12136 + cell $or $or$libresoc.v:186005$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381526,10 +385535,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183701$12136_Y + connect \Y $or$libresoc.v:186005$12320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183703$12138 + cell $or $or$libresoc.v:186007$12322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381537,10 +385546,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183703$12138_Y + connect \Y $or$libresoc.v:186007$12322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183706$12141 + cell $or $or$libresoc.v:186010$12325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381548,39 +385557,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183706$12141_Y + connect \Y $or$libresoc.v:186010$12325_Y end - attribute \src "libresoc.v:183665.7-183665.20" - process $proc$libresoc.v:183665$12147 + attribute \src "libresoc.v:185969.7-185969.20" + process $proc$libresoc.v:185969$12331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183687.7-183687.19" - process $proc$libresoc.v:183687$12148 + attribute \src "libresoc.v:185991.7-185991.19" + process $proc$libresoc.v:185991$12332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183708.3-183709.27" - process $proc$libresoc.v:183708$12143 + attribute \src "libresoc.v:186012.3-186013.27" + process $proc$libresoc.v:186012$12327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183710.3-183718.6" - process $proc$libresoc.v:183710$12144 + attribute \src "libresoc.v:186014.3-186022.6" + process $proc$libresoc.v:186014$12328 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12145 $1\q_int$next[0:0]$12146 - attribute \src "libresoc.v:183711.5-183711.29" + assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 + attribute \src "libresoc.v:186015.5-186015.29" switch \initial - attribute \src "libresoc.v:183711.9-183711.17" + attribute \src "libresoc.v:186015.9-186015.17" case 1'1 case end @@ -381589,56 +385598,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12146 1'0 + assign $1\q_int$next[0:0]$12330 1'0 case - assign $1\q_int$next[0:0]$12146 \$5 + assign $1\q_int$next[0:0]$12330 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12145 + update \q_int$next $0\q_int$next[0:0]$12329 end - connect \$9 $and$libresoc.v:183700$12135_Y - connect \$11 $or$libresoc.v:183701$12136_Y - connect \$13 $not$libresoc.v:183702$12137_Y - connect \$15 $or$libresoc.v:183703$12138_Y - connect \$1 $not$libresoc.v:183704$12139_Y - connect \$3 $and$libresoc.v:183705$12140_Y - connect \$5 $or$libresoc.v:183706$12141_Y - connect \$7 $not$libresoc.v:183707$12142_Y + connect \$9 $and$libresoc.v:186004$12319_Y + connect \$11 $or$libresoc.v:186005$12320_Y + connect \$13 $not$libresoc.v:186006$12321_Y + connect \$15 $or$libresoc.v:186007$12322_Y + connect \$1 $not$libresoc.v:186008$12323_Y + connect \$3 $and$libresoc.v:186009$12324_Y + connect \$5 $or$libresoc.v:186010$12325_Y + connect \$7 $not$libresoc.v:186011$12326_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183726.1-183784.10" +attribute \src "libresoc.v:186030.1-186088.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:183727.7-183727.20" + attribute \src "libresoc.v:186031.7-186031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183772.3-183780.6" - wire $0\q_int$next[0:0]$12159 - attribute \src "libresoc.v:183770.3-183771.27" + attribute \src "libresoc.v:186076.3-186084.6" + wire $0\q_int$next[0:0]$12343 + attribute \src "libresoc.v:186074.3-186075.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183772.3-183780.6" - wire $1\q_int$next[0:0]$12160 - attribute \src "libresoc.v:183749.7-183749.19" + attribute \src "libresoc.v:186076.3-186084.6" + wire $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186053.7-186053.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183762.17-183762.96" - wire $and$libresoc.v:183762$12149_Y - attribute \src "libresoc.v:183767.17-183767.96" - wire $and$libresoc.v:183767$12154_Y - attribute \src "libresoc.v:183764.18-183764.93" - wire $not$libresoc.v:183764$12151_Y - attribute \src "libresoc.v:183766.17-183766.92" - wire $not$libresoc.v:183766$12153_Y - attribute \src "libresoc.v:183769.17-183769.92" - wire $not$libresoc.v:183769$12156_Y - attribute \src "libresoc.v:183763.18-183763.98" - wire $or$libresoc.v:183763$12150_Y - attribute \src "libresoc.v:183765.18-183765.99" - wire $or$libresoc.v:183765$12152_Y - attribute \src "libresoc.v:183768.17-183768.97" - wire $or$libresoc.v:183768$12155_Y + attribute \src "libresoc.v:186066.17-186066.96" + wire $and$libresoc.v:186066$12333_Y + attribute \src "libresoc.v:186071.17-186071.96" + wire $and$libresoc.v:186071$12338_Y + attribute \src "libresoc.v:186068.18-186068.93" + wire $not$libresoc.v:186068$12335_Y + attribute \src "libresoc.v:186070.17-186070.92" + wire $not$libresoc.v:186070$12337_Y + attribute \src "libresoc.v:186073.17-186073.92" + wire $not$libresoc.v:186073$12340_Y + attribute \src "libresoc.v:186067.18-186067.98" + wire $or$libresoc.v:186067$12334_Y + attribute \src "libresoc.v:186069.18-186069.99" + wire $or$libresoc.v:186069$12336_Y + attribute \src "libresoc.v:186072.17-186072.97" + wire $or$libresoc.v:186072$12339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381655,11 +385664,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183727.7-183727.15" + attribute \src "libresoc.v:186031.7-186031.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381676,7 +385685,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183762$12149 + cell $and $and$libresoc.v:186066$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381684,10 +385693,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183762$12149_Y + connect \Y $and$libresoc.v:186066$12333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183767$12154 + cell $and $and$libresoc.v:186071$12338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381695,34 +385704,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183767$12154_Y + connect \Y $and$libresoc.v:186071$12338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183764$12151 + cell $not $not$libresoc.v:186068$12335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183764$12151_Y + connect \Y $not$libresoc.v:186068$12335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183766$12153 + cell $not $not$libresoc.v:186070$12337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183766$12153_Y + connect \Y $not$libresoc.v:186070$12337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183769$12156 + cell $not $not$libresoc.v:186073$12340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183769$12156_Y + connect \Y $not$libresoc.v:186073$12340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183763$12150 + cell $or $or$libresoc.v:186067$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381730,10 +385739,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183763$12150_Y + connect \Y $or$libresoc.v:186067$12334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183765$12152 + cell $or $or$libresoc.v:186069$12336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381741,10 +385750,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183765$12152_Y + connect \Y $or$libresoc.v:186069$12336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183768$12155 + cell $or $or$libresoc.v:186072$12339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381752,39 +385761,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183768$12155_Y + connect \Y $or$libresoc.v:186072$12339_Y end - attribute \src "libresoc.v:183727.7-183727.20" - process $proc$libresoc.v:183727$12161 + attribute \src "libresoc.v:186031.7-186031.20" + process $proc$libresoc.v:186031$12345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183749.7-183749.19" - process $proc$libresoc.v:183749$12162 + attribute \src "libresoc.v:186053.7-186053.19" + process $proc$libresoc.v:186053$12346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183770.3-183771.27" - process $proc$libresoc.v:183770$12157 + attribute \src "libresoc.v:186074.3-186075.27" + process $proc$libresoc.v:186074$12341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183772.3-183780.6" - process $proc$libresoc.v:183772$12158 + attribute \src "libresoc.v:186076.3-186084.6" + process $proc$libresoc.v:186076$12342 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12159 $1\q_int$next[0:0]$12160 - attribute \src "libresoc.v:183773.5-183773.29" + assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186077.5-186077.29" switch \initial - attribute \src "libresoc.v:183773.9-183773.17" + attribute \src "libresoc.v:186077.9-186077.17" case 1'1 case end @@ -381793,56 +385802,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12160 1'0 + assign $1\q_int$next[0:0]$12344 1'0 case - assign $1\q_int$next[0:0]$12160 \$5 + assign $1\q_int$next[0:0]$12344 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12159 + update \q_int$next $0\q_int$next[0:0]$12343 end - connect \$9 $and$libresoc.v:183762$12149_Y - connect \$11 $or$libresoc.v:183763$12150_Y - connect \$13 $not$libresoc.v:183764$12151_Y - connect \$15 $or$libresoc.v:183765$12152_Y - connect \$1 $not$libresoc.v:183766$12153_Y - connect \$3 $and$libresoc.v:183767$12154_Y - connect \$5 $or$libresoc.v:183768$12155_Y - connect \$7 $not$libresoc.v:183769$12156_Y + connect \$9 $and$libresoc.v:186066$12333_Y + connect \$11 $or$libresoc.v:186067$12334_Y + connect \$13 $not$libresoc.v:186068$12335_Y + connect \$15 $or$libresoc.v:186069$12336_Y + connect \$1 $not$libresoc.v:186070$12337_Y + connect \$3 $and$libresoc.v:186071$12338_Y + connect \$5 $or$libresoc.v:186072$12339_Y + connect \$7 $not$libresoc.v:186073$12340_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183788.1-183846.10" +attribute \src "libresoc.v:186092.1-186150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:183789.7-183789.20" + attribute \src "libresoc.v:186093.7-186093.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183834.3-183842.6" - wire $0\q_int$next[0:0]$12173 - attribute \src "libresoc.v:183832.3-183833.27" + attribute \src "libresoc.v:186138.3-186146.6" + wire $0\q_int$next[0:0]$12357 + attribute \src "libresoc.v:186136.3-186137.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183834.3-183842.6" - wire $1\q_int$next[0:0]$12174 - attribute \src "libresoc.v:183811.7-183811.19" + attribute \src "libresoc.v:186138.3-186146.6" + wire $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186115.7-186115.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183824.17-183824.96" - wire $and$libresoc.v:183824$12163_Y - attribute \src "libresoc.v:183829.17-183829.96" - wire $and$libresoc.v:183829$12168_Y - attribute \src "libresoc.v:183826.18-183826.93" - wire $not$libresoc.v:183826$12165_Y - attribute \src "libresoc.v:183828.17-183828.92" - wire $not$libresoc.v:183828$12167_Y - attribute \src "libresoc.v:183831.17-183831.92" - wire $not$libresoc.v:183831$12170_Y - attribute \src "libresoc.v:183825.18-183825.98" - wire $or$libresoc.v:183825$12164_Y - attribute \src "libresoc.v:183827.18-183827.99" - wire $or$libresoc.v:183827$12166_Y - attribute \src "libresoc.v:183830.17-183830.97" - wire $or$libresoc.v:183830$12169_Y + attribute \src "libresoc.v:186128.17-186128.96" + wire $and$libresoc.v:186128$12347_Y + attribute \src "libresoc.v:186133.17-186133.96" + wire $and$libresoc.v:186133$12352_Y + attribute \src "libresoc.v:186130.18-186130.93" + wire $not$libresoc.v:186130$12349_Y + attribute \src "libresoc.v:186132.17-186132.92" + wire $not$libresoc.v:186132$12351_Y + attribute \src "libresoc.v:186135.17-186135.92" + wire $not$libresoc.v:186135$12354_Y + attribute \src "libresoc.v:186129.18-186129.98" + wire $or$libresoc.v:186129$12348_Y + attribute \src "libresoc.v:186131.18-186131.99" + wire $or$libresoc.v:186131$12350_Y + attribute \src "libresoc.v:186134.17-186134.97" + wire $or$libresoc.v:186134$12353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381859,11 +385868,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183789.7-183789.15" + attribute \src "libresoc.v:186093.7-186093.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381880,7 +385889,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183824$12163 + cell $and $and$libresoc.v:186128$12347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381888,10 +385897,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183824$12163_Y + connect \Y $and$libresoc.v:186128$12347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183829$12168 + cell $and $and$libresoc.v:186133$12352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381899,34 +385908,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183829$12168_Y + connect \Y $and$libresoc.v:186133$12352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183826$12165 + cell $not $not$libresoc.v:186130$12349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183826$12165_Y + connect \Y $not$libresoc.v:186130$12349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183828$12167 + cell $not $not$libresoc.v:186132$12351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183828$12167_Y + connect \Y $not$libresoc.v:186132$12351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183831$12170 + cell $not $not$libresoc.v:186135$12354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183831$12170_Y + connect \Y $not$libresoc.v:186135$12354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183825$12164 + cell $or $or$libresoc.v:186129$12348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381934,10 +385943,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183825$12164_Y + connect \Y $or$libresoc.v:186129$12348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183827$12166 + cell $or $or$libresoc.v:186131$12350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381945,10 +385954,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183827$12166_Y + connect \Y $or$libresoc.v:186131$12350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183830$12169 + cell $or $or$libresoc.v:186134$12353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381956,39 +385965,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183830$12169_Y + connect \Y $or$libresoc.v:186134$12353_Y end - attribute \src "libresoc.v:183789.7-183789.20" - process $proc$libresoc.v:183789$12175 + attribute \src "libresoc.v:186093.7-186093.20" + process $proc$libresoc.v:186093$12359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183811.7-183811.19" - process $proc$libresoc.v:183811$12176 + attribute \src "libresoc.v:186115.7-186115.19" + process $proc$libresoc.v:186115$12360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183832.3-183833.27" - process $proc$libresoc.v:183832$12171 + attribute \src "libresoc.v:186136.3-186137.27" + process $proc$libresoc.v:186136$12355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183834.3-183842.6" - process $proc$libresoc.v:183834$12172 + attribute \src "libresoc.v:186138.3-186146.6" + process $proc$libresoc.v:186138$12356 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12173 $1\q_int$next[0:0]$12174 - attribute \src "libresoc.v:183835.5-183835.29" + assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186139.5-186139.29" switch \initial - attribute \src "libresoc.v:183835.9-183835.17" + attribute \src "libresoc.v:186139.9-186139.17" case 1'1 case end @@ -381997,56 +386006,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12174 1'0 + assign $1\q_int$next[0:0]$12358 1'0 case - assign $1\q_int$next[0:0]$12174 \$5 + assign $1\q_int$next[0:0]$12358 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12173 + update \q_int$next $0\q_int$next[0:0]$12357 end - connect \$9 $and$libresoc.v:183824$12163_Y - connect \$11 $or$libresoc.v:183825$12164_Y - connect \$13 $not$libresoc.v:183826$12165_Y - connect \$15 $or$libresoc.v:183827$12166_Y - connect \$1 $not$libresoc.v:183828$12167_Y - connect \$3 $and$libresoc.v:183829$12168_Y - connect \$5 $or$libresoc.v:183830$12169_Y - connect \$7 $not$libresoc.v:183831$12170_Y + connect \$9 $and$libresoc.v:186128$12347_Y + connect \$11 $or$libresoc.v:186129$12348_Y + connect \$13 $not$libresoc.v:186130$12349_Y + connect \$15 $or$libresoc.v:186131$12350_Y + connect \$1 $not$libresoc.v:186132$12351_Y + connect \$3 $and$libresoc.v:186133$12352_Y + connect \$5 $or$libresoc.v:186134$12353_Y + connect \$7 $not$libresoc.v:186135$12354_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183850.1-183908.10" +attribute \src "libresoc.v:186154.1-186212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:183851.7-183851.20" + attribute \src "libresoc.v:186155.7-186155.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183896.3-183904.6" - wire $0\q_int$next[0:0]$12187 - attribute \src "libresoc.v:183894.3-183895.27" + attribute \src "libresoc.v:186200.3-186208.6" + wire $0\q_int$next[0:0]$12371 + attribute \src "libresoc.v:186198.3-186199.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183896.3-183904.6" - wire $1\q_int$next[0:0]$12188 - attribute \src "libresoc.v:183873.7-183873.19" + attribute \src "libresoc.v:186200.3-186208.6" + wire $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186177.7-186177.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183886.17-183886.96" - wire $and$libresoc.v:183886$12177_Y - attribute \src "libresoc.v:183891.17-183891.96" - wire $and$libresoc.v:183891$12182_Y - attribute \src "libresoc.v:183888.18-183888.93" - wire $not$libresoc.v:183888$12179_Y - attribute \src "libresoc.v:183890.17-183890.92" - wire $not$libresoc.v:183890$12181_Y - attribute \src "libresoc.v:183893.17-183893.92" - wire $not$libresoc.v:183893$12184_Y - attribute \src "libresoc.v:183887.18-183887.98" - wire $or$libresoc.v:183887$12178_Y - attribute \src "libresoc.v:183889.18-183889.99" - wire $or$libresoc.v:183889$12180_Y - attribute \src "libresoc.v:183892.17-183892.97" - wire $or$libresoc.v:183892$12183_Y + attribute \src "libresoc.v:186190.17-186190.96" + wire $and$libresoc.v:186190$12361_Y + attribute \src "libresoc.v:186195.17-186195.96" + wire $and$libresoc.v:186195$12366_Y + attribute \src "libresoc.v:186192.18-186192.93" + wire $not$libresoc.v:186192$12363_Y + attribute \src "libresoc.v:186194.17-186194.92" + wire $not$libresoc.v:186194$12365_Y + attribute \src "libresoc.v:186197.17-186197.92" + wire $not$libresoc.v:186197$12368_Y + attribute \src "libresoc.v:186191.18-186191.98" + wire $or$libresoc.v:186191$12362_Y + attribute \src "libresoc.v:186193.18-186193.99" + wire $or$libresoc.v:186193$12364_Y + attribute \src "libresoc.v:186196.17-186196.97" + wire $or$libresoc.v:186196$12367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382063,11 +386072,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183851.7-183851.15" + attribute \src "libresoc.v:186155.7-186155.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382084,7 +386093,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183886$12177 + cell $and $and$libresoc.v:186190$12361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382092,10 +386101,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183886$12177_Y + connect \Y $and$libresoc.v:186190$12361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183891$12182 + cell $and $and$libresoc.v:186195$12366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382103,34 +386112,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183891$12182_Y + connect \Y $and$libresoc.v:186195$12366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183888$12179 + cell $not $not$libresoc.v:186192$12363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183888$12179_Y + connect \Y $not$libresoc.v:186192$12363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183890$12181 + cell $not $not$libresoc.v:186194$12365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183890$12181_Y + connect \Y $not$libresoc.v:186194$12365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183893$12184 + cell $not $not$libresoc.v:186197$12368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183893$12184_Y + connect \Y $not$libresoc.v:186197$12368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183887$12178 + cell $or $or$libresoc.v:186191$12362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382138,10 +386147,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183887$12178_Y + connect \Y $or$libresoc.v:186191$12362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183889$12180 + cell $or $or$libresoc.v:186193$12364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382149,10 +386158,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183889$12180_Y + connect \Y $or$libresoc.v:186193$12364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183892$12183 + cell $or $or$libresoc.v:186196$12367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382160,39 +386169,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183892$12183_Y + connect \Y $or$libresoc.v:186196$12367_Y end - attribute \src "libresoc.v:183851.7-183851.20" - process $proc$libresoc.v:183851$12189 + attribute \src "libresoc.v:186155.7-186155.20" + process $proc$libresoc.v:186155$12373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183873.7-183873.19" - process $proc$libresoc.v:183873$12190 + attribute \src "libresoc.v:186177.7-186177.19" + process $proc$libresoc.v:186177$12374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183894.3-183895.27" - process $proc$libresoc.v:183894$12185 + attribute \src "libresoc.v:186198.3-186199.27" + process $proc$libresoc.v:186198$12369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183896.3-183904.6" - process $proc$libresoc.v:183896$12186 + attribute \src "libresoc.v:186200.3-186208.6" + process $proc$libresoc.v:186200$12370 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12187 $1\q_int$next[0:0]$12188 - attribute \src "libresoc.v:183897.5-183897.29" + assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186201.5-186201.29" switch \initial - attribute \src "libresoc.v:183897.9-183897.17" + attribute \src "libresoc.v:186201.9-186201.17" case 1'1 case end @@ -382201,56 +386210,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12188 1'0 + assign $1\q_int$next[0:0]$12372 1'0 case - assign $1\q_int$next[0:0]$12188 \$5 + assign $1\q_int$next[0:0]$12372 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12187 + update \q_int$next $0\q_int$next[0:0]$12371 end - connect \$9 $and$libresoc.v:183886$12177_Y - connect \$11 $or$libresoc.v:183887$12178_Y - connect \$13 $not$libresoc.v:183888$12179_Y - connect \$15 $or$libresoc.v:183889$12180_Y - connect \$1 $not$libresoc.v:183890$12181_Y - connect \$3 $and$libresoc.v:183891$12182_Y - connect \$5 $or$libresoc.v:183892$12183_Y - connect \$7 $not$libresoc.v:183893$12184_Y + connect \$9 $and$libresoc.v:186190$12361_Y + connect \$11 $or$libresoc.v:186191$12362_Y + connect \$13 $not$libresoc.v:186192$12363_Y + connect \$15 $or$libresoc.v:186193$12364_Y + connect \$1 $not$libresoc.v:186194$12365_Y + connect \$3 $and$libresoc.v:186195$12366_Y + connect \$5 $or$libresoc.v:186196$12367_Y + connect \$7 $not$libresoc.v:186197$12368_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183912.1-183970.10" +attribute \src "libresoc.v:186216.1-186274.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:183913.7-183913.20" + attribute \src "libresoc.v:186217.7-186217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183958.3-183966.6" - wire $0\q_int$next[0:0]$12201 - attribute \src "libresoc.v:183956.3-183957.27" + attribute \src "libresoc.v:186262.3-186270.6" + wire $0\q_int$next[0:0]$12385 + attribute \src "libresoc.v:186260.3-186261.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183958.3-183966.6" - wire $1\q_int$next[0:0]$12202 - attribute \src "libresoc.v:183935.7-183935.19" + attribute \src "libresoc.v:186262.3-186270.6" + wire $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186239.7-186239.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183948.17-183948.96" - wire $and$libresoc.v:183948$12191_Y - attribute \src "libresoc.v:183953.17-183953.96" - wire $and$libresoc.v:183953$12196_Y - attribute \src "libresoc.v:183950.18-183950.93" - wire $not$libresoc.v:183950$12193_Y - attribute \src "libresoc.v:183952.17-183952.92" - wire $not$libresoc.v:183952$12195_Y - attribute \src "libresoc.v:183955.17-183955.92" - wire $not$libresoc.v:183955$12198_Y - attribute \src "libresoc.v:183949.18-183949.98" - wire $or$libresoc.v:183949$12192_Y - attribute \src "libresoc.v:183951.18-183951.99" - wire $or$libresoc.v:183951$12194_Y - attribute \src "libresoc.v:183954.17-183954.97" - wire $or$libresoc.v:183954$12197_Y + attribute \src "libresoc.v:186252.17-186252.96" + wire $and$libresoc.v:186252$12375_Y + attribute \src "libresoc.v:186257.17-186257.96" + wire $and$libresoc.v:186257$12380_Y + attribute \src "libresoc.v:186254.18-186254.93" + wire $not$libresoc.v:186254$12377_Y + attribute \src "libresoc.v:186256.17-186256.92" + wire $not$libresoc.v:186256$12379_Y + attribute \src "libresoc.v:186259.17-186259.92" + wire $not$libresoc.v:186259$12382_Y + attribute \src "libresoc.v:186253.18-186253.98" + wire $or$libresoc.v:186253$12376_Y + attribute \src "libresoc.v:186255.18-186255.99" + wire $or$libresoc.v:186255$12378_Y + attribute \src "libresoc.v:186258.17-186258.97" + wire $or$libresoc.v:186258$12381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382267,11 +386276,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183913.7-183913.15" + attribute \src "libresoc.v:186217.7-186217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382288,7 +386297,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183948$12191 + cell $and $and$libresoc.v:186252$12375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382296,10 +386305,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183948$12191_Y + connect \Y $and$libresoc.v:186252$12375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183953$12196 + cell $and $and$libresoc.v:186257$12380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382307,34 +386316,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183953$12196_Y + connect \Y $and$libresoc.v:186257$12380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183950$12193 + cell $not $not$libresoc.v:186254$12377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183950$12193_Y + connect \Y $not$libresoc.v:186254$12377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183952$12195 + cell $not $not$libresoc.v:186256$12379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183952$12195_Y + connect \Y $not$libresoc.v:186256$12379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183955$12198 + cell $not $not$libresoc.v:186259$12382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183955$12198_Y + connect \Y $not$libresoc.v:186259$12382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183949$12192 + cell $or $or$libresoc.v:186253$12376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382342,10 +386351,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183949$12192_Y + connect \Y $or$libresoc.v:186253$12376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183951$12194 + cell $or $or$libresoc.v:186255$12378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382353,10 +386362,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183951$12194_Y + connect \Y $or$libresoc.v:186255$12378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183954$12197 + cell $or $or$libresoc.v:186258$12381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382364,39 +386373,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183954$12197_Y + connect \Y $or$libresoc.v:186258$12381_Y end - attribute \src "libresoc.v:183913.7-183913.20" - process $proc$libresoc.v:183913$12203 + attribute \src "libresoc.v:186217.7-186217.20" + process $proc$libresoc.v:186217$12387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183935.7-183935.19" - process $proc$libresoc.v:183935$12204 + attribute \src "libresoc.v:186239.7-186239.19" + process $proc$libresoc.v:186239$12388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183956.3-183957.27" - process $proc$libresoc.v:183956$12199 + attribute \src "libresoc.v:186260.3-186261.27" + process $proc$libresoc.v:186260$12383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183958.3-183966.6" - process $proc$libresoc.v:183958$12200 + attribute \src "libresoc.v:186262.3-186270.6" + process $proc$libresoc.v:186262$12384 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12201 $1\q_int$next[0:0]$12202 - attribute \src "libresoc.v:183959.5-183959.29" + assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186263.5-186263.29" switch \initial - attribute \src "libresoc.v:183959.9-183959.17" + attribute \src "libresoc.v:186263.9-186263.17" case 1'1 case end @@ -382405,56 +386414,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12202 1'0 + assign $1\q_int$next[0:0]$12386 1'0 case - assign $1\q_int$next[0:0]$12202 \$5 + assign $1\q_int$next[0:0]$12386 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12201 + update \q_int$next $0\q_int$next[0:0]$12385 end - connect \$9 $and$libresoc.v:183948$12191_Y - connect \$11 $or$libresoc.v:183949$12192_Y - connect \$13 $not$libresoc.v:183950$12193_Y - connect \$15 $or$libresoc.v:183951$12194_Y - connect \$1 $not$libresoc.v:183952$12195_Y - connect \$3 $and$libresoc.v:183953$12196_Y - connect \$5 $or$libresoc.v:183954$12197_Y - connect \$7 $not$libresoc.v:183955$12198_Y + connect \$9 $and$libresoc.v:186252$12375_Y + connect \$11 $or$libresoc.v:186253$12376_Y + connect \$13 $not$libresoc.v:186254$12377_Y + connect \$15 $or$libresoc.v:186255$12378_Y + connect \$1 $not$libresoc.v:186256$12379_Y + connect \$3 $and$libresoc.v:186257$12380_Y + connect \$5 $or$libresoc.v:186258$12381_Y + connect \$7 $not$libresoc.v:186259$12382_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183974.1-184032.10" +attribute \src "libresoc.v:186278.1-186336.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:183975.7-183975.20" + attribute \src "libresoc.v:186279.7-186279.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184020.3-184028.6" - wire $0\q_int$next[0:0]$12215 - attribute \src "libresoc.v:184018.3-184019.27" + attribute \src "libresoc.v:186324.3-186332.6" + wire $0\q_int$next[0:0]$12399 + attribute \src "libresoc.v:186322.3-186323.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184020.3-184028.6" - wire $1\q_int$next[0:0]$12216 - attribute \src "libresoc.v:183997.7-183997.19" + attribute \src "libresoc.v:186324.3-186332.6" + wire $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186301.7-186301.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184010.17-184010.96" - wire $and$libresoc.v:184010$12205_Y - attribute \src "libresoc.v:184015.17-184015.96" - wire $and$libresoc.v:184015$12210_Y - attribute \src "libresoc.v:184012.18-184012.93" - wire $not$libresoc.v:184012$12207_Y - attribute \src "libresoc.v:184014.17-184014.92" - wire $not$libresoc.v:184014$12209_Y - attribute \src "libresoc.v:184017.17-184017.92" - wire $not$libresoc.v:184017$12212_Y - attribute \src "libresoc.v:184011.18-184011.98" - wire $or$libresoc.v:184011$12206_Y - attribute \src "libresoc.v:184013.18-184013.99" - wire $or$libresoc.v:184013$12208_Y - attribute \src "libresoc.v:184016.17-184016.97" - wire $or$libresoc.v:184016$12211_Y + attribute \src "libresoc.v:186314.17-186314.96" + wire $and$libresoc.v:186314$12389_Y + attribute \src "libresoc.v:186319.17-186319.96" + wire $and$libresoc.v:186319$12394_Y + attribute \src "libresoc.v:186316.18-186316.93" + wire $not$libresoc.v:186316$12391_Y + attribute \src "libresoc.v:186318.17-186318.92" + wire $not$libresoc.v:186318$12393_Y + attribute \src "libresoc.v:186321.17-186321.92" + wire $not$libresoc.v:186321$12396_Y + attribute \src "libresoc.v:186315.18-186315.98" + wire $or$libresoc.v:186315$12390_Y + attribute \src "libresoc.v:186317.18-186317.99" + wire $or$libresoc.v:186317$12392_Y + attribute \src "libresoc.v:186320.17-186320.97" + wire $or$libresoc.v:186320$12395_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382471,11 +386480,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183975.7-183975.15" + attribute \src "libresoc.v:186279.7-186279.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382492,7 +386501,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184010$12205 + cell $and $and$libresoc.v:186314$12389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382500,10 +386509,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184010$12205_Y + connect \Y $and$libresoc.v:186314$12389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184015$12210 + cell $and $and$libresoc.v:186319$12394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382511,34 +386520,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184015$12210_Y + connect \Y $and$libresoc.v:186319$12394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184012$12207 + cell $not $not$libresoc.v:186316$12391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184012$12207_Y + connect \Y $not$libresoc.v:186316$12391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184014$12209 + cell $not $not$libresoc.v:186318$12393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184014$12209_Y + connect \Y $not$libresoc.v:186318$12393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184017$12212 + cell $not $not$libresoc.v:186321$12396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184017$12212_Y + connect \Y $not$libresoc.v:186321$12396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184011$12206 + cell $or $or$libresoc.v:186315$12390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382546,10 +386555,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184011$12206_Y + connect \Y $or$libresoc.v:186315$12390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184013$12208 + cell $or $or$libresoc.v:186317$12392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382557,10 +386566,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184013$12208_Y + connect \Y $or$libresoc.v:186317$12392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184016$12211 + cell $or $or$libresoc.v:186320$12395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382568,39 +386577,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184016$12211_Y + connect \Y $or$libresoc.v:186320$12395_Y end - attribute \src "libresoc.v:183975.7-183975.20" - process $proc$libresoc.v:183975$12217 + attribute \src "libresoc.v:186279.7-186279.20" + process $proc$libresoc.v:186279$12401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183997.7-183997.19" - process $proc$libresoc.v:183997$12218 + attribute \src "libresoc.v:186301.7-186301.19" + process $proc$libresoc.v:186301$12402 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184018.3-184019.27" - process $proc$libresoc.v:184018$12213 + attribute \src "libresoc.v:186322.3-186323.27" + process $proc$libresoc.v:186322$12397 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184020.3-184028.6" - process $proc$libresoc.v:184020$12214 + attribute \src "libresoc.v:186324.3-186332.6" + process $proc$libresoc.v:186324$12398 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12215 $1\q_int$next[0:0]$12216 - attribute \src "libresoc.v:184021.5-184021.29" + assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186325.5-186325.29" switch \initial - attribute \src "libresoc.v:184021.9-184021.17" + attribute \src "libresoc.v:186325.9-186325.17" case 1'1 case end @@ -382609,56 +386618,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12216 1'0 + assign $1\q_int$next[0:0]$12400 1'0 case - assign $1\q_int$next[0:0]$12216 \$5 + assign $1\q_int$next[0:0]$12400 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12215 + update \q_int$next $0\q_int$next[0:0]$12399 end - connect \$9 $and$libresoc.v:184010$12205_Y - connect \$11 $or$libresoc.v:184011$12206_Y - connect \$13 $not$libresoc.v:184012$12207_Y - connect \$15 $or$libresoc.v:184013$12208_Y - connect \$1 $not$libresoc.v:184014$12209_Y - connect \$3 $and$libresoc.v:184015$12210_Y - connect \$5 $or$libresoc.v:184016$12211_Y - connect \$7 $not$libresoc.v:184017$12212_Y + connect \$9 $and$libresoc.v:186314$12389_Y + connect \$11 $or$libresoc.v:186315$12390_Y + connect \$13 $not$libresoc.v:186316$12391_Y + connect \$15 $or$libresoc.v:186317$12392_Y + connect \$1 $not$libresoc.v:186318$12393_Y + connect \$3 $and$libresoc.v:186319$12394_Y + connect \$5 $or$libresoc.v:186320$12395_Y + connect \$7 $not$libresoc.v:186321$12396_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184036.1-184094.10" +attribute \src "libresoc.v:186340.1-186398.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:184037.7-184037.20" + attribute \src "libresoc.v:186341.7-186341.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184082.3-184090.6" - wire $0\q_int$next[0:0]$12229 - attribute \src "libresoc.v:184080.3-184081.27" + attribute \src "libresoc.v:186386.3-186394.6" + wire $0\q_int$next[0:0]$12413 + attribute \src "libresoc.v:186384.3-186385.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184082.3-184090.6" - wire $1\q_int$next[0:0]$12230 - attribute \src "libresoc.v:184059.7-184059.19" + attribute \src "libresoc.v:186386.3-186394.6" + wire $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186363.7-186363.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184072.17-184072.96" - wire $and$libresoc.v:184072$12219_Y - attribute \src "libresoc.v:184077.17-184077.96" - wire $and$libresoc.v:184077$12224_Y - attribute \src "libresoc.v:184074.18-184074.93" - wire $not$libresoc.v:184074$12221_Y - attribute \src "libresoc.v:184076.17-184076.92" - wire $not$libresoc.v:184076$12223_Y - attribute \src "libresoc.v:184079.17-184079.92" - wire $not$libresoc.v:184079$12226_Y - attribute \src "libresoc.v:184073.18-184073.98" - wire $or$libresoc.v:184073$12220_Y - attribute \src "libresoc.v:184075.18-184075.99" - wire $or$libresoc.v:184075$12222_Y - attribute \src "libresoc.v:184078.17-184078.97" - wire $or$libresoc.v:184078$12225_Y + attribute \src "libresoc.v:186376.17-186376.96" + wire $and$libresoc.v:186376$12403_Y + attribute \src "libresoc.v:186381.17-186381.96" + wire $and$libresoc.v:186381$12408_Y + attribute \src "libresoc.v:186378.18-186378.93" + wire $not$libresoc.v:186378$12405_Y + attribute \src "libresoc.v:186380.17-186380.92" + wire $not$libresoc.v:186380$12407_Y + attribute \src "libresoc.v:186383.17-186383.92" + wire $not$libresoc.v:186383$12410_Y + attribute \src "libresoc.v:186377.18-186377.98" + wire $or$libresoc.v:186377$12404_Y + attribute \src "libresoc.v:186379.18-186379.99" + wire $or$libresoc.v:186379$12406_Y + attribute \src "libresoc.v:186382.17-186382.97" + wire $or$libresoc.v:186382$12409_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382675,11 +386684,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184037.7-184037.15" + attribute \src "libresoc.v:186341.7-186341.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382696,7 +386705,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184072$12219 + cell $and $and$libresoc.v:186376$12403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382704,10 +386713,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184072$12219_Y + connect \Y $and$libresoc.v:186376$12403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184077$12224 + cell $and $and$libresoc.v:186381$12408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382715,34 +386724,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184077$12224_Y + connect \Y $and$libresoc.v:186381$12408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184074$12221 + cell $not $not$libresoc.v:186378$12405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184074$12221_Y + connect \Y $not$libresoc.v:186378$12405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184076$12223 + cell $not $not$libresoc.v:186380$12407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184076$12223_Y + connect \Y $not$libresoc.v:186380$12407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184079$12226 + cell $not $not$libresoc.v:186383$12410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184079$12226_Y + connect \Y $not$libresoc.v:186383$12410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184073$12220 + cell $or $or$libresoc.v:186377$12404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382750,10 +386759,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184073$12220_Y + connect \Y $or$libresoc.v:186377$12404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184075$12222 + cell $or $or$libresoc.v:186379$12406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382761,10 +386770,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184075$12222_Y + connect \Y $or$libresoc.v:186379$12406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184078$12225 + cell $or $or$libresoc.v:186382$12409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382772,39 +386781,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184078$12225_Y + connect \Y $or$libresoc.v:186382$12409_Y end - attribute \src "libresoc.v:184037.7-184037.20" - process $proc$libresoc.v:184037$12231 + attribute \src "libresoc.v:186341.7-186341.20" + process $proc$libresoc.v:186341$12415 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184059.7-184059.19" - process $proc$libresoc.v:184059$12232 + attribute \src "libresoc.v:186363.7-186363.19" + process $proc$libresoc.v:186363$12416 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184080.3-184081.27" - process $proc$libresoc.v:184080$12227 + attribute \src "libresoc.v:186384.3-186385.27" + process $proc$libresoc.v:186384$12411 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184082.3-184090.6" - process $proc$libresoc.v:184082$12228 + attribute \src "libresoc.v:186386.3-186394.6" + process $proc$libresoc.v:186386$12412 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12229 $1\q_int$next[0:0]$12230 - attribute \src "libresoc.v:184083.5-184083.29" + assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186387.5-186387.29" switch \initial - attribute \src "libresoc.v:184083.9-184083.17" + attribute \src "libresoc.v:186387.9-186387.17" case 1'1 case end @@ -382813,56 +386822,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12230 1'0 + assign $1\q_int$next[0:0]$12414 1'0 case - assign $1\q_int$next[0:0]$12230 \$5 + assign $1\q_int$next[0:0]$12414 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12229 + update \q_int$next $0\q_int$next[0:0]$12413 end - connect \$9 $and$libresoc.v:184072$12219_Y - connect \$11 $or$libresoc.v:184073$12220_Y - connect \$13 $not$libresoc.v:184074$12221_Y - connect \$15 $or$libresoc.v:184075$12222_Y - connect \$1 $not$libresoc.v:184076$12223_Y - connect \$3 $and$libresoc.v:184077$12224_Y - connect \$5 $or$libresoc.v:184078$12225_Y - connect \$7 $not$libresoc.v:184079$12226_Y + connect \$9 $and$libresoc.v:186376$12403_Y + connect \$11 $or$libresoc.v:186377$12404_Y + connect \$13 $not$libresoc.v:186378$12405_Y + connect \$15 $or$libresoc.v:186379$12406_Y + connect \$1 $not$libresoc.v:186380$12407_Y + connect \$3 $and$libresoc.v:186381$12408_Y + connect \$5 $or$libresoc.v:186382$12409_Y + connect \$7 $not$libresoc.v:186383$12410_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184098.1-184156.10" +attribute \src "libresoc.v:186402.1-186460.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:184099.7-184099.20" + attribute \src "libresoc.v:186403.7-186403.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184144.3-184152.6" - wire $0\q_int$next[0:0]$12243 - attribute \src "libresoc.v:184142.3-184143.27" + attribute \src "libresoc.v:186448.3-186456.6" + wire $0\q_int$next[0:0]$12427 + attribute \src "libresoc.v:186446.3-186447.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184144.3-184152.6" - wire $1\q_int$next[0:0]$12244 - attribute \src "libresoc.v:184121.7-184121.19" + attribute \src "libresoc.v:186448.3-186456.6" + wire $1\q_int$next[0:0]$12428 + attribute \src "libresoc.v:186425.7-186425.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184134.17-184134.96" - wire $and$libresoc.v:184134$12233_Y - attribute \src "libresoc.v:184139.17-184139.96" - wire $and$libresoc.v:184139$12238_Y - attribute \src "libresoc.v:184136.18-184136.93" - wire $not$libresoc.v:184136$12235_Y - attribute \src "libresoc.v:184138.17-184138.92" - wire $not$libresoc.v:184138$12237_Y - attribute \src "libresoc.v:184141.17-184141.92" - wire $not$libresoc.v:184141$12240_Y - attribute \src "libresoc.v:184135.18-184135.98" - wire $or$libresoc.v:184135$12234_Y - attribute \src "libresoc.v:184137.18-184137.99" - wire $or$libresoc.v:184137$12236_Y - attribute \src "libresoc.v:184140.17-184140.97" - wire $or$libresoc.v:184140$12239_Y + attribute \src "libresoc.v:186438.17-186438.96" + wire $and$libresoc.v:186438$12417_Y + attribute \src "libresoc.v:186443.17-186443.96" + wire $and$libresoc.v:186443$12422_Y + attribute \src "libresoc.v:186440.18-186440.93" + wire $not$libresoc.v:186440$12419_Y + attribute \src "libresoc.v:186442.17-186442.92" + wire $not$libresoc.v:186442$12421_Y + attribute \src "libresoc.v:186445.17-186445.92" + wire $not$libresoc.v:186445$12424_Y + attribute \src "libresoc.v:186439.18-186439.98" + wire $or$libresoc.v:186439$12418_Y + attribute \src "libresoc.v:186441.18-186441.99" + wire $or$libresoc.v:186441$12420_Y + attribute \src "libresoc.v:186444.17-186444.97" + wire $or$libresoc.v:186444$12423_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382879,11 +386888,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184099.7-184099.15" + attribute \src "libresoc.v:186403.7-186403.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382900,7 +386909,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184134$12233 + cell $and $and$libresoc.v:186438$12417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382908,10 +386917,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184134$12233_Y + connect \Y $and$libresoc.v:186438$12417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184139$12238 + cell $and $and$libresoc.v:186443$12422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382919,34 +386928,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184139$12238_Y + connect \Y $and$libresoc.v:186443$12422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184136$12235 + cell $not $not$libresoc.v:186440$12419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184136$12235_Y + connect \Y $not$libresoc.v:186440$12419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184138$12237 + cell $not $not$libresoc.v:186442$12421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184138$12237_Y + connect \Y $not$libresoc.v:186442$12421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184141$12240 + cell $not $not$libresoc.v:186445$12424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184141$12240_Y + connect \Y $not$libresoc.v:186445$12424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184135$12234 + cell $or $or$libresoc.v:186439$12418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382954,10 +386963,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184135$12234_Y + connect \Y $or$libresoc.v:186439$12418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184137$12236 + cell $or $or$libresoc.v:186441$12420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382965,10 +386974,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184137$12236_Y + connect \Y $or$libresoc.v:186441$12420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184140$12239 + cell $or $or$libresoc.v:186444$12423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382976,39 +386985,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184140$12239_Y + connect \Y $or$libresoc.v:186444$12423_Y end - attribute \src "libresoc.v:184099.7-184099.20" - process $proc$libresoc.v:184099$12245 + attribute \src "libresoc.v:186403.7-186403.20" + process $proc$libresoc.v:186403$12429 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184121.7-184121.19" - process $proc$libresoc.v:184121$12246 + attribute \src "libresoc.v:186425.7-186425.19" + process $proc$libresoc.v:186425$12430 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184142.3-184143.27" - process $proc$libresoc.v:184142$12241 + attribute \src "libresoc.v:186446.3-186447.27" + process $proc$libresoc.v:186446$12425 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184144.3-184152.6" - process $proc$libresoc.v:184144$12242 + attribute \src "libresoc.v:186448.3-186456.6" + process $proc$libresoc.v:186448$12426 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12243 $1\q_int$next[0:0]$12244 - attribute \src "libresoc.v:184145.5-184145.29" + assign $0\q_int$next[0:0]$12427 $1\q_int$next[0:0]$12428 + attribute \src "libresoc.v:186449.5-186449.29" switch \initial - attribute \src "libresoc.v:184145.9-184145.17" + attribute \src "libresoc.v:186449.9-186449.17" case 1'1 case end @@ -383017,92 +387026,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12244 1'0 + assign $1\q_int$next[0:0]$12428 1'0 case - assign $1\q_int$next[0:0]$12244 \$5 + assign $1\q_int$next[0:0]$12428 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12243 + update \q_int$next $0\q_int$next[0:0]$12427 end - connect \$9 $and$libresoc.v:184134$12233_Y - connect \$11 $or$libresoc.v:184135$12234_Y - connect \$13 $not$libresoc.v:184136$12235_Y - connect \$15 $or$libresoc.v:184137$12236_Y - connect \$1 $not$libresoc.v:184138$12237_Y - connect \$3 $and$libresoc.v:184139$12238_Y - connect \$5 $or$libresoc.v:184140$12239_Y - connect \$7 $not$libresoc.v:184141$12240_Y + connect \$9 $and$libresoc.v:186438$12417_Y + connect \$11 $or$libresoc.v:186439$12418_Y + connect \$13 $not$libresoc.v:186440$12419_Y + connect \$15 $or$libresoc.v:186441$12420_Y + connect \$1 $not$libresoc.v:186442$12421_Y + connect \$3 $and$libresoc.v:186443$12422_Y + connect \$5 $or$libresoc.v:186444$12423_Y + connect \$7 $not$libresoc.v:186445$12424_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184160.1-184569.10" +attribute \src "libresoc.v:186464.1-186873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:184161.7-184161.20" + attribute \src "libresoc.v:186465.7-186465.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:184506.18-184506.122" - wire $and$libresoc.v:184506$12248_Y - attribute \src "libresoc.v:184508.18-184508.122" - wire $and$libresoc.v:184508$12250_Y - attribute \src "libresoc.v:184517.18-184517.105" - wire $and$libresoc.v:184517$12263_Y - attribute \src "libresoc.v:184520.18-184520.105" - wire $and$libresoc.v:184520$12266_Y - attribute \src "libresoc.v:184516.18-184516.123" - wire $eq$libresoc.v:184516$12262_Y - attribute \src "libresoc.v:184519.18-184519.123" - wire $eq$libresoc.v:184519$12265_Y - attribute \src "libresoc.v:184522.18-184522.117" - wire $eq$libresoc.v:184522$12268_Y - attribute \src "libresoc.v:184509.18-184509.97" - wire width 65 $extend$libresoc.v:184509$12251_Y - attribute \src "libresoc.v:184510.18-184510.91" - wire width 65 $extend$libresoc.v:184510$12253_Y - attribute \src "libresoc.v:184512.18-184512.97" - wire width 65 $extend$libresoc.v:184512$12256_Y - attribute \src "libresoc.v:184513.18-184513.91" - wire width 65 $extend$libresoc.v:184513$12258_Y - attribute \src "libresoc.v:184525.18-184525.99" - wire width 128 $extend$libresoc.v:184525$12271_Y - attribute \src "libresoc.v:184515.18-184515.112" - wire $ge$libresoc.v:184515$12261_Y - attribute \src "libresoc.v:184518.18-184518.124" - wire $ge$libresoc.v:184518$12264_Y - attribute \src "libresoc.v:184509.18-184509.97" - wire width 65 $neg$libresoc.v:184509$12252_Y - attribute \src "libresoc.v:184512.18-184512.97" - wire width 65 $neg$libresoc.v:184512$12257_Y - attribute \src "libresoc.v:184510.18-184510.91" - wire width 65 $pos$libresoc.v:184510$12254_Y - attribute \src "libresoc.v:184513.18-184513.91" - wire width 65 $pos$libresoc.v:184513$12259_Y - attribute \src "libresoc.v:184525.18-184525.99" - wire width 128 $pos$libresoc.v:184525$12272_Y - attribute \src "libresoc.v:184524.18-184524.117" - wire width 95 $sshl$libresoc.v:184524$12270_Y - attribute \src "libresoc.v:184526.18-184526.111" - wire width 191 $sshl$libresoc.v:184526$12273_Y - attribute \src "libresoc.v:184505.18-184505.131" - wire $ternary$libresoc.v:184505$12247_Y - attribute \src "libresoc.v:184507.18-184507.131" - wire $ternary$libresoc.v:184507$12249_Y - attribute \src "libresoc.v:184511.18-184511.119" - wire width 65 $ternary$libresoc.v:184511$12255_Y - attribute \src "libresoc.v:184514.18-184514.120" - wire width 65 $ternary$libresoc.v:184514$12260_Y - attribute \src "libresoc.v:184521.18-184521.130" - wire width 32 $ternary$libresoc.v:184521$12267_Y - attribute \src "libresoc.v:184523.18-184523.131" - wire width 32 $ternary$libresoc.v:184523$12269_Y + attribute \src "libresoc.v:186810.18-186810.122" + wire $and$libresoc.v:186810$12432_Y + attribute \src "libresoc.v:186812.18-186812.122" + wire $and$libresoc.v:186812$12434_Y + attribute \src "libresoc.v:186821.18-186821.105" + wire $and$libresoc.v:186821$12447_Y + attribute \src "libresoc.v:186824.18-186824.105" + wire $and$libresoc.v:186824$12450_Y + attribute \src "libresoc.v:186820.18-186820.123" + wire $eq$libresoc.v:186820$12446_Y + attribute \src "libresoc.v:186823.18-186823.123" + wire $eq$libresoc.v:186823$12449_Y + attribute \src "libresoc.v:186826.18-186826.117" + wire $eq$libresoc.v:186826$12452_Y + attribute \src "libresoc.v:186813.18-186813.97" + wire width 65 $extend$libresoc.v:186813$12435_Y + attribute \src "libresoc.v:186814.18-186814.91" + wire width 65 $extend$libresoc.v:186814$12437_Y + attribute \src "libresoc.v:186816.18-186816.97" + wire width 65 $extend$libresoc.v:186816$12440_Y + attribute \src "libresoc.v:186817.18-186817.91" + wire width 65 $extend$libresoc.v:186817$12442_Y + attribute \src "libresoc.v:186829.18-186829.99" + wire width 128 $extend$libresoc.v:186829$12455_Y + attribute \src "libresoc.v:186819.18-186819.112" + wire $ge$libresoc.v:186819$12445_Y + attribute \src "libresoc.v:186822.18-186822.124" + wire $ge$libresoc.v:186822$12448_Y + attribute \src "libresoc.v:186813.18-186813.97" + wire width 65 $neg$libresoc.v:186813$12436_Y + attribute \src "libresoc.v:186816.18-186816.97" + wire width 65 $neg$libresoc.v:186816$12441_Y + attribute \src "libresoc.v:186814.18-186814.91" + wire width 65 $pos$libresoc.v:186814$12438_Y + attribute \src "libresoc.v:186817.18-186817.91" + wire width 65 $pos$libresoc.v:186817$12443_Y + attribute \src "libresoc.v:186829.18-186829.99" + wire width 128 $pos$libresoc.v:186829$12456_Y + attribute \src "libresoc.v:186828.18-186828.117" + wire width 95 $sshl$libresoc.v:186828$12454_Y + attribute \src "libresoc.v:186830.18-186830.111" + wire width 191 $sshl$libresoc.v:186830$12457_Y + attribute \src "libresoc.v:186809.18-186809.131" + wire $ternary$libresoc.v:186809$12431_Y + attribute \src "libresoc.v:186811.18-186811.131" + wire $ternary$libresoc.v:186811$12433_Y + attribute \src "libresoc.v:186815.18-186815.119" + wire width 65 $ternary$libresoc.v:186815$12439_Y + attribute \src "libresoc.v:186818.18-186818.120" + wire width 65 $ternary$libresoc.v:186818$12444_Y + attribute \src "libresoc.v:186825.18-186825.130" + wire width 32 $ternary$libresoc.v:186825$12451_Y + attribute \src "libresoc.v:186827.18-186827.131" + wire width 32 $ternary$libresoc.v:186827$12453_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -383171,7 +387180,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:184161.7-184161.15" + attribute \src "libresoc.v:186465.7-186465.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -383448,7 +387457,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:184506$12248 + cell $and $and$libresoc.v:186810$12432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383456,10 +387465,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:184506$12248_Y + connect \Y $and$libresoc.v:186810$12432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:184508$12250 + cell $and $and$libresoc.v:186812$12434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383467,10 +387476,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:184508$12250_Y + connect \Y $and$libresoc.v:186812$12434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:184517$12263 + cell $and $and$libresoc.v:186821$12447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383478,10 +387487,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:184517$12263_Y + connect \Y $and$libresoc.v:186821$12447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:184520$12266 + cell $and $and$libresoc.v:186824$12450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383489,10 +387498,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:184520$12266_Y + connect \Y $and$libresoc.v:186824$12450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:184516$12262 + cell $eq $eq$libresoc.v:186820$12446 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -383500,10 +387509,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:184516$12262_Y + connect \Y $eq$libresoc.v:186820$12446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:184519$12265 + cell $eq $eq$libresoc.v:186823$12449 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -383511,10 +387520,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:184519$12265_Y + connect \Y $eq$libresoc.v:186823$12449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:184522$12268 + cell $eq $eq$libresoc.v:186826$12452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383522,50 +387531,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:184522$12268_Y + connect \Y $eq$libresoc.v:186826$12452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:184509$12251 + cell $pos $extend$libresoc.v:186813$12435 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:184509$12251_Y + connect \Y $extend$libresoc.v:186813$12435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:184510$12253 + cell $pos $extend$libresoc.v:186814$12437 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:184510$12253_Y + connect \Y $extend$libresoc.v:186814$12437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:184512$12256 + cell $pos $extend$libresoc.v:186816$12440 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:184512$12256_Y + connect \Y $extend$libresoc.v:186816$12440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:184513$12258 + cell $pos $extend$libresoc.v:186817$12442 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:184513$12258_Y + connect \Y $extend$libresoc.v:186817$12442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:184525$12271 + cell $pos $extend$libresoc.v:186829$12455 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:184525$12271_Y + connect \Y $extend$libresoc.v:186829$12455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:184515$12261 + cell $ge $ge$libresoc.v:186819$12445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383573,10 +387582,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:184515$12261_Y + connect \Y $ge$libresoc.v:186819$12445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:184518$12264 + cell $ge $ge$libresoc.v:186822$12448 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -383584,50 +387593,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:184518$12264_Y + connect \Y $ge$libresoc.v:186822$12448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:184509$12252 + cell $neg $neg$libresoc.v:186813$12436 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184509$12251_Y - connect \Y $neg$libresoc.v:184509$12252_Y + connect \A $extend$libresoc.v:186813$12435_Y + connect \Y $neg$libresoc.v:186813$12436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:184512$12257 + cell $neg $neg$libresoc.v:186816$12441 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184512$12256_Y - connect \Y $neg$libresoc.v:184512$12257_Y + connect \A $extend$libresoc.v:186816$12440_Y + connect \Y $neg$libresoc.v:186816$12441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:184510$12254 + cell $pos $pos$libresoc.v:186814$12438 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184510$12253_Y - connect \Y $pos$libresoc.v:184510$12254_Y + connect \A $extend$libresoc.v:186814$12437_Y + connect \Y $pos$libresoc.v:186814$12438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:184513$12259 + cell $pos $pos$libresoc.v:186817$12443 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184513$12258_Y - connect \Y $pos$libresoc.v:184513$12259_Y + connect \A $extend$libresoc.v:186817$12442_Y + connect \Y $pos$libresoc.v:186817$12443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:184525$12272 + cell $pos $pos$libresoc.v:186829$12456 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:184525$12271_Y - connect \Y $pos$libresoc.v:184525$12272_Y + connect \A $extend$libresoc.v:186829$12455_Y + connect \Y $pos$libresoc.v:186829$12456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:184524$12270 + cell $sshl $sshl$libresoc.v:186828$12454 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -383635,10 +387644,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:184524$12270_Y + connect \Y $sshl$libresoc.v:186828$12454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:184526$12273 + cell $sshl $sshl$libresoc.v:186830$12457 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383646,72 +387655,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:184526$12273_Y + connect \Y $sshl$libresoc.v:186830$12457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:184505$12247 + cell $mux $ternary$libresoc.v:186809$12431 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184505$12247_Y + connect \Y $ternary$libresoc.v:186809$12431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:184507$12249 + cell $mux $ternary$libresoc.v:186811$12433 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184507$12249_Y + connect \Y $ternary$libresoc.v:186811$12433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:184511$12255 + cell $mux $ternary$libresoc.v:186815$12439 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:184511$12255_Y + connect \Y $ternary$libresoc.v:186815$12439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:184514$12260 + cell $mux $ternary$libresoc.v:186818$12444 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:184514$12260_Y + connect \Y $ternary$libresoc.v:186818$12444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:184521$12267 + cell $mux $ternary$libresoc.v:186825$12451 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184521$12267_Y + connect \Y $ternary$libresoc.v:186825$12451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:184523$12269 + cell $mux $ternary$libresoc.v:186827$12453 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184523$12269_Y + connect \Y $ternary$libresoc.v:186827$12453_Y end - attribute \src "libresoc.v:184161.7-184161.20" - process $proc$libresoc.v:184161$12275 + attribute \src "libresoc.v:186465.7-186465.20" + process $proc$libresoc.v:186465$12459 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184527.3-184552.6" - process $proc$libresoc.v:184527$12274 + attribute \src "libresoc.v:186831.3-186856.6" + process $proc$libresoc.v:186831$12458 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:184528.5-184528.29" + attribute \src "libresoc.v:186832.5-186832.29" switch \initial - attribute \src "libresoc.v:184528.9-184528.17" + attribute \src "libresoc.v:186832.9-186832.17" case 1'1 case end @@ -383743,28 +387752,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:184505$12247_Y - connect \$23 $and$libresoc.v:184506$12248_Y - connect \$25 $ternary$libresoc.v:184507$12249_Y - connect \$27 $and$libresoc.v:184508$12250_Y - connect \$30 $neg$libresoc.v:184509$12252_Y - connect \$32 $pos$libresoc.v:184510$12254_Y - connect \$34 $ternary$libresoc.v:184511$12255_Y - connect \$37 $neg$libresoc.v:184512$12257_Y - connect \$39 $pos$libresoc.v:184513$12259_Y - connect \$41 $ternary$libresoc.v:184514$12260_Y - connect \$43 $ge$libresoc.v:184515$12261_Y - connect \$45 $eq$libresoc.v:184516$12262_Y - connect \$47 $and$libresoc.v:184517$12263_Y - connect \$49 $ge$libresoc.v:184518$12264_Y - connect \$51 $eq$libresoc.v:184519$12265_Y - connect \$53 $and$libresoc.v:184520$12266_Y - connect \$55 $ternary$libresoc.v:184521$12267_Y - connect \$57 $eq$libresoc.v:184522$12268_Y - connect \$59 $ternary$libresoc.v:184523$12269_Y - connect \$62 $sshl$libresoc.v:184524$12270_Y - connect \$61 $pos$libresoc.v:184525$12272_Y - connect \$66 $sshl$libresoc.v:184526$12273_Y + connect \$21 $ternary$libresoc.v:186809$12431_Y + connect \$23 $and$libresoc.v:186810$12432_Y + connect \$25 $ternary$libresoc.v:186811$12433_Y + connect \$27 $and$libresoc.v:186812$12434_Y + connect \$30 $neg$libresoc.v:186813$12436_Y + connect \$32 $pos$libresoc.v:186814$12438_Y + connect \$34 $ternary$libresoc.v:186815$12439_Y + connect \$37 $neg$libresoc.v:186816$12441_Y + connect \$39 $pos$libresoc.v:186817$12443_Y + connect \$41 $ternary$libresoc.v:186818$12444_Y + connect \$43 $ge$libresoc.v:186819$12445_Y + connect \$45 $eq$libresoc.v:186820$12446_Y + connect \$47 $and$libresoc.v:186821$12447_Y + connect \$49 $ge$libresoc.v:186822$12448_Y + connect \$51 $eq$libresoc.v:186823$12449_Y + connect \$53 $and$libresoc.v:186824$12450_Y + connect \$55 $ternary$libresoc.v:186825$12451_Y + connect \$57 $eq$libresoc.v:186826$12452_Y + connect \$59 $ternary$libresoc.v:186827$12453_Y + connect \$62 $sshl$libresoc.v:186828$12454_Y + connect \$61 $pos$libresoc.v:186829$12456_Y + connect \$66 $sshl$libresoc.v:186830$12457_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -383782,513 +387791,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:184573.1-185780.10" +attribute \src "libresoc.v:186877.1-188084.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:185351.3-185352.25" + attribute \src "libresoc.v:187655.3-187656.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:185349.3-185350.46" + attribute \src "libresoc.v:187653.3-187654.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:185700.3-185708.6" - wire $0\alu_l_r_alu$next[0:0]$12493 - attribute \src "libresoc.v:185267.3-185268.39" + attribute \src "libresoc.v:188004.3-188012.6" + wire $0\alu_l_r_alu$next[0:0]$12677 + attribute \src "libresoc.v:187571.3-187572.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 - attribute \src "libresoc.v:185295.3-185296.75" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + attribute \src "libresoc.v:187599.3-187600.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 - attribute \src "libresoc.v:185297.3-185298.89" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + attribute \src "libresoc.v:187601.3-187602.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 - attribute \src "libresoc.v:185299.3-185300.85" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + attribute \src "libresoc.v:187603.3-187604.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 - attribute \src "libresoc.v:185313.3-185314.83" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + attribute \src "libresoc.v:187617.3-187618.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 - attribute \src "libresoc.v:185317.3-185318.77" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + attribute \src "libresoc.v:187621.3-187622.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 - attribute \src "libresoc.v:185325.3-185326.69" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + attribute \src "libresoc.v:187629.3-187630.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 - attribute \src "libresoc.v:185293.3-185294.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + attribute \src "libresoc.v:187597.3-187598.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 - attribute \src "libresoc.v:185311.3-185312.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + attribute \src "libresoc.v:187615.3-187616.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 - attribute \src "libresoc.v:185321.3-185322.77" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + attribute \src "libresoc.v:187625.3-187626.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 - attribute \src "libresoc.v:185323.3-185324.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + attribute \src "libresoc.v:187627.3-187628.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 - attribute \src "libresoc.v:185305.3-185306.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + attribute \src "libresoc.v:187609.3-187610.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 - attribute \src "libresoc.v:185307.3-185308.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + attribute \src "libresoc.v:187611.3-187612.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 - attribute \src "libresoc.v:185315.3-185316.85" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + attribute \src "libresoc.v:187619.3-187620.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 - attribute \src "libresoc.v:185319.3-185320.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + attribute \src "libresoc.v:187623.3-187624.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 - attribute \src "libresoc.v:185303.3-185304.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + attribute \src "libresoc.v:187607.3-187608.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 - attribute \src "libresoc.v:185301.3-185302.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + attribute \src "libresoc.v:187605.3-187606.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 - attribute \src "libresoc.v:185309.3-185310.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + attribute \src "libresoc.v:187613.3-187614.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:185691.3-185699.6" - wire $0\alui_l_r_alui$next[0:0]$12490 - attribute \src "libresoc.v:185269.3-185270.43" + attribute \src "libresoc.v:187995.3-188003.6" + wire $0\alui_l_r_alui$next[0:0]$12674 + attribute \src "libresoc.v:187573.3-187574.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $0\data_r0__o$next[63:0]$12451 - attribute \src "libresoc.v:185289.3-185290.37" + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $0\data_r0__o$next[63:0]$12635 + attribute \src "libresoc.v:187593.3-187594.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire $0\data_r0__o_ok$next[0:0]$12452 - attribute \src "libresoc.v:185291.3-185292.43" + attribute \src "libresoc.v:187879.3-187900.6" + wire $0\data_r0__o_ok$next[0:0]$12636 + attribute \src "libresoc.v:187595.3-187596.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12459 - attribute \src "libresoc.v:185285.3-185286.43" + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12643 + attribute \src "libresoc.v:187589.3-187590.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12460 - attribute \src "libresoc.v:185287.3-185288.49" + attribute \src "libresoc.v:187901.3-187922.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12644 + attribute \src "libresoc.v:187591.3-187592.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12467 - attribute \src "libresoc.v:185281.3-185282.47" + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 + attribute \src "libresoc.v:187585.3-187586.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12468 - attribute \src "libresoc.v:185283.3-185284.53" + attribute \src "libresoc.v:187923.3-187944.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12652 + attribute \src "libresoc.v:187587.3-187588.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:185709.3-185718.6" + attribute \src "libresoc.v:188013.3-188022.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:185719.3-185728.6" + attribute \src "libresoc.v:188023.3-188032.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:185729.3-185738.6" + attribute \src "libresoc.v:188033.3-188042.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:184574.7-184574.20" + attribute \src "libresoc.v:186878.7-186878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185492.3-185500.6" - wire $0\opc_l_r_opc$next[0:0]$12395 - attribute \src "libresoc.v:185335.3-185336.39" + attribute \src "libresoc.v:187796.3-187804.6" + wire $0\opc_l_r_opc$next[0:0]$12579 + attribute \src "libresoc.v:187639.3-187640.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:185483.3-185491.6" - wire $0\opc_l_s_opc$next[0:0]$12392 - attribute \src "libresoc.v:185337.3-185338.39" + attribute \src "libresoc.v:187787.3-187795.6" + wire $0\opc_l_s_opc$next[0:0]$12576 + attribute \src "libresoc.v:187641.3-187642.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire width 3 $0\prev_wr_go$next[2:0]$12499 - attribute \src "libresoc.v:185347.3-185348.37" + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $0\prev_wr_go$next[2:0]$12683 + attribute \src "libresoc.v:187651.3-187652.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:185437.3-185446.6" + attribute \src "libresoc.v:187741.3-187750.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:185528.3-185536.6" - wire width 3 $0\req_l_r_req$next[2:0]$12407 - attribute \src "libresoc.v:185327.3-185328.39" + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $0\req_l_r_req$next[2:0]$12591 + attribute \src "libresoc.v:187631.3-187632.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:185519.3-185527.6" - wire width 3 $0\req_l_s_req$next[2:0]$12404 - attribute \src "libresoc.v:185329.3-185330.39" + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $0\req_l_s_req$next[2:0]$12588 + attribute \src "libresoc.v:187633.3-187634.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:185456.3-185464.6" - wire $0\rok_l_r_rdok$next[0:0]$12383 - attribute \src "libresoc.v:185343.3-185344.41" + attribute \src "libresoc.v:187760.3-187768.6" + wire $0\rok_l_r_rdok$next[0:0]$12567 + attribute \src "libresoc.v:187647.3-187648.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:185447.3-185455.6" - wire $0\rok_l_s_rdok$next[0:0]$12380 - attribute \src "libresoc.v:185345.3-185346.41" + attribute \src "libresoc.v:187751.3-187759.6" + wire $0\rok_l_s_rdok$next[0:0]$12564 + attribute \src "libresoc.v:187649.3-187650.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:185474.3-185482.6" - wire $0\rst_l_r_rst$next[0:0]$12389 - attribute \src "libresoc.v:185339.3-185340.39" + attribute \src "libresoc.v:187778.3-187786.6" + wire $0\rst_l_r_rst$next[0:0]$12573 + attribute \src "libresoc.v:187643.3-187644.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:185465.3-185473.6" - wire $0\rst_l_s_rst$next[0:0]$12386 - attribute \src "libresoc.v:185341.3-185342.39" + attribute \src "libresoc.v:187769.3-187777.6" + wire $0\rst_l_s_rst$next[0:0]$12570 + attribute \src "libresoc.v:187645.3-187646.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:185510.3-185518.6" - wire width 5 $0\src_l_r_src$next[4:0]$12401 - attribute \src "libresoc.v:185331.3-185332.39" + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $0\src_l_r_src$next[4:0]$12585 + attribute \src "libresoc.v:187635.3-187636.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:185501.3-185509.6" - wire width 5 $0\src_l_s_src$next[4:0]$12398 - attribute \src "libresoc.v:185333.3-185334.39" + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $0\src_l_s_src$next[4:0]$12582 + attribute \src "libresoc.v:187637.3-187638.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:185641.3-185650.6" - wire width 64 $0\src_r0$next[63:0]$12475 - attribute \src "libresoc.v:185279.3-185280.29" + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $0\src_r0$next[63:0]$12659 + attribute \src "libresoc.v:187583.3-187584.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:185651.3-185660.6" - wire width 64 $0\src_r1$next[63:0]$12478 - attribute \src "libresoc.v:185277.3-185278.29" + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $0\src_r1$next[63:0]$12662 + attribute \src "libresoc.v:187581.3-187582.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:185661.3-185670.6" - wire width 64 $0\src_r2$next[63:0]$12481 - attribute \src "libresoc.v:185275.3-185276.29" + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $0\src_r2$next[63:0]$12665 + attribute \src "libresoc.v:187579.3-187580.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:185671.3-185680.6" - wire $0\src_r3$next[0:0]$12484 - attribute \src "libresoc.v:185273.3-185274.29" + attribute \src "libresoc.v:187975.3-187984.6" + wire $0\src_r3$next[0:0]$12668 + attribute \src "libresoc.v:187577.3-187578.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:185681.3-185690.6" - wire width 2 $0\src_r4$next[1:0]$12487 - attribute \src "libresoc.v:185271.3-185272.29" + attribute \src "libresoc.v:187985.3-187994.6" + wire width 2 $0\src_r4$next[1:0]$12671 + attribute \src "libresoc.v:187575.3-187576.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:184696.7-184696.24" + attribute \src "libresoc.v:187000.7-187000.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:184706.7-184706.26" + attribute \src "libresoc.v:187010.7-187010.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:185700.3-185708.6" - wire $1\alu_l_r_alu$next[0:0]$12494 - attribute \src "libresoc.v:184714.7-184714.25" + attribute \src "libresoc.v:188004.3-188012.6" + wire $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:187018.7-187018.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 - attribute \src "libresoc.v:184757.14-184757.54" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + attribute \src "libresoc.v:187061.14-187061.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 - attribute \src "libresoc.v:184761.14-184761.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + attribute \src "libresoc.v:187065.14-187065.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 - attribute \src "libresoc.v:184765.7-184765.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + attribute \src "libresoc.v:187069.7-187069.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 - attribute \src "libresoc.v:184773.13-184773.53" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + attribute \src "libresoc.v:187077.13-187077.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 - attribute \src "libresoc.v:184777.7-184777.44" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + attribute \src "libresoc.v:187081.7-187081.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 - attribute \src "libresoc.v:184781.14-184781.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + attribute \src "libresoc.v:187085.14-187085.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 - attribute \src "libresoc.v:184860.13-184860.52" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + attribute \src "libresoc.v:187164.13-187164.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 - attribute \src "libresoc.v:184864.7-184864.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + attribute \src "libresoc.v:187168.7-187168.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 - attribute \src "libresoc.v:184868.7-184868.44" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + attribute \src "libresoc.v:187172.7-187172.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 - attribute \src "libresoc.v:184872.7-184872.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + attribute \src "libresoc.v:187176.7-187176.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 - attribute \src "libresoc.v:184876.7-184876.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + attribute \src "libresoc.v:187180.7-187180.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 - attribute \src "libresoc.v:184880.7-184880.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + attribute \src "libresoc.v:187184.7-187184.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 - attribute \src "libresoc.v:184884.7-184884.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + attribute \src "libresoc.v:187188.7-187188.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 - attribute \src "libresoc.v:184888.7-184888.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + attribute \src "libresoc.v:187192.7-187192.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 - attribute \src "libresoc.v:184892.7-184892.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + attribute \src "libresoc.v:187196.7-187196.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 - attribute \src "libresoc.v:184896.7-184896.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + attribute \src "libresoc.v:187200.7-187200.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 - attribute \src "libresoc.v:184900.7-184900.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + attribute \src "libresoc.v:187204.7-187204.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:185691.3-185699.6" - wire $1\alui_l_r_alui$next[0:0]$12491 - attribute \src "libresoc.v:184912.7-184912.27" + attribute \src "libresoc.v:187995.3-188003.6" + wire $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187216.7-187216.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $1\data_r0__o$next[63:0]$12453 - attribute \src "libresoc.v:184946.14-184946.47" + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $1\data_r0__o$next[63:0]$12637 + attribute \src "libresoc.v:187250.14-187250.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire $1\data_r0__o_ok$next[0:0]$12454 - attribute \src "libresoc.v:184950.7-184950.27" + attribute \src "libresoc.v:187879.3-187900.6" + wire $1\data_r0__o_ok$next[0:0]$12638 + attribute \src "libresoc.v:187254.7-187254.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12461 - attribute \src "libresoc.v:184954.13-184954.33" + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12645 + attribute \src "libresoc.v:187258.13-187258.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12462 - attribute \src "libresoc.v:184958.7-184958.30" + attribute \src "libresoc.v:187901.3-187922.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12646 + attribute \src "libresoc.v:187262.7-187262.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12469 - attribute \src "libresoc.v:184962.13-184962.35" + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 + attribute \src "libresoc.v:187266.13-187266.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12470 - attribute \src "libresoc.v:184966.7-184966.32" + attribute \src "libresoc.v:187923.3-187944.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12654 + attribute \src "libresoc.v:187270.7-187270.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:185709.3-185718.6" + attribute \src "libresoc.v:188013.3-188022.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:185719.3-185728.6" + attribute \src "libresoc.v:188023.3-188032.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:185729.3-185738.6" + attribute \src "libresoc.v:188033.3-188042.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:185492.3-185500.6" - wire $1\opc_l_r_opc$next[0:0]$12396 - attribute \src "libresoc.v:184983.7-184983.25" + attribute \src "libresoc.v:187796.3-187804.6" + wire $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187287.7-187287.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:185483.3-185491.6" - wire $1\opc_l_s_opc$next[0:0]$12393 - attribute \src "libresoc.v:184987.7-184987.25" + attribute \src "libresoc.v:187787.3-187795.6" + wire $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187291.7-187291.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire width 3 $1\prev_wr_go$next[2:0]$12500 - attribute \src "libresoc.v:185119.13-185119.30" + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:187423.13-187423.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:185437.3-185446.6" + attribute \src "libresoc.v:187741.3-187750.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:185528.3-185536.6" - wire width 3 $1\req_l_r_req$next[2:0]$12408 - attribute \src "libresoc.v:185127.13-185127.31" + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187431.13-187431.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:185519.3-185527.6" - wire width 3 $1\req_l_s_req$next[2:0]$12405 - attribute \src "libresoc.v:185131.13-185131.31" + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187435.13-187435.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:185456.3-185464.6" - wire $1\rok_l_r_rdok$next[0:0]$12384 - attribute \src "libresoc.v:185143.7-185143.26" + attribute \src "libresoc.v:187760.3-187768.6" + wire $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187447.7-187447.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:185447.3-185455.6" - wire $1\rok_l_s_rdok$next[0:0]$12381 - attribute \src "libresoc.v:185147.7-185147.26" + attribute \src "libresoc.v:187751.3-187759.6" + wire $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187451.7-187451.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:185474.3-185482.6" - wire $1\rst_l_r_rst$next[0:0]$12390 - attribute \src "libresoc.v:185151.7-185151.25" + attribute \src "libresoc.v:187778.3-187786.6" + wire $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187455.7-187455.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:185465.3-185473.6" - wire $1\rst_l_s_rst$next[0:0]$12387 - attribute \src "libresoc.v:185155.7-185155.25" + attribute \src "libresoc.v:187769.3-187777.6" + wire $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187459.7-187459.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:185510.3-185518.6" - wire width 5 $1\src_l_r_src$next[4:0]$12402 - attribute \src "libresoc.v:185173.13-185173.32" + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187477.13-187477.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:185501.3-185509.6" - wire width 5 $1\src_l_s_src$next[4:0]$12399 - attribute \src "libresoc.v:185177.13-185177.32" + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187481.13-187481.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:185641.3-185650.6" - wire width 64 $1\src_r0$next[63:0]$12476 - attribute \src "libresoc.v:185183.14-185183.43" + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187487.14-187487.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:185651.3-185660.6" - wire width 64 $1\src_r1$next[63:0]$12479 - attribute \src "libresoc.v:185187.14-185187.43" + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187491.14-187491.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:185661.3-185670.6" - wire width 64 $1\src_r2$next[63:0]$12482 - attribute \src "libresoc.v:185191.14-185191.43" + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187495.14-187495.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:185671.3-185680.6" - wire $1\src_r3$next[0:0]$12485 - attribute \src "libresoc.v:185195.7-185195.20" + attribute \src "libresoc.v:187975.3-187984.6" + wire $1\src_r3$next[0:0]$12669 + attribute \src "libresoc.v:187499.7-187499.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:185681.3-185690.6" - wire width 2 $1\src_r4$next[1:0]$12488 - attribute \src "libresoc.v:185199.13-185199.26" + attribute \src "libresoc.v:187985.3-187994.6" + wire width 2 $1\src_r4$next[1:0]$12672 + attribute \src "libresoc.v:187503.13-187503.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $2\data_r0__o$next[63:0]$12455 - attribute \src "libresoc.v:185575.3-185596.6" - wire $2\data_r0__o_ok$next[0:0]$12456 - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12463 - attribute \src "libresoc.v:185597.3-185618.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12464 - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12471 - attribute \src "libresoc.v:185619.3-185640.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12472 - attribute \src "libresoc.v:185575.3-185596.6" - wire $3\data_r0__o_ok$next[0:0]$12457 - attribute \src "libresoc.v:185597.3-185618.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12465 - attribute \src "libresoc.v:185619.3-185640.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12473 - attribute \src "libresoc.v:185209.19-185209.114" - wire width 5 $and$libresoc.v:185209$12277_Y - attribute \src "libresoc.v:185210.19-185210.125" - wire $and$libresoc.v:185210$12278_Y - attribute \src "libresoc.v:185211.19-185211.125" - wire $and$libresoc.v:185211$12279_Y - attribute \src "libresoc.v:185212.19-185212.125" - wire $and$libresoc.v:185212$12280_Y - attribute \src "libresoc.v:185213.18-185213.110" - wire $and$libresoc.v:185213$12281_Y - attribute \src "libresoc.v:185214.19-185214.141" - wire width 3 $and$libresoc.v:185214$12282_Y - attribute \src "libresoc.v:185215.19-185215.121" - wire width 3 $and$libresoc.v:185215$12283_Y - attribute \src "libresoc.v:185216.19-185216.127" - wire $and$libresoc.v:185216$12284_Y - attribute \src "libresoc.v:185217.19-185217.127" - wire $and$libresoc.v:185217$12285_Y - attribute \src "libresoc.v:185218.19-185218.127" - wire $and$libresoc.v:185218$12286_Y - attribute \src "libresoc.v:185220.18-185220.98" - wire $and$libresoc.v:185220$12288_Y - attribute \src "libresoc.v:185222.18-185222.100" - wire $and$libresoc.v:185222$12290_Y - attribute \src "libresoc.v:185223.18-185223.149" - wire width 3 $and$libresoc.v:185223$12291_Y - attribute \src "libresoc.v:185225.18-185225.119" - wire width 3 $and$libresoc.v:185225$12293_Y - attribute \src "libresoc.v:185228.17-185228.123" - wire $and$libresoc.v:185228$12296_Y - attribute \src "libresoc.v:185229.18-185229.116" - wire $and$libresoc.v:185229$12297_Y - attribute \src "libresoc.v:185234.18-185234.113" - wire $and$libresoc.v:185234$12302_Y - attribute \src "libresoc.v:185235.18-185235.125" - wire width 3 $and$libresoc.v:185235$12303_Y - attribute \src "libresoc.v:185237.18-185237.112" - wire $and$libresoc.v:185237$12305_Y - attribute \src "libresoc.v:185239.18-185239.132" - wire $and$libresoc.v:185239$12307_Y - attribute \src "libresoc.v:185240.18-185240.132" - wire $and$libresoc.v:185240$12308_Y - attribute \src "libresoc.v:185241.18-185241.117" - wire $and$libresoc.v:185241$12309_Y - attribute \src "libresoc.v:185247.18-185247.136" - wire $and$libresoc.v:185247$12315_Y - attribute \src "libresoc.v:185248.18-185248.124" - wire width 3 $and$libresoc.v:185248$12316_Y - attribute \src "libresoc.v:185250.18-185250.116" - wire $and$libresoc.v:185250$12318_Y - attribute \src "libresoc.v:185251.18-185251.119" - wire $and$libresoc.v:185251$12319_Y - attribute \src "libresoc.v:185252.18-185252.121" - wire $and$libresoc.v:185252$12320_Y - attribute \src "libresoc.v:185262.18-185262.140" - wire $and$libresoc.v:185262$12330_Y - attribute \src "libresoc.v:185263.18-185263.138" - wire $and$libresoc.v:185263$12331_Y - attribute \src "libresoc.v:185264.18-185264.171" - wire width 5 $and$libresoc.v:185264$12332_Y - attribute \src "libresoc.v:185266.18-185266.129" - wire width 5 $and$libresoc.v:185266$12334_Y - attribute \src "libresoc.v:185236.18-185236.113" - wire $eq$libresoc.v:185236$12304_Y - attribute \src "libresoc.v:185238.18-185238.119" - wire $eq$libresoc.v:185238$12306_Y - attribute \src "libresoc.v:185208.19-185208.115" - wire width 5 $not$libresoc.v:185208$12276_Y - attribute \src "libresoc.v:185219.18-185219.97" - wire $not$libresoc.v:185219$12287_Y - attribute \src "libresoc.v:185221.18-185221.99" - wire $not$libresoc.v:185221$12289_Y - attribute \src "libresoc.v:185224.18-185224.113" - wire width 3 $not$libresoc.v:185224$12292_Y - attribute \src "libresoc.v:185227.18-185227.106" - wire $not$libresoc.v:185227$12295_Y - attribute \src "libresoc.v:185233.18-185233.126" - wire $not$libresoc.v:185233$12301_Y - attribute \src "libresoc.v:185244.17-185244.113" - wire width 5 $not$libresoc.v:185244$12312_Y - attribute \src "libresoc.v:185265.18-185265.136" - wire $not$libresoc.v:185265$12333_Y - attribute \src "libresoc.v:185232.18-185232.112" - wire $or$libresoc.v:185232$12300_Y - attribute \src "libresoc.v:185242.18-185242.122" - wire $or$libresoc.v:185242$12310_Y - attribute \src "libresoc.v:185243.18-185243.124" - wire $or$libresoc.v:185243$12311_Y - attribute \src "libresoc.v:185245.18-185245.155" - wire width 3 $or$libresoc.v:185245$12313_Y - attribute \src "libresoc.v:185246.18-185246.181" - wire width 5 $or$libresoc.v:185246$12314_Y - attribute \src "libresoc.v:185249.18-185249.120" - wire width 3 $or$libresoc.v:185249$12317_Y - attribute \src "libresoc.v:185255.17-185255.117" - wire width 5 $or$libresoc.v:185255$12323_Y - attribute \src "libresoc.v:185261.17-185261.104" - wire $reduce_and$libresoc.v:185261$12329_Y - attribute \src "libresoc.v:185226.18-185226.106" - wire $reduce_or$libresoc.v:185226$12294_Y - attribute \src "libresoc.v:185230.18-185230.113" - wire $reduce_or$libresoc.v:185230$12298_Y - attribute \src "libresoc.v:185231.18-185231.112" - wire $reduce_or$libresoc.v:185231$12299_Y - attribute \src "libresoc.v:185253.18-185253.165" - wire $ternary$libresoc.v:185253$12321_Y - attribute \src "libresoc.v:185254.18-185254.182" - wire width 64 $ternary$libresoc.v:185254$12322_Y - attribute \src "libresoc.v:185256.18-185256.118" - wire width 64 $ternary$libresoc.v:185256$12324_Y - attribute \src "libresoc.v:185257.18-185257.115" - wire width 64 $ternary$libresoc.v:185257$12325_Y - attribute \src "libresoc.v:185258.18-185258.118" - wire width 64 $ternary$libresoc.v:185258$12326_Y - attribute \src "libresoc.v:185259.18-185259.118" - wire $ternary$libresoc.v:185259$12327_Y - attribute \src "libresoc.v:185260.18-185260.118" - wire width 2 $ternary$libresoc.v:185260$12328_Y + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $2\data_r0__o$next[63:0]$12639 + attribute \src "libresoc.v:187879.3-187900.6" + wire $2\data_r0__o_ok$next[0:0]$12640 + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12647 + attribute \src "libresoc.v:187901.3-187922.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12648 + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12655 + attribute \src "libresoc.v:187923.3-187944.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12656 + attribute \src "libresoc.v:187879.3-187900.6" + wire $3\data_r0__o_ok$next[0:0]$12641 + attribute \src "libresoc.v:187901.3-187922.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12649 + attribute \src "libresoc.v:187923.3-187944.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12657 + attribute \src "libresoc.v:187513.19-187513.114" + wire width 5 $and$libresoc.v:187513$12461_Y + attribute \src "libresoc.v:187514.19-187514.125" + wire $and$libresoc.v:187514$12462_Y + attribute \src "libresoc.v:187515.19-187515.125" + wire $and$libresoc.v:187515$12463_Y + attribute \src "libresoc.v:187516.19-187516.125" + wire $and$libresoc.v:187516$12464_Y + attribute \src "libresoc.v:187517.18-187517.110" + wire $and$libresoc.v:187517$12465_Y + attribute \src "libresoc.v:187518.19-187518.141" + wire width 3 $and$libresoc.v:187518$12466_Y + attribute \src "libresoc.v:187519.19-187519.121" + wire width 3 $and$libresoc.v:187519$12467_Y + attribute \src "libresoc.v:187520.19-187520.127" + wire $and$libresoc.v:187520$12468_Y + attribute \src "libresoc.v:187521.19-187521.127" + wire $and$libresoc.v:187521$12469_Y + attribute \src "libresoc.v:187522.19-187522.127" + wire $and$libresoc.v:187522$12470_Y + attribute \src "libresoc.v:187524.18-187524.98" + wire $and$libresoc.v:187524$12472_Y + attribute \src "libresoc.v:187526.18-187526.100" + wire $and$libresoc.v:187526$12474_Y + attribute \src "libresoc.v:187527.18-187527.149" + wire width 3 $and$libresoc.v:187527$12475_Y + attribute \src "libresoc.v:187529.18-187529.119" + wire width 3 $and$libresoc.v:187529$12477_Y + attribute \src "libresoc.v:187532.17-187532.123" + wire $and$libresoc.v:187532$12480_Y + attribute \src "libresoc.v:187533.18-187533.116" + wire $and$libresoc.v:187533$12481_Y + attribute \src "libresoc.v:187538.18-187538.113" + wire $and$libresoc.v:187538$12486_Y + attribute \src "libresoc.v:187539.18-187539.125" + wire width 3 $and$libresoc.v:187539$12487_Y + attribute \src "libresoc.v:187541.18-187541.112" + wire $and$libresoc.v:187541$12489_Y + attribute \src "libresoc.v:187543.18-187543.132" + wire $and$libresoc.v:187543$12491_Y + attribute \src "libresoc.v:187544.18-187544.132" + wire $and$libresoc.v:187544$12492_Y + attribute \src "libresoc.v:187545.18-187545.117" + wire $and$libresoc.v:187545$12493_Y + attribute \src "libresoc.v:187551.18-187551.136" + wire $and$libresoc.v:187551$12499_Y + attribute \src "libresoc.v:187552.18-187552.124" + wire width 3 $and$libresoc.v:187552$12500_Y + attribute \src "libresoc.v:187554.18-187554.116" + wire $and$libresoc.v:187554$12502_Y + attribute \src "libresoc.v:187555.18-187555.119" + wire $and$libresoc.v:187555$12503_Y + attribute \src "libresoc.v:187556.18-187556.121" + wire $and$libresoc.v:187556$12504_Y + attribute \src "libresoc.v:187566.18-187566.140" + wire $and$libresoc.v:187566$12514_Y + attribute \src "libresoc.v:187567.18-187567.138" + wire $and$libresoc.v:187567$12515_Y + attribute \src "libresoc.v:187568.18-187568.171" + wire width 5 $and$libresoc.v:187568$12516_Y + attribute \src "libresoc.v:187570.18-187570.129" + wire width 5 $and$libresoc.v:187570$12518_Y + attribute \src "libresoc.v:187540.18-187540.113" + wire $eq$libresoc.v:187540$12488_Y + attribute \src "libresoc.v:187542.18-187542.119" + wire $eq$libresoc.v:187542$12490_Y + attribute \src "libresoc.v:187512.19-187512.115" + wire width 5 $not$libresoc.v:187512$12460_Y + attribute \src "libresoc.v:187523.18-187523.97" + wire $not$libresoc.v:187523$12471_Y + attribute \src "libresoc.v:187525.18-187525.99" + wire $not$libresoc.v:187525$12473_Y + attribute \src "libresoc.v:187528.18-187528.113" + wire width 3 $not$libresoc.v:187528$12476_Y + attribute \src "libresoc.v:187531.18-187531.106" + wire $not$libresoc.v:187531$12479_Y + attribute \src "libresoc.v:187537.18-187537.126" + wire $not$libresoc.v:187537$12485_Y + attribute \src "libresoc.v:187548.17-187548.113" + wire width 5 $not$libresoc.v:187548$12496_Y + attribute \src "libresoc.v:187569.18-187569.136" + wire $not$libresoc.v:187569$12517_Y + attribute \src "libresoc.v:187536.18-187536.112" + wire $or$libresoc.v:187536$12484_Y + attribute \src "libresoc.v:187546.18-187546.122" + wire $or$libresoc.v:187546$12494_Y + attribute \src "libresoc.v:187547.18-187547.124" + wire $or$libresoc.v:187547$12495_Y + attribute \src "libresoc.v:187549.18-187549.155" + wire width 3 $or$libresoc.v:187549$12497_Y + attribute \src "libresoc.v:187550.18-187550.181" + wire width 5 $or$libresoc.v:187550$12498_Y + attribute \src "libresoc.v:187553.18-187553.120" + wire width 3 $or$libresoc.v:187553$12501_Y + attribute \src "libresoc.v:187559.17-187559.117" + wire width 5 $or$libresoc.v:187559$12507_Y + attribute \src "libresoc.v:187565.17-187565.104" + wire $reduce_and$libresoc.v:187565$12513_Y + attribute \src "libresoc.v:187530.18-187530.106" + wire $reduce_or$libresoc.v:187530$12478_Y + attribute \src "libresoc.v:187534.18-187534.113" + wire $reduce_or$libresoc.v:187534$12482_Y + attribute \src "libresoc.v:187535.18-187535.112" + wire $reduce_or$libresoc.v:187535$12483_Y + attribute \src "libresoc.v:187557.18-187557.165" + wire $ternary$libresoc.v:187557$12505_Y + attribute \src "libresoc.v:187558.18-187558.182" + wire width 64 $ternary$libresoc.v:187558$12506_Y + attribute \src "libresoc.v:187560.18-187560.118" + wire width 64 $ternary$libresoc.v:187560$12508_Y + attribute \src "libresoc.v:187561.18-187561.115" + wire width 64 $ternary$libresoc.v:187561$12509_Y + attribute \src "libresoc.v:187562.18-187562.118" + wire width 64 $ternary$libresoc.v:187562$12510_Y + attribute \src "libresoc.v:187563.18-187563.118" + wire $ternary$libresoc.v:187563$12511_Y + attribute \src "libresoc.v:187564.18-187564.118" + wire width 2 $ternary$libresoc.v:187564$12512_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -384631,9 +388640,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -384689,7 +388698,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:184574.7-184574.15" + attribute \src "libresoc.v:186878.7-186878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -384922,7 +388931,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185209$12277 + cell $and $and$libresoc.v:187513$12461 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384930,10 +388939,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:185209$12277_Y + connect \Y $and$libresoc.v:187513$12461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185210$12278 + cell $and $and$libresoc.v:187514$12462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384941,10 +388950,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185210$12278_Y + connect \Y $and$libresoc.v:187514$12462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185211$12279 + cell $and $and$libresoc.v:187515$12463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384952,10 +388961,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185211$12279_Y + connect \Y $and$libresoc.v:187515$12463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185212$12280 + cell $and $and$libresoc.v:187516$12464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384963,10 +388972,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185212$12280_Y + connect \Y $and$libresoc.v:187516$12464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:185213$12281 + cell $and $and$libresoc.v:187517$12465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384974,10 +388983,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:185213$12281_Y + connect \Y $and$libresoc.v:187517$12465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:185214$12282 + cell $and $and$libresoc.v:187518$12466 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384985,10 +388994,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:185214$12282_Y + connect \Y $and$libresoc.v:187518$12466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:185215$12283 + cell $and $and$libresoc.v:187519$12467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384996,10 +389005,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185215$12283_Y + connect \Y $and$libresoc.v:187519$12467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185216$12284 + cell $and $and$libresoc.v:187520$12468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385007,10 +389016,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185216$12284_Y + connect \Y $and$libresoc.v:187520$12468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185217$12285 + cell $and $and$libresoc.v:187521$12469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385018,10 +389027,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185217$12285_Y + connect \Y $and$libresoc.v:187521$12469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185218$12286 + cell $and $and$libresoc.v:187522$12470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385029,10 +389038,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185218$12286_Y + connect \Y $and$libresoc.v:187522$12470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:185220$12288 + cell $and $and$libresoc.v:187524$12472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385040,10 +389049,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:185220$12288_Y + connect \Y $and$libresoc.v:187524$12472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:185222$12290 + cell $and $and$libresoc.v:187526$12474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385051,10 +389060,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:185222$12290_Y + connect \Y $and$libresoc.v:187526$12474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:185223$12291 + cell $and $and$libresoc.v:187527$12475 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385062,10 +389071,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:185223$12291_Y + connect \Y $and$libresoc.v:187527$12475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:185225$12293 + cell $and $and$libresoc.v:187529$12477 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385073,10 +389082,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:185225$12293_Y + connect \Y $and$libresoc.v:187529$12477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:185228$12296 + cell $and $and$libresoc.v:187532$12480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385084,10 +389093,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:185228$12296_Y + connect \Y $and$libresoc.v:187532$12480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:185229$12297 + cell $and $and$libresoc.v:187533$12481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385095,10 +389104,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:185229$12297_Y + connect \Y $and$libresoc.v:187533$12481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:185234$12302 + cell $and $and$libresoc.v:187538$12486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385106,10 +389115,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:185234$12302_Y + connect \Y $and$libresoc.v:187538$12486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:185235$12303 + cell $and $and$libresoc.v:187539$12487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385117,10 +389126,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185235$12303_Y + connect \Y $and$libresoc.v:187539$12487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:185237$12305 + cell $and $and$libresoc.v:187541$12489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385128,10 +389137,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:185237$12305_Y + connect \Y $and$libresoc.v:187541$12489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185239$12307 + cell $and $and$libresoc.v:187543$12491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385139,10 +389148,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:185239$12307_Y + connect \Y $and$libresoc.v:187543$12491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185240$12308 + cell $and $and$libresoc.v:187544$12492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385150,10 +389159,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:185240$12308_Y + connect \Y $and$libresoc.v:187544$12492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185241$12309 + cell $and $and$libresoc.v:187545$12493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385161,10 +389170,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:185241$12309_Y + connect \Y $and$libresoc.v:187545$12493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:185247$12315 + cell $and $and$libresoc.v:187551$12499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385172,10 +389181,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:185247$12315_Y + connect \Y $and$libresoc.v:187551$12499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:185248$12316 + cell $and $and$libresoc.v:187552$12500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385183,10 +389192,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185248$12316_Y + connect \Y $and$libresoc.v:187552$12500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185250$12318 + cell $and $and$libresoc.v:187554$12502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385194,10 +389203,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185250$12318_Y + connect \Y $and$libresoc.v:187554$12502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185251$12319 + cell $and $and$libresoc.v:187555$12503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385205,10 +389214,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185251$12319_Y + connect \Y $and$libresoc.v:187555$12503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185252$12320 + cell $and $and$libresoc.v:187556$12504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385216,10 +389225,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185252$12320_Y + connect \Y $and$libresoc.v:187556$12504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:185262$12330 + cell $and $and$libresoc.v:187566$12514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385227,10 +389236,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:185262$12330_Y + connect \Y $and$libresoc.v:187566$12514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:185263$12331 + cell $and $and$libresoc.v:187567$12515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385238,10 +389247,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:185263$12331_Y + connect \Y $and$libresoc.v:187567$12515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185264$12332 + cell $and $and$libresoc.v:187568$12516 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385249,10 +389258,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:185264$12332_Y + connect \Y $and$libresoc.v:187568$12516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185266$12334 + cell $and $and$libresoc.v:187570$12518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385260,10 +389269,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:185266$12334_Y + connect \Y $and$libresoc.v:187570$12518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:185236$12304 + cell $eq $eq$libresoc.v:187540$12488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385271,10 +389280,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:185236$12304_Y + connect \Y $eq$libresoc.v:187540$12488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:185238$12306 + cell $eq $eq$libresoc.v:187542$12490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385282,74 +389291,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:185238$12306_Y + connect \Y $eq$libresoc.v:187542$12490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:185208$12276 + cell $not $not$libresoc.v:187512$12460 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:185208$12276_Y + connect \Y $not$libresoc.v:187512$12460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:185219$12287 + cell $not $not$libresoc.v:187523$12471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:185219$12287_Y + connect \Y $not$libresoc.v:187523$12471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:185221$12289 + cell $not $not$libresoc.v:187525$12473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:185221$12289_Y + connect \Y $not$libresoc.v:187525$12473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:185224$12292 + cell $not $not$libresoc.v:187528$12476 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:185224$12292_Y + connect \Y $not$libresoc.v:187528$12476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:185227$12295 + cell $not $not$libresoc.v:187531$12479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:185227$12295_Y + connect \Y $not$libresoc.v:187531$12479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:185233$12301 + cell $not $not$libresoc.v:187537$12485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:185233$12301_Y + connect \Y $not$libresoc.v:187537$12485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:185244$12312 + cell $not $not$libresoc.v:187548$12496 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:185244$12312_Y + connect \Y $not$libresoc.v:187548$12496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:185265$12333 + cell $not $not$libresoc.v:187569$12517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:185265$12333_Y + connect \Y $not$libresoc.v:187569$12517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:185232$12300 + cell $or $or$libresoc.v:187536$12484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385357,10 +389366,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:185232$12300_Y + connect \Y $or$libresoc.v:187536$12484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:185242$12310 + cell $or $or$libresoc.v:187546$12494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385368,10 +389377,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:185242$12310_Y + connect \Y $or$libresoc.v:187546$12494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:185243$12311 + cell $or $or$libresoc.v:187547$12495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385379,10 +389388,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:185243$12311_Y + connect \Y $or$libresoc.v:187547$12495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:185245$12313 + cell $or $or$libresoc.v:187549$12497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385390,10 +389399,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:185245$12313_Y + connect \Y $or$libresoc.v:187549$12497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:185246$12314 + cell $or $or$libresoc.v:187550$12498 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385401,10 +389410,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:185246$12314_Y + connect \Y $or$libresoc.v:187550$12498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:185249$12317 + cell $or $or$libresoc.v:187553$12501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385412,10 +389421,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:185249$12317_Y + connect \Y $or$libresoc.v:187553$12501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:185255$12323 + cell $or $or$libresoc.v:187559$12507 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385423,98 +389432,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:185255$12323_Y + connect \Y $or$libresoc.v:187559$12507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:185261$12329 + cell $reduce_and $reduce_and$libresoc.v:187565$12513 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:185261$12329_Y + connect \Y $reduce_and$libresoc.v:187565$12513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:185226$12294 + cell $reduce_or $reduce_or$libresoc.v:187530$12478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:185226$12294_Y + connect \Y $reduce_or$libresoc.v:187530$12478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:185230$12298 + cell $reduce_or $reduce_or$libresoc.v:187534$12482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:185230$12298_Y + connect \Y $reduce_or$libresoc.v:187534$12482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:185231$12299 + cell $reduce_or $reduce_or$libresoc.v:187535$12483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:185231$12299_Y + connect \Y $reduce_or$libresoc.v:187535$12483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:185253$12321 + cell $mux $ternary$libresoc.v:187557$12505 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:185253$12321_Y + connect \Y $ternary$libresoc.v:187557$12505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:185254$12322 + cell $mux $ternary$libresoc.v:187558$12506 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:185254$12322_Y + connect \Y $ternary$libresoc.v:187558$12506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185256$12324 + cell $mux $ternary$libresoc.v:187560$12508 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:185256$12324_Y + connect \Y $ternary$libresoc.v:187560$12508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185257$12325 + cell $mux $ternary$libresoc.v:187561$12509 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:185257$12325_Y + connect \Y $ternary$libresoc.v:187561$12509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185258$12326 + cell $mux $ternary$libresoc.v:187562$12510 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:185258$12326_Y + connect \Y $ternary$libresoc.v:187562$12510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185259$12327 + cell $mux $ternary$libresoc.v:187563$12511 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:185259$12327_Y + connect \Y $ternary$libresoc.v:187563$12511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185260$12328 + cell $mux $ternary$libresoc.v:187564$12512 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:185260$12328_Y + connect \Y $ternary$libresoc.v:187564$12512_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185353.15-185359.4" + attribute \src "libresoc.v:187657.15-187663.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385523,7 +389532,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:185360.18-185395.4" + attribute \src "libresoc.v:187664.18-187699.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385561,7 +389570,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:185396.16-185402.4" + attribute \src "libresoc.v:187700.16-187706.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385570,7 +389579,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:185403.15-185409.4" + attribute \src "libresoc.v:187707.15-187713.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385579,7 +389588,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:185410.15-185416.4" + attribute \src "libresoc.v:187714.15-187720.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385588,7 +389597,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:185417.15-185423.4" + attribute \src "libresoc.v:187721.15-187727.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385597,7 +389606,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:185424.15-185429.4" + attribute \src "libresoc.v:187728.15-187733.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385605,7 +389614,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:185430.15-185436.4" + attribute \src "libresoc.v:187734.15-187740.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385613,667 +389622,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:184574.7-184574.20" - process $proc$libresoc.v:184574$12501 + attribute \src "libresoc.v:186878.7-186878.20" + process $proc$libresoc.v:186878$12685 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184696.7-184696.24" - process $proc$libresoc.v:184696$12502 + attribute \src "libresoc.v:187000.7-187000.24" + process $proc$libresoc.v:187000$12686 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:184706.7-184706.26" - process $proc$libresoc.v:184706$12503 + attribute \src "libresoc.v:187010.7-187010.26" + process $proc$libresoc.v:187010$12687 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:184714.7-184714.25" - process $proc$libresoc.v:184714$12504 + attribute \src "libresoc.v:187018.7-187018.25" + process $proc$libresoc.v:187018$12688 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:184757.14-184757.54" - process $proc$libresoc.v:184757$12505 + attribute \src "libresoc.v:187061.14-187061.54" + process $proc$libresoc.v:187061$12689 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:184761.14-184761.73" - process $proc$libresoc.v:184761$12506 + attribute \src "libresoc.v:187065.14-187065.73" + process $proc$libresoc.v:187065$12690 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:184765.7-184765.48" - process $proc$libresoc.v:184765$12507 + attribute \src "libresoc.v:187069.7-187069.48" + process $proc$libresoc.v:187069$12691 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:184773.13-184773.53" - process $proc$libresoc.v:184773$12508 + attribute \src "libresoc.v:187077.13-187077.53" + process $proc$libresoc.v:187077$12692 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:184777.7-184777.44" - process $proc$libresoc.v:184777$12509 + attribute \src "libresoc.v:187081.7-187081.44" + process $proc$libresoc.v:187081$12693 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:184781.14-184781.48" - process $proc$libresoc.v:184781$12510 + attribute \src "libresoc.v:187085.14-187085.48" + process $proc$libresoc.v:187085$12694 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:184860.13-184860.52" - process $proc$libresoc.v:184860$12511 + attribute \src "libresoc.v:187164.13-187164.52" + process $proc$libresoc.v:187164$12695 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:184864.7-184864.45" - process $proc$libresoc.v:184864$12512 + attribute \src "libresoc.v:187168.7-187168.45" + process $proc$libresoc.v:187168$12696 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:184868.7-184868.44" - process $proc$libresoc.v:184868$12513 + attribute \src "libresoc.v:187172.7-187172.44" + process $proc$libresoc.v:187172$12697 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:184872.7-184872.45" - process $proc$libresoc.v:184872$12514 + attribute \src "libresoc.v:187176.7-187176.45" + process $proc$libresoc.v:187176$12698 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:184876.7-184876.42" - process $proc$libresoc.v:184876$12515 + attribute \src "libresoc.v:187180.7-187180.42" + process $proc$libresoc.v:187180$12699 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:184880.7-184880.42" - process $proc$libresoc.v:184880$12516 + attribute \src "libresoc.v:187184.7-187184.42" + process $proc$libresoc.v:187184$12700 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:184884.7-184884.48" - process $proc$libresoc.v:184884$12517 + attribute \src "libresoc.v:187188.7-187188.48" + process $proc$libresoc.v:187188$12701 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:184888.7-184888.45" - process $proc$libresoc.v:184888$12518 + attribute \src "libresoc.v:187192.7-187192.45" + process $proc$libresoc.v:187192$12702 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:184892.7-184892.42" - process $proc$libresoc.v:184892$12519 + attribute \src "libresoc.v:187196.7-187196.42" + process $proc$libresoc.v:187196$12703 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:184896.7-184896.42" - process $proc$libresoc.v:184896$12520 + attribute \src "libresoc.v:187200.7-187200.42" + process $proc$libresoc.v:187200$12704 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:184900.7-184900.45" - process $proc$libresoc.v:184900$12521 + attribute \src "libresoc.v:187204.7-187204.45" + process $proc$libresoc.v:187204$12705 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:184912.7-184912.27" - process $proc$libresoc.v:184912$12522 + attribute \src "libresoc.v:187216.7-187216.27" + process $proc$libresoc.v:187216$12706 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:184946.14-184946.47" - process $proc$libresoc.v:184946$12523 + attribute \src "libresoc.v:187250.14-187250.47" + process $proc$libresoc.v:187250$12707 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:184950.7-184950.27" - process $proc$libresoc.v:184950$12524 + attribute \src "libresoc.v:187254.7-187254.27" + process $proc$libresoc.v:187254$12708 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:184954.13-184954.33" - process $proc$libresoc.v:184954$12525 + attribute \src "libresoc.v:187258.13-187258.33" + process $proc$libresoc.v:187258$12709 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:184958.7-184958.30" - process $proc$libresoc.v:184958$12526 + attribute \src "libresoc.v:187262.7-187262.30" + process $proc$libresoc.v:187262$12710 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:184962.13-184962.35" - process $proc$libresoc.v:184962$12527 + attribute \src "libresoc.v:187266.13-187266.35" + process $proc$libresoc.v:187266$12711 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:184966.7-184966.32" - process $proc$libresoc.v:184966$12528 + attribute \src "libresoc.v:187270.7-187270.32" + process $proc$libresoc.v:187270$12712 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:184983.7-184983.25" - process $proc$libresoc.v:184983$12529 + attribute \src "libresoc.v:187287.7-187287.25" + process $proc$libresoc.v:187287$12713 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:184987.7-184987.25" - process $proc$libresoc.v:184987$12530 + attribute \src "libresoc.v:187291.7-187291.25" + process $proc$libresoc.v:187291$12714 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:185119.13-185119.30" - process $proc$libresoc.v:185119$12531 + attribute \src "libresoc.v:187423.13-187423.30" + process $proc$libresoc.v:187423$12715 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:185127.13-185127.31" - process $proc$libresoc.v:185127$12532 + attribute \src "libresoc.v:187431.13-187431.31" + process $proc$libresoc.v:187431$12716 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:185131.13-185131.31" - process $proc$libresoc.v:185131$12533 + attribute \src "libresoc.v:187435.13-187435.31" + process $proc$libresoc.v:187435$12717 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:185143.7-185143.26" - process $proc$libresoc.v:185143$12534 + attribute \src "libresoc.v:187447.7-187447.26" + process $proc$libresoc.v:187447$12718 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:185147.7-185147.26" - process $proc$libresoc.v:185147$12535 + attribute \src "libresoc.v:187451.7-187451.26" + process $proc$libresoc.v:187451$12719 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:185151.7-185151.25" - process $proc$libresoc.v:185151$12536 + attribute \src "libresoc.v:187455.7-187455.25" + process $proc$libresoc.v:187455$12720 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:185155.7-185155.25" - process $proc$libresoc.v:185155$12537 + attribute \src "libresoc.v:187459.7-187459.25" + process $proc$libresoc.v:187459$12721 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:185173.13-185173.32" - process $proc$libresoc.v:185173$12538 + attribute \src "libresoc.v:187477.13-187477.32" + process $proc$libresoc.v:187477$12722 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:185177.13-185177.32" - process $proc$libresoc.v:185177$12539 + attribute \src "libresoc.v:187481.13-187481.32" + process $proc$libresoc.v:187481$12723 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:185183.14-185183.43" - process $proc$libresoc.v:185183$12540 + attribute \src "libresoc.v:187487.14-187487.43" + process $proc$libresoc.v:187487$12724 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:185187.14-185187.43" - process $proc$libresoc.v:185187$12541 + attribute \src "libresoc.v:187491.14-187491.43" + process $proc$libresoc.v:187491$12725 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:185191.14-185191.43" - process $proc$libresoc.v:185191$12542 + attribute \src "libresoc.v:187495.14-187495.43" + process $proc$libresoc.v:187495$12726 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:185195.7-185195.20" - process $proc$libresoc.v:185195$12543 + attribute \src "libresoc.v:187499.7-187499.20" + process $proc$libresoc.v:187499$12727 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:185199.13-185199.26" - process $proc$libresoc.v:185199$12544 + attribute \src "libresoc.v:187503.13-187503.26" + process $proc$libresoc.v:187503$12728 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:185267.3-185268.39" - process $proc$libresoc.v:185267$12335 + attribute \src "libresoc.v:187571.3-187572.39" + process $proc$libresoc.v:187571$12519 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:185269.3-185270.43" - process $proc$libresoc.v:185269$12336 + attribute \src "libresoc.v:187573.3-187574.43" + process $proc$libresoc.v:187573$12520 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:185271.3-185272.29" - process $proc$libresoc.v:185271$12337 + attribute \src "libresoc.v:187575.3-187576.29" + process $proc$libresoc.v:187575$12521 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:185273.3-185274.29" - process $proc$libresoc.v:185273$12338 + attribute \src "libresoc.v:187577.3-187578.29" + process $proc$libresoc.v:187577$12522 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:185275.3-185276.29" - process $proc$libresoc.v:185275$12339 + attribute \src "libresoc.v:187579.3-187580.29" + process $proc$libresoc.v:187579$12523 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:185277.3-185278.29" - process $proc$libresoc.v:185277$12340 + attribute \src "libresoc.v:187581.3-187582.29" + process $proc$libresoc.v:187581$12524 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:185279.3-185280.29" - process $proc$libresoc.v:185279$12341 + attribute \src "libresoc.v:187583.3-187584.29" + process $proc$libresoc.v:187583$12525 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:185281.3-185282.47" - process $proc$libresoc.v:185281$12342 + attribute \src "libresoc.v:187585.3-187586.47" + process $proc$libresoc.v:187585$12526 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:185283.3-185284.53" - process $proc$libresoc.v:185283$12343 + attribute \src "libresoc.v:187587.3-187588.53" + process $proc$libresoc.v:187587$12527 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:185285.3-185286.43" - process $proc$libresoc.v:185285$12344 + attribute \src "libresoc.v:187589.3-187590.43" + process $proc$libresoc.v:187589$12528 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:185287.3-185288.49" - process $proc$libresoc.v:185287$12345 + attribute \src "libresoc.v:187591.3-187592.49" + process $proc$libresoc.v:187591$12529 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:185289.3-185290.37" - process $proc$libresoc.v:185289$12346 + attribute \src "libresoc.v:187593.3-187594.37" + process $proc$libresoc.v:187593$12530 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:185291.3-185292.43" - process $proc$libresoc.v:185291$12347 + attribute \src "libresoc.v:187595.3-187596.43" + process $proc$libresoc.v:187595$12531 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:185293.3-185294.79" - process $proc$libresoc.v:185293$12348 + attribute \src "libresoc.v:187597.3-187598.79" + process $proc$libresoc.v:187597$12532 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:185295.3-185296.75" - process $proc$libresoc.v:185295$12349 + attribute \src "libresoc.v:187599.3-187600.75" + process $proc$libresoc.v:187599$12533 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:185297.3-185298.89" - process $proc$libresoc.v:185297$12350 + attribute \src "libresoc.v:187601.3-187602.89" + process $proc$libresoc.v:187601$12534 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:185299.3-185300.85" - process $proc$libresoc.v:185299$12351 + attribute \src "libresoc.v:187603.3-187604.85" + process $proc$libresoc.v:187603$12535 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:185301.3-185302.73" - process $proc$libresoc.v:185301$12352 + attribute \src "libresoc.v:187605.3-187606.73" + process $proc$libresoc.v:187605$12536 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:185303.3-185304.73" - process $proc$libresoc.v:185303$12353 + attribute \src "libresoc.v:187607.3-187608.73" + process $proc$libresoc.v:187607$12537 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:185305.3-185306.73" - process $proc$libresoc.v:185305$12354 + attribute \src "libresoc.v:187609.3-187610.73" + process $proc$libresoc.v:187609$12538 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:185307.3-185308.73" - process $proc$libresoc.v:185307$12355 + attribute \src "libresoc.v:187611.3-187612.73" + process $proc$libresoc.v:187611$12539 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:185309.3-185310.79" - process $proc$libresoc.v:185309$12356 + attribute \src "libresoc.v:187613.3-187614.79" + process $proc$libresoc.v:187613$12540 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:185311.3-185312.79" - process $proc$libresoc.v:185311$12357 + attribute \src "libresoc.v:187615.3-187616.79" + process $proc$libresoc.v:187615$12541 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:185313.3-185314.83" - process $proc$libresoc.v:185313$12358 + attribute \src "libresoc.v:187617.3-187618.83" + process $proc$libresoc.v:187617$12542 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:185315.3-185316.85" - process $proc$libresoc.v:185315$12359 + attribute \src "libresoc.v:187619.3-187620.85" + process $proc$libresoc.v:187619$12543 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:185317.3-185318.77" - process $proc$libresoc.v:185317$12360 + attribute \src "libresoc.v:187621.3-187622.77" + process $proc$libresoc.v:187621$12544 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:185319.3-185320.79" - process $proc$libresoc.v:185319$12361 + attribute \src "libresoc.v:187623.3-187624.79" + process $proc$libresoc.v:187623$12545 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:185321.3-185322.77" - process $proc$libresoc.v:185321$12362 + attribute \src "libresoc.v:187625.3-187626.77" + process $proc$libresoc.v:187625$12546 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:185323.3-185324.79" - process $proc$libresoc.v:185323$12363 + attribute \src "libresoc.v:187627.3-187628.79" + process $proc$libresoc.v:187627$12547 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:185325.3-185326.69" - process $proc$libresoc.v:185325$12364 + attribute \src "libresoc.v:187629.3-187630.69" + process $proc$libresoc.v:187629$12548 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:185327.3-185328.39" - process $proc$libresoc.v:185327$12365 + attribute \src "libresoc.v:187631.3-187632.39" + process $proc$libresoc.v:187631$12549 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:185329.3-185330.39" - process $proc$libresoc.v:185329$12366 + attribute \src "libresoc.v:187633.3-187634.39" + process $proc$libresoc.v:187633$12550 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:185331.3-185332.39" - process $proc$libresoc.v:185331$12367 + attribute \src "libresoc.v:187635.3-187636.39" + process $proc$libresoc.v:187635$12551 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:185333.3-185334.39" - process $proc$libresoc.v:185333$12368 + attribute \src "libresoc.v:187637.3-187638.39" + process $proc$libresoc.v:187637$12552 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:185335.3-185336.39" - process $proc$libresoc.v:185335$12369 + attribute \src "libresoc.v:187639.3-187640.39" + process $proc$libresoc.v:187639$12553 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:185337.3-185338.39" - process $proc$libresoc.v:185337$12370 + attribute \src "libresoc.v:187641.3-187642.39" + process $proc$libresoc.v:187641$12554 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:185339.3-185340.39" - process $proc$libresoc.v:185339$12371 + attribute \src "libresoc.v:187643.3-187644.39" + process $proc$libresoc.v:187643$12555 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:185341.3-185342.39" - process $proc$libresoc.v:185341$12372 + attribute \src "libresoc.v:187645.3-187646.39" + process $proc$libresoc.v:187645$12556 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:185343.3-185344.41" - process $proc$libresoc.v:185343$12373 + attribute \src "libresoc.v:187647.3-187648.41" + process $proc$libresoc.v:187647$12557 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:185345.3-185346.41" - process $proc$libresoc.v:185345$12374 + attribute \src "libresoc.v:187649.3-187650.41" + process $proc$libresoc.v:187649$12558 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:185347.3-185348.37" - process $proc$libresoc.v:185347$12375 + attribute \src "libresoc.v:187651.3-187652.37" + process $proc$libresoc.v:187651$12559 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:185349.3-185350.46" - process $proc$libresoc.v:185349$12376 + attribute \src "libresoc.v:187653.3-187654.46" + process $proc$libresoc.v:187653$12560 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:185351.3-185352.25" - process $proc$libresoc.v:185351$12377 + attribute \src "libresoc.v:187655.3-187656.25" + process $proc$libresoc.v:187655$12561 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:185437.3-185446.6" - process $proc$libresoc.v:185437$12378 + attribute \src "libresoc.v:187741.3-187750.6" + process $proc$libresoc.v:187741$12562 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:185438.5-185438.29" + attribute \src "libresoc.v:187742.5-187742.29" switch \initial - attribute \src "libresoc.v:185438.9-185438.17" + attribute \src "libresoc.v:187742.9-187742.17" case 1'1 case end @@ -386289,14 +390298,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:185447.3-185455.6" - process $proc$libresoc.v:185447$12379 + attribute \src "libresoc.v:187751.3-187759.6" + process $proc$libresoc.v:187751$12563 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12380 $1\rok_l_s_rdok$next[0:0]$12381 - attribute \src "libresoc.v:185448.5-185448.29" + assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187752.5-187752.29" switch \initial - attribute \src "libresoc.v:185448.9-185448.17" + attribute \src "libresoc.v:187752.9-187752.17" case 1'1 case end @@ -386305,21 +390314,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12381 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12565 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12381 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12565 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12380 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 end - attribute \src "libresoc.v:185456.3-185464.6" - process $proc$libresoc.v:185456$12382 + attribute \src "libresoc.v:187760.3-187768.6" + process $proc$libresoc.v:187760$12566 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12383 $1\rok_l_r_rdok$next[0:0]$12384 - attribute \src "libresoc.v:185457.5-185457.29" + assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187761.5-187761.29" switch \initial - attribute \src "libresoc.v:185457.9-185457.17" + attribute \src "libresoc.v:187761.9-187761.17" case 1'1 case end @@ -386328,21 +390337,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12384 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12568 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12384 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12568 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12383 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 end - attribute \src "libresoc.v:185465.3-185473.6" - process $proc$libresoc.v:185465$12385 + attribute \src "libresoc.v:187769.3-187777.6" + process $proc$libresoc.v:187769$12569 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12386 $1\rst_l_s_rst$next[0:0]$12387 - attribute \src "libresoc.v:185466.5-185466.29" + assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187770.5-187770.29" switch \initial - attribute \src "libresoc.v:185466.9-185466.17" + attribute \src "libresoc.v:187770.9-187770.17" case 1'1 case end @@ -386351,21 +390360,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12387 1'0 + assign $1\rst_l_s_rst$next[0:0]$12571 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12387 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12571 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12386 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 end - attribute \src "libresoc.v:185474.3-185482.6" - process $proc$libresoc.v:185474$12388 + attribute \src "libresoc.v:187778.3-187786.6" + process $proc$libresoc.v:187778$12572 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12389 $1\rst_l_r_rst$next[0:0]$12390 - attribute \src "libresoc.v:185475.5-185475.29" + assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187779.5-187779.29" switch \initial - attribute \src "libresoc.v:185475.9-185475.17" + attribute \src "libresoc.v:187779.9-187779.17" case 1'1 case end @@ -386374,21 +390383,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12390 1'1 + assign $1\rst_l_r_rst$next[0:0]$12574 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12390 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12574 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12389 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 end - attribute \src "libresoc.v:185483.3-185491.6" - process $proc$libresoc.v:185483$12391 + attribute \src "libresoc.v:187787.3-187795.6" + process $proc$libresoc.v:187787$12575 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12392 $1\opc_l_s_opc$next[0:0]$12393 - attribute \src "libresoc.v:185484.5-185484.29" + assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187788.5-187788.29" switch \initial - attribute \src "libresoc.v:185484.9-185484.17" + attribute \src "libresoc.v:187788.9-187788.17" case 1'1 case end @@ -386397,21 +390406,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12393 1'0 + assign $1\opc_l_s_opc$next[0:0]$12577 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12393 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12577 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12392 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 end - attribute \src "libresoc.v:185492.3-185500.6" - process $proc$libresoc.v:185492$12394 + attribute \src "libresoc.v:187796.3-187804.6" + process $proc$libresoc.v:187796$12578 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12395 $1\opc_l_r_opc$next[0:0]$12396 - attribute \src "libresoc.v:185493.5-185493.29" + assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187797.5-187797.29" switch \initial - attribute \src "libresoc.v:185493.9-185493.17" + attribute \src "libresoc.v:187797.9-187797.17" case 1'1 case end @@ -386420,21 +390429,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12396 1'1 + assign $1\opc_l_r_opc$next[0:0]$12580 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12396 \req_done + assign $1\opc_l_r_opc$next[0:0]$12580 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12395 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 end - attribute \src "libresoc.v:185501.3-185509.6" - process $proc$libresoc.v:185501$12397 + attribute \src "libresoc.v:187805.3-187813.6" + process $proc$libresoc.v:187805$12581 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12398 $1\src_l_s_src$next[4:0]$12399 - attribute \src "libresoc.v:185502.5-185502.29" + assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187806.5-187806.29" switch \initial - attribute \src "libresoc.v:185502.9-185502.17" + attribute \src "libresoc.v:187806.9-187806.17" case 1'1 case end @@ -386443,21 +390452,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12399 5'00000 + assign $1\src_l_s_src$next[4:0]$12583 5'00000 case - assign $1\src_l_s_src$next[4:0]$12399 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12583 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12398 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 end - attribute \src "libresoc.v:185510.3-185518.6" - process $proc$libresoc.v:185510$12400 + attribute \src "libresoc.v:187814.3-187822.6" + process $proc$libresoc.v:187814$12584 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12401 $1\src_l_r_src$next[4:0]$12402 - attribute \src "libresoc.v:185511.5-185511.29" + assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187815.5-187815.29" switch \initial - attribute \src "libresoc.v:185511.9-185511.17" + attribute \src "libresoc.v:187815.9-187815.17" case 1'1 case end @@ -386466,21 +390475,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12402 5'11111 + assign $1\src_l_r_src$next[4:0]$12586 5'11111 case - assign $1\src_l_r_src$next[4:0]$12402 \reset_r + assign $1\src_l_r_src$next[4:0]$12586 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12401 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 end - attribute \src "libresoc.v:185519.3-185527.6" - process $proc$libresoc.v:185519$12403 + attribute \src "libresoc.v:187823.3-187831.6" + process $proc$libresoc.v:187823$12587 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12404 $1\req_l_s_req$next[2:0]$12405 - attribute \src "libresoc.v:185520.5-185520.29" + assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187824.5-187824.29" switch \initial - attribute \src "libresoc.v:185520.9-185520.17" + attribute \src "libresoc.v:187824.9-187824.17" case 1'1 case end @@ -386489,21 +390498,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12405 3'000 + assign $1\req_l_s_req$next[2:0]$12589 3'000 case - assign $1\req_l_s_req$next[2:0]$12405 \$66 + assign $1\req_l_s_req$next[2:0]$12589 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12404 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 end - attribute \src "libresoc.v:185528.3-185536.6" - process $proc$libresoc.v:185528$12406 + attribute \src "libresoc.v:187832.3-187840.6" + process $proc$libresoc.v:187832$12590 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12407 $1\req_l_r_req$next[2:0]$12408 - attribute \src "libresoc.v:185529.5-185529.29" + assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187833.5-187833.29" switch \initial - attribute \src "libresoc.v:185529.9-185529.17" + attribute \src "libresoc.v:187833.9-187833.17" case 1'1 case end @@ -386512,15 +390521,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12408 3'111 + assign $1\req_l_r_req$next[2:0]$12592 3'111 case - assign $1\req_l_r_req$next[2:0]$12408 \$68 + assign $1\req_l_r_req$next[2:0]$12592 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12407 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 end - attribute \src "libresoc.v:185537.3-185574.6" - process $proc$libresoc.v:185537$12409 + attribute \src "libresoc.v:187841.3-187878.6" + process $proc$libresoc.v:187841$12593 assign { } { } assign { } { } assign { } { } @@ -386555,32 +390564,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 - attribute \src "libresoc.v:185538.5-185538.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 + attribute \src "libresoc.v:187842.5-187842.29" switch \initial - attribute \src "libresoc.v:185538.9-185538.17" + attribute \src "libresoc.v:187842.9-187842.17" case 1'1 case end @@ -386605,25 +390614,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -386635,53 +390644,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 end - attribute \src "libresoc.v:185575.3-185596.6" - process $proc$libresoc.v:185575$12450 + attribute \src "libresoc.v:187879.3-187900.6" + process $proc$libresoc.v:187879$12634 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12451 $2\data_r0__o$next[63:0]$12455 + assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12452 $3\data_r0__o_ok$next[0:0]$12457 - attribute \src "libresoc.v:185576.5-185576.29" + assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 + attribute \src "libresoc.v:187880.5-187880.29" switch \initial - attribute \src "libresoc.v:185576.9-185576.17" + attribute \src "libresoc.v:187880.9-187880.17" case 1'1 case end @@ -386691,10 +390700,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12454 $1\data_r0__o$next[63:0]$12453 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12638 $1\data_r0__o$next[63:0]$12637 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12453 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12454 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12637 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12638 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386702,38 +390711,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12456 $2\data_r0__o$next[63:0]$12455 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12640 $2\data_r0__o$next[63:0]$12639 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12455 $1\data_r0__o$next[63:0]$12453 - assign $2\data_r0__o_ok$next[0:0]$12456 $1\data_r0__o_ok$next[0:0]$12454 + assign $2\data_r0__o$next[63:0]$12639 $1\data_r0__o$next[63:0]$12637 + assign $2\data_r0__o_ok$next[0:0]$12640 $1\data_r0__o_ok$next[0:0]$12638 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12457 1'0 + assign $3\data_r0__o_ok$next[0:0]$12641 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12457 $2\data_r0__o_ok$next[0:0]$12456 + assign $3\data_r0__o_ok$next[0:0]$12641 $2\data_r0__o_ok$next[0:0]$12640 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12451 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12452 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 end - attribute \src "libresoc.v:185597.3-185618.6" - process $proc$libresoc.v:185597$12458 + attribute \src "libresoc.v:187901.3-187922.6" + process $proc$libresoc.v:187901$12642 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12459 $2\data_r1__cr_a$next[3:0]$12463 + assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12460 $3\data_r1__cr_a_ok$next[0:0]$12465 - attribute \src "libresoc.v:185598.5-185598.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 + attribute \src "libresoc.v:187902.5-187902.29" switch \initial - attribute \src "libresoc.v:185598.9-185598.17" + attribute \src "libresoc.v:187902.9-187902.17" case 1'1 case end @@ -386743,10 +390752,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12462 $1\data_r1__cr_a$next[3:0]$12461 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12646 $1\data_r1__cr_a$next[3:0]$12645 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12461 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12462 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12645 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12646 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386754,38 +390763,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12464 $2\data_r1__cr_a$next[3:0]$12463 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12648 $2\data_r1__cr_a$next[3:0]$12647 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12463 $1\data_r1__cr_a$next[3:0]$12461 - assign $2\data_r1__cr_a_ok$next[0:0]$12464 $1\data_r1__cr_a_ok$next[0:0]$12462 + assign $2\data_r1__cr_a$next[3:0]$12647 $1\data_r1__cr_a$next[3:0]$12645 + assign $2\data_r1__cr_a_ok$next[0:0]$12648 $1\data_r1__cr_a_ok$next[0:0]$12646 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12465 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12649 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12465 $2\data_r1__cr_a_ok$next[0:0]$12464 + assign $3\data_r1__cr_a_ok$next[0:0]$12649 $2\data_r1__cr_a_ok$next[0:0]$12648 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12459 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12460 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 end - attribute \src "libresoc.v:185619.3-185640.6" - process $proc$libresoc.v:185619$12466 + attribute \src "libresoc.v:187923.3-187944.6" + process $proc$libresoc.v:187923$12650 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12467 $2\data_r2__xer_ca$next[1:0]$12471 + assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12468 $3\data_r2__xer_ca_ok$next[0:0]$12473 - attribute \src "libresoc.v:185620.5-185620.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 + attribute \src "libresoc.v:187924.5-187924.29" switch \initial - attribute \src "libresoc.v:185620.9-185620.17" + attribute \src "libresoc.v:187924.9-187924.17" case 1'1 case end @@ -386795,10 +390804,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12470 $1\data_r2__xer_ca$next[1:0]$12469 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12654 $1\data_r2__xer_ca$next[1:0]$12653 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12469 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12470 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12653 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12654 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386806,32 +390815,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12472 $2\data_r2__xer_ca$next[1:0]$12471 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12656 $2\data_r2__xer_ca$next[1:0]$12655 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12471 $1\data_r2__xer_ca$next[1:0]$12469 - assign $2\data_r2__xer_ca_ok$next[0:0]$12472 $1\data_r2__xer_ca_ok$next[0:0]$12470 + assign $2\data_r2__xer_ca$next[1:0]$12655 $1\data_r2__xer_ca$next[1:0]$12653 + assign $2\data_r2__xer_ca_ok$next[0:0]$12656 $1\data_r2__xer_ca_ok$next[0:0]$12654 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12473 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12473 $2\data_r2__xer_ca_ok$next[0:0]$12472 + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 $2\data_r2__xer_ca_ok$next[0:0]$12656 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12467 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12468 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 end - attribute \src "libresoc.v:185641.3-185650.6" - process $proc$libresoc.v:185641$12474 + attribute \src "libresoc.v:187945.3-187954.6" + process $proc$libresoc.v:187945$12658 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12475 $1\src_r0$next[63:0]$12476 - attribute \src "libresoc.v:185642.5-185642.29" + assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187946.5-187946.29" switch \initial - attribute \src "libresoc.v:185642.9-185642.17" + attribute \src "libresoc.v:187946.9-187946.17" case 1'1 case end @@ -386840,21 +390849,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12476 \src1_i + assign $1\src_r0$next[63:0]$12660 \src1_i case - assign $1\src_r0$next[63:0]$12476 \src_r0 + assign $1\src_r0$next[63:0]$12660 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12475 + update \src_r0$next $0\src_r0$next[63:0]$12659 end - attribute \src "libresoc.v:185651.3-185660.6" - process $proc$libresoc.v:185651$12477 + attribute \src "libresoc.v:187955.3-187964.6" + process $proc$libresoc.v:187955$12661 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12478 $1\src_r1$next[63:0]$12479 - attribute \src "libresoc.v:185652.5-185652.29" + assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187956.5-187956.29" switch \initial - attribute \src "libresoc.v:185652.9-185652.17" + attribute \src "libresoc.v:187956.9-187956.17" case 1'1 case end @@ -386863,21 +390872,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12479 \src_or_imm + assign $1\src_r1$next[63:0]$12663 \src_or_imm case - assign $1\src_r1$next[63:0]$12479 \src_r1 + assign $1\src_r1$next[63:0]$12663 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12478 + update \src_r1$next $0\src_r1$next[63:0]$12662 end - attribute \src "libresoc.v:185661.3-185670.6" - process $proc$libresoc.v:185661$12480 + attribute \src "libresoc.v:187965.3-187974.6" + process $proc$libresoc.v:187965$12664 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12481 $1\src_r2$next[63:0]$12482 - attribute \src "libresoc.v:185662.5-185662.29" + assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187966.5-187966.29" switch \initial - attribute \src "libresoc.v:185662.9-185662.17" + attribute \src "libresoc.v:187966.9-187966.17" case 1'1 case end @@ -386886,21 +390895,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12482 \src3_i + assign $1\src_r2$next[63:0]$12666 \src3_i case - assign $1\src_r2$next[63:0]$12482 \src_r2 + assign $1\src_r2$next[63:0]$12666 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12481 + update \src_r2$next $0\src_r2$next[63:0]$12665 end - attribute \src "libresoc.v:185671.3-185680.6" - process $proc$libresoc.v:185671$12483 + attribute \src "libresoc.v:187975.3-187984.6" + process $proc$libresoc.v:187975$12667 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12484 $1\src_r3$next[0:0]$12485 - attribute \src "libresoc.v:185672.5-185672.29" + assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 + attribute \src "libresoc.v:187976.5-187976.29" switch \initial - attribute \src "libresoc.v:185672.9-185672.17" + attribute \src "libresoc.v:187976.9-187976.17" case 1'1 case end @@ -386909,21 +390918,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12485 \src4_i + assign $1\src_r3$next[0:0]$12669 \src4_i case - assign $1\src_r3$next[0:0]$12485 \src_r3 + assign $1\src_r3$next[0:0]$12669 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12484 + update \src_r3$next $0\src_r3$next[0:0]$12668 end - attribute \src "libresoc.v:185681.3-185690.6" - process $proc$libresoc.v:185681$12486 + attribute \src "libresoc.v:187985.3-187994.6" + process $proc$libresoc.v:187985$12670 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12487 $1\src_r4$next[1:0]$12488 - attribute \src "libresoc.v:185682.5-185682.29" + assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 + attribute \src "libresoc.v:187986.5-187986.29" switch \initial - attribute \src "libresoc.v:185682.9-185682.17" + attribute \src "libresoc.v:187986.9-187986.17" case 1'1 case end @@ -386932,21 +390941,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12488 \src5_i + assign $1\src_r4$next[1:0]$12672 \src5_i case - assign $1\src_r4$next[1:0]$12488 \src_r4 + assign $1\src_r4$next[1:0]$12672 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12487 + update \src_r4$next $0\src_r4$next[1:0]$12671 end - attribute \src "libresoc.v:185691.3-185699.6" - process $proc$libresoc.v:185691$12489 + attribute \src "libresoc.v:187995.3-188003.6" + process $proc$libresoc.v:187995$12673 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12490 $1\alui_l_r_alui$next[0:0]$12491 - attribute \src "libresoc.v:185692.5-185692.29" + assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187996.5-187996.29" switch \initial - attribute \src "libresoc.v:185692.9-185692.17" + attribute \src "libresoc.v:187996.9-187996.17" case 1'1 case end @@ -386955,21 +390964,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12491 1'1 + assign $1\alui_l_r_alui$next[0:0]$12675 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12491 \$90 + assign $1\alui_l_r_alui$next[0:0]$12675 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12490 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 end - attribute \src "libresoc.v:185700.3-185708.6" - process $proc$libresoc.v:185700$12492 + attribute \src "libresoc.v:188004.3-188012.6" + process $proc$libresoc.v:188004$12676 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12493 $1\alu_l_r_alu$next[0:0]$12494 - attribute \src "libresoc.v:185701.5-185701.29" + assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:188005.5-188005.29" switch \initial - attribute \src "libresoc.v:185701.9-185701.17" + attribute \src "libresoc.v:188005.9-188005.17" case 1'1 case end @@ -386978,21 +390987,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12494 1'1 + assign $1\alu_l_r_alu$next[0:0]$12678 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12494 \$92 + assign $1\alu_l_r_alu$next[0:0]$12678 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12493 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 end - attribute \src "libresoc.v:185709.3-185718.6" - process $proc$libresoc.v:185709$12495 + attribute \src "libresoc.v:188013.3-188022.6" + process $proc$libresoc.v:188013$12679 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:185710.5-185710.29" + attribute \src "libresoc.v:188014.5-188014.29" switch \initial - attribute \src "libresoc.v:185710.9-185710.17" + attribute \src "libresoc.v:188014.9-188014.17" case 1'1 case end @@ -387008,14 +391017,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:185719.3-185728.6" - process $proc$libresoc.v:185719$12496 + attribute \src "libresoc.v:188023.3-188032.6" + process $proc$libresoc.v:188023$12680 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:185720.5-185720.29" + attribute \src "libresoc.v:188024.5-188024.29" switch \initial - attribute \src "libresoc.v:185720.9-185720.17" + attribute \src "libresoc.v:188024.9-188024.17" case 1'1 case end @@ -387031,14 +391040,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:185729.3-185738.6" - process $proc$libresoc.v:185729$12497 + attribute \src "libresoc.v:188033.3-188042.6" + process $proc$libresoc.v:188033$12681 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:185730.5-185730.29" + attribute \src "libresoc.v:188034.5-188034.29" switch \initial - attribute \src "libresoc.v:185730.9-185730.17" + attribute \src "libresoc.v:188034.9-188034.17" case 1'1 case end @@ -387054,14 +391063,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:185739.3-185747.6" - process $proc$libresoc.v:185739$12498 + attribute \src "libresoc.v:188043.3-188051.6" + process $proc$libresoc.v:188043$12682 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12499 $1\prev_wr_go$next[2:0]$12500 - attribute \src "libresoc.v:185740.5-185740.29" + assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:188044.5-188044.29" switch \initial - attribute \src "libresoc.v:185740.9-185740.17" + attribute \src "libresoc.v:188044.9-188044.17" case 1'1 case end @@ -387070,72 +391079,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12500 3'000 - case - assign $1\prev_wr_go$next[2:0]$12500 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12499 - end - connect \$100 $not$libresoc.v:185208$12276_Y - connect \$102 $and$libresoc.v:185209$12277_Y - connect \$104 $and$libresoc.v:185210$12278_Y - connect \$106 $and$libresoc.v:185211$12279_Y - connect \$108 $and$libresoc.v:185212$12280_Y - connect \$10 $and$libresoc.v:185213$12281_Y - connect \$110 $and$libresoc.v:185214$12282_Y - connect \$112 $and$libresoc.v:185215$12283_Y - connect \$114 $and$libresoc.v:185216$12284_Y - connect \$116 $and$libresoc.v:185217$12285_Y - connect \$118 $and$libresoc.v:185218$12286_Y - connect \$12 $not$libresoc.v:185219$12287_Y - connect \$14 $and$libresoc.v:185220$12288_Y - connect \$16 $not$libresoc.v:185221$12289_Y - connect \$18 $and$libresoc.v:185222$12290_Y - connect \$20 $and$libresoc.v:185223$12291_Y - connect \$24 $not$libresoc.v:185224$12292_Y - connect \$26 $and$libresoc.v:185225$12293_Y - connect \$23 $reduce_or$libresoc.v:185226$12294_Y - connect \$22 $not$libresoc.v:185227$12295_Y - connect \$2 $and$libresoc.v:185228$12296_Y - connect \$30 $and$libresoc.v:185229$12297_Y - connect \$32 $reduce_or$libresoc.v:185230$12298_Y - connect \$34 $reduce_or$libresoc.v:185231$12299_Y - connect \$36 $or$libresoc.v:185232$12300_Y - connect \$38 $not$libresoc.v:185233$12301_Y - connect \$40 $and$libresoc.v:185234$12302_Y - connect \$42 $and$libresoc.v:185235$12303_Y - connect \$44 $eq$libresoc.v:185236$12304_Y - connect \$46 $and$libresoc.v:185237$12305_Y - connect \$48 $eq$libresoc.v:185238$12306_Y - connect \$50 $and$libresoc.v:185239$12307_Y - connect \$52 $and$libresoc.v:185240$12308_Y - connect \$54 $and$libresoc.v:185241$12309_Y - connect \$56 $or$libresoc.v:185242$12310_Y - connect \$58 $or$libresoc.v:185243$12311_Y - connect \$5 $not$libresoc.v:185244$12312_Y - connect \$60 $or$libresoc.v:185245$12313_Y - connect \$62 $or$libresoc.v:185246$12314_Y - connect \$64 $and$libresoc.v:185247$12315_Y - connect \$66 $and$libresoc.v:185248$12316_Y - connect \$68 $or$libresoc.v:185249$12317_Y - connect \$70 $and$libresoc.v:185250$12318_Y - connect \$72 $and$libresoc.v:185251$12319_Y - connect \$74 $and$libresoc.v:185252$12320_Y - connect \$76 $ternary$libresoc.v:185253$12321_Y - connect \$78 $ternary$libresoc.v:185254$12322_Y - connect \$7 $or$libresoc.v:185255$12323_Y - connect \$80 $ternary$libresoc.v:185256$12324_Y - connect \$82 $ternary$libresoc.v:185257$12325_Y - connect \$84 $ternary$libresoc.v:185258$12326_Y - connect \$86 $ternary$libresoc.v:185259$12327_Y - connect \$88 $ternary$libresoc.v:185260$12328_Y - connect \$4 $reduce_and$libresoc.v:185261$12329_Y - connect \$90 $and$libresoc.v:185262$12330_Y - connect \$92 $and$libresoc.v:185263$12331_Y - connect \$94 $and$libresoc.v:185264$12332_Y - connect \$96 $not$libresoc.v:185265$12333_Y - connect \$98 $and$libresoc.v:185266$12334_Y + assign $1\prev_wr_go$next[2:0]$12684 3'000 + case + assign $1\prev_wr_go$next[2:0]$12684 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 + end + connect \$100 $not$libresoc.v:187512$12460_Y + connect \$102 $and$libresoc.v:187513$12461_Y + connect \$104 $and$libresoc.v:187514$12462_Y + connect \$106 $and$libresoc.v:187515$12463_Y + connect \$108 $and$libresoc.v:187516$12464_Y + connect \$10 $and$libresoc.v:187517$12465_Y + connect \$110 $and$libresoc.v:187518$12466_Y + connect \$112 $and$libresoc.v:187519$12467_Y + connect \$114 $and$libresoc.v:187520$12468_Y + connect \$116 $and$libresoc.v:187521$12469_Y + connect \$118 $and$libresoc.v:187522$12470_Y + connect \$12 $not$libresoc.v:187523$12471_Y + connect \$14 $and$libresoc.v:187524$12472_Y + connect \$16 $not$libresoc.v:187525$12473_Y + connect \$18 $and$libresoc.v:187526$12474_Y + connect \$20 $and$libresoc.v:187527$12475_Y + connect \$24 $not$libresoc.v:187528$12476_Y + connect \$26 $and$libresoc.v:187529$12477_Y + connect \$23 $reduce_or$libresoc.v:187530$12478_Y + connect \$22 $not$libresoc.v:187531$12479_Y + connect \$2 $and$libresoc.v:187532$12480_Y + connect \$30 $and$libresoc.v:187533$12481_Y + connect \$32 $reduce_or$libresoc.v:187534$12482_Y + connect \$34 $reduce_or$libresoc.v:187535$12483_Y + connect \$36 $or$libresoc.v:187536$12484_Y + connect \$38 $not$libresoc.v:187537$12485_Y + connect \$40 $and$libresoc.v:187538$12486_Y + connect \$42 $and$libresoc.v:187539$12487_Y + connect \$44 $eq$libresoc.v:187540$12488_Y + connect \$46 $and$libresoc.v:187541$12489_Y + connect \$48 $eq$libresoc.v:187542$12490_Y + connect \$50 $and$libresoc.v:187543$12491_Y + connect \$52 $and$libresoc.v:187544$12492_Y + connect \$54 $and$libresoc.v:187545$12493_Y + connect \$56 $or$libresoc.v:187546$12494_Y + connect \$58 $or$libresoc.v:187547$12495_Y + connect \$5 $not$libresoc.v:187548$12496_Y + connect \$60 $or$libresoc.v:187549$12497_Y + connect \$62 $or$libresoc.v:187550$12498_Y + connect \$64 $and$libresoc.v:187551$12499_Y + connect \$66 $and$libresoc.v:187552$12500_Y + connect \$68 $or$libresoc.v:187553$12501_Y + connect \$70 $and$libresoc.v:187554$12502_Y + connect \$72 $and$libresoc.v:187555$12503_Y + connect \$74 $and$libresoc.v:187556$12504_Y + connect \$76 $ternary$libresoc.v:187557$12505_Y + connect \$78 $ternary$libresoc.v:187558$12506_Y + connect \$7 $or$libresoc.v:187559$12507_Y + connect \$80 $ternary$libresoc.v:187560$12508_Y + connect \$82 $ternary$libresoc.v:187561$12509_Y + connect \$84 $ternary$libresoc.v:187562$12510_Y + connect \$86 $ternary$libresoc.v:187563$12511_Y + connect \$88 $ternary$libresoc.v:187564$12512_Y + connect \$4 $reduce_and$libresoc.v:187565$12513_Y + connect \$90 $and$libresoc.v:187566$12514_Y + connect \$92 $and$libresoc.v:187567$12515_Y + connect \$94 $and$libresoc.v:187568$12516_Y + connect \$96 $not$libresoc.v:187569$12517_Y + connect \$98 $and$libresoc.v:187570$12518_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -387169,48 +391178,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:185784.1-185964.10" +attribute \src "libresoc.v:188088.1-188268.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:185936.3-185939.6" - wire width 7 $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 - attribute \src "libresoc.v:185936.3-185939.6" - wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 - attribute \src "libresoc.v:185936.3-185939.6" - wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 - attribute \src "libresoc.v:185936.3-185939.6" + attribute \src "libresoc.v:188240.3-188243.6" + wire width 7 $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + attribute \src "libresoc.v:188240.3-188243.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:185785.7-185785.20" + attribute \src "libresoc.v:188089.7-188089.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185941.3-185949.6" - wire $0\ren_delay$next[0:0]$12666 - attribute \src "libresoc.v:185817.3-185818.35" + attribute \src "libresoc.v:188245.3-188253.6" + wire $0\ren_delay$next[0:0]$12850 + attribute \src "libresoc.v:188121.3-188122.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:185950.3-185959.6" + attribute \src "libresoc.v:188254.3-188263.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:185941.3-185949.6" - wire $1\ren_delay$next[0:0]$12667 - attribute \src "libresoc.v:185801.7-185801.23" + attribute \src "libresoc.v:188245.3-188253.6" + wire $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188105.7-188105.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:185950.3-185959.6" + attribute \src "libresoc.v:188254.3-188263.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:185940.26-185940.32" - wire width 64 $memrd$\memory$libresoc.v:185940$12664_DATA + attribute \src "libresoc.v:188244.26-188244.32" + wire width 64 $memrd$\memory$libresoc.v:188244$12848_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:185938$12658_ADDR + wire width 7 $memwr$\memory$libresoc.v:188242$12842_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:185938$12658_DATA + wire width 64 $memwr$\memory$libresoc.v:188242$12842_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:185938$12658_EN - attribute \src "libresoc.v:185935.13-185935.16" + wire width 64 $memwr$\memory$libresoc.v:188242$12842_EN + attribute \src "libresoc.v:188239.13-188239.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185785.7-185785.15" + attribute \src "libresoc.v:188089.7-188089.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -387238,1140 +391247,1140 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:185819.14-185819.20" + attribute \src "libresoc.v:188123.14-188123.20" memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12669 + cell $meminit $meminit$\memory$libresoc.v:0$12853 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12669 + parameter \PRIORITY 12853 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12670 + cell $meminit $meminit$\memory$libresoc.v:0$12854 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12670 + parameter \PRIORITY 12854 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12671 + cell $meminit $meminit$\memory$libresoc.v:0$12855 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12671 + parameter \PRIORITY 12855 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12672 + cell $meminit $meminit$\memory$libresoc.v:0$12856 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12672 + parameter \PRIORITY 12856 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12673 + cell $meminit $meminit$\memory$libresoc.v:0$12857 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12673 + parameter \PRIORITY 12857 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12674 + cell $meminit $meminit$\memory$libresoc.v:0$12858 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12674 + parameter \PRIORITY 12858 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12675 + cell $meminit $meminit$\memory$libresoc.v:0$12859 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12675 + parameter \PRIORITY 12859 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12676 + cell $meminit $meminit$\memory$libresoc.v:0$12860 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12676 + parameter \PRIORITY 12860 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12677 + cell $meminit $meminit$\memory$libresoc.v:0$12861 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12677 + parameter \PRIORITY 12861 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12678 + cell $meminit $meminit$\memory$libresoc.v:0$12862 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12678 + parameter \PRIORITY 12862 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12679 + cell $meminit $meminit$\memory$libresoc.v:0$12863 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12679 + parameter \PRIORITY 12863 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12680 + cell $meminit $meminit$\memory$libresoc.v:0$12864 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12680 + parameter \PRIORITY 12864 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12681 + cell $meminit $meminit$\memory$libresoc.v:0$12865 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12681 + parameter \PRIORITY 12865 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12682 + cell $meminit $meminit$\memory$libresoc.v:0$12866 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12682 + parameter \PRIORITY 12866 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12683 + cell $meminit $meminit$\memory$libresoc.v:0$12867 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12683 + parameter \PRIORITY 12867 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12684 + cell $meminit $meminit$\memory$libresoc.v:0$12868 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12684 + parameter \PRIORITY 12868 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12685 + cell $meminit $meminit$\memory$libresoc.v:0$12869 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12685 + parameter \PRIORITY 12869 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12686 + cell $meminit $meminit$\memory$libresoc.v:0$12870 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12686 + parameter \PRIORITY 12870 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12687 + cell $meminit $meminit$\memory$libresoc.v:0$12871 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12687 + parameter \PRIORITY 12871 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12688 + cell $meminit $meminit$\memory$libresoc.v:0$12872 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12688 + parameter \PRIORITY 12872 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12689 + cell $meminit $meminit$\memory$libresoc.v:0$12873 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12689 + parameter \PRIORITY 12873 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12690 + cell $meminit $meminit$\memory$libresoc.v:0$12874 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12690 + parameter \PRIORITY 12874 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12691 + cell $meminit $meminit$\memory$libresoc.v:0$12875 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12691 + parameter \PRIORITY 12875 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12692 + cell $meminit $meminit$\memory$libresoc.v:0$12876 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12692 + parameter \PRIORITY 12876 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12693 + cell $meminit $meminit$\memory$libresoc.v:0$12877 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12693 + parameter \PRIORITY 12877 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12694 + cell $meminit $meminit$\memory$libresoc.v:0$12878 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12694 + parameter \PRIORITY 12878 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12695 + cell $meminit $meminit$\memory$libresoc.v:0$12879 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12695 + parameter \PRIORITY 12879 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12696 + cell $meminit $meminit$\memory$libresoc.v:0$12880 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12696 + parameter \PRIORITY 12880 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12697 + cell $meminit $meminit$\memory$libresoc.v:0$12881 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12697 + parameter \PRIORITY 12881 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12698 + cell $meminit $meminit$\memory$libresoc.v:0$12882 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12698 + parameter \PRIORITY 12882 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12699 + cell $meminit $meminit$\memory$libresoc.v:0$12883 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12699 + parameter \PRIORITY 12883 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12700 + cell $meminit $meminit$\memory$libresoc.v:0$12884 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12700 + parameter \PRIORITY 12884 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12701 + cell $meminit $meminit$\memory$libresoc.v:0$12885 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12701 + parameter \PRIORITY 12885 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12702 + cell $meminit $meminit$\memory$libresoc.v:0$12886 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12702 + parameter \PRIORITY 12886 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12703 + cell $meminit $meminit$\memory$libresoc.v:0$12887 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12703 + parameter \PRIORITY 12887 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12704 + cell $meminit $meminit$\memory$libresoc.v:0$12888 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12704 + parameter \PRIORITY 12888 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12705 + cell $meminit $meminit$\memory$libresoc.v:0$12889 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12705 + parameter \PRIORITY 12889 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12706 + cell $meminit $meminit$\memory$libresoc.v:0$12890 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12706 + parameter \PRIORITY 12890 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12707 + cell $meminit $meminit$\memory$libresoc.v:0$12891 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12707 + parameter \PRIORITY 12891 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12708 + cell $meminit $meminit$\memory$libresoc.v:0$12892 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12708 + parameter \PRIORITY 12892 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12709 + cell $meminit $meminit$\memory$libresoc.v:0$12893 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12709 + parameter \PRIORITY 12893 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12710 + cell $meminit $meminit$\memory$libresoc.v:0$12894 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12710 + parameter \PRIORITY 12894 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12711 + cell $meminit $meminit$\memory$libresoc.v:0$12895 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12711 + parameter \PRIORITY 12895 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12712 + cell $meminit $meminit$\memory$libresoc.v:0$12896 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12712 + parameter \PRIORITY 12896 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12713 + cell $meminit $meminit$\memory$libresoc.v:0$12897 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12713 + parameter \PRIORITY 12897 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12714 + cell $meminit $meminit$\memory$libresoc.v:0$12898 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12714 + parameter \PRIORITY 12898 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12715 + cell $meminit $meminit$\memory$libresoc.v:0$12899 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12715 + parameter \PRIORITY 12899 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12716 + cell $meminit $meminit$\memory$libresoc.v:0$12900 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12716 + parameter \PRIORITY 12900 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12717 + cell $meminit $meminit$\memory$libresoc.v:0$12901 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12717 + parameter \PRIORITY 12901 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12718 + cell $meminit $meminit$\memory$libresoc.v:0$12902 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12718 + parameter \PRIORITY 12902 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12719 + cell $meminit $meminit$\memory$libresoc.v:0$12903 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12719 + parameter \PRIORITY 12903 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12720 + cell $meminit $meminit$\memory$libresoc.v:0$12904 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12720 + parameter \PRIORITY 12904 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12721 + cell $meminit $meminit$\memory$libresoc.v:0$12905 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12721 + parameter \PRIORITY 12905 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12722 + cell $meminit $meminit$\memory$libresoc.v:0$12906 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12722 + parameter \PRIORITY 12906 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12723 + cell $meminit $meminit$\memory$libresoc.v:0$12907 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12723 + parameter \PRIORITY 12907 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12724 + cell $meminit $meminit$\memory$libresoc.v:0$12908 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12724 + parameter \PRIORITY 12908 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12725 + cell $meminit $meminit$\memory$libresoc.v:0$12909 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12725 + parameter \PRIORITY 12909 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12726 + cell $meminit $meminit$\memory$libresoc.v:0$12910 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12726 + parameter \PRIORITY 12910 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12727 + cell $meminit $meminit$\memory$libresoc.v:0$12911 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12727 + parameter \PRIORITY 12911 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12728 + cell $meminit $meminit$\memory$libresoc.v:0$12912 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12728 + parameter \PRIORITY 12912 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12729 + cell $meminit $meminit$\memory$libresoc.v:0$12913 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12729 + parameter \PRIORITY 12913 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12730 + cell $meminit $meminit$\memory$libresoc.v:0$12914 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12730 + parameter \PRIORITY 12914 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12731 + cell $meminit $meminit$\memory$libresoc.v:0$12915 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12731 + parameter \PRIORITY 12915 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12732 + cell $meminit $meminit$\memory$libresoc.v:0$12916 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12732 + parameter \PRIORITY 12916 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12733 + cell $meminit $meminit$\memory$libresoc.v:0$12917 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12733 + parameter \PRIORITY 12917 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12734 + cell $meminit $meminit$\memory$libresoc.v:0$12918 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12734 + parameter \PRIORITY 12918 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12735 + cell $meminit $meminit$\memory$libresoc.v:0$12919 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12735 + parameter \PRIORITY 12919 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12736 + cell $meminit $meminit$\memory$libresoc.v:0$12920 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12736 + parameter \PRIORITY 12920 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12737 + cell $meminit $meminit$\memory$libresoc.v:0$12921 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12737 + parameter \PRIORITY 12921 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12738 + cell $meminit $meminit$\memory$libresoc.v:0$12922 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12738 + parameter \PRIORITY 12922 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12739 + cell $meminit $meminit$\memory$libresoc.v:0$12923 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12739 + parameter \PRIORITY 12923 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12740 + cell $meminit $meminit$\memory$libresoc.v:0$12924 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12740 + parameter \PRIORITY 12924 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12741 + cell $meminit $meminit$\memory$libresoc.v:0$12925 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12741 + parameter \PRIORITY 12925 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12742 + cell $meminit $meminit$\memory$libresoc.v:0$12926 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12742 + parameter \PRIORITY 12926 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12743 + cell $meminit $meminit$\memory$libresoc.v:0$12927 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12743 + parameter \PRIORITY 12927 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12744 + cell $meminit $meminit$\memory$libresoc.v:0$12928 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12744 + parameter \PRIORITY 12928 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12745 + cell $meminit $meminit$\memory$libresoc.v:0$12929 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12745 + parameter \PRIORITY 12929 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12746 + cell $meminit $meminit$\memory$libresoc.v:0$12930 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12746 + parameter \PRIORITY 12930 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12747 + cell $meminit $meminit$\memory$libresoc.v:0$12931 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12747 + parameter \PRIORITY 12931 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12748 + cell $meminit $meminit$\memory$libresoc.v:0$12932 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12748 + parameter \PRIORITY 12932 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12749 + cell $meminit $meminit$\memory$libresoc.v:0$12933 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12749 + parameter \PRIORITY 12933 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12750 + cell $meminit $meminit$\memory$libresoc.v:0$12934 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12750 + parameter \PRIORITY 12934 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12751 + cell $meminit $meminit$\memory$libresoc.v:0$12935 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12751 + parameter \PRIORITY 12935 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12752 + cell $meminit $meminit$\memory$libresoc.v:0$12936 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12752 + parameter \PRIORITY 12936 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12753 + cell $meminit $meminit$\memory$libresoc.v:0$12937 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12753 + parameter \PRIORITY 12937 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12754 + cell $meminit $meminit$\memory$libresoc.v:0$12938 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12754 + parameter \PRIORITY 12938 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12755 + cell $meminit $meminit$\memory$libresoc.v:0$12939 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12755 + parameter \PRIORITY 12939 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12756 + cell $meminit $meminit$\memory$libresoc.v:0$12940 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12756 + parameter \PRIORITY 12940 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12757 + cell $meminit $meminit$\memory$libresoc.v:0$12941 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12757 + parameter \PRIORITY 12941 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12758 + cell $meminit $meminit$\memory$libresoc.v:0$12942 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12758 + parameter \PRIORITY 12942 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12759 + cell $meminit $meminit$\memory$libresoc.v:0$12943 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12759 + parameter \PRIORITY 12943 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12760 + cell $meminit $meminit$\memory$libresoc.v:0$12944 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12760 + parameter \PRIORITY 12944 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12761 + cell $meminit $meminit$\memory$libresoc.v:0$12945 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12761 + parameter \PRIORITY 12945 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12762 + cell $meminit $meminit$\memory$libresoc.v:0$12946 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12762 + parameter \PRIORITY 12946 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12763 + cell $meminit $meminit$\memory$libresoc.v:0$12947 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12763 + parameter \PRIORITY 12947 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12764 + cell $meminit $meminit$\memory$libresoc.v:0$12948 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12764 + parameter \PRIORITY 12948 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12765 + cell $meminit $meminit$\memory$libresoc.v:0$12949 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12765 + parameter \PRIORITY 12949 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12766 + cell $meminit $meminit$\memory$libresoc.v:0$12950 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12766 + parameter \PRIORITY 12950 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12767 + cell $meminit $meminit$\memory$libresoc.v:0$12951 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12767 + parameter \PRIORITY 12951 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12768 + cell $meminit $meminit$\memory$libresoc.v:0$12952 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12768 + parameter \PRIORITY 12952 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12769 + cell $meminit $meminit$\memory$libresoc.v:0$12953 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12769 + parameter \PRIORITY 12953 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12770 + cell $meminit $meminit$\memory$libresoc.v:0$12954 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12770 + parameter \PRIORITY 12954 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12771 + cell $meminit $meminit$\memory$libresoc.v:0$12955 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12771 + parameter \PRIORITY 12955 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12772 + cell $meminit $meminit$\memory$libresoc.v:0$12956 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12772 + parameter \PRIORITY 12956 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12773 + cell $meminit $meminit$\memory$libresoc.v:0$12957 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12773 + parameter \PRIORITY 12957 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12774 + cell $meminit $meminit$\memory$libresoc.v:0$12958 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12774 + parameter \PRIORITY 12958 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12775 + cell $meminit $meminit$\memory$libresoc.v:0$12959 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12775 + parameter \PRIORITY 12959 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12776 + cell $meminit $meminit$\memory$libresoc.v:0$12960 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12776 + parameter \PRIORITY 12960 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12777 + cell $meminit $meminit$\memory$libresoc.v:0$12961 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12777 + parameter \PRIORITY 12961 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12778 + cell $meminit $meminit$\memory$libresoc.v:0$12962 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12778 + parameter \PRIORITY 12962 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12779 + cell $meminit $meminit$\memory$libresoc.v:0$12963 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12779 + parameter \PRIORITY 12963 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 110 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12780 + cell $meminit $meminit$\memory$libresoc.v:0$12964 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12780 + parameter \PRIORITY 12964 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 111 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12781 + cell $meminit $meminit$\memory$libresoc.v:0$12965 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12781 + parameter \PRIORITY 12965 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 112 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:185940.26-185940.32" - cell $memrd $memrd$\memory$libresoc.v:185940$12664 + attribute \src "libresoc.v:188244.26-188244.32" + cell $memrd $memrd$\memory$libresoc.v:188244$12848 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -388380,83 +392389,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:185940$12664_DATA + connect \DATA $memrd$\memory$libresoc.v:188244$12848_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12782 + cell $memwr $memwr$\memory$libresoc.v:0$12966 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 12782 + parameter \PRIORITY 12966 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:185938$12658_ADDR + connect \ADDR $memwr$\memory$libresoc.v:188242$12842_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:185938$12658_DATA - connect \EN $memwr$\memory$libresoc.v:185938$12658_EN + connect \DATA $memwr$\memory$libresoc.v:188242$12842_DATA + connect \EN $memwr$\memory$libresoc.v:188242$12842_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12785 + process $proc$libresoc.v:0$12969 sync always sync init end - attribute \src "libresoc.v:185785.7-185785.20" - process $proc$libresoc.v:185785$12783 + attribute \src "libresoc.v:188089.7-188089.20" + process $proc$libresoc.v:188089$12967 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185801.7-185801.23" - process $proc$libresoc.v:185801$12784 + attribute \src "libresoc.v:188105.7-188105.23" + process $proc$libresoc.v:188105$12968 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:185817.3-185818.35" - process $proc$libresoc.v:185817$12659 + attribute \src "libresoc.v:188121.3-188122.35" + process $proc$libresoc.v:188121$12843 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:185936.3-185939.6" - process $proc$libresoc.v:185936$12660 + attribute \src "libresoc.v:188240.3-188243.6" + process $proc$libresoc.v:188240$12844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:185938.5-185938.59" + attribute \src "libresoc.v:188242.5-188242.59" switch \spr1__wen - attribute \src "libresoc.v:185938.9-185938.18" + attribute \src "libresoc.v:188242.9-188242.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:185938$12658_ADDR $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 - update $memwr$\memory$libresoc.v:185938$12658_DATA $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 - update $memwr$\memory$libresoc.v:185938$12658_EN $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 + update $memwr$\memory$libresoc.v:188242$12842_ADDR $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + update $memwr$\memory$libresoc.v:188242$12842_DATA $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + update $memwr$\memory$libresoc.v:188242$12842_EN $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 end - attribute \src "libresoc.v:185941.3-185949.6" - process $proc$libresoc.v:185941$12665 + attribute \src "libresoc.v:188245.3-188253.6" + process $proc$libresoc.v:188245$12849 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12666 $1\ren_delay$next[0:0]$12667 - attribute \src "libresoc.v:185942.5-185942.29" + assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188246.5-188246.29" switch \initial - attribute \src "libresoc.v:185942.9-185942.17" + attribute \src "libresoc.v:188246.9-188246.17" case 1'1 case end @@ -388465,21 +392474,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12667 1'0 + assign $1\ren_delay$next[0:0]$12851 1'0 case - assign $1\ren_delay$next[0:0]$12667 \spr1__ren + assign $1\ren_delay$next[0:0]$12851 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12666 + update \ren_delay$next $0\ren_delay$next[0:0]$12850 end - attribute \src "libresoc.v:185950.3-185959.6" - process $proc$libresoc.v:185950$12668 + attribute \src "libresoc.v:188254.3-188263.6" + process $proc$libresoc.v:188254$12852 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:185951.5-185951.29" + attribute \src "libresoc.v:188255.5-188255.29" switch \initial - attribute \src "libresoc.v:185951.9-185951.17" + attribute \src "libresoc.v:188255.9-188255.17" case 1'1 case end @@ -388495,503 +392504,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:185940$12664_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:188244$12848_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:185968.1-187221.10" +attribute \src "libresoc.v:188272.1-189525.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:186718.3-186719.25" + attribute \src "libresoc.v:189022.3-189023.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:186716.3-186717.40" + attribute \src "libresoc.v:189020.3-189021.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:187112.3-187120.6" - wire $0\alu_l_r_alu$next[0:0]$12999 - attribute \src "libresoc.v:186646.3-186647.39" + attribute \src "libresoc.v:189416.3-189424.6" + wire $0\alu_l_r_alu$next[0:0]$13183 + attribute \src "libresoc.v:188950.3-188951.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 - attribute \src "libresoc.v:186688.3-186689.65" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + attribute \src "libresoc.v:188992.3-188993.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12922 - attribute \src "libresoc.v:186690.3-186691.59" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 + attribute \src "libresoc.v:188994.3-188995.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 - attribute \src "libresoc.v:186686.3-186687.69" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + attribute \src "libresoc.v:188990.3-188991.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 - attribute \src "libresoc.v:186692.3-186693.67" + attribute \src "libresoc.v:189202.3-189214.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + attribute \src "libresoc.v:188996.3-188997.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:187103.3-187111.6" - wire $0\alui_l_r_alui$next[0:0]$12996 - attribute \src "libresoc.v:186648.3-186649.43" + attribute \src "libresoc.v:189407.3-189415.6" + wire $0\alui_l_r_alui$next[0:0]$13180 + attribute \src "libresoc.v:188952.3-188953.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $0\data_r0__o$next[63:0]$12930 - attribute \src "libresoc.v:186682.3-186683.37" + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $0\data_r0__o$next[63:0]$13114 + attribute \src "libresoc.v:188986.3-188987.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire $0\data_r0__o_ok$next[0:0]$12931 - attribute \src "libresoc.v:186684.3-186685.43" + attribute \src "libresoc.v:189215.3-189236.6" + wire $0\data_r0__o_ok$next[0:0]$13115 + attribute \src "libresoc.v:188988.3-188989.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12938 - attribute \src "libresoc.v:186678.3-186679.43" + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $0\data_r1__spr1$next[63:0]$13122 + attribute \src "libresoc.v:188982.3-188983.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire $0\data_r1__spr1_ok$next[0:0]$12939 - attribute \src "libresoc.v:186680.3-186681.49" + attribute \src "libresoc.v:189237.3-189258.6" + wire $0\data_r1__spr1_ok$next[0:0]$13123 + attribute \src "libresoc.v:188984.3-188985.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12946 - attribute \src "libresoc.v:186674.3-186675.45" + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $0\data_r2__fast1$next[63:0]$13130 + attribute \src "libresoc.v:188978.3-188979.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire $0\data_r2__fast1_ok$next[0:0]$12947 - attribute \src "libresoc.v:186676.3-186677.51" + attribute \src "libresoc.v:189259.3-189280.6" + wire $0\data_r2__fast1_ok$next[0:0]$13131 + attribute \src "libresoc.v:188980.3-188981.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $0\data_r3__xer_so$next[0:0]$12954 - attribute \src "libresoc.v:186670.3-186671.47" + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so$next[0:0]$13138 + attribute \src "libresoc.v:188974.3-188975.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12955 - attribute \src "libresoc.v:186672.3-186673.53" + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so_ok$next[0:0]$13139 + attribute \src "libresoc.v:188976.3-188977.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12962 - attribute \src "libresoc.v:186666.3-186667.47" + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 + attribute \src "libresoc.v:188970.3-188971.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12963 - attribute \src "libresoc.v:186668.3-186669.53" + attribute \src "libresoc.v:189303.3-189324.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13147 + attribute \src "libresoc.v:188972.3-188973.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12970 - attribute \src "libresoc.v:186662.3-186663.47" + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 + attribute \src "libresoc.v:188966.3-188967.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12971 - attribute \src "libresoc.v:186664.3-186665.53" + attribute \src "libresoc.v:189325.3-189346.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13155 + attribute \src "libresoc.v:188968.3-188969.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:187121.3-187130.6" + attribute \src "libresoc.v:189425.3-189434.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:187131.3-187140.6" + attribute \src "libresoc.v:189435.3-189444.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:187141.3-187150.6" + attribute \src "libresoc.v:189445.3-189454.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:187151.3-187160.6" + attribute \src "libresoc.v:189455.3-189464.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:187161.3-187170.6" + attribute \src "libresoc.v:189465.3-189474.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:187171.3-187180.6" + attribute \src "libresoc.v:189475.3-189484.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:185969.7-185969.20" + attribute \src "libresoc.v:188273.7-188273.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186853.3-186861.6" - wire $0\opc_l_r_opc$next[0:0]$12906 - attribute \src "libresoc.v:186702.3-186703.39" + attribute \src "libresoc.v:189157.3-189165.6" + wire $0\opc_l_r_opc$next[0:0]$13090 + attribute \src "libresoc.v:189006.3-189007.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:186844.3-186852.6" - wire $0\opc_l_s_opc$next[0:0]$12903 - attribute \src "libresoc.v:186704.3-186705.39" + attribute \src "libresoc.v:189148.3-189156.6" + wire $0\opc_l_s_opc$next[0:0]$13087 + attribute \src "libresoc.v:189008.3-189009.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187181.3-187189.6" - wire width 6 $0\prev_wr_go$next[5:0]$13008 - attribute \src "libresoc.v:186714.3-186715.37" + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $0\prev_wr_go$next[5:0]$13192 + attribute \src "libresoc.v:189018.3-189019.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:186798.3-186807.6" + attribute \src "libresoc.v:189102.3-189111.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:186889.3-186897.6" - wire width 6 $0\req_l_r_req$next[5:0]$12918 - attribute \src "libresoc.v:186694.3-186695.39" + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $0\req_l_r_req$next[5:0]$13102 + attribute \src "libresoc.v:188998.3-188999.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:186880.3-186888.6" - wire width 6 $0\req_l_s_req$next[5:0]$12915 - attribute \src "libresoc.v:186696.3-186697.39" + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $0\req_l_s_req$next[5:0]$13099 + attribute \src "libresoc.v:189000.3-189001.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:186817.3-186825.6" - wire $0\rok_l_r_rdok$next[0:0]$12894 - attribute \src "libresoc.v:186710.3-186711.41" + attribute \src "libresoc.v:189121.3-189129.6" + wire $0\rok_l_r_rdok$next[0:0]$13078 + attribute \src "libresoc.v:189014.3-189015.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:186808.3-186816.6" - wire $0\rok_l_s_rdok$next[0:0]$12891 - attribute \src "libresoc.v:186712.3-186713.41" + attribute \src "libresoc.v:189112.3-189120.6" + wire $0\rok_l_s_rdok$next[0:0]$13075 + attribute \src "libresoc.v:189016.3-189017.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:186835.3-186843.6" - wire $0\rst_l_r_rst$next[0:0]$12900 - attribute \src "libresoc.v:186706.3-186707.39" + attribute \src "libresoc.v:189139.3-189147.6" + wire $0\rst_l_r_rst$next[0:0]$13084 + attribute \src "libresoc.v:189010.3-189011.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:186826.3-186834.6" - wire $0\rst_l_s_rst$next[0:0]$12897 - attribute \src "libresoc.v:186708.3-186709.39" + attribute \src "libresoc.v:189130.3-189138.6" + wire $0\rst_l_s_rst$next[0:0]$13081 + attribute \src "libresoc.v:189012.3-189013.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:186871.3-186879.6" - wire width 6 $0\src_l_r_src$next[5:0]$12912 - attribute \src "libresoc.v:186698.3-186699.39" + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $0\src_l_r_src$next[5:0]$13096 + attribute \src "libresoc.v:189002.3-189003.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:186862.3-186870.6" - wire width 6 $0\src_l_s_src$next[5:0]$12909 - attribute \src "libresoc.v:186700.3-186701.39" + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $0\src_l_s_src$next[5:0]$13093 + attribute \src "libresoc.v:189004.3-189005.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:187043.3-187052.6" - wire width 64 $0\src_r0$next[63:0]$12978 - attribute \src "libresoc.v:186660.3-186661.29" + attribute \src "libresoc.v:189347.3-189356.6" + wire width 64 $0\src_r0$next[63:0]$13162 + attribute \src "libresoc.v:188964.3-188965.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187053.3-187062.6" - wire width 64 $0\src_r1$next[63:0]$12981 - attribute \src "libresoc.v:186658.3-186659.29" + attribute \src "libresoc.v:189357.3-189366.6" + wire width 64 $0\src_r1$next[63:0]$13165 + attribute \src "libresoc.v:188962.3-188963.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187063.3-187072.6" - wire width 64 $0\src_r2$next[63:0]$12984 - attribute \src "libresoc.v:186656.3-186657.29" + attribute \src "libresoc.v:189367.3-189376.6" + wire width 64 $0\src_r2$next[63:0]$13168 + attribute \src "libresoc.v:188960.3-188961.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187073.3-187082.6" - wire $0\src_r3$next[0:0]$12987 - attribute \src "libresoc.v:186654.3-186655.29" + attribute \src "libresoc.v:189377.3-189386.6" + wire $0\src_r3$next[0:0]$13171 + attribute \src "libresoc.v:188958.3-188959.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:187083.3-187092.6" - wire width 2 $0\src_r4$next[1:0]$12990 - attribute \src "libresoc.v:186652.3-186653.29" + attribute \src "libresoc.v:189387.3-189396.6" + wire width 2 $0\src_r4$next[1:0]$13174 + attribute \src "libresoc.v:188956.3-188957.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:187093.3-187102.6" - wire width 2 $0\src_r5$next[1:0]$12993 - attribute \src "libresoc.v:186650.3-186651.29" + attribute \src "libresoc.v:189397.3-189406.6" + wire width 2 $0\src_r5$next[1:0]$13177 + attribute \src "libresoc.v:188954.3-188955.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:186105.7-186105.24" + attribute \src "libresoc.v:188409.7-188409.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:186115.7-186115.26" + attribute \src "libresoc.v:188419.7-188419.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:187112.3-187120.6" - wire $1\alu_l_r_alu$next[0:0]$13000 - attribute \src "libresoc.v:186123.7-186123.25" + attribute \src "libresoc.v:189416.3-189424.6" + wire $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:188427.7-188427.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 - attribute \src "libresoc.v:186168.14-186168.49" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + attribute \src "libresoc.v:188472.14-188472.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12926 - attribute \src "libresoc.v:186172.14-186172.43" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + attribute \src "libresoc.v:188476.14-188476.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 - attribute \src "libresoc.v:186251.13-186251.47" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + attribute \src "libresoc.v:188555.13-188555.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 - attribute \src "libresoc.v:186255.7-186255.39" + attribute \src "libresoc.v:189202.3-189214.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:188559.7-188559.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:187103.3-187111.6" - wire $1\alui_l_r_alui$next[0:0]$12997 - attribute \src "libresoc.v:186273.7-186273.27" + attribute \src "libresoc.v:189407.3-189415.6" + wire $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:188577.7-188577.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $1\data_r0__o$next[63:0]$12932 - attribute \src "libresoc.v:186305.14-186305.47" + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $1\data_r0__o$next[63:0]$13116 + attribute \src "libresoc.v:188609.14-188609.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire $1\data_r0__o_ok$next[0:0]$12933 - attribute \src "libresoc.v:186309.7-186309.27" + attribute \src "libresoc.v:189215.3-189236.6" + wire $1\data_r0__o_ok$next[0:0]$13117 + attribute \src "libresoc.v:188613.7-188613.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12940 - attribute \src "libresoc.v:186313.14-186313.50" + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $1\data_r1__spr1$next[63:0]$13124 + attribute \src "libresoc.v:188617.14-188617.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire $1\data_r1__spr1_ok$next[0:0]$12941 - attribute \src "libresoc.v:186317.7-186317.30" + attribute \src "libresoc.v:189237.3-189258.6" + wire $1\data_r1__spr1_ok$next[0:0]$13125 + attribute \src "libresoc.v:188621.7-188621.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12948 - attribute \src "libresoc.v:186321.14-186321.51" + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $1\data_r2__fast1$next[63:0]$13132 + attribute \src "libresoc.v:188625.14-188625.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire $1\data_r2__fast1_ok$next[0:0]$12949 - attribute \src "libresoc.v:186325.7-186325.31" + attribute \src "libresoc.v:189259.3-189280.6" + wire $1\data_r2__fast1_ok$next[0:0]$13133 + attribute \src "libresoc.v:188629.7-188629.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $1\data_r3__xer_so$next[0:0]$12956 - attribute \src "libresoc.v:186329.7-186329.29" + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so$next[0:0]$13140 + attribute \src "libresoc.v:188633.7-188633.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12957 - attribute \src "libresoc.v:186333.7-186333.32" + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so_ok$next[0:0]$13141 + attribute \src "libresoc.v:188637.7-188637.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12964 - attribute \src "libresoc.v:186337.13-186337.35" + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 + attribute \src "libresoc.v:188641.13-188641.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12965 - attribute \src "libresoc.v:186341.7-186341.32" + attribute \src "libresoc.v:189303.3-189324.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13149 + attribute \src "libresoc.v:188645.7-188645.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12972 - attribute \src "libresoc.v:186345.13-186345.35" + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 + attribute \src "libresoc.v:188649.13-188649.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12973 - attribute \src "libresoc.v:186349.7-186349.32" + attribute \src "libresoc.v:189325.3-189346.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13157 + attribute \src "libresoc.v:188653.7-188653.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:187121.3-187130.6" + attribute \src "libresoc.v:189425.3-189434.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:187131.3-187140.6" + attribute \src "libresoc.v:189435.3-189444.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:187141.3-187150.6" + attribute \src "libresoc.v:189445.3-189454.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:187151.3-187160.6" + attribute \src "libresoc.v:189455.3-189464.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:187161.3-187170.6" + attribute \src "libresoc.v:189465.3-189474.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:187171.3-187180.6" + attribute \src "libresoc.v:189475.3-189484.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:186853.3-186861.6" - wire $1\opc_l_r_opc$next[0:0]$12907 - attribute \src "libresoc.v:186377.7-186377.25" + attribute \src "libresoc.v:189157.3-189165.6" + wire $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:188681.7-188681.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:186844.3-186852.6" - wire $1\opc_l_s_opc$next[0:0]$12904 - attribute \src "libresoc.v:186381.7-186381.25" + attribute \src "libresoc.v:189148.3-189156.6" + wire $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:188685.7-188685.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187181.3-187189.6" - wire width 6 $1\prev_wr_go$next[5:0]$13009 - attribute \src "libresoc.v:186483.13-186483.31" + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:188787.13-188787.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:186798.3-186807.6" + attribute \src "libresoc.v:189102.3-189111.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:186889.3-186897.6" - wire width 6 $1\req_l_r_req$next[5:0]$12919 - attribute \src "libresoc.v:186491.13-186491.32" + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:188795.13-188795.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:186880.3-186888.6" - wire width 6 $1\req_l_s_req$next[5:0]$12916 - attribute \src "libresoc.v:186495.13-186495.32" + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:188799.13-188799.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:186817.3-186825.6" - wire $1\rok_l_r_rdok$next[0:0]$12895 - attribute \src "libresoc.v:186507.7-186507.26" + attribute \src "libresoc.v:189121.3-189129.6" + wire $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:188811.7-188811.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:186808.3-186816.6" - wire $1\rok_l_s_rdok$next[0:0]$12892 - attribute \src "libresoc.v:186511.7-186511.26" + attribute \src "libresoc.v:189112.3-189120.6" + wire $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:188815.7-188815.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:186835.3-186843.6" - wire $1\rst_l_r_rst$next[0:0]$12901 - attribute \src "libresoc.v:186515.7-186515.25" + attribute \src "libresoc.v:189139.3-189147.6" + wire $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:188819.7-188819.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:186826.3-186834.6" - wire $1\rst_l_s_rst$next[0:0]$12898 - attribute \src "libresoc.v:186519.7-186519.25" + attribute \src "libresoc.v:189130.3-189138.6" + wire $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:188823.7-188823.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:186871.3-186879.6" - wire width 6 $1\src_l_r_src$next[5:0]$12913 - attribute \src "libresoc.v:186541.13-186541.32" + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:188845.13-188845.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:186862.3-186870.6" - wire width 6 $1\src_l_s_src$next[5:0]$12910 - attribute \src "libresoc.v:186545.13-186545.32" + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $1\src_l_s_src$next[5:0]$13094 + attribute \src "libresoc.v:188849.13-188849.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:187043.3-187052.6" - wire width 64 $1\src_r0$next[63:0]$12979 - attribute \src "libresoc.v:186549.14-186549.43" + attribute \src "libresoc.v:189347.3-189356.6" + wire width 64 $1\src_r0$next[63:0]$13163 + attribute \src "libresoc.v:188853.14-188853.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187053.3-187062.6" - wire width 64 $1\src_r1$next[63:0]$12982 - attribute \src "libresoc.v:186553.14-186553.43" + attribute \src "libresoc.v:189357.3-189366.6" + wire width 64 $1\src_r1$next[63:0]$13166 + attribute \src "libresoc.v:188857.14-188857.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187063.3-187072.6" - wire width 64 $1\src_r2$next[63:0]$12985 - attribute \src "libresoc.v:186557.14-186557.43" + attribute \src "libresoc.v:189367.3-189376.6" + wire width 64 $1\src_r2$next[63:0]$13169 + attribute \src "libresoc.v:188861.14-188861.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187073.3-187082.6" - wire $1\src_r3$next[0:0]$12988 - attribute \src "libresoc.v:186561.7-186561.20" + attribute \src "libresoc.v:189377.3-189386.6" + wire $1\src_r3$next[0:0]$13172 + attribute \src "libresoc.v:188865.7-188865.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:187083.3-187092.6" - wire width 2 $1\src_r4$next[1:0]$12991 - attribute \src "libresoc.v:186565.13-186565.26" + attribute \src "libresoc.v:189387.3-189396.6" + wire width 2 $1\src_r4$next[1:0]$13175 + attribute \src "libresoc.v:188869.13-188869.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:187093.3-187102.6" - wire width 2 $1\src_r5$next[1:0]$12994 - attribute \src "libresoc.v:186569.13-186569.26" + attribute \src "libresoc.v:189397.3-189406.6" + wire width 2 $1\src_r5$next[1:0]$13178 + attribute \src "libresoc.v:188873.13-188873.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $2\data_r0__o$next[63:0]$12934 - attribute \src "libresoc.v:186911.3-186932.6" - wire $2\data_r0__o_ok$next[0:0]$12935 - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12942 - attribute \src "libresoc.v:186933.3-186954.6" - wire $2\data_r1__spr1_ok$next[0:0]$12943 - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12950 - attribute \src "libresoc.v:186955.3-186976.6" - wire $2\data_r2__fast1_ok$next[0:0]$12951 - attribute \src "libresoc.v:186977.3-186998.6" - wire $2\data_r3__xer_so$next[0:0]$12958 - attribute \src "libresoc.v:186977.3-186998.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12959 - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12966 - attribute \src "libresoc.v:186999.3-187020.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12967 - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12974 - attribute \src "libresoc.v:187021.3-187042.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12975 - attribute \src "libresoc.v:186911.3-186932.6" - wire $3\data_r0__o_ok$next[0:0]$12936 - attribute \src "libresoc.v:186933.3-186954.6" - wire $3\data_r1__spr1_ok$next[0:0]$12944 - attribute \src "libresoc.v:186955.3-186976.6" - wire $3\data_r2__fast1_ok$next[0:0]$12952 - attribute \src "libresoc.v:186977.3-186998.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12960 - attribute \src "libresoc.v:186999.3-187020.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12968 - attribute \src "libresoc.v:187021.3-187042.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12976 - attribute \src "libresoc.v:186581.19-186581.133" - wire $and$libresoc.v:186581$12787_Y - attribute \src "libresoc.v:186582.19-186582.183" - wire width 6 $and$libresoc.v:186582$12788_Y - attribute \src "libresoc.v:186583.19-186583.115" - wire width 6 $and$libresoc.v:186583$12789_Y - attribute \src "libresoc.v:186585.19-186585.115" - wire width 6 $and$libresoc.v:186585$12791_Y - attribute \src "libresoc.v:186586.19-186586.125" - wire $and$libresoc.v:186586$12792_Y - attribute \src "libresoc.v:186587.19-186587.125" - wire $and$libresoc.v:186587$12793_Y - attribute \src "libresoc.v:186588.19-186588.125" - wire $and$libresoc.v:186588$12794_Y - attribute \src "libresoc.v:186589.19-186589.125" - wire $and$libresoc.v:186589$12795_Y - attribute \src "libresoc.v:186590.19-186590.125" - wire $and$libresoc.v:186590$12796_Y - attribute \src "libresoc.v:186592.19-186592.125" - wire $and$libresoc.v:186592$12798_Y - attribute \src "libresoc.v:186593.19-186593.165" - wire width 6 $and$libresoc.v:186593$12799_Y - attribute \src "libresoc.v:186594.19-186594.121" - wire width 6 $and$libresoc.v:186594$12800_Y - attribute \src "libresoc.v:186595.19-186595.127" - wire $and$libresoc.v:186595$12801_Y - attribute \src "libresoc.v:186596.19-186596.127" - wire $and$libresoc.v:186596$12802_Y - attribute \src "libresoc.v:186598.19-186598.127" - wire $and$libresoc.v:186598$12804_Y - attribute \src "libresoc.v:186599.19-186599.127" - wire $and$libresoc.v:186599$12805_Y - attribute \src "libresoc.v:186600.19-186600.127" - wire $and$libresoc.v:186600$12806_Y - attribute \src "libresoc.v:186601.19-186601.127" - wire $and$libresoc.v:186601$12807_Y - attribute \src "libresoc.v:186602.18-186602.110" - wire $and$libresoc.v:186602$12808_Y - attribute \src "libresoc.v:186604.18-186604.98" - wire $and$libresoc.v:186604$12810_Y - attribute \src "libresoc.v:186606.18-186606.100" - wire $and$libresoc.v:186606$12812_Y - attribute \src "libresoc.v:186607.18-186607.182" - wire width 6 $and$libresoc.v:186607$12813_Y - attribute \src "libresoc.v:186609.18-186609.119" - wire width 6 $and$libresoc.v:186609$12815_Y - attribute \src "libresoc.v:186612.18-186612.116" - wire $and$libresoc.v:186612$12818_Y - attribute \src "libresoc.v:186617.18-186617.113" - wire $and$libresoc.v:186617$12823_Y - attribute \src "libresoc.v:186618.18-186618.125" - wire width 6 $and$libresoc.v:186618$12824_Y - attribute \src "libresoc.v:186620.18-186620.112" - wire $and$libresoc.v:186620$12826_Y - attribute \src "libresoc.v:186622.18-186622.126" - wire $and$libresoc.v:186622$12828_Y - attribute \src "libresoc.v:186623.18-186623.126" - wire $and$libresoc.v:186623$12829_Y - attribute \src "libresoc.v:186624.18-186624.117" - wire $and$libresoc.v:186624$12830_Y - attribute \src "libresoc.v:186629.18-186629.130" - wire $and$libresoc.v:186629$12835_Y - attribute \src "libresoc.v:186630.17-186630.123" - wire $and$libresoc.v:186630$12836_Y - attribute \src "libresoc.v:186631.18-186631.124" - wire width 6 $and$libresoc.v:186631$12837_Y - attribute \src "libresoc.v:186633.18-186633.116" - wire $and$libresoc.v:186633$12839_Y - attribute \src "libresoc.v:186634.18-186634.119" - wire $and$libresoc.v:186634$12840_Y - attribute \src "libresoc.v:186635.18-186635.120" - wire $and$libresoc.v:186635$12841_Y - attribute \src "libresoc.v:186636.18-186636.121" - wire $and$libresoc.v:186636$12842_Y - attribute \src "libresoc.v:186637.18-186637.121" - wire $and$libresoc.v:186637$12843_Y - attribute \src "libresoc.v:186638.18-186638.121" - wire $and$libresoc.v:186638$12844_Y - attribute \src "libresoc.v:186645.18-186645.134" - wire $and$libresoc.v:186645$12851_Y - attribute \src "libresoc.v:186619.18-186619.113" - wire $eq$libresoc.v:186619$12825_Y - attribute \src "libresoc.v:186621.18-186621.119" - wire $eq$libresoc.v:186621$12827_Y - attribute \src "libresoc.v:186580.17-186580.113" - wire width 6 $not$libresoc.v:186580$12786_Y - attribute \src "libresoc.v:186584.19-186584.115" - wire width 6 $not$libresoc.v:186584$12790_Y - attribute \src "libresoc.v:186603.18-186603.97" - wire $not$libresoc.v:186603$12809_Y - attribute \src "libresoc.v:186605.18-186605.99" - wire $not$libresoc.v:186605$12811_Y - attribute \src "libresoc.v:186608.18-186608.113" - wire width 6 $not$libresoc.v:186608$12814_Y - attribute \src "libresoc.v:186611.18-186611.106" - wire $not$libresoc.v:186611$12817_Y - attribute \src "libresoc.v:186616.18-186616.120" - wire $not$libresoc.v:186616$12822_Y - attribute \src "libresoc.v:186591.18-186591.118" - wire width 6 $or$libresoc.v:186591$12797_Y - attribute \src "libresoc.v:186615.18-186615.112" - wire $or$libresoc.v:186615$12821_Y - attribute \src "libresoc.v:186625.18-186625.122" - wire $or$libresoc.v:186625$12831_Y - attribute \src "libresoc.v:186626.18-186626.124" - wire $or$libresoc.v:186626$12832_Y - attribute \src "libresoc.v:186627.18-186627.194" - wire width 6 $or$libresoc.v:186627$12833_Y - attribute \src "libresoc.v:186628.18-186628.194" - wire width 6 $or$libresoc.v:186628$12834_Y - attribute \src "libresoc.v:186632.18-186632.120" - wire width 6 $or$libresoc.v:186632$12838_Y - attribute \src "libresoc.v:186597.17-186597.105" - wire $reduce_and$libresoc.v:186597$12803_Y - attribute \src "libresoc.v:186610.18-186610.106" - wire $reduce_or$libresoc.v:186610$12816_Y - attribute \src "libresoc.v:186613.18-186613.113" - wire $reduce_or$libresoc.v:186613$12819_Y - attribute \src "libresoc.v:186614.18-186614.112" - wire $reduce_or$libresoc.v:186614$12820_Y - attribute \src "libresoc.v:186639.18-186639.118" - wire width 64 $ternary$libresoc.v:186639$12845_Y - attribute \src "libresoc.v:186640.18-186640.118" - wire width 64 $ternary$libresoc.v:186640$12846_Y - attribute \src "libresoc.v:186641.18-186641.118" - wire width 64 $ternary$libresoc.v:186641$12847_Y - attribute \src "libresoc.v:186642.18-186642.118" - wire $ternary$libresoc.v:186642$12848_Y - attribute \src "libresoc.v:186643.18-186643.118" - wire width 2 $ternary$libresoc.v:186643$12849_Y - attribute \src "libresoc.v:186644.18-186644.118" - wire width 2 $ternary$libresoc.v:186644$12850_Y + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $2\data_r0__o$next[63:0]$13118 + attribute \src "libresoc.v:189215.3-189236.6" + wire $2\data_r0__o_ok$next[0:0]$13119 + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $2\data_r1__spr1$next[63:0]$13126 + attribute \src "libresoc.v:189237.3-189258.6" + wire $2\data_r1__spr1_ok$next[0:0]$13127 + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $2\data_r2__fast1$next[63:0]$13134 + attribute \src "libresoc.v:189259.3-189280.6" + wire $2\data_r2__fast1_ok$next[0:0]$13135 + attribute \src "libresoc.v:189281.3-189302.6" + wire $2\data_r3__xer_so$next[0:0]$13142 + attribute \src "libresoc.v:189281.3-189302.6" + wire $2\data_r3__xer_so_ok$next[0:0]$13143 + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$13150 + attribute \src "libresoc.v:189303.3-189324.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$13151 + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$13158 + attribute \src "libresoc.v:189325.3-189346.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$13159 + attribute \src "libresoc.v:189215.3-189236.6" + wire $3\data_r0__o_ok$next[0:0]$13120 + attribute \src "libresoc.v:189237.3-189258.6" + wire $3\data_r1__spr1_ok$next[0:0]$13128 + attribute \src "libresoc.v:189259.3-189280.6" + wire $3\data_r2__fast1_ok$next[0:0]$13136 + attribute \src "libresoc.v:189281.3-189302.6" + wire $3\data_r3__xer_so_ok$next[0:0]$13144 + attribute \src "libresoc.v:189303.3-189324.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$13152 + attribute \src "libresoc.v:189325.3-189346.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$13160 + attribute \src "libresoc.v:188885.19-188885.133" + wire $and$libresoc.v:188885$12971_Y + attribute \src "libresoc.v:188886.19-188886.183" + wire width 6 $and$libresoc.v:188886$12972_Y + attribute \src "libresoc.v:188887.19-188887.115" + wire width 6 $and$libresoc.v:188887$12973_Y + attribute \src "libresoc.v:188889.19-188889.115" + wire width 6 $and$libresoc.v:188889$12975_Y + attribute \src "libresoc.v:188890.19-188890.125" + wire $and$libresoc.v:188890$12976_Y + attribute \src "libresoc.v:188891.19-188891.125" + wire $and$libresoc.v:188891$12977_Y + attribute \src "libresoc.v:188892.19-188892.125" + wire $and$libresoc.v:188892$12978_Y + attribute \src "libresoc.v:188893.19-188893.125" + wire $and$libresoc.v:188893$12979_Y + attribute \src "libresoc.v:188894.19-188894.125" + wire $and$libresoc.v:188894$12980_Y + attribute \src "libresoc.v:188896.19-188896.125" + wire $and$libresoc.v:188896$12982_Y + attribute \src "libresoc.v:188897.19-188897.165" + wire width 6 $and$libresoc.v:188897$12983_Y + attribute \src "libresoc.v:188898.19-188898.121" + wire width 6 $and$libresoc.v:188898$12984_Y + attribute \src "libresoc.v:188899.19-188899.127" + wire $and$libresoc.v:188899$12985_Y + attribute \src "libresoc.v:188900.19-188900.127" + wire $and$libresoc.v:188900$12986_Y + attribute \src "libresoc.v:188902.19-188902.127" + wire $and$libresoc.v:188902$12988_Y + attribute \src "libresoc.v:188903.19-188903.127" + wire $and$libresoc.v:188903$12989_Y + attribute \src "libresoc.v:188904.19-188904.127" + wire $and$libresoc.v:188904$12990_Y + attribute \src "libresoc.v:188905.19-188905.127" + wire $and$libresoc.v:188905$12991_Y + attribute \src "libresoc.v:188906.18-188906.110" + wire $and$libresoc.v:188906$12992_Y + attribute \src "libresoc.v:188908.18-188908.98" + wire $and$libresoc.v:188908$12994_Y + attribute \src "libresoc.v:188910.18-188910.100" + wire $and$libresoc.v:188910$12996_Y + attribute \src "libresoc.v:188911.18-188911.182" + wire width 6 $and$libresoc.v:188911$12997_Y + attribute \src "libresoc.v:188913.18-188913.119" + wire width 6 $and$libresoc.v:188913$12999_Y + attribute \src "libresoc.v:188916.18-188916.116" + wire $and$libresoc.v:188916$13002_Y + attribute \src "libresoc.v:188921.18-188921.113" + wire $and$libresoc.v:188921$13007_Y + attribute \src "libresoc.v:188922.18-188922.125" + wire width 6 $and$libresoc.v:188922$13008_Y + attribute \src "libresoc.v:188924.18-188924.112" + wire $and$libresoc.v:188924$13010_Y + attribute \src "libresoc.v:188926.18-188926.126" + wire $and$libresoc.v:188926$13012_Y + attribute \src "libresoc.v:188927.18-188927.126" + wire $and$libresoc.v:188927$13013_Y + attribute \src "libresoc.v:188928.18-188928.117" + wire $and$libresoc.v:188928$13014_Y + attribute \src "libresoc.v:188933.18-188933.130" + wire $and$libresoc.v:188933$13019_Y + attribute \src "libresoc.v:188934.17-188934.123" + wire $and$libresoc.v:188934$13020_Y + attribute \src "libresoc.v:188935.18-188935.124" + wire width 6 $and$libresoc.v:188935$13021_Y + attribute \src "libresoc.v:188937.18-188937.116" + wire $and$libresoc.v:188937$13023_Y + attribute \src "libresoc.v:188938.18-188938.119" + wire $and$libresoc.v:188938$13024_Y + attribute \src "libresoc.v:188939.18-188939.120" + wire $and$libresoc.v:188939$13025_Y + attribute \src "libresoc.v:188940.18-188940.121" + wire $and$libresoc.v:188940$13026_Y + attribute \src "libresoc.v:188941.18-188941.121" + wire $and$libresoc.v:188941$13027_Y + attribute \src "libresoc.v:188942.18-188942.121" + wire $and$libresoc.v:188942$13028_Y + attribute \src "libresoc.v:188949.18-188949.134" + wire $and$libresoc.v:188949$13035_Y + attribute \src "libresoc.v:188923.18-188923.113" + wire $eq$libresoc.v:188923$13009_Y + attribute \src "libresoc.v:188925.18-188925.119" + wire $eq$libresoc.v:188925$13011_Y + attribute \src "libresoc.v:188884.17-188884.113" + wire width 6 $not$libresoc.v:188884$12970_Y + attribute \src "libresoc.v:188888.19-188888.115" + wire width 6 $not$libresoc.v:188888$12974_Y + attribute \src "libresoc.v:188907.18-188907.97" + wire $not$libresoc.v:188907$12993_Y + attribute \src "libresoc.v:188909.18-188909.99" + wire $not$libresoc.v:188909$12995_Y + attribute \src "libresoc.v:188912.18-188912.113" + wire width 6 $not$libresoc.v:188912$12998_Y + attribute \src "libresoc.v:188915.18-188915.106" + wire $not$libresoc.v:188915$13001_Y + attribute \src "libresoc.v:188920.18-188920.120" + wire $not$libresoc.v:188920$13006_Y + attribute \src "libresoc.v:188895.18-188895.118" + wire width 6 $or$libresoc.v:188895$12981_Y + attribute \src "libresoc.v:188919.18-188919.112" + wire $or$libresoc.v:188919$13005_Y + attribute \src "libresoc.v:188929.18-188929.122" + wire $or$libresoc.v:188929$13015_Y + attribute \src "libresoc.v:188930.18-188930.124" + wire $or$libresoc.v:188930$13016_Y + attribute \src "libresoc.v:188931.18-188931.194" + wire width 6 $or$libresoc.v:188931$13017_Y + attribute \src "libresoc.v:188932.18-188932.194" + wire width 6 $or$libresoc.v:188932$13018_Y + attribute \src "libresoc.v:188936.18-188936.120" + wire width 6 $or$libresoc.v:188936$13022_Y + attribute \src "libresoc.v:188901.17-188901.105" + wire $reduce_and$libresoc.v:188901$12987_Y + attribute \src "libresoc.v:188914.18-188914.106" + wire $reduce_or$libresoc.v:188914$13000_Y + attribute \src "libresoc.v:188917.18-188917.113" + wire $reduce_or$libresoc.v:188917$13003_Y + attribute \src "libresoc.v:188918.18-188918.112" + wire $reduce_or$libresoc.v:188918$13004_Y + attribute \src "libresoc.v:188943.18-188943.118" + wire width 64 $ternary$libresoc.v:188943$13029_Y + attribute \src "libresoc.v:188944.18-188944.118" + wire width 64 $ternary$libresoc.v:188944$13030_Y + attribute \src "libresoc.v:188945.18-188945.118" + wire width 64 $ternary$libresoc.v:188945$13031_Y + attribute \src "libresoc.v:188946.18-188946.118" + wire $ternary$libresoc.v:188946$13032_Y + attribute \src "libresoc.v:188947.18-188947.118" + wire width 2 $ternary$libresoc.v:188947$13033_Y + attribute \src "libresoc.v:188948.18-188948.118" + wire width 2 $ternary$libresoc.v:188948$13034_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -389300,9 +393309,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -389388,7 +393397,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:185969.7-185969.15" + attribute \src "libresoc.v:188273.7-188273.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -389599,7 +393608,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:186581$12787 + cell $and $and$libresoc.v:188885$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389607,10 +393616,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:186581$12787_Y + connect \Y $and$libresoc.v:188885$12971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186582$12788 + cell $and $and$libresoc.v:188886$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389618,10 +393627,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:186582$12788_Y + connect \Y $and$libresoc.v:188886$12972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186583$12789 + cell $and $and$libresoc.v:188887$12973 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389629,10 +393638,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:186583$12789_Y + connect \Y $and$libresoc.v:188887$12973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186585$12791 + cell $and $and$libresoc.v:188889$12975 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389640,10 +393649,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:186585$12791_Y + connect \Y $and$libresoc.v:188889$12975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186586$12792 + cell $and $and$libresoc.v:188890$12976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389651,10 +393660,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186586$12792_Y + connect \Y $and$libresoc.v:188890$12976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186587$12793 + cell $and $and$libresoc.v:188891$12977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389662,10 +393671,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186587$12793_Y + connect \Y $and$libresoc.v:188891$12977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186588$12794 + cell $and $and$libresoc.v:188892$12978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389673,10 +393682,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186588$12794_Y + connect \Y $and$libresoc.v:188892$12978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186589$12795 + cell $and $and$libresoc.v:188893$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389684,10 +393693,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186589$12795_Y + connect \Y $and$libresoc.v:188893$12979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186590$12796 + cell $and $and$libresoc.v:188894$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389695,10 +393704,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186590$12796_Y + connect \Y $and$libresoc.v:188894$12980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186592$12798 + cell $and $and$libresoc.v:188896$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389706,10 +393715,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186592$12798_Y + connect \Y $and$libresoc.v:188896$12982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:186593$12799 + cell $and $and$libresoc.v:188897$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389717,10 +393726,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:186593$12799_Y + connect \Y $and$libresoc.v:188897$12983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:186594$12800 + cell $and $and$libresoc.v:188898$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389728,10 +393737,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186594$12800_Y + connect \Y $and$libresoc.v:188898$12984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186595$12801 + cell $and $and$libresoc.v:188899$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389739,10 +393748,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186595$12801_Y + connect \Y $and$libresoc.v:188899$12985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186596$12802 + cell $and $and$libresoc.v:188900$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389750,10 +393759,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186596$12802_Y + connect \Y $and$libresoc.v:188900$12986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186598$12804 + cell $and $and$libresoc.v:188902$12988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389761,10 +393770,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186598$12804_Y + connect \Y $and$libresoc.v:188902$12988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186599$12805 + cell $and $and$libresoc.v:188903$12989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389772,10 +393781,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186599$12805_Y + connect \Y $and$libresoc.v:188903$12989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186600$12806 + cell $and $and$libresoc.v:188904$12990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389783,10 +393792,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186600$12806_Y + connect \Y $and$libresoc.v:188904$12990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186601$12807 + cell $and $and$libresoc.v:188905$12991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389794,10 +393803,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186601$12807_Y + connect \Y $and$libresoc.v:188905$12991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:186602$12808 + cell $and $and$libresoc.v:188906$12992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389805,10 +393814,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:186602$12808_Y + connect \Y $and$libresoc.v:188906$12992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:186604$12810 + cell $and $and$libresoc.v:188908$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389816,10 +393825,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:186604$12810_Y + connect \Y $and$libresoc.v:188908$12994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:186606$12812 + cell $and $and$libresoc.v:188910$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389827,10 +393836,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:186606$12812_Y + connect \Y $and$libresoc.v:188910$12996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:186607$12813 + cell $and $and$libresoc.v:188911$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389838,10 +393847,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:186607$12813_Y + connect \Y $and$libresoc.v:188911$12997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:186609$12815 + cell $and $and$libresoc.v:188913$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389849,10 +393858,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:186609$12815_Y + connect \Y $and$libresoc.v:188913$12999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:186612$12818 + cell $and $and$libresoc.v:188916$13002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389860,10 +393869,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:186612$12818_Y + connect \Y $and$libresoc.v:188916$13002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:186617$12823 + cell $and $and$libresoc.v:188921$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389871,10 +393880,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:186617$12823_Y + connect \Y $and$libresoc.v:188921$13007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:186618$12824 + cell $and $and$libresoc.v:188922$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389882,10 +393891,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186618$12824_Y + connect \Y $and$libresoc.v:188922$13008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:186620$12826 + cell $and $and$libresoc.v:188924$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389893,10 +393902,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:186620$12826_Y + connect \Y $and$libresoc.v:188924$13010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186622$12828 + cell $and $and$libresoc.v:188926$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389904,10 +393913,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:186622$12828_Y + connect \Y $and$libresoc.v:188926$13012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186623$12829 + cell $and $and$libresoc.v:188927$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389915,10 +393924,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:186623$12829_Y + connect \Y $and$libresoc.v:188927$13013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186624$12830 + cell $and $and$libresoc.v:188928$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389926,10 +393935,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:186624$12830_Y + connect \Y $and$libresoc.v:188928$13014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:186629$12835 + cell $and $and$libresoc.v:188933$13019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389937,10 +393946,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:186629$12835_Y + connect \Y $and$libresoc.v:188933$13019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:186630$12836 + cell $and $and$libresoc.v:188934$13020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389948,10 +393957,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:186630$12836_Y + connect \Y $and$libresoc.v:188934$13020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:186631$12837 + cell $and $and$libresoc.v:188935$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389959,10 +393968,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186631$12837_Y + connect \Y $and$libresoc.v:188935$13021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186633$12839 + cell $and $and$libresoc.v:188937$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389970,10 +393979,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186633$12839_Y + connect \Y $and$libresoc.v:188937$13023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186634$12840 + cell $and $and$libresoc.v:188938$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389981,10 +393990,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186634$12840_Y + connect \Y $and$libresoc.v:188938$13024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186635$12841 + cell $and $and$libresoc.v:188939$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389992,10 +394001,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186635$12841_Y + connect \Y $and$libresoc.v:188939$13025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186636$12842 + cell $and $and$libresoc.v:188940$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390003,10 +394012,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186636$12842_Y + connect \Y $and$libresoc.v:188940$13026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186637$12843 + cell $and $and$libresoc.v:188941$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390014,10 +394023,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186637$12843_Y + connect \Y $and$libresoc.v:188941$13027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186638$12844 + cell $and $and$libresoc.v:188942$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390025,10 +394034,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186638$12844_Y + connect \Y $and$libresoc.v:188942$13028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:186645$12851 + cell $and $and$libresoc.v:188949$13035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390036,10 +394045,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:186645$12851_Y + connect \Y $and$libresoc.v:188949$13035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:186619$12825 + cell $eq $eq$libresoc.v:188923$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390047,10 +394056,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:186619$12825_Y + connect \Y $eq$libresoc.v:188923$13009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:186621$12827 + cell $eq $eq$libresoc.v:188925$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390058,66 +394067,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:186621$12827_Y + connect \Y $eq$libresoc.v:188925$13011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:186580$12786 + cell $not $not$libresoc.v:188884$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:186580$12786_Y + connect \Y $not$libresoc.v:188884$12970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:186584$12790 + cell $not $not$libresoc.v:188888$12974 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:186584$12790_Y + connect \Y $not$libresoc.v:188888$12974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:186603$12809 + cell $not $not$libresoc.v:188907$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:186603$12809_Y + connect \Y $not$libresoc.v:188907$12993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:186605$12811 + cell $not $not$libresoc.v:188909$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:186605$12811_Y + connect \Y $not$libresoc.v:188909$12995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:186608$12814 + cell $not $not$libresoc.v:188912$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:186608$12814_Y + connect \Y $not$libresoc.v:188912$12998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:186611$12817 + cell $not $not$libresoc.v:188915$13001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:186611$12817_Y + connect \Y $not$libresoc.v:188915$13001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:186616$12822 + cell $not $not$libresoc.v:188920$13006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:186616$12822_Y + connect \Y $not$libresoc.v:188920$13006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:186591$12797 + cell $or $or$libresoc.v:188895$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390125,10 +394134,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:186591$12797_Y + connect \Y $or$libresoc.v:188895$12981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:186615$12821 + cell $or $or$libresoc.v:188919$13005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390136,10 +394145,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:186615$12821_Y + connect \Y $or$libresoc.v:188919$13005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:186625$12831 + cell $or $or$libresoc.v:188929$13015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390147,10 +394156,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:186625$12831_Y + connect \Y $or$libresoc.v:188929$13015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:186626$12832 + cell $or $or$libresoc.v:188930$13016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390158,10 +394167,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:186626$12832_Y + connect \Y $or$libresoc.v:188930$13016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:186627$12833 + cell $or $or$libresoc.v:188931$13017 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390169,10 +394178,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:186627$12833_Y + connect \Y $or$libresoc.v:188931$13017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:186628$12834 + cell $or $or$libresoc.v:188932$13018 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390180,10 +394189,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:186628$12834_Y + connect \Y $or$libresoc.v:188932$13018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:186632$12838 + cell $or $or$libresoc.v:188936$13022 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390191,90 +394200,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:186632$12838_Y + connect \Y $or$libresoc.v:188936$13022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:186597$12803 + cell $reduce_and $reduce_and$libresoc.v:188901$12987 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:186597$12803_Y + connect \Y $reduce_and$libresoc.v:188901$12987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:186610$12816 + cell $reduce_or $reduce_or$libresoc.v:188914$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:186610$12816_Y + connect \Y $reduce_or$libresoc.v:188914$13000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:186613$12819 + cell $reduce_or $reduce_or$libresoc.v:188917$13003 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:186613$12819_Y + connect \Y $reduce_or$libresoc.v:188917$13003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:186614$12820 + cell $reduce_or $reduce_or$libresoc.v:188918$13004 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:186614$12820_Y + connect \Y $reduce_or$libresoc.v:188918$13004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186639$12845 + cell $mux $ternary$libresoc.v:188943$13029 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:186639$12845_Y + connect \Y $ternary$libresoc.v:188943$13029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186640$12846 + cell $mux $ternary$libresoc.v:188944$13030 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:186640$12846_Y + connect \Y $ternary$libresoc.v:188944$13030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186641$12847 + cell $mux $ternary$libresoc.v:188945$13031 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:186641$12847_Y + connect \Y $ternary$libresoc.v:188945$13031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186642$12848 + cell $mux $ternary$libresoc.v:188946$13032 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:186642$12848_Y + connect \Y $ternary$libresoc.v:188946$13032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186643$12849 + cell $mux $ternary$libresoc.v:188947$13033 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:186643$12849_Y + connect \Y $ternary$libresoc.v:188947$13033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186644$12850 + cell $mux $ternary$libresoc.v:188948$13034 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:186644$12850_Y + connect \Y $ternary$libresoc.v:188948$13034_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:186720.14-186726.4" + attribute \src "libresoc.v:189024.14-189030.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390283,7 +394292,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:186727.12-186756.4" + attribute \src "libresoc.v:189031.12-189060.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390315,7 +394324,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:186757.15-186763.4" + attribute \src "libresoc.v:189061.15-189067.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390324,7 +394333,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:186764.14-186770.4" + attribute \src "libresoc.v:189068.14-189074.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390333,7 +394342,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:186771.14-186777.4" + attribute \src "libresoc.v:189075.14-189081.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390342,7 +394351,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:186778.14-186784.4" + attribute \src "libresoc.v:189082.14-189088.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390351,7 +394360,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:186785.14-186790.4" + attribute \src "libresoc.v:189089.14-189094.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390359,7 +394368,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:186791.14-186797.4" + attribute \src "libresoc.v:189095.14-189101.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390367,577 +394376,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:185969.7-185969.20" - process $proc$libresoc.v:185969$13010 + attribute \src "libresoc.v:188273.7-188273.20" + process $proc$libresoc.v:188273$13194 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186105.7-186105.24" - process $proc$libresoc.v:186105$13011 + attribute \src "libresoc.v:188409.7-188409.24" + process $proc$libresoc.v:188409$13195 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:186115.7-186115.26" - process $proc$libresoc.v:186115$13012 + attribute \src "libresoc.v:188419.7-188419.26" + process $proc$libresoc.v:188419$13196 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:186123.7-186123.25" - process $proc$libresoc.v:186123$13013 + attribute \src "libresoc.v:188427.7-188427.25" + process $proc$libresoc.v:188427$13197 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:186168.14-186168.49" - process $proc$libresoc.v:186168$13014 + attribute \src "libresoc.v:188472.14-188472.49" + process $proc$libresoc.v:188472$13198 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:186172.14-186172.43" - process $proc$libresoc.v:186172$13015 + attribute \src "libresoc.v:188476.14-188476.43" + process $proc$libresoc.v:188476$13199 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:186251.13-186251.47" - process $proc$libresoc.v:186251$13016 + attribute \src "libresoc.v:188555.13-188555.47" + process $proc$libresoc.v:188555$13200 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:186255.7-186255.39" - process $proc$libresoc.v:186255$13017 + attribute \src "libresoc.v:188559.7-188559.39" + process $proc$libresoc.v:188559$13201 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:186273.7-186273.27" - process $proc$libresoc.v:186273$13018 + attribute \src "libresoc.v:188577.7-188577.27" + process $proc$libresoc.v:188577$13202 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:186305.14-186305.47" - process $proc$libresoc.v:186305$13019 + attribute \src "libresoc.v:188609.14-188609.47" + process $proc$libresoc.v:188609$13203 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:186309.7-186309.27" - process $proc$libresoc.v:186309$13020 + attribute \src "libresoc.v:188613.7-188613.27" + process $proc$libresoc.v:188613$13204 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:186313.14-186313.50" - process $proc$libresoc.v:186313$13021 + attribute \src "libresoc.v:188617.14-188617.50" + process $proc$libresoc.v:188617$13205 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:186317.7-186317.30" - process $proc$libresoc.v:186317$13022 + attribute \src "libresoc.v:188621.7-188621.30" + process $proc$libresoc.v:188621$13206 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:186321.14-186321.51" - process $proc$libresoc.v:186321$13023 + attribute \src "libresoc.v:188625.14-188625.51" + process $proc$libresoc.v:188625$13207 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:186325.7-186325.31" - process $proc$libresoc.v:186325$13024 + attribute \src "libresoc.v:188629.7-188629.31" + process $proc$libresoc.v:188629$13208 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:186329.7-186329.29" - process $proc$libresoc.v:186329$13025 + attribute \src "libresoc.v:188633.7-188633.29" + process $proc$libresoc.v:188633$13209 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:186333.7-186333.32" - process $proc$libresoc.v:186333$13026 + attribute \src "libresoc.v:188637.7-188637.32" + process $proc$libresoc.v:188637$13210 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:186337.13-186337.35" - process $proc$libresoc.v:186337$13027 + attribute \src "libresoc.v:188641.13-188641.35" + process $proc$libresoc.v:188641$13211 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:186341.7-186341.32" - process $proc$libresoc.v:186341$13028 + attribute \src "libresoc.v:188645.7-188645.32" + process $proc$libresoc.v:188645$13212 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:186345.13-186345.35" - process $proc$libresoc.v:186345$13029 + attribute \src "libresoc.v:188649.13-188649.35" + process $proc$libresoc.v:188649$13213 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:186349.7-186349.32" - process $proc$libresoc.v:186349$13030 + attribute \src "libresoc.v:188653.7-188653.32" + process $proc$libresoc.v:188653$13214 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:186377.7-186377.25" - process $proc$libresoc.v:186377$13031 + attribute \src "libresoc.v:188681.7-188681.25" + process $proc$libresoc.v:188681$13215 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:186381.7-186381.25" - process $proc$libresoc.v:186381$13032 + attribute \src "libresoc.v:188685.7-188685.25" + process $proc$libresoc.v:188685$13216 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:186483.13-186483.31" - process $proc$libresoc.v:186483$13033 + attribute \src "libresoc.v:188787.13-188787.31" + process $proc$libresoc.v:188787$13217 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:186491.13-186491.32" - process $proc$libresoc.v:186491$13034 + attribute \src "libresoc.v:188795.13-188795.32" + process $proc$libresoc.v:188795$13218 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:186495.13-186495.32" - process $proc$libresoc.v:186495$13035 + attribute \src "libresoc.v:188799.13-188799.32" + process $proc$libresoc.v:188799$13219 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:186507.7-186507.26" - process $proc$libresoc.v:186507$13036 + attribute \src "libresoc.v:188811.7-188811.26" + process $proc$libresoc.v:188811$13220 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:186511.7-186511.26" - process $proc$libresoc.v:186511$13037 + attribute \src "libresoc.v:188815.7-188815.26" + process $proc$libresoc.v:188815$13221 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:186515.7-186515.25" - process $proc$libresoc.v:186515$13038 + attribute \src "libresoc.v:188819.7-188819.25" + process $proc$libresoc.v:188819$13222 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:186519.7-186519.25" - process $proc$libresoc.v:186519$13039 + attribute \src "libresoc.v:188823.7-188823.25" + process $proc$libresoc.v:188823$13223 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:186541.13-186541.32" - process $proc$libresoc.v:186541$13040 + attribute \src "libresoc.v:188845.13-188845.32" + process $proc$libresoc.v:188845$13224 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:186545.13-186545.32" - process $proc$libresoc.v:186545$13041 + attribute \src "libresoc.v:188849.13-188849.32" + process $proc$libresoc.v:188849$13225 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:186549.14-186549.43" - process $proc$libresoc.v:186549$13042 + attribute \src "libresoc.v:188853.14-188853.43" + process $proc$libresoc.v:188853$13226 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:186553.14-186553.43" - process $proc$libresoc.v:186553$13043 + attribute \src "libresoc.v:188857.14-188857.43" + process $proc$libresoc.v:188857$13227 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:186557.14-186557.43" - process $proc$libresoc.v:186557$13044 + attribute \src "libresoc.v:188861.14-188861.43" + process $proc$libresoc.v:188861$13228 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:186561.7-186561.20" - process $proc$libresoc.v:186561$13045 + attribute \src "libresoc.v:188865.7-188865.20" + process $proc$libresoc.v:188865$13229 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:186565.13-186565.26" - process $proc$libresoc.v:186565$13046 + attribute \src "libresoc.v:188869.13-188869.26" + process $proc$libresoc.v:188869$13230 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:186569.13-186569.26" - process $proc$libresoc.v:186569$13047 + attribute \src "libresoc.v:188873.13-188873.26" + process $proc$libresoc.v:188873$13231 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:186646.3-186647.39" - process $proc$libresoc.v:186646$12852 + attribute \src "libresoc.v:188950.3-188951.39" + process $proc$libresoc.v:188950$13036 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:186648.3-186649.43" - process $proc$libresoc.v:186648$12853 + attribute \src "libresoc.v:188952.3-188953.43" + process $proc$libresoc.v:188952$13037 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:186650.3-186651.29" - process $proc$libresoc.v:186650$12854 + attribute \src "libresoc.v:188954.3-188955.29" + process $proc$libresoc.v:188954$13038 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:186652.3-186653.29" - process $proc$libresoc.v:186652$12855 + attribute \src "libresoc.v:188956.3-188957.29" + process $proc$libresoc.v:188956$13039 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:186654.3-186655.29" - process $proc$libresoc.v:186654$12856 + attribute \src "libresoc.v:188958.3-188959.29" + process $proc$libresoc.v:188958$13040 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:186656.3-186657.29" - process $proc$libresoc.v:186656$12857 + attribute \src "libresoc.v:188960.3-188961.29" + process $proc$libresoc.v:188960$13041 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:186658.3-186659.29" - process $proc$libresoc.v:186658$12858 + attribute \src "libresoc.v:188962.3-188963.29" + process $proc$libresoc.v:188962$13042 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:186660.3-186661.29" - process $proc$libresoc.v:186660$12859 + attribute \src "libresoc.v:188964.3-188965.29" + process $proc$libresoc.v:188964$13043 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:186662.3-186663.47" - process $proc$libresoc.v:186662$12860 + attribute \src "libresoc.v:188966.3-188967.47" + process $proc$libresoc.v:188966$13044 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:186664.3-186665.53" - process $proc$libresoc.v:186664$12861 + attribute \src "libresoc.v:188968.3-188969.53" + process $proc$libresoc.v:188968$13045 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:186666.3-186667.47" - process $proc$libresoc.v:186666$12862 + attribute \src "libresoc.v:188970.3-188971.47" + process $proc$libresoc.v:188970$13046 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:186668.3-186669.53" - process $proc$libresoc.v:186668$12863 + attribute \src "libresoc.v:188972.3-188973.53" + process $proc$libresoc.v:188972$13047 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:186670.3-186671.47" - process $proc$libresoc.v:186670$12864 + attribute \src "libresoc.v:188974.3-188975.47" + process $proc$libresoc.v:188974$13048 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:186672.3-186673.53" - process $proc$libresoc.v:186672$12865 + attribute \src "libresoc.v:188976.3-188977.53" + process $proc$libresoc.v:188976$13049 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:186674.3-186675.45" - process $proc$libresoc.v:186674$12866 + attribute \src "libresoc.v:188978.3-188979.45" + process $proc$libresoc.v:188978$13050 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:186676.3-186677.51" - process $proc$libresoc.v:186676$12867 + attribute \src "libresoc.v:188980.3-188981.51" + process $proc$libresoc.v:188980$13051 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:186678.3-186679.43" - process $proc$libresoc.v:186678$12868 + attribute \src "libresoc.v:188982.3-188983.43" + process $proc$libresoc.v:188982$13052 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:186680.3-186681.49" - process $proc$libresoc.v:186680$12869 + attribute \src "libresoc.v:188984.3-188985.49" + process $proc$libresoc.v:188984$13053 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:186682.3-186683.37" - process $proc$libresoc.v:186682$12870 + attribute \src "libresoc.v:188986.3-188987.37" + process $proc$libresoc.v:188986$13054 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:186684.3-186685.43" - process $proc$libresoc.v:186684$12871 + attribute \src "libresoc.v:188988.3-188989.43" + process $proc$libresoc.v:188988$13055 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:186686.3-186687.69" - process $proc$libresoc.v:186686$12872 + attribute \src "libresoc.v:188990.3-188991.69" + process $proc$libresoc.v:188990$13056 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:186688.3-186689.65" - process $proc$libresoc.v:186688$12873 + attribute \src "libresoc.v:188992.3-188993.65" + process $proc$libresoc.v:188992$13057 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:186690.3-186691.59" - process $proc$libresoc.v:186690$12874 + attribute \src "libresoc.v:188994.3-188995.59" + process $proc$libresoc.v:188994$13058 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:186692.3-186693.67" - process $proc$libresoc.v:186692$12875 + attribute \src "libresoc.v:188996.3-188997.67" + process $proc$libresoc.v:188996$13059 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:186694.3-186695.39" - process $proc$libresoc.v:186694$12876 + attribute \src "libresoc.v:188998.3-188999.39" + process $proc$libresoc.v:188998$13060 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:186696.3-186697.39" - process $proc$libresoc.v:186696$12877 + attribute \src "libresoc.v:189000.3-189001.39" + process $proc$libresoc.v:189000$13061 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:186698.3-186699.39" - process $proc$libresoc.v:186698$12878 + attribute \src "libresoc.v:189002.3-189003.39" + process $proc$libresoc.v:189002$13062 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:186700.3-186701.39" - process $proc$libresoc.v:186700$12879 + attribute \src "libresoc.v:189004.3-189005.39" + process $proc$libresoc.v:189004$13063 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:186702.3-186703.39" - process $proc$libresoc.v:186702$12880 + attribute \src "libresoc.v:189006.3-189007.39" + process $proc$libresoc.v:189006$13064 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:186704.3-186705.39" - process $proc$libresoc.v:186704$12881 + attribute \src "libresoc.v:189008.3-189009.39" + process $proc$libresoc.v:189008$13065 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:186706.3-186707.39" - process $proc$libresoc.v:186706$12882 + attribute \src "libresoc.v:189010.3-189011.39" + process $proc$libresoc.v:189010$13066 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:186708.3-186709.39" - process $proc$libresoc.v:186708$12883 + attribute \src "libresoc.v:189012.3-189013.39" + process $proc$libresoc.v:189012$13067 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:186710.3-186711.41" - process $proc$libresoc.v:186710$12884 + attribute \src "libresoc.v:189014.3-189015.41" + process $proc$libresoc.v:189014$13068 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:186712.3-186713.41" - process $proc$libresoc.v:186712$12885 + attribute \src "libresoc.v:189016.3-189017.41" + process $proc$libresoc.v:189016$13069 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:186714.3-186715.37" - process $proc$libresoc.v:186714$12886 + attribute \src "libresoc.v:189018.3-189019.37" + process $proc$libresoc.v:189018$13070 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:186716.3-186717.40" - process $proc$libresoc.v:186716$12887 + attribute \src "libresoc.v:189020.3-189021.40" + process $proc$libresoc.v:189020$13071 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:186718.3-186719.25" - process $proc$libresoc.v:186718$12888 + attribute \src "libresoc.v:189022.3-189023.25" + process $proc$libresoc.v:189022$13072 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:186798.3-186807.6" - process $proc$libresoc.v:186798$12889 + attribute \src "libresoc.v:189102.3-189111.6" + process $proc$libresoc.v:189102$13073 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:186799.5-186799.29" + attribute \src "libresoc.v:189103.5-189103.29" switch \initial - attribute \src "libresoc.v:186799.9-186799.17" + attribute \src "libresoc.v:189103.9-189103.17" case 1'1 case end @@ -390953,14 +394962,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:186808.3-186816.6" - process $proc$libresoc.v:186808$12890 + attribute \src "libresoc.v:189112.3-189120.6" + process $proc$libresoc.v:189112$13074 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12891 $1\rok_l_s_rdok$next[0:0]$12892 - attribute \src "libresoc.v:186809.5-186809.29" + assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:189113.5-189113.29" switch \initial - attribute \src "libresoc.v:186809.9-186809.17" + attribute \src "libresoc.v:189113.9-189113.17" case 1'1 case end @@ -390969,21 +394978,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12892 1'0 + assign $1\rok_l_s_rdok$next[0:0]$13076 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12892 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$13076 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12891 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 end - attribute \src "libresoc.v:186817.3-186825.6" - process $proc$libresoc.v:186817$12893 + attribute \src "libresoc.v:189121.3-189129.6" + process $proc$libresoc.v:189121$13077 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12894 $1\rok_l_r_rdok$next[0:0]$12895 - attribute \src "libresoc.v:186818.5-186818.29" + assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:189122.5-189122.29" switch \initial - attribute \src "libresoc.v:186818.9-186818.17" + attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end @@ -390992,21 +395001,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12895 1'1 + assign $1\rok_l_r_rdok$next[0:0]$13079 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12895 \$68 + assign $1\rok_l_r_rdok$next[0:0]$13079 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12894 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 end - attribute \src "libresoc.v:186826.3-186834.6" - process $proc$libresoc.v:186826$12896 + attribute \src "libresoc.v:189130.3-189138.6" + process $proc$libresoc.v:189130$13080 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12897 $1\rst_l_s_rst$next[0:0]$12898 - attribute \src "libresoc.v:186827.5-186827.29" + assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:189131.5-189131.29" switch \initial - attribute \src "libresoc.v:186827.9-186827.17" + attribute \src "libresoc.v:189131.9-189131.17" case 1'1 case end @@ -391015,21 +395024,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12898 1'0 + assign $1\rst_l_s_rst$next[0:0]$13082 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12898 \all_rd + assign $1\rst_l_s_rst$next[0:0]$13082 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12897 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 end - attribute \src "libresoc.v:186835.3-186843.6" - process $proc$libresoc.v:186835$12899 + attribute \src "libresoc.v:189139.3-189147.6" + process $proc$libresoc.v:189139$13083 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12900 $1\rst_l_r_rst$next[0:0]$12901 - attribute \src "libresoc.v:186836.5-186836.29" + assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:189140.5-189140.29" switch \initial - attribute \src "libresoc.v:186836.9-186836.17" + attribute \src "libresoc.v:189140.9-189140.17" case 1'1 case end @@ -391038,21 +395047,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12901 1'1 + assign $1\rst_l_r_rst$next[0:0]$13085 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12901 \rst_r + assign $1\rst_l_r_rst$next[0:0]$13085 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12900 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 end - attribute \src "libresoc.v:186844.3-186852.6" - process $proc$libresoc.v:186844$12902 + attribute \src "libresoc.v:189148.3-189156.6" + process $proc$libresoc.v:189148$13086 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12903 $1\opc_l_s_opc$next[0:0]$12904 - attribute \src "libresoc.v:186845.5-186845.29" + assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:189149.5-189149.29" switch \initial - attribute \src "libresoc.v:186845.9-186845.17" + attribute \src "libresoc.v:189149.9-189149.17" case 1'1 case end @@ -391061,21 +395070,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12904 1'0 + assign $1\opc_l_s_opc$next[0:0]$13088 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12904 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$13088 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12903 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 end - attribute \src "libresoc.v:186853.3-186861.6" - process $proc$libresoc.v:186853$12905 + attribute \src "libresoc.v:189157.3-189165.6" + process $proc$libresoc.v:189157$13089 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12906 $1\opc_l_r_opc$next[0:0]$12907 - attribute \src "libresoc.v:186854.5-186854.29" + assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:189158.5-189158.29" switch \initial - attribute \src "libresoc.v:186854.9-186854.17" + attribute \src "libresoc.v:189158.9-189158.17" case 1'1 case end @@ -391084,21 +395093,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12907 1'1 + assign $1\opc_l_r_opc$next[0:0]$13091 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12907 \req_done + assign $1\opc_l_r_opc$next[0:0]$13091 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12906 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 end - attribute \src "libresoc.v:186862.3-186870.6" - process $proc$libresoc.v:186862$12908 + attribute \src "libresoc.v:189166.3-189174.6" + process $proc$libresoc.v:189166$13092 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12909 $1\src_l_s_src$next[5:0]$12910 - attribute \src "libresoc.v:186863.5-186863.29" + assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 + attribute \src "libresoc.v:189167.5-189167.29" switch \initial - attribute \src "libresoc.v:186863.9-186863.17" + attribute \src "libresoc.v:189167.9-189167.17" case 1'1 case end @@ -391107,21 +395116,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12910 6'000000 + assign $1\src_l_s_src$next[5:0]$13094 6'000000 case - assign $1\src_l_s_src$next[5:0]$12910 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$13094 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12909 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 end - attribute \src "libresoc.v:186871.3-186879.6" - process $proc$libresoc.v:186871$12911 + attribute \src "libresoc.v:189175.3-189183.6" + process $proc$libresoc.v:189175$13095 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12912 $1\src_l_r_src$next[5:0]$12913 - attribute \src "libresoc.v:186872.5-186872.29" + assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:189176.5-189176.29" switch \initial - attribute \src "libresoc.v:186872.9-186872.17" + attribute \src "libresoc.v:189176.9-189176.17" case 1'1 case end @@ -391130,21 +395139,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12913 6'111111 + assign $1\src_l_r_src$next[5:0]$13097 6'111111 case - assign $1\src_l_r_src$next[5:0]$12913 \reset_r + assign $1\src_l_r_src$next[5:0]$13097 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12912 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 end - attribute \src "libresoc.v:186880.3-186888.6" - process $proc$libresoc.v:186880$12914 + attribute \src "libresoc.v:189184.3-189192.6" + process $proc$libresoc.v:189184$13098 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12915 $1\req_l_s_req$next[5:0]$12916 - attribute \src "libresoc.v:186881.5-186881.29" + assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:189185.5-189185.29" switch \initial - attribute \src "libresoc.v:186881.9-186881.17" + attribute \src "libresoc.v:189185.9-189185.17" case 1'1 case end @@ -391153,21 +395162,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12916 6'000000 + assign $1\req_l_s_req$next[5:0]$13100 6'000000 case - assign $1\req_l_s_req$next[5:0]$12916 \$70 + assign $1\req_l_s_req$next[5:0]$13100 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12915 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 end - attribute \src "libresoc.v:186889.3-186897.6" - process $proc$libresoc.v:186889$12917 + attribute \src "libresoc.v:189193.3-189201.6" + process $proc$libresoc.v:189193$13101 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12918 $1\req_l_r_req$next[5:0]$12919 - attribute \src "libresoc.v:186890.5-186890.29" + assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:189194.5-189194.29" switch \initial - attribute \src "libresoc.v:186890.9-186890.17" + attribute \src "libresoc.v:189194.9-189194.17" case 1'1 case end @@ -391176,15 +395185,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12919 6'111111 + assign $1\req_l_r_req$next[5:0]$13103 6'111111 case - assign $1\req_l_r_req$next[5:0]$12919 \$72 + assign $1\req_l_r_req$next[5:0]$13103 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12918 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 end - attribute \src "libresoc.v:186898.3-186910.6" - process $proc$libresoc.v:186898$12920 + attribute \src "libresoc.v:189202.3-189214.6" + process $proc$libresoc.v:189202$13104 assign { } { } assign { } { } assign { } { } @@ -391193,13 +395202,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12922 $1\alu_spr0_spr_op__insn$next[31:0]$12926 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 - attribute \src "libresoc.v:186899.5-186899.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:189203.5-189203.29" switch \initial - attribute \src "libresoc.v:186899.9-186899.17" + attribute \src "libresoc.v:189203.9-189203.17" case 1'1 case end @@ -391211,33 +395220,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 $1\alu_spr0_spr_op__insn$next[31:0]$12926 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 $1\alu_spr0_spr_op__insn$next[31:0]$13110 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12926 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$13110 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12922 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13106 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 end - attribute \src "libresoc.v:186911.3-186932.6" - process $proc$libresoc.v:186911$12929 + attribute \src "libresoc.v:189215.3-189236.6" + process $proc$libresoc.v:189215$13113 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12930 $2\data_r0__o$next[63:0]$12934 + assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12931 $3\data_r0__o_ok$next[0:0]$12936 - attribute \src "libresoc.v:186912.5-186912.29" + assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 + attribute \src "libresoc.v:189216.5-189216.29" switch \initial - attribute \src "libresoc.v:186912.9-186912.17" + attribute \src "libresoc.v:189216.9-189216.17" case 1'1 case end @@ -391247,10 +395256,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12933 $1\data_r0__o$next[63:0]$12932 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$13117 $1\data_r0__o$next[63:0]$13116 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12932 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12933 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$13116 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13117 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391258,38 +395267,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12935 $2\data_r0__o$next[63:0]$12934 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$13119 $2\data_r0__o$next[63:0]$13118 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12934 $1\data_r0__o$next[63:0]$12932 - assign $2\data_r0__o_ok$next[0:0]$12935 $1\data_r0__o_ok$next[0:0]$12933 + assign $2\data_r0__o$next[63:0]$13118 $1\data_r0__o$next[63:0]$13116 + assign $2\data_r0__o_ok$next[0:0]$13119 $1\data_r0__o_ok$next[0:0]$13117 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12936 1'0 + assign $3\data_r0__o_ok$next[0:0]$13120 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12936 $2\data_r0__o_ok$next[0:0]$12935 + assign $3\data_r0__o_ok$next[0:0]$13120 $2\data_r0__o_ok$next[0:0]$13119 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12930 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12931 + update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 end - attribute \src "libresoc.v:186933.3-186954.6" - process $proc$libresoc.v:186933$12937 + attribute \src "libresoc.v:189237.3-189258.6" + process $proc$libresoc.v:189237$13121 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12938 $2\data_r1__spr1$next[63:0]$12942 + assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12939 $3\data_r1__spr1_ok$next[0:0]$12944 - attribute \src "libresoc.v:186934.5-186934.29" + assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 + attribute \src "libresoc.v:189238.5-189238.29" switch \initial - attribute \src "libresoc.v:186934.9-186934.17" + attribute \src "libresoc.v:189238.9-189238.17" case 1'1 case end @@ -391299,10 +395308,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12941 $1\data_r1__spr1$next[63:0]$12940 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$13125 $1\data_r1__spr1$next[63:0]$13124 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12940 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12941 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$13124 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$13125 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391310,38 +395319,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12943 $2\data_r1__spr1$next[63:0]$12942 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$13127 $2\data_r1__spr1$next[63:0]$13126 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12942 $1\data_r1__spr1$next[63:0]$12940 - assign $2\data_r1__spr1_ok$next[0:0]$12943 $1\data_r1__spr1_ok$next[0:0]$12941 + assign $2\data_r1__spr1$next[63:0]$13126 $1\data_r1__spr1$next[63:0]$13124 + assign $2\data_r1__spr1_ok$next[0:0]$13127 $1\data_r1__spr1_ok$next[0:0]$13125 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12944 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$13128 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12944 $2\data_r1__spr1_ok$next[0:0]$12943 + assign $3\data_r1__spr1_ok$next[0:0]$13128 $2\data_r1__spr1_ok$next[0:0]$13127 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12938 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12939 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 end - attribute \src "libresoc.v:186955.3-186976.6" - process $proc$libresoc.v:186955$12945 + attribute \src "libresoc.v:189259.3-189280.6" + process $proc$libresoc.v:189259$13129 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12946 $2\data_r2__fast1$next[63:0]$12950 + assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12947 $3\data_r2__fast1_ok$next[0:0]$12952 - attribute \src "libresoc.v:186956.5-186956.29" + assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 + attribute \src "libresoc.v:189260.5-189260.29" switch \initial - attribute \src "libresoc.v:186956.9-186956.17" + attribute \src "libresoc.v:189260.9-189260.17" case 1'1 case end @@ -391351,10 +395360,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12949 $1\data_r2__fast1$next[63:0]$12948 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$13133 $1\data_r2__fast1$next[63:0]$13132 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12948 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12949 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$13132 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$13133 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391362,38 +395371,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12951 $2\data_r2__fast1$next[63:0]$12950 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$13135 $2\data_r2__fast1$next[63:0]$13134 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12950 $1\data_r2__fast1$next[63:0]$12948 - assign $2\data_r2__fast1_ok$next[0:0]$12951 $1\data_r2__fast1_ok$next[0:0]$12949 + assign $2\data_r2__fast1$next[63:0]$13134 $1\data_r2__fast1$next[63:0]$13132 + assign $2\data_r2__fast1_ok$next[0:0]$13135 $1\data_r2__fast1_ok$next[0:0]$13133 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12952 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$13136 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12952 $2\data_r2__fast1_ok$next[0:0]$12951 + assign $3\data_r2__fast1_ok$next[0:0]$13136 $2\data_r2__fast1_ok$next[0:0]$13135 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12946 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12947 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 end - attribute \src "libresoc.v:186977.3-186998.6" - process $proc$libresoc.v:186977$12953 + attribute \src "libresoc.v:189281.3-189302.6" + process $proc$libresoc.v:189281$13137 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12954 $2\data_r3__xer_so$next[0:0]$12958 + assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12955 $3\data_r3__xer_so_ok$next[0:0]$12960 - attribute \src "libresoc.v:186978.5-186978.29" + assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 + attribute \src "libresoc.v:189282.5-189282.29" switch \initial - attribute \src "libresoc.v:186978.9-186978.17" + attribute \src "libresoc.v:189282.9-189282.17" case 1'1 case end @@ -391403,10 +395412,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12957 $1\data_r3__xer_so$next[0:0]$12956 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$13141 $1\data_r3__xer_so$next[0:0]$13140 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12956 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12957 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$13140 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$13141 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391414,38 +395423,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12959 $2\data_r3__xer_so$next[0:0]$12958 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$13143 $2\data_r3__xer_so$next[0:0]$13142 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12958 $1\data_r3__xer_so$next[0:0]$12956 - assign $2\data_r3__xer_so_ok$next[0:0]$12959 $1\data_r3__xer_so_ok$next[0:0]$12957 + assign $2\data_r3__xer_so$next[0:0]$13142 $1\data_r3__xer_so$next[0:0]$13140 + assign $2\data_r3__xer_so_ok$next[0:0]$13143 $1\data_r3__xer_so_ok$next[0:0]$13141 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12960 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$13144 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12960 $2\data_r3__xer_so_ok$next[0:0]$12959 + assign $3\data_r3__xer_so_ok$next[0:0]$13144 $2\data_r3__xer_so_ok$next[0:0]$13143 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12954 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12955 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 end - attribute \src "libresoc.v:186999.3-187020.6" - process $proc$libresoc.v:186999$12961 + attribute \src "libresoc.v:189303.3-189324.6" + process $proc$libresoc.v:189303$13145 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12962 $2\data_r4__xer_ov$next[1:0]$12966 + assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12963 $3\data_r4__xer_ov_ok$next[0:0]$12968 - attribute \src "libresoc.v:187000.5-187000.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 + attribute \src "libresoc.v:189304.5-189304.29" switch \initial - attribute \src "libresoc.v:187000.9-187000.17" + attribute \src "libresoc.v:189304.9-189304.17" case 1'1 case end @@ -391455,10 +395464,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12965 $1\data_r4__xer_ov$next[1:0]$12964 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13149 $1\data_r4__xer_ov$next[1:0]$13148 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12964 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12965 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$13148 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13149 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391466,38 +395475,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12967 $2\data_r4__xer_ov$next[1:0]$12966 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$13151 $2\data_r4__xer_ov$next[1:0]$13150 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12966 $1\data_r4__xer_ov$next[1:0]$12964 - assign $2\data_r4__xer_ov_ok$next[0:0]$12967 $1\data_r4__xer_ov_ok$next[0:0]$12965 + assign $2\data_r4__xer_ov$next[1:0]$13150 $1\data_r4__xer_ov$next[1:0]$13148 + assign $2\data_r4__xer_ov_ok$next[0:0]$13151 $1\data_r4__xer_ov_ok$next[0:0]$13149 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12968 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12968 $2\data_r4__xer_ov_ok$next[0:0]$12967 + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 $2\data_r4__xer_ov_ok$next[0:0]$13151 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12962 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12963 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 end - attribute \src "libresoc.v:187021.3-187042.6" - process $proc$libresoc.v:187021$12969 + attribute \src "libresoc.v:189325.3-189346.6" + process $proc$libresoc.v:189325$13153 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12970 $2\data_r5__xer_ca$next[1:0]$12974 + assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12971 $3\data_r5__xer_ca_ok$next[0:0]$12976 - attribute \src "libresoc.v:187022.5-187022.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 + attribute \src "libresoc.v:189326.5-189326.29" switch \initial - attribute \src "libresoc.v:187022.9-187022.17" + attribute \src "libresoc.v:189326.9-189326.17" case 1'1 case end @@ -391507,10 +395516,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12973 $1\data_r5__xer_ca$next[1:0]$12972 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13157 $1\data_r5__xer_ca$next[1:0]$13156 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12972 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12973 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$13156 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13157 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391518,32 +395527,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12975 $2\data_r5__xer_ca$next[1:0]$12974 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$13159 $2\data_r5__xer_ca$next[1:0]$13158 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12974 $1\data_r5__xer_ca$next[1:0]$12972 - assign $2\data_r5__xer_ca_ok$next[0:0]$12975 $1\data_r5__xer_ca_ok$next[0:0]$12973 + assign $2\data_r5__xer_ca$next[1:0]$13158 $1\data_r5__xer_ca$next[1:0]$13156 + assign $2\data_r5__xer_ca_ok$next[0:0]$13159 $1\data_r5__xer_ca_ok$next[0:0]$13157 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12976 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12976 $2\data_r5__xer_ca_ok$next[0:0]$12975 + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 $2\data_r5__xer_ca_ok$next[0:0]$13159 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12970 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12971 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 end - attribute \src "libresoc.v:187043.3-187052.6" - process $proc$libresoc.v:187043$12977 + attribute \src "libresoc.v:189347.3-189356.6" + process $proc$libresoc.v:189347$13161 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12978 $1\src_r0$next[63:0]$12979 - attribute \src "libresoc.v:187044.5-187044.29" + assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 + attribute \src "libresoc.v:189348.5-189348.29" switch \initial - attribute \src "libresoc.v:187044.9-187044.17" + attribute \src "libresoc.v:189348.9-189348.17" case 1'1 case end @@ -391552,21 +395561,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12979 \src1_i + assign $1\src_r0$next[63:0]$13163 \src1_i case - assign $1\src_r0$next[63:0]$12979 \src_r0 + assign $1\src_r0$next[63:0]$13163 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12978 + update \src_r0$next $0\src_r0$next[63:0]$13162 end - attribute \src "libresoc.v:187053.3-187062.6" - process $proc$libresoc.v:187053$12980 + attribute \src "libresoc.v:189357.3-189366.6" + process $proc$libresoc.v:189357$13164 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12981 $1\src_r1$next[63:0]$12982 - attribute \src "libresoc.v:187054.5-187054.29" + assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 + attribute \src "libresoc.v:189358.5-189358.29" switch \initial - attribute \src "libresoc.v:187054.9-187054.17" + attribute \src "libresoc.v:189358.9-189358.17" case 1'1 case end @@ -391575,21 +395584,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12982 \src2_i + assign $1\src_r1$next[63:0]$13166 \src2_i case - assign $1\src_r1$next[63:0]$12982 \src_r1 + assign $1\src_r1$next[63:0]$13166 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12981 + update \src_r1$next $0\src_r1$next[63:0]$13165 end - attribute \src "libresoc.v:187063.3-187072.6" - process $proc$libresoc.v:187063$12983 + attribute \src "libresoc.v:189367.3-189376.6" + process $proc$libresoc.v:189367$13167 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12984 $1\src_r2$next[63:0]$12985 - attribute \src "libresoc.v:187064.5-187064.29" + assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 + attribute \src "libresoc.v:189368.5-189368.29" switch \initial - attribute \src "libresoc.v:187064.9-187064.17" + attribute \src "libresoc.v:189368.9-189368.17" case 1'1 case end @@ -391598,21 +395607,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12985 \src3_i + assign $1\src_r2$next[63:0]$13169 \src3_i case - assign $1\src_r2$next[63:0]$12985 \src_r2 + assign $1\src_r2$next[63:0]$13169 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12984 + update \src_r2$next $0\src_r2$next[63:0]$13168 end - attribute \src "libresoc.v:187073.3-187082.6" - process $proc$libresoc.v:187073$12986 + attribute \src "libresoc.v:189377.3-189386.6" + process $proc$libresoc.v:189377$13170 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12987 $1\src_r3$next[0:0]$12988 - attribute \src "libresoc.v:187074.5-187074.29" + assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 + attribute \src "libresoc.v:189378.5-189378.29" switch \initial - attribute \src "libresoc.v:187074.9-187074.17" + attribute \src "libresoc.v:189378.9-189378.17" case 1'1 case end @@ -391621,21 +395630,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12988 \src4_i + assign $1\src_r3$next[0:0]$13172 \src4_i case - assign $1\src_r3$next[0:0]$12988 \src_r3 + assign $1\src_r3$next[0:0]$13172 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12987 + update \src_r3$next $0\src_r3$next[0:0]$13171 end - attribute \src "libresoc.v:187083.3-187092.6" - process $proc$libresoc.v:187083$12989 + attribute \src "libresoc.v:189387.3-189396.6" + process $proc$libresoc.v:189387$13173 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12990 $1\src_r4$next[1:0]$12991 - attribute \src "libresoc.v:187084.5-187084.29" + assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 + attribute \src "libresoc.v:189388.5-189388.29" switch \initial - attribute \src "libresoc.v:187084.9-187084.17" + attribute \src "libresoc.v:189388.9-189388.17" case 1'1 case end @@ -391644,21 +395653,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12991 \src5_i + assign $1\src_r4$next[1:0]$13175 \src5_i case - assign $1\src_r4$next[1:0]$12991 \src_r4 + assign $1\src_r4$next[1:0]$13175 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12990 + update \src_r4$next $0\src_r4$next[1:0]$13174 end - attribute \src "libresoc.v:187093.3-187102.6" - process $proc$libresoc.v:187093$12992 + attribute \src "libresoc.v:189397.3-189406.6" + process $proc$libresoc.v:189397$13176 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12993 $1\src_r5$next[1:0]$12994 - attribute \src "libresoc.v:187094.5-187094.29" + assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 + attribute \src "libresoc.v:189398.5-189398.29" switch \initial - attribute \src "libresoc.v:187094.9-187094.17" + attribute \src "libresoc.v:189398.9-189398.17" case 1'1 case end @@ -391667,21 +395676,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12994 \src6_i + assign $1\src_r5$next[1:0]$13178 \src6_i case - assign $1\src_r5$next[1:0]$12994 \src_r5 + assign $1\src_r5$next[1:0]$13178 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12993 + update \src_r5$next $0\src_r5$next[1:0]$13177 end - attribute \src "libresoc.v:187103.3-187111.6" - process $proc$libresoc.v:187103$12995 + attribute \src "libresoc.v:189407.3-189415.6" + process $proc$libresoc.v:189407$13179 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12996 $1\alui_l_r_alui$next[0:0]$12997 - attribute \src "libresoc.v:187104.5-187104.29" + assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:189408.5-189408.29" switch \initial - attribute \src "libresoc.v:187104.9-187104.17" + attribute \src "libresoc.v:189408.9-189408.17" case 1'1 case end @@ -391690,21 +395699,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12997 1'1 + assign $1\alui_l_r_alui$next[0:0]$13181 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12997 \$98 + assign $1\alui_l_r_alui$next[0:0]$13181 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12996 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 end - attribute \src "libresoc.v:187112.3-187120.6" - process $proc$libresoc.v:187112$12998 + attribute \src "libresoc.v:189416.3-189424.6" + process $proc$libresoc.v:189416$13182 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12999 $1\alu_l_r_alu$next[0:0]$13000 - attribute \src "libresoc.v:187113.5-187113.29" + assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:189417.5-189417.29" switch \initial - attribute \src "libresoc.v:187113.9-187113.17" + attribute \src "libresoc.v:189417.9-189417.17" case 1'1 case end @@ -391713,21 +395722,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13000 1'1 + assign $1\alu_l_r_alu$next[0:0]$13184 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13000 \$100 + assign $1\alu_l_r_alu$next[0:0]$13184 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12999 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 end - attribute \src "libresoc.v:187121.3-187130.6" - process $proc$libresoc.v:187121$13001 + attribute \src "libresoc.v:189425.3-189434.6" + process $proc$libresoc.v:189425$13185 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:187122.5-187122.29" + attribute \src "libresoc.v:189426.5-189426.29" switch \initial - attribute \src "libresoc.v:187122.9-187122.17" + attribute \src "libresoc.v:189426.9-189426.17" case 1'1 case end @@ -391743,14 +395752,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:187131.3-187140.6" - process $proc$libresoc.v:187131$13002 + attribute \src "libresoc.v:189435.3-189444.6" + process $proc$libresoc.v:189435$13186 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:187132.5-187132.29" + attribute \src "libresoc.v:189436.5-189436.29" switch \initial - attribute \src "libresoc.v:187132.9-187132.17" + attribute \src "libresoc.v:189436.9-189436.17" case 1'1 case end @@ -391766,14 +395775,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:187141.3-187150.6" - process $proc$libresoc.v:187141$13003 + attribute \src "libresoc.v:189445.3-189454.6" + process $proc$libresoc.v:189445$13187 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:187142.5-187142.29" + attribute \src "libresoc.v:189446.5-189446.29" switch \initial - attribute \src "libresoc.v:187142.9-187142.17" + attribute \src "libresoc.v:189446.9-189446.17" case 1'1 case end @@ -391789,14 +395798,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:187151.3-187160.6" - process $proc$libresoc.v:187151$13004 + attribute \src "libresoc.v:189455.3-189464.6" + process $proc$libresoc.v:189455$13188 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:187152.5-187152.29" + attribute \src "libresoc.v:189456.5-189456.29" switch \initial - attribute \src "libresoc.v:187152.9-187152.17" + attribute \src "libresoc.v:189456.9-189456.17" case 1'1 case end @@ -391812,14 +395821,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:187161.3-187170.6" - process $proc$libresoc.v:187161$13005 + attribute \src "libresoc.v:189465.3-189474.6" + process $proc$libresoc.v:189465$13189 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:187162.5-187162.29" + attribute \src "libresoc.v:189466.5-189466.29" switch \initial - attribute \src "libresoc.v:187162.9-187162.17" + attribute \src "libresoc.v:189466.9-189466.17" case 1'1 case end @@ -391835,14 +395844,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:187171.3-187180.6" - process $proc$libresoc.v:187171$13006 + attribute \src "libresoc.v:189475.3-189484.6" + process $proc$libresoc.v:189475$13190 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:187172.5-187172.29" + attribute \src "libresoc.v:189476.5-189476.29" switch \initial - attribute \src "libresoc.v:187172.9-187172.17" + attribute \src "libresoc.v:189476.9-189476.17" case 1'1 case end @@ -391858,14 +395867,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:187181.3-187189.6" - process $proc$libresoc.v:187181$13007 + attribute \src "libresoc.v:189485.3-189493.6" + process $proc$libresoc.v:189485$13191 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$13008 $1\prev_wr_go$next[5:0]$13009 - attribute \src "libresoc.v:187182.5-187182.29" + assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:189486.5-189486.29" switch \initial - attribute \src "libresoc.v:187182.9-187182.17" + attribute \src "libresoc.v:189486.9-189486.17" case 1'1 case end @@ -391874,79 +395883,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$13009 6'000000 - case - assign $1\prev_wr_go$next[5:0]$13009 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13008 - end - connect \$9 $not$libresoc.v:186580$12786_Y - connect \$100 $and$libresoc.v:186581$12787_Y - connect \$102 $and$libresoc.v:186582$12788_Y - connect \$104 $and$libresoc.v:186583$12789_Y - connect \$106 $not$libresoc.v:186584$12790_Y - connect \$108 $and$libresoc.v:186585$12791_Y - connect \$110 $and$libresoc.v:186586$12792_Y - connect \$112 $and$libresoc.v:186587$12793_Y - connect \$114 $and$libresoc.v:186588$12794_Y - connect \$116 $and$libresoc.v:186589$12795_Y - connect \$118 $and$libresoc.v:186590$12796_Y - connect \$11 $or$libresoc.v:186591$12797_Y - connect \$120 $and$libresoc.v:186592$12798_Y - connect \$122 $and$libresoc.v:186593$12799_Y - connect \$124 $and$libresoc.v:186594$12800_Y - connect \$126 $and$libresoc.v:186595$12801_Y - connect \$128 $and$libresoc.v:186596$12802_Y - connect \$8 $reduce_and$libresoc.v:186597$12803_Y - connect \$130 $and$libresoc.v:186598$12804_Y - connect \$132 $and$libresoc.v:186599$12805_Y - connect \$134 $and$libresoc.v:186600$12806_Y - connect \$136 $and$libresoc.v:186601$12807_Y - connect \$14 $and$libresoc.v:186602$12808_Y - connect \$16 $not$libresoc.v:186603$12809_Y - connect \$18 $and$libresoc.v:186604$12810_Y - connect \$20 $not$libresoc.v:186605$12811_Y - connect \$22 $and$libresoc.v:186606$12812_Y - connect \$24 $and$libresoc.v:186607$12813_Y - connect \$28 $not$libresoc.v:186608$12814_Y - connect \$30 $and$libresoc.v:186609$12815_Y - connect \$27 $reduce_or$libresoc.v:186610$12816_Y - connect \$26 $not$libresoc.v:186611$12817_Y - connect \$34 $and$libresoc.v:186612$12818_Y - connect \$36 $reduce_or$libresoc.v:186613$12819_Y - connect \$38 $reduce_or$libresoc.v:186614$12820_Y - connect \$40 $or$libresoc.v:186615$12821_Y - connect \$42 $not$libresoc.v:186616$12822_Y - connect \$44 $and$libresoc.v:186617$12823_Y - connect \$46 $and$libresoc.v:186618$12824_Y - connect \$48 $eq$libresoc.v:186619$12825_Y - connect \$50 $and$libresoc.v:186620$12826_Y - connect \$52 $eq$libresoc.v:186621$12827_Y - connect \$54 $and$libresoc.v:186622$12828_Y - connect \$56 $and$libresoc.v:186623$12829_Y - connect \$58 $and$libresoc.v:186624$12830_Y - connect \$60 $or$libresoc.v:186625$12831_Y - connect \$62 $or$libresoc.v:186626$12832_Y - connect \$64 $or$libresoc.v:186627$12833_Y - connect \$66 $or$libresoc.v:186628$12834_Y - connect \$68 $and$libresoc.v:186629$12835_Y - connect \$6 $and$libresoc.v:186630$12836_Y - connect \$70 $and$libresoc.v:186631$12837_Y - connect \$72 $or$libresoc.v:186632$12838_Y - connect \$74 $and$libresoc.v:186633$12839_Y - connect \$76 $and$libresoc.v:186634$12840_Y - connect \$78 $and$libresoc.v:186635$12841_Y - connect \$80 $and$libresoc.v:186636$12842_Y - connect \$82 $and$libresoc.v:186637$12843_Y - connect \$84 $and$libresoc.v:186638$12844_Y - connect \$86 $ternary$libresoc.v:186639$12845_Y - connect \$88 $ternary$libresoc.v:186640$12846_Y - connect \$90 $ternary$libresoc.v:186641$12847_Y - connect \$92 $ternary$libresoc.v:186642$12848_Y - connect \$94 $ternary$libresoc.v:186643$12849_Y - connect \$96 $ternary$libresoc.v:186644$12850_Y - connect \$98 $and$libresoc.v:186645$12851_Y + assign $1\prev_wr_go$next[5:0]$13193 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13193 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 + end + connect \$9 $not$libresoc.v:188884$12970_Y + connect \$100 $and$libresoc.v:188885$12971_Y + connect \$102 $and$libresoc.v:188886$12972_Y + connect \$104 $and$libresoc.v:188887$12973_Y + connect \$106 $not$libresoc.v:188888$12974_Y + connect \$108 $and$libresoc.v:188889$12975_Y + connect \$110 $and$libresoc.v:188890$12976_Y + connect \$112 $and$libresoc.v:188891$12977_Y + connect \$114 $and$libresoc.v:188892$12978_Y + connect \$116 $and$libresoc.v:188893$12979_Y + connect \$118 $and$libresoc.v:188894$12980_Y + connect \$11 $or$libresoc.v:188895$12981_Y + connect \$120 $and$libresoc.v:188896$12982_Y + connect \$122 $and$libresoc.v:188897$12983_Y + connect \$124 $and$libresoc.v:188898$12984_Y + connect \$126 $and$libresoc.v:188899$12985_Y + connect \$128 $and$libresoc.v:188900$12986_Y + connect \$8 $reduce_and$libresoc.v:188901$12987_Y + connect \$130 $and$libresoc.v:188902$12988_Y + connect \$132 $and$libresoc.v:188903$12989_Y + connect \$134 $and$libresoc.v:188904$12990_Y + connect \$136 $and$libresoc.v:188905$12991_Y + connect \$14 $and$libresoc.v:188906$12992_Y + connect \$16 $not$libresoc.v:188907$12993_Y + connect \$18 $and$libresoc.v:188908$12994_Y + connect \$20 $not$libresoc.v:188909$12995_Y + connect \$22 $and$libresoc.v:188910$12996_Y + connect \$24 $and$libresoc.v:188911$12997_Y + connect \$28 $not$libresoc.v:188912$12998_Y + connect \$30 $and$libresoc.v:188913$12999_Y + connect \$27 $reduce_or$libresoc.v:188914$13000_Y + connect \$26 $not$libresoc.v:188915$13001_Y + connect \$34 $and$libresoc.v:188916$13002_Y + connect \$36 $reduce_or$libresoc.v:188917$13003_Y + connect \$38 $reduce_or$libresoc.v:188918$13004_Y + connect \$40 $or$libresoc.v:188919$13005_Y + connect \$42 $not$libresoc.v:188920$13006_Y + connect \$44 $and$libresoc.v:188921$13007_Y + connect \$46 $and$libresoc.v:188922$13008_Y + connect \$48 $eq$libresoc.v:188923$13009_Y + connect \$50 $and$libresoc.v:188924$13010_Y + connect \$52 $eq$libresoc.v:188925$13011_Y + connect \$54 $and$libresoc.v:188926$13012_Y + connect \$56 $and$libresoc.v:188927$13013_Y + connect \$58 $and$libresoc.v:188928$13014_Y + connect \$60 $or$libresoc.v:188929$13015_Y + connect \$62 $or$libresoc.v:188930$13016_Y + connect \$64 $or$libresoc.v:188931$13017_Y + connect \$66 $or$libresoc.v:188932$13018_Y + connect \$68 $and$libresoc.v:188933$13019_Y + connect \$6 $and$libresoc.v:188934$13020_Y + connect \$70 $and$libresoc.v:188935$13021_Y + connect \$72 $or$libresoc.v:188936$13022_Y + connect \$74 $and$libresoc.v:188937$13023_Y + connect \$76 $and$libresoc.v:188938$13024_Y + connect \$78 $and$libresoc.v:188939$13025_Y + connect \$80 $and$libresoc.v:188940$13026_Y + connect \$82 $and$libresoc.v:188941$13027_Y + connect \$84 $and$libresoc.v:188942$13028_Y + connect \$86 $ternary$libresoc.v:188943$13029_Y + connect \$88 $ternary$libresoc.v:188944$13030_Y + connect \$90 $ternary$libresoc.v:188945$13031_Y + connect \$92 $ternary$libresoc.v:188946$13032_Y + connect \$94 $ternary$libresoc.v:188947$13033_Y + connect \$96 $ternary$libresoc.v:188948$13034_Y + connect \$98 $and$libresoc.v:188949$13035_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -391979,111 +395988,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:187225.1-187745.10" +attribute \src "libresoc.v:189529.1-190049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $0\fast1$7[63:0]$13056 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $0\fast1$7[63:0]$13240 + attribute \src "libresoc.v:189879.3-189894.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:187226.7-187226.20" + attribute \src "libresoc.v:189530.7-189530.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $0\spr1$6[63:0]$13081 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $0\spr1$6[63:0]$13265 + attribute \src "libresoc.v:189818.3-189836.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $0\xer_ca$10[1:0]$13075 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $0\xer_ca$10[1:0]$13259 + attribute \src "libresoc.v:190006.3-190026.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $0\xer_ov$9[1:0]$13069 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $0\xer_ov$9[1:0]$13253 + attribute \src "libresoc.v:189961.3-189981.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $0\xer_so$8[0:0]$13063 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $0\xer_so$8[0:0]$13247 + attribute \src "libresoc.v:189916.3-189936.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $1\fast1$7[63:0]$13057 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189879.3-189894.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $1\spr1$6[63:0]$13082 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:189818.3-189836.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $1\xer_ca$10[1:0]$13076 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:190006.3-190026.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $1\xer_ov$9[1:0]$13070 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189961.3-189981.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $1\xer_so$8[0:0]$13064 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $1\xer_so$8[0:0]$13248 + attribute \src "libresoc.v:189916.3-189936.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $2\fast1$7[63:0]$13058 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $2\fast1$7[63:0]$13242 + attribute \src "libresoc.v:189879.3-189894.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $2\spr1$6[63:0]$13083 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $2\spr1$6[63:0]$13267 + attribute \src "libresoc.v:189818.3-189836.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $2\xer_ca$10[1:0]$13077 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $2\xer_ca$10[1:0]$13261 + attribute \src "libresoc.v:190006.3-190026.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $2\xer_ov$9[1:0]$13071 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $2\xer_ov$9[1:0]$13255 + attribute \src "libresoc.v:189961.3-189981.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $2\xer_so$8[0:0]$13065 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $2\xer_so$8[0:0]$13249 + attribute \src "libresoc.v:189916.3-189936.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $3\xer_ca$10[1:0]$13078 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $3\xer_ca$10[1:0]$13262 + attribute \src "libresoc.v:190006.3-190026.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $3\xer_ov$9[1:0]$13072 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $3\xer_ov$9[1:0]$13256 + attribute \src "libresoc.v:189961.3-189981.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $3\xer_so$8[0:0]$13066 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $3\xer_so$8[0:0]$13250 + attribute \src "libresoc.v:189916.3-189936.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:187491.18-187491.106" - wire $eq$libresoc.v:187491$13048_Y - attribute \src "libresoc.v:187492.18-187492.106" - wire $eq$libresoc.v:187492$13049_Y - attribute \src "libresoc.v:187493.18-187493.106" - wire $eq$libresoc.v:187493$13050_Y - attribute \src "libresoc.v:187494.18-187494.106" - wire $eq$libresoc.v:187494$13051_Y - attribute \src "libresoc.v:187495.18-187495.106" - wire $eq$libresoc.v:187495$13052_Y - attribute \src "libresoc.v:187496.18-187496.106" - wire $eq$libresoc.v:187496$13053_Y - attribute \src "libresoc.v:187497.18-187497.106" - wire $eq$libresoc.v:187497$13054_Y + attribute \src "libresoc.v:189795.18-189795.106" + wire $eq$libresoc.v:189795$13232_Y + attribute \src "libresoc.v:189796.18-189796.106" + wire $eq$libresoc.v:189796$13233_Y + attribute \src "libresoc.v:189797.18-189797.106" + wire $eq$libresoc.v:189797$13234_Y + attribute \src "libresoc.v:189798.18-189798.106" + wire $eq$libresoc.v:189798$13235_Y + attribute \src "libresoc.v:189799.18-189799.106" + wire $eq$libresoc.v:189799$13236_Y + attribute \src "libresoc.v:189800.18-189800.106" + wire $eq$libresoc.v:189800$13237_Y + attribute \src "libresoc.v:189801.18-189801.106" + wire $eq$libresoc.v:189801$13238_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -392104,7 +396113,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:187226.7-187226.15" + attribute \src "libresoc.v:189530.7-189530.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -392339,7 +396348,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187491$13048 + cell $eq $eq$libresoc.v:189795$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392347,10 +396356,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187491$13048_Y + connect \Y $eq$libresoc.v:189795$13232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187492$13049 + cell $eq $eq$libresoc.v:189796$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392358,10 +396367,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187492$13049_Y + connect \Y $eq$libresoc.v:189796$13233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187493$13050 + cell $eq $eq$libresoc.v:189797$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392369,10 +396378,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187493$13050_Y + connect \Y $eq$libresoc.v:189797$13234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187494$13051 + cell $eq $eq$libresoc.v:189798$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392380,10 +396389,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187494$13051_Y + connect \Y $eq$libresoc.v:189798$13235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187495$13052 + cell $eq $eq$libresoc.v:189799$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392391,10 +396400,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187495$13052_Y + connect \Y $eq$libresoc.v:189799$13236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187496$13053 + cell $eq $eq$libresoc.v:189800$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392402,10 +396411,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187496$13053_Y + connect \Y $eq$libresoc.v:189800$13237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:187497$13054 + cell $eq $eq$libresoc.v:189801$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392413,24 +396422,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187497$13054_Y + connect \Y $eq$libresoc.v:189801$13238_Y end - attribute \src "libresoc.v:187226.7-187226.20" - process $proc$libresoc.v:187226$13084 + attribute \src "libresoc.v:189530.7-189530.20" + process $proc$libresoc.v:189530$13268 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187498.3-187513.6" - process $proc$libresoc.v:187498$13055 + attribute \src "libresoc.v:189802.3-189817.6" + process $proc$libresoc.v:189802$13239 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13056 $1\fast1$7[63:0]$13057 - attribute \src "libresoc.v:187499.5-187499.29" + assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189803.5-189803.29" switch \initial - attribute \src "libresoc.v:187499.9-187499.17" + attribute \src "libresoc.v:189803.9-189803.17" case 1'1 case end @@ -392439,30 +396448,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13057 $2\fast1$7[63:0]$13058 + assign $1\fast1$7[63:0]$13241 $2\fast1$7[63:0]$13242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13058 \ra + assign $2\fast1$7[63:0]$13242 \ra case - assign $2\fast1$7[63:0]$13058 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13242 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13241 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13056 + update \fast1$7 $0\fast1$7[63:0]$13240 end - attribute \src "libresoc.v:187514.3-187532.6" - process $proc$libresoc.v:187514$13059 + attribute \src "libresoc.v:189818.3-189836.6" + process $proc$libresoc.v:189818$13243 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:187515.5-187515.29" + attribute \src "libresoc.v:189819.5-189819.29" switch \initial - attribute \src "libresoc.v:187515.9-187515.17" + attribute \src "libresoc.v:189819.9-189819.17" case 1'1 case end @@ -392488,17 +396497,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:187533.3-187574.6" - process $proc$libresoc.v:187533$13060 + attribute \src "libresoc.v:189837.3-189878.6" + process $proc$libresoc.v:189837$13244 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:187534.5-187534.29" + attribute \src "libresoc.v:189838.5-189838.29" switch \initial - attribute \src "libresoc.v:187534.9-187534.17" + attribute \src "libresoc.v:189838.9-189838.17" case 1'1 case end @@ -392549,14 +396558,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:187575.3-187590.6" - process $proc$libresoc.v:187575$13061 + attribute \src "libresoc.v:189879.3-189894.6" + process $proc$libresoc.v:189879$13245 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:187576.5-187576.29" + attribute \src "libresoc.v:189880.5-189880.29" switch \initial - attribute \src "libresoc.v:187576.9-187576.17" + attribute \src "libresoc.v:189880.9-189880.17" case 1'1 case end @@ -392581,14 +396590,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:187591.3-187611.6" - process $proc$libresoc.v:187591$13062 + attribute \src "libresoc.v:189895.3-189915.6" + process $proc$libresoc.v:189895$13246 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13063 $1\xer_so$8[0:0]$13064 - attribute \src "libresoc.v:187592.5-187592.29" + assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 + attribute \src "libresoc.v:189896.5-189896.29" switch \initial - attribute \src "libresoc.v:187592.9-187592.17" + attribute \src "libresoc.v:189896.9-189896.17" case 1'1 case end @@ -392597,39 +396606,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13064 $2\xer_so$8[0:0]$13065 + assign $1\xer_so$8[0:0]$13248 $2\xer_so$8[0:0]$13249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13065 $3\xer_so$8[0:0]$13066 + assign $2\xer_so$8[0:0]$13249 $3\xer_so$8[0:0]$13250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13066 \ra [31] + assign $3\xer_so$8[0:0]$13250 \ra [31] case - assign $3\xer_so$8[0:0]$13066 1'0 + assign $3\xer_so$8[0:0]$13250 1'0 end case - assign $2\xer_so$8[0:0]$13065 1'0 + assign $2\xer_so$8[0:0]$13249 1'0 end case - assign $1\xer_so$8[0:0]$13064 1'0 + assign $1\xer_so$8[0:0]$13248 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13063 + update \xer_so$8 $0\xer_so$8[0:0]$13247 end - attribute \src "libresoc.v:187612.3-187632.6" - process $proc$libresoc.v:187612$13067 + attribute \src "libresoc.v:189916.3-189936.6" + process $proc$libresoc.v:189916$13251 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:187613.5-187613.29" + attribute \src "libresoc.v:189917.5-189917.29" switch \initial - attribute \src "libresoc.v:187613.9-187613.17" + attribute \src "libresoc.v:189917.9-189917.17" case 1'1 case end @@ -392663,14 +396672,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:187633.3-187656.6" - process $proc$libresoc.v:187633$13068 + attribute \src "libresoc.v:189937.3-189960.6" + process $proc$libresoc.v:189937$13252 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13069 $1\xer_ov$9[1:0]$13070 - attribute \src "libresoc.v:187634.5-187634.29" + assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189938.5-189938.29" switch \initial - attribute \src "libresoc.v:187634.9-187634.17" + attribute \src "libresoc.v:189938.9-189938.17" case 1'1 case end @@ -392679,40 +396688,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13070 $2\xer_ov$9[1:0]$13071 + assign $1\xer_ov$9[1:0]$13254 $2\xer_ov$9[1:0]$13255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13071 $3\xer_ov$9[1:0]$13072 + assign $2\xer_ov$9[1:0]$13255 $3\xer_ov$9[1:0]$13256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13072 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13072 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13256 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13256 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13072 2'00 + assign $3\xer_ov$9[1:0]$13256 2'00 end case - assign $2\xer_ov$9[1:0]$13071 2'00 + assign $2\xer_ov$9[1:0]$13255 2'00 end case - assign $1\xer_ov$9[1:0]$13070 2'00 + assign $1\xer_ov$9[1:0]$13254 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13069 + update \xer_ov$9 $0\xer_ov$9[1:0]$13253 end - attribute \src "libresoc.v:187657.3-187677.6" - process $proc$libresoc.v:187657$13073 + attribute \src "libresoc.v:189961.3-189981.6" + process $proc$libresoc.v:189961$13257 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:187658.5-187658.29" + attribute \src "libresoc.v:189962.5-189962.29" switch \initial - attribute \src "libresoc.v:187658.9-187658.17" + attribute \src "libresoc.v:189962.9-189962.17" case 1'1 case end @@ -392746,14 +396755,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:187678.3-187701.6" - process $proc$libresoc.v:187678$13074 + attribute \src "libresoc.v:189982.3-190005.6" + process $proc$libresoc.v:189982$13258 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13075 $1\xer_ca$10[1:0]$13076 - attribute \src "libresoc.v:187679.5-187679.29" + assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:189983.5-189983.29" switch \initial - attribute \src "libresoc.v:187679.9-187679.17" + attribute \src "libresoc.v:189983.9-189983.17" case 1'1 case end @@ -392762,40 +396771,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13076 $2\xer_ca$10[1:0]$13077 + assign $1\xer_ca$10[1:0]$13260 $2\xer_ca$10[1:0]$13261 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13077 $3\xer_ca$10[1:0]$13078 + assign $2\xer_ca$10[1:0]$13261 $3\xer_ca$10[1:0]$13262 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13078 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13078 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13262 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13262 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13078 2'00 + assign $3\xer_ca$10[1:0]$13262 2'00 end case - assign $2\xer_ca$10[1:0]$13077 2'00 + assign $2\xer_ca$10[1:0]$13261 2'00 end case - assign $1\xer_ca$10[1:0]$13076 2'00 + assign $1\xer_ca$10[1:0]$13260 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13075 + update \xer_ca$10 $0\xer_ca$10[1:0]$13259 end - attribute \src "libresoc.v:187702.3-187722.6" - process $proc$libresoc.v:187702$13079 + attribute \src "libresoc.v:190006.3-190026.6" + process $proc$libresoc.v:190006$13263 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:187703.5-187703.29" + attribute \src "libresoc.v:190007.5-190007.29" switch \initial - attribute \src "libresoc.v:187703.9-187703.17" + attribute \src "libresoc.v:190007.9-190007.17" case 1'1 case end @@ -392829,14 +396838,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:187723.3-187741.6" - process $proc$libresoc.v:187723$13080 + attribute \src "libresoc.v:190027.3-190045.6" + process $proc$libresoc.v:190027$13264 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13081 $1\spr1$6[63:0]$13082 - attribute \src "libresoc.v:187724.5-187724.29" + assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:190028.5-190028.29" switch \initial - attribute \src "libresoc.v:187724.9-187724.17" + attribute \src "libresoc.v:190028.9-190028.17" case 1'1 case end @@ -392845,64 +396854,64 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13082 $2\spr1$6[63:0]$13083 + assign $1\spr1$6[63:0]$13266 $2\spr1$6[63:0]$13267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13083 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13267 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13083 \ra + assign $2\spr1$6[63:0]$13267 \ra end case - assign $1\spr1$6[63:0]$13082 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13266 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13081 + update \spr1$6 $0\spr1$6[63:0]$13265 end - connect \$11 $eq$libresoc.v:187491$13048_Y - connect \$13 $eq$libresoc.v:187492$13049_Y - connect \$15 $eq$libresoc.v:187493$13050_Y - connect \$17 $eq$libresoc.v:187494$13051_Y - connect \$19 $eq$libresoc.v:187495$13052_Y - connect \$21 $eq$libresoc.v:187496$13053_Y - connect \$23 $eq$libresoc.v:187497$13054_Y + connect \$11 $eq$libresoc.v:189795$13232_Y + connect \$13 $eq$libresoc.v:189796$13233_Y + connect \$15 $eq$libresoc.v:189797$13234_Y + connect \$17 $eq$libresoc.v:189798$13235_Y + connect \$19 $eq$libresoc.v:189799$13236_Y + connect \$21 $eq$libresoc.v:189800$13237_Y + connect \$23 $eq$libresoc.v:189801$13238_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:187749.1-188585.10" +attribute \src "libresoc.v:190053.1-190889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:187879.3-187909.6" + attribute \src "libresoc.v:190183.3-190213.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:187910.3-187940.6" + attribute \src "libresoc.v:190214.3-190244.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:187750.7-187750.20" + attribute \src "libresoc.v:190054.7-190054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187941.3-188262.6" + attribute \src "libresoc.v:190245.3-190566.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:188263.3-188584.6" + attribute \src "libresoc.v:190567.3-190888.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:187879.3-187909.6" + attribute \src "libresoc.v:190183.3-190213.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:187910.3-187940.6" + attribute \src "libresoc.v:190214.3-190244.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:187941.3-188262.6" + attribute \src "libresoc.v:190245.3-190566.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:188263.3-188584.6" + attribute \src "libresoc.v:190567.3-190888.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:187750.7-187750.15" + attribute \src "libresoc.v:190054.7-190054.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -393022,26 +397031,26 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:187750.7-187750.20" - process $proc$libresoc.v:187750$13089 + attribute \src "libresoc.v:190054.7-190054.20" + process $proc$libresoc.v:190054$13273 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187879.3-187909.6" - process $proc$libresoc.v:187879$13085 + attribute \src "libresoc.v:190183.3-190213.6" + process $proc$libresoc.v:190183$13269 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:187880.5-187880.29" + attribute \src "libresoc.v:190184.5-190184.29" switch \initial - attribute \src "libresoc.v:187880.9-187880.17" + attribute \src "libresoc.v:190184.9-190184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -393081,18 +397090,18 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:187910.3-187940.6" - process $proc$libresoc.v:187910$13086 + attribute \src "libresoc.v:190214.3-190244.6" + process $proc$libresoc.v:190214$13270 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:187911.5-187911.29" + attribute \src "libresoc.v:190215.5-190215.29" switch \initial - attribute \src "libresoc.v:187911.9-187911.17" + attribute \src "libresoc.v:190215.9-190215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -393132,18 +397141,18 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:187941.3-188262.6" - process $proc$libresoc.v:187941$13087 + attribute \src "libresoc.v:190245.3-190566.6" + process $proc$libresoc.v:190245$13271 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:187942.5-187942.29" + attribute \src "libresoc.v:190246.5-190246.29" switch \initial - attribute \src "libresoc.v:187942.9-187942.17" + attribute \src "libresoc.v:190246.9-190246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -393571,18 +397580,18 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:188263.3-188584.6" - process $proc$libresoc.v:188263$13088 + attribute \src "libresoc.v:190567.3-190888.6" + process $proc$libresoc.v:190567$13272 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:188264.5-188264.29" + attribute \src "libresoc.v:190568.5-190568.29" switch \initial - attribute \src "libresoc.v:188264.9-188264.17" + attribute \src "libresoc.v:190568.9-190568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -394011,36 +398020,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:188589.1-189425.10" +attribute \src "libresoc.v:190893.1-191729.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:188719.3-188749.6" + attribute \src "libresoc.v:191023.3-191053.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:188750.3-188780.6" + attribute \src "libresoc.v:191054.3-191084.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:188590.7-188590.20" + attribute \src "libresoc.v:190894.7-190894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188781.3-189102.6" + attribute \src "libresoc.v:191085.3-191406.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:189103.3-189424.6" + attribute \src "libresoc.v:191407.3-191728.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:188719.3-188749.6" + attribute \src "libresoc.v:191023.3-191053.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:188750.3-188780.6" + attribute \src "libresoc.v:191054.3-191084.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:188781.3-189102.6" + attribute \src "libresoc.v:191085.3-191406.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:189103.3-189424.6" + attribute \src "libresoc.v:191407.3-191728.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:188590.7-188590.15" + attribute \src "libresoc.v:190894.7-190894.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -394160,26 +398169,26 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:188590.7-188590.20" - process $proc$libresoc.v:188590$13094 + attribute \src "libresoc.v:190894.7-190894.20" + process $proc$libresoc.v:190894$13278 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188719.3-188749.6" - process $proc$libresoc.v:188719$13090 + attribute \src "libresoc.v:191023.3-191053.6" + process $proc$libresoc.v:191023$13274 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:188720.5-188720.29" + attribute \src "libresoc.v:191024.5-191024.29" switch \initial - attribute \src "libresoc.v:188720.9-188720.17" + attribute \src "libresoc.v:191024.9-191024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -394219,18 +398228,18 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:188750.3-188780.6" - process $proc$libresoc.v:188750$13091 + attribute \src "libresoc.v:191054.3-191084.6" + process $proc$libresoc.v:191054$13275 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:188751.5-188751.29" + attribute \src "libresoc.v:191055.5-191055.29" switch \initial - attribute \src "libresoc.v:188751.9-188751.17" + attribute \src "libresoc.v:191055.9-191055.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -394270,18 +398279,18 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:188781.3-189102.6" - process $proc$libresoc.v:188781$13092 + attribute \src "libresoc.v:191085.3-191406.6" + process $proc$libresoc.v:191085$13276 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:188782.5-188782.29" + attribute \src "libresoc.v:191086.5-191086.29" switch \initial - attribute \src "libresoc.v:188782.9-188782.17" + attribute \src "libresoc.v:191086.9-191086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -394709,18 +398718,18 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:189103.3-189424.6" - process $proc$libresoc.v:189103$13093 + attribute \src "libresoc.v:191407.3-191728.6" + process $proc$libresoc.v:191407$13277 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:189104.5-189104.29" + attribute \src "libresoc.v:191408.5-191408.29" switch \initial - attribute \src "libresoc.v:189104.9-189104.17" + attribute \src "libresoc.v:191408.9-191408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -395149,70 +399158,70 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:189429.1-189569.10" +attribute \src "libresoc.v:191733.1-191873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" attribute \generator "nMigen" module \sram4k_0 - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189430.7-189430.20" + attribute \src "libresoc.v:191734.7-191734.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $0\sram4k_0_wb__ack$next[0:0]$13099 - attribute \src "libresoc.v:189470.3-189471.49" + attribute \src "libresoc.v:191793.3-191807.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13283 + attribute \src "libresoc.v:191774.3-191775.49" wire $0\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $0\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189479.3-189488.6" + attribute \src "libresoc.v:191783.3-191792.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $0\we[0:0] - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $1\sram4k_0_wb__ack$next[0:0]$13100 - attribute \src "libresoc.v:189447.7-189447.30" + attribute \src "libresoc.v:191793.3-191807.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13284 + attribute \src "libresoc.v:191751.7-191751.30" wire $1\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189479.3-189488.6" + attribute \src "libresoc.v:191783.3-191792.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $1\we[0:0] - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $2\sram4k_0_wb__ack$next[0:0]$13101 - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191793.3-191807.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $2\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $2\we[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $3\we[0:0] - attribute \src "libresoc.v:189469.17-189469.129" - wire $and$libresoc.v:189469$13095_Y + attribute \src "libresoc.v:191773.17-191773.129" + wire $and$libresoc.v:191773$13279_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189430.7-189430.15" + attribute \src "libresoc.v:191734.7-191734.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_0_wb__ack @@ -395237,7 +399246,7 @@ module \sram4k_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189469$13095 + cell $and $and$libresoc.v:191773$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395245,10 +399254,10 @@ module \sram4k_0 parameter \Y_WIDTH 1 connect \A \sram4k_0_wb__cyc connect \B \sram4k_0_wb__stb - connect \Y $and$libresoc.v:189469$13095_Y + connect \Y $and$libresoc.v:191773$13279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189472.21-189478.4" + attribute \src "libresoc.v:191776.21-191782.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395256,37 +399265,37 @@ module \sram4k_0 connect \q \q connect \we \we end - attribute \src "libresoc.v:189430.7-189430.20" - process $proc$libresoc.v:189430$13106 + attribute \src "libresoc.v:191734.7-191734.20" + process $proc$libresoc.v:191734$13290 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189447.7-189447.30" - process $proc$libresoc.v:189447$13107 + attribute \src "libresoc.v:191751.7-191751.30" + process $proc$libresoc.v:191751$13291 assign { } { } assign $1\sram4k_0_wb__ack[0:0] 1'0 sync always sync init update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:189470.3-189471.49" - process $proc$libresoc.v:189470$13096 + attribute \src "libresoc.v:191774.3-191775.49" + process $proc$libresoc.v:191774$13280 assign { } { } assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next sync posedge \clk update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:189479.3-189488.6" - process $proc$libresoc.v:189479$13097 + attribute \src "libresoc.v:191783.3-191792.6" + process $proc$libresoc.v:191783$13281 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189480.5-189480.29" + attribute \src "libresoc.v:191784.5-191784.29" switch \initial - attribute \src "libresoc.v:189480.9-189480.17" + attribute \src "libresoc.v:191784.9-191784.17" case 1'1 case end @@ -395302,15 +399311,15 @@ module \sram4k_0 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189489.3-189503.6" - process $proc$libresoc.v:189489$13098 + attribute \src "libresoc.v:191793.3-191807.6" + process $proc$libresoc.v:191793$13282 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_0_wb__ack$next[0:0]$13099 $2\sram4k_0_wb__ack$next[0:0]$13101 - attribute \src "libresoc.v:189490.5-189490.29" + assign $0\sram4k_0_wb__ack$next[0:0]$13283 $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191794.5-191794.29" switch \initial - attribute \src "libresoc.v:189490.9-189490.17" + attribute \src "libresoc.v:191794.9-191794.17" case 1'1 case end @@ -395319,30 +399328,30 @@ module \sram4k_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_0_wb__ack$next[0:0]$13100 \wb_active + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \wb_active case - assign $1\sram4k_0_wb__ack$next[0:0]$13100 \sram4k_0_wb__ack + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \sram4k_0_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_0_wb__ack$next[0:0]$13101 1'0 + assign $2\sram4k_0_wb__ack$next[0:0]$13285 1'0 case - assign $2\sram4k_0_wb__ack$next[0:0]$13101 $1\sram4k_0_wb__ack$next[0:0]$13100 + assign $2\sram4k_0_wb__ack$next[0:0]$13285 $1\sram4k_0_wb__ack$next[0:0]$13284 end sync always - update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13099 + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13283 end - attribute \src "libresoc.v:189504.3-189518.6" - process $proc$libresoc.v:189504$13102 + attribute \src "libresoc.v:191808.3-191822.6" + process $proc$libresoc.v:191808$13286 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189505.5-189505.29" + attribute \src "libresoc.v:191809.5-191809.29" switch \initial - attribute \src "libresoc.v:189505.9-189505.17" + attribute \src "libresoc.v:191809.9-191809.17" case 1'1 case end @@ -395367,14 +399376,14 @@ module \sram4k_0 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189519.3-189533.6" - process $proc$libresoc.v:189519$13103 + attribute \src "libresoc.v:191823.3-191837.6" + process $proc$libresoc.v:191823$13287 assign { } { } assign { } { } assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189520.5-189520.29" + attribute \src "libresoc.v:191824.5-191824.29" switch \initial - attribute \src "libresoc.v:189520.9-189520.17" + attribute \src "libresoc.v:191824.9-191824.17" case 1'1 case end @@ -395399,14 +399408,14 @@ module \sram4k_0 sync always update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] end - attribute \src "libresoc.v:189534.3-189548.6" - process $proc$libresoc.v:189534$13104 + attribute \src "libresoc.v:191838.3-191852.6" + process $proc$libresoc.v:191838$13288 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189535.5-189535.29" + attribute \src "libresoc.v:191839.5-191839.29" switch \initial - attribute \src "libresoc.v:189535.9-189535.17" + attribute \src "libresoc.v:191839.9-191839.17" case 1'1 case end @@ -395431,14 +399440,14 @@ module \sram4k_0 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189549.3-189568.6" - process $proc$libresoc.v:189549$13105 + attribute \src "libresoc.v:191853.3-191872.6" + process $proc$libresoc.v:191853$13289 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189550.5-189550.29" + attribute \src "libresoc.v:191854.5-191854.29" switch \initial - attribute \src "libresoc.v:189550.9-189550.17" + attribute \src "libresoc.v:191854.9-191854.17" case 1'1 case end @@ -395472,72 +399481,72 @@ module \sram4k_0 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189469$13095_Y + connect \$1 $and$libresoc.v:191773$13279_Y end -attribute \src "libresoc.v:189573.1-189713.10" +attribute \src "libresoc.v:191877.1-192017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" attribute \generator "nMigen" module \sram4k_1 - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189574.7-189574.20" + attribute \src "libresoc.v:191878.7-191878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $0\sram4k_1_wb__ack$next[0:0]$13112 - attribute \src "libresoc.v:189614.3-189615.49" + attribute \src "libresoc.v:191937.3-191951.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13296 + attribute \src "libresoc.v:191918.3-191919.49" wire $0\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $0\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189623.3-189632.6" + attribute \src "libresoc.v:191927.3-191936.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $0\we[0:0] - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $1\sram4k_1_wb__ack$next[0:0]$13113 - attribute \src "libresoc.v:189591.7-189591.30" + attribute \src "libresoc.v:191937.3-191951.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13297 + attribute \src "libresoc.v:191895.7-191895.30" wire $1\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189623.3-189632.6" + attribute \src "libresoc.v:191927.3-191936.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $1\we[0:0] - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $2\sram4k_1_wb__ack$next[0:0]$13114 - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191937.3-191951.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $2\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $2\we[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $3\we[0:0] - attribute \src "libresoc.v:189613.17-189613.129" - wire $and$libresoc.v:189613$13108_Y + attribute \src "libresoc.v:191917.17-191917.129" + wire $and$libresoc.v:191917$13292_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189574.7-189574.15" + attribute \src "libresoc.v:191878.7-191878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_1_wb__ack @@ -395562,7 +399571,7 @@ module \sram4k_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189613$13108 + cell $and $and$libresoc.v:191917$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395570,10 +399579,10 @@ module \sram4k_1 parameter \Y_WIDTH 1 connect \A \sram4k_1_wb__cyc connect \B \sram4k_1_wb__stb - connect \Y $and$libresoc.v:189613$13108_Y + connect \Y $and$libresoc.v:191917$13292_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189616.21-189622.4" + attribute \src "libresoc.v:191920.21-191926.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395581,37 +399590,37 @@ module \sram4k_1 connect \q \q connect \we \we end - attribute \src "libresoc.v:189574.7-189574.20" - process $proc$libresoc.v:189574$13119 + attribute \src "libresoc.v:191878.7-191878.20" + process $proc$libresoc.v:191878$13303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189591.7-189591.30" - process $proc$libresoc.v:189591$13120 + attribute \src "libresoc.v:191895.7-191895.30" + process $proc$libresoc.v:191895$13304 assign { } { } assign $1\sram4k_1_wb__ack[0:0] 1'0 sync always sync init update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:189614.3-189615.49" - process $proc$libresoc.v:189614$13109 + attribute \src "libresoc.v:191918.3-191919.49" + process $proc$libresoc.v:191918$13293 assign { } { } assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next sync posedge \clk update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:189623.3-189632.6" - process $proc$libresoc.v:189623$13110 + attribute \src "libresoc.v:191927.3-191936.6" + process $proc$libresoc.v:191927$13294 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189624.5-189624.29" + attribute \src "libresoc.v:191928.5-191928.29" switch \initial - attribute \src "libresoc.v:189624.9-189624.17" + attribute \src "libresoc.v:191928.9-191928.17" case 1'1 case end @@ -395627,15 +399636,15 @@ module \sram4k_1 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189633.3-189647.6" - process $proc$libresoc.v:189633$13111 + attribute \src "libresoc.v:191937.3-191951.6" + process $proc$libresoc.v:191937$13295 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_1_wb__ack$next[0:0]$13112 $2\sram4k_1_wb__ack$next[0:0]$13114 - attribute \src "libresoc.v:189634.5-189634.29" + assign $0\sram4k_1_wb__ack$next[0:0]$13296 $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191938.5-191938.29" switch \initial - attribute \src "libresoc.v:189634.9-189634.17" + attribute \src "libresoc.v:191938.9-191938.17" case 1'1 case end @@ -395644,30 +399653,30 @@ module \sram4k_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_1_wb__ack$next[0:0]$13113 \wb_active + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \wb_active case - assign $1\sram4k_1_wb__ack$next[0:0]$13113 \sram4k_1_wb__ack + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \sram4k_1_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_1_wb__ack$next[0:0]$13114 1'0 + assign $2\sram4k_1_wb__ack$next[0:0]$13298 1'0 case - assign $2\sram4k_1_wb__ack$next[0:0]$13114 $1\sram4k_1_wb__ack$next[0:0]$13113 + assign $2\sram4k_1_wb__ack$next[0:0]$13298 $1\sram4k_1_wb__ack$next[0:0]$13297 end sync always - update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13112 + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13296 end - attribute \src "libresoc.v:189648.3-189662.6" - process $proc$libresoc.v:189648$13115 + attribute \src "libresoc.v:191952.3-191966.6" + process $proc$libresoc.v:191952$13299 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189649.5-189649.29" + attribute \src "libresoc.v:191953.5-191953.29" switch \initial - attribute \src "libresoc.v:189649.9-189649.17" + attribute \src "libresoc.v:191953.9-191953.17" case 1'1 case end @@ -395692,14 +399701,14 @@ module \sram4k_1 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189663.3-189677.6" - process $proc$libresoc.v:189663$13116 + attribute \src "libresoc.v:191967.3-191981.6" + process $proc$libresoc.v:191967$13300 assign { } { } assign { } { } assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189664.5-189664.29" + attribute \src "libresoc.v:191968.5-191968.29" switch \initial - attribute \src "libresoc.v:189664.9-189664.17" + attribute \src "libresoc.v:191968.9-191968.17" case 1'1 case end @@ -395724,14 +399733,14 @@ module \sram4k_1 sync always update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] end - attribute \src "libresoc.v:189678.3-189692.6" - process $proc$libresoc.v:189678$13117 + attribute \src "libresoc.v:191982.3-191996.6" + process $proc$libresoc.v:191982$13301 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189679.5-189679.29" + attribute \src "libresoc.v:191983.5-191983.29" switch \initial - attribute \src "libresoc.v:189679.9-189679.17" + attribute \src "libresoc.v:191983.9-191983.17" case 1'1 case end @@ -395756,14 +399765,14 @@ module \sram4k_1 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189693.3-189712.6" - process $proc$libresoc.v:189693$13118 + attribute \src "libresoc.v:191997.3-192016.6" + process $proc$libresoc.v:191997$13302 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189694.5-189694.29" + attribute \src "libresoc.v:191998.5-191998.29" switch \initial - attribute \src "libresoc.v:189694.9-189694.17" + attribute \src "libresoc.v:191998.9-191998.17" case 1'1 case end @@ -395797,72 +399806,72 @@ module \sram4k_1 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189613$13108_Y + connect \$1 $and$libresoc.v:191917$13292_Y end -attribute \src "libresoc.v:189717.1-189857.10" +attribute \src "libresoc.v:192021.1-192161.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" attribute \generator "nMigen" module \sram4k_2 - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189718.7-189718.20" + attribute \src "libresoc.v:192022.7-192022.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $0\sram4k_2_wb__ack$next[0:0]$13125 - attribute \src "libresoc.v:189758.3-189759.49" + attribute \src "libresoc.v:192081.3-192095.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13309 + attribute \src "libresoc.v:192062.3-192063.49" wire $0\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $0\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189767.3-189776.6" + attribute \src "libresoc.v:192071.3-192080.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $0\we[0:0] - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $1\sram4k_2_wb__ack$next[0:0]$13126 - attribute \src "libresoc.v:189735.7-189735.30" + attribute \src "libresoc.v:192081.3-192095.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13310 + attribute \src "libresoc.v:192039.7-192039.30" wire $1\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189767.3-189776.6" + attribute \src "libresoc.v:192071.3-192080.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $1\we[0:0] - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $2\sram4k_2_wb__ack$next[0:0]$13127 - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192081.3-192095.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $2\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $2\we[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $3\we[0:0] - attribute \src "libresoc.v:189757.17-189757.129" - wire $and$libresoc.v:189757$13121_Y + attribute \src "libresoc.v:192061.17-192061.129" + wire $and$libresoc.v:192061$13305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189718.7-189718.15" + attribute \src "libresoc.v:192022.7-192022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_2_wb__ack @@ -395887,7 +399896,7 @@ module \sram4k_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189757$13121 + cell $and $and$libresoc.v:192061$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395895,10 +399904,10 @@ module \sram4k_2 parameter \Y_WIDTH 1 connect \A \sram4k_2_wb__cyc connect \B \sram4k_2_wb__stb - connect \Y $and$libresoc.v:189757$13121_Y + connect \Y $and$libresoc.v:192061$13305_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189760.21-189766.4" + attribute \src "libresoc.v:192064.21-192070.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395906,37 +399915,37 @@ module \sram4k_2 connect \q \q connect \we \we end - attribute \src "libresoc.v:189718.7-189718.20" - process $proc$libresoc.v:189718$13132 + attribute \src "libresoc.v:192022.7-192022.20" + process $proc$libresoc.v:192022$13316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189735.7-189735.30" - process $proc$libresoc.v:189735$13133 + attribute \src "libresoc.v:192039.7-192039.30" + process $proc$libresoc.v:192039$13317 assign { } { } assign $1\sram4k_2_wb__ack[0:0] 1'0 sync always sync init update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:189758.3-189759.49" - process $proc$libresoc.v:189758$13122 + attribute \src "libresoc.v:192062.3-192063.49" + process $proc$libresoc.v:192062$13306 assign { } { } assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next sync posedge \clk update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:189767.3-189776.6" - process $proc$libresoc.v:189767$13123 + attribute \src "libresoc.v:192071.3-192080.6" + process $proc$libresoc.v:192071$13307 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189768.5-189768.29" + attribute \src "libresoc.v:192072.5-192072.29" switch \initial - attribute \src "libresoc.v:189768.9-189768.17" + attribute \src "libresoc.v:192072.9-192072.17" case 1'1 case end @@ -395952,15 +399961,15 @@ module \sram4k_2 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189777.3-189791.6" - process $proc$libresoc.v:189777$13124 + attribute \src "libresoc.v:192081.3-192095.6" + process $proc$libresoc.v:192081$13308 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_2_wb__ack$next[0:0]$13125 $2\sram4k_2_wb__ack$next[0:0]$13127 - attribute \src "libresoc.v:189778.5-189778.29" + assign $0\sram4k_2_wb__ack$next[0:0]$13309 $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192082.5-192082.29" switch \initial - attribute \src "libresoc.v:189778.9-189778.17" + attribute \src "libresoc.v:192082.9-192082.17" case 1'1 case end @@ -395969,30 +399978,30 @@ module \sram4k_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_2_wb__ack$next[0:0]$13126 \wb_active + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \wb_active case - assign $1\sram4k_2_wb__ack$next[0:0]$13126 \sram4k_2_wb__ack + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \sram4k_2_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_2_wb__ack$next[0:0]$13127 1'0 + assign $2\sram4k_2_wb__ack$next[0:0]$13311 1'0 case - assign $2\sram4k_2_wb__ack$next[0:0]$13127 $1\sram4k_2_wb__ack$next[0:0]$13126 + assign $2\sram4k_2_wb__ack$next[0:0]$13311 $1\sram4k_2_wb__ack$next[0:0]$13310 end sync always - update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13125 + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13309 end - attribute \src "libresoc.v:189792.3-189806.6" - process $proc$libresoc.v:189792$13128 + attribute \src "libresoc.v:192096.3-192110.6" + process $proc$libresoc.v:192096$13312 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189793.5-189793.29" + attribute \src "libresoc.v:192097.5-192097.29" switch \initial - attribute \src "libresoc.v:189793.9-189793.17" + attribute \src "libresoc.v:192097.9-192097.17" case 1'1 case end @@ -396017,14 +400026,14 @@ module \sram4k_2 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189807.3-189821.6" - process $proc$libresoc.v:189807$13129 + attribute \src "libresoc.v:192111.3-192125.6" + process $proc$libresoc.v:192111$13313 assign { } { } assign { } { } assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189808.5-189808.29" + attribute \src "libresoc.v:192112.5-192112.29" switch \initial - attribute \src "libresoc.v:189808.9-189808.17" + attribute \src "libresoc.v:192112.9-192112.17" case 1'1 case end @@ -396049,14 +400058,14 @@ module \sram4k_2 sync always update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] end - attribute \src "libresoc.v:189822.3-189836.6" - process $proc$libresoc.v:189822$13130 + attribute \src "libresoc.v:192126.3-192140.6" + process $proc$libresoc.v:192126$13314 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189823.5-189823.29" + attribute \src "libresoc.v:192127.5-192127.29" switch \initial - attribute \src "libresoc.v:189823.9-189823.17" + attribute \src "libresoc.v:192127.9-192127.17" case 1'1 case end @@ -396081,14 +400090,14 @@ module \sram4k_2 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189837.3-189856.6" - process $proc$libresoc.v:189837$13131 + attribute \src "libresoc.v:192141.3-192160.6" + process $proc$libresoc.v:192141$13315 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189838.5-189838.29" + attribute \src "libresoc.v:192142.5-192142.29" switch \initial - attribute \src "libresoc.v:189838.9-189838.17" + attribute \src "libresoc.v:192142.9-192142.17" case 1'1 case end @@ -396122,72 +400131,72 @@ module \sram4k_2 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189757$13121_Y + connect \$1 $and$libresoc.v:192061$13305_Y end -attribute \src "libresoc.v:189861.1-190001.10" +attribute \src "libresoc.v:192165.1-192305.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" attribute \generator "nMigen" module \sram4k_3 - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189862.7-189862.20" + attribute \src "libresoc.v:192166.7-192166.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $0\sram4k_3_wb__ack$next[0:0]$13138 - attribute \src "libresoc.v:189902.3-189903.49" + attribute \src "libresoc.v:192225.3-192239.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13322 + attribute \src "libresoc.v:192206.3-192207.49" wire $0\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $0\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189911.3-189920.6" + attribute \src "libresoc.v:192215.3-192224.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $0\we[0:0] - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $1\sram4k_3_wb__ack$next[0:0]$13139 - attribute \src "libresoc.v:189879.7-189879.30" + attribute \src "libresoc.v:192225.3-192239.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13323 + attribute \src "libresoc.v:192183.7-192183.30" wire $1\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189911.3-189920.6" + attribute \src "libresoc.v:192215.3-192224.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $1\we[0:0] - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $2\sram4k_3_wb__ack$next[0:0]$13140 - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192225.3-192239.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $2\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $2\we[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $3\we[0:0] - attribute \src "libresoc.v:189901.17-189901.129" - wire $and$libresoc.v:189901$13134_Y + attribute \src "libresoc.v:192205.17-192205.129" + wire $and$libresoc.v:192205$13318_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189862.7-189862.15" + attribute \src "libresoc.v:192166.7-192166.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_3_wb__ack @@ -396212,7 +400221,7 @@ module \sram4k_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189901$13134 + cell $and $and$libresoc.v:192205$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396220,10 +400229,10 @@ module \sram4k_3 parameter \Y_WIDTH 1 connect \A \sram4k_3_wb__cyc connect \B \sram4k_3_wb__stb - connect \Y $and$libresoc.v:189901$13134_Y + connect \Y $and$libresoc.v:192205$13318_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189904.21-189910.4" + attribute \src "libresoc.v:192208.21-192214.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -396231,37 +400240,37 @@ module \sram4k_3 connect \q \q connect \we \we end - attribute \src "libresoc.v:189862.7-189862.20" - process $proc$libresoc.v:189862$13145 + attribute \src "libresoc.v:192166.7-192166.20" + process $proc$libresoc.v:192166$13329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189879.7-189879.30" - process $proc$libresoc.v:189879$13146 + attribute \src "libresoc.v:192183.7-192183.30" + process $proc$libresoc.v:192183$13330 assign { } { } assign $1\sram4k_3_wb__ack[0:0] 1'0 sync always sync init update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:189902.3-189903.49" - process $proc$libresoc.v:189902$13135 + attribute \src "libresoc.v:192206.3-192207.49" + process $proc$libresoc.v:192206$13319 assign { } { } assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next sync posedge \clk update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:189911.3-189920.6" - process $proc$libresoc.v:189911$13136 + attribute \src "libresoc.v:192215.3-192224.6" + process $proc$libresoc.v:192215$13320 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189912.5-189912.29" + attribute \src "libresoc.v:192216.5-192216.29" switch \initial - attribute \src "libresoc.v:189912.9-189912.17" + attribute \src "libresoc.v:192216.9-192216.17" case 1'1 case end @@ -396277,15 +400286,15 @@ module \sram4k_3 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189921.3-189935.6" - process $proc$libresoc.v:189921$13137 + attribute \src "libresoc.v:192225.3-192239.6" + process $proc$libresoc.v:192225$13321 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_3_wb__ack$next[0:0]$13138 $2\sram4k_3_wb__ack$next[0:0]$13140 - attribute \src "libresoc.v:189922.5-189922.29" + assign $0\sram4k_3_wb__ack$next[0:0]$13322 $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192226.5-192226.29" switch \initial - attribute \src "libresoc.v:189922.9-189922.17" + attribute \src "libresoc.v:192226.9-192226.17" case 1'1 case end @@ -396294,30 +400303,30 @@ module \sram4k_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_3_wb__ack$next[0:0]$13139 \wb_active + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \wb_active case - assign $1\sram4k_3_wb__ack$next[0:0]$13139 \sram4k_3_wb__ack + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \sram4k_3_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_3_wb__ack$next[0:0]$13140 1'0 + assign $2\sram4k_3_wb__ack$next[0:0]$13324 1'0 case - assign $2\sram4k_3_wb__ack$next[0:0]$13140 $1\sram4k_3_wb__ack$next[0:0]$13139 + assign $2\sram4k_3_wb__ack$next[0:0]$13324 $1\sram4k_3_wb__ack$next[0:0]$13323 end sync always - update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13138 + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13322 end - attribute \src "libresoc.v:189936.3-189950.6" - process $proc$libresoc.v:189936$13141 + attribute \src "libresoc.v:192240.3-192254.6" + process $proc$libresoc.v:192240$13325 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189937.5-189937.29" + attribute \src "libresoc.v:192241.5-192241.29" switch \initial - attribute \src "libresoc.v:189937.9-189937.17" + attribute \src "libresoc.v:192241.9-192241.17" case 1'1 case end @@ -396342,14 +400351,14 @@ module \sram4k_3 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189951.3-189965.6" - process $proc$libresoc.v:189951$13142 + attribute \src "libresoc.v:192255.3-192269.6" + process $proc$libresoc.v:192255$13326 assign { } { } assign { } { } assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189952.5-189952.29" + attribute \src "libresoc.v:192256.5-192256.29" switch \initial - attribute \src "libresoc.v:189952.9-189952.17" + attribute \src "libresoc.v:192256.9-192256.17" case 1'1 case end @@ -396374,14 +400383,14 @@ module \sram4k_3 sync always update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] end - attribute \src "libresoc.v:189966.3-189980.6" - process $proc$libresoc.v:189966$13143 + attribute \src "libresoc.v:192270.3-192284.6" + process $proc$libresoc.v:192270$13327 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189967.5-189967.29" + attribute \src "libresoc.v:192271.5-192271.29" switch \initial - attribute \src "libresoc.v:189967.9-189967.17" + attribute \src "libresoc.v:192271.9-192271.17" case 1'1 case end @@ -396406,14 +400415,14 @@ module \sram4k_3 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189981.3-190000.6" - process $proc$libresoc.v:189981$13144 + attribute \src "libresoc.v:192285.3-192304.6" + process $proc$libresoc.v:192285$13328 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189982.5-189982.29" + attribute \src "libresoc.v:192286.5-192286.29" switch \initial - attribute \src "libresoc.v:189982.9-189982.17" + attribute \src "libresoc.v:192286.9-192286.17" case 1'1 case end @@ -396447,39 +400456,39 @@ module \sram4k_3 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189901$13134_Y + connect \$1 $and$libresoc.v:192205$13318_Y end -attribute \src "libresoc.v:190005.1-190063.10" +attribute \src "libresoc.v:192309.1-192367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:190006.7-190006.20" + attribute \src "libresoc.v:192310.7-192310.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190051.3-190059.6" - wire width 4 $0\q_int$next[3:0]$13157 - attribute \src "libresoc.v:190049.3-190050.27" + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $0\q_int$next[3:0]$13341 + attribute \src "libresoc.v:192353.3-192354.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:190051.3-190059.6" - wire width 4 $1\q_int$next[3:0]$13158 - attribute \src "libresoc.v:190028.13-190028.25" + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192332.13-192332.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:190041.17-190041.96" - wire width 4 $and$libresoc.v:190041$13147_Y - attribute \src "libresoc.v:190046.17-190046.96" - wire width 4 $and$libresoc.v:190046$13152_Y - attribute \src "libresoc.v:190043.18-190043.93" - wire width 4 $not$libresoc.v:190043$13149_Y - attribute \src "libresoc.v:190045.17-190045.92" - wire width 4 $not$libresoc.v:190045$13151_Y - attribute \src "libresoc.v:190048.17-190048.92" - wire width 4 $not$libresoc.v:190048$13154_Y - attribute \src "libresoc.v:190042.18-190042.98" - wire width 4 $or$libresoc.v:190042$13148_Y - attribute \src "libresoc.v:190044.18-190044.99" - wire width 4 $or$libresoc.v:190044$13150_Y - attribute \src "libresoc.v:190047.17-190047.97" - wire width 4 $or$libresoc.v:190047$13153_Y + attribute \src "libresoc.v:192345.17-192345.96" + wire width 4 $and$libresoc.v:192345$13331_Y + attribute \src "libresoc.v:192350.17-192350.96" + wire width 4 $and$libresoc.v:192350$13336_Y + attribute \src "libresoc.v:192347.18-192347.93" + wire width 4 $not$libresoc.v:192347$13333_Y + attribute \src "libresoc.v:192349.17-192349.92" + wire width 4 $not$libresoc.v:192349$13335_Y + attribute \src "libresoc.v:192352.17-192352.92" + wire width 4 $not$libresoc.v:192352$13338_Y + attribute \src "libresoc.v:192346.18-192346.98" + wire width 4 $or$libresoc.v:192346$13332_Y + attribute \src "libresoc.v:192348.18-192348.99" + wire width 4 $or$libresoc.v:192348$13334_Y + attribute \src "libresoc.v:192351.17-192351.97" + wire width 4 $or$libresoc.v:192351$13337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396496,11 +400505,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190006.7-190006.15" + attribute \src "libresoc.v:192310.7-192310.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -396517,7 +400526,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190041$13147 + cell $and $and$libresoc.v:192345$13331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396525,10 +400534,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190041$13147_Y + connect \Y $and$libresoc.v:192345$13331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190046$13152 + cell $and $and$libresoc.v:192350$13336 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396536,34 +400545,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190046$13152_Y + connect \Y $and$libresoc.v:192350$13336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190043$13149 + cell $not $not$libresoc.v:192347$13333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:190043$13149_Y + connect \Y $not$libresoc.v:192347$13333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190045$13151 + cell $not $not$libresoc.v:192349$13335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190045$13151_Y + connect \Y $not$libresoc.v:192349$13335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190048$13154 + cell $not $not$libresoc.v:192352$13338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190048$13154_Y + connect \Y $not$libresoc.v:192352$13338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190042$13148 + cell $or $or$libresoc.v:192346$13332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396571,10 +400580,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190042$13148_Y + connect \Y $or$libresoc.v:192346$13332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190044$13150 + cell $or $or$libresoc.v:192348$13334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396582,10 +400591,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190044$13150_Y + connect \Y $or$libresoc.v:192348$13334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190047$13153 + cell $or $or$libresoc.v:192351$13337 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396593,39 +400602,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190047$13153_Y + connect \Y $or$libresoc.v:192351$13337_Y end - attribute \src "libresoc.v:190006.7-190006.20" - process $proc$libresoc.v:190006$13159 + attribute \src "libresoc.v:192310.7-192310.20" + process $proc$libresoc.v:192310$13343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190028.13-190028.25" - process $proc$libresoc.v:190028$13160 + attribute \src "libresoc.v:192332.13-192332.25" + process $proc$libresoc.v:192332$13344 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:190049.3-190050.27" - process $proc$libresoc.v:190049$13155 + attribute \src "libresoc.v:192353.3-192354.27" + process $proc$libresoc.v:192353$13339 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:190051.3-190059.6" - process $proc$libresoc.v:190051$13156 + attribute \src "libresoc.v:192355.3-192363.6" + process $proc$libresoc.v:192355$13340 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13157 $1\q_int$next[3:0]$13158 - attribute \src "libresoc.v:190052.5-190052.29" + assign $0\q_int$next[3:0]$13341 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192356.5-192356.29" switch \initial - attribute \src "libresoc.v:190052.9-190052.17" + attribute \src "libresoc.v:192356.9-192356.17" case 1'1 case end @@ -396634,56 +400643,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13158 4'0000 + assign $1\q_int$next[3:0]$13342 4'0000 case - assign $1\q_int$next[3:0]$13158 \$5 + assign $1\q_int$next[3:0]$13342 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13157 + update \q_int$next $0\q_int$next[3:0]$13341 end - connect \$9 $and$libresoc.v:190041$13147_Y - connect \$11 $or$libresoc.v:190042$13148_Y - connect \$13 $not$libresoc.v:190043$13149_Y - connect \$15 $or$libresoc.v:190044$13150_Y - connect \$1 $not$libresoc.v:190045$13151_Y - connect \$3 $and$libresoc.v:190046$13152_Y - connect \$5 $or$libresoc.v:190047$13153_Y - connect \$7 $not$libresoc.v:190048$13154_Y + connect \$9 $and$libresoc.v:192345$13331_Y + connect \$11 $or$libresoc.v:192346$13332_Y + connect \$13 $not$libresoc.v:192347$13333_Y + connect \$15 $or$libresoc.v:192348$13334_Y + connect \$1 $not$libresoc.v:192349$13335_Y + connect \$3 $and$libresoc.v:192350$13336_Y + connect \$5 $or$libresoc.v:192351$13337_Y + connect \$7 $not$libresoc.v:192352$13338_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190067.1-190125.10" +attribute \src "libresoc.v:192371.1-192429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:190068.7-190068.20" + attribute \src "libresoc.v:192372.7-192372.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190113.3-190121.6" - wire width 6 $0\q_int$next[5:0]$13171 - attribute \src "libresoc.v:190111.3-190112.27" + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $0\q_int$next[5:0]$13355 + attribute \src "libresoc.v:192415.3-192416.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:190113.3-190121.6" - wire width 6 $1\q_int$next[5:0]$13172 - attribute \src "libresoc.v:190090.13-190090.26" + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192394.13-192394.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:190103.17-190103.96" - wire width 6 $and$libresoc.v:190103$13161_Y - attribute \src "libresoc.v:190108.17-190108.96" - wire width 6 $and$libresoc.v:190108$13166_Y - attribute \src "libresoc.v:190105.18-190105.93" - wire width 6 $not$libresoc.v:190105$13163_Y - attribute \src "libresoc.v:190107.17-190107.92" - wire width 6 $not$libresoc.v:190107$13165_Y - attribute \src "libresoc.v:190110.17-190110.92" - wire width 6 $not$libresoc.v:190110$13168_Y - attribute \src "libresoc.v:190104.18-190104.98" - wire width 6 $or$libresoc.v:190104$13162_Y - attribute \src "libresoc.v:190106.18-190106.99" - wire width 6 $or$libresoc.v:190106$13164_Y - attribute \src "libresoc.v:190109.17-190109.97" - wire width 6 $or$libresoc.v:190109$13167_Y + attribute \src "libresoc.v:192407.17-192407.96" + wire width 6 $and$libresoc.v:192407$13345_Y + attribute \src "libresoc.v:192412.17-192412.96" + wire width 6 $and$libresoc.v:192412$13350_Y + attribute \src "libresoc.v:192409.18-192409.93" + wire width 6 $not$libresoc.v:192409$13347_Y + attribute \src "libresoc.v:192411.17-192411.92" + wire width 6 $not$libresoc.v:192411$13349_Y + attribute \src "libresoc.v:192414.17-192414.92" + wire width 6 $not$libresoc.v:192414$13352_Y + attribute \src "libresoc.v:192408.18-192408.98" + wire width 6 $or$libresoc.v:192408$13346_Y + attribute \src "libresoc.v:192410.18-192410.99" + wire width 6 $or$libresoc.v:192410$13348_Y + attribute \src "libresoc.v:192413.17-192413.97" + wire width 6 $or$libresoc.v:192413$13351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396700,11 +400709,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190068.7-190068.15" + attribute \src "libresoc.v:192372.7-192372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -396721,7 +400730,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190103$13161 + cell $and $and$libresoc.v:192407$13345 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396729,10 +400738,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190103$13161_Y + connect \Y $and$libresoc.v:192407$13345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190108$13166 + cell $and $and$libresoc.v:192412$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396740,34 +400749,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190108$13166_Y + connect \Y $and$libresoc.v:192412$13350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190105$13163 + cell $not $not$libresoc.v:192409$13347 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:190105$13163_Y + connect \Y $not$libresoc.v:192409$13347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190107$13165 + cell $not $not$libresoc.v:192411$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190107$13165_Y + connect \Y $not$libresoc.v:192411$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190110$13168 + cell $not $not$libresoc.v:192414$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190110$13168_Y + connect \Y $not$libresoc.v:192414$13352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190104$13162 + cell $or $or$libresoc.v:192408$13346 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396775,10 +400784,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190104$13162_Y + connect \Y $or$libresoc.v:192408$13346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190106$13164 + cell $or $or$libresoc.v:192410$13348 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396786,10 +400795,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190106$13164_Y + connect \Y $or$libresoc.v:192410$13348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190109$13167 + cell $or $or$libresoc.v:192413$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396797,39 +400806,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190109$13167_Y + connect \Y $or$libresoc.v:192413$13351_Y end - attribute \src "libresoc.v:190068.7-190068.20" - process $proc$libresoc.v:190068$13173 + attribute \src "libresoc.v:192372.7-192372.20" + process $proc$libresoc.v:192372$13357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190090.13-190090.26" - process $proc$libresoc.v:190090$13174 + attribute \src "libresoc.v:192394.13-192394.26" + process $proc$libresoc.v:192394$13358 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:190111.3-190112.27" - process $proc$libresoc.v:190111$13169 + attribute \src "libresoc.v:192415.3-192416.27" + process $proc$libresoc.v:192415$13353 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:190113.3-190121.6" - process $proc$libresoc.v:190113$13170 + attribute \src "libresoc.v:192417.3-192425.6" + process $proc$libresoc.v:192417$13354 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13171 $1\q_int$next[5:0]$13172 - attribute \src "libresoc.v:190114.5-190114.29" + assign $0\q_int$next[5:0]$13355 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192418.5-192418.29" switch \initial - attribute \src "libresoc.v:190114.9-190114.17" + attribute \src "libresoc.v:192418.9-192418.17" case 1'1 case end @@ -396838,56 +400847,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13172 6'000000 + assign $1\q_int$next[5:0]$13356 6'000000 case - assign $1\q_int$next[5:0]$13172 \$5 + assign $1\q_int$next[5:0]$13356 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13171 + update \q_int$next $0\q_int$next[5:0]$13355 end - connect \$9 $and$libresoc.v:190103$13161_Y - connect \$11 $or$libresoc.v:190104$13162_Y - connect \$13 $not$libresoc.v:190105$13163_Y - connect \$15 $or$libresoc.v:190106$13164_Y - connect \$1 $not$libresoc.v:190107$13165_Y - connect \$3 $and$libresoc.v:190108$13166_Y - connect \$5 $or$libresoc.v:190109$13167_Y - connect \$7 $not$libresoc.v:190110$13168_Y + connect \$9 $and$libresoc.v:192407$13345_Y + connect \$11 $or$libresoc.v:192408$13346_Y + connect \$13 $not$libresoc.v:192409$13347_Y + connect \$15 $or$libresoc.v:192410$13348_Y + connect \$1 $not$libresoc.v:192411$13349_Y + connect \$3 $and$libresoc.v:192412$13350_Y + connect \$5 $or$libresoc.v:192413$13351_Y + connect \$7 $not$libresoc.v:192414$13352_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190129.1-190187.10" +attribute \src "libresoc.v:192433.1-192491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:190130.7-190130.20" + attribute \src "libresoc.v:192434.7-192434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190175.3-190183.6" - wire width 3 $0\q_int$next[2:0]$13185 - attribute \src "libresoc.v:190173.3-190174.27" + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $0\q_int$next[2:0]$13369 + attribute \src "libresoc.v:192477.3-192478.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190175.3-190183.6" - wire width 3 $1\q_int$next[2:0]$13186 - attribute \src "libresoc.v:190152.13-190152.25" + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192456.13-192456.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190165.17-190165.96" - wire width 3 $and$libresoc.v:190165$13175_Y - attribute \src "libresoc.v:190170.17-190170.96" - wire width 3 $and$libresoc.v:190170$13180_Y - attribute \src "libresoc.v:190167.18-190167.93" - wire width 3 $not$libresoc.v:190167$13177_Y - attribute \src "libresoc.v:190169.17-190169.92" - wire width 3 $not$libresoc.v:190169$13179_Y - attribute \src "libresoc.v:190172.17-190172.92" - wire width 3 $not$libresoc.v:190172$13182_Y - attribute \src "libresoc.v:190166.18-190166.98" - wire width 3 $or$libresoc.v:190166$13176_Y - attribute \src "libresoc.v:190168.18-190168.99" - wire width 3 $or$libresoc.v:190168$13178_Y - attribute \src "libresoc.v:190171.17-190171.97" - wire width 3 $or$libresoc.v:190171$13181_Y + attribute \src "libresoc.v:192469.17-192469.96" + wire width 3 $and$libresoc.v:192469$13359_Y + attribute \src "libresoc.v:192474.17-192474.96" + wire width 3 $and$libresoc.v:192474$13364_Y + attribute \src "libresoc.v:192471.18-192471.93" + wire width 3 $not$libresoc.v:192471$13361_Y + attribute \src "libresoc.v:192473.17-192473.92" + wire width 3 $not$libresoc.v:192473$13363_Y + attribute \src "libresoc.v:192476.17-192476.92" + wire width 3 $not$libresoc.v:192476$13366_Y + attribute \src "libresoc.v:192470.18-192470.98" + wire width 3 $or$libresoc.v:192470$13360_Y + attribute \src "libresoc.v:192472.18-192472.99" + wire width 3 $or$libresoc.v:192472$13362_Y + attribute \src "libresoc.v:192475.17-192475.97" + wire width 3 $or$libresoc.v:192475$13365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396904,11 +400913,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190130.7-190130.15" + attribute \src "libresoc.v:192434.7-192434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -396925,7 +400934,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190165$13175 + cell $and $and$libresoc.v:192469$13359 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396933,10 +400942,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190165$13175_Y + connect \Y $and$libresoc.v:192469$13359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190170$13180 + cell $and $and$libresoc.v:192474$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396944,34 +400953,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190170$13180_Y + connect \Y $and$libresoc.v:192474$13364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190167$13177 + cell $not $not$libresoc.v:192471$13361 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190167$13177_Y + connect \Y $not$libresoc.v:192471$13361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190169$13179 + cell $not $not$libresoc.v:192473$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190169$13179_Y + connect \Y $not$libresoc.v:192473$13363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190172$13182 + cell $not $not$libresoc.v:192476$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190172$13182_Y + connect \Y $not$libresoc.v:192476$13366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190166$13176 + cell $or $or$libresoc.v:192470$13360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396979,10 +400988,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190166$13176_Y + connect \Y $or$libresoc.v:192470$13360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190168$13178 + cell $or $or$libresoc.v:192472$13362 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396990,10 +400999,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190168$13178_Y + connect \Y $or$libresoc.v:192472$13362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190171$13181 + cell $or $or$libresoc.v:192475$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397001,39 +401010,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190171$13181_Y + connect \Y $or$libresoc.v:192475$13365_Y end - attribute \src "libresoc.v:190130.7-190130.20" - process $proc$libresoc.v:190130$13187 + attribute \src "libresoc.v:192434.7-192434.20" + process $proc$libresoc.v:192434$13371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190152.13-190152.25" - process $proc$libresoc.v:190152$13188 + attribute \src "libresoc.v:192456.13-192456.25" + process $proc$libresoc.v:192456$13372 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190173.3-190174.27" - process $proc$libresoc.v:190173$13183 + attribute \src "libresoc.v:192477.3-192478.27" + process $proc$libresoc.v:192477$13367 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190175.3-190183.6" - process $proc$libresoc.v:190175$13184 + attribute \src "libresoc.v:192479.3-192487.6" + process $proc$libresoc.v:192479$13368 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186 - attribute \src "libresoc.v:190176.5-190176.29" + assign $0\q_int$next[2:0]$13369 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192480.5-192480.29" switch \initial - attribute \src "libresoc.v:190176.9-190176.17" + attribute \src "libresoc.v:192480.9-192480.17" case 1'1 case end @@ -397042,56 +401051,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13186 3'000 + assign $1\q_int$next[2:0]$13370 3'000 case - assign $1\q_int$next[2:0]$13186 \$5 + assign $1\q_int$next[2:0]$13370 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13185 + update \q_int$next $0\q_int$next[2:0]$13369 end - connect \$9 $and$libresoc.v:190165$13175_Y - connect \$11 $or$libresoc.v:190166$13176_Y - connect \$13 $not$libresoc.v:190167$13177_Y - connect \$15 $or$libresoc.v:190168$13178_Y - connect \$1 $not$libresoc.v:190169$13179_Y - connect \$3 $and$libresoc.v:190170$13180_Y - connect \$5 $or$libresoc.v:190171$13181_Y - connect \$7 $not$libresoc.v:190172$13182_Y + connect \$9 $and$libresoc.v:192469$13359_Y + connect \$11 $or$libresoc.v:192470$13360_Y + connect \$13 $not$libresoc.v:192471$13361_Y + connect \$15 $or$libresoc.v:192472$13362_Y + connect \$1 $not$libresoc.v:192473$13363_Y + connect \$3 $and$libresoc.v:192474$13364_Y + connect \$5 $or$libresoc.v:192475$13365_Y + connect \$7 $not$libresoc.v:192476$13366_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190191.1-190249.10" +attribute \src "libresoc.v:192495.1-192553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:190192.7-190192.20" + attribute \src "libresoc.v:192496.7-192496.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190237.3-190245.6" - wire width 5 $0\q_int$next[4:0]$13199 - attribute \src "libresoc.v:190235.3-190236.27" + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $0\q_int$next[4:0]$13383 + attribute \src "libresoc.v:192539.3-192540.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:190237.3-190245.6" - wire width 5 $1\q_int$next[4:0]$13200 - attribute \src "libresoc.v:190214.13-190214.26" + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $1\q_int$next[4:0]$13384 + attribute \src "libresoc.v:192518.13-192518.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:190227.17-190227.96" - wire width 5 $and$libresoc.v:190227$13189_Y - attribute \src "libresoc.v:190232.17-190232.96" - wire width 5 $and$libresoc.v:190232$13194_Y - attribute \src "libresoc.v:190229.18-190229.93" - wire width 5 $not$libresoc.v:190229$13191_Y - attribute \src "libresoc.v:190231.17-190231.92" - wire width 5 $not$libresoc.v:190231$13193_Y - attribute \src "libresoc.v:190234.17-190234.92" - wire width 5 $not$libresoc.v:190234$13196_Y - attribute \src "libresoc.v:190228.18-190228.98" - wire width 5 $or$libresoc.v:190228$13190_Y - attribute \src "libresoc.v:190230.18-190230.99" - wire width 5 $or$libresoc.v:190230$13192_Y - attribute \src "libresoc.v:190233.17-190233.97" - wire width 5 $or$libresoc.v:190233$13195_Y + attribute \src "libresoc.v:192531.17-192531.96" + wire width 5 $and$libresoc.v:192531$13373_Y + attribute \src "libresoc.v:192536.17-192536.96" + wire width 5 $and$libresoc.v:192536$13378_Y + attribute \src "libresoc.v:192533.18-192533.93" + wire width 5 $not$libresoc.v:192533$13375_Y + attribute \src "libresoc.v:192535.17-192535.92" + wire width 5 $not$libresoc.v:192535$13377_Y + attribute \src "libresoc.v:192538.17-192538.92" + wire width 5 $not$libresoc.v:192538$13380_Y + attribute \src "libresoc.v:192532.18-192532.98" + wire width 5 $or$libresoc.v:192532$13374_Y + attribute \src "libresoc.v:192534.18-192534.99" + wire width 5 $or$libresoc.v:192534$13376_Y + attribute \src "libresoc.v:192537.17-192537.97" + wire width 5 $or$libresoc.v:192537$13379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397108,11 +401117,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190192.7-190192.15" + attribute \src "libresoc.v:192496.7-192496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -397129,7 +401138,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190227$13189 + cell $and $and$libresoc.v:192531$13373 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397137,10 +401146,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190227$13189_Y + connect \Y $and$libresoc.v:192531$13373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190232$13194 + cell $and $and$libresoc.v:192536$13378 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397148,34 +401157,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190232$13194_Y + connect \Y $and$libresoc.v:192536$13378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190229$13191 + cell $not $not$libresoc.v:192533$13375 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:190229$13191_Y + connect \Y $not$libresoc.v:192533$13375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190231$13193 + cell $not $not$libresoc.v:192535$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:190231$13193_Y + connect \Y $not$libresoc.v:192535$13377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190234$13196 + cell $not $not$libresoc.v:192538$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:190234$13196_Y + connect \Y $not$libresoc.v:192538$13380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190228$13190 + cell $or $or$libresoc.v:192532$13374 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397183,10 +401192,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190228$13190_Y + connect \Y $or$libresoc.v:192532$13374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190230$13192 + cell $or $or$libresoc.v:192534$13376 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397194,10 +401203,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190230$13192_Y + connect \Y $or$libresoc.v:192534$13376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190233$13195 + cell $or $or$libresoc.v:192537$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397205,39 +401214,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190233$13195_Y + connect \Y $or$libresoc.v:192537$13379_Y end - attribute \src "libresoc.v:190192.7-190192.20" - process $proc$libresoc.v:190192$13201 + attribute \src "libresoc.v:192496.7-192496.20" + process $proc$libresoc.v:192496$13385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190214.13-190214.26" - process $proc$libresoc.v:190214$13202 + attribute \src "libresoc.v:192518.13-192518.26" + process $proc$libresoc.v:192518$13386 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:190235.3-190236.27" - process $proc$libresoc.v:190235$13197 + attribute \src "libresoc.v:192539.3-192540.27" + process $proc$libresoc.v:192539$13381 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:190237.3-190245.6" - process $proc$libresoc.v:190237$13198 + attribute \src "libresoc.v:192541.3-192549.6" + process $proc$libresoc.v:192541$13382 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13199 $1\q_int$next[4:0]$13200 - attribute \src "libresoc.v:190238.5-190238.29" + assign $0\q_int$next[4:0]$13383 $1\q_int$next[4:0]$13384 + attribute \src "libresoc.v:192542.5-192542.29" switch \initial - attribute \src "libresoc.v:190238.9-190238.17" + attribute \src "libresoc.v:192542.9-192542.17" case 1'1 case end @@ -397246,56 +401255,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13200 5'00000 + assign $1\q_int$next[4:0]$13384 5'00000 case - assign $1\q_int$next[4:0]$13200 \$5 + assign $1\q_int$next[4:0]$13384 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13199 + update \q_int$next $0\q_int$next[4:0]$13383 end - connect \$9 $and$libresoc.v:190227$13189_Y - connect \$11 $or$libresoc.v:190228$13190_Y - connect \$13 $not$libresoc.v:190229$13191_Y - connect \$15 $or$libresoc.v:190230$13192_Y - connect \$1 $not$libresoc.v:190231$13193_Y - connect \$3 $and$libresoc.v:190232$13194_Y - connect \$5 $or$libresoc.v:190233$13195_Y - connect \$7 $not$libresoc.v:190234$13196_Y + connect \$9 $and$libresoc.v:192531$13373_Y + connect \$11 $or$libresoc.v:192532$13374_Y + connect \$13 $not$libresoc.v:192533$13375_Y + connect \$15 $or$libresoc.v:192534$13376_Y + connect \$1 $not$libresoc.v:192535$13377_Y + connect \$3 $and$libresoc.v:192536$13378_Y + connect \$5 $or$libresoc.v:192537$13379_Y + connect \$7 $not$libresoc.v:192538$13380_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190253.1-190311.10" +attribute \src "libresoc.v:192557.1-192615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:190254.7-190254.20" + attribute \src "libresoc.v:192558.7-192558.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190299.3-190307.6" - wire width 3 $0\q_int$next[2:0]$13213 - attribute \src "libresoc.v:190297.3-190298.27" + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $0\q_int$next[2:0]$13397 + attribute \src "libresoc.v:192601.3-192602.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190299.3-190307.6" - wire width 3 $1\q_int$next[2:0]$13214 - attribute \src "libresoc.v:190276.13-190276.25" + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192580.13-192580.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190289.17-190289.96" - wire width 3 $and$libresoc.v:190289$13203_Y - attribute \src "libresoc.v:190294.17-190294.96" - wire width 3 $and$libresoc.v:190294$13208_Y - attribute \src "libresoc.v:190291.18-190291.93" - wire width 3 $not$libresoc.v:190291$13205_Y - attribute \src "libresoc.v:190293.17-190293.92" - wire width 3 $not$libresoc.v:190293$13207_Y - attribute \src "libresoc.v:190296.17-190296.92" - wire width 3 $not$libresoc.v:190296$13210_Y - attribute \src "libresoc.v:190290.18-190290.98" - wire width 3 $or$libresoc.v:190290$13204_Y - attribute \src "libresoc.v:190292.18-190292.99" - wire width 3 $or$libresoc.v:190292$13206_Y - attribute \src "libresoc.v:190295.17-190295.97" - wire width 3 $or$libresoc.v:190295$13209_Y + attribute \src "libresoc.v:192593.17-192593.96" + wire width 3 $and$libresoc.v:192593$13387_Y + attribute \src "libresoc.v:192598.17-192598.96" + wire width 3 $and$libresoc.v:192598$13392_Y + attribute \src "libresoc.v:192595.18-192595.93" + wire width 3 $not$libresoc.v:192595$13389_Y + attribute \src "libresoc.v:192597.17-192597.92" + wire width 3 $not$libresoc.v:192597$13391_Y + attribute \src "libresoc.v:192600.17-192600.92" + wire width 3 $not$libresoc.v:192600$13394_Y + attribute \src "libresoc.v:192594.18-192594.98" + wire width 3 $or$libresoc.v:192594$13388_Y + attribute \src "libresoc.v:192596.18-192596.99" + wire width 3 $or$libresoc.v:192596$13390_Y + attribute \src "libresoc.v:192599.17-192599.97" + wire width 3 $or$libresoc.v:192599$13393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397312,11 +401321,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190254.7-190254.15" + attribute \src "libresoc.v:192558.7-192558.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397333,7 +401342,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190289$13203 + cell $and $and$libresoc.v:192593$13387 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397341,10 +401350,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190289$13203_Y + connect \Y $and$libresoc.v:192593$13387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190294$13208 + cell $and $and$libresoc.v:192598$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397352,34 +401361,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190294$13208_Y + connect \Y $and$libresoc.v:192598$13392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190291$13205 + cell $not $not$libresoc.v:192595$13389 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190291$13205_Y + connect \Y $not$libresoc.v:192595$13389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190293$13207 + cell $not $not$libresoc.v:192597$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190293$13207_Y + connect \Y $not$libresoc.v:192597$13391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190296$13210 + cell $not $not$libresoc.v:192600$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190296$13210_Y + connect \Y $not$libresoc.v:192600$13394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190290$13204 + cell $or $or$libresoc.v:192594$13388 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397387,10 +401396,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190290$13204_Y + connect \Y $or$libresoc.v:192594$13388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190292$13206 + cell $or $or$libresoc.v:192596$13390 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397398,10 +401407,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190292$13206_Y + connect \Y $or$libresoc.v:192596$13390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190295$13209 + cell $or $or$libresoc.v:192599$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397409,39 +401418,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190295$13209_Y + connect \Y $or$libresoc.v:192599$13393_Y end - attribute \src "libresoc.v:190254.7-190254.20" - process $proc$libresoc.v:190254$13215 + attribute \src "libresoc.v:192558.7-192558.20" + process $proc$libresoc.v:192558$13399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190276.13-190276.25" - process $proc$libresoc.v:190276$13216 + attribute \src "libresoc.v:192580.13-192580.25" + process $proc$libresoc.v:192580$13400 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190297.3-190298.27" - process $proc$libresoc.v:190297$13211 + attribute \src "libresoc.v:192601.3-192602.27" + process $proc$libresoc.v:192601$13395 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190299.3-190307.6" - process $proc$libresoc.v:190299$13212 + attribute \src "libresoc.v:192603.3-192611.6" + process $proc$libresoc.v:192603$13396 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214 - attribute \src "libresoc.v:190300.5-190300.29" + assign $0\q_int$next[2:0]$13397 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192604.5-192604.29" switch \initial - attribute \src "libresoc.v:190300.9-190300.17" + attribute \src "libresoc.v:192604.9-192604.17" case 1'1 case end @@ -397450,56 +401459,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13214 3'000 + assign $1\q_int$next[2:0]$13398 3'000 case - assign $1\q_int$next[2:0]$13214 \$5 + assign $1\q_int$next[2:0]$13398 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13213 + update \q_int$next $0\q_int$next[2:0]$13397 end - connect \$9 $and$libresoc.v:190289$13203_Y - connect \$11 $or$libresoc.v:190290$13204_Y - connect \$13 $not$libresoc.v:190291$13205_Y - connect \$15 $or$libresoc.v:190292$13206_Y - connect \$1 $not$libresoc.v:190293$13207_Y - connect \$3 $and$libresoc.v:190294$13208_Y - connect \$5 $or$libresoc.v:190295$13209_Y - connect \$7 $not$libresoc.v:190296$13210_Y + connect \$9 $and$libresoc.v:192593$13387_Y + connect \$11 $or$libresoc.v:192594$13388_Y + connect \$13 $not$libresoc.v:192595$13389_Y + connect \$15 $or$libresoc.v:192596$13390_Y + connect \$1 $not$libresoc.v:192597$13391_Y + connect \$3 $and$libresoc.v:192598$13392_Y + connect \$5 $or$libresoc.v:192599$13393_Y + connect \$7 $not$libresoc.v:192600$13394_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190315.1-190373.10" +attribute \src "libresoc.v:192619.1-192677.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:190316.7-190316.20" + attribute \src "libresoc.v:192620.7-192620.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190361.3-190369.6" - wire width 3 $0\q_int$next[2:0]$13227 - attribute \src "libresoc.v:190359.3-190360.27" + attribute \src "libresoc.v:192665.3-192673.6" + wire width 3 $0\q_int$next[2:0]$13411 + attribute \src "libresoc.v:192663.3-192664.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190361.3-190369.6" - wire width 3 $1\q_int$next[2:0]$13228 - attribute \src "libresoc.v:190338.13-190338.25" + attribute \src "libresoc.v:192665.3-192673.6" + wire width 3 $1\q_int$next[2:0]$13412 + attribute \src "libresoc.v:192642.13-192642.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190351.17-190351.96" - wire width 3 $and$libresoc.v:190351$13217_Y - attribute \src "libresoc.v:190356.17-190356.96" - wire width 3 $and$libresoc.v:190356$13222_Y - attribute \src "libresoc.v:190353.18-190353.93" - wire width 3 $not$libresoc.v:190353$13219_Y - attribute \src "libresoc.v:190355.17-190355.92" - wire width 3 $not$libresoc.v:190355$13221_Y - attribute \src "libresoc.v:190358.17-190358.92" - wire width 3 $not$libresoc.v:190358$13224_Y - attribute \src "libresoc.v:190352.18-190352.98" - wire width 3 $or$libresoc.v:190352$13218_Y - attribute \src "libresoc.v:190354.18-190354.99" - wire width 3 $or$libresoc.v:190354$13220_Y - attribute \src "libresoc.v:190357.17-190357.97" - wire width 3 $or$libresoc.v:190357$13223_Y + attribute \src "libresoc.v:192655.17-192655.96" + wire width 3 $and$libresoc.v:192655$13401_Y + attribute \src "libresoc.v:192660.17-192660.96" + wire width 3 $and$libresoc.v:192660$13406_Y + attribute \src "libresoc.v:192657.18-192657.93" + wire width 3 $not$libresoc.v:192657$13403_Y + attribute \src "libresoc.v:192659.17-192659.92" + wire width 3 $not$libresoc.v:192659$13405_Y + attribute \src "libresoc.v:192662.17-192662.92" + wire width 3 $not$libresoc.v:192662$13408_Y + attribute \src "libresoc.v:192656.18-192656.98" + wire width 3 $or$libresoc.v:192656$13402_Y + attribute \src "libresoc.v:192658.18-192658.99" + wire width 3 $or$libresoc.v:192658$13404_Y + attribute \src "libresoc.v:192661.17-192661.97" + wire width 3 $or$libresoc.v:192661$13407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397516,11 +401525,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190316.7-190316.15" + attribute \src "libresoc.v:192620.7-192620.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397537,7 +401546,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190351$13217 + cell $and $and$libresoc.v:192655$13401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397545,10 +401554,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190351$13217_Y + connect \Y $and$libresoc.v:192655$13401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190356$13222 + cell $and $and$libresoc.v:192660$13406 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397556,34 +401565,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190356$13222_Y + connect \Y $and$libresoc.v:192660$13406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190353$13219 + cell $not $not$libresoc.v:192657$13403 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190353$13219_Y + connect \Y $not$libresoc.v:192657$13403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190355$13221 + cell $not $not$libresoc.v:192659$13405 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190355$13221_Y + connect \Y $not$libresoc.v:192659$13405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190358$13224 + cell $not $not$libresoc.v:192662$13408 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190358$13224_Y + connect \Y $not$libresoc.v:192662$13408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190352$13218 + cell $or $or$libresoc.v:192656$13402 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397591,10 +401600,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190352$13218_Y + connect \Y $or$libresoc.v:192656$13402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190354$13220 + cell $or $or$libresoc.v:192658$13404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397602,10 +401611,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190354$13220_Y + connect \Y $or$libresoc.v:192658$13404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190357$13223 + cell $or $or$libresoc.v:192661$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397613,39 +401622,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190357$13223_Y + connect \Y $or$libresoc.v:192661$13407_Y end - attribute \src "libresoc.v:190316.7-190316.20" - process $proc$libresoc.v:190316$13229 + attribute \src "libresoc.v:192620.7-192620.20" + process $proc$libresoc.v:192620$13413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190338.13-190338.25" - process $proc$libresoc.v:190338$13230 + attribute \src "libresoc.v:192642.13-192642.25" + process $proc$libresoc.v:192642$13414 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190359.3-190360.27" - process $proc$libresoc.v:190359$13225 + attribute \src "libresoc.v:192663.3-192664.27" + process $proc$libresoc.v:192663$13409 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190361.3-190369.6" - process $proc$libresoc.v:190361$13226 + attribute \src "libresoc.v:192665.3-192673.6" + process $proc$libresoc.v:192665$13410 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13227 $1\q_int$next[2:0]$13228 - attribute \src "libresoc.v:190362.5-190362.29" + assign $0\q_int$next[2:0]$13411 $1\q_int$next[2:0]$13412 + attribute \src "libresoc.v:192666.5-192666.29" switch \initial - attribute \src "libresoc.v:190362.9-190362.17" + attribute \src "libresoc.v:192666.9-192666.17" case 1'1 case end @@ -397654,56 +401663,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13228 3'000 + assign $1\q_int$next[2:0]$13412 3'000 case - assign $1\q_int$next[2:0]$13228 \$5 + assign $1\q_int$next[2:0]$13412 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13227 + update \q_int$next $0\q_int$next[2:0]$13411 end - connect \$9 $and$libresoc.v:190351$13217_Y - connect \$11 $or$libresoc.v:190352$13218_Y - connect \$13 $not$libresoc.v:190353$13219_Y - connect \$15 $or$libresoc.v:190354$13220_Y - connect \$1 $not$libresoc.v:190355$13221_Y - connect \$3 $and$libresoc.v:190356$13222_Y - connect \$5 $or$libresoc.v:190357$13223_Y - connect \$7 $not$libresoc.v:190358$13224_Y + connect \$9 $and$libresoc.v:192655$13401_Y + connect \$11 $or$libresoc.v:192656$13402_Y + connect \$13 $not$libresoc.v:192657$13403_Y + connect \$15 $or$libresoc.v:192658$13404_Y + connect \$1 $not$libresoc.v:192659$13405_Y + connect \$3 $and$libresoc.v:192660$13406_Y + connect \$5 $or$libresoc.v:192661$13407_Y + connect \$7 $not$libresoc.v:192662$13408_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190377.1-190435.10" +attribute \src "libresoc.v:192681.1-192739.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:190378.7-190378.20" + attribute \src "libresoc.v:192682.7-192682.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190423.3-190431.6" - wire width 4 $0\q_int$next[3:0]$13241 - attribute \src "libresoc.v:190421.3-190422.27" + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $0\q_int$next[3:0]$13425 + attribute \src "libresoc.v:192725.3-192726.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:190423.3-190431.6" - wire width 4 $1\q_int$next[3:0]$13242 - attribute \src "libresoc.v:190400.13-190400.25" + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192704.13-192704.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:190413.17-190413.96" - wire width 4 $and$libresoc.v:190413$13231_Y - attribute \src "libresoc.v:190418.17-190418.96" - wire width 4 $and$libresoc.v:190418$13236_Y - attribute \src "libresoc.v:190415.18-190415.93" - wire width 4 $not$libresoc.v:190415$13233_Y - attribute \src "libresoc.v:190417.17-190417.92" - wire width 4 $not$libresoc.v:190417$13235_Y - attribute \src "libresoc.v:190420.17-190420.92" - wire width 4 $not$libresoc.v:190420$13238_Y - attribute \src "libresoc.v:190414.18-190414.98" - wire width 4 $or$libresoc.v:190414$13232_Y - attribute \src "libresoc.v:190416.18-190416.99" - wire width 4 $or$libresoc.v:190416$13234_Y - attribute \src "libresoc.v:190419.17-190419.97" - wire width 4 $or$libresoc.v:190419$13237_Y + attribute \src "libresoc.v:192717.17-192717.96" + wire width 4 $and$libresoc.v:192717$13415_Y + attribute \src "libresoc.v:192722.17-192722.96" + wire width 4 $and$libresoc.v:192722$13420_Y + attribute \src "libresoc.v:192719.18-192719.93" + wire width 4 $not$libresoc.v:192719$13417_Y + attribute \src "libresoc.v:192721.17-192721.92" + wire width 4 $not$libresoc.v:192721$13419_Y + attribute \src "libresoc.v:192724.17-192724.92" + wire width 4 $not$libresoc.v:192724$13422_Y + attribute \src "libresoc.v:192718.18-192718.98" + wire width 4 $or$libresoc.v:192718$13416_Y + attribute \src "libresoc.v:192720.18-192720.99" + wire width 4 $or$libresoc.v:192720$13418_Y + attribute \src "libresoc.v:192723.17-192723.97" + wire width 4 $or$libresoc.v:192723$13421_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397720,11 +401729,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190378.7-190378.15" + attribute \src "libresoc.v:192682.7-192682.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -397741,7 +401750,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190413$13231 + cell $and $and$libresoc.v:192717$13415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397749,10 +401758,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190413$13231_Y + connect \Y $and$libresoc.v:192717$13415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190418$13236 + cell $and $and$libresoc.v:192722$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397760,34 +401769,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190418$13236_Y + connect \Y $and$libresoc.v:192722$13420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190415$13233 + cell $not $not$libresoc.v:192719$13417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:190415$13233_Y + connect \Y $not$libresoc.v:192719$13417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190417$13235 + cell $not $not$libresoc.v:192721$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190417$13235_Y + connect \Y $not$libresoc.v:192721$13419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190420$13238 + cell $not $not$libresoc.v:192724$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190420$13238_Y + connect \Y $not$libresoc.v:192724$13422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190414$13232 + cell $or $or$libresoc.v:192718$13416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397795,10 +401804,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190414$13232_Y + connect \Y $or$libresoc.v:192718$13416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190416$13234 + cell $or $or$libresoc.v:192720$13418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397806,10 +401815,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190416$13234_Y + connect \Y $or$libresoc.v:192720$13418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190419$13237 + cell $or $or$libresoc.v:192723$13421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397817,39 +401826,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190419$13237_Y + connect \Y $or$libresoc.v:192723$13421_Y end - attribute \src "libresoc.v:190378.7-190378.20" - process $proc$libresoc.v:190378$13243 + attribute \src "libresoc.v:192682.7-192682.20" + process $proc$libresoc.v:192682$13427 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190400.13-190400.25" - process $proc$libresoc.v:190400$13244 + attribute \src "libresoc.v:192704.13-192704.25" + process $proc$libresoc.v:192704$13428 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:190421.3-190422.27" - process $proc$libresoc.v:190421$13239 + attribute \src "libresoc.v:192725.3-192726.27" + process $proc$libresoc.v:192725$13423 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:190423.3-190431.6" - process $proc$libresoc.v:190423$13240 + attribute \src "libresoc.v:192727.3-192735.6" + process $proc$libresoc.v:192727$13424 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13241 $1\q_int$next[3:0]$13242 - attribute \src "libresoc.v:190424.5-190424.29" + assign $0\q_int$next[3:0]$13425 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192728.5-192728.29" switch \initial - attribute \src "libresoc.v:190424.9-190424.17" + attribute \src "libresoc.v:192728.9-192728.17" case 1'1 case end @@ -397858,56 +401867,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13242 4'0000 + assign $1\q_int$next[3:0]$13426 4'0000 case - assign $1\q_int$next[3:0]$13242 \$5 + assign $1\q_int$next[3:0]$13426 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13241 + update \q_int$next $0\q_int$next[3:0]$13425 end - connect \$9 $and$libresoc.v:190413$13231_Y - connect \$11 $or$libresoc.v:190414$13232_Y - connect \$13 $not$libresoc.v:190415$13233_Y - connect \$15 $or$libresoc.v:190416$13234_Y - connect \$1 $not$libresoc.v:190417$13235_Y - connect \$3 $and$libresoc.v:190418$13236_Y - connect \$5 $or$libresoc.v:190419$13237_Y - connect \$7 $not$libresoc.v:190420$13238_Y + connect \$9 $and$libresoc.v:192717$13415_Y + connect \$11 $or$libresoc.v:192718$13416_Y + connect \$13 $not$libresoc.v:192719$13417_Y + connect \$15 $or$libresoc.v:192720$13418_Y + connect \$1 $not$libresoc.v:192721$13419_Y + connect \$3 $and$libresoc.v:192722$13420_Y + connect \$5 $or$libresoc.v:192723$13421_Y + connect \$7 $not$libresoc.v:192724$13422_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190439.1-190497.10" +attribute \src "libresoc.v:192743.1-192801.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:190440.7-190440.20" + attribute \src "libresoc.v:192744.7-192744.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190485.3-190493.6" - wire width 3 $0\q_int$next[2:0]$13255 - attribute \src "libresoc.v:190483.3-190484.27" + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $0\q_int$next[2:0]$13439 + attribute \src "libresoc.v:192787.3-192788.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190485.3-190493.6" - wire width 3 $1\q_int$next[2:0]$13256 - attribute \src "libresoc.v:190462.13-190462.25" + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192766.13-192766.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190475.17-190475.96" - wire width 3 $and$libresoc.v:190475$13245_Y - attribute \src "libresoc.v:190480.17-190480.96" - wire width 3 $and$libresoc.v:190480$13250_Y - attribute \src "libresoc.v:190477.18-190477.93" - wire width 3 $not$libresoc.v:190477$13247_Y - attribute \src "libresoc.v:190479.17-190479.92" - wire width 3 $not$libresoc.v:190479$13249_Y - attribute \src "libresoc.v:190482.17-190482.92" - wire width 3 $not$libresoc.v:190482$13252_Y - attribute \src "libresoc.v:190476.18-190476.98" - wire width 3 $or$libresoc.v:190476$13246_Y - attribute \src "libresoc.v:190478.18-190478.99" - wire width 3 $or$libresoc.v:190478$13248_Y - attribute \src "libresoc.v:190481.17-190481.97" - wire width 3 $or$libresoc.v:190481$13251_Y + attribute \src "libresoc.v:192779.17-192779.96" + wire width 3 $and$libresoc.v:192779$13429_Y + attribute \src "libresoc.v:192784.17-192784.96" + wire width 3 $and$libresoc.v:192784$13434_Y + attribute \src "libresoc.v:192781.18-192781.93" + wire width 3 $not$libresoc.v:192781$13431_Y + attribute \src "libresoc.v:192783.17-192783.92" + wire width 3 $not$libresoc.v:192783$13433_Y + attribute \src "libresoc.v:192786.17-192786.92" + wire width 3 $not$libresoc.v:192786$13436_Y + attribute \src "libresoc.v:192780.18-192780.98" + wire width 3 $or$libresoc.v:192780$13430_Y + attribute \src "libresoc.v:192782.18-192782.99" + wire width 3 $or$libresoc.v:192782$13432_Y + attribute \src "libresoc.v:192785.17-192785.97" + wire width 3 $or$libresoc.v:192785$13435_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397924,11 +401933,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190440.7-190440.15" + attribute \src "libresoc.v:192744.7-192744.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397945,7 +401954,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190475$13245 + cell $and $and$libresoc.v:192779$13429 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397953,10 +401962,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190475$13245_Y + connect \Y $and$libresoc.v:192779$13429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190480$13250 + cell $and $and$libresoc.v:192784$13434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397964,34 +401973,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190480$13250_Y + connect \Y $and$libresoc.v:192784$13434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190477$13247 + cell $not $not$libresoc.v:192781$13431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190477$13247_Y + connect \Y $not$libresoc.v:192781$13431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190479$13249 + cell $not $not$libresoc.v:192783$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190479$13249_Y + connect \Y $not$libresoc.v:192783$13433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190482$13252 + cell $not $not$libresoc.v:192786$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190482$13252_Y + connect \Y $not$libresoc.v:192786$13436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190476$13246 + cell $or $or$libresoc.v:192780$13430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397999,10 +402008,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190476$13246_Y + connect \Y $or$libresoc.v:192780$13430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190478$13248 + cell $or $or$libresoc.v:192782$13432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398010,10 +402019,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190478$13248_Y + connect \Y $or$libresoc.v:192782$13432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190481$13251 + cell $or $or$libresoc.v:192785$13435 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398021,39 +402030,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190481$13251_Y + connect \Y $or$libresoc.v:192785$13435_Y end - attribute \src "libresoc.v:190440.7-190440.20" - process $proc$libresoc.v:190440$13257 + attribute \src "libresoc.v:192744.7-192744.20" + process $proc$libresoc.v:192744$13441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190462.13-190462.25" - process $proc$libresoc.v:190462$13258 + attribute \src "libresoc.v:192766.13-192766.25" + process $proc$libresoc.v:192766$13442 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190483.3-190484.27" - process $proc$libresoc.v:190483$13253 + attribute \src "libresoc.v:192787.3-192788.27" + process $proc$libresoc.v:192787$13437 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190485.3-190493.6" - process $proc$libresoc.v:190485$13254 + attribute \src "libresoc.v:192789.3-192797.6" + process $proc$libresoc.v:192789$13438 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13255 $1\q_int$next[2:0]$13256 - attribute \src "libresoc.v:190486.5-190486.29" + assign $0\q_int$next[2:0]$13439 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192790.5-192790.29" switch \initial - attribute \src "libresoc.v:190486.9-190486.17" + attribute \src "libresoc.v:192790.9-192790.17" case 1'1 case end @@ -398062,56 +402071,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13256 3'000 + assign $1\q_int$next[2:0]$13440 3'000 case - assign $1\q_int$next[2:0]$13256 \$5 + assign $1\q_int$next[2:0]$13440 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13255 + update \q_int$next $0\q_int$next[2:0]$13439 end - connect \$9 $and$libresoc.v:190475$13245_Y - connect \$11 $or$libresoc.v:190476$13246_Y - connect \$13 $not$libresoc.v:190477$13247_Y - connect \$15 $or$libresoc.v:190478$13248_Y - connect \$1 $not$libresoc.v:190479$13249_Y - connect \$3 $and$libresoc.v:190480$13250_Y - connect \$5 $or$libresoc.v:190481$13251_Y - connect \$7 $not$libresoc.v:190482$13252_Y + connect \$9 $and$libresoc.v:192779$13429_Y + connect \$11 $or$libresoc.v:192780$13430_Y + connect \$13 $not$libresoc.v:192781$13431_Y + connect \$15 $or$libresoc.v:192782$13432_Y + connect \$1 $not$libresoc.v:192783$13433_Y + connect \$3 $and$libresoc.v:192784$13434_Y + connect \$5 $or$libresoc.v:192785$13435_Y + connect \$7 $not$libresoc.v:192786$13436_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190501.1-190559.10" +attribute \src "libresoc.v:192805.1-192863.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:190502.7-190502.20" + attribute \src "libresoc.v:192806.7-192806.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190547.3-190555.6" - wire width 6 $0\q_int$next[5:0]$13269 - attribute \src "libresoc.v:190545.3-190546.27" + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $0\q_int$next[5:0]$13453 + attribute \src "libresoc.v:192849.3-192850.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:190547.3-190555.6" - wire width 6 $1\q_int$next[5:0]$13270 - attribute \src "libresoc.v:190524.13-190524.26" + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192828.13-192828.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:190537.17-190537.96" - wire width 6 $and$libresoc.v:190537$13259_Y - attribute \src "libresoc.v:190542.17-190542.96" - wire width 6 $and$libresoc.v:190542$13264_Y - attribute \src "libresoc.v:190539.18-190539.93" - wire width 6 $not$libresoc.v:190539$13261_Y - attribute \src "libresoc.v:190541.17-190541.92" - wire width 6 $not$libresoc.v:190541$13263_Y - attribute \src "libresoc.v:190544.17-190544.92" - wire width 6 $not$libresoc.v:190544$13266_Y - attribute \src "libresoc.v:190538.18-190538.98" - wire width 6 $or$libresoc.v:190538$13260_Y - attribute \src "libresoc.v:190540.18-190540.99" - wire width 6 $or$libresoc.v:190540$13262_Y - attribute \src "libresoc.v:190543.17-190543.97" - wire width 6 $or$libresoc.v:190543$13265_Y + attribute \src "libresoc.v:192841.17-192841.96" + wire width 6 $and$libresoc.v:192841$13443_Y + attribute \src "libresoc.v:192846.17-192846.96" + wire width 6 $and$libresoc.v:192846$13448_Y + attribute \src "libresoc.v:192843.18-192843.93" + wire width 6 $not$libresoc.v:192843$13445_Y + attribute \src "libresoc.v:192845.17-192845.92" + wire width 6 $not$libresoc.v:192845$13447_Y + attribute \src "libresoc.v:192848.17-192848.92" + wire width 6 $not$libresoc.v:192848$13450_Y + attribute \src "libresoc.v:192842.18-192842.98" + wire width 6 $or$libresoc.v:192842$13444_Y + attribute \src "libresoc.v:192844.18-192844.99" + wire width 6 $or$libresoc.v:192844$13446_Y + attribute \src "libresoc.v:192847.17-192847.97" + wire width 6 $or$libresoc.v:192847$13449_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398128,11 +402137,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190502.7-190502.15" + attribute \src "libresoc.v:192806.7-192806.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -398149,7 +402158,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190537$13259 + cell $and $and$libresoc.v:192841$13443 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398157,10 +402166,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190537$13259_Y + connect \Y $and$libresoc.v:192841$13443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190542$13264 + cell $and $and$libresoc.v:192846$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398168,34 +402177,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190542$13264_Y + connect \Y $and$libresoc.v:192846$13448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190539$13261 + cell $not $not$libresoc.v:192843$13445 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:190539$13261_Y + connect \Y $not$libresoc.v:192843$13445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190541$13263 + cell $not $not$libresoc.v:192845$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190541$13263_Y + connect \Y $not$libresoc.v:192845$13447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190544$13266 + cell $not $not$libresoc.v:192848$13450 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190544$13266_Y + connect \Y $not$libresoc.v:192848$13450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190538$13260 + cell $or $or$libresoc.v:192842$13444 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398203,10 +402212,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190538$13260_Y + connect \Y $or$libresoc.v:192842$13444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190540$13262 + cell $or $or$libresoc.v:192844$13446 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398214,10 +402223,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190540$13262_Y + connect \Y $or$libresoc.v:192844$13446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190543$13265 + cell $or $or$libresoc.v:192847$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398225,39 +402234,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190543$13265_Y + connect \Y $or$libresoc.v:192847$13449_Y end - attribute \src "libresoc.v:190502.7-190502.20" - process $proc$libresoc.v:190502$13271 + attribute \src "libresoc.v:192806.7-192806.20" + process $proc$libresoc.v:192806$13455 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190524.13-190524.26" - process $proc$libresoc.v:190524$13272 + attribute \src "libresoc.v:192828.13-192828.26" + process $proc$libresoc.v:192828$13456 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:190545.3-190546.27" - process $proc$libresoc.v:190545$13267 + attribute \src "libresoc.v:192849.3-192850.27" + process $proc$libresoc.v:192849$13451 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:190547.3-190555.6" - process $proc$libresoc.v:190547$13268 + attribute \src "libresoc.v:192851.3-192859.6" + process $proc$libresoc.v:192851$13452 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13269 $1\q_int$next[5:0]$13270 - attribute \src "libresoc.v:190548.5-190548.29" + assign $0\q_int$next[5:0]$13453 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192852.5-192852.29" switch \initial - attribute \src "libresoc.v:190548.9-190548.17" + attribute \src "libresoc.v:192852.9-192852.17" case 1'1 case end @@ -398266,56 +402275,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13270 6'000000 + assign $1\q_int$next[5:0]$13454 6'000000 case - assign $1\q_int$next[5:0]$13270 \$5 + assign $1\q_int$next[5:0]$13454 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13269 + update \q_int$next $0\q_int$next[5:0]$13453 end - connect \$9 $and$libresoc.v:190537$13259_Y - connect \$11 $or$libresoc.v:190538$13260_Y - connect \$13 $not$libresoc.v:190539$13261_Y - connect \$15 $or$libresoc.v:190540$13262_Y - connect \$1 $not$libresoc.v:190541$13263_Y - connect \$3 $and$libresoc.v:190542$13264_Y - connect \$5 $or$libresoc.v:190543$13265_Y - connect \$7 $not$libresoc.v:190544$13266_Y + connect \$9 $and$libresoc.v:192841$13443_Y + connect \$11 $or$libresoc.v:192842$13444_Y + connect \$13 $not$libresoc.v:192843$13445_Y + connect \$15 $or$libresoc.v:192844$13446_Y + connect \$1 $not$libresoc.v:192845$13447_Y + connect \$3 $and$libresoc.v:192846$13448_Y + connect \$5 $or$libresoc.v:192847$13449_Y + connect \$7 $not$libresoc.v:192848$13450_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190563.1-190621.10" +attribute \src "libresoc.v:192867.1-192925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:190564.7-190564.20" + attribute \src "libresoc.v:192868.7-192868.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190609.3-190617.6" - wire width 3 $0\q_int$next[2:0]$13283 - attribute \src "libresoc.v:190607.3-190608.27" + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $0\q_int$next[2:0]$13467 + attribute \src "libresoc.v:192911.3-192912.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190609.3-190617.6" - wire width 3 $1\q_int$next[2:0]$13284 - attribute \src "libresoc.v:190586.13-190586.25" + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192890.13-192890.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190599.17-190599.96" - wire width 3 $and$libresoc.v:190599$13273_Y - attribute \src "libresoc.v:190604.17-190604.96" - wire width 3 $and$libresoc.v:190604$13278_Y - attribute \src "libresoc.v:190601.18-190601.93" - wire width 3 $not$libresoc.v:190601$13275_Y - attribute \src "libresoc.v:190603.17-190603.92" - wire width 3 $not$libresoc.v:190603$13277_Y - attribute \src "libresoc.v:190606.17-190606.92" - wire width 3 $not$libresoc.v:190606$13280_Y - attribute \src "libresoc.v:190600.18-190600.98" - wire width 3 $or$libresoc.v:190600$13274_Y - attribute \src "libresoc.v:190602.18-190602.99" - wire width 3 $or$libresoc.v:190602$13276_Y - attribute \src "libresoc.v:190605.17-190605.97" - wire width 3 $or$libresoc.v:190605$13279_Y + attribute \src "libresoc.v:192903.17-192903.96" + wire width 3 $and$libresoc.v:192903$13457_Y + attribute \src "libresoc.v:192908.17-192908.96" + wire width 3 $and$libresoc.v:192908$13462_Y + attribute \src "libresoc.v:192905.18-192905.93" + wire width 3 $not$libresoc.v:192905$13459_Y + attribute \src "libresoc.v:192907.17-192907.92" + wire width 3 $not$libresoc.v:192907$13461_Y + attribute \src "libresoc.v:192910.17-192910.92" + wire width 3 $not$libresoc.v:192910$13464_Y + attribute \src "libresoc.v:192904.18-192904.98" + wire width 3 $or$libresoc.v:192904$13458_Y + attribute \src "libresoc.v:192906.18-192906.99" + wire width 3 $or$libresoc.v:192906$13460_Y + attribute \src "libresoc.v:192909.17-192909.97" + wire width 3 $or$libresoc.v:192909$13463_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398332,11 +402341,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190564.7-190564.15" + attribute \src "libresoc.v:192868.7-192868.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -398353,7 +402362,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190599$13273 + cell $and $and$libresoc.v:192903$13457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398361,10 +402370,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190599$13273_Y + connect \Y $and$libresoc.v:192903$13457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190604$13278 + cell $and $and$libresoc.v:192908$13462 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398372,34 +402381,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190604$13278_Y + connect \Y $and$libresoc.v:192908$13462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190601$13275 + cell $not $not$libresoc.v:192905$13459 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190601$13275_Y + connect \Y $not$libresoc.v:192905$13459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190603$13277 + cell $not $not$libresoc.v:192907$13461 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190603$13277_Y + connect \Y $not$libresoc.v:192907$13461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190606$13280 + cell $not $not$libresoc.v:192910$13464 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190606$13280_Y + connect \Y $not$libresoc.v:192910$13464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190600$13274 + cell $or $or$libresoc.v:192904$13458 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398407,10 +402416,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190600$13274_Y + connect \Y $or$libresoc.v:192904$13458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190602$13276 + cell $or $or$libresoc.v:192906$13460 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398418,10 +402427,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190602$13276_Y + connect \Y $or$libresoc.v:192906$13460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190605$13279 + cell $or $or$libresoc.v:192909$13463 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398429,39 +402438,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190605$13279_Y + connect \Y $or$libresoc.v:192909$13463_Y end - attribute \src "libresoc.v:190564.7-190564.20" - process $proc$libresoc.v:190564$13285 + attribute \src "libresoc.v:192868.7-192868.20" + process $proc$libresoc.v:192868$13469 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190586.13-190586.25" - process $proc$libresoc.v:190586$13286 + attribute \src "libresoc.v:192890.13-192890.25" + process $proc$libresoc.v:192890$13470 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190607.3-190608.27" - process $proc$libresoc.v:190607$13281 + attribute \src "libresoc.v:192911.3-192912.27" + process $proc$libresoc.v:192911$13465 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190609.3-190617.6" - process $proc$libresoc.v:190609$13282 + attribute \src "libresoc.v:192913.3-192921.6" + process $proc$libresoc.v:192913$13466 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13283 $1\q_int$next[2:0]$13284 - attribute \src "libresoc.v:190610.5-190610.29" + assign $0\q_int$next[2:0]$13467 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192914.5-192914.29" switch \initial - attribute \src "libresoc.v:190610.9-190610.17" + attribute \src "libresoc.v:192914.9-192914.17" case 1'1 case end @@ -398470,56 +402479,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13284 3'000 + assign $1\q_int$next[2:0]$13468 3'000 case - assign $1\q_int$next[2:0]$13284 \$5 + assign $1\q_int$next[2:0]$13468 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13283 + update \q_int$next $0\q_int$next[2:0]$13467 end - connect \$9 $and$libresoc.v:190599$13273_Y - connect \$11 $or$libresoc.v:190600$13274_Y - connect \$13 $not$libresoc.v:190601$13275_Y - connect \$15 $or$libresoc.v:190602$13276_Y - connect \$1 $not$libresoc.v:190603$13277_Y - connect \$3 $and$libresoc.v:190604$13278_Y - connect \$5 $or$libresoc.v:190605$13279_Y - connect \$7 $not$libresoc.v:190606$13280_Y + connect \$9 $and$libresoc.v:192903$13457_Y + connect \$11 $or$libresoc.v:192904$13458_Y + connect \$13 $not$libresoc.v:192905$13459_Y + connect \$15 $or$libresoc.v:192906$13460_Y + connect \$1 $not$libresoc.v:192907$13461_Y + connect \$3 $and$libresoc.v:192908$13462_Y + connect \$5 $or$libresoc.v:192909$13463_Y + connect \$7 $not$libresoc.v:192910$13464_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190625.1-190683.10" +attribute \src "libresoc.v:192929.1-192987.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:190626.7-190626.20" + attribute \src "libresoc.v:192930.7-192930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190671.3-190679.6" - wire $0\q_int$next[0:0]$13297 - attribute \src "libresoc.v:190669.3-190670.27" + attribute \src "libresoc.v:192975.3-192983.6" + wire $0\q_int$next[0:0]$13481 + attribute \src "libresoc.v:192973.3-192974.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190671.3-190679.6" - wire $1\q_int$next[0:0]$13298 - attribute \src "libresoc.v:190648.7-190648.19" + attribute \src "libresoc.v:192975.3-192983.6" + wire $1\q_int$next[0:0]$13482 + attribute \src "libresoc.v:192952.7-192952.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190661.17-190661.96" - wire $and$libresoc.v:190661$13287_Y - attribute \src "libresoc.v:190666.17-190666.96" - wire $and$libresoc.v:190666$13292_Y - attribute \src "libresoc.v:190663.18-190663.99" - wire $not$libresoc.v:190663$13289_Y - attribute \src "libresoc.v:190665.17-190665.98" - wire $not$libresoc.v:190665$13291_Y - attribute \src "libresoc.v:190668.17-190668.98" - wire $not$libresoc.v:190668$13294_Y - attribute \src "libresoc.v:190662.18-190662.104" - wire $or$libresoc.v:190662$13288_Y - attribute \src "libresoc.v:190664.18-190664.105" - wire $or$libresoc.v:190664$13290_Y - attribute \src "libresoc.v:190667.17-190667.103" - wire $or$libresoc.v:190667$13293_Y + attribute \src "libresoc.v:192965.17-192965.96" + wire $and$libresoc.v:192965$13471_Y + attribute \src "libresoc.v:192970.17-192970.96" + wire $and$libresoc.v:192970$13476_Y + attribute \src "libresoc.v:192967.18-192967.99" + wire $not$libresoc.v:192967$13473_Y + attribute \src "libresoc.v:192969.17-192969.98" + wire $not$libresoc.v:192969$13475_Y + attribute \src "libresoc.v:192972.17-192972.98" + wire $not$libresoc.v:192972$13478_Y + attribute \src "libresoc.v:192966.18-192966.104" + wire $or$libresoc.v:192966$13472_Y + attribute \src "libresoc.v:192968.18-192968.105" + wire $or$libresoc.v:192968$13474_Y + attribute \src "libresoc.v:192971.17-192971.103" + wire $or$libresoc.v:192971$13477_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398536,11 +402545,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190626.7-190626.15" + attribute \src "libresoc.v:192930.7-192930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398557,7 +402566,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190661$13287 + cell $and $and$libresoc.v:192965$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398565,10 +402574,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190661$13287_Y + connect \Y $and$libresoc.v:192965$13471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190666$13292 + cell $and $and$libresoc.v:192970$13476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398576,34 +402585,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190666$13292_Y + connect \Y $and$libresoc.v:192970$13476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190663$13289 + cell $not $not$libresoc.v:192967$13473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:190663$13289_Y + connect \Y $not$libresoc.v:192967$13473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190665$13291 + cell $not $not$libresoc.v:192969$13475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:190665$13291_Y + connect \Y $not$libresoc.v:192969$13475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190668$13294 + cell $not $not$libresoc.v:192972$13478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:190668$13294_Y + connect \Y $not$libresoc.v:192972$13478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190662$13288 + cell $or $or$libresoc.v:192966$13472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398611,10 +402620,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:190662$13288_Y + connect \Y $or$libresoc.v:192966$13472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190664$13290 + cell $or $or$libresoc.v:192968$13474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398622,10 +402631,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:190664$13290_Y + connect \Y $or$libresoc.v:192968$13474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190667$13293 + cell $or $or$libresoc.v:192971$13477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398633,39 +402642,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:190667$13293_Y + connect \Y $or$libresoc.v:192971$13477_Y end - attribute \src "libresoc.v:190626.7-190626.20" - process $proc$libresoc.v:190626$13299 + attribute \src "libresoc.v:192930.7-192930.20" + process $proc$libresoc.v:192930$13483 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190648.7-190648.19" - process $proc$libresoc.v:190648$13300 + attribute \src "libresoc.v:192952.7-192952.19" + process $proc$libresoc.v:192952$13484 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190669.3-190670.27" - process $proc$libresoc.v:190669$13295 + attribute \src "libresoc.v:192973.3-192974.27" + process $proc$libresoc.v:192973$13479 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190671.3-190679.6" - process $proc$libresoc.v:190671$13296 + attribute \src "libresoc.v:192975.3-192983.6" + process $proc$libresoc.v:192975$13480 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13297 $1\q_int$next[0:0]$13298 - attribute \src "libresoc.v:190672.5-190672.29" + assign $0\q_int$next[0:0]$13481 $1\q_int$next[0:0]$13482 + attribute \src "libresoc.v:192976.5-192976.29" switch \initial - attribute \src "libresoc.v:190672.9-190672.17" + attribute \src "libresoc.v:192976.9-192976.17" case 1'1 case end @@ -398674,56 +402683,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13298 1'0 + assign $1\q_int$next[0:0]$13482 1'0 case - assign $1\q_int$next[0:0]$13298 \$5 + assign $1\q_int$next[0:0]$13482 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13297 + update \q_int$next $0\q_int$next[0:0]$13481 end - connect \$9 $and$libresoc.v:190661$13287_Y - connect \$11 $or$libresoc.v:190662$13288_Y - connect \$13 $not$libresoc.v:190663$13289_Y - connect \$15 $or$libresoc.v:190664$13290_Y - connect \$1 $not$libresoc.v:190665$13291_Y - connect \$3 $and$libresoc.v:190666$13292_Y - connect \$5 $or$libresoc.v:190667$13293_Y - connect \$7 $not$libresoc.v:190668$13294_Y + connect \$9 $and$libresoc.v:192965$13471_Y + connect \$11 $or$libresoc.v:192966$13472_Y + connect \$13 $not$libresoc.v:192967$13473_Y + connect \$15 $or$libresoc.v:192968$13474_Y + connect \$1 $not$libresoc.v:192969$13475_Y + connect \$3 $and$libresoc.v:192970$13476_Y + connect \$5 $or$libresoc.v:192971$13477_Y + connect \$7 $not$libresoc.v:192972$13478_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:190687.1-190745.10" +attribute \src "libresoc.v:192991.1-193049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:190688.7-190688.20" + attribute \src "libresoc.v:192992.7-192992.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190733.3-190741.6" - wire $0\q_int$next[0:0]$13311 - attribute \src "libresoc.v:190731.3-190732.27" + attribute \src "libresoc.v:193037.3-193045.6" + wire $0\q_int$next[0:0]$13495 + attribute \src "libresoc.v:193035.3-193036.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190733.3-190741.6" - wire $1\q_int$next[0:0]$13312 - attribute \src "libresoc.v:190710.7-190710.19" + attribute \src "libresoc.v:193037.3-193045.6" + wire $1\q_int$next[0:0]$13496 + attribute \src "libresoc.v:193014.7-193014.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190723.17-190723.96" - wire $and$libresoc.v:190723$13301_Y - attribute \src "libresoc.v:190728.17-190728.96" - wire $and$libresoc.v:190728$13306_Y - attribute \src "libresoc.v:190725.18-190725.97" - wire $not$libresoc.v:190725$13303_Y - attribute \src "libresoc.v:190727.17-190727.96" - wire $not$libresoc.v:190727$13305_Y - attribute \src "libresoc.v:190730.17-190730.96" - wire $not$libresoc.v:190730$13308_Y - attribute \src "libresoc.v:190724.18-190724.102" - wire $or$libresoc.v:190724$13302_Y - attribute \src "libresoc.v:190726.18-190726.103" - wire $or$libresoc.v:190726$13304_Y - attribute \src "libresoc.v:190729.17-190729.101" - wire $or$libresoc.v:190729$13307_Y + attribute \src "libresoc.v:193027.17-193027.96" + wire $and$libresoc.v:193027$13485_Y + attribute \src "libresoc.v:193032.17-193032.96" + wire $and$libresoc.v:193032$13490_Y + attribute \src "libresoc.v:193029.18-193029.97" + wire $not$libresoc.v:193029$13487_Y + attribute \src "libresoc.v:193031.17-193031.96" + wire $not$libresoc.v:193031$13489_Y + attribute \src "libresoc.v:193034.17-193034.96" + wire $not$libresoc.v:193034$13492_Y + attribute \src "libresoc.v:193028.18-193028.102" + wire $or$libresoc.v:193028$13486_Y + attribute \src "libresoc.v:193030.18-193030.103" + wire $or$libresoc.v:193030$13488_Y + attribute \src "libresoc.v:193033.17-193033.101" + wire $or$libresoc.v:193033$13491_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398740,11 +402749,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190688.7-190688.15" + attribute \src "libresoc.v:192992.7-192992.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398761,7 +402770,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190723$13301 + cell $and $and$libresoc.v:193027$13485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398769,10 +402778,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190723$13301_Y + connect \Y $and$libresoc.v:193027$13485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190728$13306 + cell $and $and$libresoc.v:193032$13490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398780,34 +402789,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190728$13306_Y + connect \Y $and$libresoc.v:193032$13490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190725$13303 + cell $not $not$libresoc.v:193029$13487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:190725$13303_Y + connect \Y $not$libresoc.v:193029$13487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190727$13305 + cell $not $not$libresoc.v:193031$13489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:190727$13305_Y + connect \Y $not$libresoc.v:193031$13489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190730$13308 + cell $not $not$libresoc.v:193034$13492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:190730$13308_Y + connect \Y $not$libresoc.v:193034$13492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190724$13302 + cell $or $or$libresoc.v:193028$13486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398815,10 +402824,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:190724$13302_Y + connect \Y $or$libresoc.v:193028$13486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190726$13304 + cell $or $or$libresoc.v:193030$13488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398826,10 +402835,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:190726$13304_Y + connect \Y $or$libresoc.v:193030$13488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190729$13307 + cell $or $or$libresoc.v:193033$13491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398837,39 +402846,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:190729$13307_Y + connect \Y $or$libresoc.v:193033$13491_Y end - attribute \src "libresoc.v:190688.7-190688.20" - process $proc$libresoc.v:190688$13313 + attribute \src "libresoc.v:192992.7-192992.20" + process $proc$libresoc.v:192992$13497 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190710.7-190710.19" - process $proc$libresoc.v:190710$13314 + attribute \src "libresoc.v:193014.7-193014.19" + process $proc$libresoc.v:193014$13498 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190731.3-190732.27" - process $proc$libresoc.v:190731$13309 + attribute \src "libresoc.v:193035.3-193036.27" + process $proc$libresoc.v:193035$13493 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190733.3-190741.6" - process $proc$libresoc.v:190733$13310 + attribute \src "libresoc.v:193037.3-193045.6" + process $proc$libresoc.v:193037$13494 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13311 $1\q_int$next[0:0]$13312 - attribute \src "libresoc.v:190734.5-190734.29" + assign $0\q_int$next[0:0]$13495 $1\q_int$next[0:0]$13496 + attribute \src "libresoc.v:193038.5-193038.29" switch \initial - attribute \src "libresoc.v:190734.9-190734.17" + attribute \src "libresoc.v:193038.9-193038.17" case 1'1 case end @@ -398878,86 +402887,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13312 1'0 + assign $1\q_int$next[0:0]$13496 1'0 case - assign $1\q_int$next[0:0]$13312 \$5 + assign $1\q_int$next[0:0]$13496 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13311 + update \q_int$next $0\q_int$next[0:0]$13495 end - connect \$9 $and$libresoc.v:190723$13301_Y - connect \$11 $or$libresoc.v:190724$13302_Y - connect \$13 $not$libresoc.v:190725$13303_Y - connect \$15 $or$libresoc.v:190726$13304_Y - connect \$1 $not$libresoc.v:190727$13305_Y - connect \$3 $and$libresoc.v:190728$13306_Y - connect \$5 $or$libresoc.v:190729$13307_Y - connect \$7 $not$libresoc.v:190730$13308_Y + connect \$9 $and$libresoc.v:193027$13485_Y + connect \$11 $or$libresoc.v:193028$13486_Y + connect \$13 $not$libresoc.v:193029$13487_Y + connect \$15 $or$libresoc.v:193030$13488_Y + connect \$1 $not$libresoc.v:193031$13489_Y + connect \$3 $and$libresoc.v:193032$13490_Y + connect \$5 $or$libresoc.v:193033$13491_Y + connect \$7 $not$libresoc.v:193034$13492_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:190749.1-191045.10" +attribute \src "libresoc.v:193053.1-193349.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:190997.3-191006.6" + attribute \src "libresoc.v:193301.3-193310.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:190750.7-190750.20" + attribute \src "libresoc.v:193054.7-193054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191016.3-191025.6" + attribute \src "libresoc.v:193320.3-193329.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:191007.3-191015.6" - wire width 3 $0\ren_delay$12$next[2:0]$13338 - attribute \src "libresoc.v:190911.3-190912.43" - wire width 3 $0\ren_delay$12[2:0]$13327 - attribute \src "libresoc.v:190878.13-190878.34" - wire width 3 $0\ren_delay$12[2:0]$13344 - attribute \src "libresoc.v:190969.3-190977.6" - wire width 3 $0\ren_delay$19$next[2:0]$13330 - attribute \src "libresoc.v:190909.3-190910.43" - wire width 3 $0\ren_delay$19[2:0]$13325 - attribute \src "libresoc.v:190882.13-190882.34" - wire width 3 $0\ren_delay$19[2:0]$13346 - attribute \src "libresoc.v:190988.3-190996.6" - wire width 3 $0\ren_delay$next[2:0]$13334 - attribute \src "libresoc.v:190913.3-190914.35" + attribute \src "libresoc.v:193311.3-193319.6" + wire width 3 $0\ren_delay$12$next[2:0]$13522 + attribute \src "libresoc.v:193215.3-193216.43" + wire width 3 $0\ren_delay$12[2:0]$13511 + attribute \src "libresoc.v:193182.13-193182.34" + wire width 3 $0\ren_delay$12[2:0]$13528 + attribute \src "libresoc.v:193273.3-193281.6" + wire width 3 $0\ren_delay$19$next[2:0]$13514 + attribute \src "libresoc.v:193213.3-193214.43" + wire width 3 $0\ren_delay$19[2:0]$13509 + attribute \src "libresoc.v:193186.13-193186.34" + wire width 3 $0\ren_delay$19[2:0]$13530 + attribute \src "libresoc.v:193292.3-193300.6" + wire width 3 $0\ren_delay$next[2:0]$13518 + attribute \src "libresoc.v:193217.3-193218.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:190978.3-190987.6" + attribute \src "libresoc.v:193282.3-193291.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:190997.3-191006.6" + attribute \src "libresoc.v:193301.3-193310.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:191016.3-191025.6" + attribute \src "libresoc.v:193320.3-193329.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:191007.3-191015.6" - wire width 3 $1\ren_delay$12$next[2:0]$13339 - attribute \src "libresoc.v:190969.3-190977.6" - wire width 3 $1\ren_delay$19$next[2:0]$13331 - attribute \src "libresoc.v:190988.3-190996.6" - wire width 3 $1\ren_delay$next[2:0]$13335 - attribute \src "libresoc.v:190876.13-190876.29" + attribute \src "libresoc.v:193311.3-193319.6" + wire width 3 $1\ren_delay$12$next[2:0]$13523 + attribute \src "libresoc.v:193273.3-193281.6" + wire width 3 $1\ren_delay$19$next[2:0]$13515 + attribute \src "libresoc.v:193292.3-193300.6" + wire width 3 $1\ren_delay$next[2:0]$13519 + attribute \src "libresoc.v:193180.13-193180.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:190978.3-190987.6" + attribute \src "libresoc.v:193282.3-193291.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:190900.18-190900.109" - wire width 64 $or$libresoc.v:190900$13315_Y - attribute \src "libresoc.v:190902.18-190902.124" - wire width 64 $or$libresoc.v:190902$13317_Y - attribute \src "libresoc.v:190903.18-190903.110" - wire width 64 $or$libresoc.v:190903$13318_Y - attribute \src "libresoc.v:190905.18-190905.122" - wire width 64 $or$libresoc.v:190905$13320_Y - attribute \src "libresoc.v:190906.18-190906.109" - wire width 64 $or$libresoc.v:190906$13321_Y - attribute \src "libresoc.v:190908.17-190908.123" - wire width 64 $or$libresoc.v:190908$13323_Y - attribute \src "libresoc.v:190901.18-190901.100" - wire $reduce_or$libresoc.v:190901$13316_Y - attribute \src "libresoc.v:190904.18-190904.100" - wire $reduce_or$libresoc.v:190904$13319_Y - attribute \src "libresoc.v:190907.17-190907.95" - wire $reduce_or$libresoc.v:190907$13322_Y + attribute \src "libresoc.v:193204.18-193204.109" + wire width 64 $or$libresoc.v:193204$13499_Y + attribute \src "libresoc.v:193206.18-193206.124" + wire width 64 $or$libresoc.v:193206$13501_Y + attribute \src "libresoc.v:193207.18-193207.110" + wire width 64 $or$libresoc.v:193207$13502_Y + attribute \src "libresoc.v:193209.18-193209.122" + wire width 64 $or$libresoc.v:193209$13504_Y + attribute \src "libresoc.v:193210.18-193210.109" + wire width 64 $or$libresoc.v:193210$13505_Y + attribute \src "libresoc.v:193212.17-193212.123" + wire width 64 $or$libresoc.v:193212$13507_Y + attribute \src "libresoc.v:193205.18-193205.100" + wire $reduce_or$libresoc.v:193205$13500_Y + attribute \src "libresoc.v:193208.18-193208.100" + wire $reduce_or$libresoc.v:193208$13503_Y + attribute \src "libresoc.v:193211.17-193211.95" + wire $reduce_or$libresoc.v:193211$13506_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -398980,9 +402989,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -398992,7 +403001,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:190750.7-190750.15" + attribute \src "libresoc.v:193054.7-193054.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -399107,7 +403116,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190900$13315 + cell $or $or$libresoc.v:193204$13499 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399115,10 +403124,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:190900$13315_Y + connect \Y $or$libresoc.v:193204$13499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190902$13317 + cell $or $or$libresoc.v:193206$13501 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399126,10 +403135,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:190902$13317_Y + connect \Y $or$libresoc.v:193206$13501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190903$13318 + cell $or $or$libresoc.v:193207$13502 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399137,10 +403146,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:190903$13318_Y + connect \Y $or$libresoc.v:193207$13502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190905$13320 + cell $or $or$libresoc.v:193209$13504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399148,10 +403157,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:190905$13320_Y + connect \Y $or$libresoc.v:193209$13504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190906$13321 + cell $or $or$libresoc.v:193210$13505 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399159,10 +403168,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:190906$13321_Y + connect \Y $or$libresoc.v:193210$13505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190908$13323 + cell $or $or$libresoc.v:193212$13507 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399170,34 +403179,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:190908$13323_Y + connect \Y $or$libresoc.v:193212$13507_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190901$13316 + cell $reduce_or $reduce_or$libresoc.v:193205$13500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:190901$13316_Y + connect \Y $reduce_or$libresoc.v:193205$13500_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190904$13319 + cell $reduce_or $reduce_or$libresoc.v:193208$13503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:190904$13319_Y + connect \Y $reduce_or$libresoc.v:193208$13503_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190907$13322 + cell $reduce_or $reduce_or$libresoc.v:193211$13506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:190907$13322_Y + connect \Y $reduce_or$libresoc.v:193211$13506_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:190915.15-190932.4" + attribute \src "libresoc.v:193219.15-193236.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -399217,7 +403226,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:190933.15-190950.4" + attribute \src "libresoc.v:193237.15-193254.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -399237,7 +403246,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:190951.15-190968.4" + attribute \src "libresoc.v:193255.15-193272.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -399256,67 +403265,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:190750.7-190750.20" - process $proc$libresoc.v:190750$13341 + attribute \src "libresoc.v:193054.7-193054.20" + process $proc$libresoc.v:193054$13525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190876.13-190876.29" - process $proc$libresoc.v:190876$13342 + attribute \src "libresoc.v:193180.13-193180.29" + process $proc$libresoc.v:193180$13526 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:190878.13-190878.34" - process $proc$libresoc.v:190878$13343 + attribute \src "libresoc.v:193182.13-193182.34" + process $proc$libresoc.v:193182$13527 assign { } { } - assign $0\ren_delay$12[2:0]$13344 3'000 + assign $0\ren_delay$12[2:0]$13528 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13344 + update \ren_delay$12 $0\ren_delay$12[2:0]$13528 end - attribute \src "libresoc.v:190882.13-190882.34" - process $proc$libresoc.v:190882$13345 + attribute \src "libresoc.v:193186.13-193186.34" + process $proc$libresoc.v:193186$13529 assign { } { } - assign $0\ren_delay$19[2:0]$13346 3'000 + assign $0\ren_delay$19[2:0]$13530 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13346 + update \ren_delay$19 $0\ren_delay$19[2:0]$13530 end - attribute \src "libresoc.v:190909.3-190910.43" - process $proc$libresoc.v:190909$13324 + attribute \src "libresoc.v:193213.3-193214.43" + process $proc$libresoc.v:193213$13508 assign { } { } - assign $0\ren_delay$19[2:0]$13325 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13509 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13325 + update \ren_delay$19 $0\ren_delay$19[2:0]$13509 end - attribute \src "libresoc.v:190911.3-190912.43" - process $proc$libresoc.v:190911$13326 + attribute \src "libresoc.v:193215.3-193216.43" + process $proc$libresoc.v:193215$13510 assign { } { } - assign $0\ren_delay$12[2:0]$13327 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13511 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13327 + update \ren_delay$12 $0\ren_delay$12[2:0]$13511 end - attribute \src "libresoc.v:190913.3-190914.35" - process $proc$libresoc.v:190913$13328 + attribute \src "libresoc.v:193217.3-193218.35" + process $proc$libresoc.v:193217$13512 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:190969.3-190977.6" - process $proc$libresoc.v:190969$13329 + attribute \src "libresoc.v:193273.3-193281.6" + process $proc$libresoc.v:193273$13513 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13330 $1\ren_delay$19$next[2:0]$13331 - attribute \src "libresoc.v:190970.5-190970.29" + assign $0\ren_delay$19$next[2:0]$13514 $1\ren_delay$19$next[2:0]$13515 + attribute \src "libresoc.v:193274.5-193274.29" switch \initial - attribute \src "libresoc.v:190970.9-190970.17" + attribute \src "libresoc.v:193274.9-193274.17" case 1'1 case end @@ -399325,21 +403334,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13331 3'000 + assign $1\ren_delay$19$next[2:0]$13515 3'000 case - assign $1\ren_delay$19$next[2:0]$13331 \sv__ren + assign $1\ren_delay$19$next[2:0]$13515 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13330 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13514 end - attribute \src "libresoc.v:190978.3-190987.6" - process $proc$libresoc.v:190978$13332 + attribute \src "libresoc.v:193282.3-193291.6" + process $proc$libresoc.v:193282$13516 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:190979.5-190979.29" + attribute \src "libresoc.v:193283.5-193283.29" switch \initial - attribute \src "libresoc.v:190979.9-190979.17" + attribute \src "libresoc.v:193283.9-193283.17" case 1'1 case end @@ -399355,14 +403364,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:190988.3-190996.6" - process $proc$libresoc.v:190988$13333 + attribute \src "libresoc.v:193292.3-193300.6" + process $proc$libresoc.v:193292$13517 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13334 $1\ren_delay$next[2:0]$13335 - attribute \src "libresoc.v:190989.5-190989.29" + assign $0\ren_delay$next[2:0]$13518 $1\ren_delay$next[2:0]$13519 + attribute \src "libresoc.v:193293.5-193293.29" switch \initial - attribute \src "libresoc.v:190989.9-190989.17" + attribute \src "libresoc.v:193293.9-193293.17" case 1'1 case end @@ -399371,21 +403380,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13335 3'000 + assign $1\ren_delay$next[2:0]$13519 3'000 case - assign $1\ren_delay$next[2:0]$13335 \cia__ren + assign $1\ren_delay$next[2:0]$13519 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13334 + update \ren_delay$next $0\ren_delay$next[2:0]$13518 end - attribute \src "libresoc.v:190997.3-191006.6" - process $proc$libresoc.v:190997$13336 + attribute \src "libresoc.v:193301.3-193310.6" + process $proc$libresoc.v:193301$13520 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:190998.5-190998.29" + attribute \src "libresoc.v:193302.5-193302.29" switch \initial - attribute \src "libresoc.v:190998.9-190998.17" + attribute \src "libresoc.v:193302.9-193302.17" case 1'1 case end @@ -399401,14 +403410,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:191007.3-191015.6" - process $proc$libresoc.v:191007$13337 + attribute \src "libresoc.v:193311.3-193319.6" + process $proc$libresoc.v:193311$13521 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13338 $1\ren_delay$12$next[2:0]$13339 - attribute \src "libresoc.v:191008.5-191008.29" + assign $0\ren_delay$12$next[2:0]$13522 $1\ren_delay$12$next[2:0]$13523 + attribute \src "libresoc.v:193312.5-193312.29" switch \initial - attribute \src "libresoc.v:191008.9-191008.17" + attribute \src "libresoc.v:193312.9-193312.17" case 1'1 case end @@ -399417,21 +403426,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13339 3'000 + assign $1\ren_delay$12$next[2:0]$13523 3'000 case - assign $1\ren_delay$12$next[2:0]$13339 \msr__ren + assign $1\ren_delay$12$next[2:0]$13523 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13338 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13522 end - attribute \src "libresoc.v:191016.3-191025.6" - process $proc$libresoc.v:191016$13340 + attribute \src "libresoc.v:193320.3-193329.6" + process $proc$libresoc.v:193320$13524 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:191017.5-191017.29" + attribute \src "libresoc.v:193321.5-193321.29" switch \initial - attribute \src "libresoc.v:191017.9-191017.17" + attribute \src "libresoc.v:193321.9-193321.17" case 1'1 case end @@ -399447,15 +403456,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:190900$13315_Y - connect \$13 $reduce_or$libresoc.v:190901$13316_Y - connect \$15 $or$libresoc.v:190902$13317_Y - connect \$17 $or$libresoc.v:190903$13318_Y - connect \$20 $reduce_or$libresoc.v:190904$13319_Y - connect \$22 $or$libresoc.v:190905$13320_Y - connect \$24 $or$libresoc.v:190906$13321_Y - connect \$6 $reduce_or$libresoc.v:190907$13322_Y - connect \$8 $or$libresoc.v:190908$13323_Y + connect \$10 $or$libresoc.v:193204$13499_Y + connect \$13 $reduce_or$libresoc.v:193205$13500_Y + connect \$15 $or$libresoc.v:193206$13501_Y + connect \$17 $or$libresoc.v:193207$13502_Y + connect \$20 $reduce_or$libresoc.v:193208$13503_Y + connect \$22 $or$libresoc.v:193209$13504_Y + connect \$24 $or$libresoc.v:193210$13505_Y + connect \$6 $reduce_or$libresoc.v:193211$13506_Y + connect \$8 $or$libresoc.v:193212$13507_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -399476,37 +403485,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:191049.1-191107.10" +attribute \src "libresoc.v:193353.1-193411.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:191050.7-191050.20" + attribute \src "libresoc.v:193354.7-193354.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191095.3-191103.6" - wire $0\q_int$next[0:0]$13357 - attribute \src "libresoc.v:191093.3-191094.27" + attribute \src "libresoc.v:193399.3-193407.6" + wire $0\q_int$next[0:0]$13541 + attribute \src "libresoc.v:193397.3-193398.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:191095.3-191103.6" - wire $1\q_int$next[0:0]$13358 - attribute \src "libresoc.v:191072.7-191072.19" + attribute \src "libresoc.v:193399.3-193407.6" + wire $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193376.7-193376.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:191085.17-191085.96" - wire $and$libresoc.v:191085$13347_Y - attribute \src "libresoc.v:191090.17-191090.96" - wire $and$libresoc.v:191090$13352_Y - attribute \src "libresoc.v:191087.18-191087.93" - wire $not$libresoc.v:191087$13349_Y - attribute \src "libresoc.v:191089.17-191089.92" - wire $not$libresoc.v:191089$13351_Y - attribute \src "libresoc.v:191092.17-191092.92" - wire $not$libresoc.v:191092$13354_Y - attribute \src "libresoc.v:191086.18-191086.98" - wire $or$libresoc.v:191086$13348_Y - attribute \src "libresoc.v:191088.18-191088.99" - wire $or$libresoc.v:191088$13350_Y - attribute \src "libresoc.v:191091.17-191091.97" - wire $or$libresoc.v:191091$13353_Y + attribute \src "libresoc.v:193389.17-193389.96" + wire $and$libresoc.v:193389$13531_Y + attribute \src "libresoc.v:193394.17-193394.96" + wire $and$libresoc.v:193394$13536_Y + attribute \src "libresoc.v:193391.18-193391.93" + wire $not$libresoc.v:193391$13533_Y + attribute \src "libresoc.v:193393.17-193393.92" + wire $not$libresoc.v:193393$13535_Y + attribute \src "libresoc.v:193396.17-193396.92" + wire $not$libresoc.v:193396$13538_Y + attribute \src "libresoc.v:193390.18-193390.98" + wire $or$libresoc.v:193390$13532_Y + attribute \src "libresoc.v:193392.18-193392.99" + wire $or$libresoc.v:193392$13534_Y + attribute \src "libresoc.v:193395.17-193395.97" + wire $or$libresoc.v:193395$13537_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -399523,11 +403532,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:191050.7-191050.15" + attribute \src "libresoc.v:193354.7-193354.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -399544,7 +403553,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191085$13347 + cell $and $and$libresoc.v:193389$13531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399552,10 +403561,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191085$13347_Y + connect \Y $and$libresoc.v:193389$13531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191090$13352 + cell $and $and$libresoc.v:193394$13536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399563,34 +403572,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191090$13352_Y + connect \Y $and$libresoc.v:193394$13536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191087$13349 + cell $not $not$libresoc.v:193391$13533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:191087$13349_Y + connect \Y $not$libresoc.v:193391$13533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191089$13351 + cell $not $not$libresoc.v:193393$13535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:191089$13351_Y + connect \Y $not$libresoc.v:193393$13535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191092$13354 + cell $not $not$libresoc.v:193396$13538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:191092$13354_Y + connect \Y $not$libresoc.v:193396$13538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191086$13348 + cell $or $or$libresoc.v:193390$13532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399598,10 +403607,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:191086$13348_Y + connect \Y $or$libresoc.v:193390$13532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191088$13350 + cell $or $or$libresoc.v:193392$13534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399609,10 +403618,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:191088$13350_Y + connect \Y $or$libresoc.v:193392$13534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191091$13353 + cell $or $or$libresoc.v:193395$13537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399620,39 +403629,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:191091$13353_Y + connect \Y $or$libresoc.v:193395$13537_Y end - attribute \src "libresoc.v:191050.7-191050.20" - process $proc$libresoc.v:191050$13359 + attribute \src "libresoc.v:193354.7-193354.20" + process $proc$libresoc.v:193354$13543 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191072.7-191072.19" - process $proc$libresoc.v:191072$13360 + attribute \src "libresoc.v:193376.7-193376.19" + process $proc$libresoc.v:193376$13544 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:191093.3-191094.27" - process $proc$libresoc.v:191093$13355 + attribute \src "libresoc.v:193397.3-193398.27" + process $proc$libresoc.v:193397$13539 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:191095.3-191103.6" - process $proc$libresoc.v:191095$13356 + attribute \src "libresoc.v:193399.3-193407.6" + process $proc$libresoc.v:193399$13540 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13357 $1\q_int$next[0:0]$13358 - attribute \src "libresoc.v:191096.5-191096.29" + assign $0\q_int$next[0:0]$13541 $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193400.5-193400.29" switch \initial - attribute \src "libresoc.v:191096.9-191096.17" + attribute \src "libresoc.v:193400.9-193400.17" case 1'1 case end @@ -399661,26 +403670,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13358 1'0 + assign $1\q_int$next[0:0]$13542 1'0 case - assign $1\q_int$next[0:0]$13358 \$5 + assign $1\q_int$next[0:0]$13542 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13357 + update \q_int$next $0\q_int$next[0:0]$13541 end - connect \$9 $and$libresoc.v:191085$13347_Y - connect \$11 $or$libresoc.v:191086$13348_Y - connect \$13 $not$libresoc.v:191087$13349_Y - connect \$15 $or$libresoc.v:191088$13350_Y - connect \$1 $not$libresoc.v:191089$13351_Y - connect \$3 $and$libresoc.v:191090$13352_Y - connect \$5 $or$libresoc.v:191091$13353_Y - connect \$7 $not$libresoc.v:191092$13354_Y + connect \$9 $and$libresoc.v:193389$13531_Y + connect \$11 $or$libresoc.v:193390$13532_Y + connect \$13 $not$libresoc.v:193391$13533_Y + connect \$15 $or$libresoc.v:193392$13534_Y + connect \$1 $not$libresoc.v:193393$13535_Y + connect \$3 $and$libresoc.v:193394$13536_Y + connect \$5 $or$libresoc.v:193395$13537_Y + connect \$7 $not$libresoc.v:193396$13538_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:191112.1-192349.10" +attribute \src "libresoc.v:193416.1-194641.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -399694,36 +403703,36 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 404 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 400 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 406 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" + wire width 2 input 402 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 344 \dbus__ack + wire input 340 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 338 \dbus__adr + wire width 45 output 334 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 348 \dbus__bte + wire width 2 input 344 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 347 \dbus__cti + wire width 3 input 343 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 342 \dbus__cyc + wire output 338 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 340 \dbus__dat_r + wire width 64 input 336 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 339 \dbus__dat_w + wire width 64 output 335 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 346 \dbus__err + wire input 342 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 341 \dbus__sel + wire width 8 output 337 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 343 \dbus__stb + wire output 339 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 345 \dbus__we + wire output 341 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 19 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -399929,65 +403938,65 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 120 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 333 \ibus__ack + wire input 329 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 327 \ibus__adr + wire width 45 output 323 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 337 \ibus__bte + wire width 2 input 333 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 336 \ibus__cti + wire width 3 input 332 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 331 \ibus__cyc + wire output 327 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 329 \ibus__dat_r + wire width 64 input 325 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 328 \ibus__dat_w + wire width 64 input 324 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 335 \ibus__err + wire input 331 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 330 \ibus__sel + wire width 8 output 326 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 332 \ibus__stb + wire output 328 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 334 \ibus__we + wire input 330 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 391 \icp_wb__ack + wire output 387 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 385 \icp_wb__adr + wire width 28 input 381 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 389 \icp_wb__cyc + wire input 385 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 387 \icp_wb__dat_r + wire width 32 output 383 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 386 \icp_wb__dat_w + wire width 32 input 382 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 393 \icp_wb__err + wire input 389 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 388 \icp_wb__sel + wire width 4 input 384 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 390 \icp_wb__stb + wire input 386 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 392 \icp_wb__we + wire input 388 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 400 \ics_wb__ack + wire output 396 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 394 \ics_wb__adr + wire width 28 input 390 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 398 \ics_wb__cyc + wire input 394 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 396 \ics_wb__dat_r + wire width 32 output 392 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 395 \ics_wb__dat_w + wire width 32 input 391 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 402 \ics_wb__err + wire input 398 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 397 \ics_wb__sel + wire width 4 input 393 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 399 \ics_wb__stb + wire input 395 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 401 \ics_wb__we + wire input 397 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 403 \int_level_i + wire width 16 input 399 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -400006,7 +404015,7 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \mspi0_clk__core__o @@ -400057,24 +404066,24 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 409 \pc_i + wire width 64 input 405 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" - wire output 407 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" + wire output 403 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 408 \pll_lck_o + wire output 404 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" wire \pllclk_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \pwm_0__core__o @@ -400084,8 +404093,8 @@ module \test_issuer wire input 147 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 405 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 401 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400231,17 +404240,9 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 182 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 274 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 275 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dm_1__pad__i + wire input 273 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dm_1__pad__oe + wire output 274 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 183 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400255,77 +404256,77 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__core__i + wire output 287 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 292 \sdr_dq_10__core__o + wire input 288 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 293 \sdr_dq_10__core__oe + wire input 289 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_10__pad__i + wire input 290 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_10__pad__o + wire output 291 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_10__pad__oe + wire output 292 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__core__i + wire output 293 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 298 \sdr_dq_11__core__o + wire input 294 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 299 \sdr_dq_11__core__oe + wire input 295 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_11__pad__i + wire input 296 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__pad__o + wire output 297 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__oe + wire output 298 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__core__i + wire output 299 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 304 \sdr_dq_12__core__o + wire input 300 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 305 \sdr_dq_12__core__oe + wire input 301 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_12__pad__i + wire input 302 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__pad__o + wire output 303 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__oe + wire output 304 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__core__i + wire output 305 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 310 \sdr_dq_13__core__o + wire input 306 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 311 \sdr_dq_13__core__oe + wire input 307 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_13__pad__i + wire input 308 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__o + wire output 309 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_13__pad__oe + wire output 310 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__core__i + wire output 311 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 316 \sdr_dq_14__core__o + wire input 312 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 317 \sdr_dq_14__core__oe + wire input 313 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_14__pad__i + wire input 314 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_14__pad__o + wire output 315 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_14__pad__oe + wire output 316 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__core__i + wire output 317 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 322 \sdr_dq_15__core__o + wire input 318 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 323 \sdr_dq_15__core__oe + wire input 319 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 324 \sdr_dq_15__pad__i + wire input 320 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_15__pad__o + wire output 321 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__pad__oe + wire output 322 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 189 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400411,29 +404412,29 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 230 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__core__i + wire output 275 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 280 \sdr_dq_8__core__o + wire input 276 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 281 \sdr_dq_8__core__oe + wire input 277 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_8__pad__i + wire input 278 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_8__pad__o + wire output 279 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_8__pad__oe + wire output 280 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__core__i + wire output 281 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 286 \sdr_dq_9__core__o + wire input 282 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 287 \sdr_dq_9__core__oe + wire input 283 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_9__pad__i + wire input 284 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_dq_9__pad__o + wire output 285 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_dq_9__pad__oe + wire output 286 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 259 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400443,81 +404444,81 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 356 \sram4k_0_wb__ack + wire output 352 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 349 \sram4k_0_wb__adr + wire width 9 input 345 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_0_wb__cyc + wire input 349 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 351 \sram4k_0_wb__dat_r + wire width 64 output 347 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 350 \sram4k_0_wb__dat_w + wire width 64 input 346 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 357 \sram4k_0_wb__err + wire input 353 \sram4k_0_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 352 \sram4k_0_wb__sel + wire width 8 input 348 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 354 \sram4k_0_wb__stb + wire input 350 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 355 \sram4k_0_wb__we + wire input 351 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 365 \sram4k_1_wb__ack + wire output 361 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 358 \sram4k_1_wb__adr + wire width 9 input 354 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_1_wb__cyc + wire input 358 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 360 \sram4k_1_wb__dat_r + wire width 64 output 356 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 359 \sram4k_1_wb__dat_w + wire width 64 input 355 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 366 \sram4k_1_wb__err + wire input 362 \sram4k_1_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 361 \sram4k_1_wb__sel + wire width 8 input 357 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 363 \sram4k_1_wb__stb + wire input 359 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 364 \sram4k_1_wb__we + wire input 360 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 374 \sram4k_2_wb__ack + wire output 370 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 367 \sram4k_2_wb__adr + wire width 9 input 363 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 371 \sram4k_2_wb__cyc + wire input 367 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 369 \sram4k_2_wb__dat_r + wire width 64 output 365 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 368 \sram4k_2_wb__dat_w + wire width 64 input 364 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 375 \sram4k_2_wb__err + wire input 371 \sram4k_2_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 370 \sram4k_2_wb__sel + wire width 8 input 366 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 372 \sram4k_2_wb__stb + wire input 368 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 373 \sram4k_2_wb__we + wire input 369 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 383 \sram4k_3_wb__ack + wire output 379 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 376 \sram4k_3_wb__adr + wire width 9 input 372 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 380 \sram4k_3_wb__cyc + wire input 376 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 378 \sram4k_3_wb__dat_r + wire width 64 output 374 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 377 \sram4k_3_wb__dat_w + wire width 64 input 373 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 384 \sram4k_3_wb__err + wire input 380 \sram4k_3_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 379 \sram4k_3_wb__sel + wire width 8 input 375 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 381 \sram4k_3_wb__stb + wire input 377 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 382 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 378 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:191943.7-191949.4" + attribute \src "libresoc.v:194239.7-194245.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -400526,7 +404527,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:191950.6-192343.4" + attribute \src "libresoc.v:194246.6-194635.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -400782,12 +404783,8 @@ module \test_issuer connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe @@ -400927,2064 +404924,2066 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:192353.1-197545.10" +attribute \src "libresoc.v:194645.1-199858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_asmcode$next[7:0]$13857 - attribute \src "libresoc.v:194947.3-194948.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_asmcode$next[7:0]$14042 + attribute \src "libresoc.v:197237.3-197238.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $0\core_bigendian_i$10$next[0:0]$13655 - attribute \src "libresoc.v:195077.3-195078.57" - wire $0\core_bigendian_i$10[0:0]$13574 - attribute \src "libresoc.v:192630.7-192630.35" - wire $0\core_bigendian_i$10[0:0]$14064 - attribute \src "libresoc.v:196436.3-196448.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $0\core_bigendian_i$10$next[0:0]$13837 + attribute \src "libresoc.v:197367.3-197368.57" + wire $0\core_bigendian_i$10[0:0]$13756 + attribute \src "libresoc.v:194920.7-194920.35" + wire $0\core_bigendian_i$10[0:0]$14249 + attribute \src "libresoc.v:198723.3-198735.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13858 - attribute \src "libresoc.v:195021.3-195022.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_cia$next[63:0]$14043 + attribute \src "libresoc.v:197311.3-197312.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13859 - attribute \src "libresoc.v:195065.3-195066.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$14044 + attribute \src "libresoc.v:197355.3-197356.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13860 - attribute \src "libresoc.v:195067.3-195068.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$14045 + attribute \src "libresoc.v:197357.3-197358.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13861 - attribute \src "libresoc.v:195069.3-195070.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$14046 + attribute \src "libresoc.v:197359.3-197360.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13862 - attribute \src "libresoc.v:195047.3-195048.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13552 - attribute \src "libresoc.v:192656.7-192656.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14072 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13863 - attribute \src "libresoc.v:195049.3-195050.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13554 - attribute \src "libresoc.v:192660.7-192660.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14074 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13864 - attribute \src "libresoc.v:195051.3-195052.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13556 - attribute \src "libresoc.v:192664.7-192664.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14076 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13865 - attribute \src "libresoc.v:195053.3-195054.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13558 - attribute \src "libresoc.v:192668.7-192668.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14078 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13866 - attribute \src "libresoc.v:195057.3-195058.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13561 - attribute \src "libresoc.v:192672.7-192672.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14080 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13867 - attribute \src "libresoc.v:195059.3-195060.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13563 - attribute \src "libresoc.v:192676.7-192676.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14082 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13868 - attribute \src "libresoc.v:195061.3-195062.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13565 - attribute \src "libresoc.v:192680.7-192680.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14084 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13869 - attribute \src "libresoc.v:195045.3-195046.71" - wire $0\core_core_core_exc_$signal[0:0]$13550 - attribute \src "libresoc.v:192654.7-192654.42" - wire $0\core_core_core_exc_$signal[0:0]$14070 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$13870 - attribute \src "libresoc.v:195027.3-195028.61" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$14047 + attribute \src "libresoc.v:197337.3-197338.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13734 + attribute \src "libresoc.v:194946.7-194946.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14257 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$14048 + attribute \src "libresoc.v:197339.3-197340.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13736 + attribute \src "libresoc.v:194950.7-194950.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14259 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$14049 + attribute \src "libresoc.v:197341.3-197342.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13738 + attribute \src "libresoc.v:194954.7-194954.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14261 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$14050 + attribute \src "libresoc.v:197343.3-197344.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13740 + attribute \src "libresoc.v:194958.7-194958.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14263 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$14051 + attribute \src "libresoc.v:197347.3-197348.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13743 + attribute \src "libresoc.v:194962.7-194962.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14265 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$14052 + attribute \src "libresoc.v:197349.3-197350.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13745 + attribute \src "libresoc.v:194966.7-194966.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14267 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$14053 + attribute \src "libresoc.v:197351.3-197352.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13747 + attribute \src "libresoc.v:194970.7-194970.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14269 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$next[0:0]$14054 + attribute \src "libresoc.v:197335.3-197336.71" + wire $0\core_core_core_exc_$signal[0:0]$13732 + attribute \src "libresoc.v:194944.7-194944.42" + wire $0\core_core_core_exc_$signal[0:0]$14255 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$14055 + attribute \src "libresoc.v:197317.3-197318.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13871 - attribute \src "libresoc.v:195041.3-195042.69" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$14056 + attribute \src "libresoc.v:197331.3-197332.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13872 - attribute \src "libresoc.v:195023.3-195024.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $0\core_core_core_insn$next[31:0]$14057 + attribute \src "libresoc.v:197313.3-197314.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13873 - attribute \src "libresoc.v:195025.3-195026.65" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$14058 + attribute \src "libresoc.v:197315.3-197316.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_is_32bit$next[0:0]$13874 - attribute \src "libresoc.v:195073.3-195074.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_is_32bit$next[0:0]$14059 + attribute \src "libresoc.v:197363.3-197364.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13875 - attribute \src "libresoc.v:195019.3-195020.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_msr$next[63:0]$14060 + attribute \src "libresoc.v:197309.3-197310.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_oe$next[0:0]$13876 - attribute \src "libresoc.v:195037.3-195038.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe$next[0:0]$14061 + attribute \src "libresoc.v:197327.3-197328.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_oe_ok$next[0:0]$13877 - attribute \src "libresoc.v:195039.3-195040.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe_ok$next[0:0]$14062 + attribute \src "libresoc.v:197329.3-197330.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_rc$next[0:0]$13878 - attribute \src "libresoc.v:195031.3-195032.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc$next[0:0]$14063 + attribute \src "libresoc.v:197321.3-197322.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_rc_ok$next[0:0]$13879 - attribute \src "libresoc.v:195035.3-195036.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc_ok$next[0:0]$14064 + attribute \src "libresoc.v:197325.3-197326.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13880 - attribute \src "libresoc.v:195063.3-195064.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$14065 + attribute \src "libresoc.v:197353.3-197354.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13881 - attribute \src "libresoc.v:195043.3-195044.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$14066 + attribute \src "libresoc.v:197333.3-197334.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$13882 - attribute \src "libresoc.v:195001.3-195002.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$14067 + attribute \src "libresoc.v:197291.3-197292.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13883 - attribute \src "libresoc.v:195003.3-195004.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in1_ok$next[0:0]$14068 + attribute \src "libresoc.v:197293.3-197294.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$13884 - attribute \src "libresoc.v:195009.3-195010.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13530 - attribute \src "libresoc.v:192838.13-192838.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14101 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$13885 - attribute \src "libresoc.v:195005.3-195006.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$14069 + attribute \src "libresoc.v:197299.3-197300.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13712 + attribute \src "libresoc.v:195128.13-195128.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14286 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$14070 + attribute \src "libresoc.v:197295.3-197296.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13886 - attribute \src "libresoc.v:195013.3-195014.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13533 - attribute \src "libresoc.v:192846.7-192846.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14104 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13887 - attribute \src "libresoc.v:195007.3-195008.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$14071 + attribute \src "libresoc.v:197303.3-197304.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13715 + attribute \src "libresoc.v:195136.7-195136.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14289 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14072 + attribute \src "libresoc.v:197297.3-197298.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_out$next[6:0]$13888 - attribute \src "libresoc.v:195015.3-195016.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14073 + attribute \src "libresoc.v:197305.3-197306.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13889 - attribute \src "libresoc.v:195071.3-195072.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14074 + attribute \src "libresoc.v:197361.3-197362.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_dststep$next[6:0]$13609 - attribute \src "libresoc.v:194937.3-194938.51" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_dststep$next[6:0]$13791 + attribute \src "libresoc.v:197227.3-197228.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_ea$next[6:0]$13890 - attribute \src "libresoc.v:194953.3-194954.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_ea$next[6:0]$14075 + attribute \src "libresoc.v:197243.3-197244.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fast1$next[2:0]$13891 - attribute \src "libresoc.v:194983.3-194984.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast1$next[2:0]$14076 + attribute \src "libresoc.v:197273.3-197274.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_fast1_ok$next[0:0]$13892 - attribute \src "libresoc.v:194985.3-194986.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast1_ok$next[0:0]$14077 + attribute \src "libresoc.v:197275.3-197276.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fast2$next[2:0]$13893 - attribute \src "libresoc.v:194987.3-194988.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast2$next[2:0]$14078 + attribute \src "libresoc.v:197277.3-197278.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_fast2_ok$next[0:0]$13894 - attribute \src "libresoc.v:194991.3-194992.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast2_ok$next[0:0]$14079 + attribute \src "libresoc.v:197281.3-197282.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13895 - attribute \src "libresoc.v:194993.3-194994.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14080 + attribute \src "libresoc.v:197283.3-197284.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13896 - attribute \src "libresoc.v:194997.3-194998.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14081 + attribute \src "libresoc.v:197287.3-197288.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_lk$next[0:0]$13897 - attribute \src "libresoc.v:195029.3-195030.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_lk$next[0:0]$14082 + attribute \src "libresoc.v:197319.3-197320.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13610 - attribute \src "libresoc.v:194943.3-194944.47" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13792 + attribute \src "libresoc.v:197233.3-197234.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_core_pc$next[63:0]$13611 - attribute \src "libresoc.v:194915.3-194916.41" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_core_pc$next[63:0]$13793 + attribute \src "libresoc.v:197205.3-197206.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg1$next[6:0]$13898 - attribute \src "libresoc.v:194957.3-194958.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg1$next[6:0]$14083 + attribute \src "libresoc.v:197247.3-197248.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg1_ok$next[0:0]$13899 - attribute \src "libresoc.v:194959.3-194960.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg1_ok$next[0:0]$14084 + attribute \src "libresoc.v:197249.3-197250.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg2$next[6:0]$13900 - attribute \src "libresoc.v:194961.3-194962.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg2$next[6:0]$14085 + attribute \src "libresoc.v:197251.3-197252.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg2_ok$next[0:0]$13901 - attribute \src "libresoc.v:194963.3-194964.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg2_ok$next[0:0]$14086 + attribute \src "libresoc.v:197253.3-197254.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg3$next[6:0]$13902 - attribute \src "libresoc.v:194965.3-194966.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg3$next[6:0]$14087 + attribute \src "libresoc.v:197255.3-197256.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg3_ok$next[0:0]$13903 - attribute \src "libresoc.v:194969.3-194970.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg3_ok$next[0:0]$14088 + attribute \src "libresoc.v:197259.3-197260.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_rego$next[6:0]$13904 - attribute \src "libresoc.v:194949.3-194950.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_rego$next[6:0]$14089 + attribute \src "libresoc.v:197239.3-197240.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $0\core_core_spr1$next[9:0]$13905 - attribute \src "libresoc.v:194975.3-194976.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spr1$next[9:0]$14090 + attribute \src "libresoc.v:197265.3-197266.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_spr1_ok$next[0:0]$13906 - attribute \src "libresoc.v:194977.3-194978.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_spr1_ok$next[0:0]$14091 + attribute \src "libresoc.v:197267.3-197268.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $0\core_core_spro$next[9:0]$13907 - attribute \src "libresoc.v:194971.3-194972.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spro$next[9:0]$14092 + attribute \src "libresoc.v:197261.3-197262.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13612 - attribute \src "libresoc.v:194939.3-194940.51" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13794 + attribute \src "libresoc.v:197229.3-197230.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $0\core_core_subvl$next[1:0]$13613 - attribute \src "libresoc.v:194935.3-194936.47" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_subvl$next[1:0]$13795 + attribute \src "libresoc.v:197225.3-197226.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $0\core_core_svstep$next[1:0]$13614 - attribute \src "libresoc.v:194933.3-194934.49" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_svstep$next[1:0]$13796 + attribute \src "libresoc.v:197223.3-197224.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_vl$next[6:0]$13615 - attribute \src "libresoc.v:194941.3-194942.41" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_vl$next[6:0]$13797 + attribute \src "libresoc.v:197231.3-197232.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13908 - attribute \src "libresoc.v:194979.3-194980.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14093 + attribute \src "libresoc.v:197269.3-197270.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_cr_out_ok$next[0:0]$13909 - attribute \src "libresoc.v:195017.3-195018.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_cr_out_ok$next[0:0]$14094 + attribute \src "libresoc.v:197307.3-197308.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:196021.3-196030.6" - wire width 64 $0\core_data_i$12[63:0]$13673 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $0\core_data_i$12[63:0]$13856 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_dec$next[63:0]$13616 - attribute \src "libresoc.v:194931.3-194932.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_dec$next[63:0]$13798 + attribute \src "libresoc.v:197221.3-197222.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:196134.3-196143.6" + attribute \src "libresoc.v:198421.3-198430.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:196144.3-196153.6" + attribute \src "libresoc.v:198431.3-198440.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_ea_ok$next[0:0]$13910 - attribute \src "libresoc.v:194955.3-194956.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_ea_ok$next[0:0]$14095 + attribute \src "libresoc.v:197245.3-197246.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire $0\core_eint$next[0:0]$13617 - attribute \src "libresoc.v:194929.3-194930.35" + attribute \src "libresoc.v:198074.3-198118.6" + wire $0\core_eint$next[0:0]$13799 + attribute \src "libresoc.v:197219.3-197220.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_fasto1_ok$next[0:0]$13911 - attribute \src "libresoc.v:194995.3-194996.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto1_ok$next[0:0]$14096 + attribute \src "libresoc.v:197285.3-197286.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_fasto2_ok$next[0:0]$13912 - attribute \src "libresoc.v:194999.3-195000.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto2_ok$next[0:0]$14097 + attribute \src "libresoc.v:197289.3-197290.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:196183.3-196192.6" + attribute \src "libresoc.v:198470.3-198479.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196222.3-196231.6" + attribute \src "libresoc.v:198509.3-198518.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196330.3-196344.6" - wire width 3 $0\core_issue__addr$13[2:0]$13713 - attribute \src "libresoc.v:196261.3-196275.6" + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $0\core_issue__addr$13[2:0]$13896 + attribute \src "libresoc.v:198548.3-198562.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:196360.3-196374.6" + attribute \src "libresoc.v:198647.3-198661.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:196276.3-196290.6" + attribute \src "libresoc.v:198563.3-198577.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:196345.3-196359.6" + attribute \src "libresoc.v:198632.3-198646.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198354.3-198369.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_msr$next[63:0]$13618 - attribute \src "libresoc.v:194927.3-194928.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_msr$next[63:0]$13800 + attribute \src "libresoc.v:197217.3-197218.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13650 - attribute \src "libresoc.v:195099.3-195100.47" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13832 + attribute \src "libresoc.v:197389.3-197390.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_rego_ok$next[0:0]$13913 - attribute \src "libresoc.v:194951.3-194952.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_rego_ok$next[0:0]$14098 + attribute \src "libresoc.v:197241.3-197242.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_spro_ok$next[0:0]$13914 - attribute \src "libresoc.v:194973.3-194974.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_spro_ok$next[0:0]$14099 + attribute \src "libresoc.v:197263.3-197264.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:199449.3-199479.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:196474.3-196486.6" + attribute \src "libresoc.v:198761.3-198773.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $0\core_sv_a_nz$next[0:0]$13660 - attribute \src "libresoc.v:195055.3-195056.41" + attribute \src "libresoc.v:198165.3-198189.6" + wire $0\core_sv_a_nz$next[0:0]$13842 + attribute \src "libresoc.v:197345.3-197346.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:196011.3-196020.6" - wire width 3 $0\core_wen$11[2:0]$13670 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $0\core_wen$11[2:0]$13853 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_xer_out$next[0:0]$13915 - attribute \src "libresoc.v:194981.3-194982.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_xer_out$next[0:0]$14100 + attribute \src "libresoc.v:197271.3-197272.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:195113.3-195114.43" + attribute \src "libresoc.v:197403.3-197404.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13754 - attribute \src "libresoc.v:195097.3-195098.47" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13937 + attribute \src "libresoc.v:197387.3-197388.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13755 - attribute \src "libresoc.v:195105.3-195106.43" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13938 + attribute \src "libresoc.v:197395.3-197396.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13756 - attribute \src "libresoc.v:195101.3-195102.47" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13939 + attribute \src "libresoc.v:197391.3-197392.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13757 - attribute \src "libresoc.v:195095.3-195096.43" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13940 + attribute \src "libresoc.v:197385.3-197386.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13758 - attribute \src "libresoc.v:195093.3-195094.45" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13941 + attribute \src "libresoc.v:197383.3-197384.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13759 - attribute \src "libresoc.v:195103.3-195104.37" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13942 + attribute \src "libresoc.v:197393.3-197394.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:196193.3-196201.6" - wire $0\d_cr_delay$next[0:0]$13695 - attribute \src "libresoc.v:194989.3-194990.37" + attribute \src "libresoc.v:198480.3-198488.6" + wire $0\d_cr_delay$next[0:0]$13878 + attribute \src "libresoc.v:197279.3-197280.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:196154.3-196162.6" - wire $0\d_reg_delay$next[0:0]$13689 - attribute \src "libresoc.v:195011.3-195012.39" + attribute \src "libresoc.v:198441.3-198449.6" + wire $0\d_reg_delay$next[0:0]$13872 + attribute \src "libresoc.v:197301.3-197302.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:196232.3-196240.6" - wire $0\d_xer_delay$next[0:0]$13701 - attribute \src "libresoc.v:194967.3-194968.39" + attribute \src "libresoc.v:198519.3-198527.6" + wire $0\d_xer_delay$next[0:0]$13884 + attribute \src "libresoc.v:197257.3-197258.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199480.3-199510.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196212.3-196221.6" + attribute \src "libresoc.v:198499.3-198508.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196202.3-196211.6" + attribute \src "libresoc.v:198489.3-198498.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196173.3-196182.6" + attribute \src "libresoc.v:198460.3-198469.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196163.3-196172.6" + attribute \src "libresoc.v:198450.3-198459.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196251.3-196260.6" + attribute \src "libresoc.v:198538.3-198547.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196241.3-196250.6" + attribute \src "libresoc.v:198528.3-198537.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:195751.3-195759.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13597 - attribute \src "libresoc.v:194925.3-194926.45" + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13779 + attribute \src "libresoc.v:197215.3-197216.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:196487.3-196495.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13736 - attribute \src "libresoc.v:194919.3-194920.39" + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13919 + attribute \src "libresoc.v:197209.3-197210.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:195760.3-195768.6" - wire $0\dbg_dmi_req_i$next[0:0]$13600 - attribute \src "libresoc.v:194923.3-194924.43" + attribute \src "libresoc.v:198046.3-198054.6" + wire $0\dbg_dmi_req_i$next[0:0]$13782 + attribute \src "libresoc.v:197213.3-197214.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:196402.3-196410.6" - wire $0\dbg_dmi_we_i$next[0:0]$13723 - attribute \src "libresoc.v:194921.3-194922.41" + attribute \src "libresoc.v:198689.3-198697.6" + wire $0\dbg_dmi_we_i$next[0:0]$13906 + attribute \src "libresoc.v:197211.3-197212.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13718 - attribute \src "libresoc.v:194913.3-194914.41" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13901 + attribute \src "libresoc.v:197203.3-197204.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:195769.3-195777.6" - wire $0\dec2_cur_eint$next[0:0]$13603 - attribute \src "libresoc.v:195117.3-195118.43" + attribute \src "libresoc.v:198055.3-198063.6" + wire $0\dec2_cur_eint$next[0:0]$13785 + attribute \src "libresoc.v:197407.3-197408.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13802 - attribute \src "libresoc.v:195087.3-195088.41" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13985 + attribute \src "libresoc.v:197377.3-197378.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13749 - attribute \src "libresoc.v:195107.3-195108.39" + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13932 + attribute \src "libresoc.v:197397.3-197398.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13811 - attribute \src "libresoc.v:195083.3-195084.53" + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13994 + attribute \src "libresoc.v:197373.3-197374.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:195778.3-195787.6" - wire width 2 $0\delay$next[1:0]$13606 - attribute \src "libresoc.v:195115.3-195116.27" + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $0\delay$next[1:0]$13788 + attribute \src "libresoc.v:197405.3-197406.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $0\exec_fsm_state$next[0:0]$13679 - attribute \src "libresoc.v:195033.3-195034.45" + attribute \src "libresoc.v:198370.3-198404.6" + wire $0\exec_fsm_state$next[0:0]$13862 + attribute \src "libresoc.v:197323.3-197324.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:196031.3-196041.6" + attribute \src "libresoc.v:198318.3-198328.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:195942.3-195952.6" + attribute \src "libresoc.v:198250.3-198260.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198261.3-198276.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13794 - attribute \src "libresoc.v:195089.3-195090.47" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13977 + attribute \src "libresoc.v:197379.3-197380.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:197394.3-197404.6" + attribute \src "libresoc.v:199702.3-199712.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:196976.3-196986.6" + attribute \src "libresoc.v:199263.3-199273.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196657.3-196667.6" + attribute \src "libresoc.v:198944.3-198954.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199334.3-199349.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $0\fsm_state$next[1:0]$13708 - attribute \src "libresoc.v:194945.3-194946.35" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $0\fsm_state$next[1:0]$13891 + attribute \src "libresoc.v:197235.3-197236.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:192354.7-192354.20" + attribute \src "libresoc.v:194646.7-194646.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $0\issue_fsm_state$next[2:0]$13819 - attribute \src "libresoc.v:195081.3-195082.47" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $0\issue_fsm_state$next[2:0]$14002 + attribute \src "libresoc.v:197371.3-197372.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:196648.3-196656.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13742 - attribute \src "libresoc.v:194917.3-194918.49" + attribute \src "libresoc.v:198935.3-198943.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13925 + attribute \src "libresoc.v:197207.3-197208.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:196812.3-196820.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13785 - attribute \src "libresoc.v:195119.3-195120.47" + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13968 + attribute \src "libresoc.v:197409.3-197410.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:196821.3-196850.6" - wire $0\msr_read$next[0:0]$13788 - attribute \src "libresoc.v:195091.3-195092.33" + attribute \src "libresoc.v:199108.3-199137.6" + wire $0\msr_read$next[0:0]$13971 + attribute \src "libresoc.v:197381.3-197382.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:196319.3-196329.6" + attribute \src "libresoc.v:198606.3-198616.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:196391.3-196401.6" + attribute \src "libresoc.v:198678.3-198688.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $0\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $0\nia$next[63:0]$13807 - attribute \src "libresoc.v:195085.3-195086.23" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $0\nia$next[63:0]$13990 + attribute \src "libresoc.v:197375.3-197376.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $0\pc_changed$next[0:0]$13833 - attribute \src "libresoc.v:195079.3-195080.37" + attribute \src "libresoc.v:199511.3-199577.6" + wire $0\pc_changed$next[0:0]$14018 + attribute \src "libresoc.v:197369.3-197370.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:196411.3-196419.6" - wire $0\pc_ok_delay$next[0:0]$13726 - attribute \src "libresoc.v:195111.3-195112.39" + attribute \src "libresoc.v:198698.3-198706.6" + wire $0\pc_ok_delay$next[0:0]$13909 + attribute \src "libresoc.v:197401.3-197402.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:197327.3-197393.6" - wire $0\sv_changed$next[0:0]$13845 - attribute \src "libresoc.v:195075.3-195076.37" + attribute \src "libresoc.v:198228.3-198238.6" + wire $0\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $0\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $0\sv_changed$next[0:0]$14030 + attribute \src "libresoc.v:197365.3-197366.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:196449.3-196457.6" - wire $0\svstate_ok_delay$next[0:0]$13731 - attribute \src "libresoc.v:195109.3-195110.49" + attribute \src "libresoc.v:198736.3-198744.6" + wire $0\svstate_ok_delay$next[0:0]$13914 + attribute \src "libresoc.v:197399.3-197400.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $10\issue_fsm_state$next[2:0]$13829 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_asmcode$next[7:0]$13916 - attribute \src "libresoc.v:192624.13-192624.33" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_asmcode$next[7:0]$14101 + attribute \src "libresoc.v:194914.13-194914.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $1\core_bigendian_i$10$next[0:0]$13656 - attribute \src "libresoc.v:196436.3-196448.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $1\core_bigendian_i$10$next[0:0]$13838 + attribute \src "libresoc.v:198723.3-198735.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13917 - attribute \src "libresoc.v:192638.14-192638.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14102 + attribute \src "libresoc.v:194928.14-194928.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13918 - attribute \src "libresoc.v:192642.13-192642.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14103 + attribute \src "libresoc.v:194932.13-194932.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13919 - attribute \src "libresoc.v:192646.7-192646.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14104 + attribute \src "libresoc.v:194936.7-194936.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13920 - attribute \src "libresoc.v:192650.13-192650.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14105 + attribute \src "libresoc.v:194940.13-194940.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13921 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13922 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13923 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13924 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13925 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13926 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13927 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13928 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$13929 - attribute \src "libresoc.v:192701.14-192701.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14106 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14107 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14108 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14109 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14110 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14111 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14112 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14113 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$14114 + attribute \src "libresoc.v:194991.14-194991.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13930 - attribute \src "libresoc.v:192709.13-192709.46" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14115 + attribute \src "libresoc.v:194999.13-194999.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13931 - attribute \src "libresoc.v:192713.14-192713.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14116 + attribute \src "libresoc.v:195003.14-195003.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13932 - attribute \src "libresoc.v:192792.13-192792.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14117 + attribute \src "libresoc.v:195082.13-195082.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_is_32bit$next[0:0]$13933 - attribute \src "libresoc.v:192796.7-192796.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_is_32bit$next[0:0]$14118 + attribute \src "libresoc.v:195086.7-195086.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13934 - attribute \src "libresoc.v:192800.14-192800.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14119 + attribute \src "libresoc.v:195090.14-195090.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_oe$next[0:0]$13935 - attribute \src "libresoc.v:192804.7-192804.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe$next[0:0]$14120 + attribute \src "libresoc.v:195094.7-195094.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_oe_ok$next[0:0]$13936 - attribute \src "libresoc.v:192808.7-192808.34" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe_ok$next[0:0]$14121 + attribute \src "libresoc.v:195098.7-195098.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_rc$next[0:0]$13937 - attribute \src "libresoc.v:192812.7-192812.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc$next[0:0]$14122 + attribute \src "libresoc.v:195102.7-195102.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_rc_ok$next[0:0]$13938 - attribute \src "libresoc.v:192816.7-192816.34" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc_ok$next[0:0]$14123 + attribute \src "libresoc.v:195106.7-195106.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13939 - attribute \src "libresoc.v:192820.14-192820.48" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14124 + attribute \src "libresoc.v:195110.14-195110.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13940 - attribute \src "libresoc.v:192824.13-192824.44" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14125 + attribute \src "libresoc.v:195114.13-195114.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$13941 - attribute \src "libresoc.v:192828.13-192828.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14126 + attribute \src "libresoc.v:195118.13-195118.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13942 - attribute \src "libresoc.v:192832.7-192832.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14127 + attribute \src "libresoc.v:195122.7-195122.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$13943 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$13944 - attribute \src "libresoc.v:192836.13-192836.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14128 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14129 + attribute \src "libresoc.v:195126.13-195126.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13945 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13946 - attribute \src "libresoc.v:192844.7-192844.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14130 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14131 + attribute \src "libresoc.v:195134.7-195134.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_out$next[6:0]$13947 - attribute \src "libresoc.v:192852.13-192852.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14132 + attribute \src "libresoc.v:195142.13-195142.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13948 - attribute \src "libresoc.v:192856.7-192856.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14133 + attribute \src "libresoc.v:195146.7-195146.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_dststep$next[6:0]$13619 - attribute \src "libresoc.v:192860.13-192860.38" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_dststep$next[6:0]$13801 + attribute \src "libresoc.v:195150.13-195150.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_ea$next[6:0]$13949 - attribute \src "libresoc.v:192864.13-192864.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_ea$next[6:0]$14134 + attribute \src "libresoc.v:195154.13-195154.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fast1$next[2:0]$13950 - attribute \src "libresoc.v:192868.13-192868.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast1$next[2:0]$14135 + attribute \src "libresoc.v:195158.13-195158.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_fast1_ok$next[0:0]$13951 - attribute \src "libresoc.v:192872.7-192872.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast1_ok$next[0:0]$14136 + attribute \src "libresoc.v:195162.7-195162.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fast2$next[2:0]$13952 - attribute \src "libresoc.v:192876.13-192876.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast2$next[2:0]$14137 + attribute \src "libresoc.v:195166.13-195166.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_fast2_ok$next[0:0]$13953 - attribute \src "libresoc.v:192880.7-192880.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast2_ok$next[0:0]$14138 + attribute \src "libresoc.v:195170.7-195170.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13954 - attribute \src "libresoc.v:192884.13-192884.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14139 + attribute \src "libresoc.v:195174.13-195174.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13955 - attribute \src "libresoc.v:192888.13-192888.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14140 + attribute \src "libresoc.v:195178.13-195178.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_lk$next[0:0]$13956 - attribute \src "libresoc.v:192892.7-192892.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_lk$next[0:0]$14141 + attribute \src "libresoc.v:195182.7-195182.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13620 - attribute \src "libresoc.v:192896.13-192896.36" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13802 + attribute \src "libresoc.v:195186.13-195186.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_core_pc$next[63:0]$13621 - attribute \src "libresoc.v:192900.14-192900.49" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_core_pc$next[63:0]$13803 + attribute \src "libresoc.v:195190.14-195190.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg1$next[6:0]$13957 - attribute \src "libresoc.v:192904.13-192904.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg1$next[6:0]$14142 + attribute \src "libresoc.v:195194.13-195194.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg1_ok$next[0:0]$13958 - attribute \src "libresoc.v:192908.7-192908.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg1_ok$next[0:0]$14143 + attribute \src "libresoc.v:195198.7-195198.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg2$next[6:0]$13959 - attribute \src "libresoc.v:192912.13-192912.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg2$next[6:0]$14144 + attribute \src "libresoc.v:195202.13-195202.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg2_ok$next[0:0]$13960 - attribute \src "libresoc.v:192916.7-192916.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg2_ok$next[0:0]$14145 + attribute \src "libresoc.v:195206.7-195206.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg3$next[6:0]$13961 - attribute \src "libresoc.v:192920.13-192920.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg3$next[6:0]$14146 + attribute \src "libresoc.v:195210.13-195210.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg3_ok$next[0:0]$13962 - attribute \src "libresoc.v:192924.7-192924.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg3_ok$next[0:0]$14147 + attribute \src "libresoc.v:195214.7-195214.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_rego$next[6:0]$13963 - attribute \src "libresoc.v:192928.13-192928.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_rego$next[6:0]$14148 + attribute \src "libresoc.v:195218.13-195218.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $1\core_core_spr1$next[9:0]$13964 - attribute \src "libresoc.v:193046.13-193046.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spr1$next[9:0]$14149 + attribute \src "libresoc.v:195336.13-195336.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_spr1_ok$next[0:0]$13965 - attribute \src "libresoc.v:193050.7-193050.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_spr1_ok$next[0:0]$14150 + attribute \src "libresoc.v:195340.7-195340.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $1\core_core_spro$next[9:0]$13966 - attribute \src "libresoc.v:193168.13-193168.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spro$next[9:0]$14151 + attribute \src "libresoc.v:195458.13-195458.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13622 - attribute \src "libresoc.v:193172.13-193172.38" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13804 + attribute \src "libresoc.v:195462.13-195462.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $1\core_core_subvl$next[1:0]$13623 - attribute \src "libresoc.v:193176.13-193176.35" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_subvl$next[1:0]$13805 + attribute \src "libresoc.v:195466.13-195466.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $1\core_core_svstep$next[1:0]$13624 - attribute \src "libresoc.v:193180.13-193180.36" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_svstep$next[1:0]$13806 + attribute \src "libresoc.v:195470.13-195470.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_vl$next[6:0]$13625 - attribute \src "libresoc.v:193186.13-193186.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_vl$next[6:0]$13807 + attribute \src "libresoc.v:195476.13-195476.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13967 - attribute \src "libresoc.v:193190.13-193190.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14152 + attribute \src "libresoc.v:195480.13-195480.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_cr_out_ok$next[0:0]$13968 - attribute \src "libresoc.v:193198.7-193198.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_cr_out_ok$next[0:0]$14153 + attribute \src "libresoc.v:195488.7-195488.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:196021.3-196030.6" - wire width 64 $1\core_data_i$12[63:0]$13674 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_dec$next[63:0]$13626 - attribute \src "libresoc.v:193214.14-193214.45" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_dec$next[63:0]$13808 + attribute \src "libresoc.v:195504.14-195504.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:196134.3-196143.6" + attribute \src "libresoc.v:198421.3-198430.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:196144.3-196153.6" + attribute \src "libresoc.v:198431.3-198440.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_ea_ok$next[0:0]$13969 - attribute \src "libresoc.v:193224.7-193224.24" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_ea_ok$next[0:0]$14154 + attribute \src "libresoc.v:195514.7-195514.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire $1\core_eint$next[0:0]$13627 - attribute \src "libresoc.v:193228.7-193228.23" + attribute \src "libresoc.v:198074.3-198118.6" + wire $1\core_eint$next[0:0]$13809 + attribute \src "libresoc.v:195518.7-195518.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_fasto1_ok$next[0:0]$13970 - attribute \src "libresoc.v:193232.7-193232.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto1_ok$next[0:0]$14155 + attribute \src "libresoc.v:195522.7-195522.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_fasto2_ok$next[0:0]$13971 - attribute \src "libresoc.v:193236.7-193236.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto2_ok$next[0:0]$14156 + attribute \src "libresoc.v:195526.7-195526.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:196183.3-196192.6" + attribute \src "libresoc.v:198470.3-198479.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196222.3-196231.6" + attribute \src "libresoc.v:198509.3-198518.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196330.3-196344.6" - wire width 3 $1\core_issue__addr$13[2:0]$13714 - attribute \src "libresoc.v:196261.3-196275.6" + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198548.3-198562.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:196360.3-196374.6" + attribute \src "libresoc.v:198647.3-198661.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:196276.3-196290.6" + attribute \src "libresoc.v:198563.3-198577.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:196345.3-196359.6" + attribute \src "libresoc.v:198632.3-198646.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198354.3-198369.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_msr$next[63:0]$13628 - attribute \src "libresoc.v:193264.14-193264.45" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_msr$next[63:0]$13810 + attribute \src "libresoc.v:195554.14-195554.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13651 - attribute \src "libresoc.v:193272.14-193272.37" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13833 + attribute \src "libresoc.v:195562.14-195562.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_rego_ok$next[0:0]$13972 - attribute \src "libresoc.v:193276.7-193276.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_rego_ok$next[0:0]$14157 + attribute \src "libresoc.v:195566.7-195566.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_spro_ok$next[0:0]$13973 - attribute \src "libresoc.v:193280.7-193280.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_spro_ok$next[0:0]$14158 + attribute \src "libresoc.v:195570.7-195570.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:199449.3-199479.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:196474.3-196486.6" + attribute \src "libresoc.v:198761.3-198773.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $1\core_sv_a_nz$next[0:0]$13661 - attribute \src "libresoc.v:193292.7-193292.26" + attribute \src "libresoc.v:198165.3-198189.6" + wire $1\core_sv_a_nz$next[0:0]$13843 + attribute \src "libresoc.v:195582.7-195582.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:196011.3-196020.6" - wire width 3 $1\core_wen$11[2:0]$13671 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_xer_out$next[0:0]$13974 - attribute \src "libresoc.v:193302.7-193302.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_xer_out$next[0:0]$14159 + attribute \src "libresoc.v:195592.7-195592.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:193308.7-193308.30" + attribute \src "libresoc.v:195598.7-195598.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13760 - attribute \src "libresoc.v:193314.13-193314.36" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13943 + attribute \src "libresoc.v:195604.13-195604.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13761 - attribute \src "libresoc.v:193318.13-193318.34" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13944 + attribute \src "libresoc.v:195608.13-195608.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13762 - attribute \src "libresoc.v:193322.13-193322.36" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13945 + attribute \src "libresoc.v:195612.13-195612.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13763 - attribute \src "libresoc.v:193326.13-193326.33" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13946 + attribute \src "libresoc.v:195616.13-195616.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13764 - attribute \src "libresoc.v:193330.13-193330.34" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13947 + attribute \src "libresoc.v:195620.13-195620.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13765 - attribute \src "libresoc.v:193334.13-193334.31" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13948 + attribute \src "libresoc.v:195624.13-195624.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:196193.3-196201.6" - wire $1\d_cr_delay$next[0:0]$13696 - attribute \src "libresoc.v:193338.7-193338.24" + attribute \src "libresoc.v:198480.3-198488.6" + wire $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:195628.7-195628.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:196154.3-196162.6" - wire $1\d_reg_delay$next[0:0]$13690 - attribute \src "libresoc.v:193342.7-193342.25" + attribute \src "libresoc.v:198441.3-198449.6" + wire $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:195632.7-195632.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:196232.3-196240.6" - wire $1\d_xer_delay$next[0:0]$13702 - attribute \src "libresoc.v:193346.7-193346.25" + attribute \src "libresoc.v:198519.3-198527.6" + wire $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:195636.7-195636.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199480.3-199510.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196212.3-196221.6" + attribute \src "libresoc.v:198499.3-198508.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196202.3-196211.6" + attribute \src "libresoc.v:198489.3-198498.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196173.3-196182.6" + attribute \src "libresoc.v:198460.3-198469.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196163.3-196172.6" + attribute \src "libresoc.v:198450.3-198459.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196251.3-196260.6" + attribute \src "libresoc.v:198538.3-198547.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196241.3-196250.6" + attribute \src "libresoc.v:198528.3-198537.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:195751.3-195759.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13598 - attribute \src "libresoc.v:193394.13-193394.34" + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:195684.13-195684.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:196487.3-196495.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13737 - attribute \src "libresoc.v:193398.14-193398.48" + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:195688.14-195688.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:195760.3-195768.6" - wire $1\dbg_dmi_req_i$next[0:0]$13601 - attribute \src "libresoc.v:193404.7-193404.27" + attribute \src "libresoc.v:198046.3-198054.6" + wire $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:195694.7-195694.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:196402.3-196410.6" - wire $1\dbg_dmi_we_i$next[0:0]$13724 - attribute \src "libresoc.v:193408.7-193408.26" + attribute \src "libresoc.v:198689.3-198697.6" + wire $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:195698.7-195698.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13719 - attribute \src "libresoc.v:193462.14-193462.49" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13902 + attribute \src "libresoc.v:195752.14-195752.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:195769.3-195777.6" - wire $1\dec2_cur_eint$next[0:0]$13604 - attribute \src "libresoc.v:193466.7-193466.27" + attribute \src "libresoc.v:198055.3-198063.6" + wire $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:195756.7-195756.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13803 - attribute \src "libresoc.v:193470.14-193470.49" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13986 + attribute \src "libresoc.v:195760.14-195760.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13750 - attribute \src "libresoc.v:193474.14-193474.48" + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13933 + attribute \src "libresoc.v:195764.14-195764.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13812 - attribute \src "libresoc.v:193626.14-193626.40" + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:195916.14-195916.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:195778.3-195787.6" - wire width 2 $1\delay$next[1:0]$13607 - attribute \src "libresoc.v:193896.13-193896.25" + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:196186.13-196186.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $1\exec_fsm_state$next[0:0]$13680 - attribute \src "libresoc.v:193912.7-193912.28" + attribute \src "libresoc.v:198370.3-198404.6" + wire $1\exec_fsm_state$next[0:0]$13863 + attribute \src "libresoc.v:196202.7-196202.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:196031.3-196041.6" + attribute \src "libresoc.v:198318.3-198328.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:195942.3-195952.6" + attribute \src "libresoc.v:198250.3-198260.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198261.3-198276.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13795 - attribute \src "libresoc.v:193924.13-193924.35" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13978 + attribute \src "libresoc.v:196214.13-196214.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:197394.3-197404.6" + attribute \src "libresoc.v:199702.3-199712.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:196976.3-196986.6" + attribute \src "libresoc.v:199263.3-199273.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196657.3-196667.6" + attribute \src "libresoc.v:198944.3-198954.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199334.3-199349.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $1\fsm_state$next[1:0]$13709 - attribute \src "libresoc.v:193936.13-193936.29" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $1\fsm_state$next[1:0]$13892 + attribute \src "libresoc.v:196226.13-196226.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $1\issue_fsm_state$next[2:0]$13820 - attribute \src "libresoc.v:194196.13-194196.35" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $1\issue_fsm_state$next[2:0]$14003 + attribute \src "libresoc.v:196486.13-196486.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:196648.3-196656.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:194200.7-194200.30" + attribute \src "libresoc.v:198935.3-198943.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:196490.7-196490.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:196812.3-196820.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13786 - attribute \src "libresoc.v:194208.14-194208.52" + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:196498.14-196498.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:196821.3-196850.6" - wire $1\msr_read$next[0:0]$13789 - attribute \src "libresoc.v:194266.7-194266.22" + attribute \src "libresoc.v:199108.3-199137.6" + wire $1\msr_read$next[0:0]$13972 + attribute \src "libresoc.v:196556.7-196556.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:196319.3-196329.6" + attribute \src "libresoc.v:198606.3-198616.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:196391.3-196401.6" + attribute \src "libresoc.v:198678.3-198688.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $1\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $1\nia$next[63:0]$13808 - attribute \src "libresoc.v:194304.14-194304.40" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:196596.14-196596.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $1\pc_changed$next[0:0]$13834 - attribute \src "libresoc.v:194310.7-194310.24" + attribute \src "libresoc.v:199511.3-199577.6" + wire $1\pc_changed$next[0:0]$14019 + attribute \src "libresoc.v:196602.7-196602.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:196411.3-196419.6" - wire $1\pc_ok_delay$next[0:0]$13727 - attribute \src "libresoc.v:194320.7-194320.25" + attribute \src "libresoc.v:198698.3-198706.6" + wire $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:196612.7-196612.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:197327.3-197393.6" - wire $1\sv_changed$next[0:0]$13846 - attribute \src "libresoc.v:194764.7-194764.24" + attribute \src "libresoc.v:198228.3-198238.6" + wire $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $1\sv_changed$next[0:0]$14031 + attribute \src "libresoc.v:197056.7-197056.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:196449.3-196457.6" - wire $1\svstate_ok_delay$next[0:0]$13732 - attribute \src "libresoc.v:194774.7-194774.30" + attribute \src "libresoc.v:198736.3-198744.6" + wire $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:197066.7-197066.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_asmcode$next[7:0]$13975 - attribute \src "libresoc.v:195854.3-195878.6" - wire $2\core_bigendian_i$10$next[0:0]$13657 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13976 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13977 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13978 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13979 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13980 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13981 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13982 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13983 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13984 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13985 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13986 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13987 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$13988 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13989 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13990 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13991 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_is_32bit$next[0:0]$13992 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13993 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_oe$next[0:0]$13994 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_oe_ok$next[0:0]$13995 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_rc$next[0:0]$13996 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_rc_ok$next[0:0]$13997 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13998 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13999 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14000 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14001 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14002 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14003 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14004 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14005 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14006 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14007 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_dststep$next[6:0]$13629 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_ea$next[6:0]$14008 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fast1$next[2:0]$14009 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_fast1_ok$next[0:0]$14010 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fast2$next[2:0]$14011 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_fast2_ok$next[0:0]$14012 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14013 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14014 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_lk$next[0:0]$14015 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13630 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_core_pc$next[63:0]$13631 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg1$next[6:0]$14016 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg1_ok$next[0:0]$14017 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg2$next[6:0]$14018 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg2_ok$next[0:0]$14019 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg3$next[6:0]$14020 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg3_ok$next[0:0]$14021 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_rego$next[6:0]$14022 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $2\core_core_spr1$next[9:0]$14023 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_spr1_ok$next[0:0]$14024 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $2\core_core_spro$next[9:0]$14025 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13632 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $2\core_core_subvl$next[1:0]$13633 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $2\core_core_svstep$next[1:0]$13634 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_vl$next[6:0]$13635 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14026 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_cr_out_ok$next[0:0]$14027 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_asmcode$next[7:0]$14160 + attribute \src "libresoc.v:198140.3-198164.6" + wire $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14161 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14162 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14163 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14164 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14165 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14166 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14167 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14168 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14169 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14170 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14171 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14172 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$14173 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14174 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14175 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14176 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_is_32bit$next[0:0]$14177 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14178 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe$next[0:0]$14179 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe_ok$next[0:0]$14180 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc$next[0:0]$14181 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc_ok$next[0:0]$14182 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14183 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14184 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14185 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14186 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14187 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14188 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14189 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14190 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14191 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14192 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_dststep$next[6:0]$13811 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_ea$next[6:0]$14193 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast1$next[2:0]$14194 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast1_ok$next[0:0]$14195 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast2$next[2:0]$14196 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast2_ok$next[0:0]$14197 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14198 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14199 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_lk$next[0:0]$14200 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13812 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_core_pc$next[63:0]$13813 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg1$next[6:0]$14201 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg1_ok$next[0:0]$14202 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg2$next[6:0]$14203 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg2_ok$next[0:0]$14204 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg3$next[6:0]$14205 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg3_ok$next[0:0]$14206 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_rego$next[6:0]$14207 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spr1$next[9:0]$14208 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_spr1_ok$next[0:0]$14209 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spro$next[9:0]$14210 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13814 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_subvl$next[1:0]$13815 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_svstep$next[1:0]$13816 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_vl$next[6:0]$13817 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14211 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_cr_out_ok$next[0:0]$14212 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_dec$next[63:0]$13636 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_ea_ok$next[0:0]$14028 - attribute \src "libresoc.v:195788.3-195832.6" - wire $2\core_eint$next[0:0]$13637 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_fasto1_ok$next[0:0]$14029 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_fasto2_ok$next[0:0]$14030 - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_dec$next[63:0]$13818 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_ea_ok$next[0:0]$14213 + attribute \src "libresoc.v:198074.3-198118.6" + wire $2\core_eint$next[0:0]$13819 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto1_ok$next[0:0]$14214 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto2_ok$next[0:0]$14215 + attribute \src "libresoc.v:198354.3-198369.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_msr$next[63:0]$13638 - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_msr$next[63:0]$13820 + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13652 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_rego_ok$next[0:0]$14031 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_spro_ok$next[0:0]$14032 - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_rego_ok$next[0:0]$14216 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_spro_ok$next[0:0]$14217 + attribute \src "libresoc.v:199449.3-199479.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $2\core_sv_a_nz$next[0:0]$13662 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198165.3-198189.6" + wire $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_xer_out$next[0:0]$14033 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13766 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13767 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13768 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13769 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13770 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13771 - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_xer_out$next[0:0]$14218 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13949 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13950 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13951 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13952 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13953 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "libresoc.v:199480.3-199510.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13720 - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13804 - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13751 - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13813 - attribute \src "libresoc.v:196083.3-196117.6" - wire $2\exec_fsm_state$next[0:0]$13681 - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "libresoc.v:198370.3-198404.6" + wire $2\exec_fsm_state$next[0:0]$13864 + attribute \src "libresoc.v:198261.3-198276.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13796 - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "libresoc.v:199334.3-199349.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $2\fsm_state$next[1:0]$13710 - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $2\issue_fsm_state$next[2:0]$13821 - attribute \src "libresoc.v:196821.3-196850.6" - wire $2\msr_read$next[0:0]$13790 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "libresoc.v:199108.3-199137.6" + wire $2\msr_read$next[0:0]$13973 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $2\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $2\nia$next[63:0]$13809 - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $2\nia$next[63:0]$13992 + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $2\pc_changed$next[0:0]$13835 - attribute \src "libresoc.v:197327.3-197393.6" - wire $2\sv_changed$next[0:0]$13847 - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $2\pc_changed$next[0:0]$14020 + attribute \src "libresoc.v:199635.3-199701.6" + wire $2\sv_changed$next[0:0]$14032 + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $3\core_bigendian_i$10$next[0:0]$13658 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14034 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14035 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14036 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14037 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14038 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14039 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14040 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14041 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14042 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_oe_ok$next[0:0]$14043 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_rc_ok$next[0:0]$14044 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14045 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14046 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14047 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14048 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_dststep$next[6:0]$13639 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_fast1_ok$next[0:0]$14049 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_fast2_ok$next[0:0]$14050 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13640 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_core_pc$next[63:0]$13641 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg1_ok$next[0:0]$14051 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg2_ok$next[0:0]$14052 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg3_ok$next[0:0]$14053 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_spr1_ok$next[0:0]$14054 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13642 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $3\core_core_subvl$next[1:0]$13643 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $3\core_core_svstep$next[1:0]$13644 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_vl$next[6:0]$13645 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_cr_out_ok$next[0:0]$14055 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14219 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14220 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14221 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14222 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14223 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14224 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14225 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14226 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14227 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_oe_ok$next[0:0]$14228 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_rc_ok$next[0:0]$14229 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14230 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14231 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14232 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14233 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_dststep$next[6:0]$13821 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast1_ok$next[0:0]$14234 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast2_ok$next[0:0]$14235 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13822 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_core_pc$next[63:0]$13823 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg1_ok$next[0:0]$14236 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg2_ok$next[0:0]$14237 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg3_ok$next[0:0]$14238 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_spr1_ok$next[0:0]$14239 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13824 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_subvl$next[1:0]$13825 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_svstep$next[1:0]$13826 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_vl$next[6:0]$13827 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_cr_out_ok$next[0:0]$14240 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_dec$next[63:0]$13646 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_ea_ok$next[0:0]$14056 - attribute \src "libresoc.v:195788.3-195832.6" - wire $3\core_eint$next[0:0]$13647 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_fasto1_ok$next[0:0]$14057 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_fasto2_ok$next[0:0]$14058 - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_dec$next[63:0]$13828 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_ea_ok$next[0:0]$14241 + attribute \src "libresoc.v:198074.3-198118.6" + wire $3\core_eint$next[0:0]$13829 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto1_ok$next[0:0]$14242 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto2_ok$next[0:0]$14243 + attribute \src "libresoc.v:198329.3-198353.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_msr$next[63:0]$13648 - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13653 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_rego_ok$next[0:0]$14059 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_spro_ok$next[0:0]$14060 - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_rego_ok$next[0:0]$14244 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199449.3-199479.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $3\core_sv_a_nz$next[0:0]$13663 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198165.3-198189.6" + wire $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13772 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13773 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13774 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13775 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13776 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13777 - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13955 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13956 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13957 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13958 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13959 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13960 + attribute \src "libresoc.v:199480.3-199510.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13805 - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13752 - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13814 - attribute \src "libresoc.v:196083.3-196117.6" - wire $3\exec_fsm_state$next[0:0]$13682 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13797 - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "libresoc.v:198370.3-198404.6" + wire $3\exec_fsm_state$next[0:0]$13865 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "libresoc.v:198971.3-199004.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $3\issue_fsm_state$next[2:0]$13822 - attribute \src "libresoc.v:196821.3-196850.6" - wire $3\msr_read$next[0:0]$13791 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "libresoc.v:199108.3-199137.6" + wire $3\msr_read$next[0:0]$13974 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $3\next_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $3\pc_changed$next[0:0]$13836 - attribute \src "libresoc.v:197327.3-197393.6" - wire $3\sv_changed$next[0:0]$13848 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $3\pc_changed$next[0:0]$14021 + attribute \src "libresoc.v:199635.3-199701.6" + wire $3\sv_changed$next[0:0]$14033 + attribute \src "libresoc.v:199578.3-199634.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13778 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13779 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13780 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13781 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13782 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13783 - attribute \src "libresoc.v:196083.3-196117.6" - wire $4\exec_fsm_state$next[0:0]$13683 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13798 - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13961 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13962 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13963 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13964 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13965 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:198370.3-198404.6" + wire $4\exec_fsm_state$next[0:0]$13866 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "libresoc.v:198971.3-199004.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $4\issue_fsm_state$next[2:0]$13823 - attribute \src "libresoc.v:196821.3-196850.6" - wire $4\msr_read$next[0:0]$13792 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "libresoc.v:199108.3-199137.6" + wire $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $4\pc_changed$next[0:0]$13837 - attribute \src "libresoc.v:197327.3-197393.6" - wire $4\sv_changed$next[0:0]$13849 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $4\pc_changed$next[0:0]$14022 + attribute \src "libresoc.v:199635.3-199701.6" + wire $4\sv_changed$next[0:0]$14034 + attribute \src "libresoc.v:199578.3-199634.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $5\exec_fsm_state$next[0:0]$13684 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13799 - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198370.3-198404.6" + wire $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "libresoc.v:198190.3-198227.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $5\issue_fsm_state$next[2:0]$13824 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $5\pc_changed$next[0:0]$13838 - attribute \src "libresoc.v:197327.3-197393.6" - wire $5\sv_changed$next[0:0]$13850 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $5\pc_changed$next[0:0]$14023 + attribute \src "libresoc.v:199635.3-199701.6" + wire $5\sv_changed$next[0:0]$14035 + attribute \src "libresoc.v:199578.3-199634.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13800 - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:198190.3-198227.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $6\issue_fsm_state$next[2:0]$13825 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $6\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $6\pc_changed$next[0:0]$13839 - attribute \src "libresoc.v:197327.3-197393.6" - wire $6\sv_changed$next[0:0]$13851 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $6\pc_changed$next[0:0]$14024 + attribute \src "libresoc.v:199635.3-199701.6" + wire $6\sv_changed$next[0:0]$14036 + attribute \src "libresoc.v:199578.3-199634.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $7\issue_fsm_state$next[2:0]$13826 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $7\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $7\pc_changed$next[0:0]$13840 - attribute \src "libresoc.v:197327.3-197393.6" - wire $7\sv_changed$next[0:0]$13852 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $7\pc_changed$next[0:0]$14025 + attribute \src "libresoc.v:199635.3-199701.6" + wire $7\sv_changed$next[0:0]$14037 + attribute \src "libresoc.v:199578.3-199634.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $8\issue_fsm_state$next[2:0]$13827 - attribute \src "libresoc.v:197203.3-197269.6" - wire $8\pc_changed$next[0:0]$13841 - attribute \src "libresoc.v:197327.3-197393.6" - wire $8\sv_changed$next[0:0]$13853 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "libresoc.v:199511.3-199577.6" + wire $8\pc_changed$next[0:0]$14026 + attribute \src "libresoc.v:199635.3-199701.6" + wire $8\sv_changed$next[0:0]$14038 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $9\issue_fsm_state$next[2:0]$13828 - attribute \src "libresoc.v:197203.3-197269.6" - wire $9\pc_changed$next[0:0]$13842 - attribute \src "libresoc.v:197327.3-197393.6" - wire $9\sv_changed$next[0:0]$13854 - attribute \src "libresoc.v:194791.19-194791.108" - wire width 65 $add$libresoc.v:194791$13361_Y - attribute \src "libresoc.v:194864.19-194864.112" - wire width 8 $add$libresoc.v:194864$13431_Y - attribute \src "libresoc.v:194877.19-194877.115" - wire width 65 $add$libresoc.v:194877$13446_Y - attribute \src "libresoc.v:194910.18-194910.107" - wire width 65 $add$libresoc.v:194910$13478_Y - attribute \src "libresoc.v:194796.19-194796.104" - wire $and$libresoc.v:194796$13366_Y - attribute \src "libresoc.v:194799.19-194799.104" - wire $and$libresoc.v:194799$13369_Y - attribute \src "libresoc.v:194805.19-194805.104" - wire $and$libresoc.v:194805$13374_Y - attribute \src "libresoc.v:194808.19-194808.104" - wire $and$libresoc.v:194808$13377_Y - attribute \src "libresoc.v:194810.19-194810.111" - wire $and$libresoc.v:194810$13379_Y - attribute \src "libresoc.v:194813.19-194813.104" - wire $and$libresoc.v:194813$13382_Y - attribute \src "libresoc.v:194819.19-194819.104" - wire $and$libresoc.v:194819$13387_Y - attribute \src "libresoc.v:194822.19-194822.104" - wire $and$libresoc.v:194822$13390_Y - attribute \src "libresoc.v:194825.19-194825.104" - wire $and$libresoc.v:194825$13393_Y - attribute \src "libresoc.v:194828.19-194828.104" - wire $and$libresoc.v:194828$13396_Y - attribute \src "libresoc.v:194831.19-194831.104" - wire $and$libresoc.v:194831$13399_Y - attribute \src "libresoc.v:194834.19-194834.104" - wire $and$libresoc.v:194834$13402_Y - attribute \src "libresoc.v:194835.19-194835.115" - wire width 3 $and$libresoc.v:194835$13403_Y - attribute \src "libresoc.v:194839.19-194839.104" - wire $and$libresoc.v:194839$13407_Y - attribute \src "libresoc.v:194842.19-194842.104" - wire $and$libresoc.v:194842$13410_Y - attribute \src "libresoc.v:194848.19-194848.104" - wire $and$libresoc.v:194848$13415_Y - attribute \src "libresoc.v:194851.19-194851.104" - wire $and$libresoc.v:194851$13418_Y - attribute \src "libresoc.v:194852.19-194852.115" - wire width 3 $and$libresoc.v:194852$13419_Y - attribute \src "libresoc.v:194855.19-194855.111" - wire $and$libresoc.v:194855$13422_Y - attribute \src "libresoc.v:194859.19-194859.104" - wire $and$libresoc.v:194859$13426_Y - attribute \src "libresoc.v:194863.19-194863.104" - wire $and$libresoc.v:194863$13430_Y - attribute \src "libresoc.v:194867.19-194867.104" - wire $and$libresoc.v:194867$13434_Y - attribute \src "libresoc.v:194882.18-194882.109" - wire $and$libresoc.v:194882$13451_Y - attribute \src "libresoc.v:194888.18-194888.101" - wire $and$libresoc.v:194888$13458_Y - attribute \src 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"libresoc.v:194874.19-194874.113" - wire width 64 $extend$libresoc.v:194874$13442_Y - attribute \src "libresoc.v:194885.18-194885.109" - wire width 64 $extend$libresoc.v:194885$13454_Y - attribute \src "libresoc.v:194792.19-194792.106" - wire width 7 $mul$libresoc.v:194792$13362_Y - attribute \src "libresoc.v:194911.18-194911.110" - wire width 7 $mul$libresoc.v:194911$13479_Y - attribute \src "libresoc.v:194861.18-194861.102" - wire $ne$libresoc.v:194861$13428_Y - attribute \src "libresoc.v:194870.19-194870.123" - wire $ne$libresoc.v:194870$13437_Y - attribute \src "libresoc.v:194880.18-194880.102" - wire $ne$libresoc.v:194880$13449_Y - attribute \src "libresoc.v:194794.19-194794.107" - wire $not$libresoc.v:194794$13364_Y - attribute \src "libresoc.v:194795.19-194795.109" - wire $not$libresoc.v:194795$13365_Y - attribute \src "libresoc.v:194797.19-194797.107" - wire $not$libresoc.v:194797$13367_Y - attribute \src "libresoc.v:194798.19-194798.109" - wire $not$libresoc.v:194798$13368_Y - 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width 64 $pos$libresoc.v:197175$13637_Y + attribute \src "libresoc.v:197130.19-197130.93" + wire $reduce_or$libresoc.v:197130$13590_Y + attribute \src "libresoc.v:197147.19-197147.93" + wire $reduce_or$libresoc.v:197147$13606_Y + attribute \src "libresoc.v:197085.18-197085.41" + wire width 64 $shr$libresoc.v:197085$13547_Y + attribute \src "libresoc.v:197202.18-197202.40" + wire width 64 $shr$libresoc.v:197202$13662_Y + attribute \src "libresoc.v:197165.19-197165.116" + wire width 65 $sub$libresoc.v:197165$13626_Y + attribute \src "libresoc.v:197167.18-197167.101" + wire width 3 $sub$libresoc.v:197167$13628_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + wire width 8 \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + wire width 8 \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + wire width 8 \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + wire width 8 \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$186 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - wire width 3 \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + wire width 3 \$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$220 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - wire width 3 \$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + wire width 3 \$229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - wire width 8 \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - wire width 8 \$245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - wire \$253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + wire \$250 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - wire \$257 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + wire width 64 \$252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + wire \$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + wire \$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + wire \$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 3 \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$261 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$263 + wire width 64 \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 64 \$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + wire width 65 \$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + wire width 65 \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" wire width 65 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" wire width 65 \$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - wire width 65 \$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - wire width 65 \$271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" wire width 65 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" wire width 65 \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 342 \TAP_bus__tck + wire input 338 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 178 \TAP_bus__tdi + wire input 176 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 333 \TAP_bus__tdo + wire output 329 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 343 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" + wire input 339 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 392 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 388 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10 @@ -403552,7 +407551,7 @@ module \ti wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -403662,7 +407661,7 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly @@ -403694,17 +407693,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -403790,7 +407789,7 @@ module \ti wire output 15 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec2_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_cia @@ -403982,9 +407981,9 @@ module \ti wire \dec2_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc @@ -404242,7 +408241,7 @@ module \ti wire width 10 \dec2_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec2_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \dec2_trapaddr @@ -404252,52 +408251,52 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \eint_0__core__i + wire output 177 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \eint_1__core__i + wire output 178 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \eint_2__core__i + wire output 179 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883" wire \exec_pc_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:863" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e10__core__i + wire output 186 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404305,11 +408304,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e10__pad__o + wire output 187 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e10__pad__oe + wire output 188 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e11__core__i + wire output 189 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404317,11 +408316,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e11__pad__o + wire output 190 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e11__pad__oe + wire output 191 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e12__core__i + wire output 192 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404329,11 +408328,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e12__pad__o + wire output 193 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e12__pad__oe + wire output 194 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_e13__core__i + wire output 195 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404341,11 +408340,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_e13__pad__o + wire output 196 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_e13__pad__oe + wire output 197 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_e14__core__i + wire output 198 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404353,11 +408352,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_e14__pad__o + wire output 199 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_e14__pad__oe + wire output 200 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_e15__core__i + wire output 201 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404365,11 +408364,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_e15__pad__o + wire output 202 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_e15__pad__oe + wire output 203 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e8__core__i + wire output 180 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404377,11 +408376,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e8__pad__o + wire output 181 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e8__pad__oe + wire output 182 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e9__core__i + wire output 183 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404389,11 +408388,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e9__pad__o + wire output 184 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e9__pad__oe + wire output 185 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s0__core__i + wire output 204 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404401,11 +408400,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s0__pad__o + wire output 205 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s0__pad__oe + wire output 206 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s1__core__i + wire output 207 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404413,11 +408412,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s1__pad__o + wire output 208 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s1__pad__oe + wire output 209 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s2__core__i + wire output 210 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404425,11 +408424,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s2__pad__o + wire output 211 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s2__pad__oe + wire output 212 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s3__core__i + wire output 213 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404437,11 +408436,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s3__pad__o + wire output 214 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s3__pad__oe + wire output 215 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s4__core__i + wire output 216 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404449,11 +408448,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s4__pad__o + wire output 217 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s4__pad__oe + wire output 218 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \gpio_s5__core__i + wire output 219 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404461,11 +408460,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \gpio_s5__pad__o + wire output 220 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \gpio_s5__pad__oe + wire output 221 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \gpio_s6__core__i + wire output 222 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404473,11 +408472,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \gpio_s6__pad__o + wire output 223 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \gpio_s6__pad__oe + wire output 224 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \gpio_s7__core__i + wire output 225 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404485,9 +408484,9 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \gpio_s7__pad__o + wire output 226 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \gpio_s7__pad__oe + wire output 227 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -404503,35 +408502,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 376 \icp_wb__ack + wire output 372 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 382 \icp_wb__adr + wire width 28 input 378 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 377 \icp_wb__cyc + wire input 373 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 378 \icp_wb__dat_r + wire width 32 output 374 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 379 \icp_wb__dat_w + wire width 32 input 375 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 383 \icp_wb__sel + wire width 4 input 379 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 380 \icp_wb__stb + wire input 376 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 381 \icp_wb__we + wire input 377 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 389 \ics_wb__ack + wire output 385 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 384 \ics_wb__adr + wire width 28 input 380 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 386 \ics_wb__cyc + wire input 382 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 388 \ics_wb__dat_r + wire width 32 output 384 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 390 \ics_wb__dat_w + wire width 32 input 386 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 387 \ics_wb__stb + wire input 383 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 391 \ics_wb__we + wire input 387 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -404544,19 +408543,19 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:192354.7-192354.15" + attribute \src "libresoc.v:194646.7-194646.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 385 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + wire width 16 input 381 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" wire \is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" wire width 3 \issue_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o @@ -404575,65 +408574,65 @@ module \ti attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 340 \jtag_wb__ack + wire input 336 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 334 \jtag_wb__adr + wire width 29 output 330 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 336 \jtag_wb__cyc + wire output 332 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 341 \jtag_wb__dat_r + wire width 64 input 337 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 339 \jtag_wb__dat_w + wire width 64 output 335 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 335 \jtag_wb__sel + wire output 331 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 337 \jtag_wb__stb + wire output 333 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 338 \jtag_wb__we + wire output 334 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mspi0_clk__pad__o + wire output 228 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mspi0_cs_n__pad__o + wire output 229 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \mspi0_miso__core__i + wire output 231 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mspi0_mosi__pad__o + wire output 230 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \mspi1_clk__pad__o + wire output 232 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \mspi1_cs_n__pad__o + wire output 233 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \mspi1_miso__core__i + wire output 235 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 82 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire output 234 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \mtwi_scl__pad__o + wire output 239 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \mtwi_sda__core__i + wire output 236 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404641,10 +408640,10 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \mtwi_sda__pad__o + wire output 237 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" + wire output 238 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -404658,48 +408657,58 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" + wire width 7 \next_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + wire \pred_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" + wire \pred_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + wire \pred_mask_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" + wire \pred_mask_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \pwm_0__pad__o + wire output 240 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 88 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire output 241 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_clk__pad__o + wire output 245 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_cmd__core__i + wire output 242 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404707,11 +408716,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_cmd__pad__o + wire output 243 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_cmd__pad__oe + wire output 244 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data0__core__i + wire output 246 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404719,11 +408728,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data0__pad__o + wire output 247 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data0__pad__oe + wire output 248 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sd0_data1__core__i + wire output 249 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404731,11 +408740,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sd0_data1__pad__o + wire output 250 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sd0_data1__pad__oe + wire output 251 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sd0_data2__core__i + wire output 252 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404743,11 +408752,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sd0_data2__pad__o + wire output 253 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sd0_data2__pad__oe + wire output 254 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sd0_data3__core__i + wire output 255 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404755,103 +408764,95 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sd0_data3__pad__o + wire output 256 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sd0_data3__pad__oe + wire output 257 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_0__pad__o + wire output 283 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 148 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_a_10__pad__o + wire output 301 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 149 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_a_11__pad__o + wire output 302 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 150 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_a_12__pad__o + wire output 303 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_a_1__pad__o + wire output 284 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_2__pad__o + wire output 285 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_3__pad__o + wire output 286 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_4__pad__o + wire output 287 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_5__pad__o + wire output 288 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_6__pad__o + wire output 289 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_7__pad__o + wire output 290 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 138 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_a_8__pad__o + wire output 291 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 139 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_a_9__pad__o + wire output 292 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 140 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_ba_0__pad__o + wire output 293 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 141 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_ba_1__pad__o + wire output 294 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_cas_n__pad__o + wire output 298 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 143 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_cke__pad__o + wire output 296 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 142 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_clock__pad__o + wire output 295 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 147 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_cs_n__pad__o + wire output 300 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dm_0__pad__o + wire output 258 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dm_1__core__i + wire input 151 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dm_1__core__o + wire output 304 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_0__core__i + wire output 259 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 107 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404859,83 +408860,83 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_0__pad__o + wire output 260 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_0__pad__oe + wire output 261 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_10__core__i + wire output 311 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_10__core__o + wire input 159 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_10__core__oe + wire input 160 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_10__pad__i + wire input 158 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_10__pad__o + wire output 312 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_10__pad__oe + wire output 313 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_11__core__i + wire output 314 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_11__core__o + wire input 162 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_11__core__oe + wire input 163 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_11__pad__i + wire input 161 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_11__pad__o + wire output 315 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_11__pad__oe + wire output 316 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_12__core__i + wire output 317 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_12__core__o + wire input 165 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_12__core__oe + wire input 166 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_12__pad__i + wire input 164 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_12__pad__o + wire output 318 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_12__pad__oe + wire output 319 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 324 \sdr_dq_13__core__i + wire output 320 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_13__core__o + wire input 168 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_13__core__oe + wire input 169 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 169 \sdr_dq_13__pad__i + wire input 167 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_13__pad__o + wire output 321 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_13__pad__oe + wire output 322 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 327 \sdr_dq_14__core__i + wire output 323 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 173 \sdr_dq_14__core__o + wire input 171 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 174 \sdr_dq_14__core__oe + wire input 172 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_14__pad__i + wire input 170 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 328 \sdr_dq_14__pad__o + wire output 324 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 329 \sdr_dq_14__pad__oe + wire output 325 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 330 \sdr_dq_15__core__i + wire output 326 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sdr_dq_15__core__o + wire input 174 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sdr_dq_15__core__oe + wire input 175 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 175 \sdr_dq_15__pad__i + wire input 173 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 331 \sdr_dq_15__pad__o + wire output 327 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 332 \sdr_dq_15__pad__oe + wire output 328 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_1__core__i + wire output 262 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 110 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404943,11 +408944,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_1__pad__o + wire output 263 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_1__pad__oe + wire output 264 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_2__core__i + wire output 265 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 113 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404955,11 +408956,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_2__pad__o + wire output 266 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_2__pad__oe + wire output 267 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_3__core__i + wire output 268 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 116 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404967,11 +408968,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_3__pad__o + wire output 269 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_3__pad__oe + wire output 270 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_4__core__i + wire output 271 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404979,11 +408980,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_4__pad__o + wire output 272 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_4__pad__oe + wire output 273 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_5__core__i + wire output 274 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404991,11 +408992,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_5__pad__o + wire output 275 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_5__pad__oe + wire output 276 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_6__core__i + wire output 277 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -405003,11 +409004,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_6__pad__o + wire output 278 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_6__pad__oe + wire output 279 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_7__core__i + wire output 280 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -405015,130 +409016,130 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_7__pad__o + wire output 281 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_7__pad__oe + wire output 282 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_8__core__i + wire output 305 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_8__core__o + wire input 153 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_8__core__oe + wire input 154 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_8__pad__i + wire input 152 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_8__pad__o + wire output 306 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_8__pad__oe + wire output 307 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_9__core__i + wire output 308 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_9__core__o + wire input 156 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_9__core__oe + wire input 157 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_9__pad__i + wire input 155 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_9__pad__o + wire output 309 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_9__pad__oe + wire output 310 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 144 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_ras_n__pad__o + wire output 297 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_we_n__pad__o + wire output 299 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_0_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 346 \sram4k_0_wb__ack + wire output 342 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 347 \sram4k_0_wb__adr + wire width 9 input 343 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 344 \sram4k_0_wb__cyc + wire input 340 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 348 \sram4k_0_wb__dat_r + wire width 64 output 344 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 349 \sram4k_0_wb__dat_w + wire width 64 input 345 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 351 \sram4k_0_wb__sel + wire width 8 input 347 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 345 \sram4k_0_wb__stb + wire input 341 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 350 \sram4k_0_wb__we + wire input 346 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_1_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 354 \sram4k_1_wb__ack + wire output 350 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 355 \sram4k_1_wb__adr + wire width 9 input 351 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 352 \sram4k_1_wb__cyc + wire input 348 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 356 \sram4k_1_wb__dat_r + wire width 64 output 352 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 357 \sram4k_1_wb__dat_w + wire width 64 input 353 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 359 \sram4k_1_wb__sel + wire width 8 input 355 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_1_wb__stb + wire input 349 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 358 \sram4k_1_wb__we + wire input 354 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_2_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 362 \sram4k_2_wb__ack + wire output 358 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 363 \sram4k_2_wb__adr + wire width 9 input 359 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 360 \sram4k_2_wb__cyc + wire input 356 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 364 \sram4k_2_wb__dat_r + wire width 64 output 360 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 365 \sram4k_2_wb__dat_w + wire width 64 input 361 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 367 \sram4k_2_wb__sel + wire width 8 input 363 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 361 \sram4k_2_wb__stb + wire input 357 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 366 \sram4k_2_wb__we + wire input 362 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_3_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 370 \sram4k_3_wb__ack + wire output 366 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 371 \sram4k_3_wb__adr + wire width 9 input 367 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 368 \sram4k_3_wb__cyc + wire input 364 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 372 \sram4k_3_wb__dat_r + wire width 64 output 368 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 373 \sram4k_3_wb__dat_w + wire width 64 input 369 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 375 \sram4k_3_wb__sel + wire width 8 input 371 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 369 \sram4k_3_wb__stb + wire input 365 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 374 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + wire input 370 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \sv_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \svstate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \svstate_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:498" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -405150,8 +409151,8 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - cell $add $add$libresoc.v:194791$13361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + cell $add $add$libresoc.v:197083$13545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405159,10 +409160,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:194791$13361_Y + connect \Y $add$libresoc.v:197083$13545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $add $add$libresoc.v:194864$13431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + cell $add $add$libresoc.v:197095$13556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405170,10 +409171,21 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:194864$13431_Y + connect \Y $add$libresoc.v:197095$13556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - cell $add $add$libresoc.v:194877$13446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + cell $add $add$libresoc.v:197096$13557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \cur_cur_dststep + connect \B 1'1 + connect \Y $add$libresoc.v:197096$13557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + cell $add $add$libresoc.v:197166$13627 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405181,10 +409193,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:194877$13446_Y + connect \Y $add$libresoc.v:197166$13627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" - cell $add $add$libresoc.v:194910$13478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" + cell $add $add$libresoc.v:197200$13660 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405192,10 +409204,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:194910$13478_Y + connect \Y $add$libresoc.v:197200$13660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194796$13366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197088$13550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405203,10 +409215,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:194796$13366_Y + connect \Y $and$libresoc.v:197088$13550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194799$13369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197091$13553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405214,21 +409226,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:194799$13369_Y + connect \Y $and$libresoc.v:197091$13553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194805$13374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$124 - connect \B \$126 - connect \Y $and$libresoc.v:194805$13374_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194808$13377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197099$13560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405236,43 +409237,43 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:194808$13377_Y + connect \Y $and$libresoc.v:197099$13560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194810$13379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197102$13563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_svp64_mode - connect \B \$136 - connect \Y $and$libresoc.v:194810$13379_Y + connect \A \$136 + connect \B \$138 + connect \Y $and$libresoc.v:197102$13563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194813$13382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197104$13565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$140 + connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:194813$13382_Y + connect \Y $and$libresoc.v:197104$13565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194819$13387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197107$13568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$152 - connect \B \$154 - connect \Y $and$libresoc.v:194819$13387_Y + connect \A \$146 + connect \B \$148 + connect \Y $and$libresoc.v:197107$13568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194822$13390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197113$13573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405280,10 +409281,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:194822$13390_Y + connect \Y $and$libresoc.v:197113$13573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194825$13393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197116$13576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405291,10 +409292,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:194825$13393_Y + connect \Y $and$libresoc.v:197116$13576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194828$13396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197119$13579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405302,10 +409303,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:194828$13396_Y + connect \Y $and$libresoc.v:197119$13579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194831$13399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197122$13582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405313,10 +409314,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:194831$13399_Y + connect \Y $and$libresoc.v:197122$13582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194834$13402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197125$13585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405324,10 +409325,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:194834$13402_Y + connect \Y $and$libresoc.v:197125$13585_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - cell $and $and$libresoc.v:194835$13403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197128$13588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$188 + connect \B \$190 + connect \Y $and$libresoc.v:197128$13588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + cell $and $and$libresoc.v:197129$13589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -405335,54 +409347,54 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:194835$13403_Y + connect \Y $and$libresoc.v:197129$13589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194839$13407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197133$13593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$192 - connect \B \$194 - connect \Y $and$libresoc.v:194839$13407_Y + connect \A \$198 + connect \B \$200 + connect \Y $and$libresoc.v:197133$13593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194842$13410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197136$13596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$198 - connect \B \$200 - connect \Y $and$libresoc.v:194842$13410_Y + connect \A \$204 + connect \B \$206 + connect \Y $and$libresoc.v:197136$13596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194848$13415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197142$13601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$210 - connect \B \$212 - connect \Y $and$libresoc.v:194848$13415_Y + connect \A \$216 + connect \B \$218 + connect \Y $and$libresoc.v:197142$13601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194851$13418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197145$13604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$216 - connect \B \$218 - connect \Y $and$libresoc.v:194851$13418_Y + connect \A \$222 + connect \B \$224 + connect \Y $and$libresoc.v:197145$13604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - cell $and $and$libresoc.v:194852$13419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + cell $and $and$libresoc.v:197146$13605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -405390,32 +409402,21 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:194852$13419_Y + connect \Y $and$libresoc.v:197146$13605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194855$13422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197149$13608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode - connect \B \$226 - connect \Y $and$libresoc.v:194855$13422_Y + connect \B \$232 + connect \Y $and$libresoc.v:197149$13608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194859$13426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$232 - connect \B \$234 - connect \Y $and$libresoc.v:194859$13426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194863$13430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197154$13613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405423,21 +409424,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \$238 connect \B \$240 - connect \Y $and$libresoc.v:194863$13430_Y + connect \Y $and$libresoc.v:197154$13613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194867$13434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197157$13616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$247 - connect \B \$249 - connect \Y $and$libresoc.v:194867$13434_Y + connect \A \$244 + connect \B \$246 + connect \Y $and$libresoc.v:197157$13616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:194882$13451 + cell $and $and$libresoc.v:197172$13633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405445,10 +409446,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:194882$13451_Y + connect \Y $and$libresoc.v:197172$13633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194888$13458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197178$13640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405456,10 +409457,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:194888$13458_Y + connect \Y $and$libresoc.v:197178$13640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194890$13460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197180$13642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405467,10 +409468,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:194890$13460_Y + connect \Y $and$libresoc.v:197180$13642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194893$13463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197183$13645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405478,10 +409479,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:194893$13463_Y + connect \Y $and$libresoc.v:197183$13645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194899$13468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197189$13650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405489,10 +409490,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:194899$13468_Y + connect \Y $and$libresoc.v:197189$13650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194901$13470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197191$13652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405500,10 +409501,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:194901$13470_Y + connect \Y $and$libresoc.v:197191$13652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194904$13473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197194$13655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405511,10 +409512,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:194904$13473_Y + connect \Y $and$libresoc.v:197194$13655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194809$13378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197103$13564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405522,10 +409523,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194809$13378_Y + connect \Y $eq$libresoc.v:197103$13564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194854$13421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197148$13607 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405533,10 +409534,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194854$13421_Y + connect \Y $eq$libresoc.v:197148$13607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - cell $eq $eq$libresoc.v:194868$13435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + cell $eq $eq$libresoc.v:197158$13617 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405544,10 +409545,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:194868$13435_Y + connect \Y $eq$libresoc.v:197158$13617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194889$13459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197179$13641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405555,10 +409556,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194889$13459_Y + connect \Y $eq$libresoc.v:197179$13641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194900$13469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197190$13651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405566,34 +409567,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194900$13469_Y + connect \Y $eq$libresoc.v:197190$13651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:194873$13440 + cell $pos $extend$libresoc.v:197163$13622 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:194873$13440_Y + connect \Y $extend$libresoc.v:197163$13622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:194874$13442 + cell $pos $extend$libresoc.v:197164$13624 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:194874$13442_Y + connect \Y $extend$libresoc.v:197164$13624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:194885$13454 + cell $pos $extend$libresoc.v:197175$13636 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:194885$13454_Y + connect \Y $extend$libresoc.v:197175$13636_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:194792$13362 + cell $mul $mul$libresoc.v:197084$13546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405601,10 +409602,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:194792$13362_Y + connect \Y $mul$libresoc.v:197084$13546_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:194911$13479 + cell $mul $mul$libresoc.v:197201$13661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405612,10 +409613,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:194911$13479_Y + connect \Y $mul$libresoc.v:197201$13661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" - cell $ne $ne$libresoc.v:194861$13428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + cell $ne $ne$libresoc.v:197152$13611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405623,10 +409624,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:194861$13428_Y + connect \Y $ne$libresoc.v:197152$13611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - cell $ne $ne$libresoc.v:194870$13437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + cell $ne $ne$libresoc.v:197160$13619 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405634,10 +409635,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:194870$13437_Y + connect \Y $ne$libresoc.v:197160$13619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $ne $ne$libresoc.v:194880$13449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $ne $ne$libresoc.v:197170$13631 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405645,426 +409646,410 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:194880$13449_Y + connect \Y $ne$libresoc.v:197170$13631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194794$13364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197086$13548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194794$13364_Y + connect \Y $not$libresoc.v:197086$13548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194795$13365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197087$13549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194795$13365_Y + connect \Y $not$libresoc.v:197087$13549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194797$13367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197089$13551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194797$13367_Y + connect \Y $not$libresoc.v:197089$13551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194798$13368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197090$13552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194798$13368_Y + connect \Y $not$libresoc.v:197090$13552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194803$13372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197097$13558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194803$13372_Y + connect \Y $not$libresoc.v:197097$13558_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194804$13373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197098$13559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194804$13373_Y + connect \Y $not$libresoc.v:197098$13559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194806$13375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197100$13561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194806$13375_Y + connect \Y $not$libresoc.v:197100$13561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194807$13376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197101$13562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194807$13376_Y + connect \Y $not$libresoc.v:197101$13562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194811$13380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197105$13566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194811$13380_Y + connect \Y $not$libresoc.v:197105$13566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194812$13381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197106$13567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194812$13381_Y + connect \Y $not$libresoc.v:197106$13567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194817$13385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197111$13571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194817$13385_Y + connect \Y $not$libresoc.v:197111$13571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194818$13386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197112$13572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194818$13386_Y + connect \Y $not$libresoc.v:197112$13572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194820$13388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197114$13574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194820$13388_Y + connect \Y $not$libresoc.v:197114$13574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194821$13389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197115$13575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194821$13389_Y + connect \Y $not$libresoc.v:197115$13575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194823$13391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197117$13577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194823$13391_Y + connect \Y $not$libresoc.v:197117$13577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194824$13392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197118$13578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194824$13392_Y + connect \Y $not$libresoc.v:197118$13578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194826$13394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197120$13580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194826$13394_Y + connect \Y $not$libresoc.v:197120$13580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194827$13395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197121$13581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194827$13395_Y + connect \Y $not$libresoc.v:197121$13581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194829$13397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197123$13583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194829$13397_Y + connect \Y $not$libresoc.v:197123$13583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194830$13398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197124$13584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194830$13398_Y + connect \Y $not$libresoc.v:197124$13584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194832$13400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197126$13586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194832$13400_Y + connect \Y $not$libresoc.v:197126$13586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194833$13401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197127$13587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194833$13401_Y + connect \Y $not$libresoc.v:197127$13587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194837$13405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197131$13591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194837$13405_Y + connect \Y $not$libresoc.v:197131$13591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194838$13406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197132$13592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194838$13406_Y + connect \Y $not$libresoc.v:197132$13592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194840$13408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197134$13594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194840$13408_Y + connect \Y $not$libresoc.v:197134$13594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194841$13409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197135$13595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194841$13409_Y + connect \Y $not$libresoc.v:197135$13595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194846$13413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197140$13599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194846$13413_Y + connect \Y $not$libresoc.v:197140$13599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194847$13414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197141$13600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194847$13414_Y + connect \Y $not$libresoc.v:197141$13600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194849$13416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197143$13602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194849$13416_Y + connect \Y $not$libresoc.v:197143$13602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194850$13417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197144$13603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194850$13417_Y + connect \Y $not$libresoc.v:197144$13603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194856$13423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197150$13609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194856$13423_Y + connect \Y $not$libresoc.v:197150$13609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194857$13424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197151$13610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194857$13424_Y + connect \Y $not$libresoc.v:197151$13610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194858$13425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197153$13612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194858$13425_Y + connect \Y $not$libresoc.v:197153$13612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194860$13427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197155$13614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194860$13427_Y + connect \Y $not$libresoc.v:197155$13614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194862$13429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197156$13615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194862$13429_Y + connect \Y $not$libresoc.v:197156$13615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194865$13432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194865$13432_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194866$13433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194866$13433_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194871$13438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197161$13620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194871$13438_Y + connect \Y $not$libresoc.v:197161$13620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194872$13439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197162$13621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194872$13439_Y + connect \Y $not$libresoc.v:197162$13621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:194881$13450 + cell $not $not$libresoc.v:197171$13632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:194881$13450_Y + connect \Y $not$libresoc.v:197171$13632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" - cell $not $not$libresoc.v:194883$13452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + cell $not $not$libresoc.v:197173$13634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:194883$13452_Y + connect \Y $not$libresoc.v:197173$13634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" - cell $not $not$libresoc.v:194884$13453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + cell $not $not$libresoc.v:197174$13635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:194884$13453_Y + connect \Y $not$libresoc.v:197174$13635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194886$13456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197176$13638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194886$13456_Y + connect \Y $not$libresoc.v:197176$13638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194887$13457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197177$13639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194887$13457_Y + connect \Y $not$libresoc.v:197177$13639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194891$13461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197181$13643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194891$13461_Y + connect \Y $not$libresoc.v:197181$13643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194892$13462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197182$13644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194892$13462_Y + connect \Y $not$libresoc.v:197182$13644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194897$13466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197187$13648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194897$13466_Y + connect \Y $not$libresoc.v:197187$13648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194898$13467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197188$13649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194898$13467_Y + connect \Y $not$libresoc.v:197188$13649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194902$13471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197192$13653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194902$13471_Y + connect \Y $not$libresoc.v:197192$13653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194903$13472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197193$13654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194903$13472_Y + connect \Y $not$libresoc.v:197193$13654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $not $not$libresoc.v:194908$13476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + cell $not $not$libresoc.v:197198$13658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:194908$13476_Y + connect \Y $not$libresoc.v:197198$13658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $not $not$libresoc.v:194909$13477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + cell $not $not$libresoc.v:197199$13659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:194909$13477_Y + connect \Y $not$libresoc.v:197199$13659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194800$13370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197092$13554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406072,10 +410057,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194800$13370_Y + connect \Y $or$libresoc.v:197092$13554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194802$13371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197094$13555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406083,10 +410068,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:194802$13371_Y + connect \Y $or$libresoc.v:197094$13555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194814$13383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197108$13569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406094,21 +410079,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194814$13383_Y + connect \Y $or$libresoc.v:197108$13569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194816$13384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197110$13570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$148 + connect \A \$154 connect \B \is_last - connect \Y $or$libresoc.v:194816$13384_Y + connect \Y $or$libresoc.v:197110$13570_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194843$13411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197137$13597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406116,21 +410101,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194843$13411_Y + connect \Y $or$libresoc.v:197137$13597_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194845$13412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197139$13598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$206 + connect \A \$212 connect \B \is_last - connect \Y $or$libresoc.v:194845$13412_Y + connect \Y $or$libresoc.v:197139$13598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $or $or$libresoc.v:194878$13447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $or $or$libresoc.v:197168$13629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406138,10 +410123,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:194878$13447_Y + connect \Y $or$libresoc.v:197168$13629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $or $or$libresoc.v:194879$13448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $or $or$libresoc.v:197169$13630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406149,10 +410134,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:194879$13448_Y + connect \Y $or$libresoc.v:197169$13630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194894$13464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197184$13646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406160,10 +410145,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194894$13464_Y + connect \Y $or$libresoc.v:197184$13646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194896$13465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197186$13647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406171,10 +410156,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:194896$13465_Y + connect \Y $or$libresoc.v:197186$13647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194905$13474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197195$13656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406182,10 +410167,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194905$13474_Y + connect \Y $or$libresoc.v:197195$13656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194907$13475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197197$13657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406193,58 +410178,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:194907$13475_Y + connect \Y $or$libresoc.v:197197$13657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194869$13436 + cell $pos $pos$libresoc.v:197159$13618 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:194869$13436_Y + connect \Y $pos$libresoc.v:197159$13618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194873$13441 + cell $pos $pos$libresoc.v:197163$13623 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194873$13440_Y - connect \Y $pos$libresoc.v:194873$13441_Y + connect \A $extend$libresoc.v:197163$13622_Y + connect \Y $pos$libresoc.v:197163$13623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194874$13443 + cell $pos $pos$libresoc.v:197164$13625 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194874$13442_Y - connect \Y $pos$libresoc.v:194874$13443_Y + connect \A $extend$libresoc.v:197164$13624_Y + connect \Y $pos$libresoc.v:197164$13625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:194885$13455 + cell $pos $pos$libresoc.v:197175$13637 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194885$13454_Y - connect \Y $pos$libresoc.v:194885$13455_Y + connect \A $extend$libresoc.v:197175$13636_Y + connect \Y $pos$libresoc.v:197175$13637_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194836$13404 + cell $reduce_or $reduce_or$libresoc.v:197130$13590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$189 - connect \Y $reduce_or$libresoc.v:194836$13404_Y + connect \A \$195 + connect \Y $reduce_or$libresoc.v:197130$13590_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194853$13420 + cell $reduce_or $reduce_or$libresoc.v:197147$13606 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$223 - connect \Y $reduce_or$libresoc.v:194853$13420_Y + connect \A \$229 + connect \Y $reduce_or$libresoc.v:197147$13606_Y end - attribute \src "libresoc.v:194793.18-194793.41" - cell $shr $shr$libresoc.v:194793$13363 + attribute \src "libresoc.v:197085.18-197085.41" + cell $shr $shr$libresoc.v:197085$13547 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406252,10 +410237,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:194793$13363_Y + connect \Y $shr$libresoc.v:197085$13547_Y end - attribute \src "libresoc.v:194912.18-194912.40" - cell $shr $shr$libresoc.v:194912$13480 + attribute \src "libresoc.v:197202.18-197202.40" + cell $shr $shr$libresoc.v:197202$13662 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406263,10 +410248,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:194912$13480_Y + connect \Y $shr$libresoc.v:197202$13662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" - cell $sub $sub$libresoc.v:194875$13444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + cell $sub $sub$libresoc.v:197165$13626 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406274,10 +410259,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:194875$13444_Y + connect \Y $sub$libresoc.v:197165$13626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" - cell $sub $sub$libresoc.v:194876$13445 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + cell $sub $sub$libresoc.v:197167$13628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -406285,10 +410270,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:194876$13445_Y + connect \Y $sub$libresoc.v:197167$13628_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:195121.8-195219.4" + attribute \src "libresoc.v:197411.8-197509.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -406389,7 +410374,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:195220.7-195251.4" + attribute \src "libresoc.v:197510.7-197541.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -406423,7 +410408,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:195252.8-195319.4" + attribute \src "libresoc.v:197542.8-197609.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -406493,7 +410478,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:195320.8-195336.4" + attribute \src "libresoc.v:197610.8-197626.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -406512,7 +410497,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:195337.8-195669.4" + attribute \src "libresoc.v:197627.8-197955.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -406736,12 +410721,8 @@ module \ti connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe @@ -406847,7 +410828,7 @@ module \ti connect \wb_sram_en \jtag_wb_sram_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:195670.12-195682.4" + attribute \src "libresoc.v:197956.12-197968.4" cell \sram4k_0 \sram4k_0 connect \clk \clk connect \enable \sram4k_0_enable @@ -406862,7 +410843,7 @@ module \ti connect \sram4k_0_wb__we \sram4k_0_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195683.12-195695.4" + attribute \src "libresoc.v:197969.12-197981.4" cell \sram4k_1 \sram4k_1 connect \clk \clk connect \enable \sram4k_1_enable @@ -406877,7 +410858,7 @@ module \ti connect \sram4k_1_wb__we \sram4k_1_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195696.12-195708.4" + attribute \src "libresoc.v:197982.12-197994.4" cell \sram4k_2 \sram4k_2 connect \clk \clk connect \enable \sram4k_2_enable @@ -406892,7 +410873,7 @@ module \ti connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195709.12-195721.4" + attribute \src "libresoc.v:197995.12-198007.4" cell \sram4k_3 \sram4k_3 connect \clk \clk connect \enable \sram4k_3_enable @@ -406907,7 +410888,7 @@ module \ti connect \sram4k_3_wb__we \sram4k_3_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195722.12-195736.4" + attribute \src "libresoc.v:198008.12-198022.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -406924,7 +410905,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:195737.12-195750.4" + attribute \src "libresoc.v:198023.12-198036.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -406939,1582 +410920,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:192354.7-192354.20" - process $proc$libresoc.v:192354$14061 + attribute \src "libresoc.v:194646.7-194646.20" + process $proc$libresoc.v:194646$14246 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192624.13-192624.33" - process $proc$libresoc.v:192624$14062 + attribute \src "libresoc.v:194914.13-194914.33" + process $proc$libresoc.v:194914$14247 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:192630.7-192630.35" - process $proc$libresoc.v:192630$14063 + attribute \src "libresoc.v:194920.7-194920.35" + process $proc$libresoc.v:194920$14248 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14064 1'0 + assign $0\core_bigendian_i$10[0:0]$14249 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14064 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14249 end - attribute \src "libresoc.v:192638.14-192638.55" - process $proc$libresoc.v:192638$14065 + attribute \src "libresoc.v:194928.14-194928.55" + process $proc$libresoc.v:194928$14250 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:192642.13-192642.41" - process $proc$libresoc.v:192642$14066 + attribute \src "libresoc.v:194932.13-194932.41" + process $proc$libresoc.v:194932$14251 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:192646.7-192646.37" - process $proc$libresoc.v:192646$14067 + attribute \src "libresoc.v:194936.7-194936.37" + process $proc$libresoc.v:194936$14252 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:192650.13-192650.41" - process $proc$libresoc.v:192650$14068 + attribute \src "libresoc.v:194940.13-194940.41" + process $proc$libresoc.v:194940$14253 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:192654.7-192654.42" - process $proc$libresoc.v:192654$14069 + attribute \src "libresoc.v:194944.7-194944.42" + process $proc$libresoc.v:194944$14254 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14070 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14255 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14070 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14255 end - attribute \src "libresoc.v:192656.7-192656.44" - process $proc$libresoc.v:192656$14071 + attribute \src "libresoc.v:194946.7-194946.44" + process $proc$libresoc.v:194946$14256 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14072 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14257 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14072 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14257 end - attribute \src "libresoc.v:192660.7-192660.44" - process $proc$libresoc.v:192660$14073 + attribute \src "libresoc.v:194950.7-194950.44" + process $proc$libresoc.v:194950$14258 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14074 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14259 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14074 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14259 end - attribute \src "libresoc.v:192664.7-192664.44" - process $proc$libresoc.v:192664$14075 + attribute \src "libresoc.v:194954.7-194954.44" + process $proc$libresoc.v:194954$14260 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14076 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14261 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14076 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14261 end - attribute \src "libresoc.v:192668.7-192668.44" - process $proc$libresoc.v:192668$14077 + attribute \src "libresoc.v:194958.7-194958.44" + process $proc$libresoc.v:194958$14262 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14078 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14263 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14078 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14263 end - attribute \src "libresoc.v:192672.7-192672.44" - process $proc$libresoc.v:192672$14079 + attribute \src "libresoc.v:194962.7-194962.44" + process $proc$libresoc.v:194962$14264 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14080 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14265 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14080 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14265 end - attribute \src "libresoc.v:192676.7-192676.44" - process $proc$libresoc.v:192676$14081 + attribute \src "libresoc.v:194966.7-194966.44" + process $proc$libresoc.v:194966$14266 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14082 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14267 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14082 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14267 end - attribute \src "libresoc.v:192680.7-192680.44" - process $proc$libresoc.v:192680$14083 + attribute \src "libresoc.v:194970.7-194970.44" + process $proc$libresoc.v:194970$14268 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14084 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14269 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14084 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14269 end - attribute \src "libresoc.v:192701.14-192701.47" - process $proc$libresoc.v:192701$14085 + attribute \src "libresoc.v:194991.14-194991.47" + process $proc$libresoc.v:194991$14270 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:192709.13-192709.46" - process $proc$libresoc.v:192709$14086 + attribute \src "libresoc.v:194999.13-194999.46" + process $proc$libresoc.v:194999$14271 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:192713.14-192713.41" - process $proc$libresoc.v:192713$14087 + attribute \src "libresoc.v:195003.14-195003.41" + process $proc$libresoc.v:195003$14272 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:192792.13-192792.45" - process $proc$libresoc.v:192792$14088 + attribute \src "libresoc.v:195082.13-195082.45" + process $proc$libresoc.v:195082$14273 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:192796.7-192796.37" - process $proc$libresoc.v:192796$14089 + attribute \src "libresoc.v:195086.7-195086.37" + process $proc$libresoc.v:195086$14274 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:192800.14-192800.55" - process $proc$libresoc.v:192800$14090 + attribute \src "libresoc.v:195090.14-195090.55" + process $proc$libresoc.v:195090$14275 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:192804.7-192804.31" - process $proc$libresoc.v:192804$14091 + attribute \src "libresoc.v:195094.7-195094.31" + process $proc$libresoc.v:195094$14276 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:192808.7-192808.34" - process $proc$libresoc.v:192808$14092 + attribute \src "libresoc.v:195098.7-195098.34" + process $proc$libresoc.v:195098$14277 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:192812.7-192812.31" - process $proc$libresoc.v:192812$14093 + attribute \src "libresoc.v:195102.7-195102.31" + process $proc$libresoc.v:195102$14278 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:192816.7-192816.34" - process $proc$libresoc.v:192816$14094 + attribute \src "libresoc.v:195106.7-195106.34" + process $proc$libresoc.v:195106$14279 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:192820.14-192820.48" - process $proc$libresoc.v:192820$14095 + attribute \src "libresoc.v:195110.14-195110.48" + process $proc$libresoc.v:195110$14280 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:192824.13-192824.44" - process $proc$libresoc.v:192824$14096 + attribute \src "libresoc.v:195114.13-195114.44" + process $proc$libresoc.v:195114$14281 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:192828.13-192828.37" - process $proc$libresoc.v:192828$14097 + attribute \src "libresoc.v:195118.13-195118.37" + process $proc$libresoc.v:195118$14282 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:192832.7-192832.33" - process $proc$libresoc.v:192832$14098 + attribute \src "libresoc.v:195122.7-195122.33" + process $proc$libresoc.v:195122$14283 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:192836.13-192836.37" - process $proc$libresoc.v:192836$14099 + attribute \src "libresoc.v:195126.13-195126.37" + process $proc$libresoc.v:195126$14284 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:192838.13-192838.41" - process $proc$libresoc.v:192838$14100 + attribute \src "libresoc.v:195128.13-195128.41" + process $proc$libresoc.v:195128$14285 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14101 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14286 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14101 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14286 end - attribute \src "libresoc.v:192844.7-192844.33" - process $proc$libresoc.v:192844$14102 + attribute \src "libresoc.v:195134.7-195134.33" + process $proc$libresoc.v:195134$14287 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:192846.7-192846.37" - process $proc$libresoc.v:192846$14103 + attribute \src "libresoc.v:195136.7-195136.37" + process $proc$libresoc.v:195136$14288 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14104 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14289 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14104 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14289 end - attribute \src "libresoc.v:192852.13-192852.37" - process $proc$libresoc.v:192852$14105 + attribute \src "libresoc.v:195142.13-195142.37" + process $proc$libresoc.v:195142$14290 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:192856.7-192856.32" - process $proc$libresoc.v:192856$14106 + attribute \src "libresoc.v:195146.7-195146.32" + process $proc$libresoc.v:195146$14291 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:192860.13-192860.38" - process $proc$libresoc.v:192860$14107 + attribute \src "libresoc.v:195150.13-195150.38" + process $proc$libresoc.v:195150$14292 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:192864.13-192864.33" - process $proc$libresoc.v:192864$14108 + attribute \src "libresoc.v:195154.13-195154.33" + process $proc$libresoc.v:195154$14293 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:192868.13-192868.35" - process $proc$libresoc.v:192868$14109 + attribute \src "libresoc.v:195158.13-195158.35" + process $proc$libresoc.v:195158$14294 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:192872.7-192872.32" - process $proc$libresoc.v:192872$14110 + attribute \src "libresoc.v:195162.7-195162.32" + process $proc$libresoc.v:195162$14295 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:192876.13-192876.35" - process $proc$libresoc.v:192876$14111 + attribute \src "libresoc.v:195166.13-195166.35" + process $proc$libresoc.v:195166$14296 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:192880.7-192880.32" - process $proc$libresoc.v:192880$14112 + attribute \src "libresoc.v:195170.7-195170.32" + process $proc$libresoc.v:195170$14297 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:192884.13-192884.36" - process $proc$libresoc.v:192884$14113 + attribute \src "libresoc.v:195174.13-195174.36" + process $proc$libresoc.v:195174$14298 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:192888.13-192888.36" - process $proc$libresoc.v:192888$14114 + attribute \src "libresoc.v:195178.13-195178.36" + process $proc$libresoc.v:195178$14299 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:192892.7-192892.26" - process $proc$libresoc.v:192892$14115 + attribute \src "libresoc.v:195182.7-195182.26" + process $proc$libresoc.v:195182$14300 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:192896.13-192896.36" - process $proc$libresoc.v:192896$14116 + attribute \src "libresoc.v:195186.13-195186.36" + process $proc$libresoc.v:195186$14301 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:192900.14-192900.49" - process $proc$libresoc.v:192900$14117 + attribute \src "libresoc.v:195190.14-195190.49" + process $proc$libresoc.v:195190$14302 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:192904.13-192904.35" - process $proc$libresoc.v:192904$14118 + attribute \src "libresoc.v:195194.13-195194.35" + process $proc$libresoc.v:195194$14303 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:192908.7-192908.31" - process $proc$libresoc.v:192908$14119 + attribute \src "libresoc.v:195198.7-195198.31" + process $proc$libresoc.v:195198$14304 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:192912.13-192912.35" - process $proc$libresoc.v:192912$14120 + attribute \src "libresoc.v:195202.13-195202.35" + process $proc$libresoc.v:195202$14305 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:192916.7-192916.31" - process $proc$libresoc.v:192916$14121 + attribute \src "libresoc.v:195206.7-195206.31" + process $proc$libresoc.v:195206$14306 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:192920.13-192920.35" - process $proc$libresoc.v:192920$14122 + attribute \src "libresoc.v:195210.13-195210.35" + process $proc$libresoc.v:195210$14307 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:192924.7-192924.31" - process $proc$libresoc.v:192924$14123 + attribute \src "libresoc.v:195214.7-195214.31" + process $proc$libresoc.v:195214$14308 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:192928.13-192928.35" - process $proc$libresoc.v:192928$14124 + attribute \src "libresoc.v:195218.13-195218.35" + process $proc$libresoc.v:195218$14309 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:193046.13-193046.37" - process $proc$libresoc.v:193046$14125 + attribute \src "libresoc.v:195336.13-195336.37" + process $proc$libresoc.v:195336$14310 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:193050.7-193050.31" - process $proc$libresoc.v:193050$14126 + attribute \src "libresoc.v:195340.7-195340.31" + process $proc$libresoc.v:195340$14311 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:193168.13-193168.37" - process $proc$libresoc.v:193168$14127 + attribute \src "libresoc.v:195458.13-195458.37" + process $proc$libresoc.v:195458$14312 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:193172.13-193172.38" - process $proc$libresoc.v:193172$14128 + attribute \src "libresoc.v:195462.13-195462.38" + process $proc$libresoc.v:195462$14313 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:193176.13-193176.35" - process $proc$libresoc.v:193176$14129 + attribute \src "libresoc.v:195466.13-195466.35" + process $proc$libresoc.v:195466$14314 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:193180.13-193180.36" - process $proc$libresoc.v:193180$14130 + attribute \src "libresoc.v:195470.13-195470.36" + process $proc$libresoc.v:195470$14315 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:193186.13-193186.33" - process $proc$libresoc.v:193186$14131 + attribute \src "libresoc.v:195476.13-195476.33" + process $proc$libresoc.v:195476$14316 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:193190.13-193190.36" - process $proc$libresoc.v:193190$14132 + attribute \src "libresoc.v:195480.13-195480.36" + process $proc$libresoc.v:195480$14317 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:193198.7-193198.28" - process $proc$libresoc.v:193198$14133 + attribute \src "libresoc.v:195488.7-195488.28" + process $proc$libresoc.v:195488$14318 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:193214.14-193214.45" - process $proc$libresoc.v:193214$14134 + attribute \src "libresoc.v:195504.14-195504.45" + process $proc$libresoc.v:195504$14319 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:193224.7-193224.24" - process $proc$libresoc.v:193224$14135 + attribute \src "libresoc.v:195514.7-195514.24" + process $proc$libresoc.v:195514$14320 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:193228.7-193228.23" - process $proc$libresoc.v:193228$14136 + attribute \src "libresoc.v:195518.7-195518.23" + process $proc$libresoc.v:195518$14321 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:193232.7-193232.28" - process $proc$libresoc.v:193232$14137 + attribute \src "libresoc.v:195522.7-195522.28" + process $proc$libresoc.v:195522$14322 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:193236.7-193236.28" - process $proc$libresoc.v:193236$14138 + attribute \src "libresoc.v:195526.7-195526.28" + process $proc$libresoc.v:195526$14323 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:193264.14-193264.45" - process $proc$libresoc.v:193264$14139 + attribute \src "libresoc.v:195554.14-195554.45" + process $proc$libresoc.v:195554$14324 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:193272.14-193272.37" - process $proc$libresoc.v:193272$14140 + attribute \src "libresoc.v:195562.14-195562.37" + process $proc$libresoc.v:195562$14325 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:193276.7-193276.26" - process $proc$libresoc.v:193276$14141 + attribute \src "libresoc.v:195566.7-195566.26" + process $proc$libresoc.v:195566$14326 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:193280.7-193280.26" - process $proc$libresoc.v:193280$14142 + attribute \src "libresoc.v:195570.7-195570.26" + process $proc$libresoc.v:195570$14327 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:193292.7-193292.26" - process $proc$libresoc.v:193292$14143 + attribute \src "libresoc.v:195582.7-195582.26" + process $proc$libresoc.v:195582$14328 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:193302.7-193302.26" - process $proc$libresoc.v:193302$14144 + attribute \src "libresoc.v:195592.7-195592.26" + process $proc$libresoc.v:195592$14329 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:193308.7-193308.30" - process $proc$libresoc.v:193308$14145 + attribute \src "libresoc.v:195598.7-195598.30" + process $proc$libresoc.v:195598$14330 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:193314.13-193314.36" - process $proc$libresoc.v:193314$14146 + attribute \src "libresoc.v:195604.13-195604.36" + process $proc$libresoc.v:195604$14331 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:193318.13-193318.34" - process $proc$libresoc.v:193318$14147 + attribute \src "libresoc.v:195608.13-195608.34" + process $proc$libresoc.v:195608$14332 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:193322.13-193322.36" - process $proc$libresoc.v:193322$14148 + attribute \src "libresoc.v:195612.13-195612.36" + process $proc$libresoc.v:195612$14333 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:193326.13-193326.33" - process $proc$libresoc.v:193326$14149 + attribute \src "libresoc.v:195616.13-195616.33" + process $proc$libresoc.v:195616$14334 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:193330.13-193330.34" - process $proc$libresoc.v:193330$14150 + attribute \src "libresoc.v:195620.13-195620.34" + process $proc$libresoc.v:195620$14335 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:193334.13-193334.31" - process $proc$libresoc.v:193334$14151 + attribute \src "libresoc.v:195624.13-195624.31" + process $proc$libresoc.v:195624$14336 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:193338.7-193338.24" - process $proc$libresoc.v:193338$14152 + attribute \src "libresoc.v:195628.7-195628.24" + process $proc$libresoc.v:195628$14337 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:193342.7-193342.25" - process $proc$libresoc.v:193342$14153 + attribute \src "libresoc.v:195632.7-195632.25" + process $proc$libresoc.v:195632$14338 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:193346.7-193346.25" - process $proc$libresoc.v:193346$14154 + attribute \src "libresoc.v:195636.7-195636.25" + process $proc$libresoc.v:195636$14339 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:193394.13-193394.34" - process $proc$libresoc.v:193394$14155 + attribute \src "libresoc.v:195684.13-195684.34" + process $proc$libresoc.v:195684$14340 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:193398.14-193398.48" - process $proc$libresoc.v:193398$14156 + attribute \src "libresoc.v:195688.14-195688.48" + process $proc$libresoc.v:195688$14341 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:193404.7-193404.27" - process $proc$libresoc.v:193404$14157 + attribute \src "libresoc.v:195694.7-195694.27" + process $proc$libresoc.v:195694$14342 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:193408.7-193408.26" - process $proc$libresoc.v:193408$14158 + attribute \src "libresoc.v:195698.7-195698.26" + process $proc$libresoc.v:195698$14343 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:193462.14-193462.49" - process $proc$libresoc.v:193462$14159 + attribute \src "libresoc.v:195752.14-195752.49" + process $proc$libresoc.v:195752$14344 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:193466.7-193466.27" - process $proc$libresoc.v:193466$14160 + attribute \src "libresoc.v:195756.7-195756.27" + process $proc$libresoc.v:195756$14345 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:193470.14-193470.49" - process $proc$libresoc.v:193470$14161 + attribute \src "libresoc.v:195760.14-195760.49" + process $proc$libresoc.v:195760$14346 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:193474.14-193474.48" - process $proc$libresoc.v:193474$14162 + attribute \src "libresoc.v:195764.14-195764.48" + process $proc$libresoc.v:195764$14347 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:193626.14-193626.40" - process $proc$libresoc.v:193626$14163 + attribute \src "libresoc.v:195916.14-195916.40" + process $proc$libresoc.v:195916$14348 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:193896.13-193896.25" - process $proc$libresoc.v:193896$14164 + attribute \src "libresoc.v:196186.13-196186.25" + process $proc$libresoc.v:196186$14349 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:193912.7-193912.28" - process $proc$libresoc.v:193912$14165 + attribute \src "libresoc.v:196202.7-196202.28" + process $proc$libresoc.v:196202$14350 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:193924.13-193924.35" - process $proc$libresoc.v:193924$14166 + attribute \src "libresoc.v:196214.13-196214.35" + process $proc$libresoc.v:196214$14351 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:193936.13-193936.29" - process $proc$libresoc.v:193936$14167 + attribute \src "libresoc.v:196226.13-196226.29" + process $proc$libresoc.v:196226$14352 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:194196.13-194196.35" - process $proc$libresoc.v:194196$14168 + attribute \src "libresoc.v:196486.13-196486.35" + process $proc$libresoc.v:196486$14353 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:194200.7-194200.30" - process $proc$libresoc.v:194200$14169 + attribute \src "libresoc.v:196490.7-196490.30" + process $proc$libresoc.v:196490$14354 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:194208.14-194208.52" - process $proc$libresoc.v:194208$14170 + attribute \src "libresoc.v:196498.14-196498.52" + process $proc$libresoc.v:196498$14355 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:194266.7-194266.22" - process $proc$libresoc.v:194266$14171 + attribute \src "libresoc.v:196556.7-196556.22" + process $proc$libresoc.v:196556$14356 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:194304.14-194304.40" - process $proc$libresoc.v:194304$14172 + attribute \src "libresoc.v:196596.14-196596.40" + process $proc$libresoc.v:196596$14357 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:194310.7-194310.24" - process $proc$libresoc.v:194310$14173 + attribute \src "libresoc.v:196602.7-196602.24" + process $proc$libresoc.v:196602$14358 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:194320.7-194320.25" - process $proc$libresoc.v:194320$14174 + attribute \src "libresoc.v:196612.7-196612.25" + process $proc$libresoc.v:196612$14359 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:194764.7-194764.24" - process $proc$libresoc.v:194764$14175 + attribute \src "libresoc.v:197056.7-197056.24" + process $proc$libresoc.v:197056$14360 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:194774.7-194774.30" - process $proc$libresoc.v:194774$14176 + attribute \src "libresoc.v:197066.7-197066.30" + process $proc$libresoc.v:197066$14361 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:194913.3-194914.41" - process $proc$libresoc.v:194913$13481 + attribute \src "libresoc.v:197203.3-197204.41" + process $proc$libresoc.v:197203$13663 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:194915.3-194916.41" - process $proc$libresoc.v:194915$13482 + attribute \src "libresoc.v:197205.3-197206.41" + process $proc$libresoc.v:197205$13664 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:194917.3-194918.49" - process $proc$libresoc.v:194917$13483 + attribute \src "libresoc.v:197207.3-197208.49" + process $proc$libresoc.v:197207$13665 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:194919.3-194920.39" - process $proc$libresoc.v:194919$13484 + attribute \src "libresoc.v:197209.3-197210.39" + process $proc$libresoc.v:197209$13666 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:194921.3-194922.41" - process $proc$libresoc.v:194921$13485 + attribute \src "libresoc.v:197211.3-197212.41" + process $proc$libresoc.v:197211$13667 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:194923.3-194924.43" - process $proc$libresoc.v:194923$13486 + attribute \src "libresoc.v:197213.3-197214.43" + process $proc$libresoc.v:197213$13668 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:194925.3-194926.45" - process $proc$libresoc.v:194925$13487 + attribute \src "libresoc.v:197215.3-197216.45" + process $proc$libresoc.v:197215$13669 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:194927.3-194928.33" - process $proc$libresoc.v:194927$13488 + attribute \src "libresoc.v:197217.3-197218.33" + process $proc$libresoc.v:197217$13670 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:194929.3-194930.35" - process $proc$libresoc.v:194929$13489 + attribute \src "libresoc.v:197219.3-197220.35" + process $proc$libresoc.v:197219$13671 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:194931.3-194932.33" - process $proc$libresoc.v:194931$13490 + attribute \src "libresoc.v:197221.3-197222.33" + process $proc$libresoc.v:197221$13672 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:194933.3-194934.49" - process $proc$libresoc.v:194933$13491 + attribute \src "libresoc.v:197223.3-197224.49" + process $proc$libresoc.v:197223$13673 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:194935.3-194936.47" - process $proc$libresoc.v:194935$13492 + attribute \src "libresoc.v:197225.3-197226.47" + process $proc$libresoc.v:197225$13674 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:194937.3-194938.51" - process $proc$libresoc.v:194937$13493 + attribute \src "libresoc.v:197227.3-197228.51" + process $proc$libresoc.v:197227$13675 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:194939.3-194940.51" - process $proc$libresoc.v:194939$13494 + attribute \src "libresoc.v:197229.3-197230.51" + process $proc$libresoc.v:197229$13676 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:194941.3-194942.41" - process $proc$libresoc.v:194941$13495 + attribute \src "libresoc.v:197231.3-197232.41" + process $proc$libresoc.v:197231$13677 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:194943.3-194944.47" - process $proc$libresoc.v:194943$13496 + attribute \src "libresoc.v:197233.3-197234.47" + process $proc$libresoc.v:197233$13678 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:194945.3-194946.35" - process $proc$libresoc.v:194945$13497 + attribute \src "libresoc.v:197235.3-197236.35" + process $proc$libresoc.v:197235$13679 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:194947.3-194948.41" - process $proc$libresoc.v:194947$13498 + attribute \src "libresoc.v:197237.3-197238.41" + process $proc$libresoc.v:197237$13680 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:194949.3-194950.45" - process $proc$libresoc.v:194949$13499 + attribute \src "libresoc.v:197239.3-197240.45" + process $proc$libresoc.v:197239$13681 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:194951.3-194952.41" - process $proc$libresoc.v:194951$13500 + attribute \src "libresoc.v:197241.3-197242.41" + process $proc$libresoc.v:197241$13682 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:194953.3-194954.41" - process $proc$libresoc.v:194953$13501 + attribute \src "libresoc.v:197243.3-197244.41" + process $proc$libresoc.v:197243$13683 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:194955.3-194956.37" - process $proc$libresoc.v:194955$13502 + attribute \src "libresoc.v:197245.3-197246.37" + process $proc$libresoc.v:197245$13684 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:194957.3-194958.45" - process $proc$libresoc.v:194957$13503 + attribute \src "libresoc.v:197247.3-197248.45" + process $proc$libresoc.v:197247$13685 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:194959.3-194960.51" - process $proc$libresoc.v:194959$13504 + attribute \src "libresoc.v:197249.3-197250.51" + process $proc$libresoc.v:197249$13686 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:194961.3-194962.45" - process $proc$libresoc.v:194961$13505 + attribute \src "libresoc.v:197251.3-197252.45" + process $proc$libresoc.v:197251$13687 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:194963.3-194964.51" - process $proc$libresoc.v:194963$13506 + attribute \src "libresoc.v:197253.3-197254.51" + process $proc$libresoc.v:197253$13688 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:194965.3-194966.45" - process $proc$libresoc.v:194965$13507 + attribute \src "libresoc.v:197255.3-197256.45" + process $proc$libresoc.v:197255$13689 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:194967.3-194968.39" - process $proc$libresoc.v:194967$13508 + attribute \src "libresoc.v:197257.3-197258.39" + process $proc$libresoc.v:197257$13690 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:194969.3-194970.51" - process $proc$libresoc.v:194969$13509 + attribute \src "libresoc.v:197259.3-197260.51" + process $proc$libresoc.v:197259$13691 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:194971.3-194972.45" - process $proc$libresoc.v:194971$13510 + attribute \src "libresoc.v:197261.3-197262.45" + process $proc$libresoc.v:197261$13692 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:194973.3-194974.41" - process $proc$libresoc.v:194973$13511 + attribute \src "libresoc.v:197263.3-197264.41" + process $proc$libresoc.v:197263$13693 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:194975.3-194976.45" - process $proc$libresoc.v:194975$13512 + attribute \src "libresoc.v:197265.3-197266.45" + process $proc$libresoc.v:197265$13694 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:194977.3-194978.51" - process $proc$libresoc.v:194977$13513 + attribute \src "libresoc.v:197267.3-197268.51" + process $proc$libresoc.v:197267$13695 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:194979.3-194980.49" - process $proc$libresoc.v:194979$13514 + attribute \src "libresoc.v:197269.3-197270.49" + process $proc$libresoc.v:197269$13696 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:194981.3-194982.41" - process $proc$libresoc.v:194981$13515 + attribute \src "libresoc.v:197271.3-197272.41" + process $proc$libresoc.v:197271$13697 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:194983.3-194984.47" - process $proc$libresoc.v:194983$13516 + attribute \src "libresoc.v:197273.3-197274.47" + process $proc$libresoc.v:197273$13698 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:194985.3-194986.53" - process $proc$libresoc.v:194985$13517 + attribute \src "libresoc.v:197275.3-197276.53" + process $proc$libresoc.v:197275$13699 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:194987.3-194988.47" - process $proc$libresoc.v:194987$13518 + attribute \src "libresoc.v:197277.3-197278.47" + process $proc$libresoc.v:197277$13700 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:194989.3-194990.37" - process $proc$libresoc.v:194989$13519 + attribute \src "libresoc.v:197279.3-197280.37" + process $proc$libresoc.v:197279$13701 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:194991.3-194992.53" - process $proc$libresoc.v:194991$13520 + attribute \src "libresoc.v:197281.3-197282.53" + process $proc$libresoc.v:197281$13702 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:194993.3-194994.49" - process $proc$libresoc.v:194993$13521 + attribute \src "libresoc.v:197283.3-197284.49" + process $proc$libresoc.v:197283$13703 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:194995.3-194996.45" - process $proc$libresoc.v:194995$13522 + attribute \src "libresoc.v:197285.3-197286.45" + process $proc$libresoc.v:197285$13704 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:194997.3-194998.49" - process $proc$libresoc.v:194997$13523 + attribute \src "libresoc.v:197287.3-197288.49" + process $proc$libresoc.v:197287$13705 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:194999.3-195000.45" - process $proc$libresoc.v:194999$13524 + attribute \src "libresoc.v:197289.3-197290.45" + process $proc$libresoc.v:197289$13706 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:195001.3-195002.49" - process $proc$libresoc.v:195001$13525 + attribute \src "libresoc.v:197291.3-197292.49" + process $proc$libresoc.v:197291$13707 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:195003.3-195004.55" - process $proc$libresoc.v:195003$13526 + attribute \src "libresoc.v:197293.3-197294.55" + process $proc$libresoc.v:197293$13708 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:195005.3-195006.49" - process $proc$libresoc.v:195005$13527 + attribute \src "libresoc.v:197295.3-197296.49" + process $proc$libresoc.v:197295$13709 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:195007.3-195008.55" - process $proc$libresoc.v:195007$13528 + attribute \src "libresoc.v:197297.3-197298.55" + process $proc$libresoc.v:197297$13710 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:195009.3-195010.55" - process $proc$libresoc.v:195009$13529 + attribute \src "libresoc.v:197299.3-197300.55" + process $proc$libresoc.v:197299$13711 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13530 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13712 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13530 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13712 end - attribute \src "libresoc.v:195011.3-195012.39" - process $proc$libresoc.v:195011$13531 + attribute \src "libresoc.v:197301.3-197302.39" + process $proc$libresoc.v:197301$13713 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:195013.3-195014.61" - process $proc$libresoc.v:195013$13532 + attribute \src "libresoc.v:197303.3-197304.61" + process $proc$libresoc.v:197303$13714 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13533 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13715 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13533 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13715 end - attribute \src "libresoc.v:195015.3-195016.49" - process $proc$libresoc.v:195015$13534 + attribute \src "libresoc.v:197305.3-197306.49" + process $proc$libresoc.v:197305$13716 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:195017.3-195018.45" - process $proc$libresoc.v:195017$13535 + attribute \src "libresoc.v:197307.3-197308.45" + process $proc$libresoc.v:197307$13717 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:195019.3-195020.53" - process $proc$libresoc.v:195019$13536 + attribute \src "libresoc.v:197309.3-197310.53" + process $proc$libresoc.v:197309$13718 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:195021.3-195022.53" - process $proc$libresoc.v:195021$13537 + attribute \src "libresoc.v:197311.3-197312.53" + process $proc$libresoc.v:197311$13719 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:195023.3-195024.55" - process $proc$libresoc.v:195023$13538 + attribute \src "libresoc.v:197313.3-197314.55" + process $proc$libresoc.v:197313$13720 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:195025.3-195026.65" - process $proc$libresoc.v:195025$13539 + attribute \src "libresoc.v:197315.3-197316.65" + process $proc$libresoc.v:197315$13721 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:195027.3-195028.61" - process $proc$libresoc.v:195027$13540 + attribute \src "libresoc.v:197317.3-197318.61" + process $proc$libresoc.v:197317$13722 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:195029.3-195030.41" - process $proc$libresoc.v:195029$13541 + attribute \src "libresoc.v:197319.3-197320.41" + process $proc$libresoc.v:197319$13723 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:195031.3-195032.51" - process $proc$libresoc.v:195031$13542 + attribute \src "libresoc.v:197321.3-197322.51" + process $proc$libresoc.v:197321$13724 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:195033.3-195034.45" - process $proc$libresoc.v:195033$13543 + attribute \src "libresoc.v:197323.3-197324.45" + process $proc$libresoc.v:197323$13725 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:195035.3-195036.57" - process $proc$libresoc.v:195035$13544 + attribute \src "libresoc.v:197325.3-197326.57" + process $proc$libresoc.v:197325$13726 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:195037.3-195038.51" - process $proc$libresoc.v:195037$13545 + attribute \src "libresoc.v:197327.3-197328.51" + process $proc$libresoc.v:197327$13727 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:195039.3-195040.57" - process $proc$libresoc.v:195039$13546 + attribute \src "libresoc.v:197329.3-197330.57" + process $proc$libresoc.v:197329$13728 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:195041.3-195042.69" - process $proc$libresoc.v:195041$13547 + attribute \src "libresoc.v:197331.3-197332.69" + process $proc$libresoc.v:197331$13729 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:195043.3-195044.63" - process $proc$libresoc.v:195043$13548 + attribute \src "libresoc.v:197333.3-197334.63" + process $proc$libresoc.v:197333$13730 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:195045.3-195046.71" - process $proc$libresoc.v:195045$13549 + attribute \src "libresoc.v:197335.3-197336.71" + process $proc$libresoc.v:197335$13731 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13550 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13732 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13550 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13732 end - attribute \src "libresoc.v:195047.3-195048.75" - process $proc$libresoc.v:195047$13551 + attribute \src "libresoc.v:197337.3-197338.75" + process $proc$libresoc.v:197337$13733 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13552 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13734 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13552 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13734 end - attribute \src "libresoc.v:195049.3-195050.75" - process $proc$libresoc.v:195049$13553 + attribute \src "libresoc.v:197339.3-197340.75" + process $proc$libresoc.v:197339$13735 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13554 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13736 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13554 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13736 end - attribute \src "libresoc.v:195051.3-195052.75" - process $proc$libresoc.v:195051$13555 + attribute \src "libresoc.v:197341.3-197342.75" + process $proc$libresoc.v:197341$13737 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13556 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13738 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13556 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13738 end - attribute \src "libresoc.v:195053.3-195054.75" - process $proc$libresoc.v:195053$13557 + attribute \src "libresoc.v:197343.3-197344.75" + process $proc$libresoc.v:197343$13739 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13558 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13740 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13558 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13740 end - attribute \src "libresoc.v:195055.3-195056.41" - process $proc$libresoc.v:195055$13559 + attribute \src "libresoc.v:197345.3-197346.41" + process $proc$libresoc.v:197345$13741 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:195057.3-195058.75" - process $proc$libresoc.v:195057$13560 + attribute \src "libresoc.v:197347.3-197348.75" + process $proc$libresoc.v:197347$13742 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13561 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13743 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13561 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13743 end - attribute \src "libresoc.v:195059.3-195060.75" - process $proc$libresoc.v:195059$13562 + attribute \src "libresoc.v:197349.3-197350.75" + process $proc$libresoc.v:197349$13744 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13563 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13745 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13563 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13745 end - attribute \src "libresoc.v:195061.3-195062.75" - process $proc$libresoc.v:195061$13564 + attribute \src "libresoc.v:197351.3-197352.75" + process $proc$libresoc.v:197351$13746 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13565 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13747 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13565 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13747 end - attribute \src "libresoc.v:195063.3-195064.63" - process $proc$libresoc.v:195063$13566 + attribute \src "libresoc.v:197353.3-197354.63" + process $proc$libresoc.v:197353$13748 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:195065.3-195066.57" - process $proc$libresoc.v:195065$13567 + attribute \src "libresoc.v:197355.3-197356.57" + process $proc$libresoc.v:197355$13749 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:195067.3-195068.63" - process $proc$libresoc.v:195067$13568 + attribute \src "libresoc.v:197357.3-197358.63" + process $proc$libresoc.v:197357$13750 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:195069.3-195070.57" - process $proc$libresoc.v:195069$13569 + attribute \src "libresoc.v:197359.3-197360.57" + process $proc$libresoc.v:197359$13751 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:195071.3-195072.53" - process $proc$libresoc.v:195071$13570 + attribute \src "libresoc.v:197361.3-197362.53" + process $proc$libresoc.v:197361$13752 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:195073.3-195074.63" - process $proc$libresoc.v:195073$13571 + attribute \src "libresoc.v:197363.3-197364.63" + process $proc$libresoc.v:197363$13753 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:195075.3-195076.37" - process $proc$libresoc.v:195075$13572 + attribute \src "libresoc.v:197365.3-197366.37" + process $proc$libresoc.v:197365$13754 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:195077.3-195078.57" - process $proc$libresoc.v:195077$13573 + attribute \src "libresoc.v:197367.3-197368.57" + process $proc$libresoc.v:197367$13755 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13574 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13756 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13574 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13756 end - attribute \src "libresoc.v:195079.3-195080.37" - process $proc$libresoc.v:195079$13575 + attribute \src "libresoc.v:197369.3-197370.37" + process $proc$libresoc.v:197369$13757 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:195081.3-195082.47" - process $proc$libresoc.v:195081$13576 + attribute \src "libresoc.v:197371.3-197372.47" + process $proc$libresoc.v:197371$13758 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:195083.3-195084.53" - process $proc$libresoc.v:195083$13577 + attribute \src "libresoc.v:197373.3-197374.53" + process $proc$libresoc.v:197373$13759 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:195085.3-195086.23" - process $proc$libresoc.v:195085$13578 + attribute \src "libresoc.v:197375.3-197376.23" + process $proc$libresoc.v:197375$13760 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:195087.3-195088.41" - process $proc$libresoc.v:195087$13579 + attribute \src "libresoc.v:197377.3-197378.41" + process $proc$libresoc.v:197377$13761 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:195089.3-195090.47" - process $proc$libresoc.v:195089$13580 + attribute \src "libresoc.v:197379.3-197380.47" + process $proc$libresoc.v:197379$13762 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:195091.3-195092.33" - process $proc$libresoc.v:195091$13581 + attribute \src "libresoc.v:197381.3-197382.33" + process $proc$libresoc.v:197381$13763 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:195093.3-195094.45" - process $proc$libresoc.v:195093$13582 + attribute \src "libresoc.v:197383.3-197384.45" + process $proc$libresoc.v:197383$13764 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:195095.3-195096.43" - process $proc$libresoc.v:195095$13583 + attribute \src "libresoc.v:197385.3-197386.43" + process $proc$libresoc.v:197385$13765 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:195097.3-195098.47" - process $proc$libresoc.v:195097$13584 + attribute \src "libresoc.v:197387.3-197388.47" + process $proc$libresoc.v:197387$13766 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:195099.3-195100.47" - process $proc$libresoc.v:195099$13585 + attribute \src "libresoc.v:197389.3-197390.47" + process $proc$libresoc.v:197389$13767 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:195101.3-195102.47" - process $proc$libresoc.v:195101$13586 + attribute \src "libresoc.v:197391.3-197392.47" + process $proc$libresoc.v:197391$13768 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:195103.3-195104.37" - process $proc$libresoc.v:195103$13587 + attribute \src "libresoc.v:197393.3-197394.37" + process $proc$libresoc.v:197393$13769 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:195105.3-195106.43" - process $proc$libresoc.v:195105$13588 + attribute \src "libresoc.v:197395.3-197396.43" + process $proc$libresoc.v:197395$13770 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:195107.3-195108.39" - process $proc$libresoc.v:195107$13589 + attribute \src "libresoc.v:197397.3-197398.39" + process $proc$libresoc.v:197397$13771 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:195109.3-195110.49" - process $proc$libresoc.v:195109$13590 + attribute \src "libresoc.v:197399.3-197400.49" + process $proc$libresoc.v:197399$13772 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:195111.3-195112.39" - process $proc$libresoc.v:195111$13591 + attribute \src "libresoc.v:197401.3-197402.39" + process $proc$libresoc.v:197401$13773 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:195113.3-195114.43" - process $proc$libresoc.v:195113$13592 + attribute \src "libresoc.v:197403.3-197404.43" + process $proc$libresoc.v:197403$13774 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:195115.3-195116.27" - process $proc$libresoc.v:195115$13593 + attribute \src "libresoc.v:197405.3-197406.27" + process $proc$libresoc.v:197405$13775 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:195117.3-195118.43" - process $proc$libresoc.v:195117$13594 + attribute \src "libresoc.v:197407.3-197408.43" + process $proc$libresoc.v:197407$13776 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:195119.3-195120.47" - process $proc$libresoc.v:195119$13595 + attribute \src "libresoc.v:197409.3-197410.47" + process $proc$libresoc.v:197409$13777 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:195751.3-195759.6" - process $proc$libresoc.v:195751$13596 + attribute \src "libresoc.v:198037.3-198045.6" + process $proc$libresoc.v:198037$13778 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13597 $1\dbg_dmi_addr_i$next[3:0]$13598 - attribute \src "libresoc.v:195752.5-195752.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13779 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:198038.5-198038.29" switch \initial - attribute \src "libresoc.v:195752.9-195752.17" + attribute \src "libresoc.v:198038.9-198038.17" case 1'1 case end @@ -408523,21 +412504,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13598 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13780 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13598 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13780 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13597 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13779 end - attribute \src "libresoc.v:195760.3-195768.6" - process $proc$libresoc.v:195760$13599 + attribute \src "libresoc.v:198046.3-198054.6" + process $proc$libresoc.v:198046$13781 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13600 $1\dbg_dmi_req_i$next[0:0]$13601 - attribute \src "libresoc.v:195761.5-195761.29" + assign $0\dbg_dmi_req_i$next[0:0]$13782 $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:198047.5-198047.29" switch \initial - attribute \src "libresoc.v:195761.9-195761.17" + attribute \src "libresoc.v:198047.9-198047.17" case 1'1 case end @@ -408546,21 +412527,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13601 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13783 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13601 \jtag_dmi0__req_i + assign $1\dbg_dmi_req_i$next[0:0]$13783 \jtag_dmi0__req_i end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13600 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13782 end - attribute \src "libresoc.v:195769.3-195777.6" - process $proc$libresoc.v:195769$13602 + attribute \src "libresoc.v:198055.3-198063.6" + process $proc$libresoc.v:198055$13784 assign { } { } assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13603 $1\dec2_cur_eint$next[0:0]$13604 - attribute \src "libresoc.v:195770.5-195770.29" + assign $0\dec2_cur_eint$next[0:0]$13785 $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:198056.5-198056.29" switch \initial - attribute \src "libresoc.v:195770.9-195770.17" + attribute \src "libresoc.v:198056.9-198056.17" case 1'1 case end @@ -408569,38 +412550,38 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13604 1'0 + assign $1\dec2_cur_eint$next[0:0]$13786 1'0 case - assign $1\dec2_cur_eint$next[0:0]$13604 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$13786 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13603 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13785 end - attribute \src "libresoc.v:195778.3-195787.6" - process $proc$libresoc.v:195778$13605 + attribute \src "libresoc.v:198064.3-198073.6" + process $proc$libresoc.v:198064$13787 assign { } { } assign { } { } - assign $0\delay$next[1:0]$13606 $1\delay$next[1:0]$13607 - attribute \src "libresoc.v:195779.5-195779.29" + assign $0\delay$next[1:0]$13788 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:198065.5-198065.29" switch \initial - attribute \src "libresoc.v:195779.9-195779.17" + attribute \src "libresoc.v:198065.9-198065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\delay$next[1:0]$13607 \$25 [1:0] + assign $1\delay$next[1:0]$13789 \$25 [1:0] case - assign $1\delay$next[1:0]$13607 \delay + assign $1\delay$next[1:0]$13789 \delay end sync always - update \delay$next $0\delay$next[1:0]$13606 + update \delay$next $0\delay$next[1:0]$13788 end - attribute \src "libresoc.v:195788.3-195832.6" - process $proc$libresoc.v:195788$13608 + attribute \src "libresoc.v:198074.3-198118.6" + process $proc$libresoc.v:198074$13790 assign { } { } assign { } { } assign { } { } @@ -408631,23 +412612,23 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13609 $3\core_core_dststep$next[6:0]$13639 - assign $0\core_core_maxvl$next[6:0]$13610 $3\core_core_maxvl$next[6:0]$13640 - assign $0\core_core_pc$next[63:0]$13611 $3\core_core_pc$next[63:0]$13641 - assign $0\core_core_srcstep$next[6:0]$13612 $3\core_core_srcstep$next[6:0]$13642 - assign $0\core_core_subvl$next[1:0]$13613 $3\core_core_subvl$next[1:0]$13643 - assign $0\core_core_svstep$next[1:0]$13614 $3\core_core_svstep$next[1:0]$13644 - assign $0\core_core_vl$next[6:0]$13615 $3\core_core_vl$next[6:0]$13645 - assign $0\core_dec$next[63:0]$13616 $3\core_dec$next[63:0]$13646 - assign $0\core_eint$next[0:0]$13617 $3\core_eint$next[0:0]$13647 - assign $0\core_msr$next[63:0]$13618 $3\core_msr$next[63:0]$13648 - attribute \src "libresoc.v:195789.5-195789.29" + assign $0\core_core_dststep$next[6:0]$13791 $3\core_core_dststep$next[6:0]$13821 + assign $0\core_core_maxvl$next[6:0]$13792 $3\core_core_maxvl$next[6:0]$13822 + assign $0\core_core_pc$next[63:0]$13793 $3\core_core_pc$next[63:0]$13823 + assign $0\core_core_srcstep$next[6:0]$13794 $3\core_core_srcstep$next[6:0]$13824 + assign $0\core_core_subvl$next[1:0]$13795 $3\core_core_subvl$next[1:0]$13825 + assign $0\core_core_svstep$next[1:0]$13796 $3\core_core_svstep$next[1:0]$13826 + assign $0\core_core_vl$next[6:0]$13797 $3\core_core_vl$next[6:0]$13827 + assign $0\core_dec$next[63:0]$13798 $3\core_dec$next[63:0]$13828 + assign $0\core_eint$next[0:0]$13799 $3\core_eint$next[0:0]$13829 + assign $0\core_msr$next[63:0]$13800 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198075.5-198075.29" switch \initial - attribute \src "libresoc.v:195789.9-195789.17" + attribute \src "libresoc.v:198075.9-198075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -408661,17 +412642,17 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13619 $2\core_core_dststep$next[6:0]$13629 - assign $1\core_core_maxvl$next[6:0]$13620 $2\core_core_maxvl$next[6:0]$13630 - assign $1\core_core_pc$next[63:0]$13621 $2\core_core_pc$next[63:0]$13631 - assign $1\core_core_srcstep$next[6:0]$13622 $2\core_core_srcstep$next[6:0]$13632 - assign $1\core_core_subvl$next[1:0]$13623 $2\core_core_subvl$next[1:0]$13633 - assign $1\core_core_svstep$next[1:0]$13624 $2\core_core_svstep$next[1:0]$13634 - assign $1\core_core_vl$next[6:0]$13625 $2\core_core_vl$next[6:0]$13635 - assign $1\core_dec$next[63:0]$13626 $2\core_dec$next[63:0]$13636 - assign $1\core_eint$next[0:0]$13627 $2\core_eint$next[0:0]$13637 - assign $1\core_msr$next[63:0]$13628 $2\core_msr$next[63:0]$13638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_core_dststep$next[6:0]$13801 $2\core_core_dststep$next[6:0]$13811 + assign $1\core_core_maxvl$next[6:0]$13802 $2\core_core_maxvl$next[6:0]$13812 + assign $1\core_core_pc$next[63:0]$13803 $2\core_core_pc$next[63:0]$13813 + assign $1\core_core_srcstep$next[6:0]$13804 $2\core_core_srcstep$next[6:0]$13814 + assign $1\core_core_subvl$next[1:0]$13805 $2\core_core_subvl$next[1:0]$13815 + assign $1\core_core_svstep$next[1:0]$13806 $2\core_core_svstep$next[1:0]$13816 + assign $1\core_core_vl$next[6:0]$13807 $2\core_core_vl$next[6:0]$13817 + assign $1\core_dec$next[63:0]$13808 $2\core_dec$next[63:0]$13818 + assign $1\core_eint$next[0:0]$13809 $2\core_eint$next[0:0]$13819 + assign $1\core_msr$next[63:0]$13810 $2\core_msr$next[63:0]$13820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408685,21 +412666,21 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13630 $2\core_core_vl$next[6:0]$13635 $2\core_core_srcstep$next[6:0]$13632 $2\core_core_dststep$next[6:0]$13629 $2\core_core_subvl$next[1:0]$13633 $2\core_core_svstep$next[1:0]$13634 $2\core_dec$next[63:0]$13636 $2\core_eint$next[0:0]$13637 $2\core_msr$next[63:0]$13638 $2\core_core_pc$next[63:0]$13631 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13812 $2\core_core_vl$next[6:0]$13817 $2\core_core_srcstep$next[6:0]$13814 $2\core_core_dststep$next[6:0]$13811 $2\core_core_subvl$next[1:0]$13815 $2\core_core_svstep$next[1:0]$13816 $2\core_dec$next[63:0]$13818 $2\core_eint$next[0:0]$13819 $2\core_msr$next[63:0]$13820 $2\core_core_pc$next[63:0]$13813 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13629 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13630 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13631 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13632 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13633 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13634 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13635 \core_core_vl - assign $2\core_dec$next[63:0]$13636 \core_dec - assign $2\core_eint$next[0:0]$13637 \core_eint - assign $2\core_msr$next[63:0]$13638 \core_msr + assign $2\core_core_dststep$next[6:0]$13811 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13812 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13813 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13814 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13815 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13816 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13817 \core_core_vl + assign $2\core_dec$next[63:0]$13818 \core_dec + assign $2\core_eint$next[0:0]$13819 \core_eint + assign $2\core_msr$next[63:0]$13820 \core_msr end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } assign { } { } assign { } { } @@ -408710,18 +412691,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13620 $1\core_core_vl$next[6:0]$13625 $1\core_core_srcstep$next[6:0]$13622 $1\core_core_dststep$next[6:0]$13619 $1\core_core_subvl$next[1:0]$13623 $1\core_core_svstep$next[1:0]$13624 $1\core_dec$next[63:0]$13626 $1\core_eint$next[0:0]$13627 $1\core_msr$next[63:0]$13628 $1\core_core_pc$next[63:0]$13621 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13802 $1\core_core_vl$next[6:0]$13807 $1\core_core_srcstep$next[6:0]$13804 $1\core_core_dststep$next[6:0]$13801 $1\core_core_subvl$next[1:0]$13805 $1\core_core_svstep$next[1:0]$13806 $1\core_dec$next[63:0]$13808 $1\core_eint$next[0:0]$13809 $1\core_msr$next[63:0]$13810 $1\core_core_pc$next[63:0]$13803 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13619 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13620 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13621 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13622 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13623 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13624 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13625 \core_core_vl - assign $1\core_dec$next[63:0]$13626 \core_dec - assign $1\core_eint$next[0:0]$13627 \core_eint - assign $1\core_msr$next[63:0]$13628 \core_msr + assign $1\core_core_dststep$next[6:0]$13801 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13802 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13803 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13804 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13805 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13806 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13807 \core_core_vl + assign $1\core_dec$next[63:0]$13808 \core_dec + assign $1\core_eint$next[0:0]$13809 \core_eint + assign $1\core_msr$next[63:0]$13810 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -408737,200 +412718,200 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13641 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13648 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13647 1'0 - assign $3\core_dec$next[63:0]$13646 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13644 2'00 - assign $3\core_core_subvl$next[1:0]$13643 2'00 - assign $3\core_core_dststep$next[6:0]$13639 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13642 7'0000000 - assign $3\core_core_vl$next[6:0]$13645 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13640 7'0000000 + assign $3\core_core_pc$next[63:0]$13823 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13830 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13829 1'0 + assign $3\core_dec$next[63:0]$13828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13826 2'00 + assign $3\core_core_subvl$next[1:0]$13825 2'00 + assign $3\core_core_dststep$next[6:0]$13821 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13824 7'0000000 + assign $3\core_core_vl$next[6:0]$13827 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13822 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13639 $1\core_core_dststep$next[6:0]$13619 - assign $3\core_core_maxvl$next[6:0]$13640 $1\core_core_maxvl$next[6:0]$13620 - assign $3\core_core_pc$next[63:0]$13641 $1\core_core_pc$next[63:0]$13621 - assign $3\core_core_srcstep$next[6:0]$13642 $1\core_core_srcstep$next[6:0]$13622 - assign $3\core_core_subvl$next[1:0]$13643 $1\core_core_subvl$next[1:0]$13623 - assign $3\core_core_svstep$next[1:0]$13644 $1\core_core_svstep$next[1:0]$13624 - assign $3\core_core_vl$next[6:0]$13645 $1\core_core_vl$next[6:0]$13625 - assign $3\core_dec$next[63:0]$13646 $1\core_dec$next[63:0]$13626 - assign $3\core_eint$next[0:0]$13647 $1\core_eint$next[0:0]$13627 - assign $3\core_msr$next[63:0]$13648 $1\core_msr$next[63:0]$13628 + assign $3\core_core_dststep$next[6:0]$13821 $1\core_core_dststep$next[6:0]$13801 + assign $3\core_core_maxvl$next[6:0]$13822 $1\core_core_maxvl$next[6:0]$13802 + assign $3\core_core_pc$next[63:0]$13823 $1\core_core_pc$next[63:0]$13803 + assign $3\core_core_srcstep$next[6:0]$13824 $1\core_core_srcstep$next[6:0]$13804 + assign $3\core_core_subvl$next[1:0]$13825 $1\core_core_subvl$next[1:0]$13805 + assign $3\core_core_svstep$next[1:0]$13826 $1\core_core_svstep$next[1:0]$13806 + assign $3\core_core_vl$next[6:0]$13827 $1\core_core_vl$next[6:0]$13807 + assign $3\core_dec$next[63:0]$13828 $1\core_dec$next[63:0]$13808 + assign $3\core_eint$next[0:0]$13829 $1\core_eint$next[0:0]$13809 + assign $3\core_msr$next[63:0]$13830 $1\core_msr$next[63:0]$13810 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13609 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13610 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13611 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13612 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13613 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13614 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13615 - update \core_dec$next $0\core_dec$next[63:0]$13616 - update \core_eint$next $0\core_eint$next[0:0]$13617 - update \core_msr$next $0\core_msr$next[63:0]$13618 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13791 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13792 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13793 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13794 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13795 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13796 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13797 + update \core_dec$next $0\core_dec$next[63:0]$13798 + update \core_eint$next $0\core_eint$next[0:0]$13799 + update \core_msr$next $0\core_msr$next[63:0]$13800 end - attribute \src "libresoc.v:195833.3-195853.6" - process $proc$libresoc.v:195833$13649 + attribute \src "libresoc.v:198119.3-198139.6" + process $proc$libresoc.v:198119$13831 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13650 $3\core_raw_insn_i$next[31:0]$13653 - attribute \src "libresoc.v:195834.5-195834.29" + assign $0\core_raw_insn_i$next[31:0]$13832 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:198120.5-198120.29" switch \initial - attribute \src "libresoc.v:195834.9-195834.17" + attribute \src "libresoc.v:198120.9-198120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13651 $2\core_raw_insn_i$next[31:0]$13652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_raw_insn_i$next[31:0]$13833 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13652 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13834 \dec2_raw_opcode_in case - assign $2\core_raw_insn_i$next[31:0]$13652 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13834 \core_raw_insn_i end case - assign $1\core_raw_insn_i$next[31:0]$13651 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13833 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13653 0 + assign $3\core_raw_insn_i$next[31:0]$13835 0 case - assign $3\core_raw_insn_i$next[31:0]$13653 $1\core_raw_insn_i$next[31:0]$13651 + assign $3\core_raw_insn_i$next[31:0]$13835 $1\core_raw_insn_i$next[31:0]$13833 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13650 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13832 end - attribute \src "libresoc.v:195854.3-195878.6" - process $proc$libresoc.v:195854$13654 + attribute \src "libresoc.v:198140.3-198164.6" + process $proc$libresoc.v:198140$13836 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13655 $3\core_bigendian_i$10$next[0:0]$13658 - attribute \src "libresoc.v:195855.5-195855.29" + assign $0\core_bigendian_i$10$next[0:0]$13837 $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:198141.5-198141.29" switch \initial - attribute \src "libresoc.v:195855.9-195855.17" + attribute \src "libresoc.v:198141.9-198141.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13656 $2\core_bigendian_i$10$next[0:0]$13657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_bigendian_i$10$next[0:0]$13838 $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i case - assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i$10 + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i$10 end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13658 1'0 + assign $3\core_bigendian_i$10$next[0:0]$13840 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13658 $1\core_bigendian_i$10$next[0:0]$13656 + assign $3\core_bigendian_i$10$next[0:0]$13840 $1\core_bigendian_i$10$next[0:0]$13838 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13655 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13837 end - attribute \src "libresoc.v:195879.3-195903.6" - process $proc$libresoc.v:195879$13659 + attribute \src "libresoc.v:198165.3-198189.6" + process $proc$libresoc.v:198165$13841 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13660 $3\core_sv_a_nz$next[0:0]$13663 - attribute \src "libresoc.v:195880.5-195880.29" + assign $0\core_sv_a_nz$next[0:0]$13842 $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198166.5-198166.29" switch \initial - attribute \src "libresoc.v:195880.9-195880.17" + attribute \src "libresoc.v:198166.9-198166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13661 $2\core_sv_a_nz$next[0:0]$13662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_sv_a_nz$next[0:0]$13843 $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13662 \dec2_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13844 \dec2_sv_a_nz case - assign $2\core_sv_a_nz$next[0:0]$13662 \core_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13844 \core_sv_a_nz end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13661 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13843 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13661 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13843 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13663 1'0 + assign $3\core_sv_a_nz$next[0:0]$13845 1'0 case - assign $3\core_sv_a_nz$next[0:0]$13663 $1\core_sv_a_nz$next[0:0]$13661 + assign $3\core_sv_a_nz$next[0:0]$13845 $1\core_sv_a_nz$next[0:0]$13843 end sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13660 + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13842 end - attribute \src "libresoc.v:195904.3-195941.6" - process $proc$libresoc.v:195904$13664 + attribute \src "libresoc.v:198190.3-198227.6" + process $proc$libresoc.v:198190$13846 assign { } { } assign { } { } assign { } { } assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:195905.5-195905.29" + attribute \src "libresoc.v:198191.5-198191.29" switch \initial - attribute \src "libresoc.v:195905.9-195905.17" + attribute \src "libresoc.v:198191.9-198191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\insn_done[0:0] $2\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\insn_done[0:0] $3\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \$228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$234 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -408944,19 +412925,19 @@ module \ti case assign $1\insn_done[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\insn_done[0:0] $5\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$236 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\insn_done[0:0] $6\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408974,131 +412955,136 @@ module \ti sync always update \insn_done $0\insn_done[0:0] end - attribute \src "libresoc.v:195942.3-195952.6" - process $proc$libresoc.v:195942$13665 + attribute \src "libresoc.v:198228.3-198238.6" + process $proc$libresoc.v:198228$13847 assign { } { } assign { } { } - assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195943.5-195943.29" + assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198229.5-198229.29" switch \initial - attribute \src "libresoc.v:195943.9-195943.17" + attribute \src "libresoc.v:198229.9-198229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 3'011 assign { } { } - assign $1\exec_insn_valid_i[0:0] 1'1 + assign $1\pred_insn_valid_i[0:0] 1'1 case - assign $1\exec_insn_valid_i[0:0] 1'0 + assign $1\pred_insn_valid_i[0:0] 1'0 end sync always - update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] end - attribute \src "libresoc.v:195953.3-195968.6" - process $proc$libresoc.v:195953$13666 + attribute \src "libresoc.v:198239.3-198249.6" + process $proc$libresoc.v:198239$13848 assign { } { } assign { } { } - assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:195954.5-195954.29" + assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:198240.5-198240.29" switch \initial - attribute \src "libresoc.v:195954.9-195954.17" + attribute \src "libresoc.v:198240.9-198240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'100 assign { } { } - assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$236 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\exec_pc_ready_i[0:0] 1'1 - case - assign $2\exec_pc_ready_i[0:0] 1'0 - end + assign $1\pred_mask_ready_i[0:0] 1'1 case - assign $1\exec_pc_ready_i[0:0] 1'0 + assign $1\pred_mask_ready_i[0:0] 1'0 end sync always - update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] + update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] end - attribute \src "libresoc.v:195969.3-195989.6" - process $proc$libresoc.v:195969$13667 + attribute \src "libresoc.v:198250.3-198260.6" + process $proc$libresoc.v:198250$13849 assign { } { } assign { } { } - assign $0\next_srcstep[6:0] $1\next_srcstep[6:0] - attribute \src "libresoc.v:195970.5-195970.29" + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198251.5-198251.29" switch \initial - attribute \src "libresoc.v:195970.9-195970.17" + attribute \src "libresoc.v:198251.9-198251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'010 assign { } { } - assign $1\next_srcstep[6:0] $2\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + assign $1\exec_insn_valid_i[0:0] 1'1 + case + assign $1\exec_insn_valid_i[0:0] 1'0 + end + sync always + update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + end + attribute \src "libresoc.v:198261.3-198276.6" + process $proc$libresoc.v:198261$13850 + assign { } { } + assign { } { } + assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198262.5-198262.29" + switch \initial + attribute \src "libresoc.v:198262.9-198262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$242 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\next_srcstep[6:0] $3\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" - switch \exec_pc_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\next_srcstep[6:0] \$244 [6:0] - case - assign $3\next_srcstep[6:0] 7'0000000 - end + assign $2\exec_pc_ready_i[0:0] 1'1 case - assign $2\next_srcstep[6:0] 7'0000000 + assign $2\exec_pc_ready_i[0:0] 1'0 end case - assign $1\next_srcstep[6:0] 7'0000000 + assign $1\exec_pc_ready_i[0:0] 1'0 end sync always - update \next_srcstep $0\next_srcstep[6:0] + update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:195990.3-196010.6" - process $proc$libresoc.v:195990$13668 + attribute \src "libresoc.v:198277.3-198297.6" + process $proc$libresoc.v:198277$13851 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:195991.5-195991.29" + attribute \src "libresoc.v:198278.5-198278.29" switch \initial - attribute \src "libresoc.v:195991.9-195991.17" + attribute \src "libresoc.v:198278.9-198278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$248 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\is_last[0:0] \$253 + assign $3\is_last[0:0] \$250 case assign $3\is_last[0:0] 1'0 end @@ -409111,64 +413097,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:196011.3-196020.6" - process $proc$libresoc.v:196011$13669 + attribute \src "libresoc.v:198298.3-198307.6" + process $proc$libresoc.v:198298$13852 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13670 $1\core_wen$11[2:0]$13671 - attribute \src "libresoc.v:196012.5-196012.29" + assign $0\core_wen$11[2:0]$13853 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198299.5-198299.29" switch \initial - attribute \src "libresoc.v:196012.9-196012.17" + attribute \src "libresoc.v:198299.9-198299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13671 3'100 + assign $1\core_wen$11[2:0]$13854 3'100 case - assign $1\core_wen$11[2:0]$13671 3'000 + assign $1\core_wen$11[2:0]$13854 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13670 + update \core_wen$11 $0\core_wen$11[2:0]$13853 end - attribute \src "libresoc.v:196021.3-196030.6" - process $proc$libresoc.v:196021$13672 + attribute \src "libresoc.v:198308.3-198317.6" + process $proc$libresoc.v:198308$13855 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13673 $1\core_data_i$12[63:0]$13674 - attribute \src "libresoc.v:196022.5-196022.29" + assign $0\core_data_i$12[63:0]$13856 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198309.5-198309.29" switch \initial - attribute \src "libresoc.v:196022.9-196022.17" + attribute \src "libresoc.v:198309.9-198309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13674 \$255 + assign $1\core_data_i$12[63:0]$13857 \$252 case - assign $1\core_data_i$12[63:0]$13674 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13857 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13673 + update \core_data_i$12 $0\core_data_i$12[63:0]$13856 end - attribute \src "libresoc.v:196031.3-196041.6" - process $proc$libresoc.v:196031$13675 + attribute \src "libresoc.v:198318.3-198328.6" + process $proc$libresoc.v:198318$13858 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:196032.5-196032.29" + attribute \src "libresoc.v:198319.5-198319.29" switch \initial - attribute \src "libresoc.v:196032.9-196032.17" + attribute \src "libresoc.v:198319.9-198319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -409180,24 +413166,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:196042.3-196066.6" - process $proc$libresoc.v:196042$13676 + attribute \src "libresoc.v:198329.3-198353.6" + process $proc$libresoc.v:198329$13859 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:196043.5-196043.29" + attribute \src "libresoc.v:198330.5-198330.29" switch \initial - attribute \src "libresoc.v:196043.9-196043.17" + attribute \src "libresoc.v:198330.9-198330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409210,8 +413196,8 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - switch \$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + switch \$254 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -409225,24 +413211,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:196067.3-196082.6" - process $proc$libresoc.v:196067$13677 + attribute \src "libresoc.v:198354.3-198369.6" + process $proc$libresoc.v:198354$13860 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:196068.5-196068.29" + attribute \src "libresoc.v:198355.5-198355.29" switch \initial - attribute \src "libresoc.v:196068.9-196068.17" + attribute \src "libresoc.v:198355.9-198355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409257,89 +413243,89 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:196083.3-196117.6" - process $proc$libresoc.v:196083$13678 + attribute \src "libresoc.v:198370.3-198404.6" + process $proc$libresoc.v:198370$13861 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13679 $5\exec_fsm_state$next[0:0]$13684 - attribute \src "libresoc.v:196084.5-196084.29" + assign $0\exec_fsm_state$next[0:0]$13862 $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:198371.5-198371.29" switch \initial - attribute \src "libresoc.v:196084.9-196084.17" + attribute \src "libresoc.v:198371.9-198371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13680 $2\exec_fsm_state$next[0:0]$13681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $1\exec_fsm_state$next[0:0]$13863 $2\exec_fsm_state$next[0:0]$13864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13681 1'1 + assign $2\exec_fsm_state$next[0:0]$13864 1'1 case - assign $2\exec_fsm_state$next[0:0]$13681 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13864 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13680 $3\exec_fsm_state$next[0:0]$13682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$259 + assign $1\exec_fsm_state$next[0:0]$13863 $3\exec_fsm_state$next[0:0]$13865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13682 $4\exec_fsm_state$next[0:0]$13683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + assign $3\exec_fsm_state$next[0:0]$13865 $4\exec_fsm_state$next[0:0]$13866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13683 1'0 + assign $4\exec_fsm_state$next[0:0]$13866 1'0 case - assign $4\exec_fsm_state$next[0:0]$13683 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13866 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13682 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13865 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13680 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13863 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13684 1'0 + assign $5\exec_fsm_state$next[0:0]$13867 1'0 case - assign $5\exec_fsm_state$next[0:0]$13684 $1\exec_fsm_state$next[0:0]$13680 + assign $5\exec_fsm_state$next[0:0]$13867 $1\exec_fsm_state$next[0:0]$13863 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13679 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13862 end - attribute \src "libresoc.v:196118.3-196133.6" - process $proc$libresoc.v:196118$13685 + attribute \src "libresoc.v:198405.3-198420.6" + process $proc$libresoc.v:198405$13868 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196119.5-196119.29" + attribute \src "libresoc.v:198406.5-198406.29" switch \initial - attribute \src "libresoc.v:196119.9-196119.17" + attribute \src "libresoc.v:198406.9-198406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -409353,18 +413339,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:196134.3-196143.6" - process $proc$libresoc.v:196134$13686 + attribute \src "libresoc.v:198421.3-198430.6" + process $proc$libresoc.v:198421$13869 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:196135.5-196135.29" + attribute \src "libresoc.v:198422.5-198422.29" switch \initial - attribute \src "libresoc.v:196135.9-196135.17" + attribute \src "libresoc.v:198422.9-198422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409376,18 +413362,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:196144.3-196153.6" - process $proc$libresoc.v:196144$13687 + attribute \src "libresoc.v:198431.3-198440.6" + process $proc$libresoc.v:198431$13870 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:196145.5-196145.29" + attribute \src "libresoc.v:198432.5-198432.29" switch \initial - attribute \src "libresoc.v:196145.9-196145.17" + attribute \src "libresoc.v:198432.9-198432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409399,14 +413385,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:196154.3-196162.6" - process $proc$libresoc.v:196154$13688 + attribute \src "libresoc.v:198441.3-198449.6" + process $proc$libresoc.v:198441$13871 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13689 $1\d_reg_delay$next[0:0]$13690 - attribute \src "libresoc.v:196155.5-196155.29" + assign $0\d_reg_delay$next[0:0]$13872 $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:198442.5-198442.29" switch \initial - attribute \src "libresoc.v:196155.9-196155.17" + attribute \src "libresoc.v:198442.9-198442.17" case 1'1 case end @@ -409415,25 +413401,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13690 1'0 + assign $1\d_reg_delay$next[0:0]$13873 1'0 case - assign $1\d_reg_delay$next[0:0]$13690 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13873 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13689 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13872 end - attribute \src "libresoc.v:196163.3-196172.6" - process $proc$libresoc.v:196163$13691 + attribute \src "libresoc.v:198450.3-198459.6" + process $proc$libresoc.v:198450$13874 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196164.5-196164.29" + attribute \src "libresoc.v:198451.5-198451.29" switch \initial - attribute \src "libresoc.v:196164.9-196164.17" + attribute \src "libresoc.v:198451.9-198451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409445,18 +413431,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:196173.3-196182.6" - process $proc$libresoc.v:196173$13692 + attribute \src "libresoc.v:198460.3-198469.6" + process $proc$libresoc.v:198460$13875 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196174.5-196174.29" + attribute \src "libresoc.v:198461.5-198461.29" switch \initial - attribute \src "libresoc.v:196174.9-196174.17" + attribute \src "libresoc.v:198461.9-198461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409468,18 +413454,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:196183.3-196192.6" - process $proc$libresoc.v:196183$13693 + attribute \src "libresoc.v:198470.3-198479.6" + process $proc$libresoc.v:198470$13876 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196184.5-196184.29" + attribute \src "libresoc.v:198471.5-198471.29" switch \initial - attribute \src "libresoc.v:196184.9-196184.17" + attribute \src "libresoc.v:198471.9-198471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409491,14 +413477,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:196193.3-196201.6" - process $proc$libresoc.v:196193$13694 + attribute \src "libresoc.v:198480.3-198488.6" + process $proc$libresoc.v:198480$13877 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13695 $1\d_cr_delay$next[0:0]$13696 - attribute \src "libresoc.v:196194.5-196194.29" + assign $0\d_cr_delay$next[0:0]$13878 $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:198481.5-198481.29" switch \initial - attribute \src "libresoc.v:196194.9-196194.17" + attribute \src "libresoc.v:198481.9-198481.17" case 1'1 case end @@ -409507,48 +413493,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13696 1'0 + assign $1\d_cr_delay$next[0:0]$13879 1'0 case - assign $1\d_cr_delay$next[0:0]$13696 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13879 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13695 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13878 end - attribute \src "libresoc.v:196202.3-196211.6" - process $proc$libresoc.v:196202$13697 + attribute \src "libresoc.v:198489.3-198498.6" + process $proc$libresoc.v:198489$13880 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196203.5-196203.29" + attribute \src "libresoc.v:198490.5-198490.29" switch \initial - attribute \src "libresoc.v:196203.9-196203.17" + attribute \src "libresoc.v:198490.9-198490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$263 + assign $1\dbg_d_cr_data[63:0] \$260 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:196212.3-196221.6" - process $proc$libresoc.v:196212$13698 + attribute \src "libresoc.v:198499.3-198508.6" + process $proc$libresoc.v:198499$13881 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196213.5-196213.29" + attribute \src "libresoc.v:198500.5-198500.29" switch \initial - attribute \src "libresoc.v:196213.9-196213.17" + attribute \src "libresoc.v:198500.9-198500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409560,18 +413546,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:196222.3-196231.6" - process $proc$libresoc.v:196222$13699 + attribute \src "libresoc.v:198509.3-198518.6" + process $proc$libresoc.v:198509$13882 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196223.5-196223.29" + attribute \src "libresoc.v:198510.5-198510.29" switch \initial - attribute \src "libresoc.v:196223.9-196223.17" + attribute \src "libresoc.v:198510.9-198510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:964" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409583,14 +413569,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:196232.3-196240.6" - process $proc$libresoc.v:196232$13700 + attribute \src "libresoc.v:198519.3-198527.6" + process $proc$libresoc.v:198519$13883 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13701 $1\d_xer_delay$next[0:0]$13702 - attribute \src "libresoc.v:196233.5-196233.29" + assign $0\d_xer_delay$next[0:0]$13884 $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:198520.5-198520.29" switch \initial - attribute \src "libresoc.v:196233.9-196233.17" + attribute \src "libresoc.v:198520.9-198520.17" case 1'1 case end @@ -409599,48 +413585,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13702 1'0 + assign $1\d_xer_delay$next[0:0]$13885 1'0 case - assign $1\d_xer_delay$next[0:0]$13702 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13885 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13701 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13884 end - attribute \src "libresoc.v:196241.3-196250.6" - process $proc$libresoc.v:196241$13703 + attribute \src "libresoc.v:198528.3-198537.6" + process $proc$libresoc.v:198528$13886 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:196242.5-196242.29" + attribute \src "libresoc.v:198529.5-198529.29" switch \initial - attribute \src "libresoc.v:196242.9-196242.17" + attribute \src "libresoc.v:198529.9-198529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$265 + assign $1\dbg_d_xer_data[63:0] \$262 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:196251.3-196260.6" - process $proc$libresoc.v:196251$13704 + attribute \src "libresoc.v:198538.3-198547.6" + process $proc$libresoc.v:198538$13887 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196252.5-196252.29" + attribute \src "libresoc.v:198539.5-198539.29" switch \initial - attribute \src "libresoc.v:196252.9-196252.17" + attribute \src "libresoc.v:198539.9-198539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409652,18 +413638,18 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:196261.3-196275.6" - process $proc$libresoc.v:196261$13705 + attribute \src "libresoc.v:198548.3-198562.6" + process $proc$libresoc.v:198548$13888 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:196262.5-196262.29" + attribute \src "libresoc.v:198549.5-198549.29" switch \initial - attribute \src "libresoc.v:196262.9-196262.17" + attribute \src "libresoc.v:198549.9-198549.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -409679,18 +413665,18 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:196276.3-196290.6" - process $proc$libresoc.v:196276$13706 + attribute \src "libresoc.v:198563.3-198577.6" + process $proc$libresoc.v:198563$13889 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:196277.5-196277.29" + attribute \src "libresoc.v:198564.5-198564.29" switch \initial - attribute \src "libresoc.v:196277.9-196277.17" + attribute \src "libresoc.v:198564.9-198564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -409706,113 +413692,113 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:196291.3-196318.6" - process $proc$libresoc.v:196291$13707 + attribute \src "libresoc.v:198578.3-198605.6" + process $proc$libresoc.v:198578$13890 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13708 $2\fsm_state$next[1:0]$13710 - attribute \src "libresoc.v:196292.5-196292.29" + assign $0\fsm_state$next[1:0]$13891 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198579.5-198579.29" switch \initial - attribute \src "libresoc.v:196292.9-196292.17" + attribute \src "libresoc.v:198579.9-198579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'01 + assign $1\fsm_state$next[1:0]$13892 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'10 + assign $1\fsm_state$next[1:0]$13892 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'11 + assign $1\fsm_state$next[1:0]$13892 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'00 + assign $1\fsm_state$next[1:0]$13892 2'00 case - assign $1\fsm_state$next[1:0]$13709 \fsm_state + assign $1\fsm_state$next[1:0]$13892 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13710 2'00 + assign $2\fsm_state$next[1:0]$13893 2'00 case - assign $2\fsm_state$next[1:0]$13710 $1\fsm_state$next[1:0]$13709 + assign $2\fsm_state$next[1:0]$13893 $1\fsm_state$next[1:0]$13892 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13708 + update \fsm_state$next $0\fsm_state$next[1:0]$13891 end - attribute \src "libresoc.v:196319.3-196329.6" - process $proc$libresoc.v:196319$13711 + attribute \src "libresoc.v:198606.3-198616.6" + process $proc$libresoc.v:198606$13894 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:196320.5-196320.29" + attribute \src "libresoc.v:198607.5-198607.29" switch \initial - attribute \src "libresoc.v:196320.9-196320.17" + attribute \src "libresoc.v:198607.9-198607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$267 [63:0] + assign $1\new_dec[63:0] \$264 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:196330.3-196344.6" - process $proc$libresoc.v:196330$13712 + attribute \src "libresoc.v:198617.3-198631.6" + process $proc$libresoc.v:198617$13895 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13713 $1\core_issue__addr$13[2:0]$13714 - attribute \src "libresoc.v:196331.5-196331.29" + assign $0\core_issue__addr$13[2:0]$13896 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198618.5-198618.29" switch \initial - attribute \src "libresoc.v:196331.9-196331.17" + attribute \src "libresoc.v:198618.9-198618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13714 3'110 + assign $1\core_issue__addr$13[2:0]$13897 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13714 3'111 + assign $1\core_issue__addr$13[2:0]$13897 3'111 case - assign $1\core_issue__addr$13[2:0]$13714 3'000 + assign $1\core_issue__addr$13[2:0]$13897 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13713 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13896 end - attribute \src "libresoc.v:196345.3-196359.6" - process $proc$libresoc.v:196345$13715 + attribute \src "libresoc.v:198632.3-198646.6" + process $proc$libresoc.v:198632$13898 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:196346.5-196346.29" + attribute \src "libresoc.v:198633.5-198633.29" switch \initial - attribute \src "libresoc.v:196346.9-196346.17" + attribute \src "libresoc.v:198633.9-198633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -409828,18 +413814,18 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:196360.3-196374.6" - process $proc$libresoc.v:196360$13716 + attribute \src "libresoc.v:198647.3-198661.6" + process $proc$libresoc.v:198647$13899 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:196361.5-196361.29" + attribute \src "libresoc.v:198648.5-198648.29" switch \initial - attribute \src "libresoc.v:196361.9-196361.17" + attribute \src "libresoc.v:198648.9-198648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -409855,70 +413841,70 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:196375.3-196390.6" - process $proc$libresoc.v:196375$13717 + attribute \src "libresoc.v:198662.3-198677.6" + process $proc$libresoc.v:198662$13900 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13718 $2\dec2_cur_dec$next[63:0]$13720 - attribute \src "libresoc.v:196376.5-196376.29" + assign $0\dec2_cur_dec$next[63:0]$13901 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:198663.5-198663.29" switch \initial - attribute \src "libresoc.v:196376.9-196376.17" + attribute \src "libresoc.v:198663.9-198663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13719 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13902 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13719 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13902 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13720 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13720 $1\dec2_cur_dec$next[63:0]$13719 + assign $2\dec2_cur_dec$next[63:0]$13903 $1\dec2_cur_dec$next[63:0]$13902 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13718 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13901 end - attribute \src "libresoc.v:196391.3-196401.6" - process $proc$libresoc.v:196391$13721 + attribute \src "libresoc.v:198678.3-198688.6" + process $proc$libresoc.v:198678$13904 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:196392.5-196392.29" + attribute \src "libresoc.v:198679.5-198679.29" switch \initial - attribute \src "libresoc.v:196392.9-196392.17" + attribute \src "libresoc.v:198679.9-198679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$270 [63:0] + assign $1\new_tb[63:0] \$267 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:196402.3-196410.6" - process $proc$libresoc.v:196402$13722 + attribute \src "libresoc.v:198689.3-198697.6" + process $proc$libresoc.v:198689$13905 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13723 $1\dbg_dmi_we_i$next[0:0]$13724 - attribute \src "libresoc.v:196403.5-196403.29" + assign $0\dbg_dmi_we_i$next[0:0]$13906 $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:198690.5-198690.29" switch \initial - attribute \src "libresoc.v:196403.9-196403.17" + attribute \src "libresoc.v:198690.9-198690.17" case 1'1 case end @@ -409927,21 +413913,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13724 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13907 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13724 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13907 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13723 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13906 end - attribute \src "libresoc.v:196411.3-196419.6" - process $proc$libresoc.v:196411$13725 + attribute \src "libresoc.v:198698.3-198706.6" + process $proc$libresoc.v:198698$13908 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13726 $1\pc_ok_delay$next[0:0]$13727 - attribute \src "libresoc.v:196412.5-196412.29" + assign $0\pc_ok_delay$next[0:0]$13909 $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:198699.5-198699.29" switch \initial - attribute \src "libresoc.v:196412.9-196412.17" + attribute \src "libresoc.v:198699.9-198699.17" case 1'1 case end @@ -409950,26 +413936,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13727 1'0 + assign $1\pc_ok_delay$next[0:0]$13910 1'0 case - assign $1\pc_ok_delay$next[0:0]$13727 \$38 + assign $1\pc_ok_delay$next[0:0]$13910 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13726 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13909 end - attribute \src "libresoc.v:196420.3-196435.6" - process $proc$libresoc.v:196420$13728 + attribute \src "libresoc.v:198707.3-198722.6" + process $proc$libresoc.v:198707$13911 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:196421.5-196421.29" + attribute \src "libresoc.v:198708.5-198708.29" switch \initial - attribute \src "libresoc.v:196421.9-196421.17" + attribute \src "libresoc.v:198708.9-198708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409978,7 +413964,7 @@ module \ti case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409990,18 +413976,18 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:196436.3-196448.6" - process $proc$libresoc.v:196436$13729 + attribute \src "libresoc.v:198723.3-198735.6" + process $proc$libresoc.v:198723$13912 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:196437.5-196437.29" + attribute \src "libresoc.v:198724.5-198724.29" switch \initial - attribute \src "libresoc.v:196437.9-196437.17" + attribute \src "libresoc.v:198724.9-198724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410014,14 +414000,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:196449.3-196457.6" - process $proc$libresoc.v:196449$13730 + attribute \src "libresoc.v:198736.3-198744.6" + process $proc$libresoc.v:198736$13913 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13731 $1\svstate_ok_delay$next[0:0]$13732 - attribute \src "libresoc.v:196450.5-196450.29" + assign $0\svstate_ok_delay$next[0:0]$13914 $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:198737.5-198737.29" switch \initial - attribute \src "libresoc.v:196450.9-196450.17" + attribute \src "libresoc.v:198737.9-198737.17" case 1'1 case end @@ -410030,26 +414016,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13732 1'0 + assign $1\svstate_ok_delay$next[0:0]$13915 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13732 \$40 + assign $1\svstate_ok_delay$next[0:0]$13915 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13731 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13914 end - attribute \src "libresoc.v:196458.3-196473.6" - process $proc$libresoc.v:196458$13733 + attribute \src "libresoc.v:198745.3-198760.6" + process $proc$libresoc.v:198745$13916 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:196459.5-196459.29" + attribute \src "libresoc.v:198746.5-198746.29" switch \initial - attribute \src "libresoc.v:196459.9-196459.17" + attribute \src "libresoc.v:198746.9-198746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410058,7 +414044,7 @@ module \ti case assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" switch \svstate_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410070,18 +414056,18 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:196474.3-196486.6" - process $proc$libresoc.v:196474$13734 + attribute \src "libresoc.v:198761.3-198773.6" + process $proc$libresoc.v:198761$13917 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:196475.5-196475.29" + attribute \src "libresoc.v:198762.5-198762.29" switch \initial - attribute \src "libresoc.v:196475.9-196475.17" + attribute \src "libresoc.v:198762.9-198762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410094,14 +414080,14 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:196487.3-196495.6" - process $proc$libresoc.v:196487$13735 + attribute \src "libresoc.v:198774.3-198782.6" + process $proc$libresoc.v:198774$13918 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13736 $1\dbg_dmi_din$next[63:0]$13737 - attribute \src "libresoc.v:196488.5-196488.29" + assign $0\dbg_dmi_din$next[63:0]$13919 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:198775.5-198775.29" switch \initial - attribute \src "libresoc.v:196488.9-196488.17" + attribute \src "libresoc.v:198775.9-198775.17" case 1'1 case end @@ -410110,31 +414096,31 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13737 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13920 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13737 \jtag_dmi0__din + assign $1\dbg_dmi_din$next[63:0]$13920 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13736 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13919 end - attribute \src "libresoc.v:196496.3-196563.6" - process $proc$libresoc.v:196496$13738 + attribute \src "libresoc.v:198783.3-198850.6" + process $proc$libresoc.v:198783$13921 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:196497.5-196497.29" + attribute \src "libresoc.v:198784.5-198784.29" switch \initial - attribute \src "libresoc.v:196497.9-196497.17" + attribute \src "libresoc.v:198784.9-198784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410143,7 +414129,7 @@ module \ti case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410157,13 +414143,13 @@ module \ti case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410176,22 +414162,22 @@ module \ti assign $4\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410210,7 +414196,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410226,24 +414212,24 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:196564.3-196631.6" - process $proc$libresoc.v:196564$13739 + attribute \src "libresoc.v:198851.3-198918.6" + process $proc$libresoc.v:198851$13922 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:196565.5-196565.29" + attribute \src "libresoc.v:198852.5-198852.29" switch \initial - attribute \src "libresoc.v:196565.9-196565.17" + attribute \src "libresoc.v:198852.9-198852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410252,7 +414238,7 @@ module \ti case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410266,13 +414252,13 @@ module \ti case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410285,22 +414271,22 @@ module \ti assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410319,7 +414305,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410335,24 +414321,24 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:196632.3-196647.6" - process $proc$libresoc.v:196632$13740 + attribute \src "libresoc.v:198919.3-198934.6" + process $proc$libresoc.v:198919$13923 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:196633.5-196633.29" + attribute \src "libresoc.v:198920.5-198920.29" switch \initial - attribute \src "libresoc.v:196633.9-196633.17" + attribute \src "libresoc.v:198920.9-198920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410367,14 +414353,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:196648.3-196656.6" - process $proc$libresoc.v:196648$13741 + attribute \src "libresoc.v:198935.3-198943.6" + process $proc$libresoc.v:198935$13924 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:196649.5-196649.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13925 $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:198936.5-198936.29" switch \initial - attribute \src "libresoc.v:196649.9-196649.17" + attribute \src "libresoc.v:198936.9-198936.17" case 1'1 case end @@ -410383,25 +414369,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 1'0 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 \dbg_dmi_ack_o end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13925 end - attribute \src "libresoc.v:196657.3-196667.6" - process $proc$libresoc.v:196657$13744 + attribute \src "libresoc.v:198944.3-198954.6" + process $proc$libresoc.v:198944$13927 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:196658.5-196658.29" + attribute \src "libresoc.v:198945.5-198945.29" switch \initial - attribute \src "libresoc.v:196658.9-196658.17" + attribute \src "libresoc.v:198945.9-198945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -410413,24 +414399,24 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:196668.3-196683.6" - process $proc$libresoc.v:196668$13745 + attribute \src "libresoc.v:198955.3-198970.6" + process $proc$libresoc.v:198955$13928 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196669.5-196669.29" + attribute \src "libresoc.v:198956.5-198956.29" switch \initial - attribute \src "libresoc.v:196669.9-196669.17" + attribute \src "libresoc.v:198956.9-198956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410445,24 +414431,24 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:196684.3-196717.6" - process $proc$libresoc.v:196684$13746 + attribute \src "libresoc.v:198971.3-199004.6" + process $proc$libresoc.v:198971$13929 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196685.5-196685.29" + attribute \src "libresoc.v:198972.5-198972.29" switch \initial - attribute \src "libresoc.v:196685.9-196685.17" + attribute \src "libresoc.v:198972.9-198972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410475,7 +414461,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410488,7 +414474,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410503,24 +414489,24 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:196718.3-196751.6" - process $proc$libresoc.v:196718$13747 + attribute \src "libresoc.v:199005.3-199038.6" + process $proc$libresoc.v:199005$13930 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:196719.5-196719.29" + attribute \src "libresoc.v:199006.5-199006.29" switch \initial - attribute \src "libresoc.v:196719.9-196719.17" + attribute \src "libresoc.v:199006.9-199006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410533,7 +414519,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410546,7 +414532,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410561,50 +414547,50 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:196752.3-196772.6" - process $proc$libresoc.v:196752$13748 + attribute \src "libresoc.v:199039.3-199059.6" + process $proc$libresoc.v:199039$13931 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13749 $3\dec2_cur_pc$next[63:0]$13752 - attribute \src "libresoc.v:196753.5-196753.29" + assign $0\dec2_cur_pc$next[63:0]$13932 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199040.5-199040.29" switch \initial - attribute \src "libresoc.v:196753.9-196753.17" + attribute \src "libresoc.v:199040.9-199040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13750 $2\dec2_cur_pc$next[63:0]$13751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\dec2_cur_pc$next[63:0]$13933 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13751 \pc + assign $2\dec2_cur_pc$next[63:0]$13934 \pc case - assign $2\dec2_cur_pc$next[63:0]$13751 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13934 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13750 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13933 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13752 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13935 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13752 $1\dec2_cur_pc$next[63:0]$13750 + assign $3\dec2_cur_pc$next[63:0]$13935 $1\dec2_cur_pc$next[63:0]$13933 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13749 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13932 end - attribute \src "libresoc.v:196773.3-196811.6" - process $proc$libresoc.v:196773$13753 + attribute \src "libresoc.v:199060.3-199098.6" + process $proc$libresoc.v:199060$13936 assign { } { } assign { } { } assign { } { } @@ -410629,19 +414615,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13754 $4\cur_cur_dststep$next[6:0]$13778 - assign $0\cur_cur_maxvl$next[6:0]$13755 $4\cur_cur_maxvl$next[6:0]$13779 - assign $0\cur_cur_srcstep$next[6:0]$13756 $4\cur_cur_srcstep$next[6:0]$13780 - assign $0\cur_cur_subvl$next[1:0]$13757 $4\cur_cur_subvl$next[1:0]$13781 - assign $0\cur_cur_svstep$next[1:0]$13758 $4\cur_cur_svstep$next[1:0]$13782 - assign $0\cur_cur_vl$next[6:0]$13759 $4\cur_cur_vl$next[6:0]$13783 - attribute \src "libresoc.v:196774.5-196774.29" + assign $0\cur_cur_dststep$next[6:0]$13937 $4\cur_cur_dststep$next[6:0]$13961 + assign $0\cur_cur_maxvl$next[6:0]$13938 $4\cur_cur_maxvl$next[6:0]$13962 + assign $0\cur_cur_srcstep$next[6:0]$13939 $4\cur_cur_srcstep$next[6:0]$13963 + assign $0\cur_cur_subvl$next[1:0]$13940 $4\cur_cur_subvl$next[1:0]$13964 + assign $0\cur_cur_svstep$next[1:0]$13941 $4\cur_cur_svstep$next[1:0]$13965 + assign $0\cur_cur_vl$next[6:0]$13942 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:199061.5-199061.29" switch \initial - attribute \src "libresoc.v:196774.9-196774.17" + attribute \src "libresoc.v:199061.9-199061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -410651,13 +414637,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13760 $2\cur_cur_dststep$next[6:0]$13766 - assign $1\cur_cur_maxvl$next[6:0]$13761 $2\cur_cur_maxvl$next[6:0]$13767 - assign $1\cur_cur_srcstep$next[6:0]$13762 $2\cur_cur_srcstep$next[6:0]$13768 - assign $1\cur_cur_subvl$next[1:0]$13763 $2\cur_cur_subvl$next[1:0]$13769 - assign $1\cur_cur_svstep$next[1:0]$13764 $2\cur_cur_svstep$next[1:0]$13770 - assign $1\cur_cur_vl$next[6:0]$13765 $2\cur_cur_vl$next[6:0]$13771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\cur_cur_dststep$next[6:0]$13943 $2\cur_cur_dststep$next[6:0]$13949 + assign $1\cur_cur_maxvl$next[6:0]$13944 $2\cur_cur_maxvl$next[6:0]$13950 + assign $1\cur_cur_srcstep$next[6:0]$13945 $2\cur_cur_srcstep$next[6:0]$13951 + assign $1\cur_cur_subvl$next[1:0]$13946 $2\cur_cur_subvl$next[1:0]$13952 + assign $1\cur_cur_svstep$next[1:0]$13947 $2\cur_cur_svstep$next[1:0]$13953 + assign $1\cur_cur_vl$next[6:0]$13948 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410667,24 +414653,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13767 $2\cur_cur_vl$next[6:0]$13771 $2\cur_cur_srcstep$next[6:0]$13768 $2\cur_cur_dststep$next[6:0]$13766 $2\cur_cur_subvl$next[1:0]$13769 $2\cur_cur_svstep$next[1:0]$13770 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13950 $2\cur_cur_vl$next[6:0]$13954 $2\cur_cur_srcstep$next[6:0]$13951 $2\cur_cur_dststep$next[6:0]$13949 $2\cur_cur_subvl$next[1:0]$13952 $2\cur_cur_svstep$next[1:0]$13953 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13766 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13767 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13768 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13769 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13770 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13771 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13949 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13950 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13951 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13952 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13953 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13954 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13760 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13761 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13762 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13763 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13764 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13765 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13943 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13944 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13945 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13946 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13947 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13948 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410694,14 +414680,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13773 $3\cur_cur_vl$next[6:0]$13777 $3\cur_cur_srcstep$next[6:0]$13774 $3\cur_cur_dststep$next[6:0]$13772 $3\cur_cur_subvl$next[1:0]$13775 $3\cur_cur_svstep$next[1:0]$13776 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13956 $3\cur_cur_vl$next[6:0]$13960 $3\cur_cur_srcstep$next[6:0]$13957 $3\cur_cur_dststep$next[6:0]$13955 $3\cur_cur_subvl$next[1:0]$13958 $3\cur_cur_svstep$next[1:0]$13959 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13772 $1\cur_cur_dststep$next[6:0]$13760 - assign $3\cur_cur_maxvl$next[6:0]$13773 $1\cur_cur_maxvl$next[6:0]$13761 - assign $3\cur_cur_srcstep$next[6:0]$13774 $1\cur_cur_srcstep$next[6:0]$13762 - assign $3\cur_cur_subvl$next[1:0]$13775 $1\cur_cur_subvl$next[1:0]$13763 - assign $3\cur_cur_svstep$next[1:0]$13776 $1\cur_cur_svstep$next[1:0]$13764 - assign $3\cur_cur_vl$next[6:0]$13777 $1\cur_cur_vl$next[6:0]$13765 + assign $3\cur_cur_dststep$next[6:0]$13955 $1\cur_cur_dststep$next[6:0]$13943 + assign $3\cur_cur_maxvl$next[6:0]$13956 $1\cur_cur_maxvl$next[6:0]$13944 + assign $3\cur_cur_srcstep$next[6:0]$13957 $1\cur_cur_srcstep$next[6:0]$13945 + assign $3\cur_cur_subvl$next[1:0]$13958 $1\cur_cur_subvl$next[1:0]$13946 + assign $3\cur_cur_svstep$next[1:0]$13959 $1\cur_cur_svstep$next[1:0]$13947 + assign $3\cur_cur_vl$next[6:0]$13960 $1\cur_cur_vl$next[6:0]$13948 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -410713,36 +414699,36 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13782 2'00 - assign $4\cur_cur_subvl$next[1:0]$13781 2'00 - assign $4\cur_cur_dststep$next[6:0]$13778 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13780 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13783 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13779 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13965 2'00 + assign $4\cur_cur_subvl$next[1:0]$13964 2'00 + assign $4\cur_cur_dststep$next[6:0]$13961 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13963 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13966 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13962 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13778 $3\cur_cur_dststep$next[6:0]$13772 - assign $4\cur_cur_maxvl$next[6:0]$13779 $3\cur_cur_maxvl$next[6:0]$13773 - assign $4\cur_cur_srcstep$next[6:0]$13780 $3\cur_cur_srcstep$next[6:0]$13774 - assign $4\cur_cur_subvl$next[1:0]$13781 $3\cur_cur_subvl$next[1:0]$13775 - assign $4\cur_cur_svstep$next[1:0]$13782 $3\cur_cur_svstep$next[1:0]$13776 - assign $4\cur_cur_vl$next[6:0]$13783 $3\cur_cur_vl$next[6:0]$13777 + assign $4\cur_cur_dststep$next[6:0]$13961 $3\cur_cur_dststep$next[6:0]$13955 + assign $4\cur_cur_maxvl$next[6:0]$13962 $3\cur_cur_maxvl$next[6:0]$13956 + assign $4\cur_cur_srcstep$next[6:0]$13963 $3\cur_cur_srcstep$next[6:0]$13957 + assign $4\cur_cur_subvl$next[1:0]$13964 $3\cur_cur_subvl$next[1:0]$13958 + assign $4\cur_cur_svstep$next[1:0]$13965 $3\cur_cur_svstep$next[1:0]$13959 + assign $4\cur_cur_vl$next[6:0]$13966 $3\cur_cur_vl$next[6:0]$13960 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13754 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13755 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13756 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13757 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13758 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13759 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13937 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13938 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13939 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13940 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13941 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13942 end - attribute \src "libresoc.v:196812.3-196820.6" - process $proc$libresoc.v:196812$13784 + attribute \src "libresoc.v:199099.3-199107.6" + process $proc$libresoc.v:199099$13967 assign { } { } assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13785 $1\jtag_dmi0__dout$next[63:0]$13786 - attribute \src "libresoc.v:196813.5-196813.29" + assign $0\jtag_dmi0__dout$next[63:0]$13968 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:199100.5-199100.29" switch \initial - attribute \src "libresoc.v:196813.9-196813.17" + attribute \src "libresoc.v:199100.9-199100.17" case 1'1 case end @@ -410751,285 +414737,285 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13786 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13969 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__dout$next[63:0]$13786 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13969 \dbg_dmi_dout end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13785 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13968 end - attribute \src "libresoc.v:196821.3-196850.6" - process $proc$libresoc.v:196821$13787 + attribute \src "libresoc.v:199108.3-199137.6" + process $proc$libresoc.v:199108$13970 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13788 $4\msr_read$next[0:0]$13792 - attribute \src "libresoc.v:196822.5-196822.29" + assign $0\msr_read$next[0:0]$13971 $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199109.5-199109.29" switch \initial - attribute \src "libresoc.v:196822.9-196822.17" + attribute \src "libresoc.v:199109.9-199109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13789 $2\msr_read$next[0:0]$13790 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\msr_read$next[0:0]$13972 $2\msr_read$next[0:0]$13973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13790 1'0 + assign $2\msr_read$next[0:0]$13973 1'0 case - assign $2\msr_read$next[0:0]$13790 \msr_read + assign $2\msr_read$next[0:0]$13973 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13789 $3\msr_read$next[0:0]$13791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\msr_read$next[0:0]$13972 $3\msr_read$next[0:0]$13974 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13791 1'1 + assign $3\msr_read$next[0:0]$13974 1'1 case - assign $3\msr_read$next[0:0]$13791 \msr_read + assign $3\msr_read$next[0:0]$13974 \msr_read end case - assign $1\msr_read$next[0:0]$13789 \msr_read + assign $1\msr_read$next[0:0]$13972 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13792 1'1 + assign $4\msr_read$next[0:0]$13975 1'1 case - assign $4\msr_read$next[0:0]$13792 $1\msr_read$next[0:0]$13789 + assign $4\msr_read$next[0:0]$13975 $1\msr_read$next[0:0]$13972 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13788 + update \msr_read$next $0\msr_read$next[0:0]$13971 end - attribute \src "libresoc.v:196851.3-196904.6" - process $proc$libresoc.v:196851$13793 + attribute \src "libresoc.v:199138.3-199191.6" + process $proc$libresoc.v:199138$13976 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13794 $6\fetch_fsm_state$next[1:0]$13800 - attribute \src "libresoc.v:196852.5-196852.29" + assign $0\fetch_fsm_state$next[1:0]$13977 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:199139.5-199139.29" switch \initial - attribute \src "libresoc.v:196852.9-196852.17" + attribute \src "libresoc.v:199139.9-199139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $2\fetch_fsm_state$next[1:0]$13796 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\fetch_fsm_state$next[1:0]$13978 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13796 2'01 + assign $2\fetch_fsm_state$next[1:0]$13979 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13796 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13979 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $3\fetch_fsm_state$next[1:0]$13797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\fetch_fsm_state$next[1:0]$13978 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13797 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13980 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13797 2'10 + assign $3\fetch_fsm_state$next[1:0]$13980 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $4\fetch_fsm_state$next[1:0]$13798 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + assign $1\fetch_fsm_state$next[1:0]$13978 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13798 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13981 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13798 2'10 + assign $4\fetch_fsm_state$next[1:0]$13981 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $5\fetch_fsm_state$next[1:0]$13799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254" + assign $1\fetch_fsm_state$next[1:0]$13978 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13799 2'00 + assign $5\fetch_fsm_state$next[1:0]$13982 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13799 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13982 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13795 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13978 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13800 2'00 + assign $6\fetch_fsm_state$next[1:0]$13983 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13800 $1\fetch_fsm_state$next[1:0]$13795 + assign $6\fetch_fsm_state$next[1:0]$13983 $1\fetch_fsm_state$next[1:0]$13978 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13794 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13977 end - attribute \src "libresoc.v:196905.3-196925.6" - process $proc$libresoc.v:196905$13801 + attribute \src "libresoc.v:199192.3-199212.6" + process $proc$libresoc.v:199192$13984 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13802 $3\dec2_cur_msr$next[63:0]$13805 - attribute \src "libresoc.v:196906.5-196906.29" + assign $0\dec2_cur_msr$next[63:0]$13985 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199193.5-199193.29" switch \initial - attribute \src "libresoc.v:196906.9-196906.17" + attribute \src "libresoc.v:199193.9-199193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13803 $2\dec2_cur_msr$next[63:0]$13804 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\dec2_cur_msr$next[63:0]$13986 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13804 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13987 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13804 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13987 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13803 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13986 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13805 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13988 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13805 $1\dec2_cur_msr$next[63:0]$13803 + assign $3\dec2_cur_msr$next[63:0]$13988 $1\dec2_cur_msr$next[63:0]$13986 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13802 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13985 end - attribute \src "libresoc.v:196926.3-196944.6" - process $proc$libresoc.v:196926$13806 + attribute \src "libresoc.v:199213.3-199231.6" + process $proc$libresoc.v:199213$13989 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13807 $1\nia$next[63:0]$13808 - attribute \src "libresoc.v:196927.5-196927.29" + assign $0\nia$next[63:0]$13990 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:199214.5-199214.29" switch \initial - attribute \src "libresoc.v:196927.9-196927.17" + attribute \src "libresoc.v:199214.9-199214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13808 $2\nia$next[63:0]$13809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\nia$next[63:0]$13991 $2\nia$next[63:0]$13992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13809 \nia + assign $2\nia$next[63:0]$13992 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13809 \$92 [63:0] + assign $2\nia$next[63:0]$13992 \$92 [63:0] end case - assign $1\nia$next[63:0]$13808 \nia + assign $1\nia$next[63:0]$13991 \nia end sync always - update \nia$next $0\nia$next[63:0]$13807 + update \nia$next $0\nia$next[63:0]$13990 end - attribute \src "libresoc.v:196945.3-196975.6" - process $proc$libresoc.v:196945$13810 + attribute \src "libresoc.v:199232.3-199262.6" + process $proc$libresoc.v:199232$13993 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13811 $1\dec2_raw_opcode_in$next[31:0]$13812 - attribute \src "libresoc.v:196946.5-196946.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13994 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:199233.5-199233.29" switch \initial - attribute \src "libresoc.v:196946.9-196946.17" + attribute \src "libresoc.v:199233.9-199233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13812 $2\dec2_raw_opcode_in$next[31:0]$13813 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13813 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13813 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13812 $3\dec2_raw_opcode_in$next[31:0]$13814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13814 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13814 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13812 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13995 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13811 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13994 end - attribute \src "libresoc.v:196976.3-196986.6" - process $proc$libresoc.v:196976$13815 + attribute \src "libresoc.v:199263.3-199273.6" + process $proc$libresoc.v:199263$13998 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196977.5-196977.29" + attribute \src "libresoc.v:199264.5-199264.29" switch \initial - attribute \src "libresoc.v:196977.9-196977.17" + attribute \src "libresoc.v:199264.9-199264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -411041,8 +415027,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:196987.3-197043.6" - process $proc$libresoc.v:196987$13816 + attribute \src "libresoc.v:199274.3-199333.6" + process $proc$libresoc.v:199274$13999 assign { } { } assign { } { } assign { } { } @@ -411056,13 +415042,13 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:196988.5-196988.29" + attribute \src "libresoc.v:199275.5-199275.29" switch \initial - attribute \src "libresoc.v:196988.9-196988.17" + attribute \src "libresoc.v:199275.9-199275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -411078,7 +415064,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411102,7 +415088,7 @@ module \ti assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411123,7 +415109,7 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign { } { } assign { } { } @@ -411136,37 +415122,45 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\new_svstate_dststep[6:0] \cur_cur_dststep + assign { } { } assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl assign { } { } assign $4\new_svstate_subvl[1:0] \cur_cur_subvl assign $4\new_svstate_svstep[1:0] \cur_cur_svstep assign $4\new_svstate_vl[6:0] \cur_cur_vl + assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign { } { } + assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case 2'1- + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case + assign { } { } assign { } { } assign $6\new_svstate_srcstep[6:0] \next_srcstep + assign $6\new_svstate_dststep[6:0] \next_dststep end case + assign $5\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep end attribute \src "libresoc.v:0.0-0.0" @@ -411177,13 +415171,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] + assign $4\new_svstate_dststep[6:0] $7\new_svstate_dststep[6:0] assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411193,9 +415187,9 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i + assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $7\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i case - assign $5\new_svstate_dststep[6:0] \cur_cur_dststep + assign $7\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $5\new_svstate_subvl[1:0] \cur_cur_subvl @@ -411219,25 +415213,25 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:197044.3-197059.6" - process $proc$libresoc.v:197044$13817 + attribute \src "libresoc.v:199334.3-199349.6" + process $proc$libresoc.v:199334$14000 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:197045.5-197045.29" + attribute \src "libresoc.v:199335.5-199335.29" switch \initial - attribute \src "libresoc.v:197045.9-197045.17" + attribute \src "libresoc.v:199335.9-199335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -411251,154 +415245,180 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:197060.3-197140.6" - process $proc$libresoc.v:197060$13818 + attribute \src "libresoc.v:199350.3-199448.6" + process $proc$libresoc.v:199350$14001 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$13819 $10\issue_fsm_state$next[2:0]$13829 - attribute \src "libresoc.v:197061.5-197061.29" + assign $0\issue_fsm_state$next[2:0]$14002 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199351.5-199351.29" switch \initial - attribute \src "libresoc.v:197061.9-197061.17" + attribute \src "libresoc.v:199351.9-199351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $2\issue_fsm_state$next[2:0]$13821 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$134 + assign $1\issue_fsm_state$next[2:0]$14003 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$13821 $3\issue_fsm_state$next[2:0]$13822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + assign $2\issue_fsm_state$next[2:0]$14004 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$13822 3'001 + assign $3\issue_fsm_state$next[2:0]$14005 3'001 case - assign $3\issue_fsm_state$next[2:0]$13822 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$14005 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$13821 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$14004 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $4\issue_fsm_state$next[2:0]$13823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\issue_fsm_state$next[2:0]$14003 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$13823 $5\issue_fsm_state$next[2:0]$13824 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \$138 + assign $4\issue_fsm_state$next[2:0]$14006 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$13824 3'000 + assign $5\issue_fsm_state$next[2:0]$14007 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$13824 3'010 + assign $5\issue_fsm_state$next[2:0]$14007 3'010 end case - assign $4\issue_fsm_state$next[2:0]$13823 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$14006 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" + switch \pred_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\issue_fsm_state$next[2:0]$14008 3'100 + case + assign $6\issue_fsm_state$next[2:0]$14008 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" + switch \pred_mask_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\issue_fsm_state$next[2:0]$14009 3'010 + case + assign $7\issue_fsm_state$next[2:0]$14009 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $6\issue_fsm_state$next[2:0]$13825 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + assign $1\issue_fsm_state$next[2:0]$14003 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$13825 3'011 + assign $8\issue_fsm_state$next[2:0]$14010 3'101 case - assign $6\issue_fsm_state$next[2:0]$13825 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$14010 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $7\issue_fsm_state$next[2:0]$13826 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$144 + assign $1\issue_fsm_state$next[2:0]$14003 $9\issue_fsm_state$next[2:0]$14011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$150 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$13826 $8\issue_fsm_state$next[2:0]$13827 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + assign $9\issue_fsm_state$next[2:0]$14011 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$13827 $9\issue_fsm_state$next[2:0]$13828 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - switch { \$150 \$146 } + assign $10\issue_fsm_state$next[2:0]$14012 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$156 \$152 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'000 + assign $11\issue_fsm_state$next[2:0]$14013 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'000 + assign $11\issue_fsm_state$next[2:0]$14013 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'100 + assign $11\issue_fsm_state$next[2:0]$14013 3'110 end case - assign $8\issue_fsm_state$next[2:0]$13827 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$14012 \issue_fsm_state end case - assign $7\issue_fsm_state$next[2:0]$13826 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$14011 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 3'010 + assign $1\issue_fsm_state$next[2:0]$14003 3'010 case - assign $1\issue_fsm_state$next[2:0]$13820 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$14003 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$13829 3'000 + assign $12\issue_fsm_state$next[2:0]$14014 3'000 case - assign $10\issue_fsm_state$next[2:0]$13829 $1\issue_fsm_state$next[2:0]$13820 + assign $12\issue_fsm_state$next[2:0]$14014 $1\issue_fsm_state$next[2:0]$14003 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13819 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$14002 end - attribute \src "libresoc.v:197141.3-197171.6" - process $proc$libresoc.v:197141$13830 + attribute \src "libresoc.v:199449.3-199479.6" + process $proc$libresoc.v:199449$14015 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:197142.5-197142.29" + attribute \src "libresoc.v:199450.5-199450.29" switch \initial - attribute \src "libresoc.v:197142.9-197142.17" + attribute \src "libresoc.v:199450.9-199450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$162 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_stopped_i[0:0] 1'0 @@ -411408,11 +415428,11 @@ module \ti assign $2\core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\core_stopped_i[0:0] 1'0 @@ -411427,25 +415447,25 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:197172.3-197202.6" - process $proc$libresoc.v:197172$13831 + attribute \src "libresoc.v:199480.3-199510.6" + process $proc$libresoc.v:199480$14016 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:197173.5-197173.29" + attribute \src "libresoc.v:199481.5-199481.29" switch \initial - attribute \src "libresoc.v:197173.9-197173.17" + attribute \src "libresoc.v:199481.9-199481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$174 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dbg_core_stopped_i[0:0] 1'0 @@ -411455,11 +415475,11 @@ module \ti assign $2\dbg_core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$180 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\dbg_core_stopped_i[0:0] 1'0 @@ -411474,132 +415494,132 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:197203.3-197269.6" - process $proc$libresoc.v:197203$13832 + attribute \src "libresoc.v:199511.3-199577.6" + process $proc$libresoc.v:199511$14017 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13833 $9\pc_changed$next[0:0]$13842 - attribute \src "libresoc.v:197204.5-197204.29" + assign $0\pc_changed$next[0:0]$14018 $9\pc_changed$next[0:0]$14027 + attribute \src "libresoc.v:199512.5-199512.29" switch \initial - attribute \src "libresoc.v:197204.9-197204.17" + attribute \src "libresoc.v:199512.9-199512.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13834 $2\pc_changed$next[0:0]$13835 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$180 + assign $1\pc_changed$next[0:0]$14019 $2\pc_changed$next[0:0]$14020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$13835 \pc_changed + assign $2\pc_changed$next[0:0]$14020 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$13835 $3\pc_changed$next[0:0]$13836 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + assign $2\pc_changed$next[0:0]$14020 $3\pc_changed$next[0:0]$14021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13836 1'1 + assign $3\pc_changed$next[0:0]$14021 1'1 case - assign $3\pc_changed$next[0:0]$13836 \pc_changed + assign $3\pc_changed$next[0:0]$14021 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\pc_changed$next[0:0]$13834 $4\pc_changed$next[0:0]$13837 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$186 + assign $1\pc_changed$next[0:0]$14019 $4\pc_changed$next[0:0]$14022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$13837 \pc_changed + assign $4\pc_changed$next[0:0]$14022 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$13837 $5\pc_changed$next[0:0]$13838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + assign $4\pc_changed$next[0:0]$14022 $5\pc_changed$next[0:0]$14023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$13838 1'1 + assign $5\pc_changed$next[0:0]$14023 1'1 case - assign $5\pc_changed$next[0:0]$13838 \pc_changed + assign $5\pc_changed$next[0:0]$14023 \pc_changed end end case - assign $1\pc_changed$next[0:0]$13834 \pc_changed + assign $1\pc_changed$next[0:0]$14019 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$13839 $7\pc_changed$next[0:0]$13840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $6\pc_changed$next[0:0]$14024 $7\pc_changed$next[0:0]$14025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$13840 1'0 + assign $7\pc_changed$next[0:0]$14025 1'0 case - assign $7\pc_changed$next[0:0]$13840 $1\pc_changed$next[0:0]$13834 + assign $7\pc_changed$next[0:0]$14025 $1\pc_changed$next[0:0]$14019 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$13839 $8\pc_changed$next[0:0]$13841 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - switch \$188 + assign $6\pc_changed$next[0:0]$14024 $8\pc_changed$next[0:0]$14026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$13841 1'1 + assign $8\pc_changed$next[0:0]$14026 1'1 case - assign $8\pc_changed$next[0:0]$13841 $1\pc_changed$next[0:0]$13834 + assign $8\pc_changed$next[0:0]$14026 $1\pc_changed$next[0:0]$14019 end case - assign $6\pc_changed$next[0:0]$13839 $1\pc_changed$next[0:0]$13834 + assign $6\pc_changed$next[0:0]$14024 $1\pc_changed$next[0:0]$14019 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$13842 1'0 + assign $9\pc_changed$next[0:0]$14027 1'0 case - assign $9\pc_changed$next[0:0]$13842 $6\pc_changed$next[0:0]$13839 + assign $9\pc_changed$next[0:0]$14027 $6\pc_changed$next[0:0]$14024 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13833 + update \pc_changed$next $0\pc_changed$next[0:0]$14018 end - attribute \src "libresoc.v:197270.3-197326.6" - process $proc$libresoc.v:197270$13843 + attribute \src "libresoc.v:199578.3-199634.6" + process $proc$libresoc.v:199578$14028 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:197271.5-197271.29" + attribute \src "libresoc.v:199579.5-199579.29" switch \initial - attribute \src "libresoc.v:197271.9-197271.17" + attribute \src "libresoc.v:199579.9-199579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$202 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\update_svstate[0:0] 1'0 @@ -411607,7 +415627,7 @@ module \ti case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411618,23 +415638,23 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$208 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - switch { \$208 \$204 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$214 \$210 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\update_svstate[0:0] 1'0 @@ -411653,7 +415673,7 @@ module \ti case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411669,125 +415689,125 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:197327.3-197393.6" - process $proc$libresoc.v:197327$13844 + attribute \src "libresoc.v:199635.3-199701.6" + process $proc$libresoc.v:199635$14029 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$13845 $9\sv_changed$next[0:0]$13854 - attribute \src "libresoc.v:197328.5-197328.29" + assign $0\sv_changed$next[0:0]$14030 $9\sv_changed$next[0:0]$14039 + attribute \src "libresoc.v:199636.5-199636.29" switch \initial - attribute \src "libresoc.v:197328.9-197328.17" + attribute \src "libresoc.v:199636.9-199636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$13846 $2\sv_changed$next[0:0]$13847 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$214 + assign $1\sv_changed$next[0:0]$14031 $2\sv_changed$next[0:0]$14032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$13847 \sv_changed + assign $2\sv_changed$next[0:0]$14032 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$13847 $3\sv_changed$next[0:0]$13848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + assign $2\sv_changed$next[0:0]$14032 $3\sv_changed$next[0:0]$14033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$13848 1'1 + assign $3\sv_changed$next[0:0]$14033 1'1 case - assign $3\sv_changed$next[0:0]$13848 \sv_changed + assign $3\sv_changed$next[0:0]$14033 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\sv_changed$next[0:0]$13846 $4\sv_changed$next[0:0]$13849 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$220 + assign $1\sv_changed$next[0:0]$14031 $4\sv_changed$next[0:0]$14034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$13849 \sv_changed + assign $4\sv_changed$next[0:0]$14034 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$13849 $5\sv_changed$next[0:0]$13850 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + assign $4\sv_changed$next[0:0]$14034 $5\sv_changed$next[0:0]$14035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$13850 1'1 + assign $5\sv_changed$next[0:0]$14035 1'1 case - assign $5\sv_changed$next[0:0]$13850 \sv_changed + assign $5\sv_changed$next[0:0]$14035 \sv_changed end end case - assign $1\sv_changed$next[0:0]$13846 \sv_changed + assign $1\sv_changed$next[0:0]$14031 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$13851 $7\sv_changed$next[0:0]$13852 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $6\sv_changed$next[0:0]$14036 $7\sv_changed$next[0:0]$14037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$13852 1'0 + assign $7\sv_changed$next[0:0]$14037 1'0 case - assign $7\sv_changed$next[0:0]$13852 $1\sv_changed$next[0:0]$13846 + assign $7\sv_changed$next[0:0]$14037 $1\sv_changed$next[0:0]$14031 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$13851 $8\sv_changed$next[0:0]$13853 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - switch \$222 + assign $6\sv_changed$next[0:0]$14036 $8\sv_changed$next[0:0]$14038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$13853 1'1 + assign $8\sv_changed$next[0:0]$14038 1'1 case - assign $8\sv_changed$next[0:0]$13853 $1\sv_changed$next[0:0]$13846 + assign $8\sv_changed$next[0:0]$14038 $1\sv_changed$next[0:0]$14031 end case - assign $6\sv_changed$next[0:0]$13851 $1\sv_changed$next[0:0]$13846 + assign $6\sv_changed$next[0:0]$14036 $1\sv_changed$next[0:0]$14031 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$13854 1'0 + assign $9\sv_changed$next[0:0]$14039 1'0 case - assign $9\sv_changed$next[0:0]$13854 $6\sv_changed$next[0:0]$13851 + assign $9\sv_changed$next[0:0]$14039 $6\sv_changed$next[0:0]$14036 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$13845 + update \sv_changed$next $0\sv_changed$next[0:0]$14030 end - attribute \src "libresoc.v:197394.3-197404.6" - process $proc$libresoc.v:197394$13855 + attribute \src "libresoc.v:199702.3-199712.6" + process $proc$libresoc.v:199702$14040 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:197395.5-197395.29" + attribute \src "libresoc.v:199703.5-199703.29" switch \initial - attribute \src "libresoc.v:197395.9-197395.17" + attribute \src "libresoc.v:199703.9-199703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -411799,8 +415819,8 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:197405.3-197515.6" - process $proc$libresoc.v:197405$13856 + attribute \src "libresoc.v:199713.3-199823.6" + process $proc$libresoc.v:199713$14041 assign { } { } assign { } { } assign { } { } @@ -411919,11 +415939,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13857 $1\core_asmcode$next[7:0]$13916 - assign $0\core_core_core_cia$next[63:0]$13858 $1\core_core_core_cia$next[63:0]$13917 - assign $0\core_core_core_cr_rd$next[7:0]$13859 $1\core_core_core_cr_rd$next[7:0]$13918 + assign $0\core_asmcode$next[7:0]$14042 $1\core_asmcode$next[7:0]$14101 + assign $0\core_core_core_cia$next[63:0]$14043 $1\core_core_core_cia$next[63:0]$14102 + assign $0\core_core_core_cr_rd$next[7:0]$14044 $1\core_core_core_cr_rd$next[7:0]$14103 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13861 $1\core_core_core_cr_wr$next[7:0]$13920 + assign $0\core_core_core_cr_wr$next[7:0]$14046 $1\core_core_core_cr_wr$next[7:0]$14105 assign { } { } assign { } { } assign { } { } @@ -411932,86 +415952,86 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$13870 $1\core_core_core_fn_unit$next[13:0]$13929 - assign $0\core_core_core_input_carry$next[1:0]$13871 $1\core_core_core_input_carry$next[1:0]$13930 - assign $0\core_core_core_insn$next[31:0]$13872 $1\core_core_core_insn$next[31:0]$13931 - assign $0\core_core_core_insn_type$next[6:0]$13873 $1\core_core_core_insn_type$next[6:0]$13932 - assign $0\core_core_core_is_32bit$next[0:0]$13874 $1\core_core_core_is_32bit$next[0:0]$13933 - assign $0\core_core_core_msr$next[63:0]$13875 $1\core_core_core_msr$next[63:0]$13934 - assign $0\core_core_core_oe$next[0:0]$13876 $1\core_core_core_oe$next[0:0]$13935 + assign $0\core_core_core_fn_unit$next[13:0]$14055 $1\core_core_core_fn_unit$next[13:0]$14114 + assign $0\core_core_core_input_carry$next[1:0]$14056 $1\core_core_core_input_carry$next[1:0]$14115 + assign $0\core_core_core_insn$next[31:0]$14057 $1\core_core_core_insn$next[31:0]$14116 + assign $0\core_core_core_insn_type$next[6:0]$14058 $1\core_core_core_insn_type$next[6:0]$14117 + assign $0\core_core_core_is_32bit$next[0:0]$14059 $1\core_core_core_is_32bit$next[0:0]$14118 + assign $0\core_core_core_msr$next[63:0]$14060 $1\core_core_core_msr$next[63:0]$14119 + assign $0\core_core_core_oe$next[0:0]$14061 $1\core_core_core_oe$next[0:0]$14120 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13878 $1\core_core_core_rc$next[0:0]$13937 + assign $0\core_core_core_rc$next[0:0]$14063 $1\core_core_core_rc$next[0:0]$14122 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13880 $1\core_core_core_trapaddr$next[12:0]$13939 - assign $0\core_core_core_traptype$next[7:0]$13881 $1\core_core_core_traptype$next[7:0]$13940 - assign $0\core_core_cr_in1$next[6:0]$13882 $1\core_core_cr_in1$next[6:0]$13941 + assign $0\core_core_core_trapaddr$next[12:0]$14065 $1\core_core_core_trapaddr$next[12:0]$14124 + assign $0\core_core_core_traptype$next[7:0]$14066 $1\core_core_core_traptype$next[7:0]$14125 + assign $0\core_core_cr_in1$next[6:0]$14067 $1\core_core_cr_in1$next[6:0]$14126 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$13884 $1\core_core_cr_in2$1$next[6:0]$13943 - assign $0\core_core_cr_in2$next[6:0]$13885 $1\core_core_cr_in2$next[6:0]$13944 + assign $0\core_core_cr_in2$1$next[6:0]$14069 $1\core_core_cr_in2$1$next[6:0]$14128 + assign $0\core_core_cr_in2$next[6:0]$14070 $1\core_core_cr_in2$next[6:0]$14129 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$13888 $1\core_core_cr_out$next[6:0]$13947 + assign $0\core_core_cr_out$next[6:0]$14073 $1\core_core_cr_out$next[6:0]$14132 assign { } { } - assign $0\core_core_ea$next[6:0]$13890 $1\core_core_ea$next[6:0]$13949 - assign $0\core_core_fast1$next[2:0]$13891 $1\core_core_fast1$next[2:0]$13950 + assign $0\core_core_ea$next[6:0]$14075 $1\core_core_ea$next[6:0]$14134 + assign $0\core_core_fast1$next[2:0]$14076 $1\core_core_fast1$next[2:0]$14135 assign { } { } - assign $0\core_core_fast2$next[2:0]$13893 $1\core_core_fast2$next[2:0]$13952 + assign $0\core_core_fast2$next[2:0]$14078 $1\core_core_fast2$next[2:0]$14137 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13895 $1\core_core_fasto1$next[2:0]$13954 - assign $0\core_core_fasto2$next[2:0]$13896 $1\core_core_fasto2$next[2:0]$13955 - assign $0\core_core_lk$next[0:0]$13897 $1\core_core_lk$next[0:0]$13956 - assign $0\core_core_reg1$next[6:0]$13898 $1\core_core_reg1$next[6:0]$13957 + assign $0\core_core_fasto1$next[2:0]$14080 $1\core_core_fasto1$next[2:0]$14139 + assign $0\core_core_fasto2$next[2:0]$14081 $1\core_core_fasto2$next[2:0]$14140 + assign $0\core_core_lk$next[0:0]$14082 $1\core_core_lk$next[0:0]$14141 + assign $0\core_core_reg1$next[6:0]$14083 $1\core_core_reg1$next[6:0]$14142 assign { } { } - assign $0\core_core_reg2$next[6:0]$13900 $1\core_core_reg2$next[6:0]$13959 + assign $0\core_core_reg2$next[6:0]$14085 $1\core_core_reg2$next[6:0]$14144 assign { } { } - assign $0\core_core_reg3$next[6:0]$13902 $1\core_core_reg3$next[6:0]$13961 + assign $0\core_core_reg3$next[6:0]$14087 $1\core_core_reg3$next[6:0]$14146 assign { } { } - assign $0\core_core_rego$next[6:0]$13904 $1\core_core_rego$next[6:0]$13963 - assign $0\core_core_spr1$next[9:0]$13905 $1\core_core_spr1$next[9:0]$13964 + assign $0\core_core_rego$next[6:0]$14089 $1\core_core_rego$next[6:0]$14148 + assign $0\core_core_spr1$next[9:0]$14090 $1\core_core_spr1$next[9:0]$14149 assign { } { } - assign $0\core_core_spro$next[9:0]$13907 $1\core_core_spro$next[9:0]$13966 - assign $0\core_core_xer_in$next[2:0]$13908 $1\core_core_xer_in$next[2:0]$13967 + assign $0\core_core_spro$next[9:0]$14092 $1\core_core_spro$next[9:0]$14151 + assign $0\core_core_xer_in$next[2:0]$14093 $1\core_core_xer_in$next[2:0]$14152 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$13915 $1\core_xer_out$next[0:0]$13974 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13860 $3\core_core_core_cr_rd_ok$next[0:0]$14034 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13862 $3\core_core_core_exc_$signal$3$next[0:0]$14035 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13863 $3\core_core_core_exc_$signal$4$next[0:0]$14036 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13864 $3\core_core_core_exc_$signal$5$next[0:0]$14037 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13865 $3\core_core_core_exc_$signal$6$next[0:0]$14038 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13866 $3\core_core_core_exc_$signal$7$next[0:0]$14039 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13867 $3\core_core_core_exc_$signal$8$next[0:0]$14040 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13868 $3\core_core_core_exc_$signal$9$next[0:0]$14041 - assign $0\core_core_core_exc_$signal$next[0:0]$13869 $3\core_core_core_exc_$signal$next[0:0]$14042 - assign $0\core_core_core_oe_ok$next[0:0]$13877 $3\core_core_core_oe_ok$next[0:0]$14043 - assign $0\core_core_core_rc_ok$next[0:0]$13879 $3\core_core_core_rc_ok$next[0:0]$14044 - assign $0\core_core_cr_in1_ok$next[0:0]$13883 $3\core_core_cr_in1_ok$next[0:0]$14045 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13886 $3\core_core_cr_in2_ok$2$next[0:0]$14046 - assign $0\core_core_cr_in2_ok$next[0:0]$13887 $3\core_core_cr_in2_ok$next[0:0]$14047 - assign $0\core_core_cr_wr_ok$next[0:0]$13889 $3\core_core_cr_wr_ok$next[0:0]$14048 - assign $0\core_core_fast1_ok$next[0:0]$13892 $3\core_core_fast1_ok$next[0:0]$14049 - assign $0\core_core_fast2_ok$next[0:0]$13894 $3\core_core_fast2_ok$next[0:0]$14050 - assign $0\core_core_reg1_ok$next[0:0]$13899 $3\core_core_reg1_ok$next[0:0]$14051 - assign $0\core_core_reg2_ok$next[0:0]$13901 $3\core_core_reg2_ok$next[0:0]$14052 - assign $0\core_core_reg3_ok$next[0:0]$13903 $3\core_core_reg3_ok$next[0:0]$14053 - assign $0\core_core_spr1_ok$next[0:0]$13906 $3\core_core_spr1_ok$next[0:0]$14054 - assign $0\core_cr_out_ok$next[0:0]$13909 $3\core_cr_out_ok$next[0:0]$14055 - assign $0\core_ea_ok$next[0:0]$13910 $3\core_ea_ok$next[0:0]$14056 - assign $0\core_fasto1_ok$next[0:0]$13911 $3\core_fasto1_ok$next[0:0]$14057 - assign $0\core_fasto2_ok$next[0:0]$13912 $3\core_fasto2_ok$next[0:0]$14058 - assign $0\core_rego_ok$next[0:0]$13913 $3\core_rego_ok$next[0:0]$14059 - assign $0\core_spro_ok$next[0:0]$13914 $3\core_spro_ok$next[0:0]$14060 - attribute \src "libresoc.v:197406.5-197406.29" + assign $0\core_xer_out$next[0:0]$14100 $1\core_xer_out$next[0:0]$14159 + assign $0\core_core_core_cr_rd_ok$next[0:0]$14045 $3\core_core_core_cr_rd_ok$next[0:0]$14219 + assign $0\core_core_core_exc_$signal$3$next[0:0]$14047 $3\core_core_core_exc_$signal$3$next[0:0]$14220 + assign $0\core_core_core_exc_$signal$4$next[0:0]$14048 $3\core_core_core_exc_$signal$4$next[0:0]$14221 + assign $0\core_core_core_exc_$signal$5$next[0:0]$14049 $3\core_core_core_exc_$signal$5$next[0:0]$14222 + assign $0\core_core_core_exc_$signal$6$next[0:0]$14050 $3\core_core_core_exc_$signal$6$next[0:0]$14223 + assign $0\core_core_core_exc_$signal$7$next[0:0]$14051 $3\core_core_core_exc_$signal$7$next[0:0]$14224 + assign $0\core_core_core_exc_$signal$8$next[0:0]$14052 $3\core_core_core_exc_$signal$8$next[0:0]$14225 + assign $0\core_core_core_exc_$signal$9$next[0:0]$14053 $3\core_core_core_exc_$signal$9$next[0:0]$14226 + assign $0\core_core_core_exc_$signal$next[0:0]$14054 $3\core_core_core_exc_$signal$next[0:0]$14227 + assign $0\core_core_core_oe_ok$next[0:0]$14062 $3\core_core_core_oe_ok$next[0:0]$14228 + assign $0\core_core_core_rc_ok$next[0:0]$14064 $3\core_core_core_rc_ok$next[0:0]$14229 + assign $0\core_core_cr_in1_ok$next[0:0]$14068 $3\core_core_cr_in1_ok$next[0:0]$14230 + assign $0\core_core_cr_in2_ok$2$next[0:0]$14071 $3\core_core_cr_in2_ok$2$next[0:0]$14231 + assign $0\core_core_cr_in2_ok$next[0:0]$14072 $3\core_core_cr_in2_ok$next[0:0]$14232 + assign $0\core_core_cr_wr_ok$next[0:0]$14074 $3\core_core_cr_wr_ok$next[0:0]$14233 + assign $0\core_core_fast1_ok$next[0:0]$14077 $3\core_core_fast1_ok$next[0:0]$14234 + assign $0\core_core_fast2_ok$next[0:0]$14079 $3\core_core_fast2_ok$next[0:0]$14235 + assign $0\core_core_reg1_ok$next[0:0]$14084 $3\core_core_reg1_ok$next[0:0]$14236 + assign $0\core_core_reg2_ok$next[0:0]$14086 $3\core_core_reg2_ok$next[0:0]$14237 + assign $0\core_core_reg3_ok$next[0:0]$14088 $3\core_core_reg3_ok$next[0:0]$14238 + assign $0\core_core_spr1_ok$next[0:0]$14091 $3\core_core_spr1_ok$next[0:0]$14239 + assign $0\core_cr_out_ok$next[0:0]$14094 $3\core_cr_out_ok$next[0:0]$14240 + assign $0\core_ea_ok$next[0:0]$14095 $3\core_ea_ok$next[0:0]$14241 + assign $0\core_fasto1_ok$next[0:0]$14096 $3\core_fasto1_ok$next[0:0]$14242 + assign $0\core_fasto2_ok$next[0:0]$14097 $3\core_fasto2_ok$next[0:0]$14243 + assign $0\core_rego_ok$next[0:0]$14098 $3\core_rego_ok$next[0:0]$14244 + assign $0\core_spro_ok$next[0:0]$14099 $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199714.5-199714.29" switch \initial - attribute \src "libresoc.v:197406.9-197406.17" + attribute \src "libresoc.v:199714.9-199714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -412074,66 +416094,66 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13916 $2\core_asmcode$next[7:0]$13975 - assign $1\core_core_core_cia$next[63:0]$13917 $2\core_core_core_cia$next[63:0]$13976 - assign $1\core_core_core_cr_rd$next[7:0]$13918 $2\core_core_core_cr_rd$next[7:0]$13977 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 $2\core_core_core_cr_rd_ok$next[0:0]$13978 - assign $1\core_core_core_cr_wr$next[7:0]$13920 $2\core_core_core_cr_wr$next[7:0]$13979 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 $2\core_core_core_exc_$signal$3$next[0:0]$13980 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 $2\core_core_core_exc_$signal$4$next[0:0]$13981 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 $2\core_core_core_exc_$signal$5$next[0:0]$13982 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 $2\core_core_core_exc_$signal$6$next[0:0]$13983 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 $2\core_core_core_exc_$signal$7$next[0:0]$13984 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 $2\core_core_core_exc_$signal$8$next[0:0]$13985 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 $2\core_core_core_exc_$signal$9$next[0:0]$13986 - assign $1\core_core_core_exc_$signal$next[0:0]$13928 $2\core_core_core_exc_$signal$next[0:0]$13987 - assign $1\core_core_core_fn_unit$next[13:0]$13929 $2\core_core_core_fn_unit$next[13:0]$13988 - assign $1\core_core_core_input_carry$next[1:0]$13930 $2\core_core_core_input_carry$next[1:0]$13989 - assign $1\core_core_core_insn$next[31:0]$13931 $2\core_core_core_insn$next[31:0]$13990 - assign $1\core_core_core_insn_type$next[6:0]$13932 $2\core_core_core_insn_type$next[6:0]$13991 - assign $1\core_core_core_is_32bit$next[0:0]$13933 $2\core_core_core_is_32bit$next[0:0]$13992 - assign $1\core_core_core_msr$next[63:0]$13934 $2\core_core_core_msr$next[63:0]$13993 - assign $1\core_core_core_oe$next[0:0]$13935 $2\core_core_core_oe$next[0:0]$13994 - assign $1\core_core_core_oe_ok$next[0:0]$13936 $2\core_core_core_oe_ok$next[0:0]$13995 - assign $1\core_core_core_rc$next[0:0]$13937 $2\core_core_core_rc$next[0:0]$13996 - assign $1\core_core_core_rc_ok$next[0:0]$13938 $2\core_core_core_rc_ok$next[0:0]$13997 - assign $1\core_core_core_trapaddr$next[12:0]$13939 $2\core_core_core_trapaddr$next[12:0]$13998 - assign $1\core_core_core_traptype$next[7:0]$13940 $2\core_core_core_traptype$next[7:0]$13999 - assign $1\core_core_cr_in1$next[6:0]$13941 $2\core_core_cr_in1$next[6:0]$14000 - assign $1\core_core_cr_in1_ok$next[0:0]$13942 $2\core_core_cr_in1_ok$next[0:0]$14001 - assign $1\core_core_cr_in2$1$next[6:0]$13943 $2\core_core_cr_in2$1$next[6:0]$14002 - assign $1\core_core_cr_in2$next[6:0]$13944 $2\core_core_cr_in2$next[6:0]$14003 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 $2\core_core_cr_in2_ok$2$next[0:0]$14004 - assign $1\core_core_cr_in2_ok$next[0:0]$13946 $2\core_core_cr_in2_ok$next[0:0]$14005 - assign $1\core_core_cr_out$next[6:0]$13947 $2\core_core_cr_out$next[6:0]$14006 - assign $1\core_core_cr_wr_ok$next[0:0]$13948 $2\core_core_cr_wr_ok$next[0:0]$14007 - assign $1\core_core_ea$next[6:0]$13949 $2\core_core_ea$next[6:0]$14008 - assign $1\core_core_fast1$next[2:0]$13950 $2\core_core_fast1$next[2:0]$14009 - assign $1\core_core_fast1_ok$next[0:0]$13951 $2\core_core_fast1_ok$next[0:0]$14010 - assign $1\core_core_fast2$next[2:0]$13952 $2\core_core_fast2$next[2:0]$14011 - assign $1\core_core_fast2_ok$next[0:0]$13953 $2\core_core_fast2_ok$next[0:0]$14012 - assign $1\core_core_fasto1$next[2:0]$13954 $2\core_core_fasto1$next[2:0]$14013 - assign $1\core_core_fasto2$next[2:0]$13955 $2\core_core_fasto2$next[2:0]$14014 - assign $1\core_core_lk$next[0:0]$13956 $2\core_core_lk$next[0:0]$14015 - assign $1\core_core_reg1$next[6:0]$13957 $2\core_core_reg1$next[6:0]$14016 - assign $1\core_core_reg1_ok$next[0:0]$13958 $2\core_core_reg1_ok$next[0:0]$14017 - assign $1\core_core_reg2$next[6:0]$13959 $2\core_core_reg2$next[6:0]$14018 - assign $1\core_core_reg2_ok$next[0:0]$13960 $2\core_core_reg2_ok$next[0:0]$14019 - assign $1\core_core_reg3$next[6:0]$13961 $2\core_core_reg3$next[6:0]$14020 - assign $1\core_core_reg3_ok$next[0:0]$13962 $2\core_core_reg3_ok$next[0:0]$14021 - assign $1\core_core_rego$next[6:0]$13963 $2\core_core_rego$next[6:0]$14022 - assign $1\core_core_spr1$next[9:0]$13964 $2\core_core_spr1$next[9:0]$14023 - assign $1\core_core_spr1_ok$next[0:0]$13965 $2\core_core_spr1_ok$next[0:0]$14024 - assign $1\core_core_spro$next[9:0]$13966 $2\core_core_spro$next[9:0]$14025 - assign $1\core_core_xer_in$next[2:0]$13967 $2\core_core_xer_in$next[2:0]$14026 - assign $1\core_cr_out_ok$next[0:0]$13968 $2\core_cr_out_ok$next[0:0]$14027 - assign $1\core_ea_ok$next[0:0]$13969 $2\core_ea_ok$next[0:0]$14028 - assign $1\core_fasto1_ok$next[0:0]$13970 $2\core_fasto1_ok$next[0:0]$14029 - assign $1\core_fasto2_ok$next[0:0]$13971 $2\core_fasto2_ok$next[0:0]$14030 - assign $1\core_rego_ok$next[0:0]$13972 $2\core_rego_ok$next[0:0]$14031 - assign $1\core_spro_ok$next[0:0]$13973 $2\core_spro_ok$next[0:0]$14032 - assign $1\core_xer_out$next[0:0]$13974 $2\core_xer_out$next[0:0]$14033 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_asmcode$next[7:0]$14101 $2\core_asmcode$next[7:0]$14160 + assign $1\core_core_core_cia$next[63:0]$14102 $2\core_core_core_cia$next[63:0]$14161 + assign $1\core_core_core_cr_rd$next[7:0]$14103 $2\core_core_core_cr_rd$next[7:0]$14162 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 $2\core_core_core_cr_rd_ok$next[0:0]$14163 + assign $1\core_core_core_cr_wr$next[7:0]$14105 $2\core_core_core_cr_wr$next[7:0]$14164 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 $2\core_core_core_exc_$signal$3$next[0:0]$14165 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 $2\core_core_core_exc_$signal$4$next[0:0]$14166 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 $2\core_core_core_exc_$signal$5$next[0:0]$14167 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 $2\core_core_core_exc_$signal$6$next[0:0]$14168 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 $2\core_core_core_exc_$signal$7$next[0:0]$14169 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 $2\core_core_core_exc_$signal$8$next[0:0]$14170 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 $2\core_core_core_exc_$signal$9$next[0:0]$14171 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 $2\core_core_core_exc_$signal$next[0:0]$14172 + assign $1\core_core_core_fn_unit$next[13:0]$14114 $2\core_core_core_fn_unit$next[13:0]$14173 + assign $1\core_core_core_input_carry$next[1:0]$14115 $2\core_core_core_input_carry$next[1:0]$14174 + assign $1\core_core_core_insn$next[31:0]$14116 $2\core_core_core_insn$next[31:0]$14175 + assign $1\core_core_core_insn_type$next[6:0]$14117 $2\core_core_core_insn_type$next[6:0]$14176 + assign $1\core_core_core_is_32bit$next[0:0]$14118 $2\core_core_core_is_32bit$next[0:0]$14177 + assign $1\core_core_core_msr$next[63:0]$14119 $2\core_core_core_msr$next[63:0]$14178 + assign $1\core_core_core_oe$next[0:0]$14120 $2\core_core_core_oe$next[0:0]$14179 + assign $1\core_core_core_oe_ok$next[0:0]$14121 $2\core_core_core_oe_ok$next[0:0]$14180 + assign $1\core_core_core_rc$next[0:0]$14122 $2\core_core_core_rc$next[0:0]$14181 + assign $1\core_core_core_rc_ok$next[0:0]$14123 $2\core_core_core_rc_ok$next[0:0]$14182 + assign $1\core_core_core_trapaddr$next[12:0]$14124 $2\core_core_core_trapaddr$next[12:0]$14183 + assign $1\core_core_core_traptype$next[7:0]$14125 $2\core_core_core_traptype$next[7:0]$14184 + assign $1\core_core_cr_in1$next[6:0]$14126 $2\core_core_cr_in1$next[6:0]$14185 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 $2\core_core_cr_in1_ok$next[0:0]$14186 + assign $1\core_core_cr_in2$1$next[6:0]$14128 $2\core_core_cr_in2$1$next[6:0]$14187 + assign $1\core_core_cr_in2$next[6:0]$14129 $2\core_core_cr_in2$next[6:0]$14188 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 $2\core_core_cr_in2_ok$2$next[0:0]$14189 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 $2\core_core_cr_in2_ok$next[0:0]$14190 + assign $1\core_core_cr_out$next[6:0]$14132 $2\core_core_cr_out$next[6:0]$14191 + assign $1\core_core_cr_wr_ok$next[0:0]$14133 $2\core_core_cr_wr_ok$next[0:0]$14192 + assign $1\core_core_ea$next[6:0]$14134 $2\core_core_ea$next[6:0]$14193 + assign $1\core_core_fast1$next[2:0]$14135 $2\core_core_fast1$next[2:0]$14194 + assign $1\core_core_fast1_ok$next[0:0]$14136 $2\core_core_fast1_ok$next[0:0]$14195 + assign $1\core_core_fast2$next[2:0]$14137 $2\core_core_fast2$next[2:0]$14196 + assign $1\core_core_fast2_ok$next[0:0]$14138 $2\core_core_fast2_ok$next[0:0]$14197 + assign $1\core_core_fasto1$next[2:0]$14139 $2\core_core_fasto1$next[2:0]$14198 + assign $1\core_core_fasto2$next[2:0]$14140 $2\core_core_fasto2$next[2:0]$14199 + assign $1\core_core_lk$next[0:0]$14141 $2\core_core_lk$next[0:0]$14200 + assign $1\core_core_reg1$next[6:0]$14142 $2\core_core_reg1$next[6:0]$14201 + assign $1\core_core_reg1_ok$next[0:0]$14143 $2\core_core_reg1_ok$next[0:0]$14202 + assign $1\core_core_reg2$next[6:0]$14144 $2\core_core_reg2$next[6:0]$14203 + assign $1\core_core_reg2_ok$next[0:0]$14145 $2\core_core_reg2_ok$next[0:0]$14204 + assign $1\core_core_reg3$next[6:0]$14146 $2\core_core_reg3$next[6:0]$14205 + assign $1\core_core_reg3_ok$next[0:0]$14147 $2\core_core_reg3_ok$next[0:0]$14206 + assign $1\core_core_rego$next[6:0]$14148 $2\core_core_rego$next[6:0]$14207 + assign $1\core_core_spr1$next[9:0]$14149 $2\core_core_spr1$next[9:0]$14208 + assign $1\core_core_spr1_ok$next[0:0]$14150 $2\core_core_spr1_ok$next[0:0]$14209 + assign $1\core_core_spro$next[9:0]$14151 $2\core_core_spro$next[9:0]$14210 + assign $1\core_core_xer_in$next[2:0]$14152 $2\core_core_xer_in$next[2:0]$14211 + assign $1\core_cr_out_ok$next[0:0]$14153 $2\core_cr_out_ok$next[0:0]$14212 + assign $1\core_ea_ok$next[0:0]$14154 $2\core_ea_ok$next[0:0]$14213 + assign $1\core_fasto1_ok$next[0:0]$14155 $2\core_fasto1_ok$next[0:0]$14214 + assign $1\core_fasto2_ok$next[0:0]$14156 $2\core_fasto2_ok$next[0:0]$14215 + assign $1\core_rego_ok$next[0:0]$14157 $2\core_rego_ok$next[0:0]$14216 + assign $1\core_spro_ok$next[0:0]$14158 $2\core_spro_ok$next[0:0]$14217 + assign $1\core_xer_out$next[0:0]$14159 $2\core_xer_out$next[0:0]$14218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -412196,70 +416216,70 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13992 $2\core_core_cr_wr_ok$next[0:0]$14007 $2\core_core_core_cr_wr$next[7:0]$13979 $2\core_core_core_cr_rd_ok$next[0:0]$13978 $2\core_core_core_cr_rd$next[7:0]$13977 $2\core_core_core_trapaddr$next[12:0]$13998 $2\core_core_core_exc_$signal$9$next[0:0]$13986 $2\core_core_core_exc_$signal$8$next[0:0]$13985 $2\core_core_core_exc_$signal$7$next[0:0]$13984 $2\core_core_core_exc_$signal$6$next[0:0]$13983 $2\core_core_core_exc_$signal$5$next[0:0]$13982 $2\core_core_core_exc_$signal$4$next[0:0]$13981 $2\core_core_core_exc_$signal$3$next[0:0]$13980 $2\core_core_core_exc_$signal$next[0:0]$13987 $2\core_core_core_traptype$next[7:0]$13999 $2\core_core_core_input_carry$next[1:0]$13989 $2\core_core_core_oe_ok$next[0:0]$13995 $2\core_core_core_oe$next[0:0]$13994 $2\core_core_core_rc_ok$next[0:0]$13997 $2\core_core_core_rc$next[0:0]$13996 $2\core_core_lk$next[0:0]$14015 $2\core_core_core_fn_unit$next[13:0]$13988 $2\core_core_core_insn_type$next[6:0]$13991 $2\core_core_core_insn$next[31:0]$13990 $2\core_core_core_cia$next[63:0]$13976 $2\core_core_core_msr$next[63:0]$13993 $2\core_cr_out_ok$next[0:0]$14027 $2\core_core_cr_out$next[6:0]$14006 $2\core_core_cr_in2_ok$2$next[0:0]$14004 $2\core_core_cr_in2$1$next[6:0]$14002 $2\core_core_cr_in2_ok$next[0:0]$14005 $2\core_core_cr_in2$next[6:0]$14003 $2\core_core_cr_in1_ok$next[0:0]$14001 $2\core_core_cr_in1$next[6:0]$14000 $2\core_fasto2_ok$next[0:0]$14030 $2\core_core_fasto2$next[2:0]$14014 $2\core_fasto1_ok$next[0:0]$14029 $2\core_core_fasto1$next[2:0]$14013 $2\core_core_fast2_ok$next[0:0]$14012 $2\core_core_fast2$next[2:0]$14011 $2\core_core_fast1_ok$next[0:0]$14010 $2\core_core_fast1$next[2:0]$14009 $2\core_xer_out$next[0:0]$14033 $2\core_core_xer_in$next[2:0]$14026 $2\core_core_spr1_ok$next[0:0]$14024 $2\core_core_spr1$next[9:0]$14023 $2\core_spro_ok$next[0:0]$14032 $2\core_core_spro$next[9:0]$14025 $2\core_core_reg3_ok$next[0:0]$14021 $2\core_core_reg3$next[6:0]$14020 $2\core_core_reg2_ok$next[0:0]$14019 $2\core_core_reg2$next[6:0]$14018 $2\core_core_reg1_ok$next[0:0]$14017 $2\core_core_reg1$next[6:0]$14016 $2\core_ea_ok$next[0:0]$14028 $2\core_core_ea$next[6:0]$14008 $2\core_rego_ok$next[0:0]$14031 $2\core_core_rego$next[6:0]$14022 $2\core_asmcode$next[7:0]$13975 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$14177 $2\core_core_cr_wr_ok$next[0:0]$14192 $2\core_core_core_cr_wr$next[7:0]$14164 $2\core_core_core_cr_rd_ok$next[0:0]$14163 $2\core_core_core_cr_rd$next[7:0]$14162 $2\core_core_core_trapaddr$next[12:0]$14183 $2\core_core_core_exc_$signal$9$next[0:0]$14171 $2\core_core_core_exc_$signal$8$next[0:0]$14170 $2\core_core_core_exc_$signal$7$next[0:0]$14169 $2\core_core_core_exc_$signal$6$next[0:0]$14168 $2\core_core_core_exc_$signal$5$next[0:0]$14167 $2\core_core_core_exc_$signal$4$next[0:0]$14166 $2\core_core_core_exc_$signal$3$next[0:0]$14165 $2\core_core_core_exc_$signal$next[0:0]$14172 $2\core_core_core_traptype$next[7:0]$14184 $2\core_core_core_input_carry$next[1:0]$14174 $2\core_core_core_oe_ok$next[0:0]$14180 $2\core_core_core_oe$next[0:0]$14179 $2\core_core_core_rc_ok$next[0:0]$14182 $2\core_core_core_rc$next[0:0]$14181 $2\core_core_lk$next[0:0]$14200 $2\core_core_core_fn_unit$next[13:0]$14173 $2\core_core_core_insn_type$next[6:0]$14176 $2\core_core_core_insn$next[31:0]$14175 $2\core_core_core_cia$next[63:0]$14161 $2\core_core_core_msr$next[63:0]$14178 $2\core_cr_out_ok$next[0:0]$14212 $2\core_core_cr_out$next[6:0]$14191 $2\core_core_cr_in2_ok$2$next[0:0]$14189 $2\core_core_cr_in2$1$next[6:0]$14187 $2\core_core_cr_in2_ok$next[0:0]$14190 $2\core_core_cr_in2$next[6:0]$14188 $2\core_core_cr_in1_ok$next[0:0]$14186 $2\core_core_cr_in1$next[6:0]$14185 $2\core_fasto2_ok$next[0:0]$14215 $2\core_core_fasto2$next[2:0]$14199 $2\core_fasto1_ok$next[0:0]$14214 $2\core_core_fasto1$next[2:0]$14198 $2\core_core_fast2_ok$next[0:0]$14197 $2\core_core_fast2$next[2:0]$14196 $2\core_core_fast1_ok$next[0:0]$14195 $2\core_core_fast1$next[2:0]$14194 $2\core_xer_out$next[0:0]$14218 $2\core_core_xer_in$next[2:0]$14211 $2\core_core_spr1_ok$next[0:0]$14209 $2\core_core_spr1$next[9:0]$14208 $2\core_spro_ok$next[0:0]$14217 $2\core_core_spro$next[9:0]$14210 $2\core_core_reg3_ok$next[0:0]$14206 $2\core_core_reg3$next[6:0]$14205 $2\core_core_reg2_ok$next[0:0]$14204 $2\core_core_reg2$next[6:0]$14203 $2\core_core_reg1_ok$next[0:0]$14202 $2\core_core_reg1$next[6:0]$14201 $2\core_ea_ok$next[0:0]$14213 $2\core_core_ea$next[6:0]$14193 $2\core_rego_ok$next[0:0]$14216 $2\core_core_rego$next[6:0]$14207 $2\core_asmcode$next[7:0]$14160 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$13975 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13976 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13977 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13978 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13979 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13980 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13981 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13982 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13983 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13984 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13985 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13986 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13987 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$13988 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13989 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13990 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13991 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13992 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13993 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13994 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13995 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13996 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13997 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13998 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13999 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14000 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14001 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14002 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14003 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14004 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14005 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14006 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14007 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14008 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14009 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14010 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14011 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14012 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14013 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14014 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14015 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14016 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14017 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14018 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14019 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14020 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14021 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14022 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14023 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14024 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14025 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14026 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14027 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14028 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14029 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14030 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14031 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14032 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14033 \core_xer_out + assign $2\core_asmcode$next[7:0]$14160 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14161 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14162 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14163 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14164 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14165 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14166 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14167 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14168 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14169 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14170 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14171 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14172 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$14173 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14174 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14175 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14176 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14177 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14178 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14179 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14180 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14181 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14182 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14183 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14184 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14185 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14186 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14187 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14188 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14189 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14190 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14191 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14192 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14193 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14194 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14195 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14196 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14197 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14198 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14199 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14200 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14201 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14202 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14203 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14204 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14205 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14206 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14207 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14208 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14209 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14210 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14211 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14212 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14213 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14214 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14215 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14216 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14217 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14218 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } assign { } { } assign { } { } @@ -412319,67 +416339,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13933 $1\core_core_cr_wr_ok$next[0:0]$13948 $1\core_core_core_cr_wr$next[7:0]$13920 $1\core_core_core_cr_rd_ok$next[0:0]$13919 $1\core_core_core_cr_rd$next[7:0]$13918 $1\core_core_core_trapaddr$next[12:0]$13939 $1\core_core_core_exc_$signal$9$next[0:0]$13927 $1\core_core_core_exc_$signal$8$next[0:0]$13926 $1\core_core_core_exc_$signal$7$next[0:0]$13925 $1\core_core_core_exc_$signal$6$next[0:0]$13924 $1\core_core_core_exc_$signal$5$next[0:0]$13923 $1\core_core_core_exc_$signal$4$next[0:0]$13922 $1\core_core_core_exc_$signal$3$next[0:0]$13921 $1\core_core_core_exc_$signal$next[0:0]$13928 $1\core_core_core_traptype$next[7:0]$13940 $1\core_core_core_input_carry$next[1:0]$13930 $1\core_core_core_oe_ok$next[0:0]$13936 $1\core_core_core_oe$next[0:0]$13935 $1\core_core_core_rc_ok$next[0:0]$13938 $1\core_core_core_rc$next[0:0]$13937 $1\core_core_lk$next[0:0]$13956 $1\core_core_core_fn_unit$next[13:0]$13929 $1\core_core_core_insn_type$next[6:0]$13932 $1\core_core_core_insn$next[31:0]$13931 $1\core_core_core_cia$next[63:0]$13917 $1\core_core_core_msr$next[63:0]$13934 $1\core_cr_out_ok$next[0:0]$13968 $1\core_core_cr_out$next[6:0]$13947 $1\core_core_cr_in2_ok$2$next[0:0]$13945 $1\core_core_cr_in2$1$next[6:0]$13943 $1\core_core_cr_in2_ok$next[0:0]$13946 $1\core_core_cr_in2$next[6:0]$13944 $1\core_core_cr_in1_ok$next[0:0]$13942 $1\core_core_cr_in1$next[6:0]$13941 $1\core_fasto2_ok$next[0:0]$13971 $1\core_core_fasto2$next[2:0]$13955 $1\core_fasto1_ok$next[0:0]$13970 $1\core_core_fasto1$next[2:0]$13954 $1\core_core_fast2_ok$next[0:0]$13953 $1\core_core_fast2$next[2:0]$13952 $1\core_core_fast1_ok$next[0:0]$13951 $1\core_core_fast1$next[2:0]$13950 $1\core_xer_out$next[0:0]$13974 $1\core_core_xer_in$next[2:0]$13967 $1\core_core_spr1_ok$next[0:0]$13965 $1\core_core_spr1$next[9:0]$13964 $1\core_spro_ok$next[0:0]$13973 $1\core_core_spro$next[9:0]$13966 $1\core_core_reg3_ok$next[0:0]$13962 $1\core_core_reg3$next[6:0]$13961 $1\core_core_reg2_ok$next[0:0]$13960 $1\core_core_reg2$next[6:0]$13959 $1\core_core_reg1_ok$next[0:0]$13958 $1\core_core_reg1$next[6:0]$13957 $1\core_ea_ok$next[0:0]$13969 $1\core_core_ea$next[6:0]$13949 $1\core_rego_ok$next[0:0]$13972 $1\core_core_rego$next[6:0]$13963 $1\core_asmcode$next[7:0]$13916 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$14118 $1\core_core_cr_wr_ok$next[0:0]$14133 $1\core_core_core_cr_wr$next[7:0]$14105 $1\core_core_core_cr_rd_ok$next[0:0]$14104 $1\core_core_core_cr_rd$next[7:0]$14103 $1\core_core_core_trapaddr$next[12:0]$14124 $1\core_core_core_exc_$signal$9$next[0:0]$14112 $1\core_core_core_exc_$signal$8$next[0:0]$14111 $1\core_core_core_exc_$signal$7$next[0:0]$14110 $1\core_core_core_exc_$signal$6$next[0:0]$14109 $1\core_core_core_exc_$signal$5$next[0:0]$14108 $1\core_core_core_exc_$signal$4$next[0:0]$14107 $1\core_core_core_exc_$signal$3$next[0:0]$14106 $1\core_core_core_exc_$signal$next[0:0]$14113 $1\core_core_core_traptype$next[7:0]$14125 $1\core_core_core_input_carry$next[1:0]$14115 $1\core_core_core_oe_ok$next[0:0]$14121 $1\core_core_core_oe$next[0:0]$14120 $1\core_core_core_rc_ok$next[0:0]$14123 $1\core_core_core_rc$next[0:0]$14122 $1\core_core_lk$next[0:0]$14141 $1\core_core_core_fn_unit$next[13:0]$14114 $1\core_core_core_insn_type$next[6:0]$14117 $1\core_core_core_insn$next[31:0]$14116 $1\core_core_core_cia$next[63:0]$14102 $1\core_core_core_msr$next[63:0]$14119 $1\core_cr_out_ok$next[0:0]$14153 $1\core_core_cr_out$next[6:0]$14132 $1\core_core_cr_in2_ok$2$next[0:0]$14130 $1\core_core_cr_in2$1$next[6:0]$14128 $1\core_core_cr_in2_ok$next[0:0]$14131 $1\core_core_cr_in2$next[6:0]$14129 $1\core_core_cr_in1_ok$next[0:0]$14127 $1\core_core_cr_in1$next[6:0]$14126 $1\core_fasto2_ok$next[0:0]$14156 $1\core_core_fasto2$next[2:0]$14140 $1\core_fasto1_ok$next[0:0]$14155 $1\core_core_fasto1$next[2:0]$14139 $1\core_core_fast2_ok$next[0:0]$14138 $1\core_core_fast2$next[2:0]$14137 $1\core_core_fast1_ok$next[0:0]$14136 $1\core_core_fast1$next[2:0]$14135 $1\core_xer_out$next[0:0]$14159 $1\core_core_xer_in$next[2:0]$14152 $1\core_core_spr1_ok$next[0:0]$14150 $1\core_core_spr1$next[9:0]$14149 $1\core_spro_ok$next[0:0]$14158 $1\core_core_spro$next[9:0]$14151 $1\core_core_reg3_ok$next[0:0]$14147 $1\core_core_reg3$next[6:0]$14146 $1\core_core_reg2_ok$next[0:0]$14145 $1\core_core_reg2$next[6:0]$14144 $1\core_core_reg1_ok$next[0:0]$14143 $1\core_core_reg1$next[6:0]$14142 $1\core_ea_ok$next[0:0]$14154 $1\core_core_ea$next[6:0]$14134 $1\core_rego_ok$next[0:0]$14157 $1\core_core_rego$next[6:0]$14148 $1\core_asmcode$next[7:0]$14101 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$13916 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13917 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13918 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13920 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13928 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13929 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13930 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13931 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13932 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13933 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13934 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13935 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13936 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13937 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13938 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13939 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13940 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13941 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13942 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13943 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13944 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13946 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13947 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13948 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13949 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13950 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13951 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13952 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13953 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13954 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13955 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13956 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13957 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13958 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13959 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13960 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13961 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13962 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13963 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13964 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13965 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13966 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13967 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13968 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13969 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13970 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13971 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13972 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13973 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13974 \core_xer_out + assign $1\core_asmcode$next[7:0]$14101 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14102 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14103 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14105 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14114 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14115 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14116 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14117 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14118 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14119 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14120 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14121 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14122 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14123 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14124 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14125 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14126 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14128 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14129 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14132 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14133 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14134 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14135 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14136 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14137 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14138 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14139 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14140 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14141 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14142 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14143 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14144 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14145 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14146 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14147 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14148 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14149 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14150 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14151 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14152 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14153 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14154 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14155 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14156 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14157 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14158 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14159 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -412412,255 +416432,258 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$14059 1'0 - assign $3\core_ea_ok$next[0:0]$14056 1'0 - assign $3\core_core_reg1_ok$next[0:0]$14051 1'0 - assign $3\core_core_reg2_ok$next[0:0]$14052 1'0 - assign $3\core_core_reg3_ok$next[0:0]$14053 1'0 - assign $3\core_spro_ok$next[0:0]$14060 1'0 - assign $3\core_core_spr1_ok$next[0:0]$14054 1'0 - assign $3\core_core_fast1_ok$next[0:0]$14049 1'0 - assign $3\core_core_fast2_ok$next[0:0]$14050 1'0 - assign $3\core_fasto1_ok$next[0:0]$14057 1'0 - assign $3\core_fasto2_ok$next[0:0]$14058 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$14045 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$14047 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 1'0 - assign $3\core_cr_out_ok$next[0:0]$14055 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$14044 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$14043 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$14042 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$14048 1'0 - case - assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 $1\core_core_core_cr_rd_ok$next[0:0]$13919 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$13921 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$13922 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$13923 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$13924 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$13925 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$13926 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 $1\core_core_core_exc_$signal$9$next[0:0]$13927 - assign $3\core_core_core_exc_$signal$next[0:0]$14042 $1\core_core_core_exc_$signal$next[0:0]$13928 - assign $3\core_core_core_oe_ok$next[0:0]$14043 $1\core_core_core_oe_ok$next[0:0]$13936 - assign $3\core_core_core_rc_ok$next[0:0]$14044 $1\core_core_core_rc_ok$next[0:0]$13938 - assign $3\core_core_cr_in1_ok$next[0:0]$14045 $1\core_core_cr_in1_ok$next[0:0]$13942 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 $1\core_core_cr_in2_ok$2$next[0:0]$13945 - assign $3\core_core_cr_in2_ok$next[0:0]$14047 $1\core_core_cr_in2_ok$next[0:0]$13946 - assign $3\core_core_cr_wr_ok$next[0:0]$14048 $1\core_core_cr_wr_ok$next[0:0]$13948 - assign $3\core_core_fast1_ok$next[0:0]$14049 $1\core_core_fast1_ok$next[0:0]$13951 - assign $3\core_core_fast2_ok$next[0:0]$14050 $1\core_core_fast2_ok$next[0:0]$13953 - assign $3\core_core_reg1_ok$next[0:0]$14051 $1\core_core_reg1_ok$next[0:0]$13958 - assign $3\core_core_reg2_ok$next[0:0]$14052 $1\core_core_reg2_ok$next[0:0]$13960 - assign $3\core_core_reg3_ok$next[0:0]$14053 $1\core_core_reg3_ok$next[0:0]$13962 - assign $3\core_core_spr1_ok$next[0:0]$14054 $1\core_core_spr1_ok$next[0:0]$13965 - assign $3\core_cr_out_ok$next[0:0]$14055 $1\core_cr_out_ok$next[0:0]$13968 - assign $3\core_ea_ok$next[0:0]$14056 $1\core_ea_ok$next[0:0]$13969 - assign $3\core_fasto1_ok$next[0:0]$14057 $1\core_fasto1_ok$next[0:0]$13970 - assign $3\core_fasto2_ok$next[0:0]$14058 $1\core_fasto2_ok$next[0:0]$13971 - assign $3\core_rego_ok$next[0:0]$14059 $1\core_rego_ok$next[0:0]$13972 - assign $3\core_spro_ok$next[0:0]$14060 $1\core_spro_ok$next[0:0]$13973 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13857 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13858 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13859 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13860 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13861 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13862 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13863 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13864 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13865 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13866 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13867 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13868 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13869 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13870 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13871 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13872 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13873 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13874 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13875 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13876 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13877 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13878 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13879 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13880 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13881 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13882 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13883 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13884 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13885 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13886 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13887 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13888 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13889 - update \core_core_ea$next $0\core_core_ea$next[6:0]$13890 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13891 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13892 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13893 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13894 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13895 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13896 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13897 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13898 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13899 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13900 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13901 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13902 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13903 - update \core_core_rego$next $0\core_core_rego$next[6:0]$13904 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13905 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13906 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13907 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13908 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13909 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13910 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13911 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13912 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13913 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13914 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13915 - end - connect \$101 $add$libresoc.v:194791$13361_Y - connect \$103 $mul$libresoc.v:194792$13362_Y - connect \$99 $shr$libresoc.v:194793$13363_Y [31:0] - connect \$106 $not$libresoc.v:194794$13364_Y - connect \$108 $not$libresoc.v:194795$13365_Y - connect \$110 $and$libresoc.v:194796$13366_Y - connect \$112 $not$libresoc.v:194797$13367_Y - connect \$114 $not$libresoc.v:194798$13368_Y - connect \$116 $and$libresoc.v:194799$13369_Y - connect \$118 $or$libresoc.v:194800$13370_Y + assign $3\core_rego_ok$next[0:0]$14244 1'0 + assign $3\core_ea_ok$next[0:0]$14241 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14236 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14237 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14238 1'0 + assign $3\core_spro_ok$next[0:0]$14245 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14239 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14234 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14235 1'0 + assign $3\core_fasto1_ok$next[0:0]$14242 1'0 + assign $3\core_fasto2_ok$next[0:0]$14243 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 1'0 + assign $3\core_cr_out_ok$next[0:0]$14240 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14229 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14228 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 $1\core_core_core_cr_rd_ok$next[0:0]$14104 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 $1\core_core_core_exc_$signal$3$next[0:0]$14106 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 $1\core_core_core_exc_$signal$4$next[0:0]$14107 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 $1\core_core_core_exc_$signal$5$next[0:0]$14108 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 $1\core_core_core_exc_$signal$6$next[0:0]$14109 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 $1\core_core_core_exc_$signal$7$next[0:0]$14110 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 $1\core_core_core_exc_$signal$8$next[0:0]$14111 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 $1\core_core_core_exc_$signal$9$next[0:0]$14112 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 $1\core_core_core_exc_$signal$next[0:0]$14113 + assign $3\core_core_core_oe_ok$next[0:0]$14228 $1\core_core_core_oe_ok$next[0:0]$14121 + assign $3\core_core_core_rc_ok$next[0:0]$14229 $1\core_core_core_rc_ok$next[0:0]$14123 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 $1\core_core_cr_in1_ok$next[0:0]$14127 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 $1\core_core_cr_in2_ok$2$next[0:0]$14130 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 $1\core_core_cr_in2_ok$next[0:0]$14131 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 $1\core_core_cr_wr_ok$next[0:0]$14133 + assign $3\core_core_fast1_ok$next[0:0]$14234 $1\core_core_fast1_ok$next[0:0]$14136 + assign $3\core_core_fast2_ok$next[0:0]$14235 $1\core_core_fast2_ok$next[0:0]$14138 + assign $3\core_core_reg1_ok$next[0:0]$14236 $1\core_core_reg1_ok$next[0:0]$14143 + assign $3\core_core_reg2_ok$next[0:0]$14237 $1\core_core_reg2_ok$next[0:0]$14145 + assign $3\core_core_reg3_ok$next[0:0]$14238 $1\core_core_reg3_ok$next[0:0]$14147 + assign $3\core_core_spr1_ok$next[0:0]$14239 $1\core_core_spr1_ok$next[0:0]$14150 + assign $3\core_cr_out_ok$next[0:0]$14240 $1\core_cr_out_ok$next[0:0]$14153 + assign $3\core_ea_ok$next[0:0]$14241 $1\core_ea_ok$next[0:0]$14154 + assign $3\core_fasto1_ok$next[0:0]$14242 $1\core_fasto1_ok$next[0:0]$14155 + assign $3\core_fasto2_ok$next[0:0]$14243 $1\core_fasto2_ok$next[0:0]$14156 + assign $3\core_rego_ok$next[0:0]$14244 $1\core_rego_ok$next[0:0]$14157 + assign $3\core_spro_ok$next[0:0]$14245 $1\core_spro_ok$next[0:0]$14158 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$14042 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14043 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14044 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14045 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14046 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14047 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14048 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14049 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14050 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14051 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14052 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14053 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14054 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$14055 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14056 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14057 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14058 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14059 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14060 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14061 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14062 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14063 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14064 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14065 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14066 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14067 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14068 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14069 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14070 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14071 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14072 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14073 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14074 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14075 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14076 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14077 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14078 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14079 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14080 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14081 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14082 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14083 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14084 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14085 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14086 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14087 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14088 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14089 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14090 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14091 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14092 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14093 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14094 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14095 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14096 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14097 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14098 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14099 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14100 + end + connect \$101 $add$libresoc.v:197083$13545_Y + connect \$103 $mul$libresoc.v:197084$13546_Y + connect \$99 $shr$libresoc.v:197085$13547_Y [31:0] + connect \$106 $not$libresoc.v:197086$13548_Y + connect \$108 $not$libresoc.v:197087$13549_Y + connect \$110 $and$libresoc.v:197088$13550_Y + connect \$112 $not$libresoc.v:197089$13551_Y + connect \$114 $not$libresoc.v:197090$13552_Y + connect \$116 $and$libresoc.v:197091$13553_Y + connect \$118 $or$libresoc.v:197092$13554_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:194802$13371_Y - connect \$124 $not$libresoc.v:194803$13372_Y - connect \$126 $not$libresoc.v:194804$13373_Y - connect \$128 $and$libresoc.v:194805$13374_Y - connect \$130 $not$libresoc.v:194806$13375_Y - connect \$132 $not$libresoc.v:194807$13376_Y - connect \$134 $and$libresoc.v:194808$13377_Y - connect \$136 $eq$libresoc.v:194809$13378_Y - connect \$138 $and$libresoc.v:194810$13379_Y - connect \$140 $not$libresoc.v:194811$13380_Y - connect \$142 $not$libresoc.v:194812$13381_Y - connect \$144 $and$libresoc.v:194813$13382_Y - connect \$146 $or$libresoc.v:194814$13383_Y - connect \$148 1'1 - connect \$150 $or$libresoc.v:194816$13384_Y - connect \$152 $not$libresoc.v:194817$13385_Y - connect \$154 $not$libresoc.v:194818$13386_Y - connect \$156 $and$libresoc.v:194819$13387_Y - connect \$158 $not$libresoc.v:194820$13388_Y - connect \$160 $not$libresoc.v:194821$13389_Y - connect \$162 $and$libresoc.v:194822$13390_Y - connect \$164 $not$libresoc.v:194823$13391_Y - connect \$166 $not$libresoc.v:194824$13392_Y - connect \$168 $and$libresoc.v:194825$13393_Y - connect \$170 $not$libresoc.v:194826$13394_Y - connect \$172 $not$libresoc.v:194827$13395_Y - connect \$174 $and$libresoc.v:194828$13396_Y - connect \$176 $not$libresoc.v:194829$13397_Y - connect \$178 $not$libresoc.v:194830$13398_Y - connect \$180 $and$libresoc.v:194831$13399_Y - connect \$182 $not$libresoc.v:194832$13400_Y - connect \$184 $not$libresoc.v:194833$13401_Y - connect \$186 $and$libresoc.v:194834$13402_Y - connect \$189 $and$libresoc.v:194835$13403_Y - connect \$188 $reduce_or$libresoc.v:194836$13404_Y - connect \$192 $not$libresoc.v:194837$13405_Y - connect \$194 $not$libresoc.v:194838$13406_Y - connect \$196 $and$libresoc.v:194839$13407_Y - connect \$198 $not$libresoc.v:194840$13408_Y - connect \$200 $not$libresoc.v:194841$13409_Y - connect \$202 $and$libresoc.v:194842$13410_Y - connect \$204 $or$libresoc.v:194843$13411_Y - connect \$206 1'1 - connect \$208 $or$libresoc.v:194845$13412_Y - connect \$210 $not$libresoc.v:194846$13413_Y - connect \$212 $not$libresoc.v:194847$13414_Y - connect \$214 $and$libresoc.v:194848$13415_Y - connect \$216 $not$libresoc.v:194849$13416_Y - connect \$218 $not$libresoc.v:194850$13417_Y - connect \$220 $and$libresoc.v:194851$13418_Y - connect \$223 $and$libresoc.v:194852$13419_Y - connect \$222 $reduce_or$libresoc.v:194853$13420_Y - connect \$226 $eq$libresoc.v:194854$13421_Y - connect \$228 $and$libresoc.v:194855$13422_Y - connect \$230 $not$libresoc.v:194856$13423_Y - connect \$232 $not$libresoc.v:194857$13424_Y - connect \$234 $not$libresoc.v:194858$13425_Y - connect \$236 $and$libresoc.v:194859$13426_Y - connect \$238 $not$libresoc.v:194860$13427_Y - connect \$23 $ne$libresoc.v:194861$13428_Y - connect \$240 $not$libresoc.v:194862$13429_Y - connect \$242 $and$libresoc.v:194863$13430_Y - connect \$245 $add$libresoc.v:194864$13431_Y - connect \$247 $not$libresoc.v:194865$13432_Y - connect \$249 $not$libresoc.v:194866$13433_Y - connect \$251 $and$libresoc.v:194867$13434_Y - connect \$253 $eq$libresoc.v:194868$13435_Y - connect \$255 $pos$libresoc.v:194869$13436_Y - connect \$257 $ne$libresoc.v:194870$13437_Y - connect \$259 $not$libresoc.v:194871$13438_Y - connect \$261 $not$libresoc.v:194872$13439_Y - connect \$263 $pos$libresoc.v:194873$13441_Y - connect \$265 $pos$libresoc.v:194874$13443_Y - connect \$268 $sub$libresoc.v:194875$13444_Y - connect \$26 $sub$libresoc.v:194876$13445_Y - connect \$271 $add$libresoc.v:194877$13446_Y - connect \$28 $or$libresoc.v:194878$13447_Y - connect \$30 $or$libresoc.v:194879$13448_Y - connect \$32 $ne$libresoc.v:194880$13449_Y - connect \$34 $not$libresoc.v:194881$13450_Y - connect \$36 $and$libresoc.v:194882$13451_Y - connect \$38 $not$libresoc.v:194883$13452_Y - connect \$40 $not$libresoc.v:194884$13453_Y - connect \$42 $pos$libresoc.v:194885$13455_Y - connect \$44 $not$libresoc.v:194886$13456_Y - connect \$46 $not$libresoc.v:194887$13457_Y - connect \$48 $and$libresoc.v:194888$13458_Y - connect \$50 $eq$libresoc.v:194889$13459_Y - connect \$52 $and$libresoc.v:194890$13460_Y - connect \$54 $not$libresoc.v:194891$13461_Y - connect \$56 $not$libresoc.v:194892$13462_Y - connect \$58 $and$libresoc.v:194893$13463_Y - connect \$60 $or$libresoc.v:194894$13464_Y + connect \$122 $or$libresoc.v:197094$13555_Y + connect \$125 $add$libresoc.v:197095$13556_Y + connect \$128 $add$libresoc.v:197096$13557_Y + connect \$130 $not$libresoc.v:197097$13558_Y + connect \$132 $not$libresoc.v:197098$13559_Y + connect \$134 $and$libresoc.v:197099$13560_Y + connect \$136 $not$libresoc.v:197100$13561_Y + connect \$138 $not$libresoc.v:197101$13562_Y + connect \$140 $and$libresoc.v:197102$13563_Y + connect \$142 $eq$libresoc.v:197103$13564_Y + connect \$144 $and$libresoc.v:197104$13565_Y + connect \$146 $not$libresoc.v:197105$13566_Y + connect \$148 $not$libresoc.v:197106$13567_Y + connect \$150 $and$libresoc.v:197107$13568_Y + connect \$152 $or$libresoc.v:197108$13569_Y + connect \$154 1'1 + connect \$156 $or$libresoc.v:197110$13570_Y + connect \$158 $not$libresoc.v:197111$13571_Y + connect \$160 $not$libresoc.v:197112$13572_Y + connect \$162 $and$libresoc.v:197113$13573_Y + connect \$164 $not$libresoc.v:197114$13574_Y + connect \$166 $not$libresoc.v:197115$13575_Y + connect \$168 $and$libresoc.v:197116$13576_Y + connect \$170 $not$libresoc.v:197117$13577_Y + connect \$172 $not$libresoc.v:197118$13578_Y + connect \$174 $and$libresoc.v:197119$13579_Y + connect \$176 $not$libresoc.v:197120$13580_Y + connect \$178 $not$libresoc.v:197121$13581_Y + connect \$180 $and$libresoc.v:197122$13582_Y + connect \$182 $not$libresoc.v:197123$13583_Y + connect \$184 $not$libresoc.v:197124$13584_Y + connect \$186 $and$libresoc.v:197125$13585_Y + connect \$188 $not$libresoc.v:197126$13586_Y + connect \$190 $not$libresoc.v:197127$13587_Y + connect \$192 $and$libresoc.v:197128$13588_Y + connect \$195 $and$libresoc.v:197129$13589_Y + connect \$194 $reduce_or$libresoc.v:197130$13590_Y + connect \$198 $not$libresoc.v:197131$13591_Y + connect \$200 $not$libresoc.v:197132$13592_Y + connect \$202 $and$libresoc.v:197133$13593_Y + connect \$204 $not$libresoc.v:197134$13594_Y + connect \$206 $not$libresoc.v:197135$13595_Y + connect \$208 $and$libresoc.v:197136$13596_Y + connect \$210 $or$libresoc.v:197137$13597_Y + connect \$212 1'1 + connect \$214 $or$libresoc.v:197139$13598_Y + connect \$216 $not$libresoc.v:197140$13599_Y + connect \$218 $not$libresoc.v:197141$13600_Y + connect \$220 $and$libresoc.v:197142$13601_Y + connect \$222 $not$libresoc.v:197143$13602_Y + connect \$224 $not$libresoc.v:197144$13603_Y + connect \$226 $and$libresoc.v:197145$13604_Y + connect \$229 $and$libresoc.v:197146$13605_Y + connect \$228 $reduce_or$libresoc.v:197147$13606_Y + connect \$232 $eq$libresoc.v:197148$13607_Y + connect \$234 $and$libresoc.v:197149$13608_Y + connect \$236 $not$libresoc.v:197150$13609_Y + connect \$238 $not$libresoc.v:197151$13610_Y + connect \$23 $ne$libresoc.v:197152$13611_Y + connect \$240 $not$libresoc.v:197153$13612_Y + connect \$242 $and$libresoc.v:197154$13613_Y + connect \$244 $not$libresoc.v:197155$13614_Y + connect \$246 $not$libresoc.v:197156$13615_Y + connect \$248 $and$libresoc.v:197157$13616_Y + connect \$250 $eq$libresoc.v:197158$13617_Y + connect \$252 $pos$libresoc.v:197159$13618_Y + connect \$254 $ne$libresoc.v:197160$13619_Y + connect \$256 $not$libresoc.v:197161$13620_Y + connect \$258 $not$libresoc.v:197162$13621_Y + connect \$260 $pos$libresoc.v:197163$13623_Y + connect \$262 $pos$libresoc.v:197164$13625_Y + connect \$265 $sub$libresoc.v:197165$13626_Y + connect \$268 $add$libresoc.v:197166$13627_Y + connect \$26 $sub$libresoc.v:197167$13628_Y + connect \$28 $or$libresoc.v:197168$13629_Y + connect \$30 $or$libresoc.v:197169$13630_Y + connect \$32 $ne$libresoc.v:197170$13631_Y + connect \$34 $not$libresoc.v:197171$13632_Y + connect \$36 $and$libresoc.v:197172$13633_Y + connect \$38 $not$libresoc.v:197173$13634_Y + connect \$40 $not$libresoc.v:197174$13635_Y + connect \$42 $pos$libresoc.v:197175$13637_Y + connect \$44 $not$libresoc.v:197176$13638_Y + connect \$46 $not$libresoc.v:197177$13639_Y + connect \$48 $and$libresoc.v:197178$13640_Y + connect \$50 $eq$libresoc.v:197179$13641_Y + connect \$52 $and$libresoc.v:197180$13642_Y + connect \$54 $not$libresoc.v:197181$13643_Y + connect \$56 $not$libresoc.v:197182$13644_Y + connect \$58 $and$libresoc.v:197183$13645_Y + connect \$60 $or$libresoc.v:197184$13646_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:194896$13465_Y - connect \$66 $not$libresoc.v:194897$13466_Y - connect \$68 $not$libresoc.v:194898$13467_Y - connect \$70 $and$libresoc.v:194899$13468_Y - connect \$72 $eq$libresoc.v:194900$13469_Y - connect \$74 $and$libresoc.v:194901$13470_Y - connect \$76 $not$libresoc.v:194902$13471_Y - connect \$78 $not$libresoc.v:194903$13472_Y - connect \$80 $and$libresoc.v:194904$13473_Y - connect \$82 $or$libresoc.v:194905$13474_Y + connect \$64 $or$libresoc.v:197186$13647_Y + connect \$66 $not$libresoc.v:197187$13648_Y + connect \$68 $not$libresoc.v:197188$13649_Y + connect \$70 $and$libresoc.v:197189$13650_Y + connect \$72 $eq$libresoc.v:197190$13651_Y + connect \$74 $and$libresoc.v:197191$13652_Y + connect \$76 $not$libresoc.v:197192$13653_Y + connect \$78 $not$libresoc.v:197193$13654_Y + connect \$80 $and$libresoc.v:197194$13655_Y + connect \$82 $or$libresoc.v:197195$13656_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:194907$13475_Y - connect \$88 $not$libresoc.v:194908$13476_Y - connect \$90 $not$libresoc.v:194909$13477_Y - connect \$93 $add$libresoc.v:194910$13478_Y - connect \$96 $mul$libresoc.v:194911$13479_Y - connect \$95 $shr$libresoc.v:194912$13480_Y [31:0] + connect \$86 $or$libresoc.v:197197$13657_Y + connect \$88 $not$libresoc.v:197198$13658_Y + connect \$90 $not$libresoc.v:197199$13659_Y + connect \$93 $add$libresoc.v:197200$13660_Y + connect \$96 $mul$libresoc.v:197201$13661_Y + connect \$95 $shr$libresoc.v:197202$13662_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 - connect \$244 \$245 + connect \$124 \$125 + connect \$127 \$128 + connect \$264 \$265 connect \$267 \$268 - connect \$270 \$271 connect \dec2_sv_a_nz 1'0 connect \svstate_i_ok 1'0 connect \svstate_i 0 connect \is_svp64_mode 1'0 + connect \pred_insn_ready_o 1'0 + connect \pred_mask_valid_o 1'0 + connect \next_dststep \$128 [6:0] + connect \next_srcstep \$125 [6:0] connect \dbg_core_dbg_msr \dec2_cur_msr connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc @@ -412681,485 +416704,485 @@ module \ti connect \sram4k_1_enable \jtag_wb_sram_en connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:197549.1-198740.10" +attribute \src "libresoc.v:199862.1-201053.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:198285.3-198286.25" + attribute \src "libresoc.v:200598.3-200599.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:198283.3-198284.41" + attribute \src "libresoc.v:200596.3-200597.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:198643.3-198651.6" - wire $0\alu_l_r_alu$next[0:0]$14382 - attribute \src "libresoc.v:198211.3-198212.39" + attribute \src "libresoc.v:200956.3-200964.6" + wire $0\alu_l_r_alu$next[0:0]$14567 + attribute \src "libresoc.v:200524.3-200525.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14308 - attribute \src "libresoc.v:198251.3-198252.61" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14493 + attribute \src "libresoc.v:200564.3-200565.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 - attribute \src "libresoc.v:198245.3-198246.69" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + attribute \src "libresoc.v:200558.3-200559.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14310 - attribute \src "libresoc.v:198247.3-198248.63" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14495 + attribute \src "libresoc.v:200560.3-200561.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 - attribute \src "libresoc.v:198243.3-198244.73" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + attribute \src "libresoc.v:200556.3-200557.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 - attribute \src "libresoc.v:198253.3-198254.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + attribute \src "libresoc.v:200566.3-200567.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 - attribute \src "libresoc.v:198259.3-198260.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + attribute \src "libresoc.v:200572.3-200573.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14314 - attribute \src "libresoc.v:198249.3-198250.61" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14499 + attribute \src "libresoc.v:200562.3-200563.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 - attribute \src "libresoc.v:198257.3-198258.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + attribute \src "libresoc.v:200570.3-200571.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14316 - attribute \src "libresoc.v:198255.3-198256.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + attribute \src "libresoc.v:200568.3-200569.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:198634.3-198642.6" - wire $0\alui_l_r_alui$next[0:0]$14379 - attribute \src "libresoc.v:198213.3-198214.43" + attribute \src "libresoc.v:200947.3-200955.6" + wire $0\alui_l_r_alui$next[0:0]$14564 + attribute \src "libresoc.v:200526.3-200527.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $0\data_r0__o$next[63:0]$14327 - attribute \src "libresoc.v:198239.3-198240.37" + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $0\data_r0__o$next[63:0]$14512 + attribute \src "libresoc.v:200552.3-200553.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire $0\data_r0__o_ok$next[0:0]$14328 - attribute \src "libresoc.v:198241.3-198242.43" + attribute \src "libresoc.v:200797.3-200818.6" + wire $0\data_r0__o_ok$next[0:0]$14513 + attribute \src "libresoc.v:200554.3-200555.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14335 - attribute \src "libresoc.v:198235.3-198236.45" + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14520 + attribute \src "libresoc.v:200548.3-200549.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire $0\data_r1__fast1_ok$next[0:0]$14336 - attribute \src "libresoc.v:198237.3-198238.51" + attribute \src "libresoc.v:200819.3-200840.6" + wire $0\data_r1__fast1_ok$next[0:0]$14521 + attribute \src "libresoc.v:200550.3-200551.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14343 - attribute \src "libresoc.v:198231.3-198232.45" + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14528 + attribute \src "libresoc.v:200544.3-200545.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire $0\data_r2__fast2_ok$next[0:0]$14344 - attribute \src "libresoc.v:198233.3-198234.51" + attribute \src "libresoc.v:200841.3-200862.6" + wire $0\data_r2__fast2_ok$next[0:0]$14529 + attribute \src "libresoc.v:200546.3-200547.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $0\data_r3__nia$next[63:0]$14351 - attribute \src "libresoc.v:198227.3-198228.41" + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $0\data_r3__nia$next[63:0]$14536 + attribute \src "libresoc.v:200540.3-200541.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire $0\data_r3__nia_ok$next[0:0]$14352 - attribute \src "libresoc.v:198229.3-198230.47" + attribute \src "libresoc.v:200863.3-200884.6" + wire $0\data_r3__nia_ok$next[0:0]$14537 + attribute \src "libresoc.v:200542.3-200543.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $0\data_r4__msr$next[63:0]$14359 - attribute \src "libresoc.v:198223.3-198224.41" + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $0\data_r4__msr$next[63:0]$14544 + attribute \src "libresoc.v:200536.3-200537.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire $0\data_r4__msr_ok$next[0:0]$14360 - attribute \src "libresoc.v:198225.3-198226.47" + attribute \src "libresoc.v:200885.3-200906.6" + wire $0\data_r4__msr_ok$next[0:0]$14545 + attribute \src "libresoc.v:200538.3-200539.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:198652.3-198661.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:198662.3-198671.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:198672.3-198681.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:198682.3-198691.6" + attribute \src "libresoc.v:200995.3-201004.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:198692.3-198701.6" + attribute \src "libresoc.v:201005.3-201014.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:197550.7-197550.20" + attribute \src "libresoc.v:199863.7-199863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198421.3-198429.6" - wire $0\opc_l_r_opc$next[0:0]$14293 - attribute \src "libresoc.v:198269.3-198270.39" + attribute \src "libresoc.v:200734.3-200742.6" + wire $0\opc_l_r_opc$next[0:0]$14478 + attribute \src "libresoc.v:200582.3-200583.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:198412.3-198420.6" - wire $0\opc_l_s_opc$next[0:0]$14290 - attribute \src "libresoc.v:198271.3-198272.39" + attribute \src "libresoc.v:200725.3-200733.6" + wire $0\opc_l_s_opc$next[0:0]$14475 + attribute \src "libresoc.v:200584.3-200585.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:198702.3-198710.6" - wire width 5 $0\prev_wr_go$next[4:0]$14390 - attribute \src "libresoc.v:198281.3-198282.37" + attribute \src "libresoc.v:201015.3-201023.6" + wire width 5 $0\prev_wr_go$next[4:0]$14575 + attribute \src "libresoc.v:200594.3-200595.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:198366.3-198375.6" + attribute \src "libresoc.v:200679.3-200688.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:198457.3-198465.6" - wire width 5 $0\req_l_r_req$next[4:0]$14305 - attribute \src "libresoc.v:198261.3-198262.39" + attribute \src "libresoc.v:200770.3-200778.6" + wire width 5 $0\req_l_r_req$next[4:0]$14490 + attribute \src "libresoc.v:200574.3-200575.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:198448.3-198456.6" - wire width 5 $0\req_l_s_req$next[4:0]$14302 - attribute \src "libresoc.v:198263.3-198264.39" + attribute \src "libresoc.v:200761.3-200769.6" + wire width 5 $0\req_l_s_req$next[4:0]$14487 + attribute \src "libresoc.v:200576.3-200577.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:198385.3-198393.6" - wire $0\rok_l_r_rdok$next[0:0]$14281 - attribute \src "libresoc.v:198277.3-198278.41" + attribute \src "libresoc.v:200698.3-200706.6" + wire $0\rok_l_r_rdok$next[0:0]$14466 + attribute \src "libresoc.v:200590.3-200591.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:198376.3-198384.6" - wire $0\rok_l_s_rdok$next[0:0]$14278 - attribute \src "libresoc.v:198279.3-198280.41" + attribute \src "libresoc.v:200689.3-200697.6" + wire $0\rok_l_s_rdok$next[0:0]$14463 + attribute \src "libresoc.v:200592.3-200593.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:198403.3-198411.6" - wire $0\rst_l_r_rst$next[0:0]$14287 - attribute \src "libresoc.v:198273.3-198274.39" + attribute \src "libresoc.v:200716.3-200724.6" + wire $0\rst_l_r_rst$next[0:0]$14472 + attribute \src "libresoc.v:200586.3-200587.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:198394.3-198402.6" - wire $0\rst_l_s_rst$next[0:0]$14284 - attribute \src "libresoc.v:198275.3-198276.39" + attribute \src "libresoc.v:200707.3-200715.6" + wire $0\rst_l_s_rst$next[0:0]$14469 + attribute \src "libresoc.v:200588.3-200589.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:198439.3-198447.6" - wire width 4 $0\src_l_r_src$next[3:0]$14299 - attribute \src "libresoc.v:198265.3-198266.39" + attribute \src "libresoc.v:200752.3-200760.6" + wire width 4 $0\src_l_r_src$next[3:0]$14484 + attribute \src "libresoc.v:200578.3-200579.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:198430.3-198438.6" - wire width 4 $0\src_l_s_src$next[3:0]$14296 - attribute \src "libresoc.v:198267.3-198268.39" + attribute \src "libresoc.v:200743.3-200751.6" + wire width 4 $0\src_l_s_src$next[3:0]$14481 + attribute \src "libresoc.v:200580.3-200581.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:198594.3-198603.6" - wire width 64 $0\src_r0$next[63:0]$14367 - attribute \src "libresoc.v:198221.3-198222.29" + attribute \src "libresoc.v:200907.3-200916.6" + wire width 64 $0\src_r0$next[63:0]$14552 + attribute \src "libresoc.v:200534.3-200535.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:198604.3-198613.6" - wire width 64 $0\src_r1$next[63:0]$14370 - attribute \src "libresoc.v:198219.3-198220.29" + attribute \src "libresoc.v:200917.3-200926.6" + wire width 64 $0\src_r1$next[63:0]$14555 + attribute \src "libresoc.v:200532.3-200533.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:198614.3-198623.6" - wire width 64 $0\src_r2$next[63:0]$14373 - attribute \src "libresoc.v:198217.3-198218.29" + attribute \src "libresoc.v:200927.3-200936.6" + wire width 64 $0\src_r2$next[63:0]$14558 + attribute \src "libresoc.v:200530.3-200531.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:198624.3-198633.6" - wire width 64 $0\src_r3$next[63:0]$14376 - attribute \src "libresoc.v:198215.3-198216.29" + attribute \src "libresoc.v:200937.3-200946.6" + wire width 64 $0\src_r3$next[63:0]$14561 + attribute \src "libresoc.v:200528.3-200529.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:197676.7-197676.24" + attribute \src "libresoc.v:199989.7-199989.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:197686.7-197686.26" + attribute \src "libresoc.v:199999.7-199999.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:198643.3-198651.6" - wire $1\alu_l_r_alu$next[0:0]$14383 - attribute \src "libresoc.v:197694.7-197694.25" + attribute \src "libresoc.v:200956.3-200964.6" + wire $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200007.7-200007.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14317 - attribute \src "libresoc.v:197730.14-197730.59" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + attribute \src "libresoc.v:200043.14-200043.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 - attribute \src "libresoc.v:197749.14-197749.51" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + attribute \src "libresoc.v:200062.14-200062.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14319 - attribute \src "libresoc.v:197753.14-197753.45" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + attribute \src "libresoc.v:200066.14-200066.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 - attribute \src "libresoc.v:197832.13-197832.49" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + attribute \src "libresoc.v:200145.13-200145.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 - attribute \src "libresoc.v:197836.7-197836.41" + attribute \src "libresoc.v:200779.3-200796.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + attribute \src "libresoc.v:200149.7-200149.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 - attribute \src "libresoc.v:197840.13-197840.48" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + attribute \src "libresoc.v:200153.13-200153.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14323 - attribute \src "libresoc.v:197844.14-197844.59" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + attribute \src "libresoc.v:200157.14-200157.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 - attribute \src "libresoc.v:197848.14-197848.52" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 + attribute \src "libresoc.v:200161.14-200161.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 - attribute \src "libresoc.v:197852.13-197852.48" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 + attribute \src "libresoc.v:200165.13-200165.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:198634.3-198642.6" - wire $1\alui_l_r_alui$next[0:0]$14380 - attribute \src "libresoc.v:197858.7-197858.27" + attribute \src "libresoc.v:200947.3-200955.6" + wire $1\alui_l_r_alui$next[0:0]$14565 + attribute \src "libresoc.v:200171.7-200171.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $1\data_r0__o$next[63:0]$14329 - attribute \src "libresoc.v:197890.14-197890.47" + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $1\data_r0__o$next[63:0]$14514 + attribute \src "libresoc.v:200203.14-200203.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire $1\data_r0__o_ok$next[0:0]$14330 - attribute \src "libresoc.v:197894.7-197894.27" + attribute \src "libresoc.v:200797.3-200818.6" + wire $1\data_r0__o_ok$next[0:0]$14515 + attribute \src "libresoc.v:200207.7-200207.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14337 - attribute \src "libresoc.v:197898.14-197898.51" + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14522 + attribute \src "libresoc.v:200211.14-200211.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire $1\data_r1__fast1_ok$next[0:0]$14338 - attribute \src "libresoc.v:197902.7-197902.31" + attribute \src "libresoc.v:200819.3-200840.6" + wire $1\data_r1__fast1_ok$next[0:0]$14523 + attribute \src "libresoc.v:200215.7-200215.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14345 - attribute \src "libresoc.v:197906.14-197906.51" + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14530 + attribute \src "libresoc.v:200219.14-200219.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire $1\data_r2__fast2_ok$next[0:0]$14346 - attribute \src "libresoc.v:197910.7-197910.31" + attribute \src "libresoc.v:200841.3-200862.6" + wire $1\data_r2__fast2_ok$next[0:0]$14531 + attribute \src "libresoc.v:200223.7-200223.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $1\data_r3__nia$next[63:0]$14353 - attribute \src "libresoc.v:197914.14-197914.49" + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $1\data_r3__nia$next[63:0]$14538 + attribute \src "libresoc.v:200227.14-200227.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire $1\data_r3__nia_ok$next[0:0]$14354 - attribute \src "libresoc.v:197918.7-197918.29" + attribute \src "libresoc.v:200863.3-200884.6" + wire $1\data_r3__nia_ok$next[0:0]$14539 + attribute \src "libresoc.v:200231.7-200231.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $1\data_r4__msr$next[63:0]$14361 - attribute \src "libresoc.v:197922.14-197922.49" + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $1\data_r4__msr$next[63:0]$14546 + attribute \src "libresoc.v:200235.14-200235.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire $1\data_r4__msr_ok$next[0:0]$14362 - attribute \src "libresoc.v:197926.7-197926.29" + attribute \src "libresoc.v:200885.3-200906.6" + wire $1\data_r4__msr_ok$next[0:0]$14547 + attribute \src "libresoc.v:200239.7-200239.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:198652.3-198661.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:198662.3-198671.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:198672.3-198681.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:198682.3-198691.6" + attribute \src "libresoc.v:200995.3-201004.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:198692.3-198701.6" + attribute \src "libresoc.v:201005.3-201014.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:198421.3-198429.6" - wire $1\opc_l_r_opc$next[0:0]$14294 - attribute \src "libresoc.v:197957.7-197957.25" + attribute \src "libresoc.v:200734.3-200742.6" + wire $1\opc_l_r_opc$next[0:0]$14479 + attribute \src "libresoc.v:200270.7-200270.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:198412.3-198420.6" - wire $1\opc_l_s_opc$next[0:0]$14291 - attribute \src "libresoc.v:197961.7-197961.25" + attribute \src "libresoc.v:200725.3-200733.6" + wire $1\opc_l_s_opc$next[0:0]$14476 + attribute \src "libresoc.v:200274.7-200274.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:198702.3-198710.6" - wire width 5 $1\prev_wr_go$next[4:0]$14391 - attribute \src "libresoc.v:198073.13-198073.31" + attribute \src "libresoc.v:201015.3-201023.6" + wire width 5 $1\prev_wr_go$next[4:0]$14576 + attribute \src "libresoc.v:200386.13-200386.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:198366.3-198375.6" + attribute \src "libresoc.v:200679.3-200688.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:198457.3-198465.6" - wire width 5 $1\req_l_r_req$next[4:0]$14306 - attribute \src "libresoc.v:198081.13-198081.32" + attribute \src "libresoc.v:200770.3-200778.6" + wire width 5 $1\req_l_r_req$next[4:0]$14491 + attribute \src "libresoc.v:200394.13-200394.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:198448.3-198456.6" - wire width 5 $1\req_l_s_req$next[4:0]$14303 - attribute \src "libresoc.v:198085.13-198085.32" + attribute \src "libresoc.v:200761.3-200769.6" + wire width 5 $1\req_l_s_req$next[4:0]$14488 + attribute \src "libresoc.v:200398.13-200398.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:198385.3-198393.6" - wire $1\rok_l_r_rdok$next[0:0]$14282 - attribute \src "libresoc.v:198097.7-198097.26" + attribute \src "libresoc.v:200698.3-200706.6" + wire $1\rok_l_r_rdok$next[0:0]$14467 + attribute \src "libresoc.v:200410.7-200410.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:198376.3-198384.6" - wire $1\rok_l_s_rdok$next[0:0]$14279 - attribute \src "libresoc.v:198101.7-198101.26" + attribute \src "libresoc.v:200689.3-200697.6" + wire $1\rok_l_s_rdok$next[0:0]$14464 + attribute \src "libresoc.v:200414.7-200414.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:198403.3-198411.6" - wire $1\rst_l_r_rst$next[0:0]$14288 - attribute \src "libresoc.v:198105.7-198105.25" + attribute \src "libresoc.v:200716.3-200724.6" + wire $1\rst_l_r_rst$next[0:0]$14473 + attribute \src "libresoc.v:200418.7-200418.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:198394.3-198402.6" - wire $1\rst_l_s_rst$next[0:0]$14285 - attribute \src "libresoc.v:198109.7-198109.25" + attribute \src "libresoc.v:200707.3-200715.6" + wire $1\rst_l_s_rst$next[0:0]$14470 + attribute \src "libresoc.v:200422.7-200422.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:198439.3-198447.6" - wire width 4 $1\src_l_r_src$next[3:0]$14300 - attribute \src "libresoc.v:198125.13-198125.31" + attribute \src "libresoc.v:200752.3-200760.6" + wire width 4 $1\src_l_r_src$next[3:0]$14485 + attribute \src "libresoc.v:200438.13-200438.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:198430.3-198438.6" - wire width 4 $1\src_l_s_src$next[3:0]$14297 - attribute \src "libresoc.v:198129.13-198129.31" + attribute \src "libresoc.v:200743.3-200751.6" + wire width 4 $1\src_l_s_src$next[3:0]$14482 + attribute \src "libresoc.v:200442.13-200442.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:198594.3-198603.6" - wire width 64 $1\src_r0$next[63:0]$14368 - attribute \src "libresoc.v:198133.14-198133.43" + attribute \src "libresoc.v:200907.3-200916.6" + wire width 64 $1\src_r0$next[63:0]$14553 + attribute \src "libresoc.v:200446.14-200446.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:198604.3-198613.6" - wire width 64 $1\src_r1$next[63:0]$14371 - attribute \src "libresoc.v:198137.14-198137.43" + attribute \src "libresoc.v:200917.3-200926.6" + wire width 64 $1\src_r1$next[63:0]$14556 + attribute \src "libresoc.v:200450.14-200450.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:198614.3-198623.6" - wire width 64 $1\src_r2$next[63:0]$14374 - attribute \src "libresoc.v:198141.14-198141.43" + attribute \src "libresoc.v:200927.3-200936.6" + wire width 64 $1\src_r2$next[63:0]$14559 + attribute \src "libresoc.v:200454.14-200454.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:198624.3-198633.6" - wire width 64 $1\src_r3$next[63:0]$14377 - attribute \src "libresoc.v:198145.14-198145.43" + attribute \src "libresoc.v:200937.3-200946.6" + wire width 64 $1\src_r3$next[63:0]$14562 + attribute \src "libresoc.v:200458.14-200458.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $2\data_r0__o$next[63:0]$14331 - attribute \src "libresoc.v:198484.3-198505.6" - wire $2\data_r0__o_ok$next[0:0]$14332 - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14339 - attribute \src "libresoc.v:198506.3-198527.6" - wire $2\data_r1__fast1_ok$next[0:0]$14340 - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14347 - attribute \src "libresoc.v:198528.3-198549.6" - wire $2\data_r2__fast2_ok$next[0:0]$14348 - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $2\data_r3__nia$next[63:0]$14355 - attribute \src "libresoc.v:198550.3-198571.6" - wire $2\data_r3__nia_ok$next[0:0]$14356 - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $2\data_r4__msr$next[63:0]$14363 - attribute \src "libresoc.v:198572.3-198593.6" - wire $2\data_r4__msr_ok$next[0:0]$14364 - attribute \src "libresoc.v:198484.3-198505.6" - wire $3\data_r0__o_ok$next[0:0]$14333 - attribute \src "libresoc.v:198506.3-198527.6" - wire $3\data_r1__fast1_ok$next[0:0]$14341 - attribute \src "libresoc.v:198528.3-198549.6" - wire $3\data_r2__fast2_ok$next[0:0]$14349 - attribute \src "libresoc.v:198550.3-198571.6" - wire $3\data_r3__nia_ok$next[0:0]$14357 - attribute \src "libresoc.v:198572.3-198593.6" - wire $3\data_r4__msr_ok$next[0:0]$14365 - attribute \src "libresoc.v:198151.18-198151.112" - wire width 4 $and$libresoc.v:198151$14178_Y - attribute \src "libresoc.v:198152.19-198152.125" - wire $and$libresoc.v:198152$14179_Y - attribute \src "libresoc.v:198153.19-198153.125" - wire $and$libresoc.v:198153$14180_Y - attribute \src "libresoc.v:198154.19-198154.125" - wire $and$libresoc.v:198154$14181_Y - attribute \src "libresoc.v:198155.19-198155.125" - wire $and$libresoc.v:198155$14182_Y - attribute \src "libresoc.v:198156.19-198156.125" - wire $and$libresoc.v:198156$14183_Y - attribute \src "libresoc.v:198157.19-198157.157" - wire width 5 $and$libresoc.v:198157$14184_Y - attribute \src "libresoc.v:198158.19-198158.121" - wire width 5 $and$libresoc.v:198158$14185_Y - attribute \src "libresoc.v:198159.19-198159.127" - wire $and$libresoc.v:198159$14186_Y - attribute \src "libresoc.v:198160.19-198160.127" - wire $and$libresoc.v:198160$14187_Y - attribute \src "libresoc.v:198161.18-198161.110" - wire $and$libresoc.v:198161$14188_Y - attribute \src "libresoc.v:198162.19-198162.127" - wire $and$libresoc.v:198162$14189_Y - attribute \src "libresoc.v:198163.19-198163.127" - wire $and$libresoc.v:198163$14190_Y - attribute \src "libresoc.v:198164.19-198164.127" - wire $and$libresoc.v:198164$14191_Y - attribute \src "libresoc.v:198166.18-198166.98" - wire $and$libresoc.v:198166$14193_Y - attribute \src "libresoc.v:198168.18-198168.100" - wire $and$libresoc.v:198168$14195_Y - attribute \src "libresoc.v:198169.18-198169.171" - wire width 5 $and$libresoc.v:198169$14196_Y - attribute \src "libresoc.v:198171.18-198171.119" - wire width 5 $and$libresoc.v:198171$14198_Y - attribute \src "libresoc.v:198174.18-198174.116" - wire $and$libresoc.v:198174$14201_Y - attribute \src "libresoc.v:198178.17-198178.123" - wire $and$libresoc.v:198178$14205_Y - attribute \src "libresoc.v:198180.18-198180.113" - wire $and$libresoc.v:198180$14207_Y - attribute \src "libresoc.v:198181.18-198181.125" - wire width 5 $and$libresoc.v:198181$14208_Y - attribute \src "libresoc.v:198183.18-198183.112" - wire $and$libresoc.v:198183$14210_Y - attribute \src "libresoc.v:198185.18-198185.127" - wire $and$libresoc.v:198185$14212_Y - attribute \src "libresoc.v:198186.18-198186.127" - wire $and$libresoc.v:198186$14213_Y - attribute \src "libresoc.v:198187.18-198187.117" - wire $and$libresoc.v:198187$14214_Y - attribute \src "libresoc.v:198192.18-198192.131" - wire $and$libresoc.v:198192$14219_Y - attribute \src "libresoc.v:198193.18-198193.124" - wire width 5 $and$libresoc.v:198193$14220_Y - attribute \src "libresoc.v:198196.18-198196.116" - wire $and$libresoc.v:198196$14223_Y - attribute \src "libresoc.v:198197.18-198197.120" - wire $and$libresoc.v:198197$14224_Y - attribute \src "libresoc.v:198198.18-198198.120" - wire $and$libresoc.v:198198$14225_Y - attribute \src "libresoc.v:198199.18-198199.118" - wire $and$libresoc.v:198199$14226_Y - attribute \src "libresoc.v:198200.18-198200.118" - wire $and$libresoc.v:198200$14227_Y - attribute \src "libresoc.v:198206.18-198206.135" - wire $and$libresoc.v:198206$14233_Y - attribute \src "libresoc.v:198207.18-198207.133" - wire $and$libresoc.v:198207$14234_Y - attribute \src "libresoc.v:198208.18-198208.160" - wire width 4 $and$libresoc.v:198208$14235_Y - attribute \src "libresoc.v:198209.18-198209.112" - wire width 4 $and$libresoc.v:198209$14236_Y - attribute \src "libresoc.v:198182.18-198182.113" - wire $eq$libresoc.v:198182$14209_Y - attribute \src "libresoc.v:198184.18-198184.119" - wire $eq$libresoc.v:198184$14211_Y - attribute \src "libresoc.v:198165.18-198165.97" - wire $not$libresoc.v:198165$14192_Y - attribute \src "libresoc.v:198167.18-198167.99" - wire $not$libresoc.v:198167$14194_Y - attribute \src "libresoc.v:198170.18-198170.113" - wire width 5 $not$libresoc.v:198170$14197_Y - attribute \src "libresoc.v:198173.18-198173.106" - wire $not$libresoc.v:198173$14200_Y - attribute \src "libresoc.v:198179.18-198179.121" - wire $not$libresoc.v:198179$14206_Y - attribute \src "libresoc.v:198194.17-198194.113" - wire width 4 $not$libresoc.v:198194$14221_Y - attribute \src "libresoc.v:198210.18-198210.114" - wire width 4 $not$libresoc.v:198210$14237_Y - attribute \src "libresoc.v:198177.18-198177.112" - wire $or$libresoc.v:198177$14204_Y - attribute \src "libresoc.v:198188.18-198188.122" - wire $or$libresoc.v:198188$14215_Y - attribute \src "libresoc.v:198189.18-198189.124" - wire $or$libresoc.v:198189$14216_Y - attribute \src "libresoc.v:198190.18-198190.181" - wire width 5 $or$libresoc.v:198190$14217_Y - attribute \src "libresoc.v:198191.18-198191.168" - wire width 4 $or$libresoc.v:198191$14218_Y - attribute \src "libresoc.v:198195.18-198195.120" - wire width 5 $or$libresoc.v:198195$14222_Y - attribute \src "libresoc.v:198205.17-198205.117" - wire width 4 $or$libresoc.v:198205$14232_Y - attribute \src "libresoc.v:198150.17-198150.104" - wire $reduce_and$libresoc.v:198150$14177_Y - attribute \src "libresoc.v:198172.18-198172.106" - wire $reduce_or$libresoc.v:198172$14199_Y - attribute \src "libresoc.v:198175.18-198175.113" - wire $reduce_or$libresoc.v:198175$14202_Y - attribute \src "libresoc.v:198176.18-198176.112" - wire $reduce_or$libresoc.v:198176$14203_Y - attribute \src "libresoc.v:198201.18-198201.118" - wire width 64 $ternary$libresoc.v:198201$14228_Y - attribute \src "libresoc.v:198202.18-198202.118" - wire width 64 $ternary$libresoc.v:198202$14229_Y - attribute \src "libresoc.v:198203.18-198203.118" - wire width 64 $ternary$libresoc.v:198203$14230_Y - attribute \src "libresoc.v:198204.18-198204.118" - wire width 64 $ternary$libresoc.v:198204$14231_Y + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $2\data_r0__o$next[63:0]$14516 + attribute \src "libresoc.v:200797.3-200818.6" + wire $2\data_r0__o_ok$next[0:0]$14517 + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14524 + attribute \src "libresoc.v:200819.3-200840.6" + wire $2\data_r1__fast1_ok$next[0:0]$14525 + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14532 + attribute \src "libresoc.v:200841.3-200862.6" + wire $2\data_r2__fast2_ok$next[0:0]$14533 + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $2\data_r3__nia$next[63:0]$14540 + attribute \src "libresoc.v:200863.3-200884.6" + wire $2\data_r3__nia_ok$next[0:0]$14541 + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $2\data_r4__msr$next[63:0]$14548 + attribute \src "libresoc.v:200885.3-200906.6" + wire $2\data_r4__msr_ok$next[0:0]$14549 + attribute \src "libresoc.v:200797.3-200818.6" + wire $3\data_r0__o_ok$next[0:0]$14518 + attribute \src "libresoc.v:200819.3-200840.6" + wire $3\data_r1__fast1_ok$next[0:0]$14526 + attribute \src "libresoc.v:200841.3-200862.6" + wire $3\data_r2__fast2_ok$next[0:0]$14534 + attribute \src "libresoc.v:200863.3-200884.6" + wire $3\data_r3__nia_ok$next[0:0]$14542 + attribute \src "libresoc.v:200885.3-200906.6" + wire $3\data_r4__msr_ok$next[0:0]$14550 + attribute \src "libresoc.v:200464.18-200464.112" + wire width 4 $and$libresoc.v:200464$14363_Y + attribute \src "libresoc.v:200465.19-200465.125" + wire $and$libresoc.v:200465$14364_Y + attribute \src "libresoc.v:200466.19-200466.125" + wire $and$libresoc.v:200466$14365_Y + attribute \src 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\src "libresoc.v:200500.18-200500.117" + wire $and$libresoc.v:200500$14399_Y + attribute \src "libresoc.v:200505.18-200505.131" + wire $and$libresoc.v:200505$14404_Y + attribute \src "libresoc.v:200506.18-200506.124" + wire width 5 $and$libresoc.v:200506$14405_Y + attribute \src "libresoc.v:200509.18-200509.116" + wire $and$libresoc.v:200509$14408_Y + attribute \src "libresoc.v:200510.18-200510.120" + wire $and$libresoc.v:200510$14409_Y + attribute \src "libresoc.v:200511.18-200511.120" + wire $and$libresoc.v:200511$14410_Y + attribute \src "libresoc.v:200512.18-200512.118" + wire $and$libresoc.v:200512$14411_Y + attribute \src "libresoc.v:200513.18-200513.118" + wire $and$libresoc.v:200513$14412_Y + attribute \src "libresoc.v:200519.18-200519.135" + wire $and$libresoc.v:200519$14418_Y + attribute \src "libresoc.v:200520.18-200520.133" + wire $and$libresoc.v:200520$14419_Y + attribute \src "libresoc.v:200521.18-200521.160" + wire width 4 $and$libresoc.v:200521$14420_Y + attribute \src "libresoc.v:200522.18-200522.112" + wire width 4 $and$libresoc.v:200522$14421_Y + attribute \src "libresoc.v:200495.18-200495.113" + wire $eq$libresoc.v:200495$14394_Y + attribute \src "libresoc.v:200497.18-200497.119" + wire $eq$libresoc.v:200497$14396_Y + attribute \src "libresoc.v:200478.18-200478.97" + wire $not$libresoc.v:200478$14377_Y + attribute \src "libresoc.v:200480.18-200480.99" + wire $not$libresoc.v:200480$14379_Y + attribute \src "libresoc.v:200483.18-200483.113" + wire width 5 $not$libresoc.v:200483$14382_Y + attribute \src "libresoc.v:200486.18-200486.106" + wire $not$libresoc.v:200486$14385_Y + attribute \src "libresoc.v:200492.18-200492.121" + wire $not$libresoc.v:200492$14391_Y + attribute \src "libresoc.v:200507.17-200507.113" + wire width 4 $not$libresoc.v:200507$14406_Y + attribute \src "libresoc.v:200523.18-200523.114" + wire width 4 $not$libresoc.v:200523$14422_Y + attribute \src "libresoc.v:200490.18-200490.112" + wire $or$libresoc.v:200490$14389_Y + attribute \src "libresoc.v:200501.18-200501.122" + wire $or$libresoc.v:200501$14400_Y + attribute \src "libresoc.v:200502.18-200502.124" + wire $or$libresoc.v:200502$14401_Y + attribute \src "libresoc.v:200503.18-200503.181" + wire width 5 $or$libresoc.v:200503$14402_Y + attribute \src "libresoc.v:200504.18-200504.168" + wire width 4 $or$libresoc.v:200504$14403_Y + attribute \src "libresoc.v:200508.18-200508.120" + wire width 5 $or$libresoc.v:200508$14407_Y + attribute \src "libresoc.v:200518.17-200518.117" + wire width 4 $or$libresoc.v:200518$14417_Y + attribute \src "libresoc.v:200463.17-200463.104" + wire $reduce_and$libresoc.v:200463$14362_Y + attribute \src "libresoc.v:200485.18-200485.106" + wire $reduce_or$libresoc.v:200485$14384_Y + attribute \src "libresoc.v:200488.18-200488.113" + wire $reduce_or$libresoc.v:200488$14387_Y + attribute \src "libresoc.v:200489.18-200489.112" + wire $reduce_or$libresoc.v:200489$14388_Y + attribute \src "libresoc.v:200514.18-200514.118" + wire width 64 $ternary$libresoc.v:200514$14413_Y + attribute \src "libresoc.v:200515.18-200515.118" + wire width 64 $ternary$libresoc.v:200515$14414_Y + attribute \src "libresoc.v:200516.18-200516.118" + wire width 64 $ternary$libresoc.v:200516$14415_Y + attribute \src "libresoc.v:200517.18-200517.118" + wire width 64 $ternary$libresoc.v:200517$14416_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -413472,9 +417495,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -413552,7 +417575,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:197550.7-197550.15" + attribute \src "libresoc.v:199863.7-199863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -413757,7 +417780,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198151$14178 + cell $and $and$libresoc.v:200464$14363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413765,10 +417788,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:198151$14178_Y + connect \Y $and$libresoc.v:200464$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198152$14179 + cell $and $and$libresoc.v:200465$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413776,10 +417799,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198152$14179_Y + connect \Y $and$libresoc.v:200465$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198153$14180 + cell $and $and$libresoc.v:200466$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413787,10 +417810,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198153$14180_Y + connect \Y $and$libresoc.v:200466$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198154$14181 + cell $and $and$libresoc.v:200467$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413798,10 +417821,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198154$14181_Y + connect \Y $and$libresoc.v:200467$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198155$14182 + cell $and $and$libresoc.v:200468$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413809,10 +417832,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198155$14182_Y + connect \Y $and$libresoc.v:200468$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198156$14183 + cell $and $and$libresoc.v:200469$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413820,10 +417843,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198156$14183_Y + connect \Y $and$libresoc.v:200469$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:198157$14184 + cell $and $and$libresoc.v:200470$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413831,10 +417854,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:198157$14184_Y + connect \Y $and$libresoc.v:200470$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:198158$14185 + cell $and $and$libresoc.v:200471$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413842,10 +417865,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198158$14185_Y + connect \Y $and$libresoc.v:200471$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198159$14186 + cell $and $and$libresoc.v:200472$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413853,10 +417876,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198159$14186_Y + connect \Y $and$libresoc.v:200472$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198160$14187 + cell $and $and$libresoc.v:200473$14372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413864,10 +417887,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198160$14187_Y + connect \Y $and$libresoc.v:200473$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:198161$14188 + cell $and $and$libresoc.v:200474$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413875,10 +417898,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:198161$14188_Y + connect \Y $and$libresoc.v:200474$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198162$14189 + cell $and $and$libresoc.v:200475$14374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413886,10 +417909,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198162$14189_Y + connect \Y $and$libresoc.v:200475$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198163$14190 + cell $and $and$libresoc.v:200476$14375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413897,10 +417920,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198163$14190_Y + connect \Y $and$libresoc.v:200476$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198164$14191 + cell $and $and$libresoc.v:200477$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413908,10 +417931,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198164$14191_Y + connect \Y $and$libresoc.v:200477$14376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:198166$14193 + cell $and $and$libresoc.v:200479$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413919,10 +417942,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:198166$14193_Y + connect \Y $and$libresoc.v:200479$14378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:198168$14195 + cell $and $and$libresoc.v:200481$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413930,10 +417953,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:198168$14195_Y + connect \Y $and$libresoc.v:200481$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:198169$14196 + cell $and $and$libresoc.v:200482$14381 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413941,10 +417964,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:198169$14196_Y + connect \Y $and$libresoc.v:200482$14381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:198171$14198 + cell $and $and$libresoc.v:200484$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413952,10 +417975,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:198171$14198_Y + connect \Y $and$libresoc.v:200484$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:198174$14201 + cell $and $and$libresoc.v:200487$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413963,10 +417986,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:198174$14201_Y + connect \Y $and$libresoc.v:200487$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:198178$14205 + cell $and $and$libresoc.v:200491$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413974,10 +417997,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:198178$14205_Y + connect \Y $and$libresoc.v:200491$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:198180$14207 + cell $and $and$libresoc.v:200493$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413985,10 +418008,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:198180$14207_Y + connect \Y $and$libresoc.v:200493$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:198181$14208 + cell $and $and$libresoc.v:200494$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413996,10 +418019,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198181$14208_Y + connect \Y $and$libresoc.v:200494$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:198183$14210 + cell $and $and$libresoc.v:200496$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414007,10 +418030,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:198183$14210_Y + connect \Y $and$libresoc.v:200496$14395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198185$14212 + cell $and $and$libresoc.v:200498$14397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414018,10 +418041,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:198185$14212_Y + connect \Y $and$libresoc.v:200498$14397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198186$14213 + cell $and $and$libresoc.v:200499$14398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414029,10 +418052,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:198186$14213_Y + connect \Y $and$libresoc.v:200499$14398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198187$14214 + cell $and $and$libresoc.v:200500$14399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414040,10 +418063,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:198187$14214_Y + connect \Y $and$libresoc.v:200500$14399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:198192$14219 + cell $and $and$libresoc.v:200505$14404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414051,10 +418074,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:198192$14219_Y + connect \Y $and$libresoc.v:200505$14404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:198193$14220 + cell $and $and$libresoc.v:200506$14405 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414062,10 +418085,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198193$14220_Y + connect \Y $and$libresoc.v:200506$14405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198196$14223 + cell $and $and$libresoc.v:200509$14408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414073,10 +418096,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198196$14223_Y + connect \Y $and$libresoc.v:200509$14408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198197$14224 + cell $and $and$libresoc.v:200510$14409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414084,10 +418107,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198197$14224_Y + connect \Y $and$libresoc.v:200510$14409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198198$14225 + cell $and $and$libresoc.v:200511$14410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414095,10 +418118,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198198$14225_Y + connect \Y $and$libresoc.v:200511$14410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198199$14226 + cell $and $and$libresoc.v:200512$14411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414106,10 +418129,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198199$14226_Y + connect \Y $and$libresoc.v:200512$14411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198200$14227 + cell $and $and$libresoc.v:200513$14412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414117,10 +418140,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198200$14227_Y + connect \Y $and$libresoc.v:200513$14412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:198206$14233 + cell $and $and$libresoc.v:200519$14418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414128,10 +418151,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:198206$14233_Y + connect \Y $and$libresoc.v:200519$14418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:198207$14234 + cell $and $and$libresoc.v:200520$14419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414139,10 +418162,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:198207$14234_Y + connect \Y $and$libresoc.v:200520$14419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198208$14235 + cell $and $and$libresoc.v:200521$14420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414150,10 +418173,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:198208$14235_Y + connect \Y $and$libresoc.v:200521$14420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198209$14236 + cell $and $and$libresoc.v:200522$14421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414161,10 +418184,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:198209$14236_Y + connect \Y $and$libresoc.v:200522$14421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:198182$14209 + cell $eq $eq$libresoc.v:200495$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414172,10 +418195,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:198182$14209_Y + connect \Y $eq$libresoc.v:200495$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:198184$14211 + cell $eq $eq$libresoc.v:200497$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414183,66 +418206,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:198184$14211_Y + connect \Y $eq$libresoc.v:200497$14396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:198165$14192 + cell $not $not$libresoc.v:200478$14377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:198165$14192_Y + connect \Y $not$libresoc.v:200478$14377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:198167$14194 + cell $not $not$libresoc.v:200480$14379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:198167$14194_Y + connect \Y $not$libresoc.v:200480$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:198170$14197 + cell $not $not$libresoc.v:200483$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:198170$14197_Y + connect \Y $not$libresoc.v:200483$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:198173$14200 + cell $not $not$libresoc.v:200486$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:198173$14200_Y + connect \Y $not$libresoc.v:200486$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:198179$14206 + cell $not $not$libresoc.v:200492$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:198179$14206_Y + connect \Y $not$libresoc.v:200492$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:198194$14221 + cell $not $not$libresoc.v:200507$14406 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:198194$14221_Y + connect \Y $not$libresoc.v:200507$14406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:198210$14237 + cell $not $not$libresoc.v:200523$14422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:198210$14237_Y + connect \Y $not$libresoc.v:200523$14422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:198177$14204 + cell $or $or$libresoc.v:200490$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414250,10 +418273,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:198177$14204_Y + connect \Y $or$libresoc.v:200490$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:198188$14215 + cell $or $or$libresoc.v:200501$14400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414261,10 +418284,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:198188$14215_Y + connect \Y $or$libresoc.v:200501$14400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:198189$14216 + cell $or $or$libresoc.v:200502$14401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414272,10 +418295,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:198189$14216_Y + connect \Y $or$libresoc.v:200502$14401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:198190$14217 + cell $or $or$libresoc.v:200503$14402 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414283,10 +418306,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:198190$14217_Y + connect \Y $or$libresoc.v:200503$14402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:198191$14218 + cell $or $or$libresoc.v:200504$14403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414294,10 +418317,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:198191$14218_Y + connect \Y $or$libresoc.v:200504$14403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:198195$14222 + cell $or $or$libresoc.v:200508$14407 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414305,10 +418328,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:198195$14222_Y + connect \Y $or$libresoc.v:200508$14407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:198205$14232 + cell $or $or$libresoc.v:200518$14417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414316,74 +418339,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:198205$14232_Y + connect \Y $or$libresoc.v:200518$14417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:198150$14177 + cell $reduce_and $reduce_and$libresoc.v:200463$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:198150$14177_Y + connect \Y $reduce_and$libresoc.v:200463$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:198172$14199 + cell $reduce_or $reduce_or$libresoc.v:200485$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:198172$14199_Y + connect \Y $reduce_or$libresoc.v:200485$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:198175$14202 + cell $reduce_or $reduce_or$libresoc.v:200488$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:198175$14202_Y + connect \Y $reduce_or$libresoc.v:200488$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:198176$14203 + cell $reduce_or $reduce_or$libresoc.v:200489$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:198176$14203_Y + connect \Y $reduce_or$libresoc.v:200489$14388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198201$14228 + cell $mux $ternary$libresoc.v:200514$14413 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:198201$14228_Y + connect \Y $ternary$libresoc.v:200514$14413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198202$14229 + cell $mux $ternary$libresoc.v:200515$14414 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:198202$14229_Y + connect \Y $ternary$libresoc.v:200515$14414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198203$14230 + cell $mux $ternary$libresoc.v:200516$14415 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:198203$14230_Y + connect \Y $ternary$libresoc.v:200516$14415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198204$14231 + cell $mux $ternary$libresoc.v:200517$14416 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:198204$14231_Y + connect \Y $ternary$libresoc.v:200517$14416_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:198287.14-198293.4" + attribute \src "libresoc.v:200600.14-200606.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414392,7 +418415,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:198294.13-198324.4" + attribute \src "libresoc.v:200607.13-200637.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414425,7 +418448,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:198325.15-198331.4" + attribute \src "libresoc.v:200638.15-200644.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414434,7 +418457,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:198332.14-198338.4" + attribute \src "libresoc.v:200645.14-200651.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414443,7 +418466,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:198339.14-198345.4" + attribute \src "libresoc.v:200652.14-200658.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414452,7 +418475,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:198346.14-198352.4" + attribute \src "libresoc.v:200659.14-200665.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414461,7 +418484,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:198353.14-198358.4" + attribute \src "libresoc.v:200666.14-200671.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414469,7 +418492,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:198359.14-198365.4" + attribute \src "libresoc.v:200672.14-200678.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414477,592 +418500,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:197550.7-197550.20" - process $proc$libresoc.v:197550$14392 + attribute \src "libresoc.v:199863.7-199863.20" + process $proc$libresoc.v:199863$14577 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:197676.7-197676.24" - process $proc$libresoc.v:197676$14393 + attribute \src "libresoc.v:199989.7-199989.24" + process $proc$libresoc.v:199989$14578 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:197686.7-197686.26" - process $proc$libresoc.v:197686$14394 + attribute \src "libresoc.v:199999.7-199999.26" + process $proc$libresoc.v:199999$14579 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:197694.7-197694.25" - process $proc$libresoc.v:197694$14395 + attribute \src "libresoc.v:200007.7-200007.25" + process $proc$libresoc.v:200007$14580 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:197730.14-197730.59" - process $proc$libresoc.v:197730$14396 + attribute \src "libresoc.v:200043.14-200043.59" + process $proc$libresoc.v:200043$14581 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:197749.14-197749.51" - process $proc$libresoc.v:197749$14397 + attribute \src "libresoc.v:200062.14-200062.51" + process $proc$libresoc.v:200062$14582 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:197753.14-197753.45" - process $proc$libresoc.v:197753$14398 + attribute \src "libresoc.v:200066.14-200066.45" + process $proc$libresoc.v:200066$14583 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:197832.13-197832.49" - process $proc$libresoc.v:197832$14399 + attribute \src "libresoc.v:200145.13-200145.49" + process $proc$libresoc.v:200145$14584 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:197836.7-197836.41" - process $proc$libresoc.v:197836$14400 + attribute \src "libresoc.v:200149.7-200149.41" + process $proc$libresoc.v:200149$14585 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:197840.13-197840.48" - process $proc$libresoc.v:197840$14401 + attribute \src "libresoc.v:200153.13-200153.48" + process $proc$libresoc.v:200153$14586 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:197844.14-197844.59" - process $proc$libresoc.v:197844$14402 + attribute \src "libresoc.v:200157.14-200157.59" + process $proc$libresoc.v:200157$14587 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:197848.14-197848.52" - process $proc$libresoc.v:197848$14403 + attribute \src "libresoc.v:200161.14-200161.52" + process $proc$libresoc.v:200161$14588 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:197852.13-197852.48" - process $proc$libresoc.v:197852$14404 + attribute \src "libresoc.v:200165.13-200165.48" + process $proc$libresoc.v:200165$14589 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:197858.7-197858.27" - process $proc$libresoc.v:197858$14405 + attribute \src "libresoc.v:200171.7-200171.27" + process $proc$libresoc.v:200171$14590 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:197890.14-197890.47" - process $proc$libresoc.v:197890$14406 + attribute \src "libresoc.v:200203.14-200203.47" + process $proc$libresoc.v:200203$14591 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:197894.7-197894.27" - process $proc$libresoc.v:197894$14407 + attribute \src "libresoc.v:200207.7-200207.27" + process $proc$libresoc.v:200207$14592 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:197898.14-197898.51" - process $proc$libresoc.v:197898$14408 + attribute \src "libresoc.v:200211.14-200211.51" + process $proc$libresoc.v:200211$14593 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:197902.7-197902.31" - process $proc$libresoc.v:197902$14409 + attribute \src "libresoc.v:200215.7-200215.31" + process $proc$libresoc.v:200215$14594 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:197906.14-197906.51" - process $proc$libresoc.v:197906$14410 + attribute \src "libresoc.v:200219.14-200219.51" + process $proc$libresoc.v:200219$14595 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:197910.7-197910.31" - process $proc$libresoc.v:197910$14411 + attribute \src "libresoc.v:200223.7-200223.31" + process $proc$libresoc.v:200223$14596 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:197914.14-197914.49" - process $proc$libresoc.v:197914$14412 + attribute \src "libresoc.v:200227.14-200227.49" + process $proc$libresoc.v:200227$14597 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:197918.7-197918.29" - process $proc$libresoc.v:197918$14413 + attribute \src "libresoc.v:200231.7-200231.29" + process $proc$libresoc.v:200231$14598 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:197922.14-197922.49" - process $proc$libresoc.v:197922$14414 + attribute \src "libresoc.v:200235.14-200235.49" + process $proc$libresoc.v:200235$14599 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:197926.7-197926.29" - process $proc$libresoc.v:197926$14415 + attribute \src "libresoc.v:200239.7-200239.29" + process $proc$libresoc.v:200239$14600 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:197957.7-197957.25" - process $proc$libresoc.v:197957$14416 + attribute \src "libresoc.v:200270.7-200270.25" + process $proc$libresoc.v:200270$14601 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:197961.7-197961.25" - process $proc$libresoc.v:197961$14417 + attribute \src "libresoc.v:200274.7-200274.25" + process $proc$libresoc.v:200274$14602 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:198073.13-198073.31" - process $proc$libresoc.v:198073$14418 + attribute \src "libresoc.v:200386.13-200386.31" + process $proc$libresoc.v:200386$14603 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:198081.13-198081.32" - process $proc$libresoc.v:198081$14419 + attribute \src "libresoc.v:200394.13-200394.32" + process $proc$libresoc.v:200394$14604 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:198085.13-198085.32" - process $proc$libresoc.v:198085$14420 + attribute \src "libresoc.v:200398.13-200398.32" + process $proc$libresoc.v:200398$14605 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:198097.7-198097.26" - process $proc$libresoc.v:198097$14421 + attribute \src "libresoc.v:200410.7-200410.26" + process $proc$libresoc.v:200410$14606 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:198101.7-198101.26" - process $proc$libresoc.v:198101$14422 + attribute \src "libresoc.v:200414.7-200414.26" + process $proc$libresoc.v:200414$14607 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:198105.7-198105.25" - process $proc$libresoc.v:198105$14423 + attribute \src "libresoc.v:200418.7-200418.25" + process $proc$libresoc.v:200418$14608 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:198109.7-198109.25" - process $proc$libresoc.v:198109$14424 + attribute \src "libresoc.v:200422.7-200422.25" + process $proc$libresoc.v:200422$14609 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:198125.13-198125.31" - process $proc$libresoc.v:198125$14425 + attribute \src "libresoc.v:200438.13-200438.31" + process $proc$libresoc.v:200438$14610 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:198129.13-198129.31" - process $proc$libresoc.v:198129$14426 + attribute \src "libresoc.v:200442.13-200442.31" + process $proc$libresoc.v:200442$14611 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:198133.14-198133.43" - process $proc$libresoc.v:198133$14427 + attribute \src "libresoc.v:200446.14-200446.43" + process $proc$libresoc.v:200446$14612 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:198137.14-198137.43" - process $proc$libresoc.v:198137$14428 + attribute \src "libresoc.v:200450.14-200450.43" + process $proc$libresoc.v:200450$14613 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:198141.14-198141.43" - process $proc$libresoc.v:198141$14429 + attribute \src "libresoc.v:200454.14-200454.43" + process $proc$libresoc.v:200454$14614 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:198145.14-198145.43" - process $proc$libresoc.v:198145$14430 + attribute \src "libresoc.v:200458.14-200458.43" + process $proc$libresoc.v:200458$14615 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:198211.3-198212.39" - process $proc$libresoc.v:198211$14238 + attribute \src "libresoc.v:200524.3-200525.39" + process $proc$libresoc.v:200524$14423 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:198213.3-198214.43" - process $proc$libresoc.v:198213$14239 + attribute \src "libresoc.v:200526.3-200527.43" + process $proc$libresoc.v:200526$14424 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:198215.3-198216.29" - process $proc$libresoc.v:198215$14240 + attribute \src "libresoc.v:200528.3-200529.29" + process $proc$libresoc.v:200528$14425 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:198217.3-198218.29" - process $proc$libresoc.v:198217$14241 + attribute \src "libresoc.v:200530.3-200531.29" + process $proc$libresoc.v:200530$14426 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:198219.3-198220.29" - process $proc$libresoc.v:198219$14242 + attribute \src "libresoc.v:200532.3-200533.29" + process $proc$libresoc.v:200532$14427 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:198221.3-198222.29" - process $proc$libresoc.v:198221$14243 + attribute \src "libresoc.v:200534.3-200535.29" + process $proc$libresoc.v:200534$14428 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:198223.3-198224.41" - process $proc$libresoc.v:198223$14244 + attribute \src "libresoc.v:200536.3-200537.41" + process $proc$libresoc.v:200536$14429 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:198225.3-198226.47" - process $proc$libresoc.v:198225$14245 + attribute \src "libresoc.v:200538.3-200539.47" + process $proc$libresoc.v:200538$14430 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:198227.3-198228.41" - process $proc$libresoc.v:198227$14246 + attribute \src "libresoc.v:200540.3-200541.41" + process $proc$libresoc.v:200540$14431 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:198229.3-198230.47" - process $proc$libresoc.v:198229$14247 + attribute \src "libresoc.v:200542.3-200543.47" + process $proc$libresoc.v:200542$14432 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:198231.3-198232.45" - process $proc$libresoc.v:198231$14248 + attribute \src "libresoc.v:200544.3-200545.45" + process $proc$libresoc.v:200544$14433 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:198233.3-198234.51" - process $proc$libresoc.v:198233$14249 + attribute \src "libresoc.v:200546.3-200547.51" + process $proc$libresoc.v:200546$14434 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:198235.3-198236.45" - process $proc$libresoc.v:198235$14250 + attribute \src "libresoc.v:200548.3-200549.45" + process $proc$libresoc.v:200548$14435 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:198237.3-198238.51" - process $proc$libresoc.v:198237$14251 + attribute \src "libresoc.v:200550.3-200551.51" + process $proc$libresoc.v:200550$14436 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:198239.3-198240.37" - process $proc$libresoc.v:198239$14252 + attribute \src "libresoc.v:200552.3-200553.37" + process $proc$libresoc.v:200552$14437 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:198241.3-198242.43" - process $proc$libresoc.v:198241$14253 + attribute \src "libresoc.v:200554.3-200555.43" + process $proc$libresoc.v:200554$14438 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:198243.3-198244.73" - process $proc$libresoc.v:198243$14254 + attribute \src "libresoc.v:200556.3-200557.73" + process $proc$libresoc.v:200556$14439 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:198245.3-198246.69" - process $proc$libresoc.v:198245$14255 + attribute \src "libresoc.v:200558.3-200559.69" + process $proc$libresoc.v:200558$14440 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:198247.3-198248.63" - process $proc$libresoc.v:198247$14256 + attribute \src "libresoc.v:200560.3-200561.63" + process $proc$libresoc.v:200560$14441 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:198249.3-198250.61" - process $proc$libresoc.v:198249$14257 + attribute \src "libresoc.v:200562.3-200563.61" + process $proc$libresoc.v:200562$14442 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:198251.3-198252.61" - process $proc$libresoc.v:198251$14258 + attribute \src "libresoc.v:200564.3-200565.61" + process $proc$libresoc.v:200564$14443 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:198253.3-198254.71" - process $proc$libresoc.v:198253$14259 + attribute \src "libresoc.v:200566.3-200567.71" + process $proc$libresoc.v:200566$14444 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:198255.3-198256.71" - process $proc$libresoc.v:198255$14260 + attribute \src "libresoc.v:200568.3-200569.71" + process $proc$libresoc.v:200568$14445 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:198257.3-198258.71" - process $proc$libresoc.v:198257$14261 + attribute \src "libresoc.v:200570.3-200571.71" + process $proc$libresoc.v:200570$14446 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:198259.3-198260.71" - process $proc$libresoc.v:198259$14262 + attribute \src "libresoc.v:200572.3-200573.71" + process $proc$libresoc.v:200572$14447 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:198261.3-198262.39" - process $proc$libresoc.v:198261$14263 + attribute \src "libresoc.v:200574.3-200575.39" + process $proc$libresoc.v:200574$14448 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:198263.3-198264.39" - process $proc$libresoc.v:198263$14264 + attribute \src "libresoc.v:200576.3-200577.39" + process $proc$libresoc.v:200576$14449 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:198265.3-198266.39" - process $proc$libresoc.v:198265$14265 + attribute \src "libresoc.v:200578.3-200579.39" + process $proc$libresoc.v:200578$14450 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:198267.3-198268.39" - process $proc$libresoc.v:198267$14266 + attribute \src "libresoc.v:200580.3-200581.39" + process $proc$libresoc.v:200580$14451 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:198269.3-198270.39" - process $proc$libresoc.v:198269$14267 + attribute \src "libresoc.v:200582.3-200583.39" + process $proc$libresoc.v:200582$14452 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:198271.3-198272.39" - process $proc$libresoc.v:198271$14268 + attribute \src "libresoc.v:200584.3-200585.39" + process $proc$libresoc.v:200584$14453 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:198273.3-198274.39" - process $proc$libresoc.v:198273$14269 + attribute \src "libresoc.v:200586.3-200587.39" + process $proc$libresoc.v:200586$14454 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:198275.3-198276.39" - process $proc$libresoc.v:198275$14270 + attribute \src "libresoc.v:200588.3-200589.39" + process $proc$libresoc.v:200588$14455 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:198277.3-198278.41" - process $proc$libresoc.v:198277$14271 + attribute \src "libresoc.v:200590.3-200591.41" + process $proc$libresoc.v:200590$14456 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:198279.3-198280.41" - process $proc$libresoc.v:198279$14272 + attribute \src "libresoc.v:200592.3-200593.41" + process $proc$libresoc.v:200592$14457 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:198281.3-198282.37" - process $proc$libresoc.v:198281$14273 + attribute \src "libresoc.v:200594.3-200595.37" + process $proc$libresoc.v:200594$14458 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:198283.3-198284.41" - process $proc$libresoc.v:198283$14274 + attribute \src "libresoc.v:200596.3-200597.41" + process $proc$libresoc.v:200596$14459 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:198285.3-198286.25" - process $proc$libresoc.v:198285$14275 + attribute \src "libresoc.v:200598.3-200599.25" + process $proc$libresoc.v:200598$14460 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:198366.3-198375.6" - process $proc$libresoc.v:198366$14276 + attribute \src "libresoc.v:200679.3-200688.6" + process $proc$libresoc.v:200679$14461 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:198367.5-198367.29" + attribute \src "libresoc.v:200680.5-200680.29" switch \initial - attribute \src "libresoc.v:198367.9-198367.17" + attribute \src "libresoc.v:200680.9-200680.17" case 1'1 case end @@ -415078,14 +419101,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:198376.3-198384.6" - process $proc$libresoc.v:198376$14277 + attribute \src "libresoc.v:200689.3-200697.6" + process $proc$libresoc.v:200689$14462 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14278 $1\rok_l_s_rdok$next[0:0]$14279 - attribute \src "libresoc.v:198377.5-198377.29" + assign $0\rok_l_s_rdok$next[0:0]$14463 $1\rok_l_s_rdok$next[0:0]$14464 + attribute \src "libresoc.v:200690.5-200690.29" switch \initial - attribute \src "libresoc.v:198377.9-198377.17" + attribute \src "libresoc.v:200690.9-200690.17" case 1'1 case end @@ -415094,21 +419117,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14279 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14464 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14279 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14464 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14278 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14463 end - attribute \src "libresoc.v:198385.3-198393.6" - process $proc$libresoc.v:198385$14280 + attribute \src "libresoc.v:200698.3-200706.6" + process $proc$libresoc.v:200698$14465 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14281 $1\rok_l_r_rdok$next[0:0]$14282 - attribute \src "libresoc.v:198386.5-198386.29" + assign $0\rok_l_r_rdok$next[0:0]$14466 $1\rok_l_r_rdok$next[0:0]$14467 + attribute \src "libresoc.v:200699.5-200699.29" switch \initial - attribute \src "libresoc.v:198386.9-198386.17" + attribute \src "libresoc.v:200699.9-200699.17" case 1'1 case end @@ -415117,21 +419140,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14282 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14467 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14282 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14467 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14281 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14466 end - attribute \src "libresoc.v:198394.3-198402.6" - process $proc$libresoc.v:198394$14283 + attribute \src "libresoc.v:200707.3-200715.6" + process $proc$libresoc.v:200707$14468 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14284 $1\rst_l_s_rst$next[0:0]$14285 - attribute \src "libresoc.v:198395.5-198395.29" + assign $0\rst_l_s_rst$next[0:0]$14469 $1\rst_l_s_rst$next[0:0]$14470 + attribute \src "libresoc.v:200708.5-200708.29" switch \initial - attribute \src "libresoc.v:198395.9-198395.17" + attribute \src "libresoc.v:200708.9-200708.17" case 1'1 case end @@ -415140,21 +419163,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14285 1'0 + assign $1\rst_l_s_rst$next[0:0]$14470 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14285 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14470 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14284 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14469 end - attribute \src "libresoc.v:198403.3-198411.6" - process $proc$libresoc.v:198403$14286 + attribute \src "libresoc.v:200716.3-200724.6" + process $proc$libresoc.v:200716$14471 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14287 $1\rst_l_r_rst$next[0:0]$14288 - attribute \src "libresoc.v:198404.5-198404.29" + assign $0\rst_l_r_rst$next[0:0]$14472 $1\rst_l_r_rst$next[0:0]$14473 + attribute \src "libresoc.v:200717.5-200717.29" switch \initial - attribute \src "libresoc.v:198404.9-198404.17" + attribute \src "libresoc.v:200717.9-200717.17" case 1'1 case end @@ -415163,21 +419186,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14288 1'1 + assign $1\rst_l_r_rst$next[0:0]$14473 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14288 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14473 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14287 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14472 end - attribute \src "libresoc.v:198412.3-198420.6" - process $proc$libresoc.v:198412$14289 + attribute \src "libresoc.v:200725.3-200733.6" + process $proc$libresoc.v:200725$14474 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14290 $1\opc_l_s_opc$next[0:0]$14291 - attribute \src "libresoc.v:198413.5-198413.29" + assign $0\opc_l_s_opc$next[0:0]$14475 $1\opc_l_s_opc$next[0:0]$14476 + attribute \src "libresoc.v:200726.5-200726.29" switch \initial - attribute \src "libresoc.v:198413.9-198413.17" + attribute \src "libresoc.v:200726.9-200726.17" case 1'1 case end @@ -415186,21 +419209,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14291 1'0 + assign $1\opc_l_s_opc$next[0:0]$14476 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14291 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14476 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14290 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14475 end - attribute \src "libresoc.v:198421.3-198429.6" - process $proc$libresoc.v:198421$14292 + attribute \src "libresoc.v:200734.3-200742.6" + process $proc$libresoc.v:200734$14477 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14293 $1\opc_l_r_opc$next[0:0]$14294 - attribute \src "libresoc.v:198422.5-198422.29" + assign $0\opc_l_r_opc$next[0:0]$14478 $1\opc_l_r_opc$next[0:0]$14479 + attribute \src "libresoc.v:200735.5-200735.29" switch \initial - attribute \src "libresoc.v:198422.9-198422.17" + attribute \src "libresoc.v:200735.9-200735.17" case 1'1 case end @@ -415209,21 +419232,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14294 1'1 + assign $1\opc_l_r_opc$next[0:0]$14479 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14294 \req_done + assign $1\opc_l_r_opc$next[0:0]$14479 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14293 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14478 end - attribute \src "libresoc.v:198430.3-198438.6" - process $proc$libresoc.v:198430$14295 + attribute \src "libresoc.v:200743.3-200751.6" + process $proc$libresoc.v:200743$14480 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14296 $1\src_l_s_src$next[3:0]$14297 - attribute \src "libresoc.v:198431.5-198431.29" + assign $0\src_l_s_src$next[3:0]$14481 $1\src_l_s_src$next[3:0]$14482 + attribute \src "libresoc.v:200744.5-200744.29" switch \initial - attribute \src "libresoc.v:198431.9-198431.17" + attribute \src "libresoc.v:200744.9-200744.17" case 1'1 case end @@ -415232,21 +419255,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14297 4'0000 + assign $1\src_l_s_src$next[3:0]$14482 4'0000 case - assign $1\src_l_s_src$next[3:0]$14297 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14482 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14296 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14481 end - attribute \src "libresoc.v:198439.3-198447.6" - process $proc$libresoc.v:198439$14298 + attribute \src "libresoc.v:200752.3-200760.6" + process $proc$libresoc.v:200752$14483 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14299 $1\src_l_r_src$next[3:0]$14300 - attribute \src "libresoc.v:198440.5-198440.29" + assign $0\src_l_r_src$next[3:0]$14484 $1\src_l_r_src$next[3:0]$14485 + attribute \src "libresoc.v:200753.5-200753.29" switch \initial - attribute \src "libresoc.v:198440.9-198440.17" + attribute \src "libresoc.v:200753.9-200753.17" case 1'1 case end @@ -415255,21 +419278,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14300 4'1111 + assign $1\src_l_r_src$next[3:0]$14485 4'1111 case - assign $1\src_l_r_src$next[3:0]$14300 \reset_r + assign $1\src_l_r_src$next[3:0]$14485 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14299 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14484 end - attribute \src "libresoc.v:198448.3-198456.6" - process $proc$libresoc.v:198448$14301 + attribute \src "libresoc.v:200761.3-200769.6" + process $proc$libresoc.v:200761$14486 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14302 $1\req_l_s_req$next[4:0]$14303 - attribute \src "libresoc.v:198449.5-198449.29" + assign $0\req_l_s_req$next[4:0]$14487 $1\req_l_s_req$next[4:0]$14488 + attribute \src "libresoc.v:200762.5-200762.29" switch \initial - attribute \src "libresoc.v:198449.9-198449.17" + attribute \src "libresoc.v:200762.9-200762.17" case 1'1 case end @@ -415278,21 +419301,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14303 5'00000 + assign $1\req_l_s_req$next[4:0]$14488 5'00000 case - assign $1\req_l_s_req$next[4:0]$14303 \$67 + assign $1\req_l_s_req$next[4:0]$14488 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14302 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14487 end - attribute \src "libresoc.v:198457.3-198465.6" - process $proc$libresoc.v:198457$14304 + attribute \src "libresoc.v:200770.3-200778.6" + process $proc$libresoc.v:200770$14489 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14305 $1\req_l_r_req$next[4:0]$14306 - attribute \src "libresoc.v:198458.5-198458.29" + assign $0\req_l_r_req$next[4:0]$14490 $1\req_l_r_req$next[4:0]$14491 + attribute \src "libresoc.v:200771.5-200771.29" switch \initial - attribute \src "libresoc.v:198458.9-198458.17" + attribute \src "libresoc.v:200771.9-200771.17" case 1'1 case end @@ -415301,15 +419324,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14306 5'11111 + assign $1\req_l_r_req$next[4:0]$14491 5'11111 case - assign $1\req_l_r_req$next[4:0]$14306 \$69 + assign $1\req_l_r_req$next[4:0]$14491 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14305 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14490 end - attribute \src "libresoc.v:198466.3-198483.6" - process $proc$libresoc.v:198466$14307 + attribute \src "libresoc.v:200779.3-200796.6" + process $proc$libresoc.v:200779$14492 assign { } { } assign { } { } assign { } { } @@ -415328,18 +419351,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14308 $1\alu_trap0_trap_op__cia$next[63:0]$14317 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14310 $1\alu_trap0_trap_op__insn$next[31:0]$14319 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14314 $1\alu_trap0_trap_op__msr$next[63:0]$14323 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14316 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 - attribute \src "libresoc.v:198467.5-198467.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14493 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14495 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14499 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14501 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 + attribute \src "libresoc.v:200780.5-200780.29" switch \initial - attribute \src "libresoc.v:198467.9-198467.17" + attribute \src "libresoc.v:200780.9-200780.17" case 1'1 case end @@ -415356,43 +419379,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 $1\alu_trap0_trap_op__cia$next[63:0]$14317 $1\alu_trap0_trap_op__msr$next[63:0]$14323 $1\alu_trap0_trap_op__insn$next[31:0]$14319 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 $1\alu_trap0_trap_op__cia$next[63:0]$14502 $1\alu_trap0_trap_op__msr$next[63:0]$14508 $1\alu_trap0_trap_op__insn$next[31:0]$14504 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14317 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14319 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14323 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14325 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14502 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14504 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14508 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14510 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14308 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14310 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14314 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14316 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14493 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14495 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14499 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14501 end - attribute \src "libresoc.v:198484.3-198505.6" - process $proc$libresoc.v:198484$14326 + attribute \src "libresoc.v:200797.3-200818.6" + process $proc$libresoc.v:200797$14511 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14327 $2\data_r0__o$next[63:0]$14331 + assign $0\data_r0__o$next[63:0]$14512 $2\data_r0__o$next[63:0]$14516 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14328 $3\data_r0__o_ok$next[0:0]$14333 - attribute \src "libresoc.v:198485.5-198485.29" + assign $0\data_r0__o_ok$next[0:0]$14513 $3\data_r0__o_ok$next[0:0]$14518 + attribute \src "libresoc.v:200798.5-200798.29" switch \initial - attribute \src "libresoc.v:198485.9-198485.17" + attribute \src "libresoc.v:200798.9-200798.17" case 1'1 case end @@ -415402,10 +419425,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14330 $1\data_r0__o$next[63:0]$14329 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14515 $1\data_r0__o$next[63:0]$14514 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14329 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14330 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14514 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14515 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415413,38 +419436,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14332 $2\data_r0__o$next[63:0]$14331 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14517 $2\data_r0__o$next[63:0]$14516 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14331 $1\data_r0__o$next[63:0]$14329 - assign $2\data_r0__o_ok$next[0:0]$14332 $1\data_r0__o_ok$next[0:0]$14330 + assign $2\data_r0__o$next[63:0]$14516 $1\data_r0__o$next[63:0]$14514 + assign $2\data_r0__o_ok$next[0:0]$14517 $1\data_r0__o_ok$next[0:0]$14515 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14333 1'0 + assign $3\data_r0__o_ok$next[0:0]$14518 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14333 $2\data_r0__o_ok$next[0:0]$14332 + assign $3\data_r0__o_ok$next[0:0]$14518 $2\data_r0__o_ok$next[0:0]$14517 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14327 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14328 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14512 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14513 end - attribute \src "libresoc.v:198506.3-198527.6" - process $proc$libresoc.v:198506$14334 + attribute \src "libresoc.v:200819.3-200840.6" + process $proc$libresoc.v:200819$14519 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14335 $2\data_r1__fast1$next[63:0]$14339 + assign $0\data_r1__fast1$next[63:0]$14520 $2\data_r1__fast1$next[63:0]$14524 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14336 $3\data_r1__fast1_ok$next[0:0]$14341 - attribute \src "libresoc.v:198507.5-198507.29" + assign $0\data_r1__fast1_ok$next[0:0]$14521 $3\data_r1__fast1_ok$next[0:0]$14526 + attribute \src "libresoc.v:200820.5-200820.29" switch \initial - attribute \src "libresoc.v:198507.9-198507.17" + attribute \src "libresoc.v:200820.9-200820.17" case 1'1 case end @@ -415454,10 +419477,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14338 $1\data_r1__fast1$next[63:0]$14337 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14523 $1\data_r1__fast1$next[63:0]$14522 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14337 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14338 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14522 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14523 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415465,38 +419488,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14340 $2\data_r1__fast1$next[63:0]$14339 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14525 $2\data_r1__fast1$next[63:0]$14524 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14339 $1\data_r1__fast1$next[63:0]$14337 - assign $2\data_r1__fast1_ok$next[0:0]$14340 $1\data_r1__fast1_ok$next[0:0]$14338 + assign $2\data_r1__fast1$next[63:0]$14524 $1\data_r1__fast1$next[63:0]$14522 + assign $2\data_r1__fast1_ok$next[0:0]$14525 $1\data_r1__fast1_ok$next[0:0]$14523 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14341 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14526 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14341 $2\data_r1__fast1_ok$next[0:0]$14340 + assign $3\data_r1__fast1_ok$next[0:0]$14526 $2\data_r1__fast1_ok$next[0:0]$14525 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14335 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14336 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14520 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14521 end - attribute \src "libresoc.v:198528.3-198549.6" - process $proc$libresoc.v:198528$14342 + attribute \src "libresoc.v:200841.3-200862.6" + process $proc$libresoc.v:200841$14527 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14343 $2\data_r2__fast2$next[63:0]$14347 + assign $0\data_r2__fast2$next[63:0]$14528 $2\data_r2__fast2$next[63:0]$14532 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14344 $3\data_r2__fast2_ok$next[0:0]$14349 - attribute \src "libresoc.v:198529.5-198529.29" + assign $0\data_r2__fast2_ok$next[0:0]$14529 $3\data_r2__fast2_ok$next[0:0]$14534 + attribute \src "libresoc.v:200842.5-200842.29" switch \initial - attribute \src "libresoc.v:198529.9-198529.17" + attribute \src "libresoc.v:200842.9-200842.17" case 1'1 case end @@ -415506,10 +419529,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14346 $1\data_r2__fast2$next[63:0]$14345 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14531 $1\data_r2__fast2$next[63:0]$14530 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14345 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14346 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14530 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14531 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415517,38 +419540,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14348 $2\data_r2__fast2$next[63:0]$14347 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14533 $2\data_r2__fast2$next[63:0]$14532 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14347 $1\data_r2__fast2$next[63:0]$14345 - assign $2\data_r2__fast2_ok$next[0:0]$14348 $1\data_r2__fast2_ok$next[0:0]$14346 + assign $2\data_r2__fast2$next[63:0]$14532 $1\data_r2__fast2$next[63:0]$14530 + assign $2\data_r2__fast2_ok$next[0:0]$14533 $1\data_r2__fast2_ok$next[0:0]$14531 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14349 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14534 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14349 $2\data_r2__fast2_ok$next[0:0]$14348 + assign $3\data_r2__fast2_ok$next[0:0]$14534 $2\data_r2__fast2_ok$next[0:0]$14533 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14343 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14344 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14528 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14529 end - attribute \src "libresoc.v:198550.3-198571.6" - process $proc$libresoc.v:198550$14350 + attribute \src "libresoc.v:200863.3-200884.6" + process $proc$libresoc.v:200863$14535 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14351 $2\data_r3__nia$next[63:0]$14355 + assign $0\data_r3__nia$next[63:0]$14536 $2\data_r3__nia$next[63:0]$14540 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14352 $3\data_r3__nia_ok$next[0:0]$14357 - attribute \src "libresoc.v:198551.5-198551.29" + assign $0\data_r3__nia_ok$next[0:0]$14537 $3\data_r3__nia_ok$next[0:0]$14542 + attribute \src "libresoc.v:200864.5-200864.29" switch \initial - attribute \src "libresoc.v:198551.9-198551.17" + attribute \src "libresoc.v:200864.9-200864.17" case 1'1 case end @@ -415558,10 +419581,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14354 $1\data_r3__nia$next[63:0]$14353 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14539 $1\data_r3__nia$next[63:0]$14538 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14353 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14354 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14538 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14539 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415569,38 +419592,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14356 $2\data_r3__nia$next[63:0]$14355 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14541 $2\data_r3__nia$next[63:0]$14540 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14355 $1\data_r3__nia$next[63:0]$14353 - assign $2\data_r3__nia_ok$next[0:0]$14356 $1\data_r3__nia_ok$next[0:0]$14354 + assign $2\data_r3__nia$next[63:0]$14540 $1\data_r3__nia$next[63:0]$14538 + assign $2\data_r3__nia_ok$next[0:0]$14541 $1\data_r3__nia_ok$next[0:0]$14539 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14357 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14542 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14357 $2\data_r3__nia_ok$next[0:0]$14356 + assign $3\data_r3__nia_ok$next[0:0]$14542 $2\data_r3__nia_ok$next[0:0]$14541 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14351 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14352 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14536 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14537 end - attribute \src "libresoc.v:198572.3-198593.6" - process $proc$libresoc.v:198572$14358 + attribute \src "libresoc.v:200885.3-200906.6" + process $proc$libresoc.v:200885$14543 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14359 $2\data_r4__msr$next[63:0]$14363 + assign $0\data_r4__msr$next[63:0]$14544 $2\data_r4__msr$next[63:0]$14548 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14360 $3\data_r4__msr_ok$next[0:0]$14365 - attribute \src "libresoc.v:198573.5-198573.29" + assign $0\data_r4__msr_ok$next[0:0]$14545 $3\data_r4__msr_ok$next[0:0]$14550 + attribute \src "libresoc.v:200886.5-200886.29" switch \initial - attribute \src "libresoc.v:198573.9-198573.17" + attribute \src "libresoc.v:200886.9-200886.17" case 1'1 case end @@ -415610,10 +419633,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14362 $1\data_r4__msr$next[63:0]$14361 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14547 $1\data_r4__msr$next[63:0]$14546 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14361 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14362 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14546 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14547 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415621,32 +419644,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14364 $2\data_r4__msr$next[63:0]$14363 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14549 $2\data_r4__msr$next[63:0]$14548 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14363 $1\data_r4__msr$next[63:0]$14361 - assign $2\data_r4__msr_ok$next[0:0]$14364 $1\data_r4__msr_ok$next[0:0]$14362 + assign $2\data_r4__msr$next[63:0]$14548 $1\data_r4__msr$next[63:0]$14546 + assign $2\data_r4__msr_ok$next[0:0]$14549 $1\data_r4__msr_ok$next[0:0]$14547 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14365 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14550 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14365 $2\data_r4__msr_ok$next[0:0]$14364 + assign $3\data_r4__msr_ok$next[0:0]$14550 $2\data_r4__msr_ok$next[0:0]$14549 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14359 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14360 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14544 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14545 end - attribute \src "libresoc.v:198594.3-198603.6" - process $proc$libresoc.v:198594$14366 + attribute \src "libresoc.v:200907.3-200916.6" + process $proc$libresoc.v:200907$14551 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14367 $1\src_r0$next[63:0]$14368 - attribute \src "libresoc.v:198595.5-198595.29" + assign $0\src_r0$next[63:0]$14552 $1\src_r0$next[63:0]$14553 + attribute \src "libresoc.v:200908.5-200908.29" switch \initial - attribute \src "libresoc.v:198595.9-198595.17" + attribute \src "libresoc.v:200908.9-200908.17" case 1'1 case end @@ -415655,21 +419678,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14368 \src1_i + assign $1\src_r0$next[63:0]$14553 \src1_i case - assign $1\src_r0$next[63:0]$14368 \src_r0 + assign $1\src_r0$next[63:0]$14553 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14367 + update \src_r0$next $0\src_r0$next[63:0]$14552 end - attribute \src "libresoc.v:198604.3-198613.6" - process $proc$libresoc.v:198604$14369 + attribute \src "libresoc.v:200917.3-200926.6" + process $proc$libresoc.v:200917$14554 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14370 $1\src_r1$next[63:0]$14371 - attribute \src "libresoc.v:198605.5-198605.29" + assign $0\src_r1$next[63:0]$14555 $1\src_r1$next[63:0]$14556 + attribute \src "libresoc.v:200918.5-200918.29" switch \initial - attribute \src "libresoc.v:198605.9-198605.17" + attribute \src "libresoc.v:200918.9-200918.17" case 1'1 case end @@ -415678,21 +419701,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14371 \src2_i + assign $1\src_r1$next[63:0]$14556 \src2_i case - assign $1\src_r1$next[63:0]$14371 \src_r1 + assign $1\src_r1$next[63:0]$14556 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14370 + update \src_r1$next $0\src_r1$next[63:0]$14555 end - attribute \src "libresoc.v:198614.3-198623.6" - process $proc$libresoc.v:198614$14372 + attribute \src "libresoc.v:200927.3-200936.6" + process $proc$libresoc.v:200927$14557 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14373 $1\src_r2$next[63:0]$14374 - attribute \src "libresoc.v:198615.5-198615.29" + assign $0\src_r2$next[63:0]$14558 $1\src_r2$next[63:0]$14559 + attribute \src "libresoc.v:200928.5-200928.29" switch \initial - attribute \src "libresoc.v:198615.9-198615.17" + attribute \src "libresoc.v:200928.9-200928.17" case 1'1 case end @@ -415701,21 +419724,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14374 \src3_i + assign $1\src_r2$next[63:0]$14559 \src3_i case - assign $1\src_r2$next[63:0]$14374 \src_r2 + assign $1\src_r2$next[63:0]$14559 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14373 + update \src_r2$next $0\src_r2$next[63:0]$14558 end - attribute \src "libresoc.v:198624.3-198633.6" - process $proc$libresoc.v:198624$14375 + attribute \src "libresoc.v:200937.3-200946.6" + process $proc$libresoc.v:200937$14560 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14376 $1\src_r3$next[63:0]$14377 - attribute \src "libresoc.v:198625.5-198625.29" + assign $0\src_r3$next[63:0]$14561 $1\src_r3$next[63:0]$14562 + attribute \src "libresoc.v:200938.5-200938.29" switch \initial - attribute \src "libresoc.v:198625.9-198625.17" + attribute \src "libresoc.v:200938.9-200938.17" case 1'1 case end @@ -415724,21 +419747,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14377 \src4_i + assign $1\src_r3$next[63:0]$14562 \src4_i case - assign $1\src_r3$next[63:0]$14377 \src_r3 + assign $1\src_r3$next[63:0]$14562 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14376 + update \src_r3$next $0\src_r3$next[63:0]$14561 end - attribute \src "libresoc.v:198634.3-198642.6" - process $proc$libresoc.v:198634$14378 + attribute \src "libresoc.v:200947.3-200955.6" + process $proc$libresoc.v:200947$14563 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14379 $1\alui_l_r_alui$next[0:0]$14380 - attribute \src "libresoc.v:198635.5-198635.29" + assign $0\alui_l_r_alui$next[0:0]$14564 $1\alui_l_r_alui$next[0:0]$14565 + attribute \src "libresoc.v:200948.5-200948.29" switch \initial - attribute \src "libresoc.v:198635.9-198635.17" + attribute \src "libresoc.v:200948.9-200948.17" case 1'1 case end @@ -415747,21 +419770,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14380 1'1 + assign $1\alui_l_r_alui$next[0:0]$14565 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14380 \$89 + assign $1\alui_l_r_alui$next[0:0]$14565 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14379 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14564 end - attribute \src "libresoc.v:198643.3-198651.6" - process $proc$libresoc.v:198643$14381 + attribute \src "libresoc.v:200956.3-200964.6" + process $proc$libresoc.v:200956$14566 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14382 $1\alu_l_r_alu$next[0:0]$14383 - attribute \src "libresoc.v:198644.5-198644.29" + assign $0\alu_l_r_alu$next[0:0]$14567 $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200957.5-200957.29" switch \initial - attribute \src "libresoc.v:198644.9-198644.17" + attribute \src "libresoc.v:200957.9-200957.17" case 1'1 case end @@ -415770,21 +419793,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14383 1'1 + assign $1\alu_l_r_alu$next[0:0]$14568 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14383 \$91 + assign $1\alu_l_r_alu$next[0:0]$14568 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14382 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14567 end - attribute \src "libresoc.v:198652.3-198661.6" - process $proc$libresoc.v:198652$14384 + attribute \src "libresoc.v:200965.3-200974.6" + process $proc$libresoc.v:200965$14569 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:198653.5-198653.29" + attribute \src "libresoc.v:200966.5-200966.29" switch \initial - attribute \src "libresoc.v:198653.9-198653.17" + attribute \src "libresoc.v:200966.9-200966.17" case 1'1 case end @@ -415800,14 +419823,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:198662.3-198671.6" - process $proc$libresoc.v:198662$14385 + attribute \src "libresoc.v:200975.3-200984.6" + process $proc$libresoc.v:200975$14570 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:198663.5-198663.29" + attribute \src "libresoc.v:200976.5-200976.29" switch \initial - attribute \src "libresoc.v:198663.9-198663.17" + attribute \src "libresoc.v:200976.9-200976.17" case 1'1 case end @@ -415823,14 +419846,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:198672.3-198681.6" - process $proc$libresoc.v:198672$14386 + attribute \src "libresoc.v:200985.3-200994.6" + process $proc$libresoc.v:200985$14571 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:198673.5-198673.29" + attribute \src "libresoc.v:200986.5-200986.29" switch \initial - attribute \src "libresoc.v:198673.9-198673.17" + attribute \src "libresoc.v:200986.9-200986.17" case 1'1 case end @@ -415846,14 +419869,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:198682.3-198691.6" - process $proc$libresoc.v:198682$14387 + attribute \src "libresoc.v:200995.3-201004.6" + process $proc$libresoc.v:200995$14572 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:198683.5-198683.29" + attribute \src "libresoc.v:200996.5-200996.29" switch \initial - attribute \src "libresoc.v:198683.9-198683.17" + attribute \src "libresoc.v:200996.9-200996.17" case 1'1 case end @@ -415869,14 +419892,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:198692.3-198701.6" - process $proc$libresoc.v:198692$14388 + attribute \src "libresoc.v:201005.3-201014.6" + process $proc$libresoc.v:201005$14573 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:198693.5-198693.29" + attribute \src "libresoc.v:201006.5-201006.29" switch \initial - attribute \src "libresoc.v:198693.9-198693.17" + attribute \src "libresoc.v:201006.9-201006.17" case 1'1 case end @@ -415892,14 +419915,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:198702.3-198710.6" - process $proc$libresoc.v:198702$14389 + attribute \src "libresoc.v:201015.3-201023.6" + process $proc$libresoc.v:201015$14574 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14390 $1\prev_wr_go$next[4:0]$14391 - attribute \src "libresoc.v:198703.5-198703.29" + assign $0\prev_wr_go$next[4:0]$14575 $1\prev_wr_go$next[4:0]$14576 + attribute \src "libresoc.v:201016.5-201016.29" switch \initial - attribute \src "libresoc.v:198703.9-198703.17" + attribute \src "libresoc.v:201016.9-201016.17" case 1'1 case end @@ -415908,74 +419931,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14391 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14391 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14390 - end - connect \$5 $reduce_and$libresoc.v:198150$14177_Y - connect \$99 $and$libresoc.v:198151$14178_Y - connect \$101 $and$libresoc.v:198152$14179_Y - connect \$103 $and$libresoc.v:198153$14180_Y - connect \$105 $and$libresoc.v:198154$14181_Y - connect \$107 $and$libresoc.v:198155$14182_Y - connect \$109 $and$libresoc.v:198156$14183_Y - connect \$111 $and$libresoc.v:198157$14184_Y - connect \$113 $and$libresoc.v:198158$14185_Y - connect \$115 $and$libresoc.v:198159$14186_Y - connect \$117 $and$libresoc.v:198160$14187_Y - connect \$11 $and$libresoc.v:198161$14188_Y - connect \$119 $and$libresoc.v:198162$14189_Y - connect \$121 $and$libresoc.v:198163$14190_Y - connect \$123 $and$libresoc.v:198164$14191_Y - connect \$13 $not$libresoc.v:198165$14192_Y - connect \$15 $and$libresoc.v:198166$14193_Y - connect \$17 $not$libresoc.v:198167$14194_Y - connect \$19 $and$libresoc.v:198168$14195_Y - connect \$21 $and$libresoc.v:198169$14196_Y - connect \$25 $not$libresoc.v:198170$14197_Y - connect \$27 $and$libresoc.v:198171$14198_Y - connect \$24 $reduce_or$libresoc.v:198172$14199_Y - connect \$23 $not$libresoc.v:198173$14200_Y - connect \$31 $and$libresoc.v:198174$14201_Y - connect \$33 $reduce_or$libresoc.v:198175$14202_Y - connect \$35 $reduce_or$libresoc.v:198176$14203_Y - connect \$37 $or$libresoc.v:198177$14204_Y - connect \$3 $and$libresoc.v:198178$14205_Y - connect \$39 $not$libresoc.v:198179$14206_Y - connect \$41 $and$libresoc.v:198180$14207_Y - connect \$43 $and$libresoc.v:198181$14208_Y - connect \$45 $eq$libresoc.v:198182$14209_Y - connect \$47 $and$libresoc.v:198183$14210_Y - connect \$49 $eq$libresoc.v:198184$14211_Y - connect \$51 $and$libresoc.v:198185$14212_Y - connect \$53 $and$libresoc.v:198186$14213_Y - connect \$55 $and$libresoc.v:198187$14214_Y - connect \$57 $or$libresoc.v:198188$14215_Y - connect \$59 $or$libresoc.v:198189$14216_Y - connect \$61 $or$libresoc.v:198190$14217_Y - connect \$63 $or$libresoc.v:198191$14218_Y - connect \$65 $and$libresoc.v:198192$14219_Y - connect \$67 $and$libresoc.v:198193$14220_Y - connect \$6 $not$libresoc.v:198194$14221_Y - connect \$69 $or$libresoc.v:198195$14222_Y - connect \$71 $and$libresoc.v:198196$14223_Y - connect \$73 $and$libresoc.v:198197$14224_Y - connect \$75 $and$libresoc.v:198198$14225_Y - connect \$77 $and$libresoc.v:198199$14226_Y - connect \$79 $and$libresoc.v:198200$14227_Y - connect \$81 $ternary$libresoc.v:198201$14228_Y - connect \$83 $ternary$libresoc.v:198202$14229_Y - connect \$85 $ternary$libresoc.v:198203$14230_Y - connect \$87 $ternary$libresoc.v:198204$14231_Y - connect \$8 $or$libresoc.v:198205$14232_Y - connect \$89 $and$libresoc.v:198206$14233_Y - connect \$91 $and$libresoc.v:198207$14234_Y - connect \$93 $and$libresoc.v:198208$14235_Y - connect \$95 $and$libresoc.v:198209$14236_Y - connect \$97 $not$libresoc.v:198210$14237_Y + assign $1\prev_wr_go$next[4:0]$14576 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14576 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14575 + end + connect \$5 $reduce_and$libresoc.v:200463$14362_Y + connect \$99 $and$libresoc.v:200464$14363_Y + connect \$101 $and$libresoc.v:200465$14364_Y + connect \$103 $and$libresoc.v:200466$14365_Y + connect \$105 $and$libresoc.v:200467$14366_Y + connect \$107 $and$libresoc.v:200468$14367_Y + connect \$109 $and$libresoc.v:200469$14368_Y + connect \$111 $and$libresoc.v:200470$14369_Y + connect \$113 $and$libresoc.v:200471$14370_Y + connect \$115 $and$libresoc.v:200472$14371_Y + connect \$117 $and$libresoc.v:200473$14372_Y + connect \$11 $and$libresoc.v:200474$14373_Y + connect \$119 $and$libresoc.v:200475$14374_Y + connect \$121 $and$libresoc.v:200476$14375_Y + connect \$123 $and$libresoc.v:200477$14376_Y + connect \$13 $not$libresoc.v:200478$14377_Y + connect \$15 $and$libresoc.v:200479$14378_Y + connect \$17 $not$libresoc.v:200480$14379_Y + connect \$19 $and$libresoc.v:200481$14380_Y + connect \$21 $and$libresoc.v:200482$14381_Y + connect \$25 $not$libresoc.v:200483$14382_Y + connect \$27 $and$libresoc.v:200484$14383_Y + connect \$24 $reduce_or$libresoc.v:200485$14384_Y + connect \$23 $not$libresoc.v:200486$14385_Y + connect \$31 $and$libresoc.v:200487$14386_Y + connect \$33 $reduce_or$libresoc.v:200488$14387_Y + connect \$35 $reduce_or$libresoc.v:200489$14388_Y + connect \$37 $or$libresoc.v:200490$14389_Y + connect \$3 $and$libresoc.v:200491$14390_Y + connect \$39 $not$libresoc.v:200492$14391_Y + connect \$41 $and$libresoc.v:200493$14392_Y + connect \$43 $and$libresoc.v:200494$14393_Y + connect \$45 $eq$libresoc.v:200495$14394_Y + connect \$47 $and$libresoc.v:200496$14395_Y + connect \$49 $eq$libresoc.v:200497$14396_Y + connect \$51 $and$libresoc.v:200498$14397_Y + connect \$53 $and$libresoc.v:200499$14398_Y + connect \$55 $and$libresoc.v:200500$14399_Y + connect \$57 $or$libresoc.v:200501$14400_Y + connect \$59 $or$libresoc.v:200502$14401_Y + connect \$61 $or$libresoc.v:200503$14402_Y + connect \$63 $or$libresoc.v:200504$14403_Y + connect \$65 $and$libresoc.v:200505$14404_Y + connect \$67 $and$libresoc.v:200506$14405_Y + connect \$6 $not$libresoc.v:200507$14406_Y + connect \$69 $or$libresoc.v:200508$14407_Y + connect \$71 $and$libresoc.v:200509$14408_Y + connect \$73 $and$libresoc.v:200510$14409_Y + connect \$75 $and$libresoc.v:200511$14410_Y + connect \$77 $and$libresoc.v:200512$14411_Y + connect \$79 $and$libresoc.v:200513$14412_Y + connect \$81 $ternary$libresoc.v:200514$14413_Y + connect \$83 $ternary$libresoc.v:200515$14414_Y + connect \$85 $ternary$libresoc.v:200516$14415_Y + connect \$87 $ternary$libresoc.v:200517$14416_Y + connect \$8 $or$libresoc.v:200518$14417_Y + connect \$89 $and$libresoc.v:200519$14418_Y + connect \$91 $and$libresoc.v:200520$14419_Y + connect \$93 $and$libresoc.v:200521$14420_Y + connect \$95 $and$libresoc.v:200522$14421_Y + connect \$97 $not$libresoc.v:200523$14422_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -416006,37 +420029,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:198744.1-198802.10" +attribute \src "libresoc.v:201057.1-201115.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:198745.7-198745.20" + attribute \src "libresoc.v:201058.7-201058.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198790.3-198798.6" - wire $0\q_int$next[0:0]$14441 - attribute \src "libresoc.v:198788.3-198789.27" + attribute \src "libresoc.v:201103.3-201111.6" + wire $0\q_int$next[0:0]$14626 + attribute \src "libresoc.v:201101.3-201102.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198790.3-198798.6" - wire $1\q_int$next[0:0]$14442 - attribute \src "libresoc.v:198767.7-198767.19" + attribute \src "libresoc.v:201103.3-201111.6" + wire $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201080.7-201080.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198780.17-198780.96" - wire $and$libresoc.v:198780$14431_Y - attribute \src "libresoc.v:198785.17-198785.96" - wire $and$libresoc.v:198785$14436_Y - attribute \src "libresoc.v:198782.18-198782.93" - wire $not$libresoc.v:198782$14433_Y - attribute \src "libresoc.v:198784.17-198784.92" - wire $not$libresoc.v:198784$14435_Y - attribute \src "libresoc.v:198787.17-198787.92" - wire $not$libresoc.v:198787$14438_Y - attribute \src "libresoc.v:198781.18-198781.98" - wire $or$libresoc.v:198781$14432_Y - attribute \src "libresoc.v:198783.18-198783.99" - wire $or$libresoc.v:198783$14434_Y - attribute \src "libresoc.v:198786.17-198786.97" - wire $or$libresoc.v:198786$14437_Y + attribute \src "libresoc.v:201093.17-201093.96" + wire $and$libresoc.v:201093$14616_Y + attribute \src "libresoc.v:201098.17-201098.96" + wire $and$libresoc.v:201098$14621_Y + attribute \src "libresoc.v:201095.18-201095.93" + wire $not$libresoc.v:201095$14618_Y + attribute \src "libresoc.v:201097.17-201097.92" + wire $not$libresoc.v:201097$14620_Y + attribute \src "libresoc.v:201100.17-201100.92" + wire $not$libresoc.v:201100$14623_Y + attribute \src "libresoc.v:201094.18-201094.98" + wire $or$libresoc.v:201094$14617_Y + attribute \src "libresoc.v:201096.18-201096.99" + wire $or$libresoc.v:201096$14619_Y + attribute \src "libresoc.v:201099.17-201099.97" + wire $or$libresoc.v:201099$14622_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416053,11 +420076,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198745.7-198745.15" + attribute \src "libresoc.v:201058.7-201058.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416074,7 +420097,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198780$14431 + cell $and $and$libresoc.v:201093$14616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416082,10 +420105,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198780$14431_Y + connect \Y $and$libresoc.v:201093$14616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198785$14436 + cell $and $and$libresoc.v:201098$14621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416093,34 +420116,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198785$14436_Y + connect \Y $and$libresoc.v:201098$14621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198782$14433 + cell $not $not$libresoc.v:201095$14618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:198782$14433_Y + connect \Y $not$libresoc.v:201095$14618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198784$14435 + cell $not $not$libresoc.v:201097$14620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:198784$14435_Y + connect \Y $not$libresoc.v:201097$14620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198787$14438 + cell $not $not$libresoc.v:201100$14623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:198787$14438_Y + connect \Y $not$libresoc.v:201100$14623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198781$14432 + cell $or $or$libresoc.v:201094$14617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416128,10 +420151,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:198781$14432_Y + connect \Y $or$libresoc.v:201094$14617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198783$14434 + cell $or $or$libresoc.v:201096$14619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416139,10 +420162,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:198783$14434_Y + connect \Y $or$libresoc.v:201096$14619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198786$14437 + cell $or $or$libresoc.v:201099$14622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416150,39 +420173,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:198786$14437_Y + connect \Y $or$libresoc.v:201099$14622_Y end - attribute \src "libresoc.v:198745.7-198745.20" - process $proc$libresoc.v:198745$14443 + attribute \src "libresoc.v:201058.7-201058.20" + process $proc$libresoc.v:201058$14628 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198767.7-198767.19" - process $proc$libresoc.v:198767$14444 + attribute \src "libresoc.v:201080.7-201080.19" + process $proc$libresoc.v:201080$14629 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198788.3-198789.27" - process $proc$libresoc.v:198788$14439 + attribute \src "libresoc.v:201101.3-201102.27" + process $proc$libresoc.v:201101$14624 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198790.3-198798.6" - process $proc$libresoc.v:198790$14440 + attribute \src "libresoc.v:201103.3-201111.6" + process $proc$libresoc.v:201103$14625 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14441 $1\q_int$next[0:0]$14442 - attribute \src "libresoc.v:198791.5-198791.29" + assign $0\q_int$next[0:0]$14626 $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201104.5-201104.29" switch \initial - attribute \src "libresoc.v:198791.9-198791.17" + attribute \src "libresoc.v:201104.9-201104.17" case 1'1 case end @@ -416191,56 +420214,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14442 1'0 + assign $1\q_int$next[0:0]$14627 1'0 case - assign $1\q_int$next[0:0]$14442 \$5 + assign $1\q_int$next[0:0]$14627 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14441 + update \q_int$next $0\q_int$next[0:0]$14626 end - connect \$9 $and$libresoc.v:198780$14431_Y - connect \$11 $or$libresoc.v:198781$14432_Y - connect \$13 $not$libresoc.v:198782$14433_Y - connect \$15 $or$libresoc.v:198783$14434_Y - connect \$1 $not$libresoc.v:198784$14435_Y - connect \$3 $and$libresoc.v:198785$14436_Y - connect \$5 $or$libresoc.v:198786$14437_Y - connect \$7 $not$libresoc.v:198787$14438_Y + connect \$9 $and$libresoc.v:201093$14616_Y + connect \$11 $or$libresoc.v:201094$14617_Y + connect \$13 $not$libresoc.v:201095$14618_Y + connect \$15 $or$libresoc.v:201096$14619_Y + connect \$1 $not$libresoc.v:201097$14620_Y + connect \$3 $and$libresoc.v:201098$14621_Y + connect \$5 $or$libresoc.v:201099$14622_Y + connect \$7 $not$libresoc.v:201100$14623_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:198806.1-198864.10" +attribute \src "libresoc.v:201119.1-201177.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:198807.7-198807.20" + attribute \src "libresoc.v:201120.7-201120.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198852.3-198860.6" - wire $0\q_int$next[0:0]$14455 - attribute \src "libresoc.v:198850.3-198851.27" + attribute \src "libresoc.v:201165.3-201173.6" + wire $0\q_int$next[0:0]$14640 + attribute \src "libresoc.v:201163.3-201164.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198852.3-198860.6" - wire $1\q_int$next[0:0]$14456 - attribute \src "libresoc.v:198829.7-198829.19" + attribute \src "libresoc.v:201165.3-201173.6" + wire $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201142.7-201142.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198842.17-198842.96" - wire $and$libresoc.v:198842$14445_Y - attribute \src "libresoc.v:198847.17-198847.96" - wire $and$libresoc.v:198847$14450_Y - attribute \src "libresoc.v:198844.18-198844.95" - wire $not$libresoc.v:198844$14447_Y - attribute \src "libresoc.v:198846.17-198846.94" - wire $not$libresoc.v:198846$14449_Y - attribute \src "libresoc.v:198849.17-198849.94" - wire $not$libresoc.v:198849$14452_Y - attribute \src "libresoc.v:198843.18-198843.100" - wire $or$libresoc.v:198843$14446_Y - attribute \src "libresoc.v:198845.18-198845.101" - wire $or$libresoc.v:198845$14448_Y - attribute \src "libresoc.v:198848.17-198848.99" - wire $or$libresoc.v:198848$14451_Y + attribute \src "libresoc.v:201155.17-201155.96" + wire $and$libresoc.v:201155$14630_Y + attribute \src "libresoc.v:201160.17-201160.96" + wire $and$libresoc.v:201160$14635_Y + attribute \src "libresoc.v:201157.18-201157.95" + wire $not$libresoc.v:201157$14632_Y + attribute \src "libresoc.v:201159.17-201159.94" + wire $not$libresoc.v:201159$14634_Y + attribute \src "libresoc.v:201162.17-201162.94" + wire $not$libresoc.v:201162$14637_Y + attribute \src "libresoc.v:201156.18-201156.100" + wire $or$libresoc.v:201156$14631_Y + attribute \src "libresoc.v:201158.18-201158.101" + wire $or$libresoc.v:201158$14633_Y + attribute \src "libresoc.v:201161.17-201161.99" + wire $or$libresoc.v:201161$14636_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416257,11 +420280,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198807.7-198807.15" + attribute \src "libresoc.v:201120.7-201120.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416278,7 +420301,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198842$14445 + cell $and $and$libresoc.v:201155$14630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416286,10 +420309,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198842$14445_Y + connect \Y $and$libresoc.v:201155$14630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198847$14450 + cell $and $and$libresoc.v:201160$14635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416297,34 +420320,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198847$14450_Y + connect \Y $and$libresoc.v:201160$14635_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198844$14447 + cell $not $not$libresoc.v:201157$14632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:198844$14447_Y + connect \Y $not$libresoc.v:201157$14632_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198846$14449 + cell $not $not$libresoc.v:201159$14634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:198846$14449_Y + connect \Y $not$libresoc.v:201159$14634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198849$14452 + cell $not $not$libresoc.v:201162$14637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:198849$14452_Y + connect \Y $not$libresoc.v:201162$14637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198843$14446 + cell $or $or$libresoc.v:201156$14631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416332,10 +420355,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:198843$14446_Y + connect \Y $or$libresoc.v:201156$14631_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198845$14448 + cell $or $or$libresoc.v:201158$14633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416343,10 +420366,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:198845$14448_Y + connect \Y $or$libresoc.v:201158$14633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198848$14451 + cell $or $or$libresoc.v:201161$14636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416354,39 +420377,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:198848$14451_Y + connect \Y $or$libresoc.v:201161$14636_Y end - attribute \src "libresoc.v:198807.7-198807.20" - process $proc$libresoc.v:198807$14457 + attribute \src "libresoc.v:201120.7-201120.20" + process $proc$libresoc.v:201120$14642 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198829.7-198829.19" - process $proc$libresoc.v:198829$14458 + attribute \src "libresoc.v:201142.7-201142.19" + process $proc$libresoc.v:201142$14643 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198850.3-198851.27" - process $proc$libresoc.v:198850$14453 + attribute \src "libresoc.v:201163.3-201164.27" + process $proc$libresoc.v:201163$14638 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198852.3-198860.6" - process $proc$libresoc.v:198852$14454 + attribute \src "libresoc.v:201165.3-201173.6" + process $proc$libresoc.v:201165$14639 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14455 $1\q_int$next[0:0]$14456 - attribute \src "libresoc.v:198853.5-198853.29" + assign $0\q_int$next[0:0]$14640 $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201166.5-201166.29" switch \initial - attribute \src "libresoc.v:198853.9-198853.17" + attribute \src "libresoc.v:201166.9-201166.17" case 1'1 case end @@ -416395,56 +420418,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14456 1'0 + assign $1\q_int$next[0:0]$14641 1'0 case - assign $1\q_int$next[0:0]$14456 \$5 + assign $1\q_int$next[0:0]$14641 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14455 + update \q_int$next $0\q_int$next[0:0]$14640 end - connect \$9 $and$libresoc.v:198842$14445_Y - connect \$11 $or$libresoc.v:198843$14446_Y - connect \$13 $not$libresoc.v:198844$14447_Y - connect \$15 $or$libresoc.v:198845$14448_Y - connect \$1 $not$libresoc.v:198846$14449_Y - connect \$3 $and$libresoc.v:198847$14450_Y - connect \$5 $or$libresoc.v:198848$14451_Y - connect \$7 $not$libresoc.v:198849$14452_Y + connect \$9 $and$libresoc.v:201155$14630_Y + connect \$11 $or$libresoc.v:201156$14631_Y + connect \$13 $not$libresoc.v:201157$14632_Y + connect \$15 $or$libresoc.v:201158$14633_Y + connect \$1 $not$libresoc.v:201159$14634_Y + connect \$3 $and$libresoc.v:201160$14635_Y + connect \$5 $or$libresoc.v:201161$14636_Y + connect \$7 $not$libresoc.v:201162$14637_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:198868.1-198926.10" +attribute \src "libresoc.v:201181.1-201239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:198869.7-198869.20" + attribute \src "libresoc.v:201182.7-201182.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198914.3-198922.6" - wire $0\q_int$next[0:0]$14469 - attribute \src "libresoc.v:198912.3-198913.27" + attribute \src "libresoc.v:201227.3-201235.6" + wire $0\q_int$next[0:0]$14654 + attribute \src "libresoc.v:201225.3-201226.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198914.3-198922.6" - wire $1\q_int$next[0:0]$14470 - attribute \src "libresoc.v:198891.7-198891.19" + attribute \src "libresoc.v:201227.3-201235.6" + wire $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201204.7-201204.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198904.17-198904.96" - wire $and$libresoc.v:198904$14459_Y - attribute \src "libresoc.v:198909.17-198909.96" - wire $and$libresoc.v:198909$14464_Y - attribute \src "libresoc.v:198906.18-198906.93" - wire $not$libresoc.v:198906$14461_Y - attribute \src "libresoc.v:198908.17-198908.92" - wire $not$libresoc.v:198908$14463_Y - attribute \src "libresoc.v:198911.17-198911.92" - wire $not$libresoc.v:198911$14466_Y - attribute \src "libresoc.v:198905.18-198905.98" - wire $or$libresoc.v:198905$14460_Y - attribute \src "libresoc.v:198907.18-198907.99" - wire $or$libresoc.v:198907$14462_Y - attribute \src "libresoc.v:198910.17-198910.97" - wire $or$libresoc.v:198910$14465_Y + attribute \src "libresoc.v:201217.17-201217.96" + wire $and$libresoc.v:201217$14644_Y + attribute \src "libresoc.v:201222.17-201222.96" + wire $and$libresoc.v:201222$14649_Y + attribute \src "libresoc.v:201219.18-201219.93" + wire $not$libresoc.v:201219$14646_Y + attribute \src "libresoc.v:201221.17-201221.92" + wire $not$libresoc.v:201221$14648_Y + attribute \src "libresoc.v:201224.17-201224.92" + wire $not$libresoc.v:201224$14651_Y + attribute \src "libresoc.v:201218.18-201218.98" + wire $or$libresoc.v:201218$14645_Y + attribute \src "libresoc.v:201220.18-201220.99" + wire $or$libresoc.v:201220$14647_Y + attribute \src "libresoc.v:201223.17-201223.97" + wire $or$libresoc.v:201223$14650_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416461,11 +420484,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198869.7-198869.15" + attribute \src "libresoc.v:201182.7-201182.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416482,7 +420505,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198904$14459 + cell $and $and$libresoc.v:201217$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416490,10 +420513,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198904$14459_Y + connect \Y $and$libresoc.v:201217$14644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198909$14464 + cell $and $and$libresoc.v:201222$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416501,34 +420524,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198909$14464_Y + connect \Y $and$libresoc.v:201222$14649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198906$14461 + cell $not $not$libresoc.v:201219$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:198906$14461_Y + connect \Y $not$libresoc.v:201219$14646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198908$14463 + cell $not $not$libresoc.v:201221$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:198908$14463_Y + connect \Y $not$libresoc.v:201221$14648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198911$14466 + cell $not $not$libresoc.v:201224$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:198911$14466_Y + connect \Y $not$libresoc.v:201224$14651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198905$14460 + cell $or $or$libresoc.v:201218$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416536,10 +420559,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:198905$14460_Y + connect \Y $or$libresoc.v:201218$14645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198907$14462 + cell $or $or$libresoc.v:201220$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416547,10 +420570,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:198907$14462_Y + connect \Y $or$libresoc.v:201220$14647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198910$14465 + cell $or $or$libresoc.v:201223$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416558,39 +420581,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:198910$14465_Y + connect \Y $or$libresoc.v:201223$14650_Y end - attribute \src "libresoc.v:198869.7-198869.20" - process $proc$libresoc.v:198869$14471 + attribute \src "libresoc.v:201182.7-201182.20" + process $proc$libresoc.v:201182$14656 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198891.7-198891.19" - process $proc$libresoc.v:198891$14472 + attribute \src "libresoc.v:201204.7-201204.19" + process $proc$libresoc.v:201204$14657 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198912.3-198913.27" - process $proc$libresoc.v:198912$14467 + attribute \src "libresoc.v:201225.3-201226.27" + process $proc$libresoc.v:201225$14652 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198914.3-198922.6" - process $proc$libresoc.v:198914$14468 + attribute \src "libresoc.v:201227.3-201235.6" + process $proc$libresoc.v:201227$14653 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14469 $1\q_int$next[0:0]$14470 - attribute \src "libresoc.v:198915.5-198915.29" + assign $0\q_int$next[0:0]$14654 $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201228.5-201228.29" switch \initial - attribute \src "libresoc.v:198915.9-198915.17" + attribute \src "libresoc.v:201228.9-201228.17" case 1'1 case end @@ -416599,54 +420622,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14470 1'0 + assign $1\q_int$next[0:0]$14655 1'0 case - assign $1\q_int$next[0:0]$14470 \$5 + assign $1\q_int$next[0:0]$14655 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14469 + update \q_int$next $0\q_int$next[0:0]$14654 end - connect \$9 $and$libresoc.v:198904$14459_Y - connect \$11 $or$libresoc.v:198905$14460_Y - connect \$13 $not$libresoc.v:198906$14461_Y - connect \$15 $or$libresoc.v:198907$14462_Y - connect \$1 $not$libresoc.v:198908$14463_Y - connect \$3 $and$libresoc.v:198909$14464_Y - connect \$5 $or$libresoc.v:198910$14465_Y - connect \$7 $not$libresoc.v:198911$14466_Y + connect \$9 $and$libresoc.v:201217$14644_Y + connect \$11 $or$libresoc.v:201218$14645_Y + connect \$13 $not$libresoc.v:201219$14646_Y + connect \$15 $or$libresoc.v:201220$14647_Y + connect \$1 $not$libresoc.v:201221$14648_Y + connect \$3 $and$libresoc.v:201222$14649_Y + connect \$5 $or$libresoc.v:201223$14650_Y + connect \$7 $not$libresoc.v:201224$14651_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:198930.1-198996.10" +attribute \src "libresoc.v:201243.1-201309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:198975.17-198975.91" - wire $not$libresoc.v:198975$14473_Y - attribute \src "libresoc.v:198977.18-198977.93" - wire $not$libresoc.v:198977$14475_Y - attribute \src "libresoc.v:198979.18-198979.93" - wire $not$libresoc.v:198979$14477_Y - attribute \src "libresoc.v:198980.17-198980.89" - wire width 6 $not$libresoc.v:198980$14478_Y - attribute \src "libresoc.v:198982.18-198982.93" - wire $not$libresoc.v:198982$14480_Y - attribute \src "libresoc.v:198985.17-198985.91" - wire $not$libresoc.v:198985$14483_Y - attribute \src "libresoc.v:198976.18-198976.106" - wire $reduce_or$libresoc.v:198976$14474_Y - attribute \src "libresoc.v:198978.18-198978.106" - wire $reduce_or$libresoc.v:198978$14476_Y - attribute \src "libresoc.v:198981.18-198981.106" - wire $reduce_or$libresoc.v:198981$14479_Y - attribute \src "libresoc.v:198983.18-198983.90" - wire $reduce_or$libresoc.v:198983$14481_Y - attribute \src "libresoc.v:198984.17-198984.103" - wire $reduce_or$libresoc.v:198984$14482_Y - attribute \src "libresoc.v:198986.17-198986.105" - wire $reduce_or$libresoc.v:198986$14484_Y + attribute \src "libresoc.v:201288.17-201288.91" + wire $not$libresoc.v:201288$14658_Y + attribute \src "libresoc.v:201290.18-201290.93" + wire $not$libresoc.v:201290$14660_Y + attribute \src "libresoc.v:201292.18-201292.93" + wire $not$libresoc.v:201292$14662_Y + attribute \src "libresoc.v:201293.17-201293.89" + wire width 6 $not$libresoc.v:201293$14663_Y + attribute \src "libresoc.v:201295.18-201295.93" + wire $not$libresoc.v:201295$14665_Y + attribute \src "libresoc.v:201298.17-201298.91" + wire $not$libresoc.v:201298$14668_Y + attribute \src "libresoc.v:201289.18-201289.106" + wire $reduce_or$libresoc.v:201289$14659_Y + attribute \src "libresoc.v:201291.18-201291.106" + wire $reduce_or$libresoc.v:201291$14661_Y + attribute \src "libresoc.v:201294.18-201294.106" + wire $reduce_or$libresoc.v:201294$14664_Y + attribute \src "libresoc.v:201296.18-201296.90" + wire $reduce_or$libresoc.v:201296$14666_Y + attribute \src "libresoc.v:201297.17-201297.103" + wire $reduce_or$libresoc.v:201297$14667_Y + attribute \src "libresoc.v:201299.17-201299.105" + wire $reduce_or$libresoc.v:201299$14669_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416692,113 +420715,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198975$14473 + cell $not $not$libresoc.v:201288$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:198975$14473_Y + connect \Y $not$libresoc.v:201288$14658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198977$14475 + cell $not $not$libresoc.v:201290$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:198977$14475_Y + connect \Y $not$libresoc.v:201290$14660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198979$14477 + cell $not $not$libresoc.v:201292$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:198979$14477_Y + connect \Y $not$libresoc.v:201292$14662_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:198980$14478 + cell $not $not$libresoc.v:201293$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:198980$14478_Y + connect \Y $not$libresoc.v:201293$14663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198982$14480 + cell $not $not$libresoc.v:201295$14665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:198982$14480_Y + connect \Y $not$libresoc.v:201295$14665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198985$14483 + cell $not $not$libresoc.v:201298$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:198985$14483_Y + connect \Y $not$libresoc.v:201298$14668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198976$14474 + cell $reduce_or $reduce_or$libresoc.v:201289$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:198976$14474_Y + connect \Y $reduce_or$libresoc.v:201289$14659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198978$14476 + cell $reduce_or $reduce_or$libresoc.v:201291$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:198978$14476_Y + connect \Y $reduce_or$libresoc.v:201291$14661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198981$14479 + cell $reduce_or $reduce_or$libresoc.v:201294$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:198981$14479_Y + connect \Y $reduce_or$libresoc.v:201294$14664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:198983$14481 + cell $reduce_or $reduce_or$libresoc.v:201296$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:198983$14481_Y + connect \Y $reduce_or$libresoc.v:201296$14666_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198984$14482 + cell $reduce_or $reduce_or$libresoc.v:201297$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:198984$14482_Y + connect \Y $reduce_or$libresoc.v:201297$14667_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198986$14484 + cell $reduce_or $reduce_or$libresoc.v:201299$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:198986$14484_Y - end - connect \$7 $not$libresoc.v:198975$14473_Y - connect \$12 $reduce_or$libresoc.v:198976$14474_Y - connect \$11 $not$libresoc.v:198977$14475_Y - connect \$16 $reduce_or$libresoc.v:198978$14476_Y - connect \$15 $not$libresoc.v:198979$14477_Y - connect \$1 $not$libresoc.v:198980$14478_Y - connect \$20 $reduce_or$libresoc.v:198981$14479_Y - connect \$19 $not$libresoc.v:198982$14480_Y - connect \$23 $reduce_or$libresoc.v:198983$14481_Y - connect \$4 $reduce_or$libresoc.v:198984$14482_Y - connect \$3 $not$libresoc.v:198985$14483_Y - connect \$8 $reduce_or$libresoc.v:198986$14484_Y + connect \Y $reduce_or$libresoc.v:201299$14669_Y + end + connect \$7 $not$libresoc.v:201288$14658_Y + connect \$12 $reduce_or$libresoc.v:201289$14659_Y + connect \$11 $not$libresoc.v:201290$14660_Y + connect \$16 $reduce_or$libresoc.v:201291$14661_Y + connect \$15 $not$libresoc.v:201292$14662_Y + connect \$1 $not$libresoc.v:201293$14663_Y + connect \$20 $reduce_or$libresoc.v:201294$14664_Y + connect \$19 $not$libresoc.v:201295$14665_Y + connect \$23 $reduce_or$libresoc.v:201296$14666_Y + connect \$4 $reduce_or$libresoc.v:201297$14667_Y + connect \$3 $not$libresoc.v:201298$14668_Y + connect \$8 $reduce_or$libresoc.v:201299$14669_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -416809,15 +420832,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199000.1-199021.10" +attribute \src "libresoc.v:201313.1-201334.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:199015.17-199015.89" - wire $not$libresoc.v:199015$14485_Y - attribute \src "libresoc.v:199016.17-199016.89" - wire $reduce_or$libresoc.v:199016$14486_Y + attribute \src "libresoc.v:201328.17-201328.89" + wire $not$libresoc.v:201328$14670_Y + attribute \src "libresoc.v:201329.17-201329.89" + wire $reduce_or$libresoc.v:201329$14671_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416833,53 +420856,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199015$14485 + cell $not $not$libresoc.v:201328$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199015$14485_Y + connect \Y $not$libresoc.v:201328$14670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199016$14486 + cell $reduce_or $reduce_or$libresoc.v:201329$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199016$14486_Y + connect \Y $reduce_or$libresoc.v:201329$14671_Y end - connect \$1 $not$libresoc.v:199015$14485_Y - connect \$3 $reduce_or$libresoc.v:199016$14486_Y + connect \$1 $not$libresoc.v:201328$14670_Y + connect \$3 $reduce_or$libresoc.v:201329$14671_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199025.1-199082.10" +attribute \src "libresoc.v:201338.1-201395.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:199064.17-199064.91" - wire $not$libresoc.v:199064$14487_Y - attribute \src "libresoc.v:199066.18-199066.93" - wire $not$libresoc.v:199066$14489_Y - attribute \src "libresoc.v:199068.18-199068.93" - wire $not$libresoc.v:199068$14491_Y - attribute \src "libresoc.v:199069.17-199069.89" - wire width 5 $not$libresoc.v:199069$14492_Y - attribute \src "libresoc.v:199072.17-199072.91" - wire $not$libresoc.v:199072$14495_Y - attribute \src "libresoc.v:199065.18-199065.106" - wire $reduce_or$libresoc.v:199065$14488_Y - attribute \src "libresoc.v:199067.18-199067.106" - wire $reduce_or$libresoc.v:199067$14490_Y - attribute \src "libresoc.v:199070.18-199070.90" - wire $reduce_or$libresoc.v:199070$14493_Y - attribute \src "libresoc.v:199071.17-199071.103" - wire $reduce_or$libresoc.v:199071$14494_Y - attribute \src "libresoc.v:199073.17-199073.105" - wire $reduce_or$libresoc.v:199073$14496_Y + attribute \src "libresoc.v:201377.17-201377.91" + wire $not$libresoc.v:201377$14672_Y + attribute \src "libresoc.v:201379.18-201379.93" + wire $not$libresoc.v:201379$14674_Y + attribute \src "libresoc.v:201381.18-201381.93" + wire $not$libresoc.v:201381$14676_Y + attribute \src "libresoc.v:201382.17-201382.89" + wire width 5 $not$libresoc.v:201382$14677_Y + attribute \src "libresoc.v:201385.17-201385.91" + wire $not$libresoc.v:201385$14680_Y + attribute \src "libresoc.v:201378.18-201378.106" + wire $reduce_or$libresoc.v:201378$14673_Y + attribute \src "libresoc.v:201380.18-201380.106" + wire $reduce_or$libresoc.v:201380$14675_Y + attribute \src "libresoc.v:201383.18-201383.90" + wire $reduce_or$libresoc.v:201383$14678_Y + attribute \src "libresoc.v:201384.17-201384.103" + wire $reduce_or$libresoc.v:201384$14679_Y + attribute \src "libresoc.v:201386.17-201386.105" + wire $reduce_or$libresoc.v:201386$14681_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416919,95 +420942,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199064$14487 + cell $not $not$libresoc.v:201377$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199064$14487_Y + connect \Y $not$libresoc.v:201377$14672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199066$14489 + cell $not $not$libresoc.v:201379$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199066$14489_Y + connect \Y $not$libresoc.v:201379$14674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199068$14491 + cell $not $not$libresoc.v:201381$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:199068$14491_Y + connect \Y $not$libresoc.v:201381$14676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199069$14492 + cell $not $not$libresoc.v:201382$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:199069$14492_Y + connect \Y $not$libresoc.v:201382$14677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199072$14495 + cell $not $not$libresoc.v:201385$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199072$14495_Y + connect \Y $not$libresoc.v:201385$14680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199065$14488 + cell $reduce_or $reduce_or$libresoc.v:201378$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199065$14488_Y + connect \Y $reduce_or$libresoc.v:201378$14673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199067$14490 + cell $reduce_or $reduce_or$libresoc.v:201380$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:199067$14490_Y + connect \Y $reduce_or$libresoc.v:201380$14675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199070$14493 + cell $reduce_or $reduce_or$libresoc.v:201383$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199070$14493_Y + connect \Y $reduce_or$libresoc.v:201383$14678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199071$14494 + cell $reduce_or $reduce_or$libresoc.v:201384$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199071$14494_Y + connect \Y $reduce_or$libresoc.v:201384$14679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199073$14496 + cell $reduce_or $reduce_or$libresoc.v:201386$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199073$14496_Y - end - connect \$7 $not$libresoc.v:199064$14487_Y - connect \$12 $reduce_or$libresoc.v:199065$14488_Y - connect \$11 $not$libresoc.v:199066$14489_Y - connect \$16 $reduce_or$libresoc.v:199067$14490_Y - connect \$15 $not$libresoc.v:199068$14491_Y - connect \$1 $not$libresoc.v:199069$14492_Y - connect \$19 $reduce_or$libresoc.v:199070$14493_Y - connect \$4 $reduce_or$libresoc.v:199071$14494_Y - connect \$3 $not$libresoc.v:199072$14495_Y - connect \$8 $reduce_or$libresoc.v:199073$14496_Y + connect \Y $reduce_or$libresoc.v:201386$14681_Y + end + connect \$7 $not$libresoc.v:201377$14672_Y + connect \$12 $reduce_or$libresoc.v:201378$14673_Y + connect \$11 $not$libresoc.v:201379$14674_Y + connect \$16 $reduce_or$libresoc.v:201380$14675_Y + connect \$15 $not$libresoc.v:201381$14676_Y + connect \$1 $not$libresoc.v:201382$14677_Y + connect \$19 $reduce_or$libresoc.v:201383$14678_Y + connect \$4 $reduce_or$libresoc.v:201384$14679_Y + connect \$3 $not$libresoc.v:201385$14680_Y + connect \$8 $reduce_or$libresoc.v:201386$14681_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -417017,51 +421040,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199086.1-199188.10" +attribute \src "libresoc.v:201399.1-201501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:199155.17-199155.91" - wire $not$libresoc.v:199155$14497_Y - attribute \src "libresoc.v:199157.18-199157.93" - wire $not$libresoc.v:199157$14499_Y - attribute \src "libresoc.v:199159.18-199159.93" - wire $not$libresoc.v:199159$14501_Y - attribute \src "libresoc.v:199160.17-199160.89" - wire width 10 $not$libresoc.v:199160$14502_Y - attribute \src "libresoc.v:199162.18-199162.93" - wire $not$libresoc.v:199162$14504_Y - attribute \src "libresoc.v:199164.18-199164.93" - wire $not$libresoc.v:199164$14506_Y - attribute \src "libresoc.v:199166.18-199166.93" - wire $not$libresoc.v:199166$14508_Y - attribute \src "libresoc.v:199168.18-199168.93" - wire $not$libresoc.v:199168$14510_Y - attribute \src "libresoc.v:199170.18-199170.93" - wire $not$libresoc.v:199170$14512_Y - attribute \src "libresoc.v:199173.17-199173.91" - wire $not$libresoc.v:199173$14515_Y - attribute \src "libresoc.v:199156.18-199156.106" - wire $reduce_or$libresoc.v:199156$14498_Y - attribute \src "libresoc.v:199158.18-199158.106" - wire $reduce_or$libresoc.v:199158$14500_Y - attribute \src "libresoc.v:199161.18-199161.106" - wire $reduce_or$libresoc.v:199161$14503_Y - attribute \src "libresoc.v:199163.18-199163.106" - wire $reduce_or$libresoc.v:199163$14505_Y - attribute \src "libresoc.v:199165.18-199165.106" - wire $reduce_or$libresoc.v:199165$14507_Y - attribute \src "libresoc.v:199167.18-199167.106" - wire $reduce_or$libresoc.v:199167$14509_Y - attribute \src "libresoc.v:199169.18-199169.106" - wire $reduce_or$libresoc.v:199169$14511_Y - attribute \src "libresoc.v:199171.18-199171.90" - wire $reduce_or$libresoc.v:199171$14513_Y - attribute \src "libresoc.v:199172.17-199172.103" - wire $reduce_or$libresoc.v:199172$14514_Y - attribute \src "libresoc.v:199174.17-199174.105" - wire $reduce_or$libresoc.v:199174$14516_Y + attribute \src "libresoc.v:201468.17-201468.91" + wire $not$libresoc.v:201468$14682_Y + attribute \src "libresoc.v:201470.18-201470.93" + wire $not$libresoc.v:201470$14684_Y + attribute \src "libresoc.v:201472.18-201472.93" + wire $not$libresoc.v:201472$14686_Y + attribute \src "libresoc.v:201473.17-201473.89" + wire width 10 $not$libresoc.v:201473$14687_Y + attribute \src "libresoc.v:201475.18-201475.93" + wire $not$libresoc.v:201475$14689_Y + attribute \src "libresoc.v:201477.18-201477.93" + wire $not$libresoc.v:201477$14691_Y + attribute \src "libresoc.v:201479.18-201479.93" + wire $not$libresoc.v:201479$14693_Y + attribute \src "libresoc.v:201481.18-201481.93" + wire $not$libresoc.v:201481$14695_Y + attribute \src "libresoc.v:201483.18-201483.93" + wire $not$libresoc.v:201483$14697_Y + attribute \src "libresoc.v:201486.17-201486.91" + wire $not$libresoc.v:201486$14700_Y + attribute \src "libresoc.v:201469.18-201469.106" + wire $reduce_or$libresoc.v:201469$14683_Y + attribute \src "libresoc.v:201471.18-201471.106" + wire $reduce_or$libresoc.v:201471$14685_Y + attribute \src "libresoc.v:201474.18-201474.106" + wire $reduce_or$libresoc.v:201474$14688_Y + attribute \src "libresoc.v:201476.18-201476.106" + wire $reduce_or$libresoc.v:201476$14690_Y + attribute \src "libresoc.v:201478.18-201478.106" + wire $reduce_or$libresoc.v:201478$14692_Y + attribute \src "libresoc.v:201480.18-201480.106" + wire $reduce_or$libresoc.v:201480$14694_Y + attribute \src "libresoc.v:201482.18-201482.106" + wire $reduce_or$libresoc.v:201482$14696_Y + attribute \src "libresoc.v:201484.18-201484.90" + wire $reduce_or$libresoc.v:201484$14698_Y + attribute \src "libresoc.v:201485.17-201485.103" + wire $reduce_or$libresoc.v:201485$14699_Y + attribute \src "libresoc.v:201487.17-201487.105" + wire $reduce_or$libresoc.v:201487$14701_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417131,185 +421154,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199155$14497 + cell $not $not$libresoc.v:201468$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199155$14497_Y + connect \Y $not$libresoc.v:201468$14682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199157$14499 + cell $not $not$libresoc.v:201470$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199157$14499_Y + connect \Y $not$libresoc.v:201470$14684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199159$14501 + cell $not $not$libresoc.v:201472$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:199159$14501_Y + connect \Y $not$libresoc.v:201472$14686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199160$14502 + cell $not $not$libresoc.v:201473$14687 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:199160$14502_Y + connect \Y $not$libresoc.v:201473$14687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199162$14504 + cell $not $not$libresoc.v:201475$14689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:199162$14504_Y + connect \Y $not$libresoc.v:201475$14689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199164$14506 + cell $not $not$libresoc.v:201477$14691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:199164$14506_Y + connect \Y $not$libresoc.v:201477$14691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199166$14508 + cell $not $not$libresoc.v:201479$14693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:199166$14508_Y + connect \Y $not$libresoc.v:201479$14693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199168$14510 + cell $not $not$libresoc.v:201481$14695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:199168$14510_Y + connect \Y $not$libresoc.v:201481$14695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199170$14512 + cell $not $not$libresoc.v:201483$14697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:199170$14512_Y + connect \Y $not$libresoc.v:201483$14697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199173$14515 + cell $not $not$libresoc.v:201486$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199173$14515_Y + connect \Y $not$libresoc.v:201486$14700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199156$14498 + cell $reduce_or $reduce_or$libresoc.v:201469$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199156$14498_Y + connect \Y $reduce_or$libresoc.v:201469$14683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199158$14500 + cell $reduce_or $reduce_or$libresoc.v:201471$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:199158$14500_Y + connect \Y $reduce_or$libresoc.v:201471$14685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199161$14503 + cell $reduce_or $reduce_or$libresoc.v:201474$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:199161$14503_Y + connect \Y $reduce_or$libresoc.v:201474$14688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199163$14505 + cell $reduce_or $reduce_or$libresoc.v:201476$14690 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:199163$14505_Y + connect \Y $reduce_or$libresoc.v:201476$14690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199165$14507 + cell $reduce_or $reduce_or$libresoc.v:201478$14692 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:199165$14507_Y + connect \Y $reduce_or$libresoc.v:201478$14692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199167$14509 + cell $reduce_or $reduce_or$libresoc.v:201480$14694 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:199167$14509_Y + connect \Y $reduce_or$libresoc.v:201480$14694_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199169$14511 + cell $reduce_or $reduce_or$libresoc.v:201482$14696 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:199169$14511_Y + connect \Y $reduce_or$libresoc.v:201482$14696_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199171$14513 + cell $reduce_or $reduce_or$libresoc.v:201484$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199171$14513_Y + connect \Y $reduce_or$libresoc.v:201484$14698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199172$14514 + cell $reduce_or $reduce_or$libresoc.v:201485$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199172$14514_Y + connect \Y $reduce_or$libresoc.v:201485$14699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199174$14516 + cell $reduce_or $reduce_or$libresoc.v:201487$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199174$14516_Y - end - connect \$7 $not$libresoc.v:199155$14497_Y - connect \$12 $reduce_or$libresoc.v:199156$14498_Y - connect \$11 $not$libresoc.v:199157$14499_Y - connect \$16 $reduce_or$libresoc.v:199158$14500_Y - connect \$15 $not$libresoc.v:199159$14501_Y - connect \$1 $not$libresoc.v:199160$14502_Y - connect \$20 $reduce_or$libresoc.v:199161$14503_Y - connect \$19 $not$libresoc.v:199162$14504_Y - connect \$24 $reduce_or$libresoc.v:199163$14505_Y - connect \$23 $not$libresoc.v:199164$14506_Y - connect \$28 $reduce_or$libresoc.v:199165$14507_Y - connect \$27 $not$libresoc.v:199166$14508_Y - connect \$32 $reduce_or$libresoc.v:199167$14509_Y - connect \$31 $not$libresoc.v:199168$14510_Y - connect \$36 $reduce_or$libresoc.v:199169$14511_Y - connect \$35 $not$libresoc.v:199170$14512_Y - connect \$39 $reduce_or$libresoc.v:199171$14513_Y - connect \$4 $reduce_or$libresoc.v:199172$14514_Y - connect \$3 $not$libresoc.v:199173$14515_Y - connect \$8 $reduce_or$libresoc.v:199174$14516_Y + connect \Y $reduce_or$libresoc.v:201487$14701_Y + end + connect \$7 $not$libresoc.v:201468$14682_Y + connect \$12 $reduce_or$libresoc.v:201469$14683_Y + connect \$11 $not$libresoc.v:201470$14684_Y + connect \$16 $reduce_or$libresoc.v:201471$14685_Y + connect \$15 $not$libresoc.v:201472$14686_Y + connect \$1 $not$libresoc.v:201473$14687_Y + connect \$20 $reduce_or$libresoc.v:201474$14688_Y + connect \$19 $not$libresoc.v:201475$14689_Y + connect \$24 $reduce_or$libresoc.v:201476$14690_Y + connect \$23 $not$libresoc.v:201477$14691_Y + connect \$28 $reduce_or$libresoc.v:201478$14692_Y + connect \$27 $not$libresoc.v:201479$14693_Y + connect \$32 $reduce_or$libresoc.v:201480$14694_Y + connect \$31 $not$libresoc.v:201481$14695_Y + connect \$36 $reduce_or$libresoc.v:201482$14696_Y + connect \$35 $not$libresoc.v:201483$14697_Y + connect \$39 $reduce_or$libresoc.v:201484$14698_Y + connect \$4 $reduce_or$libresoc.v:201485$14699_Y + connect \$3 $not$libresoc.v:201486$14700_Y + connect \$8 $reduce_or$libresoc.v:201487$14701_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -417324,15 +421347,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199192.1-199213.10" +attribute \src "libresoc.v:201505.1-201526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:199207.17-199207.89" - wire $not$libresoc.v:199207$14517_Y - attribute \src "libresoc.v:199208.17-199208.89" - wire $reduce_or$libresoc.v:199208$14518_Y + attribute \src "libresoc.v:201520.17-201520.89" + wire $not$libresoc.v:201520$14702_Y + attribute \src "libresoc.v:201521.17-201521.89" + wire $reduce_or$libresoc.v:201521$14703_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417348,37 +421371,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199207$14517 + cell $not $not$libresoc.v:201520$14702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199207$14517_Y + connect \Y $not$libresoc.v:201520$14702_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199208$14518 + cell $reduce_or $reduce_or$libresoc.v:201521$14703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199208$14518_Y + connect \Y $reduce_or$libresoc.v:201521$14703_Y end - connect \$1 $not$libresoc.v:199207$14517_Y - connect \$3 $reduce_or$libresoc.v:199208$14518_Y + connect \$1 $not$libresoc.v:201520$14702_Y + connect \$3 $reduce_or$libresoc.v:201521$14703_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199217.1-199238.10" +attribute \src "libresoc.v:201530.1-201551.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:199232.17-199232.89" - wire $not$libresoc.v:199232$14519_Y - attribute \src "libresoc.v:199233.17-199233.89" - wire $reduce_or$libresoc.v:199233$14520_Y + attribute \src "libresoc.v:201545.17-201545.89" + wire $not$libresoc.v:201545$14704_Y + attribute \src "libresoc.v:201546.17-201546.89" + wire $reduce_or$libresoc.v:201546$14705_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417394,41 +421417,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199232$14519 + cell $not $not$libresoc.v:201545$14704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199232$14519_Y + connect \Y $not$libresoc.v:201545$14704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199233$14520 + cell $reduce_or $reduce_or$libresoc.v:201546$14705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199233$14520_Y + connect \Y $reduce_or$libresoc.v:201546$14705_Y end - connect \$1 $not$libresoc.v:199232$14519_Y - connect \$3 $reduce_or$libresoc.v:199233$14520_Y + connect \$1 $not$libresoc.v:201545$14704_Y + connect \$3 $reduce_or$libresoc.v:201546$14705_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199242.1-199272.10" +attribute \src "libresoc.v:201555.1-201585.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:199263.17-199263.89" - wire width 2 $not$libresoc.v:199263$14521_Y - attribute \src "libresoc.v:199265.17-199265.91" - wire $not$libresoc.v:199265$14523_Y - attribute \src "libresoc.v:199264.17-199264.103" - wire $reduce_or$libresoc.v:199264$14522_Y - attribute \src "libresoc.v:199266.17-199266.89" - wire $reduce_or$libresoc.v:199266$14524_Y + attribute \src "libresoc.v:201576.17-201576.89" + wire width 2 $not$libresoc.v:201576$14706_Y + attribute \src "libresoc.v:201578.17-201578.91" + wire $not$libresoc.v:201578$14708_Y + attribute \src "libresoc.v:201577.17-201577.103" + wire $reduce_or$libresoc.v:201577$14707_Y + attribute \src "libresoc.v:201579.17-201579.89" + wire $reduce_or$libresoc.v:201579$14709_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417450,64 +421473,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199263$14521 + cell $not $not$libresoc.v:201576$14706 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:199263$14521_Y + connect \Y $not$libresoc.v:201576$14706_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199265$14523 + cell $not $not$libresoc.v:201578$14708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199265$14523_Y + connect \Y $not$libresoc.v:201578$14708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199264$14522 + cell $reduce_or $reduce_or$libresoc.v:201577$14707 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199264$14522_Y + connect \Y $reduce_or$libresoc.v:201577$14707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199266$14524 + cell $reduce_or $reduce_or$libresoc.v:201579$14709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199266$14524_Y + connect \Y $reduce_or$libresoc.v:201579$14709_Y end - connect \$1 $not$libresoc.v:199263$14521_Y - connect \$4 $reduce_or$libresoc.v:199264$14522_Y - connect \$3 $not$libresoc.v:199265$14523_Y - connect \$7 $reduce_or$libresoc.v:199266$14524_Y + connect \$1 $not$libresoc.v:201576$14706_Y + connect \$4 $reduce_or$libresoc.v:201577$14707_Y + connect \$3 $not$libresoc.v:201578$14708_Y + connect \$7 $reduce_or$libresoc.v:201579$14709_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199276.1-199315.10" +attribute \src "libresoc.v:201589.1-201628.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:199303.17-199303.91" - wire $not$libresoc.v:199303$14525_Y - attribute \src "libresoc.v:199305.17-199305.89" - wire width 3 $not$libresoc.v:199305$14527_Y - attribute \src "libresoc.v:199307.17-199307.91" - wire $not$libresoc.v:199307$14529_Y - attribute \src "libresoc.v:199304.18-199304.90" - wire $reduce_or$libresoc.v:199304$14526_Y - attribute \src "libresoc.v:199306.17-199306.103" - wire $reduce_or$libresoc.v:199306$14528_Y - attribute \src "libresoc.v:199308.17-199308.105" - wire $reduce_or$libresoc.v:199308$14530_Y + attribute \src "libresoc.v:201616.17-201616.91" + wire $not$libresoc.v:201616$14710_Y + attribute \src "libresoc.v:201618.17-201618.89" + wire width 3 $not$libresoc.v:201618$14712_Y + attribute \src "libresoc.v:201620.17-201620.91" + wire $not$libresoc.v:201620$14714_Y + attribute \src "libresoc.v:201617.18-201617.90" + wire $reduce_or$libresoc.v:201617$14711_Y + attribute \src "libresoc.v:201619.17-201619.103" + wire $reduce_or$libresoc.v:201619$14713_Y + attribute \src "libresoc.v:201621.17-201621.105" + wire $reduce_or$libresoc.v:201621$14715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417535,59 +421558,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199303$14525 + cell $not $not$libresoc.v:201616$14710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199303$14525_Y + connect \Y $not$libresoc.v:201616$14710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199305$14527 + cell $not $not$libresoc.v:201618$14712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:199305$14527_Y + connect \Y $not$libresoc.v:201618$14712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199307$14529 + cell $not $not$libresoc.v:201620$14714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199307$14529_Y + connect \Y $not$libresoc.v:201620$14714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199304$14526 + cell $reduce_or $reduce_or$libresoc.v:201617$14711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199304$14526_Y + connect \Y $reduce_or$libresoc.v:201617$14711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199306$14528 + cell $reduce_or $reduce_or$libresoc.v:201619$14713 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199306$14528_Y + connect \Y $reduce_or$libresoc.v:201619$14713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199308$14530 + cell $reduce_or $reduce_or$libresoc.v:201621$14715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199308$14530_Y - end - connect \$7 $not$libresoc.v:199303$14525_Y - connect \$11 $reduce_or$libresoc.v:199304$14526_Y - connect \$1 $not$libresoc.v:199305$14527_Y - connect \$4 $reduce_or$libresoc.v:199306$14528_Y - connect \$3 $not$libresoc.v:199307$14529_Y - connect \$8 $reduce_or$libresoc.v:199308$14530_Y + connect \Y $reduce_or$libresoc.v:201621$14715_Y + end + connect \$7 $not$libresoc.v:201616$14710_Y + connect \$11 $reduce_or$libresoc.v:201617$14711_Y + connect \$1 $not$libresoc.v:201618$14712_Y + connect \$4 $reduce_or$libresoc.v:201619$14713_Y + connect \$3 $not$libresoc.v:201620$14714_Y + connect \$8 $reduce_or$libresoc.v:201621$14715_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -417595,27 +421618,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199319.1-199367.10" +attribute \src "libresoc.v:201632.1-201680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:199352.17-199352.91" - wire $not$libresoc.v:199352$14531_Y - attribute \src "libresoc.v:199354.18-199354.93" - wire $not$libresoc.v:199354$14533_Y - attribute \src "libresoc.v:199356.17-199356.89" - wire width 4 $not$libresoc.v:199356$14535_Y - attribute \src "libresoc.v:199358.17-199358.91" - wire $not$libresoc.v:199358$14537_Y - attribute \src "libresoc.v:199353.18-199353.106" - wire $reduce_or$libresoc.v:199353$14532_Y - attribute \src "libresoc.v:199355.18-199355.90" - wire $reduce_or$libresoc.v:199355$14534_Y - attribute \src "libresoc.v:199357.17-199357.103" - wire $reduce_or$libresoc.v:199357$14536_Y - attribute \src "libresoc.v:199359.17-199359.105" - wire $reduce_or$libresoc.v:199359$14538_Y + attribute \src "libresoc.v:201665.17-201665.91" + wire $not$libresoc.v:201665$14716_Y + attribute \src "libresoc.v:201667.18-201667.93" + wire $not$libresoc.v:201667$14718_Y + attribute \src "libresoc.v:201669.17-201669.89" + wire width 4 $not$libresoc.v:201669$14720_Y + attribute \src "libresoc.v:201671.17-201671.91" + wire $not$libresoc.v:201671$14722_Y + attribute \src "libresoc.v:201666.18-201666.106" + wire $reduce_or$libresoc.v:201666$14717_Y + attribute \src "libresoc.v:201668.18-201668.90" + wire $reduce_or$libresoc.v:201668$14719_Y + attribute \src "libresoc.v:201670.17-201670.103" + wire $reduce_or$libresoc.v:201670$14721_Y + attribute \src "libresoc.v:201672.17-201672.105" + wire $reduce_or$libresoc.v:201672$14723_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417649,77 +421672,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199352$14531 + cell $not $not$libresoc.v:201665$14716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199352$14531_Y + connect \Y $not$libresoc.v:201665$14716_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199354$14533 + cell $not $not$libresoc.v:201667$14718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199354$14533_Y + connect \Y $not$libresoc.v:201667$14718_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199356$14535 + cell $not $not$libresoc.v:201669$14720 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:199356$14535_Y + connect \Y $not$libresoc.v:201669$14720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199358$14537 + cell $not $not$libresoc.v:201671$14722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199358$14537_Y + connect \Y $not$libresoc.v:201671$14722_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199353$14532 + cell $reduce_or $reduce_or$libresoc.v:201666$14717 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199353$14532_Y + connect \Y $reduce_or$libresoc.v:201666$14717_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199355$14534 + cell $reduce_or $reduce_or$libresoc.v:201668$14719 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199355$14534_Y + connect \Y $reduce_or$libresoc.v:201668$14719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199357$14536 + cell $reduce_or $reduce_or$libresoc.v:201670$14721 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199357$14536_Y + connect \Y $reduce_or$libresoc.v:201670$14721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199359$14538 + cell $reduce_or $reduce_or$libresoc.v:201672$14723 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199359$14538_Y - end - connect \$7 $not$libresoc.v:199352$14531_Y - connect \$12 $reduce_or$libresoc.v:199353$14532_Y - connect \$11 $not$libresoc.v:199354$14533_Y - connect \$15 $reduce_or$libresoc.v:199355$14534_Y - connect \$1 $not$libresoc.v:199356$14535_Y - connect \$4 $reduce_or$libresoc.v:199357$14536_Y - connect \$3 $not$libresoc.v:199358$14537_Y - connect \$8 $reduce_or$libresoc.v:199359$14538_Y + connect \Y $reduce_or$libresoc.v:201672$14723_Y + end + connect \$7 $not$libresoc.v:201665$14716_Y + connect \$12 $reduce_or$libresoc.v:201666$14717_Y + connect \$11 $not$libresoc.v:201667$14718_Y + connect \$15 $reduce_or$libresoc.v:201668$14719_Y + connect \$1 $not$libresoc.v:201669$14720_Y + connect \$4 $reduce_or$libresoc.v:201670$14721_Y + connect \$3 $not$libresoc.v:201671$14722_Y + connect \$8 $reduce_or$libresoc.v:201672$14723_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417728,27 +421751,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199371.1-199419.10" +attribute \src "libresoc.v:201684.1-201732.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:199404.17-199404.91" - wire $not$libresoc.v:199404$14539_Y - attribute \src "libresoc.v:199406.18-199406.93" - wire $not$libresoc.v:199406$14541_Y - attribute \src "libresoc.v:199408.17-199408.89" - wire width 4 $not$libresoc.v:199408$14543_Y - attribute \src "libresoc.v:199410.17-199410.91" - wire $not$libresoc.v:199410$14545_Y - attribute \src "libresoc.v:199405.18-199405.106" - wire $reduce_or$libresoc.v:199405$14540_Y - attribute \src "libresoc.v:199407.18-199407.90" - wire $reduce_or$libresoc.v:199407$14542_Y - attribute \src "libresoc.v:199409.17-199409.103" - wire $reduce_or$libresoc.v:199409$14544_Y - attribute \src "libresoc.v:199411.17-199411.105" - wire $reduce_or$libresoc.v:199411$14546_Y + attribute \src "libresoc.v:201717.17-201717.91" + wire $not$libresoc.v:201717$14724_Y + attribute \src "libresoc.v:201719.18-201719.93" + wire $not$libresoc.v:201719$14726_Y + attribute \src "libresoc.v:201721.17-201721.89" + wire width 4 $not$libresoc.v:201721$14728_Y + attribute \src "libresoc.v:201723.17-201723.91" + wire $not$libresoc.v:201723$14730_Y + attribute \src "libresoc.v:201718.18-201718.106" + wire $reduce_or$libresoc.v:201718$14725_Y + attribute \src "libresoc.v:201720.18-201720.90" + wire $reduce_or$libresoc.v:201720$14727_Y + attribute \src "libresoc.v:201722.17-201722.103" + wire $reduce_or$libresoc.v:201722$14729_Y + attribute \src "libresoc.v:201724.17-201724.105" + wire $reduce_or$libresoc.v:201724$14731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417782,77 +421805,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199404$14539 + cell $not $not$libresoc.v:201717$14724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199404$14539_Y + connect \Y $not$libresoc.v:201717$14724_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199406$14541 + cell $not $not$libresoc.v:201719$14726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199406$14541_Y + connect \Y $not$libresoc.v:201719$14726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199408$14543 + cell $not $not$libresoc.v:201721$14728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:199408$14543_Y + connect \Y $not$libresoc.v:201721$14728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199410$14545 + cell $not $not$libresoc.v:201723$14730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199410$14545_Y + connect \Y $not$libresoc.v:201723$14730_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199405$14540 + cell $reduce_or $reduce_or$libresoc.v:201718$14725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199405$14540_Y + connect \Y $reduce_or$libresoc.v:201718$14725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199407$14542 + cell $reduce_or $reduce_or$libresoc.v:201720$14727 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199407$14542_Y + connect \Y $reduce_or$libresoc.v:201720$14727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199409$14544 + cell $reduce_or $reduce_or$libresoc.v:201722$14729 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199409$14544_Y + connect \Y $reduce_or$libresoc.v:201722$14729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199411$14546 + cell $reduce_or $reduce_or$libresoc.v:201724$14731 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199411$14546_Y - end - connect \$7 $not$libresoc.v:199404$14539_Y - connect \$12 $reduce_or$libresoc.v:199405$14540_Y - connect \$11 $not$libresoc.v:199406$14541_Y - connect \$15 $reduce_or$libresoc.v:199407$14542_Y - connect \$1 $not$libresoc.v:199408$14543_Y - connect \$4 $reduce_or$libresoc.v:199409$14544_Y - connect \$3 $not$libresoc.v:199410$14545_Y - connect \$8 $reduce_or$libresoc.v:199411$14546_Y + connect \Y $reduce_or$libresoc.v:201724$14731_Y + end + connect \$7 $not$libresoc.v:201717$14724_Y + connect \$12 $reduce_or$libresoc.v:201718$14725_Y + connect \$11 $not$libresoc.v:201719$14726_Y + connect \$15 $reduce_or$libresoc.v:201720$14727_Y + connect \$1 $not$libresoc.v:201721$14728_Y + connect \$4 $reduce_or$libresoc.v:201722$14729_Y + connect \$3 $not$libresoc.v:201723$14730_Y + connect \$8 $reduce_or$libresoc.v:201724$14731_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417861,67 +421884,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199423.1-199743.10" +attribute \src "libresoc.v:201736.1-202056.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:199424.7-199424.20" + attribute \src "libresoc.v:201737.7-201737.20" wire $0\initial[0:0] - attribute \src "libresoc.v:199703.3-199711.6" - wire width 3 $0\ren_delay$11$next[2:0]$14570 - attribute \src "libresoc.v:199601.3-199602.43" - wire width 3 $0\ren_delay$11[2:0]$14559 - attribute \src "libresoc.v:199560.13-199560.34" - wire width 3 $0\ren_delay$11[2:0]$14576 - attribute \src "libresoc.v:199665.3-199673.6" - wire width 3 $0\ren_delay$18$next[2:0]$14562 - attribute \src "libresoc.v:199599.3-199600.43" - wire width 3 $0\ren_delay$18[2:0]$14557 - attribute \src "libresoc.v:199564.13-199564.34" - wire width 3 $0\ren_delay$18[2:0]$14578 - attribute \src "libresoc.v:199684.3-199692.6" - wire width 3 $0\ren_delay$next[2:0]$14566 - attribute \src "libresoc.v:199603.3-199604.35" + attribute \src "libresoc.v:202016.3-202024.6" + wire width 3 $0\ren_delay$11$next[2:0]$14755 + attribute \src "libresoc.v:201914.3-201915.43" + wire width 3 $0\ren_delay$11[2:0]$14744 + attribute \src "libresoc.v:201873.13-201873.34" + wire width 3 $0\ren_delay$11[2:0]$14761 + attribute \src "libresoc.v:201978.3-201986.6" + wire width 3 $0\ren_delay$18$next[2:0]$14747 + attribute \src "libresoc.v:201912.3-201913.43" + wire width 3 $0\ren_delay$18[2:0]$14742 + attribute \src "libresoc.v:201877.13-201877.34" + wire width 3 $0\ren_delay$18[2:0]$14763 + attribute \src "libresoc.v:201997.3-202005.6" + wire width 3 $0\ren_delay$next[2:0]$14751 + attribute \src "libresoc.v:201916.3-201917.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:199693.3-199702.6" + attribute \src "libresoc.v:202006.3-202015.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:199712.3-199721.6" + attribute \src "libresoc.v:202025.3-202034.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:199674.3-199683.6" + attribute \src "libresoc.v:201987.3-201996.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:199703.3-199711.6" - wire width 3 $1\ren_delay$11$next[2:0]$14571 - attribute \src "libresoc.v:199665.3-199673.6" - wire width 3 $1\ren_delay$18$next[2:0]$14563 - attribute \src "libresoc.v:199684.3-199692.6" - wire width 3 $1\ren_delay$next[2:0]$14567 - attribute \src "libresoc.v:199558.13-199558.29" + attribute \src "libresoc.v:202016.3-202024.6" + wire width 3 $1\ren_delay$11$next[2:0]$14756 + attribute \src "libresoc.v:201978.3-201986.6" + wire width 3 $1\ren_delay$18$next[2:0]$14748 + attribute \src "libresoc.v:201997.3-202005.6" + wire width 3 $1\ren_delay$next[2:0]$14752 + attribute \src "libresoc.v:201871.13-201871.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:199693.3-199702.6" + attribute \src "libresoc.v:202006.3-202015.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:199712.3-199721.6" + attribute \src "libresoc.v:202025.3-202034.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:199674.3-199683.6" + attribute \src "libresoc.v:201987.3-201996.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:199590.17-199590.109" - wire width 2 $or$libresoc.v:199590$14547_Y - attribute \src "libresoc.v:199592.18-199592.126" - wire width 2 $or$libresoc.v:199592$14549_Y - attribute \src "libresoc.v:199593.18-199593.111" - wire width 2 $or$libresoc.v:199593$14550_Y - attribute \src "libresoc.v:199595.18-199595.126" - wire width 2 $or$libresoc.v:199595$14552_Y - attribute \src "libresoc.v:199596.18-199596.111" - wire width 2 $or$libresoc.v:199596$14553_Y - attribute \src "libresoc.v:199598.17-199598.125" - wire width 2 $or$libresoc.v:199598$14555_Y - attribute \src "libresoc.v:199591.18-199591.100" - wire $reduce_or$libresoc.v:199591$14548_Y - attribute \src "libresoc.v:199594.18-199594.100" - wire $reduce_or$libresoc.v:199594$14551_Y - attribute \src "libresoc.v:199597.17-199597.95" - wire $reduce_or$libresoc.v:199597$14554_Y + attribute \src "libresoc.v:201903.17-201903.109" + wire width 2 $or$libresoc.v:201903$14732_Y + attribute \src "libresoc.v:201905.18-201905.126" + wire width 2 $or$libresoc.v:201905$14734_Y + attribute \src "libresoc.v:201906.18-201906.111" + wire width 2 $or$libresoc.v:201906$14735_Y + attribute \src "libresoc.v:201908.18-201908.126" + wire width 2 $or$libresoc.v:201908$14737_Y + attribute \src "libresoc.v:201909.18-201909.111" + wire width 2 $or$libresoc.v:201909$14738_Y + attribute \src "libresoc.v:201911.17-201911.125" + wire width 2 $or$libresoc.v:201911$14740_Y + attribute \src "libresoc.v:201904.18-201904.100" + wire $reduce_or$libresoc.v:201904$14733_Y + attribute \src "libresoc.v:201907.18-201907.100" + wire $reduce_or$libresoc.v:201907$14736_Y + attribute \src "libresoc.v:201910.17-201910.95" + wire $reduce_or$libresoc.v:201910$14739_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -417940,9 +421963,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -417958,7 +421981,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:199424.7-199424.15" + attribute \src "libresoc.v:201737.7-201737.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -418087,7 +422110,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199590$14547 + cell $or $or$libresoc.v:201903$14732 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418095,10 +422118,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:199590$14547_Y + connect \Y $or$libresoc.v:201903$14732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199592$14549 + cell $or $or$libresoc.v:201905$14734 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418106,10 +422129,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:199592$14549_Y + connect \Y $or$libresoc.v:201905$14734_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199593$14550 + cell $or $or$libresoc.v:201906$14735 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418117,10 +422140,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:199593$14550_Y + connect \Y $or$libresoc.v:201906$14735_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199595$14552 + cell $or $or$libresoc.v:201908$14737 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418128,10 +422151,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:199595$14552_Y + connect \Y $or$libresoc.v:201908$14737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199596$14553 + cell $or $or$libresoc.v:201909$14738 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418139,10 +422162,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:199596$14553_Y + connect \Y $or$libresoc.v:201909$14738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199598$14555 + cell $or $or$libresoc.v:201911$14740 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418150,34 +422173,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:199598$14555_Y + connect \Y $or$libresoc.v:201911$14740_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199591$14548 + cell $reduce_or $reduce_or$libresoc.v:201904$14733 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:199591$14548_Y + connect \Y $reduce_or$libresoc.v:201904$14733_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199594$14551 + cell $reduce_or $reduce_or$libresoc.v:201907$14736 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:199594$14551_Y + connect \Y $reduce_or$libresoc.v:201907$14736_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199597$14554 + cell $reduce_or $reduce_or$libresoc.v:201910$14739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:199597$14554_Y + connect \Y $reduce_or$libresoc.v:201910$14739_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:199605.15-199624.4" + attribute \src "libresoc.v:201918.15-201937.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418199,7 +422222,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:199625.15-199644.4" + attribute \src "libresoc.v:201938.15-201957.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418221,7 +422244,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:199645.15-199664.4" + attribute \src "libresoc.v:201958.15-201977.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418242,67 +422265,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:199424.7-199424.20" - process $proc$libresoc.v:199424$14573 + attribute \src "libresoc.v:201737.7-201737.20" + process $proc$libresoc.v:201737$14758 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199558.13-199558.29" - process $proc$libresoc.v:199558$14574 + attribute \src "libresoc.v:201871.13-201871.29" + process $proc$libresoc.v:201871$14759 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:199560.13-199560.34" - process $proc$libresoc.v:199560$14575 + attribute \src "libresoc.v:201873.13-201873.34" + process $proc$libresoc.v:201873$14760 assign { } { } - assign $0\ren_delay$11[2:0]$14576 3'000 + assign $0\ren_delay$11[2:0]$14761 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14576 + update \ren_delay$11 $0\ren_delay$11[2:0]$14761 end - attribute \src "libresoc.v:199564.13-199564.34" - process $proc$libresoc.v:199564$14577 + attribute \src "libresoc.v:201877.13-201877.34" + process $proc$libresoc.v:201877$14762 assign { } { } - assign $0\ren_delay$18[2:0]$14578 3'000 + assign $0\ren_delay$18[2:0]$14763 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14578 + update \ren_delay$18 $0\ren_delay$18[2:0]$14763 end - attribute \src "libresoc.v:199599.3-199600.43" - process $proc$libresoc.v:199599$14556 + attribute \src "libresoc.v:201912.3-201913.43" + process $proc$libresoc.v:201912$14741 assign { } { } - assign $0\ren_delay$18[2:0]$14557 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14742 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14557 + update \ren_delay$18 $0\ren_delay$18[2:0]$14742 end - attribute \src "libresoc.v:199601.3-199602.43" - process $proc$libresoc.v:199601$14558 + attribute \src "libresoc.v:201914.3-201915.43" + process $proc$libresoc.v:201914$14743 assign { } { } - assign $0\ren_delay$11[2:0]$14559 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14744 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14559 + update \ren_delay$11 $0\ren_delay$11[2:0]$14744 end - attribute \src "libresoc.v:199603.3-199604.35" - process $proc$libresoc.v:199603$14560 + attribute \src "libresoc.v:201916.3-201917.35" + process $proc$libresoc.v:201916$14745 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:199665.3-199673.6" - process $proc$libresoc.v:199665$14561 + attribute \src "libresoc.v:201978.3-201986.6" + process $proc$libresoc.v:201978$14746 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14562 $1\ren_delay$18$next[2:0]$14563 - attribute \src "libresoc.v:199666.5-199666.29" + assign $0\ren_delay$18$next[2:0]$14747 $1\ren_delay$18$next[2:0]$14748 + attribute \src "libresoc.v:201979.5-201979.29" switch \initial - attribute \src "libresoc.v:199666.9-199666.17" + attribute \src "libresoc.v:201979.9-201979.17" case 1'1 case end @@ -418311,21 +422334,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14563 3'000 + assign $1\ren_delay$18$next[2:0]$14748 3'000 case - assign $1\ren_delay$18$next[2:0]$14563 \src3__ren + assign $1\ren_delay$18$next[2:0]$14748 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14562 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14747 end - attribute \src "libresoc.v:199674.3-199683.6" - process $proc$libresoc.v:199674$14564 + attribute \src "libresoc.v:201987.3-201996.6" + process $proc$libresoc.v:201987$14749 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:199675.5-199675.29" + attribute \src "libresoc.v:201988.5-201988.29" switch \initial - attribute \src "libresoc.v:199675.9-199675.17" + attribute \src "libresoc.v:201988.9-201988.17" case 1'1 case end @@ -418341,14 +422364,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:199684.3-199692.6" - process $proc$libresoc.v:199684$14565 + attribute \src "libresoc.v:201997.3-202005.6" + process $proc$libresoc.v:201997$14750 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14566 $1\ren_delay$next[2:0]$14567 - attribute \src "libresoc.v:199685.5-199685.29" + assign $0\ren_delay$next[2:0]$14751 $1\ren_delay$next[2:0]$14752 + attribute \src "libresoc.v:201998.5-201998.29" switch \initial - attribute \src "libresoc.v:199685.9-199685.17" + attribute \src "libresoc.v:201998.9-201998.17" case 1'1 case end @@ -418357,21 +422380,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14567 3'000 + assign $1\ren_delay$next[2:0]$14752 3'000 case - assign $1\ren_delay$next[2:0]$14567 \src1__ren + assign $1\ren_delay$next[2:0]$14752 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14566 + update \ren_delay$next $0\ren_delay$next[2:0]$14751 end - attribute \src "libresoc.v:199693.3-199702.6" - process $proc$libresoc.v:199693$14568 + attribute \src "libresoc.v:202006.3-202015.6" + process $proc$libresoc.v:202006$14753 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:199694.5-199694.29" + attribute \src "libresoc.v:202007.5-202007.29" switch \initial - attribute \src "libresoc.v:199694.9-199694.17" + attribute \src "libresoc.v:202007.9-202007.17" case 1'1 case end @@ -418387,14 +422410,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:199703.3-199711.6" - process $proc$libresoc.v:199703$14569 + attribute \src "libresoc.v:202016.3-202024.6" + process $proc$libresoc.v:202016$14754 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14570 $1\ren_delay$11$next[2:0]$14571 - attribute \src "libresoc.v:199704.5-199704.29" + assign $0\ren_delay$11$next[2:0]$14755 $1\ren_delay$11$next[2:0]$14756 + attribute \src "libresoc.v:202017.5-202017.29" switch \initial - attribute \src "libresoc.v:199704.9-199704.17" + attribute \src "libresoc.v:202017.9-202017.17" case 1'1 case end @@ -418403,21 +422426,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14571 3'000 + assign $1\ren_delay$11$next[2:0]$14756 3'000 case - assign $1\ren_delay$11$next[2:0]$14571 \src2__ren + assign $1\ren_delay$11$next[2:0]$14756 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14570 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14755 end - attribute \src "libresoc.v:199712.3-199721.6" - process $proc$libresoc.v:199712$14572 + attribute \src "libresoc.v:202025.3-202034.6" + process $proc$libresoc.v:202025$14757 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:199713.5-199713.29" + attribute \src "libresoc.v:202026.5-202026.29" switch \initial - attribute \src "libresoc.v:199713.9-199713.17" + attribute \src "libresoc.v:202026.9-202026.17" case 1'1 case end @@ -418433,15 +422456,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:199590$14547_Y - connect \$12 $reduce_or$libresoc.v:199591$14548_Y - connect \$14 $or$libresoc.v:199592$14549_Y - connect \$16 $or$libresoc.v:199593$14550_Y - connect \$19 $reduce_or$libresoc.v:199594$14551_Y - connect \$21 $or$libresoc.v:199595$14552_Y - connect \$23 $or$libresoc.v:199596$14553_Y - connect \$5 $reduce_or$libresoc.v:199597$14554_Y - connect \$7 $or$libresoc.v:199598$14555_Y + connect \$9 $or$libresoc.v:201903$14732_Y + connect \$12 $reduce_or$libresoc.v:201904$14733_Y + connect \$14 $or$libresoc.v:201905$14734_Y + connect \$16 $or$libresoc.v:201906$14735_Y + connect \$19 $reduce_or$libresoc.v:201907$14736_Y + connect \$21 $or$libresoc.v:201908$14737_Y + connect \$23 $or$libresoc.v:201909$14738_Y + connect \$5 $reduce_or$libresoc.v:201910$14739_Y + connect \$7 $or$libresoc.v:201911$14740_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -418464,153 +422487,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:199747.1-200061.10" +attribute \src "libresoc.v:202060.1-202374.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:199976.3-199984.6" - wire $0\core_irq_o$next[0:0]$14614 - attribute \src "libresoc.v:199867.3-199868.37" + attribute \src "libresoc.v:202289.3-202297.6" + wire $0\core_irq_o$next[0:0]$14799 + attribute \src "libresoc.v:202180.3-202181.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $0\cppr$10[7:0]$14618 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $0\cppr$next[7:0]$14597 - attribute \src "libresoc.v:199871.3-199872.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\cppr$10[7:0]$14803 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\cppr$next[7:0]$14782 + attribute \src "libresoc.v:202184.3-202185.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:199985.3-199994.6" + attribute \src "libresoc.v:202298.3-202307.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199748.7-199748.20" + attribute \src "libresoc.v:202061.7-202061.20" wire $0\initial[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $0\irq$12[0:0]$14619 - attribute \src "libresoc.v:199881.3-199896.6" - wire $0\irq$next[0:0]$14598 - attribute \src "libresoc.v:199875.3-199876.23" + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\irq$12[0:0]$14804 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\irq$next[0:0]$14783 + attribute \src "libresoc.v:202188.3-202189.23" wire $0\irq[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $0\mfrr$11[7:0]$14620 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $0\mfrr$next[7:0]$14599 - attribute \src "libresoc.v:199873.3-199874.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\mfrr$11[7:0]$14805 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\mfrr$next[7:0]$14784 + attribute \src "libresoc.v:202186.3-202187.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:199964.3-199975.6" + attribute \src "libresoc.v:202277.3-202288.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:199954.3-199963.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $0\wb_ack$14[0:0]$14621 - attribute \src "libresoc.v:199881.3-199896.6" - wire $0\wb_ack$next[0:0]$14600 - attribute \src "libresoc.v:199879.3-199880.29" + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\wb_ack$14[0:0]$14806 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\wb_ack$next[0:0]$14785 + attribute \src "libresoc.v:202192.3-202193.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 32 $0\wb_rd_data$13[31:0]$14622 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 32 $0\wb_rd_data$next[31:0]$14601 - attribute \src "libresoc.v:199877.3-199878.37" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 32 $0\wb_rd_data$13[31:0]$14807 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $0\wb_rd_data$next[31:0]$14786 + attribute \src "libresoc.v:202190.3-202191.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202210.3-202237.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $0\xisr$9[23:0]$14623 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 24 $0\xisr$next[23:0]$14602 - attribute \src "libresoc.v:199869.3-199870.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $0\xisr$9[23:0]$14808 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $0\xisr$next[23:0]$14787 + attribute \src "libresoc.v:202182.3-202183.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:199976.3-199984.6" - wire $1\core_irq_o$next[0:0]$14615 - attribute \src "libresoc.v:199777.7-199777.24" + attribute \src "libresoc.v:202289.3-202297.6" + wire $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202090.7-202090.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $1\cppr$10[7:0]$14624 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $1\cppr$next[7:0]$14603 - attribute \src "libresoc.v:199781.13-199781.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\cppr$10[7:0]$14809 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\cppr$next[7:0]$14788 + attribute \src "libresoc.v:202094.13-202094.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:199985.3-199994.6" + attribute \src "libresoc.v:202298.3-202307.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $1\irq$12[0:0]$14634 - attribute \src "libresoc.v:199881.3-199896.6" - wire $1\irq$next[0:0]$14604 - attribute \src "libresoc.v:199810.7-199810.17" + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\irq$next[0:0]$14789 + attribute \src "libresoc.v:202123.7-202123.17" wire $1\irq[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $1\mfrr$11[7:0]$14625 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $1\mfrr$next[7:0]$14605 - attribute \src "libresoc.v:199818.13-199818.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\mfrr$11[7:0]$14810 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\mfrr$next[7:0]$14790 + attribute \src "libresoc.v:202131.13-202131.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:199964.3-199975.6" + attribute \src "libresoc.v:202277.3-202288.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:199954.3-199963.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $1\wb_ack$14[0:0]$14626 - attribute \src "libresoc.v:199881.3-199896.6" - wire $1\wb_ack$next[0:0]$14606 - attribute \src "libresoc.v:199832.7-199832.20" + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\wb_ack$14[0:0]$14811 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\wb_ack$next[0:0]$14791 + attribute \src "libresoc.v:202145.7-202145.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:199881.3-199896.6" - wire width 32 $1\wb_rd_data$next[31:0]$14607 - attribute \src "libresoc.v:199840.14-199840.32" + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $1\wb_rd_data$next[31:0]$14792 + attribute \src "libresoc.v:202153.14-202153.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202210.3-202237.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $1\xisr$9[23:0]$14631 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 24 $1\xisr$next[23:0]$14608 - attribute \src "libresoc.v:199850.14-199850.31" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $1\xisr$9[23:0]$14816 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202163.14-202163.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $2\cppr$10[7:0]$14627 - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $2\mfrr$11[7:0]$14628 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\cppr$10[7:0]$14812 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\mfrr$11[7:0]$14813 + attribute \src "libresoc.v:202210.3-202237.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $2\xisr$9[23:0]$14632 - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $2\xisr$9[23:0]$14817 + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $3\cppr$10[7:0]$14629 - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $3\mfrr$11[7:0]$14630 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\cppr$10[7:0]$14814 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\mfrr$11[7:0]$14815 + attribute \src "libresoc.v:202210.3-202237.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $4\cppr$10[7:0]$14633 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $4\cppr$10[7:0]$14818 + attribute \src "libresoc.v:202210.3-202237.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199857.18-199857.116" - wire $and$libresoc.v:199857$14579_Y - attribute \src "libresoc.v:199861.18-199861.116" - wire $and$libresoc.v:199861$14583_Y - attribute \src "libresoc.v:199863.18-199863.116" - wire $and$libresoc.v:199863$14585_Y - attribute \src "libresoc.v:199866.17-199866.109" - wire $and$libresoc.v:199866$14588_Y - attribute \src "libresoc.v:199862.18-199862.110" - wire $eq$libresoc.v:199862$14584_Y - attribute \src "libresoc.v:199859.18-199859.114" - wire $lt$libresoc.v:199859$14581_Y - attribute \src "libresoc.v:199860.18-199860.109" - wire $lt$libresoc.v:199860$14582_Y - attribute \src "libresoc.v:199865.18-199865.114" - wire $lt$libresoc.v:199865$14587_Y - attribute \src "libresoc.v:199858.18-199858.109" - wire $ne$libresoc.v:199858$14580_Y - attribute \src "libresoc.v:199864.18-199864.109" - wire $ne$libresoc.v:199864$14586_Y + attribute \src "libresoc.v:202170.18-202170.116" + wire $and$libresoc.v:202170$14764_Y + attribute \src "libresoc.v:202174.18-202174.116" + wire $and$libresoc.v:202174$14768_Y + attribute \src "libresoc.v:202176.18-202176.116" + wire $and$libresoc.v:202176$14770_Y + attribute \src "libresoc.v:202179.17-202179.109" + wire $and$libresoc.v:202179$14773_Y + attribute \src "libresoc.v:202175.18-202175.110" + wire $eq$libresoc.v:202175$14769_Y + attribute \src "libresoc.v:202172.18-202172.114" + wire $lt$libresoc.v:202172$14766_Y + attribute \src "libresoc.v:202173.18-202173.109" + wire $lt$libresoc.v:202173$14767_Y + attribute \src "libresoc.v:202178.18-202178.114" + wire $lt$libresoc.v:202178$14772_Y + attribute \src "libresoc.v:202171.18-202171.109" + wire $ne$libresoc.v:202171$14765_Y + attribute \src "libresoc.v:202177.18-202177.109" + wire $ne$libresoc.v:202177$14771_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -418635,7 +422658,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -418669,7 +422692,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:199748.7-199748.15" + attribute \src "libresoc.v:202061.7-202061.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -418691,7 +422714,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -418720,7 +422743,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199857$14579 + cell $and $and$libresoc.v:202170$14764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418728,10 +422751,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199857$14579_Y + connect \Y $and$libresoc.v:202170$14764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199861$14583 + cell $and $and$libresoc.v:202174$14768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418739,10 +422762,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199861$14583_Y + connect \Y $and$libresoc.v:202174$14768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199863$14585 + cell $and $and$libresoc.v:202176$14770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418750,10 +422773,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199863$14585_Y + connect \Y $and$libresoc.v:202176$14770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:199866$14588 + cell $and $and$libresoc.v:202179$14773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418761,10 +422784,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:199866$14588_Y + connect \Y $and$libresoc.v:202179$14773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:199862$14584 + cell $eq $eq$libresoc.v:202175$14769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418772,10 +422795,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:199862$14584_Y + connect \Y $eq$libresoc.v:202175$14769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:199859$14581 + cell $lt $lt$libresoc.v:202172$14766 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418783,10 +422806,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:199859$14581_Y + connect \Y $lt$libresoc.v:202172$14766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:199860$14582 + cell $lt $lt$libresoc.v:202173$14767 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418794,10 +422817,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:199860$14582_Y + connect \Y $lt$libresoc.v:202173$14767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:199865$14587 + cell $lt $lt$libresoc.v:202178$14772 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418805,10 +422828,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:199865$14587_Y + connect \Y $lt$libresoc.v:202178$14772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:199858$14580 + cell $ne $ne$libresoc.v:202171$14765 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418816,10 +422839,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:199858$14580_Y + connect \Y $ne$libresoc.v:202171$14765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:199864$14586 + cell $ne $ne$libresoc.v:202177$14771 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418827,123 +422850,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:199864$14586_Y + connect \Y $ne$libresoc.v:202177$14771_Y end - attribute \src "libresoc.v:199748.7-199748.20" - process $proc$libresoc.v:199748$14635 + attribute \src "libresoc.v:202061.7-202061.20" + process $proc$libresoc.v:202061$14820 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199777.7-199777.24" - process $proc$libresoc.v:199777$14636 + attribute \src "libresoc.v:202090.7-202090.24" + process $proc$libresoc.v:202090$14821 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:199781.13-199781.25" - process $proc$libresoc.v:199781$14637 + attribute \src "libresoc.v:202094.13-202094.25" + process $proc$libresoc.v:202094$14822 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:199810.7-199810.17" - process $proc$libresoc.v:199810$14638 + attribute \src "libresoc.v:202123.7-202123.17" + process $proc$libresoc.v:202123$14823 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:199818.13-199818.25" - process $proc$libresoc.v:199818$14639 + attribute \src "libresoc.v:202131.13-202131.25" + process $proc$libresoc.v:202131$14824 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:199832.7-199832.20" - process $proc$libresoc.v:199832$14640 + attribute \src "libresoc.v:202145.7-202145.20" + process $proc$libresoc.v:202145$14825 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:199840.14-199840.32" - process $proc$libresoc.v:199840$14641 + attribute \src "libresoc.v:202153.14-202153.32" + process $proc$libresoc.v:202153$14826 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:199850.14-199850.31" - process $proc$libresoc.v:199850$14642 + attribute \src "libresoc.v:202163.14-202163.31" + process $proc$libresoc.v:202163$14827 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:199867.3-199868.37" - process $proc$libresoc.v:199867$14589 + attribute \src "libresoc.v:202180.3-202181.37" + process $proc$libresoc.v:202180$14774 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:199869.3-199870.25" - process $proc$libresoc.v:199869$14590 + attribute \src "libresoc.v:202182.3-202183.25" + process $proc$libresoc.v:202182$14775 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:199871.3-199872.25" - process $proc$libresoc.v:199871$14591 + attribute \src "libresoc.v:202184.3-202185.25" + process $proc$libresoc.v:202184$14776 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:199873.3-199874.25" - process $proc$libresoc.v:199873$14592 + attribute \src "libresoc.v:202186.3-202187.25" + process $proc$libresoc.v:202186$14777 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:199875.3-199876.23" - process $proc$libresoc.v:199875$14593 + attribute \src "libresoc.v:202188.3-202189.23" + process $proc$libresoc.v:202188$14778 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:199877.3-199878.37" - process $proc$libresoc.v:199877$14594 + attribute \src "libresoc.v:202190.3-202191.37" + process $proc$libresoc.v:202190$14779 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:199879.3-199880.29" - process $proc$libresoc.v:199879$14595 + attribute \src "libresoc.v:202192.3-202193.29" + process $proc$libresoc.v:202192$14780 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:199881.3-199896.6" - process $proc$libresoc.v:199881$14596 + attribute \src "libresoc.v:202194.3-202209.6" + process $proc$libresoc.v:202194$14781 assign { } { } assign { } { } assign { } { } @@ -418951,15 +422974,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14597 $1\cppr$next[7:0]$14603 - assign $0\irq$next[0:0]$14598 $1\irq$next[0:0]$14604 - assign $0\mfrr$next[7:0]$14599 $1\mfrr$next[7:0]$14605 - assign $0\wb_ack$next[0:0]$14600 $1\wb_ack$next[0:0]$14606 - assign $0\wb_rd_data$next[31:0]$14601 $1\wb_rd_data$next[31:0]$14607 - assign $0\xisr$next[23:0]$14602 $1\xisr$next[23:0]$14608 - attribute \src "libresoc.v:199882.5-199882.29" + assign $0\cppr$next[7:0]$14782 $1\cppr$next[7:0]$14788 + assign $0\irq$next[0:0]$14783 $1\irq$next[0:0]$14789 + assign $0\mfrr$next[7:0]$14784 $1\mfrr$next[7:0]$14790 + assign $0\wb_ack$next[0:0]$14785 $1\wb_ack$next[0:0]$14791 + assign $0\wb_rd_data$next[31:0]$14786 $1\wb_rd_data$next[31:0]$14792 + assign $0\xisr$next[23:0]$14787 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202195.5-202195.29" switch \initial - attribute \src "libresoc.v:199882.9-199882.17" + attribute \src "libresoc.v:202195.9-202195.17" case 1'1 case end @@ -418973,36 +422996,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14608 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14603 8'00000000 - assign $1\mfrr$next[7:0]$14605 8'11111111 - assign $1\irq$next[0:0]$14604 1'0 - assign $1\wb_rd_data$next[31:0]$14607 0 - assign $1\wb_ack$next[0:0]$14606 1'0 + assign $1\xisr$next[23:0]$14793 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14788 8'00000000 + assign $1\mfrr$next[7:0]$14790 8'11111111 + assign $1\irq$next[0:0]$14789 1'0 + assign $1\wb_rd_data$next[31:0]$14792 0 + assign $1\wb_ack$next[0:0]$14791 1'0 case - assign $1\cppr$next[7:0]$14603 \cppr$2 - assign $1\irq$next[0:0]$14604 \irq$4 - assign $1\mfrr$next[7:0]$14605 \mfrr$3 - assign $1\wb_ack$next[0:0]$14606 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14607 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14608 \xisr$1 + assign $1\cppr$next[7:0]$14788 \cppr$2 + assign $1\irq$next[0:0]$14789 \irq$4 + assign $1\mfrr$next[7:0]$14790 \mfrr$3 + assign $1\wb_ack$next[0:0]$14791 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14792 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14793 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14597 - update \irq$next $0\irq$next[0:0]$14598 - update \mfrr$next $0\mfrr$next[7:0]$14599 - update \wb_ack$next $0\wb_ack$next[0:0]$14600 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14601 - update \xisr$next $0\xisr$next[23:0]$14602 + update \cppr$next $0\cppr$next[7:0]$14782 + update \irq$next $0\irq$next[0:0]$14783 + update \mfrr$next $0\mfrr$next[7:0]$14784 + update \wb_ack$next $0\wb_ack$next[0:0]$14785 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14786 + update \xisr$next $0\xisr$next[23:0]$14787 end - attribute \src "libresoc.v:199897.3-199924.6" - process $proc$libresoc.v:199897$14609 + attribute \src "libresoc.v:202210.3-202237.6" + process $proc$libresoc.v:202210$14794 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199898.5-199898.29" + attribute \src "libresoc.v:202211.5-202211.29" switch \initial - attribute \src "libresoc.v:199898.9-199898.17" + attribute \src "libresoc.v:202211.9-202211.17" case 1'1 case end @@ -419046,14 +423069,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:199925.3-199953.6" - process $proc$libresoc.v:199925$14610 + attribute \src "libresoc.v:202238.3-202266.6" + process $proc$libresoc.v:202238$14795 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:199926.5-199926.29" + attribute \src "libresoc.v:202239.5-202239.29" switch \initial - attribute \src "libresoc.v:199926.9-199926.17" + attribute \src "libresoc.v:202239.9-202239.17" case 1'1 case end @@ -419096,14 +423119,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:199954.3-199963.6" - process $proc$libresoc.v:199954$14611 + attribute \src "libresoc.v:202267.3-202276.6" + process $proc$libresoc.v:202267$14796 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:199955.5-199955.29" + attribute \src "libresoc.v:202268.5-202268.29" switch \initial - attribute \src "libresoc.v:199955.9-199955.17" + attribute \src "libresoc.v:202268.9-202268.17" case 1'1 case end @@ -419119,13 +423142,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:199964.3-199975.6" - process $proc$libresoc.v:199964$14612 + attribute \src "libresoc.v:202277.3-202288.6" + process $proc$libresoc.v:202277$14797 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:199965.5-199965.29" + attribute \src "libresoc.v:202278.5-202278.29" switch \initial - attribute \src "libresoc.v:199965.9-199965.17" + attribute \src "libresoc.v:202278.9-202278.17" case 1'1 case end @@ -419143,14 +423166,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:199976.3-199984.6" - process $proc$libresoc.v:199976$14613 + attribute \src "libresoc.v:202289.3-202297.6" + process $proc$libresoc.v:202289$14798 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14614 $1\core_irq_o$next[0:0]$14615 - attribute \src "libresoc.v:199977.5-199977.29" + assign $0\core_irq_o$next[0:0]$14799 $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202290.5-202290.29" switch \initial - attribute \src "libresoc.v:199977.9-199977.17" + attribute \src "libresoc.v:202290.9-202290.17" case 1'1 case end @@ -419159,21 +423182,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14615 1'0 + assign $1\core_irq_o$next[0:0]$14800 1'0 case - assign $1\core_irq_o$next[0:0]$14615 \irq + assign $1\core_irq_o$next[0:0]$14800 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14614 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14799 end - attribute \src "libresoc.v:199985.3-199994.6" - process $proc$libresoc.v:199985$14616 + attribute \src "libresoc.v:202298.3-202307.6" + process $proc$libresoc.v:202298$14801 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199986.5-199986.29" + attribute \src "libresoc.v:202299.5-202299.29" switch \initial - attribute \src "libresoc.v:199986.9-199986.17" + attribute \src "libresoc.v:202299.9-202299.17" case 1'1 case end @@ -419189,8 +423212,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:199995.3-200057.6" - process $proc$libresoc.v:199995$14617 + attribute \src "libresoc.v:202308.3-202370.6" + process $proc$libresoc.v:202308$14802 assign { } { } assign { } { } assign { } { } @@ -419200,18 +423223,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14620 $1\mfrr$11[7:0]$14625 - assign $0\wb_ack$14[0:0]$14621 $1\wb_ack$14[0:0]$14626 + assign $0\mfrr$11[7:0]$14805 $1\mfrr$11[7:0]$14810 + assign $0\wb_ack$14[0:0]$14806 $1\wb_ack$14[0:0]$14811 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14623 $2\xisr$9[23:0]$14632 - assign $0\cppr$10[7:0]$14618 $4\cppr$10[7:0]$14633 - assign $0\wb_rd_data$13[31:0]$14622 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14619 $1\irq$12[0:0]$14634 - attribute \src "libresoc.v:199996.5-199996.29" + assign $0\xisr$9[23:0]$14808 $2\xisr$9[23:0]$14817 + assign $0\cppr$10[7:0]$14803 $4\cppr$10[7:0]$14818 + assign $0\wb_rd_data$13[31:0]$14807 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14804 $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202309.5-202309.29" switch \initial - attribute \src "libresoc.v:199996.9-199996.17" + attribute \src "libresoc.v:202309.9-202309.17" case 1'1 case end @@ -419222,712 +423245,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14626 1'1 - assign $1\cppr$10[7:0]$14624 $2\cppr$10[7:0]$14627 - assign $1\mfrr$11[7:0]$14625 $2\mfrr$11[7:0]$14628 + assign $1\wb_ack$14[0:0]$14811 1'1 + assign $1\cppr$10[7:0]$14809 $2\cppr$10[7:0]$14812 + assign $1\mfrr$11[7:0]$14810 $2\mfrr$11[7:0]$14813 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14627 $3\cppr$10[7:0]$14629 - assign $2\mfrr$11[7:0]$14628 $3\mfrr$11[7:0]$14630 + assign $2\cppr$10[7:0]$14812 $3\cppr$10[7:0]$14814 + assign $2\mfrr$11[7:0]$14813 $3\mfrr$11[7:0]$14815 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14630 \mfrr - assign $3\cppr$10[7:0]$14629 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14630 \mfrr - assign $3\cppr$10[7:0]$14629 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14629 \cppr + assign $3\cppr$10[7:0]$14814 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14630 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \be_in [31:24] case - assign $3\cppr$10[7:0]$14629 \cppr - assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14814 \cppr + assign $3\mfrr$11[7:0]$14815 \mfrr end case - assign $2\cppr$10[7:0]$14627 \cppr - assign $2\mfrr$11[7:0]$14628 \mfrr + assign $2\cppr$10[7:0]$14812 \cppr + assign $2\mfrr$11[7:0]$14813 \mfrr end case - assign $1\cppr$10[7:0]$14624 \cppr - assign $1\mfrr$11[7:0]$14625 \mfrr - assign $1\wb_ack$14[0:0]$14626 1'0 + assign $1\cppr$10[7:0]$14809 \cppr + assign $1\mfrr$11[7:0]$14810 \mfrr + assign $1\wb_ack$14[0:0]$14811 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14631 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14816 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14631 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14816 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14632 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14817 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14632 $1\xisr$9[23:0]$14631 + assign $2\xisr$9[23:0]$14817 $1\xisr$9[23:0]$14816 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14633 \min_pri + assign $4\cppr$10[7:0]$14818 \min_pri case - assign $4\cppr$10[7:0]$14633 $1\cppr$10[7:0]$14624 + assign $4\cppr$10[7:0]$14818 $1\cppr$10[7:0]$14809 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14634 1'1 + assign $1\irq$12[0:0]$14819 1'1 case - assign $1\irq$12[0:0]$14634 1'0 + assign $1\irq$12[0:0]$14819 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14618 - update \irq$12 $0\irq$12[0:0]$14619 - update \mfrr$11 $0\mfrr$11[7:0]$14620 - update \wb_ack$14 $0\wb_ack$14[0:0]$14621 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14622 - update \xisr$9 $0\xisr$9[23:0]$14623 + update \cppr$10 $0\cppr$10[7:0]$14803 + update \irq$12 $0\irq$12[0:0]$14804 + update \mfrr$11 $0\mfrr$11[7:0]$14805 + update \wb_ack$14 $0\wb_ack$14[0:0]$14806 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14807 + update \xisr$9 $0\xisr$9[23:0]$14808 end - connect \$15 $and$libresoc.v:199857$14579_Y - connect \$17 $ne$libresoc.v:199858$14580_Y - connect \$19 $lt$libresoc.v:199859$14581_Y - connect \$21 $lt$libresoc.v:199860$14582_Y - connect \$23 $and$libresoc.v:199861$14583_Y - connect \$25 $eq$libresoc.v:199862$14584_Y - connect \$27 $and$libresoc.v:199863$14585_Y - connect \$29 $ne$libresoc.v:199864$14586_Y - connect \$31 $lt$libresoc.v:199865$14587_Y - connect \$7 $and$libresoc.v:199866$14588_Y + connect \$15 $and$libresoc.v:202170$14764_Y + connect \$17 $ne$libresoc.v:202171$14765_Y + connect \$19 $lt$libresoc.v:202172$14766_Y + connect \$21 $lt$libresoc.v:202173$14767_Y + connect \$23 $and$libresoc.v:202174$14768_Y + connect \$25 $eq$libresoc.v:202175$14769_Y + connect \$27 $and$libresoc.v:202176$14770_Y + connect \$29 $ne$libresoc.v:202177$14771_Y + connect \$31 $lt$libresoc.v:202178$14772_Y + connect \$7 $and$libresoc.v:202179$14773_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:200065.1-201114.10" +attribute \src "libresoc.v:202378.1-203427.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:200706.3-200715.6" + attribute \src "libresoc.v:203019.3-203028.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:200915.3-200924.6" + attribute \src "libresoc.v:203228.3-203237.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:200935.3-200944.6" + attribute \src "libresoc.v:203248.3-203257.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:200955.3-200964.6" + attribute \src "libresoc.v:203268.3-203277.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:203288.3-203297.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:201045.3-201054.6" + attribute \src "libresoc.v:203358.3-203367.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:201065.3-201074.6" + attribute \src "libresoc.v:203378.3-203387.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:200726.3-200735.6" + attribute \src "libresoc.v:203039.3-203048.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:200746.3-200755.6" + attribute \src "libresoc.v:203059.3-203068.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:200766.3-200775.6" + attribute \src "libresoc.v:203079.3-203088.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:200795.3-200804.6" + attribute \src "libresoc.v:203108.3-203117.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:200815.3-200824.6" + attribute \src "libresoc.v:203128.3-203137.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:200835.3-200844.6" + attribute \src "libresoc.v:203148.3-203157.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:200855.3-200864.6" + attribute \src "libresoc.v:203168.3-203177.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:200875.3-200884.6" + attribute \src "libresoc.v:203188.3-203197.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:200895.3-200904.6" + attribute \src "libresoc.v:203208.3-203217.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:200696.3-200705.6" + attribute \src "libresoc.v:203009.3-203018.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:200905.3-200914.6" + attribute \src "libresoc.v:203218.3-203227.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:200925.3-200934.6" + attribute \src "libresoc.v:203238.3-203247.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:200945.3-200954.6" + attribute \src "libresoc.v:203258.3-203267.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:203278.3-203287.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:203298.3-203307.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:201055.3-201064.6" + attribute \src "libresoc.v:203368.3-203377.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:200716.3-200725.6" + attribute \src "libresoc.v:203029.3-203038.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:200736.3-200745.6" + attribute \src "libresoc.v:203049.3-203058.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:200756.3-200765.6" + attribute \src "libresoc.v:203069.3-203078.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:200776.3-200785.6" + attribute \src "libresoc.v:203089.3-203098.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:200805.3-200814.6" + attribute \src "libresoc.v:203118.3-203127.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:200825.3-200834.6" + attribute \src "libresoc.v:203138.3-203147.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:200845.3-200854.6" + attribute \src "libresoc.v:203158.3-203167.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:200865.3-200874.6" + attribute \src "libresoc.v:203178.3-203187.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:200885.3-200894.6" + attribute \src "libresoc.v:203198.3-203207.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:201075.3-201084.6" + attribute \src "libresoc.v:203388.3-203397.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:200570.3-200571.25" + attribute \src "libresoc.v:202883.3-202884.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:200568.3-200569.28" + attribute \src "libresoc.v:202881.3-202882.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:201094.3-201102.6" - wire $0\ics_wb__ack$next[0:0]$14889 - attribute \src "libresoc.v:200604.3-200605.39" + attribute \src "libresoc.v:203407.3-203415.6" + wire $0\ics_wb__ack$next[0:0]$15074 + attribute \src "libresoc.v:202917.3-202918.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:201085.3-201093.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14886 - attribute \src "libresoc.v:200606.3-200607.43" + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15071 + attribute \src "libresoc.v:202919.3-202920.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:200066.7-200066.20" + attribute \src "libresoc.v:202379.7-202379.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200786.3-200794.6" - wire width 16 $0\int_level_l$next[15:0]$14858 - attribute \src "libresoc.v:200608.3-200609.39" + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $0\int_level_l$next[15:0]$15043 + attribute \src "libresoc.v:202921.3-202922.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive0_pri$next[7:0]$14768 - attribute \src "libresoc.v:200572.3-200573.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive0_pri$next[7:0]$14953 + attribute \src "libresoc.v:202885.3-202886.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive10_pri$next[7:0]$14769 - attribute \src "libresoc.v:200592.3-200593.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive10_pri$next[7:0]$14954 + attribute \src "libresoc.v:202905.3-202906.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive11_pri$next[7:0]$14770 - attribute \src "libresoc.v:200594.3-200595.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive11_pri$next[7:0]$14955 + attribute \src "libresoc.v:202907.3-202908.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive12_pri$next[7:0]$14771 - attribute \src "libresoc.v:200596.3-200597.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive12_pri$next[7:0]$14956 + attribute \src "libresoc.v:202909.3-202910.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive13_pri$next[7:0]$14772 - attribute \src "libresoc.v:200598.3-200599.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive13_pri$next[7:0]$14957 + attribute \src "libresoc.v:202911.3-202912.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive14_pri$next[7:0]$14773 - attribute \src "libresoc.v:200600.3-200601.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive14_pri$next[7:0]$14958 + attribute \src "libresoc.v:202913.3-202914.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive15_pri$next[7:0]$14774 - attribute \src "libresoc.v:200602.3-200603.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive15_pri$next[7:0]$14959 + attribute \src "libresoc.v:202915.3-202916.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive1_pri$next[7:0]$14775 - attribute \src "libresoc.v:200574.3-200575.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive1_pri$next[7:0]$14960 + attribute \src "libresoc.v:202887.3-202888.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive2_pri$next[7:0]$14776 - attribute \src "libresoc.v:200576.3-200577.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive2_pri$next[7:0]$14961 + attribute \src "libresoc.v:202889.3-202890.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive3_pri$next[7:0]$14777 - attribute \src "libresoc.v:200578.3-200579.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive3_pri$next[7:0]$14962 + attribute \src "libresoc.v:202891.3-202892.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive4_pri$next[7:0]$14778 - attribute \src "libresoc.v:200580.3-200581.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive4_pri$next[7:0]$14963 + attribute \src "libresoc.v:202893.3-202894.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive5_pri$next[7:0]$14779 - attribute \src "libresoc.v:200582.3-200583.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive5_pri$next[7:0]$14964 + attribute \src "libresoc.v:202895.3-202896.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive6_pri$next[7:0]$14780 - attribute \src "libresoc.v:200584.3-200585.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive6_pri$next[7:0]$14965 + attribute \src "libresoc.v:202897.3-202898.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive7_pri$next[7:0]$14781 - attribute \src "libresoc.v:200586.3-200587.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive7_pri$next[7:0]$14966 + attribute \src "libresoc.v:202899.3-202900.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive8_pri$next[7:0]$14782 - attribute \src "libresoc.v:200588.3-200589.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive8_pri$next[7:0]$14967 + attribute \src "libresoc.v:202901.3-202902.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive9_pri$next[7:0]$14783 - attribute \src "libresoc.v:200590.3-200591.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive9_pri$next[7:0]$14968 + attribute \src "libresoc.v:202903.3-202904.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:200706.3-200715.6" + attribute \src "libresoc.v:203019.3-203028.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:200915.3-200924.6" + attribute \src "libresoc.v:203228.3-203237.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:200935.3-200944.6" + attribute \src "libresoc.v:203248.3-203257.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:200955.3-200964.6" + attribute \src "libresoc.v:203268.3-203277.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:203288.3-203297.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:201045.3-201054.6" + attribute \src "libresoc.v:203358.3-203367.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:201065.3-201074.6" + attribute \src "libresoc.v:203378.3-203387.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:200726.3-200735.6" + attribute \src "libresoc.v:203039.3-203048.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:200746.3-200755.6" + attribute \src "libresoc.v:203059.3-203068.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:200766.3-200775.6" + attribute \src "libresoc.v:203079.3-203088.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:200795.3-200804.6" + attribute \src "libresoc.v:203108.3-203117.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:200815.3-200824.6" + attribute \src "libresoc.v:203128.3-203137.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:200835.3-200844.6" + attribute \src "libresoc.v:203148.3-203157.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:200855.3-200864.6" + attribute \src "libresoc.v:203168.3-203177.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:200875.3-200884.6" + attribute \src "libresoc.v:203188.3-203197.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:200895.3-200904.6" + attribute \src "libresoc.v:203208.3-203217.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:200696.3-200705.6" + attribute \src "libresoc.v:203009.3-203018.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:200905.3-200914.6" + attribute \src "libresoc.v:203218.3-203227.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:200925.3-200934.6" + attribute \src "libresoc.v:203238.3-203247.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:200945.3-200954.6" + attribute \src "libresoc.v:203258.3-203267.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:203278.3-203287.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:203298.3-203307.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:201055.3-201064.6" + attribute \src "libresoc.v:203368.3-203377.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:200716.3-200725.6" + attribute \src "libresoc.v:203029.3-203038.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:200736.3-200745.6" + attribute \src "libresoc.v:203049.3-203058.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:200756.3-200765.6" + attribute \src "libresoc.v:203069.3-203078.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:200776.3-200785.6" + attribute \src "libresoc.v:203089.3-203098.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:200805.3-200814.6" + attribute \src "libresoc.v:203118.3-203127.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:200825.3-200834.6" + attribute \src "libresoc.v:203138.3-203147.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:200845.3-200854.6" + attribute \src "libresoc.v:203158.3-203167.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:200865.3-200874.6" + attribute \src "libresoc.v:203178.3-203187.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:200885.3-200894.6" + attribute \src "libresoc.v:203198.3-203207.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:201075.3-201084.6" + attribute \src "libresoc.v:203388.3-203397.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:200347.13-200347.30" + attribute \src "libresoc.v:202660.13-202660.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:200352.13-200352.29" + attribute \src "libresoc.v:202665.13-202665.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:201094.3-201102.6" - wire $1\ics_wb__ack$next[0:0]$14890 - attribute \src "libresoc.v:200361.7-200361.25" + attribute \src "libresoc.v:203407.3-203415.6" + wire $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:202674.7-202674.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:201085.3-201093.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14887 - attribute \src "libresoc.v:200370.14-200370.35" + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:202683.14-202683.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:200786.3-200794.6" - wire width 16 $1\int_level_l$next[15:0]$14859 - attribute \src "libresoc.v:200382.14-200382.36" + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:202695.14-202695.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive0_pri$next[7:0]$14784 - attribute \src "libresoc.v:200402.13-200402.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive0_pri$next[7:0]$14969 + attribute \src "libresoc.v:202715.13-202715.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive10_pri$next[7:0]$14785 - attribute \src "libresoc.v:200406.13-200406.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive10_pri$next[7:0]$14970 + attribute \src "libresoc.v:202719.13-202719.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive11_pri$next[7:0]$14786 - attribute \src "libresoc.v:200410.13-200410.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive11_pri$next[7:0]$14971 + attribute \src "libresoc.v:202723.13-202723.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive12_pri$next[7:0]$14787 - attribute \src "libresoc.v:200414.13-200414.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive12_pri$next[7:0]$14972 + attribute \src "libresoc.v:202727.13-202727.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive13_pri$next[7:0]$14788 - attribute \src "libresoc.v:200418.13-200418.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive13_pri$next[7:0]$14973 + attribute \src "libresoc.v:202731.13-202731.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive14_pri$next[7:0]$14789 - attribute \src "libresoc.v:200422.13-200422.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive14_pri$next[7:0]$14974 + attribute \src "libresoc.v:202735.13-202735.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive15_pri$next[7:0]$14790 - attribute \src "libresoc.v:200426.13-200426.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive15_pri$next[7:0]$14975 + attribute \src "libresoc.v:202739.13-202739.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive1_pri$next[7:0]$14791 - attribute \src "libresoc.v:200430.13-200430.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive1_pri$next[7:0]$14976 + attribute \src "libresoc.v:202743.13-202743.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive2_pri$next[7:0]$14792 - attribute \src "libresoc.v:200434.13-200434.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive2_pri$next[7:0]$14977 + attribute \src "libresoc.v:202747.13-202747.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive3_pri$next[7:0]$14793 - attribute \src "libresoc.v:200438.13-200438.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive3_pri$next[7:0]$14978 + attribute \src "libresoc.v:202751.13-202751.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive4_pri$next[7:0]$14794 - attribute \src "libresoc.v:200442.13-200442.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive4_pri$next[7:0]$14979 + attribute \src "libresoc.v:202755.13-202755.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive5_pri$next[7:0]$14795 - attribute \src "libresoc.v:200446.13-200446.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive5_pri$next[7:0]$14980 + attribute \src "libresoc.v:202759.13-202759.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive6_pri$next[7:0]$14796 - attribute \src "libresoc.v:200450.13-200450.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive6_pri$next[7:0]$14981 + attribute \src "libresoc.v:202763.13-202763.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive7_pri$next[7:0]$14797 - attribute \src "libresoc.v:200454.13-200454.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive7_pri$next[7:0]$14982 + attribute \src "libresoc.v:202767.13-202767.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive8_pri$next[7:0]$14798 - attribute \src "libresoc.v:200458.13-200458.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive8_pri$next[7:0]$14983 + attribute \src "libresoc.v:202771.13-202771.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive9_pri$next[7:0]$14799 - attribute \src "libresoc.v:200462.13-200462.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive9_pri$next[7:0]$14984 + attribute \src "libresoc.v:202775.13-202775.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $2\be_out[31:0] - attribute \src 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$3\xive14_pri$next[7:0]$14821 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive15_pri$next[7:0]$14822 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive1_pri$next[7:0]$14823 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive2_pri$next[7:0]$14824 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive3_pri$next[7:0]$14825 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive4_pri$next[7:0]$14826 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive5_pri$next[7:0]$14827 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive6_pri$next[7:0]$14828 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive7_pri$next[7:0]$14829 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive8_pri$next[7:0]$14830 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive9_pri$next[7:0]$14831 - attribute \src "libresoc.v:200610.3-200695.6" - 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"libresoc.v:202845.18-202845.116" + wire width 8 $ternary$libresoc.v:202845$14895_Y + attribute \src "libresoc.v:202847.18-202847.116" + wire width 8 $ternary$libresoc.v:202847$14897_Y + attribute \src "libresoc.v:202850.18-202850.116" + wire width 8 $ternary$libresoc.v:202850$14900_Y + attribute \src "libresoc.v:202852.18-202852.116" + wire width 8 $ternary$libresoc.v:202852$14902_Y + attribute \src "libresoc.v:202854.18-202854.117" + wire width 8 $ternary$libresoc.v:202854$14904_Y + attribute \src "libresoc.v:202856.18-202856.117" + wire width 8 $ternary$libresoc.v:202856$14906_Y + attribute \src "libresoc.v:202858.18-202858.117" + wire width 8 $ternary$libresoc.v:202858$14908_Y + attribute \src "libresoc.v:202861.18-202861.117" + wire width 8 $ternary$libresoc.v:202861$14911_Y + attribute \src "libresoc.v:202863.18-202863.117" + wire width 8 $ternary$libresoc.v:202863$14913_Y + attribute \src "libresoc.v:202865.18-202865.117" + wire width 8 $ternary$libresoc.v:202865$14915_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -420138,7 +424161,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -420236,7 +424259,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:200066.7-200066.15" + attribute \src "libresoc.v:202379.7-202379.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -420256,7 +424279,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -420325,7 +424348,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200467$14645 + cell $and $and$libresoc.v:202780$14830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420333,10 +424356,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:200467$14645_Y + connect \Y $and$libresoc.v:202780$14830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200469$14647 + cell $and $and$libresoc.v:202782$14832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420344,10 +424367,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:200469$14647_Y + connect \Y $and$libresoc.v:202782$14832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200471$14649 + cell $and $and$libresoc.v:202784$14834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420355,10 +424378,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:200471$14649_Y + connect \Y $and$libresoc.v:202784$14834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200473$14651 + cell $and $and$libresoc.v:202786$14836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420366,10 +424389,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:200473$14651_Y + connect \Y $and$libresoc.v:202786$14836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200475$14653 + cell $and $and$libresoc.v:202788$14838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420377,10 +424400,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:200475$14653_Y + connect \Y $and$libresoc.v:202788$14838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200477$14655 + cell $and $and$libresoc.v:202790$14840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420388,10 +424411,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:200477$14655_Y + connect \Y $and$libresoc.v:202790$14840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200479$14657 + cell $and $and$libresoc.v:202792$14842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420399,10 +424422,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:200479$14657_Y + connect \Y $and$libresoc.v:202792$14842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200482$14660 + cell $and $and$libresoc.v:202795$14845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420410,10 +424433,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:200482$14660_Y + connect \Y $and$libresoc.v:202795$14845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200484$14662 + cell $and $and$libresoc.v:202797$14847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420421,10 +424444,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:200484$14662_Y + connect \Y $and$libresoc.v:202797$14847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200486$14664 + cell $and $and$libresoc.v:202799$14849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420432,10 +424455,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:200486$14664_Y + connect \Y $and$libresoc.v:202799$14849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200489$14667 + cell $and $and$libresoc.v:202802$14852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420443,10 +424466,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:200489$14667_Y + connect \Y $and$libresoc.v:202802$14852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200491$14669 + cell $and $and$libresoc.v:202804$14854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420454,10 +424477,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:200491$14669_Y + connect \Y $and$libresoc.v:202804$14854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200493$14671 + cell $and $and$libresoc.v:202806$14856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420465,10 +424488,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:200493$14671_Y + connect \Y $and$libresoc.v:202806$14856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200495$14673 + cell $and $and$libresoc.v:202808$14858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420476,10 +424499,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:200495$14673_Y + connect \Y $and$libresoc.v:202808$14858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200497$14675 + cell $and $and$libresoc.v:202810$14860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420487,10 +424510,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:200497$14675_Y + connect \Y $and$libresoc.v:202810$14860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200499$14677 + cell $and $and$libresoc.v:202812$14862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420498,10 +424521,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:200499$14677_Y + connect \Y $and$libresoc.v:202812$14862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200501$14679 + cell $and $and$libresoc.v:202814$14864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420509,10 +424532,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:200501$14679_Y + connect \Y $and$libresoc.v:202814$14864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200504$14682 + cell $and $and$libresoc.v:202817$14867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420520,10 +424543,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:200504$14682_Y + connect \Y $and$libresoc.v:202817$14867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200506$14684 + cell $and $and$libresoc.v:202819$14869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420531,10 +424554,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:200506$14684_Y + connect \Y $and$libresoc.v:202819$14869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200508$14686 + cell $and $and$libresoc.v:202821$14871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420542,10 +424565,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:200508$14686_Y + connect \Y $and$libresoc.v:202821$14871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200511$14689 + cell $and $and$libresoc.v:202824$14874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420553,10 +424576,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:200511$14689_Y + connect \Y $and$libresoc.v:202824$14874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200513$14691 + cell $and $and$libresoc.v:202826$14876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420564,10 +424587,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:200513$14691_Y + connect \Y $and$libresoc.v:202826$14876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200515$14693 + cell $and $and$libresoc.v:202828$14878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420575,10 +424598,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:200515$14693_Y + connect \Y $and$libresoc.v:202828$14878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200517$14695 + cell $and $and$libresoc.v:202830$14880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420586,10 +424609,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:200517$14695_Y + connect \Y $and$libresoc.v:202830$14880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200519$14697 + cell $and $and$libresoc.v:202832$14882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420597,10 +424620,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:200519$14697_Y + connect \Y $and$libresoc.v:202832$14882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200522$14700 + cell $and $and$libresoc.v:202835$14885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420608,10 +424631,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:200522$14700_Y + connect \Y $and$libresoc.v:202835$14885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:200546$14724 + cell $and $and$libresoc.v:202859$14909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420619,10 +424642,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:200546$14724_Y + connect \Y $and$libresoc.v:202859$14909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:200554$14732 + cell $and $and$libresoc.v:202867$14917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420630,10 +424653,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:200554$14732_Y + connect \Y $and$libresoc.v:202867$14917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200556$14734 + cell $and $and$libresoc.v:202869$14919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420641,10 +424664,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:200556$14734_Y + connect \Y $and$libresoc.v:202869$14919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200558$14736 + cell $and $and$libresoc.v:202871$14921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420652,10 +424675,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:200558$14736_Y + connect \Y $and$libresoc.v:202871$14921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200560$14738 + cell $and $and$libresoc.v:202873$14923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420663,10 +424686,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:200560$14738_Y + connect \Y $and$libresoc.v:202873$14923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200563$14741 + cell $and $and$libresoc.v:202876$14926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420674,10 +424697,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:200563$14741_Y + connect \Y $and$libresoc.v:202876$14926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200565$14743 + cell $and $and$libresoc.v:202878$14928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420685,10 +424708,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:200565$14743_Y + connect \Y $and$libresoc.v:202878$14928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200567$14745 + cell $and $and$libresoc.v:202880$14930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420696,10 +424719,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:200567$14745_Y + connect \Y $and$libresoc.v:202880$14930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200481$14659 + cell $eq $eq$libresoc.v:202794$14844 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420707,10 +424730,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200481$14659_Y + connect \Y $eq$libresoc.v:202794$14844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200503$14681 + cell $eq $eq$libresoc.v:202816$14866 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420718,10 +424741,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200503$14681_Y + connect \Y $eq$libresoc.v:202816$14866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:200520$14698 + cell $eq $eq$libresoc.v:202833$14883 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420729,10 +424752,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:200520$14698_Y + connect \Y $eq$libresoc.v:202833$14883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200523$14701 + cell $eq $eq$libresoc.v:202836$14886 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420740,10 +424763,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:200523$14701_Y + connect \Y $eq$libresoc.v:202836$14886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200525$14703 + cell $eq $eq$libresoc.v:202838$14888 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420751,10 +424774,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200525$14703_Y + connect \Y $eq$libresoc.v:202838$14888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200527$14705 + cell $eq $eq$libresoc.v:202840$14890 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420762,10 +424785,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200527$14705_Y + connect \Y $eq$libresoc.v:202840$14890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200529$14707 + cell $eq $eq$libresoc.v:202842$14892 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420773,10 +424796,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200529$14707_Y + connect \Y $eq$libresoc.v:202842$14892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200531$14709 + cell $eq $eq$libresoc.v:202844$14894 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420784,10 +424807,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200531$14709_Y + connect \Y $eq$libresoc.v:202844$14894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200533$14711 + cell $eq $eq$libresoc.v:202846$14896 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420795,10 +424818,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200533$14711_Y + connect \Y $eq$libresoc.v:202846$14896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:200535$14713 + cell $eq $eq$libresoc.v:202848$14898 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420806,10 +424829,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:200535$14713_Y + connect \Y $eq$libresoc.v:202848$14898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200536$14714 + cell $eq $eq$libresoc.v:202849$14899 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420817,10 +424840,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200536$14714_Y + connect \Y $eq$libresoc.v:202849$14899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200538$14716 + cell $eq $eq$libresoc.v:202851$14901 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420828,10 +424851,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200538$14716_Y + connect \Y $eq$libresoc.v:202851$14901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200540$14718 + cell $eq $eq$libresoc.v:202853$14903 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420839,10 +424862,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200540$14718_Y + connect \Y $eq$libresoc.v:202853$14903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200542$14720 + cell $eq $eq$libresoc.v:202855$14905 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420850,10 +424873,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200542$14720_Y + connect \Y $eq$libresoc.v:202855$14905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200544$14722 + cell $eq $eq$libresoc.v:202857$14907 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420861,10 +424884,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200544$14722_Y + connect \Y $eq$libresoc.v:202857$14907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200547$14725 + cell $eq $eq$libresoc.v:202860$14910 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420872,10 +424895,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200547$14725_Y + connect \Y $eq$libresoc.v:202860$14910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200549$14727 + cell $eq $eq$libresoc.v:202862$14912 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420883,10 +424906,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200549$14727_Y + connect \Y $eq$libresoc.v:202862$14912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200551$14729 + cell $eq $eq$libresoc.v:202864$14914 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420894,10 +424917,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200551$14729_Y + connect \Y $eq$libresoc.v:202864$14914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200562$14740 + cell $eq $eq$libresoc.v:202875$14925 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420905,10 +424928,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200562$14740_Y + connect \Y $eq$libresoc.v:202875$14925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200466$14644 + cell $lt $lt$libresoc.v:202779$14829 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420916,10 +424939,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:200466$14644_Y + connect \Y $lt$libresoc.v:202779$14829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200468$14646 + cell $lt $lt$libresoc.v:202781$14831 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420927,10 +424950,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:200468$14646_Y + connect \Y $lt$libresoc.v:202781$14831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200470$14648 + cell $lt $lt$libresoc.v:202783$14833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420938,10 +424961,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:200470$14648_Y + connect \Y $lt$libresoc.v:202783$14833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200472$14650 + cell $lt $lt$libresoc.v:202785$14835 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420949,10 +424972,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:200472$14650_Y + connect \Y $lt$libresoc.v:202785$14835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200474$14652 + cell $lt $lt$libresoc.v:202787$14837 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420960,10 +424983,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:200474$14652_Y + connect \Y $lt$libresoc.v:202787$14837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200476$14654 + cell $lt $lt$libresoc.v:202789$14839 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420971,10 +424994,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:200476$14654_Y + connect \Y $lt$libresoc.v:202789$14839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200478$14656 + cell $lt $lt$libresoc.v:202791$14841 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420982,10 +425005,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:200478$14656_Y + connect \Y $lt$libresoc.v:202791$14841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200480$14658 + cell $lt $lt$libresoc.v:202793$14843 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420993,10 +425016,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:200480$14658_Y + connect \Y $lt$libresoc.v:202793$14843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200483$14661 + cell $lt $lt$libresoc.v:202796$14846 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421004,10 +425027,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:200483$14661_Y + connect \Y $lt$libresoc.v:202796$14846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200485$14663 + cell $lt $lt$libresoc.v:202798$14848 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421015,10 +425038,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:200485$14663_Y + connect \Y $lt$libresoc.v:202798$14848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200488$14666 + cell $lt $lt$libresoc.v:202801$14851 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421026,10 +425049,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:200488$14666_Y + connect \Y $lt$libresoc.v:202801$14851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200490$14668 + cell $lt $lt$libresoc.v:202803$14853 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421037,10 +425060,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:200490$14668_Y + connect \Y $lt$libresoc.v:202803$14853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200492$14670 + cell $lt $lt$libresoc.v:202805$14855 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421048,10 +425071,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:200492$14670_Y + connect \Y $lt$libresoc.v:202805$14855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200494$14672 + cell $lt $lt$libresoc.v:202807$14857 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421059,10 +425082,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:200494$14672_Y + connect \Y $lt$libresoc.v:202807$14857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200496$14674 + cell $lt $lt$libresoc.v:202809$14859 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421070,10 +425093,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:200496$14674_Y + connect \Y $lt$libresoc.v:202809$14859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200498$14676 + cell $lt $lt$libresoc.v:202811$14861 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421081,10 +425104,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:200498$14676_Y + connect \Y $lt$libresoc.v:202811$14861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200500$14678 + cell $lt $lt$libresoc.v:202813$14863 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421092,10 +425115,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:200500$14678_Y + connect \Y $lt$libresoc.v:202813$14863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200502$14680 + cell $lt $lt$libresoc.v:202815$14865 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421103,10 +425126,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:200502$14680_Y + connect \Y $lt$libresoc.v:202815$14865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200505$14683 + cell $lt $lt$libresoc.v:202818$14868 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421114,10 +425137,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:200505$14683_Y + connect \Y $lt$libresoc.v:202818$14868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200507$14685 + cell $lt $lt$libresoc.v:202820$14870 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421125,10 +425148,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:200507$14685_Y + connect \Y $lt$libresoc.v:202820$14870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200510$14688 + cell $lt $lt$libresoc.v:202823$14873 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421136,10 +425159,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:200510$14688_Y + connect \Y $lt$libresoc.v:202823$14873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200512$14690 + cell $lt $lt$libresoc.v:202825$14875 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421147,10 +425170,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:200512$14690_Y + connect \Y $lt$libresoc.v:202825$14875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200514$14692 + cell $lt $lt$libresoc.v:202827$14877 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421158,10 +425181,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:200514$14692_Y + connect \Y $lt$libresoc.v:202827$14877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200516$14694 + cell $lt $lt$libresoc.v:202829$14879 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421169,10 +425192,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:200516$14694_Y + connect \Y $lt$libresoc.v:202829$14879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200518$14696 + cell $lt $lt$libresoc.v:202831$14881 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421180,10 +425203,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:200518$14696_Y + connect \Y $lt$libresoc.v:202831$14881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200521$14699 + cell $lt $lt$libresoc.v:202834$14884 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421191,10 +425214,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:200521$14699_Y + connect \Y $lt$libresoc.v:202834$14884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200555$14733 + cell $lt $lt$libresoc.v:202868$14918 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421202,10 +425225,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:200555$14733_Y + connect \Y $lt$libresoc.v:202868$14918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200557$14735 + cell $lt $lt$libresoc.v:202870$14920 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421213,10 +425236,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:200557$14735_Y + connect \Y $lt$libresoc.v:202870$14920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200559$14737 + cell $lt $lt$libresoc.v:202872$14922 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421224,10 +425247,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:200559$14737_Y + connect \Y $lt$libresoc.v:202872$14922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200561$14739 + cell $lt $lt$libresoc.v:202874$14924 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421235,10 +425258,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:200561$14739_Y + connect \Y $lt$libresoc.v:202874$14924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200564$14742 + cell $lt $lt$libresoc.v:202877$14927 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421246,10 +425269,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:200564$14742_Y + connect \Y $lt$libresoc.v:202877$14927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200566$14744 + cell $lt $lt$libresoc.v:202879$14929 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421257,10 +425280,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:200566$14744_Y + connect \Y $lt$libresoc.v:202879$14929_Y end - attribute \src "libresoc.v:200553.18-200553.40" - cell $shr $shr$libresoc.v:200553$14731 + attribute \src "libresoc.v:202866.18-202866.40" + cell $shr $shr$libresoc.v:202866$14916 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -421268,469 +425291,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:200553$14731_Y + connect \Y $shr$libresoc.v:202866$14916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200465$14643 + cell $mux $ternary$libresoc.v:202778$14828 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:200465$14643_Y + connect \Y $ternary$libresoc.v:202778$14828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200487$14665 + cell $mux $ternary$libresoc.v:202800$14850 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:200487$14665_Y + connect \Y $ternary$libresoc.v:202800$14850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200509$14687 + cell $mux $ternary$libresoc.v:202822$14872 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:200509$14687_Y + connect \Y $ternary$libresoc.v:202822$14872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200524$14702 + cell $mux $ternary$libresoc.v:202837$14887 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:200524$14702_Y + connect \Y $ternary$libresoc.v:202837$14887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200526$14704 + cell $mux $ternary$libresoc.v:202839$14889 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:200526$14704_Y + connect \Y $ternary$libresoc.v:202839$14889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200528$14706 + cell $mux $ternary$libresoc.v:202841$14891 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:200528$14706_Y + connect \Y $ternary$libresoc.v:202841$14891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200530$14708 + cell $mux $ternary$libresoc.v:202843$14893 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:200530$14708_Y + connect \Y $ternary$libresoc.v:202843$14893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200532$14710 + cell $mux $ternary$libresoc.v:202845$14895 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:200532$14710_Y + connect \Y $ternary$libresoc.v:202845$14895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200534$14712 + cell $mux $ternary$libresoc.v:202847$14897 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:200534$14712_Y + connect \Y $ternary$libresoc.v:202847$14897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200537$14715 + cell $mux $ternary$libresoc.v:202850$14900 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:200537$14715_Y + connect \Y $ternary$libresoc.v:202850$14900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200539$14717 + cell $mux $ternary$libresoc.v:202852$14902 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:200539$14717_Y + connect \Y $ternary$libresoc.v:202852$14902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200541$14719 + cell $mux $ternary$libresoc.v:202854$14904 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:200541$14719_Y + connect \Y $ternary$libresoc.v:202854$14904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200543$14721 + cell $mux $ternary$libresoc.v:202856$14906 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:200543$14721_Y + connect \Y $ternary$libresoc.v:202856$14906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200545$14723 + cell $mux $ternary$libresoc.v:202858$14908 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:200545$14723_Y + connect \Y $ternary$libresoc.v:202858$14908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200548$14726 + cell $mux $ternary$libresoc.v:202861$14911 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:200548$14726_Y + connect \Y $ternary$libresoc.v:202861$14911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200550$14728 + cell $mux $ternary$libresoc.v:202863$14913 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:200550$14728_Y + connect \Y $ternary$libresoc.v:202863$14913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200552$14730 + cell $mux $ternary$libresoc.v:202865$14915 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:200552$14730_Y + connect \Y $ternary$libresoc.v:202865$14915_Y end - attribute \src "libresoc.v:200066.7-200066.20" - process $proc$libresoc.v:200066$14891 + attribute \src "libresoc.v:202379.7-202379.20" + process $proc$libresoc.v:202379$15076 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200347.13-200347.30" - process $proc$libresoc.v:200347$14892 + attribute \src "libresoc.v:202660.13-202660.30" + process $proc$libresoc.v:202660$15077 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:200352.13-200352.29" - process $proc$libresoc.v:200352$14893 + attribute \src "libresoc.v:202665.13-202665.29" + process $proc$libresoc.v:202665$15078 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:200361.7-200361.25" - process $proc$libresoc.v:200361$14894 + attribute \src "libresoc.v:202674.7-202674.25" + process $proc$libresoc.v:202674$15079 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:200370.14-200370.35" - process $proc$libresoc.v:200370$14895 + attribute \src "libresoc.v:202683.14-202683.35" + process $proc$libresoc.v:202683$15080 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:200382.14-200382.36" - process $proc$libresoc.v:200382$14896 + attribute \src "libresoc.v:202695.14-202695.36" + process $proc$libresoc.v:202695$15081 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:200402.13-200402.30" - process $proc$libresoc.v:200402$14897 + attribute \src "libresoc.v:202715.13-202715.30" + process $proc$libresoc.v:202715$15082 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:200406.13-200406.31" - process $proc$libresoc.v:200406$14898 + attribute \src "libresoc.v:202719.13-202719.31" + process $proc$libresoc.v:202719$15083 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:200410.13-200410.31" - process $proc$libresoc.v:200410$14899 + attribute \src "libresoc.v:202723.13-202723.31" + process $proc$libresoc.v:202723$15084 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:200414.13-200414.31" - process $proc$libresoc.v:200414$14900 + attribute \src "libresoc.v:202727.13-202727.31" + process $proc$libresoc.v:202727$15085 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:200418.13-200418.31" - process $proc$libresoc.v:200418$14901 + attribute \src "libresoc.v:202731.13-202731.31" + process $proc$libresoc.v:202731$15086 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:200422.13-200422.31" - process $proc$libresoc.v:200422$14902 + attribute \src "libresoc.v:202735.13-202735.31" + process $proc$libresoc.v:202735$15087 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:200426.13-200426.31" - process $proc$libresoc.v:200426$14903 + attribute \src "libresoc.v:202739.13-202739.31" + process $proc$libresoc.v:202739$15088 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:200430.13-200430.30" - process $proc$libresoc.v:200430$14904 + attribute \src "libresoc.v:202743.13-202743.30" + process $proc$libresoc.v:202743$15089 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:200434.13-200434.30" - process $proc$libresoc.v:200434$14905 + attribute \src "libresoc.v:202747.13-202747.30" + process $proc$libresoc.v:202747$15090 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:200438.13-200438.30" - process $proc$libresoc.v:200438$14906 + attribute \src "libresoc.v:202751.13-202751.30" + process $proc$libresoc.v:202751$15091 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:200442.13-200442.30" - process $proc$libresoc.v:200442$14907 + attribute \src "libresoc.v:202755.13-202755.30" + process $proc$libresoc.v:202755$15092 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:200446.13-200446.30" - process $proc$libresoc.v:200446$14908 + attribute \src "libresoc.v:202759.13-202759.30" + process $proc$libresoc.v:202759$15093 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:200450.13-200450.30" - process $proc$libresoc.v:200450$14909 + attribute \src "libresoc.v:202763.13-202763.30" + process $proc$libresoc.v:202763$15094 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:200454.13-200454.30" - process $proc$libresoc.v:200454$14910 + attribute \src "libresoc.v:202767.13-202767.30" + process $proc$libresoc.v:202767$15095 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:200458.13-200458.30" - process $proc$libresoc.v:200458$14911 + attribute \src "libresoc.v:202771.13-202771.30" + process $proc$libresoc.v:202771$15096 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:200462.13-200462.30" - process $proc$libresoc.v:200462$14912 + attribute \src "libresoc.v:202775.13-202775.30" + process $proc$libresoc.v:202775$15097 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:200568.3-200569.28" - process $proc$libresoc.v:200568$14746 + attribute \src "libresoc.v:202881.3-202882.28" + process $proc$libresoc.v:202881$14931 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:200570.3-200571.25" - process $proc$libresoc.v:200570$14747 + attribute \src "libresoc.v:202883.3-202884.25" + process $proc$libresoc.v:202883$14932 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:200572.3-200573.35" - process $proc$libresoc.v:200572$14748 + attribute \src "libresoc.v:202885.3-202886.35" + process $proc$libresoc.v:202885$14933 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:200574.3-200575.35" - process $proc$libresoc.v:200574$14749 + attribute \src "libresoc.v:202887.3-202888.35" + process $proc$libresoc.v:202887$14934 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:200576.3-200577.35" - process $proc$libresoc.v:200576$14750 + attribute \src "libresoc.v:202889.3-202890.35" + process $proc$libresoc.v:202889$14935 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:200578.3-200579.35" - process $proc$libresoc.v:200578$14751 + attribute \src "libresoc.v:202891.3-202892.35" + process $proc$libresoc.v:202891$14936 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:200580.3-200581.35" - process $proc$libresoc.v:200580$14752 + attribute \src "libresoc.v:202893.3-202894.35" + process $proc$libresoc.v:202893$14937 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:200582.3-200583.35" - process $proc$libresoc.v:200582$14753 + attribute \src "libresoc.v:202895.3-202896.35" + process $proc$libresoc.v:202895$14938 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:200584.3-200585.35" - process $proc$libresoc.v:200584$14754 + attribute \src "libresoc.v:202897.3-202898.35" + process $proc$libresoc.v:202897$14939 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:200586.3-200587.35" - process $proc$libresoc.v:200586$14755 + attribute \src "libresoc.v:202899.3-202900.35" + process $proc$libresoc.v:202899$14940 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:200588.3-200589.35" - process $proc$libresoc.v:200588$14756 + attribute \src "libresoc.v:202901.3-202902.35" + process $proc$libresoc.v:202901$14941 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:200590.3-200591.35" - process $proc$libresoc.v:200590$14757 + attribute \src "libresoc.v:202903.3-202904.35" + process $proc$libresoc.v:202903$14942 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:200592.3-200593.37" - process $proc$libresoc.v:200592$14758 + attribute \src "libresoc.v:202905.3-202906.37" + process $proc$libresoc.v:202905$14943 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:200594.3-200595.37" - process $proc$libresoc.v:200594$14759 + attribute \src "libresoc.v:202907.3-202908.37" + process $proc$libresoc.v:202907$14944 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:200596.3-200597.37" - process $proc$libresoc.v:200596$14760 + attribute \src "libresoc.v:202909.3-202910.37" + process $proc$libresoc.v:202909$14945 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:200598.3-200599.37" - process $proc$libresoc.v:200598$14761 + attribute \src "libresoc.v:202911.3-202912.37" + process $proc$libresoc.v:202911$14946 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:200600.3-200601.37" - process $proc$libresoc.v:200600$14762 + attribute \src "libresoc.v:202913.3-202914.37" + process $proc$libresoc.v:202913$14947 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:200602.3-200603.37" - process $proc$libresoc.v:200602$14763 + attribute \src "libresoc.v:202915.3-202916.37" + process $proc$libresoc.v:202915$14948 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:200604.3-200605.39" - process $proc$libresoc.v:200604$14764 + attribute \src "libresoc.v:202917.3-202918.39" + process $proc$libresoc.v:202917$14949 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:200606.3-200607.43" - process $proc$libresoc.v:200606$14765 + attribute \src "libresoc.v:202919.3-202920.43" + process $proc$libresoc.v:202919$14950 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:200608.3-200609.39" - process $proc$libresoc.v:200608$14766 + attribute \src "libresoc.v:202921.3-202922.39" + process $proc$libresoc.v:202921$14951 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:200610.3-200695.6" - process $proc$libresoc.v:200610$14767 + attribute \src "libresoc.v:202923.3-203008.6" + process $proc$libresoc.v:202923$14952 assign { } { } assign { } { } assign { } { } @@ -421779,25 +425802,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14768 $4\xive0_pri$next[7:0]$14832 - assign $0\xive10_pri$next[7:0]$14769 $4\xive10_pri$next[7:0]$14833 - assign $0\xive11_pri$next[7:0]$14770 $4\xive11_pri$next[7:0]$14834 - assign $0\xive12_pri$next[7:0]$14771 $4\xive12_pri$next[7:0]$14835 - assign $0\xive13_pri$next[7:0]$14772 $4\xive13_pri$next[7:0]$14836 - assign $0\xive14_pri$next[7:0]$14773 $4\xive14_pri$next[7:0]$14837 - assign $0\xive15_pri$next[7:0]$14774 $4\xive15_pri$next[7:0]$14838 - assign $0\xive1_pri$next[7:0]$14775 $4\xive1_pri$next[7:0]$14839 - assign $0\xive2_pri$next[7:0]$14776 $4\xive2_pri$next[7:0]$14840 - assign $0\xive3_pri$next[7:0]$14777 $4\xive3_pri$next[7:0]$14841 - assign $0\xive4_pri$next[7:0]$14778 $4\xive4_pri$next[7:0]$14842 - assign $0\xive5_pri$next[7:0]$14779 $4\xive5_pri$next[7:0]$14843 - assign $0\xive6_pri$next[7:0]$14780 $4\xive6_pri$next[7:0]$14844 - assign $0\xive7_pri$next[7:0]$14781 $4\xive7_pri$next[7:0]$14845 - assign $0\xive8_pri$next[7:0]$14782 $4\xive8_pri$next[7:0]$14846 - assign $0\xive9_pri$next[7:0]$14783 $4\xive9_pri$next[7:0]$14847 - attribute \src "libresoc.v:200611.5-200611.29" + assign $0\xive0_pri$next[7:0]$14953 $4\xive0_pri$next[7:0]$15017 + assign $0\xive10_pri$next[7:0]$14954 $4\xive10_pri$next[7:0]$15018 + assign $0\xive11_pri$next[7:0]$14955 $4\xive11_pri$next[7:0]$15019 + assign $0\xive12_pri$next[7:0]$14956 $4\xive12_pri$next[7:0]$15020 + assign $0\xive13_pri$next[7:0]$14957 $4\xive13_pri$next[7:0]$15021 + assign $0\xive14_pri$next[7:0]$14958 $4\xive14_pri$next[7:0]$15022 + assign $0\xive15_pri$next[7:0]$14959 $4\xive15_pri$next[7:0]$15023 + assign $0\xive1_pri$next[7:0]$14960 $4\xive1_pri$next[7:0]$15024 + assign $0\xive2_pri$next[7:0]$14961 $4\xive2_pri$next[7:0]$15025 + assign $0\xive3_pri$next[7:0]$14962 $4\xive3_pri$next[7:0]$15026 + assign $0\xive4_pri$next[7:0]$14963 $4\xive4_pri$next[7:0]$15027 + assign $0\xive5_pri$next[7:0]$14964 $4\xive5_pri$next[7:0]$15028 + assign $0\xive6_pri$next[7:0]$14965 $4\xive6_pri$next[7:0]$15029 + assign $0\xive7_pri$next[7:0]$14966 $4\xive7_pri$next[7:0]$15030 + assign $0\xive8_pri$next[7:0]$14967 $4\xive8_pri$next[7:0]$15031 + assign $0\xive9_pri$next[7:0]$14968 $4\xive9_pri$next[7:0]$15032 + attribute \src "libresoc.v:202924.5-202924.29" switch \initial - attribute \src "libresoc.v:200611.9-200611.17" + attribute \src "libresoc.v:202924.9-202924.17" case 1'1 case end @@ -421821,22 +425844,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14784 $2\xive0_pri$next[7:0]$14800 - assign $1\xive10_pri$next[7:0]$14785 $2\xive10_pri$next[7:0]$14801 - assign $1\xive11_pri$next[7:0]$14786 $2\xive11_pri$next[7:0]$14802 - assign $1\xive12_pri$next[7:0]$14787 $2\xive12_pri$next[7:0]$14803 - assign $1\xive13_pri$next[7:0]$14788 $2\xive13_pri$next[7:0]$14804 - assign $1\xive14_pri$next[7:0]$14789 $2\xive14_pri$next[7:0]$14805 - assign $1\xive15_pri$next[7:0]$14790 $2\xive15_pri$next[7:0]$14806 - assign $1\xive1_pri$next[7:0]$14791 $2\xive1_pri$next[7:0]$14807 - assign $1\xive2_pri$next[7:0]$14792 $2\xive2_pri$next[7:0]$14808 - assign $1\xive3_pri$next[7:0]$14793 $2\xive3_pri$next[7:0]$14809 - assign $1\xive4_pri$next[7:0]$14794 $2\xive4_pri$next[7:0]$14810 - assign $1\xive5_pri$next[7:0]$14795 $2\xive5_pri$next[7:0]$14811 - assign $1\xive6_pri$next[7:0]$14796 $2\xive6_pri$next[7:0]$14812 - assign $1\xive7_pri$next[7:0]$14797 $2\xive7_pri$next[7:0]$14813 - assign $1\xive8_pri$next[7:0]$14798 $2\xive8_pri$next[7:0]$14814 - assign $1\xive9_pri$next[7:0]$14799 $2\xive9_pri$next[7:0]$14815 + assign $1\xive0_pri$next[7:0]$14969 $2\xive0_pri$next[7:0]$14985 + assign $1\xive10_pri$next[7:0]$14970 $2\xive10_pri$next[7:0]$14986 + assign $1\xive11_pri$next[7:0]$14971 $2\xive11_pri$next[7:0]$14987 + assign $1\xive12_pri$next[7:0]$14972 $2\xive12_pri$next[7:0]$14988 + assign $1\xive13_pri$next[7:0]$14973 $2\xive13_pri$next[7:0]$14989 + assign $1\xive14_pri$next[7:0]$14974 $2\xive14_pri$next[7:0]$14990 + assign $1\xive15_pri$next[7:0]$14975 $2\xive15_pri$next[7:0]$14991 + assign $1\xive1_pri$next[7:0]$14976 $2\xive1_pri$next[7:0]$14992 + assign $1\xive2_pri$next[7:0]$14977 $2\xive2_pri$next[7:0]$14993 + assign $1\xive3_pri$next[7:0]$14978 $2\xive3_pri$next[7:0]$14994 + assign $1\xive4_pri$next[7:0]$14979 $2\xive4_pri$next[7:0]$14995 + assign $1\xive5_pri$next[7:0]$14980 $2\xive5_pri$next[7:0]$14996 + assign $1\xive6_pri$next[7:0]$14981 $2\xive6_pri$next[7:0]$14997 + assign $1\xive7_pri$next[7:0]$14982 $2\xive7_pri$next[7:0]$14998 + assign $1\xive8_pri$next[7:0]$14983 $2\xive8_pri$next[7:0]$14999 + assign $1\xive9_pri$next[7:0]$14984 $2\xive9_pri$next[7:0]$15000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -421857,381 +425880,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14800 $3\xive0_pri$next[7:0]$14816 - assign $2\xive10_pri$next[7:0]$14801 $3\xive10_pri$next[7:0]$14817 - assign $2\xive11_pri$next[7:0]$14802 $3\xive11_pri$next[7:0]$14818 - assign $2\xive12_pri$next[7:0]$14803 $3\xive12_pri$next[7:0]$14819 - assign $2\xive13_pri$next[7:0]$14804 $3\xive13_pri$next[7:0]$14820 - assign $2\xive14_pri$next[7:0]$14805 $3\xive14_pri$next[7:0]$14821 - assign $2\xive15_pri$next[7:0]$14806 $3\xive15_pri$next[7:0]$14822 - assign $2\xive1_pri$next[7:0]$14807 $3\xive1_pri$next[7:0]$14823 - assign $2\xive2_pri$next[7:0]$14808 $3\xive2_pri$next[7:0]$14824 - assign $2\xive3_pri$next[7:0]$14809 $3\xive3_pri$next[7:0]$14825 - assign $2\xive4_pri$next[7:0]$14810 $3\xive4_pri$next[7:0]$14826 - assign $2\xive5_pri$next[7:0]$14811 $3\xive5_pri$next[7:0]$14827 - assign $2\xive6_pri$next[7:0]$14812 $3\xive6_pri$next[7:0]$14828 - assign $2\xive7_pri$next[7:0]$14813 $3\xive7_pri$next[7:0]$14829 - assign $2\xive8_pri$next[7:0]$14814 $3\xive8_pri$next[7:0]$14830 - assign $2\xive9_pri$next[7:0]$14815 $3\xive9_pri$next[7:0]$14831 + assign $2\xive0_pri$next[7:0]$14985 $3\xive0_pri$next[7:0]$15001 + assign $2\xive10_pri$next[7:0]$14986 $3\xive10_pri$next[7:0]$15002 + assign $2\xive11_pri$next[7:0]$14987 $3\xive11_pri$next[7:0]$15003 + assign $2\xive12_pri$next[7:0]$14988 $3\xive12_pri$next[7:0]$15004 + assign $2\xive13_pri$next[7:0]$14989 $3\xive13_pri$next[7:0]$15005 + assign $2\xive14_pri$next[7:0]$14990 $3\xive14_pri$next[7:0]$15006 + assign $2\xive15_pri$next[7:0]$14991 $3\xive15_pri$next[7:0]$15007 + assign $2\xive1_pri$next[7:0]$14992 $3\xive1_pri$next[7:0]$15008 + assign $2\xive2_pri$next[7:0]$14993 $3\xive2_pri$next[7:0]$15009 + assign $2\xive3_pri$next[7:0]$14994 $3\xive3_pri$next[7:0]$15010 + assign $2\xive4_pri$next[7:0]$14995 $3\xive4_pri$next[7:0]$15011 + assign $2\xive5_pri$next[7:0]$14996 $3\xive5_pri$next[7:0]$15012 + assign $2\xive6_pri$next[7:0]$14997 $3\xive6_pri$next[7:0]$15013 + assign $2\xive7_pri$next[7:0]$14998 $3\xive7_pri$next[7:0]$15014 + assign $2\xive8_pri$next[7:0]$14999 $3\xive8_pri$next[7:0]$15015 + assign $2\xive9_pri$next[7:0]$15000 $3\xive9_pri$next[7:0]$15016 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive0_pri$next[7:0]$14816 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive0_pri$next[7:0]$15001 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive1_pri$next[7:0]$14823 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive1_pri$next[7:0]$15008 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive2_pri$next[7:0]$14824 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive2_pri$next[7:0]$15009 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive3_pri$next[7:0]$14825 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive3_pri$next[7:0]$15010 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive4_pri$next[7:0]$14826 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive4_pri$next[7:0]$15011 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive5_pri$next[7:0]$14827 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive5_pri$next[7:0]$15012 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive6_pri$next[7:0]$14828 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive6_pri$next[7:0]$15013 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive7_pri$next[7:0]$14829 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive7_pri$next[7:0]$15014 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive8_pri$next[7:0]$14830 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive8_pri$next[7:0]$15015 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14831 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$15016 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive10_pri$next[7:0]$14817 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive10_pri$next[7:0]$15002 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive11_pri$next[7:0]$14818 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive11_pri$next[7:0]$15003 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive12_pri$next[7:0]$14819 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive12_pri$next[7:0]$15004 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive13_pri$next[7:0]$14820 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive13_pri$next[7:0]$15005 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive14_pri$next[7:0]$14821 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive14_pri$next[7:0]$15006 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive15_pri$next[7:0]$14822 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive15_pri$next[7:0]$15007 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14800 \xive0_pri - assign $2\xive10_pri$next[7:0]$14801 \xive10_pri - assign $2\xive11_pri$next[7:0]$14802 \xive11_pri - assign $2\xive12_pri$next[7:0]$14803 \xive12_pri - assign $2\xive13_pri$next[7:0]$14804 \xive13_pri - assign $2\xive14_pri$next[7:0]$14805 \xive14_pri - assign $2\xive15_pri$next[7:0]$14806 \xive15_pri - assign $2\xive1_pri$next[7:0]$14807 \xive1_pri - assign $2\xive2_pri$next[7:0]$14808 \xive2_pri - assign $2\xive3_pri$next[7:0]$14809 \xive3_pri - assign $2\xive4_pri$next[7:0]$14810 \xive4_pri - assign $2\xive5_pri$next[7:0]$14811 \xive5_pri - assign $2\xive6_pri$next[7:0]$14812 \xive6_pri - assign $2\xive7_pri$next[7:0]$14813 \xive7_pri - assign $2\xive8_pri$next[7:0]$14814 \xive8_pri - assign $2\xive9_pri$next[7:0]$14815 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14784 \xive0_pri - assign $1\xive10_pri$next[7:0]$14785 \xive10_pri - assign $1\xive11_pri$next[7:0]$14786 \xive11_pri - assign $1\xive12_pri$next[7:0]$14787 \xive12_pri - assign $1\xive13_pri$next[7:0]$14788 \xive13_pri - assign $1\xive14_pri$next[7:0]$14789 \xive14_pri - assign $1\xive15_pri$next[7:0]$14790 \xive15_pri - assign $1\xive1_pri$next[7:0]$14791 \xive1_pri - assign $1\xive2_pri$next[7:0]$14792 \xive2_pri - assign $1\xive3_pri$next[7:0]$14793 \xive3_pri - assign $1\xive4_pri$next[7:0]$14794 \xive4_pri - assign $1\xive5_pri$next[7:0]$14795 \xive5_pri - assign $1\xive6_pri$next[7:0]$14796 \xive6_pri - assign $1\xive7_pri$next[7:0]$14797 \xive7_pri - assign $1\xive8_pri$next[7:0]$14798 \xive8_pri - assign $1\xive9_pri$next[7:0]$14799 \xive9_pri + assign $2\xive0_pri$next[7:0]$14985 \xive0_pri + assign $2\xive10_pri$next[7:0]$14986 \xive10_pri + assign $2\xive11_pri$next[7:0]$14987 \xive11_pri + assign $2\xive12_pri$next[7:0]$14988 \xive12_pri + assign $2\xive13_pri$next[7:0]$14989 \xive13_pri + assign $2\xive14_pri$next[7:0]$14990 \xive14_pri + assign $2\xive15_pri$next[7:0]$14991 \xive15_pri + assign $2\xive1_pri$next[7:0]$14992 \xive1_pri + assign $2\xive2_pri$next[7:0]$14993 \xive2_pri + assign $2\xive3_pri$next[7:0]$14994 \xive3_pri + assign $2\xive4_pri$next[7:0]$14995 \xive4_pri + assign $2\xive5_pri$next[7:0]$14996 \xive5_pri + assign $2\xive6_pri$next[7:0]$14997 \xive6_pri + assign $2\xive7_pri$next[7:0]$14998 \xive7_pri + assign $2\xive8_pri$next[7:0]$14999 \xive8_pri + assign $2\xive9_pri$next[7:0]$15000 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14969 \xive0_pri + assign $1\xive10_pri$next[7:0]$14970 \xive10_pri + assign $1\xive11_pri$next[7:0]$14971 \xive11_pri + assign $1\xive12_pri$next[7:0]$14972 \xive12_pri + assign $1\xive13_pri$next[7:0]$14973 \xive13_pri + assign $1\xive14_pri$next[7:0]$14974 \xive14_pri + assign $1\xive15_pri$next[7:0]$14975 \xive15_pri + assign $1\xive1_pri$next[7:0]$14976 \xive1_pri + assign $1\xive2_pri$next[7:0]$14977 \xive2_pri + assign $1\xive3_pri$next[7:0]$14978 \xive3_pri + assign $1\xive4_pri$next[7:0]$14979 \xive4_pri + assign $1\xive5_pri$next[7:0]$14980 \xive5_pri + assign $1\xive6_pri$next[7:0]$14981 \xive6_pri + assign $1\xive7_pri$next[7:0]$14982 \xive7_pri + assign $1\xive8_pri$next[7:0]$14983 \xive8_pri + assign $1\xive9_pri$next[7:0]$14984 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -422253,66 +426276,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14832 8'11111111 - assign $4\xive1_pri$next[7:0]$14839 8'11111111 - assign $4\xive2_pri$next[7:0]$14840 8'11111111 - assign $4\xive3_pri$next[7:0]$14841 8'11111111 - assign $4\xive4_pri$next[7:0]$14842 8'11111111 - assign $4\xive5_pri$next[7:0]$14843 8'11111111 - assign $4\xive6_pri$next[7:0]$14844 8'11111111 - assign $4\xive7_pri$next[7:0]$14845 8'11111111 - assign $4\xive8_pri$next[7:0]$14846 8'11111111 - assign $4\xive9_pri$next[7:0]$14847 8'11111111 - assign $4\xive10_pri$next[7:0]$14833 8'11111111 - assign $4\xive11_pri$next[7:0]$14834 8'11111111 - assign $4\xive12_pri$next[7:0]$14835 8'11111111 - assign $4\xive13_pri$next[7:0]$14836 8'11111111 - assign $4\xive14_pri$next[7:0]$14837 8'11111111 - assign $4\xive15_pri$next[7:0]$14838 8'11111111 + assign $4\xive0_pri$next[7:0]$15017 8'11111111 + assign $4\xive1_pri$next[7:0]$15024 8'11111111 + assign $4\xive2_pri$next[7:0]$15025 8'11111111 + assign $4\xive3_pri$next[7:0]$15026 8'11111111 + assign $4\xive4_pri$next[7:0]$15027 8'11111111 + assign $4\xive5_pri$next[7:0]$15028 8'11111111 + assign $4\xive6_pri$next[7:0]$15029 8'11111111 + assign $4\xive7_pri$next[7:0]$15030 8'11111111 + assign $4\xive8_pri$next[7:0]$15031 8'11111111 + assign $4\xive9_pri$next[7:0]$15032 8'11111111 + assign $4\xive10_pri$next[7:0]$15018 8'11111111 + assign $4\xive11_pri$next[7:0]$15019 8'11111111 + assign $4\xive12_pri$next[7:0]$15020 8'11111111 + assign $4\xive13_pri$next[7:0]$15021 8'11111111 + assign $4\xive14_pri$next[7:0]$15022 8'11111111 + assign $4\xive15_pri$next[7:0]$15023 8'11111111 case - assign $4\xive0_pri$next[7:0]$14832 $1\xive0_pri$next[7:0]$14784 - assign $4\xive10_pri$next[7:0]$14833 $1\xive10_pri$next[7:0]$14785 - assign $4\xive11_pri$next[7:0]$14834 $1\xive11_pri$next[7:0]$14786 - assign $4\xive12_pri$next[7:0]$14835 $1\xive12_pri$next[7:0]$14787 - assign $4\xive13_pri$next[7:0]$14836 $1\xive13_pri$next[7:0]$14788 - assign $4\xive14_pri$next[7:0]$14837 $1\xive14_pri$next[7:0]$14789 - assign $4\xive15_pri$next[7:0]$14838 $1\xive15_pri$next[7:0]$14790 - assign $4\xive1_pri$next[7:0]$14839 $1\xive1_pri$next[7:0]$14791 - assign $4\xive2_pri$next[7:0]$14840 $1\xive2_pri$next[7:0]$14792 - assign $4\xive3_pri$next[7:0]$14841 $1\xive3_pri$next[7:0]$14793 - assign $4\xive4_pri$next[7:0]$14842 $1\xive4_pri$next[7:0]$14794 - assign $4\xive5_pri$next[7:0]$14843 $1\xive5_pri$next[7:0]$14795 - assign $4\xive6_pri$next[7:0]$14844 $1\xive6_pri$next[7:0]$14796 - assign $4\xive7_pri$next[7:0]$14845 $1\xive7_pri$next[7:0]$14797 - assign $4\xive8_pri$next[7:0]$14846 $1\xive8_pri$next[7:0]$14798 - assign $4\xive9_pri$next[7:0]$14847 $1\xive9_pri$next[7:0]$14799 + assign $4\xive0_pri$next[7:0]$15017 $1\xive0_pri$next[7:0]$14969 + assign $4\xive10_pri$next[7:0]$15018 $1\xive10_pri$next[7:0]$14970 + assign $4\xive11_pri$next[7:0]$15019 $1\xive11_pri$next[7:0]$14971 + assign $4\xive12_pri$next[7:0]$15020 $1\xive12_pri$next[7:0]$14972 + assign $4\xive13_pri$next[7:0]$15021 $1\xive13_pri$next[7:0]$14973 + assign $4\xive14_pri$next[7:0]$15022 $1\xive14_pri$next[7:0]$14974 + assign $4\xive15_pri$next[7:0]$15023 $1\xive15_pri$next[7:0]$14975 + assign $4\xive1_pri$next[7:0]$15024 $1\xive1_pri$next[7:0]$14976 + assign $4\xive2_pri$next[7:0]$15025 $1\xive2_pri$next[7:0]$14977 + assign $4\xive3_pri$next[7:0]$15026 $1\xive3_pri$next[7:0]$14978 + assign $4\xive4_pri$next[7:0]$15027 $1\xive4_pri$next[7:0]$14979 + assign $4\xive5_pri$next[7:0]$15028 $1\xive5_pri$next[7:0]$14980 + assign $4\xive6_pri$next[7:0]$15029 $1\xive6_pri$next[7:0]$14981 + assign $4\xive7_pri$next[7:0]$15030 $1\xive7_pri$next[7:0]$14982 + assign $4\xive8_pri$next[7:0]$15031 $1\xive8_pri$next[7:0]$14983 + assign $4\xive9_pri$next[7:0]$15032 $1\xive9_pri$next[7:0]$14984 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14768 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14769 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14770 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14771 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14772 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14773 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14774 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14775 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14776 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14777 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14778 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14779 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14780 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14781 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14782 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14783 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14953 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14954 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14955 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14956 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14957 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14958 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14959 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14960 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14961 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14962 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14963 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14964 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14965 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14966 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14967 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14968 end - attribute \src "libresoc.v:200696.3-200705.6" - process $proc$libresoc.v:200696$14848 + attribute \src "libresoc.v:203009.3-203018.6" + process $proc$libresoc.v:203009$15033 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:200697.5-200697.29" + attribute \src "libresoc.v:203010.5-203010.29" switch \initial - attribute \src "libresoc.v:200697.9-200697.17" + attribute \src "libresoc.v:203010.9-203010.17" case 1'1 case end @@ -422328,14 +426351,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:200706.3-200715.6" - process $proc$libresoc.v:200706$14849 + attribute \src "libresoc.v:203019.3-203028.6" + process $proc$libresoc.v:203019$15034 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:200707.5-200707.29" + attribute \src "libresoc.v:203020.5-203020.29" switch \initial - attribute \src "libresoc.v:200707.9-200707.17" + attribute \src "libresoc.v:203020.9-203020.17" case 1'1 case end @@ -422351,14 +426374,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:200716.3-200725.6" - process $proc$libresoc.v:200716$14850 + attribute \src "libresoc.v:203029.3-203038.6" + process $proc$libresoc.v:203029$15035 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:200717.5-200717.29" + attribute \src "libresoc.v:203030.5-203030.29" switch \initial - attribute \src "libresoc.v:200717.9-200717.17" + attribute \src "libresoc.v:203030.9-203030.17" case 1'1 case end @@ -422374,14 +426397,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:200726.3-200735.6" - process $proc$libresoc.v:200726$14851 + attribute \src "libresoc.v:203039.3-203048.6" + process $proc$libresoc.v:203039$15036 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:200727.5-200727.29" + attribute \src "libresoc.v:203040.5-203040.29" switch \initial - attribute \src "libresoc.v:200727.9-200727.17" + attribute \src "libresoc.v:203040.9-203040.17" case 1'1 case end @@ -422397,14 +426420,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:200736.3-200745.6" - process $proc$libresoc.v:200736$14852 + attribute \src "libresoc.v:203049.3-203058.6" + process $proc$libresoc.v:203049$15037 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:200737.5-200737.29" + attribute \src "libresoc.v:203050.5-203050.29" switch \initial - attribute \src "libresoc.v:200737.9-200737.17" + attribute \src "libresoc.v:203050.9-203050.17" case 1'1 case end @@ -422420,14 +426443,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:200746.3-200755.6" - process $proc$libresoc.v:200746$14853 + attribute \src "libresoc.v:203059.3-203068.6" + process $proc$libresoc.v:203059$15038 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:200747.5-200747.29" + attribute \src "libresoc.v:203060.5-203060.29" switch \initial - attribute \src "libresoc.v:200747.9-200747.17" + attribute \src "libresoc.v:203060.9-203060.17" case 1'1 case end @@ -422443,14 +426466,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:200756.3-200765.6" - process $proc$libresoc.v:200756$14854 + attribute \src "libresoc.v:203069.3-203078.6" + process $proc$libresoc.v:203069$15039 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:200757.5-200757.29" + attribute \src "libresoc.v:203070.5-203070.29" switch \initial - attribute \src "libresoc.v:200757.9-200757.17" + attribute \src "libresoc.v:203070.9-203070.17" case 1'1 case end @@ -422466,14 +426489,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:200766.3-200775.6" - process $proc$libresoc.v:200766$14855 + attribute \src "libresoc.v:203079.3-203088.6" + process $proc$libresoc.v:203079$15040 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:200767.5-200767.29" + attribute \src "libresoc.v:203080.5-203080.29" switch \initial - attribute \src "libresoc.v:200767.9-200767.17" + attribute \src "libresoc.v:203080.9-203080.17" case 1'1 case end @@ -422489,14 +426512,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:200776.3-200785.6" - process $proc$libresoc.v:200776$14856 + attribute \src "libresoc.v:203089.3-203098.6" + process $proc$libresoc.v:203089$15041 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:200777.5-200777.29" + attribute \src "libresoc.v:203090.5-203090.29" switch \initial - attribute \src "libresoc.v:200777.9-200777.17" + attribute \src "libresoc.v:203090.9-203090.17" case 1'1 case end @@ -422512,14 +426535,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:200786.3-200794.6" - process $proc$libresoc.v:200786$14857 + attribute \src "libresoc.v:203099.3-203107.6" + process $proc$libresoc.v:203099$15042 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14858 $1\int_level_l$next[15:0]$14859 - attribute \src "libresoc.v:200787.5-200787.29" + assign $0\int_level_l$next[15:0]$15043 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:203100.5-203100.29" switch \initial - attribute \src "libresoc.v:200787.9-200787.17" + attribute \src "libresoc.v:203100.9-203100.17" case 1'1 case end @@ -422528,21 +426551,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14859 16'0000000000000000 + assign $1\int_level_l$next[15:0]$15044 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14859 \int_level_i + assign $1\int_level_l$next[15:0]$15044 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14858 + update \int_level_l$next $0\int_level_l$next[15:0]$15043 end - attribute \src "libresoc.v:200795.3-200804.6" - process $proc$libresoc.v:200795$14860 + attribute \src "libresoc.v:203108.3-203117.6" + process $proc$libresoc.v:203108$15045 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:200796.5-200796.29" + attribute \src "libresoc.v:203109.5-203109.29" switch \initial - attribute \src "libresoc.v:200796.9-200796.17" + attribute \src "libresoc.v:203109.9-203109.17" case 1'1 case end @@ -422558,14 +426581,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:200805.3-200814.6" - process $proc$libresoc.v:200805$14861 + attribute \src "libresoc.v:203118.3-203127.6" + process $proc$libresoc.v:203118$15046 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:200806.5-200806.29" + attribute \src "libresoc.v:203119.5-203119.29" switch \initial - attribute \src "libresoc.v:200806.9-200806.17" + attribute \src "libresoc.v:203119.9-203119.17" case 1'1 case end @@ -422581,14 +426604,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:200815.3-200824.6" - process $proc$libresoc.v:200815$14862 + attribute \src "libresoc.v:203128.3-203137.6" + process $proc$libresoc.v:203128$15047 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:200816.5-200816.29" + attribute \src "libresoc.v:203129.5-203129.29" switch \initial - attribute \src "libresoc.v:200816.9-200816.17" + attribute \src "libresoc.v:203129.9-203129.17" case 1'1 case end @@ -422604,14 +426627,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:200825.3-200834.6" - process $proc$libresoc.v:200825$14863 + attribute \src "libresoc.v:203138.3-203147.6" + process $proc$libresoc.v:203138$15048 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:200826.5-200826.29" + attribute \src "libresoc.v:203139.5-203139.29" switch \initial - attribute \src "libresoc.v:200826.9-200826.17" + attribute \src "libresoc.v:203139.9-203139.17" case 1'1 case end @@ -422627,14 +426650,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:200835.3-200844.6" - process $proc$libresoc.v:200835$14864 + attribute \src "libresoc.v:203148.3-203157.6" + process $proc$libresoc.v:203148$15049 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:200836.5-200836.29" + attribute \src "libresoc.v:203149.5-203149.29" switch \initial - attribute \src "libresoc.v:200836.9-200836.17" + attribute \src "libresoc.v:203149.9-203149.17" case 1'1 case end @@ -422650,14 +426673,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:200845.3-200854.6" - process $proc$libresoc.v:200845$14865 + attribute \src "libresoc.v:203158.3-203167.6" + process $proc$libresoc.v:203158$15050 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:200846.5-200846.29" + attribute \src "libresoc.v:203159.5-203159.29" switch \initial - attribute \src "libresoc.v:200846.9-200846.17" + attribute \src "libresoc.v:203159.9-203159.17" case 1'1 case end @@ -422673,14 +426696,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:200855.3-200864.6" - process $proc$libresoc.v:200855$14866 + attribute \src "libresoc.v:203168.3-203177.6" + process $proc$libresoc.v:203168$15051 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:200856.5-200856.29" + attribute \src "libresoc.v:203169.5-203169.29" switch \initial - attribute \src "libresoc.v:200856.9-200856.17" + attribute \src "libresoc.v:203169.9-203169.17" case 1'1 case end @@ -422696,14 +426719,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:200865.3-200874.6" - process $proc$libresoc.v:200865$14867 + attribute \src "libresoc.v:203178.3-203187.6" + process $proc$libresoc.v:203178$15052 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:200866.5-200866.29" + attribute \src "libresoc.v:203179.5-203179.29" switch \initial - attribute \src "libresoc.v:200866.9-200866.17" + attribute \src "libresoc.v:203179.9-203179.17" case 1'1 case end @@ -422719,14 +426742,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:200875.3-200884.6" - process $proc$libresoc.v:200875$14868 + attribute \src "libresoc.v:203188.3-203197.6" + process $proc$libresoc.v:203188$15053 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:200876.5-200876.29" + attribute \src "libresoc.v:203189.5-203189.29" switch \initial - attribute \src "libresoc.v:200876.9-200876.17" + attribute \src "libresoc.v:203189.9-203189.17" case 1'1 case end @@ -422742,14 +426765,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:200885.3-200894.6" - process $proc$libresoc.v:200885$14869 + attribute \src "libresoc.v:203198.3-203207.6" + process $proc$libresoc.v:203198$15054 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:200886.5-200886.29" + attribute \src "libresoc.v:203199.5-203199.29" switch \initial - attribute \src "libresoc.v:200886.9-200886.17" + attribute \src "libresoc.v:203199.9-203199.17" case 1'1 case end @@ -422765,14 +426788,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:200895.3-200904.6" - process $proc$libresoc.v:200895$14870 + attribute \src "libresoc.v:203208.3-203217.6" + process $proc$libresoc.v:203208$15055 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:200896.5-200896.29" + attribute \src "libresoc.v:203209.5-203209.29" switch \initial - attribute \src "libresoc.v:200896.9-200896.17" + attribute \src "libresoc.v:203209.9-203209.17" case 1'1 case end @@ -422788,14 +426811,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:200905.3-200914.6" - process $proc$libresoc.v:200905$14871 + attribute \src "libresoc.v:203218.3-203227.6" + process $proc$libresoc.v:203218$15056 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:200906.5-200906.29" + attribute \src "libresoc.v:203219.5-203219.29" switch \initial - attribute \src "libresoc.v:200906.9-200906.17" + attribute \src "libresoc.v:203219.9-203219.17" case 1'1 case end @@ -422811,14 +426834,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:200915.3-200924.6" - process $proc$libresoc.v:200915$14872 + attribute \src "libresoc.v:203228.3-203237.6" + process $proc$libresoc.v:203228$15057 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:200916.5-200916.29" + attribute \src "libresoc.v:203229.5-203229.29" switch \initial - attribute \src "libresoc.v:200916.9-200916.17" + attribute \src "libresoc.v:203229.9-203229.17" case 1'1 case end @@ -422834,14 +426857,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:200925.3-200934.6" - process $proc$libresoc.v:200925$14873 + attribute \src "libresoc.v:203238.3-203247.6" + process $proc$libresoc.v:203238$15058 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:200926.5-200926.29" + attribute \src "libresoc.v:203239.5-203239.29" switch \initial - attribute \src "libresoc.v:200926.9-200926.17" + attribute \src "libresoc.v:203239.9-203239.17" case 1'1 case end @@ -422857,14 +426880,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:200935.3-200944.6" - process $proc$libresoc.v:200935$14874 + attribute \src "libresoc.v:203248.3-203257.6" + process $proc$libresoc.v:203248$15059 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:200936.5-200936.29" + attribute \src "libresoc.v:203249.5-203249.29" switch \initial - attribute \src "libresoc.v:200936.9-200936.17" + attribute \src "libresoc.v:203249.9-203249.17" case 1'1 case end @@ -422880,14 +426903,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:200945.3-200954.6" - process $proc$libresoc.v:200945$14875 + attribute \src "libresoc.v:203258.3-203267.6" + process $proc$libresoc.v:203258$15060 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:200946.5-200946.29" + attribute \src "libresoc.v:203259.5-203259.29" switch \initial - attribute \src "libresoc.v:200946.9-200946.17" + attribute \src "libresoc.v:203259.9-203259.17" case 1'1 case end @@ -422903,14 +426926,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:200955.3-200964.6" - process $proc$libresoc.v:200955$14876 + attribute \src "libresoc.v:203268.3-203277.6" + process $proc$libresoc.v:203268$15061 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:200956.5-200956.29" + attribute \src "libresoc.v:203269.5-203269.29" switch \initial - attribute \src "libresoc.v:200956.9-200956.17" + attribute \src "libresoc.v:203269.9-203269.17" case 1'1 case end @@ -422926,14 +426949,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:200965.3-200974.6" - process $proc$libresoc.v:200965$14877 + attribute \src "libresoc.v:203278.3-203287.6" + process $proc$libresoc.v:203278$15062 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:200966.5-200966.29" + attribute \src "libresoc.v:203279.5-203279.29" switch \initial - attribute \src "libresoc.v:200966.9-200966.17" + attribute \src "libresoc.v:203279.9-203279.17" case 1'1 case end @@ -422949,14 +426972,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:200975.3-200984.6" - process $proc$libresoc.v:200975$14878 + attribute \src "libresoc.v:203288.3-203297.6" + process $proc$libresoc.v:203288$15063 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:200976.5-200976.29" + attribute \src "libresoc.v:203289.5-203289.29" switch \initial - attribute \src "libresoc.v:200976.9-200976.17" + attribute \src "libresoc.v:203289.9-203289.17" case 1'1 case end @@ -422972,14 +426995,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:200985.3-200994.6" - process $proc$libresoc.v:200985$14879 + attribute \src "libresoc.v:203298.3-203307.6" + process $proc$libresoc.v:203298$15064 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:200986.5-200986.29" + attribute \src "libresoc.v:203299.5-203299.29" switch \initial - attribute \src "libresoc.v:200986.9-200986.17" + attribute \src "libresoc.v:203299.9-203299.17" case 1'1 case end @@ -422995,14 +427018,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:200995.3-201044.6" - process $proc$libresoc.v:200995$14880 + attribute \src "libresoc.v:203308.3-203357.6" + process $proc$libresoc.v:203308$15065 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:200996.5-200996.29" + attribute \src "libresoc.v:203309.5-203309.29" switch \initial - attribute \src "libresoc.v:200996.9-200996.17" + attribute \src "libresoc.v:203309.9-203309.17" case 1'1 case end @@ -423095,14 +427118,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:201045.3-201054.6" - process $proc$libresoc.v:201045$14881 + attribute \src "libresoc.v:203358.3-203367.6" + process $proc$libresoc.v:203358$15066 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:201046.5-201046.29" + attribute \src "libresoc.v:203359.5-203359.29" switch \initial - attribute \src "libresoc.v:201046.9-201046.17" + attribute \src "libresoc.v:203359.9-203359.17" case 1'1 case end @@ -423118,14 +427141,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:201055.3-201064.6" - process $proc$libresoc.v:201055$14882 + attribute \src "libresoc.v:203368.3-203377.6" + process $proc$libresoc.v:203368$15067 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:201056.5-201056.29" + attribute \src "libresoc.v:203369.5-203369.29" switch \initial - attribute \src "libresoc.v:201056.9-201056.17" + attribute \src "libresoc.v:203369.9-203369.17" case 1'1 case end @@ -423141,14 +427164,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:201065.3-201074.6" - process $proc$libresoc.v:201065$14883 + attribute \src "libresoc.v:203378.3-203387.6" + process $proc$libresoc.v:203378$15068 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:201066.5-201066.29" + attribute \src "libresoc.v:203379.5-203379.29" switch \initial - attribute \src "libresoc.v:201066.9-201066.17" + attribute \src "libresoc.v:203379.9-203379.17" case 1'1 case end @@ -423164,14 +427187,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:201075.3-201084.6" - process $proc$libresoc.v:201075$14884 + attribute \src "libresoc.v:203388.3-203397.6" + process $proc$libresoc.v:203388$15069 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:201076.5-201076.29" + attribute \src "libresoc.v:203389.5-203389.29" switch \initial - attribute \src "libresoc.v:201076.9-201076.17" + attribute \src "libresoc.v:203389.9-203389.17" case 1'1 case end @@ -423187,14 +427210,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:201085.3-201093.6" - process $proc$libresoc.v:201085$14885 + attribute \src "libresoc.v:203398.3-203406.6" + process $proc$libresoc.v:203398$15070 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14886 $1\ics_wb__dat_r$next[31:0]$14887 - attribute \src "libresoc.v:201086.5-201086.29" + assign $0\ics_wb__dat_r$next[31:0]$15071 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:203399.5-203399.29" switch \initial - attribute \src "libresoc.v:201086.9-201086.17" + attribute \src "libresoc.v:203399.9-203399.17" case 1'1 case end @@ -423203,21 +427226,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14887 0 + assign $1\ics_wb__dat_r$next[31:0]$15072 0 case - assign $1\ics_wb__dat_r$next[31:0]$14887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$15072 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14886 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15071 end - attribute \src "libresoc.v:201094.3-201102.6" - process $proc$libresoc.v:201094$14888 + attribute \src "libresoc.v:203407.3-203415.6" + process $proc$libresoc.v:203407$15073 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14889 $1\ics_wb__ack$next[0:0]$14890 - attribute \src "libresoc.v:201095.5-201095.29" + assign $0\ics_wb__ack$next[0:0]$15074 $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:203408.5-203408.29" switch \initial - attribute \src "libresoc.v:201095.9-201095.17" + attribute \src "libresoc.v:203408.9-203408.17" case 1'1 case end @@ -423226,116 +427249,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14890 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14890 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14889 - end - connect \$7 $ternary$libresoc.v:200465$14643_Y - connect \$99 $lt$libresoc.v:200466$14644_Y - connect \$101 $and$libresoc.v:200467$14645_Y - connect \$103 $lt$libresoc.v:200468$14646_Y - connect \$105 $and$libresoc.v:200469$14647_Y - connect \$107 $lt$libresoc.v:200470$14648_Y - connect \$109 $and$libresoc.v:200471$14649_Y - connect \$111 $lt$libresoc.v:200472$14650_Y - connect \$113 $and$libresoc.v:200473$14651_Y - connect \$115 $lt$libresoc.v:200474$14652_Y - connect \$117 $and$libresoc.v:200475$14653_Y - connect \$119 $lt$libresoc.v:200476$14654_Y - connect \$121 $and$libresoc.v:200477$14655_Y - connect \$123 $lt$libresoc.v:200478$14656_Y - connect \$125 $and$libresoc.v:200479$14657_Y - connect \$127 $lt$libresoc.v:200480$14658_Y - connect \$12 $eq$libresoc.v:200481$14659_Y - connect \$129 $and$libresoc.v:200482$14660_Y - connect \$131 $lt$libresoc.v:200483$14661_Y - connect \$133 $and$libresoc.v:200484$14662_Y - connect \$135 $lt$libresoc.v:200485$14663_Y - connect \$137 $and$libresoc.v:200486$14664_Y - connect \$11 $ternary$libresoc.v:200487$14665_Y - connect \$139 $lt$libresoc.v:200488$14666_Y - connect \$141 $and$libresoc.v:200489$14667_Y - connect \$143 $lt$libresoc.v:200490$14668_Y - connect \$145 $and$libresoc.v:200491$14669_Y - connect \$147 $lt$libresoc.v:200492$14670_Y - connect \$149 $and$libresoc.v:200493$14671_Y - connect \$151 $lt$libresoc.v:200494$14672_Y - connect \$153 $and$libresoc.v:200495$14673_Y - connect \$155 $lt$libresoc.v:200496$14674_Y - connect \$157 $and$libresoc.v:200497$14675_Y - connect \$159 $lt$libresoc.v:200498$14676_Y - connect \$161 $and$libresoc.v:200499$14677_Y - connect \$163 $lt$libresoc.v:200500$14678_Y - connect \$165 $and$libresoc.v:200501$14679_Y - connect \$167 $lt$libresoc.v:200502$14680_Y - connect \$16 $eq$libresoc.v:200503$14681_Y - connect \$169 $and$libresoc.v:200504$14682_Y - connect \$171 $lt$libresoc.v:200505$14683_Y - connect \$173 $and$libresoc.v:200506$14684_Y - connect \$175 $lt$libresoc.v:200507$14685_Y - connect \$177 $and$libresoc.v:200508$14686_Y - connect \$15 $ternary$libresoc.v:200509$14687_Y - connect \$179 $lt$libresoc.v:200510$14688_Y - connect \$181 $and$libresoc.v:200511$14689_Y - connect \$183 $lt$libresoc.v:200512$14690_Y - connect \$185 $and$libresoc.v:200513$14691_Y - connect \$187 $lt$libresoc.v:200514$14692_Y - connect \$189 $and$libresoc.v:200515$14693_Y - connect \$191 $lt$libresoc.v:200516$14694_Y - connect \$193 $and$libresoc.v:200517$14695_Y - connect \$195 $lt$libresoc.v:200518$14696_Y - connect \$197 $and$libresoc.v:200519$14697_Y - connect \$1 $eq$libresoc.v:200520$14698_Y - connect \$199 $lt$libresoc.v:200521$14699_Y - connect \$201 $and$libresoc.v:200522$14700_Y - connect \$204 $eq$libresoc.v:200523$14701_Y - connect \$203 $ternary$libresoc.v:200524$14702_Y - connect \$20 $eq$libresoc.v:200525$14703_Y - connect \$19 $ternary$libresoc.v:200526$14704_Y - connect \$24 $eq$libresoc.v:200527$14705_Y - connect \$23 $ternary$libresoc.v:200528$14706_Y - connect \$28 $eq$libresoc.v:200529$14707_Y - connect \$27 $ternary$libresoc.v:200530$14708_Y - connect \$32 $eq$libresoc.v:200531$14709_Y - connect \$31 $ternary$libresoc.v:200532$14710_Y - connect \$36 $eq$libresoc.v:200533$14711_Y - connect \$35 $ternary$libresoc.v:200534$14712_Y - connect \$3 $eq$libresoc.v:200535$14713_Y - connect \$40 $eq$libresoc.v:200536$14714_Y - connect \$39 $ternary$libresoc.v:200537$14715_Y - connect \$44 $eq$libresoc.v:200538$14716_Y - connect \$43 $ternary$libresoc.v:200539$14717_Y - connect \$48 $eq$libresoc.v:200540$14718_Y - connect \$47 $ternary$libresoc.v:200541$14719_Y - connect \$52 $eq$libresoc.v:200542$14720_Y - connect \$51 $ternary$libresoc.v:200543$14721_Y - connect \$56 $eq$libresoc.v:200544$14722_Y - connect \$55 $ternary$libresoc.v:200545$14723_Y - connect \$5 $and$libresoc.v:200546$14724_Y - connect \$60 $eq$libresoc.v:200547$14725_Y - connect \$59 $ternary$libresoc.v:200548$14726_Y - connect \$64 $eq$libresoc.v:200549$14727_Y - connect \$63 $ternary$libresoc.v:200550$14728_Y - connect \$68 $eq$libresoc.v:200551$14729_Y - connect \$67 $ternary$libresoc.v:200552$14730_Y - connect \$71 $shr$libresoc.v:200553$14731_Y [0] - connect \$73 $and$libresoc.v:200554$14732_Y - connect \$75 $lt$libresoc.v:200555$14733_Y - connect \$77 $and$libresoc.v:200556$14734_Y - connect \$79 $lt$libresoc.v:200557$14735_Y - connect \$81 $and$libresoc.v:200558$14736_Y - connect \$83 $lt$libresoc.v:200559$14737_Y - connect \$85 $and$libresoc.v:200560$14738_Y - connect \$87 $lt$libresoc.v:200561$14739_Y - connect \$8 $eq$libresoc.v:200562$14740_Y - connect \$89 $and$libresoc.v:200563$14741_Y - connect \$91 $lt$libresoc.v:200564$14742_Y - connect \$93 $and$libresoc.v:200565$14743_Y - connect \$95 $lt$libresoc.v:200566$14744_Y - connect \$97 $and$libresoc.v:200567$14745_Y + assign $1\ics_wb__ack$next[0:0]$15075 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15075 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15074 + end + connect \$7 $ternary$libresoc.v:202778$14828_Y + connect \$99 $lt$libresoc.v:202779$14829_Y + connect \$101 $and$libresoc.v:202780$14830_Y + connect \$103 $lt$libresoc.v:202781$14831_Y + connect \$105 $and$libresoc.v:202782$14832_Y + connect \$107 $lt$libresoc.v:202783$14833_Y + connect \$109 $and$libresoc.v:202784$14834_Y + connect \$111 $lt$libresoc.v:202785$14835_Y + connect \$113 $and$libresoc.v:202786$14836_Y + connect \$115 $lt$libresoc.v:202787$14837_Y + connect \$117 $and$libresoc.v:202788$14838_Y + connect \$119 $lt$libresoc.v:202789$14839_Y + connect \$121 $and$libresoc.v:202790$14840_Y + connect \$123 $lt$libresoc.v:202791$14841_Y + connect \$125 $and$libresoc.v:202792$14842_Y + connect \$127 $lt$libresoc.v:202793$14843_Y + connect \$12 $eq$libresoc.v:202794$14844_Y + connect \$129 $and$libresoc.v:202795$14845_Y + connect \$131 $lt$libresoc.v:202796$14846_Y + connect \$133 $and$libresoc.v:202797$14847_Y + connect \$135 $lt$libresoc.v:202798$14848_Y + connect \$137 $and$libresoc.v:202799$14849_Y + connect \$11 $ternary$libresoc.v:202800$14850_Y + connect \$139 $lt$libresoc.v:202801$14851_Y + connect \$141 $and$libresoc.v:202802$14852_Y + connect \$143 $lt$libresoc.v:202803$14853_Y + connect \$145 $and$libresoc.v:202804$14854_Y + connect \$147 $lt$libresoc.v:202805$14855_Y + connect \$149 $and$libresoc.v:202806$14856_Y + connect \$151 $lt$libresoc.v:202807$14857_Y + connect \$153 $and$libresoc.v:202808$14858_Y + connect \$155 $lt$libresoc.v:202809$14859_Y + connect \$157 $and$libresoc.v:202810$14860_Y + connect \$159 $lt$libresoc.v:202811$14861_Y + connect \$161 $and$libresoc.v:202812$14862_Y + connect \$163 $lt$libresoc.v:202813$14863_Y + connect \$165 $and$libresoc.v:202814$14864_Y + connect \$167 $lt$libresoc.v:202815$14865_Y + connect \$16 $eq$libresoc.v:202816$14866_Y + connect \$169 $and$libresoc.v:202817$14867_Y + connect \$171 $lt$libresoc.v:202818$14868_Y + connect \$173 $and$libresoc.v:202819$14869_Y + connect \$175 $lt$libresoc.v:202820$14870_Y + connect \$177 $and$libresoc.v:202821$14871_Y + connect \$15 $ternary$libresoc.v:202822$14872_Y + connect \$179 $lt$libresoc.v:202823$14873_Y + connect \$181 $and$libresoc.v:202824$14874_Y + connect \$183 $lt$libresoc.v:202825$14875_Y + connect \$185 $and$libresoc.v:202826$14876_Y + connect \$187 $lt$libresoc.v:202827$14877_Y + connect \$189 $and$libresoc.v:202828$14878_Y + connect \$191 $lt$libresoc.v:202829$14879_Y + connect \$193 $and$libresoc.v:202830$14880_Y + connect \$195 $lt$libresoc.v:202831$14881_Y + connect \$197 $and$libresoc.v:202832$14882_Y + connect \$1 $eq$libresoc.v:202833$14883_Y + connect \$199 $lt$libresoc.v:202834$14884_Y + connect \$201 $and$libresoc.v:202835$14885_Y + connect \$204 $eq$libresoc.v:202836$14886_Y + connect \$203 $ternary$libresoc.v:202837$14887_Y + connect \$20 $eq$libresoc.v:202838$14888_Y + connect \$19 $ternary$libresoc.v:202839$14889_Y + connect \$24 $eq$libresoc.v:202840$14890_Y + connect \$23 $ternary$libresoc.v:202841$14891_Y + connect \$28 $eq$libresoc.v:202842$14892_Y + connect \$27 $ternary$libresoc.v:202843$14893_Y + connect \$32 $eq$libresoc.v:202844$14894_Y + connect \$31 $ternary$libresoc.v:202845$14895_Y + connect \$36 $eq$libresoc.v:202846$14896_Y + connect \$35 $ternary$libresoc.v:202847$14897_Y + connect \$3 $eq$libresoc.v:202848$14898_Y + connect \$40 $eq$libresoc.v:202849$14899_Y + connect \$39 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$and$libresoc.v:202871$14921_Y + connect \$83 $lt$libresoc.v:202872$14922_Y + connect \$85 $and$libresoc.v:202873$14923_Y + connect \$87 $lt$libresoc.v:202874$14924_Y + connect \$8 $eq$libresoc.v:202875$14925_Y + connect \$89 $and$libresoc.v:202876$14926_Y + connect \$91 $lt$libresoc.v:202877$14927_Y + connect \$93 $and$libresoc.v:202878$14928_Y + connect \$95 $lt$libresoc.v:202879$14929_Y + connect \$97 $and$libresoc.v:202880$14930_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 2bb27e0..27d000d 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14913 +autoidx 15098 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -72,7 +72,7 @@ module \ALU_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -81,15 +81,15 @@ module \ALU_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -106,7 +106,7 @@ module \ALU_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -114,7 +114,7 @@ module \ALU_dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131,7 +131,7 @@ module \ALU_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -208,13 +208,13 @@ module \ALU_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -222,21 +222,21 @@ module \ALU_dec19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:194.3-203.6" process $proc$libresoc.v:194$1 @@ -249,7 +249,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -272,7 +272,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -295,7 +295,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -318,7 +318,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -341,7 +341,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -364,7 +364,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -387,7 +387,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -410,7 +410,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -433,7 +433,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -456,7 +456,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -479,7 +479,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -502,7 +502,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -525,7 +525,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -548,7 +548,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -642,7 +642,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -651,15 +651,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -670,7 +670,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -679,15 +679,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -704,7 +704,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -712,7 +712,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -729,7 +729,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -806,13 +806,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -820,17 +820,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -841,7 +841,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -850,15 +850,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -875,7 +875,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -883,7 +883,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -900,7 +900,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -977,13 +977,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -991,17 +991,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub10_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1012,7 +1012,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1021,15 +1021,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1046,7 +1046,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1054,7 +1054,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1071,7 +1071,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1148,13 +1148,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1162,17 +1162,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub22_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1183,7 +1183,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1192,15 +1192,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1217,7 +1217,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1225,7 +1225,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1242,7 +1242,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1319,13 +1319,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1333,17 +1333,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1354,7 +1354,7 @@ module \ALU_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1363,15 +1363,15 @@ module \ALU_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1388,7 +1388,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1396,7 +1396,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1413,7 +1413,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1490,13 +1490,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1504,17 +1504,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -1531,7 +1531,7 @@ module \ALU_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1539,7 +1539,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1556,7 +1556,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1633,13 +1633,13 @@ module \ALU_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1647,23 +1647,23 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_sgn attribute \src "libresoc.v:340.7-340.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:1385.22-1401.4" @@ -1771,7 +1771,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1810,7 +1810,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1849,7 +1849,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1888,7 +1888,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1927,7 +1927,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1966,7 +1966,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2005,7 +2005,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2044,7 +2044,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2083,7 +2083,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2122,7 +2122,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2161,7 +2161,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2200,7 +2200,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2239,7 +2239,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2278,7 +2278,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2394,7 +2394,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -2403,15 +2403,15 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -2428,7 +2428,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -2436,7 +2436,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -2453,7 +2453,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -2530,13 +2530,13 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -2544,21 +2544,21 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub0_sgn attribute \src "libresoc.v:1790.7-1790.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:1790.7-1790.20" process $proc$libresoc.v:1790$45 @@ -2579,7 +2579,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2610,7 +2610,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2641,7 +2641,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2672,7 +2672,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2703,7 +2703,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2734,7 +2734,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2765,7 +2765,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2796,7 +2796,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2827,7 +2827,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2858,7 +2858,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2889,7 +2889,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2920,7 +2920,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2951,7 +2951,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2982,7 +2982,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -3076,7 +3076,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -3085,15 +3085,15 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -3110,7 +3110,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -3118,7 +3118,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -3135,7 +3135,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -3212,13 +3212,13 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -3226,21 +3226,21 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub10_sgn attribute \src "libresoc.v:2208.7-2208.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2208.7-2208.20" process $proc$libresoc.v:2208$60 @@ -3261,7 +3261,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3320,7 +3320,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3379,7 +3379,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3438,7 +3438,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3497,7 +3497,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3556,7 +3556,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3615,7 +3615,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3674,7 +3674,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3733,7 +3733,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3792,7 +3792,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3851,7 +3851,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3910,7 +3910,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3969,7 +3969,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4028,7 +4028,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4150,7 +4150,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -4159,15 +4159,15 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -4184,7 +4184,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -4192,7 +4192,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -4209,7 +4209,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -4286,13 +4286,13 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -4300,21 +4300,21 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub22_sgn attribute \src "libresoc.v:2920.7-2920.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2920.7-2920.20" process $proc$libresoc.v:2920$75 @@ -4335,7 +4335,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4382,7 +4382,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4429,7 +4429,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4476,7 +4476,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4523,7 +4523,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4570,7 +4570,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4617,7 +4617,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4664,7 +4664,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4711,7 +4711,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4758,7 +4758,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4805,7 +4805,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4852,7 +4852,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4899,7 +4899,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4946,7 +4946,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -5056,7 +5056,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5065,15 +5065,15 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -5090,7 +5090,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5098,7 +5098,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5115,7 +5115,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5192,13 +5192,13 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5206,21 +5206,21 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub26_sgn attribute \src "libresoc.v:3506.7-3506.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3506.7-3506.20" process $proc$libresoc.v:3506$90 @@ -5241,7 +5241,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5272,7 +5272,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5303,7 +5303,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5334,7 +5334,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5365,7 +5365,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5396,7 +5396,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5427,7 +5427,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5458,7 +5458,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5489,7 +5489,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5520,7 +5520,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5551,7 +5551,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5582,7 +5582,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5613,7 +5613,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5644,7 +5644,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5738,7 +5738,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5747,15 +5747,15 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -5772,7 +5772,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5780,7 +5780,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5797,7 +5797,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5874,13 +5874,13 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5888,21 +5888,21 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub8_sgn attribute \src "libresoc.v:3924.7-3924.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3924.7-3924.20" process $proc$libresoc.v:3924$105 @@ -5923,7 +5923,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -5990,7 +5990,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6057,7 +6057,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6124,7 +6124,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6191,7 +6191,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6258,7 +6258,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6325,7 +6325,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6392,7 +6392,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6459,7 +6459,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6526,7 +6526,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6593,7 +6593,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6660,7 +6660,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6727,7 +6727,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6794,7 +6794,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6900,7 +6900,7 @@ module \BRANCH_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -6909,7 +6909,7 @@ module \BRANCH_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -6926,7 +6926,7 @@ module \BRANCH_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -6943,7 +6943,7 @@ module \BRANCH_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7020,23 +7020,23 @@ module \BRANCH_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \BRANCH_dec19_rc_sel attribute \src "libresoc.v:4720.7-4720.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:4720.7-4720.20" process $proc$libresoc.v:4720$114 @@ -7057,7 +7057,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7088,7 +7088,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7119,7 +7119,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7150,7 +7150,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7181,7 +7181,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7212,7 +7212,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7243,7 +7243,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7274,7 +7274,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7332,7 +7332,7 @@ module \CR_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7341,7 +7341,7 @@ module \CR_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7358,7 +7358,7 @@ module \CR_dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7435,19 +7435,19 @@ module \CR_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec19_rc_sel attribute \src "libresoc.v:5008.7-5008.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:5008.7-5008.20" process $proc$libresoc.v:5008$120 @@ -7468,7 +7468,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7523,7 +7523,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7578,7 +7578,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7633,7 +7633,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7688,7 +7688,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7770,7 +7770,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7779,7 +7779,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7790,7 +7790,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7799,7 +7799,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7816,7 +7816,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7893,15 +7893,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7912,7 +7912,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7921,7 +7921,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -7938,7 +7938,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8015,15 +8015,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub15_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8034,7 +8034,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8043,7 +8043,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8060,7 +8060,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8137,15 +8137,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub16_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8156,7 +8156,7 @@ module \CR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8165,7 +8165,7 @@ module \CR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8182,7 +8182,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8259,15 +8259,15 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8284,7 +8284,7 @@ module \CR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8361,21 +8361,21 @@ module \CR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_rc_sel attribute \src "libresoc.v:5314.7-5314.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:5934.21-5941.4" @@ -8436,7 +8436,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8471,7 +8471,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8506,7 +8506,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8541,7 +8541,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8576,7 +8576,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8643,7 +8643,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8652,7 +8652,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8669,7 +8669,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8746,19 +8746,19 @@ module \CR_dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:6072.7-6072.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6072.7-6072.20" process $proc$libresoc.v:6072$132 @@ -8779,7 +8779,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8802,7 +8802,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8825,7 +8825,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8848,7 +8848,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8871,7 +8871,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8921,7 +8921,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8930,7 +8930,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -8947,7 +8947,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -9024,19 +9024,19 @@ module \CR_dec31_dec_sub15 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:6258.7-6258.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6258.7-6258.20" process $proc$libresoc.v:6258$138 @@ -9057,7 +9057,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9204,7 +9204,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9351,7 +9351,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9498,7 +9498,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9645,7 +9645,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9819,7 +9819,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9828,7 +9828,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -9845,7 +9845,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -9922,19 +9922,19 @@ module \CR_dec31_dec_sub16 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel attribute \src "libresoc.v:6909.7-6909.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6909.7-6909.20" process $proc$libresoc.v:6909$144 @@ -9955,7 +9955,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9978,7 +9978,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10001,7 +10001,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10024,7 +10024,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10047,7 +10047,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -10097,7 +10097,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10106,7 +10106,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10123,7 +10123,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10200,19 +10200,19 @@ module \CR_dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:7095.7-7095.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:7095.7-7095.20" process $proc$libresoc.v:7095$150 @@ -10233,7 +10233,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10256,7 +10256,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10279,7 +10279,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10302,7 +10302,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10325,7 +10325,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10411,7 +10411,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10420,15 +10420,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10439,7 +10439,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10448,15 +10448,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10473,7 +10473,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10481,7 +10481,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10498,7 +10498,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10575,13 +10575,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10589,17 +10589,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10610,7 +10610,7 @@ module \DIV_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10619,15 +10619,15 @@ module \DIV_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10644,7 +10644,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10652,7 +10652,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10669,7 +10669,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10746,13 +10746,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10760,17 +10760,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -10787,7 +10787,7 @@ module \DIV_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10795,7 +10795,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10812,7 +10812,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10889,13 +10889,13 @@ module \DIV_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10903,23 +10903,23 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_sgn attribute \src "libresoc.v:7281.7-7281.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:7813.23-7829.4" @@ -10978,7 +10978,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11005,7 +11005,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11032,7 +11032,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11059,7 +11059,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11086,7 +11086,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11113,7 +11113,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11140,7 +11140,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11167,7 +11167,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11194,7 +11194,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11221,7 +11221,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11248,7 +11248,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11275,7 +11275,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11302,7 +11302,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11329,7 +11329,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11422,7 +11422,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -11431,15 +11431,15 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -11456,7 +11456,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -11464,7 +11464,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -11481,7 +11481,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -11558,13 +11558,13 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -11572,21 +11572,21 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub11_sgn attribute \src "libresoc.v:8038.7-8038.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8038.7-8038.20" process $proc$libresoc.v:8038$180 @@ -11607,7 +11607,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11666,7 +11666,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11725,7 +11725,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11784,7 +11784,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11843,7 +11843,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11902,7 +11902,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11961,7 +11961,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12020,7 +12020,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12079,7 +12079,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12138,7 +12138,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12197,7 +12197,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12256,7 +12256,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12315,7 +12315,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12374,7 +12374,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12496,7 +12496,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -12505,15 +12505,15 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -12530,7 +12530,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -12538,7 +12538,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -12555,7 +12555,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -12632,13 +12632,13 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -12646,21 +12646,21 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub9_sgn attribute \src "libresoc.v:8750.7-8750.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8750.7-8750.20" process $proc$libresoc.v:8750$195 @@ -12681,7 +12681,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12740,7 +12740,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12799,7 +12799,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12858,7 +12858,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12917,7 +12917,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12976,7 +12976,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13035,7 +13035,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13094,7 +13094,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13153,7 +13153,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13212,7 +13212,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13271,7 +13271,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13330,7 +13330,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13389,7 +13389,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13448,7 +13448,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13557,7 +13557,7 @@ module \LDST_dec31 wire $1\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13568,7 +13568,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13577,9 +13577,9 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13590,7 +13590,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13599,7 +13599,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13616,7 +13616,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13624,7 +13624,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13641,7 +13641,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13718,9 +13718,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13728,28 +13728,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13760,7 +13760,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13769,7 +13769,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13786,7 +13786,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13794,7 +13794,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13811,7 +13811,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13888,9 +13888,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13898,28 +13898,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13930,7 +13930,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13939,7 +13939,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -13956,7 +13956,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13964,7 +13964,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13981,7 +13981,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14058,9 +14058,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14068,28 +14068,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -14100,7 +14100,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -14109,7 +14109,7 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -14126,7 +14126,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14134,7 +14134,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14151,7 +14151,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14228,9 +14228,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14238,26 +14238,26 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -14274,7 +14274,7 @@ module \LDST_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14282,7 +14282,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14299,7 +14299,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14376,9 +14376,9 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14386,32 +14386,32 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_upd attribute \src "libresoc.v:9462.7-9462.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:10330.24-10345.4" @@ -14496,7 +14496,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14531,7 +14531,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14566,7 +14566,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14601,7 +14601,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14636,7 +14636,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14671,7 +14671,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14706,7 +14706,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14741,7 +14741,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14776,7 +14776,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14811,7 +14811,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14846,7 +14846,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14881,7 +14881,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14916,7 +14916,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -15014,7 +15014,7 @@ module \LDST_dec31_dec_sub20 wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15025,7 +15025,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15034,7 +15034,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -15051,7 +15051,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -15059,7 +15059,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15076,7 +15076,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15153,9 +15153,9 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15163,30 +15163,30 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub20_upd attribute \src "libresoc.v:10652.7-10652.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:10652.7-10652.20" process $proc$libresoc.v:10652$223 @@ -15207,7 +15207,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15250,7 +15250,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15293,7 +15293,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15336,7 +15336,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15379,7 +15379,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15422,7 +15422,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15465,7 +15465,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15508,7 +15508,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15551,7 +15551,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15594,7 +15594,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15637,7 +15637,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15680,7 +15680,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15723,7 +15723,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15816,7 +15816,7 @@ module \LDST_dec31_dec_sub21 wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15827,7 +15827,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15836,7 +15836,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -15853,7 +15853,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -15861,7 +15861,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15878,7 +15878,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15955,9 +15955,9 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15965,30 +15965,30 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub21_upd attribute \src "libresoc.v:11169.7-11169.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11169.7-11169.20" process $proc$libresoc.v:11169$237 @@ -16009,7 +16009,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16084,7 +16084,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16159,7 +16159,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16234,7 +16234,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16309,7 +16309,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16384,7 +16384,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16459,7 +16459,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16534,7 +16534,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16609,7 +16609,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16684,7 +16684,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16759,7 +16759,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16834,7 +16834,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16909,7 +16909,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -17034,7 +17034,7 @@ module \LDST_dec31_dec_sub22 wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17045,7 +17045,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17054,7 +17054,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -17071,7 +17071,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -17079,7 +17079,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -17096,7 +17096,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -17173,9 +17173,9 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17183,30 +17183,30 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub22_upd attribute \src "libresoc.v:11998.7-11998.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11998.7-11998.20" process $proc$libresoc.v:11998$251 @@ -17227,7 +17227,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17278,7 +17278,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17329,7 +17329,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17380,7 +17380,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17431,7 +17431,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17482,7 +17482,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17533,7 +17533,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17584,7 +17584,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17635,7 +17635,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17686,7 +17686,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17737,7 +17737,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17788,7 +17788,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17839,7 +17839,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17940,7 +17940,7 @@ module \LDST_dec31_dec_sub23 wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17951,7 +17951,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17960,7 +17960,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -17977,7 +17977,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -17985,7 +17985,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -18002,7 +18002,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -18079,9 +18079,9 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -18089,30 +18089,30 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub23_upd attribute \src "libresoc.v:12593.7-12593.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:12593.7-12593.20" process $proc$libresoc.v:12593$265 @@ -18133,7 +18133,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18208,7 +18208,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18283,7 +18283,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18358,7 +18358,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18433,7 +18433,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18508,7 +18508,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18583,7 +18583,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18658,7 +18658,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18733,7 +18733,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18808,7 +18808,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18883,7 +18883,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18958,7 +18958,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -19033,7 +19033,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -19158,7 +19158,7 @@ module \LDST_dec58 wire $1\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $1\LDST_dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19169,7 +19169,7 @@ module \LDST_dec58 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19178,7 +19178,7 @@ module \LDST_dec58 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -19195,7 +19195,7 @@ module \LDST_dec58 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19203,7 +19203,7 @@ module \LDST_dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19220,7 +19220,7 @@ module \LDST_dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19297,9 +19297,9 @@ module \LDST_dec58 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19307,30 +19307,30 @@ module \LDST_dec58 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec58_upd attribute \src "libresoc.v:13422.7-13422.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13422.7-13422.20" process $proc$libresoc.v:13422$279 @@ -19351,7 +19351,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19382,7 +19382,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19413,7 +19413,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19444,7 +19444,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19475,7 +19475,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19506,7 +19506,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19537,7 +19537,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19568,7 +19568,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19599,7 +19599,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19630,7 +19630,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19661,7 +19661,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19692,7 +19692,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19723,7 +19723,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19804,7 +19804,7 @@ module \LDST_dec62 wire $1\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19815,7 +19815,7 @@ module \LDST_dec62 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19824,7 +19824,7 @@ module \LDST_dec62 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -19841,7 +19841,7 @@ module \LDST_dec62 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19849,7 +19849,7 @@ module \LDST_dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19866,7 +19866,7 @@ module \LDST_dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19943,9 +19943,9 @@ module \LDST_dec62 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19953,30 +19953,30 @@ module \LDST_dec62 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec62_upd attribute \src "libresoc.v:13822.7-13822.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13822.7-13822.20" process $proc$libresoc.v:13822$293 @@ -19997,7 +19997,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20024,7 +20024,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20051,7 +20051,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20078,7 +20078,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20105,7 +20105,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20132,7 +20132,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20159,7 +20159,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20186,7 +20186,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20213,7 +20213,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20240,7 +20240,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20267,7 +20267,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20294,7 +20294,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20321,7 +20321,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20411,7 +20411,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20420,15 +20420,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20439,7 +20439,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20448,15 +20448,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20473,7 +20473,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20481,7 +20481,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20498,7 +20498,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20575,13 +20575,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20589,17 +20589,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20610,7 +20610,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20619,15 +20619,15 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20644,7 +20644,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20652,7 +20652,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20669,7 +20669,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20746,13 +20746,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20760,17 +20760,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -20787,7 +20787,7 @@ module \LOGICAL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20795,7 +20795,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20812,7 +20812,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20889,13 +20889,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20903,23 +20903,23 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_sgn attribute \src "libresoc.v:14183.7-14183.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:14715.27-14731.4" @@ -20978,7 +20978,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21005,7 +21005,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21032,7 +21032,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21059,7 +21059,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21086,7 +21086,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21113,7 +21113,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21140,7 +21140,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21167,7 +21167,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21194,7 +21194,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21221,7 +21221,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21248,7 +21248,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21275,7 +21275,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21302,7 +21302,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21329,7 +21329,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21422,7 +21422,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -21431,15 +21431,15 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -21456,7 +21456,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -21464,7 +21464,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -21481,7 +21481,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -21558,13 +21558,13 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -21572,21 +21572,21 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub26_sgn attribute \src "libresoc.v:14940.7-14940.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:14940.7-14940.20" process $proc$libresoc.v:14940$323 @@ -21607,7 +21607,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21662,7 +21662,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21717,7 +21717,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21772,7 +21772,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21827,7 +21827,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21882,7 +21882,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21937,7 +21937,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21992,7 +21992,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22047,7 +22047,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22102,7 +22102,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22157,7 +22157,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22212,7 +22212,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22267,7 +22267,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22322,7 +22322,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22440,7 +22440,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -22449,15 +22449,15 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -22474,7 +22474,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -22482,7 +22482,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -22499,7 +22499,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -22576,13 +22576,13 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -22590,21 +22590,21 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub28_sgn attribute \src "libresoc.v:15610.7-15610.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:15610.7-15610.20" process $proc$libresoc.v:15610$338 @@ -22625,7 +22625,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22684,7 +22684,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22743,7 +22743,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22802,7 +22802,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22861,7 +22861,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22920,7 +22920,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22979,7 +22979,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23038,7 +23038,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23097,7 +23097,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23156,7 +23156,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23215,7 +23215,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23274,7 +23274,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23333,7 +23333,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23392,7 +23392,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23490,7 +23490,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23499,7 +23499,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23510,7 +23510,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23519,7 +23519,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23536,7 +23536,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23553,7 +23553,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23630,19 +23630,19 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23653,7 +23653,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23662,7 +23662,7 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23679,7 +23679,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23696,7 +23696,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23773,19 +23773,19 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -23802,7 +23802,7 @@ module \MUL_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23819,7 +23819,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23896,25 +23896,25 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_sgn attribute \src "libresoc.v:16322.7-16322.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:16764.23-16774.4" @@ -23961,7 +23961,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23988,7 +23988,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24015,7 +24015,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24042,7 +24042,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24069,7 +24069,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24096,7 +24096,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24123,7 +24123,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24150,7 +24150,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -24219,7 +24219,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24228,7 +24228,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -24245,7 +24245,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24262,7 +24262,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24339,23 +24339,23 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub11_sgn attribute \src "libresoc.v:16899.7-16899.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:16899.7-16899.20" process $proc$libresoc.v:16899$356 @@ -24376,7 +24376,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24419,7 +24419,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24462,7 +24462,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24505,7 +24505,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24548,7 +24548,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24591,7 +24591,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24634,7 +24634,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24677,7 +24677,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24759,7 +24759,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24768,7 +24768,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -24785,7 +24785,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24802,7 +24802,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24879,23 +24879,23 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub9_sgn attribute \src "libresoc.v:17259.7-17259.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:17259.7-17259.20" process $proc$libresoc.v:17259$365 @@ -24916,7 +24916,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24959,7 +24959,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25002,7 +25002,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25045,7 +25045,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25088,7 +25088,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25131,7 +25131,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25174,7 +25174,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25217,7 +25217,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25311,7 +25311,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25320,15 +25320,15 @@ module \SHIFT_ROT_dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -25345,7 +25345,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -25362,7 +25362,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -25439,25 +25439,25 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec30_sgn attribute \src "libresoc.v:17619.7-17619.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch attribute \src "libresoc.v:17619.7-17619.20" process $proc$libresoc.v:17619$377 @@ -25478,7 +25478,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25537,7 +25537,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25596,7 +25596,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25655,7 +25655,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25714,7 +25714,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25773,7 +25773,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25832,7 +25832,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25891,7 +25891,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25950,7 +25950,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26009,7 +26009,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26068,7 +26068,7 @@ module \SHIFT_ROT_dec30 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -26178,7 +26178,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26187,15 +26187,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26206,7 +26206,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26215,15 +26215,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26240,7 +26240,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26257,7 +26257,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26334,21 +26334,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26359,7 +26359,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26368,15 +26368,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26393,7 +26393,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26410,7 +26410,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26487,21 +26487,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26512,7 +26512,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26521,15 +26521,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26546,7 +26546,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26563,7 +26563,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26640,21 +26640,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -26671,7 +26671,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26688,7 +26688,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26765,27 +26765,27 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_sgn attribute \src "libresoc.v:18199.7-18199.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:18827.29-18840.4" @@ -26854,7 +26854,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26885,7 +26885,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26916,7 +26916,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26947,7 +26947,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26978,7 +26978,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27009,7 +27009,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27040,7 +27040,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27071,7 +27071,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27102,7 +27102,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27133,7 +27133,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27164,7 +27164,7 @@ module \SHIFT_ROT_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -27250,7 +27250,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27259,15 +27259,15 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -27284,7 +27284,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27301,7 +27301,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27378,25 +27378,25 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn attribute \src "libresoc.v:19055.7-19055.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19055.7-19055.20" process $proc$libresoc.v:19055$401 @@ -27417,7 +27417,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27452,7 +27452,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27487,7 +27487,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27522,7 +27522,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27557,7 +27557,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27592,7 +27592,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27627,7 +27627,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27662,7 +27662,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27697,7 +27697,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27732,7 +27732,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27767,7 +27767,7 @@ module \SHIFT_ROT_dec31_dec_sub24 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27853,7 +27853,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27862,15 +27862,15 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -27887,7 +27887,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27904,7 +27904,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27981,25 +27981,25 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn attribute \src "libresoc.v:19437.7-19437.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19437.7-19437.20" process $proc$libresoc.v:19437$413 @@ -28020,7 +28020,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28051,7 +28051,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28082,7 +28082,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28113,7 +28113,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28144,7 +28144,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28175,7 +28175,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28206,7 +28206,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28237,7 +28237,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28268,7 +28268,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28299,7 +28299,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28330,7 +28330,7 @@ module \SHIFT_ROT_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28412,7 +28412,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28421,15 +28421,15 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -28446,7 +28446,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -28463,7 +28463,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28540,25 +28540,25 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn attribute \src "libresoc.v:19786.7-19786.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19786.7-19786.20" process $proc$libresoc.v:19786$425 @@ -28579,7 +28579,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28614,7 +28614,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28649,7 +28649,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28684,7 +28684,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28719,7 +28719,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28754,7 +28754,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28789,7 +28789,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28824,7 +28824,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28859,7 +28859,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28894,7 +28894,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28929,7 +28929,7 @@ module \SHIFT_ROT_dec31_dec_sub27 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -29010,7 +29010,7 @@ module \SPR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29019,7 +29019,7 @@ module \SPR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -29030,7 +29030,7 @@ module \SPR_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29039,7 +29039,7 @@ module \SPR_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29056,7 +29056,7 @@ module \SPR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29133,17 +29133,17 @@ module \SPR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29160,7 +29160,7 @@ module \SPR_dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29237,23 +29237,23 @@ module \SPR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_rc_sel attribute \src "libresoc.v:20168.7-20168.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:20427.23-20435.4" @@ -29285,7 +29285,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29308,7 +29308,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29331,7 +29331,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29354,7 +29354,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29377,7 +29377,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29400,7 +29400,7 @@ module \SPR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -29456,7 +29456,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -29465,7 +29465,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -29482,7 +29482,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29559,21 +29559,21 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:20504.7-20504.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:20504.7-20504.20" process $proc$libresoc.v:20504$439 @@ -29594,7 +29594,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29621,7 +29621,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29648,7 +29648,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29675,7 +29675,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29702,7 +29702,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29729,7 +29729,7 @@ module \SPR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -30873,9 +30873,9 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:21161.7-21161.15" wire \initial @@ -31077,9 +31077,9 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:21223.7-21223.15" wire \initial @@ -32173,9 +32173,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -35288,9 +35288,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a @@ -36331,9 +36331,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36677,9 +36677,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -37203,9 +37203,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -38725,9 +38725,9 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26241.7-26241.15" wire \initial @@ -38929,9 +38929,9 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26303.7-26303.15" wire \initial @@ -39133,9 +39133,9 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26365.7-26365.15" wire \initial @@ -39337,9 +39337,9 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26427.7-26427.15" wire \initial @@ -39541,9 +39541,9 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26489.7-26489.15" wire \initial @@ -39745,9 +39745,9 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26551.7-26551.15" wire \initial @@ -39949,9 +39949,9 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26613.7-26613.15" wire \initial @@ -40153,9 +40153,9 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26675.7-26675.15" wire \initial @@ -40357,9 +40357,9 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26737.7-26737.15" wire \initial @@ -40561,9 +40561,9 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:26799.7-26799.15" wire \initial @@ -40723,9 +40723,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -41749,9 +41749,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a @@ -42981,9 +42981,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -44027,9 +44027,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -44596,9 +44596,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -45524,9 +45524,9 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31575.7-31575.15" wire \initial @@ -45728,9 +45728,9 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31637.7-31637.15" wire \initial @@ -45932,9 +45932,9 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31699.7-31699.15" wire \initial @@ -46136,9 +46136,9 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31761.7-31761.15" wire \initial @@ -46340,9 +46340,9 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31823.7-31823.15" wire \initial @@ -46544,9 +46544,9 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31885.7-31885.15" wire \initial @@ -46748,9 +46748,9 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:31947.7-31947.15" wire \initial @@ -46952,9 +46952,9 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:32009.7-32009.15" wire \initial @@ -47156,9 +47156,9 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:32071.7-32071.15" wire \initial @@ -50601,9 +50601,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -52840,9 +52840,9 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "libresoc.v:34540.7-34540.15" wire \initial @@ -62431,9 +62431,9 @@ module \core wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 97 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter @@ -62623,11 +62623,11 @@ module \core wire \dec_ALU_ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_ALU_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_ALU_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia @@ -62735,9 +62735,9 @@ module \core wire \dec_BRANCH_BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -62835,9 +62835,9 @@ module \core attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_CR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_CR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_DIV_DIV__data_len @@ -62969,11 +62969,11 @@ module \core wire \dec_DIV_DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_DIV_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_DIV_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse @@ -63102,11 +63102,11 @@ module \core wire \dec_LDST_LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LDST_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LDST_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len @@ -63238,11 +63238,11 @@ module \core wire \dec_LOGICAL_LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LOGICAL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LOGICAL_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63358,9 +63358,9 @@ module \core wire \dec_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_MUL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63490,9 +63490,9 @@ module \core wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -63592,9 +63592,9 @@ module \core wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SPR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 74 \dmi__addr @@ -65721,15 +65721,15 @@ module \core wire width 3 input 9 \sv__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" wire input 68 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \sv_a_nz$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 87 \wb_dcache_en @@ -85800,97 +85800,125 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:49145.1-49778.10" +attribute \src "libresoc.v:49145.1-49881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr + attribute \src "libresoc.v:49840.3-49849.6" + wire width 4 $0\cr_pred__data_o[3:0] attribute \src "libresoc.v:49146.7-49146.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49692.3-49700.6" - wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:49528.3-49529.43" - wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:49474.13-49474.35" - wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49711.3-49719.6" - wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:49526.3-49527.43" - wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:49478.13-49478.35" - wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49730.3-49738.6" - wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:49530.3-49531.35" + attribute \src "libresoc.v:49774.3-49782.6" + wire width 8 $0\ren_delay$17$next[7:0]$3056 + attribute \src "libresoc.v:49594.3-49595.43" + wire width 8 $0\ren_delay$17[7:0]$3053 + attribute \src "libresoc.v:49526.13-49526.35" + wire width 8 $0\ren_delay$17[7:0]$3074 + attribute \src "libresoc.v:49793.3-49801.6" + wire width 8 $0\ren_delay$34$next[7:0]$3060 + attribute \src "libresoc.v:49592.3-49593.43" + wire width 8 $0\ren_delay$34[7:0]$3051 + attribute \src "libresoc.v:49530.13-49530.35" + wire width 8 $0\ren_delay$34[7:0]$3076 + attribute \src "libresoc.v:49812.3-49820.6" + wire width 8 $0\ren_delay$51$next[7:0]$3064 + attribute \src "libresoc.v:49590.3-49591.43" + wire width 8 $0\ren_delay$51[7:0]$3049 + attribute \src "libresoc.v:49534.13-49534.35" + wire width 8 $0\ren_delay$51[7:0]$3078 + attribute \src "libresoc.v:49831.3-49839.6" + wire width 8 $0\ren_delay$next[7:0]$3068 + attribute \src "libresoc.v:49596.3-49597.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49739.3-49748.6" + attribute \src "libresoc.v:49783.3-49792.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49701.3-49710.6" + attribute \src "libresoc.v:49802.3-49811.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49720.3-49729.6" + attribute \src "libresoc.v:49821.3-49830.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49692.3-49700.6" - wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49711.3-49719.6" - wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49730.3-49738.6" - wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49472.13-49472.30" + attribute \src "libresoc.v:49840.3-49849.6" + wire width 4 $1\cr_pred__data_o[3:0] + attribute \src "libresoc.v:49774.3-49782.6" + wire width 8 $1\ren_delay$17$next[7:0]$3057 + attribute \src "libresoc.v:49793.3-49801.6" + wire width 8 $1\ren_delay$34$next[7:0]$3061 + attribute \src "libresoc.v:49812.3-49820.6" + wire width 8 $1\ren_delay$51$next[7:0]$3065 + attribute \src "libresoc.v:49831.3-49839.6" + wire width 8 $1\ren_delay$next[7:0]$3069 + attribute \src "libresoc.v:49524.13-49524.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49739.3-49748.6" + attribute \src "libresoc.v:49783.3-49792.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49701.3-49710.6" + attribute \src "libresoc.v:49802.3-49811.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49720.3-49729.6" + attribute \src "libresoc.v:49821.3-49830.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49502.17-49502.125" - wire width 4 $or$libresoc.v:49502$3016_Y - attribute \src "libresoc.v:49503.18-49503.126" - wire width 4 $or$libresoc.v:49503$3017_Y - attribute \src "libresoc.v:49504.18-49504.96" - wire width 4 $or$libresoc.v:49504$3018_Y - attribute \src "libresoc.v:49505.18-49505.96" - wire width 4 $or$libresoc.v:49505$3019_Y - attribute \src "libresoc.v:49508.18-49508.126" - wire width 4 $or$libresoc.v:49508$3022_Y - attribute \src "libresoc.v:49509.18-49509.126" - wire width 4 $or$libresoc.v:49509$3023_Y - attribute \src "libresoc.v:49510.18-49510.97" - wire width 4 $or$libresoc.v:49510$3024_Y - attribute \src "libresoc.v:49511.18-49511.126" - wire width 4 $or$libresoc.v:49511$3025_Y - attribute \src "libresoc.v:49512.18-49512.126" - wire width 4 $or$libresoc.v:49512$3026_Y - attribute \src "libresoc.v:49513.18-49513.97" - wire width 4 $or$libresoc.v:49513$3027_Y - attribute \src "libresoc.v:49514.18-49514.97" - wire width 4 $or$libresoc.v:49514$3028_Y - attribute \src "libresoc.v:49516.18-49516.126" - wire width 4 $or$libresoc.v:49516$3030_Y - attribute \src "libresoc.v:49517.17-49517.125" - wire width 4 $or$libresoc.v:49517$3031_Y - attribute \src "libresoc.v:49518.18-49518.126" - wire width 4 $or$libresoc.v:49518$3032_Y - attribute \src "libresoc.v:49519.18-49519.97" - wire width 4 $or$libresoc.v:49519$3033_Y - attribute \src "libresoc.v:49520.18-49520.126" - wire width 4 $or$libresoc.v:49520$3034_Y - attribute \src "libresoc.v:49521.18-49521.126" - wire width 4 $or$libresoc.v:49521$3035_Y - attribute \src "libresoc.v:49522.18-49522.97" - wire width 4 $or$libresoc.v:49522$3036_Y - attribute \src "libresoc.v:49523.18-49523.97" - wire width 4 $or$libresoc.v:49523$3037_Y - attribute \src "libresoc.v:49524.17-49524.125" - wire width 4 $or$libresoc.v:49524$3038_Y - attribute \src "libresoc.v:49525.17-49525.94" - wire width 4 $or$libresoc.v:49525$3039_Y - attribute \src "libresoc.v:49506.18-49506.100" - wire $reduce_or$libresoc.v:49506$3020_Y - attribute \src "libresoc.v:49507.17-49507.95" - wire $reduce_or$libresoc.v:49507$3021_Y - attribute \src "libresoc.v:49515.18-49515.100" - wire $reduce_or$libresoc.v:49515$3029_Y + attribute \src "libresoc.v:49558.17-49558.131" + wire width 4 $or$libresoc.v:49558$3016_Y + attribute \src "libresoc.v:49559.18-49559.132" + wire width 4 $or$libresoc.v:49559$3017_Y + attribute \src "libresoc.v:49560.18-49560.96" + wire width 4 $or$libresoc.v:49560$3018_Y + attribute \src "libresoc.v:49561.18-49561.96" + wire width 4 $or$libresoc.v:49561$3019_Y + attribute \src "libresoc.v:49564.18-49564.126" + wire width 4 $or$libresoc.v:49564$3022_Y + attribute \src "libresoc.v:49565.18-49565.126" + wire width 4 $or$libresoc.v:49565$3023_Y + attribute \src "libresoc.v:49566.18-49566.97" + wire width 4 $or$libresoc.v:49566$3024_Y + attribute \src "libresoc.v:49567.18-49567.126" + wire width 4 $or$libresoc.v:49567$3025_Y + attribute \src "libresoc.v:49568.18-49568.126" + wire width 4 $or$libresoc.v:49568$3026_Y + attribute \src "libresoc.v:49569.18-49569.97" + wire width 4 $or$libresoc.v:49569$3027_Y + attribute \src "libresoc.v:49570.18-49570.97" + wire width 4 $or$libresoc.v:49570$3028_Y + attribute \src "libresoc.v:49572.18-49572.126" + wire width 4 $or$libresoc.v:49572$3030_Y + attribute \src "libresoc.v:49573.17-49573.131" + wire width 4 $or$libresoc.v:49573$3031_Y + attribute \src "libresoc.v:49574.18-49574.126" + wire width 4 $or$libresoc.v:49574$3032_Y + attribute \src "libresoc.v:49575.18-49575.97" + wire width 4 $or$libresoc.v:49575$3033_Y + attribute \src "libresoc.v:49576.18-49576.126" + wire width 4 $or$libresoc.v:49576$3034_Y + attribute \src "libresoc.v:49577.18-49577.126" + wire width 4 $or$libresoc.v:49577$3035_Y + attribute \src "libresoc.v:49578.18-49578.97" + wire width 4 $or$libresoc.v:49578$3036_Y + attribute \src "libresoc.v:49579.18-49579.97" + wire width 4 $or$libresoc.v:49579$3037_Y + attribute \src "libresoc.v:49581.18-49581.126" + wire width 4 $or$libresoc.v:49581$3039_Y + attribute \src "libresoc.v:49582.18-49582.126" + wire width 4 $or$libresoc.v:49582$3040_Y + attribute \src "libresoc.v:49583.18-49583.97" + wire width 4 $or$libresoc.v:49583$3041_Y + attribute \src "libresoc.v:49584.17-49584.131" + wire width 4 $or$libresoc.v:49584$3042_Y + attribute \src "libresoc.v:49585.18-49585.126" + wire width 4 $or$libresoc.v:49585$3043_Y + attribute \src "libresoc.v:49586.18-49586.126" + wire width 4 $or$libresoc.v:49586$3044_Y + attribute \src "libresoc.v:49587.18-49587.97" + wire width 4 $or$libresoc.v:49587$3045_Y + attribute \src "libresoc.v:49588.18-49588.97" + wire width 4 $or$libresoc.v:49588$3046_Y + attribute \src "libresoc.v:49589.17-49589.94" + wire width 4 $or$libresoc.v:49589$3047_Y + attribute \src "libresoc.v:49562.18-49562.100" + wire $reduce_or$libresoc.v:49562$3020_Y + attribute \src "libresoc.v:49563.17-49563.95" + wire $reduce_or$libresoc.v:49563$3021_Y + attribute \src "libresoc.v:49571.18-49571.100" + wire $reduce_or$libresoc.v:49571$3029_Y + attribute \src "libresoc.v:49580.18-49580.100" + wire $reduce_or$libresoc.v:49580$3038_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85935,18 +85963,38 @@ module \cr wire width 4 \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + wire width 4 \$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + wire width 4 \$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \cr_pred__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 \data_i$52 + wire width 4 \data_i$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 3 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -85962,6 +86010,10 @@ module \cr attribute \src "libresoc.v:49146.7-49146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_0_cr_pred0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_cr_pred0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen @@ -85994,6 +86046,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_1_cr_pred1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_cr_pred1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen @@ -86026,6 +86082,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_2_cr_pred2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_cr_pred2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen @@ -86058,6 +86118,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_3_cr_pred3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_3_cr_pred3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest13__wen @@ -86090,6 +86154,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_w3__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_4_cr_pred4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_4_cr_pred4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest14__wen @@ -86122,6 +86190,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_w4__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_cr_pred5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_cr_pred5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest15__wen @@ -86154,6 +86226,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_w5__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_cr_pred6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_cr_pred6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest16__wen @@ -86186,6 +86262,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_w6__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_cr_pred7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_cr_pred7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest17__wen @@ -86228,6 +86308,10 @@ module \cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 6 \src1__data_o @@ -86244,31 +86328,31 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 15 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 8 \wen$51 + wire width 8 \wen$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49502$3016 + cell $or $or$libresoc.v:49558$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49502$3016_Y + connect \A \reg_4_cr_pred4__data_o + connect \B \reg_5_cr_pred5__data_o + connect \Y $or$libresoc.v:49558$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49503$3017 + cell $or $or$libresoc.v:49559$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49503$3017_Y + connect \A \reg_6_cr_pred6__data_o + connect \B \reg_7_cr_pred7__data_o + connect \Y $or$libresoc.v:49559$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49504$3018 + cell $or $or$libresoc.v:49560$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86276,10 +86360,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49504$3018_Y + connect \Y $or$libresoc.v:49560$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49505$3019 + cell $or $or$libresoc.v:49561$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86287,32 +86371,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49505$3019_Y + connect \Y $or$libresoc.v:49561$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49508$3022 + cell $or $or$libresoc.v:49564$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49508$3022_Y + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$libresoc.v:49564$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49509$3023 + cell $or $or$libresoc.v:49565$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49509$3023_Y + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:49565$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49510$3024 + cell $or $or$libresoc.v:49566$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86320,32 +86404,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49510$3024_Y + connect \Y $or$libresoc.v:49566$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49511$3025 + cell $or $or$libresoc.v:49567$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49511$3025_Y + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$libresoc.v:49567$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49512$3026 + cell $or $or$libresoc.v:49568$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49512$3026_Y + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$libresoc.v:49568$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49513$3027 + cell $or $or$libresoc.v:49569$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86353,10 +86437,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49513$3027_Y + connect \Y $or$libresoc.v:49569$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49514$3028 + cell $or $or$libresoc.v:49570$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86364,43 +86448,43 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49514$3028_Y + connect \Y $or$libresoc.v:49570$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49516$3030 + cell $or $or$libresoc.v:49572$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49516$3030_Y + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$libresoc.v:49572$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49517$3031 + cell $or $or$libresoc.v:49573$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49517$3031_Y + connect \A \reg_0_cr_pred0__data_o + connect \B \reg_1_cr_pred1__data_o + connect \Y $or$libresoc.v:49573$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49518$3032 + cell $or $or$libresoc.v:49574$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49518$3032_Y + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$libresoc.v:49574$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49519$3033 + cell $or $or$libresoc.v:49575$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86408,32 +86492,32 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49519$3033_Y + connect \Y $or$libresoc.v:49575$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49520$3034 + cell $or $or$libresoc.v:49576$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49520$3034_Y + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$libresoc.v:49576$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49521$3035 + cell $or $or$libresoc.v:49577$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49521$3035_Y + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$libresoc.v:49577$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49522$3036 + cell $or $or$libresoc.v:49578$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86441,10 +86525,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49522$3036_Y + connect \Y $or$libresoc.v:49578$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49523$3037 + cell $or $or$libresoc.v:49579$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86452,21 +86536,98 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49523$3037_Y + connect \Y $or$libresoc.v:49579$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49524$3038 + cell $or $or$libresoc.v:49581$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49524$3038_Y + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$libresoc.v:49581$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49582$3040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:49582$3040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49583$3041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$54 + connect \B \$56 + connect \Y $or$libresoc.v:49583$3041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49584$3042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_cr_pred2__data_o + connect \B \reg_3_cr_pred3__data_o + connect \Y $or$libresoc.v:49584$3042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49585$3043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:49585$3043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49586$3044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:49586$3044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49587$3045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$60 + connect \B \$62 + connect \Y $or$libresoc.v:49587$3045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49588$3046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$58 + connect \B \$64 + connect \Y $or$libresoc.v:49588$3046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49525$3039 + cell $or $or$libresoc.v:49589$3047 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86474,37 +86635,47 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49525$3039_Y + connect \Y $or$libresoc.v:49589$3047_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49506$3020 + cell $reduce_or $reduce_or$libresoc.v:49562$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49506$3020_Y + connect \Y $reduce_or$libresoc.v:49562$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49507$3021 + cell $reduce_or $reduce_or$libresoc.v:49563$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49507$3021_Y + connect \Y $reduce_or$libresoc.v:49563$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49515$3029 + cell $reduce_or $reduce_or$libresoc.v:49571$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49515$3029_Y + connect \Y $reduce_or$libresoc.v:49571$3029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49580$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$51 + connect \Y $reduce_or$libresoc.v:49580$3038_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49532.9-49551.4" + attribute \src "libresoc.v:49598.9-49619.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred0__data_o \reg_0_cr_pred0__data_o + connect \cr_pred0__ren \reg_0_cr_pred0__ren connect \dest10__data_i \reg_0_dest10__data_i connect \dest10__wen \reg_0_dest10__wen connect \dest20__data_i \reg_0_dest20__data_i @@ -86523,10 +86694,12 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49552.9-49571.4" + attribute \src "libresoc.v:49620.9-49641.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred1__data_o \reg_1_cr_pred1__data_o + connect \cr_pred1__ren \reg_1_cr_pred1__ren connect \dest11__data_i \reg_1_dest11__data_i connect \dest11__wen \reg_1_dest11__wen connect \dest21__data_i \reg_1_dest21__data_i @@ -86545,10 +86718,12 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49572.9-49591.4" + attribute \src "libresoc.v:49642.9-49663.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred2__data_o \reg_2_cr_pred2__data_o + connect \cr_pred2__ren \reg_2_cr_pred2__ren connect \dest12__data_i \reg_2_dest12__data_i connect \dest12__wen \reg_2_dest12__wen connect \dest22__data_i \reg_2_dest22__data_i @@ -86567,10 +86742,12 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49592.9-49611.4" + attribute \src "libresoc.v:49664.9-49685.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred3__data_o \reg_3_cr_pred3__data_o + connect \cr_pred3__ren \reg_3_cr_pred3__ren connect \dest13__data_i \reg_3_dest13__data_i connect \dest13__wen \reg_3_dest13__wen connect \dest23__data_i \reg_3_dest23__data_i @@ -86589,10 +86766,12 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49612.9-49631.4" + attribute \src "libresoc.v:49686.9-49707.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred4__data_o \reg_4_cr_pred4__data_o + connect \cr_pred4__ren \reg_4_cr_pred4__ren connect \dest14__data_i \reg_4_dest14__data_i connect \dest14__wen \reg_4_dest14__wen connect \dest24__data_i \reg_4_dest24__data_i @@ -86611,10 +86790,12 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49632.9-49651.4" + attribute \src "libresoc.v:49708.9-49729.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred5__data_o \reg_5_cr_pred5__data_o + connect \cr_pred5__ren \reg_5_cr_pred5__ren connect \dest15__data_i \reg_5_dest15__data_i connect \dest15__wen \reg_5_dest15__wen connect \dest25__data_i \reg_5_dest25__data_i @@ -86633,10 +86814,12 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49652.9-49671.4" + attribute \src "libresoc.v:49730.9-49751.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred6__data_o \reg_6_cr_pred6__data_o + connect \cr_pred6__ren \reg_6_cr_pred6__ren connect \dest16__data_i \reg_6_dest16__data_i connect \dest16__wen \reg_6_dest16__wen connect \dest26__data_i \reg_6_dest26__data_i @@ -86655,10 +86838,12 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49672.9-49691.4" + attribute \src "libresoc.v:49752.9-49773.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst + connect \cr_pred7__data_o \reg_7_cr_pred7__data_o + connect \cr_pred7__ren \reg_7_cr_pred7__ren connect \dest17__data_i \reg_7_dest17__data_i connect \dest17__wen \reg_7_dest17__wen connect \dest27__data_i \reg_7_dest27__data_i @@ -86677,66 +86862,81 @@ module \cr connect \w7__wen \reg_7_w7__wen end attribute \src "libresoc.v:49146.7-49146.20" - process $proc$libresoc.v:49146$3057 + process $proc$libresoc.v:49146$3071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49472.13-49472.30" - process $proc$libresoc.v:49472$3058 + attribute \src "libresoc.v:49524.13-49524.30" + process $proc$libresoc.v:49524$3072 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49474.13-49474.35" - process $proc$libresoc.v:49474$3059 + attribute \src "libresoc.v:49526.13-49526.35" + process $proc$libresoc.v:49526$3073 assign { } { } - assign $0\ren_delay$17[7:0]$3060 8'00000000 + assign $0\ren_delay$17[7:0]$3074 8'00000000 sync always sync init - update \ren_delay$17 $0\ren_delay$17[7:0]$3060 + update \ren_delay$17 $0\ren_delay$17[7:0]$3074 end - attribute \src "libresoc.v:49478.13-49478.35" - process $proc$libresoc.v:49478$3061 + attribute \src "libresoc.v:49530.13-49530.35" + process $proc$libresoc.v:49530$3075 assign { } { } - assign $0\ren_delay$34[7:0]$3062 8'00000000 + assign $0\ren_delay$34[7:0]$3076 8'00000000 sync always sync init - update \ren_delay$34 $0\ren_delay$34[7:0]$3062 + update \ren_delay$34 $0\ren_delay$34[7:0]$3076 end - attribute \src "libresoc.v:49526.3-49527.43" - process $proc$libresoc.v:49526$3040 + attribute \src "libresoc.v:49534.13-49534.35" + process $proc$libresoc.v:49534$3077 assign { } { } - assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next + assign $0\ren_delay$51[7:0]$3078 8'00000000 + sync always + sync init + update \ren_delay$51 $0\ren_delay$51[7:0]$3078 + end + attribute \src "libresoc.v:49590.3-49591.43" + process $proc$libresoc.v:49590$3048 + assign { } { } + assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next + sync posedge \coresync_clk + update \ren_delay$51 $0\ren_delay$51[7:0]$3049 + end + attribute \src "libresoc.v:49592.3-49593.43" + process $proc$libresoc.v:49592$3050 + assign { } { } + assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next sync posedge \coresync_clk - update \ren_delay$34 $0\ren_delay$34[7:0]$3041 + update \ren_delay$34 $0\ren_delay$34[7:0]$3051 end - attribute \src "libresoc.v:49528.3-49529.43" - process $proc$libresoc.v:49528$3042 + attribute \src "libresoc.v:49594.3-49595.43" + process $proc$libresoc.v:49594$3052 assign { } { } - assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next + assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$3043 + update \ren_delay$17 $0\ren_delay$17[7:0]$3053 end - attribute \src "libresoc.v:49530.3-49531.35" - process $proc$libresoc.v:49530$3044 + attribute \src "libresoc.v:49596.3-49597.35" + process $proc$libresoc.v:49596$3054 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49692.3-49700.6" - process $proc$libresoc.v:49692$3045 + attribute \src "libresoc.v:49774.3-49782.6" + process $proc$libresoc.v:49774$3055 assign { } { } assign { } { } - assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49693.5-49693.29" + assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057 + attribute \src "libresoc.v:49775.5-49775.29" switch \initial - attribute \src "libresoc.v:49693.9-49693.17" + attribute \src "libresoc.v:49775.9-49775.17" case 1'1 case end @@ -86745,21 +86945,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$17$next[7:0]$3047 8'00000000 + assign $1\ren_delay$17$next[7:0]$3057 8'00000000 case - assign $1\ren_delay$17$next[7:0]$3047 \src2__ren + assign $1\ren_delay$17$next[7:0]$3057 \src1__ren end sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056 end - attribute \src "libresoc.v:49701.3-49710.6" - process $proc$libresoc.v:49701$3048 + attribute \src "libresoc.v:49783.3-49792.6" + process $proc$libresoc.v:49783$3058 assign { } { } assign { } { } - assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49702.5-49702.29" + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49784.5-49784.29" switch \initial - attribute \src "libresoc.v:49702.9-49702.17" + attribute \src "libresoc.v:49784.9-49784.17" case 1'1 case end @@ -86768,21 +86968,67 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src2__data_o[3:0] \$32 + assign $1\src1__data_o[3:0] \$32 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + attribute \src "libresoc.v:49793.3-49801.6" + process $proc$libresoc.v:49793$3059 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061 + attribute \src "libresoc.v:49794.5-49794.29" + switch \initial + attribute \src "libresoc.v:49794.9-49794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3061 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3061 \src2__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060 + end + attribute \src "libresoc.v:49802.3-49811.6" + process $proc$libresoc.v:49802$3062 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:49803.5-49803.29" + switch \initial + attribute \src "libresoc.v:49803.9-49803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$49 case assign $1\src2__data_o[3:0] 4'0000 end sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49711.3-49719.6" - process $proc$libresoc.v:49711$3049 + attribute \src "libresoc.v:49812.3-49820.6" + process $proc$libresoc.v:49812$3063 assign { } { } assign { } { } - assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49712.5-49712.29" + assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065 + attribute \src "libresoc.v:49813.5-49813.29" switch \initial - attribute \src "libresoc.v:49712.9-49712.17" + attribute \src "libresoc.v:49813.9-49813.17" case 1'1 case end @@ -86791,44 +87037,44 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$34$next[7:0]$3051 8'00000000 + assign $1\ren_delay$51$next[7:0]$3065 8'00000000 case - assign $1\ren_delay$34$next[7:0]$3051 \src3__ren + assign $1\ren_delay$51$next[7:0]$3065 \src3__ren end sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 + update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064 end - attribute \src "libresoc.v:49720.3-49729.6" - process $proc$libresoc.v:49720$3052 + attribute \src "libresoc.v:49821.3-49830.6" + process $proc$libresoc.v:49821$3066 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49721.5-49721.29" + attribute \src "libresoc.v:49822.5-49822.29" switch \initial - attribute \src "libresoc.v:49721.9-49721.17" + attribute \src "libresoc.v:49822.9-49822.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$35 + switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src3__data_o[3:0] \$49 + assign $1\src3__data_o[3:0] \$66 case assign $1\src3__data_o[3:0] 4'0000 end sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49730.3-49738.6" - process $proc$libresoc.v:49730$3053 + attribute \src "libresoc.v:49831.3-49839.6" + process $proc$libresoc.v:49831$3067 assign { } { } assign { } { } - assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49731.5-49731.29" + assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069 + attribute \src "libresoc.v:49832.5-49832.29" switch \initial - attribute \src "libresoc.v:49731.9-49731.17" + attribute \src "libresoc.v:49832.9-49832.17" case 1'1 case end @@ -86837,21 +87083,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[7:0]$3055 8'00000000 + assign $1\ren_delay$next[7:0]$3069 8'00000000 case - assign $1\ren_delay$next[7:0]$3055 \src1__ren + assign $1\ren_delay$next[7:0]$3069 \cr_pred__ren end sync always - update \ren_delay$next $0\ren_delay$next[7:0]$3054 + update \ren_delay$next $0\ren_delay$next[7:0]$3068 end - attribute \src "libresoc.v:49739.3-49748.6" - process $proc$libresoc.v:49739$3056 + attribute \src "libresoc.v:49840.3-49849.6" + process $proc$libresoc.v:49840$3070 assign { } { } assign { } { } - assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49740.5-49740.29" + assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0] + attribute \src "libresoc.v:49841.5-49841.29" switch \initial - attribute \src "libresoc.v:49740.9-49740.17" + attribute \src "libresoc.v:49841.9-49841.17" case 1'1 case end @@ -86860,39 +87106,48 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src1__data_o[3:0] \$15 - case - assign $1\src1__data_o[3:0] 4'0000 - end - sync always - update \src1__data_o $0\src1__data_o[3:0] - end - connect \$9 $or$libresoc.v:49502$3016_Y - connect \$11 $or$libresoc.v:49503$3017_Y - connect \$13 $or$libresoc.v:49504$3018_Y - connect \$15 $or$libresoc.v:49505$3019_Y - connect \$18 $reduce_or$libresoc.v:49506$3020_Y - connect \$1 $reduce_or$libresoc.v:49507$3021_Y - connect \$20 $or$libresoc.v:49508$3022_Y - connect \$22 $or$libresoc.v:49509$3023_Y - connect \$24 $or$libresoc.v:49510$3024_Y - connect \$26 $or$libresoc.v:49511$3025_Y - connect \$28 $or$libresoc.v:49512$3026_Y - connect \$30 $or$libresoc.v:49513$3027_Y - connect \$32 $or$libresoc.v:49514$3028_Y - connect \$35 $reduce_or$libresoc.v:49515$3029_Y - connect \$37 $or$libresoc.v:49516$3030_Y - connect \$3 $or$libresoc.v:49517$3031_Y - connect \$39 $or$libresoc.v:49518$3032_Y - connect \$41 $or$libresoc.v:49519$3033_Y - connect \$43 $or$libresoc.v:49520$3034_Y - connect \$45 $or$libresoc.v:49521$3035_Y - connect \$47 $or$libresoc.v:49522$3036_Y - connect \$49 $or$libresoc.v:49523$3037_Y - connect \$5 $or$libresoc.v:49524$3038_Y - connect \$7 $or$libresoc.v:49525$3039_Y - connect \wen$51 8'00000000 - connect \data_i$52 4'0000 + assign $1\cr_pred__data_o[3:0] \$15 + case + assign $1\cr_pred__data_o[3:0] 4'0000 + end + sync always + update \cr_pred__data_o $0\cr_pred__data_o[3:0] + end + connect \$9 $or$libresoc.v:49558$3016_Y + connect \$11 $or$libresoc.v:49559$3017_Y + connect \$13 $or$libresoc.v:49560$3018_Y + connect \$15 $or$libresoc.v:49561$3019_Y + connect \$18 $reduce_or$libresoc.v:49562$3020_Y + connect \$1 $reduce_or$libresoc.v:49563$3021_Y + connect \$20 $or$libresoc.v:49564$3022_Y + connect \$22 $or$libresoc.v:49565$3023_Y + connect \$24 $or$libresoc.v:49566$3024_Y + connect \$26 $or$libresoc.v:49567$3025_Y + connect \$28 $or$libresoc.v:49568$3026_Y + connect \$30 $or$libresoc.v:49569$3027_Y + connect \$32 $or$libresoc.v:49570$3028_Y + connect \$35 $reduce_or$libresoc.v:49571$3029_Y + connect \$37 $or$libresoc.v:49572$3030_Y + connect \$3 $or$libresoc.v:49573$3031_Y + connect \$39 $or$libresoc.v:49574$3032_Y + connect \$41 $or$libresoc.v:49575$3033_Y + connect \$43 $or$libresoc.v:49576$3034_Y + connect \$45 $or$libresoc.v:49577$3035_Y + connect \$47 $or$libresoc.v:49578$3036_Y + connect \$49 $or$libresoc.v:49579$3037_Y + connect \$52 $reduce_or$libresoc.v:49580$3038_Y + connect \$54 $or$libresoc.v:49581$3039_Y + connect \$56 $or$libresoc.v:49582$3040_Y + connect \$58 $or$libresoc.v:49583$3041_Y + connect \$5 $or$libresoc.v:49584$3042_Y + connect \$60 $or$libresoc.v:49585$3043_Y + connect \$62 $or$libresoc.v:49586$3044_Y + connect \$64 $or$libresoc.v:49587$3045_Y + connect \$66 $or$libresoc.v:49588$3046_Y + connect \$7 $or$libresoc.v:49589$3047_Y + connect \cr_pred__ren 8'00000000 + connect \wen$68 8'00000000 + connect \data_i$69 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren @@ -86920,394 +87175,395 @@ module \cr connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000 end -attribute \src "libresoc.v:49782.1-50839.10" +attribute \src "libresoc.v:49885.1-50942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50440.3-50441.25" + attribute \src "libresoc.v:50543.3-50544.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 - attribute \src "libresoc.v:50412.3-50413.61" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + attribute \src "libresoc.v:50515.3-50516.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:50414.3-50415.55" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199 + attribute \src "libresoc.v:50517.3-50518.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:50410.3-50411.65" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 + attribute \src "libresoc.v:50513.3-50514.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50438.3-50439.39" + attribute \src "libresoc.v:50541.3-50542.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50760.3-50768.6" - wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:50382.3-50383.39" + attribute \src "libresoc.v:50863.3-50871.6" + wire $0\alu_l_r_alu$next[0:0]$3250 + attribute \src "libresoc.v:50485.3-50486.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50751.3-50759.6" - wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:50384.3-50385.43" + attribute \src "libresoc.v:50854.3-50862.6" + wire $0\alui_l_r_alui$next[0:0]$3247 + attribute \src "libresoc.v:50487.3-50488.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:50406.3-50407.37" + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $0\data_r0__o$next[63:0]$3205 + attribute \src "libresoc.v:50509.3-50510.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:50408.3-50409.43" + attribute \src "libresoc.v:50728.3-50749.6" + wire $0\data_r0__o_ok$next[0:0]$3206 + attribute \src "libresoc.v:50511.3-50512.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:50402.3-50403.49" + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3213 + attribute \src "libresoc.v:50505.3-50506.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:50404.3-50405.55" + attribute \src "libresoc.v:50750.3-50771.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3214 + attribute \src "libresoc.v:50507.3-50508.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:50398.3-50399.43" + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3221 + attribute \src "libresoc.v:50501.3-50502.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:50400.3-50401.49" + attribute \src "libresoc.v:50772.3-50793.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3222 + attribute \src "libresoc.v:50503.3-50504.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50872.3-50881.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50779.3-50788.6" + attribute \src "libresoc.v:50882.3-50891.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50789.3-50798.6" + attribute \src "libresoc.v:50892.3-50901.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49783.7-49783.20" + attribute \src "libresoc.v:49886.7-49886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50568.3-50576.6" - wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:50424.3-50425.39" + attribute \src "libresoc.v:50671.3-50679.6" + wire $0\opc_l_r_opc$next[0:0]$3183 + attribute \src "libresoc.v:50527.3-50528.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50559.3-50567.6" - wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:50426.3-50427.39" + attribute \src "libresoc.v:50662.3-50670.6" + wire $0\opc_l_s_opc$next[0:0]$3180 + attribute \src "libresoc.v:50529.3-50530.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50799.3-50807.6" - wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:50436.3-50437.37" + attribute \src "libresoc.v:50902.3-50910.6" + wire width 3 $0\prev_wr_go$next[2:0]$3256 + attribute \src "libresoc.v:50539.3-50540.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50513.3-50522.6" + attribute \src "libresoc.v:50616.3-50625.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50604.3-50612.6" - wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:50416.3-50417.39" + attribute \src "libresoc.v:50707.3-50715.6" + wire width 3 $0\req_l_r_req$next[2:0]$3195 + attribute \src "libresoc.v:50519.3-50520.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50595.3-50603.6" - wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:50418.3-50419.39" + attribute \src "libresoc.v:50698.3-50706.6" + wire width 3 $0\req_l_s_req$next[2:0]$3192 + attribute \src "libresoc.v:50521.3-50522.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50532.3-50540.6" - wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:50432.3-50433.41" + attribute \src "libresoc.v:50635.3-50643.6" + wire $0\rok_l_r_rdok$next[0:0]$3171 + attribute \src "libresoc.v:50535.3-50536.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50523.3-50531.6" - wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:50434.3-50435.41" + attribute \src "libresoc.v:50626.3-50634.6" + wire $0\rok_l_s_rdok$next[0:0]$3168 + attribute \src "libresoc.v:50537.3-50538.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50550.3-50558.6" - wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:50428.3-50429.39" + attribute \src "libresoc.v:50653.3-50661.6" + wire $0\rst_l_r_rst$next[0:0]$3177 + attribute \src "libresoc.v:50531.3-50532.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50541.3-50549.6" - wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:50430.3-50431.39" + attribute \src "libresoc.v:50644.3-50652.6" + wire $0\rst_l_s_rst$next[0:0]$3174 + attribute \src "libresoc.v:50533.3-50534.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50586.3-50594.6" - wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:50420.3-50421.39" + attribute \src "libresoc.v:50689.3-50697.6" + wire width 6 $0\src_l_r_src$next[5:0]$3189 + attribute \src "libresoc.v:50523.3-50524.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50577.3-50585.6" - wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:50422.3-50423.39" + attribute \src "libresoc.v:50680.3-50688.6" + wire width 6 $0\src_l_s_src$next[5:0]$3186 + attribute \src "libresoc.v:50525.3-50526.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50691.3-50700.6" - wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:50396.3-50397.29" + attribute \src "libresoc.v:50794.3-50803.6" + wire width 64 $0\src_r0$next[63:0]$3229 + attribute \src "libresoc.v:50499.3-50500.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50701.3-50710.6" - wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:50394.3-50395.29" + attribute \src "libresoc.v:50804.3-50813.6" + wire width 64 $0\src_r1$next[63:0]$3232 + attribute \src "libresoc.v:50497.3-50498.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50711.3-50720.6" - wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:50392.3-50393.29" + attribute \src "libresoc.v:50814.3-50823.6" + wire width 32 $0\src_r2$next[31:0]$3235 + attribute \src "libresoc.v:50495.3-50496.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50721.3-50730.6" - wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:50390.3-50391.29" + attribute \src "libresoc.v:50824.3-50833.6" + wire width 4 $0\src_r3$next[3:0]$3238 + attribute \src "libresoc.v:50493.3-50494.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50731.3-50740.6" - wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:50388.3-50389.29" + attribute \src "libresoc.v:50834.3-50843.6" + wire width 4 $0\src_r4$next[3:0]$3241 + attribute \src "libresoc.v:50491.3-50492.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50741.3-50750.6" - wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:50386.3-50387.29" + attribute \src "libresoc.v:50844.3-50853.6" + wire width 4 $0\src_r5$next[3:0]$3244 + attribute \src "libresoc.v:50489.3-50490.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49901.7-49901.24" + attribute \src "libresoc.v:50004.7-50004.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 - attribute \src "libresoc.v:49932.14-49932.47" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + attribute \src "libresoc.v:50035.14-50035.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49936.14-49936.41" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + attribute \src "libresoc.v:50039.14-50039.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50613.3-50624.6" - wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50015.13-50015.45" + attribute \src "libresoc.v:50716.3-50727.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50118.13-50118.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50039.7-50039.26" + attribute \src "libresoc.v:50142.7-50142.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50760.3-50768.6" - wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50047.7-50047.25" + attribute \src "libresoc.v:50863.3-50871.6" + wire $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50150.7-50150.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50751.3-50759.6" - wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50059.7-50059.27" + attribute \src "libresoc.v:50854.3-50862.6" + wire $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50162.7-50162.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:50093.14-50093.47" + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $1\data_r0__o$next[63:0]$3207 + attribute \src "libresoc.v:50196.14-50196.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:50097.7-50097.27" + attribute \src "libresoc.v:50728.3-50749.6" + wire $1\data_r0__o_ok$next[0:0]$3208 + attribute \src "libresoc.v:50200.7-50200.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:50101.14-50101.38" + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3215 + attribute \src "libresoc.v:50204.14-50204.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50647.3-50668.6" - wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:50105.7-50105.33" + attribute \src "libresoc.v:50750.3-50771.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3216 + attribute \src "libresoc.v:50208.7-50208.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:50109.13-50109.33" + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3223 + attribute \src "libresoc.v:50212.13-50212.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50669.3-50690.6" - wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:50113.7-50113.30" + attribute \src "libresoc.v:50772.3-50793.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3224 + attribute \src "libresoc.v:50216.7-50216.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50769.3-50778.6" + attribute \src "libresoc.v:50872.3-50881.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50779.3-50788.6" + attribute \src "libresoc.v:50882.3-50891.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50789.3-50798.6" + attribute \src "libresoc.v:50892.3-50901.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50568.3-50576.6" - wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50132.7-50132.25" + attribute \src "libresoc.v:50671.3-50679.6" + wire $1\opc_l_r_opc$next[0:0]$3184 + attribute \src "libresoc.v:50235.7-50235.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50559.3-50567.6" - wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50136.7-50136.25" + attribute \src "libresoc.v:50662.3-50670.6" + wire $1\opc_l_s_opc$next[0:0]$3181 + attribute \src "libresoc.v:50239.7-50239.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50799.3-50807.6" - wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50236.13-50236.30" + attribute \src "libresoc.v:50902.3-50910.6" + wire width 3 $1\prev_wr_go$next[2:0]$3257 + attribute \src "libresoc.v:50339.13-50339.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50513.3-50522.6" + attribute \src "libresoc.v:50616.3-50625.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50604.3-50612.6" - wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50244.13-50244.31" + attribute \src "libresoc.v:50707.3-50715.6" + wire width 3 $1\req_l_r_req$next[2:0]$3196 + attribute \src "libresoc.v:50347.13-50347.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50595.3-50603.6" - wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50248.13-50248.31" + attribute \src "libresoc.v:50698.3-50706.6" + wire width 3 $1\req_l_s_req$next[2:0]$3193 + attribute \src "libresoc.v:50351.13-50351.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50532.3-50540.6" - wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50260.7-50260.26" + attribute \src "libresoc.v:50635.3-50643.6" + wire $1\rok_l_r_rdok$next[0:0]$3172 + attribute \src "libresoc.v:50363.7-50363.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50523.3-50531.6" - wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50264.7-50264.26" + attribute \src "libresoc.v:50626.3-50634.6" + wire $1\rok_l_s_rdok$next[0:0]$3169 + attribute \src "libresoc.v:50367.7-50367.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50550.3-50558.6" - wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50268.7-50268.25" + attribute \src "libresoc.v:50653.3-50661.6" + wire $1\rst_l_r_rst$next[0:0]$3178 + attribute \src "libresoc.v:50371.7-50371.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50541.3-50549.6" - wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50272.7-50272.25" + attribute \src "libresoc.v:50644.3-50652.6" + wire $1\rst_l_s_rst$next[0:0]$3175 + attribute \src "libresoc.v:50375.7-50375.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50586.3-50594.6" - wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50292.13-50292.32" + attribute \src "libresoc.v:50689.3-50697.6" + wire width 6 $1\src_l_r_src$next[5:0]$3190 + attribute \src "libresoc.v:50395.13-50395.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50577.3-50585.6" - wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50296.13-50296.32" + attribute \src "libresoc.v:50680.3-50688.6" + wire width 6 $1\src_l_s_src$next[5:0]$3187 + attribute \src "libresoc.v:50399.13-50399.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50691.3-50700.6" - wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50300.14-50300.43" + attribute \src "libresoc.v:50794.3-50803.6" + wire width 64 $1\src_r0$next[63:0]$3230 + attribute \src "libresoc.v:50403.14-50403.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50701.3-50710.6" - wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50304.14-50304.43" + attribute \src "libresoc.v:50804.3-50813.6" + wire width 64 $1\src_r1$next[63:0]$3233 + attribute \src "libresoc.v:50407.14-50407.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50711.3-50720.6" - wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50308.14-50308.28" + attribute \src "libresoc.v:50814.3-50823.6" + wire width 32 $1\src_r2$next[31:0]$3236 + attribute \src "libresoc.v:50411.14-50411.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50721.3-50730.6" - wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50312.13-50312.26" + attribute \src "libresoc.v:50824.3-50833.6" + wire width 4 $1\src_r3$next[3:0]$3239 + attribute \src "libresoc.v:50415.13-50415.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50731.3-50740.6" - wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50316.13-50316.26" + attribute \src "libresoc.v:50834.3-50843.6" + wire width 4 $1\src_r4$next[3:0]$3242 + attribute \src "libresoc.v:50419.13-50419.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50741.3-50750.6" - wire width 4 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50320.13-50320.26" + attribute \src "libresoc.v:50844.3-50853.6" + wire width 4 $1\src_r5$next[3:0]$3245 + attribute \src "libresoc.v:50423.13-50423.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50625.3-50646.6" - wire width 64 $2\data_r0__o$next[63:0]$3193 - attribute \src "libresoc.v:50625.3-50646.6" - wire $2\data_r0__o_ok$next[0:0]$3194 - attribute \src "libresoc.v:50647.3-50668.6" - wire width 32 $2\data_r1__full_cr$next[31:0]$3201 - attribute \src "libresoc.v:50647.3-50668.6" - wire $2\data_r1__full_cr_ok$next[0:0]$3202 - attribute \src "libresoc.v:50669.3-50690.6" - wire width 4 $2\data_r2__cr_a$next[3:0]$3209 - attribute \src "libresoc.v:50669.3-50690.6" - wire $2\data_r2__cr_a_ok$next[0:0]$3210 - attribute \src "libresoc.v:50625.3-50646.6" - wire $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50647.3-50668.6" - wire $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50669.3-50690.6" - wire $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50326.18-50326.112" - wire width 6 $and$libresoc.v:50326$3064_Y - attribute \src "libresoc.v:50327.19-50327.125" - wire $and$libresoc.v:50327$3065_Y - attribute \src "libresoc.v:50328.19-50328.125" - wire $and$libresoc.v:50328$3066_Y - attribute \src "libresoc.v:50329.19-50329.125" - wire $and$libresoc.v:50329$3067_Y - attribute \src "libresoc.v:50330.19-50330.141" - wire width 3 $and$libresoc.v:50330$3068_Y - attribute \src "libresoc.v:50331.19-50331.121" - wire width 3 $and$libresoc.v:50331$3069_Y - attribute \src "libresoc.v:50332.19-50332.127" - wire $and$libresoc.v:50332$3070_Y - attribute \src "libresoc.v:50333.19-50333.127" - wire $and$libresoc.v:50333$3071_Y - attribute \src "libresoc.v:50334.19-50334.127" - wire $and$libresoc.v:50334$3072_Y - attribute \src "libresoc.v:50335.18-50335.110" - wire $and$libresoc.v:50335$3073_Y - attribute \src "libresoc.v:50337.18-50337.98" - wire $and$libresoc.v:50337$3075_Y - attribute \src "libresoc.v:50339.18-50339.100" - wire $and$libresoc.v:50339$3077_Y - attribute \src "libresoc.v:50340.18-50340.149" - wire width 3 $and$libresoc.v:50340$3078_Y - attribute \src "libresoc.v:50342.18-50342.119" - wire width 3 $and$libresoc.v:50342$3080_Y - attribute \src "libresoc.v:50345.18-50345.116" - wire $and$libresoc.v:50345$3083_Y - attribute \src "libresoc.v:50349.17-50349.123" - wire $and$libresoc.v:50349$3087_Y - attribute \src "libresoc.v:50351.18-50351.113" - wire $and$libresoc.v:50351$3089_Y - attribute \src "libresoc.v:50352.18-50352.125" - wire width 3 $and$libresoc.v:50352$3090_Y - attribute \src "libresoc.v:50354.18-50354.112" - wire $and$libresoc.v:50354$3092_Y - attribute \src "libresoc.v:50356.18-50356.125" - wire $and$libresoc.v:50356$3094_Y - attribute \src "libresoc.v:50357.18-50357.125" - wire $and$libresoc.v:50357$3095_Y - attribute \src "libresoc.v:50358.18-50358.117" - wire $and$libresoc.v:50358$3096_Y - attribute \src "libresoc.v:50363.18-50363.129" - wire $and$libresoc.v:50363$3101_Y - attribute \src "libresoc.v:50364.18-50364.124" - wire width 3 $and$libresoc.v:50364$3102_Y - attribute \src "libresoc.v:50367.18-50367.116" - wire $and$libresoc.v:50367$3105_Y - attribute \src "libresoc.v:50368.18-50368.122" - wire $and$libresoc.v:50368$3106_Y - attribute \src "libresoc.v:50369.18-50369.119" - wire $and$libresoc.v:50369$3107_Y - attribute \src "libresoc.v:50377.18-50377.133" - wire $and$libresoc.v:50377$3115_Y - attribute \src "libresoc.v:50378.18-50378.131" - wire $and$libresoc.v:50378$3116_Y - attribute \src "libresoc.v:50379.18-50379.182" - wire width 6 $and$libresoc.v:50379$3117_Y - attribute \src "libresoc.v:50380.18-50380.113" - wire width 6 $and$libresoc.v:50380$3118_Y - attribute \src "libresoc.v:50353.18-50353.113" - wire $eq$libresoc.v:50353$3091_Y - attribute \src "libresoc.v:50355.18-50355.119" - wire $eq$libresoc.v:50355$3093_Y - attribute \src "libresoc.v:50336.18-50336.97" - wire $not$libresoc.v:50336$3074_Y - attribute \src "libresoc.v:50338.18-50338.99" - wire $not$libresoc.v:50338$3076_Y - attribute \src "libresoc.v:50341.18-50341.113" - wire width 3 $not$libresoc.v:50341$3079_Y - attribute \src "libresoc.v:50344.18-50344.106" - wire $not$libresoc.v:50344$3082_Y - attribute \src "libresoc.v:50350.18-50350.119" - wire $not$libresoc.v:50350$3088_Y - attribute \src "libresoc.v:50365.17-50365.113" - wire width 6 $not$libresoc.v:50365$3103_Y - attribute \src "libresoc.v:50381.18-50381.114" - wire width 6 $not$libresoc.v:50381$3119_Y - attribute \src "libresoc.v:50348.18-50348.112" - wire $or$libresoc.v:50348$3086_Y - attribute \src "libresoc.v:50359.18-50359.122" - wire $or$libresoc.v:50359$3097_Y - attribute \src "libresoc.v:50360.18-50360.124" - wire $or$libresoc.v:50360$3098_Y - attribute \src "libresoc.v:50361.18-50361.155" - wire width 3 $or$libresoc.v:50361$3099_Y - attribute \src "libresoc.v:50362.18-50362.194" - wire width 6 $or$libresoc.v:50362$3100_Y - attribute \src "libresoc.v:50366.18-50366.120" - wire width 3 $or$libresoc.v:50366$3104_Y - attribute \src "libresoc.v:50376.17-50376.117" - wire width 6 $or$libresoc.v:50376$3114_Y - attribute \src "libresoc.v:50325.17-50325.104" - wire $reduce_and$libresoc.v:50325$3063_Y - attribute \src "libresoc.v:50343.18-50343.106" - wire $reduce_or$libresoc.v:50343$3081_Y - attribute \src "libresoc.v:50346.18-50346.113" - wire $reduce_or$libresoc.v:50346$3084_Y - attribute \src "libresoc.v:50347.18-50347.112" - wire $reduce_or$libresoc.v:50347$3085_Y - attribute \src "libresoc.v:50370.18-50370.118" - wire width 64 $ternary$libresoc.v:50370$3108_Y - attribute \src "libresoc.v:50371.18-50371.118" - wire width 64 $ternary$libresoc.v:50371$3109_Y - attribute \src "libresoc.v:50372.18-50372.118" - wire width 32 $ternary$libresoc.v:50372$3110_Y - attribute \src "libresoc.v:50373.18-50373.118" - wire width 4 $ternary$libresoc.v:50373$3111_Y - attribute \src "libresoc.v:50374.18-50374.118" - wire width 4 $ternary$libresoc.v:50374$3112_Y - attribute \src "libresoc.v:50375.18-50375.118" - wire width 4 $ternary$libresoc.v:50375$3113_Y + attribute \src "libresoc.v:50728.3-50749.6" + wire width 64 $2\data_r0__o$next[63:0]$3209 + attribute \src "libresoc.v:50728.3-50749.6" + wire $2\data_r0__o_ok$next[0:0]$3210 + attribute \src "libresoc.v:50750.3-50771.6" + wire width 32 $2\data_r1__full_cr$next[31:0]$3217 + attribute \src "libresoc.v:50750.3-50771.6" + wire $2\data_r1__full_cr_ok$next[0:0]$3218 + attribute \src "libresoc.v:50772.3-50793.6" + wire width 4 $2\data_r2__cr_a$next[3:0]$3225 + attribute \src "libresoc.v:50772.3-50793.6" + wire $2\data_r2__cr_a_ok$next[0:0]$3226 + attribute \src "libresoc.v:50728.3-50749.6" + wire $3\data_r0__o_ok$next[0:0]$3211 + attribute \src "libresoc.v:50750.3-50771.6" + wire $3\data_r1__full_cr_ok$next[0:0]$3219 + attribute \src "libresoc.v:50772.3-50793.6" + wire $3\data_r2__cr_a_ok$next[0:0]$3227 + attribute \src "libresoc.v:50429.18-50429.112" + wire width 6 $and$libresoc.v:50429$3080_Y + attribute \src "libresoc.v:50430.19-50430.125" + wire $and$libresoc.v:50430$3081_Y + attribute \src "libresoc.v:50431.19-50431.125" + wire $and$libresoc.v:50431$3082_Y + attribute \src "libresoc.v:50432.19-50432.125" + wire $and$libresoc.v:50432$3083_Y + attribute \src "libresoc.v:50433.19-50433.141" + wire width 3 $and$libresoc.v:50433$3084_Y + attribute \src "libresoc.v:50434.19-50434.121" + wire width 3 $and$libresoc.v:50434$3085_Y + attribute \src "libresoc.v:50435.19-50435.127" + wire $and$libresoc.v:50435$3086_Y + attribute \src "libresoc.v:50436.19-50436.127" + wire $and$libresoc.v:50436$3087_Y + attribute \src "libresoc.v:50437.19-50437.127" + wire $and$libresoc.v:50437$3088_Y + attribute \src "libresoc.v:50438.18-50438.110" + wire $and$libresoc.v:50438$3089_Y + attribute \src "libresoc.v:50440.18-50440.98" + wire $and$libresoc.v:50440$3091_Y + attribute \src "libresoc.v:50442.18-50442.100" + wire $and$libresoc.v:50442$3093_Y + attribute \src "libresoc.v:50443.18-50443.149" + wire width 3 $and$libresoc.v:50443$3094_Y + attribute \src "libresoc.v:50445.18-50445.119" + wire width 3 $and$libresoc.v:50445$3096_Y + attribute \src "libresoc.v:50448.18-50448.116" + wire $and$libresoc.v:50448$3099_Y + attribute \src "libresoc.v:50452.17-50452.123" + wire $and$libresoc.v:50452$3103_Y + attribute \src "libresoc.v:50454.18-50454.113" + wire $and$libresoc.v:50454$3105_Y + attribute \src "libresoc.v:50455.18-50455.125" + wire width 3 $and$libresoc.v:50455$3106_Y + attribute \src "libresoc.v:50457.18-50457.112" + wire $and$libresoc.v:50457$3108_Y + attribute \src "libresoc.v:50459.18-50459.125" + wire $and$libresoc.v:50459$3110_Y + attribute \src "libresoc.v:50460.18-50460.125" + wire $and$libresoc.v:50460$3111_Y + attribute \src "libresoc.v:50461.18-50461.117" + wire $and$libresoc.v:50461$3112_Y + attribute \src "libresoc.v:50466.18-50466.129" + wire $and$libresoc.v:50466$3117_Y + attribute \src "libresoc.v:50467.18-50467.124" + wire width 3 $and$libresoc.v:50467$3118_Y + attribute \src "libresoc.v:50470.18-50470.116" + wire $and$libresoc.v:50470$3121_Y + attribute \src "libresoc.v:50471.18-50471.122" + wire $and$libresoc.v:50471$3122_Y + attribute \src "libresoc.v:50472.18-50472.119" + wire $and$libresoc.v:50472$3123_Y + attribute \src "libresoc.v:50480.18-50480.133" + wire $and$libresoc.v:50480$3131_Y + attribute \src "libresoc.v:50481.18-50481.131" + wire $and$libresoc.v:50481$3132_Y + attribute \src "libresoc.v:50482.18-50482.182" + wire width 6 $and$libresoc.v:50482$3133_Y + attribute \src "libresoc.v:50483.18-50483.113" + wire width 6 $and$libresoc.v:50483$3134_Y + attribute \src "libresoc.v:50456.18-50456.113" + wire $eq$libresoc.v:50456$3107_Y + attribute \src "libresoc.v:50458.18-50458.119" + wire $eq$libresoc.v:50458$3109_Y + attribute \src "libresoc.v:50439.18-50439.97" + wire $not$libresoc.v:50439$3090_Y + attribute \src "libresoc.v:50441.18-50441.99" + wire $not$libresoc.v:50441$3092_Y + attribute \src "libresoc.v:50444.18-50444.113" + wire width 3 $not$libresoc.v:50444$3095_Y + attribute \src "libresoc.v:50447.18-50447.106" + wire $not$libresoc.v:50447$3098_Y + attribute \src "libresoc.v:50453.18-50453.119" + wire $not$libresoc.v:50453$3104_Y + attribute \src "libresoc.v:50468.17-50468.113" + wire width 6 $not$libresoc.v:50468$3119_Y + attribute \src "libresoc.v:50484.18-50484.114" + wire width 6 $not$libresoc.v:50484$3135_Y + attribute \src "libresoc.v:50451.18-50451.112" + wire $or$libresoc.v:50451$3102_Y + attribute \src "libresoc.v:50462.18-50462.122" + wire $or$libresoc.v:50462$3113_Y + attribute \src "libresoc.v:50463.18-50463.124" + wire $or$libresoc.v:50463$3114_Y + attribute \src "libresoc.v:50464.18-50464.155" + wire width 3 $or$libresoc.v:50464$3115_Y + attribute \src "libresoc.v:50465.18-50465.194" + wire width 6 $or$libresoc.v:50465$3116_Y + attribute \src "libresoc.v:50469.18-50469.120" + wire width 3 $or$libresoc.v:50469$3120_Y + attribute \src "libresoc.v:50479.17-50479.117" + wire width 6 $or$libresoc.v:50479$3130_Y + attribute \src "libresoc.v:50428.17-50428.104" + wire $reduce_and$libresoc.v:50428$3079_Y + attribute \src "libresoc.v:50446.18-50446.106" + wire $reduce_or$libresoc.v:50446$3097_Y + attribute \src "libresoc.v:50449.18-50449.113" + wire $reduce_or$libresoc.v:50449$3100_Y + attribute \src "libresoc.v:50450.18-50450.112" + wire $reduce_or$libresoc.v:50450$3101_Y + attribute \src "libresoc.v:50473.18-50473.118" + wire width 64 $ternary$libresoc.v:50473$3124_Y + attribute \src "libresoc.v:50474.18-50474.118" + wire width 64 $ternary$libresoc.v:50474$3125_Y + attribute \src "libresoc.v:50475.18-50475.118" + wire width 32 $ternary$libresoc.v:50475$3126_Y + attribute \src "libresoc.v:50476.18-50476.118" + wire width 4 $ternary$libresoc.v:50476$3127_Y + attribute \src "libresoc.v:50477.18-50477.118" + wire width 4 $ternary$libresoc.v:50477$3128_Y + attribute \src "libresoc.v:50478.18-50478.118" + wire width 4 $ternary$libresoc.v:50478$3129_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87588,9 +87844,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87648,7 +87904,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49783.7-49783.15" + attribute \src "libresoc.v:49886.7-49886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok @@ -87849,7 +88105,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50326$3064 + cell $and $and$libresoc.v:50429$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87857,10 +88113,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50326$3064_Y + connect \Y $and$libresoc.v:50429$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50327$3065 + cell $and $and$libresoc.v:50430$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87868,10 +88124,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50327$3065_Y + connect \Y $and$libresoc.v:50430$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50328$3066 + cell $and $and$libresoc.v:50431$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87879,10 +88135,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50328$3066_Y + connect \Y $and$libresoc.v:50431$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50329$3067 + cell $and $and$libresoc.v:50432$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87890,10 +88146,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50329$3067_Y + connect \Y $and$libresoc.v:50432$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50330$3068 + cell $and $and$libresoc.v:50433$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87901,10 +88157,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50330$3068_Y + connect \Y $and$libresoc.v:50433$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50331$3069 + cell $and $and$libresoc.v:50434$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87912,10 +88168,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50331$3069_Y + connect \Y $and$libresoc.v:50434$3085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50332$3070 + cell $and $and$libresoc.v:50435$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87923,10 +88179,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50332$3070_Y + connect \Y $and$libresoc.v:50435$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50333$3071 + cell $and $and$libresoc.v:50436$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87934,10 +88190,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50333$3071_Y + connect \Y $and$libresoc.v:50436$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50334$3072 + cell $and $and$libresoc.v:50437$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87945,10 +88201,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50334$3072_Y + connect \Y $and$libresoc.v:50437$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50335$3073 + cell $and $and$libresoc.v:50438$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87956,10 +88212,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50335$3073_Y + connect \Y $and$libresoc.v:50438$3089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50337$3075 + cell $and $and$libresoc.v:50440$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87967,10 +88223,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50337$3075_Y + connect \Y $and$libresoc.v:50440$3091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50339$3077 + cell $and $and$libresoc.v:50442$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87978,10 +88234,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50339$3077_Y + connect \Y $and$libresoc.v:50442$3093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50340$3078 + cell $and $and$libresoc.v:50443$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87989,10 +88245,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50340$3078_Y + connect \Y $and$libresoc.v:50443$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50342$3080 + cell $and $and$libresoc.v:50445$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88000,10 +88256,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50342$3080_Y + connect \Y $and$libresoc.v:50445$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50345$3083 + cell $and $and$libresoc.v:50448$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88011,10 +88267,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50345$3083_Y + connect \Y $and$libresoc.v:50448$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50349$3087 + cell $and $and$libresoc.v:50452$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88022,10 +88278,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50349$3087_Y + connect \Y $and$libresoc.v:50452$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50351$3089 + cell $and $and$libresoc.v:50454$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88033,10 +88289,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50351$3089_Y + connect \Y $and$libresoc.v:50454$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50352$3090 + cell $and $and$libresoc.v:50455$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88044,10 +88300,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50352$3090_Y + connect \Y $and$libresoc.v:50455$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50354$3092 + cell $and $and$libresoc.v:50457$3108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88055,10 +88311,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50354$3092_Y + connect \Y $and$libresoc.v:50457$3108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50356$3094 + cell $and $and$libresoc.v:50459$3110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88066,10 +88322,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50356$3094_Y + connect \Y $and$libresoc.v:50459$3110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50357$3095 + cell $and $and$libresoc.v:50460$3111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88077,10 +88333,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50357$3095_Y + connect \Y $and$libresoc.v:50460$3111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50358$3096 + cell $and $and$libresoc.v:50461$3112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88088,10 +88344,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50358$3096_Y + connect \Y $and$libresoc.v:50461$3112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50363$3101 + cell $and $and$libresoc.v:50466$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88099,10 +88355,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50363$3101_Y + connect \Y $and$libresoc.v:50466$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50364$3102 + cell $and $and$libresoc.v:50467$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88110,10 +88366,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50364$3102_Y + connect \Y $and$libresoc.v:50467$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50367$3105 + cell $and $and$libresoc.v:50470$3121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88121,10 +88377,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50367$3105_Y + connect \Y $and$libresoc.v:50470$3121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50368$3106 + cell $and $and$libresoc.v:50471$3122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88132,10 +88388,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50368$3106_Y + connect \Y $and$libresoc.v:50471$3122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50369$3107 + cell $and $and$libresoc.v:50472$3123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88143,10 +88399,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50369$3107_Y + connect \Y $and$libresoc.v:50472$3123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50377$3115 + cell $and $and$libresoc.v:50480$3131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88154,10 +88410,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50377$3115_Y + connect \Y $and$libresoc.v:50480$3131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50378$3116 + cell $and $and$libresoc.v:50481$3132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88165,10 +88421,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50378$3116_Y + connect \Y $and$libresoc.v:50481$3132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50379$3117 + cell $and $and$libresoc.v:50482$3133 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88176,10 +88432,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50379$3117_Y + connect \Y $and$libresoc.v:50482$3133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50380$3118 + cell $and $and$libresoc.v:50483$3134 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88187,10 +88443,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50380$3118_Y + connect \Y $and$libresoc.v:50483$3134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50353$3091 + cell $eq $eq$libresoc.v:50456$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88198,10 +88454,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50353$3091_Y + connect \Y $eq$libresoc.v:50456$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50355$3093 + cell $eq $eq$libresoc.v:50458$3109 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88209,66 +88465,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50355$3093_Y + connect \Y $eq$libresoc.v:50458$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50336$3074 + cell $not $not$libresoc.v:50439$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50336$3074_Y + connect \Y $not$libresoc.v:50439$3090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50338$3076 + cell $not $not$libresoc.v:50441$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50338$3076_Y + connect \Y $not$libresoc.v:50441$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50341$3079 + cell $not $not$libresoc.v:50444$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50341$3079_Y + connect \Y $not$libresoc.v:50444$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50344$3082 + cell $not $not$libresoc.v:50447$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50344$3082_Y + connect \Y $not$libresoc.v:50447$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50350$3088 + cell $not $not$libresoc.v:50453$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50350$3088_Y + connect \Y $not$libresoc.v:50453$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50365$3103 + cell $not $not$libresoc.v:50468$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50365$3103_Y + connect \Y $not$libresoc.v:50468$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50381$3119 + cell $not $not$libresoc.v:50484$3135 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50381$3119_Y + connect \Y $not$libresoc.v:50484$3135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50348$3086 + cell $or $or$libresoc.v:50451$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88276,10 +88532,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50348$3086_Y + connect \Y $or$libresoc.v:50451$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50359$3097 + cell $or $or$libresoc.v:50462$3113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88287,10 +88543,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50359$3097_Y + connect \Y $or$libresoc.v:50462$3113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50360$3098 + cell $or $or$libresoc.v:50463$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88298,10 +88554,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50360$3098_Y + connect \Y $or$libresoc.v:50463$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50361$3099 + cell $or $or$libresoc.v:50464$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88309,10 +88565,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50361$3099_Y + connect \Y $or$libresoc.v:50464$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50362$3100 + cell $or $or$libresoc.v:50465$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88320,10 +88576,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50362$3100_Y + connect \Y $or$libresoc.v:50465$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50366$3104 + cell $or $or$libresoc.v:50469$3120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88331,10 +88587,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50366$3104_Y + connect \Y $or$libresoc.v:50469$3120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50376$3114 + cell $or $or$libresoc.v:50479$3130 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88342,90 +88598,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50376$3114_Y + connect \Y $or$libresoc.v:50479$3130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50325$3063 + cell $reduce_and $reduce_and$libresoc.v:50428$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50325$3063_Y + connect \Y $reduce_and$libresoc.v:50428$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50343$3081 + cell $reduce_or $reduce_or$libresoc.v:50446$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50343$3081_Y + connect \Y $reduce_or$libresoc.v:50446$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50346$3084 + cell $reduce_or $reduce_or$libresoc.v:50449$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50346$3084_Y + connect \Y $reduce_or$libresoc.v:50449$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50347$3085 + cell $reduce_or $reduce_or$libresoc.v:50450$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50347$3085_Y + connect \Y $reduce_or$libresoc.v:50450$3101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50370$3108 + cell $mux $ternary$libresoc.v:50473$3124 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50370$3108_Y + connect \Y $ternary$libresoc.v:50473$3124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50371$3109 + cell $mux $ternary$libresoc.v:50474$3125 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50371$3109_Y + connect \Y $ternary$libresoc.v:50474$3125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50372$3110 + cell $mux $ternary$libresoc.v:50475$3126 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50372$3110_Y + connect \Y $ternary$libresoc.v:50475$3126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50373$3111 + cell $mux $ternary$libresoc.v:50476$3127 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50373$3111_Y + connect \Y $ternary$libresoc.v:50476$3127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50374$3112 + cell $mux $ternary$libresoc.v:50477$3128 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50374$3112_Y + connect \Y $ternary$libresoc.v:50477$3128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50375$3113 + cell $mux $ternary$libresoc.v:50478$3129 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50375$3113_Y + connect \Y $ternary$libresoc.v:50478$3129_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50442.11-50464.4" + attribute \src "libresoc.v:50545.11-50567.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88450,7 +88706,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50465.14-50471.4" + attribute \src "libresoc.v:50568.14-50574.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88459,7 +88715,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50472.15-50478.4" + attribute \src "libresoc.v:50575.15-50581.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88468,7 +88724,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50479.14-50485.4" + attribute \src "libresoc.v:50582.14-50588.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88477,7 +88733,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50486.14-50492.4" + attribute \src "libresoc.v:50589.14-50595.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88486,7 +88742,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50493.14-50499.4" + attribute \src "libresoc.v:50596.14-50602.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88495,7 +88751,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50500.14-50505.4" + attribute \src "libresoc.v:50603.14-50608.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88503,7 +88759,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50506.14-50512.4" + attribute \src "libresoc.v:50609.14-50615.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88511,472 +88767,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49783.7-49783.20" - process $proc$libresoc.v:49783$3242 + attribute \src "libresoc.v:49886.7-49886.20" + process $proc$libresoc.v:49886$3258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49901.7-49901.24" - process $proc$libresoc.v:49901$3243 + attribute \src "libresoc.v:50004.7-50004.24" + process $proc$libresoc.v:50004$3259 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49932.14-49932.47" - process $proc$libresoc.v:49932$3244 + attribute \src "libresoc.v:50035.14-50035.47" + process $proc$libresoc.v:50035$3260 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:49936.14-49936.41" - process $proc$libresoc.v:49936$3245 + attribute \src "libresoc.v:50039.14-50039.41" + process $proc$libresoc.v:50039$3261 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50015.13-50015.45" - process $proc$libresoc.v:50015$3246 + attribute \src "libresoc.v:50118.13-50118.45" + process $proc$libresoc.v:50118$3262 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50039.7-50039.26" - process $proc$libresoc.v:50039$3247 + attribute \src "libresoc.v:50142.7-50142.26" + process $proc$libresoc.v:50142$3263 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:50047.7-50047.25" - process $proc$libresoc.v:50047$3248 + attribute \src "libresoc.v:50150.7-50150.25" + process $proc$libresoc.v:50150$3264 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50059.7-50059.27" - process $proc$libresoc.v:50059$3249 + attribute \src "libresoc.v:50162.7-50162.27" + process $proc$libresoc.v:50162$3265 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50093.14-50093.47" - process $proc$libresoc.v:50093$3250 + attribute \src "libresoc.v:50196.14-50196.47" + process $proc$libresoc.v:50196$3266 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:50097.7-50097.27" - process $proc$libresoc.v:50097$3251 + attribute \src "libresoc.v:50200.7-50200.27" + process $proc$libresoc.v:50200$3267 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50101.14-50101.38" - process $proc$libresoc.v:50101$3252 + attribute \src "libresoc.v:50204.14-50204.38" + process $proc$libresoc.v:50204$3268 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50105.7-50105.33" - process $proc$libresoc.v:50105$3253 + attribute \src "libresoc.v:50208.7-50208.33" + process $proc$libresoc.v:50208$3269 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50109.13-50109.33" - process $proc$libresoc.v:50109$3254 + attribute \src "libresoc.v:50212.13-50212.33" + process $proc$libresoc.v:50212$3270 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50113.7-50113.30" - process $proc$libresoc.v:50113$3255 + attribute \src "libresoc.v:50216.7-50216.30" + process $proc$libresoc.v:50216$3271 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50132.7-50132.25" - process $proc$libresoc.v:50132$3256 + attribute \src "libresoc.v:50235.7-50235.25" + process $proc$libresoc.v:50235$3272 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50136.7-50136.25" - process $proc$libresoc.v:50136$3257 + attribute \src "libresoc.v:50239.7-50239.25" + process $proc$libresoc.v:50239$3273 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50236.13-50236.30" - process $proc$libresoc.v:50236$3258 + attribute \src "libresoc.v:50339.13-50339.30" + process $proc$libresoc.v:50339$3274 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:50244.13-50244.31" - process $proc$libresoc.v:50244$3259 + attribute \src "libresoc.v:50347.13-50347.31" + process $proc$libresoc.v:50347$3275 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:50248.13-50248.31" - process $proc$libresoc.v:50248$3260 + attribute \src "libresoc.v:50351.13-50351.31" + process $proc$libresoc.v:50351$3276 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:50260.7-50260.26" - process $proc$libresoc.v:50260$3261 + attribute \src "libresoc.v:50363.7-50363.26" + process $proc$libresoc.v:50363$3277 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50264.7-50264.26" - process $proc$libresoc.v:50264$3262 + attribute \src "libresoc.v:50367.7-50367.26" + process $proc$libresoc.v:50367$3278 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50268.7-50268.25" - process $proc$libresoc.v:50268$3263 + attribute \src "libresoc.v:50371.7-50371.25" + process $proc$libresoc.v:50371$3279 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50272.7-50272.25" - process $proc$libresoc.v:50272$3264 + attribute \src "libresoc.v:50375.7-50375.25" + process $proc$libresoc.v:50375$3280 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50292.13-50292.32" - process $proc$libresoc.v:50292$3265 + attribute \src "libresoc.v:50395.13-50395.32" + process $proc$libresoc.v:50395$3281 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:50296.13-50296.32" - process $proc$libresoc.v:50296$3266 + attribute \src "libresoc.v:50399.13-50399.32" + process $proc$libresoc.v:50399$3282 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:50300.14-50300.43" - process $proc$libresoc.v:50300$3267 + attribute \src "libresoc.v:50403.14-50403.43" + process $proc$libresoc.v:50403$3283 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50304.14-50304.43" - process $proc$libresoc.v:50304$3268 + attribute \src "libresoc.v:50407.14-50407.43" + process $proc$libresoc.v:50407$3284 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50308.14-50308.28" - process $proc$libresoc.v:50308$3269 + attribute \src "libresoc.v:50411.14-50411.28" + process $proc$libresoc.v:50411$3285 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50312.13-50312.26" - process $proc$libresoc.v:50312$3270 + attribute \src "libresoc.v:50415.13-50415.26" + process $proc$libresoc.v:50415$3286 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50316.13-50316.26" - process $proc$libresoc.v:50316$3271 + attribute \src "libresoc.v:50419.13-50419.26" + process $proc$libresoc.v:50419$3287 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50320.13-50320.26" - process $proc$libresoc.v:50320$3272 + attribute \src "libresoc.v:50423.13-50423.26" + process $proc$libresoc.v:50423$3288 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50382.3-50383.39" - process $proc$libresoc.v:50382$3120 + attribute \src "libresoc.v:50485.3-50486.39" + process $proc$libresoc.v:50485$3136 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50384.3-50385.43" - process $proc$libresoc.v:50384$3121 + attribute \src "libresoc.v:50487.3-50488.43" + process $proc$libresoc.v:50487$3137 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50386.3-50387.29" - process $proc$libresoc.v:50386$3122 + attribute \src "libresoc.v:50489.3-50490.29" + process $proc$libresoc.v:50489$3138 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50388.3-50389.29" - process $proc$libresoc.v:50388$3123 + attribute \src "libresoc.v:50491.3-50492.29" + process $proc$libresoc.v:50491$3139 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50390.3-50391.29" - process $proc$libresoc.v:50390$3124 + attribute \src "libresoc.v:50493.3-50494.29" + process $proc$libresoc.v:50493$3140 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50392.3-50393.29" - process $proc$libresoc.v:50392$3125 + attribute \src "libresoc.v:50495.3-50496.29" + process $proc$libresoc.v:50495$3141 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50394.3-50395.29" - process $proc$libresoc.v:50394$3126 + attribute \src "libresoc.v:50497.3-50498.29" + process $proc$libresoc.v:50497$3142 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50396.3-50397.29" - process $proc$libresoc.v:50396$3127 + attribute \src "libresoc.v:50499.3-50500.29" + process $proc$libresoc.v:50499$3143 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50398.3-50399.43" - process $proc$libresoc.v:50398$3128 + attribute \src "libresoc.v:50501.3-50502.43" + process $proc$libresoc.v:50501$3144 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50400.3-50401.49" - process $proc$libresoc.v:50400$3129 + attribute \src "libresoc.v:50503.3-50504.49" + process $proc$libresoc.v:50503$3145 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50402.3-50403.49" - process $proc$libresoc.v:50402$3130 + attribute \src "libresoc.v:50505.3-50506.49" + process $proc$libresoc.v:50505$3146 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50404.3-50405.55" - process $proc$libresoc.v:50404$3131 + attribute \src "libresoc.v:50507.3-50508.55" + process $proc$libresoc.v:50507$3147 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50406.3-50407.37" - process $proc$libresoc.v:50406$3132 + attribute \src "libresoc.v:50509.3-50510.37" + process $proc$libresoc.v:50509$3148 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50408.3-50409.43" - process $proc$libresoc.v:50408$3133 + attribute \src "libresoc.v:50511.3-50512.43" + process $proc$libresoc.v:50511$3149 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50410.3-50411.65" - process $proc$libresoc.v:50410$3134 + attribute \src "libresoc.v:50513.3-50514.65" + process $proc$libresoc.v:50513$3150 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50412.3-50413.61" - process $proc$libresoc.v:50412$3135 + attribute \src "libresoc.v:50515.3-50516.61" + process $proc$libresoc.v:50515$3151 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50414.3-50415.55" - process $proc$libresoc.v:50414$3136 + attribute \src "libresoc.v:50517.3-50518.55" + process $proc$libresoc.v:50517$3152 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50416.3-50417.39" - process $proc$libresoc.v:50416$3137 + attribute \src "libresoc.v:50519.3-50520.39" + process $proc$libresoc.v:50519$3153 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50418.3-50419.39" - process $proc$libresoc.v:50418$3138 + attribute \src "libresoc.v:50521.3-50522.39" + process $proc$libresoc.v:50521$3154 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50420.3-50421.39" - process $proc$libresoc.v:50420$3139 + attribute \src "libresoc.v:50523.3-50524.39" + process $proc$libresoc.v:50523$3155 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50422.3-50423.39" - process $proc$libresoc.v:50422$3140 + attribute \src "libresoc.v:50525.3-50526.39" + process $proc$libresoc.v:50525$3156 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50424.3-50425.39" - process $proc$libresoc.v:50424$3141 + attribute \src "libresoc.v:50527.3-50528.39" + process $proc$libresoc.v:50527$3157 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50426.3-50427.39" - process $proc$libresoc.v:50426$3142 + attribute \src "libresoc.v:50529.3-50530.39" + process $proc$libresoc.v:50529$3158 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50428.3-50429.39" - process $proc$libresoc.v:50428$3143 + attribute \src "libresoc.v:50531.3-50532.39" + process $proc$libresoc.v:50531$3159 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50430.3-50431.39" - process $proc$libresoc.v:50430$3144 + attribute \src "libresoc.v:50533.3-50534.39" + process $proc$libresoc.v:50533$3160 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50432.3-50433.41" - process $proc$libresoc.v:50432$3145 + attribute \src "libresoc.v:50535.3-50536.41" + process $proc$libresoc.v:50535$3161 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50434.3-50435.41" - process $proc$libresoc.v:50434$3146 + attribute \src "libresoc.v:50537.3-50538.41" + process $proc$libresoc.v:50537$3162 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50436.3-50437.37" - process $proc$libresoc.v:50436$3147 + attribute \src "libresoc.v:50539.3-50540.37" + process $proc$libresoc.v:50539$3163 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50438.3-50439.39" - process $proc$libresoc.v:50438$3148 + attribute \src "libresoc.v:50541.3-50542.39" + process $proc$libresoc.v:50541$3164 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50440.3-50441.25" - process $proc$libresoc.v:50440$3149 + attribute \src "libresoc.v:50543.3-50544.25" + process $proc$libresoc.v:50543$3165 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50513.3-50522.6" - process $proc$libresoc.v:50513$3150 + attribute \src "libresoc.v:50616.3-50625.6" + process $proc$libresoc.v:50616$3166 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50514.5-50514.29" + attribute \src "libresoc.v:50617.5-50617.29" switch \initial - attribute \src "libresoc.v:50514.9-50514.17" + attribute \src "libresoc.v:50617.9-50617.17" case 1'1 case end @@ -88992,14 +89248,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50523.3-50531.6" - process $proc$libresoc.v:50523$3151 + attribute \src "libresoc.v:50626.3-50634.6" + process $proc$libresoc.v:50626$3167 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50524.5-50524.29" + assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169 + attribute \src "libresoc.v:50627.5-50627.29" switch \initial - attribute \src "libresoc.v:50524.9-50524.17" + attribute \src "libresoc.v:50627.9-50627.17" case 1'1 case end @@ -89008,21 +89264,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 + assign $1\rok_l_s_rdok$next[0:0]$3169 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$3169 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168 end - attribute \src "libresoc.v:50532.3-50540.6" - process $proc$libresoc.v:50532$3154 + attribute \src "libresoc.v:50635.3-50643.6" + process $proc$libresoc.v:50635$3170 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50533.5-50533.29" + assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172 + attribute \src "libresoc.v:50636.5-50636.29" switch \initial - attribute \src "libresoc.v:50533.9-50533.17" + attribute \src "libresoc.v:50636.9-50636.17" case 1'1 case end @@ -89031,21 +89287,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 + assign $1\rok_l_r_rdok$next[0:0]$3172 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 + assign $1\rok_l_r_rdok$next[0:0]$3172 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171 end - attribute \src "libresoc.v:50541.3-50549.6" - process $proc$libresoc.v:50541$3157 + attribute \src "libresoc.v:50644.3-50652.6" + process $proc$libresoc.v:50644$3173 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50542.5-50542.29" + assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175 + attribute \src "libresoc.v:50645.5-50645.29" switch \initial - attribute \src "libresoc.v:50542.9-50542.17" + attribute \src "libresoc.v:50645.9-50645.17" case 1'1 case end @@ -89054,21 +89310,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3159 1'0 + assign $1\rst_l_s_rst$next[0:0]$3175 1'0 case - assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd + assign $1\rst_l_s_rst$next[0:0]$3175 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174 end - attribute \src "libresoc.v:50550.3-50558.6" - process $proc$libresoc.v:50550$3160 + attribute \src "libresoc.v:50653.3-50661.6" + process $proc$libresoc.v:50653$3176 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50551.5-50551.29" + assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178 + attribute \src "libresoc.v:50654.5-50654.29" switch \initial - attribute \src "libresoc.v:50551.9-50551.17" + attribute \src "libresoc.v:50654.9-50654.17" case 1'1 case end @@ -89077,21 +89333,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3162 1'1 + assign $1\rst_l_r_rst$next[0:0]$3178 1'1 case - assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r + assign $1\rst_l_r_rst$next[0:0]$3178 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177 end - attribute \src "libresoc.v:50559.3-50567.6" - process $proc$libresoc.v:50559$3163 + attribute \src "libresoc.v:50662.3-50670.6" + process $proc$libresoc.v:50662$3179 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50560.5-50560.29" + assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181 + attribute \src "libresoc.v:50663.5-50663.29" switch \initial - attribute \src "libresoc.v:50560.9-50560.17" + attribute \src "libresoc.v:50663.9-50663.17" case 1'1 case end @@ -89100,21 +89356,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3165 1'0 + assign $1\opc_l_s_opc$next[0:0]$3181 1'0 case - assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$3181 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180 end - attribute \src "libresoc.v:50568.3-50576.6" - process $proc$libresoc.v:50568$3166 + attribute \src "libresoc.v:50671.3-50679.6" + process $proc$libresoc.v:50671$3182 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50569.5-50569.29" + assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184 + attribute \src "libresoc.v:50672.5-50672.29" switch \initial - attribute \src "libresoc.v:50569.9-50569.17" + attribute \src "libresoc.v:50672.9-50672.17" case 1'1 case end @@ -89123,21 +89379,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3168 1'1 + assign $1\opc_l_r_opc$next[0:0]$3184 1'1 case - assign $1\opc_l_r_opc$next[0:0]$3168 \req_done + assign $1\opc_l_r_opc$next[0:0]$3184 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183 end - attribute \src "libresoc.v:50577.3-50585.6" - process $proc$libresoc.v:50577$3169 + attribute \src "libresoc.v:50680.3-50688.6" + process $proc$libresoc.v:50680$3185 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50578.5-50578.29" + assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187 + attribute \src "libresoc.v:50681.5-50681.29" switch \initial - attribute \src "libresoc.v:50578.9-50578.17" + attribute \src "libresoc.v:50681.9-50681.17" case 1'1 case end @@ -89146,21 +89402,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$3171 6'000000 + assign $1\src_l_s_src$next[5:0]$3187 6'000000 case - assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$3187 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186 end - attribute \src "libresoc.v:50586.3-50594.6" - process $proc$libresoc.v:50586$3172 + attribute \src "libresoc.v:50689.3-50697.6" + process $proc$libresoc.v:50689$3188 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50587.5-50587.29" + assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190 + attribute \src "libresoc.v:50690.5-50690.29" switch \initial - attribute \src "libresoc.v:50587.9-50587.17" + attribute \src "libresoc.v:50690.9-50690.17" case 1'1 case end @@ -89169,21 +89425,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$3174 6'111111 + assign $1\src_l_r_src$next[5:0]$3190 6'111111 case - assign $1\src_l_r_src$next[5:0]$3174 \reset_r + assign $1\src_l_r_src$next[5:0]$3190 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189 end - attribute \src "libresoc.v:50595.3-50603.6" - process $proc$libresoc.v:50595$3175 + attribute \src "libresoc.v:50698.3-50706.6" + process $proc$libresoc.v:50698$3191 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50596.5-50596.29" + assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193 + attribute \src "libresoc.v:50699.5-50699.29" switch \initial - attribute \src "libresoc.v:50596.9-50596.17" + attribute \src "libresoc.v:50699.9-50699.17" case 1'1 case end @@ -89192,21 +89448,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$3177 3'000 + assign $1\req_l_s_req$next[2:0]$3193 3'000 case - assign $1\req_l_s_req$next[2:0]$3177 \$67 + assign $1\req_l_s_req$next[2:0]$3193 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192 end - attribute \src "libresoc.v:50604.3-50612.6" - process $proc$libresoc.v:50604$3178 + attribute \src "libresoc.v:50707.3-50715.6" + process $proc$libresoc.v:50707$3194 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50605.5-50605.29" + assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196 + attribute \src "libresoc.v:50708.5-50708.29" switch \initial - attribute \src "libresoc.v:50605.9-50605.17" + attribute \src "libresoc.v:50708.9-50708.17" case 1'1 case end @@ -89215,27 +89471,27 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$3180 3'111 + assign $1\req_l_r_req$next[2:0]$3196 3'111 case - assign $1\req_l_r_req$next[2:0]$3180 \$69 + assign $1\req_l_r_req$next[2:0]$3196 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195 end - attribute \src "libresoc.v:50613.3-50624.6" - process $proc$libresoc.v:50613$3181 + attribute \src "libresoc.v:50716.3-50727.6" + process $proc$libresoc.v:50716$3197 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50614.5-50614.29" + assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 + attribute \src "libresoc.v:50717.5-50717.29" switch \initial - attribute \src "libresoc.v:50614.9-50614.17" + attribute \src "libresoc.v:50717.9-50717.17" case 1'1 case end @@ -89246,31 +89502,31 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3202 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type + assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3202 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 end - attribute \src "libresoc.v:50625.3-50646.6" - process $proc$libresoc.v:50625$3188 + attribute \src "libresoc.v:50728.3-50749.6" + process $proc$libresoc.v:50728$3204 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 + assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50626.5-50626.29" + assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211 + attribute \src "libresoc.v:50729.5-50729.29" switch \initial - attribute \src "libresoc.v:50626.9-50626.17" + attribute \src "libresoc.v:50729.9-50729.17" case 1'1 case end @@ -89280,10 +89536,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } + assign { $1\data_r0__o_ok$next[0:0]$3208 $1\data_r0__o$next[63:0]$3207 } { \o_ok \alu_cr0_o } case - assign $1\data_r0__o$next[63:0]$3191 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$3207 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3208 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89291,38 +89547,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$3210 $2\data_r0__o$next[63:0]$3209 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 - assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 + assign $2\data_r0__o$next[63:0]$3209 $1\data_r0__o$next[63:0]$3207 + assign $2\data_r0__o_ok$next[0:0]$3210 $1\data_r0__o_ok$next[0:0]$3208 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3195 1'0 + assign $3\data_r0__o_ok$next[0:0]$3211 1'0 case - assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 + assign $3\data_r0__o_ok$next[0:0]$3211 $2\data_r0__o_ok$next[0:0]$3210 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 + update \data_r0__o$next $0\data_r0__o$next[63:0]$3205 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50647.3-50668.6" - process $proc$libresoc.v:50647$3196 + attribute \src "libresoc.v:50750.3-50771.6" + process $proc$libresoc.v:50750$3212 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 + assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217 assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50648.5-50648.29" + assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219 + attribute \src "libresoc.v:50751.5-50751.29" switch \initial - attribute \src "libresoc.v:50648.9-50648.17" + attribute \src "libresoc.v:50751.9-50751.17" case 1'1 case end @@ -89332,10 +89588,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } + assign { $1\data_r1__full_cr_ok$next[0:0]$3216 $1\data_r1__full_cr$next[31:0]$3215 } { \full_cr_ok \alu_cr0_full_cr } case - assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok + assign $1\data_r1__full_cr$next[31:0]$3215 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3216 \data_r1__full_cr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89343,38 +89599,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 + assign { $2\data_r1__full_cr_ok$next[0:0]$3218 $2\data_r1__full_cr$next[31:0]$3217 } 33'000000000000000000000000000000000 case - assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 - assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 + assign $2\data_r1__full_cr$next[31:0]$3217 $1\data_r1__full_cr$next[31:0]$3215 + assign $2\data_r1__full_cr_ok$next[0:0]$3218 $1\data_r1__full_cr_ok$next[0:0]$3216 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 + assign $3\data_r1__full_cr_ok$next[0:0]$3219 1'0 case - assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 + assign $3\data_r1__full_cr_ok$next[0:0]$3219 $2\data_r1__full_cr_ok$next[0:0]$3218 end sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214 end - attribute \src "libresoc.v:50669.3-50690.6" - process $proc$libresoc.v:50669$3204 + attribute \src "libresoc.v:50772.3-50793.6" + process $proc$libresoc.v:50772$3220 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 + assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225 assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50670.5-50670.29" + assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227 + attribute \src "libresoc.v:50773.5-50773.29" switch \initial - attribute \src "libresoc.v:50670.9-50670.17" + attribute \src "libresoc.v:50773.9-50773.17" case 1'1 case end @@ -89384,10 +89640,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } + assign { $1\data_r2__cr_a_ok$next[0:0]$3224 $1\data_r2__cr_a$next[3:0]$3223 } { \cr_a_ok \alu_cr0_cr_a } case - assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok + assign $1\data_r2__cr_a$next[3:0]$3223 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3224 \data_r2__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -89395,32 +89651,32 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 + assign { $2\data_r2__cr_a_ok$next[0:0]$3226 $2\data_r2__cr_a$next[3:0]$3225 } 5'00000 case - assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 - assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 + assign $2\data_r2__cr_a$next[3:0]$3225 $1\data_r2__cr_a$next[3:0]$3223 + assign $2\data_r2__cr_a_ok$next[0:0]$3226 $1\data_r2__cr_a_ok$next[0:0]$3224 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 + assign $3\data_r2__cr_a_ok$next[0:0]$3227 1'0 case - assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 + assign $3\data_r2__cr_a_ok$next[0:0]$3227 $2\data_r2__cr_a_ok$next[0:0]$3226 end sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222 end - attribute \src "libresoc.v:50691.3-50700.6" - process $proc$libresoc.v:50691$3212 + attribute \src "libresoc.v:50794.3-50803.6" + process $proc$libresoc.v:50794$3228 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50692.5-50692.29" + assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230 + attribute \src "libresoc.v:50795.5-50795.29" switch \initial - attribute \src "libresoc.v:50692.9-50692.17" + attribute \src "libresoc.v:50795.9-50795.17" case 1'1 case end @@ -89429,21 +89685,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$3214 \src1_i + assign $1\src_r0$next[63:0]$3230 \src1_i case - assign $1\src_r0$next[63:0]$3214 \src_r0 + assign $1\src_r0$next[63:0]$3230 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$3213 + update \src_r0$next $0\src_r0$next[63:0]$3229 end - attribute \src "libresoc.v:50701.3-50710.6" - process $proc$libresoc.v:50701$3215 + attribute \src "libresoc.v:50804.3-50813.6" + process $proc$libresoc.v:50804$3231 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50702.5-50702.29" + assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233 + attribute \src "libresoc.v:50805.5-50805.29" switch \initial - attribute \src "libresoc.v:50702.9-50702.17" + attribute \src "libresoc.v:50805.9-50805.17" case 1'1 case end @@ -89452,21 +89708,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$3217 \src2_i + assign $1\src_r1$next[63:0]$3233 \src2_i case - assign $1\src_r1$next[63:0]$3217 \src_r1 + assign $1\src_r1$next[63:0]$3233 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$3216 + update \src_r1$next $0\src_r1$next[63:0]$3232 end - attribute \src "libresoc.v:50711.3-50720.6" - process $proc$libresoc.v:50711$3218 + attribute \src "libresoc.v:50814.3-50823.6" + process $proc$libresoc.v:50814$3234 assign { } { } assign { } { } - assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50712.5-50712.29" + assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236 + attribute \src "libresoc.v:50815.5-50815.29" switch \initial - attribute \src "libresoc.v:50712.9-50712.17" + attribute \src "libresoc.v:50815.9-50815.17" case 1'1 case end @@ -89475,21 +89731,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[31:0]$3220 \src3_i + assign $1\src_r2$next[31:0]$3236 \src3_i case - assign $1\src_r2$next[31:0]$3220 \src_r2 + assign $1\src_r2$next[31:0]$3236 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[31:0]$3219 + update \src_r2$next $0\src_r2$next[31:0]$3235 end - attribute \src "libresoc.v:50721.3-50730.6" - process $proc$libresoc.v:50721$3221 + attribute \src "libresoc.v:50824.3-50833.6" + process $proc$libresoc.v:50824$3237 assign { } { } assign { } { } - assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50722.5-50722.29" + assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239 + attribute \src "libresoc.v:50825.5-50825.29" switch \initial - attribute \src "libresoc.v:50722.9-50722.17" + attribute \src "libresoc.v:50825.9-50825.17" case 1'1 case end @@ -89498,21 +89754,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[3:0]$3223 \src4_i + assign $1\src_r3$next[3:0]$3239 \src4_i case - assign $1\src_r3$next[3:0]$3223 \src_r3 + assign $1\src_r3$next[3:0]$3239 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[3:0]$3222 + update \src_r3$next $0\src_r3$next[3:0]$3238 end - attribute \src "libresoc.v:50731.3-50740.6" - process $proc$libresoc.v:50731$3224 + attribute \src "libresoc.v:50834.3-50843.6" + process $proc$libresoc.v:50834$3240 assign { } { } assign { } { } - assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50732.5-50732.29" + assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242 + attribute \src "libresoc.v:50835.5-50835.29" switch \initial - attribute \src "libresoc.v:50732.9-50732.17" + attribute \src "libresoc.v:50835.9-50835.17" case 1'1 case end @@ -89521,21 +89777,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[3:0]$3226 \src5_i + assign $1\src_r4$next[3:0]$3242 \src5_i case - assign $1\src_r4$next[3:0]$3226 \src_r4 + assign $1\src_r4$next[3:0]$3242 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[3:0]$3225 + update \src_r4$next $0\src_r4$next[3:0]$3241 end - attribute \src "libresoc.v:50741.3-50750.6" - process $proc$libresoc.v:50741$3227 + attribute \src "libresoc.v:50844.3-50853.6" + process $proc$libresoc.v:50844$3243 assign { } { } assign { } { } - assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50742.5-50742.29" + assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245 + attribute \src "libresoc.v:50845.5-50845.29" switch \initial - attribute \src "libresoc.v:50742.9-50742.17" + attribute \src "libresoc.v:50845.9-50845.17" case 1'1 case end @@ -89544,21 +89800,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[3:0]$3229 \src6_i + assign $1\src_r5$next[3:0]$3245 \src6_i case - assign $1\src_r5$next[3:0]$3229 \src_r5 + assign $1\src_r5$next[3:0]$3245 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[3:0]$3228 + update \src_r5$next $0\src_r5$next[3:0]$3244 end - attribute \src "libresoc.v:50751.3-50759.6" - process $proc$libresoc.v:50751$3230 + attribute \src "libresoc.v:50854.3-50862.6" + process $proc$libresoc.v:50854$3246 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50752.5-50752.29" + assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248 + attribute \src "libresoc.v:50855.5-50855.29" switch \initial - attribute \src "libresoc.v:50752.9-50752.17" + attribute \src "libresoc.v:50855.9-50855.17" case 1'1 case end @@ -89567,21 +89823,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3232 1'1 + assign $1\alui_l_r_alui$next[0:0]$3248 1'1 case - assign $1\alui_l_r_alui$next[0:0]$3232 \$89 + assign $1\alui_l_r_alui$next[0:0]$3248 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247 end - attribute \src "libresoc.v:50760.3-50768.6" - process $proc$libresoc.v:50760$3233 + attribute \src "libresoc.v:50863.3-50871.6" + process $proc$libresoc.v:50863$3249 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50761.5-50761.29" + assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251 + attribute \src "libresoc.v:50864.5-50864.29" switch \initial - attribute \src "libresoc.v:50761.9-50761.17" + attribute \src "libresoc.v:50864.9-50864.17" case 1'1 case end @@ -89590,21 +89846,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3235 1'1 + assign $1\alu_l_r_alu$next[0:0]$3251 1'1 case - assign $1\alu_l_r_alu$next[0:0]$3235 \$91 + assign $1\alu_l_r_alu$next[0:0]$3251 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250 end - attribute \src "libresoc.v:50769.3-50778.6" - process $proc$libresoc.v:50769$3236 + attribute \src "libresoc.v:50872.3-50881.6" + process $proc$libresoc.v:50872$3252 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50770.5-50770.29" + attribute \src "libresoc.v:50873.5-50873.29" switch \initial - attribute \src "libresoc.v:50770.9-50770.17" + attribute \src "libresoc.v:50873.9-50873.17" case 1'1 case end @@ -89620,14 +89876,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50779.3-50788.6" - process $proc$libresoc.v:50779$3237 + attribute \src "libresoc.v:50882.3-50891.6" + process $proc$libresoc.v:50882$3253 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50780.5-50780.29" + attribute \src "libresoc.v:50883.5-50883.29" switch \initial - attribute \src "libresoc.v:50780.9-50780.17" + attribute \src "libresoc.v:50883.9-50883.17" case 1'1 case end @@ -89643,14 +89899,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50789.3-50798.6" - process $proc$libresoc.v:50789$3238 + attribute \src "libresoc.v:50892.3-50901.6" + process $proc$libresoc.v:50892$3254 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50790.5-50790.29" + attribute \src "libresoc.v:50893.5-50893.29" switch \initial - attribute \src "libresoc.v:50790.9-50790.17" + attribute \src "libresoc.v:50893.9-50893.17" case 1'1 case end @@ -89666,14 +89922,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50799.3-50807.6" - process $proc$libresoc.v:50799$3239 + attribute \src "libresoc.v:50902.3-50910.6" + process $proc$libresoc.v:50902$3255 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50800.5-50800.29" + assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257 + attribute \src "libresoc.v:50903.5-50903.29" switch \initial - attribute \src "libresoc.v:50800.9-50800.17" + attribute \src "libresoc.v:50903.9-50903.17" case 1'1 case end @@ -89682,70 +89938,70 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$3241 3'000 - case - assign $1\prev_wr_go$next[2:0]$3241 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 - end - connect \$5 $reduce_and$libresoc.v:50325$3063_Y - connect \$99 $and$libresoc.v:50326$3064_Y - connect \$101 $and$libresoc.v:50327$3065_Y - connect \$103 $and$libresoc.v:50328$3066_Y - connect \$105 $and$libresoc.v:50329$3067_Y - connect \$107 $and$libresoc.v:50330$3068_Y - connect \$109 $and$libresoc.v:50331$3069_Y - connect \$111 $and$libresoc.v:50332$3070_Y - connect \$113 $and$libresoc.v:50333$3071_Y - connect \$115 $and$libresoc.v:50334$3072_Y - connect \$11 $and$libresoc.v:50335$3073_Y - connect \$13 $not$libresoc.v:50336$3074_Y - connect \$15 $and$libresoc.v:50337$3075_Y - connect \$17 $not$libresoc.v:50338$3076_Y - connect \$19 $and$libresoc.v:50339$3077_Y - connect \$21 $and$libresoc.v:50340$3078_Y - connect \$25 $not$libresoc.v:50341$3079_Y - connect \$27 $and$libresoc.v:50342$3080_Y - connect \$24 $reduce_or$libresoc.v:50343$3081_Y - connect \$23 $not$libresoc.v:50344$3082_Y - connect \$31 $and$libresoc.v:50345$3083_Y - connect \$33 $reduce_or$libresoc.v:50346$3084_Y - connect \$35 $reduce_or$libresoc.v:50347$3085_Y - connect \$37 $or$libresoc.v:50348$3086_Y - connect \$3 $and$libresoc.v:50349$3087_Y - connect \$39 $not$libresoc.v:50350$3088_Y - connect \$41 $and$libresoc.v:50351$3089_Y - connect \$43 $and$libresoc.v:50352$3090_Y - connect \$45 $eq$libresoc.v:50353$3091_Y - connect \$47 $and$libresoc.v:50354$3092_Y - connect \$49 $eq$libresoc.v:50355$3093_Y - connect \$51 $and$libresoc.v:50356$3094_Y - connect \$53 $and$libresoc.v:50357$3095_Y - connect \$55 $and$libresoc.v:50358$3096_Y - connect \$57 $or$libresoc.v:50359$3097_Y - connect \$59 $or$libresoc.v:50360$3098_Y - connect \$61 $or$libresoc.v:50361$3099_Y - connect \$63 $or$libresoc.v:50362$3100_Y - connect \$65 $and$libresoc.v:50363$3101_Y - connect \$67 $and$libresoc.v:50364$3102_Y - connect \$6 $not$libresoc.v:50365$3103_Y - connect \$69 $or$libresoc.v:50366$3104_Y - connect \$71 $and$libresoc.v:50367$3105_Y - connect \$73 $and$libresoc.v:50368$3106_Y - connect \$75 $and$libresoc.v:50369$3107_Y - connect \$77 $ternary$libresoc.v:50370$3108_Y - connect \$79 $ternary$libresoc.v:50371$3109_Y - connect \$81 $ternary$libresoc.v:50372$3110_Y - connect \$83 $ternary$libresoc.v:50373$3111_Y - connect \$85 $ternary$libresoc.v:50374$3112_Y - connect \$87 $ternary$libresoc.v:50375$3113_Y - connect \$8 $or$libresoc.v:50376$3114_Y - connect \$89 $and$libresoc.v:50377$3115_Y - connect \$91 $and$libresoc.v:50378$3116_Y - connect \$93 $and$libresoc.v:50379$3117_Y - connect \$95 $and$libresoc.v:50380$3118_Y - connect \$97 $not$libresoc.v:50381$3119_Y + assign $1\prev_wr_go$next[2:0]$3257 3'000 + case + assign $1\prev_wr_go$next[2:0]$3257 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256 + end + connect \$5 $reduce_and$libresoc.v:50428$3079_Y + connect \$99 $and$libresoc.v:50429$3080_Y + connect \$101 $and$libresoc.v:50430$3081_Y + connect \$103 $and$libresoc.v:50431$3082_Y + connect \$105 $and$libresoc.v:50432$3083_Y + connect \$107 $and$libresoc.v:50433$3084_Y + connect \$109 $and$libresoc.v:50434$3085_Y + connect \$111 $and$libresoc.v:50435$3086_Y + connect \$113 $and$libresoc.v:50436$3087_Y + connect \$115 $and$libresoc.v:50437$3088_Y + connect \$11 $and$libresoc.v:50438$3089_Y + connect \$13 $not$libresoc.v:50439$3090_Y + connect \$15 $and$libresoc.v:50440$3091_Y + connect \$17 $not$libresoc.v:50441$3092_Y + connect \$19 $and$libresoc.v:50442$3093_Y + connect \$21 $and$libresoc.v:50443$3094_Y + connect \$25 $not$libresoc.v:50444$3095_Y + connect \$27 $and$libresoc.v:50445$3096_Y + connect \$24 $reduce_or$libresoc.v:50446$3097_Y + connect \$23 $not$libresoc.v:50447$3098_Y + connect \$31 $and$libresoc.v:50448$3099_Y + connect \$33 $reduce_or$libresoc.v:50449$3100_Y + connect \$35 $reduce_or$libresoc.v:50450$3101_Y + connect \$37 $or$libresoc.v:50451$3102_Y + connect \$3 $and$libresoc.v:50452$3103_Y + connect \$39 $not$libresoc.v:50453$3104_Y + connect \$41 $and$libresoc.v:50454$3105_Y + connect \$43 $and$libresoc.v:50455$3106_Y + connect \$45 $eq$libresoc.v:50456$3107_Y + connect \$47 $and$libresoc.v:50457$3108_Y + connect \$49 $eq$libresoc.v:50458$3109_Y + connect \$51 $and$libresoc.v:50459$3110_Y + connect \$53 $and$libresoc.v:50460$3111_Y + connect \$55 $and$libresoc.v:50461$3112_Y + connect \$57 $or$libresoc.v:50462$3113_Y + connect \$59 $or$libresoc.v:50463$3114_Y + connect \$61 $or$libresoc.v:50464$3115_Y + connect \$63 $or$libresoc.v:50465$3116_Y + connect \$65 $and$libresoc.v:50466$3117_Y + connect \$67 $and$libresoc.v:50467$3118_Y + connect \$6 $not$libresoc.v:50468$3119_Y + connect \$69 $or$libresoc.v:50469$3120_Y + connect \$71 $and$libresoc.v:50470$3121_Y + connect \$73 $and$libresoc.v:50471$3122_Y + connect \$75 $and$libresoc.v:50472$3123_Y + connect \$77 $ternary$libresoc.v:50473$3124_Y + connect \$79 $ternary$libresoc.v:50474$3125_Y + connect \$81 $ternary$libresoc.v:50475$3126_Y + connect \$83 $ternary$libresoc.v:50476$3127_Y + connect \$85 $ternary$libresoc.v:50477$3128_Y + connect \$87 $ternary$libresoc.v:50478$3129_Y + connect \$8 $or$libresoc.v:50479$3130_Y + connect \$89 $and$libresoc.v:50480$3131_Y + connect \$91 $and$libresoc.v:50481$3132_Y + connect \$93 $and$libresoc.v:50482$3133_Y + connect \$95 $and$libresoc.v:50483$3134_Y + connect \$97 $not$libresoc.v:50484$3135_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89778,31 +90034,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50843.1-50892.10" +attribute \src "libresoc.v:50946.1-50995.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50844.7-50844.20" + attribute \src "libresoc.v:50947.7-50947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50880.3-50888.6" - wire $0\q_int$next[0:0]$3280 - attribute \src "libresoc.v:50878.3-50879.27" + attribute \src "libresoc.v:50983.3-50991.6" + wire $0\q_int$next[0:0]$3296 + attribute \src "libresoc.v:50981.3-50982.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50880.3-50888.6" - wire $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50862.7-50862.19" + attribute \src "libresoc.v:50983.3-50991.6" + wire $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50965.7-50965.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50875.17-50875.96" - wire $and$libresoc.v:50875$3275_Y - attribute \src "libresoc.v:50874.17-50874.92" - wire $not$libresoc.v:50874$3274_Y - attribute \src "libresoc.v:50877.17-50877.92" - wire $not$libresoc.v:50877$3277_Y - attribute \src "libresoc.v:50873.17-50873.98" - wire $or$libresoc.v:50873$3273_Y - attribute \src "libresoc.v:50876.17-50876.97" - wire $or$libresoc.v:50876$3276_Y + attribute \src "libresoc.v:50978.17-50978.96" + wire $and$libresoc.v:50978$3291_Y + attribute \src "libresoc.v:50977.17-50977.92" + wire $not$libresoc.v:50977$3290_Y + attribute \src "libresoc.v:50980.17-50980.92" + wire $not$libresoc.v:50980$3293_Y + attribute \src "libresoc.v:50976.17-50976.98" + wire $or$libresoc.v:50976$3289_Y + attribute \src "libresoc.v:50979.17-50979.97" + wire $or$libresoc.v:50979$3292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -89813,11 +90069,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:50844.7-50844.15" + attribute \src "libresoc.v:50947.7-50947.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -89834,7 +90090,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50875$3275 + cell $and $and$libresoc.v:50978$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89842,26 +90098,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50875$3275_Y + connect \Y $and$libresoc.v:50978$3291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50874$3274 + cell $not $not$libresoc.v:50977$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50874$3274_Y + connect \Y $not$libresoc.v:50977$3290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50877$3277 + cell $not $not$libresoc.v:50980$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50877$3277_Y + connect \Y $not$libresoc.v:50980$3293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50873$3273 + cell $or $or$libresoc.v:50976$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89869,10 +90125,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50873$3273_Y + connect \Y $or$libresoc.v:50976$3289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50876$3276 + cell $or $or$libresoc.v:50979$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89880,39 +90136,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50876$3276_Y + connect \Y $or$libresoc.v:50979$3292_Y end - attribute \src "libresoc.v:50844.7-50844.20" - process $proc$libresoc.v:50844$3282 + attribute \src "libresoc.v:50947.7-50947.20" + process $proc$libresoc.v:50947$3298 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50862.7-50862.19" - process $proc$libresoc.v:50862$3283 + attribute \src "libresoc.v:50965.7-50965.19" + process $proc$libresoc.v:50965$3299 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50878.3-50879.27" - process $proc$libresoc.v:50878$3278 + attribute \src "libresoc.v:50981.3-50982.27" + process $proc$libresoc.v:50981$3294 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50880.3-50888.6" - process $proc$libresoc.v:50880$3279 + attribute \src "libresoc.v:50983.3-50991.6" + process $proc$libresoc.v:50983$3295 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 - attribute \src "libresoc.v:50881.5-50881.29" + assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50984.5-50984.29" switch \initial - attribute \src "libresoc.v:50881.9-50881.17" + attribute \src "libresoc.v:50984.9-50984.17" case 1'1 case end @@ -89921,331 +90177,331 @@ module \cyc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$3281 1'0 + assign $1\q_int$next[0:0]$3297 1'0 case - assign $1\q_int$next[0:0]$3281 \$5 + assign $1\q_int$next[0:0]$3297 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$3280 + update \q_int$next $0\q_int$next[0:0]$3296 end - connect \$9 $or$libresoc.v:50873$3273_Y - connect \$1 $not$libresoc.v:50874$3274_Y - connect \$3 $and$libresoc.v:50875$3275_Y - connect \$5 $or$libresoc.v:50876$3276_Y - connect \$7 $not$libresoc.v:50877$3277_Y + connect \$9 $or$libresoc.v:50976$3289_Y + connect \$1 $not$libresoc.v:50977$3290_Y + connect \$3 $and$libresoc.v:50978$3291_Y + connect \$5 $or$libresoc.v:50979$3292_Y + connect \$7 $not$libresoc.v:50980$3293_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50896.1-51628.10" +attribute \src "libresoc.v:50999.1-51731.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51441.3-51450.6" + attribute \src "libresoc.v:51544.3-51553.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51248.3-51257.6" + attribute \src "libresoc.v:51351.3-51360.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51451.3-51460.6" + attribute \src "libresoc.v:51554.3-51563.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51230.3-51247.6" + attribute \src "libresoc.v:51333.3-51350.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51461.3-51494.6" + attribute \src "libresoc.v:51564.3-51597.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51432.3-51440.6" - wire $0\dmi_read_log_data$next[0:0]$3398 - attribute \src "libresoc.v:51208.3-51209.51" + attribute \src "libresoc.v:51535.3-51543.6" + wire $0\dmi_read_log_data$next[0:0]$3414 + attribute \src "libresoc.v:51311.3-51312.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51423.3-51431.6" - wire $0\dmi_read_log_data_1$next[0:0]$3395 - attribute \src "libresoc.v:51210.3-51211.55" + attribute \src "libresoc.v:51526.3-51534.6" + wire $0\dmi_read_log_data_1$next[0:0]$3411 + attribute \src "libresoc.v:51313.3-51314.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51258.3-51266.6" - wire $0\dmi_req_i_1$next[0:0]$3361 - attribute \src "libresoc.v:51220.3-51221.39" + attribute \src "libresoc.v:51361.3-51369.6" + wire $0\dmi_req_i_1$next[0:0]$3377 + attribute \src "libresoc.v:51323.3-51324.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $0\do_dmi_log_rd$next[0:0]$3425 - attribute \src "libresoc.v:51222.3-51223.43" + attribute \src "libresoc.v:51688.3-51721.6" + wire $0\do_dmi_log_rd$next[0:0]$3441 + attribute \src "libresoc.v:51325.3-51326.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51555.3-51584.6" - wire $0\do_icreset$next[0:0]$3418 - attribute \src "libresoc.v:51224.3-51225.37" + attribute \src "libresoc.v:51658.3-51687.6" + wire $0\do_icreset$next[0:0]$3434 + attribute \src "libresoc.v:51327.3-51328.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51525.3-51554.6" - wire $0\do_reset$next[0:0]$3411 - attribute \src "libresoc.v:51226.3-51227.33" + attribute \src "libresoc.v:51628.3-51657.6" + wire $0\do_reset$next[0:0]$3427 + attribute \src "libresoc.v:51329.3-51330.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51495.3-51524.6" - wire $0\do_step$next[0:0]$3404 - attribute \src "libresoc.v:51228.3-51229.31" + attribute \src "libresoc.v:51598.3-51627.6" + wire $0\do_step$next[0:0]$3420 + attribute \src "libresoc.v:51331.3-51332.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $0\gspr_index$next[6:0]$3383 - attribute \src "libresoc.v:51214.3-51215.37" + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $0\gspr_index$next[6:0]$3399 + attribute \src "libresoc.v:51317.3-51318.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50897.7-50897.20" + attribute \src "libresoc.v:51000.7-51000.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3389 - attribute \src "libresoc.v:51212.3-51213.41" + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3405 + attribute \src "libresoc.v:51315.3-51316.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51317.3-51360.6" - wire $0\stopping$next[0:0]$3374 - attribute \src "libresoc.v:51216.3-51217.33" + attribute \src "libresoc.v:51420.3-51463.6" + wire $0\stopping$next[0:0]$3390 + attribute \src "libresoc.v:51319.3-51320.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51267.3-51316.6" - wire $0\terminated$next[0:0]$3364 - attribute \src "libresoc.v:51218.3-51219.37" + attribute \src "libresoc.v:51370.3-51419.6" + wire $0\terminated$next[0:0]$3380 + attribute \src "libresoc.v:51321.3-51322.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51441.3-51450.6" + attribute \src "libresoc.v:51544.3-51553.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51248.3-51257.6" + attribute \src "libresoc.v:51351.3-51360.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51451.3-51460.6" + attribute \src "libresoc.v:51554.3-51563.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51230.3-51247.6" + attribute \src "libresoc.v:51333.3-51350.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51461.3-51494.6" + attribute \src "libresoc.v:51564.3-51597.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51432.3-51440.6" - wire $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51084.7-51084.31" + attribute \src "libresoc.v:51535.3-51543.6" + wire $1\dmi_read_log_data$next[0:0]$3415 + attribute \src "libresoc.v:51187.7-51187.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51423.3-51431.6" - wire $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51088.7-51088.33" + attribute \src "libresoc.v:51526.3-51534.6" + wire $1\dmi_read_log_data_1$next[0:0]$3412 + attribute \src "libresoc.v:51191.7-51191.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51258.3-51266.6" - wire $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51094.7-51094.25" + attribute \src "libresoc.v:51361.3-51369.6" + wire $1\dmi_req_i_1$next[0:0]$3378 + attribute \src "libresoc.v:51197.7-51197.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $1\do_dmi_log_rd$next[0:0]$3426 - attribute \src "libresoc.v:51100.7-51100.27" + attribute \src "libresoc.v:51688.3-51721.6" + wire $1\do_dmi_log_rd$next[0:0]$3442 + attribute \src "libresoc.v:51203.7-51203.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51555.3-51584.6" - wire $1\do_icreset$next[0:0]$3419 - attribute \src "libresoc.v:51104.7-51104.24" + attribute \src "libresoc.v:51658.3-51687.6" + wire $1\do_icreset$next[0:0]$3435 + attribute \src "libresoc.v:51207.7-51207.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51525.3-51554.6" - wire $1\do_reset$next[0:0]$3412 - attribute \src "libresoc.v:51108.7-51108.22" + attribute \src "libresoc.v:51628.3-51657.6" + wire $1\do_reset$next[0:0]$3428 + attribute \src "libresoc.v:51211.7-51211.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51495.3-51524.6" - wire $1\do_step$next[0:0]$3405 - attribute \src "libresoc.v:51112.7-51112.21" + attribute \src "libresoc.v:51598.3-51627.6" + wire $1\do_step$next[0:0]$3421 + attribute \src "libresoc.v:51215.7-51215.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $1\gspr_index$next[6:0]$3384 - attribute \src "libresoc.v:51116.13-51116.31" + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $1\gspr_index$next[6:0]$3400 + attribute \src "libresoc.v:51219.13-51219.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3390 - attribute \src "libresoc.v:51122.14-51122.34" + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3406 + attribute \src "libresoc.v:51225.14-51225.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51317.3-51360.6" - wire $1\stopping$next[0:0]$3375 - attribute \src "libresoc.v:51134.7-51134.22" + attribute \src "libresoc.v:51420.3-51463.6" + wire $1\stopping$next[0:0]$3391 + attribute \src "libresoc.v:51237.7-51237.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51267.3-51316.6" - wire $1\terminated$next[0:0]$3365 - attribute \src "libresoc.v:51140.7-51140.24" + attribute \src "libresoc.v:51370.3-51419.6" + wire $1\terminated$next[0:0]$3381 + attribute \src "libresoc.v:51243.7-51243.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51585.3-51618.6" - wire $2\do_dmi_log_rd$next[0:0]$3427 - attribute \src "libresoc.v:51555.3-51584.6" - wire $2\do_icreset$next[0:0]$3420 - attribute \src "libresoc.v:51525.3-51554.6" - wire $2\do_reset$next[0:0]$3413 - attribute \src "libresoc.v:51495.3-51524.6" - wire $2\do_step$next[0:0]$3406 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $2\gspr_index$next[6:0]$3385 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3391 - attribute \src "libresoc.v:51317.3-51360.6" - wire $2\stopping$next[0:0]$3376 - attribute \src "libresoc.v:51267.3-51316.6" - wire $2\terminated$next[0:0]$3366 - attribute \src "libresoc.v:51585.3-51618.6" - wire $3\do_dmi_log_rd$next[0:0]$3428 - attribute \src "libresoc.v:51555.3-51584.6" - wire $3\do_icreset$next[0:0]$3421 - attribute \src "libresoc.v:51525.3-51554.6" - wire $3\do_reset$next[0:0]$3414 - attribute \src "libresoc.v:51495.3-51524.6" - wire $3\do_step$next[0:0]$3407 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $3\gspr_index$next[6:0]$3386 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3392 - attribute \src "libresoc.v:51317.3-51360.6" - wire $3\stopping$next[0:0]$3377 - attribute \src "libresoc.v:51267.3-51316.6" - wire $3\terminated$next[0:0]$3367 - attribute \src "libresoc.v:51585.3-51618.6" - wire $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51555.3-51584.6" - wire $4\do_icreset$next[0:0]$3422 - attribute \src "libresoc.v:51525.3-51554.6" - wire $4\do_reset$next[0:0]$3415 - attribute \src "libresoc.v:51495.3-51524.6" - wire $4\do_step$next[0:0]$3408 - attribute \src "libresoc.v:51361.3-51388.6" - wire width 7 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51389.3-51422.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51317.3-51360.6" - wire $4\stopping$next[0:0]$3378 - attribute \src "libresoc.v:51267.3-51316.6" - wire $4\terminated$next[0:0]$3368 - attribute \src "libresoc.v:51555.3-51584.6" - wire $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51525.3-51554.6" - wire $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51495.3-51524.6" - wire $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51317.3-51360.6" - wire $5\stopping$next[0:0]$3379 - attribute \src "libresoc.v:51267.3-51316.6" - wire $5\terminated$next[0:0]$3369 - attribute \src "libresoc.v:51317.3-51360.6" - wire $6\stopping$next[0:0]$3380 - attribute \src "libresoc.v:51267.3-51316.6" - wire $6\terminated$next[0:0]$3370 - attribute \src "libresoc.v:51317.3-51360.6" - wire $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51267.3-51316.6" - wire $7\terminated$next[0:0]$3371 - attribute \src "libresoc.v:51267.3-51316.6" - wire $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51155.19-51155.110" - wire width 3 $add$libresoc.v:51155$3294_Y - attribute \src "libresoc.v:51149.19-51149.103" - wire $and$libresoc.v:51149$3288_Y - attribute \src "libresoc.v:51151.19-51151.113" - wire $and$libresoc.v:51151$3290_Y - attribute \src "libresoc.v:51156.18-51156.110" - wire $and$libresoc.v:51156$3295_Y - attribute \src "libresoc.v:51158.19-51158.103" - wire $and$libresoc.v:51158$3297_Y - attribute \src "libresoc.v:51160.19-51160.102" - wire $and$libresoc.v:51160$3299_Y - attribute \src "libresoc.v:51166.18-51166.101" - wire $and$libresoc.v:51166$3305_Y - attribute \src "libresoc.v:51168.18-51168.111" - wire $and$libresoc.v:51168$3307_Y - attribute \src "libresoc.v:51173.18-51173.101" - wire $and$libresoc.v:51173$3312_Y - attribute \src "libresoc.v:51176.18-51176.111" - wire $and$libresoc.v:51176$3315_Y - attribute \src "libresoc.v:51181.18-51181.101" - wire $and$libresoc.v:51181$3320_Y - attribute \src "libresoc.v:51183.18-51183.111" - wire $and$libresoc.v:51183$3322_Y - attribute \src "libresoc.v:51189.18-51189.101" - wire $and$libresoc.v:51189$3328_Y - attribute \src "libresoc.v:51191.18-51191.111" - wire $and$libresoc.v:51191$3330_Y - attribute \src "libresoc.v:51196.18-51196.101" - wire $and$libresoc.v:51196$3335_Y - attribute \src "libresoc.v:51197.17-51197.99" - wire $and$libresoc.v:51197$3336_Y - attribute \src "libresoc.v:51199.18-51199.111" - wire $and$libresoc.v:51199$3338_Y - attribute \src "libresoc.v:51204.18-51204.101" - wire $and$libresoc.v:51204$3343_Y - attribute \src "libresoc.v:51206.18-51206.111" - wire $and$libresoc.v:51206$3345_Y - attribute \src "libresoc.v:51146.18-51146.103" - wire $eq$libresoc.v:51146$3285_Y - attribute \src "libresoc.v:51147.19-51147.104" - wire $eq$libresoc.v:51147$3286_Y - attribute \src "libresoc.v:51152.19-51152.104" - wire $eq$libresoc.v:51152$3291_Y - attribute \src "libresoc.v:51153.19-51153.104" - wire $eq$libresoc.v:51153$3292_Y - attribute \src "libresoc.v:51154.19-51154.104" - wire $eq$libresoc.v:51154$3293_Y - attribute \src "libresoc.v:51157.19-51157.104" - wire $eq$libresoc.v:51157$3296_Y - attribute \src "libresoc.v:51161.18-51161.103" - wire $eq$libresoc.v:51161$3300_Y - attribute \src "libresoc.v:51162.18-51162.103" - wire $eq$libresoc.v:51162$3301_Y - attribute \src "libresoc.v:51163.18-51163.103" - wire $eq$libresoc.v:51163$3302_Y - attribute \src "libresoc.v:51169.18-51169.103" - wire $eq$libresoc.v:51169$3308_Y - attribute \src "libresoc.v:51170.18-51170.103" - wire $eq$libresoc.v:51170$3309_Y - attribute \src "libresoc.v:51171.18-51171.103" - wire $eq$libresoc.v:51171$3310_Y - attribute \src "libresoc.v:51177.18-51177.103" - wire $eq$libresoc.v:51177$3316_Y - attribute \src "libresoc.v:51178.18-51178.103" - wire $eq$libresoc.v:51178$3317_Y - attribute \src "libresoc.v:51179.18-51179.103" - wire $eq$libresoc.v:51179$3318_Y - attribute \src "libresoc.v:51184.18-51184.103" - wire $eq$libresoc.v:51184$3323_Y - attribute \src "libresoc.v:51185.18-51185.103" - wire $eq$libresoc.v:51185$3324_Y - attribute \src "libresoc.v:51187.18-51187.103" - wire $eq$libresoc.v:51187$3326_Y - attribute \src "libresoc.v:51192.18-51192.103" - wire $eq$libresoc.v:51192$3331_Y - attribute \src "libresoc.v:51193.18-51193.103" - wire $eq$libresoc.v:51193$3332_Y - attribute \src "libresoc.v:51194.18-51194.103" - wire $eq$libresoc.v:51194$3333_Y - attribute \src "libresoc.v:51200.18-51200.103" - wire $eq$libresoc.v:51200$3339_Y - attribute \src "libresoc.v:51201.18-51201.103" - wire $eq$libresoc.v:51201$3340_Y - attribute \src "libresoc.v:51202.18-51202.103" - wire $eq$libresoc.v:51202$3341_Y - attribute \src "libresoc.v:51207.18-51207.103" - wire $eq$libresoc.v:51207$3346_Y - attribute \src "libresoc.v:51145.17-51145.103" - wire $not$libresoc.v:51145$3284_Y - attribute \src "libresoc.v:51148.19-51148.99" - wire $not$libresoc.v:51148$3287_Y - attribute \src "libresoc.v:51150.19-51150.105" - wire $not$libresoc.v:51150$3289_Y - attribute \src "libresoc.v:51159.19-51159.95" - wire $not$libresoc.v:51159$3298_Y - attribute \src "libresoc.v:51165.18-51165.98" - wire $not$libresoc.v:51165$3304_Y - attribute \src "libresoc.v:51167.18-51167.104" - wire $not$libresoc.v:51167$3306_Y - attribute \src "libresoc.v:51172.18-51172.98" - wire $not$libresoc.v:51172$3311_Y - attribute \src "libresoc.v:51174.18-51174.104" - wire $not$libresoc.v:51174$3313_Y - attribute \src "libresoc.v:51180.18-51180.98" - wire $not$libresoc.v:51180$3319_Y - attribute \src "libresoc.v:51182.18-51182.104" - wire $not$libresoc.v:51182$3321_Y - attribute \src "libresoc.v:51186.17-51186.97" - wire $not$libresoc.v:51186$3325_Y - attribute \src "libresoc.v:51188.18-51188.98" - wire $not$libresoc.v:51188$3327_Y - attribute \src "libresoc.v:51190.18-51190.104" - wire $not$libresoc.v:51190$3329_Y - attribute \src "libresoc.v:51195.18-51195.98" - wire $not$libresoc.v:51195$3334_Y - attribute \src "libresoc.v:51198.18-51198.104" - wire $not$libresoc.v:51198$3337_Y - attribute \src "libresoc.v:51203.18-51203.98" - wire $not$libresoc.v:51203$3342_Y - attribute \src "libresoc.v:51205.18-51205.104" - wire $not$libresoc.v:51205$3344_Y - attribute \src "libresoc.v:51164.17-51164.126" - wire width 64 $pos$libresoc.v:51164$3303_Y - attribute \src "libresoc.v:51175.17-51175.245" - wire width 64 $pos$libresoc.v:51175$3314_Y + attribute \src "libresoc.v:51688.3-51721.6" + wire $2\do_dmi_log_rd$next[0:0]$3443 + attribute \src "libresoc.v:51658.3-51687.6" + wire $2\do_icreset$next[0:0]$3436 + attribute \src "libresoc.v:51628.3-51657.6" + wire $2\do_reset$next[0:0]$3429 + attribute \src "libresoc.v:51598.3-51627.6" + wire $2\do_step$next[0:0]$3422 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $2\gspr_index$next[6:0]$3401 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3407 + attribute \src "libresoc.v:51420.3-51463.6" + wire $2\stopping$next[0:0]$3392 + attribute \src "libresoc.v:51370.3-51419.6" + wire $2\terminated$next[0:0]$3382 + attribute \src "libresoc.v:51688.3-51721.6" + wire $3\do_dmi_log_rd$next[0:0]$3444 + attribute \src "libresoc.v:51658.3-51687.6" + wire $3\do_icreset$next[0:0]$3437 + attribute \src "libresoc.v:51628.3-51657.6" + wire $3\do_reset$next[0:0]$3430 + attribute \src "libresoc.v:51598.3-51627.6" + wire $3\do_step$next[0:0]$3423 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $3\gspr_index$next[6:0]$3402 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3408 + attribute \src "libresoc.v:51420.3-51463.6" + wire $3\stopping$next[0:0]$3393 + attribute \src "libresoc.v:51370.3-51419.6" + wire $3\terminated$next[0:0]$3383 + attribute \src "libresoc.v:51688.3-51721.6" + wire $4\do_dmi_log_rd$next[0:0]$3445 + attribute \src "libresoc.v:51658.3-51687.6" + wire $4\do_icreset$next[0:0]$3438 + attribute \src "libresoc.v:51628.3-51657.6" + wire $4\do_reset$next[0:0]$3431 + attribute \src "libresoc.v:51598.3-51627.6" + wire $4\do_step$next[0:0]$3424 + attribute \src "libresoc.v:51464.3-51491.6" + wire width 7 $4\gspr_index$next[6:0]$3403 + attribute \src "libresoc.v:51492.3-51525.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3409 + attribute \src "libresoc.v:51420.3-51463.6" + wire $4\stopping$next[0:0]$3394 + attribute \src "libresoc.v:51370.3-51419.6" + wire $4\terminated$next[0:0]$3384 + attribute \src "libresoc.v:51658.3-51687.6" + wire $5\do_icreset$next[0:0]$3439 + attribute \src "libresoc.v:51628.3-51657.6" + wire $5\do_reset$next[0:0]$3432 + attribute \src "libresoc.v:51598.3-51627.6" + wire $5\do_step$next[0:0]$3425 + attribute \src "libresoc.v:51420.3-51463.6" + wire $5\stopping$next[0:0]$3395 + attribute \src "libresoc.v:51370.3-51419.6" + wire $5\terminated$next[0:0]$3385 + attribute \src "libresoc.v:51420.3-51463.6" + wire $6\stopping$next[0:0]$3396 + attribute \src "libresoc.v:51370.3-51419.6" + wire $6\terminated$next[0:0]$3386 + attribute \src "libresoc.v:51420.3-51463.6" + wire $7\stopping$next[0:0]$3397 + attribute \src "libresoc.v:51370.3-51419.6" + wire $7\terminated$next[0:0]$3387 + attribute \src "libresoc.v:51370.3-51419.6" + wire $8\terminated$next[0:0]$3388 + attribute \src "libresoc.v:51258.19-51258.110" + wire width 3 $add$libresoc.v:51258$3310_Y + attribute \src "libresoc.v:51252.19-51252.103" + wire $and$libresoc.v:51252$3304_Y + attribute \src "libresoc.v:51254.19-51254.113" + wire $and$libresoc.v:51254$3306_Y + attribute \src "libresoc.v:51259.18-51259.110" + wire $and$libresoc.v:51259$3311_Y + attribute \src "libresoc.v:51261.19-51261.103" + wire $and$libresoc.v:51261$3313_Y + attribute \src "libresoc.v:51263.19-51263.102" + wire $and$libresoc.v:51263$3315_Y + attribute \src "libresoc.v:51269.18-51269.101" + wire $and$libresoc.v:51269$3321_Y + attribute \src "libresoc.v:51271.18-51271.111" + wire $and$libresoc.v:51271$3323_Y + attribute \src "libresoc.v:51276.18-51276.101" + wire $and$libresoc.v:51276$3328_Y + attribute \src "libresoc.v:51279.18-51279.111" + wire $and$libresoc.v:51279$3331_Y + attribute \src "libresoc.v:51284.18-51284.101" + wire $and$libresoc.v:51284$3336_Y + attribute \src "libresoc.v:51286.18-51286.111" + wire $and$libresoc.v:51286$3338_Y + attribute \src "libresoc.v:51292.18-51292.101" + wire $and$libresoc.v:51292$3344_Y + attribute \src "libresoc.v:51294.18-51294.111" + wire $and$libresoc.v:51294$3346_Y + attribute \src "libresoc.v:51299.18-51299.101" + wire $and$libresoc.v:51299$3351_Y + attribute \src "libresoc.v:51300.17-51300.99" + wire $and$libresoc.v:51300$3352_Y + attribute \src "libresoc.v:51302.18-51302.111" + wire $and$libresoc.v:51302$3354_Y + attribute \src "libresoc.v:51307.18-51307.101" + wire $and$libresoc.v:51307$3359_Y + attribute \src "libresoc.v:51309.18-51309.111" + wire $and$libresoc.v:51309$3361_Y + attribute \src "libresoc.v:51249.18-51249.103" + wire $eq$libresoc.v:51249$3301_Y + attribute \src "libresoc.v:51250.19-51250.104" + wire $eq$libresoc.v:51250$3302_Y + attribute \src "libresoc.v:51255.19-51255.104" + wire $eq$libresoc.v:51255$3307_Y + attribute \src "libresoc.v:51256.19-51256.104" + wire $eq$libresoc.v:51256$3308_Y + attribute \src "libresoc.v:51257.19-51257.104" + wire $eq$libresoc.v:51257$3309_Y + attribute \src "libresoc.v:51260.19-51260.104" + wire $eq$libresoc.v:51260$3312_Y + attribute \src "libresoc.v:51264.18-51264.103" + wire $eq$libresoc.v:51264$3316_Y + attribute \src "libresoc.v:51265.18-51265.103" + wire $eq$libresoc.v:51265$3317_Y + attribute \src "libresoc.v:51266.18-51266.103" + wire $eq$libresoc.v:51266$3318_Y + attribute \src "libresoc.v:51272.18-51272.103" + wire $eq$libresoc.v:51272$3324_Y + attribute \src "libresoc.v:51273.18-51273.103" + wire $eq$libresoc.v:51273$3325_Y + attribute \src "libresoc.v:51274.18-51274.103" + wire $eq$libresoc.v:51274$3326_Y + attribute \src "libresoc.v:51280.18-51280.103" + wire $eq$libresoc.v:51280$3332_Y + attribute \src "libresoc.v:51281.18-51281.103" + wire $eq$libresoc.v:51281$3333_Y + attribute \src "libresoc.v:51282.18-51282.103" + wire $eq$libresoc.v:51282$3334_Y + attribute \src "libresoc.v:51287.18-51287.103" + wire $eq$libresoc.v:51287$3339_Y + attribute \src "libresoc.v:51288.18-51288.103" + wire $eq$libresoc.v:51288$3340_Y + attribute \src "libresoc.v:51290.18-51290.103" + wire $eq$libresoc.v:51290$3342_Y + attribute \src "libresoc.v:51295.18-51295.103" + wire $eq$libresoc.v:51295$3347_Y + attribute \src "libresoc.v:51296.18-51296.103" + wire $eq$libresoc.v:51296$3348_Y + attribute \src "libresoc.v:51297.18-51297.103" + wire $eq$libresoc.v:51297$3349_Y + attribute \src "libresoc.v:51303.18-51303.103" + wire $eq$libresoc.v:51303$3355_Y + attribute \src "libresoc.v:51304.18-51304.103" + wire $eq$libresoc.v:51304$3356_Y + attribute \src "libresoc.v:51305.18-51305.103" + wire $eq$libresoc.v:51305$3357_Y + attribute \src "libresoc.v:51310.18-51310.103" + wire $eq$libresoc.v:51310$3362_Y + attribute \src "libresoc.v:51248.17-51248.103" + wire $not$libresoc.v:51248$3300_Y + attribute \src "libresoc.v:51251.19-51251.99" + wire $not$libresoc.v:51251$3303_Y + attribute \src "libresoc.v:51253.19-51253.105" + wire $not$libresoc.v:51253$3305_Y + attribute \src "libresoc.v:51262.19-51262.95" + wire $not$libresoc.v:51262$3314_Y + attribute \src "libresoc.v:51268.18-51268.98" + wire $not$libresoc.v:51268$3320_Y + attribute \src "libresoc.v:51270.18-51270.104" + wire $not$libresoc.v:51270$3322_Y + attribute \src "libresoc.v:51275.18-51275.98" + wire $not$libresoc.v:51275$3327_Y + attribute \src "libresoc.v:51277.18-51277.104" + wire $not$libresoc.v:51277$3329_Y + attribute \src "libresoc.v:51283.18-51283.98" + wire $not$libresoc.v:51283$3335_Y + attribute \src "libresoc.v:51285.18-51285.104" + wire $not$libresoc.v:51285$3337_Y + attribute \src "libresoc.v:51289.17-51289.97" + wire $not$libresoc.v:51289$3341_Y + attribute \src "libresoc.v:51291.18-51291.98" + wire $not$libresoc.v:51291$3343_Y + attribute \src "libresoc.v:51293.18-51293.104" + wire $not$libresoc.v:51293$3345_Y + attribute \src "libresoc.v:51298.18-51298.98" + wire $not$libresoc.v:51298$3350_Y + attribute \src "libresoc.v:51301.18-51301.104" + wire $not$libresoc.v:51301$3353_Y + attribute \src "libresoc.v:51306.18-51306.98" + wire $not$libresoc.v:51306$3358_Y + attribute \src "libresoc.v:51308.18-51308.104" + wire $not$libresoc.v:51308$3360_Y + attribute \src "libresoc.v:51267.17-51267.126" + wire width 64 $pos$libresoc.v:51267$3319_Y + attribute \src "libresoc.v:51278.17-51278.245" + wire width 64 $pos$libresoc.v:51278$3330_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90374,7 +90630,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90464,7 +90720,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:50897.7-50897.15" + attribute \src "libresoc.v:51000.7-51000.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90474,7 +90730,7 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg @@ -90491,7 +90747,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:51155$3294 + cell $add $add$libresoc.v:51258$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90499,10 +90755,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51155$3294_Y + connect \Y $add$libresoc.v:51258$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51149$3288 + cell $and $and$libresoc.v:51252$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90510,10 +90766,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:51149$3288_Y + connect \Y $and$libresoc.v:51252$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51151$3290 + cell $and $and$libresoc.v:51254$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90521,10 +90777,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:51151$3290_Y + connect \Y $and$libresoc.v:51254$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51156$3295 + cell $and $and$libresoc.v:51259$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90532,10 +90788,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:51156$3295_Y + connect \Y $and$libresoc.v:51259$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:51158$3297 + cell $and $and$libresoc.v:51261$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90543,10 +90799,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:51158$3297_Y + connect \Y $and$libresoc.v:51261$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:51160$3299 + cell $and $and$libresoc.v:51263$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90554,10 +90810,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:51160$3299_Y + connect \Y $and$libresoc.v:51263$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51166$3305 + cell $and $and$libresoc.v:51269$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90565,10 +90821,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:51166$3305_Y + connect \Y $and$libresoc.v:51269$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51168$3307 + cell $and $and$libresoc.v:51271$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90576,10 +90832,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:51168$3307_Y + connect \Y $and$libresoc.v:51271$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51173$3312 + cell $and $and$libresoc.v:51276$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90587,10 +90843,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:51173$3312_Y + connect \Y $and$libresoc.v:51276$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51176$3315 + cell $and $and$libresoc.v:51279$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90598,10 +90854,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:51176$3315_Y + connect \Y $and$libresoc.v:51279$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51181$3320 + cell $and $and$libresoc.v:51284$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90609,10 +90865,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:51181$3320_Y + connect \Y $and$libresoc.v:51284$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51183$3322 + cell $and $and$libresoc.v:51286$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90620,10 +90876,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:51183$3322_Y + connect \Y $and$libresoc.v:51286$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51189$3328 + cell $and $and$libresoc.v:51292$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90631,10 +90887,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:51189$3328_Y + connect \Y $and$libresoc.v:51292$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51191$3330 + cell $and $and$libresoc.v:51294$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90642,10 +90898,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:51191$3330_Y + connect \Y $and$libresoc.v:51294$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51196$3335 + cell $and $and$libresoc.v:51299$3351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90653,10 +90909,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:51196$3335_Y + connect \Y $and$libresoc.v:51299$3351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51197$3336 + cell $and $and$libresoc.v:51300$3352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90664,10 +90920,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:51197$3336_Y + connect \Y $and$libresoc.v:51300$3352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51199$3338 + cell $and $and$libresoc.v:51302$3354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90675,10 +90931,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:51199$3338_Y + connect \Y $and$libresoc.v:51302$3354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51204$3343 + cell $and $and$libresoc.v:51307$3359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90686,10 +90942,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:51204$3343_Y + connect \Y $and$libresoc.v:51307$3359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51206$3345 + cell $and $and$libresoc.v:51309$3361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90697,10 +90953,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:51206$3345_Y + connect \Y $and$libresoc.v:51309$3361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51146$3285 + cell $eq $eq$libresoc.v:51249$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90708,10 +90964,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51146$3285_Y + connect \Y $eq$libresoc.v:51249$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51147$3286 + cell $eq $eq$libresoc.v:51250$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90719,10 +90975,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51147$3286_Y + connect \Y $eq$libresoc.v:51250$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51152$3291 + cell $eq $eq$libresoc.v:51255$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90730,10 +90986,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51152$3291_Y + connect \Y $eq$libresoc.v:51255$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51153$3292 + cell $eq $eq$libresoc.v:51256$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90741,10 +90997,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51153$3292_Y + connect \Y $eq$libresoc.v:51256$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51154$3293 + cell $eq $eq$libresoc.v:51257$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90752,10 +91008,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51154$3293_Y + connect \Y $eq$libresoc.v:51257$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:51157$3296 + cell $eq $eq$libresoc.v:51260$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90763,10 +91019,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51157$3296_Y + connect \Y $eq$libresoc.v:51260$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51161$3300 + cell $eq $eq$libresoc.v:51264$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90774,10 +91030,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51161$3300_Y + connect \Y $eq$libresoc.v:51264$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51162$3301 + cell $eq $eq$libresoc.v:51265$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90785,10 +91041,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51162$3301_Y + connect \Y $eq$libresoc.v:51265$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51163$3302 + cell $eq $eq$libresoc.v:51266$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90796,10 +91052,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51163$3302_Y + connect \Y $eq$libresoc.v:51266$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51169$3308 + cell $eq $eq$libresoc.v:51272$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90807,10 +91063,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51169$3308_Y + connect \Y $eq$libresoc.v:51272$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51170$3309 + cell $eq $eq$libresoc.v:51273$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90818,10 +91074,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51170$3309_Y + connect \Y $eq$libresoc.v:51273$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51171$3310 + cell $eq $eq$libresoc.v:51274$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90829,10 +91085,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51171$3310_Y + connect \Y $eq$libresoc.v:51274$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51177$3316 + cell $eq $eq$libresoc.v:51280$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90840,10 +91096,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51177$3316_Y + connect \Y $eq$libresoc.v:51280$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51178$3317 + cell $eq $eq$libresoc.v:51281$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90851,10 +91107,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51178$3317_Y + connect \Y $eq$libresoc.v:51281$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51179$3318 + cell $eq $eq$libresoc.v:51282$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90862,10 +91118,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51179$3318_Y + connect \Y $eq$libresoc.v:51282$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51184$3323 + cell $eq $eq$libresoc.v:51287$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90873,10 +91129,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51184$3323_Y + connect \Y $eq$libresoc.v:51287$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51185$3324 + cell $eq $eq$libresoc.v:51288$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90884,10 +91140,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51185$3324_Y + connect \Y $eq$libresoc.v:51288$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51187$3326 + cell $eq $eq$libresoc.v:51290$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90895,10 +91151,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51187$3326_Y + connect \Y $eq$libresoc.v:51290$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51192$3331 + cell $eq $eq$libresoc.v:51295$3347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90906,10 +91162,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51192$3331_Y + connect \Y $eq$libresoc.v:51295$3347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51193$3332 + cell $eq $eq$libresoc.v:51296$3348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90917,10 +91173,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51193$3332_Y + connect \Y $eq$libresoc.v:51296$3348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51194$3333 + cell $eq $eq$libresoc.v:51297$3349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90928,10 +91184,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51194$3333_Y + connect \Y $eq$libresoc.v:51297$3349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51200$3339 + cell $eq $eq$libresoc.v:51303$3355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90939,10 +91195,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51200$3339_Y + connect \Y $eq$libresoc.v:51303$3355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51201$3340 + cell $eq $eq$libresoc.v:51304$3356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90950,10 +91206,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51201$3340_Y + connect \Y $eq$libresoc.v:51304$3356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51202$3341 + cell $eq $eq$libresoc.v:51305$3357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90961,10 +91217,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51202$3341_Y + connect \Y $eq$libresoc.v:51305$3357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51207$3346 + cell $eq $eq$libresoc.v:51310$3362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90972,340 +91228,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51207$3346_Y + connect \Y $eq$libresoc.v:51310$3362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51145$3284 + cell $not $not$libresoc.v:51248$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51145$3284_Y + connect \Y $not$libresoc.v:51248$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51148$3287 + cell $not $not$libresoc.v:51251$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51148$3287_Y + connect \Y $not$libresoc.v:51251$3303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51150$3289 + cell $not $not$libresoc.v:51253$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51150$3289_Y + connect \Y $not$libresoc.v:51253$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:51159$3298 + cell $not $not$libresoc.v:51262$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51159$3298_Y + connect \Y $not$libresoc.v:51262$3314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51165$3304 + cell $not $not$libresoc.v:51268$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51165$3304_Y + connect \Y $not$libresoc.v:51268$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51167$3306 + cell $not $not$libresoc.v:51270$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51167$3306_Y + connect \Y $not$libresoc.v:51270$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51172$3311 + cell $not $not$libresoc.v:51275$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51172$3311_Y + connect \Y $not$libresoc.v:51275$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51174$3313 + cell $not $not$libresoc.v:51277$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51174$3313_Y + connect \Y $not$libresoc.v:51277$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51180$3319 + cell $not $not$libresoc.v:51283$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51180$3319_Y + connect \Y $not$libresoc.v:51283$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51182$3321 + cell $not $not$libresoc.v:51285$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51182$3321_Y + connect \Y $not$libresoc.v:51285$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51186$3325 + cell $not $not$libresoc.v:51289$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51186$3325_Y + connect \Y $not$libresoc.v:51289$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51188$3327 + cell $not $not$libresoc.v:51291$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51188$3327_Y + connect \Y $not$libresoc.v:51291$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51190$3329 + cell $not $not$libresoc.v:51293$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51190$3329_Y + connect \Y $not$libresoc.v:51293$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51195$3334 + cell $not $not$libresoc.v:51298$3350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51195$3334_Y + connect \Y $not$libresoc.v:51298$3350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51198$3337 + cell $not $not$libresoc.v:51301$3353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51198$3337_Y + connect \Y $not$libresoc.v:51301$3353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51203$3342 + cell $not $not$libresoc.v:51306$3358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51203$3342_Y + connect \Y $not$libresoc.v:51306$3358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51205$3344 + cell $not $not$libresoc.v:51308$3360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51205$3344_Y + connect \Y $not$libresoc.v:51308$3360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:51164$3303 + cell $pos $pos$libresoc.v:51267$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51164$3303_Y + connect \Y $pos$libresoc.v:51267$3319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:51175$3314 + cell $pos $pos$libresoc.v:51278$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:51175$3314_Y + connect \Y $pos$libresoc.v:51278$3330_Y end - attribute \src "libresoc.v:50897.7-50897.20" - process $proc$libresoc.v:50897$3430 + attribute \src "libresoc.v:51000.7-51000.20" + process $proc$libresoc.v:51000$3446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51084.7-51084.31" - process $proc$libresoc.v:51084$3431 + attribute \src "libresoc.v:51187.7-51187.31" + process $proc$libresoc.v:51187$3447 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51088.7-51088.33" - process $proc$libresoc.v:51088$3432 + attribute \src "libresoc.v:51191.7-51191.33" + process $proc$libresoc.v:51191$3448 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51094.7-51094.25" - process $proc$libresoc.v:51094$3433 + attribute \src "libresoc.v:51197.7-51197.25" + process $proc$libresoc.v:51197$3449 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51100.7-51100.27" - process $proc$libresoc.v:51100$3434 + attribute \src "libresoc.v:51203.7-51203.27" + process $proc$libresoc.v:51203$3450 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51104.7-51104.24" - process $proc$libresoc.v:51104$3435 + attribute \src "libresoc.v:51207.7-51207.24" + process $proc$libresoc.v:51207$3451 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51108.7-51108.22" - process $proc$libresoc.v:51108$3436 + attribute \src "libresoc.v:51211.7-51211.22" + process $proc$libresoc.v:51211$3452 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51112.7-51112.21" - process $proc$libresoc.v:51112$3437 + attribute \src "libresoc.v:51215.7-51215.21" + process $proc$libresoc.v:51215$3453 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51116.13-51116.31" - process $proc$libresoc.v:51116$3438 + attribute \src "libresoc.v:51219.13-51219.31" + process $proc$libresoc.v:51219$3454 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51122.14-51122.34" - process $proc$libresoc.v:51122$3439 + attribute \src "libresoc.v:51225.14-51225.34" + process $proc$libresoc.v:51225$3455 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51134.7-51134.22" - process $proc$libresoc.v:51134$3440 + attribute \src "libresoc.v:51237.7-51237.22" + process $proc$libresoc.v:51237$3456 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51140.7-51140.24" - process $proc$libresoc.v:51140$3441 + attribute \src "libresoc.v:51243.7-51243.24" + process $proc$libresoc.v:51243$3457 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51208.3-51209.51" - process $proc$libresoc.v:51208$3347 + attribute \src "libresoc.v:51311.3-51312.51" + process $proc$libresoc.v:51311$3363 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51210.3-51211.55" - process $proc$libresoc.v:51210$3348 + attribute \src "libresoc.v:51313.3-51314.55" + process $proc$libresoc.v:51313$3364 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51212.3-51213.41" - process $proc$libresoc.v:51212$3349 + attribute \src "libresoc.v:51315.3-51316.41" + process $proc$libresoc.v:51315$3365 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51214.3-51215.37" - process $proc$libresoc.v:51214$3350 + attribute \src "libresoc.v:51317.3-51318.37" + process $proc$libresoc.v:51317$3366 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51216.3-51217.33" - process $proc$libresoc.v:51216$3351 + attribute \src "libresoc.v:51319.3-51320.33" + process $proc$libresoc.v:51319$3367 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51218.3-51219.37" - process $proc$libresoc.v:51218$3352 + attribute \src "libresoc.v:51321.3-51322.37" + process $proc$libresoc.v:51321$3368 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51220.3-51221.39" - process $proc$libresoc.v:51220$3353 + attribute \src "libresoc.v:51323.3-51324.39" + process $proc$libresoc.v:51323$3369 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51222.3-51223.43" - process $proc$libresoc.v:51222$3354 + attribute \src "libresoc.v:51325.3-51326.43" + process $proc$libresoc.v:51325$3370 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51224.3-51225.37" - process $proc$libresoc.v:51224$3355 + attribute \src "libresoc.v:51327.3-51328.37" + process $proc$libresoc.v:51327$3371 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51226.3-51227.33" - process $proc$libresoc.v:51226$3356 + attribute \src "libresoc.v:51329.3-51330.33" + process $proc$libresoc.v:51329$3372 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51228.3-51229.31" - process $proc$libresoc.v:51228$3357 + attribute \src "libresoc.v:51331.3-51332.31" + process $proc$libresoc.v:51331$3373 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51230.3-51247.6" - process $proc$libresoc.v:51230$3358 + attribute \src "libresoc.v:51333.3-51350.6" + process $proc$libresoc.v:51333$3374 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51231.5-51231.29" + attribute \src "libresoc.v:51334.5-51334.29" switch \initial - attribute \src "libresoc.v:51231.9-51231.17" + attribute \src "libresoc.v:51334.9-51334.17" case 1'1 case end @@ -91331,14 +91587,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51248.3-51257.6" - process $proc$libresoc.v:51248$3359 + attribute \src "libresoc.v:51351.3-51360.6" + process $proc$libresoc.v:51351$3375 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51249.5-51249.29" + attribute \src "libresoc.v:51352.5-51352.29" switch \initial - attribute \src "libresoc.v:51249.9-51249.17" + attribute \src "libresoc.v:51352.9-51352.17" case 1'1 case end @@ -91354,14 +91610,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51258.3-51266.6" - process $proc$libresoc.v:51258$3360 + attribute \src "libresoc.v:51361.3-51369.6" + process $proc$libresoc.v:51361$3376 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 - attribute \src "libresoc.v:51259.5-51259.29" + assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378 + attribute \src "libresoc.v:51362.5-51362.29" switch \initial - attribute \src "libresoc.v:51259.9-51259.17" + attribute \src "libresoc.v:51362.9-51362.17" case 1'1 case end @@ -91370,23 +91626,23 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3362 1'0 + assign $1\dmi_req_i_1$next[0:0]$3378 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3378 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377 end - attribute \src "libresoc.v:51267.3-51316.6" - process $proc$libresoc.v:51267$3363 + attribute \src "libresoc.v:51370.3-51419.6" + process $proc$libresoc.v:51370$3379 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 - attribute \src "libresoc.v:51268.5-51268.29" + assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388 + attribute \src "libresoc.v:51371.5-51371.29" switch \initial - attribute \src "libresoc.v:51268.9-51268.17" + attribute \src "libresoc.v:51371.9-51371.17" case 1'1 case end @@ -91395,13 +91651,13 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366 + assign $1\terminated$next[0:0]$3381 $2\terminated$next[0:0]$3382 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367 + assign $2\terminated$next[0:0]$3382 $3\terminated$next[0:0]$3383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$73 \$71 \$69 } attribute \src "libresoc.v:0.0-0.0" @@ -91409,74 +91665,74 @@ module \dbg assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370 + assign $3\terminated$next[0:0]$3383 $6\terminated$next[0:0]$3386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3368 1'0 + assign $4\terminated$next[0:0]$3384 1'0 case - assign $4\terminated$next[0:0]$3368 \terminated + assign $4\terminated$next[0:0]$3384 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3369 1'0 + assign $5\terminated$next[0:0]$3385 1'0 case - assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368 + assign $5\terminated$next[0:0]$3385 $4\terminated$next[0:0]$3384 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3370 1'0 + assign $6\terminated$next[0:0]$3386 1'0 case - assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369 + assign $6\terminated$next[0:0]$3386 $5\terminated$next[0:0]$3385 end case - assign $3\terminated$next[0:0]$3367 \terminated + assign $3\terminated$next[0:0]$3383 \terminated end case - assign $2\terminated$next[0:0]$3366 \terminated + assign $2\terminated$next[0:0]$3382 \terminated end case - assign $1\terminated$next[0:0]$3365 \terminated + assign $1\terminated$next[0:0]$3381 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3371 1'1 + assign $7\terminated$next[0:0]$3387 1'1 case - assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365 + assign $7\terminated$next[0:0]$3387 $1\terminated$next[0:0]$3381 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3372 1'0 + assign $8\terminated$next[0:0]$3388 1'0 case - assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371 + assign $8\terminated$next[0:0]$3388 $7\terminated$next[0:0]$3387 end sync always - update \terminated$next $0\terminated$next[0:0]$3364 + update \terminated$next $0\terminated$next[0:0]$3380 end - attribute \src "libresoc.v:51317.3-51360.6" - process $proc$libresoc.v:51317$3373 + attribute \src "libresoc.v:51420.3-51463.6" + process $proc$libresoc.v:51420$3389 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 - attribute \src "libresoc.v:51318.5-51318.29" + assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397 + attribute \src "libresoc.v:51421.5-51421.29" switch \initial - attribute \src "libresoc.v:51318.9-51318.17" + attribute \src "libresoc.v:51421.9-51421.17" case 1'1 case end @@ -91485,77 +91741,77 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376 + assign $1\stopping$next[0:0]$3391 $2\stopping$next[0:0]$3392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377 + assign $2\stopping$next[0:0]$3392 $3\stopping$next[0:0]$3393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$87 \$85 \$83 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379 + assign $3\stopping$next[0:0]$3393 $5\stopping$next[0:0]$3395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3378 1'1 + assign $4\stopping$next[0:0]$3394 1'1 case - assign $4\stopping$next[0:0]$3378 \stopping + assign $4\stopping$next[0:0]$3394 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3379 1'0 + assign $5\stopping$next[0:0]$3395 1'0 case - assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378 + assign $5\stopping$next[0:0]$3395 $4\stopping$next[0:0]$3394 end case - assign $3\stopping$next[0:0]$3377 \stopping + assign $3\stopping$next[0:0]$3393 \stopping end case - assign $2\stopping$next[0:0]$3376 \stopping + assign $2\stopping$next[0:0]$3392 \stopping end case - assign $1\stopping$next[0:0]$3375 \stopping + assign $1\stopping$next[0:0]$3391 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3380 1'1 + assign $6\stopping$next[0:0]$3396 1'1 case - assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375 + assign $6\stopping$next[0:0]$3396 $1\stopping$next[0:0]$3391 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3381 1'0 + assign $7\stopping$next[0:0]$3397 1'0 case - assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380 + assign $7\stopping$next[0:0]$3397 $6\stopping$next[0:0]$3396 end sync always - update \stopping$next $0\stopping$next[0:0]$3374 + update \stopping$next $0\stopping$next[0:0]$3390 end - attribute \src "libresoc.v:51361.3-51388.6" - process $proc$libresoc.v:51361$3382 + attribute \src "libresoc.v:51464.3-51491.6" + process $proc$libresoc.v:51464$3398 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 - attribute \src "libresoc.v:51362.5-51362.29" + assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403 + attribute \src "libresoc.v:51465.5-51465.29" switch \initial - attribute \src "libresoc.v:51362.9-51362.17" + attribute \src "libresoc.v:51465.9-51465.17" case 1'1 case end @@ -91564,52 +91820,52 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385 + assign $1\gspr_index$next[6:0]$3400 $2\gspr_index$next[6:0]$3401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386 + assign $2\gspr_index$next[6:0]$3401 $3\gspr_index$next[6:0]$3402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$101 \$99 \$97 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3386 \gspr_index + assign $3\gspr_index$next[6:0]$3402 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3402 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3386 \gspr_index + assign $3\gspr_index$next[6:0]$3402 \gspr_index end case - assign $2\gspr_index$next[6:0]$3385 \gspr_index + assign $2\gspr_index$next[6:0]$3401 \gspr_index end case - assign $1\gspr_index$next[6:0]$3384 \gspr_index + assign $1\gspr_index$next[6:0]$3400 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3387 7'0000000 + assign $4\gspr_index$next[6:0]$3403 7'0000000 case - assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384 + assign $4\gspr_index$next[6:0]$3403 $1\gspr_index$next[6:0]$3400 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3383 + update \gspr_index$next $0\gspr_index$next[6:0]$3399 end - attribute \src "libresoc.v:51389.3-51422.6" - process $proc$libresoc.v:51389$3388 + attribute \src "libresoc.v:51492.3-51525.6" + process $proc$libresoc.v:51492$3404 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 - attribute \src "libresoc.v:51390.5-51390.29" + assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409 + attribute \src "libresoc.v:51493.5-51493.29" switch \initial - attribute \src "libresoc.v:51390.9-51390.17" + attribute \src "libresoc.v:51493.9-51493.17" case 1'1 case end @@ -91618,58 +91874,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391 + assign $1\log_dmi_addr$next[31:0]$3406 $2\log_dmi_addr$next[31:0]$3407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392 + assign $2\log_dmi_addr$next[31:0]$3407 $3\log_dmi_addr$next[31:0]$3408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$115 \$113 \$111 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3408 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3408 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3407 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0] + assign $1\log_dmi_addr$next[31:0]$3406 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3406 [1:0] \$117 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3406 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3393 0 + assign $4\log_dmi_addr$next[31:0]$3409 0 case - assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390 + assign $4\log_dmi_addr$next[31:0]$3409 $1\log_dmi_addr$next[31:0]$3406 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405 end - attribute \src "libresoc.v:51423.3-51431.6" - process $proc$libresoc.v:51423$3394 + attribute \src "libresoc.v:51526.3-51534.6" + process $proc$libresoc.v:51526$3410 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 - attribute \src "libresoc.v:51424.5-51424.29" + assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412 + attribute \src "libresoc.v:51527.5-51527.29" switch \initial - attribute \src "libresoc.v:51424.9-51424.17" + attribute \src "libresoc.v:51527.9-51527.17" case 1'1 case end @@ -91678,21 +91934,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3412 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3412 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411 end - attribute \src "libresoc.v:51432.3-51440.6" - process $proc$libresoc.v:51432$3397 + attribute \src "libresoc.v:51535.3-51543.6" + process $proc$libresoc.v:51535$3413 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 - attribute \src "libresoc.v:51433.5-51433.29" + assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415 + attribute \src "libresoc.v:51536.5-51536.29" switch \initial - attribute \src "libresoc.v:51433.9-51433.17" + attribute \src "libresoc.v:51536.9-51536.17" case 1'1 case end @@ -91701,21 +91957,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3399 1'0 + assign $1\dmi_read_log_data$next[0:0]$3415 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3399 \$122 + assign $1\dmi_read_log_data$next[0:0]$3415 \$122 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414 end - attribute \src "libresoc.v:51441.3-51450.6" - process $proc$libresoc.v:51441$3400 + attribute \src "libresoc.v:51544.3-51553.6" + process $proc$libresoc.v:51544$3416 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51442.5-51442.29" + attribute \src "libresoc.v:51545.5-51545.29" switch \initial - attribute \src "libresoc.v:51442.9-51442.17" + attribute \src "libresoc.v:51545.9-51545.17" case 1'1 case end @@ -91731,14 +91987,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51451.3-51460.6" - process $proc$libresoc.v:51451$3401 + attribute \src "libresoc.v:51554.3-51563.6" + process $proc$libresoc.v:51554$3417 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51452.5-51452.29" + attribute \src "libresoc.v:51555.5-51555.29" switch \initial - attribute \src "libresoc.v:51452.9-51452.17" + attribute \src "libresoc.v:51555.9-51555.17" case 1'1 case end @@ -91754,14 +92010,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51461.3-51494.6" - process $proc$libresoc.v:51461$3402 + attribute \src "libresoc.v:51564.3-51597.6" + process $proc$libresoc.v:51564$3418 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51462.5-51462.29" + attribute \src "libresoc.v:51565.5-51565.29" switch \initial - attribute \src "libresoc.v:51462.9-51462.17" + attribute \src "libresoc.v:51565.9-51565.17" case 1'1 case end @@ -91809,15 +92065,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51495.3-51524.6" - process $proc$libresoc.v:51495$3403 + attribute \src "libresoc.v:51598.3-51627.6" + process $proc$libresoc.v:51598$3419 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 - attribute \src "libresoc.v:51496.5-51496.29" + assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425 + attribute \src "libresoc.v:51599.5-51599.29" switch \initial - attribute \src "libresoc.v:51496.9-51496.17" + attribute \src "libresoc.v:51599.9-51599.17" case 1'1 case end @@ -91826,58 +92082,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406 + assign $1\do_step$next[0:0]$3421 $2\do_step$next[0:0]$3422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407 + assign $2\do_step$next[0:0]$3422 $3\do_step$next[0:0]$3423 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$17 \$15 \$13 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408 + assign $3\do_step$next[0:0]$3423 $4\do_step$next[0:0]$3424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3408 1'1 + assign $4\do_step$next[0:0]$3424 1'1 case - assign $4\do_step$next[0:0]$3408 1'0 + assign $4\do_step$next[0:0]$3424 1'0 end case - assign $3\do_step$next[0:0]$3407 1'0 + assign $3\do_step$next[0:0]$3423 1'0 end case - assign $2\do_step$next[0:0]$3406 1'0 + assign $2\do_step$next[0:0]$3422 1'0 end case - assign $1\do_step$next[0:0]$3405 1'0 + assign $1\do_step$next[0:0]$3421 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3409 1'0 + assign $5\do_step$next[0:0]$3425 1'0 case - assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405 + assign $5\do_step$next[0:0]$3425 $1\do_step$next[0:0]$3421 end sync always - update \do_step$next $0\do_step$next[0:0]$3404 + update \do_step$next $0\do_step$next[0:0]$3420 end - attribute \src "libresoc.v:51525.3-51554.6" - process $proc$libresoc.v:51525$3410 + attribute \src "libresoc.v:51628.3-51657.6" + process $proc$libresoc.v:51628$3426 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:51526.5-51526.29" + assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432 + attribute \src "libresoc.v:51629.5-51629.29" switch \initial - attribute \src "libresoc.v:51526.9-51526.17" + attribute \src "libresoc.v:51629.9-51629.17" case 1'1 case end @@ -91886,58 +92142,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413 + assign $1\do_reset$next[0:0]$3428 $2\do_reset$next[0:0]$3429 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414 + assign $2\do_reset$next[0:0]$3429 $3\do_reset$next[0:0]$3430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$31 \$29 \$27 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415 + assign $3\do_reset$next[0:0]$3430 $4\do_reset$next[0:0]$3431 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3415 1'1 + assign $4\do_reset$next[0:0]$3431 1'1 case - assign $4\do_reset$next[0:0]$3415 1'0 + assign $4\do_reset$next[0:0]$3431 1'0 end case - assign $3\do_reset$next[0:0]$3414 1'0 + assign $3\do_reset$next[0:0]$3430 1'0 end case - assign $2\do_reset$next[0:0]$3413 1'0 + assign $2\do_reset$next[0:0]$3429 1'0 end case - assign $1\do_reset$next[0:0]$3412 1'0 + assign $1\do_reset$next[0:0]$3428 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3416 1'0 + assign $5\do_reset$next[0:0]$3432 1'0 case - assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412 + assign $5\do_reset$next[0:0]$3432 $1\do_reset$next[0:0]$3428 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3411 + update \do_reset$next $0\do_reset$next[0:0]$3427 end - attribute \src "libresoc.v:51555.3-51584.6" - process $proc$libresoc.v:51555$3417 + attribute \src "libresoc.v:51658.3-51687.6" + process $proc$libresoc.v:51658$3433 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:51556.5-51556.29" + assign $0\do_icreset$next[0:0]$3434 $5\do_icreset$next[0:0]$3439 + attribute \src "libresoc.v:51659.5-51659.29" switch \initial - attribute \src "libresoc.v:51556.9-51556.17" + attribute \src "libresoc.v:51659.9-51659.17" case 1'1 case end @@ -91946,58 +92202,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420 + assign $1\do_icreset$next[0:0]$3435 $2\do_icreset$next[0:0]$3436 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421 + assign $2\do_icreset$next[0:0]$3436 $3\do_icreset$next[0:0]$3437 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$45 \$43 \$41 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422 + assign $3\do_icreset$next[0:0]$3437 $4\do_icreset$next[0:0]$3438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3422 1'1 + assign $4\do_icreset$next[0:0]$3438 1'1 case - assign $4\do_icreset$next[0:0]$3422 1'0 + assign $4\do_icreset$next[0:0]$3438 1'0 end case - assign $3\do_icreset$next[0:0]$3421 1'0 + assign $3\do_icreset$next[0:0]$3437 1'0 end case - assign $2\do_icreset$next[0:0]$3420 1'0 + assign $2\do_icreset$next[0:0]$3436 1'0 end case - assign $1\do_icreset$next[0:0]$3419 1'0 + assign $1\do_icreset$next[0:0]$3435 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3423 1'0 + assign $5\do_icreset$next[0:0]$3439 1'0 case - assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419 + assign $5\do_icreset$next[0:0]$3439 $1\do_icreset$next[0:0]$3435 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3418 + update \do_icreset$next $0\do_icreset$next[0:0]$3434 end - attribute \src "libresoc.v:51585.3-51618.6" - process $proc$libresoc.v:51585$3424 + attribute \src "libresoc.v:51688.3-51721.6" + process $proc$libresoc.v:51688$3440 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 - attribute \src "libresoc.v:51586.5-51586.29" + assign $0\do_dmi_log_rd$next[0:0]$3441 $4\do_dmi_log_rd$next[0:0]$3445 + attribute \src "libresoc.v:51689.5-51689.29" switch \initial - attribute \src "libresoc.v:51586.9-51586.17" + attribute \src "libresoc.v:51689.9-51689.17" case 1'1 case end @@ -92006,113 +92262,113 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427 + assign $1\do_dmi_log_rd$next[0:0]$3442 $2\do_dmi_log_rd$next[0:0]$3443 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428 + assign $2\do_dmi_log_rd$next[0:0]$3443 $3\do_dmi_log_rd$next[0:0]$3444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$59 \$57 \$55 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3428 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3444 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3427 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3443 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3426 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3442 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3426 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3442 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3429 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 - end - connect \$9 $not$libresoc.v:51145$3284_Y - connect \$99 $eq$libresoc.v:51146$3285_Y - connect \$101 $eq$libresoc.v:51147$3286_Y - connect \$103 $not$libresoc.v:51148$3287_Y - connect \$105 $and$libresoc.v:51149$3288_Y - connect \$107 $not$libresoc.v:51150$3289_Y - connect \$109 $and$libresoc.v:51151$3290_Y - connect \$111 $eq$libresoc.v:51152$3291_Y - connect \$113 $eq$libresoc.v:51153$3292_Y - connect \$115 $eq$libresoc.v:51154$3293_Y - connect \$118 $add$libresoc.v:51155$3294_Y - connect \$11 $and$libresoc.v:51156$3295_Y - connect \$120 $eq$libresoc.v:51157$3296_Y - connect \$122 $and$libresoc.v:51158$3297_Y - connect \$124 $not$libresoc.v:51159$3298_Y - connect \$126 $and$libresoc.v:51160$3299_Y - connect \$13 $eq$libresoc.v:51161$3300_Y - connect \$15 $eq$libresoc.v:51162$3301_Y - connect \$17 $eq$libresoc.v:51163$3302_Y - connect \$1 $pos$libresoc.v:51164$3303_Y - connect \$19 $not$libresoc.v:51165$3304_Y - connect \$21 $and$libresoc.v:51166$3305_Y - connect \$23 $not$libresoc.v:51167$3306_Y - connect \$25 $and$libresoc.v:51168$3307_Y - connect \$27 $eq$libresoc.v:51169$3308_Y - connect \$29 $eq$libresoc.v:51170$3309_Y - connect \$31 $eq$libresoc.v:51171$3310_Y - connect \$33 $not$libresoc.v:51172$3311_Y - connect \$35 $and$libresoc.v:51173$3312_Y - connect \$37 $not$libresoc.v:51174$3313_Y - connect \$3 $pos$libresoc.v:51175$3314_Y - connect \$39 $and$libresoc.v:51176$3315_Y - connect \$41 $eq$libresoc.v:51177$3316_Y - connect \$43 $eq$libresoc.v:51178$3317_Y - connect \$45 $eq$libresoc.v:51179$3318_Y - connect \$47 $not$libresoc.v:51180$3319_Y - connect \$49 $and$libresoc.v:51181$3320_Y - connect \$51 $not$libresoc.v:51182$3321_Y - connect \$53 $and$libresoc.v:51183$3322_Y - connect \$55 $eq$libresoc.v:51184$3323_Y - connect \$57 $eq$libresoc.v:51185$3324_Y - connect \$5 $not$libresoc.v:51186$3325_Y - connect \$59 $eq$libresoc.v:51187$3326_Y - connect \$61 $not$libresoc.v:51188$3327_Y - connect \$63 $and$libresoc.v:51189$3328_Y - connect \$65 $not$libresoc.v:51190$3329_Y - connect \$67 $and$libresoc.v:51191$3330_Y - connect \$69 $eq$libresoc.v:51192$3331_Y - connect \$71 $eq$libresoc.v:51193$3332_Y - connect \$73 $eq$libresoc.v:51194$3333_Y - connect \$75 $not$libresoc.v:51195$3334_Y - connect \$77 $and$libresoc.v:51196$3335_Y - connect \$7 $and$libresoc.v:51197$3336_Y - connect \$79 $not$libresoc.v:51198$3337_Y - connect \$81 $and$libresoc.v:51199$3338_Y - connect \$83 $eq$libresoc.v:51200$3339_Y - connect \$85 $eq$libresoc.v:51201$3340_Y - connect \$87 $eq$libresoc.v:51202$3341_Y - connect \$89 $not$libresoc.v:51203$3342_Y - connect \$91 $and$libresoc.v:51204$3343_Y - connect \$93 $not$libresoc.v:51205$3344_Y - connect \$95 $and$libresoc.v:51206$3345_Y - connect \$97 $eq$libresoc.v:51207$3346_Y + assign $4\do_dmi_log_rd$next[0:0]$3445 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3445 $1\do_dmi_log_rd$next[0:0]$3442 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3441 + end + connect \$9 $not$libresoc.v:51248$3300_Y + connect \$99 $eq$libresoc.v:51249$3301_Y + connect \$101 $eq$libresoc.v:51250$3302_Y + connect \$103 $not$libresoc.v:51251$3303_Y + connect \$105 $and$libresoc.v:51252$3304_Y + connect \$107 $not$libresoc.v:51253$3305_Y + connect \$109 $and$libresoc.v:51254$3306_Y + connect \$111 $eq$libresoc.v:51255$3307_Y + connect \$113 $eq$libresoc.v:51256$3308_Y + connect \$115 $eq$libresoc.v:51257$3309_Y + connect \$118 $add$libresoc.v:51258$3310_Y + connect \$11 $and$libresoc.v:51259$3311_Y + connect \$120 $eq$libresoc.v:51260$3312_Y + connect \$122 $and$libresoc.v:51261$3313_Y + connect \$124 $not$libresoc.v:51262$3314_Y + connect \$126 $and$libresoc.v:51263$3315_Y + connect \$13 $eq$libresoc.v:51264$3316_Y + connect \$15 $eq$libresoc.v:51265$3317_Y + connect \$17 $eq$libresoc.v:51266$3318_Y + connect \$1 $pos$libresoc.v:51267$3319_Y + connect \$19 $not$libresoc.v:51268$3320_Y + connect \$21 $and$libresoc.v:51269$3321_Y + connect \$23 $not$libresoc.v:51270$3322_Y + connect \$25 $and$libresoc.v:51271$3323_Y + connect \$27 $eq$libresoc.v:51272$3324_Y + connect \$29 $eq$libresoc.v:51273$3325_Y + connect \$31 $eq$libresoc.v:51274$3326_Y + connect \$33 $not$libresoc.v:51275$3327_Y + connect \$35 $and$libresoc.v:51276$3328_Y + connect \$37 $not$libresoc.v:51277$3329_Y + connect \$3 $pos$libresoc.v:51278$3330_Y + connect \$39 $and$libresoc.v:51279$3331_Y + connect \$41 $eq$libresoc.v:51280$3332_Y + connect \$43 $eq$libresoc.v:51281$3333_Y + connect \$45 $eq$libresoc.v:51282$3334_Y + connect \$47 $not$libresoc.v:51283$3335_Y + connect \$49 $and$libresoc.v:51284$3336_Y + connect \$51 $not$libresoc.v:51285$3337_Y + connect \$53 $and$libresoc.v:51286$3338_Y + connect \$55 $eq$libresoc.v:51287$3339_Y + connect \$57 $eq$libresoc.v:51288$3340_Y + connect \$5 $not$libresoc.v:51289$3341_Y + connect \$59 $eq$libresoc.v:51290$3342_Y + connect \$61 $not$libresoc.v:51291$3343_Y + connect \$63 $and$libresoc.v:51292$3344_Y + connect \$65 $not$libresoc.v:51293$3345_Y + connect \$67 $and$libresoc.v:51294$3346_Y + connect \$69 $eq$libresoc.v:51295$3347_Y + connect \$71 $eq$libresoc.v:51296$3348_Y + connect \$73 $eq$libresoc.v:51297$3349_Y + connect \$75 $not$libresoc.v:51298$3350_Y + connect \$77 $and$libresoc.v:51299$3351_Y + connect \$7 $and$libresoc.v:51300$3352_Y + connect \$79 $not$libresoc.v:51301$3353_Y + connect \$81 $and$libresoc.v:51302$3354_Y + connect \$83 $eq$libresoc.v:51303$3355_Y + connect \$85 $eq$libresoc.v:51304$3356_Y + connect \$87 $eq$libresoc.v:51305$3357_Y + connect \$89 $not$libresoc.v:51306$3358_Y + connect \$91 $and$libresoc.v:51307$3359_Y + connect \$93 $not$libresoc.v:51308$3360_Y + connect \$95 $and$libresoc.v:51309$3361_Y + connect \$97 $eq$libresoc.v:51310$3362_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92123,140 +92379,140 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51632.1-53682.10" +attribute \src "libresoc.v:51735.1-53785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53243.3-53276.6" + attribute \src "libresoc.v:53346.3-53379.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53277.3-53310.6" + attribute \src "libresoc.v:53380.3-53413.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:52903.3-52936.6" + attribute \src "libresoc.v:53006.3-53039.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:53005.3-53038.6" + attribute \src "libresoc.v:53108.3-53141.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53107.3-53140.6" + attribute \src "libresoc.v:53210.3-53243.6" wire width 14 $0\ALU_function_unit[13:0] - attribute \src "libresoc.v:53175.3-53208.6" + attribute \src "libresoc.v:53278.3-53311.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53209.3-53242.6" + attribute \src "libresoc.v:53312.3-53345.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53141.3-53174.6" + attribute \src "libresoc.v:53244.3-53277.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:52937.3-52970.6" + attribute \src "libresoc.v:53040.3-53073.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:52971.3-53004.6" + attribute \src "libresoc.v:53074.3-53107.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53039.3-53072.6" + attribute \src "libresoc.v:53142.3-53175.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53311.3-53344.6" + attribute \src "libresoc.v:53414.3-53447.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52869.3-52902.6" + attribute \src "libresoc.v:52972.3-53005.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53073.3-53106.6" + attribute \src "libresoc.v:53176.3-53209.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51633.7-51633.20" + attribute \src "libresoc.v:51736.7-51736.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53243.3-53276.6" + attribute \src "libresoc.v:53346.3-53379.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53277.3-53310.6" + attribute \src "libresoc.v:53380.3-53413.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52903.3-52936.6" + attribute \src "libresoc.v:53006.3-53039.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53005.3-53038.6" + attribute \src "libresoc.v:53108.3-53141.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53107.3-53140.6" + attribute \src "libresoc.v:53210.3-53243.6" wire width 14 $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53175.3-53208.6" + attribute \src "libresoc.v:53278.3-53311.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53209.3-53242.6" + attribute \src "libresoc.v:53312.3-53345.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53141.3-53174.6" + attribute \src "libresoc.v:53244.3-53277.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52937.3-52970.6" + attribute \src "libresoc.v:53040.3-53073.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52971.3-53004.6" + attribute \src "libresoc.v:53074.3-53107.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53039.3-53072.6" + attribute \src "libresoc.v:53142.3-53175.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53311.3-53344.6" + attribute \src "libresoc.v:53414.3-53447.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52869.3-52902.6" + attribute \src "libresoc.v:52972.3-53005.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53073.3-53106.6" + attribute \src "libresoc.v:53176.3-53209.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52834.17-52834.211" - wire width 32 $ternary$libresoc.v:52834$3442_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:52937.17-52937.211" + wire width 32 $ternary$libresoc.v:52937$3458_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \ALU_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \ALU_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \ALU_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \ALU_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \ALU_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92267,7 +92523,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92276,15 +92532,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92295,7 +92551,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92304,15 +92560,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92329,7 +92585,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92337,7 +92593,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92354,7 +92610,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92431,13 +92687,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec19_ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92445,17 +92701,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -92466,7 +92722,7 @@ module \dec attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -92475,15 +92731,15 @@ module \dec attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92500,7 +92756,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92508,7 +92764,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92525,7 +92781,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92602,13 +92858,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92616,17 +92872,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -92643,7 +92899,7 @@ module \dec attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -92651,7 +92907,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -92668,7 +92924,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -92745,13 +93001,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -92759,634 +93015,634 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:51633.7-51633.15" + attribute \src "libresoc.v:51736.7-51736.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:52834$3442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:52937$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52834$3442_Y + connect \Y $ternary$libresoc.v:52937$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52835.13-52851.4" + attribute \src "libresoc.v:52938.13-52954.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93405,7 +93661,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52852.13-52868.4" + attribute \src "libresoc.v:52955.13-52971.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93423,26 +93679,26 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51633.7-51633.20" - process $proc$libresoc.v:51633$3457 + attribute \src "libresoc.v:51736.7-51736.20" + process $proc$libresoc.v:51736$3473 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52869.3-52902.6" - process $proc$libresoc.v:52869$3443 + attribute \src "libresoc.v:52972.3-53005.6" + process $proc$libresoc.v:52972$3459 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52870.5-52870.29" + attribute \src "libresoc.v:52973.5-52973.29" switch \initial - attribute \src "libresoc.v:52870.9-52870.17" + attribute \src "libresoc.v:52973.9-52973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93486,18 +93742,18 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52903.3-52936.6" - process $proc$libresoc.v:52903$3444 + attribute \src "libresoc.v:53006.3-53039.6" + process $proc$libresoc.v:53006$3460 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52904.5-52904.29" + attribute \src "libresoc.v:53007.5-53007.29" switch \initial - attribute \src "libresoc.v:52904.9-52904.17" + attribute \src "libresoc.v:53007.9-53007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93541,18 +93797,18 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:52937.3-52970.6" - process $proc$libresoc.v:52937$3445 + attribute \src "libresoc.v:53040.3-53073.6" + process $proc$libresoc.v:53040$3461 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52938.5-52938.29" + attribute \src "libresoc.v:53041.5-53041.29" switch \initial - attribute \src "libresoc.v:52938.9-52938.17" + attribute \src "libresoc.v:53041.9-53041.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93596,18 +93852,18 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:52971.3-53004.6" - process $proc$libresoc.v:52971$3446 + attribute \src "libresoc.v:53074.3-53107.6" + process $proc$libresoc.v:53074$3462 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52972.5-52972.29" + attribute \src "libresoc.v:53075.5-53075.29" switch \initial - attribute \src "libresoc.v:52972.9-52972.17" + attribute \src "libresoc.v:53075.9-53075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93651,18 +93907,18 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:53005.3-53038.6" - process $proc$libresoc.v:53005$3447 + attribute \src "libresoc.v:53108.3-53141.6" + process $proc$libresoc.v:53108$3463 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53006.5-53006.29" + attribute \src "libresoc.v:53109.5-53109.29" switch \initial - attribute \src "libresoc.v:53006.9-53006.17" + attribute \src "libresoc.v:53109.9-53109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93706,18 +93962,18 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53039.3-53072.6" - process $proc$libresoc.v:53039$3448 + attribute \src "libresoc.v:53142.3-53175.6" + process $proc$libresoc.v:53142$3464 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53040.5-53040.29" + attribute \src "libresoc.v:53143.5-53143.29" switch \initial - attribute \src "libresoc.v:53040.9-53040.17" + attribute \src "libresoc.v:53143.9-53143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93761,18 +94017,18 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53073.3-53106.6" - process $proc$libresoc.v:53073$3449 + attribute \src "libresoc.v:53176.3-53209.6" + process $proc$libresoc.v:53176$3465 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53074.5-53074.29" + attribute \src "libresoc.v:53177.5-53177.29" switch \initial - attribute \src "libresoc.v:53074.9-53074.17" + attribute \src "libresoc.v:53177.9-53177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93816,18 +94072,18 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53107.3-53140.6" - process $proc$libresoc.v:53107$3450 + attribute \src "libresoc.v:53210.3-53243.6" + process $proc$libresoc.v:53210$3466 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53108.5-53108.29" + attribute \src "libresoc.v:53211.5-53211.29" switch \initial - attribute \src "libresoc.v:53108.9-53108.17" + attribute \src "libresoc.v:53211.9-53211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93871,18 +94127,18 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:53141.3-53174.6" - process $proc$libresoc.v:53141$3451 + attribute \src "libresoc.v:53244.3-53277.6" + process $proc$libresoc.v:53244$3467 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53142.5-53142.29" + attribute \src "libresoc.v:53245.5-53245.29" switch \initial - attribute \src "libresoc.v:53142.9-53142.17" + attribute \src "libresoc.v:53245.9-53245.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93926,18 +94182,18 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53175.3-53208.6" - process $proc$libresoc.v:53175$3452 + attribute \src "libresoc.v:53278.3-53311.6" + process $proc$libresoc.v:53278$3468 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53176.5-53176.29" + attribute \src "libresoc.v:53279.5-53279.29" switch \initial - attribute \src "libresoc.v:53176.9-53176.17" + attribute \src "libresoc.v:53279.9-53279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93981,18 +94237,18 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53209.3-53242.6" - process $proc$libresoc.v:53209$3453 + attribute \src "libresoc.v:53312.3-53345.6" + process $proc$libresoc.v:53312$3469 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53210.5-53210.29" + attribute \src "libresoc.v:53313.5-53313.29" switch \initial - attribute \src "libresoc.v:53210.9-53210.17" + attribute \src "libresoc.v:53313.9-53313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94036,18 +94292,18 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53243.3-53276.6" - process $proc$libresoc.v:53243$3454 + attribute \src "libresoc.v:53346.3-53379.6" + process $proc$libresoc.v:53346$3470 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53244.5-53244.29" + attribute \src "libresoc.v:53347.5-53347.29" switch \initial - attribute \src "libresoc.v:53244.9-53244.17" + attribute \src "libresoc.v:53347.9-53347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94091,18 +94347,18 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53277.3-53310.6" - process $proc$libresoc.v:53277$3455 + attribute \src "libresoc.v:53380.3-53413.6" + process $proc$libresoc.v:53380$3471 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53278.5-53278.29" + attribute \src "libresoc.v:53381.5-53381.29" switch \initial - attribute \src "libresoc.v:53278.9-53278.17" + attribute \src "libresoc.v:53381.9-53381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94146,18 +94402,18 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53311.3-53344.6" - process $proc$libresoc.v:53311$3456 + attribute \src "libresoc.v:53414.3-53447.6" + process $proc$libresoc.v:53414$3472 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53312.5-53312.29" + attribute \src "libresoc.v:53415.5-53415.29" switch \initial - attribute \src "libresoc.v:53312.9-53312.17" + attribute \src "libresoc.v:53415.9-53415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94201,7 +94457,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52834$3442_Y + connect \$1 $ternary$libresoc.v:52937$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94540,134 +94796,134 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53686.1-55151.10" +attribute \src "libresoc.v:53789.1-55254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54775.3-54787.6" + attribute \src "libresoc.v:54878.3-54890.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54788.3-54800.6" + attribute \src "libresoc.v:54891.3-54903.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54749.3-54761.6" + attribute \src "libresoc.v:54852.3-54864.6" wire width 14 $0\CR_function_unit[13:0] - attribute \src "libresoc.v:54762.3-54774.6" + attribute \src "libresoc.v:54865.3-54877.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54801.3-54813.6" + attribute \src "libresoc.v:54904.3-54916.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53687.7-53687.20" + attribute \src "libresoc.v:53790.7-53790.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54775.3-54787.6" + attribute \src "libresoc.v:54878.3-54890.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54788.3-54800.6" + attribute \src "libresoc.v:54891.3-54903.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54749.3-54761.6" + attribute \src "libresoc.v:54852.3-54864.6" wire width 14 $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54762.3-54774.6" + attribute \src "libresoc.v:54865.3-54877.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54801.3-54813.6" + attribute \src "libresoc.v:54904.3-54916.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54732.17-54732.211" - wire width 32 $ternary$libresoc.v:54732$3458_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:54835.17-54835.211" + wire width 32 $ternary$libresoc.v:54835$3474_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \CR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \CR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \CR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \CR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \CR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \CR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \CR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 9 \CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \CR_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 8 \CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \CR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \CR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \CR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94678,7 +94934,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94687,7 +94943,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \CR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94698,7 +94954,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec19_CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94707,7 +94963,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec19_CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94724,7 +94980,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec19_CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -94801,15 +95057,15 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec19_CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec19_CR_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -94820,7 +95076,7 @@ module \dec$138 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -94829,7 +95085,7 @@ module \dec$138 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_CR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94846,7 +95102,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -94923,15 +95179,15 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_CR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -94948,7 +95204,7 @@ module \dec$138 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -95025,602 +95281,602 @@ module \dec$138 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \CR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:53687.7-53687.15" + attribute \src "libresoc.v:53790.7-53790.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:54732$3458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:54835$3474 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54732$3458_Y + connect \Y $ternary$libresoc.v:54835$3474_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54733.12-54740.4" + attribute \src "libresoc.v:54836.12-54843.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95630,7 +95886,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54741.12-54748.4" + attribute \src "libresoc.v:54844.12-54851.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95639,26 +95895,26 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53687.7-53687.20" - process $proc$libresoc.v:53687$3464 + attribute \src "libresoc.v:53790.7-53790.20" + process $proc$libresoc.v:53790$3480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54749.3-54761.6" - process $proc$libresoc.v:54749$3459 + attribute \src "libresoc.v:54852.3-54864.6" + process $proc$libresoc.v:54852$3475 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54750.5-54750.29" + attribute \src "libresoc.v:54853.5-54853.29" switch \initial - attribute \src "libresoc.v:54750.9-54750.17" + attribute \src "libresoc.v:54853.9-54853.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95674,18 +95930,18 @@ module \dec$138 sync always update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54762.3-54774.6" - process $proc$libresoc.v:54762$3460 + attribute \src "libresoc.v:54865.3-54877.6" + process $proc$libresoc.v:54865$3476 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54763.5-54763.29" + attribute \src "libresoc.v:54866.5-54866.29" switch \initial - attribute \src "libresoc.v:54763.9-54763.17" + attribute \src "libresoc.v:54866.9-54866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95701,18 +95957,18 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54775.3-54787.6" - process $proc$libresoc.v:54775$3461 + attribute \src "libresoc.v:54878.3-54890.6" + process $proc$libresoc.v:54878$3477 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54776.5-54776.29" + attribute \src "libresoc.v:54879.5-54879.29" switch \initial - attribute \src "libresoc.v:54776.9-54776.17" + attribute \src "libresoc.v:54879.9-54879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95728,18 +95984,18 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54788.3-54800.6" - process $proc$libresoc.v:54788$3462 + attribute \src "libresoc.v:54891.3-54903.6" + process $proc$libresoc.v:54891$3478 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54789.5-54789.29" + attribute \src "libresoc.v:54892.5-54892.29" switch \initial - attribute \src "libresoc.v:54789.9-54789.17" + attribute \src "libresoc.v:54892.9-54892.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95755,18 +96011,18 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54801.3-54813.6" - process $proc$libresoc.v:54801$3463 + attribute \src "libresoc.v:54904.3-54916.6" + process $proc$libresoc.v:54904$3479 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54802.5-54802.29" + attribute \src "libresoc.v:54905.5-54905.29" switch \initial - attribute \src "libresoc.v:54802.9-54802.17" + attribute \src "libresoc.v:54905.9-54905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95782,7 +96038,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54732$3458_Y + connect \$1 $ternary$libresoc.v:54835$3474_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96121,136 +96377,136 @@ module \dec$138 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55155.1-56600.10" +attribute \src "libresoc.v:55258.1-56703.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:56184.3-56199.6" + attribute \src "libresoc.v:56287.3-56302.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56200.3-56215.6" + attribute \src "libresoc.v:56303.3-56318.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56136.3-56151.6" + attribute \src "libresoc.v:56239.3-56254.6" wire width 14 $0\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56168.3-56183.6" + attribute \src "libresoc.v:56271.3-56286.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56152.3-56167.6" + attribute \src "libresoc.v:56255.3-56270.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56232.3-56247.6" + attribute \src "libresoc.v:56335.3-56350.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56248.3-56263.6" + attribute \src "libresoc.v:56351.3-56366.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56216.3-56231.6" + attribute \src "libresoc.v:56319.3-56334.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55156.7-55156.20" + attribute \src "libresoc.v:55259.7-55259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56184.3-56199.6" + attribute \src "libresoc.v:56287.3-56302.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56200.3-56215.6" + attribute \src "libresoc.v:56303.3-56318.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56136.3-56151.6" + attribute \src "libresoc.v:56239.3-56254.6" wire width 14 $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56168.3-56183.6" + attribute \src "libresoc.v:56271.3-56286.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56152.3-56167.6" + attribute \src "libresoc.v:56255.3-56270.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56232.3-56247.6" + attribute \src "libresoc.v:56335.3-56350.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56248.3-56263.6" + attribute \src "libresoc.v:56351.3-56366.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56216.3-56231.6" + attribute \src "libresoc.v:56319.3-56334.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56124.17-56124.211" - wire width 32 $ternary$libresoc.v:56124$3465_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:56227.17-56227.211" + wire width 32 $ternary$libresoc.v:56227$3481_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BRANCH_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BRANCH_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \BRANCH_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \BRANCH_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 20 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 16 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 18 \BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \BRANCH_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 14 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96261,7 +96517,7 @@ module \dec$141 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96270,7 +96526,7 @@ module \dec$141 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96281,7 +96537,7 @@ module \dec$141 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96290,7 +96546,7 @@ module \dec$141 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -96307,7 +96563,7 @@ module \dec$141 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96324,7 +96580,7 @@ module \dec$141 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -96401,19 +96657,19 @@ module \dec$141 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -96430,7 +96686,7 @@ module \dec$141 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96447,7 +96703,7 @@ module \dec$141 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -96524,616 +96780,616 @@ module \dec$141 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 15 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:55156.7-55156.15" + attribute \src "libresoc.v:55259.7-55259.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:56124$3465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:56227$3481 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56124$3465_Y + connect \Y $ternary$libresoc.v:56227$3481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56125.16-56135.4" + attribute \src "libresoc.v:56228.16-56238.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97145,26 +97401,26 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55156.7-55156.20" - process $proc$libresoc.v:55156$3474 + attribute \src "libresoc.v:55259.7-55259.20" + process $proc$libresoc.v:55259$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56136.3-56151.6" - process $proc$libresoc.v:56136$3466 + attribute \src "libresoc.v:56239.3-56254.6" + process $proc$libresoc.v:56239$3482 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56137.5-56137.29" + attribute \src "libresoc.v:56240.5-56240.29" switch \initial - attribute \src "libresoc.v:56137.9-56137.17" + attribute \src "libresoc.v:56240.9-56240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97184,18 +97440,18 @@ module \dec$141 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:56152.3-56167.6" - process $proc$libresoc.v:56152$3467 + attribute \src "libresoc.v:56255.3-56270.6" + process $proc$libresoc.v:56255$3483 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56153.5-56153.29" + attribute \src "libresoc.v:56256.5-56256.29" switch \initial - attribute \src "libresoc.v:56153.9-56153.17" + attribute \src "libresoc.v:56256.9-56256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97215,18 +97471,18 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56168.3-56183.6" - process $proc$libresoc.v:56168$3468 + attribute \src "libresoc.v:56271.3-56286.6" + process $proc$libresoc.v:56271$3484 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56169.5-56169.29" + attribute \src "libresoc.v:56272.5-56272.29" switch \initial - attribute \src "libresoc.v:56169.9-56169.17" + attribute \src "libresoc.v:56272.9-56272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97246,18 +97502,18 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56184.3-56199.6" - process $proc$libresoc.v:56184$3469 + attribute \src "libresoc.v:56287.3-56302.6" + process $proc$libresoc.v:56287$3485 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56185.5-56185.29" + attribute \src "libresoc.v:56288.5-56288.29" switch \initial - attribute \src "libresoc.v:56185.9-56185.17" + attribute \src "libresoc.v:56288.9-56288.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97277,18 +97533,18 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56200.3-56215.6" - process $proc$libresoc.v:56200$3470 + attribute \src "libresoc.v:56303.3-56318.6" + process $proc$libresoc.v:56303$3486 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56201.5-56201.29" + attribute \src "libresoc.v:56304.5-56304.29" switch \initial - attribute \src "libresoc.v:56201.9-56201.17" + attribute \src "libresoc.v:56304.9-56304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97308,18 +97564,18 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56216.3-56231.6" - process $proc$libresoc.v:56216$3471 + attribute \src "libresoc.v:56319.3-56334.6" + process $proc$libresoc.v:56319$3487 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56217.5-56217.29" + attribute \src "libresoc.v:56320.5-56320.29" switch \initial - attribute \src "libresoc.v:56217.9-56217.17" + attribute \src "libresoc.v:56320.9-56320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97339,18 +97595,18 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56232.3-56247.6" - process $proc$libresoc.v:56232$3472 + attribute \src "libresoc.v:56335.3-56350.6" + process $proc$libresoc.v:56335$3488 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56233.5-56233.29" + attribute \src "libresoc.v:56336.5-56336.29" switch \initial - attribute \src "libresoc.v:56233.9-56233.17" + attribute \src "libresoc.v:56336.9-56336.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97370,18 +97626,18 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56248.3-56263.6" - process $proc$libresoc.v:56248$3473 + attribute \src "libresoc.v:56351.3-56366.6" + process $proc$libresoc.v:56351$3489 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56249.5-56249.29" + attribute \src "libresoc.v:56352.5-56352.29" switch \initial - attribute \src "libresoc.v:56249.9-56249.17" + attribute \src "libresoc.v:56352.9-56352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -97401,7 +97657,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56124$3465_Y + connect \$1 $ternary$libresoc.v:56227$3481_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97739,260 +97995,260 @@ module \dec$141 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56604.1-58381.10" +attribute \src "libresoc.v:56707.1-58484.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:57933.3-57960.6" + attribute \src "libresoc.v:58036.3-58063.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57961.3-57988.6" + attribute \src "libresoc.v:58064.3-58091.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57653.3-57680.6" + attribute \src "libresoc.v:57756.3-57783.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57737.3-57764.6" + attribute \src "libresoc.v:57840.3-57867.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57821.3-57848.6" + attribute \src "libresoc.v:57924.3-57951.6" wire width 14 $0\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57877.3-57904.6" + attribute \src "libresoc.v:57980.3-58007.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57905.3-57932.6" + attribute \src "libresoc.v:58008.3-58035.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57849.3-57876.6" + attribute \src "libresoc.v:57952.3-57979.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57681.3-57708.6" + attribute \src "libresoc.v:57784.3-57811.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57709.3-57736.6" + attribute \src "libresoc.v:57812.3-57839.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57765.3-57792.6" + attribute \src "libresoc.v:57868.3-57895.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57989.3-58016.6" + attribute \src "libresoc.v:58092.3-58119.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58017.3-58044.6" + attribute \src "libresoc.v:58120.3-58147.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57793.3-57820.6" + attribute \src "libresoc.v:57896.3-57923.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56605.7-56605.20" + attribute \src "libresoc.v:56708.7-56708.20" wire $0\initial[0:0] - attribute \src "libresoc.v:57933.3-57960.6" + attribute \src "libresoc.v:58036.3-58063.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57961.3-57988.6" + attribute \src "libresoc.v:58064.3-58091.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57653.3-57680.6" + attribute \src "libresoc.v:57756.3-57783.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57737.3-57764.6" + attribute \src "libresoc.v:57840.3-57867.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57821.3-57848.6" + attribute \src "libresoc.v:57924.3-57951.6" wire width 14 $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57877.3-57904.6" + attribute \src "libresoc.v:57980.3-58007.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57905.3-57932.6" + attribute \src "libresoc.v:58008.3-58035.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57849.3-57876.6" + attribute \src "libresoc.v:57952.3-57979.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57681.3-57708.6" + attribute \src "libresoc.v:57784.3-57811.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57709.3-57736.6" + attribute \src "libresoc.v:57812.3-57839.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57765.3-57792.6" + attribute \src "libresoc.v:57868.3-57895.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57989.3-58016.6" + attribute \src "libresoc.v:58092.3-58119.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58017.3-58044.6" + attribute \src "libresoc.v:58120.3-58147.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57793.3-57820.6" + attribute \src "libresoc.v:57896.3-57923.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57635.17-57635.211" - wire width 32 $ternary$libresoc.v:57635$3475_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:57738.17-57738.211" + wire width 32 $ternary$libresoc.v:57738$3491_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LOGICAL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LOGICAL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LOGICAL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LOGICAL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LOGICAL_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98003,7 +98259,7 @@ module \dec$145 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98012,15 +98268,15 @@ module \dec$145 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98031,7 +98287,7 @@ module \dec$145 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98040,15 +98296,15 @@ module \dec$145 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -98065,7 +98321,7 @@ module \dec$145 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -98073,7 +98329,7 @@ module \dec$145 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -98090,7 +98346,7 @@ module \dec$145 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -98167,13 +98423,13 @@ module \dec$145 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -98181,17 +98437,17 @@ module \dec$145 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -98208,7 +98464,7 @@ module \dec$145 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -98216,7 +98472,7 @@ module \dec$145 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -98233,7 +98489,7 @@ module \dec$145 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -98310,13 +98566,13 @@ module \dec$145 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -98324,514 +98580,514 @@ module \dec$145 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:56605.7-56605.15" + attribute \src "libresoc.v:56708.7-56708.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:57635$3475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:57738$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57635$3475_Y + connect \Y $ternary$libresoc.v:57738$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57636.17-57652.4" + attribute \src "libresoc.v:57739.17-57755.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -98849,26 +99105,26 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56605.7-56605.20" - process $proc$libresoc.v:56605$3490 + attribute \src "libresoc.v:56708.7-56708.20" + process $proc$libresoc.v:56708$3506 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57653.3-57680.6" - process $proc$libresoc.v:57653$3476 + attribute \src "libresoc.v:57756.3-57783.6" + process $proc$libresoc.v:57756$3492 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57654.5-57654.29" + attribute \src "libresoc.v:57757.5-57757.29" switch \initial - attribute \src "libresoc.v:57654.9-57654.17" + attribute \src "libresoc.v:57757.9-57757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98904,18 +99160,18 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57681.3-57708.6" - process $proc$libresoc.v:57681$3477 + attribute \src "libresoc.v:57784.3-57811.6" + process $proc$libresoc.v:57784$3493 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57682.5-57682.29" + attribute \src "libresoc.v:57785.5-57785.29" switch \initial - attribute \src "libresoc.v:57682.9-57682.17" + attribute \src "libresoc.v:57785.9-57785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98951,18 +99207,18 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57709.3-57736.6" - process $proc$libresoc.v:57709$3478 + attribute \src "libresoc.v:57812.3-57839.6" + process $proc$libresoc.v:57812$3494 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57710.5-57710.29" + attribute \src "libresoc.v:57813.5-57813.29" switch \initial - attribute \src "libresoc.v:57710.9-57710.17" + attribute \src "libresoc.v:57813.9-57813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98998,18 +99254,18 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57737.3-57764.6" - process $proc$libresoc.v:57737$3479 + attribute \src "libresoc.v:57840.3-57867.6" + process $proc$libresoc.v:57840$3495 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57738.5-57738.29" + attribute \src "libresoc.v:57841.5-57841.29" switch \initial - attribute \src "libresoc.v:57738.9-57738.17" + attribute \src "libresoc.v:57841.9-57841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99045,18 +99301,18 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57765.3-57792.6" - process $proc$libresoc.v:57765$3480 + attribute \src "libresoc.v:57868.3-57895.6" + process $proc$libresoc.v:57868$3496 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57766.5-57766.29" + attribute \src "libresoc.v:57869.5-57869.29" switch \initial - attribute \src "libresoc.v:57766.9-57766.17" + attribute \src "libresoc.v:57869.9-57869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99092,18 +99348,18 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57793.3-57820.6" - process $proc$libresoc.v:57793$3481 + attribute \src "libresoc.v:57896.3-57923.6" + process $proc$libresoc.v:57896$3497 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57794.5-57794.29" + attribute \src "libresoc.v:57897.5-57897.29" switch \initial - attribute \src "libresoc.v:57794.9-57794.17" + attribute \src "libresoc.v:57897.9-57897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99139,18 +99395,18 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57821.3-57848.6" - process $proc$libresoc.v:57821$3482 + attribute \src "libresoc.v:57924.3-57951.6" + process $proc$libresoc.v:57924$3498 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57822.5-57822.29" + attribute \src "libresoc.v:57925.5-57925.29" switch \initial - attribute \src "libresoc.v:57822.9-57822.17" + attribute \src "libresoc.v:57925.9-57925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99186,18 +99442,18 @@ module \dec$145 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57849.3-57876.6" - process $proc$libresoc.v:57849$3483 + attribute \src "libresoc.v:57952.3-57979.6" + process $proc$libresoc.v:57952$3499 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57850.5-57850.29" + attribute \src "libresoc.v:57953.5-57953.29" switch \initial - attribute \src "libresoc.v:57850.9-57850.17" + attribute \src "libresoc.v:57953.9-57953.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99233,18 +99489,18 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57877.3-57904.6" - process $proc$libresoc.v:57877$3484 + attribute \src "libresoc.v:57980.3-58007.6" + process $proc$libresoc.v:57980$3500 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57878.5-57878.29" + attribute \src "libresoc.v:57981.5-57981.29" switch \initial - attribute \src "libresoc.v:57878.9-57878.17" + attribute \src "libresoc.v:57981.9-57981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99280,18 +99536,18 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57905.3-57932.6" - process $proc$libresoc.v:57905$3485 + attribute \src "libresoc.v:58008.3-58035.6" + process $proc$libresoc.v:58008$3501 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57906.5-57906.29" + attribute \src "libresoc.v:58009.5-58009.29" switch \initial - attribute \src "libresoc.v:57906.9-57906.17" + attribute \src "libresoc.v:58009.9-58009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99327,18 +99583,18 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:57933.3-57960.6" - process $proc$libresoc.v:57933$3486 + attribute \src "libresoc.v:58036.3-58063.6" + process $proc$libresoc.v:58036$3502 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57934.5-57934.29" + attribute \src "libresoc.v:58037.5-58037.29" switch \initial - attribute \src "libresoc.v:57934.9-57934.17" + attribute \src "libresoc.v:58037.9-58037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99374,18 +99630,18 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:57961.3-57988.6" - process $proc$libresoc.v:57961$3487 + attribute \src "libresoc.v:58064.3-58091.6" + process $proc$libresoc.v:58064$3503 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57962.5-57962.29" + attribute \src "libresoc.v:58065.5-58065.29" switch \initial - attribute \src "libresoc.v:57962.9-57962.17" + attribute \src "libresoc.v:58065.9-58065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99421,18 +99677,18 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:57989.3-58016.6" - process $proc$libresoc.v:57989$3488 + attribute \src "libresoc.v:58092.3-58119.6" + process $proc$libresoc.v:58092$3504 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57990.5-57990.29" + attribute \src "libresoc.v:58093.5-58093.29" switch \initial - attribute \src "libresoc.v:57990.9-57990.17" + attribute \src "libresoc.v:58093.9-58093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99468,18 +99724,18 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58017.3-58044.6" - process $proc$libresoc.v:58017$3489 + attribute \src "libresoc.v:58120.3-58147.6" + process $proc$libresoc.v:58120$3505 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58018.5-58018.29" + attribute \src "libresoc.v:58121.5-58121.29" switch \initial - attribute \src "libresoc.v:58018.9-58018.17" + attribute \src "libresoc.v:58121.9-58121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99515,7 +99771,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57635$3475_Y + connect \$1 $ternary$libresoc.v:57738$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -99853,284 +100109,284 @@ module \dec$145 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58385.1-59720.10" +attribute \src "libresoc.v:58488.1-59823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59344.3-59353.6" + attribute \src "libresoc.v:59447.3-59456.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59354.3-59363.6" + attribute \src "libresoc.v:59457.3-59466.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59324.3-59333.6" + attribute \src "libresoc.v:59427.3-59436.6" wire width 14 $0\SPR_function_unit[13:0] - attribute \src "libresoc.v:59334.3-59343.6" + attribute \src "libresoc.v:59437.3-59446.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59374.3-59383.6" + attribute \src "libresoc.v:59477.3-59486.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59364.3-59373.6" + attribute \src "libresoc.v:59467.3-59476.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58386.7-58386.20" + attribute \src "libresoc.v:58489.7-58489.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59344.3-59353.6" + attribute \src "libresoc.v:59447.3-59456.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59354.3-59363.6" + attribute \src "libresoc.v:59457.3-59466.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59324.3-59333.6" + attribute \src "libresoc.v:59427.3-59436.6" wire width 14 $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59334.3-59343.6" + attribute \src "libresoc.v:59437.3-59446.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59374.3-59383.6" + attribute \src "libresoc.v:59477.3-59486.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59364.3-59373.6" + attribute \src "libresoc.v:59467.3-59476.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59314.17-59314.211" - wire width 32 $ternary$libresoc.v:59314$3491_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:59417.17-59417.211" + wire width 32 $ternary$libresoc.v:59417$3507_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SPR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SPR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SPR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \SPR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 10 \SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 9 \SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100141,7 +100397,7 @@ module \dec$150 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100150,7 +100406,7 @@ module \dec$150 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100161,7 +100417,7 @@ module \dec$150 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100170,7 +100426,7 @@ module \dec$150 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -100187,7 +100443,7 @@ module \dec$150 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100264,17 +100520,17 @@ module \dec$150 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_SPR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -100291,7 +100547,7 @@ module \dec$150 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100368,458 +100624,458 @@ module \dec$150 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:58386.7-58386.15" + attribute \src "libresoc.v:58489.7-58489.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:59314$3491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:59417$3507 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59314$3491_Y + connect \Y $ternary$libresoc.v:59417$3507_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59315.13-59323.4" + attribute \src "libresoc.v:59418.13-59426.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -100829,26 +101085,26 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58386.7-58386.20" - process $proc$libresoc.v:58386$3498 + attribute \src "libresoc.v:58489.7-58489.20" + process $proc$libresoc.v:58489$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59324.3-59333.6" - process $proc$libresoc.v:59324$3492 + attribute \src "libresoc.v:59427.3-59436.6" + process $proc$libresoc.v:59427$3508 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59325.5-59325.29" + attribute \src "libresoc.v:59428.5-59428.29" switch \initial - attribute \src "libresoc.v:59325.9-59325.17" + attribute \src "libresoc.v:59428.9-59428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100860,18 +101116,18 @@ module \dec$150 sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59334.3-59343.6" - process $proc$libresoc.v:59334$3493 + attribute \src "libresoc.v:59437.3-59446.6" + process $proc$libresoc.v:59437$3509 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59335.5-59335.29" + attribute \src "libresoc.v:59438.5-59438.29" switch \initial - attribute \src "libresoc.v:59335.9-59335.17" + attribute \src "libresoc.v:59438.9-59438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100883,18 +101139,18 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59344.3-59353.6" - process $proc$libresoc.v:59344$3494 + attribute \src "libresoc.v:59447.3-59456.6" + process $proc$libresoc.v:59447$3510 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59345.5-59345.29" + attribute \src "libresoc.v:59448.5-59448.29" switch \initial - attribute \src "libresoc.v:59345.9-59345.17" + attribute \src "libresoc.v:59448.9-59448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100906,18 +101162,18 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59354.3-59363.6" - process $proc$libresoc.v:59354$3495 + attribute \src "libresoc.v:59457.3-59466.6" + process $proc$libresoc.v:59457$3511 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59355.5-59355.29" + attribute \src "libresoc.v:59458.5-59458.29" switch \initial - attribute \src "libresoc.v:59355.9-59355.17" + attribute \src "libresoc.v:59458.9-59458.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100929,18 +101185,18 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59364.3-59373.6" - process $proc$libresoc.v:59364$3496 + attribute \src "libresoc.v:59467.3-59476.6" + process $proc$libresoc.v:59467$3512 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59365.5-59365.29" + attribute \src "libresoc.v:59468.5-59468.29" switch \initial - attribute \src "libresoc.v:59365.9-59365.17" + attribute \src "libresoc.v:59468.9-59468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100952,18 +101208,18 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59374.3-59383.6" - process $proc$libresoc.v:59374$3497 + attribute \src "libresoc.v:59477.3-59486.6" + process $proc$libresoc.v:59477$3513 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59375.5-59375.29" + attribute \src "libresoc.v:59478.5-59478.29" switch \initial - attribute \src "libresoc.v:59375.9-59375.17" + attribute \src "libresoc.v:59478.9-59478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -100975,7 +101231,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59314$3491_Y + connect \$1 $ternary$libresoc.v:59417$3507_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101313,170 +101569,170 @@ module \dec$150 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59724.1-61249.10" +attribute \src "libresoc.v:59827.1-61352.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60873.3-60882.6" + attribute \src "libresoc.v:60976.3-60985.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60883.3-60892.6" + attribute \src "libresoc.v:60986.3-60995.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60773.3-60782.6" + attribute \src "libresoc.v:60876.3-60885.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60803.3-60812.6" + attribute \src "libresoc.v:60906.3-60915.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60833.3-60842.6" + attribute \src "libresoc.v:60936.3-60945.6" wire width 14 $0\DIV_function_unit[13:0] - attribute \src "libresoc.v:60853.3-60862.6" + attribute \src "libresoc.v:60956.3-60965.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60863.3-60872.6" + attribute \src "libresoc.v:60966.3-60975.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60843.3-60852.6" + attribute \src "libresoc.v:60946.3-60955.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60783.3-60792.6" + attribute \src "libresoc.v:60886.3-60895.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60793.3-60802.6" + attribute \src "libresoc.v:60896.3-60905.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60813.3-60822.6" + attribute \src "libresoc.v:60916.3-60925.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60893.3-60902.6" + attribute \src "libresoc.v:60996.3-61005.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60903.3-60912.6" + attribute \src "libresoc.v:61006.3-61015.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60823.3-60832.6" + attribute \src "libresoc.v:60926.3-60935.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59725.7-59725.20" + attribute \src "libresoc.v:59828.7-59828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60873.3-60882.6" + attribute \src "libresoc.v:60976.3-60985.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60883.3-60892.6" + attribute \src "libresoc.v:60986.3-60995.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60773.3-60782.6" + attribute \src "libresoc.v:60876.3-60885.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60803.3-60812.6" + attribute \src "libresoc.v:60906.3-60915.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60833.3-60842.6" + attribute \src "libresoc.v:60936.3-60945.6" wire width 14 $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60853.3-60862.6" + attribute \src "libresoc.v:60956.3-60965.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60863.3-60872.6" + attribute \src "libresoc.v:60966.3-60975.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60843.3-60852.6" + attribute \src "libresoc.v:60946.3-60955.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60783.3-60792.6" + attribute \src "libresoc.v:60886.3-60895.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60793.3-60802.6" + attribute \src "libresoc.v:60896.3-60905.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60813.3-60822.6" + attribute \src "libresoc.v:60916.3-60925.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60893.3-60902.6" + attribute \src "libresoc.v:60996.3-61005.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60903.3-60912.6" + attribute \src "libresoc.v:61006.3-61015.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60823.3-60832.6" + attribute \src "libresoc.v:60926.3-60935.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60755.17-60755.211" - wire width 32 $ternary$libresoc.v:60755$3499_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:60858.17-60858.211" + wire width 32 $ternary$libresoc.v:60858$3515_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \DIV_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -101487,7 +101743,7 @@ module \dec$153 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -101496,15 +101752,15 @@ module \dec$153 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -101515,7 +101771,7 @@ module \dec$153 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -101524,15 +101780,15 @@ module \dec$153 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -101549,7 +101805,7 @@ module \dec$153 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -101557,7 +101813,7 @@ module \dec$153 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -101574,7 +101830,7 @@ module \dec$153 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -101651,13 +101907,13 @@ module \dec$153 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -101665,17 +101921,17 @@ module \dec$153 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -101692,7 +101948,7 @@ module \dec$153 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -101700,7 +101956,7 @@ module \dec$153 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -101717,7 +101973,7 @@ module \dec$153 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -101794,13 +102050,13 @@ module \dec$153 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -101808,604 +102064,604 @@ module \dec$153 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src 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wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:59725.7-59725.15" + attribute \src "libresoc.v:59828.7-59828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:60755$3499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:60858$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60755$3499_Y + connect \Y $ternary$libresoc.v:60858$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60756.13-60772.4" + attribute \src "libresoc.v:60859.13-60875.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102423,26 +102679,26 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59725.7-59725.20" - process $proc$libresoc.v:59725$3514 + attribute \src "libresoc.v:59828.7-59828.20" + process $proc$libresoc.v:59828$3530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60773.3-60782.6" - process $proc$libresoc.v:60773$3500 + attribute \src "libresoc.v:60876.3-60885.6" + process $proc$libresoc.v:60876$3516 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60774.5-60774.29" + attribute \src "libresoc.v:60877.5-60877.29" switch \initial - attribute \src "libresoc.v:60774.9-60774.17" + attribute \src "libresoc.v:60877.9-60877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102454,18 +102710,18 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60783.3-60792.6" - process $proc$libresoc.v:60783$3501 + attribute \src "libresoc.v:60886.3-60895.6" + process $proc$libresoc.v:60886$3517 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60784.5-60784.29" + attribute \src "libresoc.v:60887.5-60887.29" switch \initial - attribute \src "libresoc.v:60784.9-60784.17" + attribute \src "libresoc.v:60887.9-60887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102477,18 +102733,18 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60793.3-60802.6" - process $proc$libresoc.v:60793$3502 + attribute \src "libresoc.v:60896.3-60905.6" + process $proc$libresoc.v:60896$3518 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60794.5-60794.29" + attribute \src "libresoc.v:60897.5-60897.29" switch \initial - attribute \src "libresoc.v:60794.9-60794.17" + attribute \src "libresoc.v:60897.9-60897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102500,18 +102756,18 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60803.3-60812.6" - process $proc$libresoc.v:60803$3503 + attribute \src "libresoc.v:60906.3-60915.6" + process $proc$libresoc.v:60906$3519 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60804.5-60804.29" + attribute \src "libresoc.v:60907.5-60907.29" switch \initial - attribute \src "libresoc.v:60804.9-60804.17" + attribute \src "libresoc.v:60907.9-60907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102523,18 +102779,18 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60813.3-60822.6" - process $proc$libresoc.v:60813$3504 + attribute \src "libresoc.v:60916.3-60925.6" + process $proc$libresoc.v:60916$3520 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60814.5-60814.29" + attribute \src "libresoc.v:60917.5-60917.29" switch \initial - attribute \src "libresoc.v:60814.9-60814.17" + attribute \src "libresoc.v:60917.9-60917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102546,18 +102802,18 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60823.3-60832.6" - process $proc$libresoc.v:60823$3505 + attribute \src "libresoc.v:60926.3-60935.6" + process $proc$libresoc.v:60926$3521 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60824.5-60824.29" + attribute \src "libresoc.v:60927.5-60927.29" switch \initial - attribute \src "libresoc.v:60824.9-60824.17" + attribute \src "libresoc.v:60927.9-60927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102569,18 +102825,18 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60833.3-60842.6" - process $proc$libresoc.v:60833$3506 + attribute \src "libresoc.v:60936.3-60945.6" + process $proc$libresoc.v:60936$3522 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60834.5-60834.29" + attribute \src "libresoc.v:60937.5-60937.29" switch \initial - attribute \src "libresoc.v:60834.9-60834.17" + attribute \src "libresoc.v:60937.9-60937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102592,18 +102848,18 @@ module \dec$153 sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60843.3-60852.6" - process $proc$libresoc.v:60843$3507 + attribute \src "libresoc.v:60946.3-60955.6" + process $proc$libresoc.v:60946$3523 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60844.5-60844.29" + attribute \src "libresoc.v:60947.5-60947.29" switch \initial - attribute \src "libresoc.v:60844.9-60844.17" + attribute \src "libresoc.v:60947.9-60947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102615,18 +102871,18 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60853.3-60862.6" - process $proc$libresoc.v:60853$3508 + attribute \src "libresoc.v:60956.3-60965.6" + process $proc$libresoc.v:60956$3524 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60854.5-60854.29" + attribute \src "libresoc.v:60957.5-60957.29" switch \initial - attribute \src "libresoc.v:60854.9-60854.17" + attribute \src "libresoc.v:60957.9-60957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102638,18 +102894,18 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60863.3-60872.6" - process $proc$libresoc.v:60863$3509 + attribute \src "libresoc.v:60966.3-60975.6" + process $proc$libresoc.v:60966$3525 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60864.5-60864.29" + attribute \src "libresoc.v:60967.5-60967.29" switch \initial - attribute \src "libresoc.v:60864.9-60864.17" + attribute \src "libresoc.v:60967.9-60967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102661,18 +102917,18 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60873.3-60882.6" - process $proc$libresoc.v:60873$3510 + attribute \src "libresoc.v:60976.3-60985.6" + process $proc$libresoc.v:60976$3526 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60874.5-60874.29" + attribute \src "libresoc.v:60977.5-60977.29" switch \initial - attribute \src "libresoc.v:60874.9-60874.17" + attribute \src "libresoc.v:60977.9-60977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102684,18 +102940,18 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60883.3-60892.6" - process $proc$libresoc.v:60883$3511 + attribute \src "libresoc.v:60986.3-60995.6" + process $proc$libresoc.v:60986$3527 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60884.5-60884.29" + attribute \src "libresoc.v:60987.5-60987.29" switch \initial - attribute \src "libresoc.v:60884.9-60884.17" + attribute \src "libresoc.v:60987.9-60987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102707,18 +102963,18 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60893.3-60902.6" - process $proc$libresoc.v:60893$3512 + attribute \src "libresoc.v:60996.3-61005.6" + process $proc$libresoc.v:60996$3528 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60894.5-60894.29" + attribute \src "libresoc.v:60997.5-60997.29" switch \initial - attribute \src "libresoc.v:60894.9-60894.17" + attribute \src "libresoc.v:60997.9-60997.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102730,18 +102986,18 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60903.3-60912.6" - process $proc$libresoc.v:60903$3513 + attribute \src "libresoc.v:61006.3-61015.6" + process $proc$libresoc.v:61006$3529 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60904.5-60904.29" + attribute \src "libresoc.v:61007.5-61007.29" switch \initial - attribute \src "libresoc.v:60904.9-60904.17" + attribute \src "libresoc.v:61007.9-61007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102753,7 +103009,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60755$3499_Y + connect \$1 $ternary$libresoc.v:60858$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103091,272 +103347,272 @@ module \dec$153 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61253.1-62674.10" +attribute \src "libresoc.v:61356.1-62777.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:62273.3-62285.6" + attribute \src "libresoc.v:62376.3-62388.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62286.3-62298.6" + attribute \src "libresoc.v:62389.3-62401.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62234.3-62246.6" + attribute \src "libresoc.v:62337.3-62349.6" wire width 14 $0\MUL_function_unit[13:0] - attribute \src "libresoc.v:62260.3-62272.6" + attribute \src "libresoc.v:62363.3-62375.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62247.3-62259.6" + attribute \src "libresoc.v:62350.3-62362.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62312.3-62324.6" + attribute \src "libresoc.v:62415.3-62427.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62299.3-62311.6" + attribute \src "libresoc.v:62402.3-62414.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62325.3-62337.6" + attribute \src "libresoc.v:62428.3-62440.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61254.7-61254.20" + attribute \src "libresoc.v:61357.7-61357.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62273.3-62285.6" + attribute \src "libresoc.v:62376.3-62388.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62286.3-62298.6" + attribute \src "libresoc.v:62389.3-62401.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62234.3-62246.6" + attribute \src "libresoc.v:62337.3-62349.6" wire width 14 $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62260.3-62272.6" + attribute \src "libresoc.v:62363.3-62375.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62247.3-62259.6" + attribute \src "libresoc.v:62350.3-62362.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62312.3-62324.6" + attribute \src "libresoc.v:62415.3-62427.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62299.3-62311.6" + attribute \src "libresoc.v:62402.3-62414.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62325.3-62337.6" + attribute \src "libresoc.v:62428.3-62440.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62222.17-62222.211" - wire width 32 $ternary$libresoc.v:62222$3515_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:62325.17-62325.211" + wire width 32 $ternary$libresoc.v:62325$3531_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 18 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \MUL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \MUL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \MUL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \MUL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 15 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \MUL_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 16 \MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 13 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 11 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -103367,7 +103623,7 @@ module \dec$158 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103376,7 +103632,7 @@ module \dec$158 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -103387,7 +103643,7 @@ module \dec$158 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103396,7 +103652,7 @@ module \dec$158 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -103413,7 +103669,7 @@ module \dec$158 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103430,7 +103686,7 @@ module \dec$158 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103507,19 +103763,19 @@ module \dec$158 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -103536,7 +103792,7 @@ module \dec$158 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103553,7 +103809,7 @@ module \dec$158 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103630,480 +103886,480 @@ module \dec$158 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:61254.7-61254.15" + attribute \src "libresoc.v:61357.7-61357.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:62222$3515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:62325$3531 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62222$3515_Y + connect \Y $ternary$libresoc.v:62325$3531_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62223.13-62233.4" + attribute \src "libresoc.v:62326.13-62336.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104115,26 +104371,26 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61254.7-61254.20" - process $proc$libresoc.v:61254$3524 + attribute \src "libresoc.v:61357.7-61357.20" + process $proc$libresoc.v:61357$3540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62234.3-62246.6" - process $proc$libresoc.v:62234$3516 + attribute \src "libresoc.v:62337.3-62349.6" + process $proc$libresoc.v:62337$3532 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62235.5-62235.29" + attribute \src "libresoc.v:62338.5-62338.29" switch \initial - attribute \src "libresoc.v:62235.9-62235.17" + attribute \src "libresoc.v:62338.9-62338.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104150,18 +104406,18 @@ module \dec$158 sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:62247.3-62259.6" - process $proc$libresoc.v:62247$3517 + attribute \src "libresoc.v:62350.3-62362.6" + process $proc$libresoc.v:62350$3533 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62248.5-62248.29" + attribute \src "libresoc.v:62351.5-62351.29" switch \initial - attribute \src "libresoc.v:62248.9-62248.17" + attribute \src "libresoc.v:62351.9-62351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104177,18 +104433,18 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62260.3-62272.6" - process $proc$libresoc.v:62260$3518 + attribute \src "libresoc.v:62363.3-62375.6" + process $proc$libresoc.v:62363$3534 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62261.5-62261.29" + attribute \src "libresoc.v:62364.5-62364.29" switch \initial - attribute \src "libresoc.v:62261.9-62261.17" + attribute \src "libresoc.v:62364.9-62364.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104204,18 +104460,18 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62273.3-62285.6" - process $proc$libresoc.v:62273$3519 + attribute \src "libresoc.v:62376.3-62388.6" + process $proc$libresoc.v:62376$3535 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62274.5-62274.29" + attribute \src "libresoc.v:62377.5-62377.29" switch \initial - attribute \src "libresoc.v:62274.9-62274.17" + attribute \src "libresoc.v:62377.9-62377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104231,18 +104487,18 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62286.3-62298.6" - process $proc$libresoc.v:62286$3520 + attribute \src "libresoc.v:62389.3-62401.6" + process $proc$libresoc.v:62389$3536 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62287.5-62287.29" + attribute \src "libresoc.v:62390.5-62390.29" switch \initial - attribute \src "libresoc.v:62287.9-62287.17" + attribute \src "libresoc.v:62390.9-62390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104258,18 +104514,18 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62299.3-62311.6" - process $proc$libresoc.v:62299$3521 + attribute \src "libresoc.v:62402.3-62414.6" + process $proc$libresoc.v:62402$3537 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62300.5-62300.29" + attribute \src "libresoc.v:62403.5-62403.29" switch \initial - attribute \src "libresoc.v:62300.9-62300.17" + attribute \src "libresoc.v:62403.9-62403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104285,18 +104541,18 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62312.3-62324.6" - process $proc$libresoc.v:62312$3522 + attribute \src "libresoc.v:62415.3-62427.6" + process $proc$libresoc.v:62415$3538 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62313.5-62313.29" + attribute \src "libresoc.v:62416.5-62416.29" switch \initial - attribute \src "libresoc.v:62313.9-62313.17" + attribute \src "libresoc.v:62416.9-62416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104312,18 +104568,18 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62325.3-62337.6" - process $proc$libresoc.v:62325$3523 + attribute \src "libresoc.v:62428.3-62440.6" + process $proc$libresoc.v:62428$3539 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62326.5-62326.29" + attribute \src "libresoc.v:62429.5-62429.29" switch \initial - attribute \src "libresoc.v:62326.9-62326.17" + attribute \src "libresoc.v:62429.9-62429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -104339,7 +104595,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62222$3515_Y + connect \$1 $ternary$libresoc.v:62325$3531_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104677,304 +104933,304 @@ module \dec$158 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62678.1-64432.10" +attribute \src "libresoc.v:62781.1-64535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:64007.3-64028.6" + attribute \src "libresoc.v:64110.3-64131.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64029.3-64050.6" + attribute \src "libresoc.v:64132.3-64153.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64073.3-64094.6" + attribute \src "libresoc.v:64176.3-64197.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63875.3-63896.6" + attribute \src "libresoc.v:63978.3-63999.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63941.3-63962.6" + attribute \src "libresoc.v:64044.3-64065.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63985.3-64006.6" + attribute \src "libresoc.v:64088.3-64109.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63963.3-63984.6" + attribute \src "libresoc.v:64066.3-64087.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63853.3-63874.6" + attribute \src "libresoc.v:63956.3-63977.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63897.3-63918.6" + attribute \src "libresoc.v:64000.3-64021.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64051.3-64072.6" + attribute \src "libresoc.v:64154.3-64175.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63919.3-63940.6" + attribute \src "libresoc.v:64022.3-64043.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62679.7-62679.20" + attribute \src "libresoc.v:62782.7-62782.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64007.3-64028.6" + attribute \src "libresoc.v:64110.3-64131.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64029.3-64050.6" + attribute \src "libresoc.v:64132.3-64153.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64073.3-64094.6" + attribute \src "libresoc.v:64176.3-64197.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63875.3-63896.6" + attribute \src "libresoc.v:63978.3-63999.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63941.3-63962.6" + attribute \src "libresoc.v:64044.3-64065.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63985.3-64006.6" + attribute \src "libresoc.v:64088.3-64109.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63963.3-63984.6" + attribute \src "libresoc.v:64066.3-64087.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63853.3-63874.6" + attribute \src "libresoc.v:63956.3-63977.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63897.3-63918.6" + attribute \src "libresoc.v:64000.3-64021.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64051.3-64072.6" + attribute \src "libresoc.v:64154.3-64175.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63919.3-63940.6" + attribute \src "libresoc.v:64022.3-64043.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63824.17-63824.211" - wire width 32 $ternary$libresoc.v:63824$3525_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:63927.17-63927.211" + wire width 32 $ternary$libresoc.v:63927$3541_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 22 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SHIFT_ROT_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SHIFT_ROT_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 23 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 19 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 21 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SHIFT_ROT_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 20 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 15 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 16 \SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -104985,7 +105241,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -104994,15 +105250,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 11 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \SHIFT_ROT_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105013,7 +105269,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105022,15 +105278,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105047,7 +105303,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105064,7 +105320,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105141,21 +105397,21 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec30_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105166,7 +105422,7 @@ module \dec$162 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105175,15 +105431,15 @@ module \dec$162 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105200,7 +105456,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105217,7 +105473,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105294,21 +105550,21 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -105325,7 +105581,7 @@ module \dec$162 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105342,7 +105598,7 @@ module \dec$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105419,462 +105675,462 @@ module \dec$162 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 18 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:62679.7-62679.15" + attribute \src "libresoc.v:62782.7-62782.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:63824$3525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:63927$3541 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63824$3525_Y + connect \Y $ternary$libresoc.v:63927$3541_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63825.19-63838.4" + attribute \src "libresoc.v:63928.19-63941.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -105890,7 +106146,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63839.19-63852.4" + attribute \src "libresoc.v:63942.19-63955.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -105905,26 +106161,26 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62679.7-62679.20" - process $proc$libresoc.v:62679$3537 + attribute \src "libresoc.v:62782.7-62782.20" + process $proc$libresoc.v:62782$3553 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63853.3-63874.6" - process $proc$libresoc.v:63853$3526 + attribute \src "libresoc.v:63956.3-63977.6" + process $proc$libresoc.v:63956$3542 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63854.5-63854.29" + attribute \src "libresoc.v:63957.5-63957.29" switch \initial - attribute \src "libresoc.v:63854.9-63854.17" + attribute \src "libresoc.v:63957.9-63957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105952,18 +106208,18 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63875.3-63896.6" - process $proc$libresoc.v:63875$3527 + attribute \src "libresoc.v:63978.3-63999.6" + process $proc$libresoc.v:63978$3543 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63876.5-63876.29" + attribute \src "libresoc.v:63979.5-63979.29" switch \initial - attribute \src "libresoc.v:63876.9-63876.17" + attribute \src "libresoc.v:63979.9-63979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -105991,18 +106247,18 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63897.3-63918.6" - process $proc$libresoc.v:63897$3528 + attribute \src "libresoc.v:64000.3-64021.6" + process $proc$libresoc.v:64000$3544 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63898.5-63898.29" + attribute \src "libresoc.v:64001.5-64001.29" switch \initial - attribute \src "libresoc.v:63898.9-63898.17" + attribute \src "libresoc.v:64001.9-64001.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106030,18 +106286,18 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63919.3-63940.6" - process $proc$libresoc.v:63919$3529 + attribute \src "libresoc.v:64022.3-64043.6" + process $proc$libresoc.v:64022$3545 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63920.5-63920.29" + attribute \src "libresoc.v:64023.5-64023.29" switch \initial - attribute \src "libresoc.v:63920.9-63920.17" + attribute \src "libresoc.v:64023.9-64023.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106069,18 +106325,18 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:63941.3-63962.6" - process $proc$libresoc.v:63941$3530 + attribute \src "libresoc.v:64044.3-64065.6" + process $proc$libresoc.v:64044$3546 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:63942.5-63942.29" + attribute \src "libresoc.v:64045.5-64045.29" switch \initial - attribute \src "libresoc.v:63942.9-63942.17" + attribute \src "libresoc.v:64045.9-64045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106108,18 +106364,18 @@ module \dec$162 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:63963.3-63984.6" - process $proc$libresoc.v:63963$3531 + attribute \src "libresoc.v:64066.3-64087.6" + process $proc$libresoc.v:64066$3547 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63964.5-63964.29" + attribute \src "libresoc.v:64067.5-64067.29" switch \initial - attribute \src "libresoc.v:63964.9-63964.17" + attribute \src "libresoc.v:64067.9-64067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106147,18 +106403,18 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:63985.3-64006.6" - process $proc$libresoc.v:63985$3532 + attribute \src "libresoc.v:64088.3-64109.6" + process $proc$libresoc.v:64088$3548 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63986.5-63986.29" + attribute \src "libresoc.v:64089.5-64089.29" switch \initial - attribute \src "libresoc.v:63986.9-63986.17" + attribute \src "libresoc.v:64089.9-64089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106186,18 +106442,18 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:64007.3-64028.6" - process $proc$libresoc.v:64007$3533 + attribute \src "libresoc.v:64110.3-64131.6" + process $proc$libresoc.v:64110$3549 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64008.5-64008.29" + attribute \src "libresoc.v:64111.5-64111.29" switch \initial - attribute \src "libresoc.v:64008.9-64008.17" + attribute \src "libresoc.v:64111.9-64111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106225,18 +106481,18 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64029.3-64050.6" - process $proc$libresoc.v:64029$3534 + attribute \src "libresoc.v:64132.3-64153.6" + process $proc$libresoc.v:64132$3550 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64030.5-64030.29" + attribute \src "libresoc.v:64133.5-64133.29" switch \initial - attribute \src "libresoc.v:64030.9-64030.17" + attribute \src "libresoc.v:64133.9-64133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106264,18 +106520,18 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64051.3-64072.6" - process $proc$libresoc.v:64051$3535 + attribute \src "libresoc.v:64154.3-64175.6" + process $proc$libresoc.v:64154$3551 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64052.5-64052.29" + attribute \src "libresoc.v:64155.5-64155.29" switch \initial - attribute \src "libresoc.v:64052.9-64052.17" + attribute \src "libresoc.v:64155.9-64155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106303,18 +106559,18 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64073.3-64094.6" - process $proc$libresoc.v:64073$3536 + attribute \src "libresoc.v:64176.3-64197.6" + process $proc$libresoc.v:64176$3552 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64074.5-64074.29" + attribute \src "libresoc.v:64177.5-64177.29" switch \initial - attribute \src "libresoc.v:64074.9-64074.17" + attribute \src "libresoc.v:64177.9-64177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -106342,7 +106598,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63824$3525_Y + connect \$1 $ternary$libresoc.v:63927$3541_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106681,258 +106937,258 @@ module \dec$162 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64436.1-66945.10" +attribute \src "libresoc.v:64539.1-67048.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:66027.3-66084.6" + attribute \src "libresoc.v:66130.3-66187.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66491.3-66548.6" + attribute \src "libresoc.v:66594.3-66651.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66549.3-66606.6" + attribute \src "libresoc.v:66652.3-66709.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66259.3-66316.6" + attribute \src "libresoc.v:66362.3-66419.6" wire width 14 $0\LDST_function_unit[13:0] - attribute \src "libresoc.v:66375.3-66432.6" + attribute \src "libresoc.v:66478.3-66535.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66433.3-66490.6" + attribute \src "libresoc.v:66536.3-66593.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66317.3-66374.6" + attribute \src "libresoc.v:66420.3-66477.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66143.3-66200.6" + attribute \src "libresoc.v:66246.3-66303.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65853.3-65910.6" + attribute \src "libresoc.v:65956.3-66013.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65969.3-66026.6" + attribute \src "libresoc.v:66072.3-66129.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66201.3-66258.6" + attribute \src "libresoc.v:66304.3-66361.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66085.3-66142.6" + attribute \src "libresoc.v:66188.3-66245.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65911.3-65968.6" + attribute \src "libresoc.v:66014.3-66071.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64437.7-64437.20" + attribute \src "libresoc.v:64540.7-64540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66027.3-66084.6" + attribute \src "libresoc.v:66130.3-66187.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66491.3-66548.6" + attribute \src "libresoc.v:66594.3-66651.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66549.3-66606.6" + attribute \src "libresoc.v:66652.3-66709.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66259.3-66316.6" + attribute \src "libresoc.v:66362.3-66419.6" wire width 14 $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66375.3-66432.6" + attribute \src "libresoc.v:66478.3-66535.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66433.3-66490.6" + attribute \src "libresoc.v:66536.3-66593.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66317.3-66374.6" + attribute \src "libresoc.v:66420.3-66477.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66143.3-66200.6" + attribute \src "libresoc.v:66246.3-66303.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65853.3-65910.6" + attribute \src "libresoc.v:65956.3-66013.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65969.3-66026.6" + attribute \src "libresoc.v:66072.3-66129.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66201.3-66258.6" + attribute \src "libresoc.v:66304.3-66361.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66085.3-66142.6" + attribute \src "libresoc.v:66188.3-66245.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65911.3-65968.6" + attribute \src "libresoc.v:66014.3-66071.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65804.17-65804.211" - wire width 32 $ternary$libresoc.v:65804$3538_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:65907.17-65907.211" + wire width 32 $ternary$libresoc.v:65907$3554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 24 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LDST_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LDST_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LDST_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LDST_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 21 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LDST_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 16 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 22 \LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 17 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106943,7 +107199,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106952,9 +107208,9 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -106965,7 +107221,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -106974,7 +107230,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -106991,7 +107247,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -106999,7 +107255,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107016,7 +107272,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107093,9 +107349,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107103,28 +107359,28 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -107135,7 +107391,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -107144,7 +107400,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107161,7 +107417,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107169,7 +107425,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107186,7 +107442,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107263,9 +107519,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec58_LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107273,28 +107529,28 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -107305,7 +107561,7 @@ module \dec$166 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -107314,7 +107570,7 @@ module \dec$166 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107331,7 +107587,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107339,7 +107595,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107356,7 +107612,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107433,9 +107689,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec62_LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107443,26 +107699,26 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -107479,7 +107735,7 @@ module \dec$166 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -107487,7 +107743,7 @@ module \dec$166 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -107504,7 +107760,7 @@ module \dec$166 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -107581,9 +107837,9 @@ module \dec$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -107591,523 +107847,523 @@ module \dec$166 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:64437.7-64437.15" + attribute \src "libresoc.v:64540.7-64540.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 26 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:65804$3538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:65907$3554 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65804$3538_Y + connect \Y $ternary$libresoc.v:65907$3554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65805.14-65820.4" + attribute \src "libresoc.v:65908.14-65923.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108125,7 +108381,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65821.14-65836.4" + attribute \src "libresoc.v:65924.14-65939.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108143,7 +108399,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65837.14-65852.4" + attribute \src "libresoc.v:65940.14-65955.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108160,26 +108416,26 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64437.7-64437.20" - process $proc$libresoc.v:64437$3552 + attribute \src "libresoc.v:64540.7-64540.20" + process $proc$libresoc.v:64540$3568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65853.3-65910.6" - process $proc$libresoc.v:65853$3539 + attribute \src "libresoc.v:65956.3-66013.6" + process $proc$libresoc.v:65956$3555 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65854.5-65854.29" + attribute \src "libresoc.v:65957.5-65957.29" switch \initial - attribute \src "libresoc.v:65854.9-65854.17" + attribute \src "libresoc.v:65957.9-65957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108255,18 +108511,18 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65911.3-65968.6" - process $proc$libresoc.v:65911$3540 + attribute \src "libresoc.v:66014.3-66071.6" + process $proc$libresoc.v:66014$3556 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65912.5-65912.29" + attribute \src "libresoc.v:66015.5-66015.29" switch \initial - attribute \src "libresoc.v:65912.9-65912.17" + attribute \src "libresoc.v:66015.9-66015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108342,18 +108598,18 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:65969.3-66026.6" - process $proc$libresoc.v:65969$3541 + attribute \src "libresoc.v:66072.3-66129.6" + process $proc$libresoc.v:66072$3557 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65970.5-65970.29" + attribute \src "libresoc.v:66073.5-66073.29" switch \initial - attribute \src "libresoc.v:65970.9-65970.17" + attribute \src "libresoc.v:66073.9-66073.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108429,18 +108685,18 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66027.3-66084.6" - process $proc$libresoc.v:66027$3542 + attribute \src "libresoc.v:66130.3-66187.6" + process $proc$libresoc.v:66130$3558 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66028.5-66028.29" + attribute \src "libresoc.v:66131.5-66131.29" switch \initial - attribute \src "libresoc.v:66028.9-66028.17" + attribute \src "libresoc.v:66131.9-66131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108516,18 +108772,18 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66085.3-66142.6" - process $proc$libresoc.v:66085$3543 + attribute \src "libresoc.v:66188.3-66245.6" + process $proc$libresoc.v:66188$3559 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66086.5-66086.29" + attribute \src "libresoc.v:66189.5-66189.29" switch \initial - attribute \src "libresoc.v:66086.9-66086.17" + attribute \src "libresoc.v:66189.9-66189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108603,18 +108859,18 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66143.3-66200.6" - process $proc$libresoc.v:66143$3544 + attribute \src "libresoc.v:66246.3-66303.6" + process $proc$libresoc.v:66246$3560 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66144.5-66144.29" + attribute \src "libresoc.v:66247.5-66247.29" switch \initial - attribute \src "libresoc.v:66144.9-66144.17" + attribute \src "libresoc.v:66247.9-66247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108690,18 +108946,18 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66201.3-66258.6" - process $proc$libresoc.v:66201$3545 + attribute \src "libresoc.v:66304.3-66361.6" + process $proc$libresoc.v:66304$3561 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66202.5-66202.29" + attribute \src "libresoc.v:66305.5-66305.29" switch \initial - attribute \src "libresoc.v:66202.9-66202.17" + attribute \src "libresoc.v:66305.9-66305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108777,18 +109033,18 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66259.3-66316.6" - process $proc$libresoc.v:66259$3546 + attribute \src "libresoc.v:66362.3-66419.6" + process $proc$libresoc.v:66362$3562 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66260.5-66260.29" + attribute \src "libresoc.v:66363.5-66363.29" switch \initial - attribute \src "libresoc.v:66260.9-66260.17" + attribute \src "libresoc.v:66363.9-66363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108864,18 +109120,18 @@ module \dec$166 sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:66317.3-66374.6" - process $proc$libresoc.v:66317$3547 + attribute \src "libresoc.v:66420.3-66477.6" + process $proc$libresoc.v:66420$3563 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66318.5-66318.29" + attribute \src "libresoc.v:66421.5-66421.29" switch \initial - attribute \src "libresoc.v:66318.9-66318.17" + attribute \src "libresoc.v:66421.9-66421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -108951,18 +109207,18 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66375.3-66432.6" - process $proc$libresoc.v:66375$3548 + attribute \src "libresoc.v:66478.3-66535.6" + process $proc$libresoc.v:66478$3564 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66376.5-66376.29" + attribute \src "libresoc.v:66479.5-66479.29" switch \initial - attribute \src "libresoc.v:66376.9-66376.17" + attribute \src "libresoc.v:66479.9-66479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109038,18 +109294,18 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66433.3-66490.6" - process $proc$libresoc.v:66433$3549 + attribute \src "libresoc.v:66536.3-66593.6" + process $proc$libresoc.v:66536$3565 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66434.5-66434.29" + attribute \src "libresoc.v:66537.5-66537.29" switch \initial - attribute \src "libresoc.v:66434.9-66434.17" + attribute \src "libresoc.v:66537.9-66537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109125,18 +109381,18 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66491.3-66548.6" - process $proc$libresoc.v:66491$3550 + attribute \src "libresoc.v:66594.3-66651.6" + process $proc$libresoc.v:66594$3566 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66492.5-66492.29" + attribute \src "libresoc.v:66595.5-66595.29" switch \initial - attribute \src "libresoc.v:66492.9-66492.17" + attribute \src "libresoc.v:66595.9-66595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109212,18 +109468,18 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66549.3-66606.6" - process $proc$libresoc.v:66549$3551 + attribute \src "libresoc.v:66652.3-66709.6" + process $proc$libresoc.v:66652$3567 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66550.5-66550.29" + attribute \src "libresoc.v:66653.5-66653.29" switch \initial - attribute \src "libresoc.v:66550.9-66550.17" + attribute \src "libresoc.v:66653.9-66653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -109299,7 +109555,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65804$3538_Y + connect \$1 $ternary$libresoc.v:65907$3554_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109639,890 +109895,896 @@ module \dec$166 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:66949.1-74952.10" +attribute \src "libresoc.v:67052.1-75269.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $0\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $0\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:66950.7-66950.20" + attribute \src "libresoc.v:67053.7-67053.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $0\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $0\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $0\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $1\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $1\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $1\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $1\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $1\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:70260.3-70404.6" + attribute \src "libresoc.v:70432.3-70576.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:70405.3-70549.6" + attribute \src "libresoc.v:70577.3-70721.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70118.3-70259.6" + attribute \src "libresoc.v:70290.3-70431.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:73305.3-73449.6" + attribute \src "libresoc.v:73622.3-73766.6" wire $2\br[0:0] - attribute \src "libresoc.v:71130.3-71274.6" + attribute \src "libresoc.v:71302.3-71446.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:71275.3-71419.6" + attribute \src "libresoc.v:71447.3-71591.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:72725.3-72869.6" + attribute \src "libresoc.v:73042.3-73186.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:73160.3-73304.6" + attribute \src "libresoc.v:73477.3-73621.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:69973.3-70117.6" + attribute \src "libresoc.v:70145.3-70289.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:74320.3-74464.6" + attribute \src "libresoc.v:74637.3-74781.6" wire width 14 $2\function_unit[13:0] - attribute \src "libresoc.v:70550.3-70694.6" + attribute \src "libresoc.v:70722.3-70866.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70695.3-70839.6" + attribute \src "libresoc.v:70867.3-71011.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:70840.3-70984.6" + attribute \src "libresoc.v:71012.3-71156.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:74465.3-74609.6" + attribute \src "libresoc.v:74782.3-74926.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:72870.3-73014.6" + attribute \src "libresoc.v:73187.3-73331.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:73015.3-73159.6" + attribute \src "libresoc.v:73332.3-73476.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:73740.3-73884.6" + attribute \src "libresoc.v:74057.3-74201.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:72290.3-72434.6" + attribute \src "libresoc.v:72607.3-72751.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:74030.3-74174.6" + attribute \src "libresoc.v:74347.3-74491.6" wire $2\lk[0:0] - attribute \src "libresoc.v:70985.3-71129.6" + attribute \src "libresoc.v:71157.3-71301.6" wire width 3 $2\out_sel[2:0] - attribute \src "libresoc.v:72580.3-72724.6" + attribute \src "libresoc.v:72897.3-73041.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73595.3-73739.6" + attribute \src "libresoc.v:73912.3-74056.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:74175.3-74319.6" + attribute \src "libresoc.v:74492.3-74636.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:73885.3-74029.6" + attribute \src "libresoc.v:74202.3-74346.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:73450.3-73594.6" + attribute \src "libresoc.v:73767.3-73911.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:72000.3-72144.6" + attribute \src "libresoc.v:72317.3-72461.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72145.3-72289.6" + attribute \src "libresoc.v:72462.3-72606.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71420.3-71564.6" + attribute \src "libresoc.v:71592.3-71736.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71565.3-71709.6" + attribute \src "libresoc.v:71737.3-71881.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71710.3-71854.6" + attribute \src "libresoc.v:71882.3-72026.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:71855.3-71999.6" + attribute \src "libresoc.v:72172.3-72316.6" + wire width 3 $2\sv_out2[2:0] + attribute \src "libresoc.v:72027.3-72171.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:72435.3-72579.6" + attribute \src "libresoc.v:72752.3-72896.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69762.17-69762.211" - wire width 32 $ternary$libresoc.v:69762$3553_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + attribute \src "libresoc.v:69928.17-69928.211" + wire width 32 $ternary$libresoc.v:69928$3569_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 26 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 25 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 31 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 30 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 29 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 27 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 output 28 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 21 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 22 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src 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wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 17 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 36 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110533,7 +110795,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110542,31 +110804,31 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec19_dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110577,7 +110839,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110586,15 +110848,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110627,7 +110889,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -110644,7 +110906,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110652,7 +110914,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110669,13 +110931,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110752,13 +111014,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec19_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110766,9 +111028,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -110776,21 +111038,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110799,7 +111061,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110808,7 +111070,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110817,7 +111079,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110826,7 +111088,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110835,7 +111097,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -110844,32 +111106,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec19_dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec19_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec22_dec22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -110880,7 +111151,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -110889,15 +111160,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110930,7 +111201,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec22_dec22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -110947,7 +111218,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec22_dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110955,7 +111226,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110972,13 +111243,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec22_dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111055,13 +111326,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec22_dec22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111069,9 +111340,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec22_dec22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111079,21 +111350,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111102,7 +111373,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111111,7 +111382,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111120,7 +111391,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111129,7 +111400,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111138,7 +111409,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111147,32 +111418,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec22_dec22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec22_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec30_dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111183,7 +111463,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111192,15 +111472,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111233,7 +111513,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111250,7 +111530,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111258,7 +111538,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111275,13 +111555,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec30_dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111358,13 +111638,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec30_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111372,9 +111652,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec30_dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111382,21 +111662,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec30_dec30_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111405,7 +111685,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111414,7 +111694,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111423,7 +111703,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111432,7 +111712,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111441,7 +111721,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111450,32 +111730,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec30_dec30_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec30_dec30_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec30_dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec30_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111486,7 +111775,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111495,15 +111784,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111536,7 +111825,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111553,7 +111842,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111561,7 +111850,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111578,13 +111867,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111661,13 +111950,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111675,9 +111964,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111685,21 +111974,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec31_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111708,7 +111997,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111717,7 +112006,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111726,7 +112015,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111735,7 +112024,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111744,7 +112033,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -111753,32 +112042,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec31_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec31_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec58_dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -111789,7 +112087,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -111798,15 +112096,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -111839,7 +112137,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -111856,7 +112154,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec58_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -111864,7 +112162,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -111881,13 +112179,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec58_dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -111964,13 +112262,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec58_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -111978,9 +112276,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec58_dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -111988,21 +112286,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec58_dec58_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112011,7 +112309,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112020,7 +112318,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112029,7 +112327,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112038,7 +112336,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112047,7 +112345,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112056,32 +112354,41 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec58_dec58_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec58_dec58_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec58_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec58_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec62_dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -112092,7 +112399,7 @@ module \dec$171 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -112101,15 +112408,15 @@ module \dec$171 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -112142,7 +112449,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -112159,7 +112466,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec62_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -112167,7 +112474,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -112184,13 +112491,13 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec62_dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112267,13 +112574,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec62_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -112281,9 +112588,9 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec62_dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -112291,21 +112598,21 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec62_dec62_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112314,7 +112621,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112323,7 +112630,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112332,7 +112639,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112341,7 +112648,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112350,7 +112657,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112359,16 +112666,25 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec62_dec62_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec62_dec62_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec62_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -112401,7 +112717,7 @@ module \dec$171 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -112418,7 +112734,7 @@ module \dec$171 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -112426,7 +112742,7 @@ module \dec$171 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -112443,15 +112759,15 @@ module \dec$171 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 14 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:66950.7-66950.15" + attribute \src "libresoc.v:67053.7-67053.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112528,13 +112844,13 @@ module \dec$171 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -112542,15 +112858,15 @@ module \dec$171 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -112558,25 +112874,25 @@ module \dec$171 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \sh attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112585,7 +112901,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112594,7 +112910,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112603,7 +112919,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112612,7 +112928,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112621,7 +112937,7 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -112630,25 +112946,34 @@ module \dec$171 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:69762$3553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" + cell $mux $ternary$libresoc.v:69928$3569 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69762$3553_Y + connect \Y $ternary$libresoc.v:69928$3569_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69763.9-69797.4" + attribute \src "libresoc.v:69929.9-69964.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -112681,11 +113006,12 @@ module \dec$171 connect \dec19_sv_in2 \dec19_dec19_sv_in2 connect \dec19_sv_in3 \dec19_dec19_sv_in3 connect \dec19_sv_out \dec19_dec19_sv_out + connect \dec19_sv_out2 \dec19_dec19_sv_out2 connect \dec19_upd \dec19_dec19_upd connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69798.9-69832.4" + attribute \src "libresoc.v:69965.9-70000.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype @@ -112718,11 +113044,12 @@ module \dec$171 connect \dec22_sv_in2 \dec22_dec22_sv_in2 connect \dec22_sv_in3 \dec22_dec22_sv_in3 connect \dec22_sv_out \dec22_dec22_sv_out + connect \dec22_sv_out2 \dec22_dec22_sv_out2 connect \dec22_upd \dec22_dec22_upd connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69833.9-69867.4" + attribute \src "libresoc.v:70001.9-70036.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -112755,11 +113082,12 @@ module \dec$171 connect \dec30_sv_in2 \dec30_dec30_sv_in2 connect \dec30_sv_in3 \dec30_dec30_sv_in3 connect \dec30_sv_out \dec30_dec30_sv_out + connect \dec30_sv_out2 \dec30_dec30_sv_out2 connect \dec30_upd \dec30_dec30_upd connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69868.9-69902.4" + attribute \src "libresoc.v:70037.9-70072.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -112792,11 +113120,12 @@ module \dec$171 connect \dec31_sv_in2 \dec31_dec31_sv_in2 connect \dec31_sv_in3 \dec31_dec31_sv_in3 connect \dec31_sv_out \dec31_dec31_sv_out + connect \dec31_sv_out2 \dec31_dec31_sv_out2 connect \dec31_upd \dec31_dec31_upd connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69903.9-69937.4" + attribute \src "libresoc.v:70073.9-70108.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -112829,11 +113158,12 @@ module \dec$171 connect \dec58_sv_in2 \dec58_dec58_sv_in2 connect \dec58_sv_in3 \dec58_dec58_sv_in3 connect \dec58_sv_out \dec58_dec58_sv_out + connect \dec58_sv_out2 \dec58_dec58_sv_out2 connect \dec58_upd \dec58_dec58_upd connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69938.9-69972.4" + attribute \src "libresoc.v:70109.9-70144.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -112866,30 +113196,31 @@ module \dec$171 connect \dec62_sv_in2 \dec62_dec62_sv_in2 connect \dec62_sv_in3 \dec62_dec62_sv_in3 connect \dec62_sv_out \dec62_dec62_sv_out + connect \dec62_sv_out2 \dec62_dec62_sv_out2 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:66950.7-66950.20" - process $proc$libresoc.v:66950$3586 + attribute \src "libresoc.v:67053.7-67053.20" + process $proc$libresoc.v:67053$3603 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:69973.3-70117.6" - process $proc$libresoc.v:69973$3554 + attribute \src "libresoc.v:70145.3-70289.6" + process $proc$libresoc.v:70145$3570 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:69974.5-69974.29" + attribute \src "libresoc.v:70146.5-70146.29" switch \initial - attribute \src "libresoc.v:69974.9-69974.17" + attribute \src "libresoc.v:70146.9-70146.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113062,7 +113393,7 @@ module \dec$171 case assign $1\form[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113082,19 +113413,19 @@ module \dec$171 sync always update \form $0\form[4:0] end - attribute \src "libresoc.v:70118.3-70259.6" - process $proc$libresoc.v:70118$3555 + attribute \src "libresoc.v:70290.3-70431.6" + process $proc$libresoc.v:70290$3571 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:70119.5-70119.29" + attribute \src "libresoc.v:70291.5-70291.29" switch \initial - attribute \src "libresoc.v:70119.9-70119.17" + attribute \src "libresoc.v:70291.9-70291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113263,7 +113594,7 @@ module \dec$171 case assign $1\asmcode[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113283,19 +113614,19 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:70260.3-70404.6" - process $proc$libresoc.v:70260$3556 + attribute \src "libresoc.v:70432.3-70576.6" + process $proc$libresoc.v:70432$3572 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:70261.5-70261.29" + attribute \src "libresoc.v:70433.5-70433.29" switch \initial - attribute \src "libresoc.v:70261.9-70261.17" + attribute \src "libresoc.v:70433.9-70433.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113468,7 +113799,7 @@ module \dec$171 case assign $1\SV_Etype[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113488,19 +113819,19 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:70405.3-70549.6" - process $proc$libresoc.v:70405$3557 + attribute \src "libresoc.v:70577.3-70721.6" + process $proc$libresoc.v:70577$3573 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70406.5-70406.29" + attribute \src "libresoc.v:70578.5-70578.29" switch \initial - attribute \src "libresoc.v:70406.9-70406.17" + attribute \src "libresoc.v:70578.9-70578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113673,7 +114004,7 @@ module \dec$171 case assign $1\SV_Ptype[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113693,19 +114024,19 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70550.3-70694.6" - process $proc$libresoc.v:70550$3558 + attribute \src "libresoc.v:70722.3-70866.6" + process $proc$libresoc.v:70722$3574 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70551.5-70551.29" + attribute \src "libresoc.v:70723.5-70723.29" switch \initial - attribute \src "libresoc.v:70551.9-70551.17" + attribute \src "libresoc.v:70723.9-70723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113878,7 +114209,7 @@ module \dec$171 case assign $1\in1_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113898,19 +114229,19 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70695.3-70839.6" - process $proc$libresoc.v:70695$3559 + attribute \src "libresoc.v:70867.3-71011.6" + process $proc$libresoc.v:70867$3575 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70696.5-70696.29" + attribute \src "libresoc.v:70868.5-70868.29" switch \initial - attribute \src "libresoc.v:70696.9-70696.17" + attribute \src "libresoc.v:70868.9-70868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114083,7 +114414,7 @@ module \dec$171 case assign $1\in2_sel[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114103,19 +114434,19 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:70840.3-70984.6" - process $proc$libresoc.v:70840$3560 + attribute \src "libresoc.v:71012.3-71156.6" + process $proc$libresoc.v:71012$3576 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:70841.5-70841.29" + attribute \src "libresoc.v:71013.5-71013.29" switch \initial - attribute \src "libresoc.v:70841.9-70841.17" + attribute \src "libresoc.v:71013.9-71013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114288,7 +114619,7 @@ module \dec$171 case assign $1\in3_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114308,19 +114639,19 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:70985.3-71129.6" - process $proc$libresoc.v:70985$3561 + attribute \src "libresoc.v:71157.3-71301.6" + process $proc$libresoc.v:71157$3577 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] - attribute \src "libresoc.v:70986.5-70986.29" + attribute \src "libresoc.v:71158.5-71158.29" switch \initial - attribute \src "libresoc.v:70986.9-70986.17" + attribute \src "libresoc.v:71158.9-71158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114493,7 +114824,7 @@ module \dec$171 case assign $1\out_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114513,19 +114844,19 @@ module \dec$171 sync always update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:71130.3-71274.6" - process $proc$libresoc.v:71130$3562 + attribute \src "libresoc.v:71302.3-71446.6" + process $proc$libresoc.v:71302$3578 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:71131.5-71131.29" + attribute \src "libresoc.v:71303.5-71303.29" switch \initial - attribute \src "libresoc.v:71131.9-71131.17" + attribute \src "libresoc.v:71303.9-71303.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114698,7 +115029,7 @@ module \dec$171 case assign $1\cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114718,19 +115049,19 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:71275.3-71419.6" - process $proc$libresoc.v:71275$3563 + attribute \src "libresoc.v:71447.3-71591.6" + process $proc$libresoc.v:71447$3579 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:71276.5-71276.29" + attribute \src "libresoc.v:71448.5-71448.29" switch \initial - attribute \src "libresoc.v:71276.9-71276.17" + attribute \src "libresoc.v:71448.9-71448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114903,7 +115234,7 @@ module \dec$171 case assign $1\cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114923,19 +115254,19 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:71420.3-71564.6" - process $proc$libresoc.v:71420$3564 + attribute \src "libresoc.v:71592.3-71736.6" + process $proc$libresoc.v:71592$3580 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:71421.5-71421.29" + attribute \src "libresoc.v:71593.5-71593.29" switch \initial - attribute \src "libresoc.v:71421.9-71421.17" + attribute \src "libresoc.v:71593.9-71593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115108,7 +115439,7 @@ module \dec$171 case assign $1\sv_in1[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115128,19 +115459,19 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71565.3-71709.6" - process $proc$libresoc.v:71565$3565 + attribute \src "libresoc.v:71737.3-71881.6" + process $proc$libresoc.v:71737$3581 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71566.5-71566.29" + attribute \src "libresoc.v:71738.5-71738.29" switch \initial - attribute \src "libresoc.v:71566.9-71566.17" + attribute \src "libresoc.v:71738.9-71738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115313,7 +115644,7 @@ module \dec$171 case assign $1\sv_in2[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115333,19 +115664,19 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71710.3-71854.6" - process $proc$libresoc.v:71710$3566 + attribute \src "libresoc.v:71882.3-72026.6" + process $proc$libresoc.v:71882$3582 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71711.5-71711.29" + attribute \src "libresoc.v:71883.5-71883.29" switch \initial - attribute \src "libresoc.v:71711.9-71711.17" + attribute \src "libresoc.v:71883.9-71883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115518,7 +115849,7 @@ module \dec$171 case assign $1\sv_in3[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115538,19 +115869,19 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:71855.3-71999.6" - process $proc$libresoc.v:71855$3567 + attribute \src "libresoc.v:72027.3-72171.6" + process $proc$libresoc.v:72027$3583 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:71856.5-71856.29" + attribute \src "libresoc.v:72028.5-72028.29" switch \initial - attribute \src "libresoc.v:71856.9-71856.17" + attribute \src "libresoc.v:72028.9-72028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115723,7 +116054,7 @@ module \dec$171 case assign $1\sv_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115743,19 +116074,224 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:72000.3-72144.6" - process $proc$libresoc.v:72000$3568 + attribute \src "libresoc.v:72172.3-72316.6" + process $proc$libresoc.v:72172$3584 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out2[2:0] $2\sv_out2[2:0] + attribute \src "libresoc.v:72173.5-72173.29" + switch \initial + attribute \src "libresoc.v:72173.9-72173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out2[2:0] \dec19_dec19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out2[2:0] \dec30_dec30_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out2[2:0] \dec31_dec31_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out2[2:0] \dec58_dec58_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out2[2:0] \dec62_dec62_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'010110 + assign { } { } + assign $1\sv_out2[2:0] \dec22_dec22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out2[2:0] 3'000 + case + assign $1\sv_out2[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out2[2:0] 3'000 + case + assign $2\sv_out2[2:0] $1\sv_out2[2:0] + end + sync always + update \sv_out2 $0\sv_out2[2:0] + end + attribute \src "libresoc.v:72317.3-72461.6" + process $proc$libresoc.v:72317$3585 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72001.5-72001.29" + attribute \src "libresoc.v:72318.5-72318.29" switch \initial - attribute \src "libresoc.v:72001.9-72001.17" + attribute \src "libresoc.v:72318.9-72318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115928,7 +116464,7 @@ module \dec$171 case assign $1\sv_cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115948,19 +116484,19 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:72145.3-72289.6" - process $proc$libresoc.v:72145$3569 + attribute \src "libresoc.v:72462.3-72606.6" + process $proc$libresoc.v:72462$3586 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:72146.5-72146.29" + attribute \src "libresoc.v:72463.5-72463.29" switch \initial - attribute \src "libresoc.v:72146.9-72146.17" + attribute \src "libresoc.v:72463.9-72463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116133,7 +116669,7 @@ module \dec$171 case assign $1\sv_cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116153,19 +116689,19 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:72290.3-72434.6" - process $proc$libresoc.v:72290$3570 + attribute \src "libresoc.v:72607.3-72751.6" + process $proc$libresoc.v:72607$3587 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:72291.5-72291.29" + attribute \src "libresoc.v:72608.5-72608.29" switch \initial - attribute \src "libresoc.v:72291.9-72291.17" + attribute \src "libresoc.v:72608.9-72608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116338,7 +116874,7 @@ module \dec$171 case assign $1\ldst_len[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116358,19 +116894,19 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:72435.3-72579.6" - process $proc$libresoc.v:72435$3571 + attribute \src "libresoc.v:72752.3-72896.6" + process $proc$libresoc.v:72752$3588 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:72436.5-72436.29" + attribute \src "libresoc.v:72753.5-72753.29" switch \initial - attribute \src "libresoc.v:72436.9-72436.17" + attribute \src "libresoc.v:72753.9-72753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116543,7 +117079,7 @@ module \dec$171 case assign $1\upd[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116563,19 +117099,19 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72580.3-72724.6" - process $proc$libresoc.v:72580$3572 + attribute \src "libresoc.v:72897.3-73041.6" + process $proc$libresoc.v:72897$3589 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72581.5-72581.29" + attribute \src "libresoc.v:72898.5-72898.29" switch \initial - attribute \src "libresoc.v:72581.9-72581.17" + attribute \src "libresoc.v:72898.9-72898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116748,7 +117284,7 @@ module \dec$171 case assign $1\rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116768,19 +117304,19 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:72725.3-72869.6" - process $proc$libresoc.v:72725$3573 + attribute \src "libresoc.v:73042.3-73186.6" + process $proc$libresoc.v:73042$3590 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:72726.5-72726.29" + attribute \src "libresoc.v:73043.5-73043.29" switch \initial - attribute \src "libresoc.v:72726.9-72726.17" + attribute \src "libresoc.v:73043.9-73043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -116953,7 +117489,7 @@ module \dec$171 case assign $1\cry_in[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -116973,19 +117509,19 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:72870.3-73014.6" - process $proc$libresoc.v:72870$3574 + attribute \src "libresoc.v:73187.3-73331.6" + process $proc$libresoc.v:73187$3591 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:72871.5-72871.29" + attribute \src "libresoc.v:73188.5-73188.29" switch \initial - attribute \src "libresoc.v:72871.9-72871.17" + attribute \src "libresoc.v:73188.9-73188.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117158,7 +117694,7 @@ module \dec$171 case assign $1\inv_a[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117178,19 +117714,19 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:73015.3-73159.6" - process $proc$libresoc.v:73015$3575 + attribute \src "libresoc.v:73332.3-73476.6" + process $proc$libresoc.v:73332$3592 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:73016.5-73016.29" + attribute \src "libresoc.v:73333.5-73333.29" switch \initial - attribute \src "libresoc.v:73016.9-73016.17" + attribute \src "libresoc.v:73333.9-73333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117363,7 +117899,7 @@ module \dec$171 case assign $1\inv_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117383,19 +117919,19 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:73160.3-73304.6" - process $proc$libresoc.v:73160$3576 + attribute \src "libresoc.v:73477.3-73621.6" + process $proc$libresoc.v:73477$3593 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:73161.5-73161.29" + attribute \src "libresoc.v:73478.5-73478.29" switch \initial - attribute \src "libresoc.v:73161.9-73161.17" + attribute \src "libresoc.v:73478.9-73478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117568,7 +118104,7 @@ module \dec$171 case assign $1\cry_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117588,19 +118124,19 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:73305.3-73449.6" - process $proc$libresoc.v:73305$3577 + attribute \src "libresoc.v:73622.3-73766.6" + process $proc$libresoc.v:73622$3594 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:73306.5-73306.29" + attribute \src "libresoc.v:73623.5-73623.29" switch \initial - attribute \src "libresoc.v:73306.9-73306.17" + attribute \src "libresoc.v:73623.9-73623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117773,7 +118309,7 @@ module \dec$171 case assign $1\br[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117793,19 +118329,19 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:73450.3-73594.6" - process $proc$libresoc.v:73450$3578 + attribute \src "libresoc.v:73767.3-73911.6" + process $proc$libresoc.v:73767$3595 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:73451.5-73451.29" + attribute \src "libresoc.v:73768.5-73768.29" switch \initial - attribute \src "libresoc.v:73451.9-73451.17" + attribute \src "libresoc.v:73768.9-73768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -117978,7 +118514,7 @@ module \dec$171 case assign $1\sgn_ext[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -117998,19 +118534,19 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73595.3-73739.6" - process $proc$libresoc.v:73595$3579 + attribute \src "libresoc.v:73912.3-74056.6" + process $proc$libresoc.v:73912$3596 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73596.5-73596.29" + attribute \src "libresoc.v:73913.5-73913.29" switch \initial - attribute \src "libresoc.v:73596.9-73596.17" + attribute \src "libresoc.v:73913.9-73913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118183,7 +118719,7 @@ module \dec$171 case assign $1\rsrv[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118203,19 +118739,19 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:73740.3-73884.6" - process $proc$libresoc.v:73740$3580 + attribute \src "libresoc.v:74057.3-74201.6" + process $proc$libresoc.v:74057$3597 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:73741.5-73741.29" + attribute \src "libresoc.v:74058.5-74058.29" switch \initial - attribute \src "libresoc.v:73741.9-73741.17" + attribute \src "libresoc.v:74058.9-74058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118388,7 +118924,7 @@ module \dec$171 case assign $1\is_32b[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118408,19 +118944,19 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:73885.3-74029.6" - process $proc$libresoc.v:73885$3581 + attribute \src "libresoc.v:74202.3-74346.6" + process $proc$libresoc.v:74202$3598 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:73886.5-73886.29" + attribute \src "libresoc.v:74203.5-74203.29" switch \initial - attribute \src "libresoc.v:73886.9-73886.17" + attribute \src "libresoc.v:74203.9-74203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118593,7 +119129,7 @@ module \dec$171 case assign $1\sgn[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118613,19 +119149,19 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:74030.3-74174.6" - process $proc$libresoc.v:74030$3582 + attribute \src "libresoc.v:74347.3-74491.6" + process $proc$libresoc.v:74347$3599 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:74031.5-74031.29" + attribute \src "libresoc.v:74348.5-74348.29" switch \initial - attribute \src "libresoc.v:74031.9-74031.17" + attribute \src "libresoc.v:74348.9-74348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -118798,7 +119334,7 @@ module \dec$171 case assign $1\lk[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -118818,19 +119354,19 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:74175.3-74319.6" - process $proc$libresoc.v:74175$3583 + attribute \src "libresoc.v:74492.3-74636.6" + process $proc$libresoc.v:74492$3600 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74176.5-74176.29" + attribute \src "libresoc.v:74493.5-74493.29" switch \initial - attribute \src "libresoc.v:74176.9-74176.17" + attribute \src "libresoc.v:74493.9-74493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119003,7 +119539,7 @@ module \dec$171 case assign $1\sgl_pipe[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119023,19 +119559,19 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:74320.3-74464.6" - process $proc$libresoc.v:74320$3584 + attribute \src "libresoc.v:74637.3-74781.6" + process $proc$libresoc.v:74637$3601 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] - attribute \src "libresoc.v:74321.5-74321.29" + attribute \src "libresoc.v:74638.5-74638.29" switch \initial - attribute \src "libresoc.v:74321.9-74321.17" + attribute \src "libresoc.v:74638.9-74638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119208,7 +119744,7 @@ module \dec$171 case assign $1\function_unit[13:0] 14'00000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119228,19 +119764,19 @@ module \dec$171 sync always update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:74465.3-74609.6" - process $proc$libresoc.v:74465$3585 + attribute \src "libresoc.v:74782.3-74926.6" + process $proc$libresoc.v:74782$3602 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:74466.5-74466.29" + attribute \src "libresoc.v:74783.5-74783.29" switch \initial - attribute \src "libresoc.v:74466.9-74466.17" + attribute \src "libresoc.v:74783.9-74783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -119413,7 +119949,7 @@ module \dec$171 case assign $1\internal_op[6:0] 7'0000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -119433,7 +119969,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - connect \$2 $ternary$libresoc.v:69762$3553_Y + connect \$2 $ternary$libresoc.v:69928$3569_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -119777,157 +120313,161 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:74956.1-76960.10" +attribute \src "libresoc.v:75273.1-77339.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:76647.3-76698.6" + attribute \src "libresoc.v:77026.3-77077.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76699.3-76750.6" + attribute \src "libresoc.v:77078.3-77129.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76023.3-76074.6" + attribute \src "libresoc.v:76402.3-76453.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:76231.3-76282.6" + attribute \src "libresoc.v:76610.3-76661.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:75347.3-75398.6" + attribute \src "libresoc.v:75674.3-75725.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75399.3-75450.6" + attribute \src "libresoc.v:75726.3-75777.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:75971.3-76022.6" + attribute \src "libresoc.v:76350.3-76401.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:76179.3-76230.6" + attribute \src "libresoc.v:76558.3-76609.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76439.3-76490.6" + attribute \src "libresoc.v:76766.3-76817.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:75295.3-75346.6" + attribute \src "libresoc.v:75622.3-75673.6" wire width 14 $0\dec19_function_unit[13:0] - attribute \src "libresoc.v:76751.3-76802.6" + attribute \src "libresoc.v:77130.3-77181.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76803.3-76854.6" + attribute \src "libresoc.v:77182.3-77233.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76855.3-76906.6" + attribute \src "libresoc.v:77234.3-77285.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75867.3-75918.6" + attribute \src "libresoc.v:76194.3-76245.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:76075.3-76126.6" + attribute \src "libresoc.v:76454.3-76505.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:76127.3-76178.6" + attribute \src "libresoc.v:76506.3-76557.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:76387.3-76438.6" + attribute \src "libresoc.v:76818.3-76869.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:75763.3-75814.6" + attribute \src "libresoc.v:76142.3-76193.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76543.3-76594.6" + attribute \src "libresoc.v:76922.3-76973.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:76907.3-76958.6" + attribute \src "libresoc.v:77286.3-77337.6" wire width 3 $0\dec19_out_sel[2:0] - attribute \src "libresoc.v:75919.3-75970.6" + attribute \src "libresoc.v:76298.3-76349.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76335.3-76386.6" + attribute \src "libresoc.v:76714.3-76765.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76595.3-76646.6" + attribute \src "libresoc.v:76974.3-77025.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76491.3-76542.6" + attribute \src "libresoc.v:76870.3-76921.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:76283.3-76334.6" + attribute \src "libresoc.v:76662.3-76713.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75659.3-75710.6" + attribute \src "libresoc.v:76038.3-76089.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75711.3-75762.6" + attribute \src "libresoc.v:76090.3-76141.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75451.3-75502.6" + attribute \src "libresoc.v:75778.3-75829.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75503.3-75554.6" + attribute \src "libresoc.v:75830.3-75881.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75555.3-75606.6" + attribute \src "libresoc.v:75882.3-75933.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75607.3-75658.6" + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $0\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:75815.3-75866.6" + attribute \src "libresoc.v:76246.3-76297.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:74957.7-74957.20" + attribute \src "libresoc.v:75274.7-75274.20" wire $0\initial[0:0] - attribute \src "libresoc.v:76647.3-76698.6" + attribute \src "libresoc.v:77026.3-77077.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76699.3-76750.6" + attribute \src "libresoc.v:77078.3-77129.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76023.3-76074.6" + attribute \src "libresoc.v:76402.3-76453.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76231.3-76282.6" + attribute \src "libresoc.v:76610.3-76661.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:75347.3-75398.6" + attribute \src "libresoc.v:75674.3-75725.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75399.3-75450.6" + attribute \src "libresoc.v:75726.3-75777.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75971.3-76022.6" + attribute \src "libresoc.v:76350.3-76401.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76179.3-76230.6" + attribute \src "libresoc.v:76558.3-76609.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76439.3-76490.6" + attribute \src "libresoc.v:76766.3-76817.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:75295.3-75346.6" + attribute \src "libresoc.v:75622.3-75673.6" wire width 14 $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:76751.3-76802.6" + attribute \src "libresoc.v:77130.3-77181.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76803.3-76854.6" + attribute \src "libresoc.v:77182.3-77233.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76855.3-76906.6" + attribute \src "libresoc.v:77234.3-77285.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75867.3-75918.6" + attribute \src "libresoc.v:76194.3-76245.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76075.3-76126.6" + attribute \src "libresoc.v:76454.3-76505.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76127.3-76178.6" + attribute \src "libresoc.v:76506.3-76557.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76387.3-76438.6" + attribute \src "libresoc.v:76818.3-76869.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:75763.3-75814.6" + attribute \src "libresoc.v:76142.3-76193.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76543.3-76594.6" + attribute \src "libresoc.v:76922.3-76973.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:76907.3-76958.6" + attribute \src "libresoc.v:77286.3-77337.6" wire width 3 $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:75919.3-75970.6" + attribute \src "libresoc.v:76298.3-76349.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76335.3-76386.6" + attribute \src "libresoc.v:76714.3-76765.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76595.3-76646.6" + attribute \src "libresoc.v:76974.3-77025.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76491.3-76542.6" + attribute \src "libresoc.v:76870.3-76921.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76283.3-76334.6" + attribute \src "libresoc.v:76662.3-76713.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75659.3-75710.6" + attribute \src "libresoc.v:76038.3-76089.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75711.3-75762.6" + attribute \src "libresoc.v:76090.3-76141.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75451.3-75502.6" + attribute \src "libresoc.v:75778.3-75829.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75503.3-75554.6" + attribute \src "libresoc.v:75830.3-75881.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75555.3-75606.6" + attribute \src "libresoc.v:75882.3-75933.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75607.3-75658.6" + attribute \src "libresoc.v:75986.3-76037.6" + wire width 3 $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75934.3-75985.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75815.3-75866.6" + attribute \src "libresoc.v:76246.3-76297.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -119937,7 +120477,7 @@ module \dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -119946,16 +120486,16 @@ module \dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -119987,7 +120527,7 @@ module \dec19 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -120004,7 +120544,7 @@ module \dec19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -120012,7 +120552,7 @@ module \dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -120029,13 +120569,13 @@ module \dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -120112,46 +120652,46 @@ module \dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120159,8 +120699,8 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec19_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120168,8 +120708,8 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec19_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -120177,7 +120717,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120186,7 +120726,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120195,7 +120735,7 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -120204,41 +120744,50 @@ module \dec19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec19_upd - attribute \src "libresoc.v:74957.7-74957.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec19_upd + attribute \src "libresoc.v:75274.7-75274.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch - attribute \src "libresoc.v:74957.7-74957.20" - process $proc$libresoc.v:74957$3619 + attribute \src "libresoc.v:75274.7-75274.20" + process $proc$libresoc.v:75274$3637 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75295.3-75346.6" - process $proc$libresoc.v:75295$3587 + attribute \src "libresoc.v:75622.3-75673.6" + process $proc$libresoc.v:75622$3604 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:75296.5-75296.29" + attribute \src "libresoc.v:75623.5-75623.29" switch \initial - attribute \src "libresoc.v:75296.9-75296.17" + attribute \src "libresoc.v:75623.9-75623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120306,18 +120855,18 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:75347.3-75398.6" - process $proc$libresoc.v:75347$3588 + attribute \src "libresoc.v:75674.3-75725.6" + process $proc$libresoc.v:75674$3605 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75348.5-75348.29" + attribute \src "libresoc.v:75675.5-75675.29" switch \initial - attribute \src "libresoc.v:75348.9-75348.17" + attribute \src "libresoc.v:75675.9-75675.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120385,18 +120934,18 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75399.3-75450.6" - process $proc$libresoc.v:75399$3589 + attribute \src "libresoc.v:75726.3-75777.6" + process $proc$libresoc.v:75726$3606 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75400.5-75400.29" + attribute \src "libresoc.v:75727.5-75727.29" switch \initial - attribute \src "libresoc.v:75400.9-75400.17" + attribute \src "libresoc.v:75727.9-75727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120464,18 +121013,18 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75451.3-75502.6" - process $proc$libresoc.v:75451$3590 + attribute \src "libresoc.v:75778.3-75829.6" + process $proc$libresoc.v:75778$3607 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75452.5-75452.29" + attribute \src "libresoc.v:75779.5-75779.29" switch \initial - attribute \src "libresoc.v:75452.9-75452.17" + attribute \src "libresoc.v:75779.9-75779.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120543,18 +121092,18 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75503.3-75554.6" - process $proc$libresoc.v:75503$3591 + attribute \src "libresoc.v:75830.3-75881.6" + process $proc$libresoc.v:75830$3608 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75504.5-75504.29" + attribute \src "libresoc.v:75831.5-75831.29" switch \initial - attribute \src "libresoc.v:75504.9-75504.17" + attribute \src "libresoc.v:75831.9-75831.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120622,18 +121171,18 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75555.3-75606.6" - process $proc$libresoc.v:75555$3592 + attribute \src "libresoc.v:75882.3-75933.6" + process $proc$libresoc.v:75882$3609 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75556.5-75556.29" + attribute \src "libresoc.v:75883.5-75883.29" switch \initial - attribute \src "libresoc.v:75556.9-75556.17" + attribute \src "libresoc.v:75883.9-75883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120701,18 +121250,18 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75607.3-75658.6" - process $proc$libresoc.v:75607$3593 + attribute \src "libresoc.v:75934.3-75985.6" + process $proc$libresoc.v:75934$3610 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75608.5-75608.29" + attribute \src "libresoc.v:75935.5-75935.29" switch \initial - attribute \src "libresoc.v:75608.9-75608.17" + attribute \src "libresoc.v:75935.9-75935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120780,18 +121329,97 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75659.3-75710.6" - process $proc$libresoc.v:75659$3594 + attribute \src "libresoc.v:75986.3-76037.6" + process $proc$libresoc.v:75986$3611 + assign { } { } + assign { } { } + assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] + attribute \src "libresoc.v:75987.5-75987.29" + switch \initial + attribute \src "libresoc.v:75987.9-75987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_out2[2:0] 3'000 + case + assign $1\dec19_sv_out2[2:0] 3'000 + end + sync always + update \dec19_sv_out2 $0\dec19_sv_out2[2:0] + end + attribute \src "libresoc.v:76038.3-76089.6" + process $proc$libresoc.v:76038$3612 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75660.5-75660.29" + attribute \src "libresoc.v:76039.5-76039.29" switch \initial - attribute \src "libresoc.v:75660.9-75660.17" + attribute \src "libresoc.v:76039.9-76039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120859,18 +121487,18 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:75711.3-75762.6" - process $proc$libresoc.v:75711$3595 + attribute \src "libresoc.v:76090.3-76141.6" + process $proc$libresoc.v:76090$3613 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75712.5-75712.29" + attribute \src "libresoc.v:76091.5-76091.29" switch \initial - attribute \src "libresoc.v:75712.9-75712.17" + attribute \src "libresoc.v:76091.9-76091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -120938,18 +121566,18 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:75763.3-75814.6" - process $proc$libresoc.v:75763$3596 + attribute \src "libresoc.v:76142.3-76193.6" + process $proc$libresoc.v:76142$3614 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:75764.5-75764.29" + attribute \src "libresoc.v:76143.5-76143.29" switch \initial - attribute \src "libresoc.v:75764.9-75764.17" + attribute \src "libresoc.v:76143.9-76143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121017,176 +121645,176 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:75815.3-75866.6" - process $proc$libresoc.v:75815$3597 + attribute \src "libresoc.v:76194.3-76245.6" + process $proc$libresoc.v:76194$3615 assign { } { } assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:75816.5-75816.29" + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:76195.5-76195.29" switch \initial - attribute \src "libresoc.v:75816.9-75816.17" + attribute \src "libresoc.v:76195.9-76195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0100100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000110 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'1000110 case - assign $1\dec19_upd[1:0] 2'00 + assign $1\dec19_internal_op[6:0] 7'0000000 end sync always - update \dec19_upd $0\dec19_upd[1:0] + update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:75867.3-75918.6" - process $proc$libresoc.v:75867$3598 + attribute \src "libresoc.v:76246.3-76297.6" + process $proc$libresoc.v:76246$3616 assign { } { } assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75868.5-75868.29" + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:76247.5-76247.29" switch \initial - attribute \src "libresoc.v:75868.9-75868.17" + attribute \src "libresoc.v:76247.9-76247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 + assign $1\dec19_upd[1:0] 2'00 case - assign $1\dec19_internal_op[6:0] 7'0000000 + assign $1\dec19_upd[1:0] 2'00 end sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] + update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:75919.3-75970.6" - process $proc$libresoc.v:75919$3599 + attribute \src "libresoc.v:76298.3-76349.6" + process $proc$libresoc.v:76298$3617 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75920.5-75920.29" + attribute \src "libresoc.v:76299.5-76299.29" switch \initial - attribute \src "libresoc.v:75920.9-75920.17" + attribute \src "libresoc.v:76299.9-76299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121254,18 +121882,18 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:75971.3-76022.6" - process $proc$libresoc.v:75971$3600 + attribute \src "libresoc.v:76350.3-76401.6" + process $proc$libresoc.v:76350$3618 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75972.5-75972.29" + attribute \src "libresoc.v:76351.5-76351.29" switch \initial - attribute \src "libresoc.v:75972.9-75972.17" + attribute \src "libresoc.v:76351.9-76351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121333,18 +121961,18 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:76023.3-76074.6" - process $proc$libresoc.v:76023$3601 + attribute \src "libresoc.v:76402.3-76453.6" + process $proc$libresoc.v:76402$3619 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76024.5-76024.29" + attribute \src "libresoc.v:76403.5-76403.29" switch \initial - attribute \src "libresoc.v:76024.9-76024.17" + attribute \src "libresoc.v:76403.9-76403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121412,18 +122040,18 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:76075.3-76126.6" - process $proc$libresoc.v:76075$3602 + attribute \src "libresoc.v:76454.3-76505.6" + process $proc$libresoc.v:76454$3620 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76076.5-76076.29" + attribute \src "libresoc.v:76455.5-76455.29" switch \initial - attribute \src "libresoc.v:76076.9-76076.17" + attribute \src "libresoc.v:76455.9-76455.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121491,18 +122119,18 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:76127.3-76178.6" - process $proc$libresoc.v:76127$3603 + attribute \src "libresoc.v:76506.3-76557.6" + process $proc$libresoc.v:76506$3621 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76128.5-76128.29" + attribute \src "libresoc.v:76507.5-76507.29" switch \initial - attribute \src "libresoc.v:76128.9-76128.17" + attribute \src "libresoc.v:76507.9-76507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121570,18 +122198,18 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:76179.3-76230.6" - process $proc$libresoc.v:76179$3604 + attribute \src "libresoc.v:76558.3-76609.6" + process $proc$libresoc.v:76558$3622 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76180.5-76180.29" + attribute \src "libresoc.v:76559.5-76559.29" switch \initial - attribute \src "libresoc.v:76180.9-76180.17" + attribute \src "libresoc.v:76559.9-76559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121649,18 +122277,18 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:76231.3-76282.6" - process $proc$libresoc.v:76231$3605 + attribute \src "libresoc.v:76610.3-76661.6" + process $proc$libresoc.v:76610$3623 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:76232.5-76232.29" + attribute \src "libresoc.v:76611.5-76611.29" switch \initial - attribute \src "libresoc.v:76232.9-76232.17" + attribute \src "libresoc.v:76611.9-76611.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121728,18 +122356,18 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:76283.3-76334.6" - process $proc$libresoc.v:76283$3606 + attribute \src "libresoc.v:76662.3-76713.6" + process $proc$libresoc.v:76662$3624 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76284.5-76284.29" + attribute \src "libresoc.v:76663.5-76663.29" switch \initial - attribute \src "libresoc.v:76284.9-76284.17" + attribute \src "libresoc.v:76663.9-76663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121807,18 +122435,18 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:76335.3-76386.6" - process $proc$libresoc.v:76335$3607 + attribute \src "libresoc.v:76714.3-76765.6" + process $proc$libresoc.v:76714$3625 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76336.5-76336.29" + attribute \src "libresoc.v:76715.5-76715.29" switch \initial - attribute \src "libresoc.v:76336.9-76336.17" + attribute \src "libresoc.v:76715.9-76715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -121886,176 +122514,176 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:76387.3-76438.6" - process $proc$libresoc.v:76387$3608 + attribute \src "libresoc.v:76766.3-76817.6" + process $proc$libresoc.v:76766$3626 assign { } { } assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76388.5-76388.29" + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:76767.5-76767.29" switch \initial - attribute \src "libresoc.v:76388.9-76388.17" + attribute \src "libresoc.v:76767.9-76767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'01001 case - assign $1\dec19_is_32b[0:0] 1'0 + assign $1\dec19_form[4:0] 5'00000 end sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] + update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76439.3-76490.6" - process $proc$libresoc.v:76439$3609 + attribute \src "libresoc.v:76818.3-76869.6" + process $proc$libresoc.v:76818$3627 assign { } { } assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76440.5-76440.29" + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:76819.5-76819.29" switch \initial - attribute \src "libresoc.v:76440.9-76440.17" + attribute \src "libresoc.v:76819.9-76819.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } - assign $1\dec19_form[4:0] 5'01001 + assign $1\dec19_is_32b[0:0] 1'0 case - assign $1\dec19_form[4:0] 5'00000 + assign $1\dec19_is_32b[0:0] 1'0 end sync always - update \dec19_form $0\dec19_form[4:0] + update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76491.3-76542.6" - process $proc$libresoc.v:76491$3610 + attribute \src "libresoc.v:76870.3-76921.6" + process $proc$libresoc.v:76870$3628 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76492.5-76492.29" + attribute \src "libresoc.v:76871.5-76871.29" switch \initial - attribute \src "libresoc.v:76492.9-76492.17" + attribute \src "libresoc.v:76871.9-76871.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122123,18 +122751,18 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76543.3-76594.6" - process $proc$libresoc.v:76543$3611 + attribute \src "libresoc.v:76922.3-76973.6" + process $proc$libresoc.v:76922$3629 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76544.5-76544.29" + attribute \src "libresoc.v:76923.5-76923.29" switch \initial - attribute \src "libresoc.v:76544.9-76544.17" + attribute \src "libresoc.v:76923.9-76923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122202,18 +122830,18 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76595.3-76646.6" - process $proc$libresoc.v:76595$3612 + attribute \src "libresoc.v:76974.3-77025.6" + process $proc$libresoc.v:76974$3630 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76596.5-76596.29" + attribute \src "libresoc.v:76975.5-76975.29" switch \initial - attribute \src "libresoc.v:76596.9-76596.17" + attribute \src "libresoc.v:76975.9-76975.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122281,18 +122909,18 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:76647.3-76698.6" - process $proc$libresoc.v:76647$3613 + attribute \src "libresoc.v:77026.3-77077.6" + process $proc$libresoc.v:77026$3631 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76648.5-76648.29" + attribute \src "libresoc.v:77027.5-77027.29" switch \initial - attribute \src "libresoc.v:76648.9-76648.17" + attribute \src "libresoc.v:77027.9-77027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122360,18 +122988,18 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:76699.3-76750.6" - process $proc$libresoc.v:76699$3614 + attribute \src "libresoc.v:77078.3-77129.6" + process $proc$libresoc.v:77078$3632 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76700.5-76700.29" + attribute \src "libresoc.v:77079.5-77079.29" switch \initial - attribute \src "libresoc.v:76700.9-76700.17" + attribute \src "libresoc.v:77079.9-77079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122439,18 +123067,18 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:76751.3-76802.6" - process $proc$libresoc.v:76751$3615 + attribute \src "libresoc.v:77130.3-77181.6" + process $proc$libresoc.v:77130$3633 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76752.5-76752.29" + attribute \src "libresoc.v:77131.5-77131.29" switch \initial - attribute \src "libresoc.v:76752.9-76752.17" + attribute \src "libresoc.v:77131.9-77131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122518,18 +123146,18 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:76803.3-76854.6" - process $proc$libresoc.v:76803$3616 + attribute \src "libresoc.v:77182.3-77233.6" + process $proc$libresoc.v:77182$3634 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76804.5-76804.29" + attribute \src "libresoc.v:77183.5-77183.29" switch \initial - attribute \src "libresoc.v:76804.9-76804.17" + attribute \src "libresoc.v:77183.9-77183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122597,18 +123225,18 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:76855.3-76906.6" - process $proc$libresoc.v:76855$3617 + attribute \src "libresoc.v:77234.3-77285.6" + process $proc$libresoc.v:77234$3635 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76856.5-76856.29" + attribute \src "libresoc.v:77235.5-77235.29" switch \initial - attribute \src "libresoc.v:76856.9-76856.17" + attribute \src "libresoc.v:77235.9-77235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122676,18 +123304,18 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:76907.3-76958.6" - process $proc$libresoc.v:76907$3618 + attribute \src "libresoc.v:77286.3-77337.6" + process $proc$libresoc.v:77286$3636 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:76908.5-76908.29" + attribute \src "libresoc.v:77287.5-77287.29" switch \initial - attribute \src "libresoc.v:76908.9-76908.17" + attribute \src "libresoc.v:77287.9-77287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -122757,832 +123385,832 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:76964.1-79185.10" +attribute \src "libresoc.v:77343.1-79564.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $0\cr_in2$1[6:0]$3680 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $0\cr_in2$1[6:0]$3698 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\cr_in2_ok$2[0:0]$3681 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\cr_in2_ok$2[0:0]$3699 + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$3[0:0]$3683 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$4[0:0]$3684 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$5[0:0]$3685 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$6[0:0]$3686 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$7[0:0]$3687 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$8[0:0]$3688 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal$9[0:0]$3689 - attribute \src "libresoc.v:78948.3-79105.6" - wire $0\exc_$signal[0:0]$3682 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$3[0:0]$3701 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$4[0:0]$3702 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$5[0:0]$3703 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$6[0:0]$3704 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$7[0:0]$3705 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$8[0:0]$3706 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal$9[0:0]$3707 + attribute \src "libresoc.v:79327.3-79484.6" + wire $0\exc_$signal[0:0]$3700 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $0\fn_unit[13:0] - attribute \src "libresoc.v:76965.7-76965.20" + attribute \src "libresoc.v:77344.7-77344.20" wire $0\initial[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:78850.3-78864.6" + attribute \src "libresoc.v:79229.3-79243.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78875.3-78887.6" + attribute \src "libresoc.v:79254.3-79266.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78865.3-78874.6" + attribute \src "libresoc.v:79244.3-79253.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78914.3-78923.6" + attribute \src "libresoc.v:79293.3-79302.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:78904.3-78913.6" + attribute \src "libresoc.v:79283.3-79292.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $1\cr_in2$1[6:0]$3690 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $1\cr_in2$1[6:0]$3708 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\cr_in2_ok$2[0:0]$3691 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\cr_in2_ok$2[0:0]$3709 + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$3[0:0]$3693 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$4[0:0]$3694 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$5[0:0]$3695 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$6[0:0]$3696 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$7[0:0]$3697 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$8[0:0]$3698 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal$9[0:0]$3699 - attribute \src "libresoc.v:78948.3-79105.6" - wire $1\exc_$signal[0:0]$3692 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$3[0:0]$3711 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$4[0:0]$3712 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$5[0:0]$3713 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$6[0:0]$3714 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$7[0:0]$3715 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$8[0:0]$3716 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal$9[0:0]$3717 + attribute \src "libresoc.v:79327.3-79484.6" + wire $1\exc_$signal[0:0]$3710 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $1\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:78850.3-78864.6" + attribute \src "libresoc.v:79229.3-79243.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78875.3-78887.6" + attribute \src "libresoc.v:79254.3-79266.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78865.3-78874.6" + attribute \src "libresoc.v:79244.3-79253.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78914.3-78923.6" + attribute \src "libresoc.v:79293.3-79302.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:78904.3-78913.6" + attribute \src "libresoc.v:79283.3-79292.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $2\cr_in2$1[6:0]$3700 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $2\cr_in2$1[6:0]$3718 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\cr_in2_ok$2[0:0]$3701 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\cr_in2_ok$2[0:0]$3719 + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$3[0:0]$3703 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$4[0:0]$3704 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$5[0:0]$3705 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$6[0:0]$3706 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$7[0:0]$3707 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$8[0:0]$3708 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal$9[0:0]$3709 - attribute \src "libresoc.v:78948.3-79105.6" - wire $2\exc_$signal[0:0]$3702 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$3[0:0]$3721 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$4[0:0]$3722 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$5[0:0]$3723 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$6[0:0]$3724 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$7[0:0]$3725 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$8[0:0]$3726 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal$9[0:0]$3727 + attribute \src "libresoc.v:79327.3-79484.6" + wire $2\exc_$signal[0:0]$3720 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $2\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:78924.3-78947.6" + attribute \src "libresoc.v:79303.3-79326.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:78888.3-78903.6" + attribute \src "libresoc.v:79267.3-79282.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $3\cr_in2$1[6:0]$3710 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $3\cr_in2$1[6:0]$3728 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\cr_in2_ok$2[0:0]$3711 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\cr_in2_ok$2[0:0]$3729 + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$3[0:0]$3713 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$4[0:0]$3714 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$5[0:0]$3715 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$6[0:0]$3716 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$7[0:0]$3717 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$8[0:0]$3718 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal$9[0:0]$3719 - attribute \src "libresoc.v:78948.3-79105.6" - wire $3\exc_$signal[0:0]$3712 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$3[0:0]$3731 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$4[0:0]$3732 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$5[0:0]$3733 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$6[0:0]$3734 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$7[0:0]$3735 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$8[0:0]$3736 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal$9[0:0]$3737 + attribute \src "libresoc.v:79327.3-79484.6" + wire $3\exc_$signal[0:0]$3730 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $3\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire width 7 $4\cr_in2$1[6:0]$3720 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire width 7 $4\cr_in2$1[6:0]$3738 + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\cr_in2_ok$2[0:0]$3721 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\cr_in2_ok$2[0:0]$3739 + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$3[0:0]$3723 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$4[0:0]$3724 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$5[0:0]$3725 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$6[0:0]$3726 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$7[0:0]$3727 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$8[0:0]$3728 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal$9[0:0]$3729 - attribute \src "libresoc.v:78948.3-79105.6" - wire $4\exc_$signal[0:0]$3722 - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$3[0:0]$3741 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$4[0:0]$3742 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$5[0:0]$3743 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$6[0:0]$3744 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$7[0:0]$3745 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$8[0:0]$3746 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal$9[0:0]$3747 + attribute \src "libresoc.v:79327.3-79484.6" + wire $4\exc_$signal[0:0]$3740 + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 14 $4\fn_unit[13:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\lk[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\oe[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rc[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:78948.3-79105.6" + attribute \src "libresoc.v:79327.3-79484.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:78671.19-78671.122" - wire $and$libresoc.v:78671$3630_Y - attribute \src "libresoc.v:78672.19-78672.125" - wire $and$libresoc.v:78672$3631_Y - attribute \src "libresoc.v:78673.19-78673.126" - wire $and$libresoc.v:78673$3632_Y - attribute \src "libresoc.v:78680.18-78680.114" - wire $and$libresoc.v:78680$3639_Y - attribute \src "libresoc.v:78681.18-78681.116" - wire $and$libresoc.v:78681$3640_Y - attribute \src "libresoc.v:78683.18-78683.114" - wire $and$libresoc.v:78683$3642_Y - attribute \src "libresoc.v:78685.18-78685.110" - wire $and$libresoc.v:78685$3644_Y - attribute \src "libresoc.v:78697.18-78697.114" - wire $and$libresoc.v:78697$3656_Y - attribute \src "libresoc.v:78698.18-78698.116" - wire $and$libresoc.v:78698$3657_Y - attribute \src "libresoc.v:78700.18-78700.114" - wire $and$libresoc.v:78700$3659_Y - attribute \src "libresoc.v:78702.18-78702.110" - wire $and$libresoc.v:78702$3661_Y - attribute \src "libresoc.v:78667.19-78667.124" - wire $eq$libresoc.v:78667$3626_Y - attribute \src "libresoc.v:78668.19-78668.124" - wire $eq$libresoc.v:78668$3627_Y - attribute \src "libresoc.v:78669.19-78669.124" - wire $eq$libresoc.v:78669$3628_Y - attribute \src "libresoc.v:78670.19-78670.124" - wire $eq$libresoc.v:78670$3629_Y - attribute \src "libresoc.v:78674.19-78674.124" - wire $eq$libresoc.v:78674$3633_Y - attribute \src "libresoc.v:78675.18-78675.117" - wire $eq$libresoc.v:78675$3634_Y - attribute \src "libresoc.v:78676.18-78676.117" - wire $eq$libresoc.v:78676$3635_Y - attribute \src "libresoc.v:78678.18-78678.117" - wire $eq$libresoc.v:78678$3637_Y - attribute \src "libresoc.v:78679.18-78679.127" - wire $eq$libresoc.v:78679$3638_Y - attribute \src "libresoc.v:78682.18-78682.127" - wire $eq$libresoc.v:78682$3641_Y - attribute \src "libresoc.v:78686.18-78686.122" - wire $eq$libresoc.v:78686$3645_Y - attribute \src "libresoc.v:78687.18-78687.122" - wire $eq$libresoc.v:78687$3646_Y - attribute \src "libresoc.v:78689.18-78689.110" - wire $eq$libresoc.v:78689$3648_Y - attribute \src "libresoc.v:78690.18-78690.110" - wire $eq$libresoc.v:78690$3649_Y - attribute \src "libresoc.v:78692.18-78692.112" - wire $eq$libresoc.v:78692$3651_Y - attribute \src "libresoc.v:78694.18-78694.110" - wire $eq$libresoc.v:78694$3653_Y - attribute \src "libresoc.v:78696.18-78696.127" - wire $eq$libresoc.v:78696$3655_Y - attribute \src "libresoc.v:78699.18-78699.127" - wire $eq$libresoc.v:78699$3658_Y - attribute \src "libresoc.v:78664.19-78664.124" - wire width 7 $extend$libresoc.v:78664$3620_Y - attribute \src "libresoc.v:78665.19-78665.124" - wire width 7 $extend$libresoc.v:78665$3622_Y - attribute \src "libresoc.v:78666.19-78666.123" - wire width 7 $extend$libresoc.v:78666$3624_Y - attribute \src "libresoc.v:78703.18-78703.111" - wire width 7 $extend$libresoc.v:78703$3662_Y - attribute \src "libresoc.v:78704.18-78704.111" - wire width 7 $extend$libresoc.v:78704$3664_Y - attribute \src "libresoc.v:78705.18-78705.111" - wire width 7 $extend$libresoc.v:78705$3666_Y - attribute \src "libresoc.v:78706.18-78706.113" - wire width 7 $extend$libresoc.v:78706$3668_Y - attribute \src "libresoc.v:78707.18-78707.121" - wire width 7 $extend$libresoc.v:78707$3670_Y - attribute \src "libresoc.v:78684.18-78684.110" - wire $not$libresoc.v:78684$3643_Y - attribute \src "libresoc.v:78701.18-78701.110" - wire $not$libresoc.v:78701$3660_Y - attribute \src "libresoc.v:78677.18-78677.111" - wire $or$libresoc.v:78677$3636_Y - attribute \src "libresoc.v:78688.18-78688.110" - wire $or$libresoc.v:78688$3647_Y - attribute \src "libresoc.v:78691.18-78691.110" - wire $or$libresoc.v:78691$3650_Y - attribute \src "libresoc.v:78693.18-78693.110" - wire $or$libresoc.v:78693$3652_Y - attribute \src "libresoc.v:78695.18-78695.110" - wire $or$libresoc.v:78695$3654_Y - attribute \src "libresoc.v:78664.19-78664.124" - wire width 7 $pos$libresoc.v:78664$3621_Y - attribute \src "libresoc.v:78665.19-78665.124" - wire width 7 $pos$libresoc.v:78665$3623_Y - attribute \src "libresoc.v:78666.19-78666.123" - wire width 7 $pos$libresoc.v:78666$3625_Y - attribute \src "libresoc.v:78703.18-78703.111" - wire width 7 $pos$libresoc.v:78703$3663_Y - attribute \src "libresoc.v:78704.18-78704.111" - wire width 7 $pos$libresoc.v:78704$3665_Y - attribute \src "libresoc.v:78705.18-78705.111" - wire width 7 $pos$libresoc.v:78705$3667_Y - attribute \src "libresoc.v:78706.18-78706.113" - wire width 7 $pos$libresoc.v:78706$3669_Y - attribute \src "libresoc.v:78707.18-78707.121" - wire width 7 $pos$libresoc.v:78707$3671_Y + attribute \src "libresoc.v:79050.19-79050.122" + wire $and$libresoc.v:79050$3648_Y + attribute \src "libresoc.v:79051.19-79051.125" + wire $and$libresoc.v:79051$3649_Y + attribute \src "libresoc.v:79052.19-79052.126" + wire $and$libresoc.v:79052$3650_Y + attribute \src "libresoc.v:79059.18-79059.114" + wire $and$libresoc.v:79059$3657_Y + attribute \src "libresoc.v:79060.18-79060.116" + wire $and$libresoc.v:79060$3658_Y + attribute \src "libresoc.v:79062.18-79062.114" + wire $and$libresoc.v:79062$3660_Y + attribute \src "libresoc.v:79064.18-79064.110" + wire $and$libresoc.v:79064$3662_Y + attribute \src "libresoc.v:79076.18-79076.114" + wire $and$libresoc.v:79076$3674_Y + attribute \src "libresoc.v:79077.18-79077.116" + wire $and$libresoc.v:79077$3675_Y + attribute \src "libresoc.v:79079.18-79079.114" + wire $and$libresoc.v:79079$3677_Y + attribute \src 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"libresoc.v:79043.19-79043.124" + wire width 7 $pos$libresoc.v:79043$3639_Y + attribute \src "libresoc.v:79044.19-79044.124" + wire width 7 $pos$libresoc.v:79044$3641_Y + attribute \src "libresoc.v:79045.19-79045.123" + wire width 7 $pos$libresoc.v:79045$3643_Y + attribute \src "libresoc.v:79082.18-79082.111" + wire width 7 $pos$libresoc.v:79082$3681_Y + attribute \src "libresoc.v:79083.18-79083.111" + wire width 7 $pos$libresoc.v:79083$3683_Y + attribute \src "libresoc.v:79084.18-79084.111" + wire width 7 $pos$libresoc.v:79084$3685_Y + attribute \src "libresoc.v:79085.18-79085.113" + wire width 7 $pos$libresoc.v:79085$3687_Y + attribute \src "libresoc.v:79086.18-79086.121" + wire width 7 $pos$libresoc.v:79086$3689_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$90 @@ -123596,7 +124224,7 @@ module \dec2 wire width 7 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 39 \cia @@ -123648,43 +124276,43 @@ module \dec2 wire \dec2_exc_$signal$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_a_fast_a @@ -123700,7 +124328,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -123820,9 +124448,9 @@ module \dec2 wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire \dec_a_sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_b_fast_b @@ -123847,7 +124475,7 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c @@ -123857,7 +124485,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123868,7 +124496,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield @@ -123886,7 +124514,7 @@ module \dec2 wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123897,7 +124525,7 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123906,7 +124534,7 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_out_cr_bitfield @@ -123916,9 +124544,9 @@ module \dec2 wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123927,13 +124555,13 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_cry_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -123950,7 +124578,7 @@ module \dec2 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123958,7 +124586,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123975,13 +124603,13 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124058,19 +124686,19 @@ module \dec2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" wire \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_fast_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o2_reg_o2 @@ -124090,7 +124718,7 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124218,9 +124846,9 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -124228,7 +124856,7 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -124238,20 +124866,20 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 8 \ea @@ -124273,7 +124901,7 @@ module \dec2 wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1214" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 22 \fast1 @@ -124308,9 +124936,9 @@ module \dec2 attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 14 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1199" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217" wire \illeg_ok - attribute \src "libresoc.v:76965.7-76965.15" + attribute \src "libresoc.v:77344.7-77344.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -124320,19 +124948,19 @@ module \dec2 wire width 2 output 48 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" wire width 32 \insn_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194" wire width 32 \insn_in$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" wire width 32 \insn_in$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" wire width 32 \insn_in$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396" wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124413,11 +125041,11 @@ module \dec2 wire width 7 output 41 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire output 63 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 43 \lk @@ -124427,9 +125055,9 @@ module \dec2 wire output 46 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 4 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \rc @@ -124457,9 +125085,9 @@ module \dec2 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" wire width 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124697,7 +125325,7 @@ module \dec2 wire width 10 output 16 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 65 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode @@ -125147,8 +125775,8 @@ module \dec2 wire width 3 output 20 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" - cell $and $and$libresoc.v:78671$3630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" + cell $and $and$libresoc.v:79050$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125156,10 +125784,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78671$3630_Y + connect \Y $and$libresoc.v:79050$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" - cell $and $and$libresoc.v:78672$3631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" + cell $and $and$libresoc.v:79051$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125167,10 +125795,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78672$3631_Y + connect \Y $and$libresoc.v:79051$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" - cell $and $and$libresoc.v:78673$3632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" + cell $and $and$libresoc.v:79052$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125178,10 +125806,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:78673$3632_Y + connect \Y $and$libresoc.v:79052$3650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78680$3639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79059$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125189,10 +125817,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:78680$3639_Y + connect \Y $and$libresoc.v:79059$3657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78681$3640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79060$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125200,10 +125828,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78681$3640_Y + connect \Y $and$libresoc.v:79060$3658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78683$3642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79062$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125211,10 +125839,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:78683$3642_Y + connect \Y $and$libresoc.v:79062$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78685$3644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79064$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125222,10 +125850,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:78685$3644_Y + connect \Y $and$libresoc.v:79064$3662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78697$3656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79076$3674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125233,10 +125861,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:78697$3656_Y + connect \Y $and$libresoc.v:79076$3674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:78698$3657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:79077$3675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125244,10 +125872,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:78698$3657_Y + connect \Y $and$libresoc.v:79077$3675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78700$3659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79079$3677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125255,10 +125883,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:78700$3659_Y + connect \Y $and$libresoc.v:79079$3677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:78702$3661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:79081$3679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125266,10 +125894,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:78702$3661_Y + connect \Y $and$libresoc.v:79081$3679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" - cell $eq $eq$libresoc.v:78667$3626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" + cell $eq $eq$libresoc.v:79046$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125277,10 +125905,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78667$3626_Y + connect \Y $eq$libresoc.v:79046$3644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" - cell $eq $eq$libresoc.v:78668$3627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" + cell $eq $eq$libresoc.v:79047$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125288,10 +125916,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:78668$3627_Y + connect \Y $eq$libresoc.v:79047$3645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" - cell $eq $eq$libresoc.v:78669$3628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" + cell $eq $eq$libresoc.v:79048$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125299,10 +125927,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78669$3628_Y + connect \Y $eq$libresoc.v:79048$3646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" - cell $eq $eq$libresoc.v:78670$3629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" + cell $eq $eq$libresoc.v:79049$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125310,10 +125938,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:78670$3629_Y + connect \Y $eq$libresoc.v:79049$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" - cell $eq $eq$libresoc.v:78674$3633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" + cell $eq $eq$libresoc.v:79053$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125321,10 +125949,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:78674$3633_Y + connect \Y $eq$libresoc.v:79053$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1253" - cell $eq $eq$libresoc.v:78675$3634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" + cell $eq $eq$libresoc.v:79054$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125332,10 +125960,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:78675$3634_Y + connect \Y $eq$libresoc.v:79054$3652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" - cell $eq $eq$libresoc.v:78676$3635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $eq $eq$libresoc.v:79055$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125343,10 +125971,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:78676$3635_Y + connect \Y $eq$libresoc.v:79055$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" - cell $eq $eq$libresoc.v:78678$3637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" + cell $eq $eq$libresoc.v:79057$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125354,10 +125982,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:78678$3637_Y + connect \Y $eq$libresoc.v:79057$3655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:78679$3638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79058$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125365,10 +125993,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78679$3638_Y + connect \Y $eq$libresoc.v:79058$3656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:78682$3641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79061$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125376,10 +126004,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78682$3641_Y + connect \Y $eq$libresoc.v:79061$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:78686$3645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:79065$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125387,10 +126015,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78686$3645_Y + connect \Y $eq$libresoc.v:79065$3663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:78687$3646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:79066$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125398,10 +126026,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78687$3646_Y + connect \Y $eq$libresoc.v:79066$3664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78689$3648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79068$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125409,10 +126037,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:78689$3648_Y + connect \Y $eq$libresoc.v:79068$3666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78690$3649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79069$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125420,10 +126048,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:78690$3649_Y + connect \Y $eq$libresoc.v:79069$3667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:78692$3651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:79071$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125431,10 +126059,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:78692$3651_Y + connect \Y $eq$libresoc.v:79071$3669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:78694$3653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:79073$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -125442,10 +126070,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:78694$3653_Y + connect \Y $eq$libresoc.v:79073$3671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:78696$3655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:79075$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125453,10 +126081,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:78696$3655_Y + connect \Y $eq$libresoc.v:79075$3673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:78699$3658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:79078$3676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125464,90 +126092,90 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:78699$3658_Y + connect \Y $eq$libresoc.v:79078$3676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78664$3620 + cell $pos $extend$libresoc.v:79043$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:78664$3620_Y + connect \Y $extend$libresoc.v:79043$3638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78665$3622 + cell $pos $extend$libresoc.v:79044$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:78665$3622_Y + connect \Y $extend$libresoc.v:79044$3640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78666$3624 + cell $pos $extend$libresoc.v:79045$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:78666$3624_Y + connect \Y $extend$libresoc.v:79045$3642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78703$3662 + cell $pos $extend$libresoc.v:79082$3680 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:78703$3662_Y + connect \Y $extend$libresoc.v:79082$3680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78704$3664 + cell $pos $extend$libresoc.v:79083$3682 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:78704$3664_Y + connect \Y $extend$libresoc.v:79083$3682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78705$3666 + cell $pos $extend$libresoc.v:79084$3684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:78705$3666_Y + connect \Y $extend$libresoc.v:79084$3684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78706$3668 + cell $pos $extend$libresoc.v:79085$3686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:78706$3668_Y + connect \Y $extend$libresoc.v:79085$3686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:78707$3670 + cell $pos $extend$libresoc.v:79086$3688 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:78707$3670_Y + connect \Y $extend$libresoc.v:79086$3688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:78684$3643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79063$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78684$3643_Y + connect \Y $not$libresoc.v:79063$3661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:78701$3660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:79080$3678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:78701$3660_Y + connect \Y $not$libresoc.v:79080$3678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" - cell $or $or$libresoc.v:78677$3636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" + cell $or $or$libresoc.v:79056$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125555,10 +126183,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:78677$3636_Y + connect \Y $or$libresoc.v:79056$3654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:78688$3647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:79067$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125566,10 +126194,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:78688$3647_Y + connect \Y $or$libresoc.v:79067$3665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:78691$3650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79070$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125577,10 +126205,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:78691$3650_Y + connect \Y $or$libresoc.v:79070$3668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:78693$3652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:79072$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125588,10 +126216,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:78693$3652_Y + connect \Y $or$libresoc.v:79072$3670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:78695$3654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:79074$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125599,74 +126227,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:78695$3654_Y + connect \Y $or$libresoc.v:79074$3672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78664$3621 + cell $pos $pos$libresoc.v:79043$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78664$3620_Y - connect \Y $pos$libresoc.v:78664$3621_Y + connect \A $extend$libresoc.v:79043$3638_Y + connect \Y $pos$libresoc.v:79043$3639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78665$3623 + cell $pos $pos$libresoc.v:79044$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78665$3622_Y - connect \Y $pos$libresoc.v:78665$3623_Y + connect \A $extend$libresoc.v:79044$3640_Y + connect \Y $pos$libresoc.v:79044$3641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78666$3625 + cell $pos $pos$libresoc.v:79045$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78666$3624_Y - connect \Y $pos$libresoc.v:78666$3625_Y + connect \A $extend$libresoc.v:79045$3642_Y + connect \Y $pos$libresoc.v:79045$3643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78703$3663 + cell $pos $pos$libresoc.v:79082$3681 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78703$3662_Y - connect \Y $pos$libresoc.v:78703$3663_Y + connect \A $extend$libresoc.v:79082$3680_Y + connect \Y $pos$libresoc.v:79082$3681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78704$3665 + cell $pos $pos$libresoc.v:79083$3683 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78704$3664_Y - connect \Y $pos$libresoc.v:78704$3665_Y + connect \A $extend$libresoc.v:79083$3682_Y + connect \Y $pos$libresoc.v:79083$3683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78705$3667 + cell $pos $pos$libresoc.v:79084$3685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78705$3666_Y - connect \Y $pos$libresoc.v:78705$3667_Y + connect \A $extend$libresoc.v:79084$3684_Y + connect \Y $pos$libresoc.v:79084$3685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78706$3669 + cell $pos $pos$libresoc.v:79085$3687 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78706$3668_Y - connect \Y $pos$libresoc.v:78706$3669_Y + connect \A $extend$libresoc.v:79085$3686_Y + connect \Y $pos$libresoc.v:79085$3687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:78707$3671 + cell $pos $pos$libresoc.v:79086$3689 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:78707$3670_Y - connect \Y $pos$libresoc.v:78707$3671_Y + connect \A $extend$libresoc.v:79086$3688_Y + connect \Y $pos$libresoc.v:79086$3689_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:78708.13-78745.4" + attribute \src "libresoc.v:79087.13-79124.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -125706,7 +126334,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78746.9-78761.4" + attribute \src "libresoc.v:79125.9-79140.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -125724,7 +126352,7 @@ module \dec2 connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:78762.9-78772.4" + attribute \src "libresoc.v:79141.9-79151.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -125737,7 +126365,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78773.9-78779.4" + attribute \src "libresoc.v:79152.9-79158.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -125746,7 +126374,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78780.13-78799.4" + attribute \src "libresoc.v:79159.13-79178.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -125768,7 +126396,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78800.14-78812.4" + attribute \src "libresoc.v:79179.14-79191.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -125783,7 +126411,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78813.9-78826.4" + attribute \src "libresoc.v:79192.9-79205.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -125799,7 +126427,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:78827.10-78836.4" + attribute \src "libresoc.v:79206.10-79215.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -125811,7 +126439,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78837.16-78843.4" + attribute \src "libresoc.v:79216.16-79222.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -125820,32 +126448,32 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78844.16-78849.4" + attribute \src "libresoc.v:79223.16-79228.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:76965.7-76965.20" - process $proc$libresoc.v:76965$3730 + attribute \src "libresoc.v:77344.7-77344.20" + process $proc$libresoc.v:77344$3748 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:78850.3-78864.6" - process $proc$libresoc.v:78850$3672 + attribute \src "libresoc.v:79229.3-79243.6" + process $proc$libresoc.v:79229$3690 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:78851.5-78851.29" + attribute \src "libresoc.v:79230.5-79230.29" switch \initial - attribute \src "libresoc.v:78851.9-78851.17" + attribute \src "libresoc.v:79230.9-79230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$83 \$75 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125863,18 +126491,18 @@ module \dec2 sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:78865.3-78874.6" - process $proc$libresoc.v:78865$3673 + attribute \src "libresoc.v:79244.3-79253.6" + process $proc$libresoc.v:79244$3691 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78866.5-78866.29" + attribute \src "libresoc.v:79245.5-79245.29" switch \initial - attribute \src "libresoc.v:78866.9-78866.17" + attribute \src "libresoc.v:79245.9-79245.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125886,18 +126514,18 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:78875.3-78887.6" - process $proc$libresoc.v:78875$3674 + attribute \src "libresoc.v:79254.3-79266.6" + process $proc$libresoc.v:79254$3692 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:78876.5-78876.29" + attribute \src "libresoc.v:79255.5-79255.29" switch \initial - attribute \src "libresoc.v:78876.9-78876.17" + attribute \src "libresoc.v:79255.9-79255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$49 \$41 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -125913,19 +126541,19 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:78888.3-78903.6" - process $proc$libresoc.v:78888$3675 + attribute \src "libresoc.v:79267.3-79282.6" + process $proc$libresoc.v:79267$3693 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78889.5-78889.29" + attribute \src "libresoc.v:79268.5-79268.29" switch \initial - attribute \src "libresoc.v:78889.9-78889.17" + attribute \src "libresoc.v:79268.9-79268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125934,7 +126562,7 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125946,18 +126574,18 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:78904.3-78913.6" - process $proc$libresoc.v:78904$3676 + attribute \src "libresoc.v:79283.3-79292.6" + process $proc$libresoc.v:79283$3694 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78905.5-78905.29" + attribute \src "libresoc.v:79284.5-79284.29" switch \initial - attribute \src "libresoc.v:78905.9-78905.17" + attribute \src "libresoc.v:79284.9-79284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125969,18 +126597,18 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:78914.3-78923.6" - process $proc$libresoc.v:78914$3677 + attribute \src "libresoc.v:79293.3-79302.6" + process $proc$libresoc.v:79293$3695 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78915.5-78915.29" + attribute \src "libresoc.v:79294.5-79294.29" switch \initial - attribute \src "libresoc.v:78915.9-78915.17" + attribute \src "libresoc.v:79294.9-79294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125992,18 +126620,18 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:78924.3-78947.6" - process $proc$libresoc.v:78924$3678 + attribute \src "libresoc.v:79303.3-79326.6" + process $proc$libresoc.v:79303$3696 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78925.5-78925.29" + attribute \src "libresoc.v:79304.5-79304.29" switch \initial - attribute \src "libresoc.v:78925.9-78925.17" + attribute \src "libresoc.v:79304.9-79304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 @@ -126017,7 +126645,7 @@ module \dec2 case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126032,8 +126660,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:78948.3-79105.6" - process $proc$libresoc.v:78948$3679 + attribute \src "libresoc.v:79327.3-79484.6" + process $proc$libresoc.v:79327$3697 assign { } { } assign { } { } assign { } { } @@ -126110,22 +126738,22 @@ module \dec2 assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[6:0] $1\cr_in2[6:0] - assign $0\cr_in2$1[6:0]$3680 $1\cr_in2$1[6:0]$3690 + assign $0\cr_in2$1[6:0]$3698 $1\cr_in2$1[6:0]$3708 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3681 $1\cr_in2_ok$2[0:0]$3691 + assign $0\cr_in2_ok$2[0:0]$3699 $1\cr_in2_ok$2[0:0]$3709 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3682 $1\exc_$signal[0:0]$3692 - assign $0\exc_$signal$3[0:0]$3683 $1\exc_$signal$3[0:0]$3693 - assign $0\exc_$signal$4[0:0]$3684 $1\exc_$signal$4[0:0]$3694 - assign $0\exc_$signal$5[0:0]$3685 $1\exc_$signal$5[0:0]$3695 - assign $0\exc_$signal$6[0:0]$3686 $1\exc_$signal$6[0:0]$3696 - assign $0\exc_$signal$7[0:0]$3687 $1\exc_$signal$7[0:0]$3697 - assign $0\exc_$signal$8[0:0]$3688 $1\exc_$signal$8[0:0]$3698 - assign $0\exc_$signal$9[0:0]$3689 $1\exc_$signal$9[0:0]$3699 + assign $0\exc_$signal[0:0]$3700 $1\exc_$signal[0:0]$3710 + assign $0\exc_$signal$3[0:0]$3701 $1\exc_$signal$3[0:0]$3711 + assign $0\exc_$signal$4[0:0]$3702 $1\exc_$signal$4[0:0]$3712 + assign $0\exc_$signal$5[0:0]$3703 $1\exc_$signal$5[0:0]$3713 + assign $0\exc_$signal$6[0:0]$3704 $1\exc_$signal$6[0:0]$3714 + assign $0\exc_$signal$7[0:0]$3705 $1\exc_$signal$7[0:0]$3715 + assign $0\exc_$signal$8[0:0]$3706 $1\exc_$signal$8[0:0]$3716 + assign $0\exc_$signal$9[0:0]$3707 $1\exc_$signal$9[0:0]$3717 assign { } { } assign { } { } assign { } { } @@ -126161,13 +126789,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:78949.5-78949.29" + attribute \src "libresoc.v:79328.5-79328.29" switch \initial - attribute \src "libresoc.v:78949.9-78949.17" + attribute \src "libresoc.v:79328.9-79328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1227" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -126247,22 +126875,22 @@ module \dec2 assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] assign $1\cr_in2[6:0] $2\cr_in2[6:0] - assign $1\cr_in2$1[6:0]$3690 $2\cr_in2$1[6:0]$3700 + assign $1\cr_in2$1[6:0]$3708 $2\cr_in2$1[6:0]$3718 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3691 $2\cr_in2_ok$2[0:0]$3701 + assign $1\cr_in2_ok$2[0:0]$3709 $2\cr_in2_ok$2[0:0]$3719 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3692 $2\exc_$signal[0:0]$3702 - assign $1\exc_$signal$3[0:0]$3693 $2\exc_$signal$3[0:0]$3703 - assign $1\exc_$signal$4[0:0]$3694 $2\exc_$signal$4[0:0]$3704 - assign $1\exc_$signal$5[0:0]$3695 $2\exc_$signal$5[0:0]$3705 - assign $1\exc_$signal$6[0:0]$3696 $2\exc_$signal$6[0:0]$3706 - assign $1\exc_$signal$7[0:0]$3697 $2\exc_$signal$7[0:0]$3707 - assign $1\exc_$signal$8[0:0]$3698 $2\exc_$signal$8[0:0]$3708 - assign $1\exc_$signal$9[0:0]$3699 $2\exc_$signal$9[0:0]$3709 + assign $1\exc_$signal[0:0]$3710 $2\exc_$signal[0:0]$3720 + assign $1\exc_$signal$3[0:0]$3711 $2\exc_$signal$3[0:0]$3721 + assign $1\exc_$signal$4[0:0]$3712 $2\exc_$signal$4[0:0]$3722 + assign $1\exc_$signal$5[0:0]$3713 $2\exc_$signal$5[0:0]$3723 + assign $1\exc_$signal$6[0:0]$3714 $2\exc_$signal$6[0:0]$3724 + assign $1\exc_$signal$7[0:0]$3715 $2\exc_$signal$7[0:0]$3725 + assign $1\exc_$signal$8[0:0]$3716 $2\exc_$signal$8[0:0]$3726 + assign $1\exc_$signal$9[0:0]$3717 $2\exc_$signal$9[0:0]$3727 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] @@ -126289,7 +126917,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126352,7 +126980,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3709 $2\exc_$signal$8[0:0]$3708 $2\exc_$signal$7[0:0]$3707 $2\exc_$signal$6[0:0]$3706 $2\exc_$signal$5[0:0]$3705 $2\exc_$signal$4[0:0]$3704 $2\exc_$signal$3[0:0]$3703 $2\exc_$signal[0:0]$3702 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3701 $2\cr_in2$1[6:0]$3700 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3727 $2\exc_$signal$8[0:0]$3726 $2\exc_$signal$7[0:0]$3725 $2\exc_$signal$6[0:0]$3724 $2\exc_$signal$5[0:0]$3723 $2\exc_$signal$4[0:0]$3722 $2\exc_$signal$3[0:0]$3721 $2\exc_$signal[0:0]$3720 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3719 $2\cr_in2$1[6:0]$3718 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 assign $2\fn_unit[13:0] 14'00000010000000 @@ -126438,22 +127066,22 @@ module \dec2 assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $3\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3700 $3\cr_in2$1[6:0]$3710 + assign $2\cr_in2$1[6:0]$3718 $3\cr_in2$1[6:0]$3728 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3701 $3\cr_in2_ok$2[0:0]$3711 + assign $2\cr_in2_ok$2[0:0]$3719 $3\cr_in2_ok$2[0:0]$3729 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3702 $3\exc_$signal[0:0]$3712 - assign $2\exc_$signal$3[0:0]$3703 $3\exc_$signal$3[0:0]$3713 - assign $2\exc_$signal$4[0:0]$3704 $3\exc_$signal$4[0:0]$3714 - assign $2\exc_$signal$5[0:0]$3705 $3\exc_$signal$5[0:0]$3715 - assign $2\exc_$signal$6[0:0]$3706 $3\exc_$signal$6[0:0]$3716 - assign $2\exc_$signal$7[0:0]$3707 $3\exc_$signal$7[0:0]$3717 - assign $2\exc_$signal$8[0:0]$3708 $3\exc_$signal$8[0:0]$3718 - assign $2\exc_$signal$9[0:0]$3709 $3\exc_$signal$9[0:0]$3719 + assign $2\exc_$signal[0:0]$3720 $3\exc_$signal[0:0]$3730 + assign $2\exc_$signal$3[0:0]$3721 $3\exc_$signal$3[0:0]$3731 + assign $2\exc_$signal$4[0:0]$3722 $3\exc_$signal$4[0:0]$3732 + assign $2\exc_$signal$5[0:0]$3723 $3\exc_$signal$5[0:0]$3733 + assign $2\exc_$signal$6[0:0]$3724 $3\exc_$signal$6[0:0]$3734 + assign $2\exc_$signal$7[0:0]$3725 $3\exc_$signal$7[0:0]$3735 + assign $2\exc_$signal$8[0:0]$3726 $3\exc_$signal$8[0:0]$3736 + assign $2\exc_$signal$9[0:0]$3727 $3\exc_$signal$9[0:0]$3737 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] @@ -126480,7 +127108,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1231" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126543,7 +127171,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 @@ -126612,13 +127240,13 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3711 $3\cr_in2$1[6:0]$3710 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3729 $3\cr_in2$1[6:0]$3728 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3719 $3\exc_$signal$8[0:0]$3718 $3\exc_$signal$7[0:0]$3717 $3\exc_$signal$6[0:0]$3716 $3\exc_$signal$5[0:0]$3715 $3\exc_$signal$4[0:0]$3714 $3\exc_$signal$3[0:0]$3713 $3\exc_$signal[0:0]$3712 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign { $3\exc_$signal$9[0:0]$3737 $3\exc_$signal$8[0:0]$3736 $3\exc_$signal$7[0:0]$3735 $3\exc_$signal$6[0:0]$3734 $3\exc_$signal$5[0:0]$3733 $3\exc_$signal$4[0:0]$3732 $3\exc_$signal$3[0:0]$3731 $3\exc_$signal[0:0]$3730 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end @@ -126700,22 +127328,22 @@ module \dec2 assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $4\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3700 $4\cr_in2$1[6:0]$3720 + assign $2\cr_in2$1[6:0]$3718 $4\cr_in2$1[6:0]$3738 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3701 $4\cr_in2_ok$2[0:0]$3721 + assign $2\cr_in2_ok$2[0:0]$3719 $4\cr_in2_ok$2[0:0]$3739 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3702 $4\exc_$signal[0:0]$3722 - assign $2\exc_$signal$3[0:0]$3703 $4\exc_$signal$3[0:0]$3723 - assign $2\exc_$signal$4[0:0]$3704 $4\exc_$signal$4[0:0]$3724 - assign $2\exc_$signal$5[0:0]$3705 $4\exc_$signal$5[0:0]$3725 - assign $2\exc_$signal$6[0:0]$3706 $4\exc_$signal$6[0:0]$3726 - assign $2\exc_$signal$7[0:0]$3707 $4\exc_$signal$7[0:0]$3727 - assign $2\exc_$signal$8[0:0]$3708 $4\exc_$signal$8[0:0]$3728 - assign $2\exc_$signal$9[0:0]$3709 $4\exc_$signal$9[0:0]$3729 + assign $2\exc_$signal[0:0]$3720 $4\exc_$signal[0:0]$3740 + assign $2\exc_$signal$3[0:0]$3721 $4\exc_$signal$3[0:0]$3741 + assign $2\exc_$signal$4[0:0]$3722 $4\exc_$signal$4[0:0]$3742 + assign $2\exc_$signal$5[0:0]$3723 $4\exc_$signal$5[0:0]$3743 + assign $2\exc_$signal$6[0:0]$3724 $4\exc_$signal$6[0:0]$3744 + assign $2\exc_$signal$7[0:0]$3725 $4\exc_$signal$7[0:0]$3745 + assign $2\exc_$signal$8[0:0]$3726 $4\exc_$signal$8[0:0]$3746 + assign $2\exc_$signal$9[0:0]$3727 $4\exc_$signal$9[0:0]$3747 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] @@ -126742,7 +127370,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1237" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126805,7 +127433,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -126874,7 +127502,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3729 $4\exc_$signal$8[0:0]$3728 $4\exc_$signal$7[0:0]$3727 $4\exc_$signal$6[0:0]$3726 $4\exc_$signal$5[0:0]$3725 $4\exc_$signal$4[0:0]$3724 $4\exc_$signal$3[0:0]$3723 $4\exc_$signal[0:0]$3722 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3721 $4\cr_in2$1[6:0]$3720 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3747 $4\exc_$signal$8[0:0]$3746 $4\exc_$signal$7[0:0]$3745 $4\exc_$signal$6[0:0]$3744 $4\exc_$signal$5[0:0]$3743 $4\exc_$signal$4[0:0]$3742 $4\exc_$signal$3[0:0]$3741 $4\exc_$signal[0:0]$3740 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3739 $4\cr_in2$1[6:0]$3738 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 @@ -126945,7 +127573,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127014,7 +127642,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127083,7 +127711,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127152,7 +127780,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 @@ -127221,9 +127849,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3699 $1\exc_$signal$8[0:0]$3698 $1\exc_$signal$7[0:0]$3697 $1\exc_$signal$6[0:0]$3696 $1\exc_$signal$5[0:0]$3695 $1\exc_$signal$4[0:0]$3694 $1\exc_$signal$3[0:0]$3693 $1\exc_$signal[0:0]$3692 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3691 $1\cr_in2$1[6:0]$3690 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3717 $1\exc_$signal$8[0:0]$3716 $1\exc_$signal$7[0:0]$3715 $1\exc_$signal$6[0:0]$3714 $1\exc_$signal$5[0:0]$3713 $1\exc_$signal$4[0:0]$3712 $1\exc_$signal$3[0:0]$3711 $1\exc_$signal[0:0]$3710 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3709 $1\cr_in2$1[6:0]$3708 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127241,7 +127869,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127277,22 +127905,22 @@ module \dec2 update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[6:0] - update \cr_in2$1 $0\cr_in2$1[6:0]$3680 + update \cr_in2$1 $0\cr_in2$1[6:0]$3698 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3681 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3699 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3682 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3683 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3684 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3685 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3686 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3687 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3688 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3689 + update \exc_$signal $0\exc_$signal[0:0]$3700 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3701 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3702 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3703 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3704 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3705 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3706 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3707 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] @@ -127320,50 +127948,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:78664$3621_Y - connect \$102 $pos$libresoc.v:78665$3623_Y - connect \$104 $pos$libresoc.v:78666$3625_Y - connect \$106 $eq$libresoc.v:78667$3626_Y - connect \$108 $eq$libresoc.v:78668$3627_Y - connect \$110 $eq$libresoc.v:78669$3628_Y - connect \$112 $eq$libresoc.v:78670$3629_Y - connect \$114 $and$libresoc.v:78671$3630_Y - connect \$116 $and$libresoc.v:78672$3631_Y - connect \$118 $and$libresoc.v:78673$3632_Y - connect \$120 $eq$libresoc.v:78674$3633_Y - connect \$28 $eq$libresoc.v:78675$3634_Y - connect \$30 $eq$libresoc.v:78676$3635_Y - connect \$32 $or$libresoc.v:78677$3636_Y - connect \$34 $eq$libresoc.v:78678$3637_Y - connect \$37 $eq$libresoc.v:78679$3638_Y - connect \$39 $and$libresoc.v:78680$3639_Y - connect \$41 $and$libresoc.v:78681$3640_Y - connect \$43 $eq$libresoc.v:78682$3641_Y - connect \$45 $and$libresoc.v:78683$3642_Y - connect \$47 $not$libresoc.v:78684$3643_Y - connect \$49 $and$libresoc.v:78685$3644_Y - connect \$51 $eq$libresoc.v:78686$3645_Y - connect \$53 $eq$libresoc.v:78687$3646_Y - connect \$55 $or$libresoc.v:78688$3647_Y - connect \$57 $eq$libresoc.v:78689$3648_Y - connect \$59 $eq$libresoc.v:78690$3649_Y - connect \$61 $or$libresoc.v:78691$3650_Y - connect \$63 $eq$libresoc.v:78692$3651_Y - connect \$65 $or$libresoc.v:78693$3652_Y - connect \$67 $eq$libresoc.v:78694$3653_Y - connect \$69 $or$libresoc.v:78695$3654_Y - connect \$71 $eq$libresoc.v:78696$3655_Y - connect \$73 $and$libresoc.v:78697$3656_Y - connect \$75 $and$libresoc.v:78698$3657_Y - connect \$77 $eq$libresoc.v:78699$3658_Y - connect \$79 $and$libresoc.v:78700$3659_Y - connect \$81 $not$libresoc.v:78701$3660_Y - connect \$83 $and$libresoc.v:78702$3661_Y - connect \$90 $pos$libresoc.v:78703$3663_Y - connect \$92 $pos$libresoc.v:78704$3665_Y - connect \$94 $pos$libresoc.v:78705$3667_Y - connect \$96 $pos$libresoc.v:78706$3669_Y - connect \$98 $pos$libresoc.v:78707$3671_Y + connect \$100 $pos$libresoc.v:79043$3639_Y + connect \$102 $pos$libresoc.v:79044$3641_Y + connect \$104 $pos$libresoc.v:79045$3643_Y + connect \$106 $eq$libresoc.v:79046$3644_Y + connect \$108 $eq$libresoc.v:79047$3645_Y + connect \$110 $eq$libresoc.v:79048$3646_Y + connect \$112 $eq$libresoc.v:79049$3647_Y + connect \$114 $and$libresoc.v:79050$3648_Y + connect \$116 $and$libresoc.v:79051$3649_Y + connect \$118 $and$libresoc.v:79052$3650_Y + connect \$120 $eq$libresoc.v:79053$3651_Y + connect \$28 $eq$libresoc.v:79054$3652_Y + connect \$30 $eq$libresoc.v:79055$3653_Y + connect \$32 $or$libresoc.v:79056$3654_Y + connect \$34 $eq$libresoc.v:79057$3655_Y + connect \$37 $eq$libresoc.v:79058$3656_Y + connect \$39 $and$libresoc.v:79059$3657_Y + connect \$41 $and$libresoc.v:79060$3658_Y + connect \$43 $eq$libresoc.v:79061$3659_Y + connect \$45 $and$libresoc.v:79062$3660_Y + connect \$47 $not$libresoc.v:79063$3661_Y + connect \$49 $and$libresoc.v:79064$3662_Y + connect \$51 $eq$libresoc.v:79065$3663_Y + connect \$53 $eq$libresoc.v:79066$3664_Y + connect \$55 $or$libresoc.v:79067$3665_Y + connect \$57 $eq$libresoc.v:79068$3666_Y + connect \$59 $eq$libresoc.v:79069$3667_Y + connect \$61 $or$libresoc.v:79070$3668_Y + connect \$63 $eq$libresoc.v:79071$3669_Y + connect \$65 $or$libresoc.v:79072$3670_Y + connect \$67 $eq$libresoc.v:79073$3671_Y + connect \$69 $or$libresoc.v:79074$3672_Y + connect \$71 $eq$libresoc.v:79075$3673_Y + connect \$73 $and$libresoc.v:79076$3674_Y + connect \$75 $and$libresoc.v:79077$3675_Y + connect \$77 $eq$libresoc.v:79078$3676_Y + connect \$79 $and$libresoc.v:79079$3677_Y + connect \$81 $not$libresoc.v:79080$3678_Y + connect \$83 $and$libresoc.v:79081$3679_Y + connect \$90 $pos$libresoc.v:79082$3681_Y + connect \$92 $pos$libresoc.v:79083$3683_Y + connect \$94 $pos$libresoc.v:79084$3685_Y + connect \$96 $pos$libresoc.v:79085$3687_Y + connect \$98 $pos$libresoc.v:79086$3689_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -127444,157 +128072,161 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79189.1-79849.10" +attribute \src "libresoc.v:79568.1-80248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 - attribute \src "libresoc.v:79788.3-79797.6" + attribute \src "libresoc.v:80187.3-80196.6" wire width 2 $0\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79798.3-79807.6" + attribute \src "libresoc.v:80197.3-80206.6" wire width 2 $0\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79668.3-79677.6" + attribute \src "libresoc.v:80067.3-80076.6" wire width 8 $0\dec22_asmcode[7:0] - attribute \src "libresoc.v:79708.3-79717.6" + attribute \src "libresoc.v:80107.3-80116.6" wire $0\dec22_br[0:0] - attribute \src "libresoc.v:79538.3-79547.6" + attribute \src "libresoc.v:79927.3-79936.6" wire width 3 $0\dec22_cr_in[2:0] - attribute \src "libresoc.v:79548.3-79557.6" + attribute \src "libresoc.v:79937.3-79946.6" wire width 3 $0\dec22_cr_out[2:0] - attribute \src "libresoc.v:79658.3-79667.6" + attribute \src "libresoc.v:80057.3-80066.6" wire width 2 $0\dec22_cry_in[1:0] - attribute \src "libresoc.v:79698.3-79707.6" + attribute \src "libresoc.v:80097.3-80106.6" wire $0\dec22_cry_out[0:0] - attribute \src "libresoc.v:79748.3-79757.6" + attribute \src "libresoc.v:80137.3-80146.6" wire width 5 $0\dec22_form[4:0] - attribute \src "libresoc.v:79528.3-79537.6" + attribute \src "libresoc.v:79917.3-79926.6" wire width 14 $0\dec22_function_unit[13:0] - attribute \src "libresoc.v:79808.3-79817.6" + attribute \src "libresoc.v:80207.3-80216.6" wire width 3 $0\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79818.3-79827.6" + attribute \src "libresoc.v:80217.3-80226.6" wire width 4 $0\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79828.3-79837.6" + attribute \src "libresoc.v:80227.3-80236.6" wire width 2 $0\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79638.3-79647.6" + attribute \src "libresoc.v:80027.3-80036.6" wire width 7 $0\dec22_internal_op[6:0] - attribute \src "libresoc.v:79678.3-79687.6" + attribute \src "libresoc.v:80077.3-80086.6" wire $0\dec22_inv_a[0:0] - attribute \src "libresoc.v:79688.3-79697.6" + attribute \src "libresoc.v:80087.3-80096.6" wire $0\dec22_inv_out[0:0] - attribute \src "libresoc.v:79738.3-79747.6" + attribute \src "libresoc.v:80147.3-80156.6" wire $0\dec22_is_32b[0:0] - attribute \src "libresoc.v:79618.3-79627.6" + attribute \src "libresoc.v:80017.3-80026.6" wire width 4 $0\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79768.3-79777.6" + attribute \src "libresoc.v:80167.3-80176.6" wire $0\dec22_lk[0:0] - attribute \src "libresoc.v:79838.3-79847.6" + attribute \src "libresoc.v:80237.3-80246.6" wire width 3 $0\dec22_out_sel[2:0] - attribute \src "libresoc.v:79648.3-79657.6" + attribute \src "libresoc.v:80047.3-80056.6" wire width 2 $0\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79728.3-79737.6" + attribute \src "libresoc.v:80127.3-80136.6" wire $0\dec22_rsrv[0:0] - attribute \src "libresoc.v:79778.3-79787.6" + attribute \src "libresoc.v:80177.3-80186.6" wire $0\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79758.3-79767.6" + attribute \src "libresoc.v:80157.3-80166.6" wire $0\dec22_sgn[0:0] - attribute \src "libresoc.v:79718.3-79727.6" + attribute \src "libresoc.v:80117.3-80126.6" wire $0\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79598.3-79607.6" + attribute \src "libresoc.v:79997.3-80006.6" wire width 3 $0\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79608.3-79617.6" + attribute \src "libresoc.v:80007.3-80016.6" wire width 3 $0\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79558.3-79567.6" + attribute \src "libresoc.v:79947.3-79956.6" wire width 3 $0\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79568.3-79577.6" + attribute \src "libresoc.v:79957.3-79966.6" wire width 3 $0\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79578.3-79587.6" + attribute \src "libresoc.v:79967.3-79976.6" wire width 3 $0\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79588.3-79597.6" + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $0\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" wire width 3 $0\dec22_sv_out[2:0] - attribute \src "libresoc.v:79628.3-79637.6" + attribute \src "libresoc.v:80037.3-80046.6" wire width 2 $0\dec22_upd[1:0] - attribute \src "libresoc.v:79190.7-79190.20" + attribute \src "libresoc.v:79569.7-79569.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79788.3-79797.6" + attribute \src "libresoc.v:80187.3-80196.6" wire width 2 $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79798.3-79807.6" + attribute \src "libresoc.v:80197.3-80206.6" wire width 2 $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79668.3-79677.6" + attribute \src "libresoc.v:80067.3-80076.6" wire width 8 $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79708.3-79717.6" + attribute \src "libresoc.v:80107.3-80116.6" wire $1\dec22_br[0:0] - attribute \src "libresoc.v:79538.3-79547.6" + attribute \src "libresoc.v:79927.3-79936.6" wire width 3 $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79548.3-79557.6" + attribute \src "libresoc.v:79937.3-79946.6" wire width 3 $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79658.3-79667.6" + attribute \src "libresoc.v:80057.3-80066.6" wire width 2 $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79698.3-79707.6" + attribute \src "libresoc.v:80097.3-80106.6" wire $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:79748.3-79757.6" + attribute \src "libresoc.v:80137.3-80146.6" wire width 5 $1\dec22_form[4:0] - attribute \src "libresoc.v:79528.3-79537.6" + attribute \src "libresoc.v:79917.3-79926.6" wire width 14 $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79808.3-79817.6" + attribute \src "libresoc.v:80207.3-80216.6" wire width 3 $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79818.3-79827.6" + attribute \src "libresoc.v:80217.3-80226.6" wire width 4 $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79828.3-79837.6" + attribute \src "libresoc.v:80227.3-80236.6" wire width 2 $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79638.3-79647.6" + attribute \src "libresoc.v:80027.3-80036.6" wire width 7 $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79678.3-79687.6" + attribute \src "libresoc.v:80077.3-80086.6" wire $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79688.3-79697.6" + attribute \src "libresoc.v:80087.3-80096.6" wire $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:79738.3-79747.6" + attribute \src "libresoc.v:80147.3-80156.6" wire $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:79618.3-79627.6" + attribute \src "libresoc.v:80017.3-80026.6" wire width 4 $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79768.3-79777.6" + attribute \src "libresoc.v:80167.3-80176.6" wire $1\dec22_lk[0:0] - attribute \src "libresoc.v:79838.3-79847.6" + attribute \src "libresoc.v:80237.3-80246.6" wire width 3 $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:79648.3-79657.6" + attribute \src "libresoc.v:80047.3-80056.6" wire width 2 $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79728.3-79737.6" + attribute \src "libresoc.v:80127.3-80136.6" wire $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:79778.3-79787.6" + attribute \src "libresoc.v:80177.3-80186.6" wire $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79758.3-79767.6" + attribute \src "libresoc.v:80157.3-80166.6" wire $1\dec22_sgn[0:0] - attribute \src "libresoc.v:79718.3-79727.6" + attribute \src "libresoc.v:80117.3-80126.6" wire $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79598.3-79607.6" + attribute \src "libresoc.v:79997.3-80006.6" wire width 3 $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79608.3-79617.6" + attribute \src "libresoc.v:80007.3-80016.6" wire width 3 $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79558.3-79567.6" + attribute \src "libresoc.v:79947.3-79956.6" wire width 3 $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79568.3-79577.6" + attribute \src "libresoc.v:79957.3-79966.6" wire width 3 $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79578.3-79587.6" + attribute \src "libresoc.v:79967.3-79976.6" wire width 3 $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79588.3-79597.6" + attribute \src "libresoc.v:79987.3-79996.6" + wire width 3 $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79977.3-79986.6" wire width 3 $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79628.3-79637.6" + attribute \src "libresoc.v:80037.3-80046.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -127604,7 +128236,7 @@ module \dec22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -127613,16 +128245,16 @@ module \dec22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -127654,7 +128286,7 @@ module \dec22 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -127671,7 +128303,7 @@ module \dec22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -127679,7 +128311,7 @@ module \dec22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127696,13 +128328,13 @@ module \dec22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -127779,46 +128411,46 @@ module \dec22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127826,8 +128458,8 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec22_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127835,8 +128467,8 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec22_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -127844,7 +128476,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127853,7 +128485,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127862,7 +128494,7 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -127871,41 +128503,50 @@ module \dec22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec22_upd - attribute \src "libresoc.v:79190.7-79190.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec22_upd + attribute \src "libresoc.v:79569.7-79569.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79190.7-79190.20" - process $proc$libresoc.v:79190$3763 + attribute \src "libresoc.v:79569.7-79569.20" + process $proc$libresoc.v:79569$3782 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79528.3-79537.6" - process $proc$libresoc.v:79528$3731 + attribute \src "libresoc.v:79917.3-79926.6" + process $proc$libresoc.v:79917$3749 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79529.5-79529.29" + attribute \src "libresoc.v:79918.5-79918.29" switch \initial - attribute \src "libresoc.v:79529.9-79529.17" + attribute \src "libresoc.v:79918.9-79918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127917,18 +128558,18 @@ module \dec22 sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end - attribute \src "libresoc.v:79538.3-79547.6" - process $proc$libresoc.v:79538$3732 + attribute \src "libresoc.v:79927.3-79936.6" + process $proc$libresoc.v:79927$3750 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79539.5-79539.29" + attribute \src "libresoc.v:79928.5-79928.29" switch \initial - attribute \src "libresoc.v:79539.9-79539.17" + attribute \src "libresoc.v:79928.9-79928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127940,18 +128581,18 @@ module \dec22 sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end - attribute \src "libresoc.v:79548.3-79557.6" - process $proc$libresoc.v:79548$3733 + attribute \src "libresoc.v:79937.3-79946.6" + process $proc$libresoc.v:79937$3751 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79549.5-79549.29" + attribute \src "libresoc.v:79938.5-79938.29" switch \initial - attribute \src "libresoc.v:79549.9-79549.17" + attribute \src "libresoc.v:79938.9-79938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127963,18 +128604,18 @@ module \dec22 sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end - attribute \src "libresoc.v:79558.3-79567.6" - process $proc$libresoc.v:79558$3734 + attribute \src "libresoc.v:79947.3-79956.6" + process $proc$libresoc.v:79947$3752 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79559.5-79559.29" + attribute \src "libresoc.v:79948.5-79948.29" switch \initial - attribute \src "libresoc.v:79559.9-79559.17" + attribute \src "libresoc.v:79948.9-79948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -127986,18 +128627,18 @@ module \dec22 sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end - attribute \src "libresoc.v:79568.3-79577.6" - process $proc$libresoc.v:79568$3735 + attribute \src "libresoc.v:79957.3-79966.6" + process $proc$libresoc.v:79957$3753 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79569.5-79569.29" + attribute \src "libresoc.v:79958.5-79958.29" switch \initial - attribute \src "libresoc.v:79569.9-79569.17" + attribute \src "libresoc.v:79958.9-79958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128009,18 +128650,18 @@ module \dec22 sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end - attribute \src "libresoc.v:79578.3-79587.6" - process $proc$libresoc.v:79578$3736 + attribute \src "libresoc.v:79967.3-79976.6" + process $proc$libresoc.v:79967$3754 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79579.5-79579.29" + attribute \src "libresoc.v:79968.5-79968.29" switch \initial - attribute \src "libresoc.v:79579.9-79579.17" + attribute \src "libresoc.v:79968.9-79968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128032,18 +128673,18 @@ module \dec22 sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end - attribute \src "libresoc.v:79588.3-79597.6" - process $proc$libresoc.v:79588$3737 + attribute \src "libresoc.v:79977.3-79986.6" + process $proc$libresoc.v:79977$3755 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79589.5-79589.29" + attribute \src "libresoc.v:79978.5-79978.29" switch \initial - attribute \src "libresoc.v:79589.9-79589.17" + attribute \src "libresoc.v:79978.9-79978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128055,18 +128696,41 @@ module \dec22 sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end - attribute \src "libresoc.v:79598.3-79607.6" - process $proc$libresoc.v:79598$3738 + attribute \src "libresoc.v:79987.3-79996.6" + process $proc$libresoc.v:79987$3756 + assign { } { } + assign { } { } + assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] + attribute \src "libresoc.v:79988.5-79988.29" + switch \initial + attribute \src "libresoc.v:79988.9-79988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec22_sv_out2[2:0] 3'000 + case + assign $1\dec22_sv_out2[2:0] 3'000 + end + sync always + update \dec22_sv_out2 $0\dec22_sv_out2[2:0] + end + attribute \src "libresoc.v:79997.3-80006.6" + process $proc$libresoc.v:79997$3757 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79599.5-79599.29" + attribute \src "libresoc.v:79998.5-79998.29" switch \initial - attribute \src "libresoc.v:79599.9-79599.17" + attribute \src "libresoc.v:79998.9-79998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128078,18 +128742,18 @@ module \dec22 sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end - attribute \src "libresoc.v:79608.3-79617.6" - process $proc$libresoc.v:79608$3739 + attribute \src "libresoc.v:80007.3-80016.6" + process $proc$libresoc.v:80007$3758 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79609.5-79609.29" + attribute \src "libresoc.v:80008.5-80008.29" switch \initial - attribute \src "libresoc.v:79609.9-79609.17" + attribute \src "libresoc.v:80008.9-80008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128101,18 +128765,18 @@ module \dec22 sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end - attribute \src "libresoc.v:79618.3-79627.6" - process $proc$libresoc.v:79618$3740 + attribute \src "libresoc.v:80017.3-80026.6" + process $proc$libresoc.v:80017$3759 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:79619.5-79619.29" + attribute \src "libresoc.v:80018.5-80018.29" switch \initial - attribute \src "libresoc.v:79619.9-79619.17" + attribute \src "libresoc.v:80018.9-80018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128124,64 +128788,64 @@ module \dec22 sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end - attribute \src "libresoc.v:79628.3-79637.6" - process $proc$libresoc.v:79628$3741 + attribute \src "libresoc.v:80027.3-80036.6" + process $proc$libresoc.v:80027$3760 assign { } { } assign { } { } - assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] - attribute \src "libresoc.v:79629.5-79629.29" + assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] + attribute \src "libresoc.v:80028.5-80028.29" switch \initial - attribute \src "libresoc.v:79629.9-79629.17" + attribute \src "libresoc.v:80028.9-80028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_upd[1:0] 2'00 + assign $1\dec22_internal_op[6:0] 7'1001100 case - assign $1\dec22_upd[1:0] 2'00 + assign $1\dec22_internal_op[6:0] 7'0000000 end sync always - update \dec22_upd $0\dec22_upd[1:0] + update \dec22_internal_op $0\dec22_internal_op[6:0] end - attribute \src "libresoc.v:79638.3-79647.6" - process $proc$libresoc.v:79638$3742 + attribute \src "libresoc.v:80037.3-80046.6" + process $proc$libresoc.v:80037$3761 assign { } { } assign { } { } - assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:79639.5-79639.29" + assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] + attribute \src "libresoc.v:80038.5-80038.29" switch \initial - attribute \src "libresoc.v:79639.9-79639.17" + attribute \src "libresoc.v:80038.9-80038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_internal_op[6:0] 7'1001100 + assign $1\dec22_upd[1:0] 2'00 case - assign $1\dec22_internal_op[6:0] 7'0000000 + assign $1\dec22_upd[1:0] 2'00 end sync always - update \dec22_internal_op $0\dec22_internal_op[6:0] + update \dec22_upd $0\dec22_upd[1:0] end - attribute \src "libresoc.v:79648.3-79657.6" - process $proc$libresoc.v:79648$3743 + attribute \src "libresoc.v:80047.3-80056.6" + process $proc$libresoc.v:80047$3762 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:79649.5-79649.29" + attribute \src "libresoc.v:80048.5-80048.29" switch \initial - attribute \src "libresoc.v:79649.9-79649.17" + attribute \src "libresoc.v:80048.9-80048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128193,18 +128857,18 @@ module \dec22 sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end - attribute \src "libresoc.v:79658.3-79667.6" - process $proc$libresoc.v:79658$3744 + attribute \src "libresoc.v:80057.3-80066.6" + process $proc$libresoc.v:80057$3763 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:79659.5-79659.29" + attribute \src "libresoc.v:80058.5-80058.29" switch \initial - attribute \src "libresoc.v:79659.9-79659.17" + attribute \src "libresoc.v:80058.9-80058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128216,18 +128880,18 @@ module \dec22 sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end - attribute \src "libresoc.v:79668.3-79677.6" - process $proc$libresoc.v:79668$3745 + attribute \src "libresoc.v:80067.3-80076.6" + process $proc$libresoc.v:80067$3764 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:79669.5-79669.29" + attribute \src "libresoc.v:80068.5-80068.29" switch \initial - attribute \src "libresoc.v:79669.9-79669.17" + attribute \src "libresoc.v:80068.9-80068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128239,18 +128903,18 @@ module \dec22 sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end - attribute \src "libresoc.v:79678.3-79687.6" - process $proc$libresoc.v:79678$3746 + attribute \src "libresoc.v:80077.3-80086.6" + process $proc$libresoc.v:80077$3765 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:79679.5-79679.29" + attribute \src "libresoc.v:80078.5-80078.29" switch \initial - attribute \src "libresoc.v:79679.9-79679.17" + attribute \src "libresoc.v:80078.9-80078.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128262,18 +128926,18 @@ module \dec22 sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end - attribute \src "libresoc.v:79688.3-79697.6" - process $proc$libresoc.v:79688$3747 + attribute \src "libresoc.v:80087.3-80096.6" + process $proc$libresoc.v:80087$3766 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:79689.5-79689.29" + attribute \src "libresoc.v:80088.5-80088.29" switch \initial - attribute \src "libresoc.v:79689.9-79689.17" + attribute \src "libresoc.v:80088.9-80088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128285,18 +128949,18 @@ module \dec22 sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end - attribute \src "libresoc.v:79698.3-79707.6" - process $proc$libresoc.v:79698$3748 + attribute \src "libresoc.v:80097.3-80106.6" + process $proc$libresoc.v:80097$3767 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:79699.5-79699.29" + attribute \src "libresoc.v:80098.5-80098.29" switch \initial - attribute \src "libresoc.v:79699.9-79699.17" + attribute \src "libresoc.v:80098.9-80098.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128308,18 +128972,18 @@ module \dec22 sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end - attribute \src "libresoc.v:79708.3-79717.6" - process $proc$libresoc.v:79708$3749 + attribute \src "libresoc.v:80107.3-80116.6" + process $proc$libresoc.v:80107$3768 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] - attribute \src "libresoc.v:79709.5-79709.29" + attribute \src "libresoc.v:80108.5-80108.29" switch \initial - attribute \src "libresoc.v:79709.9-79709.17" + attribute \src "libresoc.v:80108.9-80108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128331,18 +128995,18 @@ module \dec22 sync always update \dec22_br $0\dec22_br[0:0] end - attribute \src "libresoc.v:79718.3-79727.6" - process $proc$libresoc.v:79718$3750 + attribute \src "libresoc.v:80117.3-80126.6" + process $proc$libresoc.v:80117$3769 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79719.5-79719.29" + attribute \src "libresoc.v:80118.5-80118.29" switch \initial - attribute \src "libresoc.v:79719.9-79719.17" + attribute \src "libresoc.v:80118.9-80118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128354,18 +129018,18 @@ module \dec22 sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end - attribute \src "libresoc.v:79728.3-79737.6" - process $proc$libresoc.v:79728$3751 + attribute \src "libresoc.v:80127.3-80136.6" + process $proc$libresoc.v:80127$3770 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:79729.5-79729.29" + attribute \src "libresoc.v:80128.5-80128.29" switch \initial - attribute \src "libresoc.v:79729.9-79729.17" + attribute \src "libresoc.v:80128.9-80128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128377,64 +129041,64 @@ module \dec22 sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end - attribute \src "libresoc.v:79738.3-79747.6" - process $proc$libresoc.v:79738$3752 + attribute \src "libresoc.v:80137.3-80146.6" + process $proc$libresoc.v:80137$3771 assign { } { } assign { } { } - assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:79739.5-79739.29" + assign $0\dec22_form[4:0] $1\dec22_form[4:0] + attribute \src "libresoc.v:80138.5-80138.29" switch \initial - attribute \src "libresoc.v:79739.9-79739.17" + attribute \src "libresoc.v:80138.9-80138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_is_32b[0:0] 1'0 + assign $1\dec22_form[4:0] 5'11101 case - assign $1\dec22_is_32b[0:0] 1'0 + assign $1\dec22_form[4:0] 5'00000 end sync always - update \dec22_is_32b $0\dec22_is_32b[0:0] + update \dec22_form $0\dec22_form[4:0] end - attribute \src "libresoc.v:79748.3-79757.6" - process $proc$libresoc.v:79748$3753 + attribute \src "libresoc.v:80147.3-80156.6" + process $proc$libresoc.v:80147$3772 assign { } { } assign { } { } - assign $0\dec22_form[4:0] $1\dec22_form[4:0] - attribute \src "libresoc.v:79749.5-79749.29" + assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] + attribute \src "libresoc.v:80148.5-80148.29" switch \initial - attribute \src "libresoc.v:79749.9-79749.17" + attribute \src "libresoc.v:80148.9-80148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec22_form[4:0] 5'11101 + assign $1\dec22_is_32b[0:0] 1'0 case - assign $1\dec22_form[4:0] 5'00000 + assign $1\dec22_is_32b[0:0] 1'0 end sync always - update \dec22_form $0\dec22_form[4:0] + update \dec22_is_32b $0\dec22_is_32b[0:0] end - attribute \src "libresoc.v:79758.3-79767.6" - process $proc$libresoc.v:79758$3754 + attribute \src "libresoc.v:80157.3-80166.6" + process $proc$libresoc.v:80157$3773 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] - attribute \src "libresoc.v:79759.5-79759.29" + attribute \src "libresoc.v:80158.5-80158.29" switch \initial - attribute \src "libresoc.v:79759.9-79759.17" + attribute \src "libresoc.v:80158.9-80158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128446,18 +129110,18 @@ module \dec22 sync always update \dec22_sgn $0\dec22_sgn[0:0] end - attribute \src "libresoc.v:79768.3-79777.6" - process $proc$libresoc.v:79768$3755 + attribute \src "libresoc.v:80167.3-80176.6" + process $proc$libresoc.v:80167$3774 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] - attribute \src "libresoc.v:79769.5-79769.29" + attribute \src "libresoc.v:80168.5-80168.29" switch \initial - attribute \src "libresoc.v:79769.9-79769.17" + attribute \src "libresoc.v:80168.9-80168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128469,18 +129133,18 @@ module \dec22 sync always update \dec22_lk $0\dec22_lk[0:0] end - attribute \src "libresoc.v:79778.3-79787.6" - process $proc$libresoc.v:79778$3756 + attribute \src "libresoc.v:80177.3-80186.6" + process $proc$libresoc.v:80177$3775 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:79779.5-79779.29" + attribute \src "libresoc.v:80178.5-80178.29" switch \initial - attribute \src "libresoc.v:79779.9-79779.17" + attribute \src "libresoc.v:80178.9-80178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128492,18 +129156,18 @@ module \dec22 sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end - attribute \src "libresoc.v:79788.3-79797.6" - process $proc$libresoc.v:79788$3757 + attribute \src "libresoc.v:80187.3-80196.6" + process $proc$libresoc.v:80187$3776 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:79789.5-79789.29" + attribute \src "libresoc.v:80188.5-80188.29" switch \initial - attribute \src "libresoc.v:79789.9-79789.17" + attribute \src "libresoc.v:80188.9-80188.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128515,18 +129179,18 @@ module \dec22 sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end - attribute \src "libresoc.v:79798.3-79807.6" - process $proc$libresoc.v:79798$3758 + attribute \src "libresoc.v:80197.3-80206.6" + process $proc$libresoc.v:80197$3777 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:79799.5-79799.29" + attribute \src "libresoc.v:80198.5-80198.29" switch \initial - attribute \src "libresoc.v:79799.9-79799.17" + attribute \src "libresoc.v:80198.9-80198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128538,18 +129202,18 @@ module \dec22 sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end - attribute \src "libresoc.v:79808.3-79817.6" - process $proc$libresoc.v:79808$3759 + attribute \src "libresoc.v:80207.3-80216.6" + process $proc$libresoc.v:80207$3778 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:79809.5-79809.29" + attribute \src "libresoc.v:80208.5-80208.29" switch \initial - attribute \src "libresoc.v:79809.9-79809.17" + attribute \src "libresoc.v:80208.9-80208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128561,18 +129225,18 @@ module \dec22 sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end - attribute \src "libresoc.v:79818.3-79827.6" - process $proc$libresoc.v:79818$3760 + attribute \src "libresoc.v:80217.3-80226.6" + process $proc$libresoc.v:80217$3779 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:79819.5-79819.29" + attribute \src "libresoc.v:80218.5-80218.29" switch \initial - attribute \src "libresoc.v:79819.9-79819.17" + attribute \src "libresoc.v:80218.9-80218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128584,18 +129248,18 @@ module \dec22 sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end - attribute \src "libresoc.v:79828.3-79837.6" - process $proc$libresoc.v:79828$3761 + attribute \src "libresoc.v:80227.3-80236.6" + process $proc$libresoc.v:80227$3780 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:79829.5-79829.29" + attribute \src "libresoc.v:80228.5-80228.29" switch \initial - attribute \src "libresoc.v:79829.9-79829.17" + attribute \src "libresoc.v:80228.9-80228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128607,18 +129271,18 @@ module \dec22 sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end - attribute \src "libresoc.v:79838.3-79847.6" - process $proc$libresoc.v:79838$3762 + attribute \src "libresoc.v:80237.3-80246.6" + process $proc$libresoc.v:80237$3781 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:79839.5-79839.29" + attribute \src "libresoc.v:80238.5-80238.29" switch \initial - attribute \src "libresoc.v:79839.9-79839.17" + attribute \src "libresoc.v:80238.9-80238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 @@ -128632,157 +129296,161 @@ module \dec22 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:79853.1-81377.10" +attribute \src "libresoc.v:80252.1-81823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:81154.3-81190.6" + attribute \src "libresoc.v:81600.3-81636.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81191.3-81227.6" + attribute \src "libresoc.v:81637.3-81673.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80710.3-80746.6" + attribute \src "libresoc.v:81156.3-81192.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:80858.3-80894.6" + attribute \src "libresoc.v:81304.3-81340.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:80229.3-80265.6" + attribute \src "libresoc.v:80638.3-80674.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:80266.3-80302.6" + attribute \src "libresoc.v:80675.3-80711.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:80673.3-80709.6" + attribute \src "libresoc.v:81119.3-81155.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:80821.3-80857.6" + attribute \src "libresoc.v:81267.3-81303.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:81006.3-81042.6" + attribute \src "libresoc.v:81415.3-81451.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:80192.3-80228.6" + attribute \src "libresoc.v:80601.3-80637.6" wire width 14 $0\dec30_function_unit[13:0] - attribute \src "libresoc.v:81228.3-81264.6" + attribute \src "libresoc.v:81674.3-81710.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81265.3-81301.6" + attribute \src "libresoc.v:81711.3-81747.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81302.3-81338.6" + attribute \src "libresoc.v:81748.3-81784.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80599.3-80635.6" + attribute \src "libresoc.v:81008.3-81044.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:80747.3-80783.6" + attribute \src "libresoc.v:81193.3-81229.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:80784.3-80820.6" + attribute \src "libresoc.v:81230.3-81266.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:80969.3-81005.6" + attribute \src "libresoc.v:81452.3-81488.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:80525.3-80561.6" + attribute \src "libresoc.v:80971.3-81007.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81080.3-81116.6" + attribute \src "libresoc.v:81526.3-81562.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:81339.3-81375.6" + attribute \src "libresoc.v:81785.3-81821.6" wire width 3 $0\dec30_out_sel[2:0] - attribute \src "libresoc.v:80636.3-80672.6" + attribute \src "libresoc.v:81082.3-81118.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80932.3-80968.6" + attribute \src "libresoc.v:81378.3-81414.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:81117.3-81153.6" + attribute \src "libresoc.v:81563.3-81599.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81043.3-81079.6" + attribute \src "libresoc.v:81489.3-81525.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:80895.3-80931.6" + attribute \src "libresoc.v:81341.3-81377.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80451.3-80487.6" + attribute \src "libresoc.v:80897.3-80933.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80488.3-80524.6" + attribute \src "libresoc.v:80934.3-80970.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80303.3-80339.6" + attribute \src "libresoc.v:80712.3-80748.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80340.3-80376.6" + attribute \src "libresoc.v:80749.3-80785.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80377.3-80413.6" + attribute \src "libresoc.v:80786.3-80822.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80414.3-80450.6" + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $0\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:80562.3-80598.6" + attribute \src "libresoc.v:81045.3-81081.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:79854.7-79854.20" + attribute \src "libresoc.v:80253.7-80253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81154.3-81190.6" + attribute \src "libresoc.v:81600.3-81636.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81191.3-81227.6" + attribute \src "libresoc.v:81637.3-81673.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80710.3-80746.6" + attribute \src "libresoc.v:81156.3-81192.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80858.3-80894.6" + attribute \src "libresoc.v:81304.3-81340.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:80229.3-80265.6" + attribute \src "libresoc.v:80638.3-80674.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80266.3-80302.6" + attribute \src "libresoc.v:80675.3-80711.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80673.3-80709.6" + attribute \src "libresoc.v:81119.3-81155.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80821.3-80857.6" + attribute \src "libresoc.v:81267.3-81303.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81006.3-81042.6" + attribute \src "libresoc.v:81415.3-81451.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:80192.3-80228.6" + attribute \src "libresoc.v:80601.3-80637.6" wire width 14 $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:81228.3-81264.6" + attribute \src "libresoc.v:81674.3-81710.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81265.3-81301.6" + attribute \src "libresoc.v:81711.3-81747.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81302.3-81338.6" + attribute \src "libresoc.v:81748.3-81784.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80599.3-80635.6" + attribute \src "libresoc.v:81008.3-81044.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80747.3-80783.6" + attribute \src "libresoc.v:81193.3-81229.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80784.3-80820.6" + attribute \src "libresoc.v:81230.3-81266.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80969.3-81005.6" + attribute \src "libresoc.v:81452.3-81488.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80525.3-80561.6" + attribute \src "libresoc.v:80971.3-81007.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81080.3-81116.6" + attribute \src "libresoc.v:81526.3-81562.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:81339.3-81375.6" + attribute \src "libresoc.v:81785.3-81821.6" wire width 3 $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:80636.3-80672.6" + attribute \src "libresoc.v:81082.3-81118.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80932.3-80968.6" + attribute \src "libresoc.v:81378.3-81414.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81117.3-81153.6" + attribute \src "libresoc.v:81563.3-81599.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81043.3-81079.6" + attribute \src "libresoc.v:81489.3-81525.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:80895.3-80931.6" + attribute \src "libresoc.v:81341.3-81377.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80451.3-80487.6" + attribute \src "libresoc.v:80897.3-80933.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80488.3-80524.6" + attribute \src "libresoc.v:80934.3-80970.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80303.3-80339.6" + attribute \src "libresoc.v:80712.3-80748.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80340.3-80376.6" + attribute \src "libresoc.v:80749.3-80785.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80377.3-80413.6" + attribute \src "libresoc.v:80786.3-80822.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80414.3-80450.6" + attribute \src "libresoc.v:80860.3-80896.6" + wire width 3 $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80823.3-80859.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80562.3-80598.6" + attribute \src "libresoc.v:81045.3-81081.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec30_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec30_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128792,7 +129460,7 @@ module \dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -128801,16 +129469,16 @@ module \dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -128842,7 +129510,7 @@ module \dec30 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -128859,7 +129527,7 @@ module \dec30 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -128867,7 +129535,7 @@ module \dec30 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -128884,13 +129552,13 @@ module \dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -128967,46 +129635,46 @@ module \dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec30_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec30_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129014,8 +129682,8 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec30_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec30_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129023,8 +129691,8 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec30_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec30_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -129032,7 +129700,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec30_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129041,7 +129709,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec30_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129050,7 +129718,7 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec30_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -129059,41 +129727,50 @@ module \dec30 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec30_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec30_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec30_upd - attribute \src "libresoc.v:79854.7-79854.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec30_upd + attribute \src "libresoc.v:80253.7-80253.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79854.7-79854.20" - process $proc$libresoc.v:79854$3796 + attribute \src "libresoc.v:80253.7-80253.20" + process $proc$libresoc.v:80253$3816 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80192.3-80228.6" - process $proc$libresoc.v:80192$3764 + attribute \src "libresoc.v:80601.3-80637.6" + process $proc$libresoc.v:80601$3783 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:80193.5-80193.29" + attribute \src "libresoc.v:80602.5-80602.29" switch \initial - attribute \src "libresoc.v:80193.9-80193.17" + attribute \src "libresoc.v:80602.9-80602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129141,18 +129818,18 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:80229.3-80265.6" - process $proc$libresoc.v:80229$3765 + attribute \src "libresoc.v:80638.3-80674.6" + process $proc$libresoc.v:80638$3784 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80230.5-80230.29" + attribute \src "libresoc.v:80639.5-80639.29" switch \initial - attribute \src "libresoc.v:80230.9-80230.17" + attribute \src "libresoc.v:80639.9-80639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129200,18 +129877,18 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:80266.3-80302.6" - process $proc$libresoc.v:80266$3766 + attribute \src "libresoc.v:80675.3-80711.6" + process $proc$libresoc.v:80675$3785 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80267.5-80267.29" + attribute \src "libresoc.v:80676.5-80676.29" switch \initial - attribute \src "libresoc.v:80267.9-80267.17" + attribute \src "libresoc.v:80676.9-80676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129259,18 +129936,18 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:80303.3-80339.6" - process $proc$libresoc.v:80303$3767 + attribute \src "libresoc.v:80712.3-80748.6" + process $proc$libresoc.v:80712$3786 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80304.5-80304.29" + attribute \src "libresoc.v:80713.5-80713.29" switch \initial - attribute \src "libresoc.v:80304.9-80304.17" + attribute \src "libresoc.v:80713.9-80713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129318,18 +129995,18 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:80340.3-80376.6" - process $proc$libresoc.v:80340$3768 + attribute \src "libresoc.v:80749.3-80785.6" + process $proc$libresoc.v:80749$3787 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80341.5-80341.29" + attribute \src "libresoc.v:80750.5-80750.29" switch \initial - attribute \src "libresoc.v:80341.9-80341.17" + attribute \src "libresoc.v:80750.9-80750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129377,18 +130054,18 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:80377.3-80413.6" - process $proc$libresoc.v:80377$3769 + attribute \src "libresoc.v:80786.3-80822.6" + process $proc$libresoc.v:80786$3788 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80378.5-80378.29" + attribute \src "libresoc.v:80787.5-80787.29" switch \initial - attribute \src "libresoc.v:80378.9-80378.17" + attribute \src "libresoc.v:80787.9-80787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129436,18 +130113,18 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:80414.3-80450.6" - process $proc$libresoc.v:80414$3770 + attribute \src "libresoc.v:80823.3-80859.6" + process $proc$libresoc.v:80823$3789 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80415.5-80415.29" + attribute \src "libresoc.v:80824.5-80824.29" switch \initial - attribute \src "libresoc.v:80415.9-80415.17" + attribute \src "libresoc.v:80824.9-80824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129495,18 +130172,77 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:80451.3-80487.6" - process $proc$libresoc.v:80451$3771 + attribute \src "libresoc.v:80860.3-80896.6" + process $proc$libresoc.v:80860$3790 + assign { } { } + assign { } { } + assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] + attribute \src "libresoc.v:80861.5-80861.29" + switch \initial + attribute \src "libresoc.v:80861.9-80861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_out2[2:0] 3'000 + case + assign $1\dec30_sv_out2[2:0] 3'000 + end + sync always + update \dec30_sv_out2 $0\dec30_sv_out2[2:0] + end + attribute \src "libresoc.v:80897.3-80933.6" + process $proc$libresoc.v:80897$3791 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80452.5-80452.29" + attribute \src "libresoc.v:80898.5-80898.29" switch \initial - attribute \src "libresoc.v:80452.9-80452.17" + attribute \src "libresoc.v:80898.9-80898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129554,18 +130290,18 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:80488.3-80524.6" - process $proc$libresoc.v:80488$3772 + attribute \src "libresoc.v:80934.3-80970.6" + process $proc$libresoc.v:80934$3792 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80489.5-80489.29" + attribute \src "libresoc.v:80935.5-80935.29" switch \initial - attribute \src "libresoc.v:80489.9-80489.17" + attribute \src "libresoc.v:80935.9-80935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129613,18 +130349,18 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:80525.3-80561.6" - process $proc$libresoc.v:80525$3773 + attribute \src "libresoc.v:80971.3-81007.6" + process $proc$libresoc.v:80971$3793 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80526.5-80526.29" + attribute \src "libresoc.v:80972.5-80972.29" switch \initial - attribute \src "libresoc.v:80526.9-80526.17" + attribute \src "libresoc.v:80972.9-80972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129672,136 +130408,136 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:80562.3-80598.6" - process $proc$libresoc.v:80562$3774 + attribute \src "libresoc.v:81008.3-81044.6" + process $proc$libresoc.v:81008$3794 assign { } { } assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:80563.5-80563.29" + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:81009.5-81009.29" switch \initial - attribute \src "libresoc.v:80563.9-80563.17" + attribute \src "libresoc.v:81009.9-81009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0111010 case - assign $1\dec30_upd[1:0] 2'00 + assign $1\dec30_internal_op[6:0] 7'0000000 end sync always - update \dec30_upd $0\dec30_upd[1:0] + update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:80599.3-80635.6" - process $proc$libresoc.v:80599$3775 + attribute \src "libresoc.v:81045.3-81081.6" + process $proc$libresoc.v:81045$3795 assign { } { } assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80600.5-80600.29" + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:81046.5-81046.29" switch \initial - attribute \src "libresoc.v:80600.9-80600.17" + attribute \src "libresoc.v:81046.9-81046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 + assign $1\dec30_upd[1:0] 2'00 case - assign $1\dec30_internal_op[6:0] 7'0000000 + assign $1\dec30_upd[1:0] 2'00 end sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] + update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:80636.3-80672.6" - process $proc$libresoc.v:80636$3776 + attribute \src "libresoc.v:81082.3-81118.6" + process $proc$libresoc.v:81082$3796 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80637.5-80637.29" + attribute \src "libresoc.v:81083.5-81083.29" switch \initial - attribute \src "libresoc.v:80637.9-80637.17" + attribute \src "libresoc.v:81083.9-81083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129849,18 +130585,18 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:80673.3-80709.6" - process $proc$libresoc.v:80673$3777 + attribute \src "libresoc.v:81119.3-81155.6" + process $proc$libresoc.v:81119$3797 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80674.5-80674.29" + attribute \src "libresoc.v:81120.5-81120.29" switch \initial - attribute \src "libresoc.v:80674.9-80674.17" + attribute \src "libresoc.v:81120.9-81120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129908,18 +130644,18 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:80710.3-80746.6" - process $proc$libresoc.v:80710$3778 + attribute \src "libresoc.v:81156.3-81192.6" + process $proc$libresoc.v:81156$3798 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80711.5-80711.29" + attribute \src "libresoc.v:81157.5-81157.29" switch \initial - attribute \src "libresoc.v:80711.9-80711.17" + attribute \src "libresoc.v:81157.9-81157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -129967,18 +130703,18 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:80747.3-80783.6" - process $proc$libresoc.v:80747$3779 + attribute \src "libresoc.v:81193.3-81229.6" + process $proc$libresoc.v:81193$3799 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80748.5-80748.29" + attribute \src "libresoc.v:81194.5-81194.29" switch \initial - attribute \src "libresoc.v:80748.9-80748.17" + attribute \src "libresoc.v:81194.9-81194.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130026,18 +130762,18 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:80784.3-80820.6" - process $proc$libresoc.v:80784$3780 + attribute \src "libresoc.v:81230.3-81266.6" + process $proc$libresoc.v:81230$3800 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80785.5-80785.29" + attribute \src "libresoc.v:81231.5-81231.29" switch \initial - attribute \src "libresoc.v:80785.9-80785.17" + attribute \src "libresoc.v:81231.9-81231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130085,18 +130821,18 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:80821.3-80857.6" - process $proc$libresoc.v:80821$3781 + attribute \src "libresoc.v:81267.3-81303.6" + process $proc$libresoc.v:81267$3801 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:80822.5-80822.29" + attribute \src "libresoc.v:81268.5-81268.29" switch \initial - attribute \src "libresoc.v:80822.9-80822.17" + attribute \src "libresoc.v:81268.9-81268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130144,18 +130880,18 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:80858.3-80894.6" - process $proc$libresoc.v:80858$3782 + attribute \src "libresoc.v:81304.3-81340.6" + process $proc$libresoc.v:81304$3802 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:80859.5-80859.29" + attribute \src "libresoc.v:81305.5-81305.29" switch \initial - attribute \src "libresoc.v:80859.9-80859.17" + attribute \src "libresoc.v:81305.9-81305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130203,18 +130939,18 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:80895.3-80931.6" - process $proc$libresoc.v:80895$3783 + attribute \src "libresoc.v:81341.3-81377.6" + process $proc$libresoc.v:81341$3803 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80896.5-80896.29" + attribute \src "libresoc.v:81342.5-81342.29" switch \initial - attribute \src "libresoc.v:80896.9-80896.17" + attribute \src "libresoc.v:81342.9-81342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130262,18 +130998,18 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:80932.3-80968.6" - process $proc$libresoc.v:80932$3784 + attribute \src "libresoc.v:81378.3-81414.6" + process $proc$libresoc.v:81378$3804 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:80933.5-80933.29" + attribute \src "libresoc.v:81379.5-81379.29" switch \initial - attribute \src "libresoc.v:80933.9-80933.17" + attribute \src "libresoc.v:81379.9-81379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130321,136 +131057,136 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:80969.3-81005.6" - process $proc$libresoc.v:80969$3785 + attribute \src "libresoc.v:81415.3-81451.6" + process $proc$libresoc.v:81415$3805 assign { } { } assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80970.5-80970.29" + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:81416.5-81416.29" switch \initial - attribute \src "libresoc.v:80970.9-80970.17" + attribute \src "libresoc.v:81416.9-81416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'10100 case - assign $1\dec30_is_32b[0:0] 1'0 + assign $1\dec30_form[4:0] 5'00000 end sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] + update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:81006.3-81042.6" - process $proc$libresoc.v:81006$3786 + attribute \src "libresoc.v:81452.3-81488.6" + process $proc$libresoc.v:81452$3806 assign { } { } assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:81007.5-81007.29" + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:81453.5-81453.29" switch \initial - attribute \src "libresoc.v:81007.9-81007.17" + attribute \src "libresoc.v:81453.9-81453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\dec30_form[4:0] 5'10101 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\dec30_form[4:0] 5'10100 + assign $1\dec30_is_32b[0:0] 1'0 case - assign $1\dec30_form[4:0] 5'00000 + assign $1\dec30_is_32b[0:0] 1'0 end sync always - update \dec30_form $0\dec30_form[4:0] + update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:81043.3-81079.6" - process $proc$libresoc.v:81043$3787 + attribute \src "libresoc.v:81489.3-81525.6" + process $proc$libresoc.v:81489$3807 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81044.5-81044.29" + attribute \src "libresoc.v:81490.5-81490.29" switch \initial - attribute \src "libresoc.v:81044.9-81044.17" + attribute \src "libresoc.v:81490.9-81490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130498,18 +131234,18 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:81080.3-81116.6" - process $proc$libresoc.v:81080$3788 + attribute \src "libresoc.v:81526.3-81562.6" + process $proc$libresoc.v:81526$3808 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:81081.5-81081.29" + attribute \src "libresoc.v:81527.5-81527.29" switch \initial - attribute \src "libresoc.v:81081.9-81081.17" + attribute \src "libresoc.v:81527.9-81527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130557,18 +131293,18 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:81117.3-81153.6" - process $proc$libresoc.v:81117$3789 + attribute \src "libresoc.v:81563.3-81599.6" + process $proc$libresoc.v:81563$3809 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81118.5-81118.29" + attribute \src "libresoc.v:81564.5-81564.29" switch \initial - attribute \src "libresoc.v:81118.9-81118.17" + attribute \src "libresoc.v:81564.9-81564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130616,18 +131352,18 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:81154.3-81190.6" - process $proc$libresoc.v:81154$3790 + attribute \src "libresoc.v:81600.3-81636.6" + process $proc$libresoc.v:81600$3810 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81155.5-81155.29" + attribute \src "libresoc.v:81601.5-81601.29" switch \initial - attribute \src "libresoc.v:81155.9-81155.17" + attribute \src "libresoc.v:81601.9-81601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130675,18 +131411,18 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:81191.3-81227.6" - process $proc$libresoc.v:81191$3791 + attribute \src "libresoc.v:81637.3-81673.6" + process $proc$libresoc.v:81637$3811 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81192.5-81192.29" + attribute \src "libresoc.v:81638.5-81638.29" switch \initial - attribute \src "libresoc.v:81192.9-81192.17" + attribute \src "libresoc.v:81638.9-81638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130734,18 +131470,18 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:81228.3-81264.6" - process $proc$libresoc.v:81228$3792 + attribute \src "libresoc.v:81674.3-81710.6" + process $proc$libresoc.v:81674$3812 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81229.5-81229.29" + attribute \src "libresoc.v:81675.5-81675.29" switch \initial - attribute \src "libresoc.v:81229.9-81229.17" + attribute \src "libresoc.v:81675.9-81675.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130793,18 +131529,18 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:81265.3-81301.6" - process $proc$libresoc.v:81265$3793 + attribute \src "libresoc.v:81711.3-81747.6" + process $proc$libresoc.v:81711$3813 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81266.5-81266.29" + attribute \src "libresoc.v:81712.5-81712.29" switch \initial - attribute \src "libresoc.v:81266.9-81266.17" + attribute \src "libresoc.v:81712.9-81712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130852,18 +131588,18 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:81302.3-81338.6" - process $proc$libresoc.v:81302$3794 + attribute \src "libresoc.v:81748.3-81784.6" + process $proc$libresoc.v:81748$3814 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81303.5-81303.29" + attribute \src "libresoc.v:81749.5-81749.29" switch \initial - attribute \src "libresoc.v:81303.9-81303.17" + attribute \src "libresoc.v:81749.9-81749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130911,18 +131647,18 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:81339.3-81375.6" - process $proc$libresoc.v:81339$3795 + attribute \src "libresoc.v:81785.3-81821.6" + process $proc$libresoc.v:81785$3815 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81340.5-81340.29" + attribute \src "libresoc.v:81786.5-81786.29" switch \initial - attribute \src "libresoc.v:81340.9-81340.17" + attribute \src "libresoc.v:81786.9-81786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -130972,157 +131708,161 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:81381.1-89778.10" +attribute \src "libresoc.v:81827.1-90475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:88050.3-88110.6" + attribute \src "libresoc.v:88686.3-88746.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88111.3-88171.6" + attribute \src "libresoc.v:88747.3-88807.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87989.3-88049.6" + attribute \src "libresoc.v:88625.3-88685.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:89331.3-89391.6" + attribute \src "libresoc.v:90028.3-90088.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:88416.3-88476.6" + attribute \src "libresoc.v:89052.3-89112.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:88477.3-88537.6" + attribute \src "libresoc.v:89113.3-89173.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:89087.3-89147.6" + attribute \src "libresoc.v:89784.3-89844.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:89270.3-89330.6" + attribute \src "libresoc.v:89967.3-90027.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:87928.3-87988.6" + attribute \src "libresoc.v:88564.3-88624.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:87806.3-87866.6" + attribute \src "libresoc.v:88442.3-88502.6" wire width 14 $0\dec31_function_unit[13:0] - attribute \src "libresoc.v:88172.3-88232.6" + attribute \src "libresoc.v:88808.3-88868.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88233.3-88293.6" + attribute \src "libresoc.v:88869.3-88929.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88294.3-88354.6" + attribute \src "libresoc.v:88930.3-88990.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87867.3-87927.6" + attribute \src "libresoc.v:88503.3-88563.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:89148.3-89208.6" + attribute \src "libresoc.v:89845.3-89905.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:89209.3-89269.6" + attribute \src "libresoc.v:89906.3-89966.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:89514.3-89574.6" + attribute \src "libresoc.v:90211.3-90271.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:88904.3-88964.6" + attribute \src "libresoc.v:89601.3-89661.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89636.3-89696.6" + attribute \src "libresoc.v:90333.3-90393.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:88355.3-88415.6" + attribute \src "libresoc.v:88991.3-89051.6" wire width 3 $0\dec31_out_sel[2:0] - attribute \src "libresoc.v:89026.3-89086.6" + attribute \src "libresoc.v:89723.3-89783.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89453.3-89513.6" + attribute \src "libresoc.v:90150.3-90210.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:89697.3-89757.6" + attribute \src "libresoc.v:90394.3-90454.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89575.3-89635.6" + attribute \src "libresoc.v:90272.3-90332.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:89392.3-89452.6" + attribute \src "libresoc.v:90089.3-90149.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88782.3-88842.6" + attribute \src "libresoc.v:89479.3-89539.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88843.3-88903.6" + attribute \src "libresoc.v:89540.3-89600.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88538.3-88598.6" + attribute \src "libresoc.v:89174.3-89234.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88599.3-88659.6" + attribute \src "libresoc.v:89235.3-89295.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88660.3-88720.6" + attribute \src "libresoc.v:89296.3-89356.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88721.3-88781.6" + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $0\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:88965.3-89025.6" + attribute \src "libresoc.v:89662.3-89722.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:81382.7-81382.20" + attribute \src "libresoc.v:81828.7-81828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88050.3-88110.6" + attribute \src "libresoc.v:88686.3-88746.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88111.3-88171.6" + attribute \src "libresoc.v:88747.3-88807.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87989.3-88049.6" + attribute \src "libresoc.v:88625.3-88685.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:89331.3-89391.6" + attribute \src "libresoc.v:90028.3-90088.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:88416.3-88476.6" + attribute \src "libresoc.v:89052.3-89112.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:88477.3-88537.6" + attribute \src "libresoc.v:89113.3-89173.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89087.3-89147.6" + attribute \src "libresoc.v:89784.3-89844.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89270.3-89330.6" + attribute \src "libresoc.v:89967.3-90027.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:87928.3-87988.6" + attribute \src "libresoc.v:88564.3-88624.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:87806.3-87866.6" + attribute \src "libresoc.v:88442.3-88502.6" wire width 14 $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88172.3-88232.6" + attribute \src "libresoc.v:88808.3-88868.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88233.3-88293.6" + attribute \src "libresoc.v:88869.3-88929.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88294.3-88354.6" + attribute \src "libresoc.v:88930.3-88990.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87867.3-87927.6" + attribute \src "libresoc.v:88503.3-88563.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:89148.3-89208.6" + attribute \src "libresoc.v:89845.3-89905.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89209.3-89269.6" + attribute \src "libresoc.v:89906.3-89966.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89514.3-89574.6" + attribute \src "libresoc.v:90211.3-90271.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:88904.3-88964.6" + attribute \src "libresoc.v:89601.3-89661.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89636.3-89696.6" + attribute \src "libresoc.v:90333.3-90393.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:88355.3-88415.6" + attribute \src "libresoc.v:88991.3-89051.6" wire width 3 $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:89026.3-89086.6" + attribute \src "libresoc.v:89723.3-89783.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89453.3-89513.6" + attribute \src "libresoc.v:90150.3-90210.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:89697.3-89757.6" + attribute \src "libresoc.v:90394.3-90454.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89575.3-89635.6" + attribute \src "libresoc.v:90272.3-90332.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:89392.3-89452.6" + attribute \src "libresoc.v:90089.3-90149.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88782.3-88842.6" + attribute \src "libresoc.v:89479.3-89539.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88843.3-88903.6" + attribute \src "libresoc.v:89540.3-89600.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88538.3-88598.6" + attribute \src "libresoc.v:89174.3-89234.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88599.3-88659.6" + attribute \src "libresoc.v:89235.3-89295.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88660.3-88720.6" + attribute \src "libresoc.v:89296.3-89356.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88721.3-88781.6" + attribute \src "libresoc.v:89418.3-89478.6" + wire width 3 $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89357.3-89417.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88965.3-89025.6" + attribute \src "libresoc.v:89662.3-89722.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -131132,7 +131872,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131141,31 +131881,31 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131176,7 +131916,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131185,15 +131925,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131226,7 +131966,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131243,7 +131983,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131251,7 +131991,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131268,13 +132008,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131351,13 +132091,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131365,9 +132105,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131375,21 +132115,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131398,7 +132138,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131407,7 +132147,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131416,7 +132156,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131425,7 +132165,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131434,7 +132174,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131443,32 +132183,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub0_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131479,7 +132228,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131488,15 +132237,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131529,7 +132278,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131546,7 +132295,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131554,7 +132303,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131571,13 +132320,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131654,13 +132403,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131668,9 +132417,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131678,21 +132427,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131701,7 +132450,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131710,7 +132459,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131719,7 +132468,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131728,7 +132477,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131737,7 +132486,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -131746,32 +132495,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub10_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -131782,7 +132540,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -131791,15 +132549,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131832,7 +132590,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -131849,7 +132607,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131857,7 +132615,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131874,13 +132632,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131957,13 +132715,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131971,9 +132729,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -131981,21 +132739,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132004,7 +132762,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132013,7 +132771,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132022,7 +132780,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132031,7 +132789,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132040,7 +132798,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132049,32 +132807,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub11_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132085,7 +132852,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132094,15 +132861,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132135,7 +132902,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132152,7 +132919,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132160,7 +132927,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132177,13 +132944,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132260,13 +133027,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132274,9 +133041,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132284,21 +133051,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132307,7 +133074,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132316,7 +133083,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132325,7 +133092,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132334,7 +133101,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132343,7 +133110,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132352,32 +133119,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub15_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132388,7 +133164,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132397,15 +133173,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132438,7 +133214,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132455,7 +133231,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132463,7 +133239,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132480,13 +133256,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132563,13 +133339,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132577,9 +133353,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132587,21 +133363,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132610,7 +133386,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132619,7 +133395,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132628,7 +133404,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132637,7 +133413,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132646,7 +133422,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132655,32 +133431,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub16_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132691,7 +133476,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132700,15 +133485,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132741,7 +133526,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -132758,7 +133543,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132766,7 +133551,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132783,13 +133568,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132866,13 +133651,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132880,9 +133665,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -132890,21 +133675,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132913,7 +133698,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132922,7 +133707,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132931,7 +133716,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132940,7 +133725,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132949,7 +133734,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -132958,32 +133743,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub18_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132994,7 +133788,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133003,15 +133797,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133044,7 +133838,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133061,7 +133855,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133069,7 +133863,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133086,13 +133880,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133169,13 +133963,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133183,9 +133977,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133193,21 +133987,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133216,7 +134010,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133225,7 +134019,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133234,7 +134028,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133243,7 +134037,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133252,7 +134046,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133261,32 +134055,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub19_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133297,7 +134100,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133306,15 +134109,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133347,7 +134150,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133364,7 +134167,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133372,7 +134175,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133389,13 +134192,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133472,13 +134275,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133486,9 +134289,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133496,21 +134299,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133519,7 +134322,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133528,7 +134331,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133537,7 +134340,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133546,7 +134349,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133555,7 +134358,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133564,32 +134367,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub20_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133600,7 +134412,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133609,15 +134421,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133650,7 +134462,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133667,7 +134479,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133675,7 +134487,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133692,13 +134504,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -133775,13 +134587,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -133789,9 +134601,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -133799,21 +134611,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133822,7 +134634,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133831,7 +134643,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133840,7 +134652,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133849,7 +134661,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133858,7 +134670,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -133867,32 +134679,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub21_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -133903,7 +134724,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -133912,15 +134733,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -133953,7 +134774,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -133970,7 +134791,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -133978,7 +134799,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -133995,13 +134816,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134078,13 +134899,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134092,9 +134913,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134102,21 +134923,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134125,7 +134946,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134134,7 +134955,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134143,7 +134964,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134152,7 +134973,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134161,7 +134982,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134170,32 +134991,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub22_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134206,7 +135036,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134215,15 +135045,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134256,7 +135086,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134273,7 +135103,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134281,7 +135111,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134298,13 +135128,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134381,13 +135211,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134395,9 +135225,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134405,21 +135235,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134428,7 +135258,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134437,7 +135267,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134446,7 +135276,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134455,7 +135285,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134464,7 +135294,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134473,32 +135303,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub23_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134509,7 +135348,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134518,15 +135357,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134559,7 +135398,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134576,7 +135415,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134584,7 +135423,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134601,13 +135440,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134684,13 +135523,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -134698,9 +135537,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -134708,21 +135547,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134731,7 +135570,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134740,7 +135579,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134749,7 +135588,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134758,7 +135597,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134767,7 +135606,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -134776,32 +135615,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub24_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -134812,7 +135660,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -134821,15 +135669,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -134862,7 +135710,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -134879,7 +135727,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -134887,7 +135735,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -134904,13 +135752,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -134987,13 +135835,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135001,9 +135849,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135011,21 +135859,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135034,7 +135882,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135043,7 +135891,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135052,7 +135900,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135061,7 +135909,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135070,7 +135918,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135079,32 +135927,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub26_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135115,7 +135972,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135124,15 +135981,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135165,7 +136022,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135182,7 +136039,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135190,7 +136047,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135207,13 +136064,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135290,13 +136147,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135304,9 +136161,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135314,21 +136171,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135337,7 +136194,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135346,7 +136203,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135355,7 +136212,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135364,7 +136221,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135373,7 +136230,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135382,32 +136239,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub27_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135418,7 +136284,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135427,15 +136293,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135468,7 +136334,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135485,7 +136351,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135493,7 +136359,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135510,13 +136376,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135593,13 +136459,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135607,9 +136473,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135617,21 +136483,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135640,7 +136506,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135649,7 +136515,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135658,7 +136524,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135667,7 +136533,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135676,7 +136542,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135685,32 +136551,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub28_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135721,7 +136596,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135730,15 +136605,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135771,7 +136646,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -135788,7 +136663,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub4_dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135796,7 +136671,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135813,13 +136688,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135896,13 +136771,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135910,9 +136785,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -135920,21 +136795,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135943,7 +136818,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135952,7 +136827,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135961,7 +136836,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135970,7 +136845,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135979,7 +136854,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -135988,32 +136863,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub4_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -136024,7 +136908,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -136033,15 +136917,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136074,7 +136958,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136091,7 +136975,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136099,7 +136983,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136116,13 +137000,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136199,13 +137083,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -136213,9 +137097,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -136223,21 +137107,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136246,7 +137130,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136255,7 +137139,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136264,7 +137148,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136273,7 +137157,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136282,7 +137166,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136291,32 +137175,41 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub8_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -136327,7 +137220,7 @@ module \dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -136336,15 +137229,15 @@ module \dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136377,7 +137270,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136394,7 +137287,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136402,7 +137295,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136419,13 +137312,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136502,13 +137395,13 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -136516,9 +137409,9 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" @@ -136526,21 +137419,21 @@ module \dec31 attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136549,7 +137442,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136558,7 +137451,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136567,7 +137460,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136576,7 +137469,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136585,7 +137478,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136594,16 +137487,25 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub9_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -136636,7 +137538,7 @@ module \dec31 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -136653,7 +137555,7 @@ module \dec31 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -136661,7 +137563,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -136678,13 +137580,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -136761,46 +137663,46 @@ module \dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136808,8 +137710,8 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136817,8 +137719,8 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -136826,7 +137728,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136835,7 +137737,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136844,7 +137746,7 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -136853,25 +137755,34 @@ module \dec31 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_upd - attribute \src "libresoc.v:81382.7-81382.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_upd + attribute \src "libresoc.v:81828.7-81828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:87176.18-87210.4" + attribute \src "libresoc.v:87794.18-87829.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -136904,11 +137815,12 @@ module \dec31 connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out + connect \dec31_dec_sub0_sv_out2 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87211.19-87245.4" + attribute \src "libresoc.v:87830.19-87865.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -136941,11 +137853,12 @@ module \dec31 connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out + connect \dec31_dec_sub10_sv_out2 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87246.19-87280.4" + attribute \src "libresoc.v:87866.19-87901.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -136978,11 +137891,12 @@ module \dec31 connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out + connect \dec31_dec_sub11_sv_out2 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87281.19-87315.4" + attribute \src "libresoc.v:87902.19-87937.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -137015,11 +137929,12 @@ module \dec31 connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out + connect \dec31_dec_sub15_sv_out2 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87316.19-87350.4" + attribute \src "libresoc.v:87938.19-87973.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -137052,11 +137967,12 @@ module \dec31 connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out + connect \dec31_dec_sub16_sv_out2 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87351.19-87385.4" + attribute \src "libresoc.v:87974.19-88009.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -137089,11 +138005,12 @@ module \dec31 connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out + connect \dec31_dec_sub18_sv_out2 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87386.19-87420.4" + attribute \src "libresoc.v:88010.19-88045.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -137126,11 +138043,12 @@ module \dec31 connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out + connect \dec31_dec_sub19_sv_out2 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87421.19-87455.4" + attribute \src "libresoc.v:88046.19-88081.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -137163,11 +138081,12 @@ module \dec31 connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out + connect \dec31_dec_sub20_sv_out2 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87456.19-87490.4" + attribute \src "libresoc.v:88082.19-88117.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -137200,11 +138119,12 @@ module \dec31 connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out + connect \dec31_dec_sub21_sv_out2 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87491.19-87525.4" + attribute \src "libresoc.v:88118.19-88153.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -137237,11 +138157,12 @@ module \dec31 connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out + connect \dec31_dec_sub22_sv_out2 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87526.19-87560.4" + attribute \src "libresoc.v:88154.19-88189.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -137274,11 +138195,12 @@ module \dec31 connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out + connect \dec31_dec_sub23_sv_out2 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87561.19-87595.4" + attribute \src "libresoc.v:88190.19-88225.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -137311,11 +138233,12 @@ module \dec31 connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out + connect \dec31_dec_sub24_sv_out2 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87596.19-87630.4" + attribute \src "libresoc.v:88226.19-88261.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -137348,11 +138271,12 @@ module \dec31 connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out + connect \dec31_dec_sub26_sv_out2 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87631.19-87665.4" + attribute \src "libresoc.v:88262.19-88297.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -137385,11 +138309,12 @@ module \dec31 connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out + connect \dec31_dec_sub27_sv_out2 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87666.19-87700.4" + attribute \src "libresoc.v:88298.19-88333.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -137422,11 +138347,12 @@ module \dec31 connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out + connect \dec31_dec_sub28_sv_out2 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87701.18-87735.4" + attribute \src "libresoc.v:88334.18-88369.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -137459,11 +138385,12 @@ module \dec31 connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out + connect \dec31_dec_sub4_sv_out2 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87736.18-87770.4" + attribute \src "libresoc.v:88370.18-88405.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -137496,11 +138423,12 @@ module \dec31 connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out + connect \dec31_dec_sub8_sv_out2 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87771.18-87805.4" + attribute \src "libresoc.v:88406.18-88441.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -137533,29 +138461,30 @@ module \dec31 connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out + connect \dec31_dec_sub9_sv_out2 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:81382.7-81382.20" - process $proc$libresoc.v:81382$3829 + attribute \src "libresoc.v:81828.7-81828.20" + process $proc$libresoc.v:81828$3850 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:87806.3-87866.6" - process $proc$libresoc.v:87806$3797 + attribute \src "libresoc.v:88442.3-88502.6" + process $proc$libresoc.v:88442$3817 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:87807.5-87807.29" + attribute \src "libresoc.v:88443.5-88443.29" switch \initial - attribute \src "libresoc.v:87807.9-87807.17" + attribute \src "libresoc.v:88443.9-88443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137635,18 +138564,18 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:87867.3-87927.6" - process $proc$libresoc.v:87867$3798 + attribute \src "libresoc.v:88503.3-88563.6" + process $proc$libresoc.v:88503$3818 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:87868.5-87868.29" + attribute \src "libresoc.v:88504.5-88504.29" switch \initial - attribute \src "libresoc.v:87868.9-87868.17" + attribute \src "libresoc.v:88504.9-88504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137726,18 +138655,18 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:87928.3-87988.6" - process $proc$libresoc.v:87928$3799 + attribute \src "libresoc.v:88564.3-88624.6" + process $proc$libresoc.v:88564$3819 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:87929.5-87929.29" + attribute \src "libresoc.v:88565.5-88565.29" switch \initial - attribute \src "libresoc.v:87929.9-87929.17" + attribute \src "libresoc.v:88565.9-88565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137817,18 +138746,18 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:87989.3-88049.6" - process $proc$libresoc.v:87989$3800 + attribute \src "libresoc.v:88625.3-88685.6" + process $proc$libresoc.v:88625$3820 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:87990.5-87990.29" + attribute \src "libresoc.v:88626.5-88626.29" switch \initial - attribute \src "libresoc.v:87990.9-87990.17" + attribute \src "libresoc.v:88626.9-88626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137908,18 +138837,18 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:88050.3-88110.6" - process $proc$libresoc.v:88050$3801 + attribute \src "libresoc.v:88686.3-88746.6" + process $proc$libresoc.v:88686$3821 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88051.5-88051.29" + attribute \src "libresoc.v:88687.5-88687.29" switch \initial - attribute \src "libresoc.v:88051.9-88051.17" + attribute \src "libresoc.v:88687.9-88687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -137999,18 +138928,18 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:88111.3-88171.6" - process $proc$libresoc.v:88111$3802 + attribute \src "libresoc.v:88747.3-88807.6" + process $proc$libresoc.v:88747$3822 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88112.5-88112.29" + attribute \src "libresoc.v:88748.5-88748.29" switch \initial - attribute \src "libresoc.v:88112.9-88112.17" + attribute \src "libresoc.v:88748.9-88748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138090,18 +139019,18 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:88172.3-88232.6" - process $proc$libresoc.v:88172$3803 + attribute \src "libresoc.v:88808.3-88868.6" + process $proc$libresoc.v:88808$3823 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88173.5-88173.29" + attribute \src "libresoc.v:88809.5-88809.29" switch \initial - attribute \src "libresoc.v:88173.9-88173.17" + attribute \src "libresoc.v:88809.9-88809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138181,18 +139110,18 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:88233.3-88293.6" - process $proc$libresoc.v:88233$3804 + attribute \src "libresoc.v:88869.3-88929.6" + process $proc$libresoc.v:88869$3824 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88234.5-88234.29" + attribute \src "libresoc.v:88870.5-88870.29" switch \initial - attribute \src "libresoc.v:88234.9-88234.17" + attribute \src "libresoc.v:88870.9-88870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138272,18 +139201,18 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:88294.3-88354.6" - process $proc$libresoc.v:88294$3805 + attribute \src "libresoc.v:88930.3-88990.6" + process $proc$libresoc.v:88930$3825 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88295.5-88295.29" + attribute \src "libresoc.v:88931.5-88931.29" switch \initial - attribute \src "libresoc.v:88295.9-88295.17" + attribute \src "libresoc.v:88931.9-88931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138363,18 +139292,18 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:88355.3-88415.6" - process $proc$libresoc.v:88355$3806 + attribute \src "libresoc.v:88991.3-89051.6" + process $proc$libresoc.v:88991$3826 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:88356.5-88356.29" + attribute \src "libresoc.v:88992.5-88992.29" switch \initial - attribute \src "libresoc.v:88356.9-88356.17" + attribute \src "libresoc.v:88992.9-88992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138454,18 +139383,18 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:88416.3-88476.6" - process $proc$libresoc.v:88416$3807 + attribute \src "libresoc.v:89052.3-89112.6" + process $proc$libresoc.v:89052$3827 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:88417.5-88417.29" + attribute \src "libresoc.v:89053.5-89053.29" switch \initial - attribute \src "libresoc.v:88417.9-88417.17" + attribute \src "libresoc.v:89053.9-89053.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138545,18 +139474,18 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:88477.3-88537.6" - process $proc$libresoc.v:88477$3808 + attribute \src "libresoc.v:89113.3-89173.6" + process $proc$libresoc.v:89113$3828 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:88478.5-88478.29" + attribute \src "libresoc.v:89114.5-89114.29" switch \initial - attribute \src "libresoc.v:88478.9-88478.17" + attribute \src "libresoc.v:89114.9-89114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138636,18 +139565,18 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:88538.3-88598.6" - process $proc$libresoc.v:88538$3809 + attribute \src "libresoc.v:89174.3-89234.6" + process $proc$libresoc.v:89174$3829 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:88539.5-88539.29" + attribute \src "libresoc.v:89175.5-89175.29" switch \initial - attribute \src "libresoc.v:88539.9-88539.17" + attribute \src "libresoc.v:89175.9-89175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138727,18 +139656,18 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:88599.3-88659.6" - process $proc$libresoc.v:88599$3810 + attribute \src "libresoc.v:89235.3-89295.6" + process $proc$libresoc.v:89235$3830 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:88600.5-88600.29" + attribute \src "libresoc.v:89236.5-89236.29" switch \initial - attribute \src "libresoc.v:88600.9-88600.17" + attribute \src "libresoc.v:89236.9-89236.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138818,18 +139747,18 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:88660.3-88720.6" - process $proc$libresoc.v:88660$3811 + attribute \src "libresoc.v:89296.3-89356.6" + process $proc$libresoc.v:89296$3831 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88661.5-88661.29" + attribute \src "libresoc.v:89297.5-89297.29" switch \initial - attribute \src "libresoc.v:88661.9-88661.17" + attribute \src "libresoc.v:89297.9-89297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -138909,18 +139838,18 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:88721.3-88781.6" - process $proc$libresoc.v:88721$3812 + attribute \src "libresoc.v:89357.3-89417.6" + process $proc$libresoc.v:89357$3832 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88722.5-88722.29" + attribute \src "libresoc.v:89358.5-89358.29" switch \initial - attribute \src "libresoc.v:88722.9-88722.17" + attribute \src "libresoc.v:89358.9-89358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139000,18 +139929,109 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:88782.3-88842.6" - process $proc$libresoc.v:88782$3813 + attribute \src "libresoc.v:89418.3-89478.6" + process $proc$libresoc.v:89418$3833 + assign { } { } + assign { } { } + assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] + attribute \src "libresoc.v:89419.5-89419.29" + switch \initial + attribute \src "libresoc.v:89419.9-89419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out2 + case + assign $1\dec31_sv_out2[2:0] 3'000 + end + sync always + update \dec31_sv_out2 $0\dec31_sv_out2[2:0] + end + attribute \src "libresoc.v:89479.3-89539.6" + process $proc$libresoc.v:89479$3834 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88783.5-88783.29" + attribute \src "libresoc.v:89480.5-89480.29" switch \initial - attribute \src "libresoc.v:88783.9-88783.17" + attribute \src "libresoc.v:89480.9-89480.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139091,18 +140111,18 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:88843.3-88903.6" - process $proc$libresoc.v:88843$3814 + attribute \src "libresoc.v:89540.3-89600.6" + process $proc$libresoc.v:89540$3835 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88844.5-88844.29" + attribute \src "libresoc.v:89541.5-89541.29" switch \initial - attribute \src "libresoc.v:88844.9-88844.17" + attribute \src "libresoc.v:89541.9-89541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139182,18 +140202,18 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:88904.3-88964.6" - process $proc$libresoc.v:88904$3815 + attribute \src "libresoc.v:89601.3-89661.6" + process $proc$libresoc.v:89601$3836 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88905.5-88905.29" + attribute \src "libresoc.v:89602.5-89602.29" switch \initial - attribute \src "libresoc.v:88905.9-88905.17" + attribute \src "libresoc.v:89602.9-89602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139273,18 +140293,18 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:88965.3-89025.6" - process $proc$libresoc.v:88965$3816 + attribute \src "libresoc.v:89662.3-89722.6" + process $proc$libresoc.v:89662$3837 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:88966.5-88966.29" + attribute \src "libresoc.v:89663.5-89663.29" switch \initial - attribute \src "libresoc.v:88966.9-88966.17" + attribute \src "libresoc.v:89663.9-89663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139364,18 +140384,18 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:89026.3-89086.6" - process $proc$libresoc.v:89026$3817 + attribute \src "libresoc.v:89723.3-89783.6" + process $proc$libresoc.v:89723$3838 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89027.5-89027.29" + attribute \src "libresoc.v:89724.5-89724.29" switch \initial - attribute \src "libresoc.v:89027.9-89027.17" + attribute \src "libresoc.v:89724.9-89724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139455,18 +140475,18 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:89087.3-89147.6" - process $proc$libresoc.v:89087$3818 + attribute \src "libresoc.v:89784.3-89844.6" + process $proc$libresoc.v:89784$3839 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89088.5-89088.29" + attribute \src "libresoc.v:89785.5-89785.29" switch \initial - attribute \src "libresoc.v:89088.9-89088.17" + attribute \src "libresoc.v:89785.9-89785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139546,18 +140566,18 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:89148.3-89208.6" - process $proc$libresoc.v:89148$3819 + attribute \src "libresoc.v:89845.3-89905.6" + process $proc$libresoc.v:89845$3840 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89149.5-89149.29" + attribute \src "libresoc.v:89846.5-89846.29" switch \initial - attribute \src "libresoc.v:89149.9-89149.17" + attribute \src "libresoc.v:89846.9-89846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139637,18 +140657,18 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:89209.3-89269.6" - process $proc$libresoc.v:89209$3820 + attribute \src "libresoc.v:89906.3-89966.6" + process $proc$libresoc.v:89906$3841 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89210.5-89210.29" + attribute \src "libresoc.v:89907.5-89907.29" switch \initial - attribute \src "libresoc.v:89210.9-89210.17" + attribute \src "libresoc.v:89907.9-89907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139728,18 +140748,18 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:89270.3-89330.6" - process $proc$libresoc.v:89270$3821 + attribute \src "libresoc.v:89967.3-90027.6" + process $proc$libresoc.v:89967$3842 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:89271.5-89271.29" + attribute \src "libresoc.v:89968.5-89968.29" switch \initial - attribute \src "libresoc.v:89271.9-89271.17" + attribute \src "libresoc.v:89968.9-89968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139819,18 +140839,18 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:89331.3-89391.6" - process $proc$libresoc.v:89331$3822 + attribute \src "libresoc.v:90028.3-90088.6" + process $proc$libresoc.v:90028$3843 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:89332.5-89332.29" + attribute \src "libresoc.v:90029.5-90029.29" switch \initial - attribute \src "libresoc.v:89332.9-89332.17" + attribute \src "libresoc.v:90029.9-90029.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -139910,18 +140930,18 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:89392.3-89452.6" - process $proc$libresoc.v:89392$3823 + attribute \src "libresoc.v:90089.3-90149.6" + process $proc$libresoc.v:90089$3844 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89393.5-89393.29" + attribute \src "libresoc.v:90090.5-90090.29" switch \initial - attribute \src "libresoc.v:89393.9-89393.17" + attribute \src "libresoc.v:90090.9-90090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140001,18 +141021,18 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:89453.3-89513.6" - process $proc$libresoc.v:89453$3824 + attribute \src "libresoc.v:90150.3-90210.6" + process $proc$libresoc.v:90150$3845 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:89454.5-89454.29" + attribute \src "libresoc.v:90151.5-90151.29" switch \initial - attribute \src "libresoc.v:89454.9-89454.17" + attribute \src "libresoc.v:90151.9-90151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140092,18 +141112,18 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:89514.3-89574.6" - process $proc$libresoc.v:89514$3825 + attribute \src "libresoc.v:90211.3-90271.6" + process $proc$libresoc.v:90211$3846 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:89515.5-89515.29" + attribute \src "libresoc.v:90212.5-90212.29" switch \initial - attribute \src "libresoc.v:89515.9-89515.17" + attribute \src "libresoc.v:90212.9-90212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140183,18 +141203,18 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:89575.3-89635.6" - process $proc$libresoc.v:89575$3826 + attribute \src "libresoc.v:90272.3-90332.6" + process $proc$libresoc.v:90272$3847 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:89576.5-89576.29" + attribute \src "libresoc.v:90273.5-90273.29" switch \initial - attribute \src "libresoc.v:89576.9-89576.17" + attribute \src "libresoc.v:90273.9-90273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140274,18 +141294,18 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:89636.3-89696.6" - process $proc$libresoc.v:89636$3827 + attribute \src "libresoc.v:90333.3-90393.6" + process $proc$libresoc.v:90333$3848 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:89637.5-89637.29" + attribute \src "libresoc.v:90334.5-90334.29" switch \initial - attribute \src "libresoc.v:89637.9-89637.17" + attribute \src "libresoc.v:90334.9-90334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140365,18 +141385,18 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:89697.3-89757.6" - process $proc$libresoc.v:89697$3828 + attribute \src "libresoc.v:90394.3-90454.6" + process $proc$libresoc.v:90394$3849 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89698.5-89698.29" + attribute \src "libresoc.v:90395.5-90395.29" switch \initial - attribute \src "libresoc.v:89698.9-89698.17" + attribute \src "libresoc.v:90395.9-90395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -140477,157 +141497,161 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:89782.1-90730.10" +attribute \src "libresoc.v:90479.1-91456.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:90615.3-90633.6" + attribute \src "libresoc.v:91341.3-91359.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90634.3-90652.6" + attribute \src "libresoc.v:91360.3-91378.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91113.3-91131.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91189.3-91207.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:90847.3-90865.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:90866.3-90884.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91094.3-91112.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91170.3-91188.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91246.3-91264.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90828.3-90846.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90653.3-90671.6" + attribute \src "libresoc.v:91379.3-91397.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90672.3-90690.6" + attribute \src "libresoc.v:91398.3-91416.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90691.3-90709.6" + attribute \src "libresoc.v:91417.3-91435.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91037.3-91055.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91132.3-91150.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91151.3-91169.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91265.3-91283.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91018.3-91036.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90577.3-90595.6" + attribute \src "libresoc.v:91303.3-91321.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90710.3-90728.6" + attribute \src "libresoc.v:91436.3-91454.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91075.3-91093.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91227.3-91245.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90596.3-90614.6" + attribute \src "libresoc.v:91322.3-91340.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90558.3-90576.6" + attribute \src "libresoc.v:91284.3-91302.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91208.3-91226.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:90980.3-90998.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:90999.3-91017.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:90885.3-90903.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:90904.3-90922.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:90923.3-90941.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91056.3-91074.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:89783.7-89783.20" + attribute \src "libresoc.v:90480.7-90480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90615.3-90633.6" + attribute \src "libresoc.v:91341.3-91359.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90634.3-90652.6" + attribute \src "libresoc.v:91360.3-91378.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91113.3-91131.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91189.3-91207.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:90847.3-90865.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:90866.3-90884.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91094.3-91112.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91170.3-91188.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91246.3-91264.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90828.3-90846.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90653.3-90671.6" + attribute \src "libresoc.v:91379.3-91397.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90672.3-90690.6" + attribute \src "libresoc.v:91398.3-91416.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90691.3-90709.6" + attribute \src "libresoc.v:91417.3-91435.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91037.3-91055.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91132.3-91150.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91151.3-91169.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91265.3-91283.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91018.3-91036.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90577.3-90595.6" + attribute \src "libresoc.v:91303.3-91321.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90710.3-90728.6" + attribute \src "libresoc.v:91436.3-91454.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91075.3-91093.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91227.3-91245.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90596.3-90614.6" + attribute \src "libresoc.v:91322.3-91340.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90558.3-90576.6" + attribute \src "libresoc.v:91284.3-91302.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91208.3-91226.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:90980.3-90998.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:90999.3-91017.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:90885.3-90903.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:90904.3-90922.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:90923.3-90941.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:90961.3-90979.6" + wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90942.3-90960.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91056.3-91074.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub0_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub0_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -140637,7 +141661,7 @@ module \dec31_dec_sub0 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -140646,16 +141670,16 @@ module \dec31_dec_sub0 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub0_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -140687,7 +141711,7 @@ module \dec31_dec_sub0 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -140704,7 +141728,7 @@ module \dec31_dec_sub0 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -140712,7 +141736,7 @@ module \dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -140729,13 +141753,13 @@ module \dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -140812,46 +141836,46 @@ module \dec31_dec_sub0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub0_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub0_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub0_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub0_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140859,8 +141883,8 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub0_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub0_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140868,8 +141892,8 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub0_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub0_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -140877,7 +141901,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub0_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140886,7 +141910,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub0_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140895,7 +141919,7 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub0_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -140904,41 +141928,50 @@ module \dec31_dec_sub0 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub0_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub0_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub0_upd - attribute \src "libresoc.v:89783.7-89783.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub0_upd + attribute \src "libresoc.v:90480.7-90480.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:89783.7-89783.20" - process $proc$libresoc.v:89783$3862 + attribute \src "libresoc.v:90480.7-90480.20" + process $proc$libresoc.v:90480$3884 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90121.3-90139.6" - process $proc$libresoc.v:90121$3830 + attribute \src "libresoc.v:90828.3-90846.6" + process $proc$libresoc.v:90828$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90122.5-90122.29" + attribute \src "libresoc.v:90829.5-90829.29" switch \initial - attribute \src "libresoc.v:90122.9-90122.17" + attribute \src "libresoc.v:90829.9-90829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -140962,18 +141995,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:90140.3-90158.6" - process $proc$libresoc.v:90140$3831 + attribute \src "libresoc.v:90847.3-90865.6" + process $proc$libresoc.v:90847$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90141.5-90141.29" + attribute \src "libresoc.v:90848.5-90848.29" switch \initial - attribute \src "libresoc.v:90141.9-90141.17" + attribute \src "libresoc.v:90848.9-90848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -140997,18 +142030,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:90159.3-90177.6" - process $proc$libresoc.v:90159$3832 + attribute \src "libresoc.v:90866.3-90884.6" + process $proc$libresoc.v:90866$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90160.5-90160.29" + attribute \src "libresoc.v:90867.5-90867.29" switch \initial - attribute \src "libresoc.v:90160.9-90160.17" + attribute \src "libresoc.v:90867.9-90867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141032,18 +142065,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:90178.3-90196.6" - process $proc$libresoc.v:90178$3833 + attribute \src "libresoc.v:90885.3-90903.6" + process $proc$libresoc.v:90885$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90179.5-90179.29" + attribute \src "libresoc.v:90886.5-90886.29" switch \initial - attribute \src "libresoc.v:90179.9-90179.17" + attribute \src "libresoc.v:90886.9-90886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141067,18 +142100,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:90197.3-90215.6" - process $proc$libresoc.v:90197$3834 + attribute \src "libresoc.v:90904.3-90922.6" + process $proc$libresoc.v:90904$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90198.5-90198.29" + attribute \src "libresoc.v:90905.5-90905.29" switch \initial - attribute \src "libresoc.v:90198.9-90198.17" + attribute \src "libresoc.v:90905.9-90905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141102,18 +142135,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:90216.3-90234.6" - process $proc$libresoc.v:90216$3835 + attribute \src "libresoc.v:90923.3-90941.6" + process $proc$libresoc.v:90923$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90217.5-90217.29" + attribute \src "libresoc.v:90924.5-90924.29" switch \initial - attribute \src "libresoc.v:90217.9-90217.17" + attribute \src "libresoc.v:90924.9-90924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141137,18 +142170,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:90235.3-90253.6" - process $proc$libresoc.v:90235$3836 + attribute \src "libresoc.v:90942.3-90960.6" + process $proc$libresoc.v:90942$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90236.5-90236.29" + attribute \src "libresoc.v:90943.5-90943.29" switch \initial - attribute \src "libresoc.v:90236.9-90236.17" + attribute \src "libresoc.v:90943.9-90943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141172,18 +142205,53 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:90254.3-90272.6" - process $proc$libresoc.v:90254$3837 + attribute \src "libresoc.v:90961.3-90979.6" + process $proc$libresoc.v:90961$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] + attribute \src "libresoc.v:90962.5-90962.29" + switch \initial + attribute \src "libresoc.v:90962.9-90962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] + end + attribute \src "libresoc.v:90980.3-90998.6" + process $proc$libresoc.v:90980$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90255.5-90255.29" + attribute \src "libresoc.v:90981.5-90981.29" switch \initial - attribute \src "libresoc.v:90255.9-90255.17" + attribute \src "libresoc.v:90981.9-90981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141207,18 +142275,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:90273.3-90291.6" - process $proc$libresoc.v:90273$3838 + attribute \src "libresoc.v:90999.3-91017.6" + process $proc$libresoc.v:90999$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90274.5-90274.29" + attribute \src "libresoc.v:91000.5-91000.29" switch \initial - attribute \src "libresoc.v:90274.9-90274.17" + attribute \src "libresoc.v:91000.9-91000.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141242,18 +142310,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:90292.3-90310.6" - process $proc$libresoc.v:90292$3839 + attribute \src "libresoc.v:91018.3-91036.6" + process $proc$libresoc.v:91018$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:90293.5-90293.29" + attribute \src "libresoc.v:91019.5-91019.29" switch \initial - attribute \src "libresoc.v:90293.9-90293.17" + attribute \src "libresoc.v:91019.9-91019.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141277,88 +142345,88 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:90311.3-90329.6" - process $proc$libresoc.v:90311$3840 + attribute \src "libresoc.v:91037.3-91055.6" + process $proc$libresoc.v:91037$3862 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90312.5-90312.29" + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:91038.5-91038.29" switch \initial - attribute \src "libresoc.v:90312.9-90312.17" + attribute \src "libresoc.v:91038.9-91038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 case - assign $1\dec31_dec_sub0_upd[1:0] 2'00 + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:90330.3-90348.6" - process $proc$libresoc.v:90330$3841 + attribute \src "libresoc.v:91056.3-91074.6" + process $proc$libresoc.v:91056$3863 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:90331.5-90331.29" + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:91057.5-91057.29" switch \initial - attribute \src "libresoc.v:90331.9-90331.17" + attribute \src "libresoc.v:91057.9-91057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub0_upd[1:0] 2'00 end sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:90349.3-90367.6" - process $proc$libresoc.v:90349$3842 + attribute \src "libresoc.v:91075.3-91093.6" + process $proc$libresoc.v:91075$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:90350.5-90350.29" + attribute \src "libresoc.v:91076.5-91076.29" switch \initial - attribute \src "libresoc.v:90350.9-90350.17" + attribute \src "libresoc.v:91076.9-91076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141382,18 +142450,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:90368.3-90386.6" - process $proc$libresoc.v:90368$3843 + attribute \src "libresoc.v:91094.3-91112.6" + process $proc$libresoc.v:91094$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:90369.5-90369.29" + attribute \src "libresoc.v:91095.5-91095.29" switch \initial - attribute \src "libresoc.v:90369.9-90369.17" + attribute \src "libresoc.v:91095.9-91095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141417,18 +142485,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:90387.3-90405.6" - process $proc$libresoc.v:90387$3844 + attribute \src "libresoc.v:91113.3-91131.6" + process $proc$libresoc.v:91113$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:90388.5-90388.29" + attribute \src "libresoc.v:91114.5-91114.29" switch \initial - attribute \src "libresoc.v:90388.9-90388.17" + attribute \src "libresoc.v:91114.9-91114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141452,18 +142520,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:90406.3-90424.6" - process $proc$libresoc.v:90406$3845 + attribute \src "libresoc.v:91132.3-91150.6" + process $proc$libresoc.v:91132$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:90407.5-90407.29" + attribute \src "libresoc.v:91133.5-91133.29" switch \initial - attribute \src "libresoc.v:90407.9-90407.17" + attribute \src "libresoc.v:91133.9-91133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141487,18 +142555,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:90425.3-90443.6" - process $proc$libresoc.v:90425$3846 + attribute \src "libresoc.v:91151.3-91169.6" + process $proc$libresoc.v:91151$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:90426.5-90426.29" + attribute \src "libresoc.v:91152.5-91152.29" switch \initial - attribute \src "libresoc.v:90426.9-90426.17" + attribute \src "libresoc.v:91152.9-91152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141522,18 +142590,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:90444.3-90462.6" - process $proc$libresoc.v:90444$3847 + attribute \src "libresoc.v:91170.3-91188.6" + process $proc$libresoc.v:91170$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:90445.5-90445.29" + attribute \src "libresoc.v:91171.5-91171.29" switch \initial - attribute \src "libresoc.v:90445.9-90445.17" + attribute \src "libresoc.v:91171.9-91171.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141557,18 +142625,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:90463.3-90481.6" - process $proc$libresoc.v:90463$3848 + attribute \src "libresoc.v:91189.3-91207.6" + process $proc$libresoc.v:91189$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90464.5-90464.29" + attribute \src "libresoc.v:91190.5-91190.29" switch \initial - attribute \src "libresoc.v:90464.9-90464.17" + attribute \src "libresoc.v:91190.9-91190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141592,18 +142660,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:90482.3-90500.6" - process $proc$libresoc.v:90482$3849 + attribute \src "libresoc.v:91208.3-91226.6" + process $proc$libresoc.v:91208$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90483.5-90483.29" + attribute \src "libresoc.v:91209.5-91209.29" switch \initial - attribute \src "libresoc.v:90483.9-90483.17" + attribute \src "libresoc.v:91209.9-91209.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141627,18 +142695,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:90501.3-90519.6" - process $proc$libresoc.v:90501$3850 + attribute \src "libresoc.v:91227.3-91245.6" + process $proc$libresoc.v:91227$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:90502.5-90502.29" + attribute \src "libresoc.v:91228.5-91228.29" switch \initial - attribute \src "libresoc.v:90502.9-90502.17" + attribute \src "libresoc.v:91228.9-91228.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141662,88 +142730,88 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:90520.3-90538.6" - process $proc$libresoc.v:90520$3851 + attribute \src "libresoc.v:91246.3-91264.6" + process $proc$libresoc.v:91246$3873 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:90521.5-90521.29" + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:91247.5-91247.29" switch \initial - attribute \src "libresoc.v:90521.9-90521.17" + attribute \src "libresoc.v:91247.9-91247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'11000 case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub0_form[4:0] 5'00000 end sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:90539.3-90557.6" - process $proc$libresoc.v:90539$3852 + attribute \src "libresoc.v:91265.3-91283.6" + process $proc$libresoc.v:91265$3874 assign { } { } assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90540.5-90540.29" + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:91266.5-91266.29" switch \initial - attribute \src "libresoc.v:90540.9-90540.17" + attribute \src "libresoc.v:91266.9-91266.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:90558.3-90576.6" - process $proc$libresoc.v:90558$3853 + attribute \src "libresoc.v:91284.3-91302.6" + process $proc$libresoc.v:91284$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:90559.5-90559.29" + attribute \src "libresoc.v:91285.5-91285.29" switch \initial - attribute \src "libresoc.v:90559.9-90559.17" + attribute \src "libresoc.v:91285.9-91285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141767,18 +142835,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:90577.3-90595.6" - process $proc$libresoc.v:90577$3854 + attribute \src "libresoc.v:91303.3-91321.6" + process $proc$libresoc.v:91303$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90578.5-90578.29" + attribute \src "libresoc.v:91304.5-91304.29" switch \initial - attribute \src "libresoc.v:90578.9-90578.17" + attribute \src "libresoc.v:91304.9-91304.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141802,18 +142870,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:90596.3-90614.6" - process $proc$libresoc.v:90596$3855 + attribute \src "libresoc.v:91322.3-91340.6" + process $proc$libresoc.v:91322$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:90597.5-90597.29" + attribute \src "libresoc.v:91323.5-91323.29" switch \initial - attribute \src "libresoc.v:90597.9-90597.17" + attribute \src "libresoc.v:91323.9-91323.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141837,18 +142905,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:90615.3-90633.6" - process $proc$libresoc.v:90615$3856 + attribute \src "libresoc.v:91341.3-91359.6" + process $proc$libresoc.v:91341$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:90616.5-90616.29" + attribute \src "libresoc.v:91342.5-91342.29" switch \initial - attribute \src "libresoc.v:90616.9-90616.17" + attribute \src "libresoc.v:91342.9-91342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141872,18 +142940,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:90634.3-90652.6" - process $proc$libresoc.v:90634$3857 + attribute \src "libresoc.v:91360.3-91378.6" + process $proc$libresoc.v:91360$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:90635.5-90635.29" + attribute \src "libresoc.v:91361.5-91361.29" switch \initial - attribute \src "libresoc.v:90635.9-90635.17" + attribute \src "libresoc.v:91361.9-91361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141907,18 +142975,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:90653.3-90671.6" - process $proc$libresoc.v:90653$3858 + attribute \src "libresoc.v:91379.3-91397.6" + process $proc$libresoc.v:91379$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:90654.5-90654.29" + attribute \src "libresoc.v:91380.5-91380.29" switch \initial - attribute \src "libresoc.v:90654.9-90654.17" + attribute \src "libresoc.v:91380.9-91380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141942,18 +143010,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:90672.3-90690.6" - process $proc$libresoc.v:90672$3859 + attribute \src "libresoc.v:91398.3-91416.6" + process $proc$libresoc.v:91398$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:90673.5-90673.29" + attribute \src "libresoc.v:91399.5-91399.29" switch \initial - attribute \src "libresoc.v:90673.9-90673.17" + attribute \src "libresoc.v:91399.9-91399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141977,18 +143045,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:90691.3-90709.6" - process $proc$libresoc.v:90691$3860 + attribute \src "libresoc.v:91417.3-91435.6" + process $proc$libresoc.v:91417$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:90692.5-90692.29" + attribute \src "libresoc.v:91418.5-91418.29" switch \initial - attribute \src "libresoc.v:90692.9-90692.17" + attribute \src "libresoc.v:91418.9-91418.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142012,18 +143080,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:90710.3-90728.6" - process $proc$libresoc.v:90710$3861 + attribute \src "libresoc.v:91436.3-91454.6" + process $proc$libresoc.v:91436$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:90711.5-90711.29" + attribute \src "libresoc.v:91437.5-91437.29" switch \initial - attribute \src "libresoc.v:90711.9-90711.17" + attribute \src "libresoc.v:91437.9-91437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142049,157 +143117,161 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90734.1-92258.10" +attribute \src "libresoc.v:91460.1-93031.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:92035.3-92071.6" + attribute \src "libresoc.v:92808.3-92844.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92072.3-92108.6" + attribute \src "libresoc.v:92845.3-92881.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:91591.3-91627.6" + attribute \src "libresoc.v:92364.3-92400.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91739.3-91775.6" + attribute \src "libresoc.v:92512.3-92548.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91110.3-91146.6" + attribute \src "libresoc.v:91846.3-91882.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91147.3-91183.6" + attribute \src "libresoc.v:91883.3-91919.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91554.3-91590.6" + attribute \src "libresoc.v:92327.3-92363.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91702.3-91738.6" + attribute \src "libresoc.v:92475.3-92511.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91887.3-91923.6" + attribute \src "libresoc.v:92623.3-92659.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91073.3-91109.6" + attribute \src "libresoc.v:91809.3-91845.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92109.3-92145.6" + attribute \src "libresoc.v:92882.3-92918.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92146.3-92182.6" + attribute \src "libresoc.v:92919.3-92955.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92183.3-92219.6" + attribute \src "libresoc.v:92956.3-92992.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:91480.3-91516.6" + attribute \src "libresoc.v:92216.3-92252.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91628.3-91664.6" + attribute \src "libresoc.v:92401.3-92437.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91665.3-91701.6" + attribute \src "libresoc.v:92438.3-92474.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91850.3-91886.6" + attribute \src "libresoc.v:92660.3-92696.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91406.3-91442.6" + attribute \src "libresoc.v:92179.3-92215.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91961.3-91997.6" + attribute \src "libresoc.v:92734.3-92770.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92220.3-92256.6" + attribute \src "libresoc.v:92993.3-93029.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:91517.3-91553.6" + attribute \src "libresoc.v:92290.3-92326.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91813.3-91849.6" + attribute \src "libresoc.v:92586.3-92622.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91998.3-92034.6" + attribute \src "libresoc.v:92771.3-92807.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91924.3-91960.6" + attribute \src "libresoc.v:92697.3-92733.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91776.3-91812.6" + attribute \src "libresoc.v:92549.3-92585.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91332.3-91368.6" + attribute \src "libresoc.v:92105.3-92141.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91369.3-91405.6" + attribute \src "libresoc.v:92142.3-92178.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91184.3-91220.6" + attribute \src "libresoc.v:91920.3-91956.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91221.3-91257.6" + attribute \src "libresoc.v:91957.3-91993.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91258.3-91294.6" + attribute \src "libresoc.v:91994.3-92030.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91295.3-91331.6" + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91443.3-91479.6" + attribute \src "libresoc.v:92253.3-92289.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:90735.7-90735.20" + attribute \src "libresoc.v:91461.7-91461.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92035.3-92071.6" + attribute \src "libresoc.v:92808.3-92844.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92072.3-92108.6" + attribute \src "libresoc.v:92845.3-92881.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:91591.3-91627.6" + attribute \src "libresoc.v:92364.3-92400.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91739.3-91775.6" + attribute \src "libresoc.v:92512.3-92548.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91110.3-91146.6" + attribute \src "libresoc.v:91846.3-91882.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91147.3-91183.6" + attribute \src "libresoc.v:91883.3-91919.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91554.3-91590.6" + attribute \src "libresoc.v:92327.3-92363.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91702.3-91738.6" + attribute \src "libresoc.v:92475.3-92511.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91887.3-91923.6" + attribute \src "libresoc.v:92623.3-92659.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91073.3-91109.6" + attribute \src "libresoc.v:91809.3-91845.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92109.3-92145.6" + attribute \src "libresoc.v:92882.3-92918.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92146.3-92182.6" + attribute \src "libresoc.v:92919.3-92955.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92183.3-92219.6" + attribute \src "libresoc.v:92956.3-92992.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:91480.3-91516.6" + attribute \src "libresoc.v:92216.3-92252.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91628.3-91664.6" + attribute \src "libresoc.v:92401.3-92437.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91665.3-91701.6" + attribute \src "libresoc.v:92438.3-92474.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91850.3-91886.6" + attribute \src "libresoc.v:92660.3-92696.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91406.3-91442.6" + attribute \src "libresoc.v:92179.3-92215.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91961.3-91997.6" + attribute \src "libresoc.v:92734.3-92770.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92220.3-92256.6" + attribute \src "libresoc.v:92993.3-93029.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:91517.3-91553.6" + attribute \src "libresoc.v:92290.3-92326.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91813.3-91849.6" + attribute \src "libresoc.v:92586.3-92622.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91998.3-92034.6" + attribute \src "libresoc.v:92771.3-92807.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91924.3-91960.6" + attribute \src "libresoc.v:92697.3-92733.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91776.3-91812.6" + attribute \src "libresoc.v:92549.3-92585.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91332.3-91368.6" + attribute \src "libresoc.v:92105.3-92141.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91369.3-91405.6" + attribute \src "libresoc.v:92142.3-92178.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91184.3-91220.6" + attribute \src "libresoc.v:91920.3-91956.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91221.3-91257.6" + attribute \src "libresoc.v:91957.3-91993.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91258.3-91294.6" + attribute \src "libresoc.v:91994.3-92030.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91295.3-91331.6" + attribute \src "libresoc.v:92068.3-92104.6" + wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92031.3-92067.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91443.3-91479.6" + attribute \src "libresoc.v:92253.3-92289.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub10_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub10_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub10_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -142209,7 +143281,7 @@ module \dec31_dec_sub10 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -142218,16 +143290,16 @@ module \dec31_dec_sub10 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub10_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -142259,7 +143331,7 @@ module \dec31_dec_sub10 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -142276,7 +143348,7 @@ module \dec31_dec_sub10 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -142284,7 +143356,7 @@ module \dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -142301,13 +143373,13 @@ module \dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -142384,46 +143456,46 @@ module \dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub10_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub10_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub10_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub10_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142431,8 +143503,8 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub10_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub10_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142440,8 +143512,8 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub10_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub10_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -142449,7 +143521,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub10_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142458,7 +143530,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub10_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142467,7 +143539,7 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub10_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -142476,41 +143548,50 @@ module \dec31_dec_sub10 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub10_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub10_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub10_upd - attribute \src "libresoc.v:90735.7-90735.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub10_upd + attribute \src "libresoc.v:91461.7-91461.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:90735.7-90735.20" - process $proc$libresoc.v:90735$3895 + attribute \src "libresoc.v:91461.7-91461.20" + process $proc$libresoc.v:91461$3918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91073.3-91109.6" - process $proc$libresoc.v:91073$3863 + attribute \src "libresoc.v:91809.3-91845.6" + process $proc$libresoc.v:91809$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:91074.5-91074.29" + attribute \src "libresoc.v:91810.5-91810.29" switch \initial - attribute \src "libresoc.v:91074.9-91074.17" + attribute \src "libresoc.v:91810.9-91810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142558,18 +143639,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:91110.3-91146.6" - process $proc$libresoc.v:91110$3864 + attribute \src "libresoc.v:91846.3-91882.6" + process $proc$libresoc.v:91846$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91111.5-91111.29" + attribute \src "libresoc.v:91847.5-91847.29" switch \initial - attribute \src "libresoc.v:91111.9-91111.17" + attribute \src "libresoc.v:91847.9-91847.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142617,18 +143698,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:91147.3-91183.6" - process $proc$libresoc.v:91147$3865 + attribute \src "libresoc.v:91883.3-91919.6" + process $proc$libresoc.v:91883$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91148.5-91148.29" + attribute \src "libresoc.v:91884.5-91884.29" switch \initial - attribute \src "libresoc.v:91148.9-91148.17" + attribute \src "libresoc.v:91884.9-91884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142676,18 +143757,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:91184.3-91220.6" - process $proc$libresoc.v:91184$3866 + attribute \src "libresoc.v:91920.3-91956.6" + process $proc$libresoc.v:91920$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91185.5-91185.29" + attribute \src "libresoc.v:91921.5-91921.29" switch \initial - attribute \src "libresoc.v:91185.9-91185.17" + attribute \src "libresoc.v:91921.9-91921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142735,18 +143816,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:91221.3-91257.6" - process $proc$libresoc.v:91221$3867 + attribute \src "libresoc.v:91957.3-91993.6" + process $proc$libresoc.v:91957$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91222.5-91222.29" + attribute \src "libresoc.v:91958.5-91958.29" switch \initial - attribute \src "libresoc.v:91222.9-91222.17" + attribute \src "libresoc.v:91958.9-91958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142794,18 +143875,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:91258.3-91294.6" - process $proc$libresoc.v:91258$3868 + attribute \src "libresoc.v:91994.3-92030.6" + process $proc$libresoc.v:91994$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91259.5-91259.29" + attribute \src "libresoc.v:91995.5-91995.29" switch \initial - attribute \src "libresoc.v:91259.9-91259.17" + attribute \src "libresoc.v:91995.9-91995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142853,18 +143934,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:91295.3-91331.6" - process $proc$libresoc.v:91295$3869 + attribute \src "libresoc.v:92031.3-92067.6" + process $proc$libresoc.v:92031$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:91296.5-91296.29" + attribute \src "libresoc.v:92032.5-92032.29" switch \initial - attribute \src "libresoc.v:91296.9-91296.17" + attribute \src "libresoc.v:92032.9-92032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142912,18 +143993,77 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:91332.3-91368.6" - process $proc$libresoc.v:91332$3870 + attribute \src "libresoc.v:92068.3-92104.6" + process $proc$libresoc.v:92068$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] + attribute \src "libresoc.v:92069.5-92069.29" + switch \initial + attribute \src "libresoc.v:92069.9-92069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] + end + attribute \src "libresoc.v:92105.3-92141.6" + process $proc$libresoc.v:92105$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:91333.5-91333.29" + attribute \src "libresoc.v:92106.5-92106.29" switch \initial - attribute \src "libresoc.v:91333.9-91333.17" + attribute \src "libresoc.v:92106.9-92106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -142971,18 +144111,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:91369.3-91405.6" - process $proc$libresoc.v:91369$3871 + attribute \src "libresoc.v:92142.3-92178.6" + process $proc$libresoc.v:92142$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91370.5-91370.29" + attribute \src "libresoc.v:92143.5-92143.29" switch \initial - attribute \src "libresoc.v:91370.9-91370.17" + attribute \src "libresoc.v:92143.9-92143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143030,18 +144170,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:91406.3-91442.6" - process $proc$libresoc.v:91406$3872 + attribute \src "libresoc.v:92179.3-92215.6" + process $proc$libresoc.v:92179$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91407.5-91407.29" + attribute \src "libresoc.v:92180.5-92180.29" switch \initial - attribute \src "libresoc.v:91407.9-91407.17" + attribute \src "libresoc.v:92180.9-92180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143089,136 +144229,136 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:91443.3-91479.6" - process $proc$libresoc.v:91443$3873 + attribute \src "libresoc.v:92216.3-92252.6" + process $proc$libresoc.v:92216$3896 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:91444.5-91444.29" + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:92217.5-92217.29" switch \initial - attribute \src "libresoc.v:91444.9-91444.17" + attribute \src "libresoc.v:92217.9-92217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:91480.3-91516.6" - process $proc$libresoc.v:91480$3874 + attribute \src "libresoc.v:92253.3-92289.6" + process $proc$libresoc.v:92253$3897 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:91481.5-91481.29" + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:92254.5-92254.29" switch \initial - attribute \src "libresoc.v:91481.9-91481.17" + attribute \src "libresoc.v:92254.9-92254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 end sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:91517.3-91553.6" - process $proc$libresoc.v:91517$3875 + attribute \src "libresoc.v:92290.3-92326.6" + process $proc$libresoc.v:92290$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91518.5-91518.29" + attribute \src "libresoc.v:92291.5-92291.29" switch \initial - attribute \src "libresoc.v:91518.9-91518.17" + attribute \src "libresoc.v:92291.9-92291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143266,18 +144406,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:91554.3-91590.6" - process $proc$libresoc.v:91554$3876 + attribute \src "libresoc.v:92327.3-92363.6" + process $proc$libresoc.v:92327$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:91555.5-91555.29" + attribute \src "libresoc.v:92328.5-92328.29" switch \initial - attribute \src "libresoc.v:91555.9-91555.17" + attribute \src "libresoc.v:92328.9-92328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143325,18 +144465,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:91591.3-91627.6" - process $proc$libresoc.v:91591$3877 + attribute \src "libresoc.v:92364.3-92400.6" + process $proc$libresoc.v:92364$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91592.5-91592.29" + attribute \src "libresoc.v:92365.5-92365.29" switch \initial - attribute \src "libresoc.v:91592.9-91592.17" + attribute \src "libresoc.v:92365.9-92365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143384,18 +144524,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:91628.3-91664.6" - process $proc$libresoc.v:91628$3878 + attribute \src "libresoc.v:92401.3-92437.6" + process $proc$libresoc.v:92401$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:91629.5-91629.29" + attribute \src "libresoc.v:92402.5-92402.29" switch \initial - attribute \src "libresoc.v:91629.9-91629.17" + attribute \src "libresoc.v:92402.9-92402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143443,18 +144583,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:91665.3-91701.6" - process $proc$libresoc.v:91665$3879 + attribute \src "libresoc.v:92438.3-92474.6" + process $proc$libresoc.v:92438$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91666.5-91666.29" + attribute \src "libresoc.v:92439.5-92439.29" switch \initial - attribute \src "libresoc.v:91666.9-91666.17" + attribute \src "libresoc.v:92439.9-92439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143502,18 +144642,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:91702.3-91738.6" - process $proc$libresoc.v:91702$3880 + attribute \src "libresoc.v:92475.3-92511.6" + process $proc$libresoc.v:92475$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91703.5-91703.29" + attribute \src "libresoc.v:92476.5-92476.29" switch \initial - attribute \src "libresoc.v:91703.9-91703.17" + attribute \src "libresoc.v:92476.9-92476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143561,18 +144701,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:91739.3-91775.6" - process $proc$libresoc.v:91739$3881 + attribute \src "libresoc.v:92512.3-92548.6" + process $proc$libresoc.v:92512$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91740.5-91740.29" + attribute \src "libresoc.v:92513.5-92513.29" switch \initial - attribute \src "libresoc.v:91740.9-91740.17" + attribute \src "libresoc.v:92513.9-92513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143620,18 +144760,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:91776.3-91812.6" - process $proc$libresoc.v:91776$3882 + attribute \src "libresoc.v:92549.3-92585.6" + process $proc$libresoc.v:92549$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91777.5-91777.29" + attribute \src "libresoc.v:92550.5-92550.29" switch \initial - attribute \src "libresoc.v:91777.9-91777.17" + attribute \src "libresoc.v:92550.9-92550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143679,18 +144819,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:91813.3-91849.6" - process $proc$libresoc.v:91813$3883 + attribute \src "libresoc.v:92586.3-92622.6" + process $proc$libresoc.v:92586$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91814.5-91814.29" + attribute \src "libresoc.v:92587.5-92587.29" switch \initial - attribute \src "libresoc.v:91814.9-91814.17" + attribute \src "libresoc.v:92587.9-92587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143738,136 +144878,136 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:91850.3-91886.6" - process $proc$libresoc.v:91850$3884 + attribute \src "libresoc.v:92623.3-92659.6" + process $proc$libresoc.v:92623$3907 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91851.5-91851.29" + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:92624.5-92624.29" switch \initial - attribute \src "libresoc.v:91851.9-91851.17" + attribute \src "libresoc.v:92624.9-92624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'10001 case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub10_form[4:0] 5'00000 end sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:91887.3-91923.6" - process $proc$libresoc.v:91887$3885 + attribute \src "libresoc.v:92660.3-92696.6" + process $proc$libresoc.v:92660$3908 assign { } { } assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91888.5-91888.29" + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:92661.5-92661.29" switch \initial - attribute \src "libresoc.v:91888.9-91888.17" + attribute \src "libresoc.v:92661.9-92661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:91924.3-91960.6" - process $proc$libresoc.v:91924$3886 + attribute \src "libresoc.v:92697.3-92733.6" + process $proc$libresoc.v:92697$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91925.5-91925.29" + attribute \src "libresoc.v:92698.5-92698.29" switch \initial - attribute \src "libresoc.v:91925.9-91925.17" + attribute \src "libresoc.v:92698.9-92698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143915,18 +145055,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:91961.3-91997.6" - process $proc$libresoc.v:91961$3887 + attribute \src "libresoc.v:92734.3-92770.6" + process $proc$libresoc.v:92734$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:91962.5-91962.29" + attribute \src "libresoc.v:92735.5-92735.29" switch \initial - attribute \src "libresoc.v:91962.9-91962.17" + attribute \src "libresoc.v:92735.9-92735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -143974,18 +145114,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:91998.3-92034.6" - process $proc$libresoc.v:91998$3888 + attribute \src "libresoc.v:92771.3-92807.6" + process $proc$libresoc.v:92771$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91999.5-91999.29" + attribute \src "libresoc.v:92772.5-92772.29" switch \initial - attribute \src "libresoc.v:91999.9-91999.17" + attribute \src "libresoc.v:92772.9-92772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144033,18 +145173,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:92035.3-92071.6" - process $proc$libresoc.v:92035$3889 + attribute \src "libresoc.v:92808.3-92844.6" + process $proc$libresoc.v:92808$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92036.5-92036.29" + attribute \src "libresoc.v:92809.5-92809.29" switch \initial - attribute \src "libresoc.v:92036.9-92036.17" + attribute \src "libresoc.v:92809.9-92809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144092,18 +145232,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:92072.3-92108.6" - process $proc$libresoc.v:92072$3890 + attribute \src "libresoc.v:92845.3-92881.6" + process $proc$libresoc.v:92845$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92073.5-92073.29" + attribute \src "libresoc.v:92846.5-92846.29" switch \initial - attribute \src "libresoc.v:92073.9-92073.17" + attribute \src "libresoc.v:92846.9-92846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144151,18 +145291,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:92109.3-92145.6" - process $proc$libresoc.v:92109$3891 + attribute \src "libresoc.v:92882.3-92918.6" + process $proc$libresoc.v:92882$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92110.5-92110.29" + attribute \src "libresoc.v:92883.5-92883.29" switch \initial - attribute \src "libresoc.v:92110.9-92110.17" + attribute \src "libresoc.v:92883.9-92883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144210,18 +145350,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:92146.3-92182.6" - process $proc$libresoc.v:92146$3892 + attribute \src "libresoc.v:92919.3-92955.6" + process $proc$libresoc.v:92919$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92147.5-92147.29" + attribute \src "libresoc.v:92920.5-92920.29" switch \initial - attribute \src "libresoc.v:92147.9-92147.17" + attribute \src "libresoc.v:92920.9-92920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144269,18 +145409,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:92183.3-92219.6" - process $proc$libresoc.v:92183$3893 + attribute \src "libresoc.v:92956.3-92992.6" + process $proc$libresoc.v:92956$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92184.5-92184.29" + attribute \src "libresoc.v:92957.5-92957.29" switch \initial - attribute \src "libresoc.v:92184.9-92184.17" + attribute \src "libresoc.v:92957.9-92957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144328,18 +145468,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:92220.3-92256.6" - process $proc$libresoc.v:92220$3894 + attribute \src "libresoc.v:92993.3-93029.6" + process $proc$libresoc.v:92993$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92221.5-92221.29" + attribute \src "libresoc.v:92994.5-92994.29" switch \initial - attribute \src "libresoc.v:92221.9-92221.17" + attribute \src "libresoc.v:92994.9-92994.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -144389,157 +145529,161 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92262.1-94362.10" +attribute \src "libresoc.v:93035.1-95200.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:94031.3-94085.6" + attribute \src "libresoc.v:94869.3-94923.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94086.3-94140.6" + attribute \src "libresoc.v:94924.3-94978.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:93371.3-93425.6" + attribute \src "libresoc.v:94209.3-94263.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93591.3-93645.6" + attribute \src "libresoc.v:94429.3-94483.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92656.3-92710.6" + attribute \src "libresoc.v:93439.3-93493.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92711.3-92765.6" + attribute \src "libresoc.v:93494.3-93548.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93316.3-93370.6" + attribute \src "libresoc.v:94154.3-94208.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93536.3-93590.6" + attribute \src "libresoc.v:94374.3-94428.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93811.3-93865.6" + attribute \src "libresoc.v:94594.3-94648.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:92601.3-92655.6" + attribute \src "libresoc.v:93384.3-93438.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94141.3-94195.6" + attribute \src "libresoc.v:94979.3-95033.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94196.3-94250.6" + attribute \src "libresoc.v:95034.3-95088.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94251.3-94305.6" + attribute \src "libresoc.v:95089.3-95143.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93206.3-93260.6" + attribute \src "libresoc.v:93989.3-94043.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93426.3-93480.6" + attribute \src "libresoc.v:94264.3-94318.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93481.3-93535.6" + attribute \src "libresoc.v:94319.3-94373.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93756.3-93810.6" + attribute \src "libresoc.v:94649.3-94703.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93096.3-93150.6" + attribute \src "libresoc.v:93934.3-93988.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93921.3-93975.6" + attribute \src "libresoc.v:94759.3-94813.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94306.3-94360.6" + attribute \src "libresoc.v:95144.3-95198.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93261.3-93315.6" + attribute \src "libresoc.v:94099.3-94153.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93701.3-93755.6" + attribute \src "libresoc.v:94539.3-94593.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93976.3-94030.6" + attribute \src "libresoc.v:94814.3-94868.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93866.3-93920.6" + attribute \src "libresoc.v:94704.3-94758.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93646.3-93700.6" + attribute \src "libresoc.v:94484.3-94538.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92986.3-93040.6" + attribute \src "libresoc.v:93824.3-93878.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93041.3-93095.6" + attribute \src "libresoc.v:93879.3-93933.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92766.3-92820.6" + attribute \src "libresoc.v:93549.3-93603.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92821.3-92875.6" + attribute \src "libresoc.v:93604.3-93658.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92876.3-92930.6" + attribute \src "libresoc.v:93659.3-93713.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92931.3-92985.6" + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93151.3-93205.6" + attribute \src "libresoc.v:94044.3-94098.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:92263.7-92263.20" + attribute \src "libresoc.v:93036.7-93036.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94031.3-94085.6" + attribute \src "libresoc.v:94869.3-94923.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94086.3-94140.6" + attribute \src "libresoc.v:94924.3-94978.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:93371.3-93425.6" + attribute \src "libresoc.v:94209.3-94263.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93591.3-93645.6" + attribute \src "libresoc.v:94429.3-94483.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92656.3-92710.6" + attribute \src "libresoc.v:93439.3-93493.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92711.3-92765.6" + attribute \src "libresoc.v:93494.3-93548.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93316.3-93370.6" + attribute \src "libresoc.v:94154.3-94208.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93536.3-93590.6" + attribute \src "libresoc.v:94374.3-94428.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93811.3-93865.6" + attribute \src "libresoc.v:94594.3-94648.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:92601.3-92655.6" + attribute \src "libresoc.v:93384.3-93438.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94141.3-94195.6" + attribute \src "libresoc.v:94979.3-95033.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94196.3-94250.6" + attribute \src "libresoc.v:95034.3-95088.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94251.3-94305.6" + attribute \src "libresoc.v:95089.3-95143.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93206.3-93260.6" + attribute \src "libresoc.v:93989.3-94043.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93426.3-93480.6" + attribute \src "libresoc.v:94264.3-94318.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93481.3-93535.6" + attribute \src "libresoc.v:94319.3-94373.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93756.3-93810.6" + attribute \src "libresoc.v:94649.3-94703.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93096.3-93150.6" + attribute \src "libresoc.v:93934.3-93988.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93921.3-93975.6" + attribute \src "libresoc.v:94759.3-94813.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94306.3-94360.6" + attribute \src "libresoc.v:95144.3-95198.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:93261.3-93315.6" + attribute \src "libresoc.v:94099.3-94153.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93701.3-93755.6" + attribute \src "libresoc.v:94539.3-94593.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93976.3-94030.6" + attribute \src "libresoc.v:94814.3-94868.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93866.3-93920.6" + attribute \src "libresoc.v:94704.3-94758.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93646.3-93700.6" + attribute \src "libresoc.v:94484.3-94538.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92986.3-93040.6" + attribute \src "libresoc.v:93824.3-93878.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93041.3-93095.6" + attribute \src "libresoc.v:93879.3-93933.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92766.3-92820.6" + attribute \src "libresoc.v:93549.3-93603.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92821.3-92875.6" + attribute \src "libresoc.v:93604.3-93658.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92876.3-92930.6" + attribute \src "libresoc.v:93659.3-93713.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92931.3-92985.6" + attribute \src "libresoc.v:93769.3-93823.6" + wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93714.3-93768.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93151.3-93205.6" + attribute \src "libresoc.v:94044.3-94098.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub11_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub11_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub11_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -144549,7 +145693,7 @@ module \dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -144558,16 +145702,16 @@ module \dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub11_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -144599,7 +145743,7 @@ module \dec31_dec_sub11 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -144616,7 +145760,7 @@ module \dec31_dec_sub11 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -144624,7 +145768,7 @@ module \dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -144641,13 +145785,13 @@ module \dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -144724,46 +145868,46 @@ module \dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub11_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub11_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub11_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub11_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144771,8 +145915,8 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub11_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub11_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144780,8 +145924,8 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub11_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub11_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -144789,7 +145933,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub11_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144798,7 +145942,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub11_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144807,7 +145951,7 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub11_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -144816,41 +145960,50 @@ module \dec31_dec_sub11 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub11_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub11_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub11_upd - attribute \src "libresoc.v:92263.7-92263.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub11_upd + attribute \src "libresoc.v:93036.7-93036.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:92263.7-92263.20" - process $proc$libresoc.v:92263$3928 + attribute \src "libresoc.v:93036.7-93036.20" + process $proc$libresoc.v:93036$3952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:92601.3-92655.6" - process $proc$libresoc.v:92601$3896 + attribute \src "libresoc.v:93384.3-93438.6" + process $proc$libresoc.v:93384$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:92602.5-92602.29" + attribute \src "libresoc.v:93385.5-93385.29" switch \initial - attribute \src "libresoc.v:92602.9-92602.17" + attribute \src "libresoc.v:93385.9-93385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -144922,18 +146075,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:92656.3-92710.6" - process $proc$libresoc.v:92656$3897 + attribute \src "libresoc.v:93439.3-93493.6" + process $proc$libresoc.v:93439$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92657.5-92657.29" + attribute \src "libresoc.v:93440.5-93440.29" switch \initial - attribute \src "libresoc.v:92657.9-92657.17" + attribute \src "libresoc.v:93440.9-93440.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145005,18 +146158,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:92711.3-92765.6" - process $proc$libresoc.v:92711$3898 + attribute \src "libresoc.v:93494.3-93548.6" + process $proc$libresoc.v:93494$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:92712.5-92712.29" + attribute \src "libresoc.v:93495.5-93495.29" switch \initial - attribute \src "libresoc.v:92712.9-92712.17" + attribute \src "libresoc.v:93495.9-93495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145088,18 +146241,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:92766.3-92820.6" - process $proc$libresoc.v:92766$3899 + attribute \src "libresoc.v:93549.3-93603.6" + process $proc$libresoc.v:93549$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92767.5-92767.29" + attribute \src "libresoc.v:93550.5-93550.29" switch \initial - attribute \src "libresoc.v:92767.9-92767.17" + attribute \src "libresoc.v:93550.9-93550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145171,18 +146324,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:92821.3-92875.6" - process $proc$libresoc.v:92821$3900 + attribute \src "libresoc.v:93604.3-93658.6" + process $proc$libresoc.v:93604$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92822.5-92822.29" + attribute \src "libresoc.v:93605.5-93605.29" switch \initial - attribute \src "libresoc.v:92822.9-92822.17" + attribute \src "libresoc.v:93605.9-93605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145254,18 +146407,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:92876.3-92930.6" - process $proc$libresoc.v:92876$3901 + attribute \src "libresoc.v:93659.3-93713.6" + process $proc$libresoc.v:93659$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92877.5-92877.29" + attribute \src "libresoc.v:93660.5-93660.29" switch \initial - attribute \src "libresoc.v:92877.9-92877.17" + attribute \src "libresoc.v:93660.9-93660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145337,18 +146490,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:92931.3-92985.6" - process $proc$libresoc.v:92931$3902 + attribute \src "libresoc.v:93714.3-93768.6" + process $proc$libresoc.v:93714$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:92932.5-92932.29" + attribute \src "libresoc.v:93715.5-93715.29" switch \initial - attribute \src "libresoc.v:92932.9-92932.17" + attribute \src "libresoc.v:93715.9-93715.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145420,18 +146573,101 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:92986.3-93040.6" - process $proc$libresoc.v:92986$3903 + attribute \src "libresoc.v:93769.3-93823.6" + process $proc$libresoc.v:93769$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] + attribute \src "libresoc.v:93770.5-93770.29" + switch \initial + attribute \src "libresoc.v:93770.9-93770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] + end + attribute \src "libresoc.v:93824.3-93878.6" + process $proc$libresoc.v:93824$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:92987.5-92987.29" + attribute \src "libresoc.v:93825.5-93825.29" switch \initial - attribute \src "libresoc.v:92987.9-92987.17" + attribute \src "libresoc.v:93825.9-93825.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145503,18 +146739,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:93041.3-93095.6" - process $proc$libresoc.v:93041$3904 + attribute \src "libresoc.v:93879.3-93933.6" + process $proc$libresoc.v:93879$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93042.5-93042.29" + attribute \src "libresoc.v:93880.5-93880.29" switch \initial - attribute \src "libresoc.v:93042.9-93042.17" + attribute \src "libresoc.v:93880.9-93880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145586,18 +146822,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:93096.3-93150.6" - process $proc$libresoc.v:93096$3905 + attribute \src "libresoc.v:93934.3-93988.6" + process $proc$libresoc.v:93934$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93097.5-93097.29" + attribute \src "libresoc.v:93935.5-93935.29" switch \initial - attribute \src "libresoc.v:93097.9-93097.17" + attribute \src "libresoc.v:93935.9-93935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145669,184 +146905,184 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:93151.3-93205.6" - process $proc$libresoc.v:93151$3906 + attribute \src "libresoc.v:93989.3-94043.6" + process $proc$libresoc.v:93989$3930 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:93152.5-93152.29" + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:93990.5-93990.29" switch \initial - attribute \src "libresoc.v:93152.9-93152.17" + attribute \src "libresoc.v:93990.9-93990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:93206.3-93260.6" - process $proc$libresoc.v:93206$3907 + attribute \src "libresoc.v:94044.3-94098.6" + process $proc$libresoc.v:94044$3931 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93207.5-93207.29" + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:94045.5-94045.29" switch \initial - attribute \src "libresoc.v:93207.9-93207.17" + attribute \src "libresoc.v:94045.9-94045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub11_upd[1:0] 2'00 end sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:93261.3-93315.6" - process $proc$libresoc.v:93261$3908 + attribute \src "libresoc.v:94099.3-94153.6" + process $proc$libresoc.v:94099$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:93262.5-93262.29" + attribute \src "libresoc.v:94100.5-94100.29" switch \initial - attribute \src "libresoc.v:93262.9-93262.17" + attribute \src "libresoc.v:94100.9-94100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -145918,18 +147154,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:93316.3-93370.6" - process $proc$libresoc.v:93316$3909 + attribute \src "libresoc.v:94154.3-94208.6" + process $proc$libresoc.v:94154$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:93317.5-93317.29" + attribute \src "libresoc.v:94155.5-94155.29" switch \initial - attribute \src "libresoc.v:93317.9-93317.17" + attribute \src "libresoc.v:94155.9-94155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146001,18 +147237,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:93371.3-93425.6" - process $proc$libresoc.v:93371$3910 + attribute \src "libresoc.v:94209.3-94263.6" + process $proc$libresoc.v:94209$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:93372.5-93372.29" + attribute \src "libresoc.v:94210.5-94210.29" switch \initial - attribute \src "libresoc.v:93372.9-93372.17" + attribute \src "libresoc.v:94210.9-94210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146084,18 +147320,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:93426.3-93480.6" - process $proc$libresoc.v:93426$3911 + attribute \src "libresoc.v:94264.3-94318.6" + process $proc$libresoc.v:94264$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:93427.5-93427.29" + attribute \src "libresoc.v:94265.5-94265.29" switch \initial - attribute \src "libresoc.v:93427.9-93427.17" + attribute \src "libresoc.v:94265.9-94265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146167,18 +147403,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:93481.3-93535.6" - process $proc$libresoc.v:93481$3912 + attribute \src "libresoc.v:94319.3-94373.6" + process $proc$libresoc.v:94319$3936 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93482.5-93482.29" + attribute \src "libresoc.v:94320.5-94320.29" switch \initial - attribute \src "libresoc.v:93482.9-93482.17" + attribute \src "libresoc.v:94320.9-94320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146250,18 +147486,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:93536.3-93590.6" - process $proc$libresoc.v:93536$3913 + attribute \src "libresoc.v:94374.3-94428.6" + process $proc$libresoc.v:94374$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93537.5-93537.29" + attribute \src "libresoc.v:94375.5-94375.29" switch \initial - attribute \src "libresoc.v:93537.9-93537.17" + attribute \src "libresoc.v:94375.9-94375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146333,18 +147569,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:93591.3-93645.6" - process $proc$libresoc.v:93591$3914 + attribute \src "libresoc.v:94429.3-94483.6" + process $proc$libresoc.v:94429$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93592.5-93592.29" + attribute \src "libresoc.v:94430.5-94430.29" switch \initial - attribute \src "libresoc.v:93592.9-93592.17" + attribute \src "libresoc.v:94430.9-94430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146416,18 +147652,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:93646.3-93700.6" - process $proc$libresoc.v:93646$3915 + attribute \src "libresoc.v:94484.3-94538.6" + process $proc$libresoc.v:94484$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93647.5-93647.29" + attribute \src "libresoc.v:94485.5-94485.29" switch \initial - attribute \src "libresoc.v:93647.9-93647.17" + attribute \src "libresoc.v:94485.9-94485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146499,18 +147735,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:93701.3-93755.6" - process $proc$libresoc.v:93701$3916 + attribute \src "libresoc.v:94539.3-94593.6" + process $proc$libresoc.v:94539$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93702.5-93702.29" + attribute \src "libresoc.v:94540.5-94540.29" switch \initial - attribute \src "libresoc.v:93702.9-93702.17" + attribute \src "libresoc.v:94540.9-94540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146582,184 +147818,184 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:93756.3-93810.6" - process $proc$libresoc.v:93756$3917 + attribute \src "libresoc.v:94594.3-94648.6" + process $proc$libresoc.v:94594$3941 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93757.5-93757.29" + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:94595.5-94595.29" switch \initial - attribute \src "libresoc.v:93757.9-93757.17" + attribute \src "libresoc.v:94595.9-94595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub11_form[4:0] 5'10001 case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub11_form[4:0] 5'00000 end sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:93811.3-93865.6" - process $proc$libresoc.v:93811$3918 + attribute \src "libresoc.v:94649.3-94703.6" + process $proc$libresoc.v:94649$3942 assign { } { } assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93812.5-93812.29" + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:94650.5-94650.29" switch \initial - attribute \src "libresoc.v:93812.9-93812.17" + attribute \src "libresoc.v:94650.9-94650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:93866.3-93920.6" - process $proc$libresoc.v:93866$3919 + attribute \src "libresoc.v:94704.3-94758.6" + process $proc$libresoc.v:94704$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93867.5-93867.29" + attribute \src "libresoc.v:94705.5-94705.29" switch \initial - attribute \src "libresoc.v:93867.9-93867.17" + attribute \src "libresoc.v:94705.9-94705.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146831,18 +148067,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:93921.3-93975.6" - process $proc$libresoc.v:93921$3920 + attribute \src "libresoc.v:94759.3-94813.6" + process $proc$libresoc.v:94759$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:93922.5-93922.29" + attribute \src "libresoc.v:94760.5-94760.29" switch \initial - attribute \src "libresoc.v:93922.9-93922.17" + attribute \src "libresoc.v:94760.9-94760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146914,18 +148150,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:93976.3-94030.6" - process $proc$libresoc.v:93976$3921 + attribute \src "libresoc.v:94814.3-94868.6" + process $proc$libresoc.v:94814$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93977.5-93977.29" + attribute \src "libresoc.v:94815.5-94815.29" switch \initial - attribute \src "libresoc.v:93977.9-93977.17" + attribute \src "libresoc.v:94815.9-94815.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -146997,18 +148233,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:94031.3-94085.6" - process $proc$libresoc.v:94031$3922 + attribute \src "libresoc.v:94869.3-94923.6" + process $proc$libresoc.v:94869$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94032.5-94032.29" + attribute \src "libresoc.v:94870.5-94870.29" switch \initial - attribute \src "libresoc.v:94032.9-94032.17" + attribute \src "libresoc.v:94870.9-94870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147080,18 +148316,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:94086.3-94140.6" - process $proc$libresoc.v:94086$3923 + attribute \src "libresoc.v:94924.3-94978.6" + process $proc$libresoc.v:94924$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94087.5-94087.29" + attribute \src "libresoc.v:94925.5-94925.29" switch \initial - attribute \src "libresoc.v:94087.9-94087.17" + attribute \src "libresoc.v:94925.9-94925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147163,18 +148399,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:94141.3-94195.6" - process $proc$libresoc.v:94141$3924 + attribute \src "libresoc.v:94979.3-95033.6" + process $proc$libresoc.v:94979$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94142.5-94142.29" + attribute \src "libresoc.v:94980.5-94980.29" switch \initial - attribute \src "libresoc.v:94142.9-94142.17" + attribute \src "libresoc.v:94980.9-94980.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147246,18 +148482,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:94196.3-94250.6" - process $proc$libresoc.v:94196$3925 + attribute \src "libresoc.v:95034.3-95088.6" + process $proc$libresoc.v:95034$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:94197.5-94197.29" + attribute \src "libresoc.v:95035.5-95035.29" switch \initial - attribute \src "libresoc.v:94197.9-94197.17" + attribute \src "libresoc.v:95035.9-95035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147329,18 +148565,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:94251.3-94305.6" - process $proc$libresoc.v:94251$3926 + attribute \src "libresoc.v:95089.3-95143.6" + process $proc$libresoc.v:95089$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:94252.5-94252.29" + attribute \src "libresoc.v:95090.5-95090.29" switch \initial - attribute \src "libresoc.v:94252.9-94252.17" + attribute \src "libresoc.v:95090.9-95090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147412,18 +148648,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:94306.3-94360.6" - process $proc$libresoc.v:94306$3927 + attribute \src "libresoc.v:95144.3-95198.6" + process $proc$libresoc.v:95144$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94307.5-94307.29" + attribute \src "libresoc.v:95145.5-95145.29" switch \initial - attribute \src "libresoc.v:94307.9-94307.17" + attribute \src "libresoc.v:95145.9-95145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -147497,157 +148733,161 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:94366.1-98002.10" +attribute \src "libresoc.v:95204.1-98953.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:97383.3-97485.6" + attribute \src "libresoc.v:98334.3-98436.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97486.3-97588.6" + attribute \src "libresoc.v:98437.3-98539.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96147.3-96249.6" + attribute \src "libresoc.v:97098.3-97200.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96559.3-96661.6" + attribute \src "libresoc.v:97510.3-97612.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94808.3-94910.6" + attribute \src "libresoc.v:95656.3-95758.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94911.3-95013.6" + attribute \src "libresoc.v:95759.3-95861.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96044.3-96146.6" + attribute \src "libresoc.v:96995.3-97097.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96456.3-96558.6" + attribute \src "libresoc.v:97407.3-97509.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96971.3-97073.6" + attribute \src "libresoc.v:97819.3-97921.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:94705.3-94807.6" + attribute \src "libresoc.v:95553.3-95655.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:97589.3-97691.6" + attribute \src "libresoc.v:98540.3-98642.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97692.3-97794.6" + attribute \src "libresoc.v:98643.3-98745.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97795.3-97897.6" + attribute \src "libresoc.v:98746.3-98848.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95838.3-95940.6" + attribute \src "libresoc.v:96686.3-96788.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96250.3-96352.6" + attribute \src "libresoc.v:97201.3-97303.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96353.3-96455.6" + attribute \src "libresoc.v:97304.3-97406.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96868.3-96970.6" + attribute \src "libresoc.v:97922.3-98024.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:95632.3-95734.6" + attribute \src "libresoc.v:96583.3-96685.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:97177.3-97279.6" + attribute \src "libresoc.v:98128.3-98230.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97898.3-98000.6" + attribute \src "libresoc.v:98849.3-98951.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:95941.3-96043.6" + attribute \src "libresoc.v:96892.3-96994.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96765.3-96867.6" + attribute \src "libresoc.v:97716.3-97818.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97280.3-97382.6" + attribute \src "libresoc.v:98231.3-98333.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97074.3-97176.6" + attribute \src "libresoc.v:98025.3-98127.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:96662.3-96764.6" + attribute \src "libresoc.v:97613.3-97715.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95426.3-95528.6" + attribute \src "libresoc.v:96377.3-96479.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95529.3-95631.6" + attribute \src "libresoc.v:96480.3-96582.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95014.3-95116.6" + attribute \src "libresoc.v:95862.3-95964.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95117.3-95219.6" + attribute \src "libresoc.v:95965.3-96067.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95220.3-95322.6" + attribute \src "libresoc.v:96068.3-96170.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95323.3-95425.6" + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95735.3-95837.6" + attribute \src "libresoc.v:96789.3-96891.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:94367.7-94367.20" + attribute \src "libresoc.v:95205.7-95205.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97383.3-97485.6" + attribute \src "libresoc.v:98334.3-98436.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97486.3-97588.6" + attribute \src "libresoc.v:98437.3-98539.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96147.3-96249.6" + attribute \src "libresoc.v:97098.3-97200.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96559.3-96661.6" + attribute \src "libresoc.v:97510.3-97612.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94808.3-94910.6" + attribute \src "libresoc.v:95656.3-95758.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94911.3-95013.6" + attribute \src "libresoc.v:95759.3-95861.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96044.3-96146.6" + attribute \src "libresoc.v:96995.3-97097.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96456.3-96558.6" + attribute \src "libresoc.v:97407.3-97509.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96971.3-97073.6" + attribute \src "libresoc.v:97819.3-97921.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:94705.3-94807.6" + attribute \src "libresoc.v:95553.3-95655.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:97589.3-97691.6" + attribute \src "libresoc.v:98540.3-98642.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97692.3-97794.6" + attribute \src "libresoc.v:98643.3-98745.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97795.3-97897.6" + attribute \src "libresoc.v:98746.3-98848.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95838.3-95940.6" + attribute \src "libresoc.v:96686.3-96788.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96250.3-96352.6" + attribute \src "libresoc.v:97201.3-97303.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96353.3-96455.6" + attribute \src "libresoc.v:97304.3-97406.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96868.3-96970.6" + attribute \src "libresoc.v:97922.3-98024.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:95632.3-95734.6" + attribute \src "libresoc.v:96583.3-96685.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:97177.3-97279.6" + attribute \src "libresoc.v:98128.3-98230.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97898.3-98000.6" + attribute \src "libresoc.v:98849.3-98951.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:95941.3-96043.6" + attribute \src "libresoc.v:96892.3-96994.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96765.3-96867.6" + attribute \src "libresoc.v:97716.3-97818.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97280.3-97382.6" + attribute \src "libresoc.v:98231.3-98333.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97074.3-97176.6" + attribute \src "libresoc.v:98025.3-98127.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:96662.3-96764.6" + attribute \src "libresoc.v:97613.3-97715.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95426.3-95528.6" + attribute \src "libresoc.v:96377.3-96479.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95529.3-95631.6" + attribute \src "libresoc.v:96480.3-96582.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95014.3-95116.6" + attribute \src "libresoc.v:95862.3-95964.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95117.3-95219.6" + attribute \src "libresoc.v:95965.3-96067.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95220.3-95322.6" + attribute \src "libresoc.v:96068.3-96170.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95323.3-95425.6" + attribute \src "libresoc.v:96274.3-96376.6" + wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96171.3-96273.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95735.3-95837.6" + attribute \src "libresoc.v:96789.3-96891.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub15_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub15_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub15_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -147657,7 +148897,7 @@ module \dec31_dec_sub15 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -147666,16 +148906,16 @@ module \dec31_dec_sub15 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub15_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -147707,7 +148947,7 @@ module \dec31_dec_sub15 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -147724,7 +148964,7 @@ module \dec31_dec_sub15 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -147732,7 +148972,7 @@ module \dec31_dec_sub15 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -147749,13 +148989,13 @@ module \dec31_dec_sub15 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -147832,46 +149072,46 @@ module \dec31_dec_sub15 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub15_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub15_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub15_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub15_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147879,8 +149119,8 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub15_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub15_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147888,8 +149128,8 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub15_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub15_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -147897,7 +149137,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub15_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147906,7 +149146,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub15_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147915,7 +149155,7 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub15_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -147924,41 +149164,50 @@ module \dec31_dec_sub15 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub15_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub15_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub15_upd - attribute \src "libresoc.v:94367.7-94367.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub15_upd + attribute \src "libresoc.v:95205.7-95205.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:94367.7-94367.20" - process $proc$libresoc.v:94367$3961 + attribute \src "libresoc.v:95205.7-95205.20" + process $proc$libresoc.v:95205$3986 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:94705.3-94807.6" - process $proc$libresoc.v:94705$3929 + attribute \src "libresoc.v:95553.3-95655.6" + process $proc$libresoc.v:95553$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:94706.5-94706.29" + attribute \src "libresoc.v:95554.5-95554.29" switch \initial - attribute \src "libresoc.v:94706.9-94706.17" + attribute \src "libresoc.v:95554.9-95554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148094,18 +149343,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:94808.3-94910.6" - process $proc$libresoc.v:94808$3930 + attribute \src "libresoc.v:95656.3-95758.6" + process $proc$libresoc.v:95656$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94809.5-94809.29" + attribute \src "libresoc.v:95657.5-95657.29" switch \initial - attribute \src "libresoc.v:94809.9-94809.17" + attribute \src "libresoc.v:95657.9-95657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148241,18 +149490,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:94911.3-95013.6" - process $proc$libresoc.v:94911$3931 + attribute \src "libresoc.v:95759.3-95861.6" + process $proc$libresoc.v:95759$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:94912.5-94912.29" + attribute \src "libresoc.v:95760.5-95760.29" switch \initial - attribute \src "libresoc.v:94912.9-94912.17" + attribute \src "libresoc.v:95760.9-95760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148388,18 +149637,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:95014.3-95116.6" - process $proc$libresoc.v:95014$3932 + attribute \src "libresoc.v:95862.3-95964.6" + process $proc$libresoc.v:95862$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95015.5-95015.29" + attribute \src "libresoc.v:95863.5-95863.29" switch \initial - attribute \src "libresoc.v:95015.9-95015.17" + attribute \src "libresoc.v:95863.9-95863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148535,18 +149784,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:95117.3-95219.6" - process $proc$libresoc.v:95117$3933 + attribute \src "libresoc.v:95965.3-96067.6" + process $proc$libresoc.v:95965$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95118.5-95118.29" + attribute \src "libresoc.v:95966.5-95966.29" switch \initial - attribute \src "libresoc.v:95118.9-95118.17" + attribute \src "libresoc.v:95966.9-95966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148682,18 +149931,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:95220.3-95322.6" - process $proc$libresoc.v:95220$3934 + attribute \src "libresoc.v:96068.3-96170.6" + process $proc$libresoc.v:96068$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:95221.5-95221.29" + attribute \src "libresoc.v:96069.5-96069.29" switch \initial - attribute \src "libresoc.v:95221.9-95221.17" + attribute \src "libresoc.v:96069.9-96069.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148829,18 +150078,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:95323.3-95425.6" - process $proc$libresoc.v:95323$3935 + attribute \src "libresoc.v:96171.3-96273.6" + process $proc$libresoc.v:96171$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95324.5-95324.29" + attribute \src "libresoc.v:96172.5-96172.29" switch \initial - attribute \src "libresoc.v:95324.9-95324.17" + attribute \src "libresoc.v:96172.9-96172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -148976,18 +150225,165 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:95426.3-95528.6" - process $proc$libresoc.v:95426$3936 + attribute \src "libresoc.v:96274.3-96376.6" + process $proc$libresoc.v:96274$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] + attribute \src "libresoc.v:96275.5-96275.29" + switch \initial + attribute \src "libresoc.v:96275.9-96275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] + end + attribute \src "libresoc.v:96377.3-96479.6" + process $proc$libresoc.v:96377$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:95427.5-95427.29" + attribute \src "libresoc.v:96378.5-96378.29" switch \initial - attribute \src "libresoc.v:95427.9-95427.17" + attribute \src "libresoc.v:96378.9-96378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149123,18 +150519,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:95529.3-95631.6" - process $proc$libresoc.v:95529$3937 + attribute \src "libresoc.v:96480.3-96582.6" + process $proc$libresoc.v:96480$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95530.5-95530.29" + attribute \src "libresoc.v:96481.5-96481.29" switch \initial - attribute \src "libresoc.v:95530.9-95530.17" + attribute \src "libresoc.v:96481.9-96481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149270,18 +150666,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:95632.3-95734.6" - process $proc$libresoc.v:95632$3938 + attribute \src "libresoc.v:96583.3-96685.6" + process $proc$libresoc.v:96583$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:95633.5-95633.29" + attribute \src "libresoc.v:96584.5-96584.29" switch \initial - attribute \src "libresoc.v:95633.9-95633.17" + attribute \src "libresoc.v:96584.9-96584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149417,312 +150813,312 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:95735.3-95837.6" - process $proc$libresoc.v:95735$3939 + attribute \src "libresoc.v:96686.3-96788.6" + process $proc$libresoc.v:96686$3964 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95736.5-95736.29" + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:96687.5-96687.29" switch \initial - attribute \src "libresoc.v:95736.9-95736.17" + attribute \src "libresoc.v:96687.9-96687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:95838.3-95940.6" - process $proc$libresoc.v:95838$3940 + attribute \src "libresoc.v:96789.3-96891.6" + process $proc$libresoc.v:96789$3965 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:95839.5-95839.29" + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:96790.5-96790.29" switch \initial - attribute \src "libresoc.v:95839.9-95839.17" + attribute \src "libresoc.v:96790.9-96790.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 end sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:95941.3-96043.6" - process $proc$libresoc.v:95941$3941 + attribute \src "libresoc.v:96892.3-96994.6" + process $proc$libresoc.v:96892$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:95942.5-95942.29" + attribute \src "libresoc.v:96893.5-96893.29" switch \initial - attribute \src "libresoc.v:95942.9-95942.17" + attribute \src "libresoc.v:96893.9-96893.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -149858,18 +151254,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:96044.3-96146.6" - process $proc$libresoc.v:96044$3942 + attribute \src "libresoc.v:96995.3-97097.6" + process $proc$libresoc.v:96995$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96045.5-96045.29" + attribute \src "libresoc.v:96996.5-96996.29" switch \initial - attribute \src "libresoc.v:96045.9-96045.17" + attribute \src "libresoc.v:96996.9-96996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150005,18 +151401,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:96147.3-96249.6" - process $proc$libresoc.v:96147$3943 + attribute \src "libresoc.v:97098.3-97200.6" + process $proc$libresoc.v:97098$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:96148.5-96148.29" + attribute \src "libresoc.v:97099.5-97099.29" switch \initial - attribute \src "libresoc.v:96148.9-96148.17" + attribute \src "libresoc.v:97099.9-97099.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150152,18 +151548,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:96250.3-96352.6" - process $proc$libresoc.v:96250$3944 + attribute \src "libresoc.v:97201.3-97303.6" + process $proc$libresoc.v:97201$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:96251.5-96251.29" + attribute \src "libresoc.v:97202.5-97202.29" switch \initial - attribute \src "libresoc.v:96251.9-96251.17" + attribute \src "libresoc.v:97202.9-97202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150299,18 +151695,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:96353.3-96455.6" - process $proc$libresoc.v:96353$3945 + attribute \src "libresoc.v:97304.3-97406.6" + process $proc$libresoc.v:97304$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96354.5-96354.29" + attribute \src "libresoc.v:97305.5-97305.29" switch \initial - attribute \src "libresoc.v:96354.9-96354.17" + attribute \src "libresoc.v:97305.9-97305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150446,18 +151842,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:96456.3-96558.6" - process $proc$libresoc.v:96456$3946 + attribute \src "libresoc.v:97407.3-97509.6" + process $proc$libresoc.v:97407$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96457.5-96457.29" + attribute \src "libresoc.v:97408.5-97408.29" switch \initial - attribute \src "libresoc.v:96457.9-96457.17" + attribute \src "libresoc.v:97408.9-97408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150593,18 +151989,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:96559.3-96661.6" - process $proc$libresoc.v:96559$3947 + attribute \src "libresoc.v:97510.3-97612.6" + process $proc$libresoc.v:97510$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:96560.5-96560.29" + attribute \src "libresoc.v:97511.5-97511.29" switch \initial - attribute \src "libresoc.v:96560.9-96560.17" + attribute \src "libresoc.v:97511.9-97511.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150740,18 +152136,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:96662.3-96764.6" - process $proc$libresoc.v:96662$3948 + attribute \src "libresoc.v:97613.3-97715.6" + process $proc$libresoc.v:97613$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96663.5-96663.29" + attribute \src "libresoc.v:97614.5-97614.29" switch \initial - attribute \src "libresoc.v:96663.9-96663.17" + attribute \src "libresoc.v:97614.9-97614.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150887,18 +152283,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:96765.3-96867.6" - process $proc$libresoc.v:96765$3949 + attribute \src "libresoc.v:97716.3-97818.6" + process $proc$libresoc.v:97716$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:96766.5-96766.29" + attribute \src "libresoc.v:97717.5-97717.29" switch \initial - attribute \src "libresoc.v:96766.9-96766.17" + attribute \src "libresoc.v:97717.9-97717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151034,312 +152430,312 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:96868.3-96970.6" - process $proc$libresoc.v:96868$3950 + attribute \src "libresoc.v:97819.3-97921.6" + process $proc$libresoc.v:97819$3975 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96869.5-96869.29" + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:97820.5-97820.29" switch \initial - attribute \src "libresoc.v:96869.9-96869.17" + attribute \src "libresoc.v:97820.9-97820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'10010 case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub15_form[4:0] 5'00000 end sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:96971.3-97073.6" - process $proc$libresoc.v:96971$3951 + attribute \src "libresoc.v:97922.3-98024.6" + process $proc$libresoc.v:97922$3976 assign { } { } assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:96972.5-96972.29" + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:97923.5-97923.29" switch \initial - attribute \src "libresoc.v:96972.9-96972.17" + attribute \src "libresoc.v:97923.9-97923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:97074.3-97176.6" - process $proc$libresoc.v:97074$3952 + attribute \src "libresoc.v:98025.3-98127.6" + process $proc$libresoc.v:98025$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97075.5-97075.29" + attribute \src "libresoc.v:98026.5-98026.29" switch \initial - attribute \src "libresoc.v:97075.9-97075.17" + attribute \src "libresoc.v:98026.9-98026.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151475,18 +152871,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:97177.3-97279.6" - process $proc$libresoc.v:97177$3953 + attribute \src "libresoc.v:98128.3-98230.6" + process $proc$libresoc.v:98128$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97178.5-97178.29" + attribute \src "libresoc.v:98129.5-98129.29" switch \initial - attribute \src "libresoc.v:97178.9-97178.17" + attribute \src "libresoc.v:98129.9-98129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151622,18 +153018,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:97280.3-97382.6" - process $proc$libresoc.v:97280$3954 + attribute \src "libresoc.v:98231.3-98333.6" + process $proc$libresoc.v:98231$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:97281.5-97281.29" + attribute \src "libresoc.v:98232.5-98232.29" switch \initial - attribute \src "libresoc.v:97281.9-97281.17" + attribute \src "libresoc.v:98232.9-98232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151769,18 +153165,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:97383.3-97485.6" - process $proc$libresoc.v:97383$3955 + attribute \src "libresoc.v:98334.3-98436.6" + process $proc$libresoc.v:98334$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:97384.5-97384.29" + attribute \src "libresoc.v:98335.5-98335.29" switch \initial - attribute \src "libresoc.v:97384.9-97384.17" + attribute \src "libresoc.v:98335.9-98335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151916,18 +153312,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:97486.3-97588.6" - process $proc$libresoc.v:97486$3956 + attribute \src "libresoc.v:98437.3-98539.6" + process $proc$libresoc.v:98437$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97487.5-97487.29" + attribute \src "libresoc.v:98438.5-98438.29" switch \initial - attribute \src "libresoc.v:97487.9-97487.17" + attribute \src "libresoc.v:98438.9-98438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152063,18 +153459,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:97589.3-97691.6" - process $proc$libresoc.v:97589$3957 + attribute \src "libresoc.v:98540.3-98642.6" + process $proc$libresoc.v:98540$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:97590.5-97590.29" + attribute \src "libresoc.v:98541.5-98541.29" switch \initial - attribute \src "libresoc.v:97590.9-97590.17" + attribute \src "libresoc.v:98541.9-98541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152210,18 +153606,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:97692.3-97794.6" - process $proc$libresoc.v:97692$3958 + attribute \src "libresoc.v:98643.3-98745.6" + process $proc$libresoc.v:98643$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97693.5-97693.29" + attribute \src "libresoc.v:98644.5-98644.29" switch \initial - attribute \src "libresoc.v:97693.9-97693.17" + attribute \src "libresoc.v:98644.9-98644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152357,18 +153753,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:97795.3-97897.6" - process $proc$libresoc.v:97795$3959 + attribute \src "libresoc.v:98746.3-98848.6" + process $proc$libresoc.v:98746$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:97796.5-97796.29" + attribute \src "libresoc.v:98747.5-98747.29" switch \initial - attribute \src "libresoc.v:97796.9-97796.17" + attribute \src "libresoc.v:98747.9-98747.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152504,18 +153900,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:97898.3-98000.6" - process $proc$libresoc.v:97898$3960 + attribute \src "libresoc.v:98849.3-98951.6" + process $proc$libresoc.v:98849$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:97899.5-97899.29" + attribute \src "libresoc.v:98850.5-98850.29" switch \initial - attribute \src "libresoc.v:97899.9-97899.17" + attribute \src "libresoc.v:98850.9-98850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -152653,157 +154049,161 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98006.1-98666.10" +attribute \src "libresoc.v:98957.1-99637.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:98605.3-98614.6" + attribute \src "libresoc.v:99576.3-99585.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98615.3-98624.6" + attribute \src "libresoc.v:99586.3-99595.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98485.3-98494.6" + attribute \src "libresoc.v:99456.3-99465.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98525.3-98534.6" + attribute \src "libresoc.v:99496.3-99505.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98355.3-98364.6" + attribute \src "libresoc.v:99316.3-99325.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98365.3-98374.6" + attribute \src "libresoc.v:99326.3-99335.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98475.3-98484.6" + attribute \src "libresoc.v:99446.3-99455.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98515.3-98524.6" + attribute \src "libresoc.v:99486.3-99495.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98565.3-98574.6" + attribute \src "libresoc.v:99526.3-99535.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98345.3-98354.6" + attribute \src "libresoc.v:99306.3-99315.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98625.3-98634.6" + attribute \src "libresoc.v:99596.3-99605.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98635.3-98644.6" + attribute \src "libresoc.v:99606.3-99615.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98645.3-98654.6" + attribute \src "libresoc.v:99616.3-99625.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98455.3-98464.6" + attribute \src "libresoc.v:99416.3-99425.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98495.3-98504.6" + attribute \src "libresoc.v:99466.3-99475.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98505.3-98514.6" + attribute \src "libresoc.v:99476.3-99485.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98555.3-98564.6" + attribute \src "libresoc.v:99536.3-99545.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98435.3-98444.6" + attribute \src "libresoc.v:99406.3-99415.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98585.3-98594.6" + attribute \src "libresoc.v:99556.3-99565.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98655.3-98664.6" + attribute \src "libresoc.v:99626.3-99635.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98465.3-98474.6" + attribute \src "libresoc.v:99436.3-99445.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98545.3-98554.6" + attribute \src "libresoc.v:99516.3-99525.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98595.3-98604.6" + attribute \src "libresoc.v:99566.3-99575.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98575.3-98584.6" + attribute \src "libresoc.v:99546.3-99555.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98535.3-98544.6" + attribute \src "libresoc.v:99506.3-99515.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98415.3-98424.6" + attribute \src "libresoc.v:99386.3-99395.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98425.3-98434.6" + attribute \src "libresoc.v:99396.3-99405.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98375.3-98384.6" + attribute \src "libresoc.v:99336.3-99345.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98385.3-98394.6" + attribute \src "libresoc.v:99346.3-99355.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98395.3-98404.6" + attribute \src "libresoc.v:99356.3-99365.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98405.3-98414.6" + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98445.3-98454.6" + attribute \src "libresoc.v:99426.3-99435.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98007.7-98007.20" + attribute \src "libresoc.v:98958.7-98958.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98605.3-98614.6" + attribute \src "libresoc.v:99576.3-99585.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98615.3-98624.6" + attribute \src "libresoc.v:99586.3-99595.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98485.3-98494.6" + attribute \src "libresoc.v:99456.3-99465.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98525.3-98534.6" + attribute \src "libresoc.v:99496.3-99505.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98355.3-98364.6" + attribute \src "libresoc.v:99316.3-99325.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98365.3-98374.6" + attribute \src "libresoc.v:99326.3-99335.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98475.3-98484.6" + attribute \src "libresoc.v:99446.3-99455.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98515.3-98524.6" + attribute \src "libresoc.v:99486.3-99495.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98565.3-98574.6" + attribute \src "libresoc.v:99526.3-99535.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98345.3-98354.6" + attribute \src "libresoc.v:99306.3-99315.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98625.3-98634.6" + attribute \src "libresoc.v:99596.3-99605.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98635.3-98644.6" + attribute \src "libresoc.v:99606.3-99615.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98645.3-98654.6" + attribute \src "libresoc.v:99616.3-99625.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98455.3-98464.6" + attribute \src "libresoc.v:99416.3-99425.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98495.3-98504.6" + attribute \src "libresoc.v:99466.3-99475.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98505.3-98514.6" + attribute \src "libresoc.v:99476.3-99485.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98555.3-98564.6" + attribute \src "libresoc.v:99536.3-99545.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98435.3-98444.6" + attribute \src "libresoc.v:99406.3-99415.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98585.3-98594.6" + attribute \src "libresoc.v:99556.3-99565.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98655.3-98664.6" + attribute \src "libresoc.v:99626.3-99635.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98465.3-98474.6" + attribute \src "libresoc.v:99436.3-99445.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98545.3-98554.6" + attribute \src "libresoc.v:99516.3-99525.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98595.3-98604.6" + attribute \src "libresoc.v:99566.3-99575.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98575.3-98584.6" + attribute \src "libresoc.v:99546.3-99555.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98535.3-98544.6" + attribute \src "libresoc.v:99506.3-99515.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98415.3-98424.6" + attribute \src "libresoc.v:99386.3-99395.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98425.3-98434.6" + attribute \src "libresoc.v:99396.3-99405.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98375.3-98384.6" + attribute \src "libresoc.v:99336.3-99345.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98385.3-98394.6" + attribute \src "libresoc.v:99346.3-99355.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98395.3-98404.6" + attribute \src "libresoc.v:99356.3-99365.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98405.3-98414.6" + attribute \src "libresoc.v:99376.3-99385.6" + wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99366.3-99375.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98445.3-98454.6" + attribute \src "libresoc.v:99426.3-99435.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub16_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub16_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub16_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -152813,7 +154213,7 @@ module \dec31_dec_sub16 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -152822,16 +154222,16 @@ module \dec31_dec_sub16 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub16_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -152863,7 +154263,7 @@ module \dec31_dec_sub16 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -152880,7 +154280,7 @@ module \dec31_dec_sub16 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -152888,7 +154288,7 @@ module \dec31_dec_sub16 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -152905,13 +154305,13 @@ module \dec31_dec_sub16 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -152988,46 +154388,46 @@ module \dec31_dec_sub16 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub16_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub16_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub16_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub16_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153035,8 +154435,8 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub16_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub16_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153044,8 +154444,8 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub16_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub16_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -153053,7 +154453,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub16_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153062,7 +154462,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub16_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153071,7 +154471,7 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub16_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -153080,41 +154480,50 @@ module \dec31_dec_sub16 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub16_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub16_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub16_upd - attribute \src "libresoc.v:98007.7-98007.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub16_upd + attribute \src "libresoc.v:98958.7-98958.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98007.7-98007.20" - process $proc$libresoc.v:98007$3994 + attribute \src "libresoc.v:98958.7-98958.20" + process $proc$libresoc.v:98958$4020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:98345.3-98354.6" - process $proc$libresoc.v:98345$3962 + attribute \src "libresoc.v:99306.3-99315.6" + process $proc$libresoc.v:99306$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:98346.5-98346.29" + attribute \src "libresoc.v:99307.5-99307.29" switch \initial - attribute \src "libresoc.v:98346.9-98346.17" + attribute \src "libresoc.v:99307.9-99307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153126,18 +154535,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:98355.3-98364.6" - process $proc$libresoc.v:98355$3963 + attribute \src "libresoc.v:99316.3-99325.6" + process $proc$libresoc.v:99316$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:98356.5-98356.29" + attribute \src "libresoc.v:99317.5-99317.29" switch \initial - attribute \src "libresoc.v:98356.9-98356.17" + attribute \src "libresoc.v:99317.9-99317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153149,18 +154558,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:98365.3-98374.6" - process $proc$libresoc.v:98365$3964 + attribute \src "libresoc.v:99326.3-99335.6" + process $proc$libresoc.v:99326$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:98366.5-98366.29" + attribute \src "libresoc.v:99327.5-99327.29" switch \initial - attribute \src "libresoc.v:98366.9-98366.17" + attribute \src "libresoc.v:99327.9-99327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153172,18 +154581,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:98375.3-98384.6" - process $proc$libresoc.v:98375$3965 + attribute \src "libresoc.v:99336.3-99345.6" + process $proc$libresoc.v:99336$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:98376.5-98376.29" + attribute \src "libresoc.v:99337.5-99337.29" switch \initial - attribute \src "libresoc.v:98376.9-98376.17" + attribute \src "libresoc.v:99337.9-99337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153195,18 +154604,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:98385.3-98394.6" - process $proc$libresoc.v:98385$3966 + attribute \src "libresoc.v:99346.3-99355.6" + process $proc$libresoc.v:99346$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:98386.5-98386.29" + attribute \src "libresoc.v:99347.5-99347.29" switch \initial - attribute \src "libresoc.v:98386.9-98386.17" + attribute \src "libresoc.v:99347.9-99347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153218,18 +154627,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:98395.3-98404.6" - process $proc$libresoc.v:98395$3967 + attribute \src "libresoc.v:99356.3-99365.6" + process $proc$libresoc.v:99356$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:98396.5-98396.29" + attribute \src "libresoc.v:99357.5-99357.29" switch \initial - attribute \src "libresoc.v:98396.9-98396.17" + attribute \src "libresoc.v:99357.9-99357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153241,18 +154650,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:98405.3-98414.6" - process $proc$libresoc.v:98405$3968 + attribute \src "libresoc.v:99366.3-99375.6" + process $proc$libresoc.v:99366$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:98406.5-98406.29" + attribute \src "libresoc.v:99367.5-99367.29" switch \initial - attribute \src "libresoc.v:98406.9-98406.17" + attribute \src "libresoc.v:99367.9-99367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153264,18 +154673,41 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:98415.3-98424.6" - process $proc$libresoc.v:98415$3969 + attribute \src "libresoc.v:99376.3-99385.6" + process $proc$libresoc.v:99376$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] + attribute \src "libresoc.v:99377.5-99377.29" + switch \initial + attribute \src "libresoc.v:99377.9-99377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] + end + attribute \src "libresoc.v:99386.3-99395.6" + process $proc$libresoc.v:99386$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:98416.5-98416.29" + attribute \src "libresoc.v:99387.5-99387.29" switch \initial - attribute \src "libresoc.v:98416.9-98416.17" + attribute \src "libresoc.v:99387.9-99387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153287,18 +154719,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:98425.3-98434.6" - process $proc$libresoc.v:98425$3970 + attribute \src "libresoc.v:99396.3-99405.6" + process $proc$libresoc.v:99396$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:98426.5-98426.29" + attribute \src "libresoc.v:99397.5-99397.29" switch \initial - attribute \src "libresoc.v:98426.9-98426.17" + attribute \src "libresoc.v:99397.9-99397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153310,18 +154742,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:98435.3-98444.6" - process $proc$libresoc.v:98435$3971 + attribute \src "libresoc.v:99406.3-99415.6" + process $proc$libresoc.v:99406$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:98436.5-98436.29" + attribute \src "libresoc.v:99407.5-99407.29" switch \initial - attribute \src "libresoc.v:98436.9-98436.17" + attribute \src "libresoc.v:99407.9-99407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153333,64 +154765,64 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:98445.3-98454.6" - process $proc$libresoc.v:98445$3972 + attribute \src "libresoc.v:99416.3-99425.6" + process $proc$libresoc.v:99416$3998 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98446.5-98446.29" + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:99417.5-99417.29" switch \initial - attribute \src "libresoc.v:98446.9-98446.17" + attribute \src "libresoc.v:99417.9-99417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:98455.3-98464.6" - process $proc$libresoc.v:98455$3973 + attribute \src "libresoc.v:99426.3-99435.6" + process $proc$libresoc.v:99426$3999 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:98456.5-98456.29" + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:99427.5-99427.29" switch \initial - attribute \src "libresoc.v:98456.9-98456.17" + attribute \src "libresoc.v:99427.9-99427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub16_upd[1:0] 2'00 end sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:98465.3-98474.6" - process $proc$libresoc.v:98465$3974 + attribute \src "libresoc.v:99436.3-99445.6" + process $proc$libresoc.v:99436$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:98466.5-98466.29" + attribute \src "libresoc.v:99437.5-99437.29" switch \initial - attribute \src "libresoc.v:98466.9-98466.17" + attribute \src "libresoc.v:99437.9-99437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153402,18 +154834,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:98475.3-98484.6" - process $proc$libresoc.v:98475$3975 + attribute \src "libresoc.v:99446.3-99455.6" + process $proc$libresoc.v:99446$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:98476.5-98476.29" + attribute \src "libresoc.v:99447.5-99447.29" switch \initial - attribute \src "libresoc.v:98476.9-98476.17" + attribute \src "libresoc.v:99447.9-99447.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153425,18 +154857,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:98485.3-98494.6" - process $proc$libresoc.v:98485$3976 + attribute \src "libresoc.v:99456.3-99465.6" + process $proc$libresoc.v:99456$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:98486.5-98486.29" + attribute \src "libresoc.v:99457.5-99457.29" switch \initial - attribute \src "libresoc.v:98486.9-98486.17" + attribute \src "libresoc.v:99457.9-99457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153448,18 +154880,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:98495.3-98504.6" - process $proc$libresoc.v:98495$3977 + attribute \src "libresoc.v:99466.3-99475.6" + process $proc$libresoc.v:99466$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:98496.5-98496.29" + attribute \src "libresoc.v:99467.5-99467.29" switch \initial - attribute \src "libresoc.v:98496.9-98496.17" + attribute \src "libresoc.v:99467.9-99467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153471,18 +154903,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:98505.3-98514.6" - process $proc$libresoc.v:98505$3978 + attribute \src "libresoc.v:99476.3-99485.6" + process $proc$libresoc.v:99476$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:98506.5-98506.29" + attribute \src "libresoc.v:99477.5-99477.29" switch \initial - attribute \src "libresoc.v:98506.9-98506.17" + attribute \src "libresoc.v:99477.9-99477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153494,18 +154926,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:98515.3-98524.6" - process $proc$libresoc.v:98515$3979 + attribute \src "libresoc.v:99486.3-99495.6" + process $proc$libresoc.v:99486$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:98516.5-98516.29" + attribute \src "libresoc.v:99487.5-99487.29" switch \initial - attribute \src "libresoc.v:98516.9-98516.17" + attribute \src "libresoc.v:99487.9-99487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153517,18 +154949,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:98525.3-98534.6" - process $proc$libresoc.v:98525$3980 + attribute \src "libresoc.v:99496.3-99505.6" + process $proc$libresoc.v:99496$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:98526.5-98526.29" + attribute \src "libresoc.v:99497.5-99497.29" switch \initial - attribute \src "libresoc.v:98526.9-98526.17" + attribute \src "libresoc.v:99497.9-99497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153540,18 +154972,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:98535.3-98544.6" - process $proc$libresoc.v:98535$3981 + attribute \src "libresoc.v:99506.3-99515.6" + process $proc$libresoc.v:99506$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:98536.5-98536.29" + attribute \src "libresoc.v:99507.5-99507.29" switch \initial - attribute \src "libresoc.v:98536.9-98536.17" + attribute \src "libresoc.v:99507.9-99507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153563,18 +154995,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:98545.3-98554.6" - process $proc$libresoc.v:98545$3982 + attribute \src "libresoc.v:99516.3-99525.6" + process $proc$libresoc.v:99516$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:98546.5-98546.29" + attribute \src "libresoc.v:99517.5-99517.29" switch \initial - attribute \src "libresoc.v:98546.9-98546.17" + attribute \src "libresoc.v:99517.9-99517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153586,64 +155018,64 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:98555.3-98564.6" - process $proc$libresoc.v:98555$3983 + attribute \src "libresoc.v:99526.3-99535.6" + process $proc$libresoc.v:99526$4009 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:98556.5-98556.29" + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:99527.5-99527.29" switch \initial - attribute \src "libresoc.v:98556.9-98556.17" + attribute \src "libresoc.v:99527.9-99527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_form[4:0] 5'01010 case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub16_form[4:0] 5'00000 end sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:98565.3-98574.6" - process $proc$libresoc.v:98565$3984 + attribute \src "libresoc.v:99536.3-99545.6" + process $proc$libresoc.v:99536$4010 assign { } { } assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:98566.5-98566.29" + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:99537.5-99537.29" switch \initial - attribute \src "libresoc.v:98566.9-98566.17" + attribute \src "libresoc.v:99537.9-99537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:98575.3-98584.6" - process $proc$libresoc.v:98575$3985 + attribute \src "libresoc.v:99546.3-99555.6" + process $proc$libresoc.v:99546$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:98576.5-98576.29" + attribute \src "libresoc.v:99547.5-99547.29" switch \initial - attribute \src "libresoc.v:98576.9-98576.17" + attribute \src "libresoc.v:99547.9-99547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153655,18 +155087,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:98585.3-98594.6" - process $proc$libresoc.v:98585$3986 + attribute \src "libresoc.v:99556.3-99565.6" + process $proc$libresoc.v:99556$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:98586.5-98586.29" + attribute \src "libresoc.v:99557.5-99557.29" switch \initial - attribute \src "libresoc.v:98586.9-98586.17" + attribute \src "libresoc.v:99557.9-99557.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153678,18 +155110,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:98595.3-98604.6" - process $proc$libresoc.v:98595$3987 + attribute \src "libresoc.v:99566.3-99575.6" + process $proc$libresoc.v:99566$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:98596.5-98596.29" + attribute \src "libresoc.v:99567.5-99567.29" switch \initial - attribute \src "libresoc.v:98596.9-98596.17" + attribute \src "libresoc.v:99567.9-99567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153701,18 +155133,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:98605.3-98614.6" - process $proc$libresoc.v:98605$3988 + attribute \src "libresoc.v:99576.3-99585.6" + process $proc$libresoc.v:99576$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:98606.5-98606.29" + attribute \src "libresoc.v:99577.5-99577.29" switch \initial - attribute \src "libresoc.v:98606.9-98606.17" + attribute \src "libresoc.v:99577.9-99577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153724,18 +155156,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:98615.3-98624.6" - process $proc$libresoc.v:98615$3989 + attribute \src "libresoc.v:99586.3-99595.6" + process $proc$libresoc.v:99586$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:98616.5-98616.29" + attribute \src "libresoc.v:99587.5-99587.29" switch \initial - attribute \src "libresoc.v:98616.9-98616.17" + attribute \src "libresoc.v:99587.9-99587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153747,18 +155179,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:98625.3-98634.6" - process $proc$libresoc.v:98625$3990 + attribute \src "libresoc.v:99596.3-99605.6" + process $proc$libresoc.v:99596$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:98626.5-98626.29" + attribute \src "libresoc.v:99597.5-99597.29" switch \initial - attribute \src "libresoc.v:98626.9-98626.17" + attribute \src "libresoc.v:99597.9-99597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153770,18 +155202,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:98635.3-98644.6" - process $proc$libresoc.v:98635$3991 + attribute \src "libresoc.v:99606.3-99615.6" + process $proc$libresoc.v:99606$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:98636.5-98636.29" + attribute \src "libresoc.v:99607.5-99607.29" switch \initial - attribute \src "libresoc.v:98636.9-98636.17" + attribute \src "libresoc.v:99607.9-99607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153793,18 +155225,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:98645.3-98654.6" - process $proc$libresoc.v:98645$3992 + attribute \src "libresoc.v:99616.3-99625.6" + process $proc$libresoc.v:99616$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:98646.5-98646.29" + attribute \src "libresoc.v:99617.5-99617.29" switch \initial - attribute \src "libresoc.v:98646.9-98646.17" + attribute \src "libresoc.v:99617.9-99617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153816,18 +155248,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:98655.3-98664.6" - process $proc$libresoc.v:98655$3993 + attribute \src "libresoc.v:99626.3-99635.6" + process $proc$libresoc.v:99626$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:98656.5-98656.29" + attribute \src "libresoc.v:99627.5-99627.29" switch \initial - attribute \src "libresoc.v:98656.9-98656.17" + attribute \src "libresoc.v:99627.9-99627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -153841,157 +155273,161 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98670.1-99714.10" +attribute \src "libresoc.v:99641.1-100717.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:99581.3-99602.6" + attribute \src "libresoc.v:100584.3-100605.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99603.3-99624.6" + attribute \src "libresoc.v:100606.3-100627.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99317.3-99338.6" + attribute \src "libresoc.v:100320.3-100341.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99426.6" + attribute \src "libresoc.v:100408.3-100429.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99031.3-99052.6" + attribute \src "libresoc.v:100012.3-100033.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99053.3-99074.6" + attribute \src "libresoc.v:100034.3-100055.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99295.3-99316.6" + attribute \src "libresoc.v:100298.3-100319.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99383.3-99404.6" + attribute \src "libresoc.v:100386.3-100407.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99493.3-99514.6" + attribute \src "libresoc.v:100474.3-100495.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99009.3-99030.6" + attribute \src "libresoc.v:99990.3-100011.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99625.3-99646.6" + attribute \src "libresoc.v:100628.3-100649.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99647.3-99668.6" + attribute \src "libresoc.v:100650.3-100671.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99669.3-99690.6" + attribute \src "libresoc.v:100672.3-100693.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99251.3-99272.6" + attribute \src "libresoc.v:100232.3-100253.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99339.3-99360.6" + attribute \src "libresoc.v:100342.3-100363.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99361.3-99382.6" + attribute \src "libresoc.v:100364.3-100385.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99471.3-99492.6" + attribute \src "libresoc.v:100496.3-100517.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99207.3-99228.6" + attribute \src "libresoc.v:100210.3-100231.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99537.3-99558.6" + attribute \src "libresoc.v:100540.3-100561.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99691.3-99712.6" + attribute \src "libresoc.v:100694.3-100715.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99273.3-99294.6" + attribute \src "libresoc.v:100276.3-100297.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99449.3-99470.6" + attribute \src "libresoc.v:100452.3-100473.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99559.3-99580.6" + attribute \src "libresoc.v:100562.3-100583.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99515.3-99536.6" + attribute \src "libresoc.v:100518.3-100539.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99427.3-99448.6" + attribute \src "libresoc.v:100430.3-100451.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99163.3-99184.6" + attribute \src "libresoc.v:100166.3-100187.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99185.3-99206.6" + attribute \src "libresoc.v:100188.3-100209.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99075.3-99096.6" + attribute \src "libresoc.v:100056.3-100077.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99097.3-99118.6" + attribute \src "libresoc.v:100078.3-100099.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99119.3-99140.6" + attribute \src "libresoc.v:100100.3-100121.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99141.3-99162.6" + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99229.3-99250.6" + attribute \src "libresoc.v:100254.3-100275.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:98671.7-98671.20" + attribute \src "libresoc.v:99642.7-99642.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99581.3-99602.6" + attribute \src "libresoc.v:100584.3-100605.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99603.3-99624.6" + attribute \src "libresoc.v:100606.3-100627.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99317.3-99338.6" + attribute \src "libresoc.v:100320.3-100341.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99426.6" + attribute \src "libresoc.v:100408.3-100429.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99031.3-99052.6" + attribute \src "libresoc.v:100012.3-100033.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99053.3-99074.6" + attribute \src "libresoc.v:100034.3-100055.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99295.3-99316.6" + attribute \src "libresoc.v:100298.3-100319.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99383.3-99404.6" + attribute \src "libresoc.v:100386.3-100407.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99493.3-99514.6" + attribute \src "libresoc.v:100474.3-100495.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99009.3-99030.6" + attribute \src "libresoc.v:99990.3-100011.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99625.3-99646.6" + attribute \src "libresoc.v:100628.3-100649.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99647.3-99668.6" + attribute \src "libresoc.v:100650.3-100671.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99669.3-99690.6" + attribute \src "libresoc.v:100672.3-100693.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99251.3-99272.6" + attribute \src "libresoc.v:100232.3-100253.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99339.3-99360.6" + attribute \src "libresoc.v:100342.3-100363.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99361.3-99382.6" + attribute \src "libresoc.v:100364.3-100385.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99471.3-99492.6" + attribute \src "libresoc.v:100496.3-100517.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99207.3-99228.6" + attribute \src "libresoc.v:100210.3-100231.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99537.3-99558.6" + attribute \src "libresoc.v:100540.3-100561.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99691.3-99712.6" + attribute \src "libresoc.v:100694.3-100715.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99273.3-99294.6" + attribute \src "libresoc.v:100276.3-100297.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99449.3-99470.6" + attribute \src "libresoc.v:100452.3-100473.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99559.3-99580.6" + attribute \src "libresoc.v:100562.3-100583.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99515.3-99536.6" + attribute \src "libresoc.v:100518.3-100539.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99427.3-99448.6" + attribute \src "libresoc.v:100430.3-100451.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99163.3-99184.6" + attribute \src "libresoc.v:100166.3-100187.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99185.3-99206.6" + attribute \src "libresoc.v:100188.3-100209.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99075.3-99096.6" + attribute \src "libresoc.v:100056.3-100077.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99097.3-99118.6" + attribute \src "libresoc.v:100078.3-100099.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99119.3-99140.6" + attribute \src "libresoc.v:100100.3-100121.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99141.3-99162.6" + attribute \src "libresoc.v:100144.3-100165.6" + wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100122.3-100143.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99229.3-99250.6" + attribute \src "libresoc.v:100254.3-100275.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub18_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub18_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub18_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -154001,7 +155437,7 @@ module \dec31_dec_sub18 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -154010,16 +155446,16 @@ module \dec31_dec_sub18 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub18_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -154051,7 +155487,7 @@ module \dec31_dec_sub18 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -154068,7 +155504,7 @@ module \dec31_dec_sub18 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -154076,7 +155512,7 @@ module \dec31_dec_sub18 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -154093,13 +155529,13 @@ module \dec31_dec_sub18 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -154176,46 +155612,46 @@ module \dec31_dec_sub18 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub18_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub18_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub18_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154223,8 +155659,8 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub18_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub18_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154232,8 +155668,8 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub18_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub18_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -154241,7 +155677,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub18_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154250,7 +155686,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub18_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154259,7 +155695,7 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub18_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -154268,80 +155704,42 @@ module \dec31_dec_sub18 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub18_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub18_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub18_upd - attribute \src "libresoc.v:98671.7-98671.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub18_upd + attribute \src "libresoc.v:99642.7-99642.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98671.7-98671.20" - process $proc$libresoc.v:98671$4027 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99009.3-99030.6" - process $proc$libresoc.v:99009$3995 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99010.5-99010.29" - switch \initial - attribute \src "libresoc.v:99010.9-99010.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - case - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] - end - attribute \src "libresoc.v:99031.3-99052.6" - process $proc$libresoc.v:99031$3996 + attribute \src "libresoc.v:100012.3-100033.6" + process $proc$libresoc.v:100012$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:99032.5-99032.29" + attribute \src "libresoc.v:100013.5-100013.29" switch \initial - attribute \src "libresoc.v:99032.9-99032.17" + attribute \src "libresoc.v:100013.9-100013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154369,18 +155767,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:99053.3-99074.6" - process $proc$libresoc.v:99053$3997 + attribute \src "libresoc.v:100034.3-100055.6" + process $proc$libresoc.v:100034$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:99054.5-99054.29" + attribute \src "libresoc.v:100035.5-100035.29" switch \initial - attribute \src "libresoc.v:99054.9-99054.17" + attribute \src "libresoc.v:100035.9-100035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154408,18 +155806,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:99075.3-99096.6" - process $proc$libresoc.v:99075$3998 + attribute \src "libresoc.v:100056.3-100077.6" + process $proc$libresoc.v:100056$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:99076.5-99076.29" + attribute \src "libresoc.v:100057.5-100057.29" switch \initial - attribute \src "libresoc.v:99076.9-99076.17" + attribute \src "libresoc.v:100057.9-100057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154447,18 +155845,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:99097.3-99118.6" - process $proc$libresoc.v:99097$3999 + attribute \src "libresoc.v:100078.3-100099.6" + process $proc$libresoc.v:100078$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:99098.5-99098.29" + attribute \src "libresoc.v:100079.5-100079.29" switch \initial - attribute \src "libresoc.v:99098.9-99098.17" + attribute \src "libresoc.v:100079.9-100079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154486,18 +155884,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:99119.3-99140.6" - process $proc$libresoc.v:99119$4000 + attribute \src "libresoc.v:100100.3-100121.6" + process $proc$libresoc.v:100100$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:99120.5-99120.29" + attribute \src "libresoc.v:100101.5-100101.29" switch \initial - attribute \src "libresoc.v:99120.9-99120.17" + attribute \src "libresoc.v:100101.9-100101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154525,18 +155923,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:99141.3-99162.6" - process $proc$libresoc.v:99141$4001 + attribute \src "libresoc.v:100122.3-100143.6" + process $proc$libresoc.v:100122$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:99142.5-99142.29" + attribute \src "libresoc.v:100123.5-100123.29" switch \initial - attribute \src "libresoc.v:99142.9-99142.17" + attribute \src "libresoc.v:100123.9-100123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154564,18 +155962,57 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:99163.3-99184.6" - process $proc$libresoc.v:99163$4002 + attribute \src "libresoc.v:100144.3-100165.6" + process $proc$libresoc.v:100144$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] + attribute \src "libresoc.v:100145.5-100145.29" + switch \initial + attribute \src "libresoc.v:100145.9-100145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] + end + attribute \src "libresoc.v:100166.3-100187.6" + process $proc$libresoc.v:100166$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:99164.5-99164.29" + attribute \src "libresoc.v:100167.5-100167.29" switch \initial - attribute \src "libresoc.v:99164.9-99164.17" + attribute \src "libresoc.v:100167.9-100167.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154603,18 +156040,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:99185.3-99206.6" - process $proc$libresoc.v:99185$4003 + attribute \src "libresoc.v:100188.3-100209.6" + process $proc$libresoc.v:100188$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:99186.5-99186.29" + attribute \src "libresoc.v:100189.5-100189.29" switch \initial - attribute \src "libresoc.v:99186.9-99186.17" + attribute \src "libresoc.v:100189.9-100189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154642,18 +156079,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:99207.3-99228.6" - process $proc$libresoc.v:99207$4004 + attribute \src "libresoc.v:100210.3-100231.6" + process $proc$libresoc.v:100210$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:99208.5-99208.29" + attribute \src "libresoc.v:100211.5-100211.29" switch \initial - attribute \src "libresoc.v:99208.9-99208.17" + attribute \src "libresoc.v:100211.9-100211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154681,96 +156118,96 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:99229.3-99250.6" - process $proc$libresoc.v:99229$4005 + attribute \src "libresoc.v:100232.3-100253.6" + process $proc$libresoc.v:100232$4032 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:99230.5-99230.29" + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:100233.5-100233.29" switch \initial - attribute \src "libresoc.v:99230.9-99230.17" + attribute \src "libresoc.v:100233.9-100233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:99251.3-99272.6" - process $proc$libresoc.v:99251$4006 + attribute \src "libresoc.v:100254.3-100275.6" + process $proc$libresoc.v:100254$4033 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:99252.5-99252.29" + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:100255.5-100255.29" switch \initial - attribute \src "libresoc.v:99252.9-99252.17" + attribute \src "libresoc.v:100255.9-100255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub18_upd[1:0] 2'00 end sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:99273.3-99294.6" - process $proc$libresoc.v:99273$4007 + attribute \src "libresoc.v:100276.3-100297.6" + process $proc$libresoc.v:100276$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:99274.5-99274.29" + attribute \src "libresoc.v:100277.5-100277.29" switch \initial - attribute \src "libresoc.v:99274.9-99274.17" + attribute \src "libresoc.v:100277.9-100277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154798,18 +156235,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:99295.3-99316.6" - process $proc$libresoc.v:99295$4008 + attribute \src "libresoc.v:100298.3-100319.6" + process $proc$libresoc.v:100298$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:99296.5-99296.29" + attribute \src "libresoc.v:100299.5-100299.29" switch \initial - attribute \src "libresoc.v:99296.9-99296.17" + attribute \src "libresoc.v:100299.9-100299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154837,18 +156274,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:99317.3-99338.6" - process $proc$libresoc.v:99317$4009 + attribute \src "libresoc.v:100320.3-100341.6" + process $proc$libresoc.v:100320$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:99318.5-99318.29" + attribute \src "libresoc.v:100321.5-100321.29" switch \initial - attribute \src "libresoc.v:99318.9-99318.17" + attribute \src "libresoc.v:100321.9-100321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154876,18 +156313,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:99339.3-99360.6" - process $proc$libresoc.v:99339$4010 + attribute \src "libresoc.v:100342.3-100363.6" + process $proc$libresoc.v:100342$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:99340.5-99340.29" + attribute \src "libresoc.v:100343.5-100343.29" switch \initial - attribute \src "libresoc.v:99340.9-99340.17" + attribute \src "libresoc.v:100343.9-100343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154915,18 +156352,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:99361.3-99382.6" - process $proc$libresoc.v:99361$4011 + attribute \src "libresoc.v:100364.3-100385.6" + process $proc$libresoc.v:100364$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:99362.5-99362.29" + attribute \src "libresoc.v:100365.5-100365.29" switch \initial - attribute \src "libresoc.v:99362.9-99362.17" + attribute \src "libresoc.v:100365.9-100365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154954,18 +156391,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:99383.3-99404.6" - process $proc$libresoc.v:99383$4012 + attribute \src "libresoc.v:100386.3-100407.6" + process $proc$libresoc.v:100386$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:99384.5-99384.29" + attribute \src "libresoc.v:100387.5-100387.29" switch \initial - attribute \src "libresoc.v:99384.9-99384.17" + attribute \src "libresoc.v:100387.9-100387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -154993,18 +156430,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:99405.3-99426.6" - process $proc$libresoc.v:99405$4013 + attribute \src "libresoc.v:100408.3-100429.6" + process $proc$libresoc.v:100408$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:99406.5-99406.29" + attribute \src "libresoc.v:100409.5-100409.29" switch \initial - attribute \src "libresoc.v:99406.9-99406.17" + attribute \src "libresoc.v:100409.9-100409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155032,18 +156469,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:99427.3-99448.6" - process $proc$libresoc.v:99427$4014 + attribute \src "libresoc.v:100430.3-100451.6" + process $proc$libresoc.v:100430$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:99428.5-99428.29" + attribute \src "libresoc.v:100431.5-100431.29" switch \initial - attribute \src "libresoc.v:99428.9-99428.17" + attribute \src "libresoc.v:100431.9-100431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155071,18 +156508,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:99449.3-99470.6" - process $proc$libresoc.v:99449$4015 + attribute \src "libresoc.v:100452.3-100473.6" + process $proc$libresoc.v:100452$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:99450.5-99450.29" + attribute \src "libresoc.v:100453.5-100453.29" switch \initial - attribute \src "libresoc.v:99450.9-99450.17" + attribute \src "libresoc.v:100453.9-100453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155110,96 +156547,96 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:99471.3-99492.6" - process $proc$libresoc.v:99471$4016 + attribute \src "libresoc.v:100474.3-100495.6" + process $proc$libresoc.v:100474$4043 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:99472.5-99472.29" + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:100475.5-100475.29" switch \initial - attribute \src "libresoc.v:99472.9-99472.17" + attribute \src "libresoc.v:100475.9-100475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'01000 case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub18_form[4:0] 5'00000 end sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:99493.3-99514.6" - process $proc$libresoc.v:99493$4017 + attribute \src "libresoc.v:100496.3-100517.6" + process $proc$libresoc.v:100496$4044 assign { } { } assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99494.5-99494.29" + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:100497.5-100497.29" switch \initial - attribute \src "libresoc.v:99494.9-99494.17" + attribute \src "libresoc.v:100497.9-100497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:99515.3-99536.6" - process $proc$libresoc.v:99515$4018 + attribute \src "libresoc.v:100518.3-100539.6" + process $proc$libresoc.v:100518$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:99516.5-99516.29" + attribute \src "libresoc.v:100519.5-100519.29" switch \initial - attribute \src "libresoc.v:99516.9-99516.17" + attribute \src "libresoc.v:100519.9-100519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155227,18 +156664,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:99537.3-99558.6" - process $proc$libresoc.v:99537$4019 + attribute \src "libresoc.v:100540.3-100561.6" + process $proc$libresoc.v:100540$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:99538.5-99538.29" + attribute \src "libresoc.v:100541.5-100541.29" switch \initial - attribute \src "libresoc.v:99538.9-99538.17" + attribute \src "libresoc.v:100541.9-100541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155266,18 +156703,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:99559.3-99580.6" - process $proc$libresoc.v:99559$4020 + attribute \src "libresoc.v:100562.3-100583.6" + process $proc$libresoc.v:100562$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:99560.5-99560.29" + attribute \src "libresoc.v:100563.5-100563.29" switch \initial - attribute \src "libresoc.v:99560.9-99560.17" + attribute \src "libresoc.v:100563.9-100563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155305,18 +156742,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:99581.3-99602.6" - process $proc$libresoc.v:99581$4021 + attribute \src "libresoc.v:100584.3-100605.6" + process $proc$libresoc.v:100584$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:99582.5-99582.29" + attribute \src "libresoc.v:100585.5-100585.29" switch \initial - attribute \src "libresoc.v:99582.9-99582.17" + attribute \src "libresoc.v:100585.9-100585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155344,18 +156781,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:99603.3-99624.6" - process $proc$libresoc.v:99603$4022 + attribute \src "libresoc.v:100606.3-100627.6" + process $proc$libresoc.v:100606$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:99604.5-99604.29" + attribute \src "libresoc.v:100607.5-100607.29" switch \initial - attribute \src "libresoc.v:99604.9-99604.17" + attribute \src "libresoc.v:100607.9-100607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155383,18 +156820,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:99625.3-99646.6" - process $proc$libresoc.v:99625$4023 + attribute \src "libresoc.v:100628.3-100649.6" + process $proc$libresoc.v:100628$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:99626.5-99626.29" + attribute \src "libresoc.v:100629.5-100629.29" switch \initial - attribute \src "libresoc.v:99626.9-99626.17" + attribute \src "libresoc.v:100629.9-100629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155422,18 +156859,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:99647.3-99668.6" - process $proc$libresoc.v:99647$4024 + attribute \src "libresoc.v:100650.3-100671.6" + process $proc$libresoc.v:100650$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:99648.5-99648.29" + attribute \src "libresoc.v:100651.5-100651.29" switch \initial - attribute \src "libresoc.v:99648.9-99648.17" + attribute \src "libresoc.v:100651.9-100651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155461,18 +156898,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:99669.3-99690.6" - process $proc$libresoc.v:99669$4025 + attribute \src "libresoc.v:100672.3-100693.6" + process $proc$libresoc.v:100672$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:99670.5-99670.29" + attribute \src "libresoc.v:100673.5-100673.29" switch \initial - attribute \src "libresoc.v:99670.9-99670.17" + attribute \src "libresoc.v:100673.9-100673.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155500,18 +156937,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:99691.3-99712.6" - process $proc$libresoc.v:99691$4026 + attribute \src "libresoc.v:100694.3-100715.6" + process $proc$libresoc.v:100694$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:99692.5-99692.29" + attribute \src "libresoc.v:100695.5-100695.29" switch \initial - attribute \src "libresoc.v:99692.9-99692.17" + attribute \src "libresoc.v:100695.9-100695.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -155539,159 +156976,210 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end + attribute \src "libresoc.v:99642.7-99642.20" + process $proc$libresoc.v:99642$4054 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99990.3-100011.6" + process $proc$libresoc.v:99990$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:99991.5-99991.29" + switch \initial + attribute \src "libresoc.v:99991.9-99991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + case + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99718.1-100666.10" +attribute \src "libresoc.v:100721.1-101698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:100551.3-100569.6" + attribute \src "libresoc.v:101583.3-101601.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100570.3-100588.6" + attribute \src "libresoc.v:101602.3-101620.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100323.3-100341.6" + attribute \src "libresoc.v:101355.3-101373.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100399.3-100417.6" + attribute \src "libresoc.v:101431.3-101449.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100076.3-100094.6" + attribute \src "libresoc.v:101089.3-101107.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100095.3-100113.6" + attribute \src "libresoc.v:101108.3-101126.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100304.3-100322.6" + attribute \src "libresoc.v:101336.3-101354.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100380.3-100398.6" + attribute \src "libresoc.v:101412.3-101430.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100475.3-100493.6" + attribute \src "libresoc.v:101488.3-101506.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100057.3-100075.6" + attribute \src "libresoc.v:101070.3-101088.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100589.3-100607.6" + attribute \src "libresoc.v:101621.3-101639.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100608.3-100626.6" + attribute \src "libresoc.v:101640.3-101658.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100627.3-100645.6" + attribute \src "libresoc.v:101659.3-101677.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100266.3-100284.6" + attribute \src "libresoc.v:101279.3-101297.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100360.6" + attribute \src "libresoc.v:101374.3-101392.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100361.3-100379.6" + attribute \src "libresoc.v:101393.3-101411.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100456.3-100474.6" + attribute \src "libresoc.v:101507.3-101525.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100228.3-100246.6" + attribute \src "libresoc.v:101260.3-101278.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100513.3-100531.6" + attribute \src "libresoc.v:101545.3-101563.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100646.3-100664.6" + attribute \src "libresoc.v:101678.3-101696.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100285.3-100303.6" + attribute \src "libresoc.v:101317.3-101335.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100437.3-100455.6" + attribute \src "libresoc.v:101469.3-101487.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100532.3-100550.6" + attribute \src "libresoc.v:101564.3-101582.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100494.3-100512.6" + attribute \src "libresoc.v:101526.3-101544.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100418.3-100436.6" + attribute \src "libresoc.v:101450.3-101468.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100190.3-100208.6" + attribute \src "libresoc.v:101222.3-101240.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100209.3-100227.6" + attribute \src "libresoc.v:101241.3-101259.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100114.3-100132.6" + attribute \src "libresoc.v:101127.3-101145.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100133.3-100151.6" + attribute \src "libresoc.v:101146.3-101164.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100152.3-100170.6" + attribute \src "libresoc.v:101165.3-101183.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100171.3-100189.6" + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100247.3-100265.6" + attribute \src "libresoc.v:101298.3-101316.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:99719.7-99719.20" + attribute \src "libresoc.v:100722.7-100722.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100551.3-100569.6" + attribute \src "libresoc.v:101583.3-101601.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100570.3-100588.6" + attribute \src "libresoc.v:101602.3-101620.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100323.3-100341.6" + attribute \src "libresoc.v:101355.3-101373.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100399.3-100417.6" + attribute \src "libresoc.v:101431.3-101449.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100076.3-100094.6" + attribute \src "libresoc.v:101089.3-101107.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100095.3-100113.6" + attribute \src "libresoc.v:101108.3-101126.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100304.3-100322.6" + attribute \src "libresoc.v:101336.3-101354.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100380.3-100398.6" + attribute \src "libresoc.v:101412.3-101430.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100475.3-100493.6" + attribute \src "libresoc.v:101488.3-101506.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100057.3-100075.6" + attribute \src "libresoc.v:101070.3-101088.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100589.3-100607.6" + attribute \src "libresoc.v:101621.3-101639.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100608.3-100626.6" + attribute \src "libresoc.v:101640.3-101658.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100627.3-100645.6" + attribute \src "libresoc.v:101659.3-101677.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100266.3-100284.6" + attribute \src "libresoc.v:101279.3-101297.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100360.6" + attribute \src "libresoc.v:101374.3-101392.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100361.3-100379.6" + attribute \src "libresoc.v:101393.3-101411.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100456.3-100474.6" + attribute \src "libresoc.v:101507.3-101525.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100228.3-100246.6" + attribute \src "libresoc.v:101260.3-101278.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100513.3-100531.6" + attribute \src "libresoc.v:101545.3-101563.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100646.3-100664.6" + attribute \src "libresoc.v:101678.3-101696.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100285.3-100303.6" + attribute \src "libresoc.v:101317.3-101335.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100437.3-100455.6" + attribute \src "libresoc.v:101469.3-101487.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100532.3-100550.6" + attribute \src "libresoc.v:101564.3-101582.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100494.3-100512.6" + attribute \src "libresoc.v:101526.3-101544.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100418.3-100436.6" + attribute \src "libresoc.v:101450.3-101468.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100190.3-100208.6" + attribute \src "libresoc.v:101222.3-101240.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100209.3-100227.6" + attribute \src "libresoc.v:101241.3-101259.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100114.3-100132.6" + attribute \src "libresoc.v:101127.3-101145.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100133.3-100151.6" + attribute \src "libresoc.v:101146.3-101164.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100152.3-100170.6" + attribute \src "libresoc.v:101165.3-101183.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100171.3-100189.6" + attribute \src "libresoc.v:101203.3-101221.6" + wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101184.3-101202.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100247.3-100265.6" + attribute \src "libresoc.v:101298.3-101316.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub19_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -155701,7 +157189,7 @@ module \dec31_dec_sub19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -155710,16 +157198,16 @@ module \dec31_dec_sub19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -155751,7 +157239,7 @@ module \dec31_dec_sub19 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -155768,7 +157256,7 @@ module \dec31_dec_sub19 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -155776,7 +157264,7 @@ module \dec31_dec_sub19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -155793,13 +157281,13 @@ module \dec31_dec_sub19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -155876,46 +157364,46 @@ module \dec31_dec_sub19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155923,8 +157411,8 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub19_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155932,8 +157420,8 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub19_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -155941,7 +157429,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155950,7 +157438,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155959,7 +157447,7 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -155968,33 +157456,50 @@ module \dec31_dec_sub19 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub19_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub19_upd - attribute \src "libresoc.v:99719.7-99719.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub19_upd + attribute \src "libresoc.v:100722.7-100722.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100057.3-100075.6" - process $proc$libresoc.v:100057$4028 + attribute \src "libresoc.v:100722.7-100722.20" + process $proc$libresoc.v:100722$4088 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101070.3-101088.6" + process $proc$libresoc.v:101070$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:100058.5-100058.29" + attribute \src "libresoc.v:101071.5-101071.29" switch \initial - attribute \src "libresoc.v:100058.9-100058.17" + attribute \src "libresoc.v:101071.9-101071.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156018,18 +157523,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:100076.3-100094.6" - process $proc$libresoc.v:100076$4029 + attribute \src "libresoc.v:101089.3-101107.6" + process $proc$libresoc.v:101089$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:100077.5-100077.29" + attribute \src "libresoc.v:101090.5-101090.29" switch \initial - attribute \src "libresoc.v:100077.9-100077.17" + attribute \src "libresoc.v:101090.9-101090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156053,18 +157558,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:100095.3-100113.6" - process $proc$libresoc.v:100095$4030 + attribute \src "libresoc.v:101108.3-101126.6" + process $proc$libresoc.v:101108$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:100096.5-100096.29" + attribute \src "libresoc.v:101109.5-101109.29" switch \initial - attribute \src "libresoc.v:100096.9-100096.17" + attribute \src "libresoc.v:101109.9-101109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156088,18 +157593,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:100114.3-100132.6" - process $proc$libresoc.v:100114$4031 + attribute \src "libresoc.v:101127.3-101145.6" + process $proc$libresoc.v:101127$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:100115.5-100115.29" + attribute \src "libresoc.v:101128.5-101128.29" switch \initial - attribute \src "libresoc.v:100115.9-100115.17" + attribute \src "libresoc.v:101128.9-101128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156123,18 +157628,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:100133.3-100151.6" - process $proc$libresoc.v:100133$4032 + attribute \src "libresoc.v:101146.3-101164.6" + process $proc$libresoc.v:101146$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:100134.5-100134.29" + attribute \src "libresoc.v:101147.5-101147.29" switch \initial - attribute \src "libresoc.v:100134.9-100134.17" + attribute \src "libresoc.v:101147.9-101147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156158,18 +157663,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:100152.3-100170.6" - process $proc$libresoc.v:100152$4033 + attribute \src "libresoc.v:101165.3-101183.6" + process $proc$libresoc.v:101165$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:100153.5-100153.29" + attribute \src "libresoc.v:101166.5-101166.29" switch \initial - attribute \src "libresoc.v:100153.9-100153.17" + attribute \src "libresoc.v:101166.9-101166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156193,18 +157698,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:100171.3-100189.6" - process $proc$libresoc.v:100171$4034 + attribute \src "libresoc.v:101184.3-101202.6" + process $proc$libresoc.v:101184$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:100172.5-100172.29" + attribute \src "libresoc.v:101185.5-101185.29" switch \initial - attribute \src "libresoc.v:100172.9-100172.17" + attribute \src "libresoc.v:101185.9-101185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156228,18 +157733,53 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:100190.3-100208.6" - process $proc$libresoc.v:100190$4035 + attribute \src "libresoc.v:101203.3-101221.6" + process $proc$libresoc.v:101203$4062 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] + attribute \src "libresoc.v:101204.5-101204.29" + switch \initial + attribute \src "libresoc.v:101204.9-101204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] + end + attribute \src "libresoc.v:101222.3-101240.6" + process $proc$libresoc.v:101222$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:100191.5-100191.29" + attribute \src "libresoc.v:101223.5-101223.29" switch \initial - attribute \src "libresoc.v:100191.9-100191.17" + attribute \src "libresoc.v:101223.9-101223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156263,18 +157803,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:100209.3-100227.6" - process $proc$libresoc.v:100209$4036 + attribute \src "libresoc.v:101241.3-101259.6" + process $proc$libresoc.v:101241$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:100210.5-100210.29" + attribute \src "libresoc.v:101242.5-101242.29" switch \initial - attribute \src "libresoc.v:100210.9-100210.17" + attribute \src "libresoc.v:101242.9-101242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156298,18 +157838,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:100228.3-100246.6" - process $proc$libresoc.v:100228$4037 + attribute \src "libresoc.v:101260.3-101278.6" + process $proc$libresoc.v:101260$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:100229.5-100229.29" + attribute \src "libresoc.v:101261.5-101261.29" switch \initial - attribute \src "libresoc.v:100229.9-100229.17" + attribute \src "libresoc.v:101261.9-101261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156333,88 +157873,88 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:100247.3-100265.6" - process $proc$libresoc.v:100247$4038 + attribute \src "libresoc.v:101279.3-101297.6" + process $proc$libresoc.v:101279$4066 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:100248.5-100248.29" + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:101280.5-101280.29" switch \initial - attribute \src "libresoc.v:100248.9-100248.17" + attribute \src "libresoc.v:101280.9-101280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:100266.3-100284.6" - process $proc$libresoc.v:100266$4039 + attribute \src "libresoc.v:101298.3-101316.6" + process $proc$libresoc.v:101298$4067 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:100267.5-100267.29" + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:101299.5-101299.29" switch \initial - attribute \src "libresoc.v:100267.9-100267.17" + attribute \src "libresoc.v:101299.9-101299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub19_upd[1:0] 2'00 end sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:100285.3-100303.6" - process $proc$libresoc.v:100285$4040 + attribute \src "libresoc.v:101317.3-101335.6" + process $proc$libresoc.v:101317$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:100286.5-100286.29" + attribute \src "libresoc.v:101318.5-101318.29" switch \initial - attribute \src "libresoc.v:100286.9-100286.17" + attribute \src "libresoc.v:101318.9-101318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156438,18 +157978,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:100304.3-100322.6" - process $proc$libresoc.v:100304$4041 + attribute \src "libresoc.v:101336.3-101354.6" + process $proc$libresoc.v:101336$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:100305.5-100305.29" + attribute \src "libresoc.v:101337.5-101337.29" switch \initial - attribute \src "libresoc.v:100305.9-100305.17" + attribute \src "libresoc.v:101337.9-101337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156473,18 +158013,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:100323.3-100341.6" - process $proc$libresoc.v:100323$4042 + attribute \src "libresoc.v:101355.3-101373.6" + process $proc$libresoc.v:101355$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:100324.5-100324.29" + attribute \src "libresoc.v:101356.5-101356.29" switch \initial - attribute \src "libresoc.v:100324.9-100324.17" + attribute \src "libresoc.v:101356.9-101356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156508,18 +158048,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:100342.3-100360.6" - process $proc$libresoc.v:100342$4043 + attribute \src "libresoc.v:101374.3-101392.6" + process $proc$libresoc.v:101374$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:100343.5-100343.29" + attribute \src "libresoc.v:101375.5-101375.29" switch \initial - attribute \src "libresoc.v:100343.9-100343.17" + attribute \src "libresoc.v:101375.9-101375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156543,18 +158083,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:100361.3-100379.6" - process $proc$libresoc.v:100361$4044 + attribute \src "libresoc.v:101393.3-101411.6" + process $proc$libresoc.v:101393$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:100362.5-100362.29" + attribute \src "libresoc.v:101394.5-101394.29" switch \initial - attribute \src "libresoc.v:100362.9-100362.17" + attribute \src "libresoc.v:101394.9-101394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156578,18 +158118,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:100380.3-100398.6" - process $proc$libresoc.v:100380$4045 + attribute \src "libresoc.v:101412.3-101430.6" + process $proc$libresoc.v:101412$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:100381.5-100381.29" + attribute \src "libresoc.v:101413.5-101413.29" switch \initial - attribute \src "libresoc.v:100381.9-100381.17" + attribute \src "libresoc.v:101413.9-101413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156613,18 +158153,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:100399.3-100417.6" - process $proc$libresoc.v:100399$4046 + attribute \src "libresoc.v:101431.3-101449.6" + process $proc$libresoc.v:101431$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:100400.5-100400.29" + attribute \src "libresoc.v:101432.5-101432.29" switch \initial - attribute \src "libresoc.v:100400.9-100400.17" + attribute \src "libresoc.v:101432.9-101432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156648,18 +158188,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:100418.3-100436.6" - process $proc$libresoc.v:100418$4047 + attribute \src "libresoc.v:101450.3-101468.6" + process $proc$libresoc.v:101450$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:100419.5-100419.29" + attribute \src "libresoc.v:101451.5-101451.29" switch \initial - attribute \src "libresoc.v:100419.9-100419.17" + attribute \src "libresoc.v:101451.9-101451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156683,18 +158223,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:100437.3-100455.6" - process $proc$libresoc.v:100437$4048 + attribute \src "libresoc.v:101469.3-101487.6" + process $proc$libresoc.v:101469$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:100438.5-100438.29" + attribute \src "libresoc.v:101470.5-101470.29" switch \initial - attribute \src "libresoc.v:100438.9-100438.17" + attribute \src "libresoc.v:101470.9-101470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156718,88 +158258,88 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:100456.3-100474.6" - process $proc$libresoc.v:100456$4049 + attribute \src "libresoc.v:101488.3-101506.6" + process $proc$libresoc.v:101488$4077 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:100457.5-100457.29" + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:101489.5-101489.29" switch \initial - attribute \src "libresoc.v:100457.9-100457.17" + attribute \src "libresoc.v:101489.9-101489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'01010 case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub19_form[4:0] 5'00000 end sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:100475.3-100493.6" - process $proc$libresoc.v:100475$4050 + attribute \src "libresoc.v:101507.3-101525.6" + process $proc$libresoc.v:101507$4078 assign { } { } assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:100476.5-100476.29" + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:101508.5-101508.29" switch \initial - attribute \src "libresoc.v:100476.9-100476.17" + attribute \src "libresoc.v:101508.9-101508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:100494.3-100512.6" - process $proc$libresoc.v:100494$4051 + attribute \src "libresoc.v:101526.3-101544.6" + process $proc$libresoc.v:101526$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:100495.5-100495.29" + attribute \src "libresoc.v:101527.5-101527.29" switch \initial - attribute \src "libresoc.v:100495.9-100495.17" + attribute \src "libresoc.v:101527.9-101527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156823,18 +158363,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:100513.3-100531.6" - process $proc$libresoc.v:100513$4052 + attribute \src "libresoc.v:101545.3-101563.6" + process $proc$libresoc.v:101545$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:100514.5-100514.29" + attribute \src "libresoc.v:101546.5-101546.29" switch \initial - attribute \src "libresoc.v:100514.9-100514.17" + attribute \src "libresoc.v:101546.9-101546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156858,18 +158398,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:100532.3-100550.6" - process $proc$libresoc.v:100532$4053 + attribute \src "libresoc.v:101564.3-101582.6" + process $proc$libresoc.v:101564$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:100533.5-100533.29" + attribute \src "libresoc.v:101565.5-101565.29" switch \initial - attribute \src "libresoc.v:100533.9-100533.17" + attribute \src "libresoc.v:101565.9-101565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156893,18 +158433,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:100551.3-100569.6" - process $proc$libresoc.v:100551$4054 + attribute \src "libresoc.v:101583.3-101601.6" + process $proc$libresoc.v:101583$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:100552.5-100552.29" + attribute \src "libresoc.v:101584.5-101584.29" switch \initial - attribute \src "libresoc.v:100552.9-100552.17" + attribute \src "libresoc.v:101584.9-101584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156928,18 +158468,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:100570.3-100588.6" - process $proc$libresoc.v:100570$4055 + attribute \src "libresoc.v:101602.3-101620.6" + process $proc$libresoc.v:101602$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:100571.5-100571.29" + attribute \src "libresoc.v:101603.5-101603.29" switch \initial - attribute \src "libresoc.v:100571.9-100571.17" + attribute \src "libresoc.v:101603.9-101603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156963,18 +158503,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:100589.3-100607.6" - process $proc$libresoc.v:100589$4056 + attribute \src "libresoc.v:101621.3-101639.6" + process $proc$libresoc.v:101621$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:100590.5-100590.29" + attribute \src "libresoc.v:101622.5-101622.29" switch \initial - attribute \src "libresoc.v:100590.9-100590.17" + attribute \src "libresoc.v:101622.9-101622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156998,18 +158538,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:100608.3-100626.6" - process $proc$libresoc.v:100608$4057 + attribute \src "libresoc.v:101640.3-101658.6" + process $proc$libresoc.v:101640$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:100609.5-100609.29" + attribute \src "libresoc.v:101641.5-101641.29" switch \initial - attribute \src "libresoc.v:100609.9-100609.17" + attribute \src "libresoc.v:101641.9-101641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157033,18 +158573,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:100627.3-100645.6" - process $proc$libresoc.v:100627$4058 + attribute \src "libresoc.v:101659.3-101677.6" + process $proc$libresoc.v:101659$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:100628.5-100628.29" + attribute \src "libresoc.v:101660.5-101660.29" switch \initial - attribute \src "libresoc.v:100628.9-100628.17" + attribute \src "libresoc.v:101660.9-101660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157068,18 +158608,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:100646.3-100664.6" - process $proc$libresoc.v:100646$4059 + attribute \src "libresoc.v:101678.3-101696.6" + process $proc$libresoc.v:101678$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:100647.5-100647.29" + attribute \src "libresoc.v:101679.5-101679.29" switch \initial - attribute \src "libresoc.v:100647.9-100647.17" + attribute \src "libresoc.v:101679.9-101679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -157103,167 +158643,163 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] end - attribute \src "libresoc.v:99719.7-99719.20" - process $proc$libresoc.v:99719$4060 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100670.1-101810.10" +attribute \src "libresoc.v:101702.1-102877.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:101659.3-101683.6" + attribute \src "libresoc.v:102726.3-102750.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101684.3-101708.6" + attribute \src "libresoc.v:102751.3-102775.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101359.3-101383.6" + attribute \src "libresoc.v:102426.3-102450.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101459.3-101483.6" + attribute \src "libresoc.v:102526.3-102550.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101034.3-101058.6" + attribute \src "libresoc.v:102076.3-102100.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101059.3-101083.6" + attribute \src "libresoc.v:102101.3-102125.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101334.3-101358.6" + attribute \src "libresoc.v:102401.3-102425.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101434.3-101458.6" + attribute \src "libresoc.v:102501.3-102525.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101559.3-101583.6" + attribute \src "libresoc.v:102601.3-102625.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101009.3-101033.6" + attribute \src "libresoc.v:102051.3-102075.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101709.3-101733.6" + attribute \src "libresoc.v:102776.3-102800.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101734.3-101758.6" + attribute \src "libresoc.v:102801.3-102825.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101759.3-101783.6" + attribute \src "libresoc.v:102826.3-102850.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101284.3-101308.6" + attribute \src "libresoc.v:102326.3-102350.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101384.3-101408.6" + attribute \src "libresoc.v:102451.3-102475.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101409.3-101433.6" + attribute \src "libresoc.v:102476.3-102500.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101534.3-101558.6" + attribute \src "libresoc.v:102626.3-102650.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101234.3-101258.6" + attribute \src "libresoc.v:102301.3-102325.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101609.3-101633.6" + attribute \src "libresoc.v:102676.3-102700.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101784.3-101808.6" + attribute \src "libresoc.v:102851.3-102875.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101309.3-101333.6" + attribute \src "libresoc.v:102376.3-102400.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101509.3-101533.6" + attribute \src "libresoc.v:102576.3-102600.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101634.3-101658.6" + attribute \src "libresoc.v:102701.3-102725.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101584.3-101608.6" + attribute \src "libresoc.v:102651.3-102675.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101484.3-101508.6" + attribute \src "libresoc.v:102551.3-102575.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101184.3-101208.6" + attribute \src "libresoc.v:102251.3-102275.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101209.3-101233.6" + attribute \src "libresoc.v:102276.3-102300.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101084.3-101108.6" + attribute \src "libresoc.v:102126.3-102150.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101109.3-101133.6" + attribute \src "libresoc.v:102151.3-102175.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101134.3-101158.6" + attribute \src "libresoc.v:102176.3-102200.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101159.3-101183.6" + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101259.3-101283.6" + attribute \src "libresoc.v:102351.3-102375.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:100671.7-100671.20" + attribute \src "libresoc.v:101703.7-101703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101659.3-101683.6" + attribute \src "libresoc.v:102726.3-102750.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101684.3-101708.6" + attribute \src "libresoc.v:102751.3-102775.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101359.3-101383.6" + attribute \src "libresoc.v:102426.3-102450.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101459.3-101483.6" + attribute \src "libresoc.v:102526.3-102550.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101034.3-101058.6" + attribute \src "libresoc.v:102076.3-102100.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101059.3-101083.6" + attribute \src "libresoc.v:102101.3-102125.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101334.3-101358.6" + attribute \src "libresoc.v:102401.3-102425.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101434.3-101458.6" + attribute \src "libresoc.v:102501.3-102525.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101559.3-101583.6" + attribute \src "libresoc.v:102601.3-102625.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101009.3-101033.6" + attribute \src "libresoc.v:102051.3-102075.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101709.3-101733.6" + attribute \src "libresoc.v:102776.3-102800.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101734.3-101758.6" + attribute \src "libresoc.v:102801.3-102825.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101759.3-101783.6" + attribute \src "libresoc.v:102826.3-102850.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101284.3-101308.6" + attribute \src "libresoc.v:102326.3-102350.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101384.3-101408.6" + attribute \src "libresoc.v:102451.3-102475.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101409.3-101433.6" + attribute \src "libresoc.v:102476.3-102500.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101534.3-101558.6" + attribute \src "libresoc.v:102626.3-102650.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101234.3-101258.6" + attribute \src "libresoc.v:102301.3-102325.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101609.3-101633.6" + attribute \src "libresoc.v:102676.3-102700.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101784.3-101808.6" + attribute \src "libresoc.v:102851.3-102875.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101309.3-101333.6" + attribute \src "libresoc.v:102376.3-102400.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101509.3-101533.6" + attribute \src "libresoc.v:102576.3-102600.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101634.3-101658.6" + attribute \src "libresoc.v:102701.3-102725.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101584.3-101608.6" + attribute \src "libresoc.v:102651.3-102675.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101484.3-101508.6" + attribute \src "libresoc.v:102551.3-102575.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101184.3-101208.6" + attribute \src "libresoc.v:102251.3-102275.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101209.3-101233.6" + attribute \src "libresoc.v:102276.3-102300.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101084.3-101108.6" + attribute \src "libresoc.v:102126.3-102150.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101109.3-101133.6" + attribute \src "libresoc.v:102151.3-102175.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101134.3-101158.6" + attribute \src "libresoc.v:102176.3-102200.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101159.3-101183.6" + attribute \src "libresoc.v:102226.3-102250.6" + wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102201.3-102225.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101259.3-101283.6" + attribute \src "libresoc.v:102351.3-102375.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub20_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub20_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub20_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -157273,7 +158809,7 @@ module \dec31_dec_sub20 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -157282,16 +158818,16 @@ module \dec31_dec_sub20 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub20_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -157323,7 +158859,7 @@ module \dec31_dec_sub20 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -157340,7 +158876,7 @@ module \dec31_dec_sub20 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -157348,7 +158884,7 @@ module \dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -157365,13 +158901,13 @@ module \dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -157448,46 +158984,46 @@ module \dec31_dec_sub20 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub20_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub20_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub20_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub20_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157495,8 +159031,8 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub20_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub20_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157504,8 +159040,8 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub20_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub20_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -157513,7 +159049,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub20_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157522,7 +159058,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub20_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157531,7 +159067,7 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub20_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -157540,41 +159076,50 @@ module \dec31_dec_sub20 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub20_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub20_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub20_upd - attribute \src "libresoc.v:100671.7-100671.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub20_upd + attribute \src "libresoc.v:101703.7-101703.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100671.7-100671.20" - process $proc$libresoc.v:100671$4093 + attribute \src "libresoc.v:101703.7-101703.20" + process $proc$libresoc.v:101703$4122 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101009.3-101033.6" - process $proc$libresoc.v:101009$4061 + attribute \src "libresoc.v:102051.3-102075.6" + process $proc$libresoc.v:102051$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:101010.5-101010.29" + attribute \src "libresoc.v:102052.5-102052.29" switch \initial - attribute \src "libresoc.v:101010.9-101010.17" + attribute \src "libresoc.v:102052.9-102052.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157606,18 +159151,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:101034.3-101058.6" - process $proc$libresoc.v:101034$4062 + attribute \src "libresoc.v:102076.3-102100.6" + process $proc$libresoc.v:102076$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:101035.5-101035.29" + attribute \src "libresoc.v:102077.5-102077.29" switch \initial - attribute \src "libresoc.v:101035.9-101035.17" + attribute \src "libresoc.v:102077.9-102077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157649,18 +159194,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:101059.3-101083.6" - process $proc$libresoc.v:101059$4063 + attribute \src "libresoc.v:102101.3-102125.6" + process $proc$libresoc.v:102101$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:101060.5-101060.29" + attribute \src "libresoc.v:102102.5-102102.29" switch \initial - attribute \src "libresoc.v:101060.9-101060.17" + attribute \src "libresoc.v:102102.9-102102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157692,18 +159237,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:101084.3-101108.6" - process $proc$libresoc.v:101084$4064 + attribute \src "libresoc.v:102126.3-102150.6" + process $proc$libresoc.v:102126$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:101085.5-101085.29" + attribute \src "libresoc.v:102127.5-102127.29" switch \initial - attribute \src "libresoc.v:101085.9-101085.17" + attribute \src "libresoc.v:102127.9-102127.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157735,18 +159280,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:101109.3-101133.6" - process $proc$libresoc.v:101109$4065 + attribute \src "libresoc.v:102151.3-102175.6" + process $proc$libresoc.v:102151$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:101110.5-101110.29" + attribute \src "libresoc.v:102152.5-102152.29" switch \initial - attribute \src "libresoc.v:101110.9-101110.17" + attribute \src "libresoc.v:102152.9-102152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157778,18 +159323,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:101134.3-101158.6" - process $proc$libresoc.v:101134$4066 + attribute \src "libresoc.v:102176.3-102200.6" + process $proc$libresoc.v:102176$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:101135.5-101135.29" + attribute \src "libresoc.v:102177.5-102177.29" switch \initial - attribute \src "libresoc.v:101135.9-101135.17" + attribute \src "libresoc.v:102177.9-102177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157821,18 +159366,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:101159.3-101183.6" - process $proc$libresoc.v:101159$4067 + attribute \src "libresoc.v:102201.3-102225.6" + process $proc$libresoc.v:102201$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:101160.5-101160.29" + attribute \src "libresoc.v:102202.5-102202.29" switch \initial - attribute \src "libresoc.v:101160.9-101160.17" + attribute \src "libresoc.v:102202.9-102202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157864,18 +159409,61 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:101184.3-101208.6" - process $proc$libresoc.v:101184$4068 + attribute \src "libresoc.v:102226.3-102250.6" + process $proc$libresoc.v:102226$4096 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] + attribute \src "libresoc.v:102227.5-102227.29" + switch \initial + attribute \src "libresoc.v:102227.9-102227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] + end + attribute \src "libresoc.v:102251.3-102275.6" + process $proc$libresoc.v:102251$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:101185.5-101185.29" + attribute \src "libresoc.v:102252.5-102252.29" switch \initial - attribute \src "libresoc.v:101185.9-101185.17" + attribute \src "libresoc.v:102252.9-102252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157907,18 +159495,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:101209.3-101233.6" - process $proc$libresoc.v:101209$4069 + attribute \src "libresoc.v:102276.3-102300.6" + process $proc$libresoc.v:102276$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:101210.5-101210.29" + attribute \src "libresoc.v:102277.5-102277.29" switch \initial - attribute \src "libresoc.v:101210.9-101210.17" + attribute \src "libresoc.v:102277.9-102277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157950,18 +159538,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:101234.3-101258.6" - process $proc$libresoc.v:101234$4070 + attribute \src "libresoc.v:102301.3-102325.6" + process $proc$libresoc.v:102301$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:101235.5-101235.29" + attribute \src "libresoc.v:102302.5-102302.29" switch \initial - attribute \src "libresoc.v:101235.9-101235.17" + attribute \src "libresoc.v:102302.9-102302.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -157993,104 +159581,104 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:101259.3-101283.6" - process $proc$libresoc.v:101259$4071 + attribute \src "libresoc.v:102326.3-102350.6" + process $proc$libresoc.v:102326$4100 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:101260.5-101260.29" + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:102327.5-102327.29" switch \initial - attribute \src "libresoc.v:101260.9-101260.17" + attribute \src "libresoc.v:102327.9-102327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:101284.3-101308.6" - process $proc$libresoc.v:101284$4072 + attribute \src "libresoc.v:102351.3-102375.6" + process $proc$libresoc.v:102351$4101 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:101285.5-101285.29" + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:102352.5-102352.29" switch \initial - attribute \src "libresoc.v:101285.9-101285.17" + attribute \src "libresoc.v:102352.9-102352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub20_upd[1:0] 2'00 end sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:101309.3-101333.6" - process $proc$libresoc.v:101309$4073 + attribute \src "libresoc.v:102376.3-102400.6" + process $proc$libresoc.v:102376$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:101310.5-101310.29" + attribute \src "libresoc.v:102377.5-102377.29" switch \initial - attribute \src "libresoc.v:101310.9-101310.17" + attribute \src "libresoc.v:102377.9-102377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158122,18 +159710,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:101334.3-101358.6" - process $proc$libresoc.v:101334$4074 + attribute \src "libresoc.v:102401.3-102425.6" + process $proc$libresoc.v:102401$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:101335.5-101335.29" + attribute \src "libresoc.v:102402.5-102402.29" switch \initial - attribute \src "libresoc.v:101335.9-101335.17" + attribute \src "libresoc.v:102402.9-102402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158165,18 +159753,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:101359.3-101383.6" - process $proc$libresoc.v:101359$4075 + attribute \src "libresoc.v:102426.3-102450.6" + process $proc$libresoc.v:102426$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:101360.5-101360.29" + attribute \src "libresoc.v:102427.5-102427.29" switch \initial - attribute \src "libresoc.v:101360.9-101360.17" + attribute \src "libresoc.v:102427.9-102427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158208,18 +159796,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:101384.3-101408.6" - process $proc$libresoc.v:101384$4076 + attribute \src "libresoc.v:102451.3-102475.6" + process $proc$libresoc.v:102451$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:101385.5-101385.29" + attribute \src "libresoc.v:102452.5-102452.29" switch \initial - attribute \src "libresoc.v:101385.9-101385.17" + attribute \src "libresoc.v:102452.9-102452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158251,18 +159839,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:101409.3-101433.6" - process $proc$libresoc.v:101409$4077 + attribute \src "libresoc.v:102476.3-102500.6" + process $proc$libresoc.v:102476$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:101410.5-101410.29" + attribute \src "libresoc.v:102477.5-102477.29" switch \initial - attribute \src "libresoc.v:101410.9-101410.17" + attribute \src "libresoc.v:102477.9-102477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158294,18 +159882,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:101434.3-101458.6" - process $proc$libresoc.v:101434$4078 + attribute \src "libresoc.v:102501.3-102525.6" + process $proc$libresoc.v:102501$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:101435.5-101435.29" + attribute \src "libresoc.v:102502.5-102502.29" switch \initial - attribute \src "libresoc.v:101435.9-101435.17" + attribute \src "libresoc.v:102502.9-102502.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158337,18 +159925,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:101459.3-101483.6" - process $proc$libresoc.v:101459$4079 + attribute \src "libresoc.v:102526.3-102550.6" + process $proc$libresoc.v:102526$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:101460.5-101460.29" + attribute \src "libresoc.v:102527.5-102527.29" switch \initial - attribute \src "libresoc.v:101460.9-101460.17" + attribute \src "libresoc.v:102527.9-102527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158380,18 +159968,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:101484.3-101508.6" - process $proc$libresoc.v:101484$4080 + attribute \src "libresoc.v:102551.3-102575.6" + process $proc$libresoc.v:102551$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:101485.5-101485.29" + attribute \src "libresoc.v:102552.5-102552.29" switch \initial - attribute \src "libresoc.v:101485.9-101485.17" + attribute \src "libresoc.v:102552.9-102552.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158423,18 +160011,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:101509.3-101533.6" - process $proc$libresoc.v:101509$4081 + attribute \src "libresoc.v:102576.3-102600.6" + process $proc$libresoc.v:102576$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:101510.5-101510.29" + attribute \src "libresoc.v:102577.5-102577.29" switch \initial - attribute \src "libresoc.v:101510.9-101510.17" + attribute \src "libresoc.v:102577.9-102577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158466,104 +160054,104 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:101534.3-101558.6" - process $proc$libresoc.v:101534$4082 + attribute \src "libresoc.v:102601.3-102625.6" + process $proc$libresoc.v:102601$4111 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:101535.5-101535.29" + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:102602.5-102602.29" switch \initial - attribute \src "libresoc.v:101535.9-101535.17" + attribute \src "libresoc.v:102602.9-102602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'01000 case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub20_form[4:0] 5'00000 end sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:101559.3-101583.6" - process $proc$libresoc.v:101559$4083 + attribute \src "libresoc.v:102626.3-102650.6" + process $proc$libresoc.v:102626$4112 assign { } { } assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:101560.5-101560.29" + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:102627.5-102627.29" switch \initial - attribute \src "libresoc.v:101560.9-101560.17" + attribute \src "libresoc.v:102627.9-102627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:101584.3-101608.6" - process $proc$libresoc.v:101584$4084 + attribute \src "libresoc.v:102651.3-102675.6" + process $proc$libresoc.v:102651$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:101585.5-101585.29" + attribute \src "libresoc.v:102652.5-102652.29" switch \initial - attribute \src "libresoc.v:101585.9-101585.17" + attribute \src "libresoc.v:102652.9-102652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158595,18 +160183,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:101609.3-101633.6" - process $proc$libresoc.v:101609$4085 + attribute \src "libresoc.v:102676.3-102700.6" + process $proc$libresoc.v:102676$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101610.5-101610.29" + attribute \src "libresoc.v:102677.5-102677.29" switch \initial - attribute \src "libresoc.v:101610.9-101610.17" + attribute \src "libresoc.v:102677.9-102677.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158638,18 +160226,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:101634.3-101658.6" - process $proc$libresoc.v:101634$4086 + attribute \src "libresoc.v:102701.3-102725.6" + process $proc$libresoc.v:102701$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:101635.5-101635.29" + attribute \src "libresoc.v:102702.5-102702.29" switch \initial - attribute \src "libresoc.v:101635.9-101635.17" + attribute \src "libresoc.v:102702.9-102702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158681,18 +160269,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:101659.3-101683.6" - process $proc$libresoc.v:101659$4087 + attribute \src "libresoc.v:102726.3-102750.6" + process $proc$libresoc.v:102726$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:101660.5-101660.29" + attribute \src "libresoc.v:102727.5-102727.29" switch \initial - attribute \src "libresoc.v:101660.9-101660.17" + attribute \src "libresoc.v:102727.9-102727.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158724,18 +160312,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:101684.3-101708.6" - process $proc$libresoc.v:101684$4088 + attribute \src "libresoc.v:102751.3-102775.6" + process $proc$libresoc.v:102751$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:101685.5-101685.29" + attribute \src "libresoc.v:102752.5-102752.29" switch \initial - attribute \src "libresoc.v:101685.9-101685.17" + attribute \src "libresoc.v:102752.9-102752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158767,18 +160355,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:101709.3-101733.6" - process $proc$libresoc.v:101709$4089 + attribute \src "libresoc.v:102776.3-102800.6" + process $proc$libresoc.v:102776$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101710.5-101710.29" + attribute \src "libresoc.v:102777.5-102777.29" switch \initial - attribute \src "libresoc.v:101710.9-101710.17" + attribute \src "libresoc.v:102777.9-102777.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158810,18 +160398,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:101734.3-101758.6" - process $proc$libresoc.v:101734$4090 + attribute \src "libresoc.v:102801.3-102825.6" + process $proc$libresoc.v:102801$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101735.5-101735.29" + attribute \src "libresoc.v:102802.5-102802.29" switch \initial - attribute \src "libresoc.v:101735.9-101735.17" + attribute \src "libresoc.v:102802.9-102802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158853,18 +160441,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:101759.3-101783.6" - process $proc$libresoc.v:101759$4091 + attribute \src "libresoc.v:102826.3-102850.6" + process $proc$libresoc.v:102826$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101760.5-101760.29" + attribute \src "libresoc.v:102827.5-102827.29" switch \initial - attribute \src "libresoc.v:101760.9-101760.17" + attribute \src "libresoc.v:102827.9-102827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158896,18 +160484,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:101784.3-101808.6" - process $proc$libresoc.v:101784$4092 + attribute \src "libresoc.v:102851.3-102875.6" + process $proc$libresoc.v:102851$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:101785.5-101785.29" + attribute \src "libresoc.v:102852.5-102852.29" switch \initial - attribute \src "libresoc.v:101785.9-101785.17" + attribute \src "libresoc.v:102852.9-102852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -158941,157 +160529,161 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101814.1-103704.10" +attribute \src "libresoc.v:102881.1-104830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:103409.3-103457.6" + attribute \src "libresoc.v:104535.3-104583.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103458.3-103506.6" + attribute \src "libresoc.v:104584.3-104632.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103378.3-103408.6" + attribute \src "libresoc.v:104504.3-104534.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102986.3-103034.6" + attribute \src "libresoc.v:104112.3-104160.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102202.3-102250.6" + attribute \src "libresoc.v:103279.3-103327.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102251.3-102299.6" + attribute \src "libresoc.v:103328.3-103376.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102790.3-102838.6" + attribute \src "libresoc.v:103916.3-103964.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102937.3-102985.6" + attribute \src "libresoc.v:104063.3-104111.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:103231.3-103279.6" + attribute \src "libresoc.v:104308.3-104356.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:102153.3-102201.6" + attribute \src "libresoc.v:103230.3-103278.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103507.3-103555.6" + attribute \src "libresoc.v:104633.3-104681.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103556.3-103604.6" + attribute \src "libresoc.v:104682.3-104730.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103605.3-103653.6" + attribute \src "libresoc.v:104731.3-104779.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102692.3-102740.6" + attribute \src "libresoc.v:103769.3-103817.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102839.3-102887.6" + attribute \src "libresoc.v:103965.3-104013.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102888.3-102936.6" + attribute \src "libresoc.v:104014.3-104062.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:103133.3-103181.6" + attribute \src "libresoc.v:104259.3-104307.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:102594.3-102642.6" + attribute \src "libresoc.v:103720.3-103768.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103280.3-103328.6" + attribute \src "libresoc.v:104406.3-104454.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103654.3-103702.6" + attribute \src "libresoc.v:104780.3-104828.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:102741.3-102789.6" + attribute \src "libresoc.v:103867.3-103915.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103084.3-103132.6" + attribute \src "libresoc.v:104210.3-104258.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103329.3-103377.6" + attribute \src "libresoc.v:104455.3-104503.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103182.3-103230.6" + attribute \src "libresoc.v:104357.3-104405.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103035.3-103083.6" + attribute \src "libresoc.v:104161.3-104209.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:102496.3-102544.6" + attribute \src "libresoc.v:103622.3-103670.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102545.3-102593.6" + attribute \src "libresoc.v:103671.3-103719.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102300.3-102348.6" + attribute \src "libresoc.v:103377.3-103425.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102349.3-102397.6" + attribute \src "libresoc.v:103426.3-103474.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102398.3-102446.6" + attribute \src "libresoc.v:103475.3-103523.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102447.3-102495.6" + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102643.3-102691.6" + attribute \src "libresoc.v:103818.3-103866.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:101815.7-101815.20" + attribute \src "libresoc.v:102882.7-102882.20" wire $0\initial[0:0] - attribute \src "libresoc.v:103409.3-103457.6" + attribute \src "libresoc.v:104535.3-104583.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103458.3-103506.6" + attribute \src "libresoc.v:104584.3-104632.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103378.3-103408.6" + attribute \src "libresoc.v:104504.3-104534.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102986.3-103034.6" + attribute \src "libresoc.v:104112.3-104160.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102202.3-102250.6" + attribute \src "libresoc.v:103279.3-103327.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102251.3-102299.6" + attribute \src "libresoc.v:103328.3-103376.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102790.3-102838.6" + attribute \src "libresoc.v:103916.3-103964.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102937.3-102985.6" + attribute \src "libresoc.v:104063.3-104111.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:103231.3-103279.6" + attribute \src "libresoc.v:104308.3-104356.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:102153.3-102201.6" + attribute \src "libresoc.v:103230.3-103278.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103507.3-103555.6" + attribute \src "libresoc.v:104633.3-104681.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103556.3-103604.6" + attribute \src "libresoc.v:104682.3-104730.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103605.3-103653.6" + attribute \src "libresoc.v:104731.3-104779.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102692.3-102740.6" + attribute \src "libresoc.v:103769.3-103817.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102839.3-102887.6" + attribute \src "libresoc.v:103965.3-104013.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102888.3-102936.6" + attribute \src "libresoc.v:104014.3-104062.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:103133.3-103181.6" + attribute \src "libresoc.v:104259.3-104307.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:102594.3-102642.6" + attribute \src "libresoc.v:103720.3-103768.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103280.3-103328.6" + attribute \src "libresoc.v:104406.3-104454.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103654.3-103702.6" + attribute \src "libresoc.v:104780.3-104828.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:102741.3-102789.6" + attribute \src "libresoc.v:103867.3-103915.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103084.3-103132.6" + attribute \src "libresoc.v:104210.3-104258.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103329.3-103377.6" + attribute \src "libresoc.v:104455.3-104503.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103182.3-103230.6" + attribute \src "libresoc.v:104357.3-104405.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103035.3-103083.6" + attribute \src "libresoc.v:104161.3-104209.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:102496.3-102544.6" + attribute \src "libresoc.v:103622.3-103670.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102545.3-102593.6" + attribute \src "libresoc.v:103671.3-103719.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102300.3-102348.6" + attribute \src "libresoc.v:103377.3-103425.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102349.3-102397.6" + attribute \src "libresoc.v:103426.3-103474.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102398.3-102446.6" + attribute \src "libresoc.v:103475.3-103523.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102447.3-102495.6" + attribute \src "libresoc.v:103573.3-103621.6" + wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103524.3-103572.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102643.3-102691.6" + attribute \src "libresoc.v:103818.3-103866.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub21_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub21_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub21_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -159101,7 +160693,7 @@ module \dec31_dec_sub21 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -159110,16 +160702,16 @@ module \dec31_dec_sub21 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub21_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -159151,7 +160743,7 @@ module \dec31_dec_sub21 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -159168,7 +160760,7 @@ module \dec31_dec_sub21 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -159176,7 +160768,7 @@ module \dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -159193,13 +160785,13 @@ module \dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -159276,46 +160868,46 @@ module \dec31_dec_sub21 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub21_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub21_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub21_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159323,8 +160915,8 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub21_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub21_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159332,8 +160924,8 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub21_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub21_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -159341,7 +160933,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub21_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159350,7 +160942,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub21_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159359,7 +160951,7 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub21_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -159368,41 +160960,50 @@ module \dec31_dec_sub21 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub21_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub21_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub21_upd - attribute \src "libresoc.v:101815.7-101815.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub21_upd + attribute \src "libresoc.v:102882.7-102882.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:101815.7-101815.20" - process $proc$libresoc.v:101815$4126 + attribute \src "libresoc.v:102882.7-102882.20" + process $proc$libresoc.v:102882$4156 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102153.3-102201.6" - process $proc$libresoc.v:102153$4094 + attribute \src "libresoc.v:103230.3-103278.6" + process $proc$libresoc.v:103230$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:102154.5-102154.29" + attribute \src "libresoc.v:103231.5-103231.29" switch \initial - attribute \src "libresoc.v:102154.9-102154.17" + attribute \src "libresoc.v:103231.9-103231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159466,18 +161067,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:102202.3-102250.6" - process $proc$libresoc.v:102202$4095 + attribute \src "libresoc.v:103279.3-103327.6" + process $proc$libresoc.v:103279$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:102203.5-102203.29" + attribute \src "libresoc.v:103280.5-103280.29" switch \initial - attribute \src "libresoc.v:102203.9-102203.17" + attribute \src "libresoc.v:103280.9-103280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159541,18 +161142,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:102251.3-102299.6" - process $proc$libresoc.v:102251$4096 + attribute \src "libresoc.v:103328.3-103376.6" + process $proc$libresoc.v:103328$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102252.5-102252.29" + attribute \src "libresoc.v:103329.5-103329.29" switch \initial - attribute \src "libresoc.v:102252.9-102252.17" + attribute \src "libresoc.v:103329.9-103329.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159616,18 +161217,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:102300.3-102348.6" - process $proc$libresoc.v:102300$4097 + attribute \src "libresoc.v:103377.3-103425.6" + process $proc$libresoc.v:103377$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:102301.5-102301.29" + attribute \src "libresoc.v:103378.5-103378.29" switch \initial - attribute \src "libresoc.v:102301.9-102301.17" + attribute \src "libresoc.v:103378.9-103378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159691,18 +161292,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:102349.3-102397.6" - process $proc$libresoc.v:102349$4098 + attribute \src "libresoc.v:103426.3-103474.6" + process $proc$libresoc.v:103426$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:102350.5-102350.29" + attribute \src "libresoc.v:103427.5-103427.29" switch \initial - attribute \src "libresoc.v:102350.9-102350.17" + attribute \src "libresoc.v:103427.9-103427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159766,18 +161367,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:102398.3-102446.6" - process $proc$libresoc.v:102398$4099 + attribute \src "libresoc.v:103475.3-103523.6" + process $proc$libresoc.v:103475$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:102399.5-102399.29" + attribute \src "libresoc.v:103476.5-103476.29" switch \initial - attribute \src "libresoc.v:102399.9-102399.17" + attribute \src "libresoc.v:103476.9-103476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159841,18 +161442,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:102447.3-102495.6" - process $proc$libresoc.v:102447$4100 + attribute \src "libresoc.v:103524.3-103572.6" + process $proc$libresoc.v:103524$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:102448.5-102448.29" + attribute \src "libresoc.v:103525.5-103525.29" switch \initial - attribute \src "libresoc.v:102448.9-102448.17" + attribute \src "libresoc.v:103525.9-103525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159916,18 +161517,93 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:102496.3-102544.6" - process $proc$libresoc.v:102496$4101 + attribute \src "libresoc.v:103573.3-103621.6" + process $proc$libresoc.v:103573$4130 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] + attribute \src "libresoc.v:103574.5-103574.29" + switch \initial + attribute \src "libresoc.v:103574.9-103574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] + end + attribute \src "libresoc.v:103622.3-103670.6" + process $proc$libresoc.v:103622$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:102497.5-102497.29" + attribute \src "libresoc.v:103623.5-103623.29" switch \initial - attribute \src "libresoc.v:102497.9-102497.17" + attribute \src "libresoc.v:103623.9-103623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -159991,18 +161667,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:102545.3-102593.6" - process $proc$libresoc.v:102545$4102 + attribute \src "libresoc.v:103671.3-103719.6" + process $proc$libresoc.v:103671$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:102546.5-102546.29" + attribute \src "libresoc.v:103672.5-103672.29" switch \initial - attribute \src "libresoc.v:102546.9-102546.17" + attribute \src "libresoc.v:103672.9-103672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160066,18 +161742,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:102594.3-102642.6" - process $proc$libresoc.v:102594$4103 + attribute \src "libresoc.v:103720.3-103768.6" + process $proc$libresoc.v:103720$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:102595.5-102595.29" + attribute \src "libresoc.v:103721.5-103721.29" switch \initial - attribute \src "libresoc.v:102595.9-102595.17" + attribute \src "libresoc.v:103721.9-103721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160141,168 +161817,168 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:102643.3-102691.6" - process $proc$libresoc.v:102643$4104 + attribute \src "libresoc.v:103769.3-103817.6" + process $proc$libresoc.v:103769$4134 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:102644.5-102644.29" + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:103770.5-103770.29" switch \initial - attribute \src "libresoc.v:102644.9-102644.17" + attribute \src "libresoc.v:103770.9-103770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:102692.3-102740.6" - process $proc$libresoc.v:102692$4105 + attribute \src "libresoc.v:103818.3-103866.6" + process $proc$libresoc.v:103818$4135 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102693.5-102693.29" + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:103819.5-103819.29" switch \initial - attribute \src "libresoc.v:102693.9-102693.17" + attribute \src "libresoc.v:103819.9-103819.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub21_upd[1:0] 2'10 case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub21_upd[1:0] 2'00 end sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:102741.3-102789.6" - process $proc$libresoc.v:102741$4106 + attribute \src "libresoc.v:103867.3-103915.6" + process $proc$libresoc.v:103867$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:102742.5-102742.29" + attribute \src "libresoc.v:103868.5-103868.29" switch \initial - attribute \src "libresoc.v:102742.9-102742.17" + attribute \src "libresoc.v:103868.9-103868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160366,18 +162042,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:102790.3-102838.6" - process $proc$libresoc.v:102790$4107 + attribute \src "libresoc.v:103916.3-103964.6" + process $proc$libresoc.v:103916$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102791.5-102791.29" + attribute \src "libresoc.v:103917.5-103917.29" switch \initial - attribute \src "libresoc.v:102791.9-102791.17" + attribute \src "libresoc.v:103917.9-103917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160441,18 +162117,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:102839.3-102887.6" - process $proc$libresoc.v:102839$4108 + attribute \src "libresoc.v:103965.3-104013.6" + process $proc$libresoc.v:103965$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102840.5-102840.29" + attribute \src "libresoc.v:103966.5-103966.29" switch \initial - attribute \src "libresoc.v:102840.9-102840.17" + attribute \src "libresoc.v:103966.9-103966.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160516,18 +162192,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:102888.3-102936.6" - process $proc$libresoc.v:102888$4109 + attribute \src "libresoc.v:104014.3-104062.6" + process $proc$libresoc.v:104014$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:102889.5-102889.29" + attribute \src "libresoc.v:104015.5-104015.29" switch \initial - attribute \src "libresoc.v:102889.9-102889.17" + attribute \src "libresoc.v:104015.9-104015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160591,18 +162267,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:102937.3-102985.6" - process $proc$libresoc.v:102937$4110 + attribute \src "libresoc.v:104063.3-104111.6" + process $proc$libresoc.v:104063$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:102938.5-102938.29" + attribute \src "libresoc.v:104064.5-104064.29" switch \initial - attribute \src "libresoc.v:102938.9-102938.17" + attribute \src "libresoc.v:104064.9-104064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160666,18 +162342,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:102986.3-103034.6" - process $proc$libresoc.v:102986$4111 + attribute \src "libresoc.v:104112.3-104160.6" + process $proc$libresoc.v:104112$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102987.5-102987.29" + attribute \src "libresoc.v:104113.5-104113.29" switch \initial - attribute \src "libresoc.v:102987.9-102987.17" + attribute \src "libresoc.v:104113.9-104113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160741,18 +162417,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:103035.3-103083.6" - process $proc$libresoc.v:103035$4112 + attribute \src "libresoc.v:104161.3-104209.6" + process $proc$libresoc.v:104161$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103036.5-103036.29" + attribute \src "libresoc.v:104162.5-104162.29" switch \initial - attribute \src "libresoc.v:103036.9-103036.17" + attribute \src "libresoc.v:104162.9-104162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160816,18 +162492,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:103084.3-103132.6" - process $proc$libresoc.v:103084$4113 + attribute \src "libresoc.v:104210.3-104258.6" + process $proc$libresoc.v:104210$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:103085.5-103085.29" + attribute \src "libresoc.v:104211.5-104211.29" switch \initial - attribute \src "libresoc.v:103085.9-103085.17" + attribute \src "libresoc.v:104211.9-104211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160891,18 +162567,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:103133.3-103181.6" - process $proc$libresoc.v:103133$4114 + attribute \src "libresoc.v:104259.3-104307.6" + process $proc$libresoc.v:104259$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103134.5-103134.29" + attribute \src "libresoc.v:104260.5-104260.29" switch \initial - attribute \src "libresoc.v:103134.9-103134.17" + attribute \src "libresoc.v:104260.9-104260.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -160966,168 +162642,168 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:103182.3-103230.6" - process $proc$libresoc.v:103182$4115 + attribute \src "libresoc.v:104308.3-104356.6" + process $proc$libresoc.v:104308$4145 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:103183.5-103183.29" + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:104309.5-104309.29" switch \initial - attribute \src "libresoc.v:103183.9-103183.17" + attribute \src "libresoc.v:104309.9-104309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'01000 case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'00000 end sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:103231.3-103279.6" - process $proc$libresoc.v:103231$4116 + attribute \src "libresoc.v:104357.3-104405.6" + process $proc$libresoc.v:104357$4146 assign { } { } assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103232.5-103232.29" + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:104358.5-104358.29" switch \initial - attribute \src "libresoc.v:103232.9-103232.17" + attribute \src "libresoc.v:104358.9-104358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 end sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:103280.3-103328.6" - process $proc$libresoc.v:103280$4117 + attribute \src "libresoc.v:104406.3-104454.6" + process $proc$libresoc.v:104406$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:103281.5-103281.29" + attribute \src "libresoc.v:104407.5-104407.29" switch \initial - attribute \src "libresoc.v:103281.9-103281.17" + attribute \src "libresoc.v:104407.9-104407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161191,18 +162867,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:103329.3-103377.6" - process $proc$libresoc.v:103329$4118 + attribute \src "libresoc.v:104455.3-104503.6" + process $proc$libresoc.v:104455$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:103330.5-103330.29" + attribute \src "libresoc.v:104456.5-104456.29" switch \initial - attribute \src "libresoc.v:103330.9-103330.17" + attribute \src "libresoc.v:104456.9-104456.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161266,18 +162942,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:103378.3-103408.6" - process $proc$libresoc.v:103378$4119 + attribute \src "libresoc.v:104504.3-104534.6" + process $proc$libresoc.v:104504$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:103379.5-103379.29" + attribute \src "libresoc.v:104505.5-104505.29" switch \initial - attribute \src "libresoc.v:103379.9-103379.17" + attribute \src "libresoc.v:104505.9-104505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -161317,18 +162993,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:103409.3-103457.6" - process $proc$libresoc.v:103409$4120 + attribute \src "libresoc.v:104535.3-104583.6" + process $proc$libresoc.v:104535$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:103410.5-103410.29" + attribute \src "libresoc.v:104536.5-104536.29" switch \initial - attribute \src "libresoc.v:103410.9-103410.17" + attribute \src "libresoc.v:104536.9-104536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161392,18 +163068,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:103458.3-103506.6" - process $proc$libresoc.v:103458$4121 + attribute \src "libresoc.v:104584.3-104632.6" + process $proc$libresoc.v:104584$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:103459.5-103459.29" + attribute \src "libresoc.v:104585.5-104585.29" switch \initial - attribute \src "libresoc.v:103459.9-103459.17" + attribute \src "libresoc.v:104585.9-104585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161467,18 +163143,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:103507.3-103555.6" - process $proc$libresoc.v:103507$4122 + attribute \src "libresoc.v:104633.3-104681.6" + process $proc$libresoc.v:104633$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:103508.5-103508.29" + attribute \src "libresoc.v:104634.5-104634.29" switch \initial - attribute \src "libresoc.v:103508.9-103508.17" + attribute \src "libresoc.v:104634.9-104634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161542,18 +163218,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:103556.3-103604.6" - process $proc$libresoc.v:103556$4123 + attribute \src "libresoc.v:104682.3-104730.6" + process $proc$libresoc.v:104682$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:103557.5-103557.29" + attribute \src "libresoc.v:104683.5-104683.29" switch \initial - attribute \src "libresoc.v:103557.9-103557.17" + attribute \src "libresoc.v:104683.9-104683.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161617,18 +163293,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:103605.3-103653.6" - process $proc$libresoc.v:103605$4124 + attribute \src "libresoc.v:104731.3-104779.6" + process $proc$libresoc.v:104731$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103606.5-103606.29" + attribute \src "libresoc.v:104732.5-104732.29" switch \initial - attribute \src "libresoc.v:103606.9-103606.17" + attribute \src "libresoc.v:104732.9-104732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161692,18 +163368,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:103654.3-103702.6" - process $proc$libresoc.v:103654$4125 + attribute \src "libresoc.v:104780.3-104828.6" + process $proc$libresoc.v:104780$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103655.5-103655.29" + attribute \src "libresoc.v:104781.5-104781.29" switch \initial - attribute \src "libresoc.v:103655.9-103655.17" + attribute \src "libresoc.v:104781.9-104781.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -161769,157 +163445,161 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:103708.1-105808.10" +attribute \src "libresoc.v:104834.1-106999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:105477.3-105531.6" + attribute \src "libresoc.v:106668.3-106722.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105532.3-105586.6" + attribute \src "libresoc.v:106723.3-106777.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104817.3-104871.6" + attribute \src "libresoc.v:106008.3-106062.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:105037.3-105091.6" + attribute \src "libresoc.v:106228.3-106282.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:104102.3-104156.6" + attribute \src "libresoc.v:105238.3-105292.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104157.3-104211.6" + attribute \src "libresoc.v:105293.3-105347.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104762.3-104816.6" + attribute \src "libresoc.v:105953.3-106007.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104982.3-105036.6" + attribute \src "libresoc.v:106173.3-106227.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:105257.3-105311.6" + attribute \src "libresoc.v:106393.3-106447.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:104047.3-104101.6" + attribute \src "libresoc.v:105183.3-105237.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105587.3-105641.6" + attribute \src "libresoc.v:106778.3-106832.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105642.3-105696.6" + attribute \src "libresoc.v:106833.3-106887.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105697.3-105751.6" + attribute \src "libresoc.v:106888.3-106942.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104652.3-104706.6" + attribute \src "libresoc.v:105788.3-105842.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104872.3-104926.6" + attribute \src "libresoc.v:106063.3-106117.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104927.3-104981.6" + attribute \src "libresoc.v:106118.3-106172.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:105202.3-105256.6" + attribute \src "libresoc.v:106448.3-106502.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:104542.3-104596.6" + attribute \src "libresoc.v:105733.3-105787.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105367.3-105421.6" + attribute \src "libresoc.v:106558.3-106612.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105752.3-105806.6" + attribute \src "libresoc.v:106943.3-106997.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:104707.3-104761.6" + attribute \src "libresoc.v:105898.3-105952.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105147.3-105201.6" + attribute \src "libresoc.v:106338.3-106392.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105422.3-105476.6" + attribute \src "libresoc.v:106613.3-106667.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105312.3-105366.6" + attribute \src "libresoc.v:106503.3-106557.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105092.3-105146.6" + attribute \src "libresoc.v:106283.3-106337.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:104432.3-104486.6" + attribute \src "libresoc.v:105623.3-105677.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104487.3-104541.6" + attribute \src "libresoc.v:105678.3-105732.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104212.3-104266.6" + attribute \src "libresoc.v:105348.3-105402.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104267.3-104321.6" + attribute \src "libresoc.v:105403.3-105457.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104322.3-104376.6" + attribute \src "libresoc.v:105458.3-105512.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104377.3-104431.6" + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104597.3-104651.6" + attribute \src "libresoc.v:105843.3-105897.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:103709.7-103709.20" + attribute \src "libresoc.v:104835.7-104835.20" wire $0\initial[0:0] - attribute \src "libresoc.v:105477.3-105531.6" + attribute \src "libresoc.v:106668.3-106722.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105532.3-105586.6" + attribute \src "libresoc.v:106723.3-106777.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104817.3-104871.6" + attribute \src "libresoc.v:106008.3-106062.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:105037.3-105091.6" + attribute \src "libresoc.v:106228.3-106282.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:104102.3-104156.6" + attribute \src "libresoc.v:105238.3-105292.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104157.3-104211.6" + attribute \src "libresoc.v:105293.3-105347.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104762.3-104816.6" + attribute \src "libresoc.v:105953.3-106007.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104982.3-105036.6" + attribute \src "libresoc.v:106173.3-106227.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:105257.3-105311.6" + attribute \src "libresoc.v:106393.3-106447.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:104047.3-104101.6" + attribute \src "libresoc.v:105183.3-105237.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105587.3-105641.6" + attribute \src "libresoc.v:106778.3-106832.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105642.3-105696.6" + attribute \src "libresoc.v:106833.3-106887.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105697.3-105751.6" + attribute \src "libresoc.v:106888.3-106942.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104652.3-104706.6" + attribute \src "libresoc.v:105788.3-105842.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104872.3-104926.6" + attribute \src "libresoc.v:106063.3-106117.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104927.3-104981.6" + attribute \src "libresoc.v:106118.3-106172.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:105202.3-105256.6" + attribute \src "libresoc.v:106448.3-106502.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:104542.3-104596.6" + attribute \src "libresoc.v:105733.3-105787.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105367.3-105421.6" + attribute \src "libresoc.v:106558.3-106612.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105752.3-105806.6" + attribute \src "libresoc.v:106943.3-106997.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:104707.3-104761.6" + attribute \src "libresoc.v:105898.3-105952.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105147.3-105201.6" + attribute \src "libresoc.v:106338.3-106392.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105422.3-105476.6" + attribute \src "libresoc.v:106613.3-106667.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105312.3-105366.6" + attribute \src "libresoc.v:106503.3-106557.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105092.3-105146.6" + attribute \src "libresoc.v:106283.3-106337.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:104432.3-104486.6" + attribute \src "libresoc.v:105623.3-105677.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104487.3-104541.6" + attribute \src "libresoc.v:105678.3-105732.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104212.3-104266.6" + attribute \src "libresoc.v:105348.3-105402.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104267.3-104321.6" + attribute \src "libresoc.v:105403.3-105457.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104322.3-104376.6" + attribute \src "libresoc.v:105458.3-105512.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104377.3-104431.6" + attribute \src "libresoc.v:105568.3-105622.6" + wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105513.3-105567.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104597.3-104651.6" + attribute \src "libresoc.v:105843.3-105897.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub22_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -161929,7 +163609,7 @@ module \dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -161938,16 +163618,16 @@ module \dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -161979,7 +163659,7 @@ module \dec31_dec_sub22 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -161996,7 +163676,7 @@ module \dec31_dec_sub22 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -162004,7 +163684,7 @@ module \dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -162021,13 +163701,13 @@ module \dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -162104,46 +163784,46 @@ module \dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162151,8 +163831,8 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub22_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162160,8 +163840,8 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub22_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -162169,7 +163849,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162178,7 +163858,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162187,7 +163867,7 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -162196,41 +163876,50 @@ module \dec31_dec_sub22 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub22_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub22_upd - attribute \src "libresoc.v:103709.7-103709.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub22_upd + attribute \src "libresoc.v:104835.7-104835.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:103709.7-103709.20" - process $proc$libresoc.v:103709$4159 + attribute \src "libresoc.v:104835.7-104835.20" + process $proc$libresoc.v:104835$4190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:104047.3-104101.6" - process $proc$libresoc.v:104047$4127 + attribute \src "libresoc.v:105183.3-105237.6" + process $proc$libresoc.v:105183$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:104048.5-104048.29" + attribute \src "libresoc.v:105184.5-105184.29" switch \initial - attribute \src "libresoc.v:104048.9-104048.17" + attribute \src "libresoc.v:105184.9-105184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162302,18 +163991,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:104102.3-104156.6" - process $proc$libresoc.v:104102$4128 + attribute \src "libresoc.v:105238.3-105292.6" + process $proc$libresoc.v:105238$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:104103.5-104103.29" + attribute \src "libresoc.v:105239.5-105239.29" switch \initial - attribute \src "libresoc.v:104103.9-104103.17" + attribute \src "libresoc.v:105239.9-105239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162385,18 +164074,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:104157.3-104211.6" - process $proc$libresoc.v:104157$4129 + attribute \src "libresoc.v:105293.3-105347.6" + process $proc$libresoc.v:105293$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104158.5-104158.29" + attribute \src "libresoc.v:105294.5-105294.29" switch \initial - attribute \src "libresoc.v:104158.9-104158.17" + attribute \src "libresoc.v:105294.9-105294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162468,18 +164157,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:104212.3-104266.6" - process $proc$libresoc.v:104212$4130 + attribute \src "libresoc.v:105348.3-105402.6" + process $proc$libresoc.v:105348$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:104213.5-104213.29" + attribute \src "libresoc.v:105349.5-105349.29" switch \initial - attribute \src "libresoc.v:104213.9-104213.17" + attribute \src "libresoc.v:105349.9-105349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162551,18 +164240,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:104267.3-104321.6" - process $proc$libresoc.v:104267$4131 + attribute \src "libresoc.v:105403.3-105457.6" + process $proc$libresoc.v:105403$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:104268.5-104268.29" + attribute \src "libresoc.v:105404.5-105404.29" switch \initial - attribute \src "libresoc.v:104268.9-104268.17" + attribute \src "libresoc.v:105404.9-105404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162634,18 +164323,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:104322.3-104376.6" - process $proc$libresoc.v:104322$4132 + attribute \src "libresoc.v:105458.3-105512.6" + process $proc$libresoc.v:105458$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:104323.5-104323.29" + attribute \src "libresoc.v:105459.5-105459.29" switch \initial - attribute \src "libresoc.v:104323.9-104323.17" + attribute \src "libresoc.v:105459.9-105459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162717,18 +164406,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:104377.3-104431.6" - process $proc$libresoc.v:104377$4133 + attribute \src "libresoc.v:105513.3-105567.6" + process $proc$libresoc.v:105513$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:104378.5-104378.29" + attribute \src "libresoc.v:105514.5-105514.29" switch \initial - attribute \src "libresoc.v:104378.9-104378.17" + attribute \src "libresoc.v:105514.9-105514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162800,18 +164489,101 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:104432.3-104486.6" - process $proc$libresoc.v:104432$4134 + attribute \src "libresoc.v:105568.3-105622.6" + process $proc$libresoc.v:105568$4164 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] + attribute \src "libresoc.v:105569.5-105569.29" + switch \initial + attribute \src "libresoc.v:105569.9-105569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] + end + attribute \src "libresoc.v:105623.3-105677.6" + process $proc$libresoc.v:105623$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:104433.5-104433.29" + attribute \src "libresoc.v:105624.5-105624.29" switch \initial - attribute \src "libresoc.v:104433.9-104433.17" + attribute \src "libresoc.v:105624.9-105624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162883,18 +164655,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:104487.3-104541.6" - process $proc$libresoc.v:104487$4135 + attribute \src "libresoc.v:105678.3-105732.6" + process $proc$libresoc.v:105678$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:104488.5-104488.29" + attribute \src "libresoc.v:105679.5-105679.29" switch \initial - attribute \src "libresoc.v:104488.9-104488.17" + attribute \src "libresoc.v:105679.9-105679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -162966,18 +164738,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:104542.3-104596.6" - process $proc$libresoc.v:104542$4136 + attribute \src "libresoc.v:105733.3-105787.6" + process $proc$libresoc.v:105733$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:104543.5-104543.29" + attribute \src "libresoc.v:105734.5-105734.29" switch \initial - attribute \src "libresoc.v:104543.9-104543.17" + attribute \src "libresoc.v:105734.9-105734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163049,184 +164821,184 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:104597.3-104651.6" - process $proc$libresoc.v:104597$4137 + attribute \src "libresoc.v:105788.3-105842.6" + process $proc$libresoc.v:105788$4168 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:104598.5-104598.29" + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:105789.5-105789.29" switch \initial - attribute \src "libresoc.v:104598.9-104598.17" + attribute \src "libresoc.v:105789.9-105789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:104652.3-104706.6" - process $proc$libresoc.v:104652$4138 + attribute \src "libresoc.v:105843.3-105897.6" + process $proc$libresoc.v:105843$4169 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104653.5-104653.29" + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:105844.5-105844.29" switch \initial - attribute \src "libresoc.v:104653.9-104653.17" + attribute \src "libresoc.v:105844.9-105844.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 end sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:104707.3-104761.6" - process $proc$libresoc.v:104707$4139 + attribute \src "libresoc.v:105898.3-105952.6" + process $proc$libresoc.v:105898$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:104708.5-104708.29" + attribute \src "libresoc.v:105899.5-105899.29" switch \initial - attribute \src "libresoc.v:104708.9-104708.17" + attribute \src "libresoc.v:105899.9-105899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163298,18 +165070,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:104762.3-104816.6" - process $proc$libresoc.v:104762$4140 + attribute \src "libresoc.v:105953.3-106007.6" + process $proc$libresoc.v:105953$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104763.5-104763.29" + attribute \src "libresoc.v:105954.5-105954.29" switch \initial - attribute \src "libresoc.v:104763.9-104763.17" + attribute \src "libresoc.v:105954.9-105954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163381,18 +165153,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:104817.3-104871.6" - process $proc$libresoc.v:104817$4141 + attribute \src "libresoc.v:106008.3-106062.6" + process $proc$libresoc.v:106008$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:104818.5-104818.29" + attribute \src "libresoc.v:106009.5-106009.29" switch \initial - attribute \src "libresoc.v:104818.9-104818.17" + attribute \src "libresoc.v:106009.9-106009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163464,18 +165236,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:104872.3-104926.6" - process $proc$libresoc.v:104872$4142 + attribute \src "libresoc.v:106063.3-106117.6" + process $proc$libresoc.v:106063$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104873.5-104873.29" + attribute \src "libresoc.v:106064.5-106064.29" switch \initial - attribute \src "libresoc.v:104873.9-104873.17" + attribute \src "libresoc.v:106064.9-106064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163547,18 +165319,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:104927.3-104981.6" - process $proc$libresoc.v:104927$4143 + attribute \src "libresoc.v:106118.3-106172.6" + process $proc$libresoc.v:106118$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:104928.5-104928.29" + attribute \src "libresoc.v:106119.5-106119.29" switch \initial - attribute \src "libresoc.v:104928.9-104928.17" + attribute \src "libresoc.v:106119.9-106119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163630,18 +165402,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:104982.3-105036.6" - process $proc$libresoc.v:104982$4144 + attribute \src "libresoc.v:106173.3-106227.6" + process $proc$libresoc.v:106173$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:104983.5-104983.29" + attribute \src "libresoc.v:106174.5-106174.29" switch \initial - attribute \src "libresoc.v:104983.9-104983.17" + attribute \src "libresoc.v:106174.9-106174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163713,18 +165485,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:105037.3-105091.6" - process $proc$libresoc.v:105037$4145 + attribute \src "libresoc.v:106228.3-106282.6" + process $proc$libresoc.v:106228$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105038.5-105038.29" + attribute \src "libresoc.v:106229.5-106229.29" switch \initial - attribute \src "libresoc.v:105038.9-105038.17" + attribute \src "libresoc.v:106229.9-106229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163796,18 +165568,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:105092.3-105146.6" - process $proc$libresoc.v:105092$4146 + attribute \src "libresoc.v:106283.3-106337.6" + process $proc$libresoc.v:106283$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105093.5-105093.29" + attribute \src "libresoc.v:106284.5-106284.29" switch \initial - attribute \src "libresoc.v:105093.9-105093.17" + attribute \src "libresoc.v:106284.9-106284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163879,18 +165651,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:105147.3-105201.6" - process $proc$libresoc.v:105147$4147 + attribute \src "libresoc.v:106338.3-106392.6" + process $proc$libresoc.v:106338$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:105148.5-105148.29" + attribute \src "libresoc.v:106339.5-106339.29" switch \initial - attribute \src "libresoc.v:105148.9-105148.17" + attribute \src "libresoc.v:106339.9-106339.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -163962,184 +165734,184 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:105202.3-105256.6" - process $proc$libresoc.v:105202$4148 + attribute \src "libresoc.v:106393.3-106447.6" + process $proc$libresoc.v:106393$4179 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105203.5-105203.29" + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:106394.5-106394.29" switch \initial - attribute \src "libresoc.v:105203.9-105203.17" + attribute \src "libresoc.v:106394.9-106394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'01000 case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'00000 end sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:105257.3-105311.6" - process $proc$libresoc.v:105257$4149 + attribute \src "libresoc.v:106448.3-106502.6" + process $proc$libresoc.v:106448$4180 assign { } { } assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105258.5-105258.29" + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:106449.5-106449.29" switch \initial - attribute \src "libresoc.v:105258.9-105258.17" + attribute \src "libresoc.v:106449.9-106449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:105312.3-105366.6" - process $proc$libresoc.v:105312$4150 + attribute \src "libresoc.v:106503.3-106557.6" + process $proc$libresoc.v:106503$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:105313.5-105313.29" + attribute \src "libresoc.v:106504.5-106504.29" switch \initial - attribute \src "libresoc.v:105313.9-105313.17" + attribute \src "libresoc.v:106504.9-106504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164211,18 +165983,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:105367.3-105421.6" - process $proc$libresoc.v:105367$4151 + attribute \src "libresoc.v:106558.3-106612.6" + process $proc$libresoc.v:106558$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105368.5-105368.29" + attribute \src "libresoc.v:106559.5-106559.29" switch \initial - attribute \src "libresoc.v:105368.9-105368.17" + attribute \src "libresoc.v:106559.9-106559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164294,18 +166066,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:105422.3-105476.6" - process $proc$libresoc.v:105422$4152 + attribute \src "libresoc.v:106613.3-106667.6" + process $proc$libresoc.v:106613$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:105423.5-105423.29" + attribute \src "libresoc.v:106614.5-106614.29" switch \initial - attribute \src "libresoc.v:105423.9-105423.17" + attribute \src "libresoc.v:106614.9-106614.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164377,18 +166149,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:105477.3-105531.6" - process $proc$libresoc.v:105477$4153 + attribute \src "libresoc.v:106668.3-106722.6" + process $proc$libresoc.v:106668$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:105478.5-105478.29" + attribute \src "libresoc.v:106669.5-106669.29" switch \initial - attribute \src "libresoc.v:105478.9-105478.17" + attribute \src "libresoc.v:106669.9-106669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164460,18 +166232,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:105532.3-105586.6" - process $proc$libresoc.v:105532$4154 + attribute \src "libresoc.v:106723.3-106777.6" + process $proc$libresoc.v:106723$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:105533.5-105533.29" + attribute \src "libresoc.v:106724.5-106724.29" switch \initial - attribute \src "libresoc.v:105533.9-105533.17" + attribute \src "libresoc.v:106724.9-106724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164543,18 +166315,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:105587.3-105641.6" - process $proc$libresoc.v:105587$4155 + attribute \src "libresoc.v:106778.3-106832.6" + process $proc$libresoc.v:106778$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:105588.5-105588.29" + attribute \src "libresoc.v:106779.5-106779.29" switch \initial - attribute \src "libresoc.v:105588.9-105588.17" + attribute \src "libresoc.v:106779.9-106779.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164626,18 +166398,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:105642.3-105696.6" - process $proc$libresoc.v:105642$4156 + attribute \src "libresoc.v:106833.3-106887.6" + process $proc$libresoc.v:106833$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:105643.5-105643.29" + attribute \src "libresoc.v:106834.5-106834.29" switch \initial - attribute \src "libresoc.v:105643.9-105643.17" + attribute \src "libresoc.v:106834.9-106834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164709,18 +166481,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:105697.3-105751.6" - process $proc$libresoc.v:105697$4157 + attribute \src "libresoc.v:106888.3-106942.6" + process $proc$libresoc.v:106888$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105698.5-105698.29" + attribute \src "libresoc.v:106889.5-106889.29" switch \initial - attribute \src "libresoc.v:105698.9-105698.17" + attribute \src "libresoc.v:106889.9-106889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164792,18 +166564,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:105752.3-105806.6" - process $proc$libresoc.v:105752$4158 + attribute \src "libresoc.v:106943.3-106997.6" + process $proc$libresoc.v:106943$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105753.5-105753.29" + attribute \src "libresoc.v:106944.5-106944.29" switch \initial - attribute \src "libresoc.v:105753.9-105753.17" + attribute \src "libresoc.v:106944.9-106944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -164877,157 +166649,161 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:105812.1-107720.10" +attribute \src "libresoc.v:107003.1-108970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:107425.3-107473.6" + attribute \src "libresoc.v:108675.3-108723.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107474.3-107522.6" + attribute \src "libresoc.v:108724.3-108772.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106837.3-106885.6" + attribute \src "libresoc.v:108087.3-108135.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:107033.3-107081.6" + attribute \src "libresoc.v:108283.3-108331.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:106200.3-106248.6" + attribute \src "libresoc.v:107401.3-107449.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106249.3-106297.6" + attribute \src "libresoc.v:107450.3-107498.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106788.3-106836.6" + attribute \src "libresoc.v:108038.3-108086.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106984.3-107032.6" + attribute \src "libresoc.v:108234.3-108282.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:107229.3-107277.6" + attribute \src "libresoc.v:108430.3-108478.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:106151.3-106199.6" + attribute \src "libresoc.v:107352.3-107400.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107523.3-107571.6" + attribute \src "libresoc.v:108773.3-108821.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107572.3-107620.6" + attribute \src "libresoc.v:108822.3-108870.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107621.3-107669.6" + attribute \src "libresoc.v:108871.3-108919.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106690.3-106738.6" + attribute \src "libresoc.v:107891.3-107939.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106886.3-106934.6" + attribute \src "libresoc.v:108136.3-108184.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106935.3-106983.6" + attribute \src "libresoc.v:108185.3-108233.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:107180.3-107228.6" + attribute \src "libresoc.v:108479.3-108527.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:106592.3-106640.6" + attribute \src "libresoc.v:107842.3-107890.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107327.3-107375.6" + attribute \src "libresoc.v:108577.3-108625.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107670.3-107718.6" + attribute \src "libresoc.v:108920.3-108968.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:106739.3-106787.6" + attribute \src "libresoc.v:107989.3-108037.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107131.3-107179.6" + attribute \src "libresoc.v:108381.3-108429.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107376.3-107424.6" + attribute \src "libresoc.v:108626.3-108674.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107278.3-107326.6" + attribute \src "libresoc.v:108528.3-108576.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107082.3-107130.6" + attribute \src "libresoc.v:108332.3-108380.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:106494.3-106542.6" + attribute \src "libresoc.v:107744.3-107792.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106543.3-106591.6" + attribute \src "libresoc.v:107793.3-107841.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106298.3-106346.6" + attribute \src "libresoc.v:107499.3-107547.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106347.3-106395.6" + attribute \src "libresoc.v:107548.3-107596.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106396.3-106444.6" + attribute \src "libresoc.v:107597.3-107645.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106445.3-106493.6" + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106641.3-106689.6" + attribute \src "libresoc.v:107940.3-107988.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:105813.7-105813.20" + attribute \src "libresoc.v:107004.7-107004.20" wire $0\initial[0:0] - attribute \src "libresoc.v:107425.3-107473.6" + attribute \src "libresoc.v:108675.3-108723.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107474.3-107522.6" + attribute \src "libresoc.v:108724.3-108772.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106837.3-106885.6" + attribute \src "libresoc.v:108087.3-108135.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:107033.3-107081.6" + attribute \src "libresoc.v:108283.3-108331.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:106200.3-106248.6" + attribute \src "libresoc.v:107401.3-107449.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106249.3-106297.6" + attribute \src "libresoc.v:107450.3-107498.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106788.3-106836.6" + attribute \src "libresoc.v:108038.3-108086.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106984.3-107032.6" + attribute \src "libresoc.v:108234.3-108282.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:107229.3-107277.6" + attribute \src "libresoc.v:108430.3-108478.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:106151.3-106199.6" + attribute \src "libresoc.v:107352.3-107400.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107523.3-107571.6" + attribute \src "libresoc.v:108773.3-108821.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107572.3-107620.6" + attribute \src "libresoc.v:108822.3-108870.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107621.3-107669.6" + attribute \src "libresoc.v:108871.3-108919.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106690.3-106738.6" + attribute \src "libresoc.v:107891.3-107939.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106886.3-106934.6" + attribute \src "libresoc.v:108136.3-108184.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106935.3-106983.6" + attribute \src "libresoc.v:108185.3-108233.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:107180.3-107228.6" + attribute \src "libresoc.v:108479.3-108527.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:106592.3-106640.6" + attribute \src "libresoc.v:107842.3-107890.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107327.3-107375.6" + attribute \src "libresoc.v:108577.3-108625.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107670.3-107718.6" + attribute \src "libresoc.v:108920.3-108968.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:106739.3-106787.6" + attribute \src "libresoc.v:107989.3-108037.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107131.3-107179.6" + attribute \src "libresoc.v:108381.3-108429.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107376.3-107424.6" + attribute \src "libresoc.v:108626.3-108674.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107278.3-107326.6" + attribute \src "libresoc.v:108528.3-108576.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107082.3-107130.6" + attribute \src "libresoc.v:108332.3-108380.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:106494.3-106542.6" + attribute \src "libresoc.v:107744.3-107792.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106543.3-106591.6" + attribute \src "libresoc.v:107793.3-107841.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106298.3-106346.6" + attribute \src "libresoc.v:107499.3-107547.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106347.3-106395.6" + attribute \src "libresoc.v:107548.3-107596.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106396.3-106444.6" + attribute \src "libresoc.v:107597.3-107645.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106445.3-106493.6" + attribute \src "libresoc.v:107695.3-107743.6" + wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107646.3-107694.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106641.3-106689.6" + attribute \src "libresoc.v:107940.3-107988.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub23_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub23_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub23_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -165037,7 +166813,7 @@ module \dec31_dec_sub23 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165046,16 +166822,16 @@ module \dec31_dec_sub23 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub23_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -165087,7 +166863,7 @@ module \dec31_dec_sub23 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -165104,7 +166880,7 @@ module \dec31_dec_sub23 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -165112,7 +166888,7 @@ module \dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -165129,13 +166905,13 @@ module \dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -165212,46 +166988,46 @@ module \dec31_dec_sub23 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub23_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub23_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub23_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165259,8 +167035,8 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub23_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub23_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165268,8 +167044,8 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub23_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub23_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -165277,7 +167053,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub23_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165286,7 +167062,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub23_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165295,7 +167071,7 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub23_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -165304,41 +167080,50 @@ module \dec31_dec_sub23 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub23_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub23_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub23_upd - attribute \src "libresoc.v:105813.7-105813.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub23_upd + attribute \src "libresoc.v:107004.7-107004.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:105813.7-105813.20" - process $proc$libresoc.v:105813$4192 + attribute \src "libresoc.v:107004.7-107004.20" + process $proc$libresoc.v:107004$4224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:106151.3-106199.6" - process $proc$libresoc.v:106151$4160 + attribute \src "libresoc.v:107352.3-107400.6" + process $proc$libresoc.v:107352$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:106152.5-106152.29" + attribute \src "libresoc.v:107353.5-107353.29" switch \initial - attribute \src "libresoc.v:106152.9-106152.17" + attribute \src "libresoc.v:107353.9-107353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165402,18 +167187,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:106200.3-106248.6" - process $proc$libresoc.v:106200$4161 + attribute \src "libresoc.v:107401.3-107449.6" + process $proc$libresoc.v:107401$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:106201.5-106201.29" + attribute \src "libresoc.v:107402.5-107402.29" switch \initial - attribute \src "libresoc.v:106201.9-106201.17" + attribute \src "libresoc.v:107402.9-107402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165477,18 +167262,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:106249.3-106297.6" - process $proc$libresoc.v:106249$4162 + attribute \src "libresoc.v:107450.3-107498.6" + process $proc$libresoc.v:107450$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106250.5-106250.29" + attribute \src "libresoc.v:107451.5-107451.29" switch \initial - attribute \src "libresoc.v:106250.9-106250.17" + attribute \src "libresoc.v:107451.9-107451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165552,18 +167337,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:106298.3-106346.6" - process $proc$libresoc.v:106298$4163 + attribute \src "libresoc.v:107499.3-107547.6" + process $proc$libresoc.v:107499$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:106299.5-106299.29" + attribute \src "libresoc.v:107500.5-107500.29" switch \initial - attribute \src "libresoc.v:106299.9-106299.17" + attribute \src "libresoc.v:107500.9-107500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165627,18 +167412,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:106347.3-106395.6" - process $proc$libresoc.v:106347$4164 + attribute \src "libresoc.v:107548.3-107596.6" + process $proc$libresoc.v:107548$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:106348.5-106348.29" + attribute \src "libresoc.v:107549.5-107549.29" switch \initial - attribute \src "libresoc.v:106348.9-106348.17" + attribute \src "libresoc.v:107549.9-107549.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165702,18 +167487,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:106396.3-106444.6" - process $proc$libresoc.v:106396$4165 + attribute \src "libresoc.v:107597.3-107645.6" + process $proc$libresoc.v:107597$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:106397.5-106397.29" + attribute \src "libresoc.v:107598.5-107598.29" switch \initial - attribute \src "libresoc.v:106397.9-106397.17" + attribute \src "libresoc.v:107598.9-107598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165777,18 +167562,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:106445.3-106493.6" - process $proc$libresoc.v:106445$4166 + attribute \src "libresoc.v:107646.3-107694.6" + process $proc$libresoc.v:107646$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:106446.5-106446.29" + attribute \src "libresoc.v:107647.5-107647.29" switch \initial - attribute \src "libresoc.v:106446.9-106446.17" + attribute \src "libresoc.v:107647.9-107647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165852,18 +167637,93 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:106494.3-106542.6" - process $proc$libresoc.v:106494$4167 + attribute \src "libresoc.v:107695.3-107743.6" + process $proc$libresoc.v:107695$4198 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] + attribute \src "libresoc.v:107696.5-107696.29" + switch \initial + attribute \src "libresoc.v:107696.9-107696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] + end + attribute \src "libresoc.v:107744.3-107792.6" + process $proc$libresoc.v:107744$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:106495.5-106495.29" + attribute \src "libresoc.v:107745.5-107745.29" switch \initial - attribute \src "libresoc.v:106495.9-106495.17" + attribute \src "libresoc.v:107745.9-107745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -165927,18 +167787,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:106543.3-106591.6" - process $proc$libresoc.v:106543$4168 + attribute \src "libresoc.v:107793.3-107841.6" + process $proc$libresoc.v:107793$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:106544.5-106544.29" + attribute \src "libresoc.v:107794.5-107794.29" switch \initial - attribute \src "libresoc.v:106544.9-106544.17" + attribute \src "libresoc.v:107794.9-107794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166002,18 +167862,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:106592.3-106640.6" - process $proc$libresoc.v:106592$4169 + attribute \src "libresoc.v:107842.3-107890.6" + process $proc$libresoc.v:107842$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:106593.5-106593.29" + attribute \src "libresoc.v:107843.5-107843.29" switch \initial - attribute \src "libresoc.v:106593.9-106593.17" + attribute \src "libresoc.v:107843.9-107843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166077,168 +167937,168 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:106641.3-106689.6" - process $proc$libresoc.v:106641$4170 + attribute \src "libresoc.v:107891.3-107939.6" + process $proc$libresoc.v:107891$4202 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:106642.5-106642.29" + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:107892.5-107892.29" switch \initial - attribute \src "libresoc.v:106642.9-106642.17" + attribute \src "libresoc.v:107892.9-107892.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:106690.3-106738.6" - process $proc$libresoc.v:106690$4171 + attribute \src "libresoc.v:107940.3-107988.6" + process $proc$libresoc.v:107940$4203 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106691.5-106691.29" + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:107941.5-107941.29" switch \initial - attribute \src "libresoc.v:106691.9-106691.17" + attribute \src "libresoc.v:107941.9-107941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 end sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:106739.3-106787.6" - process $proc$libresoc.v:106739$4172 + attribute \src "libresoc.v:107989.3-108037.6" + process $proc$libresoc.v:107989$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:106740.5-106740.29" + attribute \src "libresoc.v:107990.5-107990.29" switch \initial - attribute \src "libresoc.v:106740.9-106740.17" + attribute \src "libresoc.v:107990.9-107990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166302,18 +168162,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:106788.3-106836.6" - process $proc$libresoc.v:106788$4173 + attribute \src "libresoc.v:108038.3-108086.6" + process $proc$libresoc.v:108038$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106789.5-106789.29" + attribute \src "libresoc.v:108039.5-108039.29" switch \initial - attribute \src "libresoc.v:106789.9-106789.17" + attribute \src "libresoc.v:108039.9-108039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166377,18 +168237,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:106837.3-106885.6" - process $proc$libresoc.v:106837$4174 + attribute \src "libresoc.v:108087.3-108135.6" + process $proc$libresoc.v:108087$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:106838.5-106838.29" + attribute \src "libresoc.v:108088.5-108088.29" switch \initial - attribute \src "libresoc.v:106838.9-106838.17" + attribute \src "libresoc.v:108088.9-108088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166452,18 +168312,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:106886.3-106934.6" - process $proc$libresoc.v:106886$4175 + attribute \src "libresoc.v:108136.3-108184.6" + process $proc$libresoc.v:108136$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106887.5-106887.29" + attribute \src "libresoc.v:108137.5-108137.29" switch \initial - attribute \src "libresoc.v:106887.9-106887.17" + attribute \src "libresoc.v:108137.9-108137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166527,18 +168387,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:106935.3-106983.6" - process $proc$libresoc.v:106935$4176 + attribute \src "libresoc.v:108185.3-108233.6" + process $proc$libresoc.v:108185$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:106936.5-106936.29" + attribute \src "libresoc.v:108186.5-108186.29" switch \initial - attribute \src "libresoc.v:106936.9-106936.17" + attribute \src "libresoc.v:108186.9-108186.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166602,18 +168462,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:106984.3-107032.6" - process $proc$libresoc.v:106984$4177 + attribute \src "libresoc.v:108234.3-108282.6" + process $proc$libresoc.v:108234$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:106985.5-106985.29" + attribute \src "libresoc.v:108235.5-108235.29" switch \initial - attribute \src "libresoc.v:106985.9-106985.17" + attribute \src "libresoc.v:108235.9-108235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166677,18 +168537,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:107033.3-107081.6" - process $proc$libresoc.v:107033$4178 + attribute \src "libresoc.v:108283.3-108331.6" + process $proc$libresoc.v:108283$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107034.5-107034.29" + attribute \src "libresoc.v:108284.5-108284.29" switch \initial - attribute \src "libresoc.v:107034.9-107034.17" + attribute \src "libresoc.v:108284.9-108284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166752,18 +168612,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:107082.3-107130.6" - process $proc$libresoc.v:107082$4179 + attribute \src "libresoc.v:108332.3-108380.6" + process $proc$libresoc.v:108332$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107083.5-107083.29" + attribute \src "libresoc.v:108333.5-108333.29" switch \initial - attribute \src "libresoc.v:107083.9-107083.17" + attribute \src "libresoc.v:108333.9-108333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166827,18 +168687,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:107131.3-107179.6" - process $proc$libresoc.v:107131$4180 + attribute \src "libresoc.v:108381.3-108429.6" + process $proc$libresoc.v:108381$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:107132.5-107132.29" + attribute \src "libresoc.v:108382.5-108382.29" switch \initial - attribute \src "libresoc.v:107132.9-107132.17" + attribute \src "libresoc.v:108382.9-108382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -166902,168 +168762,168 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:107180.3-107228.6" - process $proc$libresoc.v:107180$4181 + attribute \src "libresoc.v:108430.3-108478.6" + process $proc$libresoc.v:108430$4213 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107181.5-107181.29" + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:108431.5-108431.29" switch \initial - attribute \src "libresoc.v:107181.9-107181.17" + attribute \src "libresoc.v:108431.9-108431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'01000 case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'00000 end sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:107229.3-107277.6" - process $proc$libresoc.v:107229$4182 + attribute \src "libresoc.v:108479.3-108527.6" + process $proc$libresoc.v:108479$4214 assign { } { } assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107230.5-107230.29" + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:108480.5-108480.29" switch \initial - attribute \src "libresoc.v:107230.9-107230.17" + attribute \src "libresoc.v:108480.9-108480.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:107278.3-107326.6" - process $proc$libresoc.v:107278$4183 + attribute \src "libresoc.v:108528.3-108576.6" + process $proc$libresoc.v:108528$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:107279.5-107279.29" + attribute \src "libresoc.v:108529.5-108529.29" switch \initial - attribute \src "libresoc.v:107279.9-107279.17" + attribute \src "libresoc.v:108529.9-108529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167127,18 +168987,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:107327.3-107375.6" - process $proc$libresoc.v:107327$4184 + attribute \src "libresoc.v:108577.3-108625.6" + process $proc$libresoc.v:108577$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:107328.5-107328.29" + attribute \src "libresoc.v:108578.5-108578.29" switch \initial - attribute \src "libresoc.v:107328.9-107328.17" + attribute \src "libresoc.v:108578.9-108578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167202,18 +169062,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:107376.3-107424.6" - process $proc$libresoc.v:107376$4185 + attribute \src "libresoc.v:108626.3-108674.6" + process $proc$libresoc.v:108626$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:107377.5-107377.29" + attribute \src "libresoc.v:108627.5-108627.29" switch \initial - attribute \src "libresoc.v:107377.9-107377.17" + attribute \src "libresoc.v:108627.9-108627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167277,18 +169137,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:107425.3-107473.6" - process $proc$libresoc.v:107425$4186 + attribute \src "libresoc.v:108675.3-108723.6" + process $proc$libresoc.v:108675$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:107426.5-107426.29" + attribute \src "libresoc.v:108676.5-108676.29" switch \initial - attribute \src "libresoc.v:107426.9-107426.17" + attribute \src "libresoc.v:108676.9-108676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167352,18 +169212,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:107474.3-107522.6" - process $proc$libresoc.v:107474$4187 + attribute \src "libresoc.v:108724.3-108772.6" + process $proc$libresoc.v:108724$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:107475.5-107475.29" + attribute \src "libresoc.v:108725.5-108725.29" switch \initial - attribute \src "libresoc.v:107475.9-107475.17" + attribute \src "libresoc.v:108725.9-108725.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167427,18 +169287,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:107523.3-107571.6" - process $proc$libresoc.v:107523$4188 + attribute \src "libresoc.v:108773.3-108821.6" + process $proc$libresoc.v:108773$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:107524.5-107524.29" + attribute \src "libresoc.v:108774.5-108774.29" switch \initial - attribute \src "libresoc.v:107524.9-107524.17" + attribute \src "libresoc.v:108774.9-108774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167502,18 +169362,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:107572.3-107620.6" - process $proc$libresoc.v:107572$4189 + attribute \src "libresoc.v:108822.3-108870.6" + process $proc$libresoc.v:108822$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:107573.5-107573.29" + attribute \src "libresoc.v:108823.5-108823.29" switch \initial - attribute \src "libresoc.v:107573.9-107573.17" + attribute \src "libresoc.v:108823.9-108823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167577,18 +169437,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:107621.3-107669.6" - process $proc$libresoc.v:107621$4190 + attribute \src "libresoc.v:108871.3-108919.6" + process $proc$libresoc.v:108871$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107622.5-107622.29" + attribute \src "libresoc.v:108872.5-108872.29" switch \initial - attribute \src "libresoc.v:107622.9-107622.17" + attribute \src "libresoc.v:108872.9-108872.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167652,18 +169512,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:107670.3-107718.6" - process $proc$libresoc.v:107670$4191 + attribute \src "libresoc.v:108920.3-108968.6" + process $proc$libresoc.v:108920$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107671.5-107671.29" + attribute \src "libresoc.v:108921.5-108921.29" switch \initial - attribute \src "libresoc.v:107671.9-107671.17" + attribute \src "libresoc.v:108921.9-108921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -167729,157 +169589,161 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107724.1-108672.10" +attribute \src "libresoc.v:108974.1-109951.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:108557.3-108575.6" + attribute \src "libresoc.v:109836.3-109854.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108576.3-108594.6" + attribute \src "libresoc.v:109855.3-109873.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108329.3-108347.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108405.3-108423.6" + attribute \src "libresoc.v:109684.3-109702.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108082.3-108100.6" + attribute \src "libresoc.v:109342.3-109360.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108101.3-108119.6" + attribute \src "libresoc.v:109361.3-109379.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108310.3-108328.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108386.3-108404.6" + attribute \src "libresoc.v:109665.3-109683.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108481.3-108499.6" + attribute \src "libresoc.v:109741.3-109759.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108063.3-108081.6" + attribute \src "libresoc.v:109323.3-109341.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108595.3-108613.6" + attribute \src "libresoc.v:109874.3-109892.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108614.3-108632.6" + attribute \src "libresoc.v:109893.3-109911.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108633.3-108651.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108272.3-108290.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108348.3-108366.6" + attribute \src "libresoc.v:109627.3-109645.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108367.3-108385.6" + attribute \src "libresoc.v:109646.3-109664.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108462.3-108480.6" + attribute \src "libresoc.v:109760.3-109778.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108234.3-108252.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108519.3-108537.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108652.3-108670.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108291.3-108309.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108443.3-108461.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108538.3-108556.6" + attribute \src "libresoc.v:109817.3-109835.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108500.3-108518.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108424.3-108442.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108196.3-108214.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108215.3-108233.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108120.3-108138.6" + attribute \src "libresoc.v:109380.3-109398.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108139.3-108157.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108158.3-108176.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108177.3-108195.6" + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108253.3-108271.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:107725.7-107725.20" + attribute \src "libresoc.v:108975.7-108975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108557.3-108575.6" + attribute \src "libresoc.v:109836.3-109854.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108576.3-108594.6" + attribute \src "libresoc.v:109855.3-109873.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108329.3-108347.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108405.3-108423.6" + attribute \src "libresoc.v:109684.3-109702.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108082.3-108100.6" + attribute \src "libresoc.v:109342.3-109360.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108101.3-108119.6" + attribute \src "libresoc.v:109361.3-109379.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108310.3-108328.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108386.3-108404.6" + attribute \src "libresoc.v:109665.3-109683.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108481.3-108499.6" + attribute \src "libresoc.v:109741.3-109759.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108063.3-108081.6" + attribute \src "libresoc.v:109323.3-109341.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108595.3-108613.6" + attribute \src "libresoc.v:109874.3-109892.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108614.3-108632.6" + attribute \src "libresoc.v:109893.3-109911.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108633.3-108651.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108272.3-108290.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108348.3-108366.6" + attribute \src "libresoc.v:109627.3-109645.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108367.3-108385.6" + attribute \src "libresoc.v:109646.3-109664.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108462.3-108480.6" + attribute \src "libresoc.v:109760.3-109778.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108234.3-108252.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108519.3-108537.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108652.3-108670.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108291.3-108309.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108443.3-108461.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108538.3-108556.6" + attribute \src "libresoc.v:109817.3-109835.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108500.3-108518.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108424.3-108442.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108196.3-108214.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108215.3-108233.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108120.3-108138.6" + attribute \src "libresoc.v:109380.3-109398.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108139.3-108157.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108158.3-108176.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108177.3-108195.6" + attribute \src "libresoc.v:109456.3-109474.6" + wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108253.3-108271.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub24_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub24_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub24_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -167889,7 +169753,7 @@ module \dec31_dec_sub24 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167898,16 +169762,16 @@ module \dec31_dec_sub24 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -167939,7 +169803,7 @@ module \dec31_dec_sub24 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -167956,7 +169820,7 @@ module \dec31_dec_sub24 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -167964,7 +169828,7 @@ module \dec31_dec_sub24 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167981,13 +169845,13 @@ module \dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -168064,46 +169928,46 @@ module \dec31_dec_sub24 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub24_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub24_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub24_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub24_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168111,8 +169975,8 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub24_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub24_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168120,8 +169984,8 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub24_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub24_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -168129,7 +169993,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub24_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168138,7 +170002,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub24_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168147,7 +170011,7 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub24_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -168156,41 +170020,50 @@ module \dec31_dec_sub24 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub24_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub24_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub24_upd - attribute \src "libresoc.v:107725.7-107725.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub24_upd + attribute \src "libresoc.v:108975.7-108975.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:107725.7-107725.20" - process $proc$libresoc.v:107725$4225 + attribute \src "libresoc.v:108975.7-108975.20" + process $proc$libresoc.v:108975$4258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:108063.3-108081.6" - process $proc$libresoc.v:108063$4193 + attribute \src "libresoc.v:109323.3-109341.6" + process $proc$libresoc.v:109323$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:108064.5-108064.29" + attribute \src "libresoc.v:109324.5-109324.29" switch \initial - attribute \src "libresoc.v:108064.9-108064.17" + attribute \src "libresoc.v:109324.9-109324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168214,18 +170087,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:108082.3-108100.6" - process $proc$libresoc.v:108082$4194 + attribute \src "libresoc.v:109342.3-109360.6" + process $proc$libresoc.v:109342$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:108083.5-108083.29" + attribute \src "libresoc.v:109343.5-109343.29" switch \initial - attribute \src "libresoc.v:108083.9-108083.17" + attribute \src "libresoc.v:109343.9-109343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168249,18 +170122,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:108101.3-108119.6" - process $proc$libresoc.v:108101$4195 + attribute \src "libresoc.v:109361.3-109379.6" + process $proc$libresoc.v:109361$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:108102.5-108102.29" + attribute \src "libresoc.v:109362.5-109362.29" switch \initial - attribute \src "libresoc.v:108102.9-108102.17" + attribute \src "libresoc.v:109362.9-109362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168284,18 +170157,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:108120.3-108138.6" - process $proc$libresoc.v:108120$4196 + attribute \src "libresoc.v:109380.3-109398.6" + process $proc$libresoc.v:109380$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:108121.5-108121.29" + attribute \src "libresoc.v:109381.5-109381.29" switch \initial - attribute \src "libresoc.v:108121.9-108121.17" + attribute \src "libresoc.v:109381.9-109381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168319,18 +170192,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:108139.3-108157.6" - process $proc$libresoc.v:108139$4197 + attribute \src "libresoc.v:109399.3-109417.6" + process $proc$libresoc.v:109399$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:108140.5-108140.29" + attribute \src "libresoc.v:109400.5-109400.29" switch \initial - attribute \src "libresoc.v:108140.9-108140.17" + attribute \src "libresoc.v:109400.9-109400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168354,18 +170227,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:108158.3-108176.6" - process $proc$libresoc.v:108158$4198 + attribute \src "libresoc.v:109418.3-109436.6" + process $proc$libresoc.v:109418$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:108159.5-108159.29" + attribute \src "libresoc.v:109419.5-109419.29" switch \initial - attribute \src "libresoc.v:108159.9-108159.17" + attribute \src "libresoc.v:109419.9-109419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168389,18 +170262,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:108177.3-108195.6" - process $proc$libresoc.v:108177$4199 + attribute \src "libresoc.v:109437.3-109455.6" + process $proc$libresoc.v:109437$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:108178.5-108178.29" + attribute \src "libresoc.v:109438.5-109438.29" switch \initial - attribute \src "libresoc.v:108178.9-108178.17" + attribute \src "libresoc.v:109438.9-109438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168424,18 +170297,53 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:108196.3-108214.6" - process $proc$libresoc.v:108196$4200 + attribute \src "libresoc.v:109456.3-109474.6" + process $proc$libresoc.v:109456$4232 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] + attribute \src "libresoc.v:109457.5-109457.29" + switch \initial + attribute \src "libresoc.v:109457.9-109457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] + end + attribute \src "libresoc.v:109475.3-109493.6" + process $proc$libresoc.v:109475$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:108197.5-108197.29" + attribute \src "libresoc.v:109476.5-109476.29" switch \initial - attribute \src "libresoc.v:108197.9-108197.17" + attribute \src "libresoc.v:109476.9-109476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168459,18 +170367,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:108215.3-108233.6" - process $proc$libresoc.v:108215$4201 + attribute \src "libresoc.v:109494.3-109512.6" + process $proc$libresoc.v:109494$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:108216.5-108216.29" + attribute \src "libresoc.v:109495.5-109495.29" switch \initial - attribute \src "libresoc.v:108216.9-108216.17" + attribute \src "libresoc.v:109495.9-109495.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168494,18 +170402,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:108234.3-108252.6" - process $proc$libresoc.v:108234$4202 + attribute \src "libresoc.v:109513.3-109531.6" + process $proc$libresoc.v:109513$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:108235.5-108235.29" + attribute \src "libresoc.v:109514.5-109514.29" switch \initial - attribute \src "libresoc.v:108235.9-108235.17" + attribute \src "libresoc.v:109514.9-109514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168529,88 +170437,88 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:108253.3-108271.6" - process $proc$libresoc.v:108253$4203 + attribute \src "libresoc.v:109532.3-109550.6" + process $proc$libresoc.v:109532$4236 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:108254.5-108254.29" + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:109533.5-109533.29" switch \initial - attribute \src "libresoc.v:108254.9-108254.17" + attribute \src "libresoc.v:109533.9-109533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:108272.3-108290.6" - process $proc$libresoc.v:108272$4204 + attribute \src "libresoc.v:109551.3-109569.6" + process $proc$libresoc.v:109551$4237 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:108273.5-108273.29" + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:109552.5-109552.29" switch \initial - attribute \src "libresoc.v:108273.9-108273.17" + attribute \src "libresoc.v:109552.9-109552.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 end sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:108291.3-108309.6" - process $proc$libresoc.v:108291$4205 + attribute \src "libresoc.v:109570.3-109588.6" + process $proc$libresoc.v:109570$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:108292.5-108292.29" + attribute \src "libresoc.v:109571.5-109571.29" switch \initial - attribute \src "libresoc.v:108292.9-108292.17" + attribute \src "libresoc.v:109571.9-109571.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168634,18 +170542,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:108310.3-108328.6" - process $proc$libresoc.v:108310$4206 + attribute \src "libresoc.v:109589.3-109607.6" + process $proc$libresoc.v:109589$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:108311.5-108311.29" + attribute \src "libresoc.v:109590.5-109590.29" switch \initial - attribute \src "libresoc.v:108311.9-108311.17" + attribute \src "libresoc.v:109590.9-109590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168669,18 +170577,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:108329.3-108347.6" - process $proc$libresoc.v:108329$4207 + attribute \src "libresoc.v:109608.3-109626.6" + process $proc$libresoc.v:109608$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:108330.5-108330.29" + attribute \src "libresoc.v:109609.5-109609.29" switch \initial - attribute \src "libresoc.v:108330.9-108330.17" + attribute \src "libresoc.v:109609.9-109609.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168704,18 +170612,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:108348.3-108366.6" - process $proc$libresoc.v:108348$4208 + attribute \src "libresoc.v:109627.3-109645.6" + process $proc$libresoc.v:109627$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:108349.5-108349.29" + attribute \src "libresoc.v:109628.5-109628.29" switch \initial - attribute \src "libresoc.v:108349.9-108349.17" + attribute \src "libresoc.v:109628.9-109628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168739,18 +170647,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:108367.3-108385.6" - process $proc$libresoc.v:108367$4209 + attribute \src "libresoc.v:109646.3-109664.6" + process $proc$libresoc.v:109646$4242 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:108368.5-108368.29" + attribute \src "libresoc.v:109647.5-109647.29" switch \initial - attribute \src "libresoc.v:108368.9-108368.17" + attribute \src "libresoc.v:109647.9-109647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168774,18 +170682,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:108386.3-108404.6" - process $proc$libresoc.v:108386$4210 + attribute \src "libresoc.v:109665.3-109683.6" + process $proc$libresoc.v:109665$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:108387.5-108387.29" + attribute \src "libresoc.v:109666.5-109666.29" switch \initial - attribute \src "libresoc.v:108387.9-108387.17" + attribute \src "libresoc.v:109666.9-109666.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168809,18 +170717,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:108405.3-108423.6" - process $proc$libresoc.v:108405$4211 + attribute \src "libresoc.v:109684.3-109702.6" + process $proc$libresoc.v:109684$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:108406.5-108406.29" + attribute \src "libresoc.v:109685.5-109685.29" switch \initial - attribute \src "libresoc.v:108406.9-108406.17" + attribute \src "libresoc.v:109685.9-109685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168844,18 +170752,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:108424.3-108442.6" - process $proc$libresoc.v:108424$4212 + attribute \src "libresoc.v:109703.3-109721.6" + process $proc$libresoc.v:109703$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:108425.5-108425.29" + attribute \src "libresoc.v:109704.5-109704.29" switch \initial - attribute \src "libresoc.v:108425.9-108425.17" + attribute \src "libresoc.v:109704.9-109704.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168879,18 +170787,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:108443.3-108461.6" - process $proc$libresoc.v:108443$4213 + attribute \src "libresoc.v:109722.3-109740.6" + process $proc$libresoc.v:109722$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:108444.5-108444.29" + attribute \src "libresoc.v:109723.5-109723.29" switch \initial - attribute \src "libresoc.v:108444.9-108444.17" + attribute \src "libresoc.v:109723.9-109723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -168914,88 +170822,88 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:108462.3-108480.6" - process $proc$libresoc.v:108462$4214 + attribute \src "libresoc.v:109741.3-109759.6" + process $proc$libresoc.v:109741$4247 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:108463.5-108463.29" + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:109742.5-109742.29" switch \initial - attribute \src "libresoc.v:108463.9-108463.17" + attribute \src "libresoc.v:109742.9-109742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub24_form[4:0] 5'01000 case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub24_form[4:0] 5'00000 end sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:108481.3-108499.6" - process $proc$libresoc.v:108481$4215 + attribute \src "libresoc.v:109760.3-109778.6" + process $proc$libresoc.v:109760$4248 assign { } { } assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:108482.5-108482.29" + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:109761.5-109761.29" switch \initial - attribute \src "libresoc.v:108482.9-108482.17" + attribute \src "libresoc.v:109761.9-109761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:108500.3-108518.6" - process $proc$libresoc.v:108500$4216 + attribute \src "libresoc.v:109779.3-109797.6" + process $proc$libresoc.v:109779$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:108501.5-108501.29" + attribute \src "libresoc.v:109780.5-109780.29" switch \initial - attribute \src "libresoc.v:108501.9-108501.17" + attribute \src "libresoc.v:109780.9-109780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169019,18 +170927,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:108519.3-108537.6" - process $proc$libresoc.v:108519$4217 + attribute \src "libresoc.v:109798.3-109816.6" + process $proc$libresoc.v:109798$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:108520.5-108520.29" + attribute \src "libresoc.v:109799.5-109799.29" switch \initial - attribute \src "libresoc.v:108520.9-108520.17" + attribute \src "libresoc.v:109799.9-109799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169054,18 +170962,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:108538.3-108556.6" - process $proc$libresoc.v:108538$4218 + attribute \src "libresoc.v:109817.3-109835.6" + process $proc$libresoc.v:109817$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:108539.5-108539.29" + attribute \src "libresoc.v:109818.5-109818.29" switch \initial - attribute \src "libresoc.v:108539.9-108539.17" + attribute \src "libresoc.v:109818.9-109818.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169089,18 +170997,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:108557.3-108575.6" - process $proc$libresoc.v:108557$4219 + attribute \src "libresoc.v:109836.3-109854.6" + process $proc$libresoc.v:109836$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:108558.5-108558.29" + attribute \src "libresoc.v:109837.5-109837.29" switch \initial - attribute \src "libresoc.v:108558.9-108558.17" + attribute \src "libresoc.v:109837.9-109837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169124,18 +171032,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:108576.3-108594.6" - process $proc$libresoc.v:108576$4220 + attribute \src "libresoc.v:109855.3-109873.6" + process $proc$libresoc.v:109855$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:108577.5-108577.29" + attribute \src "libresoc.v:109856.5-109856.29" switch \initial - attribute \src "libresoc.v:108577.9-108577.17" + attribute \src "libresoc.v:109856.9-109856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169159,18 +171067,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:108595.3-108613.6" - process $proc$libresoc.v:108595$4221 + attribute \src "libresoc.v:109874.3-109892.6" + process $proc$libresoc.v:109874$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:108596.5-108596.29" + attribute \src "libresoc.v:109875.5-109875.29" switch \initial - attribute \src "libresoc.v:108596.9-108596.17" + attribute \src "libresoc.v:109875.9-109875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169194,18 +171102,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:108614.3-108632.6" - process $proc$libresoc.v:108614$4222 + attribute \src "libresoc.v:109893.3-109911.6" + process $proc$libresoc.v:109893$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:108615.5-108615.29" + attribute \src "libresoc.v:109894.5-109894.29" switch \initial - attribute \src "libresoc.v:108615.9-108615.17" + attribute \src "libresoc.v:109894.9-109894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169229,18 +171137,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:108633.3-108651.6" - process $proc$libresoc.v:108633$4223 + attribute \src "libresoc.v:109912.3-109930.6" + process $proc$libresoc.v:109912$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:108634.5-108634.29" + attribute \src "libresoc.v:109913.5-109913.29" switch \initial - attribute \src "libresoc.v:108634.9-108634.17" + attribute \src "libresoc.v:109913.9-109913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169264,18 +171172,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:108652.3-108670.6" - process $proc$libresoc.v:108652$4224 + attribute \src "libresoc.v:109931.3-109949.6" + process $proc$libresoc.v:109931$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:108653.5-108653.29" + attribute \src "libresoc.v:109932.5-109932.29" switch \initial - attribute \src "libresoc.v:108653.9-108653.17" + attribute \src "libresoc.v:109932.9-109932.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -169301,157 +171209,161 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108676.1-110680.10" +attribute \src "libresoc.v:109955.1-112021.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:110367.3-110418.6" + attribute \src "libresoc.v:111708.3-111759.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110419.3-110470.6" + attribute \src "libresoc.v:111760.3-111811.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:109743.3-109794.6" + attribute \src "libresoc.v:111084.3-111135.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109951.3-110002.6" + attribute \src "libresoc.v:111292.3-111343.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109067.3-109118.6" + attribute \src "libresoc.v:110356.3-110407.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109119.3-109170.6" + attribute \src "libresoc.v:110408.3-110459.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109691.3-109742.6" + attribute \src "libresoc.v:111032.3-111083.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109899.3-109950.6" + attribute \src "libresoc.v:111240.3-111291.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:110159.3-110210.6" + attribute \src "libresoc.v:111448.3-111499.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:109015.3-109066.6" + attribute \src "libresoc.v:110304.3-110355.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110471.3-110522.6" + attribute \src "libresoc.v:111812.3-111863.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110523.3-110574.6" + attribute \src "libresoc.v:111864.3-111915.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110575.3-110626.6" + attribute \src "libresoc.v:111916.3-111967.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:109587.3-109638.6" + attribute \src "libresoc.v:110876.3-110927.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109795.3-109846.6" + attribute \src "libresoc.v:111136.3-111187.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109847.3-109898.6" + attribute \src "libresoc.v:111188.3-111239.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:110107.3-110158.6" + attribute \src "libresoc.v:111500.3-111551.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:109483.3-109534.6" + attribute \src "libresoc.v:110824.3-110875.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110263.3-110314.6" + attribute \src "libresoc.v:111604.3-111655.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110627.3-110678.6" + attribute \src "libresoc.v:111968.3-112019.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:109639.3-109690.6" + attribute \src "libresoc.v:110980.3-111031.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110055.3-110106.6" + attribute \src "libresoc.v:111396.3-111447.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110315.3-110366.6" + attribute \src "libresoc.v:111656.3-111707.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110211.3-110262.6" + attribute \src "libresoc.v:111552.3-111603.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110003.3-110054.6" + attribute \src "libresoc.v:111344.3-111395.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:109379.3-109430.6" + attribute \src "libresoc.v:110720.3-110771.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109431.3-109482.6" + attribute \src "libresoc.v:110772.3-110823.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109171.3-109222.6" + attribute \src "libresoc.v:110460.3-110511.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109223.3-109274.6" + attribute \src "libresoc.v:110512.3-110563.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109275.3-109326.6" + attribute \src "libresoc.v:110564.3-110615.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109327.3-109378.6" + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109535.3-109586.6" + attribute \src "libresoc.v:110928.3-110979.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:108677.7-108677.20" + attribute \src "libresoc.v:109956.7-109956.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110367.3-110418.6" + attribute \src "libresoc.v:111708.3-111759.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110419.3-110470.6" + attribute \src "libresoc.v:111760.3-111811.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:109743.3-109794.6" + attribute \src "libresoc.v:111084.3-111135.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109951.3-110002.6" + attribute \src "libresoc.v:111292.3-111343.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109067.3-109118.6" + attribute \src "libresoc.v:110356.3-110407.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109119.3-109170.6" + attribute \src "libresoc.v:110408.3-110459.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109691.3-109742.6" + attribute \src "libresoc.v:111032.3-111083.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109899.3-109950.6" + attribute \src "libresoc.v:111240.3-111291.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:110159.3-110210.6" + attribute \src "libresoc.v:111448.3-111499.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:109015.3-109066.6" + attribute \src "libresoc.v:110304.3-110355.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110471.3-110522.6" + attribute \src "libresoc.v:111812.3-111863.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110523.3-110574.6" + attribute \src "libresoc.v:111864.3-111915.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110575.3-110626.6" + attribute \src "libresoc.v:111916.3-111967.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:109587.3-109638.6" + attribute \src "libresoc.v:110876.3-110927.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109795.3-109846.6" + attribute \src "libresoc.v:111136.3-111187.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109847.3-109898.6" + attribute \src "libresoc.v:111188.3-111239.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:110107.3-110158.6" + attribute \src "libresoc.v:111500.3-111551.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:109483.3-109534.6" + attribute \src "libresoc.v:110824.3-110875.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110263.3-110314.6" + attribute \src "libresoc.v:111604.3-111655.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110627.3-110678.6" + attribute \src "libresoc.v:111968.3-112019.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:109639.3-109690.6" + attribute \src "libresoc.v:110980.3-111031.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110055.3-110106.6" + attribute \src "libresoc.v:111396.3-111447.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110315.3-110366.6" + attribute \src "libresoc.v:111656.3-111707.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110211.3-110262.6" + attribute \src "libresoc.v:111552.3-111603.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110003.3-110054.6" + attribute \src "libresoc.v:111344.3-111395.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:109379.3-109430.6" + attribute \src "libresoc.v:110720.3-110771.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109431.3-109482.6" + attribute \src "libresoc.v:110772.3-110823.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109171.3-109222.6" + attribute \src "libresoc.v:110460.3-110511.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109223.3-109274.6" + attribute \src "libresoc.v:110512.3-110563.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109275.3-109326.6" + attribute \src "libresoc.v:110564.3-110615.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109327.3-109378.6" + attribute \src "libresoc.v:110668.3-110719.6" + wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110616.3-110667.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109535.3-109586.6" + attribute \src "libresoc.v:110928.3-110979.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub26_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub26_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub26_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -169461,7 +171373,7 @@ module \dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -169470,16 +171382,16 @@ module \dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -169511,7 +171423,7 @@ module \dec31_dec_sub26 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -169528,7 +171440,7 @@ module \dec31_dec_sub26 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169536,7 +171448,7 @@ module \dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -169553,13 +171465,13 @@ module \dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -169636,46 +171548,46 @@ module \dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub26_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub26_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub26_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub26_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169683,8 +171595,8 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub26_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub26_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169692,8 +171604,8 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub26_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub26_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -169701,7 +171613,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub26_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169710,7 +171622,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub26_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169719,7 +171631,7 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub26_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -169728,41 +171640,50 @@ module \dec31_dec_sub26 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub26_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub26_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub26_upd - attribute \src "libresoc.v:108677.7-108677.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub26_upd + attribute \src "libresoc.v:109956.7-109956.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:108677.7-108677.20" - process $proc$libresoc.v:108677$4258 + attribute \src "libresoc.v:109956.7-109956.20" + process $proc$libresoc.v:109956$4292 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109015.3-109066.6" - process $proc$libresoc.v:109015$4226 + attribute \src "libresoc.v:110304.3-110355.6" + process $proc$libresoc.v:110304$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:109016.5-109016.29" + attribute \src "libresoc.v:110305.5-110305.29" switch \initial - attribute \src "libresoc.v:109016.9-109016.17" + attribute \src "libresoc.v:110305.9-110305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169830,18 +171751,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:109067.3-109118.6" - process $proc$libresoc.v:109067$4227 + attribute \src "libresoc.v:110356.3-110407.6" + process $proc$libresoc.v:110356$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:109068.5-109068.29" + attribute \src "libresoc.v:110357.5-110357.29" switch \initial - attribute \src "libresoc.v:109068.9-109068.17" + attribute \src "libresoc.v:110357.9-110357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169909,18 +171830,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:109119.3-109170.6" - process $proc$libresoc.v:109119$4228 + attribute \src "libresoc.v:110408.3-110459.6" + process $proc$libresoc.v:110408$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:109120.5-109120.29" + attribute \src "libresoc.v:110409.5-110409.29" switch \initial - attribute \src "libresoc.v:109120.9-109120.17" + attribute \src "libresoc.v:110409.9-110409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -169988,18 +171909,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:109171.3-109222.6" - process $proc$libresoc.v:109171$4229 + attribute \src "libresoc.v:110460.3-110511.6" + process $proc$libresoc.v:110460$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:109172.5-109172.29" + attribute \src "libresoc.v:110461.5-110461.29" switch \initial - attribute \src "libresoc.v:109172.9-109172.17" + attribute \src "libresoc.v:110461.9-110461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170067,18 +171988,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:109223.3-109274.6" - process $proc$libresoc.v:109223$4230 + attribute \src "libresoc.v:110512.3-110563.6" + process $proc$libresoc.v:110512$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:109224.5-109224.29" + attribute \src "libresoc.v:110513.5-110513.29" switch \initial - attribute \src "libresoc.v:109224.9-109224.17" + attribute \src "libresoc.v:110513.9-110513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170146,18 +172067,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:109275.3-109326.6" - process $proc$libresoc.v:109275$4231 + attribute \src "libresoc.v:110564.3-110615.6" + process $proc$libresoc.v:110564$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:109276.5-109276.29" + attribute \src "libresoc.v:110565.5-110565.29" switch \initial - attribute \src "libresoc.v:109276.9-109276.17" + attribute \src "libresoc.v:110565.9-110565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170225,18 +172146,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:109327.3-109378.6" - process $proc$libresoc.v:109327$4232 + attribute \src "libresoc.v:110616.3-110667.6" + process $proc$libresoc.v:110616$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:109328.5-109328.29" + attribute \src "libresoc.v:110617.5-110617.29" switch \initial - attribute \src "libresoc.v:109328.9-109328.17" + attribute \src "libresoc.v:110617.9-110617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170304,18 +172225,97 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:109379.3-109430.6" - process $proc$libresoc.v:109379$4233 + attribute \src "libresoc.v:110668.3-110719.6" + process $proc$libresoc.v:110668$4266 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] + attribute \src "libresoc.v:110669.5-110669.29" + switch \initial + attribute \src "libresoc.v:110669.9-110669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] + end + attribute \src "libresoc.v:110720.3-110771.6" + process $proc$libresoc.v:110720$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:109380.5-109380.29" + attribute \src "libresoc.v:110721.5-110721.29" switch \initial - attribute \src "libresoc.v:109380.9-109380.17" + attribute \src "libresoc.v:110721.9-110721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170383,18 +172383,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:109431.3-109482.6" - process $proc$libresoc.v:109431$4234 + attribute \src "libresoc.v:110772.3-110823.6" + process $proc$libresoc.v:110772$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:109432.5-109432.29" + attribute \src "libresoc.v:110773.5-110773.29" switch \initial - attribute \src "libresoc.v:109432.9-109432.17" + attribute \src "libresoc.v:110773.9-110773.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170462,18 +172462,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:109483.3-109534.6" - process $proc$libresoc.v:109483$4235 + attribute \src "libresoc.v:110824.3-110875.6" + process $proc$libresoc.v:110824$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:109484.5-109484.29" + attribute \src "libresoc.v:110825.5-110825.29" switch \initial - attribute \src "libresoc.v:109484.9-109484.17" + attribute \src "libresoc.v:110825.9-110825.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170541,176 +172541,176 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:109535.3-109586.6" - process $proc$libresoc.v:109535$4236 + attribute \src "libresoc.v:110876.3-110927.6" + process $proc$libresoc.v:110876$4270 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:109536.5-109536.29" + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:110877.5-110877.29" switch \initial - attribute \src "libresoc.v:109536.9-109536.17" + attribute \src "libresoc.v:110877.9-110877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:109587.3-109638.6" - process $proc$libresoc.v:109587$4237 + attribute \src "libresoc.v:110928.3-110979.6" + process $proc$libresoc.v:110928$4271 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109588.5-109588.29" + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:110929.5-110929.29" switch \initial - attribute \src "libresoc.v:109588.9-109588.17" + attribute \src "libresoc.v:110929.9-110929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 end sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:109639.3-109690.6" - process $proc$libresoc.v:109639$4238 + attribute \src "libresoc.v:110980.3-111031.6" + process $proc$libresoc.v:110980$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:109640.5-109640.29" + attribute \src "libresoc.v:110981.5-110981.29" switch \initial - attribute \src "libresoc.v:109640.9-109640.17" + attribute \src "libresoc.v:110981.9-110981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170778,18 +172778,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:109691.3-109742.6" - process $proc$libresoc.v:109691$4239 + attribute \src "libresoc.v:111032.3-111083.6" + process $proc$libresoc.v:111032$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109692.5-109692.29" + attribute \src "libresoc.v:111033.5-111033.29" switch \initial - attribute \src "libresoc.v:109692.9-109692.17" + attribute \src "libresoc.v:111033.9-111033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170857,18 +172857,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:109743.3-109794.6" - process $proc$libresoc.v:109743$4240 + attribute \src "libresoc.v:111084.3-111135.6" + process $proc$libresoc.v:111084$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109744.5-109744.29" + attribute \src "libresoc.v:111085.5-111085.29" switch \initial - attribute \src "libresoc.v:109744.9-109744.17" + attribute \src "libresoc.v:111085.9-111085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -170936,18 +172936,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:109795.3-109846.6" - process $proc$libresoc.v:109795$4241 + attribute \src "libresoc.v:111136.3-111187.6" + process $proc$libresoc.v:111136$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109796.5-109796.29" + attribute \src "libresoc.v:111137.5-111137.29" switch \initial - attribute \src "libresoc.v:109796.9-109796.17" + attribute \src "libresoc.v:111137.9-111137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171015,18 +173015,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:109847.3-109898.6" - process $proc$libresoc.v:109847$4242 + attribute \src "libresoc.v:111188.3-111239.6" + process $proc$libresoc.v:111188$4276 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:109848.5-109848.29" + attribute \src "libresoc.v:111189.5-111189.29" switch \initial - attribute \src "libresoc.v:109848.9-109848.17" + attribute \src "libresoc.v:111189.9-111189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171094,18 +173094,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:109899.3-109950.6" - process $proc$libresoc.v:109899$4243 + attribute \src "libresoc.v:111240.3-111291.6" + process $proc$libresoc.v:111240$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:109900.5-109900.29" + attribute \src "libresoc.v:111241.5-111241.29" switch \initial - attribute \src "libresoc.v:109900.9-109900.17" + attribute \src "libresoc.v:111241.9-111241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171173,18 +173173,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:109951.3-110002.6" - process $proc$libresoc.v:109951$4244 + attribute \src "libresoc.v:111292.3-111343.6" + process $proc$libresoc.v:111292$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109952.5-109952.29" + attribute \src "libresoc.v:111293.5-111293.29" switch \initial - attribute \src "libresoc.v:109952.9-109952.17" + attribute \src "libresoc.v:111293.9-111293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171252,18 +173252,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:110003.3-110054.6" - process $proc$libresoc.v:110003$4245 + attribute \src "libresoc.v:111344.3-111395.6" + process $proc$libresoc.v:111344$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110004.5-110004.29" + attribute \src "libresoc.v:111345.5-111345.29" switch \initial - attribute \src "libresoc.v:110004.9-110004.17" + attribute \src "libresoc.v:111345.9-111345.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171331,18 +173331,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:110055.3-110106.6" - process $proc$libresoc.v:110055$4246 + attribute \src "libresoc.v:111396.3-111447.6" + process $proc$libresoc.v:111396$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:110056.5-110056.29" + attribute \src "libresoc.v:111397.5-111397.29" switch \initial - attribute \src "libresoc.v:110056.9-110056.17" + attribute \src "libresoc.v:111397.9-111397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171410,176 +173410,176 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:110107.3-110158.6" - process $proc$libresoc.v:110107$4247 + attribute \src "libresoc.v:111448.3-111499.6" + process $proc$libresoc.v:111448$4281 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110108.5-110108.29" + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:111449.5-111449.29" switch \initial - attribute \src "libresoc.v:110108.9-110108.17" + attribute \src "libresoc.v:111449.9-111449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'10000 case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'00000 end sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:110159.3-110210.6" - process $proc$libresoc.v:110159$4248 + attribute \src "libresoc.v:111500.3-111551.6" + process $proc$libresoc.v:111500$4282 assign { } { } assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110160.5-110160.29" + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:111501.5-111501.29" switch \initial - attribute \src "libresoc.v:110160.9-110160.17" + attribute \src "libresoc.v:111501.9-111501.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:110211.3-110262.6" - process $proc$libresoc.v:110211$4249 + attribute \src "libresoc.v:111552.3-111603.6" + process $proc$libresoc.v:111552$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:110212.5-110212.29" + attribute \src "libresoc.v:111553.5-111553.29" switch \initial - attribute \src "libresoc.v:110212.9-110212.17" + attribute \src "libresoc.v:111553.9-111553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171647,18 +173647,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:110263.3-110314.6" - process $proc$libresoc.v:110263$4250 + attribute \src "libresoc.v:111604.3-111655.6" + process $proc$libresoc.v:111604$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:110264.5-110264.29" + attribute \src "libresoc.v:111605.5-111605.29" switch \initial - attribute \src "libresoc.v:110264.9-110264.17" + attribute \src "libresoc.v:111605.9-111605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171726,18 +173726,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:110315.3-110366.6" - process $proc$libresoc.v:110315$4251 + attribute \src "libresoc.v:111656.3-111707.6" + process $proc$libresoc.v:111656$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:110316.5-110316.29" + attribute \src "libresoc.v:111657.5-111657.29" switch \initial - attribute \src "libresoc.v:110316.9-110316.17" + attribute \src "libresoc.v:111657.9-111657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171805,18 +173805,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:110367.3-110418.6" - process $proc$libresoc.v:110367$4252 + attribute \src "libresoc.v:111708.3-111759.6" + process $proc$libresoc.v:111708$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:110368.5-110368.29" + attribute \src "libresoc.v:111709.5-111709.29" switch \initial - attribute \src "libresoc.v:110368.9-110368.17" + attribute \src "libresoc.v:111709.9-111709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171884,18 +173884,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:110419.3-110470.6" - process $proc$libresoc.v:110419$4253 + attribute \src "libresoc.v:111760.3-111811.6" + process $proc$libresoc.v:111760$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:110420.5-110420.29" + attribute \src "libresoc.v:111761.5-111761.29" switch \initial - attribute \src "libresoc.v:110420.9-110420.17" + attribute \src "libresoc.v:111761.9-111761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -171963,18 +173963,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:110471.3-110522.6" - process $proc$libresoc.v:110471$4254 + attribute \src "libresoc.v:111812.3-111863.6" + process $proc$libresoc.v:111812$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:110472.5-110472.29" + attribute \src "libresoc.v:111813.5-111813.29" switch \initial - attribute \src "libresoc.v:110472.9-110472.17" + attribute \src "libresoc.v:111813.9-111813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172042,18 +174042,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:110523.3-110574.6" - process $proc$libresoc.v:110523$4255 + attribute \src "libresoc.v:111864.3-111915.6" + process $proc$libresoc.v:111864$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:110524.5-110524.29" + attribute \src "libresoc.v:111865.5-111865.29" switch \initial - attribute \src "libresoc.v:110524.9-110524.17" + attribute \src "libresoc.v:111865.9-111865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172121,18 +174121,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:110575.3-110626.6" - process $proc$libresoc.v:110575$4256 + attribute \src "libresoc.v:111916.3-111967.6" + process $proc$libresoc.v:111916$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110576.5-110576.29" + attribute \src "libresoc.v:111917.5-111917.29" switch \initial - attribute \src "libresoc.v:110576.9-110576.17" + attribute \src "libresoc.v:111917.9-111917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172200,18 +174200,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:110627.3-110678.6" - process $proc$libresoc.v:110627$4257 + attribute \src "libresoc.v:111968.3-112019.6" + process $proc$libresoc.v:111968$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110628.5-110628.29" + attribute \src "libresoc.v:111969.5-111969.29" switch \initial - attribute \src "libresoc.v:110628.9-110628.17" + attribute \src "libresoc.v:111969.9-111969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -172281,157 +174281,161 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:110684.1-111632.10" +attribute \src "libresoc.v:112025.1-113002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:111517.3-111535.6" + attribute \src "libresoc.v:112887.3-112905.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111536.3-111554.6" + attribute \src "libresoc.v:112906.3-112924.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111289.3-111307.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111365.3-111383.6" + attribute \src "libresoc.v:112735.3-112753.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111042.3-111060.6" + attribute \src "libresoc.v:112393.3-112411.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111061.3-111079.6" + attribute \src "libresoc.v:112412.3-112430.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111270.3-111288.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111346.3-111364.6" + attribute \src "libresoc.v:112716.3-112734.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111441.3-111459.6" + attribute \src "libresoc.v:112792.3-112810.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111023.3-111041.6" + attribute \src "libresoc.v:112374.3-112392.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111555.3-111573.6" + attribute \src "libresoc.v:112925.3-112943.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111574.3-111592.6" + attribute \src "libresoc.v:112944.3-112962.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111593.3-111611.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111232.3-111250.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111308.3-111326.6" + attribute \src "libresoc.v:112678.3-112696.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111327.3-111345.6" + attribute \src "libresoc.v:112697.3-112715.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111422.3-111440.6" + attribute \src "libresoc.v:112811.3-112829.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111194.3-111212.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111479.3-111497.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111612.3-111630.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111251.3-111269.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111403.3-111421.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111498.3-111516.6" + attribute \src "libresoc.v:112868.3-112886.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111460.3-111478.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111384.3-111402.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111156.3-111174.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111175.3-111193.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111080.3-111098.6" + attribute \src "libresoc.v:112431.3-112449.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111099.3-111117.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111118.3-111136.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111137.3-111155.6" + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111213.3-111231.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:110685.7-110685.20" + attribute \src "libresoc.v:112026.7-112026.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111517.3-111535.6" + attribute \src "libresoc.v:112887.3-112905.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111536.3-111554.6" + attribute \src "libresoc.v:112906.3-112924.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111289.3-111307.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111365.3-111383.6" + attribute \src "libresoc.v:112735.3-112753.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111042.3-111060.6" + attribute \src "libresoc.v:112393.3-112411.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111061.3-111079.6" + attribute \src "libresoc.v:112412.3-112430.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111270.3-111288.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111346.3-111364.6" + attribute \src "libresoc.v:112716.3-112734.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111441.3-111459.6" + attribute \src "libresoc.v:112792.3-112810.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111023.3-111041.6" + attribute \src "libresoc.v:112374.3-112392.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111555.3-111573.6" + attribute \src "libresoc.v:112925.3-112943.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111574.3-111592.6" + attribute \src "libresoc.v:112944.3-112962.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111593.3-111611.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111232.3-111250.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111308.3-111326.6" + attribute \src "libresoc.v:112678.3-112696.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111327.3-111345.6" + attribute \src "libresoc.v:112697.3-112715.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111422.3-111440.6" + attribute \src "libresoc.v:112811.3-112829.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111194.3-111212.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111479.3-111497.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111612.3-111630.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111251.3-111269.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111403.3-111421.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111498.3-111516.6" + attribute \src "libresoc.v:112868.3-112886.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111460.3-111478.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111384.3-111402.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111156.3-111174.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111175.3-111193.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111080.3-111098.6" + attribute \src "libresoc.v:112431.3-112449.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111099.3-111117.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111118.3-111136.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111137.3-111155.6" + attribute \src "libresoc.v:112507.3-112525.6" + wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111213.3-111231.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub27_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub27_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub27_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -172441,7 +174445,7 @@ module \dec31_dec_sub27 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -172450,16 +174454,16 @@ module \dec31_dec_sub27 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -172491,7 +174495,7 @@ module \dec31_dec_sub27 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -172508,7 +174512,7 @@ module \dec31_dec_sub27 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -172516,7 +174520,7 @@ module \dec31_dec_sub27 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -172533,13 +174537,13 @@ module \dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -172616,46 +174620,46 @@ module \dec31_dec_sub27 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub27_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub27_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub27_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub27_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172663,8 +174667,8 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub27_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub27_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172672,8 +174676,8 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub27_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub27_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -172681,7 +174685,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub27_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172690,7 +174694,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub27_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172699,7 +174703,7 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub27_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -172708,41 +174712,50 @@ module \dec31_dec_sub27 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub27_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub27_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub27_upd - attribute \src "libresoc.v:110685.7-110685.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub27_upd + attribute \src "libresoc.v:112026.7-112026.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:110685.7-110685.20" - process $proc$libresoc.v:110685$4291 + attribute \src "libresoc.v:112026.7-112026.20" + process $proc$libresoc.v:112026$4326 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111023.3-111041.6" - process $proc$libresoc.v:111023$4259 + attribute \src "libresoc.v:112374.3-112392.6" + process $proc$libresoc.v:112374$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:111024.5-111024.29" + attribute \src "libresoc.v:112375.5-112375.29" switch \initial - attribute \src "libresoc.v:111024.9-111024.17" + attribute \src "libresoc.v:112375.9-112375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172766,18 +174779,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:111042.3-111060.6" - process $proc$libresoc.v:111042$4260 + attribute \src "libresoc.v:112393.3-112411.6" + process $proc$libresoc.v:112393$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:111043.5-111043.29" + attribute \src "libresoc.v:112394.5-112394.29" switch \initial - attribute \src "libresoc.v:111043.9-111043.17" + attribute \src "libresoc.v:112394.9-112394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172801,18 +174814,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:111061.3-111079.6" - process $proc$libresoc.v:111061$4261 + attribute \src "libresoc.v:112412.3-112430.6" + process $proc$libresoc.v:112412$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:111062.5-111062.29" + attribute \src "libresoc.v:112413.5-112413.29" switch \initial - attribute \src "libresoc.v:111062.9-111062.17" + attribute \src "libresoc.v:112413.9-112413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172836,18 +174849,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:111080.3-111098.6" - process $proc$libresoc.v:111080$4262 + attribute \src "libresoc.v:112431.3-112449.6" + process $proc$libresoc.v:112431$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:111081.5-111081.29" + attribute \src "libresoc.v:112432.5-112432.29" switch \initial - attribute \src "libresoc.v:111081.9-111081.17" + attribute \src "libresoc.v:112432.9-112432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172871,18 +174884,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:111099.3-111117.6" - process $proc$libresoc.v:111099$4263 + attribute \src "libresoc.v:112450.3-112468.6" + process $proc$libresoc.v:112450$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:111100.5-111100.29" + attribute \src "libresoc.v:112451.5-112451.29" switch \initial - attribute \src "libresoc.v:111100.9-111100.17" + attribute \src "libresoc.v:112451.9-112451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172906,18 +174919,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:111118.3-111136.6" - process $proc$libresoc.v:111118$4264 + attribute \src "libresoc.v:112469.3-112487.6" + process $proc$libresoc.v:112469$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:111119.5-111119.29" + attribute \src "libresoc.v:112470.5-112470.29" switch \initial - attribute \src "libresoc.v:111119.9-111119.17" + attribute \src "libresoc.v:112470.9-112470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172941,18 +174954,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:111137.3-111155.6" - process $proc$libresoc.v:111137$4265 + attribute \src "libresoc.v:112488.3-112506.6" + process $proc$libresoc.v:112488$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:111138.5-111138.29" + attribute \src "libresoc.v:112489.5-112489.29" switch \initial - attribute \src "libresoc.v:111138.9-111138.17" + attribute \src "libresoc.v:112489.9-112489.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -172976,18 +174989,53 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:111156.3-111174.6" - process $proc$libresoc.v:111156$4266 + attribute \src "libresoc.v:112507.3-112525.6" + process $proc$libresoc.v:112507$4300 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] + attribute \src "libresoc.v:112508.5-112508.29" + switch \initial + attribute \src "libresoc.v:112508.9-112508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] + end + attribute \src "libresoc.v:112526.3-112544.6" + process $proc$libresoc.v:112526$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:111157.5-111157.29" + attribute \src "libresoc.v:112527.5-112527.29" switch \initial - attribute \src "libresoc.v:111157.9-111157.17" + attribute \src "libresoc.v:112527.9-112527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173011,18 +175059,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:111175.3-111193.6" - process $proc$libresoc.v:111175$4267 + attribute \src "libresoc.v:112545.3-112563.6" + process $proc$libresoc.v:112545$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:111176.5-111176.29" + attribute \src "libresoc.v:112546.5-112546.29" switch \initial - attribute \src "libresoc.v:111176.9-111176.17" + attribute \src "libresoc.v:112546.9-112546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173046,18 +175094,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:111194.3-111212.6" - process $proc$libresoc.v:111194$4268 + attribute \src "libresoc.v:112564.3-112582.6" + process $proc$libresoc.v:112564$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:111195.5-111195.29" + attribute \src "libresoc.v:112565.5-112565.29" switch \initial - attribute \src "libresoc.v:111195.9-111195.17" + attribute \src "libresoc.v:112565.9-112565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173081,88 +175129,88 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:111213.3-111231.6" - process $proc$libresoc.v:111213$4269 + attribute \src "libresoc.v:112583.3-112601.6" + process $proc$libresoc.v:112583$4304 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:111214.5-111214.29" + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:112584.5-112584.29" switch \initial - attribute \src "libresoc.v:111214.9-111214.17" + attribute \src "libresoc.v:112584.9-112584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:111232.3-111250.6" - process $proc$libresoc.v:111232$4270 + attribute \src "libresoc.v:112602.3-112620.6" + process $proc$libresoc.v:112602$4305 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:111233.5-111233.29" + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:112603.5-112603.29" switch \initial - attribute \src "libresoc.v:111233.9-111233.17" + attribute \src "libresoc.v:112603.9-112603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 end sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:111251.3-111269.6" - process $proc$libresoc.v:111251$4271 + attribute \src "libresoc.v:112621.3-112639.6" + process $proc$libresoc.v:112621$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:111252.5-111252.29" + attribute \src "libresoc.v:112622.5-112622.29" switch \initial - attribute \src "libresoc.v:111252.9-111252.17" + attribute \src "libresoc.v:112622.9-112622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173186,18 +175234,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:111270.3-111288.6" - process $proc$libresoc.v:111270$4272 + attribute \src "libresoc.v:112640.3-112658.6" + process $proc$libresoc.v:112640$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:111271.5-111271.29" + attribute \src "libresoc.v:112641.5-112641.29" switch \initial - attribute \src "libresoc.v:111271.9-111271.17" + attribute \src "libresoc.v:112641.9-112641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173221,18 +175269,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:111289.3-111307.6" - process $proc$libresoc.v:111289$4273 + attribute \src "libresoc.v:112659.3-112677.6" + process $proc$libresoc.v:112659$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:111290.5-111290.29" + attribute \src "libresoc.v:112660.5-112660.29" switch \initial - attribute \src "libresoc.v:111290.9-111290.17" + attribute \src "libresoc.v:112660.9-112660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173256,18 +175304,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:111308.3-111326.6" - process $proc$libresoc.v:111308$4274 + attribute \src "libresoc.v:112678.3-112696.6" + process $proc$libresoc.v:112678$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:111309.5-111309.29" + attribute \src "libresoc.v:112679.5-112679.29" switch \initial - attribute \src "libresoc.v:111309.9-111309.17" + attribute \src "libresoc.v:112679.9-112679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173291,18 +175339,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:111327.3-111345.6" - process $proc$libresoc.v:111327$4275 + attribute \src "libresoc.v:112697.3-112715.6" + process $proc$libresoc.v:112697$4310 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:111328.5-111328.29" + attribute \src "libresoc.v:112698.5-112698.29" switch \initial - attribute \src "libresoc.v:111328.9-111328.17" + attribute \src "libresoc.v:112698.9-112698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173326,18 +175374,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:111346.3-111364.6" - process $proc$libresoc.v:111346$4276 + attribute \src "libresoc.v:112716.3-112734.6" + process $proc$libresoc.v:112716$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:111347.5-111347.29" + attribute \src "libresoc.v:112717.5-112717.29" switch \initial - attribute \src "libresoc.v:111347.9-111347.17" + attribute \src "libresoc.v:112717.9-112717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173361,18 +175409,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:111365.3-111383.6" - process $proc$libresoc.v:111365$4277 + attribute \src "libresoc.v:112735.3-112753.6" + process $proc$libresoc.v:112735$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:111366.5-111366.29" + attribute \src "libresoc.v:112736.5-112736.29" switch \initial - attribute \src "libresoc.v:111366.9-111366.17" + attribute \src "libresoc.v:112736.9-112736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173396,18 +175444,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:111384.3-111402.6" - process $proc$libresoc.v:111384$4278 + attribute \src "libresoc.v:112754.3-112772.6" + process $proc$libresoc.v:112754$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:111385.5-111385.29" + attribute \src "libresoc.v:112755.5-112755.29" switch \initial - attribute \src "libresoc.v:111385.9-111385.17" + attribute \src "libresoc.v:112755.9-112755.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173431,18 +175479,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:111403.3-111421.6" - process $proc$libresoc.v:111403$4279 + attribute \src "libresoc.v:112773.3-112791.6" + process $proc$libresoc.v:112773$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:111404.5-111404.29" + attribute \src "libresoc.v:112774.5-112774.29" switch \initial - attribute \src "libresoc.v:111404.9-111404.17" + attribute \src "libresoc.v:112774.9-112774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173466,88 +175514,88 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:111422.3-111440.6" - process $proc$libresoc.v:111422$4280 + attribute \src "libresoc.v:112792.3-112810.6" + process $proc$libresoc.v:112792$4315 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:111423.5-111423.29" + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:112793.5-112793.29" switch \initial - attribute \src "libresoc.v:111423.9-111423.17" + attribute \src "libresoc.v:112793.9-112793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub27_form[4:0] 5'00000 end sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:111441.3-111459.6" - process $proc$libresoc.v:111441$4281 + attribute \src "libresoc.v:112811.3-112829.6" + process $proc$libresoc.v:112811$4316 assign { } { } assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:111442.5-111442.29" + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:112812.5-112812.29" switch \initial - attribute \src "libresoc.v:111442.9-111442.17" + attribute \src "libresoc.v:112812.9-112812.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:111460.3-111478.6" - process $proc$libresoc.v:111460$4282 + attribute \src "libresoc.v:112830.3-112848.6" + process $proc$libresoc.v:112830$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:111461.5-111461.29" + attribute \src "libresoc.v:112831.5-112831.29" switch \initial - attribute \src "libresoc.v:111461.9-111461.17" + attribute \src "libresoc.v:112831.9-112831.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173571,18 +175619,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:111479.3-111497.6" - process $proc$libresoc.v:111479$4283 + attribute \src "libresoc.v:112849.3-112867.6" + process $proc$libresoc.v:112849$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:111480.5-111480.29" + attribute \src "libresoc.v:112850.5-112850.29" switch \initial - attribute \src "libresoc.v:111480.9-111480.17" + attribute \src "libresoc.v:112850.9-112850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173606,18 +175654,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:111498.3-111516.6" - process $proc$libresoc.v:111498$4284 + attribute \src "libresoc.v:112868.3-112886.6" + process $proc$libresoc.v:112868$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:111499.5-111499.29" + attribute \src "libresoc.v:112869.5-112869.29" switch \initial - attribute \src "libresoc.v:111499.9-111499.17" + attribute \src "libresoc.v:112869.9-112869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173641,18 +175689,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:111517.3-111535.6" - process $proc$libresoc.v:111517$4285 + attribute \src "libresoc.v:112887.3-112905.6" + process $proc$libresoc.v:112887$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:111518.5-111518.29" + attribute \src "libresoc.v:112888.5-112888.29" switch \initial - attribute \src "libresoc.v:111518.9-111518.17" + attribute \src "libresoc.v:112888.9-112888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173676,18 +175724,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:111536.3-111554.6" - process $proc$libresoc.v:111536$4286 + attribute \src "libresoc.v:112906.3-112924.6" + process $proc$libresoc.v:112906$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:111537.5-111537.29" + attribute \src "libresoc.v:112907.5-112907.29" switch \initial - attribute \src "libresoc.v:111537.9-111537.17" + attribute \src "libresoc.v:112907.9-112907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173711,18 +175759,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:111555.3-111573.6" - process $proc$libresoc.v:111555$4287 + attribute \src "libresoc.v:112925.3-112943.6" + process $proc$libresoc.v:112925$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:111556.5-111556.29" + attribute \src "libresoc.v:112926.5-112926.29" switch \initial - attribute \src "libresoc.v:111556.9-111556.17" + attribute \src "libresoc.v:112926.9-112926.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173746,18 +175794,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:111574.3-111592.6" - process $proc$libresoc.v:111574$4288 + attribute \src "libresoc.v:112944.3-112962.6" + process $proc$libresoc.v:112944$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:111575.5-111575.29" + attribute \src "libresoc.v:112945.5-112945.29" switch \initial - attribute \src "libresoc.v:111575.9-111575.17" + attribute \src "libresoc.v:112945.9-112945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173781,18 +175829,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:111593.3-111611.6" - process $proc$libresoc.v:111593$4289 + attribute \src "libresoc.v:112963.3-112981.6" + process $proc$libresoc.v:112963$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:111594.5-111594.29" + attribute \src "libresoc.v:112964.5-112964.29" switch \initial - attribute \src "libresoc.v:111594.9-111594.17" + attribute \src "libresoc.v:112964.9-112964.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173816,18 +175864,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:111612.3-111630.6" - process $proc$libresoc.v:111612$4290 + attribute \src "libresoc.v:112982.3-113000.6" + process $proc$libresoc.v:112982$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:111613.5-111613.29" + attribute \src "libresoc.v:112983.5-112983.29" switch \initial - attribute \src "libresoc.v:111613.9-111613.17" + attribute \src "libresoc.v:112983.9-112983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -173853,157 +175901,161 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:111636.1-113160.10" +attribute \src "libresoc.v:113006.1-114577.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:112937.3-112973.6" + attribute \src "libresoc.v:114354.3-114390.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112974.3-113010.6" + attribute \src "libresoc.v:114391.3-114427.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112493.3-112529.6" + attribute \src "libresoc.v:113910.3-113946.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112641.3-112677.6" + attribute \src "libresoc.v:114058.3-114094.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112012.3-112048.6" + attribute \src "libresoc.v:113392.3-113428.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112049.3-112085.6" + attribute \src "libresoc.v:113429.3-113465.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112456.3-112492.6" + attribute \src "libresoc.v:113873.3-113909.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112604.3-112640.6" + attribute \src "libresoc.v:114021.3-114057.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112789.3-112825.6" + attribute \src "libresoc.v:114169.3-114205.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111975.3-112011.6" + attribute \src "libresoc.v:113355.3-113391.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113011.3-113047.6" + attribute \src "libresoc.v:114428.3-114464.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113048.3-113084.6" + attribute \src "libresoc.v:114465.3-114501.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113085.3-113121.6" + attribute \src "libresoc.v:114502.3-114538.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:112382.3-112418.6" + attribute \src "libresoc.v:113762.3-113798.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112530.3-112566.6" + attribute \src "libresoc.v:113947.3-113983.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112567.3-112603.6" + attribute \src "libresoc.v:113984.3-114020.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112752.3-112788.6" + attribute \src "libresoc.v:114206.3-114242.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112308.3-112344.6" + attribute \src "libresoc.v:113725.3-113761.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112863.3-112899.6" + attribute \src "libresoc.v:114280.3-114316.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:113122.3-113158.6" + attribute \src "libresoc.v:114539.3-114575.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:112419.3-112455.6" + attribute \src "libresoc.v:113836.3-113872.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112715.3-112751.6" + attribute \src "libresoc.v:114132.3-114168.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112900.3-112936.6" + attribute \src "libresoc.v:114317.3-114353.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112826.3-112862.6" + attribute \src "libresoc.v:114243.3-114279.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112678.3-112714.6" + attribute \src "libresoc.v:114095.3-114131.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112234.3-112270.6" + attribute \src "libresoc.v:113651.3-113687.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112271.3-112307.6" + attribute \src "libresoc.v:113688.3-113724.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112086.3-112122.6" + attribute \src "libresoc.v:113466.3-113502.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112123.3-112159.6" + attribute \src "libresoc.v:113503.3-113539.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112160.3-112196.6" + attribute \src "libresoc.v:113540.3-113576.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112197.3-112233.6" + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112345.3-112381.6" + attribute \src "libresoc.v:113799.3-113835.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:111637.7-111637.20" + attribute \src "libresoc.v:113007.7-113007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112937.3-112973.6" + attribute \src "libresoc.v:114354.3-114390.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112974.3-113010.6" + attribute \src "libresoc.v:114391.3-114427.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112493.3-112529.6" + attribute \src "libresoc.v:113910.3-113946.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112641.3-112677.6" + attribute \src "libresoc.v:114058.3-114094.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112012.3-112048.6" + attribute \src "libresoc.v:113392.3-113428.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112049.3-112085.6" + attribute \src "libresoc.v:113429.3-113465.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112456.3-112492.6" + attribute \src "libresoc.v:113873.3-113909.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112604.3-112640.6" + attribute \src "libresoc.v:114021.3-114057.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112789.3-112825.6" + attribute \src "libresoc.v:114169.3-114205.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111975.3-112011.6" + attribute \src "libresoc.v:113355.3-113391.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113011.3-113047.6" + attribute \src "libresoc.v:114428.3-114464.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113048.3-113084.6" + attribute \src "libresoc.v:114465.3-114501.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113085.3-113121.6" + attribute \src "libresoc.v:114502.3-114538.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:112382.3-112418.6" + attribute \src "libresoc.v:113762.3-113798.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112530.3-112566.6" + attribute \src "libresoc.v:113947.3-113983.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112567.3-112603.6" + attribute \src "libresoc.v:113984.3-114020.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112752.3-112788.6" + attribute \src "libresoc.v:114206.3-114242.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112308.3-112344.6" + attribute \src "libresoc.v:113725.3-113761.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112863.3-112899.6" + attribute \src "libresoc.v:114280.3-114316.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:113122.3-113158.6" + attribute \src "libresoc.v:114539.3-114575.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:112419.3-112455.6" + attribute \src "libresoc.v:113836.3-113872.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112715.3-112751.6" + attribute \src "libresoc.v:114132.3-114168.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112900.3-112936.6" + attribute \src "libresoc.v:114317.3-114353.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112826.3-112862.6" + attribute \src "libresoc.v:114243.3-114279.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112678.3-112714.6" + attribute \src "libresoc.v:114095.3-114131.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112234.3-112270.6" + attribute \src "libresoc.v:113651.3-113687.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112271.3-112307.6" + attribute \src "libresoc.v:113688.3-113724.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112086.3-112122.6" + attribute \src "libresoc.v:113466.3-113502.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112123.3-112159.6" + attribute \src "libresoc.v:113503.3-113539.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112160.3-112196.6" + attribute \src "libresoc.v:113540.3-113576.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112197.3-112233.6" + attribute \src "libresoc.v:113614.3-113650.6" + wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113577.3-113613.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112345.3-112381.6" + attribute \src "libresoc.v:113799.3-113835.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub28_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub28_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub28_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -174013,7 +176065,7 @@ module \dec31_dec_sub28 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -174022,16 +176074,16 @@ module \dec31_dec_sub28 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub28_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -174063,7 +176115,7 @@ module \dec31_dec_sub28 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -174080,7 +176132,7 @@ module \dec31_dec_sub28 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -174088,7 +176140,7 @@ module \dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -174105,13 +176157,13 @@ module \dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -174188,46 +176240,46 @@ module \dec31_dec_sub28 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub28_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub28_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub28_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174235,8 +176287,8 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub28_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub28_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174244,8 +176296,8 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub28_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub28_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -174253,7 +176305,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub28_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174262,7 +176314,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub28_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174271,7 +176323,7 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub28_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -174280,41 +176332,50 @@ module \dec31_dec_sub28 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub28_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub28_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub28_upd - attribute \src "libresoc.v:111637.7-111637.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub28_upd + attribute \src "libresoc.v:113007.7-113007.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:111637.7-111637.20" - process $proc$libresoc.v:111637$4324 + attribute \src "libresoc.v:113007.7-113007.20" + process $proc$libresoc.v:113007$4360 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111975.3-112011.6" - process $proc$libresoc.v:111975$4292 + attribute \src "libresoc.v:113355.3-113391.6" + process $proc$libresoc.v:113355$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:111976.5-111976.29" + attribute \src "libresoc.v:113356.5-113356.29" switch \initial - attribute \src "libresoc.v:111976.9-111976.17" + attribute \src "libresoc.v:113356.9-113356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174362,18 +176423,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:112012.3-112048.6" - process $proc$libresoc.v:112012$4293 + attribute \src "libresoc.v:113392.3-113428.6" + process $proc$libresoc.v:113392$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:112013.5-112013.29" + attribute \src "libresoc.v:113393.5-113393.29" switch \initial - attribute \src "libresoc.v:112013.9-112013.17" + attribute \src "libresoc.v:113393.9-113393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174421,18 +176482,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:112049.3-112085.6" - process $proc$libresoc.v:112049$4294 + attribute \src "libresoc.v:113429.3-113465.6" + process $proc$libresoc.v:113429$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:112050.5-112050.29" + attribute \src "libresoc.v:113430.5-113430.29" switch \initial - attribute \src "libresoc.v:112050.9-112050.17" + attribute \src "libresoc.v:113430.9-113430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174480,18 +176541,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:112086.3-112122.6" - process $proc$libresoc.v:112086$4295 + attribute \src "libresoc.v:113466.3-113502.6" + process $proc$libresoc.v:113466$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:112087.5-112087.29" + attribute \src "libresoc.v:113467.5-113467.29" switch \initial - attribute \src "libresoc.v:112087.9-112087.17" + attribute \src "libresoc.v:113467.9-113467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174539,18 +176600,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:112123.3-112159.6" - process $proc$libresoc.v:112123$4296 + attribute \src "libresoc.v:113503.3-113539.6" + process $proc$libresoc.v:113503$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:112124.5-112124.29" + attribute \src "libresoc.v:113504.5-113504.29" switch \initial - attribute \src "libresoc.v:112124.9-112124.17" + attribute \src "libresoc.v:113504.9-113504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174598,18 +176659,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:112160.3-112196.6" - process $proc$libresoc.v:112160$4297 + attribute \src "libresoc.v:113540.3-113576.6" + process $proc$libresoc.v:113540$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:112161.5-112161.29" + attribute \src "libresoc.v:113541.5-113541.29" switch \initial - attribute \src "libresoc.v:112161.9-112161.17" + attribute \src "libresoc.v:113541.9-113541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174657,18 +176718,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:112197.3-112233.6" - process $proc$libresoc.v:112197$4298 + attribute \src "libresoc.v:113577.3-113613.6" + process $proc$libresoc.v:113577$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:112198.5-112198.29" + attribute \src "libresoc.v:113578.5-113578.29" switch \initial - attribute \src "libresoc.v:112198.9-112198.17" + attribute \src "libresoc.v:113578.9-113578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174716,18 +176777,77 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:112234.3-112270.6" - process $proc$libresoc.v:112234$4299 + attribute \src "libresoc.v:113614.3-113650.6" + process $proc$libresoc.v:113614$4334 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] + attribute \src "libresoc.v:113615.5-113615.29" + switch \initial + attribute \src "libresoc.v:113615.9-113615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] + end + attribute \src "libresoc.v:113651.3-113687.6" + process $proc$libresoc.v:113651$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:112235.5-112235.29" + attribute \src "libresoc.v:113652.5-113652.29" switch \initial - attribute \src "libresoc.v:112235.9-112235.17" + attribute \src "libresoc.v:113652.9-113652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174775,18 +176895,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:112271.3-112307.6" - process $proc$libresoc.v:112271$4300 + attribute \src "libresoc.v:113688.3-113724.6" + process $proc$libresoc.v:113688$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:112272.5-112272.29" + attribute \src "libresoc.v:113689.5-113689.29" switch \initial - attribute \src "libresoc.v:112272.9-112272.17" + attribute \src "libresoc.v:113689.9-113689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174834,18 +176954,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:112308.3-112344.6" - process $proc$libresoc.v:112308$4301 + attribute \src "libresoc.v:113725.3-113761.6" + process $proc$libresoc.v:113725$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112309.5-112309.29" + attribute \src "libresoc.v:113726.5-113726.29" switch \initial - attribute \src "libresoc.v:112309.9-112309.17" + attribute \src "libresoc.v:113726.9-113726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -174893,136 +177013,136 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:112345.3-112381.6" - process $proc$libresoc.v:112345$4302 + attribute \src "libresoc.v:113762.3-113798.6" + process $proc$libresoc.v:113762$4338 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:112346.5-112346.29" + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:113763.5-113763.29" switch \initial - attribute \src "libresoc.v:112346.9-112346.17" + attribute \src "libresoc.v:113763.9-113763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:112382.3-112418.6" - process $proc$libresoc.v:112382$4303 + attribute \src "libresoc.v:113799.3-113835.6" + process $proc$libresoc.v:113799$4339 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:112383.5-112383.29" + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:113800.5-113800.29" switch \initial - attribute \src "libresoc.v:112383.9-112383.17" + attribute \src "libresoc.v:113800.9-113800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 end sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:112419.3-112455.6" - process $proc$libresoc.v:112419$4304 + attribute \src "libresoc.v:113836.3-113872.6" + process $proc$libresoc.v:113836$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:112420.5-112420.29" + attribute \src "libresoc.v:113837.5-113837.29" switch \initial - attribute \src "libresoc.v:112420.9-112420.17" + attribute \src "libresoc.v:113837.9-113837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175070,18 +177190,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:112456.3-112492.6" - process $proc$libresoc.v:112456$4305 + attribute \src "libresoc.v:113873.3-113909.6" + process $proc$libresoc.v:113873$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:112457.5-112457.29" + attribute \src "libresoc.v:113874.5-113874.29" switch \initial - attribute \src "libresoc.v:112457.9-112457.17" + attribute \src "libresoc.v:113874.9-113874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175129,18 +177249,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:112493.3-112529.6" - process $proc$libresoc.v:112493$4306 + attribute \src "libresoc.v:113910.3-113946.6" + process $proc$libresoc.v:113910$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:112494.5-112494.29" + attribute \src "libresoc.v:113911.5-113911.29" switch \initial - attribute \src "libresoc.v:112494.9-112494.17" + attribute \src "libresoc.v:113911.9-113911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175188,18 +177308,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:112530.3-112566.6" - process $proc$libresoc.v:112530$4307 + attribute \src "libresoc.v:113947.3-113983.6" + process $proc$libresoc.v:113947$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:112531.5-112531.29" + attribute \src "libresoc.v:113948.5-113948.29" switch \initial - attribute \src "libresoc.v:112531.9-112531.17" + attribute \src "libresoc.v:113948.9-113948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175247,18 +177367,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:112567.3-112603.6" - process $proc$libresoc.v:112567$4308 + attribute \src "libresoc.v:113984.3-114020.6" + process $proc$libresoc.v:113984$4344 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:112568.5-112568.29" + attribute \src "libresoc.v:113985.5-113985.29" switch \initial - attribute \src "libresoc.v:112568.9-112568.17" + attribute \src "libresoc.v:113985.9-113985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175306,18 +177426,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:112604.3-112640.6" - process $proc$libresoc.v:112604$4309 + attribute \src "libresoc.v:114021.3-114057.6" + process $proc$libresoc.v:114021$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112605.5-112605.29" + attribute \src "libresoc.v:114022.5-114022.29" switch \initial - attribute \src "libresoc.v:112605.9-112605.17" + attribute \src "libresoc.v:114022.9-114022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175365,18 +177485,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:112641.3-112677.6" - process $proc$libresoc.v:112641$4310 + attribute \src "libresoc.v:114058.3-114094.6" + process $proc$libresoc.v:114058$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:112642.5-112642.29" + attribute \src "libresoc.v:114059.5-114059.29" switch \initial - attribute \src "libresoc.v:112642.9-112642.17" + attribute \src "libresoc.v:114059.9-114059.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175424,18 +177544,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:112678.3-112714.6" - process $proc$libresoc.v:112678$4311 + attribute \src "libresoc.v:114095.3-114131.6" + process $proc$libresoc.v:114095$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:112679.5-112679.29" + attribute \src "libresoc.v:114096.5-114096.29" switch \initial - attribute \src "libresoc.v:112679.9-112679.17" + attribute \src "libresoc.v:114096.9-114096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175483,18 +177603,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:112715.3-112751.6" - process $proc$libresoc.v:112715$4312 + attribute \src "libresoc.v:114132.3-114168.6" + process $proc$libresoc.v:114132$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112716.5-112716.29" + attribute \src "libresoc.v:114133.5-114133.29" switch \initial - attribute \src "libresoc.v:112716.9-112716.17" + attribute \src "libresoc.v:114133.9-114133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175542,136 +177662,136 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:112752.3-112788.6" - process $proc$libresoc.v:112752$4313 + attribute \src "libresoc.v:114169.3-114205.6" + process $proc$libresoc.v:114169$4349 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:112753.5-112753.29" + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:114170.5-114170.29" switch \initial - attribute \src "libresoc.v:112753.9-112753.17" + attribute \src "libresoc.v:114170.9-114170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'00000 end sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:112789.3-112825.6" - process $proc$libresoc.v:112789$4314 + attribute \src "libresoc.v:114206.3-114242.6" + process $proc$libresoc.v:114206$4350 assign { } { } assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:112790.5-112790.29" + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:114207.5-114207.29" switch \initial - attribute \src "libresoc.v:112790.9-112790.17" + attribute \src "libresoc.v:114207.9-114207.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:112826.3-112862.6" - process $proc$libresoc.v:112826$4315 + attribute \src "libresoc.v:114243.3-114279.6" + process $proc$libresoc.v:114243$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112827.5-112827.29" + attribute \src "libresoc.v:114244.5-114244.29" switch \initial - attribute \src "libresoc.v:112827.9-112827.17" + attribute \src "libresoc.v:114244.9-114244.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175719,18 +177839,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:112863.3-112899.6" - process $proc$libresoc.v:112863$4316 + attribute \src "libresoc.v:114280.3-114316.6" + process $proc$libresoc.v:114280$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:112864.5-112864.29" + attribute \src "libresoc.v:114281.5-114281.29" switch \initial - attribute \src "libresoc.v:112864.9-112864.17" + attribute \src "libresoc.v:114281.9-114281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175778,18 +177898,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:112900.3-112936.6" - process $proc$libresoc.v:112900$4317 + attribute \src "libresoc.v:114317.3-114353.6" + process $proc$libresoc.v:114317$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112901.5-112901.29" + attribute \src "libresoc.v:114318.5-114318.29" switch \initial - attribute \src "libresoc.v:112901.9-112901.17" + attribute \src "libresoc.v:114318.9-114318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175837,18 +177957,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:112937.3-112973.6" - process $proc$libresoc.v:112937$4318 + attribute \src "libresoc.v:114354.3-114390.6" + process $proc$libresoc.v:114354$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112938.5-112938.29" + attribute \src "libresoc.v:114355.5-114355.29" switch \initial - attribute \src "libresoc.v:112938.9-112938.17" + attribute \src "libresoc.v:114355.9-114355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175896,18 +178016,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:112974.3-113010.6" - process $proc$libresoc.v:112974$4319 + attribute \src "libresoc.v:114391.3-114427.6" + process $proc$libresoc.v:114391$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112975.5-112975.29" + attribute \src "libresoc.v:114392.5-114392.29" switch \initial - attribute \src "libresoc.v:112975.9-112975.17" + attribute \src "libresoc.v:114392.9-114392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -175955,18 +178075,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:113011.3-113047.6" - process $proc$libresoc.v:113011$4320 + attribute \src "libresoc.v:114428.3-114464.6" + process $proc$libresoc.v:114428$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:113012.5-113012.29" + attribute \src "libresoc.v:114429.5-114429.29" switch \initial - attribute \src "libresoc.v:113012.9-113012.17" + attribute \src "libresoc.v:114429.9-114429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176014,18 +178134,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:113048.3-113084.6" - process $proc$libresoc.v:113048$4321 + attribute \src "libresoc.v:114465.3-114501.6" + process $proc$libresoc.v:114465$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:113049.5-113049.29" + attribute \src "libresoc.v:114466.5-114466.29" switch \initial - attribute \src "libresoc.v:113049.9-113049.17" + attribute \src "libresoc.v:114466.9-114466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176073,18 +178193,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:113085.3-113121.6" - process $proc$libresoc.v:113085$4322 + attribute \src "libresoc.v:114502.3-114538.6" + process $proc$libresoc.v:114502$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113086.5-113086.29" + attribute \src "libresoc.v:114503.5-114503.29" switch \initial - attribute \src "libresoc.v:113086.9-113086.17" + attribute \src "libresoc.v:114503.9-114503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176132,18 +178252,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:113122.3-113158.6" - process $proc$libresoc.v:113122$4323 + attribute \src "libresoc.v:114539.3-114575.6" + process $proc$libresoc.v:114539$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113123.5-113123.29" + attribute \src "libresoc.v:114540.5-114540.29" switch \initial - attribute \src "libresoc.v:113123.9-113123.17" + attribute \src "libresoc.v:114540.9-114540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -176193,157 +178313,161 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113164.1-113920.10" +attribute \src "libresoc.v:114581.1-115360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:113841.3-113853.6" + attribute \src "libresoc.v:115281.3-115293.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113854.3-113866.6" + attribute \src "libresoc.v:115294.3-115306.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113685.3-113697.6" + attribute \src "libresoc.v:115125.3-115137.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113737.3-113749.6" + attribute \src "libresoc.v:115177.3-115189.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113516.3-113528.6" + attribute \src "libresoc.v:114943.3-114955.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113529.3-113541.6" + attribute \src "libresoc.v:114956.3-114968.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113672.3-113684.6" + attribute \src "libresoc.v:115112.3-115124.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113724.3-113736.6" + attribute \src "libresoc.v:115164.3-115176.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113789.3-113801.6" + attribute \src "libresoc.v:115216.3-115228.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113503.3-113515.6" + attribute \src "libresoc.v:114930.3-114942.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113867.3-113879.6" + attribute \src "libresoc.v:115307.3-115319.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113880.3-113892.6" + attribute \src "libresoc.v:115320.3-115332.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113893.3-113905.6" + attribute \src "libresoc.v:115333.3-115345.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113646.3-113658.6" + attribute \src "libresoc.v:115073.3-115085.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113698.3-113710.6" + attribute \src "libresoc.v:115138.3-115150.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113711.3-113723.6" + attribute \src "libresoc.v:115151.3-115163.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113776.3-113788.6" + attribute \src "libresoc.v:115229.3-115241.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113620.3-113632.6" + attribute \src "libresoc.v:115060.3-115072.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113815.3-113827.6" + attribute \src "libresoc.v:115255.3-115267.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113906.3-113918.6" + attribute \src "libresoc.v:115346.3-115358.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113659.3-113671.6" + attribute \src "libresoc.v:115099.3-115111.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113763.3-113775.6" + attribute \src "libresoc.v:115203.3-115215.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113828.3-113840.6" + attribute \src "libresoc.v:115268.3-115280.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113802.3-113814.6" + attribute \src "libresoc.v:115242.3-115254.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113750.3-113762.6" + attribute \src "libresoc.v:115190.3-115202.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113594.3-113606.6" + attribute \src "libresoc.v:115034.3-115046.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113607.3-113619.6" + attribute \src "libresoc.v:115047.3-115059.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113542.3-113554.6" + attribute \src "libresoc.v:114969.3-114981.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113555.3-113567.6" + attribute \src "libresoc.v:114982.3-114994.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113568.3-113580.6" + attribute \src "libresoc.v:114995.3-115007.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113581.3-113593.6" + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113633.3-113645.6" + attribute \src "libresoc.v:115086.3-115098.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:113165.7-113165.20" + attribute \src "libresoc.v:114582.7-114582.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113841.3-113853.6" + attribute \src "libresoc.v:115281.3-115293.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113854.3-113866.6" + attribute \src "libresoc.v:115294.3-115306.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113685.3-113697.6" + attribute \src "libresoc.v:115125.3-115137.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113737.3-113749.6" + attribute \src "libresoc.v:115177.3-115189.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113516.3-113528.6" + attribute \src "libresoc.v:114943.3-114955.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113529.3-113541.6" + attribute \src "libresoc.v:114956.3-114968.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113672.3-113684.6" + attribute \src "libresoc.v:115112.3-115124.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113724.3-113736.6" + attribute \src "libresoc.v:115164.3-115176.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113789.3-113801.6" + attribute \src "libresoc.v:115216.3-115228.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113503.3-113515.6" + attribute \src "libresoc.v:114930.3-114942.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113867.3-113879.6" + attribute \src "libresoc.v:115307.3-115319.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113880.3-113892.6" + attribute \src "libresoc.v:115320.3-115332.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113893.3-113905.6" + attribute \src "libresoc.v:115333.3-115345.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113646.3-113658.6" + attribute \src "libresoc.v:115073.3-115085.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113698.3-113710.6" + attribute \src "libresoc.v:115138.3-115150.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113711.3-113723.6" + attribute \src "libresoc.v:115151.3-115163.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113776.3-113788.6" + attribute \src "libresoc.v:115229.3-115241.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113620.3-113632.6" + attribute \src "libresoc.v:115060.3-115072.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113815.3-113827.6" + attribute \src "libresoc.v:115255.3-115267.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113906.3-113918.6" + attribute \src "libresoc.v:115346.3-115358.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113659.3-113671.6" + attribute \src "libresoc.v:115099.3-115111.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113763.3-113775.6" + attribute \src "libresoc.v:115203.3-115215.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113828.3-113840.6" + attribute \src "libresoc.v:115268.3-115280.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113802.3-113814.6" + attribute \src "libresoc.v:115242.3-115254.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113750.3-113762.6" + attribute \src "libresoc.v:115190.3-115202.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113594.3-113606.6" + attribute \src "libresoc.v:115034.3-115046.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113607.3-113619.6" + attribute \src "libresoc.v:115047.3-115059.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113542.3-113554.6" + attribute \src "libresoc.v:114969.3-114981.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113555.3-113567.6" + attribute \src "libresoc.v:114982.3-114994.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113568.3-113580.6" + attribute \src "libresoc.v:114995.3-115007.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113581.3-113593.6" + attribute \src "libresoc.v:115021.3-115033.6" + wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115008.3-115020.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113633.3-113645.6" + attribute \src "libresoc.v:115086.3-115098.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub4_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub4_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub4_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -176353,7 +178477,7 @@ module \dec31_dec_sub4 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -176362,16 +178486,16 @@ module \dec31_dec_sub4 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub4_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -176403,7 +178527,7 @@ module \dec31_dec_sub4 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -176420,7 +178544,7 @@ module \dec31_dec_sub4 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -176428,7 +178552,7 @@ module \dec31_dec_sub4 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -176445,13 +178569,13 @@ module \dec31_dec_sub4 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -176528,46 +178652,46 @@ module \dec31_dec_sub4 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub4_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub4_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub4_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub4_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176575,8 +178699,8 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub4_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub4_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176584,8 +178708,8 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub4_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub4_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -176593,7 +178717,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub4_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176602,7 +178726,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub4_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176611,7 +178735,7 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub4_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -176620,41 +178744,50 @@ module \dec31_dec_sub4 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub4_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub4_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub4_upd - attribute \src "libresoc.v:113165.7-113165.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub4_upd + attribute \src "libresoc.v:114582.7-114582.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113165.7-113165.20" - process $proc$libresoc.v:113165$4357 + attribute \src "libresoc.v:114582.7-114582.20" + process $proc$libresoc.v:114582$4394 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113503.3-113515.6" - process $proc$libresoc.v:113503$4325 + attribute \src "libresoc.v:114930.3-114942.6" + process $proc$libresoc.v:114930$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:113504.5-113504.29" + attribute \src "libresoc.v:114931.5-114931.29" switch \initial - attribute \src "libresoc.v:113504.9-113504.17" + attribute \src "libresoc.v:114931.9-114931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176670,18 +178803,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:113516.3-113528.6" - process $proc$libresoc.v:113516$4326 + attribute \src "libresoc.v:114943.3-114955.6" + process $proc$libresoc.v:114943$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:113517.5-113517.29" + attribute \src "libresoc.v:114944.5-114944.29" switch \initial - attribute \src "libresoc.v:113517.9-113517.17" + attribute \src "libresoc.v:114944.9-114944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176697,18 +178830,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:113529.3-113541.6" - process $proc$libresoc.v:113529$4327 + attribute \src "libresoc.v:114956.3-114968.6" + process $proc$libresoc.v:114956$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:113530.5-113530.29" + attribute \src "libresoc.v:114957.5-114957.29" switch \initial - attribute \src "libresoc.v:113530.9-113530.17" + attribute \src "libresoc.v:114957.9-114957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176724,18 +178857,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:113542.3-113554.6" - process $proc$libresoc.v:113542$4328 + attribute \src "libresoc.v:114969.3-114981.6" + process $proc$libresoc.v:114969$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:113543.5-113543.29" + attribute \src "libresoc.v:114970.5-114970.29" switch \initial - attribute \src "libresoc.v:113543.9-113543.17" + attribute \src "libresoc.v:114970.9-114970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176751,18 +178884,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:113555.3-113567.6" - process $proc$libresoc.v:113555$4329 + attribute \src "libresoc.v:114982.3-114994.6" + process $proc$libresoc.v:114982$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:113556.5-113556.29" + attribute \src "libresoc.v:114983.5-114983.29" switch \initial - attribute \src "libresoc.v:113556.9-113556.17" + attribute \src "libresoc.v:114983.9-114983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176778,18 +178911,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:113568.3-113580.6" - process $proc$libresoc.v:113568$4330 + attribute \src "libresoc.v:114995.3-115007.6" + process $proc$libresoc.v:114995$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:113569.5-113569.29" + attribute \src "libresoc.v:114996.5-114996.29" switch \initial - attribute \src "libresoc.v:113569.9-113569.17" + attribute \src "libresoc.v:114996.9-114996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176805,18 +178938,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:113581.3-113593.6" - process $proc$libresoc.v:113581$4331 + attribute \src "libresoc.v:115008.3-115020.6" + process $proc$libresoc.v:115008$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:113582.5-113582.29" + attribute \src "libresoc.v:115009.5-115009.29" switch \initial - attribute \src "libresoc.v:113582.9-113582.17" + attribute \src "libresoc.v:115009.9-115009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176832,18 +178965,45 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:113594.3-113606.6" - process $proc$libresoc.v:113594$4332 + attribute \src "libresoc.v:115021.3-115033.6" + process $proc$libresoc.v:115021$4368 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] + attribute \src "libresoc.v:115022.5-115022.29" + switch \initial + attribute \src "libresoc.v:115022.9-115022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] + end + attribute \src "libresoc.v:115034.3-115046.6" + process $proc$libresoc.v:115034$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:113595.5-113595.29" + attribute \src "libresoc.v:115035.5-115035.29" switch \initial - attribute \src "libresoc.v:113595.9-113595.17" + attribute \src "libresoc.v:115035.9-115035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176859,18 +179019,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:113607.3-113619.6" - process $proc$libresoc.v:113607$4333 + attribute \src "libresoc.v:115047.3-115059.6" + process $proc$libresoc.v:115047$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:113608.5-113608.29" + attribute \src "libresoc.v:115048.5-115048.29" switch \initial - attribute \src "libresoc.v:113608.9-113608.17" + attribute \src "libresoc.v:115048.9-115048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176886,18 +179046,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:113620.3-113632.6" - process $proc$libresoc.v:113620$4334 + attribute \src "libresoc.v:115060.3-115072.6" + process $proc$libresoc.v:115060$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113621.5-113621.29" + attribute \src "libresoc.v:115061.5-115061.29" switch \initial - attribute \src "libresoc.v:113621.9-113621.17" + attribute \src "libresoc.v:115061.9-115061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176913,72 +179073,72 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:113633.3-113645.6" - process $proc$libresoc.v:113633$4335 + attribute \src "libresoc.v:115073.3-115085.6" + process $proc$libresoc.v:115073$4372 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:113634.5-113634.29" + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:115074.5-115074.29" switch \initial - attribute \src "libresoc.v:113634.9-113634.17" + attribute \src "libresoc.v:115074.9-115074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:113646.3-113658.6" - process $proc$libresoc.v:113646$4336 + attribute \src "libresoc.v:115086.3-115098.6" + process $proc$libresoc.v:115086$4373 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:113647.5-113647.29" + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:115087.5-115087.29" switch \initial - attribute \src "libresoc.v:113647.9-113647.17" + attribute \src "libresoc.v:115087.9-115087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub4_upd[1:0] 2'00 end sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:113659.3-113671.6" - process $proc$libresoc.v:113659$4337 + attribute \src "libresoc.v:115099.3-115111.6" + process $proc$libresoc.v:115099$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113660.5-113660.29" + attribute \src "libresoc.v:115100.5-115100.29" switch \initial - attribute \src "libresoc.v:113660.9-113660.17" + attribute \src "libresoc.v:115100.9-115100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -176994,18 +179154,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:113672.3-113684.6" - process $proc$libresoc.v:113672$4338 + attribute \src "libresoc.v:115112.3-115124.6" + process $proc$libresoc.v:115112$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:113673.5-113673.29" + attribute \src "libresoc.v:115113.5-115113.29" switch \initial - attribute \src "libresoc.v:113673.9-113673.17" + attribute \src "libresoc.v:115113.9-115113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177021,18 +179181,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:113685.3-113697.6" - process $proc$libresoc.v:113685$4339 + attribute \src "libresoc.v:115125.3-115137.6" + process $proc$libresoc.v:115125$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:113686.5-113686.29" + attribute \src "libresoc.v:115126.5-115126.29" switch \initial - attribute \src "libresoc.v:113686.9-113686.17" + attribute \src "libresoc.v:115126.9-115126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177048,18 +179208,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:113698.3-113710.6" - process $proc$libresoc.v:113698$4340 + attribute \src "libresoc.v:115138.3-115150.6" + process $proc$libresoc.v:115138$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:113699.5-113699.29" + attribute \src "libresoc.v:115139.5-115139.29" switch \initial - attribute \src "libresoc.v:113699.9-113699.17" + attribute \src "libresoc.v:115139.9-115139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177075,18 +179235,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:113711.3-113723.6" - process $proc$libresoc.v:113711$4341 + attribute \src "libresoc.v:115151.3-115163.6" + process $proc$libresoc.v:115151$4378 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113712.5-113712.29" + attribute \src "libresoc.v:115152.5-115152.29" switch \initial - attribute \src "libresoc.v:113712.9-113712.17" + attribute \src "libresoc.v:115152.9-115152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177102,18 +179262,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:113724.3-113736.6" - process $proc$libresoc.v:113724$4342 + attribute \src "libresoc.v:115164.3-115176.6" + process $proc$libresoc.v:115164$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113725.5-113725.29" + attribute \src "libresoc.v:115165.5-115165.29" switch \initial - attribute \src "libresoc.v:113725.9-113725.17" + attribute \src "libresoc.v:115165.9-115165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177129,18 +179289,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:113737.3-113749.6" - process $proc$libresoc.v:113737$4343 + attribute \src "libresoc.v:115177.3-115189.6" + process $proc$libresoc.v:115177$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:113738.5-113738.29" + attribute \src "libresoc.v:115178.5-115178.29" switch \initial - attribute \src "libresoc.v:113738.9-113738.17" + attribute \src "libresoc.v:115178.9-115178.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177156,18 +179316,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:113750.3-113762.6" - process $proc$libresoc.v:113750$4344 + attribute \src "libresoc.v:115190.3-115202.6" + process $proc$libresoc.v:115190$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:113751.5-113751.29" + attribute \src "libresoc.v:115191.5-115191.29" switch \initial - attribute \src "libresoc.v:113751.9-113751.17" + attribute \src "libresoc.v:115191.9-115191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177183,18 +179343,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:113763.3-113775.6" - process $proc$libresoc.v:113763$4345 + attribute \src "libresoc.v:115203.3-115215.6" + process $proc$libresoc.v:115203$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113764.5-113764.29" + attribute \src "libresoc.v:115204.5-115204.29" switch \initial - attribute \src "libresoc.v:113764.9-113764.17" + attribute \src "libresoc.v:115204.9-115204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177210,72 +179370,72 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:113776.3-113788.6" - process $proc$libresoc.v:113776$4346 + attribute \src "libresoc.v:115216.3-115228.6" + process $proc$libresoc.v:115216$4383 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113777.5-113777.29" + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:115217.5-115217.29" switch \initial - attribute \src "libresoc.v:113777.9-113777.17" + attribute \src "libresoc.v:115217.9-115217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + assign $1\dec31_dec_sub4_form[4:0] 5'01000 case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub4_form[4:0] 5'00000 end sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:113789.3-113801.6" - process $proc$libresoc.v:113789$4347 + attribute \src "libresoc.v:115229.3-115241.6" + process $proc$libresoc.v:115229$4384 assign { } { } assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113790.5-113790.29" + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:115230.5-115230.29" switch \initial - attribute \src "libresoc.v:113790.9-113790.17" + attribute \src "libresoc.v:115230.9-115230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:113802.3-113814.6" - process $proc$libresoc.v:113802$4348 + attribute \src "libresoc.v:115242.3-115254.6" + process $proc$libresoc.v:115242$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113803.5-113803.29" + attribute \src "libresoc.v:115243.5-115243.29" switch \initial - attribute \src "libresoc.v:113803.9-113803.17" + attribute \src "libresoc.v:115243.9-115243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177291,18 +179451,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:113815.3-113827.6" - process $proc$libresoc.v:113815$4349 + attribute \src "libresoc.v:115255.3-115267.6" + process $proc$libresoc.v:115255$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113816.5-113816.29" + attribute \src "libresoc.v:115256.5-115256.29" switch \initial - attribute \src "libresoc.v:113816.9-113816.17" + attribute \src "libresoc.v:115256.9-115256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177318,18 +179478,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:113828.3-113840.6" - process $proc$libresoc.v:113828$4350 + attribute \src "libresoc.v:115268.3-115280.6" + process $proc$libresoc.v:115268$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113829.5-113829.29" + attribute \src "libresoc.v:115269.5-115269.29" switch \initial - attribute \src "libresoc.v:113829.9-113829.17" + attribute \src "libresoc.v:115269.9-115269.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177345,18 +179505,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:113841.3-113853.6" - process $proc$libresoc.v:113841$4351 + attribute \src "libresoc.v:115281.3-115293.6" + process $proc$libresoc.v:115281$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113842.5-113842.29" + attribute \src "libresoc.v:115282.5-115282.29" switch \initial - attribute \src "libresoc.v:113842.9-113842.17" + attribute \src "libresoc.v:115282.9-115282.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177372,18 +179532,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:113854.3-113866.6" - process $proc$libresoc.v:113854$4352 + attribute \src "libresoc.v:115294.3-115306.6" + process $proc$libresoc.v:115294$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113855.5-113855.29" + attribute \src "libresoc.v:115295.5-115295.29" switch \initial - attribute \src "libresoc.v:113855.9-113855.17" + attribute \src "libresoc.v:115295.9-115295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177399,18 +179559,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:113867.3-113879.6" - process $proc$libresoc.v:113867$4353 + attribute \src "libresoc.v:115307.3-115319.6" + process $proc$libresoc.v:115307$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113868.5-113868.29" + attribute \src "libresoc.v:115308.5-115308.29" switch \initial - attribute \src "libresoc.v:113868.9-113868.17" + attribute \src "libresoc.v:115308.9-115308.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177426,18 +179586,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:113880.3-113892.6" - process $proc$libresoc.v:113880$4354 + attribute \src "libresoc.v:115320.3-115332.6" + process $proc$libresoc.v:115320$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113881.5-113881.29" + attribute \src "libresoc.v:115321.5-115321.29" switch \initial - attribute \src "libresoc.v:113881.9-113881.17" + attribute \src "libresoc.v:115321.9-115321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177453,18 +179613,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:113893.3-113905.6" - process $proc$libresoc.v:113893$4355 + attribute \src "libresoc.v:115333.3-115345.6" + process $proc$libresoc.v:115333$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113894.5-113894.29" + attribute \src "libresoc.v:115334.5-115334.29" switch \initial - attribute \src "libresoc.v:113894.9-113894.17" + attribute \src "libresoc.v:115334.9-115334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177480,18 +179640,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:113906.3-113918.6" - process $proc$libresoc.v:113906$4356 + attribute \src "libresoc.v:115346.3-115358.6" + process $proc$libresoc.v:115346$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:113907.5-113907.29" + attribute \src "libresoc.v:115347.5-115347.29" switch \initial - attribute \src "libresoc.v:113907.9-113907.17" + attribute \src "libresoc.v:115347.9-115347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -177509,157 +179669,161 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113924.1-115640.10" +attribute \src "libresoc.v:115364.1-117133.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:115381.3-115423.6" + attribute \src "libresoc.v:116874.3-116916.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115424.3-115466.6" + attribute \src "libresoc.v:116917.3-116959.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114865.3-114907.6" + attribute \src "libresoc.v:116358.3-116400.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:115037.3-115079.6" + attribute \src "libresoc.v:116530.3-116572.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:114306.3-114348.6" + attribute \src "libresoc.v:115756.3-115798.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114349.3-114391.6" + attribute \src "libresoc.v:115799.3-115841.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114822.3-114864.6" + attribute \src "libresoc.v:116315.3-116357.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114994.3-115036.6" + attribute \src "libresoc.v:116487.3-116529.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:115209.3-115251.6" + attribute \src "libresoc.v:116659.3-116701.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:114263.3-114305.6" + attribute \src "libresoc.v:115713.3-115755.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115467.3-115509.6" + attribute \src "libresoc.v:116960.3-117002.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115510.3-115552.6" + attribute \src "libresoc.v:117003.3-117045.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115553.3-115595.6" + attribute \src "libresoc.v:117046.3-117088.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:114736.3-114778.6" + attribute \src "libresoc.v:116186.3-116228.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114908.3-114950.6" + attribute \src "libresoc.v:116401.3-116443.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114951.3-114993.6" + attribute \src "libresoc.v:116444.3-116486.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:115166.3-115208.6" + attribute \src "libresoc.v:116702.3-116744.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:114650.3-114692.6" + attribute \src "libresoc.v:116143.3-116185.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:115295.3-115337.6" + attribute \src "libresoc.v:116788.3-116830.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115596.3-115638.6" + attribute \src "libresoc.v:117089.3-117131.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:114779.3-114821.6" + attribute \src "libresoc.v:116272.3-116314.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:115123.3-115165.6" + attribute \src "libresoc.v:116616.3-116658.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115338.3-115380.6" + attribute \src "libresoc.v:116831.3-116873.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115252.3-115294.6" + attribute \src "libresoc.v:116745.3-116787.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115080.3-115122.6" + attribute \src "libresoc.v:116573.3-116615.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:114564.3-114606.6" + attribute \src "libresoc.v:116057.3-116099.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114607.3-114649.6" + attribute \src "libresoc.v:116100.3-116142.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114392.3-114434.6" + attribute \src "libresoc.v:115842.3-115884.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114435.3-114477.6" + attribute \src "libresoc.v:115885.3-115927.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114478.3-114520.6" + attribute \src "libresoc.v:115928.3-115970.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114521.3-114563.6" + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114693.3-114735.6" + attribute \src "libresoc.v:116229.3-116271.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:113925.7-113925.20" + attribute \src "libresoc.v:115365.7-115365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115381.3-115423.6" + attribute \src "libresoc.v:116874.3-116916.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115424.3-115466.6" + attribute \src "libresoc.v:116917.3-116959.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114865.3-114907.6" + attribute \src "libresoc.v:116358.3-116400.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:115037.3-115079.6" + attribute \src "libresoc.v:116530.3-116572.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:114306.3-114348.6" + attribute \src "libresoc.v:115756.3-115798.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114349.3-114391.6" + attribute \src "libresoc.v:115799.3-115841.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114822.3-114864.6" + attribute \src "libresoc.v:116315.3-116357.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114994.3-115036.6" + attribute \src "libresoc.v:116487.3-116529.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:115209.3-115251.6" + attribute \src "libresoc.v:116659.3-116701.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:114263.3-114305.6" + attribute \src "libresoc.v:115713.3-115755.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115467.3-115509.6" + attribute \src "libresoc.v:116960.3-117002.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115510.3-115552.6" + attribute \src "libresoc.v:117003.3-117045.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115553.3-115595.6" + attribute \src "libresoc.v:117046.3-117088.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:114736.3-114778.6" + attribute \src "libresoc.v:116186.3-116228.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114908.3-114950.6" + attribute \src "libresoc.v:116401.3-116443.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114951.3-114993.6" + attribute \src "libresoc.v:116444.3-116486.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:115166.3-115208.6" + attribute \src "libresoc.v:116702.3-116744.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:114650.3-114692.6" + attribute \src "libresoc.v:116143.3-116185.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:115295.3-115337.6" + attribute \src "libresoc.v:116788.3-116830.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115596.3-115638.6" + attribute \src "libresoc.v:117089.3-117131.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:114779.3-114821.6" + attribute \src "libresoc.v:116272.3-116314.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:115123.3-115165.6" + attribute \src "libresoc.v:116616.3-116658.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115338.3-115380.6" + attribute \src "libresoc.v:116831.3-116873.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115252.3-115294.6" + attribute \src "libresoc.v:116745.3-116787.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115080.3-115122.6" + attribute \src "libresoc.v:116573.3-116615.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:114564.3-114606.6" + attribute \src "libresoc.v:116057.3-116099.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114607.3-114649.6" + attribute \src "libresoc.v:116100.3-116142.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114392.3-114434.6" + attribute \src "libresoc.v:115842.3-115884.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114435.3-114477.6" + attribute \src "libresoc.v:115885.3-115927.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114478.3-114520.6" + attribute \src "libresoc.v:115928.3-115970.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114521.3-114563.6" + attribute \src "libresoc.v:116014.3-116056.6" + wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:115971.3-116013.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114693.3-114735.6" + attribute \src "libresoc.v:116229.3-116271.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub8_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub8_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub8_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -177669,7 +179833,7 @@ module \dec31_dec_sub8 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -177678,16 +179842,16 @@ module \dec31_dec_sub8 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub8_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -177719,7 +179883,7 @@ module \dec31_dec_sub8 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -177736,7 +179900,7 @@ module \dec31_dec_sub8 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -177744,7 +179908,7 @@ module \dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -177761,13 +179925,13 @@ module \dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -177844,46 +180008,46 @@ module \dec31_dec_sub8 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub8_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub8_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub8_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub8_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177891,8 +180055,8 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub8_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub8_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177900,8 +180064,8 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub8_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub8_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -177909,7 +180073,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub8_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177918,7 +180082,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub8_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177927,7 +180091,7 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub8_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -177936,41 +180100,50 @@ module \dec31_dec_sub8 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub8_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub8_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub8_upd - attribute \src "libresoc.v:113925.7-113925.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub8_upd + attribute \src "libresoc.v:115365.7-115365.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113925.7-113925.20" - process $proc$libresoc.v:113925$4390 + attribute \src "libresoc.v:115365.7-115365.20" + process $proc$libresoc.v:115365$4428 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114263.3-114305.6" - process $proc$libresoc.v:114263$4358 + attribute \src "libresoc.v:115713.3-115755.6" + process $proc$libresoc.v:115713$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:114264.5-114264.29" + attribute \src "libresoc.v:115714.5-115714.29" switch \initial - attribute \src "libresoc.v:114264.9-114264.17" + attribute \src "libresoc.v:115714.9-115714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178026,18 +180199,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:114306.3-114348.6" - process $proc$libresoc.v:114306$4359 + attribute \src "libresoc.v:115756.3-115798.6" + process $proc$libresoc.v:115756$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:114307.5-114307.29" + attribute \src "libresoc.v:115757.5-115757.29" switch \initial - attribute \src "libresoc.v:114307.9-114307.17" + attribute \src "libresoc.v:115757.9-115757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178093,18 +180266,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:114349.3-114391.6" - process $proc$libresoc.v:114349$4360 + attribute \src "libresoc.v:115799.3-115841.6" + process $proc$libresoc.v:115799$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114350.5-114350.29" + attribute \src "libresoc.v:115800.5-115800.29" switch \initial - attribute \src "libresoc.v:114350.9-114350.17" + attribute \src "libresoc.v:115800.9-115800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178160,18 +180333,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:114392.3-114434.6" - process $proc$libresoc.v:114392$4361 + attribute \src "libresoc.v:115842.3-115884.6" + process $proc$libresoc.v:115842$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:114393.5-114393.29" + attribute \src "libresoc.v:115843.5-115843.29" switch \initial - attribute \src "libresoc.v:114393.9-114393.17" + attribute \src "libresoc.v:115843.9-115843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178227,18 +180400,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:114435.3-114477.6" - process $proc$libresoc.v:114435$4362 + attribute \src "libresoc.v:115885.3-115927.6" + process $proc$libresoc.v:115885$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:114436.5-114436.29" + attribute \src "libresoc.v:115886.5-115886.29" switch \initial - attribute \src "libresoc.v:114436.9-114436.17" + attribute \src "libresoc.v:115886.9-115886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178294,18 +180467,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:114478.3-114520.6" - process $proc$libresoc.v:114478$4363 + attribute \src "libresoc.v:115928.3-115970.6" + process $proc$libresoc.v:115928$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:114479.5-114479.29" + attribute \src "libresoc.v:115929.5-115929.29" switch \initial - attribute \src "libresoc.v:114479.9-114479.17" + attribute \src "libresoc.v:115929.9-115929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178361,18 +180534,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:114521.3-114563.6" - process $proc$libresoc.v:114521$4364 + attribute \src "libresoc.v:115971.3-116013.6" + process $proc$libresoc.v:115971$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:114522.5-114522.29" + attribute \src "libresoc.v:115972.5-115972.29" switch \initial - attribute \src "libresoc.v:114522.9-114522.17" + attribute \src "libresoc.v:115972.9-115972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178428,18 +180601,85 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:114564.3-114606.6" - process $proc$libresoc.v:114564$4365 + attribute \src "libresoc.v:116014.3-116056.6" + process $proc$libresoc.v:116014$4402 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] + attribute \src "libresoc.v:116015.5-116015.29" + switch \initial + attribute \src "libresoc.v:116015.9-116015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] + end + attribute \src "libresoc.v:116057.3-116099.6" + process $proc$libresoc.v:116057$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:114565.5-114565.29" + attribute \src "libresoc.v:116058.5-116058.29" switch \initial - attribute \src "libresoc.v:114565.9-114565.17" + attribute \src "libresoc.v:116058.9-116058.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178495,18 +180735,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:114607.3-114649.6" - process $proc$libresoc.v:114607$4366 + attribute \src "libresoc.v:116100.3-116142.6" + process $proc$libresoc.v:116100$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:114608.5-114608.29" + attribute \src "libresoc.v:116101.5-116101.29" switch \initial - attribute \src "libresoc.v:114608.9-114608.17" + attribute \src "libresoc.v:116101.9-116101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178562,18 +180802,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:114650.3-114692.6" - process $proc$libresoc.v:114650$4367 + attribute \src "libresoc.v:116143.3-116185.6" + process $proc$libresoc.v:116143$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:114651.5-114651.29" + attribute \src "libresoc.v:116144.5-116144.29" switch \initial - attribute \src "libresoc.v:114651.9-114651.17" + attribute \src "libresoc.v:116144.9-116144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178629,152 +180869,152 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:114693.3-114735.6" - process $proc$libresoc.v:114693$4368 + attribute \src "libresoc.v:116186.3-116228.6" + process $proc$libresoc.v:116186$4406 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:114694.5-114694.29" + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:116187.5-116187.29" switch \initial - attribute \src "libresoc.v:114694.9-114694.17" + attribute \src "libresoc.v:116187.9-116187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:114736.3-114778.6" - process $proc$libresoc.v:114736$4369 + attribute \src "libresoc.v:116229.3-116271.6" + process $proc$libresoc.v:116229$4407 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114737.5-114737.29" + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:116230.5-116230.29" switch \initial - attribute \src "libresoc.v:114737.9-114737.17" + attribute \src "libresoc.v:116230.9-116230.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub8_upd[1:0] 2'00 end sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:114779.3-114821.6" - process $proc$libresoc.v:114779$4370 + attribute \src "libresoc.v:116272.3-116314.6" + process $proc$libresoc.v:116272$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:114780.5-114780.29" + attribute \src "libresoc.v:116273.5-116273.29" switch \initial - attribute \src "libresoc.v:114780.9-114780.17" + attribute \src "libresoc.v:116273.9-116273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178830,18 +181070,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:114822.3-114864.6" - process $proc$libresoc.v:114822$4371 + attribute \src "libresoc.v:116315.3-116357.6" + process $proc$libresoc.v:116315$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114823.5-114823.29" + attribute \src "libresoc.v:116316.5-116316.29" switch \initial - attribute \src "libresoc.v:114823.9-114823.17" + attribute \src "libresoc.v:116316.9-116316.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178897,18 +181137,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:114865.3-114907.6" - process $proc$libresoc.v:114865$4372 + attribute \src "libresoc.v:116358.3-116400.6" + process $proc$libresoc.v:116358$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:114866.5-114866.29" + attribute \src "libresoc.v:116359.5-116359.29" switch \initial - attribute \src "libresoc.v:114866.9-114866.17" + attribute \src "libresoc.v:116359.9-116359.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -178964,18 +181204,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:114908.3-114950.6" - process $proc$libresoc.v:114908$4373 + attribute \src "libresoc.v:116401.3-116443.6" + process $proc$libresoc.v:116401$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114909.5-114909.29" + attribute \src "libresoc.v:116402.5-116402.29" switch \initial - attribute \src "libresoc.v:114909.9-114909.17" + attribute \src "libresoc.v:116402.9-116402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179031,18 +181271,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:114951.3-114993.6" - process $proc$libresoc.v:114951$4374 + attribute \src "libresoc.v:116444.3-116486.6" + process $proc$libresoc.v:116444$4412 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:114952.5-114952.29" + attribute \src "libresoc.v:116445.5-116445.29" switch \initial - attribute \src "libresoc.v:114952.9-114952.17" + attribute \src "libresoc.v:116445.9-116445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179098,18 +181338,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:114994.3-115036.6" - process $proc$libresoc.v:114994$4375 + attribute \src "libresoc.v:116487.3-116529.6" + process $proc$libresoc.v:116487$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:114995.5-114995.29" + attribute \src "libresoc.v:116488.5-116488.29" switch \initial - attribute \src "libresoc.v:114995.9-114995.17" + attribute \src "libresoc.v:116488.9-116488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179165,18 +181405,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:115037.3-115079.6" - process $proc$libresoc.v:115037$4376 + attribute \src "libresoc.v:116530.3-116572.6" + process $proc$libresoc.v:116530$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115038.5-115038.29" + attribute \src "libresoc.v:116531.5-116531.29" switch \initial - attribute \src "libresoc.v:115038.9-115038.17" + attribute \src "libresoc.v:116531.9-116531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179232,18 +181472,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:115080.3-115122.6" - process $proc$libresoc.v:115080$4377 + attribute \src "libresoc.v:116573.3-116615.6" + process $proc$libresoc.v:116573$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:115081.5-115081.29" + attribute \src "libresoc.v:116574.5-116574.29" switch \initial - attribute \src "libresoc.v:115081.9-115081.17" + attribute \src "libresoc.v:116574.9-116574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179299,18 +181539,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:115123.3-115165.6" - process $proc$libresoc.v:115123$4378 + attribute \src "libresoc.v:116616.3-116658.6" + process $proc$libresoc.v:116616$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:115124.5-115124.29" + attribute \src "libresoc.v:116617.5-116617.29" switch \initial - attribute \src "libresoc.v:115124.9-115124.17" + attribute \src "libresoc.v:116617.9-116617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179366,152 +181606,152 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:115166.3-115208.6" - process $proc$libresoc.v:115166$4379 + attribute \src "libresoc.v:116659.3-116701.6" + process $proc$libresoc.v:116659$4417 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:115167.5-115167.29" + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:116660.5-116660.29" switch \initial - attribute \src "libresoc.v:115167.9-115167.17" + attribute \src "libresoc.v:116660.9-116660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'00000 end sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:115209.3-115251.6" - process $proc$libresoc.v:115209$4380 + attribute \src "libresoc.v:116702.3-116744.6" + process $proc$libresoc.v:116702$4418 assign { } { } assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115210.5-115210.29" + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:116703.5-116703.29" switch \initial - attribute \src "libresoc.v:115210.9-115210.17" + attribute \src "libresoc.v:116703.9-116703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:115252.3-115294.6" - process $proc$libresoc.v:115252$4381 + attribute \src "libresoc.v:116745.3-116787.6" + process $proc$libresoc.v:116745$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:115253.5-115253.29" + attribute \src "libresoc.v:116746.5-116746.29" switch \initial - attribute \src "libresoc.v:115253.9-115253.17" + attribute \src "libresoc.v:116746.9-116746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179567,18 +181807,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:115295.3-115337.6" - process $proc$libresoc.v:115295$4382 + attribute \src "libresoc.v:116788.3-116830.6" + process $proc$libresoc.v:116788$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:115296.5-115296.29" + attribute \src "libresoc.v:116789.5-116789.29" switch \initial - attribute \src "libresoc.v:115296.9-115296.17" + attribute \src "libresoc.v:116789.9-116789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179634,18 +181874,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:115338.3-115380.6" - process $proc$libresoc.v:115338$4383 + attribute \src "libresoc.v:116831.3-116873.6" + process $proc$libresoc.v:116831$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:115339.5-115339.29" + attribute \src "libresoc.v:116832.5-116832.29" switch \initial - attribute \src "libresoc.v:115339.9-115339.17" + attribute \src "libresoc.v:116832.9-116832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179701,18 +181941,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:115381.3-115423.6" - process $proc$libresoc.v:115381$4384 + attribute \src "libresoc.v:116874.3-116916.6" + process $proc$libresoc.v:116874$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:115382.5-115382.29" + attribute \src "libresoc.v:116875.5-116875.29" switch \initial - attribute \src "libresoc.v:115382.9-115382.17" + attribute \src "libresoc.v:116875.9-116875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179768,18 +182008,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:115424.3-115466.6" - process $proc$libresoc.v:115424$4385 + attribute \src "libresoc.v:116917.3-116959.6" + process $proc$libresoc.v:116917$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:115425.5-115425.29" + attribute \src "libresoc.v:116918.5-116918.29" switch \initial - attribute \src "libresoc.v:115425.9-115425.17" + attribute \src "libresoc.v:116918.9-116918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179835,18 +182075,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:115467.3-115509.6" - process $proc$libresoc.v:115467$4386 + attribute \src "libresoc.v:116960.3-117002.6" + process $proc$libresoc.v:116960$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:115468.5-115468.29" + attribute \src "libresoc.v:116961.5-116961.29" switch \initial - attribute \src "libresoc.v:115468.9-115468.17" + attribute \src "libresoc.v:116961.9-116961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179902,18 +182142,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:115510.3-115552.6" - process $proc$libresoc.v:115510$4387 + attribute \src "libresoc.v:117003.3-117045.6" + process $proc$libresoc.v:117003$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:115511.5-115511.29" + attribute \src "libresoc.v:117004.5-117004.29" switch \initial - attribute \src "libresoc.v:115511.9-115511.17" + attribute \src "libresoc.v:117004.9-117004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -179969,18 +182209,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:115553.3-115595.6" - process $proc$libresoc.v:115553$4388 + attribute \src "libresoc.v:117046.3-117088.6" + process $proc$libresoc.v:117046$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:115554.5-115554.29" + attribute \src "libresoc.v:117047.5-117047.29" switch \initial - attribute \src "libresoc.v:115554.9-115554.17" + attribute \src "libresoc.v:117047.9-117047.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -180036,18 +182276,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:115596.3-115638.6" - process $proc$libresoc.v:115596$4389 + attribute \src "libresoc.v:117089.3-117131.6" + process $proc$libresoc.v:117089$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:115597.5-115597.29" + attribute \src "libresoc.v:117090.5-117090.29" switch \initial - attribute \src "libresoc.v:115597.9-115597.17" + attribute \src "libresoc.v:117090.9-117090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -180105,157 +182345,161 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:115644.1-117744.10" +attribute \src "libresoc.v:117137.1-119302.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:117413.3-117467.6" + attribute \src "libresoc.v:118971.3-119025.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117468.3-117522.6" + attribute \src "libresoc.v:119026.3-119080.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:118311.3-118365.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116973.3-117027.6" + attribute \src "libresoc.v:118531.3-118585.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:117541.3-117595.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:117596.3-117650.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:118256.3-118310.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:118476.3-118530.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:117193.3-117247.6" + attribute \src "libresoc.v:118696.3-118750.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:117486.3-117540.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117523.3-117577.6" + attribute \src "libresoc.v:119081.3-119135.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117578.3-117632.6" + attribute \src "libresoc.v:119136.3-119190.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117633.3-117687.6" + attribute \src "libresoc.v:119191.3-119245.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:118091.3-118145.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:118366.3-118420.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:118421.3-118475.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:117138.3-117192.6" + attribute \src "libresoc.v:118751.3-118805.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:118036.3-118090.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:117303.3-117357.6" + attribute \src "libresoc.v:118861.3-118915.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117688.3-117742.6" + attribute \src "libresoc.v:119246.3-119300.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:118201.3-118255.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:117083.3-117137.6" + attribute \src "libresoc.v:118641.3-118695.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117358.3-117412.6" + attribute \src "libresoc.v:118916.3-118970.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117248.3-117302.6" + attribute \src "libresoc.v:118806.3-118860.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117028.3-117082.6" + attribute \src "libresoc.v:118586.3-118640.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:117926.3-117980.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:117981.3-118035.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:117651.3-117705.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:117706.3-117760.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:117761.3-117815.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:118146.3-118200.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:115645.7-115645.20" + attribute \src "libresoc.v:117138.7-117138.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117413.3-117467.6" + attribute \src "libresoc.v:118971.3-119025.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117468.3-117522.6" + attribute \src "libresoc.v:119026.3-119080.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:118311.3-118365.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116973.3-117027.6" + attribute \src "libresoc.v:118531.3-118585.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:117541.3-117595.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:117596.3-117650.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:118256.3-118310.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:118476.3-118530.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:117193.3-117247.6" + attribute \src "libresoc.v:118696.3-118750.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:117486.3-117540.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117523.3-117577.6" + attribute \src "libresoc.v:119081.3-119135.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117578.3-117632.6" + attribute \src "libresoc.v:119136.3-119190.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117633.3-117687.6" + attribute \src "libresoc.v:119191.3-119245.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:118091.3-118145.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:118366.3-118420.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:118421.3-118475.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:117138.3-117192.6" + attribute \src "libresoc.v:118751.3-118805.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:118036.3-118090.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:117303.3-117357.6" + attribute \src "libresoc.v:118861.3-118915.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117688.3-117742.6" + attribute \src "libresoc.v:119246.3-119300.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:118201.3-118255.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:117083.3-117137.6" + attribute \src "libresoc.v:118641.3-118695.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117358.3-117412.6" + attribute \src "libresoc.v:118916.3-118970.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117248.3-117302.6" + attribute \src "libresoc.v:118806.3-118860.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117028.3-117082.6" + attribute \src "libresoc.v:118586.3-118640.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:117926.3-117980.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:117981.3-118035.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:117651.3-117705.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:117706.3-117760.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:117761.3-117815.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:117871.3-117925.6" + wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117816.3-117870.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:118146.3-118200.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub9_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub9_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec31_dec_sub9_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -180265,7 +182509,7 @@ module \dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -180274,16 +182518,16 @@ module \dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec31_dec_sub9_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -180315,7 +182559,7 @@ module \dec31_dec_sub9 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -180332,7 +182576,7 @@ module \dec31_dec_sub9 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -180340,7 +182584,7 @@ module \dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -180357,13 +182601,13 @@ module \dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -180440,46 +182684,46 @@ module \dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec31_dec_sub9_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec31_dec_sub9_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec31_dec_sub9_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec31_dec_sub9_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180487,8 +182731,8 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec31_dec_sub9_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec31_dec_sub9_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180496,8 +182740,8 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec31_dec_sub9_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec31_dec_sub9_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -180505,7 +182749,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub9_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180514,7 +182758,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub9_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180523,7 +182767,7 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub9_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -180532,41 +182776,50 @@ module \dec31_dec_sub9 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub9_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec31_dec_sub9_upd - attribute \src "libresoc.v:115645.7-115645.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec31_dec_sub9_upd + attribute \src "libresoc.v:117138.7-117138.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:115645.7-115645.20" - process $proc$libresoc.v:115645$4423 + attribute \src "libresoc.v:117138.7-117138.20" + process $proc$libresoc.v:117138$4462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115983.3-116037.6" - process $proc$libresoc.v:115983$4391 + attribute \src "libresoc.v:117486.3-117540.6" + process $proc$libresoc.v:117486$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:115984.5-115984.29" + attribute \src "libresoc.v:117487.5-117487.29" switch \initial - attribute \src "libresoc.v:115984.9-115984.17" + attribute \src "libresoc.v:117487.9-117487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180638,18 +182891,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:116038.3-116092.6" - process $proc$libresoc.v:116038$4392 + attribute \src "libresoc.v:117541.3-117595.6" + process $proc$libresoc.v:117541$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:116039.5-116039.29" + attribute \src "libresoc.v:117542.5-117542.29" switch \initial - attribute \src "libresoc.v:116039.9-116039.17" + attribute \src "libresoc.v:117542.9-117542.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180721,18 +182974,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:116093.3-116147.6" - process $proc$libresoc.v:116093$4393 + attribute \src "libresoc.v:117596.3-117650.6" + process $proc$libresoc.v:117596$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:116094.5-116094.29" + attribute \src "libresoc.v:117597.5-117597.29" switch \initial - attribute \src "libresoc.v:116094.9-116094.17" + attribute \src "libresoc.v:117597.9-117597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180804,18 +183057,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:116148.3-116202.6" - process $proc$libresoc.v:116148$4394 + attribute \src "libresoc.v:117651.3-117705.6" + process $proc$libresoc.v:117651$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:116149.5-116149.29" + attribute \src "libresoc.v:117652.5-117652.29" switch \initial - attribute \src "libresoc.v:116149.9-116149.17" + attribute \src "libresoc.v:117652.9-117652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180887,18 +183140,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:116203.3-116257.6" - process $proc$libresoc.v:116203$4395 + attribute \src "libresoc.v:117706.3-117760.6" + process $proc$libresoc.v:117706$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:116204.5-116204.29" + attribute \src "libresoc.v:117707.5-117707.29" switch \initial - attribute \src "libresoc.v:116204.9-116204.17" + attribute \src "libresoc.v:117707.9-117707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -180970,18 +183223,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:116258.3-116312.6" - process $proc$libresoc.v:116258$4396 + attribute \src "libresoc.v:117761.3-117815.6" + process $proc$libresoc.v:117761$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:116259.5-116259.29" + attribute \src "libresoc.v:117762.5-117762.29" switch \initial - attribute \src "libresoc.v:116259.9-116259.17" + attribute \src "libresoc.v:117762.9-117762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181053,18 +183306,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:116313.3-116367.6" - process $proc$libresoc.v:116313$4397 + attribute \src "libresoc.v:117816.3-117870.6" + process $proc$libresoc.v:117816$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:116314.5-116314.29" + attribute \src "libresoc.v:117817.5-117817.29" switch \initial - attribute \src "libresoc.v:116314.9-116314.17" + attribute \src "libresoc.v:117817.9-117817.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181136,18 +183389,101 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:116368.3-116422.6" - process $proc$libresoc.v:116368$4398 + attribute \src "libresoc.v:117871.3-117925.6" + process $proc$libresoc.v:117871$4436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] + attribute \src "libresoc.v:117872.5-117872.29" + switch \initial + attribute \src "libresoc.v:117872.9-117872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] + end + attribute \src "libresoc.v:117926.3-117980.6" + process $proc$libresoc.v:117926$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:116369.5-116369.29" + attribute \src "libresoc.v:117927.5-117927.29" switch \initial - attribute \src "libresoc.v:116369.9-116369.17" + attribute \src "libresoc.v:117927.9-117927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181219,18 +183555,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:116423.3-116477.6" - process $proc$libresoc.v:116423$4399 + attribute \src "libresoc.v:117981.3-118035.6" + process $proc$libresoc.v:117981$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:116424.5-116424.29" + attribute \src "libresoc.v:117982.5-117982.29" switch \initial - attribute \src "libresoc.v:116424.9-116424.17" + attribute \src "libresoc.v:117982.9-117982.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181302,18 +183638,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:116478.3-116532.6" - process $proc$libresoc.v:116478$4400 + attribute \src "libresoc.v:118036.3-118090.6" + process $proc$libresoc.v:118036$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:116479.5-116479.29" + attribute \src "libresoc.v:118037.5-118037.29" switch \initial - attribute \src "libresoc.v:116479.9-116479.17" + attribute \src "libresoc.v:118037.9-118037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181385,184 +183721,184 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:116533.3-116587.6" - process $proc$libresoc.v:116533$4401 + attribute \src "libresoc.v:118091.3-118145.6" + process $proc$libresoc.v:118091$4440 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:116534.5-116534.29" + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:118092.5-118092.29" switch \initial - attribute \src "libresoc.v:116534.9-116534.17" + attribute \src "libresoc.v:118092.9-118092.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:116588.3-116642.6" - process $proc$libresoc.v:116588$4402 + attribute \src "libresoc.v:118146.3-118200.6" + process $proc$libresoc.v:118146$4441 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116589.5-116589.29" + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:118147.5-118147.29" switch \initial - attribute \src "libresoc.v:116589.9-116589.17" + attribute \src "libresoc.v:118147.9-118147.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + assign $1\dec31_dec_sub9_upd[1:0] 2'00 end sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:116643.3-116697.6" - process $proc$libresoc.v:116643$4403 + attribute \src "libresoc.v:118201.3-118255.6" + process $proc$libresoc.v:118201$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:116644.5-116644.29" + attribute \src "libresoc.v:118202.5-118202.29" switch \initial - attribute \src "libresoc.v:116644.9-116644.17" + attribute \src "libresoc.v:118202.9-118202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181634,18 +183970,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:116698.3-116752.6" - process $proc$libresoc.v:116698$4404 + attribute \src "libresoc.v:118256.3-118310.6" + process $proc$libresoc.v:118256$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116699.5-116699.29" + attribute \src "libresoc.v:118257.5-118257.29" switch \initial - attribute \src "libresoc.v:116699.9-116699.17" + attribute \src "libresoc.v:118257.9-118257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181717,18 +184053,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:116753.3-116807.6" - process $proc$libresoc.v:116753$4405 + attribute \src "libresoc.v:118311.3-118365.6" + process $proc$libresoc.v:118311$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116754.5-116754.29" + attribute \src "libresoc.v:118312.5-118312.29" switch \initial - attribute \src "libresoc.v:116754.9-116754.17" + attribute \src "libresoc.v:118312.9-118312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181800,18 +184136,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:116808.3-116862.6" - process $proc$libresoc.v:116808$4406 + attribute \src "libresoc.v:118366.3-118420.6" + process $proc$libresoc.v:118366$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116809.5-116809.29" + attribute \src "libresoc.v:118367.5-118367.29" switch \initial - attribute \src "libresoc.v:116809.9-116809.17" + attribute \src "libresoc.v:118367.9-118367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181883,18 +184219,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:116863.3-116917.6" - process $proc$libresoc.v:116863$4407 + attribute \src "libresoc.v:118421.3-118475.6" + process $proc$libresoc.v:118421$4446 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:116864.5-116864.29" + attribute \src "libresoc.v:118422.5-118422.29" switch \initial - attribute \src "libresoc.v:116864.9-116864.17" + attribute \src "libresoc.v:118422.9-118422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -181966,18 +184302,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:116918.3-116972.6" - process $proc$libresoc.v:116918$4408 + attribute \src "libresoc.v:118476.3-118530.6" + process $proc$libresoc.v:118476$4447 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:116919.5-116919.29" + attribute \src "libresoc.v:118477.5-118477.29" switch \initial - attribute \src "libresoc.v:116919.9-116919.17" + attribute \src "libresoc.v:118477.9-118477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182049,18 +184385,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:116973.3-117027.6" - process $proc$libresoc.v:116973$4409 + attribute \src "libresoc.v:118531.3-118585.6" + process $proc$libresoc.v:118531$4448 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116974.5-116974.29" + attribute \src "libresoc.v:118532.5-118532.29" switch \initial - attribute \src "libresoc.v:116974.9-116974.17" + attribute \src "libresoc.v:118532.9-118532.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182132,18 +184468,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:117028.3-117082.6" - process $proc$libresoc.v:117028$4410 + attribute \src "libresoc.v:118586.3-118640.6" + process $proc$libresoc.v:118586$4449 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117029.5-117029.29" + attribute \src "libresoc.v:118587.5-118587.29" switch \initial - attribute \src "libresoc.v:117029.9-117029.17" + attribute \src "libresoc.v:118587.9-118587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182215,18 +184551,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:117083.3-117137.6" - process $proc$libresoc.v:117083$4411 + attribute \src "libresoc.v:118641.3-118695.6" + process $proc$libresoc.v:118641$4450 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:117084.5-117084.29" + attribute \src "libresoc.v:118642.5-118642.29" switch \initial - attribute \src "libresoc.v:117084.9-117084.17" + attribute \src "libresoc.v:118642.9-118642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182298,184 +184634,184 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:117138.3-117192.6" - process $proc$libresoc.v:117138$4412 + attribute \src "libresoc.v:118696.3-118750.6" + process $proc$libresoc.v:118696$4451 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:117139.5-117139.29" + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:118697.5-118697.29" switch \initial - attribute \src "libresoc.v:117139.9-117139.17" + attribute \src "libresoc.v:118697.9-118697.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + assign $1\dec31_dec_sub9_form[4:0] 5'00000 end sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:117193.3-117247.6" - process $proc$libresoc.v:117193$4413 + attribute \src "libresoc.v:118751.3-118805.6" + process $proc$libresoc.v:118751$4452 assign { } { } assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117194.5-117194.29" + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:118752.5-118752.29" switch \initial - attribute \src "libresoc.v:117194.9-117194.17" + attribute \src "libresoc.v:118752.9-118752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 end sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:117248.3-117302.6" - process $proc$libresoc.v:117248$4414 + attribute \src "libresoc.v:118806.3-118860.6" + process $proc$libresoc.v:118806$4453 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:117249.5-117249.29" + attribute \src "libresoc.v:118807.5-118807.29" switch \initial - attribute \src "libresoc.v:117249.9-117249.17" + attribute \src "libresoc.v:118807.9-118807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182547,18 +184883,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:117303.3-117357.6" - process $proc$libresoc.v:117303$4415 + attribute \src "libresoc.v:118861.3-118915.6" + process $proc$libresoc.v:118861$4454 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:117304.5-117304.29" + attribute \src "libresoc.v:118862.5-118862.29" switch \initial - attribute \src "libresoc.v:117304.9-117304.17" + attribute \src "libresoc.v:118862.9-118862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182630,18 +184966,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:117358.3-117412.6" - process $proc$libresoc.v:117358$4416 + attribute \src "libresoc.v:118916.3-118970.6" + process $proc$libresoc.v:118916$4455 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:117359.5-117359.29" + attribute \src "libresoc.v:118917.5-118917.29" switch \initial - attribute \src "libresoc.v:117359.9-117359.17" + attribute \src "libresoc.v:118917.9-118917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182713,18 +185049,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:117413.3-117467.6" - process $proc$libresoc.v:117413$4417 + attribute \src "libresoc.v:118971.3-119025.6" + process $proc$libresoc.v:118971$4456 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:117414.5-117414.29" + attribute \src "libresoc.v:118972.5-118972.29" switch \initial - attribute \src "libresoc.v:117414.9-117414.17" + attribute \src "libresoc.v:118972.9-118972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182796,18 +185132,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:117468.3-117522.6" - process $proc$libresoc.v:117468$4418 + attribute \src "libresoc.v:119026.3-119080.6" + process $proc$libresoc.v:119026$4457 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:117469.5-117469.29" + attribute \src "libresoc.v:119027.5-119027.29" switch \initial - attribute \src "libresoc.v:117469.9-117469.17" + attribute \src "libresoc.v:119027.9-119027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182879,18 +185215,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:117523.3-117577.6" - process $proc$libresoc.v:117523$4419 + attribute \src "libresoc.v:119081.3-119135.6" + process $proc$libresoc.v:119081$4458 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:117524.5-117524.29" + attribute \src "libresoc.v:119082.5-119082.29" switch \initial - attribute \src "libresoc.v:117524.9-117524.17" + attribute \src "libresoc.v:119082.9-119082.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -182962,18 +185298,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:117578.3-117632.6" - process $proc$libresoc.v:117578$4420 + attribute \src "libresoc.v:119136.3-119190.6" + process $proc$libresoc.v:119136$4459 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:117579.5-117579.29" + attribute \src "libresoc.v:119137.5-119137.29" switch \initial - attribute \src "libresoc.v:117579.9-117579.17" + attribute \src "libresoc.v:119137.9-119137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183045,18 +185381,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:117633.3-117687.6" - process $proc$libresoc.v:117633$4421 + attribute \src "libresoc.v:119191.3-119245.6" + process $proc$libresoc.v:119191$4460 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:117634.5-117634.29" + attribute \src "libresoc.v:119192.5-119192.29" switch \initial - attribute \src "libresoc.v:117634.9-117634.17" + attribute \src "libresoc.v:119192.9-119192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183128,18 +185464,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:117688.3-117742.6" - process $proc$libresoc.v:117688$4422 + attribute \src "libresoc.v:119246.3-119300.6" + process $proc$libresoc.v:119246$4461 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:117689.5-117689.29" + attribute \src "libresoc.v:119247.5-119247.29" switch \initial - attribute \src "libresoc.v:117689.9-117689.17" + attribute \src "libresoc.v:119247.9-119247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -183213,157 +185549,161 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:117748.1-118600.10" +attribute \src "libresoc.v:119306.1-120184.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:118503.3-118518.6" + attribute \src "libresoc.v:120087.3-120102.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118519.3-118534.6" + attribute \src "libresoc.v:120103.3-120118.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118326.6" + attribute \src "libresoc.v:119895.3-119910.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:118375.3-118390.6" + attribute \src "libresoc.v:119959.3-119974.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:118103.3-118118.6" + attribute \src "libresoc.v:119671.3-119686.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:118119.3-118134.6" + attribute \src "libresoc.v:119687.3-119702.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:118295.3-118310.6" + attribute \src "libresoc.v:119879.3-119894.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:118359.3-118374.6" + attribute \src "libresoc.v:119943.3-119958.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:118439.3-118454.6" + attribute \src "libresoc.v:120007.3-120022.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:118087.3-118102.6" + attribute \src "libresoc.v:119655.3-119670.6" wire width 14 $0\dec58_function_unit[13:0] - attribute \src "libresoc.v:118535.3-118550.6" + attribute \src "libresoc.v:120119.3-120134.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118551.3-118566.6" + attribute \src "libresoc.v:120135.3-120150.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118567.3-118582.6" + attribute \src "libresoc.v:120151.3-120166.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118263.3-118278.6" + attribute \src "libresoc.v:119831.3-119846.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:118327.3-118342.6" + attribute \src "libresoc.v:119911.3-119926.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:118343.3-118358.6" + attribute \src "libresoc.v:119927.3-119942.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:118423.3-118438.6" + attribute \src "libresoc.v:120023.3-120038.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:118231.3-118246.6" + attribute \src "libresoc.v:119815.3-119830.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118471.3-118486.6" + attribute \src "libresoc.v:120055.3-120070.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:118583.3-118598.6" + attribute \src "libresoc.v:120167.3-120182.6" wire width 3 $0\dec58_out_sel[2:0] - attribute \src "libresoc.v:118279.3-118294.6" + attribute \src "libresoc.v:119863.3-119878.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118407.3-118422.6" + attribute \src "libresoc.v:119991.3-120006.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:118487.3-118502.6" + attribute \src "libresoc.v:120071.3-120086.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118455.3-118470.6" + attribute \src "libresoc.v:120039.3-120054.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:118391.3-118406.6" + attribute \src "libresoc.v:119975.3-119990.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118199.3-118214.6" + attribute \src "libresoc.v:119783.3-119798.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118215.3-118230.6" + attribute \src "libresoc.v:119799.3-119814.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118135.3-118150.6" + attribute \src "libresoc.v:119703.3-119718.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118151.3-118166.6" + attribute \src "libresoc.v:119719.3-119734.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118167.3-118182.6" + attribute \src "libresoc.v:119735.3-119750.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118183.3-118198.6" + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $0\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:118247.3-118262.6" + attribute \src "libresoc.v:119847.3-119862.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:117749.7-117749.20" + attribute \src "libresoc.v:119307.7-119307.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118503.3-118518.6" + attribute \src "libresoc.v:120087.3-120102.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118519.3-118534.6" + attribute \src "libresoc.v:120103.3-120118.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118326.6" + attribute \src "libresoc.v:119895.3-119910.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:118375.3-118390.6" + attribute \src "libresoc.v:119959.3-119974.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:118103.3-118118.6" + attribute \src "libresoc.v:119671.3-119686.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:118119.3-118134.6" + attribute \src "libresoc.v:119687.3-119702.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:118295.3-118310.6" + attribute \src "libresoc.v:119879.3-119894.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:118359.3-118374.6" + attribute \src "libresoc.v:119943.3-119958.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:118439.3-118454.6" + attribute \src "libresoc.v:120007.3-120022.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:118087.3-118102.6" + attribute \src "libresoc.v:119655.3-119670.6" wire width 14 $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:118535.3-118550.6" + attribute \src "libresoc.v:120119.3-120134.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118551.3-118566.6" + attribute \src "libresoc.v:120135.3-120150.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118567.3-118582.6" + attribute \src "libresoc.v:120151.3-120166.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118263.3-118278.6" + attribute \src "libresoc.v:119831.3-119846.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:118327.3-118342.6" + attribute \src "libresoc.v:119911.3-119926.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:118343.3-118358.6" + attribute \src "libresoc.v:119927.3-119942.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:118423.3-118438.6" + attribute \src "libresoc.v:120023.3-120038.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:118231.3-118246.6" + attribute \src "libresoc.v:119815.3-119830.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118471.3-118486.6" + attribute \src "libresoc.v:120055.3-120070.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:118583.3-118598.6" + attribute \src "libresoc.v:120167.3-120182.6" wire width 3 $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:118279.3-118294.6" + attribute \src "libresoc.v:119863.3-119878.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118407.3-118422.6" + attribute \src "libresoc.v:119991.3-120006.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:118487.3-118502.6" + attribute \src "libresoc.v:120071.3-120086.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118455.3-118470.6" + attribute \src "libresoc.v:120039.3-120054.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:118391.3-118406.6" + attribute \src "libresoc.v:119975.3-119990.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118199.3-118214.6" + attribute \src "libresoc.v:119783.3-119798.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118215.3-118230.6" + attribute \src "libresoc.v:119799.3-119814.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118135.3-118150.6" + attribute \src "libresoc.v:119703.3-119718.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118151.3-118166.6" + attribute \src "libresoc.v:119719.3-119734.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118167.3-118182.6" + attribute \src "libresoc.v:119735.3-119750.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118183.3-118198.6" + attribute \src "libresoc.v:119767.3-119782.6" + wire width 3 $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119751.3-119766.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:118247.3-118262.6" + attribute \src "libresoc.v:119847.3-119862.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec58_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec58_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec58_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -183373,7 +185713,7 @@ module \dec58 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -183382,16 +185722,16 @@ module \dec58 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec58_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -183423,7 +185763,7 @@ module \dec58 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -183440,7 +185780,7 @@ module \dec58 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -183448,7 +185788,7 @@ module \dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -183465,13 +185805,13 @@ module \dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -183548,46 +185888,46 @@ module \dec58 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec58_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec58_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec58_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec58_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183595,8 +185935,8 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec58_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec58_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183604,8 +185944,8 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec58_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec58_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -183613,7 +185953,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec58_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183622,7 +185962,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec58_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183631,7 +185971,7 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec58_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -183640,41 +185980,50 @@ module \dec58 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec58_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec58_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec58_upd - attribute \src "libresoc.v:117749.7-117749.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec58_upd + attribute \src "libresoc.v:119307.7-119307.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:117749.7-117749.20" - process $proc$libresoc.v:117749$4456 + attribute \src "libresoc.v:119307.7-119307.20" + process $proc$libresoc.v:119307$4496 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118087.3-118102.6" - process $proc$libresoc.v:118087$4424 + attribute \src "libresoc.v:119655.3-119670.6" + process $proc$libresoc.v:119655$4463 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:118088.5-118088.29" + attribute \src "libresoc.v:119656.5-119656.29" switch \initial - attribute \src "libresoc.v:118088.9-118088.17" + attribute \src "libresoc.v:119656.9-119656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183694,18 +186043,18 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:118103.3-118118.6" - process $proc$libresoc.v:118103$4425 + attribute \src "libresoc.v:119671.3-119686.6" + process $proc$libresoc.v:119671$4464 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:118104.5-118104.29" + attribute \src "libresoc.v:119672.5-119672.29" switch \initial - attribute \src "libresoc.v:118104.9-118104.17" + attribute \src "libresoc.v:119672.9-119672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183725,18 +186074,18 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:118119.3-118134.6" - process $proc$libresoc.v:118119$4426 + attribute \src "libresoc.v:119687.3-119702.6" + process $proc$libresoc.v:119687$4465 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:118120.5-118120.29" + attribute \src "libresoc.v:119688.5-119688.29" switch \initial - attribute \src "libresoc.v:118120.9-118120.17" + attribute \src "libresoc.v:119688.9-119688.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183756,18 +186105,18 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:118135.3-118150.6" - process $proc$libresoc.v:118135$4427 + attribute \src "libresoc.v:119703.3-119718.6" + process $proc$libresoc.v:119703$4466 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:118136.5-118136.29" + attribute \src "libresoc.v:119704.5-119704.29" switch \initial - attribute \src "libresoc.v:118136.9-118136.17" + attribute \src "libresoc.v:119704.9-119704.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183787,18 +186136,18 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:118151.3-118166.6" - process $proc$libresoc.v:118151$4428 + attribute \src "libresoc.v:119719.3-119734.6" + process $proc$libresoc.v:119719$4467 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:118152.5-118152.29" + attribute \src "libresoc.v:119720.5-119720.29" switch \initial - attribute \src "libresoc.v:118152.9-118152.17" + attribute \src "libresoc.v:119720.9-119720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183818,18 +186167,18 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:118167.3-118182.6" - process $proc$libresoc.v:118167$4429 + attribute \src "libresoc.v:119735.3-119750.6" + process $proc$libresoc.v:119735$4468 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:118168.5-118168.29" + attribute \src "libresoc.v:119736.5-119736.29" switch \initial - attribute \src "libresoc.v:118168.9-118168.17" + attribute \src "libresoc.v:119736.9-119736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183849,18 +186198,18 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:118183.3-118198.6" - process $proc$libresoc.v:118183$4430 + attribute \src "libresoc.v:119751.3-119766.6" + process $proc$libresoc.v:119751$4469 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:118184.5-118184.29" + attribute \src "libresoc.v:119752.5-119752.29" switch \initial - attribute \src "libresoc.v:118184.9-118184.17" + attribute \src "libresoc.v:119752.9-119752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183880,18 +186229,49 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:118199.3-118214.6" - process $proc$libresoc.v:118199$4431 + attribute \src "libresoc.v:119767.3-119782.6" + process $proc$libresoc.v:119767$4470 + assign { } { } + assign { } { } + assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] + attribute \src "libresoc.v:119768.5-119768.29" + switch \initial + attribute \src "libresoc.v:119768.9-119768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_out2[2:0] 3'000 + case + assign $1\dec58_sv_out2[2:0] 3'000 + end + sync always + update \dec58_sv_out2 $0\dec58_sv_out2[2:0] + end + attribute \src "libresoc.v:119783.3-119798.6" + process $proc$libresoc.v:119783$4471 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:118200.5-118200.29" + attribute \src "libresoc.v:119784.5-119784.29" switch \initial - attribute \src "libresoc.v:118200.9-118200.17" + attribute \src "libresoc.v:119784.9-119784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183911,18 +186291,18 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:118215.3-118230.6" - process $proc$libresoc.v:118215$4432 + attribute \src "libresoc.v:119799.3-119814.6" + process $proc$libresoc.v:119799$4472 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:118216.5-118216.29" + attribute \src "libresoc.v:119800.5-119800.29" switch \initial - attribute \src "libresoc.v:118216.9-118216.17" + attribute \src "libresoc.v:119800.9-119800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183942,18 +186322,18 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:118231.3-118246.6" - process $proc$libresoc.v:118231$4433 + attribute \src "libresoc.v:119815.3-119830.6" + process $proc$libresoc.v:119815$4473 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:118232.5-118232.29" + attribute \src "libresoc.v:119816.5-119816.29" switch \initial - attribute \src "libresoc.v:118232.9-118232.17" + attribute \src "libresoc.v:119816.9-119816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -183973,80 +186353,80 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:118247.3-118262.6" - process $proc$libresoc.v:118247$4434 + attribute \src "libresoc.v:119831.3-119846.6" + process $proc$libresoc.v:119831$4474 assign { } { } assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:118248.5-118248.29" + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:119832.5-119832.29" switch \initial - attribute \src "libresoc.v:118248.9-118248.17" + attribute \src "libresoc.v:119832.9-119832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_upd[1:0] 2'01 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0100101 case - assign $1\dec58_upd[1:0] 2'00 + assign $1\dec58_internal_op[6:0] 7'0000000 end sync always - update \dec58_upd $0\dec58_upd[1:0] + update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:118263.3-118278.6" - process $proc$libresoc.v:118263$4435 + attribute \src "libresoc.v:119847.3-119862.6" + process $proc$libresoc.v:119847$4475 assign { } { } assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:118264.5-118264.29" + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:119848.5-119848.29" switch \initial - attribute \src "libresoc.v:118264.9-118264.17" + attribute \src "libresoc.v:119848.9-119848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 + assign $1\dec58_upd[1:0] 2'00 case - assign $1\dec58_internal_op[6:0] 7'0000000 + assign $1\dec58_upd[1:0] 2'00 end sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] + update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:118279.3-118294.6" - process $proc$libresoc.v:118279$4436 + attribute \src "libresoc.v:119863.3-119878.6" + process $proc$libresoc.v:119863$4476 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:118280.5-118280.29" + attribute \src "libresoc.v:119864.5-119864.29" switch \initial - attribute \src "libresoc.v:118280.9-118280.17" + attribute \src "libresoc.v:119864.9-119864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184066,18 +186446,18 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:118295.3-118310.6" - process $proc$libresoc.v:118295$4437 + attribute \src "libresoc.v:119879.3-119894.6" + process $proc$libresoc.v:119879$4477 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:118296.5-118296.29" + attribute \src "libresoc.v:119880.5-119880.29" switch \initial - attribute \src "libresoc.v:118296.9-118296.17" + attribute \src "libresoc.v:119880.9-119880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184097,18 +186477,18 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:118311.3-118326.6" - process $proc$libresoc.v:118311$4438 + attribute \src "libresoc.v:119895.3-119910.6" + process $proc$libresoc.v:119895$4478 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:118312.5-118312.29" + attribute \src "libresoc.v:119896.5-119896.29" switch \initial - attribute \src "libresoc.v:118312.9-118312.17" + attribute \src "libresoc.v:119896.9-119896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184128,18 +186508,18 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:118327.3-118342.6" - process $proc$libresoc.v:118327$4439 + attribute \src "libresoc.v:119911.3-119926.6" + process $proc$libresoc.v:119911$4479 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:118328.5-118328.29" + attribute \src "libresoc.v:119912.5-119912.29" switch \initial - attribute \src "libresoc.v:118328.9-118328.17" + attribute \src "libresoc.v:119912.9-119912.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184159,18 +186539,18 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:118343.3-118358.6" - process $proc$libresoc.v:118343$4440 + attribute \src "libresoc.v:119927.3-119942.6" + process $proc$libresoc.v:119927$4480 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:118344.5-118344.29" + attribute \src "libresoc.v:119928.5-119928.29" switch \initial - attribute \src "libresoc.v:118344.9-118344.17" + attribute \src "libresoc.v:119928.9-119928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184190,18 +186570,18 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:118359.3-118374.6" - process $proc$libresoc.v:118359$4441 + attribute \src "libresoc.v:119943.3-119958.6" + process $proc$libresoc.v:119943$4481 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:118360.5-118360.29" + attribute \src "libresoc.v:119944.5-119944.29" switch \initial - attribute \src "libresoc.v:118360.9-118360.17" + attribute \src "libresoc.v:119944.9-119944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184221,18 +186601,18 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:118375.3-118390.6" - process $proc$libresoc.v:118375$4442 + attribute \src "libresoc.v:119959.3-119974.6" + process $proc$libresoc.v:119959$4482 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:118376.5-118376.29" + attribute \src "libresoc.v:119960.5-119960.29" switch \initial - attribute \src "libresoc.v:118376.9-118376.17" + attribute \src "libresoc.v:119960.9-119960.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184252,18 +186632,18 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:118391.3-118406.6" - process $proc$libresoc.v:118391$4443 + attribute \src "libresoc.v:119975.3-119990.6" + process $proc$libresoc.v:119975$4483 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:118392.5-118392.29" + attribute \src "libresoc.v:119976.5-119976.29" switch \initial - attribute \src "libresoc.v:118392.9-118392.17" + attribute \src "libresoc.v:119976.9-119976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184283,18 +186663,18 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:118407.3-118422.6" - process $proc$libresoc.v:118407$4444 + attribute \src "libresoc.v:119991.3-120006.6" + process $proc$libresoc.v:119991$4484 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:118408.5-118408.29" + attribute \src "libresoc.v:119992.5-119992.29" switch \initial - attribute \src "libresoc.v:118408.9-118408.17" + attribute \src "libresoc.v:119992.9-119992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184314,80 +186694,80 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:118423.3-118438.6" - process $proc$libresoc.v:118423$4445 + attribute \src "libresoc.v:120007.3-120022.6" + process $proc$libresoc.v:120007$4485 assign { } { } assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:118424.5-118424.29" + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:120008.5-120008.29" switch \initial - attribute \src "libresoc.v:118424.9-118424.17" + attribute \src "libresoc.v:120008.9-120008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00101 case - assign $1\dec58_is_32b[0:0] 1'0 + assign $1\dec58_form[4:0] 5'00000 end sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] + update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:118439.3-118454.6" - process $proc$libresoc.v:118439$4446 + attribute \src "libresoc.v:120023.3-120038.6" + process $proc$libresoc.v:120023$4486 assign { } { } assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:118440.5-118440.29" + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:120024.5-120024.29" switch \initial - attribute \src "libresoc.v:118440.9-118440.17" + attribute \src "libresoc.v:120024.9-120024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\dec58_form[4:0] 5'00101 + assign $1\dec58_is_32b[0:0] 1'0 case - assign $1\dec58_form[4:0] 5'00000 + assign $1\dec58_is_32b[0:0] 1'0 end sync always - update \dec58_form $0\dec58_form[4:0] + update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:118455.3-118470.6" - process $proc$libresoc.v:118455$4447 + attribute \src "libresoc.v:120039.3-120054.6" + process $proc$libresoc.v:120039$4487 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:118456.5-118456.29" + attribute \src "libresoc.v:120040.5-120040.29" switch \initial - attribute \src "libresoc.v:118456.9-118456.17" + attribute \src "libresoc.v:120040.9-120040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184407,18 +186787,18 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:118471.3-118486.6" - process $proc$libresoc.v:118471$4448 + attribute \src "libresoc.v:120055.3-120070.6" + process $proc$libresoc.v:120055$4488 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:118472.5-118472.29" + attribute \src "libresoc.v:120056.5-120056.29" switch \initial - attribute \src "libresoc.v:118472.9-118472.17" + attribute \src "libresoc.v:120056.9-120056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184438,18 +186818,18 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:118487.3-118502.6" - process $proc$libresoc.v:118487$4449 + attribute \src "libresoc.v:120071.3-120086.6" + process $proc$libresoc.v:120071$4489 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:118488.5-118488.29" + attribute \src "libresoc.v:120072.5-120072.29" switch \initial - attribute \src "libresoc.v:118488.9-118488.17" + attribute \src "libresoc.v:120072.9-120072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184469,18 +186849,18 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:118503.3-118518.6" - process $proc$libresoc.v:118503$4450 + attribute \src "libresoc.v:120087.3-120102.6" + process $proc$libresoc.v:120087$4490 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:118504.5-118504.29" + attribute \src "libresoc.v:120088.5-120088.29" switch \initial - attribute \src "libresoc.v:118504.9-118504.17" + attribute \src "libresoc.v:120088.9-120088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184500,18 +186880,18 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:118519.3-118534.6" - process $proc$libresoc.v:118519$4451 + attribute \src "libresoc.v:120103.3-120118.6" + process $proc$libresoc.v:120103$4491 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:118520.5-118520.29" + attribute \src "libresoc.v:120104.5-120104.29" switch \initial - attribute \src "libresoc.v:118520.9-118520.17" + attribute \src "libresoc.v:120104.9-120104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184531,18 +186911,18 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:118535.3-118550.6" - process $proc$libresoc.v:118535$4452 + attribute \src "libresoc.v:120119.3-120134.6" + process $proc$libresoc.v:120119$4492 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:118536.5-118536.29" + attribute \src "libresoc.v:120120.5-120120.29" switch \initial - attribute \src "libresoc.v:118536.9-118536.17" + attribute \src "libresoc.v:120120.9-120120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184562,18 +186942,18 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:118551.3-118566.6" - process $proc$libresoc.v:118551$4453 + attribute \src "libresoc.v:120135.3-120150.6" + process $proc$libresoc.v:120135$4493 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:118552.5-118552.29" + attribute \src "libresoc.v:120136.5-120136.29" switch \initial - attribute \src "libresoc.v:118552.9-118552.17" + attribute \src "libresoc.v:120136.9-120136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184593,18 +186973,18 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:118567.3-118582.6" - process $proc$libresoc.v:118567$4454 + attribute \src "libresoc.v:120151.3-120166.6" + process $proc$libresoc.v:120151$4494 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:118568.5-118568.29" + attribute \src "libresoc.v:120152.5-120152.29" switch \initial - attribute \src "libresoc.v:118568.9-118568.17" + attribute \src "libresoc.v:120152.9-120152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184624,18 +187004,18 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:118583.3-118598.6" - process $proc$libresoc.v:118583$4455 + attribute \src "libresoc.v:120167.3-120182.6" + process $proc$libresoc.v:120167$4495 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:118584.5-118584.29" + attribute \src "libresoc.v:120168.5-120168.29" switch \initial - attribute \src "libresoc.v:118584.9-118584.17" + attribute \src "libresoc.v:120168.9-120168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -184657,157 +187037,161 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:118604.1-119360.10" +attribute \src "libresoc.v:120188.1-120967.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:119281.3-119293.6" + attribute \src "libresoc.v:120888.3-120900.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119294.3-119306.6" + attribute \src "libresoc.v:120901.3-120913.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119125.3-119137.6" + attribute \src "libresoc.v:120732.3-120744.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:119177.3-119189.6" + attribute \src "libresoc.v:120784.3-120796.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:118956.3-118968.6" + attribute \src "libresoc.v:120550.3-120562.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:118969.3-118981.6" + attribute \src "libresoc.v:120563.3-120575.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:119112.3-119124.6" + attribute \src "libresoc.v:120719.3-120731.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:119164.3-119176.6" + attribute \src "libresoc.v:120771.3-120783.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:119229.3-119241.6" + attribute \src "libresoc.v:120823.3-120835.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:118943.3-118955.6" + attribute \src "libresoc.v:120537.3-120549.6" wire width 14 $0\dec62_function_unit[13:0] - attribute \src "libresoc.v:119307.3-119319.6" + attribute \src "libresoc.v:120914.3-120926.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119320.3-119332.6" + attribute \src "libresoc.v:120927.3-120939.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119333.3-119345.6" + attribute \src "libresoc.v:120940.3-120952.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119086.3-119098.6" + attribute \src "libresoc.v:120680.3-120692.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:119138.3-119150.6" + attribute \src "libresoc.v:120745.3-120757.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:119151.3-119163.6" + attribute \src "libresoc.v:120758.3-120770.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:119216.3-119228.6" + attribute \src "libresoc.v:120836.3-120848.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:119060.3-119072.6" + attribute \src "libresoc.v:120667.3-120679.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119255.3-119267.6" + attribute \src "libresoc.v:120862.3-120874.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:119346.3-119358.6" + attribute \src "libresoc.v:120953.3-120965.6" wire width 3 $0\dec62_out_sel[2:0] - attribute \src "libresoc.v:119099.3-119111.6" + attribute \src "libresoc.v:120706.3-120718.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119203.3-119215.6" + attribute \src "libresoc.v:120810.3-120822.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:119268.3-119280.6" + attribute \src "libresoc.v:120875.3-120887.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119242.3-119254.6" + attribute \src "libresoc.v:120849.3-120861.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:119190.3-119202.6" + attribute \src "libresoc.v:120797.3-120809.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119034.3-119046.6" + attribute \src "libresoc.v:120641.3-120653.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119047.3-119059.6" + attribute \src "libresoc.v:120654.3-120666.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118982.3-118994.6" + attribute \src "libresoc.v:120576.3-120588.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118995.3-119007.6" + attribute \src "libresoc.v:120589.3-120601.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:119008.3-119020.6" + attribute \src "libresoc.v:120602.3-120614.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119021.3-119033.6" + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $0\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:119073.3-119085.6" + attribute \src "libresoc.v:120693.3-120705.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:118605.7-118605.20" + attribute \src "libresoc.v:120189.7-120189.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119281.3-119293.6" + attribute \src "libresoc.v:120888.3-120900.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119294.3-119306.6" + attribute \src "libresoc.v:120901.3-120913.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119125.3-119137.6" + attribute \src "libresoc.v:120732.3-120744.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:119177.3-119189.6" + attribute \src "libresoc.v:120784.3-120796.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:118956.3-118968.6" + attribute \src "libresoc.v:120550.3-120562.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118969.3-118981.6" + attribute \src "libresoc.v:120563.3-120575.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:119112.3-119124.6" + attribute \src "libresoc.v:120719.3-120731.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:119164.3-119176.6" + attribute \src "libresoc.v:120771.3-120783.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:119229.3-119241.6" + attribute \src "libresoc.v:120823.3-120835.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:118943.3-118955.6" + attribute \src "libresoc.v:120537.3-120549.6" wire width 14 $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:119307.3-119319.6" + attribute \src "libresoc.v:120914.3-120926.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119320.3-119332.6" + attribute \src "libresoc.v:120927.3-120939.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119333.3-119345.6" + attribute \src "libresoc.v:120940.3-120952.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119086.3-119098.6" + attribute \src "libresoc.v:120680.3-120692.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:119138.3-119150.6" + attribute \src "libresoc.v:120745.3-120757.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:119151.3-119163.6" + attribute \src "libresoc.v:120758.3-120770.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:119216.3-119228.6" + attribute \src "libresoc.v:120836.3-120848.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:119060.3-119072.6" + attribute \src "libresoc.v:120667.3-120679.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119255.3-119267.6" + attribute \src "libresoc.v:120862.3-120874.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:119346.3-119358.6" + attribute \src "libresoc.v:120953.3-120965.6" wire width 3 $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:119099.3-119111.6" + attribute \src "libresoc.v:120706.3-120718.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119203.3-119215.6" + attribute \src "libresoc.v:120810.3-120822.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:119268.3-119280.6" + attribute \src "libresoc.v:120875.3-120887.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119242.3-119254.6" + attribute \src "libresoc.v:120849.3-120861.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:119190.3-119202.6" + attribute \src "libresoc.v:120797.3-120809.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119034.3-119046.6" + attribute \src "libresoc.v:120641.3-120653.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119047.3-119059.6" + attribute \src "libresoc.v:120654.3-120666.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118982.3-118994.6" + attribute \src "libresoc.v:120576.3-120588.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118995.3-119007.6" + attribute \src "libresoc.v:120589.3-120601.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:119008.3-119020.6" + attribute \src "libresoc.v:120602.3-120614.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119021.3-119033.6" + attribute \src "libresoc.v:120628.3-120640.6" + wire width 3 $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120615.3-120627.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:119073.3-119085.6" + attribute \src "libresoc.v:120693.3-120705.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec62_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec62_SV_Ptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 26 \dec62_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 27 \dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -184817,7 +187201,7 @@ module \dec62 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -184826,16 +187210,16 @@ module \dec62 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 22 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 25 \dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 23 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 26 \dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -184867,7 +187251,7 @@ module \dec62 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -184884,7 +187268,7 @@ module \dec62 attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -184892,7 +187276,7 @@ module \dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -184909,13 +187293,13 @@ module \dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184992,46 +187376,46 @@ module \dec62 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 23 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 24 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 29 \dec62_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 24 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 25 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 30 \dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 19 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 31 \dec62_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 4 output 20 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 32 \dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 21 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 28 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 32 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 30 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 27 \dec62_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 22 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 29 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 33 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 31 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" + wire output 28 \dec62_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185039,8 +187423,8 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 17 \dec62_sv_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 18 \dec62_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185048,8 +187432,8 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 18 \dec62_sv_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 19 \dec62_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -185057,7 +187441,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec62_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185066,7 +187450,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec62_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185075,7 +187459,7 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec62_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -185084,41 +187468,50 @@ module \dec62 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec62_sv_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 3 output 17 \dec62_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 20 \dec62_upd - attribute \src "libresoc.v:118605.7-118605.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" + wire width 2 output 21 \dec62_upd + attribute \src "libresoc.v:120189.7-120189.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" - wire width 32 input 33 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" + wire width 32 input 34 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:118605.7-118605.20" - process $proc$libresoc.v:118605$4489 + attribute \src "libresoc.v:120189.7-120189.20" + process $proc$libresoc.v:120189$4530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118943.3-118955.6" - process $proc$libresoc.v:118943$4457 + attribute \src "libresoc.v:120537.3-120549.6" + process $proc$libresoc.v:120537$4497 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:118944.5-118944.29" + attribute \src "libresoc.v:120538.5-120538.29" switch \initial - attribute \src "libresoc.v:118944.9-118944.17" + attribute \src "libresoc.v:120538.9-120538.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185134,18 +187527,18 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:118956.3-118968.6" - process $proc$libresoc.v:118956$4458 + attribute \src "libresoc.v:120550.3-120562.6" + process $proc$libresoc.v:120550$4498 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118957.5-118957.29" + attribute \src "libresoc.v:120551.5-120551.29" switch \initial - attribute \src "libresoc.v:118957.9-118957.17" + attribute \src "libresoc.v:120551.9-120551.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185161,18 +187554,18 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:118969.3-118981.6" - process $proc$libresoc.v:118969$4459 + attribute \src "libresoc.v:120563.3-120575.6" + process $proc$libresoc.v:120563$4499 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:118970.5-118970.29" + attribute \src "libresoc.v:120564.5-120564.29" switch \initial - attribute \src "libresoc.v:118970.9-118970.17" + attribute \src "libresoc.v:120564.9-120564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185188,18 +187581,18 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:118982.3-118994.6" - process $proc$libresoc.v:118982$4460 + attribute \src "libresoc.v:120576.3-120588.6" + process $proc$libresoc.v:120576$4500 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118983.5-118983.29" + attribute \src "libresoc.v:120577.5-120577.29" switch \initial - attribute \src "libresoc.v:118983.9-118983.17" + attribute \src "libresoc.v:120577.9-120577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185215,18 +187608,18 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:118995.3-119007.6" - process $proc$libresoc.v:118995$4461 + attribute \src "libresoc.v:120589.3-120601.6" + process $proc$libresoc.v:120589$4501 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:118996.5-118996.29" + attribute \src "libresoc.v:120590.5-120590.29" switch \initial - attribute \src "libresoc.v:118996.9-118996.17" + attribute \src "libresoc.v:120590.9-120590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185242,18 +187635,18 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:119008.3-119020.6" - process $proc$libresoc.v:119008$4462 + attribute \src "libresoc.v:120602.3-120614.6" + process $proc$libresoc.v:120602$4502 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:119009.5-119009.29" + attribute \src "libresoc.v:120603.5-120603.29" switch \initial - attribute \src "libresoc.v:119009.9-119009.17" + attribute \src "libresoc.v:120603.9-120603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185269,18 +187662,18 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:119021.3-119033.6" - process $proc$libresoc.v:119021$4463 + attribute \src "libresoc.v:120615.3-120627.6" + process $proc$libresoc.v:120615$4503 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:119022.5-119022.29" + attribute \src "libresoc.v:120616.5-120616.29" switch \initial - attribute \src "libresoc.v:119022.9-119022.17" + attribute \src "libresoc.v:120616.9-120616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185296,18 +187689,45 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:119034.3-119046.6" - process $proc$libresoc.v:119034$4464 + attribute \src "libresoc.v:120628.3-120640.6" + process $proc$libresoc.v:120628$4504 + assign { } { } + assign { } { } + assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] + attribute \src "libresoc.v:120629.5-120629.29" + switch \initial + attribute \src "libresoc.v:120629.9-120629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_out2[2:0] 3'001 + case + assign $1\dec62_sv_out2[2:0] 3'000 + end + sync always + update \dec62_sv_out2 $0\dec62_sv_out2[2:0] + end + attribute \src "libresoc.v:120641.3-120653.6" + process $proc$libresoc.v:120641$4505 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:119035.5-119035.29" + attribute \src "libresoc.v:120642.5-120642.29" switch \initial - attribute \src "libresoc.v:119035.9-119035.17" + attribute \src "libresoc.v:120642.9-120642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185323,18 +187743,18 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:119047.3-119059.6" - process $proc$libresoc.v:119047$4465 + attribute \src "libresoc.v:120654.3-120666.6" + process $proc$libresoc.v:120654$4506 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:119048.5-119048.29" + attribute \src "libresoc.v:120655.5-120655.29" switch \initial - attribute \src "libresoc.v:119048.9-119048.17" + attribute \src "libresoc.v:120655.9-120655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185350,18 +187770,18 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:119060.3-119072.6" - process $proc$libresoc.v:119060$4466 + attribute \src "libresoc.v:120667.3-120679.6" + process $proc$libresoc.v:120667$4507 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:119061.5-119061.29" + attribute \src "libresoc.v:120668.5-120668.29" switch \initial - attribute \src "libresoc.v:119061.9-119061.17" + attribute \src "libresoc.v:120668.9-120668.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185377,72 +187797,72 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:119073.3-119085.6" - process $proc$libresoc.v:119073$4467 + attribute \src "libresoc.v:120680.3-120692.6" + process $proc$libresoc.v:120680$4508 assign { } { } assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:119074.5-119074.29" + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:120681.5-120681.29" switch \initial - attribute \src "libresoc.v:119074.9-119074.17" + attribute \src "libresoc.v:120681.9-120681.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_upd[1:0] 2'00 + assign $1\dec62_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_upd[1:0] 2'01 + assign $1\dec62_internal_op[6:0] 7'0100110 case - assign $1\dec62_upd[1:0] 2'00 + assign $1\dec62_internal_op[6:0] 7'0000000 end sync always - update \dec62_upd $0\dec62_upd[1:0] + update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:119086.3-119098.6" - process $proc$libresoc.v:119086$4468 + attribute \src "libresoc.v:120693.3-120705.6" + process $proc$libresoc.v:120693$4509 assign { } { } assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:119087.5-119087.29" + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:120694.5-120694.29" switch \initial - attribute \src "libresoc.v:119087.9-119087.17" + attribute \src "libresoc.v:120694.9-120694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec62_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 + assign $1\dec62_upd[1:0] 2'01 case - assign $1\dec62_internal_op[6:0] 7'0000000 + assign $1\dec62_upd[1:0] 2'00 end sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] + update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:119099.3-119111.6" - process $proc$libresoc.v:119099$4469 + attribute \src "libresoc.v:120706.3-120718.6" + process $proc$libresoc.v:120706$4510 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:119100.5-119100.29" + attribute \src "libresoc.v:120707.5-120707.29" switch \initial - attribute \src "libresoc.v:119100.9-119100.17" + attribute \src "libresoc.v:120707.9-120707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185458,18 +187878,18 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:119112.3-119124.6" - process $proc$libresoc.v:119112$4470 + attribute \src "libresoc.v:120719.3-120731.6" + process $proc$libresoc.v:120719$4511 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:119113.5-119113.29" + attribute \src "libresoc.v:120720.5-120720.29" switch \initial - attribute \src "libresoc.v:119113.9-119113.17" + attribute \src "libresoc.v:120720.9-120720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185485,18 +187905,18 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:119125.3-119137.6" - process $proc$libresoc.v:119125$4471 + attribute \src "libresoc.v:120732.3-120744.6" + process $proc$libresoc.v:120732$4512 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:119126.5-119126.29" + attribute \src "libresoc.v:120733.5-120733.29" switch \initial - attribute \src "libresoc.v:119126.9-119126.17" + attribute \src "libresoc.v:120733.9-120733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185512,18 +187932,18 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:119138.3-119150.6" - process $proc$libresoc.v:119138$4472 + attribute \src "libresoc.v:120745.3-120757.6" + process $proc$libresoc.v:120745$4513 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:119139.5-119139.29" + attribute \src "libresoc.v:120746.5-120746.29" switch \initial - attribute \src "libresoc.v:119139.9-119139.17" + attribute \src "libresoc.v:120746.9-120746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185539,18 +187959,18 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:119151.3-119163.6" - process $proc$libresoc.v:119151$4473 + attribute \src "libresoc.v:120758.3-120770.6" + process $proc$libresoc.v:120758$4514 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:119152.5-119152.29" + attribute \src "libresoc.v:120759.5-120759.29" switch \initial - attribute \src "libresoc.v:119152.9-119152.17" + attribute \src "libresoc.v:120759.9-120759.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185566,18 +187986,18 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:119164.3-119176.6" - process $proc$libresoc.v:119164$4474 + attribute \src "libresoc.v:120771.3-120783.6" + process $proc$libresoc.v:120771$4515 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:119165.5-119165.29" + attribute \src "libresoc.v:120772.5-120772.29" switch \initial - attribute \src "libresoc.v:119165.9-119165.17" + attribute \src "libresoc.v:120772.9-120772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185593,18 +188013,18 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:119177.3-119189.6" - process $proc$libresoc.v:119177$4475 + attribute \src "libresoc.v:120784.3-120796.6" + process $proc$libresoc.v:120784$4516 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:119178.5-119178.29" + attribute \src "libresoc.v:120785.5-120785.29" switch \initial - attribute \src "libresoc.v:119178.9-119178.17" + attribute \src "libresoc.v:120785.9-120785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185620,18 +188040,18 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:119190.3-119202.6" - process $proc$libresoc.v:119190$4476 + attribute \src "libresoc.v:120797.3-120809.6" + process $proc$libresoc.v:120797$4517 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:119191.5-119191.29" + attribute \src "libresoc.v:120798.5-120798.29" switch \initial - attribute \src "libresoc.v:119191.9-119191.17" + attribute \src "libresoc.v:120798.9-120798.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185647,18 +188067,18 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:119203.3-119215.6" - process $proc$libresoc.v:119203$4477 + attribute \src "libresoc.v:120810.3-120822.6" + process $proc$libresoc.v:120810$4518 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:119204.5-119204.29" + attribute \src "libresoc.v:120811.5-120811.29" switch \initial - attribute \src "libresoc.v:119204.9-119204.17" + attribute \src "libresoc.v:120811.9-120811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185674,72 +188094,72 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:119216.3-119228.6" - process $proc$libresoc.v:119216$4478 + attribute \src "libresoc.v:120823.3-120835.6" + process $proc$libresoc.v:120823$4519 assign { } { } assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:119217.5-119217.29" + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:120824.5-120824.29" switch \initial - attribute \src "libresoc.v:119217.9-119217.17" + attribute \src "libresoc.v:120824.9-120824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00101 case - assign $1\dec62_is_32b[0:0] 1'0 + assign $1\dec62_form[4:0] 5'00000 end sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] + update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:119229.3-119241.6" - process $proc$libresoc.v:119229$4479 + attribute \src "libresoc.v:120836.3-120848.6" + process $proc$libresoc.v:120836$4520 assign { } { } assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:119230.5-119230.29" + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:120837.5-120837.29" switch \initial - attribute \src "libresoc.v:119230.9-119230.17" + attribute \src "libresoc.v:120837.9-120837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec62_form[4:0] 5'00101 + assign $1\dec62_is_32b[0:0] 1'0 case - assign $1\dec62_form[4:0] 5'00000 + assign $1\dec62_is_32b[0:0] 1'0 end sync always - update \dec62_form $0\dec62_form[4:0] + update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:119242.3-119254.6" - process $proc$libresoc.v:119242$4480 + attribute \src "libresoc.v:120849.3-120861.6" + process $proc$libresoc.v:120849$4521 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:119243.5-119243.29" + attribute \src "libresoc.v:120850.5-120850.29" switch \initial - attribute \src "libresoc.v:119243.9-119243.17" + attribute \src "libresoc.v:120850.9-120850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185755,18 +188175,18 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:119255.3-119267.6" - process $proc$libresoc.v:119255$4481 + attribute \src "libresoc.v:120862.3-120874.6" + process $proc$libresoc.v:120862$4522 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:119256.5-119256.29" + attribute \src "libresoc.v:120863.5-120863.29" switch \initial - attribute \src "libresoc.v:119256.9-119256.17" + attribute \src "libresoc.v:120863.9-120863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185782,18 +188202,18 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:119268.3-119280.6" - process $proc$libresoc.v:119268$4482 + attribute \src "libresoc.v:120875.3-120887.6" + process $proc$libresoc.v:120875$4523 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:119269.5-119269.29" + attribute \src "libresoc.v:120876.5-120876.29" switch \initial - attribute \src "libresoc.v:119269.9-119269.17" + attribute \src "libresoc.v:120876.9-120876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185809,18 +188229,18 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:119281.3-119293.6" - process $proc$libresoc.v:119281$4483 + attribute \src "libresoc.v:120888.3-120900.6" + process $proc$libresoc.v:120888$4524 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:119282.5-119282.29" + attribute \src "libresoc.v:120889.5-120889.29" switch \initial - attribute \src "libresoc.v:119282.9-119282.17" + attribute \src "libresoc.v:120889.9-120889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185836,18 +188256,18 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:119294.3-119306.6" - process $proc$libresoc.v:119294$4484 + attribute \src "libresoc.v:120901.3-120913.6" + process $proc$libresoc.v:120901$4525 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:119295.5-119295.29" + attribute \src "libresoc.v:120902.5-120902.29" switch \initial - attribute \src "libresoc.v:119295.9-119295.17" + attribute \src "libresoc.v:120902.9-120902.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185863,18 +188283,18 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:119307.3-119319.6" - process $proc$libresoc.v:119307$4485 + attribute \src "libresoc.v:120914.3-120926.6" + process $proc$libresoc.v:120914$4526 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:119308.5-119308.29" + attribute \src "libresoc.v:120915.5-120915.29" switch \initial - attribute \src "libresoc.v:119308.9-119308.17" + attribute \src "libresoc.v:120915.9-120915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185890,18 +188310,18 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:119320.3-119332.6" - process $proc$libresoc.v:119320$4486 + attribute \src "libresoc.v:120927.3-120939.6" + process $proc$libresoc.v:120927$4527 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:119321.5-119321.29" + attribute \src "libresoc.v:120928.5-120928.29" switch \initial - attribute \src "libresoc.v:119321.9-119321.17" + attribute \src "libresoc.v:120928.9-120928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185917,18 +188337,18 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:119333.3-119345.6" - process $proc$libresoc.v:119333$4487 + attribute \src "libresoc.v:120940.3-120952.6" + process $proc$libresoc.v:120940$4528 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:119334.5-119334.29" + attribute \src "libresoc.v:120941.5-120941.29" switch \initial - attribute \src "libresoc.v:119334.9-119334.17" + attribute \src "libresoc.v:120941.9-120941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185944,18 +188364,18 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:119346.3-119358.6" - process $proc$libresoc.v:119346$4488 + attribute \src "libresoc.v:120953.3-120965.6" + process $proc$libresoc.v:120953$4529 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:119347.5-119347.29" + attribute \src "libresoc.v:120954.5-120954.29" switch \initial - attribute \src "libresoc.v:119347.9-119347.17" + attribute \src "libresoc.v:120954.9-120954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -185973,120 +188393,120 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:119364.1-119947.10" +attribute \src "libresoc.v:120971.1-121554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:119910.3-119924.6" + attribute \src "libresoc.v:121517.3-121531.6" wire width 14 $0\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119897.3-119909.6" + attribute \src "libresoc.v:121504.3-121516.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:119882.3-119896.6" + attribute \src "libresoc.v:121489.3-121503.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119365.7-119365.20" + attribute \src "libresoc.v:120972.7-120972.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119910.3-119924.6" + attribute \src "libresoc.v:121517.3-121531.6" wire width 14 $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119897.3-119909.6" + attribute \src "libresoc.v:121504.3-121516.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:119882.3-119896.6" + attribute \src "libresoc.v:121489.3-121503.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119798.18-119798.113" - wire $and$libresoc.v:119798$4490_Y - attribute \src "libresoc.v:119800.18-119800.110" - wire $and$libresoc.v:119800$4492_Y - attribute \src "libresoc.v:119813.18-119813.114" - wire $and$libresoc.v:119813$4505_Y - attribute \src "libresoc.v:119814.18-119814.116" - wire $and$libresoc.v:119814$4506_Y - attribute \src "libresoc.v:119816.18-119816.114" - wire $and$libresoc.v:119816$4508_Y - attribute \src "libresoc.v:119818.18-119818.110" - wire $and$libresoc.v:119818$4510_Y - attribute \src "libresoc.v:119819.17-119819.112" - wire $and$libresoc.v:119819$4511_Y - attribute \src "libresoc.v:119820.17-119820.114" - wire $and$libresoc.v:119820$4512_Y - attribute \src "libresoc.v:119801.18-119801.126" - wire $eq$libresoc.v:119801$4493_Y - attribute \src "libresoc.v:119802.18-119802.126" - wire $eq$libresoc.v:119802$4494_Y - attribute \src "libresoc.v:119804.18-119804.110" - wire $eq$libresoc.v:119804$4496_Y - attribute \src "libresoc.v:119805.18-119805.110" - wire $eq$libresoc.v:119805$4497_Y - attribute \src "libresoc.v:119807.18-119807.112" - wire $eq$libresoc.v:119807$4499_Y - attribute \src "libresoc.v:119808.17-119808.130" - wire $eq$libresoc.v:119808$4500_Y - attribute \src "libresoc.v:119810.18-119810.110" - wire $eq$libresoc.v:119810$4502_Y - attribute \src "libresoc.v:119812.18-119812.131" - wire $eq$libresoc.v:119812$4504_Y - attribute \src "libresoc.v:119815.18-119815.131" - wire $eq$libresoc.v:119815$4507_Y - attribute \src "libresoc.v:119821.17-119821.130" - wire $eq$libresoc.v:119821$4513_Y - attribute \src "libresoc.v:119799.18-119799.110" - wire $not$libresoc.v:119799$4491_Y - attribute \src "libresoc.v:119817.18-119817.110" - wire $not$libresoc.v:119817$4509_Y - attribute \src "libresoc.v:119803.18-119803.110" - wire $or$libresoc.v:119803$4495_Y - attribute \src "libresoc.v:119806.18-119806.110" - wire $or$libresoc.v:119806$4498_Y - attribute \src "libresoc.v:119809.18-119809.110" - wire $or$libresoc.v:119809$4501_Y - attribute \src "libresoc.v:119811.18-119811.110" - wire $or$libresoc.v:119811$4503_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:121405.18-121405.113" + wire $and$libresoc.v:121405$4531_Y + attribute \src "libresoc.v:121407.18-121407.110" + wire $and$libresoc.v:121407$4533_Y + attribute \src "libresoc.v:121420.18-121420.114" + wire $and$libresoc.v:121420$4546_Y + attribute \src "libresoc.v:121421.18-121421.116" + wire $and$libresoc.v:121421$4547_Y + attribute \src "libresoc.v:121423.18-121423.114" + wire $and$libresoc.v:121423$4549_Y + attribute \src "libresoc.v:121425.18-121425.110" + wire $and$libresoc.v:121425$4551_Y + attribute \src "libresoc.v:121426.17-121426.112" + wire $and$libresoc.v:121426$4552_Y + attribute \src "libresoc.v:121427.17-121427.114" + wire $and$libresoc.v:121427$4553_Y + attribute \src "libresoc.v:121408.18-121408.126" + wire $eq$libresoc.v:121408$4534_Y + attribute \src "libresoc.v:121409.18-121409.126" + wire $eq$libresoc.v:121409$4535_Y + attribute \src "libresoc.v:121411.18-121411.110" + wire $eq$libresoc.v:121411$4537_Y + attribute \src "libresoc.v:121412.18-121412.110" + wire $eq$libresoc.v:121412$4538_Y + attribute \src "libresoc.v:121414.18-121414.112" + wire $eq$libresoc.v:121414$4540_Y + attribute \src "libresoc.v:121415.17-121415.130" + wire $eq$libresoc.v:121415$4541_Y + attribute \src "libresoc.v:121417.18-121417.110" + wire $eq$libresoc.v:121417$4543_Y + attribute \src "libresoc.v:121419.18-121419.131" + wire $eq$libresoc.v:121419$4545_Y + attribute \src "libresoc.v:121422.18-121422.131" + wire $eq$libresoc.v:121422$4548_Y + attribute \src "libresoc.v:121428.17-121428.130" + wire $eq$libresoc.v:121428$4554_Y + attribute \src "libresoc.v:121406.18-121406.110" + wire $not$libresoc.v:121406$4532_Y + attribute \src "libresoc.v:121424.18-121424.110" + wire $not$libresoc.v:121424$4550_Y + attribute \src "libresoc.v:121410.18-121410.110" + wire $or$libresoc.v:121410$4536_Y + attribute \src "libresoc.v:121413.18-121413.110" + wire $or$libresoc.v:121413$4539_Y + attribute \src "libresoc.v:121416.18-121416.110" + wire $or$libresoc.v:121416$4542_Y + attribute \src "libresoc.v:121418.18-121418.110" + wire $or$libresoc.v:121418$4544_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \ALU__data_len @@ -186218,27 +188638,27 @@ module \dec_ALU wire output 14 \ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -186247,15 +188667,15 @@ module \dec_ALU attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -186272,7 +188692,7 @@ module \dec_ALU attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -186280,7 +188700,7 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -186297,7 +188717,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -186374,13 +188794,13 @@ module \dec_ALU attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -186388,19 +188808,19 @@ module \dec_ALU attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -186408,9 +188828,9 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -186431,7 +188851,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -186441,9 +188861,9 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -186453,26 +188873,26 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119365.7-119365.15" + attribute \src "libresoc.v:120972.7-120972.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119798$4490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121405$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186480,10 +188900,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:119798$4490_Y + connect \Y $and$libresoc.v:121405$4531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119800$4492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121407$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186491,10 +188911,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:119800$4492_Y + connect \Y $and$libresoc.v:121407$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119813$4505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121420$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186502,10 +188922,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:119813$4505_Y + connect \Y $and$libresoc.v:121420$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119814$4506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121421$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186513,10 +188933,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119814$4506_Y + connect \Y $and$libresoc.v:121421$4547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119816$4508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121423$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186524,10 +188944,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:119816$4508_Y + connect \Y $and$libresoc.v:121423$4549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:119818$4510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121425$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186535,10 +188955,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:119818$4510_Y + connect \Y $and$libresoc.v:121425$4551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119819$4511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121426$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186546,10 +188966,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:119819$4511_Y + connect \Y $and$libresoc.v:121426$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:119820$4512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121427$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186557,10 +188977,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:119820$4512_Y + connect \Y $and$libresoc.v:121427$4553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:119801$4493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121408$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186568,10 +188988,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119801$4493_Y + connect \Y $eq$libresoc.v:121408$4534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:119802$4494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:121409$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186579,10 +188999,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119802$4494_Y + connect \Y $eq$libresoc.v:121409$4535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119804$4496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121411$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186590,10 +189010,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:119804$4496_Y + connect \Y $eq$libresoc.v:121411$4537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119805$4497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121412$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186601,10 +189021,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:119805$4497_Y + connect \Y $eq$libresoc.v:121412$4538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:119807$4499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121414$4540 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186612,10 +189032,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119807$4499_Y + connect \Y $eq$libresoc.v:121414$4540_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:119808$4500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121415$4541 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186623,10 +189043,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:119808$4500_Y + connect \Y $eq$libresoc.v:121415$4541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:119810$4502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:121417$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -186634,10 +189054,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:119810$4502_Y + connect \Y $eq$libresoc.v:121417$4543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:119812$4504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121419$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186645,10 +189065,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:119812$4504_Y + connect \Y $eq$libresoc.v:121419$4545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:119815$4507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121422$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186656,10 +189076,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:119815$4507_Y + connect \Y $eq$libresoc.v:121422$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:119821$4513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121428$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -186667,26 +189087,26 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:119821$4513_Y + connect \Y $eq$libresoc.v:121428$4554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:119799$4491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121406$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119799$4491_Y + connect \Y $not$libresoc.v:121406$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:119817$4509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121424$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:119817$4509_Y + connect \Y $not$libresoc.v:121424$4550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:119803$4495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:121410$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186694,10 +189114,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:119803$4495_Y + connect \Y $or$libresoc.v:121410$4536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:119806$4498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121413$4539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186705,10 +189125,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:119806$4498_Y + connect \Y $or$libresoc.v:121413$4539_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:119809$4501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121416$4542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186716,10 +189136,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:119809$4501_Y + connect \Y $or$libresoc.v:121416$4542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:119811$4503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121418$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -186727,10 +189147,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:119811$4503_Y + connect \Y $or$libresoc.v:121418$4544_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119822.7-119850.4" + attribute \src "libresoc.v:121429.7-121457.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -186761,7 +189181,7 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119851.10-119856.4" + attribute \src "libresoc.v:121458.10-121463.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out @@ -186769,7 +189189,7 @@ module \dec_ALU connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:119857.10-119868.4" + attribute \src "libresoc.v:121464.10-121475.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -186783,7 +189203,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119869.10-119875.4" + attribute \src "libresoc.v:121476.10-121482.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -186792,33 +189212,33 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119876.10-119881.4" + attribute \src "libresoc.v:121483.10-121488.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119365.7-119365.20" - process $proc$libresoc.v:119365$4517 + attribute \src "libresoc.v:120972.7-120972.20" + process $proc$libresoc.v:120972$4558 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119882.3-119896.6" - process $proc$libresoc.v:119882$4514 + attribute \src "libresoc.v:121489.3-121503.6" + process $proc$libresoc.v:121489$4555 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:119883.5-119883.29" + attribute \src "libresoc.v:121490.5-121490.29" switch \initial - attribute \src "libresoc.v:119883.9-119883.17" + attribute \src "libresoc.v:121490.9-121490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -186834,18 +189254,18 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:119897.3-119909.6" - process $proc$libresoc.v:119897$4515 + attribute \src "libresoc.v:121504.3-121516.6" + process $proc$libresoc.v:121504$4556 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:119898.5-119898.29" + attribute \src "libresoc.v:121505.5-121505.29" switch \initial - attribute \src "libresoc.v:119898.9-119898.17" + attribute \src "libresoc.v:121505.9-121505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -186861,17 +189281,17 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:119910.3-119924.6" - process $proc$libresoc.v:119910$4516 + attribute \src "libresoc.v:121517.3-121531.6" + process $proc$libresoc.v:121517$4557 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:119911.5-119911.29" + attribute \src "libresoc.v:121518.5-121518.29" switch \initial - attribute \src "libresoc.v:119911.9-119911.17" + attribute \src "libresoc.v:121518.9-121518.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -186889,30 +189309,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end - connect \$10 $and$libresoc.v:119798$4490_Y - connect \$12 $not$libresoc.v:119799$4491_Y - connect \$14 $and$libresoc.v:119800$4492_Y - connect \$16 $eq$libresoc.v:119801$4493_Y - connect \$18 $eq$libresoc.v:119802$4494_Y - connect \$20 $or$libresoc.v:119803$4495_Y - connect \$22 $eq$libresoc.v:119804$4496_Y - connect \$24 $eq$libresoc.v:119805$4497_Y - connect \$26 $or$libresoc.v:119806$4498_Y - connect \$28 $eq$libresoc.v:119807$4499_Y - connect \$2 $eq$libresoc.v:119808$4500_Y - connect \$30 $or$libresoc.v:119809$4501_Y - connect \$32 $eq$libresoc.v:119810$4502_Y - connect \$34 $or$libresoc.v:119811$4503_Y - connect \$36 $eq$libresoc.v:119812$4504_Y - connect \$38 $and$libresoc.v:119813$4505_Y - connect \$40 $and$libresoc.v:119814$4506_Y - connect \$42 $eq$libresoc.v:119815$4507_Y - connect \$44 $and$libresoc.v:119816$4508_Y - connect \$46 $not$libresoc.v:119817$4509_Y - connect \$48 $and$libresoc.v:119818$4510_Y - connect \$4 $and$libresoc.v:119819$4511_Y - connect \$6 $and$libresoc.v:119820$4512_Y - connect \$8 $eq$libresoc.v:119821$4513_Y + connect \$10 $and$libresoc.v:121405$4531_Y + connect \$12 $not$libresoc.v:121406$4532_Y + connect \$14 $and$libresoc.v:121407$4533_Y + connect \$16 $eq$libresoc.v:121408$4534_Y + connect \$18 $eq$libresoc.v:121409$4535_Y + connect \$20 $or$libresoc.v:121410$4536_Y + connect \$22 $eq$libresoc.v:121411$4537_Y + connect \$24 $eq$libresoc.v:121412$4538_Y + connect \$26 $or$libresoc.v:121413$4539_Y + connect \$28 $eq$libresoc.v:121414$4540_Y + connect \$2 $eq$libresoc.v:121415$4541_Y + connect \$30 $or$libresoc.v:121416$4542_Y + connect \$32 $eq$libresoc.v:121417$4543_Y + connect \$34 $or$libresoc.v:121418$4544_Y + connect \$36 $eq$libresoc.v:121419$4545_Y + connect \$38 $and$libresoc.v:121420$4546_Y + connect \$40 $and$libresoc.v:121421$4547_Y + connect \$42 $eq$libresoc.v:121422$4548_Y + connect \$44 $and$libresoc.v:121423$4549_Y + connect \$46 $not$libresoc.v:121424$4550_Y + connect \$48 $and$libresoc.v:121425$4551_Y + connect \$4 $and$libresoc.v:121426$4552_Y + connect \$6 $and$libresoc.v:121427$4553_Y + connect \$8 $eq$libresoc.v:121428$4554_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -186936,120 +189356,120 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:119951.1-120431.10" +attribute \src "libresoc.v:121558.1-122038.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:120381.3-120395.6" + attribute \src "libresoc.v:121988.3-122002.6" wire width 14 $0\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120406.3-120418.6" + attribute \src "libresoc.v:122013.3-122025.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120396.3-120405.6" + attribute \src "libresoc.v:122003.3-122012.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:119952.7-119952.20" + attribute \src "libresoc.v:121559.7-121559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120381.3-120395.6" + attribute \src "libresoc.v:121988.3-122002.6" wire width 14 $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120406.3-120418.6" + attribute \src "libresoc.v:122013.3-122025.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120396.3-120405.6" + attribute \src "libresoc.v:122003.3-122012.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:120313.18-120313.113" - wire $and$libresoc.v:120313$4518_Y - attribute \src "libresoc.v:120315.18-120315.110" - wire $and$libresoc.v:120315$4520_Y - attribute \src "libresoc.v:120328.18-120328.114" - wire $and$libresoc.v:120328$4533_Y - attribute \src "libresoc.v:120329.18-120329.116" - wire $and$libresoc.v:120329$4534_Y - attribute \src "libresoc.v:120331.18-120331.114" - wire $and$libresoc.v:120331$4536_Y - attribute \src "libresoc.v:120333.18-120333.110" - wire $and$libresoc.v:120333$4538_Y - attribute \src "libresoc.v:120334.17-120334.112" - wire $and$libresoc.v:120334$4539_Y - attribute \src "libresoc.v:120335.17-120335.114" - wire $and$libresoc.v:120335$4540_Y - attribute \src "libresoc.v:120316.18-120316.129" - wire $eq$libresoc.v:120316$4521_Y - attribute \src "libresoc.v:120317.18-120317.129" - wire $eq$libresoc.v:120317$4522_Y - attribute \src "libresoc.v:120319.18-120319.110" - wire $eq$libresoc.v:120319$4524_Y - attribute \src "libresoc.v:120320.18-120320.110" - wire $eq$libresoc.v:120320$4525_Y - attribute \src "libresoc.v:120322.18-120322.112" - wire $eq$libresoc.v:120322$4527_Y - attribute \src "libresoc.v:120323.17-120323.133" - wire $eq$libresoc.v:120323$4528_Y - attribute \src "libresoc.v:120325.18-120325.110" - wire $eq$libresoc.v:120325$4530_Y - attribute \src "libresoc.v:120327.18-120327.134" - wire $eq$libresoc.v:120327$4532_Y - attribute \src "libresoc.v:120330.18-120330.134" - wire $eq$libresoc.v:120330$4535_Y - attribute \src "libresoc.v:120336.17-120336.133" - wire $eq$libresoc.v:120336$4541_Y - attribute \src "libresoc.v:120314.18-120314.110" - wire $not$libresoc.v:120314$4519_Y - attribute \src "libresoc.v:120332.18-120332.110" - wire $not$libresoc.v:120332$4537_Y - attribute \src "libresoc.v:120318.18-120318.110" - wire $or$libresoc.v:120318$4523_Y - attribute \src "libresoc.v:120321.18-120321.110" - wire $or$libresoc.v:120321$4526_Y - attribute \src "libresoc.v:120324.18-120324.110" - wire $or$libresoc.v:120324$4529_Y - attribute \src "libresoc.v:120326.18-120326.110" - wire $or$libresoc.v:120326$4531_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:121920.18-121920.113" + wire $and$libresoc.v:121920$4559_Y + attribute \src "libresoc.v:121922.18-121922.110" + wire $and$libresoc.v:121922$4561_Y + attribute \src "libresoc.v:121935.18-121935.114" + wire $and$libresoc.v:121935$4574_Y + attribute \src "libresoc.v:121936.18-121936.116" + wire $and$libresoc.v:121936$4575_Y + attribute \src "libresoc.v:121938.18-121938.114" + wire $and$libresoc.v:121938$4577_Y + attribute \src "libresoc.v:121940.18-121940.110" + wire $and$libresoc.v:121940$4579_Y + attribute \src "libresoc.v:121941.17-121941.112" + wire $and$libresoc.v:121941$4580_Y + attribute \src "libresoc.v:121942.17-121942.114" + wire $and$libresoc.v:121942$4581_Y + attribute \src "libresoc.v:121923.18-121923.129" + wire $eq$libresoc.v:121923$4562_Y + attribute \src "libresoc.v:121924.18-121924.129" + wire $eq$libresoc.v:121924$4563_Y + attribute \src "libresoc.v:121926.18-121926.110" + wire $eq$libresoc.v:121926$4565_Y + attribute \src "libresoc.v:121927.18-121927.110" + wire $eq$libresoc.v:121927$4566_Y + attribute \src "libresoc.v:121929.18-121929.112" + wire $eq$libresoc.v:121929$4568_Y + attribute \src "libresoc.v:121930.17-121930.133" + wire $eq$libresoc.v:121930$4569_Y + attribute \src "libresoc.v:121932.18-121932.110" + wire $eq$libresoc.v:121932$4571_Y + attribute \src "libresoc.v:121934.18-121934.134" + wire $eq$libresoc.v:121934$4573_Y + attribute \src "libresoc.v:121937.18-121937.134" + wire $eq$libresoc.v:121937$4576_Y + attribute \src "libresoc.v:121943.17-121943.133" + wire $eq$libresoc.v:121943$4582_Y + attribute \src "libresoc.v:121921.18-121921.110" + wire $not$libresoc.v:121921$4560_Y + attribute \src "libresoc.v:121939.18-121939.110" + wire $not$libresoc.v:121939$4578_Y + attribute \src "libresoc.v:121925.18-121925.110" + wire $or$libresoc.v:121925$4564_Y + attribute \src "libresoc.v:121928.18-121928.110" + wire $or$libresoc.v:121928$4567_Y + attribute \src "libresoc.v:121931.18-121931.110" + wire $or$libresoc.v:121931$4570_Y + attribute \src "libresoc.v:121933.18-121933.110" + wire $or$libresoc.v:121933$4572_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia @@ -187157,29 +189577,29 @@ module \dec_BRANCH wire output 10 \BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 2 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -187188,7 +189608,7 @@ module \dec_BRANCH attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -187205,7 +189625,7 @@ module \dec_BRANCH attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -187222,7 +189642,7 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -187299,19 +189719,19 @@ module \dec_BRANCH attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -187332,38 +189752,38 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119952.7-119952.15" + attribute \src "libresoc.v:121559.7-121559.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120313$4518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121920$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187371,10 +189791,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120313$4518_Y + connect \Y $and$libresoc.v:121920$4559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120315$4520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121922$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187382,10 +189802,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120315$4520_Y + connect \Y $and$libresoc.v:121922$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120328$4533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121935$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187393,10 +189813,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120328$4533_Y + connect \Y $and$libresoc.v:121935$4574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120329$4534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121936$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187404,10 +189824,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120329$4534_Y + connect \Y $and$libresoc.v:121936$4575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120331$4536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121938$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187415,10 +189835,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120331$4536_Y + connect \Y $and$libresoc.v:121938$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120333$4538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:121940$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187426,10 +189846,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120333$4538_Y + connect \Y $and$libresoc.v:121940$4579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120334$4539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121941$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187437,10 +189857,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120334$4539_Y + connect \Y $and$libresoc.v:121941$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120335$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:121942$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187448,10 +189868,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120335$4540_Y + connect \Y $and$libresoc.v:121942$4581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120316$4521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:121923$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187459,10 +189879,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120316$4521_Y + connect \Y $eq$libresoc.v:121923$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:120317$4522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:121924$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187470,10 +189890,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120317$4522_Y + connect \Y $eq$libresoc.v:121924$4563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120319$4524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121926$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187481,10 +189901,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120319$4524_Y + connect \Y $eq$libresoc.v:121926$4565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120320$4525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121927$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187492,10 +189912,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120320$4525_Y + connect \Y $eq$libresoc.v:121927$4566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120322$4527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:121929$4568 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187503,10 +189923,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120322$4527_Y + connect \Y $eq$libresoc.v:121929$4568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120323$4528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121930$4569 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187514,10 +189934,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120323$4528_Y + connect \Y $eq$libresoc.v:121930$4569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:120325$4530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:121932$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -187525,10 +189945,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120325$4530_Y + connect \Y $eq$libresoc.v:121932$4571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120327$4532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:121934$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187536,10 +189956,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120327$4532_Y + connect \Y $eq$libresoc.v:121934$4573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120330$4535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121937$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187547,10 +189967,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120330$4535_Y + connect \Y $eq$libresoc.v:121937$4576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120336$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:121943$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -187558,26 +189978,26 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120336$4541_Y + connect \Y $eq$libresoc.v:121943$4582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120314$4519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121921$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120314$4519_Y + connect \Y $not$libresoc.v:121921$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120332$4537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:121939$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120332$4537_Y + connect \Y $not$libresoc.v:121939$4578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:120318$4523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:121925$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187585,10 +190005,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120318$4523_Y + connect \Y $or$libresoc.v:121925$4564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120321$4526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121928$4567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187596,10 +190016,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120321$4526_Y + connect \Y $or$libresoc.v:121928$4567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120324$4529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:121931$4570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187607,10 +190027,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120324$4529_Y + connect \Y $or$libresoc.v:121931$4570_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:120326$4531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:121933$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -187618,10 +190038,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120326$4531_Y + connect \Y $or$libresoc.v:121933$4572_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120337.13-120359.4" + attribute \src "libresoc.v:121944.13-121966.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -187646,7 +190066,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120360.16-120371.4" + attribute \src "libresoc.v:121967.16-121978.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -187660,37 +190080,37 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120372.16-120376.4" + attribute \src "libresoc.v:121979.16-121983.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120377.16-120380.4" + attribute \src "libresoc.v:121984.16-121987.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119952.7-119952.20" - process $proc$libresoc.v:119952$4545 + attribute \src "libresoc.v:121559.7-121559.20" + process $proc$libresoc.v:121559$4586 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120381.3-120395.6" - process $proc$libresoc.v:120381$4542 + attribute \src "libresoc.v:121988.3-122002.6" + process $proc$libresoc.v:121988$4583 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:120382.5-120382.29" + attribute \src "libresoc.v:121989.5-121989.29" switch \initial - attribute \src "libresoc.v:120382.9-120382.17" + attribute \src "libresoc.v:121989.9-121989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -187708,18 +190128,18 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:120396.3-120405.6" - process $proc$libresoc.v:120396$4543 + attribute \src "libresoc.v:122003.3-122012.6" + process $proc$libresoc.v:122003$4584 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:120397.5-120397.29" + attribute \src "libresoc.v:122004.5-122004.29" switch \initial - attribute \src "libresoc.v:120397.9-120397.17" + attribute \src "libresoc.v:122004.9-122004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:869" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -187731,18 +190151,18 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:120406.3-120418.6" - process $proc$libresoc.v:120406$4544 + attribute \src "libresoc.v:122013.3-122025.6" + process $proc$libresoc.v:122013$4585 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:120407.5-120407.29" + attribute \src "libresoc.v:122014.5-122014.29" switch \initial - attribute \src "libresoc.v:120407.9-120407.17" + attribute \src "libresoc.v:122014.9-122014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -187758,30 +190178,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:120313$4518_Y - connect \$12 $not$libresoc.v:120314$4519_Y - connect \$14 $and$libresoc.v:120315$4520_Y - connect \$16 $eq$libresoc.v:120316$4521_Y - connect \$18 $eq$libresoc.v:120317$4522_Y - connect \$20 $or$libresoc.v:120318$4523_Y - connect \$22 $eq$libresoc.v:120319$4524_Y - connect \$24 $eq$libresoc.v:120320$4525_Y - connect \$26 $or$libresoc.v:120321$4526_Y - connect \$28 $eq$libresoc.v:120322$4527_Y - connect \$2 $eq$libresoc.v:120323$4528_Y - connect \$30 $or$libresoc.v:120324$4529_Y - connect \$32 $eq$libresoc.v:120325$4530_Y - connect \$34 $or$libresoc.v:120326$4531_Y - connect \$36 $eq$libresoc.v:120327$4532_Y - connect \$38 $and$libresoc.v:120328$4533_Y - connect \$40 $and$libresoc.v:120329$4534_Y - connect \$42 $eq$libresoc.v:120330$4535_Y - connect \$44 $and$libresoc.v:120331$4536_Y - connect \$46 $not$libresoc.v:120332$4537_Y - connect \$48 $and$libresoc.v:120333$4538_Y - connect \$4 $and$libresoc.v:120334$4539_Y - connect \$6 $and$libresoc.v:120335$4540_Y - connect \$8 $eq$libresoc.v:120336$4541_Y + connect \$10 $and$libresoc.v:121920$4559_Y + connect \$12 $not$libresoc.v:121921$4560_Y + connect \$14 $and$libresoc.v:121922$4561_Y + connect \$16 $eq$libresoc.v:121923$4562_Y + connect \$18 $eq$libresoc.v:121924$4563_Y + connect \$20 $or$libresoc.v:121925$4564_Y + connect \$22 $eq$libresoc.v:121926$4565_Y + connect \$24 $eq$libresoc.v:121927$4566_Y + connect \$26 $or$libresoc.v:121928$4567_Y + connect \$28 $eq$libresoc.v:121929$4568_Y + connect \$2 $eq$libresoc.v:121930$4569_Y + connect \$30 $or$libresoc.v:121931$4570_Y + connect \$32 $eq$libresoc.v:121932$4571_Y + connect \$34 $or$libresoc.v:121933$4572_Y + connect \$36 $eq$libresoc.v:121934$4573_Y + connect \$38 $and$libresoc.v:121935$4574_Y + connect \$40 $and$libresoc.v:121936$4575_Y + connect \$42 $eq$libresoc.v:121937$4576_Y + connect \$44 $and$libresoc.v:121938$4577_Y + connect \$46 $not$libresoc.v:121939$4578_Y + connect \$48 $and$libresoc.v:121940$4579_Y + connect \$4 $and$libresoc.v:121941$4580_Y + connect \$6 $and$libresoc.v:121942$4581_Y + connect \$8 $eq$libresoc.v:121943$4582_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -187795,116 +190215,116 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:120435.1-120807.10" +attribute \src "libresoc.v:122042.1-122414.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:120784.3-120798.6" + attribute \src "libresoc.v:122391.3-122405.6" wire width 14 $0\CR__fn_unit[13:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:122378.3-122390.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:120436.7-120436.20" + attribute \src "libresoc.v:122043.7-122043.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120784.3-120798.6" + attribute \src "libresoc.v:122391.3-122405.6" wire width 14 $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:122378.3-122390.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:120726.18-120726.113" - wire $and$libresoc.v:120726$4546_Y - attribute \src "libresoc.v:120728.18-120728.110" - wire $and$libresoc.v:120728$4548_Y - attribute \src "libresoc.v:120741.18-120741.114" - wire $and$libresoc.v:120741$4561_Y - attribute \src "libresoc.v:120742.18-120742.116" - wire $and$libresoc.v:120742$4562_Y - attribute \src "libresoc.v:120744.18-120744.114" - wire $and$libresoc.v:120744$4564_Y - attribute \src "libresoc.v:120746.18-120746.110" - wire $and$libresoc.v:120746$4566_Y - attribute \src "libresoc.v:120747.17-120747.112" - wire $and$libresoc.v:120747$4567_Y - attribute \src "libresoc.v:120748.17-120748.114" - wire $and$libresoc.v:120748$4568_Y - attribute \src "libresoc.v:120729.18-120729.125" - wire $eq$libresoc.v:120729$4549_Y - attribute \src "libresoc.v:120730.18-120730.125" - wire $eq$libresoc.v:120730$4550_Y - attribute \src "libresoc.v:120732.18-120732.110" - wire $eq$libresoc.v:120732$4552_Y - attribute \src "libresoc.v:120733.18-120733.110" - wire $eq$libresoc.v:120733$4553_Y - attribute \src "libresoc.v:120735.18-120735.112" - wire $eq$libresoc.v:120735$4555_Y - attribute \src "libresoc.v:120736.17-120736.129" - wire $eq$libresoc.v:120736$4556_Y - attribute \src "libresoc.v:120738.18-120738.110" - wire $eq$libresoc.v:120738$4558_Y - attribute \src "libresoc.v:120740.18-120740.130" - wire $eq$libresoc.v:120740$4560_Y - attribute \src "libresoc.v:120743.18-120743.130" - wire $eq$libresoc.v:120743$4563_Y - attribute \src "libresoc.v:120749.17-120749.129" - wire $eq$libresoc.v:120749$4569_Y - attribute \src "libresoc.v:120727.18-120727.110" - wire $not$libresoc.v:120727$4547_Y - attribute \src "libresoc.v:120745.18-120745.110" - wire $not$libresoc.v:120745$4565_Y - attribute \src "libresoc.v:120731.18-120731.110" - wire $or$libresoc.v:120731$4551_Y - attribute \src "libresoc.v:120734.18-120734.110" - wire $or$libresoc.v:120734$4554_Y - attribute \src "libresoc.v:120737.18-120737.110" - wire $or$libresoc.v:120737$4557_Y - attribute \src "libresoc.v:120739.18-120739.110" - wire $or$libresoc.v:120739$4559_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:122333.18-122333.113" + wire $and$libresoc.v:122333$4587_Y + attribute \src "libresoc.v:122335.18-122335.110" + wire $and$libresoc.v:122335$4589_Y + attribute \src "libresoc.v:122348.18-122348.114" + wire $and$libresoc.v:122348$4602_Y + attribute \src "libresoc.v:122349.18-122349.116" + wire $and$libresoc.v:122349$4603_Y + attribute \src "libresoc.v:122351.18-122351.114" + wire $and$libresoc.v:122351$4605_Y + attribute \src "libresoc.v:122353.18-122353.110" + wire $and$libresoc.v:122353$4607_Y + attribute \src "libresoc.v:122354.17-122354.112" + wire $and$libresoc.v:122354$4608_Y + attribute \src "libresoc.v:122355.17-122355.114" + wire $and$libresoc.v:122355$4609_Y + attribute \src "libresoc.v:122336.18-122336.125" + wire $eq$libresoc.v:122336$4590_Y + attribute \src "libresoc.v:122337.18-122337.125" + wire $eq$libresoc.v:122337$4591_Y + attribute \src "libresoc.v:122339.18-122339.110" + wire $eq$libresoc.v:122339$4593_Y + attribute \src "libresoc.v:122340.18-122340.110" + wire $eq$libresoc.v:122340$4594_Y + attribute \src "libresoc.v:122342.18-122342.112" + wire $eq$libresoc.v:122342$4596_Y + attribute \src "libresoc.v:122343.17-122343.129" + wire $eq$libresoc.v:122343$4597_Y + attribute \src "libresoc.v:122345.18-122345.110" + wire $eq$libresoc.v:122345$4599_Y + attribute \src "libresoc.v:122347.18-122347.130" + wire $eq$libresoc.v:122347$4601_Y + attribute \src "libresoc.v:122350.18-122350.130" + wire $eq$libresoc.v:122350$4604_Y + attribute \src "libresoc.v:122356.17-122356.129" + wire $eq$libresoc.v:122356$4610_Y + attribute \src "libresoc.v:122334.18-122334.110" + wire $not$libresoc.v:122334$4588_Y + attribute \src "libresoc.v:122352.18-122352.110" + wire $not$libresoc.v:122352$4606_Y + attribute \src "libresoc.v:122338.18-122338.110" + wire $or$libresoc.v:122338$4592_Y + attribute \src "libresoc.v:122341.18-122341.110" + wire $or$libresoc.v:122341$4595_Y + attribute \src "libresoc.v:122344.18-122344.110" + wire $or$libresoc.v:122344$4598_Y + attribute \src "libresoc.v:122346.18-122346.110" + wire $or$libresoc.v:122346$4600_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188002,13 +190422,13 @@ module \dec_CR attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_CR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -188017,7 +190437,7 @@ module \dec_CR attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188034,7 +190454,7 @@ module \dec_CR attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -188111,44 +190531,44 @@ module \dec_CR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_CR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120436.7-120436.15" + attribute \src "libresoc.v:122043.7-122043.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 5 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120726$4546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122333$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188156,10 +190576,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:120726$4546_Y + connect \Y $and$libresoc.v:122333$4587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120728$4548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122335$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188167,10 +190587,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:120728$4548_Y + connect \Y $and$libresoc.v:122335$4589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120741$4561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122348$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188178,10 +190598,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:120741$4561_Y + connect \Y $and$libresoc.v:122348$4602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120742$4562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122349$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188189,10 +190609,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120742$4562_Y + connect \Y $and$libresoc.v:122349$4603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120744$4564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122351$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188200,10 +190620,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:120744$4564_Y + connect \Y $and$libresoc.v:122351$4605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:120746$4566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122353$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188211,10 +190631,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:120746$4566_Y + connect \Y $and$libresoc.v:122353$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120747$4567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122354$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188222,10 +190642,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:120747$4567_Y + connect \Y $and$libresoc.v:122354$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:120748$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122355$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188233,10 +190653,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:120748$4568_Y + connect \Y $and$libresoc.v:122355$4609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:120729$4549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122336$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188244,10 +190664,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120729$4549_Y + connect \Y $eq$libresoc.v:122336$4590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:120730$4550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:122337$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188255,10 +190675,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120730$4550_Y + connect \Y $eq$libresoc.v:122337$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120732$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122339$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188266,10 +190686,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:120732$4552_Y + connect \Y $eq$libresoc.v:122339$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120733$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122340$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188277,10 +190697,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:120733$4553_Y + connect \Y $eq$libresoc.v:122340$4594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:120735$4555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122342$4596 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188288,10 +190708,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120735$4555_Y + connect \Y $eq$libresoc.v:122342$4596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120736$4556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122343$4597 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188299,10 +190719,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120736$4556_Y + connect \Y $eq$libresoc.v:122343$4597_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:120738$4558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:122345$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -188310,10 +190730,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:120738$4558_Y + connect \Y $eq$libresoc.v:122345$4599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:120740$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122347$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188321,10 +190741,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:120740$4560_Y + connect \Y $eq$libresoc.v:122347$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120743$4563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122350$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188332,10 +190752,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120743$4563_Y + connect \Y $eq$libresoc.v:122350$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:120749$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122356$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -188343,26 +190763,26 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:120749$4569_Y + connect \Y $eq$libresoc.v:122356$4610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120727$4547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122334$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120727$4547_Y + connect \Y $not$libresoc.v:122334$4588_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:120745$4565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122352$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:120745$4565_Y + connect \Y $not$libresoc.v:122352$4606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:120731$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:122338$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188370,10 +190790,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:120731$4551_Y + connect \Y $or$libresoc.v:122338$4592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120734$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122341$4595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188381,10 +190801,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:120734$4554_Y + connect \Y $or$libresoc.v:122341$4595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:120737$4557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122344$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188392,10 +190812,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:120737$4557_Y + connect \Y $or$libresoc.v:122344$4598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:120739$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:122346$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188403,10 +190823,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:120739$4559_Y + connect \Y $or$libresoc.v:122346$4600_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120750.13-120761.4" + attribute \src "libresoc.v:122357.13-122368.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -188420,38 +190840,38 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120762.16-120766.4" + attribute \src "libresoc.v:122369.16-122373.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120767.16-120770.4" + attribute \src "libresoc.v:122374.16-122377.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120436.7-120436.20" - process $proc$libresoc.v:120436$4572 + attribute \src "libresoc.v:122043.7-122043.20" + process $proc$libresoc.v:122043$4613 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120771.3-120783.6" - process $proc$libresoc.v:120771$4570 + attribute \src "libresoc.v:122378.3-122390.6" + process $proc$libresoc.v:122378$4611 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:120772.5-120772.29" + attribute \src "libresoc.v:122379.5-122379.29" switch \initial - attribute \src "libresoc.v:120772.9-120772.17" + attribute \src "libresoc.v:122379.9-122379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -188467,17 +190887,17 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:120784.3-120798.6" - process $proc$libresoc.v:120784$4571 + attribute \src "libresoc.v:122391.3-122405.6" + process $proc$libresoc.v:122391$4612 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:120785.5-120785.29" + attribute \src "libresoc.v:122392.5-122392.29" switch \initial - attribute \src "libresoc.v:120785.9-120785.17" + attribute \src "libresoc.v:122392.9-122392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -188495,30 +190915,30 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:120726$4546_Y - connect \$12 $not$libresoc.v:120727$4547_Y - connect \$14 $and$libresoc.v:120728$4548_Y - connect \$16 $eq$libresoc.v:120729$4549_Y - connect \$18 $eq$libresoc.v:120730$4550_Y - connect \$20 $or$libresoc.v:120731$4551_Y - connect \$22 $eq$libresoc.v:120732$4552_Y - connect \$24 $eq$libresoc.v:120733$4553_Y - connect \$26 $or$libresoc.v:120734$4554_Y - connect \$28 $eq$libresoc.v:120735$4555_Y - connect \$2 $eq$libresoc.v:120736$4556_Y - connect \$30 $or$libresoc.v:120737$4557_Y - connect \$32 $eq$libresoc.v:120738$4558_Y - connect \$34 $or$libresoc.v:120739$4559_Y - connect \$36 $eq$libresoc.v:120740$4560_Y - connect \$38 $and$libresoc.v:120741$4561_Y - connect \$40 $and$libresoc.v:120742$4562_Y - connect \$42 $eq$libresoc.v:120743$4563_Y - connect \$44 $and$libresoc.v:120744$4564_Y - connect \$46 $not$libresoc.v:120745$4565_Y - connect \$48 $and$libresoc.v:120746$4566_Y - connect \$4 $and$libresoc.v:120747$4567_Y - connect \$6 $and$libresoc.v:120748$4568_Y - connect \$8 $eq$libresoc.v:120749$4569_Y + connect \$10 $and$libresoc.v:122333$4587_Y + connect \$12 $not$libresoc.v:122334$4588_Y + connect \$14 $and$libresoc.v:122335$4589_Y + connect \$16 $eq$libresoc.v:122336$4590_Y + connect \$18 $eq$libresoc.v:122337$4591_Y + connect \$20 $or$libresoc.v:122338$4592_Y + connect \$22 $eq$libresoc.v:122339$4593_Y + connect \$24 $eq$libresoc.v:122340$4594_Y + connect \$26 $or$libresoc.v:122341$4595_Y + connect \$28 $eq$libresoc.v:122342$4596_Y + connect \$2 $eq$libresoc.v:122343$4597_Y + connect \$30 $or$libresoc.v:122344$4598_Y + connect \$32 $eq$libresoc.v:122345$4599_Y + connect \$34 $or$libresoc.v:122346$4600_Y + connect \$36 $eq$libresoc.v:122347$4601_Y + connect \$38 $and$libresoc.v:122348$4602_Y + connect \$40 $and$libresoc.v:122349$4603_Y + connect \$42 $eq$libresoc.v:122350$4604_Y + connect \$44 $and$libresoc.v:122351$4605_Y + connect \$46 $not$libresoc.v:122352$4606_Y + connect \$48 $and$libresoc.v:122353$4607_Y + connect \$4 $and$libresoc.v:122354$4608_Y + connect \$6 $and$libresoc.v:122355$4609_Y + connect \$8 $eq$libresoc.v:122356$4610_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -188528,120 +190948,120 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:120811.1-121394.10" +attribute \src "libresoc.v:122418.1-123001.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:121357.3-121371.6" + attribute \src "libresoc.v:122964.3-122978.6" wire width 14 $0\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121344.3-121356.6" + attribute \src "libresoc.v:122951.3-122963.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:121329.3-121343.6" + attribute \src "libresoc.v:122936.3-122950.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:120812.7-120812.20" + attribute \src "libresoc.v:122419.7-122419.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121357.3-121371.6" + attribute \src "libresoc.v:122964.3-122978.6" wire width 14 $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121344.3-121356.6" + attribute \src "libresoc.v:122951.3-122963.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:121329.3-121343.6" + attribute \src "libresoc.v:122936.3-122950.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:121245.18-121245.113" - wire $and$libresoc.v:121245$4573_Y - attribute \src "libresoc.v:121247.18-121247.110" - wire $and$libresoc.v:121247$4575_Y - attribute \src "libresoc.v:121260.18-121260.114" - wire $and$libresoc.v:121260$4588_Y - attribute \src "libresoc.v:121261.18-121261.116" - wire $and$libresoc.v:121261$4589_Y - attribute \src "libresoc.v:121263.18-121263.114" - wire $and$libresoc.v:121263$4591_Y - attribute \src "libresoc.v:121265.18-121265.110" - wire $and$libresoc.v:121265$4593_Y - attribute \src "libresoc.v:121266.17-121266.112" - wire $and$libresoc.v:121266$4594_Y - attribute \src "libresoc.v:121267.17-121267.114" - wire $and$libresoc.v:121267$4595_Y - attribute \src "libresoc.v:121248.18-121248.126" - wire $eq$libresoc.v:121248$4576_Y - attribute \src "libresoc.v:121249.18-121249.126" - wire $eq$libresoc.v:121249$4577_Y - attribute \src "libresoc.v:121251.18-121251.110" - wire $eq$libresoc.v:121251$4579_Y - attribute \src "libresoc.v:121252.18-121252.110" - wire $eq$libresoc.v:121252$4580_Y - attribute \src "libresoc.v:121254.18-121254.112" - wire $eq$libresoc.v:121254$4582_Y - attribute \src "libresoc.v:121255.17-121255.130" - wire $eq$libresoc.v:121255$4583_Y - attribute \src "libresoc.v:121257.18-121257.110" - wire $eq$libresoc.v:121257$4585_Y - attribute \src "libresoc.v:121259.18-121259.131" - wire $eq$libresoc.v:121259$4587_Y - attribute \src "libresoc.v:121262.18-121262.131" - wire $eq$libresoc.v:121262$4590_Y - attribute \src "libresoc.v:121268.17-121268.130" - wire $eq$libresoc.v:121268$4596_Y - attribute \src "libresoc.v:121246.18-121246.110" - wire $not$libresoc.v:121246$4574_Y - attribute \src "libresoc.v:121264.18-121264.110" - wire $not$libresoc.v:121264$4592_Y - attribute \src "libresoc.v:121250.18-121250.110" - wire $or$libresoc.v:121250$4578_Y - attribute \src "libresoc.v:121253.18-121253.110" - wire $or$libresoc.v:121253$4581_Y - attribute \src "libresoc.v:121256.18-121256.110" - wire $or$libresoc.v:121256$4584_Y - attribute \src "libresoc.v:121258.18-121258.110" - wire $or$libresoc.v:121258$4586_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:122852.18-122852.113" + wire $and$libresoc.v:122852$4614_Y + attribute \src "libresoc.v:122854.18-122854.110" + wire $and$libresoc.v:122854$4616_Y + attribute \src "libresoc.v:122867.18-122867.114" + wire $and$libresoc.v:122867$4629_Y + attribute \src "libresoc.v:122868.18-122868.116" + wire $and$libresoc.v:122868$4630_Y + attribute \src "libresoc.v:122870.18-122870.114" + wire $and$libresoc.v:122870$4632_Y + attribute \src "libresoc.v:122872.18-122872.110" + wire $and$libresoc.v:122872$4634_Y + attribute \src "libresoc.v:122873.17-122873.112" + wire $and$libresoc.v:122873$4635_Y + attribute \src "libresoc.v:122874.17-122874.114" + wire $and$libresoc.v:122874$4636_Y + attribute \src "libresoc.v:122855.18-122855.126" + wire $eq$libresoc.v:122855$4617_Y + attribute \src "libresoc.v:122856.18-122856.126" + wire $eq$libresoc.v:122856$4618_Y + attribute \src "libresoc.v:122858.18-122858.110" + wire $eq$libresoc.v:122858$4620_Y + attribute \src "libresoc.v:122859.18-122859.110" + wire $eq$libresoc.v:122859$4621_Y + attribute \src "libresoc.v:122861.18-122861.112" + wire $eq$libresoc.v:122861$4623_Y + attribute \src "libresoc.v:122862.17-122862.130" + wire $eq$libresoc.v:122862$4624_Y + attribute \src "libresoc.v:122864.18-122864.110" + wire $eq$libresoc.v:122864$4626_Y + attribute \src "libresoc.v:122866.18-122866.131" + wire $eq$libresoc.v:122866$4628_Y + attribute \src "libresoc.v:122869.18-122869.131" + wire $eq$libresoc.v:122869$4631_Y + attribute \src "libresoc.v:122875.17-122875.130" + wire $eq$libresoc.v:122875$4637_Y + attribute \src "libresoc.v:122853.18-122853.110" + wire $not$libresoc.v:122853$4615_Y + attribute \src "libresoc.v:122871.18-122871.110" + wire $not$libresoc.v:122871$4633_Y + attribute \src "libresoc.v:122857.18-122857.110" + wire $or$libresoc.v:122857$4619_Y + attribute \src "libresoc.v:122860.18-122860.110" + wire $or$libresoc.v:122860$4622_Y + attribute \src "libresoc.v:122863.18-122863.110" + wire $or$libresoc.v:122863$4625_Y + attribute \src "libresoc.v:122865.18-122865.110" + wire $or$libresoc.v:122865$4627_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \DIV__data_len @@ -188773,27 +191193,27 @@ module \dec_DIV wire output 15 \DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -188802,15 +191222,15 @@ module \dec_DIV attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -188827,7 +191247,7 @@ module \dec_DIV attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188835,7 +191255,7 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -188852,7 +191272,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -188929,13 +191349,13 @@ module \dec_DIV attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -188943,19 +191363,19 @@ module \dec_DIV attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188963,9 +191383,9 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -188986,7 +191406,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -188996,9 +191416,9 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -189008,26 +191428,26 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120812.7-120812.15" + attribute \src "libresoc.v:122419.7-122419.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121245$4573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122852$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189035,10 +191455,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121245$4573_Y + connect \Y $and$libresoc.v:122852$4614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121247$4575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122854$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189046,10 +191466,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121247$4575_Y + connect \Y $and$libresoc.v:122854$4616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121260$4588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122867$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189057,10 +191477,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121260$4588_Y + connect \Y $and$libresoc.v:122867$4629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121261$4589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122868$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189068,10 +191488,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121261$4589_Y + connect \Y $and$libresoc.v:122868$4630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121263$4591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122870$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189079,10 +191499,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121263$4591_Y + connect \Y $and$libresoc.v:122870$4632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121265$4593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:122872$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189090,10 +191510,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121265$4593_Y + connect \Y $and$libresoc.v:122872$4634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121266$4594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122873$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189101,10 +191521,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121266$4594_Y + connect \Y $and$libresoc.v:122873$4635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121267$4595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:122874$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189112,10 +191532,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121267$4595_Y + connect \Y $and$libresoc.v:122874$4636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121248$4576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:122855$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189123,10 +191543,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121248$4576_Y + connect \Y $eq$libresoc.v:122855$4617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121249$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:122856$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189134,10 +191554,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121249$4577_Y + connect \Y $eq$libresoc.v:122856$4618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121251$4579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122858$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189145,10 +191565,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121251$4579_Y + connect \Y $eq$libresoc.v:122858$4620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121252$4580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122859$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189156,10 +191576,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121252$4580_Y + connect \Y $eq$libresoc.v:122859$4621_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121254$4582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:122861$4623 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189167,10 +191587,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121254$4582_Y + connect \Y $eq$libresoc.v:122861$4623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121255$4583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122862$4624 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189178,10 +191598,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121255$4583_Y + connect \Y $eq$libresoc.v:122862$4624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121257$4585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:122864$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189189,10 +191609,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121257$4585_Y + connect \Y $eq$libresoc.v:122864$4626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121259$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:122866$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189200,10 +191620,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121259$4587_Y + connect \Y $eq$libresoc.v:122866$4628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121262$4590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122869$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189211,10 +191631,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121262$4590_Y + connect \Y $eq$libresoc.v:122869$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121268$4596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:122875$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189222,26 +191642,26 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121268$4596_Y + connect \Y $eq$libresoc.v:122875$4637_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121246$4574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122853$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121246$4574_Y + connect \Y $not$libresoc.v:122853$4615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121264$4592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:122871$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121264$4592_Y + connect \Y $not$libresoc.v:122871$4633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:121250$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:122857$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189249,10 +191669,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121250$4578_Y + connect \Y $or$libresoc.v:122857$4619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121253$4581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122860$4622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189260,10 +191680,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121253$4581_Y + connect \Y $or$libresoc.v:122860$4622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121256$4584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:122863$4625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189271,10 +191691,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121256$4584_Y + connect \Y $or$libresoc.v:122863$4625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121258$4586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:122865$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189282,10 +191702,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121258$4586_Y + connect \Y $or$libresoc.v:122865$4627_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121269.13-121297.4" + attribute \src "libresoc.v:122876.13-122904.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -189316,7 +191736,7 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121298.16-121303.4" + attribute \src "libresoc.v:122905.16-122910.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out @@ -189324,7 +191744,7 @@ module \dec_DIV connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121304.16-121315.4" + attribute \src "libresoc.v:122911.16-122922.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -189338,7 +191758,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121316.16-121322.4" + attribute \src "libresoc.v:122923.16-122929.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -189347,33 +191767,33 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121323.16-121328.4" + attribute \src "libresoc.v:122930.16-122935.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120812.7-120812.20" - process $proc$libresoc.v:120812$4600 + attribute \src "libresoc.v:122419.7-122419.20" + process $proc$libresoc.v:122419$4641 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121329.3-121343.6" - process $proc$libresoc.v:121329$4597 + attribute \src "libresoc.v:122936.3-122950.6" + process $proc$libresoc.v:122936$4638 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:121330.5-121330.29" + attribute \src "libresoc.v:122937.5-122937.29" switch \initial - attribute \src "libresoc.v:121330.9-121330.17" + attribute \src "libresoc.v:122937.9-122937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -189389,18 +191809,18 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:121344.3-121356.6" - process $proc$libresoc.v:121344$4598 + attribute \src "libresoc.v:122951.3-122963.6" + process $proc$libresoc.v:122951$4639 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:121345.5-121345.29" + attribute \src "libresoc.v:122952.5-122952.29" switch \initial - attribute \src "libresoc.v:121345.9-121345.17" + attribute \src "libresoc.v:122952.9-122952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189416,17 +191836,17 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:121357.3-121371.6" - process $proc$libresoc.v:121357$4599 + attribute \src "libresoc.v:122964.3-122978.6" + process $proc$libresoc.v:122964$4640 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:121358.5-121358.29" + attribute \src "libresoc.v:122965.5-122965.29" switch \initial - attribute \src "libresoc.v:121358.9-121358.17" + attribute \src "libresoc.v:122965.9-122965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -189444,30 +191864,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121245$4573_Y - connect \$12 $not$libresoc.v:121246$4574_Y - connect \$14 $and$libresoc.v:121247$4575_Y - connect \$16 $eq$libresoc.v:121248$4576_Y - connect \$18 $eq$libresoc.v:121249$4577_Y - connect \$20 $or$libresoc.v:121250$4578_Y - connect \$22 $eq$libresoc.v:121251$4579_Y - connect \$24 $eq$libresoc.v:121252$4580_Y - connect \$26 $or$libresoc.v:121253$4581_Y - connect \$28 $eq$libresoc.v:121254$4582_Y - connect \$2 $eq$libresoc.v:121255$4583_Y - connect \$30 $or$libresoc.v:121256$4584_Y - connect \$32 $eq$libresoc.v:121257$4585_Y - connect \$34 $or$libresoc.v:121258$4586_Y - connect \$36 $eq$libresoc.v:121259$4587_Y - connect \$38 $and$libresoc.v:121260$4588_Y - connect \$40 $and$libresoc.v:121261$4589_Y - connect \$42 $eq$libresoc.v:121262$4590_Y - connect \$44 $and$libresoc.v:121263$4591_Y - connect \$46 $not$libresoc.v:121264$4592_Y - connect \$48 $and$libresoc.v:121265$4593_Y - connect \$4 $and$libresoc.v:121266$4594_Y - connect \$6 $and$libresoc.v:121267$4595_Y - connect \$8 $eq$libresoc.v:121268$4596_Y + connect \$10 $and$libresoc.v:122852$4614_Y + connect \$12 $not$libresoc.v:122853$4615_Y + connect \$14 $and$libresoc.v:122854$4616_Y + connect \$16 $eq$libresoc.v:122855$4617_Y + connect \$18 $eq$libresoc.v:122856$4618_Y + connect \$20 $or$libresoc.v:122857$4619_Y + connect \$22 $eq$libresoc.v:122858$4620_Y + connect \$24 $eq$libresoc.v:122859$4621_Y + connect \$26 $or$libresoc.v:122860$4622_Y + connect \$28 $eq$libresoc.v:122861$4623_Y + connect \$2 $eq$libresoc.v:122862$4624_Y + connect \$30 $or$libresoc.v:122863$4625_Y + connect \$32 $eq$libresoc.v:122864$4626_Y + connect \$34 $or$libresoc.v:122865$4627_Y + connect \$36 $eq$libresoc.v:122866$4628_Y + connect \$38 $and$libresoc.v:122867$4629_Y + connect \$40 $and$libresoc.v:122868$4630_Y + connect \$42 $eq$libresoc.v:122869$4631_Y + connect \$44 $and$libresoc.v:122870$4632_Y + connect \$46 $not$libresoc.v:122871$4633_Y + connect \$48 $and$libresoc.v:122872$4634_Y + connect \$4 $and$libresoc.v:122873$4635_Y + connect \$6 $and$libresoc.v:122874$4636_Y + connect \$8 $eq$libresoc.v:122875$4637_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -189491,116 +191911,116 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:121398.1-121959.10" +attribute \src "libresoc.v:123005.1-123566.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:121923.3-121937.6" + attribute \src "libresoc.v:123530.3-123544.6" wire width 14 $0\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121910.3-121922.6" + attribute \src "libresoc.v:123517.3-123529.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:121399.7-121399.20" + attribute \src "libresoc.v:123006.7-123006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121923.3-121937.6" + attribute \src "libresoc.v:123530.3-123544.6" wire width 14 $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121910.3-121922.6" + attribute \src "libresoc.v:123517.3-123529.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:121827.18-121827.113" - wire $and$libresoc.v:121827$4601_Y - attribute \src "libresoc.v:121829.18-121829.110" - wire $and$libresoc.v:121829$4603_Y - attribute \src "libresoc.v:121842.18-121842.114" - wire $and$libresoc.v:121842$4616_Y - attribute \src "libresoc.v:121843.18-121843.116" - wire $and$libresoc.v:121843$4617_Y - attribute \src "libresoc.v:121845.18-121845.114" - wire $and$libresoc.v:121845$4619_Y - attribute \src "libresoc.v:121847.18-121847.110" - wire $and$libresoc.v:121847$4621_Y - attribute \src "libresoc.v:121848.17-121848.112" - wire $and$libresoc.v:121848$4622_Y - attribute \src "libresoc.v:121849.17-121849.114" - wire $and$libresoc.v:121849$4623_Y - attribute \src "libresoc.v:121830.18-121830.127" - wire $eq$libresoc.v:121830$4604_Y - attribute \src "libresoc.v:121831.18-121831.127" - wire $eq$libresoc.v:121831$4605_Y - attribute \src "libresoc.v:121833.18-121833.110" - wire $eq$libresoc.v:121833$4607_Y - attribute \src "libresoc.v:121834.18-121834.110" - wire $eq$libresoc.v:121834$4608_Y - attribute \src "libresoc.v:121836.18-121836.112" - wire $eq$libresoc.v:121836$4610_Y - attribute \src "libresoc.v:121837.17-121837.131" - wire $eq$libresoc.v:121837$4611_Y - attribute \src "libresoc.v:121839.18-121839.110" - wire $eq$libresoc.v:121839$4613_Y - attribute \src "libresoc.v:121841.18-121841.132" - wire $eq$libresoc.v:121841$4615_Y - attribute \src "libresoc.v:121844.18-121844.132" - wire $eq$libresoc.v:121844$4618_Y - attribute \src "libresoc.v:121850.17-121850.131" - wire $eq$libresoc.v:121850$4624_Y - attribute \src "libresoc.v:121828.18-121828.110" - wire $not$libresoc.v:121828$4602_Y - attribute \src "libresoc.v:121846.18-121846.110" - wire $not$libresoc.v:121846$4620_Y - attribute \src "libresoc.v:121832.18-121832.110" - wire $or$libresoc.v:121832$4606_Y - attribute \src "libresoc.v:121835.18-121835.110" - wire $or$libresoc.v:121835$4609_Y - attribute \src "libresoc.v:121838.18-121838.110" - wire $or$libresoc.v:121838$4612_Y - attribute \src "libresoc.v:121840.18-121840.110" - wire $or$libresoc.v:121840$4614_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:123434.18-123434.113" + wire $and$libresoc.v:123434$4642_Y + attribute \src "libresoc.v:123436.18-123436.110" + wire $and$libresoc.v:123436$4644_Y + attribute \src "libresoc.v:123449.18-123449.114" + wire $and$libresoc.v:123449$4657_Y + attribute \src "libresoc.v:123450.18-123450.116" + wire $and$libresoc.v:123450$4658_Y + attribute \src "libresoc.v:123452.18-123452.114" + wire $and$libresoc.v:123452$4660_Y + attribute \src "libresoc.v:123454.18-123454.110" + wire $and$libresoc.v:123454$4662_Y + attribute \src "libresoc.v:123455.17-123455.112" + wire $and$libresoc.v:123455$4663_Y + attribute \src "libresoc.v:123456.17-123456.114" + wire $and$libresoc.v:123456$4664_Y + attribute \src "libresoc.v:123437.18-123437.127" + wire $eq$libresoc.v:123437$4645_Y + attribute \src "libresoc.v:123438.18-123438.127" + wire $eq$libresoc.v:123438$4646_Y + attribute \src "libresoc.v:123440.18-123440.110" + wire $eq$libresoc.v:123440$4648_Y + attribute \src "libresoc.v:123441.18-123441.110" + wire $eq$libresoc.v:123441$4649_Y + attribute \src "libresoc.v:123443.18-123443.112" + wire $eq$libresoc.v:123443$4651_Y + attribute \src "libresoc.v:123444.17-123444.131" + wire $eq$libresoc.v:123444$4652_Y + attribute \src "libresoc.v:123446.18-123446.110" + wire $eq$libresoc.v:123446$4654_Y + attribute \src "libresoc.v:123448.18-123448.132" + wire $eq$libresoc.v:123448$4656_Y + attribute \src "libresoc.v:123451.18-123451.132" + wire $eq$libresoc.v:123451$4659_Y + attribute \src "libresoc.v:123457.17-123457.131" + wire $eq$libresoc.v:123457$4665_Y + attribute \src "libresoc.v:123435.18-123435.110" + wire $not$libresoc.v:123435$4643_Y + attribute \src "libresoc.v:123453.18-123453.110" + wire $not$libresoc.v:123453$4661_Y + attribute \src "libresoc.v:123439.18-123439.110" + wire $or$libresoc.v:123439$4647_Y + attribute \src "libresoc.v:123442.18-123442.110" + wire $or$libresoc.v:123442$4650_Y + attribute \src "libresoc.v:123445.18-123445.110" + wire $or$libresoc.v:123445$4653_Y + attribute \src "libresoc.v:123447.18-123447.110" + wire $or$libresoc.v:123447$4655_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \LDST__byte_reverse @@ -189729,29 +192149,29 @@ module \dec_LDST wire output 16 \LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_br attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -189760,7 +192180,7 @@ module \dec_LDST attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -189777,7 +192197,7 @@ module \dec_LDST attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -189785,7 +192205,7 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -189802,7 +192222,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -189879,9 +192299,9 @@ module \dec_LDST attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -189889,28 +192309,28 @@ module \dec_LDST attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -189918,9 +192338,9 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -189941,7 +192361,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -189951,9 +192371,9 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -189963,26 +192383,26 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121399.7-121399.15" + attribute \src "libresoc.v:123006.7-123006.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121827$4601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123434$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189990,10 +192410,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121827$4601_Y + connect \Y $and$libresoc.v:123434$4642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121829$4603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123436$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190001,10 +192421,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121829$4603_Y + connect \Y $and$libresoc.v:123436$4644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121842$4616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123449$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190012,10 +192432,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121842$4616_Y + connect \Y $and$libresoc.v:123449$4657_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121843$4617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123450$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190023,10 +192443,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121843$4617_Y + connect \Y $and$libresoc.v:123450$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121845$4619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123452$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190034,10 +192454,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121845$4619_Y + connect \Y $and$libresoc.v:123452$4660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:121847$4621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:123454$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190045,10 +192465,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121847$4621_Y + connect \Y $and$libresoc.v:123454$4662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121848$4622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123455$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190056,10 +192476,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121848$4622_Y + connect \Y $and$libresoc.v:123455$4663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:121849$4623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:123456$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190067,10 +192487,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121849$4623_Y + connect \Y $and$libresoc.v:123456$4664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:121830$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:123437$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190078,10 +192498,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121830$4604_Y + connect \Y $eq$libresoc.v:123437$4645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121831$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:123438$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190089,10 +192509,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121831$4605_Y + connect \Y $eq$libresoc.v:123438$4646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121833$4607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123440$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190100,10 +192520,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121833$4607_Y + connect \Y $eq$libresoc.v:123440$4648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121834$4608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123441$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190111,10 +192531,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121834$4608_Y + connect \Y $eq$libresoc.v:123441$4649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:121836$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:123443$4651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190122,10 +192542,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121836$4610_Y + connect \Y $eq$libresoc.v:123443$4651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121837$4611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123444$4652 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190133,10 +192553,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121837$4611_Y + connect \Y $eq$libresoc.v:123444$4652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121839$4613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:123446$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190144,10 +192564,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121839$4613_Y + connect \Y $eq$libresoc.v:123446$4654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:121841$4615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:123448$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190155,10 +192575,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121841$4615_Y + connect \Y $eq$libresoc.v:123448$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121844$4618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123451$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190166,10 +192586,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121844$4618_Y + connect \Y $eq$libresoc.v:123451$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:121850$4624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:123457$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190177,26 +192597,26 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121850$4624_Y + connect \Y $eq$libresoc.v:123457$4665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121828$4602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123435$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121828$4602_Y + connect \Y $not$libresoc.v:123435$4643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:121846$4620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:123453$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121846$4620_Y + connect \Y $not$libresoc.v:123453$4661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:121832$4606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:123439$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190204,10 +192624,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121832$4606_Y + connect \Y $or$libresoc.v:123439$4647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121835$4609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123442$4650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190215,10 +192635,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121835$4609_Y + connect \Y $or$libresoc.v:123442$4650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:121838$4612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:123445$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190226,10 +192646,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121838$4612_Y + connect \Y $or$libresoc.v:123445$4653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121840$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:123447$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190237,10 +192657,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121840$4614_Y + connect \Y $or$libresoc.v:123447$4655_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121851.13-121878.4" + attribute \src "libresoc.v:123458.13-123485.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -190270,7 +192690,7 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121879.16-121884.4" + attribute \src "libresoc.v:123486.16-123491.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out @@ -190278,7 +192698,7 @@ module \dec_LDST connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121885.16-121896.4" + attribute \src "libresoc.v:123492.16-123503.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -190292,7 +192712,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121897.16-121903.4" + attribute \src "libresoc.v:123504.16-123510.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -190301,33 +192721,33 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121904.16-121909.4" + attribute \src "libresoc.v:123511.16-123516.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121399.7-121399.20" - process $proc$libresoc.v:121399$4627 + attribute \src "libresoc.v:123006.7-123006.20" + process $proc$libresoc.v:123006$4668 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121910.3-121922.6" - process $proc$libresoc.v:121910$4625 + attribute \src "libresoc.v:123517.3-123529.6" + process $proc$libresoc.v:123517$4666 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:121911.5-121911.29" + attribute \src "libresoc.v:123518.5-123518.29" switch \initial - attribute \src "libresoc.v:121911.9-121911.17" + attribute \src "libresoc.v:123518.9-123518.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190343,17 +192763,17 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:121923.3-121937.6" - process $proc$libresoc.v:121923$4626 + attribute \src "libresoc.v:123530.3-123544.6" + process $proc$libresoc.v:123530$4667 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:121924.5-121924.29" + attribute \src "libresoc.v:123531.5-123531.29" switch \initial - attribute \src "libresoc.v:121924.9-121924.17" + attribute \src "libresoc.v:123531.9-123531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -190371,30 +192791,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121827$4601_Y - connect \$12 $not$libresoc.v:121828$4602_Y - connect \$14 $and$libresoc.v:121829$4603_Y - connect \$16 $eq$libresoc.v:121830$4604_Y - connect \$18 $eq$libresoc.v:121831$4605_Y - connect \$20 $or$libresoc.v:121832$4606_Y - connect \$22 $eq$libresoc.v:121833$4607_Y - connect \$24 $eq$libresoc.v:121834$4608_Y - connect \$26 $or$libresoc.v:121835$4609_Y - connect \$28 $eq$libresoc.v:121836$4610_Y - connect \$2 $eq$libresoc.v:121837$4611_Y - connect \$30 $or$libresoc.v:121838$4612_Y - connect \$32 $eq$libresoc.v:121839$4613_Y - connect \$34 $or$libresoc.v:121840$4614_Y - connect \$36 $eq$libresoc.v:121841$4615_Y - connect \$38 $and$libresoc.v:121842$4616_Y - connect \$40 $and$libresoc.v:121843$4617_Y - connect \$42 $eq$libresoc.v:121844$4618_Y - connect \$44 $and$libresoc.v:121845$4619_Y - connect \$46 $not$libresoc.v:121846$4620_Y - connect \$48 $and$libresoc.v:121847$4621_Y - connect \$4 $and$libresoc.v:121848$4622_Y - connect \$6 $and$libresoc.v:121849$4623_Y - connect \$8 $eq$libresoc.v:121850$4624_Y + connect \$10 $and$libresoc.v:123434$4642_Y + connect \$12 $not$libresoc.v:123435$4643_Y + connect \$14 $and$libresoc.v:123436$4644_Y + connect \$16 $eq$libresoc.v:123437$4645_Y + connect \$18 $eq$libresoc.v:123438$4646_Y + connect \$20 $or$libresoc.v:123439$4647_Y + connect \$22 $eq$libresoc.v:123440$4648_Y + connect \$24 $eq$libresoc.v:123441$4649_Y + connect \$26 $or$libresoc.v:123442$4650_Y + connect \$28 $eq$libresoc.v:123443$4651_Y + connect \$2 $eq$libresoc.v:123444$4652_Y + connect \$30 $or$libresoc.v:123445$4653_Y + connect \$32 $eq$libresoc.v:123446$4654_Y + connect \$34 $or$libresoc.v:123447$4655_Y + connect \$36 $eq$libresoc.v:123448$4656_Y + connect \$38 $and$libresoc.v:123449$4657_Y + connect \$40 $and$libresoc.v:123450$4658_Y + connect \$42 $eq$libresoc.v:123451$4659_Y + connect \$44 $and$libresoc.v:123452$4660_Y + connect \$46 $not$libresoc.v:123453$4661_Y + connect \$48 $and$libresoc.v:123454$4662_Y + connect \$4 $and$libresoc.v:123455$4663_Y + connect \$6 $and$libresoc.v:123456$4664_Y + connect \$8 $eq$libresoc.v:123457$4665_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -190417,120 +192837,120 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:121963.1-122546.10" +attribute \src "libresoc.v:123570.1-124153.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:122509.3-122523.6" + attribute \src "libresoc.v:124116.3-124130.6" wire width 14 $0\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122496.3-122508.6" + attribute \src "libresoc.v:124103.3-124115.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122481.3-122495.6" + attribute \src "libresoc.v:124088.3-124102.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:121964.7-121964.20" + attribute \src "libresoc.v:123571.7-123571.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122509.3-122523.6" + attribute \src "libresoc.v:124116.3-124130.6" wire width 14 $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122496.3-122508.6" + attribute \src "libresoc.v:124103.3-124115.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122481.3-122495.6" + attribute \src "libresoc.v:124088.3-124102.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:122397.18-122397.113" - wire $and$libresoc.v:122397$4628_Y - attribute \src "libresoc.v:122399.18-122399.110" - wire $and$libresoc.v:122399$4630_Y - attribute \src "libresoc.v:122412.18-122412.114" - wire $and$libresoc.v:122412$4643_Y - attribute \src "libresoc.v:122413.18-122413.116" - wire $and$libresoc.v:122413$4644_Y - attribute \src "libresoc.v:122415.18-122415.114" - wire $and$libresoc.v:122415$4646_Y - attribute \src "libresoc.v:122417.18-122417.110" - wire $and$libresoc.v:122417$4648_Y - attribute \src "libresoc.v:122418.17-122418.112" - wire $and$libresoc.v:122418$4649_Y - attribute \src "libresoc.v:122419.17-122419.114" - wire $and$libresoc.v:122419$4650_Y - attribute \src "libresoc.v:122400.18-122400.130" - wire $eq$libresoc.v:122400$4631_Y - attribute \src "libresoc.v:122401.18-122401.130" - wire $eq$libresoc.v:122401$4632_Y - attribute \src "libresoc.v:122403.18-122403.110" - wire $eq$libresoc.v:122403$4634_Y - attribute \src "libresoc.v:122404.18-122404.110" - wire $eq$libresoc.v:122404$4635_Y - attribute \src "libresoc.v:122406.18-122406.112" - wire $eq$libresoc.v:122406$4637_Y - attribute \src "libresoc.v:122407.17-122407.134" - wire $eq$libresoc.v:122407$4638_Y - attribute \src "libresoc.v:122409.18-122409.110" - wire $eq$libresoc.v:122409$4640_Y - attribute \src "libresoc.v:122411.18-122411.135" - wire $eq$libresoc.v:122411$4642_Y - attribute \src "libresoc.v:122414.18-122414.135" - wire $eq$libresoc.v:122414$4645_Y - attribute \src "libresoc.v:122420.17-122420.134" - wire $eq$libresoc.v:122420$4651_Y - attribute \src "libresoc.v:122398.18-122398.110" - wire $not$libresoc.v:122398$4629_Y - attribute \src "libresoc.v:122416.18-122416.110" - wire $not$libresoc.v:122416$4647_Y - attribute \src "libresoc.v:122402.18-122402.110" - wire $or$libresoc.v:122402$4633_Y - attribute \src "libresoc.v:122405.18-122405.110" - wire $or$libresoc.v:122405$4636_Y - attribute \src "libresoc.v:122408.18-122408.110" - wire $or$libresoc.v:122408$4639_Y - attribute \src "libresoc.v:122410.18-122410.110" - wire $or$libresoc.v:122410$4641_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:124004.18-124004.113" + wire $and$libresoc.v:124004$4669_Y + attribute \src "libresoc.v:124006.18-124006.110" + wire $and$libresoc.v:124006$4671_Y + attribute \src "libresoc.v:124019.18-124019.114" + wire $and$libresoc.v:124019$4684_Y + attribute \src "libresoc.v:124020.18-124020.116" + wire $and$libresoc.v:124020$4685_Y + attribute \src "libresoc.v:124022.18-124022.114" + wire $and$libresoc.v:124022$4687_Y + attribute \src "libresoc.v:124024.18-124024.110" + wire $and$libresoc.v:124024$4689_Y + attribute \src "libresoc.v:124025.17-124025.112" + wire $and$libresoc.v:124025$4690_Y + attribute \src "libresoc.v:124026.17-124026.114" + wire $and$libresoc.v:124026$4691_Y + attribute \src "libresoc.v:124007.18-124007.130" + wire $eq$libresoc.v:124007$4672_Y + attribute \src "libresoc.v:124008.18-124008.130" + wire $eq$libresoc.v:124008$4673_Y + attribute \src "libresoc.v:124010.18-124010.110" + wire $eq$libresoc.v:124010$4675_Y + attribute \src "libresoc.v:124011.18-124011.110" + wire $eq$libresoc.v:124011$4676_Y + attribute \src "libresoc.v:124013.18-124013.112" + wire $eq$libresoc.v:124013$4678_Y + attribute \src "libresoc.v:124014.17-124014.134" + wire $eq$libresoc.v:124014$4679_Y + attribute \src "libresoc.v:124016.18-124016.110" + wire $eq$libresoc.v:124016$4681_Y + attribute \src "libresoc.v:124018.18-124018.135" + wire $eq$libresoc.v:124018$4683_Y + attribute \src "libresoc.v:124021.18-124021.135" + wire $eq$libresoc.v:124021$4686_Y + attribute \src "libresoc.v:124027.17-124027.134" + wire $eq$libresoc.v:124027$4692_Y + attribute \src "libresoc.v:124005.18-124005.110" + wire $not$libresoc.v:124005$4670_Y + attribute \src "libresoc.v:124023.18-124023.110" + wire $not$libresoc.v:124023$4688_Y + attribute \src "libresoc.v:124009.18-124009.110" + wire $or$libresoc.v:124009$4674_Y + attribute \src "libresoc.v:124012.18-124012.110" + wire $or$libresoc.v:124012$4677_Y + attribute \src "libresoc.v:124015.18-124015.110" + wire $or$libresoc.v:124015$4680_Y + attribute \src "libresoc.v:124017.18-124017.110" + wire $or$libresoc.v:124017$4682_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \LOGICAL__data_len @@ -190662,27 +193082,27 @@ module \dec_LOGICAL wire output 15 \LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -190691,15 +193111,15 @@ module \dec_LOGICAL attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -190716,7 +193136,7 @@ module \dec_LOGICAL attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -190724,7 +193144,7 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -190741,7 +193161,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -190818,13 +193238,13 @@ module \dec_LOGICAL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -190832,19 +193252,19 @@ module \dec_LOGICAL attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -190852,9 +193272,9 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -190875,7 +193295,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -190885,9 +193305,9 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -190897,26 +193317,26 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121964.7-121964.15" + attribute \src "libresoc.v:123571.7-123571.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122397$4628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124004$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190924,10 +193344,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122397$4628_Y + connect \Y $and$libresoc.v:124004$4669_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122399$4630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124006$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190935,10 +193355,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122399$4630_Y + connect \Y $and$libresoc.v:124006$4671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122412$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124019$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190946,10 +193366,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122412$4643_Y + connect \Y $and$libresoc.v:124019$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122413$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124020$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190957,10 +193377,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122413$4644_Y + connect \Y $and$libresoc.v:124020$4685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122415$4646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124022$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190968,10 +193388,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122415$4646_Y + connect \Y $and$libresoc.v:124022$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122417$4648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124024$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190979,10 +193399,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122417$4648_Y + connect \Y $and$libresoc.v:124024$4689_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122418$4649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124025$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190990,10 +193410,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122418$4649_Y + connect \Y $and$libresoc.v:124025$4690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122419$4650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124026$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191001,10 +193421,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122419$4650_Y + connect \Y $and$libresoc.v:124026$4691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:122400$4631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124007$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191012,10 +193432,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122400$4631_Y + connect \Y $eq$libresoc.v:124007$4672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122401$4632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124008$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191023,10 +193443,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122401$4632_Y + connect \Y $eq$libresoc.v:124008$4673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122403$4634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124010$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191034,10 +193454,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122403$4634_Y + connect \Y $eq$libresoc.v:124010$4675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122404$4635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124011$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191045,10 +193465,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122404$4635_Y + connect \Y $eq$libresoc.v:124011$4676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122406$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124013$4678 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191056,10 +193476,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122406$4637_Y + connect \Y $eq$libresoc.v:124013$4678_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122407$4638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124014$4679 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191067,10 +193487,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122407$4638_Y + connect \Y $eq$libresoc.v:124014$4679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122409$4640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124016$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191078,10 +193498,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122409$4640_Y + connect \Y $eq$libresoc.v:124016$4681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122411$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124018$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191089,10 +193509,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122411$4642_Y + connect \Y $eq$libresoc.v:124018$4683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122414$4645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124021$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191100,10 +193520,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122414$4645_Y + connect \Y $eq$libresoc.v:124021$4686_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122420$4651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124027$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191111,26 +193531,26 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122420$4651_Y + connect \Y $eq$libresoc.v:124027$4692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122398$4629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124005$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122398$4629_Y + connect \Y $not$libresoc.v:124005$4670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122416$4647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124023$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122416$4647_Y + connect \Y $not$libresoc.v:124023$4688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:122402$4633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124009$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191138,10 +193558,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122402$4633_Y + connect \Y $or$libresoc.v:124009$4674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122405$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124012$4677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191149,10 +193569,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122405$4636_Y + connect \Y $or$libresoc.v:124012$4677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122408$4639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124015$4680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191160,10 +193580,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122408$4639_Y + connect \Y $or$libresoc.v:124015$4680_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122410$4641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124017$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191171,10 +193591,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122410$4641_Y + connect \Y $or$libresoc.v:124017$4682_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122421.13-122449.4" + attribute \src "libresoc.v:124028.13-124056.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -191205,7 +193625,7 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122450.16-122455.4" + attribute \src "libresoc.v:124057.16-124062.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out @@ -191213,7 +193633,7 @@ module \dec_LOGICAL connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:122456.16-122467.4" + attribute \src "libresoc.v:124063.16-124074.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -191227,7 +193647,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122468.16-122474.4" + attribute \src "libresoc.v:124075.16-124081.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -191236,33 +193656,33 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122475.16-122480.4" + attribute \src "libresoc.v:124082.16-124087.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121964.7-121964.20" - process $proc$libresoc.v:121964$4655 + attribute \src "libresoc.v:123571.7-123571.20" + process $proc$libresoc.v:123571$4696 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122481.3-122495.6" - process $proc$libresoc.v:122481$4652 + attribute \src "libresoc.v:124088.3-124102.6" + process $proc$libresoc.v:124088$4693 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:122482.5-122482.29" + attribute \src "libresoc.v:124089.5-124089.29" switch \initial - attribute \src "libresoc.v:122482.9-122482.17" + attribute \src "libresoc.v:124089.9-124089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -191278,18 +193698,18 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:122496.3-122508.6" - process $proc$libresoc.v:122496$4653 + attribute \src "libresoc.v:124103.3-124115.6" + process $proc$libresoc.v:124103$4694 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:122497.5-122497.29" + attribute \src "libresoc.v:124104.5-124104.29" switch \initial - attribute \src "libresoc.v:122497.9-122497.17" + attribute \src "libresoc.v:124104.9-124104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191305,17 +193725,17 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:122509.3-122523.6" - process $proc$libresoc.v:122509$4654 + attribute \src "libresoc.v:124116.3-124130.6" + process $proc$libresoc.v:124116$4695 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:122510.5-122510.29" + attribute \src "libresoc.v:124117.5-124117.29" switch \initial - attribute \src "libresoc.v:122510.9-122510.17" + attribute \src "libresoc.v:124117.9-124117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -191333,30 +193753,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122397$4628_Y - connect \$12 $not$libresoc.v:122398$4629_Y - connect \$14 $and$libresoc.v:122399$4630_Y - connect \$16 $eq$libresoc.v:122400$4631_Y - connect \$18 $eq$libresoc.v:122401$4632_Y - connect \$20 $or$libresoc.v:122402$4633_Y - connect \$22 $eq$libresoc.v:122403$4634_Y - connect \$24 $eq$libresoc.v:122404$4635_Y - connect \$26 $or$libresoc.v:122405$4636_Y - connect \$28 $eq$libresoc.v:122406$4637_Y - connect \$2 $eq$libresoc.v:122407$4638_Y - connect \$30 $or$libresoc.v:122408$4639_Y - connect \$32 $eq$libresoc.v:122409$4640_Y - connect \$34 $or$libresoc.v:122410$4641_Y - connect \$36 $eq$libresoc.v:122411$4642_Y - connect \$38 $and$libresoc.v:122412$4643_Y - connect \$40 $and$libresoc.v:122413$4644_Y - connect \$42 $eq$libresoc.v:122414$4645_Y - connect \$44 $and$libresoc.v:122415$4646_Y - connect \$46 $not$libresoc.v:122416$4647_Y - connect \$48 $and$libresoc.v:122417$4648_Y - connect \$4 $and$libresoc.v:122418$4649_Y - connect \$6 $and$libresoc.v:122419$4650_Y - connect \$8 $eq$libresoc.v:122420$4651_Y + connect \$10 $and$libresoc.v:124004$4669_Y + connect \$12 $not$libresoc.v:124005$4670_Y + connect \$14 $and$libresoc.v:124006$4671_Y + connect \$16 $eq$libresoc.v:124007$4672_Y + connect \$18 $eq$libresoc.v:124008$4673_Y + connect \$20 $or$libresoc.v:124009$4674_Y + connect \$22 $eq$libresoc.v:124010$4675_Y + connect \$24 $eq$libresoc.v:124011$4676_Y + connect \$26 $or$libresoc.v:124012$4677_Y + connect \$28 $eq$libresoc.v:124013$4678_Y + connect \$2 $eq$libresoc.v:124014$4679_Y + connect \$30 $or$libresoc.v:124015$4680_Y + connect \$32 $eq$libresoc.v:124016$4681_Y + connect \$34 $or$libresoc.v:124017$4682_Y + connect \$36 $eq$libresoc.v:124018$4683_Y + connect \$38 $and$libresoc.v:124019$4684_Y + connect \$40 $and$libresoc.v:124020$4685_Y + connect \$42 $eq$libresoc.v:124021$4686_Y + connect \$44 $and$libresoc.v:124022$4687_Y + connect \$46 $not$libresoc.v:124023$4688_Y + connect \$48 $and$libresoc.v:124024$4689_Y + connect \$4 $and$libresoc.v:124025$4690_Y + connect \$6 $and$libresoc.v:124026$4691_Y + connect \$8 $eq$libresoc.v:124027$4692_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -191380,120 +193800,120 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:122550.1-123052.10" +attribute \src "libresoc.v:124157.1-124659.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:123023.3-123037.6" + attribute \src "libresoc.v:124630.3-124644.6" wire width 14 $0\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123010.3-123022.6" + attribute \src "libresoc.v:124617.3-124629.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:122995.3-123009.6" + attribute \src "libresoc.v:124602.3-124616.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122551.7-122551.20" + attribute \src "libresoc.v:124158.7-124158.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123023.3-123037.6" + attribute \src "libresoc.v:124630.3-124644.6" wire width 14 $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123010.3-123022.6" + attribute \src "libresoc.v:124617.3-124629.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:122995.3-123009.6" + attribute \src "libresoc.v:124602.3-124616.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122924.18-122924.113" - wire $and$libresoc.v:122924$4656_Y - attribute \src "libresoc.v:122926.18-122926.110" - wire $and$libresoc.v:122926$4658_Y - attribute \src "libresoc.v:122939.18-122939.114" - wire $and$libresoc.v:122939$4671_Y - attribute \src "libresoc.v:122940.18-122940.116" - wire $and$libresoc.v:122940$4672_Y - attribute \src "libresoc.v:122942.18-122942.114" - wire $and$libresoc.v:122942$4674_Y - attribute \src "libresoc.v:122944.18-122944.110" - wire $and$libresoc.v:122944$4676_Y - attribute \src "libresoc.v:122945.17-122945.112" - wire $and$libresoc.v:122945$4677_Y - attribute \src "libresoc.v:122946.17-122946.114" - wire $and$libresoc.v:122946$4678_Y - attribute \src "libresoc.v:122927.18-122927.126" - wire $eq$libresoc.v:122927$4659_Y - attribute \src "libresoc.v:122928.18-122928.126" - wire $eq$libresoc.v:122928$4660_Y - attribute \src "libresoc.v:122930.18-122930.110" - wire $eq$libresoc.v:122930$4662_Y - attribute \src "libresoc.v:122931.18-122931.110" - wire $eq$libresoc.v:122931$4663_Y - attribute \src "libresoc.v:122933.18-122933.112" - wire $eq$libresoc.v:122933$4665_Y - attribute \src "libresoc.v:122934.17-122934.130" - wire $eq$libresoc.v:122934$4666_Y - attribute \src "libresoc.v:122936.18-122936.110" - wire $eq$libresoc.v:122936$4668_Y - attribute \src "libresoc.v:122938.18-122938.131" - wire $eq$libresoc.v:122938$4670_Y - attribute \src "libresoc.v:122941.18-122941.131" - wire $eq$libresoc.v:122941$4673_Y - attribute \src "libresoc.v:122947.17-122947.130" - wire $eq$libresoc.v:122947$4679_Y - attribute \src "libresoc.v:122925.18-122925.110" - wire $not$libresoc.v:122925$4657_Y - attribute \src "libresoc.v:122943.18-122943.110" - wire $not$libresoc.v:122943$4675_Y - attribute \src "libresoc.v:122929.18-122929.110" - wire $or$libresoc.v:122929$4661_Y - attribute \src "libresoc.v:122932.18-122932.110" - wire $or$libresoc.v:122932$4664_Y - attribute \src "libresoc.v:122935.18-122935.110" - wire $or$libresoc.v:122935$4667_Y - attribute \src "libresoc.v:122937.18-122937.110" - wire $or$libresoc.v:122937$4669_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:124531.18-124531.113" + wire $and$libresoc.v:124531$4697_Y + attribute \src "libresoc.v:124533.18-124533.110" + wire $and$libresoc.v:124533$4699_Y + attribute \src "libresoc.v:124546.18-124546.114" + wire $and$libresoc.v:124546$4712_Y + attribute \src "libresoc.v:124547.18-124547.116" + wire $and$libresoc.v:124547$4713_Y + attribute \src "libresoc.v:124549.18-124549.114" + wire $and$libresoc.v:124549$4715_Y + attribute \src "libresoc.v:124551.18-124551.110" + wire $and$libresoc.v:124551$4717_Y + attribute \src "libresoc.v:124552.17-124552.112" + wire $and$libresoc.v:124552$4718_Y + attribute \src "libresoc.v:124553.17-124553.114" + wire $and$libresoc.v:124553$4719_Y + attribute \src "libresoc.v:124534.18-124534.126" + wire $eq$libresoc.v:124534$4700_Y + attribute \src "libresoc.v:124535.18-124535.126" + wire $eq$libresoc.v:124535$4701_Y + attribute \src "libresoc.v:124537.18-124537.110" + wire $eq$libresoc.v:124537$4703_Y + attribute \src "libresoc.v:124538.18-124538.110" + wire $eq$libresoc.v:124538$4704_Y + attribute \src "libresoc.v:124540.18-124540.112" + wire $eq$libresoc.v:124540$4706_Y + attribute \src "libresoc.v:124541.17-124541.130" + wire $eq$libresoc.v:124541$4707_Y + attribute \src "libresoc.v:124543.18-124543.110" + wire $eq$libresoc.v:124543$4709_Y + attribute \src "libresoc.v:124545.18-124545.131" + wire $eq$libresoc.v:124545$4711_Y + attribute \src "libresoc.v:124548.18-124548.131" + wire $eq$libresoc.v:124548$4714_Y + attribute \src "libresoc.v:124554.17-124554.130" + wire $eq$libresoc.v:124554$4720_Y + attribute \src "libresoc.v:124532.18-124532.110" + wire $not$libresoc.v:124532$4698_Y + attribute \src "libresoc.v:124550.18-124550.110" + wire $not$libresoc.v:124550$4716_Y + attribute \src "libresoc.v:124536.18-124536.110" + wire $or$libresoc.v:124536$4702_Y + attribute \src "libresoc.v:124539.18-124539.110" + wire $or$libresoc.v:124539$4705_Y + attribute \src "libresoc.v:124542.18-124542.110" + wire $or$libresoc.v:124542$4708_Y + attribute \src "libresoc.v:124544.18-124544.110" + wire $or$libresoc.v:124544$4710_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -191609,25 +194029,25 @@ module \dec_MUL wire output 6 \MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -191636,7 +194056,7 @@ module \dec_MUL attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -191653,7 +194073,7 @@ module \dec_MUL attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -191670,7 +194090,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -191747,19 +194167,19 @@ module \dec_MUL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -191780,7 +194200,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -191790,9 +194210,9 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -191802,24 +194222,24 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122551.7-122551.15" + attribute \src "libresoc.v:124158.7-124158.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 14 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122924$4656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124531$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191827,10 +194247,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122924$4656_Y + connect \Y $and$libresoc.v:124531$4697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122926$4658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124533$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191838,10 +194258,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122926$4658_Y + connect \Y $and$libresoc.v:124533$4699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122939$4671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124546$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191849,10 +194269,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122939$4671_Y + connect \Y $and$libresoc.v:124546$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122940$4672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124547$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191860,10 +194280,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122940$4672_Y + connect \Y $and$libresoc.v:124547$4713_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122942$4674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124549$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191871,10 +194291,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122942$4674_Y + connect \Y $and$libresoc.v:124549$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:122944$4676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:124551$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191882,10 +194302,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122944$4676_Y + connect \Y $and$libresoc.v:124551$4717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122945$4677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124552$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191893,10 +194313,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122945$4677_Y + connect \Y $and$libresoc.v:124552$4718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:122946$4678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:124553$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191904,10 +194324,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122946$4678_Y + connect \Y $and$libresoc.v:124553$4719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:122927$4659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:124534$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191915,10 +194335,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122927$4659_Y + connect \Y $eq$libresoc.v:124534$4700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122928$4660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:124535$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191926,10 +194346,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122928$4660_Y + connect \Y $eq$libresoc.v:124535$4701_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122930$4662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124537$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191937,10 +194357,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122930$4662_Y + connect \Y $eq$libresoc.v:124537$4703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122931$4663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124538$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191948,10 +194368,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122931$4663_Y + connect \Y $eq$libresoc.v:124538$4704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:122933$4665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:124540$4706 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191959,10 +194379,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122933$4665_Y + connect \Y $eq$libresoc.v:124540$4706_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122934$4666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124541$4707 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191970,10 +194390,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122934$4666_Y + connect \Y $eq$libresoc.v:124541$4707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122936$4668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:124543$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191981,10 +194401,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122936$4668_Y + connect \Y $eq$libresoc.v:124543$4709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:122938$4670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:124545$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191992,10 +194412,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122938$4670_Y + connect \Y $eq$libresoc.v:124545$4711_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122941$4673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124548$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192003,10 +194423,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122941$4673_Y + connect \Y $eq$libresoc.v:124548$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:122947$4679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:124554$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192014,26 +194434,26 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122947$4679_Y + connect \Y $eq$libresoc.v:124554$4720_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122925$4657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124532$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122925$4657_Y + connect \Y $not$libresoc.v:124532$4698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:122943$4675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:124550$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122943$4675_Y + connect \Y $not$libresoc.v:124550$4716_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:122929$4661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:124536$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192041,10 +194461,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122929$4661_Y + connect \Y $or$libresoc.v:124536$4702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122932$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124539$4705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192052,10 +194472,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122932$4664_Y + connect \Y $or$libresoc.v:124539$4705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:122935$4667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:124542$4708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192063,10 +194483,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122935$4667_Y + connect \Y $or$libresoc.v:124542$4708_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122937$4669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:124544$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192074,10 +194494,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122937$4669_Y + connect \Y $or$libresoc.v:124544$4710_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122948.13-122969.4" + attribute \src "libresoc.v:124555.13-124576.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -192101,7 +194521,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122970.16-122981.4" + attribute \src "libresoc.v:124577.16-124588.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -192115,7 +194535,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122982.16-122988.4" + attribute \src "libresoc.v:124589.16-124595.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -192124,33 +194544,33 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122989.16-122994.4" + attribute \src "libresoc.v:124596.16-124601.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122551.7-122551.20" - process $proc$libresoc.v:122551$4683 + attribute \src "libresoc.v:124158.7-124158.20" + process $proc$libresoc.v:124158$4724 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122995.3-123009.6" - process $proc$libresoc.v:122995$4680 + attribute \src "libresoc.v:124602.3-124616.6" + process $proc$libresoc.v:124602$4721 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:122996.5-122996.29" + attribute \src "libresoc.v:124603.5-124603.29" switch \initial - attribute \src "libresoc.v:122996.9-122996.17" + attribute \src "libresoc.v:124603.9-124603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -192166,18 +194586,18 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:123010.3-123022.6" - process $proc$libresoc.v:123010$4681 + attribute \src "libresoc.v:124617.3-124629.6" + process $proc$libresoc.v:124617$4722 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:123011.5-123011.29" + attribute \src "libresoc.v:124618.5-124618.29" switch \initial - attribute \src "libresoc.v:123011.9-123011.17" + attribute \src "libresoc.v:124618.9-124618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192193,17 +194613,17 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:123023.3-123037.6" - process $proc$libresoc.v:123023$4682 + attribute \src "libresoc.v:124630.3-124644.6" + process $proc$libresoc.v:124630$4723 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:123024.5-123024.29" + attribute \src "libresoc.v:124631.5-124631.29" switch \initial - attribute \src "libresoc.v:123024.9-123024.17" + attribute \src "libresoc.v:124631.9-124631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192221,30 +194641,30 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122924$4656_Y - connect \$12 $not$libresoc.v:122925$4657_Y - connect \$14 $and$libresoc.v:122926$4658_Y - connect \$16 $eq$libresoc.v:122927$4659_Y - connect \$18 $eq$libresoc.v:122928$4660_Y - connect \$20 $or$libresoc.v:122929$4661_Y - connect \$22 $eq$libresoc.v:122930$4662_Y - connect \$24 $eq$libresoc.v:122931$4663_Y - connect \$26 $or$libresoc.v:122932$4664_Y - connect \$28 $eq$libresoc.v:122933$4665_Y - connect \$2 $eq$libresoc.v:122934$4666_Y - connect \$30 $or$libresoc.v:122935$4667_Y - connect \$32 $eq$libresoc.v:122936$4668_Y - connect \$34 $or$libresoc.v:122937$4669_Y - connect \$36 $eq$libresoc.v:122938$4670_Y - connect \$38 $and$libresoc.v:122939$4671_Y - connect \$40 $and$libresoc.v:122940$4672_Y - connect \$42 $eq$libresoc.v:122941$4673_Y - connect \$44 $and$libresoc.v:122942$4674_Y - connect \$46 $not$libresoc.v:122943$4675_Y - connect \$48 $and$libresoc.v:122944$4676_Y - connect \$4 $and$libresoc.v:122945$4677_Y - connect \$6 $and$libresoc.v:122946$4678_Y - connect \$8 $eq$libresoc.v:122947$4679_Y + connect \$10 $and$libresoc.v:124531$4697_Y + connect \$12 $not$libresoc.v:124532$4698_Y + connect \$14 $and$libresoc.v:124533$4699_Y + connect \$16 $eq$libresoc.v:124534$4700_Y + connect \$18 $eq$libresoc.v:124535$4701_Y + connect \$20 $or$libresoc.v:124536$4702_Y + connect \$22 $eq$libresoc.v:124537$4703_Y + connect \$24 $eq$libresoc.v:124538$4704_Y + connect \$26 $or$libresoc.v:124539$4705_Y + connect \$28 $eq$libresoc.v:124540$4706_Y + connect \$2 $eq$libresoc.v:124541$4707_Y + connect \$30 $or$libresoc.v:124542$4708_Y + connect \$32 $eq$libresoc.v:124543$4709_Y + connect \$34 $or$libresoc.v:124544$4710_Y + connect \$36 $eq$libresoc.v:124545$4711_Y + connect \$38 $and$libresoc.v:124546$4712_Y + connect \$40 $and$libresoc.v:124547$4713_Y + connect \$42 $eq$libresoc.v:124548$4714_Y + connect \$44 $and$libresoc.v:124549$4715_Y + connect \$46 $not$libresoc.v:124550$4716_Y + connect \$48 $and$libresoc.v:124551$4717_Y + connect \$4 $and$libresoc.v:124552$4718_Y + connect \$6 $and$libresoc.v:124553$4719_Y + connect \$8 $eq$libresoc.v:124554$4720_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -192260,120 +194680,120 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:123056.1-123602.10" +attribute \src "libresoc.v:124663.1-125209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:123568.3-123582.6" + attribute \src "libresoc.v:125175.3-125189.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123555.3-123567.6" + attribute \src "libresoc.v:125162.3-125174.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123540.3-123554.6" + attribute \src "libresoc.v:125147.3-125161.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123057.7-123057.20" + attribute \src "libresoc.v:124664.7-124664.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123568.3-123582.6" + attribute \src "libresoc.v:125175.3-125189.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123555.3-123567.6" + attribute \src "libresoc.v:125162.3-125174.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123540.3-123554.6" + attribute \src "libresoc.v:125147.3-125161.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123465.18-123465.113" - wire $and$libresoc.v:123465$4684_Y - attribute \src "libresoc.v:123467.18-123467.110" - wire $and$libresoc.v:123467$4686_Y - attribute \src "libresoc.v:123480.18-123480.114" - wire $and$libresoc.v:123480$4699_Y - attribute \src "libresoc.v:123481.18-123481.116" - wire $and$libresoc.v:123481$4700_Y - attribute \src "libresoc.v:123483.18-123483.114" - wire $and$libresoc.v:123483$4702_Y - attribute \src "libresoc.v:123485.18-123485.110" - wire $and$libresoc.v:123485$4704_Y - attribute \src "libresoc.v:123486.17-123486.112" - wire $and$libresoc.v:123486$4705_Y - attribute \src "libresoc.v:123487.17-123487.114" - wire $and$libresoc.v:123487$4706_Y - attribute \src "libresoc.v:123468.18-123468.132" - wire $eq$libresoc.v:123468$4687_Y - attribute \src "libresoc.v:123469.18-123469.132" - wire $eq$libresoc.v:123469$4688_Y - attribute \src "libresoc.v:123471.18-123471.110" - wire $eq$libresoc.v:123471$4690_Y - attribute \src "libresoc.v:123472.18-123472.110" - wire $eq$libresoc.v:123472$4691_Y - attribute \src "libresoc.v:123474.18-123474.112" - wire $eq$libresoc.v:123474$4693_Y - attribute \src "libresoc.v:123475.17-123475.136" - wire $eq$libresoc.v:123475$4694_Y - attribute \src "libresoc.v:123477.18-123477.110" - wire $eq$libresoc.v:123477$4696_Y - attribute \src "libresoc.v:123479.18-123479.137" - wire $eq$libresoc.v:123479$4698_Y - attribute \src "libresoc.v:123482.18-123482.137" - wire $eq$libresoc.v:123482$4701_Y - attribute \src "libresoc.v:123488.17-123488.136" - wire $eq$libresoc.v:123488$4707_Y - attribute \src "libresoc.v:123466.18-123466.110" - wire $not$libresoc.v:123466$4685_Y - attribute \src "libresoc.v:123484.18-123484.110" - wire $not$libresoc.v:123484$4703_Y - attribute \src "libresoc.v:123470.18-123470.110" - wire $or$libresoc.v:123470$4689_Y - attribute \src "libresoc.v:123473.18-123473.110" - wire $or$libresoc.v:123473$4692_Y - attribute \src "libresoc.v:123476.18-123476.110" - wire $or$libresoc.v:123476$4695_Y - attribute \src "libresoc.v:123478.18-123478.110" - wire $or$libresoc.v:123478$4697_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:125072.18-125072.113" + wire $and$libresoc.v:125072$4725_Y + attribute \src "libresoc.v:125074.18-125074.110" + wire $and$libresoc.v:125074$4727_Y + attribute \src "libresoc.v:125087.18-125087.114" + wire $and$libresoc.v:125087$4740_Y + attribute \src "libresoc.v:125088.18-125088.116" + wire $and$libresoc.v:125088$4741_Y + attribute \src "libresoc.v:125090.18-125090.114" + wire $and$libresoc.v:125090$4743_Y + attribute \src "libresoc.v:125092.18-125092.110" + wire $and$libresoc.v:125092$4745_Y + attribute \src "libresoc.v:125093.17-125093.112" + wire $and$libresoc.v:125093$4746_Y + attribute \src "libresoc.v:125094.17-125094.114" + wire $and$libresoc.v:125094$4747_Y + attribute \src "libresoc.v:125075.18-125075.132" + wire $eq$libresoc.v:125075$4728_Y + attribute \src "libresoc.v:125076.18-125076.132" + wire $eq$libresoc.v:125076$4729_Y + attribute \src "libresoc.v:125078.18-125078.110" + wire $eq$libresoc.v:125078$4731_Y + attribute \src "libresoc.v:125079.18-125079.110" + wire $eq$libresoc.v:125079$4732_Y + attribute \src "libresoc.v:125081.18-125081.112" + wire $eq$libresoc.v:125081$4734_Y + attribute \src "libresoc.v:125082.17-125082.136" + wire $eq$libresoc.v:125082$4735_Y + attribute \src "libresoc.v:125084.18-125084.110" + wire $eq$libresoc.v:125084$4737_Y + attribute \src "libresoc.v:125086.18-125086.137" + wire $eq$libresoc.v:125086$4739_Y + attribute \src "libresoc.v:125089.18-125089.137" + wire $eq$libresoc.v:125089$4742_Y + attribute \src "libresoc.v:125095.17-125095.136" + wire $eq$libresoc.v:125095$4748_Y + attribute \src "libresoc.v:125073.18-125073.110" + wire $not$libresoc.v:125073$4726_Y + attribute \src "libresoc.v:125091.18-125091.110" + wire $not$libresoc.v:125091$4744_Y + attribute \src "libresoc.v:125077.18-125077.110" + wire $or$libresoc.v:125077$4730_Y + attribute \src "libresoc.v:125080.18-125080.110" + wire $or$libresoc.v:125080$4733_Y + attribute \src "libresoc.v:125083.18-125083.110" + wire $or$libresoc.v:125083$4736_Y + attribute \src "libresoc.v:125085.18-125085.110" + wire $or$libresoc.v:125085$4738_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -192503,25 +194923,25 @@ module \dec_SHIFT_ROT wire output 6 \SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -192532,7 +194952,7 @@ module \dec_SHIFT_ROT attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -192541,15 +194961,15 @@ module \dec_SHIFT_ROT attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -192566,7 +194986,7 @@ module \dec_SHIFT_ROT attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -192583,7 +195003,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -192660,21 +195080,21 @@ module \dec_SHIFT_ROT attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_SHIFT_ROT_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -192695,7 +195115,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe @@ -192705,9 +195125,9 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc @@ -192717,24 +195137,24 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123057.7-123057.15" + attribute \src "libresoc.v:124664.7-124664.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123465$4684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125072$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192742,10 +195162,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123465$4684_Y + connect \Y $and$libresoc.v:125072$4725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123467$4686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125074$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192753,10 +195173,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123467$4686_Y + connect \Y $and$libresoc.v:125074$4727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123480$4699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125087$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192764,10 +195184,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123480$4699_Y + connect \Y $and$libresoc.v:125087$4740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123481$4700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125088$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192775,10 +195195,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123481$4700_Y + connect \Y $and$libresoc.v:125088$4741_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123483$4702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125090$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192786,10 +195206,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123483$4702_Y + connect \Y $and$libresoc.v:125090$4743_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123485$4704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125092$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192797,10 +195217,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123485$4704_Y + connect \Y $and$libresoc.v:125092$4745_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123486$4705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125093$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192808,10 +195228,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123486$4705_Y + connect \Y $and$libresoc.v:125093$4746_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123487$4706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125094$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192819,10 +195239,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123487$4706_Y + connect \Y $and$libresoc.v:125094$4747_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:123468$4687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:125075$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192830,10 +195250,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123468$4687_Y + connect \Y $eq$libresoc.v:125075$4728_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123469$4688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:125076$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192841,10 +195261,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123469$4688_Y + connect \Y $eq$libresoc.v:125076$4729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123471$4690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125078$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192852,10 +195272,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123471$4690_Y + connect \Y $eq$libresoc.v:125078$4731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123472$4691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125079$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192863,10 +195283,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123472$4691_Y + connect \Y $eq$libresoc.v:125079$4732_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123474$4693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125081$4734 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192874,10 +195294,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123474$4693_Y + connect \Y $eq$libresoc.v:125081$4734_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123475$4694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125082$4735 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192885,10 +195305,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123475$4694_Y + connect \Y $eq$libresoc.v:125082$4735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123477$4696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:125084$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192896,10 +195316,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123477$4696_Y + connect \Y $eq$libresoc.v:125084$4737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123479$4698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125086$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192907,10 +195327,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123479$4698_Y + connect \Y $eq$libresoc.v:125086$4739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123482$4701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125089$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192918,10 +195338,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123482$4701_Y + connect \Y $eq$libresoc.v:125089$4742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123488$4707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125095$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192929,26 +195349,26 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123488$4707_Y + connect \Y $eq$libresoc.v:125095$4748_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123466$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125073$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123466$4685_Y + connect \Y $not$libresoc.v:125073$4726_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123484$4703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125091$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123484$4703_Y + connect \Y $not$libresoc.v:125091$4744_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:123470$4689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:125077$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192956,10 +195376,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123470$4689_Y + connect \Y $or$libresoc.v:125077$4730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123473$4692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125080$4733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192967,10 +195387,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123473$4692_Y + connect \Y $or$libresoc.v:125080$4733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123476$4695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125083$4736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192978,10 +195398,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123476$4695_Y + connect \Y $or$libresoc.v:125083$4736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123478$4697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125085$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192989,10 +195409,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123478$4697_Y + connect \Y $or$libresoc.v:125085$4738_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123489.13-123514.4" + attribute \src "libresoc.v:125096.13-125121.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -193020,7 +195440,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123515.16-123526.4" + attribute \src "libresoc.v:125122.16-125133.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -193034,7 +195454,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123527.16-123533.4" + attribute \src "libresoc.v:125134.16-125140.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -193043,33 +195463,33 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123534.16-123539.4" + attribute \src "libresoc.v:125141.16-125146.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123057.7-123057.20" - process $proc$libresoc.v:123057$4711 + attribute \src "libresoc.v:124664.7-124664.20" + process $proc$libresoc.v:124664$4752 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123540.3-123554.6" - process $proc$libresoc.v:123540$4708 + attribute \src "libresoc.v:125147.3-125161.6" + process $proc$libresoc.v:125147$4749 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:123541.5-123541.29" + attribute \src "libresoc.v:125148.5-125148.29" switch \initial - attribute \src "libresoc.v:123541.9-123541.17" + attribute \src "libresoc.v:125148.9-125148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851" switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 @@ -193085,18 +195505,18 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:123555.3-123567.6" - process $proc$libresoc.v:123555$4709 + attribute \src "libresoc.v:125162.3-125174.6" + process $proc$libresoc.v:125162$4750 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:123556.5-123556.29" + attribute \src "libresoc.v:125163.5-125163.29" switch \initial - attribute \src "libresoc.v:123556.9-123556.17" + attribute \src "libresoc.v:125163.9-125163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193112,17 +195532,17 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:123568.3-123582.6" - process $proc$libresoc.v:123568$4710 + attribute \src "libresoc.v:125175.3-125189.6" + process $proc$libresoc.v:125175$4751 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:123569.5-123569.29" + attribute \src "libresoc.v:125176.5-125176.29" switch \initial - attribute \src "libresoc.v:123569.9-123569.17" + attribute \src "libresoc.v:125176.9-125176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193140,30 +195560,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123465$4684_Y - connect \$12 $not$libresoc.v:123466$4685_Y - connect \$14 $and$libresoc.v:123467$4686_Y - connect \$16 $eq$libresoc.v:123468$4687_Y - connect \$18 $eq$libresoc.v:123469$4688_Y - connect \$20 $or$libresoc.v:123470$4689_Y - connect \$22 $eq$libresoc.v:123471$4690_Y - connect \$24 $eq$libresoc.v:123472$4691_Y - connect \$26 $or$libresoc.v:123473$4692_Y - connect \$28 $eq$libresoc.v:123474$4693_Y - connect \$2 $eq$libresoc.v:123475$4694_Y - connect \$30 $or$libresoc.v:123476$4695_Y - connect \$32 $eq$libresoc.v:123477$4696_Y - connect \$34 $or$libresoc.v:123478$4697_Y - connect \$36 $eq$libresoc.v:123479$4698_Y - connect \$38 $and$libresoc.v:123480$4699_Y - connect \$40 $and$libresoc.v:123481$4700_Y - connect \$42 $eq$libresoc.v:123482$4701_Y - connect \$44 $and$libresoc.v:123483$4702_Y - connect \$46 $not$libresoc.v:123484$4703_Y - connect \$48 $and$libresoc.v:123485$4704_Y - connect \$4 $and$libresoc.v:123486$4705_Y - connect \$6 $and$libresoc.v:123487$4706_Y - connect \$8 $eq$libresoc.v:123488$4707_Y + connect \$10 $and$libresoc.v:125072$4725_Y + connect \$12 $not$libresoc.v:125073$4726_Y + connect \$14 $and$libresoc.v:125074$4727_Y + connect \$16 $eq$libresoc.v:125075$4728_Y + connect \$18 $eq$libresoc.v:125076$4729_Y + connect \$20 $or$libresoc.v:125077$4730_Y + connect \$22 $eq$libresoc.v:125078$4731_Y + connect \$24 $eq$libresoc.v:125079$4732_Y + connect \$26 $or$libresoc.v:125080$4733_Y + connect \$28 $eq$libresoc.v:125081$4734_Y + connect \$2 $eq$libresoc.v:125082$4735_Y + connect \$30 $or$libresoc.v:125083$4736_Y + connect \$32 $eq$libresoc.v:125084$4737_Y + connect \$34 $or$libresoc.v:125085$4738_Y + connect \$36 $eq$libresoc.v:125086$4739_Y + connect \$38 $and$libresoc.v:125087$4740_Y + connect \$40 $and$libresoc.v:125088$4741_Y + connect \$42 $eq$libresoc.v:125089$4742_Y + connect \$44 $and$libresoc.v:125090$4743_Y + connect \$46 $not$libresoc.v:125091$4744_Y + connect \$48 $and$libresoc.v:125092$4745_Y + connect \$4 $and$libresoc.v:125093$4746_Y + connect \$6 $and$libresoc.v:125094$4747_Y + connect \$8 $eq$libresoc.v:125095$4748_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -193184,116 +195604,116 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:123606.1-123984.10" +attribute \src "libresoc.v:125213.1-125591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:123960.3-123974.6" + attribute \src "libresoc.v:125567.3-125581.6" wire width 14 $0\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123947.3-123959.6" + attribute \src "libresoc.v:125554.3-125566.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:123607.7-123607.20" + attribute \src "libresoc.v:125214.7-125214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123960.3-123974.6" + attribute \src "libresoc.v:125567.3-125581.6" wire width 14 $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123947.3-123959.6" + attribute \src "libresoc.v:125554.3-125566.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:123901.18-123901.113" - wire $and$libresoc.v:123901$4712_Y - attribute \src "libresoc.v:123903.18-123903.110" - wire $and$libresoc.v:123903$4714_Y - attribute \src "libresoc.v:123916.18-123916.114" - wire $and$libresoc.v:123916$4727_Y - attribute \src "libresoc.v:123917.18-123917.116" - wire $and$libresoc.v:123917$4728_Y - attribute \src "libresoc.v:123919.18-123919.114" - wire $and$libresoc.v:123919$4730_Y - attribute \src "libresoc.v:123921.18-123921.110" - wire $and$libresoc.v:123921$4732_Y - attribute \src "libresoc.v:123922.17-123922.112" - wire $and$libresoc.v:123922$4733_Y - attribute \src "libresoc.v:123923.17-123923.114" - wire $and$libresoc.v:123923$4734_Y - attribute \src "libresoc.v:123904.18-123904.126" - wire $eq$libresoc.v:123904$4715_Y - attribute \src "libresoc.v:123905.18-123905.126" - wire $eq$libresoc.v:123905$4716_Y - attribute \src "libresoc.v:123907.18-123907.110" - wire $eq$libresoc.v:123907$4718_Y - attribute \src "libresoc.v:123908.18-123908.110" - wire $eq$libresoc.v:123908$4719_Y - attribute \src "libresoc.v:123910.18-123910.112" - wire $eq$libresoc.v:123910$4721_Y - attribute \src "libresoc.v:123911.17-123911.130" - wire $eq$libresoc.v:123911$4722_Y - attribute \src "libresoc.v:123913.18-123913.110" - wire $eq$libresoc.v:123913$4724_Y - attribute \src "libresoc.v:123915.18-123915.131" - wire $eq$libresoc.v:123915$4726_Y - attribute \src "libresoc.v:123918.18-123918.131" - wire $eq$libresoc.v:123918$4729_Y - attribute \src "libresoc.v:123924.17-123924.130" - wire $eq$libresoc.v:123924$4735_Y - attribute \src "libresoc.v:123902.18-123902.110" - wire $not$libresoc.v:123902$4713_Y - attribute \src "libresoc.v:123920.18-123920.110" - wire $not$libresoc.v:123920$4731_Y - attribute \src "libresoc.v:123906.18-123906.110" - wire $or$libresoc.v:123906$4717_Y - attribute \src "libresoc.v:123909.18-123909.110" - wire $or$libresoc.v:123909$4720_Y - attribute \src "libresoc.v:123912.18-123912.110" - wire $or$libresoc.v:123912$4723_Y - attribute \src "libresoc.v:123914.18-123914.110" - wire $or$libresoc.v:123914$4725_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "libresoc.v:125508.18-125508.113" + wire $and$libresoc.v:125508$4753_Y + attribute \src "libresoc.v:125510.18-125510.110" + wire $and$libresoc.v:125510$4755_Y + attribute \src "libresoc.v:125523.18-125523.114" + wire $and$libresoc.v:125523$4768_Y + attribute \src "libresoc.v:125524.18-125524.116" + wire $and$libresoc.v:125524$4769_Y + attribute \src "libresoc.v:125526.18-125526.114" + wire $and$libresoc.v:125526$4771_Y + attribute \src "libresoc.v:125528.18-125528.110" + wire $and$libresoc.v:125528$4773_Y + attribute \src "libresoc.v:125529.17-125529.112" + wire $and$libresoc.v:125529$4774_Y + attribute \src "libresoc.v:125530.17-125530.114" + wire $and$libresoc.v:125530$4775_Y + attribute \src "libresoc.v:125511.18-125511.126" + wire $eq$libresoc.v:125511$4756_Y + attribute \src "libresoc.v:125512.18-125512.126" + wire $eq$libresoc.v:125512$4757_Y + attribute \src "libresoc.v:125514.18-125514.110" + wire $eq$libresoc.v:125514$4759_Y + attribute \src "libresoc.v:125515.18-125515.110" + wire $eq$libresoc.v:125515$4760_Y + attribute \src "libresoc.v:125517.18-125517.112" + wire $eq$libresoc.v:125517$4762_Y + attribute \src "libresoc.v:125518.17-125518.130" + wire $eq$libresoc.v:125518$4763_Y + attribute \src "libresoc.v:125520.18-125520.110" + wire $eq$libresoc.v:125520$4765_Y + attribute \src "libresoc.v:125522.18-125522.131" + wire $eq$libresoc.v:125522$4767_Y + attribute \src "libresoc.v:125525.18-125525.131" + wire $eq$libresoc.v:125525$4770_Y + attribute \src "libresoc.v:125531.17-125531.130" + wire $eq$libresoc.v:125531$4776_Y + attribute \src "libresoc.v:125509.18-125509.110" + wire $not$libresoc.v:125509$4754_Y + attribute \src "libresoc.v:125527.18-125527.110" + wire $not$libresoc.v:125527$4772_Y + attribute \src "libresoc.v:125513.18-125513.110" + wire $or$libresoc.v:125513$4758_Y + attribute \src "libresoc.v:125516.18-125516.110" + wire $or$libresoc.v:125516$4761_Y + attribute \src "libresoc.v:125519.18-125519.110" + wire $or$libresoc.v:125519$4764_Y + attribute \src "libresoc.v:125521.18-125521.110" + wire $or$libresoc.v:125521$4766_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -193393,13 +195813,13 @@ module \dec_SPR wire width 7 output 2 \SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 5 \SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -193408,7 +195828,7 @@ module \dec_SPR attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SPR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -193425,7 +195845,7 @@ module \dec_SPR attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -193502,46 +195922,46 @@ module \dec_SPR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SPR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123607.7-123607.15" + attribute \src "libresoc.v:125214.7-125214.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \is_mmu_spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:812" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813" wire \is_spr_mv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 6 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123901$4712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125508$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193549,10 +195969,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123901$4712_Y + connect \Y $and$libresoc.v:125508$4753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123903$4714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125510$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193560,10 +195980,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123903$4714_Y + connect \Y $and$libresoc.v:125510$4755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123916$4727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125523$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193571,10 +195991,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123916$4727_Y + connect \Y $and$libresoc.v:125523$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123917$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125524$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193582,10 +196002,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123917$4728_Y + connect \Y $and$libresoc.v:125524$4769_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123919$4730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125526$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193593,10 +196013,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123919$4730_Y + connect \Y $and$libresoc.v:125526$4771_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $and $and$libresoc.v:123921$4732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $and $and$libresoc.v:125528$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193604,10 +196024,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123921$4732_Y + connect \Y $and$libresoc.v:125528$4773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123922$4733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125529$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193615,10 +196035,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123922$4733_Y + connect \Y $and$libresoc.v:125529$4774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $and $and$libresoc.v:123923$4734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $and $and$libresoc.v:125530$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193626,10 +196046,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123923$4734_Y + connect \Y $and$libresoc.v:125530$4775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" - cell $eq $eq$libresoc.v:123904$4715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" + cell $eq $eq$libresoc.v:125511$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193637,10 +196057,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123904$4715_Y + connect \Y $eq$libresoc.v:125511$4756_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123905$4716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $eq $eq$libresoc.v:125512$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193648,10 +196068,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123905$4716_Y + connect \Y $eq$libresoc.v:125512$4757_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123907$4718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125514$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193659,10 +196079,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123907$4718_Y + connect \Y $eq$libresoc.v:125514$4759_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123908$4719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125515$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193670,10 +196090,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123908$4719_Y + connect \Y $eq$libresoc.v:125515$4760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $eq $eq$libresoc.v:123910$4721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $eq $eq$libresoc.v:125517$4762 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193681,10 +196101,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123910$4721_Y + connect \Y $eq$libresoc.v:125517$4762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123911$4722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125518$4763 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193692,10 +196112,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123911$4722_Y + connect \Y $eq$libresoc.v:125518$4763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123913$4724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $eq $eq$libresoc.v:125520$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193703,10 +196123,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123913$4724_Y + connect \Y $eq$libresoc.v:125520$4765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" - cell $eq $eq$libresoc.v:123915$4726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" + cell $eq $eq$libresoc.v:125522$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193714,10 +196134,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123915$4726_Y + connect \Y $eq$libresoc.v:125522$4767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123918$4729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125525$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193725,10 +196145,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123918$4729_Y + connect \Y $eq$libresoc.v:125525$4770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $eq $eq$libresoc.v:123924$4735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $eq $eq$libresoc.v:125531$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193736,26 +196156,26 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123924$4735_Y + connect \Y $eq$libresoc.v:125531$4776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123902$4713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125509$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123902$4713_Y + connect \Y $not$libresoc.v:125509$4754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:825" - cell $not $not$libresoc.v:123920$4731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" + cell $not $not$libresoc.v:125527$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123920$4731_Y + connect \Y $not$libresoc.v:125527$4772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $or $or$libresoc.v:123906$4717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" + cell $or $or$libresoc.v:125513$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193763,10 +196183,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123906$4717_Y + connect \Y $or$libresoc.v:125513$4758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123909$4720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125516$4761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193774,10 +196194,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123909$4720_Y + connect \Y $or$libresoc.v:125516$4761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:818" - cell $or $or$libresoc.v:123912$4723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" + cell $or $or$libresoc.v:125519$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193785,10 +196205,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123912$4723_Y + connect \Y $or$libresoc.v:125519$4764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123914$4725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" + cell $or $or$libresoc.v:125521$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193796,10 +196216,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123914$4725_Y + connect \Y $or$libresoc.v:125521$4766_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123925.13-123937.4" + attribute \src "libresoc.v:125532.13-125544.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -193814,38 +196234,38 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123938.16-123942.4" + attribute \src "libresoc.v:125545.16-125549.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123943.16-123946.4" + attribute \src "libresoc.v:125550.16-125553.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123607.7-123607.20" - process $proc$libresoc.v:123607$4738 + attribute \src "libresoc.v:125214.7-125214.20" + process $proc$libresoc.v:125214$4779 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123947.3-123959.6" - process $proc$libresoc.v:123947$4736 + attribute \src "libresoc.v:125554.3-125566.6" + process $proc$libresoc.v:125554$4777 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:123948.5-123948.29" + attribute \src "libresoc.v:125555.5-125555.29" switch \initial - attribute \src "libresoc.v:123948.9-123948.17" + attribute \src "libresoc.v:125555.9-125555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193861,17 +196281,17 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:123960.3-123974.6" - process $proc$libresoc.v:123960$4737 + attribute \src "libresoc.v:125567.3-125581.6" + process $proc$libresoc.v:125567$4778 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:123961.5-123961.29" + attribute \src "libresoc.v:125568.5-125568.29" switch \initial - attribute \src "libresoc.v:123961.9-123961.17" + attribute \src "libresoc.v:125568.9-125568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:821" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -193889,30 +196309,30 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123901$4712_Y - connect \$12 $not$libresoc.v:123902$4713_Y - connect \$14 $and$libresoc.v:123903$4714_Y - connect \$16 $eq$libresoc.v:123904$4715_Y - connect \$18 $eq$libresoc.v:123905$4716_Y - connect \$20 $or$libresoc.v:123906$4717_Y - connect \$22 $eq$libresoc.v:123907$4718_Y - connect \$24 $eq$libresoc.v:123908$4719_Y - connect \$26 $or$libresoc.v:123909$4720_Y - connect \$28 $eq$libresoc.v:123910$4721_Y - connect \$2 $eq$libresoc.v:123911$4722_Y - connect \$30 $or$libresoc.v:123912$4723_Y - connect \$32 $eq$libresoc.v:123913$4724_Y - connect \$34 $or$libresoc.v:123914$4725_Y - connect \$36 $eq$libresoc.v:123915$4726_Y - connect \$38 $and$libresoc.v:123916$4727_Y - connect \$40 $and$libresoc.v:123917$4728_Y - connect \$42 $eq$libresoc.v:123918$4729_Y - connect \$44 $and$libresoc.v:123919$4730_Y - connect \$46 $not$libresoc.v:123920$4731_Y - connect \$48 $and$libresoc.v:123921$4732_Y - connect \$4 $and$libresoc.v:123922$4733_Y - connect \$6 $and$libresoc.v:123923$4734_Y - connect \$8 $eq$libresoc.v:123924$4735_Y + connect \$10 $and$libresoc.v:125508$4753_Y + connect \$12 $not$libresoc.v:125509$4754_Y + connect \$14 $and$libresoc.v:125510$4755_Y + connect \$16 $eq$libresoc.v:125511$4756_Y + connect \$18 $eq$libresoc.v:125512$4757_Y + connect \$20 $or$libresoc.v:125513$4758_Y + connect \$22 $eq$libresoc.v:125514$4759_Y + connect \$24 $eq$libresoc.v:125515$4760_Y + connect \$26 $or$libresoc.v:125516$4761_Y + connect \$28 $eq$libresoc.v:125517$4762_Y + connect \$2 $eq$libresoc.v:125518$4763_Y + connect \$30 $or$libresoc.v:125519$4764_Y + connect \$32 $eq$libresoc.v:125520$4765_Y + connect \$34 $or$libresoc.v:125521$4766_Y + connect \$36 $eq$libresoc.v:125522$4767_Y + connect \$38 $and$libresoc.v:125523$4768_Y + connect \$40 $and$libresoc.v:125524$4769_Y + connect \$42 $eq$libresoc.v:125525$4770_Y + connect \$44 $and$libresoc.v:125526$4771_Y + connect \$46 $not$libresoc.v:125527$4772_Y + connect \$48 $and$libresoc.v:125528$4773_Y + connect \$4 $and$libresoc.v:125529$4774_Y + connect \$6 $and$libresoc.v:125530$4775_Y + connect \$8 $eq$libresoc.v:125531$4776_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -193923,148 +196343,148 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:123988.1-124517.10" +attribute \src "libresoc.v:125595.1-126124.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:123989.7-123989.20" + attribute \src "libresoc.v:125596.7-125596.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:124481.3-124491.6" + attribute \src "libresoc.v:126088.3-126098.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:124492.3-124502.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:124481.3-124491.6" + attribute \src "libresoc.v:126088.3-126098.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:124503.3-124514.6" + attribute \src "libresoc.v:126110.3-126121.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:124492.3-124502.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:124413.3-124428.6" + attribute \src "libresoc.v:126020.3-126035.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:124429.3-124444.6" + attribute \src "libresoc.v:126036.3-126051.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:124445.3-124480.6" + attribute \src "libresoc.v:126052.3-126087.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:124388.18-124388.108" - wire $and$libresoc.v:124388$4740_Y - attribute \src "libresoc.v:124397.18-124397.110" - wire $and$libresoc.v:124397$4749_Y - attribute \src "libresoc.v:124402.18-124402.113" - wire $and$libresoc.v:124402$4754_Y - attribute \src "libresoc.v:124390.18-124390.112" - wire $eq$libresoc.v:124390$4742_Y - attribute \src "libresoc.v:124391.18-124391.112" - wire $eq$libresoc.v:124391$4743_Y - attribute \src "libresoc.v:124392.17-124392.111" - wire $eq$libresoc.v:124392$4744_Y - attribute \src "libresoc.v:124393.18-124393.112" - wire $eq$libresoc.v:124393$4745_Y - attribute \src "libresoc.v:124399.18-124399.112" - wire $eq$libresoc.v:124399$4751_Y - attribute \src "libresoc.v:124403.17-124403.111" - wire $eq$libresoc.v:124403$4755_Y - attribute \src "libresoc.v:124394.18-124394.109" - wire $ne$libresoc.v:124394$4746_Y - attribute \src "libresoc.v:124395.18-124395.111" - wire $ne$libresoc.v:124395$4747_Y - attribute \src "libresoc.v:124404.17-124404.108" - wire $ne$libresoc.v:124404$4756_Y - attribute \src "libresoc.v:124405.17-124405.110" - wire $ne$libresoc.v:124405$4757_Y - attribute \src "libresoc.v:124400.18-124400.105" - wire $not$libresoc.v:124400$4752_Y - attribute \src "libresoc.v:124401.18-124401.108" - wire $not$libresoc.v:124401$4753_Y - attribute \src "libresoc.v:124387.17-124387.107" - wire $or$libresoc.v:124387$4739_Y - attribute \src "libresoc.v:124389.18-124389.109" - wire $or$libresoc.v:124389$4741_Y - attribute \src "libresoc.v:124396.18-124396.110" - wire $or$libresoc.v:124396$4748_Y - attribute \src "libresoc.v:124398.18-124398.110" - wire $or$libresoc.v:124398$4750_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + attribute \src "libresoc.v:125995.18-125995.108" + wire $and$libresoc.v:125995$4781_Y + attribute \src "libresoc.v:126004.18-126004.110" + wire $and$libresoc.v:126004$4790_Y + attribute \src "libresoc.v:126009.18-126009.113" + wire $and$libresoc.v:126009$4795_Y + attribute \src "libresoc.v:125997.18-125997.112" + wire $eq$libresoc.v:125997$4783_Y + attribute \src "libresoc.v:125998.18-125998.112" + wire $eq$libresoc.v:125998$4784_Y + attribute \src "libresoc.v:125999.17-125999.111" + wire $eq$libresoc.v:125999$4785_Y + attribute \src "libresoc.v:126000.18-126000.112" + wire $eq$libresoc.v:126000$4786_Y + attribute \src "libresoc.v:126006.18-126006.112" + wire $eq$libresoc.v:126006$4792_Y + attribute \src "libresoc.v:126010.17-126010.111" + wire $eq$libresoc.v:126010$4796_Y + attribute \src "libresoc.v:126001.18-126001.109" + wire $ne$libresoc.v:126001$4787_Y + attribute \src "libresoc.v:126002.18-126002.111" + wire $ne$libresoc.v:126002$4788_Y + attribute \src "libresoc.v:126011.17-126011.108" + wire $ne$libresoc.v:126011$4797_Y + attribute \src "libresoc.v:126012.17-126012.110" + wire $ne$libresoc.v:126012$4798_Y + attribute \src "libresoc.v:126007.18-126007.105" + wire $not$libresoc.v:126007$4793_Y + attribute \src "libresoc.v:126008.18-126008.108" + wire $not$libresoc.v:126008$4794_Y + attribute \src "libresoc.v:125994.17-125994.107" + wire $or$libresoc.v:125994$4780_Y + attribute \src "libresoc.v:125996.18-125996.109" + wire $or$libresoc.v:125996$4782_Y + attribute \src "libresoc.v:126003.18-126003.110" + wire $or$libresoc.v:126003$4789_Y + attribute \src "libresoc.v:126005.18-126005.110" + wire $or$libresoc.v:126005$4791_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - wire \$19 + wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 13 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 9 \fast_a_ok - attribute \src "libresoc.v:123989.7-123989.15" + attribute \src "libresoc.v:125596.7-125596.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -194141,15 +196561,15 @@ module \dec_a attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 14 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 4 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -194157,9 +196577,9 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:145" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -194283,7 +196703,7 @@ module \dec_a wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -194403,10 +196823,10 @@ module \dec_a wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire input 2 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $and $and$libresoc.v:124388$4740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $and $and$libresoc.v:125995$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194414,10 +196834,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 - connect \Y $and$libresoc.v:124388$4740_Y + connect \Y $and$libresoc.v:125995$4781_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $and $and$libresoc.v:124397$4749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $and $and$libresoc.v:126004$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194425,10 +196845,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 - connect \Y $and$libresoc.v:124397$4749_Y + connect \Y $and$libresoc.v:126004$4790_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" - cell $and $and$libresoc.v:124402$4754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $and $and$libresoc.v:126009$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194436,10 +196856,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 - connect \Y $and$libresoc.v:124402$4754_Y + connect \Y $and$libresoc.v:126009$4795_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $eq $eq$libresoc.v:124390$4742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + cell $eq $eq$libresoc.v:125997$4783 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194447,10 +196867,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:124390$4742_Y + connect \Y $eq$libresoc.v:125997$4783_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:124391$4743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:125998$4784 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194458,10 +196878,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:124391$4743_Y + connect \Y $eq$libresoc.v:125998$4784_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" - cell $eq $eq$libresoc.v:124392$4744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $eq $eq$libresoc.v:125999$4785 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194469,10 +196889,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:124392$4744_Y + connect \Y $eq$libresoc.v:125999$4785_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:124393$4745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $eq $eq$libresoc.v:126000$4786 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194480,10 +196900,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124393$4745_Y + connect \Y $eq$libresoc.v:126000$4786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $eq $eq$libresoc.v:124399$4751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + cell $eq $eq$libresoc.v:126006$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194491,10 +196911,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:124399$4751_Y + connect \Y $eq$libresoc.v:126006$4792_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:124403$4755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + cell $eq $eq$libresoc.v:126010$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194502,10 +196922,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124403$4755_Y + connect \Y $eq$libresoc.v:126010$4796_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124394$4746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126001$4787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194513,10 +196933,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:124394$4746_Y + connect \Y $ne$libresoc.v:126001$4787_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124395$4747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126002$4788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194524,10 +196944,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:124395$4747_Y + connect \Y $ne$libresoc.v:126002$4788_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124404$4756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126011$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194535,10 +196955,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:124404$4756_Y + connect \Y $ne$libresoc.v:126011$4797_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $ne $ne$libresoc.v:124405$4757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $ne $ne$libresoc.v:126012$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194546,26 +196966,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:124405$4757_Y + connect \Y $ne$libresoc.v:126012$4798_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - cell $not $not$libresoc.v:124400$4752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + cell $not $not$libresoc.v:126007$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:124400$4752_Y + connect \Y $not$libresoc.v:126007$4793_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" - cell $not $not$libresoc.v:124401$4753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + cell $not $not$libresoc.v:126008$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:124401$4753_Y + connect \Y $not$libresoc.v:126008$4794_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124387$4739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:125994$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194573,10 +196993,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:124387$4739_Y + connect \Y $or$libresoc.v:125994$4780_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124389$4741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:125996$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194584,10 +197004,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 - connect \Y $or$libresoc.v:124389$4741_Y + connect \Y $or$libresoc.v:125996$4782_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124396$4748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:126003$4789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194595,10 +197015,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 - connect \Y $or$libresoc.v:124396$4748_Y + connect \Y $or$libresoc.v:126003$4789_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $or $or$libresoc.v:124398$4750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $or $or$libresoc.v:126005$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194606,10 +197026,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 - connect \Y $or$libresoc.v:124398$4750_Y + connect \Y $or$libresoc.v:126005$4791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124406.10-124412.4" + attribute \src "libresoc.v:126013.10-126019.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -194617,27 +197037,27 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:123989.7-123989.20" - process $proc$libresoc.v:123989$4764 + attribute \src "libresoc.v:125596.7-125596.20" + process $proc$libresoc.v:125596$4805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124413.3-124428.6" - process $proc$libresoc.v:124413$4758 + attribute \src "libresoc.v:126020.3-126035.6" + process $proc$libresoc.v:126020$4799 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:124414.5-124414.29" + attribute \src "libresoc.v:126021.5-126021.29" switch \initial - attribute \src "libresoc.v:124414.9-124414.17" + attribute \src "libresoc.v:126021.9-126021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194646,7 +197066,7 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194658,19 +197078,19 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:124429.3-124444.6" - process $proc$libresoc.v:124429$4759 + attribute \src "libresoc.v:126036.3-126051.6" + process $proc$libresoc.v:126036$4800 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:124430.5-124430.29" + attribute \src "libresoc.v:126037.5-126037.29" switch \initial - attribute \src "libresoc.v:124430.9-124430.17" + attribute \src "libresoc.v:126037.9-126037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194679,7 +197099,7 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194691,21 +197111,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:124445.3-124480.6" - process $proc$libresoc.v:124445$4760 + attribute \src "libresoc.v:126052.3-126087.6" + process $proc$libresoc.v:126052$4801 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:124446.5-124446.29" + attribute \src "libresoc.v:126053.5-126053.29" switch \initial - attribute \src "libresoc.v:124446.9-124446.17" + attribute \src "libresoc.v:126053.9-126053.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -194713,7 +197133,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194731,7 +197151,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194756,18 +197176,18 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:124481.3-124491.6" - process $proc$libresoc.v:124481$4761 + attribute \src "libresoc.v:126088.3-126098.6" + process $proc$libresoc.v:126088$4802 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:124482.5-124482.29" + attribute \src "libresoc.v:126089.5-126089.29" switch \initial - attribute \src "libresoc.v:124482.9-124482.17" + attribute \src "libresoc.v:126089.9-126089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194779,18 +197199,18 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:124492.3-124502.6" - process $proc$libresoc.v:124492$4762 + attribute \src "libresoc.v:126099.3-126109.6" + process $proc$libresoc.v:126099$4803 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:124493.5-124493.29" + attribute \src "libresoc.v:126100.5-126100.29" switch \initial - attribute \src "libresoc.v:124493.9-124493.17" + attribute \src "libresoc.v:126100.9-126100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194802,21 +197222,21 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:124503.3-124514.6" - process $proc$libresoc.v:124503$4763 + attribute \src "libresoc.v:126110.3-126121.6" + process $proc$libresoc.v:126110$4804 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:124504.5-124504.29" + attribute \src "libresoc.v:126111.5-126111.29" switch \initial - attribute \src "libresoc.v:124504.9-124504.17" + attribute \src "libresoc.v:126111.9-126111.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -194831,66 +197251,66 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:124387$4739_Y - connect \$11 $and$libresoc.v:124388$4740_Y - connect \$13 $or$libresoc.v:124389$4741_Y - connect \$15 $eq$libresoc.v:124390$4742_Y - connect \$17 $eq$libresoc.v:124391$4743_Y - connect \$1 $eq$libresoc.v:124392$4744_Y - connect \$19 $eq$libresoc.v:124393$4745_Y - connect \$21 $ne$libresoc.v:124394$4746_Y - connect \$23 $ne$libresoc.v:124395$4747_Y - connect \$25 $or$libresoc.v:124396$4748_Y - connect \$27 $and$libresoc.v:124397$4749_Y - connect \$29 $or$libresoc.v:124398$4750_Y - connect \$31 $eq$libresoc.v:124399$4751_Y - connect \$33 $not$libresoc.v:124400$4752_Y - connect \$35 $not$libresoc.v:124401$4753_Y - connect \$37 $and$libresoc.v:124402$4754_Y - connect \$3 $eq$libresoc.v:124403$4755_Y - connect \$5 $ne$libresoc.v:124404$4756_Y - connect \$7 $ne$libresoc.v:124405$4757_Y + connect \$9 $or$libresoc.v:125994$4780_Y + connect \$11 $and$libresoc.v:125995$4781_Y + connect \$13 $or$libresoc.v:125996$4782_Y + connect \$15 $eq$libresoc.v:125997$4783_Y + connect \$17 $eq$libresoc.v:125998$4784_Y + connect \$1 $eq$libresoc.v:125999$4785_Y + connect \$19 $eq$libresoc.v:126000$4786_Y + connect \$21 $ne$libresoc.v:126001$4787_Y + connect \$23 $ne$libresoc.v:126002$4788_Y + connect \$25 $or$libresoc.v:126003$4789_Y + connect \$27 $and$libresoc.v:126004$4790_Y + connect \$29 $or$libresoc.v:126005$4791_Y + connect \$31 $eq$libresoc.v:126006$4792_Y + connect \$33 $not$libresoc.v:126007$4793_Y + connect \$35 $not$libresoc.v:126008$4794_Y + connect \$37 $and$libresoc.v:126009$4795_Y + connect \$3 $eq$libresoc.v:126010$4796_Y + connect \$5 $ne$libresoc.v:126011$4797_Y + connect \$7 $ne$libresoc.v:126012$4798_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:124521.1-124566.10" +attribute \src "libresoc.v:126128.1-126173.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:124555.3-124564.6" + attribute \src "libresoc.v:126162.3-126171.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124522.7-124522.20" + attribute \src "libresoc.v:126129.7-126129.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124555.3-124564.6" + attribute \src "libresoc.v:126162.3-126171.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124550.17-124550.107" - wire $and$libresoc.v:124550$4765_Y - attribute \src "libresoc.v:124553.17-124553.107" - wire $and$libresoc.v:124553$4768_Y - attribute \src "libresoc.v:124551.17-124551.111" - wire $eq$libresoc.v:124551$4766_Y - attribute \src "libresoc.v:124552.17-124552.108" - wire $eq$libresoc.v:124552$4767_Y - attribute \src "libresoc.v:124554.17-124554.110" - wire $eq$libresoc.v:124554$4769_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126157.17-126157.107" + wire $and$libresoc.v:126157$4806_Y + attribute \src "libresoc.v:126160.17-126160.107" + wire $and$libresoc.v:126160$4809_Y + attribute \src "libresoc.v:126158.17-126158.111" + wire $eq$libresoc.v:126158$4807_Y + attribute \src "libresoc.v:126159.17-126159.108" + wire $eq$libresoc.v:126159$4808_Y + attribute \src "libresoc.v:126161.17-126161.110" + wire $eq$libresoc.v:126161$4810_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124522.7-124522.15" + attribute \src "libresoc.v:126129.7-126129.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -194898,12 +197318,12 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124550$4765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126157$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194911,10 +197331,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124550$4765_Y + connect \Y $and$libresoc.v:126157$4806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124553$4768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126160$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194922,10 +197342,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124553$4768_Y + connect \Y $and$libresoc.v:126160$4809_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124551$4766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126158$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -194933,10 +197353,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124551$4766_Y + connect \Y $eq$libresoc.v:126158$4807_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124552$4767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126159$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -194944,10 +197364,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124552$4767_Y + connect \Y $eq$libresoc.v:126159$4808_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124554$4769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126161$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194955,28 +197375,28 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124554$4769_Y + connect \Y $eq$libresoc.v:126161$4810_Y end - attribute \src "libresoc.v:124522.7-124522.20" - process $proc$libresoc.v:124522$4771 + attribute \src "libresoc.v:126129.7-126129.20" + process $proc$libresoc.v:126129$4812 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124555.3-124564.6" - process $proc$libresoc.v:124555$4770 + attribute \src "libresoc.v:126162.3-126171.6" + process $proc$libresoc.v:126162$4811 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124556.5-124556.29" + attribute \src "libresoc.v:126163.5-126163.29" switch \initial - attribute \src "libresoc.v:124556.9-124556.17" + attribute \src "libresoc.v:126163.9-126163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -194988,51 +197408,51 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124550$4765_Y - connect \$1 $eq$libresoc.v:124551$4766_Y - connect \$3 $eq$libresoc.v:124552$4767_Y - connect \$5 $and$libresoc.v:124553$4768_Y - connect \$7 $eq$libresoc.v:124554$4769_Y + connect \$9 $and$libresoc.v:126157$4806_Y + connect \$1 $eq$libresoc.v:126158$4807_Y + connect \$3 $eq$libresoc.v:126159$4808_Y + connect \$5 $and$libresoc.v:126160$4809_Y + connect \$7 $eq$libresoc.v:126161$4810_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:124570.1-124615.10" +attribute \src "libresoc.v:126177.1-126222.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:124604.3-124613.6" + attribute \src "libresoc.v:126211.3-126220.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124571.7-124571.20" + attribute \src "libresoc.v:126178.7-126178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124604.3-124613.6" + attribute \src "libresoc.v:126211.3-126220.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124599.17-124599.107" - wire $and$libresoc.v:124599$4772_Y - attribute \src "libresoc.v:124602.17-124602.107" - wire $and$libresoc.v:124602$4775_Y - attribute \src "libresoc.v:124600.17-124600.111" - wire $eq$libresoc.v:124600$4773_Y - attribute \src "libresoc.v:124601.17-124601.108" - wire $eq$libresoc.v:124601$4774_Y - attribute \src "libresoc.v:124603.17-124603.110" - wire $eq$libresoc.v:124603$4776_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126206.17-126206.107" + wire $and$libresoc.v:126206$4813_Y + attribute \src "libresoc.v:126209.17-126209.107" + wire $and$libresoc.v:126209$4816_Y + attribute \src "libresoc.v:126207.17-126207.111" + wire $eq$libresoc.v:126207$4814_Y + attribute \src "libresoc.v:126208.17-126208.108" + wire $eq$libresoc.v:126208$4815_Y + attribute \src "libresoc.v:126210.17-126210.110" + wire $eq$libresoc.v:126210$4817_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124571.7-124571.15" + attribute \src "libresoc.v:126178.7-126178.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195040,12 +197460,12 @@ module \dec_ai$148 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124599$4772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126206$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195053,10 +197473,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124599$4772_Y + connect \Y $and$libresoc.v:126206$4813_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124602$4775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126209$4816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195064,10 +197484,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124602$4775_Y + connect \Y $and$libresoc.v:126209$4816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124600$4773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126207$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195075,10 +197495,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124600$4773_Y + connect \Y $eq$libresoc.v:126207$4814_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124601$4774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126208$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195086,10 +197506,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124601$4774_Y + connect \Y $eq$libresoc.v:126208$4815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124603$4776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126210$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195097,28 +197517,28 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124603$4776_Y + connect \Y $eq$libresoc.v:126210$4817_Y end - attribute \src "libresoc.v:124571.7-124571.20" - process $proc$libresoc.v:124571$4778 + attribute \src "libresoc.v:126178.7-126178.20" + process $proc$libresoc.v:126178$4819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124604.3-124613.6" - process $proc$libresoc.v:124604$4777 + attribute \src "libresoc.v:126211.3-126220.6" + process $proc$libresoc.v:126211$4818 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124605.5-124605.29" + attribute \src "libresoc.v:126212.5-126212.29" switch \initial - attribute \src "libresoc.v:124605.9-124605.17" + attribute \src "libresoc.v:126212.9-126212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195130,51 +197550,51 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124599$4772_Y - connect \$1 $eq$libresoc.v:124600$4773_Y - connect \$3 $eq$libresoc.v:124601$4774_Y - connect \$5 $and$libresoc.v:124602$4775_Y - connect \$7 $eq$libresoc.v:124603$4776_Y + connect \$9 $and$libresoc.v:126206$4813_Y + connect \$1 $eq$libresoc.v:126207$4814_Y + connect \$3 $eq$libresoc.v:126208$4815_Y + connect \$5 $and$libresoc.v:126209$4816_Y + connect \$7 $eq$libresoc.v:126210$4817_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:124619.1-124664.10" +attribute \src "libresoc.v:126226.1-126271.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:124653.3-124662.6" + attribute \src "libresoc.v:126260.3-126269.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124620.7-124620.20" + attribute \src "libresoc.v:126227.7-126227.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124653.3-124662.6" + attribute \src "libresoc.v:126260.3-126269.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124648.17-124648.107" - wire $and$libresoc.v:124648$4779_Y - attribute \src "libresoc.v:124651.17-124651.107" - wire $and$libresoc.v:124651$4782_Y - attribute \src "libresoc.v:124649.17-124649.111" - wire $eq$libresoc.v:124649$4780_Y - attribute \src "libresoc.v:124650.17-124650.108" - wire $eq$libresoc.v:124650$4781_Y - attribute \src "libresoc.v:124652.17-124652.110" - wire $eq$libresoc.v:124652$4783_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126255.17-126255.107" + wire $and$libresoc.v:126255$4820_Y + attribute \src "libresoc.v:126258.17-126258.107" + wire $and$libresoc.v:126258$4823_Y + attribute \src "libresoc.v:126256.17-126256.111" + wire $eq$libresoc.v:126256$4821_Y + attribute \src "libresoc.v:126257.17-126257.108" + wire $eq$libresoc.v:126257$4822_Y + attribute \src "libresoc.v:126259.17-126259.110" + wire $eq$libresoc.v:126259$4824_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124620.7-124620.15" + attribute \src "libresoc.v:126227.7-126227.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195182,12 +197602,12 @@ module \dec_ai$156 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124648$4779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126255$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195195,10 +197615,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124648$4779_Y + connect \Y $and$libresoc.v:126255$4820_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124651$4782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126258$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195206,10 +197626,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124651$4782_Y + connect \Y $and$libresoc.v:126258$4823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124649$4780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126256$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195217,10 +197637,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124649$4780_Y + connect \Y $eq$libresoc.v:126256$4821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124650$4781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126257$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195228,10 +197648,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124650$4781_Y + connect \Y $eq$libresoc.v:126257$4822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124652$4783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126259$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195239,28 +197659,28 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124652$4783_Y + connect \Y $eq$libresoc.v:126259$4824_Y end - attribute \src "libresoc.v:124620.7-124620.20" - process $proc$libresoc.v:124620$4785 + attribute \src "libresoc.v:126227.7-126227.20" + process $proc$libresoc.v:126227$4826 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124653.3-124662.6" - process $proc$libresoc.v:124653$4784 + attribute \src "libresoc.v:126260.3-126269.6" + process $proc$libresoc.v:126260$4825 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124654.5-124654.29" + attribute \src "libresoc.v:126261.5-126261.29" switch \initial - attribute \src "libresoc.v:124654.9-124654.17" + attribute \src "libresoc.v:126261.9-126261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195272,51 +197692,51 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124648$4779_Y - connect \$1 $eq$libresoc.v:124649$4780_Y - connect \$3 $eq$libresoc.v:124650$4781_Y - connect \$5 $and$libresoc.v:124651$4782_Y - connect \$7 $eq$libresoc.v:124652$4783_Y + connect \$9 $and$libresoc.v:126255$4820_Y + connect \$1 $eq$libresoc.v:126256$4821_Y + connect \$3 $eq$libresoc.v:126257$4822_Y + connect \$5 $and$libresoc.v:126258$4823_Y + connect \$7 $eq$libresoc.v:126259$4824_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:124668.1-124713.10" +attribute \src "libresoc.v:126275.1-126320.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:124702.3-124711.6" + attribute \src "libresoc.v:126309.3-126318.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:124669.7-124669.20" + attribute \src "libresoc.v:126276.7-126276.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124702.3-124711.6" + attribute \src "libresoc.v:126309.3-126318.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124697.17-124697.107" - wire $and$libresoc.v:124697$4786_Y - attribute \src "libresoc.v:124700.17-124700.107" - wire $and$libresoc.v:124700$4789_Y - attribute \src "libresoc.v:124698.17-124698.111" - wire $eq$libresoc.v:124698$4787_Y - attribute \src "libresoc.v:124699.17-124699.108" - wire $eq$libresoc.v:124699$4788_Y - attribute \src "libresoc.v:124701.17-124701.110" - wire $eq$libresoc.v:124701$4790_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "libresoc.v:126304.17-126304.107" + wire $and$libresoc.v:126304$4827_Y + attribute \src "libresoc.v:126307.17-126307.107" + wire $and$libresoc.v:126307$4830_Y + attribute \src "libresoc.v:126305.17-126305.111" + wire $eq$libresoc.v:126305$4828_Y + attribute \src "libresoc.v:126306.17-126306.108" + wire $eq$libresoc.v:126306$4829_Y + attribute \src "libresoc.v:126308.17-126308.110" + wire $eq$libresoc.v:126308$4831_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:124669.7-124669.15" + attribute \src "libresoc.v:126276.7-126276.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -195324,12 +197744,12 @@ module \dec_ai$169 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:124697$4786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $and $and$libresoc.v:126304$4827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195337,10 +197757,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:124697$4786_Y + connect \Y $and$libresoc.v:126304$4827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $and $and$libresoc.v:124700$4789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $and $and$libresoc.v:126307$4830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195348,10 +197768,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124700$4789_Y + connect \Y $and$libresoc.v:126307$4830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124698$4787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126305$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -195359,10 +197779,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124698$4787_Y + connect \Y $eq$libresoc.v:126305$4828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:174" - cell $eq $eq$libresoc.v:124699$4788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + cell $eq $eq$libresoc.v:126306$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -195370,10 +197790,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124699$4788_Y + connect \Y $eq$libresoc.v:126306$4829_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:124701$4790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + cell $eq $eq$libresoc.v:126308$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195381,28 +197801,28 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:124701$4790_Y + connect \Y $eq$libresoc.v:126308$4831_Y end - attribute \src "libresoc.v:124669.7-124669.20" - process $proc$libresoc.v:124669$4792 + attribute \src "libresoc.v:126276.7-126276.20" + process $proc$libresoc.v:126276$4833 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124702.3-124711.6" - process $proc$libresoc.v:124702$4791 + attribute \src "libresoc.v:126309.3-126318.6" + process $proc$libresoc.v:126309$4832 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124703.5-124703.29" + attribute \src "libresoc.v:126310.5-126310.29" switch \initial - attribute \src "libresoc.v:124703.9-124703.17" + attribute \src "libresoc.v:126310.9-126310.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -195414,79 +197834,79 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:124697$4786_Y - connect \$1 $eq$libresoc.v:124698$4787_Y - connect \$3 $eq$libresoc.v:124699$4788_Y - connect \$5 $and$libresoc.v:124700$4789_Y - connect \$7 $eq$libresoc.v:124701$4790_Y + connect \$9 $and$libresoc.v:126304$4827_Y + connect \$1 $eq$libresoc.v:126305$4828_Y + connect \$3 $eq$libresoc.v:126306$4829_Y + connect \$5 $and$libresoc.v:126307$4830_Y + connect \$7 $eq$libresoc.v:126308$4831_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:124717.1-124915.10" +attribute \src "libresoc.v:126324.1-126522.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:124718.7-124718.20" + attribute \src "libresoc.v:126325.7-126325.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124849.3-124863.6" + attribute \src "libresoc.v:126456.3-126470.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:124864.3-124878.6" + attribute \src "libresoc.v:126471.3-126485.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124849.3-124863.6" + attribute \src "libresoc.v:126456.3-126470.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:124864.3-124878.6" + attribute \src "libresoc.v:126471.3-126485.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124879.3-124896.6" + attribute \src "libresoc.v:126486.3-126503.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:124897.3-124914.6" + attribute \src "libresoc.v:126504.3-126521.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:124843.17-124843.117" - wire $eq$libresoc.v:124843$4793_Y - attribute \src "libresoc.v:124847.17-124847.117" - wire $eq$libresoc.v:124847$4799_Y - attribute \src "libresoc.v:124845.17-124845.100" - wire width 7 $extend$libresoc.v:124845$4795_Y - attribute \src "libresoc.v:124846.17-124846.100" - wire width 7 $extend$libresoc.v:124846$4797_Y - attribute \src "libresoc.v:124844.18-124844.108" - wire $not$libresoc.v:124844$4794_Y - attribute \src "libresoc.v:124848.17-124848.107" - wire $not$libresoc.v:124848$4800_Y - attribute \src "libresoc.v:124845.17-124845.100" - wire width 7 $pos$libresoc.v:124845$4796_Y - attribute \src "libresoc.v:124846.17-124846.100" - wire width 7 $pos$libresoc.v:124846$4798_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126450.17-126450.117" + wire $eq$libresoc.v:126450$4834_Y + attribute \src "libresoc.v:126454.17-126454.117" + wire $eq$libresoc.v:126454$4840_Y + attribute \src "libresoc.v:126452.17-126452.100" + wire width 7 $extend$libresoc.v:126452$4836_Y + attribute \src "libresoc.v:126453.17-126453.100" + wire width 7 $extend$libresoc.v:126453$4838_Y + attribute \src "libresoc.v:126451.18-126451.108" + wire $not$libresoc.v:126451$4835_Y + attribute \src "libresoc.v:126455.17-126455.107" + wire $not$libresoc.v:126455$4841_Y + attribute \src "libresoc.v:126452.17-126452.100" + wire width 7 $pos$libresoc.v:126452$4837_Y + attribute \src "libresoc.v:126453.17-126453.100" + wire width 7 $pos$libresoc.v:126453$4839_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 8 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:124718.7-124718.15" + attribute \src "libresoc.v:126325.7-126325.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -195563,7 +197983,7 @@ module \dec_b attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 9 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 2 \reg_b @@ -195584,10 +198004,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - cell $eq $eq$libresoc.v:124843$4793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + cell $eq $eq$libresoc.v:126450$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195595,10 +198015,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124843$4793_Y + connect \Y $eq$libresoc.v:126450$4834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - cell $eq $eq$libresoc.v:124847$4799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + cell $eq $eq$libresoc.v:126454$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195606,76 +198026,76 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124847$4799_Y + connect \Y $eq$libresoc.v:126454$4840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124845$4795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126452$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:124845$4795_Y + connect \Y $extend$libresoc.v:126452$4836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124846$4797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126453$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:124846$4797_Y + connect \Y $extend$libresoc.v:126453$4838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" - cell $not $not$libresoc.v:124844$4794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + cell $not $not$libresoc.v:126451$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124844$4794_Y + connect \Y $not$libresoc.v:126451$4835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" - cell $not $not$libresoc.v:124848$4800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" + cell $not $not$libresoc.v:126455$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124848$4800_Y + connect \Y $not$libresoc.v:126455$4841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124845$4796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126452$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124845$4795_Y - connect \Y $pos$libresoc.v:124845$4796_Y + connect \A $extend$libresoc.v:126452$4836_Y + connect \Y $pos$libresoc.v:126452$4837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124846$4798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126453$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124846$4797_Y - connect \Y $pos$libresoc.v:124846$4798_Y + connect \A $extend$libresoc.v:126453$4838_Y + connect \Y $pos$libresoc.v:126453$4839_Y end - attribute \src "libresoc.v:124718.7-124718.20" - process $proc$libresoc.v:124718$4805 + attribute \src "libresoc.v:126325.7-126325.20" + process $proc$libresoc.v:126325$4846 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124849.3-124863.6" - process $proc$libresoc.v:124849$4801 + attribute \src "libresoc.v:126456.3-126470.6" + process $proc$libresoc.v:126456$4842 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:124850.5-124850.29" + attribute \src "libresoc.v:126457.5-126457.29" switch \initial - attribute \src "libresoc.v:124850.9-124850.17" + attribute \src "libresoc.v:126457.9-126457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -195691,18 +198111,18 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:124864.3-124878.6" - process $proc$libresoc.v:124864$4802 + attribute \src "libresoc.v:126471.3-126485.6" + process $proc$libresoc.v:126471$4843 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124865.5-124865.29" + attribute \src "libresoc.v:126472.5-126472.29" switch \initial - attribute \src "libresoc.v:124865.9-124865.17" + attribute \src "libresoc.v:126472.9-126472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -195718,24 +198138,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:124879.3-124896.6" - process $proc$libresoc.v:124879$4803 + attribute \src "libresoc.v:126486.3-126503.6" + process $proc$libresoc.v:126486$4844 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:124880.5-124880.29" + attribute \src "libresoc.v:126487.5-126487.29" switch \initial - attribute \src "libresoc.v:124880.9-124880.17" + attribute \src "libresoc.v:126487.9-126487.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195754,24 +198174,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:124897.3-124914.6" - process $proc$libresoc.v:124897$4804 + attribute \src "libresoc.v:126504.3-126521.6" + process $proc$libresoc.v:126504$4845 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124898.5-124898.29" + attribute \src "libresoc.v:126505.5-126505.29" switch \initial - attribute \src "libresoc.v:124898.9-124898.17" + attribute \src "libresoc.v:126505.9-126505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -195790,131 +198210,131 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:124843$4793_Y - connect \$11 $not$libresoc.v:124844$4794_Y - connect \$1 $pos$libresoc.v:124845$4796_Y - connect \$3 $pos$libresoc.v:124846$4798_Y - connect \$5 $eq$libresoc.v:124847$4799_Y - connect \$7 $not$libresoc.v:124848$4800_Y + connect \$9 $eq$libresoc.v:126450$4834_Y + connect \$11 $not$libresoc.v:126451$4835_Y + connect \$1 $pos$libresoc.v:126452$4837_Y + connect \$3 $pos$libresoc.v:126453$4839_Y + connect \$5 $eq$libresoc.v:126454$4840_Y + connect \$7 $not$libresoc.v:126455$4841_Y end -attribute \src "libresoc.v:124919.1-125172.10" +attribute \src "libresoc.v:126526.1-126779.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:125146.3-125156.6" + attribute \src "libresoc.v:126753.3-126763.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125157.3-125167.6" + attribute \src "libresoc.v:126764.3-126774.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125008.3-125054.6" + attribute \src "libresoc.v:126615.3-126661.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125055.3-125101.6" + attribute \src "libresoc.v:126662.3-126708.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124920.7-124920.20" + attribute \src "libresoc.v:126527.7-126527.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125135.3-125145.6" + attribute \src "libresoc.v:126742.3-126752.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125102.3-125112.6" + attribute \src "libresoc.v:126709.3-126719.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125113.3-125123.6" + attribute \src "libresoc.v:126720.3-126730.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125124.3-125134.6" + attribute \src "libresoc.v:126731.3-126741.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125146.3-125156.6" + attribute \src "libresoc.v:126753.3-126763.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125157.3-125167.6" + attribute \src "libresoc.v:126764.3-126774.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125008.3-125054.6" + attribute \src "libresoc.v:126615.3-126661.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125055.3-125101.6" + attribute \src "libresoc.v:126662.3-126708.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125135.3-125145.6" + attribute \src "libresoc.v:126742.3-126752.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125102.3-125112.6" + attribute \src "libresoc.v:126709.3-126719.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125113.3-125123.6" + attribute \src "libresoc.v:126720.3-126730.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125124.3-125134.6" + attribute \src "libresoc.v:126731.3-126741.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124998.17-124998.104" - wire width 64 $extend$libresoc.v:124998$4806_Y - attribute \src "libresoc.v:124999.18-124999.107" - wire width 64 $extend$libresoc.v:124999$4808_Y - attribute \src "libresoc.v:125002.17-125002.104" - wire width 64 $extend$libresoc.v:125002$4812_Y - attribute \src "libresoc.v:125006.17-125006.102" - wire width 64 $extend$libresoc.v:125006$4817_Y - attribute \src "libresoc.v:124998.17-124998.104" - wire width 64 $pos$libresoc.v:124998$4807_Y - attribute \src "libresoc.v:124999.18-124999.107" - wire width 64 $pos$libresoc.v:124999$4809_Y - attribute \src "libresoc.v:125002.17-125002.104" - wire width 64 $pos$libresoc.v:125002$4813_Y - attribute \src "libresoc.v:125006.17-125006.102" - wire width 64 $pos$libresoc.v:125006$4818_Y - attribute \src "libresoc.v:125000.18-125000.114" - wire width 47 $sshl$libresoc.v:125000$4810_Y - attribute \src "libresoc.v:125001.18-125001.113" - wire width 27 $sshl$libresoc.v:125001$4811_Y - attribute \src "libresoc.v:125003.18-125003.113" - wire width 17 $sshl$libresoc.v:125003$4814_Y - attribute \src "libresoc.v:125004.18-125004.113" - wire width 17 $sshl$libresoc.v:125004$4815_Y - attribute \src "libresoc.v:125005.17-125005.109" - wire width 47 $sshl$libresoc.v:125005$4816_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126605.17-126605.104" + wire width 64 $extend$libresoc.v:126605$4847_Y + attribute \src "libresoc.v:126606.18-126606.107" + wire width 64 $extend$libresoc.v:126606$4849_Y + attribute \src "libresoc.v:126609.17-126609.104" + wire width 64 $extend$libresoc.v:126609$4853_Y + attribute \src "libresoc.v:126613.17-126613.102" + wire width 64 $extend$libresoc.v:126613$4858_Y + attribute \src "libresoc.v:126605.17-126605.104" + wire width 64 $pos$libresoc.v:126605$4848_Y + attribute \src "libresoc.v:126606.18-126606.107" + wire width 64 $pos$libresoc.v:126606$4850_Y + attribute \src "libresoc.v:126609.17-126609.104" + wire width 64 $pos$libresoc.v:126609$4854_Y + attribute \src "libresoc.v:126613.17-126613.102" + wire width 64 $pos$libresoc.v:126613$4859_Y + attribute \src "libresoc.v:126607.18-126607.114" + wire width 47 $sshl$libresoc.v:126607$4851_Y + attribute \src "libresoc.v:126608.18-126608.113" + wire width 27 $sshl$libresoc.v:126608$4852_Y + attribute \src "libresoc.v:126610.18-126610.113" + wire width 17 $sshl$libresoc.v:126610$4855_Y + attribute \src "libresoc.v:126611.18-126611.113" + wire width 17 $sshl$libresoc.v:126611$4856_Y + attribute \src "libresoc.v:126612.17-126612.109" + wire width 47 $sshl$libresoc.v:126612$4857_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124920.7-124920.15" + attribute \src "libresoc.v:126527.7-126527.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195931,80 +198351,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124998$4806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126605$4847 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:124998$4806_Y + connect \Y $extend$libresoc.v:126605$4847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124999$4808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126606$4849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:124999$4808_Y + connect \Y $extend$libresoc.v:126606$4849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125002$4812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126609$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:125002$4812_Y + connect \Y $extend$libresoc.v:126609$4853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125006$4817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:126613$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125006$4817_Y + connect \Y $extend$libresoc.v:126613$4858_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124998$4807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126605$4848 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124998$4806_Y - connect \Y $pos$libresoc.v:124998$4807_Y + connect \A $extend$libresoc.v:126605$4847_Y + connect \Y $pos$libresoc.v:126605$4848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124999$4809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126606$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124999$4808_Y - connect \Y $pos$libresoc.v:124999$4809_Y + connect \A $extend$libresoc.v:126606$4849_Y + connect \Y $pos$libresoc.v:126606$4850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125002$4813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126609$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125002$4812_Y - connect \Y $pos$libresoc.v:125002$4813_Y + connect \A $extend$libresoc.v:126609$4853_Y + connect \Y $pos$libresoc.v:126609$4854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125006$4818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126613$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125006$4817_Y - connect \Y $pos$libresoc.v:125006$4818_Y + connect \A $extend$libresoc.v:126613$4858_Y + connect \Y $pos$libresoc.v:126613$4859_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125000$4810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126607$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196012,10 +198432,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125000$4810_Y + connect \Y $sshl$libresoc.v:126607$4851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125001$4811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126608$4852 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196023,10 +198443,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125001$4811_Y + connect \Y $sshl$libresoc.v:126608$4852_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125003$4814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126610$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196034,10 +198454,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125003$4814_Y + connect \Y $sshl$libresoc.v:126610$4855_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125004$4815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126611$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196045,10 +198465,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125004$4815_Y + connect \Y $sshl$libresoc.v:126611$4856_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125005$4816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126612$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196056,28 +198476,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125005$4816_Y + connect \Y $sshl$libresoc.v:126612$4857_Y end - attribute \src "libresoc.v:124920.7-124920.20" - process $proc$libresoc.v:124920$4827 + attribute \src "libresoc.v:126527.7-126527.20" + process $proc$libresoc.v:126527$4868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125008.3-125054.6" - process $proc$libresoc.v:125008$4819 + attribute \src "libresoc.v:126615.3-126661.6" + process $proc$libresoc.v:126615$4860 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125009.5-125009.29" + attribute \src "libresoc.v:126616.5-126616.29" switch \initial - attribute \src "libresoc.v:125009.9-125009.17" + attribute \src "libresoc.v:126616.9-126616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196125,18 +198545,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125055.3-125101.6" - process $proc$libresoc.v:125055$4820 + attribute \src "libresoc.v:126662.3-126708.6" + process $proc$libresoc.v:126662$4861 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125056.5-125056.29" + attribute \src "libresoc.v:126663.5-126663.29" switch \initial - attribute \src "libresoc.v:125056.9-125056.17" + attribute \src "libresoc.v:126663.9-126663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196184,18 +198604,18 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125102.3-125112.6" - process $proc$libresoc.v:125102$4821 + attribute \src "libresoc.v:126709.3-126719.6" + process $proc$libresoc.v:126709$4862 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125103.5-125103.29" + attribute \src "libresoc.v:126710.5-126710.29" switch \initial - attribute \src "libresoc.v:125103.9-125103.17" + attribute \src "libresoc.v:126710.9-126710.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196207,18 +198627,18 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125113.3-125123.6" - process $proc$libresoc.v:125113$4822 + attribute \src "libresoc.v:126720.3-126730.6" + process $proc$libresoc.v:126720$4863 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125114.5-125114.29" + attribute \src "libresoc.v:126721.5-126721.29" switch \initial - attribute \src "libresoc.v:125114.9-125114.17" + attribute \src "libresoc.v:126721.9-126721.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196230,18 +198650,18 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125124.3-125134.6" - process $proc$libresoc.v:125124$4823 + attribute \src "libresoc.v:126731.3-126741.6" + process $proc$libresoc.v:126731$4864 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125125.5-125125.29" + attribute \src "libresoc.v:126732.5-126732.29" switch \initial - attribute \src "libresoc.v:125125.9-125125.17" + attribute \src "libresoc.v:126732.9-126732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196253,18 +198673,18 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125135.3-125145.6" - process $proc$libresoc.v:125135$4824 + attribute \src "libresoc.v:126742.3-126752.6" + process $proc$libresoc.v:126742$4865 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125136.5-125136.29" + attribute \src "libresoc.v:126743.5-126743.29" switch \initial - attribute \src "libresoc.v:125136.9-125136.17" + attribute \src "libresoc.v:126743.9-126743.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196276,18 +198696,18 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125146.3-125156.6" - process $proc$libresoc.v:125146$4825 + attribute \src "libresoc.v:126753.3-126763.6" + process $proc$libresoc.v:126753$4866 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125147.5-125147.29" + attribute \src "libresoc.v:126754.5-126754.29" switch \initial - attribute \src "libresoc.v:125147.9-125147.17" + attribute \src "libresoc.v:126754.9-126754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196299,18 +198719,18 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125157.3-125167.6" - process $proc$libresoc.v:125157$4826 + attribute \src "libresoc.v:126764.3-126774.6" + process $proc$libresoc.v:126764$4867 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125158.5-125158.29" + attribute \src "libresoc.v:126765.5-126765.29" switch \initial - attribute \src "libresoc.v:125158.9-125158.17" + attribute \src "libresoc.v:126765.9-126765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196322,139 +198742,139 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124998$4807_Y - connect \$11 $pos$libresoc.v:124999$4809_Y - connect \$14 $sshl$libresoc.v:125000$4810_Y - connect \$17 $sshl$libresoc.v:125001$4811_Y - connect \$1 $pos$libresoc.v:125002$4813_Y - connect \$20 $sshl$libresoc.v:125003$4814_Y - connect \$23 $sshl$libresoc.v:125004$4815_Y - connect \$4 $sshl$libresoc.v:125005$4816_Y - connect \$3 $pos$libresoc.v:125006$4818_Y + connect \$9 $pos$libresoc.v:126605$4848_Y + connect \$11 $pos$libresoc.v:126606$4850_Y + connect \$14 $sshl$libresoc.v:126607$4851_Y + connect \$17 $sshl$libresoc.v:126608$4852_Y + connect \$1 $pos$libresoc.v:126609$4854_Y + connect \$20 $sshl$libresoc.v:126610$4855_Y + connect \$23 $sshl$libresoc.v:126611$4856_Y + connect \$4 $sshl$libresoc.v:126612$4857_Y + connect \$3 $pos$libresoc.v:126613$4859_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125176.1-125429.10" +attribute \src "libresoc.v:126783.1-127036.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:125403.3-125413.6" + attribute \src "libresoc.v:127010.3-127020.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125414.3-125424.6" + attribute \src "libresoc.v:127021.3-127031.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125265.3-125311.6" + attribute \src "libresoc.v:126872.3-126918.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125312.3-125358.6" + attribute \src "libresoc.v:126919.3-126965.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125177.7-125177.20" + attribute \src "libresoc.v:126784.7-126784.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125392.3-125402.6" + attribute \src "libresoc.v:126999.3-127009.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125359.3-125369.6" + attribute \src "libresoc.v:126966.3-126976.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125370.3-125380.6" + attribute \src "libresoc.v:126977.3-126987.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125381.3-125391.6" + attribute \src "libresoc.v:126988.3-126998.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125403.3-125413.6" + attribute \src "libresoc.v:127010.3-127020.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125414.3-125424.6" + attribute \src "libresoc.v:127021.3-127031.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125265.3-125311.6" + attribute \src "libresoc.v:126872.3-126918.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125312.3-125358.6" + attribute \src "libresoc.v:126919.3-126965.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125392.3-125402.6" + attribute \src "libresoc.v:126999.3-127009.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125359.3-125369.6" + attribute \src "libresoc.v:126966.3-126976.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125370.3-125380.6" + attribute \src "libresoc.v:126977.3-126987.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125381.3-125391.6" + attribute \src "libresoc.v:126988.3-126998.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125255.17-125255.107" - wire width 64 $extend$libresoc.v:125255$4828_Y - attribute \src "libresoc.v:125256.18-125256.110" - wire width 64 $extend$libresoc.v:125256$4830_Y - attribute \src "libresoc.v:125259.17-125259.107" - wire width 64 $extend$libresoc.v:125259$4834_Y - attribute \src "libresoc.v:125263.17-125263.102" - wire width 64 $extend$libresoc.v:125263$4839_Y - attribute \src "libresoc.v:125255.17-125255.107" - wire width 64 $pos$libresoc.v:125255$4829_Y - attribute \src "libresoc.v:125256.18-125256.110" - wire width 64 $pos$libresoc.v:125256$4831_Y - attribute \src "libresoc.v:125259.17-125259.107" - wire width 64 $pos$libresoc.v:125259$4835_Y - attribute \src "libresoc.v:125263.17-125263.102" - wire width 64 $pos$libresoc.v:125263$4840_Y - attribute \src "libresoc.v:125257.18-125257.117" - wire width 47 $sshl$libresoc.v:125257$4832_Y - attribute \src "libresoc.v:125258.18-125258.116" - wire width 27 $sshl$libresoc.v:125258$4833_Y - attribute \src "libresoc.v:125260.18-125260.116" - wire width 17 $sshl$libresoc.v:125260$4836_Y - attribute \src "libresoc.v:125261.18-125261.116" - wire width 17 $sshl$libresoc.v:125261$4837_Y - attribute \src "libresoc.v:125262.17-125262.109" - wire width 47 $sshl$libresoc.v:125262$4838_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:126862.17-126862.107" + wire width 64 $extend$libresoc.v:126862$4869_Y + attribute \src "libresoc.v:126863.18-126863.110" + wire width 64 $extend$libresoc.v:126863$4871_Y + attribute \src "libresoc.v:126866.17-126866.107" + wire width 64 $extend$libresoc.v:126866$4875_Y + attribute \src "libresoc.v:126870.17-126870.102" + wire width 64 $extend$libresoc.v:126870$4880_Y + attribute \src "libresoc.v:126862.17-126862.107" + wire width 64 $pos$libresoc.v:126862$4870_Y + attribute \src "libresoc.v:126863.18-126863.110" + wire width 64 $pos$libresoc.v:126863$4872_Y + attribute \src "libresoc.v:126866.17-126866.107" + wire width 64 $pos$libresoc.v:126866$4876_Y + attribute \src "libresoc.v:126870.17-126870.102" + wire width 64 $pos$libresoc.v:126870$4881_Y + attribute \src "libresoc.v:126864.18-126864.117" + wire width 47 $sshl$libresoc.v:126864$4873_Y + attribute \src "libresoc.v:126865.18-126865.116" + wire width 27 $sshl$libresoc.v:126865$4874_Y + attribute \src "libresoc.v:126867.18-126867.116" + wire width 17 $sshl$libresoc.v:126867$4877_Y + attribute \src "libresoc.v:126868.18-126868.116" + wire width 17 $sshl$libresoc.v:126868$4878_Y + attribute \src "libresoc.v:126869.17-126869.109" + wire width 47 $sshl$libresoc.v:126869$4879_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125177.7-125177.15" + attribute \src "libresoc.v:126784.7-126784.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -196471,80 +198891,80 @@ module \dec_bi$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125255$4828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126862$4869 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:125255$4828_Y + connect \Y $extend$libresoc.v:126862$4869_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125256$4830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126863$4871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:125256$4830_Y + connect \Y $extend$libresoc.v:126863$4871_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125259$4834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:126866$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:125259$4834_Y + connect \Y $extend$libresoc.v:126866$4875_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125263$4839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:126870$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125263$4839_Y + connect \Y $extend$libresoc.v:126870$4880_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125255$4829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126862$4870 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125255$4828_Y - connect \Y $pos$libresoc.v:125255$4829_Y + connect \A $extend$libresoc.v:126862$4869_Y + connect \Y $pos$libresoc.v:126862$4870_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125256$4831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126863$4872 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125256$4830_Y - connect \Y $pos$libresoc.v:125256$4831_Y + connect \A $extend$libresoc.v:126863$4871_Y + connect \Y $pos$libresoc.v:126863$4872_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125259$4835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:126866$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125259$4834_Y - connect \Y $pos$libresoc.v:125259$4835_Y + connect \A $extend$libresoc.v:126866$4875_Y + connect \Y $pos$libresoc.v:126866$4876_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125263$4840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:126870$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125263$4839_Y - connect \Y $pos$libresoc.v:125263$4840_Y + connect \A $extend$libresoc.v:126870$4880_Y + connect \Y $pos$libresoc.v:126870$4881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125257$4832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:126864$4873 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196552,10 +198972,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125257$4832_Y + connect \Y $sshl$libresoc.v:126864$4873_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125258$4833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126865$4874 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196563,10 +198983,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125258$4833_Y + connect \Y $sshl$libresoc.v:126865$4874_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125260$4836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126867$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196574,10 +198994,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125260$4836_Y + connect \Y $sshl$libresoc.v:126867$4877_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125261$4837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:126868$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196585,10 +199005,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125261$4837_Y + connect \Y $sshl$libresoc.v:126868$4878_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125262$4838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:126869$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196596,28 +199016,28 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125262$4838_Y + connect \Y $sshl$libresoc.v:126869$4879_Y end - attribute \src "libresoc.v:125177.7-125177.20" - process $proc$libresoc.v:125177$4849 + attribute \src "libresoc.v:126784.7-126784.20" + process $proc$libresoc.v:126784$4890 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125265.3-125311.6" - process $proc$libresoc.v:125265$4841 + attribute \src "libresoc.v:126872.3-126918.6" + process $proc$libresoc.v:126872$4882 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125266.5-125266.29" + attribute \src "libresoc.v:126873.5-126873.29" switch \initial - attribute \src "libresoc.v:125266.9-125266.17" + attribute \src "libresoc.v:126873.9-126873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196665,18 +199085,18 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125312.3-125358.6" - process $proc$libresoc.v:125312$4842 + attribute \src "libresoc.v:126919.3-126965.6" + process $proc$libresoc.v:126919$4883 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125313.5-125313.29" + attribute \src "libresoc.v:126920.5-126920.29" switch \initial - attribute \src "libresoc.v:125313.9-125313.17" + attribute \src "libresoc.v:126920.9-126920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196724,18 +199144,18 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125359.3-125369.6" - process $proc$libresoc.v:125359$4843 + attribute \src "libresoc.v:126966.3-126976.6" + process $proc$libresoc.v:126966$4884 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125360.5-125360.29" + attribute \src "libresoc.v:126967.5-126967.29" switch \initial - attribute \src "libresoc.v:125360.9-125360.17" + attribute \src "libresoc.v:126967.9-126967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196747,18 +199167,18 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125370.3-125380.6" - process $proc$libresoc.v:125370$4844 + attribute \src "libresoc.v:126977.3-126987.6" + process $proc$libresoc.v:126977$4885 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125371.5-125371.29" + attribute \src "libresoc.v:126978.5-126978.29" switch \initial - attribute \src "libresoc.v:125371.9-125371.17" + attribute \src "libresoc.v:126978.9-126978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196770,18 +199190,18 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125381.3-125391.6" - process $proc$libresoc.v:125381$4845 + attribute \src "libresoc.v:126988.3-126998.6" + process $proc$libresoc.v:126988$4886 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125382.5-125382.29" + attribute \src "libresoc.v:126989.5-126989.29" switch \initial - attribute \src "libresoc.v:125382.9-125382.17" + attribute \src "libresoc.v:126989.9-126989.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196793,18 +199213,18 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125392.3-125402.6" - process $proc$libresoc.v:125392$4846 + attribute \src "libresoc.v:126999.3-127009.6" + process $proc$libresoc.v:126999$4887 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125393.5-125393.29" + attribute \src "libresoc.v:127000.5-127000.29" switch \initial - attribute \src "libresoc.v:125393.9-125393.17" + attribute \src "libresoc.v:127000.9-127000.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196816,18 +199236,18 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125403.3-125413.6" - process $proc$libresoc.v:125403$4847 + attribute \src "libresoc.v:127010.3-127020.6" + process $proc$libresoc.v:127010$4888 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125404.5-125404.29" + attribute \src "libresoc.v:127011.5-127011.29" switch \initial - attribute \src "libresoc.v:125404.9-125404.17" + attribute \src "libresoc.v:127011.9-127011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196839,18 +199259,18 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125414.3-125424.6" - process $proc$libresoc.v:125414$4848 + attribute \src "libresoc.v:127021.3-127031.6" + process $proc$libresoc.v:127021$4889 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125415.5-125415.29" + attribute \src "libresoc.v:127022.5-127022.29" switch \initial - attribute \src "libresoc.v:125415.9-125415.17" + attribute \src "libresoc.v:127022.9-127022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196862,139 +199282,139 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125255$4829_Y - connect \$11 $pos$libresoc.v:125256$4831_Y - connect \$14 $sshl$libresoc.v:125257$4832_Y - connect \$17 $sshl$libresoc.v:125258$4833_Y - connect \$1 $pos$libresoc.v:125259$4835_Y - connect \$20 $sshl$libresoc.v:125260$4836_Y - connect \$23 $sshl$libresoc.v:125261$4837_Y - connect \$4 $sshl$libresoc.v:125262$4838_Y - connect \$3 $pos$libresoc.v:125263$4840_Y + connect \$9 $pos$libresoc.v:126862$4870_Y + connect \$11 $pos$libresoc.v:126863$4872_Y + connect \$14 $sshl$libresoc.v:126864$4873_Y + connect \$17 $sshl$libresoc.v:126865$4874_Y + connect \$1 $pos$libresoc.v:126866$4876_Y + connect \$20 $sshl$libresoc.v:126867$4877_Y + connect \$23 $sshl$libresoc.v:126868$4878_Y + connect \$4 $sshl$libresoc.v:126869$4879_Y + connect \$3 $pos$libresoc.v:126870$4881_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125433.1-125686.10" +attribute \src "libresoc.v:127040.1-127293.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:125660.3-125670.6" + attribute \src "libresoc.v:127267.3-127277.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125671.3-125681.6" + attribute \src "libresoc.v:127278.3-127288.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125522.3-125568.6" + attribute \src "libresoc.v:127129.3-127175.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125569.3-125615.6" + attribute \src "libresoc.v:127176.3-127222.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125434.7-125434.20" + attribute \src "libresoc.v:127041.7-127041.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125649.3-125659.6" + attribute \src "libresoc.v:127256.3-127266.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125616.3-125626.6" + attribute \src "libresoc.v:127223.3-127233.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125627.3-125637.6" + attribute \src "libresoc.v:127234.3-127244.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125638.3-125648.6" + attribute \src "libresoc.v:127245.3-127255.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125660.3-125670.6" + attribute \src "libresoc.v:127267.3-127277.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125671.3-125681.6" + attribute \src "libresoc.v:127278.3-127288.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125522.3-125568.6" + attribute \src "libresoc.v:127129.3-127175.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125569.3-125615.6" + attribute \src "libresoc.v:127176.3-127222.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125649.3-125659.6" + attribute \src "libresoc.v:127256.3-127266.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125616.3-125626.6" + attribute \src "libresoc.v:127223.3-127233.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125627.3-125637.6" + attribute \src "libresoc.v:127234.3-127244.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125638.3-125648.6" + attribute \src "libresoc.v:127245.3-127255.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125512.17-125512.108" - wire width 64 $extend$libresoc.v:125512$4850_Y - attribute \src "libresoc.v:125513.18-125513.111" - wire width 64 $extend$libresoc.v:125513$4852_Y - attribute \src "libresoc.v:125516.17-125516.108" - wire width 64 $extend$libresoc.v:125516$4856_Y - attribute \src "libresoc.v:125520.17-125520.102" - wire width 64 $extend$libresoc.v:125520$4861_Y - attribute \src "libresoc.v:125512.17-125512.108" - wire width 64 $pos$libresoc.v:125512$4851_Y - attribute \src "libresoc.v:125513.18-125513.111" - wire width 64 $pos$libresoc.v:125513$4853_Y - attribute \src "libresoc.v:125516.17-125516.108" - wire width 64 $pos$libresoc.v:125516$4857_Y - attribute \src "libresoc.v:125520.17-125520.102" - wire width 64 $pos$libresoc.v:125520$4862_Y - attribute \src "libresoc.v:125514.18-125514.118" - wire width 47 $sshl$libresoc.v:125514$4854_Y - attribute \src "libresoc.v:125515.18-125515.117" - wire width 27 $sshl$libresoc.v:125515$4855_Y - attribute \src "libresoc.v:125517.18-125517.117" - wire width 17 $sshl$libresoc.v:125517$4858_Y - attribute \src "libresoc.v:125518.18-125518.117" - wire width 17 $sshl$libresoc.v:125518$4859_Y - attribute \src "libresoc.v:125519.17-125519.109" - wire width 47 $sshl$libresoc.v:125519$4860_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127119.17-127119.108" + wire width 64 $extend$libresoc.v:127119$4891_Y + attribute \src "libresoc.v:127120.18-127120.111" + wire width 64 $extend$libresoc.v:127120$4893_Y + attribute \src "libresoc.v:127123.17-127123.108" + wire width 64 $extend$libresoc.v:127123$4897_Y + attribute \src "libresoc.v:127127.17-127127.102" + wire width 64 $extend$libresoc.v:127127$4902_Y + attribute \src "libresoc.v:127119.17-127119.108" + wire width 64 $pos$libresoc.v:127119$4892_Y + attribute \src "libresoc.v:127120.18-127120.111" + wire width 64 $pos$libresoc.v:127120$4894_Y + attribute \src "libresoc.v:127123.17-127123.108" + wire width 64 $pos$libresoc.v:127123$4898_Y + attribute \src "libresoc.v:127127.17-127127.102" + wire width 64 $pos$libresoc.v:127127$4903_Y + attribute \src "libresoc.v:127121.18-127121.118" + wire width 47 $sshl$libresoc.v:127121$4895_Y + attribute \src "libresoc.v:127122.18-127122.117" + wire width 27 $sshl$libresoc.v:127122$4896_Y + attribute \src "libresoc.v:127124.18-127124.117" + wire width 17 $sshl$libresoc.v:127124$4899_Y + attribute \src "libresoc.v:127125.18-127125.117" + wire width 17 $sshl$libresoc.v:127125$4900_Y + attribute \src "libresoc.v:127126.17-127126.109" + wire width 47 $sshl$libresoc.v:127126$4901_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125434.7-125434.15" + attribute \src "libresoc.v:127041.7-127041.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -197011,80 +199431,80 @@ module \dec_bi$149 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125512$4850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127119$4891 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:125512$4850_Y + connect \Y $extend$libresoc.v:127119$4891_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125513$4852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127120$4893 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:125513$4852_Y + connect \Y $extend$libresoc.v:127120$4893_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125516$4856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127123$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:125516$4856_Y + connect \Y $extend$libresoc.v:127123$4897_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125520$4861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127127$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125520$4861_Y + connect \Y $extend$libresoc.v:127127$4902_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125512$4851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127119$4892 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125512$4850_Y - connect \Y $pos$libresoc.v:125512$4851_Y + connect \A $extend$libresoc.v:127119$4891_Y + connect \Y $pos$libresoc.v:127119$4892_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125513$4853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127120$4894 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125513$4852_Y - connect \Y $pos$libresoc.v:125513$4853_Y + connect \A $extend$libresoc.v:127120$4893_Y + connect \Y $pos$libresoc.v:127120$4894_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125516$4857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127123$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125516$4856_Y - connect \Y $pos$libresoc.v:125516$4857_Y + connect \A $extend$libresoc.v:127123$4897_Y + connect \Y $pos$libresoc.v:127123$4898_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125520$4862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127127$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125520$4861_Y - connect \Y $pos$libresoc.v:125520$4862_Y + connect \A $extend$libresoc.v:127127$4902_Y + connect \Y $pos$libresoc.v:127127$4903_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125514$4854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127121$4895 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197092,10 +199512,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125514$4854_Y + connect \Y $sshl$libresoc.v:127121$4895_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125515$4855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127122$4896 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -197103,10 +199523,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125515$4855_Y + connect \Y $sshl$libresoc.v:127122$4896_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125517$4858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127124$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197114,10 +199534,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125517$4858_Y + connect \Y $sshl$libresoc.v:127124$4899_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125518$4859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127125$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197125,10 +199545,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125518$4859_Y + connect \Y $sshl$libresoc.v:127125$4900_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125519$4860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127126$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197136,28 +199556,28 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125519$4860_Y + connect \Y $sshl$libresoc.v:127126$4901_Y end - attribute \src "libresoc.v:125434.7-125434.20" - process $proc$libresoc.v:125434$4871 + attribute \src "libresoc.v:127041.7-127041.20" + process $proc$libresoc.v:127041$4912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125522.3-125568.6" - process $proc$libresoc.v:125522$4863 + attribute \src "libresoc.v:127129.3-127175.6" + process $proc$libresoc.v:127129$4904 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125523.5-125523.29" + attribute \src "libresoc.v:127130.5-127130.29" switch \initial - attribute \src "libresoc.v:125523.9-125523.17" + attribute \src "libresoc.v:127130.9-127130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197205,18 +199625,18 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125569.3-125615.6" - process $proc$libresoc.v:125569$4864 + attribute \src "libresoc.v:127176.3-127222.6" + process $proc$libresoc.v:127176$4905 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125570.5-125570.29" + attribute \src "libresoc.v:127177.5-127177.29" switch \initial - attribute \src "libresoc.v:125570.9-125570.17" + attribute \src "libresoc.v:127177.9-127177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197264,18 +199684,18 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125616.3-125626.6" - process $proc$libresoc.v:125616$4865 + attribute \src "libresoc.v:127223.3-127233.6" + process $proc$libresoc.v:127223$4906 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125617.5-125617.29" + attribute \src "libresoc.v:127224.5-127224.29" switch \initial - attribute \src "libresoc.v:125617.9-125617.17" + attribute \src "libresoc.v:127224.9-127224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -197287,18 +199707,18 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125627.3-125637.6" - process $proc$libresoc.v:125627$4866 + attribute \src "libresoc.v:127234.3-127244.6" + process $proc$libresoc.v:127234$4907 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125628.5-125628.29" + attribute \src "libresoc.v:127235.5-127235.29" switch \initial - attribute \src "libresoc.v:125628.9-125628.17" + attribute \src "libresoc.v:127235.9-127235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -197310,18 +199730,18 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125638.3-125648.6" - process $proc$libresoc.v:125638$4867 + attribute \src "libresoc.v:127245.3-127255.6" + process $proc$libresoc.v:127245$4908 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125639.5-125639.29" + attribute \src "libresoc.v:127246.5-127246.29" switch \initial - attribute \src "libresoc.v:125639.9-125639.17" + attribute \src "libresoc.v:127246.9-127246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -197333,18 +199753,18 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125649.3-125659.6" - process $proc$libresoc.v:125649$4868 + attribute \src "libresoc.v:127256.3-127266.6" + process $proc$libresoc.v:127256$4909 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125650.5-125650.29" + attribute \src "libresoc.v:127257.5-127257.29" switch \initial - attribute \src "libresoc.v:125650.9-125650.17" + attribute \src "libresoc.v:127257.9-127257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -197356,18 +199776,18 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125660.3-125670.6" - process $proc$libresoc.v:125660$4869 + attribute \src "libresoc.v:127267.3-127277.6" + process $proc$libresoc.v:127267$4910 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125661.5-125661.29" + attribute \src "libresoc.v:127268.5-127268.29" switch \initial - attribute \src "libresoc.v:125661.9-125661.17" + attribute \src "libresoc.v:127268.9-127268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -197379,18 +199799,18 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125671.3-125681.6" - process $proc$libresoc.v:125671$4870 + attribute \src "libresoc.v:127278.3-127288.6" + process $proc$libresoc.v:127278$4911 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125672.5-125672.29" + attribute \src "libresoc.v:127279.5-127279.29" switch \initial - attribute \src "libresoc.v:125672.9-125672.17" + attribute \src "libresoc.v:127279.9-127279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -197402,139 +199822,139 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125512$4851_Y - connect \$11 $pos$libresoc.v:125513$4853_Y - connect \$14 $sshl$libresoc.v:125514$4854_Y - connect \$17 $sshl$libresoc.v:125515$4855_Y - connect \$1 $pos$libresoc.v:125516$4857_Y - connect \$20 $sshl$libresoc.v:125517$4858_Y - connect \$23 $sshl$libresoc.v:125518$4859_Y - connect \$4 $sshl$libresoc.v:125519$4860_Y - connect \$3 $pos$libresoc.v:125520$4862_Y + connect \$9 $pos$libresoc.v:127119$4892_Y + connect \$11 $pos$libresoc.v:127120$4894_Y + connect \$14 $sshl$libresoc.v:127121$4895_Y + connect \$17 $sshl$libresoc.v:127122$4896_Y + connect \$1 $pos$libresoc.v:127123$4898_Y + connect \$20 $sshl$libresoc.v:127124$4899_Y + connect \$23 $sshl$libresoc.v:127125$4900_Y + connect \$4 $sshl$libresoc.v:127126$4901_Y + connect \$3 $pos$libresoc.v:127127$4903_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125690.1-125943.10" +attribute \src "libresoc.v:127297.1-127550.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:125917.3-125927.6" + attribute \src "libresoc.v:127524.3-127534.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125928.3-125938.6" + attribute \src "libresoc.v:127535.3-127545.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125779.3-125825.6" + attribute \src "libresoc.v:127386.3-127432.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125826.3-125872.6" + attribute \src "libresoc.v:127433.3-127479.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125691.7-125691.20" + attribute \src "libresoc.v:127298.7-127298.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125906.3-125916.6" + attribute \src "libresoc.v:127513.3-127523.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125873.3-125883.6" + attribute \src "libresoc.v:127480.3-127490.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125884.3-125894.6" + attribute \src "libresoc.v:127491.3-127501.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125895.3-125905.6" + attribute \src "libresoc.v:127502.3-127512.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125917.3-125927.6" + attribute \src "libresoc.v:127524.3-127534.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125928.3-125938.6" + attribute \src "libresoc.v:127535.3-127545.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125779.3-125825.6" + attribute \src "libresoc.v:127386.3-127432.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125826.3-125872.6" + attribute \src "libresoc.v:127433.3-127479.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125906.3-125916.6" + attribute \src "libresoc.v:127513.3-127523.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125873.3-125883.6" + attribute \src "libresoc.v:127480.3-127490.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125884.3-125894.6" + attribute \src "libresoc.v:127491.3-127501.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125895.3-125905.6" + attribute \src "libresoc.v:127502.3-127512.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125769.17-125769.104" - wire width 64 $extend$libresoc.v:125769$4872_Y - attribute \src "libresoc.v:125770.18-125770.107" - wire width 64 $extend$libresoc.v:125770$4874_Y - attribute \src "libresoc.v:125773.17-125773.104" - wire width 64 $extend$libresoc.v:125773$4878_Y - attribute \src "libresoc.v:125777.17-125777.102" - wire width 64 $extend$libresoc.v:125777$4883_Y - attribute \src "libresoc.v:125769.17-125769.104" - wire width 64 $pos$libresoc.v:125769$4873_Y - attribute \src "libresoc.v:125770.18-125770.107" - wire width 64 $pos$libresoc.v:125770$4875_Y - attribute \src "libresoc.v:125773.17-125773.104" - wire width 64 $pos$libresoc.v:125773$4879_Y - attribute \src "libresoc.v:125777.17-125777.102" - wire width 64 $pos$libresoc.v:125777$4884_Y - attribute \src "libresoc.v:125771.18-125771.114" - wire width 47 $sshl$libresoc.v:125771$4876_Y - attribute \src "libresoc.v:125772.18-125772.113" - wire width 27 $sshl$libresoc.v:125772$4877_Y - attribute \src "libresoc.v:125774.18-125774.113" - wire width 17 $sshl$libresoc.v:125774$4880_Y - attribute \src "libresoc.v:125775.18-125775.113" - wire width 17 $sshl$libresoc.v:125775$4881_Y - attribute \src "libresoc.v:125776.17-125776.109" - wire width 47 $sshl$libresoc.v:125776$4882_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $extend$libresoc.v:127376$4913_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $extend$libresoc.v:127377$4915_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $extend$libresoc.v:127380$4919_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $extend$libresoc.v:127384$4924_Y + attribute \src "libresoc.v:127376.17-127376.104" + wire width 64 $pos$libresoc.v:127376$4914_Y + attribute \src "libresoc.v:127377.18-127377.107" + wire width 64 $pos$libresoc.v:127377$4916_Y + attribute \src "libresoc.v:127380.17-127380.104" + wire width 64 $pos$libresoc.v:127380$4920_Y + attribute \src "libresoc.v:127384.17-127384.102" + wire width 64 $pos$libresoc.v:127384$4925_Y + attribute \src "libresoc.v:127378.18-127378.114" + wire width 47 $sshl$libresoc.v:127378$4917_Y + attribute \src "libresoc.v:127379.18-127379.113" + wire width 27 $sshl$libresoc.v:127379$4918_Y + attribute \src "libresoc.v:127381.18-127381.113" + wire width 17 $sshl$libresoc.v:127381$4921_Y + attribute \src "libresoc.v:127382.18-127382.113" + wire width 17 $sshl$libresoc.v:127382$4922_Y + attribute \src "libresoc.v:127383.17-127383.109" + wire width 47 $sshl$libresoc.v:127383$4923_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125691.7-125691.15" + attribute \src "libresoc.v:127298.7-127298.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -197551,80 +199971,80 @@ module \dec_bi$157 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125769$4872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127376$4913 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:125769$4872_Y + connect \Y $extend$libresoc.v:127376$4913_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125770$4874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127377$4915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:125770$4874_Y + connect \Y $extend$libresoc.v:127377$4915_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125773$4878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127380$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:125773$4878_Y + connect \Y $extend$libresoc.v:127380$4919_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:125777$4883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127384$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125777$4883_Y + connect \Y $extend$libresoc.v:127384$4924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125769$4873 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127376$4914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125769$4872_Y - connect \Y $pos$libresoc.v:125769$4873_Y + connect \A $extend$libresoc.v:127376$4913_Y + connect \Y $pos$libresoc.v:127376$4914_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125770$4875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127377$4916 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125770$4874_Y - connect \Y $pos$libresoc.v:125770$4875_Y + connect \A $extend$libresoc.v:127377$4915_Y + connect \Y $pos$libresoc.v:127377$4916_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125773$4879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127380$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125773$4878_Y - connect \Y $pos$libresoc.v:125773$4879_Y + connect \A $extend$libresoc.v:127380$4919_Y + connect \Y $pos$libresoc.v:127380$4920_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:125777$4884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127384$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125777$4883_Y - connect \Y $pos$libresoc.v:125777$4884_Y + connect \A $extend$libresoc.v:127384$4924_Y + connect \Y $pos$libresoc.v:127384$4925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:125771$4876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127378$4917 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197632,10 +200052,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125771$4876_Y + connect \Y $sshl$libresoc.v:127378$4917_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:125772$4877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127379$4918 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -197643,10 +200063,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125772$4877_Y + connect \Y $sshl$libresoc.v:127379$4918_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:125774$4880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127381$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197654,10 +200074,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125774$4880_Y + connect \Y $sshl$libresoc.v:127381$4921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:125775$4881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127382$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -197665,10 +200085,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125775$4881_Y + connect \Y $sshl$libresoc.v:127382$4922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:125776$4882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127383$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -197676,28 +200096,28 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125776$4882_Y + connect \Y $sshl$libresoc.v:127383$4923_Y end - attribute \src "libresoc.v:125691.7-125691.20" - process $proc$libresoc.v:125691$4893 + attribute \src "libresoc.v:127298.7-127298.20" + process $proc$libresoc.v:127298$4934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125779.3-125825.6" - process $proc$libresoc.v:125779$4885 + attribute \src "libresoc.v:127386.3-127432.6" + process $proc$libresoc.v:127386$4926 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125780.5-125780.29" + attribute \src "libresoc.v:127387.5-127387.29" switch \initial - attribute \src "libresoc.v:125780.9-125780.17" + attribute \src "libresoc.v:127387.9-127387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197745,18 +200165,18 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125826.3-125872.6" - process $proc$libresoc.v:125826$4886 + attribute \src "libresoc.v:127433.3-127479.6" + process $proc$libresoc.v:127433$4927 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125827.5-125827.29" + attribute \src "libresoc.v:127434.5-127434.29" switch \initial - attribute \src "libresoc.v:125827.9-125827.17" + attribute \src "libresoc.v:127434.9-127434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -197804,18 +200224,18 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125873.3-125883.6" - process $proc$libresoc.v:125873$4887 + attribute \src "libresoc.v:127480.3-127490.6" + process $proc$libresoc.v:127480$4928 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125874.5-125874.29" + attribute \src "libresoc.v:127481.5-127481.29" switch \initial - attribute \src "libresoc.v:125874.9-125874.17" + attribute \src "libresoc.v:127481.9-127481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -197827,18 +200247,18 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125884.3-125894.6" - process $proc$libresoc.v:125884$4888 + attribute \src "libresoc.v:127491.3-127501.6" + process $proc$libresoc.v:127491$4929 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125885.5-125885.29" + attribute \src "libresoc.v:127492.5-127492.29" switch \initial - attribute \src "libresoc.v:125885.9-125885.17" + attribute \src "libresoc.v:127492.9-127492.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -197850,18 +200270,18 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125895.3-125905.6" - process $proc$libresoc.v:125895$4889 + attribute \src "libresoc.v:127502.3-127512.6" + process $proc$libresoc.v:127502$4930 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125896.5-125896.29" + attribute \src "libresoc.v:127503.5-127503.29" switch \initial - attribute \src "libresoc.v:125896.9-125896.17" + attribute \src "libresoc.v:127503.9-127503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -197873,18 +200293,18 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125906.3-125916.6" - process $proc$libresoc.v:125906$4890 + attribute \src "libresoc.v:127513.3-127523.6" + process $proc$libresoc.v:127513$4931 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125907.5-125907.29" + attribute \src "libresoc.v:127514.5-127514.29" switch \initial - attribute \src "libresoc.v:125907.9-125907.17" + attribute \src "libresoc.v:127514.9-127514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -197896,18 +200316,18 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125917.3-125927.6" - process $proc$libresoc.v:125917$4891 + attribute \src "libresoc.v:127524.3-127534.6" + process $proc$libresoc.v:127524$4932 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125918.5-125918.29" + attribute \src "libresoc.v:127525.5-127525.29" switch \initial - attribute \src "libresoc.v:125918.9-125918.17" + attribute \src "libresoc.v:127525.9-127525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -197919,18 +200339,18 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125928.3-125938.6" - process $proc$libresoc.v:125928$4892 + attribute \src "libresoc.v:127535.3-127545.6" + process $proc$libresoc.v:127535$4933 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125929.5-125929.29" + attribute \src "libresoc.v:127536.5-127536.29" switch \initial - attribute \src "libresoc.v:125929.9-125929.17" + attribute \src "libresoc.v:127536.9-127536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -197942,139 +200362,139 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125769$4873_Y - connect \$11 $pos$libresoc.v:125770$4875_Y - connect \$14 $sshl$libresoc.v:125771$4876_Y - connect \$17 $sshl$libresoc.v:125772$4877_Y - connect \$1 $pos$libresoc.v:125773$4879_Y - connect \$20 $sshl$libresoc.v:125774$4880_Y - connect \$23 $sshl$libresoc.v:125775$4881_Y - connect \$4 $sshl$libresoc.v:125776$4882_Y - connect \$3 $pos$libresoc.v:125777$4884_Y + connect \$9 $pos$libresoc.v:127376$4914_Y + connect \$11 $pos$libresoc.v:127377$4916_Y + connect \$14 $sshl$libresoc.v:127378$4917_Y + connect \$17 $sshl$libresoc.v:127379$4918_Y + connect \$1 $pos$libresoc.v:127380$4920_Y + connect \$20 $sshl$libresoc.v:127381$4921_Y + connect \$23 $sshl$libresoc.v:127382$4922_Y + connect \$4 $sshl$libresoc.v:127383$4923_Y + connect \$3 $pos$libresoc.v:127384$4925_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125947.1-126200.10" +attribute \src "libresoc.v:127554.1-127807.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:126174.3-126184.6" + attribute \src "libresoc.v:127781.3-127791.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126185.3-126195.6" + attribute \src "libresoc.v:127792.3-127802.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126036.3-126082.6" + attribute \src "libresoc.v:127643.3-127689.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126083.3-126129.6" + attribute \src "libresoc.v:127690.3-127736.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125948.7-125948.20" + attribute \src "libresoc.v:127555.7-127555.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126163.3-126173.6" + attribute \src "libresoc.v:127770.3-127780.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126130.3-126140.6" + attribute \src "libresoc.v:127737.3-127747.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126141.3-126151.6" + attribute \src "libresoc.v:127748.3-127758.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126152.3-126162.6" + attribute \src "libresoc.v:127759.3-127769.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126174.3-126184.6" + attribute \src "libresoc.v:127781.3-127791.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126185.3-126195.6" + attribute \src "libresoc.v:127792.3-127802.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126036.3-126082.6" + attribute \src "libresoc.v:127643.3-127689.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126083.3-126129.6" + attribute \src "libresoc.v:127690.3-127736.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126163.3-126173.6" + attribute \src "libresoc.v:127770.3-127780.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126130.3-126140.6" + attribute \src "libresoc.v:127737.3-127747.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126141.3-126151.6" + attribute \src "libresoc.v:127748.3-127758.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126152.3-126162.6" + attribute \src "libresoc.v:127759.3-127769.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126026.17-126026.104" - wire width 64 $extend$libresoc.v:126026$4894_Y - attribute \src "libresoc.v:126027.18-126027.107" - wire width 64 $extend$libresoc.v:126027$4896_Y - attribute \src "libresoc.v:126030.17-126030.104" - wire width 64 $extend$libresoc.v:126030$4900_Y - attribute \src "libresoc.v:126034.17-126034.102" - wire width 64 $extend$libresoc.v:126034$4905_Y - attribute \src "libresoc.v:126026.17-126026.104" - wire width 64 $pos$libresoc.v:126026$4895_Y - attribute \src "libresoc.v:126027.18-126027.107" - wire width 64 $pos$libresoc.v:126027$4897_Y - attribute \src "libresoc.v:126030.17-126030.104" - wire width 64 $pos$libresoc.v:126030$4901_Y - attribute \src "libresoc.v:126034.17-126034.102" - wire width 64 $pos$libresoc.v:126034$4906_Y - attribute \src "libresoc.v:126028.18-126028.114" - wire width 47 $sshl$libresoc.v:126028$4898_Y - attribute \src "libresoc.v:126029.18-126029.113" - wire width 27 $sshl$libresoc.v:126029$4899_Y - attribute \src "libresoc.v:126031.18-126031.113" - wire width 17 $sshl$libresoc.v:126031$4902_Y - attribute \src "libresoc.v:126032.18-126032.113" - wire width 17 $sshl$libresoc.v:126032$4903_Y - attribute \src "libresoc.v:126033.17-126033.109" - wire width 47 $sshl$libresoc.v:126033$4904_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $extend$libresoc.v:127633$4935_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $extend$libresoc.v:127634$4937_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $extend$libresoc.v:127637$4941_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $extend$libresoc.v:127641$4946_Y + attribute \src "libresoc.v:127633.17-127633.104" + wire width 64 $pos$libresoc.v:127633$4936_Y + attribute \src "libresoc.v:127634.18-127634.107" + wire width 64 $pos$libresoc.v:127634$4938_Y + attribute \src "libresoc.v:127637.17-127637.104" + wire width 64 $pos$libresoc.v:127637$4942_Y + attribute \src "libresoc.v:127641.17-127641.102" + wire width 64 $pos$libresoc.v:127641$4947_Y + attribute \src "libresoc.v:127635.18-127635.114" + wire width 47 $sshl$libresoc.v:127635$4939_Y + attribute \src "libresoc.v:127636.18-127636.113" + wire width 27 $sshl$libresoc.v:127636$4940_Y + attribute \src "libresoc.v:127638.18-127638.113" + wire width 17 $sshl$libresoc.v:127638$4943_Y + attribute \src "libresoc.v:127639.18-127639.113" + wire width 17 $sshl$libresoc.v:127639$4944_Y + attribute \src "libresoc.v:127640.17-127640.109" + wire width 47 $sshl$libresoc.v:127640$4945_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125948.7-125948.15" + attribute \src "libresoc.v:127555.7-127555.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198091,80 +200511,80 @@ module \dec_bi$161 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126026$4894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127633$4935 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:126026$4894_Y + connect \Y $extend$libresoc.v:127633$4935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126027$4896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127634$4937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:126027$4896_Y + connect \Y $extend$libresoc.v:127634$4937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126030$4900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127637$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:126030$4900_Y + connect \Y $extend$libresoc.v:127637$4941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126034$4905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127641$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126034$4905_Y + connect \Y $extend$libresoc.v:127641$4946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126026$4895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127633$4936 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126026$4894_Y - connect \Y $pos$libresoc.v:126026$4895_Y + connect \A $extend$libresoc.v:127633$4935_Y + connect \Y $pos$libresoc.v:127633$4936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126027$4897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127634$4938 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126027$4896_Y - connect \Y $pos$libresoc.v:126027$4897_Y + connect \A $extend$libresoc.v:127634$4937_Y + connect \Y $pos$libresoc.v:127634$4938_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126030$4901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127637$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126030$4900_Y - connect \Y $pos$libresoc.v:126030$4901_Y + connect \A $extend$libresoc.v:127637$4941_Y + connect \Y $pos$libresoc.v:127637$4942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126034$4906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127641$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126034$4905_Y - connect \Y $pos$libresoc.v:126034$4906_Y + connect \A $extend$libresoc.v:127641$4946_Y + connect \Y $pos$libresoc.v:127641$4947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126028$4898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127635$4939 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198172,10 +200592,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126028$4898_Y + connect \Y $sshl$libresoc.v:127635$4939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126029$4899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127636$4940 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198183,10 +200603,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126029$4899_Y + connect \Y $sshl$libresoc.v:127636$4940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126031$4902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127638$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198194,10 +200614,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126031$4902_Y + connect \Y $sshl$libresoc.v:127638$4943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126032$4903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127639$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198205,10 +200625,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126032$4903_Y + connect \Y $sshl$libresoc.v:127639$4944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126033$4904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127640$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198216,28 +200636,28 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126033$4904_Y + connect \Y $sshl$libresoc.v:127640$4945_Y end - attribute \src "libresoc.v:125948.7-125948.20" - process $proc$libresoc.v:125948$4915 + attribute \src "libresoc.v:127555.7-127555.20" + process $proc$libresoc.v:127555$4956 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126036.3-126082.6" - process $proc$libresoc.v:126036$4907 + attribute \src "libresoc.v:127643.3-127689.6" + process $proc$libresoc.v:127643$4948 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126037.5-126037.29" + attribute \src "libresoc.v:127644.5-127644.29" switch \initial - attribute \src "libresoc.v:126037.9-126037.17" + attribute \src "libresoc.v:127644.9-127644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198285,18 +200705,18 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126083.3-126129.6" - process $proc$libresoc.v:126083$4908 + attribute \src "libresoc.v:127690.3-127736.6" + process $proc$libresoc.v:127690$4949 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126084.5-126084.29" + attribute \src "libresoc.v:127691.5-127691.29" switch \initial - attribute \src "libresoc.v:126084.9-126084.17" + attribute \src "libresoc.v:127691.9-127691.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198344,18 +200764,18 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126130.3-126140.6" - process $proc$libresoc.v:126130$4909 + attribute \src "libresoc.v:127737.3-127747.6" + process $proc$libresoc.v:127737$4950 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126131.5-126131.29" + attribute \src "libresoc.v:127738.5-127738.29" switch \initial - attribute \src "libresoc.v:126131.9-126131.17" + attribute \src "libresoc.v:127738.9-127738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -198367,18 +200787,18 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126141.3-126151.6" - process $proc$libresoc.v:126141$4910 + attribute \src "libresoc.v:127748.3-127758.6" + process $proc$libresoc.v:127748$4951 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126142.5-126142.29" + attribute \src "libresoc.v:127749.5-127749.29" switch \initial - attribute \src "libresoc.v:126142.9-126142.17" + attribute \src "libresoc.v:127749.9-127749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -198390,18 +200810,18 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126152.3-126162.6" - process $proc$libresoc.v:126152$4911 + attribute \src "libresoc.v:127759.3-127769.6" + process $proc$libresoc.v:127759$4952 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126153.5-126153.29" + attribute \src "libresoc.v:127760.5-127760.29" switch \initial - attribute \src "libresoc.v:126153.9-126153.17" + attribute \src "libresoc.v:127760.9-127760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -198413,18 +200833,18 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126163.3-126173.6" - process $proc$libresoc.v:126163$4912 + attribute \src "libresoc.v:127770.3-127780.6" + process $proc$libresoc.v:127770$4953 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126164.5-126164.29" + attribute \src "libresoc.v:127771.5-127771.29" switch \initial - attribute \src "libresoc.v:126164.9-126164.17" + attribute \src "libresoc.v:127771.9-127771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -198436,18 +200856,18 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126174.3-126184.6" - process $proc$libresoc.v:126174$4913 + attribute \src "libresoc.v:127781.3-127791.6" + process $proc$libresoc.v:127781$4954 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126175.5-126175.29" + attribute \src "libresoc.v:127782.5-127782.29" switch \initial - attribute \src "libresoc.v:126175.9-126175.17" + attribute \src "libresoc.v:127782.9-127782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -198459,18 +200879,18 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126185.3-126195.6" - process $proc$libresoc.v:126185$4914 + attribute \src "libresoc.v:127792.3-127802.6" + process $proc$libresoc.v:127792$4955 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126186.5-126186.29" + attribute \src "libresoc.v:127793.5-127793.29" switch \initial - attribute \src "libresoc.v:126186.9-126186.17" + attribute \src "libresoc.v:127793.9-127793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -198482,139 +200902,139 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126026$4895_Y - connect \$11 $pos$libresoc.v:126027$4897_Y - connect \$14 $sshl$libresoc.v:126028$4898_Y - connect \$17 $sshl$libresoc.v:126029$4899_Y - connect \$1 $pos$libresoc.v:126030$4901_Y - connect \$20 $sshl$libresoc.v:126031$4902_Y - connect \$23 $sshl$libresoc.v:126032$4903_Y - connect \$4 $sshl$libresoc.v:126033$4904_Y - connect \$3 $pos$libresoc.v:126034$4906_Y + connect \$9 $pos$libresoc.v:127633$4936_Y + connect \$11 $pos$libresoc.v:127634$4938_Y + connect \$14 $sshl$libresoc.v:127635$4939_Y + connect \$17 $sshl$libresoc.v:127636$4940_Y + connect \$1 $pos$libresoc.v:127637$4942_Y + connect \$20 $sshl$libresoc.v:127638$4943_Y + connect \$23 $sshl$libresoc.v:127639$4944_Y + connect \$4 $sshl$libresoc.v:127640$4945_Y + connect \$3 $pos$libresoc.v:127641$4947_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126204.1-126457.10" +attribute \src "libresoc.v:127811.1-128064.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:126431.3-126441.6" + attribute \src "libresoc.v:128038.3-128048.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126442.3-126452.6" + attribute \src "libresoc.v:128049.3-128059.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126293.3-126339.6" + attribute \src "libresoc.v:127900.3-127946.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126340.3-126386.6" + attribute \src "libresoc.v:127947.3-127993.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126205.7-126205.20" + attribute \src "libresoc.v:127812.7-127812.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126420.3-126430.6" + attribute \src "libresoc.v:128027.3-128037.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126387.3-126397.6" + attribute \src "libresoc.v:127994.3-128004.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126398.3-126408.6" + attribute \src "libresoc.v:128005.3-128015.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126409.3-126419.6" + attribute \src "libresoc.v:128016.3-128026.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126431.3-126441.6" + attribute \src "libresoc.v:128038.3-128048.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126442.3-126452.6" + attribute \src "libresoc.v:128049.3-128059.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126293.3-126339.6" + attribute \src "libresoc.v:127900.3-127946.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126340.3-126386.6" + attribute \src "libresoc.v:127947.3-127993.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126420.3-126430.6" + attribute \src "libresoc.v:128027.3-128037.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126387.3-126397.6" + attribute \src "libresoc.v:127994.3-128004.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126398.3-126408.6" + attribute \src "libresoc.v:128005.3-128015.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126409.3-126419.6" + attribute \src "libresoc.v:128016.3-128026.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126283.17-126283.110" - wire width 64 $extend$libresoc.v:126283$4916_Y - attribute \src "libresoc.v:126284.18-126284.113" - wire width 64 $extend$libresoc.v:126284$4918_Y - attribute \src "libresoc.v:126287.17-126287.110" - wire width 64 $extend$libresoc.v:126287$4922_Y - attribute \src "libresoc.v:126291.17-126291.102" - wire width 64 $extend$libresoc.v:126291$4927_Y - attribute \src "libresoc.v:126283.17-126283.110" - wire width 64 $pos$libresoc.v:126283$4917_Y - attribute \src "libresoc.v:126284.18-126284.113" - wire width 64 $pos$libresoc.v:126284$4919_Y - attribute \src "libresoc.v:126287.17-126287.110" - wire width 64 $pos$libresoc.v:126287$4923_Y - attribute \src "libresoc.v:126291.17-126291.102" - wire width 64 $pos$libresoc.v:126291$4928_Y - attribute \src "libresoc.v:126285.18-126285.120" - wire width 47 $sshl$libresoc.v:126285$4920_Y - attribute \src "libresoc.v:126286.18-126286.119" - wire width 27 $sshl$libresoc.v:126286$4921_Y - attribute \src "libresoc.v:126288.18-126288.119" - wire width 17 $sshl$libresoc.v:126288$4924_Y - attribute \src "libresoc.v:126289.18-126289.119" - wire width 17 $sshl$libresoc.v:126289$4925_Y - attribute \src "libresoc.v:126290.17-126290.109" - wire width 47 $sshl$libresoc.v:126290$4926_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $extend$libresoc.v:127890$4957_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $extend$libresoc.v:127891$4959_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $extend$libresoc.v:127894$4963_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $extend$libresoc.v:127898$4968_Y + attribute \src "libresoc.v:127890.17-127890.110" + wire width 64 $pos$libresoc.v:127890$4958_Y + attribute \src "libresoc.v:127891.18-127891.113" + wire width 64 $pos$libresoc.v:127891$4960_Y + attribute \src "libresoc.v:127894.17-127894.110" + wire width 64 $pos$libresoc.v:127894$4964_Y + attribute \src "libresoc.v:127898.17-127898.102" + wire width 64 $pos$libresoc.v:127898$4969_Y + attribute \src "libresoc.v:127892.18-127892.120" + wire width 47 $sshl$libresoc.v:127892$4961_Y + attribute \src "libresoc.v:127893.18-127893.119" + wire width 27 $sshl$libresoc.v:127893$4962_Y + attribute \src "libresoc.v:127895.18-127895.119" + wire width 17 $sshl$libresoc.v:127895$4965_Y + attribute \src "libresoc.v:127896.18-127896.119" + wire width 17 $sshl$libresoc.v:127896$4966_Y + attribute \src "libresoc.v:127897.17-127897.109" + wire width 47 $sshl$libresoc.v:127897$4967_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126205.7-126205.15" + attribute \src "libresoc.v:127812.7-127812.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -198631,80 +201051,80 @@ module \dec_bi$165 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126283$4916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127890$4957 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:126283$4916_Y + connect \Y $extend$libresoc.v:127890$4957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126284$4918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127891$4959 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:126284$4918_Y + connect \Y $extend$libresoc.v:127891$4959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126287$4922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:127894$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:126287$4922_Y + connect \Y $extend$libresoc.v:127894$4963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126291$4927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:127898$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126291$4927_Y + connect \Y $extend$libresoc.v:127898$4968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126283$4917 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127890$4958 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126283$4916_Y - connect \Y $pos$libresoc.v:126283$4917_Y + connect \A $extend$libresoc.v:127890$4957_Y + connect \Y $pos$libresoc.v:127890$4958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126284$4919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127891$4960 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126284$4918_Y - connect \Y $pos$libresoc.v:126284$4919_Y + connect \A $extend$libresoc.v:127891$4959_Y + connect \Y $pos$libresoc.v:127891$4960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126287$4923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:127894$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126287$4922_Y - connect \Y $pos$libresoc.v:126287$4923_Y + connect \A $extend$libresoc.v:127894$4963_Y + connect \Y $pos$libresoc.v:127894$4964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126291$4928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:127898$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126291$4927_Y - connect \Y $pos$libresoc.v:126291$4928_Y + connect \A $extend$libresoc.v:127898$4968_Y + connect \Y $pos$libresoc.v:127898$4969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126285$4920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:127892$4961 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198712,10 +201132,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126285$4920_Y + connect \Y $sshl$libresoc.v:127892$4961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126286$4921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:127893$4962 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198723,10 +201143,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126286$4921_Y + connect \Y $sshl$libresoc.v:127893$4962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126288$4924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:127895$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198734,10 +201154,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126288$4924_Y + connect \Y $sshl$libresoc.v:127895$4965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126289$4925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:127896$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198745,10 +201165,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126289$4925_Y + connect \Y $sshl$libresoc.v:127896$4966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126290$4926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:127897$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198756,28 +201176,28 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126290$4926_Y + connect \Y $sshl$libresoc.v:127897$4967_Y end - attribute \src "libresoc.v:126205.7-126205.20" - process $proc$libresoc.v:126205$4937 + attribute \src "libresoc.v:127812.7-127812.20" + process $proc$libresoc.v:127812$4978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126293.3-126339.6" - process $proc$libresoc.v:126293$4929 + attribute \src "libresoc.v:127900.3-127946.6" + process $proc$libresoc.v:127900$4970 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126294.5-126294.29" + attribute \src "libresoc.v:127901.5-127901.29" switch \initial - attribute \src "libresoc.v:126294.9-126294.17" + attribute \src "libresoc.v:127901.9-127901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198825,18 +201245,18 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126340.3-126386.6" - process $proc$libresoc.v:126340$4930 + attribute \src "libresoc.v:127947.3-127993.6" + process $proc$libresoc.v:127947$4971 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126341.5-126341.29" + attribute \src "libresoc.v:127948.5-127948.29" switch \initial - attribute \src "libresoc.v:126341.9-126341.17" + attribute \src "libresoc.v:127948.9-127948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -198884,18 +201304,18 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126387.3-126397.6" - process $proc$libresoc.v:126387$4931 + attribute \src "libresoc.v:127994.3-128004.6" + process $proc$libresoc.v:127994$4972 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126388.5-126388.29" + attribute \src "libresoc.v:127995.5-127995.29" switch \initial - attribute \src "libresoc.v:126388.9-126388.17" + attribute \src "libresoc.v:127995.9-127995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -198907,18 +201327,18 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126398.3-126408.6" - process $proc$libresoc.v:126398$4932 + attribute \src "libresoc.v:128005.3-128015.6" + process $proc$libresoc.v:128005$4973 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126399.5-126399.29" + attribute \src "libresoc.v:128006.5-128006.29" switch \initial - attribute \src "libresoc.v:126399.9-126399.17" + attribute \src "libresoc.v:128006.9-128006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -198930,18 +201350,18 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126409.3-126419.6" - process $proc$libresoc.v:126409$4933 + attribute \src "libresoc.v:128016.3-128026.6" + process $proc$libresoc.v:128016$4974 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126410.5-126410.29" + attribute \src "libresoc.v:128017.5-128017.29" switch \initial - attribute \src "libresoc.v:126410.9-126410.17" + attribute \src "libresoc.v:128017.9-128017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -198953,18 +201373,18 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126420.3-126430.6" - process $proc$libresoc.v:126420$4934 + attribute \src "libresoc.v:128027.3-128037.6" + process $proc$libresoc.v:128027$4975 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126421.5-126421.29" + attribute \src "libresoc.v:128028.5-128028.29" switch \initial - attribute \src "libresoc.v:126421.9-126421.17" + attribute \src "libresoc.v:128028.9-128028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -198976,18 +201396,18 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126431.3-126441.6" - process $proc$libresoc.v:126431$4935 + attribute \src "libresoc.v:128038.3-128048.6" + process $proc$libresoc.v:128038$4976 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126432.5-126432.29" + attribute \src "libresoc.v:128039.5-128039.29" switch \initial - attribute \src "libresoc.v:126432.9-126432.17" + attribute \src "libresoc.v:128039.9-128039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -198999,18 +201419,18 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126442.3-126452.6" - process $proc$libresoc.v:126442$4936 + attribute \src "libresoc.v:128049.3-128059.6" + process $proc$libresoc.v:128049$4977 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126443.5-126443.29" + attribute \src "libresoc.v:128050.5-128050.29" switch \initial - attribute \src "libresoc.v:126443.9-126443.17" + attribute \src "libresoc.v:128050.9-128050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -199022,139 +201442,139 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126283$4917_Y - connect \$11 $pos$libresoc.v:126284$4919_Y - connect \$14 $sshl$libresoc.v:126285$4920_Y - connect \$17 $sshl$libresoc.v:126286$4921_Y - connect \$1 $pos$libresoc.v:126287$4923_Y - connect \$20 $sshl$libresoc.v:126288$4924_Y - connect \$23 $sshl$libresoc.v:126289$4925_Y - connect \$4 $sshl$libresoc.v:126290$4926_Y - connect \$3 $pos$libresoc.v:126291$4928_Y + connect \$9 $pos$libresoc.v:127890$4958_Y + connect \$11 $pos$libresoc.v:127891$4960_Y + connect \$14 $sshl$libresoc.v:127892$4961_Y + connect \$17 $sshl$libresoc.v:127893$4962_Y + connect \$1 $pos$libresoc.v:127894$4964_Y + connect \$20 $sshl$libresoc.v:127895$4965_Y + connect \$23 $sshl$libresoc.v:127896$4966_Y + connect \$4 $sshl$libresoc.v:127897$4967_Y + connect \$3 $pos$libresoc.v:127898$4969_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126461.1-126714.10" +attribute \src "libresoc.v:128068.1-128321.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:126688.3-126698.6" + attribute \src "libresoc.v:128295.3-128305.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126699.3-126709.6" + attribute \src "libresoc.v:128306.3-128316.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126550.3-126596.6" + attribute \src "libresoc.v:128157.3-128203.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126597.3-126643.6" + attribute \src "libresoc.v:128204.3-128250.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126462.7-126462.20" + attribute \src "libresoc.v:128069.7-128069.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126677.3-126687.6" + attribute \src "libresoc.v:128284.3-128294.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126644.3-126654.6" + attribute \src "libresoc.v:128251.3-128261.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126655.3-126665.6" + attribute \src "libresoc.v:128262.3-128272.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126666.3-126676.6" + attribute \src "libresoc.v:128273.3-128283.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126688.3-126698.6" + attribute \src "libresoc.v:128295.3-128305.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126699.3-126709.6" + attribute \src "libresoc.v:128306.3-128316.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126550.3-126596.6" + attribute \src "libresoc.v:128157.3-128203.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126597.3-126643.6" + attribute \src "libresoc.v:128204.3-128250.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126677.3-126687.6" + attribute \src "libresoc.v:128284.3-128294.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126644.3-126654.6" + attribute \src "libresoc.v:128251.3-128261.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126655.3-126665.6" + attribute \src "libresoc.v:128262.3-128272.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126666.3-126676.6" + attribute \src "libresoc.v:128273.3-128283.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126540.17-126540.105" - wire width 64 $extend$libresoc.v:126540$4938_Y - attribute \src "libresoc.v:126541.18-126541.108" - wire width 64 $extend$libresoc.v:126541$4940_Y - attribute \src "libresoc.v:126544.17-126544.105" - wire width 64 $extend$libresoc.v:126544$4944_Y - attribute \src "libresoc.v:126548.17-126548.102" - wire width 64 $extend$libresoc.v:126548$4949_Y - attribute \src "libresoc.v:126540.17-126540.105" - wire width 64 $pos$libresoc.v:126540$4939_Y - attribute \src "libresoc.v:126541.18-126541.108" - wire width 64 $pos$libresoc.v:126541$4941_Y - attribute \src "libresoc.v:126544.17-126544.105" - wire width 64 $pos$libresoc.v:126544$4945_Y - attribute \src "libresoc.v:126548.17-126548.102" - wire width 64 $pos$libresoc.v:126548$4950_Y - attribute \src "libresoc.v:126542.18-126542.115" - wire width 47 $sshl$libresoc.v:126542$4942_Y - attribute \src "libresoc.v:126543.18-126543.114" - wire width 27 $sshl$libresoc.v:126543$4943_Y - attribute \src "libresoc.v:126545.18-126545.114" - wire width 17 $sshl$libresoc.v:126545$4946_Y - attribute \src "libresoc.v:126546.18-126546.114" - wire width 17 $sshl$libresoc.v:126546$4947_Y - attribute \src "libresoc.v:126547.17-126547.109" - wire width 47 $sshl$libresoc.v:126547$4948_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $extend$libresoc.v:128147$4979_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $extend$libresoc.v:128148$4981_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $extend$libresoc.v:128151$4985_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $extend$libresoc.v:128155$4990_Y + attribute \src "libresoc.v:128147.17-128147.105" + wire width 64 $pos$libresoc.v:128147$4980_Y + attribute \src "libresoc.v:128148.18-128148.108" + wire width 64 $pos$libresoc.v:128148$4982_Y + attribute \src "libresoc.v:128151.17-128151.105" + wire width 64 $pos$libresoc.v:128151$4986_Y + attribute \src "libresoc.v:128155.17-128155.102" + wire width 64 $pos$libresoc.v:128155$4991_Y + attribute \src "libresoc.v:128149.18-128149.115" + wire width 47 $sshl$libresoc.v:128149$4983_Y + attribute \src "libresoc.v:128150.18-128150.114" + wire width 27 $sshl$libresoc.v:128150$4984_Y + attribute \src "libresoc.v:128152.18-128152.114" + wire width 17 $sshl$libresoc.v:128152$4987_Y + attribute \src "libresoc.v:128153.18-128153.114" + wire width 17 $sshl$libresoc.v:128153$4988_Y + attribute \src "libresoc.v:128154.17-128154.109" + wire width 47 $sshl$libresoc.v:128154$4989_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:268" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126462.7-126462.15" + attribute \src "libresoc.v:128069.7-128069.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -199171,80 +201591,80 @@ module \dec_bi$170 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126540$4938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128147$4979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:126540$4938_Y + connect \Y $extend$libresoc.v:128147$4979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126541$4940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128148$4981 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:126541$4940_Y + connect \Y $extend$libresoc.v:128148$4981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:126544$4944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $extend$libresoc.v:128151$4985 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:126544$4944_Y + connect \Y $extend$libresoc.v:128151$4985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $extend$libresoc.v:126548$4949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $extend$libresoc.v:128155$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126548$4949_Y + connect \Y $extend$libresoc.v:128155$4990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126540$4939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128147$4980 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126540$4938_Y - connect \Y $pos$libresoc.v:126540$4939_Y + connect \A $extend$libresoc.v:128147$4979_Y + connect \Y $pos$libresoc.v:128147$4980_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126541$4941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128148$4982 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126541$4940_Y - connect \Y $pos$libresoc.v:126541$4941_Y + connect \A $extend$libresoc.v:128148$4981_Y + connect \Y $pos$libresoc.v:128148$4982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:126544$4945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" + cell $pos $pos$libresoc.v:128151$4986 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126544$4944_Y - connect \Y $pos$libresoc.v:126544$4945_Y + connect \A $extend$libresoc.v:128151$4985_Y + connect \Y $pos$libresoc.v:128151$4986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $pos $pos$libresoc.v:126548$4950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $pos $pos$libresoc.v:128155$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126548$4949_Y - connect \Y $pos$libresoc.v:126548$4950_Y + connect \A $extend$libresoc.v:128155$4990_Y + connect \Y $pos$libresoc.v:128155$4991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $sshl $sshl$libresoc.v:126542$4942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:128149$4983 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199252,10 +201672,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126542$4942_Y + connect \Y $sshl$libresoc.v:128149$4983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - cell $sshl $sshl$libresoc.v:126543$4943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:128150$4984 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -199263,10 +201683,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126543$4943_Y + connect \Y $sshl$libresoc.v:128150$4984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $sshl $sshl$libresoc.v:126545$4946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:128152$4987 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199274,10 +201694,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126545$4946_Y + connect \Y $sshl$libresoc.v:128152$4987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" - cell $sshl $sshl$libresoc.v:126546$4947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" + cell $sshl $sshl$libresoc.v:128153$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199285,10 +201705,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126546$4947_Y + connect \Y $sshl$libresoc.v:128153$4988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" - cell $sshl $sshl$libresoc.v:126547$4948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" + cell $sshl $sshl$libresoc.v:128154$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199296,28 +201716,28 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126547$4948_Y + connect \Y $sshl$libresoc.v:128154$4989_Y end - attribute \src "libresoc.v:126462.7-126462.20" - process $proc$libresoc.v:126462$4959 + attribute \src "libresoc.v:128069.7-128069.20" + process $proc$libresoc.v:128069$5000 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126550.3-126596.6" - process $proc$libresoc.v:126550$4951 + attribute \src "libresoc.v:128157.3-128203.6" + process $proc$libresoc.v:128157$4992 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126551.5-126551.29" + attribute \src "libresoc.v:128158.5-128158.29" switch \initial - attribute \src "libresoc.v:126551.9-126551.17" + attribute \src "libresoc.v:128158.9-128158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199365,18 +201785,18 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126597.3-126643.6" - process $proc$libresoc.v:126597$4952 + attribute \src "libresoc.v:128204.3-128250.6" + process $proc$libresoc.v:128204$4993 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126598.5-126598.29" + attribute \src "libresoc.v:128205.5-128205.29" switch \initial - attribute \src "libresoc.v:126598.9-126598.17" + attribute \src "libresoc.v:128205.9-128205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -199424,18 +201844,18 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126644.3-126654.6" - process $proc$libresoc.v:126644$4953 + attribute \src "libresoc.v:128251.3-128261.6" + process $proc$libresoc.v:128251$4994 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126645.5-126645.29" + attribute \src "libresoc.v:128252.5-128252.29" switch \initial - attribute \src "libresoc.v:126645.9-126645.17" + attribute \src "libresoc.v:128252.9-128252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -199447,18 +201867,18 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126655.3-126665.6" - process $proc$libresoc.v:126655$4954 + attribute \src "libresoc.v:128262.3-128272.6" + process $proc$libresoc.v:128262$4995 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126656.5-126656.29" + attribute \src "libresoc.v:128263.5-128263.29" switch \initial - attribute \src "libresoc.v:126656.9-126656.17" + attribute \src "libresoc.v:128263.9-128263.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -199470,18 +201890,18 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126666.3-126676.6" - process $proc$libresoc.v:126666$4955 + attribute \src "libresoc.v:128273.3-128283.6" + process $proc$libresoc.v:128273$4996 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126667.5-126667.29" + attribute \src "libresoc.v:128274.5-128274.29" switch \initial - attribute \src "libresoc.v:126667.9-126667.17" + attribute \src "libresoc.v:128274.9-128274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -199493,18 +201913,18 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126677.3-126687.6" - process $proc$libresoc.v:126677$4956 + attribute \src "libresoc.v:128284.3-128294.6" + process $proc$libresoc.v:128284$4997 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126678.5-126678.29" + attribute \src "libresoc.v:128285.5-128285.29" switch \initial - attribute \src "libresoc.v:126678.9-126678.17" + attribute \src "libresoc.v:128285.9-128285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -199516,18 +201936,18 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126688.3-126698.6" - process $proc$libresoc.v:126688$4957 + attribute \src "libresoc.v:128295.3-128305.6" + process $proc$libresoc.v:128295$4998 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126689.5-126689.29" + attribute \src "libresoc.v:128296.5-128296.29" switch \initial - attribute \src "libresoc.v:126689.9-126689.17" + attribute \src "libresoc.v:128296.9-128296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -199539,18 +201959,18 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126699.3-126709.6" - process $proc$libresoc.v:126699$4958 + attribute \src "libresoc.v:128306.3-128316.6" + process $proc$libresoc.v:128306$4999 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126700.5-126700.29" + attribute \src "libresoc.v:128307.5-128307.29" switch \initial - attribute \src "libresoc.v:126700.9-126700.17" + attribute \src "libresoc.v:128307.9-128307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -199562,41 +201982,41 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126540$4939_Y - connect \$11 $pos$libresoc.v:126541$4941_Y - connect \$14 $sshl$libresoc.v:126542$4942_Y - connect \$17 $sshl$libresoc.v:126543$4943_Y - connect \$1 $pos$libresoc.v:126544$4945_Y - connect \$20 $sshl$libresoc.v:126545$4946_Y - connect \$23 $sshl$libresoc.v:126546$4947_Y - connect \$4 $sshl$libresoc.v:126547$4948_Y - connect \$3 $pos$libresoc.v:126548$4950_Y + connect \$9 $pos$libresoc.v:128147$4980_Y + connect \$11 $pos$libresoc.v:128148$4982_Y + connect \$14 $sshl$libresoc.v:128149$4983_Y + connect \$17 $sshl$libresoc.v:128150$4984_Y + connect \$1 $pos$libresoc.v:128151$4986_Y + connect \$20 $sshl$libresoc.v:128152$4987_Y + connect \$23 $sshl$libresoc.v:128153$4988_Y + connect \$4 $sshl$libresoc.v:128154$4989_Y + connect \$3 $pos$libresoc.v:128155$4991_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126718.1-126766.10" +attribute \src "libresoc.v:128325.1-128373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:126719.7-126719.20" + attribute \src "libresoc.v:128326.7-128326.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126736.3-126750.6" + attribute \src "libresoc.v:128343.3-128357.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:126751.3-126765.6" + attribute \src "libresoc.v:128358.3-128372.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:126736.3-126750.6" + attribute \src "libresoc.v:128343.3-128357.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:126751.3-126765.6" + attribute \src "libresoc.v:128358.3-128372.6" wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS - attribute \src "libresoc.v:126719.7-126719.15" + attribute \src "libresoc.v:128326.7-128326.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c @@ -199606,28 +202026,28 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:126719.7-126719.20" - process $proc$libresoc.v:126719$4962 + attribute \src "libresoc.v:128326.7-128326.20" + process $proc$libresoc.v:128326$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126736.3-126750.6" - process $proc$libresoc.v:126736$4960 + attribute \src "libresoc.v:128343.3-128357.6" + process $proc$libresoc.v:128343$5001 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:126737.5-126737.29" + attribute \src "libresoc.v:128344.5-128344.29" switch \initial - attribute \src "libresoc.v:126737.9-126737.17" + attribute \src "libresoc.v:128344.9-128344.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199643,18 +202063,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:126751.3-126765.6" - process $proc$libresoc.v:126751$4961 + attribute \src "libresoc.v:128358.3-128372.6" + process $proc$libresoc.v:128358$5002 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:126752.5-126752.29" + attribute \src "libresoc.v:128359.5-128359.29" switch \initial - attribute \src "libresoc.v:126752.9-126752.17" + attribute \src "libresoc.v:128359.9-128359.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -199671,90 +202091,90 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:126770.1-127102.10" +attribute \src "libresoc.v:128377.1-128709.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:127022.3-127052.6" + attribute \src "libresoc.v:128629.3-128659.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127053.3-127063.6" + attribute \src "libresoc.v:128660.3-128670.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126955.3-126965.6" + attribute \src "libresoc.v:128562.3-128572.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127064.3-127074.6" + attribute \src "libresoc.v:128671.3-128681.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126985.3-126995.6" + attribute \src "libresoc.v:128592.3-128602.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126924.3-126954.6" + attribute \src "libresoc.v:128531.3-128561.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:126996.3-127006.6" + attribute \src "libresoc.v:128603.3-128613.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126771.7-126771.20" + attribute \src "libresoc.v:128378.7-128378.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127075.3-127085.6" + attribute \src "libresoc.v:128682.3-128692.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127007.3-127021.6" + attribute \src "libresoc.v:128614.3-128628.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:127022.3-127052.6" + attribute \src "libresoc.v:128629.3-128659.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127053.3-127063.6" + attribute \src "libresoc.v:128660.3-128670.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126955.3-126965.6" + attribute \src "libresoc.v:128562.3-128572.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127064.3-127074.6" + attribute \src "libresoc.v:128671.3-128681.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126985.3-126995.6" + attribute \src "libresoc.v:128592.3-128602.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126924.3-126954.6" + attribute \src "libresoc.v:128531.3-128561.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:126996.3-127006.6" + attribute \src "libresoc.v:128603.3-128613.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127075.3-127085.6" + attribute \src "libresoc.v:128682.3-128692.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127007.3-127021.6" + attribute \src "libresoc.v:128614.3-128628.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:126966.3-126984.6" + attribute \src "libresoc.v:128573.3-128591.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127086.3-127101.6" + attribute \src "libresoc.v:128693.3-128708.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:126917.17-126917.112" - wire $and$libresoc.v:126917$4964_Y - attribute \src "libresoc.v:126919.17-126919.112" - wire $and$libresoc.v:126919$4966_Y - attribute \src "libresoc.v:126916.17-126916.117" - wire $eq$libresoc.v:126916$4963_Y - attribute \src "libresoc.v:126918.17-126918.117" - wire $eq$libresoc.v:126918$4965_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "libresoc.v:128524.17-128524.112" + wire $and$libresoc.v:128524$5005_Y + attribute \src "libresoc.v:128526.17-128526.112" + wire $and$libresoc.v:128526$5007_Y + attribute \src "libresoc.v:128523.17-128523.117" + wire $eq$libresoc.v:128523$5004_Y + attribute \src "libresoc.v:128525.17-128525.117" + wire $eq$libresoc.v:128525$5006_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 17 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 5 \cr_bitfield @@ -199772,9 +202192,9 @@ module \dec_cr_in wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:126771.7-126771.15" + attribute \src "libresoc.v:128378.7-128378.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -199851,9 +202271,9 @@ module \dec_cr_in attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 18 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i @@ -199868,12 +202288,12 @@ module \dec_cr_in attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $and $and$libresoc.v:126917$4964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128524$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199881,10 +202301,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:126917$4964_Y + connect \Y $and$libresoc.v:128524$5005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $and $and$libresoc.v:126919$4966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $and $and$libresoc.v:128526$5007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199892,10 +202312,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:126919$4966_Y + connect \Y $and$libresoc.v:128526$5007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $eq $eq$libresoc.v:126916$4963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128523$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -199903,10 +202323,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126916$4963_Y + connect \Y $eq$libresoc.v:128523$5004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" - cell $eq $eq$libresoc.v:126918$4965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" + cell $eq $eq$libresoc.v:128525$5006 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -199914,34 +202334,34 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126918$4965_Y + connect \Y $eq$libresoc.v:128525$5006_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126920.9-126923.4" + attribute \src "libresoc.v:128527.9-128530.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:126771.7-126771.20" - process $proc$libresoc.v:126771$4978 + attribute \src "libresoc.v:128378.7-128378.20" + process $proc$libresoc.v:128378$5019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126924.3-126954.6" - process $proc$libresoc.v:126924$4967 + attribute \src "libresoc.v:128531.3-128561.6" + process $proc$libresoc.v:128531$5008 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126925.5-126925.29" + attribute \src "libresoc.v:128532.5-128532.29" switch \initial - attribute \src "libresoc.v:126925.9-126925.17" + attribute \src "libresoc.v:128532.9-128532.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -199973,18 +202393,18 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:126955.3-126965.6" - process $proc$libresoc.v:126955$4968 + attribute \src "libresoc.v:128562.3-128572.6" + process $proc$libresoc.v:128562$5009 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126956.5-126956.29" + attribute \src "libresoc.v:128563.5-128563.29" switch \initial - attribute \src "libresoc.v:126956.9-126956.17" + attribute \src "libresoc.v:128563.9-128563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -199996,24 +202416,24 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:126966.3-126984.6" - process $proc$libresoc.v:126966$4969 + attribute \src "libresoc.v:128573.3-128591.6" + process $proc$libresoc.v:128573$5010 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:126967.5-126967.29" + attribute \src "libresoc.v:128574.5-128574.29" switch \initial - attribute \src "libresoc.v:126967.9-126967.17" + attribute \src "libresoc.v:128574.9-128574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200030,18 +202450,18 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:126985.3-126995.6" - process $proc$libresoc.v:126985$4970 + attribute \src "libresoc.v:128592.3-128602.6" + process $proc$libresoc.v:128592$5011 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126986.5-126986.29" + attribute \src "libresoc.v:128593.5-128593.29" switch \initial - attribute \src "libresoc.v:126986.9-126986.17" + attribute \src "libresoc.v:128593.9-128593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200053,18 +202473,18 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:126996.3-127006.6" - process $proc$libresoc.v:126996$4971 + attribute \src "libresoc.v:128603.3-128613.6" + process $proc$libresoc.v:128603$5012 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126997.5-126997.29" + attribute \src "libresoc.v:128604.5-128604.29" switch \initial - attribute \src "libresoc.v:126997.9-126997.17" + attribute \src "libresoc.v:128604.9-128604.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -200076,18 +202496,18 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:127007.3-127021.6" - process $proc$libresoc.v:127007$4972 + attribute \src "libresoc.v:128614.3-128628.6" + process $proc$libresoc.v:128614$5013 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:127008.5-127008.29" + attribute \src "libresoc.v:128615.5-128615.29" switch \initial - attribute \src "libresoc.v:127008.9-127008.17" + attribute \src "libresoc.v:128615.9-128615.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200103,18 +202523,18 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:127022.3-127052.6" - process $proc$libresoc.v:127022$4973 + attribute \src "libresoc.v:128629.3-128659.6" + process $proc$libresoc.v:128629$5014 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127023.5-127023.29" + attribute \src "libresoc.v:128630.5-128630.29" switch \initial - attribute \src "libresoc.v:127023.9-127023.17" + attribute \src "libresoc.v:128630.9-128630.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200146,18 +202566,18 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:127053.3-127063.6" - process $proc$libresoc.v:127053$4974 + attribute \src "libresoc.v:128660.3-128670.6" + process $proc$libresoc.v:128660$5015 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127054.5-127054.29" + attribute \src "libresoc.v:128661.5-128661.29" switch \initial - attribute \src "libresoc.v:127054.9-127054.17" + attribute \src "libresoc.v:128661.9-128661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200169,18 +202589,18 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:127064.3-127074.6" - process $proc$libresoc.v:127064$4975 + attribute \src "libresoc.v:128671.3-128681.6" + process $proc$libresoc.v:128671$5016 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127065.5-127065.29" + attribute \src "libresoc.v:128672.5-128672.29" switch \initial - attribute \src "libresoc.v:127065.9-127065.17" + attribute \src "libresoc.v:128672.9-128672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200192,18 +202612,18 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:127075.3-127085.6" - process $proc$libresoc.v:127075$4976 + attribute \src "libresoc.v:128682.3-128692.6" + process $proc$libresoc.v:128682$5017 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127076.5-127076.29" + attribute \src "libresoc.v:128683.5-128683.29" switch \initial - attribute \src "libresoc.v:127076.9-127076.17" + attribute \src "libresoc.v:128683.9-128683.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -200215,24 +202635,24 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:127086.3-127101.6" - process $proc$libresoc.v:127086$4977 + attribute \src "libresoc.v:128693.3-128708.6" + process $proc$libresoc.v:128693$5018 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127087.5-127087.29" + attribute \src "libresoc.v:128694.5-128694.29" switch \initial - attribute \src "libresoc.v:127087.9-127087.17" + attribute \src "libresoc.v:128694.9-128694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200247,69 +202667,69 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:126916$4963_Y - connect \$3 $and$libresoc.v:126917$4964_Y - connect \$5 $eq$libresoc.v:126918$4965_Y - connect \$7 $and$libresoc.v:126919$4966_Y + connect \$1 $eq$libresoc.v:128523$5004_Y + connect \$3 $and$libresoc.v:128524$5005_Y + connect \$5 $eq$libresoc.v:128525$5006_Y + connect \$7 $and$libresoc.v:128526$5007_Y end -attribute \src "libresoc.v:127106.1-127376.10" +attribute \src "libresoc.v:128713.1-128983.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:127286.3-127308.6" + attribute \src "libresoc.v:128893.3-128915.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127237.3-127259.6" + attribute \src "libresoc.v:128844.3-128866.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:127260.3-127270.6" + attribute \src "libresoc.v:128867.3-128877.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127107.7-127107.20" + attribute \src "libresoc.v:128714.7-128714.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127309.3-127319.6" + attribute \src "libresoc.v:128916.3-128926.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127271.3-127285.6" + attribute \src "libresoc.v:128878.3-128892.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:127286.3-127308.6" + attribute \src "libresoc.v:128893.3-128915.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127237.3-127259.6" + attribute \src "libresoc.v:128844.3-128866.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:127260.3-127270.6" + attribute \src "libresoc.v:128867.3-128877.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127309.3-127319.6" + attribute \src "libresoc.v:128916.3-128926.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127271.3-127285.6" + attribute \src "libresoc.v:128878.3-128892.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:127320.3-127340.6" + attribute \src "libresoc.v:128927.3-128947.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:127341.3-127375.6" + attribute \src "libresoc.v:128948.3-128982.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:127230.17-127230.117" - wire $eq$libresoc.v:127230$4979_Y - attribute \src "libresoc.v:127231.17-127231.117" - wire $eq$libresoc.v:127231$4980_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "libresoc.v:128837.17-128837.117" + wire $eq$libresoc.v:128837$5020_Y + attribute \src "libresoc.v:128838.17-128838.117" + wire $eq$libresoc.v:128838$5021_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 9 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \cr_bitfield @@ -200319,9 +202739,9 @@ module \dec_cr_out wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:127107.7-127107.15" + attribute \src "libresoc.v:128714.7-128714.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -200398,9 +202818,9 @@ module \dec_cr_out attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 11 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:637" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:638" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o @@ -200408,7 +202828,7 @@ module \dec_cr_out wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -200417,12 +202837,12 @@ module \dec_cr_out attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:599" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" wire width 2 \sv_override - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" - cell $eq $eq$libresoc.v:127230$4979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128837$5020 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -200430,10 +202850,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:127230$4979_Y + connect \Y $eq$libresoc.v:128837$5020_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" - cell $eq $eq$libresoc.v:127231$4980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + cell $eq $eq$libresoc.v:128838$5021 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -200441,35 +202861,35 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:127231$4980_Y + connect \Y $eq$libresoc.v:128838$5021_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127232.15-127236.4" + attribute \src "libresoc.v:128839.15-128843.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:127107.7-127107.20" - process $proc$libresoc.v:127107$4988 + attribute \src "libresoc.v:128714.7-128714.20" + process $proc$libresoc.v:128714$5029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127237.3-127259.6" - process $proc$libresoc.v:127237$4981 + attribute \src "libresoc.v:128844.3-128866.6" + process $proc$libresoc.v:128844$5022 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127238.5-127238.29" + attribute \src "libresoc.v:128845.5-128845.29" switch \initial - attribute \src "libresoc.v:127238.9-127238.17" + attribute \src "libresoc.v:128845.9-128845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200493,18 +202913,18 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:127260.3-127270.6" - process $proc$libresoc.v:127260$4982 + attribute \src "libresoc.v:128867.3-128877.6" + process $proc$libresoc.v:128867$5023 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127261.5-127261.29" + attribute \src "libresoc.v:128868.5-128868.29" switch \initial - attribute \src "libresoc.v:127261.9-127261.17" + attribute \src "libresoc.v:128868.9-128868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200516,18 +202936,18 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:127271.3-127285.6" - process $proc$libresoc.v:127271$4983 + attribute \src "libresoc.v:128878.3-128892.6" + process $proc$libresoc.v:128878$5024 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:127272.5-127272.29" + attribute \src "libresoc.v:128879.5-128879.29" switch \initial - attribute \src "libresoc.v:127272.9-127272.17" + attribute \src "libresoc.v:128879.9-128879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200543,18 +202963,18 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:127286.3-127308.6" - process $proc$libresoc.v:127286$4984 + attribute \src "libresoc.v:128893.3-128915.6" + process $proc$libresoc.v:128893$5025 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127287.5-127287.29" + attribute \src "libresoc.v:128894.5-128894.29" switch \initial - attribute \src "libresoc.v:127287.9-127287.17" + attribute \src "libresoc.v:128894.9-128894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -200578,18 +202998,18 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:127309.3-127319.6" - process $proc$libresoc.v:127309$4985 + attribute \src "libresoc.v:128916.3-128926.6" + process $proc$libresoc.v:128916$5026 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127310.5-127310.29" + attribute \src "libresoc.v:128917.5-128917.29" switch \initial - attribute \src "libresoc.v:127310.9-127310.17" + attribute \src "libresoc.v:128917.9-128917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -200601,30 +203021,30 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:127320.3-127340.6" - process $proc$libresoc.v:127320$4986 + attribute \src "libresoc.v:128927.3-128947.6" + process $proc$libresoc.v:128927$5027 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127321.5-127321.29" + attribute \src "libresoc.v:128928.5-128928.29" switch \initial - attribute \src "libresoc.v:127321.9-127321.17" + attribute \src "libresoc.v:128928.9-128928.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200642,36 +203062,36 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:127341.3-127375.6" - process $proc$libresoc.v:127341$4987 + attribute \src "libresoc.v:128948.3-128982.6" + process $proc$libresoc.v:128948$5028 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:127342.5-127342.29" + attribute \src "libresoc.v:128949.5-128949.29" switch \initial - attribute \src "libresoc.v:127342.9-127342.17" + attribute \src "libresoc.v:128949.9-128949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:644" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -200698,95 +203118,95 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:127230$4979_Y - connect \$3 $eq$libresoc.v:127231$4980_Y + connect \$1 $eq$libresoc.v:128837$5020_Y + connect \$3 $eq$libresoc.v:128838$5021_Y end -attribute \src "libresoc.v:127380.1-127865.10" +attribute \src "libresoc.v:128987.1-129472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:127381.7-127381.20" + attribute \src "libresoc.v:128988.7-128988.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127752.3-127766.6" + attribute \src "libresoc.v:129359.3-129373.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:127767.3-127781.6" + attribute \src "libresoc.v:129374.3-129388.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:127782.3-127792.6" + attribute \src "libresoc.v:129389.3-129399.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:127752.3-127766.6" + attribute \src "libresoc.v:129359.3-129373.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:127767.3-127781.6" + attribute \src "libresoc.v:129374.3-129388.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:127782.3-127792.6" + attribute \src "libresoc.v:129389.3-129399.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:127809.3-127825.6" + attribute \src "libresoc.v:129416.3-129432.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:127793.3-127808.6" + attribute \src "libresoc.v:129400.3-129415.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:127826.3-127864.6" + attribute \src "libresoc.v:129433.3-129471.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:127741.17-127741.117" - wire $eq$libresoc.v:127741$4989_Y - attribute \src "libresoc.v:127742.17-127742.117" - wire $eq$libresoc.v:127742$4990_Y - attribute \src "libresoc.v:127743.17-127743.117" - wire $eq$libresoc.v:127743$4991_Y - attribute \src "libresoc.v:127744.17-127744.104" - wire $not$libresoc.v:127744$4992_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "libresoc.v:129348.17-129348.117" + wire $eq$libresoc.v:129348$5030_Y + attribute \src "libresoc.v:129349.17-129349.117" + wire $eq$libresoc.v:129349$5031_Y + attribute \src "libresoc.v:129350.17-129350.117" + wire $eq$libresoc.v:129350$5032_Y + attribute \src "libresoc.v:129351.17-129351.104" + wire $not$libresoc.v:129351$5033_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 9 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \fast_o_ok - attribute \src "libresoc.v:127381.7-127381.15" + attribute \src "libresoc.v:128988.7-128988.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -200863,7 +203283,7 @@ module \dec_o attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 3 \reg_o @@ -200875,9 +203295,9 @@ module \dec_o attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -201001,7 +203421,7 @@ module \dec_o wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -201121,8 +203541,8 @@ module \dec_o wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127741$4989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129348$5030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201130,10 +203550,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127741$4989_Y + connect \Y $eq$libresoc.v:129348$5030_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127742$4990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129349$5031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201141,10 +203561,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127742$4990_Y + connect \Y $eq$libresoc.v:129349$5031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" - cell $eq $eq$libresoc.v:127743$4991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" + cell $eq $eq$libresoc.v:129350$5032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -201152,18 +203572,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:127743$4991_Y + connect \Y $eq$libresoc.v:129350$5032_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - cell $not $not$libresoc.v:127744$4992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + cell $not $not$libresoc.v:129351$5033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:127744$4992_Y + connect \Y $not$libresoc.v:129351$5033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127745.16-127751.4" + attribute \src "libresoc.v:129352.16-129358.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -201171,26 +203591,26 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:127381.7-127381.20" - process $proc$libresoc.v:127381$4999 + attribute \src "libresoc.v:128988.7-128988.20" + process $proc$libresoc.v:128988$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127752.3-127766.6" - process $proc$libresoc.v:127752$4993 + attribute \src "libresoc.v:129359.3-129373.6" + process $proc$libresoc.v:129359$5034 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:127753.5-127753.29" + attribute \src "libresoc.v:129360.5-129360.29" switch \initial - attribute \src "libresoc.v:127753.9-127753.17" + attribute \src "libresoc.v:129360.9-129360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -201206,18 +203626,18 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:127767.3-127781.6" - process $proc$libresoc.v:127767$4994 + attribute \src "libresoc.v:129374.3-129388.6" + process $proc$libresoc.v:129374$5035 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:127768.5-127768.29" + attribute \src "libresoc.v:129375.5-129375.29" switch \initial - attribute \src "libresoc.v:127768.9-127768.17" + attribute \src "libresoc.v:129375.9-129375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -201233,18 +203653,18 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:127782.3-127792.6" - process $proc$libresoc.v:127782$4995 + attribute \src "libresoc.v:129389.3-129399.6" + process $proc$libresoc.v:129389$5036 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:127783.5-127783.29" + attribute \src "libresoc.v:129390.5-129390.29" switch \initial - attribute \src "libresoc.v:127783.9-127783.17" + attribute \src "libresoc.v:129390.9-129390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201256,24 +203676,24 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:127793.3-127808.6" - process $proc$libresoc.v:127793$4996 + attribute \src "libresoc.v:129400.3-129415.6" + process $proc$libresoc.v:129400$5037 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:127794.5-127794.29" + attribute \src "libresoc.v:129401.5-129401.29" switch \initial - attribute \src "libresoc.v:127794.9-127794.17" + attribute \src "libresoc.v:129401.9-129401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201288,21 +203708,21 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:127809.3-127825.6" - process $proc$libresoc.v:127809$4997 + attribute \src "libresoc.v:129416.3-129432.6" + process $proc$libresoc.v:129416$5038 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:127810.5-127810.29" + attribute \src "libresoc.v:129417.5-129417.29" switch \initial - attribute \src "libresoc.v:127810.9-127810.17" + attribute \src "libresoc.v:129417.9-129417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201310,7 +203730,7 @@ module \dec_o assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201329,8 +203749,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:127826.3-127864.6" - process $proc$libresoc.v:127826$4998 + attribute \src "libresoc.v:129433.3-129471.6" + process $proc$libresoc.v:129433$5039 assign { } { } assign { } { } assign { } { } @@ -201339,13 +203759,13 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:127827.5-127827.29" + attribute \src "libresoc.v:129434.5-129434.29" switch \initial - attribute \src "libresoc.v:127827.9-127827.17" + attribute \src "libresoc.v:129434.9-129434.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:343" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'011 @@ -201353,7 +203773,7 @@ module \dec_o assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201368,7 +203788,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -201376,7 +203796,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201402,53 +203822,53 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:127741$4989_Y - connect \$3 $eq$libresoc.v:127742$4990_Y - connect \$5 $eq$libresoc.v:127743$4991_Y - connect \$7 $not$libresoc.v:127744$4992_Y + connect \$1 $eq$libresoc.v:129348$5030_Y + connect \$3 $eq$libresoc.v:129349$5031_Y + connect \$5 $eq$libresoc.v:129350$5032_Y + connect \$7 $not$libresoc.v:129351$5033_Y end -attribute \src "libresoc.v:127869.1-128037.10" +attribute \src "libresoc.v:129476.1-129644.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:127870.7-127870.20" + attribute \src "libresoc.v:129477.7-129477.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127977.3-127986.6" + attribute \src "libresoc.v:129584.3-129593.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:127987.3-127996.6" + attribute \src "libresoc.v:129594.3-129603.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:127977.3-127986.6" + attribute \src "libresoc.v:129584.3-129593.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:127987.3-127996.6" + attribute \src "libresoc.v:129594.3-129603.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:127997.3-128016.6" + attribute \src "libresoc.v:129604.3-129623.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:128017.3-128036.6" + attribute \src "libresoc.v:129624.3-129643.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:127975.17-127975.108" - wire $eq$libresoc.v:127975$5000_Y - attribute \src "libresoc.v:127976.17-127976.108" - wire $eq$libresoc.v:127976$5001_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "libresoc.v:129582.17-129582.108" + wire $eq$libresoc.v:129582$5041_Y + attribute \src "libresoc.v:129583.17-129583.108" + wire $eq$libresoc.v:129583$5042_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:127870.7-127870.15" + attribute \src "libresoc.v:129477.7-129477.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201525,9 +203945,9 @@ module \dec_o2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_o2 @@ -201538,10 +203958,10 @@ module \dec_o2 attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" - cell $eq $eq$libresoc.v:127975$5000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129582$5041 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -201549,10 +203969,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:127975$5000_Y + connect \Y $eq$libresoc.v:129582$5041_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" - cell $eq $eq$libresoc.v:127976$5001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" + cell $eq $eq$libresoc.v:129583$5042 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -201560,28 +203980,28 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:127976$5001_Y + connect \Y $eq$libresoc.v:129583$5042_Y end - attribute \src "libresoc.v:127870.7-127870.20" - process $proc$libresoc.v:127870$5006 + attribute \src "libresoc.v:129477.7-129477.20" + process $proc$libresoc.v:129477$5047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127977.3-127986.6" - process $proc$libresoc.v:127977$5002 + attribute \src "libresoc.v:129584.3-129593.6" + process $proc$libresoc.v:129584$5043 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:127978.5-127978.29" + attribute \src "libresoc.v:129585.5-129585.29" switch \initial - attribute \src "libresoc.v:127978.9-127978.17" + attribute \src "libresoc.v:129585.9-129585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201593,18 +204013,18 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:127987.3-127996.6" - process $proc$libresoc.v:127987$5003 + attribute \src "libresoc.v:129594.3-129603.6" + process $proc$libresoc.v:129594$5044 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:127988.5-127988.29" + attribute \src "libresoc.v:129595.5-129595.29" switch \initial - attribute \src "libresoc.v:127988.9-127988.17" + attribute \src "libresoc.v:129595.9-129595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201616,24 +204036,24 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:127997.3-128016.6" - process $proc$libresoc.v:127997$5004 + attribute \src "libresoc.v:129604.3-129623.6" + process $proc$libresoc.v:129604$5045 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:127998.5-127998.29" + attribute \src "libresoc.v:129605.5-129605.29" switch \initial - attribute \src "libresoc.v:127998.9-127998.17" + attribute \src "libresoc.v:129605.9-129605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2[2:0] $2\fast_o2[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201652,24 +204072,24 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:128017.3-128036.6" - process $proc$libresoc.v:128017$5005 + attribute \src "libresoc.v:129624.3-129643.6" + process $proc$libresoc.v:129624$5046 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:128018.5-128018.29" + attribute \src "libresoc.v:129625.5-129625.29" switch \initial - attribute \src "libresoc.v:128018.9-128018.17" + attribute \src "libresoc.v:129625.9-129625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -201688,29 +204108,29 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:127975$5000_Y - connect \$3 $eq$libresoc.v:127976$5001_Y + connect \$1 $eq$libresoc.v:129582$5041_Y + connect \$3 $eq$libresoc.v:129583$5042_Y end -attribute \src "libresoc.v:128041.1-128176.10" +attribute \src "libresoc.v:129648.1-129783.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:128042.7-128042.20" + attribute \src "libresoc.v:129649.7-129649.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128134.3-128154.6" + attribute \src "libresoc.v:129741.3-129761.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128155.3-128175.6" + attribute \src "libresoc.v:129762.3-129782.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201787,9 +204207,9 @@ module \dec_oe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:128042.7-128042.15" + attribute \src "libresoc.v:129649.7-129649.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -201799,28 +204219,28 @@ module \dec_oe attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128042.7-128042.20" - process $proc$libresoc.v:128042$5009 + attribute \src "libresoc.v:129649.7-129649.20" + process $proc$libresoc.v:129649$5050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128134.3-128154.6" - process $proc$libresoc.v:128134$5007 + attribute \src "libresoc.v:129741.3-129761.6" + process $proc$libresoc.v:129741$5048 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128135.5-128135.29" + attribute \src "libresoc.v:129742.5-129742.29" switch \initial - attribute \src "libresoc.v:128135.9-128135.17" + attribute \src "libresoc.v:129742.9-129742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201829,7 +204249,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201842,18 +204262,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128155.3-128175.6" - process $proc$libresoc.v:128155$5008 + attribute \src "libresoc.v:129762.3-129782.6" + process $proc$libresoc.v:129762$5049 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128156.5-128156.29" + attribute \src "libresoc.v:129763.5-129763.29" switch \initial - attribute \src "libresoc.v:128156.9-128156.17" + attribute \src "libresoc.v:129763.9-129763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -201862,7 +204282,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -201876,26 +204296,26 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128180.1-128313.10" +attribute \src "libresoc.v:129787.1-129920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:128181.7-128181.20" + attribute \src "libresoc.v:129788.7-129788.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128271.3-128291.6" + attribute \src "libresoc.v:129878.3-129898.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128292.3-128312.6" + attribute \src "libresoc.v:129899.3-129919.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -201972,9 +204392,9 @@ module \dec_oe$140 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:128181.7-128181.15" + attribute \src "libresoc.v:129788.7-129788.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -201984,28 +204404,28 @@ module \dec_oe$140 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128181.7-128181.20" - process $proc$libresoc.v:128181$5012 + attribute \src "libresoc.v:129788.7-129788.20" + process $proc$libresoc.v:129788$5053 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128271.3-128291.6" - process $proc$libresoc.v:128271$5010 + attribute \src "libresoc.v:129878.3-129898.6" + process $proc$libresoc.v:129878$5051 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128272.5-128272.29" + attribute \src "libresoc.v:129879.5-129879.29" switch \initial - attribute \src "libresoc.v:128272.9-128272.17" + attribute \src "libresoc.v:129879.9-129879.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202014,7 +204434,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202027,18 +204447,18 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128292.3-128312.6" - process $proc$libresoc.v:128292$5011 + attribute \src "libresoc.v:129899.3-129919.6" + process $proc$libresoc.v:129899$5052 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128293.5-128293.29" + attribute \src "libresoc.v:129900.5-129900.29" switch \initial - attribute \src "libresoc.v:128293.9-128293.17" + attribute \src "libresoc.v:129900.9-129900.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202047,7 +204467,7 @@ module \dec_oe$140 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202061,26 +204481,26 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128317.1-128450.10" +attribute \src "libresoc.v:129924.1-130057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:128318.7-128318.20" + attribute \src "libresoc.v:129925.7-129925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128408.3-128428.6" + attribute \src "libresoc.v:130015.3-130035.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128429.3-128449.6" + attribute \src "libresoc.v:130036.3-130056.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202157,9 +204577,9 @@ module \dec_oe$143 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:128318.7-128318.15" + attribute \src "libresoc.v:129925.7-129925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -202169,28 +204589,28 @@ module \dec_oe$143 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128318.7-128318.20" - process $proc$libresoc.v:128318$5015 + attribute \src "libresoc.v:129925.7-129925.20" + process $proc$libresoc.v:129925$5056 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128408.3-128428.6" - process $proc$libresoc.v:128408$5013 + attribute \src "libresoc.v:130015.3-130035.6" + process $proc$libresoc.v:130015$5054 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128409.5-128409.29" + attribute \src "libresoc.v:130016.5-130016.29" switch \initial - attribute \src "libresoc.v:128409.9-128409.17" + attribute \src "libresoc.v:130016.9-130016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202199,7 +204619,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202212,18 +204632,18 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128429.3-128449.6" - process $proc$libresoc.v:128429$5014 + attribute \src "libresoc.v:130036.3-130056.6" + process $proc$libresoc.v:130036$5055 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128430.5-128430.29" + attribute \src "libresoc.v:130037.5-130037.29" switch \initial - attribute \src "libresoc.v:128430.9-128430.17" + attribute \src "libresoc.v:130037.9-130037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202232,7 +204652,7 @@ module \dec_oe$143 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202246,26 +204666,26 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128454.1-128589.10" +attribute \src "libresoc.v:130061.1-130196.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:128455.7-128455.20" + attribute \src "libresoc.v:130062.7-130062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128547.3-128567.6" + attribute \src "libresoc.v:130154.3-130174.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128568.3-128588.6" + attribute \src "libresoc.v:130175.3-130195.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202342,9 +204762,9 @@ module \dec_oe$147 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:128455.7-128455.15" + attribute \src "libresoc.v:130062.7-130062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202354,28 +204774,28 @@ module \dec_oe$147 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128455.7-128455.20" - process $proc$libresoc.v:128455$5018 + attribute \src "libresoc.v:130062.7-130062.20" + process $proc$libresoc.v:130062$5059 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128547.3-128567.6" - process $proc$libresoc.v:128547$5016 + attribute \src "libresoc.v:130154.3-130174.6" + process $proc$libresoc.v:130154$5057 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128548.5-128548.29" + attribute \src "libresoc.v:130155.5-130155.29" switch \initial - attribute \src "libresoc.v:128548.9-128548.17" + attribute \src "libresoc.v:130155.9-130155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202384,7 +204804,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202397,18 +204817,18 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128568.3-128588.6" - process $proc$libresoc.v:128568$5017 + attribute \src "libresoc.v:130175.3-130195.6" + process $proc$libresoc.v:130175$5058 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128569.5-128569.29" + attribute \src "libresoc.v:130176.5-130176.29" switch \initial - attribute \src "libresoc.v:128569.9-128569.17" + attribute \src "libresoc.v:130176.9-130176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202417,7 +204837,7 @@ module \dec_oe$147 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202431,26 +204851,26 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128593.1-128726.10" +attribute \src "libresoc.v:130200.1-130333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:128594.7-128594.20" + attribute \src "libresoc.v:130201.7-130201.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128684.3-128704.6" + attribute \src "libresoc.v:130291.3-130311.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128705.3-128725.6" + attribute \src "libresoc.v:130312.3-130332.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202527,9 +204947,9 @@ module \dec_oe$152 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:128594.7-128594.15" + attribute \src "libresoc.v:130201.7-130201.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -202539,28 +204959,28 @@ module \dec_oe$152 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:128594.7-128594.20" - process $proc$libresoc.v:128594$5021 + attribute \src "libresoc.v:130201.7-130201.20" + process $proc$libresoc.v:130201$5062 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128684.3-128704.6" - process $proc$libresoc.v:128684$5019 + attribute \src "libresoc.v:130291.3-130311.6" + process $proc$libresoc.v:130291$5060 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128685.5-128685.29" + attribute \src "libresoc.v:130292.5-130292.29" switch \initial - attribute \src "libresoc.v:128685.9-128685.17" + attribute \src "libresoc.v:130292.9-130292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202569,7 +204989,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202582,18 +205002,18 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128705.3-128725.6" - process $proc$libresoc.v:128705$5020 + attribute \src "libresoc.v:130312.3-130332.6" + process $proc$libresoc.v:130312$5061 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128706.5-128706.29" + attribute \src "libresoc.v:130313.5-130313.29" switch \initial - attribute \src "libresoc.v:128706.9-128706.17" + attribute \src "libresoc.v:130313.9-130313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202602,7 +205022,7 @@ module \dec_oe$152 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202616,26 +205036,26 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128730.1-128865.10" +attribute \src "libresoc.v:130337.1-130472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:128731.7-128731.20" + attribute \src "libresoc.v:130338.7-130338.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128823.3-128843.6" + attribute \src "libresoc.v:130430.3-130450.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128844.3-128864.6" + attribute \src "libresoc.v:130451.3-130471.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202712,9 +205132,9 @@ module \dec_oe$155 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:128731.7-128731.15" + attribute \src "libresoc.v:130338.7-130338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202724,28 +205144,28 @@ module \dec_oe$155 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128731.7-128731.20" - process $proc$libresoc.v:128731$5024 + attribute \src "libresoc.v:130338.7-130338.20" + process $proc$libresoc.v:130338$5065 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128823.3-128843.6" - process $proc$libresoc.v:128823$5022 + attribute \src "libresoc.v:130430.3-130450.6" + process $proc$libresoc.v:130430$5063 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128824.5-128824.29" + attribute \src "libresoc.v:130431.5-130431.29" switch \initial - attribute \src "libresoc.v:128824.9-128824.17" + attribute \src "libresoc.v:130431.9-130431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202754,7 +205174,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202767,18 +205187,18 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128844.3-128864.6" - process $proc$libresoc.v:128844$5023 + attribute \src "libresoc.v:130451.3-130471.6" + process $proc$libresoc.v:130451$5064 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128845.5-128845.29" + attribute \src "libresoc.v:130452.5-130452.29" switch \initial - attribute \src "libresoc.v:128845.9-128845.17" + attribute \src "libresoc.v:130452.9-130452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202787,7 +205207,7 @@ module \dec_oe$155 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202801,26 +205221,26 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:128869.1-129004.10" +attribute \src "libresoc.v:130476.1-130611.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:128870.7-128870.20" + attribute \src "libresoc.v:130477.7-130477.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $0\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $1\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:128962.3-128982.6" + attribute \src "libresoc.v:130569.3-130589.6" wire $2\oe[0:0] - attribute \src "libresoc.v:128983.3-129003.6" + attribute \src "libresoc.v:130590.3-130610.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -202897,9 +205317,9 @@ module \dec_oe$160 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:128870.7-128870.15" + attribute \src "libresoc.v:130477.7-130477.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -202909,28 +205329,28 @@ module \dec_oe$160 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128870.7-128870.20" - process $proc$libresoc.v:128870$5027 + attribute \src "libresoc.v:130477.7-130477.20" + process $proc$libresoc.v:130477$5068 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128962.3-128982.6" - process $proc$libresoc.v:128962$5025 + attribute \src "libresoc.v:130569.3-130589.6" + process $proc$libresoc.v:130569$5066 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:128963.5-128963.29" + attribute \src "libresoc.v:130570.5-130570.29" switch \initial - attribute \src "libresoc.v:128963.9-128963.17" + attribute \src "libresoc.v:130570.9-130570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202939,7 +205359,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202952,18 +205372,18 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128983.3-129003.6" - process $proc$libresoc.v:128983$5026 + attribute \src "libresoc.v:130590.3-130610.6" + process $proc$libresoc.v:130590$5067 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:128984.5-128984.29" + attribute \src "libresoc.v:130591.5-130591.29" switch \initial - attribute \src "libresoc.v:128984.9-128984.17" + attribute \src "libresoc.v:130591.9-130591.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -202972,7 +205392,7 @@ module \dec_oe$160 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -202986,26 +205406,26 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129008.1-129143.10" +attribute \src "libresoc.v:130615.1-130750.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:129009.7-129009.20" + attribute \src "libresoc.v:130616.7-130616.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129101.3-129121.6" + attribute \src "libresoc.v:130708.3-130728.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129122.3-129142.6" + attribute \src "libresoc.v:130729.3-130749.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203082,9 +205502,9 @@ module \dec_oe$164 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:129009.7-129009.15" + attribute \src "libresoc.v:130616.7-130616.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203094,28 +205514,28 @@ module \dec_oe$164 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129009.7-129009.20" - process $proc$libresoc.v:129009$5030 + attribute \src "libresoc.v:130616.7-130616.20" + process $proc$libresoc.v:130616$5071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129101.3-129121.6" - process $proc$libresoc.v:129101$5028 + attribute \src "libresoc.v:130708.3-130728.6" + process $proc$libresoc.v:130708$5069 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129102.5-129102.29" + attribute \src "libresoc.v:130709.5-130709.29" switch \initial - attribute \src "libresoc.v:129102.9-129102.17" + attribute \src "libresoc.v:130709.9-130709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203124,7 +205544,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203137,18 +205557,18 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129122.3-129142.6" - process $proc$libresoc.v:129122$5029 + attribute \src "libresoc.v:130729.3-130749.6" + process $proc$libresoc.v:130729$5070 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129123.5-129123.29" + attribute \src "libresoc.v:130730.5-130730.29" switch \initial - attribute \src "libresoc.v:129123.9-129123.17" + attribute \src "libresoc.v:130730.9-130730.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203157,7 +205577,7 @@ module \dec_oe$164 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203171,26 +205591,26 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129147.1-129282.10" +attribute \src "libresoc.v:130754.1-130889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:129148.7-129148.20" + attribute \src "libresoc.v:130755.7-130755.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129240.3-129260.6" + attribute \src "libresoc.v:130847.3-130867.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129261.3-129281.6" + attribute \src "libresoc.v:130868.3-130888.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203267,9 +205687,9 @@ module \dec_oe$168 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:129148.7-129148.15" + attribute \src "libresoc.v:130755.7-130755.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203279,28 +205699,28 @@ module \dec_oe$168 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129148.7-129148.20" - process $proc$libresoc.v:129148$5033 + attribute \src "libresoc.v:130755.7-130755.20" + process $proc$libresoc.v:130755$5074 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129240.3-129260.6" - process $proc$libresoc.v:129240$5031 + attribute \src "libresoc.v:130847.3-130867.6" + process $proc$libresoc.v:130847$5072 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129241.5-129241.29" + attribute \src "libresoc.v:130848.5-130848.29" switch \initial - attribute \src "libresoc.v:129241.9-129241.17" + attribute \src "libresoc.v:130848.9-130848.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203309,7 +205729,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203322,18 +205742,18 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129261.3-129281.6" - process $proc$libresoc.v:129261$5032 + attribute \src "libresoc.v:130868.3-130888.6" + process $proc$libresoc.v:130868$5073 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129262.5-129262.29" + attribute \src "libresoc.v:130869.5-130869.29" switch \initial - attribute \src "libresoc.v:129262.9-129262.17" + attribute \src "libresoc.v:130869.9-130869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203342,7 +205762,7 @@ module \dec_oe$168 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203356,28 +205776,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129286.1-129421.10" +attribute \src "libresoc.v:130893.1-131028.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:129287.7-129287.20" + attribute \src "libresoc.v:130894.7-130894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129379.3-129399.6" + attribute \src "libresoc.v:130986.3-131006.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129400.3-129420.6" + attribute \src "libresoc.v:131007.3-131027.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE - attribute \src "libresoc.v:129287.7-129287.15" + attribute \src "libresoc.v:130894.7-130894.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203454,7 +205874,7 @@ module \dec_oe$173 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -203464,28 +205884,28 @@ module \dec_oe$173 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129287.7-129287.20" - process $proc$libresoc.v:129287$5036 + attribute \src "libresoc.v:130894.7-130894.20" + process $proc$libresoc.v:130894$5077 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129379.3-129399.6" - process $proc$libresoc.v:129379$5034 + attribute \src "libresoc.v:130986.3-131006.6" + process $proc$libresoc.v:130986$5075 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129380.5-129380.29" + attribute \src "libresoc.v:130987.5-130987.29" switch \initial - attribute \src "libresoc.v:129380.9-129380.17" + attribute \src "libresoc.v:130987.9-130987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203494,7 +205914,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203507,18 +205927,18 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129400.3-129420.6" - process $proc$libresoc.v:129400$5035 + attribute \src "libresoc.v:131007.3-131027.6" + process $proc$libresoc.v:131007$5076 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129401.5-129401.29" + attribute \src "libresoc.v:131008.5-131008.29" switch \initial - attribute \src "libresoc.v:129401.9-129401.17" + attribute \src "libresoc.v:131008.9-131008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -203527,7 +205947,7 @@ module \dec_oe$173 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203541,24 +205961,24 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129425.1-129479.10" +attribute \src "libresoc.v:131032.1-131086.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:129426.7-129426.20" + attribute \src "libresoc.v:131033.7-131033.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129441.3-129459.6" + attribute \src "libresoc.v:131048.3-131066.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129460.3-129478.6" + attribute \src "libresoc.v:131067.3-131085.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129441.3-129459.6" + attribute \src "libresoc.v:131048.3-131066.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129460.3-129478.6" + attribute \src "libresoc.v:131067.3-131085.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc - attribute \src "libresoc.v:129426.7-129426.15" + attribute \src "libresoc.v:131033.7-131033.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -203568,28 +205988,28 @@ module \dec_rc attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129426.7-129426.20" - process $proc$libresoc.v:129426$5039 + attribute \src "libresoc.v:131033.7-131033.20" + process $proc$libresoc.v:131033$5080 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129441.3-129459.6" - process $proc$libresoc.v:129441$5037 + attribute \src "libresoc.v:131048.3-131066.6" + process $proc$libresoc.v:131048$5078 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129442.5-129442.29" + attribute \src "libresoc.v:131049.5-131049.29" switch \initial - attribute \src "libresoc.v:129442.9-129442.17" + attribute \src "libresoc.v:131049.9-131049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203609,18 +206029,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129460.3-129478.6" - process $proc$libresoc.v:129460$5038 + attribute \src "libresoc.v:131067.3-131085.6" + process $proc$libresoc.v:131067$5079 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129461.5-129461.29" + attribute \src "libresoc.v:131068.5-131068.29" switch \initial - attribute \src "libresoc.v:129461.9-129461.17" + attribute \src "libresoc.v:131068.9-131068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203641,24 +206061,24 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129483.1-129535.10" +attribute \src "libresoc.v:131090.1-131142.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:129484.7-129484.20" + attribute \src "libresoc.v:131091.7-131091.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129497.3-129515.6" + attribute \src "libresoc.v:131104.3-131122.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129516.3-129534.6" + attribute \src "libresoc.v:131123.3-131141.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129497.3-129515.6" + attribute \src "libresoc.v:131104.3-131122.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129516.3-129534.6" + attribute \src "libresoc.v:131123.3-131141.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc - attribute \src "libresoc.v:129484.7-129484.15" + attribute \src "libresoc.v:131091.7-131091.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203668,28 +206088,28 @@ module \dec_rc$139 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129484.7-129484.20" - process $proc$libresoc.v:129484$5042 + attribute \src "libresoc.v:131091.7-131091.20" + process $proc$libresoc.v:131091$5083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129497.3-129515.6" - process $proc$libresoc.v:129497$5040 + attribute \src "libresoc.v:131104.3-131122.6" + process $proc$libresoc.v:131104$5081 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129498.5-129498.29" + attribute \src "libresoc.v:131105.5-131105.29" switch \initial - attribute \src "libresoc.v:129498.9-129498.17" + attribute \src "libresoc.v:131105.9-131105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203709,18 +206129,18 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129516.3-129534.6" - process $proc$libresoc.v:129516$5041 + attribute \src "libresoc.v:131123.3-131141.6" + process $proc$libresoc.v:131123$5082 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129517.5-129517.29" + attribute \src "libresoc.v:131124.5-131124.29" switch \initial - attribute \src "libresoc.v:129517.9-129517.17" + attribute \src "libresoc.v:131124.9-131124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203741,24 +206161,24 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129539.1-129591.10" +attribute \src "libresoc.v:131146.1-131198.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:129540.7-129540.20" + attribute \src "libresoc.v:131147.7-131147.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129553.3-129571.6" + attribute \src "libresoc.v:131160.3-131178.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129572.3-129590.6" + attribute \src "libresoc.v:131179.3-131197.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129553.3-129571.6" + attribute \src "libresoc.v:131160.3-131178.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129572.3-129590.6" + attribute \src "libresoc.v:131179.3-131197.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:129540.7-129540.15" + attribute \src "libresoc.v:131147.7-131147.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203768,28 +206188,28 @@ module \dec_rc$142 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129540.7-129540.20" - process $proc$libresoc.v:129540$5045 + attribute \src "libresoc.v:131147.7-131147.20" + process $proc$libresoc.v:131147$5086 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129553.3-129571.6" - process $proc$libresoc.v:129553$5043 + attribute \src "libresoc.v:131160.3-131178.6" + process $proc$libresoc.v:131160$5084 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129554.5-129554.29" + attribute \src "libresoc.v:131161.5-131161.29" switch \initial - attribute \src "libresoc.v:129554.9-129554.17" + attribute \src "libresoc.v:131161.9-131161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203809,18 +206229,18 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129572.3-129590.6" - process $proc$libresoc.v:129572$5044 + attribute \src "libresoc.v:131179.3-131197.6" + process $proc$libresoc.v:131179$5085 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129573.5-129573.29" + attribute \src "libresoc.v:131180.5-131180.29" switch \initial - attribute \src "libresoc.v:129573.9-129573.17" + attribute \src "libresoc.v:131180.9-131180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203841,24 +206261,24 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129595.1-129649.10" +attribute \src "libresoc.v:131202.1-131256.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:129596.7-129596.20" + attribute \src "libresoc.v:131203.7-131203.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129611.3-129629.6" + attribute \src "libresoc.v:131218.3-131236.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129630.3-129648.6" + attribute \src "libresoc.v:131237.3-131255.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129611.3-129629.6" + attribute \src "libresoc.v:131218.3-131236.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129630.3-129648.6" + attribute \src "libresoc.v:131237.3-131255.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:129596.7-129596.15" + attribute \src "libresoc.v:131203.7-131203.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -203868,28 +206288,28 @@ module \dec_rc$146 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129596.7-129596.20" - process $proc$libresoc.v:129596$5048 + attribute \src "libresoc.v:131203.7-131203.20" + process $proc$libresoc.v:131203$5089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129611.3-129629.6" - process $proc$libresoc.v:129611$5046 + attribute \src "libresoc.v:131218.3-131236.6" + process $proc$libresoc.v:131218$5087 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129612.5-129612.29" + attribute \src "libresoc.v:131219.5-131219.29" switch \initial - attribute \src "libresoc.v:129612.9-129612.17" + attribute \src "libresoc.v:131219.9-131219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203909,18 +206329,18 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129630.3-129648.6" - process $proc$libresoc.v:129630$5047 + attribute \src "libresoc.v:131237.3-131255.6" + process $proc$libresoc.v:131237$5088 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129631.5-129631.29" + attribute \src "libresoc.v:131238.5-131238.29" switch \initial - attribute \src "libresoc.v:129631.9-129631.17" + attribute \src "libresoc.v:131238.9-131238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -203941,24 +206361,24 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129653.1-129705.10" +attribute \src "libresoc.v:131260.1-131312.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:129654.7-129654.20" + attribute \src "libresoc.v:131261.7-131261.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129667.3-129685.6" + attribute \src "libresoc.v:131274.3-131292.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129686.3-129704.6" + attribute \src "libresoc.v:131293.3-131311.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129667.3-129685.6" + attribute \src "libresoc.v:131274.3-131292.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129686.3-129704.6" + attribute \src "libresoc.v:131293.3-131311.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc - attribute \src "libresoc.v:129654.7-129654.15" + attribute \src "libresoc.v:131261.7-131261.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -203968,28 +206388,28 @@ module \dec_rc$151 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:129654.7-129654.20" - process $proc$libresoc.v:129654$5051 + attribute \src "libresoc.v:131261.7-131261.20" + process $proc$libresoc.v:131261$5092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129667.3-129685.6" - process $proc$libresoc.v:129667$5049 + attribute \src "libresoc.v:131274.3-131292.6" + process $proc$libresoc.v:131274$5090 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129668.5-129668.29" + attribute \src "libresoc.v:131275.5-131275.29" switch \initial - attribute \src "libresoc.v:129668.9-129668.17" + attribute \src "libresoc.v:131275.9-131275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204009,18 +206429,18 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129686.3-129704.6" - process $proc$libresoc.v:129686$5050 + attribute \src "libresoc.v:131293.3-131311.6" + process $proc$libresoc.v:131293$5091 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129687.5-129687.29" + attribute \src "libresoc.v:131294.5-131294.29" switch \initial - attribute \src "libresoc.v:129687.9-129687.17" + attribute \src "libresoc.v:131294.9-131294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204041,24 +206461,24 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129709.1-129763.10" +attribute \src "libresoc.v:131316.1-131370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:129710.7-129710.20" + attribute \src "libresoc.v:131317.7-131317.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129725.3-129743.6" + attribute \src "libresoc.v:131332.3-131350.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129744.3-129762.6" + attribute \src "libresoc.v:131351.3-131369.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129725.3-129743.6" + attribute \src "libresoc.v:131332.3-131350.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129744.3-129762.6" + attribute \src "libresoc.v:131351.3-131369.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc - attribute \src "libresoc.v:129710.7-129710.15" + attribute \src "libresoc.v:131317.7-131317.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204068,28 +206488,28 @@ module \dec_rc$154 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129710.7-129710.20" - process $proc$libresoc.v:129710$5054 + attribute \src "libresoc.v:131317.7-131317.20" + process $proc$libresoc.v:131317$5095 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129725.3-129743.6" - process $proc$libresoc.v:129725$5052 + attribute \src "libresoc.v:131332.3-131350.6" + process $proc$libresoc.v:131332$5093 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129726.5-129726.29" + attribute \src "libresoc.v:131333.5-131333.29" switch \initial - attribute \src "libresoc.v:129726.9-129726.17" + attribute \src "libresoc.v:131333.9-131333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204109,18 +206529,18 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129744.3-129762.6" - process $proc$libresoc.v:129744$5053 + attribute \src "libresoc.v:131351.3-131369.6" + process $proc$libresoc.v:131351$5094 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129745.5-129745.29" + attribute \src "libresoc.v:131352.5-131352.29" switch \initial - attribute \src "libresoc.v:129745.9-129745.17" + attribute \src "libresoc.v:131352.9-131352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204141,24 +206561,24 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129767.1-129821.10" +attribute \src "libresoc.v:131374.1-131428.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:129768.7-129768.20" + attribute \src "libresoc.v:131375.7-131375.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129783.3-129801.6" + attribute \src "libresoc.v:131390.3-131408.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129802.3-129820.6" + attribute \src "libresoc.v:131409.3-131427.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129783.3-129801.6" + attribute \src "libresoc.v:131390.3-131408.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129802.3-129820.6" + attribute \src "libresoc.v:131409.3-131427.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc - attribute \src "libresoc.v:129768.7-129768.15" + attribute \src "libresoc.v:131375.7-131375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204168,28 +206588,28 @@ module \dec_rc$159 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129768.7-129768.20" - process $proc$libresoc.v:129768$5057 + attribute \src "libresoc.v:131375.7-131375.20" + process $proc$libresoc.v:131375$5098 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129783.3-129801.6" - process $proc$libresoc.v:129783$5055 + attribute \src "libresoc.v:131390.3-131408.6" + process $proc$libresoc.v:131390$5096 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129784.5-129784.29" + attribute \src "libresoc.v:131391.5-131391.29" switch \initial - attribute \src "libresoc.v:129784.9-129784.17" + attribute \src "libresoc.v:131391.9-131391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204209,18 +206629,18 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129802.3-129820.6" - process $proc$libresoc.v:129802$5056 + attribute \src "libresoc.v:131409.3-131427.6" + process $proc$libresoc.v:131409$5097 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129803.5-129803.29" + attribute \src "libresoc.v:131410.5-131410.29" switch \initial - attribute \src "libresoc.v:129803.9-129803.17" + attribute \src "libresoc.v:131410.9-131410.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204241,24 +206661,24 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129825.1-129879.10" +attribute \src "libresoc.v:131432.1-131486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:129826.7-129826.20" + attribute \src "libresoc.v:131433.7-131433.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129841.3-129859.6" + attribute \src "libresoc.v:131448.3-131466.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129860.3-129878.6" + attribute \src "libresoc.v:131467.3-131485.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129841.3-129859.6" + attribute \src "libresoc.v:131448.3-131466.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129860.3-129878.6" + attribute \src "libresoc.v:131467.3-131485.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:129826.7-129826.15" + attribute \src "libresoc.v:131433.7-131433.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204268,28 +206688,28 @@ module \dec_rc$163 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129826.7-129826.20" - process $proc$libresoc.v:129826$5060 + attribute \src "libresoc.v:131433.7-131433.20" + process $proc$libresoc.v:131433$5101 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129841.3-129859.6" - process $proc$libresoc.v:129841$5058 + attribute \src "libresoc.v:131448.3-131466.6" + process $proc$libresoc.v:131448$5099 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129842.5-129842.29" + attribute \src "libresoc.v:131449.5-131449.29" switch \initial - attribute \src "libresoc.v:129842.9-129842.17" + attribute \src "libresoc.v:131449.9-131449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204309,18 +206729,18 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129860.3-129878.6" - process $proc$libresoc.v:129860$5059 + attribute \src "libresoc.v:131467.3-131485.6" + process $proc$libresoc.v:131467$5100 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129861.5-129861.29" + attribute \src "libresoc.v:131468.5-131468.29" switch \initial - attribute \src "libresoc.v:129861.9-129861.17" + attribute \src "libresoc.v:131468.9-131468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204341,24 +206761,24 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129883.1-129937.10" +attribute \src "libresoc.v:131490.1-131544.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:129884.7-129884.20" + attribute \src "libresoc.v:131491.7-131491.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129899.3-129917.6" + attribute \src "libresoc.v:131506.3-131524.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129918.3-129936.6" + attribute \src "libresoc.v:131525.3-131543.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129899.3-129917.6" + attribute \src "libresoc.v:131506.3-131524.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129918.3-129936.6" + attribute \src "libresoc.v:131525.3-131543.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc - attribute \src "libresoc.v:129884.7-129884.15" + attribute \src "libresoc.v:131491.7-131491.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204368,28 +206788,28 @@ module \dec_rc$167 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129884.7-129884.20" - process $proc$libresoc.v:129884$5063 + attribute \src "libresoc.v:131491.7-131491.20" + process $proc$libresoc.v:131491$5104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129899.3-129917.6" - process $proc$libresoc.v:129899$5061 + attribute \src "libresoc.v:131506.3-131524.6" + process $proc$libresoc.v:131506$5102 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129900.5-129900.29" + attribute \src "libresoc.v:131507.5-131507.29" switch \initial - attribute \src "libresoc.v:129900.9-129900.17" + attribute \src "libresoc.v:131507.9-131507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204409,18 +206829,18 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129918.3-129936.6" - process $proc$libresoc.v:129918$5062 + attribute \src "libresoc.v:131525.3-131543.6" + process $proc$libresoc.v:131525$5103 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129919.5-129919.29" + attribute \src "libresoc.v:131526.5-131526.29" switch \initial - attribute \src "libresoc.v:129919.9-129919.17" + attribute \src "libresoc.v:131526.9-131526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204441,24 +206861,24 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129941.1-129995.10" +attribute \src "libresoc.v:131548.1-131602.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:129942.7-129942.20" + attribute \src "libresoc.v:131549.7-131549.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129957.3-129975.6" + attribute \src "libresoc.v:131564.3-131582.6" wire $0\rc[0:0] - attribute \src "libresoc.v:129976.3-129994.6" + attribute \src "libresoc.v:131583.3-131601.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:129957.3-129975.6" + attribute \src "libresoc.v:131564.3-131582.6" wire $1\rc[0:0] - attribute \src "libresoc.v:129976.3-129994.6" + attribute \src "libresoc.v:131583.3-131601.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc - attribute \src "libresoc.v:129942.7-129942.15" + attribute \src "libresoc.v:131549.7-131549.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -204468,28 +206888,28 @@ module \dec_rc$172 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:129942.7-129942.20" - process $proc$libresoc.v:129942$5066 + attribute \src "libresoc.v:131549.7-131549.20" + process $proc$libresoc.v:131549$5107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129957.3-129975.6" - process $proc$libresoc.v:129957$5064 + attribute \src "libresoc.v:131564.3-131582.6" + process $proc$libresoc.v:131564$5105 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:129958.5-129958.29" + attribute \src "libresoc.v:131565.5-131565.29" switch \initial - attribute \src "libresoc.v:129958.9-129958.17" + attribute \src "libresoc.v:131565.9-131565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204509,18 +206929,18 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:129976.3-129994.6" - process $proc$libresoc.v:129976$5065 + attribute \src "libresoc.v:131583.3-131601.6" + process $proc$libresoc.v:131583$5106 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:129977.5-129977.29" + attribute \src "libresoc.v:131584.5-131584.29" switch \initial - attribute \src "libresoc.v:129977.9-129977.17" + attribute \src "libresoc.v:131584.9-131584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -204541,539 +206961,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:129999.1-131243.10" +attribute \src "libresoc.v:131606.1-132850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:130800.3-130801.25" + attribute \src "libresoc.v:132407.3-132408.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5206 - attribute \src "libresoc.v:130772.3-130773.75" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247 + attribute \src "libresoc.v:132379.3-132380.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 - attribute \src "libresoc.v:130742.3-130743.73" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + attribute \src "libresoc.v:132349.3-132350.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 - attribute \src "libresoc.v:130744.3-130745.87" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + attribute \src "libresoc.v:132351.3-132352.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 - attribute \src "libresoc.v:130746.3-130747.83" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + attribute \src "libresoc.v:132353.3-132354.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5210 - attribute \src "libresoc.v:130760.3-130761.81" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + attribute \src "libresoc.v:132367.3-132368.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5211 - attribute \src "libresoc.v:130774.3-130775.67" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252 + attribute \src "libresoc.v:132381.3-132382.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5212 - attribute \src "libresoc.v:130740.3-130741.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + attribute \src "libresoc.v:132347.3-132348.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$5213 - attribute \src "libresoc.v:130756.3-130757.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + attribute \src "libresoc.v:132363.3-132364.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$5214 - attribute \src "libresoc.v:130762.3-130763.79" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + attribute \src "libresoc.v:132369.3-132370.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 - attribute \src "libresoc.v:130768.3-130769.75" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + attribute \src "libresoc.v:132375.3-132376.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$5216 - attribute \src "libresoc.v:130770.3-130771.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + attribute \src "libresoc.v:132377.3-132378.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 - attribute \src "libresoc.v:130752.3-130753.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + attribute \src "libresoc.v:132359.3-132360.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 - attribute \src "libresoc.v:130754.3-130755.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + attribute \src "libresoc.v:132361.3-132362.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$5219 - attribute \src "libresoc.v:130766.3-130767.83" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + attribute \src "libresoc.v:132373.3-132374.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 - attribute \src "libresoc.v:130750.3-130751.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + attribute \src "libresoc.v:132357.3-132358.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 - attribute \src "libresoc.v:130748.3-130749.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + attribute \src "libresoc.v:132355.3-132356.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 - attribute \src "libresoc.v:130764.3-130765.77" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + attribute \src "libresoc.v:132371.3-132372.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$5223 - attribute \src "libresoc.v:130758.3-130759.71" + attribute \src "libresoc.v:132594.3-132632.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264 + attribute \src "libresoc.v:132365.3-132366.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130798.3-130799.40" + attribute \src "libresoc.v:132405.3-132406.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:131153.3-131161.6" - wire $0\alu_l_r_alu$next[0:0]$5293 - attribute \src "libresoc.v:130714.3-130715.39" + attribute \src "libresoc.v:132760.3-132768.6" + wire $0\alu_l_r_alu$next[0:0]$5334 + attribute \src "libresoc.v:132321.3-132322.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:131144.3-131152.6" - wire $0\alui_l_r_alui$next[0:0]$5290 - attribute \src "libresoc.v:130716.3-130717.43" + attribute \src "libresoc.v:132751.3-132759.6" + wire $0\alui_l_r_alui$next[0:0]$5331 + attribute \src "libresoc.v:132323.3-132324.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $0\data_r0__o$next[63:0]$5249 - attribute \src "libresoc.v:130736.3-130737.37" + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $0\data_r0__o$next[63:0]$5290 + attribute \src "libresoc.v:132343.3-132344.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire $0\data_r0__o_ok$next[0:0]$5250 - attribute \src "libresoc.v:130738.3-130739.43" + attribute \src "libresoc.v:132633.3-132654.6" + wire $0\data_r0__o_ok$next[0:0]$5291 + attribute \src "libresoc.v:132345.3-132346.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5257 - attribute \src "libresoc.v:130732.3-130733.43" + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5298 + attribute \src "libresoc.v:132339.3-132340.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5258 - attribute \src "libresoc.v:130734.3-130735.49" + attribute \src "libresoc.v:132655.3-132676.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5299 + attribute \src "libresoc.v:132341.3-132342.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$5265 - attribute \src "libresoc.v:130728.3-130729.47" + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5306 + attribute \src "libresoc.v:132335.3-132336.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$5266 - attribute \src "libresoc.v:130730.3-130731.53" + attribute \src "libresoc.v:132677.3-132698.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5307 + attribute \src "libresoc.v:132337.3-132338.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $0\data_r3__xer_so$next[0:0]$5273 - attribute \src "libresoc.v:130724.3-130725.47" + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so$next[0:0]$5314 + attribute \src "libresoc.v:132331.3-132332.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $0\data_r3__xer_so_ok$next[0:0]$5274 - attribute \src "libresoc.v:130726.3-130727.53" + attribute \src "libresoc.v:132699.3-132720.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5315 + attribute \src "libresoc.v:132333.3-132334.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:131162.3-131171.6" + attribute \src "libresoc.v:132769.3-132778.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:131172.3-131181.6" + attribute \src "libresoc.v:132779.3-132788.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:131182.3-131191.6" + attribute \src "libresoc.v:132789.3-132798.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:131192.3-131201.6" + attribute \src "libresoc.v:132799.3-132808.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:130000.7-130000.20" + attribute \src "libresoc.v:131607.7-131607.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130942.3-130950.6" - wire $0\opc_l_r_opc$next[0:0]$5191 - attribute \src "libresoc.v:130784.3-130785.39" + attribute \src "libresoc.v:132549.3-132557.6" + wire $0\opc_l_r_opc$next[0:0]$5232 + attribute \src "libresoc.v:132391.3-132392.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130933.3-130941.6" - wire $0\opc_l_s_opc$next[0:0]$5188 - attribute \src "libresoc.v:130786.3-130787.39" + attribute \src "libresoc.v:132540.3-132548.6" + wire $0\opc_l_s_opc$next[0:0]$5229 + attribute \src "libresoc.v:132393.3-132394.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:131202.3-131210.6" - wire width 4 $0\prev_wr_go$next[3:0]$5300 - attribute \src "libresoc.v:130796.3-130797.37" + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $0\prev_wr_go$next[3:0]$5341 + attribute \src "libresoc.v:132403.3-132404.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:130887.3-130896.6" + attribute \src "libresoc.v:132494.3-132503.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:130978.3-130986.6" - wire width 4 $0\req_l_r_req$next[3:0]$5203 - attribute \src "libresoc.v:130776.3-130777.39" + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $0\req_l_r_req$next[3:0]$5244 + attribute \src "libresoc.v:132383.3-132384.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:130969.3-130977.6" - wire width 4 $0\req_l_s_req$next[3:0]$5200 - attribute \src "libresoc.v:130778.3-130779.39" + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $0\req_l_s_req$next[3:0]$5241 + attribute \src "libresoc.v:132385.3-132386.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:130906.3-130914.6" - wire $0\rok_l_r_rdok$next[0:0]$5179 - attribute \src "libresoc.v:130792.3-130793.41" + attribute \src "libresoc.v:132513.3-132521.6" + wire $0\rok_l_r_rdok$next[0:0]$5220 + attribute \src "libresoc.v:132399.3-132400.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130897.3-130905.6" - wire $0\rok_l_s_rdok$next[0:0]$5176 - attribute \src "libresoc.v:130794.3-130795.41" + attribute \src "libresoc.v:132504.3-132512.6" + wire $0\rok_l_s_rdok$next[0:0]$5217 + attribute \src "libresoc.v:132401.3-132402.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130924.3-130932.6" - wire $0\rst_l_r_rst$next[0:0]$5185 - attribute \src "libresoc.v:130788.3-130789.39" + attribute \src "libresoc.v:132531.3-132539.6" + wire $0\rst_l_r_rst$next[0:0]$5226 + attribute \src "libresoc.v:132395.3-132396.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130915.3-130923.6" - wire $0\rst_l_s_rst$next[0:0]$5182 - attribute \src "libresoc.v:130790.3-130791.39" + attribute \src "libresoc.v:132522.3-132530.6" + wire $0\rst_l_s_rst$next[0:0]$5223 + attribute \src "libresoc.v:132397.3-132398.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130960.3-130968.6" - wire width 3 $0\src_l_r_src$next[2:0]$5197 - attribute \src "libresoc.v:130780.3-130781.39" + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $0\src_l_r_src$next[2:0]$5238 + attribute \src "libresoc.v:132387.3-132388.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:130951.3-130959.6" - wire width 3 $0\src_l_s_src$next[2:0]$5194 - attribute \src "libresoc.v:130782.3-130783.39" + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $0\src_l_s_src$next[2:0]$5235 + attribute \src "libresoc.v:132389.3-132390.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:131114.3-131123.6" - wire width 64 $0\src_r0$next[63:0]$5281 - attribute \src "libresoc.v:130722.3-130723.29" + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $0\src_r0$next[63:0]$5322 + attribute \src "libresoc.v:132329.3-132330.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:131124.3-131133.6" - wire width 64 $0\src_r1$next[63:0]$5284 - attribute \src "libresoc.v:130720.3-130721.29" + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $0\src_r1$next[63:0]$5325 + attribute \src "libresoc.v:132327.3-132328.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:131134.3-131143.6" - wire $0\src_r2$next[0:0]$5287 - attribute \src "libresoc.v:130718.3-130719.29" + attribute \src "libresoc.v:132741.3-132750.6" + wire $0\src_r2$next[0:0]$5328 + attribute \src "libresoc.v:132325.3-132326.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:130130.7-130130.24" + attribute \src "libresoc.v:131737.7-131737.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5224 - attribute \src "libresoc.v:130140.13-130140.49" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + attribute \src "libresoc.v:131747.13-131747.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 - attribute \src "libresoc.v:130159.14-130159.53" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 + attribute \src "libresoc.v:131766.14-131766.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 - attribute \src "libresoc.v:130163.14-130163.72" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + attribute \src "libresoc.v:131770.14-131770.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 - attribute \src "libresoc.v:130167.7-130167.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + attribute \src "libresoc.v:131774.7-131774.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 - attribute \src "libresoc.v:130175.13-130175.52" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + attribute \src "libresoc.v:131782.13-131782.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5229 - attribute \src "libresoc.v:130179.14-130179.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270 + attribute \src "libresoc.v:131786.14-131786.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 - attribute \src "libresoc.v:130258.13-130258.51" + attribute \src "libresoc.v:132594.3-132632.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + attribute \src "libresoc.v:131865.13-131865.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$5231 - attribute \src "libresoc.v:130262.7-130262.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + attribute \src "libresoc.v:131869.7-131869.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$5232 - attribute \src "libresoc.v:130266.7-130266.45" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + attribute \src "libresoc.v:131873.7-131873.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 - attribute \src "libresoc.v:130270.7-130270.43" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + attribute \src "libresoc.v:131877.7-131877.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$5234 - attribute \src "libresoc.v:130274.7-130274.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275 + attribute \src "libresoc.v:131881.7-131881.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 - attribute \src "libresoc.v:130278.7-130278.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + attribute \src "libresoc.v:131885.7-131885.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 - attribute \src "libresoc.v:130282.7-130282.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + attribute \src "libresoc.v:131889.7-131889.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$5237 - attribute \src "libresoc.v:130286.7-130286.47" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278 + attribute \src "libresoc.v:131893.7-131893.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 - attribute \src "libresoc.v:130290.7-130290.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + attribute \src "libresoc.v:131897.7-131897.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 - attribute \src "libresoc.v:130294.7-130294.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 + attribute \src "libresoc.v:131901.7-131901.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 - attribute \src "libresoc.v:130298.7-130298.44" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + attribute \src "libresoc.v:131905.7-131905.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$5241 - attribute \src "libresoc.v:130302.7-130302.41" + attribute \src "libresoc.v:132594.3-132632.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + attribute \src "libresoc.v:131909.7-131909.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130328.7-130328.26" + attribute \src "libresoc.v:131935.7-131935.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:131153.3-131161.6" - wire $1\alu_l_r_alu$next[0:0]$5294 - attribute \src "libresoc.v:130336.7-130336.25" + attribute \src "libresoc.v:132760.3-132768.6" + wire $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:131943.7-131943.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:131144.3-131152.6" - wire $1\alui_l_r_alui$next[0:0]$5291 - attribute \src "libresoc.v:130348.7-130348.27" + attribute \src "libresoc.v:132751.3-132759.6" + wire $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:131955.7-131955.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $1\data_r0__o$next[63:0]$5251 - attribute \src "libresoc.v:130382.14-130382.47" + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $1\data_r0__o$next[63:0]$5292 + attribute \src "libresoc.v:131989.14-131989.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:131026.3-131047.6" - wire $1\data_r0__o_ok$next[0:0]$5252 - attribute \src "libresoc.v:130386.7-130386.27" + attribute \src "libresoc.v:132633.3-132654.6" + wire $1\data_r0__o_ok$next[0:0]$5293 + attribute \src "libresoc.v:131993.7-131993.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5259 - attribute \src "libresoc.v:130390.13-130390.33" + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5300 + attribute \src "libresoc.v:131997.13-131997.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:131048.3-131069.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5260 - attribute \src "libresoc.v:130394.7-130394.30" + attribute \src "libresoc.v:132655.3-132676.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5301 + attribute \src "libresoc.v:132001.7-132001.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$5267 - attribute \src "libresoc.v:130398.13-130398.35" + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5308 + attribute \src "libresoc.v:132005.13-132005.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:131070.3-131091.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$5268 - attribute \src "libresoc.v:130402.7-130402.32" + attribute \src "libresoc.v:132677.3-132698.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5309 + attribute \src "libresoc.v:132009.7-132009.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $1\data_r3__xer_so$next[0:0]$5275 - attribute \src "libresoc.v:130406.7-130406.29" + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so$next[0:0]$5316 + attribute \src "libresoc.v:132013.7-132013.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:131092.3-131113.6" - wire $1\data_r3__xer_so_ok$next[0:0]$5276 - attribute \src "libresoc.v:130410.7-130410.32" + attribute \src "libresoc.v:132699.3-132720.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5317 + attribute \src "libresoc.v:132017.7-132017.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:131162.3-131171.6" + attribute \src "libresoc.v:132769.3-132778.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:131172.3-131181.6" + attribute \src "libresoc.v:132779.3-132788.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:131182.3-131191.6" + attribute \src "libresoc.v:132789.3-132798.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:131192.3-131201.6" + attribute \src "libresoc.v:132799.3-132808.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:130942.3-130950.6" - wire $1\opc_l_r_opc$next[0:0]$5192 - attribute \src "libresoc.v:130430.7-130430.25" + attribute \src "libresoc.v:132549.3-132557.6" + wire $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132037.7-132037.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130933.3-130941.6" - wire $1\opc_l_s_opc$next[0:0]$5189 - attribute \src "libresoc.v:130434.7-130434.25" + attribute \src "libresoc.v:132540.3-132548.6" + wire $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132041.7-132041.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:131202.3-131210.6" - wire width 4 $1\prev_wr_go$next[3:0]$5301 - attribute \src "libresoc.v:130568.13-130568.30" + attribute \src "libresoc.v:132809.3-132817.6" + wire width 4 $1\prev_wr_go$next[3:0]$5342 + attribute \src "libresoc.v:132175.13-132175.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:130887.3-130896.6" + attribute \src "libresoc.v:132494.3-132503.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:130978.3-130986.6" - wire width 4 $1\req_l_r_req$next[3:0]$5204 - attribute \src "libresoc.v:130576.13-130576.31" + attribute \src "libresoc.v:132585.3-132593.6" + wire width 4 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132183.13-132183.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:130969.3-130977.6" - wire width 4 $1\req_l_s_req$next[3:0]$5201 - attribute \src "libresoc.v:130580.13-130580.31" + attribute \src "libresoc.v:132576.3-132584.6" + wire width 4 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132187.13-132187.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:130906.3-130914.6" - wire $1\rok_l_r_rdok$next[0:0]$5180 - attribute \src "libresoc.v:130592.7-130592.26" + attribute \src "libresoc.v:132513.3-132521.6" + wire $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132199.7-132199.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130897.3-130905.6" - wire $1\rok_l_s_rdok$next[0:0]$5177 - attribute \src "libresoc.v:130596.7-130596.26" + attribute \src "libresoc.v:132504.3-132512.6" + wire $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132203.7-132203.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130924.3-130932.6" - wire $1\rst_l_r_rst$next[0:0]$5186 - attribute \src "libresoc.v:130600.7-130600.25" + attribute \src "libresoc.v:132531.3-132539.6" + wire $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132207.7-132207.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130915.3-130923.6" - wire $1\rst_l_s_rst$next[0:0]$5183 - attribute \src "libresoc.v:130604.7-130604.25" + attribute \src "libresoc.v:132522.3-132530.6" + wire $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132211.7-132211.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130960.3-130968.6" - wire width 3 $1\src_l_r_src$next[2:0]$5198 - attribute \src "libresoc.v:130618.13-130618.31" + attribute \src "libresoc.v:132567.3-132575.6" + wire width 3 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132225.13-132225.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:130951.3-130959.6" - wire width 3 $1\src_l_s_src$next[2:0]$5195 - attribute \src "libresoc.v:130622.13-130622.31" + attribute \src "libresoc.v:132558.3-132566.6" + wire width 3 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132229.13-132229.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:131114.3-131123.6" - wire width 64 $1\src_r0$next[63:0]$5282 - attribute \src "libresoc.v:130630.14-130630.43" + attribute \src "libresoc.v:132721.3-132730.6" + wire width 64 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132237.14-132237.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:131124.3-131133.6" - wire width 64 $1\src_r1$next[63:0]$5285 - attribute \src "libresoc.v:130634.14-130634.43" + attribute \src "libresoc.v:132731.3-132740.6" + wire width 64 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132241.14-132241.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:131134.3-131143.6" - wire $1\src_r2$next[0:0]$5288 - attribute \src "libresoc.v:130638.7-130638.20" + attribute \src "libresoc.v:132741.3-132750.6" + wire $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132245.7-132245.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:130987.3-131025.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 - attribute \src "libresoc.v:130987.3-131025.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 - attribute \src "libresoc.v:131026.3-131047.6" - wire width 64 $2\data_r0__o$next[63:0]$5253 - attribute \src "libresoc.v:131026.3-131047.6" - wire $2\data_r0__o_ok$next[0:0]$5254 - attribute \src "libresoc.v:131048.3-131069.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$5261 - attribute \src "libresoc.v:131048.3-131069.6" - wire $2\data_r1__cr_a_ok$next[0:0]$5262 - attribute \src "libresoc.v:131070.3-131091.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$5269 - attribute \src "libresoc.v:131070.3-131091.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$5270 - attribute \src "libresoc.v:131092.3-131113.6" - wire $2\data_r3__xer_so$next[0:0]$5277 - attribute \src "libresoc.v:131092.3-131113.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5278 - attribute \src "libresoc.v:131026.3-131047.6" - wire $3\data_r0__o_ok$next[0:0]$5255 - attribute \src "libresoc.v:131048.3-131069.6" - wire $3\data_r1__cr_a_ok$next[0:0]$5263 - attribute \src "libresoc.v:131070.3-131091.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$5271 - attribute \src "libresoc.v:131092.3-131113.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5279 - attribute \src "libresoc.v:130653.19-130653.133" - wire width 3 $and$libresoc.v:130653$5069_Y - attribute \src "libresoc.v:130655.19-130655.115" - wire width 3 $and$libresoc.v:130655$5071_Y - attribute \src "libresoc.v:130656.18-130656.110" - wire $and$libresoc.v:130656$5072_Y - attribute \src "libresoc.v:130657.19-130657.125" - wire $and$libresoc.v:130657$5073_Y - attribute \src "libresoc.v:130658.19-130658.125" - wire $and$libresoc.v:130658$5074_Y - attribute \src "libresoc.v:130659.19-130659.125" - wire $and$libresoc.v:130659$5075_Y - attribute \src "libresoc.v:130660.19-130660.125" - wire $and$libresoc.v:130660$5076_Y - attribute \src "libresoc.v:130661.19-130661.149" - wire width 4 $and$libresoc.v:130661$5077_Y - attribute \src "libresoc.v:130662.19-130662.121" - wire width 4 $and$libresoc.v:130662$5078_Y - attribute \src "libresoc.v:130663.19-130663.127" - wire $and$libresoc.v:130663$5079_Y - attribute \src "libresoc.v:130664.19-130664.127" - wire $and$libresoc.v:130664$5080_Y - attribute \src "libresoc.v:130665.19-130665.127" - wire $and$libresoc.v:130665$5081_Y - attribute \src "libresoc.v:130666.19-130666.127" - wire $and$libresoc.v:130666$5082_Y - attribute \src "libresoc.v:130668.18-130668.98" - wire $and$libresoc.v:130668$5084_Y - attribute \src "libresoc.v:130670.18-130670.100" - wire $and$libresoc.v:130670$5086_Y - attribute \src "libresoc.v:130671.18-130671.160" - wire width 4 $and$libresoc.v:130671$5087_Y - attribute \src "libresoc.v:130673.18-130673.119" - wire width 4 $and$libresoc.v:130673$5089_Y - attribute \src "libresoc.v:130676.17-130676.123" - wire $and$libresoc.v:130676$5092_Y - attribute \src "libresoc.v:130677.18-130677.116" - wire $and$libresoc.v:130677$5093_Y - attribute \src "libresoc.v:130682.18-130682.113" - wire $and$libresoc.v:130682$5098_Y - attribute \src "libresoc.v:130683.18-130683.125" - wire width 4 $and$libresoc.v:130683$5099_Y - attribute \src "libresoc.v:130685.18-130685.112" - wire $and$libresoc.v:130685$5101_Y - attribute \src "libresoc.v:130687.18-130687.126" - wire $and$libresoc.v:130687$5103_Y - attribute \src "libresoc.v:130688.18-130688.126" - wire $and$libresoc.v:130688$5104_Y - attribute \src "libresoc.v:130689.18-130689.117" - wire $and$libresoc.v:130689$5105_Y - attribute \src "libresoc.v:130695.18-130695.130" - wire $and$libresoc.v:130695$5111_Y - attribute \src "libresoc.v:130696.18-130696.124" - wire width 4 $and$libresoc.v:130696$5112_Y - attribute \src "libresoc.v:130698.18-130698.116" - wire $and$libresoc.v:130698$5114_Y - attribute \src "libresoc.v:130699.18-130699.119" - wire $and$libresoc.v:130699$5115_Y - attribute \src "libresoc.v:130700.18-130700.121" - wire $and$libresoc.v:130700$5116_Y - attribute \src "libresoc.v:130701.18-130701.121" - wire $and$libresoc.v:130701$5117_Y - attribute \src "libresoc.v:130711.18-130711.134" - wire $and$libresoc.v:130711$5127_Y - attribute \src "libresoc.v:130712.18-130712.132" - wire $and$libresoc.v:130712$5128_Y - attribute \src "libresoc.v:130713.18-130713.149" - wire width 3 $and$libresoc.v:130713$5129_Y - attribute \src "libresoc.v:130684.18-130684.113" - wire $eq$libresoc.v:130684$5100_Y - attribute \src "libresoc.v:130686.18-130686.119" - wire $eq$libresoc.v:130686$5102_Y - attribute \src "libresoc.v:130651.19-130651.130" - wire $not$libresoc.v:130651$5067_Y - attribute \src "libresoc.v:130652.19-130652.136" - wire $not$libresoc.v:130652$5068_Y - attribute \src "libresoc.v:130654.19-130654.115" - wire width 3 $not$libresoc.v:130654$5070_Y - attribute \src "libresoc.v:130667.18-130667.97" - wire $not$libresoc.v:130667$5083_Y - attribute \src "libresoc.v:130669.18-130669.99" - wire $not$libresoc.v:130669$5085_Y - attribute \src "libresoc.v:130672.18-130672.113" - wire width 4 $not$libresoc.v:130672$5088_Y - attribute \src "libresoc.v:130675.18-130675.106" - wire $not$libresoc.v:130675$5091_Y - attribute \src "libresoc.v:130681.18-130681.120" - wire $not$libresoc.v:130681$5097_Y - attribute \src "libresoc.v:130692.17-130692.113" - wire width 3 $not$libresoc.v:130692$5108_Y - attribute \src "libresoc.v:130680.18-130680.112" - wire $or$libresoc.v:130680$5096_Y - attribute \src "libresoc.v:130690.18-130690.122" - wire $or$libresoc.v:130690$5106_Y - attribute \src "libresoc.v:130691.18-130691.124" - wire $or$libresoc.v:130691$5107_Y - attribute \src "libresoc.v:130693.18-130693.168" - wire width 4 $or$libresoc.v:130693$5109_Y - attribute \src "libresoc.v:130694.18-130694.155" - wire width 3 $or$libresoc.v:130694$5110_Y - attribute \src "libresoc.v:130697.18-130697.120" - wire width 4 $or$libresoc.v:130697$5113_Y - attribute \src "libresoc.v:130703.17-130703.117" - wire width 3 $or$libresoc.v:130703$5119_Y - attribute \src "libresoc.v:130708.17-130708.104" - wire $reduce_and$libresoc.v:130708$5124_Y - attribute \src "libresoc.v:130674.18-130674.106" - wire $reduce_or$libresoc.v:130674$5090_Y - attribute \src "libresoc.v:130678.18-130678.113" - wire $reduce_or$libresoc.v:130678$5094_Y - attribute \src "libresoc.v:130679.18-130679.112" - wire $reduce_or$libresoc.v:130679$5095_Y - attribute \src "libresoc.v:130702.18-130702.158" - wire $ternary$libresoc.v:130702$5118_Y - attribute \src "libresoc.v:130704.18-130704.159" - wire width 64 $ternary$libresoc.v:130704$5120_Y - attribute \src "libresoc.v:130705.18-130705.164" - wire $ternary$libresoc.v:130705$5121_Y - attribute \src "libresoc.v:130706.18-130706.180" - wire width 64 $ternary$libresoc.v:130706$5122_Y - attribute \src "libresoc.v:130707.18-130707.115" - wire width 64 $ternary$libresoc.v:130707$5123_Y - attribute \src "libresoc.v:130709.18-130709.125" - wire width 64 $ternary$libresoc.v:130709$5125_Y - attribute \src "libresoc.v:130710.18-130710.118" - wire $ternary$libresoc.v:130710$5126_Y + attribute \src "libresoc.v:132594.3-132632.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + attribute \src "libresoc.v:132594.3-132632.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132633.3-132654.6" + wire width 64 $2\data_r0__o$next[63:0]$5294 + attribute \src "libresoc.v:132633.3-132654.6" + wire $2\data_r0__o_ok$next[0:0]$5295 + attribute \src "libresoc.v:132655.3-132676.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5302 + attribute \src "libresoc.v:132655.3-132676.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5303 + attribute \src "libresoc.v:132677.3-132698.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5310 + attribute \src "libresoc.v:132677.3-132698.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5311 + attribute \src "libresoc.v:132699.3-132720.6" + wire $2\data_r3__xer_so$next[0:0]$5318 + attribute \src "libresoc.v:132699.3-132720.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5319 + attribute \src "libresoc.v:132633.3-132654.6" + wire $3\data_r0__o_ok$next[0:0]$5296 + attribute \src "libresoc.v:132655.3-132676.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5304 + attribute \src "libresoc.v:132677.3-132698.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5312 + attribute \src "libresoc.v:132699.3-132720.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5320 + attribute \src "libresoc.v:132260.19-132260.133" + wire width 3 $and$libresoc.v:132260$5110_Y + attribute \src "libresoc.v:132262.19-132262.115" + wire width 3 $and$libresoc.v:132262$5112_Y + attribute \src "libresoc.v:132263.18-132263.110" + wire $and$libresoc.v:132263$5113_Y + attribute \src "libresoc.v:132264.19-132264.125" + wire $and$libresoc.v:132264$5114_Y + attribute \src "libresoc.v:132265.19-132265.125" + wire $and$libresoc.v:132265$5115_Y + attribute \src "libresoc.v:132266.19-132266.125" + wire $and$libresoc.v:132266$5116_Y + attribute \src "libresoc.v:132267.19-132267.125" + wire $and$libresoc.v:132267$5117_Y + attribute \src "libresoc.v:132268.19-132268.149" + wire width 4 $and$libresoc.v:132268$5118_Y + attribute \src "libresoc.v:132269.19-132269.121" + wire width 4 $and$libresoc.v:132269$5119_Y + attribute \src "libresoc.v:132270.19-132270.127" + wire $and$libresoc.v:132270$5120_Y + attribute \src "libresoc.v:132271.19-132271.127" + wire $and$libresoc.v:132271$5121_Y + attribute \src "libresoc.v:132272.19-132272.127" + wire $and$libresoc.v:132272$5122_Y + attribute \src "libresoc.v:132273.19-132273.127" + wire $and$libresoc.v:132273$5123_Y + attribute \src "libresoc.v:132275.18-132275.98" + wire $and$libresoc.v:132275$5125_Y + attribute \src "libresoc.v:132277.18-132277.100" + wire $and$libresoc.v:132277$5127_Y + attribute \src "libresoc.v:132278.18-132278.160" + wire width 4 $and$libresoc.v:132278$5128_Y + attribute \src "libresoc.v:132280.18-132280.119" + wire width 4 $and$libresoc.v:132280$5130_Y + attribute \src "libresoc.v:132283.17-132283.123" + wire $and$libresoc.v:132283$5133_Y + attribute \src "libresoc.v:132284.18-132284.116" + wire $and$libresoc.v:132284$5134_Y + attribute \src "libresoc.v:132289.18-132289.113" + wire $and$libresoc.v:132289$5139_Y + attribute \src "libresoc.v:132290.18-132290.125" + wire width 4 $and$libresoc.v:132290$5140_Y + attribute \src "libresoc.v:132292.18-132292.112" + wire $and$libresoc.v:132292$5142_Y + attribute \src "libresoc.v:132294.18-132294.126" + wire $and$libresoc.v:132294$5144_Y + attribute \src "libresoc.v:132295.18-132295.126" + wire $and$libresoc.v:132295$5145_Y + attribute \src "libresoc.v:132296.18-132296.117" + wire $and$libresoc.v:132296$5146_Y + attribute \src "libresoc.v:132302.18-132302.130" + wire $and$libresoc.v:132302$5152_Y + attribute \src "libresoc.v:132303.18-132303.124" + wire width 4 $and$libresoc.v:132303$5153_Y + attribute \src "libresoc.v:132305.18-132305.116" + wire $and$libresoc.v:132305$5155_Y + attribute \src "libresoc.v:132306.18-132306.119" + wire $and$libresoc.v:132306$5156_Y + attribute \src "libresoc.v:132307.18-132307.121" + wire $and$libresoc.v:132307$5157_Y + attribute \src "libresoc.v:132308.18-132308.121" + wire $and$libresoc.v:132308$5158_Y + attribute \src "libresoc.v:132318.18-132318.134" + wire $and$libresoc.v:132318$5168_Y + attribute \src "libresoc.v:132319.18-132319.132" + wire $and$libresoc.v:132319$5169_Y + attribute \src "libresoc.v:132320.18-132320.149" + wire width 3 $and$libresoc.v:132320$5170_Y + attribute \src "libresoc.v:132291.18-132291.113" + wire $eq$libresoc.v:132291$5141_Y + attribute \src "libresoc.v:132293.18-132293.119" + wire $eq$libresoc.v:132293$5143_Y + attribute \src "libresoc.v:132258.19-132258.130" + wire $not$libresoc.v:132258$5108_Y + attribute \src "libresoc.v:132259.19-132259.136" + wire $not$libresoc.v:132259$5109_Y + attribute \src "libresoc.v:132261.19-132261.115" + wire width 3 $not$libresoc.v:132261$5111_Y + attribute \src "libresoc.v:132274.18-132274.97" + wire $not$libresoc.v:132274$5124_Y + attribute \src "libresoc.v:132276.18-132276.99" + wire $not$libresoc.v:132276$5126_Y + attribute \src "libresoc.v:132279.18-132279.113" + wire width 4 $not$libresoc.v:132279$5129_Y + attribute \src "libresoc.v:132282.18-132282.106" + wire $not$libresoc.v:132282$5132_Y + attribute \src "libresoc.v:132288.18-132288.120" + wire $not$libresoc.v:132288$5138_Y + attribute \src "libresoc.v:132299.17-132299.113" + wire width 3 $not$libresoc.v:132299$5149_Y + attribute \src "libresoc.v:132287.18-132287.112" + wire $or$libresoc.v:132287$5137_Y + attribute \src "libresoc.v:132297.18-132297.122" + wire $or$libresoc.v:132297$5147_Y + attribute \src "libresoc.v:132298.18-132298.124" + wire $or$libresoc.v:132298$5148_Y + attribute \src "libresoc.v:132300.18-132300.168" + wire width 4 $or$libresoc.v:132300$5150_Y + attribute \src "libresoc.v:132301.18-132301.155" + wire width 3 $or$libresoc.v:132301$5151_Y + attribute \src "libresoc.v:132304.18-132304.120" + wire width 4 $or$libresoc.v:132304$5154_Y + attribute \src "libresoc.v:132310.17-132310.117" + wire width 3 $or$libresoc.v:132310$5160_Y + attribute \src "libresoc.v:132315.17-132315.104" + wire $reduce_and$libresoc.v:132315$5165_Y + attribute \src "libresoc.v:132281.18-132281.106" + wire $reduce_or$libresoc.v:132281$5131_Y + attribute \src "libresoc.v:132285.18-132285.113" + wire $reduce_or$libresoc.v:132285$5135_Y + attribute \src "libresoc.v:132286.18-132286.112" + wire $reduce_or$libresoc.v:132286$5136_Y + attribute \src "libresoc.v:132309.18-132309.158" + wire $ternary$libresoc.v:132309$5159_Y + attribute \src "libresoc.v:132311.18-132311.159" + wire width 64 $ternary$libresoc.v:132311$5161_Y + attribute \src "libresoc.v:132312.18-132312.164" + wire $ternary$libresoc.v:132312$5162_Y + attribute \src "libresoc.v:132313.18-132313.180" + wire width 64 $ternary$libresoc.v:132313$5163_Y + attribute \src "libresoc.v:132314.18-132314.115" + wire width 64 $ternary$libresoc.v:132314$5164_Y + attribute \src "libresoc.v:132316.18-132316.125" + wire width 64 $ternary$libresoc.v:132316$5166_Y + attribute \src "libresoc.v:132317.18-132317.118" + wire $ternary$libresoc.v:132317$5167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -205426,9 +207846,9 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -205494,7 +207914,7 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:130000.7-130000.15" + attribute \src "libresoc.v:131607.7-131607.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -205723,7 +208143,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130653$5069 + cell $and $and$libresoc.v:132260$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -205731,10 +208151,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:130653$5069_Y + connect \Y $and$libresoc.v:132260$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130655$5071 + cell $and $and$libresoc.v:132262$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -205742,10 +208162,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:130655$5071_Y + connect \Y $and$libresoc.v:132262$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:130656$5072 + cell $and $and$libresoc.v:132263$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205753,10 +208173,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:130656$5072_Y + connect \Y $and$libresoc.v:132263$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130657$5073 + cell $and $and$libresoc.v:132264$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205764,10 +208184,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130657$5073_Y + connect \Y $and$libresoc.v:132264$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130658$5074 + cell $and $and$libresoc.v:132265$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205775,10 +208195,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130658$5074_Y + connect \Y $and$libresoc.v:132265$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130659$5075 + cell $and $and$libresoc.v:132266$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205786,10 +208206,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130659$5075_Y + connect \Y $and$libresoc.v:132266$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130660$5076 + cell $and $and$libresoc.v:132267$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205797,10 +208217,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130660$5076_Y + connect \Y $and$libresoc.v:132267$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130661$5077 + cell $and $and$libresoc.v:132268$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205808,10 +208228,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:130661$5077_Y + connect \Y $and$libresoc.v:132268$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130662$5078 + cell $and $and$libresoc.v:132269$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205819,10 +208239,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130662$5078_Y + connect \Y $and$libresoc.v:132269$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130663$5079 + cell $and $and$libresoc.v:132270$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205830,10 +208250,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130663$5079_Y + connect \Y $and$libresoc.v:132270$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130664$5080 + cell $and $and$libresoc.v:132271$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205841,10 +208261,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130664$5080_Y + connect \Y $and$libresoc.v:132271$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130665$5081 + cell $and $and$libresoc.v:132272$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205852,10 +208272,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130665$5081_Y + connect \Y $and$libresoc.v:132272$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130666$5082 + cell $and $and$libresoc.v:132273$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205863,10 +208283,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130666$5082_Y + connect \Y $and$libresoc.v:132273$5123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:130668$5084 + cell $and $and$libresoc.v:132275$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205874,10 +208294,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:130668$5084_Y + connect \Y $and$libresoc.v:132275$5125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:130670$5086 + cell $and $and$libresoc.v:132277$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205885,10 +208305,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:130670$5086_Y + connect \Y $and$libresoc.v:132277$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:130671$5087 + cell $and $and$libresoc.v:132278$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205896,10 +208316,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130671$5087_Y + connect \Y $and$libresoc.v:132278$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130673$5089 + cell $and $and$libresoc.v:132280$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205907,10 +208327,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:130673$5089_Y + connect \Y $and$libresoc.v:132280$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:130676$5092 + cell $and $and$libresoc.v:132283$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205918,10 +208338,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:130676$5092_Y + connect \Y $and$libresoc.v:132283$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130677$5093 + cell $and $and$libresoc.v:132284$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205929,10 +208349,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:130677$5093_Y + connect \Y $and$libresoc.v:132284$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:130682$5098 + cell $and $and$libresoc.v:132289$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205940,10 +208360,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:130682$5098_Y + connect \Y $and$libresoc.v:132289$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130683$5099 + cell $and $and$libresoc.v:132290$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -205951,10 +208371,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130683$5099_Y + connect \Y $and$libresoc.v:132290$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130685$5101 + cell $and $and$libresoc.v:132292$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205962,10 +208382,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:130685$5101_Y + connect \Y $and$libresoc.v:132292$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130687$5103 + cell $and $and$libresoc.v:132294$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205973,10 +208393,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:130687$5103_Y + connect \Y $and$libresoc.v:132294$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130688$5104 + cell $and $and$libresoc.v:132295$5145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205984,10 +208404,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:130688$5104_Y + connect \Y $and$libresoc.v:132295$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130689$5105 + cell $and $and$libresoc.v:132296$5146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -205995,10 +208415,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:130689$5105_Y + connect \Y $and$libresoc.v:132296$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:130695$5111 + cell $and $and$libresoc.v:132302$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206006,10 +208426,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:130695$5111_Y + connect \Y $and$libresoc.v:132302$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:130696$5112 + cell $and $and$libresoc.v:132303$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206017,10 +208437,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130696$5112_Y + connect \Y $and$libresoc.v:132303$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130698$5114 + cell $and $and$libresoc.v:132305$5155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206028,10 +208448,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130698$5114_Y + connect \Y $and$libresoc.v:132305$5155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130699$5115 + cell $and $and$libresoc.v:132306$5156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206039,10 +208459,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130699$5115_Y + connect \Y $and$libresoc.v:132306$5156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130700$5116 + cell $and $and$libresoc.v:132307$5157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206050,10 +208470,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130700$5116_Y + connect \Y $and$libresoc.v:132307$5157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130701$5117 + cell $and $and$libresoc.v:132308$5158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206061,10 +208481,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130701$5117_Y + connect \Y $and$libresoc.v:132308$5158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:130711$5127 + cell $and $and$libresoc.v:132318$5168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206072,10 +208492,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:130711$5127_Y + connect \Y $and$libresoc.v:132318$5168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:130712$5128 + cell $and $and$libresoc.v:132319$5169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206083,10 +208503,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:130712$5128_Y + connect \Y $and$libresoc.v:132319$5169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130713$5129 + cell $and $and$libresoc.v:132320$5170 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206094,10 +208514,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130713$5129_Y + connect \Y $and$libresoc.v:132320$5170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:130684$5100 + cell $eq $eq$libresoc.v:132291$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206105,10 +208525,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:130684$5100_Y + connect \Y $eq$libresoc.v:132291$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:130686$5102 + cell $eq $eq$libresoc.v:132293$5143 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206116,82 +208536,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:130686$5102_Y + connect \Y $eq$libresoc.v:132293$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130651$5067 + cell $not $not$libresoc.v:132258$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:130651$5067_Y + connect \Y $not$libresoc.v:132258$5108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130652$5068 + cell $not $not$libresoc.v:132259$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:130652$5068_Y + connect \Y $not$libresoc.v:132259$5109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:130654$5070 + cell $not $not$libresoc.v:132261$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:130654$5070_Y + connect \Y $not$libresoc.v:132261$5111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:130667$5083 + cell $not $not$libresoc.v:132274$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:130667$5083_Y + connect \Y $not$libresoc.v:132274$5124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:130669$5085 + cell $not $not$libresoc.v:132276$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:130669$5085_Y + connect \Y $not$libresoc.v:132276$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130672$5088 + cell $not $not$libresoc.v:132279$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:130672$5088_Y + connect \Y $not$libresoc.v:132279$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130675$5091 + cell $not $not$libresoc.v:132282$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:130675$5091_Y + connect \Y $not$libresoc.v:132282$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:130681$5097 + cell $not $not$libresoc.v:132288$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:130681$5097_Y + connect \Y $not$libresoc.v:132288$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:130692$5108 + cell $not $not$libresoc.v:132299$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:130692$5108_Y + connect \Y $not$libresoc.v:132299$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:130680$5096 + cell $or $or$libresoc.v:132287$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206199,10 +208619,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:130680$5096_Y + connect \Y $or$libresoc.v:132287$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:130690$5106 + cell $or $or$libresoc.v:132297$5147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206210,10 +208630,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130690$5106_Y + connect \Y $or$libresoc.v:132297$5147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:130691$5107 + cell $or $or$libresoc.v:132298$5148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -206221,10 +208641,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130691$5107_Y + connect \Y $or$libresoc.v:132298$5148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:130693$5109 + cell $or $or$libresoc.v:132300$5150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206232,10 +208652,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130693$5109_Y + connect \Y $or$libresoc.v:132300$5150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:130694$5110 + cell $or $or$libresoc.v:132301$5151 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206243,10 +208663,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130694$5110_Y + connect \Y $or$libresoc.v:132301$5151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:130697$5113 + cell $or $or$libresoc.v:132304$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -206254,10 +208674,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:130697$5113_Y + connect \Y $or$libresoc.v:132304$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:130703$5119 + cell $or $or$libresoc.v:132310$5160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -206265,98 +208685,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:130703$5119_Y + connect \Y $or$libresoc.v:132310$5160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:130708$5124 + cell $reduce_and $reduce_and$libresoc.v:132315$5165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:130708$5124_Y + connect \Y $reduce_and$libresoc.v:132315$5165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:130674$5090 + cell $reduce_or $reduce_or$libresoc.v:132281$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:130674$5090_Y + connect \Y $reduce_or$libresoc.v:132281$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130678$5094 + cell $reduce_or $reduce_or$libresoc.v:132285$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:130678$5094_Y + connect \Y $reduce_or$libresoc.v:132285$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130679$5095 + cell $reduce_or $reduce_or$libresoc.v:132286$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:130679$5095_Y + connect \Y $reduce_or$libresoc.v:132286$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130702$5118 + cell $mux $ternary$libresoc.v:132309$5159 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130702$5118_Y + connect \Y $ternary$libresoc.v:132309$5159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130704$5120 + cell $mux $ternary$libresoc.v:132311$5161 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130704$5120_Y + connect \Y $ternary$libresoc.v:132311$5161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130705$5121 + cell $mux $ternary$libresoc.v:132312$5162 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130705$5121_Y + connect \Y $ternary$libresoc.v:132312$5162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130706$5122 + cell $mux $ternary$libresoc.v:132313$5163 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130706$5122_Y + connect \Y $ternary$libresoc.v:132313$5163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130707$5123 + cell $mux $ternary$libresoc.v:132314$5164 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:130707$5123_Y + connect \Y $ternary$libresoc.v:132314$5164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130709$5125 + cell $mux $ternary$libresoc.v:132316$5166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:130709$5125_Y + connect \Y $ternary$libresoc.v:132316$5166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:130710$5126 + cell $mux $ternary$libresoc.v:132317$5167 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:130710$5126_Y + connect \Y $ternary$libresoc.v:132317$5167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:130802.12-130838.4" + attribute \src "libresoc.v:132409.12-132445.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206395,7 +208815,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:130839.14-130845.4" + attribute \src "libresoc.v:132446.14-132452.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206404,7 +208824,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:130846.15-130852.4" + attribute \src "libresoc.v:132453.15-132459.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206413,7 +208833,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:130853.14-130859.4" + attribute \src "libresoc.v:132460.14-132466.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206422,7 +208842,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:130860.14-130866.4" + attribute \src "libresoc.v:132467.14-132473.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206431,7 +208851,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:130867.14-130873.4" + attribute \src "libresoc.v:132474.14-132480.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206440,7 +208860,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:130874.14-130879.4" + attribute \src "libresoc.v:132481.14-132486.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206448,7 +208868,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:130880.14-130886.4" + attribute \src "libresoc.v:132487.14-132493.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -206456,682 +208876,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:130000.7-130000.20" - process $proc$libresoc.v:130000$5302 + attribute \src "libresoc.v:131607.7-131607.20" + process $proc$libresoc.v:131607$5343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130130.7-130130.24" - process $proc$libresoc.v:130130$5303 + attribute \src "libresoc.v:131737.7-131737.24" + process $proc$libresoc.v:131737$5344 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:130140.13-130140.49" - process $proc$libresoc.v:130140$5304 + attribute \src "libresoc.v:131747.13-131747.49" + process $proc$libresoc.v:131747$5345 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:130159.14-130159.53" - process $proc$libresoc.v:130159$5305 + attribute \src "libresoc.v:131766.14-131766.53" + process $proc$libresoc.v:131766$5346 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:130163.14-130163.72" - process $proc$libresoc.v:130163$5306 + attribute \src "libresoc.v:131770.14-131770.72" + process $proc$libresoc.v:131770$5347 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130167.7-130167.47" - process $proc$libresoc.v:130167$5307 + attribute \src "libresoc.v:131774.7-131774.47" + process $proc$libresoc.v:131774$5348 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130175.13-130175.52" - process $proc$libresoc.v:130175$5308 + attribute \src "libresoc.v:131782.13-131782.52" + process $proc$libresoc.v:131782$5349 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:130179.14-130179.47" - process $proc$libresoc.v:130179$5309 + attribute \src "libresoc.v:131786.14-131786.47" + process $proc$libresoc.v:131786$5350 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:130258.13-130258.51" - process $proc$libresoc.v:130258$5310 + attribute \src "libresoc.v:131865.13-131865.51" + process $proc$libresoc.v:131865$5351 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:130262.7-130262.44" - process $proc$libresoc.v:130262$5311 + attribute \src "libresoc.v:131869.7-131869.44" + process $proc$libresoc.v:131869$5352 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:130266.7-130266.45" - process $proc$libresoc.v:130266$5312 + attribute \src "libresoc.v:131873.7-131873.45" + process $proc$libresoc.v:131873$5353 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:130270.7-130270.43" - process $proc$libresoc.v:130270$5313 + attribute \src "libresoc.v:131877.7-131877.43" + process $proc$libresoc.v:131877$5354 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:130274.7-130274.44" - process $proc$libresoc.v:130274$5314 + attribute \src "libresoc.v:131881.7-131881.44" + process $proc$libresoc.v:131881$5355 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:130278.7-130278.41" - process $proc$libresoc.v:130278$5315 + attribute \src "libresoc.v:131885.7-131885.41" + process $proc$libresoc.v:131885$5356 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:130282.7-130282.41" - process $proc$libresoc.v:130282$5316 + attribute \src "libresoc.v:131889.7-131889.41" + process $proc$libresoc.v:131889$5357 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:130286.7-130286.47" - process $proc$libresoc.v:130286$5317 + attribute \src "libresoc.v:131893.7-131893.47" + process $proc$libresoc.v:131893$5358 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:130290.7-130290.41" - process $proc$libresoc.v:130290$5318 + attribute \src "libresoc.v:131897.7-131897.41" + process $proc$libresoc.v:131897$5359 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:130294.7-130294.41" - process $proc$libresoc.v:130294$5319 + attribute \src "libresoc.v:131901.7-131901.41" + process $proc$libresoc.v:131901$5360 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:130298.7-130298.44" - process $proc$libresoc.v:130298$5320 + attribute \src "libresoc.v:131905.7-131905.44" + process $proc$libresoc.v:131905$5361 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:130302.7-130302.41" - process $proc$libresoc.v:130302$5321 + attribute \src "libresoc.v:131909.7-131909.41" + process $proc$libresoc.v:131909$5362 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:130328.7-130328.26" - process $proc$libresoc.v:130328$5322 + attribute \src "libresoc.v:131935.7-131935.26" + process $proc$libresoc.v:131935$5363 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:130336.7-130336.25" - process $proc$libresoc.v:130336$5323 + attribute \src "libresoc.v:131943.7-131943.25" + process $proc$libresoc.v:131943$5364 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:130348.7-130348.27" - process $proc$libresoc.v:130348$5324 + attribute \src "libresoc.v:131955.7-131955.27" + process $proc$libresoc.v:131955$5365 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:130382.14-130382.47" - process $proc$libresoc.v:130382$5325 + attribute \src "libresoc.v:131989.14-131989.47" + process $proc$libresoc.v:131989$5366 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:130386.7-130386.27" - process $proc$libresoc.v:130386$5326 + attribute \src "libresoc.v:131993.7-131993.27" + process $proc$libresoc.v:131993$5367 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:130390.13-130390.33" - process $proc$libresoc.v:130390$5327 + attribute \src "libresoc.v:131997.13-131997.33" + process $proc$libresoc.v:131997$5368 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:130394.7-130394.30" - process $proc$libresoc.v:130394$5328 + attribute \src "libresoc.v:132001.7-132001.30" + process $proc$libresoc.v:132001$5369 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:130398.13-130398.35" - process $proc$libresoc.v:130398$5329 + attribute \src "libresoc.v:132005.13-132005.35" + process $proc$libresoc.v:132005$5370 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:130402.7-130402.32" - process $proc$libresoc.v:130402$5330 + attribute \src "libresoc.v:132009.7-132009.32" + process $proc$libresoc.v:132009$5371 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:130406.7-130406.29" - process $proc$libresoc.v:130406$5331 + attribute \src "libresoc.v:132013.7-132013.29" + process $proc$libresoc.v:132013$5372 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:130410.7-130410.32" - process $proc$libresoc.v:130410$5332 + attribute \src "libresoc.v:132017.7-132017.32" + process $proc$libresoc.v:132017$5373 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:130430.7-130430.25" - process $proc$libresoc.v:130430$5333 + attribute \src "libresoc.v:132037.7-132037.25" + process $proc$libresoc.v:132037$5374 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130434.7-130434.25" - process $proc$libresoc.v:130434$5334 + attribute \src "libresoc.v:132041.7-132041.25" + process $proc$libresoc.v:132041$5375 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130568.13-130568.30" - process $proc$libresoc.v:130568$5335 + attribute \src "libresoc.v:132175.13-132175.30" + process $proc$libresoc.v:132175$5376 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:130576.13-130576.31" - process $proc$libresoc.v:130576$5336 + attribute \src "libresoc.v:132183.13-132183.31" + process $proc$libresoc.v:132183$5377 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:130580.13-130580.31" - process $proc$libresoc.v:130580$5337 + attribute \src "libresoc.v:132187.13-132187.31" + process $proc$libresoc.v:132187$5378 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:130592.7-130592.26" - process $proc$libresoc.v:130592$5338 + attribute \src "libresoc.v:132199.7-132199.26" + process $proc$libresoc.v:132199$5379 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130596.7-130596.26" - process $proc$libresoc.v:130596$5339 + attribute \src "libresoc.v:132203.7-132203.26" + process $proc$libresoc.v:132203$5380 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130600.7-130600.25" - process $proc$libresoc.v:130600$5340 + attribute \src "libresoc.v:132207.7-132207.25" + process $proc$libresoc.v:132207$5381 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130604.7-130604.25" - process $proc$libresoc.v:130604$5341 + attribute \src "libresoc.v:132211.7-132211.25" + process $proc$libresoc.v:132211$5382 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130618.13-130618.31" - process $proc$libresoc.v:130618$5342 + attribute \src "libresoc.v:132225.13-132225.31" + process $proc$libresoc.v:132225$5383 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:130622.13-130622.31" - process $proc$libresoc.v:130622$5343 + attribute \src "libresoc.v:132229.13-132229.31" + process $proc$libresoc.v:132229$5384 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:130630.14-130630.43" - process $proc$libresoc.v:130630$5344 + attribute \src "libresoc.v:132237.14-132237.43" + process $proc$libresoc.v:132237$5385 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:130634.14-130634.43" - process $proc$libresoc.v:130634$5345 + attribute \src "libresoc.v:132241.14-132241.43" + process $proc$libresoc.v:132241$5386 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:130638.7-130638.20" - process $proc$libresoc.v:130638$5346 + attribute \src "libresoc.v:132245.7-132245.20" + process $proc$libresoc.v:132245$5387 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:130714.3-130715.39" - process $proc$libresoc.v:130714$5130 + attribute \src "libresoc.v:132321.3-132322.39" + process $proc$libresoc.v:132321$5171 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:130716.3-130717.43" - process $proc$libresoc.v:130716$5131 + attribute \src "libresoc.v:132323.3-132324.43" + process $proc$libresoc.v:132323$5172 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:130718.3-130719.29" - process $proc$libresoc.v:130718$5132 + attribute \src "libresoc.v:132325.3-132326.29" + process $proc$libresoc.v:132325$5173 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:130720.3-130721.29" - process $proc$libresoc.v:130720$5133 + attribute \src "libresoc.v:132327.3-132328.29" + process $proc$libresoc.v:132327$5174 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:130722.3-130723.29" - process $proc$libresoc.v:130722$5134 + attribute \src "libresoc.v:132329.3-132330.29" + process $proc$libresoc.v:132329$5175 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:130724.3-130725.47" - process $proc$libresoc.v:130724$5135 + attribute \src "libresoc.v:132331.3-132332.47" + process $proc$libresoc.v:132331$5176 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:130726.3-130727.53" - process $proc$libresoc.v:130726$5136 + attribute \src "libresoc.v:132333.3-132334.53" + process $proc$libresoc.v:132333$5177 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:130728.3-130729.47" - process $proc$libresoc.v:130728$5137 + attribute \src "libresoc.v:132335.3-132336.47" + process $proc$libresoc.v:132335$5178 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:130730.3-130731.53" - process $proc$libresoc.v:130730$5138 + attribute \src "libresoc.v:132337.3-132338.53" + process $proc$libresoc.v:132337$5179 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:130732.3-130733.43" - process $proc$libresoc.v:130732$5139 + attribute \src "libresoc.v:132339.3-132340.43" + process $proc$libresoc.v:132339$5180 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:130734.3-130735.49" - process $proc$libresoc.v:130734$5140 + attribute \src "libresoc.v:132341.3-132342.49" + process $proc$libresoc.v:132341$5181 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:130736.3-130737.37" - process $proc$libresoc.v:130736$5141 + attribute \src "libresoc.v:132343.3-132344.37" + process $proc$libresoc.v:132343$5182 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:130738.3-130739.43" - process $proc$libresoc.v:130738$5142 + attribute \src "libresoc.v:132345.3-132346.43" + process $proc$libresoc.v:132345$5183 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:130740.3-130741.77" - process $proc$libresoc.v:130740$5143 + attribute \src "libresoc.v:132347.3-132348.77" + process $proc$libresoc.v:132347$5184 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:130742.3-130743.73" - process $proc$libresoc.v:130742$5144 + attribute \src "libresoc.v:132349.3-132350.73" + process $proc$libresoc.v:132349$5185 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:130744.3-130745.87" - process $proc$libresoc.v:130744$5145 + attribute \src "libresoc.v:132351.3-132352.87" + process $proc$libresoc.v:132351$5186 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130746.3-130747.83" - process $proc$libresoc.v:130746$5146 + attribute \src "libresoc.v:132353.3-132354.83" + process $proc$libresoc.v:132353$5187 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130748.3-130749.71" - process $proc$libresoc.v:130748$5147 + attribute \src "libresoc.v:132355.3-132356.71" + process $proc$libresoc.v:132355$5188 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:130750.3-130751.71" - process $proc$libresoc.v:130750$5148 + attribute \src "libresoc.v:132357.3-132358.71" + process $proc$libresoc.v:132357$5189 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:130752.3-130753.71" - process $proc$libresoc.v:130752$5149 + attribute \src "libresoc.v:132359.3-132360.71" + process $proc$libresoc.v:132359$5190 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:130754.3-130755.71" - process $proc$libresoc.v:130754$5150 + attribute \src "libresoc.v:132361.3-132362.71" + process $proc$libresoc.v:132361$5191 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:130756.3-130757.77" - process $proc$libresoc.v:130756$5151 + attribute \src "libresoc.v:132363.3-132364.77" + process $proc$libresoc.v:132363$5192 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:130758.3-130759.71" - process $proc$libresoc.v:130758$5152 + attribute \src "libresoc.v:132365.3-132366.71" + process $proc$libresoc.v:132365$5193 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:130760.3-130761.81" - process $proc$libresoc.v:130760$5153 + attribute \src "libresoc.v:132367.3-132368.81" + process $proc$libresoc.v:132367$5194 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:130762.3-130763.79" - process $proc$libresoc.v:130762$5154 + attribute \src "libresoc.v:132369.3-132370.79" + process $proc$libresoc.v:132369$5195 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:130764.3-130765.77" - process $proc$libresoc.v:130764$5155 + attribute \src "libresoc.v:132371.3-132372.77" + process $proc$libresoc.v:132371$5196 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:130766.3-130767.83" - process $proc$libresoc.v:130766$5156 + attribute \src "libresoc.v:132373.3-132374.83" + process $proc$libresoc.v:132373$5197 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:130768.3-130769.75" - process $proc$libresoc.v:130768$5157 + attribute \src "libresoc.v:132375.3-132376.75" + process $proc$libresoc.v:132375$5198 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:130770.3-130771.77" - process $proc$libresoc.v:130770$5158 + attribute \src "libresoc.v:132377.3-132378.77" + process $proc$libresoc.v:132377$5199 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:130772.3-130773.75" - process $proc$libresoc.v:130772$5159 + attribute \src "libresoc.v:132379.3-132380.75" + process $proc$libresoc.v:132379$5200 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:130774.3-130775.67" - process $proc$libresoc.v:130774$5160 + attribute \src "libresoc.v:132381.3-132382.67" + process $proc$libresoc.v:132381$5201 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:130776.3-130777.39" - process $proc$libresoc.v:130776$5161 + attribute \src "libresoc.v:132383.3-132384.39" + process $proc$libresoc.v:132383$5202 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:130778.3-130779.39" - process $proc$libresoc.v:130778$5162 + attribute \src "libresoc.v:132385.3-132386.39" + process $proc$libresoc.v:132385$5203 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:130780.3-130781.39" - process $proc$libresoc.v:130780$5163 + attribute \src "libresoc.v:132387.3-132388.39" + process $proc$libresoc.v:132387$5204 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:130782.3-130783.39" - process $proc$libresoc.v:130782$5164 + attribute \src "libresoc.v:132389.3-132390.39" + process $proc$libresoc.v:132389$5205 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:130784.3-130785.39" - process $proc$libresoc.v:130784$5165 + attribute \src "libresoc.v:132391.3-132392.39" + process $proc$libresoc.v:132391$5206 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130786.3-130787.39" - process $proc$libresoc.v:130786$5166 + attribute \src "libresoc.v:132393.3-132394.39" + process $proc$libresoc.v:132393$5207 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130788.3-130789.39" - process $proc$libresoc.v:130788$5167 + attribute \src "libresoc.v:132395.3-132396.39" + process $proc$libresoc.v:132395$5208 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130790.3-130791.39" - process $proc$libresoc.v:130790$5168 + attribute \src "libresoc.v:132397.3-132398.39" + process $proc$libresoc.v:132397$5209 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130792.3-130793.41" - process $proc$libresoc.v:130792$5169 + attribute \src "libresoc.v:132399.3-132400.41" + process $proc$libresoc.v:132399$5210 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130794.3-130795.41" - process $proc$libresoc.v:130794$5170 + attribute \src "libresoc.v:132401.3-132402.41" + process $proc$libresoc.v:132401$5211 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130796.3-130797.37" - process $proc$libresoc.v:130796$5171 + attribute \src "libresoc.v:132403.3-132404.37" + process $proc$libresoc.v:132403$5212 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:130798.3-130799.40" - process $proc$libresoc.v:130798$5172 + attribute \src "libresoc.v:132405.3-132406.40" + process $proc$libresoc.v:132405$5213 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:130800.3-130801.25" - process $proc$libresoc.v:130800$5173 + attribute \src "libresoc.v:132407.3-132408.25" + process $proc$libresoc.v:132407$5214 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:130887.3-130896.6" - process $proc$libresoc.v:130887$5174 + attribute \src "libresoc.v:132494.3-132503.6" + process $proc$libresoc.v:132494$5215 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:130888.5-130888.29" + attribute \src "libresoc.v:132495.5-132495.29" switch \initial - attribute \src "libresoc.v:130888.9-130888.17" + attribute \src "libresoc.v:132495.9-132495.17" case 1'1 case end @@ -207147,14 +209567,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:130897.3-130905.6" - process $proc$libresoc.v:130897$5175 + attribute \src "libresoc.v:132504.3-132512.6" + process $proc$libresoc.v:132504$5216 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5176 $1\rok_l_s_rdok$next[0:0]$5177 - attribute \src "libresoc.v:130898.5-130898.29" + assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218 + attribute \src "libresoc.v:132505.5-132505.29" switch \initial - attribute \src "libresoc.v:130898.9-130898.17" + attribute \src "libresoc.v:132505.9-132505.17" case 1'1 case end @@ -207163,21 +209583,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5177 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5218 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$5177 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$5218 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5176 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217 end - attribute \src "libresoc.v:130906.3-130914.6" - process $proc$libresoc.v:130906$5178 + attribute \src "libresoc.v:132513.3-132521.6" + process $proc$libresoc.v:132513$5219 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5179 $1\rok_l_r_rdok$next[0:0]$5180 - attribute \src "libresoc.v:130907.5-130907.29" + assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221 + attribute \src "libresoc.v:132514.5-132514.29" switch \initial - attribute \src "libresoc.v:130907.9-130907.17" + attribute \src "libresoc.v:132514.9-132514.17" case 1'1 case end @@ -207186,21 +209606,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5180 1'1 + assign $1\rok_l_r_rdok$next[0:0]$5221 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$5180 \$64 + assign $1\rok_l_r_rdok$next[0:0]$5221 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5179 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220 end - attribute \src "libresoc.v:130915.3-130923.6" - process $proc$libresoc.v:130915$5181 + attribute \src "libresoc.v:132522.3-132530.6" + process $proc$libresoc.v:132522$5222 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5182 $1\rst_l_s_rst$next[0:0]$5183 - attribute \src "libresoc.v:130916.5-130916.29" + assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224 + attribute \src "libresoc.v:132523.5-132523.29" switch \initial - attribute \src "libresoc.v:130916.9-130916.17" + attribute \src "libresoc.v:132523.9-132523.17" case 1'1 case end @@ -207209,21 +209629,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5183 1'0 + assign $1\rst_l_s_rst$next[0:0]$5224 1'0 case - assign $1\rst_l_s_rst$next[0:0]$5183 \all_rd + assign $1\rst_l_s_rst$next[0:0]$5224 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5182 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223 end - attribute \src "libresoc.v:130924.3-130932.6" - process $proc$libresoc.v:130924$5184 + attribute \src "libresoc.v:132531.3-132539.6" + process $proc$libresoc.v:132531$5225 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5185 $1\rst_l_r_rst$next[0:0]$5186 - attribute \src "libresoc.v:130925.5-130925.29" + assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227 + attribute \src "libresoc.v:132532.5-132532.29" switch \initial - attribute \src "libresoc.v:130925.9-130925.17" + attribute \src "libresoc.v:132532.9-132532.17" case 1'1 case end @@ -207232,21 +209652,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5186 1'1 + assign $1\rst_l_r_rst$next[0:0]$5227 1'1 case - assign $1\rst_l_r_rst$next[0:0]$5186 \rst_r + assign $1\rst_l_r_rst$next[0:0]$5227 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5185 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226 end - attribute \src "libresoc.v:130933.3-130941.6" - process $proc$libresoc.v:130933$5187 + attribute \src "libresoc.v:132540.3-132548.6" + process $proc$libresoc.v:132540$5228 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5188 $1\opc_l_s_opc$next[0:0]$5189 - attribute \src "libresoc.v:130934.5-130934.29" + assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230 + attribute \src "libresoc.v:132541.5-132541.29" switch \initial - attribute \src "libresoc.v:130934.9-130934.17" + attribute \src "libresoc.v:132541.9-132541.17" case 1'1 case end @@ -207255,21 +209675,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5189 1'0 + assign $1\opc_l_s_opc$next[0:0]$5230 1'0 case - assign $1\opc_l_s_opc$next[0:0]$5189 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$5230 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5188 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229 end - attribute \src "libresoc.v:130942.3-130950.6" - process $proc$libresoc.v:130942$5190 + attribute \src "libresoc.v:132549.3-132557.6" + process $proc$libresoc.v:132549$5231 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5191 $1\opc_l_r_opc$next[0:0]$5192 - attribute \src "libresoc.v:130943.5-130943.29" + assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233 + attribute \src "libresoc.v:132550.5-132550.29" switch \initial - attribute \src "libresoc.v:130943.9-130943.17" + attribute \src "libresoc.v:132550.9-132550.17" case 1'1 case end @@ -207278,21 +209698,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5192 1'1 + assign $1\opc_l_r_opc$next[0:0]$5233 1'1 case - assign $1\opc_l_r_opc$next[0:0]$5192 \req_done + assign $1\opc_l_r_opc$next[0:0]$5233 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5191 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232 end - attribute \src "libresoc.v:130951.3-130959.6" - process $proc$libresoc.v:130951$5193 + attribute \src "libresoc.v:132558.3-132566.6" + process $proc$libresoc.v:132558$5234 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$5194 $1\src_l_s_src$next[2:0]$5195 - attribute \src "libresoc.v:130952.5-130952.29" + assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236 + attribute \src "libresoc.v:132559.5-132559.29" switch \initial - attribute \src "libresoc.v:130952.9-130952.17" + attribute \src "libresoc.v:132559.9-132559.17" case 1'1 case end @@ -207301,21 +209721,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$5195 3'000 + assign $1\src_l_s_src$next[2:0]$5236 3'000 case - assign $1\src_l_s_src$next[2:0]$5195 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$5236 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5194 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235 end - attribute \src "libresoc.v:130960.3-130968.6" - process $proc$libresoc.v:130960$5196 + attribute \src "libresoc.v:132567.3-132575.6" + process $proc$libresoc.v:132567$5237 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$5197 $1\src_l_r_src$next[2:0]$5198 - attribute \src "libresoc.v:130961.5-130961.29" + assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239 + attribute \src "libresoc.v:132568.5-132568.29" switch \initial - attribute \src "libresoc.v:130961.9-130961.17" + attribute \src "libresoc.v:132568.9-132568.17" case 1'1 case end @@ -207324,21 +209744,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$5198 3'111 + assign $1\src_l_r_src$next[2:0]$5239 3'111 case - assign $1\src_l_r_src$next[2:0]$5198 \reset_r + assign $1\src_l_r_src$next[2:0]$5239 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5197 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238 end - attribute \src "libresoc.v:130969.3-130977.6" - process $proc$libresoc.v:130969$5199 + attribute \src "libresoc.v:132576.3-132584.6" + process $proc$libresoc.v:132576$5240 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$5200 $1\req_l_s_req$next[3:0]$5201 - attribute \src "libresoc.v:130970.5-130970.29" + assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242 + attribute \src "libresoc.v:132577.5-132577.29" switch \initial - attribute \src "libresoc.v:130970.9-130970.17" + attribute \src "libresoc.v:132577.9-132577.17" case 1'1 case end @@ -207347,21 +209767,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$5201 4'0000 + assign $1\req_l_s_req$next[3:0]$5242 4'0000 case - assign $1\req_l_s_req$next[3:0]$5201 \$66 + assign $1\req_l_s_req$next[3:0]$5242 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5200 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241 end - attribute \src "libresoc.v:130978.3-130986.6" - process $proc$libresoc.v:130978$5202 + attribute \src "libresoc.v:132585.3-132593.6" + process $proc$libresoc.v:132585$5243 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$5203 $1\req_l_r_req$next[3:0]$5204 - attribute \src "libresoc.v:130979.5-130979.29" + assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245 + attribute \src "libresoc.v:132586.5-132586.29" switch \initial - attribute \src "libresoc.v:130979.9-130979.17" + attribute \src "libresoc.v:132586.9-132586.17" case 1'1 case end @@ -207370,15 +209790,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$5204 4'1111 + assign $1\req_l_r_req$next[3:0]$5245 4'1111 case - assign $1\req_l_r_req$next[3:0]$5204 \$68 + assign $1\req_l_r_req$next[3:0]$5245 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5203 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244 end - attribute \src "libresoc.v:130987.3-131025.6" - process $proc$libresoc.v:130987$5205 + attribute \src "libresoc.v:132594.3-132632.6" + process $proc$libresoc.v:132594$5246 assign { } { } assign { } { } assign { } { } @@ -207415,33 +209835,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$5206 $1\alu_div0_logical_op__data_len$next[3:0]$5224 - assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 + assign $0\alu_div0_logical_op__data_len$next[3:0]$5247 $1\alu_div0_logical_op__data_len$next[3:0]$5265 + assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$5210 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 - assign $0\alu_div0_logical_op__insn$next[31:0]$5211 $1\alu_div0_logical_op__insn$next[31:0]$5229 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$5212 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$5213 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$5214 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$5216 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5251 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 + assign $0\alu_div0_logical_op__insn$next[31:0]$5252 $1\alu_div0_logical_op__insn$next[31:0]$5270 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5253 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5254 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5255 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5257 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$5219 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5260 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$5223 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 - attribute \src "libresoc.v:130988.5-130988.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5264 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 + attribute \src "libresoc.v:132595.5-132595.29" switch \initial - attribute \src "libresoc.v:130988.9-130988.17" + attribute \src "libresoc.v:132595.9-132595.17" case 1'1 case end @@ -207467,26 +209887,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$5229 $1\alu_div0_logical_op__data_len$next[3:0]$5224 $1\alu_div0_logical_op__is_signed$next[0:0]$5234 $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 $1\alu_div0_logical_op__output_carry$next[0:0]$5237 $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 $1\alu_div0_logical_op__invert_out$next[0:0]$5232 $1\alu_div0_logical_op__input_carry$next[1:0]$5228 $1\alu_div0_logical_op__zero_a$next[0:0]$5241 $1\alu_div0_logical_op__invert_in$next[0:0]$5231 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 $1\alu_div0_logical_op__insn_type$next[6:0]$5230 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5270 $1\alu_div0_logical_op__data_len$next[3:0]$5265 $1\alu_div0_logical_op__is_signed$next[0:0]$5275 $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 $1\alu_div0_logical_op__output_carry$next[0:0]$5278 $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 $1\alu_div0_logical_op__invert_out$next[0:0]$5273 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 $1\alu_div0_logical_op__zero_a$next[0:0]$5282 $1\alu_div0_logical_op__invert_in$next[0:0]$5272 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$5224 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5225 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$5228 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$5229 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$5230 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$5231 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$5232 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5233 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$5234 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$5237 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5240 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$5241 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$5265 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5269 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5270 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5271 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5272 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5273 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5275 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5278 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5282 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -207498,54 +209918,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5242 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5226 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5243 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5227 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5244 $1\alu_div0_logical_op__oe__oe$next[0:0]$5235 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5245 $1\alu_div0_logical_op__oe__ok$next[0:0]$5236 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5238 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5247 $1\alu_div0_logical_op__rc__rc$next[0:0]$5239 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5206 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5207 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5208 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5209 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5210 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5211 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5212 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5213 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5214 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5215 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5216 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5217 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5218 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5219 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5220 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5221 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5222 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5223 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5247 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5251 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5252 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5253 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5254 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5255 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5257 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5260 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264 end - attribute \src "libresoc.v:131026.3-131047.6" - process $proc$libresoc.v:131026$5248 + attribute \src "libresoc.v:132633.3-132654.6" + process $proc$libresoc.v:132633$5289 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$5249 $2\data_r0__o$next[63:0]$5253 + assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5250 $3\data_r0__o_ok$next[0:0]$5255 - attribute \src "libresoc.v:131027.5-131027.29" + assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296 + attribute \src "libresoc.v:132634.5-132634.29" switch \initial - attribute \src "libresoc.v:131027.9-131027.17" + attribute \src "libresoc.v:132634.9-132634.17" case 1'1 case end @@ -207555,10 +209975,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5252 $1\data_r0__o$next[63:0]$5251 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$5293 $1\data_r0__o$next[63:0]$5292 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$5251 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5252 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$5292 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5293 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207566,38 +209986,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5254 $2\data_r0__o$next[63:0]$5253 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o$next[63:0]$5294 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$5253 $1\data_r0__o$next[63:0]$5251 - assign $2\data_r0__o_ok$next[0:0]$5254 $1\data_r0__o_ok$next[0:0]$5252 + assign $2\data_r0__o$next[63:0]$5294 $1\data_r0__o$next[63:0]$5292 + assign $2\data_r0__o_ok$next[0:0]$5295 $1\data_r0__o_ok$next[0:0]$5293 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5255 1'0 + assign $3\data_r0__o_ok$next[0:0]$5296 1'0 case - assign $3\data_r0__o_ok$next[0:0]$5255 $2\data_r0__o_ok$next[0:0]$5254 + assign $3\data_r0__o_ok$next[0:0]$5296 $2\data_r0__o_ok$next[0:0]$5295 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5249 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5250 + update \data_r0__o$next $0\data_r0__o$next[63:0]$5290 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291 end - attribute \src "libresoc.v:131048.3-131069.6" - process $proc$libresoc.v:131048$5256 + attribute \src "libresoc.v:132655.3-132676.6" + process $proc$libresoc.v:132655$5297 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5257 $2\data_r1__cr_a$next[3:0]$5261 + assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5258 $3\data_r1__cr_a_ok$next[0:0]$5263 - attribute \src "libresoc.v:131049.5-131049.29" + assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304 + attribute \src "libresoc.v:132656.5-132656.29" switch \initial - attribute \src "libresoc.v:131049.9-131049.17" + attribute \src "libresoc.v:132656.9-132656.17" case 1'1 case end @@ -207607,10 +210027,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5260 $1\data_r1__cr_a$next[3:0]$5259 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$5301 $1\data_r1__cr_a$next[3:0]$5300 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$5259 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5260 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$5300 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5301 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207618,38 +210038,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5262 $2\data_r1__cr_a$next[3:0]$5261 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a$next[3:0]$5302 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$5261 $1\data_r1__cr_a$next[3:0]$5259 - assign $2\data_r1__cr_a_ok$next[0:0]$5262 $1\data_r1__cr_a_ok$next[0:0]$5260 + assign $2\data_r1__cr_a$next[3:0]$5302 $1\data_r1__cr_a$next[3:0]$5300 + assign $2\data_r1__cr_a_ok$next[0:0]$5303 $1\data_r1__cr_a_ok$next[0:0]$5301 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5263 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$5304 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$5263 $2\data_r1__cr_a_ok$next[0:0]$5262 + assign $3\data_r1__cr_a_ok$next[0:0]$5304 $2\data_r1__cr_a_ok$next[0:0]$5303 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5257 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5258 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299 end - attribute \src "libresoc.v:131070.3-131091.6" - process $proc$libresoc.v:131070$5264 + attribute \src "libresoc.v:132677.3-132698.6" + process $proc$libresoc.v:132677$5305 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$5265 $2\data_r2__xer_ov$next[1:0]$5269 + assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$5266 $3\data_r2__xer_ov_ok$next[0:0]$5271 - attribute \src "libresoc.v:131071.5-131071.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312 + attribute \src "libresoc.v:132678.5-132678.29" switch \initial - attribute \src "libresoc.v:131071.9-131071.17" + attribute \src "libresoc.v:132678.9-132678.17" case 1'1 case end @@ -207659,10 +210079,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$5268 $1\data_r2__xer_ov$next[1:0]$5267 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5309 $1\data_r2__xer_ov$next[1:0]$5308 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$5267 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$5268 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$5308 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5309 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207670,38 +210090,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$5270 $2\data_r2__xer_ov$next[1:0]$5269 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov$next[1:0]$5310 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$5269 $1\data_r2__xer_ov$next[1:0]$5267 - assign $2\data_r2__xer_ov_ok$next[0:0]$5270 $1\data_r2__xer_ov_ok$next[0:0]$5268 + assign $2\data_r2__xer_ov$next[1:0]$5310 $1\data_r2__xer_ov$next[1:0]$5308 + assign $2\data_r2__xer_ov_ok$next[0:0]$5311 $1\data_r2__xer_ov_ok$next[0:0]$5309 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$5271 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$5271 $2\data_r2__xer_ov_ok$next[0:0]$5270 + assign $3\data_r2__xer_ov_ok$next[0:0]$5312 $2\data_r2__xer_ov_ok$next[0:0]$5311 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5265 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5266 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307 end - attribute \src "libresoc.v:131092.3-131113.6" - process $proc$libresoc.v:131092$5272 + attribute \src "libresoc.v:132699.3-132720.6" + process $proc$libresoc.v:132699$5313 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$5273 $2\data_r3__xer_so$next[0:0]$5277 + assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$5274 $3\data_r3__xer_so_ok$next[0:0]$5279 - attribute \src "libresoc.v:131093.5-131093.29" + assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320 + attribute \src "libresoc.v:132700.5-132700.29" switch \initial - attribute \src "libresoc.v:131093.9-131093.17" + attribute \src "libresoc.v:132700.9-132700.17" case 1'1 case end @@ -207711,10 +210131,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$5276 $1\data_r3__xer_so$next[0:0]$5275 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5316 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$5275 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$5276 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$5316 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5317 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -207722,32 +210142,32 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5278 $2\data_r3__xer_so$next[0:0]$5277 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so$next[0:0]$5318 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$5277 $1\data_r3__xer_so$next[0:0]$5275 - assign $2\data_r3__xer_so_ok$next[0:0]$5278 $1\data_r3__xer_so_ok$next[0:0]$5276 + assign $2\data_r3__xer_so$next[0:0]$5318 $1\data_r3__xer_so$next[0:0]$5316 + assign $2\data_r3__xer_so_ok$next[0:0]$5319 $1\data_r3__xer_so_ok$next[0:0]$5317 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5279 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5320 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$5279 $2\data_r3__xer_so_ok$next[0:0]$5278 + assign $3\data_r3__xer_so_ok$next[0:0]$5320 $2\data_r3__xer_so_ok$next[0:0]$5319 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5273 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5274 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315 end - attribute \src "libresoc.v:131114.3-131123.6" - process $proc$libresoc.v:131114$5280 + attribute \src "libresoc.v:132721.3-132730.6" + process $proc$libresoc.v:132721$5321 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$5281 $1\src_r0$next[63:0]$5282 - attribute \src "libresoc.v:131115.5-131115.29" + assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323 + attribute \src "libresoc.v:132722.5-132722.29" switch \initial - attribute \src "libresoc.v:131115.9-131115.17" + attribute \src "libresoc.v:132722.9-132722.17" case 1'1 case end @@ -207756,21 +210176,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$5282 \src_or_imm + assign $1\src_r0$next[63:0]$5323 \src_or_imm case - assign $1\src_r0$next[63:0]$5282 \src_r0 + assign $1\src_r0$next[63:0]$5323 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$5281 + update \src_r0$next $0\src_r0$next[63:0]$5322 end - attribute \src "libresoc.v:131124.3-131133.6" - process $proc$libresoc.v:131124$5283 + attribute \src "libresoc.v:132731.3-132740.6" + process $proc$libresoc.v:132731$5324 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$5284 $1\src_r1$next[63:0]$5285 - attribute \src "libresoc.v:131125.5-131125.29" + assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326 + attribute \src "libresoc.v:132732.5-132732.29" switch \initial - attribute \src "libresoc.v:131125.9-131125.17" + attribute \src "libresoc.v:132732.9-132732.17" case 1'1 case end @@ -207779,21 +210199,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$5285 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5326 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$5285 \src_r1 + assign $1\src_r1$next[63:0]$5326 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$5284 + update \src_r1$next $0\src_r1$next[63:0]$5325 end - attribute \src "libresoc.v:131134.3-131143.6" - process $proc$libresoc.v:131134$5286 + attribute \src "libresoc.v:132741.3-132750.6" + process $proc$libresoc.v:132741$5327 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$5287 $1\src_r2$next[0:0]$5288 - attribute \src "libresoc.v:131135.5-131135.29" + assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329 + attribute \src "libresoc.v:132742.5-132742.29" switch \initial - attribute \src "libresoc.v:131135.9-131135.17" + attribute \src "libresoc.v:132742.9-132742.17" case 1'1 case end @@ -207802,21 +210222,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$5288 \src3_i + assign $1\src_r2$next[0:0]$5329 \src3_i case - assign $1\src_r2$next[0:0]$5288 \src_r2 + assign $1\src_r2$next[0:0]$5329 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$5287 + update \src_r2$next $0\src_r2$next[0:0]$5328 end - attribute \src "libresoc.v:131144.3-131152.6" - process $proc$libresoc.v:131144$5289 + attribute \src "libresoc.v:132751.3-132759.6" + process $proc$libresoc.v:132751$5330 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5290 $1\alui_l_r_alui$next[0:0]$5291 - attribute \src "libresoc.v:131145.5-131145.29" + assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332 + attribute \src "libresoc.v:132752.5-132752.29" switch \initial - attribute \src "libresoc.v:131145.9-131145.17" + attribute \src "libresoc.v:132752.9-132752.17" case 1'1 case end @@ -207825,21 +210245,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5291 1'1 + assign $1\alui_l_r_alui$next[0:0]$5332 1'1 case - assign $1\alui_l_r_alui$next[0:0]$5291 \$94 + assign $1\alui_l_r_alui$next[0:0]$5332 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5290 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331 end - attribute \src "libresoc.v:131153.3-131161.6" - process $proc$libresoc.v:131153$5292 + attribute \src "libresoc.v:132760.3-132768.6" + process $proc$libresoc.v:132760$5333 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5293 $1\alu_l_r_alu$next[0:0]$5294 - attribute \src "libresoc.v:131154.5-131154.29" + assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335 + attribute \src "libresoc.v:132761.5-132761.29" switch \initial - attribute \src "libresoc.v:131154.9-131154.17" + attribute \src "libresoc.v:132761.9-132761.17" case 1'1 case end @@ -207848,21 +210268,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5294 1'1 + assign $1\alu_l_r_alu$next[0:0]$5335 1'1 case - assign $1\alu_l_r_alu$next[0:0]$5294 \$96 + assign $1\alu_l_r_alu$next[0:0]$5335 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5293 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5334 end - attribute \src "libresoc.v:131162.3-131171.6" - process $proc$libresoc.v:131162$5295 + attribute \src "libresoc.v:132769.3-132778.6" + process $proc$libresoc.v:132769$5336 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:131163.5-131163.29" + attribute \src "libresoc.v:132770.5-132770.29" switch \initial - attribute \src "libresoc.v:131163.9-131163.17" + attribute \src "libresoc.v:132770.9-132770.17" case 1'1 case end @@ -207878,14 +210298,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:131172.3-131181.6" - process $proc$libresoc.v:131172$5296 + attribute \src "libresoc.v:132779.3-132788.6" + process $proc$libresoc.v:132779$5337 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:131173.5-131173.29" + attribute \src "libresoc.v:132780.5-132780.29" switch \initial - attribute \src "libresoc.v:131173.9-131173.17" + attribute \src "libresoc.v:132780.9-132780.17" case 1'1 case end @@ -207901,14 +210321,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:131182.3-131191.6" - process $proc$libresoc.v:131182$5297 + attribute \src "libresoc.v:132789.3-132798.6" + process $proc$libresoc.v:132789$5338 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:131183.5-131183.29" + attribute \src "libresoc.v:132790.5-132790.29" switch \initial - attribute \src "libresoc.v:131183.9-131183.17" + attribute \src "libresoc.v:132790.9-132790.17" case 1'1 case end @@ -207924,14 +210344,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:131192.3-131201.6" - process $proc$libresoc.v:131192$5298 + attribute \src "libresoc.v:132799.3-132808.6" + process $proc$libresoc.v:132799$5339 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:131193.5-131193.29" + attribute \src "libresoc.v:132800.5-132800.29" switch \initial - attribute \src "libresoc.v:131193.9-131193.17" + attribute \src "libresoc.v:132800.9-132800.17" case 1'1 case end @@ -207947,14 +210367,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:131202.3-131210.6" - process $proc$libresoc.v:131202$5299 + attribute \src "libresoc.v:132809.3-132817.6" + process $proc$libresoc.v:132809$5340 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$5300 $1\prev_wr_go$next[3:0]$5301 - attribute \src "libresoc.v:131203.5-131203.29" + assign $0\prev_wr_go$next[3:0]$5341 $1\prev_wr_go$next[3:0]$5342 + attribute \src "libresoc.v:132810.5-132810.29" switch \initial - attribute \src "libresoc.v:131203.9-131203.17" + attribute \src "libresoc.v:132810.9-132810.17" case 1'1 case end @@ -207963,76 +210383,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$5301 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5301 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5300 - end - connect \$100 $not$libresoc.v:130651$5067_Y - connect \$102 $not$libresoc.v:130652$5068_Y - connect \$104 $and$libresoc.v:130653$5069_Y - connect \$106 $not$libresoc.v:130654$5070_Y - connect \$108 $and$libresoc.v:130655$5071_Y - connect \$10 $and$libresoc.v:130656$5072_Y - connect \$110 $and$libresoc.v:130657$5073_Y - connect \$112 $and$libresoc.v:130658$5074_Y - connect \$114 $and$libresoc.v:130659$5075_Y - connect \$116 $and$libresoc.v:130660$5076_Y - connect \$118 $and$libresoc.v:130661$5077_Y - connect \$120 $and$libresoc.v:130662$5078_Y - connect \$122 $and$libresoc.v:130663$5079_Y - connect \$124 $and$libresoc.v:130664$5080_Y - connect \$126 $and$libresoc.v:130665$5081_Y - connect \$128 $and$libresoc.v:130666$5082_Y - connect \$12 $not$libresoc.v:130667$5083_Y - connect \$14 $and$libresoc.v:130668$5084_Y - connect \$16 $not$libresoc.v:130669$5085_Y - connect \$18 $and$libresoc.v:130670$5086_Y - connect \$20 $and$libresoc.v:130671$5087_Y - connect \$24 $not$libresoc.v:130672$5088_Y - connect \$26 $and$libresoc.v:130673$5089_Y - connect \$23 $reduce_or$libresoc.v:130674$5090_Y - connect \$22 $not$libresoc.v:130675$5091_Y - connect \$2 $and$libresoc.v:130676$5092_Y - connect \$30 $and$libresoc.v:130677$5093_Y - connect \$32 $reduce_or$libresoc.v:130678$5094_Y - connect \$34 $reduce_or$libresoc.v:130679$5095_Y - connect \$36 $or$libresoc.v:130680$5096_Y - connect \$38 $not$libresoc.v:130681$5097_Y - connect \$40 $and$libresoc.v:130682$5098_Y - connect \$42 $and$libresoc.v:130683$5099_Y - connect \$44 $eq$libresoc.v:130684$5100_Y - connect \$46 $and$libresoc.v:130685$5101_Y - connect \$48 $eq$libresoc.v:130686$5102_Y - connect \$50 $and$libresoc.v:130687$5103_Y - connect \$52 $and$libresoc.v:130688$5104_Y - connect \$54 $and$libresoc.v:130689$5105_Y - connect \$56 $or$libresoc.v:130690$5106_Y - connect \$58 $or$libresoc.v:130691$5107_Y - connect \$5 $not$libresoc.v:130692$5108_Y - connect \$60 $or$libresoc.v:130693$5109_Y - connect \$62 $or$libresoc.v:130694$5110_Y - connect \$64 $and$libresoc.v:130695$5111_Y - connect \$66 $and$libresoc.v:130696$5112_Y - connect \$68 $or$libresoc.v:130697$5113_Y - connect \$70 $and$libresoc.v:130698$5114_Y - connect \$72 $and$libresoc.v:130699$5115_Y - connect \$74 $and$libresoc.v:130700$5116_Y - connect \$76 $and$libresoc.v:130701$5117_Y - connect \$78 $ternary$libresoc.v:130702$5118_Y - connect \$7 $or$libresoc.v:130703$5119_Y - connect \$80 $ternary$libresoc.v:130704$5120_Y - connect \$83 $ternary$libresoc.v:130705$5121_Y - connect \$86 $ternary$libresoc.v:130706$5122_Y - connect \$88 $ternary$libresoc.v:130707$5123_Y - connect \$4 $reduce_and$libresoc.v:130708$5124_Y - connect \$90 $ternary$libresoc.v:130709$5125_Y - connect \$92 $ternary$libresoc.v:130710$5126_Y - connect \$94 $and$libresoc.v:130711$5127_Y - connect \$96 $and$libresoc.v:130712$5128_Y - connect \$98 $and$libresoc.v:130713$5129_Y + assign $1\prev_wr_go$next[3:0]$5342 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5342 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5341 + end + connect \$100 $not$libresoc.v:132258$5108_Y + connect \$102 $not$libresoc.v:132259$5109_Y + connect \$104 $and$libresoc.v:132260$5110_Y + connect \$106 $not$libresoc.v:132261$5111_Y + connect \$108 $and$libresoc.v:132262$5112_Y + connect \$10 $and$libresoc.v:132263$5113_Y + connect \$110 $and$libresoc.v:132264$5114_Y + connect \$112 $and$libresoc.v:132265$5115_Y + connect \$114 $and$libresoc.v:132266$5116_Y + connect \$116 $and$libresoc.v:132267$5117_Y + connect \$118 $and$libresoc.v:132268$5118_Y + connect \$120 $and$libresoc.v:132269$5119_Y + connect \$122 $and$libresoc.v:132270$5120_Y + connect \$124 $and$libresoc.v:132271$5121_Y + connect \$126 $and$libresoc.v:132272$5122_Y + connect \$128 $and$libresoc.v:132273$5123_Y + connect \$12 $not$libresoc.v:132274$5124_Y + connect \$14 $and$libresoc.v:132275$5125_Y + connect \$16 $not$libresoc.v:132276$5126_Y + connect \$18 $and$libresoc.v:132277$5127_Y + connect \$20 $and$libresoc.v:132278$5128_Y + connect \$24 $not$libresoc.v:132279$5129_Y + connect \$26 $and$libresoc.v:132280$5130_Y + connect \$23 $reduce_or$libresoc.v:132281$5131_Y + connect \$22 $not$libresoc.v:132282$5132_Y + connect \$2 $and$libresoc.v:132283$5133_Y + connect \$30 $and$libresoc.v:132284$5134_Y + connect \$32 $reduce_or$libresoc.v:132285$5135_Y + connect \$34 $reduce_or$libresoc.v:132286$5136_Y + connect \$36 $or$libresoc.v:132287$5137_Y + connect \$38 $not$libresoc.v:132288$5138_Y + connect \$40 $and$libresoc.v:132289$5139_Y + connect \$42 $and$libresoc.v:132290$5140_Y + connect \$44 $eq$libresoc.v:132291$5141_Y + connect \$46 $and$libresoc.v:132292$5142_Y + connect \$48 $eq$libresoc.v:132293$5143_Y + connect \$50 $and$libresoc.v:132294$5144_Y + connect \$52 $and$libresoc.v:132295$5145_Y + connect \$54 $and$libresoc.v:132296$5146_Y + connect \$56 $or$libresoc.v:132297$5147_Y + connect \$58 $or$libresoc.v:132298$5148_Y + connect \$5 $not$libresoc.v:132299$5149_Y + connect \$60 $or$libresoc.v:132300$5150_Y + connect \$62 $or$libresoc.v:132301$5151_Y + connect \$64 $and$libresoc.v:132302$5152_Y + connect \$66 $and$libresoc.v:132303$5153_Y + connect \$68 $or$libresoc.v:132304$5154_Y + connect \$70 $and$libresoc.v:132305$5155_Y + connect \$72 $and$libresoc.v:132306$5156_Y + connect \$74 $and$libresoc.v:132307$5157_Y + connect \$76 $and$libresoc.v:132308$5158_Y + connect \$78 $ternary$libresoc.v:132309$5159_Y + connect \$7 $or$libresoc.v:132310$5160_Y + connect \$80 $ternary$libresoc.v:132311$5161_Y + connect \$83 $ternary$libresoc.v:132312$5162_Y + connect \$86 $ternary$libresoc.v:132313$5163_Y + connect \$88 $ternary$libresoc.v:132314$5164_Y + connect \$4 $reduce_and$libresoc.v:132315$5165_Y + connect \$90 $ternary$libresoc.v:132316$5166_Y + connect \$92 $ternary$libresoc.v:132317$5167_Y + connect \$94 $and$libresoc.v:132318$5168_Y + connect \$96 $and$libresoc.v:132319$5169_Y + connect \$98 $and$libresoc.v:132320$5170_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -208066,7 +210486,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:131247.1-131256.10" +attribute \src "libresoc.v:132854.1-132863.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -208080,37 +210500,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:131260.1-131342.10" +attribute \src "libresoc.v:132867.1-132949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:131261.7-131261.20" + attribute \src "libresoc.v:132868.7-132868.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131326.3-131337.6" + attribute \src "libresoc.v:132933.3-132944.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131314.3-131325.6" + attribute \src "libresoc.v:132921.3-132932.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:131302.3-131313.6" + attribute \src "libresoc.v:132909.3-132920.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:131326.3-131337.6" + attribute \src "libresoc.v:132933.3-132944.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131314.3-131325.6" + attribute \src "libresoc.v:132921.3-132932.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:131302.3-131313.6" + attribute \src "libresoc.v:132909.3-132920.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:131296.18-131296.106" - wire width 8 $add$libresoc.v:131296$5347_Y - attribute \src "libresoc.v:131297.18-131297.109" - wire $ge$libresoc.v:131297$5348_Y - attribute \src "libresoc.v:131301.17-131301.108" - wire $ge$libresoc.v:131301$5352_Y - attribute \src "libresoc.v:131300.17-131300.101" - wire $not$libresoc.v:131300$5351_Y - attribute \src "libresoc.v:131298.17-131298.101" - wire width 127 $sshl$libresoc.v:131298$5349_Y - attribute \src "libresoc.v:131299.17-131299.109" - wire width 129 $sub$libresoc.v:131299$5350_Y + attribute \src "libresoc.v:132903.18-132903.106" + wire width 8 $add$libresoc.v:132903$5388_Y + attribute \src "libresoc.v:132904.18-132904.109" + wire $ge$libresoc.v:132904$5389_Y + attribute \src "libresoc.v:132908.17-132908.108" + wire $ge$libresoc.v:132908$5393_Y + attribute \src "libresoc.v:132907.17-132907.101" + wire $not$libresoc.v:132907$5392_Y + attribute \src "libresoc.v:132905.17-132905.101" + wire width 127 $sshl$libresoc.v:132905$5390_Y + attribute \src "libresoc.v:132906.17-132906.109" + wire width 129 $sub$libresoc.v:132906$5391_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -208135,7 +210555,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:131261.7-131261.15" + attribute \src "libresoc.v:132868.7-132868.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -208146,7 +210566,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:131296$5347 + cell $add $add$libresoc.v:132903$5388 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208154,10 +210574,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:131296$5347_Y + connect \Y $add$libresoc.v:132903$5388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:131297$5348 + cell $ge $ge$libresoc.v:132904$5389 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208165,10 +210585,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:131297$5348_Y + connect \Y $ge$libresoc.v:132904$5389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:131301$5352 + cell $ge $ge$libresoc.v:132908$5393 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -208176,18 +210596,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:131301$5352_Y + connect \Y $ge$libresoc.v:132908$5393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:131300$5351 + cell $not $not$libresoc.v:132907$5392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:131300$5351_Y + connect \Y $not$libresoc.v:132907$5392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:131298$5349 + cell $sshl $sshl$libresoc.v:132905$5390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -208195,10 +210615,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:131298$5349_Y + connect \Y $sshl$libresoc.v:132905$5390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:131299$5350 + cell $sub $sub$libresoc.v:132906$5391 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -208206,23 +210626,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:131299$5350_Y + connect \Y $sub$libresoc.v:132906$5391_Y end - attribute \src "libresoc.v:131261.7-131261.20" - process $proc$libresoc.v:131261$5356 + attribute \src "libresoc.v:132868.7-132868.20" + process $proc$libresoc.v:132868$5397 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131302.3-131313.6" - process $proc$libresoc.v:131302$5353 + attribute \src "libresoc.v:132909.3-132920.6" + process $proc$libresoc.v:132909$5394 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:131303.5-131303.29" + attribute \src "libresoc.v:132910.5-132910.29" switch \initial - attribute \src "libresoc.v:131303.9-131303.17" + attribute \src "libresoc.v:132910.9-132910.17" case 1'1 case end @@ -208240,13 +210660,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:131314.3-131325.6" - process $proc$libresoc.v:131314$5354 + attribute \src "libresoc.v:132921.3-132932.6" + process $proc$libresoc.v:132921$5395 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:131315.5-131315.29" + attribute \src "libresoc.v:132922.5-132922.29" switch \initial - attribute \src "libresoc.v:131315.9-131315.17" + attribute \src "libresoc.v:132922.9-132922.17" case 1'1 case end @@ -208264,13 +210684,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:131326.3-131337.6" - process $proc$libresoc.v:131326$5355 + attribute \src "libresoc.v:132933.3-132944.6" + process $proc$libresoc.v:132933$5396 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:131327.5-131327.29" + attribute \src "libresoc.v:132934.5-132934.29" switch \initial - attribute \src "libresoc.v:131327.9-131327.17" + attribute \src "libresoc.v:132934.9-132934.17" case 1'1 case end @@ -208288,18 +210708,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:131296$5347_Y - connect \$13 $ge$libresoc.v:131297$5348_Y - connect \$2 $sshl$libresoc.v:131298$5349_Y - connect \$4 $sub$libresoc.v:131299$5350_Y - connect \$6 $not$libresoc.v:131300$5351_Y - connect \$8 $ge$libresoc.v:131301$5352_Y + connect \$11 $add$libresoc.v:132903$5388_Y + connect \$13 $ge$libresoc.v:132904$5389_Y + connect \$2 $sshl$libresoc.v:132905$5390_Y + connect \$4 $sub$libresoc.v:132906$5391_Y + connect \$6 $not$libresoc.v:132907$5392_Y + connect \$8 $ge$libresoc.v:132908$5393_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:131346.1-131589.10" +attribute \src "libresoc.v:132953.1-133196.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -208547,94 +210967,94 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:131593.1-131764.10" +attribute \src "libresoc.v:133200.1-133371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:131688.3-131694.6" - wire width 3 $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 3 $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 - attribute \src "libresoc.v:131688.3-131694.6" - wire width 64 $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" + wire width 3 $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 3 $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 + attribute \src "libresoc.v:133295.3-133301.6" + wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:131688.3-131694.6" + attribute \src "libresoc.v:133295.3-133301.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:131594.7-131594.20" + attribute \src "libresoc.v:133201.7-133201.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131745.3-131754.6" + attribute \src "libresoc.v:133352.3-133361.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:131717.3-131725.6" - wire $0\ren_delay$10$next[0:0]$5387 - attribute \src "libresoc.v:131670.3-131671.43" - wire $0\ren_delay$10[0:0]$5370 - attribute \src "libresoc.v:131645.7-131645.28" - wire $0\ren_delay$10[0:0]$5407 - attribute \src "libresoc.v:131736.3-131744.6" - wire $0\ren_delay$11$next[0:0]$5391 - attribute \src "libresoc.v:131668.3-131669.43" - wire $0\ren_delay$11[0:0]$5368 - attribute \src "libresoc.v:131649.7-131649.28" + attribute \src "libresoc.v:133324.3-133332.6" + wire $0\ren_delay$10$next[0:0]$5428 + attribute \src "libresoc.v:133277.3-133278.43" + wire $0\ren_delay$10[0:0]$5411 + attribute \src "libresoc.v:133252.7-133252.28" + wire $0\ren_delay$10[0:0]$5448 + attribute \src "libresoc.v:133343.3-133351.6" + wire $0\ren_delay$11$next[0:0]$5432 + attribute \src "libresoc.v:133275.3-133276.43" wire $0\ren_delay$11[0:0]$5409 - attribute \src "libresoc.v:131698.3-131706.6" - wire $0\ren_delay$next[0:0]$5383 - attribute \src "libresoc.v:131672.3-131673.35" + attribute \src "libresoc.v:133256.7-133256.28" + wire $0\ren_delay$11[0:0]$5450 + attribute \src "libresoc.v:133305.3-133313.6" + wire $0\ren_delay$next[0:0]$5424 + attribute \src "libresoc.v:133279.3-133280.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:131707.3-131716.6" + attribute \src "libresoc.v:133314.3-133323.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:131726.3-131735.6" + attribute \src "libresoc.v:133333.3-133342.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:131745.3-131754.6" + attribute \src "libresoc.v:133352.3-133361.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:131717.3-131725.6" - wire $1\ren_delay$10$next[0:0]$5388 - attribute \src "libresoc.v:131736.3-131744.6" - wire $1\ren_delay$11$next[0:0]$5392 - attribute \src "libresoc.v:131698.3-131706.6" - wire $1\ren_delay$next[0:0]$5384 - attribute \src "libresoc.v:131643.7-131643.23" + attribute \src "libresoc.v:133324.3-133332.6" + wire $1\ren_delay$10$next[0:0]$5429 + attribute \src "libresoc.v:133343.3-133351.6" + wire $1\ren_delay$11$next[0:0]$5433 + attribute \src "libresoc.v:133305.3-133313.6" + wire $1\ren_delay$next[0:0]$5425 + attribute \src "libresoc.v:133250.7-133250.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:131707.3-131716.6" + attribute \src "libresoc.v:133314.3-133323.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:131726.3-131735.6" + attribute \src "libresoc.v:133333.3-133342.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:131695.26-131695.32" - wire width 64 $memrd$\memory$libresoc.v:131695$5379_DATA - attribute \src "libresoc.v:131696.30-131696.36" - wire width 64 $memrd$\memory$libresoc.v:131696$5380_DATA - attribute \src "libresoc.v:131697.30-131697.36" - wire width 64 $memrd$\memory$libresoc.v:131697$5381_DATA + attribute \src "libresoc.v:133302.26-133302.32" + wire width 64 $memrd$\memory$libresoc.v:133302$5420_DATA + attribute \src "libresoc.v:133303.30-133303.36" + wire width 64 $memrd$\memory$libresoc.v:133303$5421_DATA + attribute \src "libresoc.v:133304.30-133304.36" + wire width 64 $memrd$\memory$libresoc.v:133304$5422_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:131692$5365_ADDR + wire width 3 $memwr$\memory$libresoc.v:133299$5406_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131692$5365_DATA + wire width 64 $memwr$\memory$libresoc.v:133299$5406_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131692$5365_EN + wire width 64 $memwr$\memory$libresoc.v:133299$5406_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:131693$5366_ADDR + wire width 3 $memwr$\memory$libresoc.v:133300$5407_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131693$5366_DATA + wire width 64 $memwr$\memory$libresoc.v:133300$5407_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:131693$5366_EN - attribute \src "libresoc.v:131685.13-131685.16" + wire width 64 $memwr$\memory$libresoc.v:133300$5407_EN + attribute \src "libresoc.v:133292.13-133292.16" wire width 3 \_0_ - attribute \src "libresoc.v:131686.13-131686.16" + attribute \src "libresoc.v:133293.13-133293.16" wire width 3 \_1_ - attribute \src "libresoc.v:131687.13-131687.16" + attribute \src "libresoc.v:133294.13-133294.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \dest1__addr @@ -208642,7 +211062,7 @@ module \fast wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "libresoc.v:131594.7-131594.15" + attribute \src "libresoc.v:133201.7-133201.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -208704,90 +211124,90 @@ module \fast wire width 64 output 11 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src2__ren - attribute \src "libresoc.v:131674.14-131674.20" + attribute \src "libresoc.v:133281.14-133281.20" memory width 64 size 8 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5394 + cell $meminit $meminit$\memory$libresoc.v:0$5435 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5394 + parameter \PRIORITY 5435 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5395 + cell $meminit $meminit$\memory$libresoc.v:0$5436 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5395 + parameter \PRIORITY 5436 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5396 + cell $meminit $meminit$\memory$libresoc.v:0$5437 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5396 + parameter \PRIORITY 5437 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5397 + cell $meminit $meminit$\memory$libresoc.v:0$5438 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5397 + parameter \PRIORITY 5438 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5398 + cell $meminit $meminit$\memory$libresoc.v:0$5439 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5398 + parameter \PRIORITY 5439 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5399 + cell $meminit $meminit$\memory$libresoc.v:0$5440 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5399 + parameter \PRIORITY 5440 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5400 + cell $meminit $meminit$\memory$libresoc.v:0$5441 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5400 + parameter \PRIORITY 5441 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5401 + cell $meminit $meminit$\memory$libresoc.v:0$5442 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5401 + parameter \PRIORITY 5442 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:131695.26-131695.32" - cell $memrd $memrd$\memory$libresoc.v:131695$5379 + attribute \src "libresoc.v:133302.26-133302.32" + cell $memrd $memrd$\memory$libresoc.v:133302$5420 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208796,11 +211216,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131695$5379_DATA + connect \DATA $memrd$\memory$libresoc.v:133302$5420_DATA connect \EN 1'x end - attribute \src "libresoc.v:131696.30-131696.36" - cell $memrd $memrd$\memory$libresoc.v:131696$5380 + attribute \src "libresoc.v:133303.30-133303.36" + cell $memrd $memrd$\memory$libresoc.v:133303$5421 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208809,11 +211229,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131696$5380_DATA + connect \DATA $memrd$\memory$libresoc.v:133303$5421_DATA connect \EN 1'x end - attribute \src "libresoc.v:131697.30-131697.36" - cell $memrd $memrd$\memory$libresoc.v:131697$5381 + attribute \src "libresoc.v:133304.30-133304.36" + cell $memrd $memrd$\memory$libresoc.v:133304$5422 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -208822,95 +211242,95 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:131697$5381_DATA + connect \DATA $memrd$\memory$libresoc.v:133304$5422_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5402 + cell $memwr $memwr$\memory$libresoc.v:0$5443 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5402 + parameter \PRIORITY 5443 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:131692$5365_ADDR + connect \ADDR $memwr$\memory$libresoc.v:133299$5406_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:131692$5365_DATA - connect \EN $memwr$\memory$libresoc.v:131692$5365_EN + connect \DATA $memwr$\memory$libresoc.v:133299$5406_DATA + connect \EN $memwr$\memory$libresoc.v:133299$5406_EN end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5403 + cell $memwr $memwr$\memory$libresoc.v:0$5444 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5403 + parameter \PRIORITY 5444 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:131693$5366_ADDR + connect \ADDR $memwr$\memory$libresoc.v:133300$5407_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:131693$5366_DATA - connect \EN $memwr$\memory$libresoc.v:131693$5366_EN + connect \DATA $memwr$\memory$libresoc.v:133300$5407_DATA + connect \EN $memwr$\memory$libresoc.v:133300$5407_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5410 + process $proc$libresoc.v:0$5451 sync always sync init end - attribute \src "libresoc.v:131594.7-131594.20" - process $proc$libresoc.v:131594$5404 + attribute \src "libresoc.v:133201.7-133201.20" + process $proc$libresoc.v:133201$5445 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131643.7-131643.23" - process $proc$libresoc.v:131643$5405 + attribute \src "libresoc.v:133250.7-133250.23" + process $proc$libresoc.v:133250$5446 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:131645.7-131645.28" - process $proc$libresoc.v:131645$5406 + attribute \src "libresoc.v:133252.7-133252.28" + process $proc$libresoc.v:133252$5447 assign { } { } - assign $0\ren_delay$10[0:0]$5407 1'0 + assign $0\ren_delay$10[0:0]$5448 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5407 + update \ren_delay$10 $0\ren_delay$10[0:0]$5448 end - attribute \src "libresoc.v:131649.7-131649.28" - process $proc$libresoc.v:131649$5408 + attribute \src "libresoc.v:133256.7-133256.28" + process $proc$libresoc.v:133256$5449 assign { } { } - assign $0\ren_delay$11[0:0]$5409 1'0 + assign $0\ren_delay$11[0:0]$5450 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5409 + update \ren_delay$11 $0\ren_delay$11[0:0]$5450 end - attribute \src "libresoc.v:131668.3-131669.43" - process $proc$libresoc.v:131668$5367 + attribute \src "libresoc.v:133275.3-133276.43" + process $proc$libresoc.v:133275$5408 assign { } { } - assign $0\ren_delay$11[0:0]$5368 \ren_delay$11$next + assign $0\ren_delay$11[0:0]$5409 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5368 + update \ren_delay$11 $0\ren_delay$11[0:0]$5409 end - attribute \src "libresoc.v:131670.3-131671.43" - process $proc$libresoc.v:131670$5369 + attribute \src "libresoc.v:133277.3-133278.43" + process $proc$libresoc.v:133277$5410 assign { } { } - assign $0\ren_delay$10[0:0]$5370 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5411 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5370 + update \ren_delay$10 $0\ren_delay$10[0:0]$5411 end - attribute \src "libresoc.v:131672.3-131673.35" - process $proc$libresoc.v:131672$5371 + attribute \src "libresoc.v:133279.3-133280.35" + process $proc$libresoc.v:133279$5412 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:131688.3-131694.6" - process $proc$libresoc.v:131688$5372 + attribute \src "libresoc.v:133295.3-133301.6" + process $proc$libresoc.v:133295$5413 assign { } { } assign { } { } assign { } { } @@ -208920,52 +211340,52 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 3'xxx - assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 3'xxx - assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 3'xxx + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 3'xxx + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[2:0] \src1__addr assign $0\_1_[2:0] \src2__addr assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:131692.5-131692.62" + attribute \src "libresoc.v:133299.5-133299.62" switch \issue__wen - attribute \src "libresoc.v:131692.9-131692.19" + attribute \src "libresoc.v:133299.9-133299.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 \issue__data_i - assign $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 \issue__data_i + assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "libresoc.v:131693.5-131693.58" + attribute \src "libresoc.v:133300.5-133300.58" switch \dest1__wen - attribute \src "libresoc.v:131693.9-131693.19" + attribute \src "libresoc.v:133300.9-133300.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 \dest1__addr - assign $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 \dest1__addr + assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:131692$5365_ADDR $0$memwr$\memory$libresoc.v:131692$5365_ADDR[2:0]$5373 - update $memwr$\memory$libresoc.v:131692$5365_DATA $0$memwr$\memory$libresoc.v:131692$5365_DATA[63:0]$5374 - update $memwr$\memory$libresoc.v:131692$5365_EN $0$memwr$\memory$libresoc.v:131692$5365_EN[63:0]$5375 - update $memwr$\memory$libresoc.v:131693$5366_ADDR $0$memwr$\memory$libresoc.v:131693$5366_ADDR[2:0]$5376 - update $memwr$\memory$libresoc.v:131693$5366_DATA $0$memwr$\memory$libresoc.v:131693$5366_DATA[63:0]$5377 - update $memwr$\memory$libresoc.v:131693$5366_EN $0$memwr$\memory$libresoc.v:131693$5366_EN[63:0]$5378 + update $memwr$\memory$libresoc.v:133299$5406_ADDR $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 + update $memwr$\memory$libresoc.v:133299$5406_DATA $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 + update $memwr$\memory$libresoc.v:133299$5406_EN $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 + update $memwr$\memory$libresoc.v:133300$5407_ADDR $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 + update $memwr$\memory$libresoc.v:133300$5407_DATA $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 + update $memwr$\memory$libresoc.v:133300$5407_EN $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 end - attribute \src "libresoc.v:131698.3-131706.6" - process $proc$libresoc.v:131698$5382 + attribute \src "libresoc.v:133305.3-133313.6" + process $proc$libresoc.v:133305$5423 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5383 $1\ren_delay$next[0:0]$5384 - attribute \src "libresoc.v:131699.5-131699.29" + assign $0\ren_delay$next[0:0]$5424 $1\ren_delay$next[0:0]$5425 + attribute \src "libresoc.v:133306.5-133306.29" switch \initial - attribute \src "libresoc.v:131699.9-131699.17" + attribute \src "libresoc.v:133306.9-133306.17" case 1'1 case end @@ -208974,21 +211394,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5384 1'0 + assign $1\ren_delay$next[0:0]$5425 1'0 case - assign $1\ren_delay$next[0:0]$5384 \src1__ren + assign $1\ren_delay$next[0:0]$5425 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5383 + update \ren_delay$next $0\ren_delay$next[0:0]$5424 end - attribute \src "libresoc.v:131707.3-131716.6" - process $proc$libresoc.v:131707$5385 + attribute \src "libresoc.v:133314.3-133323.6" + process $proc$libresoc.v:133314$5426 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:131708.5-131708.29" + attribute \src "libresoc.v:133315.5-133315.29" switch \initial - attribute \src "libresoc.v:131708.9-131708.17" + attribute \src "libresoc.v:133315.9-133315.17" case 1'1 case end @@ -209004,14 +211424,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:131717.3-131725.6" - process $proc$libresoc.v:131717$5386 + attribute \src "libresoc.v:133324.3-133332.6" + process $proc$libresoc.v:133324$5427 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5387 $1\ren_delay$10$next[0:0]$5388 - attribute \src "libresoc.v:131718.5-131718.29" + assign $0\ren_delay$10$next[0:0]$5428 $1\ren_delay$10$next[0:0]$5429 + attribute \src "libresoc.v:133325.5-133325.29" switch \initial - attribute \src "libresoc.v:131718.9-131718.17" + attribute \src "libresoc.v:133325.9-133325.17" case 1'1 case end @@ -209020,21 +211440,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5388 1'0 + assign $1\ren_delay$10$next[0:0]$5429 1'0 case - assign $1\ren_delay$10$next[0:0]$5388 \src2__ren + assign $1\ren_delay$10$next[0:0]$5429 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5387 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5428 end - attribute \src "libresoc.v:131726.3-131735.6" - process $proc$libresoc.v:131726$5389 + attribute \src "libresoc.v:133333.3-133342.6" + process $proc$libresoc.v:133333$5430 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:131727.5-131727.29" + attribute \src "libresoc.v:133334.5-133334.29" switch \initial - attribute \src "libresoc.v:131727.9-131727.17" + attribute \src "libresoc.v:133334.9-133334.17" case 1'1 case end @@ -209050,14 +211470,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:131736.3-131744.6" - process $proc$libresoc.v:131736$5390 + attribute \src "libresoc.v:133343.3-133351.6" + process $proc$libresoc.v:133343$5431 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5391 $1\ren_delay$11$next[0:0]$5392 - attribute \src "libresoc.v:131737.5-131737.29" + assign $0\ren_delay$11$next[0:0]$5432 $1\ren_delay$11$next[0:0]$5433 + attribute \src "libresoc.v:133344.5-133344.29" switch \initial - attribute \src "libresoc.v:131737.9-131737.17" + attribute \src "libresoc.v:133344.9-133344.17" case 1'1 case end @@ -209066,21 +211486,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5392 1'0 + assign $1\ren_delay$11$next[0:0]$5433 1'0 case - assign $1\ren_delay$11$next[0:0]$5392 \issue__ren + assign $1\ren_delay$11$next[0:0]$5433 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5391 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5432 end - attribute \src "libresoc.v:131745.3-131754.6" - process $proc$libresoc.v:131745$5393 + attribute \src "libresoc.v:133352.3-133361.6" + process $proc$libresoc.v:133352$5434 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:131746.5-131746.29" + attribute \src "libresoc.v:133353.5-133353.29" switch \initial - attribute \src "libresoc.v:131746.9-131746.17" + attribute \src "libresoc.v:133353.9-133353.17" case 1'1 case end @@ -209096,9 +211516,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:131695$5379_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:131696$5380_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:131697$5381_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:133302$5420_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:133303$5421_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:133304$5422_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -209109,14 +211529,14 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:131768.1-133718.10" +attribute \src "libresoc.v:133375.1-135325.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 257 \cr_a_ok @@ -210696,7 +213116,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:133350.8-133392.4" + attribute \src "libresoc.v:134957.8-134999.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210741,7 +213161,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:133393.11-133420.4" + attribute \src "libresoc.v:135000.11-135027.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210771,7 +213191,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133421.7-133446.4" + attribute \src "libresoc.v:135028.7-135053.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210799,7 +213219,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133447.8-133486.4" + attribute \src "libresoc.v:135054.8-135093.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210841,7 +213261,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133487.9-133541.4" + attribute \src "libresoc.v:135094.9-135148.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210898,7 +213318,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133542.12-133577.4" + attribute \src "libresoc.v:135149.12-135184.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210936,7 +213356,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133578.8-133611.4" + attribute \src "libresoc.v:135185.8-135218.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210972,7 +213392,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133612.13-133650.4" + attribute \src "libresoc.v:135219.13-135257.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211013,7 +213433,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133651.8-133683.4" + attribute \src "libresoc.v:135258.8-135290.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211048,7 +213468,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:133684.9-133717.4" + attribute \src "libresoc.v:135291.9-135324.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -211084,37 +213504,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:133722.1-133780.10" +attribute \src "libresoc.v:135329.1-135387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:133723.7-133723.20" + attribute \src "libresoc.v:135330.7-135330.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133768.3-133776.6" - wire $0\q_int$next[0:0]$5421 - attribute \src "libresoc.v:133766.3-133767.27" + attribute \src "libresoc.v:135375.3-135383.6" + wire $0\q_int$next[0:0]$5462 + attribute \src "libresoc.v:135373.3-135374.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:133768.3-133776.6" - wire $1\q_int$next[0:0]$5422 - attribute \src "libresoc.v:133747.7-133747.19" + attribute \src "libresoc.v:135375.3-135383.6" + wire $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135354.7-135354.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:133758.17-133758.96" - wire $and$libresoc.v:133758$5411_Y - attribute \src "libresoc.v:133763.17-133763.96" - wire $and$libresoc.v:133763$5416_Y - attribute \src "libresoc.v:133760.18-133760.95" - wire $not$libresoc.v:133760$5413_Y - attribute \src "libresoc.v:133762.17-133762.94" - wire $not$libresoc.v:133762$5415_Y - attribute \src "libresoc.v:133765.17-133765.94" - wire $not$libresoc.v:133765$5418_Y - attribute \src "libresoc.v:133759.18-133759.100" - wire $or$libresoc.v:133759$5412_Y - attribute \src "libresoc.v:133761.18-133761.101" - wire $or$libresoc.v:133761$5414_Y - attribute \src "libresoc.v:133764.17-133764.99" - wire $or$libresoc.v:133764$5417_Y + attribute \src "libresoc.v:135365.17-135365.96" + wire $and$libresoc.v:135365$5452_Y + attribute \src "libresoc.v:135370.17-135370.96" + wire $and$libresoc.v:135370$5457_Y + attribute \src "libresoc.v:135367.18-135367.95" + wire $not$libresoc.v:135367$5454_Y + attribute \src "libresoc.v:135369.17-135369.94" + wire $not$libresoc.v:135369$5456_Y + attribute \src "libresoc.v:135372.17-135372.94" + wire $not$libresoc.v:135372$5459_Y + attribute \src "libresoc.v:135366.18-135366.100" + wire $or$libresoc.v:135366$5453_Y + attribute \src "libresoc.v:135368.18-135368.101" + wire $or$libresoc.v:135368$5455_Y + attribute \src "libresoc.v:135371.17-135371.99" + wire $or$libresoc.v:135371$5458_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -211131,11 +213551,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:133723.7-133723.15" + attribute \src "libresoc.v:135330.7-135330.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -211152,7 +213572,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:133758$5411 + cell $and $and$libresoc.v:135365$5452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211160,10 +213580,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:133758$5411_Y + connect \Y $and$libresoc.v:135365$5452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:133763$5416 + cell $and $and$libresoc.v:135370$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211171,34 +213591,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:133763$5416_Y + connect \Y $and$libresoc.v:135370$5457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:133760$5413 + cell $not $not$libresoc.v:135367$5454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:133760$5413_Y + connect \Y $not$libresoc.v:135367$5454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:133762$5415 + cell $not $not$libresoc.v:135369$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:133762$5415_Y + connect \Y $not$libresoc.v:135369$5456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:133765$5418 + cell $not $not$libresoc.v:135372$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:133765$5418_Y + connect \Y $not$libresoc.v:135372$5459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:133759$5412 + cell $or $or$libresoc.v:135366$5453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211206,10 +213626,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:133759$5412_Y + connect \Y $or$libresoc.v:135366$5453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:133761$5414 + cell $or $or$libresoc.v:135368$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211217,10 +213637,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:133761$5414_Y + connect \Y $or$libresoc.v:135368$5455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:133764$5417 + cell $or $or$libresoc.v:135371$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211228,39 +213648,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:133764$5417_Y + connect \Y $or$libresoc.v:135371$5458_Y end - attribute \src "libresoc.v:133723.7-133723.20" - process $proc$libresoc.v:133723$5423 + attribute \src "libresoc.v:135330.7-135330.20" + process $proc$libresoc.v:135330$5464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133747.7-133747.19" - process $proc$libresoc.v:133747$5424 + attribute \src "libresoc.v:135354.7-135354.19" + process $proc$libresoc.v:135354$5465 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:133766.3-133767.27" - process $proc$libresoc.v:133766$5419 + attribute \src "libresoc.v:135373.3-135374.27" + process $proc$libresoc.v:135373$5460 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:133768.3-133776.6" - process $proc$libresoc.v:133768$5420 + attribute \src "libresoc.v:135375.3-135383.6" + process $proc$libresoc.v:135375$5461 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5421 $1\q_int$next[0:0]$5422 - attribute \src "libresoc.v:133769.5-133769.29" + assign $0\q_int$next[0:0]$5462 $1\q_int$next[0:0]$5463 + attribute \src "libresoc.v:135376.5-135376.29" switch \initial - attribute \src "libresoc.v:133769.9-133769.17" + attribute \src "libresoc.v:135376.9-135376.17" case 1'1 case end @@ -211269,192 +213689,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5422 1'0 + assign $1\q_int$next[0:0]$5463 1'0 case - assign $1\q_int$next[0:0]$5422 \$5 + assign $1\q_int$next[0:0]$5463 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5421 + update \q_int$next $0\q_int$next[0:0]$5462 end - connect \$9 $and$libresoc.v:133758$5411_Y - connect \$11 $or$libresoc.v:133759$5412_Y - connect \$13 $not$libresoc.v:133760$5413_Y - connect \$15 $or$libresoc.v:133761$5414_Y - connect \$1 $not$libresoc.v:133762$5415_Y - connect \$3 $and$libresoc.v:133763$5416_Y - connect \$5 $or$libresoc.v:133764$5417_Y - connect \$7 $not$libresoc.v:133765$5418_Y + connect \$9 $and$libresoc.v:135365$5452_Y + connect \$11 $or$libresoc.v:135366$5453_Y + connect \$13 $not$libresoc.v:135367$5454_Y + connect \$15 $or$libresoc.v:135368$5455_Y + connect \$1 $not$libresoc.v:135369$5456_Y + connect \$3 $and$libresoc.v:135370$5457_Y + connect \$5 $or$libresoc.v:135371$5458_Y + connect \$7 $not$libresoc.v:135372$5459_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:133784.1-134163.10" +attribute \src "libresoc.v:135391.1-135770.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:134115.3-134124.6" + attribute \src "libresoc.v:135722.3-135731.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5493 - attribute \src "libresoc.v:133926.3-133927.39" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5534 + attribute \src "libresoc.v:135533.3-135534.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135732.3-135749.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $0\f_fetch_err_o$next[0:0]$5488 - attribute \src "libresoc.v:133928.3-133929.43" + attribute \src "libresoc.v:135679.3-135701.6" + wire $0\f_fetch_err_o$next[0:0]$5529 + attribute \src "libresoc.v:135535.3-135536.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $0\ibus__adr$next[44:0]$5483 - attribute \src "libresoc.v:133930.3-133931.35" + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $0\ibus__adr$next[44:0]$5524 + attribute \src "libresoc.v:135537.3-135538.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:133940.3-133967.6" - wire $0\ibus__cyc$next[0:0]$5459 - attribute \src "libresoc.v:133938.3-133939.35" + attribute \src "libresoc.v:135547.3-135574.6" + wire $0\ibus__cyc$next[0:0]$5500 + attribute \src "libresoc.v:135545.3-135546.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $0\ibus__sel$next[7:0]$5471 - attribute \src "libresoc.v:133934.3-133935.35" + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $0\ibus__sel$next[7:0]$5512 + attribute \src "libresoc.v:135541.3-135542.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:133968.3-133995.6" - wire $0\ibus__stb$next[0:0]$5465 - attribute \src "libresoc.v:133936.3-133937.35" + attribute \src "libresoc.v:135575.3-135602.6" + wire $0\ibus__stb$next[0:0]$5506 + attribute \src "libresoc.v:135543.3-135544.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $0\ibus_rdata$next[63:0]$5477 - attribute \src "libresoc.v:133932.3-133933.37" + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $0\ibus_rdata$next[63:0]$5518 + attribute \src "libresoc.v:135539.3-135540.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:133785.7-133785.20" + attribute \src "libresoc.v:135392.7-135392.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134115.3-134124.6" + attribute \src "libresoc.v:135722.3-135731.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5494 - attribute \src "libresoc.v:133849.14-133849.44" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5535 + attribute \src "libresoc.v:135456.14-135456.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135732.3-135749.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $1\f_fetch_err_o$next[0:0]$5489 - attribute \src "libresoc.v:133856.7-133856.27" + attribute \src "libresoc.v:135679.3-135701.6" + wire $1\f_fetch_err_o$next[0:0]$5530 + attribute \src "libresoc.v:135463.7-135463.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $1\ibus__adr$next[44:0]$5484 - attribute \src "libresoc.v:133870.14-133870.42" + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $1\ibus__adr$next[44:0]$5525 + attribute \src "libresoc.v:135477.14-135477.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:133940.3-133967.6" - wire $1\ibus__cyc$next[0:0]$5460 - attribute \src "libresoc.v:133875.7-133875.23" + attribute \src "libresoc.v:135547.3-135574.6" + wire $1\ibus__cyc$next[0:0]$5501 + attribute \src "libresoc.v:135482.7-135482.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $1\ibus__sel$next[7:0]$5472 - attribute \src "libresoc.v:133884.13-133884.30" + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $1\ibus__sel$next[7:0]$5513 + attribute \src "libresoc.v:135491.13-135491.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:133968.3-133995.6" - wire $1\ibus__stb$next[0:0]$5466 - attribute \src "libresoc.v:133889.7-133889.23" + attribute \src "libresoc.v:135575.3-135602.6" + wire $1\ibus__stb$next[0:0]$5507 + attribute \src "libresoc.v:135496.7-135496.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $1\ibus_rdata$next[63:0]$5478 - attribute \src "libresoc.v:133893.14-133893.47" + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $1\ibus_rdata$next[63:0]$5519 + attribute \src "libresoc.v:135500.14-135500.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5495 - attribute \src "libresoc.v:134125.3-134142.6" + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5536 + attribute \src "libresoc.v:135732.3-135749.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:134072.3-134094.6" - wire $2\f_fetch_err_o$next[0:0]$5490 - attribute \src "libresoc.v:134143.3-134160.6" + attribute \src "libresoc.v:135679.3-135701.6" + wire $2\f_fetch_err_o$next[0:0]$5531 + attribute \src "libresoc.v:135750.3-135767.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $2\ibus__adr$next[44:0]$5485 - attribute \src "libresoc.v:133940.3-133967.6" - wire $2\ibus__cyc$next[0:0]$5461 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $2\ibus__sel$next[7:0]$5473 - attribute \src "libresoc.v:133968.3-133995.6" - wire $2\ibus__stb$next[0:0]$5467 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $2\ibus_rdata$next[63:0]$5479 - attribute \src "libresoc.v:134095.3-134114.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5496 - attribute \src "libresoc.v:134072.3-134094.6" - wire $3\f_fetch_err_o$next[0:0]$5491 - attribute \src "libresoc.v:134049.3-134071.6" - wire width 45 $3\ibus__adr$next[44:0]$5486 - attribute \src "libresoc.v:133940.3-133967.6" - wire $3\ibus__cyc$next[0:0]$5462 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $3\ibus__sel$next[7:0]$5474 - attribute \src "libresoc.v:133968.3-133995.6" - wire $3\ibus__stb$next[0:0]$5468 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $3\ibus_rdata$next[63:0]$5480 - attribute \src "libresoc.v:133940.3-133967.6" - wire $4\ibus__cyc$next[0:0]$5463 - attribute \src "libresoc.v:133996.3-134023.6" - wire width 8 $4\ibus__sel$next[7:0]$5475 - attribute \src "libresoc.v:133968.3-133995.6" - wire $4\ibus__stb$next[0:0]$5469 - attribute \src "libresoc.v:134024.3-134048.6" - wire width 64 $4\ibus_rdata$next[63:0]$5481 - attribute \src "libresoc.v:133902.18-133902.110" - wire $and$libresoc.v:133902$5427_Y - attribute \src "libresoc.v:133908.18-133908.110" - wire $and$libresoc.v:133908$5433_Y - attribute \src "libresoc.v:133913.18-133913.110" - wire $and$libresoc.v:133913$5438_Y - attribute \src "libresoc.v:133916.17-133916.108" - wire $and$libresoc.v:133916$5441_Y - attribute \src "libresoc.v:133919.18-133919.110" - wire $and$libresoc.v:133919$5444_Y - attribute \src "libresoc.v:133920.18-133920.115" - wire $and$libresoc.v:133920$5445_Y - attribute \src "libresoc.v:133922.18-133922.115" - wire $and$libresoc.v:133922$5447_Y - attribute \src "libresoc.v:133901.18-133901.105" - wire $not$libresoc.v:133901$5426_Y - attribute \src "libresoc.v:133904.18-133904.105" - wire $not$libresoc.v:133904$5429_Y - attribute \src "libresoc.v:133905.17-133905.104" - wire $not$libresoc.v:133905$5430_Y - attribute \src "libresoc.v:133907.18-133907.105" - wire $not$libresoc.v:133907$5432_Y - attribute \src "libresoc.v:133910.18-133910.105" - wire $not$libresoc.v:133910$5435_Y - attribute \src "libresoc.v:133912.18-133912.105" - wire $not$libresoc.v:133912$5437_Y - attribute \src "libresoc.v:133915.18-133915.105" - wire $not$libresoc.v:133915$5440_Y - attribute \src "libresoc.v:133918.18-133918.105" - wire $not$libresoc.v:133918$5443_Y - attribute \src "libresoc.v:133921.18-133921.105" - wire $not$libresoc.v:133921$5446_Y - attribute \src "libresoc.v:133923.18-133923.105" - wire $not$libresoc.v:133923$5448_Y - attribute \src "libresoc.v:133925.17-133925.104" - wire $not$libresoc.v:133925$5450_Y - attribute \src "libresoc.v:133900.17-133900.103" - wire $or$libresoc.v:133900$5425_Y - attribute \src "libresoc.v:133903.18-133903.115" - wire $or$libresoc.v:133903$5428_Y - attribute \src "libresoc.v:133906.18-133906.106" - wire $or$libresoc.v:133906$5431_Y - attribute \src "libresoc.v:133909.18-133909.115" - wire $or$libresoc.v:133909$5434_Y - attribute \src "libresoc.v:133911.18-133911.106" - wire $or$libresoc.v:133911$5436_Y - attribute \src "libresoc.v:133914.18-133914.115" - wire $or$libresoc.v:133914$5439_Y - attribute \src "libresoc.v:133917.18-133917.106" - wire $or$libresoc.v:133917$5442_Y - attribute \src "libresoc.v:133924.17-133924.114" - wire $or$libresoc.v:133924$5449_Y + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $2\ibus__adr$next[44:0]$5526 + attribute \src "libresoc.v:135547.3-135574.6" + wire $2\ibus__cyc$next[0:0]$5502 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $2\ibus__sel$next[7:0]$5514 + attribute \src "libresoc.v:135575.3-135602.6" + wire $2\ibus__stb$next[0:0]$5508 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $2\ibus_rdata$next[63:0]$5520 + attribute \src "libresoc.v:135702.3-135721.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5537 + attribute \src "libresoc.v:135679.3-135701.6" + wire $3\f_fetch_err_o$next[0:0]$5532 + attribute \src "libresoc.v:135656.3-135678.6" + wire width 45 $3\ibus__adr$next[44:0]$5527 + attribute \src "libresoc.v:135547.3-135574.6" + wire $3\ibus__cyc$next[0:0]$5503 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $3\ibus__sel$next[7:0]$5515 + attribute \src "libresoc.v:135575.3-135602.6" + wire $3\ibus__stb$next[0:0]$5509 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $3\ibus_rdata$next[63:0]$5521 + attribute \src "libresoc.v:135547.3-135574.6" + wire $4\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:135603.3-135630.6" + wire width 8 $4\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:135575.3-135602.6" + wire $4\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:135631.3-135655.6" + wire width 64 $4\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:135509.18-135509.110" + wire $and$libresoc.v:135509$5468_Y + attribute \src "libresoc.v:135515.18-135515.110" + wire $and$libresoc.v:135515$5474_Y + attribute \src "libresoc.v:135520.18-135520.110" + wire $and$libresoc.v:135520$5479_Y + attribute \src "libresoc.v:135523.17-135523.108" + wire $and$libresoc.v:135523$5482_Y + attribute \src "libresoc.v:135526.18-135526.110" + wire $and$libresoc.v:135526$5485_Y + attribute \src "libresoc.v:135527.18-135527.115" + wire $and$libresoc.v:135527$5486_Y + attribute \src "libresoc.v:135529.18-135529.115" + wire $and$libresoc.v:135529$5488_Y + attribute \src "libresoc.v:135508.18-135508.105" + wire $not$libresoc.v:135508$5467_Y + attribute \src "libresoc.v:135511.18-135511.105" + wire $not$libresoc.v:135511$5470_Y + attribute \src "libresoc.v:135512.17-135512.104" + wire $not$libresoc.v:135512$5471_Y + attribute \src "libresoc.v:135514.18-135514.105" + wire $not$libresoc.v:135514$5473_Y + attribute \src "libresoc.v:135517.18-135517.105" + wire $not$libresoc.v:135517$5476_Y + attribute \src "libresoc.v:135519.18-135519.105" + wire $not$libresoc.v:135519$5478_Y + attribute \src "libresoc.v:135522.18-135522.105" + wire $not$libresoc.v:135522$5481_Y + attribute \src "libresoc.v:135525.18-135525.105" + wire $not$libresoc.v:135525$5484_Y + attribute \src "libresoc.v:135528.18-135528.105" + wire $not$libresoc.v:135528$5487_Y + attribute \src "libresoc.v:135530.18-135530.105" + wire $not$libresoc.v:135530$5489_Y + attribute \src "libresoc.v:135532.17-135532.104" + wire $not$libresoc.v:135532$5491_Y + attribute \src "libresoc.v:135507.17-135507.103" + wire $or$libresoc.v:135507$5466_Y + attribute \src "libresoc.v:135510.18-135510.115" + wire $or$libresoc.v:135510$5469_Y + attribute \src "libresoc.v:135513.18-135513.106" + wire $or$libresoc.v:135513$5472_Y + attribute \src "libresoc.v:135516.18-135516.115" + wire $or$libresoc.v:135516$5475_Y + attribute \src "libresoc.v:135518.18-135518.106" + wire $or$libresoc.v:135518$5477_Y + attribute \src "libresoc.v:135521.18-135521.115" + wire $or$libresoc.v:135521$5480_Y + attribute \src "libresoc.v:135524.18-135524.106" + wire $or$libresoc.v:135524$5483_Y + attribute \src "libresoc.v:135531.17-135531.114" + wire $or$libresoc.v:135531$5490_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -211515,7 +213935,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -211559,14 +213979,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:133785.7-133785.15" + attribute \src "libresoc.v:135392.7-135392.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133902$5427 + cell $and $and$libresoc.v:135509$5468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211574,10 +213994,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:133902$5427_Y + connect \Y $and$libresoc.v:135509$5468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133908$5433 + cell $and $and$libresoc.v:135515$5474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211585,10 +214005,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:133908$5433_Y + connect \Y $and$libresoc.v:135515$5474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133913$5438 + cell $and $and$libresoc.v:135520$5479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211596,10 +214016,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:133913$5438_Y + connect \Y $and$libresoc.v:135520$5479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133916$5441 + cell $and $and$libresoc.v:135523$5482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211607,10 +214027,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:133916$5441_Y + connect \Y $and$libresoc.v:135523$5482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:133919$5444 + cell $and $and$libresoc.v:135526$5485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211618,10 +214038,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:133919$5444_Y + connect \Y $and$libresoc.v:135526$5485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:133920$5445 + cell $and $and$libresoc.v:135527$5486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211629,10 +214049,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:133920$5445_Y + connect \Y $and$libresoc.v:135527$5486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:133922$5447 + cell $and $and$libresoc.v:135529$5488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211640,98 +214060,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:133922$5447_Y + connect \Y $and$libresoc.v:135529$5488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133901$5426 + cell $not $not$libresoc.v:135508$5467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133901$5426_Y + connect \Y $not$libresoc.v:135508$5467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133904$5429 + cell $not $not$libresoc.v:135511$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133904$5429_Y + connect \Y $not$libresoc.v:135511$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133905$5430 + cell $not $not$libresoc.v:135512$5471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133905$5430_Y + connect \Y $not$libresoc.v:135512$5471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133907$5432 + cell $not $not$libresoc.v:135514$5473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133907$5432_Y + connect \Y $not$libresoc.v:135514$5473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133910$5435 + cell $not $not$libresoc.v:135517$5476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133910$5435_Y + connect \Y $not$libresoc.v:135517$5476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133912$5437 + cell $not $not$libresoc.v:135519$5478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133912$5437_Y + connect \Y $not$libresoc.v:135519$5478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133915$5440 + cell $not $not$libresoc.v:135522$5481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133915$5440_Y + connect \Y $not$libresoc.v:135522$5481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:133918$5443 + cell $not $not$libresoc.v:135525$5484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:133918$5443_Y + connect \Y $not$libresoc.v:135525$5484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:133921$5446 + cell $not $not$libresoc.v:135528$5487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:133921$5446_Y + connect \Y $not$libresoc.v:135528$5487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:133923$5448 + cell $not $not$libresoc.v:135530$5489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:133923$5448_Y + connect \Y $not$libresoc.v:135530$5489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:133925$5450 + cell $not $not$libresoc.v:135532$5491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:133925$5450_Y + connect \Y $not$libresoc.v:135532$5491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133900$5425 + cell $or $or$libresoc.v:135507$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211739,10 +214159,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:133900$5425_Y + connect \Y $or$libresoc.v:135507$5466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133903$5428 + cell $or $or$libresoc.v:135510$5469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211750,10 +214170,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133903$5428_Y + connect \Y $or$libresoc.v:135510$5469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133906$5431 + cell $or $or$libresoc.v:135513$5472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211761,10 +214181,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:133906$5431_Y + connect \Y $or$libresoc.v:135513$5472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133909$5434 + cell $or $or$libresoc.v:135516$5475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211772,10 +214192,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133909$5434_Y + connect \Y $or$libresoc.v:135516$5475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133911$5436 + cell $or $or$libresoc.v:135518$5477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211783,10 +214203,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:133911$5436_Y + connect \Y $or$libresoc.v:135518$5477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133914$5439 + cell $or $or$libresoc.v:135521$5480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211794,10 +214214,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133914$5439_Y + connect \Y $or$libresoc.v:135521$5480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133917$5442 + cell $or $or$libresoc.v:135524$5483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211805,10 +214225,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:133917$5442_Y + connect \Y $or$libresoc.v:135524$5483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:133924$5449 + cell $or $or$libresoc.v:135531$5490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -211816,130 +214236,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:133924$5449_Y + connect \Y $or$libresoc.v:135531$5490_Y end - attribute \src "libresoc.v:133785.7-133785.20" - process $proc$libresoc.v:133785$5500 + attribute \src "libresoc.v:135392.7-135392.20" + process $proc$libresoc.v:135392$5541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133849.14-133849.44" - process $proc$libresoc.v:133849$5501 + attribute \src "libresoc.v:135456.14-135456.44" + process $proc$libresoc.v:135456$5542 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:133856.7-133856.27" - process $proc$libresoc.v:133856$5502 + attribute \src "libresoc.v:135463.7-135463.27" + process $proc$libresoc.v:135463$5543 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:133870.14-133870.42" - process $proc$libresoc.v:133870$5503 + attribute \src "libresoc.v:135477.14-135477.42" + process $proc$libresoc.v:135477$5544 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:133875.7-133875.23" - process $proc$libresoc.v:133875$5504 + attribute \src "libresoc.v:135482.7-135482.23" + process $proc$libresoc.v:135482$5545 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:133884.13-133884.30" - process $proc$libresoc.v:133884$5505 + attribute \src "libresoc.v:135491.13-135491.30" + process $proc$libresoc.v:135491$5546 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:133889.7-133889.23" - process $proc$libresoc.v:133889$5506 + attribute \src "libresoc.v:135496.7-135496.23" + process $proc$libresoc.v:135496$5547 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:133893.14-133893.47" - process $proc$libresoc.v:133893$5507 + attribute \src "libresoc.v:135500.14-135500.47" + process $proc$libresoc.v:135500$5548 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:133926.3-133927.39" - process $proc$libresoc.v:133926$5451 + attribute \src "libresoc.v:135533.3-135534.39" + process $proc$libresoc.v:135533$5492 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:133928.3-133929.43" - process $proc$libresoc.v:133928$5452 + attribute \src "libresoc.v:135535.3-135536.43" + process $proc$libresoc.v:135535$5493 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:133930.3-133931.35" - process $proc$libresoc.v:133930$5453 + attribute \src "libresoc.v:135537.3-135538.35" + process $proc$libresoc.v:135537$5494 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:133932.3-133933.37" - process $proc$libresoc.v:133932$5454 + attribute \src "libresoc.v:135539.3-135540.37" + process $proc$libresoc.v:135539$5495 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:133934.3-133935.35" - process $proc$libresoc.v:133934$5455 + attribute \src "libresoc.v:135541.3-135542.35" + process $proc$libresoc.v:135541$5496 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:133936.3-133937.35" - process $proc$libresoc.v:133936$5456 + attribute \src "libresoc.v:135543.3-135544.35" + process $proc$libresoc.v:135543$5497 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:133938.3-133939.35" - process $proc$libresoc.v:133938$5457 + attribute \src "libresoc.v:135545.3-135546.35" + process $proc$libresoc.v:135545$5498 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:133940.3-133967.6" - process $proc$libresoc.v:133940$5458 + attribute \src "libresoc.v:135547.3-135574.6" + process $proc$libresoc.v:135547$5499 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5459 $4\ibus__cyc$next[0:0]$5463 - attribute \src "libresoc.v:133941.5-133941.29" + assign $0\ibus__cyc$next[0:0]$5500 $4\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:135548.5-135548.29" switch \initial - attribute \src "libresoc.v:133941.9-133941.17" + attribute \src "libresoc.v:135548.9-135548.17" case 1'1 case end @@ -211948,53 +214368,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5460 $2\ibus__cyc$next[0:0]$5461 + assign $1\ibus__cyc$next[0:0]$5501 $2\ibus__cyc$next[0:0]$5502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5461 $3\ibus__cyc$next[0:0]$5462 + assign $2\ibus__cyc$next[0:0]$5502 $3\ibus__cyc$next[0:0]$5503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5462 1'0 + assign $3\ibus__cyc$next[0:0]$5503 1'0 case - assign $3\ibus__cyc$next[0:0]$5462 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5503 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5461 1'1 + assign $2\ibus__cyc$next[0:0]$5502 1'1 case - assign $2\ibus__cyc$next[0:0]$5461 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5502 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5460 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5501 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5463 1'0 + assign $4\ibus__cyc$next[0:0]$5504 1'0 case - assign $4\ibus__cyc$next[0:0]$5463 $1\ibus__cyc$next[0:0]$5460 + assign $4\ibus__cyc$next[0:0]$5504 $1\ibus__cyc$next[0:0]$5501 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5459 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5500 end - attribute \src "libresoc.v:133968.3-133995.6" - process $proc$libresoc.v:133968$5464 + attribute \src "libresoc.v:135575.3-135602.6" + process $proc$libresoc.v:135575$5505 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5465 $4\ibus__stb$next[0:0]$5469 - attribute \src "libresoc.v:133969.5-133969.29" + assign $0\ibus__stb$next[0:0]$5506 $4\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:135576.5-135576.29" switch \initial - attribute \src "libresoc.v:133969.9-133969.17" + attribute \src "libresoc.v:135576.9-135576.17" case 1'1 case end @@ -212003,53 +214423,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5466 $2\ibus__stb$next[0:0]$5467 + assign $1\ibus__stb$next[0:0]$5507 $2\ibus__stb$next[0:0]$5508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5467 $3\ibus__stb$next[0:0]$5468 + assign $2\ibus__stb$next[0:0]$5508 $3\ibus__stb$next[0:0]$5509 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5468 1'0 + assign $3\ibus__stb$next[0:0]$5509 1'0 case - assign $3\ibus__stb$next[0:0]$5468 \ibus__stb + assign $3\ibus__stb$next[0:0]$5509 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5467 1'1 + assign $2\ibus__stb$next[0:0]$5508 1'1 case - assign $2\ibus__stb$next[0:0]$5467 \ibus__stb + assign $2\ibus__stb$next[0:0]$5508 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5466 \ibus__stb + assign $1\ibus__stb$next[0:0]$5507 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5469 1'0 + assign $4\ibus__stb$next[0:0]$5510 1'0 case - assign $4\ibus__stb$next[0:0]$5469 $1\ibus__stb$next[0:0]$5466 + assign $4\ibus__stb$next[0:0]$5510 $1\ibus__stb$next[0:0]$5507 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5465 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5506 end - attribute \src "libresoc.v:133996.3-134023.6" - process $proc$libresoc.v:133996$5470 + attribute \src "libresoc.v:135603.3-135630.6" + process $proc$libresoc.v:135603$5511 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5471 $4\ibus__sel$next[7:0]$5475 - attribute \src "libresoc.v:133997.5-133997.29" + assign $0\ibus__sel$next[7:0]$5512 $4\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:135604.5-135604.29" switch \initial - attribute \src "libresoc.v:133997.9-133997.17" + attribute \src "libresoc.v:135604.9-135604.17" case 1'1 case end @@ -212058,53 +214478,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5472 $2\ibus__sel$next[7:0]$5473 + assign $1\ibus__sel$next[7:0]$5513 $2\ibus__sel$next[7:0]$5514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5473 $3\ibus__sel$next[7:0]$5474 + assign $2\ibus__sel$next[7:0]$5514 $3\ibus__sel$next[7:0]$5515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5474 8'00000000 + assign $3\ibus__sel$next[7:0]$5515 8'00000000 case - assign $3\ibus__sel$next[7:0]$5474 \ibus__sel + assign $3\ibus__sel$next[7:0]$5515 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5473 8'11111111 + assign $2\ibus__sel$next[7:0]$5514 8'11111111 case - assign $2\ibus__sel$next[7:0]$5473 \ibus__sel + assign $2\ibus__sel$next[7:0]$5514 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5472 \ibus__sel + assign $1\ibus__sel$next[7:0]$5513 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5475 8'00000000 + assign $4\ibus__sel$next[7:0]$5516 8'00000000 case - assign $4\ibus__sel$next[7:0]$5475 $1\ibus__sel$next[7:0]$5472 + assign $4\ibus__sel$next[7:0]$5516 $1\ibus__sel$next[7:0]$5513 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5471 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5512 end - attribute \src "libresoc.v:134024.3-134048.6" - process $proc$libresoc.v:134024$5476 + attribute \src "libresoc.v:135631.3-135655.6" + process $proc$libresoc.v:135631$5517 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5477 $4\ibus_rdata$next[63:0]$5481 - attribute \src "libresoc.v:134025.5-134025.29" + assign $0\ibus_rdata$next[63:0]$5518 $4\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:135632.5-135632.29" switch \initial - attribute \src "libresoc.v:134025.9-134025.17" + attribute \src "libresoc.v:135632.9-135632.17" case 1'1 case end @@ -212113,49 +214533,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5478 $2\ibus_rdata$next[63:0]$5479 + assign $1\ibus_rdata$next[63:0]$5519 $2\ibus_rdata$next[63:0]$5520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5479 $3\ibus_rdata$next[63:0]$5480 + assign $2\ibus_rdata$next[63:0]$5520 $3\ibus_rdata$next[63:0]$5521 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5480 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5521 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5480 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5521 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5479 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5520 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5478 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5519 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5481 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5522 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5481 $1\ibus_rdata$next[63:0]$5478 + assign $4\ibus_rdata$next[63:0]$5522 $1\ibus_rdata$next[63:0]$5519 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5477 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5518 end - attribute \src "libresoc.v:134049.3-134071.6" - process $proc$libresoc.v:134049$5482 + attribute \src "libresoc.v:135656.3-135678.6" + process $proc$libresoc.v:135656$5523 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5483 $3\ibus__adr$next[44:0]$5486 - attribute \src "libresoc.v:134050.5-134050.29" + assign $0\ibus__adr$next[44:0]$5524 $3\ibus__adr$next[44:0]$5527 + attribute \src "libresoc.v:135657.5-135657.29" switch \initial - attribute \src "libresoc.v:134050.9-134050.17" + attribute \src "libresoc.v:135657.9-135657.17" case 1'1 case end @@ -212164,43 +214584,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5484 $2\ibus__adr$next[44:0]$5485 + assign $1\ibus__adr$next[44:0]$5525 $2\ibus__adr$next[44:0]$5526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5485 \ibus__adr + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5485 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5526 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5485 \ibus__adr + assign $2\ibus__adr$next[44:0]$5526 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5484 \ibus__adr + assign $1\ibus__adr$next[44:0]$5525 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5486 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5527 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5486 $1\ibus__adr$next[44:0]$5484 + assign $3\ibus__adr$next[44:0]$5527 $1\ibus__adr$next[44:0]$5525 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5483 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5524 end - attribute \src "libresoc.v:134072.3-134094.6" - process $proc$libresoc.v:134072$5487 + attribute \src "libresoc.v:135679.3-135701.6" + process $proc$libresoc.v:135679$5528 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5488 $3\f_fetch_err_o$next[0:0]$5491 - attribute \src "libresoc.v:134073.5-134073.29" + assign $0\f_fetch_err_o$next[0:0]$5529 $3\f_fetch_err_o$next[0:0]$5532 + attribute \src "libresoc.v:135680.5-135680.29" switch \initial - attribute \src "libresoc.v:134073.9-134073.17" + attribute \src "libresoc.v:135680.9-135680.17" case 1'1 case end @@ -212209,44 +214629,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5489 $2\f_fetch_err_o$next[0:0]$5490 + assign $1\f_fetch_err_o$next[0:0]$5530 $2\f_fetch_err_o$next[0:0]$5531 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5490 1'1 + assign $2\f_fetch_err_o$next[0:0]$5531 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5490 1'0 + assign $2\f_fetch_err_o$next[0:0]$5531 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5490 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5531 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5489 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5491 1'0 + assign $3\f_fetch_err_o$next[0:0]$5532 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5491 $1\f_fetch_err_o$next[0:0]$5489 + assign $3\f_fetch_err_o$next[0:0]$5532 $1\f_fetch_err_o$next[0:0]$5530 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5488 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5529 end - attribute \src "libresoc.v:134095.3-134114.6" - process $proc$libresoc.v:134095$5492 + attribute \src "libresoc.v:135702.3-135721.6" + process $proc$libresoc.v:135702$5533 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5493 $3\f_badaddr_o$next[44:0]$5496 - attribute \src "libresoc.v:134096.5-134096.29" + assign $0\f_badaddr_o$next[44:0]$5534 $3\f_badaddr_o$next[44:0]$5537 + attribute \src "libresoc.v:135703.5-135703.29" switch \initial - attribute \src "libresoc.v:134096.9-134096.17" + attribute \src "libresoc.v:135703.9-135703.17" case 1'1 case end @@ -212255,39 +214675,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5494 $2\f_badaddr_o$next[44:0]$5495 + assign $1\f_badaddr_o$next[44:0]$5535 $2\f_badaddr_o$next[44:0]$5536 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5495 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5536 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5495 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5536 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5494 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5535 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5496 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5537 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5496 $1\f_badaddr_o$next[44:0]$5494 + assign $3\f_badaddr_o$next[44:0]$5537 $1\f_badaddr_o$next[44:0]$5535 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5493 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5534 end - attribute \src "libresoc.v:134115.3-134124.6" - process $proc$libresoc.v:134115$5497 + attribute \src "libresoc.v:135722.3-135731.6" + process $proc$libresoc.v:135722$5538 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:134116.5-134116.29" + attribute \src "libresoc.v:135723.5-135723.29" switch \initial - attribute \src "libresoc.v:134116.9-134116.17" + attribute \src "libresoc.v:135723.9-135723.17" case 1'1 case end @@ -212303,14 +214723,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:134125.3-134142.6" - process $proc$libresoc.v:134125$5498 + attribute \src "libresoc.v:135732.3-135749.6" + process $proc$libresoc.v:135732$5539 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:134126.5-134126.29" + attribute \src "libresoc.v:135733.5-135733.29" switch \initial - attribute \src "libresoc.v:134126.9-134126.17" + attribute \src "libresoc.v:135733.9-135733.17" case 1'1 case end @@ -212337,14 +214757,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:134143.3-134160.6" - process $proc$libresoc.v:134143$5499 + attribute \src "libresoc.v:135750.3-135767.6" + process $proc$libresoc.v:135750$5540 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:134144.5-134144.29" + attribute \src "libresoc.v:135751.5-135751.29" switch \initial - attribute \src "libresoc.v:134144.9-134144.17" + attribute \src "libresoc.v:135751.9-135751.17" case 1'1 case end @@ -212370,52 +214790,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:133900$5425_Y - connect \$11 $not$libresoc.v:133901$5426_Y - connect \$13 $and$libresoc.v:133902$5427_Y - connect \$15 $or$libresoc.v:133903$5428_Y - connect \$17 $not$libresoc.v:133904$5429_Y - connect \$1 $not$libresoc.v:133905$5430_Y - connect \$19 $or$libresoc.v:133906$5431_Y - connect \$21 $not$libresoc.v:133907$5432_Y - connect \$23 $and$libresoc.v:133908$5433_Y - connect \$25 $or$libresoc.v:133909$5434_Y - connect \$27 $not$libresoc.v:133910$5435_Y - connect \$29 $or$libresoc.v:133911$5436_Y - connect \$31 $not$libresoc.v:133912$5437_Y - connect \$33 $and$libresoc.v:133913$5438_Y - connect \$35 $or$libresoc.v:133914$5439_Y - connect \$37 $not$libresoc.v:133915$5440_Y - connect \$3 $and$libresoc.v:133916$5441_Y - connect \$39 $or$libresoc.v:133917$5442_Y - connect \$41 $not$libresoc.v:133918$5443_Y - connect \$43 $and$libresoc.v:133919$5444_Y - connect \$45 $and$libresoc.v:133920$5445_Y - connect \$47 $not$libresoc.v:133921$5446_Y - connect \$49 $and$libresoc.v:133922$5447_Y - connect \$51 $not$libresoc.v:133923$5448_Y - connect \$5 $or$libresoc.v:133924$5449_Y - connect \$7 $not$libresoc.v:133925$5450_Y + connect \$9 $or$libresoc.v:135507$5466_Y + connect \$11 $not$libresoc.v:135508$5467_Y + connect \$13 $and$libresoc.v:135509$5468_Y + connect \$15 $or$libresoc.v:135510$5469_Y + connect \$17 $not$libresoc.v:135511$5470_Y + connect \$1 $not$libresoc.v:135512$5471_Y + connect \$19 $or$libresoc.v:135513$5472_Y + connect \$21 $not$libresoc.v:135514$5473_Y + connect \$23 $and$libresoc.v:135515$5474_Y + connect \$25 $or$libresoc.v:135516$5475_Y + connect \$27 $not$libresoc.v:135517$5476_Y + connect \$29 $or$libresoc.v:135518$5477_Y + connect \$31 $not$libresoc.v:135519$5478_Y + connect \$33 $and$libresoc.v:135520$5479_Y + connect \$35 $or$libresoc.v:135521$5480_Y + connect \$37 $not$libresoc.v:135522$5481_Y + connect \$3 $and$libresoc.v:135523$5482_Y + connect \$39 $or$libresoc.v:135524$5483_Y + connect \$41 $not$libresoc.v:135525$5484_Y + connect \$43 $and$libresoc.v:135526$5485_Y + connect \$45 $and$libresoc.v:135527$5486_Y + connect \$47 $not$libresoc.v:135528$5487_Y + connect \$49 $and$libresoc.v:135529$5488_Y + connect \$51 $not$libresoc.v:135530$5489_Y + connect \$5 $or$libresoc.v:135531$5490_Y + connect \$7 $not$libresoc.v:135532$5491_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:134167.1-134494.10" +attribute \src "libresoc.v:135774.1-136101.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:134457.3-134468.6" + attribute \src "libresoc.v:136064.3-136075.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:134168.7-134168.20" + attribute \src "libresoc.v:135775.7-135775.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134469.3-134487.6" - wire width 2 $0\xer_ca$23[1:0]$5511 - attribute \src "libresoc.v:134457.3-134468.6" + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $0\xer_ca$23[1:0]$5552 + attribute \src "libresoc.v:136064.3-136075.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:134469.3-134487.6" - wire width 2 $1\xer_ca$23[1:0]$5512 - attribute \src "libresoc.v:134456.18-134456.100" - wire width 64 $not$libresoc.v:134456$5508_Y + attribute \src "libresoc.v:136076.3-136094.6" + wire width 2 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136063.18-136063.100" + wire width 64 $not$libresoc.v:136063$5549_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -212682,7 +215102,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134168.7-134168.15" + attribute \src "libresoc.v:135775.7-135775.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -212705,28 +215125,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:134456$5508 + cell $not $not$libresoc.v:136063$5549 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:134456$5508_Y + connect \Y $not$libresoc.v:136063$5549_Y end - attribute \src "libresoc.v:134168.7-134168.20" - process $proc$libresoc.v:134168$5513 + attribute \src "libresoc.v:135775.7-135775.20" + process $proc$libresoc.v:135775$5554 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134457.3-134468.6" - process $proc$libresoc.v:134457$5509 + attribute \src "libresoc.v:136064.3-136075.6" + process $proc$libresoc.v:136064$5550 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:134458.5-134458.29" + attribute \src "libresoc.v:136065.5-136065.29" switch \initial - attribute \src "libresoc.v:134458.9-134458.17" + attribute \src "libresoc.v:136065.9-136065.17" case 1'1 case end @@ -212744,14 +215164,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:134469.3-134487.6" - process $proc$libresoc.v:134469$5510 + attribute \src "libresoc.v:136076.3-136094.6" + process $proc$libresoc.v:136076$5551 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5511 $1\xer_ca$23[1:0]$5512 - attribute \src "libresoc.v:134470.5-134470.29" + assign $0\xer_ca$23[1:0]$5552 $1\xer_ca$23[1:0]$5553 + attribute \src "libresoc.v:136077.5-136077.29" switch \initial - attribute \src "libresoc.v:134470.9-134470.17" + attribute \src "libresoc.v:136077.9-136077.17" case 1'1 case end @@ -212760,22 +215180,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5512 2'00 + assign $1\xer_ca$23[1:0]$5553 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5512 2'11 + assign $1\xer_ca$23[1:0]$5553 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5512 \xer_ca + assign $1\xer_ca$23[1:0]$5553 \xer_ca case - assign $1\xer_ca$23[1:0]$5512 2'00 + assign $1\xer_ca$23[1:0]$5553 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5511 + update \xer_ca$23 $0\xer_ca$23[1:0]$5552 end - connect \$24 $not$libresoc.v:134456$5508_Y + connect \$24 $not$libresoc.v:136063$5549_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -212783,30 +215203,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:134498.1-134826.10" +attribute \src "libresoc.v:136105.1-136433.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:134788.3-134799.6" + attribute \src "libresoc.v:136395.3-136406.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:134499.7-134499.20" + attribute \src "libresoc.v:136106.7-136106.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134800.3-134818.6" - wire width 2 $0\xer_ca$23[1:0]$5517 - attribute \src "libresoc.v:134788.3-134799.6" + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $0\xer_ca$23[1:0]$5558 + attribute \src "libresoc.v:136395.3-136406.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:134800.3-134818.6" - wire width 2 $1\xer_ca$23[1:0]$5518 - attribute \src "libresoc.v:134787.18-134787.100" - wire width 64 $not$libresoc.v:134787$5514_Y + attribute \src "libresoc.v:136407.3-136425.6" + wire width 2 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136394.18-136394.100" + wire width 64 $not$libresoc.v:136394$5555_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134499.7-134499.15" + attribute \src "libresoc.v:136106.7-136106.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -213089,28 +215509,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:134787$5514 + cell $not $not$libresoc.v:136394$5555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:134787$5514_Y + connect \Y $not$libresoc.v:136394$5555_Y end - attribute \src "libresoc.v:134499.7-134499.20" - process $proc$libresoc.v:134499$5519 + attribute \src "libresoc.v:136106.7-136106.20" + process $proc$libresoc.v:136106$5560 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134788.3-134799.6" - process $proc$libresoc.v:134788$5515 + attribute \src "libresoc.v:136395.3-136406.6" + process $proc$libresoc.v:136395$5556 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:134789.5-134789.29" + attribute \src "libresoc.v:136396.5-136396.29" switch \initial - attribute \src "libresoc.v:134789.9-134789.17" + attribute \src "libresoc.v:136396.9-136396.17" case 1'1 case end @@ -213128,14 +215548,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:134800.3-134818.6" - process $proc$libresoc.v:134800$5516 + attribute \src "libresoc.v:136407.3-136425.6" + process $proc$libresoc.v:136407$5557 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5517 $1\xer_ca$23[1:0]$5518 - attribute \src "libresoc.v:134801.5-134801.29" + assign $0\xer_ca$23[1:0]$5558 $1\xer_ca$23[1:0]$5559 + attribute \src "libresoc.v:136408.5-136408.29" switch \initial - attribute \src "libresoc.v:134801.9-134801.17" + attribute \src "libresoc.v:136408.9-136408.17" case 1'1 case end @@ -213144,22 +215564,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5518 2'00 + assign $1\xer_ca$23[1:0]$5559 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5518 2'11 + assign $1\xer_ca$23[1:0]$5559 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5518 \xer_ca + assign $1\xer_ca$23[1:0]$5559 \xer_ca case - assign $1\xer_ca$23[1:0]$5518 2'00 + assign $1\xer_ca$23[1:0]$5559 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5517 + update \xer_ca$23 $0\xer_ca$23[1:0]$5558 end - connect \$24 $not$libresoc.v:134787$5514_Y + connect \$24 $not$libresoc.v:136394$5555_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -213168,26 +215588,26 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:134830.1-135133.10" +attribute \src "libresoc.v:136437.1-136740.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:135115.3-135126.6" + attribute \src "libresoc.v:136722.3-136733.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:134831.7-134831.20" + attribute \src "libresoc.v:136438.7-136438.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135115.3-135126.6" + attribute \src "libresoc.v:136722.3-136733.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:135114.18-135114.100" - wire width 64 $not$libresoc.v:135114$5520_Y + attribute \src "libresoc.v:136721.18-136721.100" + wire width 64 $not$libresoc.v:136721$5561_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:134831.7-134831.15" + attribute \src "libresoc.v:136438.7-136438.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -213466,28 +215886,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:135114$5520 + cell $not $not$libresoc.v:136721$5561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:135114$5520_Y + connect \Y $not$libresoc.v:136721$5561_Y end - attribute \src "libresoc.v:134831.7-134831.20" - process $proc$libresoc.v:134831$5522 + attribute \src "libresoc.v:136438.7-136438.20" + process $proc$libresoc.v:136438$5563 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135115.3-135126.6" - process $proc$libresoc.v:135115$5521 + attribute \src "libresoc.v:136722.3-136733.6" + process $proc$libresoc.v:136722$5562 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:135116.5-135116.29" + attribute \src "libresoc.v:136723.5-136723.29" switch \initial - attribute \src "libresoc.v:135116.9-135116.17" + attribute \src "libresoc.v:136723.9-136723.17" case 1'1 case end @@ -213505,7 +215925,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:135114$5520_Y + connect \$23 $not$libresoc.v:136721$5561_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -213513,26 +215933,26 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:135137.1-135440.10" +attribute \src "libresoc.v:136744.1-137047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:135422.3-135433.6" + attribute \src "libresoc.v:137029.3-137040.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:135138.7-135138.20" + attribute \src "libresoc.v:136745.7-136745.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135422.3-135433.6" + attribute \src "libresoc.v:137029.3-137040.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:135421.18-135421.100" - wire width 64 $not$libresoc.v:135421$5523_Y + attribute \src "libresoc.v:137028.18-137028.100" + wire width 64 $not$libresoc.v:137028$5564_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:135138.7-135138.15" + attribute \src "libresoc.v:136745.7-136745.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -213811,28 +216231,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:135421$5523 + cell $not $not$libresoc.v:137028$5564 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:135421$5523_Y + connect \Y $not$libresoc.v:137028$5564_Y end - attribute \src "libresoc.v:135138.7-135138.20" - process $proc$libresoc.v:135138$5525 + attribute \src "libresoc.v:136745.7-136745.20" + process $proc$libresoc.v:136745$5566 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135422.3-135433.6" - process $proc$libresoc.v:135422$5524 + attribute \src "libresoc.v:137029.3-137040.6" + process $proc$libresoc.v:137029$5565 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:135423.5-135423.29" + attribute \src "libresoc.v:137030.5-137030.29" switch \initial - attribute \src "libresoc.v:135423.9-135423.17" + attribute \src "libresoc.v:137030.9-137030.17" case 1'1 case end @@ -213850,7 +216270,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:135421$5523_Y + connect \$23 $not$libresoc.v:137028$5564_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -213858,7 +216278,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:135444.1-135700.10" +attribute \src "libresoc.v:137051.1-137307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -214119,100 +216539,118 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:135704.1-135923.10" +attribute \src "libresoc.v:137311.1-137571.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:135829.3-135835.6" - wire width 5 $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 - attribute \src "libresoc.v:135829.3-135835.6" - wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 - attribute \src "libresoc.v:135829.3-135835.6" - wire width 64 $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + attribute \src "libresoc.v:137453.3-137460.6" + wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:135829.3-135835.6" + attribute \src "libresoc.v:137453.3-137460.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:135858.3-135867.6" + attribute \src "libresoc.v:137453.3-137460.6" + wire width 5 $0\_4_[4:0] + attribute \src "libresoc.v:137503.3-137512.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:135705.7-135705.20" + attribute \src "libresoc.v:137312.7-137312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135849.3-135857.6" - wire $0\ren_delay$10$next[0:0]$5578 - attribute \src "libresoc.v:135782.3-135783.43" - wire $0\ren_delay$10[0:0]$5560 - attribute \src "libresoc.v:135748.7-135748.28" - wire $0\ren_delay$10[0:0]$5626 - attribute \src "libresoc.v:135878.3-135886.6" - wire $0\ren_delay$8$next[0:0]$5583 - attribute \src "libresoc.v:135786.3-135787.41" - wire $0\ren_delay$8[0:0]$5564 - attribute \src "libresoc.v:135752.7-135752.27" - wire $0\ren_delay$8[0:0]$5628 - attribute \src "libresoc.v:135897.3-135905.6" - wire $0\ren_delay$9$next[0:0]$5587 - attribute \src "libresoc.v:135784.3-135785.41" - wire $0\ren_delay$9[0:0]$5562 - attribute \src "libresoc.v:135756.7-135756.27" - wire $0\ren_delay$9[0:0]$5630 - attribute \src "libresoc.v:135840.3-135848.6" - wire $0\ren_delay$next[0:0]$5575 - attribute \src "libresoc.v:135788.3-135789.35" + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $0\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $0\ren_delay$10$next[0:0]$5631 + attribute \src "libresoc.v:137409.3-137410.43" + wire $0\ren_delay$10[0:0]$5607 + attribute \src "libresoc.v:137365.7-137365.28" + wire $0\ren_delay$10[0:0]$5674 + attribute \src "libresoc.v:137542.3-137550.6" + wire $0\ren_delay$11$next[0:0]$5635 + attribute \src "libresoc.v:137407.3-137408.43" + wire $0\ren_delay$11[0:0]$5605 + attribute \src "libresoc.v:137369.7-137369.28" + wire $0\ren_delay$11[0:0]$5676 + attribute \src "libresoc.v:137475.3-137483.6" + wire $0\ren_delay$12$next[0:0]$5622 + attribute \src "libresoc.v:137405.3-137406.43" + wire $0\ren_delay$12[0:0]$5603 + attribute \src "libresoc.v:137373.7-137373.28" + wire $0\ren_delay$12[0:0]$5678 + attribute \src "libresoc.v:137494.3-137502.6" + wire $0\ren_delay$13$next[0:0]$5626 + attribute \src "libresoc.v:137403.3-137404.43" + wire $0\ren_delay$13[0:0]$5601 + attribute \src "libresoc.v:137377.7-137377.28" + wire $0\ren_delay$13[0:0]$5680 + attribute \src "libresoc.v:137466.3-137474.6" + wire $0\ren_delay$next[0:0]$5619 + attribute \src "libresoc.v:137411.3-137412.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:135868.3-135877.6" + attribute \src "libresoc.v:137513.3-137522.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:135887.3-135896.6" + attribute \src "libresoc.v:137532.3-137541.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:135906.3-135915.6" + attribute \src "libresoc.v:137551.3-137560.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:135858.3-135867.6" + attribute \src "libresoc.v:137503.3-137512.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:135849.3-135857.6" - wire $1\ren_delay$10$next[0:0]$5579 - attribute \src "libresoc.v:135878.3-135886.6" - wire $1\ren_delay$8$next[0:0]$5584 - attribute \src "libresoc.v:135897.3-135905.6" - wire $1\ren_delay$9$next[0:0]$5588 - attribute \src "libresoc.v:135840.3-135848.6" - wire $1\ren_delay$next[0:0]$5576 - attribute \src "libresoc.v:135746.7-135746.23" + attribute \src "libresoc.v:137484.3-137493.6" + wire width 64 $1\pred__data_o[63:0] + attribute \src "libresoc.v:137523.3-137531.6" + wire $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137542.3-137550.6" + wire $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137475.3-137483.6" + wire $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137494.3-137502.6" + wire $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137466.3-137474.6" + wire $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137363.7-137363.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:135868.3-135877.6" + attribute \src "libresoc.v:137513.3-137522.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:135887.3-135896.6" + attribute \src "libresoc.v:137532.3-137541.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:135906.3-135915.6" + attribute \src "libresoc.v:137551.3-137560.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:135836.26-135836.32" - wire width 64 $memrd$\memory$libresoc.v:135836$5570_DATA - attribute \src "libresoc.v:135837.30-135837.36" - wire width 64 $memrd$\memory$libresoc.v:135837$5571_DATA - attribute \src "libresoc.v:135838.30-135838.36" - wire width 64 $memrd$\memory$libresoc.v:135838$5572_DATA - attribute \src "libresoc.v:135839.30-135839.36" - wire width 64 $memrd$\memory$libresoc.v:135839$5573_DATA + attribute \src "libresoc.v:137461.26-137461.32" + wire width 64 $memrd$\memory$libresoc.v:137461$5613_DATA + attribute \src "libresoc.v:137462.30-137462.36" + wire width 64 $memrd$\memory$libresoc.v:137462$5614_DATA + attribute \src "libresoc.v:137463.30-137463.36" + wire width 64 $memrd$\memory$libresoc.v:137463$5615_DATA + attribute \src "libresoc.v:137464.30-137464.36" + wire width 64 $memrd$\memory$libresoc.v:137464$5616_DATA + attribute \src "libresoc.v:137465.30-137465.36" + wire width 64 $memrd$\memory$libresoc.v:137465$5617_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:135834$5558_ADDR + wire width 5 $memwr$\memory$libresoc.v:137459$5599_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:135834$5558_DATA + wire width 64 $memwr$\memory$libresoc.v:137459$5599_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:135834$5558_EN - attribute \src "libresoc.v:135825.13-135825.16" + wire width 64 $memwr$\memory$libresoc.v:137459$5599_EN + attribute \src "libresoc.v:137448.13-137448.16" wire width 5 \_0_ - attribute \src "libresoc.v:135826.13-135826.16" + attribute \src "libresoc.v:137449.13-137449.16" wire width 5 \_1_ - attribute \src "libresoc.v:135827.13-135827.16" + attribute \src "libresoc.v:137450.13-137450.16" wire width 5 \_2_ - attribute \src "libresoc.v:135828.13-135828.16" + attribute \src "libresoc.v:137451.13-137451.16" wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "libresoc.v:137452.13-137452.16" + wire width 5 \_4_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 15 \dest1__addr @@ -214226,7 +216664,7 @@ module \int wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:135705.7-135705.15" + attribute \src "libresoc.v:137312.7-137312.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -214237,6 +216675,8 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$3 @@ -214244,12 +216684,20 @@ module \int wire width 64 \memory_r_data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 5 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 \pred__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \pred__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \pred__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" @@ -214257,13 +216705,17 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8 + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8$next + wire \ren_delay$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9 + wire \ren_delay$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9$next + wire \ren_delay$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -214284,330 +216736,330 @@ module \int wire width 64 output 11 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src3__ren - attribute \src "libresoc.v:135790.14-135790.20" + attribute \src "libresoc.v:137413.14-137413.20" memory width 64 size 32 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5590 + cell $meminit $meminit$\memory$libresoc.v:0$5638 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5590 + parameter \PRIORITY 5638 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5591 + cell $meminit $meminit$\memory$libresoc.v:0$5639 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5591 + parameter \PRIORITY 5639 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5592 + cell $meminit $meminit$\memory$libresoc.v:0$5640 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5592 + parameter \PRIORITY 5640 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5593 + cell $meminit $meminit$\memory$libresoc.v:0$5641 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5593 + parameter \PRIORITY 5641 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5594 + cell $meminit $meminit$\memory$libresoc.v:0$5642 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5594 + parameter \PRIORITY 5642 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5595 + cell $meminit $meminit$\memory$libresoc.v:0$5643 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5595 + parameter \PRIORITY 5643 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5596 + cell $meminit $meminit$\memory$libresoc.v:0$5644 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5596 + parameter \PRIORITY 5644 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5597 + cell $meminit $meminit$\memory$libresoc.v:0$5645 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5597 + parameter \PRIORITY 5645 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5598 + cell $meminit $meminit$\memory$libresoc.v:0$5646 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5598 + parameter \PRIORITY 5646 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5599 + cell $meminit $meminit$\memory$libresoc.v:0$5647 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5599 + parameter \PRIORITY 5647 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5600 + cell $meminit $meminit$\memory$libresoc.v:0$5648 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5600 + parameter \PRIORITY 5648 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5601 + cell $meminit $meminit$\memory$libresoc.v:0$5649 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5601 + parameter \PRIORITY 5649 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5602 + cell $meminit $meminit$\memory$libresoc.v:0$5650 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5602 + parameter \PRIORITY 5650 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5603 + cell $meminit $meminit$\memory$libresoc.v:0$5651 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5603 + parameter \PRIORITY 5651 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5604 + cell $meminit $meminit$\memory$libresoc.v:0$5652 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5604 + parameter \PRIORITY 5652 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5605 + cell $meminit $meminit$\memory$libresoc.v:0$5653 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5605 + parameter \PRIORITY 5653 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5606 + cell $meminit $meminit$\memory$libresoc.v:0$5654 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5606 + parameter \PRIORITY 5654 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5607 + cell $meminit $meminit$\memory$libresoc.v:0$5655 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5607 + parameter \PRIORITY 5655 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5608 + cell $meminit $meminit$\memory$libresoc.v:0$5656 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5608 + parameter \PRIORITY 5656 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5609 + cell $meminit $meminit$\memory$libresoc.v:0$5657 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5609 + parameter \PRIORITY 5657 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5610 + cell $meminit $meminit$\memory$libresoc.v:0$5658 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5610 + parameter \PRIORITY 5658 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5611 + cell $meminit $meminit$\memory$libresoc.v:0$5659 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5611 + parameter \PRIORITY 5659 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5612 + cell $meminit $meminit$\memory$libresoc.v:0$5660 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5612 + parameter \PRIORITY 5660 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5613 + cell $meminit $meminit$\memory$libresoc.v:0$5661 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5613 + parameter \PRIORITY 5661 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5614 + cell $meminit $meminit$\memory$libresoc.v:0$5662 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5614 + parameter \PRIORITY 5662 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5615 + cell $meminit $meminit$\memory$libresoc.v:0$5663 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5615 + parameter \PRIORITY 5663 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5616 + cell $meminit $meminit$\memory$libresoc.v:0$5664 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5616 + parameter \PRIORITY 5664 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5617 + cell $meminit $meminit$\memory$libresoc.v:0$5665 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5617 + parameter \PRIORITY 5665 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5618 + cell $meminit $meminit$\memory$libresoc.v:0$5666 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5618 + parameter \PRIORITY 5666 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5619 + cell $meminit $meminit$\memory$libresoc.v:0$5667 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5619 + parameter \PRIORITY 5667 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5620 + cell $meminit $meminit$\memory$libresoc.v:0$5668 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5620 + parameter \PRIORITY 5668 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5621 + cell $meminit $meminit$\memory$libresoc.v:0$5669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5621 + parameter \PRIORITY 5669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:135836.26-135836.32" - cell $memrd $memrd$\memory$libresoc.v:135836$5570 + attribute \src "libresoc.v:137461.26-137461.32" + cell $memrd $memrd$\memory$libresoc.v:137461$5613 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214616,11 +217068,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135836$5570_DATA + connect \DATA $memrd$\memory$libresoc.v:137461$5613_DATA connect \EN 1'x end - attribute \src "libresoc.v:135837.30-135837.36" - cell $memrd $memrd$\memory$libresoc.v:135837$5571 + attribute \src "libresoc.v:137462.30-137462.36" + cell $memrd $memrd$\memory$libresoc.v:137462$5614 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214629,11 +217081,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135837$5571_DATA + connect \DATA $memrd$\memory$libresoc.v:137462$5614_DATA connect \EN 1'x end - attribute \src "libresoc.v:135838.30-135838.36" - cell $memrd $memrd$\memory$libresoc.v:135838$5572 + attribute \src "libresoc.v:137463.30-137463.36" + cell $memrd $memrd$\memory$libresoc.v:137463$5615 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214642,11 +217094,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135838$5572_DATA + connect \DATA $memrd$\memory$libresoc.v:137463$5615_DATA connect \EN 1'x end - attribute \src "libresoc.v:135839.30-135839.36" - cell $memrd $memrd$\memory$libresoc.v:135839$5573 + attribute \src "libresoc.v:137464.30-137464.36" + cell $memrd $memrd$\memory$libresoc.v:137464$5616 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -214655,97 +217107,126 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135839$5573_DATA + connect \DATA $memrd$\memory$libresoc.v:137464$5616_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:137465.30-137465.36" + cell $memrd $memrd$\memory$libresoc.v:137465$5617 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_4_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:137465$5617_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5622 + cell $memwr $memwr$\memory$libresoc.v:0$5670 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5622 + parameter \PRIORITY 5670 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:135834$5558_ADDR + connect \ADDR $memwr$\memory$libresoc.v:137459$5599_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:135834$5558_DATA - connect \EN $memwr$\memory$libresoc.v:135834$5558_EN + connect \DATA $memwr$\memory$libresoc.v:137459$5599_DATA + connect \EN $memwr$\memory$libresoc.v:137459$5599_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5631 + process $proc$libresoc.v:0$5681 sync always sync init end - attribute \src "libresoc.v:135705.7-135705.20" - process $proc$libresoc.v:135705$5623 + attribute \src "libresoc.v:137312.7-137312.20" + process $proc$libresoc.v:137312$5671 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135746.7-135746.23" - process $proc$libresoc.v:135746$5624 + attribute \src "libresoc.v:137363.7-137363.23" + process $proc$libresoc.v:137363$5672 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:135748.7-135748.28" - process $proc$libresoc.v:135748$5625 + attribute \src "libresoc.v:137365.7-137365.28" + process $proc$libresoc.v:137365$5673 assign { } { } - assign $0\ren_delay$10[0:0]$5626 1'0 + assign $0\ren_delay$10[0:0]$5674 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5626 + update \ren_delay$10 $0\ren_delay$10[0:0]$5674 end - attribute \src "libresoc.v:135752.7-135752.27" - process $proc$libresoc.v:135752$5627 + attribute \src "libresoc.v:137369.7-137369.28" + process $proc$libresoc.v:137369$5675 assign { } { } - assign $0\ren_delay$8[0:0]$5628 1'0 + assign $0\ren_delay$11[0:0]$5676 1'0 sync always sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5628 + update \ren_delay$11 $0\ren_delay$11[0:0]$5676 end - attribute \src "libresoc.v:135756.7-135756.27" - process $proc$libresoc.v:135756$5629 + attribute \src "libresoc.v:137373.7-137373.28" + process $proc$libresoc.v:137373$5677 assign { } { } - assign $0\ren_delay$9[0:0]$5630 1'0 + assign $0\ren_delay$12[0:0]$5678 1'0 sync always sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5630 + update \ren_delay$12 $0\ren_delay$12[0:0]$5678 end - attribute \src "libresoc.v:135782.3-135783.43" - process $proc$libresoc.v:135782$5559 + attribute \src "libresoc.v:137377.7-137377.28" + process $proc$libresoc.v:137377$5679 assign { } { } - assign $0\ren_delay$10[0:0]$5560 \ren_delay$10$next + assign $0\ren_delay$13[0:0]$5680 1'0 + sync always + sync init + update \ren_delay$13 $0\ren_delay$13[0:0]$5680 + end + attribute \src "libresoc.v:137403.3-137404.43" + process $proc$libresoc.v:137403$5600 + assign { } { } + assign $0\ren_delay$13[0:0]$5601 \ren_delay$13$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5560 + update \ren_delay$13 $0\ren_delay$13[0:0]$5601 end - attribute \src "libresoc.v:135784.3-135785.41" - process $proc$libresoc.v:135784$5561 + attribute \src "libresoc.v:137405.3-137406.43" + process $proc$libresoc.v:137405$5602 assign { } { } - assign $0\ren_delay$9[0:0]$5562 \ren_delay$9$next + assign $0\ren_delay$12[0:0]$5603 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5562 + update \ren_delay$12 $0\ren_delay$12[0:0]$5603 end - attribute \src "libresoc.v:135786.3-135787.41" - process $proc$libresoc.v:135786$5563 + attribute \src "libresoc.v:137407.3-137408.43" + process $proc$libresoc.v:137407$5604 assign { } { } - assign $0\ren_delay$8[0:0]$5564 \ren_delay$8$next + assign $0\ren_delay$11[0:0]$5605 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5564 + update \ren_delay$11 $0\ren_delay$11[0:0]$5605 end - attribute \src "libresoc.v:135788.3-135789.35" - process $proc$libresoc.v:135788$5565 + attribute \src "libresoc.v:137409.3-137410.43" + process $proc$libresoc.v:137409$5606 + assign { } { } + assign $0\ren_delay$10[0:0]$5607 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5607 + end + attribute \src "libresoc.v:137411.3-137412.35" + process $proc$libresoc.v:137411$5608 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:135829.3-135835.6" - process $proc$libresoc.v:135829$5566 + attribute \src "libresoc.v:137453.3-137460.6" + process $proc$libresoc.v:137453$5609 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -214753,20 +217234,21 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 5'xxxxx - assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 5'xxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[4:0] \src1__addr assign $0\_1_[4:0] \src2__addr assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:135834.5-135834.58" + assign $0\_3_[4:0] 5'00000 + assign $0\_4_[4:0] \dmi__addr + attribute \src "libresoc.v:137459.5-137459.58" switch \dest1__wen - attribute \src "libresoc.v:135834.9-135834.19" + attribute \src "libresoc.v:137459.9-137459.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 \dest1__addr - assign $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 \dest1__addr + assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk @@ -214774,18 +217256,19 @@ module \int update \_1_ $0\_1_[4:0] update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:135834$5558_ADDR $0$memwr$\memory$libresoc.v:135834$5558_ADDR[4:0]$5567 - update $memwr$\memory$libresoc.v:135834$5558_DATA $0$memwr$\memory$libresoc.v:135834$5558_DATA[63:0]$5568 - update $memwr$\memory$libresoc.v:135834$5558_EN $0$memwr$\memory$libresoc.v:135834$5558_EN[63:0]$5569 + update \_4_ $0\_4_[4:0] + update $memwr$\memory$libresoc.v:137459$5599_ADDR $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 + update $memwr$\memory$libresoc.v:137459$5599_DATA $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 + update $memwr$\memory$libresoc.v:137459$5599_EN $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 end - attribute \src "libresoc.v:135840.3-135848.6" - process $proc$libresoc.v:135840$5574 + attribute \src "libresoc.v:137466.3-137474.6" + process $proc$libresoc.v:137466$5618 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5575 $1\ren_delay$next[0:0]$5576 - attribute \src "libresoc.v:135841.5-135841.29" + assign $0\ren_delay$next[0:0]$5619 $1\ren_delay$next[0:0]$5620 + attribute \src "libresoc.v:137467.5-137467.29" switch \initial - attribute \src "libresoc.v:135841.9-135841.17" + attribute \src "libresoc.v:137467.9-137467.17" case 1'1 case end @@ -214794,21 +217277,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5576 1'0 + assign $1\ren_delay$next[0:0]$5620 1'0 case - assign $1\ren_delay$next[0:0]$5576 \src1__ren + assign $1\ren_delay$next[0:0]$5620 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5575 + update \ren_delay$next $0\ren_delay$next[0:0]$5619 end - attribute \src "libresoc.v:135849.3-135857.6" - process $proc$libresoc.v:135849$5577 + attribute \src "libresoc.v:137475.3-137483.6" + process $proc$libresoc.v:137475$5621 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5578 $1\ren_delay$10$next[0:0]$5579 - attribute \src "libresoc.v:135850.5-135850.29" + assign $0\ren_delay$12$next[0:0]$5622 $1\ren_delay$12$next[0:0]$5623 + attribute \src "libresoc.v:137476.5-137476.29" switch \initial - attribute \src "libresoc.v:135850.9-135850.17" + attribute \src "libresoc.v:137476.9-137476.17" case 1'1 case end @@ -214817,44 +217300,90 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5579 1'0 + assign $1\ren_delay$12$next[0:0]$5623 1'0 case - assign $1\ren_delay$10$next[0:0]$5579 \dmi__ren + assign $1\ren_delay$12$next[0:0]$5623 \pred__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5578 + update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5622 end - attribute \src "libresoc.v:135858.3-135867.6" - process $proc$libresoc.v:135858$5580 + attribute \src "libresoc.v:137484.3-137493.6" + process $proc$libresoc.v:137484$5624 + assign { } { } + assign { } { } + assign $0\pred__data_o[63:0] $1\pred__data_o[63:0] + attribute \src "libresoc.v:137485.5-137485.29" + switch \initial + attribute \src "libresoc.v:137485.9-137485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pred__data_o[63:0] \memory_r_data$7 + case + assign $1\pred__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \pred__data_o $0\pred__data_o[63:0] + end + attribute \src "libresoc.v:137494.3-137502.6" + process $proc$libresoc.v:137494$5625 + assign { } { } + assign { } { } + assign $0\ren_delay$13$next[0:0]$5626 $1\ren_delay$13$next[0:0]$5627 + attribute \src "libresoc.v:137495.5-137495.29" + switch \initial + attribute \src "libresoc.v:137495.9-137495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$13$next[0:0]$5627 1'0 + case + assign $1\ren_delay$13$next[0:0]$5627 \dmi__ren + end + sync always + update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5626 + end + attribute \src "libresoc.v:137503.3-137512.6" + process $proc$libresoc.v:137503$5628 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:135859.5-135859.29" + attribute \src "libresoc.v:137504.5-137504.29" switch \initial - attribute \src "libresoc.v:135859.9-135859.17" + attribute \src "libresoc.v:137504.9-137504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 + switch \ren_delay$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$7 + assign $1\dmi__data_o[63:0] \memory_r_data$9 case assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:135868.3-135877.6" - process $proc$libresoc.v:135868$5581 + attribute \src "libresoc.v:137513.3-137522.6" + process $proc$libresoc.v:137513$5629 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:135869.5-135869.29" + attribute \src "libresoc.v:137514.5-137514.29" switch \initial - attribute \src "libresoc.v:135869.9-135869.17" + attribute \src "libresoc.v:137514.9-137514.17" case 1'1 case end @@ -214870,14 +217399,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:135878.3-135886.6" - process $proc$libresoc.v:135878$5582 + attribute \src "libresoc.v:137523.3-137531.6" + process $proc$libresoc.v:137523$5630 assign { } { } assign { } { } - assign $0\ren_delay$8$next[0:0]$5583 $1\ren_delay$8$next[0:0]$5584 - attribute \src "libresoc.v:135879.5-135879.29" + assign $0\ren_delay$10$next[0:0]$5631 $1\ren_delay$10$next[0:0]$5632 + attribute \src "libresoc.v:137524.5-137524.29" switch \initial - attribute \src "libresoc.v:135879.9-135879.17" + attribute \src "libresoc.v:137524.9-137524.17" case 1'1 case end @@ -214886,26 +217415,26 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$8$next[0:0]$5584 1'0 + assign $1\ren_delay$10$next[0:0]$5632 1'0 case - assign $1\ren_delay$8$next[0:0]$5584 \src2__ren + assign $1\ren_delay$10$next[0:0]$5632 \src2__ren end sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5583 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5631 end - attribute \src "libresoc.v:135887.3-135896.6" - process $proc$libresoc.v:135887$5585 + attribute \src "libresoc.v:137532.3-137541.6" + process $proc$libresoc.v:137532$5633 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:135888.5-135888.29" + attribute \src "libresoc.v:137533.5-137533.29" switch \initial - attribute \src "libresoc.v:135888.9-135888.17" + attribute \src "libresoc.v:137533.9-137533.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$8 + switch \ren_delay$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -214916,14 +217445,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:135897.3-135905.6" - process $proc$libresoc.v:135897$5586 + attribute \src "libresoc.v:137542.3-137550.6" + process $proc$libresoc.v:137542$5634 assign { } { } assign { } { } - assign $0\ren_delay$9$next[0:0]$5587 $1\ren_delay$9$next[0:0]$5588 - attribute \src "libresoc.v:135898.5-135898.29" + assign $0\ren_delay$11$next[0:0]$5635 $1\ren_delay$11$next[0:0]$5636 + attribute \src "libresoc.v:137543.5-137543.29" switch \initial - attribute \src "libresoc.v:135898.9-135898.17" + attribute \src "libresoc.v:137543.9-137543.17" case 1'1 case end @@ -214932,26 +217461,26 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$9$next[0:0]$5588 1'0 + assign $1\ren_delay$11$next[0:0]$5636 1'0 case - assign $1\ren_delay$9$next[0:0]$5588 \src3__ren + assign $1\ren_delay$11$next[0:0]$5636 \src3__ren end sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5587 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5635 end - attribute \src "libresoc.v:135906.3-135915.6" - process $proc$libresoc.v:135906$5589 + attribute \src "libresoc.v:137551.3-137560.6" + process $proc$libresoc.v:137551$5637 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:135907.5-135907.29" + attribute \src "libresoc.v:137552.5-137552.29" switch \initial - attribute \src "libresoc.v:135907.9-135907.17" + attribute \src "libresoc.v:137552.9-137552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$9 + switch \ren_delay$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -214962,937 +217491,937 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:135836$5570_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:135837$5571_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:135838$5572_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:135839$5573_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:137461$5613_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:137462$5614_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:137463$5615_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:137464$5616_DATA + connect \memory_r_data$9 $memrd$\memory$libresoc.v:137465$5617_DATA + connect \pred__addr 5'00000 + connect \pred__ren 1'0 connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr - connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$8 \dmi__addr + connect \memory_r_addr$6 5'00000 connect \memory_r_addr$4 \src3__addr connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:135927.1-138650.10" +attribute \src "libresoc.v:137575.1-140282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:138080.3-138106.6" + attribute \src "libresoc.v:139714.3-139740.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:137728.3-137743.6" + attribute \src "libresoc.v:139362.3-139377.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$6043 - attribute \src "libresoc.v:137631.3-137632.41" + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6091 + attribute \src "libresoc.v:139265.3-139266.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $0\dmi0__din$next[63:0]$6056 - attribute \src "libresoc.v:137627.3-137628.35" + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $0\dmi0__din$next[63:0]$6104 + attribute \src "libresoc.v:139261.3-139262.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:137930.3-137946.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5980 - attribute \src "libresoc.v:137659.3-137660.47" + attribute \src "libresoc.v:139564.3-139580.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6028 + attribute \src "libresoc.v:139293.3-139294.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5984 - attribute \src "libresoc.v:137657.3-137658.47" + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 + attribute \src "libresoc.v:139291.3-139292.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:137912.3-137920.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5974 - attribute \src "libresoc.v:137663.3-137664.63" + attribute \src "libresoc.v:139546.3-139554.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:139297.3-139298.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:137921.3-137929.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 - attribute \src "libresoc.v:137661.3-137662.73" + attribute \src "libresoc.v:139555.3-139563.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:139295.3-139296.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6061 - attribute \src "libresoc.v:137625.3-137626.45" + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 + attribute \src "libresoc.v:139259.3-139260.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5995 - attribute \src "libresoc.v:137651.3-137652.47" + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 + attribute \src "libresoc.v:139285.3-139286.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5999 - attribute \src "libresoc.v:137649.3-137650.47" + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 + attribute \src "libresoc.v:139283.3-139284.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:137968.3-137976.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5989 - attribute \src "libresoc.v:137655.3-137656.63" + attribute \src "libresoc.v:139602.3-139610.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6037 + attribute \src "libresoc.v:139289.3-139290.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:137977.3-137985.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5992 - attribute \src "libresoc.v:137653.3-137654.73" + attribute \src "libresoc.v:139611.3-139619.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:139287.3-139288.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $0\fsm_state$503$next[2:0]$6049 - attribute \src "libresoc.v:137629.3-137630.45" - wire width 3 $0\fsm_state$503[2:0]$5895 - attribute \src "libresoc.v:136573.13-136573.35" - wire width 3 $0\fsm_state$503[2:0]$6098 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $0\fsm_state$next[2:0]$6026 - attribute \src "libresoc.v:137637.3-137638.35" + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $0\fsm_state$499$next[2:0]$6097 + attribute \src "libresoc.v:139263.3-139264.45" + wire width 3 $0\fsm_state$499[2:0]$5943 + attribute \src "libresoc.v:138217.13-138217.35" + wire width 3 $0\fsm_state$499[2:0]$6146 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $0\fsm_state$next[2:0]$6074 + attribute \src "libresoc.v:139271.3-139272.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:135928.7-135928.20" + attribute \src "libresoc.v:137576.7-137576.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $0\io_bd$next[153:0]$6081 - attribute \src "libresoc.v:137689.3-137690.27" - wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $0\io_sr$next[153:0]$6077 - attribute \src "libresoc.v:137691.3-137692.27" - wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$6020 - attribute \src "libresoc.v:137639.3-137640.41" + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $0\io_bd$next[151:0]$6129 + attribute \src "libresoc.v:139323.3-139324.27" + wire width 152 $0\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $0\io_sr$next[151:0]$6125 + attribute \src "libresoc.v:139325.3-139326.27" + wire width 152 $0\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6068 + attribute \src "libresoc.v:139273.3-139274.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$6033 - attribute \src "libresoc.v:137635.3-137636.45" + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 + attribute \src "libresoc.v:139269.3-139270.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:137818.3-137834.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5950 - attribute \src "libresoc.v:137675.3-137676.53" + attribute \src "libresoc.v:139452.3-139468.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 + attribute \src "libresoc.v:139309.3-139310.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5954 - attribute \src "libresoc.v:137673.3-137674.53" + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 + attribute \src "libresoc.v:139307.3-139308.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:137800.3-137808.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5944 - attribute \src "libresoc.v:137679.3-137680.69" + attribute \src "libresoc.v:139434.3-139442.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:139313.3-139314.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:137809.3-137817.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 - attribute \src "libresoc.v:137677.3-137678.79" + attribute \src "libresoc.v:139443.3-139451.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:139311.3-139312.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6038 - attribute \src "libresoc.v:137633.3-137634.51" + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 + attribute \src "libresoc.v:139267.3-139268.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5965 - attribute \src "libresoc.v:137667.3-137668.53" + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 + attribute \src "libresoc.v:139301.3-139302.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5969 - attribute \src "libresoc.v:137665.3-137666.53" + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 + attribute \src "libresoc.v:139299.3-139300.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:137856.3-137864.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5959 - attribute \src "libresoc.v:137671.3-137672.69" + attribute \src "libresoc.v:139490.3-139498.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:139305.3-139306.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:137865.3-137873.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 - attribute \src "libresoc.v:137669.3-137670.79" + attribute \src "libresoc.v:139499.3-139507.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:139303.3-139304.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:137762.3-137778.6" - wire $0\sr0__oe$next[0:0]$5935 - attribute \src "libresoc.v:137683.3-137684.31" + attribute \src "libresoc.v:139396.3-139412.6" + wire $0\sr0__oe$next[0:0]$5983 + attribute \src "libresoc.v:139317.3-139318.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $0\sr0_reg$next[2:0]$5939 - attribute \src "libresoc.v:137681.3-137682.31" + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $0\sr0_reg$next[2:0]$5987 + attribute \src "libresoc.v:139315.3-139316.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:137744.3-137752.6" - wire $0\sr0_update_core$next[0:0]$5929 - attribute \src "libresoc.v:137687.3-137688.47" + attribute \src "libresoc.v:139378.3-139386.6" + wire $0\sr0_update_core$next[0:0]$5977 + attribute \src "libresoc.v:139321.3-139322.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:137753.3-137761.6" - wire $0\sr0_update_core_prev$next[0:0]$5932 - attribute \src "libresoc.v:137685.3-137686.57" + attribute \src "libresoc.v:139387.3-139395.6" + wire $0\sr0_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:139319.3-139320.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:138396.3-138405.6" + attribute \src "libresoc.v:140030.3-140039.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:138042.3-138058.6" - wire $0\sr5__oe$next[0:0]$6010 - attribute \src "libresoc.v:137643.3-137644.31" + attribute \src "libresoc.v:139676.3-139692.6" + wire $0\sr5__oe$next[0:0]$6058 + attribute \src "libresoc.v:139277.3-139278.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $0\sr5_reg$next[2:0]$6014 - attribute \src "libresoc.v:137641.3-137642.31" + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $0\sr5_reg$next[2:0]$6062 + attribute \src "libresoc.v:139275.3-139276.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:138024.3-138032.6" - wire $0\sr5_update_core$next[0:0]$6004 - attribute \src "libresoc.v:137647.3-137648.47" + attribute \src "libresoc.v:139658.3-139666.6" + wire $0\sr5_update_core$next[0:0]$6052 + attribute \src "libresoc.v:139281.3-139282.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:138033.3-138041.6" - wire $0\sr5_update_core_prev$next[0:0]$6007 - attribute \src "libresoc.v:137645.3-137646.57" + attribute \src "libresoc.v:139667.3-139675.6" + wire $0\sr5_update_core_prev$next[0:0]$6055 + attribute \src "libresoc.v:139279.3-139280.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_dcache_en$next[0:0]$6066 - attribute \src "libresoc.v:137621.3-137622.41" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_dcache_en$next[0:0]$6114 + attribute \src "libresoc.v:139255.3-139256.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_icache_en$next[0:0]$6067 - attribute \src "libresoc.v:137619.3-137620.41" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_icache_en$next[0:0]$6115 + attribute \src "libresoc.v:139253.3-139254.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $0\wb_sram_en$next[0:0]$6068 - attribute \src "libresoc.v:137623.3-137624.37" + attribute \src "libresoc.v:140009.3-140029.6" + wire $0\wb_sram_en$next[0:0]$6116 + attribute \src "libresoc.v:139257.3-139258.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:138080.3-138106.6" + attribute \src "libresoc.v:139714.3-139740.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:137728.3-137743.6" + attribute \src "libresoc.v:139362.3-139377.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$6044 - attribute \src "libresoc.v:136486.13-136486.32" + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6092 + attribute \src "libresoc.v:138130.13-138130.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $1\dmi0__din$next[63:0]$6057 - attribute \src "libresoc.v:136491.14-136491.46" + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $1\dmi0__din$next[63:0]$6105 + attribute \src "libresoc.v:138135.14-138135.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:137930.3-137946.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5981 - attribute \src "libresoc.v:136505.7-136505.29" + attribute \src "libresoc.v:139564.3-139580.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6029 + attribute \src "libresoc.v:138149.7-138149.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5985 - attribute \src "libresoc.v:136513.13-136513.36" + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 + attribute \src "libresoc.v:138157.13-138157.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:137912.3-137920.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5975 - attribute \src "libresoc.v:136521.7-136521.37" + attribute \src "libresoc.v:139546.3-139554.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:138165.7-138165.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:137921.3-137929.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 - attribute \src "libresoc.v:136525.7-136525.42" + attribute \src "libresoc.v:139555.3-139563.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:138169.7-138169.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6062 - attribute \src "libresoc.v:136529.14-136529.51" + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 + attribute \src "libresoc.v:138173.14-138173.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5996 - attribute \src "libresoc.v:136535.13-136535.35" + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 + attribute \src "libresoc.v:138179.13-138179.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$6000 - attribute \src "libresoc.v:136543.14-136543.52" + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 + attribute \src "libresoc.v:138187.14-138187.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:137968.3-137976.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5990 - attribute \src "libresoc.v:136551.7-136551.37" + attribute \src "libresoc.v:139602.3-139610.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:138195.7-138195.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:137977.3-137985.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5993 - attribute \src "libresoc.v:136555.7-136555.42" + attribute \src "libresoc.v:139611.3-139619.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:138199.7-138199.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $1\fsm_state$503$next[2:0]$6050 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $1\fsm_state$next[2:0]$6027 - attribute \src "libresoc.v:136571.13-136571.29" + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $1\fsm_state$499$next[2:0]$6098 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $1\fsm_state$next[2:0]$6075 + attribute \src "libresoc.v:138215.13-138215.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $1\io_bd$next[153:0]$6082 - attribute \src "libresoc.v:136771.15-136771.67" - wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $1\io_sr$next[153:0]$6078 - attribute \src "libresoc.v:136783.15-136783.67" - wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$6021 - attribute \src "libresoc.v:136792.14-136792.41" + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $1\io_bd$next[151:0]$6130 + attribute \src "libresoc.v:138415.15-138415.66" + wire width 152 $1\io_bd[151:0] + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $1\io_sr$next[151:0]$6126 + attribute \src "libresoc.v:138427.15-138427.66" + wire width 152 $1\io_sr[151:0] + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6069 + attribute \src "libresoc.v:138436.14-138436.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$6034 - attribute \src "libresoc.v:136801.14-136801.51" + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 + attribute \src "libresoc.v:138445.14-138445.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:137818.3-137834.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5951 - attribute \src "libresoc.v:136815.7-136815.32" + attribute \src "libresoc.v:139452.3-139468.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 + attribute \src "libresoc.v:138459.7-138459.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5955 - attribute \src "libresoc.v:136823.14-136823.47" + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + attribute \src "libresoc.v:138467.14-138467.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:137800.3-137808.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:136831.7-136831.40" + attribute \src "libresoc.v:139434.3-139442.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:138475.7-138475.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:137809.3-137817.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:136835.7-136835.45" + attribute \src "libresoc.v:139443.3-139451.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:138479.7-138479.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6039 - attribute \src "libresoc.v:136839.14-136839.54" + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 + attribute \src "libresoc.v:138483.14-138483.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5966 - attribute \src "libresoc.v:136845.13-136845.38" + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 + attribute \src "libresoc.v:138489.13-138489.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5970 - attribute \src "libresoc.v:136853.14-136853.55" + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 + attribute \src "libresoc.v:138497.14-138497.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:137856.3-137864.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5960 - attribute \src "libresoc.v:136861.7-136861.40" + attribute \src "libresoc.v:139490.3-139498.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:138505.7-138505.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:137865.3-137873.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:136865.7-136865.45" + attribute \src "libresoc.v:139499.3-139507.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:138509.7-138509.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:137762.3-137778.6" - wire $1\sr0__oe$next[0:0]$5936 - attribute \src "libresoc.v:137295.7-137295.21" + attribute \src "libresoc.v:139396.3-139412.6" + wire $1\sr0__oe$next[0:0]$5984 + attribute \src "libresoc.v:138931.7-138931.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $1\sr0_reg$next[2:0]$5940 - attribute \src "libresoc.v:137303.13-137303.27" + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $1\sr0_reg$next[2:0]$5988 + attribute \src "libresoc.v:138939.13-138939.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:137744.3-137752.6" - wire $1\sr0_update_core$next[0:0]$5930 - attribute \src "libresoc.v:137311.7-137311.29" + attribute \src "libresoc.v:139378.3-139386.6" + wire $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:138947.7-138947.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:137753.3-137761.6" - wire $1\sr0_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:137315.7-137315.34" + attribute \src "libresoc.v:139387.3-139395.6" + wire $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:138951.7-138951.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:138396.3-138405.6" + attribute \src "libresoc.v:140030.3-140039.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:138042.3-138058.6" - wire $1\sr5__oe$next[0:0]$6011 - attribute \src "libresoc.v:137325.7-137325.21" + attribute \src "libresoc.v:139676.3-139692.6" + wire $1\sr5__oe$next[0:0]$6059 + attribute \src "libresoc.v:138961.7-138961.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $1\sr5_reg$next[2:0]$6015 - attribute \src "libresoc.v:137333.13-137333.27" + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $1\sr5_reg$next[2:0]$6063 + attribute \src "libresoc.v:138969.13-138969.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:138024.3-138032.6" - wire $1\sr5_update_core$next[0:0]$6005 - attribute \src "libresoc.v:137341.7-137341.29" + attribute \src "libresoc.v:139658.3-139666.6" + wire $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:138977.7-138977.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:138033.3-138041.6" - wire $1\sr5_update_core_prev$next[0:0]$6008 - attribute \src "libresoc.v:137345.7-137345.34" + attribute \src "libresoc.v:139667.3-139675.6" + wire $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:138981.7-138981.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_dcache_en$next[0:0]$6069 - attribute \src "libresoc.v:137350.7-137350.26" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_dcache_en$next[0:0]$6117 + attribute \src "libresoc.v:138986.7-138986.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_icache_en$next[0:0]$6070 - attribute \src "libresoc.v:137355.7-137355.26" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_icache_en$next[0:0]$6118 + attribute \src "libresoc.v:138991.7-138991.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:138375.3-138395.6" - wire $1\wb_sram_en$next[0:0]$6071 - attribute \src "libresoc.v:137360.7-137360.24" + attribute \src "libresoc.v:140009.3-140029.6" + wire $1\wb_sram_en$next[0:0]$6119 + attribute \src "libresoc.v:138996.7-138996.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6045 - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $2\dmi0__din$next[63:0]$6058 - attribute \src "libresoc.v:137930.3-137946.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5982 - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5986 - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6063 - attribute \src "libresoc.v:137986.3-138002.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5997 - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$6001 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $2\fsm_state$503$next[2:0]$6051 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $2\fsm_state$next[2:0]$6028 - attribute \src "libresoc.v:138424.3-138444.6" - wire width 154 $2\io_bd$next[153:0]$6083 - attribute \src "libresoc.v:138406.3-138423.6" - wire width 154 $2\io_sr$next[153:0]$6079 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$6022 - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$6035 - attribute \src "libresoc.v:137818.3-137834.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5952 - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5956 - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6040 - attribute \src "libresoc.v:137874.3-137890.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5967 - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5971 - attribute \src "libresoc.v:137762.3-137778.6" - wire $2\sr0__oe$next[0:0]$5937 - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $2\sr0_reg$next[2:0]$5941 - attribute \src "libresoc.v:138042.3-138058.6" - wire $2\sr5__oe$next[0:0]$6012 - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $2\sr5_reg$next[2:0]$6016 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_dcache_en$next[0:0]$6072 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_icache_en$next[0:0]$6073 - attribute \src "libresoc.v:138375.3-138395.6" - wire $2\wb_sram_en$next[0:0]$6074 - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6046 - attribute \src "libresoc.v:138327.3-138353.6" - wire width 64 $3\dmi0__din$next[63:0]$6059 - attribute \src "libresoc.v:137947.3-137967.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5987 - attribute \src "libresoc.v:138354.3-138374.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6064 - attribute \src "libresoc.v:138003.3-138023.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$6002 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $3\fsm_state$503$next[2:0]$6052 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $3\fsm_state$next[2:0]$6029 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$6023 - attribute \src "libresoc.v:138193.3-138219.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$6036 - attribute \src "libresoc.v:137835.3-137855.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5957 - attribute \src "libresoc.v:138220.3-138240.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6041 - attribute \src "libresoc.v:137891.3-137911.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5972 - attribute \src "libresoc.v:137779.3-137799.6" - wire width 3 $3\sr0_reg$next[2:0]$5942 - attribute \src "libresoc.v:138059.3-138079.6" - wire width 3 $3\sr5_reg$next[2:0]$6017 - attribute \src "libresoc.v:138241.3-138273.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6047 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $4\fsm_state$503$next[2:0]$6053 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $4\fsm_state$next[2:0]$6030 - attribute \src "libresoc.v:138107.3-138139.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$6024 - attribute \src "libresoc.v:138274.3-138326.6" - wire width 3 $5\fsm_state$503$next[2:0]$6054 - attribute \src "libresoc.v:138140.3-138192.6" - wire width 3 $5\fsm_state$next[2:0]$6031 - attribute \src "libresoc.v:137583.19-137583.112" - wire width 30 $add$libresoc.v:137583$5852_Y - attribute \src "libresoc.v:137585.19-137585.112" - wire width 30 $add$libresoc.v:137585$5854_Y - attribute \src "libresoc.v:137591.19-137591.112" - wire width 5 $add$libresoc.v:137591$5861_Y - attribute \src "libresoc.v:137592.19-137592.112" - wire width 5 $add$libresoc.v:137592$5862_Y - attribute \src "libresoc.v:137407.18-137407.112" - wire $and$libresoc.v:137407$5676_Y - attribute \src "libresoc.v:137474.18-137474.108" - wire $and$libresoc.v:137474$5743_Y - attribute \src "libresoc.v:137485.18-137485.110" - wire $and$libresoc.v:137485$5754_Y - attribute \src "libresoc.v:137513.19-137513.110" - wire $and$libresoc.v:137513$5782_Y - attribute \src "libresoc.v:137516.19-137516.114" - wire $and$libresoc.v:137516$5785_Y - attribute \src "libresoc.v:137519.19-137519.112" - wire $and$libresoc.v:137519$5788_Y - attribute \src "libresoc.v:137521.19-137521.113" - wire $and$libresoc.v:137521$5790_Y - attribute \src "libresoc.v:137523.19-137523.121" - wire $and$libresoc.v:137523$5792_Y - attribute \src "libresoc.v:137526.19-137526.114" - wire $and$libresoc.v:137526$5795_Y - attribute \src "libresoc.v:137528.19-137528.112" - wire $and$libresoc.v:137528$5797_Y - attribute \src "libresoc.v:137532.19-137532.113" - wire $and$libresoc.v:137532$5801_Y - attribute \src "libresoc.v:137534.19-137534.132" - wire $and$libresoc.v:137534$5803_Y - attribute \src "libresoc.v:137538.19-137538.114" - wire $and$libresoc.v:137538$5807_Y - attribute \src "libresoc.v:137540.19-137540.112" - wire $and$libresoc.v:137540$5809_Y - attribute \src "libresoc.v:137543.19-137543.113" - wire $and$libresoc.v:137543$5812_Y - attribute \src "libresoc.v:137545.19-137545.132" - wire $and$libresoc.v:137545$5814_Y - attribute \src "libresoc.v:137548.19-137548.114" - wire $and$libresoc.v:137548$5817_Y - attribute \src "libresoc.v:137550.19-137550.112" - wire $and$libresoc.v:137550$5819_Y - attribute \src "libresoc.v:137552.18-137552.108" - wire $and$libresoc.v:137552$5821_Y - attribute \src "libresoc.v:137553.19-137553.113" - wire $and$libresoc.v:137553$5822_Y - attribute \src "libresoc.v:137555.19-137555.129" - wire $and$libresoc.v:137555$5824_Y - attribute \src "libresoc.v:137559.19-137559.114" - wire $and$libresoc.v:137559$5828_Y - attribute \src "libresoc.v:137561.19-137561.112" - wire $and$libresoc.v:137561$5830_Y - attribute \src "libresoc.v:137563.18-137563.111" - wire $and$libresoc.v:137563$5832_Y - attribute \src "libresoc.v:137564.19-137564.113" - wire $and$libresoc.v:137564$5833_Y - attribute \src "libresoc.v:137566.19-137566.129" - wire $and$libresoc.v:137566$5835_Y - attribute \src "libresoc.v:137569.19-137569.114" - wire $and$libresoc.v:137569$5838_Y - attribute \src "libresoc.v:137571.19-137571.112" - wire $and$libresoc.v:137571$5840_Y - attribute \src "libresoc.v:137573.19-137573.113" - wire $and$libresoc.v:137573$5842_Y - attribute \src "libresoc.v:137576.19-137576.121" - wire $and$libresoc.v:137576$5845_Y - attribute \src "libresoc.v:137608.17-137608.106" - wire $and$libresoc.v:137608$5878_Y - attribute \src "libresoc.v:137363.17-137363.110" - wire $eq$libresoc.v:137363$5632_Y - attribute \src "libresoc.v:137374.18-137374.111" - wire $eq$libresoc.v:137374$5643_Y - attribute \src "libresoc.v:137385.18-137385.111" - wire $eq$libresoc.v:137385$5654_Y - attribute \src "libresoc.v:137418.17-137418.110" - wire $eq$libresoc.v:137418$5687_Y - attribute \src "libresoc.v:137419.18-137419.111" - wire $eq$libresoc.v:137419$5688_Y - attribute \src "libresoc.v:137430.18-137430.111" - wire $eq$libresoc.v:137430$5699_Y - attribute \src "libresoc.v:137452.18-137452.111" - wire $eq$libresoc.v:137452$5721_Y - attribute \src "libresoc.v:137496.18-137496.111" - wire $eq$libresoc.v:137496$5765_Y - attribute \src "libresoc.v:137507.18-137507.111" - wire $eq$libresoc.v:137507$5776_Y - attribute \src "libresoc.v:137508.19-137508.112" - wire $eq$libresoc.v:137508$5777_Y - attribute \src "libresoc.v:137509.19-137509.112" - wire $eq$libresoc.v:137509$5778_Y - attribute \src "libresoc.v:137511.19-137511.112" - wire $eq$libresoc.v:137511$5780_Y - attribute \src "libresoc.v:137514.19-137514.112" - wire $eq$libresoc.v:137514$5783_Y - attribute \src "libresoc.v:137524.19-137524.112" - wire $eq$libresoc.v:137524$5793_Y - attribute \src "libresoc.v:137529.17-137529.110" - wire $eq$libresoc.v:137529$5798_Y - attribute \src "libresoc.v:137530.18-137530.111" - wire $eq$libresoc.v:137530$5799_Y - attribute \src "libresoc.v:137535.19-137535.112" - wire $eq$libresoc.v:137535$5804_Y - attribute \src "libresoc.v:137536.19-137536.112" - wire $eq$libresoc.v:137536$5805_Y - attribute \src "libresoc.v:137546.19-137546.112" - wire $eq$libresoc.v:137546$5815_Y - attribute \src "libresoc.v:137556.19-137556.112" - wire $eq$libresoc.v:137556$5825_Y - attribute \src "libresoc.v:137557.19-137557.112" - wire $eq$libresoc.v:137557$5826_Y - attribute \src "libresoc.v:137567.19-137567.112" - wire $eq$libresoc.v:137567$5836_Y - attribute \src "libresoc.v:137574.18-137574.111" - wire $eq$libresoc.v:137574$5843_Y - attribute \src "libresoc.v:137577.19-137577.110" - wire $eq$libresoc.v:137577$5846_Y - attribute \src "libresoc.v:137579.19-137579.110" - wire $eq$libresoc.v:137579$5848_Y - attribute \src "libresoc.v:137580.19-137580.110" - wire $eq$libresoc.v:137580$5849_Y - attribute \src "libresoc.v:137582.19-137582.110" - wire $eq$libresoc.v:137582$5851_Y - attribute \src "libresoc.v:137584.18-137584.111" - wire $eq$libresoc.v:137584$5853_Y - attribute \src "libresoc.v:137587.19-137587.116" - wire $eq$libresoc.v:137587$5857_Y - attribute \src "libresoc.v:137588.19-137588.116" - wire $eq$libresoc.v:137588$5858_Y - attribute \src "libresoc.v:137590.19-137590.116" - wire $eq$libresoc.v:137590$5860_Y - attribute \src "libresoc.v:137586.19-137586.106" - wire width 8 $extend$libresoc.v:137586$5855_Y - attribute \src "libresoc.v:137515.19-137515.109" - wire $ne$libresoc.v:137515$5784_Y - attribute \src "libresoc.v:137517.19-137517.109" - wire $ne$libresoc.v:137517$5786_Y - attribute \src "libresoc.v:137520.19-137520.109" - wire $ne$libresoc.v:137520$5789_Y - attribute \src "libresoc.v:137525.19-137525.120" - wire $ne$libresoc.v:137525$5794_Y - attribute \src "libresoc.v:137527.19-137527.120" - wire $ne$libresoc.v:137527$5796_Y - attribute \src "libresoc.v:137531.19-137531.120" - wire $ne$libresoc.v:137531$5800_Y - attribute \src "libresoc.v:137537.19-137537.120" - wire $ne$libresoc.v:137537$5806_Y - attribute \src "libresoc.v:137539.19-137539.120" - wire $ne$libresoc.v:137539$5808_Y - attribute \src "libresoc.v:137542.19-137542.120" - wire $ne$libresoc.v:137542$5811_Y - attribute \src "libresoc.v:137547.19-137547.117" - wire $ne$libresoc.v:137547$5816_Y - attribute \src "libresoc.v:137549.19-137549.117" - wire $ne$libresoc.v:137549$5818_Y - attribute \src "libresoc.v:137551.19-137551.117" - wire $ne$libresoc.v:137551$5820_Y - attribute \src "libresoc.v:137558.19-137558.117" - wire $ne$libresoc.v:137558$5827_Y - attribute \src "libresoc.v:137560.19-137560.117" - wire $ne$libresoc.v:137560$5829_Y - attribute \src "libresoc.v:137562.19-137562.117" - wire $ne$libresoc.v:137562$5831_Y - attribute \src "libresoc.v:137568.19-137568.109" - wire $ne$libresoc.v:137568$5837_Y - attribute \src "libresoc.v:137570.19-137570.109" - wire $ne$libresoc.v:137570$5839_Y - attribute \src "libresoc.v:137572.19-137572.109" - wire $ne$libresoc.v:137572$5841_Y - attribute \src "libresoc.v:137522.19-137522.110" - wire $not$libresoc.v:137522$5791_Y - attribute \src "libresoc.v:137533.19-137533.121" - wire $not$libresoc.v:137533$5802_Y - attribute \src "libresoc.v:137544.19-137544.121" - wire $not$libresoc.v:137544$5813_Y - attribute \src "libresoc.v:137554.19-137554.118" - wire $not$libresoc.v:137554$5823_Y - attribute \src "libresoc.v:137565.19-137565.118" - wire $not$libresoc.v:137565$5834_Y - attribute \src "libresoc.v:137575.19-137575.110" - wire $not$libresoc.v:137575$5844_Y - attribute \src "libresoc.v:137578.19-137578.100" - wire $not$libresoc.v:137578$5847_Y - attribute \src "libresoc.v:137396.18-137396.104" - wire $or$libresoc.v:137396$5665_Y - attribute \src "libresoc.v:137441.18-137441.104" - wire $or$libresoc.v:137441$5710_Y - attribute \src "libresoc.v:137463.18-137463.104" - wire $or$libresoc.v:137463$5732_Y - attribute \src "libresoc.v:137510.19-137510.107" - wire $or$libresoc.v:137510$5779_Y - attribute \src "libresoc.v:137512.19-137512.107" - wire $or$libresoc.v:137512$5781_Y - attribute \src "libresoc.v:137518.18-137518.104" - wire $or$libresoc.v:137518$5787_Y - attribute \src "libresoc.v:137541.18-137541.104" - wire $or$libresoc.v:137541$5810_Y - attribute \src "libresoc.v:137581.19-137581.107" - wire $or$libresoc.v:137581$5850_Y - attribute \src "libresoc.v:137589.19-137589.107" - wire $or$libresoc.v:137589$5859_Y - attribute \src "libresoc.v:137597.17-137597.101" - wire $or$libresoc.v:137597$5867_Y - attribute \src "libresoc.v:137586.19-137586.106" - wire width 8 $pos$libresoc.v:137586$5856_Y - attribute \src "libresoc.v:137364.18-137364.133" - wire $ternary$libresoc.v:137364$5633_Y - attribute \src "libresoc.v:137365.19-137365.133" - wire $ternary$libresoc.v:137365$5634_Y - attribute \src "libresoc.v:137366.19-137366.134" - wire $ternary$libresoc.v:137366$5635_Y - attribute \src "libresoc.v:137367.19-137367.133" - wire $ternary$libresoc.v:137367$5636_Y - attribute \src "libresoc.v:137368.19-137368.132" - wire $ternary$libresoc.v:137368$5637_Y - attribute \src "libresoc.v:137369.19-137369.133" - wire $ternary$libresoc.v:137369$5638_Y - attribute \src "libresoc.v:137370.19-137370.133" - wire $ternary$libresoc.v:137370$5639_Y - attribute \src "libresoc.v:137371.19-137371.132" - wire $ternary$libresoc.v:137371$5640_Y - attribute \src "libresoc.v:137372.19-137372.133" - wire $ternary$libresoc.v:137372$5641_Y - attribute \src "libresoc.v:137373.19-137373.133" - wire $ternary$libresoc.v:137373$5642_Y - attribute \src "libresoc.v:137375.19-137375.132" - wire $ternary$libresoc.v:137375$5644_Y - attribute \src "libresoc.v:137376.19-137376.133" - wire $ternary$libresoc.v:137376$5645_Y - attribute \src "libresoc.v:137377.19-137377.133" - wire $ternary$libresoc.v:137377$5646_Y - attribute \src "libresoc.v:137378.19-137378.132" - wire $ternary$libresoc.v:137378$5647_Y - attribute \src "libresoc.v:137379.19-137379.133" - wire $ternary$libresoc.v:137379$5648_Y - attribute \src "libresoc.v:137380.19-137380.133" - wire $ternary$libresoc.v:137380$5649_Y - attribute \src "libresoc.v:137381.19-137381.132" - wire $ternary$libresoc.v:137381$5650_Y - attribute \src "libresoc.v:137382.19-137382.133" - wire $ternary$libresoc.v:137382$5651_Y - attribute \src "libresoc.v:137383.19-137383.133" - wire $ternary$libresoc.v:137383$5652_Y - attribute \src "libresoc.v:137384.19-137384.132" - wire $ternary$libresoc.v:137384$5653_Y - attribute \src "libresoc.v:137386.19-137386.133" - wire $ternary$libresoc.v:137386$5655_Y - attribute \src "libresoc.v:137387.19-137387.133" - wire $ternary$libresoc.v:137387$5656_Y - attribute \src "libresoc.v:137388.19-137388.132" - wire $ternary$libresoc.v:137388$5657_Y - attribute \src "libresoc.v:137389.19-137389.133" - wire $ternary$libresoc.v:137389$5658_Y - attribute \src "libresoc.v:137390.19-137390.133" - wire $ternary$libresoc.v:137390$5659_Y - attribute \src "libresoc.v:137391.19-137391.132" - wire $ternary$libresoc.v:137391$5660_Y - attribute \src "libresoc.v:137392.19-137392.133" - wire $ternary$libresoc.v:137392$5661_Y - attribute \src "libresoc.v:137393.19-137393.134" - wire $ternary$libresoc.v:137393$5662_Y - attribute \src "libresoc.v:137394.19-137394.135" - wire $ternary$libresoc.v:137394$5663_Y - attribute \src "libresoc.v:137395.19-137395.135" - wire $ternary$libresoc.v:137395$5664_Y - attribute \src "libresoc.v:137397.19-137397.136" - wire $ternary$libresoc.v:137397$5666_Y - attribute \src "libresoc.v:137398.19-137398.134" - wire $ternary$libresoc.v:137398$5667_Y - attribute \src "libresoc.v:137399.19-137399.135" - wire $ternary$libresoc.v:137399$5668_Y - attribute \src "libresoc.v:137400.19-137400.135" - wire $ternary$libresoc.v:137400$5669_Y - attribute \src "libresoc.v:137401.19-137401.136" - wire $ternary$libresoc.v:137401$5670_Y - attribute \src "libresoc.v:137402.19-137402.134" - wire $ternary$libresoc.v:137402$5671_Y - attribute \src "libresoc.v:137403.19-137403.133" - wire $ternary$libresoc.v:137403$5672_Y - attribute \src "libresoc.v:137404.19-137404.134" - wire $ternary$libresoc.v:137404$5673_Y - attribute \src "libresoc.v:137405.19-137405.133" - wire $ternary$libresoc.v:137405$5674_Y - attribute \src "libresoc.v:137406.19-137406.130" - wire $ternary$libresoc.v:137406$5675_Y - attribute \src "libresoc.v:137408.19-137408.130" - wire $ternary$libresoc.v:137408$5677_Y - attribute \src "libresoc.v:137409.19-137409.133" - wire $ternary$libresoc.v:137409$5678_Y - attribute \src "libresoc.v:137410.19-137410.132" - wire $ternary$libresoc.v:137410$5679_Y - attribute \src "libresoc.v:137411.19-137411.133" - wire $ternary$libresoc.v:137411$5680_Y - attribute \src "libresoc.v:137412.19-137412.132" - wire $ternary$libresoc.v:137412$5681_Y - attribute \src "libresoc.v:137413.19-137413.135" - wire $ternary$libresoc.v:137413$5682_Y - attribute \src "libresoc.v:137414.19-137414.134" - wire $ternary$libresoc.v:137414$5683_Y - attribute \src "libresoc.v:137415.19-137415.135" - wire $ternary$libresoc.v:137415$5684_Y - attribute \src "libresoc.v:137416.19-137416.135" - wire $ternary$libresoc.v:137416$5685_Y - attribute \src "libresoc.v:137417.19-137417.134" - wire $ternary$libresoc.v:137417$5686_Y - attribute \src "libresoc.v:137420.19-137420.135" - wire $ternary$libresoc.v:137420$5689_Y - attribute \src "libresoc.v:137421.19-137421.135" - wire $ternary$libresoc.v:137421$5690_Y - attribute \src "libresoc.v:137422.19-137422.134" - wire $ternary$libresoc.v:137422$5691_Y - attribute \src "libresoc.v:137423.19-137423.135" - wire $ternary$libresoc.v:137423$5692_Y - attribute \src "libresoc.v:137424.19-137424.135" - wire $ternary$libresoc.v:137424$5693_Y - attribute \src "libresoc.v:137425.19-137425.134" - wire $ternary$libresoc.v:137425$5694_Y - attribute \src "libresoc.v:137426.19-137426.135" - wire $ternary$libresoc.v:137426$5695_Y - attribute \src "libresoc.v:137427.19-137427.133" - wire $ternary$libresoc.v:137427$5696_Y - attribute \src "libresoc.v:137428.19-137428.134" - wire $ternary$libresoc.v:137428$5697_Y - attribute \src "libresoc.v:137429.19-137429.133" - wire $ternary$libresoc.v:137429$5698_Y - attribute \src "libresoc.v:137431.19-137431.134" - wire $ternary$libresoc.v:137431$5700_Y - attribute \src "libresoc.v:137432.19-137432.134" - wire $ternary$libresoc.v:137432$5701_Y - attribute \src "libresoc.v:137433.19-137433.133" - wire $ternary$libresoc.v:137433$5702_Y - attribute \src "libresoc.v:137434.19-137434.134" - wire $ternary$libresoc.v:137434$5703_Y - attribute \src "libresoc.v:137435.19-137435.134" - wire $ternary$libresoc.v:137435$5704_Y - attribute \src "libresoc.v:137436.19-137436.133" - wire $ternary$libresoc.v:137436$5705_Y - attribute \src "libresoc.v:137437.19-137437.134" - wire $ternary$libresoc.v:137437$5706_Y - attribute \src "libresoc.v:137438.19-137438.134" - wire $ternary$libresoc.v:137438$5707_Y - attribute \src "libresoc.v:137439.19-137439.133" - wire $ternary$libresoc.v:137439$5708_Y - attribute \src "libresoc.v:137440.19-137440.134" - wire $ternary$libresoc.v:137440$5709_Y - attribute \src "libresoc.v:137442.19-137442.134" - wire $ternary$libresoc.v:137442$5711_Y - attribute \src "libresoc.v:137443.19-137443.133" - wire $ternary$libresoc.v:137443$5712_Y - attribute \src "libresoc.v:137444.19-137444.134" - wire $ternary$libresoc.v:137444$5713_Y - attribute \src "libresoc.v:137445.19-137445.134" - wire $ternary$libresoc.v:137445$5714_Y - attribute \src "libresoc.v:137446.19-137446.133" - wire $ternary$libresoc.v:137446$5715_Y - attribute \src "libresoc.v:137447.19-137447.134" - wire $ternary$libresoc.v:137447$5716_Y - attribute \src "libresoc.v:137448.19-137448.135" - wire $ternary$libresoc.v:137448$5717_Y - attribute \src "libresoc.v:137449.19-137449.134" - wire $ternary$libresoc.v:137449$5718_Y - attribute \src "libresoc.v:137450.19-137450.135" - wire $ternary$libresoc.v:137450$5719_Y - attribute \src "libresoc.v:137451.19-137451.135" - wire $ternary$libresoc.v:137451$5720_Y - attribute \src "libresoc.v:137453.19-137453.134" - wire $ternary$libresoc.v:137453$5722_Y - attribute \src "libresoc.v:137454.19-137454.135" - wire $ternary$libresoc.v:137454$5723_Y - attribute \src "libresoc.v:137455.19-137455.133" - wire $ternary$libresoc.v:137455$5724_Y - attribute \src "libresoc.v:137456.19-137456.133" - wire $ternary$libresoc.v:137456$5725_Y - attribute \src "libresoc.v:137457.19-137457.133" - wire $ternary$libresoc.v:137457$5726_Y - attribute \src "libresoc.v:137458.19-137458.133" - wire $ternary$libresoc.v:137458$5727_Y - attribute \src "libresoc.v:137459.19-137459.133" - wire $ternary$libresoc.v:137459$5728_Y - attribute \src "libresoc.v:137460.19-137460.133" - wire $ternary$libresoc.v:137460$5729_Y - attribute \src "libresoc.v:137461.19-137461.133" - wire $ternary$libresoc.v:137461$5730_Y - attribute \src "libresoc.v:137462.19-137462.133" - wire $ternary$libresoc.v:137462$5731_Y - attribute \src "libresoc.v:137464.19-137464.133" - wire $ternary$libresoc.v:137464$5733_Y - attribute \src "libresoc.v:137465.19-137465.133" - wire $ternary$libresoc.v:137465$5734_Y - attribute \src "libresoc.v:137466.19-137466.134" - wire $ternary$libresoc.v:137466$5735_Y - attribute \src "libresoc.v:137467.19-137467.134" - wire $ternary$libresoc.v:137467$5736_Y - attribute \src "libresoc.v:137468.19-137468.135" - wire $ternary$libresoc.v:137468$5737_Y - attribute \src "libresoc.v:137469.19-137469.133" - wire $ternary$libresoc.v:137469$5738_Y - attribute \src "libresoc.v:137470.19-137470.135" - wire $ternary$libresoc.v:137470$5739_Y - attribute \src "libresoc.v:137471.19-137471.135" - wire $ternary$libresoc.v:137471$5740_Y - attribute \src "libresoc.v:137472.19-137472.134" - wire $ternary$libresoc.v:137472$5741_Y - attribute \src "libresoc.v:137473.19-137473.134" - wire $ternary$libresoc.v:137473$5742_Y - attribute \src "libresoc.v:137475.19-137475.134" - wire $ternary$libresoc.v:137475$5744_Y - attribute \src "libresoc.v:137476.19-137476.134" - wire $ternary$libresoc.v:137476$5745_Y - attribute \src "libresoc.v:137477.19-137477.134" - wire $ternary$libresoc.v:137477$5746_Y - attribute \src "libresoc.v:137478.19-137478.135" - wire $ternary$libresoc.v:137478$5747_Y - attribute \src "libresoc.v:137479.19-137479.134" - wire $ternary$libresoc.v:137479$5748_Y - attribute \src "libresoc.v:137480.19-137480.135" - wire $ternary$libresoc.v:137480$5749_Y - attribute \src "libresoc.v:137481.19-137481.135" - wire $ternary$libresoc.v:137481$5750_Y - attribute \src "libresoc.v:137482.19-137482.134" - wire $ternary$libresoc.v:137482$5751_Y - attribute \src "libresoc.v:137483.19-137483.135" - wire $ternary$libresoc.v:137483$5752_Y - attribute \src "libresoc.v:137484.19-137484.135" - wire $ternary$libresoc.v:137484$5753_Y - attribute \src "libresoc.v:137486.19-137486.134" - wire $ternary$libresoc.v:137486$5755_Y - attribute \src "libresoc.v:137487.19-137487.135" - wire $ternary$libresoc.v:137487$5756_Y - attribute \src "libresoc.v:137488.19-137488.136" - wire $ternary$libresoc.v:137488$5757_Y - attribute \src "libresoc.v:137489.19-137489.135" - wire $ternary$libresoc.v:137489$5758_Y - attribute \src "libresoc.v:137490.19-137490.136" - wire $ternary$libresoc.v:137490$5759_Y - attribute \src "libresoc.v:137491.19-137491.136" - wire $ternary$libresoc.v:137491$5760_Y - attribute \src "libresoc.v:137492.19-137492.135" - wire $ternary$libresoc.v:137492$5761_Y - attribute \src "libresoc.v:137493.19-137493.136" - wire $ternary$libresoc.v:137493$5762_Y - attribute \src "libresoc.v:137494.19-137494.136" - wire $ternary$libresoc.v:137494$5763_Y - attribute \src "libresoc.v:137495.19-137495.135" - wire $ternary$libresoc.v:137495$5764_Y - attribute \src "libresoc.v:137497.19-137497.136" - wire $ternary$libresoc.v:137497$5766_Y - attribute \src "libresoc.v:137498.19-137498.136" - wire $ternary$libresoc.v:137498$5767_Y - attribute \src "libresoc.v:137499.19-137499.135" - wire $ternary$libresoc.v:137499$5768_Y - attribute \src "libresoc.v:137500.19-137500.136" - wire $ternary$libresoc.v:137500$5769_Y - attribute \src "libresoc.v:137501.19-137501.136" - wire $ternary$libresoc.v:137501$5770_Y - attribute \src "libresoc.v:137502.19-137502.135" - wire $ternary$libresoc.v:137502$5771_Y - attribute \src "libresoc.v:137503.19-137503.136" - wire $ternary$libresoc.v:137503$5772_Y - attribute \src "libresoc.v:137504.19-137504.136" - wire $ternary$libresoc.v:137504$5773_Y - attribute \src "libresoc.v:137505.19-137505.135" - wire $ternary$libresoc.v:137505$5774_Y - attribute \src "libresoc.v:137506.19-137506.136" - wire $ternary$libresoc.v:137506$5775_Y - attribute \src "libresoc.v:137593.18-137593.130" - wire $ternary$libresoc.v:137593$5863_Y - attribute \src "libresoc.v:137594.18-137594.130" - wire $ternary$libresoc.v:137594$5864_Y - attribute \src "libresoc.v:137595.18-137595.130" - wire $ternary$libresoc.v:137595$5865_Y - attribute \src "libresoc.v:137596.18-137596.131" - wire $ternary$libresoc.v:137596$5866_Y - attribute \src "libresoc.v:137598.18-137598.130" - wire $ternary$libresoc.v:137598$5868_Y - attribute \src "libresoc.v:137599.18-137599.131" - wire $ternary$libresoc.v:137599$5869_Y - attribute \src "libresoc.v:137600.18-137600.131" - wire $ternary$libresoc.v:137600$5870_Y - attribute \src "libresoc.v:137601.18-137601.130" - wire $ternary$libresoc.v:137601$5871_Y - attribute \src "libresoc.v:137602.18-137602.131" - wire $ternary$libresoc.v:137602$5872_Y - attribute \src "libresoc.v:137603.18-137603.132" - wire $ternary$libresoc.v:137603$5873_Y - attribute \src "libresoc.v:137604.18-137604.132" - wire $ternary$libresoc.v:137604$5874_Y - attribute \src "libresoc.v:137605.18-137605.133" - wire $ternary$libresoc.v:137605$5875_Y - attribute \src "libresoc.v:137606.18-137606.133" - wire $ternary$libresoc.v:137606$5876_Y - attribute \src "libresoc.v:137607.18-137607.132" - wire $ternary$libresoc.v:137607$5877_Y - attribute \src "libresoc.v:137609.18-137609.133" - wire $ternary$libresoc.v:137609$5879_Y - attribute \src "libresoc.v:137610.18-137610.133" - wire $ternary$libresoc.v:137610$5880_Y - attribute \src "libresoc.v:137611.18-137611.132" - wire $ternary$libresoc.v:137611$5881_Y - attribute \src "libresoc.v:137612.18-137612.133" - wire $ternary$libresoc.v:137612$5882_Y - attribute \src "libresoc.v:137613.18-137613.133" - wire $ternary$libresoc.v:137613$5883_Y - attribute \src "libresoc.v:137614.18-137614.132" - wire $ternary$libresoc.v:137614$5884_Y - attribute \src "libresoc.v:137615.18-137615.133" - wire $ternary$libresoc.v:137615$5885_Y - attribute \src "libresoc.v:137616.18-137616.133" - wire $ternary$libresoc.v:137616$5886_Y - attribute \src "libresoc.v:137617.18-137617.132" - wire $ternary$libresoc.v:137617$5887_Y - attribute \src "libresoc.v:137618.18-137618.133" - wire $ternary$libresoc.v:137618$5888_Y + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $2\dmi0__din$next[63:0]$6106 + attribute \src "libresoc.v:139564.3-139580.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "libresoc.v:139620.3-139636.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $2\fsm_state$499$next[2:0]$6099 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $2\fsm_state$next[2:0]$6076 + attribute \src "libresoc.v:140058.3-140078.6" + wire width 152 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140040.3-140057.6" + wire width 152 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "libresoc.v:139452.3-139468.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "libresoc.v:139508.3-139524.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 + attribute \src "libresoc.v:139396.3-139412.6" + wire $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $2\sr0_reg$next[2:0]$5989 + attribute \src "libresoc.v:139676.3-139692.6" + wire $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $2\sr5_reg$next[2:0]$6064 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_dcache_en$next[0:0]$6120 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_icache_en$next[0:0]$6121 + attribute \src "libresoc.v:140009.3-140029.6" + wire $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "libresoc.v:139961.3-139987.6" + wire width 64 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139581.3-139601.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139988.3-140008.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139637.3-139657.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $3\fsm_state$499$next[2:0]$6100 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $3\fsm_state$next[2:0]$6077 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "libresoc.v:139827.3-139853.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139469.3-139489.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139854.3-139874.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139525.3-139545.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139413.3-139433.6" + wire width 3 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139693.3-139713.6" + wire width 3 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139875.3-139907.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $4\fsm_state$499$next[2:0]$6101 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $4\fsm_state$next[2:0]$6078 + attribute \src "libresoc.v:139741.3-139773.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139908.3-139960.6" + wire width 3 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139774.3-139826.6" + wire width 3 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139217.19-139217.112" + wire width 30 $add$libresoc.v:139217$5900_Y + attribute \src "libresoc.v:139218.19-139218.112" + wire width 30 $add$libresoc.v:139218$5901_Y + attribute \src "libresoc.v:139225.19-139225.112" + wire width 5 $add$libresoc.v:139225$5909_Y + attribute \src "libresoc.v:139226.19-139226.112" + wire width 5 $add$libresoc.v:139226$5910_Y + attribute \src "libresoc.v:139043.18-139043.112" + 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$and$libresoc.v:139168$5851_Y + attribute \src "libresoc.v:139172.19-139172.114" + wire $and$libresoc.v:139172$5855_Y + attribute \src "libresoc.v:139174.19-139174.112" + wire $and$libresoc.v:139174$5857_Y + attribute \src "libresoc.v:139176.19-139176.113" + wire $and$libresoc.v:139176$5859_Y + attribute \src "libresoc.v:139179.19-139179.132" + wire $and$libresoc.v:139179$5862_Y + attribute \src "libresoc.v:139182.19-139182.114" + wire $and$libresoc.v:139182$5865_Y + attribute \src "libresoc.v:139184.19-139184.112" + wire $and$libresoc.v:139184$5867_Y + attribute \src "libresoc.v:139186.19-139186.113" + wire $and$libresoc.v:139186$5869_Y + attribute \src "libresoc.v:139188.18-139188.108" + wire $and$libresoc.v:139188$5871_Y + attribute \src "libresoc.v:139189.19-139189.129" + wire $and$libresoc.v:139189$5872_Y + attribute \src "libresoc.v:139193.19-139193.114" + wire $and$libresoc.v:139193$5876_Y + attribute \src "libresoc.v:139195.19-139195.112" + wire $and$libresoc.v:139195$5878_Y + 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$eq$libresoc.v:139165$5848_Y + attribute \src "libresoc.v:139166.18-139166.111" + wire $eq$libresoc.v:139166$5849_Y + attribute \src "libresoc.v:139169.19-139169.112" + wire $eq$libresoc.v:139169$5852_Y + attribute \src "libresoc.v:139170.19-139170.112" + wire $eq$libresoc.v:139170$5853_Y + attribute \src "libresoc.v:139180.19-139180.112" + wire $eq$libresoc.v:139180$5863_Y + attribute \src "libresoc.v:139190.19-139190.112" + wire $eq$libresoc.v:139190$5873_Y + attribute \src "libresoc.v:139191.19-139191.112" + wire $eq$libresoc.v:139191$5874_Y + attribute \src "libresoc.v:139201.19-139201.112" + wire $eq$libresoc.v:139201$5884_Y + attribute \src "libresoc.v:139210.18-139210.111" + wire $eq$libresoc.v:139210$5893_Y + attribute \src "libresoc.v:139211.19-139211.110" + wire $eq$libresoc.v:139211$5894_Y + attribute \src "libresoc.v:139213.19-139213.110" + wire $eq$libresoc.v:139213$5896_Y + attribute \src "libresoc.v:139214.19-139214.110" + wire $eq$libresoc.v:139214$5897_Y + attribute \src "libresoc.v:139216.19-139216.110" + wire $eq$libresoc.v:139216$5899_Y + attribute \src "libresoc.v:139220.18-139220.111" + wire $eq$libresoc.v:139220$5904_Y + attribute \src "libresoc.v:139221.19-139221.116" + wire $eq$libresoc.v:139221$5905_Y + attribute \src "libresoc.v:139222.19-139222.116" + wire $eq$libresoc.v:139222$5906_Y + attribute \src "libresoc.v:139224.19-139224.116" + wire $eq$libresoc.v:139224$5908_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $extend$libresoc.v:139219$5902_Y + attribute \src "libresoc.v:139149.19-139149.109" + wire $ne$libresoc.v:139149$5832_Y + attribute \src "libresoc.v:139151.19-139151.109" + wire $ne$libresoc.v:139151$5834_Y + attribute \src "libresoc.v:139153.19-139153.109" + wire $ne$libresoc.v:139153$5836_Y + attribute \src "libresoc.v:139159.19-139159.120" + wire $ne$libresoc.v:139159$5842_Y + attribute \src "libresoc.v:139161.19-139161.120" + wire $ne$libresoc.v:139161$5844_Y + attribute \src "libresoc.v:139163.19-139163.120" + wire $ne$libresoc.v:139163$5846_Y + attribute \src "libresoc.v:139171.19-139171.120" + wire $ne$libresoc.v:139171$5854_Y + attribute \src "libresoc.v:139173.19-139173.120" + wire $ne$libresoc.v:139173$5856_Y + attribute \src "libresoc.v:139175.19-139175.120" + wire $ne$libresoc.v:139175$5858_Y + attribute \src "libresoc.v:139181.19-139181.117" + wire $ne$libresoc.v:139181$5864_Y + attribute \src "libresoc.v:139183.19-139183.117" + wire $ne$libresoc.v:139183$5866_Y + attribute \src "libresoc.v:139185.19-139185.117" + wire $ne$libresoc.v:139185$5868_Y + attribute \src "libresoc.v:139192.19-139192.117" + wire $ne$libresoc.v:139192$5875_Y + attribute \src "libresoc.v:139194.19-139194.117" + wire $ne$libresoc.v:139194$5877_Y + attribute \src "libresoc.v:139196.19-139196.117" + wire $ne$libresoc.v:139196$5879_Y + attribute \src "libresoc.v:139202.19-139202.109" + wire $ne$libresoc.v:139202$5885_Y + attribute \src "libresoc.v:139204.19-139204.109" + wire $ne$libresoc.v:139204$5887_Y + attribute \src "libresoc.v:139206.19-139206.109" + wire $ne$libresoc.v:139206$5889_Y + attribute \src "libresoc.v:139156.19-139156.110" + wire $not$libresoc.v:139156$5839_Y + attribute \src "libresoc.v:139167.19-139167.121" + wire $not$libresoc.v:139167$5850_Y + attribute \src "libresoc.v:139178.19-139178.121" + wire $not$libresoc.v:139178$5861_Y + attribute \src "libresoc.v:139187.19-139187.118" + wire $not$libresoc.v:139187$5870_Y + attribute \src "libresoc.v:139198.19-139198.118" + wire $not$libresoc.v:139198$5881_Y + attribute \src "libresoc.v:139208.19-139208.110" + wire $not$libresoc.v:139208$5891_Y + attribute \src "libresoc.v:139212.19-139212.100" + wire $not$libresoc.v:139212$5895_Y + attribute \src "libresoc.v:139032.18-139032.104" + wire $or$libresoc.v:139032$5715_Y + attribute \src "libresoc.v:139077.18-139077.104" + wire $or$libresoc.v:139077$5760_Y + attribute \src "libresoc.v:139099.18-139099.104" + wire $or$libresoc.v:139099$5782_Y + attribute \src "libresoc.v:139144.19-139144.107" + wire $or$libresoc.v:139144$5827_Y + attribute \src "libresoc.v:139146.19-139146.107" + wire $or$libresoc.v:139146$5829_Y + attribute \src "libresoc.v:139154.18-139154.104" + wire $or$libresoc.v:139154$5837_Y + attribute \src "libresoc.v:139177.18-139177.104" + wire $or$libresoc.v:139177$5860_Y + attribute \src "libresoc.v:139215.19-139215.107" + wire $or$libresoc.v:139215$5898_Y + attribute \src "libresoc.v:139223.19-139223.107" + wire $or$libresoc.v:139223$5907_Y + attribute \src "libresoc.v:139231.17-139231.101" + wire $or$libresoc.v:139231$5915_Y + attribute \src "libresoc.v:139219.19-139219.106" + wire width 8 $pos$libresoc.v:139219$5903_Y + attribute \src "libresoc.v:139000.18-139000.133" + wire $ternary$libresoc.v:139000$5683_Y + attribute \src "libresoc.v:139001.19-139001.133" + wire $ternary$libresoc.v:139001$5684_Y + attribute \src "libresoc.v:139002.19-139002.134" + wire $ternary$libresoc.v:139002$5685_Y + attribute \src "libresoc.v:139003.19-139003.133" + wire $ternary$libresoc.v:139003$5686_Y + attribute \src "libresoc.v:139004.19-139004.132" + wire $ternary$libresoc.v:139004$5687_Y + attribute \src "libresoc.v:139005.19-139005.133" + wire $ternary$libresoc.v:139005$5688_Y + attribute \src "libresoc.v:139006.19-139006.133" + wire $ternary$libresoc.v:139006$5689_Y + attribute \src "libresoc.v:139007.19-139007.132" + wire $ternary$libresoc.v:139007$5690_Y + attribute \src "libresoc.v:139008.19-139008.133" + wire $ternary$libresoc.v:139008$5691_Y + attribute \src "libresoc.v:139009.19-139009.133" + wire $ternary$libresoc.v:139009$5692_Y + attribute \src "libresoc.v:139011.19-139011.132" + wire $ternary$libresoc.v:139011$5694_Y + attribute \src "libresoc.v:139012.19-139012.133" + wire $ternary$libresoc.v:139012$5695_Y + attribute \src "libresoc.v:139013.19-139013.133" + wire $ternary$libresoc.v:139013$5696_Y + attribute \src "libresoc.v:139014.19-139014.132" + wire $ternary$libresoc.v:139014$5697_Y + attribute \src "libresoc.v:139015.19-139015.133" + wire $ternary$libresoc.v:139015$5698_Y + attribute \src "libresoc.v:139016.19-139016.133" + wire $ternary$libresoc.v:139016$5699_Y + attribute \src "libresoc.v:139017.19-139017.132" + wire $ternary$libresoc.v:139017$5700_Y + attribute \src "libresoc.v:139018.19-139018.133" + wire $ternary$libresoc.v:139018$5701_Y + attribute \src "libresoc.v:139019.19-139019.133" + wire $ternary$libresoc.v:139019$5702_Y + attribute \src "libresoc.v:139020.19-139020.132" + wire $ternary$libresoc.v:139020$5703_Y + attribute \src "libresoc.v:139022.19-139022.133" + wire $ternary$libresoc.v:139022$5705_Y + attribute \src "libresoc.v:139023.19-139023.133" + wire $ternary$libresoc.v:139023$5706_Y + attribute \src "libresoc.v:139024.19-139024.132" + wire $ternary$libresoc.v:139024$5707_Y + attribute \src "libresoc.v:139025.19-139025.133" + wire $ternary$libresoc.v:139025$5708_Y + attribute \src "libresoc.v:139026.19-139026.133" + wire $ternary$libresoc.v:139026$5709_Y + attribute \src "libresoc.v:139027.19-139027.132" + wire $ternary$libresoc.v:139027$5710_Y + attribute \src "libresoc.v:139028.19-139028.133" + wire $ternary$libresoc.v:139028$5711_Y + attribute \src "libresoc.v:139029.19-139029.134" + wire $ternary$libresoc.v:139029$5712_Y + attribute \src "libresoc.v:139030.19-139030.135" + wire $ternary$libresoc.v:139030$5713_Y + attribute \src "libresoc.v:139031.19-139031.135" + wire $ternary$libresoc.v:139031$5714_Y + attribute \src "libresoc.v:139033.19-139033.136" + wire $ternary$libresoc.v:139033$5716_Y + attribute \src "libresoc.v:139034.19-139034.134" + wire $ternary$libresoc.v:139034$5717_Y + attribute \src "libresoc.v:139035.19-139035.135" + wire $ternary$libresoc.v:139035$5718_Y + attribute \src "libresoc.v:139036.19-139036.135" + wire $ternary$libresoc.v:139036$5719_Y + attribute \src "libresoc.v:139037.19-139037.136" + wire $ternary$libresoc.v:139037$5720_Y + attribute \src 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attribute \src "libresoc.v:139050.19-139050.134" + wire $ternary$libresoc.v:139050$5733_Y + attribute \src "libresoc.v:139051.19-139051.135" + wire $ternary$libresoc.v:139051$5734_Y + attribute \src "libresoc.v:139052.19-139052.135" + wire $ternary$libresoc.v:139052$5735_Y + attribute \src "libresoc.v:139053.19-139053.134" + wire $ternary$libresoc.v:139053$5736_Y + attribute \src "libresoc.v:139056.19-139056.135" + wire $ternary$libresoc.v:139056$5739_Y + attribute \src "libresoc.v:139057.19-139057.135" + wire $ternary$libresoc.v:139057$5740_Y + attribute \src "libresoc.v:139058.19-139058.134" + wire $ternary$libresoc.v:139058$5741_Y + attribute \src "libresoc.v:139059.19-139059.135" + wire $ternary$libresoc.v:139059$5742_Y + attribute \src "libresoc.v:139060.19-139060.135" + wire $ternary$libresoc.v:139060$5743_Y + attribute \src "libresoc.v:139061.19-139061.134" + wire $ternary$libresoc.v:139061$5744_Y + attribute \src "libresoc.v:139062.19-139062.135" + wire $ternary$libresoc.v:139062$5745_Y + attribute \src "libresoc.v:139063.19-139063.133" + wire $ternary$libresoc.v:139063$5746_Y + attribute \src "libresoc.v:139064.19-139064.134" + wire $ternary$libresoc.v:139064$5747_Y + attribute \src "libresoc.v:139065.19-139065.133" + wire $ternary$libresoc.v:139065$5748_Y + attribute \src "libresoc.v:139067.19-139067.134" + wire $ternary$libresoc.v:139067$5750_Y + attribute \src "libresoc.v:139068.19-139068.134" + wire $ternary$libresoc.v:139068$5751_Y + attribute \src "libresoc.v:139069.19-139069.133" + wire $ternary$libresoc.v:139069$5752_Y + attribute \src "libresoc.v:139070.19-139070.134" + wire $ternary$libresoc.v:139070$5753_Y + attribute \src "libresoc.v:139071.19-139071.134" + wire $ternary$libresoc.v:139071$5754_Y + attribute \src "libresoc.v:139072.19-139072.133" + wire $ternary$libresoc.v:139072$5755_Y + attribute \src "libresoc.v:139073.19-139073.134" + wire $ternary$libresoc.v:139073$5756_Y + attribute \src "libresoc.v:139074.19-139074.134" + wire $ternary$libresoc.v:139074$5757_Y + attribute \src "libresoc.v:139075.19-139075.133" + wire $ternary$libresoc.v:139075$5758_Y + attribute \src "libresoc.v:139076.19-139076.134" + wire $ternary$libresoc.v:139076$5759_Y + attribute \src "libresoc.v:139078.19-139078.134" + wire $ternary$libresoc.v:139078$5761_Y + attribute \src "libresoc.v:139079.19-139079.133" + wire $ternary$libresoc.v:139079$5762_Y + attribute \src "libresoc.v:139080.19-139080.134" + wire $ternary$libresoc.v:139080$5763_Y + attribute \src "libresoc.v:139081.19-139081.134" + wire $ternary$libresoc.v:139081$5764_Y + attribute \src "libresoc.v:139082.19-139082.133" + wire $ternary$libresoc.v:139082$5765_Y + attribute \src "libresoc.v:139083.19-139083.134" + wire $ternary$libresoc.v:139083$5766_Y + attribute \src "libresoc.v:139084.19-139084.135" + wire $ternary$libresoc.v:139084$5767_Y + attribute \src "libresoc.v:139085.19-139085.134" + wire $ternary$libresoc.v:139085$5768_Y + attribute \src "libresoc.v:139086.19-139086.135" + wire $ternary$libresoc.v:139086$5769_Y + attribute \src "libresoc.v:139087.19-139087.135" + wire $ternary$libresoc.v:139087$5770_Y + attribute \src "libresoc.v:139089.19-139089.134" + wire $ternary$libresoc.v:139089$5772_Y + attribute \src "libresoc.v:139090.19-139090.135" + wire $ternary$libresoc.v:139090$5773_Y + attribute \src "libresoc.v:139091.19-139091.133" + wire $ternary$libresoc.v:139091$5774_Y + attribute \src "libresoc.v:139092.19-139092.133" + wire $ternary$libresoc.v:139092$5775_Y + attribute \src "libresoc.v:139093.19-139093.133" + wire $ternary$libresoc.v:139093$5776_Y + attribute \src "libresoc.v:139094.19-139094.133" + wire $ternary$libresoc.v:139094$5777_Y + attribute \src "libresoc.v:139095.19-139095.133" + wire $ternary$libresoc.v:139095$5778_Y + attribute \src "libresoc.v:139096.19-139096.133" + wire $ternary$libresoc.v:139096$5779_Y + attribute \src "libresoc.v:139097.19-139097.133" + wire $ternary$libresoc.v:139097$5780_Y + attribute \src "libresoc.v:139098.19-139098.133" + wire $ternary$libresoc.v:139098$5781_Y + attribute \src "libresoc.v:139100.19-139100.133" + wire $ternary$libresoc.v:139100$5783_Y + attribute \src "libresoc.v:139101.19-139101.133" + wire $ternary$libresoc.v:139101$5784_Y + attribute \src "libresoc.v:139102.19-139102.134" + wire $ternary$libresoc.v:139102$5785_Y + attribute \src "libresoc.v:139103.19-139103.134" + wire $ternary$libresoc.v:139103$5786_Y + attribute \src "libresoc.v:139104.19-139104.135" + wire $ternary$libresoc.v:139104$5787_Y + attribute \src "libresoc.v:139105.19-139105.133" + wire $ternary$libresoc.v:139105$5788_Y + attribute \src "libresoc.v:139106.19-139106.135" + wire $ternary$libresoc.v:139106$5789_Y + attribute \src "libresoc.v:139107.19-139107.135" + wire $ternary$libresoc.v:139107$5790_Y + attribute \src "libresoc.v:139108.19-139108.134" + wire $ternary$libresoc.v:139108$5791_Y + attribute \src "libresoc.v:139109.19-139109.134" + wire $ternary$libresoc.v:139109$5792_Y + attribute \src "libresoc.v:139111.19-139111.134" + wire $ternary$libresoc.v:139111$5794_Y + attribute \src "libresoc.v:139112.19-139112.134" + wire $ternary$libresoc.v:139112$5795_Y + attribute \src "libresoc.v:139113.19-139113.134" + wire $ternary$libresoc.v:139113$5796_Y + attribute \src "libresoc.v:139114.19-139114.134" + wire $ternary$libresoc.v:139114$5797_Y + attribute \src "libresoc.v:139115.19-139115.135" + wire $ternary$libresoc.v:139115$5798_Y + attribute \src "libresoc.v:139116.19-139116.134" + wire $ternary$libresoc.v:139116$5799_Y + attribute \src "libresoc.v:139117.19-139117.135" + wire $ternary$libresoc.v:139117$5800_Y + attribute \src "libresoc.v:139118.19-139118.135" + wire $ternary$libresoc.v:139118$5801_Y + attribute \src "libresoc.v:139119.19-139119.134" + wire $ternary$libresoc.v:139119$5802_Y + attribute \src "libresoc.v:139120.19-139120.135" + wire $ternary$libresoc.v:139120$5803_Y + attribute \src "libresoc.v:139122.19-139122.136" + wire $ternary$libresoc.v:139122$5805_Y + attribute \src "libresoc.v:139123.19-139123.135" + wire $ternary$libresoc.v:139123$5806_Y + attribute \src "libresoc.v:139124.19-139124.136" + wire $ternary$libresoc.v:139124$5807_Y + attribute \src "libresoc.v:139125.19-139125.136" + wire $ternary$libresoc.v:139125$5808_Y + attribute \src "libresoc.v:139126.19-139126.135" + wire $ternary$libresoc.v:139126$5809_Y + attribute \src "libresoc.v:139127.19-139127.136" + wire $ternary$libresoc.v:139127$5810_Y + attribute \src "libresoc.v:139128.19-139128.136" + wire $ternary$libresoc.v:139128$5811_Y + attribute \src "libresoc.v:139129.19-139129.135" + wire $ternary$libresoc.v:139129$5812_Y + attribute \src "libresoc.v:139130.19-139130.136" + wire $ternary$libresoc.v:139130$5813_Y + attribute \src "libresoc.v:139131.19-139131.136" + wire $ternary$libresoc.v:139131$5814_Y + attribute \src "libresoc.v:139133.19-139133.135" + wire $ternary$libresoc.v:139133$5816_Y + attribute \src "libresoc.v:139134.19-139134.136" + wire $ternary$libresoc.v:139134$5817_Y + attribute \src "libresoc.v:139135.19-139135.136" + wire $ternary$libresoc.v:139135$5818_Y + attribute \src "libresoc.v:139136.19-139136.135" + wire $ternary$libresoc.v:139136$5819_Y + attribute \src "libresoc.v:139137.19-139137.136" + wire $ternary$libresoc.v:139137$5820_Y + attribute \src "libresoc.v:139138.19-139138.136" + wire $ternary$libresoc.v:139138$5821_Y + attribute \src "libresoc.v:139139.19-139139.135" + wire $ternary$libresoc.v:139139$5822_Y + attribute \src "libresoc.v:139140.19-139140.136" + wire $ternary$libresoc.v:139140$5823_Y + attribute \src "libresoc.v:139227.18-139227.130" + wire $ternary$libresoc.v:139227$5911_Y + attribute \src "libresoc.v:139228.18-139228.130" + wire $ternary$libresoc.v:139228$5912_Y + attribute \src "libresoc.v:139229.18-139229.130" + wire $ternary$libresoc.v:139229$5913_Y + attribute \src "libresoc.v:139230.18-139230.131" + wire $ternary$libresoc.v:139230$5914_Y + attribute \src "libresoc.v:139232.18-139232.130" + wire $ternary$libresoc.v:139232$5916_Y + attribute \src "libresoc.v:139233.18-139233.131" + wire $ternary$libresoc.v:139233$5917_Y + attribute \src "libresoc.v:139234.18-139234.131" + wire $ternary$libresoc.v:139234$5918_Y + attribute \src "libresoc.v:139235.18-139235.130" + wire $ternary$libresoc.v:139235$5919_Y + attribute \src "libresoc.v:139236.18-139236.131" + wire $ternary$libresoc.v:139236$5920_Y + attribute \src "libresoc.v:139237.18-139237.132" + wire $ternary$libresoc.v:139237$5921_Y + attribute \src "libresoc.v:139238.18-139238.132" + wire $ternary$libresoc.v:139238$5922_Y + attribute \src "libresoc.v:139239.18-139239.133" + wire $ternary$libresoc.v:139239$5923_Y + attribute \src "libresoc.v:139240.18-139240.133" + wire $ternary$libresoc.v:139240$5924_Y + attribute \src "libresoc.v:139241.18-139241.132" + wire $ternary$libresoc.v:139241$5925_Y + attribute \src "libresoc.v:139243.18-139243.133" + wire $ternary$libresoc.v:139243$5927_Y + attribute \src "libresoc.v:139244.18-139244.133" + wire $ternary$libresoc.v:139244$5928_Y + attribute \src "libresoc.v:139245.18-139245.132" + wire $ternary$libresoc.v:139245$5929_Y + attribute \src "libresoc.v:139246.18-139246.133" + wire $ternary$libresoc.v:139246$5930_Y + attribute \src "libresoc.v:139247.18-139247.133" + wire $ternary$libresoc.v:139247$5931_Y + attribute \src "libresoc.v:139248.18-139248.132" + wire $ternary$libresoc.v:139248$5932_Y + attribute \src "libresoc.v:139249.18-139249.133" + wire $ternary$libresoc.v:139249$5933_Y + attribute \src "libresoc.v:139250.18-139250.133" + wire $ternary$libresoc.v:139250$5934_Y + attribute \src "libresoc.v:139251.18-139251.132" + wire $ternary$libresoc.v:139251$5935_Y + attribute \src "libresoc.v:139252.18-139252.133" + wire $ternary$libresoc.v:139252$5936_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -216121,246 +218650,242 @@ module \jtag wire \$301 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$305 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$307 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$329 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$349 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$357 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$365 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$369 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$371 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$375 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$379 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$383 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$389 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$393 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$397 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$401 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$405 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$409 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$413 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$413 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$417 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$417 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$421 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$421 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$427 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$427 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$429 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$431 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$435 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$439 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$443 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$447 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$449 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$451 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$455 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$459 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$465 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$469 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$473 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$477 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" wire \$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$481 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$480 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" wire \$483 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$484 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 + wire \$485 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" wire \$489 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$493 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$495 + wire width 30 \$491 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$496 + wire width 30 \$492 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$498 + wire width 30 \$494 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$499 + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$497 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$501 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 + wire \$500 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$506 + wire \$502 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$508 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 + wire \$504 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$510 + wire \$506 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$512 + wire width 5 \$508 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$513 + wire width 5 \$509 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$515 + wire width 5 \$511 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$516 + wire width 5 \$512 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$53 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" @@ -216414,13 +218939,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tck + wire input 325 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 165 \TAP_bus__tdi + wire input 163 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 320 \TAP_bus__tdo + wire output 316 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 330 \TAP_bus__tms + wire input 326 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -216443,8 +218968,8 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 331 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 327 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -216520,27 +219045,27 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_0__core__i + wire output 164 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 11 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_1__core__i + wire output 165 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 12 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \eint_2__core__i + wire output 166 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 13 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503 + wire width 3 \fsm_state$499 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503$next + wire width 3 \fsm_state$499$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__core__i + wire output 173 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 21 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216548,11 +219073,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 20 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__o + wire output 174 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e10__pad__oe + wire output 175 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__core__i + wire output 176 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216560,11 +219085,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__o + wire output 177 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e11__pad__oe + wire output 178 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__core__i + wire output 179 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216572,11 +219097,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__o + wire output 180 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e12__pad__oe + wire output 181 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__core__i + wire output 182 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216584,11 +219109,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__o + wire output 183 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e13__pad__oe + wire output 184 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__core__i + wire output 185 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216596,11 +219121,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__o + wire output 186 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e14__pad__oe + wire output 187 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__core__i + wire output 188 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216608,11 +219133,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__o + wire output 189 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e15__pad__oe + wire output 190 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__core__i + wire output 167 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 15 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216620,11 +219145,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 14 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__o + wire output 168 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e8__pad__oe + wire output 169 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__core__i + wire output 170 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 18 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216632,11 +219157,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 17 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__o + wire output 171 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e9__pad__oe + wire output 172 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__core__i + wire output 191 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216644,11 +219169,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__o + wire output 192 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s0__pad__oe + wire output 193 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__core__i + wire output 194 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216656,11 +219181,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__o + wire output 195 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s1__pad__oe + wire output 196 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__core__i + wire output 197 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216668,11 +219193,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__o + wire output 198 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s2__pad__oe + wire output 199 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__core__i + wire output 200 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216680,11 +219205,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__o + wire output 201 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s3__pad__oe + wire output 202 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__core__i + wire output 203 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216692,11 +219217,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__o + wire output 204 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s4__pad__oe + wire output 205 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__core__i + wire output 206 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216704,11 +219229,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__o + wire output 207 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s5__pad__oe + wire output 208 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__core__i + wire output 209 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216716,11 +219241,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__o + wire output 210 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s6__pad__oe + wire output 211 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__core__i + wire output 212 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216728,15 +219253,15 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__o + wire output 213 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s7__pad__oe - attribute \src "libresoc.v:135928.7-135928.15" + wire output 214 \gpio_s7__pad__oe + attribute \src "libresoc.v:137576.7-137576.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd + wire width 152 \io_bd attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd$next + wire width 152 \io_bd$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" @@ -216746,31 +219271,31 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr + wire width 152 \io_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr$next + wire width 152 \io_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 327 \jtag_wb__ack + wire input 323 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 321 \jtag_wb__adr + wire width 29 output 317 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__cyc + wire output 319 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 328 \jtag_wb__dat_r + wire width 64 input 324 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 326 \jtag_wb__dat_w + wire width 64 output 322 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__sel + wire output 318 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__stb + wire output 320 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 325 \jtag_wb__we + wire output 321 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -216832,41 +219357,41 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_clk__pad__o + wire output 215 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_cs_n__pad__o + wire output 216 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi0_miso__core__i + wire output 218 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 65 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_mosi__pad__o + wire output 217 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_clk__pad__o + wire output 219 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_cs_n__pad__o + wire output 220 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mspi1_miso__core__i + wire output 222 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 68 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_mosi__pad__o + wire output 221 \mspi1_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \mtwi_scl__pad__o + wire output 226 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__core__i + wire output 223 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 71 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216874,9 +219399,9 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__o + wire output 224 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_sda__pad__oe + wire output 225 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -216888,19 +219413,19 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 74 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_0__pad__o + wire output 227 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire output 228 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_clk__pad__o + wire output 232 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__core__i + wire output 229 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216908,11 +219433,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__o + wire output 230 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_cmd__pad__oe + wire output 231 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__core__i + wire output 233 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216920,11 +219445,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__o + wire output 234 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data0__pad__oe + wire output 235 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__core__i + wire output 236 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216932,11 +219457,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__o + wire output 237 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data1__pad__oe + wire output 238 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__core__i + wire output 239 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216944,11 +219469,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__o + wire output 240 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data2__pad__oe + wire output 241 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__core__i + wire output 242 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -216956,103 +219481,95 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__o + wire output 243 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_data3__pad__oe + wire output 244 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 117 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_0__pad__o + wire output 270 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_10__pad__o + wire output 288 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_11__pad__o + wire output 289 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_12__pad__o + wire output 290 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_1__pad__o + wire output 271 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_2__pad__o + wire output 272 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 120 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_3__pad__o + wire output 273 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_4__pad__o + wire output 274 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_5__pad__o + wire output 275 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 123 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_6__pad__o + wire output 276 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_7__pad__o + wire output 277 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_8__pad__o + wire output 278 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 126 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_a_9__pad__o + wire output 279 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_0__pad__o + wire output 280 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_ba_1__pad__o + wire output 281 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_cas_n__pad__o + wire output 285 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_cke__pad__o + wire output 283 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 129 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_clock__pad__o + wire output 282 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_cs_n__pad__o + wire output 287 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__core__i + wire output 245 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__o + wire input 138 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dm_1__core__oe + wire output 291 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__core__i + wire output 246 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217060,83 +219577,83 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__o + wire output 247 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_0__pad__oe + wire output 248 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__core__i + wire output 298 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__o + wire input 146 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_10__core__oe + wire input 147 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__pad__i + wire input 145 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__o + wire output 299 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_10__pad__oe + wire output 300 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__core__i + wire output 301 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__o + wire input 149 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_11__core__oe + wire input 150 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__pad__i + wire input 148 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__o + wire output 302 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_11__pad__oe + wire output 303 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__core__i + wire output 304 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__o + wire input 152 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_12__core__oe + wire input 153 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__pad__i + wire input 151 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__o + wire output 305 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_12__pad__oe + wire output 306 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__core__i + wire output 307 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__o + wire input 155 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_13__core__oe + wire input 156 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__pad__i + wire input 154 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__o + wire output 308 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__oe + wire output 309 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__core__i + wire output 310 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__o + wire input 158 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_14__core__oe + wire input 159 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__pad__i + wire input 157 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__o + wire output 311 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_14__pad__oe + wire output 312 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__core__i + wire output 313 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__o + wire input 161 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_15__core__oe + wire input 162 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__pad__i + wire input 160 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__o + wire output 314 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_15__pad__oe + wire output 315 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__core__i + wire output 249 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217144,11 +219661,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__o + wire output 250 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_1__pad__oe + wire output 251 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__core__i + wire output 252 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217156,11 +219673,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__o + wire output 253 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_2__pad__oe + wire output 254 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__core__i + wire output 255 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217168,11 +219685,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__o + wire output 256 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_3__pad__oe + wire output 257 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__core__i + wire output 258 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217180,11 +219697,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__o + wire output 259 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_4__pad__oe + wire output 260 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__core__i + wire output 261 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217192,11 +219709,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 108 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__o + wire output 262 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_5__pad__oe + wire output 263 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__core__i + wire output 264 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217204,11 +219721,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 111 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__o + wire output 265 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_6__pad__oe + wire output 266 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__core__i + wire output 267 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -217216,41 +219733,41 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 114 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__o + wire output 268 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_7__pad__oe + wire output 269 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__core__i + wire output 292 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__o + wire input 140 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_8__core__oe + wire input 141 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__pad__i + wire input 139 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__o + wire output 293 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_8__pad__oe + wire output 294 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__core__i + wire output 295 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__o + wire input 143 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_9__core__oe + wire input 144 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__pad__i + wire input 142 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__o + wire output 296 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_9__pad__oe + wire output 297 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_ras_n__pad__o + wire output 284 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_we_n__pad__o + wire output 286 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -217322,7 +219839,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:137583$5852 + cell $add $add$libresoc.v:139217$5900 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -217330,10 +219847,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:137583$5852_Y + connect \Y $add$libresoc.v:139217$5900_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:137585$5854 + cell $add $add$libresoc.v:139218$5901 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -217341,10 +219858,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:137585$5854_Y + connect \Y $add$libresoc.v:139218$5901_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:137591$5861 + cell $add $add$libresoc.v:139225$5909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217352,10 +219869,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:137591$5861_Y + connect \Y $add$libresoc.v:139225$5909_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:137592$5862 + cell $add $add$libresoc.v:139226$5910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217363,10 +219880,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:137592$5862_Y + connect \Y $add$libresoc.v:139226$5910_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:137407$5676 + cell $and $and$libresoc.v:139043$5726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217374,10 +219891,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137407$5676_Y + connect \Y $and$libresoc.v:139043$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137474$5743 + cell $and $and$libresoc.v:139110$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217385,10 +219902,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:137474$5743_Y + connect \Y $and$libresoc.v:139110$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:137485$5754 + cell $and $and$libresoc.v:139121$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217396,307 +219913,307 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137485$5754_Y + connect \Y $and$libresoc.v:139121$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137513$5782 + cell $and $and$libresoc.v:139147$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$367 - connect \Y $and$libresoc.v:137513$5782_Y + connect \B \$363 + connect \Y $and$libresoc.v:139147$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137516$5785 + cell $and $and$libresoc.v:139150$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$373 + connect \A \$369 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137516$5785_Y + connect \Y $and$libresoc.v:139150$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137519$5788 + cell $and $and$libresoc.v:139152$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$377 + connect \A \$373 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137519$5788_Y + connect \Y $and$libresoc.v:139152$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137521$5790 + cell $and $and$libresoc.v:139155$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$381 + connect \A \$377 connect \B \_fsm_update - connect \Y $and$libresoc.v:137521$5790_Y + connect \Y $and$libresoc.v:139155$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137523$5792 + cell $and $and$libresoc.v:139157$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev - connect \B \$385 - connect \Y $and$libresoc.v:137523$5792_Y + connect \B \$381 + connect \Y $and$libresoc.v:139157$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137526$5795 + cell $and $and$libresoc.v:139160$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$391 + connect \A \$387 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137526$5795_Y + connect \Y $and$libresoc.v:139160$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137528$5797 + cell $and $and$libresoc.v:139162$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 + connect \A \$391 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137528$5797_Y + connect \Y $and$libresoc.v:139162$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137532$5801 + cell $and $and$libresoc.v:139164$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$399 + connect \A \$395 connect \B \_fsm_update - connect \Y $and$libresoc.v:137532$5801_Y + connect \Y $and$libresoc.v:139164$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137534$5803 + cell $and $and$libresoc.v:139168$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$403 - connect \Y $and$libresoc.v:137534$5803_Y + connect \B \$399 + connect \Y $and$libresoc.v:139168$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137538$5807 + cell $and $and$libresoc.v:139172$5855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$411 + connect \A \$407 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137538$5807_Y + connect \Y $and$libresoc.v:139172$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137540$5809 + cell $and $and$libresoc.v:139174$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$415 + connect \A \$411 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137540$5809_Y + connect \Y $and$libresoc.v:139174$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137543$5812 + cell $and $and$libresoc.v:139176$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$419 + connect \A \$415 connect \B \_fsm_update - connect \Y $and$libresoc.v:137543$5812_Y + connect \Y $and$libresoc.v:139176$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137545$5814 + cell $and $and$libresoc.v:139179$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev - connect \B \$423 - connect \Y $and$libresoc.v:137545$5814_Y + connect \B \$419 + connect \Y $and$libresoc.v:139179$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137548$5817 + cell $and $and$libresoc.v:139182$5865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 + connect \A \$425 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137548$5817_Y + connect \Y $and$libresoc.v:139182$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137550$5819 + cell $and $and$libresoc.v:139184$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 + connect \A \$429 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137550$5819_Y + connect \Y $and$libresoc.v:139184$5867_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:137552$5821 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139186$5869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:137552$5821_Y + connect \A \$433 + connect \B \_fsm_update + connect \Y $and$libresoc.v:139186$5869_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137553$5822 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:139188$5871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$437 - connect \B \_fsm_update - connect \Y $and$libresoc.v:137553$5822_Y + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:139188$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137555$5824 + cell $and $and$libresoc.v:139189$5872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev - connect \B \$441 - connect \Y $and$libresoc.v:137555$5824_Y + connect \B \$437 + connect \Y $and$libresoc.v:139189$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137559$5828 + cell $and $and$libresoc.v:139193$5876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$449 + connect \A \$445 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137559$5828_Y + connect \Y $and$libresoc.v:139193$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137561$5830 + cell $and $and$libresoc.v:139195$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$453 + connect \A \$449 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137561$5830_Y + connect \Y $and$libresoc.v:139195$5878_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:137563$5832 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:139197$5880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$43 + connect \A \$453 connect \B \_fsm_update - connect \Y $and$libresoc.v:137563$5832_Y + connect \Y $and$libresoc.v:139197$5880_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137564$5833 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:139199$5882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$457 + connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:137564$5833_Y + connect \Y $and$libresoc.v:139199$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137566$5835 + cell $and $and$libresoc.v:139200$5883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev - connect \B \$461 - connect \Y $and$libresoc.v:137566$5835_Y + connect \B \$457 + connect \Y $and$libresoc.v:139200$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:137569$5838 + cell $and $and$libresoc.v:139203$5886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$467 + connect \A \$463 connect \B \_fsm_capture - connect \Y $and$libresoc.v:137569$5838_Y + connect \Y $and$libresoc.v:139203$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:137571$5840 + cell $and $and$libresoc.v:139205$5888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 + connect \A \$467 connect \B \_fsm_shift - connect \Y $and$libresoc.v:137571$5840_Y + connect \Y $and$libresoc.v:139205$5888_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:137573$5842 + cell $and $and$libresoc.v:139207$5890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$475 + connect \A \$471 connect \B \_fsm_update - connect \Y $and$libresoc.v:137573$5842_Y + connect \Y $and$libresoc.v:139207$5890_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:137576$5845 + cell $and $and$libresoc.v:139209$5892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev - connect \B \$479 - connect \Y $and$libresoc.v:137576$5845_Y + connect \B \$475 + connect \Y $and$libresoc.v:139209$5892_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:137608$5878 + cell $and $and$libresoc.v:139242$5926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -217704,10 +220221,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:137608$5878_Y + connect \Y $and$libresoc.v:139242$5926_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:137363$5632 + cell $eq $eq$libresoc.v:138999$5682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217715,10 +220232,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:137363$5632_Y + connect \Y $eq$libresoc.v:138999$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137374$5643 + cell $eq $eq$libresoc.v:139010$5693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217726,10 +220243,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137374$5643_Y + connect \Y $eq$libresoc.v:139010$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137385$5654 + cell $eq $eq$libresoc.v:139021$5704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217737,10 +220254,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137385$5654_Y + connect \Y $eq$libresoc.v:139021$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:137418$5687 + cell $eq $eq$libresoc.v:139054$5737 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217748,10 +220265,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:137418$5687_Y + connect \Y $eq$libresoc.v:139054$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137419$5688 + cell $eq $eq$libresoc.v:139055$5738 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217759,10 +220276,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137419$5688_Y + connect \Y $eq$libresoc.v:139055$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137430$5699 + cell $eq $eq$libresoc.v:139066$5749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217770,10 +220287,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137430$5699_Y + connect \Y $eq$libresoc.v:139066$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137452$5721 + cell $eq $eq$libresoc.v:139088$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217781,10 +220298,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137452$5721_Y + connect \Y $eq$libresoc.v:139088$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137496$5765 + cell $eq $eq$libresoc.v:139132$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217792,32 +220309,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137496$5765_Y + connect \Y $eq$libresoc.v:139132$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137507$5776 + cell $eq $eq$libresoc.v:139141$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:137507$5776_Y + connect \B 1'0 + connect \Y $eq$libresoc.v:139141$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137508$5777 + cell $eq $eq$libresoc.v:139142$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:137508$5777_Y + connect \B 2'10 + connect \Y $eq$libresoc.v:139142$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:137509$5778 + cell $eq $eq$libresoc.v:139143$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217825,10 +220342,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137509$5778_Y + connect \Y $eq$libresoc.v:139143$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137511$5780 + cell $eq $eq$libresoc.v:139145$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217836,10 +220353,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137511$5780_Y + connect \Y $eq$libresoc.v:139145$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137514$5783 + cell $eq $eq$libresoc.v:139148$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217847,10 +220364,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:137514$5783_Y + connect \Y $eq$libresoc.v:139148$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137524$5793 + cell $eq $eq$libresoc.v:139158$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217858,10 +220375,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:137524$5793_Y + connect \Y $eq$libresoc.v:139158$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:137529$5798 + cell $eq $eq$libresoc.v:139165$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217869,10 +220386,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:137529$5798_Y + connect \Y $eq$libresoc.v:139165$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:137530$5799 + cell $eq $eq$libresoc.v:139166$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217880,10 +220397,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:137530$5799_Y + connect \Y $eq$libresoc.v:139166$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137535$5804 + cell $eq $eq$libresoc.v:139169$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217891,10 +220408,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:137535$5804_Y + connect \Y $eq$libresoc.v:139169$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137536$5805 + cell $eq $eq$libresoc.v:139170$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217902,10 +220419,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:137536$5805_Y + connect \Y $eq$libresoc.v:139170$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137546$5815 + cell $eq $eq$libresoc.v:139180$5863 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217913,10 +220430,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:137546$5815_Y + connect \Y $eq$libresoc.v:139180$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137556$5825 + cell $eq $eq$libresoc.v:139190$5873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217924,10 +220441,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:137556$5825_Y + connect \Y $eq$libresoc.v:139190$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137557$5826 + cell $eq $eq$libresoc.v:139191$5874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217935,10 +220452,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:137557$5826_Y + connect \Y $eq$libresoc.v:139191$5874_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:137567$5836 + cell $eq $eq$libresoc.v:139201$5884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217946,10 +220463,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:137567$5836_Y + connect \Y $eq$libresoc.v:139201$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:137574$5843 + cell $eq $eq$libresoc.v:139210$5893 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -217957,10 +220474,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137574$5843_Y + connect \Y $eq$libresoc.v:139210$5893_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:137577$5846 + cell $eq $eq$libresoc.v:139211$5894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217968,10 +220485,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:137577$5846_Y + connect \Y $eq$libresoc.v:139211$5894_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:137579$5848 + cell $eq $eq$libresoc.v:139213$5896 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217979,10 +220496,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:137579$5848_Y + connect \Y $eq$libresoc.v:139213$5896_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:137580$5849 + cell $eq $eq$libresoc.v:139214$5897 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -217990,10 +220507,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:137580$5849_Y + connect \Y $eq$libresoc.v:139214$5897_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:137582$5851 + cell $eq $eq$libresoc.v:139216$5899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -218001,10 +220518,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:137582$5851_Y + connect \Y $eq$libresoc.v:139216$5899_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:137584$5853 + cell $eq $eq$libresoc.v:139220$5904 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -218012,51 +220529,51 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:137584$5853_Y + connect \Y $eq$libresoc.v:139220$5904_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:137587$5857 + cell $eq $eq$libresoc.v:139221$5905 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 1'1 - connect \Y $eq$libresoc.v:137587$5857_Y + connect \Y $eq$libresoc.v:139221$5905_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:137588$5858 + cell $eq $eq$libresoc.v:139222$5906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:137588$5858_Y + connect \Y $eq$libresoc.v:139222$5906_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:137590$5860 + cell $eq $eq$libresoc.v:139224$5908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$503 + connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:137590$5860_Y + connect \Y $eq$libresoc.v:139224$5908_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:137586$5855 + cell $pos $extend$libresoc.v:139219$5902 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:137586$5855_Y + connect \Y $extend$libresoc.v:139219$5902_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137515$5784 + cell $ne $ne$libresoc.v:139149$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218064,10 +220581,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137515$5784_Y + connect \Y $ne$libresoc.v:139149$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137517$5786 + cell $ne $ne$libresoc.v:139151$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218075,10 +220592,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137517$5786_Y + connect \Y $ne$libresoc.v:139151$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137520$5789 + cell $ne $ne$libresoc.v:139153$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218086,10 +220603,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137520$5789_Y + connect \Y $ne$libresoc.v:139153$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137525$5794 + cell $ne $ne$libresoc.v:139159$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218097,10 +220614,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137525$5794_Y + connect \Y $ne$libresoc.v:139159$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137527$5796 + cell $ne $ne$libresoc.v:139161$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218108,10 +220625,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137527$5796_Y + connect \Y $ne$libresoc.v:139161$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137531$5800 + cell $ne $ne$libresoc.v:139163$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218119,10 +220636,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137531$5800_Y + connect \Y $ne$libresoc.v:139163$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137537$5806 + cell $ne $ne$libresoc.v:139171$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218130,10 +220647,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137537$5806_Y + connect \Y $ne$libresoc.v:139171$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137539$5808 + cell $ne $ne$libresoc.v:139173$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218141,10 +220658,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137539$5808_Y + connect \Y $ne$libresoc.v:139173$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137542$5811 + cell $ne $ne$libresoc.v:139175$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218152,10 +220669,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137542$5811_Y + connect \Y $ne$libresoc.v:139175$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137547$5816 + cell $ne $ne$libresoc.v:139181$5864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218163,10 +220680,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137547$5816_Y + connect \Y $ne$libresoc.v:139181$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137549$5818 + cell $ne $ne$libresoc.v:139183$5866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218174,10 +220691,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137549$5818_Y + connect \Y $ne$libresoc.v:139183$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137551$5820 + cell $ne $ne$libresoc.v:139185$5868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218185,10 +220702,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137551$5820_Y + connect \Y $ne$libresoc.v:139185$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137558$5827 + cell $ne $ne$libresoc.v:139192$5875 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218196,10 +220713,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137558$5827_Y + connect \Y $ne$libresoc.v:139192$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137560$5829 + cell $ne $ne$libresoc.v:139194$5877 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218207,10 +220724,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137560$5829_Y + connect \Y $ne$libresoc.v:139194$5877_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137562$5831 + cell $ne $ne$libresoc.v:139196$5879 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -218218,10 +220735,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137562$5831_Y + connect \Y $ne$libresoc.v:139196$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:137568$5837 + cell $ne $ne$libresoc.v:139202$5885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218229,10 +220746,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137568$5837_Y + connect \Y $ne$libresoc.v:139202$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:137570$5839 + cell $ne $ne$libresoc.v:139204$5887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218240,10 +220757,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137570$5839_Y + connect \Y $ne$libresoc.v:139204$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:137572$5841 + cell $ne $ne$libresoc.v:139206$5889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218251,66 +220768,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:137572$5841_Y + connect \Y $ne$libresoc.v:139206$5889_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137522$5791 + cell $not $not$libresoc.v:139156$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:137522$5791_Y + connect \Y $not$libresoc.v:139156$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137533$5802 + cell $not $not$libresoc.v:139167$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:137533$5802_Y + connect \Y $not$libresoc.v:139167$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137544$5813 + cell $not $not$libresoc.v:139178$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:137544$5813_Y + connect \Y $not$libresoc.v:139178$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137554$5823 + cell $not $not$libresoc.v:139187$5870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:137554$5823_Y + connect \Y $not$libresoc.v:139187$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137565$5834 + cell $not $not$libresoc.v:139198$5881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:137565$5834_Y + connect \Y $not$libresoc.v:139198$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:137575$5844 + cell $not $not$libresoc.v:139208$5891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:137575$5844_Y + connect \Y $not$libresoc.v:139208$5891_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:137578$5847 + cell $not $not$libresoc.v:139212$5895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$484 - connect \Y $not$libresoc.v:137578$5847_Y + connect \A \$480 + connect \Y $not$libresoc.v:139212$5895_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137396$5665 + cell $or $or$libresoc.v:139032$5715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218318,10 +220835,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:137396$5665_Y + connect \Y $or$libresoc.v:139032$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137441$5710 + cell $or $or$libresoc.v:139077$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218329,10 +220846,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:137441$5710_Y + connect \Y $or$libresoc.v:139077$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137463$5732 + cell $or $or$libresoc.v:139099$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218340,32 +220857,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:137463$5732_Y + connect \Y $or$libresoc.v:139099$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137510$5779 + cell $or $or$libresoc.v:139144$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:137510$5779_Y + connect \A \$355 + connect \B \$357 + connect \Y $or$libresoc.v:139144$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137512$5781 + cell $or $or$libresoc.v:139146$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$363 - connect \B \$365 - connect \Y $or$libresoc.v:137512$5781_Y + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:139146$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:137518$5787 + cell $or $or$libresoc.v:139154$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218373,10 +220890,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:137518$5787_Y + connect \Y $or$libresoc.v:139154$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:137541$5810 + cell $or $or$libresoc.v:139177$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218384,32 +220901,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:137541$5810_Y + connect \Y $or$libresoc.v:139177$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:137581$5850 + cell $or $or$libresoc.v:139215$5898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$487 - connect \B \$489 - connect \Y $or$libresoc.v:137581$5850_Y + connect \A \$483 + connect \B \$485 + connect \Y $or$libresoc.v:139215$5898_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:137589$5859 + cell $or $or$libresoc.v:139223$5907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$504 - connect \B \$506 - connect \Y $or$libresoc.v:137589$5859_Y + connect \A \$500 + connect \B \$502 + connect \Y $or$libresoc.v:139223$5907_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:137597$5867 + cell $or $or$libresoc.v:139231$5915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -218417,1250 +220934,1234 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:137597$5867_Y + connect \Y $or$libresoc.v:139231$5915_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:137586$5856 + cell $pos $pos$libresoc.v:139219$5903 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:137586$5855_Y - connect \Y $pos$libresoc.v:137586$5856_Y + connect \A $extend$libresoc.v:139219$5902_Y + connect \Y $pos$libresoc.v:139219$5903_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137364$5633 + cell $mux $ternary$libresoc.v:139000$5683 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137364$5633_Y + connect \Y $ternary$libresoc.v:139000$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137365$5634 + cell $mux $ternary$libresoc.v:139001$5684 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137365$5634_Y + connect \Y $ternary$libresoc.v:139001$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137366$5635 + cell $mux $ternary$libresoc.v:139002$5685 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137366$5635_Y + connect \Y $ternary$libresoc.v:139002$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137367$5636 + cell $mux $ternary$libresoc.v:139003$5686 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137367$5636_Y + connect \Y $ternary$libresoc.v:139003$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137368$5637 + cell $mux $ternary$libresoc.v:139004$5687 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137368$5637_Y + connect \Y $ternary$libresoc.v:139004$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137369$5638 + cell $mux $ternary$libresoc.v:139005$5688 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137369$5638_Y + connect \Y $ternary$libresoc.v:139005$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137370$5639 + cell $mux $ternary$libresoc.v:139006$5689 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137370$5639_Y + connect \Y $ternary$libresoc.v:139006$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137371$5640 + cell $mux $ternary$libresoc.v:139007$5690 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137371$5640_Y + connect \Y $ternary$libresoc.v:139007$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137372$5641 + cell $mux $ternary$libresoc.v:139008$5691 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137372$5641_Y + connect \Y $ternary$libresoc.v:139008$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137373$5642 + cell $mux $ternary$libresoc.v:139009$5692 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137373$5642_Y + connect \Y $ternary$libresoc.v:139009$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137375$5644 + cell $mux $ternary$libresoc.v:139011$5694 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137375$5644_Y + connect \Y $ternary$libresoc.v:139011$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137376$5645 + cell $mux $ternary$libresoc.v:139012$5695 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137376$5645_Y + connect \Y $ternary$libresoc.v:139012$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137377$5646 + cell $mux $ternary$libresoc.v:139013$5696 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137377$5646_Y + connect \Y $ternary$libresoc.v:139013$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137378$5647 + cell $mux $ternary$libresoc.v:139014$5697 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137378$5647_Y + connect \Y $ternary$libresoc.v:139014$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137379$5648 + cell $mux $ternary$libresoc.v:139015$5698 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137379$5648_Y + connect \Y $ternary$libresoc.v:139015$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137380$5649 + cell $mux $ternary$libresoc.v:139016$5699 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137380$5649_Y + connect \Y $ternary$libresoc.v:139016$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137381$5650 + cell $mux $ternary$libresoc.v:139017$5700 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137381$5650_Y + connect \Y $ternary$libresoc.v:139017$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137382$5651 + cell $mux $ternary$libresoc.v:139018$5701 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137382$5651_Y + connect \Y $ternary$libresoc.v:139018$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137383$5652 + cell $mux $ternary$libresoc.v:139019$5702 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137383$5652_Y + connect \Y $ternary$libresoc.v:139019$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137384$5653 + cell $mux $ternary$libresoc.v:139020$5703 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137384$5653_Y + connect \Y $ternary$libresoc.v:139020$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137386$5655 + cell $mux $ternary$libresoc.v:139022$5705 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137386$5655_Y + connect \Y $ternary$libresoc.v:139022$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137387$5656 + cell $mux $ternary$libresoc.v:139023$5706 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137387$5656_Y + connect \Y $ternary$libresoc.v:139023$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137388$5657 + cell $mux $ternary$libresoc.v:139024$5707 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137388$5657_Y + connect \Y $ternary$libresoc.v:139024$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137389$5658 + cell $mux $ternary$libresoc.v:139025$5708 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137389$5658_Y + connect \Y $ternary$libresoc.v:139025$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137390$5659 + cell $mux $ternary$libresoc.v:139026$5709 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137390$5659_Y + connect \Y $ternary$libresoc.v:139026$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137391$5660 + cell $mux $ternary$libresoc.v:139027$5710 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137391$5660_Y + connect \Y $ternary$libresoc.v:139027$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137392$5661 + cell $mux $ternary$libresoc.v:139028$5711 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137392$5661_Y + connect \Y $ternary$libresoc.v:139028$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137393$5662 + cell $mux $ternary$libresoc.v:139029$5712 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137393$5662_Y + connect \Y $ternary$libresoc.v:139029$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137394$5663 + cell $mux $ternary$libresoc.v:139030$5713 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137394$5663_Y + connect \Y $ternary$libresoc.v:139030$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137395$5664 + cell $mux $ternary$libresoc.v:139031$5714 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137395$5664_Y + connect \Y $ternary$libresoc.v:139031$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137397$5666 + cell $mux $ternary$libresoc.v:139033$5716 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137397$5666_Y + connect \Y $ternary$libresoc.v:139033$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137398$5667 + cell $mux $ternary$libresoc.v:139034$5717 parameter \WIDTH 1 connect \A \mspi1_clk__core__o connect \B \io_bd [55] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137398$5667_Y + connect \Y $ternary$libresoc.v:139034$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137399$5668 + cell $mux $ternary$libresoc.v:139035$5718 parameter \WIDTH 1 connect \A \mspi1_cs_n__core__o connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137399$5668_Y + connect \Y $ternary$libresoc.v:139035$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137400$5669 + cell $mux $ternary$libresoc.v:139036$5719 parameter \WIDTH 1 connect \A \mspi1_mosi__core__o connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137400$5669_Y + connect \Y $ternary$libresoc.v:139036$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137401$5670 + cell $mux $ternary$libresoc.v:139037$5720 parameter \WIDTH 1 connect \A \mspi1_miso__pad__i connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137401$5670_Y + connect \Y $ternary$libresoc.v:139037$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137402$5671 + cell $mux $ternary$libresoc.v:139038$5721 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [59] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137402$5671_Y + connect \Y $ternary$libresoc.v:139038$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137403$5672 + cell $mux $ternary$libresoc.v:139039$5722 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137403$5672_Y + connect \Y $ternary$libresoc.v:139039$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137404$5673 + cell $mux $ternary$libresoc.v:139040$5723 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137404$5673_Y + connect \Y $ternary$libresoc.v:139040$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137405$5674 + cell $mux $ternary$libresoc.v:139041$5724 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137405$5674_Y + connect \Y $ternary$libresoc.v:139041$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137406$5675 + cell $mux $ternary$libresoc.v:139042$5725 parameter \WIDTH 1 connect \A \pwm_0__core__o connect \B \io_bd [63] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137406$5675_Y + connect \Y $ternary$libresoc.v:139042$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137408$5677 + cell $mux $ternary$libresoc.v:139044$5727 parameter \WIDTH 1 connect \A \pwm_1__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137408$5677_Y + connect \Y $ternary$libresoc.v:139044$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137409$5678 + cell $mux $ternary$libresoc.v:139045$5728 parameter \WIDTH 1 connect \A \sd0_cmd__pad__i connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137409$5678_Y + connect \Y $ternary$libresoc.v:139045$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137410$5679 + cell $mux $ternary$libresoc.v:139046$5729 parameter \WIDTH 1 connect \A \sd0_cmd__core__o connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137410$5679_Y + connect \Y $ternary$libresoc.v:139046$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137411$5680 + cell $mux $ternary$libresoc.v:139047$5730 parameter \WIDTH 1 connect \A \sd0_cmd__core__oe connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137411$5680_Y + connect \Y $ternary$libresoc.v:139047$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137412$5681 + cell $mux $ternary$libresoc.v:139048$5731 parameter \WIDTH 1 connect \A \sd0_clk__core__o connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137412$5681_Y + connect \Y $ternary$libresoc.v:139048$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137413$5682 + cell $mux $ternary$libresoc.v:139049$5732 parameter \WIDTH 1 connect \A \sd0_data0__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137413$5682_Y + connect \Y $ternary$libresoc.v:139049$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137414$5683 + cell $mux $ternary$libresoc.v:139050$5733 parameter \WIDTH 1 connect \A \sd0_data0__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137414$5683_Y + connect \Y $ternary$libresoc.v:139050$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137415$5684 + cell $mux $ternary$libresoc.v:139051$5734 parameter \WIDTH 1 connect \A \sd0_data0__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137415$5684_Y + connect \Y $ternary$libresoc.v:139051$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137416$5685 + cell $mux $ternary$libresoc.v:139052$5735 parameter \WIDTH 1 connect \A \sd0_data1__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137416$5685_Y + connect \Y $ternary$libresoc.v:139052$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137417$5686 + cell $mux $ternary$libresoc.v:139053$5736 parameter \WIDTH 1 connect \A \sd0_data1__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137417$5686_Y + connect \Y $ternary$libresoc.v:139053$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137420$5689 + cell $mux $ternary$libresoc.v:139056$5739 parameter \WIDTH 1 connect \A \sd0_data1__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137420$5689_Y + connect \Y $ternary$libresoc.v:139056$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137421$5690 + cell $mux $ternary$libresoc.v:139057$5740 parameter \WIDTH 1 connect \A \sd0_data2__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137421$5690_Y + connect \Y $ternary$libresoc.v:139057$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137422$5691 + cell $mux $ternary$libresoc.v:139058$5741 parameter \WIDTH 1 connect \A \sd0_data2__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137422$5691_Y + connect \Y $ternary$libresoc.v:139058$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137423$5692 + cell $mux $ternary$libresoc.v:139059$5742 parameter \WIDTH 1 connect \A \sd0_data2__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137423$5692_Y + connect \Y $ternary$libresoc.v:139059$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137424$5693 + cell $mux $ternary$libresoc.v:139060$5743 parameter \WIDTH 1 connect \A \sd0_data3__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137424$5693_Y + connect \Y $ternary$libresoc.v:139060$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137425$5694 + cell $mux $ternary$libresoc.v:139061$5744 parameter \WIDTH 1 connect \A \sd0_data3__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137425$5694_Y + connect \Y $ternary$libresoc.v:139061$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137426$5695 + cell $mux $ternary$libresoc.v:139062$5745 parameter \WIDTH 1 connect \A \sd0_data3__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137426$5695_Y + connect \Y $ternary$libresoc.v:139062$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137427$5696 + cell $mux $ternary$libresoc.v:139063$5746 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [81] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137427$5696_Y + connect \Y $ternary$libresoc.v:139063$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137428$5697 + cell $mux $ternary$libresoc.v:139064$5747 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137428$5697_Y + connect \Y $ternary$libresoc.v:139064$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137429$5698 + cell $mux $ternary$libresoc.v:139065$5748 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137429$5698_Y + connect \Y $ternary$libresoc.v:139065$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137431$5700 + cell $mux $ternary$libresoc.v:139067$5750 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137431$5700_Y + connect \Y $ternary$libresoc.v:139067$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137432$5701 + cell $mux $ternary$libresoc.v:139068$5751 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137432$5701_Y + connect \Y $ternary$libresoc.v:139068$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137433$5702 + cell $mux $ternary$libresoc.v:139069$5752 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137433$5702_Y + connect \Y $ternary$libresoc.v:139069$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137434$5703 + cell $mux $ternary$libresoc.v:139070$5753 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137434$5703_Y + connect \Y $ternary$libresoc.v:139070$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137435$5704 + cell $mux $ternary$libresoc.v:139071$5754 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137435$5704_Y + connect \Y $ternary$libresoc.v:139071$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137436$5705 + cell $mux $ternary$libresoc.v:139072$5755 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137436$5705_Y + connect \Y $ternary$libresoc.v:139072$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137437$5706 + cell $mux $ternary$libresoc.v:139073$5756 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137437$5706_Y + connect \Y $ternary$libresoc.v:139073$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137438$5707 + cell $mux $ternary$libresoc.v:139074$5757 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [91] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137438$5707_Y + connect \Y $ternary$libresoc.v:139074$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137439$5708 + cell $mux $ternary$libresoc.v:139075$5758 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137439$5708_Y + connect \Y $ternary$libresoc.v:139075$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137440$5709 + cell $mux $ternary$libresoc.v:139076$5759 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137440$5709_Y + connect \Y $ternary$libresoc.v:139076$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137442$5711 + cell $mux $ternary$libresoc.v:139078$5761 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [94] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137442$5711_Y + connect \Y $ternary$libresoc.v:139078$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137443$5712 + cell $mux $ternary$libresoc.v:139079$5762 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137443$5712_Y + connect \Y $ternary$libresoc.v:139079$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137444$5713 + cell $mux $ternary$libresoc.v:139080$5763 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137444$5713_Y + connect \Y $ternary$libresoc.v:139080$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137445$5714 + cell $mux $ternary$libresoc.v:139081$5764 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [97] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137445$5714_Y + connect \Y $ternary$libresoc.v:139081$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137446$5715 + cell $mux $ternary$libresoc.v:139082$5765 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137446$5715_Y + connect \Y $ternary$libresoc.v:139082$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137447$5716 + cell $mux $ternary$libresoc.v:139083$5766 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137447$5716_Y + connect \Y $ternary$libresoc.v:139083$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137448$5717 + cell $mux $ternary$libresoc.v:139084$5767 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [100] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137448$5717_Y + connect \Y $ternary$libresoc.v:139084$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137449$5718 + cell $mux $ternary$libresoc.v:139085$5768 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137449$5718_Y + connect \Y $ternary$libresoc.v:139085$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137450$5719 + cell $mux $ternary$libresoc.v:139086$5769 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137450$5719_Y + connect \Y $ternary$libresoc.v:139086$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137451$5720 + cell $mux $ternary$libresoc.v:139087$5770 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [103] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137451$5720_Y + connect \Y $ternary$libresoc.v:139087$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137453$5722 + cell $mux $ternary$libresoc.v:139089$5772 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137453$5722_Y + connect \Y $ternary$libresoc.v:139089$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137454$5723 + cell $mux $ternary$libresoc.v:139090$5773 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137454$5723_Y + connect \Y $ternary$libresoc.v:139090$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137455$5724 + cell $mux $ternary$libresoc.v:139091$5774 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137455$5724_Y + connect \Y $ternary$libresoc.v:139091$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137456$5725 + cell $mux $ternary$libresoc.v:139092$5775 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137456$5725_Y + connect \Y $ternary$libresoc.v:139092$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137457$5726 + cell $mux $ternary$libresoc.v:139093$5776 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137457$5726_Y + connect \Y $ternary$libresoc.v:139093$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137458$5727 + cell $mux $ternary$libresoc.v:139094$5777 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137458$5727_Y + connect \Y $ternary$libresoc.v:139094$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137459$5728 + cell $mux $ternary$libresoc.v:139095$5778 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137459$5728_Y + connect \Y $ternary$libresoc.v:139095$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137460$5729 + cell $mux $ternary$libresoc.v:139096$5779 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137460$5729_Y + connect \Y $ternary$libresoc.v:139096$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137461$5730 + cell $mux $ternary$libresoc.v:139097$5780 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137461$5730_Y + connect \Y $ternary$libresoc.v:139097$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137462$5731 + cell $mux $ternary$libresoc.v:139098$5781 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137462$5731_Y + connect \Y $ternary$libresoc.v:139098$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137464$5733 + cell $mux $ternary$libresoc.v:139100$5783 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137464$5733_Y + connect \Y $ternary$libresoc.v:139100$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137465$5734 + cell $mux $ternary$libresoc.v:139101$5784 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137465$5734_Y + connect \Y $ternary$libresoc.v:139101$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137466$5735 + cell $mux $ternary$libresoc.v:139102$5785 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137466$5735_Y + connect \Y $ternary$libresoc.v:139102$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137467$5736 + cell $mux $ternary$libresoc.v:139103$5786 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137467$5736_Y + connect \Y $ternary$libresoc.v:139103$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137468$5737 + cell $mux $ternary$libresoc.v:139104$5787 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137468$5737_Y + connect \Y $ternary$libresoc.v:139104$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137469$5738 + cell $mux $ternary$libresoc.v:139105$5788 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137469$5738_Y + connect \Y $ternary$libresoc.v:139105$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137470$5739 + cell $mux $ternary$libresoc.v:139106$5789 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137470$5739_Y + connect \Y $ternary$libresoc.v:139106$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137471$5740 + cell $mux $ternary$libresoc.v:139107$5790 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137471$5740_Y + connect \Y $ternary$libresoc.v:139107$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137472$5741 + cell $mux $ternary$libresoc.v:139108$5791 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137472$5741_Y + connect \Y $ternary$libresoc.v:139108$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137473$5742 + cell $mux $ternary$libresoc.v:139109$5792 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137473$5742_Y + connect \Y $ternary$libresoc.v:139109$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137475$5744 + cell $mux $ternary$libresoc.v:139111$5794 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137475$5744_Y + connect \Y $ternary$libresoc.v:139111$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137476$5745 + cell $mux $ternary$libresoc.v:139112$5795 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137476$5745_Y + connect \Y $ternary$libresoc.v:139112$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:137477$5746 + cell $mux $ternary$libresoc.v:139113$5796 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137477$5746_Y + connect \Y $ternary$libresoc.v:139113$5796_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137478$5747 - parameter \WIDTH 1 - connect \A \sdr_dm_1__pad__i - connect \B \io_bd [127] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137478$5747_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137479$5748 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:139114$5797 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o - connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137479$5748_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137480$5749 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__oe - connect \B \io_bd [129] + connect \B \io_bd [127] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137480$5749_Y + connect \Y $ternary$libresoc.v:139114$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137481$5750 + cell $mux $ternary$libresoc.v:139115$5798 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i - connect \B \io_bd [130] + connect \B \io_bd [128] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137481$5750_Y + connect \Y $ternary$libresoc.v:139115$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137482$5751 + cell $mux $ternary$libresoc.v:139116$5799 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o - connect \B \io_bd [131] + connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137482$5751_Y + connect \Y $ternary$libresoc.v:139116$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137483$5752 + cell $mux $ternary$libresoc.v:139117$5800 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe - connect \B \io_bd [132] + connect \B \io_bd [130] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137483$5752_Y + connect \Y $ternary$libresoc.v:139117$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137484$5753 + cell $mux $ternary$libresoc.v:139118$5801 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i - connect \B \io_bd [133] + connect \B \io_bd [131] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137484$5753_Y + connect \Y $ternary$libresoc.v:139118$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137486$5755 + cell $mux $ternary$libresoc.v:139119$5802 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o - connect \B \io_bd [134] + connect \B \io_bd [132] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137486$5755_Y + connect \Y $ternary$libresoc.v:139119$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137487$5756 + cell $mux $ternary$libresoc.v:139120$5803 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe - connect \B \io_bd [135] + connect \B \io_bd [133] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137487$5756_Y + connect \Y $ternary$libresoc.v:139120$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137488$5757 + cell $mux $ternary$libresoc.v:139122$5805 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i - connect \B \io_bd [136] + connect \B \io_bd [134] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137488$5757_Y + connect \Y $ternary$libresoc.v:139122$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137489$5758 + cell $mux $ternary$libresoc.v:139123$5806 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o - connect \B \io_bd [137] + connect \B \io_bd [135] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137489$5758_Y + connect \Y $ternary$libresoc.v:139123$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137490$5759 + cell $mux $ternary$libresoc.v:139124$5807 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe - connect \B \io_bd [138] + connect \B \io_bd [136] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137490$5759_Y + connect \Y $ternary$libresoc.v:139124$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137491$5760 + cell $mux $ternary$libresoc.v:139125$5808 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i - connect \B \io_bd [139] + connect \B \io_bd [137] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137491$5760_Y + connect \Y $ternary$libresoc.v:139125$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137492$5761 + cell $mux $ternary$libresoc.v:139126$5809 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o - connect \B \io_bd [140] + connect \B \io_bd [138] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137492$5761_Y + connect \Y $ternary$libresoc.v:139126$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137493$5762 + cell $mux $ternary$libresoc.v:139127$5810 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe - connect \B \io_bd [141] + connect \B \io_bd [139] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137493$5762_Y + connect \Y $ternary$libresoc.v:139127$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137494$5763 + cell $mux $ternary$libresoc.v:139128$5811 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i - connect \B \io_bd [142] + connect \B \io_bd [140] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137494$5763_Y + connect \Y $ternary$libresoc.v:139128$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137495$5764 + cell $mux $ternary$libresoc.v:139129$5812 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o - connect \B \io_bd [143] + connect \B \io_bd [141] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137495$5764_Y + connect \Y $ternary$libresoc.v:139129$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137497$5766 + cell $mux $ternary$libresoc.v:139130$5813 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe - connect \B \io_bd [144] + connect \B \io_bd [142] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137497$5766_Y + connect \Y $ternary$libresoc.v:139130$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137498$5767 + cell $mux $ternary$libresoc.v:139131$5814 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i - connect \B \io_bd [145] + connect \B \io_bd [143] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137498$5767_Y + connect \Y $ternary$libresoc.v:139131$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137499$5768 + cell $mux $ternary$libresoc.v:139133$5816 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o - connect \B \io_bd [146] + connect \B \io_bd [144] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137499$5768_Y + connect \Y $ternary$libresoc.v:139133$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137500$5769 + cell $mux $ternary$libresoc.v:139134$5817 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe - connect \B \io_bd [147] + connect \B \io_bd [145] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137500$5769_Y + connect \Y $ternary$libresoc.v:139134$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137501$5770 + cell $mux $ternary$libresoc.v:139135$5818 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i - connect \B \io_bd [148] + connect \B \io_bd [146] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137501$5770_Y + connect \Y $ternary$libresoc.v:139135$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137502$5771 + cell $mux $ternary$libresoc.v:139136$5819 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o - connect \B \io_bd [149] + connect \B \io_bd [147] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137502$5771_Y + connect \Y $ternary$libresoc.v:139136$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137503$5772 + cell $mux $ternary$libresoc.v:139137$5820 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe - connect \B \io_bd [150] + connect \B \io_bd [148] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137503$5772_Y + connect \Y $ternary$libresoc.v:139137$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137504$5773 + cell $mux $ternary$libresoc.v:139138$5821 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i - connect \B \io_bd [151] + connect \B \io_bd [149] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137504$5773_Y + connect \Y $ternary$libresoc.v:139138$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137505$5774 + cell $mux $ternary$libresoc.v:139139$5822 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o - connect \B \io_bd [152] + connect \B \io_bd [150] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137505$5774_Y + connect \Y $ternary$libresoc.v:139139$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137506$5775 + cell $mux $ternary$libresoc.v:139140$5823 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe - connect \B \io_bd [153] + connect \B \io_bd [151] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137506$5775_Y + connect \Y $ternary$libresoc.v:139140$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137593$5863 + cell $mux $ternary$libresoc.v:139227$5911 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137593$5863_Y + connect \Y $ternary$libresoc.v:139227$5911_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137594$5864 + cell $mux $ternary$libresoc.v:139228$5912 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137594$5864_Y + connect \Y $ternary$libresoc.v:139228$5912_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:137595$5865 + cell $mux $ternary$libresoc.v:139229$5913 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137595$5865_Y + connect \Y $ternary$libresoc.v:139229$5913_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137596$5866 + cell $mux $ternary$libresoc.v:139230$5914 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137596$5866_Y + connect \Y $ternary$libresoc.v:139230$5914_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137598$5868 + cell $mux $ternary$libresoc.v:139232$5916 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137598$5868_Y + connect \Y $ternary$libresoc.v:139232$5916_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137599$5869 + cell $mux $ternary$libresoc.v:139233$5917 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137599$5869_Y + connect \Y $ternary$libresoc.v:139233$5917_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137600$5870 + cell $mux $ternary$libresoc.v:139234$5918 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137600$5870_Y + connect \Y $ternary$libresoc.v:139234$5918_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137601$5871 + cell $mux $ternary$libresoc.v:139235$5919 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137601$5871_Y + connect \Y $ternary$libresoc.v:139235$5919_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137602$5872 + cell $mux $ternary$libresoc.v:139236$5920 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137602$5872_Y + connect \Y $ternary$libresoc.v:139236$5920_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137603$5873 + cell $mux $ternary$libresoc.v:139237$5921 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137603$5873_Y + connect \Y $ternary$libresoc.v:139237$5921_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137604$5874 + cell $mux $ternary$libresoc.v:139238$5922 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137604$5874_Y + connect \Y $ternary$libresoc.v:139238$5922_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137605$5875 + cell $mux $ternary$libresoc.v:139239$5923 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137605$5875_Y + connect \Y $ternary$libresoc.v:139239$5923_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137606$5876 + cell $mux $ternary$libresoc.v:139240$5924 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137606$5876_Y + connect \Y $ternary$libresoc.v:139240$5924_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137607$5877 + cell $mux $ternary$libresoc.v:139241$5925 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137607$5877_Y + connect \Y $ternary$libresoc.v:139241$5925_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137609$5879 + cell $mux $ternary$libresoc.v:139243$5927 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137609$5879_Y + connect \Y $ternary$libresoc.v:139243$5927_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137610$5880 + cell $mux $ternary$libresoc.v:139244$5928 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137610$5880_Y + connect \Y $ternary$libresoc.v:139244$5928_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137611$5881 + cell $mux $ternary$libresoc.v:139245$5929 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137611$5881_Y + connect \Y $ternary$libresoc.v:139245$5929_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137612$5882 + cell $mux $ternary$libresoc.v:139246$5930 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137612$5882_Y + connect \Y $ternary$libresoc.v:139246$5930_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137613$5883 + cell $mux $ternary$libresoc.v:139247$5931 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137613$5883_Y + connect \Y $ternary$libresoc.v:139247$5931_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137614$5884 + cell $mux $ternary$libresoc.v:139248$5932 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137614$5884_Y + connect \Y $ternary$libresoc.v:139248$5932_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137615$5885 + cell $mux $ternary$libresoc.v:139249$5933 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137615$5885_Y + connect \Y $ternary$libresoc.v:139249$5933_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:137616$5886 + cell $mux $ternary$libresoc.v:139250$5934 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:137616$5886_Y + connect \Y $ternary$libresoc.v:139250$5934_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:137617$5887 + cell $mux $ternary$libresoc.v:139251$5935 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137617$5887_Y + connect \Y $ternary$libresoc.v:139251$5935_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:137618$5888 + cell $mux $ternary$libresoc.v:139252$5936 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:137618$5888_Y + connect \Y $ternary$libresoc.v:139252$5936_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:137693.8-137705.4" + attribute \src "libresoc.v:139327.8-139339.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -219675,7 +222176,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:137706.12-137716.4" + attribute \src "libresoc.v:139340.12-139350.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -219688,7 +222189,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:137717.12-137727.4" + attribute \src "libresoc.v:139351.12-139361.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -219700,582 +222201,582 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:135928.7-135928.20" - process $proc$libresoc.v:135928$6084 + attribute \src "libresoc.v:137576.7-137576.20" + process $proc$libresoc.v:137576$6132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136486.13-136486.32" - process $proc$libresoc.v:136486$6085 + attribute \src "libresoc.v:138130.13-138130.32" + process $proc$libresoc.v:138130$6133 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:136491.14-136491.46" - process $proc$libresoc.v:136491$6086 + attribute \src "libresoc.v:138135.14-138135.46" + process $proc$libresoc.v:138135$6134 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:136505.7-136505.29" - process $proc$libresoc.v:136505$6087 + attribute \src "libresoc.v:138149.7-138149.29" + process $proc$libresoc.v:138149$6135 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:136513.13-136513.36" - process $proc$libresoc.v:136513$6088 + attribute \src "libresoc.v:138157.13-138157.36" + process $proc$libresoc.v:138157$6136 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:136521.7-136521.37" - process $proc$libresoc.v:136521$6089 + attribute \src "libresoc.v:138165.7-138165.37" + process $proc$libresoc.v:138165$6137 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:136525.7-136525.42" - process $proc$libresoc.v:136525$6090 + attribute \src "libresoc.v:138169.7-138169.42" + process $proc$libresoc.v:138169$6138 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:136529.14-136529.51" - process $proc$libresoc.v:136529$6091 + attribute \src "libresoc.v:138173.14-138173.51" + process $proc$libresoc.v:138173$6139 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:136535.13-136535.35" - process $proc$libresoc.v:136535$6092 + attribute \src "libresoc.v:138179.13-138179.35" + process $proc$libresoc.v:138179$6140 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:136543.14-136543.52" - process $proc$libresoc.v:136543$6093 + attribute \src "libresoc.v:138187.14-138187.52" + process $proc$libresoc.v:138187$6141 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:136551.7-136551.37" - process $proc$libresoc.v:136551$6094 + attribute \src "libresoc.v:138195.7-138195.37" + process $proc$libresoc.v:138195$6142 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:136555.7-136555.42" - process $proc$libresoc.v:136555$6095 + attribute \src "libresoc.v:138199.7-138199.42" + process $proc$libresoc.v:138199$6143 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:136571.13-136571.29" - process $proc$libresoc.v:136571$6096 + attribute \src "libresoc.v:138215.13-138215.29" + process $proc$libresoc.v:138215$6144 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:136573.13-136573.35" - process $proc$libresoc.v:136573$6097 + attribute \src "libresoc.v:138217.13-138217.35" + process $proc$libresoc.v:138217$6145 assign { } { } - assign $0\fsm_state$503[2:0]$6098 3'000 + assign $0\fsm_state$499[2:0]$6146 3'000 sync always sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$6098 + update \fsm_state$499 $0\fsm_state$499[2:0]$6146 end - attribute \src "libresoc.v:136771.15-136771.67" - process $proc$libresoc.v:136771$6099 + attribute \src "libresoc.v:138415.15-138415.66" + process $proc$libresoc.v:138415$6147 assign { } { } - assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_bd[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_bd $1\io_bd[153:0] + update \io_bd $1\io_bd[151:0] end - attribute \src "libresoc.v:136783.15-136783.67" - process $proc$libresoc.v:136783$6100 + attribute \src "libresoc.v:138427.15-138427.66" + process $proc$libresoc.v:138427$6148 assign { } { } - assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_sr[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[153:0] + update \io_sr $1\io_sr[151:0] end - attribute \src "libresoc.v:136792.14-136792.41" - process $proc$libresoc.v:136792$6101 + attribute \src "libresoc.v:138436.14-138436.41" + process $proc$libresoc.v:138436$6149 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:136801.14-136801.51" - process $proc$libresoc.v:136801$6102 + attribute \src "libresoc.v:138445.14-138445.51" + process $proc$libresoc.v:138445$6150 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:136815.7-136815.32" - process $proc$libresoc.v:136815$6103 + attribute \src "libresoc.v:138459.7-138459.32" + process $proc$libresoc.v:138459$6151 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:136823.14-136823.47" - process $proc$libresoc.v:136823$6104 + attribute \src "libresoc.v:138467.14-138467.47" + process $proc$libresoc.v:138467$6152 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:136831.7-136831.40" - process $proc$libresoc.v:136831$6105 + attribute \src "libresoc.v:138475.7-138475.40" + process $proc$libresoc.v:138475$6153 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:136835.7-136835.45" - process $proc$libresoc.v:136835$6106 + attribute \src "libresoc.v:138479.7-138479.45" + process $proc$libresoc.v:138479$6154 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:136839.14-136839.54" - process $proc$libresoc.v:136839$6107 + attribute \src "libresoc.v:138483.14-138483.54" + process $proc$libresoc.v:138483$6155 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:136845.13-136845.38" - process $proc$libresoc.v:136845$6108 + attribute \src "libresoc.v:138489.13-138489.38" + process $proc$libresoc.v:138489$6156 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:136853.14-136853.55" - process $proc$libresoc.v:136853$6109 + attribute \src "libresoc.v:138497.14-138497.55" + process $proc$libresoc.v:138497$6157 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:136861.7-136861.40" - process $proc$libresoc.v:136861$6110 + attribute \src "libresoc.v:138505.7-138505.40" + process $proc$libresoc.v:138505$6158 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:136865.7-136865.45" - process $proc$libresoc.v:136865$6111 + attribute \src "libresoc.v:138509.7-138509.45" + process $proc$libresoc.v:138509$6159 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137295.7-137295.21" - process $proc$libresoc.v:137295$6112 + attribute \src "libresoc.v:138931.7-138931.21" + process $proc$libresoc.v:138931$6160 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:137303.13-137303.27" - process $proc$libresoc.v:137303$6113 + attribute \src "libresoc.v:138939.13-138939.27" + process $proc$libresoc.v:138939$6161 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:137311.7-137311.29" - process $proc$libresoc.v:137311$6114 + attribute \src "libresoc.v:138947.7-138947.29" + process $proc$libresoc.v:138947$6162 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:137315.7-137315.34" - process $proc$libresoc.v:137315$6115 + attribute \src "libresoc.v:138951.7-138951.34" + process $proc$libresoc.v:138951$6163 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:137325.7-137325.21" - process $proc$libresoc.v:137325$6116 + attribute \src "libresoc.v:138961.7-138961.21" + process $proc$libresoc.v:138961$6164 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:137333.13-137333.27" - process $proc$libresoc.v:137333$6117 + attribute \src "libresoc.v:138969.13-138969.27" + process $proc$libresoc.v:138969$6165 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:137341.7-137341.29" - process $proc$libresoc.v:137341$6118 + attribute \src "libresoc.v:138977.7-138977.29" + process $proc$libresoc.v:138977$6166 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:137345.7-137345.34" - process $proc$libresoc.v:137345$6119 + attribute \src "libresoc.v:138981.7-138981.34" + process $proc$libresoc.v:138981$6167 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:137350.7-137350.26" - process $proc$libresoc.v:137350$6120 + attribute \src "libresoc.v:138986.7-138986.26" + process $proc$libresoc.v:138986$6168 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:137355.7-137355.26" - process $proc$libresoc.v:137355$6121 + attribute \src "libresoc.v:138991.7-138991.26" + process $proc$libresoc.v:138991$6169 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:137360.7-137360.24" - process $proc$libresoc.v:137360$6122 + attribute \src "libresoc.v:138996.7-138996.24" + process $proc$libresoc.v:138996$6170 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:137619.3-137620.41" - process $proc$libresoc.v:137619$5889 + attribute \src "libresoc.v:139253.3-139254.41" + process $proc$libresoc.v:139253$5937 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:137621.3-137622.41" - process $proc$libresoc.v:137621$5890 + attribute \src "libresoc.v:139255.3-139256.41" + process $proc$libresoc.v:139255$5938 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:137623.3-137624.37" - process $proc$libresoc.v:137623$5891 + attribute \src "libresoc.v:139257.3-139258.37" + process $proc$libresoc.v:139257$5939 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:137625.3-137626.45" - process $proc$libresoc.v:137625$5892 + attribute \src "libresoc.v:139259.3-139260.45" + process $proc$libresoc.v:139259$5940 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:137627.3-137628.35" - process $proc$libresoc.v:137627$5893 + attribute \src "libresoc.v:139261.3-139262.35" + process $proc$libresoc.v:139261$5941 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:137629.3-137630.45" - process $proc$libresoc.v:137629$5894 + attribute \src "libresoc.v:139263.3-139264.45" + process $proc$libresoc.v:139263$5942 assign { } { } - assign $0\fsm_state$503[2:0]$5895 \fsm_state$503$next + assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5895 + update \fsm_state$499 $0\fsm_state$499[2:0]$5943 end - attribute \src "libresoc.v:137631.3-137632.41" - process $proc$libresoc.v:137631$5896 + attribute \src "libresoc.v:139265.3-139266.41" + process $proc$libresoc.v:139265$5944 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:137633.3-137634.51" - process $proc$libresoc.v:137633$5897 + attribute \src "libresoc.v:139267.3-139268.51" + process $proc$libresoc.v:139267$5945 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:137635.3-137636.45" - process $proc$libresoc.v:137635$5898 + attribute \src "libresoc.v:139269.3-139270.45" + process $proc$libresoc.v:139269$5946 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:137637.3-137638.35" - process $proc$libresoc.v:137637$5899 + attribute \src "libresoc.v:139271.3-139272.35" + process $proc$libresoc.v:139271$5947 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:137639.3-137640.41" - process $proc$libresoc.v:137639$5900 + attribute \src "libresoc.v:139273.3-139274.41" + process $proc$libresoc.v:139273$5948 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:137641.3-137642.31" - process $proc$libresoc.v:137641$5901 + attribute \src "libresoc.v:139275.3-139276.31" + process $proc$libresoc.v:139275$5949 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:137643.3-137644.31" - process $proc$libresoc.v:137643$5902 + attribute \src "libresoc.v:139277.3-139278.31" + process $proc$libresoc.v:139277$5950 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:137645.3-137646.57" - process $proc$libresoc.v:137645$5903 + attribute \src "libresoc.v:139279.3-139280.57" + process $proc$libresoc.v:139279$5951 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:137647.3-137648.47" - process $proc$libresoc.v:137647$5904 + attribute \src "libresoc.v:139281.3-139282.47" + process $proc$libresoc.v:139281$5952 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:137649.3-137650.47" - process $proc$libresoc.v:137649$5905 + attribute \src "libresoc.v:139283.3-139284.47" + process $proc$libresoc.v:139283$5953 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:137651.3-137652.47" - process $proc$libresoc.v:137651$5906 + attribute \src "libresoc.v:139285.3-139286.47" + process $proc$libresoc.v:139285$5954 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:137653.3-137654.73" - process $proc$libresoc.v:137653$5907 + attribute \src "libresoc.v:139287.3-139288.73" + process $proc$libresoc.v:139287$5955 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137655.3-137656.63" - process $proc$libresoc.v:137655$5908 + attribute \src "libresoc.v:139289.3-139290.63" + process $proc$libresoc.v:139289$5956 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:137657.3-137658.47" - process $proc$libresoc.v:137657$5909 + attribute \src "libresoc.v:139291.3-139292.47" + process $proc$libresoc.v:139291$5957 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:137659.3-137660.47" - process $proc$libresoc.v:137659$5910 + attribute \src "libresoc.v:139293.3-139294.47" + process $proc$libresoc.v:139293$5958 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:137661.3-137662.73" - process $proc$libresoc.v:137661$5911 + attribute \src "libresoc.v:139295.3-139296.73" + process $proc$libresoc.v:139295$5959 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:137663.3-137664.63" - process $proc$libresoc.v:137663$5912 + attribute \src "libresoc.v:139297.3-139298.63" + process $proc$libresoc.v:139297$5960 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:137665.3-137666.53" - process $proc$libresoc.v:137665$5913 + attribute \src "libresoc.v:139299.3-139300.53" + process $proc$libresoc.v:139299$5961 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:137667.3-137668.53" - process $proc$libresoc.v:137667$5914 + attribute \src "libresoc.v:139301.3-139302.53" + process $proc$libresoc.v:139301$5962 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:137669.3-137670.79" - process $proc$libresoc.v:137669$5915 + attribute \src "libresoc.v:139303.3-139304.79" + process $proc$libresoc.v:139303$5963 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:137671.3-137672.69" - process $proc$libresoc.v:137671$5916 + attribute \src "libresoc.v:139305.3-139306.69" + process $proc$libresoc.v:139305$5964 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:137673.3-137674.53" - process $proc$libresoc.v:137673$5917 + attribute \src "libresoc.v:139307.3-139308.53" + process $proc$libresoc.v:139307$5965 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:137675.3-137676.53" - process $proc$libresoc.v:137675$5918 + attribute \src "libresoc.v:139309.3-139310.53" + process $proc$libresoc.v:139309$5966 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:137677.3-137678.79" - process $proc$libresoc.v:137677$5919 + attribute \src "libresoc.v:139311.3-139312.79" + process $proc$libresoc.v:139311$5967 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:137679.3-137680.69" - process $proc$libresoc.v:137679$5920 + attribute \src "libresoc.v:139313.3-139314.69" + process $proc$libresoc.v:139313$5968 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:137681.3-137682.31" - process $proc$libresoc.v:137681$5921 + attribute \src "libresoc.v:139315.3-139316.31" + process $proc$libresoc.v:139315$5969 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:137683.3-137684.31" - process $proc$libresoc.v:137683$5922 + attribute \src "libresoc.v:139317.3-139318.31" + process $proc$libresoc.v:139317$5970 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:137685.3-137686.57" - process $proc$libresoc.v:137685$5923 + attribute \src "libresoc.v:139319.3-139320.57" + process $proc$libresoc.v:139319$5971 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:137687.3-137688.47" - process $proc$libresoc.v:137687$5924 + attribute \src "libresoc.v:139321.3-139322.47" + process $proc$libresoc.v:139321$5972 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:137689.3-137690.27" - process $proc$libresoc.v:137689$5925 + attribute \src "libresoc.v:139323.3-139324.27" + process $proc$libresoc.v:139323$5973 assign { } { } - assign $0\io_bd[153:0] \io_bd$next + assign $0\io_bd[151:0] \io_bd$next sync negedge \negjtag_clk - update \io_bd $0\io_bd[153:0] + update \io_bd $0\io_bd[151:0] end - attribute \src "libresoc.v:137691.3-137692.27" - process $proc$libresoc.v:137691$5926 + attribute \src "libresoc.v:139325.3-139326.27" + process $proc$libresoc.v:139325$5974 assign { } { } - assign $0\io_sr[153:0] \io_sr$next + assign $0\io_sr[151:0] \io_sr$next sync posedge \posjtag_clk - update \io_sr $0\io_sr[153:0] + update \io_sr $0\io_sr[151:0] end - attribute \src "libresoc.v:137728.3-137743.6" - process $proc$libresoc.v:137728$5927 + attribute \src "libresoc.v:139362.3-139377.6" + process $proc$libresoc.v:139362$5975 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:137729.5-137729.29" + attribute \src "libresoc.v:139363.5-139363.29" switch \initial - attribute \src "libresoc.v:137729.9-137729.17" + attribute \src "libresoc.v:139363.9-139363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$369 \_idblock_select_id \_fsm_isir } + switch { \$365 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } @@ -220287,21 +222788,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [153] + assign $1\TAP_tdo[0:0] \io_sr [151] case assign $1\TAP_tdo[0:0] 1'0 end sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:137744.3-137752.6" - process $proc$libresoc.v:137744$5928 + attribute \src "libresoc.v:139378.3-139386.6" + process $proc$libresoc.v:139378$5976 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5929 $1\sr0_update_core$next[0:0]$5930 - attribute \src "libresoc.v:137745.5-137745.29" + assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:139379.5-139379.29" switch \initial - attribute \src "libresoc.v:137745.9-137745.17" + attribute \src "libresoc.v:139379.9-139379.17" case 1'1 case end @@ -220310,21 +222811,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5930 1'0 + assign $1\sr0_update_core$next[0:0]$5978 1'0 case - assign $1\sr0_update_core$next[0:0]$5930 \sr0_update + assign $1\sr0_update_core$next[0:0]$5978 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5929 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 end - attribute \src "libresoc.v:137753.3-137761.6" - process $proc$libresoc.v:137753$5931 + attribute \src "libresoc.v:139387.3-139395.6" + process $proc$libresoc.v:139387$5979 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5932 $1\sr0_update_core_prev$next[0:0]$5933 - attribute \src "libresoc.v:137754.5-137754.29" + assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:139388.5-139388.29" switch \initial - attribute \src "libresoc.v:137754.9-137754.17" + attribute \src "libresoc.v:139388.9-139388.17" case 1'1 case end @@ -220333,57 +222834,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5933 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5933 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5932 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 end - attribute \src "libresoc.v:137762.3-137778.6" - process $proc$libresoc.v:137762$5934 + attribute \src "libresoc.v:139396.3-139412.6" + process $proc$libresoc.v:139396$5982 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5935 $2\sr0__oe$next[0:0]$5937 - attribute \src "libresoc.v:137763.5-137763.29" + assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:139397.5-139397.29" switch \initial - attribute \src "libresoc.v:137763.9-137763.17" + attribute \src "libresoc.v:139397.9-139397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$387 + switch \$383 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5936 \sr0_isir + assign $1\sr0__oe$next[0:0]$5984 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5936 1'0 + assign $1\sr0__oe$next[0:0]$5984 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5937 1'0 + assign $2\sr0__oe$next[0:0]$5985 1'0 case - assign $2\sr0__oe$next[0:0]$5937 $1\sr0__oe$next[0:0]$5936 + assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5935 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 end - attribute \src "libresoc.v:137779.3-137799.6" - process $proc$libresoc.v:137779$5938 + attribute \src "libresoc.v:139413.3-139433.6" + process $proc$libresoc.v:139413$5986 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5939 $3\sr0_reg$next[2:0]$5942 - attribute \src "libresoc.v:137780.5-137780.29" + assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:139414.5-139414.29" switch \initial - attribute \src "libresoc.v:137780.9-137780.17" + attribute \src "libresoc.v:139414.9-139414.17" case 1'1 case end @@ -220392,39 +222893,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5940 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5940 \sr0_reg + assign $1\sr0_reg$next[2:0]$5988 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5941 \sr0__i + assign $2\sr0_reg$next[2:0]$5989 \sr0__i case - assign $2\sr0_reg$next[2:0]$5941 $1\sr0_reg$next[2:0]$5940 + assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5942 3'000 + assign $3\sr0_reg$next[2:0]$5990 3'000 case - assign $3\sr0_reg$next[2:0]$5942 $2\sr0_reg$next[2:0]$5941 + assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5939 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 end - attribute \src "libresoc.v:137800.3-137808.6" - process $proc$libresoc.v:137800$5943 + attribute \src "libresoc.v:139434.3-139442.6" + process $proc$libresoc.v:139434$5991 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5944 $1\jtag_wb_addrsr_update_core$next[0:0]$5945 - attribute \src "libresoc.v:137801.5-137801.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:139435.5-139435.29" switch \initial - attribute \src "libresoc.v:137801.9-137801.17" + attribute \src "libresoc.v:139435.9-139435.17" case 1'1 case end @@ -220433,21 +222934,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5945 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5944 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 end - attribute \src "libresoc.v:137809.3-137817.6" - process $proc$libresoc.v:137809$5946 + attribute \src "libresoc.v:139443.3-139451.6" + process $proc$libresoc.v:139443$5994 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 - attribute \src "libresoc.v:137810.5-137810.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:139444.5-139444.29" switch \initial - attribute \src "libresoc.v:137810.9-137810.17" + attribute \src "libresoc.v:139444.9-139444.17" case 1'1 case end @@ -220456,57 +222957,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5948 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5947 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 end - attribute \src "libresoc.v:137818.3-137834.6" - process $proc$libresoc.v:137818$5949 + attribute \src "libresoc.v:139452.3-139468.6" + process $proc$libresoc.v:139452$5997 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5950 $2\jtag_wb_addrsr__oe$next[0:0]$5952 - attribute \src "libresoc.v:137819.5-137819.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:139453.5-139453.29" switch \initial - attribute \src "libresoc.v:137819.9-137819.17" + attribute \src "libresoc.v:139453.9-139453.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$405 + switch \$401 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5951 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5952 $1\jtag_wb_addrsr__oe$next[0:0]$5951 + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5950 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 end - attribute \src "libresoc.v:137835.3-137855.6" - process $proc$libresoc.v:137835$5953 + attribute \src "libresoc.v:139469.3-139489.6" + process $proc$libresoc.v:139469$6001 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5954 $3\jtag_wb_addrsr_reg$next[28:0]$5957 - attribute \src "libresoc.v:137836.5-137836.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:139470.5-139470.29" switch \initial - attribute \src "libresoc.v:137836.9-137836.17" + attribute \src "libresoc.v:139470.9-139470.17" case 1'1 case end @@ -220515,39 +223016,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5955 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5956 $1\jtag_wb_addrsr_reg$next[28:0]$5955 + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5957 $2\jtag_wb_addrsr_reg$next[28:0]$5956 + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5954 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 end - attribute \src "libresoc.v:137856.3-137864.6" - process $proc$libresoc.v:137856$5958 + attribute \src "libresoc.v:139490.3-139498.6" + process $proc$libresoc.v:139490$6006 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5959 $1\jtag_wb_datasr_update_core$next[0:0]$5960 - attribute \src "libresoc.v:137857.5-137857.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:139491.5-139491.29" switch \initial - attribute \src "libresoc.v:137857.9-137857.17" + attribute \src "libresoc.v:139491.9-139491.17" case 1'1 case end @@ -220556,21 +223057,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5960 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5959 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 end - attribute \src "libresoc.v:137865.3-137873.6" - process $proc$libresoc.v:137865$5961 + attribute \src "libresoc.v:139499.3-139507.6" + process $proc$libresoc.v:139499$6009 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 - attribute \src "libresoc.v:137866.5-137866.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:139500.5-139500.29" switch \initial - attribute \src "libresoc.v:137866.9-137866.17" + attribute \src "libresoc.v:139500.9-139500.17" case 1'1 case end @@ -220579,57 +223080,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5963 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5962 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 end - attribute \src "libresoc.v:137874.3-137890.6" - process $proc$libresoc.v:137874$5964 + attribute \src "libresoc.v:139508.3-139524.6" + process $proc$libresoc.v:139508$6012 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5965 $2\jtag_wb_datasr__oe$next[1:0]$5967 - attribute \src "libresoc.v:137875.5-137875.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:139509.5-139509.29" switch \initial - attribute \src "libresoc.v:137875.9-137875.17" + attribute \src "libresoc.v:139509.9-139509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$425 + switch \$421 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5966 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5966 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5967 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$5967 $1\jtag_wb_datasr__oe$next[1:0]$5966 + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5965 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 end - attribute \src "libresoc.v:137891.3-137911.6" - process $proc$libresoc.v:137891$5968 + attribute \src "libresoc.v:139525.3-139545.6" + process $proc$libresoc.v:139525$6016 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5969 $3\jtag_wb_datasr_reg$next[63:0]$5972 - attribute \src "libresoc.v:137892.5-137892.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:139526.5-139526.29" switch \initial - attribute \src "libresoc.v:137892.9-137892.17" + attribute \src "libresoc.v:139526.9-139526.17" case 1'1 case end @@ -220638,39 +223139,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5970 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$5970 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5971 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$5971 $1\jtag_wb_datasr_reg$next[63:0]$5970 + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$5972 $2\jtag_wb_datasr_reg$next[63:0]$5971 + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5969 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 end - attribute \src "libresoc.v:137912.3-137920.6" - process $proc$libresoc.v:137912$5973 + attribute \src "libresoc.v:139546.3-139554.6" + process $proc$libresoc.v:139546$6021 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5974 $1\dmi0_addrsr_update_core$next[0:0]$5975 - attribute \src "libresoc.v:137913.5-137913.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:139547.5-139547.29" switch \initial - attribute \src "libresoc.v:137913.9-137913.17" + attribute \src "libresoc.v:139547.9-139547.17" case 1'1 case end @@ -220679,21 +223180,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5975 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$5975 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5974 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 end - attribute \src "libresoc.v:137921.3-137929.6" - process $proc$libresoc.v:137921$5976 + attribute \src "libresoc.v:139555.3-139563.6" + process $proc$libresoc.v:139555$6024 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 - attribute \src "libresoc.v:137922.5-137922.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:139556.5-139556.29" switch \initial - attribute \src "libresoc.v:137922.9-137922.17" + attribute \src "libresoc.v:139556.9-139556.17" case 1'1 case end @@ -220702,57 +223203,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5978 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5977 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 end - attribute \src "libresoc.v:137930.3-137946.6" - process $proc$libresoc.v:137930$5979 + attribute \src "libresoc.v:139564.3-139580.6" + process $proc$libresoc.v:139564$6027 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5980 $2\dmi0_addrsr__oe$next[0:0]$5982 - attribute \src "libresoc.v:137931.5-137931.29" + assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:139565.5-139565.29" switch \initial - attribute \src "libresoc.v:137931.9-137931.17" + attribute \src "libresoc.v:139565.9-139565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$443 + switch \$439 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5981 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5981 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5982 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$5982 $1\dmi0_addrsr__oe$next[0:0]$5981 + assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5980 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 end - attribute \src "libresoc.v:137947.3-137967.6" - process $proc$libresoc.v:137947$5983 + attribute \src "libresoc.v:139581.3-139601.6" + process $proc$libresoc.v:139581$6031 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5984 $3\dmi0_addrsr_reg$next[7:0]$5987 - attribute \src "libresoc.v:137948.5-137948.29" + assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:139582.5-139582.29" switch \initial - attribute \src "libresoc.v:137948.9-137948.17" + attribute \src "libresoc.v:139582.9-139582.17" case 1'1 case end @@ -220761,39 +223262,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5985 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$5985 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5986 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$5986 $1\dmi0_addrsr_reg$next[7:0]$5985 + assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5987 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$5987 $2\dmi0_addrsr_reg$next[7:0]$5986 + assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5984 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 end - attribute \src "libresoc.v:137968.3-137976.6" - process $proc$libresoc.v:137968$5988 + attribute \src "libresoc.v:139602.3-139610.6" + process $proc$libresoc.v:139602$6036 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5989 $1\dmi0_datasr_update_core$next[0:0]$5990 - attribute \src "libresoc.v:137969.5-137969.29" + assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:139603.5-139603.29" switch \initial - attribute \src "libresoc.v:137969.9-137969.17" + attribute \src "libresoc.v:139603.9-139603.17" case 1'1 case end @@ -220802,21 +223303,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5990 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$5990 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5989 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 end - attribute \src "libresoc.v:137977.3-137985.6" - process $proc$libresoc.v:137977$5991 + attribute \src "libresoc.v:139611.3-139619.6" + process $proc$libresoc.v:139611$6039 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5992 $1\dmi0_datasr_update_core_prev$next[0:0]$5993 - attribute \src "libresoc.v:137978.5-137978.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:139612.5-139612.29" switch \initial - attribute \src "libresoc.v:137978.9-137978.17" + attribute \src "libresoc.v:139612.9-139612.17" case 1'1 case end @@ -220825,57 +223326,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5993 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5992 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 end - attribute \src "libresoc.v:137986.3-138002.6" - process $proc$libresoc.v:137986$5994 + attribute \src "libresoc.v:139620.3-139636.6" + process $proc$libresoc.v:139620$6042 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5995 $2\dmi0_datasr__oe$next[1:0]$5997 - attribute \src "libresoc.v:137987.5-137987.29" + assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:139621.5-139621.29" switch \initial - attribute \src "libresoc.v:137987.9-137987.17" + attribute \src "libresoc.v:139621.9-139621.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$463 + switch \$459 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5996 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5996 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5997 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$5997 $1\dmi0_datasr__oe$next[1:0]$5996 + assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5995 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 end - attribute \src "libresoc.v:138003.3-138023.6" - process $proc$libresoc.v:138003$5998 + attribute \src "libresoc.v:139637.3-139657.6" + process $proc$libresoc.v:139637$6046 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5999 $3\dmi0_datasr_reg$next[63:0]$6002 - attribute \src "libresoc.v:138004.5-138004.29" + assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:139638.5-139638.29" switch \initial - attribute \src "libresoc.v:138004.9-138004.17" + attribute \src "libresoc.v:139638.9-139638.17" case 1'1 case end @@ -220884,39 +223385,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$6000 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$6000 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$6001 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$6001 $1\dmi0_datasr_reg$next[63:0]$6000 + assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$6002 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$6002 $2\dmi0_datasr_reg$next[63:0]$6001 + assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5999 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 end - attribute \src "libresoc.v:138024.3-138032.6" - process $proc$libresoc.v:138024$6003 + attribute \src "libresoc.v:139658.3-139666.6" + process $proc$libresoc.v:139658$6051 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$6004 $1\sr5_update_core$next[0:0]$6005 - attribute \src "libresoc.v:138025.5-138025.29" + assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:139659.5-139659.29" switch \initial - attribute \src "libresoc.v:138025.9-138025.17" + attribute \src "libresoc.v:139659.9-139659.17" case 1'1 case end @@ -220925,21 +223426,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$6005 1'0 + assign $1\sr5_update_core$next[0:0]$6053 1'0 case - assign $1\sr5_update_core$next[0:0]$6005 \sr5_update + assign $1\sr5_update_core$next[0:0]$6053 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6004 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 end - attribute \src "libresoc.v:138033.3-138041.6" - process $proc$libresoc.v:138033$6006 + attribute \src "libresoc.v:139667.3-139675.6" + process $proc$libresoc.v:139667$6054 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$6007 $1\sr5_update_core_prev$next[0:0]$6008 - attribute \src "libresoc.v:138034.5-138034.29" + assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:139668.5-139668.29" switch \initial - attribute \src "libresoc.v:138034.9-138034.17" + attribute \src "libresoc.v:139668.9-139668.17" case 1'1 case end @@ -220948,57 +223449,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$6008 1'0 + assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$6008 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6007 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 end - attribute \src "libresoc.v:138042.3-138058.6" - process $proc$libresoc.v:138042$6009 + attribute \src "libresoc.v:139676.3-139692.6" + process $proc$libresoc.v:139676$6057 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$6010 $2\sr5__oe$next[0:0]$6012 - attribute \src "libresoc.v:138043.5-138043.29" + assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:139677.5-139677.29" switch \initial - attribute \src "libresoc.v:138043.9-138043.17" + attribute \src "libresoc.v:139677.9-139677.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$481 + switch \$477 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$6011 \sr5_isir + assign $1\sr5__oe$next[0:0]$6059 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$6011 1'0 + assign $1\sr5__oe$next[0:0]$6059 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$6012 1'0 + assign $2\sr5__oe$next[0:0]$6060 1'0 case - assign $2\sr5__oe$next[0:0]$6012 $1\sr5__oe$next[0:0]$6011 + assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$6010 + update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 end - attribute \src "libresoc.v:138059.3-138079.6" - process $proc$libresoc.v:138059$6013 + attribute \src "libresoc.v:139693.3-139713.6" + process $proc$libresoc.v:139693$6061 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[2:0]$6014 $3\sr5_reg$next[2:0]$6017 - attribute \src "libresoc.v:138060.5-138060.29" + assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 + attribute \src "libresoc.v:139694.5-139694.29" switch \initial - attribute \src "libresoc.v:138060.9-138060.17" + attribute \src "libresoc.v:139694.9-139694.17" case 1'1 case end @@ -221007,38 +223508,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[2:0]$6015 { \TAP_bus__tdi \sr5_reg [2:1] } + assign $1\sr5_reg$next[2:0]$6063 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[2:0]$6015 \sr5_reg + assign $1\sr5_reg$next[2:0]$6063 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[2:0]$6016 \sr5__i + assign $2\sr5_reg$next[2:0]$6064 \sr5__i case - assign $2\sr5_reg$next[2:0]$6016 $1\sr5_reg$next[2:0]$6015 + assign $2\sr5_reg$next[2:0]$6064 $1\sr5_reg$next[2:0]$6063 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[2:0]$6017 3'000 + assign $3\sr5_reg$next[2:0]$6065 3'000 case - assign $3\sr5_reg$next[2:0]$6017 $2\sr5_reg$next[2:0]$6016 + assign $3\sr5_reg$next[2:0]$6065 $2\sr5_reg$next[2:0]$6064 end sync always - update \sr5_reg$next $0\sr5_reg$next[2:0]$6014 + update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 end - attribute \src "libresoc.v:138080.3-138106.6" - process $proc$libresoc.v:138080$6018 + attribute \src "libresoc.v:139714.3-139740.6" + process $proc$libresoc.v:139714$6066 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:138081.5-138081.29" + attribute \src "libresoc.v:139715.5-139715.29" switch \initial - attribute \src "libresoc.v:138081.9-138081.17" + attribute \src "libresoc.v:139715.9-139715.17" case 1'1 case end @@ -221076,15 +223577,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:138107.3-138139.6" - process $proc$libresoc.v:138107$6019 + attribute \src "libresoc.v:139741.3-139773.6" + process $proc$libresoc.v:139741$6067 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$6020 $4\jtag_wb__adr$next[28:0]$6024 - attribute \src "libresoc.v:138108.5-138108.29" + assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:139742.5-139742.29" switch \initial - attribute \src "libresoc.v:138108.9-138108.17" + attribute \src "libresoc.v:139742.9-139742.17" case 1'1 case end @@ -221093,57 +223594,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6021 $2\jtag_wb__adr$next[28:0]$6022 + assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6022 \$495 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6070 \$491 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$6022 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6021 $3\jtag_wb__adr$next[28:0]$6023 + assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$6023 \$498 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6071 \$494 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$6023 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$6021 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$6024 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$6024 $1\jtag_wb__adr$next[28:0]$6021 + assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6020 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 end - attribute \src "libresoc.v:138140.3-138192.6" - process $proc$libresoc.v:138140$6025 + attribute \src "libresoc.v:139774.3-139826.6" + process $proc$libresoc.v:139774$6073 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$6026 $5\fsm_state$next[2:0]$6031 - attribute \src "libresoc.v:138141.5-138141.29" + assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139775.5-139775.29" switch \initial - attribute \src "libresoc.v:138141.9-138141.17" + attribute \src "libresoc.v:139775.9-139775.17" case 1'1 case end @@ -221152,82 +223653,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $2\fsm_state$next[2:0]$6028 + assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'001 + assign $2\fsm_state$next[2:0]$6076 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'001 + assign $2\fsm_state$next[2:0]$6076 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$6028 3'010 + assign $2\fsm_state$next[2:0]$6076 3'010 case - assign $2\fsm_state$next[2:0]$6028 \fsm_state + assign $2\fsm_state$next[2:0]$6076 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$6027 3'011 + assign $1\fsm_state$next[2:0]$6075 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $3\fsm_state$next[2:0]$6029 + assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$6029 3'000 + assign $3\fsm_state$next[2:0]$6077 3'000 case - assign $3\fsm_state$next[2:0]$6029 \fsm_state + assign $3\fsm_state$next[2:0]$6077 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$6027 3'100 + assign $1\fsm_state$next[2:0]$6075 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$6027 $4\fsm_state$next[2:0]$6030 + assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$6030 3'001 + assign $4\fsm_state$next[2:0]$6078 3'001 case - assign $4\fsm_state$next[2:0]$6030 \fsm_state + assign $4\fsm_state$next[2:0]$6078 \fsm_state end case - assign $1\fsm_state$next[2:0]$6027 \fsm_state + assign $1\fsm_state$next[2:0]$6075 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$6031 3'000 + assign $5\fsm_state$next[2:0]$6079 3'000 case - assign $5\fsm_state$next[2:0]$6031 $1\fsm_state$next[2:0]$6027 + assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$6026 + update \fsm_state$next $0\fsm_state$next[2:0]$6074 end - attribute \src "libresoc.v:138193.3-138219.6" - process $proc$libresoc.v:138193$6032 + attribute \src "libresoc.v:139827.3-139853.6" + process $proc$libresoc.v:139827$6080 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$6033 $3\jtag_wb__dat_w$next[63:0]$6036 - attribute \src "libresoc.v:138194.5-138194.29" + assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:139828.5-139828.29" switch \initial - attribute \src "libresoc.v:138194.9-138194.17" + attribute \src "libresoc.v:139828.9-139828.17" case 1'1 case end @@ -221236,46 +223737,46 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$6034 $2\jtag_wb__dat_w$next[63:0]$6035 + assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$6035 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$6034 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$6036 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$6036 $1\jtag_wb__dat_w$next[63:0]$6034 + assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6033 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 end - attribute \src "libresoc.v:138220.3-138240.6" - process $proc$libresoc.v:138220$6037 + attribute \src "libresoc.v:139854.3-139874.6" + process $proc$libresoc.v:139854$6085 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$6038 $3\jtag_wb_datasr__i$next[63:0]$6041 - attribute \src "libresoc.v:138221.5-138221.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:139855.5-139855.29" switch \initial - attribute \src "libresoc.v:138221.9-138221.17" + attribute \src "libresoc.v:139855.9-139855.17" case 1'1 case end @@ -221284,266 +223785,266 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$6039 $2\jtag_wb_datasr__i$next[63:0]$6040 + assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$6040 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$6039 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$6041 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$6041 $1\jtag_wb_datasr__i$next[63:0]$6039 + assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6038 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 end - attribute \src "libresoc.v:138241.3-138273.6" - process $proc$libresoc.v:138241$6042 + attribute \src "libresoc.v:139875.3-139907.6" + process $proc$libresoc.v:139875$6090 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$6043 $4\dmi0__addr_i$next[3:0]$6047 - attribute \src "libresoc.v:138242.5-138242.29" + assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:139876.5-139876.29" switch \initial - attribute \src "libresoc.v:138242.9-138242.17" + attribute \src "libresoc.v:139876.9-139876.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6044 $2\dmi0__addr_i$next[3:0]$6045 + assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6045 \$512 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6093 \$508 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$6045 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6044 $3\dmi0__addr_i$next[3:0]$6046 + assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6046 \$515 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6094 \$511 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$6046 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$6044 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6047 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$6047 $1\dmi0__addr_i$next[3:0]$6044 + assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6043 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 end - attribute \src "libresoc.v:138274.3-138326.6" - process $proc$libresoc.v:138274$6048 + attribute \src "libresoc.v:139908.3-139960.6" + process $proc$libresoc.v:139908$6096 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$6049 $5\fsm_state$503$next[2:0]$6054 - attribute \src "libresoc.v:138275.5-138275.29" + assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 + attribute \src "libresoc.v:139909.5-139909.29" switch \initial - attribute \src "libresoc.v:138275.9-138275.17" + attribute \src "libresoc.v:139909.9-139909.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $2\fsm_state$503$next[2:0]$6051 + assign $1\fsm_state$499$next[2:0]$6098 $2\fsm_state$499$next[2:0]$6099 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'001 + assign $2\fsm_state$499$next[2:0]$6099 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'001 + assign $2\fsm_state$499$next[2:0]$6099 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$503$next[2:0]$6051 3'010 + assign $2\fsm_state$499$next[2:0]$6099 3'010 case - assign $2\fsm_state$503$next[2:0]$6051 \fsm_state$503 + assign $2\fsm_state$499$next[2:0]$6099 \fsm_state$499 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 3'011 + assign $1\fsm_state$499$next[2:0]$6098 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $3\fsm_state$503$next[2:0]$6052 + assign $1\fsm_state$499$next[2:0]$6098 $3\fsm_state$499$next[2:0]$6100 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$503$next[2:0]$6052 3'000 + assign $3\fsm_state$499$next[2:0]$6100 3'000 case - assign $3\fsm_state$503$next[2:0]$6052 \fsm_state$503 + assign $3\fsm_state$499$next[2:0]$6100 \fsm_state$499 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 3'100 + assign $1\fsm_state$499$next[2:0]$6098 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$503$next[2:0]$6050 $4\fsm_state$503$next[2:0]$6053 + assign $1\fsm_state$499$next[2:0]$6098 $4\fsm_state$499$next[2:0]$6101 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$503$next[2:0]$6053 3'001 + assign $4\fsm_state$499$next[2:0]$6101 3'001 case - assign $4\fsm_state$503$next[2:0]$6053 \fsm_state$503 + assign $4\fsm_state$499$next[2:0]$6101 \fsm_state$499 end case - assign $1\fsm_state$503$next[2:0]$6050 \fsm_state$503 + assign $1\fsm_state$499$next[2:0]$6098 \fsm_state$499 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$6054 3'000 + assign $5\fsm_state$499$next[2:0]$6102 3'000 case - assign $5\fsm_state$503$next[2:0]$6054 $1\fsm_state$503$next[2:0]$6050 + assign $5\fsm_state$499$next[2:0]$6102 $1\fsm_state$499$next[2:0]$6098 end sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6049 + update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 end - attribute \src "libresoc.v:138327.3-138353.6" - process $proc$libresoc.v:138327$6055 + attribute \src "libresoc.v:139961.3-139987.6" + process $proc$libresoc.v:139961$6103 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6056 $3\dmi0__din$next[63:0]$6059 - attribute \src "libresoc.v:138328.5-138328.29" + assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:139962.5-139962.29" switch \initial - attribute \src "libresoc.v:138328.9-138328.17" + attribute \src "libresoc.v:139962.9-139962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$6057 $2\dmi0__din$next[63:0]$6058 + assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$6058 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$6058 \dmi0__din + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$6057 \dmi0__din + assign $1\dmi0__din$next[63:0]$6105 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6059 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6059 $1\dmi0__din$next[63:0]$6057 + assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6056 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 end - attribute \src "libresoc.v:138354.3-138374.6" - process $proc$libresoc.v:138354$6060 + attribute \src "libresoc.v:139988.3-140008.6" + process $proc$libresoc.v:139988$6108 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6061 $3\dmi0_datasr__i$next[63:0]$6064 - attribute \src "libresoc.v:138355.5-138355.29" + assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:139989.5-139989.29" switch \initial - attribute \src "libresoc.v:138355.9-138355.17" + attribute \src "libresoc.v:139989.9-139989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + switch \fsm_state$499 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6062 $2\dmi0_datasr__i$next[63:0]$6063 + assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$6063 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$6062 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6064 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$6064 $1\dmi0_datasr__i$next[63:0]$6062 + assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6061 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 end - attribute \src "libresoc.v:138375.3-138395.6" - process $proc$libresoc.v:138375$6065 + attribute \src "libresoc.v:140009.3-140029.6" + process $proc$libresoc.v:140009$6113 assign { } { } assign { } { } assign { } { } @@ -221553,12 +224054,12 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$6066 $2\wb_dcache_en$next[0:0]$6072 - assign $0\wb_icache_en$next[0:0]$6067 $2\wb_icache_en$next[0:0]$6073 - assign $0\wb_sram_en$next[0:0]$6068 $2\wb_sram_en$next[0:0]$6074 - attribute \src "libresoc.v:138376.5-138376.29" + assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 + assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 + assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 + attribute \src "libresoc.v:140010.5-140010.29" switch \initial - attribute \src "libresoc.v:138376.9-138376.17" + attribute \src "libresoc.v:140010.9-140010.17" case 1'1 case end @@ -221569,11 +224070,11 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign { $1\wb_sram_en$next[0:0]$6071 $1\wb_dcache_en$next[0:0]$6069 $1\wb_icache_en$next[0:0]$6070 } \sr5__o + assign { $1\wb_sram_en$next[0:0]$6119 $1\wb_dcache_en$next[0:0]$6117 $1\wb_icache_en$next[0:0]$6118 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$6069 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6070 \wb_icache_en - assign $1\wb_sram_en$next[0:0]$6071 \wb_sram_en + assign $1\wb_dcache_en$next[0:0]$6117 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6118 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6119 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -221582,27 +224083,27 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$6073 1'1 - assign $2\wb_dcache_en$next[0:0]$6072 1'1 - assign $2\wb_sram_en$next[0:0]$6074 1'1 + assign $2\wb_icache_en$next[0:0]$6121 1'1 + assign $2\wb_dcache_en$next[0:0]$6120 1'1 + assign $2\wb_sram_en$next[0:0]$6122 1'1 case - assign $2\wb_dcache_en$next[0:0]$6072 $1\wb_dcache_en$next[0:0]$6069 - assign $2\wb_icache_en$next[0:0]$6073 $1\wb_icache_en$next[0:0]$6070 - assign $2\wb_sram_en$next[0:0]$6074 $1\wb_sram_en$next[0:0]$6071 + assign $2\wb_dcache_en$next[0:0]$6120 $1\wb_dcache_en$next[0:0]$6117 + assign $2\wb_icache_en$next[0:0]$6121 $1\wb_icache_en$next[0:0]$6118 + assign $2\wb_sram_en$next[0:0]$6122 $1\wb_sram_en$next[0:0]$6119 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6066 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6067 - update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6068 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 end - attribute \src "libresoc.v:138396.3-138405.6" - process $proc$libresoc.v:138396$6075 + attribute \src "libresoc.v:140030.3-140039.6" + process $proc$libresoc.v:140030$6123 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:138397.5-138397.29" + attribute \src "libresoc.v:140031.5-140031.29" switch \initial - attribute \src "libresoc.v:138397.9-138397.17" + attribute \src "libresoc.v:140031.9-140031.17" case 1'1 case end @@ -221618,15 +224119,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:138406.3-138423.6" - process $proc$libresoc.v:138406$6076 + attribute \src "libresoc.v:140040.3-140057.6" + process $proc$libresoc.v:140040$6124 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[153:0]$6077 $2\io_sr$next[153:0]$6079 - attribute \src "libresoc.v:138407.5-138407.29" + assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 + attribute \src "libresoc.v:140041.5-140041.29" switch \initial - attribute \src "libresoc.v:138407.9-138407.17" + attribute \src "libresoc.v:140041.9-140041.17" case 1'1 case end @@ -221635,35 +224136,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[153:0]$6078 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[151:0]$6126 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[153:0]$6078 { \io_sr [152:0] \TAP_bus__tdi } + assign $1\io_sr$next[151:0]$6126 { \io_sr [150:0] \TAP_bus__tdi } case - assign $1\io_sr$next[153:0]$6078 \io_sr + assign $1\io_sr$next[151:0]$6126 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$6079 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[151:0]$6127 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[153:0]$6079 $1\io_sr$next[153:0]$6078 + assign $2\io_sr$next[151:0]$6127 $1\io_sr$next[151:0]$6126 end sync always - update \io_sr$next $0\io_sr$next[153:0]$6077 + update \io_sr$next $0\io_sr$next[151:0]$6125 end - attribute \src "libresoc.v:138424.3-138444.6" - process $proc$libresoc.v:138424$6080 + attribute \src "libresoc.v:140058.3-140078.6" + process $proc$libresoc.v:140058$6128 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[153:0]$6081 $2\io_bd$next[153:0]$6083 - attribute \src "libresoc.v:138425.5-138425.29" + assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 + attribute \src "libresoc.v:140059.5-140059.29" switch \initial - attribute \src "libresoc.v:138425.9-138425.17" + attribute \src "libresoc.v:140059.9-140059.17" case 1'1 case end @@ -221671,356 +224172,352 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[153:0]$6082 \io_sr + assign $1\io_bd$next[151:0]$6130 \io_sr case - assign $1\io_bd$next[153:0]$6082 \io_bd + assign $1\io_bd$next[151:0]$6130 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[153:0]$6083 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$6083 $1\io_bd$next[153:0]$6082 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$6081 - end - connect \$9 $eq$libresoc.v:137363$5632_Y - connect \$99 $ternary$libresoc.v:137364$5633_Y - connect \$101 $ternary$libresoc.v:137365$5634_Y - connect \$103 $ternary$libresoc.v:137366$5635_Y - connect \$105 $ternary$libresoc.v:137367$5636_Y - connect \$107 $ternary$libresoc.v:137368$5637_Y - connect \$109 $ternary$libresoc.v:137369$5638_Y - connect \$111 $ternary$libresoc.v:137370$5639_Y - connect \$113 $ternary$libresoc.v:137371$5640_Y - connect \$115 $ternary$libresoc.v:137372$5641_Y - connect \$117 $ternary$libresoc.v:137373$5642_Y - connect \$11 $eq$libresoc.v:137374$5643_Y - connect \$119 $ternary$libresoc.v:137375$5644_Y - connect \$121 $ternary$libresoc.v:137376$5645_Y - connect \$123 $ternary$libresoc.v:137377$5646_Y - connect \$125 $ternary$libresoc.v:137378$5647_Y - connect \$127 $ternary$libresoc.v:137379$5648_Y - connect \$129 $ternary$libresoc.v:137380$5649_Y - connect \$131 $ternary$libresoc.v:137381$5650_Y - connect \$133 $ternary$libresoc.v:137382$5651_Y - connect \$135 $ternary$libresoc.v:137383$5652_Y - connect \$137 $ternary$libresoc.v:137384$5653_Y - connect \$13 $eq$libresoc.v:137385$5654_Y - connect \$139 $ternary$libresoc.v:137386$5655_Y - connect \$141 $ternary$libresoc.v:137387$5656_Y - connect \$143 $ternary$libresoc.v:137388$5657_Y - connect \$145 $ternary$libresoc.v:137389$5658_Y - connect \$147 $ternary$libresoc.v:137390$5659_Y - connect \$149 $ternary$libresoc.v:137391$5660_Y - connect \$151 $ternary$libresoc.v:137392$5661_Y - connect \$153 $ternary$libresoc.v:137393$5662_Y - connect \$155 $ternary$libresoc.v:137394$5663_Y - connect \$157 $ternary$libresoc.v:137395$5664_Y - connect \$15 $or$libresoc.v:137396$5665_Y - connect \$159 $ternary$libresoc.v:137397$5666_Y - connect \$161 $ternary$libresoc.v:137398$5667_Y - connect \$163 $ternary$libresoc.v:137399$5668_Y - connect \$165 $ternary$libresoc.v:137400$5669_Y - connect \$167 $ternary$libresoc.v:137401$5670_Y - connect \$169 $ternary$libresoc.v:137402$5671_Y - connect \$171 $ternary$libresoc.v:137403$5672_Y - connect \$173 $ternary$libresoc.v:137404$5673_Y - connect \$175 $ternary$libresoc.v:137405$5674_Y - connect \$177 $ternary$libresoc.v:137406$5675_Y - connect \$17 $and$libresoc.v:137407$5676_Y - connect \$179 $ternary$libresoc.v:137408$5677_Y - connect \$181 $ternary$libresoc.v:137409$5678_Y - connect \$183 $ternary$libresoc.v:137410$5679_Y - connect \$185 $ternary$libresoc.v:137411$5680_Y - connect \$187 $ternary$libresoc.v:137412$5681_Y - connect \$189 $ternary$libresoc.v:137413$5682_Y - connect \$191 $ternary$libresoc.v:137414$5683_Y - connect \$193 $ternary$libresoc.v:137415$5684_Y - connect \$195 $ternary$libresoc.v:137416$5685_Y - connect \$197 $ternary$libresoc.v:137417$5686_Y - connect \$1 $eq$libresoc.v:137418$5687_Y - connect \$19 $eq$libresoc.v:137419$5688_Y - connect \$199 $ternary$libresoc.v:137420$5689_Y - connect \$201 $ternary$libresoc.v:137421$5690_Y - connect \$203 $ternary$libresoc.v:137422$5691_Y - connect \$205 $ternary$libresoc.v:137423$5692_Y - connect \$207 $ternary$libresoc.v:137424$5693_Y - connect \$209 $ternary$libresoc.v:137425$5694_Y - connect \$211 $ternary$libresoc.v:137426$5695_Y - connect \$213 $ternary$libresoc.v:137427$5696_Y - connect \$215 $ternary$libresoc.v:137428$5697_Y - connect \$217 $ternary$libresoc.v:137429$5698_Y - connect \$21 $eq$libresoc.v:137430$5699_Y - connect \$219 $ternary$libresoc.v:137431$5700_Y - connect \$221 $ternary$libresoc.v:137432$5701_Y - connect \$223 $ternary$libresoc.v:137433$5702_Y - connect \$225 $ternary$libresoc.v:137434$5703_Y - connect \$227 $ternary$libresoc.v:137435$5704_Y - connect \$229 $ternary$libresoc.v:137436$5705_Y - connect \$231 $ternary$libresoc.v:137437$5706_Y - connect \$233 $ternary$libresoc.v:137438$5707_Y - connect \$235 $ternary$libresoc.v:137439$5708_Y - connect \$237 $ternary$libresoc.v:137440$5709_Y - connect \$23 $or$libresoc.v:137441$5710_Y - connect \$239 $ternary$libresoc.v:137442$5711_Y - connect \$241 $ternary$libresoc.v:137443$5712_Y - connect \$243 $ternary$libresoc.v:137444$5713_Y - connect \$245 $ternary$libresoc.v:137445$5714_Y - connect \$247 $ternary$libresoc.v:137446$5715_Y - connect \$249 $ternary$libresoc.v:137447$5716_Y - connect \$251 $ternary$libresoc.v:137448$5717_Y - connect \$253 $ternary$libresoc.v:137449$5718_Y - connect \$255 $ternary$libresoc.v:137450$5719_Y - connect \$257 $ternary$libresoc.v:137451$5720_Y - connect \$25 $eq$libresoc.v:137452$5721_Y - connect \$259 $ternary$libresoc.v:137453$5722_Y - connect \$261 $ternary$libresoc.v:137454$5723_Y - connect \$263 $ternary$libresoc.v:137455$5724_Y - connect \$265 $ternary$libresoc.v:137456$5725_Y - connect \$267 $ternary$libresoc.v:137457$5726_Y - connect \$269 $ternary$libresoc.v:137458$5727_Y - connect \$271 $ternary$libresoc.v:137459$5728_Y - connect \$273 $ternary$libresoc.v:137460$5729_Y - connect \$275 $ternary$libresoc.v:137461$5730_Y - connect \$277 $ternary$libresoc.v:137462$5731_Y - connect \$27 $or$libresoc.v:137463$5732_Y - connect \$279 $ternary$libresoc.v:137464$5733_Y - connect \$281 $ternary$libresoc.v:137465$5734_Y - connect \$283 $ternary$libresoc.v:137466$5735_Y - connect \$285 $ternary$libresoc.v:137467$5736_Y - connect \$287 $ternary$libresoc.v:137468$5737_Y - connect \$289 $ternary$libresoc.v:137469$5738_Y - connect \$291 $ternary$libresoc.v:137470$5739_Y - connect \$293 $ternary$libresoc.v:137471$5740_Y - connect \$295 $ternary$libresoc.v:137472$5741_Y - connect \$297 $ternary$libresoc.v:137473$5742_Y - connect \$29 $and$libresoc.v:137474$5743_Y - connect \$299 $ternary$libresoc.v:137475$5744_Y - connect \$301 $ternary$libresoc.v:137476$5745_Y - connect \$303 $ternary$libresoc.v:137477$5746_Y - connect \$305 $ternary$libresoc.v:137478$5747_Y - connect \$307 $ternary$libresoc.v:137479$5748_Y - connect \$309 $ternary$libresoc.v:137480$5749_Y - connect \$311 $ternary$libresoc.v:137481$5750_Y - connect \$313 $ternary$libresoc.v:137482$5751_Y - connect \$315 $ternary$libresoc.v:137483$5752_Y - connect \$317 $ternary$libresoc.v:137484$5753_Y - connect \$31 $and$libresoc.v:137485$5754_Y - connect \$319 $ternary$libresoc.v:137486$5755_Y - connect \$321 $ternary$libresoc.v:137487$5756_Y - connect \$323 $ternary$libresoc.v:137488$5757_Y - connect \$325 $ternary$libresoc.v:137489$5758_Y - connect \$327 $ternary$libresoc.v:137490$5759_Y - connect \$329 $ternary$libresoc.v:137491$5760_Y - connect \$331 $ternary$libresoc.v:137492$5761_Y - connect \$333 $ternary$libresoc.v:137493$5762_Y - connect \$335 $ternary$libresoc.v:137494$5763_Y - connect \$337 $ternary$libresoc.v:137495$5764_Y - connect \$33 $eq$libresoc.v:137496$5765_Y - connect \$339 $ternary$libresoc.v:137497$5766_Y - connect \$341 $ternary$libresoc.v:137498$5767_Y - connect \$343 $ternary$libresoc.v:137499$5768_Y - connect \$345 $ternary$libresoc.v:137500$5769_Y - connect \$347 $ternary$libresoc.v:137501$5770_Y - connect \$349 $ternary$libresoc.v:137502$5771_Y - connect \$351 $ternary$libresoc.v:137503$5772_Y - connect \$353 $ternary$libresoc.v:137504$5773_Y - connect \$355 $ternary$libresoc.v:137505$5774_Y - connect \$357 $ternary$libresoc.v:137506$5775_Y - connect \$35 $eq$libresoc.v:137507$5776_Y - connect \$359 $eq$libresoc.v:137508$5777_Y - connect \$361 $eq$libresoc.v:137509$5778_Y - connect \$363 $or$libresoc.v:137510$5779_Y - connect \$365 $eq$libresoc.v:137511$5780_Y - connect \$367 $or$libresoc.v:137512$5781_Y - connect \$369 $and$libresoc.v:137513$5782_Y - connect \$371 $eq$libresoc.v:137514$5783_Y - connect \$373 $ne$libresoc.v:137515$5784_Y - connect \$375 $and$libresoc.v:137516$5785_Y - connect \$377 $ne$libresoc.v:137517$5786_Y - connect \$37 $or$libresoc.v:137518$5787_Y - connect \$379 $and$libresoc.v:137519$5788_Y - connect \$381 $ne$libresoc.v:137520$5789_Y - connect \$383 $and$libresoc.v:137521$5790_Y - connect \$385 $not$libresoc.v:137522$5791_Y - connect \$387 $and$libresoc.v:137523$5792_Y - connect \$389 $eq$libresoc.v:137524$5793_Y - connect \$391 $ne$libresoc.v:137525$5794_Y - connect \$393 $and$libresoc.v:137526$5795_Y - connect \$395 $ne$libresoc.v:137527$5796_Y - connect \$397 $and$libresoc.v:137528$5797_Y - connect \$3 $eq$libresoc.v:137529$5798_Y - connect \$39 $eq$libresoc.v:137530$5799_Y - connect \$399 $ne$libresoc.v:137531$5800_Y - connect \$401 $and$libresoc.v:137532$5801_Y - connect \$403 $not$libresoc.v:137533$5802_Y - connect \$405 $and$libresoc.v:137534$5803_Y - connect \$407 $eq$libresoc.v:137535$5804_Y - connect \$409 $eq$libresoc.v:137536$5805_Y - connect \$411 $ne$libresoc.v:137537$5806_Y - connect \$413 $and$libresoc.v:137538$5807_Y - connect \$415 $ne$libresoc.v:137539$5808_Y - connect \$417 $and$libresoc.v:137540$5809_Y - connect \$41 $or$libresoc.v:137541$5810_Y - connect \$419 $ne$libresoc.v:137542$5811_Y - connect \$421 $and$libresoc.v:137543$5812_Y - connect \$423 $not$libresoc.v:137544$5813_Y - connect \$425 $and$libresoc.v:137545$5814_Y - connect \$427 $eq$libresoc.v:137546$5815_Y - connect \$429 $ne$libresoc.v:137547$5816_Y - connect \$431 $and$libresoc.v:137548$5817_Y - connect \$433 $ne$libresoc.v:137549$5818_Y - connect \$435 $and$libresoc.v:137550$5819_Y - connect \$437 $ne$libresoc.v:137551$5820_Y - connect \$43 $and$libresoc.v:137552$5821_Y - connect \$439 $and$libresoc.v:137553$5822_Y - connect \$441 $not$libresoc.v:137554$5823_Y - connect \$443 $and$libresoc.v:137555$5824_Y - connect \$445 $eq$libresoc.v:137556$5825_Y - connect \$447 $eq$libresoc.v:137557$5826_Y - connect \$449 $ne$libresoc.v:137558$5827_Y - connect \$451 $and$libresoc.v:137559$5828_Y - connect \$453 $ne$libresoc.v:137560$5829_Y - connect \$455 $and$libresoc.v:137561$5830_Y - connect \$457 $ne$libresoc.v:137562$5831_Y - connect \$45 $and$libresoc.v:137563$5832_Y - connect \$459 $and$libresoc.v:137564$5833_Y - connect \$461 $not$libresoc.v:137565$5834_Y - connect \$463 $and$libresoc.v:137566$5835_Y - connect \$465 $eq$libresoc.v:137567$5836_Y - connect \$467 $ne$libresoc.v:137568$5837_Y - connect \$469 $and$libresoc.v:137569$5838_Y - connect \$471 $ne$libresoc.v:137570$5839_Y - connect \$473 $and$libresoc.v:137571$5840_Y - connect \$475 $ne$libresoc.v:137572$5841_Y - connect \$477 $and$libresoc.v:137573$5842_Y - connect \$47 $eq$libresoc.v:137574$5843_Y - connect \$479 $not$libresoc.v:137575$5844_Y - connect \$481 $and$libresoc.v:137576$5845_Y - connect \$484 $eq$libresoc.v:137577$5846_Y - connect \$483 $not$libresoc.v:137578$5847_Y - connect \$487 $eq$libresoc.v:137579$5848_Y - connect \$489 $eq$libresoc.v:137580$5849_Y - connect \$491 $or$libresoc.v:137581$5850_Y - connect \$493 $eq$libresoc.v:137582$5851_Y - connect \$496 $add$libresoc.v:137583$5852_Y - connect \$49 $eq$libresoc.v:137584$5853_Y - connect \$499 $add$libresoc.v:137585$5854_Y - connect \$501 $pos$libresoc.v:137586$5856_Y - connect \$504 $eq$libresoc.v:137587$5857_Y - connect \$506 $eq$libresoc.v:137588$5858_Y - connect \$508 $or$libresoc.v:137589$5859_Y - connect \$510 $eq$libresoc.v:137590$5860_Y - connect \$513 $add$libresoc.v:137591$5861_Y - connect \$516 $add$libresoc.v:137592$5862_Y - connect \$51 $ternary$libresoc.v:137593$5863_Y - connect \$53 $ternary$libresoc.v:137594$5864_Y - connect \$55 $ternary$libresoc.v:137595$5865_Y - connect \$57 $ternary$libresoc.v:137596$5866_Y - connect \$5 $or$libresoc.v:137597$5867_Y - connect \$59 $ternary$libresoc.v:137598$5868_Y - connect \$61 $ternary$libresoc.v:137599$5869_Y - connect \$63 $ternary$libresoc.v:137600$5870_Y - connect \$65 $ternary$libresoc.v:137601$5871_Y - connect \$67 $ternary$libresoc.v:137602$5872_Y - connect \$69 $ternary$libresoc.v:137603$5873_Y - connect \$71 $ternary$libresoc.v:137604$5874_Y - connect \$73 $ternary$libresoc.v:137605$5875_Y - connect \$75 $ternary$libresoc.v:137606$5876_Y - connect \$77 $ternary$libresoc.v:137607$5877_Y - connect \$7 $and$libresoc.v:137608$5878_Y - connect \$79 $ternary$libresoc.v:137609$5879_Y - connect \$81 $ternary$libresoc.v:137610$5880_Y - connect \$83 $ternary$libresoc.v:137611$5881_Y - connect \$85 $ternary$libresoc.v:137612$5882_Y - connect \$87 $ternary$libresoc.v:137613$5883_Y - connect \$89 $ternary$libresoc.v:137614$5884_Y - connect \$91 $ternary$libresoc.v:137615$5885_Y - connect \$93 $ternary$libresoc.v:137616$5886_Y - connect \$95 $ternary$libresoc.v:137617$5887_Y - connect \$97 $ternary$libresoc.v:137618$5888_Y - connect \$495 \$496 - connect \$498 \$499 - connect \$512 \$513 - connect \$515 \$516 + assign $2\io_bd$next[151:0]$6131 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[151:0]$6131 $1\io_bd$next[151:0]$6130 + end + sync always + update \io_bd$next $0\io_bd$next[151:0]$6129 + end + connect \$9 $eq$libresoc.v:138999$5682_Y + connect \$99 $ternary$libresoc.v:139000$5683_Y + connect \$101 $ternary$libresoc.v:139001$5684_Y + connect \$103 $ternary$libresoc.v:139002$5685_Y + connect \$105 $ternary$libresoc.v:139003$5686_Y + connect \$107 $ternary$libresoc.v:139004$5687_Y + connect \$109 $ternary$libresoc.v:139005$5688_Y + connect \$111 $ternary$libresoc.v:139006$5689_Y + connect \$113 $ternary$libresoc.v:139007$5690_Y + connect \$115 $ternary$libresoc.v:139008$5691_Y + connect \$117 $ternary$libresoc.v:139009$5692_Y + connect \$11 $eq$libresoc.v:139010$5693_Y + connect \$119 $ternary$libresoc.v:139011$5694_Y + connect \$121 $ternary$libresoc.v:139012$5695_Y + connect \$123 $ternary$libresoc.v:139013$5696_Y + connect \$125 $ternary$libresoc.v:139014$5697_Y + connect \$127 $ternary$libresoc.v:139015$5698_Y + connect \$129 $ternary$libresoc.v:139016$5699_Y + connect \$131 $ternary$libresoc.v:139017$5700_Y + connect \$133 $ternary$libresoc.v:139018$5701_Y + connect \$135 $ternary$libresoc.v:139019$5702_Y + connect \$137 $ternary$libresoc.v:139020$5703_Y + connect \$13 $eq$libresoc.v:139021$5704_Y + connect \$139 $ternary$libresoc.v:139022$5705_Y + connect \$141 $ternary$libresoc.v:139023$5706_Y + connect \$143 $ternary$libresoc.v:139024$5707_Y + connect \$145 $ternary$libresoc.v:139025$5708_Y + connect \$147 $ternary$libresoc.v:139026$5709_Y + connect \$149 $ternary$libresoc.v:139027$5710_Y + connect \$151 $ternary$libresoc.v:139028$5711_Y + connect \$153 $ternary$libresoc.v:139029$5712_Y + connect \$155 $ternary$libresoc.v:139030$5713_Y + connect \$157 $ternary$libresoc.v:139031$5714_Y + connect \$15 $or$libresoc.v:139032$5715_Y + connect \$159 $ternary$libresoc.v:139033$5716_Y + connect \$161 $ternary$libresoc.v:139034$5717_Y + connect \$163 $ternary$libresoc.v:139035$5718_Y + connect \$165 $ternary$libresoc.v:139036$5719_Y + connect \$167 $ternary$libresoc.v:139037$5720_Y + connect \$169 $ternary$libresoc.v:139038$5721_Y + connect \$171 $ternary$libresoc.v:139039$5722_Y + connect \$173 $ternary$libresoc.v:139040$5723_Y + connect \$175 $ternary$libresoc.v:139041$5724_Y + connect \$177 $ternary$libresoc.v:139042$5725_Y + connect \$17 $and$libresoc.v:139043$5726_Y + connect \$179 $ternary$libresoc.v:139044$5727_Y + connect \$181 $ternary$libresoc.v:139045$5728_Y + connect \$183 $ternary$libresoc.v:139046$5729_Y + connect \$185 $ternary$libresoc.v:139047$5730_Y + connect \$187 $ternary$libresoc.v:139048$5731_Y + connect \$189 $ternary$libresoc.v:139049$5732_Y + connect \$191 $ternary$libresoc.v:139050$5733_Y + connect \$193 $ternary$libresoc.v:139051$5734_Y + connect \$195 $ternary$libresoc.v:139052$5735_Y + connect \$197 $ternary$libresoc.v:139053$5736_Y + connect \$1 $eq$libresoc.v:139054$5737_Y + connect \$19 $eq$libresoc.v:139055$5738_Y + connect \$199 $ternary$libresoc.v:139056$5739_Y + connect \$201 $ternary$libresoc.v:139057$5740_Y + connect \$203 $ternary$libresoc.v:139058$5741_Y + connect \$205 $ternary$libresoc.v:139059$5742_Y + connect \$207 $ternary$libresoc.v:139060$5743_Y + connect \$209 $ternary$libresoc.v:139061$5744_Y + connect \$211 $ternary$libresoc.v:139062$5745_Y + connect \$213 $ternary$libresoc.v:139063$5746_Y + connect \$215 $ternary$libresoc.v:139064$5747_Y + connect \$217 $ternary$libresoc.v:139065$5748_Y + connect \$21 $eq$libresoc.v:139066$5749_Y + connect \$219 $ternary$libresoc.v:139067$5750_Y + connect \$221 $ternary$libresoc.v:139068$5751_Y + connect \$223 $ternary$libresoc.v:139069$5752_Y + connect \$225 $ternary$libresoc.v:139070$5753_Y + connect \$227 $ternary$libresoc.v:139071$5754_Y + connect \$229 $ternary$libresoc.v:139072$5755_Y + connect \$231 $ternary$libresoc.v:139073$5756_Y + connect \$233 $ternary$libresoc.v:139074$5757_Y + connect \$235 $ternary$libresoc.v:139075$5758_Y + connect \$237 $ternary$libresoc.v:139076$5759_Y + connect \$23 $or$libresoc.v:139077$5760_Y + connect \$239 $ternary$libresoc.v:139078$5761_Y + connect \$241 $ternary$libresoc.v:139079$5762_Y + connect \$243 $ternary$libresoc.v:139080$5763_Y + connect \$245 $ternary$libresoc.v:139081$5764_Y + connect \$247 $ternary$libresoc.v:139082$5765_Y + connect \$249 $ternary$libresoc.v:139083$5766_Y + connect \$251 $ternary$libresoc.v:139084$5767_Y + connect \$253 $ternary$libresoc.v:139085$5768_Y + connect \$255 $ternary$libresoc.v:139086$5769_Y + connect \$257 $ternary$libresoc.v:139087$5770_Y + connect \$25 $eq$libresoc.v:139088$5771_Y + connect \$259 $ternary$libresoc.v:139089$5772_Y + connect \$261 $ternary$libresoc.v:139090$5773_Y + connect \$263 $ternary$libresoc.v:139091$5774_Y + connect \$265 $ternary$libresoc.v:139092$5775_Y + connect \$267 $ternary$libresoc.v:139093$5776_Y + connect \$269 $ternary$libresoc.v:139094$5777_Y + connect \$271 $ternary$libresoc.v:139095$5778_Y + connect \$273 $ternary$libresoc.v:139096$5779_Y + connect \$275 $ternary$libresoc.v:139097$5780_Y + connect \$277 $ternary$libresoc.v:139098$5781_Y + connect \$27 $or$libresoc.v:139099$5782_Y + connect \$279 $ternary$libresoc.v:139100$5783_Y + connect \$281 $ternary$libresoc.v:139101$5784_Y + connect \$283 $ternary$libresoc.v:139102$5785_Y + connect \$285 $ternary$libresoc.v:139103$5786_Y + connect \$287 $ternary$libresoc.v:139104$5787_Y + connect \$289 $ternary$libresoc.v:139105$5788_Y + connect \$291 $ternary$libresoc.v:139106$5789_Y + connect \$293 $ternary$libresoc.v:139107$5790_Y + connect \$295 $ternary$libresoc.v:139108$5791_Y + connect \$297 $ternary$libresoc.v:139109$5792_Y + connect \$29 $and$libresoc.v:139110$5793_Y + connect \$299 $ternary$libresoc.v:139111$5794_Y + connect \$301 $ternary$libresoc.v:139112$5795_Y + connect \$303 $ternary$libresoc.v:139113$5796_Y + connect \$305 $ternary$libresoc.v:139114$5797_Y + connect \$307 $ternary$libresoc.v:139115$5798_Y + connect \$309 $ternary$libresoc.v:139116$5799_Y + connect \$311 $ternary$libresoc.v:139117$5800_Y + connect \$313 $ternary$libresoc.v:139118$5801_Y + connect \$315 $ternary$libresoc.v:139119$5802_Y + connect \$317 $ternary$libresoc.v:139120$5803_Y + connect \$31 $and$libresoc.v:139121$5804_Y + connect \$319 $ternary$libresoc.v:139122$5805_Y + connect \$321 $ternary$libresoc.v:139123$5806_Y + connect \$323 $ternary$libresoc.v:139124$5807_Y + connect \$325 $ternary$libresoc.v:139125$5808_Y + connect \$327 $ternary$libresoc.v:139126$5809_Y + connect \$329 $ternary$libresoc.v:139127$5810_Y + connect \$331 $ternary$libresoc.v:139128$5811_Y + connect \$333 $ternary$libresoc.v:139129$5812_Y + connect \$335 $ternary$libresoc.v:139130$5813_Y + connect \$337 $ternary$libresoc.v:139131$5814_Y + connect \$33 $eq$libresoc.v:139132$5815_Y + connect \$339 $ternary$libresoc.v:139133$5816_Y + connect \$341 $ternary$libresoc.v:139134$5817_Y + connect \$343 $ternary$libresoc.v:139135$5818_Y + connect \$345 $ternary$libresoc.v:139136$5819_Y + connect \$347 $ternary$libresoc.v:139137$5820_Y + connect \$349 $ternary$libresoc.v:139138$5821_Y + connect \$351 $ternary$libresoc.v:139139$5822_Y + connect \$353 $ternary$libresoc.v:139140$5823_Y + connect \$355 $eq$libresoc.v:139141$5824_Y + connect \$357 $eq$libresoc.v:139142$5825_Y + connect \$35 $eq$libresoc.v:139143$5826_Y + connect \$359 $or$libresoc.v:139144$5827_Y + connect \$361 $eq$libresoc.v:139145$5828_Y + connect \$363 $or$libresoc.v:139146$5829_Y + connect \$365 $and$libresoc.v:139147$5830_Y + connect \$367 $eq$libresoc.v:139148$5831_Y + connect \$369 $ne$libresoc.v:139149$5832_Y + connect \$371 $and$libresoc.v:139150$5833_Y + connect \$373 $ne$libresoc.v:139151$5834_Y + connect \$375 $and$libresoc.v:139152$5835_Y + connect \$377 $ne$libresoc.v:139153$5836_Y + connect \$37 $or$libresoc.v:139154$5837_Y + connect \$379 $and$libresoc.v:139155$5838_Y + connect \$381 $not$libresoc.v:139156$5839_Y + connect \$383 $and$libresoc.v:139157$5840_Y + connect \$385 $eq$libresoc.v:139158$5841_Y + connect \$387 $ne$libresoc.v:139159$5842_Y + connect \$389 $and$libresoc.v:139160$5843_Y + connect \$391 $ne$libresoc.v:139161$5844_Y + connect \$393 $and$libresoc.v:139162$5845_Y + connect \$395 $ne$libresoc.v:139163$5846_Y + connect \$397 $and$libresoc.v:139164$5847_Y + connect \$3 $eq$libresoc.v:139165$5848_Y + connect \$39 $eq$libresoc.v:139166$5849_Y + connect \$399 $not$libresoc.v:139167$5850_Y + connect \$401 $and$libresoc.v:139168$5851_Y + connect \$403 $eq$libresoc.v:139169$5852_Y + connect \$405 $eq$libresoc.v:139170$5853_Y + connect \$407 $ne$libresoc.v:139171$5854_Y + connect \$409 $and$libresoc.v:139172$5855_Y + connect \$411 $ne$libresoc.v:139173$5856_Y + connect \$413 $and$libresoc.v:139174$5857_Y + connect \$415 $ne$libresoc.v:139175$5858_Y + connect \$417 $and$libresoc.v:139176$5859_Y + connect \$41 $or$libresoc.v:139177$5860_Y + connect \$419 $not$libresoc.v:139178$5861_Y + connect \$421 $and$libresoc.v:139179$5862_Y + connect \$423 $eq$libresoc.v:139180$5863_Y + connect \$425 $ne$libresoc.v:139181$5864_Y + connect \$427 $and$libresoc.v:139182$5865_Y + connect \$429 $ne$libresoc.v:139183$5866_Y + connect \$431 $and$libresoc.v:139184$5867_Y + connect \$433 $ne$libresoc.v:139185$5868_Y + connect \$435 $and$libresoc.v:139186$5869_Y + connect \$437 $not$libresoc.v:139187$5870_Y + connect \$43 $and$libresoc.v:139188$5871_Y + connect \$439 $and$libresoc.v:139189$5872_Y + connect \$441 $eq$libresoc.v:139190$5873_Y + connect \$443 $eq$libresoc.v:139191$5874_Y + connect \$445 $ne$libresoc.v:139192$5875_Y + connect \$447 $and$libresoc.v:139193$5876_Y + connect \$449 $ne$libresoc.v:139194$5877_Y + connect \$451 $and$libresoc.v:139195$5878_Y + connect \$453 $ne$libresoc.v:139196$5879_Y + connect \$455 $and$libresoc.v:139197$5880_Y + connect \$457 $not$libresoc.v:139198$5881_Y + connect \$45 $and$libresoc.v:139199$5882_Y + connect \$459 $and$libresoc.v:139200$5883_Y + connect \$461 $eq$libresoc.v:139201$5884_Y + connect \$463 $ne$libresoc.v:139202$5885_Y + connect \$465 $and$libresoc.v:139203$5886_Y + connect \$467 $ne$libresoc.v:139204$5887_Y + connect \$469 $and$libresoc.v:139205$5888_Y + connect \$471 $ne$libresoc.v:139206$5889_Y + connect \$473 $and$libresoc.v:139207$5890_Y + connect \$475 $not$libresoc.v:139208$5891_Y + connect \$477 $and$libresoc.v:139209$5892_Y + connect \$47 $eq$libresoc.v:139210$5893_Y + connect \$480 $eq$libresoc.v:139211$5894_Y + connect \$479 $not$libresoc.v:139212$5895_Y + connect \$483 $eq$libresoc.v:139213$5896_Y + connect \$485 $eq$libresoc.v:139214$5897_Y + connect \$487 $or$libresoc.v:139215$5898_Y + connect \$489 $eq$libresoc.v:139216$5899_Y + connect \$492 $add$libresoc.v:139217$5900_Y + connect \$495 $add$libresoc.v:139218$5901_Y + connect \$497 $pos$libresoc.v:139219$5903_Y + connect \$49 $eq$libresoc.v:139220$5904_Y + connect \$500 $eq$libresoc.v:139221$5905_Y + connect \$502 $eq$libresoc.v:139222$5906_Y + connect \$504 $or$libresoc.v:139223$5907_Y + connect \$506 $eq$libresoc.v:139224$5908_Y + connect \$509 $add$libresoc.v:139225$5909_Y + connect \$512 $add$libresoc.v:139226$5910_Y + connect \$51 $ternary$libresoc.v:139227$5911_Y + connect \$53 $ternary$libresoc.v:139228$5912_Y + connect \$55 $ternary$libresoc.v:139229$5913_Y + connect \$57 $ternary$libresoc.v:139230$5914_Y + connect \$5 $or$libresoc.v:139231$5915_Y + connect \$59 $ternary$libresoc.v:139232$5916_Y + connect \$61 $ternary$libresoc.v:139233$5917_Y + connect \$63 $ternary$libresoc.v:139234$5918_Y + connect \$65 $ternary$libresoc.v:139235$5919_Y + connect \$67 $ternary$libresoc.v:139236$5920_Y + connect \$69 $ternary$libresoc.v:139237$5921_Y + connect \$71 $ternary$libresoc.v:139238$5922_Y + connect \$73 $ternary$libresoc.v:139239$5923_Y + connect \$75 $ternary$libresoc.v:139240$5924_Y + connect \$77 $ternary$libresoc.v:139241$5925_Y + connect \$7 $and$libresoc.v:139242$5926_Y + connect \$79 $ternary$libresoc.v:139243$5927_Y + connect \$81 $ternary$libresoc.v:139244$5928_Y + connect \$83 $ternary$libresoc.v:139245$5929_Y + connect \$85 $ternary$libresoc.v:139246$5930_Y + connect \$87 $ternary$libresoc.v:139247$5931_Y + connect \$89 $ternary$libresoc.v:139248$5932_Y + connect \$91 $ternary$libresoc.v:139249$5933_Y + connect \$93 $ternary$libresoc.v:139250$5934_Y + connect \$95 $ternary$libresoc.v:139251$5935_Y + connect \$97 $ternary$libresoc.v:139252$5936_Y + connect \$491 \$492 + connect \$494 \$495 + connect \$508 \$509 + connect \$511 \$512 connect \sr5__ie 1'0 connect \sr0__i \sr0__o - connect \dmi0__we_i \$510 - connect \dmi0__req_i \$508 - connect \dmi0_addrsr__i \$501 - connect \jtag_wb__we \$493 - connect \jtag_wb__stb \$491 - connect \jtag_wb__cyc \$483 + connect \dmi0__we_i \$506 + connect \dmi0__req_i \$504 + connect \dmi0_addrsr__i \$497 + connect \jtag_wb__we \$489 + connect \jtag_wb__stb \$487 + connect \jtag_wb__cyc \$479 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$477 - connect \sr5_shift \$473 - connect \sr5_capture \$469 - connect \sr5_isir \$465 + connect \sr5_update \$473 + connect \sr5_shift \$469 + connect \sr5_capture \$465 + connect \sr5_isir \$461 connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$459 - connect \dmi0_datasr_shift \$455 - connect \dmi0_datasr_capture \$451 - connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr_update \$455 + connect \dmi0_datasr_shift \$451 + connect \dmi0_datasr_capture \$447 + connect \dmi0_datasr_isir { \$443 \$441 } connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$439 - connect \dmi0_addrsr_shift \$435 - connect \dmi0_addrsr_capture \$431 - connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr_update \$435 + connect \dmi0_addrsr_shift \$431 + connect \dmi0_addrsr_capture \$427 + connect \dmi0_addrsr_isir \$423 connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$421 - connect \jtag_wb_datasr_shift \$417 - connect \jtag_wb_datasr_capture \$413 - connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr_update \$417 + connect \jtag_wb_datasr_shift \$413 + connect \jtag_wb_datasr_capture \$409 + connect \jtag_wb_datasr_isir { \$405 \$403 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$401 - connect \jtag_wb_addrsr_shift \$397 - connect \jtag_wb_addrsr_capture \$393 - connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr_update \$397 + connect \jtag_wb_addrsr_shift \$393 + connect \jtag_wb_addrsr_capture \$389 + connect \jtag_wb_addrsr_isir \$385 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$383 - connect \sr0_shift \$379 - connect \sr0_capture \$375 - connect \sr0_isir \$371 + connect \sr0_update \$379 + connect \sr0_shift \$375 + connect \sr0_capture \$371 + connect \sr0_isir \$367 connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$357 - connect \sdr_dq_15__pad__o \$355 - connect \sdr_dq_15__core__i \$353 - connect \sdr_dq_14__pad__oe \$351 - connect \sdr_dq_14__pad__o \$349 - connect \sdr_dq_14__core__i \$347 - connect \sdr_dq_13__pad__oe \$345 - connect \sdr_dq_13__pad__o \$343 - connect \sdr_dq_13__core__i \$341 - connect \sdr_dq_12__pad__oe \$339 - connect \sdr_dq_12__pad__o \$337 - connect \sdr_dq_12__core__i \$335 - connect \sdr_dq_11__pad__oe \$333 - connect \sdr_dq_11__pad__o \$331 - connect \sdr_dq_11__core__i \$329 - connect \sdr_dq_10__pad__oe \$327 - connect \sdr_dq_10__pad__o \$325 - connect \sdr_dq_10__core__i \$323 - connect \sdr_dq_9__pad__oe \$321 - connect \sdr_dq_9__pad__o \$319 - connect \sdr_dq_9__core__i \$317 - connect \sdr_dq_8__pad__oe \$315 - connect \sdr_dq_8__pad__o \$313 - connect \sdr_dq_8__core__i \$311 - connect \sdr_dm_1__pad__oe \$309 - connect \sdr_dm_1__pad__o \$307 - connect \sdr_dm_1__core__i \$305 + connect \sdr_dq_15__pad__oe \$353 + connect \sdr_dq_15__pad__o \$351 + connect \sdr_dq_15__core__i \$349 + connect \sdr_dq_14__pad__oe \$347 + connect \sdr_dq_14__pad__o \$345 + connect \sdr_dq_14__core__i \$343 + connect \sdr_dq_13__pad__oe \$341 + connect \sdr_dq_13__pad__o \$339 + connect \sdr_dq_13__core__i \$337 + connect \sdr_dq_12__pad__oe \$335 + connect \sdr_dq_12__pad__o \$333 + connect \sdr_dq_12__core__i \$331 + connect \sdr_dq_11__pad__oe \$329 + connect \sdr_dq_11__pad__o \$327 + connect \sdr_dq_11__core__i \$325 + connect \sdr_dq_10__pad__oe \$323 + connect \sdr_dq_10__pad__o \$321 + connect \sdr_dq_10__core__i \$319 + connect \sdr_dq_9__pad__oe \$317 + connect \sdr_dq_9__pad__o \$315 + connect \sdr_dq_9__core__i \$313 + connect \sdr_dq_8__pad__oe \$311 + connect \sdr_dq_8__pad__o \$309 + connect \sdr_dq_8__core__i \$307 + connect \sdr_dm_1__pad__o \$305 connect \sdr_a_12__pad__o \$303 connect \sdr_a_11__pad__o \$301 connect \sdr_a_10__pad__o \$299 @@ -222156,14 +224653,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:138654.1-138843.10" +attribute \src "libresoc.v:140286.1-140475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -222266,7 +224763,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:138759.12-138793.4" + attribute \src "libresoc.v:140391.12-140425.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222303,7 +224800,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:138794.9-138816.4" + attribute \src "libresoc.v:140426.9-140448.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222328,7 +224825,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:138817.9-138841.4" + attribute \src "libresoc.v:140449.9-140473.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222356,145 +224853,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:138847.1-139255.10" +attribute \src "libresoc.v:140479.1-140887.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:139110.3-139124.6" - wire $0\idx_l$23$next[0:0]$6162 - attribute \src "libresoc.v:139010.3-139011.35" - wire $0\idx_l$23[0:0]$6129 - attribute \src "libresoc.v:138868.7-138868.24" - wire $0\idx_l$23[0:0]$6184 - attribute \src "libresoc.v:139165.3-139174.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $0\idx_l$23$next[0:0]$6210 + attribute \src "libresoc.v:140642.3-140643.35" + wire $0\idx_l$23[0:0]$6177 + attribute \src "libresoc.v:140500.7-140500.24" + wire $0\idx_l$23[0:0]$6232 + attribute \src "libresoc.v:140797.3-140806.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139155.3-139164.6" + attribute \src "libresoc.v:140787.3-140796.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:138848.7-138848.20" + attribute \src "libresoc.v:140480.7-140480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139031.3-139040.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6131 - attribute \src "libresoc.v:139041.3-139050.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6134 - attribute \src "libresoc.v:139083.3-139092.6" + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 + attribute \src "libresoc.v:140673.3-140682.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 + attribute \src "libresoc.v:140715.3-140724.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139073.3-139082.6" + attribute \src "libresoc.v:140705.3-140714.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139145.3-139154.6" + attribute \src "libresoc.v:140777.3-140786.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139220.3-139229.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6179 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6146 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6147 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6148 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6149 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6150 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6151 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6152 - attribute \src "libresoc.v:139093.3-139109.6" - wire $0\ldst_port0_exc_$signal[0:0]$6145 - attribute \src "libresoc.v:139230.3-139239.6" + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6194 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6195 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6196 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6197 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6198 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6199 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6200 + attribute \src "libresoc.v:140725.3-140741.6" + wire $0\ldst_port0_exc_$signal[0:0]$6193 + attribute \src "libresoc.v:140862.3-140871.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139200.3-139209.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6173 - attribute \src "libresoc.v:139210.3-139219.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6176 - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140832.3-140841.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6221 + attribute \src "libresoc.v:140842.3-140851.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6224 + attribute \src "libresoc.v:140694.3-140704.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140694.3-140704.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139135.3-139144.6" + attribute \src "libresoc.v:140767.3-140776.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139125.3-139134.6" + attribute \src "libresoc.v:140757.3-140766.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139051.3-139061.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6137 - attribute \src "libresoc.v:139051.3-139061.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6138 - attribute \src "libresoc.v:139008.3-139009.36" + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 + attribute \src "libresoc.v:140683.3-140693.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + attribute \src "libresoc.v:140640.3-140641.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:139190.3-139199.6" + attribute \src "libresoc.v:140822.3-140831.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140807.3-140821.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139110.3-139124.6" - wire $1\idx_l$23$next[0:0]$6163 - attribute \src "libresoc.v:139165.3-139174.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $1\idx_l$23$next[0:0]$6211 + attribute \src "libresoc.v:140797.3-140806.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139155.3-139164.6" + attribute \src "libresoc.v:140787.3-140796.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:139031.3-139040.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6132 - attribute \src "libresoc.v:139041.3-139050.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6135 - attribute \src "libresoc.v:139083.3-139092.6" + attribute \src "libresoc.v:140663.3-140672.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140673.3-140682.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140715.3-140724.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139073.3-139082.6" + attribute \src "libresoc.v:140705.3-140714.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139145.3-139154.6" + attribute \src "libresoc.v:140777.3-140786.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139220.3-139229.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6180 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6154 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6155 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6156 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6157 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6158 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6159 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6160 - attribute \src "libresoc.v:139093.3-139109.6" - wire $1\ldst_port0_exc_$signal[0:0]$6153 - attribute \src "libresoc.v:139230.3-139239.6" + attribute \src "libresoc.v:140852.3-140861.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6202 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6203 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6204 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6205 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6206 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6207 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140725.3-140741.6" + wire $1\ldst_port0_exc_$signal[0:0]$6201 + attribute \src "libresoc.v:140862.3-140871.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139200.3-139209.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6174 - attribute \src "libresoc.v:139210.3-139219.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6177 - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140832.3-140841.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140842.3-140851.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140694.3-140704.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:139062.3-139072.6" + attribute \src "libresoc.v:140694.3-140704.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139135.3-139144.6" + attribute \src "libresoc.v:140767.3-140776.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139125.3-139134.6" + attribute \src "libresoc.v:140757.3-140766.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139051.3-139061.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6139 - attribute \src "libresoc.v:139051.3-139061.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6140 - attribute \src "libresoc.v:138995.7-138995.25" + attribute \src "libresoc.v:140683.3-140693.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 + attribute \src "libresoc.v:140683.3-140693.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140627.7-140627.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:139190.3-139199.6" + attribute \src "libresoc.v:140822.3-140831.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140807.3-140821.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139110.3-139124.6" - wire $2\idx_l$23$next[0:0]$6164 - attribute \src "libresoc.v:139175.3-139189.6" + attribute \src "libresoc.v:140742.3-140756.6" + wire $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140807.3-140821.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139006.18-139006.103" - wire $not$libresoc.v:139006$6125_Y - attribute \src "libresoc.v:139007.18-139007.118" - wire $not$libresoc.v:139007$6126_Y - attribute \src "libresoc.v:139004.18-139004.134" - wire $or$libresoc.v:139004$6123_Y - attribute \src "libresoc.v:139005.18-139005.120" - wire $ternary$libresoc.v:139005$6124_Y + attribute \src "libresoc.v:140638.18-140638.103" + wire $not$libresoc.v:140638$6173_Y + attribute \src "libresoc.v:140639.18-140639.118" + wire $not$libresoc.v:140639$6174_Y + attribute \src "libresoc.v:140636.18-140636.134" + wire $or$libresoc.v:140636$6171_Y + attribute \src "libresoc.v:140637.18-140637.120" + wire $ternary$libresoc.v:140637$6172_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -222509,9 +225006,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -222523,7 +225020,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:138848.7-138848.15" + attribute \src "libresoc.v:140480.7-140480.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -222634,23 +225131,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:139006$6125 + cell $not $not$libresoc.v:140638$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:139006$6125_Y + connect \Y $not$libresoc.v:140638$6173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:139007$6126 + cell $not $not$libresoc.v:140639$6174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:139007$6126_Y + connect \Y $not$libresoc.v:140639$6174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:139004$6123 + cell $or $or$libresoc.v:140636$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -222658,18 +225155,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:139004$6123_Y + connect \Y $or$libresoc.v:140636$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:139005$6124 + cell $mux $ternary$libresoc.v:140637$6172 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:139005$6124_Y + connect \Y $ternary$libresoc.v:140637$6172_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139012.9-139018.4" + attribute \src "libresoc.v:140644.9-140650.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222678,14 +225175,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:139019.8-139023.4" + attribute \src "libresoc.v:140651.8-140655.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:139024.17-139030.4" + attribute \src "libresoc.v:140656.17-140662.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -222693,52 +225190,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:138848.7-138848.20" - process $proc$libresoc.v:138848$6182 + attribute \src "libresoc.v:140480.7-140480.20" + process $proc$libresoc.v:140480$6230 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138868.7-138868.24" - process $proc$libresoc.v:138868$6183 + attribute \src "libresoc.v:140500.7-140500.24" + process $proc$libresoc.v:140500$6231 assign { } { } - assign $0\idx_l$23[0:0]$6184 1'0 + assign $0\idx_l$23[0:0]$6232 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$6184 + update \idx_l$23 $0\idx_l$23[0:0]$6232 end - attribute \src "libresoc.v:138995.7-138995.25" - process $proc$libresoc.v:138995$6185 + attribute \src "libresoc.v:140627.7-140627.25" + process $proc$libresoc.v:140627$6233 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:139008.3-139009.36" - process $proc$libresoc.v:139008$6127 + attribute \src "libresoc.v:140640.3-140641.36" + process $proc$libresoc.v:140640$6175 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:139010.3-139011.35" - process $proc$libresoc.v:139010$6128 + attribute \src "libresoc.v:140642.3-140643.35" + process $proc$libresoc.v:140642$6176 assign { } { } - assign $0\idx_l$23[0:0]$6129 \idx_l$23$next + assign $0\idx_l$23[0:0]$6177 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6129 + update \idx_l$23 $0\idx_l$23[0:0]$6177 end - attribute \src "libresoc.v:139031.3-139040.6" - process $proc$libresoc.v:139031$6130 + attribute \src "libresoc.v:140663.3-140672.6" + process $proc$libresoc.v:140663$6178 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6131 $1\ldst_port0_addr_i$12[47:0]$6132 - attribute \src "libresoc.v:139032.5-139032.29" + assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 + attribute \src "libresoc.v:140664.5-140664.29" switch \initial - attribute \src "libresoc.v:139032.9-139032.17" + attribute \src "libresoc.v:140664.9-140664.17" case 1'1 case end @@ -222747,21 +225244,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6132 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6180 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$6132 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6180 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6131 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 end - attribute \src "libresoc.v:139041.3-139050.6" - process $proc$libresoc.v:139041$6133 + attribute \src "libresoc.v:140673.3-140682.6" + process $proc$libresoc.v:140673$6181 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6134 $1\ldst_port0_addr_i_ok$13[0:0]$6135 - attribute \src "libresoc.v:139042.5-139042.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 + attribute \src "libresoc.v:140674.5-140674.29" switch \initial - attribute \src "libresoc.v:139042.9-139042.17" + attribute \src "libresoc.v:140674.9-140674.17" case 1'1 case end @@ -222770,24 +225267,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6135 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6134 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 end - attribute \src "libresoc.v:139051.3-139061.6" - process $proc$libresoc.v:139051$6136 + attribute \src "libresoc.v:140683.3-140693.6" + process $proc$libresoc.v:140683$6184 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6137 $1\ldst_port0_st_data_i$18[63:0]$6139 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6138 $1\ldst_port0_st_data_i_ok$17[0:0]$6140 - attribute \src "libresoc.v:139052.5-139052.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 + attribute \src "libresoc.v:140684.5-140684.29" switch \initial - attribute \src "libresoc.v:139052.9-139052.17" + attribute \src "libresoc.v:140684.9-140684.17" case 1'1 case end @@ -222797,26 +225294,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6140 $1\ldst_port0_st_data_i$18[63:0]$6139 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6188 $1\ldst_port0_st_data_i$18[63:0]$6187 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$6139 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6140 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6188 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6137 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6138 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 end - attribute \src "libresoc.v:139062.3-139072.6" - process $proc$libresoc.v:139062$6141 + attribute \src "libresoc.v:140694.3-140704.6" + process $proc$libresoc.v:140694$6189 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:139063.5-139063.29" + attribute \src "libresoc.v:140695.5-140695.29" switch \initial - attribute \src "libresoc.v:139063.9-139063.17" + attribute \src "libresoc.v:140695.9-140695.17" case 1'1 case end @@ -222835,14 +225332,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:139073.3-139082.6" - process $proc$libresoc.v:139073$6142 + attribute \src "libresoc.v:140705.3-140714.6" + process $proc$libresoc.v:140705$6190 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:139074.5-139074.29" + attribute \src "libresoc.v:140706.5-140706.29" switch \initial - attribute \src "libresoc.v:139074.9-139074.17" + attribute \src "libresoc.v:140706.9-140706.17" case 1'1 case end @@ -222858,14 +225355,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:139083.3-139092.6" - process $proc$libresoc.v:139083$6143 + attribute \src "libresoc.v:140715.3-140724.6" + process $proc$libresoc.v:140715$6191 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:139084.5-139084.29" + attribute \src "libresoc.v:140716.5-140716.29" switch \initial - attribute \src "libresoc.v:139084.9-139084.17" + attribute \src "libresoc.v:140716.9-140716.17" case 1'1 case end @@ -222881,8 +225378,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:139093.3-139109.6" - process $proc$libresoc.v:139093$6144 + attribute \src "libresoc.v:140725.3-140741.6" + process $proc$libresoc.v:140725$6192 assign { } { } assign { } { } assign { } { } @@ -222899,17 +225396,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6145 $1\ldst_port0_exc_$signal[0:0]$6153 - assign $0\ldst_port0_exc_$signal$1[0:0]$6146 $1\ldst_port0_exc_$signal$1[0:0]$6154 - assign $0\ldst_port0_exc_$signal$2[0:0]$6147 $1\ldst_port0_exc_$signal$2[0:0]$6155 - assign $0\ldst_port0_exc_$signal$3[0:0]$6148 $1\ldst_port0_exc_$signal$3[0:0]$6156 - assign $0\ldst_port0_exc_$signal$4[0:0]$6149 $1\ldst_port0_exc_$signal$4[0:0]$6157 - assign $0\ldst_port0_exc_$signal$5[0:0]$6150 $1\ldst_port0_exc_$signal$5[0:0]$6158 - assign $0\ldst_port0_exc_$signal$6[0:0]$6151 $1\ldst_port0_exc_$signal$6[0:0]$6159 - assign $0\ldst_port0_exc_$signal$7[0:0]$6152 $1\ldst_port0_exc_$signal$7[0:0]$6160 - attribute \src "libresoc.v:139094.5-139094.29" + assign $0\ldst_port0_exc_$signal[0:0]$6193 $1\ldst_port0_exc_$signal[0:0]$6201 + assign $0\ldst_port0_exc_$signal$1[0:0]$6194 $1\ldst_port0_exc_$signal$1[0:0]$6202 + assign $0\ldst_port0_exc_$signal$2[0:0]$6195 $1\ldst_port0_exc_$signal$2[0:0]$6203 + assign $0\ldst_port0_exc_$signal$3[0:0]$6196 $1\ldst_port0_exc_$signal$3[0:0]$6204 + assign $0\ldst_port0_exc_$signal$4[0:0]$6197 $1\ldst_port0_exc_$signal$4[0:0]$6205 + assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 + assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 + assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 + attribute \src "libresoc.v:140726.5-140726.29" switch \initial - attribute \src "libresoc.v:139094.9-139094.17" + attribute \src "libresoc.v:140726.9-140726.17" case 1'1 case end @@ -222925,36 +225422,36 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6160 $1\ldst_port0_exc_$signal$6[0:0]$6159 $1\ldst_port0_exc_$signal$5[0:0]$6158 $1\ldst_port0_exc_$signal$4[0:0]$6157 $1\ldst_port0_exc_$signal$3[0:0]$6156 $1\ldst_port0_exc_$signal$2[0:0]$6155 $1\ldst_port0_exc_$signal$1[0:0]$6154 $1\ldst_port0_exc_$signal[0:0]$6153 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6208 $1\ldst_port0_exc_$signal$6[0:0]$6207 $1\ldst_port0_exc_$signal$5[0:0]$6206 $1\ldst_port0_exc_$signal$4[0:0]$6205 $1\ldst_port0_exc_$signal$3[0:0]$6204 $1\ldst_port0_exc_$signal$2[0:0]$6203 $1\ldst_port0_exc_$signal$1[0:0]$6202 $1\ldst_port0_exc_$signal[0:0]$6201 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$6153 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6154 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6155 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6156 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6157 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6158 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6159 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6160 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6201 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6202 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6203 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6204 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6205 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6206 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6207 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6208 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6145 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6146 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6147 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6148 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6149 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6150 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6151 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6152 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6193 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6194 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6195 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6196 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6197 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6198 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 end - attribute \src "libresoc.v:139110.3-139124.6" - process $proc$libresoc.v:139110$6161 + attribute \src "libresoc.v:140742.3-140756.6" + process $proc$libresoc.v:140742$6209 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$6162 $2\idx_l$23$next[0:0]$6164 - attribute \src "libresoc.v:139111.5-139111.29" + assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 + attribute \src "libresoc.v:140743.5-140743.29" switch \initial - attribute \src "libresoc.v:139111.9-139111.17" + attribute \src "libresoc.v:140743.9-140743.17" case 1'1 case end @@ -222963,30 +225460,30 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$6163 \pick_o + assign $1\idx_l$23$next[0:0]$6211 \pick_o case - assign $1\idx_l$23$next[0:0]$6163 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6211 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$6164 1'0 + assign $2\idx_l$23$next[0:0]$6212 1'0 case - assign $2\idx_l$23$next[0:0]$6164 $1\idx_l$23$next[0:0]$6163 + assign $2\idx_l$23$next[0:0]$6212 $1\idx_l$23$next[0:0]$6211 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6162 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 end - attribute \src "libresoc.v:139125.3-139134.6" - process $proc$libresoc.v:139125$6165 + attribute \src "libresoc.v:140757.3-140766.6" + process $proc$libresoc.v:140757$6213 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:139126.5-139126.29" + attribute \src "libresoc.v:140758.5-140758.29" switch \initial - attribute \src "libresoc.v:139126.9-139126.17" + attribute \src "libresoc.v:140758.9-140758.17" case 1'1 case end @@ -223002,14 +225499,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:139135.3-139144.6" - process $proc$libresoc.v:139135$6166 + attribute \src "libresoc.v:140767.3-140776.6" + process $proc$libresoc.v:140767$6214 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:139136.5-139136.29" + attribute \src "libresoc.v:140768.5-140768.29" switch \initial - attribute \src "libresoc.v:139136.9-139136.17" + attribute \src "libresoc.v:140768.9-140768.17" case 1'1 case end @@ -223025,14 +225522,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:139145.3-139154.6" - process $proc$libresoc.v:139145$6167 + attribute \src "libresoc.v:140777.3-140786.6" + process $proc$libresoc.v:140777$6215 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:139146.5-139146.29" + attribute \src "libresoc.v:140778.5-140778.29" switch \initial - attribute \src "libresoc.v:139146.9-139146.17" + attribute \src "libresoc.v:140778.9-140778.17" case 1'1 case end @@ -223048,14 +225545,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:139155.3-139164.6" - process $proc$libresoc.v:139155$6168 + attribute \src "libresoc.v:140787.3-140796.6" + process $proc$libresoc.v:140787$6216 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:139156.5-139156.29" + attribute \src "libresoc.v:140788.5-140788.29" switch \initial - attribute \src "libresoc.v:139156.9-139156.17" + attribute \src "libresoc.v:140788.9-140788.17" case 1'1 case end @@ -223071,14 +225568,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:139165.3-139174.6" - process $proc$libresoc.v:139165$6169 + attribute \src "libresoc.v:140797.3-140806.6" + process $proc$libresoc.v:140797$6217 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:139166.5-139166.29" + attribute \src "libresoc.v:140798.5-140798.29" switch \initial - attribute \src "libresoc.v:139166.9-139166.17" + attribute \src "libresoc.v:140798.9-140798.17" case 1'1 case end @@ -223094,14 +225591,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:139175.3-139189.6" - process $proc$libresoc.v:139175$6170 + attribute \src "libresoc.v:140807.3-140821.6" + process $proc$libresoc.v:140807$6218 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:139176.5-139176.29" + attribute \src "libresoc.v:140808.5-140808.29" switch \initial - attribute \src "libresoc.v:139176.9-139176.17" + attribute \src "libresoc.v:140808.9-140808.17" case 1'1 case end @@ -223126,14 +225623,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:139190.3-139199.6" - process $proc$libresoc.v:139190$6171 + attribute \src "libresoc.v:140822.3-140831.6" + process $proc$libresoc.v:140822$6219 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:139191.5-139191.29" + attribute \src "libresoc.v:140823.5-140823.29" switch \initial - attribute \src "libresoc.v:139191.9-139191.17" + attribute \src "libresoc.v:140823.9-140823.17" case 1'1 case end @@ -223149,14 +225646,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:139200.3-139209.6" - process $proc$libresoc.v:139200$6172 + attribute \src "libresoc.v:140832.3-140841.6" + process $proc$libresoc.v:140832$6220 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6173 $1\ldst_port0_is_ld_i$8[0:0]$6174 - attribute \src "libresoc.v:139201.5-139201.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 + attribute \src "libresoc.v:140833.5-140833.29" switch \initial - attribute \src "libresoc.v:139201.9-139201.17" + attribute \src "libresoc.v:140833.9-140833.17" case 1'1 case end @@ -223165,21 +225662,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6174 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$6174 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6222 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6173 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 end - attribute \src "libresoc.v:139210.3-139219.6" - process $proc$libresoc.v:139210$6175 + attribute \src "libresoc.v:140842.3-140851.6" + process $proc$libresoc.v:140842$6223 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6176 $1\ldst_port0_is_st_i$9[0:0]$6177 - attribute \src "libresoc.v:139211.5-139211.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 + attribute \src "libresoc.v:140843.5-140843.29" switch \initial - attribute \src "libresoc.v:139211.9-139211.17" + attribute \src "libresoc.v:140843.9-140843.17" case 1'1 case end @@ -223188,21 +225685,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6177 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6225 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$6177 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6225 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6176 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 end - attribute \src "libresoc.v:139220.3-139229.6" - process $proc$libresoc.v:139220$6178 + attribute \src "libresoc.v:140852.3-140861.6" + process $proc$libresoc.v:140852$6226 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6179 $1\ldst_port0_data_len$11[3:0]$6180 - attribute \src "libresoc.v:139221.5-139221.29" + assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 + attribute \src "libresoc.v:140853.5-140853.29" switch \initial - attribute \src "libresoc.v:139221.9-139221.17" + attribute \src "libresoc.v:140853.9-140853.17" case 1'1 case end @@ -223211,21 +225708,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6180 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6228 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$6180 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6228 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6179 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 end - attribute \src "libresoc.v:139230.3-139239.6" - process $proc$libresoc.v:139230$6181 + attribute \src "libresoc.v:140862.3-140871.6" + process $proc$libresoc.v:140862$6229 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:139231.5-139231.29" + attribute \src "libresoc.v:140863.5-140863.29" switch \initial - attribute \src "libresoc.v:139231.9-139231.17" + attribute \src "libresoc.v:140863.9-140863.17" case 1'1 case end @@ -223241,10 +225738,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:139004$6123_Y - connect \$24 $ternary$libresoc.v:139005$6124_Y - connect \$26 $not$libresoc.v:139006$6125_Y - connect \$28 $not$libresoc.v:139007$6126_Y + connect \$20 $or$libresoc.v:140636$6171_Y + connect \$24 $ternary$libresoc.v:140637$6172_Y + connect \$26 $not$libresoc.v:140638$6173_Y + connect \$28 $not$libresoc.v:140639$6174_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -223261,37 +225758,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:139259.1-139317.10" +attribute \src "libresoc.v:140891.1-140949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:139260.7-139260.20" + attribute \src "libresoc.v:140892.7-140892.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139305.3-139313.6" - wire $0\q_int$next[0:0]$6196 - attribute \src "libresoc.v:139303.3-139304.27" + attribute \src "libresoc.v:140937.3-140945.6" + wire $0\q_int$next[0:0]$6244 + attribute \src "libresoc.v:140935.3-140936.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:139305.3-139313.6" - wire $1\q_int$next[0:0]$6197 - attribute \src "libresoc.v:139282.7-139282.19" + attribute \src "libresoc.v:140937.3-140945.6" + wire $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140914.7-140914.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:139295.17-139295.96" - wire $and$libresoc.v:139295$6186_Y - attribute \src "libresoc.v:139300.17-139300.96" - wire $and$libresoc.v:139300$6191_Y - attribute \src "libresoc.v:139297.18-139297.99" - wire $not$libresoc.v:139297$6188_Y - attribute \src "libresoc.v:139299.17-139299.98" - wire $not$libresoc.v:139299$6190_Y - attribute \src "libresoc.v:139302.17-139302.98" - wire $not$libresoc.v:139302$6193_Y - attribute \src "libresoc.v:139296.18-139296.104" - wire $or$libresoc.v:139296$6187_Y - attribute \src "libresoc.v:139298.18-139298.105" - wire $or$libresoc.v:139298$6189_Y - attribute \src "libresoc.v:139301.17-139301.103" - wire $or$libresoc.v:139301$6192_Y + attribute \src "libresoc.v:140927.17-140927.96" + wire $and$libresoc.v:140927$6234_Y + attribute \src "libresoc.v:140932.17-140932.96" + wire $and$libresoc.v:140932$6239_Y + attribute \src "libresoc.v:140929.18-140929.99" + wire $not$libresoc.v:140929$6236_Y + attribute \src "libresoc.v:140931.17-140931.98" + wire $not$libresoc.v:140931$6238_Y + attribute \src "libresoc.v:140934.17-140934.98" + wire $not$libresoc.v:140934$6241_Y + attribute \src "libresoc.v:140928.18-140928.104" + wire $or$libresoc.v:140928$6235_Y + attribute \src "libresoc.v:140930.18-140930.105" + wire $or$libresoc.v:140930$6237_Y + attribute \src "libresoc.v:140933.17-140933.103" + wire $or$libresoc.v:140933$6240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -223308,11 +225805,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:139260.7-139260.15" + attribute \src "libresoc.v:140892.7-140892.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -223329,7 +225826,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:139295$6186 + cell $and $and$libresoc.v:140927$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223337,10 +225834,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:139295$6186_Y + connect \Y $and$libresoc.v:140927$6234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:139300$6191 + cell $and $and$libresoc.v:140932$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223348,34 +225845,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:139300$6191_Y + connect \Y $and$libresoc.v:140932$6239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:139297$6188 + cell $not $not$libresoc.v:140929$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:139297$6188_Y + connect \Y $not$libresoc.v:140929$6236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:139299$6190 + cell $not $not$libresoc.v:140931$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:139299$6190_Y + connect \Y $not$libresoc.v:140931$6238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:139302$6193 + cell $not $not$libresoc.v:140934$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:139302$6193_Y + connect \Y $not$libresoc.v:140934$6241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:139296$6187 + cell $or $or$libresoc.v:140928$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223383,10 +225880,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:139296$6187_Y + connect \Y $or$libresoc.v:140928$6235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:139298$6189 + cell $or $or$libresoc.v:140930$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223394,10 +225891,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:139298$6189_Y + connect \Y $or$libresoc.v:140930$6237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:139301$6192 + cell $or $or$libresoc.v:140933$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -223405,39 +225902,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:139301$6192_Y + connect \Y $or$libresoc.v:140933$6240_Y end - attribute \src "libresoc.v:139260.7-139260.20" - process $proc$libresoc.v:139260$6198 + attribute \src "libresoc.v:140892.7-140892.20" + process $proc$libresoc.v:140892$6246 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139282.7-139282.19" - process $proc$libresoc.v:139282$6199 + attribute \src "libresoc.v:140914.7-140914.19" + process $proc$libresoc.v:140914$6247 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:139303.3-139304.27" - process $proc$libresoc.v:139303$6194 + attribute \src "libresoc.v:140935.3-140936.27" + process $proc$libresoc.v:140935$6242 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:139305.3-139313.6" - process $proc$libresoc.v:139305$6195 + attribute \src "libresoc.v:140937.3-140945.6" + process $proc$libresoc.v:140937$6243 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6196 $1\q_int$next[0:0]$6197 - attribute \src "libresoc.v:139306.5-139306.29" + assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 + attribute \src "libresoc.v:140938.5-140938.29" switch \initial - attribute \src "libresoc.v:139306.9-139306.17" + attribute \src "libresoc.v:140938.9-140938.17" case 1'1 case end @@ -223446,572 +225943,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6197 1'0 + assign $1\q_int$next[0:0]$6245 1'0 case - assign $1\q_int$next[0:0]$6197 \$5 + assign $1\q_int$next[0:0]$6245 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6196 + update \q_int$next $0\q_int$next[0:0]$6244 end - connect \$9 $and$libresoc.v:139295$6186_Y - connect \$11 $or$libresoc.v:139296$6187_Y - connect \$13 $not$libresoc.v:139297$6188_Y - connect \$15 $or$libresoc.v:139298$6189_Y - connect \$1 $not$libresoc.v:139299$6190_Y - connect \$3 $and$libresoc.v:139300$6191_Y - connect \$5 $or$libresoc.v:139301$6192_Y - connect \$7 $not$libresoc.v:139302$6193_Y + connect \$9 $and$libresoc.v:140927$6234_Y + connect \$11 $or$libresoc.v:140928$6235_Y + connect \$13 $not$libresoc.v:140929$6236_Y + connect \$15 $or$libresoc.v:140930$6237_Y + connect \$1 $not$libresoc.v:140931$6238_Y + connect \$3 $and$libresoc.v:140932$6239_Y + connect \$5 $or$libresoc.v:140933$6240_Y + connect \$7 $not$libresoc.v:140934$6241_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:139321.1-140684.10" +attribute \src "libresoc.v:140953.1-142316.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:140339.3-140347.6" - wire $0\adr_l_r_adr$next[0:0]$6342 - attribute \src "libresoc.v:140221.3-140222.39" + attribute \src "libresoc.v:141971.3-141979.6" + wire $0\adr_l_r_adr$next[0:0]$6390 + attribute \src "libresoc.v:141853.3-141854.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:140167.3-140168.21" + attribute \src "libresoc.v:141799.3-141800.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:140504.3-140513.6" + attribute \src "libresoc.v:142136.3-142145.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:140514.3-140523.6" + attribute \src "libresoc.v:142146.3-142155.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:140494.3-140503.6" - wire width 64 $0\ea_r$next[63:0]$6430 - attribute \src "libresoc.v:140169.3-140170.25" + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $0\ea_r$next[63:0]$6478 + attribute \src "libresoc.v:141801.3-141802.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:139322.7-139322.20" + attribute \src "libresoc.v:140954.7-140954.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:140436.3-140445.6" - wire width 64 $0\ldo_r$next[63:0]$6415 - attribute \src "libresoc.v:140177.3-140178.27" + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $0\ldo_r$next[63:0]$6463 + attribute \src "libresoc.v:141809.3-141810.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:140165.3-140166.33" + attribute \src "libresoc.v:141797.3-141798.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:140524.3-140532.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6435 - attribute \src "libresoc.v:140163.3-140164.57" + attribute \src "libresoc.v:142156.3-142164.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 + attribute \src "libresoc.v:141795.3-141796.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:140613.3-140624.6" + attribute \src "libresoc.v:142245.3-142256.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140384.3-140392.6" - wire $0\lsd_l_r_lsd$next[0:0]$6357 - attribute \src "libresoc.v:140211.3-140212.39" + attribute \src "libresoc.v:142016.3-142024.6" + wire $0\lsd_l_r_lsd$next[0:0]$6405 + attribute \src "libresoc.v:141843.3-141844.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:140312.3-140320.6" - wire $0\opc_l_r_opc$next[0:0]$6333 - attribute \src "libresoc.v:140227.3-140228.39" + attribute \src "libresoc.v:141944.3-141952.6" + wire $0\opc_l_r_opc$next[0:0]$6381 + attribute \src "libresoc.v:141859.3-141860.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140303.3-140311.6" - wire $0\opc_l_s_opc$next[0:0]$6330 - attribute \src "libresoc.v:140229.3-140230.39" + attribute \src "libresoc.v:141935.3-141943.6" + wire $0\opc_l_s_opc$next[0:0]$6378 + attribute \src "libresoc.v:141861.3-141862.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__byte_reverse$next[0:0]$6360 - attribute \src "libresoc.v:140203.3-140204.57" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__byte_reverse$next[0:0]$6408 + attribute \src "libresoc.v:141835.3-141836.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6361 - attribute \src "libresoc.v:140201.3-140202.49" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6409 + attribute \src "libresoc.v:141833.3-141834.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $0\oper_r__fn_unit$next[13:0]$6362 - attribute \src "libresoc.v:140181.3-140182.47" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 + attribute \src "libresoc.v:141813.3-141814.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6363 - attribute \src "libresoc.v:140183.3-140184.61" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 + attribute \src "libresoc.v:141815.3-141816.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6364 - attribute \src "libresoc.v:140185.3-140186.57" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6412 + attribute \src "libresoc.v:141817.3-141818.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $0\oper_r__insn$next[31:0]$6365 - attribute \src "libresoc.v:140209.3-140210.41" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $0\oper_r__insn$next[31:0]$6413 + attribute \src "libresoc.v:141841.3-141842.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6366 - attribute \src "libresoc.v:140179.3-140180.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6414 + attribute \src "libresoc.v:141811.3-141812.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__is_32bit$next[0:0]$6367 - attribute \src "libresoc.v:140197.3-140198.49" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_32bit$next[0:0]$6415 + attribute \src "libresoc.v:141829.3-141830.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__is_signed$next[0:0]$6368 - attribute \src "libresoc.v:140199.3-140200.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__is_signed$next[0:0]$6416 + attribute \src "libresoc.v:141831.3-141832.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6369 - attribute \src "libresoc.v:140207.3-140208.51" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 + attribute \src "libresoc.v:141839.3-141840.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__oe__oe$next[0:0]$6370 - attribute \src "libresoc.v:140193.3-140194.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__oe$next[0:0]$6418 + attribute \src "libresoc.v:141825.3-141826.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__oe__ok$next[0:0]$6371 - attribute \src "libresoc.v:140195.3-140196.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__oe__ok$next[0:0]$6419 + attribute \src "libresoc.v:141827.3-141828.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__rc__ok$next[0:0]$6372 - attribute \src "libresoc.v:140191.3-140192.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__ok$next[0:0]$6420 + attribute \src "libresoc.v:141823.3-141824.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__rc__rc$next[0:0]$6373 - attribute \src "libresoc.v:140189.3-140190.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__rc__rc$next[0:0]$6421 + attribute \src "libresoc.v:141821.3-141822.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__sign_extend$next[0:0]$6374 - attribute \src "libresoc.v:140205.3-140206.55" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__sign_extend$next[0:0]$6422 + attribute \src "libresoc.v:141837.3-141838.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $0\oper_r__zero_a$next[0:0]$6375 - attribute \src "libresoc.v:140187.3-140188.45" + attribute \src "libresoc.v:142025.3-142067.6" + wire $0\oper_r__zero_a$next[0:0]$6423 + attribute \src "libresoc.v:141819.3-141820.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:140231.3-140232.28" + attribute \src "libresoc.v:141863.3-141864.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:140557.3-140568.6" + attribute \src "libresoc.v:142189.3-142200.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:140330.3-140338.6" - wire width 3 $0\src_l_r_src$next[2:0]$6339 - attribute \src "libresoc.v:140223.3-140224.39" + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $0\src_l_r_src$next[2:0]$6387 + attribute \src "libresoc.v:141855.3-141856.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:140321.3-140329.6" - wire width 3 $0\src_l_s_src$next[2:0]$6336 - attribute \src "libresoc.v:140225.3-140226.39" + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $0\src_l_s_src$next[2:0]$6384 + attribute \src "libresoc.v:141857.3-141858.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $0\src_r0$next[63:0]$6418 - attribute \src "libresoc.v:140175.3-140176.29" + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $0\src_r0$next[63:0]$6466 + attribute \src "libresoc.v:141807.3-141808.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $0\src_r1$next[63:0]$6422 - attribute \src "libresoc.v:140173.3-140174.29" + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $0\src_r1$next[63:0]$6470 + attribute \src "libresoc.v:141805.3-141806.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $0\src_r2$next[63:0]$6426 - attribute \src "libresoc.v:140171.3-140172.29" + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $0\src_r2$next[63:0]$6474 + attribute \src "libresoc.v:141803.3-141804.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:140375.3-140383.6" - wire $0\sto_l_r_sto$next[0:0]$6354 - attribute \src "libresoc.v:140213.3-140214.39" + attribute \src "libresoc.v:142007.3-142015.6" + wire $0\sto_l_r_sto$next[0:0]$6402 + attribute \src "libresoc.v:141845.3-141846.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:140366.3-140374.6" - wire $0\upd_l_r_upd$next[0:0]$6351 - attribute \src "libresoc.v:140215.3-140216.39" + attribute \src "libresoc.v:141998.3-142006.6" + wire $0\upd_l_r_upd$next[0:0]$6399 + attribute \src "libresoc.v:141847.3-141848.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:140357.3-140365.6" - wire $0\upd_l_s_upd$next[0:0]$6348 - attribute \src "libresoc.v:140217.3-140218.39" + attribute \src "libresoc.v:141989.3-141997.6" + wire $0\upd_l_s_upd$next[0:0]$6396 + attribute \src "libresoc.v:141849.3-141850.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:140348.3-140356.6" - wire $0\wri_l_r_wri$next[0:0]$6345 - attribute \src "libresoc.v:140219.3-140220.39" + attribute \src "libresoc.v:141980.3-141988.6" + wire $0\wri_l_r_wri$next[0:0]$6393 + attribute \src "libresoc.v:141851.3-141852.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:140339.3-140347.6" - wire $1\adr_l_r_adr$next[0:0]$6343 - attribute \src "libresoc.v:139518.7-139518.25" + attribute \src "libresoc.v:141971.3-141979.6" + wire $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141150.7-141150.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:139532.7-139532.20" + attribute \src "libresoc.v:141164.7-141164.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:140504.3-140513.6" + attribute \src "libresoc.v:142136.3-142145.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:140514.3-140523.6" + attribute \src "libresoc.v:142146.3-142155.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:140494.3-140503.6" - wire width 64 $1\ea_r$next[63:0]$6431 - attribute \src "libresoc.v:139578.14-139578.41" + attribute \src "libresoc.v:142126.3-142135.6" + wire width 64 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:141210.14-141210.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:140436.3-140445.6" - wire width 64 $1\ldo_r$next[63:0]$6416 - attribute \src "libresoc.v:139608.14-139608.42" + attribute \src "libresoc.v:142068.3-142077.6" + wire width 64 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:141240.14-141240.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:139613.14-139613.62" + attribute \src "libresoc.v:141245.14-141245.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:140524.3-140532.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6436 - attribute \src "libresoc.v:139618.7-139618.34" + attribute \src "libresoc.v:142156.3-142164.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:141250.7-141250.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:140613.3-140624.6" + attribute \src "libresoc.v:142245.3-142256.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140384.3-140392.6" - wire $1\lsd_l_r_lsd$next[0:0]$6358 - attribute \src "libresoc.v:139667.7-139667.25" + attribute \src "libresoc.v:142016.3-142024.6" + wire $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:141299.7-141299.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:140312.3-140320.6" - wire $1\opc_l_r_opc$next[0:0]$6334 - attribute \src "libresoc.v:139681.7-139681.25" + attribute \src "libresoc.v:141944.3-141952.6" + wire $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141313.7-141313.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140303.3-140311.6" - wire $1\opc_l_s_opc$next[0:0]$6331 - attribute \src "libresoc.v:139685.7-139685.25" + attribute \src "libresoc.v:141935.3-141943.6" + wire $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141317.7-141317.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__byte_reverse$next[0:0]$6376 - attribute \src "libresoc.v:139816.7-139816.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__byte_reverse$next[0:0]$6424 + attribute \src "libresoc.v:141448.7-141448.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6377 - attribute \src "libresoc.v:139820.13-139820.36" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6425 + attribute \src "libresoc.v:141452.13-141452.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $1\oper_r__fn_unit$next[13:0]$6378 - attribute \src "libresoc.v:139839.14-139839.40" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 + attribute \src "libresoc.v:141471.14-141471.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6379 - attribute \src "libresoc.v:139843.14-139843.59" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 + attribute \src "libresoc.v:141475.14-141475.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6380 - attribute \src "libresoc.v:139847.7-139847.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6428 + attribute \src "libresoc.v:141479.7-141479.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $1\oper_r__insn$next[31:0]$6381 - attribute \src "libresoc.v:139851.14-139851.34" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $1\oper_r__insn$next[31:0]$6429 + attribute \src "libresoc.v:141483.14-141483.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6382 - attribute \src "libresoc.v:139930.13-139930.38" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6430 + attribute \src "libresoc.v:141562.13-141562.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__is_32bit$next[0:0]$6383 - attribute \src "libresoc.v:139934.7-139934.30" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_32bit$next[0:0]$6431 + attribute \src "libresoc.v:141566.7-141566.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__is_signed$next[0:0]$6384 - attribute \src "libresoc.v:139938.7-139938.31" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__is_signed$next[0:0]$6432 + attribute \src "libresoc.v:141570.7-141570.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6385 - attribute \src "libresoc.v:139947.13-139947.37" + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 + attribute \src "libresoc.v:141579.13-141579.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__oe__oe$next[0:0]$6386 - attribute \src "libresoc.v:139951.7-139951.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__oe$next[0:0]$6434 + attribute \src "libresoc.v:141583.7-141583.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__oe__ok$next[0:0]$6387 - attribute \src "libresoc.v:139955.7-139955.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__oe__ok$next[0:0]$6435 + attribute \src "libresoc.v:141587.7-141587.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__rc__ok$next[0:0]$6388 - attribute \src "libresoc.v:139959.7-139959.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__ok$next[0:0]$6436 + attribute \src "libresoc.v:141591.7-141591.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__rc__rc$next[0:0]$6389 - attribute \src "libresoc.v:139963.7-139963.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__rc__rc$next[0:0]$6437 + attribute \src "libresoc.v:141595.7-141595.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__sign_extend$next[0:0]$6390 - attribute \src "libresoc.v:139967.7-139967.33" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__sign_extend$next[0:0]$6438 + attribute \src "libresoc.v:141599.7-141599.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $1\oper_r__zero_a$next[0:0]$6391 - attribute \src "libresoc.v:139971.7-139971.28" + attribute \src "libresoc.v:142025.3-142067.6" + wire $1\oper_r__zero_a$next[0:0]$6439 + attribute \src "libresoc.v:141603.7-141603.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:139975.7-139975.21" + attribute \src "libresoc.v:141607.7-141607.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:140557.3-140568.6" + attribute \src "libresoc.v:142189.3-142200.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:140330.3-140338.6" - wire width 3 $1\src_l_r_src$next[2:0]$6340 - attribute \src "libresoc.v:140017.13-140017.31" + attribute \src "libresoc.v:141962.3-141970.6" + wire width 3 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141649.13-141649.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:140321.3-140329.6" - wire width 3 $1\src_l_s_src$next[2:0]$6337 - attribute \src "libresoc.v:140021.13-140021.31" + attribute \src "libresoc.v:141953.3-141961.6" + wire width 3 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141653.13-141653.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $1\src_r0$next[63:0]$6419 - attribute \src "libresoc.v:140025.14-140025.43" + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $1\src_r0$next[63:0]$6467 + attribute \src "libresoc.v:141657.14-141657.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $1\src_r1$next[63:0]$6423 - attribute \src "libresoc.v:140029.14-140029.43" + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $1\src_r1$next[63:0]$6471 + attribute \src "libresoc.v:141661.14-141661.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $1\src_r2$next[63:0]$6427 - attribute \src "libresoc.v:140033.14-140033.43" + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $1\src_r2$next[63:0]$6475 + attribute \src "libresoc.v:141665.14-141665.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:140375.3-140383.6" - wire $1\sto_l_r_sto$next[0:0]$6355 - attribute \src "libresoc.v:140043.7-140043.25" + attribute \src "libresoc.v:142007.3-142015.6" + wire $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:141675.7-141675.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:140366.3-140374.6" - wire $1\upd_l_r_upd$next[0:0]$6352 - attribute \src "libresoc.v:140053.7-140053.25" + attribute \src "libresoc.v:141998.3-142006.6" + wire $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141685.7-141685.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:140357.3-140365.6" - wire $1\upd_l_s_upd$next[0:0]$6349 - attribute \src "libresoc.v:140057.7-140057.25" + attribute \src "libresoc.v:141989.3-141997.6" + wire $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141689.7-141689.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:140348.3-140356.6" - wire $1\wri_l_r_wri$next[0:0]$6346 - attribute \src "libresoc.v:140067.7-140067.25" + attribute \src "libresoc.v:141980.3-141988.6" + wire $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141699.7-141699.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:140569.3-140588.6" + attribute \src "libresoc.v:142201.3-142220.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:140533.3-140556.6" + attribute \src "libresoc.v:142165.3-142188.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__byte_reverse$next[0:0]$6392 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6393 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 14 $2\oper_r__fn_unit$next[13:0]$6394 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6395 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6396 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 32 $2\oper_r__insn$next[31:0]$6397 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6398 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__is_32bit$next[0:0]$6399 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__is_signed$next[0:0]$6400 - attribute \src "libresoc.v:140393.3-140435.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6401 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__oe__oe$next[0:0]$6402 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__oe__ok$next[0:0]$6403 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__rc__ok$next[0:0]$6404 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__rc__rc$next[0:0]$6405 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__sign_extend$next[0:0]$6406 - attribute \src "libresoc.v:140393.3-140435.6" - wire $2\oper_r__zero_a$next[0:0]$6407 - attribute \src "libresoc.v:140446.3-140461.6" - wire width 64 $2\src_r0$next[63:0]$6420 - attribute \src "libresoc.v:140462.3-140477.6" - wire width 64 $2\src_r1$next[63:0]$6424 - attribute \src "libresoc.v:140478.3-140493.6" - wire width 64 $2\src_r2$next[63:0]$6428 - attribute \src "libresoc.v:140589.3-140612.6" + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__byte_reverse$next[0:0]$6440 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6441 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6444 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 32 $2\oper_r__insn$next[31:0]$6445 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6446 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_32bit$next[0:0]$6447 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__is_signed$next[0:0]$6448 + attribute \src "libresoc.v:142025.3-142067.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__oe$next[0:0]$6450 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__oe__ok$next[0:0]$6451 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__ok$next[0:0]$6452 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__rc__rc$next[0:0]$6453 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__sign_extend$next[0:0]$6454 + attribute \src "libresoc.v:142025.3-142067.6" + wire $2\oper_r__zero_a$next[0:0]$6455 + attribute \src "libresoc.v:142078.3-142093.6" + wire width 64 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142094.3-142109.6" + wire width 64 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142110.3-142125.6" + wire width 64 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142221.3-142244.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:140393.3-140435.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6408 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6409 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__oe__oe$next[0:0]$6410 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__oe__ok$next[0:0]$6411 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__rc__ok$next[0:0]$6412 - attribute \src "libresoc.v:140393.3-140435.6" - wire $3\oper_r__rc__rc$next[0:0]$6413 - attribute \src "libresoc.v:140149.18-140149.124" - wire width 65 $add$libresoc.v:140149$6280_Y - attribute \src "libresoc.v:140072.19-140072.118" - wire $and$libresoc.v:140072$6200_Y - attribute \src "libresoc.v:140073.19-140073.125" - wire $and$libresoc.v:140073$6201_Y - attribute \src "libresoc.v:140074.19-140074.120" - wire $and$libresoc.v:140074$6202_Y - attribute \src "libresoc.v:140075.19-140075.125" - wire $and$libresoc.v:140075$6203_Y - attribute \src "libresoc.v:140076.19-140076.118" - wire $and$libresoc.v:140076$6204_Y - attribute \src "libresoc.v:140078.19-140078.119" - wire $and$libresoc.v:140078$6206_Y - attribute \src "libresoc.v:140079.19-140079.123" - wire $and$libresoc.v:140079$6207_Y - attribute \src "libresoc.v:140080.19-140080.123" - wire $and$libresoc.v:140080$6208_Y - attribute \src "libresoc.v:140081.19-140081.120" - wire $and$libresoc.v:140081$6209_Y - attribute \src "libresoc.v:140082.19-140082.123" - wire $and$libresoc.v:140082$6210_Y - attribute \src "libresoc.v:140083.19-140083.119" - wire $and$libresoc.v:140083$6211_Y - attribute \src "libresoc.v:140084.19-140084.123" - wire $and$libresoc.v:140084$6212_Y - attribute \src "libresoc.v:140085.19-140085.125" - wire $and$libresoc.v:140085$6213_Y - attribute \src "libresoc.v:140087.19-140087.116" - wire $and$libresoc.v:140087$6215_Y - attribute \src "libresoc.v:140089.19-140089.120" - wire $and$libresoc.v:140089$6217_Y - attribute \src "libresoc.v:140090.19-140090.123" - wire $and$libresoc.v:140090$6218_Y - attribute \src "libresoc.v:140094.19-140094.125" - wire $and$libresoc.v:140094$6222_Y - attribute \src "libresoc.v:140095.19-140095.123" - wire $and$libresoc.v:140095$6223_Y - attribute \src "libresoc.v:140100.19-140100.116" - wire $and$libresoc.v:140100$6228_Y - attribute \src "libresoc.v:140102.19-140102.116" - wire $and$libresoc.v:140102$6230_Y - attribute \src "libresoc.v:140105.19-140105.118" - wire $and$libresoc.v:140105$6233_Y - attribute \src "libresoc.v:140107.19-140107.125" - wire $and$libresoc.v:140107$6235_Y - attribute \src "libresoc.v:140110.19-140110.160" - wire width 3 $and$libresoc.v:140110$6238_Y - attribute \src "libresoc.v:140111.19-140111.122" - wire $and$libresoc.v:140111$6239_Y - attribute \src "libresoc.v:140112.19-140112.122" - wire $and$libresoc.v:140112$6240_Y - attribute \src "libresoc.v:140114.19-140114.122" - wire $and$libresoc.v:140114$6243_Y - attribute \src "libresoc.v:140126.18-140126.123" - wire $and$libresoc.v:140126$6257_Y - attribute \src "libresoc.v:140127.18-140127.123" - wire $and$libresoc.v:140127$6258_Y - attribute \src "libresoc.v:140129.18-140129.114" - wire $and$libresoc.v:140129$6260_Y - attribute \src "libresoc.v:140131.18-140131.113" - wire $and$libresoc.v:140131$6262_Y - attribute \src "libresoc.v:140134.18-140134.113" - wire $and$libresoc.v:140134$6265_Y - attribute \src "libresoc.v:140138.18-140138.113" - wire $and$libresoc.v:140138$6269_Y - attribute \src "libresoc.v:140141.18-140141.119" - wire $and$libresoc.v:140141$6272_Y - attribute \src "libresoc.v:140150.18-140150.150" - wire width 3 $and$libresoc.v:140150$6281_Y - attribute \src "libresoc.v:140152.18-140152.113" - wire width 3 $and$libresoc.v:140152$6283_Y - attribute \src "libresoc.v:140154.18-140154.113" - wire width 3 $and$libresoc.v:140154$6285_Y - attribute \src "libresoc.v:140155.18-140155.127" - wire $and$libresoc.v:140155$6286_Y - attribute \src "libresoc.v:140156.18-140156.117" - wire $and$libresoc.v:140156$6287_Y - attribute \src "libresoc.v:140161.18-140161.117" - wire $and$libresoc.v:140161$6292_Y - attribute \src "libresoc.v:140086.19-140086.127" - wire $eq$libresoc.v:140086$6214_Y - attribute \src "libresoc.v:140106.19-140106.127" - wire $eq$libresoc.v:140106$6234_Y - attribute \src "libresoc.v:140108.19-140108.127" - wire $eq$libresoc.v:140108$6236_Y - attribute \src "libresoc.v:140119.19-140119.126" - wire $eq$libresoc.v:140119$6249_Y - attribute \src "libresoc.v:140124.18-140124.127" - wire $eq$libresoc.v:140124$6255_Y - attribute \src "libresoc.v:140125.18-140125.127" - wire $eq$libresoc.v:140125$6256_Y - attribute \src "libresoc.v:140133.18-140133.126" - wire $eq$libresoc.v:140133$6264_Y - attribute \src "libresoc.v:140137.18-140137.126" - wire $eq$libresoc.v:140137$6268_Y - attribute \src "libresoc.v:140113.19-140113.110" - wire width 96 $extend$libresoc.v:140113$6241_Y - attribute \src "libresoc.v:140115.19-140115.116" - wire width 64 $extend$libresoc.v:140115$6244_Y - attribute \src "libresoc.v:140120.19-140120.102" - wire width 64 $extend$libresoc.v:140120$6250_Y - attribute \src "libresoc.v:140098.19-140098.109" - wire $not$libresoc.v:140098$6226_Y - attribute \src "libresoc.v:140103.19-140103.121" - wire $not$libresoc.v:140103$6231_Y - attribute \src "libresoc.v:140128.18-140128.112" - wire $not$libresoc.v:140128$6259_Y - attribute \src "libresoc.v:140130.18-140130.110" - wire $not$libresoc.v:140130$6261_Y - attribute \src "libresoc.v:140132.18-140132.120" - wire $not$libresoc.v:140132$6263_Y - attribute \src "libresoc.v:140136.18-140136.120" - wire $not$libresoc.v:140136$6267_Y - attribute \src "libresoc.v:140151.18-140151.143" - wire width 2 $not$libresoc.v:140151$6282_Y - attribute \src "libresoc.v:140153.18-140153.115" - wire width 3 $not$libresoc.v:140153$6284_Y - attribute \src "libresoc.v:140160.18-140160.107" - wire $not$libresoc.v:140160$6291_Y - attribute \src "libresoc.v:140162.18-140162.118" - wire $not$libresoc.v:140162$6293_Y - attribute \src "libresoc.v:140077.18-140077.124" - wire $or$libresoc.v:140077$6205_Y - attribute \src "libresoc.v:140088.18-140088.129" - wire $or$libresoc.v:140088$6216_Y - attribute \src "libresoc.v:140091.19-140091.123" - wire $or$libresoc.v:140091$6219_Y - attribute \src "libresoc.v:140092.19-140092.125" - wire $or$libresoc.v:140092$6220_Y - attribute \src "libresoc.v:140093.19-140093.125" - wire $or$libresoc.v:140093$6221_Y - attribute \src "libresoc.v:140096.19-140096.132" - wire $or$libresoc.v:140096$6224_Y - attribute \src "libresoc.v:140097.19-140097.126" - wire $or$libresoc.v:140097$6225_Y - attribute \src "libresoc.v:140099.18-140099.129" - wire $or$libresoc.v:140099$6227_Y - attribute \src "libresoc.v:140101.19-140101.125" - wire $or$libresoc.v:140101$6229_Y - attribute \src "libresoc.v:140104.19-140104.119" - wire $or$libresoc.v:140104$6232_Y - attribute \src "libresoc.v:140109.18-140109.126" - wire $or$libresoc.v:140109$6237_Y - attribute \src "libresoc.v:140117.18-140117.156" - wire width 3 $or$libresoc.v:140117$6247_Y - attribute \src "libresoc.v:140123.18-140123.126" - wire $or$libresoc.v:140123$6254_Y - attribute \src "libresoc.v:140135.18-140135.116" - wire $or$libresoc.v:140135$6266_Y - attribute \src "libresoc.v:140139.18-140139.116" - wire $or$libresoc.v:140139$6270_Y - attribute \src "libresoc.v:140140.18-140140.127" - wire width 2 $or$libresoc.v:140140$6271_Y - attribute \src "libresoc.v:140142.18-140142.118" - wire $or$libresoc.v:140142$6273_Y - attribute \src "libresoc.v:140143.18-140143.118" - wire $or$libresoc.v:140143$6274_Y - attribute \src "libresoc.v:140144.18-140144.114" - wire $or$libresoc.v:140144$6275_Y - attribute \src "libresoc.v:140157.17-140157.124" - wire $or$libresoc.v:140157$6288_Y - attribute \src "libresoc.v:140158.18-140158.132" - wire $or$libresoc.v:140158$6289_Y - attribute \src "libresoc.v:140159.18-140159.134" - wire $or$libresoc.v:140159$6290_Y - attribute \src "libresoc.v:140113.19-140113.110" - wire width 96 $pos$libresoc.v:140113$6242_Y - attribute \src "libresoc.v:140115.19-140115.116" - wire width 64 $pos$libresoc.v:140115$6245_Y - attribute \src "libresoc.v:140116.19-140116.148" - wire width 64 $pos$libresoc.v:140116$6246_Y - attribute \src "libresoc.v:140118.19-140118.206" - wire width 64 $pos$libresoc.v:140118$6248_Y - attribute \src "libresoc.v:140120.19-140120.102" - wire width 64 $pos$libresoc.v:140120$6251_Y - attribute \src "libresoc.v:140121.19-140121.120" - wire width 64 $pos$libresoc.v:140121$6252_Y - attribute \src "libresoc.v:140122.19-140122.150" - wire width 64 $pos$libresoc.v:140122$6253_Y - attribute \src "libresoc.v:140145.18-140145.107" - wire width 64 $ternary$libresoc.v:140145$6276_Y - attribute \src "libresoc.v:140146.18-140146.112" - wire width 64 $ternary$libresoc.v:140146$6277_Y - attribute \src "libresoc.v:140147.18-140147.147" - wire width 64 $ternary$libresoc.v:140147$6278_Y - attribute \src "libresoc.v:140148.18-140148.155" - wire width 64 $ternary$libresoc.v:140148$6279_Y + attribute \src "libresoc.v:142025.3-142067.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6457 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__oe$next[0:0]$6458 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__oe__ok$next[0:0]$6459 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__ok$next[0:0]$6460 + attribute \src "libresoc.v:142025.3-142067.6" + wire $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:141781.18-141781.124" + wire width 65 $add$libresoc.v:141781$6328_Y + attribute \src "libresoc.v:141704.19-141704.118" + wire $and$libresoc.v:141704$6248_Y + attribute \src "libresoc.v:141705.19-141705.125" + wire $and$libresoc.v:141705$6249_Y + attribute \src "libresoc.v:141706.19-141706.120" + wire $and$libresoc.v:141706$6250_Y + attribute \src "libresoc.v:141707.19-141707.125" + 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$or$libresoc.v:141790$6337_Y + attribute \src "libresoc.v:141791.18-141791.134" + wire $or$libresoc.v:141791$6338_Y + attribute \src "libresoc.v:141745.19-141745.110" + wire width 96 $pos$libresoc.v:141745$6290_Y + attribute \src "libresoc.v:141747.19-141747.116" + wire width 64 $pos$libresoc.v:141747$6293_Y + attribute \src "libresoc.v:141748.19-141748.148" + wire width 64 $pos$libresoc.v:141748$6294_Y + attribute \src "libresoc.v:141750.19-141750.206" + wire width 64 $pos$libresoc.v:141750$6296_Y + attribute \src "libresoc.v:141752.19-141752.102" + wire width 64 $pos$libresoc.v:141752$6299_Y + attribute \src "libresoc.v:141753.19-141753.120" + wire width 64 $pos$libresoc.v:141753$6300_Y + attribute \src "libresoc.v:141754.19-141754.150" + wire width 64 $pos$libresoc.v:141754$6301_Y + attribute \src "libresoc.v:141777.18-141777.107" + wire width 64 $ternary$libresoc.v:141777$6324_Y + attribute \src "libresoc.v:141778.18-141778.112" + wire width 64 $ternary$libresoc.v:141778$6325_Y + attribute \src "libresoc.v:141779.18-141779.147" + wire width 64 $ternary$libresoc.v:141779$6326_Y + attribute \src "libresoc.v:141780.18-141780.155" + wire width 64 $ternary$libresoc.v:141780$6327_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -224226,9 +226723,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -224286,7 +226783,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:139322.7-139322.15" + attribute \src "libresoc.v:140954.7-140954.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -224761,7 +227258,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:140149$6280 + cell $add $add$libresoc.v:141781$6328 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -224769,10 +227266,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:140149$6280_Y + connect \Y $add$libresoc.v:141781$6328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:140072$6200 + cell $and $and$libresoc.v:141704$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224780,10 +227277,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:140072$6200_Y + connect \Y $and$libresoc.v:141704$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:140073$6201 + cell $and $and$libresoc.v:141705$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224791,10 +227288,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:140073$6201_Y + connect \Y $and$libresoc.v:141705$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:140074$6202 + cell $and $and$libresoc.v:141706$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224802,10 +227299,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140074$6202_Y + connect \Y $and$libresoc.v:141706$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140075$6203 + cell $and $and$libresoc.v:141707$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224813,10 +227310,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:140075$6203_Y + connect \Y $and$libresoc.v:141707$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140076$6204 + cell $and $and$libresoc.v:141708$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224824,10 +227321,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:140076$6204_Y + connect \Y $and$libresoc.v:141708$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:140078$6206 + cell $and $and$libresoc.v:141710$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224835,10 +227332,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:140078$6206_Y + connect \Y $and$libresoc.v:141710$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:140079$6207 + cell $and $and$libresoc.v:141711$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224846,10 +227343,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140079$6207_Y + connect \Y $and$libresoc.v:141711$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140080$6208 + cell $and $and$libresoc.v:141712$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224857,10 +227354,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:140080$6208_Y + connect \Y $and$libresoc.v:141712$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140081$6209 + cell $and $and$libresoc.v:141713$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224868,10 +227365,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:140081$6209_Y + connect \Y $and$libresoc.v:141713$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140082$6210 + cell $and $and$libresoc.v:141714$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224879,10 +227376,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:140082$6210_Y + connect \Y $and$libresoc.v:141714$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140083$6211 + cell $and $and$libresoc.v:141715$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224890,10 +227387,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:140083$6211_Y + connect \Y $and$libresoc.v:141715$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:140084$6212 + cell $and $and$libresoc.v:141716$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224901,10 +227398,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140084$6212_Y + connect \Y $and$libresoc.v:141716$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140085$6213 + cell $and $and$libresoc.v:141717$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224912,10 +227409,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:140085$6213_Y + connect \Y $and$libresoc.v:141717$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140087$6215 + cell $and $and$libresoc.v:141719$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224923,10 +227420,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:140087$6215_Y + connect \Y $and$libresoc.v:141719$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140089$6217 + cell $and $and$libresoc.v:141721$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224934,10 +227431,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:140089$6217_Y + connect \Y $and$libresoc.v:141721$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:140090$6218 + cell $and $and$libresoc.v:141722$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224945,10 +227442,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140090$6218_Y + connect \Y $and$libresoc.v:141722$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140094$6222 + cell $and $and$libresoc.v:141726$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224956,10 +227453,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:140094$6222_Y + connect \Y $and$libresoc.v:141726$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140095$6223 + cell $and $and$libresoc.v:141727$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224967,10 +227464,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:140095$6223_Y + connect \Y $and$libresoc.v:141727$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:140100$6228 + cell $and $and$libresoc.v:141732$6276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224978,10 +227475,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:140100$6228_Y + connect \Y $and$libresoc.v:141732$6276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:140102$6230 + cell $and $and$libresoc.v:141734$6278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -224989,10 +227486,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:140102$6230_Y + connect \Y $and$libresoc.v:141734$6278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:140105$6233 + cell $and $and$libresoc.v:141737$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225000,10 +227497,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:140105$6233_Y + connect \Y $and$libresoc.v:141737$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:140107$6235 + cell $and $and$libresoc.v:141739$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225011,10 +227508,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:140107$6235_Y + connect \Y $and$libresoc.v:141739$6283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:140110$6238 + cell $and $and$libresoc.v:141742$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225022,10 +227519,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:140110$6238_Y + connect \Y $and$libresoc.v:141742$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:140111$6239 + cell $and $and$libresoc.v:141743$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225033,10 +227530,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:140111$6239_Y + connect \Y $and$libresoc.v:141743$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:140112$6240 + cell $and $and$libresoc.v:141744$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225044,10 +227541,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:140112$6240_Y + connect \Y $and$libresoc.v:141744$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:140114$6243 + cell $and $and$libresoc.v:141746$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225055,10 +227552,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:140114$6243_Y + connect \Y $and$libresoc.v:141746$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:140126$6257 + cell $and $and$libresoc.v:141758$6305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225066,10 +227563,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:140126$6257_Y + connect \Y $and$libresoc.v:141758$6305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:140127$6258 + cell $and $and$libresoc.v:141759$6306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225077,10 +227574,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:140127$6258_Y + connect \Y $and$libresoc.v:141759$6306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:140129$6260 + cell $and $and$libresoc.v:141761$6308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225088,10 +227585,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:140129$6260_Y + connect \Y $and$libresoc.v:141761$6308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:140131$6262 + cell $and $and$libresoc.v:141763$6310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225099,10 +227596,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:140131$6262_Y + connect \Y $and$libresoc.v:141763$6310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:140134$6265 + cell $and $and$libresoc.v:141766$6313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225110,10 +227607,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:140134$6265_Y + connect \Y $and$libresoc.v:141766$6313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:140138$6269 + cell $and $and$libresoc.v:141770$6317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225121,10 +227618,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:140138$6269_Y + connect \Y $and$libresoc.v:141770$6317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:140141$6272 + cell $and $and$libresoc.v:141773$6320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225132,10 +227629,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:140141$6272_Y + connect \Y $and$libresoc.v:141773$6320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140150$6281 + cell $and $and$libresoc.v:141782$6329 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225143,10 +227640,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:140150$6281_Y + connect \Y $and$libresoc.v:141782$6329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140152$6283 + cell $and $and$libresoc.v:141784$6331 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225154,10 +227651,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:140152$6283_Y + connect \Y $and$libresoc.v:141784$6331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:140154$6285 + cell $and $and$libresoc.v:141786$6333 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225165,10 +227662,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:140154$6285_Y + connect \Y $and$libresoc.v:141786$6333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:140155$6286 + cell $and $and$libresoc.v:141787$6334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225176,10 +227673,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:140155$6286_Y + connect \Y $and$libresoc.v:141787$6334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:140156$6287 + cell $and $and$libresoc.v:141788$6335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225187,10 +227684,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:140156$6287_Y + connect \Y $and$libresoc.v:141788$6335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:140161$6292 + cell $and $and$libresoc.v:141793$6340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225198,10 +227695,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:140161$6292_Y + connect \Y $and$libresoc.v:141793$6340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140086$6214 + cell $eq $eq$libresoc.v:141718$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225209,10 +227706,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140086$6214_Y + connect \Y $eq$libresoc.v:141718$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140106$6234 + cell $eq $eq$libresoc.v:141738$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225220,10 +227717,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140106$6234_Y + connect \Y $eq$libresoc.v:141738$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140108$6236 + cell $eq $eq$libresoc.v:141740$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225231,10 +227728,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140108$6236_Y + connect \Y $eq$libresoc.v:141740$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:140119$6249 + cell $eq $eq$libresoc.v:141751$6297 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -225242,10 +227739,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:140119$6249_Y + connect \Y $eq$libresoc.v:141751$6297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:140124$6255 + cell $eq $eq$libresoc.v:141756$6303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225253,10 +227750,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:140124$6255_Y + connect \Y $eq$libresoc.v:141756$6303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:140125$6256 + cell $eq $eq$libresoc.v:141757$6304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -225264,10 +227761,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:140125$6256_Y + connect \Y $eq$libresoc.v:141757$6304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140133$6264 + cell $eq $eq$libresoc.v:141765$6312 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225275,10 +227772,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140133$6264_Y + connect \Y $eq$libresoc.v:141765$6312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:140137$6268 + cell $eq $eq$libresoc.v:141769$6316 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -225286,114 +227783,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:140137$6268_Y + connect \Y $eq$libresoc.v:141769$6316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:140113$6241 + cell $pos $extend$libresoc.v:141745$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:140113$6241_Y + connect \Y $extend$libresoc.v:141745$6289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:140115$6244 + cell $pos $extend$libresoc.v:141747$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:140115$6244_Y + connect \Y $extend$libresoc.v:141747$6292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:140120$6250 + cell $pos $extend$libresoc.v:141752$6298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:140120$6250_Y + connect \Y $extend$libresoc.v:141752$6298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:140098$6226 + cell $not $not$libresoc.v:141730$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:140098$6226_Y + connect \Y $not$libresoc.v:141730$6274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:140103$6231 + cell $not $not$libresoc.v:141735$6279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140103$6231_Y + connect \Y $not$libresoc.v:141735$6279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:140128$6259 + cell $not $not$libresoc.v:141760$6307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:140128$6259_Y + connect \Y $not$libresoc.v:141760$6307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:140130$6261 + cell $not $not$libresoc.v:141762$6309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:140130$6261_Y + connect \Y $not$libresoc.v:141762$6309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:140132$6263 + cell $not $not$libresoc.v:141764$6311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140132$6263_Y + connect \Y $not$libresoc.v:141764$6311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:140136$6267 + cell $not $not$libresoc.v:141768$6315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:140136$6267_Y + connect \Y $not$libresoc.v:141768$6315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:140151$6282 + cell $not $not$libresoc.v:141783$6330 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:140151$6282_Y + connect \Y $not$libresoc.v:141783$6330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:140153$6284 + cell $not $not$libresoc.v:141785$6332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:140153$6284_Y + connect \Y $not$libresoc.v:141785$6332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:140160$6291 + cell $not $not$libresoc.v:141792$6339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:140160$6291_Y + connect \Y $not$libresoc.v:141792$6339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:140162$6293 + cell $not $not$libresoc.v:141794$6341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:140162$6293_Y + connect \Y $not$libresoc.v:141794$6341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:140077$6205 + cell $or $or$libresoc.v:141709$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225401,10 +227898,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140077$6205_Y + connect \Y $or$libresoc.v:141709$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:140088$6216 + cell $or $or$libresoc.v:141720$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225412,10 +227909,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140088$6216_Y + connect \Y $or$libresoc.v:141720$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140091$6219 + cell $or $or$libresoc.v:141723$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225423,10 +227920,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:140091$6219_Y + connect \Y $or$libresoc.v:141723$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140092$6220 + cell $or $or$libresoc.v:141724$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225434,10 +227931,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:140092$6220_Y + connect \Y $or$libresoc.v:141724$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:140093$6221 + cell $or $or$libresoc.v:141725$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225445,10 +227942,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:140093$6221_Y + connect \Y $or$libresoc.v:141725$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:140096$6224 + cell $or $or$libresoc.v:141728$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225456,10 +227953,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:140096$6224_Y + connect \Y $or$libresoc.v:141728$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:140097$6225 + cell $or $or$libresoc.v:141729$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225467,10 +227964,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:140097$6225_Y + connect \Y $or$libresoc.v:141729$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:140099$6227 + cell $or $or$libresoc.v:141731$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225478,10 +227975,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140099$6227_Y + connect \Y $or$libresoc.v:141731$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:140101$6229 + cell $or $or$libresoc.v:141733$6277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225489,10 +227986,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:140101$6229_Y + connect \Y $or$libresoc.v:141733$6277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:140104$6232 + cell $or $or$libresoc.v:141736$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225500,10 +227997,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:140104$6232_Y + connect \Y $or$libresoc.v:141736$6280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:140109$6237 + cell $or $or$libresoc.v:141741$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225511,10 +228008,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140109$6237_Y + connect \Y $or$libresoc.v:141741$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:140117$6247 + cell $or $or$libresoc.v:141749$6295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -225522,10 +228019,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140117$6247_Y + connect \Y $or$libresoc.v:141749$6295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:140123$6254 + cell $or $or$libresoc.v:141755$6302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225533,10 +228030,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140123$6254_Y + connect \Y $or$libresoc.v:141755$6302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:140135$6266 + cell $or $or$libresoc.v:141767$6314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225544,10 +228041,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:140135$6266_Y + connect \Y $or$libresoc.v:141767$6314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:140139$6270 + cell $or $or$libresoc.v:141771$6318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225555,10 +228052,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:140139$6270_Y + connect \Y $or$libresoc.v:141771$6318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:140140$6271 + cell $or $or$libresoc.v:141772$6319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225566,10 +228063,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:140140$6271_Y + connect \Y $or$libresoc.v:141772$6319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:140142$6273 + cell $or $or$libresoc.v:141774$6321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225577,10 +228074,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:140142$6273_Y + connect \Y $or$libresoc.v:141774$6321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:140143$6274 + cell $or $or$libresoc.v:141775$6322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225588,10 +228085,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:140143$6274_Y + connect \Y $or$libresoc.v:141775$6322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:140144$6275 + cell $or $or$libresoc.v:141776$6323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225599,10 +228096,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:140144$6275_Y + connect \Y $or$libresoc.v:141776$6323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:140157$6288 + cell $or $or$libresoc.v:141789$6336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225610,10 +228107,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140157$6288_Y + connect \Y $or$libresoc.v:141789$6336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:140158$6289 + cell $or $or$libresoc.v:141790$6337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225621,10 +228118,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:140158$6289_Y + connect \Y $or$libresoc.v:141790$6337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:140159$6290 + cell $or $or$libresoc.v:141791$6338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225632,98 +228129,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:140159$6290_Y + connect \Y $or$libresoc.v:141791$6338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:140113$6242 + cell $pos $pos$libresoc.v:141745$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:140113$6241_Y - connect \Y $pos$libresoc.v:140113$6242_Y + connect \A $extend$libresoc.v:141745$6289_Y + connect \Y $pos$libresoc.v:141745$6290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140115$6245 + cell $pos $pos$libresoc.v:141747$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:140115$6244_Y - connect \Y $pos$libresoc.v:140115$6245_Y + connect \A $extend$libresoc.v:141747$6292_Y + connect \Y $pos$libresoc.v:141747$6293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140116$6246 + cell $pos $pos$libresoc.v:141748$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:140116$6246_Y + connect \Y $pos$libresoc.v:141748$6294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140118$6248 + cell $pos $pos$libresoc.v:141750$6296 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:140118$6248_Y + connect \Y $pos$libresoc.v:141750$6296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140120$6251 + cell $pos $pos$libresoc.v:141752$6299 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:140120$6250_Y - connect \Y $pos$libresoc.v:140120$6251_Y + connect \A $extend$libresoc.v:141752$6298_Y + connect \Y $pos$libresoc.v:141752$6299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140121$6252 + cell $pos $pos$libresoc.v:141753$6300 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:140121$6252_Y + connect \Y $pos$libresoc.v:141753$6300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:140122$6253 + cell $pos $pos$libresoc.v:141754$6301 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:140122$6253_Y + connect \Y $pos$libresoc.v:141754$6301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140145$6276 + cell $mux $ternary$libresoc.v:141777$6324 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:140145$6276_Y + connect \Y $ternary$libresoc.v:141777$6324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140146$6277 + cell $mux $ternary$libresoc.v:141778$6325 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:140146$6277_Y + connect \Y $ternary$libresoc.v:141778$6325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:140147$6278 + cell $mux $ternary$libresoc.v:141779$6326 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:140147$6278_Y + connect \Y $ternary$libresoc.v:141779$6326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:140148$6279 + cell $mux $ternary$libresoc.v:141780$6327 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:140148$6279_Y + connect \Y $ternary$libresoc.v:141780$6327_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140233.9-140239.4" + attribute \src "libresoc.v:141865.9-141871.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225732,7 +228229,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:140240.15-140246.4" + attribute \src "libresoc.v:141872.15-141878.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225741,7 +228238,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:140247.9-140253.4" + attribute \src "libresoc.v:141879.9-141885.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225750,7 +228247,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:140254.9-140260.4" + attribute \src "libresoc.v:141886.9-141892.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225759,7 +228256,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:140261.15-140267.4" + attribute \src "libresoc.v:141893.15-141899.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225768,7 +228265,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:140268.15-140274.4" + attribute \src "libresoc.v:141900.15-141906.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225777,7 +228274,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:140275.15-140281.4" + attribute \src "libresoc.v:141907.15-141913.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225786,7 +228283,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:140282.9-140288.4" + attribute \src "libresoc.v:141914.9-141920.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225795,7 +228292,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:140289.9-140295.4" + attribute \src "libresoc.v:141921.9-141927.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225804,7 +228301,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:140296.9-140302.4" + attribute \src "libresoc.v:141928.9-141934.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225812,547 +228309,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:139322.7-139322.20" - process $proc$libresoc.v:139322$6442 + attribute \src "libresoc.v:140954.7-140954.20" + process $proc$libresoc.v:140954$6490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139518.7-139518.25" - process $proc$libresoc.v:139518$6443 + attribute \src "libresoc.v:141150.7-141150.25" + process $proc$libresoc.v:141150$6491 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:139532.7-139532.20" - process $proc$libresoc.v:139532$6444 + attribute \src "libresoc.v:141164.7-141164.20" + process $proc$libresoc.v:141164$6492 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:139578.14-139578.41" - process $proc$libresoc.v:139578$6445 + attribute \src "libresoc.v:141210.14-141210.41" + process $proc$libresoc.v:141210$6493 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:139608.14-139608.42" - process $proc$libresoc.v:139608$6446 + attribute \src "libresoc.v:141240.14-141240.42" + process $proc$libresoc.v:141240$6494 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:139613.14-139613.62" - process $proc$libresoc.v:139613$6447 + attribute \src "libresoc.v:141245.14-141245.62" + process $proc$libresoc.v:141245$6495 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:139618.7-139618.34" - process $proc$libresoc.v:139618$6448 + attribute \src "libresoc.v:141250.7-141250.34" + process $proc$libresoc.v:141250$6496 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:139667.7-139667.25" - process $proc$libresoc.v:139667$6449 + attribute \src "libresoc.v:141299.7-141299.25" + process $proc$libresoc.v:141299$6497 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:139681.7-139681.25" - process $proc$libresoc.v:139681$6450 + attribute \src "libresoc.v:141313.7-141313.25" + process $proc$libresoc.v:141313$6498 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:139685.7-139685.25" - process $proc$libresoc.v:139685$6451 + attribute \src "libresoc.v:141317.7-141317.25" + process $proc$libresoc.v:141317$6499 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:139816.7-139816.34" - process $proc$libresoc.v:139816$6452 + attribute \src "libresoc.v:141448.7-141448.34" + process $proc$libresoc.v:141448$6500 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:139820.13-139820.36" - process $proc$libresoc.v:139820$6453 + attribute \src "libresoc.v:141452.13-141452.36" + process $proc$libresoc.v:141452$6501 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:139839.14-139839.40" - process $proc$libresoc.v:139839$6454 + attribute \src "libresoc.v:141471.14-141471.40" + process $proc$libresoc.v:141471$6502 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:139843.14-139843.59" - process $proc$libresoc.v:139843$6455 + attribute \src "libresoc.v:141475.14-141475.59" + process $proc$libresoc.v:141475$6503 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:139847.7-139847.34" - process $proc$libresoc.v:139847$6456 + attribute \src "libresoc.v:141479.7-141479.34" + process $proc$libresoc.v:141479$6504 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:139851.14-139851.34" - process $proc$libresoc.v:139851$6457 + attribute \src "libresoc.v:141483.14-141483.34" + process $proc$libresoc.v:141483$6505 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:139930.13-139930.38" - process $proc$libresoc.v:139930$6458 + attribute \src "libresoc.v:141562.13-141562.38" + process $proc$libresoc.v:141562$6506 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:139934.7-139934.30" - process $proc$libresoc.v:139934$6459 + attribute \src "libresoc.v:141566.7-141566.30" + process $proc$libresoc.v:141566$6507 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:139938.7-139938.31" - process $proc$libresoc.v:139938$6460 + attribute \src "libresoc.v:141570.7-141570.31" + process $proc$libresoc.v:141570$6508 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:139947.13-139947.37" - process $proc$libresoc.v:139947$6461 + attribute \src "libresoc.v:141579.13-141579.37" + process $proc$libresoc.v:141579$6509 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:139951.7-139951.28" - process $proc$libresoc.v:139951$6462 + attribute \src "libresoc.v:141583.7-141583.28" + process $proc$libresoc.v:141583$6510 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:139955.7-139955.28" - process $proc$libresoc.v:139955$6463 + attribute \src "libresoc.v:141587.7-141587.28" + process $proc$libresoc.v:141587$6511 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:139959.7-139959.28" - process $proc$libresoc.v:139959$6464 + attribute \src "libresoc.v:141591.7-141591.28" + process $proc$libresoc.v:141591$6512 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:139963.7-139963.28" - process $proc$libresoc.v:139963$6465 + attribute \src "libresoc.v:141595.7-141595.28" + process $proc$libresoc.v:141595$6513 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:139967.7-139967.33" - process $proc$libresoc.v:139967$6466 + attribute \src "libresoc.v:141599.7-141599.33" + process $proc$libresoc.v:141599$6514 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:139971.7-139971.28" - process $proc$libresoc.v:139971$6467 + attribute \src "libresoc.v:141603.7-141603.28" + process $proc$libresoc.v:141603$6515 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:139975.7-139975.21" - process $proc$libresoc.v:139975$6468 + attribute \src "libresoc.v:141607.7-141607.21" + process $proc$libresoc.v:141607$6516 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:140017.13-140017.31" - process $proc$libresoc.v:140017$6469 + attribute \src "libresoc.v:141649.13-141649.31" + process $proc$libresoc.v:141649$6517 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:140021.13-140021.31" - process $proc$libresoc.v:140021$6470 + attribute \src "libresoc.v:141653.13-141653.31" + process $proc$libresoc.v:141653$6518 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:140025.14-140025.43" - process $proc$libresoc.v:140025$6471 + attribute \src "libresoc.v:141657.14-141657.43" + process $proc$libresoc.v:141657$6519 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:140029.14-140029.43" - process $proc$libresoc.v:140029$6472 + attribute \src "libresoc.v:141661.14-141661.43" + process $proc$libresoc.v:141661$6520 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:140033.14-140033.43" - process $proc$libresoc.v:140033$6473 + attribute \src "libresoc.v:141665.14-141665.43" + process $proc$libresoc.v:141665$6521 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:140043.7-140043.25" - process $proc$libresoc.v:140043$6474 + attribute \src "libresoc.v:141675.7-141675.25" + process $proc$libresoc.v:141675$6522 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:140053.7-140053.25" - process $proc$libresoc.v:140053$6475 + attribute \src "libresoc.v:141685.7-141685.25" + process $proc$libresoc.v:141685$6523 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:140057.7-140057.25" - process $proc$libresoc.v:140057$6476 + attribute \src "libresoc.v:141689.7-141689.25" + process $proc$libresoc.v:141689$6524 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:140067.7-140067.25" - process $proc$libresoc.v:140067$6477 + attribute \src "libresoc.v:141699.7-141699.25" + process $proc$libresoc.v:141699$6525 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:140163.3-140164.57" - process $proc$libresoc.v:140163$6294 + attribute \src "libresoc.v:141795.3-141796.57" + process $proc$libresoc.v:141795$6342 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:140165.3-140166.33" - process $proc$libresoc.v:140165$6295 + attribute \src "libresoc.v:141797.3-141798.33" + process $proc$libresoc.v:141797$6343 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:140167.3-140168.21" - process $proc$libresoc.v:140167$6296 + attribute \src "libresoc.v:141799.3-141800.21" + process $proc$libresoc.v:141799$6344 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:140169.3-140170.25" - process $proc$libresoc.v:140169$6297 + attribute \src "libresoc.v:141801.3-141802.25" + process $proc$libresoc.v:141801$6345 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:140171.3-140172.29" - process $proc$libresoc.v:140171$6298 + attribute \src "libresoc.v:141803.3-141804.29" + process $proc$libresoc.v:141803$6346 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:140173.3-140174.29" - process $proc$libresoc.v:140173$6299 + attribute \src "libresoc.v:141805.3-141806.29" + process $proc$libresoc.v:141805$6347 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:140175.3-140176.29" - process $proc$libresoc.v:140175$6300 + attribute \src "libresoc.v:141807.3-141808.29" + process $proc$libresoc.v:141807$6348 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:140177.3-140178.27" - process $proc$libresoc.v:140177$6301 + attribute \src "libresoc.v:141809.3-141810.27" + process $proc$libresoc.v:141809$6349 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:140179.3-140180.51" - process $proc$libresoc.v:140179$6302 + attribute \src "libresoc.v:141811.3-141812.51" + process $proc$libresoc.v:141811$6350 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:140181.3-140182.47" - process $proc$libresoc.v:140181$6303 + attribute \src "libresoc.v:141813.3-141814.47" + process $proc$libresoc.v:141813$6351 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:140183.3-140184.61" - process $proc$libresoc.v:140183$6304 + attribute \src "libresoc.v:141815.3-141816.61" + process $proc$libresoc.v:141815$6352 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:140185.3-140186.57" - process $proc$libresoc.v:140185$6305 + attribute \src "libresoc.v:141817.3-141818.57" + process $proc$libresoc.v:141817$6353 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:140187.3-140188.45" - process $proc$libresoc.v:140187$6306 + attribute \src "libresoc.v:141819.3-141820.45" + process $proc$libresoc.v:141819$6354 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:140189.3-140190.45" - process $proc$libresoc.v:140189$6307 + attribute \src "libresoc.v:141821.3-141822.45" + process $proc$libresoc.v:141821$6355 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:140191.3-140192.45" - process $proc$libresoc.v:140191$6308 + attribute \src "libresoc.v:141823.3-141824.45" + process $proc$libresoc.v:141823$6356 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:140193.3-140194.45" - process $proc$libresoc.v:140193$6309 + attribute \src "libresoc.v:141825.3-141826.45" + process $proc$libresoc.v:141825$6357 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:140195.3-140196.45" - process $proc$libresoc.v:140195$6310 + attribute \src "libresoc.v:141827.3-141828.45" + process $proc$libresoc.v:141827$6358 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:140197.3-140198.49" - process $proc$libresoc.v:140197$6311 + attribute \src "libresoc.v:141829.3-141830.49" + process $proc$libresoc.v:141829$6359 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:140199.3-140200.51" - process $proc$libresoc.v:140199$6312 + attribute \src "libresoc.v:141831.3-141832.51" + process $proc$libresoc.v:141831$6360 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:140201.3-140202.49" - process $proc$libresoc.v:140201$6313 + attribute \src "libresoc.v:141833.3-141834.49" + process $proc$libresoc.v:141833$6361 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:140203.3-140204.57" - process $proc$libresoc.v:140203$6314 + attribute \src "libresoc.v:141835.3-141836.57" + process $proc$libresoc.v:141835$6362 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:140205.3-140206.55" - process $proc$libresoc.v:140205$6315 + attribute \src "libresoc.v:141837.3-141838.55" + process $proc$libresoc.v:141837$6363 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:140207.3-140208.51" - process $proc$libresoc.v:140207$6316 + attribute \src "libresoc.v:141839.3-141840.51" + process $proc$libresoc.v:141839$6364 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:140209.3-140210.41" - process $proc$libresoc.v:140209$6317 + attribute \src "libresoc.v:141841.3-141842.41" + process $proc$libresoc.v:141841$6365 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:140211.3-140212.39" - process $proc$libresoc.v:140211$6318 + attribute \src "libresoc.v:141843.3-141844.39" + process $proc$libresoc.v:141843$6366 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:140213.3-140214.39" - process $proc$libresoc.v:140213$6319 + attribute \src "libresoc.v:141845.3-141846.39" + process $proc$libresoc.v:141845$6367 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:140215.3-140216.39" - process $proc$libresoc.v:140215$6320 + attribute \src "libresoc.v:141847.3-141848.39" + process $proc$libresoc.v:141847$6368 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:140217.3-140218.39" - process $proc$libresoc.v:140217$6321 + attribute \src "libresoc.v:141849.3-141850.39" + process $proc$libresoc.v:141849$6369 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:140219.3-140220.39" - process $proc$libresoc.v:140219$6322 + attribute \src "libresoc.v:141851.3-141852.39" + process $proc$libresoc.v:141851$6370 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:140221.3-140222.39" - process $proc$libresoc.v:140221$6323 + attribute \src "libresoc.v:141853.3-141854.39" + process $proc$libresoc.v:141853$6371 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:140223.3-140224.39" - process $proc$libresoc.v:140223$6324 + attribute \src "libresoc.v:141855.3-141856.39" + process $proc$libresoc.v:141855$6372 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:140225.3-140226.39" - process $proc$libresoc.v:140225$6325 + attribute \src "libresoc.v:141857.3-141858.39" + process $proc$libresoc.v:141857$6373 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:140227.3-140228.39" - process $proc$libresoc.v:140227$6326 + attribute \src "libresoc.v:141859.3-141860.39" + process $proc$libresoc.v:141859$6374 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:140229.3-140230.39" - process $proc$libresoc.v:140229$6327 + attribute \src "libresoc.v:141861.3-141862.39" + process $proc$libresoc.v:141861$6375 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:140231.3-140232.28" - process $proc$libresoc.v:140231$6328 + attribute \src "libresoc.v:141863.3-141864.28" + process $proc$libresoc.v:141863$6376 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:140303.3-140311.6" - process $proc$libresoc.v:140303$6329 + attribute \src "libresoc.v:141935.3-141943.6" + process $proc$libresoc.v:141935$6377 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6330 $1\opc_l_s_opc$next[0:0]$6331 - attribute \src "libresoc.v:140304.5-140304.29" + assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 + attribute \src "libresoc.v:141936.5-141936.29" switch \initial - attribute \src "libresoc.v:140304.9-140304.17" + attribute \src "libresoc.v:141936.9-141936.17" case 1'1 case end @@ -226361,21 +228858,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6331 1'0 + assign $1\opc_l_s_opc$next[0:0]$6379 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6331 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6379 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6330 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 end - attribute \src "libresoc.v:140312.3-140320.6" - process $proc$libresoc.v:140312$6332 + attribute \src "libresoc.v:141944.3-141952.6" + process $proc$libresoc.v:141944$6380 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6333 $1\opc_l_r_opc$next[0:0]$6334 - attribute \src "libresoc.v:140313.5-140313.29" + assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 + attribute \src "libresoc.v:141945.5-141945.29" switch \initial - attribute \src "libresoc.v:140313.9-140313.17" + attribute \src "libresoc.v:141945.9-141945.17" case 1'1 case end @@ -226384,21 +228881,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6334 1'1 + assign $1\opc_l_r_opc$next[0:0]$6382 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6334 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6382 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6333 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 end - attribute \src "libresoc.v:140321.3-140329.6" - process $proc$libresoc.v:140321$6335 + attribute \src "libresoc.v:141953.3-141961.6" + process $proc$libresoc.v:141953$6383 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6336 $1\src_l_s_src$next[2:0]$6337 - attribute \src "libresoc.v:140322.5-140322.29" + assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 + attribute \src "libresoc.v:141954.5-141954.29" switch \initial - attribute \src "libresoc.v:140322.9-140322.17" + attribute \src "libresoc.v:141954.9-141954.17" case 1'1 case end @@ -226407,21 +228904,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6337 3'000 + assign $1\src_l_s_src$next[2:0]$6385 3'000 case - assign $1\src_l_s_src$next[2:0]$6337 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6385 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6336 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 end - attribute \src "libresoc.v:140330.3-140338.6" - process $proc$libresoc.v:140330$6338 + attribute \src "libresoc.v:141962.3-141970.6" + process $proc$libresoc.v:141962$6386 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6339 $1\src_l_r_src$next[2:0]$6340 - attribute \src "libresoc.v:140331.5-140331.29" + assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 + attribute \src "libresoc.v:141963.5-141963.29" switch \initial - attribute \src "libresoc.v:140331.9-140331.17" + attribute \src "libresoc.v:141963.9-141963.17" case 1'1 case end @@ -226430,21 +228927,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6340 3'111 + assign $1\src_l_r_src$next[2:0]$6388 3'111 case - assign $1\src_l_r_src$next[2:0]$6340 \reset_r + assign $1\src_l_r_src$next[2:0]$6388 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6339 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 end - attribute \src "libresoc.v:140339.3-140347.6" - process $proc$libresoc.v:140339$6341 + attribute \src "libresoc.v:141971.3-141979.6" + process $proc$libresoc.v:141971$6389 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6342 $1\adr_l_r_adr$next[0:0]$6343 - attribute \src "libresoc.v:140340.5-140340.29" + assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 + attribute \src "libresoc.v:141972.5-141972.29" switch \initial - attribute \src "libresoc.v:140340.9-140340.17" + attribute \src "libresoc.v:141972.9-141972.17" case 1'1 case end @@ -226453,21 +228950,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6343 1'1 + assign $1\adr_l_r_adr$next[0:0]$6391 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6343 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6391 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6342 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 end - attribute \src "libresoc.v:140348.3-140356.6" - process $proc$libresoc.v:140348$6344 + attribute \src "libresoc.v:141980.3-141988.6" + process $proc$libresoc.v:141980$6392 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6345 $1\wri_l_r_wri$next[0:0]$6346 - attribute \src "libresoc.v:140349.5-140349.29" + assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 + attribute \src "libresoc.v:141981.5-141981.29" switch \initial - attribute \src "libresoc.v:140349.9-140349.17" + attribute \src "libresoc.v:141981.9-141981.17" case 1'1 case end @@ -226476,21 +228973,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6346 1'1 + assign $1\wri_l_r_wri$next[0:0]$6394 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6346 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6394 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6345 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 end - attribute \src "libresoc.v:140357.3-140365.6" - process $proc$libresoc.v:140357$6347 + attribute \src "libresoc.v:141989.3-141997.6" + process $proc$libresoc.v:141989$6395 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6348 $1\upd_l_s_upd$next[0:0]$6349 - attribute \src "libresoc.v:140358.5-140358.29" + assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 + attribute \src "libresoc.v:141990.5-141990.29" switch \initial - attribute \src "libresoc.v:140358.9-140358.17" + attribute \src "libresoc.v:141990.9-141990.17" case 1'1 case end @@ -226499,21 +228996,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6349 1'0 + assign $1\upd_l_s_upd$next[0:0]$6397 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6349 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6397 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6348 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 end - attribute \src "libresoc.v:140366.3-140374.6" - process $proc$libresoc.v:140366$6350 + attribute \src "libresoc.v:141998.3-142006.6" + process $proc$libresoc.v:141998$6398 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6351 $1\upd_l_r_upd$next[0:0]$6352 - attribute \src "libresoc.v:140367.5-140367.29" + assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 + attribute \src "libresoc.v:141999.5-141999.29" switch \initial - attribute \src "libresoc.v:140367.9-140367.17" + attribute \src "libresoc.v:141999.9-141999.17" case 1'1 case end @@ -226522,21 +229019,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6352 1'1 + assign $1\upd_l_r_upd$next[0:0]$6400 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6352 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6400 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6351 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 end - attribute \src "libresoc.v:140375.3-140383.6" - process $proc$libresoc.v:140375$6353 + attribute \src "libresoc.v:142007.3-142015.6" + process $proc$libresoc.v:142007$6401 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6354 $1\sto_l_r_sto$next[0:0]$6355 - attribute \src "libresoc.v:140376.5-140376.29" + assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 + attribute \src "libresoc.v:142008.5-142008.29" switch \initial - attribute \src "libresoc.v:140376.9-140376.17" + attribute \src "libresoc.v:142008.9-142008.17" case 1'1 case end @@ -226545,21 +229042,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6355 1'1 + assign $1\sto_l_r_sto$next[0:0]$6403 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6355 \$59 + assign $1\sto_l_r_sto$next[0:0]$6403 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6354 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 end - attribute \src "libresoc.v:140384.3-140392.6" - process $proc$libresoc.v:140384$6356 + attribute \src "libresoc.v:142016.3-142024.6" + process $proc$libresoc.v:142016$6404 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6357 $1\lsd_l_r_lsd$next[0:0]$6358 - attribute \src "libresoc.v:140385.5-140385.29" + assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 + attribute \src "libresoc.v:142017.5-142017.29" switch \initial - attribute \src "libresoc.v:140385.9-140385.17" + attribute \src "libresoc.v:142017.9-142017.17" case 1'1 case end @@ -226568,15 +229065,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6358 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6406 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6358 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6406 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6357 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 end - attribute \src "libresoc.v:140393.3-140435.6" - process $proc$libresoc.v:140393$6359 + attribute \src "libresoc.v:142025.3-142067.6" + process $proc$libresoc.v:142025$6407 assign { } { } assign { } { } assign { } { } @@ -226625,31 +229122,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6360 $2\oper_r__byte_reverse$next[0:0]$6392 - assign $0\oper_r__data_len$next[3:0]$6361 $2\oper_r__data_len$next[3:0]$6393 - assign $0\oper_r__fn_unit$next[13:0]$6362 $2\oper_r__fn_unit$next[13:0]$6394 + assign $0\oper_r__byte_reverse$next[0:0]$6408 $2\oper_r__byte_reverse$next[0:0]$6440 + assign $0\oper_r__data_len$next[3:0]$6409 $2\oper_r__data_len$next[3:0]$6441 + assign $0\oper_r__fn_unit$next[13:0]$6410 $2\oper_r__fn_unit$next[13:0]$6442 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6365 $2\oper_r__insn$next[31:0]$6397 - assign $0\oper_r__insn_type$next[6:0]$6366 $2\oper_r__insn_type$next[6:0]$6398 - assign $0\oper_r__is_32bit$next[0:0]$6367 $2\oper_r__is_32bit$next[0:0]$6399 - assign $0\oper_r__is_signed$next[0:0]$6368 $2\oper_r__is_signed$next[0:0]$6400 - assign $0\oper_r__ldst_mode$next[1:0]$6369 $2\oper_r__ldst_mode$next[1:0]$6401 + assign $0\oper_r__insn$next[31:0]$6413 $2\oper_r__insn$next[31:0]$6445 + assign $0\oper_r__insn_type$next[6:0]$6414 $2\oper_r__insn_type$next[6:0]$6446 + assign $0\oper_r__is_32bit$next[0:0]$6415 $2\oper_r__is_32bit$next[0:0]$6447 + assign $0\oper_r__is_signed$next[0:0]$6416 $2\oper_r__is_signed$next[0:0]$6448 + assign $0\oper_r__ldst_mode$next[1:0]$6417 $2\oper_r__ldst_mode$next[1:0]$6449 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6374 $2\oper_r__sign_extend$next[0:0]$6406 - assign $0\oper_r__zero_a$next[0:0]$6375 $2\oper_r__zero_a$next[0:0]$6407 - assign $0\oper_r__imm_data__data$next[63:0]$6363 $3\oper_r__imm_data__data$next[63:0]$6408 - assign $0\oper_r__imm_data__ok$next[0:0]$6364 $3\oper_r__imm_data__ok$next[0:0]$6409 - assign $0\oper_r__oe__oe$next[0:0]$6370 $3\oper_r__oe__oe$next[0:0]$6410 - assign $0\oper_r__oe__ok$next[0:0]$6371 $3\oper_r__oe__ok$next[0:0]$6411 - assign $0\oper_r__rc__ok$next[0:0]$6372 $3\oper_r__rc__ok$next[0:0]$6412 - assign $0\oper_r__rc__rc$next[0:0]$6373 $3\oper_r__rc__rc$next[0:0]$6413 - attribute \src "libresoc.v:140394.5-140394.29" + assign $0\oper_r__sign_extend$next[0:0]$6422 $2\oper_r__sign_extend$next[0:0]$6454 + assign $0\oper_r__zero_a$next[0:0]$6423 $2\oper_r__zero_a$next[0:0]$6455 + assign $0\oper_r__imm_data__data$next[63:0]$6411 $3\oper_r__imm_data__data$next[63:0]$6456 + assign $0\oper_r__imm_data__ok$next[0:0]$6412 $3\oper_r__imm_data__ok$next[0:0]$6457 + assign $0\oper_r__oe__oe$next[0:0]$6418 $3\oper_r__oe__oe$next[0:0]$6458 + assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 + assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 + assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 + attribute \src "libresoc.v:142026.5-142026.29" switch \initial - attribute \src "libresoc.v:140394.9-140394.17" + attribute \src "libresoc.v:142026.9-142026.17" case 1'1 case end @@ -226673,24 +229170,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6385 $1\oper_r__sign_extend$next[0:0]$6390 $1\oper_r__byte_reverse$next[0:0]$6376 $1\oper_r__data_len$next[3:0]$6377 $1\oper_r__is_signed$next[0:0]$6384 $1\oper_r__is_32bit$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6387 $1\oper_r__oe__oe$next[0:0]$6386 $1\oper_r__rc__ok$next[0:0]$6388 $1\oper_r__rc__rc$next[0:0]$6389 $1\oper_r__zero_a$next[0:0]$6391 $1\oper_r__imm_data__ok$next[0:0]$6380 $1\oper_r__imm_data__data$next[63:0]$6379 $1\oper_r__fn_unit$next[13:0]$6378 $1\oper_r__insn_type$next[6:0]$6382 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6429 $1\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__data_len$next[3:0]$6425 $1\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__zero_a$next[0:0]$6439 $1\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__insn_type$next[6:0]$6430 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6376 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6377 \oper_r__data_len - assign $1\oper_r__fn_unit$next[13:0]$6378 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6379 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6380 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6381 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6382 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6383 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6384 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6385 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6386 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6387 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6388 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6389 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6390 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6391 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6424 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6425 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6426 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6427 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6428 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6429 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6430 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6431 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6432 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6433 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6434 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6435 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6436 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6437 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6438 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6439 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -226712,24 +229209,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6397 $2\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__data_len$next[3:0]$6393 $2\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__oe__ok$next[0:0]$6403 $2\oper_r__oe__oe$next[0:0]$6402 $2\oper_r__rc__ok$next[0:0]$6404 $2\oper_r__rc__rc$next[0:0]$6405 $2\oper_r__zero_a$next[0:0]$6407 $2\oper_r__imm_data__ok$next[0:0]$6396 $2\oper_r__imm_data__data$next[63:0]$6395 $2\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__insn_type$next[6:0]$6398 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6445 $2\oper_r__ldst_mode$next[1:0]$6449 $2\oper_r__sign_extend$next[0:0]$6454 $2\oper_r__byte_reverse$next[0:0]$6440 $2\oper_r__data_len$next[3:0]$6441 $2\oper_r__is_signed$next[0:0]$6448 $2\oper_r__is_32bit$next[0:0]$6447 $2\oper_r__oe__ok$next[0:0]$6451 $2\oper_r__oe__oe$next[0:0]$6450 $2\oper_r__rc__ok$next[0:0]$6452 $2\oper_r__rc__rc$next[0:0]$6453 $2\oper_r__zero_a$next[0:0]$6455 $2\oper_r__imm_data__ok$next[0:0]$6444 $2\oper_r__imm_data__data$next[63:0]$6443 $2\oper_r__fn_unit$next[13:0]$6442 $2\oper_r__insn_type$next[6:0]$6446 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6392 $1\oper_r__byte_reverse$next[0:0]$6376 - assign $2\oper_r__data_len$next[3:0]$6393 $1\oper_r__data_len$next[3:0]$6377 - assign $2\oper_r__fn_unit$next[13:0]$6394 $1\oper_r__fn_unit$next[13:0]$6378 - assign $2\oper_r__imm_data__data$next[63:0]$6395 $1\oper_r__imm_data__data$next[63:0]$6379 - assign $2\oper_r__imm_data__ok$next[0:0]$6396 $1\oper_r__imm_data__ok$next[0:0]$6380 - assign $2\oper_r__insn$next[31:0]$6397 $1\oper_r__insn$next[31:0]$6381 - assign $2\oper_r__insn_type$next[6:0]$6398 $1\oper_r__insn_type$next[6:0]$6382 - assign $2\oper_r__is_32bit$next[0:0]$6399 $1\oper_r__is_32bit$next[0:0]$6383 - assign $2\oper_r__is_signed$next[0:0]$6400 $1\oper_r__is_signed$next[0:0]$6384 - assign $2\oper_r__ldst_mode$next[1:0]$6401 $1\oper_r__ldst_mode$next[1:0]$6385 - assign $2\oper_r__oe__oe$next[0:0]$6402 $1\oper_r__oe__oe$next[0:0]$6386 - assign $2\oper_r__oe__ok$next[0:0]$6403 $1\oper_r__oe__ok$next[0:0]$6387 - assign $2\oper_r__rc__ok$next[0:0]$6404 $1\oper_r__rc__ok$next[0:0]$6388 - assign $2\oper_r__rc__rc$next[0:0]$6405 $1\oper_r__rc__rc$next[0:0]$6389 - assign $2\oper_r__sign_extend$next[0:0]$6406 $1\oper_r__sign_extend$next[0:0]$6390 - assign $2\oper_r__zero_a$next[0:0]$6407 $1\oper_r__zero_a$next[0:0]$6391 + assign $2\oper_r__byte_reverse$next[0:0]$6440 $1\oper_r__byte_reverse$next[0:0]$6424 + assign $2\oper_r__data_len$next[3:0]$6441 $1\oper_r__data_len$next[3:0]$6425 + assign $2\oper_r__fn_unit$next[13:0]$6442 $1\oper_r__fn_unit$next[13:0]$6426 + assign $2\oper_r__imm_data__data$next[63:0]$6443 $1\oper_r__imm_data__data$next[63:0]$6427 + assign $2\oper_r__imm_data__ok$next[0:0]$6444 $1\oper_r__imm_data__ok$next[0:0]$6428 + assign $2\oper_r__insn$next[31:0]$6445 $1\oper_r__insn$next[31:0]$6429 + assign $2\oper_r__insn_type$next[6:0]$6446 $1\oper_r__insn_type$next[6:0]$6430 + assign $2\oper_r__is_32bit$next[0:0]$6447 $1\oper_r__is_32bit$next[0:0]$6431 + assign $2\oper_r__is_signed$next[0:0]$6448 $1\oper_r__is_signed$next[0:0]$6432 + assign $2\oper_r__ldst_mode$next[1:0]$6449 $1\oper_r__ldst_mode$next[1:0]$6433 + assign $2\oper_r__oe__oe$next[0:0]$6450 $1\oper_r__oe__oe$next[0:0]$6434 + assign $2\oper_r__oe__ok$next[0:0]$6451 $1\oper_r__oe__ok$next[0:0]$6435 + assign $2\oper_r__rc__ok$next[0:0]$6452 $1\oper_r__rc__ok$next[0:0]$6436 + assign $2\oper_r__rc__rc$next[0:0]$6453 $1\oper_r__rc__rc$next[0:0]$6437 + assign $2\oper_r__sign_extend$next[0:0]$6454 $1\oper_r__sign_extend$next[0:0]$6438 + assign $2\oper_r__zero_a$next[0:0]$6455 $1\oper_r__zero_a$next[0:0]$6439 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -226741,46 +229238,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6409 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6413 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6412 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6410 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6411 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6461 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6460 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6458 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6459 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6408 $2\oper_r__imm_data__data$next[63:0]$6395 - assign $3\oper_r__imm_data__ok$next[0:0]$6409 $2\oper_r__imm_data__ok$next[0:0]$6396 - assign $3\oper_r__oe__oe$next[0:0]$6410 $2\oper_r__oe__oe$next[0:0]$6402 - assign $3\oper_r__oe__ok$next[0:0]$6411 $2\oper_r__oe__ok$next[0:0]$6403 - assign $3\oper_r__rc__ok$next[0:0]$6412 $2\oper_r__rc__ok$next[0:0]$6404 - assign $3\oper_r__rc__rc$next[0:0]$6413 $2\oper_r__rc__rc$next[0:0]$6405 + assign $3\oper_r__imm_data__data$next[63:0]$6456 $2\oper_r__imm_data__data$next[63:0]$6443 + assign $3\oper_r__imm_data__ok$next[0:0]$6457 $2\oper_r__imm_data__ok$next[0:0]$6444 + assign $3\oper_r__oe__oe$next[0:0]$6458 $2\oper_r__oe__oe$next[0:0]$6450 + assign $3\oper_r__oe__ok$next[0:0]$6459 $2\oper_r__oe__ok$next[0:0]$6451 + assign $3\oper_r__rc__ok$next[0:0]$6460 $2\oper_r__rc__ok$next[0:0]$6452 + assign $3\oper_r__rc__rc$next[0:0]$6461 $2\oper_r__rc__rc$next[0:0]$6453 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6360 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6361 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6362 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6363 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6364 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6365 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6366 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6367 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6368 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6369 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6370 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6371 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6372 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6373 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6374 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6375 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6408 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6409 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6410 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6411 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6412 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6413 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6414 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6415 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6416 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6417 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6418 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6419 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6420 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6421 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 end - attribute \src "libresoc.v:140436.3-140445.6" - process $proc$libresoc.v:140436$6414 + attribute \src "libresoc.v:142068.3-142077.6" + process $proc$libresoc.v:142068$6462 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6415 $1\ldo_r$next[63:0]$6416 - attribute \src "libresoc.v:140437.5-140437.29" + assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 + attribute \src "libresoc.v:142069.5-142069.29" switch \initial - attribute \src "libresoc.v:140437.9-140437.17" + attribute \src "libresoc.v:142069.9-142069.17" case 1'1 case end @@ -226789,22 +229286,22 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6416 \ldd_o + assign $1\ldo_r$next[63:0]$6464 \ldd_o case - assign $1\ldo_r$next[63:0]$6416 \ldo_r + assign $1\ldo_r$next[63:0]$6464 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6415 + update \ldo_r$next $0\ldo_r$next[63:0]$6463 end - attribute \src "libresoc.v:140446.3-140461.6" - process $proc$libresoc.v:140446$6417 + attribute \src "libresoc.v:142078.3-142093.6" + process $proc$libresoc.v:142078$6465 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6418 $2\src_r0$next[63:0]$6420 - attribute \src "libresoc.v:140447.5-140447.29" + assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 + attribute \src "libresoc.v:142079.5-142079.29" switch \initial - attribute \src "libresoc.v:140447.9-140447.17" + attribute \src "libresoc.v:142079.9-142079.17" case 1'1 case end @@ -226813,31 +229310,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6419 \src1_i + assign $1\src_r0$next[63:0]$6467 \src1_i case - assign $1\src_r0$next[63:0]$6419 \src_r0 + assign $1\src_r0$next[63:0]$6467 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6420 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6420 $1\src_r0$next[63:0]$6419 + assign $2\src_r0$next[63:0]$6468 $1\src_r0$next[63:0]$6467 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6418 + update \src_r0$next $0\src_r0$next[63:0]$6466 end - attribute \src "libresoc.v:140462.3-140477.6" - process $proc$libresoc.v:140462$6421 + attribute \src "libresoc.v:142094.3-142109.6" + process $proc$libresoc.v:142094$6469 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6422 $2\src_r1$next[63:0]$6424 - attribute \src "libresoc.v:140463.5-140463.29" + assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:142095.5-142095.29" switch \initial - attribute \src "libresoc.v:140463.9-140463.17" + attribute \src "libresoc.v:142095.9-142095.17" case 1'1 case end @@ -226846,31 +229343,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6423 \src2_i + assign $1\src_r1$next[63:0]$6471 \src2_i case - assign $1\src_r1$next[63:0]$6423 \src_r1 + assign $1\src_r1$next[63:0]$6471 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6424 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6424 $1\src_r1$next[63:0]$6423 + assign $2\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6471 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6422 + update \src_r1$next $0\src_r1$next[63:0]$6470 end - attribute \src "libresoc.v:140478.3-140493.6" - process $proc$libresoc.v:140478$6425 + attribute \src "libresoc.v:142110.3-142125.6" + process $proc$libresoc.v:142110$6473 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6426 $2\src_r2$next[63:0]$6428 - attribute \src "libresoc.v:140479.5-140479.29" + assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 + attribute \src "libresoc.v:142111.5-142111.29" switch \initial - attribute \src "libresoc.v:140479.9-140479.17" + attribute \src "libresoc.v:142111.9-142111.17" case 1'1 case end @@ -226879,30 +229376,30 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6427 \src3_i + assign $1\src_r2$next[63:0]$6475 \src3_i case - assign $1\src_r2$next[63:0]$6427 \src_r2 + assign $1\src_r2$next[63:0]$6475 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6428 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6476 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6428 $1\src_r2$next[63:0]$6427 + assign $2\src_r2$next[63:0]$6476 $1\src_r2$next[63:0]$6475 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6426 + update \src_r2$next $0\src_r2$next[63:0]$6474 end - attribute \src "libresoc.v:140494.3-140503.6" - process $proc$libresoc.v:140494$6429 + attribute \src "libresoc.v:142126.3-142135.6" + process $proc$libresoc.v:142126$6477 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6430 $1\ea_r$next[63:0]$6431 - attribute \src "libresoc.v:140495.5-140495.29" + assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 + attribute \src "libresoc.v:142127.5-142127.29" switch \initial - attribute \src "libresoc.v:140495.9-140495.17" + attribute \src "libresoc.v:142127.9-142127.17" case 1'1 case end @@ -226911,21 +229408,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6431 \alu_o + assign $1\ea_r$next[63:0]$6479 \alu_o case - assign $1\ea_r$next[63:0]$6431 \ea_r + assign $1\ea_r$next[63:0]$6479 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6430 + update \ea_r$next $0\ea_r$next[63:0]$6478 end - attribute \src "libresoc.v:140504.3-140513.6" - process $proc$libresoc.v:140504$6432 + attribute \src "libresoc.v:142136.3-142145.6" + process $proc$libresoc.v:142136$6480 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:140505.5-140505.29" + attribute \src "libresoc.v:142137.5-142137.29" switch \initial - attribute \src "libresoc.v:140505.9-140505.17" + attribute \src "libresoc.v:142137.9-142137.17" case 1'1 case end @@ -226941,14 +229438,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:140514.3-140523.6" - process $proc$libresoc.v:140514$6433 + attribute \src "libresoc.v:142146.3-142155.6" + process $proc$libresoc.v:142146$6481 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:140515.5-140515.29" + attribute \src "libresoc.v:142147.5-142147.29" switch \initial - attribute \src "libresoc.v:140515.9-140515.17" + attribute \src "libresoc.v:142147.9-142147.17" case 1'1 case end @@ -226964,14 +229461,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:140524.3-140532.6" - process $proc$libresoc.v:140524$6434 + attribute \src "libresoc.v:142156.3-142164.6" + process $proc$libresoc.v:142156$6482 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6435 $1\ldst_port0_addr_i_ok$next[0:0]$6436 - attribute \src "libresoc.v:140525.5-140525.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 + attribute \src "libresoc.v:142157.5-142157.29" switch \initial - attribute \src "libresoc.v:140525.9-140525.17" + attribute \src "libresoc.v:142157.9-142157.17" case 1'1 case end @@ -226980,21 +229477,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6436 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6435 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 end - attribute \src "libresoc.v:140533.3-140556.6" - process $proc$libresoc.v:140533$6437 + attribute \src "libresoc.v:142165.3-142188.6" + process $proc$libresoc.v:142165$6485 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:140534.5-140534.29" + attribute \src "libresoc.v:142166.5-142166.29" switch \initial - attribute \src "libresoc.v:140534.9-140534.17" + attribute \src "libresoc.v:142166.9-142166.17" case 1'1 case end @@ -227031,13 +229528,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:140557.3-140568.6" - process $proc$libresoc.v:140557$6438 + attribute \src "libresoc.v:142189.3-142200.6" + process $proc$libresoc.v:142189$6486 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:140558.5-140558.29" + attribute \src "libresoc.v:142190.5-142190.29" switch \initial - attribute \src "libresoc.v:140558.9-140558.17" + attribute \src "libresoc.v:142190.9-142190.17" case 1'1 case end @@ -227055,13 +229552,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:140569.3-140588.6" - process $proc$libresoc.v:140569$6439 + attribute \src "libresoc.v:142201.3-142220.6" + process $proc$libresoc.v:142201$6487 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:140570.5-140570.29" + attribute \src "libresoc.v:142202.5-142202.29" switch \initial - attribute \src "libresoc.v:140570.9-140570.17" + attribute \src "libresoc.v:142202.9-142202.17" case 1'1 case end @@ -227090,14 +229587,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:140589.3-140612.6" - process $proc$libresoc.v:140589$6440 + attribute \src "libresoc.v:142221.3-142244.6" + process $proc$libresoc.v:142221$6488 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:140590.5-140590.29" + attribute \src "libresoc.v:142222.5-142222.29" switch \initial - attribute \src "libresoc.v:140590.9-140590.17" + attribute \src "libresoc.v:142222.9-142222.17" case 1'1 case end @@ -227134,13 +229631,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:140613.3-140624.6" - process $proc$libresoc.v:140613$6441 + attribute \src "libresoc.v:142245.3-142256.6" + process $proc$libresoc.v:142245$6489 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:140614.5-140614.29" + attribute \src "libresoc.v:142246.5-142246.29" switch \initial - attribute \src "libresoc.v:140614.9-140614.17" + attribute \src "libresoc.v:142246.9-142246.17" case 1'1 case end @@ -227158,97 +229655,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:140072$6200_Y - connect \$102 $and$libresoc.v:140073$6201_Y - connect \$104 $and$libresoc.v:140074$6202_Y - connect \$106 $and$libresoc.v:140075$6203_Y - connect \$108 $and$libresoc.v:140076$6204_Y - connect \$10 $or$libresoc.v:140077$6205_Y - connect \$110 $and$libresoc.v:140078$6206_Y - connect \$112 $and$libresoc.v:140079$6207_Y - connect \$114 $and$libresoc.v:140080$6208_Y - connect \$116 $and$libresoc.v:140081$6209_Y - connect \$118 $and$libresoc.v:140082$6210_Y - connect \$120 $and$libresoc.v:140083$6211_Y - connect \$122 $and$libresoc.v:140084$6212_Y - connect \$124 $and$libresoc.v:140085$6213_Y - connect \$126 $eq$libresoc.v:140086$6214_Y - connect \$128 $and$libresoc.v:140087$6215_Y - connect \$12 $or$libresoc.v:140088$6216_Y - connect \$130 $and$libresoc.v:140089$6217_Y - connect \$132 $and$libresoc.v:140090$6218_Y - connect \$134 $or$libresoc.v:140091$6219_Y - connect \$136 $or$libresoc.v:140092$6220_Y - connect \$138 $or$libresoc.v:140093$6221_Y - connect \$140 $and$libresoc.v:140094$6222_Y - connect \$142 $and$libresoc.v:140095$6223_Y - connect \$145 $or$libresoc.v:140096$6224_Y - connect \$147 $or$libresoc.v:140097$6225_Y - connect \$144 $not$libresoc.v:140098$6226_Y - connect \$14 $or$libresoc.v:140099$6227_Y - connect \$150 $and$libresoc.v:140100$6228_Y - connect \$152 $or$libresoc.v:140101$6229_Y - connect \$154 $and$libresoc.v:140102$6230_Y - connect \$156 $not$libresoc.v:140103$6231_Y - connect \$158 $or$libresoc.v:140104$6232_Y - connect \$160 $and$libresoc.v:140105$6233_Y - connect \$162 $eq$libresoc.v:140106$6234_Y - connect \$164 $and$libresoc.v:140107$6235_Y - connect \$167 $eq$libresoc.v:140108$6236_Y - connect \$16 $or$libresoc.v:140109$6237_Y - connect \$169 $and$libresoc.v:140110$6238_Y - connect \$171 $and$libresoc.v:140111$6239_Y - connect \$173 $and$libresoc.v:140112$6240_Y - connect \$175 $pos$libresoc.v:140113$6242_Y - connect \$177 $and$libresoc.v:140114$6243_Y - connect \$186 $pos$libresoc.v:140115$6245_Y - connect \$188 $pos$libresoc.v:140116$6246_Y - connect \$18 $or$libresoc.v:140117$6247_Y - connect \$190 $pos$libresoc.v:140118$6248_Y - connect \$192 $eq$libresoc.v:140119$6249_Y - connect \$194 $pos$libresoc.v:140120$6251_Y - connect \$196 $pos$libresoc.v:140121$6252_Y - connect \$198 $pos$libresoc.v:140122$6253_Y - connect \$20 $or$libresoc.v:140123$6254_Y - connect \$22 $eq$libresoc.v:140124$6255_Y - connect \$24 $eq$libresoc.v:140125$6256_Y - connect \$26 $and$libresoc.v:140126$6257_Y - connect \$28 $and$libresoc.v:140127$6258_Y - connect \$30 $not$libresoc.v:140128$6259_Y - connect \$32 $and$libresoc.v:140129$6260_Y - connect \$34 $not$libresoc.v:140130$6261_Y - connect \$36 $and$libresoc.v:140131$6262_Y - connect \$39 $not$libresoc.v:140132$6263_Y - connect \$41 $eq$libresoc.v:140133$6264_Y - connect \$43 $and$libresoc.v:140134$6265_Y - connect \$45 $or$libresoc.v:140135$6266_Y - connect \$47 $not$libresoc.v:140136$6267_Y - connect \$49 $eq$libresoc.v:140137$6268_Y - connect \$51 $and$libresoc.v:140138$6269_Y - connect \$53 $or$libresoc.v:140139$6270_Y - connect \$55 $or$libresoc.v:140140$6271_Y - connect \$57 $and$libresoc.v:140141$6272_Y - connect \$59 $or$libresoc.v:140142$6273_Y - connect \$61 $or$libresoc.v:140143$6274_Y - connect \$63 $or$libresoc.v:140144$6275_Y - connect \$65 $ternary$libresoc.v:140145$6276_Y - connect \$67 $ternary$libresoc.v:140146$6277_Y - connect \$69 $ternary$libresoc.v:140147$6278_Y - connect \$71 $ternary$libresoc.v:140148$6279_Y - connect \$74 $add$libresoc.v:140149$6280_Y - connect \$76 $and$libresoc.v:140150$6281_Y - connect \$78 $not$libresoc.v:140151$6282_Y - connect \$80 $and$libresoc.v:140152$6283_Y - connect \$82 $not$libresoc.v:140153$6284_Y - connect \$84 $and$libresoc.v:140154$6285_Y - connect \$86 $and$libresoc.v:140155$6286_Y - connect \$88 $and$libresoc.v:140156$6287_Y - connect \$8 $or$libresoc.v:140157$6288_Y - connect \$90 $or$libresoc.v:140158$6289_Y - connect \$93 $or$libresoc.v:140159$6290_Y - connect \$92 $not$libresoc.v:140160$6291_Y - connect \$96 $and$libresoc.v:140161$6292_Y - connect \$98 $not$libresoc.v:140162$6293_Y + connect \$100 $and$libresoc.v:141704$6248_Y + connect \$102 $and$libresoc.v:141705$6249_Y + connect \$104 $and$libresoc.v:141706$6250_Y + connect \$106 $and$libresoc.v:141707$6251_Y + connect \$108 $and$libresoc.v:141708$6252_Y + connect \$10 $or$libresoc.v:141709$6253_Y + connect \$110 $and$libresoc.v:141710$6254_Y + connect \$112 $and$libresoc.v:141711$6255_Y + connect \$114 $and$libresoc.v:141712$6256_Y + connect \$116 $and$libresoc.v:141713$6257_Y + connect \$118 $and$libresoc.v:141714$6258_Y + connect \$120 $and$libresoc.v:141715$6259_Y + connect \$122 $and$libresoc.v:141716$6260_Y + connect \$124 $and$libresoc.v:141717$6261_Y + connect \$126 $eq$libresoc.v:141718$6262_Y + connect \$128 $and$libresoc.v:141719$6263_Y + connect \$12 $or$libresoc.v:141720$6264_Y + connect \$130 $and$libresoc.v:141721$6265_Y + connect \$132 $and$libresoc.v:141722$6266_Y + connect \$134 $or$libresoc.v:141723$6267_Y + connect \$136 $or$libresoc.v:141724$6268_Y + connect \$138 $or$libresoc.v:141725$6269_Y + connect \$140 $and$libresoc.v:141726$6270_Y + connect \$142 $and$libresoc.v:141727$6271_Y + connect \$145 $or$libresoc.v:141728$6272_Y + connect \$147 $or$libresoc.v:141729$6273_Y + connect \$144 $not$libresoc.v:141730$6274_Y + connect \$14 $or$libresoc.v:141731$6275_Y + connect \$150 $and$libresoc.v:141732$6276_Y + connect \$152 $or$libresoc.v:141733$6277_Y + connect \$154 $and$libresoc.v:141734$6278_Y + connect \$156 $not$libresoc.v:141735$6279_Y + connect \$158 $or$libresoc.v:141736$6280_Y + connect \$160 $and$libresoc.v:141737$6281_Y + connect \$162 $eq$libresoc.v:141738$6282_Y + connect \$164 $and$libresoc.v:141739$6283_Y + connect \$167 $eq$libresoc.v:141740$6284_Y + connect \$16 $or$libresoc.v:141741$6285_Y + connect \$169 $and$libresoc.v:141742$6286_Y + connect \$171 $and$libresoc.v:141743$6287_Y + connect \$173 $and$libresoc.v:141744$6288_Y + connect \$175 $pos$libresoc.v:141745$6290_Y + connect \$177 $and$libresoc.v:141746$6291_Y + connect \$186 $pos$libresoc.v:141747$6293_Y + connect \$188 $pos$libresoc.v:141748$6294_Y + connect \$18 $or$libresoc.v:141749$6295_Y + connect \$190 $pos$libresoc.v:141750$6296_Y + connect \$192 $eq$libresoc.v:141751$6297_Y + connect \$194 $pos$libresoc.v:141752$6299_Y + connect \$196 $pos$libresoc.v:141753$6300_Y + connect \$198 $pos$libresoc.v:141754$6301_Y + connect \$20 $or$libresoc.v:141755$6302_Y + connect \$22 $eq$libresoc.v:141756$6303_Y + connect \$24 $eq$libresoc.v:141757$6304_Y + connect \$26 $and$libresoc.v:141758$6305_Y + connect \$28 $and$libresoc.v:141759$6306_Y + connect \$30 $not$libresoc.v:141760$6307_Y + connect \$32 $and$libresoc.v:141761$6308_Y + connect \$34 $not$libresoc.v:141762$6309_Y + connect \$36 $and$libresoc.v:141763$6310_Y + connect \$39 $not$libresoc.v:141764$6311_Y + connect \$41 $eq$libresoc.v:141765$6312_Y + connect \$43 $and$libresoc.v:141766$6313_Y + connect \$45 $or$libresoc.v:141767$6314_Y + connect \$47 $not$libresoc.v:141768$6315_Y + connect \$49 $eq$libresoc.v:141769$6316_Y + connect \$51 $and$libresoc.v:141770$6317_Y + connect \$53 $or$libresoc.v:141771$6318_Y + connect \$55 $or$libresoc.v:141772$6319_Y + connect \$57 $and$libresoc.v:141773$6320_Y + connect \$59 $or$libresoc.v:141774$6321_Y + connect \$61 $or$libresoc.v:141775$6322_Y + connect \$63 $or$libresoc.v:141776$6323_Y + connect \$65 $ternary$libresoc.v:141777$6324_Y + connect \$67 $ternary$libresoc.v:141778$6325_Y + connect \$69 $ternary$libresoc.v:141779$6326_Y + connect \$71 $ternary$libresoc.v:141780$6327_Y + connect \$74 $add$libresoc.v:141781$6328_Y + connect \$76 $and$libresoc.v:141782$6329_Y + connect \$78 $not$libresoc.v:141783$6330_Y + connect \$80 $and$libresoc.v:141784$6331_Y + connect \$82 $not$libresoc.v:141785$6332_Y + connect \$84 $and$libresoc.v:141786$6333_Y + connect \$86 $and$libresoc.v:141787$6334_Y + connect \$88 $and$libresoc.v:141788$6335_Y + connect \$8 $or$libresoc.v:141789$6336_Y + connect \$90 $or$libresoc.v:141790$6337_Y + connect \$93 $or$libresoc.v:141791$6338_Y + connect \$92 $not$libresoc.v:141792$6339_Y + connect \$96 $and$libresoc.v:141793$6340_Y + connect \$98 $not$libresoc.v:141794$6341_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -227309,271 +229806,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:140688.1-141275.10" +attribute \src "libresoc.v:142320.1-142907.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:140689.7-140689.20" + attribute \src "libresoc.v:142321.7-142321.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $10\mask[9:9] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $11\mask[10:10] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $12\mask[11:11] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $13\mask[12:12] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $14\mask[13:13] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $15\mask[14:14] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $16\mask[15:15] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $17\mask[16:16] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $18\mask[17:17] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $19\mask[18:18] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $1\mask[0:0] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $20\mask[19:19] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $21\mask[20:20] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $22\mask[21:21] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $23\mask[22:22] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $24\mask[23:23] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $25\mask[24:24] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $26\mask[25:25] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $27\mask[26:26] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $28\mask[27:27] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $29\mask[28:28] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $2\mask[1:1] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $30\mask[29:29] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $31\mask[30:30] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $32\mask[31:31] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $33\mask[32:32] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $34\mask[33:33] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $35\mask[34:34] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $36\mask[35:35] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $37\mask[36:36] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $38\mask[37:37] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $39\mask[38:38] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $3\mask[2:2] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $40\mask[39:39] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $41\mask[40:40] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $42\mask[41:41] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $43\mask[42:42] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $44\mask[43:43] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $45\mask[44:44] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $46\mask[45:45] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $47\mask[46:46] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $48\mask[47:47] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $49\mask[48:48] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $4\mask[3:3] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $50\mask[49:49] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $51\mask[50:50] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $52\mask[51:51] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $53\mask[52:52] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $54\mask[53:53] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $55\mask[54:54] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $56\mask[55:55] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $57\mask[56:56] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $58\mask[57:57] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $59\mask[58:58] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $5\mask[4:4] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $60\mask[59:59] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $61\mask[60:60] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $62\mask[61:61] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $63\mask[62:62] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $64\mask[63:63] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $6\mask[5:5] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $7\mask[6:6] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $8\mask[7:7] - attribute \src "libresoc.v:140887.3-141274.6" + attribute \src "libresoc.v:142519.3-142906.6" wire $9\mask[8:8] - attribute \src "libresoc.v:140823.17-140823.96" - wire $gt$libresoc.v:140823$6478_Y - attribute \src "libresoc.v:140824.18-140824.98" - wire $gt$libresoc.v:140824$6479_Y - attribute \src "libresoc.v:140825.19-140825.99" - wire $gt$libresoc.v:140825$6480_Y - attribute \src "libresoc.v:140826.19-140826.99" - wire $gt$libresoc.v:140826$6481_Y - attribute \src "libresoc.v:140827.19-140827.99" - wire $gt$libresoc.v:140827$6482_Y - attribute \src "libresoc.v:140828.19-140828.99" - wire $gt$libresoc.v:140828$6483_Y - attribute \src "libresoc.v:140829.19-140829.99" - wire $gt$libresoc.v:140829$6484_Y - attribute \src "libresoc.v:140830.19-140830.99" - wire $gt$libresoc.v:140830$6485_Y - attribute \src "libresoc.v:140831.19-140831.99" - wire $gt$libresoc.v:140831$6486_Y - attribute \src "libresoc.v:140832.19-140832.99" - wire $gt$libresoc.v:140832$6487_Y - attribute \src "libresoc.v:140833.19-140833.99" - wire $gt$libresoc.v:140833$6488_Y - attribute \src "libresoc.v:140834.18-140834.97" - wire $gt$libresoc.v:140834$6489_Y - attribute \src "libresoc.v:140835.19-140835.99" - wire $gt$libresoc.v:140835$6490_Y - attribute \src "libresoc.v:140836.19-140836.99" - wire $gt$libresoc.v:140836$6491_Y - attribute \src "libresoc.v:140837.19-140837.99" - wire $gt$libresoc.v:140837$6492_Y - attribute \src "libresoc.v:140838.19-140838.99" - wire $gt$libresoc.v:140838$6493_Y - attribute \src "libresoc.v:140839.19-140839.99" - wire $gt$libresoc.v:140839$6494_Y - attribute \src "libresoc.v:140840.18-140840.97" - wire $gt$libresoc.v:140840$6495_Y - attribute \src "libresoc.v:140841.18-140841.97" - wire $gt$libresoc.v:140841$6496_Y - attribute \src "libresoc.v:140842.18-140842.97" - wire $gt$libresoc.v:140842$6497_Y - attribute \src "libresoc.v:140843.17-140843.96" - wire $gt$libresoc.v:140843$6498_Y - attribute \src "libresoc.v:140844.18-140844.97" - wire $gt$libresoc.v:140844$6499_Y - attribute \src "libresoc.v:140845.18-140845.97" - wire $gt$libresoc.v:140845$6500_Y - attribute \src "libresoc.v:140846.18-140846.97" - wire $gt$libresoc.v:140846$6501_Y - attribute \src "libresoc.v:140847.18-140847.97" - wire $gt$libresoc.v:140847$6502_Y - attribute \src "libresoc.v:140848.18-140848.97" - wire $gt$libresoc.v:140848$6503_Y - attribute \src "libresoc.v:140849.18-140849.97" - wire $gt$libresoc.v:140849$6504_Y - attribute \src "libresoc.v:140850.18-140850.97" - wire $gt$libresoc.v:140850$6505_Y - attribute \src "libresoc.v:140851.18-140851.98" - wire $gt$libresoc.v:140851$6506_Y - attribute \src "libresoc.v:140852.18-140852.98" - wire $gt$libresoc.v:140852$6507_Y - attribute \src "libresoc.v:140853.18-140853.98" - wire $gt$libresoc.v:140853$6508_Y - attribute \src "libresoc.v:140854.17-140854.96" - wire $gt$libresoc.v:140854$6509_Y - attribute \src "libresoc.v:140855.18-140855.98" - wire $gt$libresoc.v:140855$6510_Y - attribute \src "libresoc.v:140856.18-140856.98" - wire $gt$libresoc.v:140856$6511_Y - attribute \src "libresoc.v:140857.18-140857.98" - wire $gt$libresoc.v:140857$6512_Y - attribute \src "libresoc.v:140858.18-140858.98" - wire $gt$libresoc.v:140858$6513_Y - attribute \src "libresoc.v:140859.18-140859.98" - wire $gt$libresoc.v:140859$6514_Y - attribute \src "libresoc.v:140860.18-140860.98" - wire $gt$libresoc.v:140860$6515_Y - attribute \src "libresoc.v:140861.18-140861.98" - wire $gt$libresoc.v:140861$6516_Y - attribute \src "libresoc.v:140862.18-140862.98" - wire $gt$libresoc.v:140862$6517_Y - attribute \src "libresoc.v:140863.18-140863.98" - wire $gt$libresoc.v:140863$6518_Y - attribute \src "libresoc.v:140864.18-140864.98" - wire $gt$libresoc.v:140864$6519_Y - attribute \src "libresoc.v:140865.17-140865.96" - wire $gt$libresoc.v:140865$6520_Y - attribute \src "libresoc.v:140866.18-140866.98" - wire $gt$libresoc.v:140866$6521_Y - attribute \src "libresoc.v:140867.18-140867.98" - wire $gt$libresoc.v:140867$6522_Y - attribute \src "libresoc.v:140868.18-140868.98" - wire $gt$libresoc.v:140868$6523_Y - attribute \src "libresoc.v:140869.18-140869.98" - wire $gt$libresoc.v:140869$6524_Y - attribute \src "libresoc.v:140870.18-140870.98" - wire $gt$libresoc.v:140870$6525_Y - attribute \src "libresoc.v:140871.18-140871.98" - wire $gt$libresoc.v:140871$6526_Y - attribute \src "libresoc.v:140872.18-140872.98" - wire $gt$libresoc.v:140872$6527_Y - attribute \src "libresoc.v:140873.18-140873.98" - wire $gt$libresoc.v:140873$6528_Y - attribute \src "libresoc.v:140874.18-140874.98" - wire $gt$libresoc.v:140874$6529_Y - attribute \src "libresoc.v:140875.18-140875.98" - wire $gt$libresoc.v:140875$6530_Y - attribute \src "libresoc.v:140876.17-140876.96" - wire $gt$libresoc.v:140876$6531_Y - attribute \src "libresoc.v:140877.18-140877.98" - wire $gt$libresoc.v:140877$6532_Y - attribute \src "libresoc.v:140878.18-140878.98" - wire $gt$libresoc.v:140878$6533_Y - attribute \src "libresoc.v:140879.18-140879.98" - wire $gt$libresoc.v:140879$6534_Y - attribute \src "libresoc.v:140880.18-140880.98" - wire $gt$libresoc.v:140880$6535_Y - attribute \src "libresoc.v:140881.18-140881.98" - wire $gt$libresoc.v:140881$6536_Y - attribute \src "libresoc.v:140882.18-140882.98" - wire $gt$libresoc.v:140882$6537_Y - attribute \src "libresoc.v:140883.18-140883.98" - wire $gt$libresoc.v:140883$6538_Y - attribute \src "libresoc.v:140884.18-140884.98" - wire $gt$libresoc.v:140884$6539_Y - attribute \src "libresoc.v:140885.18-140885.98" - wire $gt$libresoc.v:140885$6540_Y - attribute \src "libresoc.v:140886.18-140886.98" - wire $gt$libresoc.v:140886$6541_Y + attribute \src "libresoc.v:142455.17-142455.96" + wire $gt$libresoc.v:142455$6526_Y + attribute \src "libresoc.v:142456.18-142456.98" + wire $gt$libresoc.v:142456$6527_Y + attribute \src "libresoc.v:142457.19-142457.99" + wire $gt$libresoc.v:142457$6528_Y + attribute \src "libresoc.v:142458.19-142458.99" + wire $gt$libresoc.v:142458$6529_Y + attribute \src "libresoc.v:142459.19-142459.99" + wire $gt$libresoc.v:142459$6530_Y + attribute \src "libresoc.v:142460.19-142460.99" + wire $gt$libresoc.v:142460$6531_Y + attribute \src "libresoc.v:142461.19-142461.99" + wire $gt$libresoc.v:142461$6532_Y + attribute \src "libresoc.v:142462.19-142462.99" + wire $gt$libresoc.v:142462$6533_Y + attribute \src "libresoc.v:142463.19-142463.99" + wire $gt$libresoc.v:142463$6534_Y + attribute \src "libresoc.v:142464.19-142464.99" + wire $gt$libresoc.v:142464$6535_Y + attribute \src "libresoc.v:142465.19-142465.99" + wire $gt$libresoc.v:142465$6536_Y + attribute \src "libresoc.v:142466.18-142466.97" + wire $gt$libresoc.v:142466$6537_Y + attribute \src "libresoc.v:142467.19-142467.99" + wire $gt$libresoc.v:142467$6538_Y + attribute \src "libresoc.v:142468.19-142468.99" + wire $gt$libresoc.v:142468$6539_Y + attribute \src "libresoc.v:142469.19-142469.99" + wire $gt$libresoc.v:142469$6540_Y + attribute \src "libresoc.v:142470.19-142470.99" + wire $gt$libresoc.v:142470$6541_Y + attribute \src "libresoc.v:142471.19-142471.99" + wire $gt$libresoc.v:142471$6542_Y + attribute \src "libresoc.v:142472.18-142472.97" + wire $gt$libresoc.v:142472$6543_Y + attribute \src "libresoc.v:142473.18-142473.97" + wire $gt$libresoc.v:142473$6544_Y + attribute \src "libresoc.v:142474.18-142474.97" + wire $gt$libresoc.v:142474$6545_Y + attribute \src "libresoc.v:142475.17-142475.96" + wire $gt$libresoc.v:142475$6546_Y + attribute \src "libresoc.v:142476.18-142476.97" + wire $gt$libresoc.v:142476$6547_Y + attribute \src "libresoc.v:142477.18-142477.97" + wire $gt$libresoc.v:142477$6548_Y + attribute \src "libresoc.v:142478.18-142478.97" + wire $gt$libresoc.v:142478$6549_Y + attribute \src "libresoc.v:142479.18-142479.97" + wire $gt$libresoc.v:142479$6550_Y + attribute \src "libresoc.v:142480.18-142480.97" + wire $gt$libresoc.v:142480$6551_Y + attribute \src "libresoc.v:142481.18-142481.97" + wire $gt$libresoc.v:142481$6552_Y + attribute \src "libresoc.v:142482.18-142482.97" + wire $gt$libresoc.v:142482$6553_Y + attribute \src "libresoc.v:142483.18-142483.98" + wire $gt$libresoc.v:142483$6554_Y + attribute \src "libresoc.v:142484.18-142484.98" + wire $gt$libresoc.v:142484$6555_Y + attribute \src "libresoc.v:142485.18-142485.98" + wire $gt$libresoc.v:142485$6556_Y + attribute \src "libresoc.v:142486.17-142486.96" + wire $gt$libresoc.v:142486$6557_Y + attribute \src "libresoc.v:142487.18-142487.98" + wire $gt$libresoc.v:142487$6558_Y + attribute \src "libresoc.v:142488.18-142488.98" + wire $gt$libresoc.v:142488$6559_Y + attribute \src "libresoc.v:142489.18-142489.98" + wire $gt$libresoc.v:142489$6560_Y + attribute \src "libresoc.v:142490.18-142490.98" + wire $gt$libresoc.v:142490$6561_Y + attribute \src "libresoc.v:142491.18-142491.98" + wire $gt$libresoc.v:142491$6562_Y + attribute \src "libresoc.v:142492.18-142492.98" + wire $gt$libresoc.v:142492$6563_Y + attribute \src "libresoc.v:142493.18-142493.98" + wire $gt$libresoc.v:142493$6564_Y + attribute \src "libresoc.v:142494.18-142494.98" + wire $gt$libresoc.v:142494$6565_Y + attribute \src "libresoc.v:142495.18-142495.98" + wire $gt$libresoc.v:142495$6566_Y + attribute \src "libresoc.v:142496.18-142496.98" + wire $gt$libresoc.v:142496$6567_Y + attribute \src "libresoc.v:142497.17-142497.96" + wire $gt$libresoc.v:142497$6568_Y + attribute \src "libresoc.v:142498.18-142498.98" + wire $gt$libresoc.v:142498$6569_Y + attribute \src "libresoc.v:142499.18-142499.98" + wire $gt$libresoc.v:142499$6570_Y + attribute \src "libresoc.v:142500.18-142500.98" + wire $gt$libresoc.v:142500$6571_Y + attribute \src "libresoc.v:142501.18-142501.98" + wire $gt$libresoc.v:142501$6572_Y + attribute \src "libresoc.v:142502.18-142502.98" + wire $gt$libresoc.v:142502$6573_Y + attribute \src "libresoc.v:142503.18-142503.98" + wire $gt$libresoc.v:142503$6574_Y + attribute \src "libresoc.v:142504.18-142504.98" + wire $gt$libresoc.v:142504$6575_Y + attribute \src "libresoc.v:142505.18-142505.98" + wire $gt$libresoc.v:142505$6576_Y + attribute \src "libresoc.v:142506.18-142506.98" + wire $gt$libresoc.v:142506$6577_Y + attribute \src "libresoc.v:142507.18-142507.98" + wire $gt$libresoc.v:142507$6578_Y + attribute \src "libresoc.v:142508.17-142508.96" + wire $gt$libresoc.v:142508$6579_Y + attribute \src "libresoc.v:142509.18-142509.98" + wire $gt$libresoc.v:142509$6580_Y + attribute \src "libresoc.v:142510.18-142510.98" + wire $gt$libresoc.v:142510$6581_Y + attribute \src "libresoc.v:142511.18-142511.98" + wire $gt$libresoc.v:142511$6582_Y + attribute \src "libresoc.v:142512.18-142512.98" + wire $gt$libresoc.v:142512$6583_Y + attribute \src "libresoc.v:142513.18-142513.98" + wire $gt$libresoc.v:142513$6584_Y + attribute \src "libresoc.v:142514.18-142514.98" + wire $gt$libresoc.v:142514$6585_Y + attribute \src "libresoc.v:142515.18-142515.98" + wire $gt$libresoc.v:142515$6586_Y + attribute \src "libresoc.v:142516.18-142516.98" + wire $gt$libresoc.v:142516$6587_Y + attribute \src "libresoc.v:142517.18-142517.98" + wire $gt$libresoc.v:142517$6588_Y + attribute \src "libresoc.v:142518.18-142518.98" + wire $gt$libresoc.v:142518$6589_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -227702,14 +230199,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:140689.7-140689.15" + attribute \src "libresoc.v:142321.7-142321.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140823$6478 + cell $gt $gt$libresoc.v:142455$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227717,10 +230214,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:140823$6478_Y + connect \Y $gt$libresoc.v:142455$6526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140824$6479 + cell $gt $gt$libresoc.v:142456$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227728,10 +230225,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:140824$6479_Y + connect \Y $gt$libresoc.v:142456$6527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140825$6480 + cell $gt $gt$libresoc.v:142457$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227739,10 +230236,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:140825$6480_Y + connect \Y $gt$libresoc.v:142457$6528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140826$6481 + cell $gt $gt$libresoc.v:142458$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227750,10 +230247,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:140826$6481_Y + connect \Y $gt$libresoc.v:142458$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140827$6482 + cell $gt $gt$libresoc.v:142459$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227761,10 +230258,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:140827$6482_Y + connect \Y $gt$libresoc.v:142459$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140828$6483 + cell $gt $gt$libresoc.v:142460$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227772,10 +230269,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:140828$6483_Y + connect \Y $gt$libresoc.v:142460$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140829$6484 + cell $gt $gt$libresoc.v:142461$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227783,10 +230280,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:140829$6484_Y + connect \Y $gt$libresoc.v:142461$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140830$6485 + cell $gt $gt$libresoc.v:142462$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227794,10 +230291,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:140830$6485_Y + connect \Y $gt$libresoc.v:142462$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140831$6486 + cell $gt $gt$libresoc.v:142463$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227805,10 +230302,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:140831$6486_Y + connect \Y $gt$libresoc.v:142463$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140832$6487 + cell $gt $gt$libresoc.v:142464$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227816,10 +230313,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:140832$6487_Y + connect \Y $gt$libresoc.v:142464$6535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140833$6488 + cell $gt $gt$libresoc.v:142465$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227827,10 +230324,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:140833$6488_Y + connect \Y $gt$libresoc.v:142465$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140834$6489 + cell $gt $gt$libresoc.v:142466$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227838,10 +230335,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:140834$6489_Y + connect \Y $gt$libresoc.v:142466$6537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140835$6490 + cell $gt $gt$libresoc.v:142467$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227849,10 +230346,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:140835$6490_Y + connect \Y $gt$libresoc.v:142467$6538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140836$6491 + cell $gt $gt$libresoc.v:142468$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227860,10 +230357,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:140836$6491_Y + connect \Y $gt$libresoc.v:142468$6539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140837$6492 + cell $gt $gt$libresoc.v:142469$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227871,10 +230368,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:140837$6492_Y + connect \Y $gt$libresoc.v:142469$6540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140838$6493 + cell $gt $gt$libresoc.v:142470$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227882,10 +230379,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:140838$6493_Y + connect \Y $gt$libresoc.v:142470$6541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140839$6494 + cell $gt $gt$libresoc.v:142471$6542 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227893,10 +230390,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:140839$6494_Y + connect \Y $gt$libresoc.v:142471$6542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140840$6495 + cell $gt $gt$libresoc.v:142472$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227904,10 +230401,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:140840$6495_Y + connect \Y $gt$libresoc.v:142472$6543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140841$6496 + cell $gt $gt$libresoc.v:142473$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227915,10 +230412,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:140841$6496_Y + connect \Y $gt$libresoc.v:142473$6544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140842$6497 + cell $gt $gt$libresoc.v:142474$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227926,10 +230423,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:140842$6497_Y + connect \Y $gt$libresoc.v:142474$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140843$6498 + cell $gt $gt$libresoc.v:142475$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227937,10 +230434,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:140843$6498_Y + connect \Y $gt$libresoc.v:142475$6546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140844$6499 + cell $gt $gt$libresoc.v:142476$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227948,10 +230445,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:140844$6499_Y + connect \Y $gt$libresoc.v:142476$6547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140845$6500 + cell $gt $gt$libresoc.v:142477$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227959,10 +230456,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:140845$6500_Y + connect \Y $gt$libresoc.v:142477$6548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140846$6501 + cell $gt $gt$libresoc.v:142478$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227970,10 +230467,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:140846$6501_Y + connect \Y $gt$libresoc.v:142478$6549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140847$6502 + cell $gt $gt$libresoc.v:142479$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227981,10 +230478,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:140847$6502_Y + connect \Y $gt$libresoc.v:142479$6550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140848$6503 + cell $gt $gt$libresoc.v:142480$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227992,10 +230489,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:140848$6503_Y + connect \Y $gt$libresoc.v:142480$6551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140849$6504 + cell $gt $gt$libresoc.v:142481$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228003,10 +230500,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:140849$6504_Y + connect \Y $gt$libresoc.v:142481$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140850$6505 + cell $gt $gt$libresoc.v:142482$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228014,10 +230511,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:140850$6505_Y + connect \Y $gt$libresoc.v:142482$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140851$6506 + cell $gt $gt$libresoc.v:142483$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228025,10 +230522,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:140851$6506_Y + connect \Y $gt$libresoc.v:142483$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140852$6507 + cell $gt $gt$libresoc.v:142484$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228036,10 +230533,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:140852$6507_Y + connect \Y $gt$libresoc.v:142484$6555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140853$6508 + cell $gt $gt$libresoc.v:142485$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228047,10 +230544,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:140853$6508_Y + connect \Y $gt$libresoc.v:142485$6556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140854$6509 + cell $gt $gt$libresoc.v:142486$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228058,10 +230555,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:140854$6509_Y + connect \Y $gt$libresoc.v:142486$6557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140855$6510 + cell $gt $gt$libresoc.v:142487$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228069,10 +230566,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:140855$6510_Y + connect \Y $gt$libresoc.v:142487$6558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140856$6511 + cell $gt $gt$libresoc.v:142488$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228080,10 +230577,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:140856$6511_Y + connect \Y $gt$libresoc.v:142488$6559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140857$6512 + cell $gt $gt$libresoc.v:142489$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228091,10 +230588,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:140857$6512_Y + connect \Y $gt$libresoc.v:142489$6560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140858$6513 + cell $gt $gt$libresoc.v:142490$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228102,10 +230599,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:140858$6513_Y + connect \Y $gt$libresoc.v:142490$6561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140859$6514 + cell $gt $gt$libresoc.v:142491$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228113,10 +230610,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:140859$6514_Y + connect \Y $gt$libresoc.v:142491$6562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140860$6515 + cell $gt $gt$libresoc.v:142492$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228124,10 +230621,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:140860$6515_Y + connect \Y $gt$libresoc.v:142492$6563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140861$6516 + cell $gt $gt$libresoc.v:142493$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228135,10 +230632,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:140861$6516_Y + connect \Y $gt$libresoc.v:142493$6564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140862$6517 + cell $gt $gt$libresoc.v:142494$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228146,10 +230643,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:140862$6517_Y + connect \Y $gt$libresoc.v:142494$6565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140863$6518 + cell $gt $gt$libresoc.v:142495$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228157,10 +230654,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:140863$6518_Y + connect \Y $gt$libresoc.v:142495$6566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140864$6519 + cell $gt $gt$libresoc.v:142496$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228168,10 +230665,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:140864$6519_Y + connect \Y $gt$libresoc.v:142496$6567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140865$6520 + cell $gt $gt$libresoc.v:142497$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228179,10 +230676,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:140865$6520_Y + connect \Y $gt$libresoc.v:142497$6568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140866$6521 + cell $gt $gt$libresoc.v:142498$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228190,10 +230687,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:140866$6521_Y + connect \Y $gt$libresoc.v:142498$6569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140867$6522 + cell $gt $gt$libresoc.v:142499$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228201,10 +230698,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:140867$6522_Y + connect \Y $gt$libresoc.v:142499$6570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140868$6523 + cell $gt $gt$libresoc.v:142500$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228212,10 +230709,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:140868$6523_Y + connect \Y $gt$libresoc.v:142500$6571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140869$6524 + cell $gt $gt$libresoc.v:142501$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228223,10 +230720,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:140869$6524_Y + connect \Y $gt$libresoc.v:142501$6572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140870$6525 + cell $gt $gt$libresoc.v:142502$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228234,10 +230731,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:140870$6525_Y + connect \Y $gt$libresoc.v:142502$6573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140871$6526 + cell $gt $gt$libresoc.v:142503$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228245,10 +230742,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:140871$6526_Y + connect \Y $gt$libresoc.v:142503$6574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140872$6527 + cell $gt $gt$libresoc.v:142504$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228256,10 +230753,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:140872$6527_Y + connect \Y $gt$libresoc.v:142504$6575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140873$6528 + cell $gt $gt$libresoc.v:142505$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228267,10 +230764,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:140873$6528_Y + connect \Y $gt$libresoc.v:142505$6576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140874$6529 + cell $gt $gt$libresoc.v:142506$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228278,10 +230775,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:140874$6529_Y + connect \Y $gt$libresoc.v:142506$6577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140875$6530 + cell $gt $gt$libresoc.v:142507$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228289,10 +230786,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:140875$6530_Y + connect \Y $gt$libresoc.v:142507$6578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140876$6531 + cell $gt $gt$libresoc.v:142508$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228300,10 +230797,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:140876$6531_Y + connect \Y $gt$libresoc.v:142508$6579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140877$6532 + cell $gt $gt$libresoc.v:142509$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228311,10 +230808,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:140877$6532_Y + connect \Y $gt$libresoc.v:142509$6580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140878$6533 + cell $gt $gt$libresoc.v:142510$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228322,10 +230819,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:140878$6533_Y + connect \Y $gt$libresoc.v:142510$6581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140879$6534 + cell $gt $gt$libresoc.v:142511$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228333,10 +230830,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:140879$6534_Y + connect \Y $gt$libresoc.v:142511$6582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140880$6535 + cell $gt $gt$libresoc.v:142512$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228344,10 +230841,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:140880$6535_Y + connect \Y $gt$libresoc.v:142512$6583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140881$6536 + cell $gt $gt$libresoc.v:142513$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228355,10 +230852,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:140881$6536_Y + connect \Y $gt$libresoc.v:142513$6584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140882$6537 + cell $gt $gt$libresoc.v:142514$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228366,10 +230863,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:140882$6537_Y + connect \Y $gt$libresoc.v:142514$6585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140883$6538 + cell $gt $gt$libresoc.v:142515$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228377,10 +230874,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:140883$6538_Y + connect \Y $gt$libresoc.v:142515$6586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140884$6539 + cell $gt $gt$libresoc.v:142516$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228388,10 +230885,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:140884$6539_Y + connect \Y $gt$libresoc.v:142516$6587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140885$6540 + cell $gt $gt$libresoc.v:142517$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228399,10 +230896,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:140885$6540_Y + connect \Y $gt$libresoc.v:142517$6588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:140886$6541 + cell $gt $gt$libresoc.v:142518$6589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -228410,18 +230907,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:140886$6541_Y + connect \Y $gt$libresoc.v:142518$6589_Y end - attribute \src "libresoc.v:140689.7-140689.20" - process $proc$libresoc.v:140689$6543 + attribute \src "libresoc.v:142321.7-142321.20" + process $proc$libresoc.v:142321$6591 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140887.3-141274.6" - process $proc$libresoc.v:140887$6542 + attribute \src "libresoc.v:142519.3-142906.6" + process $proc$libresoc.v:142519$6590 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -228488,9 +230985,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:140888.5-140888.29" + attribute \src "libresoc.v:142520.5-142520.29" switch \initial - attribute \src "libresoc.v:140888.9-140888.17" + attribute \src "libresoc.v:142520.9-142520.17" case 1'1 case end @@ -229073,86 +231570,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:140823$6478_Y - connect \$99 $gt$libresoc.v:140824$6479_Y - connect \$101 $gt$libresoc.v:140825$6480_Y - connect \$103 $gt$libresoc.v:140826$6481_Y - connect \$105 $gt$libresoc.v:140827$6482_Y - connect \$107 $gt$libresoc.v:140828$6483_Y - connect \$109 $gt$libresoc.v:140829$6484_Y - connect \$111 $gt$libresoc.v:140830$6485_Y - connect \$113 $gt$libresoc.v:140831$6486_Y - connect \$115 $gt$libresoc.v:140832$6487_Y - connect \$117 $gt$libresoc.v:140833$6488_Y - connect \$11 $gt$libresoc.v:140834$6489_Y - connect \$119 $gt$libresoc.v:140835$6490_Y - connect \$121 $gt$libresoc.v:140836$6491_Y - connect \$123 $gt$libresoc.v:140837$6492_Y - connect \$125 $gt$libresoc.v:140838$6493_Y - connect \$127 $gt$libresoc.v:140839$6494_Y - connect \$13 $gt$libresoc.v:140840$6495_Y - connect \$15 $gt$libresoc.v:140841$6496_Y - connect \$17 $gt$libresoc.v:140842$6497_Y - connect \$1 $gt$libresoc.v:140843$6498_Y - connect \$19 $gt$libresoc.v:140844$6499_Y - connect \$21 $gt$libresoc.v:140845$6500_Y - connect \$23 $gt$libresoc.v:140846$6501_Y - connect \$25 $gt$libresoc.v:140847$6502_Y - connect \$27 $gt$libresoc.v:140848$6503_Y - connect \$29 $gt$libresoc.v:140849$6504_Y - connect \$31 $gt$libresoc.v:140850$6505_Y - connect \$33 $gt$libresoc.v:140851$6506_Y - connect \$35 $gt$libresoc.v:140852$6507_Y - connect \$37 $gt$libresoc.v:140853$6508_Y - connect \$3 $gt$libresoc.v:140854$6509_Y - connect \$39 $gt$libresoc.v:140855$6510_Y - connect \$41 $gt$libresoc.v:140856$6511_Y - connect \$43 $gt$libresoc.v:140857$6512_Y - connect \$45 $gt$libresoc.v:140858$6513_Y - connect \$47 $gt$libresoc.v:140859$6514_Y - connect \$49 $gt$libresoc.v:140860$6515_Y - connect \$51 $gt$libresoc.v:140861$6516_Y - connect \$53 $gt$libresoc.v:140862$6517_Y - connect \$55 $gt$libresoc.v:140863$6518_Y - connect \$57 $gt$libresoc.v:140864$6519_Y - connect \$5 $gt$libresoc.v:140865$6520_Y - connect \$59 $gt$libresoc.v:140866$6521_Y - connect \$61 $gt$libresoc.v:140867$6522_Y - connect \$63 $gt$libresoc.v:140868$6523_Y - connect \$65 $gt$libresoc.v:140869$6524_Y - connect \$67 $gt$libresoc.v:140870$6525_Y - connect \$69 $gt$libresoc.v:140871$6526_Y - connect \$71 $gt$libresoc.v:140872$6527_Y - connect \$73 $gt$libresoc.v:140873$6528_Y - connect \$75 $gt$libresoc.v:140874$6529_Y - connect \$77 $gt$libresoc.v:140875$6530_Y - connect \$7 $gt$libresoc.v:140876$6531_Y - connect \$79 $gt$libresoc.v:140877$6532_Y - connect \$81 $gt$libresoc.v:140878$6533_Y - connect \$83 $gt$libresoc.v:140879$6534_Y - connect \$85 $gt$libresoc.v:140880$6535_Y - connect \$87 $gt$libresoc.v:140881$6536_Y - connect \$89 $gt$libresoc.v:140882$6537_Y - connect \$91 $gt$libresoc.v:140883$6538_Y - connect \$93 $gt$libresoc.v:140884$6539_Y - connect \$95 $gt$libresoc.v:140885$6540_Y - connect \$97 $gt$libresoc.v:140886$6541_Y + connect \$9 $gt$libresoc.v:142455$6526_Y + connect \$99 $gt$libresoc.v:142456$6527_Y + connect \$101 $gt$libresoc.v:142457$6528_Y + connect \$103 $gt$libresoc.v:142458$6529_Y + connect \$105 $gt$libresoc.v:142459$6530_Y + connect \$107 $gt$libresoc.v:142460$6531_Y + connect \$109 $gt$libresoc.v:142461$6532_Y + connect \$111 $gt$libresoc.v:142462$6533_Y + connect \$113 $gt$libresoc.v:142463$6534_Y + connect \$115 $gt$libresoc.v:142464$6535_Y + connect \$117 $gt$libresoc.v:142465$6536_Y + connect \$11 $gt$libresoc.v:142466$6537_Y + connect \$119 $gt$libresoc.v:142467$6538_Y + connect \$121 $gt$libresoc.v:142468$6539_Y + connect \$123 $gt$libresoc.v:142469$6540_Y + connect \$125 $gt$libresoc.v:142470$6541_Y + connect \$127 $gt$libresoc.v:142471$6542_Y + connect \$13 $gt$libresoc.v:142472$6543_Y + connect \$15 $gt$libresoc.v:142473$6544_Y + connect \$17 $gt$libresoc.v:142474$6545_Y + connect \$1 $gt$libresoc.v:142475$6546_Y + connect \$19 $gt$libresoc.v:142476$6547_Y + connect \$21 $gt$libresoc.v:142477$6548_Y + connect \$23 $gt$libresoc.v:142478$6549_Y + connect \$25 $gt$libresoc.v:142479$6550_Y + connect \$27 $gt$libresoc.v:142480$6551_Y + connect \$29 $gt$libresoc.v:142481$6552_Y + connect \$31 $gt$libresoc.v:142482$6553_Y + connect \$33 $gt$libresoc.v:142483$6554_Y + connect \$35 $gt$libresoc.v:142484$6555_Y + connect \$37 $gt$libresoc.v:142485$6556_Y + connect \$3 $gt$libresoc.v:142486$6557_Y + connect \$39 $gt$libresoc.v:142487$6558_Y + connect \$41 $gt$libresoc.v:142488$6559_Y + connect \$43 $gt$libresoc.v:142489$6560_Y + connect \$45 $gt$libresoc.v:142490$6561_Y + connect \$47 $gt$libresoc.v:142491$6562_Y + connect \$49 $gt$libresoc.v:142492$6563_Y + connect \$51 $gt$libresoc.v:142493$6564_Y + connect \$53 $gt$libresoc.v:142494$6565_Y + connect \$55 $gt$libresoc.v:142495$6566_Y + connect \$57 $gt$libresoc.v:142496$6567_Y + connect \$5 $gt$libresoc.v:142497$6568_Y + connect \$59 $gt$libresoc.v:142498$6569_Y + connect \$61 $gt$libresoc.v:142499$6570_Y + connect \$63 $gt$libresoc.v:142500$6571_Y + connect \$65 $gt$libresoc.v:142501$6572_Y + connect \$67 $gt$libresoc.v:142502$6573_Y + connect \$69 $gt$libresoc.v:142503$6574_Y + connect \$71 $gt$libresoc.v:142504$6575_Y + connect \$73 $gt$libresoc.v:142505$6576_Y + connect \$75 $gt$libresoc.v:142506$6577_Y + connect \$77 $gt$libresoc.v:142507$6578_Y + connect \$7 $gt$libresoc.v:142508$6579_Y + connect \$79 $gt$libresoc.v:142509$6580_Y + connect \$81 $gt$libresoc.v:142510$6581_Y + connect \$83 $gt$libresoc.v:142511$6582_Y + connect \$85 $gt$libresoc.v:142512$6583_Y + connect \$87 $gt$libresoc.v:142513$6584_Y + connect \$89 $gt$libresoc.v:142514$6585_Y + connect \$91 $gt$libresoc.v:142515$6586_Y + connect \$93 $gt$libresoc.v:142516$6587_Y + connect \$95 $gt$libresoc.v:142517$6588_Y + connect \$97 $gt$libresoc.v:142518$6589_Y end -attribute \src "libresoc.v:141279.1-141308.10" +attribute \src "libresoc.v:142911.1-142940.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:141303.17-141303.101" - wire width 64 $extend$libresoc.v:141303$6547_Y - attribute \src "libresoc.v:141303.17-141303.101" - wire width 64 $pos$libresoc.v:141303$6548_Y - attribute \src "libresoc.v:141300.17-141300.111" - wire width 20 $sshl$libresoc.v:141300$6544_Y - attribute \src "libresoc.v:141302.17-141302.113" - wire width 32 $sshl$libresoc.v:141302$6546_Y - attribute \src "libresoc.v:141301.17-141301.107" - wire width 21 $sub$libresoc.v:141301$6545_Y + attribute \src "libresoc.v:142935.17-142935.101" + wire width 64 $extend$libresoc.v:142935$6595_Y + attribute \src "libresoc.v:142935.17-142935.101" + wire width 64 $pos$libresoc.v:142935$6596_Y + attribute \src "libresoc.v:142932.17-142932.111" + wire width 20 $sshl$libresoc.v:142932$6592_Y + attribute \src "libresoc.v:142934.17-142934.113" + wire width 32 $sshl$libresoc.v:142934$6594_Y + attribute \src "libresoc.v:142933.17-142933.107" + wire width 21 $sub$libresoc.v:142933$6593_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -229174,23 +231671,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:141303$6547 + cell $pos $extend$libresoc.v:142935$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:141303$6547_Y + connect \Y $extend$libresoc.v:142935$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:141303$6548 + cell $pos $pos$libresoc.v:142935$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141303$6547_Y - connect \Y $pos$libresoc.v:141303$6548_Y + connect \A $extend$libresoc.v:142935$6595_Y + connect \Y $pos$libresoc.v:142935$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:141300$6544 + cell $sshl $sshl$libresoc.v:142932$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -229198,10 +231695,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:141300$6544_Y + connect \Y $sshl$libresoc.v:142932$6592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:141302$6546 + cell $sshl $sshl$libresoc.v:142934$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -229209,10 +231706,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:141302$6546_Y + connect \Y $sshl$libresoc.v:142934$6594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:141301$6545 + cell $sub $sub$libresoc.v:142933$6593 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -229220,48 +231717,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:141301$6545_Y + connect \Y $sub$libresoc.v:142933$6593_Y end - connect \$2 $sshl$libresoc.v:141300$6544_Y - connect \$4 $sub$libresoc.v:141301$6545_Y - connect \$7 $sshl$libresoc.v:141302$6546_Y - connect \$6 $pos$libresoc.v:141303$6548_Y + connect \$2 $sshl$libresoc.v:142932$6592_Y + connect \$4 $sub$libresoc.v:142933$6593_Y + connect \$7 $sshl$libresoc.v:142934$6594_Y + connect \$6 $pos$libresoc.v:142935$6596_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:141312.1-141370.10" +attribute \src "libresoc.v:142944.1-143002.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:141313.7-141313.20" + attribute \src "libresoc.v:142945.7-142945.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141358.3-141366.6" - wire $0\q_int$next[0:0]$6559 - attribute \src "libresoc.v:141356.3-141357.27" + attribute \src "libresoc.v:142990.3-142998.6" + wire $0\q_int$next[0:0]$6607 + attribute \src "libresoc.v:142988.3-142989.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:141358.3-141366.6" - wire $1\q_int$next[0:0]$6560 - attribute \src "libresoc.v:141335.7-141335.19" + attribute \src "libresoc.v:142990.3-142998.6" + wire $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142967.7-142967.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:141348.17-141348.96" - wire $and$libresoc.v:141348$6549_Y - attribute \src "libresoc.v:141353.17-141353.96" - wire $and$libresoc.v:141353$6554_Y - attribute \src "libresoc.v:141350.18-141350.93" - wire $not$libresoc.v:141350$6551_Y - attribute \src "libresoc.v:141352.17-141352.92" - wire $not$libresoc.v:141352$6553_Y - attribute \src "libresoc.v:141355.17-141355.92" - wire $not$libresoc.v:141355$6556_Y - attribute \src "libresoc.v:141349.18-141349.98" - wire $or$libresoc.v:141349$6550_Y - attribute \src "libresoc.v:141351.18-141351.99" - wire $or$libresoc.v:141351$6552_Y - attribute \src "libresoc.v:141354.17-141354.97" - wire $or$libresoc.v:141354$6555_Y + attribute \src "libresoc.v:142980.17-142980.96" + wire $and$libresoc.v:142980$6597_Y + attribute \src "libresoc.v:142985.17-142985.96" + wire $and$libresoc.v:142985$6602_Y + attribute \src "libresoc.v:142982.18-142982.93" + wire $not$libresoc.v:142982$6599_Y + attribute \src "libresoc.v:142984.17-142984.92" + wire $not$libresoc.v:142984$6601_Y + attribute \src "libresoc.v:142987.17-142987.92" + wire $not$libresoc.v:142987$6604_Y + attribute \src "libresoc.v:142981.18-142981.98" + wire $or$libresoc.v:142981$6598_Y + attribute \src "libresoc.v:142983.18-142983.99" + wire $or$libresoc.v:142983$6600_Y + attribute \src "libresoc.v:142986.17-142986.97" + wire $or$libresoc.v:142986$6603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -229278,11 +231775,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:141313.7-141313.15" + attribute \src "libresoc.v:142945.7-142945.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -229299,7 +231796,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:141348$6549 + cell $and $and$libresoc.v:142980$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229307,10 +231804,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:141348$6549_Y + connect \Y $and$libresoc.v:142980$6597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:141353$6554 + cell $and $and$libresoc.v:142985$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229318,34 +231815,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:141353$6554_Y + connect \Y $and$libresoc.v:142985$6602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:141350$6551 + cell $not $not$libresoc.v:142982$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:141350$6551_Y + connect \Y $not$libresoc.v:142982$6599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:141352$6553 + cell $not $not$libresoc.v:142984$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:141352$6553_Y + connect \Y $not$libresoc.v:142984$6601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:141355$6556 + cell $not $not$libresoc.v:142987$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:141355$6556_Y + connect \Y $not$libresoc.v:142987$6604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:141349$6550 + cell $or $or$libresoc.v:142981$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229353,10 +231850,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:141349$6550_Y + connect \Y $or$libresoc.v:142981$6598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:141351$6552 + cell $or $or$libresoc.v:142983$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229364,10 +231861,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:141351$6552_Y + connect \Y $or$libresoc.v:142983$6600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:141354$6555 + cell $or $or$libresoc.v:142986$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -229375,39 +231872,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:141354$6555_Y + connect \Y $or$libresoc.v:142986$6603_Y end - attribute \src "libresoc.v:141313.7-141313.20" - process $proc$libresoc.v:141313$6561 + attribute \src "libresoc.v:142945.7-142945.20" + process $proc$libresoc.v:142945$6609 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141335.7-141335.19" - process $proc$libresoc.v:141335$6562 + attribute \src "libresoc.v:142967.7-142967.19" + process $proc$libresoc.v:142967$6610 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:141356.3-141357.27" - process $proc$libresoc.v:141356$6557 + attribute \src "libresoc.v:142988.3-142989.27" + process $proc$libresoc.v:142988$6605 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:141358.3-141366.6" - process $proc$libresoc.v:141358$6558 + attribute \src "libresoc.v:142990.3-142998.6" + process $proc$libresoc.v:142990$6606 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6559 $1\q_int$next[0:0]$6560 - attribute \src "libresoc.v:141359.5-141359.29" + assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 + attribute \src "libresoc.v:142991.5-142991.29" switch \initial - attribute \src "libresoc.v:141359.9-141359.17" + attribute \src "libresoc.v:142991.9-142991.17" case 1'1 case end @@ -229416,494 +231913,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6560 1'0 + assign $1\q_int$next[0:0]$6608 1'0 case - assign $1\q_int$next[0:0]$6560 \$5 + assign $1\q_int$next[0:0]$6608 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6559 + update \q_int$next $0\q_int$next[0:0]$6607 end - connect \$9 $and$libresoc.v:141348$6549_Y - connect \$11 $or$libresoc.v:141349$6550_Y - connect \$13 $not$libresoc.v:141350$6551_Y - connect \$15 $or$libresoc.v:141351$6552_Y - connect \$1 $not$libresoc.v:141352$6553_Y - connect \$3 $and$libresoc.v:141353$6554_Y - connect \$5 $or$libresoc.v:141354$6555_Y - connect \$7 $not$libresoc.v:141355$6556_Y + connect \$9 $and$libresoc.v:142980$6597_Y + connect \$11 $or$libresoc.v:142981$6598_Y + connect \$13 $not$libresoc.v:142982$6599_Y + connect \$15 $or$libresoc.v:142983$6600_Y + connect \$1 $not$libresoc.v:142984$6601_Y + connect \$3 $and$libresoc.v:142985$6602_Y + connect \$5 $or$libresoc.v:142986$6603_Y + connect \$7 $not$libresoc.v:142987$6604_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:141374.1-142494.10" +attribute \src "libresoc.v:143006.1-144126.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:142119.3-142120.24" + attribute \src "libresoc.v:143751.3-143752.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:142117.3-142118.44" + attribute \src "libresoc.v:143749.3-143750.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:142424.3-142432.6" - wire $0\alu_l_r_alu$next[0:0]$6763 - attribute \src "libresoc.v:142041.3-142042.39" + attribute \src "libresoc.v:144056.3-144064.6" + wire $0\alu_l_r_alu$next[0:0]$6811 + attribute \src "libresoc.v:143673.3-143674.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6692 - attribute \src "libresoc.v:142091.3-142092.83" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + attribute \src "libresoc.v:143723.3-143724.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 - attribute \src "libresoc.v:142061.3-142062.81" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + attribute \src "libresoc.v:143693.3-143694.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 - attribute \src "libresoc.v:142063.3-142064.95" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + attribute \src "libresoc.v:143695.3-143696.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 - attribute \src "libresoc.v:142065.3-142066.91" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + attribute \src "libresoc.v:143697.3-143698.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 - attribute \src "libresoc.v:142079.3-142080.89" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + attribute \src "libresoc.v:143711.3-143712.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6697 - attribute \src "libresoc.v:142093.3-142094.75" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 + attribute \src "libresoc.v:143725.3-143726.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 - attribute \src "libresoc.v:142059.3-142060.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + attribute \src "libresoc.v:143691.3-143692.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 - attribute \src "libresoc.v:142075.3-142076.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + attribute \src "libresoc.v:143707.3-143708.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 - attribute \src "libresoc.v:142081.3-142082.87" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + attribute \src "libresoc.v:143713.3-143714.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 - attribute \src "libresoc.v:142087.3-142088.83" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + attribute \src "libresoc.v:143719.3-143720.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 - attribute \src "libresoc.v:142089.3-142090.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + attribute \src "libresoc.v:143721.3-143722.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 - attribute \src "libresoc.v:142071.3-142072.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + attribute \src "libresoc.v:143703.3-143704.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 - attribute \src "libresoc.v:142073.3-142074.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + attribute \src "libresoc.v:143705.3-143706.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 - attribute \src "libresoc.v:142085.3-142086.91" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + attribute \src "libresoc.v:143717.3-143718.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 - attribute \src "libresoc.v:142069.3-142070.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + attribute \src "libresoc.v:143701.3-143702.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 - attribute \src "libresoc.v:142067.3-142068.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + attribute \src "libresoc.v:143699.3-143700.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 - attribute \src "libresoc.v:142083.3-142084.85" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + attribute \src "libresoc.v:143715.3-143716.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 - attribute \src "libresoc.v:142077.3-142078.79" + attribute \src "libresoc.v:143934.3-143972.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + attribute \src "libresoc.v:143709.3-143710.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:142415.3-142423.6" - wire $0\alui_l_r_alui$next[0:0]$6760 - attribute \src "libresoc.v:142043.3-142044.43" + attribute \src "libresoc.v:144047.3-144055.6" + wire $0\alui_l_r_alui$next[0:0]$6808 + attribute \src "libresoc.v:143675.3-143676.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $0\data_r0__o$next[63:0]$6735 - attribute \src "libresoc.v:142055.3-142056.37" + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $0\data_r0__o$next[63:0]$6783 + attribute \src "libresoc.v:143687.3-143688.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire $0\data_r0__o_ok$next[0:0]$6736 - attribute \src "libresoc.v:142057.3-142058.43" + attribute \src "libresoc.v:143973.3-143994.6" + wire $0\data_r0__o_ok$next[0:0]$6784 + attribute \src "libresoc.v:143689.3-143690.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6743 - attribute \src "libresoc.v:142051.3-142052.43" + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6791 + attribute \src "libresoc.v:143683.3-143684.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6744 - attribute \src "libresoc.v:142053.3-142054.49" + attribute \src "libresoc.v:143995.3-144016.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6792 + attribute \src "libresoc.v:143685.3-143686.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:142433.3-142442.6" + attribute \src "libresoc.v:144065.3-144074.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142443.3-142452.6" + attribute \src "libresoc.v:144075.3-144084.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:141375.7-141375.20" + attribute \src "libresoc.v:143007.7-143007.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142257.3-142265.6" - wire $0\opc_l_r_opc$next[0:0]$6677 - attribute \src "libresoc.v:142103.3-142104.39" + attribute \src "libresoc.v:143889.3-143897.6" + wire $0\opc_l_r_opc$next[0:0]$6725 + attribute \src "libresoc.v:143735.3-143736.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142248.3-142256.6" - wire $0\opc_l_s_opc$next[0:0]$6674 - attribute \src "libresoc.v:142105.3-142106.39" + attribute \src "libresoc.v:143880.3-143888.6" + wire $0\opc_l_s_opc$next[0:0]$6722 + attribute \src "libresoc.v:143737.3-143738.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142453.3-142461.6" - wire width 2 $0\prev_wr_go$next[1:0]$6768 - attribute \src "libresoc.v:142115.3-142116.37" + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $0\prev_wr_go$next[1:0]$6816 + attribute \src "libresoc.v:143747.3-143748.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:142202.3-142211.6" + attribute \src "libresoc.v:143834.3-143843.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:142293.3-142301.6" - wire width 2 $0\req_l_r_req$next[1:0]$6689 - attribute \src "libresoc.v:142095.3-142096.39" + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $0\req_l_r_req$next[1:0]$6737 + attribute \src "libresoc.v:143727.3-143728.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:142284.3-142292.6" - wire width 2 $0\req_l_s_req$next[1:0]$6686 - attribute \src "libresoc.v:142097.3-142098.39" + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $0\req_l_s_req$next[1:0]$6734 + attribute \src "libresoc.v:143729.3-143730.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:142221.3-142229.6" - wire $0\rok_l_r_rdok$next[0:0]$6665 - attribute \src "libresoc.v:142111.3-142112.41" + attribute \src "libresoc.v:143853.3-143861.6" + wire $0\rok_l_r_rdok$next[0:0]$6713 + attribute \src "libresoc.v:143743.3-143744.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:142212.3-142220.6" - wire $0\rok_l_s_rdok$next[0:0]$6662 - attribute \src "libresoc.v:142113.3-142114.41" + attribute \src "libresoc.v:143844.3-143852.6" + wire $0\rok_l_s_rdok$next[0:0]$6710 + attribute \src "libresoc.v:143745.3-143746.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:142239.3-142247.6" - wire $0\rst_l_r_rst$next[0:0]$6671 - attribute \src "libresoc.v:142107.3-142108.39" + attribute \src "libresoc.v:143871.3-143879.6" + wire $0\rst_l_r_rst$next[0:0]$6719 + attribute \src "libresoc.v:143739.3-143740.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:142230.3-142238.6" - wire $0\rst_l_s_rst$next[0:0]$6668 - attribute \src "libresoc.v:142109.3-142110.39" + attribute \src "libresoc.v:143862.3-143870.6" + wire $0\rst_l_s_rst$next[0:0]$6716 + attribute \src "libresoc.v:143741.3-143742.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:142275.3-142283.6" - wire width 3 $0\src_l_r_src$next[2:0]$6683 - attribute \src "libresoc.v:142099.3-142100.39" + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $0\src_l_r_src$next[2:0]$6731 + attribute \src "libresoc.v:143731.3-143732.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:142266.3-142274.6" - wire width 3 $0\src_l_s_src$next[2:0]$6680 - attribute \src "libresoc.v:142101.3-142102.39" + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $0\src_l_s_src$next[2:0]$6728 + attribute \src "libresoc.v:143733.3-143734.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142385.3-142394.6" - wire width 64 $0\src_r0$next[63:0]$6751 - attribute \src "libresoc.v:142049.3-142050.29" + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $0\src_r0$next[63:0]$6799 + attribute \src "libresoc.v:143681.3-143682.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142395.3-142404.6" - wire width 64 $0\src_r1$next[63:0]$6754 - attribute \src "libresoc.v:142047.3-142048.29" + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $0\src_r1$next[63:0]$6802 + attribute \src "libresoc.v:143679.3-143680.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142405.3-142414.6" - wire $0\src_r2$next[0:0]$6757 - attribute \src "libresoc.v:142045.3-142046.29" + attribute \src "libresoc.v:144037.3-144046.6" + wire $0\src_r2$next[0:0]$6805 + attribute \src "libresoc.v:143677.3-143678.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:141493.7-141493.24" + attribute \src "libresoc.v:143125.7-143125.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:141503.7-141503.26" + attribute \src "libresoc.v:143135.7-143135.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:142424.3-142432.6" - wire $1\alu_l_r_alu$next[0:0]$6764 - attribute \src "libresoc.v:141511.7-141511.25" + attribute \src "libresoc.v:144056.3-144064.6" + wire $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:143143.7-143143.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 - attribute \src "libresoc.v:141519.13-141519.53" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + attribute \src "libresoc.v:143151.13-143151.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 - attribute \src "libresoc.v:141538.14-141538.57" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + attribute \src "libresoc.v:143170.14-143170.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 - attribute \src "libresoc.v:141542.14-141542.76" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + attribute \src "libresoc.v:143174.14-143174.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 - attribute \src "libresoc.v:141546.7-141546.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + attribute \src "libresoc.v:143178.7-143178.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 - attribute \src "libresoc.v:141554.13-141554.56" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + attribute \src "libresoc.v:143186.13-143186.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6715 - attribute \src "libresoc.v:141558.14-141558.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + attribute \src "libresoc.v:143190.14-143190.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 - attribute \src "libresoc.v:141637.13-141637.55" + attribute \src "libresoc.v:143934.3-143972.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + attribute \src "libresoc.v:143269.13-143269.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 - attribute \src "libresoc.v:141641.7-141641.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + attribute \src "libresoc.v:143273.7-143273.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 - attribute \src "libresoc.v:141645.7-141645.49" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + attribute \src "libresoc.v:143277.7-143277.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 - attribute \src "libresoc.v:141649.7-141649.47" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + attribute \src "libresoc.v:143281.7-143281.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 - attribute \src "libresoc.v:141653.7-141653.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + attribute \src "libresoc.v:143285.7-143285.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 - attribute \src "libresoc.v:141657.7-141657.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + attribute \src "libresoc.v:143289.7-143289.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 - attribute \src "libresoc.v:141661.7-141661.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + attribute \src "libresoc.v:143293.7-143293.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 - attribute \src "libresoc.v:141665.7-141665.51" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + attribute \src "libresoc.v:143297.7-143297.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 - attribute \src "libresoc.v:141669.7-141669.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + attribute \src "libresoc.v:143301.7-143301.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 - attribute \src "libresoc.v:141673.7-141673.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + attribute \src "libresoc.v:143305.7-143305.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 - attribute \src "libresoc.v:141677.7-141677.48" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + attribute \src "libresoc.v:143309.7-143309.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 - attribute \src "libresoc.v:141681.7-141681.45" + attribute \src "libresoc.v:143934.3-143972.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + attribute \src "libresoc.v:143313.7-143313.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:142415.3-142423.6" - wire $1\alui_l_r_alui$next[0:0]$6761 - attribute \src "libresoc.v:141707.7-141707.27" + attribute \src "libresoc.v:144047.3-144055.6" + wire $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:143339.7-143339.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $1\data_r0__o$next[63:0]$6737 - attribute \src "libresoc.v:141741.14-141741.47" + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $1\data_r0__o$next[63:0]$6785 + attribute \src "libresoc.v:143373.14-143373.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:142341.3-142362.6" - wire $1\data_r0__o_ok$next[0:0]$6738 - attribute \src "libresoc.v:141745.7-141745.27" + attribute \src "libresoc.v:143973.3-143994.6" + wire $1\data_r0__o_ok$next[0:0]$6786 + attribute \src "libresoc.v:143377.7-143377.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6745 - attribute \src "libresoc.v:141749.13-141749.33" + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6793 + attribute \src "libresoc.v:143381.13-143381.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:142363.3-142384.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6746 - attribute \src "libresoc.v:141753.7-141753.30" + attribute \src "libresoc.v:143995.3-144016.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6794 + attribute \src "libresoc.v:143385.7-143385.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:142433.3-142442.6" + attribute \src "libresoc.v:144065.3-144074.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142443.3-142452.6" + attribute \src "libresoc.v:144075.3-144084.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:142257.3-142265.6" - wire $1\opc_l_r_opc$next[0:0]$6678 - attribute \src "libresoc.v:141767.7-141767.25" + attribute \src "libresoc.v:143889.3-143897.6" + wire $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143399.7-143399.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:142248.3-142256.6" - wire $1\opc_l_s_opc$next[0:0]$6675 - attribute \src "libresoc.v:141771.7-141771.25" + attribute \src "libresoc.v:143880.3-143888.6" + wire $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143403.7-143403.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142453.3-142461.6" - wire width 2 $1\prev_wr_go$next[1:0]$6769 - attribute \src "libresoc.v:141905.13-141905.30" + attribute \src "libresoc.v:144085.3-144093.6" + wire width 2 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:143537.13-143537.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:142202.3-142211.6" + attribute \src "libresoc.v:143834.3-143843.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:142293.3-142301.6" - wire width 2 $1\req_l_r_req$next[1:0]$6690 - attribute \src "libresoc.v:141913.13-141913.31" + attribute \src "libresoc.v:143925.3-143933.6" + wire width 2 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143545.13-143545.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:142284.3-142292.6" - wire width 2 $1\req_l_s_req$next[1:0]$6687 - attribute \src "libresoc.v:141917.13-141917.31" + attribute \src "libresoc.v:143916.3-143924.6" + wire width 2 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143549.13-143549.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:142221.3-142229.6" - wire $1\rok_l_r_rdok$next[0:0]$6666 - attribute \src "libresoc.v:141929.7-141929.26" + attribute \src "libresoc.v:143853.3-143861.6" + wire $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143561.7-143561.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:142212.3-142220.6" - wire $1\rok_l_s_rdok$next[0:0]$6663 - attribute \src "libresoc.v:141933.7-141933.26" + attribute \src "libresoc.v:143844.3-143852.6" + wire $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143565.7-143565.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:142239.3-142247.6" - wire $1\rst_l_r_rst$next[0:0]$6672 - attribute \src "libresoc.v:141937.7-141937.25" + attribute \src "libresoc.v:143871.3-143879.6" + wire $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143569.7-143569.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:142230.3-142238.6" - wire $1\rst_l_s_rst$next[0:0]$6669 - attribute \src "libresoc.v:141941.7-141941.25" + attribute \src "libresoc.v:143862.3-143870.6" + wire $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143573.7-143573.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:142275.3-142283.6" - wire width 3 $1\src_l_r_src$next[2:0]$6684 - attribute \src "libresoc.v:141955.13-141955.31" + attribute \src "libresoc.v:143907.3-143915.6" + wire width 3 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143587.13-143587.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:142266.3-142274.6" - wire width 3 $1\src_l_s_src$next[2:0]$6681 - attribute \src "libresoc.v:141959.13-141959.31" + attribute \src "libresoc.v:143898.3-143906.6" + wire width 3 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143591.13-143591.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142385.3-142394.6" - wire width 64 $1\src_r0$next[63:0]$6752 - attribute \src "libresoc.v:141967.14-141967.43" + attribute \src "libresoc.v:144017.3-144026.6" + wire width 64 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:143599.14-143599.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142395.3-142404.6" - wire width 64 $1\src_r1$next[63:0]$6755 - attribute \src "libresoc.v:141971.14-141971.43" + attribute \src "libresoc.v:144027.3-144036.6" + wire width 64 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:143603.14-143603.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142405.3-142414.6" - wire $1\src_r2$next[0:0]$6758 - attribute \src "libresoc.v:141975.7-141975.20" + attribute \src "libresoc.v:144037.3-144046.6" + wire $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:143607.7-143607.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:142302.3-142340.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 - attribute \src "libresoc.v:142302.3-142340.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 - attribute \src "libresoc.v:142341.3-142362.6" - wire width 64 $2\data_r0__o$next[63:0]$6739 - attribute \src "libresoc.v:142341.3-142362.6" - wire $2\data_r0__o_ok$next[0:0]$6740 - attribute \src "libresoc.v:142363.3-142384.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6747 - attribute \src "libresoc.v:142363.3-142384.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6748 - attribute \src "libresoc.v:142341.3-142362.6" - wire $3\data_r0__o_ok$next[0:0]$6741 - attribute \src "libresoc.v:142363.3-142384.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6749 - attribute \src "libresoc.v:141984.17-141984.109" - wire $and$libresoc.v:141984$6563_Y - attribute \src "libresoc.v:141985.18-141985.130" - wire width 3 $and$libresoc.v:141985$6564_Y - attribute \src "libresoc.v:141987.19-141987.114" - wire width 3 $and$libresoc.v:141987$6566_Y - attribute \src "libresoc.v:141988.19-141988.125" - wire $and$libresoc.v:141988$6567_Y - attribute \src "libresoc.v:141989.19-141989.125" - wire $and$libresoc.v:141989$6568_Y - attribute \src "libresoc.v:141990.19-141990.133" - wire width 2 $and$libresoc.v:141990$6569_Y - attribute \src "libresoc.v:141991.19-141991.121" - wire width 2 $and$libresoc.v:141991$6570_Y - attribute \src "libresoc.v:141992.19-141992.127" - wire $and$libresoc.v:141992$6571_Y - attribute \src "libresoc.v:141993.19-141993.127" - wire $and$libresoc.v:141993$6572_Y - attribute \src "libresoc.v:141995.18-141995.98" - wire $and$libresoc.v:141995$6574_Y - attribute \src "libresoc.v:141997.18-141997.100" - wire $and$libresoc.v:141997$6576_Y - attribute \src "libresoc.v:141998.17-141998.123" - wire $and$libresoc.v:141998$6577_Y - attribute \src "libresoc.v:141999.18-141999.138" - wire width 2 $and$libresoc.v:141999$6578_Y - attribute \src "libresoc.v:142001.18-142001.119" - wire width 2 $and$libresoc.v:142001$6580_Y - attribute \src "libresoc.v:142004.18-142004.116" - wire $and$libresoc.v:142004$6583_Y - attribute \src "libresoc.v:142009.18-142009.113" - wire $and$libresoc.v:142009$6588_Y - attribute \src "libresoc.v:142010.18-142010.125" - wire width 2 $and$libresoc.v:142010$6589_Y - attribute \src "libresoc.v:142012.18-142012.112" - wire $and$libresoc.v:142012$6591_Y - attribute \src "libresoc.v:142015.18-142015.130" - wire $and$libresoc.v:142015$6594_Y - attribute \src "libresoc.v:142016.18-142016.130" - wire $and$libresoc.v:142016$6595_Y - attribute \src "libresoc.v:142017.18-142017.117" - wire $and$libresoc.v:142017$6596_Y - attribute \src "libresoc.v:142022.18-142022.134" - wire $and$libresoc.v:142022$6601_Y - attribute \src "libresoc.v:142023.18-142023.124" - wire width 2 $and$libresoc.v:142023$6602_Y - attribute \src "libresoc.v:142026.18-142026.116" - wire $and$libresoc.v:142026$6605_Y - attribute \src "libresoc.v:142027.18-142027.119" - wire $and$libresoc.v:142027$6606_Y - attribute \src "libresoc.v:142036.18-142036.138" - wire $and$libresoc.v:142036$6615_Y - attribute \src "libresoc.v:142037.18-142037.136" - wire $and$libresoc.v:142037$6616_Y - attribute \src "libresoc.v:142038.18-142038.149" - wire width 3 $and$libresoc.v:142038$6617_Y - attribute \src "libresoc.v:142011.18-142011.113" - wire $eq$libresoc.v:142011$6590_Y - attribute \src "libresoc.v:142013.18-142013.119" - wire $eq$libresoc.v:142013$6592_Y - attribute \src "libresoc.v:141986.19-141986.115" - wire width 3 $not$libresoc.v:141986$6565_Y - attribute \src "libresoc.v:141994.18-141994.97" - wire $not$libresoc.v:141994$6573_Y - attribute \src "libresoc.v:141996.18-141996.99" - wire $not$libresoc.v:141996$6575_Y - attribute \src "libresoc.v:142000.18-142000.113" - wire width 2 $not$libresoc.v:142000$6579_Y - attribute \src "libresoc.v:142003.18-142003.106" - wire $not$libresoc.v:142003$6582_Y - attribute \src "libresoc.v:142008.18-142008.124" - wire $not$libresoc.v:142008$6587_Y - attribute \src "libresoc.v:142014.17-142014.113" - wire width 3 $not$libresoc.v:142014$6593_Y - attribute \src "libresoc.v:142039.18-142039.133" - wire $not$libresoc.v:142039$6618_Y - attribute \src "libresoc.v:142040.18-142040.139" - wire $not$libresoc.v:142040$6619_Y - attribute \src "libresoc.v:142007.18-142007.112" - wire $or$libresoc.v:142007$6586_Y - attribute \src "libresoc.v:142018.18-142018.122" - wire $or$libresoc.v:142018$6597_Y - attribute \src "libresoc.v:142019.18-142019.124" - wire $or$libresoc.v:142019$6598_Y - attribute \src "libresoc.v:142020.18-142020.142" - wire width 2 $or$libresoc.v:142020$6599_Y - attribute \src "libresoc.v:142021.18-142021.155" - wire width 3 $or$libresoc.v:142021$6600_Y - attribute \src "libresoc.v:142024.18-142024.120" - wire width 2 $or$libresoc.v:142024$6603_Y - attribute \src "libresoc.v:142025.17-142025.117" - wire width 3 $or$libresoc.v:142025$6604_Y - attribute \src "libresoc.v:142031.17-142031.104" - wire $reduce_and$libresoc.v:142031$6610_Y - attribute \src "libresoc.v:142002.18-142002.106" - wire $reduce_or$libresoc.v:142002$6581_Y - attribute \src "libresoc.v:142005.18-142005.113" - wire $reduce_or$libresoc.v:142005$6584_Y - attribute \src "libresoc.v:142006.18-142006.112" - wire $reduce_or$libresoc.v:142006$6585_Y - attribute \src "libresoc.v:142028.18-142028.162" - wire $ternary$libresoc.v:142028$6607_Y - attribute \src "libresoc.v:142029.18-142029.163" - wire width 64 $ternary$libresoc.v:142029$6608_Y - attribute \src "libresoc.v:142030.18-142030.168" - wire $ternary$libresoc.v:142030$6609_Y - attribute \src "libresoc.v:142032.18-142032.188" - wire width 64 $ternary$libresoc.v:142032$6611_Y - attribute \src "libresoc.v:142033.18-142033.115" - wire width 64 $ternary$libresoc.v:142033$6612_Y - attribute \src "libresoc.v:142034.18-142034.125" - wire width 64 $ternary$libresoc.v:142034$6613_Y - attribute \src "libresoc.v:142035.18-142035.118" - wire $ternary$libresoc.v:142035$6614_Y + attribute \src "libresoc.v:143934.3-143972.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + attribute \src "libresoc.v:143934.3-143972.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143973.3-143994.6" + wire width 64 $2\data_r0__o$next[63:0]$6787 + attribute \src "libresoc.v:143973.3-143994.6" + wire $2\data_r0__o_ok$next[0:0]$6788 + attribute \src "libresoc.v:143995.3-144016.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6795 + attribute \src "libresoc.v:143995.3-144016.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6796 + attribute \src "libresoc.v:143973.3-143994.6" + wire $3\data_r0__o_ok$next[0:0]$6789 + attribute \src "libresoc.v:143995.3-144016.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6797 + attribute \src "libresoc.v:143616.17-143616.109" + wire $and$libresoc.v:143616$6611_Y + attribute \src "libresoc.v:143617.18-143617.130" + wire width 3 $and$libresoc.v:143617$6612_Y + attribute \src "libresoc.v:143619.19-143619.114" + wire width 3 $and$libresoc.v:143619$6614_Y + attribute \src "libresoc.v:143620.19-143620.125" + wire $and$libresoc.v:143620$6615_Y + attribute \src "libresoc.v:143621.19-143621.125" + wire $and$libresoc.v:143621$6616_Y + attribute \src "libresoc.v:143622.19-143622.133" + wire width 2 $and$libresoc.v:143622$6617_Y + attribute \src "libresoc.v:143623.19-143623.121" + wire width 2 $and$libresoc.v:143623$6618_Y + attribute \src "libresoc.v:143624.19-143624.127" + wire $and$libresoc.v:143624$6619_Y + attribute \src "libresoc.v:143625.19-143625.127" + wire $and$libresoc.v:143625$6620_Y + attribute \src "libresoc.v:143627.18-143627.98" + wire $and$libresoc.v:143627$6622_Y + attribute \src "libresoc.v:143629.18-143629.100" + wire $and$libresoc.v:143629$6624_Y + attribute \src "libresoc.v:143630.17-143630.123" + wire $and$libresoc.v:143630$6625_Y + attribute \src "libresoc.v:143631.18-143631.138" + wire width 2 $and$libresoc.v:143631$6626_Y + attribute \src "libresoc.v:143633.18-143633.119" + wire width 2 $and$libresoc.v:143633$6628_Y + attribute \src "libresoc.v:143636.18-143636.116" + wire $and$libresoc.v:143636$6631_Y + attribute \src "libresoc.v:143641.18-143641.113" + wire $and$libresoc.v:143641$6636_Y + attribute \src "libresoc.v:143642.18-143642.125" + wire width 2 $and$libresoc.v:143642$6637_Y + attribute \src "libresoc.v:143644.18-143644.112" + wire $and$libresoc.v:143644$6639_Y + attribute \src "libresoc.v:143647.18-143647.130" + wire $and$libresoc.v:143647$6642_Y + attribute \src "libresoc.v:143648.18-143648.130" + wire $and$libresoc.v:143648$6643_Y + attribute \src "libresoc.v:143649.18-143649.117" + wire $and$libresoc.v:143649$6644_Y + attribute \src "libresoc.v:143654.18-143654.134" + wire $and$libresoc.v:143654$6649_Y + attribute \src "libresoc.v:143655.18-143655.124" + wire width 2 $and$libresoc.v:143655$6650_Y + attribute \src "libresoc.v:143658.18-143658.116" + wire $and$libresoc.v:143658$6653_Y + attribute \src "libresoc.v:143659.18-143659.119" + wire $and$libresoc.v:143659$6654_Y + attribute \src "libresoc.v:143668.18-143668.138" + wire $and$libresoc.v:143668$6663_Y + attribute \src "libresoc.v:143669.18-143669.136" + wire $and$libresoc.v:143669$6664_Y + attribute \src "libresoc.v:143670.18-143670.149" + wire width 3 $and$libresoc.v:143670$6665_Y + attribute \src "libresoc.v:143643.18-143643.113" + wire $eq$libresoc.v:143643$6638_Y + attribute \src "libresoc.v:143645.18-143645.119" + wire $eq$libresoc.v:143645$6640_Y + attribute \src "libresoc.v:143618.19-143618.115" + wire width 3 $not$libresoc.v:143618$6613_Y + attribute \src "libresoc.v:143626.18-143626.97" + wire $not$libresoc.v:143626$6621_Y + attribute \src "libresoc.v:143628.18-143628.99" + wire $not$libresoc.v:143628$6623_Y + attribute \src "libresoc.v:143632.18-143632.113" + wire width 2 $not$libresoc.v:143632$6627_Y + attribute \src "libresoc.v:143635.18-143635.106" + wire $not$libresoc.v:143635$6630_Y + attribute \src "libresoc.v:143640.18-143640.124" + wire $not$libresoc.v:143640$6635_Y + attribute \src "libresoc.v:143646.17-143646.113" + wire width 3 $not$libresoc.v:143646$6641_Y + attribute \src "libresoc.v:143671.18-143671.133" + wire $not$libresoc.v:143671$6666_Y + attribute \src "libresoc.v:143672.18-143672.139" + wire $not$libresoc.v:143672$6667_Y + attribute \src "libresoc.v:143639.18-143639.112" + wire $or$libresoc.v:143639$6634_Y + attribute \src "libresoc.v:143650.18-143650.122" + wire $or$libresoc.v:143650$6645_Y + attribute \src "libresoc.v:143651.18-143651.124" + wire $or$libresoc.v:143651$6646_Y + attribute \src "libresoc.v:143652.18-143652.142" + wire width 2 $or$libresoc.v:143652$6647_Y + attribute \src "libresoc.v:143653.18-143653.155" + wire width 3 $or$libresoc.v:143653$6648_Y + attribute \src "libresoc.v:143656.18-143656.120" + wire width 2 $or$libresoc.v:143656$6651_Y + attribute \src "libresoc.v:143657.17-143657.117" + wire width 3 $or$libresoc.v:143657$6652_Y + attribute \src "libresoc.v:143663.17-143663.104" + wire $reduce_and$libresoc.v:143663$6658_Y + attribute \src "libresoc.v:143634.18-143634.106" + wire $reduce_or$libresoc.v:143634$6629_Y + attribute \src "libresoc.v:143637.18-143637.113" + wire $reduce_or$libresoc.v:143637$6632_Y + attribute \src "libresoc.v:143638.18-143638.112" + wire $reduce_or$libresoc.v:143638$6633_Y + attribute \src "libresoc.v:143660.18-143660.162" + wire $ternary$libresoc.v:143660$6655_Y + attribute \src "libresoc.v:143661.18-143661.163" + wire width 64 $ternary$libresoc.v:143661$6656_Y + attribute \src "libresoc.v:143662.18-143662.168" + wire $ternary$libresoc.v:143662$6657_Y + attribute \src "libresoc.v:143664.18-143664.188" + wire width 64 $ternary$libresoc.v:143664$6659_Y + attribute \src "libresoc.v:143665.18-143665.115" + wire width 64 $ternary$libresoc.v:143665$6660_Y + attribute \src "libresoc.v:143666.18-143666.125" + wire width 64 $ternary$libresoc.v:143666$6661_Y + attribute \src "libresoc.v:143667.18-143667.118" + wire $ternary$libresoc.v:143667$6662_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -230240,9 +232737,9 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -230288,7 +232785,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:141375.7-141375.15" + attribute \src "libresoc.v:143007.7-143007.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -230513,7 +233010,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:141984$6563 + cell $and $and$libresoc.v:143616$6611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230521,10 +233018,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:141984$6563_Y + connect \Y $and$libresoc.v:143616$6611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:141985$6564 + cell $and $and$libresoc.v:143617$6612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230532,10 +233029,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:141985$6564_Y + connect \Y $and$libresoc.v:143617$6612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:141987$6566 + cell $and $and$libresoc.v:143619$6614 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230543,10 +233040,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:141987$6566_Y + connect \Y $and$libresoc.v:143619$6614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:141988$6567 + cell $and $and$libresoc.v:143620$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230554,10 +233051,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141988$6567_Y + connect \Y $and$libresoc.v:143620$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:141989$6568 + cell $and $and$libresoc.v:143621$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230565,10 +233062,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141989$6568_Y + connect \Y $and$libresoc.v:143621$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:141990$6569 + cell $and $and$libresoc.v:143622$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230576,10 +233073,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:141990$6569_Y + connect \Y $and$libresoc.v:143622$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:141991$6570 + cell $and $and$libresoc.v:143623$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230587,10 +233084,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:141991$6570_Y + connect \Y $and$libresoc.v:143623$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:141992$6571 + cell $and $and$libresoc.v:143624$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230598,10 +233095,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141992$6571_Y + connect \Y $and$libresoc.v:143624$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:141993$6572 + cell $and $and$libresoc.v:143625$6620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230609,10 +233106,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141993$6572_Y + connect \Y $and$libresoc.v:143625$6620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:141995$6574 + cell $and $and$libresoc.v:143627$6622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230620,10 +233117,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:141995$6574_Y + connect \Y $and$libresoc.v:143627$6622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:141997$6576 + cell $and $and$libresoc.v:143629$6624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230631,10 +233128,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:141997$6576_Y + connect \Y $and$libresoc.v:143629$6624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:141998$6577 + cell $and $and$libresoc.v:143630$6625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230642,10 +233139,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:141998$6577_Y + connect \Y $and$libresoc.v:143630$6625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:141999$6578 + cell $and $and$libresoc.v:143631$6626 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230653,10 +233150,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:141999$6578_Y + connect \Y $and$libresoc.v:143631$6626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:142001$6580 + cell $and $and$libresoc.v:143633$6628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230664,10 +233161,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:142001$6580_Y + connect \Y $and$libresoc.v:143633$6628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:142004$6583 + cell $and $and$libresoc.v:143636$6631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230675,10 +233172,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:142004$6583_Y + connect \Y $and$libresoc.v:143636$6631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:142009$6588 + cell $and $and$libresoc.v:143641$6636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230686,10 +233183,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:142009$6588_Y + connect \Y $and$libresoc.v:143641$6636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:142010$6589 + cell $and $and$libresoc.v:143642$6637 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230697,10 +233194,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:142010$6589_Y + connect \Y $and$libresoc.v:143642$6637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:142012$6591 + cell $and $and$libresoc.v:143644$6639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230708,10 +233205,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:142012$6591_Y + connect \Y $and$libresoc.v:143644$6639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142015$6594 + cell $and $and$libresoc.v:143647$6642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230719,10 +233216,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:142015$6594_Y + connect \Y $and$libresoc.v:143647$6642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142016$6595 + cell $and $and$libresoc.v:143648$6643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230730,10 +233227,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:142016$6595_Y + connect \Y $and$libresoc.v:143648$6643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:142017$6596 + cell $and $and$libresoc.v:143649$6644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230741,10 +233238,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:142017$6596_Y + connect \Y $and$libresoc.v:143649$6644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:142022$6601 + cell $and $and$libresoc.v:143654$6649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230752,10 +233249,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:142022$6601_Y + connect \Y $and$libresoc.v:143654$6649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:142023$6602 + cell $and $and$libresoc.v:143655$6650 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230763,10 +233260,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:142023$6602_Y + connect \Y $and$libresoc.v:143655$6650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:142026$6605 + cell $and $and$libresoc.v:143658$6653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230774,10 +233271,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:142026$6605_Y + connect \Y $and$libresoc.v:143658$6653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:142027$6606 + cell $and $and$libresoc.v:143659$6654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230785,10 +233282,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:142027$6606_Y + connect \Y $and$libresoc.v:143659$6654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:142036$6615 + cell $and $and$libresoc.v:143668$6663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230796,10 +233293,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:142036$6615_Y + connect \Y $and$libresoc.v:143668$6663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:142037$6616 + cell $and $and$libresoc.v:143669$6664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230807,10 +233304,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:142037$6616_Y + connect \Y $and$libresoc.v:143669$6664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:142038$6617 + cell $and $and$libresoc.v:143670$6665 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230818,10 +233315,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:142038$6617_Y + connect \Y $and$libresoc.v:143670$6665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:142011$6590 + cell $eq $eq$libresoc.v:143643$6638 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230829,10 +233326,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:142011$6590_Y + connect \Y $eq$libresoc.v:143643$6638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:142013$6592 + cell $eq $eq$libresoc.v:143645$6640 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230840,82 +233337,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:142013$6592_Y + connect \Y $eq$libresoc.v:143645$6640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:141986$6565 + cell $not $not$libresoc.v:143618$6613 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:141986$6565_Y + connect \Y $not$libresoc.v:143618$6613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:141994$6573 + cell $not $not$libresoc.v:143626$6621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:141994$6573_Y + connect \Y $not$libresoc.v:143626$6621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:141996$6575 + cell $not $not$libresoc.v:143628$6623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:141996$6575_Y + connect \Y $not$libresoc.v:143628$6623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:142000$6579 + cell $not $not$libresoc.v:143632$6627 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:142000$6579_Y + connect \Y $not$libresoc.v:143632$6627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:142003$6582 + cell $not $not$libresoc.v:143635$6630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:142003$6582_Y + connect \Y $not$libresoc.v:143635$6630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:142008$6587 + cell $not $not$libresoc.v:143640$6635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:142008$6587_Y + connect \Y $not$libresoc.v:143640$6635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:142014$6593 + cell $not $not$libresoc.v:143646$6641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:142014$6593_Y + connect \Y $not$libresoc.v:143646$6641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:142039$6618 + cell $not $not$libresoc.v:143671$6666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:142039$6618_Y + connect \Y $not$libresoc.v:143671$6666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:142040$6619 + cell $not $not$libresoc.v:143672$6667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:142040$6619_Y + connect \Y $not$libresoc.v:143672$6667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:142007$6586 + cell $or $or$libresoc.v:143639$6634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230923,10 +233420,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:142007$6586_Y + connect \Y $or$libresoc.v:143639$6634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:142018$6597 + cell $or $or$libresoc.v:143650$6645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230934,10 +233431,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142018$6597_Y + connect \Y $or$libresoc.v:143650$6645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:142019$6598 + cell $or $or$libresoc.v:143651$6646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230945,10 +233442,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:142019$6598_Y + connect \Y $or$libresoc.v:143651$6646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:142020$6599 + cell $or $or$libresoc.v:143652$6647 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230956,10 +233453,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:142020$6599_Y + connect \Y $or$libresoc.v:143652$6647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:142021$6600 + cell $or $or$libresoc.v:143653$6648 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230967,10 +233464,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:142021$6600_Y + connect \Y $or$libresoc.v:143653$6648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:142024$6603 + cell $or $or$libresoc.v:143656$6651 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230978,10 +233475,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:142024$6603_Y + connect \Y $or$libresoc.v:143656$6651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:142025$6604 + cell $or $or$libresoc.v:143657$6652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230989,98 +233486,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:142025$6604_Y + connect \Y $or$libresoc.v:143657$6652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:142031$6610 + cell $reduce_and $reduce_and$libresoc.v:143663$6658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:142031$6610_Y + connect \Y $reduce_and$libresoc.v:143663$6658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:142002$6581 + cell $reduce_or $reduce_or$libresoc.v:143634$6629 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:142002$6581_Y + connect \Y $reduce_or$libresoc.v:143634$6629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:142005$6584 + cell $reduce_or $reduce_or$libresoc.v:143637$6632 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:142005$6584_Y + connect \Y $reduce_or$libresoc.v:143637$6632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:142006$6585 + cell $reduce_or $reduce_or$libresoc.v:143638$6633 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:142006$6585_Y + connect \Y $reduce_or$libresoc.v:143638$6633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:142028$6607 + cell $mux $ternary$libresoc.v:143660$6655 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:142028$6607_Y + connect \Y $ternary$libresoc.v:143660$6655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:142029$6608 + cell $mux $ternary$libresoc.v:143661$6656 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:142029$6608_Y + connect \Y $ternary$libresoc.v:143661$6656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:142030$6609 + cell $mux $ternary$libresoc.v:143662$6657 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:142030$6609_Y + connect \Y $ternary$libresoc.v:143662$6657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:142032$6611 + cell $mux $ternary$libresoc.v:143664$6659 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:142032$6611_Y + connect \Y $ternary$libresoc.v:143664$6659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142033$6612 + cell $mux $ternary$libresoc.v:143665$6660 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:142033$6612_Y + connect \Y $ternary$libresoc.v:143665$6660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142034$6613 + cell $mux $ternary$libresoc.v:143666$6661 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:142034$6613_Y + connect \Y $ternary$libresoc.v:143666$6661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:142035$6614 + cell $mux $ternary$libresoc.v:143667$6662 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:142035$6614_Y + connect \Y $ternary$libresoc.v:143667$6662_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142121.14-142127.4" + attribute \src "libresoc.v:143753.14-143759.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231089,7 +233586,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:142128.16-142160.4" + attribute \src "libresoc.v:143760.16-143792.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231124,7 +233621,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:142161.15-142167.4" + attribute \src "libresoc.v:143793.15-143799.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231133,7 +233630,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:142168.14-142174.4" + attribute \src "libresoc.v:143800.14-143806.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231142,7 +233639,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:142175.14-142181.4" + attribute \src "libresoc.v:143807.14-143813.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231151,7 +233648,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:142182.14-142188.4" + attribute \src "libresoc.v:143814.14-143820.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231160,7 +233657,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:142189.14-142194.4" + attribute \src "libresoc.v:143821.14-143826.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231168,7 +233665,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:142195.14-142201.4" + attribute \src "libresoc.v:143827.14-143833.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -231176,622 +233673,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:141375.7-141375.20" - process $proc$libresoc.v:141375$6770 + attribute \src "libresoc.v:143007.7-143007.20" + process $proc$libresoc.v:143007$6818 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141493.7-141493.24" - process $proc$libresoc.v:141493$6771 + attribute \src "libresoc.v:143125.7-143125.24" + process $proc$libresoc.v:143125$6819 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:141503.7-141503.26" - process $proc$libresoc.v:141503$6772 + attribute \src "libresoc.v:143135.7-143135.26" + process $proc$libresoc.v:143135$6820 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:141511.7-141511.25" - process $proc$libresoc.v:141511$6773 + attribute \src "libresoc.v:143143.7-143143.25" + process $proc$libresoc.v:143143$6821 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:141519.13-141519.53" - process $proc$libresoc.v:141519$6774 + attribute \src "libresoc.v:143151.13-143151.53" + process $proc$libresoc.v:143151$6822 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:141538.14-141538.57" - process $proc$libresoc.v:141538$6775 + attribute \src "libresoc.v:143170.14-143170.57" + process $proc$libresoc.v:143170$6823 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:141542.14-141542.76" - process $proc$libresoc.v:141542$6776 + attribute \src "libresoc.v:143174.14-143174.76" + process $proc$libresoc.v:143174$6824 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:141546.7-141546.51" - process $proc$libresoc.v:141546$6777 + attribute \src "libresoc.v:143178.7-143178.51" + process $proc$libresoc.v:143178$6825 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:141554.13-141554.56" - process $proc$libresoc.v:141554$6778 + attribute \src "libresoc.v:143186.13-143186.56" + process $proc$libresoc.v:143186$6826 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:141558.14-141558.51" - process $proc$libresoc.v:141558$6779 + attribute \src "libresoc.v:143190.14-143190.51" + process $proc$libresoc.v:143190$6827 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:141637.13-141637.55" - process $proc$libresoc.v:141637$6780 + attribute \src "libresoc.v:143269.13-143269.55" + process $proc$libresoc.v:143269$6828 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:141641.7-141641.48" - process $proc$libresoc.v:141641$6781 + attribute \src "libresoc.v:143273.7-143273.48" + process $proc$libresoc.v:143273$6829 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:141645.7-141645.49" - process $proc$libresoc.v:141645$6782 + attribute \src "libresoc.v:143277.7-143277.49" + process $proc$libresoc.v:143277$6830 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:141649.7-141649.47" - process $proc$libresoc.v:141649$6783 + attribute \src "libresoc.v:143281.7-143281.47" + process $proc$libresoc.v:143281$6831 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:141653.7-141653.48" - process $proc$libresoc.v:141653$6784 + attribute \src "libresoc.v:143285.7-143285.48" + process $proc$libresoc.v:143285$6832 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:141657.7-141657.45" - process $proc$libresoc.v:141657$6785 + attribute \src "libresoc.v:143289.7-143289.45" + process $proc$libresoc.v:143289$6833 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:141661.7-141661.45" - process $proc$libresoc.v:141661$6786 + attribute \src "libresoc.v:143293.7-143293.45" + process $proc$libresoc.v:143293$6834 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:141665.7-141665.51" - process $proc$libresoc.v:141665$6787 + attribute \src "libresoc.v:143297.7-143297.51" + process $proc$libresoc.v:143297$6835 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:141669.7-141669.45" - process $proc$libresoc.v:141669$6788 + attribute \src "libresoc.v:143301.7-143301.45" + process $proc$libresoc.v:143301$6836 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:141673.7-141673.45" - process $proc$libresoc.v:141673$6789 + attribute \src "libresoc.v:143305.7-143305.45" + process $proc$libresoc.v:143305$6837 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:141677.7-141677.48" - process $proc$libresoc.v:141677$6790 + attribute \src "libresoc.v:143309.7-143309.48" + process $proc$libresoc.v:143309$6838 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:141681.7-141681.45" - process $proc$libresoc.v:141681$6791 + attribute \src "libresoc.v:143313.7-143313.45" + process $proc$libresoc.v:143313$6839 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:141707.7-141707.27" - process $proc$libresoc.v:141707$6792 + attribute \src "libresoc.v:143339.7-143339.27" + process $proc$libresoc.v:143339$6840 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:141741.14-141741.47" - process $proc$libresoc.v:141741$6793 + attribute \src "libresoc.v:143373.14-143373.47" + process $proc$libresoc.v:143373$6841 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:141745.7-141745.27" - process $proc$libresoc.v:141745$6794 + attribute \src "libresoc.v:143377.7-143377.27" + process $proc$libresoc.v:143377$6842 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:141749.13-141749.33" - process $proc$libresoc.v:141749$6795 + attribute \src "libresoc.v:143381.13-143381.33" + process $proc$libresoc.v:143381$6843 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:141753.7-141753.30" - process $proc$libresoc.v:141753$6796 + attribute \src "libresoc.v:143385.7-143385.30" + process $proc$libresoc.v:143385$6844 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:141767.7-141767.25" - process $proc$libresoc.v:141767$6797 + attribute \src "libresoc.v:143399.7-143399.25" + process $proc$libresoc.v:143399$6845 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141771.7-141771.25" - process $proc$libresoc.v:141771$6798 + attribute \src "libresoc.v:143403.7-143403.25" + process $proc$libresoc.v:143403$6846 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141905.13-141905.30" - process $proc$libresoc.v:141905$6799 + attribute \src "libresoc.v:143537.13-143537.30" + process $proc$libresoc.v:143537$6847 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:141913.13-141913.31" - process $proc$libresoc.v:141913$6800 + attribute \src "libresoc.v:143545.13-143545.31" + process $proc$libresoc.v:143545$6848 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:141917.13-141917.31" - process $proc$libresoc.v:141917$6801 + attribute \src "libresoc.v:143549.13-143549.31" + process $proc$libresoc.v:143549$6849 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:141929.7-141929.26" - process $proc$libresoc.v:141929$6802 + attribute \src "libresoc.v:143561.7-143561.26" + process $proc$libresoc.v:143561$6850 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:141933.7-141933.26" - process $proc$libresoc.v:141933$6803 + attribute \src "libresoc.v:143565.7-143565.26" + process $proc$libresoc.v:143565$6851 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:141937.7-141937.25" - process $proc$libresoc.v:141937$6804 + attribute \src "libresoc.v:143569.7-143569.25" + process $proc$libresoc.v:143569$6852 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:141941.7-141941.25" - process $proc$libresoc.v:141941$6805 + attribute \src "libresoc.v:143573.7-143573.25" + process $proc$libresoc.v:143573$6853 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:141955.13-141955.31" - process $proc$libresoc.v:141955$6806 + attribute \src "libresoc.v:143587.13-143587.31" + process $proc$libresoc.v:143587$6854 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:141959.13-141959.31" - process $proc$libresoc.v:141959$6807 + attribute \src "libresoc.v:143591.13-143591.31" + process $proc$libresoc.v:143591$6855 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:141967.14-141967.43" - process $proc$libresoc.v:141967$6808 + attribute \src "libresoc.v:143599.14-143599.43" + process $proc$libresoc.v:143599$6856 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:141971.14-141971.43" - process $proc$libresoc.v:141971$6809 + attribute \src "libresoc.v:143603.14-143603.43" + process $proc$libresoc.v:143603$6857 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:141975.7-141975.20" - process $proc$libresoc.v:141975$6810 + attribute \src "libresoc.v:143607.7-143607.20" + process $proc$libresoc.v:143607$6858 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:142041.3-142042.39" - process $proc$libresoc.v:142041$6620 + attribute \src "libresoc.v:143673.3-143674.39" + process $proc$libresoc.v:143673$6668 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:142043.3-142044.43" - process $proc$libresoc.v:142043$6621 + attribute \src "libresoc.v:143675.3-143676.43" + process $proc$libresoc.v:143675$6669 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:142045.3-142046.29" - process $proc$libresoc.v:142045$6622 + attribute \src "libresoc.v:143677.3-143678.29" + process $proc$libresoc.v:143677$6670 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:142047.3-142048.29" - process $proc$libresoc.v:142047$6623 + attribute \src "libresoc.v:143679.3-143680.29" + process $proc$libresoc.v:143679$6671 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:142049.3-142050.29" - process $proc$libresoc.v:142049$6624 + attribute \src "libresoc.v:143681.3-143682.29" + process $proc$libresoc.v:143681$6672 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:142051.3-142052.43" - process $proc$libresoc.v:142051$6625 + attribute \src "libresoc.v:143683.3-143684.43" + process $proc$libresoc.v:143683$6673 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:142053.3-142054.49" - process $proc$libresoc.v:142053$6626 + attribute \src "libresoc.v:143685.3-143686.49" + process $proc$libresoc.v:143685$6674 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:142055.3-142056.37" - process $proc$libresoc.v:142055$6627 + attribute \src "libresoc.v:143687.3-143688.37" + process $proc$libresoc.v:143687$6675 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:142057.3-142058.43" - process $proc$libresoc.v:142057$6628 + attribute \src "libresoc.v:143689.3-143690.43" + process $proc$libresoc.v:143689$6676 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:142059.3-142060.85" - process $proc$libresoc.v:142059$6629 + attribute \src "libresoc.v:143691.3-143692.85" + process $proc$libresoc.v:143691$6677 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:142061.3-142062.81" - process $proc$libresoc.v:142061$6630 + attribute \src "libresoc.v:143693.3-143694.81" + process $proc$libresoc.v:143693$6678 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:142063.3-142064.95" - process $proc$libresoc.v:142063$6631 + attribute \src "libresoc.v:143695.3-143696.95" + process $proc$libresoc.v:143695$6679 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142065.3-142066.91" - process $proc$libresoc.v:142065$6632 + attribute \src "libresoc.v:143697.3-143698.91" + process $proc$libresoc.v:143697$6680 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142067.3-142068.79" - process $proc$libresoc.v:142067$6633 + attribute \src "libresoc.v:143699.3-143700.79" + process $proc$libresoc.v:143699$6681 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:142069.3-142070.79" - process $proc$libresoc.v:142069$6634 + attribute \src "libresoc.v:143701.3-143702.79" + process $proc$libresoc.v:143701$6682 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:142071.3-142072.79" - process $proc$libresoc.v:142071$6635 + attribute \src "libresoc.v:143703.3-143704.79" + process $proc$libresoc.v:143703$6683 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:142073.3-142074.79" - process $proc$libresoc.v:142073$6636 + attribute \src "libresoc.v:143705.3-143706.79" + process $proc$libresoc.v:143705$6684 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:142075.3-142076.85" - process $proc$libresoc.v:142075$6637 + attribute \src "libresoc.v:143707.3-143708.85" + process $proc$libresoc.v:143707$6685 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:142077.3-142078.79" - process $proc$libresoc.v:142077$6638 + attribute \src "libresoc.v:143709.3-143710.79" + process $proc$libresoc.v:143709$6686 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:142079.3-142080.89" - process $proc$libresoc.v:142079$6639 + attribute \src "libresoc.v:143711.3-143712.89" + process $proc$libresoc.v:143711$6687 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:142081.3-142082.87" - process $proc$libresoc.v:142081$6640 + attribute \src "libresoc.v:143713.3-143714.87" + process $proc$libresoc.v:143713$6688 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:142083.3-142084.85" - process $proc$libresoc.v:142083$6641 + attribute \src "libresoc.v:143715.3-143716.85" + process $proc$libresoc.v:143715$6689 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:142085.3-142086.91" - process $proc$libresoc.v:142085$6642 + attribute \src "libresoc.v:143717.3-143718.91" + process $proc$libresoc.v:143717$6690 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:142087.3-142088.83" - process $proc$libresoc.v:142087$6643 + attribute \src "libresoc.v:143719.3-143720.83" + process $proc$libresoc.v:143719$6691 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:142089.3-142090.85" - process $proc$libresoc.v:142089$6644 + attribute \src "libresoc.v:143721.3-143722.85" + process $proc$libresoc.v:143721$6692 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:142091.3-142092.83" - process $proc$libresoc.v:142091$6645 + attribute \src "libresoc.v:143723.3-143724.83" + process $proc$libresoc.v:143723$6693 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:142093.3-142094.75" - process $proc$libresoc.v:142093$6646 + attribute \src "libresoc.v:143725.3-143726.75" + process $proc$libresoc.v:143725$6694 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:142095.3-142096.39" - process $proc$libresoc.v:142095$6647 + attribute \src "libresoc.v:143727.3-143728.39" + process $proc$libresoc.v:143727$6695 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:142097.3-142098.39" - process $proc$libresoc.v:142097$6648 + attribute \src "libresoc.v:143729.3-143730.39" + process $proc$libresoc.v:143729$6696 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:142099.3-142100.39" - process $proc$libresoc.v:142099$6649 + attribute \src "libresoc.v:143731.3-143732.39" + process $proc$libresoc.v:143731$6697 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:142101.3-142102.39" - process $proc$libresoc.v:142101$6650 + attribute \src "libresoc.v:143733.3-143734.39" + process $proc$libresoc.v:143733$6698 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:142103.3-142104.39" - process $proc$libresoc.v:142103$6651 + attribute \src "libresoc.v:143735.3-143736.39" + process $proc$libresoc.v:143735$6699 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:142105.3-142106.39" - process $proc$libresoc.v:142105$6652 + attribute \src "libresoc.v:143737.3-143738.39" + process $proc$libresoc.v:143737$6700 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:142107.3-142108.39" - process $proc$libresoc.v:142107$6653 + attribute \src "libresoc.v:143739.3-143740.39" + process $proc$libresoc.v:143739$6701 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:142109.3-142110.39" - process $proc$libresoc.v:142109$6654 + attribute \src "libresoc.v:143741.3-143742.39" + process $proc$libresoc.v:143741$6702 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:142111.3-142112.41" - process $proc$libresoc.v:142111$6655 + attribute \src "libresoc.v:143743.3-143744.41" + process $proc$libresoc.v:143743$6703 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:142113.3-142114.41" - process $proc$libresoc.v:142113$6656 + attribute \src "libresoc.v:143745.3-143746.41" + process $proc$libresoc.v:143745$6704 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:142115.3-142116.37" - process $proc$libresoc.v:142115$6657 + attribute \src "libresoc.v:143747.3-143748.37" + process $proc$libresoc.v:143747$6705 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:142117.3-142118.44" - process $proc$libresoc.v:142117$6658 + attribute \src "libresoc.v:143749.3-143750.44" + process $proc$libresoc.v:143749$6706 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:142119.3-142120.24" - process $proc$libresoc.v:142119$6659 + attribute \src "libresoc.v:143751.3-143752.24" + process $proc$libresoc.v:143751$6707 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:142202.3-142211.6" - process $proc$libresoc.v:142202$6660 + attribute \src "libresoc.v:143834.3-143843.6" + process $proc$libresoc.v:143834$6708 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:142203.5-142203.29" + attribute \src "libresoc.v:143835.5-143835.29" switch \initial - attribute \src "libresoc.v:142203.9-142203.17" + attribute \src "libresoc.v:143835.9-143835.17" case 1'1 case end @@ -231807,14 +234304,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:142212.3-142220.6" - process $proc$libresoc.v:142212$6661 + attribute \src "libresoc.v:143844.3-143852.6" + process $proc$libresoc.v:143844$6709 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6662 $1\rok_l_s_rdok$next[0:0]$6663 - attribute \src "libresoc.v:142213.5-142213.29" + assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 + attribute \src "libresoc.v:143845.5-143845.29" switch \initial - attribute \src "libresoc.v:142213.9-142213.17" + attribute \src "libresoc.v:143845.9-143845.17" case 1'1 case end @@ -231823,21 +234320,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6663 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6711 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6663 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6711 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6662 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 end - attribute \src "libresoc.v:142221.3-142229.6" - process $proc$libresoc.v:142221$6664 + attribute \src "libresoc.v:143853.3-143861.6" + process $proc$libresoc.v:143853$6712 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6665 $1\rok_l_r_rdok$next[0:0]$6666 - attribute \src "libresoc.v:142222.5-142222.29" + assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 + attribute \src "libresoc.v:143854.5-143854.29" switch \initial - attribute \src "libresoc.v:142222.9-142222.17" + attribute \src "libresoc.v:143854.9-143854.17" case 1'1 case end @@ -231846,21 +234343,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6666 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6714 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6666 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6714 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6665 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 end - attribute \src "libresoc.v:142230.3-142238.6" - process $proc$libresoc.v:142230$6667 + attribute \src "libresoc.v:143862.3-143870.6" + process $proc$libresoc.v:143862$6715 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6668 $1\rst_l_s_rst$next[0:0]$6669 - attribute \src "libresoc.v:142231.5-142231.29" + assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 + attribute \src "libresoc.v:143863.5-143863.29" switch \initial - attribute \src "libresoc.v:142231.9-142231.17" + attribute \src "libresoc.v:143863.9-143863.17" case 1'1 case end @@ -231869,21 +234366,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6669 1'0 + assign $1\rst_l_s_rst$next[0:0]$6717 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6669 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6717 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6668 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 end - attribute \src "libresoc.v:142239.3-142247.6" - process $proc$libresoc.v:142239$6670 + attribute \src "libresoc.v:143871.3-143879.6" + process $proc$libresoc.v:143871$6718 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6671 $1\rst_l_r_rst$next[0:0]$6672 - attribute \src "libresoc.v:142240.5-142240.29" + assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 + attribute \src "libresoc.v:143872.5-143872.29" switch \initial - attribute \src "libresoc.v:142240.9-142240.17" + attribute \src "libresoc.v:143872.9-143872.17" case 1'1 case end @@ -231892,21 +234389,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6672 1'1 + assign $1\rst_l_r_rst$next[0:0]$6720 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6672 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6720 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6671 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 end - attribute \src "libresoc.v:142248.3-142256.6" - process $proc$libresoc.v:142248$6673 + attribute \src "libresoc.v:143880.3-143888.6" + process $proc$libresoc.v:143880$6721 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6674 $1\opc_l_s_opc$next[0:0]$6675 - attribute \src "libresoc.v:142249.5-142249.29" + assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 + attribute \src "libresoc.v:143881.5-143881.29" switch \initial - attribute \src "libresoc.v:142249.9-142249.17" + attribute \src "libresoc.v:143881.9-143881.17" case 1'1 case end @@ -231915,21 +234412,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6675 1'0 + assign $1\opc_l_s_opc$next[0:0]$6723 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6675 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6723 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6674 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 end - attribute \src "libresoc.v:142257.3-142265.6" - process $proc$libresoc.v:142257$6676 + attribute \src "libresoc.v:143889.3-143897.6" + process $proc$libresoc.v:143889$6724 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6677 $1\opc_l_r_opc$next[0:0]$6678 - attribute \src "libresoc.v:142258.5-142258.29" + assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 + attribute \src "libresoc.v:143890.5-143890.29" switch \initial - attribute \src "libresoc.v:142258.9-142258.17" + attribute \src "libresoc.v:143890.9-143890.17" case 1'1 case end @@ -231938,21 +234435,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6678 1'1 + assign $1\opc_l_r_opc$next[0:0]$6726 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6678 \req_done + assign $1\opc_l_r_opc$next[0:0]$6726 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6677 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 end - attribute \src "libresoc.v:142266.3-142274.6" - process $proc$libresoc.v:142266$6679 + attribute \src "libresoc.v:143898.3-143906.6" + process $proc$libresoc.v:143898$6727 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6680 $1\src_l_s_src$next[2:0]$6681 - attribute \src "libresoc.v:142267.5-142267.29" + assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 + attribute \src "libresoc.v:143899.5-143899.29" switch \initial - attribute \src "libresoc.v:142267.9-142267.17" + attribute \src "libresoc.v:143899.9-143899.17" case 1'1 case end @@ -231961,21 +234458,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6681 3'000 + assign $1\src_l_s_src$next[2:0]$6729 3'000 case - assign $1\src_l_s_src$next[2:0]$6681 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6729 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6680 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 end - attribute \src "libresoc.v:142275.3-142283.6" - process $proc$libresoc.v:142275$6682 + attribute \src "libresoc.v:143907.3-143915.6" + process $proc$libresoc.v:143907$6730 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6683 $1\src_l_r_src$next[2:0]$6684 - attribute \src "libresoc.v:142276.5-142276.29" + assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 + attribute \src "libresoc.v:143908.5-143908.29" switch \initial - attribute \src "libresoc.v:142276.9-142276.17" + attribute \src "libresoc.v:143908.9-143908.17" case 1'1 case end @@ -231984,21 +234481,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6684 3'111 + assign $1\src_l_r_src$next[2:0]$6732 3'111 case - assign $1\src_l_r_src$next[2:0]$6684 \reset_r + assign $1\src_l_r_src$next[2:0]$6732 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6683 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 end - attribute \src "libresoc.v:142284.3-142292.6" - process $proc$libresoc.v:142284$6685 + attribute \src "libresoc.v:143916.3-143924.6" + process $proc$libresoc.v:143916$6733 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6686 $1\req_l_s_req$next[1:0]$6687 - attribute \src "libresoc.v:142285.5-142285.29" + assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 + attribute \src "libresoc.v:143917.5-143917.29" switch \initial - attribute \src "libresoc.v:142285.9-142285.17" + attribute \src "libresoc.v:143917.9-143917.17" case 1'1 case end @@ -232007,21 +234504,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6687 2'00 + assign $1\req_l_s_req$next[1:0]$6735 2'00 case - assign $1\req_l_s_req$next[1:0]$6687 \$65 + assign $1\req_l_s_req$next[1:0]$6735 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6686 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 end - attribute \src "libresoc.v:142293.3-142301.6" - process $proc$libresoc.v:142293$6688 + attribute \src "libresoc.v:143925.3-143933.6" + process $proc$libresoc.v:143925$6736 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6689 $1\req_l_r_req$next[1:0]$6690 - attribute \src "libresoc.v:142294.5-142294.29" + assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 + attribute \src "libresoc.v:143926.5-143926.29" switch \initial - attribute \src "libresoc.v:142294.9-142294.17" + attribute \src "libresoc.v:143926.9-143926.17" case 1'1 case end @@ -232030,15 +234527,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6690 2'11 + assign $1\req_l_r_req$next[1:0]$6738 2'11 case - assign $1\req_l_r_req$next[1:0]$6690 \$67 + assign $1\req_l_r_req$next[1:0]$6738 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6689 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 end - attribute \src "libresoc.v:142302.3-142340.6" - process $proc$libresoc.v:142302$6691 + attribute \src "libresoc.v:143934.3-143972.6" + process $proc$libresoc.v:143934$6739 assign { } { } assign { } { } assign { } { } @@ -232075,33 +234572,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6692 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 - assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6740 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6697 $1\alu_logical0_logical_op__insn$next[31:0]$6715 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6745 $1\alu_logical0_logical_op__insn$next[31:0]$6763 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 - attribute \src "libresoc.v:142303.5-142303.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 + attribute \src "libresoc.v:143935.5-143935.29" switch \initial - attribute \src "libresoc.v:142303.9-142303.17" + attribute \src "libresoc.v:143935.9-143935.17" case 1'1 case end @@ -232127,26 +234624,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6715 $1\alu_logical0_logical_op__data_len$next[3:0]$6710 $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6763 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6710 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6711 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6714 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6715 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6716 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6717 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6718 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6719 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6720 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6723 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6726 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6727 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6758 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6763 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -232158,54 +234655,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6728 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6712 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6729 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6713 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6730 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6721 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6731 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6722 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6732 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6724 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6733 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6725 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6692 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6693 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6694 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6695 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6696 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6697 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6698 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6699 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6700 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6701 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6702 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6703 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6704 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6705 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6706 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6707 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6708 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6709 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6740 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6745 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 end - attribute \src "libresoc.v:142341.3-142362.6" - process $proc$libresoc.v:142341$6734 + attribute \src "libresoc.v:143973.3-143994.6" + process $proc$libresoc.v:143973$6782 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6735 $2\data_r0__o$next[63:0]$6739 + assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6736 $3\data_r0__o_ok$next[0:0]$6741 - attribute \src "libresoc.v:142342.5-142342.29" + assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 + attribute \src "libresoc.v:143974.5-143974.29" switch \initial - attribute \src "libresoc.v:142342.9-142342.17" + attribute \src "libresoc.v:143974.9-143974.17" case 1'1 case end @@ -232215,10 +234712,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6738 $1\data_r0__o$next[63:0]$6737 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6786 $1\data_r0__o$next[63:0]$6785 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6737 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6738 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6785 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6786 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -232226,38 +234723,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6740 $2\data_r0__o$next[63:0]$6739 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6788 $2\data_r0__o$next[63:0]$6787 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6739 $1\data_r0__o$next[63:0]$6737 - assign $2\data_r0__o_ok$next[0:0]$6740 $1\data_r0__o_ok$next[0:0]$6738 + assign $2\data_r0__o$next[63:0]$6787 $1\data_r0__o$next[63:0]$6785 + assign $2\data_r0__o_ok$next[0:0]$6788 $1\data_r0__o_ok$next[0:0]$6786 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6741 1'0 + assign $3\data_r0__o_ok$next[0:0]$6789 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6741 $2\data_r0__o_ok$next[0:0]$6740 + assign $3\data_r0__o_ok$next[0:0]$6789 $2\data_r0__o_ok$next[0:0]$6788 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6735 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6736 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 end - attribute \src "libresoc.v:142363.3-142384.6" - process $proc$libresoc.v:142363$6742 + attribute \src "libresoc.v:143995.3-144016.6" + process $proc$libresoc.v:143995$6790 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6743 $2\data_r1__cr_a$next[3:0]$6747 + assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6744 $3\data_r1__cr_a_ok$next[0:0]$6749 - attribute \src "libresoc.v:142364.5-142364.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 + attribute \src "libresoc.v:143996.5-143996.29" switch \initial - attribute \src "libresoc.v:142364.9-142364.17" + attribute \src "libresoc.v:143996.9-143996.17" case 1'1 case end @@ -232267,10 +234764,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6746 $1\data_r1__cr_a$next[3:0]$6745 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6794 $1\data_r1__cr_a$next[3:0]$6793 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6745 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6746 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6793 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6794 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -232278,32 +234775,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6748 $2\data_r1__cr_a$next[3:0]$6747 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6796 $2\data_r1__cr_a$next[3:0]$6795 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6747 $1\data_r1__cr_a$next[3:0]$6745 - assign $2\data_r1__cr_a_ok$next[0:0]$6748 $1\data_r1__cr_a_ok$next[0:0]$6746 + assign $2\data_r1__cr_a$next[3:0]$6795 $1\data_r1__cr_a$next[3:0]$6793 + assign $2\data_r1__cr_a_ok$next[0:0]$6796 $1\data_r1__cr_a_ok$next[0:0]$6794 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6749 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6797 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6749 $2\data_r1__cr_a_ok$next[0:0]$6748 + assign $3\data_r1__cr_a_ok$next[0:0]$6797 $2\data_r1__cr_a_ok$next[0:0]$6796 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6743 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6744 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 end - attribute \src "libresoc.v:142385.3-142394.6" - process $proc$libresoc.v:142385$6750 + attribute \src "libresoc.v:144017.3-144026.6" + process $proc$libresoc.v:144017$6798 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6751 $1\src_r0$next[63:0]$6752 - attribute \src "libresoc.v:142386.5-142386.29" + assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 + attribute \src "libresoc.v:144018.5-144018.29" switch \initial - attribute \src "libresoc.v:142386.9-142386.17" + attribute \src "libresoc.v:144018.9-144018.17" case 1'1 case end @@ -232312,21 +234809,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6752 \src_or_imm + assign $1\src_r0$next[63:0]$6800 \src_or_imm case - assign $1\src_r0$next[63:0]$6752 \src_r0 + assign $1\src_r0$next[63:0]$6800 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6751 + update \src_r0$next $0\src_r0$next[63:0]$6799 end - attribute \src "libresoc.v:142395.3-142404.6" - process $proc$libresoc.v:142395$6753 + attribute \src "libresoc.v:144027.3-144036.6" + process $proc$libresoc.v:144027$6801 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6754 $1\src_r1$next[63:0]$6755 - attribute \src "libresoc.v:142396.5-142396.29" + assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 + attribute \src "libresoc.v:144028.5-144028.29" switch \initial - attribute \src "libresoc.v:142396.9-142396.17" + attribute \src "libresoc.v:144028.9-144028.17" case 1'1 case end @@ -232335,21 +234832,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6755 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6803 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6755 \src_r1 + assign $1\src_r1$next[63:0]$6803 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6754 + update \src_r1$next $0\src_r1$next[63:0]$6802 end - attribute \src "libresoc.v:142405.3-142414.6" - process $proc$libresoc.v:142405$6756 + attribute \src "libresoc.v:144037.3-144046.6" + process $proc$libresoc.v:144037$6804 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6757 $1\src_r2$next[0:0]$6758 - attribute \src "libresoc.v:142406.5-142406.29" + assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 + attribute \src "libresoc.v:144038.5-144038.29" switch \initial - attribute \src "libresoc.v:142406.9-142406.17" + attribute \src "libresoc.v:144038.9-144038.17" case 1'1 case end @@ -232358,21 +234855,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6758 \src3_i + assign $1\src_r2$next[0:0]$6806 \src3_i case - assign $1\src_r2$next[0:0]$6758 \src_r2 + assign $1\src_r2$next[0:0]$6806 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6757 + update \src_r2$next $0\src_r2$next[0:0]$6805 end - attribute \src "libresoc.v:142415.3-142423.6" - process $proc$libresoc.v:142415$6759 + attribute \src "libresoc.v:144047.3-144055.6" + process $proc$libresoc.v:144047$6807 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6760 $1\alui_l_r_alui$next[0:0]$6761 - attribute \src "libresoc.v:142416.5-142416.29" + assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 + attribute \src "libresoc.v:144048.5-144048.29" switch \initial - attribute \src "libresoc.v:142416.9-142416.17" + attribute \src "libresoc.v:144048.9-144048.17" case 1'1 case end @@ -232381,21 +234878,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6761 1'1 + assign $1\alui_l_r_alui$next[0:0]$6809 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6761 \$89 + assign $1\alui_l_r_alui$next[0:0]$6809 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6760 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 end - attribute \src "libresoc.v:142424.3-142432.6" - process $proc$libresoc.v:142424$6762 + attribute \src "libresoc.v:144056.3-144064.6" + process $proc$libresoc.v:144056$6810 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6763 $1\alu_l_r_alu$next[0:0]$6764 - attribute \src "libresoc.v:142425.5-142425.29" + assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 + attribute \src "libresoc.v:144057.5-144057.29" switch \initial - attribute \src "libresoc.v:142425.9-142425.17" + attribute \src "libresoc.v:144057.9-144057.17" case 1'1 case end @@ -232404,21 +234901,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6764 1'1 + assign $1\alu_l_r_alu$next[0:0]$6812 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6764 \$91 + assign $1\alu_l_r_alu$next[0:0]$6812 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6763 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 end - attribute \src "libresoc.v:142433.3-142442.6" - process $proc$libresoc.v:142433$6765 + attribute \src "libresoc.v:144065.3-144074.6" + process $proc$libresoc.v:144065$6813 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142434.5-142434.29" + attribute \src "libresoc.v:144066.5-144066.29" switch \initial - attribute \src "libresoc.v:142434.9-142434.17" + attribute \src "libresoc.v:144066.9-144066.17" case 1'1 case end @@ -232434,14 +234931,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142443.3-142452.6" - process $proc$libresoc.v:142443$6766 + attribute \src "libresoc.v:144075.3-144084.6" + process $proc$libresoc.v:144075$6814 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:142444.5-142444.29" + attribute \src "libresoc.v:144076.5-144076.29" switch \initial - attribute \src "libresoc.v:142444.9-142444.17" + attribute \src "libresoc.v:144076.9-144076.17" case 1'1 case end @@ -232457,14 +234954,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:142453.3-142461.6" - process $proc$libresoc.v:142453$6767 + attribute \src "libresoc.v:144085.3-144093.6" + process $proc$libresoc.v:144085$6815 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6768 $1\prev_wr_go$next[1:0]$6769 - attribute \src "libresoc.v:142454.5-142454.29" + assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 + attribute \src "libresoc.v:144086.5-144086.29" switch \initial - attribute \src "libresoc.v:142454.9-142454.17" + attribute \src "libresoc.v:144086.9-144086.17" case 1'1 case end @@ -232473,70 +234970,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6769 2'00 - case - assign $1\prev_wr_go$next[1:0]$6769 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6768 - end - connect \$9 $and$libresoc.v:141984$6563_Y - connect \$99 $and$libresoc.v:141985$6564_Y - connect \$101 $not$libresoc.v:141986$6565_Y - connect \$103 $and$libresoc.v:141987$6566_Y - connect \$105 $and$libresoc.v:141988$6567_Y - connect \$107 $and$libresoc.v:141989$6568_Y - connect \$109 $and$libresoc.v:141990$6569_Y - connect \$111 $and$libresoc.v:141991$6570_Y - connect \$113 $and$libresoc.v:141992$6571_Y - connect \$115 $and$libresoc.v:141993$6572_Y - connect \$11 $not$libresoc.v:141994$6573_Y - connect \$13 $and$libresoc.v:141995$6574_Y - connect \$15 $not$libresoc.v:141996$6575_Y - connect \$17 $and$libresoc.v:141997$6576_Y - connect \$1 $and$libresoc.v:141998$6577_Y - connect \$19 $and$libresoc.v:141999$6578_Y - connect \$23 $not$libresoc.v:142000$6579_Y - connect \$25 $and$libresoc.v:142001$6580_Y - connect \$22 $reduce_or$libresoc.v:142002$6581_Y - connect \$21 $not$libresoc.v:142003$6582_Y - connect \$29 $and$libresoc.v:142004$6583_Y - connect \$31 $reduce_or$libresoc.v:142005$6584_Y - connect \$33 $reduce_or$libresoc.v:142006$6585_Y - connect \$35 $or$libresoc.v:142007$6586_Y - connect \$37 $not$libresoc.v:142008$6587_Y - connect \$39 $and$libresoc.v:142009$6588_Y - connect \$41 $and$libresoc.v:142010$6589_Y - connect \$43 $eq$libresoc.v:142011$6590_Y - connect \$45 $and$libresoc.v:142012$6591_Y - connect \$47 $eq$libresoc.v:142013$6592_Y - connect \$4 $not$libresoc.v:142014$6593_Y - connect \$49 $and$libresoc.v:142015$6594_Y - connect \$51 $and$libresoc.v:142016$6595_Y - connect \$53 $and$libresoc.v:142017$6596_Y - connect \$55 $or$libresoc.v:142018$6597_Y - connect \$57 $or$libresoc.v:142019$6598_Y - connect \$59 $or$libresoc.v:142020$6599_Y - connect \$61 $or$libresoc.v:142021$6600_Y - connect \$63 $and$libresoc.v:142022$6601_Y - connect \$65 $and$libresoc.v:142023$6602_Y - connect \$67 $or$libresoc.v:142024$6603_Y - connect \$6 $or$libresoc.v:142025$6604_Y - connect \$69 $and$libresoc.v:142026$6605_Y - connect \$71 $and$libresoc.v:142027$6606_Y - connect \$73 $ternary$libresoc.v:142028$6607_Y - connect \$75 $ternary$libresoc.v:142029$6608_Y - connect \$78 $ternary$libresoc.v:142030$6609_Y - connect \$3 $reduce_and$libresoc.v:142031$6610_Y - connect \$81 $ternary$libresoc.v:142032$6611_Y - connect \$83 $ternary$libresoc.v:142033$6612_Y - connect \$85 $ternary$libresoc.v:142034$6613_Y - connect \$87 $ternary$libresoc.v:142035$6614_Y - connect \$89 $and$libresoc.v:142036$6615_Y - connect \$91 $and$libresoc.v:142037$6616_Y - connect \$93 $and$libresoc.v:142038$6617_Y - connect \$95 $not$libresoc.v:142039$6618_Y - connect \$97 $not$libresoc.v:142040$6619_Y + assign $1\prev_wr_go$next[1:0]$6817 2'00 + case + assign $1\prev_wr_go$next[1:0]$6817 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 + end + connect \$9 $and$libresoc.v:143616$6611_Y + connect \$99 $and$libresoc.v:143617$6612_Y + connect \$101 $not$libresoc.v:143618$6613_Y + connect \$103 $and$libresoc.v:143619$6614_Y + connect \$105 $and$libresoc.v:143620$6615_Y + connect \$107 $and$libresoc.v:143621$6616_Y + connect \$109 $and$libresoc.v:143622$6617_Y + connect \$111 $and$libresoc.v:143623$6618_Y + connect \$113 $and$libresoc.v:143624$6619_Y + connect \$115 $and$libresoc.v:143625$6620_Y + connect \$11 $not$libresoc.v:143626$6621_Y + connect \$13 $and$libresoc.v:143627$6622_Y + connect \$15 $not$libresoc.v:143628$6623_Y + connect \$17 $and$libresoc.v:143629$6624_Y + connect \$1 $and$libresoc.v:143630$6625_Y + connect \$19 $and$libresoc.v:143631$6626_Y + connect \$23 $not$libresoc.v:143632$6627_Y + connect \$25 $and$libresoc.v:143633$6628_Y + connect \$22 $reduce_or$libresoc.v:143634$6629_Y + connect \$21 $not$libresoc.v:143635$6630_Y + connect \$29 $and$libresoc.v:143636$6631_Y + connect \$31 $reduce_or$libresoc.v:143637$6632_Y + connect \$33 $reduce_or$libresoc.v:143638$6633_Y + connect \$35 $or$libresoc.v:143639$6634_Y + connect \$37 $not$libresoc.v:143640$6635_Y + connect \$39 $and$libresoc.v:143641$6636_Y + connect \$41 $and$libresoc.v:143642$6637_Y + connect \$43 $eq$libresoc.v:143643$6638_Y + connect \$45 $and$libresoc.v:143644$6639_Y + connect \$47 $eq$libresoc.v:143645$6640_Y + connect \$4 $not$libresoc.v:143646$6641_Y + connect \$49 $and$libresoc.v:143647$6642_Y + connect \$51 $and$libresoc.v:143648$6643_Y + connect \$53 $and$libresoc.v:143649$6644_Y + connect \$55 $or$libresoc.v:143650$6645_Y + connect \$57 $or$libresoc.v:143651$6646_Y + connect \$59 $or$libresoc.v:143652$6647_Y + connect \$61 $or$libresoc.v:143653$6648_Y + connect \$63 $and$libresoc.v:143654$6649_Y + connect \$65 $and$libresoc.v:143655$6650_Y + connect \$67 $or$libresoc.v:143656$6651_Y + connect \$6 $or$libresoc.v:143657$6652_Y + connect \$69 $and$libresoc.v:143658$6653_Y + connect \$71 $and$libresoc.v:143659$6654_Y + connect \$73 $ternary$libresoc.v:143660$6655_Y + connect \$75 $ternary$libresoc.v:143661$6656_Y + connect \$78 $ternary$libresoc.v:143662$6657_Y + connect \$3 $reduce_and$libresoc.v:143663$6658_Y + connect \$81 $ternary$libresoc.v:143664$6659_Y + connect \$83 $ternary$libresoc.v:143665$6660_Y + connect \$85 $ternary$libresoc.v:143666$6661_Y + connect \$87 $ternary$libresoc.v:143667$6662_Y + connect \$89 $and$libresoc.v:143668$6663_Y + connect \$91 $and$libresoc.v:143669$6664_Y + connect \$93 $and$libresoc.v:143670$6665_Y + connect \$95 $not$libresoc.v:143671$6666_Y + connect \$97 $not$libresoc.v:143672$6667_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -232570,248 +235067,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:142498.1-143889.10" +attribute \src "libresoc.v:144130.1-145521.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:143828.3-143846.6" - wire width 4 $0\cr_a$next[3:0]$6895 - attribute \src "libresoc.v:143588.3-143589.25" + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $0\cr_a$next[3:0]$6943 + attribute \src "libresoc.v:145220.3-145221.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $0\cr_a_ok$next[0:0]$6896 - attribute \src "libresoc.v:143590.3-143591.31" + attribute \src "libresoc.v:145460.3-145478.6" + wire $0\cr_a_ok$next[0:0]$6944 + attribute \src "libresoc.v:145222.3-145223.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:142499.7-142499.20" + attribute \src "libresoc.v:144131.7-144131.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6846 - attribute \src "libresoc.v:143628.3-143629.57" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6894 + attribute \src "libresoc.v:145260.3-145261.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$6847 - attribute \src "libresoc.v:143598.3-143599.55" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 + attribute \src "libresoc.v:145230.3-145231.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6848 - attribute \src "libresoc.v:143600.3-143601.69" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 + attribute \src "libresoc.v:145232.3-145233.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6849 - attribute \src "libresoc.v:143602.3-143603.65" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6897 + attribute \src "libresoc.v:145234.3-145235.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6850 - attribute \src "libresoc.v:143616.3-143617.63" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6898 + attribute \src "libresoc.v:145248.3-145249.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 32 $0\logical_op__insn$next[31:0]$6851 - attribute \src "libresoc.v:143630.3-143631.49" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $0\logical_op__insn$next[31:0]$6899 + attribute \src "libresoc.v:145262.3-145263.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6852 - attribute \src "libresoc.v:143596.3-143597.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6900 + attribute \src "libresoc.v:145228.3-145229.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__invert_in$next[0:0]$6853 - attribute \src "libresoc.v:143612.3-143613.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_in$next[0:0]$6901 + attribute \src "libresoc.v:145244.3-145245.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__invert_out$next[0:0]$6854 - attribute \src "libresoc.v:143618.3-143619.61" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__invert_out$next[0:0]$6902 + attribute \src "libresoc.v:145250.3-145251.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__is_32bit$next[0:0]$6855 - attribute \src "libresoc.v:143624.3-143625.57" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_32bit$next[0:0]$6903 + attribute \src "libresoc.v:145256.3-145257.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__is_signed$next[0:0]$6856 - attribute \src "libresoc.v:143626.3-143627.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__is_signed$next[0:0]$6904 + attribute \src "libresoc.v:145258.3-145259.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__oe__oe$next[0:0]$6857 - attribute \src "libresoc.v:143608.3-143609.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__oe$next[0:0]$6905 + attribute \src "libresoc.v:145240.3-145241.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__oe__ok$next[0:0]$6858 - attribute \src "libresoc.v:143610.3-143611.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__oe__ok$next[0:0]$6906 + attribute \src "libresoc.v:145242.3-145243.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__output_carry$next[0:0]$6859 - attribute \src "libresoc.v:143622.3-143623.65" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__output_carry$next[0:0]$6907 + attribute \src "libresoc.v:145254.3-145255.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__rc__ok$next[0:0]$6860 - attribute \src "libresoc.v:143606.3-143607.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__ok$next[0:0]$6908 + attribute \src "libresoc.v:145238.3-145239.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__rc__rc$next[0:0]$6861 - attribute \src "libresoc.v:143604.3-143605.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__rc__rc$next[0:0]$6909 + attribute \src "libresoc.v:145236.3-145237.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__write_cr0$next[0:0]$6862 - attribute \src "libresoc.v:143620.3-143621.59" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__write_cr0$next[0:0]$6910 + attribute \src "libresoc.v:145252.3-145253.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $0\logical_op__zero_a$next[0:0]$6863 - attribute \src "libresoc.v:143614.3-143615.53" + attribute \src "libresoc.v:145399.3-145440.6" + wire $0\logical_op__zero_a$next[0:0]$6911 + attribute \src "libresoc.v:145246.3-145247.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:143754.3-143766.6" - wire width 2 $0\muxid$next[1:0]$6843 - attribute \src "libresoc.v:143632.3-143633.27" + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $0\muxid$next[1:0]$6891 + attribute \src "libresoc.v:145264.3-145265.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire width 64 $0\o$next[63:0]$6889 - attribute \src "libresoc.v:143592.3-143593.19" + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $0\o$next[63:0]$6937 + attribute \src "libresoc.v:145224.3-145225.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire $0\o_ok$next[0:0]$6890 - attribute \src "libresoc.v:143594.3-143595.25" + attribute \src "libresoc.v:145441.3-145459.6" + wire $0\o_ok$next[0:0]$6938 + attribute \src "libresoc.v:145226.3-145227.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:143736.3-143753.6" - wire $0\r_busy$next[0:0]$6839 - attribute \src "libresoc.v:143634.3-143635.29" + attribute \src "libresoc.v:145368.3-145385.6" + wire $0\r_busy$next[0:0]$6887 + attribute \src "libresoc.v:145266.3-145267.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $0\xer_so$next[0:0]$6901 - attribute \src "libresoc.v:143584.3-143585.29" + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so$next[0:0]$6949 + attribute \src "libresoc.v:145216.3-145217.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $0\xer_so_ok$next[0:0]$6902 - attribute \src "libresoc.v:143586.3-143587.35" + attribute \src "libresoc.v:145479.3-145497.6" + wire $0\xer_so_ok$next[0:0]$6950 + attribute \src "libresoc.v:145218.3-145219.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire width 4 $1\cr_a$next[3:0]$6897 - attribute \src "libresoc.v:142508.13-142508.24" + attribute \src "libresoc.v:145460.3-145478.6" + wire width 4 $1\cr_a$next[3:0]$6945 + attribute \src "libresoc.v:144140.13-144140.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $1\cr_a_ok$next[0:0]$6898 - attribute \src "libresoc.v:142517.7-142517.21" + attribute \src "libresoc.v:145460.3-145478.6" + wire $1\cr_a_ok$next[0:0]$6946 + attribute \src "libresoc.v:144149.7-144149.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6864 - attribute \src "libresoc.v:142802.13-142802.40" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6912 + attribute \src "libresoc.v:144434.13-144434.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$6865 - attribute \src "libresoc.v:142826.14-142826.44" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 + attribute \src "libresoc.v:144458.14-144458.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6866 - attribute \src "libresoc.v:142865.14-142865.63" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 + attribute \src "libresoc.v:144497.14-144497.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6867 - attribute \src "libresoc.v:142874.7-142874.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6915 + attribute \src "libresoc.v:144506.7-144506.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6868 - attribute \src "libresoc.v:142887.13-142887.43" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6916 + attribute \src "libresoc.v:144519.13-144519.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 32 $1\logical_op__insn$next[31:0]$6869 - attribute \src "libresoc.v:142904.14-142904.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 32 $1\logical_op__insn$next[31:0]$6917 + attribute \src "libresoc.v:144536.14-144536.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6870 - attribute \src "libresoc.v:142988.13-142988.42" + attribute \src "libresoc.v:145399.3-145440.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6918 + attribute \src "libresoc.v:144620.13-144620.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__invert_in$next[0:0]$6871 - attribute \src "libresoc.v:143147.7-143147.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_in$next[0:0]$6919 + attribute \src "libresoc.v:144779.7-144779.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__invert_out$next[0:0]$6872 - attribute \src "libresoc.v:143156.7-143156.36" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__invert_out$next[0:0]$6920 + attribute \src "libresoc.v:144788.7-144788.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__is_32bit$next[0:0]$6873 - attribute \src "libresoc.v:143165.7-143165.34" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_32bit$next[0:0]$6921 + attribute \src "libresoc.v:144797.7-144797.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__is_signed$next[0:0]$6874 - attribute \src "libresoc.v:143174.7-143174.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__is_signed$next[0:0]$6922 + attribute \src "libresoc.v:144806.7-144806.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__oe__oe$next[0:0]$6875 - attribute \src "libresoc.v:143183.7-143183.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__oe$next[0:0]$6923 + attribute \src "libresoc.v:144815.7-144815.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__oe__ok$next[0:0]$6876 - attribute \src "libresoc.v:143192.7-143192.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__oe__ok$next[0:0]$6924 + attribute \src "libresoc.v:144824.7-144824.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__output_carry$next[0:0]$6877 - attribute \src "libresoc.v:143201.7-143201.38" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__output_carry$next[0:0]$6925 + attribute \src "libresoc.v:144833.7-144833.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__rc__ok$next[0:0]$6878 - attribute \src "libresoc.v:143210.7-143210.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__ok$next[0:0]$6926 + attribute \src "libresoc.v:144842.7-144842.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__rc__rc$next[0:0]$6879 - attribute \src "libresoc.v:143219.7-143219.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__rc__rc$next[0:0]$6927 + attribute \src "libresoc.v:144851.7-144851.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__write_cr0$next[0:0]$6880 - attribute \src "libresoc.v:143228.7-143228.35" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__write_cr0$next[0:0]$6928 + attribute \src "libresoc.v:144860.7-144860.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143767.3-143808.6" - wire $1\logical_op__zero_a$next[0:0]$6881 - attribute \src "libresoc.v:143237.7-143237.32" + attribute \src "libresoc.v:145399.3-145440.6" + wire $1\logical_op__zero_a$next[0:0]$6929 + attribute \src "libresoc.v:144869.7-144869.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:143754.3-143766.6" - wire width 2 $1\muxid$next[1:0]$6844 - attribute \src "libresoc.v:143522.13-143522.25" + attribute \src "libresoc.v:145386.3-145398.6" + wire width 2 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145154.13-145154.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire width 64 $1\o$next[63:0]$6891 - attribute \src "libresoc.v:143537.14-143537.38" + attribute \src "libresoc.v:145441.3-145459.6" + wire width 64 $1\o$next[63:0]$6939 + attribute \src "libresoc.v:145169.14-145169.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:143809.3-143827.6" - wire $1\o_ok$next[0:0]$6892 - attribute \src "libresoc.v:143544.7-143544.18" + attribute \src "libresoc.v:145441.3-145459.6" + wire $1\o_ok$next[0:0]$6940 + attribute \src "libresoc.v:145176.7-145176.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:143736.3-143753.6" - wire $1\r_busy$next[0:0]$6840 - attribute \src "libresoc.v:143558.7-143558.20" + attribute \src "libresoc.v:145368.3-145385.6" + wire $1\r_busy$next[0:0]$6888 + attribute \src "libresoc.v:145190.7-145190.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $1\xer_so$next[0:0]$6903 - attribute \src "libresoc.v:143567.7-143567.20" + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so$next[0:0]$6951 + attribute \src "libresoc.v:145199.7-145199.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:143847.3-143865.6" - wire $1\xer_so_ok$next[0:0]$6904 - attribute \src "libresoc.v:143576.7-143576.23" + attribute \src "libresoc.v:145479.3-145497.6" + wire $1\xer_so_ok$next[0:0]$6952 + attribute \src "libresoc.v:145208.7-145208.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:143828.3-143846.6" - wire $2\cr_a_ok$next[0:0]$6899 - attribute \src "libresoc.v:143767.3-143808.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6882 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6883 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__oe__oe$next[0:0]$6884 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__oe__ok$next[0:0]$6885 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__rc__ok$next[0:0]$6886 - attribute \src "libresoc.v:143767.3-143808.6" - wire $2\logical_op__rc__rc$next[0:0]$6887 - attribute \src "libresoc.v:143809.3-143827.6" - wire $2\o_ok$next[0:0]$6893 - attribute \src "libresoc.v:143736.3-143753.6" - wire $2\r_busy$next[0:0]$6841 - attribute \src "libresoc.v:143847.3-143865.6" - wire $2\xer_so_ok$next[0:0]$6905 - attribute \src "libresoc.v:143583.18-143583.118" - wire $and$libresoc.v:143583$6811_Y + attribute \src "libresoc.v:145460.3-145478.6" + wire $2\cr_a_ok$next[0:0]$6947 + attribute \src "libresoc.v:145399.3-145440.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6930 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6931 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__oe__oe$next[0:0]$6932 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__oe__ok$next[0:0]$6933 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__rc__ok$next[0:0]$6934 + attribute \src "libresoc.v:145399.3-145440.6" + wire $2\logical_op__rc__rc$next[0:0]$6935 + attribute \src "libresoc.v:145441.3-145459.6" + wire $2\o_ok$next[0:0]$6941 + attribute \src "libresoc.v:145368.3-145385.6" + wire $2\r_busy$next[0:0]$6889 + attribute \src "libresoc.v:145479.3-145497.6" + wire $2\xer_so_ok$next[0:0]$6953 + attribute \src "libresoc.v:145215.18-145215.118" + wire $and$libresoc.v:145215$6859_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -232829,7 +235326,7 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:142499.7-142499.15" + attribute \src "libresoc.v:144131.7-144131.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -233868,7 +236365,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:143583$6811 + cell $and $and$libresoc.v:145215$6859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233876,10 +236373,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:143583$6811_Y + connect \Y $and$libresoc.v:145215$6859_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143636.14-143681.4" + attribute \src "libresoc.v:145268.14-145313.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -233927,7 +236424,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143682.13-143727.4" + attribute \src "libresoc.v:145314.13-145359.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -233975,424 +236472,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:143728.10-143731.4" + attribute \src "libresoc.v:145360.10-145363.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:143732.10-143735.4" + attribute \src "libresoc.v:145364.10-145367.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:142499.7-142499.20" - process $proc$libresoc.v:142499$6906 + attribute \src "libresoc.v:144131.7-144131.20" + process $proc$libresoc.v:144131$6954 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142508.13-142508.24" - process $proc$libresoc.v:142508$6907 + attribute \src "libresoc.v:144140.13-144140.24" + process $proc$libresoc.v:144140$6955 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:142517.7-142517.21" - process $proc$libresoc.v:142517$6908 + attribute \src "libresoc.v:144149.7-144149.21" + process $proc$libresoc.v:144149$6956 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:142802.13-142802.40" - process $proc$libresoc.v:142802$6909 + attribute \src "libresoc.v:144434.13-144434.40" + process $proc$libresoc.v:144434$6957 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:142826.14-142826.44" - process $proc$libresoc.v:142826$6910 + attribute \src "libresoc.v:144458.14-144458.44" + process $proc$libresoc.v:144458$6958 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:142865.14-142865.63" - process $proc$libresoc.v:142865$6911 + attribute \src "libresoc.v:144497.14-144497.63" + process $proc$libresoc.v:144497$6959 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:142874.7-142874.38" - process $proc$libresoc.v:142874$6912 + attribute \src "libresoc.v:144506.7-144506.38" + process $proc$libresoc.v:144506$6960 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:142887.13-142887.43" - process $proc$libresoc.v:142887$6913 + attribute \src "libresoc.v:144519.13-144519.43" + process $proc$libresoc.v:144519$6961 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:142904.14-142904.38" - process $proc$libresoc.v:142904$6914 + attribute \src "libresoc.v:144536.14-144536.38" + process $proc$libresoc.v:144536$6962 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:142988.13-142988.42" - process $proc$libresoc.v:142988$6915 + attribute \src "libresoc.v:144620.13-144620.42" + process $proc$libresoc.v:144620$6963 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143147.7-143147.35" - process $proc$libresoc.v:143147$6916 + attribute \src "libresoc.v:144779.7-144779.35" + process $proc$libresoc.v:144779$6964 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143156.7-143156.36" - process $proc$libresoc.v:143156$6917 + attribute \src "libresoc.v:144788.7-144788.36" + process $proc$libresoc.v:144788$6965 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143165.7-143165.34" - process $proc$libresoc.v:143165$6918 + attribute \src "libresoc.v:144797.7-144797.34" + process $proc$libresoc.v:144797$6966 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143174.7-143174.35" - process $proc$libresoc.v:143174$6919 + attribute \src "libresoc.v:144806.7-144806.35" + process $proc$libresoc.v:144806$6967 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143183.7-143183.32" - process $proc$libresoc.v:143183$6920 + attribute \src "libresoc.v:144815.7-144815.32" + process $proc$libresoc.v:144815$6968 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143192.7-143192.32" - process $proc$libresoc.v:143192$6921 + attribute \src "libresoc.v:144824.7-144824.32" + process $proc$libresoc.v:144824$6969 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143201.7-143201.38" - process $proc$libresoc.v:143201$6922 + attribute \src "libresoc.v:144833.7-144833.38" + process $proc$libresoc.v:144833$6970 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143210.7-143210.32" - process $proc$libresoc.v:143210$6923 + attribute \src "libresoc.v:144842.7-144842.32" + process $proc$libresoc.v:144842$6971 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143219.7-143219.32" - process $proc$libresoc.v:143219$6924 + attribute \src "libresoc.v:144851.7-144851.32" + process $proc$libresoc.v:144851$6972 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143228.7-143228.35" - process $proc$libresoc.v:143228$6925 + attribute \src "libresoc.v:144860.7-144860.35" + process $proc$libresoc.v:144860$6973 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143237.7-143237.32" - process $proc$libresoc.v:143237$6926 + attribute \src "libresoc.v:144869.7-144869.32" + process $proc$libresoc.v:144869$6974 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143522.13-143522.25" - process $proc$libresoc.v:143522$6927 + attribute \src "libresoc.v:145154.13-145154.25" + process $proc$libresoc.v:145154$6975 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:143537.14-143537.38" - process $proc$libresoc.v:143537$6928 + attribute \src "libresoc.v:145169.14-145169.38" + process $proc$libresoc.v:145169$6976 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:143544.7-143544.18" - process $proc$libresoc.v:143544$6929 + attribute \src "libresoc.v:145176.7-145176.18" + process $proc$libresoc.v:145176$6977 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:143558.7-143558.20" - process $proc$libresoc.v:143558$6930 + attribute \src "libresoc.v:145190.7-145190.20" + process $proc$libresoc.v:145190$6978 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:143567.7-143567.20" - process $proc$libresoc.v:143567$6931 + attribute \src "libresoc.v:145199.7-145199.20" + process $proc$libresoc.v:145199$6979 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:143576.7-143576.23" - process $proc$libresoc.v:143576$6932 + attribute \src "libresoc.v:145208.7-145208.23" + process $proc$libresoc.v:145208$6980 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:143584.3-143585.29" - process $proc$libresoc.v:143584$6812 + attribute \src "libresoc.v:145216.3-145217.29" + process $proc$libresoc.v:145216$6860 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:143586.3-143587.35" - process $proc$libresoc.v:143586$6813 + attribute \src "libresoc.v:145218.3-145219.35" + process $proc$libresoc.v:145218$6861 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:143588.3-143589.25" - process $proc$libresoc.v:143588$6814 + attribute \src "libresoc.v:145220.3-145221.25" + process $proc$libresoc.v:145220$6862 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:143590.3-143591.31" - process $proc$libresoc.v:143590$6815 + attribute \src "libresoc.v:145222.3-145223.31" + process $proc$libresoc.v:145222$6863 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:143592.3-143593.19" - process $proc$libresoc.v:143592$6816 + attribute \src "libresoc.v:145224.3-145225.19" + process $proc$libresoc.v:145224$6864 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:143594.3-143595.25" - process $proc$libresoc.v:143594$6817 + attribute \src "libresoc.v:145226.3-145227.25" + process $proc$libresoc.v:145226$6865 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:143596.3-143597.59" - process $proc$libresoc.v:143596$6818 + attribute \src "libresoc.v:145228.3-145229.59" + process $proc$libresoc.v:145228$6866 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143598.3-143599.55" - process $proc$libresoc.v:143598$6819 + attribute \src "libresoc.v:145230.3-145231.55" + process $proc$libresoc.v:145230$6867 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143600.3-143601.69" - process $proc$libresoc.v:143600$6820 + attribute \src "libresoc.v:145232.3-145233.69" + process $proc$libresoc.v:145232$6868 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143602.3-143603.65" - process $proc$libresoc.v:143602$6821 + attribute \src "libresoc.v:145234.3-145235.65" + process $proc$libresoc.v:145234$6869 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143604.3-143605.53" - process $proc$libresoc.v:143604$6822 + attribute \src "libresoc.v:145236.3-145237.53" + process $proc$libresoc.v:145236$6870 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143606.3-143607.53" - process $proc$libresoc.v:143606$6823 + attribute \src "libresoc.v:145238.3-145239.53" + process $proc$libresoc.v:145238$6871 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143608.3-143609.53" - process $proc$libresoc.v:143608$6824 + attribute \src "libresoc.v:145240.3-145241.53" + process $proc$libresoc.v:145240$6872 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143610.3-143611.53" - process $proc$libresoc.v:143610$6825 + attribute \src "libresoc.v:145242.3-145243.53" + process $proc$libresoc.v:145242$6873 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143612.3-143613.59" - process $proc$libresoc.v:143612$6826 + attribute \src "libresoc.v:145244.3-145245.59" + process $proc$libresoc.v:145244$6874 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143614.3-143615.53" - process $proc$libresoc.v:143614$6827 + attribute \src "libresoc.v:145246.3-145247.53" + process $proc$libresoc.v:145246$6875 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143616.3-143617.63" - process $proc$libresoc.v:143616$6828 + attribute \src "libresoc.v:145248.3-145249.63" + process $proc$libresoc.v:145248$6876 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143618.3-143619.61" - process $proc$libresoc.v:143618$6829 + attribute \src "libresoc.v:145250.3-145251.61" + process $proc$libresoc.v:145250$6877 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143620.3-143621.59" - process $proc$libresoc.v:143620$6830 + attribute \src "libresoc.v:145252.3-145253.59" + process $proc$libresoc.v:145252$6878 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143622.3-143623.65" - process $proc$libresoc.v:143622$6831 + attribute \src "libresoc.v:145254.3-145255.65" + process $proc$libresoc.v:145254$6879 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143624.3-143625.57" - process $proc$libresoc.v:143624$6832 + attribute \src "libresoc.v:145256.3-145257.57" + process $proc$libresoc.v:145256$6880 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143626.3-143627.59" - process $proc$libresoc.v:143626$6833 + attribute \src "libresoc.v:145258.3-145259.59" + process $proc$libresoc.v:145258$6881 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143628.3-143629.57" - process $proc$libresoc.v:143628$6834 + attribute \src "libresoc.v:145260.3-145261.57" + process $proc$libresoc.v:145260$6882 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:143630.3-143631.49" - process $proc$libresoc.v:143630$6835 + attribute \src "libresoc.v:145262.3-145263.49" + process $proc$libresoc.v:145262$6883 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:143632.3-143633.27" - process $proc$libresoc.v:143632$6836 + attribute \src "libresoc.v:145264.3-145265.27" + process $proc$libresoc.v:145264$6884 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:143634.3-143635.29" - process $proc$libresoc.v:143634$6837 + attribute \src "libresoc.v:145266.3-145267.29" + process $proc$libresoc.v:145266$6885 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:143736.3-143753.6" - process $proc$libresoc.v:143736$6838 + attribute \src "libresoc.v:145368.3-145385.6" + process $proc$libresoc.v:145368$6886 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6839 $2\r_busy$next[0:0]$6841 - attribute \src "libresoc.v:143737.5-143737.29" + assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 + attribute \src "libresoc.v:145369.5-145369.29" switch \initial - attribute \src "libresoc.v:143737.9-143737.17" + attribute \src "libresoc.v:145369.9-145369.17" case 1'1 case end @@ -234401,34 +236898,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6840 1'1 + assign $1\r_busy$next[0:0]$6888 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6840 1'0 + assign $1\r_busy$next[0:0]$6888 1'0 case - assign $1\r_busy$next[0:0]$6840 \r_busy + assign $1\r_busy$next[0:0]$6888 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6841 1'0 + assign $2\r_busy$next[0:0]$6889 1'0 case - assign $2\r_busy$next[0:0]$6841 $1\r_busy$next[0:0]$6840 + assign $2\r_busy$next[0:0]$6889 $1\r_busy$next[0:0]$6888 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6839 + update \r_busy$next $0\r_busy$next[0:0]$6887 end - attribute \src "libresoc.v:143754.3-143766.6" - process $proc$libresoc.v:143754$6842 + attribute \src "libresoc.v:145386.3-145398.6" + process $proc$libresoc.v:145386$6890 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6843 $1\muxid$next[1:0]$6844 - attribute \src "libresoc.v:143755.5-143755.29" + assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 + attribute \src "libresoc.v:145387.5-145387.29" switch \initial - attribute \src "libresoc.v:143755.9-143755.17" + attribute \src "libresoc.v:145387.9-145387.17" case 1'1 case end @@ -234437,19 +236934,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6844 \muxid$66 + assign $1\muxid$next[1:0]$6892 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6844 \muxid$66 + assign $1\muxid$next[1:0]$6892 \muxid$66 case - assign $1\muxid$next[1:0]$6844 \muxid + assign $1\muxid$next[1:0]$6892 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6843 + update \muxid$next $0\muxid$next[1:0]$6891 end - attribute \src "libresoc.v:143767.3-143808.6" - process $proc$libresoc.v:143767$6845 + attribute \src "libresoc.v:145399.3-145440.6" + process $proc$libresoc.v:145399$6893 assign { } { } assign { } { } assign { } { } @@ -234486,33 +236983,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6846 $1\logical_op__data_len$next[3:0]$6864 - assign $0\logical_op__fn_unit$next[13:0]$6847 $1\logical_op__fn_unit$next[13:0]$6865 + assign $0\logical_op__data_len$next[3:0]$6894 $1\logical_op__data_len$next[3:0]$6912 + assign $0\logical_op__fn_unit$next[13:0]$6895 $1\logical_op__fn_unit$next[13:0]$6913 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6850 $1\logical_op__input_carry$next[1:0]$6868 - assign $0\logical_op__insn$next[31:0]$6851 $1\logical_op__insn$next[31:0]$6869 - assign $0\logical_op__insn_type$next[6:0]$6852 $1\logical_op__insn_type$next[6:0]$6870 - assign $0\logical_op__invert_in$next[0:0]$6853 $1\logical_op__invert_in$next[0:0]$6871 - assign $0\logical_op__invert_out$next[0:0]$6854 $1\logical_op__invert_out$next[0:0]$6872 - assign $0\logical_op__is_32bit$next[0:0]$6855 $1\logical_op__is_32bit$next[0:0]$6873 - assign $0\logical_op__is_signed$next[0:0]$6856 $1\logical_op__is_signed$next[0:0]$6874 + assign $0\logical_op__input_carry$next[1:0]$6898 $1\logical_op__input_carry$next[1:0]$6916 + assign $0\logical_op__insn$next[31:0]$6899 $1\logical_op__insn$next[31:0]$6917 + assign $0\logical_op__insn_type$next[6:0]$6900 $1\logical_op__insn_type$next[6:0]$6918 + assign $0\logical_op__invert_in$next[0:0]$6901 $1\logical_op__invert_in$next[0:0]$6919 + assign $0\logical_op__invert_out$next[0:0]$6902 $1\logical_op__invert_out$next[0:0]$6920 + assign $0\logical_op__is_32bit$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6921 + assign $0\logical_op__is_signed$next[0:0]$6904 $1\logical_op__is_signed$next[0:0]$6922 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6859 $1\logical_op__output_carry$next[0:0]$6877 + assign $0\logical_op__output_carry$next[0:0]$6907 $1\logical_op__output_carry$next[0:0]$6925 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6862 $1\logical_op__write_cr0$next[0:0]$6880 - assign $0\logical_op__zero_a$next[0:0]$6863 $1\logical_op__zero_a$next[0:0]$6881 - assign $0\logical_op__imm_data__data$next[63:0]$6848 $2\logical_op__imm_data__data$next[63:0]$6882 - assign $0\logical_op__imm_data__ok$next[0:0]$6849 $2\logical_op__imm_data__ok$next[0:0]$6883 - assign $0\logical_op__oe__oe$next[0:0]$6857 $2\logical_op__oe__oe$next[0:0]$6884 - assign $0\logical_op__oe__ok$next[0:0]$6858 $2\logical_op__oe__ok$next[0:0]$6885 - assign $0\logical_op__rc__ok$next[0:0]$6860 $2\logical_op__rc__ok$next[0:0]$6886 - assign $0\logical_op__rc__rc$next[0:0]$6861 $2\logical_op__rc__rc$next[0:0]$6887 - attribute \src "libresoc.v:143768.5-143768.29" + assign $0\logical_op__write_cr0$next[0:0]$6910 $1\logical_op__write_cr0$next[0:0]$6928 + assign $0\logical_op__zero_a$next[0:0]$6911 $1\logical_op__zero_a$next[0:0]$6929 + assign $0\logical_op__imm_data__data$next[63:0]$6896 $2\logical_op__imm_data__data$next[63:0]$6930 + assign $0\logical_op__imm_data__ok$next[0:0]$6897 $2\logical_op__imm_data__ok$next[0:0]$6931 + assign $0\logical_op__oe__oe$next[0:0]$6905 $2\logical_op__oe__oe$next[0:0]$6932 + assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 + assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 + assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 + attribute \src "libresoc.v:145400.5-145400.29" switch \initial - attribute \src "libresoc.v:143768.9-143768.17" + attribute \src "libresoc.v:145400.9-145400.17" case 1'1 case end @@ -234538,7 +237035,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -234559,26 +237056,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6869 $1\logical_op__data_len$next[3:0]$6864 $1\logical_op__is_signed$next[0:0]$6874 $1\logical_op__is_32bit$next[0:0]$6873 $1\logical_op__output_carry$next[0:0]$6877 $1\logical_op__write_cr0$next[0:0]$6880 $1\logical_op__invert_out$next[0:0]$6872 $1\logical_op__input_carry$next[1:0]$6868 $1\logical_op__zero_a$next[0:0]$6881 $1\logical_op__invert_in$next[0:0]$6871 $1\logical_op__oe__ok$next[0:0]$6876 $1\logical_op__oe__oe$next[0:0]$6875 $1\logical_op__rc__ok$next[0:0]$6878 $1\logical_op__rc__rc$next[0:0]$6879 $1\logical_op__imm_data__ok$next[0:0]$6867 $1\logical_op__imm_data__data$next[63:0]$6866 $1\logical_op__fn_unit$next[13:0]$6865 $1\logical_op__insn_type$next[6:0]$6870 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6864 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$6865 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6866 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6867 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6868 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6869 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6870 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6871 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6872 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6873 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6874 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6875 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6876 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6877 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6878 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6879 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6880 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6881 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6912 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6913 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6914 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6915 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6916 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6917 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6918 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6919 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6920 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6921 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6922 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6923 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6924 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6925 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6926 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6927 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6928 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6929 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -234590,52 +237087,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6882 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6883 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6887 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6886 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6884 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6885 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6935 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6934 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6932 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6933 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6882 $1\logical_op__imm_data__data$next[63:0]$6866 - assign $2\logical_op__imm_data__ok$next[0:0]$6883 $1\logical_op__imm_data__ok$next[0:0]$6867 - assign $2\logical_op__oe__oe$next[0:0]$6884 $1\logical_op__oe__oe$next[0:0]$6875 - assign $2\logical_op__oe__ok$next[0:0]$6885 $1\logical_op__oe__ok$next[0:0]$6876 - assign $2\logical_op__rc__ok$next[0:0]$6886 $1\logical_op__rc__ok$next[0:0]$6878 - assign $2\logical_op__rc__rc$next[0:0]$6887 $1\logical_op__rc__rc$next[0:0]$6879 + assign $2\logical_op__imm_data__data$next[63:0]$6930 $1\logical_op__imm_data__data$next[63:0]$6914 + assign $2\logical_op__imm_data__ok$next[0:0]$6931 $1\logical_op__imm_data__ok$next[0:0]$6915 + assign $2\logical_op__oe__oe$next[0:0]$6932 $1\logical_op__oe__oe$next[0:0]$6923 + assign $2\logical_op__oe__ok$next[0:0]$6933 $1\logical_op__oe__ok$next[0:0]$6924 + assign $2\logical_op__rc__ok$next[0:0]$6934 $1\logical_op__rc__ok$next[0:0]$6926 + assign $2\logical_op__rc__rc$next[0:0]$6935 $1\logical_op__rc__rc$next[0:0]$6927 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6846 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6847 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6848 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6849 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6850 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6851 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6852 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6853 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6854 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6855 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6856 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6857 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6858 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6859 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6860 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6861 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6862 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6863 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6894 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6895 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6896 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6897 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6898 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6899 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6900 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6901 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6902 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6903 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6904 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6905 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6906 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6907 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6908 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6909 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 end - attribute \src "libresoc.v:143809.3-143827.6" - process $proc$libresoc.v:143809$6888 + attribute \src "libresoc.v:145441.3-145459.6" + process $proc$libresoc.v:145441$6936 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6889 $1\o$next[63:0]$6891 + assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 assign { } { } - assign $0\o_ok$next[0:0]$6890 $2\o_ok$next[0:0]$6893 - attribute \src "libresoc.v:143810.5-143810.29" + assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 + attribute \src "libresoc.v:145442.5-145442.29" switch \initial - attribute \src "libresoc.v:143810.9-143810.17" + attribute \src "libresoc.v:145442.9-145442.17" case 1'1 case end @@ -234645,41 +237142,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6892 $1\o$next[63:0]$6891 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6891 \o - assign $1\o_ok$next[0:0]$6892 \o_ok + assign $1\o$next[63:0]$6939 \o + assign $1\o_ok$next[0:0]$6940 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6893 1'0 + assign $2\o_ok$next[0:0]$6941 1'0 case - assign $2\o_ok$next[0:0]$6893 $1\o_ok$next[0:0]$6892 + assign $2\o_ok$next[0:0]$6941 $1\o_ok$next[0:0]$6940 end sync always - update \o$next $0\o$next[63:0]$6889 - update \o_ok$next $0\o_ok$next[0:0]$6890 + update \o$next $0\o$next[63:0]$6937 + update \o_ok$next $0\o_ok$next[0:0]$6938 end - attribute \src "libresoc.v:143828.3-143846.6" - process $proc$libresoc.v:143828$6894 + attribute \src "libresoc.v:145460.3-145478.6" + process $proc$libresoc.v:145460$6942 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6895 $1\cr_a$next[3:0]$6897 + assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 assign { } { } - assign $0\cr_a_ok$next[0:0]$6896 $2\cr_a_ok$next[0:0]$6899 - attribute \src "libresoc.v:143829.5-143829.29" + assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 + attribute \src "libresoc.v:145461.5-145461.29" switch \initial - attribute \src "libresoc.v:143829.9-143829.17" + attribute \src "libresoc.v:145461.9-145461.17" case 1'1 case end @@ -234689,41 +237186,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6898 $1\cr_a$next[3:0]$6897 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6897 \cr_a - assign $1\cr_a_ok$next[0:0]$6898 \cr_a_ok + assign $1\cr_a$next[3:0]$6945 \cr_a + assign $1\cr_a_ok$next[0:0]$6946 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6899 1'0 + assign $2\cr_a_ok$next[0:0]$6947 1'0 case - assign $2\cr_a_ok$next[0:0]$6899 $1\cr_a_ok$next[0:0]$6898 + assign $2\cr_a_ok$next[0:0]$6947 $1\cr_a_ok$next[0:0]$6946 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6895 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6896 + update \cr_a$next $0\cr_a$next[3:0]$6943 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 end - attribute \src "libresoc.v:143847.3-143865.6" - process $proc$libresoc.v:143847$6900 + attribute \src "libresoc.v:145479.3-145497.6" + process $proc$libresoc.v:145479$6948 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6901 $1\xer_so$next[0:0]$6903 + assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 assign { } { } - assign $0\xer_so_ok$next[0:0]$6902 $2\xer_so_ok$next[0:0]$6905 - attribute \src "libresoc.v:143848.5-143848.29" + assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 + attribute \src "libresoc.v:145480.5-145480.29" switch \initial - attribute \src "libresoc.v:143848.9-143848.17" + attribute \src "libresoc.v:145480.9-145480.17" case 1'1 case end @@ -234733,30 +237230,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6904 $1\xer_so$next[0:0]$6903 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6903 \xer_so - assign $1\xer_so_ok$next[0:0]$6904 \xer_so_ok + assign $1\xer_so$next[0:0]$6951 \xer_so + assign $1\xer_so_ok$next[0:0]$6952 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6905 1'0 + assign $2\xer_so_ok$next[0:0]$6953 1'0 case - assign $2\xer_so_ok$next[0:0]$6905 $1\xer_so_ok$next[0:0]$6904 + assign $2\xer_so_ok$next[0:0]$6953 $1\xer_so_ok$next[0:0]$6952 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6901 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6902 + update \xer_so$next $0\xer_so$next[0:0]$6949 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 end - connect \$64 $and$libresoc.v:143583$6811_Y + connect \$64 $and$libresoc.v:145215$6859_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -234781,230 +237278,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:143893.1-144926.10" +attribute \src "libresoc.v:145525.1-146558.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:144893.3-144911.6" - wire width 4 $0\cr_a$22$next[3:0]$7038 - attribute \src "libresoc.v:144697.3-144698.33" - wire width 4 $0\cr_a$22[3:0]$6935 - attribute \src "libresoc.v:143905.13-143905.29" - wire width 4 $0\cr_a$22[3:0]$7045 - attribute \src "libresoc.v:144893.3-144911.6" - wire $0\cr_a_ok$23$next[0:0]$7039 - attribute \src "libresoc.v:144699.3-144700.39" - wire $0\cr_a_ok$23[0:0]$6937 - attribute \src "libresoc.v:143914.7-143914.26" - wire $0\cr_a_ok$23[0:0]$7047 - attribute \src "libresoc.v:143894.7-143894.20" + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $0\cr_a$22$next[3:0]$7086 + attribute \src "libresoc.v:146329.3-146330.33" + wire width 4 $0\cr_a$22[3:0]$6983 + attribute \src "libresoc.v:145537.13-145537.29" + wire width 4 $0\cr_a$22[3:0]$7093 + attribute \src "libresoc.v:146525.3-146543.6" + wire $0\cr_a_ok$23$next[0:0]$7087 + attribute \src "libresoc.v:146331.3-146332.39" + wire $0\cr_a_ok$23[0:0]$6985 + attribute \src "libresoc.v:145546.7-145546.26" + wire $0\cr_a_ok$23[0:0]$7095 + attribute \src "libresoc.v:145526.7-145526.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144832.3-144873.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6989 - attribute \src "libresoc.v:144737.3-144738.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6975 - attribute \src "libresoc.v:143925.13-143925.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7049 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6990 - attribute \src "libresoc.v:144707.3-144708.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$6945 - attribute \src "libresoc.v:143964.14-143964.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$7051 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6991 - attribute \src "libresoc.v:144709.3-144710.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6947 - attribute \src "libresoc.v:143988.14-143988.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7053 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6992 - attribute \src "libresoc.v:144711.3-144712.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6949 - attribute \src "libresoc.v:143997.7-143997.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7055 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6993 - attribute \src "libresoc.v:144725.3-144726.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6963 - attribute \src "libresoc.v:144014.13-144014.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7057 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6994 - attribute \src "libresoc.v:144739.3-144740.57" - wire width 32 $0\logical_op__insn$19[31:0]$6977 - attribute \src "libresoc.v:144027.14-144027.43" - wire width 32 $0\logical_op__insn$19[31:0]$7059 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6995 - attribute \src "libresoc.v:144705.3-144706.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6943 - attribute \src "libresoc.v:144186.13-144186.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7061 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__invert_in$10$next[0:0]$6996 - attribute \src "libresoc.v:144721.3-144722.67" - wire $0\logical_op__invert_in$10[0:0]$6959 - attribute \src "libresoc.v:144270.7-144270.40" - wire $0\logical_op__invert_in$10[0:0]$7063 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__invert_out$13$next[0:0]$6997 - attribute \src "libresoc.v:144727.3-144728.69" - wire $0\logical_op__invert_out$13[0:0]$6965 - attribute \src "libresoc.v:144279.7-144279.41" - wire $0\logical_op__invert_out$13[0:0]$7065 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6998 - attribute \src "libresoc.v:144733.3-144734.65" - wire $0\logical_op__is_32bit$16[0:0]$6971 - attribute \src "libresoc.v:144288.7-144288.39" - wire $0\logical_op__is_32bit$16[0:0]$7067 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__is_signed$17$next[0:0]$6999 - attribute \src "libresoc.v:144735.3-144736.67" - wire $0\logical_op__is_signed$17[0:0]$6973 - attribute \src "libresoc.v:144297.7-144297.40" - wire $0\logical_op__is_signed$17[0:0]$7069 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__oe__oe$8$next[0:0]$7000 - attribute \src "libresoc.v:144717.3-144718.59" - wire $0\logical_op__oe__oe$8[0:0]$6955 - attribute \src "libresoc.v:144308.7-144308.36" - wire $0\logical_op__oe__oe$8[0:0]$7071 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__oe__ok$9$next[0:0]$7001 - attribute \src "libresoc.v:144719.3-144720.59" - wire $0\logical_op__oe__ok$9[0:0]$6957 - attribute \src "libresoc.v:144317.7-144317.36" - wire $0\logical_op__oe__ok$9[0:0]$7073 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__output_carry$15$next[0:0]$7002 - attribute \src "libresoc.v:144731.3-144732.73" - wire $0\logical_op__output_carry$15[0:0]$6969 - attribute \src "libresoc.v:144324.7-144324.43" - wire $0\logical_op__output_carry$15[0:0]$7075 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__rc__ok$7$next[0:0]$7003 - attribute \src "libresoc.v:144715.3-144716.59" - wire $0\logical_op__rc__ok$7[0:0]$6953 - attribute \src "libresoc.v:144335.7-144335.36" - wire $0\logical_op__rc__ok$7[0:0]$7077 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__rc__rc$6$next[0:0]$7004 - attribute \src "libresoc.v:144713.3-144714.59" - wire $0\logical_op__rc__rc$6[0:0]$6951 - attribute \src "libresoc.v:144344.7-144344.36" - wire $0\logical_op__rc__rc$6[0:0]$7079 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__write_cr0$14$next[0:0]$7005 - attribute \src "libresoc.v:144729.3-144730.67" - wire $0\logical_op__write_cr0$14[0:0]$6967 - attribute \src "libresoc.v:144351.7-144351.40" - wire $0\logical_op__write_cr0$14[0:0]$7081 - attribute \src "libresoc.v:144832.3-144873.6" - wire $0\logical_op__zero_a$11$next[0:0]$7006 - attribute \src "libresoc.v:144723.3-144724.61" - wire $0\logical_op__zero_a$11[0:0]$6961 - attribute \src "libresoc.v:144360.7-144360.37" - wire $0\logical_op__zero_a$11[0:0]$7083 - attribute \src "libresoc.v:144819.3-144831.6" - wire width 2 $0\muxid$1$next[1:0]$6986 - attribute \src "libresoc.v:144741.3-144742.33" - wire width 2 $0\muxid$1[1:0]$6979 - attribute \src "libresoc.v:144369.13-144369.29" - wire width 2 $0\muxid$1[1:0]$7085 - attribute \src "libresoc.v:144874.3-144892.6" - wire width 64 $0\o$20$next[63:0]$7032 - attribute \src "libresoc.v:144701.3-144702.27" - wire width 64 $0\o$20[63:0]$6939 - attribute \src "libresoc.v:144384.14-144384.43" - wire width 64 $0\o$20[63:0]$7087 - attribute \src "libresoc.v:144874.3-144892.6" - wire $0\o_ok$21$next[0:0]$7033 - attribute \src "libresoc.v:144703.3-144704.33" - wire $0\o_ok$21[0:0]$6941 - attribute \src "libresoc.v:144393.7-144393.23" - wire $0\o_ok$21[0:0]$7089 - attribute \src "libresoc.v:144801.3-144818.6" - wire $0\r_busy$next[0:0]$6982 - attribute \src "libresoc.v:144743.3-144744.29" + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 + attribute \src "libresoc.v:146369.3-146370.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7023 + attribute \src "libresoc.v:145557.13-145557.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7097 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 + attribute \src "libresoc.v:146339.3-146340.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 + attribute \src "libresoc.v:145596.14-145596.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 + attribute \src "libresoc.v:146341.3-146342.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 + attribute \src "libresoc.v:145620.14-145620.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 + attribute \src "libresoc.v:146343.3-146344.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6997 + attribute \src "libresoc.v:145629.7-145629.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7103 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 + attribute \src "libresoc.v:146357.3-146358.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$7011 + attribute \src "libresoc.v:145646.13-145646.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7105 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7042 + attribute \src "libresoc.v:146371.3-146372.57" + wire width 32 $0\logical_op__insn$19[31:0]$7025 + attribute \src "libresoc.v:145659.14-145659.43" + wire width 32 $0\logical_op__insn$19[31:0]$7107 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 + attribute \src "libresoc.v:146337.3-146338.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6991 + attribute \src "libresoc.v:145818.13-145818.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7109 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_in$10$next[0:0]$7044 + attribute \src "libresoc.v:146353.3-146354.67" + wire $0\logical_op__invert_in$10[0:0]$7007 + attribute \src "libresoc.v:145902.7-145902.40" + wire $0\logical_op__invert_in$10[0:0]$7111 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__invert_out$13$next[0:0]$7045 + attribute \src "libresoc.v:146359.3-146360.69" + wire $0\logical_op__invert_out$13[0:0]$7013 + attribute \src "libresoc.v:145911.7-145911.41" + wire $0\logical_op__invert_out$13[0:0]$7113 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7046 + attribute \src "libresoc.v:146365.3-146366.65" + wire $0\logical_op__is_32bit$16[0:0]$7019 + attribute \src "libresoc.v:145920.7-145920.39" + wire $0\logical_op__is_32bit$16[0:0]$7115 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__is_signed$17$next[0:0]$7047 + attribute \src "libresoc.v:146367.3-146368.67" + wire $0\logical_op__is_signed$17[0:0]$7021 + attribute \src "libresoc.v:145929.7-145929.40" + wire $0\logical_op__is_signed$17[0:0]$7117 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7048 + attribute \src "libresoc.v:146349.3-146350.59" + wire $0\logical_op__oe__oe$8[0:0]$7003 + attribute \src "libresoc.v:145940.7-145940.36" + wire $0\logical_op__oe__oe$8[0:0]$7119 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7049 + attribute \src "libresoc.v:146351.3-146352.59" + wire $0\logical_op__oe__ok$9[0:0]$7005 + attribute \src "libresoc.v:145949.7-145949.36" + wire $0\logical_op__oe__ok$9[0:0]$7121 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__output_carry$15$next[0:0]$7050 + attribute \src "libresoc.v:146363.3-146364.73" + wire $0\logical_op__output_carry$15[0:0]$7017 + attribute \src "libresoc.v:145956.7-145956.43" + wire $0\logical_op__output_carry$15[0:0]$7123 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7051 + attribute \src "libresoc.v:146347.3-146348.59" + wire $0\logical_op__rc__ok$7[0:0]$7001 + attribute \src "libresoc.v:145967.7-145967.36" + wire $0\logical_op__rc__ok$7[0:0]$7125 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7052 + attribute \src "libresoc.v:146345.3-146346.59" + wire $0\logical_op__rc__rc$6[0:0]$6999 + attribute \src "libresoc.v:145976.7-145976.36" + wire $0\logical_op__rc__rc$6[0:0]$7127 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7053 + attribute \src "libresoc.v:146361.3-146362.67" + wire $0\logical_op__write_cr0$14[0:0]$7015 + attribute \src "libresoc.v:145983.7-145983.40" + wire $0\logical_op__write_cr0$14[0:0]$7129 + attribute \src "libresoc.v:146464.3-146505.6" + wire $0\logical_op__zero_a$11$next[0:0]$7054 + attribute \src "libresoc.v:146355.3-146356.61" + wire $0\logical_op__zero_a$11[0:0]$7009 + attribute \src "libresoc.v:145992.7-145992.37" + wire $0\logical_op__zero_a$11[0:0]$7131 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $0\muxid$1$next[1:0]$7034 + attribute \src "libresoc.v:146373.3-146374.33" + wire width 2 $0\muxid$1[1:0]$7027 + attribute \src "libresoc.v:146001.13-146001.29" + wire width 2 $0\muxid$1[1:0]$7133 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $0\o$20$next[63:0]$7080 + attribute \src "libresoc.v:146333.3-146334.27" + wire width 64 $0\o$20[63:0]$6987 + attribute \src "libresoc.v:146016.14-146016.43" + wire width 64 $0\o$20[63:0]$7135 + attribute \src "libresoc.v:146506.3-146524.6" + wire $0\o_ok$21$next[0:0]$7081 + attribute \src "libresoc.v:146335.3-146336.33" + wire $0\o_ok$21[0:0]$6989 + attribute \src "libresoc.v:146025.7-146025.23" + wire $0\o_ok$21[0:0]$7137 + attribute \src "libresoc.v:146433.3-146450.6" + wire $0\r_busy$next[0:0]$7030 + attribute \src "libresoc.v:146375.3-146376.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:144893.3-144911.6" - wire width 4 $1\cr_a$22$next[3:0]$7040 - attribute \src "libresoc.v:144893.3-144911.6" - wire $1\cr_a_ok$23$next[0:0]$7041 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$7007 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7008 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7009 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$7010 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$7011 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$7012 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$7013 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__invert_in$10$next[0:0]$7014 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__invert_out$13$next[0:0]$7015 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__is_32bit$16$next[0:0]$7016 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__is_signed$17$next[0:0]$7017 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__oe__oe$8$next[0:0]$7018 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__oe__ok$9$next[0:0]$7019 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__output_carry$15$next[0:0]$7020 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__rc__ok$7$next[0:0]$7021 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__rc__rc$6$next[0:0]$7022 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__write_cr0$14$next[0:0]$7023 - attribute \src "libresoc.v:144832.3-144873.6" - wire $1\logical_op__zero_a$11$next[0:0]$7024 - attribute \src "libresoc.v:144819.3-144831.6" - wire width 2 $1\muxid$1$next[1:0]$6987 - attribute \src "libresoc.v:144874.3-144892.6" - wire width 64 $1\o$20$next[63:0]$7034 - attribute \src "libresoc.v:144874.3-144892.6" - wire $1\o_ok$21$next[0:0]$7035 - attribute \src "libresoc.v:144801.3-144818.6" - wire $1\r_busy$next[0:0]$6983 - attribute \src "libresoc.v:144687.7-144687.20" + attribute \src "libresoc.v:146525.3-146543.6" + wire width 4 $1\cr_a$22$next[3:0]$7088 + attribute \src "libresoc.v:146525.3-146543.6" + wire $1\cr_a_ok$23$next[0:0]$7089 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7060 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_in$10$next[0:0]$7062 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__invert_out$13$next[0:0]$7063 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7064 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__is_signed$17$next[0:0]$7065 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7066 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7067 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__output_carry$15$next[0:0]$7068 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7069 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7070 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7071 + attribute \src "libresoc.v:146464.3-146505.6" + wire $1\logical_op__zero_a$11$next[0:0]$7072 + attribute \src "libresoc.v:146451.3-146463.6" + wire width 2 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146506.3-146524.6" + wire width 64 $1\o$20$next[63:0]$7082 + attribute \src "libresoc.v:146506.3-146524.6" + wire $1\o_ok$21$next[0:0]$7083 + attribute \src "libresoc.v:146433.3-146450.6" + wire $1\r_busy$next[0:0]$7031 + attribute \src "libresoc.v:146319.7-146319.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:144893.3-144911.6" - wire $2\cr_a_ok$23$next[0:0]$7042 - attribute \src "libresoc.v:144832.3-144873.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7025 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$7026 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__oe__oe$8$next[0:0]$7027 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__oe__ok$9$next[0:0]$7028 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__rc__ok$7$next[0:0]$7029 - attribute \src "libresoc.v:144832.3-144873.6" - wire $2\logical_op__rc__rc$6$next[0:0]$7030 - attribute \src "libresoc.v:144874.3-144892.6" - wire $2\o_ok$21$next[0:0]$7036 - attribute \src "libresoc.v:144801.3-144818.6" - wire $2\r_busy$next[0:0]$6984 - attribute \src "libresoc.v:144696.18-144696.118" - wire $and$libresoc.v:144696$6933_Y + attribute \src "libresoc.v:146525.3-146543.6" + wire $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146464.3-146505.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7075 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7076 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7077 + attribute \src "libresoc.v:146464.3-146505.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146506.3-146524.6" + wire $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146433.3-146450.6" + wire $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146328.18-146328.118" + wire $and$libresoc.v:146328$6981_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -235024,7 +237521,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:143894.7-143894.15" + attribute \src "libresoc.v:145526.7-145526.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -235781,7 +238278,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:144696$6933 + cell $and $and$libresoc.v:146328$6981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235789,16 +238286,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:144696$6933_Y + connect \Y $and$libresoc.v:146328$6981_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:144745.10-144748.4" + attribute \src "libresoc.v:146377.10-146380.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:144749.15-144796.4" + attribute \src "libresoc.v:146381.15-146428.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -235848,388 +238345,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:144797.10-144800.4" + attribute \src "libresoc.v:146429.10-146432.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:143894.7-143894.20" - process $proc$libresoc.v:143894$7043 + attribute \src "libresoc.v:145526.7-145526.20" + process $proc$libresoc.v:145526$7091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143905.13-143905.29" - process $proc$libresoc.v:143905$7044 + attribute \src "libresoc.v:145537.13-145537.29" + process $proc$libresoc.v:145537$7092 assign { } { } - assign $0\cr_a$22[3:0]$7045 4'0000 + assign $0\cr_a$22[3:0]$7093 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$7045 + update \cr_a$22 $0\cr_a$22[3:0]$7093 end - attribute \src "libresoc.v:143914.7-143914.26" - process $proc$libresoc.v:143914$7046 + attribute \src "libresoc.v:145546.7-145546.26" + process $proc$libresoc.v:145546$7094 assign { } { } - assign $0\cr_a_ok$23[0:0]$7047 1'0 + assign $0\cr_a_ok$23[0:0]$7095 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7047 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 end - attribute \src "libresoc.v:143925.13-143925.45" - process $proc$libresoc.v:143925$7048 + attribute \src "libresoc.v:145557.13-145557.45" + process $proc$libresoc.v:145557$7096 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7049 4'0000 + assign $0\logical_op__data_len$18[3:0]$7097 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7049 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 end - attribute \src "libresoc.v:143964.14-143964.48" - process $proc$libresoc.v:143964$7050 + attribute \src "libresoc.v:145596.14-145596.48" + process $proc$libresoc.v:145596$7098 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$7051 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7051 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 end - attribute \src "libresoc.v:143988.14-143988.67" - process $proc$libresoc.v:143988$7052 + attribute \src "libresoc.v:145620.14-145620.67" + process $proc$libresoc.v:145620$7100 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7053 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7053 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 end - attribute \src "libresoc.v:143997.7-143997.42" - process $proc$libresoc.v:143997$7054 + attribute \src "libresoc.v:145629.7-145629.42" + process $proc$libresoc.v:145629$7102 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7055 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7055 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 end - attribute \src "libresoc.v:144014.13-144014.48" - process $proc$libresoc.v:144014$7056 + attribute \src "libresoc.v:145646.13-145646.48" + process $proc$libresoc.v:145646$7104 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7057 2'00 + assign $0\logical_op__input_carry$12[1:0]$7105 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7057 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 end - attribute \src "libresoc.v:144027.14-144027.43" - process $proc$libresoc.v:144027$7058 + attribute \src "libresoc.v:145659.14-145659.43" + process $proc$libresoc.v:145659$7106 assign { } { } - assign $0\logical_op__insn$19[31:0]$7059 0 + assign $0\logical_op__insn$19[31:0]$7107 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7059 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 end - attribute \src "libresoc.v:144186.13-144186.46" - process $proc$libresoc.v:144186$7060 + attribute \src "libresoc.v:145818.13-145818.46" + process $proc$libresoc.v:145818$7108 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7061 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7061 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 end - attribute \src "libresoc.v:144270.7-144270.40" - process $proc$libresoc.v:144270$7062 + attribute \src "libresoc.v:145902.7-145902.40" + process $proc$libresoc.v:145902$7110 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7063 1'0 + assign $0\logical_op__invert_in$10[0:0]$7111 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7063 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 end - attribute \src "libresoc.v:144279.7-144279.41" - process $proc$libresoc.v:144279$7064 + attribute \src "libresoc.v:145911.7-145911.41" + process $proc$libresoc.v:145911$7112 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7065 1'0 + assign $0\logical_op__invert_out$13[0:0]$7113 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7065 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 end - attribute \src "libresoc.v:144288.7-144288.39" - process $proc$libresoc.v:144288$7066 + attribute \src "libresoc.v:145920.7-145920.39" + process $proc$libresoc.v:145920$7114 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7067 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7067 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 end - attribute \src "libresoc.v:144297.7-144297.40" - process $proc$libresoc.v:144297$7068 + attribute \src "libresoc.v:145929.7-145929.40" + process $proc$libresoc.v:145929$7116 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7069 1'0 + assign $0\logical_op__is_signed$17[0:0]$7117 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7069 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 end - attribute \src "libresoc.v:144308.7-144308.36" - process $proc$libresoc.v:144308$7070 + attribute \src "libresoc.v:145940.7-145940.36" + process $proc$libresoc.v:145940$7118 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7071 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7071 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 end - attribute \src "libresoc.v:144317.7-144317.36" - process $proc$libresoc.v:144317$7072 + attribute \src "libresoc.v:145949.7-145949.36" + process $proc$libresoc.v:145949$7120 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7073 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7073 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 end - attribute \src "libresoc.v:144324.7-144324.43" - process $proc$libresoc.v:144324$7074 + attribute \src "libresoc.v:145956.7-145956.43" + process $proc$libresoc.v:145956$7122 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7075 1'0 + assign $0\logical_op__output_carry$15[0:0]$7123 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7075 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 end - attribute \src "libresoc.v:144335.7-144335.36" - process $proc$libresoc.v:144335$7076 + attribute \src "libresoc.v:145967.7-145967.36" + process $proc$libresoc.v:145967$7124 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7077 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7077 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 end - attribute \src "libresoc.v:144344.7-144344.36" - process $proc$libresoc.v:144344$7078 + attribute \src "libresoc.v:145976.7-145976.36" + process $proc$libresoc.v:145976$7126 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7079 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7079 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 end - attribute \src "libresoc.v:144351.7-144351.40" - process $proc$libresoc.v:144351$7080 + attribute \src "libresoc.v:145983.7-145983.40" + process $proc$libresoc.v:145983$7128 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7081 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7081 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 end - attribute \src "libresoc.v:144360.7-144360.37" - process $proc$libresoc.v:144360$7082 + attribute \src "libresoc.v:145992.7-145992.37" + process $proc$libresoc.v:145992$7130 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7083 1'0 + assign $0\logical_op__zero_a$11[0:0]$7131 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7083 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 end - attribute \src "libresoc.v:144369.13-144369.29" - process $proc$libresoc.v:144369$7084 + attribute \src "libresoc.v:146001.13-146001.29" + process $proc$libresoc.v:146001$7132 assign { } { } - assign $0\muxid$1[1:0]$7085 2'00 + assign $0\muxid$1[1:0]$7133 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7085 + update \muxid$1 $0\muxid$1[1:0]$7133 end - attribute \src "libresoc.v:144384.14-144384.43" - process $proc$libresoc.v:144384$7086 + attribute \src "libresoc.v:146016.14-146016.43" + process $proc$libresoc.v:146016$7134 assign { } { } - assign $0\o$20[63:0]$7087 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$7087 + update \o$20 $0\o$20[63:0]$7135 end - attribute \src "libresoc.v:144393.7-144393.23" - process $proc$libresoc.v:144393$7088 + attribute \src "libresoc.v:146025.7-146025.23" + process $proc$libresoc.v:146025$7136 assign { } { } - assign $0\o_ok$21[0:0]$7089 1'0 + assign $0\o_ok$21[0:0]$7137 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$7089 + update \o_ok$21 $0\o_ok$21[0:0]$7137 end - attribute \src "libresoc.v:144687.7-144687.20" - process $proc$libresoc.v:144687$7090 + attribute \src "libresoc.v:146319.7-146319.20" + process $proc$libresoc.v:146319$7138 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:144697.3-144698.33" - process $proc$libresoc.v:144697$6934 + attribute \src "libresoc.v:146329.3-146330.33" + process $proc$libresoc.v:146329$6982 assign { } { } - assign $0\cr_a$22[3:0]$6935 \cr_a$22$next + assign $0\cr_a$22[3:0]$6983 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6935 + update \cr_a$22 $0\cr_a$22[3:0]$6983 end - attribute \src "libresoc.v:144699.3-144700.39" - process $proc$libresoc.v:144699$6936 + attribute \src "libresoc.v:146331.3-146332.39" + process $proc$libresoc.v:146331$6984 assign { } { } - assign $0\cr_a_ok$23[0:0]$6937 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6937 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 end - attribute \src "libresoc.v:144701.3-144702.27" - process $proc$libresoc.v:144701$6938 + attribute \src "libresoc.v:146333.3-146334.27" + process $proc$libresoc.v:146333$6986 assign { } { } - assign $0\o$20[63:0]$6939 \o$20$next + assign $0\o$20[63:0]$6987 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6939 + update \o$20 $0\o$20[63:0]$6987 end - attribute \src "libresoc.v:144703.3-144704.33" - process $proc$libresoc.v:144703$6940 + attribute \src "libresoc.v:146335.3-146336.33" + process $proc$libresoc.v:146335$6988 assign { } { } - assign $0\o_ok$21[0:0]$6941 \o_ok$21$next + assign $0\o_ok$21[0:0]$6989 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6941 + update \o_ok$21 $0\o_ok$21[0:0]$6989 end - attribute \src "libresoc.v:144705.3-144706.65" - process $proc$libresoc.v:144705$6942 + attribute \src "libresoc.v:146337.3-146338.65" + process $proc$libresoc.v:146337$6990 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6943 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6943 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 end - attribute \src "libresoc.v:144707.3-144708.61" - process $proc$libresoc.v:144707$6944 + attribute \src "libresoc.v:146339.3-146340.61" + process $proc$libresoc.v:146339$6992 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$6945 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6945 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 end - attribute \src "libresoc.v:144709.3-144710.75" - process $proc$libresoc.v:144709$6946 + attribute \src "libresoc.v:146341.3-146342.75" + process $proc$libresoc.v:146341$6994 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6947 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6947 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 end - attribute \src "libresoc.v:144711.3-144712.71" - process $proc$libresoc.v:144711$6948 + attribute \src "libresoc.v:146343.3-146344.71" + process $proc$libresoc.v:146343$6996 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6949 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6949 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 end - attribute \src "libresoc.v:144713.3-144714.59" - process $proc$libresoc.v:144713$6950 + attribute \src "libresoc.v:146345.3-146346.59" + process $proc$libresoc.v:146345$6998 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6951 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6951 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 end - attribute \src "libresoc.v:144715.3-144716.59" - process $proc$libresoc.v:144715$6952 + attribute \src "libresoc.v:146347.3-146348.59" + process $proc$libresoc.v:146347$7000 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6953 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6953 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 end - attribute \src "libresoc.v:144717.3-144718.59" - process $proc$libresoc.v:144717$6954 + attribute \src "libresoc.v:146349.3-146350.59" + process $proc$libresoc.v:146349$7002 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6955 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6955 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 end - attribute \src "libresoc.v:144719.3-144720.59" - process $proc$libresoc.v:144719$6956 + attribute \src "libresoc.v:146351.3-146352.59" + process $proc$libresoc.v:146351$7004 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6957 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6957 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 end - attribute \src "libresoc.v:144721.3-144722.67" - process $proc$libresoc.v:144721$6958 + attribute \src "libresoc.v:146353.3-146354.67" + process $proc$libresoc.v:146353$7006 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6959 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6959 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 end - attribute \src "libresoc.v:144723.3-144724.61" - process $proc$libresoc.v:144723$6960 + attribute \src "libresoc.v:146355.3-146356.61" + process $proc$libresoc.v:146355$7008 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6961 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6961 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 end - attribute \src "libresoc.v:144725.3-144726.71" - process $proc$libresoc.v:144725$6962 + attribute \src "libresoc.v:146357.3-146358.71" + process $proc$libresoc.v:146357$7010 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6963 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6963 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 end - attribute \src "libresoc.v:144727.3-144728.69" - process $proc$libresoc.v:144727$6964 + attribute \src "libresoc.v:146359.3-146360.69" + process $proc$libresoc.v:146359$7012 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6965 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6965 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 end - attribute \src "libresoc.v:144729.3-144730.67" - process $proc$libresoc.v:144729$6966 + attribute \src "libresoc.v:146361.3-146362.67" + process $proc$libresoc.v:146361$7014 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6967 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6967 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 end - attribute \src "libresoc.v:144731.3-144732.73" - process $proc$libresoc.v:144731$6968 + attribute \src "libresoc.v:146363.3-146364.73" + process $proc$libresoc.v:146363$7016 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6969 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6969 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 end - attribute \src "libresoc.v:144733.3-144734.65" - process $proc$libresoc.v:144733$6970 + attribute \src "libresoc.v:146365.3-146366.65" + process $proc$libresoc.v:146365$7018 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6971 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6971 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 end - attribute \src "libresoc.v:144735.3-144736.67" - process $proc$libresoc.v:144735$6972 + attribute \src "libresoc.v:146367.3-146368.67" + process $proc$libresoc.v:146367$7020 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6973 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6973 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 end - attribute \src "libresoc.v:144737.3-144738.65" - process $proc$libresoc.v:144737$6974 + attribute \src "libresoc.v:146369.3-146370.65" + process $proc$libresoc.v:146369$7022 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6975 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6975 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 end - attribute \src "libresoc.v:144739.3-144740.57" - process $proc$libresoc.v:144739$6976 + attribute \src "libresoc.v:146371.3-146372.57" + process $proc$libresoc.v:146371$7024 assign { } { } - assign $0\logical_op__insn$19[31:0]$6977 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6977 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 end - attribute \src "libresoc.v:144741.3-144742.33" - process $proc$libresoc.v:144741$6978 + attribute \src "libresoc.v:146373.3-146374.33" + process $proc$libresoc.v:146373$7026 assign { } { } - assign $0\muxid$1[1:0]$6979 \muxid$1$next + assign $0\muxid$1[1:0]$7027 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6979 + update \muxid$1 $0\muxid$1[1:0]$7027 end - attribute \src "libresoc.v:144743.3-144744.29" - process $proc$libresoc.v:144743$6980 + attribute \src "libresoc.v:146375.3-146376.29" + process $proc$libresoc.v:146375$7028 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:144801.3-144818.6" - process $proc$libresoc.v:144801$6981 + attribute \src "libresoc.v:146433.3-146450.6" + process $proc$libresoc.v:146433$7029 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6982 $2\r_busy$next[0:0]$6984 - attribute \src "libresoc.v:144802.5-144802.29" + assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 + attribute \src "libresoc.v:146434.5-146434.29" switch \initial - attribute \src "libresoc.v:144802.9-144802.17" + attribute \src "libresoc.v:146434.9-146434.17" case 1'1 case end @@ -236238,34 +238735,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6983 1'1 + assign $1\r_busy$next[0:0]$7031 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6983 1'0 + assign $1\r_busy$next[0:0]$7031 1'0 case - assign $1\r_busy$next[0:0]$6983 \r_busy + assign $1\r_busy$next[0:0]$7031 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6984 1'0 + assign $2\r_busy$next[0:0]$7032 1'0 case - assign $2\r_busy$next[0:0]$6984 $1\r_busy$next[0:0]$6983 + assign $2\r_busy$next[0:0]$7032 $1\r_busy$next[0:0]$7031 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6982 + update \r_busy$next $0\r_busy$next[0:0]$7030 end - attribute \src "libresoc.v:144819.3-144831.6" - process $proc$libresoc.v:144819$6985 + attribute \src "libresoc.v:146451.3-146463.6" + process $proc$libresoc.v:146451$7033 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$6986 $1\muxid$1$next[1:0]$6987 - attribute \src "libresoc.v:144820.5-144820.29" + assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 + attribute \src "libresoc.v:146452.5-146452.29" switch \initial - attribute \src "libresoc.v:144820.9-144820.17" + attribute \src "libresoc.v:146452.9-146452.17" case 1'1 case end @@ -236274,19 +238771,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$6987 \muxid$51 + assign $1\muxid$1$next[1:0]$7035 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$6987 \muxid$51 + assign $1\muxid$1$next[1:0]$7035 \muxid$51 case - assign $1\muxid$1$next[1:0]$6987 \muxid$1 + assign $1\muxid$1$next[1:0]$7035 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6986 + update \muxid$1$next $0\muxid$1$next[1:0]$7034 end - attribute \src "libresoc.v:144832.3-144873.6" - process $proc$libresoc.v:144832$6988 + attribute \src "libresoc.v:146464.3-146505.6" + process $proc$libresoc.v:146464$7036 assign { } { } assign { } { } assign { } { } @@ -236323,33 +238820,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6989 $1\logical_op__data_len$18$next[3:0]$7007 - assign $0\logical_op__fn_unit$3$next[13:0]$6990 $1\logical_op__fn_unit$3$next[13:0]$7008 + assign $0\logical_op__data_len$18$next[3:0]$7037 $1\logical_op__data_len$18$next[3:0]$7055 + assign $0\logical_op__fn_unit$3$next[13:0]$7038 $1\logical_op__fn_unit$3$next[13:0]$7056 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6993 $1\logical_op__input_carry$12$next[1:0]$7011 - assign $0\logical_op__insn$19$next[31:0]$6994 $1\logical_op__insn$19$next[31:0]$7012 - assign $0\logical_op__insn_type$2$next[6:0]$6995 $1\logical_op__insn_type$2$next[6:0]$7013 - assign $0\logical_op__invert_in$10$next[0:0]$6996 $1\logical_op__invert_in$10$next[0:0]$7014 - assign $0\logical_op__invert_out$13$next[0:0]$6997 $1\logical_op__invert_out$13$next[0:0]$7015 - assign $0\logical_op__is_32bit$16$next[0:0]$6998 $1\logical_op__is_32bit$16$next[0:0]$7016 - assign $0\logical_op__is_signed$17$next[0:0]$6999 $1\logical_op__is_signed$17$next[0:0]$7017 + assign $0\logical_op__input_carry$12$next[1:0]$7041 $1\logical_op__input_carry$12$next[1:0]$7059 + assign $0\logical_op__insn$19$next[31:0]$7042 $1\logical_op__insn$19$next[31:0]$7060 + assign $0\logical_op__insn_type$2$next[6:0]$7043 $1\logical_op__insn_type$2$next[6:0]$7061 + assign $0\logical_op__invert_in$10$next[0:0]$7044 $1\logical_op__invert_in$10$next[0:0]$7062 + assign $0\logical_op__invert_out$13$next[0:0]$7045 $1\logical_op__invert_out$13$next[0:0]$7063 + assign $0\logical_op__is_32bit$16$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7064 + assign $0\logical_op__is_signed$17$next[0:0]$7047 $1\logical_op__is_signed$17$next[0:0]$7065 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$7002 $1\logical_op__output_carry$15$next[0:0]$7020 + assign $0\logical_op__output_carry$15$next[0:0]$7050 $1\logical_op__output_carry$15$next[0:0]$7068 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$7005 $1\logical_op__write_cr0$14$next[0:0]$7023 - assign $0\logical_op__zero_a$11$next[0:0]$7006 $1\logical_op__zero_a$11$next[0:0]$7024 - assign $0\logical_op__imm_data__data$4$next[63:0]$6991 $2\logical_op__imm_data__data$4$next[63:0]$7025 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6992 $2\logical_op__imm_data__ok$5$next[0:0]$7026 - assign $0\logical_op__oe__oe$8$next[0:0]$7000 $2\logical_op__oe__oe$8$next[0:0]$7027 - assign $0\logical_op__oe__ok$9$next[0:0]$7001 $2\logical_op__oe__ok$9$next[0:0]$7028 - assign $0\logical_op__rc__ok$7$next[0:0]$7003 $2\logical_op__rc__ok$7$next[0:0]$7029 - assign $0\logical_op__rc__rc$6$next[0:0]$7004 $2\logical_op__rc__rc$6$next[0:0]$7030 - attribute \src "libresoc.v:144833.5-144833.29" + assign $0\logical_op__write_cr0$14$next[0:0]$7053 $1\logical_op__write_cr0$14$next[0:0]$7071 + assign $0\logical_op__zero_a$11$next[0:0]$7054 $1\logical_op__zero_a$11$next[0:0]$7072 + assign $0\logical_op__imm_data__data$4$next[63:0]$7039 $2\logical_op__imm_data__data$4$next[63:0]$7073 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7040 $2\logical_op__imm_data__ok$5$next[0:0]$7074 + assign $0\logical_op__oe__oe$8$next[0:0]$7048 $2\logical_op__oe__oe$8$next[0:0]$7075 + assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 + assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 + assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 + attribute \src "libresoc.v:146465.5-146465.29" switch \initial - attribute \src "libresoc.v:144833.9-144833.17" + attribute \src "libresoc.v:146465.9-146465.17" case 1'1 case end @@ -236375,7 +238872,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -236396,26 +238893,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7012 $1\logical_op__data_len$18$next[3:0]$7007 $1\logical_op__is_signed$17$next[0:0]$7017 $1\logical_op__is_32bit$16$next[0:0]$7016 $1\logical_op__output_carry$15$next[0:0]$7020 $1\logical_op__write_cr0$14$next[0:0]$7023 $1\logical_op__invert_out$13$next[0:0]$7015 $1\logical_op__input_carry$12$next[1:0]$7011 $1\logical_op__zero_a$11$next[0:0]$7024 $1\logical_op__invert_in$10$next[0:0]$7014 $1\logical_op__oe__ok$9$next[0:0]$7019 $1\logical_op__oe__oe$8$next[0:0]$7018 $1\logical_op__rc__ok$7$next[0:0]$7021 $1\logical_op__rc__rc$6$next[0:0]$7022 $1\logical_op__imm_data__ok$5$next[0:0]$7010 $1\logical_op__imm_data__data$4$next[63:0]$7009 $1\logical_op__fn_unit$3$next[13:0]$7008 $1\logical_op__insn_type$2$next[6:0]$7013 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$7007 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$7008 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$7009 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$7010 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$7011 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$7012 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$7013 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$7014 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$7015 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$7016 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$7017 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$7018 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$7019 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$7020 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$7021 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$7022 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$7023 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$7024 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$7055 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7056 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7057 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7058 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7059 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7060 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7061 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7062 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7063 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7064 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7065 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7066 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7067 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7068 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7069 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7070 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7071 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7072 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -236427,52 +238924,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$7025 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$7030 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$7029 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$7027 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$7028 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$7025 $1\logical_op__imm_data__data$4$next[63:0]$7009 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7026 $1\logical_op__imm_data__ok$5$next[0:0]$7010 - assign $2\logical_op__oe__oe$8$next[0:0]$7027 $1\logical_op__oe__oe$8$next[0:0]$7018 - assign $2\logical_op__oe__ok$9$next[0:0]$7028 $1\logical_op__oe__ok$9$next[0:0]$7019 - assign $2\logical_op__rc__ok$7$next[0:0]$7029 $1\logical_op__rc__ok$7$next[0:0]$7021 - assign $2\logical_op__rc__rc$6$next[0:0]$7030 $1\logical_op__rc__rc$6$next[0:0]$7022 + assign $2\logical_op__imm_data__data$4$next[63:0]$7073 $1\logical_op__imm_data__data$4$next[63:0]$7057 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 $1\logical_op__imm_data__ok$5$next[0:0]$7058 + assign $2\logical_op__oe__oe$8$next[0:0]$7075 $1\logical_op__oe__oe$8$next[0:0]$7066 + assign $2\logical_op__oe__ok$9$next[0:0]$7076 $1\logical_op__oe__ok$9$next[0:0]$7067 + assign $2\logical_op__rc__ok$7$next[0:0]$7077 $1\logical_op__rc__ok$7$next[0:0]$7069 + assign $2\logical_op__rc__rc$6$next[0:0]$7078 $1\logical_op__rc__rc$6$next[0:0]$7070 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6989 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6990 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6991 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6992 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6993 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6994 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6995 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6996 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6997 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6998 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6999 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7000 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7001 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7002 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7003 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7004 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7005 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7006 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7037 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7038 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7039 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7040 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7041 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7042 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7043 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7044 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7045 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7046 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7047 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7048 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7049 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7050 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7051 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7052 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 end - attribute \src "libresoc.v:144874.3-144892.6" - process $proc$libresoc.v:144874$7031 + attribute \src "libresoc.v:146506.3-146524.6" + process $proc$libresoc.v:146506$7079 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$7032 $1\o$20$next[63:0]$7034 + assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 assign { } { } - assign $0\o_ok$21$next[0:0]$7033 $2\o_ok$21$next[0:0]$7036 - attribute \src "libresoc.v:144875.5-144875.29" + assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 + attribute \src "libresoc.v:146507.5-146507.29" switch \initial - attribute \src "libresoc.v:144875.9-144875.17" + attribute \src "libresoc.v:146507.9-146507.17" case 1'1 case end @@ -236482,41 +238979,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7035 $1\o$20$next[63:0]$7034 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$7034 \o$20 - assign $1\o_ok$21$next[0:0]$7035 \o_ok$21 + assign $1\o$20$next[63:0]$7082 \o$20 + assign $1\o_ok$21$next[0:0]$7083 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$7036 1'0 + assign $2\o_ok$21$next[0:0]$7084 1'0 case - assign $2\o_ok$21$next[0:0]$7036 $1\o_ok$21$next[0:0]$7035 + assign $2\o_ok$21$next[0:0]$7084 $1\o_ok$21$next[0:0]$7083 end sync always - update \o$20$next $0\o$20$next[63:0]$7032 - update \o_ok$21$next $0\o_ok$21$next[0:0]$7033 + update \o$20$next $0\o$20$next[63:0]$7080 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 end - attribute \src "libresoc.v:144893.3-144911.6" - process $proc$libresoc.v:144893$7037 + attribute \src "libresoc.v:146525.3-146543.6" + process $proc$libresoc.v:146525$7085 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$7038 $1\cr_a$22$next[3:0]$7040 + assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$7039 $2\cr_a_ok$23$next[0:0]$7042 - attribute \src "libresoc.v:144894.5-144894.29" + assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 + attribute \src "libresoc.v:146526.5-146526.29" switch \initial - attribute \src "libresoc.v:144894.9-144894.17" + attribute \src "libresoc.v:146526.9-146526.17" case 1'1 case end @@ -236526,30 +239023,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7041 $1\cr_a$22$next[3:0]$7040 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$7040 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$7041 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7088 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7089 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$7042 1'0 + assign $2\cr_a_ok$23$next[0:0]$7090 1'0 case - assign $2\cr_a_ok$23$next[0:0]$7042 $1\cr_a_ok$23$next[0:0]$7041 + assign $2\cr_a_ok$23$next[0:0]$7090 $1\cr_a_ok$23$next[0:0]$7089 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$7038 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7039 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 end - connect \$49 $and$libresoc.v:144696$6933_Y + connect \$49 $and$libresoc.v:146328$6981_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -237334,15 +239831,15 @@ module \ls180 wire $0\main_libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:7705.1-10349.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:182.12-182.74" + attribute \src "ls180.v:204.12-204.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:179.5-179.69" + attribute \src "ls180.v:176.5-176.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:172.5-172.72" + attribute \src "ls180.v:181.5-181.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:175.11-175.79" + attribute \src "ls180.v:184.11-184.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:195.12-195.78" + attribute \src "ls180.v:188.12-188.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -248066,24 +250563,24 @@ module \ls180 wire \builder_sync_rhs_array_muxed6 attribute \src "ls180.v:2014.6-2014.18" wire \builder_wait - attribute \src "ls180.v:42.19-42.23" - wire width 3 input 38 \eint - attribute \src "ls180.v:206.12-206.18" + attribute \src "ls180.v:13.19-13.23" + wire width 3 input 9 \eint + attribute \src "ls180.v:179.12-179.18" wire width 3 \eint_1 - attribute \src "ls180.v:18.21-18.27" - wire width 16 output 14 \gpio_i - attribute \src "ls180.v:19.20-19.26" - wire width 16 output 15 \gpio_o - attribute \src "ls180.v:20.20-20.27" - wire width 16 output 16 \gpio_oe - attribute \src "ls180.v:14.14-14.21" - wire output 10 \i2c_scl - attribute \src "ls180.v:15.14-15.23" - wire output 11 \i2c_sda_i - attribute \src "ls180.v:16.14-16.23" - wire output 12 \i2c_sda_o - attribute \src "ls180.v:17.14-17.24" - wire output 13 \i2c_sda_oe + attribute \src "ls180.v:40.21-40.27" + wire width 16 output 36 \gpio_i + attribute \src "ls180.v:41.20-41.26" + wire width 16 output 37 \gpio_o + attribute \src "ls180.v:42.20-42.27" + wire width 16 output 38 \gpio_oe + attribute \src "ls180.v:9.14-9.21" + wire output 5 \i2c_scl + attribute \src "ls180.v:10.14-10.23" + wire output 6 \i2c_sda_i + attribute \src "ls180.v:11.14-11.23" + wire output 7 \i2c_sda_o + attribute \src "ls180.v:12.14-12.24" + wire output 8 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -248442,71 +250939,71 @@ module \ls180 wire width 64 \main_libresocsim_libresoc2 attribute \src "ls180.v:169.12-169.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:182.12-182.66" + attribute \src "ls180.v:204.12-204.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:183.13-183.67" + attribute \src "ls180.v:205.13-205.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:184.13-184.68" + attribute \src "ls180.v:206.13-206.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:178.6-178.61" + attribute \src "ls180.v:175.6-175.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:179.5-179.62" + attribute \src "ls180.v:176.5-176.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:180.6-180.63" + attribute \src "ls180.v:177.6-177.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:181.6-181.64" + attribute \src "ls180.v:178.6-178.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:171.6-171.64" + attribute \src "ls180.v:180.6-180.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:172.5-172.65" + attribute \src "ls180.v:181.5-181.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:173.6-173.66" + attribute \src "ls180.v:182.6-182.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:174.6-174.67" + attribute \src "ls180.v:183.6-183.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:175.11-175.72" + attribute \src "ls180.v:184.11-184.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:176.12-176.73" + attribute \src "ls180.v:185.12-185.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:177.6-177.68" + attribute \src "ls180.v:186.6-186.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:194.13-194.68" + attribute \src "ls180.v:187.13-187.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:203.12-203.68" + attribute \src "ls180.v:196.12-196.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:200.6-200.65" + attribute \src "ls180.v:193.6-193.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:202.6-202.63" + attribute \src "ls180.v:195.6-195.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:201.6-201.64" + attribute \src "ls180.v:194.6-194.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:204.12-204.68" + attribute \src "ls180.v:197.12-197.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:195.12-195.70" + attribute \src "ls180.v:188.12-188.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:196.13-196.71" + attribute \src "ls180.v:189.13-189.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:197.6-197.65" + attribute \src "ls180.v:190.6-190.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:199.6-199.65" + attribute \src "ls180.v:192.6-192.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:198.6-198.64" + attribute \src "ls180.v:191.6-191.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:185.6-185.67" + attribute \src "ls180.v:171.6-171.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:187.6-187.68" + attribute \src "ls180.v:173.6-173.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:188.6-188.68" + attribute \src "ls180.v:174.6-174.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:186.6-186.68" + attribute \src "ls180.v:172.6-172.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:189.6-189.67" + attribute \src "ls180.v:199.6-199.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:191.6-191.68" + attribute \src "ls180.v:201.6-201.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:192.6-192.68" + attribute \src "ls180.v:202.6-202.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:190.6-190.68" + attribute \src "ls180.v:200.6-200.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -251836,50 +254333,50 @@ module \ls180 wire width 24 input 48 \nc attribute \src "ls180.v:341.6-341.13" wire \por_clk - attribute \src "ls180.v:29.19-29.22" - wire width 2 output 25 \pwm - attribute \src "ls180.v:193.12-193.17" + attribute \src "ls180.v:39.19-39.22" + wire width 2 output 35 \pwm + attribute \src "ls180.v:203.12-203.17" wire width 2 \pwm_1 - attribute \src "ls180.v:5.13-5.23" - wire output 1 \sdcard_clk - attribute \src "ls180.v:6.14-6.26" - wire output 2 \sdcard_cmd_i - attribute \src "ls180.v:7.13-7.25" - wire output 3 \sdcard_cmd_o - attribute \src "ls180.v:8.13-8.26" - wire output 4 \sdcard_cmd_oe - attribute \src "ls180.v:9.20-9.33" - wire width 4 output 5 \sdcard_data_i - attribute \src "ls180.v:10.19-10.32" - wire width 4 output 6 \sdcard_data_o - attribute \src "ls180.v:11.13-11.27" - wire output 7 \sdcard_data_oe - attribute \src "ls180.v:30.20-30.27" - wire width 13 output 26 \sdram_a - attribute \src "ls180.v:39.19-39.27" - wire width 2 output 35 \sdram_ba - attribute \src "ls180.v:36.13-36.24" - wire output 32 \sdram_cas_n - attribute \src "ls180.v:38.13-38.22" - wire output 34 \sdram_cke - attribute \src "ls180.v:41.13-41.24" - wire output 37 \sdram_clock - attribute \src "ls180.v:205.6-205.19" + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdcard_clk + attribute \src "ls180.v:15.14-15.26" + wire output 11 \sdcard_cmd_i + attribute \src "ls180.v:16.13-16.25" + wire output 12 \sdcard_cmd_o + attribute \src "ls180.v:17.13-17.26" + wire output 13 \sdcard_cmd_oe + attribute \src "ls180.v:18.20-18.33" + wire width 4 output 14 \sdcard_data_i + attribute \src "ls180.v:19.19-19.32" + wire width 4 output 15 \sdcard_data_o + attribute \src "ls180.v:20.13-20.27" + wire output 16 \sdcard_data_oe + attribute \src "ls180.v:21.20-21.27" + wire width 13 output 17 \sdram_a + attribute \src "ls180.v:30.19-30.27" + wire width 2 output 26 \sdram_ba + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_cas_n + attribute \src "ls180.v:29.13-29.22" + wire output 25 \sdram_cke + attribute \src "ls180.v:32.13-32.24" + wire output 28 \sdram_clock + attribute \src "ls180.v:198.6-198.19" wire \sdram_clock_1 - attribute \src "ls180.v:37.13-37.23" - wire output 33 \sdram_cs_n - attribute \src "ls180.v:40.19-40.27" - wire width 2 output 36 \sdram_dm - attribute \src "ls180.v:31.21-31.31" - wire width 16 output 27 \sdram_dq_i - attribute \src "ls180.v:32.20-32.30" - wire width 16 output 28 \sdram_dq_o - attribute \src "ls180.v:33.13-33.24" - wire output 29 \sdram_dq_oe - attribute \src "ls180.v:35.13-35.24" - wire output 31 \sdram_ras_n - attribute \src "ls180.v:34.13-34.23" - wire output 30 \sdram_we_n + attribute \src "ls180.v:28.13-28.23" + wire output 24 \sdram_cs_n + attribute \src "ls180.v:31.19-31.27" + wire width 2 output 27 \sdram_dm + attribute \src "ls180.v:22.21-22.31" + wire width 16 output 18 \sdram_dq_i + attribute \src "ls180.v:23.20-23.30" + wire width 16 output 19 \sdram_dq_o + attribute \src "ls180.v:24.13-24.24" + wire output 20 \sdram_dq_oe + attribute \src "ls180.v:26.13-26.24" + wire output 22 \sdram_ras_n + attribute \src "ls180.v:25.13-25.23" + wire output 21 \sdram_we_n attribute \src "ls180.v:2763.6-2763.15" wire \sdrio_clk attribute \src "ls180.v:2764.6-2764.17" @@ -252018,22 +254515,22 @@ module \ls180 wire \sdrio_clk_8 attribute \src "ls180.v:2772.6-2772.17" wire \sdrio_clk_9 - attribute \src "ls180.v:21.13-21.26" - wire output 17 \spimaster_clk - attribute \src "ls180.v:23.13-23.27" - wire output 19 \spimaster_cs_n - attribute \src "ls180.v:24.13-24.27" - wire input 20 \spimaster_miso - attribute \src "ls180.v:22.13-22.27" - wire output 18 \spimaster_mosi - attribute \src "ls180.v:25.13-25.26" - wire output 21 \spisdcard_clk - attribute \src "ls180.v:27.13-27.27" - wire output 23 \spisdcard_cs_n - attribute \src "ls180.v:28.13-28.27" - wire input 24 \spisdcard_miso - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spisdcard_mosi + attribute \src "ls180.v:5.13-5.26" + wire output 1 \spimaster_clk + attribute \src "ls180.v:7.13-7.27" + wire output 3 \spimaster_cs_n + attribute \src "ls180.v:8.13-8.27" + wire input 4 \spimaster_miso + attribute \src "ls180.v:6.13-6.27" + wire output 2 \spimaster_mosi + attribute \src "ls180.v:33.13-33.26" + wire output 29 \spisdcard_clk + attribute \src "ls180.v:35.13-35.27" + wire output 31 \spisdcard_cs_n + attribute \src "ls180.v:36.13-36.27" + wire input 32 \spisdcard_miso + attribute \src "ls180.v:34.13-34.27" + wire output 30 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk attribute \src "ls180.v:339.6-339.15" @@ -252048,10 +254545,10 @@ module \ls180 wire input 40 \sys_rst attribute \src "ls180.v:340.6-340.15" wire \sys_rst_1 - attribute \src "ls180.v:13.13-13.20" - wire input 9 \uart_rx - attribute \src "ls180.v:12.13-12.20" - wire output 8 \uart_tx + attribute \src "ls180.v:38.13-38.20" + wire input 34 \uart_rx + attribute \src "ls180.v:37.13-37.20" + wire output 33 \uart_tx attribute \src "ls180.v:10351.12-10351.15" memory width 64 size 64 \mem attribute \src "ls180.v:10379.12-10379.17" @@ -285618,14 +288115,6 @@ module \ls180 sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:172.5-172.72" - process $proc$ls180.v:172$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end attribute \src "ls180.v:1725.5-1725.45" process $proc$ls180.v:1725$3797 assign { } { } @@ -285754,14 +288243,6 @@ module \ls180 update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:175.11-175.79" - process $proc$ls180.v:175$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end attribute \src "ls180.v:1751.11-1751.41" process $proc$ls180.v:1751$3813 assign { } { } @@ -285810,6 +288291,14 @@ module \ls180 update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end + attribute \src "ls180.v:176.5-176.69" + process $proc$ls180.v:176$3150 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end attribute \src "ls180.v:1764.5-1764.43" process $proc$ls180.v:1764$3819 assign { } { } @@ -285962,14 +288451,6 @@ module \ls180 sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:179.5-179.69" - process $proc$ls180.v:179$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end attribute \src "ls180.v:1799.11-1799.64" process $proc$ls180.v:1799$3838 assign { } { } @@ -285986,12 +288467,12 @@ module \ls180 sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:182.12-182.74" - process $proc$ls180.v:182$3153 + attribute \src "ls180.v:181.5-181.72" + process $proc$ls180.v:181$3151 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init end attribute \src "ls180.v:1825.11-1825.45" @@ -286034,6 +288515,14 @@ module \ls180 sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end + attribute \src "ls180.v:184.11-184.79" + process $proc$ls180.v:184$3152 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end attribute \src "ls180.v:1842.5-1842.36" process $proc$ls180.v:1842$3845 assign { } { } @@ -286242,6 +288731,14 @@ module \ls180 update \builder_locked1 $0\builder_locked1[0:0] sync init end + attribute \src "ls180.v:188.12-188.78" + process $proc$ls180.v:188$3153 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end attribute \src "ls180.v:1880.5-1880.27" process $proc$ls180.v:1880$3871 assign { } { } @@ -286802,14 +289299,6 @@ module \ls180 sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:195.12-195.78" - process $proc$ls180.v:195$3154 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end attribute \src "ls180.v:1950.5-1950.59" process $proc$ls180.v:1950$3941 assign { } { } @@ -287186,6 +289675,14 @@ module \ls180 sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end + attribute \src "ls180.v:204.12-204.74" + process $proc$ls180.v:204$3154 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end attribute \src "ls180.v:2061.11-2061.51" process $proc$ls180.v:2061$3988 assign { } { } @@ -288370,16 +290867,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 assign $0\main_converter1_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state attribute \src "ls180.v:2978.2-3011.9" switch \builder_converter1_state @@ -288483,8 +290980,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 assign $0\main_wb_sdram_sel[3:0] 4'0000 assign $0\main_wb_sdram_cyc[0:0] 1'0 @@ -288492,7 +290990,6 @@ module \ls180 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state attribute \src "ls180.v:3038.2-3071.9" switch \builder_converter2_state @@ -288807,10 +291304,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 attribute \src "ls180.v:3254.2-3264.5" switch \main_sdram_command_issue_re attribute \src "ls180.v:3254.6-3254.33" @@ -288846,10 +291343,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign { } { } assign $0\builder_refresher_next_state[1:0] \builder_refresher_state attribute \src "ls180.v:3314.2-3337.9" switch \builder_refresher_state @@ -288998,6 +291495,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 @@ -289010,8 +291509,6 @@ module \ls180 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state attribute \src "ls180.v:3418.2-3494.9" switch \builder_bankmachine0_state @@ -289235,6 +291732,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 @@ -289247,8 +291746,6 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state attribute \src "ls180.v:3575.2-3651.9" switch \builder_bankmachine1_state @@ -289528,20 +292025,20 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state attribute \src "ls180.v:3732.2-3808.9" switch \builder_bankmachine2_state @@ -289773,20 +292270,20 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state attribute \src "ls180.v:3889.2-3965.9" switch \builder_bankmachine3_state @@ -290268,8 +292765,8 @@ module \ls180 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\main_sdram_en0[0:0] 1'0 assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed @@ -290414,8 +292911,8 @@ module \ls180 process $proc$ls180.v:4187$676 assign { } { } assign { } { } - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 attribute \src "ls180.v:4190.2-4199.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" @@ -290484,6 +292981,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign { } { } assign $0\main_litedram_wb_stb[0:0] 1'0 @@ -290493,7 +292991,6 @@ module \ls180 assign $0\main_converter_skip[0:0] 1'0 assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\builder_converter_next_state[0:0] \builder_converter_state attribute \src "ls180.v:4231.2-4264.9" switch \builder_converter_state @@ -290707,6 +293204,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spimaster25_clk_enable[0:0] 1'0 @@ -290715,7 +293213,6 @@ module \ls180 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 - assign { } { } assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state attribute \src "ls180.v:4431.2-4467.9" switch \builder_spimaster0_state @@ -290936,6 +293433,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 @@ -290943,7 +293441,6 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state attribute \src "ls180.v:4599.2-4621.9" switch \builder_sdphy_sdphyinit_state @@ -291203,6 +293700,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 @@ -291218,7 +293716,6 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:4751.2-4825.9" switch \builder_sdphy_sdphycmdr_state @@ -291442,12 +293939,12 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:4868.2-4886.9" switch \builder_sdphy_sdphycrcr_state @@ -291496,6 +293993,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 @@ -291504,7 +294002,6 @@ module \ls180 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state attribute \src "ls180.v:4899.2-4959.9" switch \builder_sdphy_fsm_state @@ -291686,21 +294183,21 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state attribute \src "ls180.v:5011.2-5094.9" switch \builder_sdphy_sdphydatar_state @@ -292053,21 +294550,21 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:5230.2-5291.9" switch \builder_sdcore_crcupstreaminserter_state @@ -292412,6 +294909,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 @@ -292450,7 +294948,6 @@ module \ls180 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state attribute \src "ls180.v:5436.2-5584.9" switch \builder_sdcore_fsm_state @@ -293018,13 +295515,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:5752.2-5778.9" switch \builder_sdmem2blockdma_resetinserter_state @@ -293176,6 +295673,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 @@ -293183,8 +295682,6 @@ module \ls180 assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign { } { } assign $0\builder_next_state[1:0] \builder_state attribute \src "ls180.v:5859.2-5883.9" switch \builder_state @@ -295119,13 +297616,13 @@ module \ls180 end attribute \src "ls180.v:7705.1-10349.4" process $proc$ls180.v:7705$2573 - assign $0\uart_tx[0:0] \uart_tx assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } + assign $0\uart_tx[0:0] \uart_tx assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } @@ -299699,13 +302196,13 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\uart_tx[0:0] 1'1 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 assign $0\pwm[1:0] 2'00 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 @@ -299994,13 +302491,13 @@ module \ls180 case end sync posedge \sys_clk_1 - update \uart_tx $0\uart_tx[0:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] @@ -303083,37 +305580,37 @@ module \ls180 connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3076_DATA end -attribute \src "libresoc.v:144930.1-144988.10" +attribute \src "libresoc.v:146562.1-146620.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:144931.7-144931.20" + attribute \src "libresoc.v:146563.7-146563.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144976.3-144984.6" - wire $0\q_int$next[0:0]$7101 - attribute \src "libresoc.v:144974.3-144975.27" + attribute \src "libresoc.v:146608.3-146616.6" + wire $0\q_int$next[0:0]$7149 + attribute \src "libresoc.v:146606.3-146607.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:144976.3-144984.6" - wire $1\q_int$next[0:0]$7102 - attribute \src "libresoc.v:144953.7-144953.19" + attribute \src "libresoc.v:146608.3-146616.6" + wire $1\q_int$next[0:0]$7150 + attribute \src "libresoc.v:146585.7-146585.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:144966.17-144966.96" - wire $and$libresoc.v:144966$7091_Y - attribute \src "libresoc.v:144971.17-144971.96" - wire $and$libresoc.v:144971$7096_Y - attribute \src "libresoc.v:144968.18-144968.93" - wire $not$libresoc.v:144968$7093_Y - attribute \src "libresoc.v:144970.17-144970.92" - wire $not$libresoc.v:144970$7095_Y - attribute \src "libresoc.v:144973.17-144973.92" - wire $not$libresoc.v:144973$7098_Y - attribute \src "libresoc.v:144967.18-144967.98" - wire $or$libresoc.v:144967$7092_Y - attribute \src "libresoc.v:144969.18-144969.99" - wire $or$libresoc.v:144969$7094_Y - attribute \src "libresoc.v:144972.17-144972.97" - wire $or$libresoc.v:144972$7097_Y + attribute \src "libresoc.v:146598.17-146598.96" + wire $and$libresoc.v:146598$7139_Y + attribute \src "libresoc.v:146603.17-146603.96" + wire $and$libresoc.v:146603$7144_Y + attribute \src "libresoc.v:146600.18-146600.93" + wire $not$libresoc.v:146600$7141_Y + attribute \src "libresoc.v:146602.17-146602.92" + wire $not$libresoc.v:146602$7143_Y + attribute \src "libresoc.v:146605.17-146605.92" + wire $not$libresoc.v:146605$7146_Y + attribute \src "libresoc.v:146599.18-146599.98" + wire $or$libresoc.v:146599$7140_Y + attribute \src "libresoc.v:146601.18-146601.99" + wire $or$libresoc.v:146601$7142_Y + attribute \src "libresoc.v:146604.17-146604.97" + wire $or$libresoc.v:146604$7145_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -303130,11 +305627,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:144931.7-144931.15" + attribute \src "libresoc.v:146563.7-146563.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -303151,7 +305648,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:144966$7091 + cell $and $and$libresoc.v:146598$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303159,10 +305656,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:144966$7091_Y + connect \Y $and$libresoc.v:146598$7139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:144971$7096 + cell $and $and$libresoc.v:146603$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303170,34 +305667,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:144971$7096_Y + connect \Y $and$libresoc.v:146603$7144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:144968$7093 + cell $not $not$libresoc.v:146600$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:144968$7093_Y + connect \Y $not$libresoc.v:146600$7141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:144970$7095 + cell $not $not$libresoc.v:146602$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:144970$7095_Y + connect \Y $not$libresoc.v:146602$7143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:144973$7098 + cell $not $not$libresoc.v:146605$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:144973$7098_Y + connect \Y $not$libresoc.v:146605$7146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:144967$7092 + cell $or $or$libresoc.v:146599$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303205,10 +305702,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:144967$7092_Y + connect \Y $or$libresoc.v:146599$7140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:144969$7094 + cell $or $or$libresoc.v:146601$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303216,10 +305713,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:144969$7094_Y + connect \Y $or$libresoc.v:146601$7142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:144972$7097 + cell $or $or$libresoc.v:146604$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303227,39 +305724,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:144972$7097_Y + connect \Y $or$libresoc.v:146604$7145_Y end - attribute \src "libresoc.v:144931.7-144931.20" - process $proc$libresoc.v:144931$7103 + attribute \src "libresoc.v:146563.7-146563.20" + process $proc$libresoc.v:146563$7151 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144953.7-144953.19" - process $proc$libresoc.v:144953$7104 + attribute \src "libresoc.v:146585.7-146585.19" + process $proc$libresoc.v:146585$7152 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:144974.3-144975.27" - process $proc$libresoc.v:144974$7099 + attribute \src "libresoc.v:146606.3-146607.27" + process $proc$libresoc.v:146606$7147 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:144976.3-144984.6" - process $proc$libresoc.v:144976$7100 + attribute \src "libresoc.v:146608.3-146616.6" + process $proc$libresoc.v:146608$7148 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7101 $1\q_int$next[0:0]$7102 - attribute \src "libresoc.v:144977.5-144977.29" + assign $0\q_int$next[0:0]$7149 $1\q_int$next[0:0]$7150 + attribute \src "libresoc.v:146609.5-146609.29" switch \initial - attribute \src "libresoc.v:144977.9-144977.17" + attribute \src "libresoc.v:146609.9-146609.17" case 1'1 case end @@ -303268,266 +305765,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7102 1'0 + assign $1\q_int$next[0:0]$7150 1'0 case - assign $1\q_int$next[0:0]$7102 \$5 + assign $1\q_int$next[0:0]$7150 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7101 + update \q_int$next $0\q_int$next[0:0]$7149 end - connect \$9 $and$libresoc.v:144966$7091_Y - connect \$11 $or$libresoc.v:144967$7092_Y - connect \$13 $not$libresoc.v:144968$7093_Y - connect \$15 $or$libresoc.v:144969$7094_Y - connect \$1 $not$libresoc.v:144970$7095_Y - connect \$3 $and$libresoc.v:144971$7096_Y - connect \$5 $or$libresoc.v:144972$7097_Y - connect \$7 $not$libresoc.v:144973$7098_Y + connect \$9 $and$libresoc.v:146598$7139_Y + connect \$11 $or$libresoc.v:146599$7140_Y + connect \$13 $not$libresoc.v:146600$7141_Y + connect \$15 $or$libresoc.v:146601$7142_Y + connect \$1 $not$libresoc.v:146602$7143_Y + connect \$3 $and$libresoc.v:146603$7144_Y + connect \$5 $or$libresoc.v:146604$7145_Y + connect \$7 $not$libresoc.v:146605$7146_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:144992.1-145526.10" +attribute \src "libresoc.v:146624.1-147158.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $0\dbus__adr$next[44:0]$7190 - attribute \src "libresoc.v:145230.3-145231.35" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $0\dbus__adr$next[44:0]$7238 + attribute \src "libresoc.v:146862.3-146863.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:145240.3-145267.6" - wire $0\dbus__cyc$next[0:0]$7164 - attribute \src "libresoc.v:145238.3-145239.35" + attribute \src "libresoc.v:146872.3-146899.6" + wire $0\dbus__cyc$next[0:0]$7212 + attribute \src "libresoc.v:146870.3-146871.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7200 - attribute \src "libresoc.v:145226.3-145227.39" + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7248 + attribute \src "libresoc.v:146858.3-146859.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $0\dbus__sel$next[7:0]$7178 - attribute \src "libresoc.v:145234.3-145235.35" + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $0\dbus__sel$next[7:0]$7226 + attribute \src "libresoc.v:146866.3-146867.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:145268.3-145295.6" - wire $0\dbus__stb$next[0:0]$7170 - attribute \src "libresoc.v:145236.3-145237.35" + attribute \src "libresoc.v:146900.3-146927.6" + wire $0\dbus__stb$next[0:0]$7218 + attribute \src "libresoc.v:146868.3-146869.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:145406.3-145431.6" - wire $0\dbus__we$next[0:0]$7195 - attribute \src "libresoc.v:145228.3-145229.33" + attribute \src "libresoc.v:147038.3-147063.6" + wire $0\dbus__we$next[0:0]$7243 + attribute \src "libresoc.v:146860.3-146861.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:144993.7-144993.20" + attribute \src "libresoc.v:146625.7-146625.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7215 - attribute \src "libresoc.v:145220.3-145221.39" + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7263 + attribute \src "libresoc.v:146852.3-146853.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:146938.3-146955.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7184 - attribute \src "libresoc.v:145232.3-145233.39" + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7232 + attribute \src "libresoc.v:146864.3-146865.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:145458.3-145480.6" - wire $0\m_load_err_o$next[0:0]$7205 - attribute \src "libresoc.v:145224.3-145225.41" + attribute \src "libresoc.v:147090.3-147112.6" + wire $0\m_load_err_o$next[0:0]$7253 + attribute \src "libresoc.v:146856.3-146857.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:145481.3-145503.6" - wire $0\m_store_err_o$next[0:0]$7210 - attribute \src "libresoc.v:145222.3-145223.43" + attribute \src "libresoc.v:147113.3-147135.6" + wire $0\m_store_err_o$next[0:0]$7258 + attribute \src "libresoc.v:146854.3-146855.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:145296.3-145305.6" + attribute \src "libresoc.v:146928.3-146937.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $1\dbus__adr$next[44:0]$7191 - attribute \src "libresoc.v:145098.14-145098.42" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $1\dbus__adr$next[44:0]$7239 + attribute \src "libresoc.v:146730.14-146730.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:145240.3-145267.6" - wire $1\dbus__cyc$next[0:0]$7165 - attribute \src "libresoc.v:145103.7-145103.23" + attribute \src "libresoc.v:146872.3-146899.6" + wire $1\dbus__cyc$next[0:0]$7213 + attribute \src "libresoc.v:146735.7-146735.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7201 - attribute \src "libresoc.v:145110.14-145110.48" + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7249 + attribute \src "libresoc.v:146742.14-146742.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $1\dbus__sel$next[7:0]$7179 - attribute \src "libresoc.v:145117.13-145117.30" + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $1\dbus__sel$next[7:0]$7227 + attribute \src "libresoc.v:146749.13-146749.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:145268.3-145295.6" - wire $1\dbus__stb$next[0:0]$7171 - attribute \src "libresoc.v:145122.7-145122.23" + attribute \src "libresoc.v:146900.3-146927.6" + wire $1\dbus__stb$next[0:0]$7219 + attribute \src "libresoc.v:146754.7-146754.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:145406.3-145431.6" - wire $1\dbus__we$next[0:0]$7196 - attribute \src "libresoc.v:145127.7-145127.22" + attribute \src "libresoc.v:147038.3-147063.6" + wire $1\dbus__we$next[0:0]$7244 + attribute \src "libresoc.v:146759.7-146759.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7216 - attribute \src "libresoc.v:145131.14-145131.44" + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7264 + attribute \src "libresoc.v:146763.14-146763.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:146938.3-146955.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7185 - attribute \src "libresoc.v:145138.14-145138.48" + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7233 + attribute \src "libresoc.v:146770.14-146770.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:145458.3-145480.6" - wire $1\m_load_err_o$next[0:0]$7206 - attribute \src "libresoc.v:145142.7-145142.26" + attribute \src "libresoc.v:147090.3-147112.6" + wire $1\m_load_err_o$next[0:0]$7254 + attribute \src "libresoc.v:146774.7-146774.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:145481.3-145503.6" - wire $1\m_store_err_o$next[0:0]$7211 - attribute \src "libresoc.v:145148.7-145148.27" + attribute \src "libresoc.v:147113.3-147135.6" + wire $1\m_store_err_o$next[0:0]$7259 + attribute \src "libresoc.v:146780.7-146780.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:145296.3-145305.6" + attribute \src "libresoc.v:146928.3-146937.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $2\dbus__adr$next[44:0]$7192 - attribute \src "libresoc.v:145240.3-145267.6" - wire $2\dbus__cyc$next[0:0]$7166 - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7202 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $2\dbus__sel$next[7:0]$7180 - attribute \src "libresoc.v:145268.3-145295.6" - wire $2\dbus__stb$next[0:0]$7172 - attribute \src "libresoc.v:145406.3-145431.6" - wire $2\dbus__we$next[0:0]$7197 - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7217 - attribute \src "libresoc.v:145306.3-145323.6" + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $2\dbus__adr$next[44:0]$7240 + attribute \src "libresoc.v:146872.3-146899.6" + wire $2\dbus__cyc$next[0:0]$7214 + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7250 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $2\dbus__sel$next[7:0]$7228 + attribute \src "libresoc.v:146900.3-146927.6" + wire $2\dbus__stb$next[0:0]$7220 + attribute \src "libresoc.v:147038.3-147063.6" + wire $2\dbus__we$next[0:0]$7245 + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7265 + attribute \src "libresoc.v:146938.3-146955.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7186 - attribute \src "libresoc.v:145458.3-145480.6" - wire $2\m_load_err_o$next[0:0]$7207 - attribute \src "libresoc.v:145481.3-145503.6" - wire $2\m_store_err_o$next[0:0]$7212 - attribute \src "libresoc.v:145380.3-145405.6" - wire width 45 $3\dbus__adr$next[44:0]$7193 - attribute \src "libresoc.v:145240.3-145267.6" - wire $3\dbus__cyc$next[0:0]$7167 - attribute \src "libresoc.v:145432.3-145457.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7203 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $3\dbus__sel$next[7:0]$7181 - attribute \src "libresoc.v:145268.3-145295.6" - wire $3\dbus__stb$next[0:0]$7173 - attribute \src "libresoc.v:145406.3-145431.6" - wire $3\dbus__we$next[0:0]$7198 - attribute \src "libresoc.v:145504.3-145523.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7218 - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7187 - attribute \src "libresoc.v:145458.3-145480.6" - wire $3\m_load_err_o$next[0:0]$7208 - attribute \src "libresoc.v:145481.3-145503.6" - wire $3\m_store_err_o$next[0:0]$7213 - attribute \src "libresoc.v:145240.3-145267.6" - wire $4\dbus__cyc$next[0:0]$7168 - attribute \src "libresoc.v:145324.3-145354.6" - wire width 8 $4\dbus__sel$next[7:0]$7182 - attribute \src "libresoc.v:145268.3-145295.6" - wire $4\dbus__stb$next[0:0]$7174 - attribute \src "libresoc.v:145355.3-145379.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7188 - attribute \src "libresoc.v:145176.18-145176.116" - wire $and$libresoc.v:145176$7109_Y - attribute \src "libresoc.v:145179.18-145179.111" - wire $and$libresoc.v:145179$7112_Y - attribute \src "libresoc.v:145184.18-145184.116" - wire $and$libresoc.v:145184$7117_Y - attribute \src "libresoc.v:145186.18-145186.111" - wire $and$libresoc.v:145186$7119_Y - attribute \src "libresoc.v:145188.17-145188.114" - wire $and$libresoc.v:145188$7121_Y - attribute \src "libresoc.v:145192.18-145192.116" - wire $and$libresoc.v:145192$7125_Y - attribute \src "libresoc.v:145194.18-145194.111" - wire $and$libresoc.v:145194$7127_Y - attribute \src "libresoc.v:145200.18-145200.116" - wire $and$libresoc.v:145200$7133_Y - attribute \src "libresoc.v:145202.18-145202.111" - wire $and$libresoc.v:145202$7135_Y - attribute \src "libresoc.v:145204.18-145204.116" - wire $and$libresoc.v:145204$7137_Y - attribute \src "libresoc.v:145206.18-145206.111" - wire $and$libresoc.v:145206$7139_Y - attribute \src "libresoc.v:145208.18-145208.116" - wire $and$libresoc.v:145208$7141_Y - attribute \src "libresoc.v:145210.17-145210.108" - wire $and$libresoc.v:145210$7143_Y - attribute \src "libresoc.v:145211.18-145211.111" - wire $and$libresoc.v:145211$7144_Y - attribute \src "libresoc.v:145212.18-145212.120" - wire $and$libresoc.v:145212$7145_Y - attribute \src "libresoc.v:145215.18-145215.120" - wire $and$libresoc.v:145215$7148_Y - attribute \src "libresoc.v:145217.18-145217.120" - wire $and$libresoc.v:145217$7150_Y - attribute \src "libresoc.v:145173.18-145173.110" - wire $not$libresoc.v:145173$7106_Y - attribute \src "libresoc.v:145178.18-145178.110" - wire $not$libresoc.v:145178$7111_Y - attribute \src "libresoc.v:145181.18-145181.110" - wire $not$libresoc.v:145181$7114_Y - attribute \src "libresoc.v:145185.18-145185.110" - wire $not$libresoc.v:145185$7118_Y - attribute \src "libresoc.v:145189.18-145189.110" - wire $not$libresoc.v:145189$7122_Y - attribute \src "libresoc.v:145193.18-145193.110" - wire $not$libresoc.v:145193$7126_Y - attribute \src "libresoc.v:145196.18-145196.110" - wire $not$libresoc.v:145196$7129_Y - attribute \src "libresoc.v:145199.17-145199.109" - wire $not$libresoc.v:145199$7132_Y - attribute \src "libresoc.v:145201.18-145201.110" - wire $not$libresoc.v:145201$7134_Y - attribute \src "libresoc.v:145205.18-145205.110" - wire $not$libresoc.v:145205$7138_Y - attribute \src "libresoc.v:145209.18-145209.110" - wire $not$libresoc.v:145209$7142_Y - attribute \src "libresoc.v:145213.18-145213.110" - wire $not$libresoc.v:145213$7146_Y - attribute \src "libresoc.v:145214.18-145214.109" - wire $not$libresoc.v:145214$7147_Y - attribute \src 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$or$libresoc.v:145191$7124_Y - attribute \src "libresoc.v:145195.18-145195.120" - wire $or$libresoc.v:145195$7128_Y - attribute \src "libresoc.v:145197.18-145197.111" - wire $or$libresoc.v:145197$7130_Y - attribute \src "libresoc.v:145198.18-145198.114" - wire $or$libresoc.v:145198$7131_Y - attribute \src "libresoc.v:145203.18-145203.114" - wire $or$libresoc.v:145203$7136_Y - attribute \src "libresoc.v:145207.18-145207.114" - wire $or$libresoc.v:145207$7140_Y - attribute \src "libresoc.v:145219.18-145219.127" - wire $or$libresoc.v:145219$7152_Y + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7234 + attribute \src "libresoc.v:147090.3-147112.6" + wire $2\m_load_err_o$next[0:0]$7255 + attribute \src "libresoc.v:147113.3-147135.6" + wire $2\m_store_err_o$next[0:0]$7260 + attribute \src "libresoc.v:147012.3-147037.6" + wire width 45 $3\dbus__adr$next[44:0]$7241 + attribute \src "libresoc.v:146872.3-146899.6" + wire $3\dbus__cyc$next[0:0]$7215 + attribute \src "libresoc.v:147064.3-147089.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7251 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $3\dbus__sel$next[7:0]$7229 + attribute \src "libresoc.v:146900.3-146927.6" + wire $3\dbus__stb$next[0:0]$7221 + attribute \src "libresoc.v:147038.3-147063.6" + wire $3\dbus__we$next[0:0]$7246 + attribute \src "libresoc.v:147136.3-147155.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7266 + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7235 + attribute \src "libresoc.v:147090.3-147112.6" + wire $3\m_load_err_o$next[0:0]$7256 + attribute \src "libresoc.v:147113.3-147135.6" + wire $3\m_store_err_o$next[0:0]$7261 + attribute \src "libresoc.v:146872.3-146899.6" + wire $4\dbus__cyc$next[0:0]$7216 + attribute \src "libresoc.v:146956.3-146986.6" + wire width 8 $4\dbus__sel$next[7:0]$7230 + attribute \src "libresoc.v:146900.3-146927.6" + wire $4\dbus__stb$next[0:0]$7222 + attribute \src "libresoc.v:146987.3-147011.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7236 + attribute \src "libresoc.v:146808.18-146808.116" + wire $and$libresoc.v:146808$7157_Y + attribute \src "libresoc.v:146811.18-146811.111" + wire $and$libresoc.v:146811$7160_Y + attribute \src "libresoc.v:146816.18-146816.116" + wire $and$libresoc.v:146816$7165_Y + attribute \src "libresoc.v:146818.18-146818.111" + wire $and$libresoc.v:146818$7167_Y + attribute \src "libresoc.v:146820.17-146820.114" + wire $and$libresoc.v:146820$7169_Y + attribute \src "libresoc.v:146824.18-146824.116" + wire $and$libresoc.v:146824$7173_Y + attribute \src "libresoc.v:146826.18-146826.111" + wire $and$libresoc.v:146826$7175_Y + attribute \src "libresoc.v:146832.18-146832.116" + wire $and$libresoc.v:146832$7181_Y + attribute \src "libresoc.v:146834.18-146834.111" + wire $and$libresoc.v:146834$7183_Y + attribute \src "libresoc.v:146836.18-146836.116" + wire $and$libresoc.v:146836$7185_Y + attribute \src "libresoc.v:146838.18-146838.111" + wire $and$libresoc.v:146838$7187_Y + attribute \src "libresoc.v:146840.18-146840.116" + wire $and$libresoc.v:146840$7189_Y + attribute \src "libresoc.v:146842.17-146842.108" + wire $and$libresoc.v:146842$7191_Y + attribute \src "libresoc.v:146843.18-146843.111" + wire $and$libresoc.v:146843$7192_Y + attribute \src "libresoc.v:146844.18-146844.120" + wire $and$libresoc.v:146844$7193_Y + attribute \src "libresoc.v:146847.18-146847.120" + wire $and$libresoc.v:146847$7196_Y + attribute \src "libresoc.v:146849.18-146849.120" + wire $and$libresoc.v:146849$7198_Y + attribute \src "libresoc.v:146805.18-146805.110" + wire $not$libresoc.v:146805$7154_Y + attribute \src "libresoc.v:146810.18-146810.110" + wire $not$libresoc.v:146810$7159_Y + attribute \src "libresoc.v:146813.18-146813.110" + wire $not$libresoc.v:146813$7162_Y + attribute \src "libresoc.v:146817.18-146817.110" + wire $not$libresoc.v:146817$7166_Y + attribute \src "libresoc.v:146821.18-146821.110" + wire $not$libresoc.v:146821$7170_Y + attribute \src "libresoc.v:146825.18-146825.110" + wire $not$libresoc.v:146825$7174_Y + attribute \src "libresoc.v:146828.18-146828.110" + wire $not$libresoc.v:146828$7177_Y + attribute \src "libresoc.v:146831.17-146831.109" + wire $not$libresoc.v:146831$7180_Y + attribute \src "libresoc.v:146833.18-146833.110" + wire $not$libresoc.v:146833$7182_Y + attribute \src "libresoc.v:146837.18-146837.110" + wire $not$libresoc.v:146837$7186_Y + attribute \src "libresoc.v:146841.18-146841.110" + wire $not$libresoc.v:146841$7190_Y + attribute \src "libresoc.v:146845.18-146845.110" + wire $not$libresoc.v:146845$7194_Y + attribute \src "libresoc.v:146846.18-146846.109" + wire $not$libresoc.v:146846$7195_Y + attribute \src "libresoc.v:146848.18-146848.110" + wire $not$libresoc.v:146848$7197_Y + attribute \src "libresoc.v:146850.18-146850.110" + wire $not$libresoc.v:146850$7199_Y + attribute \src "libresoc.v:146804.17-146804.119" + wire $or$libresoc.v:146804$7153_Y + attribute \src "libresoc.v:146806.18-146806.110" + wire $or$libresoc.v:146806$7155_Y + attribute \src "libresoc.v:146807.18-146807.114" + wire $or$libresoc.v:146807$7156_Y + attribute \src "libresoc.v:146809.17-146809.113" + wire $or$libresoc.v:146809$7158_Y + attribute \src "libresoc.v:146812.18-146812.120" + wire $or$libresoc.v:146812$7161_Y + attribute \src "libresoc.v:146814.18-146814.111" + wire $or$libresoc.v:146814$7163_Y + attribute \src "libresoc.v:146815.18-146815.114" + wire $or$libresoc.v:146815$7164_Y + attribute \src "libresoc.v:146819.18-146819.120" + wire $or$libresoc.v:146819$7168_Y + attribute \src "libresoc.v:146822.18-146822.111" + wire $or$libresoc.v:146822$7171_Y + attribute \src "libresoc.v:146823.18-146823.114" + wire $or$libresoc.v:146823$7172_Y + attribute \src "libresoc.v:146827.18-146827.120" + wire $or$libresoc.v:146827$7176_Y + attribute \src "libresoc.v:146829.18-146829.111" + wire $or$libresoc.v:146829$7178_Y + attribute \src "libresoc.v:146830.18-146830.114" + wire $or$libresoc.v:146830$7179_Y + attribute \src "libresoc.v:146835.18-146835.114" + wire $or$libresoc.v:146835$7184_Y + attribute \src "libresoc.v:146839.18-146839.114" + wire $or$libresoc.v:146839$7188_Y + attribute \src "libresoc.v:146851.18-146851.127" + wire $or$libresoc.v:146851$7200_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -303624,9 +306121,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -303658,7 +306155,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:144993.7-144993.15" + attribute \src "libresoc.v:146625.7-146625.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -303701,7 +306198,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145176$7109 + cell $and $and$libresoc.v:146808$7157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303709,10 +306206,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:145176$7109_Y + connect \Y $and$libresoc.v:146808$7157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145179$7112 + cell $and $and$libresoc.v:146811$7160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303720,10 +306217,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:145179$7112_Y + connect \Y $and$libresoc.v:146811$7160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145184$7117 + cell $and $and$libresoc.v:146816$7165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303731,10 +306228,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:145184$7117_Y + connect \Y $and$libresoc.v:146816$7165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145186$7119 + cell $and $and$libresoc.v:146818$7167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303742,10 +306239,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:145186$7119_Y + connect \Y $and$libresoc.v:146818$7167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145188$7121 + cell $and $and$libresoc.v:146820$7169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303753,10 +306250,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:145188$7121_Y + connect \Y $and$libresoc.v:146820$7169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145192$7125 + cell $and $and$libresoc.v:146824$7173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303764,10 +306261,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:145192$7125_Y + connect \Y $and$libresoc.v:146824$7173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145194$7127 + cell $and $and$libresoc.v:146826$7175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303775,10 +306272,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:145194$7127_Y + connect \Y $and$libresoc.v:146826$7175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145200$7133 + cell $and $and$libresoc.v:146832$7181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303786,10 +306283,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:145200$7133_Y + connect \Y $and$libresoc.v:146832$7181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145202$7135 + cell $and $and$libresoc.v:146834$7183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303797,10 +306294,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:145202$7135_Y + connect \Y $and$libresoc.v:146834$7183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145204$7137 + cell $and $and$libresoc.v:146836$7185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303808,10 +306305,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:145204$7137_Y + connect \Y $and$libresoc.v:146836$7185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145206$7139 + cell $and $and$libresoc.v:146838$7187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303819,10 +306316,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:145206$7139_Y + connect \Y $and$libresoc.v:146838$7187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145208$7141 + cell $and $and$libresoc.v:146840$7189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303830,10 +306327,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:145208$7141_Y + connect \Y $and$libresoc.v:146840$7189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145210$7143 + cell $and $and$libresoc.v:146842$7191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303841,10 +306338,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:145210$7143_Y + connect \Y $and$libresoc.v:146842$7191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:145211$7144 + cell $and $and$libresoc.v:146843$7192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303852,10 +306349,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:145211$7144_Y + connect \Y $and$libresoc.v:146843$7192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145212$7145 + cell $and $and$libresoc.v:146844$7193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303863,10 +306360,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145212$7145_Y + connect \Y $and$libresoc.v:146844$7193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145215$7148 + cell $and $and$libresoc.v:146847$7196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303874,10 +306371,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145215$7148_Y + connect \Y $and$libresoc.v:146847$7196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:145217$7150 + cell $and $and$libresoc.v:146849$7198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303885,130 +306382,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:145217$7150_Y + connect \Y $and$libresoc.v:146849$7198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145173$7106 + cell $not $not$libresoc.v:146805$7154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145173$7106_Y + connect \Y $not$libresoc.v:146805$7154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145178$7111 + cell $not $not$libresoc.v:146810$7159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145178$7111_Y + connect \Y $not$libresoc.v:146810$7159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145181$7114 + cell $not $not$libresoc.v:146813$7162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145181$7114_Y + connect \Y $not$libresoc.v:146813$7162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145185$7118 + cell $not $not$libresoc.v:146817$7166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145185$7118_Y + connect \Y $not$libresoc.v:146817$7166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145189$7122 + cell $not $not$libresoc.v:146821$7170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145189$7122_Y + connect \Y $not$libresoc.v:146821$7170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145193$7126 + cell $not $not$libresoc.v:146825$7174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145193$7126_Y + connect \Y $not$libresoc.v:146825$7174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:145196$7129 + cell $not $not$libresoc.v:146828$7177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:145196$7129_Y + connect \Y $not$libresoc.v:146828$7177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145199$7132 + cell $not $not$libresoc.v:146831$7180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145199$7132_Y + connect \Y $not$libresoc.v:146831$7180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145201$7134 + cell $not $not$libresoc.v:146833$7182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145201$7134_Y + connect \Y $not$libresoc.v:146833$7182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145205$7138 + cell $not $not$libresoc.v:146837$7186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145205$7138_Y + connect \Y $not$libresoc.v:146837$7186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:145209$7142 + cell $not $not$libresoc.v:146841$7190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:145209$7142_Y + connect \Y $not$libresoc.v:146841$7190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145213$7146 + cell $not $not$libresoc.v:146845$7194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145213$7146_Y + connect \Y $not$libresoc.v:146845$7194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:145214$7147 + cell $not $not$libresoc.v:146846$7195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:145214$7147_Y + connect \Y $not$libresoc.v:146846$7195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145216$7149 + cell $not $not$libresoc.v:146848$7197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145216$7149_Y + connect \Y $not$libresoc.v:146848$7197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:145218$7151 + cell $not $not$libresoc.v:146850$7199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:145218$7151_Y + connect \Y $not$libresoc.v:146850$7199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145172$7105 + cell $or $or$libresoc.v:146804$7153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304016,10 +306513,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145172$7105_Y + connect \Y $or$libresoc.v:146804$7153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145174$7107 + cell $or $or$libresoc.v:146806$7155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304027,10 +306524,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:145174$7107_Y + connect \Y $or$libresoc.v:146806$7155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145175$7108 + cell $or $or$libresoc.v:146807$7156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304038,10 +306535,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145175$7108_Y + connect \Y $or$libresoc.v:146807$7156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145177$7110 + cell $or $or$libresoc.v:146809$7158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304049,10 +306546,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145177$7110_Y + connect \Y $or$libresoc.v:146809$7158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145180$7113 + cell $or $or$libresoc.v:146812$7161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304060,10 +306557,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145180$7113_Y + connect \Y $or$libresoc.v:146812$7161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145182$7115 + cell $or $or$libresoc.v:146814$7163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304071,10 +306568,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:145182$7115_Y + connect \Y $or$libresoc.v:146814$7163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145183$7116 + cell $or $or$libresoc.v:146815$7164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304082,10 +306579,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145183$7116_Y + connect \Y $or$libresoc.v:146815$7164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145187$7120 + cell $or $or$libresoc.v:146819$7168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304093,10 +306590,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145187$7120_Y + connect \Y $or$libresoc.v:146819$7168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145190$7123 + cell $or $or$libresoc.v:146822$7171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304104,10 +306601,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:145190$7123_Y + connect \Y $or$libresoc.v:146822$7171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145191$7124 + cell $or $or$libresoc.v:146823$7172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304115,10 +306612,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145191$7124_Y + connect \Y $or$libresoc.v:146823$7172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145195$7128 + cell $or $or$libresoc.v:146827$7176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304126,10 +306623,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:145195$7128_Y + connect \Y $or$libresoc.v:146827$7176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:145197$7130 + cell $or $or$libresoc.v:146829$7178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304137,10 +306634,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:145197$7130_Y + connect \Y $or$libresoc.v:146829$7178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145198$7131 + cell $or $or$libresoc.v:146830$7179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304148,10 +306645,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145198$7131_Y + connect \Y $or$libresoc.v:146830$7179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145203$7136 + cell $or $or$libresoc.v:146835$7184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304159,10 +306656,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145203$7136_Y + connect \Y $or$libresoc.v:146835$7184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:145207$7140 + cell $or $or$libresoc.v:146839$7188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304170,10 +306667,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:145207$7140_Y + connect \Y $or$libresoc.v:146839$7188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:145219$7152 + cell $or $or$libresoc.v:146851$7200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304181,175 +306678,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:145219$7152_Y + connect \Y $or$libresoc.v:146851$7200_Y end - attribute \src "libresoc.v:144993.7-144993.20" - process $proc$libresoc.v:144993$7219 + attribute \src "libresoc.v:146625.7-146625.20" + process $proc$libresoc.v:146625$7267 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145098.14-145098.42" - process $proc$libresoc.v:145098$7220 + attribute \src "libresoc.v:146730.14-146730.42" + process $proc$libresoc.v:146730$7268 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:145103.7-145103.23" - process $proc$libresoc.v:145103$7221 + attribute \src "libresoc.v:146735.7-146735.23" + process $proc$libresoc.v:146735$7269 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:145110.14-145110.48" - process $proc$libresoc.v:145110$7222 + attribute \src "libresoc.v:146742.14-146742.48" + process $proc$libresoc.v:146742$7270 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:145117.13-145117.30" - process $proc$libresoc.v:145117$7223 + attribute \src "libresoc.v:146749.13-146749.30" + process $proc$libresoc.v:146749$7271 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:145122.7-145122.23" - process $proc$libresoc.v:145122$7224 + attribute \src "libresoc.v:146754.7-146754.23" + process $proc$libresoc.v:146754$7272 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:145127.7-145127.22" - process $proc$libresoc.v:145127$7225 + attribute \src "libresoc.v:146759.7-146759.22" + process $proc$libresoc.v:146759$7273 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:145131.14-145131.44" - process $proc$libresoc.v:145131$7226 + attribute \src "libresoc.v:146763.14-146763.44" + process $proc$libresoc.v:146763$7274 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:145138.14-145138.48" - process $proc$libresoc.v:145138$7227 + attribute \src "libresoc.v:146770.14-146770.48" + process $proc$libresoc.v:146770$7275 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:145142.7-145142.26" - process $proc$libresoc.v:145142$7228 + attribute \src "libresoc.v:146774.7-146774.26" + process $proc$libresoc.v:146774$7276 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:145148.7-145148.27" - process $proc$libresoc.v:145148$7229 + attribute \src "libresoc.v:146780.7-146780.27" + process $proc$libresoc.v:146780$7277 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:145220.3-145221.39" - process $proc$libresoc.v:145220$7153 + attribute \src "libresoc.v:146852.3-146853.39" + process $proc$libresoc.v:146852$7201 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:145222.3-145223.43" - process $proc$libresoc.v:145222$7154 + attribute \src "libresoc.v:146854.3-146855.43" + process $proc$libresoc.v:146854$7202 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:145224.3-145225.41" - process $proc$libresoc.v:145224$7155 + attribute \src "libresoc.v:146856.3-146857.41" + process $proc$libresoc.v:146856$7203 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:145226.3-145227.39" - process $proc$libresoc.v:145226$7156 + attribute \src "libresoc.v:146858.3-146859.39" + process $proc$libresoc.v:146858$7204 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:145228.3-145229.33" - process $proc$libresoc.v:145228$7157 + attribute \src "libresoc.v:146860.3-146861.33" + process $proc$libresoc.v:146860$7205 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:145230.3-145231.35" - process $proc$libresoc.v:145230$7158 + attribute \src "libresoc.v:146862.3-146863.35" + process $proc$libresoc.v:146862$7206 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:145232.3-145233.39" - process $proc$libresoc.v:145232$7159 + attribute \src "libresoc.v:146864.3-146865.39" + process $proc$libresoc.v:146864$7207 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:145234.3-145235.35" - process $proc$libresoc.v:145234$7160 + attribute \src "libresoc.v:146866.3-146867.35" + process $proc$libresoc.v:146866$7208 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:145236.3-145237.35" - process $proc$libresoc.v:145236$7161 + attribute \src "libresoc.v:146868.3-146869.35" + process $proc$libresoc.v:146868$7209 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:145238.3-145239.35" - process $proc$libresoc.v:145238$7162 + attribute \src "libresoc.v:146870.3-146871.35" + process $proc$libresoc.v:146870$7210 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:145240.3-145267.6" - process $proc$libresoc.v:145240$7163 + attribute \src "libresoc.v:146872.3-146899.6" + process $proc$libresoc.v:146872$7211 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$7164 $4\dbus__cyc$next[0:0]$7168 - attribute \src "libresoc.v:145241.5-145241.29" + assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 + attribute \src "libresoc.v:146873.5-146873.29" switch \initial - attribute \src "libresoc.v:145241.9-145241.17" + attribute \src "libresoc.v:146873.9-146873.17" case 1'1 case end @@ -304358,53 +306855,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$7165 $2\dbus__cyc$next[0:0]$7166 + assign $1\dbus__cyc$next[0:0]$7213 $2\dbus__cyc$next[0:0]$7214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$7166 $3\dbus__cyc$next[0:0]$7167 + assign $2\dbus__cyc$next[0:0]$7214 $3\dbus__cyc$next[0:0]$7215 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$7167 1'0 + assign $3\dbus__cyc$next[0:0]$7215 1'0 case - assign $3\dbus__cyc$next[0:0]$7167 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7215 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$7166 1'1 + assign $2\dbus__cyc$next[0:0]$7214 1'1 case - assign $2\dbus__cyc$next[0:0]$7166 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7214 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$7165 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7213 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$7168 1'0 + assign $4\dbus__cyc$next[0:0]$7216 1'0 case - assign $4\dbus__cyc$next[0:0]$7168 $1\dbus__cyc$next[0:0]$7165 + assign $4\dbus__cyc$next[0:0]$7216 $1\dbus__cyc$next[0:0]$7213 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7164 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 end - attribute \src "libresoc.v:145268.3-145295.6" - process $proc$libresoc.v:145268$7169 + attribute \src "libresoc.v:146900.3-146927.6" + process $proc$libresoc.v:146900$7217 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$7170 $4\dbus__stb$next[0:0]$7174 - attribute \src "libresoc.v:145269.5-145269.29" + assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 + attribute \src "libresoc.v:146901.5-146901.29" switch \initial - attribute \src "libresoc.v:145269.9-145269.17" + attribute \src "libresoc.v:146901.9-146901.17" case 1'1 case end @@ -304413,52 +306910,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$7171 $2\dbus__stb$next[0:0]$7172 + assign $1\dbus__stb$next[0:0]$7219 $2\dbus__stb$next[0:0]$7220 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$7172 $3\dbus__stb$next[0:0]$7173 + assign $2\dbus__stb$next[0:0]$7220 $3\dbus__stb$next[0:0]$7221 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$7173 1'0 + assign $3\dbus__stb$next[0:0]$7221 1'0 case - assign $3\dbus__stb$next[0:0]$7173 \dbus__stb + assign $3\dbus__stb$next[0:0]$7221 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$7172 1'1 + assign $2\dbus__stb$next[0:0]$7220 1'1 case - assign $2\dbus__stb$next[0:0]$7172 \dbus__stb + assign $2\dbus__stb$next[0:0]$7220 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$7171 \dbus__stb + assign $1\dbus__stb$next[0:0]$7219 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$7174 1'0 + assign $4\dbus__stb$next[0:0]$7222 1'0 case - assign $4\dbus__stb$next[0:0]$7174 $1\dbus__stb$next[0:0]$7171 + assign $4\dbus__stb$next[0:0]$7222 $1\dbus__stb$next[0:0]$7219 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7170 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 end - attribute \src "libresoc.v:145296.3-145305.6" - process $proc$libresoc.v:145296$7175 + attribute \src "libresoc.v:146928.3-146937.6" + process $proc$libresoc.v:146928$7223 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:145297.5-145297.29" + attribute \src "libresoc.v:146929.5-146929.29" switch \initial - attribute \src "libresoc.v:145297.9-145297.17" + attribute \src "libresoc.v:146929.9-146929.17" case 1'1 case end @@ -304474,14 +306971,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:145306.3-145323.6" - process $proc$libresoc.v:145306$7176 + attribute \src "libresoc.v:146938.3-146955.6" + process $proc$libresoc.v:146938$7224 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:145307.5-145307.29" + attribute \src "libresoc.v:146939.5-146939.29" switch \initial - attribute \src "libresoc.v:145307.9-145307.17" + attribute \src "libresoc.v:146939.9-146939.17" case 1'1 case end @@ -304508,15 +307005,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:145324.3-145354.6" - process $proc$libresoc.v:145324$7177 + attribute \src "libresoc.v:146956.3-146986.6" + process $proc$libresoc.v:146956$7225 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$7178 $4\dbus__sel$next[7:0]$7182 - attribute \src "libresoc.v:145325.5-145325.29" + assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 + attribute \src "libresoc.v:146957.5-146957.29" switch \initial - attribute \src "libresoc.v:145325.9-145325.17" + attribute \src "libresoc.v:146957.9-146957.17" case 1'1 case end @@ -304525,55 +307022,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$7179 $2\dbus__sel$next[7:0]$7180 + assign $1\dbus__sel$next[7:0]$7227 $2\dbus__sel$next[7:0]$7228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$7180 $3\dbus__sel$next[7:0]$7181 + assign $2\dbus__sel$next[7:0]$7228 $3\dbus__sel$next[7:0]$7229 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$7181 8'00000000 + assign $3\dbus__sel$next[7:0]$7229 8'00000000 case - assign $3\dbus__sel$next[7:0]$7181 \dbus__sel + assign $3\dbus__sel$next[7:0]$7229 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$7180 \x_mask_i + assign $2\dbus__sel$next[7:0]$7228 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$7180 8'00000000 + assign $2\dbus__sel$next[7:0]$7228 8'00000000 end case - assign $1\dbus__sel$next[7:0]$7179 \dbus__sel + assign $1\dbus__sel$next[7:0]$7227 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$7182 8'00000000 + assign $4\dbus__sel$next[7:0]$7230 8'00000000 case - assign $4\dbus__sel$next[7:0]$7182 $1\dbus__sel$next[7:0]$7179 + assign $4\dbus__sel$next[7:0]$7230 $1\dbus__sel$next[7:0]$7227 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7178 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 end - attribute \src "libresoc.v:145355.3-145379.6" - process $proc$libresoc.v:145355$7183 + attribute \src "libresoc.v:146987.3-147011.6" + process $proc$libresoc.v:146987$7231 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7184 $4\m_ld_data_o$next[63:0]$7188 - attribute \src "libresoc.v:145356.5-145356.29" + assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 + attribute \src "libresoc.v:146988.5-146988.29" switch \initial - attribute \src "libresoc.v:145356.9-145356.17" + attribute \src "libresoc.v:146988.9-146988.17" case 1'1 case end @@ -304582,49 +307079,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$7185 $2\m_ld_data_o$next[63:0]$7186 + assign $1\m_ld_data_o$next[63:0]$7233 $2\m_ld_data_o$next[63:0]$7234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$7186 $3\m_ld_data_o$next[63:0]$7187 + assign $2\m_ld_data_o$next[63:0]$7234 $3\m_ld_data_o$next[63:0]$7235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$7187 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7235 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$7187 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7235 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7186 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7234 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$7185 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7233 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$7188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7236 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$7188 $1\m_ld_data_o$next[63:0]$7185 + assign $4\m_ld_data_o$next[63:0]$7236 $1\m_ld_data_o$next[63:0]$7233 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7184 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 end - attribute \src "libresoc.v:145380.3-145405.6" - process $proc$libresoc.v:145380$7189 + attribute \src "libresoc.v:147012.3-147037.6" + process $proc$libresoc.v:147012$7237 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$7190 $3\dbus__adr$next[44:0]$7193 - attribute \src "libresoc.v:145381.5-145381.29" + assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 + attribute \src "libresoc.v:147013.5-147013.29" switch \initial - attribute \src "libresoc.v:145381.9-145381.17" + attribute \src "libresoc.v:147013.9-147013.17" case 1'1 case end @@ -304633,45 +307130,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$7191 $2\dbus__adr$next[44:0]$7192 + assign $1\dbus__adr$next[44:0]$7239 $2\dbus__adr$next[44:0]$7240 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$7192 \dbus__adr + assign $2\dbus__adr$next[44:0]$7240 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$7192 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7240 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$7192 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7240 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$7191 \dbus__adr + assign $1\dbus__adr$next[44:0]$7239 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$7193 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7241 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$7193 $1\dbus__adr$next[44:0]$7191 + assign $3\dbus__adr$next[44:0]$7241 $1\dbus__adr$next[44:0]$7239 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7190 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 end - attribute \src "libresoc.v:145406.3-145431.6" - process $proc$libresoc.v:145406$7194 + attribute \src "libresoc.v:147038.3-147063.6" + process $proc$libresoc.v:147038$7242 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$7195 $3\dbus__we$next[0:0]$7198 - attribute \src "libresoc.v:145407.5-145407.29" + assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 + attribute \src "libresoc.v:147039.5-147039.29" switch \initial - attribute \src "libresoc.v:145407.9-145407.17" + attribute \src "libresoc.v:147039.9-147039.17" case 1'1 case end @@ -304680,45 +307177,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$7196 $2\dbus__we$next[0:0]$7197 + assign $1\dbus__we$next[0:0]$7244 $2\dbus__we$next[0:0]$7245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$7197 \dbus__we + assign $2\dbus__we$next[0:0]$7245 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$7197 \x_st_i + assign $2\dbus__we$next[0:0]$7245 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$7197 1'0 + assign $2\dbus__we$next[0:0]$7245 1'0 end case - assign $1\dbus__we$next[0:0]$7196 \dbus__we + assign $1\dbus__we$next[0:0]$7244 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$7198 1'0 + assign $3\dbus__we$next[0:0]$7246 1'0 case - assign $3\dbus__we$next[0:0]$7198 $1\dbus__we$next[0:0]$7196 + assign $3\dbus__we$next[0:0]$7246 $1\dbus__we$next[0:0]$7244 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7195 + update \dbus__we$next $0\dbus__we$next[0:0]$7243 end - attribute \src "libresoc.v:145432.3-145457.6" - process $proc$libresoc.v:145432$7199 + attribute \src "libresoc.v:147064.3-147089.6" + process $proc$libresoc.v:147064$7247 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$7200 $3\dbus__dat_w$next[63:0]$7203 - attribute \src "libresoc.v:145433.5-145433.29" + assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 + attribute \src "libresoc.v:147065.5-147065.29" switch \initial - attribute \src "libresoc.v:145433.9-145433.17" + attribute \src "libresoc.v:147065.9-147065.17" case 1'1 case end @@ -304727,45 +307224,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$7201 $2\dbus__dat_w$next[63:0]$7202 + assign $1\dbus__dat_w$next[63:0]$7249 $2\dbus__dat_w$next[63:0]$7250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7202 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7250 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$7202 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7250 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$7202 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7250 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$7201 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7249 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$7203 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7251 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$7203 $1\dbus__dat_w$next[63:0]$7201 + assign $3\dbus__dat_w$next[63:0]$7251 $1\dbus__dat_w$next[63:0]$7249 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7200 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 end - attribute \src "libresoc.v:145458.3-145480.6" - process $proc$libresoc.v:145458$7204 + attribute \src "libresoc.v:147090.3-147112.6" + process $proc$libresoc.v:147090$7252 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$7205 $3\m_load_err_o$next[0:0]$7208 - attribute \src "libresoc.v:145459.5-145459.29" + assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 + attribute \src "libresoc.v:147091.5-147091.29" switch \initial - attribute \src "libresoc.v:145459.9-145459.17" + attribute \src "libresoc.v:147091.9-147091.17" case 1'1 case end @@ -304774,44 +307271,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$7206 $2\m_load_err_o$next[0:0]$7207 + assign $1\m_load_err_o$next[0:0]$7254 $2\m_load_err_o$next[0:0]$7255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$7207 \$85 + assign $2\m_load_err_o$next[0:0]$7255 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$7207 1'0 + assign $2\m_load_err_o$next[0:0]$7255 1'0 case - assign $2\m_load_err_o$next[0:0]$7207 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7255 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$7206 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7254 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$7208 1'0 + assign $3\m_load_err_o$next[0:0]$7256 1'0 case - assign $3\m_load_err_o$next[0:0]$7208 $1\m_load_err_o$next[0:0]$7206 + assign $3\m_load_err_o$next[0:0]$7256 $1\m_load_err_o$next[0:0]$7254 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7205 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 end - attribute \src "libresoc.v:145481.3-145503.6" - process $proc$libresoc.v:145481$7209 + attribute \src "libresoc.v:147113.3-147135.6" + process $proc$libresoc.v:147113$7257 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7210 $3\m_store_err_o$next[0:0]$7213 - attribute \src "libresoc.v:145482.5-145482.29" + assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 + attribute \src "libresoc.v:147114.5-147114.29" switch \initial - attribute \src "libresoc.v:145482.9-145482.17" + attribute \src "libresoc.v:147114.9-147114.17" case 1'1 case end @@ -304820,44 +307317,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$7211 $2\m_store_err_o$next[0:0]$7212 + assign $1\m_store_err_o$next[0:0]$7259 $2\m_store_err_o$next[0:0]$7260 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$7212 \dbus__we + assign $2\m_store_err_o$next[0:0]$7260 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$7212 1'0 + assign $2\m_store_err_o$next[0:0]$7260 1'0 case - assign $2\m_store_err_o$next[0:0]$7212 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7260 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$7211 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7259 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$7213 1'0 + assign $3\m_store_err_o$next[0:0]$7261 1'0 case - assign $3\m_store_err_o$next[0:0]$7213 $1\m_store_err_o$next[0:0]$7211 + assign $3\m_store_err_o$next[0:0]$7261 $1\m_store_err_o$next[0:0]$7259 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7210 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 end - attribute \src "libresoc.v:145504.3-145523.6" - process $proc$libresoc.v:145504$7214 + attribute \src "libresoc.v:147136.3-147155.6" + process $proc$libresoc.v:147136$7262 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7215 $3\m_badaddr_o$next[44:0]$7218 - attribute \src "libresoc.v:145505.5-145505.29" + assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 + attribute \src "libresoc.v:147137.5-147137.29" switch \initial - attribute \src "libresoc.v:145505.9-145505.17" + attribute \src "libresoc.v:147137.9-147137.17" case 1'1 case end @@ -304866,343 +307363,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$7216 $2\m_badaddr_o$next[44:0]$7217 + assign $1\m_badaddr_o$next[44:0]$7264 $2\m_badaddr_o$next[44:0]$7265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$7217 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7265 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$7217 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7265 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$7216 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7264 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$7218 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7218 $1\m_badaddr_o$next[44:0]$7216 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7215 - end - connect \$9 $or$libresoc.v:145172$7105_Y - connect \$11 $not$libresoc.v:145173$7106_Y - connect \$13 $or$libresoc.v:145174$7107_Y - connect \$15 $or$libresoc.v:145175$7108_Y - connect \$17 $and$libresoc.v:145176$7109_Y - connect \$1 $or$libresoc.v:145177$7110_Y - connect \$19 $not$libresoc.v:145178$7111_Y - connect \$21 $and$libresoc.v:145179$7112_Y - connect \$23 $or$libresoc.v:145180$7113_Y - connect \$25 $not$libresoc.v:145181$7114_Y - connect \$27 $or$libresoc.v:145182$7115_Y - connect \$29 $or$libresoc.v:145183$7116_Y - connect \$31 $and$libresoc.v:145184$7117_Y - connect \$33 $not$libresoc.v:145185$7118_Y - connect \$35 $and$libresoc.v:145186$7119_Y - connect \$37 $or$libresoc.v:145187$7120_Y - connect \$3 $and$libresoc.v:145188$7121_Y - connect \$39 $not$libresoc.v:145189$7122_Y - connect \$41 $or$libresoc.v:145190$7123_Y - connect \$43 $or$libresoc.v:145191$7124_Y - connect \$45 $and$libresoc.v:145192$7125_Y - connect \$47 $not$libresoc.v:145193$7126_Y - connect \$49 $and$libresoc.v:145194$7127_Y - connect \$51 $or$libresoc.v:145195$7128_Y - connect \$53 $not$libresoc.v:145196$7129_Y - connect \$55 $or$libresoc.v:145197$7130_Y - connect \$57 $or$libresoc.v:145198$7131_Y - connect \$5 $not$libresoc.v:145199$7132_Y - connect \$59 $and$libresoc.v:145200$7133_Y - connect \$61 $not$libresoc.v:145201$7134_Y - connect \$63 $and$libresoc.v:145202$7135_Y - connect \$65 $or$libresoc.v:145203$7136_Y - connect \$67 $and$libresoc.v:145204$7137_Y - connect \$69 $not$libresoc.v:145205$7138_Y - connect \$71 $and$libresoc.v:145206$7139_Y - connect \$73 $or$libresoc.v:145207$7140_Y - connect \$75 $and$libresoc.v:145208$7141_Y - connect \$77 $not$libresoc.v:145209$7142_Y - connect \$7 $and$libresoc.v:145210$7143_Y - connect \$79 $and$libresoc.v:145211$7144_Y - connect \$81 $and$libresoc.v:145212$7145_Y - connect \$83 $not$libresoc.v:145213$7146_Y - connect \$85 $not$libresoc.v:145214$7147_Y - connect \$87 $and$libresoc.v:145215$7148_Y - connect \$89 $not$libresoc.v:145216$7149_Y - connect \$91 $and$libresoc.v:145217$7150_Y - connect \$93 $not$libresoc.v:145218$7151_Y - connect \$95 $or$libresoc.v:145219$7152_Y + assign $3\m_badaddr_o$next[44:0]$7266 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7266 $1\m_badaddr_o$next[44:0]$7264 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 + end + connect \$9 $or$libresoc.v:146804$7153_Y + connect \$11 $not$libresoc.v:146805$7154_Y + connect \$13 $or$libresoc.v:146806$7155_Y + connect \$15 $or$libresoc.v:146807$7156_Y + connect \$17 $and$libresoc.v:146808$7157_Y + connect \$1 $or$libresoc.v:146809$7158_Y + connect \$19 $not$libresoc.v:146810$7159_Y + connect \$21 $and$libresoc.v:146811$7160_Y + connect \$23 $or$libresoc.v:146812$7161_Y + connect \$25 $not$libresoc.v:146813$7162_Y + connect \$27 $or$libresoc.v:146814$7163_Y + connect \$29 $or$libresoc.v:146815$7164_Y + connect \$31 $and$libresoc.v:146816$7165_Y + connect \$33 $not$libresoc.v:146817$7166_Y + connect \$35 $and$libresoc.v:146818$7167_Y + connect \$37 $or$libresoc.v:146819$7168_Y + connect \$3 $and$libresoc.v:146820$7169_Y + connect \$39 $not$libresoc.v:146821$7170_Y + connect \$41 $or$libresoc.v:146822$7171_Y + connect \$43 $or$libresoc.v:146823$7172_Y + connect \$45 $and$libresoc.v:146824$7173_Y + connect \$47 $not$libresoc.v:146825$7174_Y + connect \$49 $and$libresoc.v:146826$7175_Y + connect \$51 $or$libresoc.v:146827$7176_Y + connect \$53 $not$libresoc.v:146828$7177_Y + connect \$55 $or$libresoc.v:146829$7178_Y + connect \$57 $or$libresoc.v:146830$7179_Y + connect \$5 $not$libresoc.v:146831$7180_Y + connect \$59 $and$libresoc.v:146832$7181_Y + connect \$61 $not$libresoc.v:146833$7182_Y + connect \$63 $and$libresoc.v:146834$7183_Y + connect \$65 $or$libresoc.v:146835$7184_Y + connect \$67 $and$libresoc.v:146836$7185_Y + connect \$69 $not$libresoc.v:146837$7186_Y + connect \$71 $and$libresoc.v:146838$7187_Y + connect \$73 $or$libresoc.v:146839$7188_Y + connect \$75 $and$libresoc.v:146840$7189_Y + connect \$77 $not$libresoc.v:146841$7190_Y + connect \$7 $and$libresoc.v:146842$7191_Y + connect \$79 $and$libresoc.v:146843$7192_Y + connect \$81 $and$libresoc.v:146844$7193_Y + connect \$83 $not$libresoc.v:146845$7194_Y + connect \$85 $not$libresoc.v:146846$7195_Y + connect \$87 $and$libresoc.v:146847$7196_Y + connect \$89 $not$libresoc.v:146848$7197_Y + connect \$91 $and$libresoc.v:146849$7198_Y + connect \$93 $not$libresoc.v:146850$7199_Y + connect \$95 $or$libresoc.v:146851$7200_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:145530.1-146491.10" +attribute \src "libresoc.v:147162.1-148123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:146443.3-146453.6" + attribute \src "libresoc.v:148075.3-148085.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:146413.3-146422.6" + attribute \src "libresoc.v:148045.3-148054.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:146423.3-146432.6" + attribute \src "libresoc.v:148055.3-148064.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:146433.3-146442.6" + attribute \src "libresoc.v:148065.3-148074.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:146287.3-146300.6" + attribute \src "libresoc.v:147919.3-147932.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:146454.3-146464.6" + attribute \src "libresoc.v:148086.3-148096.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:146465.3-146475.6" + attribute \src "libresoc.v:148097.3-148107.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:146215.3-146229.6" + attribute \src "libresoc.v:147847.3-147861.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:146393.3-146412.6" + attribute \src "libresoc.v:148025.3-148044.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:145531.7-145531.20" + attribute \src "libresoc.v:147163.7-147163.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146053.3-146062.6" + attribute \src "libresoc.v:147685.3-147694.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:146268.3-146286.6" + attribute \src "libresoc.v:147900.3-147918.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:146346.3-146359.6" + attribute \src "libresoc.v:147978.3-147991.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:146382.3-146392.6" + attribute \src "libresoc.v:148014.3-148024.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:146324.3-146334.6" - wire width 2 $0\xer_ca$20[1:0]$7305 - attribute \src "libresoc.v:146335.3-146345.6" + attribute \src "libresoc.v:147956.3-147966.6" + wire width 2 $0\xer_ca$20[1:0]$7353 + attribute \src "libresoc.v:147967.3-147977.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:146360.3-146370.6" + attribute \src "libresoc.v:147992.3-148002.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:146371.3-146381.6" + attribute \src "libresoc.v:148003.3-148013.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:146086.3-146096.6" + attribute \src "libresoc.v:147718.3-147728.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:146476.3-146486.6" + attribute \src "libresoc.v:148108.3-148118.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:146443.3-146453.6" + attribute \src "libresoc.v:148075.3-148085.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:146413.3-146422.6" + attribute \src "libresoc.v:148045.3-148054.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:146423.3-146432.6" + attribute \src "libresoc.v:148055.3-148064.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:146433.3-146442.6" + attribute \src "libresoc.v:148065.3-148074.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:146287.3-146300.6" + attribute \src "libresoc.v:147919.3-147932.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:146454.3-146464.6" + attribute \src "libresoc.v:148086.3-148096.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:146465.3-146475.6" + attribute \src "libresoc.v:148097.3-148107.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:146215.3-146229.6" + attribute \src "libresoc.v:147847.3-147861.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:146393.3-146412.6" + attribute \src "libresoc.v:148025.3-148044.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:146053.3-146062.6" + attribute \src "libresoc.v:147685.3-147694.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:146268.3-146286.6" + attribute \src "libresoc.v:147900.3-147918.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:146346.3-146359.6" + attribute \src "libresoc.v:147978.3-147991.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:146382.3-146392.6" + attribute \src "libresoc.v:148014.3-148024.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:146324.3-146334.6" - wire width 2 $1\xer_ca$20[1:0]$7306 - attribute \src "libresoc.v:146335.3-146345.6" + attribute \src "libresoc.v:147956.3-147966.6" + wire width 2 $1\xer_ca$20[1:0]$7354 + attribute \src "libresoc.v:147967.3-147977.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:146360.3-146370.6" + attribute \src "libresoc.v:147992.3-148002.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:146371.3-146381.6" + attribute \src "libresoc.v:148003.3-148013.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146086.3-146096.6" + attribute \src "libresoc.v:147718.3-147728.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:146476.3-146486.6" + attribute \src "libresoc.v:148108.3-148118.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:146063.3-146085.6" + attribute \src "libresoc.v:147695.3-147717.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:146301.3-146323.6" + attribute \src "libresoc.v:147933.3-147955.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:146189.3-146214.6" + attribute \src "libresoc.v:147821.3-147846.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:146124.3-146142.6" + attribute \src "libresoc.v:147756.3-147774.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:146143.3-146161.6" + attribute \src "libresoc.v:147775.3-147793.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:146162.3-146188.6" + attribute \src "libresoc.v:147794.3-147820.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:146097.3-146123.6" + attribute \src "libresoc.v:147729.3-147755.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:146230.3-146267.6" + attribute \src "libresoc.v:147862.3-147899.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:146028.18-146028.105" - wire width 67 $add$libresoc.v:146028$7266_Y - attribute \src "libresoc.v:146002.19-146002.107" - wire $and$libresoc.v:146002$7240_Y - attribute \src "libresoc.v:146006.19-146006.107" - wire $and$libresoc.v:146006$7244_Y - attribute \src "libresoc.v:146039.18-146039.106" - wire $and$libresoc.v:146039$7277_Y - attribute \src "libresoc.v:146044.18-146044.106" - wire $and$libresoc.v:146044$7282_Y - attribute \src "libresoc.v:146047.18-146047.106" - wire $and$libresoc.v:146047$7285_Y - attribute \src "libresoc.v:146050.18-146050.106" - wire $and$libresoc.v:146050$7288_Y - attribute \src "libresoc.v:145993.19-145993.118" - wire $eq$libresoc.v:145993$7231_Y - attribute \src "libresoc.v:145994.19-145994.118" - wire $eq$libresoc.v:145994$7232_Y - attribute \src "libresoc.v:145995.19-145995.118" - wire $eq$libresoc.v:145995$7233_Y - attribute \src "libresoc.v:146007.19-146007.109" - wire $eq$libresoc.v:146007$7245_Y - attribute \src "libresoc.v:146008.19-146008.110" - wire $eq$libresoc.v:146008$7246_Y - attribute \src "libresoc.v:146009.19-146009.111" - wire $eq$libresoc.v:146009$7247_Y - attribute \src "libresoc.v:146010.19-146010.111" - wire $eq$libresoc.v:146010$7248_Y - attribute \src "libresoc.v:146011.19-146011.111" - wire $eq$libresoc.v:146011$7249_Y - attribute \src "libresoc.v:146012.19-146012.111" - wire $eq$libresoc.v:146012$7250_Y - attribute \src "libresoc.v:146013.19-146013.111" - wire $eq$libresoc.v:146013$7251_Y - attribute \src "libresoc.v:146014.19-146014.111" - wire $eq$libresoc.v:146014$7252_Y - attribute \src "libresoc.v:146015.18-146015.118" - wire $eq$libresoc.v:146015$7253_Y - attribute \src "libresoc.v:146017.18-146017.118" - wire $eq$libresoc.v:146017$7255_Y - attribute \src "libresoc.v:146018.18-146018.118" - wire $eq$libresoc.v:146018$7256_Y - attribute \src "libresoc.v:146019.18-146019.118" - wire $eq$libresoc.v:146019$7257_Y - attribute \src "libresoc.v:146020.18-146020.118" - wire $eq$libresoc.v:146020$7258_Y - attribute \src "libresoc.v:146022.18-146022.118" - wire $eq$libresoc.v:146022$7260_Y - attribute \src "libresoc.v:146023.18-146023.118" - wire $eq$libresoc.v:146023$7261_Y - attribute \src "libresoc.v:146025.18-146025.118" - wire $eq$libresoc.v:146025$7263_Y - attribute \src "libresoc.v:146026.18-146026.118" - wire $eq$libresoc.v:146026$7264_Y - attribute \src "libresoc.v:146040.18-146040.107" - wire $ne$libresoc.v:146040$7278_Y - attribute \src "libresoc.v:146051.18-146051.107" - wire $ne$libresoc.v:146051$7289_Y - attribute \src "libresoc.v:146001.19-146001.100" - wire $not$libresoc.v:146001$7239_Y - attribute \src "libresoc.v:146005.19-146005.100" - wire $not$libresoc.v:146005$7243_Y - attribute \src "libresoc.v:146016.18-146016.110" - wire $not$libresoc.v:146016$7254_Y - attribute \src "libresoc.v:146029.18-146029.97" - wire width 64 $not$libresoc.v:146029$7267_Y - attribute \src "libresoc.v:146034.18-146034.99" - wire $not$libresoc.v:146034$7272_Y - attribute \src "libresoc.v:146037.18-146037.99" - wire $not$libresoc.v:146037$7275_Y - attribute \src "libresoc.v:146041.18-146041.99" - wire $not$libresoc.v:146041$7279_Y - attribute \src "libresoc.v:146042.18-146042.99" - wire $not$libresoc.v:146042$7280_Y - attribute \src "libresoc.v:146021.18-146021.104" - wire $or$libresoc.v:146021$7259_Y - attribute \src "libresoc.v:146024.18-146024.104" - wire $or$libresoc.v:146024$7262_Y - attribute \src "libresoc.v:146027.18-146027.104" - wire $or$libresoc.v:146027$7265_Y - attribute \src "libresoc.v:146038.18-146038.110" - wire $or$libresoc.v:146038$7276_Y - attribute \src "libresoc.v:146043.18-146043.110" - wire $or$libresoc.v:146043$7281_Y - attribute \src "libresoc.v:146046.18-146046.110" - wire $or$libresoc.v:146046$7284_Y - attribute \src "libresoc.v:146049.18-146049.110" - wire $or$libresoc.v:146049$7287_Y - attribute \src "libresoc.v:145992.18-145992.98" - wire $reduce_or$libresoc.v:145992$7230_Y - attribute \src "libresoc.v:145996.19-145996.99" - wire $reduce_or$libresoc.v:145996$7234_Y - attribute \src "libresoc.v:146033.18-146033.99" - wire $reduce_or$libresoc.v:146033$7271_Y - attribute \src "libresoc.v:146036.18-146036.99" - wire $reduce_or$libresoc.v:146036$7274_Y - attribute \src "libresoc.v:146045.18-146045.121" - wire $ternary$libresoc.v:146045$7283_Y - attribute \src "libresoc.v:146048.18-146048.119" - wire $ternary$libresoc.v:146048$7286_Y - attribute \src "libresoc.v:146052.18-146052.123" - wire $ternary$libresoc.v:146052$7290_Y - attribute \src "libresoc.v:145997.19-145997.111" - wire $xor$libresoc.v:145997$7235_Y - attribute \src "libresoc.v:145998.19-145998.111" - wire $xor$libresoc.v:145998$7236_Y - attribute \src "libresoc.v:145999.19-145999.110" - wire $xor$libresoc.v:145999$7237_Y - attribute \src "libresoc.v:146000.19-146000.110" - wire $xor$libresoc.v:146000$7238_Y - attribute \src "libresoc.v:146003.19-146003.110" - wire $xor$libresoc.v:146003$7241_Y - attribute \src "libresoc.v:146004.19-146004.110" - wire $xor$libresoc.v:146004$7242_Y - attribute \src "libresoc.v:146030.18-146030.111" - wire $xor$libresoc.v:146030$7268_Y - attribute \src "libresoc.v:146031.18-146031.107" - wire $xor$libresoc.v:146031$7269_Y - attribute \src "libresoc.v:146032.18-146032.113" - wire width 32 $xor$libresoc.v:146032$7270_Y - attribute \src "libresoc.v:146035.18-146035.115" - wire width 32 $xor$libresoc.v:146035$7273_Y + attribute \src "libresoc.v:147660.18-147660.105" + wire width 67 $add$libresoc.v:147660$7314_Y + attribute \src "libresoc.v:147634.19-147634.107" + wire $and$libresoc.v:147634$7288_Y + attribute \src "libresoc.v:147638.19-147638.107" + wire $and$libresoc.v:147638$7292_Y + attribute \src "libresoc.v:147671.18-147671.106" + wire $and$libresoc.v:147671$7325_Y + attribute \src "libresoc.v:147676.18-147676.106" + wire $and$libresoc.v:147676$7330_Y + attribute \src "libresoc.v:147679.18-147679.106" + wire $and$libresoc.v:147679$7333_Y + attribute \src "libresoc.v:147682.18-147682.106" + wire $and$libresoc.v:147682$7336_Y + attribute \src "libresoc.v:147625.19-147625.118" + wire $eq$libresoc.v:147625$7279_Y + attribute \src "libresoc.v:147626.19-147626.118" + wire $eq$libresoc.v:147626$7280_Y + attribute \src "libresoc.v:147627.19-147627.118" + wire $eq$libresoc.v:147627$7281_Y + attribute \src "libresoc.v:147639.19-147639.109" + wire $eq$libresoc.v:147639$7293_Y + attribute \src "libresoc.v:147640.19-147640.110" + wire $eq$libresoc.v:147640$7294_Y + attribute \src "libresoc.v:147641.19-147641.111" + wire $eq$libresoc.v:147641$7295_Y + attribute \src "libresoc.v:147642.19-147642.111" + wire $eq$libresoc.v:147642$7296_Y + attribute \src "libresoc.v:147643.19-147643.111" + wire $eq$libresoc.v:147643$7297_Y + attribute \src "libresoc.v:147644.19-147644.111" + wire $eq$libresoc.v:147644$7298_Y + attribute \src "libresoc.v:147645.19-147645.111" + wire $eq$libresoc.v:147645$7299_Y + attribute \src "libresoc.v:147646.19-147646.111" + wire $eq$libresoc.v:147646$7300_Y + attribute \src "libresoc.v:147647.18-147647.118" + wire $eq$libresoc.v:147647$7301_Y + attribute \src "libresoc.v:147649.18-147649.118" + wire $eq$libresoc.v:147649$7303_Y + attribute \src "libresoc.v:147650.18-147650.118" + wire $eq$libresoc.v:147650$7304_Y + attribute \src "libresoc.v:147651.18-147651.118" + wire $eq$libresoc.v:147651$7305_Y + attribute \src "libresoc.v:147652.18-147652.118" + wire $eq$libresoc.v:147652$7306_Y + attribute \src "libresoc.v:147654.18-147654.118" + wire $eq$libresoc.v:147654$7308_Y + attribute \src "libresoc.v:147655.18-147655.118" + wire $eq$libresoc.v:147655$7309_Y + attribute \src "libresoc.v:147657.18-147657.118" + wire $eq$libresoc.v:147657$7311_Y + attribute \src "libresoc.v:147658.18-147658.118" + wire $eq$libresoc.v:147658$7312_Y + attribute \src "libresoc.v:147672.18-147672.107" + wire $ne$libresoc.v:147672$7326_Y + attribute \src "libresoc.v:147683.18-147683.107" + wire $ne$libresoc.v:147683$7337_Y + attribute \src "libresoc.v:147633.19-147633.100" + wire $not$libresoc.v:147633$7287_Y + attribute \src "libresoc.v:147637.19-147637.100" + wire $not$libresoc.v:147637$7291_Y + attribute \src "libresoc.v:147648.18-147648.110" + wire $not$libresoc.v:147648$7302_Y + attribute \src "libresoc.v:147661.18-147661.97" + wire width 64 $not$libresoc.v:147661$7315_Y + attribute \src "libresoc.v:147666.18-147666.99" + wire $not$libresoc.v:147666$7320_Y + attribute \src "libresoc.v:147669.18-147669.99" + wire $not$libresoc.v:147669$7323_Y + attribute \src "libresoc.v:147673.18-147673.99" + wire $not$libresoc.v:147673$7327_Y + attribute \src "libresoc.v:147674.18-147674.99" + wire $not$libresoc.v:147674$7328_Y + attribute \src "libresoc.v:147653.18-147653.104" + wire $or$libresoc.v:147653$7307_Y + attribute \src "libresoc.v:147656.18-147656.104" + wire $or$libresoc.v:147656$7310_Y + attribute \src "libresoc.v:147659.18-147659.104" + wire $or$libresoc.v:147659$7313_Y + attribute \src "libresoc.v:147670.18-147670.110" + wire $or$libresoc.v:147670$7324_Y + attribute \src "libresoc.v:147675.18-147675.110" + wire $or$libresoc.v:147675$7329_Y + attribute \src "libresoc.v:147678.18-147678.110" + wire $or$libresoc.v:147678$7332_Y + attribute \src "libresoc.v:147681.18-147681.110" + wire $or$libresoc.v:147681$7335_Y + attribute \src "libresoc.v:147624.18-147624.98" + wire $reduce_or$libresoc.v:147624$7278_Y + attribute \src "libresoc.v:147628.19-147628.99" + wire $reduce_or$libresoc.v:147628$7282_Y + attribute \src "libresoc.v:147665.18-147665.99" + wire $reduce_or$libresoc.v:147665$7319_Y + attribute \src "libresoc.v:147668.18-147668.99" + wire $reduce_or$libresoc.v:147668$7322_Y + attribute \src "libresoc.v:147677.18-147677.121" + wire $ternary$libresoc.v:147677$7331_Y + attribute \src "libresoc.v:147680.18-147680.119" + wire $ternary$libresoc.v:147680$7334_Y + attribute \src "libresoc.v:147684.18-147684.123" + wire $ternary$libresoc.v:147684$7338_Y + attribute \src "libresoc.v:147629.19-147629.111" + wire $xor$libresoc.v:147629$7283_Y + attribute \src "libresoc.v:147630.19-147630.111" + wire $xor$libresoc.v:147630$7284_Y + attribute \src "libresoc.v:147631.19-147631.110" + wire $xor$libresoc.v:147631$7285_Y + attribute \src "libresoc.v:147632.19-147632.110" + wire $xor$libresoc.v:147632$7286_Y + attribute \src "libresoc.v:147635.19-147635.110" + wire $xor$libresoc.v:147635$7289_Y + attribute \src "libresoc.v:147636.19-147636.110" + wire $xor$libresoc.v:147636$7290_Y + attribute \src "libresoc.v:147662.18-147662.111" + wire $xor$libresoc.v:147662$7316_Y + attribute \src "libresoc.v:147663.18-147663.107" + wire $xor$libresoc.v:147663$7317_Y + attribute \src "libresoc.v:147664.18-147664.113" + wire width 32 $xor$libresoc.v:147664$7318_Y + attribute \src "libresoc.v:147667.18-147667.115" + wire width 32 $xor$libresoc.v:147667$7321_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -305613,7 +308110,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:145531.7-145531.15" + attribute \src "libresoc.v:147163.7-147163.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -305658,7 +308155,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:146028$7266 + cell $add $add$libresoc.v:147660$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -305666,10 +308163,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:146028$7266_Y + connect \Y $add$libresoc.v:147660$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:146002$7240 + cell $and $and$libresoc.v:147634$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305677,10 +308174,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:146002$7240_Y + connect \Y $and$libresoc.v:147634$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:146006$7244 + cell $and $and$libresoc.v:147638$7292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305688,10 +308185,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:146006$7244_Y + connect \Y $and$libresoc.v:147638$7292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146039$7277 + cell $and $and$libresoc.v:147671$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305699,10 +308196,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:146039$7277_Y + connect \Y $and$libresoc.v:147671$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146044$7282 + cell $and $and$libresoc.v:147676$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305710,10 +308207,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:146044$7282_Y + connect \Y $and$libresoc.v:147676$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146047$7285 + cell $and $and$libresoc.v:147679$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305721,10 +308218,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:146047$7285_Y + connect \Y $and$libresoc.v:147679$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:146050$7288 + cell $and $and$libresoc.v:147682$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305732,10 +308229,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:146050$7288_Y + connect \Y $and$libresoc.v:147682$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:145993$7231 + cell $eq $eq$libresoc.v:147625$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305743,10 +308240,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:145993$7231_Y + connect \Y $eq$libresoc.v:147625$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:145994$7232 + cell $eq $eq$libresoc.v:147626$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305754,10 +308251,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:145994$7232_Y + connect \Y $eq$libresoc.v:147626$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:145995$7233 + cell $eq $eq$libresoc.v:147627$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305765,10 +308262,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:145995$7233_Y + connect \Y $eq$libresoc.v:147627$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146007$7245 + cell $eq $eq$libresoc.v:147639$7293 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305776,10 +308273,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:146007$7245_Y + connect \Y $eq$libresoc.v:147639$7293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146008$7246 + cell $eq $eq$libresoc.v:147640$7294 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305787,10 +308284,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:146008$7246_Y + connect \Y $eq$libresoc.v:147640$7294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146009$7247 + cell $eq $eq$libresoc.v:147641$7295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305798,10 +308295,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:146009$7247_Y + connect \Y $eq$libresoc.v:147641$7295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146010$7248 + cell $eq $eq$libresoc.v:147642$7296 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305809,10 +308306,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:146010$7248_Y + connect \Y $eq$libresoc.v:147642$7296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146011$7249 + cell $eq $eq$libresoc.v:147643$7297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305820,10 +308317,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:146011$7249_Y + connect \Y $eq$libresoc.v:147643$7297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146012$7250 + cell $eq $eq$libresoc.v:147644$7298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305831,10 +308328,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:146012$7250_Y + connect \Y $eq$libresoc.v:147644$7298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146013$7251 + cell $eq $eq$libresoc.v:147645$7299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305842,10 +308339,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:146013$7251_Y + connect \Y $eq$libresoc.v:147645$7299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:146014$7252 + cell $eq $eq$libresoc.v:147646$7300 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305853,10 +308350,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:146014$7252_Y + connect \Y $eq$libresoc.v:147646$7300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:146015$7253 + cell $eq $eq$libresoc.v:147647$7301 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305864,10 +308361,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146015$7253_Y + connect \Y $eq$libresoc.v:147647$7301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:146017$7255 + cell $eq $eq$libresoc.v:147649$7303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305875,10 +308372,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146017$7255_Y + connect \Y $eq$libresoc.v:147649$7303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:146018$7256 + cell $eq $eq$libresoc.v:147650$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305886,10 +308383,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146018$7256_Y + connect \Y $eq$libresoc.v:147650$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146019$7257 + cell $eq $eq$libresoc.v:147651$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305897,10 +308394,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146019$7257_Y + connect \Y $eq$libresoc.v:147651$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146020$7258 + cell $eq $eq$libresoc.v:147652$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305908,10 +308405,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146020$7258_Y + connect \Y $eq$libresoc.v:147652$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146022$7260 + cell $eq $eq$libresoc.v:147654$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305919,10 +308416,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146022$7260_Y + connect \Y $eq$libresoc.v:147654$7308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146023$7261 + cell $eq $eq$libresoc.v:147655$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305930,10 +308427,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146023$7261_Y + connect \Y $eq$libresoc.v:147655$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:146025$7263 + cell $eq $eq$libresoc.v:147657$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305941,10 +308438,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:146025$7263_Y + connect \Y $eq$libresoc.v:147657$7311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:146026$7264 + cell $eq $eq$libresoc.v:147658$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305952,10 +308449,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:146026$7264_Y + connect \Y $eq$libresoc.v:147658$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:146040$7278 + cell $ne $ne$libresoc.v:147672$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305963,10 +308460,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:146040$7278_Y + connect \Y $ne$libresoc.v:147672$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:146051$7289 + cell $ne $ne$libresoc.v:147683$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305974,74 +308471,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:146051$7289_Y + connect \Y $ne$libresoc.v:147683$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:146001$7239 + cell $not $not$libresoc.v:147633$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:146001$7239_Y + connect \Y $not$libresoc.v:147633$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:146005$7243 + cell $not $not$libresoc.v:147637$7291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:146005$7243_Y + connect \Y $not$libresoc.v:147637$7291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:146016$7254 + cell $not $not$libresoc.v:147648$7302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:146016$7254_Y + connect \Y $not$libresoc.v:147648$7302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:146029$7267 + cell $not $not$libresoc.v:147661$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:146029$7267_Y + connect \Y $not$libresoc.v:147661$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:146034$7272 + cell $not $not$libresoc.v:147666$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:146034$7272_Y + connect \Y $not$libresoc.v:147666$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:146037$7275 + cell $not $not$libresoc.v:147669$7323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:146037$7275_Y + connect \Y $not$libresoc.v:147669$7323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:146041$7279 + cell $not $not$libresoc.v:147673$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:146041$7279_Y + connect \Y $not$libresoc.v:147673$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:146042$7280 + cell $not $not$libresoc.v:147674$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:146042$7280_Y + connect \Y $not$libresoc.v:147674$7328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146021$7259 + cell $or $or$libresoc.v:147653$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306049,10 +308546,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:146021$7259_Y + connect \Y $or$libresoc.v:147653$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146024$7262 + cell $or $or$libresoc.v:147656$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306060,10 +308557,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:146024$7262_Y + connect \Y $or$libresoc.v:147656$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:146027$7265 + cell $or $or$libresoc.v:147659$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306071,10 +308568,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:146027$7265_Y + connect \Y $or$libresoc.v:147659$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146038$7276 + cell $or $or$libresoc.v:147670$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306082,10 +308579,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146038$7276_Y + connect \Y $or$libresoc.v:147670$7324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146043$7281 + cell $or $or$libresoc.v:147675$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306093,10 +308590,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146043$7281_Y + connect \Y $or$libresoc.v:147675$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146046$7284 + cell $or $or$libresoc.v:147678$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306104,10 +308601,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146046$7284_Y + connect \Y $or$libresoc.v:147678$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:146049$7287 + cell $or $or$libresoc.v:147681$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306115,66 +308612,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:146049$7287_Y + connect \Y $or$libresoc.v:147681$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:145992$7230 + cell $reduce_or $reduce_or$libresoc.v:147624$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:145992$7230_Y + connect \Y $reduce_or$libresoc.v:147624$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:145996$7234 + cell $reduce_or $reduce_or$libresoc.v:147628$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:145996$7234_Y + connect \Y $reduce_or$libresoc.v:147628$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:146033$7271 + cell $reduce_or $reduce_or$libresoc.v:147665$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:146033$7271_Y + connect \Y $reduce_or$libresoc.v:147665$7319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:146036$7274 + cell $reduce_or $reduce_or$libresoc.v:147668$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:146036$7274_Y + connect \Y $reduce_or$libresoc.v:147668$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:146045$7283 + cell $mux $ternary$libresoc.v:147677$7331 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:146045$7283_Y + connect \Y $ternary$libresoc.v:147677$7331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:146048$7286 + cell $mux $ternary$libresoc.v:147680$7334 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:146048$7286_Y + connect \Y $ternary$libresoc.v:147680$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:146052$7290 + cell $mux $ternary$libresoc.v:147684$7338 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:146052$7290_Y + connect \Y $ternary$libresoc.v:147684$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:145997$7235 + cell $xor $xor$libresoc.v:147629$7283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306182,10 +308679,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:145997$7235_Y + connect \Y $xor$libresoc.v:147629$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:145998$7236 + cell $xor $xor$libresoc.v:147630$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306193,10 +308690,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:145998$7236_Y + connect \Y $xor$libresoc.v:147630$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:145999$7237 + cell $xor $xor$libresoc.v:147631$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306204,10 +308701,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:145999$7237_Y + connect \Y $xor$libresoc.v:147631$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146000$7238 + cell $xor $xor$libresoc.v:147632$7286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306215,10 +308712,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:146000$7238_Y + connect \Y $xor$libresoc.v:147632$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146003$7241 + cell $xor $xor$libresoc.v:147635$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306226,10 +308723,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:146003$7241_Y + connect \Y $xor$libresoc.v:147635$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:146004$7242 + cell $xor $xor$libresoc.v:147636$7290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306237,10 +308734,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:146004$7242_Y + connect \Y $xor$libresoc.v:147636$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:146030$7268 + cell $xor $xor$libresoc.v:147662$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306248,10 +308745,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:146030$7268_Y + connect \Y $xor$libresoc.v:147662$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:146031$7269 + cell $xor $xor$libresoc.v:147663$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306259,10 +308756,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:146031$7269_Y + connect \Y $xor$libresoc.v:147663$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:146032$7270 + cell $xor $xor$libresoc.v:147664$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -306270,10 +308767,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:146032$7270_Y + connect \Y $xor$libresoc.v:147664$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:146035$7273 + cell $xor $xor$libresoc.v:147667$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -306281,24 +308778,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:146035$7273_Y + connect \Y $xor$libresoc.v:147667$7321_Y end - attribute \src "libresoc.v:145531.7-145531.20" - process $proc$libresoc.v:145531$7320 + attribute \src "libresoc.v:147163.7-147163.20" + process $proc$libresoc.v:147163$7368 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146053.3-146062.6" - process $proc$libresoc.v:146053$7291 + attribute \src "libresoc.v:147685.3-147694.6" + process $proc$libresoc.v:147685$7339 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:146054.5-146054.29" + attribute \src "libresoc.v:147686.5-147686.29" switch \initial - attribute \src "libresoc.v:146054.9-146054.17" + attribute \src "libresoc.v:147686.9-147686.17" case 1'1 case end @@ -306314,13 +308811,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:146063.3-146085.6" - process $proc$libresoc.v:146063$7292 + attribute \src "libresoc.v:147695.3-147717.6" + process $proc$libresoc.v:147695$7340 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:146064.5-146064.29" + attribute \src "libresoc.v:147696.5-147696.29" switch \initial - attribute \src "libresoc.v:146064.9-146064.17" + attribute \src "libresoc.v:147696.9-147696.17" case 1'1 case end @@ -306353,14 +308850,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:146086.3-146096.6" - process $proc$libresoc.v:146086$7293 + attribute \src "libresoc.v:147718.3-147728.6" + process $proc$libresoc.v:147718$7341 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:146087.5-146087.29" + attribute \src "libresoc.v:147719.5-147719.29" switch \initial - attribute \src "libresoc.v:146087.9-146087.17" + attribute \src "libresoc.v:147719.9-147719.17" case 1'1 case end @@ -306376,14 +308873,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:146097.3-146123.6" - process $proc$libresoc.v:146097$7294 + attribute \src "libresoc.v:147729.3-147755.6" + process $proc$libresoc.v:147729$7342 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:146098.5-146098.29" + attribute \src "libresoc.v:147730.5-147730.29" switch \initial - attribute \src "libresoc.v:146098.9-146098.17" + attribute \src "libresoc.v:147730.9-147730.17" case 1'1 case end @@ -306421,14 +308918,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:146124.3-146142.6" - process $proc$libresoc.v:146124$7295 + attribute \src "libresoc.v:147756.3-147774.6" + process $proc$libresoc.v:147756$7343 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:146125.5-146125.29" + attribute \src "libresoc.v:147757.5-147757.29" switch \initial - attribute \src "libresoc.v:146125.9-146125.17" + attribute \src "libresoc.v:147757.9-147757.17" case 1'1 case end @@ -306454,14 +308951,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:146143.3-146161.6" - process $proc$libresoc.v:146143$7296 + attribute \src "libresoc.v:147775.3-147793.6" + process $proc$libresoc.v:147775$7344 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:146144.5-146144.29" + attribute \src "libresoc.v:147776.5-147776.29" switch \initial - attribute \src "libresoc.v:146144.9-146144.17" + attribute \src "libresoc.v:147776.9-147776.17" case 1'1 case end @@ -306487,14 +308984,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:146162.3-146188.6" - process $proc$libresoc.v:146162$7297 + attribute \src "libresoc.v:147794.3-147820.6" + process $proc$libresoc.v:147794$7345 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:146163.5-146163.29" + attribute \src "libresoc.v:147795.5-147795.29" switch \initial - attribute \src "libresoc.v:146163.9-146163.17" + attribute \src "libresoc.v:147795.9-147795.17" case 1'1 case end @@ -306530,14 +309027,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:146189.3-146214.6" - process $proc$libresoc.v:146189$7298 + attribute \src "libresoc.v:147821.3-147846.6" + process $proc$libresoc.v:147821$7346 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:146190.5-146190.29" + attribute \src "libresoc.v:147822.5-147822.29" switch \initial - attribute \src "libresoc.v:146190.9-146190.17" + attribute \src "libresoc.v:147822.9-147822.17" case 1'1 case end @@ -306569,14 +309066,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:146215.3-146229.6" - process $proc$libresoc.v:146215$7299 + attribute \src "libresoc.v:147847.3-147861.6" + process $proc$libresoc.v:147847$7347 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:146216.5-146216.29" + attribute \src "libresoc.v:147848.5-147848.29" switch \initial - attribute \src "libresoc.v:146216.9-146216.17" + attribute \src "libresoc.v:147848.9-147848.17" case 1'1 case end @@ -306596,14 +309093,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:146230.3-146267.6" - process $proc$libresoc.v:146230$7300 + attribute \src "libresoc.v:147862.3-147899.6" + process $proc$libresoc.v:147862$7348 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:146231.5-146231.29" + attribute \src "libresoc.v:147863.5-147863.29" switch \initial - attribute \src "libresoc.v:146231.9-146231.17" + attribute \src "libresoc.v:147863.9-147863.17" case 1'1 case end @@ -306656,14 +309153,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:146268.3-146286.6" - process $proc$libresoc.v:146268$7301 + attribute \src "libresoc.v:147900.3-147918.6" + process $proc$libresoc.v:147900$7349 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:146269.5-146269.29" + attribute \src "libresoc.v:147901.5-147901.29" switch \initial - attribute \src "libresoc.v:146269.9-146269.17" + attribute \src "libresoc.v:147901.9-147901.17" case 1'1 case end @@ -306687,14 +309184,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:146287.3-146300.6" - process $proc$libresoc.v:146287$7302 + attribute \src "libresoc.v:147919.3-147932.6" + process $proc$libresoc.v:147919$7350 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:146288.5-146288.29" + attribute \src "libresoc.v:147920.5-147920.29" switch \initial - attribute \src "libresoc.v:146288.9-146288.17" + attribute \src "libresoc.v:147920.9-147920.17" case 1'1 case end @@ -306711,13 +309208,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:146301.3-146323.6" - process $proc$libresoc.v:146301$7303 + attribute \src "libresoc.v:147933.3-147955.6" + process $proc$libresoc.v:147933$7351 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:146302.5-146302.29" + attribute \src "libresoc.v:147934.5-147934.29" switch \initial - attribute \src "libresoc.v:146302.9-146302.17" + attribute \src "libresoc.v:147934.9-147934.17" case 1'1 case end @@ -306750,14 +309247,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:146324.3-146334.6" - process $proc$libresoc.v:146324$7304 + attribute \src "libresoc.v:147956.3-147966.6" + process $proc$libresoc.v:147956$7352 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$7305 $1\xer_ca$20[1:0]$7306 - attribute \src "libresoc.v:146325.5-146325.29" + assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 + attribute \src "libresoc.v:147957.5-147957.29" switch \initial - attribute \src "libresoc.v:146325.9-146325.17" + attribute \src "libresoc.v:147957.9-147957.17" case 1'1 case end @@ -306766,21 +309263,21 @@ module \main attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$7306 \ca + assign $1\xer_ca$20[1:0]$7354 \ca case - assign $1\xer_ca$20[1:0]$7306 2'00 + assign $1\xer_ca$20[1:0]$7354 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7305 + update \xer_ca$20 $0\xer_ca$20[1:0]$7353 end - attribute \src "libresoc.v:146335.3-146345.6" - process $proc$libresoc.v:146335$7307 + attribute \src "libresoc.v:147967.3-147977.6" + process $proc$libresoc.v:147967$7355 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:146336.5-146336.29" + attribute \src "libresoc.v:147968.5-147968.29" switch \initial - attribute \src "libresoc.v:146336.9-146336.17" + attribute \src "libresoc.v:147968.9-147968.17" case 1'1 case end @@ -306796,14 +309293,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:146346.3-146359.6" - process $proc$libresoc.v:146346$7308 + attribute \src "libresoc.v:147978.3-147991.6" + process $proc$libresoc.v:147978$7356 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:146347.5-146347.29" + attribute \src "libresoc.v:147979.5-147979.29" switch \initial - attribute \src "libresoc.v:146347.9-146347.17" + attribute \src "libresoc.v:147979.9-147979.17" case 1'1 case end @@ -306820,14 +309317,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:146360.3-146370.6" - process $proc$libresoc.v:146360$7309 + attribute \src "libresoc.v:147992.3-148002.6" + process $proc$libresoc.v:147992$7357 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:146361.5-146361.29" + attribute \src "libresoc.v:147993.5-147993.29" switch \initial - attribute \src "libresoc.v:146361.9-146361.17" + attribute \src "libresoc.v:147993.9-147993.17" case 1'1 case end @@ -306843,14 +309340,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:146371.3-146381.6" - process $proc$libresoc.v:146371$7310 + attribute \src "libresoc.v:148003.3-148013.6" + process $proc$libresoc.v:148003$7358 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146372.5-146372.29" + attribute \src "libresoc.v:148004.5-148004.29" switch \initial - attribute \src "libresoc.v:146372.9-146372.17" + attribute \src "libresoc.v:148004.9-148004.17" case 1'1 case end @@ -306866,14 +309363,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:146382.3-146392.6" - process $proc$libresoc.v:146382$7311 + attribute \src "libresoc.v:148014.3-148024.6" + process $proc$libresoc.v:148014$7359 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:146383.5-146383.29" + attribute \src "libresoc.v:148015.5-148015.29" switch \initial - attribute \src "libresoc.v:146383.9-146383.17" + attribute \src "libresoc.v:148015.9-148015.17" case 1'1 case end @@ -306889,14 +309386,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:146393.3-146412.6" - process $proc$libresoc.v:146393$7312 + attribute \src "libresoc.v:148025.3-148044.6" + process $proc$libresoc.v:148025$7360 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:146394.5-146394.29" + attribute \src "libresoc.v:148026.5-148026.29" switch \initial - attribute \src "libresoc.v:146394.9-146394.17" + attribute \src "libresoc.v:148026.9-148026.17" case 1'1 case end @@ -306919,14 +309416,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:146413.3-146422.6" - process $proc$libresoc.v:146413$7313 + attribute \src "libresoc.v:148045.3-148054.6" + process $proc$libresoc.v:148045$7361 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:146414.5-146414.29" + attribute \src "libresoc.v:148046.5-148046.29" switch \initial - attribute \src "libresoc.v:146414.9-146414.17" + attribute \src "libresoc.v:148046.9-148046.17" case 1'1 case end @@ -306942,14 +309439,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:146423.3-146432.6" - process $proc$libresoc.v:146423$7314 + attribute \src "libresoc.v:148055.3-148064.6" + process $proc$libresoc.v:148055$7362 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:146424.5-146424.29" + attribute \src "libresoc.v:148056.5-148056.29" switch \initial - attribute \src "libresoc.v:146424.9-146424.17" + attribute \src "libresoc.v:148056.9-148056.17" case 1'1 case end @@ -306965,14 +309462,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:146433.3-146442.6" - process $proc$libresoc.v:146433$7315 + attribute \src "libresoc.v:148065.3-148074.6" + process $proc$libresoc.v:148065$7363 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:146434.5-146434.29" + attribute \src "libresoc.v:148066.5-148066.29" switch \initial - attribute \src "libresoc.v:146434.9-146434.17" + attribute \src "libresoc.v:148066.9-148066.17" case 1'1 case end @@ -306988,14 +309485,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:146443.3-146453.6" - process $proc$libresoc.v:146443$7316 + attribute \src "libresoc.v:148075.3-148085.6" + process $proc$libresoc.v:148075$7364 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:146444.5-146444.29" + attribute \src "libresoc.v:148076.5-148076.29" switch \initial - attribute \src "libresoc.v:146444.9-146444.17" + attribute \src "libresoc.v:148076.9-148076.17" case 1'1 case end @@ -307011,14 +309508,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:146454.3-146464.6" - process $proc$libresoc.v:146454$7317 + attribute \src "libresoc.v:148086.3-148096.6" + process $proc$libresoc.v:148086$7365 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:146455.5-146455.29" + attribute \src "libresoc.v:148087.5-148087.29" switch \initial - attribute \src "libresoc.v:146455.9-146455.17" + attribute \src "libresoc.v:148087.9-148087.17" case 1'1 case end @@ -307034,14 +309531,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:146465.3-146475.6" - process $proc$libresoc.v:146465$7318 + attribute \src "libresoc.v:148097.3-148107.6" + process $proc$libresoc.v:148097$7366 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:146466.5-146466.29" + attribute \src "libresoc.v:148098.5-148098.29" switch \initial - attribute \src "libresoc.v:146466.9-146466.17" + attribute \src "libresoc.v:148098.9-148098.17" case 1'1 case end @@ -307057,14 +309554,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:146476.3-146486.6" - process $proc$libresoc.v:146476$7319 + attribute \src "libresoc.v:148108.3-148118.6" + process $proc$libresoc.v:148108$7367 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:146477.5-146477.29" + attribute \src "libresoc.v:148109.5-148109.29" switch \initial - attribute \src "libresoc.v:146477.9-146477.17" + attribute \src "libresoc.v:148109.9-148109.17" case 1'1 case end @@ -307080,88 +309577,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:145992$7230_Y - connect \$101 $eq$libresoc.v:145993$7231_Y - connect \$103 $eq$libresoc.v:145994$7232_Y - connect \$105 $eq$libresoc.v:145995$7233_Y - connect \$107 $reduce_or$libresoc.v:145996$7234_Y - connect \$109 $xor$libresoc.v:145997$7235_Y - connect \$111 $xor$libresoc.v:145998$7236_Y - connect \$113 $xor$libresoc.v:145999$7237_Y - connect \$116 $xor$libresoc.v:146000$7238_Y - connect \$115 $not$libresoc.v:146001$7239_Y - connect \$119 $and$libresoc.v:146002$7240_Y - connect \$121 $xor$libresoc.v:146003$7241_Y - connect \$124 $xor$libresoc.v:146004$7242_Y - connect \$123 $not$libresoc.v:146005$7243_Y - connect \$127 $and$libresoc.v:146006$7244_Y - connect \$129 $eq$libresoc.v:146007$7245_Y - connect \$131 $eq$libresoc.v:146008$7246_Y - connect \$133 $eq$libresoc.v:146009$7247_Y - connect \$135 $eq$libresoc.v:146010$7248_Y - connect \$137 $eq$libresoc.v:146011$7249_Y - connect \$139 $eq$libresoc.v:146012$7250_Y - connect \$141 $eq$libresoc.v:146013$7251_Y - connect \$143 $eq$libresoc.v:146014$7252_Y - connect \$22 $eq$libresoc.v:146015$7253_Y - connect \$24 $not$libresoc.v:146016$7254_Y - connect \$26 $eq$libresoc.v:146017$7255_Y - connect \$28 $eq$libresoc.v:146018$7256_Y - connect \$30 $eq$libresoc.v:146019$7257_Y - connect \$32 $eq$libresoc.v:146020$7258_Y - connect \$34 $or$libresoc.v:146021$7259_Y - connect \$36 $eq$libresoc.v:146022$7260_Y - connect \$38 $eq$libresoc.v:146023$7261_Y - connect \$40 $or$libresoc.v:146024$7262_Y - connect \$42 $eq$libresoc.v:146025$7263_Y - connect \$44 $eq$libresoc.v:146026$7264_Y - connect \$46 $or$libresoc.v:146027$7265_Y - connect \$49 $add$libresoc.v:146028$7266_Y - connect \$51 $not$libresoc.v:146029$7267_Y - connect \$53 $xor$libresoc.v:146030$7268_Y - connect \$55 $xor$libresoc.v:146031$7269_Y - connect \$59 $xor$libresoc.v:146032$7270_Y - connect \$58 $reduce_or$libresoc.v:146033$7271_Y - connect \$57 $not$libresoc.v:146034$7272_Y - connect \$65 $xor$libresoc.v:146035$7273_Y - connect \$64 $reduce_or$libresoc.v:146036$7274_Y - connect \$63 $not$libresoc.v:146037$7275_Y - connect \$69 $or$libresoc.v:146038$7276_Y - connect \$71 $and$libresoc.v:146039$7277_Y - connect \$73 $ne$libresoc.v:146040$7278_Y - connect \$75 $not$libresoc.v:146041$7279_Y - connect \$77 $not$libresoc.v:146042$7280_Y - connect \$79 $or$libresoc.v:146043$7281_Y - connect \$81 $and$libresoc.v:146044$7282_Y - connect \$83 $ternary$libresoc.v:146045$7283_Y - connect \$85 $or$libresoc.v:146046$7284_Y - connect \$87 $and$libresoc.v:146047$7285_Y - connect \$89 $ternary$libresoc.v:146048$7286_Y - connect \$91 $or$libresoc.v:146049$7287_Y - connect \$93 $and$libresoc.v:146050$7288_Y - connect \$95 $ne$libresoc.v:146051$7289_Y - connect \$97 $ternary$libresoc.v:146052$7290_Y + connect \$99 $reduce_or$libresoc.v:147624$7278_Y + connect \$101 $eq$libresoc.v:147625$7279_Y + connect \$103 $eq$libresoc.v:147626$7280_Y + connect \$105 $eq$libresoc.v:147627$7281_Y + connect \$107 $reduce_or$libresoc.v:147628$7282_Y + connect \$109 $xor$libresoc.v:147629$7283_Y + connect \$111 $xor$libresoc.v:147630$7284_Y + connect \$113 $xor$libresoc.v:147631$7285_Y + connect \$116 $xor$libresoc.v:147632$7286_Y + connect \$115 $not$libresoc.v:147633$7287_Y + connect \$119 $and$libresoc.v:147634$7288_Y + connect \$121 $xor$libresoc.v:147635$7289_Y + connect \$124 $xor$libresoc.v:147636$7290_Y + connect \$123 $not$libresoc.v:147637$7291_Y + connect \$127 $and$libresoc.v:147638$7292_Y + connect \$129 $eq$libresoc.v:147639$7293_Y + connect \$131 $eq$libresoc.v:147640$7294_Y + connect \$133 $eq$libresoc.v:147641$7295_Y + connect \$135 $eq$libresoc.v:147642$7296_Y + connect \$137 $eq$libresoc.v:147643$7297_Y + connect \$139 $eq$libresoc.v:147644$7298_Y + connect \$141 $eq$libresoc.v:147645$7299_Y + connect \$143 $eq$libresoc.v:147646$7300_Y + connect \$22 $eq$libresoc.v:147647$7301_Y + connect \$24 $not$libresoc.v:147648$7302_Y + connect \$26 $eq$libresoc.v:147649$7303_Y + connect \$28 $eq$libresoc.v:147650$7304_Y + connect \$30 $eq$libresoc.v:147651$7305_Y + connect \$32 $eq$libresoc.v:147652$7306_Y + connect \$34 $or$libresoc.v:147653$7307_Y + connect \$36 $eq$libresoc.v:147654$7308_Y + connect \$38 $eq$libresoc.v:147655$7309_Y + connect \$40 $or$libresoc.v:147656$7310_Y + connect \$42 $eq$libresoc.v:147657$7311_Y + connect \$44 $eq$libresoc.v:147658$7312_Y + connect \$46 $or$libresoc.v:147659$7313_Y + connect \$49 $add$libresoc.v:147660$7314_Y + connect \$51 $not$libresoc.v:147661$7315_Y + connect \$53 $xor$libresoc.v:147662$7316_Y + connect \$55 $xor$libresoc.v:147663$7317_Y + connect \$59 $xor$libresoc.v:147664$7318_Y + connect \$58 $reduce_or$libresoc.v:147665$7319_Y + connect \$57 $not$libresoc.v:147666$7320_Y + connect \$65 $xor$libresoc.v:147667$7321_Y + connect \$64 $reduce_or$libresoc.v:147668$7322_Y + connect \$63 $not$libresoc.v:147669$7323_Y + connect \$69 $or$libresoc.v:147670$7324_Y + connect \$71 $and$libresoc.v:147671$7325_Y + connect \$73 $ne$libresoc.v:147672$7326_Y + connect \$75 $not$libresoc.v:147673$7327_Y + connect \$77 $not$libresoc.v:147674$7328_Y + connect \$79 $or$libresoc.v:147675$7329_Y + connect \$81 $and$libresoc.v:147676$7330_Y + connect \$83 $ternary$libresoc.v:147677$7331_Y + connect \$85 $or$libresoc.v:147678$7332_Y + connect \$87 $and$libresoc.v:147679$7333_Y + connect \$89 $ternary$libresoc.v:147680$7334_Y + connect \$91 $or$libresoc.v:147681$7335_Y + connect \$93 $and$libresoc.v:147682$7336_Y + connect \$95 $ne$libresoc.v:147683$7337_Y + connect \$97 $ternary$libresoc.v:147684$7338_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:146495.1-146909.10" +attribute \src "libresoc.v:148127.1-148541.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:146496.7-146496.20" + attribute \src "libresoc.v:148128.7-148128.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146861.3-146891.6" + attribute \src "libresoc.v:148493.3-148523.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:146826.3-146860.6" + attribute \src "libresoc.v:148458.3-148492.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:146861.3-146891.6" + attribute \src "libresoc.v:148493.3-148523.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:146826.3-146860.6" + attribute \src "libresoc.v:148458.3-148492.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:146496.7-146496.15" + attribute \src "libresoc.v:148128.7-148128.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -307476,7 +309973,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:146810.11-146825.4" + attribute \src "libresoc.v:148442.11-148457.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -307493,22 +309990,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:146496.7-146496.20" - process $proc$libresoc.v:146496$7323 + attribute \src "libresoc.v:148128.7-148128.20" + process $proc$libresoc.v:148128$7371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146826.3-146860.6" - process $proc$libresoc.v:146826$7321 + attribute \src "libresoc.v:148458.3-148492.6" + process $proc$libresoc.v:148458$7369 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:146827.5-146827.29" + attribute \src "libresoc.v:148459.5-148459.29" switch \initial - attribute \src "libresoc.v:146827.9-146827.17" + attribute \src "libresoc.v:148459.9-148459.17" case 1'1 case end @@ -307540,14 +310037,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:146861.3-146891.6" - process $proc$libresoc.v:146861$7322 + attribute \src "libresoc.v:148493.3-148523.6" + process $proc$libresoc.v:148493$7370 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:146862.5-146862.29" + attribute \src "libresoc.v:148494.5-148494.29" switch \initial - attribute \src "libresoc.v:146862.9-146862.17" + attribute \src "libresoc.v:148494.9-148494.17" case 1'1 case end @@ -307601,109 +310098,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:146913.1-147449.10" +attribute \src "libresoc.v:148545.1-149081.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:147235.3-147246.6" + attribute \src "libresoc.v:148867.3-148878.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:147274.3-147292.6" + attribute \src "libresoc.v:148906.3-148924.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:147328.3-147342.6" + attribute \src "libresoc.v:148960.3-148974.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:147380.3-147392.6" + attribute \src "libresoc.v:149012.3-149024.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:147343.3-147355.6" + attribute \src "libresoc.v:148975.3-148987.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:147427.3-147439.6" + attribute \src "libresoc.v:149059.3-149071.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147393.3-147405.6" - wire width 64 $0\fast1$10[63:0]$7356 - attribute \src "libresoc.v:147293.3-147307.6" + attribute \src "libresoc.v:149025.3-149037.6" + wire width 64 $0\fast1$10[63:0]$7404 + attribute \src "libresoc.v:148925.3-148939.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:147308.3-147317.6" - wire width 64 $0\fast2$11[63:0]$7348 - attribute \src "libresoc.v:147318.3-147327.6" + attribute \src "libresoc.v:148940.3-148949.6" + wire width 64 $0\fast2$11[63:0]$7396 + attribute \src "libresoc.v:148950.3-148959.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:146914.7-146914.20" + attribute \src "libresoc.v:148546.7-148546.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:147235.3-147246.6" + attribute \src "libresoc.v:148867.3-148878.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:147274.3-147292.6" + attribute \src "libresoc.v:148906.3-148924.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:147328.3-147342.6" + attribute \src "libresoc.v:148960.3-148974.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:147380.3-147392.6" + attribute \src "libresoc.v:149012.3-149024.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:147343.3-147355.6" + attribute \src "libresoc.v:148975.3-148987.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:147427.3-147439.6" + attribute \src "libresoc.v:149059.3-149071.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147393.3-147405.6" - wire width 64 $1\fast1$10[63:0]$7357 - attribute \src "libresoc.v:147293.3-147307.6" + attribute \src "libresoc.v:149025.3-149037.6" + wire width 64 $1\fast1$10[63:0]$7405 + attribute \src "libresoc.v:148925.3-148939.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:147308.3-147317.6" - wire width 64 $1\fast2$11[63:0]$7349 - attribute \src "libresoc.v:147318.3-147327.6" + attribute \src "libresoc.v:148940.3-148949.6" + wire width 64 $1\fast2$11[63:0]$7397 + attribute \src "libresoc.v:148950.3-148959.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:147356.3-147379.6" + attribute \src "libresoc.v:148988.3-149011.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:147247.3-147273.6" + attribute \src "libresoc.v:148879.3-148905.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:147406.3-147426.6" + attribute \src "libresoc.v:149038.3-149058.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:147219.18-147219.119" - wire width 65 $add$libresoc.v:147219$7326_Y - attribute \src "libresoc.v:147234.18-147234.113" - wire width 65 $add$libresoc.v:147234$7342_Y - attribute \src "libresoc.v:147226.18-147226.115" - wire $and$libresoc.v:147226$7333_Y - attribute \src "libresoc.v:147227.18-147227.117" - wire $and$libresoc.v:147227$7334_Y - attribute \src "libresoc.v:147233.18-147233.118" - wire $and$libresoc.v:147233$7341_Y - attribute \src "libresoc.v:147217.18-147217.120" - wire $eq$libresoc.v:147217$7324_Y - attribute \src "libresoc.v:147220.18-147220.111" - wire $eq$libresoc.v:147220$7327_Y - attribute \src "libresoc.v:147222.18-147222.111" - wire $eq$libresoc.v:147222$7329_Y - attribute \src "libresoc.v:147223.18-147223.111" - wire $eq$libresoc.v:147223$7330_Y - attribute \src "libresoc.v:147224.18-147224.109" - wire $eq$libresoc.v:147224$7331_Y - attribute \src "libresoc.v:147229.18-147229.98" - wire width 64 $extend$libresoc.v:147229$7336_Y - attribute \src "libresoc.v:147225.18-147225.104" - wire $not$libresoc.v:147225$7332_Y - attribute \src "libresoc.v:147232.18-147232.112" - wire $not$libresoc.v:147232$7340_Y - attribute \src "libresoc.v:147218.18-147218.116" - wire $or$libresoc.v:147218$7325_Y - attribute \src "libresoc.v:147221.18-147221.109" - wire $or$libresoc.v:147221$7328_Y - attribute \src "libresoc.v:147229.18-147229.98" - wire width 64 $pos$libresoc.v:147229$7337_Y - attribute \src "libresoc.v:147230.18-147230.103" - wire $reduce_or$libresoc.v:147230$7338_Y - attribute \src "libresoc.v:147228.18-147228.108" - wire width 65 $sub$libresoc.v:147228$7335_Y - attribute \src "libresoc.v:147231.18-147231.108" - wire $xor$libresoc.v:147231$7339_Y + attribute \src "libresoc.v:148851.18-148851.119" + wire width 65 $add$libresoc.v:148851$7374_Y + attribute \src "libresoc.v:148866.18-148866.113" + wire width 65 $add$libresoc.v:148866$7390_Y + attribute \src "libresoc.v:148858.18-148858.115" + wire $and$libresoc.v:148858$7381_Y + attribute \src "libresoc.v:148859.18-148859.117" + wire $and$libresoc.v:148859$7382_Y + attribute \src "libresoc.v:148865.18-148865.118" + wire $and$libresoc.v:148865$7389_Y + attribute \src "libresoc.v:148849.18-148849.120" + wire $eq$libresoc.v:148849$7372_Y + attribute \src "libresoc.v:148852.18-148852.111" + wire $eq$libresoc.v:148852$7375_Y + attribute \src "libresoc.v:148854.18-148854.111" + wire $eq$libresoc.v:148854$7377_Y + attribute \src "libresoc.v:148855.18-148855.111" + wire $eq$libresoc.v:148855$7378_Y + attribute \src "libresoc.v:148856.18-148856.109" + wire $eq$libresoc.v:148856$7379_Y + attribute \src "libresoc.v:148861.18-148861.98" + wire width 64 $extend$libresoc.v:148861$7384_Y + attribute \src "libresoc.v:148857.18-148857.104" + wire $not$libresoc.v:148857$7380_Y + attribute \src "libresoc.v:148864.18-148864.112" + wire $not$libresoc.v:148864$7388_Y + attribute \src "libresoc.v:148850.18-148850.116" + wire $or$libresoc.v:148850$7373_Y + attribute \src "libresoc.v:148853.18-148853.109" + wire $or$libresoc.v:148853$7376_Y + attribute \src "libresoc.v:148861.18-148861.98" + wire width 64 $pos$libresoc.v:148861$7385_Y + attribute \src "libresoc.v:148862.18-148862.103" + wire $reduce_or$libresoc.v:148862$7386_Y + attribute \src "libresoc.v:148860.18-148860.108" + wire width 65 $sub$libresoc.v:148860$7383_Y + attribute \src "libresoc.v:148863.18-148863.108" + wire $xor$libresoc.v:148863$7387_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -307994,7 +310491,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:146914.7-146914.15" + attribute \src "libresoc.v:148546.7-148546.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -308005,7 +310502,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:147219$7326 + cell $add $add$libresoc.v:148851$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308013,10 +310510,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:147219$7326_Y + connect \Y $add$libresoc.v:148851$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:147234$7342 + cell $add $add$libresoc.v:148866$7390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308024,10 +310521,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:147234$7342_Y + connect \Y $add$libresoc.v:148866$7390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:147226$7333 + cell $and $and$libresoc.v:148858$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308035,10 +310532,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:147226$7333_Y + connect \Y $and$libresoc.v:148858$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:147227$7334 + cell $and $and$libresoc.v:148859$7382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308046,10 +310543,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:147227$7334_Y + connect \Y $and$libresoc.v:148859$7382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:147233$7341 + cell $and $and$libresoc.v:148865$7389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308057,10 +310554,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:147233$7341_Y + connect \Y $and$libresoc.v:148865$7389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:147217$7324 + cell $eq $eq$libresoc.v:148849$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308068,10 +310565,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:147217$7324_Y + connect \Y $eq$libresoc.v:148849$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:147220$7327 + cell $eq $eq$libresoc.v:148852$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308079,10 +310576,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:147220$7327_Y + connect \Y $eq$libresoc.v:148852$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:147222$7329 + cell $eq $eq$libresoc.v:148854$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -308090,10 +310587,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:147222$7329_Y + connect \Y $eq$libresoc.v:148854$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:147223$7330 + cell $eq $eq$libresoc.v:148855$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -308101,10 +310598,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:147223$7330_Y + connect \Y $eq$libresoc.v:148855$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:147224$7331 + cell $eq $eq$libresoc.v:148856$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308112,34 +310609,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:147224$7331_Y + connect \Y $eq$libresoc.v:148856$7379_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147229$7336 + cell $pos $extend$libresoc.v:148861$7384 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:147229$7336_Y + connect \Y $extend$libresoc.v:148861$7384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:147225$7332 + cell $not $not$libresoc.v:148857$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:147225$7332_Y + connect \Y $not$libresoc.v:148857$7380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:147232$7340 + cell $not $not$libresoc.v:148864$7388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:147232$7340_Y + connect \Y $not$libresoc.v:148864$7388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:147218$7325 + cell $or $or$libresoc.v:148850$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308147,10 +310644,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:147218$7325_Y + connect \Y $or$libresoc.v:148850$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:147221$7328 + cell $or $or$libresoc.v:148853$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308158,26 +310655,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:147221$7328_Y + connect \Y $or$libresoc.v:148853$7376_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147229$7337 + cell $pos $pos$libresoc.v:148861$7385 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147229$7336_Y - connect \Y $pos$libresoc.v:147229$7337_Y + connect \A $extend$libresoc.v:148861$7384_Y + connect \Y $pos$libresoc.v:148861$7385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:147230$7338 + cell $reduce_or $reduce_or$libresoc.v:148862$7386 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:147230$7338_Y + connect \Y $reduce_or$libresoc.v:148862$7386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:147228$7335 + cell $sub $sub$libresoc.v:148860$7383 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308185,10 +310682,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:147228$7335_Y + connect \Y $sub$libresoc.v:148860$7383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:147231$7339 + cell $xor $xor$libresoc.v:148863$7387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308196,23 +310693,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:147231$7339_Y + connect \Y $xor$libresoc.v:148863$7387_Y end - attribute \src "libresoc.v:146914.7-146914.20" - process $proc$libresoc.v:146914$7360 + attribute \src "libresoc.v:148546.7-148546.20" + process $proc$libresoc.v:148546$7408 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147235.3-147246.6" - process $proc$libresoc.v:147235$7343 + attribute \src "libresoc.v:148867.3-148878.6" + process $proc$libresoc.v:148867$7391 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:147236.5-147236.29" + attribute \src "libresoc.v:148868.5-148868.29" switch \initial - attribute \src "libresoc.v:147236.9-147236.17" + attribute \src "libresoc.v:148868.9-148868.17" case 1'1 case end @@ -308230,14 +310727,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:147247.3-147273.6" - process $proc$libresoc.v:147247$7344 + attribute \src "libresoc.v:148879.3-148905.6" + process $proc$libresoc.v:148879$7392 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:147248.5-147248.29" + attribute \src "libresoc.v:148880.5-148880.29" switch \initial - attribute \src "libresoc.v:147248.9-147248.17" + attribute \src "libresoc.v:148880.9-148880.17" case 1'1 case end @@ -308272,14 +310769,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:147274.3-147292.6" - process $proc$libresoc.v:147274$7345 + attribute \src "libresoc.v:148906.3-148924.6" + process $proc$libresoc.v:148906$7393 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:147275.5-147275.29" + attribute \src "libresoc.v:148907.5-148907.29" switch \initial - attribute \src "libresoc.v:147275.9-147275.17" + attribute \src "libresoc.v:148907.9-148907.17" case 1'1 case end @@ -308303,14 +310800,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:147293.3-147307.6" - process $proc$libresoc.v:147293$7346 + attribute \src "libresoc.v:148925.3-148939.6" + process $proc$libresoc.v:148925$7394 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:147294.5-147294.29" + attribute \src "libresoc.v:148926.5-148926.29" switch \initial - attribute \src "libresoc.v:147294.9-147294.17" + attribute \src "libresoc.v:148926.9-148926.17" case 1'1 case end @@ -308330,14 +310827,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:147308.3-147317.6" - process $proc$libresoc.v:147308$7347 + attribute \src "libresoc.v:148940.3-148949.6" + process $proc$libresoc.v:148940$7395 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7348 $1\fast2$11[63:0]$7349 - attribute \src "libresoc.v:147309.5-147309.29" + assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 + attribute \src "libresoc.v:148941.5-148941.29" switch \initial - attribute \src "libresoc.v:147309.9-147309.17" + attribute \src "libresoc.v:148941.9-148941.17" case 1'1 case end @@ -308346,21 +310843,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7349 \$48 [63:0] + assign $1\fast2$11[63:0]$7397 \$48 [63:0] case - assign $1\fast2$11[63:0]$7349 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7397 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7348 + update \fast2$11 $0\fast2$11[63:0]$7396 end - attribute \src "libresoc.v:147318.3-147327.6" - process $proc$libresoc.v:147318$7350 + attribute \src "libresoc.v:148950.3-148959.6" + process $proc$libresoc.v:148950$7398 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:147319.5-147319.29" + attribute \src "libresoc.v:148951.5-148951.29" switch \initial - attribute \src "libresoc.v:147319.9-147319.17" + attribute \src "libresoc.v:148951.9-148951.17" case 1'1 case end @@ -308376,14 +310873,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:147328.3-147342.6" - process $proc$libresoc.v:147328$7351 + attribute \src "libresoc.v:148960.3-148974.6" + process $proc$libresoc.v:148960$7399 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:147329.5-147329.29" + attribute \src "libresoc.v:148961.5-148961.29" switch \initial - attribute \src "libresoc.v:147329.9-147329.17" + attribute \src "libresoc.v:148961.9-148961.17" case 1'1 case end @@ -308411,14 +310908,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:147343.3-147355.6" - process $proc$libresoc.v:147343$7352 + attribute \src "libresoc.v:148975.3-148987.6" + process $proc$libresoc.v:148975$7400 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:147344.5-147344.29" + attribute \src "libresoc.v:148976.5-148976.29" switch \initial - attribute \src "libresoc.v:147344.9-147344.17" + attribute \src "libresoc.v:148976.9-148976.17" case 1'1 case end @@ -308435,14 +310932,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:147356.3-147379.6" - process $proc$libresoc.v:147356$7353 + attribute \src "libresoc.v:148988.3-149011.6" + process $proc$libresoc.v:148988$7401 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:147357.5-147357.29" + attribute \src "libresoc.v:148989.5-148989.29" switch \initial - attribute \src "libresoc.v:147357.9-147357.17" + attribute \src "libresoc.v:148989.9-148989.17" case 1'1 case end @@ -308477,14 +310974,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:147380.3-147392.6" - process $proc$libresoc.v:147380$7354 + attribute \src "libresoc.v:149012.3-149024.6" + process $proc$libresoc.v:149012$7402 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:147381.5-147381.29" + attribute \src "libresoc.v:149013.5-149013.29" switch \initial - attribute \src "libresoc.v:147381.9-147381.17" + attribute \src "libresoc.v:149013.9-149013.17" case 1'1 case end @@ -308501,14 +310998,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:147393.3-147405.6" - process $proc$libresoc.v:147393$7355 + attribute \src "libresoc.v:149025.3-149037.6" + process $proc$libresoc.v:149025$7403 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7356 $1\fast1$10[63:0]$7357 - attribute \src "libresoc.v:147394.5-147394.29" + assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 + attribute \src "libresoc.v:149026.5-149026.29" switch \initial - attribute \src "libresoc.v:147394.9-147394.17" + attribute \src "libresoc.v:149026.9-149026.17" case 1'1 case end @@ -308516,23 +311013,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7357 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7405 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7357 \ctr_n + assign $1\fast1$10[63:0]$7405 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7356 + update \fast1$10 $0\fast1$10[63:0]$7404 end - attribute \src "libresoc.v:147406.3-147426.6" - process $proc$libresoc.v:147406$7358 + attribute \src "libresoc.v:149038.3-149058.6" + process $proc$libresoc.v:149038$7406 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:147407.5-147407.29" + attribute \src "libresoc.v:149039.5-149039.29" switch \initial - attribute \src "libresoc.v:147407.9-147407.17" + attribute \src "libresoc.v:149039.9-149039.17" case 1'1 case end @@ -308560,14 +311057,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:147427.3-147439.6" - process $proc$libresoc.v:147427$7359 + attribute \src "libresoc.v:149059.3-149071.6" + process $proc$libresoc.v:149059$7407 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:147428.5-147428.29" + attribute \src "libresoc.v:149060.5-149060.29" switch \initial - attribute \src "libresoc.v:147428.9-147428.17" + attribute \src "libresoc.v:149060.9-149060.17" case 1'1 case end @@ -308584,24 +311081,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:147217$7324_Y - connect \$14 $or$libresoc.v:147218$7325_Y - connect \$17 $add$libresoc.v:147219$7326_Y - connect \$19 $eq$libresoc.v:147220$7327_Y - connect \$21 $or$libresoc.v:147221$7328_Y - connect \$23 $eq$libresoc.v:147222$7329_Y - connect \$25 $eq$libresoc.v:147223$7330_Y - connect \$27 $eq$libresoc.v:147224$7331_Y - connect \$29 $not$libresoc.v:147225$7332_Y - connect \$31 $and$libresoc.v:147226$7333_Y - connect \$33 $and$libresoc.v:147227$7334_Y - connect \$36 $sub$libresoc.v:147228$7335_Y - connect \$38 $pos$libresoc.v:147229$7337_Y - connect \$40 $reduce_or$libresoc.v:147230$7338_Y - connect \$42 $xor$libresoc.v:147231$7339_Y - connect \$44 $not$libresoc.v:147232$7340_Y - connect \$46 $and$libresoc.v:147233$7341_Y - connect \$49 $add$libresoc.v:147234$7342_Y + connect \$12 $eq$libresoc.v:148849$7372_Y + connect \$14 $or$libresoc.v:148850$7373_Y + connect \$17 $add$libresoc.v:148851$7374_Y + connect \$19 $eq$libresoc.v:148852$7375_Y + connect \$21 $or$libresoc.v:148853$7376_Y + connect \$23 $eq$libresoc.v:148854$7377_Y + connect \$25 $eq$libresoc.v:148855$7378_Y + connect \$27 $eq$libresoc.v:148856$7379_Y + connect \$29 $not$libresoc.v:148857$7380_Y + connect \$31 $and$libresoc.v:148858$7381_Y + connect \$33 $and$libresoc.v:148859$7382_Y + connect \$36 $sub$libresoc.v:148860$7383_Y + connect \$38 $pos$libresoc.v:148861$7385_Y + connect \$40 $reduce_or$libresoc.v:148862$7386_Y + connect \$42 $xor$libresoc.v:148863$7387_Y + connect \$44 $not$libresoc.v:148864$7388_Y + connect \$46 $and$libresoc.v:148865$7389_Y + connect \$49 $add$libresoc.v:148866$7390_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -308612,279 +311109,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:147453.1-148403.10" +attribute \src "libresoc.v:149085.1-150035.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:148368.3-148379.6" + attribute \src "libresoc.v:150000.3-150011.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:147866.3-147877.6" + attribute \src "libresoc.v:149498.3-149509.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:148380.3-148391.6" + attribute \src "libresoc.v:150012.3-150023.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:148149.3-148160.6" + attribute \src "libresoc.v:149781.3-149792.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $0\fast1$11[63:0]$7406 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $0\fast1$11[63:0]$7454 + attribute \src "libresoc.v:149606.3-149637.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $0\fast2$12[63:0]$7411 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $0\fast2$12[63:0]$7459 + attribute \src "libresoc.v:149721.3-149752.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:147454.7-147454.20" + attribute \src "libresoc.v:149086.7-149086.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:148330.3-148348.6" + attribute \src "libresoc.v:149962.3-149980.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148349.3-148367.6" + attribute \src "libresoc.v:149981.3-149999.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$60[0:0]$7425 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$61[0:0]$7426 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$62[0:0]$7427 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$67[0:0]$7428 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$68[0:0]$7429 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$69[0:0]$7430 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal$70[0:0]$7431 - attribute \src "libresoc.v:148121.3-148148.6" - wire $0\trapexc_$signal[0:0]$7424 - attribute \src "libresoc.v:148006.3-148088.6" - wire $10\fast2$12[19:19]$7421 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$60[0:0]$7473 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$61[0:0]$7474 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$62[0:0]$7475 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$67[0:0]$7476 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$68[0:0]$7477 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$69[0:0]$7478 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal$70[0:0]$7479 + attribute \src "libresoc.v:149753.3-149780.6" + wire $0\trapexc_$signal[0:0]$7472 + attribute \src "libresoc.v:149638.3-149720.6" + wire $10\fast2$12[19:19]$7469 + attribute \src "libresoc.v:149793.3-149961.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $11\msr[15:15] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $12\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $13\msr[60:60] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $14\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $15\msr[12:12] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $17\msr[15:15] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:148368.3-148379.6" + attribute \src "libresoc.v:150000.3-150011.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:147866.3-147877.6" + attribute \src "libresoc.v:149498.3-149509.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:148380.3-148391.6" + attribute \src "libresoc.v:150012.3-150023.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:148149.3-148160.6" + attribute \src "libresoc.v:149781.3-149792.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $1\fast1$11[63:0]$7407 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $1\fast1$11[63:0]$7455 + attribute \src "libresoc.v:149606.3-149637.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $1\fast2$12[63:0]$7412 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $1\fast2$12[63:0]$7460 + attribute \src "libresoc.v:149721.3-149752.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:148330.3-148348.6" + attribute \src "libresoc.v:149962.3-149980.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148349.3-148367.6" + attribute \src "libresoc.v:149981.3-149999.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$60[0:0]$7433 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$61[0:0]$7434 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$62[0:0]$7435 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$67[0:0]$7436 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$68[0:0]$7437 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$69[0:0]$7438 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal$70[0:0]$7439 - attribute \src "libresoc.v:148121.3-148148.6" - wire $1\trapexc_$signal[0:0]$7432 - attribute \src "libresoc.v:147942.3-147973.6" - wire width 64 $2\fast1$11[63:0]$7408 - attribute \src "libresoc.v:147974.3-148005.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$60[0:0]$7481 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$61[0:0]$7482 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$62[0:0]$7483 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$67[0:0]$7484 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$68[0:0]$7485 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$69[0:0]$7486 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:149753.3-149780.6" + wire $1\trapexc_$signal[0:0]$7480 + attribute \src "libresoc.v:149574.3-149605.6" + wire width 64 $2\fast1$11[63:0]$7456 + attribute \src "libresoc.v:149606.3-149637.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 64 $2\fast2$12[63:0]$7413 - attribute \src "libresoc.v:148089.3-148120.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 64 $2\fast2$12[63:0]$7461 + attribute \src "libresoc.v:149721.3-149752.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149793.3-149961.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:147878.3-147909.6" + attribute \src "libresoc.v:149510.3-149541.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:147910.3-147941.6" + attribute \src "libresoc.v:149542.3-149573.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$60[0:0]$7441 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$61[0:0]$7442 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$62[0:0]$7443 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$67[0:0]$7444 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$68[0:0]$7445 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$69[0:0]$7446 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal$70[0:0]$7447 - attribute \src "libresoc.v:148121.3-148148.6" - wire $2\trapexc_$signal[0:0]$7440 - attribute \src "libresoc.v:148006.3-148088.6" - wire $3\fast2$12[17:17]$7414 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$60[0:0]$7489 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$61[0:0]$7490 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$62[0:0]$7491 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$67[0:0]$7492 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$68[0:0]$7493 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$69[0:0]$7494 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal$70[0:0]$7495 + attribute \src "libresoc.v:149753.3-149780.6" + wire $2\trapexc_$signal[0:0]$7488 + attribute \src "libresoc.v:149638.3-149720.6" + wire $3\fast2$12[17:17]$7462 + attribute \src "libresoc.v:149793.3-149961.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$60[0:0]$7449 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$61[0:0]$7450 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$62[0:0]$7451 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$67[0:0]$7452 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$68[0:0]$7453 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$69[0:0]$7454 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal$70[0:0]$7455 - attribute \src "libresoc.v:148121.3-148148.6" - wire $3\trapexc_$signal[0:0]$7448 - attribute \src "libresoc.v:148006.3-148088.6" - wire $4\fast2$12[18:18]$7415 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$60[0:0]$7497 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$61[0:0]$7498 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$62[0:0]$7499 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$67[0:0]$7500 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$68[0:0]$7501 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$69[0:0]$7502 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal$70[0:0]$7503 + attribute \src "libresoc.v:149753.3-149780.6" + wire $3\trapexc_$signal[0:0]$7496 + attribute \src "libresoc.v:149638.3-149720.6" + wire $4\fast2$12[18:18]$7463 + attribute \src "libresoc.v:149793.3-149961.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:148006.3-148088.6" - wire $5\fast2$12[20:20]$7416 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $5\fast2$12[20:20]$7464 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:148006.3-148088.6" - wire $6\fast2$12[16:16]$7417 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $6\fast2$12[16:16]$7465 + attribute \src "libresoc.v:149793.3-149961.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:148006.3-148088.6" - wire width 2 $7\fast2$12[19:18]$7418 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire width 2 $7\fast2$12[19:18]$7466 + attribute \src "libresoc.v:149793.3-149961.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:148006.3-148088.6" - wire $8\fast2$12[28:28]$7419 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $8\fast2$12[28:28]$7467 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:148006.3-148088.6" - wire $9\fast2$12[30:30]$7420 - attribute \src "libresoc.v:148161.3-148329.6" + attribute \src "libresoc.v:149638.3-149720.6" + wire $9\fast2$12[30:30]$7468 + attribute \src "libresoc.v:149793.3-149961.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:147842.18-147842.113" - wire width 65 $add$libresoc.v:147842$7377_Y - attribute \src "libresoc.v:147836.18-147836.108" - wire width 5 $and$libresoc.v:147836$7370_Y - attribute \src "libresoc.v:147844.18-147844.118" - wire width 8 $and$libresoc.v:147844$7379_Y - attribute \src "libresoc.v:147846.18-147846.118" - wire width 8 $and$libresoc.v:147846$7381_Y - attribute \src "libresoc.v:147848.18-147848.118" - wire width 8 $and$libresoc.v:147848$7383_Y - attribute \src "libresoc.v:147850.18-147850.119" - wire width 8 $and$libresoc.v:147850$7385_Y - attribute \src "libresoc.v:147852.18-147852.119" - wire width 8 $and$libresoc.v:147852$7387_Y - attribute \src "libresoc.v:147854.18-147854.119" - wire width 8 $and$libresoc.v:147854$7389_Y - attribute \src "libresoc.v:147860.18-147860.106" - wire $and$libresoc.v:147860$7396_Y - attribute \src "libresoc.v:147865.18-147865.106" - wire $and$libresoc.v:147865$7401_Y - attribute \src "libresoc.v:147835.18-147835.100" - wire $eq$libresoc.v:147835$7369_Y - attribute \src "libresoc.v:147843.18-147843.119" - wire $eq$libresoc.v:147843$7378_Y - attribute \src "libresoc.v:147857.18-147857.121" - wire $eq$libresoc.v:147857$7393_Y - attribute \src "libresoc.v:147858.18-147858.121" - wire $eq$libresoc.v:147858$7394_Y - attribute \src "libresoc.v:147859.18-147859.111" - wire $eq$libresoc.v:147859$7395_Y - attribute \src "libresoc.v:147863.18-147863.121" - wire $eq$libresoc.v:147863$7399_Y - attribute \src "libresoc.v:147864.18-147864.114" - wire $eq$libresoc.v:147864$7400_Y - attribute \src "libresoc.v:147829.18-147829.95" - wire width 64 $extend$libresoc.v:147829$7361_Y - attribute \src "libresoc.v:147830.18-147830.95" - wire width 64 $extend$libresoc.v:147830$7363_Y - attribute \src "libresoc.v:147841.18-147841.100" - wire width 64 $extend$libresoc.v:147841$7375_Y - attribute \src "libresoc.v:147856.18-147856.109" - wire width 65 $extend$libresoc.v:147856$7391_Y - attribute \src "libresoc.v:147832.18-147832.121" - wire $gt$libresoc.v:147832$7366_Y - attribute \src "libresoc.v:147834.18-147834.99" - wire $gt$libresoc.v:147834$7368_Y - attribute \src "libresoc.v:147831.18-147831.121" - wire $lt$libresoc.v:147831$7365_Y - attribute \src "libresoc.v:147833.18-147833.99" - wire $lt$libresoc.v:147833$7367_Y - attribute \src "libresoc.v:147861.18-147861.112" - wire $not$libresoc.v:147861$7397_Y - attribute \src "libresoc.v:147862.18-147862.112" - wire $not$libresoc.v:147862$7398_Y - attribute \src "libresoc.v:147839.18-147839.106" - wire $or$libresoc.v:147839$7373_Y - attribute \src "libresoc.v:147829.18-147829.95" - wire width 64 $pos$libresoc.v:147829$7362_Y - attribute \src "libresoc.v:147830.18-147830.95" - wire width 64 $pos$libresoc.v:147830$7364_Y - attribute \src "libresoc.v:147841.18-147841.100" - wire width 64 $pos$libresoc.v:147841$7376_Y - attribute \src "libresoc.v:147856.18-147856.109" - wire width 65 $pos$libresoc.v:147856$7392_Y - attribute \src "libresoc.v:147837.18-147837.100" - wire $reduce_or$libresoc.v:147837$7371_Y - attribute \src "libresoc.v:147838.18-147838.113" - wire $reduce_or$libresoc.v:147838$7372_Y - attribute \src "libresoc.v:147845.18-147845.91" - wire $reduce_or$libresoc.v:147845$7380_Y - attribute \src "libresoc.v:147847.18-147847.91" - wire $reduce_or$libresoc.v:147847$7382_Y - attribute \src "libresoc.v:147849.18-147849.91" - wire $reduce_or$libresoc.v:147849$7384_Y - attribute \src "libresoc.v:147851.18-147851.91" - wire $reduce_or$libresoc.v:147851$7386_Y - attribute \src "libresoc.v:147853.18-147853.91" - wire $reduce_or$libresoc.v:147853$7388_Y - attribute \src "libresoc.v:147855.18-147855.91" - wire $reduce_or$libresoc.v:147855$7390_Y - attribute \src "libresoc.v:147840.18-147840.120" - wire width 20 $sshl$libresoc.v:147840$7374_Y + attribute \src "libresoc.v:149474.18-149474.113" + wire width 65 $add$libresoc.v:149474$7425_Y + attribute \src "libresoc.v:149468.18-149468.108" + wire width 5 $and$libresoc.v:149468$7418_Y + attribute \src "libresoc.v:149476.18-149476.118" + wire width 8 $and$libresoc.v:149476$7427_Y + attribute \src "libresoc.v:149478.18-149478.118" + wire width 8 $and$libresoc.v:149478$7429_Y + attribute \src "libresoc.v:149480.18-149480.118" + wire width 8 $and$libresoc.v:149480$7431_Y + attribute \src "libresoc.v:149482.18-149482.119" + wire width 8 $and$libresoc.v:149482$7433_Y + attribute \src "libresoc.v:149484.18-149484.119" + wire width 8 $and$libresoc.v:149484$7435_Y + attribute \src "libresoc.v:149486.18-149486.119" + wire width 8 $and$libresoc.v:149486$7437_Y + attribute \src "libresoc.v:149492.18-149492.106" + wire $and$libresoc.v:149492$7444_Y + attribute \src "libresoc.v:149497.18-149497.106" + wire $and$libresoc.v:149497$7449_Y + attribute \src "libresoc.v:149467.18-149467.100" + wire $eq$libresoc.v:149467$7417_Y + attribute \src "libresoc.v:149475.18-149475.119" + wire $eq$libresoc.v:149475$7426_Y + attribute \src "libresoc.v:149489.18-149489.121" + wire $eq$libresoc.v:149489$7441_Y + attribute \src "libresoc.v:149490.18-149490.121" + wire $eq$libresoc.v:149490$7442_Y + attribute \src "libresoc.v:149491.18-149491.111" + wire $eq$libresoc.v:149491$7443_Y + attribute \src "libresoc.v:149495.18-149495.121" + wire $eq$libresoc.v:149495$7447_Y + attribute \src "libresoc.v:149496.18-149496.114" + wire $eq$libresoc.v:149496$7448_Y + attribute \src "libresoc.v:149461.18-149461.95" + wire width 64 $extend$libresoc.v:149461$7409_Y + attribute \src "libresoc.v:149462.18-149462.95" + wire width 64 $extend$libresoc.v:149462$7411_Y + attribute \src "libresoc.v:149473.18-149473.100" + wire width 64 $extend$libresoc.v:149473$7423_Y + attribute \src "libresoc.v:149488.18-149488.109" + wire width 65 $extend$libresoc.v:149488$7439_Y + attribute \src "libresoc.v:149464.18-149464.121" + wire $gt$libresoc.v:149464$7414_Y + attribute \src "libresoc.v:149466.18-149466.99" + wire $gt$libresoc.v:149466$7416_Y + attribute \src "libresoc.v:149463.18-149463.121" + wire $lt$libresoc.v:149463$7413_Y + attribute \src "libresoc.v:149465.18-149465.99" + wire $lt$libresoc.v:149465$7415_Y + attribute \src "libresoc.v:149493.18-149493.112" + wire $not$libresoc.v:149493$7445_Y + attribute \src "libresoc.v:149494.18-149494.112" + wire $not$libresoc.v:149494$7446_Y + attribute \src "libresoc.v:149471.18-149471.106" + wire $or$libresoc.v:149471$7421_Y + attribute \src "libresoc.v:149461.18-149461.95" + wire width 64 $pos$libresoc.v:149461$7410_Y + attribute \src "libresoc.v:149462.18-149462.95" + wire width 64 $pos$libresoc.v:149462$7412_Y + attribute \src "libresoc.v:149473.18-149473.100" + wire width 64 $pos$libresoc.v:149473$7424_Y + attribute \src "libresoc.v:149488.18-149488.109" + wire width 65 $pos$libresoc.v:149488$7440_Y + attribute \src "libresoc.v:149469.18-149469.100" + wire $reduce_or$libresoc.v:149469$7419_Y + attribute \src "libresoc.v:149470.18-149470.113" + wire $reduce_or$libresoc.v:149470$7420_Y + attribute \src "libresoc.v:149477.18-149477.91" + wire $reduce_or$libresoc.v:149477$7428_Y + attribute \src "libresoc.v:149479.18-149479.91" + wire $reduce_or$libresoc.v:149479$7430_Y + attribute \src "libresoc.v:149481.18-149481.91" + wire $reduce_or$libresoc.v:149481$7432_Y + attribute \src "libresoc.v:149483.18-149483.91" + wire $reduce_or$libresoc.v:149483$7434_Y + attribute \src "libresoc.v:149485.18-149485.91" + wire $reduce_or$libresoc.v:149485$7436_Y + attribute \src "libresoc.v:149487.18-149487.91" + wire $reduce_or$libresoc.v:149487$7438_Y + attribute \src "libresoc.v:149472.18-149472.120" + wire width 20 $sshl$libresoc.v:149472$7422_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -308987,7 +311484,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:147454.7-147454.15" + attribute \src "libresoc.v:149086.7-149086.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -309252,7 +311749,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:147842$7377 + cell $add $add$libresoc.v:149474$7425 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309260,10 +311757,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:147842$7377_Y + connect \Y $add$libresoc.v:149474$7425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:147836$7370 + cell $and $and$libresoc.v:149468$7418 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -309271,10 +311768,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:147836$7370_Y + connect \Y $and$libresoc.v:149468$7418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:147844$7379 + cell $and $and$libresoc.v:149476$7427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309282,10 +311779,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:147844$7379_Y + connect \Y $and$libresoc.v:149476$7427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:147846$7381 + cell $and $and$libresoc.v:149478$7429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309293,10 +311790,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:147846$7381_Y + connect \Y $and$libresoc.v:149478$7429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:147848$7383 + cell $and $and$libresoc.v:149480$7431 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309304,10 +311801,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:147848$7383_Y + connect \Y $and$libresoc.v:149480$7431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:147850$7385 + cell $and $and$libresoc.v:149482$7433 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309315,10 +311812,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:147850$7385_Y + connect \Y $and$libresoc.v:149482$7433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:147852$7387 + cell $and $and$libresoc.v:149484$7435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309326,10 +311823,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:147852$7387_Y + connect \Y $and$libresoc.v:149484$7435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:147854$7389 + cell $and $and$libresoc.v:149486$7437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309337,10 +311834,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:147854$7389_Y + connect \Y $and$libresoc.v:149486$7437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:147860$7396 + cell $and $and$libresoc.v:149492$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309348,10 +311845,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:147860$7396_Y + connect \Y $and$libresoc.v:149492$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:147865$7401 + cell $and $and$libresoc.v:149497$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309359,10 +311856,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:147865$7401_Y + connect \Y $and$libresoc.v:149497$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:147835$7369 + cell $eq $eq$libresoc.v:149467$7417 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309370,10 +311867,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:147835$7369_Y + connect \Y $eq$libresoc.v:149467$7417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:147843$7378 + cell $eq $eq$libresoc.v:149475$7426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -309381,10 +311878,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:147843$7378_Y + connect \Y $eq$libresoc.v:149475$7426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:147857$7393 + cell $eq $eq$libresoc.v:149489$7441 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -309392,10 +311889,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:147857$7393_Y + connect \Y $eq$libresoc.v:149489$7441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:147858$7394 + cell $eq $eq$libresoc.v:149490$7442 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309403,10 +311900,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:147858$7394_Y + connect \Y $eq$libresoc.v:149490$7442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:147859$7395 + cell $eq $eq$libresoc.v:149491$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309414,10 +311911,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:147859$7395_Y + connect \Y $eq$libresoc.v:149491$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:147863$7399 + cell $eq $eq$libresoc.v:149495$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309425,10 +311922,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:147863$7399_Y + connect \Y $eq$libresoc.v:149495$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:147864$7400 + cell $eq $eq$libresoc.v:149496$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -309436,42 +311933,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:147864$7400_Y + connect \Y $eq$libresoc.v:149496$7448_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147829$7361 + cell $pos $extend$libresoc.v:149461$7409 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:147829$7361_Y + connect \Y $extend$libresoc.v:149461$7409_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147830$7363 + cell $pos $extend$libresoc.v:149462$7411 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:147830$7363_Y + connect \Y $extend$libresoc.v:149462$7411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:147841$7375 + cell $pos $extend$libresoc.v:149473$7423 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:147841$7375_Y + connect \Y $extend$libresoc.v:149473$7423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:147856$7391 + cell $pos $extend$libresoc.v:149488$7439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:147856$7391_Y + connect \Y $extend$libresoc.v:149488$7439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:147832$7366 + cell $gt $gt$libresoc.v:149464$7414 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -309479,10 +311976,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:147832$7366_Y + connect \Y $gt$libresoc.v:149464$7414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:147834$7368 + cell $gt $gt$libresoc.v:149466$7416 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309490,10 +311987,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:147834$7368_Y + connect \Y $gt$libresoc.v:149466$7416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:147831$7365 + cell $lt $lt$libresoc.v:149463$7413 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -309501,10 +311998,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:147831$7365_Y + connect \Y $lt$libresoc.v:149463$7413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:147833$7367 + cell $lt $lt$libresoc.v:149465$7415 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -309512,26 +312009,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:147833$7367_Y + connect \Y $lt$libresoc.v:149465$7415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:147861$7397 + cell $not $not$libresoc.v:149493$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:147861$7397_Y + connect \Y $not$libresoc.v:149493$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:147862$7398 + cell $not $not$libresoc.v:149494$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:147862$7398_Y + connect \Y $not$libresoc.v:149494$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:147839$7373 + cell $or $or$libresoc.v:149471$7421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309539,106 +312036,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:147839$7373_Y + connect \Y $or$libresoc.v:149471$7421_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147829$7362 + cell $pos $pos$libresoc.v:149461$7410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147829$7361_Y - connect \Y $pos$libresoc.v:147829$7362_Y + connect \A $extend$libresoc.v:149461$7409_Y + connect \Y $pos$libresoc.v:149461$7410_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147830$7364 + cell $pos $pos$libresoc.v:149462$7412 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147830$7363_Y - connect \Y $pos$libresoc.v:147830$7364_Y + connect \A $extend$libresoc.v:149462$7411_Y + connect \Y $pos$libresoc.v:149462$7412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:147841$7376 + cell $pos $pos$libresoc.v:149473$7424 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:147841$7375_Y - connect \Y $pos$libresoc.v:147841$7376_Y + connect \A $extend$libresoc.v:149473$7423_Y + connect \Y $pos$libresoc.v:149473$7424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:147856$7392 + cell $pos $pos$libresoc.v:149488$7440 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:147856$7391_Y - connect \Y $pos$libresoc.v:147856$7392_Y + connect \A $extend$libresoc.v:149488$7439_Y + connect \Y $pos$libresoc.v:149488$7440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:147837$7371 + cell $reduce_or $reduce_or$libresoc.v:149469$7419 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:147837$7371_Y + connect \Y $reduce_or$libresoc.v:149469$7419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:147838$7372 + cell $reduce_or $reduce_or$libresoc.v:149470$7420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:147838$7372_Y + connect \Y $reduce_or$libresoc.v:149470$7420_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147845$7380 + cell $reduce_or $reduce_or$libresoc.v:149477$7428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:147845$7380_Y + connect \Y $reduce_or$libresoc.v:149477$7428_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147847$7382 + cell $reduce_or $reduce_or$libresoc.v:149479$7430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:147847$7382_Y + connect \Y $reduce_or$libresoc.v:149479$7430_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147849$7384 + cell $reduce_or $reduce_or$libresoc.v:149481$7432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:147849$7384_Y + connect \Y $reduce_or$libresoc.v:149481$7432_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147851$7386 + cell $reduce_or $reduce_or$libresoc.v:149483$7434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:147851$7386_Y + connect \Y $reduce_or$libresoc.v:149483$7434_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147853$7388 + cell $reduce_or $reduce_or$libresoc.v:149485$7436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:147853$7388_Y + connect \Y $reduce_or$libresoc.v:149485$7436_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:147855$7390 + cell $reduce_or $reduce_or$libresoc.v:149487$7438 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:147855$7390_Y + connect \Y $reduce_or$libresoc.v:149487$7438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:147840$7374 + cell $sshl $sshl$libresoc.v:149472$7422 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -309646,23 +312143,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:147840$7374_Y + connect \Y $sshl$libresoc.v:149472$7422_Y end - attribute \src "libresoc.v:147454.7-147454.20" - process $proc$libresoc.v:147454$7462 + attribute \src "libresoc.v:149086.7-149086.20" + process $proc$libresoc.v:149086$7510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147866.3-147877.6" - process $proc$libresoc.v:147866$7402 + attribute \src "libresoc.v:149498.3-149509.6" + process $proc$libresoc.v:149498$7450 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:147867.5-147867.29" + attribute \src "libresoc.v:149499.5-149499.29" switch \initial - attribute \src "libresoc.v:147867.9-147867.17" + attribute \src "libresoc.v:149499.9-149499.17" case 1'1 case end @@ -309680,14 +312177,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:147878.3-147909.6" - process $proc$libresoc.v:147878$7403 + attribute \src "libresoc.v:149510.3-149541.6" + process $proc$libresoc.v:149510$7451 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:147879.5-147879.29" + attribute \src "libresoc.v:149511.5-149511.29" switch \initial - attribute \src "libresoc.v:147879.9-147879.17" + attribute \src "libresoc.v:149511.9-149511.17" case 1'1 case end @@ -309726,14 +312223,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:147910.3-147941.6" - process $proc$libresoc.v:147910$7404 + attribute \src "libresoc.v:149542.3-149573.6" + process $proc$libresoc.v:149542$7452 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:147911.5-147911.29" + attribute \src "libresoc.v:149543.5-149543.29" switch \initial - attribute \src "libresoc.v:147911.9-147911.17" + attribute \src "libresoc.v:149543.9-149543.17" case 1'1 case end @@ -309772,14 +312269,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:147942.3-147973.6" - process $proc$libresoc.v:147942$7405 + attribute \src "libresoc.v:149574.3-149605.6" + process $proc$libresoc.v:149574$7453 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7406 $1\fast1$11[63:0]$7407 - attribute \src "libresoc.v:147943.5-147943.29" + assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 + attribute \src "libresoc.v:149575.5-149575.29" switch \initial - attribute \src "libresoc.v:147943.9-147943.17" + attribute \src "libresoc.v:149575.9-149575.17" case 1'1 case end @@ -309788,43 +312285,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7407 $2\fast1$11[63:0]$7408 + assign $1\fast1$11[63:0]$7455 $2\fast1$11[63:0]$7456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7408 \trap_op__cia + assign $2\fast1$11[63:0]$7456 \trap_op__cia case - assign $2\fast1$11[63:0]$7408 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7407 \$39 [63:0] + assign $1\fast1$11[63:0]$7455 \$39 [63:0] case - assign $1\fast1$11[63:0]$7407 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7406 + update \fast1$11 $0\fast1$11[63:0]$7454 end - attribute \src "libresoc.v:147974.3-148005.6" - process $proc$libresoc.v:147974$7409 + attribute \src "libresoc.v:149606.3-149637.6" + process $proc$libresoc.v:149606$7457 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:147975.5-147975.29" + attribute \src "libresoc.v:149607.5-149607.29" switch \initial - attribute \src "libresoc.v:147975.9-147975.17" + attribute \src "libresoc.v:149607.9-149607.17" case 1'1 case end @@ -309862,14 +312359,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:148006.3-148088.6" - process $proc$libresoc.v:148006$7410 + attribute \src "libresoc.v:149638.3-149720.6" + process $proc$libresoc.v:149638$7458 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7411 $1\fast2$12[63:0]$7412 - attribute \src "libresoc.v:148007.5-148007.29" + assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 + attribute \src "libresoc.v:149639.5-149639.29" switch \initial - attribute \src "libresoc.v:148007.9-148007.17" + attribute \src "libresoc.v:149639.9-149639.17" case 1'1 case end @@ -309878,59 +312375,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7412 $2\fast2$12[63:0]$7413 + assign $1\fast2$12[63:0]$7460 $2\fast2$12[63:0]$7461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7413 [29] $2\fast2$12[63:0]$7413 [27] $2\fast2$12[63:0]$7413 [21] } 3'000 - assign $2\fast2$12[63:0]$7413 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7413 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7413 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7413 [17] $3\fast2$12[17:17]$7414 - assign { } { } - assign $2\fast2$12[63:0]$7413 [20] $5\fast2$12[20:20]$7416 - assign $2\fast2$12[63:0]$7413 [16] $6\fast2$12[16:16]$7417 - assign $2\fast2$12[63:0]$7413 [18] $7\fast2$12[19:18]$7418 [0] - assign $2\fast2$12[63:0]$7413 [28] $8\fast2$12[28:28]$7419 - assign $2\fast2$12[63:0]$7413 [30] $9\fast2$12[30:30]$7420 - assign $2\fast2$12[63:0]$7413 [19] $10\fast2$12[19:19]$7421 + assign { $2\fast2$12[63:0]$7461 [29] $2\fast2$12[63:0]$7461 [27] $2\fast2$12[63:0]$7461 [21] } 3'000 + assign $2\fast2$12[63:0]$7461 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7461 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7461 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7461 [17] $3\fast2$12[17:17]$7462 + assign { } { } + assign $2\fast2$12[63:0]$7461 [20] $5\fast2$12[20:20]$7464 + assign $2\fast2$12[63:0]$7461 [16] $6\fast2$12[16:16]$7465 + assign $2\fast2$12[63:0]$7461 [18] $7\fast2$12[19:18]$7466 [0] + assign $2\fast2$12[63:0]$7461 [28] $8\fast2$12[28:28]$7467 + assign $2\fast2$12[63:0]$7461 [30] $9\fast2$12[30:30]$7468 + assign $2\fast2$12[63:0]$7461 [19] $10\fast2$12[19:19]$7469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7414 1'1 + assign $3\fast2$12[17:17]$7462 1'1 case - assign $3\fast2$12[17:17]$7414 1'0 + assign $3\fast2$12[17:17]$7462 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7415 1'1 + assign $4\fast2$12[18:18]$7463 1'1 case - assign $4\fast2$12[18:18]$7415 1'0 + assign $4\fast2$12[18:18]$7463 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7416 1'1 + assign $5\fast2$12[20:20]$7464 1'1 case - assign $5\fast2$12[20:20]$7416 1'0 + assign $5\fast2$12[20:20]$7464 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7417 1'1 + assign $6\fast2$12[16:16]$7465 1'1 case - assign $6\fast2$12[16:16]$7417 1'0 + assign $6\fast2$12[16:16]$7465 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -309939,57 +312436,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7420 \trapexc_$signal - assign $8\fast2$12[28:28]$7419 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7418 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7418 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7468 \trapexc_$signal + assign $8\fast2$12[28:28]$7467 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7466 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7466 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7418 { 1'0 $4\fast2$12[18:18]$7415 } - assign $8\fast2$12[28:28]$7419 1'0 - assign $9\fast2$12[30:30]$7420 1'0 + assign $7\fast2$12[19:18]$7466 { 1'0 $4\fast2$12[18:18]$7463 } + assign $8\fast2$12[28:28]$7467 1'0 + assign $9\fast2$12[30:30]$7468 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7421 1'1 + assign $10\fast2$12[19:19]$7469 1'1 case - assign $10\fast2$12[19:19]$7421 $7\fast2$12[19:18]$7418 [1] + assign $10\fast2$12[19:19]$7469 $7\fast2$12[19:18]$7466 [1] end case - assign $2\fast2$12[63:0]$7413 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7461 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7412 [30:27] $1\fast2$12[63:0]$7412 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7412 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7412 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7412 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7460 [30:27] $1\fast2$12[63:0]$7460 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7460 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7460 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7460 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7412 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7411 + update \fast2$12 $0\fast2$12[63:0]$7459 end - attribute \src "libresoc.v:148089.3-148120.6" - process $proc$libresoc.v:148089$7422 + attribute \src "libresoc.v:149721.3-149752.6" + process $proc$libresoc.v:149721$7470 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:148090.5-148090.29" + attribute \src "libresoc.v:149722.5-149722.29" switch \initial - attribute \src "libresoc.v:148090.9-148090.17" + attribute \src "libresoc.v:149722.9-149722.17" case 1'1 case end @@ -310027,8 +312524,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:148121.3-148148.6" - process $proc$libresoc.v:148121$7423 + attribute \src "libresoc.v:149753.3-149780.6" + process $proc$libresoc.v:149753$7471 assign { } { } assign { } { } assign { } { } @@ -310045,17 +312542,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7424 $1\trapexc_$signal[0:0]$7432 - assign $0\trapexc_$signal$60[0:0]$7425 $1\trapexc_$signal$60[0:0]$7433 - assign $0\trapexc_$signal$61[0:0]$7426 $1\trapexc_$signal$61[0:0]$7434 - assign $0\trapexc_$signal$62[0:0]$7427 $1\trapexc_$signal$62[0:0]$7435 - assign $0\trapexc_$signal$67[0:0]$7428 $1\trapexc_$signal$67[0:0]$7436 - assign $0\trapexc_$signal$68[0:0]$7429 $1\trapexc_$signal$68[0:0]$7437 - assign $0\trapexc_$signal$69[0:0]$7430 $1\trapexc_$signal$69[0:0]$7438 - assign $0\trapexc_$signal$70[0:0]$7431 $1\trapexc_$signal$70[0:0]$7439 - attribute \src "libresoc.v:148122.5-148122.29" + assign $0\trapexc_$signal[0:0]$7472 $1\trapexc_$signal[0:0]$7480 + assign $0\trapexc_$signal$60[0:0]$7473 $1\trapexc_$signal$60[0:0]$7481 + assign $0\trapexc_$signal$61[0:0]$7474 $1\trapexc_$signal$61[0:0]$7482 + assign $0\trapexc_$signal$62[0:0]$7475 $1\trapexc_$signal$62[0:0]$7483 + assign $0\trapexc_$signal$67[0:0]$7476 $1\trapexc_$signal$67[0:0]$7484 + assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 + assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 + assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:149754.5-149754.29" switch \initial - attribute \src "libresoc.v:148122.9-148122.17" + attribute \src "libresoc.v:149754.9-149754.17" case 1'1 case end @@ -310071,14 +312568,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7432 $2\trapexc_$signal[0:0]$7440 - assign $1\trapexc_$signal$60[0:0]$7433 $2\trapexc_$signal$60[0:0]$7441 - assign $1\trapexc_$signal$61[0:0]$7434 $2\trapexc_$signal$61[0:0]$7442 - assign $1\trapexc_$signal$62[0:0]$7435 $2\trapexc_$signal$62[0:0]$7443 - assign $1\trapexc_$signal$67[0:0]$7436 $2\trapexc_$signal$67[0:0]$7444 - assign $1\trapexc_$signal$68[0:0]$7437 $2\trapexc_$signal$68[0:0]$7445 - assign $1\trapexc_$signal$69[0:0]$7438 $2\trapexc_$signal$69[0:0]$7446 - assign $1\trapexc_$signal$70[0:0]$7439 $2\trapexc_$signal$70[0:0]$7447 + assign $1\trapexc_$signal[0:0]$7480 $2\trapexc_$signal[0:0]$7488 + assign $1\trapexc_$signal$60[0:0]$7481 $2\trapexc_$signal$60[0:0]$7489 + assign $1\trapexc_$signal$61[0:0]$7482 $2\trapexc_$signal$61[0:0]$7490 + assign $1\trapexc_$signal$62[0:0]$7483 $2\trapexc_$signal$62[0:0]$7491 + assign $1\trapexc_$signal$67[0:0]$7484 $2\trapexc_$signal$67[0:0]$7492 + assign $1\trapexc_$signal$68[0:0]$7485 $2\trapexc_$signal$68[0:0]$7493 + assign $1\trapexc_$signal$69[0:0]$7486 $2\trapexc_$signal$69[0:0]$7494 + assign $1\trapexc_$signal$70[0:0]$7487 $2\trapexc_$signal$70[0:0]$7495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -310091,14 +312588,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7440 $3\trapexc_$signal[0:0]$7448 - assign $2\trapexc_$signal$60[0:0]$7441 $3\trapexc_$signal$60[0:0]$7449 - assign $2\trapexc_$signal$61[0:0]$7442 $3\trapexc_$signal$61[0:0]$7450 - assign $2\trapexc_$signal$62[0:0]$7443 $3\trapexc_$signal$62[0:0]$7451 - assign $2\trapexc_$signal$67[0:0]$7444 $3\trapexc_$signal$67[0:0]$7452 - assign $2\trapexc_$signal$68[0:0]$7445 $3\trapexc_$signal$68[0:0]$7453 - assign $2\trapexc_$signal$69[0:0]$7446 $3\trapexc_$signal$69[0:0]$7454 - assign $2\trapexc_$signal$70[0:0]$7447 $3\trapexc_$signal$70[0:0]$7455 + assign $2\trapexc_$signal[0:0]$7488 $3\trapexc_$signal[0:0]$7496 + assign $2\trapexc_$signal$60[0:0]$7489 $3\trapexc_$signal$60[0:0]$7497 + assign $2\trapexc_$signal$61[0:0]$7490 $3\trapexc_$signal$61[0:0]$7498 + assign $2\trapexc_$signal$62[0:0]$7491 $3\trapexc_$signal$62[0:0]$7499 + assign $2\trapexc_$signal$67[0:0]$7492 $3\trapexc_$signal$67[0:0]$7500 + assign $2\trapexc_$signal$68[0:0]$7493 $3\trapexc_$signal$68[0:0]$7501 + assign $2\trapexc_$signal$69[0:0]$7494 $3\trapexc_$signal$69[0:0]$7502 + assign $2\trapexc_$signal$70[0:0]$7495 $3\trapexc_$signal$70[0:0]$7503 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -310111,54 +312608,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7455 $3\trapexc_$signal$62[0:0]$7451 $3\trapexc_$signal$60[0:0]$7449 $3\trapexc_$signal$61[0:0]$7450 $3\trapexc_$signal[0:0]$7448 $3\trapexc_$signal$69[0:0]$7454 $3\trapexc_$signal$68[0:0]$7453 $3\trapexc_$signal$67[0:0]$7452 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7503 $3\trapexc_$signal$62[0:0]$7499 $3\trapexc_$signal$60[0:0]$7497 $3\trapexc_$signal$61[0:0]$7498 $3\trapexc_$signal[0:0]$7496 $3\trapexc_$signal$69[0:0]$7502 $3\trapexc_$signal$68[0:0]$7501 $3\trapexc_$signal$67[0:0]$7500 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7448 1'0 - assign $3\trapexc_$signal$60[0:0]$7449 1'0 - assign $3\trapexc_$signal$61[0:0]$7450 1'0 - assign $3\trapexc_$signal$62[0:0]$7451 1'0 - assign $3\trapexc_$signal$67[0:0]$7452 1'0 - assign $3\trapexc_$signal$68[0:0]$7453 1'0 - assign $3\trapexc_$signal$69[0:0]$7454 1'0 - assign $3\trapexc_$signal$70[0:0]$7455 1'0 + assign $3\trapexc_$signal[0:0]$7496 1'0 + assign $3\trapexc_$signal$60[0:0]$7497 1'0 + assign $3\trapexc_$signal$61[0:0]$7498 1'0 + assign $3\trapexc_$signal$62[0:0]$7499 1'0 + assign $3\trapexc_$signal$67[0:0]$7500 1'0 + assign $3\trapexc_$signal$68[0:0]$7501 1'0 + assign $3\trapexc_$signal$69[0:0]$7502 1'0 + assign $3\trapexc_$signal$70[0:0]$7503 1'0 end case - assign $2\trapexc_$signal[0:0]$7440 1'0 - assign $2\trapexc_$signal$60[0:0]$7441 1'0 - assign $2\trapexc_$signal$61[0:0]$7442 1'0 - assign $2\trapexc_$signal$62[0:0]$7443 1'0 - assign $2\trapexc_$signal$67[0:0]$7444 1'0 - assign $2\trapexc_$signal$68[0:0]$7445 1'0 - assign $2\trapexc_$signal$69[0:0]$7446 1'0 - assign $2\trapexc_$signal$70[0:0]$7447 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7432 1'0 - assign $1\trapexc_$signal$60[0:0]$7433 1'0 - assign $1\trapexc_$signal$61[0:0]$7434 1'0 - assign $1\trapexc_$signal$62[0:0]$7435 1'0 - assign $1\trapexc_$signal$67[0:0]$7436 1'0 - assign $1\trapexc_$signal$68[0:0]$7437 1'0 - assign $1\trapexc_$signal$69[0:0]$7438 1'0 - assign $1\trapexc_$signal$70[0:0]$7439 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7424 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7425 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7426 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7427 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7428 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7429 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7430 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7431 - end - attribute \src "libresoc.v:148149.3-148160.6" - process $proc$libresoc.v:148149$7456 + assign $2\trapexc_$signal[0:0]$7488 1'0 + assign $2\trapexc_$signal$60[0:0]$7489 1'0 + assign $2\trapexc_$signal$61[0:0]$7490 1'0 + assign $2\trapexc_$signal$62[0:0]$7491 1'0 + assign $2\trapexc_$signal$67[0:0]$7492 1'0 + assign $2\trapexc_$signal$68[0:0]$7493 1'0 + assign $2\trapexc_$signal$69[0:0]$7494 1'0 + assign $2\trapexc_$signal$70[0:0]$7495 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7480 1'0 + assign $1\trapexc_$signal$60[0:0]$7481 1'0 + assign $1\trapexc_$signal$61[0:0]$7482 1'0 + assign $1\trapexc_$signal$62[0:0]$7483 1'0 + assign $1\trapexc_$signal$67[0:0]$7484 1'0 + assign $1\trapexc_$signal$68[0:0]$7485 1'0 + assign $1\trapexc_$signal$69[0:0]$7486 1'0 + assign $1\trapexc_$signal$70[0:0]$7487 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7472 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7473 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7474 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7475 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7476 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7477 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 + end + attribute \src "libresoc.v:149781.3-149792.6" + process $proc$libresoc.v:149781$7504 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:148150.5-148150.29" + attribute \src "libresoc.v:149782.5-149782.29" switch \initial - attribute \src "libresoc.v:148150.9-148150.17" + attribute \src "libresoc.v:149782.9-149782.17" case 1'1 case end @@ -310176,17 +312673,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:148161.3-148329.6" - process $proc$libresoc.v:148161$7457 + attribute \src "libresoc.v:149793.3-149961.6" + process $proc$libresoc.v:149793$7505 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:148162.5-148162.29" + attribute \src "libresoc.v:149794.5-149794.29" switch \initial - attribute \src "libresoc.v:148162.9-148162.17" + attribute \src "libresoc.v:149794.9-149794.17" case 1'1 case end @@ -310400,14 +312897,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:148330.3-148348.6" - process $proc$libresoc.v:148330$7458 + attribute \src "libresoc.v:149962.3-149980.6" + process $proc$libresoc.v:149962$7506 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148331.5-148331.29" + attribute \src "libresoc.v:149963.5-149963.29" switch \initial - attribute \src "libresoc.v:148331.9-148331.17" + attribute \src "libresoc.v:149963.9-149963.17" case 1'1 case end @@ -310429,14 +312926,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:148349.3-148367.6" - process $proc$libresoc.v:148349$7459 + attribute \src "libresoc.v:149981.3-149999.6" + process $proc$libresoc.v:149981$7507 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148350.5-148350.29" + attribute \src "libresoc.v:149982.5-149982.29" switch \initial - attribute \src "libresoc.v:148350.9-148350.17" + attribute \src "libresoc.v:149982.9-149982.17" case 1'1 case end @@ -310458,13 +312955,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148368.3-148379.6" - process $proc$libresoc.v:148368$7460 + attribute \src "libresoc.v:150000.3-150011.6" + process $proc$libresoc.v:150000$7508 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:148369.5-148369.29" + attribute \src "libresoc.v:150001.5-150001.29" switch \initial - attribute \src "libresoc.v:148369.9-148369.17" + attribute \src "libresoc.v:150001.9-150001.17" case 1'1 case end @@ -310482,13 +312979,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:148380.3-148391.6" - process $proc$libresoc.v:148380$7461 + attribute \src "libresoc.v:150012.3-150023.6" + process $proc$libresoc.v:150012$7509 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:148381.5-148381.29" + attribute \src "libresoc.v:150013.5-150013.29" switch \initial - attribute \src "libresoc.v:148381.9-148381.17" + attribute \src "libresoc.v:150013.9-150013.17" case 1'1 case end @@ -310506,43 +313003,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:147829$7362_Y - connect \$15 $pos$libresoc.v:147830$7364_Y - connect \$17 $lt$libresoc.v:147831$7365_Y - connect \$19 $gt$libresoc.v:147832$7366_Y - connect \$21 $lt$libresoc.v:147833$7367_Y - connect \$23 $gt$libresoc.v:147834$7368_Y - connect \$25 $eq$libresoc.v:147835$7369_Y - connect \$28 $and$libresoc.v:147836$7370_Y - connect \$27 $reduce_or$libresoc.v:147837$7371_Y - connect \$31 $reduce_or$libresoc.v:147838$7372_Y - connect \$33 $or$libresoc.v:147839$7373_Y - connect \$36 $sshl$libresoc.v:147840$7374_Y - connect \$35 $pos$libresoc.v:147841$7376_Y - connect \$40 $add$libresoc.v:147842$7377_Y - connect \$42 $eq$libresoc.v:147843$7378_Y - connect \$45 $and$libresoc.v:147844$7379_Y - connect \$44 $reduce_or$libresoc.v:147845$7380_Y - connect \$49 $and$libresoc.v:147846$7381_Y - connect \$48 $reduce_or$libresoc.v:147847$7382_Y - connect \$53 $and$libresoc.v:147848$7383_Y - connect \$52 $reduce_or$libresoc.v:147849$7384_Y - connect \$57 $and$libresoc.v:147850$7385_Y - connect \$56 $reduce_or$libresoc.v:147851$7386_Y - connect \$64 $and$libresoc.v:147852$7387_Y - connect \$63 $reduce_or$libresoc.v:147853$7388_Y - connect \$72 $and$libresoc.v:147854$7389_Y - connect \$71 $reduce_or$libresoc.v:147855$7390_Y - connect \$75 $pos$libresoc.v:147856$7392_Y - connect \$77 $eq$libresoc.v:147857$7393_Y - connect \$79 $eq$libresoc.v:147858$7394_Y - connect \$81 $eq$libresoc.v:147859$7395_Y - connect \$83 $and$libresoc.v:147860$7396_Y - connect \$85 $not$libresoc.v:147861$7397_Y - connect \$87 $not$libresoc.v:147862$7398_Y - connect \$89 $eq$libresoc.v:147863$7399_Y - connect \$91 $eq$libresoc.v:147864$7400_Y - connect \$93 $and$libresoc.v:147865$7401_Y + connect \$13 $pos$libresoc.v:149461$7410_Y + connect \$15 $pos$libresoc.v:149462$7412_Y + connect \$17 $lt$libresoc.v:149463$7413_Y + connect \$19 $gt$libresoc.v:149464$7414_Y + connect \$21 $lt$libresoc.v:149465$7415_Y + connect \$23 $gt$libresoc.v:149466$7416_Y + connect \$25 $eq$libresoc.v:149467$7417_Y + connect \$28 $and$libresoc.v:149468$7418_Y + connect \$27 $reduce_or$libresoc.v:149469$7419_Y + connect \$31 $reduce_or$libresoc.v:149470$7420_Y + connect \$33 $or$libresoc.v:149471$7421_Y + connect \$36 $sshl$libresoc.v:149472$7422_Y + connect \$35 $pos$libresoc.v:149473$7424_Y + connect \$40 $add$libresoc.v:149474$7425_Y + connect \$42 $eq$libresoc.v:149475$7426_Y + connect \$45 $and$libresoc.v:149476$7427_Y + connect \$44 $reduce_or$libresoc.v:149477$7428_Y + connect \$49 $and$libresoc.v:149478$7429_Y + connect \$48 $reduce_or$libresoc.v:149479$7430_Y + connect \$53 $and$libresoc.v:149480$7431_Y + connect \$52 $reduce_or$libresoc.v:149481$7432_Y + connect \$57 $and$libresoc.v:149482$7433_Y + connect \$56 $reduce_or$libresoc.v:149483$7434_Y + connect \$64 $and$libresoc.v:149484$7435_Y + connect \$63 $reduce_or$libresoc.v:149485$7436_Y + connect \$72 $and$libresoc.v:149486$7437_Y + connect \$71 $reduce_or$libresoc.v:149487$7438_Y + connect \$75 $pos$libresoc.v:149488$7440_Y + connect \$77 $eq$libresoc.v:149489$7441_Y + connect \$79 $eq$libresoc.v:149490$7442_Y + connect \$81 $eq$libresoc.v:149491$7443_Y + connect \$83 $and$libresoc.v:149492$7444_Y + connect \$85 $not$libresoc.v:149493$7445_Y + connect \$87 $not$libresoc.v:149494$7446_Y + connect \$89 $eq$libresoc.v:149495$7447_Y + connect \$91 $eq$libresoc.v:149496$7448_Y + connect \$93 $and$libresoc.v:149497$7449_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -310555,239 +313052,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:148407.1-149156.10" +attribute \src "libresoc.v:150039.1-150788.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:149123.3-149133.6" + attribute \src "libresoc.v:150755.3-150765.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:149068.3-149078.6" + attribute \src "libresoc.v:150700.3-150710.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:149046.3-149056.6" + attribute \src "libresoc.v:150678.3-150688.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:149035.3-149045.6" + attribute \src "libresoc.v:150667.3-150677.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:149024.3-149034.6" + attribute \src "libresoc.v:150656.3-150666.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:149112.3-149122.6" + attribute \src "libresoc.v:150744.3-150754.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:148408.7-148408.20" + attribute \src "libresoc.v:150040.7-150040.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149090.3-149100.6" + attribute \src "libresoc.v:150722.3-150732.6" wire $0\par0[0:0] - attribute \src "libresoc.v:149101.3-149111.6" + attribute \src "libresoc.v:150733.3-150743.6" wire $0\par1[0:0] - attribute \src "libresoc.v:149057.3-149067.6" + attribute \src "libresoc.v:150689.3-150699.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:149079.3-149089.6" + attribute \src "libresoc.v:150711.3-150721.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:149123.3-149133.6" + attribute \src "libresoc.v:150755.3-150765.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:149068.3-149078.6" + attribute \src "libresoc.v:150700.3-150710.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:149046.3-149056.6" + attribute \src "libresoc.v:150678.3-150688.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:149035.3-149045.6" + attribute \src "libresoc.v:150667.3-150677.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:149024.3-149034.6" + attribute \src "libresoc.v:150656.3-150666.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:149112.3-149122.6" + attribute \src "libresoc.v:150744.3-150754.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149090.3-149100.6" + attribute \src "libresoc.v:150722.3-150732.6" wire $1\par0[0:0] - attribute \src "libresoc.v:149101.3-149111.6" + attribute \src "libresoc.v:150733.3-150743.6" wire $1\par1[0:0] - attribute \src "libresoc.v:149057.3-149067.6" + attribute \src "libresoc.v:150689.3-150699.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:149079.3-149089.6" + attribute \src "libresoc.v:150711.3-150721.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:149134.3-149152.6" + attribute \src "libresoc.v:150766.3-150784.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:148969.3-149023.6" + attribute \src "libresoc.v:150601.3-150655.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:148916.18-148916.103" - wire width 64 $and$libresoc.v:148916$7509_Y - attribute \src "libresoc.v:148875.18-148875.118" - wire $eq$libresoc.v:148875$7463_Y - attribute \src "libresoc.v:148876.19-148876.119" - wire $eq$libresoc.v:148876$7464_Y - attribute \src "libresoc.v:148877.19-148877.119" - wire $eq$libresoc.v:148877$7465_Y - attribute \src "libresoc.v:148878.19-148878.119" - wire $eq$libresoc.v:148878$7466_Y - attribute \src "libresoc.v:148879.19-148879.119" - wire $eq$libresoc.v:148879$7467_Y - attribute \src "libresoc.v:148880.19-148880.119" - wire $eq$libresoc.v:148880$7468_Y - attribute \src "libresoc.v:148881.19-148881.119" - wire $eq$libresoc.v:148881$7469_Y - attribute \src "libresoc.v:148882.19-148882.119" - wire $eq$libresoc.v:148882$7470_Y - attribute \src "libresoc.v:148883.19-148883.119" - wire $eq$libresoc.v:148883$7471_Y - attribute \src "libresoc.v:148884.19-148884.119" - wire $eq$libresoc.v:148884$7472_Y - attribute \src "libresoc.v:148885.19-148885.119" - wire $eq$libresoc.v:148885$7473_Y - attribute \src "libresoc.v:148886.19-148886.119" - wire $eq$libresoc.v:148886$7474_Y - attribute \src "libresoc.v:148887.19-148887.119" - wire $eq$libresoc.v:148887$7475_Y - attribute \src "libresoc.v:148888.19-148888.119" - wire $eq$libresoc.v:148888$7476_Y - attribute \src "libresoc.v:148889.19-148889.119" - wire $eq$libresoc.v:148889$7477_Y - attribute \src "libresoc.v:148890.19-148890.119" - wire $eq$libresoc.v:148890$7478_Y - attribute \src "libresoc.v:148891.19-148891.119" - wire $eq$libresoc.v:148891$7479_Y - attribute \src "libresoc.v:148892.19-148892.119" - wire $eq$libresoc.v:148892$7480_Y - attribute \src "libresoc.v:148893.19-148893.119" - wire $eq$libresoc.v:148893$7481_Y - attribute \src "libresoc.v:148894.19-148894.119" - wire $eq$libresoc.v:148894$7482_Y - attribute \src "libresoc.v:148895.19-148895.119" - wire $eq$libresoc.v:148895$7483_Y - attribute \src "libresoc.v:148896.19-148896.119" - wire $eq$libresoc.v:148896$7484_Y - attribute \src "libresoc.v:148897.19-148897.119" - wire $eq$libresoc.v:148897$7485_Y - attribute \src "libresoc.v:148898.19-148898.119" - wire $eq$libresoc.v:148898$7486_Y - attribute \src "libresoc.v:148899.19-148899.119" - wire $eq$libresoc.v:148899$7487_Y - attribute \src "libresoc.v:148900.19-148900.119" - wire $eq$libresoc.v:148900$7488_Y - attribute \src "libresoc.v:148901.19-148901.119" - wire $eq$libresoc.v:148901$7489_Y - attribute \src "libresoc.v:148902.19-148902.119" - wire $eq$libresoc.v:148902$7490_Y - attribute \src "libresoc.v:148903.19-148903.128" - wire $eq$libresoc.v:148903$7491_Y - attribute \src "libresoc.v:148919.18-148919.114" - wire $eq$libresoc.v:148919$7512_Y - attribute \src "libresoc.v:148920.18-148920.114" - wire $eq$libresoc.v:148920$7513_Y - attribute \src "libresoc.v:148921.18-148921.114" - wire $eq$libresoc.v:148921$7514_Y - attribute \src "libresoc.v:148922.18-148922.114" - wire $eq$libresoc.v:148922$7515_Y - attribute \src "libresoc.v:148923.18-148923.114" - wire $eq$libresoc.v:148923$7516_Y - attribute \src "libresoc.v:148924.18-148924.114" - wire $eq$libresoc.v:148924$7517_Y - attribute \src "libresoc.v:148925.18-148925.114" - wire $eq$libresoc.v:148925$7518_Y - attribute \src "libresoc.v:148926.18-148926.114" - wire $eq$libresoc.v:148926$7519_Y - attribute \src "libresoc.v:148927.18-148927.116" - wire $eq$libresoc.v:148927$7520_Y - attribute \src "libresoc.v:148928.18-148928.116" - wire $eq$libresoc.v:148928$7521_Y - attribute \src "libresoc.v:148929.18-148929.116" - wire $eq$libresoc.v:148929$7522_Y - attribute \src "libresoc.v:148930.18-148930.116" - wire $eq$libresoc.v:148930$7523_Y - attribute \src "libresoc.v:148931.18-148931.116" - wire $eq$libresoc.v:148931$7524_Y - attribute \src "libresoc.v:148932.18-148932.116" - wire $eq$libresoc.v:148932$7525_Y - attribute \src "libresoc.v:148933.18-148933.116" - wire $eq$libresoc.v:148933$7526_Y - attribute \src "libresoc.v:148934.18-148934.116" - wire $eq$libresoc.v:148934$7527_Y - attribute \src "libresoc.v:148935.18-148935.118" - wire $eq$libresoc.v:148935$7528_Y - attribute \src "libresoc.v:148936.18-148936.118" - wire $eq$libresoc.v:148936$7529_Y - attribute \src "libresoc.v:148937.18-148937.118" - wire $eq$libresoc.v:148937$7530_Y - attribute \src "libresoc.v:148938.18-148938.118" - wire $eq$libresoc.v:148938$7531_Y - attribute \src "libresoc.v:148939.18-148939.118" - wire $eq$libresoc.v:148939$7532_Y - attribute \src "libresoc.v:148940.18-148940.118" - wire $eq$libresoc.v:148940$7533_Y - attribute \src "libresoc.v:148941.18-148941.118" - wire $eq$libresoc.v:148941$7534_Y - attribute \src "libresoc.v:148942.18-148942.118" - wire $eq$libresoc.v:148942$7535_Y - attribute \src "libresoc.v:148943.18-148943.118" - wire $eq$libresoc.v:148943$7536_Y - attribute \src "libresoc.v:148944.18-148944.118" - wire $eq$libresoc.v:148944$7537_Y - attribute \src "libresoc.v:148945.18-148945.118" - wire $eq$libresoc.v:148945$7538_Y - attribute \src "libresoc.v:148946.18-148946.118" - wire $eq$libresoc.v:148946$7539_Y - attribute \src "libresoc.v:148947.18-148947.118" - wire $eq$libresoc.v:148947$7540_Y - attribute \src "libresoc.v:148948.18-148948.118" - wire $eq$libresoc.v:148948$7541_Y - attribute \src "libresoc.v:148949.18-148949.118" - wire $eq$libresoc.v:148949$7542_Y - attribute \src "libresoc.v:148950.18-148950.118" - wire $eq$libresoc.v:148950$7543_Y - attribute \src "libresoc.v:148951.18-148951.118" - wire $eq$libresoc.v:148951$7544_Y - attribute \src "libresoc.v:148952.18-148952.118" - wire $eq$libresoc.v:148952$7545_Y - attribute \src "libresoc.v:148953.18-148953.118" - wire $eq$libresoc.v:148953$7546_Y - attribute \src "libresoc.v:148954.18-148954.118" - wire $eq$libresoc.v:148954$7547_Y - attribute \src "libresoc.v:148905.19-148905.104" - wire width 64 $extend$libresoc.v:148905$7493_Y - attribute \src "libresoc.v:148907.19-148907.93" - wire width 8 $extend$libresoc.v:148907$7496_Y - attribute \src "libresoc.v:148909.19-148909.105" - wire width 64 $extend$libresoc.v:148909$7499_Y - attribute \src "libresoc.v:148910.19-148910.118" - wire width 64 $extend$libresoc.v:148910$7501_Y - attribute \src "libresoc.v:148914.19-148914.105" - wire width 64 $extend$libresoc.v:148914$7506_Y - attribute \src "libresoc.v:148917.18-148917.103" - wire width 64 $or$libresoc.v:148917$7510_Y - attribute \src "libresoc.v:148905.19-148905.104" - wire width 64 $pos$libresoc.v:148905$7494_Y - attribute \src "libresoc.v:148907.19-148907.93" - wire width 8 $pos$libresoc.v:148907$7497_Y - attribute \src "libresoc.v:148909.19-148909.105" - wire width 64 $pos$libresoc.v:148909$7500_Y - attribute \src "libresoc.v:148910.19-148910.118" - wire width 64 $pos$libresoc.v:148910$7502_Y - attribute \src "libresoc.v:148914.19-148914.105" - wire width 64 $pos$libresoc.v:148914$7507_Y - attribute \src "libresoc.v:148911.19-148911.131" - wire $reduce_xor$libresoc.v:148911$7503_Y - attribute \src "libresoc.v:148912.19-148912.133" - wire $reduce_xor$libresoc.v:148912$7504_Y - attribute \src "libresoc.v:148906.19-148906.112" - wire width 8 $sub$libresoc.v:148906$7495_Y - attribute \src "libresoc.v:148908.19-148908.135" - wire width 8 $ternary$libresoc.v:148908$7498_Y - attribute \src "libresoc.v:148913.19-148913.398" - wire width 32 $ternary$libresoc.v:148913$7505_Y - attribute \src "libresoc.v:148915.19-148915.621" - wire width 64 $ternary$libresoc.v:148915$7508_Y - attribute \src "libresoc.v:148904.19-148904.108" - wire $xor$libresoc.v:148904$7492_Y - attribute \src "libresoc.v:148918.18-148918.103" - wire width 64 $xor$libresoc.v:148918$7511_Y + attribute \src "libresoc.v:150548.18-150548.103" + wire width 64 $and$libresoc.v:150548$7557_Y + attribute \src "libresoc.v:150507.18-150507.118" + wire $eq$libresoc.v:150507$7511_Y + attribute \src "libresoc.v:150508.19-150508.119" + wire $eq$libresoc.v:150508$7512_Y + attribute \src "libresoc.v:150509.19-150509.119" + wire $eq$libresoc.v:150509$7513_Y + attribute \src "libresoc.v:150510.19-150510.119" + wire $eq$libresoc.v:150510$7514_Y + attribute \src "libresoc.v:150511.19-150511.119" + wire $eq$libresoc.v:150511$7515_Y + attribute \src "libresoc.v:150512.19-150512.119" + wire $eq$libresoc.v:150512$7516_Y + attribute \src "libresoc.v:150513.19-150513.119" + wire $eq$libresoc.v:150513$7517_Y + attribute \src "libresoc.v:150514.19-150514.119" + wire $eq$libresoc.v:150514$7518_Y + attribute \src "libresoc.v:150515.19-150515.119" + wire $eq$libresoc.v:150515$7519_Y + attribute \src "libresoc.v:150516.19-150516.119" + wire $eq$libresoc.v:150516$7520_Y + attribute \src "libresoc.v:150517.19-150517.119" + wire $eq$libresoc.v:150517$7521_Y + attribute \src "libresoc.v:150518.19-150518.119" + wire $eq$libresoc.v:150518$7522_Y + attribute \src "libresoc.v:150519.19-150519.119" + wire $eq$libresoc.v:150519$7523_Y + attribute \src "libresoc.v:150520.19-150520.119" + wire $eq$libresoc.v:150520$7524_Y + attribute \src "libresoc.v:150521.19-150521.119" + wire $eq$libresoc.v:150521$7525_Y + attribute \src "libresoc.v:150522.19-150522.119" + wire $eq$libresoc.v:150522$7526_Y + attribute \src "libresoc.v:150523.19-150523.119" + wire $eq$libresoc.v:150523$7527_Y + attribute \src "libresoc.v:150524.19-150524.119" + wire $eq$libresoc.v:150524$7528_Y + attribute \src "libresoc.v:150525.19-150525.119" + wire $eq$libresoc.v:150525$7529_Y + attribute \src "libresoc.v:150526.19-150526.119" + wire $eq$libresoc.v:150526$7530_Y + attribute \src "libresoc.v:150527.19-150527.119" + wire $eq$libresoc.v:150527$7531_Y + attribute \src "libresoc.v:150528.19-150528.119" + wire $eq$libresoc.v:150528$7532_Y + attribute \src "libresoc.v:150529.19-150529.119" + wire $eq$libresoc.v:150529$7533_Y + attribute \src "libresoc.v:150530.19-150530.119" + wire $eq$libresoc.v:150530$7534_Y + attribute \src "libresoc.v:150531.19-150531.119" + wire $eq$libresoc.v:150531$7535_Y + attribute \src "libresoc.v:150532.19-150532.119" + wire $eq$libresoc.v:150532$7536_Y + attribute \src "libresoc.v:150533.19-150533.119" + wire $eq$libresoc.v:150533$7537_Y + attribute \src "libresoc.v:150534.19-150534.119" + wire $eq$libresoc.v:150534$7538_Y + attribute \src "libresoc.v:150535.19-150535.128" + wire $eq$libresoc.v:150535$7539_Y + attribute \src "libresoc.v:150551.18-150551.114" + wire $eq$libresoc.v:150551$7560_Y + attribute \src "libresoc.v:150552.18-150552.114" + wire $eq$libresoc.v:150552$7561_Y + attribute \src "libresoc.v:150553.18-150553.114" + wire $eq$libresoc.v:150553$7562_Y + attribute \src "libresoc.v:150554.18-150554.114" + wire $eq$libresoc.v:150554$7563_Y + attribute \src "libresoc.v:150555.18-150555.114" + wire $eq$libresoc.v:150555$7564_Y + attribute \src "libresoc.v:150556.18-150556.114" + wire $eq$libresoc.v:150556$7565_Y + attribute \src "libresoc.v:150557.18-150557.114" + wire $eq$libresoc.v:150557$7566_Y + attribute \src "libresoc.v:150558.18-150558.114" + wire $eq$libresoc.v:150558$7567_Y + attribute \src "libresoc.v:150559.18-150559.116" + wire $eq$libresoc.v:150559$7568_Y + attribute \src "libresoc.v:150560.18-150560.116" + wire $eq$libresoc.v:150560$7569_Y + attribute \src "libresoc.v:150561.18-150561.116" + wire $eq$libresoc.v:150561$7570_Y + attribute \src "libresoc.v:150562.18-150562.116" + wire $eq$libresoc.v:150562$7571_Y + attribute \src "libresoc.v:150563.18-150563.116" + wire $eq$libresoc.v:150563$7572_Y + attribute \src "libresoc.v:150564.18-150564.116" + wire $eq$libresoc.v:150564$7573_Y + attribute \src "libresoc.v:150565.18-150565.116" + wire $eq$libresoc.v:150565$7574_Y + attribute \src "libresoc.v:150566.18-150566.116" + wire $eq$libresoc.v:150566$7575_Y + attribute \src "libresoc.v:150567.18-150567.118" + wire $eq$libresoc.v:150567$7576_Y + attribute \src "libresoc.v:150568.18-150568.118" + wire $eq$libresoc.v:150568$7577_Y + attribute \src "libresoc.v:150569.18-150569.118" + wire $eq$libresoc.v:150569$7578_Y + attribute \src "libresoc.v:150570.18-150570.118" + wire $eq$libresoc.v:150570$7579_Y + attribute \src "libresoc.v:150571.18-150571.118" + wire $eq$libresoc.v:150571$7580_Y + attribute \src "libresoc.v:150572.18-150572.118" + wire $eq$libresoc.v:150572$7581_Y + attribute \src "libresoc.v:150573.18-150573.118" + wire $eq$libresoc.v:150573$7582_Y + attribute \src "libresoc.v:150574.18-150574.118" + wire $eq$libresoc.v:150574$7583_Y + attribute \src "libresoc.v:150575.18-150575.118" + wire $eq$libresoc.v:150575$7584_Y + attribute \src "libresoc.v:150576.18-150576.118" + wire $eq$libresoc.v:150576$7585_Y + attribute \src "libresoc.v:150577.18-150577.118" + wire $eq$libresoc.v:150577$7586_Y + attribute \src "libresoc.v:150578.18-150578.118" + wire $eq$libresoc.v:150578$7587_Y + attribute \src "libresoc.v:150579.18-150579.118" + wire $eq$libresoc.v:150579$7588_Y + attribute \src "libresoc.v:150580.18-150580.118" + wire $eq$libresoc.v:150580$7589_Y + attribute \src "libresoc.v:150581.18-150581.118" + wire $eq$libresoc.v:150581$7590_Y + attribute \src "libresoc.v:150582.18-150582.118" + wire $eq$libresoc.v:150582$7591_Y + attribute \src "libresoc.v:150583.18-150583.118" + wire $eq$libresoc.v:150583$7592_Y + attribute \src "libresoc.v:150584.18-150584.118" + wire $eq$libresoc.v:150584$7593_Y + attribute \src "libresoc.v:150585.18-150585.118" + wire $eq$libresoc.v:150585$7594_Y + attribute \src "libresoc.v:150586.18-150586.118" + wire $eq$libresoc.v:150586$7595_Y + attribute \src "libresoc.v:150537.19-150537.104" + wire width 64 $extend$libresoc.v:150537$7541_Y + attribute \src "libresoc.v:150539.19-150539.93" + wire width 8 $extend$libresoc.v:150539$7544_Y + attribute \src "libresoc.v:150541.19-150541.105" + wire width 64 $extend$libresoc.v:150541$7547_Y + attribute \src "libresoc.v:150542.19-150542.118" + wire width 64 $extend$libresoc.v:150542$7549_Y + attribute \src "libresoc.v:150546.19-150546.105" + wire width 64 $extend$libresoc.v:150546$7554_Y + attribute \src "libresoc.v:150549.18-150549.103" + wire width 64 $or$libresoc.v:150549$7558_Y + attribute \src "libresoc.v:150537.19-150537.104" + wire width 64 $pos$libresoc.v:150537$7542_Y + attribute \src "libresoc.v:150539.19-150539.93" + wire width 8 $pos$libresoc.v:150539$7545_Y + attribute \src "libresoc.v:150541.19-150541.105" + wire width 64 $pos$libresoc.v:150541$7548_Y + attribute \src "libresoc.v:150542.19-150542.118" + wire width 64 $pos$libresoc.v:150542$7550_Y + attribute \src "libresoc.v:150546.19-150546.105" + wire width 64 $pos$libresoc.v:150546$7555_Y + attribute \src "libresoc.v:150543.19-150543.131" + wire $reduce_xor$libresoc.v:150543$7551_Y + attribute \src "libresoc.v:150544.19-150544.133" + wire $reduce_xor$libresoc.v:150544$7552_Y + attribute \src "libresoc.v:150538.19-150538.112" + wire width 8 $sub$libresoc.v:150538$7543_Y + attribute \src "libresoc.v:150540.19-150540.135" + wire width 8 $ternary$libresoc.v:150540$7546_Y + attribute \src "libresoc.v:150545.19-150545.398" + wire width 32 $ternary$libresoc.v:150545$7553_Y + attribute \src "libresoc.v:150547.19-150547.621" + wire width 64 $ternary$libresoc.v:150547$7556_Y + attribute \src "libresoc.v:150536.19-150536.108" + wire $xor$libresoc.v:150536$7540_Y + attribute \src "libresoc.v:150550.18-150550.103" + wire width 64 $xor$libresoc.v:150550$7559_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -310966,7 +313463,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:148408.7-148408.15" + attribute \src "libresoc.v:150040.7-150040.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -311255,7 +313752,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:148916$7509 + cell $and $and$libresoc.v:150548$7557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311263,10 +313760,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:148916$7509_Y + connect \Y $and$libresoc.v:150548$7557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148875$7463 + cell $eq $eq$libresoc.v:150507$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311274,10 +313771,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148875$7463_Y + connect \Y $eq$libresoc.v:150507$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148876$7464 + cell $eq $eq$libresoc.v:150508$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311285,10 +313782,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148876$7464_Y + connect \Y $eq$libresoc.v:150508$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148877$7465 + cell $eq $eq$libresoc.v:150509$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311296,10 +313793,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148877$7465_Y + connect \Y $eq$libresoc.v:150509$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148878$7466 + cell $eq $eq$libresoc.v:150510$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311307,10 +313804,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148878$7466_Y + connect \Y $eq$libresoc.v:150510$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148879$7467 + cell $eq $eq$libresoc.v:150511$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311318,10 +313815,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148879$7467_Y + connect \Y $eq$libresoc.v:150511$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148880$7468 + cell $eq $eq$libresoc.v:150512$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311329,10 +313826,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148880$7468_Y + connect \Y $eq$libresoc.v:150512$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148881$7469 + cell $eq $eq$libresoc.v:150513$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311340,10 +313837,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148881$7469_Y + connect \Y $eq$libresoc.v:150513$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148882$7470 + cell $eq $eq$libresoc.v:150514$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311351,10 +313848,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148882$7470_Y + connect \Y $eq$libresoc.v:150514$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148883$7471 + cell $eq $eq$libresoc.v:150515$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311362,10 +313859,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148883$7471_Y + connect \Y $eq$libresoc.v:150515$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148884$7472 + cell $eq $eq$libresoc.v:150516$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311373,10 +313870,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148884$7472_Y + connect \Y $eq$libresoc.v:150516$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148885$7473 + cell $eq $eq$libresoc.v:150517$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311384,10 +313881,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148885$7473_Y + connect \Y $eq$libresoc.v:150517$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148886$7474 + cell $eq $eq$libresoc.v:150518$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311395,10 +313892,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:148886$7474_Y + connect \Y $eq$libresoc.v:150518$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148887$7475 + cell $eq $eq$libresoc.v:150519$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311406,10 +313903,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148887$7475_Y + connect \Y $eq$libresoc.v:150519$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148888$7476 + cell $eq $eq$libresoc.v:150520$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311417,10 +313914,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148888$7476_Y + connect \Y $eq$libresoc.v:150520$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148889$7477 + cell $eq $eq$libresoc.v:150521$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311428,10 +313925,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148889$7477_Y + connect \Y $eq$libresoc.v:150521$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148890$7478 + cell $eq $eq$libresoc.v:150522$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311439,10 +313936,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148890$7478_Y + connect \Y $eq$libresoc.v:150522$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148891$7479 + cell $eq $eq$libresoc.v:150523$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311450,10 +313947,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148891$7479_Y + connect \Y $eq$libresoc.v:150523$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148892$7480 + cell $eq $eq$libresoc.v:150524$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311461,10 +313958,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148892$7480_Y + connect \Y $eq$libresoc.v:150524$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148893$7481 + cell $eq $eq$libresoc.v:150525$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311472,10 +313969,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148893$7481_Y + connect \Y $eq$libresoc.v:150525$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148894$7482 + cell $eq $eq$libresoc.v:150526$7530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311483,10 +313980,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:148894$7482_Y + connect \Y $eq$libresoc.v:150526$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148895$7483 + cell $eq $eq$libresoc.v:150527$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311494,10 +313991,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148895$7483_Y + connect \Y $eq$libresoc.v:150527$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148896$7484 + cell $eq $eq$libresoc.v:150528$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311505,10 +314002,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148896$7484_Y + connect \Y $eq$libresoc.v:150528$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148897$7485 + cell $eq $eq$libresoc.v:150529$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311516,10 +314013,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148897$7485_Y + connect \Y $eq$libresoc.v:150529$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148898$7486 + cell $eq $eq$libresoc.v:150530$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311527,10 +314024,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148898$7486_Y + connect \Y $eq$libresoc.v:150530$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148899$7487 + cell $eq $eq$libresoc.v:150531$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311538,10 +314035,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148899$7487_Y + connect \Y $eq$libresoc.v:150531$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148900$7488 + cell $eq $eq$libresoc.v:150532$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311549,10 +314046,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148900$7488_Y + connect \Y $eq$libresoc.v:150532$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148901$7489 + cell $eq $eq$libresoc.v:150533$7537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311560,10 +314057,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148901$7489_Y + connect \Y $eq$libresoc.v:150533$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148902$7490 + cell $eq $eq$libresoc.v:150534$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311571,10 +314068,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:148902$7490_Y + connect \Y $eq$libresoc.v:150534$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:148903$7491 + cell $eq $eq$libresoc.v:150535$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311582,10 +314079,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:148903$7491_Y + connect \Y $eq$libresoc.v:150535$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148919$7512 + cell $eq $eq$libresoc.v:150551$7560 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311593,10 +314090,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148919$7512_Y + connect \Y $eq$libresoc.v:150551$7560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148920$7513 + cell $eq $eq$libresoc.v:150552$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311604,10 +314101,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148920$7513_Y + connect \Y $eq$libresoc.v:150552$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148921$7514 + cell $eq $eq$libresoc.v:150553$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311615,10 +314112,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148921$7514_Y + connect \Y $eq$libresoc.v:150553$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148922$7515 + cell $eq $eq$libresoc.v:150554$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311626,10 +314123,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148922$7515_Y + connect \Y $eq$libresoc.v:150554$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148923$7516 + cell $eq $eq$libresoc.v:150555$7564 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311637,10 +314134,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148923$7516_Y + connect \Y $eq$libresoc.v:150555$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148924$7517 + cell $eq $eq$libresoc.v:150556$7565 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311648,10 +314145,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148924$7517_Y + connect \Y $eq$libresoc.v:150556$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148925$7518 + cell $eq $eq$libresoc.v:150557$7566 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311659,10 +314156,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148925$7518_Y + connect \Y $eq$libresoc.v:150557$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148926$7519 + cell $eq $eq$libresoc.v:150558$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311670,10 +314167,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:148926$7519_Y + connect \Y $eq$libresoc.v:150558$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148927$7520 + cell $eq $eq$libresoc.v:150559$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311681,10 +314178,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148927$7520_Y + connect \Y $eq$libresoc.v:150559$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148928$7521 + cell $eq $eq$libresoc.v:150560$7569 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311692,10 +314189,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148928$7521_Y + connect \Y $eq$libresoc.v:150560$7569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148929$7522 + cell $eq $eq$libresoc.v:150561$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311703,10 +314200,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148929$7522_Y + connect \Y $eq$libresoc.v:150561$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148930$7523 + cell $eq $eq$libresoc.v:150562$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311714,10 +314211,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148930$7523_Y + connect \Y $eq$libresoc.v:150562$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148931$7524 + cell $eq $eq$libresoc.v:150563$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311725,10 +314222,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148931$7524_Y + connect \Y $eq$libresoc.v:150563$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148932$7525 + cell $eq $eq$libresoc.v:150564$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311736,10 +314233,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148932$7525_Y + connect \Y $eq$libresoc.v:150564$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148933$7526 + cell $eq $eq$libresoc.v:150565$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311747,10 +314244,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148933$7526_Y + connect \Y $eq$libresoc.v:150565$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148934$7527 + cell $eq $eq$libresoc.v:150566$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311758,10 +314255,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:148934$7527_Y + connect \Y $eq$libresoc.v:150566$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148935$7528 + cell $eq $eq$libresoc.v:150567$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311769,10 +314266,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148935$7528_Y + connect \Y $eq$libresoc.v:150567$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148936$7529 + cell $eq $eq$libresoc.v:150568$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311780,10 +314277,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148936$7529_Y + connect \Y $eq$libresoc.v:150568$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148937$7530 + cell $eq $eq$libresoc.v:150569$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311791,10 +314288,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148937$7530_Y + connect \Y $eq$libresoc.v:150569$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148938$7531 + cell $eq $eq$libresoc.v:150570$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311802,10 +314299,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148938$7531_Y + connect \Y $eq$libresoc.v:150570$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148939$7532 + cell $eq $eq$libresoc.v:150571$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311813,10 +314310,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148939$7532_Y + connect \Y $eq$libresoc.v:150571$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148940$7533 + cell $eq $eq$libresoc.v:150572$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311824,10 +314321,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148940$7533_Y + connect \Y $eq$libresoc.v:150572$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148941$7534 + cell $eq $eq$libresoc.v:150573$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311835,10 +314332,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148941$7534_Y + connect \Y $eq$libresoc.v:150573$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148942$7535 + cell $eq $eq$libresoc.v:150574$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311846,10 +314343,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:148942$7535_Y + connect \Y $eq$libresoc.v:150574$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148943$7536 + cell $eq $eq$libresoc.v:150575$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311857,10 +314354,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148943$7536_Y + connect \Y $eq$libresoc.v:150575$7584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148944$7537 + cell $eq $eq$libresoc.v:150576$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311868,10 +314365,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148944$7537_Y + connect \Y $eq$libresoc.v:150576$7585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148945$7538 + cell $eq $eq$libresoc.v:150577$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311879,10 +314376,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148945$7538_Y + connect \Y $eq$libresoc.v:150577$7586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148946$7539 + cell $eq $eq$libresoc.v:150578$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311890,10 +314387,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148946$7539_Y + connect \Y $eq$libresoc.v:150578$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148947$7540 + cell $eq $eq$libresoc.v:150579$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311901,10 +314398,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148947$7540_Y + connect \Y $eq$libresoc.v:150579$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148948$7541 + cell $eq $eq$libresoc.v:150580$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311912,10 +314409,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148948$7541_Y + connect \Y $eq$libresoc.v:150580$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148949$7542 + cell $eq $eq$libresoc.v:150581$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311923,10 +314420,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148949$7542_Y + connect \Y $eq$libresoc.v:150581$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148950$7543 + cell $eq $eq$libresoc.v:150582$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311934,10 +314431,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:148950$7543_Y + connect \Y $eq$libresoc.v:150582$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148951$7544 + cell $eq $eq$libresoc.v:150583$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311945,10 +314442,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148951$7544_Y + connect \Y $eq$libresoc.v:150583$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148952$7545 + cell $eq $eq$libresoc.v:150584$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311956,10 +314453,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148952$7545_Y + connect \Y $eq$libresoc.v:150584$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148953$7546 + cell $eq $eq$libresoc.v:150585$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311967,10 +314464,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148953$7546_Y + connect \Y $eq$libresoc.v:150585$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:148954$7547 + cell $eq $eq$libresoc.v:150586$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311978,50 +314475,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:148954$7547_Y + connect \Y $eq$libresoc.v:150586$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:148905$7493 + cell $pos $extend$libresoc.v:150537$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:148905$7493_Y + connect \Y $extend$libresoc.v:150537$7541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:148907$7496 + cell $pos $extend$libresoc.v:150539$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:148907$7496_Y + connect \Y $extend$libresoc.v:150539$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:148909$7499 + cell $pos $extend$libresoc.v:150541$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:148909$7499_Y + connect \Y $extend$libresoc.v:150541$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:148910$7501 + cell $pos $extend$libresoc.v:150542$7549 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:148910$7501_Y + connect \Y $extend$libresoc.v:150542$7549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:148914$7506 + cell $pos $extend$libresoc.v:150546$7554 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:148914$7506_Y + connect \Y $extend$libresoc.v:150546$7554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:148917$7510 + cell $or $or$libresoc.v:150549$7558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312029,66 +314526,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:148917$7510_Y + connect \Y $or$libresoc.v:150549$7558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:148905$7494 + cell $pos $pos$libresoc.v:150537$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148905$7493_Y - connect \Y $pos$libresoc.v:148905$7494_Y + connect \A $extend$libresoc.v:150537$7541_Y + connect \Y $pos$libresoc.v:150537$7542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:148907$7497 + cell $pos $pos$libresoc.v:150539$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:148907$7496_Y - connect \Y $pos$libresoc.v:148907$7497_Y + connect \A $extend$libresoc.v:150539$7544_Y + connect \Y $pos$libresoc.v:150539$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:148909$7500 + cell $pos $pos$libresoc.v:150541$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148909$7499_Y - connect \Y $pos$libresoc.v:148909$7500_Y + connect \A $extend$libresoc.v:150541$7547_Y + connect \Y $pos$libresoc.v:150541$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:148910$7502 + cell $pos $pos$libresoc.v:150542$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148910$7501_Y - connect \Y $pos$libresoc.v:148910$7502_Y + connect \A $extend$libresoc.v:150542$7549_Y + connect \Y $pos$libresoc.v:150542$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:148914$7507 + cell $pos $pos$libresoc.v:150546$7555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148914$7506_Y - connect \Y $pos$libresoc.v:148914$7507_Y + connect \A $extend$libresoc.v:150546$7554_Y + connect \Y $pos$libresoc.v:150546$7555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:148911$7503 + cell $reduce_xor $reduce_xor$libresoc.v:150543$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:148911$7503_Y + connect \Y $reduce_xor$libresoc.v:150543$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:148912$7504 + cell $reduce_xor $reduce_xor$libresoc.v:150544$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:148912$7504_Y + connect \Y $reduce_xor$libresoc.v:150544$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:148906$7495 + cell $sub $sub$libresoc.v:150538$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -312096,34 +314593,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:148906$7495_Y + connect \Y $sub$libresoc.v:150538$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:148908$7498 + cell $mux $ternary$libresoc.v:150540$7546 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:148908$7498_Y + connect \Y $ternary$libresoc.v:150540$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:148913$7505 + cell $mux $ternary$libresoc.v:150545$7553 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:148913$7505_Y + connect \Y $ternary$libresoc.v:150545$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:148915$7508 + cell $mux $ternary$libresoc.v:150547$7556 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:148915$7508_Y + connect \Y $ternary$libresoc.v:150547$7556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:148904$7492 + cell $xor $xor$libresoc.v:150536$7540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312131,10 +314628,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:148904$7492_Y + connect \Y $xor$libresoc.v:150536$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:148918$7511 + cell $xor $xor$libresoc.v:150550$7559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312142,47 +314639,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:148918$7511_Y + connect \Y $xor$libresoc.v:150550$7559_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:148955.10-148959.4" + attribute \src "libresoc.v:150587.10-150591.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:148960.7-148963.4" + attribute \src "libresoc.v:150592.7-150595.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:148964.12-148968.4" + attribute \src "libresoc.v:150596.12-150600.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:148408.7-148408.20" - process $proc$libresoc.v:148408$7560 + attribute \src "libresoc.v:150040.7-150040.20" + process $proc$libresoc.v:150040$7608 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148969.3-149023.6" - process $proc$libresoc.v:148969$7548 + attribute \src "libresoc.v:150601.3-150655.6" + process $proc$libresoc.v:150601$7596 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148970.5-148970.29" + attribute \src "libresoc.v:150602.5-150602.29" switch \initial - attribute \src "libresoc.v:148970.9-148970.17" + attribute \src "libresoc.v:150602.9-150602.17" case 1'1 case end @@ -312250,14 +314747,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:149024.3-149034.6" - process $proc$libresoc.v:149024$7549 + attribute \src "libresoc.v:150656.3-150666.6" + process $proc$libresoc.v:150656$7597 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:149025.5-149025.29" + attribute \src "libresoc.v:150657.5-150657.29" switch \initial - attribute \src "libresoc.v:149025.9-149025.17" + attribute \src "libresoc.v:150657.9-150657.17" case 1'1 case end @@ -312273,14 +314770,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:149035.3-149045.6" - process $proc$libresoc.v:149035$7550 + attribute \src "libresoc.v:150667.3-150677.6" + process $proc$libresoc.v:150667$7598 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:149036.5-149036.29" + attribute \src "libresoc.v:150668.5-150668.29" switch \initial - attribute \src "libresoc.v:149036.9-149036.17" + attribute \src "libresoc.v:150668.9-150668.17" case 1'1 case end @@ -312296,14 +314793,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:149046.3-149056.6" - process $proc$libresoc.v:149046$7551 + attribute \src "libresoc.v:150678.3-150688.6" + process $proc$libresoc.v:150678$7599 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:149047.5-149047.29" + attribute \src "libresoc.v:150679.5-150679.29" switch \initial - attribute \src "libresoc.v:149047.9-149047.17" + attribute \src "libresoc.v:150679.9-150679.17" case 1'1 case end @@ -312319,14 +314816,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:149057.3-149067.6" - process $proc$libresoc.v:149057$7552 + attribute \src "libresoc.v:150689.3-150699.6" + process $proc$libresoc.v:150689$7600 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:149058.5-149058.29" + attribute \src "libresoc.v:150690.5-150690.29" switch \initial - attribute \src "libresoc.v:149058.9-149058.17" + attribute \src "libresoc.v:150690.9-150690.17" case 1'1 case end @@ -312342,14 +314839,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:149068.3-149078.6" - process $proc$libresoc.v:149068$7553 + attribute \src "libresoc.v:150700.3-150710.6" + process $proc$libresoc.v:150700$7601 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:149069.5-149069.29" + attribute \src "libresoc.v:150701.5-150701.29" switch \initial - attribute \src "libresoc.v:149069.9-149069.17" + attribute \src "libresoc.v:150701.9-150701.17" case 1'1 case end @@ -312365,14 +314862,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:149079.3-149089.6" - process $proc$libresoc.v:149079$7554 + attribute \src "libresoc.v:150711.3-150721.6" + process $proc$libresoc.v:150711$7602 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:149080.5-149080.29" + attribute \src "libresoc.v:150712.5-150712.29" switch \initial - attribute \src "libresoc.v:149080.9-149080.17" + attribute \src "libresoc.v:150712.9-150712.17" case 1'1 case end @@ -312388,14 +314885,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:149090.3-149100.6" - process $proc$libresoc.v:149090$7555 + attribute \src "libresoc.v:150722.3-150732.6" + process $proc$libresoc.v:150722$7603 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:149091.5-149091.29" + attribute \src "libresoc.v:150723.5-150723.29" switch \initial - attribute \src "libresoc.v:149091.9-149091.17" + attribute \src "libresoc.v:150723.9-150723.17" case 1'1 case end @@ -312411,14 +314908,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:149101.3-149111.6" - process $proc$libresoc.v:149101$7556 + attribute \src "libresoc.v:150733.3-150743.6" + process $proc$libresoc.v:150733$7604 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:149102.5-149102.29" + attribute \src "libresoc.v:150734.5-150734.29" switch \initial - attribute \src "libresoc.v:149102.9-149102.17" + attribute \src "libresoc.v:150734.9-150734.17" case 1'1 case end @@ -312434,14 +314931,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:149112.3-149122.6" - process $proc$libresoc.v:149112$7557 + attribute \src "libresoc.v:150744.3-150754.6" + process $proc$libresoc.v:150744$7605 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:149113.5-149113.29" + attribute \src "libresoc.v:150745.5-150745.29" switch \initial - attribute \src "libresoc.v:149113.9-149113.17" + attribute \src "libresoc.v:150745.9-150745.17" case 1'1 case end @@ -312457,14 +314954,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:149123.3-149133.6" - process $proc$libresoc.v:149123$7558 + attribute \src "libresoc.v:150755.3-150765.6" + process $proc$libresoc.v:150755$7606 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:149124.5-149124.29" + attribute \src "libresoc.v:150756.5-150756.29" switch \initial - attribute \src "libresoc.v:149124.9-149124.17" + attribute \src "libresoc.v:150756.9-150756.17" case 1'1 case end @@ -312480,14 +314977,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:149134.3-149152.6" - process $proc$libresoc.v:149134$7559 + attribute \src "libresoc.v:150766.3-150784.6" + process $proc$libresoc.v:150766$7607 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:149135.5-149135.29" + attribute \src "libresoc.v:150767.5-150767.29" switch \initial - attribute \src "libresoc.v:149135.9-149135.17" + attribute \src "libresoc.v:150767.9-150767.17" case 1'1 case end @@ -312514,193 +315011,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:148875$7463_Y - connect \$101 $eq$libresoc.v:148876$7464_Y - connect \$103 $eq$libresoc.v:148877$7465_Y - connect \$105 $eq$libresoc.v:148878$7466_Y - connect \$107 $eq$libresoc.v:148879$7467_Y - connect \$109 $eq$libresoc.v:148880$7468_Y - connect \$111 $eq$libresoc.v:148881$7469_Y - connect \$113 $eq$libresoc.v:148882$7470_Y - connect \$115 $eq$libresoc.v:148883$7471_Y - connect \$117 $eq$libresoc.v:148884$7472_Y - connect \$119 $eq$libresoc.v:148885$7473_Y - connect \$121 $eq$libresoc.v:148886$7474_Y - connect \$123 $eq$libresoc.v:148887$7475_Y - connect \$125 $eq$libresoc.v:148888$7476_Y - connect \$127 $eq$libresoc.v:148889$7477_Y - connect \$129 $eq$libresoc.v:148890$7478_Y - connect \$131 $eq$libresoc.v:148891$7479_Y - connect \$133 $eq$libresoc.v:148892$7480_Y - connect \$135 $eq$libresoc.v:148893$7481_Y - connect \$137 $eq$libresoc.v:148894$7482_Y - connect \$139 $eq$libresoc.v:148895$7483_Y - connect \$141 $eq$libresoc.v:148896$7484_Y - connect \$143 $eq$libresoc.v:148897$7485_Y - connect \$145 $eq$libresoc.v:148898$7486_Y - connect \$147 $eq$libresoc.v:148899$7487_Y - connect \$149 $eq$libresoc.v:148900$7488_Y - connect \$151 $eq$libresoc.v:148901$7489_Y - connect \$153 $eq$libresoc.v:148902$7490_Y - connect \$155 $eq$libresoc.v:148903$7491_Y - connect \$158 $xor$libresoc.v:148904$7492_Y - connect \$157 $pos$libresoc.v:148905$7494_Y - connect \$162 $sub$libresoc.v:148906$7495_Y - connect \$164 $pos$libresoc.v:148907$7497_Y - connect \$166 $ternary$libresoc.v:148908$7498_Y - connect \$161 $pos$libresoc.v:148909$7500_Y - connect \$169 $pos$libresoc.v:148910$7502_Y - connect \$171 $reduce_xor$libresoc.v:148911$7503_Y - connect \$173 $reduce_xor$libresoc.v:148912$7504_Y - connect \$176 $ternary$libresoc.v:148913$7505_Y - connect \$175 $pos$libresoc.v:148914$7507_Y - connect \$179 $ternary$libresoc.v:148915$7508_Y - connect \$21 $and$libresoc.v:148916$7509_Y - connect \$23 $or$libresoc.v:148917$7510_Y - connect \$25 $xor$libresoc.v:148918$7511_Y - connect \$27 $eq$libresoc.v:148919$7512_Y - connect \$29 $eq$libresoc.v:148920$7513_Y - connect \$31 $eq$libresoc.v:148921$7514_Y - connect \$33 $eq$libresoc.v:148922$7515_Y - connect \$35 $eq$libresoc.v:148923$7516_Y - connect \$37 $eq$libresoc.v:148924$7517_Y - connect \$39 $eq$libresoc.v:148925$7518_Y - connect \$41 $eq$libresoc.v:148926$7519_Y - connect \$43 $eq$libresoc.v:148927$7520_Y - connect \$45 $eq$libresoc.v:148928$7521_Y - connect \$47 $eq$libresoc.v:148929$7522_Y - connect \$49 $eq$libresoc.v:148930$7523_Y - connect \$51 $eq$libresoc.v:148931$7524_Y - connect \$53 $eq$libresoc.v:148932$7525_Y - connect \$55 $eq$libresoc.v:148933$7526_Y - connect \$57 $eq$libresoc.v:148934$7527_Y - connect \$59 $eq$libresoc.v:148935$7528_Y - connect \$61 $eq$libresoc.v:148936$7529_Y - connect \$63 $eq$libresoc.v:148937$7530_Y - connect \$65 $eq$libresoc.v:148938$7531_Y - connect \$67 $eq$libresoc.v:148939$7532_Y - connect \$69 $eq$libresoc.v:148940$7533_Y - connect \$71 $eq$libresoc.v:148941$7534_Y - connect \$73 $eq$libresoc.v:148942$7535_Y - connect \$75 $eq$libresoc.v:148943$7536_Y - connect \$77 $eq$libresoc.v:148944$7537_Y - connect \$79 $eq$libresoc.v:148945$7538_Y - connect \$81 $eq$libresoc.v:148946$7539_Y - connect \$83 $eq$libresoc.v:148947$7540_Y - connect \$85 $eq$libresoc.v:148948$7541_Y - connect \$87 $eq$libresoc.v:148949$7542_Y - connect \$89 $eq$libresoc.v:148950$7543_Y - connect \$91 $eq$libresoc.v:148951$7544_Y - connect \$93 $eq$libresoc.v:148952$7545_Y - connect \$95 $eq$libresoc.v:148953$7546_Y - connect \$97 $eq$libresoc.v:148954$7547_Y + connect \$99 $eq$libresoc.v:150507$7511_Y + connect \$101 $eq$libresoc.v:150508$7512_Y + connect \$103 $eq$libresoc.v:150509$7513_Y + connect \$105 $eq$libresoc.v:150510$7514_Y + connect \$107 $eq$libresoc.v:150511$7515_Y + connect \$109 $eq$libresoc.v:150512$7516_Y + connect \$111 $eq$libresoc.v:150513$7517_Y + connect \$113 $eq$libresoc.v:150514$7518_Y + connect \$115 $eq$libresoc.v:150515$7519_Y + connect \$117 $eq$libresoc.v:150516$7520_Y + connect \$119 $eq$libresoc.v:150517$7521_Y + connect \$121 $eq$libresoc.v:150518$7522_Y + connect \$123 $eq$libresoc.v:150519$7523_Y + connect \$125 $eq$libresoc.v:150520$7524_Y + connect \$127 $eq$libresoc.v:150521$7525_Y + connect \$129 $eq$libresoc.v:150522$7526_Y + connect \$131 $eq$libresoc.v:150523$7527_Y + connect \$133 $eq$libresoc.v:150524$7528_Y + connect \$135 $eq$libresoc.v:150525$7529_Y + connect \$137 $eq$libresoc.v:150526$7530_Y + connect \$139 $eq$libresoc.v:150527$7531_Y + connect \$141 $eq$libresoc.v:150528$7532_Y + connect \$143 $eq$libresoc.v:150529$7533_Y + connect \$145 $eq$libresoc.v:150530$7534_Y + connect \$147 $eq$libresoc.v:150531$7535_Y + connect \$149 $eq$libresoc.v:150532$7536_Y + connect \$151 $eq$libresoc.v:150533$7537_Y + connect \$153 $eq$libresoc.v:150534$7538_Y + connect \$155 $eq$libresoc.v:150535$7539_Y + connect \$158 $xor$libresoc.v:150536$7540_Y + connect \$157 $pos$libresoc.v:150537$7542_Y + connect \$162 $sub$libresoc.v:150538$7543_Y + connect \$164 $pos$libresoc.v:150539$7545_Y + connect \$166 $ternary$libresoc.v:150540$7546_Y + connect \$161 $pos$libresoc.v:150541$7548_Y + connect \$169 $pos$libresoc.v:150542$7550_Y + connect \$171 $reduce_xor$libresoc.v:150543$7551_Y + connect \$173 $reduce_xor$libresoc.v:150544$7552_Y + connect \$176 $ternary$libresoc.v:150545$7553_Y + connect \$175 $pos$libresoc.v:150546$7555_Y + connect \$179 $ternary$libresoc.v:150547$7556_Y + connect \$21 $and$libresoc.v:150548$7557_Y + connect \$23 $or$libresoc.v:150549$7558_Y + connect \$25 $xor$libresoc.v:150550$7559_Y + connect \$27 $eq$libresoc.v:150551$7560_Y + connect \$29 $eq$libresoc.v:150552$7561_Y + connect \$31 $eq$libresoc.v:150553$7562_Y + connect \$33 $eq$libresoc.v:150554$7563_Y + connect \$35 $eq$libresoc.v:150555$7564_Y + connect \$37 $eq$libresoc.v:150556$7565_Y + connect \$39 $eq$libresoc.v:150557$7566_Y + connect \$41 $eq$libresoc.v:150558$7567_Y + connect \$43 $eq$libresoc.v:150559$7568_Y + connect \$45 $eq$libresoc.v:150560$7569_Y + connect \$47 $eq$libresoc.v:150561$7570_Y + connect \$49 $eq$libresoc.v:150562$7571_Y + connect \$51 $eq$libresoc.v:150563$7572_Y + connect \$53 $eq$libresoc.v:150564$7573_Y + connect \$55 $eq$libresoc.v:150565$7574_Y + connect \$57 $eq$libresoc.v:150566$7575_Y + connect \$59 $eq$libresoc.v:150567$7576_Y + connect \$61 $eq$libresoc.v:150568$7577_Y + connect \$63 $eq$libresoc.v:150569$7578_Y + connect \$65 $eq$libresoc.v:150570$7579_Y + connect \$67 $eq$libresoc.v:150571$7580_Y + connect \$69 $eq$libresoc.v:150572$7581_Y + connect \$71 $eq$libresoc.v:150573$7582_Y + connect \$73 $eq$libresoc.v:150574$7583_Y + connect \$75 $eq$libresoc.v:150575$7584_Y + connect \$77 $eq$libresoc.v:150576$7585_Y + connect \$79 $eq$libresoc.v:150577$7586_Y + connect \$81 $eq$libresoc.v:150578$7587_Y + connect \$83 $eq$libresoc.v:150579$7588_Y + connect \$85 $eq$libresoc.v:150580$7589_Y + connect \$87 $eq$libresoc.v:150581$7590_Y + connect \$89 $eq$libresoc.v:150582$7591_Y + connect \$91 $eq$libresoc.v:150583$7592_Y + connect \$93 $eq$libresoc.v:150584$7593_Y + connect \$95 $eq$libresoc.v:150585$7594_Y + connect \$97 $eq$libresoc.v:150586$7595_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:149160.1-149675.10" +attribute \src "libresoc.v:150792.1-151307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:149530.3-149540.6" + attribute \src "libresoc.v:151162.3-151172.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:149584.3-149594.6" + attribute \src "libresoc.v:151216.3-151226.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:149595.3-149605.6" + attribute \src "libresoc.v:151227.3-151237.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:149648.3-149658.6" + attribute \src "libresoc.v:151280.3-151290.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:149573.3-149583.6" + attribute \src "libresoc.v:151205.3-151215.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $0\cr_a$6[3:0]$7575 - attribute \src "libresoc.v:149442.3-149476.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $0\cr_a$6[3:0]$7623 + attribute \src "libresoc.v:151074.3-151108.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151173.3-151193.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149659.3-149669.6" - wire width 32 $0\full_cr$5[31:0]$7590 - attribute \src "libresoc.v:149477.3-149487.6" + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $0\full_cr$5[31:0]$7638 + attribute \src "libresoc.v:151109.3-151119.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:149161.7-149161.20" + attribute \src "libresoc.v:150793.7-150793.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149562.3-149572.6" + attribute \src "libresoc.v:151194.3-151204.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149530.3-149540.6" + attribute \src "libresoc.v:151162.3-151172.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:149584.3-149594.6" + attribute \src "libresoc.v:151216.3-151226.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:149595.3-149605.6" + attribute \src "libresoc.v:151227.3-151237.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:149648.3-149658.6" + attribute \src "libresoc.v:151280.3-151290.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:149573.3-149583.6" + attribute \src "libresoc.v:151205.3-151215.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $1\cr_a$6[3:0]$7576 - attribute \src "libresoc.v:149442.3-149476.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151074.3-151108.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151173.3-151193.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149659.3-149669.6" - wire width 32 $1\full_cr$5[31:0]$7591 - attribute \src "libresoc.v:149477.3-149487.6" + attribute \src "libresoc.v:151291.3-151301.6" + wire width 32 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151109.3-151119.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:149562.3-149572.6" + attribute \src "libresoc.v:151194.3-151204.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149606.3-149626.6" + attribute \src "libresoc.v:151238.3-151258.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:149627.3-149647.6" + attribute \src "libresoc.v:151259.3-151279.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:149442.3-149476.6" - wire width 4 $2\cr_a$6[3:0]$7577 - attribute \src "libresoc.v:149541.3-149561.6" + attribute \src "libresoc.v:151074.3-151108.6" + wire width 4 $2\cr_a$6[3:0]$7625 + attribute \src "libresoc.v:151173.3-151193.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:149488.3-149529.6" + attribute \src "libresoc.v:151120.3-151161.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:149438.18-149438.96" - wire width 64 $extend$libresoc.v:149438$7567_Y - attribute \src "libresoc.v:149440.18-149440.98" - wire width 65 $extend$libresoc.v:149440$7570_Y - attribute \src "libresoc.v:149441.17-149441.92" - wire width 5 $extend$libresoc.v:149441$7572_Y - attribute \src "libresoc.v:149438.18-149438.96" - wire width 64 $pos$libresoc.v:149438$7568_Y - attribute \src "libresoc.v:149440.18-149440.98" - wire width 65 $pos$libresoc.v:149440$7571_Y - attribute \src "libresoc.v:149441.17-149441.92" - wire width 5 $pos$libresoc.v:149441$7573_Y - attribute \src "libresoc.v:149432.18-149432.116" - wire width 3 $sub$libresoc.v:149432$7561_Y - attribute \src "libresoc.v:149433.18-149433.116" - wire width 3 $sub$libresoc.v:149433$7562_Y - attribute \src "libresoc.v:149434.18-149434.116" - wire width 3 $sub$libresoc.v:149434$7563_Y - attribute \src "libresoc.v:149435.18-149435.114" - wire $ternary$libresoc.v:149435$7564_Y - attribute \src "libresoc.v:149436.18-149436.115" - wire $ternary$libresoc.v:149436$7565_Y - attribute \src "libresoc.v:149437.18-149437.112" - wire $ternary$libresoc.v:149437$7566_Y - attribute \src "libresoc.v:149439.18-149439.108" - wire width 64 $ternary$libresoc.v:149439$7569_Y + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $extend$libresoc.v:151070$7615_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $extend$libresoc.v:151072$7618_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $extend$libresoc.v:151073$7620_Y + attribute \src "libresoc.v:151070.18-151070.96" + wire width 64 $pos$libresoc.v:151070$7616_Y + attribute \src "libresoc.v:151072.18-151072.98" + wire width 65 $pos$libresoc.v:151072$7619_Y + attribute \src "libresoc.v:151073.17-151073.92" + wire width 5 $pos$libresoc.v:151073$7621_Y + attribute \src "libresoc.v:151064.18-151064.116" + wire width 3 $sub$libresoc.v:151064$7609_Y + attribute \src "libresoc.v:151065.18-151065.116" + wire width 3 $sub$libresoc.v:151065$7610_Y + attribute \src "libresoc.v:151066.18-151066.116" + wire width 3 $sub$libresoc.v:151066$7611_Y + attribute \src "libresoc.v:151067.18-151067.114" + wire $ternary$libresoc.v:151067$7612_Y + attribute \src "libresoc.v:151068.18-151068.115" + wire $ternary$libresoc.v:151068$7613_Y + attribute \src "libresoc.v:151069.18-151069.112" + wire $ternary$libresoc.v:151069$7614_Y + attribute \src "libresoc.v:151071.18-151071.108" + wire width 64 $ternary$libresoc.v:151071$7617_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -312951,7 +315448,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:149161.7-149161.15" + attribute \src "libresoc.v:150793.7-150793.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -312968,55 +315465,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149438$7567 + cell $pos $extend$libresoc.v:151070$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:149438$7567_Y + connect \Y $extend$libresoc.v:151070$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:149440$7570 + cell $pos $extend$libresoc.v:151072$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:149440$7570_Y + connect \Y $extend$libresoc.v:151072$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:149441$7572 + cell $pos $extend$libresoc.v:151073$7620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:149441$7572_Y + connect \Y $extend$libresoc.v:151073$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149438$7568 + cell $pos $pos$libresoc.v:151070$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149438$7567_Y - connect \Y $pos$libresoc.v:149438$7568_Y + connect \A $extend$libresoc.v:151070$7615_Y + connect \Y $pos$libresoc.v:151070$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:149440$7571 + cell $pos $pos$libresoc.v:151072$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149440$7570_Y - connect \Y $pos$libresoc.v:149440$7571_Y + connect \A $extend$libresoc.v:151072$7618_Y + connect \Y $pos$libresoc.v:151072$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:149441$7573 + cell $pos $pos$libresoc.v:151073$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:149441$7572_Y - connect \Y $pos$libresoc.v:149441$7573_Y + connect \A $extend$libresoc.v:151073$7620_Y + connect \Y $pos$libresoc.v:151073$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:149432$7561 + cell $sub $sub$libresoc.v:151064$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313024,10 +315521,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:149432$7561_Y + connect \Y $sub$libresoc.v:151064$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:149433$7562 + cell $sub $sub$libresoc.v:151065$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313035,10 +315532,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:149433$7562_Y + connect \Y $sub$libresoc.v:151065$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:149434$7563 + cell $sub $sub$libresoc.v:151066$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -313046,59 +315543,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:149434$7563_Y + connect \Y $sub$libresoc.v:151066$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:149435$7564 + cell $mux $ternary$libresoc.v:151067$7612 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:149435$7564_Y + connect \Y $ternary$libresoc.v:151067$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:149436$7565 + cell $mux $ternary$libresoc.v:151068$7613 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:149436$7565_Y + connect \Y $ternary$libresoc.v:151068$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:149437$7566 + cell $mux $ternary$libresoc.v:151069$7614 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:149437$7566_Y + connect \Y $ternary$libresoc.v:151069$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:149439$7569 + cell $mux $ternary$libresoc.v:151071$7617 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:149439$7569_Y + connect \Y $ternary$libresoc.v:151071$7617_Y end - attribute \src "libresoc.v:149161.7-149161.20" - process $proc$libresoc.v:149161$7592 + attribute \src "libresoc.v:150793.7-150793.20" + process $proc$libresoc.v:150793$7640 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149442.3-149476.6" - process $proc$libresoc.v:149442$7574 + attribute \src "libresoc.v:151074.3-151108.6" + process $proc$libresoc.v:151074$7622 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7575 $1\cr_a$6[3:0]$7576 - attribute \src "libresoc.v:149443.5-149443.29" + assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 + attribute \src "libresoc.v:151075.5-151075.29" switch \initial - attribute \src "libresoc.v:149443.9-149443.17" + attribute \src "libresoc.v:151075.9-151075.17" case 1'1 case end @@ -313108,52 +315605,52 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7576 \$7 [3:0] + assign $1\cr_a$6[3:0]$7624 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7576 $2\cr_a$6[3:0]$7577 + assign $1\cr_a$6[3:0]$7624 $2\cr_a$6[3:0]$7625 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7577 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7577 [0] \bit_o + assign $2\cr_a$6[3:0]$7625 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7625 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7577 [3:2] $2\cr_a$6[3:0]$7577 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7577 [1] \bit_o + assign { $2\cr_a$6[3:0]$7625 [3:2] $2\cr_a$6[3:0]$7625 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7625 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7577 [3] $2\cr_a$6[3:0]$7577 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7577 [2] \bit_o + assign { $2\cr_a$6[3:0]$7625 [3] $2\cr_a$6[3:0]$7625 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7625 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7577 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7577 [3] \bit_o + assign $2\cr_a$6[3:0]$7625 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7625 [3] \bit_o case - assign $2\cr_a$6[3:0]$7577 \cr_c + assign $2\cr_a$6[3:0]$7625 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7576 4'0000 + assign $1\cr_a$6[3:0]$7624 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7575 + update \cr_a$6 $0\cr_a$6[3:0]$7623 end - attribute \src "libresoc.v:149477.3-149487.6" - process $proc$libresoc.v:149477$7578 + attribute \src "libresoc.v:151109.3-151119.6" + process $proc$libresoc.v:151109$7626 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:149478.5-149478.29" + attribute \src "libresoc.v:151110.5-151110.29" switch \initial - attribute \src "libresoc.v:149478.9-149478.17" + attribute \src "libresoc.v:151110.9-151110.17" case 1'1 case end @@ -313169,17 +315666,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:149488.3-149529.6" - process $proc$libresoc.v:149488$7579 + attribute \src "libresoc.v:151120.3-151161.6" + process $proc$libresoc.v:151120$7627 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:149489.5-149489.29" + attribute \src "libresoc.v:151121.5-151121.29" switch \initial - attribute \src "libresoc.v:149489.9-149489.17" + attribute \src "libresoc.v:151121.9-151121.17" case 1'1 case end @@ -313226,14 +315723,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:149530.3-149540.6" - process $proc$libresoc.v:149530$7580 + attribute \src "libresoc.v:151162.3-151172.6" + process $proc$libresoc.v:151162$7628 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:149531.5-149531.29" + attribute \src "libresoc.v:151163.5-151163.29" switch \initial - attribute \src "libresoc.v:149531.9-149531.17" + attribute \src "libresoc.v:151163.9-151163.17" case 1'1 case end @@ -313249,14 +315746,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:149541.3-149561.6" - process $proc$libresoc.v:149541$7581 + attribute \src "libresoc.v:151173.3-151193.6" + process $proc$libresoc.v:151173$7629 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:149542.5-149542.29" + attribute \src "libresoc.v:151174.5-151174.29" switch \initial - attribute \src "libresoc.v:149542.9-149542.17" + attribute \src "libresoc.v:151174.9-151174.17" case 1'1 case end @@ -313293,14 +315790,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:149562.3-149572.6" - process $proc$libresoc.v:149562$7582 + attribute \src "libresoc.v:151194.3-151204.6" + process $proc$libresoc.v:151194$7630 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:149563.5-149563.29" + attribute \src "libresoc.v:151195.5-151195.29" switch \initial - attribute \src "libresoc.v:149563.9-149563.17" + attribute \src "libresoc.v:151195.9-151195.17" case 1'1 case end @@ -313316,14 +315813,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:149573.3-149583.6" - process $proc$libresoc.v:149573$7583 + attribute \src "libresoc.v:151205.3-151215.6" + process $proc$libresoc.v:151205$7631 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:149574.5-149574.29" + attribute \src "libresoc.v:151206.5-151206.29" switch \initial - attribute \src "libresoc.v:149574.9-149574.17" + attribute \src "libresoc.v:151206.9-151206.17" case 1'1 case end @@ -313339,14 +315836,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:149584.3-149594.6" - process $proc$libresoc.v:149584$7584 + attribute \src "libresoc.v:151216.3-151226.6" + process $proc$libresoc.v:151216$7632 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:149585.5-149585.29" + attribute \src "libresoc.v:151217.5-151217.29" switch \initial - attribute \src "libresoc.v:149585.9-149585.17" + attribute \src "libresoc.v:151217.9-151217.17" case 1'1 case end @@ -313362,14 +315859,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:149595.3-149605.6" - process $proc$libresoc.v:149595$7585 + attribute \src "libresoc.v:151227.3-151237.6" + process $proc$libresoc.v:151227$7633 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:149596.5-149596.29" + attribute \src "libresoc.v:151228.5-151228.29" switch \initial - attribute \src "libresoc.v:149596.9-149596.17" + attribute \src "libresoc.v:151228.9-151228.17" case 1'1 case end @@ -313385,14 +315882,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:149606.3-149626.6" - process $proc$libresoc.v:149606$7586 + attribute \src "libresoc.v:151238.3-151258.6" + process $proc$libresoc.v:151238$7634 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:149607.5-149607.29" + attribute \src "libresoc.v:151239.5-151239.29" switch \initial - attribute \src "libresoc.v:149607.9-149607.17" + attribute \src "libresoc.v:151239.9-151239.17" case 1'1 case end @@ -313429,14 +315926,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:149627.3-149647.6" - process $proc$libresoc.v:149627$7587 + attribute \src "libresoc.v:151259.3-151279.6" + process $proc$libresoc.v:151259$7635 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:149628.5-149628.29" + attribute \src "libresoc.v:151260.5-151260.29" switch \initial - attribute \src "libresoc.v:149628.9-149628.17" + attribute \src "libresoc.v:151260.9-151260.17" case 1'1 case end @@ -313473,14 +315970,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:149648.3-149658.6" - process $proc$libresoc.v:149648$7588 + attribute \src "libresoc.v:151280.3-151290.6" + process $proc$libresoc.v:151280$7636 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:149649.5-149649.29" + attribute \src "libresoc.v:151281.5-151281.29" switch \initial - attribute \src "libresoc.v:149649.9-149649.17" + attribute \src "libresoc.v:151281.9-151281.17" case 1'1 case end @@ -313496,14 +315993,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:149659.3-149669.6" - process $proc$libresoc.v:149659$7589 + attribute \src "libresoc.v:151291.3-151301.6" + process $proc$libresoc.v:151291$7637 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7590 $1\full_cr$5[31:0]$7591 - attribute \src "libresoc.v:149660.5-149660.29" + assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 + attribute \src "libresoc.v:151292.5-151292.29" switch \initial - attribute \src "libresoc.v:149660.9-149660.17" + attribute \src "libresoc.v:151292.9-151292.17" case 1'1 case end @@ -313512,508 +316009,508 @@ module \main$9 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7591 \ra [31:0] + assign $1\full_cr$5[31:0]$7639 \ra [31:0] case - assign $1\full_cr$5[31:0]$7591 0 + assign $1\full_cr$5[31:0]$7639 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7590 + update \full_cr$5 $0\full_cr$5[31:0]$7638 end - connect \$10 $sub$libresoc.v:149432$7561_Y - connect \$13 $sub$libresoc.v:149433$7562_Y - connect \$16 $sub$libresoc.v:149434$7563_Y - connect \$18 $ternary$libresoc.v:149435$7564_Y - connect \$20 $ternary$libresoc.v:149436$7565_Y - connect \$22 $ternary$libresoc.v:149437$7566_Y - connect \$24 $pos$libresoc.v:149438$7568_Y - connect \$27 $ternary$libresoc.v:149439$7569_Y - connect \$26 $pos$libresoc.v:149440$7571_Y - connect \$7 $pos$libresoc.v:149441$7573_Y + connect \$10 $sub$libresoc.v:151064$7609_Y + connect \$13 $sub$libresoc.v:151065$7610_Y + connect \$16 $sub$libresoc.v:151066$7611_Y + connect \$18 $ternary$libresoc.v:151067$7612_Y + connect \$20 $ternary$libresoc.v:151068$7613_Y + connect \$22 $ternary$libresoc.v:151069$7614_Y + connect \$24 $pos$libresoc.v:151070$7616_Y + connect \$27 $ternary$libresoc.v:151071$7617_Y + connect \$26 $pos$libresoc.v:151072$7619_Y + connect \$7 $pos$libresoc.v:151073$7621_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:149679.1-150840.10" +attribute \src "libresoc.v:151311.1-152472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:150411.3-150412.25" + attribute \src "libresoc.v:152043.3-152044.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:150409.3-150410.40" + attribute \src "libresoc.v:152041.3-152042.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:150752.3-150760.6" - wire $0\alu_l_r_alu$next[0:0]$7798 - attribute \src "libresoc.v:150337.3-150338.39" + attribute \src "libresoc.v:152384.3-152392.6" + wire $0\alu_l_r_alu$next[0:0]$7846 + attribute \src "libresoc.v:151969.3-151970.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 - attribute \src "libresoc.v:150365.3-150366.65" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + attribute \src "libresoc.v:151997.3-151998.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 - attribute \src "libresoc.v:150367.3-150368.79" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + attribute \src "libresoc.v:151999.3-152000.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 - attribute \src "libresoc.v:150369.3-150370.75" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + attribute \src "libresoc.v:152001.3-152002.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7726 - attribute \src "libresoc.v:150385.3-150386.59" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 + attribute \src "libresoc.v:152017.3-152018.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 - attribute \src "libresoc.v:150363.3-150364.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + attribute \src "libresoc.v:151995.3-151996.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 - attribute \src "libresoc.v:150381.3-150382.67" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + attribute \src "libresoc.v:152013.3-152014.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 - attribute \src "libresoc.v:150383.3-150384.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + attribute \src "libresoc.v:152015.3-152016.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 - attribute \src "libresoc.v:150375.3-150376.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + attribute \src "libresoc.v:152007.3-152008.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 - attribute \src "libresoc.v:150377.3-150378.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + attribute \src "libresoc.v:152009.3-152010.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 - attribute \src "libresoc.v:150373.3-150374.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + attribute \src "libresoc.v:152005.3-152006.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 - attribute \src "libresoc.v:150371.3-150372.63" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + attribute \src "libresoc.v:152003.3-152004.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 - attribute \src "libresoc.v:150379.3-150380.69" + attribute \src "libresoc.v:152224.3-152256.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + attribute \src "libresoc.v:152011.3-152012.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:150743.3-150751.6" - wire $0\alui_l_r_alui$next[0:0]$7795 - attribute \src "libresoc.v:150339.3-150340.43" + attribute \src "libresoc.v:152375.3-152383.6" + wire $0\alui_l_r_alui$next[0:0]$7843 + attribute \src "libresoc.v:151971.3-151972.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $0\data_r0__o$next[63:0]$7754 - attribute \src "libresoc.v:150359.3-150360.37" + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $0\data_r0__o$next[63:0]$7802 + attribute \src "libresoc.v:151991.3-151992.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire $0\data_r0__o_ok$next[0:0]$7755 - attribute \src "libresoc.v:150361.3-150362.43" + attribute \src "libresoc.v:152257.3-152278.6" + wire $0\data_r0__o_ok$next[0:0]$7803 + attribute \src "libresoc.v:151993.3-151994.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7762 - attribute \src "libresoc.v:150355.3-150356.43" + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7810 + attribute \src "libresoc.v:151987.3-151988.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7763 - attribute \src "libresoc.v:150357.3-150358.49" + attribute \src "libresoc.v:152279.3-152300.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7811 + attribute \src "libresoc.v:151989.3-151990.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7770 - attribute \src "libresoc.v:150351.3-150352.47" + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 + attribute \src "libresoc.v:151983.3-151984.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7771 - attribute \src "libresoc.v:150353.3-150354.53" + attribute \src "libresoc.v:152301.3-152322.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7819 + attribute \src "libresoc.v:151985.3-151986.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $0\data_r3__xer_so$next[0:0]$7778 - attribute \src "libresoc.v:150347.3-150348.47" + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so$next[0:0]$7826 + attribute \src "libresoc.v:151979.3-151980.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7779 - attribute \src "libresoc.v:150349.3-150350.53" + attribute \src "libresoc.v:152323.3-152344.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7827 + attribute \src "libresoc.v:151981.3-151982.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:150761.3-150770.6" + attribute \src "libresoc.v:152393.3-152402.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:150771.3-150780.6" + attribute \src "libresoc.v:152403.3-152412.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:150781.3-150790.6" + attribute \src "libresoc.v:152413.3-152422.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:150791.3-150800.6" + attribute \src "libresoc.v:152423.3-152432.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:149680.7-149680.20" + attribute \src "libresoc.v:151312.7-151312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150547.3-150555.6" - wire $0\opc_l_r_opc$next[0:0]$7708 - attribute \src "libresoc.v:150395.3-150396.39" + attribute \src "libresoc.v:152179.3-152187.6" + wire $0\opc_l_r_opc$next[0:0]$7756 + attribute \src "libresoc.v:152027.3-152028.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:150538.3-150546.6" - wire $0\opc_l_s_opc$next[0:0]$7705 - attribute \src "libresoc.v:150397.3-150398.39" + attribute \src "libresoc.v:152170.3-152178.6" + wire $0\opc_l_s_opc$next[0:0]$7753 + attribute \src "libresoc.v:152029.3-152030.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:150801.3-150809.6" - wire width 4 $0\prev_wr_go$next[3:0]$7805 - attribute \src "libresoc.v:150407.3-150408.37" + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $0\prev_wr_go$next[3:0]$7853 + attribute \src "libresoc.v:152039.3-152040.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:150492.3-150501.6" + attribute \src "libresoc.v:152124.3-152133.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:150583.3-150591.6" - wire width 4 $0\req_l_r_req$next[3:0]$7720 - attribute \src "libresoc.v:150387.3-150388.39" + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $0\req_l_r_req$next[3:0]$7768 + attribute \src "libresoc.v:152019.3-152020.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:150574.3-150582.6" - wire width 4 $0\req_l_s_req$next[3:0]$7717 - attribute \src "libresoc.v:150389.3-150390.39" + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $0\req_l_s_req$next[3:0]$7765 + attribute \src "libresoc.v:152021.3-152022.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:150511.3-150519.6" - wire $0\rok_l_r_rdok$next[0:0]$7696 - attribute \src "libresoc.v:150403.3-150404.41" + attribute \src "libresoc.v:152143.3-152151.6" + wire $0\rok_l_r_rdok$next[0:0]$7744 + attribute \src "libresoc.v:152035.3-152036.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:150502.3-150510.6" - wire $0\rok_l_s_rdok$next[0:0]$7693 - attribute \src "libresoc.v:150405.3-150406.41" + attribute \src "libresoc.v:152134.3-152142.6" + wire $0\rok_l_s_rdok$next[0:0]$7741 + attribute \src "libresoc.v:152037.3-152038.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:150529.3-150537.6" - wire $0\rst_l_r_rst$next[0:0]$7702 - attribute \src "libresoc.v:150399.3-150400.39" + attribute \src "libresoc.v:152161.3-152169.6" + wire $0\rst_l_r_rst$next[0:0]$7750 + attribute \src "libresoc.v:152031.3-152032.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:150520.3-150528.6" - wire $0\rst_l_s_rst$next[0:0]$7699 - attribute \src "libresoc.v:150401.3-150402.39" + attribute \src "libresoc.v:152152.3-152160.6" + wire $0\rst_l_s_rst$next[0:0]$7747 + attribute \src "libresoc.v:152033.3-152034.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:150565.3-150573.6" - wire width 3 $0\src_l_r_src$next[2:0]$7714 - attribute \src "libresoc.v:150391.3-150392.39" + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $0\src_l_r_src$next[2:0]$7762 + attribute \src "libresoc.v:152023.3-152024.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:150556.3-150564.6" - wire width 3 $0\src_l_s_src$next[2:0]$7711 - attribute \src "libresoc.v:150393.3-150394.39" + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $0\src_l_s_src$next[2:0]$7759 + attribute \src "libresoc.v:152025.3-152026.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:150713.3-150722.6" - wire width 64 $0\src_r0$next[63:0]$7786 - attribute \src "libresoc.v:150345.3-150346.29" + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $0\src_r0$next[63:0]$7834 + attribute \src "libresoc.v:151977.3-151978.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:150723.3-150732.6" - wire width 64 $0\src_r1$next[63:0]$7789 - attribute \src "libresoc.v:150343.3-150344.29" + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $0\src_r1$next[63:0]$7837 + attribute \src "libresoc.v:151975.3-151976.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:150733.3-150742.6" - wire $0\src_r2$next[0:0]$7792 - attribute \src "libresoc.v:150341.3-150342.29" + attribute \src "libresoc.v:152365.3-152374.6" + wire $0\src_r2$next[0:0]$7840 + attribute \src "libresoc.v:151973.3-151974.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:149804.7-149804.24" + attribute \src "libresoc.v:151436.7-151436.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:149814.7-149814.26" + attribute \src "libresoc.v:151446.7-151446.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:150752.3-150760.6" - wire $1\alu_l_r_alu$next[0:0]$7799 - attribute \src "libresoc.v:149822.7-149822.25" + attribute \src "libresoc.v:152384.3-152392.6" + wire $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:151454.7-151454.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 - attribute \src "libresoc.v:149845.14-149845.49" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + attribute \src "libresoc.v:151477.14-151477.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 - attribute \src "libresoc.v:149849.14-149849.68" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + attribute \src "libresoc.v:151481.14-151481.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 - attribute \src "libresoc.v:149853.7-149853.43" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + attribute \src "libresoc.v:151485.7-151485.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7738 - attribute \src "libresoc.v:149857.14-149857.43" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + attribute \src "libresoc.v:151489.14-151489.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 - attribute \src "libresoc.v:149936.13-149936.47" + attribute \src "libresoc.v:152224.3-152256.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + attribute \src "libresoc.v:151568.13-151568.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 - attribute \src "libresoc.v:149940.7-149940.39" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + attribute \src "libresoc.v:151572.7-151572.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 - attribute \src "libresoc.v:149944.7-149944.40" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + attribute \src "libresoc.v:151576.7-151576.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 - attribute \src "libresoc.v:149948.7-149948.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + attribute \src "libresoc.v:151580.7-151580.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 - attribute \src "libresoc.v:149952.7-149952.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + attribute \src "libresoc.v:151584.7-151584.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 - attribute \src "libresoc.v:149956.7-149956.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + attribute \src "libresoc.v:151588.7-151588.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 - attribute \src "libresoc.v:149960.7-149960.37" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + attribute \src "libresoc.v:151592.7-151592.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 - attribute \src "libresoc.v:149964.7-149964.40" + attribute \src "libresoc.v:152224.3-152256.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + attribute \src "libresoc.v:151596.7-151596.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:150743.3-150751.6" - wire $1\alui_l_r_alui$next[0:0]$7796 - attribute \src "libresoc.v:149994.7-149994.27" + attribute \src "libresoc.v:152375.3-152383.6" + wire $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:151626.7-151626.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $1\data_r0__o$next[63:0]$7756 - attribute \src "libresoc.v:150028.14-150028.47" + attribute \src "libresoc.v:152257.3-152278.6" + wire width 64 $1\data_r0__o$next[63:0]$7804 + attribute \src "libresoc.v:151660.14-151660.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:150625.3-150646.6" - wire $1\data_r0__o_ok$next[0:0]$7757 - attribute \src "libresoc.v:150032.7-150032.27" + attribute \src "libresoc.v:152257.3-152278.6" + wire $1\data_r0__o_ok$next[0:0]$7805 + attribute \src "libresoc.v:151664.7-151664.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7764 - attribute \src "libresoc.v:150036.13-150036.33" + attribute \src "libresoc.v:152279.3-152300.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7812 + attribute \src "libresoc.v:151668.13-151668.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:150647.3-150668.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7765 - attribute \src "libresoc.v:150040.7-150040.30" + attribute \src "libresoc.v:152279.3-152300.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7813 + attribute \src "libresoc.v:151672.7-151672.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7772 - attribute \src "libresoc.v:150044.13-150044.35" + attribute \src "libresoc.v:152301.3-152322.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 + attribute \src "libresoc.v:151676.13-151676.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:150669.3-150690.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7773 - attribute \src "libresoc.v:150048.7-150048.32" + attribute \src "libresoc.v:152301.3-152322.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7821 + attribute \src "libresoc.v:151680.7-151680.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $1\data_r3__xer_so$next[0:0]$7780 - attribute \src "libresoc.v:150052.7-150052.29" + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so$next[0:0]$7828 + attribute \src "libresoc.v:151684.7-151684.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:150691.3-150712.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7781 - attribute \src "libresoc.v:150056.7-150056.32" + attribute \src "libresoc.v:152323.3-152344.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7829 + attribute \src "libresoc.v:151688.7-151688.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:150761.3-150770.6" + attribute \src "libresoc.v:152393.3-152402.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:150771.3-150780.6" + attribute \src "libresoc.v:152403.3-152412.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:150781.3-150790.6" + attribute \src "libresoc.v:152413.3-152422.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:150791.3-150800.6" + attribute \src "libresoc.v:152423.3-152432.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:150547.3-150555.6" - wire $1\opc_l_r_opc$next[0:0]$7709 - attribute \src "libresoc.v:150076.7-150076.25" + attribute \src "libresoc.v:152179.3-152187.6" + wire $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:151708.7-151708.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:150538.3-150546.6" - wire $1\opc_l_s_opc$next[0:0]$7706 - attribute \src "libresoc.v:150080.7-150080.25" + attribute \src "libresoc.v:152170.3-152178.6" + wire $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:151712.7-151712.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:150801.3-150809.6" - wire width 4 $1\prev_wr_go$next[3:0]$7806 - attribute \src "libresoc.v:150198.13-150198.30" + attribute \src "libresoc.v:152433.3-152441.6" + wire width 4 $1\prev_wr_go$next[3:0]$7854 + attribute \src "libresoc.v:151830.13-151830.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:150492.3-150501.6" + attribute \src "libresoc.v:152124.3-152133.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:150583.3-150591.6" - wire width 4 $1\req_l_r_req$next[3:0]$7721 - attribute \src "libresoc.v:150206.13-150206.31" + attribute \src "libresoc.v:152215.3-152223.6" + wire width 4 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:151838.13-151838.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:150574.3-150582.6" - wire width 4 $1\req_l_s_req$next[3:0]$7718 - attribute \src "libresoc.v:150210.13-150210.31" + attribute \src "libresoc.v:152206.3-152214.6" + wire width 4 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:151842.13-151842.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:150511.3-150519.6" - wire $1\rok_l_r_rdok$next[0:0]$7697 - attribute \src "libresoc.v:150222.7-150222.26" + attribute \src "libresoc.v:152143.3-152151.6" + wire $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:151854.7-151854.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:150502.3-150510.6" - wire $1\rok_l_s_rdok$next[0:0]$7694 - attribute \src "libresoc.v:150226.7-150226.26" + attribute \src "libresoc.v:152134.3-152142.6" + wire $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:151858.7-151858.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:150529.3-150537.6" - wire $1\rst_l_r_rst$next[0:0]$7703 - attribute \src "libresoc.v:150230.7-150230.25" + attribute \src "libresoc.v:152161.3-152169.6" + wire $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:151862.7-151862.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:150520.3-150528.6" - wire $1\rst_l_s_rst$next[0:0]$7700 - attribute \src "libresoc.v:150234.7-150234.25" + attribute \src "libresoc.v:152152.3-152160.6" + wire $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:151866.7-151866.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:150565.3-150573.6" - wire width 3 $1\src_l_r_src$next[2:0]$7715 - attribute \src "libresoc.v:150248.13-150248.31" + attribute \src "libresoc.v:152197.3-152205.6" + wire width 3 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:151880.13-151880.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:150556.3-150564.6" - wire width 3 $1\src_l_s_src$next[2:0]$7712 - attribute \src "libresoc.v:150252.13-150252.31" + attribute \src "libresoc.v:152188.3-152196.6" + wire width 3 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:151884.13-151884.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:150713.3-150722.6" - wire width 64 $1\src_r0$next[63:0]$7787 - attribute \src "libresoc.v:150258.14-150258.43" + attribute \src "libresoc.v:152345.3-152354.6" + wire width 64 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:151890.14-151890.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:150723.3-150732.6" - wire width 64 $1\src_r1$next[63:0]$7790 - attribute \src "libresoc.v:150262.14-150262.43" + attribute \src "libresoc.v:152355.3-152364.6" + wire width 64 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:151894.14-151894.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:150733.3-150742.6" - wire $1\src_r2$next[0:0]$7793 - attribute \src "libresoc.v:150266.7-150266.20" + attribute \src "libresoc.v:152365.3-152374.6" + wire $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:151898.7-151898.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:150592.3-150624.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 - attribute \src "libresoc.v:150592.3-150624.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 - attribute \src "libresoc.v:150625.3-150646.6" - wire width 64 $2\data_r0__o$next[63:0]$7758 - attribute \src "libresoc.v:150625.3-150646.6" - wire $2\data_r0__o_ok$next[0:0]$7759 - attribute \src "libresoc.v:150647.3-150668.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7766 - attribute \src "libresoc.v:150647.3-150668.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7767 - attribute \src "libresoc.v:150669.3-150690.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7774 - attribute \src "libresoc.v:150669.3-150690.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7775 - attribute \src "libresoc.v:150691.3-150712.6" - wire $2\data_r3__xer_so$next[0:0]$7782 - attribute \src "libresoc.v:150691.3-150712.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7783 - attribute \src "libresoc.v:150625.3-150646.6" - wire $3\data_r0__o_ok$next[0:0]$7760 - attribute \src "libresoc.v:150647.3-150668.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7768 - attribute \src "libresoc.v:150669.3-150690.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7776 - attribute \src "libresoc.v:150691.3-150712.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7784 - attribute \src "libresoc.v:150277.19-150277.113" - wire width 3 $and$libresoc.v:150277$7593_Y - attribute \src "libresoc.v:150278.19-150278.125" - wire $and$libresoc.v:150278$7594_Y - attribute \src "libresoc.v:150279.19-150279.125" - wire $and$libresoc.v:150279$7595_Y - attribute \src "libresoc.v:150280.19-150280.125" - wire $and$libresoc.v:150280$7596_Y - attribute \src "libresoc.v:150281.19-150281.125" - wire $and$libresoc.v:150281$7597_Y - attribute \src "libresoc.v:150282.18-150282.110" - wire $and$libresoc.v:150282$7598_Y - attribute \src "libresoc.v:150283.19-150283.149" - wire width 4 $and$libresoc.v:150283$7599_Y - attribute \src "libresoc.v:150284.19-150284.121" - wire width 4 $and$libresoc.v:150284$7600_Y - attribute \src "libresoc.v:150285.19-150285.127" - wire $and$libresoc.v:150285$7601_Y - attribute \src "libresoc.v:150286.19-150286.127" - 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$and$libresoc.v:150307$7623_Y - attribute \src "libresoc.v:150309.18-150309.126" - wire $and$libresoc.v:150309$7625_Y - attribute \src "libresoc.v:150310.18-150310.126" - wire $and$libresoc.v:150310$7626_Y - attribute \src "libresoc.v:150311.18-150311.117" - wire $and$libresoc.v:150311$7627_Y - attribute \src "libresoc.v:150317.18-150317.130" - wire $and$libresoc.v:150317$7633_Y - attribute \src "libresoc.v:150318.18-150318.124" - wire width 4 $and$libresoc.v:150318$7634_Y - attribute \src "libresoc.v:150320.18-150320.116" - wire $and$libresoc.v:150320$7636_Y - attribute \src "libresoc.v:150321.18-150321.119" - wire $and$libresoc.v:150321$7637_Y - attribute \src "libresoc.v:150322.18-150322.121" - wire $and$libresoc.v:150322$7638_Y - attribute \src "libresoc.v:150323.18-150323.121" - wire $and$libresoc.v:150323$7639_Y - attribute \src "libresoc.v:150330.18-150330.134" - wire $and$libresoc.v:150330$7646_Y - attribute \src "libresoc.v:150332.18-150332.132" - wire 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$and$libresoc.v:151931$7663_Y + attribute \src "libresoc.v:151936.18-151936.113" + wire $and$libresoc.v:151936$7668_Y + attribute \src "libresoc.v:151937.18-151937.125" + wire width 4 $and$libresoc.v:151937$7669_Y + attribute \src "libresoc.v:151939.18-151939.112" + wire $and$libresoc.v:151939$7671_Y + attribute \src "libresoc.v:151941.18-151941.126" + wire $and$libresoc.v:151941$7673_Y + attribute \src "libresoc.v:151942.18-151942.126" + wire $and$libresoc.v:151942$7674_Y + attribute \src "libresoc.v:151943.18-151943.117" + wire $and$libresoc.v:151943$7675_Y + attribute \src "libresoc.v:151949.18-151949.130" + wire $and$libresoc.v:151949$7681_Y + attribute \src "libresoc.v:151950.18-151950.124" + wire width 4 $and$libresoc.v:151950$7682_Y + attribute \src "libresoc.v:151952.18-151952.116" + wire $and$libresoc.v:151952$7684_Y + attribute \src "libresoc.v:151953.18-151953.119" + wire $and$libresoc.v:151953$7685_Y + attribute \src "libresoc.v:151954.18-151954.121" + wire $and$libresoc.v:151954$7686_Y + attribute \src "libresoc.v:151955.18-151955.121" + wire $and$libresoc.v:151955$7687_Y + attribute \src "libresoc.v:151962.18-151962.134" + wire $and$libresoc.v:151962$7694_Y + attribute \src "libresoc.v:151964.18-151964.132" + wire $and$libresoc.v:151964$7696_Y + attribute \src "libresoc.v:151965.18-151965.149" + wire width 3 $and$libresoc.v:151965$7697_Y + attribute \src "libresoc.v:151967.18-151967.129" + wire width 3 $and$libresoc.v:151967$7699_Y + attribute \src "libresoc.v:151938.18-151938.113" + wire $eq$libresoc.v:151938$7670_Y + attribute \src "libresoc.v:151940.18-151940.119" + wire $eq$libresoc.v:151940$7672_Y + attribute \src "libresoc.v:151921.18-151921.97" + wire $not$libresoc.v:151921$7653_Y + attribute \src "libresoc.v:151923.18-151923.99" + wire $not$libresoc.v:151923$7655_Y + attribute \src "libresoc.v:151926.18-151926.113" + wire width 4 $not$libresoc.v:151926$7658_Y + attribute \src "libresoc.v:151929.18-151929.106" + wire $not$libresoc.v:151929$7661_Y + attribute \src "libresoc.v:151935.18-151935.120" + wire $not$libresoc.v:151935$7667_Y + attribute \src "libresoc.v:151946.17-151946.113" + wire width 3 $not$libresoc.v:151946$7678_Y + attribute \src "libresoc.v:151966.18-151966.131" + wire $not$libresoc.v:151966$7698_Y + attribute \src "libresoc.v:151968.18-151968.114" + wire width 3 $not$libresoc.v:151968$7700_Y + attribute \src "libresoc.v:151934.18-151934.112" + wire $or$libresoc.v:151934$7666_Y + attribute \src "libresoc.v:151944.18-151944.122" + wire $or$libresoc.v:151944$7676_Y + attribute \src "libresoc.v:151945.18-151945.124" + wire $or$libresoc.v:151945$7677_Y + attribute \src "libresoc.v:151947.18-151947.168" + wire width 4 $or$libresoc.v:151947$7679_Y + attribute \src "libresoc.v:151948.18-151948.155" + wire width 3 $or$libresoc.v:151948$7680_Y + attribute \src "libresoc.v:151951.18-151951.120" + wire width 4 $or$libresoc.v:151951$7683_Y + attribute \src "libresoc.v:151957.17-151957.117" + wire width 3 $or$libresoc.v:151957$7689_Y + attribute \src "libresoc.v:151963.17-151963.104" + wire $reduce_and$libresoc.v:151963$7695_Y + attribute \src "libresoc.v:151928.18-151928.106" + wire $reduce_or$libresoc.v:151928$7660_Y + attribute \src "libresoc.v:151932.18-151932.113" + wire $reduce_or$libresoc.v:151932$7664_Y + attribute \src "libresoc.v:151933.18-151933.112" + wire $reduce_or$libresoc.v:151933$7665_Y + attribute \src "libresoc.v:151956.18-151956.160" + wire $ternary$libresoc.v:151956$7688_Y + attribute \src "libresoc.v:151958.18-151958.172" + wire width 64 $ternary$libresoc.v:151958$7690_Y + attribute \src "libresoc.v:151959.18-151959.118" + wire width 64 $ternary$libresoc.v:151959$7691_Y + attribute \src "libresoc.v:151960.18-151960.115" + wire width 64 $ternary$libresoc.v:151960$7692_Y + attribute \src "libresoc.v:151961.18-151961.118" + wire $ternary$libresoc.v:151961$7693_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -314332,9 +316829,9 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok @@ -314400,7 +316897,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:149680.7-149680.15" + attribute \src "libresoc.v:151312.7-151312.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok @@ -314609,7 +317106,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150277$7593 + cell $and $and$libresoc.v:151909$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314617,10 +317114,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:150277$7593_Y + connect \Y $and$libresoc.v:151909$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150278$7594 + cell $and $and$libresoc.v:151910$7642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314628,10 +317125,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150278$7594_Y + connect \Y $and$libresoc.v:151910$7642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150279$7595 + cell $and $and$libresoc.v:151911$7643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314639,10 +317136,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150279$7595_Y + connect \Y $and$libresoc.v:151911$7643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150280$7596 + cell $and $and$libresoc.v:151912$7644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314650,10 +317147,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150280$7596_Y + connect \Y $and$libresoc.v:151912$7644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:150281$7597 + cell $and $and$libresoc.v:151913$7645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314661,10 +317158,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:150281$7597_Y + connect \Y $and$libresoc.v:151913$7645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:150282$7598 + cell $and $and$libresoc.v:151914$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314672,10 +317169,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:150282$7598_Y + connect \Y $and$libresoc.v:151914$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:150283$7599 + cell $and $and$libresoc.v:151915$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314683,10 +317180,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:150283$7599_Y + connect \Y $and$libresoc.v:151915$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:150284$7600 + cell $and $and$libresoc.v:151916$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314694,10 +317191,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150284$7600_Y + connect \Y $and$libresoc.v:151916$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150285$7601 + cell $and $and$libresoc.v:151917$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314705,10 +317202,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150285$7601_Y + connect \Y $and$libresoc.v:151917$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150286$7602 + cell $and $and$libresoc.v:151918$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314716,10 +317213,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150286$7602_Y + connect \Y $and$libresoc.v:151918$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150287$7603 + cell $and $and$libresoc.v:151919$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314727,10 +317224,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150287$7603_Y + connect \Y $and$libresoc.v:151919$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:150288$7604 + cell $and $and$libresoc.v:151920$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314738,10 +317235,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:150288$7604_Y + connect \Y $and$libresoc.v:151920$7652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:150290$7606 + cell $and $and$libresoc.v:151922$7654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314749,10 +317246,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:150290$7606_Y + connect \Y $and$libresoc.v:151922$7654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:150292$7608 + cell $and $and$libresoc.v:151924$7656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314760,10 +317257,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:150292$7608_Y + connect \Y $and$libresoc.v:151924$7656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:150293$7609 + cell $and $and$libresoc.v:151925$7657 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314771,10 +317268,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:150293$7609_Y + connect \Y $and$libresoc.v:151925$7657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:150295$7611 + cell $and $and$libresoc.v:151927$7659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314782,10 +317279,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:150295$7611_Y + connect \Y $and$libresoc.v:151927$7659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:150298$7614 + cell $and $and$libresoc.v:151930$7662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314793,10 +317290,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:150298$7614_Y + connect \Y $and$libresoc.v:151930$7662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:150299$7615 + cell $and $and$libresoc.v:151931$7663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314804,10 +317301,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:150299$7615_Y + connect \Y $and$libresoc.v:151931$7663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:150304$7620 + cell $and $and$libresoc.v:151936$7668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314815,10 +317312,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:150304$7620_Y + connect \Y $and$libresoc.v:151936$7668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:150305$7621 + cell $and $and$libresoc.v:151937$7669 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314826,10 +317323,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150305$7621_Y + connect \Y $and$libresoc.v:151937$7669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:150307$7623 + cell $and $and$libresoc.v:151939$7671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314837,10 +317334,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:150307$7623_Y + connect \Y $and$libresoc.v:151939$7671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150309$7625 + cell $and $and$libresoc.v:151941$7673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314848,10 +317345,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:150309$7625_Y + connect \Y $and$libresoc.v:151941$7673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150310$7626 + cell $and $and$libresoc.v:151942$7674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314859,10 +317356,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:150310$7626_Y + connect \Y $and$libresoc.v:151942$7674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:150311$7627 + cell $and $and$libresoc.v:151943$7675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314870,10 +317367,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:150311$7627_Y + connect \Y $and$libresoc.v:151943$7675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:150317$7633 + cell $and $and$libresoc.v:151949$7681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314881,10 +317378,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:150317$7633_Y + connect \Y $and$libresoc.v:151949$7681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:150318$7634 + cell $and $and$libresoc.v:151950$7682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314892,10 +317389,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:150318$7634_Y + connect \Y $and$libresoc.v:151950$7682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150320$7636 + cell $and $and$libresoc.v:151952$7684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314903,10 +317400,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150320$7636_Y + connect \Y $and$libresoc.v:151952$7684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150321$7637 + cell $and $and$libresoc.v:151953$7685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314914,10 +317411,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150321$7637_Y + connect \Y $and$libresoc.v:151953$7685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150322$7638 + cell $and $and$libresoc.v:151954$7686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314925,10 +317422,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150322$7638_Y + connect \Y $and$libresoc.v:151954$7686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:150323$7639 + cell $and $and$libresoc.v:151955$7687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314936,10 +317433,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:150323$7639_Y + connect \Y $and$libresoc.v:151955$7687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:150330$7646 + cell $and $and$libresoc.v:151962$7694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314947,10 +317444,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:150330$7646_Y + connect \Y $and$libresoc.v:151962$7694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:150332$7648 + cell $and $and$libresoc.v:151964$7696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314958,10 +317455,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:150332$7648_Y + connect \Y $and$libresoc.v:151964$7696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150333$7649 + cell $and $and$libresoc.v:151965$7697 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314969,10 +317466,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:150333$7649_Y + connect \Y $and$libresoc.v:151965$7697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:150335$7651 + cell $and $and$libresoc.v:151967$7699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314980,10 +317477,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:150335$7651_Y + connect \Y $and$libresoc.v:151967$7699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:150306$7622 + cell $eq $eq$libresoc.v:151938$7670 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314991,10 +317488,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:150306$7622_Y + connect \Y $eq$libresoc.v:151938$7670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:150308$7624 + cell $eq $eq$libresoc.v:151940$7672 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315002,74 +317499,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:150308$7624_Y + connect \Y $eq$libresoc.v:151940$7672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:150289$7605 + cell $not $not$libresoc.v:151921$7653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:150289$7605_Y + connect \Y $not$libresoc.v:151921$7653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:150291$7607 + cell $not $not$libresoc.v:151923$7655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:150291$7607_Y + connect \Y $not$libresoc.v:151923$7655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:150294$7610 + cell $not $not$libresoc.v:151926$7658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:150294$7610_Y + connect \Y $not$libresoc.v:151926$7658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:150297$7613 + cell $not $not$libresoc.v:151929$7661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:150297$7613_Y + connect \Y $not$libresoc.v:151929$7661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:150303$7619 + cell $not $not$libresoc.v:151935$7667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:150303$7619_Y + connect \Y $not$libresoc.v:151935$7667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:150314$7630 + cell $not $not$libresoc.v:151946$7678 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:150314$7630_Y + connect \Y $not$libresoc.v:151946$7678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:150334$7650 + cell $not $not$libresoc.v:151966$7698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:150334$7650_Y + connect \Y $not$libresoc.v:151966$7698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:150336$7652 + cell $not $not$libresoc.v:151968$7700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:150336$7652_Y + connect \Y $not$libresoc.v:151968$7700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:150302$7618 + cell $or $or$libresoc.v:151934$7666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315077,10 +317574,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:150302$7618_Y + connect \Y $or$libresoc.v:151934$7666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:150312$7628 + cell $or $or$libresoc.v:151944$7676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315088,10 +317585,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:150312$7628_Y + connect \Y $or$libresoc.v:151944$7676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:150313$7629 + cell $or $or$libresoc.v:151945$7677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -315099,10 +317596,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:150313$7629_Y + connect \Y $or$libresoc.v:151945$7677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:150315$7631 + cell $or $or$libresoc.v:151947$7679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315110,10 +317607,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:150315$7631_Y + connect \Y $or$libresoc.v:151947$7679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:150316$7632 + cell $or $or$libresoc.v:151948$7680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -315121,10 +317618,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:150316$7632_Y + connect \Y $or$libresoc.v:151948$7680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:150319$7635 + cell $or $or$libresoc.v:151951$7683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -315132,10 +317629,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:150319$7635_Y + connect \Y $or$libresoc.v:151951$7683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:150325$7641 + cell $or $or$libresoc.v:151957$7689 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -315143,82 +317640,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:150325$7641_Y + connect \Y $or$libresoc.v:151957$7689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:150331$7647 + cell $reduce_and $reduce_and$libresoc.v:151963$7695 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:150331$7647_Y + connect \Y $reduce_and$libresoc.v:151963$7695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:150296$7612 + cell $reduce_or $reduce_or$libresoc.v:151928$7660 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:150296$7612_Y + connect \Y $reduce_or$libresoc.v:151928$7660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:150300$7616 + cell $reduce_or $reduce_or$libresoc.v:151932$7664 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:150300$7616_Y + connect \Y $reduce_or$libresoc.v:151932$7664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:150301$7617 + cell $reduce_or $reduce_or$libresoc.v:151933$7665 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:150301$7617_Y + connect \Y $reduce_or$libresoc.v:151933$7665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:150324$7640 + cell $mux $ternary$libresoc.v:151956$7688 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:150324$7640_Y + connect \Y $ternary$libresoc.v:151956$7688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:150326$7642 + cell $mux $ternary$libresoc.v:151958$7690 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:150326$7642_Y + connect \Y $ternary$libresoc.v:151958$7690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150327$7643 + cell $mux $ternary$libresoc.v:151959$7691 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:150327$7643_Y + connect \Y $ternary$libresoc.v:151959$7691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150328$7644 + cell $mux $ternary$libresoc.v:151960$7692 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:150328$7644_Y + connect \Y $ternary$libresoc.v:151960$7692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:150329$7645 + cell $mux $ternary$libresoc.v:151961$7693 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:150329$7645_Y + connect \Y $ternary$libresoc.v:151961$7693_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150413.15-150419.4" + attribute \src "libresoc.v:152045.15-152051.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315227,7 +317724,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:150420.12-150450.4" + attribute \src "libresoc.v:152052.12-152082.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315260,7 +317757,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:150451.16-150457.4" + attribute \src "libresoc.v:152083.16-152089.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315269,7 +317766,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:150458.15-150464.4" + attribute \src "libresoc.v:152090.15-152096.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315278,7 +317775,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:150465.15-150471.4" + attribute \src "libresoc.v:152097.15-152103.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315287,7 +317784,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:150472.15-150478.4" + attribute \src "libresoc.v:152104.15-152110.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315296,7 +317793,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:150479.15-150484.4" + attribute \src "libresoc.v:152111.15-152116.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315304,7 +317801,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:150485.15-150491.4" + attribute \src "libresoc.v:152117.15-152123.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -315312,592 +317809,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:149680.7-149680.20" - process $proc$libresoc.v:149680$7807 + attribute \src "libresoc.v:151312.7-151312.20" + process $proc$libresoc.v:151312$7855 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149804.7-149804.24" - process $proc$libresoc.v:149804$7808 + attribute \src "libresoc.v:151436.7-151436.24" + process $proc$libresoc.v:151436$7856 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:149814.7-149814.26" - process $proc$libresoc.v:149814$7809 + attribute \src "libresoc.v:151446.7-151446.26" + process $proc$libresoc.v:151446$7857 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:149822.7-149822.25" - process $proc$libresoc.v:149822$7810 + attribute \src "libresoc.v:151454.7-151454.25" + process $proc$libresoc.v:151454$7858 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:149845.14-149845.49" - process $proc$libresoc.v:149845$7811 + attribute \src "libresoc.v:151477.14-151477.49" + process $proc$libresoc.v:151477$7859 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:149849.14-149849.68" - process $proc$libresoc.v:149849$7812 + attribute \src "libresoc.v:151481.14-151481.68" + process $proc$libresoc.v:151481$7860 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:149853.7-149853.43" - process $proc$libresoc.v:149853$7813 + attribute \src "libresoc.v:151485.7-151485.43" + process $proc$libresoc.v:151485$7861 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:149857.14-149857.43" - process $proc$libresoc.v:149857$7814 + attribute \src "libresoc.v:151489.14-151489.43" + process $proc$libresoc.v:151489$7862 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:149936.13-149936.47" - process $proc$libresoc.v:149936$7815 + attribute \src "libresoc.v:151568.13-151568.47" + process $proc$libresoc.v:151568$7863 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:149940.7-149940.39" - process $proc$libresoc.v:149940$7816 + attribute \src "libresoc.v:151572.7-151572.39" + process $proc$libresoc.v:151572$7864 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:149944.7-149944.40" - process $proc$libresoc.v:149944$7817 + attribute \src "libresoc.v:151576.7-151576.40" + process $proc$libresoc.v:151576$7865 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:149948.7-149948.37" - process $proc$libresoc.v:149948$7818 + attribute \src "libresoc.v:151580.7-151580.37" + process $proc$libresoc.v:151580$7866 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:149952.7-149952.37" - process $proc$libresoc.v:149952$7819 + attribute \src "libresoc.v:151584.7-151584.37" + process $proc$libresoc.v:151584$7867 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:149956.7-149956.37" - process $proc$libresoc.v:149956$7820 + attribute \src "libresoc.v:151588.7-151588.37" + process $proc$libresoc.v:151588$7868 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:149960.7-149960.37" - process $proc$libresoc.v:149960$7821 + attribute \src "libresoc.v:151592.7-151592.37" + process $proc$libresoc.v:151592$7869 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:149964.7-149964.40" - process $proc$libresoc.v:149964$7822 + attribute \src "libresoc.v:151596.7-151596.40" + process $proc$libresoc.v:151596$7870 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:149994.7-149994.27" - process $proc$libresoc.v:149994$7823 + attribute \src "libresoc.v:151626.7-151626.27" + process $proc$libresoc.v:151626$7871 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:150028.14-150028.47" - process $proc$libresoc.v:150028$7824 + attribute \src "libresoc.v:151660.14-151660.47" + process $proc$libresoc.v:151660$7872 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:150032.7-150032.27" - process $proc$libresoc.v:150032$7825 + attribute \src "libresoc.v:151664.7-151664.27" + process $proc$libresoc.v:151664$7873 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:150036.13-150036.33" - process $proc$libresoc.v:150036$7826 + attribute \src "libresoc.v:151668.13-151668.33" + process $proc$libresoc.v:151668$7874 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:150040.7-150040.30" - process $proc$libresoc.v:150040$7827 + attribute \src "libresoc.v:151672.7-151672.30" + process $proc$libresoc.v:151672$7875 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:150044.13-150044.35" - process $proc$libresoc.v:150044$7828 + attribute \src "libresoc.v:151676.13-151676.35" + process $proc$libresoc.v:151676$7876 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:150048.7-150048.32" - process $proc$libresoc.v:150048$7829 + attribute \src "libresoc.v:151680.7-151680.32" + process $proc$libresoc.v:151680$7877 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:150052.7-150052.29" - process $proc$libresoc.v:150052$7830 + attribute \src "libresoc.v:151684.7-151684.29" + process $proc$libresoc.v:151684$7878 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:150056.7-150056.32" - process $proc$libresoc.v:150056$7831 + attribute \src "libresoc.v:151688.7-151688.32" + process $proc$libresoc.v:151688$7879 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:150076.7-150076.25" - process $proc$libresoc.v:150076$7832 + attribute \src "libresoc.v:151708.7-151708.25" + process $proc$libresoc.v:151708$7880 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:150080.7-150080.25" - process $proc$libresoc.v:150080$7833 + attribute \src "libresoc.v:151712.7-151712.25" + process $proc$libresoc.v:151712$7881 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:150198.13-150198.30" - process $proc$libresoc.v:150198$7834 + attribute \src "libresoc.v:151830.13-151830.30" + process $proc$libresoc.v:151830$7882 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:150206.13-150206.31" - process $proc$libresoc.v:150206$7835 + attribute \src "libresoc.v:151838.13-151838.31" + process $proc$libresoc.v:151838$7883 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:150210.13-150210.31" - process $proc$libresoc.v:150210$7836 + attribute \src "libresoc.v:151842.13-151842.31" + process $proc$libresoc.v:151842$7884 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:150222.7-150222.26" - process $proc$libresoc.v:150222$7837 + attribute \src "libresoc.v:151854.7-151854.26" + process $proc$libresoc.v:151854$7885 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:150226.7-150226.26" - process $proc$libresoc.v:150226$7838 + attribute \src "libresoc.v:151858.7-151858.26" + process $proc$libresoc.v:151858$7886 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:150230.7-150230.25" - process $proc$libresoc.v:150230$7839 + attribute \src "libresoc.v:151862.7-151862.25" + process $proc$libresoc.v:151862$7887 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:150234.7-150234.25" - process $proc$libresoc.v:150234$7840 + attribute \src "libresoc.v:151866.7-151866.25" + process $proc$libresoc.v:151866$7888 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:150248.13-150248.31" - process $proc$libresoc.v:150248$7841 + attribute \src "libresoc.v:151880.13-151880.31" + process $proc$libresoc.v:151880$7889 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:150252.13-150252.31" - process $proc$libresoc.v:150252$7842 + attribute \src "libresoc.v:151884.13-151884.31" + process $proc$libresoc.v:151884$7890 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:150258.14-150258.43" - process $proc$libresoc.v:150258$7843 + attribute \src "libresoc.v:151890.14-151890.43" + process $proc$libresoc.v:151890$7891 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:150262.14-150262.43" - process $proc$libresoc.v:150262$7844 + attribute \src "libresoc.v:151894.14-151894.43" + process $proc$libresoc.v:151894$7892 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:150266.7-150266.20" - process $proc$libresoc.v:150266$7845 + attribute \src "libresoc.v:151898.7-151898.20" + process $proc$libresoc.v:151898$7893 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:150337.3-150338.39" - process $proc$libresoc.v:150337$7653 + attribute \src "libresoc.v:151969.3-151970.39" + process $proc$libresoc.v:151969$7701 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:150339.3-150340.43" - process $proc$libresoc.v:150339$7654 + attribute \src "libresoc.v:151971.3-151972.43" + process $proc$libresoc.v:151971$7702 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:150341.3-150342.29" - process $proc$libresoc.v:150341$7655 + attribute \src "libresoc.v:151973.3-151974.29" + process $proc$libresoc.v:151973$7703 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:150343.3-150344.29" - process $proc$libresoc.v:150343$7656 + attribute \src "libresoc.v:151975.3-151976.29" + process $proc$libresoc.v:151975$7704 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:150345.3-150346.29" - process $proc$libresoc.v:150345$7657 + attribute \src "libresoc.v:151977.3-151978.29" + process $proc$libresoc.v:151977$7705 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:150347.3-150348.47" - process $proc$libresoc.v:150347$7658 + attribute \src "libresoc.v:151979.3-151980.47" + process $proc$libresoc.v:151979$7706 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:150349.3-150350.53" - process $proc$libresoc.v:150349$7659 + attribute \src "libresoc.v:151981.3-151982.53" + process $proc$libresoc.v:151981$7707 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:150351.3-150352.47" - process $proc$libresoc.v:150351$7660 + attribute \src "libresoc.v:151983.3-151984.47" + process $proc$libresoc.v:151983$7708 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:150353.3-150354.53" - process $proc$libresoc.v:150353$7661 + attribute \src "libresoc.v:151985.3-151986.53" + process $proc$libresoc.v:151985$7709 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:150355.3-150356.43" - process $proc$libresoc.v:150355$7662 + attribute \src "libresoc.v:151987.3-151988.43" + process $proc$libresoc.v:151987$7710 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:150357.3-150358.49" - process $proc$libresoc.v:150357$7663 + attribute \src "libresoc.v:151989.3-151990.49" + process $proc$libresoc.v:151989$7711 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:150359.3-150360.37" - process $proc$libresoc.v:150359$7664 + attribute \src "libresoc.v:151991.3-151992.37" + process $proc$libresoc.v:151991$7712 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:150361.3-150362.43" - process $proc$libresoc.v:150361$7665 + attribute \src "libresoc.v:151993.3-151994.43" + process $proc$libresoc.v:151993$7713 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:150363.3-150364.69" - process $proc$libresoc.v:150363$7666 + attribute \src "libresoc.v:151995.3-151996.69" + process $proc$libresoc.v:151995$7714 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:150365.3-150366.65" - process $proc$libresoc.v:150365$7667 + attribute \src "libresoc.v:151997.3-151998.65" + process $proc$libresoc.v:151997$7715 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:150367.3-150368.79" - process $proc$libresoc.v:150367$7668 + attribute \src "libresoc.v:151999.3-152000.79" + process $proc$libresoc.v:151999$7716 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:150369.3-150370.75" - process $proc$libresoc.v:150369$7669 + attribute \src "libresoc.v:152001.3-152002.75" + process $proc$libresoc.v:152001$7717 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:150371.3-150372.63" - process $proc$libresoc.v:150371$7670 + attribute \src "libresoc.v:152003.3-152004.63" + process $proc$libresoc.v:152003$7718 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:150373.3-150374.63" - process $proc$libresoc.v:150373$7671 + attribute \src "libresoc.v:152005.3-152006.63" + process $proc$libresoc.v:152005$7719 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:150375.3-150376.63" - process $proc$libresoc.v:150375$7672 + attribute \src "libresoc.v:152007.3-152008.63" + process $proc$libresoc.v:152007$7720 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:150377.3-150378.63" - process $proc$libresoc.v:150377$7673 + attribute \src "libresoc.v:152009.3-152010.63" + process $proc$libresoc.v:152009$7721 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:150379.3-150380.69" - process $proc$libresoc.v:150379$7674 + attribute \src "libresoc.v:152011.3-152012.69" + process $proc$libresoc.v:152011$7722 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:150381.3-150382.67" - process $proc$libresoc.v:150381$7675 + attribute \src "libresoc.v:152013.3-152014.67" + process $proc$libresoc.v:152013$7723 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:150383.3-150384.69" - process $proc$libresoc.v:150383$7676 + attribute \src "libresoc.v:152015.3-152016.69" + process $proc$libresoc.v:152015$7724 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:150385.3-150386.59" - process $proc$libresoc.v:150385$7677 + attribute \src "libresoc.v:152017.3-152018.59" + process $proc$libresoc.v:152017$7725 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:150387.3-150388.39" - process $proc$libresoc.v:150387$7678 + attribute \src "libresoc.v:152019.3-152020.39" + process $proc$libresoc.v:152019$7726 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:150389.3-150390.39" - process $proc$libresoc.v:150389$7679 + attribute \src "libresoc.v:152021.3-152022.39" + process $proc$libresoc.v:152021$7727 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:150391.3-150392.39" - process $proc$libresoc.v:150391$7680 + attribute \src "libresoc.v:152023.3-152024.39" + process $proc$libresoc.v:152023$7728 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:150393.3-150394.39" - process $proc$libresoc.v:150393$7681 + attribute \src "libresoc.v:152025.3-152026.39" + process $proc$libresoc.v:152025$7729 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:150395.3-150396.39" - process $proc$libresoc.v:150395$7682 + attribute \src "libresoc.v:152027.3-152028.39" + process $proc$libresoc.v:152027$7730 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:150397.3-150398.39" - process $proc$libresoc.v:150397$7683 + attribute \src "libresoc.v:152029.3-152030.39" + process $proc$libresoc.v:152029$7731 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:150399.3-150400.39" - process $proc$libresoc.v:150399$7684 + attribute \src "libresoc.v:152031.3-152032.39" + process $proc$libresoc.v:152031$7732 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:150401.3-150402.39" - process $proc$libresoc.v:150401$7685 + attribute \src "libresoc.v:152033.3-152034.39" + process $proc$libresoc.v:152033$7733 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:150403.3-150404.41" - process $proc$libresoc.v:150403$7686 + attribute \src "libresoc.v:152035.3-152036.41" + process $proc$libresoc.v:152035$7734 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:150405.3-150406.41" - process $proc$libresoc.v:150405$7687 + attribute \src "libresoc.v:152037.3-152038.41" + process $proc$libresoc.v:152037$7735 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:150407.3-150408.37" - process $proc$libresoc.v:150407$7688 + attribute \src "libresoc.v:152039.3-152040.37" + process $proc$libresoc.v:152039$7736 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:150409.3-150410.40" - process $proc$libresoc.v:150409$7689 + attribute \src "libresoc.v:152041.3-152042.40" + process $proc$libresoc.v:152041$7737 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:150411.3-150412.25" - process $proc$libresoc.v:150411$7690 + attribute \src "libresoc.v:152043.3-152044.25" + process $proc$libresoc.v:152043$7738 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:150492.3-150501.6" - process $proc$libresoc.v:150492$7691 + attribute \src "libresoc.v:152124.3-152133.6" + process $proc$libresoc.v:152124$7739 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:150493.5-150493.29" + attribute \src "libresoc.v:152125.5-152125.29" switch \initial - attribute \src "libresoc.v:150493.9-150493.17" + attribute \src "libresoc.v:152125.9-152125.17" case 1'1 case end @@ -315913,14 +318410,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:150502.3-150510.6" - process $proc$libresoc.v:150502$7692 + attribute \src "libresoc.v:152134.3-152142.6" + process $proc$libresoc.v:152134$7740 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7693 $1\rok_l_s_rdok$next[0:0]$7694 - attribute \src "libresoc.v:150503.5-150503.29" + assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 + attribute \src "libresoc.v:152135.5-152135.29" switch \initial - attribute \src "libresoc.v:150503.9-150503.17" + attribute \src "libresoc.v:152135.9-152135.17" case 1'1 case end @@ -315929,21 +318426,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7694 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7742 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7694 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7742 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7693 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 end - attribute \src "libresoc.v:150511.3-150519.6" - process $proc$libresoc.v:150511$7695 + attribute \src "libresoc.v:152143.3-152151.6" + process $proc$libresoc.v:152143$7743 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7696 $1\rok_l_r_rdok$next[0:0]$7697 - attribute \src "libresoc.v:150512.5-150512.29" + assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 + attribute \src "libresoc.v:152144.5-152144.29" switch \initial - attribute \src "libresoc.v:150512.9-150512.17" + attribute \src "libresoc.v:152144.9-152144.17" case 1'1 case end @@ -315952,21 +318449,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7697 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7745 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7697 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7745 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7696 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 end - attribute \src "libresoc.v:150520.3-150528.6" - process $proc$libresoc.v:150520$7698 + attribute \src "libresoc.v:152152.3-152160.6" + process $proc$libresoc.v:152152$7746 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7699 $1\rst_l_s_rst$next[0:0]$7700 - attribute \src "libresoc.v:150521.5-150521.29" + assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 + attribute \src "libresoc.v:152153.5-152153.29" switch \initial - attribute \src "libresoc.v:150521.9-150521.17" + attribute \src "libresoc.v:152153.9-152153.17" case 1'1 case end @@ -315975,21 +318472,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7700 1'0 + assign $1\rst_l_s_rst$next[0:0]$7748 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7700 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7748 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7699 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 end - attribute \src "libresoc.v:150529.3-150537.6" - process $proc$libresoc.v:150529$7701 + attribute \src "libresoc.v:152161.3-152169.6" + process $proc$libresoc.v:152161$7749 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7702 $1\rst_l_r_rst$next[0:0]$7703 - attribute \src "libresoc.v:150530.5-150530.29" + assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 + attribute \src "libresoc.v:152162.5-152162.29" switch \initial - attribute \src "libresoc.v:150530.9-150530.17" + attribute \src "libresoc.v:152162.9-152162.17" case 1'1 case end @@ -315998,21 +318495,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7703 1'1 + assign $1\rst_l_r_rst$next[0:0]$7751 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7703 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7751 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7702 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 end - attribute \src "libresoc.v:150538.3-150546.6" - process $proc$libresoc.v:150538$7704 + attribute \src "libresoc.v:152170.3-152178.6" + process $proc$libresoc.v:152170$7752 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7705 $1\opc_l_s_opc$next[0:0]$7706 - attribute \src "libresoc.v:150539.5-150539.29" + assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 + attribute \src "libresoc.v:152171.5-152171.29" switch \initial - attribute \src "libresoc.v:150539.9-150539.17" + attribute \src "libresoc.v:152171.9-152171.17" case 1'1 case end @@ -316021,21 +318518,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7706 1'0 + assign $1\opc_l_s_opc$next[0:0]$7754 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7706 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7754 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7705 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 end - attribute \src "libresoc.v:150547.3-150555.6" - process $proc$libresoc.v:150547$7707 + attribute \src "libresoc.v:152179.3-152187.6" + process $proc$libresoc.v:152179$7755 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7708 $1\opc_l_r_opc$next[0:0]$7709 - attribute \src "libresoc.v:150548.5-150548.29" + assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 + attribute \src "libresoc.v:152180.5-152180.29" switch \initial - attribute \src "libresoc.v:150548.9-150548.17" + attribute \src "libresoc.v:152180.9-152180.17" case 1'1 case end @@ -316044,21 +318541,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7709 1'1 + assign $1\opc_l_r_opc$next[0:0]$7757 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7709 \req_done + assign $1\opc_l_r_opc$next[0:0]$7757 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7708 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 end - attribute \src "libresoc.v:150556.3-150564.6" - process $proc$libresoc.v:150556$7710 + attribute \src "libresoc.v:152188.3-152196.6" + process $proc$libresoc.v:152188$7758 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7711 $1\src_l_s_src$next[2:0]$7712 - attribute \src "libresoc.v:150557.5-150557.29" + assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 + attribute \src "libresoc.v:152189.5-152189.29" switch \initial - attribute \src "libresoc.v:150557.9-150557.17" + attribute \src "libresoc.v:152189.9-152189.17" case 1'1 case end @@ -316067,21 +318564,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7712 3'000 + assign $1\src_l_s_src$next[2:0]$7760 3'000 case - assign $1\src_l_s_src$next[2:0]$7712 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7760 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7711 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 end - attribute \src "libresoc.v:150565.3-150573.6" - process $proc$libresoc.v:150565$7713 + attribute \src "libresoc.v:152197.3-152205.6" + process $proc$libresoc.v:152197$7761 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7714 $1\src_l_r_src$next[2:0]$7715 - attribute \src "libresoc.v:150566.5-150566.29" + assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 + attribute \src "libresoc.v:152198.5-152198.29" switch \initial - attribute \src "libresoc.v:150566.9-150566.17" + attribute \src "libresoc.v:152198.9-152198.17" case 1'1 case end @@ -316090,21 +318587,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7715 3'111 + assign $1\src_l_r_src$next[2:0]$7763 3'111 case - assign $1\src_l_r_src$next[2:0]$7715 \reset_r + assign $1\src_l_r_src$next[2:0]$7763 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7714 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 end - attribute \src "libresoc.v:150574.3-150582.6" - process $proc$libresoc.v:150574$7716 + attribute \src "libresoc.v:152206.3-152214.6" + process $proc$libresoc.v:152206$7764 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7717 $1\req_l_s_req$next[3:0]$7718 - attribute \src "libresoc.v:150575.5-150575.29" + assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 + attribute \src "libresoc.v:152207.5-152207.29" switch \initial - attribute \src "libresoc.v:150575.9-150575.17" + attribute \src "libresoc.v:152207.9-152207.17" case 1'1 case end @@ -316113,21 +318610,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7718 4'0000 + assign $1\req_l_s_req$next[3:0]$7766 4'0000 case - assign $1\req_l_s_req$next[3:0]$7718 \$66 + assign $1\req_l_s_req$next[3:0]$7766 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7717 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 end - attribute \src "libresoc.v:150583.3-150591.6" - process $proc$libresoc.v:150583$7719 + attribute \src "libresoc.v:152215.3-152223.6" + process $proc$libresoc.v:152215$7767 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7720 $1\req_l_r_req$next[3:0]$7721 - attribute \src "libresoc.v:150584.5-150584.29" + assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 + attribute \src "libresoc.v:152216.5-152216.29" switch \initial - attribute \src "libresoc.v:150584.9-150584.17" + attribute \src "libresoc.v:152216.9-152216.17" case 1'1 case end @@ -316136,15 +318633,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7721 4'1111 + assign $1\req_l_r_req$next[3:0]$7769 4'1111 case - assign $1\req_l_r_req$next[3:0]$7721 \$68 + assign $1\req_l_r_req$next[3:0]$7769 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7720 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 end - attribute \src "libresoc.v:150592.3-150624.6" - process $proc$libresoc.v:150592$7722 + attribute \src "libresoc.v:152224.3-152256.6" + process $proc$libresoc.v:152224$7770 assign { } { } assign { } { } assign { } { } @@ -316169,27 +318666,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7726 $1\alu_mul0_mul_op__insn$next[31:0]$7738 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7774 $1\alu_mul0_mul_op__insn$next[31:0]$7786 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 - attribute \src "libresoc.v:150593.5-150593.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 + attribute \src "libresoc.v:152225.5-152225.29" switch \initial - attribute \src "libresoc.v:150593.9-150593.17" + attribute \src "libresoc.v:152225.9-152225.17" case 1'1 case end @@ -316209,20 +318706,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7738 $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7786 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7735 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7738 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7739 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7740 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7741 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7746 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7786 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -316234,48 +318731,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7747 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7736 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7748 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7737 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7749 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7742 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7750 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7743 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7751 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7744 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7752 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7745 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7723 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7724 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7725 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7726 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7727 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7728 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7729 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7730 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7731 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7732 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7733 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7734 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7774 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 end - attribute \src "libresoc.v:150625.3-150646.6" - process $proc$libresoc.v:150625$7753 + attribute \src "libresoc.v:152257.3-152278.6" + process $proc$libresoc.v:152257$7801 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7754 $2\data_r0__o$next[63:0]$7758 + assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7755 $3\data_r0__o_ok$next[0:0]$7760 - attribute \src "libresoc.v:150626.5-150626.29" + assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 + attribute \src "libresoc.v:152258.5-152258.29" switch \initial - attribute \src "libresoc.v:150626.9-150626.17" + attribute \src "libresoc.v:152258.9-152258.17" case 1'1 case end @@ -316285,10 +318782,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7757 $1\data_r0__o$next[63:0]$7756 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7805 $1\data_r0__o$next[63:0]$7804 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7756 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7757 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7804 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7805 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316296,38 +318793,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7759 $2\data_r0__o$next[63:0]$7758 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7807 $2\data_r0__o$next[63:0]$7806 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7758 $1\data_r0__o$next[63:0]$7756 - assign $2\data_r0__o_ok$next[0:0]$7759 $1\data_r0__o_ok$next[0:0]$7757 + assign $2\data_r0__o$next[63:0]$7806 $1\data_r0__o$next[63:0]$7804 + assign $2\data_r0__o_ok$next[0:0]$7807 $1\data_r0__o_ok$next[0:0]$7805 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7760 1'0 + assign $3\data_r0__o_ok$next[0:0]$7808 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7760 $2\data_r0__o_ok$next[0:0]$7759 + assign $3\data_r0__o_ok$next[0:0]$7808 $2\data_r0__o_ok$next[0:0]$7807 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7754 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7755 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 end - attribute \src "libresoc.v:150647.3-150668.6" - process $proc$libresoc.v:150647$7761 + attribute \src "libresoc.v:152279.3-152300.6" + process $proc$libresoc.v:152279$7809 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7762 $2\data_r1__cr_a$next[3:0]$7766 + assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7763 $3\data_r1__cr_a_ok$next[0:0]$7768 - attribute \src "libresoc.v:150648.5-150648.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 + attribute \src "libresoc.v:152280.5-152280.29" switch \initial - attribute \src "libresoc.v:150648.9-150648.17" + attribute \src "libresoc.v:152280.9-152280.17" case 1'1 case end @@ -316337,10 +318834,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7765 $1\data_r1__cr_a$next[3:0]$7764 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7813 $1\data_r1__cr_a$next[3:0]$7812 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7764 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7765 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7812 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7813 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316348,38 +318845,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7767 $2\data_r1__cr_a$next[3:0]$7766 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7815 $2\data_r1__cr_a$next[3:0]$7814 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7766 $1\data_r1__cr_a$next[3:0]$7764 - assign $2\data_r1__cr_a_ok$next[0:0]$7767 $1\data_r1__cr_a_ok$next[0:0]$7765 + assign $2\data_r1__cr_a$next[3:0]$7814 $1\data_r1__cr_a$next[3:0]$7812 + assign $2\data_r1__cr_a_ok$next[0:0]$7815 $1\data_r1__cr_a_ok$next[0:0]$7813 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7768 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7816 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7768 $2\data_r1__cr_a_ok$next[0:0]$7767 + assign $3\data_r1__cr_a_ok$next[0:0]$7816 $2\data_r1__cr_a_ok$next[0:0]$7815 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7762 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7763 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 end - attribute \src "libresoc.v:150669.3-150690.6" - process $proc$libresoc.v:150669$7769 + attribute \src "libresoc.v:152301.3-152322.6" + process $proc$libresoc.v:152301$7817 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7770 $2\data_r2__xer_ov$next[1:0]$7774 + assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7771 $3\data_r2__xer_ov_ok$next[0:0]$7776 - attribute \src "libresoc.v:150670.5-150670.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 + attribute \src "libresoc.v:152302.5-152302.29" switch \initial - attribute \src "libresoc.v:150670.9-150670.17" + attribute \src "libresoc.v:152302.9-152302.17" case 1'1 case end @@ -316389,10 +318886,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7773 $1\data_r2__xer_ov$next[1:0]$7772 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7821 $1\data_r2__xer_ov$next[1:0]$7820 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7772 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7773 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7820 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7821 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316400,38 +318897,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7775 $2\data_r2__xer_ov$next[1:0]$7774 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7823 $2\data_r2__xer_ov$next[1:0]$7822 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7774 $1\data_r2__xer_ov$next[1:0]$7772 - assign $2\data_r2__xer_ov_ok$next[0:0]$7775 $1\data_r2__xer_ov_ok$next[0:0]$7773 + assign $2\data_r2__xer_ov$next[1:0]$7822 $1\data_r2__xer_ov$next[1:0]$7820 + assign $2\data_r2__xer_ov_ok$next[0:0]$7823 $1\data_r2__xer_ov_ok$next[0:0]$7821 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7776 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7776 $2\data_r2__xer_ov_ok$next[0:0]$7775 + assign $3\data_r2__xer_ov_ok$next[0:0]$7824 $2\data_r2__xer_ov_ok$next[0:0]$7823 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7770 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7771 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 end - attribute \src "libresoc.v:150691.3-150712.6" - process $proc$libresoc.v:150691$7777 + attribute \src "libresoc.v:152323.3-152344.6" + process $proc$libresoc.v:152323$7825 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7778 $2\data_r3__xer_so$next[0:0]$7782 + assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7779 $3\data_r3__xer_so_ok$next[0:0]$7784 - attribute \src "libresoc.v:150692.5-150692.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 + attribute \src "libresoc.v:152324.5-152324.29" switch \initial - attribute \src "libresoc.v:150692.9-150692.17" + attribute \src "libresoc.v:152324.9-152324.17" case 1'1 case end @@ -316441,10 +318938,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7781 $1\data_r3__xer_so$next[0:0]$7780 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7829 $1\data_r3__xer_so$next[0:0]$7828 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7780 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7781 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7828 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7829 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -316452,32 +318949,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7783 $2\data_r3__xer_so$next[0:0]$7782 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7831 $2\data_r3__xer_so$next[0:0]$7830 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7782 $1\data_r3__xer_so$next[0:0]$7780 - assign $2\data_r3__xer_so_ok$next[0:0]$7783 $1\data_r3__xer_so_ok$next[0:0]$7781 + assign $2\data_r3__xer_so$next[0:0]$7830 $1\data_r3__xer_so$next[0:0]$7828 + assign $2\data_r3__xer_so_ok$next[0:0]$7831 $1\data_r3__xer_so_ok$next[0:0]$7829 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7784 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7832 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7784 $2\data_r3__xer_so_ok$next[0:0]$7783 + assign $3\data_r3__xer_so_ok$next[0:0]$7832 $2\data_r3__xer_so_ok$next[0:0]$7831 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7778 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7779 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 end - attribute \src "libresoc.v:150713.3-150722.6" - process $proc$libresoc.v:150713$7785 + attribute \src "libresoc.v:152345.3-152354.6" + process $proc$libresoc.v:152345$7833 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7786 $1\src_r0$next[63:0]$7787 - attribute \src "libresoc.v:150714.5-150714.29" + assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 + attribute \src "libresoc.v:152346.5-152346.29" switch \initial - attribute \src "libresoc.v:150714.9-150714.17" + attribute \src "libresoc.v:152346.9-152346.17" case 1'1 case end @@ -316486,21 +318983,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7787 \src1_i + assign $1\src_r0$next[63:0]$7835 \src1_i case - assign $1\src_r0$next[63:0]$7787 \src_r0 + assign $1\src_r0$next[63:0]$7835 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7786 + update \src_r0$next $0\src_r0$next[63:0]$7834 end - attribute \src "libresoc.v:150723.3-150732.6" - process $proc$libresoc.v:150723$7788 + attribute \src "libresoc.v:152355.3-152364.6" + process $proc$libresoc.v:152355$7836 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7789 $1\src_r1$next[63:0]$7790 - attribute \src "libresoc.v:150724.5-150724.29" + assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 + attribute \src "libresoc.v:152356.5-152356.29" switch \initial - attribute \src "libresoc.v:150724.9-150724.17" + attribute \src "libresoc.v:152356.9-152356.17" case 1'1 case end @@ -316509,21 +319006,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7790 \src_or_imm + assign $1\src_r1$next[63:0]$7838 \src_or_imm case - assign $1\src_r1$next[63:0]$7790 \src_r1 + assign $1\src_r1$next[63:0]$7838 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7789 + update \src_r1$next $0\src_r1$next[63:0]$7837 end - attribute \src "libresoc.v:150733.3-150742.6" - process $proc$libresoc.v:150733$7791 + attribute \src "libresoc.v:152365.3-152374.6" + process $proc$libresoc.v:152365$7839 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7792 $1\src_r2$next[0:0]$7793 - attribute \src "libresoc.v:150734.5-150734.29" + assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 + attribute \src "libresoc.v:152366.5-152366.29" switch \initial - attribute \src "libresoc.v:150734.9-150734.17" + attribute \src "libresoc.v:152366.9-152366.17" case 1'1 case end @@ -316532,21 +319029,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7793 \src3_i + assign $1\src_r2$next[0:0]$7841 \src3_i case - assign $1\src_r2$next[0:0]$7793 \src_r2 + assign $1\src_r2$next[0:0]$7841 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7792 + update \src_r2$next $0\src_r2$next[0:0]$7840 end - attribute \src "libresoc.v:150743.3-150751.6" - process $proc$libresoc.v:150743$7794 + attribute \src "libresoc.v:152375.3-152383.6" + process $proc$libresoc.v:152375$7842 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7795 $1\alui_l_r_alui$next[0:0]$7796 - attribute \src "libresoc.v:150744.5-150744.29" + assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 + attribute \src "libresoc.v:152376.5-152376.29" switch \initial - attribute \src "libresoc.v:150744.9-150744.17" + attribute \src "libresoc.v:152376.9-152376.17" case 1'1 case end @@ -316555,21 +319052,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7796 1'1 + assign $1\alui_l_r_alui$next[0:0]$7844 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7796 \$88 + assign $1\alui_l_r_alui$next[0:0]$7844 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7795 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 end - attribute \src "libresoc.v:150752.3-150760.6" - process $proc$libresoc.v:150752$7797 + attribute \src "libresoc.v:152384.3-152392.6" + process $proc$libresoc.v:152384$7845 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7798 $1\alu_l_r_alu$next[0:0]$7799 - attribute \src "libresoc.v:150753.5-150753.29" + assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 + attribute \src "libresoc.v:152385.5-152385.29" switch \initial - attribute \src "libresoc.v:150753.9-150753.17" + attribute \src "libresoc.v:152385.9-152385.17" case 1'1 case end @@ -316578,21 +319075,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7799 1'1 + assign $1\alu_l_r_alu$next[0:0]$7847 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7799 \$90 + assign $1\alu_l_r_alu$next[0:0]$7847 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7798 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 end - attribute \src "libresoc.v:150761.3-150770.6" - process $proc$libresoc.v:150761$7800 + attribute \src "libresoc.v:152393.3-152402.6" + process $proc$libresoc.v:152393$7848 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:150762.5-150762.29" + attribute \src "libresoc.v:152394.5-152394.29" switch \initial - attribute \src "libresoc.v:150762.9-150762.17" + attribute \src "libresoc.v:152394.9-152394.17" case 1'1 case end @@ -316608,14 +319105,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:150771.3-150780.6" - process $proc$libresoc.v:150771$7801 + attribute \src "libresoc.v:152403.3-152412.6" + process $proc$libresoc.v:152403$7849 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:150772.5-150772.29" + attribute \src "libresoc.v:152404.5-152404.29" switch \initial - attribute \src "libresoc.v:150772.9-150772.17" + attribute \src "libresoc.v:152404.9-152404.17" case 1'1 case end @@ -316631,14 +319128,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:150781.3-150790.6" - process $proc$libresoc.v:150781$7802 + attribute \src "libresoc.v:152413.3-152422.6" + process $proc$libresoc.v:152413$7850 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:150782.5-150782.29" + attribute \src "libresoc.v:152414.5-152414.29" switch \initial - attribute \src "libresoc.v:150782.9-150782.17" + attribute \src "libresoc.v:152414.9-152414.17" case 1'1 case end @@ -316654,14 +319151,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:150791.3-150800.6" - process $proc$libresoc.v:150791$7803 + attribute \src "libresoc.v:152423.3-152432.6" + process $proc$libresoc.v:152423$7851 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:150792.5-150792.29" + attribute \src "libresoc.v:152424.5-152424.29" switch \initial - attribute \src "libresoc.v:150792.9-150792.17" + attribute \src "libresoc.v:152424.9-152424.17" case 1'1 case end @@ -316677,14 +319174,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:150801.3-150809.6" - process $proc$libresoc.v:150801$7804 + attribute \src "libresoc.v:152433.3-152441.6" + process $proc$libresoc.v:152433$7852 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7805 $1\prev_wr_go$next[3:0]$7806 - attribute \src "libresoc.v:150802.5-150802.29" + assign $0\prev_wr_go$next[3:0]$7853 $1\prev_wr_go$next[3:0]$7854 + attribute \src "libresoc.v:152434.5-152434.29" switch \initial - attribute \src "libresoc.v:150802.9-150802.17" + attribute \src "libresoc.v:152434.9-152434.17" case 1'1 case end @@ -316693,73 +319190,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7806 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7806 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7805 - end - connect \$100 $and$libresoc.v:150277$7593_Y - connect \$102 $and$libresoc.v:150278$7594_Y - connect \$104 $and$libresoc.v:150279$7595_Y - connect \$106 $and$libresoc.v:150280$7596_Y - connect \$108 $and$libresoc.v:150281$7597_Y - connect \$10 $and$libresoc.v:150282$7598_Y - connect \$110 $and$libresoc.v:150283$7599_Y - connect \$112 $and$libresoc.v:150284$7600_Y - connect \$114 $and$libresoc.v:150285$7601_Y - connect \$116 $and$libresoc.v:150286$7602_Y - connect \$118 $and$libresoc.v:150287$7603_Y - connect \$120 $and$libresoc.v:150288$7604_Y - connect \$12 $not$libresoc.v:150289$7605_Y - connect \$14 $and$libresoc.v:150290$7606_Y - connect \$16 $not$libresoc.v:150291$7607_Y - connect \$18 $and$libresoc.v:150292$7608_Y - connect \$20 $and$libresoc.v:150293$7609_Y - connect \$24 $not$libresoc.v:150294$7610_Y - connect \$26 $and$libresoc.v:150295$7611_Y - connect \$23 $reduce_or$libresoc.v:150296$7612_Y - connect \$22 $not$libresoc.v:150297$7613_Y - connect \$2 $and$libresoc.v:150298$7614_Y - connect \$30 $and$libresoc.v:150299$7615_Y - connect \$32 $reduce_or$libresoc.v:150300$7616_Y - connect \$34 $reduce_or$libresoc.v:150301$7617_Y - connect \$36 $or$libresoc.v:150302$7618_Y - connect \$38 $not$libresoc.v:150303$7619_Y - connect \$40 $and$libresoc.v:150304$7620_Y - connect \$42 $and$libresoc.v:150305$7621_Y - connect \$44 $eq$libresoc.v:150306$7622_Y - connect \$46 $and$libresoc.v:150307$7623_Y - connect \$48 $eq$libresoc.v:150308$7624_Y - connect \$50 $and$libresoc.v:150309$7625_Y - connect \$52 $and$libresoc.v:150310$7626_Y - connect \$54 $and$libresoc.v:150311$7627_Y - connect \$56 $or$libresoc.v:150312$7628_Y - connect \$58 $or$libresoc.v:150313$7629_Y - connect \$5 $not$libresoc.v:150314$7630_Y - connect \$60 $or$libresoc.v:150315$7631_Y - connect \$62 $or$libresoc.v:150316$7632_Y - connect \$64 $and$libresoc.v:150317$7633_Y - connect \$66 $and$libresoc.v:150318$7634_Y - connect \$68 $or$libresoc.v:150319$7635_Y - connect \$70 $and$libresoc.v:150320$7636_Y - connect \$72 $and$libresoc.v:150321$7637_Y - connect \$74 $and$libresoc.v:150322$7638_Y - connect \$76 $and$libresoc.v:150323$7639_Y - connect \$78 $ternary$libresoc.v:150324$7640_Y - connect \$7 $or$libresoc.v:150325$7641_Y - connect \$80 $ternary$libresoc.v:150326$7642_Y - connect \$82 $ternary$libresoc.v:150327$7643_Y - connect \$84 $ternary$libresoc.v:150328$7644_Y - connect \$86 $ternary$libresoc.v:150329$7645_Y - connect \$88 $and$libresoc.v:150330$7646_Y - connect \$4 $reduce_and$libresoc.v:150331$7647_Y - connect \$90 $and$libresoc.v:150332$7648_Y - connect \$92 $and$libresoc.v:150333$7649_Y - connect \$94 $not$libresoc.v:150334$7650_Y - connect \$96 $and$libresoc.v:150335$7651_Y - connect \$98 $not$libresoc.v:150336$7652_Y + assign $1\prev_wr_go$next[3:0]$7854 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7854 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7853 + end + connect \$100 $and$libresoc.v:151909$7641_Y + connect \$102 $and$libresoc.v:151910$7642_Y + connect \$104 $and$libresoc.v:151911$7643_Y + connect \$106 $and$libresoc.v:151912$7644_Y + connect \$108 $and$libresoc.v:151913$7645_Y + connect \$10 $and$libresoc.v:151914$7646_Y + connect \$110 $and$libresoc.v:151915$7647_Y + connect \$112 $and$libresoc.v:151916$7648_Y + connect \$114 $and$libresoc.v:151917$7649_Y + connect \$116 $and$libresoc.v:151918$7650_Y + connect \$118 $and$libresoc.v:151919$7651_Y + connect \$120 $and$libresoc.v:151920$7652_Y + connect \$12 $not$libresoc.v:151921$7653_Y + connect \$14 $and$libresoc.v:151922$7654_Y + connect \$16 $not$libresoc.v:151923$7655_Y + connect \$18 $and$libresoc.v:151924$7656_Y + connect \$20 $and$libresoc.v:151925$7657_Y + connect \$24 $not$libresoc.v:151926$7658_Y + connect \$26 $and$libresoc.v:151927$7659_Y + connect \$23 $reduce_or$libresoc.v:151928$7660_Y + connect \$22 $not$libresoc.v:151929$7661_Y + connect \$2 $and$libresoc.v:151930$7662_Y + connect \$30 $and$libresoc.v:151931$7663_Y + connect \$32 $reduce_or$libresoc.v:151932$7664_Y + connect \$34 $reduce_or$libresoc.v:151933$7665_Y + connect \$36 $or$libresoc.v:151934$7666_Y + connect \$38 $not$libresoc.v:151935$7667_Y + connect \$40 $and$libresoc.v:151936$7668_Y + connect \$42 $and$libresoc.v:151937$7669_Y + connect \$44 $eq$libresoc.v:151938$7670_Y + connect \$46 $and$libresoc.v:151939$7671_Y + connect \$48 $eq$libresoc.v:151940$7672_Y + connect \$50 $and$libresoc.v:151941$7673_Y + connect \$52 $and$libresoc.v:151942$7674_Y + connect \$54 $and$libresoc.v:151943$7675_Y + connect \$56 $or$libresoc.v:151944$7676_Y + connect \$58 $or$libresoc.v:151945$7677_Y + connect \$5 $not$libresoc.v:151946$7678_Y + connect \$60 $or$libresoc.v:151947$7679_Y + connect \$62 $or$libresoc.v:151948$7680_Y + connect \$64 $and$libresoc.v:151949$7681_Y + connect \$66 $and$libresoc.v:151950$7682_Y + connect \$68 $or$libresoc.v:151951$7683_Y + connect \$70 $and$libresoc.v:151952$7684_Y + connect \$72 $and$libresoc.v:151953$7685_Y + connect \$74 $and$libresoc.v:151954$7686_Y + connect \$76 $and$libresoc.v:151955$7687_Y + connect \$78 $ternary$libresoc.v:151956$7688_Y + connect \$7 $or$libresoc.v:151957$7689_Y + connect \$80 $ternary$libresoc.v:151958$7690_Y + connect \$82 $ternary$libresoc.v:151959$7691_Y + connect \$84 $ternary$libresoc.v:151960$7692_Y + connect \$86 $ternary$libresoc.v:151961$7693_Y + connect \$88 $and$libresoc.v:151962$7694_Y + connect \$4 $reduce_and$libresoc.v:151963$7695_Y + connect \$90 $and$libresoc.v:151964$7696_Y + connect \$92 $and$libresoc.v:151965$7697_Y + connect \$94 $not$libresoc.v:151966$7698_Y + connect \$96 $and$libresoc.v:151967$7699_Y + connect \$98 $not$libresoc.v:151968$7700_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -316791,51 +319288,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:150844.1-151177.10" +attribute \src "libresoc.v:152476.1-152809.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:151144.18-151144.116" - wire $and$libresoc.v:151144$7847_Y - attribute \src "libresoc.v:151146.18-151146.116" - wire $and$libresoc.v:151146$7849_Y - attribute \src "libresoc.v:151147.18-151147.117" - wire $and$libresoc.v:151147$7850_Y - attribute \src "libresoc.v:151148.18-151148.117" - wire $and$libresoc.v:151148$7851_Y - attribute \src "libresoc.v:151151.18-151151.95" - wire width 65 $extend$libresoc.v:151151$7854_Y - attribute \src "libresoc.v:151152.18-151152.91" - wire width 65 $extend$libresoc.v:151152$7856_Y - attribute \src "libresoc.v:151154.18-151154.95" - wire width 65 $extend$libresoc.v:151154$7859_Y - attribute \src "libresoc.v:151155.18-151155.91" - wire width 65 $extend$libresoc.v:151155$7861_Y - attribute \src "libresoc.v:151151.18-151151.95" - wire width 65 $neg$libresoc.v:151151$7855_Y - attribute \src "libresoc.v:151154.18-151154.95" - wire width 65 $neg$libresoc.v:151154$7860_Y - attribute \src "libresoc.v:151152.18-151152.91" - wire width 65 $pos$libresoc.v:151152$7857_Y - attribute \src "libresoc.v:151155.18-151155.91" - wire width 65 $pos$libresoc.v:151155$7862_Y - attribute \src "libresoc.v:151143.18-151143.125" - wire $ternary$libresoc.v:151143$7846_Y - attribute \src "libresoc.v:151145.18-151145.125" - wire $ternary$libresoc.v:151145$7848_Y - attribute \src "libresoc.v:151153.18-151153.112" - wire width 65 $ternary$libresoc.v:151153$7858_Y - attribute \src "libresoc.v:151156.18-151156.112" - wire width 65 $ternary$libresoc.v:151156$7863_Y - attribute \src "libresoc.v:151157.18-151157.116" - wire width 32 $ternary$libresoc.v:151157$7864_Y - attribute \src "libresoc.v:151158.18-151158.116" - wire width 32 $ternary$libresoc.v:151158$7865_Y - attribute \src "libresoc.v:151149.18-151149.106" - wire $xor$libresoc.v:151149$7852_Y - attribute \src "libresoc.v:151150.18-151150.110" - wire $xor$libresoc.v:151150$7853_Y + attribute \src "libresoc.v:152776.18-152776.116" + wire $and$libresoc.v:152776$7895_Y + attribute \src "libresoc.v:152778.18-152778.116" + wire $and$libresoc.v:152778$7897_Y + attribute \src "libresoc.v:152779.18-152779.117" + wire $and$libresoc.v:152779$7898_Y + attribute \src "libresoc.v:152780.18-152780.117" + wire $and$libresoc.v:152780$7899_Y + attribute \src "libresoc.v:152783.18-152783.95" + wire width 65 $extend$libresoc.v:152783$7902_Y + attribute \src "libresoc.v:152784.18-152784.91" + wire width 65 $extend$libresoc.v:152784$7904_Y + attribute \src "libresoc.v:152786.18-152786.95" + wire width 65 $extend$libresoc.v:152786$7907_Y + attribute \src "libresoc.v:152787.18-152787.91" + wire width 65 $extend$libresoc.v:152787$7909_Y + attribute \src "libresoc.v:152783.18-152783.95" + wire width 65 $neg$libresoc.v:152783$7903_Y + attribute \src "libresoc.v:152786.18-152786.95" + wire width 65 $neg$libresoc.v:152786$7908_Y + attribute \src "libresoc.v:152784.18-152784.91" + wire width 65 $pos$libresoc.v:152784$7905_Y + attribute \src "libresoc.v:152787.18-152787.91" + wire width 65 $pos$libresoc.v:152787$7910_Y + attribute \src "libresoc.v:152775.18-152775.125" + wire $ternary$libresoc.v:152775$7894_Y + attribute \src "libresoc.v:152777.18-152777.125" + wire $ternary$libresoc.v:152777$7896_Y + attribute \src "libresoc.v:152785.18-152785.112" + wire width 65 $ternary$libresoc.v:152785$7906_Y + attribute \src "libresoc.v:152788.18-152788.112" + wire width 65 $ternary$libresoc.v:152788$7911_Y + attribute \src "libresoc.v:152789.18-152789.116" + wire width 32 $ternary$libresoc.v:152789$7912_Y + attribute \src "libresoc.v:152790.18-152790.116" + wire width 32 $ternary$libresoc.v:152790$7913_Y + attribute \src "libresoc.v:152781.18-152781.106" + wire $xor$libresoc.v:152781$7900_Y + attribute \src "libresoc.v:152782.18-152782.110" + wire $xor$libresoc.v:152782$7901_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -317135,7 +319632,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:151144$7847 + cell $and $and$libresoc.v:152776$7895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317143,10 +319640,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151144$7847_Y + connect \Y $and$libresoc.v:152776$7895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:151146$7849 + cell $and $and$libresoc.v:152778$7897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317154,10 +319651,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151146$7849_Y + connect \Y $and$libresoc.v:152778$7897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:151147$7850 + cell $and $and$libresoc.v:152779$7898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317165,10 +319662,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151147$7850_Y + connect \Y $and$libresoc.v:152779$7898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:151148$7851 + cell $and $and$libresoc.v:152780$7899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317176,122 +319673,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:151148$7851_Y + connect \Y $and$libresoc.v:152780$7899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:151151$7854 + cell $pos $extend$libresoc.v:152783$7902 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:151151$7854_Y + connect \Y $extend$libresoc.v:152783$7902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151152$7856 + cell $pos $extend$libresoc.v:152784$7904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:151152$7856_Y + connect \Y $extend$libresoc.v:152784$7904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:151154$7859 + cell $pos $extend$libresoc.v:152786$7907 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:151154$7859_Y + connect \Y $extend$libresoc.v:152786$7907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151155$7861 + cell $pos $extend$libresoc.v:152787$7909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:151155$7861_Y + connect \Y $extend$libresoc.v:152787$7909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:151151$7855 + cell $neg $neg$libresoc.v:152783$7903 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151151$7854_Y - connect \Y $neg$libresoc.v:151151$7855_Y + connect \A $extend$libresoc.v:152783$7902_Y + connect \Y $neg$libresoc.v:152783$7903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:151154$7860 + cell $neg $neg$libresoc.v:152786$7908 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151154$7859_Y - connect \Y $neg$libresoc.v:151154$7860_Y + connect \A $extend$libresoc.v:152786$7907_Y + connect \Y $neg$libresoc.v:152786$7908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151152$7857 + cell $pos $pos$libresoc.v:152784$7905 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151152$7856_Y - connect \Y $pos$libresoc.v:151152$7857_Y + connect \A $extend$libresoc.v:152784$7904_Y + connect \Y $pos$libresoc.v:152784$7905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151155$7862 + cell $pos $pos$libresoc.v:152787$7910 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151155$7861_Y - connect \Y $pos$libresoc.v:151155$7862_Y + connect \A $extend$libresoc.v:152787$7909_Y + connect \Y $pos$libresoc.v:152787$7910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:151143$7846 + cell $mux $ternary$libresoc.v:152775$7894 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:151143$7846_Y + connect \Y $ternary$libresoc.v:152775$7894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:151145$7848 + cell $mux $ternary$libresoc.v:152777$7896 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:151145$7848_Y + connect \Y $ternary$libresoc.v:152777$7896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:151153$7858 + cell $mux $ternary$libresoc.v:152785$7906 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:151153$7858_Y + connect \Y $ternary$libresoc.v:152785$7906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:151156$7863 + cell $mux $ternary$libresoc.v:152788$7911 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:151156$7863_Y + connect \Y $ternary$libresoc.v:152788$7911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:151157$7864 + cell $mux $ternary$libresoc.v:152789$7912 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:151157$7864_Y + connect \Y $ternary$libresoc.v:152789$7912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:151158$7865 + cell $mux $ternary$libresoc.v:152790$7913 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:151158$7865_Y + connect \Y $ternary$libresoc.v:152790$7913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:151149$7852 + cell $xor $xor$libresoc.v:152781$7900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317299,10 +319796,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:151149$7852_Y + connect \Y $xor$libresoc.v:152781$7900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:151150$7853 + cell $xor $xor$libresoc.v:152782$7901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317310,24 +319807,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:151150$7853_Y - end - connect \$17 $ternary$libresoc.v:151143$7846_Y - connect \$19 $and$libresoc.v:151144$7847_Y - connect \$21 $ternary$libresoc.v:151145$7848_Y - connect \$23 $and$libresoc.v:151146$7849_Y - connect \$25 $and$libresoc.v:151147$7850_Y - connect \$27 $and$libresoc.v:151148$7851_Y - connect \$29 $xor$libresoc.v:151149$7852_Y - connect \$31 $xor$libresoc.v:151150$7853_Y - connect \$34 $neg$libresoc.v:151151$7855_Y - connect \$36 $pos$libresoc.v:151152$7857_Y - connect \$38 $ternary$libresoc.v:151153$7858_Y - connect \$41 $neg$libresoc.v:151154$7860_Y - connect \$43 $pos$libresoc.v:151155$7862_Y - connect \$45 $ternary$libresoc.v:151156$7863_Y - connect \$47 $ternary$libresoc.v:151157$7864_Y - connect \$49 $ternary$libresoc.v:151158$7865_Y + connect \Y $xor$libresoc.v:152782$7901_Y + end + connect \$17 $ternary$libresoc.v:152775$7894_Y + connect \$19 $and$libresoc.v:152776$7895_Y + connect \$21 $ternary$libresoc.v:152777$7896_Y + connect \$23 $and$libresoc.v:152778$7897_Y + connect \$25 $and$libresoc.v:152779$7898_Y + connect \$27 $and$libresoc.v:152780$7899_Y + connect \$29 $xor$libresoc.v:152781$7900_Y + connect \$31 $xor$libresoc.v:152782$7901_Y + connect \$34 $neg$libresoc.v:152783$7903_Y + connect \$36 $pos$libresoc.v:152784$7905_Y + connect \$38 $ternary$libresoc.v:152785$7906_Y + connect \$41 $neg$libresoc.v:152786$7908_Y + connect \$43 $pos$libresoc.v:152787$7910_Y + connect \$45 $ternary$libresoc.v:152788$7911_Y + connect \$47 $ternary$libresoc.v:152789$7912_Y + connect \$49 $ternary$libresoc.v:152790$7913_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -317347,17 +319844,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:151181.1-151444.10" +attribute \src "libresoc.v:152813.1-153076.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:151437.18-151437.98" - wire width 129 $extend$libresoc.v:151437$7867_Y - attribute \src "libresoc.v:151436.18-151436.99" - wire width 128 $mul$libresoc.v:151436$7866_Y - attribute \src "libresoc.v:151437.18-151437.98" - wire width 129 $pos$libresoc.v:151437$7868_Y + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $extend$libresoc.v:153069$7915_Y + attribute \src "libresoc.v:153068.18-153068.99" + wire width 128 $mul$libresoc.v:153068$7914_Y + attribute \src "libresoc.v:153069.18-153069.98" + wire width 129 $pos$libresoc.v:153069$7916_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -317613,15 +320110,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:151437$7867 + cell $pos $extend$libresoc.v:153069$7915 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:151437$7867_Y + connect \Y $extend$libresoc.v:153069$7915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:151436$7866 + cell $mul $mul$libresoc.v:153068$7914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -317629,18 +320126,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:151436$7866_Y + connect \Y $mul$libresoc.v:153068$7914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:151437$7868 + cell $pos $pos$libresoc.v:153069$7916 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:151437$7867_Y - connect \Y $pos$libresoc.v:151437$7868_Y + connect \A $extend$libresoc.v:153069$7915_Y + connect \Y $pos$libresoc.v:153069$7916_Y end - connect \$18 $mul$libresoc.v:151436$7866_Y - connect \$17 $pos$libresoc.v:151437$7868_Y + connect \$18 $mul$libresoc.v:153068$7914_Y + connect \$17 $pos$libresoc.v:153069$7916_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -317648,65 +320145,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:151448.1-151833.10" +attribute \src "libresoc.v:153080.1-153465.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:151449.7-151449.20" + attribute \src "libresoc.v:153081.7-153081.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:151748.3-151766.6" - wire width 64 $0\o$14[63:0]$7885 - attribute \src "libresoc.v:151767.3-151785.6" + attribute \src "libresoc.v:153380.3-153398.6" + wire width 64 $0\o$14[63:0]$7933 + attribute \src "libresoc.v:153399.3-153417.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151805.3-151815.6" + attribute \src "libresoc.v:153437.3-153447.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:151816.3-151826.6" + attribute \src "libresoc.v:153448.3-153458.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:151748.3-151766.6" - wire width 64 $1\o$14[63:0]$7886 - attribute \src "libresoc.v:151767.3-151785.6" + attribute \src "libresoc.v:153380.3-153398.6" + wire width 64 $1\o$14[63:0]$7934 + attribute \src "libresoc.v:153399.3-153417.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151805.3-151815.6" + attribute \src "libresoc.v:153437.3-153447.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:151816.3-151826.6" + attribute \src "libresoc.v:153448.3-153458.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:151786.3-151804.6" + attribute \src "libresoc.v:153418.3-153436.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:151742.18-151742.104" - wire $and$libresoc.v:151742$7877_Y - attribute \src "libresoc.v:151746.18-151746.104" - wire $and$libresoc.v:151746$7881_Y - attribute \src "libresoc.v:151736.18-151736.95" - wire width 130 $extend$libresoc.v:151736$7869_Y - attribute \src "libresoc.v:151737.18-151737.90" - wire width 130 $extend$libresoc.v:151737$7871_Y - attribute \src "libresoc.v:151747.18-151747.95" - wire width 2 $extend$libresoc.v:151747$7882_Y - attribute \src "libresoc.v:151736.18-151736.95" - wire width 130 $neg$libresoc.v:151736$7870_Y - attribute \src "libresoc.v:151741.18-151741.98" - wire $not$libresoc.v:151741$7876_Y - attribute \src "libresoc.v:151745.18-151745.98" - wire $not$libresoc.v:151745$7880_Y - attribute \src "libresoc.v:151737.18-151737.90" - wire width 130 $pos$libresoc.v:151737$7872_Y - attribute \src "libresoc.v:151747.18-151747.95" - wire width 2 $pos$libresoc.v:151747$7883_Y - attribute \src "libresoc.v:151740.18-151740.106" - wire $reduce_and$libresoc.v:151740$7875_Y - attribute \src "libresoc.v:151744.18-151744.107" - wire $reduce_and$libresoc.v:151744$7879_Y - attribute \src "libresoc.v:151739.18-151739.106" - wire $reduce_or$libresoc.v:151739$7874_Y - attribute \src "libresoc.v:151743.18-151743.107" - wire $reduce_or$libresoc.v:151743$7878_Y - attribute \src "libresoc.v:151738.18-151738.114" - wire width 130 $ternary$libresoc.v:151738$7873_Y + attribute \src "libresoc.v:153374.18-153374.104" + wire $and$libresoc.v:153374$7925_Y + attribute \src "libresoc.v:153378.18-153378.104" + wire $and$libresoc.v:153378$7929_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $extend$libresoc.v:153368$7917_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $extend$libresoc.v:153369$7919_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $extend$libresoc.v:153379$7930_Y + attribute \src "libresoc.v:153368.18-153368.95" + wire width 130 $neg$libresoc.v:153368$7918_Y + attribute \src "libresoc.v:153373.18-153373.98" + wire $not$libresoc.v:153373$7924_Y + attribute \src "libresoc.v:153377.18-153377.98" + wire $not$libresoc.v:153377$7928_Y + attribute \src "libresoc.v:153369.18-153369.90" + wire width 130 $pos$libresoc.v:153369$7920_Y + attribute \src "libresoc.v:153379.18-153379.95" + wire width 2 $pos$libresoc.v:153379$7931_Y + attribute \src "libresoc.v:153372.18-153372.106" + wire $reduce_and$libresoc.v:153372$7923_Y + attribute \src "libresoc.v:153376.18-153376.107" + wire $reduce_and$libresoc.v:153376$7927_Y + attribute \src "libresoc.v:153371.18-153371.106" + wire $reduce_or$libresoc.v:153371$7922_Y + attribute \src "libresoc.v:153375.18-153375.107" + wire $reduce_or$libresoc.v:153375$7926_Y + attribute \src "libresoc.v:153370.18-153370.114" + wire width 130 $ternary$libresoc.v:153370$7921_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -317733,7 +320230,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:151449.7-151449.15" + attribute \src "libresoc.v:153081.7-153081.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -317992,7 +320489,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:151742$7877 + cell $and $and$libresoc.v:153374$7925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318000,10 +320497,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:151742$7877_Y + connect \Y $and$libresoc.v:153374$7925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:151746$7881 + cell $and $and$libresoc.v:153378$7929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318011,128 +320508,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:151746$7881_Y + connect \Y $and$libresoc.v:153378$7929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:151736$7869 + cell $pos $extend$libresoc.v:153368$7917 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:151736$7869_Y + connect \Y $extend$libresoc.v:153368$7917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151737$7871 + cell $pos $extend$libresoc.v:153369$7919 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:151737$7871_Y + connect \Y $extend$libresoc.v:153369$7919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151747$7882 + cell $pos $extend$libresoc.v:153379$7930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:151747$7882_Y + connect \Y $extend$libresoc.v:153379$7930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:151736$7870 + cell $neg $neg$libresoc.v:153368$7918 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:151736$7869_Y - connect \Y $neg$libresoc.v:151736$7870_Y + connect \A $extend$libresoc.v:153368$7917_Y + connect \Y $neg$libresoc.v:153368$7918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:151741$7876 + cell $not $not$libresoc.v:153373$7924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:151741$7876_Y + connect \Y $not$libresoc.v:153373$7924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:151745$7880 + cell $not $not$libresoc.v:153377$7928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:151745$7880_Y + connect \Y $not$libresoc.v:153377$7928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151737$7872 + cell $pos $pos$libresoc.v:153369$7920 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:151737$7871_Y - connect \Y $pos$libresoc.v:151737$7872_Y + connect \A $extend$libresoc.v:153369$7919_Y + connect \Y $pos$libresoc.v:153369$7920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151747$7883 + cell $pos $pos$libresoc.v:153379$7931 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:151747$7882_Y - connect \Y $pos$libresoc.v:151747$7883_Y + connect \A $extend$libresoc.v:153379$7930_Y + connect \Y $pos$libresoc.v:153379$7931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:151740$7875 + cell $reduce_and $reduce_and$libresoc.v:153372$7923 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:151740$7875_Y + connect \Y $reduce_and$libresoc.v:153372$7923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:151744$7879 + cell $reduce_and $reduce_and$libresoc.v:153376$7927 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:151744$7879_Y + connect \Y $reduce_and$libresoc.v:153376$7927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:151739$7874 + cell $reduce_or $reduce_or$libresoc.v:153371$7922 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:151739$7874_Y + connect \Y $reduce_or$libresoc.v:153371$7922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:151743$7878 + cell $reduce_or $reduce_or$libresoc.v:153375$7926 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:151743$7878_Y + connect \Y $reduce_or$libresoc.v:153375$7926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:151738$7873 + cell $mux $ternary$libresoc.v:153370$7921 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:151738$7873_Y + connect \Y $ternary$libresoc.v:153370$7921_Y end - attribute \src "libresoc.v:151449.7-151449.20" - process $proc$libresoc.v:151449$7891 + attribute \src "libresoc.v:153081.7-153081.20" + process $proc$libresoc.v:153081$7939 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151748.3-151766.6" - process $proc$libresoc.v:151748$7884 + attribute \src "libresoc.v:153380.3-153398.6" + process $proc$libresoc.v:153380$7932 assign { } { } assign { } { } - assign $0\o$14[63:0]$7885 $1\o$14[63:0]$7886 - attribute \src "libresoc.v:151749.5-151749.29" + assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 + attribute \src "libresoc.v:153381.5-153381.29" switch \initial - attribute \src "libresoc.v:151749.9-151749.17" + attribute \src "libresoc.v:153381.9-153381.17" case 1'1 case end @@ -318141,29 +320638,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7886 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7934 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7886 \mul_o [127:64] + assign $1\o$14[63:0]$7934 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7886 \mul_o [63:0] + assign $1\o$14[63:0]$7934 \mul_o [63:0] case - assign $1\o$14[63:0]$7886 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7934 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7885 + update \o$14 $0\o$14[63:0]$7933 end - attribute \src "libresoc.v:151767.3-151785.6" - process $proc$libresoc.v:151767$7887 + attribute \src "libresoc.v:153399.3-153417.6" + process $proc$libresoc.v:153399$7935 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:151768.5-151768.29" + attribute \src "libresoc.v:153400.5-153400.29" switch \initial - attribute \src "libresoc.v:151768.9-151768.17" + attribute \src "libresoc.v:153400.9-153400.17" case 1'1 case end @@ -318187,14 +320684,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:151786.3-151804.6" - process $proc$libresoc.v:151786$7888 + attribute \src "libresoc.v:153418.3-153436.6" + process $proc$libresoc.v:153418$7936 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:151787.5-151787.29" + attribute \src "libresoc.v:153419.5-153419.29" switch \initial - attribute \src "libresoc.v:151787.9-151787.17" + attribute \src "libresoc.v:153419.9-153419.17" case 1'1 case end @@ -318221,14 +320718,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:151805.3-151815.6" - process $proc$libresoc.v:151805$7889 + attribute \src "libresoc.v:153437.3-153447.6" + process $proc$libresoc.v:153437$7937 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:151806.5-151806.29" + attribute \src "libresoc.v:153438.5-153438.29" switch \initial - attribute \src "libresoc.v:151806.9-151806.17" + attribute \src "libresoc.v:153438.9-153438.17" case 1'1 case end @@ -318244,14 +320741,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:151816.3-151826.6" - process $proc$libresoc.v:151816$7890 + attribute \src "libresoc.v:153448.3-153458.6" + process $proc$libresoc.v:153448$7938 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:151817.5-151817.29" + attribute \src "libresoc.v:153449.5-153449.29" switch \initial - attribute \src "libresoc.v:151817.9-151817.17" + attribute \src "libresoc.v:153449.9-153449.17" case 1'1 case end @@ -318267,18 +320764,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:151736$7870_Y - connect \$19 $pos$libresoc.v:151737$7872_Y - connect \$21 $ternary$libresoc.v:151738$7873_Y - connect \$23 $reduce_or$libresoc.v:151739$7874_Y - connect \$26 $reduce_and$libresoc.v:151740$7875_Y - connect \$25 $not$libresoc.v:151741$7876_Y - connect \$29 $and$libresoc.v:151742$7877_Y - connect \$31 $reduce_or$libresoc.v:151743$7878_Y - connect \$34 $reduce_and$libresoc.v:151744$7879_Y - connect \$33 $not$libresoc.v:151745$7880_Y - connect \$37 $and$libresoc.v:151746$7881_Y - connect \$39 $pos$libresoc.v:151747$7883_Y + connect \$17 $neg$libresoc.v:153368$7918_Y + connect \$19 $pos$libresoc.v:153369$7920_Y + connect \$21 $ternary$libresoc.v:153370$7921_Y + connect \$23 $reduce_or$libresoc.v:153371$7922_Y + connect \$26 $reduce_and$libresoc.v:153372$7923_Y + connect \$25 $not$libresoc.v:153373$7924_Y + connect \$29 $and$libresoc.v:153374$7925_Y + connect \$31 $reduce_or$libresoc.v:153375$7926_Y + connect \$34 $reduce_and$libresoc.v:153376$7927_Y + connect \$33 $not$libresoc.v:153377$7928_Y + connect \$37 $and$libresoc.v:153378$7929_Y + connect \$39 $pos$libresoc.v:153379$7931_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -318286,188 +320783,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:151837.1-153054.10" +attribute \src "libresoc.v:153469.1-154686.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:151838.7-151838.20" + attribute \src "libresoc.v:153470.7-153470.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 14 $0\mul_op__fn_unit$next[13:0]$7920 - attribute \src "libresoc.v:152796.3-152797.47" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 + attribute \src "libresoc.v:154428.3-154429.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7921 - attribute \src "libresoc.v:152798.3-152799.61" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 + attribute \src "libresoc.v:154430.3-154431.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7922 - attribute \src "libresoc.v:152800.3-152801.57" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7970 + attribute \src "libresoc.v:154432.3-154433.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 32 $0\mul_op__insn$next[31:0]$7923 - attribute \src "libresoc.v:152816.3-152817.41" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $0\mul_op__insn$next[31:0]$7971 + attribute \src "libresoc.v:154448.3-154449.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7924 - attribute \src "libresoc.v:152794.3-152795.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7972 + attribute \src "libresoc.v:154426.3-154427.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__is_32bit$next[0:0]$7925 - attribute \src "libresoc.v:152812.3-152813.49" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_32bit$next[0:0]$7973 + attribute \src "libresoc.v:154444.3-154445.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__is_signed$next[0:0]$7926 - attribute \src "libresoc.v:152814.3-152815.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__is_signed$next[0:0]$7974 + attribute \src "libresoc.v:154446.3-154447.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__oe__oe$next[0:0]$7927 - attribute \src "libresoc.v:152806.3-152807.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__oe$next[0:0]$7975 + attribute \src "libresoc.v:154438.3-154439.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__oe__ok$next[0:0]$7928 - attribute \src "libresoc.v:152808.3-152809.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__oe__ok$next[0:0]$7976 + attribute \src "libresoc.v:154440.3-154441.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__rc__ok$next[0:0]$7929 - attribute \src "libresoc.v:152804.3-152805.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__ok$next[0:0]$7977 + attribute \src "libresoc.v:154436.3-154437.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__rc__rc$next[0:0]$7930 - attribute \src "libresoc.v:152802.3-152803.45" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__rc__rc$next[0:0]$7978 + attribute \src "libresoc.v:154434.3-154435.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $0\mul_op__write_cr0$next[0:0]$7931 - attribute \src "libresoc.v:152810.3-152811.51" + attribute \src "libresoc.v:154563.3-154598.6" + wire $0\mul_op__write_cr0$next[0:0]$7979 + attribute \src "libresoc.v:154442.3-154443.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152918.3-152930.6" - wire width 2 $0\muxid$next[1:0]$7917 - attribute \src "libresoc.v:152818.3-152819.27" + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $0\muxid$next[1:0]$7965 + attribute \src "libresoc.v:154450.3-154451.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:153006.3-153018.6" - wire $0\neg_res$next[0:0]$7960 - attribute \src "libresoc.v:153019.3-153031.6" - wire $0\neg_res32$next[0:0]$7963 - attribute \src "libresoc.v:152784.3-152785.35" + attribute \src "libresoc.v:154638.3-154650.6" + wire $0\neg_res$next[0:0]$8008 + attribute \src "libresoc.v:154651.3-154663.6" + wire $0\neg_res32$next[0:0]$8011 + attribute \src "libresoc.v:154416.3-154417.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:152786.3-152787.31" + attribute \src "libresoc.v:154418.3-154419.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:152900.3-152917.6" - wire $0\r_busy$next[0:0]$7913 - attribute \src "libresoc.v:152820.3-152821.29" + attribute \src "libresoc.v:154532.3-154549.6" + wire $0\r_busy$next[0:0]$7961 + attribute \src "libresoc.v:154452.3-154453.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:152967.3-152979.6" - wire width 64 $0\ra$next[63:0]$7951 - attribute \src "libresoc.v:152792.3-152793.21" + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $0\ra$next[63:0]$7999 + attribute \src "libresoc.v:154424.3-154425.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:152980.3-152992.6" - wire width 64 $0\rb$next[63:0]$7954 - attribute \src "libresoc.v:152790.3-152791.21" + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $0\rb$next[63:0]$8002 + attribute \src "libresoc.v:154422.3-154423.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:152993.3-153005.6" - wire $0\xer_so$next[0:0]$7957 - attribute \src "libresoc.v:152788.3-152789.29" + attribute \src "libresoc.v:154625.3-154637.6" + wire $0\xer_so$next[0:0]$8005 + attribute \src "libresoc.v:154420.3-154421.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 14 $1\mul_op__fn_unit$next[13:0]$7932 - attribute \src "libresoc.v:152354.14-152354.40" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 + attribute \src "libresoc.v:153986.14-153986.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7933 - attribute \src "libresoc.v:152393.14-152393.59" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 + attribute \src "libresoc.v:154025.14-154025.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7934 - attribute \src "libresoc.v:152402.7-152402.34" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7982 + attribute \src "libresoc.v:154034.7-154034.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 32 $1\mul_op__insn$next[31:0]$7935 - attribute \src "libresoc.v:152411.14-152411.34" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 32 $1\mul_op__insn$next[31:0]$7983 + attribute \src "libresoc.v:154043.14-154043.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7936 - attribute \src "libresoc.v:152495.13-152495.38" + attribute \src "libresoc.v:154563.3-154598.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7984 + attribute \src "libresoc.v:154127.13-154127.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__is_32bit$next[0:0]$7937 - attribute \src "libresoc.v:152654.7-152654.30" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_32bit$next[0:0]$7985 + attribute \src "libresoc.v:154286.7-154286.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__is_signed$next[0:0]$7938 - attribute \src "libresoc.v:152663.7-152663.31" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__is_signed$next[0:0]$7986 + attribute \src "libresoc.v:154295.7-154295.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__oe__oe$next[0:0]$7939 - attribute \src "libresoc.v:152672.7-152672.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__oe$next[0:0]$7987 + attribute \src "libresoc.v:154304.7-154304.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__oe__ok$next[0:0]$7940 - attribute \src "libresoc.v:152681.7-152681.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__oe__ok$next[0:0]$7988 + attribute \src "libresoc.v:154313.7-154313.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__rc__ok$next[0:0]$7941 - attribute \src "libresoc.v:152690.7-152690.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__ok$next[0:0]$7989 + attribute \src "libresoc.v:154322.7-154322.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__rc__rc$next[0:0]$7942 - attribute \src "libresoc.v:152699.7-152699.28" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__rc__rc$next[0:0]$7990 + attribute \src "libresoc.v:154331.7-154331.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire $1\mul_op__write_cr0$next[0:0]$7943 - attribute \src "libresoc.v:152708.7-152708.31" + attribute \src "libresoc.v:154563.3-154598.6" + wire $1\mul_op__write_cr0$next[0:0]$7991 + attribute \src "libresoc.v:154340.7-154340.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152918.3-152930.6" - wire width 2 $1\muxid$next[1:0]$7918 - attribute \src "libresoc.v:152717.13-152717.25" + attribute \src "libresoc.v:154550.3-154562.6" + wire width 2 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154349.13-154349.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:153006.3-153018.6" - wire $1\neg_res$next[0:0]$7961 - attribute \src "libresoc.v:153019.3-153031.6" - wire $1\neg_res32$next[0:0]$7964 - attribute \src "libresoc.v:152739.7-152739.23" + attribute \src "libresoc.v:154638.3-154650.6" + wire $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154651.3-154663.6" + wire $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154371.7-154371.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:152732.7-152732.21" + attribute \src "libresoc.v:154364.7-154364.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:152900.3-152917.6" - wire $1\r_busy$next[0:0]$7914 - attribute \src "libresoc.v:152753.7-152753.20" + attribute \src "libresoc.v:154532.3-154549.6" + wire $1\r_busy$next[0:0]$7962 + attribute \src "libresoc.v:154385.7-154385.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:152967.3-152979.6" - wire width 64 $1\ra$next[63:0]$7952 - attribute \src "libresoc.v:152758.14-152758.39" + attribute \src "libresoc.v:154599.3-154611.6" + wire width 64 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154390.14-154390.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:152980.3-152992.6" - wire width 64 $1\rb$next[63:0]$7955 - attribute \src "libresoc.v:152767.14-152767.39" + attribute \src "libresoc.v:154612.3-154624.6" + wire width 64 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154399.14-154399.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:152993.3-153005.6" - wire $1\xer_so$next[0:0]$7958 - attribute \src "libresoc.v:152776.7-152776.20" + attribute \src "libresoc.v:154625.3-154637.6" + wire $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154408.7-154408.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:152931.3-152966.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7944 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7945 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__oe__oe$next[0:0]$7946 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__oe__ok$next[0:0]$7947 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__rc__ok$next[0:0]$7948 - attribute \src "libresoc.v:152931.3-152966.6" - wire $2\mul_op__rc__rc$next[0:0]$7949 - attribute \src "libresoc.v:152900.3-152917.6" - wire $2\r_busy$next[0:0]$7915 - attribute \src "libresoc.v:152783.18-152783.118" - wire $and$libresoc.v:152783$7892_Y + attribute \src "libresoc.v:154563.3-154598.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7993 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__oe$next[0:0]$7994 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__oe__ok$next[0:0]$7995 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__ok$next[0:0]$7996 + attribute \src "libresoc.v:154563.3-154598.6" + wire $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154532.3-154549.6" + wire $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154415.18-154415.118" + wire $and$libresoc.v:154415$7940_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:151838.7-151838.15" + attribute \src "libresoc.v:153470.7-153470.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -319390,7 +321887,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:152783$7892 + cell $and $and$libresoc.v:154415$7940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319398,10 +321895,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:152783$7892_Y + connect \Y $and$libresoc.v:154415$7940_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152822.14-152855.4" + attribute \src "libresoc.v:154454.14-154487.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -319437,7 +321934,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:152856.8-152891.4" + attribute \src "libresoc.v:154488.8-154523.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -319475,319 +321972,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:152892.10-152895.4" + attribute \src "libresoc.v:154524.10-154527.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:152896.10-152899.4" + attribute \src "libresoc.v:154528.10-154531.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:151838.7-151838.20" - process $proc$libresoc.v:151838$7965 + attribute \src "libresoc.v:153470.7-153470.20" + process $proc$libresoc.v:153470$8013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152354.14-152354.40" - process $proc$libresoc.v:152354$7966 + attribute \src "libresoc.v:153986.14-153986.40" + process $proc$libresoc.v:153986$8014 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152393.14-152393.59" - process $proc$libresoc.v:152393$7967 + attribute \src "libresoc.v:154025.14-154025.59" + process $proc$libresoc.v:154025$8015 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152402.7-152402.34" - process $proc$libresoc.v:152402$7968 + attribute \src "libresoc.v:154034.7-154034.34" + process $proc$libresoc.v:154034$8016 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152411.14-152411.34" - process $proc$libresoc.v:152411$7969 + attribute \src "libresoc.v:154043.14-154043.34" + process $proc$libresoc.v:154043$8017 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:152495.13-152495.38" - process $proc$libresoc.v:152495$7970 + attribute \src "libresoc.v:154127.13-154127.38" + process $proc$libresoc.v:154127$8018 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152654.7-152654.30" - process $proc$libresoc.v:152654$7971 + attribute \src "libresoc.v:154286.7-154286.30" + process $proc$libresoc.v:154286$8019 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152663.7-152663.31" - process $proc$libresoc.v:152663$7972 + attribute \src "libresoc.v:154295.7-154295.31" + process $proc$libresoc.v:154295$8020 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152672.7-152672.28" - process $proc$libresoc.v:152672$7973 + attribute \src "libresoc.v:154304.7-154304.28" + process $proc$libresoc.v:154304$8021 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152681.7-152681.28" - process $proc$libresoc.v:152681$7974 + attribute \src "libresoc.v:154313.7-154313.28" + process $proc$libresoc.v:154313$8022 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152690.7-152690.28" - process $proc$libresoc.v:152690$7975 + attribute \src "libresoc.v:154322.7-154322.28" + process $proc$libresoc.v:154322$8023 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152699.7-152699.28" - process $proc$libresoc.v:152699$7976 + attribute \src "libresoc.v:154331.7-154331.28" + process $proc$libresoc.v:154331$8024 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152708.7-152708.31" - process $proc$libresoc.v:152708$7977 + attribute \src "libresoc.v:154340.7-154340.31" + process $proc$libresoc.v:154340$8025 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152717.13-152717.25" - process $proc$libresoc.v:152717$7978 + attribute \src "libresoc.v:154349.13-154349.25" + process $proc$libresoc.v:154349$8026 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:152732.7-152732.21" - process $proc$libresoc.v:152732$7979 + attribute \src "libresoc.v:154364.7-154364.21" + process $proc$libresoc.v:154364$8027 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:152739.7-152739.23" - process $proc$libresoc.v:152739$7980 + attribute \src "libresoc.v:154371.7-154371.23" + process $proc$libresoc.v:154371$8028 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:152753.7-152753.20" - process $proc$libresoc.v:152753$7981 + attribute \src "libresoc.v:154385.7-154385.20" + process $proc$libresoc.v:154385$8029 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:152758.14-152758.39" - process $proc$libresoc.v:152758$7982 + attribute \src "libresoc.v:154390.14-154390.39" + process $proc$libresoc.v:154390$8030 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:152767.14-152767.39" - process $proc$libresoc.v:152767$7983 + attribute \src "libresoc.v:154399.14-154399.39" + process $proc$libresoc.v:154399$8031 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:152776.7-152776.20" - process $proc$libresoc.v:152776$7984 + attribute \src "libresoc.v:154408.7-154408.20" + process $proc$libresoc.v:154408$8032 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:152784.3-152785.35" - process $proc$libresoc.v:152784$7893 + attribute \src "libresoc.v:154416.3-154417.35" + process $proc$libresoc.v:154416$7941 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:152786.3-152787.31" - process $proc$libresoc.v:152786$7894 + attribute \src "libresoc.v:154418.3-154419.31" + process $proc$libresoc.v:154418$7942 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:152788.3-152789.29" - process $proc$libresoc.v:152788$7895 + attribute \src "libresoc.v:154420.3-154421.29" + process $proc$libresoc.v:154420$7943 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:152790.3-152791.21" - process $proc$libresoc.v:152790$7896 + attribute \src "libresoc.v:154422.3-154423.21" + process $proc$libresoc.v:154422$7944 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:152792.3-152793.21" - process $proc$libresoc.v:152792$7897 + attribute \src "libresoc.v:154424.3-154425.21" + process $proc$libresoc.v:154424$7945 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:152794.3-152795.51" - process $proc$libresoc.v:152794$7898 + attribute \src "libresoc.v:154426.3-154427.51" + process $proc$libresoc.v:154426$7946 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:152796.3-152797.47" - process $proc$libresoc.v:152796$7899 + attribute \src "libresoc.v:154428.3-154429.47" + process $proc$libresoc.v:154428$7947 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:152798.3-152799.61" - process $proc$libresoc.v:152798$7900 + attribute \src "libresoc.v:154430.3-154431.61" + process $proc$libresoc.v:154430$7948 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152800.3-152801.57" - process $proc$libresoc.v:152800$7901 + attribute \src "libresoc.v:154432.3-154433.57" + process $proc$libresoc.v:154432$7949 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152802.3-152803.45" - process $proc$libresoc.v:152802$7902 + attribute \src "libresoc.v:154434.3-154435.45" + process $proc$libresoc.v:154434$7950 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152804.3-152805.45" - process $proc$libresoc.v:152804$7903 + attribute \src "libresoc.v:154436.3-154437.45" + process $proc$libresoc.v:154436$7951 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152806.3-152807.45" - process $proc$libresoc.v:152806$7904 + attribute \src "libresoc.v:154438.3-154439.45" + process $proc$libresoc.v:154438$7952 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152808.3-152809.45" - process $proc$libresoc.v:152808$7905 + attribute \src "libresoc.v:154440.3-154441.45" + process $proc$libresoc.v:154440$7953 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152810.3-152811.51" - process $proc$libresoc.v:152810$7906 + attribute \src "libresoc.v:154442.3-154443.51" + process $proc$libresoc.v:154442$7954 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152812.3-152813.49" - process $proc$libresoc.v:152812$7907 + attribute \src "libresoc.v:154444.3-154445.49" + process $proc$libresoc.v:154444$7955 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152814.3-152815.51" - process $proc$libresoc.v:152814$7908 + attribute \src "libresoc.v:154446.3-154447.51" + process $proc$libresoc.v:154446$7956 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152816.3-152817.41" - process $proc$libresoc.v:152816$7909 + attribute \src "libresoc.v:154448.3-154449.41" + process $proc$libresoc.v:154448$7957 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:152818.3-152819.27" - process $proc$libresoc.v:152818$7910 + attribute \src "libresoc.v:154450.3-154451.27" + process $proc$libresoc.v:154450$7958 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:152820.3-152821.29" - process $proc$libresoc.v:152820$7911 + attribute \src "libresoc.v:154452.3-154453.29" + process $proc$libresoc.v:154452$7959 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:152900.3-152917.6" - process $proc$libresoc.v:152900$7912 + attribute \src "libresoc.v:154532.3-154549.6" + process $proc$libresoc.v:154532$7960 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7913 $2\r_busy$next[0:0]$7915 - attribute \src "libresoc.v:152901.5-152901.29" + assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 + attribute \src "libresoc.v:154533.5-154533.29" switch \initial - attribute \src "libresoc.v:152901.9-152901.17" + attribute \src "libresoc.v:154533.9-154533.17" case 1'1 case end @@ -319796,34 +322293,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7914 1'1 + assign $1\r_busy$next[0:0]$7962 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7914 1'0 + assign $1\r_busy$next[0:0]$7962 1'0 case - assign $1\r_busy$next[0:0]$7914 \r_busy + assign $1\r_busy$next[0:0]$7962 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7915 1'0 + assign $2\r_busy$next[0:0]$7963 1'0 case - assign $2\r_busy$next[0:0]$7915 $1\r_busy$next[0:0]$7914 + assign $2\r_busy$next[0:0]$7963 $1\r_busy$next[0:0]$7962 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7913 + update \r_busy$next $0\r_busy$next[0:0]$7961 end - attribute \src "libresoc.v:152918.3-152930.6" - process $proc$libresoc.v:152918$7916 + attribute \src "libresoc.v:154550.3-154562.6" + process $proc$libresoc.v:154550$7964 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7917 $1\muxid$next[1:0]$7918 - attribute \src "libresoc.v:152919.5-152919.29" + assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 + attribute \src "libresoc.v:154551.5-154551.29" switch \initial - attribute \src "libresoc.v:152919.9-152919.17" + attribute \src "libresoc.v:154551.9-154551.17" case 1'1 case end @@ -319832,19 +322329,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7918 \muxid$52 + assign $1\muxid$next[1:0]$7966 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7918 \muxid$52 + assign $1\muxid$next[1:0]$7966 \muxid$52 case - assign $1\muxid$next[1:0]$7918 \muxid + assign $1\muxid$next[1:0]$7966 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7917 + update \muxid$next $0\muxid$next[1:0]$7965 end - attribute \src "libresoc.v:152931.3-152966.6" - process $proc$libresoc.v:152931$7919 + attribute \src "libresoc.v:154563.3-154598.6" + process $proc$libresoc.v:154563$7967 assign { } { } assign { } { } assign { } { } @@ -319869,27 +322366,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[13:0]$7920 $1\mul_op__fn_unit$next[13:0]$7932 + assign $0\mul_op__fn_unit$next[13:0]$7968 $1\mul_op__fn_unit$next[13:0]$7980 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7923 $1\mul_op__insn$next[31:0]$7935 - assign $0\mul_op__insn_type$next[6:0]$7924 $1\mul_op__insn_type$next[6:0]$7936 - assign $0\mul_op__is_32bit$next[0:0]$7925 $1\mul_op__is_32bit$next[0:0]$7937 - assign $0\mul_op__is_signed$next[0:0]$7926 $1\mul_op__is_signed$next[0:0]$7938 + assign $0\mul_op__insn$next[31:0]$7971 $1\mul_op__insn$next[31:0]$7983 + assign $0\mul_op__insn_type$next[6:0]$7972 $1\mul_op__insn_type$next[6:0]$7984 + assign $0\mul_op__is_32bit$next[0:0]$7973 $1\mul_op__is_32bit$next[0:0]$7985 + assign $0\mul_op__is_signed$next[0:0]$7974 $1\mul_op__is_signed$next[0:0]$7986 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7931 $1\mul_op__write_cr0$next[0:0]$7943 - assign $0\mul_op__imm_data__data$next[63:0]$7921 $2\mul_op__imm_data__data$next[63:0]$7944 - assign $0\mul_op__imm_data__ok$next[0:0]$7922 $2\mul_op__imm_data__ok$next[0:0]$7945 - assign $0\mul_op__oe__oe$next[0:0]$7927 $2\mul_op__oe__oe$next[0:0]$7946 - assign $0\mul_op__oe__ok$next[0:0]$7928 $2\mul_op__oe__ok$next[0:0]$7947 - assign $0\mul_op__rc__ok$next[0:0]$7929 $2\mul_op__rc__ok$next[0:0]$7948 - assign $0\mul_op__rc__rc$next[0:0]$7930 $2\mul_op__rc__rc$next[0:0]$7949 - attribute \src "libresoc.v:152932.5-152932.29" + assign $0\mul_op__write_cr0$next[0:0]$7979 $1\mul_op__write_cr0$next[0:0]$7991 + assign $0\mul_op__imm_data__data$next[63:0]$7969 $2\mul_op__imm_data__data$next[63:0]$7992 + assign $0\mul_op__imm_data__ok$next[0:0]$7970 $2\mul_op__imm_data__ok$next[0:0]$7993 + assign $0\mul_op__oe__oe$next[0:0]$7975 $2\mul_op__oe__oe$next[0:0]$7994 + assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 + assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 + assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 + attribute \src "libresoc.v:154564.5-154564.29" switch \initial - attribute \src "libresoc.v:152932.9-152932.17" + attribute \src "libresoc.v:154564.9-154564.17" case 1'1 case end @@ -319909,7 +322406,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -319924,20 +322421,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7935 $1\mul_op__is_signed$next[0:0]$7938 $1\mul_op__is_32bit$next[0:0]$7937 $1\mul_op__write_cr0$next[0:0]$7943 $1\mul_op__oe__ok$next[0:0]$7940 $1\mul_op__oe__oe$next[0:0]$7939 $1\mul_op__rc__ok$next[0:0]$7941 $1\mul_op__rc__rc$next[0:0]$7942 $1\mul_op__imm_data__ok$next[0:0]$7934 $1\mul_op__imm_data__data$next[63:0]$7933 $1\mul_op__fn_unit$next[13:0]$7932 $1\mul_op__insn_type$next[6:0]$7936 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[13:0]$7932 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7933 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7934 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7935 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7936 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7937 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7938 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7939 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7940 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7941 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7942 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7943 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7980 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7981 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7982 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7983 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7984 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7985 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7986 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7987 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7988 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7989 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7990 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7991 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -319949,42 +322446,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7944 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7945 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7949 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7948 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7946 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7947 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7992 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7997 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7996 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7994 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7995 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7944 $1\mul_op__imm_data__data$next[63:0]$7933 - assign $2\mul_op__imm_data__ok$next[0:0]$7945 $1\mul_op__imm_data__ok$next[0:0]$7934 - assign $2\mul_op__oe__oe$next[0:0]$7946 $1\mul_op__oe__oe$next[0:0]$7939 - assign $2\mul_op__oe__ok$next[0:0]$7947 $1\mul_op__oe__ok$next[0:0]$7940 - assign $2\mul_op__rc__ok$next[0:0]$7948 $1\mul_op__rc__ok$next[0:0]$7941 - assign $2\mul_op__rc__rc$next[0:0]$7949 $1\mul_op__rc__rc$next[0:0]$7942 + assign $2\mul_op__imm_data__data$next[63:0]$7992 $1\mul_op__imm_data__data$next[63:0]$7981 + assign $2\mul_op__imm_data__ok$next[0:0]$7993 $1\mul_op__imm_data__ok$next[0:0]$7982 + assign $2\mul_op__oe__oe$next[0:0]$7994 $1\mul_op__oe__oe$next[0:0]$7987 + assign $2\mul_op__oe__ok$next[0:0]$7995 $1\mul_op__oe__ok$next[0:0]$7988 + assign $2\mul_op__rc__ok$next[0:0]$7996 $1\mul_op__rc__ok$next[0:0]$7989 + assign $2\mul_op__rc__rc$next[0:0]$7997 $1\mul_op__rc__rc$next[0:0]$7990 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7920 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7921 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7922 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7923 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7924 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7925 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7926 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7927 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7928 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7929 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7930 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7931 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7968 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7969 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7970 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7971 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7972 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7973 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7974 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7975 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7976 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7977 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 end - attribute \src "libresoc.v:152967.3-152979.6" - process $proc$libresoc.v:152967$7950 + attribute \src "libresoc.v:154599.3-154611.6" + process $proc$libresoc.v:154599$7998 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7951 $1\ra$next[63:0]$7952 - attribute \src "libresoc.v:152968.5-152968.29" + assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 + attribute \src "libresoc.v:154600.5-154600.29" switch \initial - attribute \src "libresoc.v:152968.9-152968.17" + attribute \src "libresoc.v:154600.9-154600.17" case 1'1 case end @@ -319993,25 +322490,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$7952 \ra$65 + assign $1\ra$next[63:0]$8000 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$7952 \ra$65 + assign $1\ra$next[63:0]$8000 \ra$65 case - assign $1\ra$next[63:0]$7952 \ra + assign $1\ra$next[63:0]$8000 \ra end sync always - update \ra$next $0\ra$next[63:0]$7951 + update \ra$next $0\ra$next[63:0]$7999 end - attribute \src "libresoc.v:152980.3-152992.6" - process $proc$libresoc.v:152980$7953 + attribute \src "libresoc.v:154612.3-154624.6" + process $proc$libresoc.v:154612$8001 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7954 $1\rb$next[63:0]$7955 - attribute \src "libresoc.v:152981.5-152981.29" + assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 + attribute \src "libresoc.v:154613.5-154613.29" switch \initial - attribute \src "libresoc.v:152981.9-152981.17" + attribute \src "libresoc.v:154613.9-154613.17" case 1'1 case end @@ -320020,25 +322517,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$7955 \rb$66 + assign $1\rb$next[63:0]$8003 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$7955 \rb$66 + assign $1\rb$next[63:0]$8003 \rb$66 case - assign $1\rb$next[63:0]$7955 \rb + assign $1\rb$next[63:0]$8003 \rb end sync always - update \rb$next $0\rb$next[63:0]$7954 + update \rb$next $0\rb$next[63:0]$8002 end - attribute \src "libresoc.v:152993.3-153005.6" - process $proc$libresoc.v:152993$7956 + attribute \src "libresoc.v:154625.3-154637.6" + process $proc$libresoc.v:154625$8004 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$7957 $1\xer_so$next[0:0]$7958 - attribute \src "libresoc.v:152994.5-152994.29" + assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 + attribute \src "libresoc.v:154626.5-154626.29" switch \initial - attribute \src "libresoc.v:152994.9-152994.17" + attribute \src "libresoc.v:154626.9-154626.17" case 1'1 case end @@ -320047,25 +322544,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$7958 \xer_so$67 + assign $1\xer_so$next[0:0]$8006 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$7958 \xer_so$67 + assign $1\xer_so$next[0:0]$8006 \xer_so$67 case - assign $1\xer_so$next[0:0]$7958 \xer_so + assign $1\xer_so$next[0:0]$8006 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$7957 + update \xer_so$next $0\xer_so$next[0:0]$8005 end - attribute \src "libresoc.v:153006.3-153018.6" - process $proc$libresoc.v:153006$7959 + attribute \src "libresoc.v:154638.3-154650.6" + process $proc$libresoc.v:154638$8007 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$7960 $1\neg_res$next[0:0]$7961 - attribute \src "libresoc.v:153007.5-153007.29" + assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 + attribute \src "libresoc.v:154639.5-154639.29" switch \initial - attribute \src "libresoc.v:153007.9-153007.17" + attribute \src "libresoc.v:154639.9-154639.17" case 1'1 case end @@ -320074,25 +322571,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$7961 \neg_res$68 + assign $1\neg_res$next[0:0]$8009 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$7961 \neg_res$68 + assign $1\neg_res$next[0:0]$8009 \neg_res$68 case - assign $1\neg_res$next[0:0]$7961 \neg_res + assign $1\neg_res$next[0:0]$8009 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$7960 + update \neg_res$next $0\neg_res$next[0:0]$8008 end - attribute \src "libresoc.v:153019.3-153031.6" - process $proc$libresoc.v:153019$7962 + attribute \src "libresoc.v:154651.3-154663.6" + process $proc$libresoc.v:154651$8010 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$7963 $1\neg_res32$next[0:0]$7964 - attribute \src "libresoc.v:153020.5-153020.29" + assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 + attribute \src "libresoc.v:154652.5-154652.29" switch \initial - attribute \src "libresoc.v:153020.9-153020.17" + attribute \src "libresoc.v:154652.9-154652.17" case 1'1 case end @@ -320101,18 +322598,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$7964 \neg_res32$69 + assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$7964 \neg_res32 + assign $1\neg_res32$next[0:0]$8012 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7963 + update \neg_res32$next $0\neg_res32$next[0:0]$8011 end - connect \$50 $and$libresoc.v:152783$7892_Y + connect \$50 $and$libresoc.v:154415$7940_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -320136,180 +322633,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:153058.1-153978.10" +attribute \src "libresoc.v:154690.1-155610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:153059.7-153059.20" + attribute \src "libresoc.v:154691.7-154691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153872.3-153907.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8028 - attribute \src "libresoc.v:153770.3-153771.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$7996 - attribute \src "libresoc.v:153350.14-153350.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8072 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8029 - attribute \src "libresoc.v:153772.3-153773.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7998 - attribute \src "libresoc.v:153376.14-153376.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8074 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8030 - attribute \src "libresoc.v:153774.3-153775.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8000 - attribute \src "libresoc.v:153385.7-153385.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8076 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8031 - attribute \src "libresoc.v:153790.3-153791.49" - wire width 32 $0\mul_op__insn$13[31:0]$8016 - attribute \src "libresoc.v:153392.14-153392.39" - wire width 32 $0\mul_op__insn$13[31:0]$8078 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8032 - attribute \src "libresoc.v:153768.3-153769.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7994 - attribute \src "libresoc.v:153551.13-153551.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8080 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8033 - attribute \src "libresoc.v:153786.3-153787.57" - wire $0\mul_op__is_32bit$11[0:0]$8012 - attribute \src "libresoc.v:153635.7-153635.35" - wire $0\mul_op__is_32bit$11[0:0]$8082 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__is_signed$12$next[0:0]$8034 - attribute \src "libresoc.v:153788.3-153789.59" - wire $0\mul_op__is_signed$12[0:0]$8014 - attribute \src "libresoc.v:153644.7-153644.36" - wire $0\mul_op__is_signed$12[0:0]$8084 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8035 - attribute \src "libresoc.v:153780.3-153781.51" - wire $0\mul_op__oe__oe$8[0:0]$8006 - attribute \src "libresoc.v:153655.7-153655.32" - wire $0\mul_op__oe__oe$8[0:0]$8086 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8036 - attribute \src "libresoc.v:153782.3-153783.51" - wire $0\mul_op__oe__ok$9[0:0]$8008 - attribute \src "libresoc.v:153664.7-153664.32" - wire $0\mul_op__oe__ok$9[0:0]$8088 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8037 - attribute \src "libresoc.v:153778.3-153779.51" - wire $0\mul_op__rc__ok$7[0:0]$8004 - attribute \src "libresoc.v:153673.7-153673.32" - wire $0\mul_op__rc__ok$7[0:0]$8090 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8038 - attribute \src "libresoc.v:153776.3-153777.51" - wire $0\mul_op__rc__rc$6[0:0]$8002 - attribute \src "libresoc.v:153682.7-153682.32" - wire $0\mul_op__rc__rc$6[0:0]$8092 - attribute \src "libresoc.v:153872.3-153907.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8039 - attribute \src "libresoc.v:153784.3-153785.59" - wire $0\mul_op__write_cr0$10[0:0]$8010 - attribute \src "libresoc.v:153689.7-153689.36" - wire $0\mul_op__write_cr0$10[0:0]$8094 - attribute \src "libresoc.v:153859.3-153871.6" - wire width 2 $0\muxid$1$next[1:0]$8025 - attribute \src "libresoc.v:153792.3-153793.33" - wire width 2 $0\muxid$1[1:0]$8018 - attribute \src "libresoc.v:153698.13-153698.29" - wire width 2 $0\muxid$1[1:0]$8096 - attribute \src "libresoc.v:153934.3-153946.6" - wire $0\neg_res$15$next[0:0]$8065 - attribute \src "libresoc.v:153762.3-153763.39" - wire $0\neg_res$15[0:0]$7989 - attribute \src "libresoc.v:153713.7-153713.26" - wire $0\neg_res$15[0:0]$8098 - attribute \src "libresoc.v:153947.3-153959.6" - wire $0\neg_res32$16$next[0:0]$8068 - attribute \src "libresoc.v:153760.3-153761.43" - wire $0\neg_res32$16[0:0]$7987 - attribute \src "libresoc.v:153722.7-153722.28" - wire $0\neg_res32$16[0:0]$8100 - attribute \src "libresoc.v:153908.3-153920.6" - wire width 129 $0\o$next[128:0]$8059 - attribute \src "libresoc.v:153766.3-153767.19" + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 + attribute \src "libresoc.v:155402.3-155403.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 + attribute \src "libresoc.v:154982.14-154982.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 + attribute \src "libresoc.v:155404.3-155405.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 + attribute \src "libresoc.v:155008.14-155008.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 + attribute \src "libresoc.v:155406.3-155407.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8048 + attribute \src "libresoc.v:155017.7-155017.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8124 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8079 + attribute \src "libresoc.v:155422.3-155423.49" + wire width 32 $0\mul_op__insn$13[31:0]$8064 + attribute \src "libresoc.v:155024.14-155024.39" + wire width 32 $0\mul_op__insn$13[31:0]$8126 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 + attribute \src "libresoc.v:155400.3-155401.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8042 + attribute \src "libresoc.v:155183.13-155183.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8128 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8081 + attribute \src "libresoc.v:155418.3-155419.57" + wire $0\mul_op__is_32bit$11[0:0]$8060 + attribute \src "libresoc.v:155267.7-155267.35" + wire $0\mul_op__is_32bit$11[0:0]$8130 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__is_signed$12$next[0:0]$8082 + attribute \src "libresoc.v:155420.3-155421.59" + wire $0\mul_op__is_signed$12[0:0]$8062 + attribute \src "libresoc.v:155276.7-155276.36" + wire $0\mul_op__is_signed$12[0:0]$8132 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8083 + attribute \src "libresoc.v:155412.3-155413.51" + wire $0\mul_op__oe__oe$8[0:0]$8054 + attribute \src "libresoc.v:155287.7-155287.32" + wire $0\mul_op__oe__oe$8[0:0]$8134 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8084 + attribute \src "libresoc.v:155414.3-155415.51" + wire $0\mul_op__oe__ok$9[0:0]$8056 + attribute \src "libresoc.v:155296.7-155296.32" + wire $0\mul_op__oe__ok$9[0:0]$8136 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8085 + attribute \src "libresoc.v:155410.3-155411.51" + wire $0\mul_op__rc__ok$7[0:0]$8052 + attribute \src "libresoc.v:155305.7-155305.32" + wire $0\mul_op__rc__ok$7[0:0]$8138 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8086 + attribute \src "libresoc.v:155408.3-155409.51" + wire $0\mul_op__rc__rc$6[0:0]$8050 + attribute \src "libresoc.v:155314.7-155314.32" + wire $0\mul_op__rc__rc$6[0:0]$8140 + attribute \src "libresoc.v:155504.3-155539.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8087 + attribute \src "libresoc.v:155416.3-155417.59" + wire $0\mul_op__write_cr0$10[0:0]$8058 + attribute \src "libresoc.v:155321.7-155321.36" + wire $0\mul_op__write_cr0$10[0:0]$8142 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $0\muxid$1$next[1:0]$8073 + attribute \src "libresoc.v:155424.3-155425.33" + wire width 2 $0\muxid$1[1:0]$8066 + attribute \src "libresoc.v:155330.13-155330.29" + wire width 2 $0\muxid$1[1:0]$8144 + attribute \src "libresoc.v:155566.3-155578.6" + wire $0\neg_res$15$next[0:0]$8113 + attribute \src "libresoc.v:155394.3-155395.39" + wire $0\neg_res$15[0:0]$8037 + attribute \src "libresoc.v:155345.7-155345.26" + wire $0\neg_res$15[0:0]$8146 + attribute \src "libresoc.v:155579.3-155591.6" + wire $0\neg_res32$16$next[0:0]$8116 + attribute \src "libresoc.v:155392.3-155393.43" + wire $0\neg_res32$16[0:0]$8035 + attribute \src "libresoc.v:155354.7-155354.28" + wire $0\neg_res32$16[0:0]$8148 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $0\o$next[128:0]$8107 + attribute \src "libresoc.v:155398.3-155399.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:153841.3-153858.6" - wire $0\r_busy$next[0:0]$8021 - attribute \src "libresoc.v:153794.3-153795.29" + attribute \src "libresoc.v:155473.3-155490.6" + wire $0\r_busy$next[0:0]$8069 + attribute \src "libresoc.v:155426.3-155427.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:153921.3-153933.6" - wire $0\xer_so$14$next[0:0]$8062 - attribute \src "libresoc.v:153764.3-153765.37" - wire $0\xer_so$14[0:0]$7991 - attribute \src "libresoc.v:153754.7-153754.25" - wire $0\xer_so$14[0:0]$8104 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8040 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8041 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8042 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8043 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8044 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8045 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__is_signed$12$next[0:0]$8046 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8047 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8048 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8049 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8050 - attribute \src "libresoc.v:153872.3-153907.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8051 - attribute \src "libresoc.v:153859.3-153871.6" - wire width 2 $1\muxid$1$next[1:0]$8026 - attribute \src "libresoc.v:153934.3-153946.6" - wire $1\neg_res$15$next[0:0]$8066 - attribute \src "libresoc.v:153947.3-153959.6" - wire $1\neg_res32$16$next[0:0]$8069 - attribute \src "libresoc.v:153908.3-153920.6" - wire width 129 $1\o$next[128:0]$8060 - attribute \src "libresoc.v:153729.15-153729.57" + attribute \src "libresoc.v:155553.3-155565.6" + wire $0\xer_so$14$next[0:0]$8110 + attribute \src "libresoc.v:155396.3-155397.37" + wire $0\xer_so$14[0:0]$8039 + attribute \src "libresoc.v:155386.7-155386.25" + wire $0\xer_so$14[0:0]$8152 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8091 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8093 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__is_signed$12$next[0:0]$8094 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8095 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8096 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8097 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8098 + attribute \src "libresoc.v:155504.3-155539.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8099 + attribute \src "libresoc.v:155491.3-155503.6" + wire width 2 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155566.3-155578.6" + wire $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155579.3-155591.6" + wire $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155540.3-155552.6" + wire width 129 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155361.15-155361.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:153841.3-153858.6" - wire $1\r_busy$next[0:0]$8022 - attribute \src "libresoc.v:153743.7-153743.20" + attribute \src "libresoc.v:155473.3-155490.6" + wire $1\r_busy$next[0:0]$8070 + attribute \src "libresoc.v:155375.7-155375.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:153921.3-153933.6" - wire $1\xer_so$14$next[0:0]$8063 - attribute \src "libresoc.v:153872.3-153907.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8052 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8053 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8054 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8055 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8056 - attribute \src "libresoc.v:153872.3-153907.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8057 - attribute \src "libresoc.v:153841.3-153858.6" - wire $2\r_busy$next[0:0]$8023 - attribute \src "libresoc.v:153759.18-153759.118" - wire $and$libresoc.v:153759$7985_Y + attribute \src "libresoc.v:155553.3-155565.6" + wire $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155504.3-155539.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8102 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8103 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8104 + attribute \src "libresoc.v:155504.3-155539.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155473.3-155490.6" + wire $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155391.18-155391.118" + wire $and$libresoc.v:155391$8033_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:153059.7-153059.15" + attribute \src "libresoc.v:154691.7-154691.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -320988,7 +323485,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:153759$7985 + cell $and $and$libresoc.v:155391$8033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320996,10 +323493,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:153759$7985_Y + connect \Y $and$libresoc.v:155391$8033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:153796.8-153832.4" + attribute \src "libresoc.v:155428.8-155464.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -321038,304 +323535,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:153833.10-153836.4" + attribute \src "libresoc.v:155465.10-155468.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:153837.10-153840.4" + attribute \src "libresoc.v:155469.10-155472.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153059.7-153059.20" - process $proc$libresoc.v:153059$8070 + attribute \src "libresoc.v:154691.7-154691.20" + process $proc$libresoc.v:154691$8118 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153350.14-153350.44" - process $proc$libresoc.v:153350$8071 + attribute \src "libresoc.v:154982.14-154982.44" + process $proc$libresoc.v:154982$8119 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8072 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8072 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 end - attribute \src "libresoc.v:153376.14-153376.63" - process $proc$libresoc.v:153376$8073 + attribute \src "libresoc.v:155008.14-155008.63" + process $proc$libresoc.v:155008$8121 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8074 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8074 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 end - attribute \src "libresoc.v:153385.7-153385.38" - process $proc$libresoc.v:153385$8075 + attribute \src "libresoc.v:155017.7-155017.38" + process $proc$libresoc.v:155017$8123 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8076 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8076 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 end - attribute \src "libresoc.v:153392.14-153392.39" - process $proc$libresoc.v:153392$8077 + attribute \src "libresoc.v:155024.14-155024.39" + process $proc$libresoc.v:155024$8125 assign { } { } - assign $0\mul_op__insn$13[31:0]$8078 0 + assign $0\mul_op__insn$13[31:0]$8126 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8078 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 end - attribute \src "libresoc.v:153551.13-153551.42" - process $proc$libresoc.v:153551$8079 + attribute \src "libresoc.v:155183.13-155183.42" + process $proc$libresoc.v:155183$8127 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8080 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8080 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 end - attribute \src "libresoc.v:153635.7-153635.35" - process $proc$libresoc.v:153635$8081 + attribute \src "libresoc.v:155267.7-155267.35" + process $proc$libresoc.v:155267$8129 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8082 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8082 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 end - attribute \src "libresoc.v:153644.7-153644.36" - process $proc$libresoc.v:153644$8083 + attribute \src "libresoc.v:155276.7-155276.36" + process $proc$libresoc.v:155276$8131 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8084 1'0 + assign $0\mul_op__is_signed$12[0:0]$8132 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8084 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 end - attribute \src "libresoc.v:153655.7-153655.32" - process $proc$libresoc.v:153655$8085 + attribute \src "libresoc.v:155287.7-155287.32" + process $proc$libresoc.v:155287$8133 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8086 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8086 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 end - attribute \src "libresoc.v:153664.7-153664.32" - process $proc$libresoc.v:153664$8087 + attribute \src "libresoc.v:155296.7-155296.32" + process $proc$libresoc.v:155296$8135 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8088 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8088 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 end - attribute \src "libresoc.v:153673.7-153673.32" - process $proc$libresoc.v:153673$8089 + attribute \src "libresoc.v:155305.7-155305.32" + process $proc$libresoc.v:155305$8137 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8090 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8090 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 end - attribute \src "libresoc.v:153682.7-153682.32" - process $proc$libresoc.v:153682$8091 + attribute \src "libresoc.v:155314.7-155314.32" + process $proc$libresoc.v:155314$8139 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8092 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8092 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 end - attribute \src "libresoc.v:153689.7-153689.36" - process $proc$libresoc.v:153689$8093 + attribute \src "libresoc.v:155321.7-155321.36" + process $proc$libresoc.v:155321$8141 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8094 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8094 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 end - attribute \src "libresoc.v:153698.13-153698.29" - process $proc$libresoc.v:153698$8095 + attribute \src "libresoc.v:155330.13-155330.29" + process $proc$libresoc.v:155330$8143 assign { } { } - assign $0\muxid$1[1:0]$8096 2'00 + assign $0\muxid$1[1:0]$8144 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8096 + update \muxid$1 $0\muxid$1[1:0]$8144 end - attribute \src "libresoc.v:153713.7-153713.26" - process $proc$libresoc.v:153713$8097 + attribute \src "libresoc.v:155345.7-155345.26" + process $proc$libresoc.v:155345$8145 assign { } { } - assign $0\neg_res$15[0:0]$8098 1'0 + assign $0\neg_res$15[0:0]$8146 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$8098 + update \neg_res$15 $0\neg_res$15[0:0]$8146 end - attribute \src "libresoc.v:153722.7-153722.28" - process $proc$libresoc.v:153722$8099 + attribute \src "libresoc.v:155354.7-155354.28" + process $proc$libresoc.v:155354$8147 assign { } { } - assign $0\neg_res32$16[0:0]$8100 1'0 + assign $0\neg_res32$16[0:0]$8148 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8100 + update \neg_res32$16 $0\neg_res32$16[0:0]$8148 end - attribute \src "libresoc.v:153729.15-153729.57" - process $proc$libresoc.v:153729$8101 + attribute \src "libresoc.v:155361.15-155361.57" + process $proc$libresoc.v:155361$8149 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:153743.7-153743.20" - process $proc$libresoc.v:153743$8102 + attribute \src "libresoc.v:155375.7-155375.20" + process $proc$libresoc.v:155375$8150 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:153754.7-153754.25" - process $proc$libresoc.v:153754$8103 + attribute \src "libresoc.v:155386.7-155386.25" + process $proc$libresoc.v:155386$8151 assign { } { } - assign $0\xer_so$14[0:0]$8104 1'0 + assign $0\xer_so$14[0:0]$8152 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$8104 + update \xer_so$14 $0\xer_so$14[0:0]$8152 end - attribute \src "libresoc.v:153760.3-153761.43" - process $proc$libresoc.v:153760$7986 + attribute \src "libresoc.v:155392.3-155393.43" + process $proc$libresoc.v:155392$8034 assign { } { } - assign $0\neg_res32$16[0:0]$7987 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7987 + update \neg_res32$16 $0\neg_res32$16[0:0]$8035 end - attribute \src "libresoc.v:153762.3-153763.39" - process $proc$libresoc.v:153762$7988 + attribute \src "libresoc.v:155394.3-155395.39" + process $proc$libresoc.v:155394$8036 assign { } { } - assign $0\neg_res$15[0:0]$7989 \neg_res$15$next + assign $0\neg_res$15[0:0]$8037 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7989 + update \neg_res$15 $0\neg_res$15[0:0]$8037 end - attribute \src "libresoc.v:153764.3-153765.37" - process $proc$libresoc.v:153764$7990 + attribute \src "libresoc.v:155396.3-155397.37" + process $proc$libresoc.v:155396$8038 assign { } { } - assign $0\xer_so$14[0:0]$7991 \xer_so$14$next + assign $0\xer_so$14[0:0]$8039 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7991 + update \xer_so$14 $0\xer_so$14[0:0]$8039 end - attribute \src "libresoc.v:153766.3-153767.19" - process $proc$libresoc.v:153766$7992 + attribute \src "libresoc.v:155398.3-155399.19" + process $proc$libresoc.v:155398$8040 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:153768.3-153769.57" - process $proc$libresoc.v:153768$7993 + attribute \src "libresoc.v:155400.3-155401.57" + process $proc$libresoc.v:155400$8041 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7994 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7994 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 end - attribute \src "libresoc.v:153770.3-153771.53" - process $proc$libresoc.v:153770$7995 + attribute \src "libresoc.v:155402.3-155403.53" + process $proc$libresoc.v:155402$8043 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$7996 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7996 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 end - attribute \src "libresoc.v:153772.3-153773.67" - process $proc$libresoc.v:153772$7997 + attribute \src "libresoc.v:155404.3-155405.67" + process $proc$libresoc.v:155404$8045 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7998 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7998 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 end - attribute \src "libresoc.v:153774.3-153775.63" - process $proc$libresoc.v:153774$7999 + attribute \src "libresoc.v:155406.3-155407.63" + process $proc$libresoc.v:155406$8047 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8000 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8000 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 end - attribute \src "libresoc.v:153776.3-153777.51" - process $proc$libresoc.v:153776$8001 + attribute \src "libresoc.v:155408.3-155409.51" + process $proc$libresoc.v:155408$8049 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8002 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8002 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 end - attribute \src "libresoc.v:153778.3-153779.51" - process $proc$libresoc.v:153778$8003 + attribute \src "libresoc.v:155410.3-155411.51" + process $proc$libresoc.v:155410$8051 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8004 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8004 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 end - attribute \src "libresoc.v:153780.3-153781.51" - process $proc$libresoc.v:153780$8005 + attribute \src "libresoc.v:155412.3-155413.51" + process $proc$libresoc.v:155412$8053 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8006 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8006 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 end - attribute \src "libresoc.v:153782.3-153783.51" - process $proc$libresoc.v:153782$8007 + attribute \src "libresoc.v:155414.3-155415.51" + process $proc$libresoc.v:155414$8055 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8008 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8008 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 end - attribute \src "libresoc.v:153784.3-153785.59" - process $proc$libresoc.v:153784$8009 + attribute \src "libresoc.v:155416.3-155417.59" + process $proc$libresoc.v:155416$8057 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8010 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8010 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 end - attribute \src "libresoc.v:153786.3-153787.57" - process $proc$libresoc.v:153786$8011 + attribute \src "libresoc.v:155418.3-155419.57" + process $proc$libresoc.v:155418$8059 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8012 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8012 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 end - attribute \src "libresoc.v:153788.3-153789.59" - process $proc$libresoc.v:153788$8013 + attribute \src "libresoc.v:155420.3-155421.59" + process $proc$libresoc.v:155420$8061 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8014 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8014 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 end - attribute \src "libresoc.v:153790.3-153791.49" - process $proc$libresoc.v:153790$8015 + attribute \src "libresoc.v:155422.3-155423.49" + process $proc$libresoc.v:155422$8063 assign { } { } - assign $0\mul_op__insn$13[31:0]$8016 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8016 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 end - attribute \src "libresoc.v:153792.3-153793.33" - process $proc$libresoc.v:153792$8017 + attribute \src "libresoc.v:155424.3-155425.33" + process $proc$libresoc.v:155424$8065 assign { } { } - assign $0\muxid$1[1:0]$8018 \muxid$1$next + assign $0\muxid$1[1:0]$8066 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8018 + update \muxid$1 $0\muxid$1[1:0]$8066 end - attribute \src "libresoc.v:153794.3-153795.29" - process $proc$libresoc.v:153794$8019 + attribute \src "libresoc.v:155426.3-155427.29" + process $proc$libresoc.v:155426$8067 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:153841.3-153858.6" - process $proc$libresoc.v:153841$8020 + attribute \src "libresoc.v:155473.3-155490.6" + process $proc$libresoc.v:155473$8068 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8021 $2\r_busy$next[0:0]$8023 - attribute \src "libresoc.v:153842.5-153842.29" + assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 + attribute \src "libresoc.v:155474.5-155474.29" switch \initial - attribute \src "libresoc.v:153842.9-153842.17" + attribute \src "libresoc.v:155474.9-155474.17" case 1'1 case end @@ -321344,34 +323841,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8022 1'1 + assign $1\r_busy$next[0:0]$8070 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8022 1'0 + assign $1\r_busy$next[0:0]$8070 1'0 case - assign $1\r_busy$next[0:0]$8022 \r_busy + assign $1\r_busy$next[0:0]$8070 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8023 1'0 + assign $2\r_busy$next[0:0]$8071 1'0 case - assign $2\r_busy$next[0:0]$8023 $1\r_busy$next[0:0]$8022 + assign $2\r_busy$next[0:0]$8071 $1\r_busy$next[0:0]$8070 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8021 + update \r_busy$next $0\r_busy$next[0:0]$8069 end - attribute \src "libresoc.v:153859.3-153871.6" - process $proc$libresoc.v:153859$8024 + attribute \src "libresoc.v:155491.3-155503.6" + process $proc$libresoc.v:155491$8072 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8025 $1\muxid$1$next[1:0]$8026 - attribute \src "libresoc.v:153860.5-153860.29" + assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 + attribute \src "libresoc.v:155492.5-155492.29" switch \initial - attribute \src "libresoc.v:153860.9-153860.17" + attribute \src "libresoc.v:155492.9-155492.17" case 1'1 case end @@ -321380,19 +323877,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8026 \muxid$36 + assign $1\muxid$1$next[1:0]$8074 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8026 \muxid$36 + assign $1\muxid$1$next[1:0]$8074 \muxid$36 case - assign $1\muxid$1$next[1:0]$8026 \muxid$1 + assign $1\muxid$1$next[1:0]$8074 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8025 + update \muxid$1$next $0\muxid$1$next[1:0]$8073 end - attribute \src "libresoc.v:153872.3-153907.6" - process $proc$libresoc.v:153872$8027 + attribute \src "libresoc.v:155504.3-155539.6" + process $proc$libresoc.v:155504$8075 assign { } { } assign { } { } assign { } { } @@ -321417,27 +323914,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8028 $1\mul_op__fn_unit$3$next[13:0]$8040 + assign $0\mul_op__fn_unit$3$next[13:0]$8076 $1\mul_op__fn_unit$3$next[13:0]$8088 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8031 $1\mul_op__insn$13$next[31:0]$8043 - assign $0\mul_op__insn_type$2$next[6:0]$8032 $1\mul_op__insn_type$2$next[6:0]$8044 - assign $0\mul_op__is_32bit$11$next[0:0]$8033 $1\mul_op__is_32bit$11$next[0:0]$8045 - assign $0\mul_op__is_signed$12$next[0:0]$8034 $1\mul_op__is_signed$12$next[0:0]$8046 + assign $0\mul_op__insn$13$next[31:0]$8079 $1\mul_op__insn$13$next[31:0]$8091 + assign $0\mul_op__insn_type$2$next[6:0]$8080 $1\mul_op__insn_type$2$next[6:0]$8092 + assign $0\mul_op__is_32bit$11$next[0:0]$8081 $1\mul_op__is_32bit$11$next[0:0]$8093 + assign $0\mul_op__is_signed$12$next[0:0]$8082 $1\mul_op__is_signed$12$next[0:0]$8094 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8039 $1\mul_op__write_cr0$10$next[0:0]$8051 - assign $0\mul_op__imm_data__data$4$next[63:0]$8029 $2\mul_op__imm_data__data$4$next[63:0]$8052 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8030 $2\mul_op__imm_data__ok$5$next[0:0]$8053 - assign $0\mul_op__oe__oe$8$next[0:0]$8035 $2\mul_op__oe__oe$8$next[0:0]$8054 - assign $0\mul_op__oe__ok$9$next[0:0]$8036 $2\mul_op__oe__ok$9$next[0:0]$8055 - assign $0\mul_op__rc__ok$7$next[0:0]$8037 $2\mul_op__rc__ok$7$next[0:0]$8056 - assign $0\mul_op__rc__rc$6$next[0:0]$8038 $2\mul_op__rc__rc$6$next[0:0]$8057 - attribute \src "libresoc.v:153873.5-153873.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8087 $1\mul_op__write_cr0$10$next[0:0]$8099 + assign $0\mul_op__imm_data__data$4$next[63:0]$8077 $2\mul_op__imm_data__data$4$next[63:0]$8100 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8078 $2\mul_op__imm_data__ok$5$next[0:0]$8101 + assign $0\mul_op__oe__oe$8$next[0:0]$8083 $2\mul_op__oe__oe$8$next[0:0]$8102 + assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 + assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 + assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 + attribute \src "libresoc.v:155505.5-155505.29" switch \initial - attribute \src "libresoc.v:153873.9-153873.17" + attribute \src "libresoc.v:155505.9-155505.17" case 1'1 case end @@ -321457,7 +323954,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -321472,20 +323969,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8043 $1\mul_op__is_signed$12$next[0:0]$8046 $1\mul_op__is_32bit$11$next[0:0]$8045 $1\mul_op__write_cr0$10$next[0:0]$8051 $1\mul_op__oe__ok$9$next[0:0]$8048 $1\mul_op__oe__oe$8$next[0:0]$8047 $1\mul_op__rc__ok$7$next[0:0]$8049 $1\mul_op__rc__rc$6$next[0:0]$8050 $1\mul_op__imm_data__ok$5$next[0:0]$8042 $1\mul_op__imm_data__data$4$next[63:0]$8041 $1\mul_op__fn_unit$3$next[13:0]$8040 $1\mul_op__insn_type$2$next[6:0]$8044 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8040 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8041 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8042 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8043 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8044 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8045 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8046 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8047 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8048 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8049 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8050 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8051 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8088 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8089 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8090 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8091 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8092 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8093 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8094 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8095 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8096 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8097 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8098 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8099 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -321497,42 +323994,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8052 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8057 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8056 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8054 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8055 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8052 $1\mul_op__imm_data__data$4$next[63:0]$8041 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8053 $1\mul_op__imm_data__ok$5$next[0:0]$8042 - assign $2\mul_op__oe__oe$8$next[0:0]$8054 $1\mul_op__oe__oe$8$next[0:0]$8047 - assign $2\mul_op__oe__ok$9$next[0:0]$8055 $1\mul_op__oe__ok$9$next[0:0]$8048 - assign $2\mul_op__rc__ok$7$next[0:0]$8056 $1\mul_op__rc__ok$7$next[0:0]$8049 - assign $2\mul_op__rc__rc$6$next[0:0]$8057 $1\mul_op__rc__rc$6$next[0:0]$8050 + assign $2\mul_op__imm_data__data$4$next[63:0]$8100 $1\mul_op__imm_data__data$4$next[63:0]$8089 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 $1\mul_op__imm_data__ok$5$next[0:0]$8090 + assign $2\mul_op__oe__oe$8$next[0:0]$8102 $1\mul_op__oe__oe$8$next[0:0]$8095 + assign $2\mul_op__oe__ok$9$next[0:0]$8103 $1\mul_op__oe__ok$9$next[0:0]$8096 + assign $2\mul_op__rc__ok$7$next[0:0]$8104 $1\mul_op__rc__ok$7$next[0:0]$8097 + assign $2\mul_op__rc__rc$6$next[0:0]$8105 $1\mul_op__rc__rc$6$next[0:0]$8098 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8028 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8029 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8030 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8031 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8032 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8033 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8034 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8035 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8036 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8037 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8038 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8039 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8076 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8077 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8078 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8079 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8080 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8081 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8082 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8083 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8084 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8085 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 end - attribute \src "libresoc.v:153908.3-153920.6" - process $proc$libresoc.v:153908$8058 + attribute \src "libresoc.v:155540.3-155552.6" + process $proc$libresoc.v:155540$8106 assign { } { } assign { } { } - assign $0\o$next[128:0]$8059 $1\o$next[128:0]$8060 - attribute \src "libresoc.v:153909.5-153909.29" + assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 + attribute \src "libresoc.v:155541.5-155541.29" switch \initial - attribute \src "libresoc.v:153909.9-153909.17" + attribute \src "libresoc.v:155541.9-155541.17" case 1'1 case end @@ -321541,25 +324038,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$8060 \o$49 + assign $1\o$next[128:0]$8108 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$8060 \o$49 + assign $1\o$next[128:0]$8108 \o$49 case - assign $1\o$next[128:0]$8060 \o + assign $1\o$next[128:0]$8108 \o end sync always - update \o$next $0\o$next[128:0]$8059 + update \o$next $0\o$next[128:0]$8107 end - attribute \src "libresoc.v:153921.3-153933.6" - process $proc$libresoc.v:153921$8061 + attribute \src "libresoc.v:155553.3-155565.6" + process $proc$libresoc.v:155553$8109 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8062 $1\xer_so$14$next[0:0]$8063 - attribute \src "libresoc.v:153922.5-153922.29" + assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 + attribute \src "libresoc.v:155554.5-155554.29" switch \initial - attribute \src "libresoc.v:153922.9-153922.17" + attribute \src "libresoc.v:155554.9-155554.17" case 1'1 case end @@ -321568,25 +324065,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$8063 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$8063 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8111 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8062 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 end - attribute \src "libresoc.v:153934.3-153946.6" - process $proc$libresoc.v:153934$8064 + attribute \src "libresoc.v:155566.3-155578.6" + process $proc$libresoc.v:155566$8112 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8065 $1\neg_res$15$next[0:0]$8066 - attribute \src "libresoc.v:153935.5-153935.29" + assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 + attribute \src "libresoc.v:155567.5-155567.29" switch \initial - attribute \src "libresoc.v:153935.9-153935.17" + attribute \src "libresoc.v:155567.9-155567.17" case 1'1 case end @@ -321595,25 +324092,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$8066 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$8066 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8114 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8065 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 end - attribute \src "libresoc.v:153947.3-153959.6" - process $proc$libresoc.v:153947$8067 + attribute \src "libresoc.v:155579.3-155591.6" + process $proc$libresoc.v:155579$8115 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8068 $1\neg_res32$16$next[0:0]$8069 - attribute \src "libresoc.v:153948.5-153948.29" + assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 + attribute \src "libresoc.v:155580.5-155580.29" switch \initial - attribute \src "libresoc.v:153948.9-153948.17" + attribute \src "libresoc.v:155580.9-155580.17" case 1'1 case end @@ -321622,18 +324119,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$8069 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8068 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 end - connect \$34 $and$libresoc.v:153759$7985_Y + connect \$34 $and$libresoc.v:155391$8033_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -321653,218 +324150,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:153982.1-155278.10" +attribute \src "libresoc.v:155614.1-156910.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:155196.3-155214.6" - wire width 4 $0\cr_a$next[3:0]$8188 - attribute \src "libresoc.v:154988.3-154989.25" + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $0\cr_a$next[3:0]$8236 + attribute \src "libresoc.v:156620.3-156621.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $0\cr_a_ok$next[0:0]$8189 - attribute \src "libresoc.v:154990.3-154991.31" + attribute \src "libresoc.v:156828.3-156846.6" + wire $0\cr_a_ok$next[0:0]$8237 + attribute \src "libresoc.v:156622.3-156623.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:153983.7-153983.20" + attribute \src "libresoc.v:155615.7-155615.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155141.3-155176.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8151 - attribute \src "libresoc.v:154998.3-154999.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8119 - attribute \src "libresoc.v:154294.14-154294.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8209 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8152 - attribute \src "libresoc.v:155000.3-155001.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8121 - attribute \src "libresoc.v:154318.14-154318.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8211 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8153 - attribute \src "libresoc.v:155002.3-155003.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8123 - attribute \src "libresoc.v:154327.7-154327.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8213 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8154 - attribute \src "libresoc.v:155018.3-155019.49" - wire width 32 $0\mul_op__insn$13[31:0]$8139 - attribute \src "libresoc.v:154336.14-154336.39" - wire width 32 $0\mul_op__insn$13[31:0]$8215 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8155 - attribute \src "libresoc.v:154996.3-154997.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8117 - attribute \src "libresoc.v:154495.13-154495.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8217 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8156 - attribute \src "libresoc.v:155014.3-155015.57" - wire $0\mul_op__is_32bit$11[0:0]$8135 - attribute \src "libresoc.v:154579.7-154579.35" - wire $0\mul_op__is_32bit$11[0:0]$8219 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__is_signed$12$next[0:0]$8157 - attribute \src "libresoc.v:155016.3-155017.59" - wire $0\mul_op__is_signed$12[0:0]$8137 - attribute \src "libresoc.v:154588.7-154588.36" - wire $0\mul_op__is_signed$12[0:0]$8221 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8158 - attribute \src "libresoc.v:155008.3-155009.51" - wire $0\mul_op__oe__oe$8[0:0]$8129 - attribute \src "libresoc.v:154599.7-154599.32" - wire $0\mul_op__oe__oe$8[0:0]$8223 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8159 - attribute \src "libresoc.v:155010.3-155011.51" - wire $0\mul_op__oe__ok$9[0:0]$8131 - attribute \src "libresoc.v:154608.7-154608.32" - wire $0\mul_op__oe__ok$9[0:0]$8225 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8160 - attribute \src "libresoc.v:155006.3-155007.51" - wire $0\mul_op__rc__ok$7[0:0]$8127 - attribute \src "libresoc.v:154617.7-154617.32" - wire $0\mul_op__rc__ok$7[0:0]$8227 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8161 - attribute \src "libresoc.v:155004.3-155005.51" - wire $0\mul_op__rc__rc$6[0:0]$8125 - attribute \src "libresoc.v:154624.7-154624.32" - wire $0\mul_op__rc__rc$6[0:0]$8229 - attribute \src "libresoc.v:155141.3-155176.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8162 - attribute \src "libresoc.v:155012.3-155013.59" - wire $0\mul_op__write_cr0$10[0:0]$8133 - attribute \src "libresoc.v:154633.7-154633.36" - wire $0\mul_op__write_cr0$10[0:0]$8231 - attribute \src "libresoc.v:155128.3-155140.6" - wire width 2 $0\muxid$1$next[1:0]$8148 - attribute \src "libresoc.v:155020.3-155021.33" - wire width 2 $0\muxid$1[1:0]$8141 - attribute \src "libresoc.v:154642.13-154642.29" - wire width 2 $0\muxid$1[1:0]$8233 - attribute \src "libresoc.v:155177.3-155195.6" - wire width 64 $0\o$14$next[63:0]$8183 - attribute \src "libresoc.v:154992.3-154993.27" - wire width 64 $0\o$14[63:0]$8114 - attribute \src "libresoc.v:154663.14-154663.43" - wire width 64 $0\o$14[63:0]$8235 - attribute \src "libresoc.v:155177.3-155195.6" - wire $0\o_ok$next[0:0]$8182 - attribute \src "libresoc.v:154994.3-154995.25" + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 + attribute \src "libresoc.v:156630.3-156631.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 + attribute \src "libresoc.v:155926.14-155926.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 + attribute \src "libresoc.v:156632.3-156633.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 + attribute \src "libresoc.v:155950.14-155950.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 + attribute \src "libresoc.v:156634.3-156635.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8171 + attribute \src "libresoc.v:155959.7-155959.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8261 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8202 + attribute \src "libresoc.v:156650.3-156651.49" + wire width 32 $0\mul_op__insn$13[31:0]$8187 + attribute \src "libresoc.v:155968.14-155968.39" + wire width 32 $0\mul_op__insn$13[31:0]$8263 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 + attribute \src "libresoc.v:156628.3-156629.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8165 + attribute \src "libresoc.v:156127.13-156127.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8265 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8204 + attribute \src "libresoc.v:156646.3-156647.57" + wire $0\mul_op__is_32bit$11[0:0]$8183 + attribute \src "libresoc.v:156211.7-156211.35" + wire $0\mul_op__is_32bit$11[0:0]$8267 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__is_signed$12$next[0:0]$8205 + attribute \src "libresoc.v:156648.3-156649.59" + wire $0\mul_op__is_signed$12[0:0]$8185 + attribute \src "libresoc.v:156220.7-156220.36" + wire $0\mul_op__is_signed$12[0:0]$8269 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8206 + attribute \src "libresoc.v:156640.3-156641.51" + wire $0\mul_op__oe__oe$8[0:0]$8177 + attribute \src "libresoc.v:156231.7-156231.32" + wire $0\mul_op__oe__oe$8[0:0]$8271 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8207 + attribute \src "libresoc.v:156642.3-156643.51" + wire $0\mul_op__oe__ok$9[0:0]$8179 + attribute \src "libresoc.v:156240.7-156240.32" + wire $0\mul_op__oe__ok$9[0:0]$8273 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8208 + attribute \src "libresoc.v:156638.3-156639.51" + wire $0\mul_op__rc__ok$7[0:0]$8175 + attribute \src "libresoc.v:156249.7-156249.32" + wire $0\mul_op__rc__ok$7[0:0]$8275 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8209 + attribute \src "libresoc.v:156636.3-156637.51" + wire $0\mul_op__rc__rc$6[0:0]$8173 + attribute \src "libresoc.v:156256.7-156256.32" + wire $0\mul_op__rc__rc$6[0:0]$8277 + attribute \src "libresoc.v:156773.3-156808.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8210 + attribute \src "libresoc.v:156644.3-156645.59" + wire $0\mul_op__write_cr0$10[0:0]$8181 + attribute \src "libresoc.v:156265.7-156265.36" + wire $0\mul_op__write_cr0$10[0:0]$8279 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $0\muxid$1$next[1:0]$8196 + attribute \src "libresoc.v:156652.3-156653.33" + wire width 2 $0\muxid$1[1:0]$8189 + attribute \src "libresoc.v:156274.13-156274.29" + wire width 2 $0\muxid$1[1:0]$8281 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $0\o$14$next[63:0]$8231 + attribute \src "libresoc.v:156624.3-156625.27" + wire width 64 $0\o$14[63:0]$8162 + attribute \src "libresoc.v:156295.14-156295.43" + wire width 64 $0\o$14[63:0]$8283 + attribute \src "libresoc.v:156809.3-156827.6" + wire $0\o_ok$next[0:0]$8230 + attribute \src "libresoc.v:156626.3-156627.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:155110.3-155127.6" - wire $0\r_busy$next[0:0]$8144 - attribute \src "libresoc.v:155022.3-155023.29" + attribute \src "libresoc.v:156742.3-156759.6" + wire $0\r_busy$next[0:0]$8192 + attribute \src "libresoc.v:156654.3-156655.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire width 2 $0\xer_ov$next[1:0]$8194 - attribute \src "libresoc.v:154984.3-154985.29" + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $0\xer_ov$next[1:0]$8242 + attribute \src "libresoc.v:156616.3-156617.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire $0\xer_ov_ok$next[0:0]$8195 - attribute \src "libresoc.v:154986.3-154987.35" + attribute \src "libresoc.v:156847.3-156865.6" + wire $0\xer_ov_ok$next[0:0]$8243 + attribute \src "libresoc.v:156618.3-156619.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:155234.3-155252.6" - wire $0\xer_so$15$next[0:0]$8201 - attribute \src "libresoc.v:154980.3-154981.37" - wire $0\xer_so$15[0:0]$8107 - attribute \src "libresoc.v:154965.7-154965.25" - wire $0\xer_so$15[0:0]$8241 - attribute \src "libresoc.v:155234.3-155252.6" - wire $0\xer_so_ok$next[0:0]$8200 - attribute \src "libresoc.v:154982.3-154983.35" + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so$15$next[0:0]$8249 + attribute \src "libresoc.v:156612.3-156613.37" + wire $0\xer_so$15[0:0]$8155 + attribute \src "libresoc.v:156597.7-156597.25" + wire $0\xer_so$15[0:0]$8289 + attribute \src "libresoc.v:156866.3-156884.6" + wire $0\xer_so_ok$next[0:0]$8248 + attribute \src "libresoc.v:156614.3-156615.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire width 4 $1\cr_a$next[3:0]$8190 - attribute \src "libresoc.v:153992.13-153992.24" + attribute \src "libresoc.v:156828.3-156846.6" + wire width 4 $1\cr_a$next[3:0]$8238 + attribute \src "libresoc.v:155624.13-155624.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $1\cr_a_ok$next[0:0]$8191 - attribute \src "libresoc.v:154001.7-154001.21" + attribute \src "libresoc.v:156828.3-156846.6" + wire $1\cr_a_ok$next[0:0]$8239 + attribute \src "libresoc.v:155633.7-155633.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:155141.3-155176.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8163 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8164 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8165 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8166 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8167 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8168 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__is_signed$12$next[0:0]$8169 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8170 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8171 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8172 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8173 - attribute \src "libresoc.v:155141.3-155176.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8174 - attribute \src "libresoc.v:155128.3-155140.6" - wire width 2 $1\muxid$1$next[1:0]$8149 - attribute \src "libresoc.v:155177.3-155195.6" - wire width 64 $1\o$14$next[63:0]$8185 - attribute \src "libresoc.v:155177.3-155195.6" - wire $1\o_ok$next[0:0]$8184 - attribute \src "libresoc.v:154670.7-154670.18" + attribute \src "libresoc.v:156773.3-156808.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8214 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8216 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__is_signed$12$next[0:0]$8217 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8218 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8219 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8220 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8221 + attribute \src "libresoc.v:156773.3-156808.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8222 + attribute \src "libresoc.v:156760.3-156772.6" + wire width 2 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156809.3-156827.6" + wire width 64 $1\o$14$next[63:0]$8233 + attribute \src "libresoc.v:156809.3-156827.6" + wire $1\o_ok$next[0:0]$8232 + attribute \src "libresoc.v:156302.7-156302.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:155110.3-155127.6" - wire $1\r_busy$next[0:0]$8145 - attribute \src "libresoc.v:154942.7-154942.20" + attribute \src "libresoc.v:156742.3-156759.6" + wire $1\r_busy$next[0:0]$8193 + attribute \src "libresoc.v:156574.7-156574.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire width 2 $1\xer_ov$next[1:0]$8196 - attribute \src "libresoc.v:154947.13-154947.26" + attribute \src "libresoc.v:156847.3-156865.6" + wire width 2 $1\xer_ov$next[1:0]$8244 + attribute \src "libresoc.v:156579.13-156579.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:155215.3-155233.6" - wire $1\xer_ov_ok$next[0:0]$8197 - attribute \src "libresoc.v:154954.7-154954.23" + attribute \src "libresoc.v:156847.3-156865.6" + wire $1\xer_ov_ok$next[0:0]$8245 + attribute \src "libresoc.v:156586.7-156586.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:155234.3-155252.6" - wire $1\xer_so$15$next[0:0]$8203 - attribute \src "libresoc.v:155234.3-155252.6" - wire $1\xer_so_ok$next[0:0]$8202 - attribute \src "libresoc.v:154972.7-154972.23" + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so$15$next[0:0]$8251 + attribute \src "libresoc.v:156866.3-156884.6" + wire $1\xer_so_ok$next[0:0]$8250 + attribute \src "libresoc.v:156604.7-156604.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155196.3-155214.6" - wire $2\cr_a_ok$next[0:0]$8192 - attribute \src "libresoc.v:155141.3-155176.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8175 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8176 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8177 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8178 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8179 - attribute \src "libresoc.v:155141.3-155176.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8180 - attribute \src "libresoc.v:155177.3-155195.6" - wire $2\o_ok$next[0:0]$8186 - attribute \src "libresoc.v:155110.3-155127.6" - wire $2\r_busy$next[0:0]$8146 - attribute \src "libresoc.v:155215.3-155233.6" - wire $2\xer_ov_ok$next[0:0]$8198 - attribute \src "libresoc.v:155234.3-155252.6" - wire $2\xer_so_ok$next[0:0]$8204 - attribute \src "libresoc.v:154979.18-154979.118" - wire $and$libresoc.v:154979$8105_Y + attribute \src "libresoc.v:156828.3-156846.6" + wire $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156773.3-156808.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8225 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8226 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8227 + attribute \src "libresoc.v:156773.3-156808.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156809.3-156827.6" + wire $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156742.3-156759.6" + wire $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156847.3-156865.6" + wire $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156866.3-156884.6" + wire $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156611.18-156611.118" + wire $and$libresoc.v:156611$8153_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a @@ -321884,7 +324381,7 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:153983.7-153983.15" + attribute \src "libresoc.v:155615.7-155615.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -322837,7 +325334,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:154979$8105 + cell $and $and$libresoc.v:156611$8153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322845,10 +325342,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:154979$8105_Y + connect \Y $and$libresoc.v:156611$8153_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155024.8-155060.4" + attribute \src "libresoc.v:156656.8-156692.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -322887,13 +325384,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:155061.10-155064.4" + attribute \src "libresoc.v:156693.10-156696.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155065.16-155105.4" + attribute \src "libresoc.v:156697.16-156737.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -322936,358 +325433,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:155106.10-155109.4" + attribute \src "libresoc.v:156738.10-156741.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153983.7-153983.20" - process $proc$libresoc.v:153983$8205 + attribute \src "libresoc.v:155615.7-155615.20" + process $proc$libresoc.v:155615$8253 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153992.13-153992.24" - process $proc$libresoc.v:153992$8206 + attribute \src "libresoc.v:155624.13-155624.24" + process $proc$libresoc.v:155624$8254 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:154001.7-154001.21" - process $proc$libresoc.v:154001$8207 + attribute \src "libresoc.v:155633.7-155633.21" + process $proc$libresoc.v:155633$8255 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:154294.14-154294.44" - process $proc$libresoc.v:154294$8208 + attribute \src "libresoc.v:155926.14-155926.44" + process $proc$libresoc.v:155926$8256 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8209 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8209 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 end - attribute \src "libresoc.v:154318.14-154318.63" - process $proc$libresoc.v:154318$8210 + attribute \src "libresoc.v:155950.14-155950.63" + process $proc$libresoc.v:155950$8258 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8211 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8211 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 end - attribute \src "libresoc.v:154327.7-154327.38" - process $proc$libresoc.v:154327$8212 + attribute \src "libresoc.v:155959.7-155959.38" + process $proc$libresoc.v:155959$8260 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8213 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8213 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 end - attribute \src "libresoc.v:154336.14-154336.39" - process $proc$libresoc.v:154336$8214 + attribute \src "libresoc.v:155968.14-155968.39" + process $proc$libresoc.v:155968$8262 assign { } { } - assign $0\mul_op__insn$13[31:0]$8215 0 + assign $0\mul_op__insn$13[31:0]$8263 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8215 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 end - attribute \src "libresoc.v:154495.13-154495.42" - process $proc$libresoc.v:154495$8216 + attribute \src "libresoc.v:156127.13-156127.42" + process $proc$libresoc.v:156127$8264 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8217 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8217 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 end - attribute \src "libresoc.v:154579.7-154579.35" - process $proc$libresoc.v:154579$8218 + attribute \src "libresoc.v:156211.7-156211.35" + process $proc$libresoc.v:156211$8266 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8219 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8219 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 end - attribute \src "libresoc.v:154588.7-154588.36" - process $proc$libresoc.v:154588$8220 + attribute \src "libresoc.v:156220.7-156220.36" + process $proc$libresoc.v:156220$8268 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8221 1'0 + assign $0\mul_op__is_signed$12[0:0]$8269 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8221 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 end - attribute \src "libresoc.v:154599.7-154599.32" - process $proc$libresoc.v:154599$8222 + attribute \src "libresoc.v:156231.7-156231.32" + process $proc$libresoc.v:156231$8270 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8223 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8223 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 end - attribute \src "libresoc.v:154608.7-154608.32" - process $proc$libresoc.v:154608$8224 + attribute \src "libresoc.v:156240.7-156240.32" + process $proc$libresoc.v:156240$8272 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8225 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8225 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 end - attribute \src "libresoc.v:154617.7-154617.32" - process $proc$libresoc.v:154617$8226 + attribute \src "libresoc.v:156249.7-156249.32" + process $proc$libresoc.v:156249$8274 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8227 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8227 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 end - attribute \src "libresoc.v:154624.7-154624.32" - process $proc$libresoc.v:154624$8228 + attribute \src "libresoc.v:156256.7-156256.32" + process $proc$libresoc.v:156256$8276 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8229 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8229 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 end - attribute \src "libresoc.v:154633.7-154633.36" - process $proc$libresoc.v:154633$8230 + attribute \src "libresoc.v:156265.7-156265.36" + process $proc$libresoc.v:156265$8278 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8231 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8231 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 end - attribute \src "libresoc.v:154642.13-154642.29" - process $proc$libresoc.v:154642$8232 + attribute \src "libresoc.v:156274.13-156274.29" + process $proc$libresoc.v:156274$8280 assign { } { } - assign $0\muxid$1[1:0]$8233 2'00 + assign $0\muxid$1[1:0]$8281 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8233 + update \muxid$1 $0\muxid$1[1:0]$8281 end - attribute \src "libresoc.v:154663.14-154663.43" - process $proc$libresoc.v:154663$8234 + attribute \src "libresoc.v:156295.14-156295.43" + process $proc$libresoc.v:156295$8282 assign { } { } - assign $0\o$14[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$8235 + update \o$14 $0\o$14[63:0]$8283 end - attribute \src "libresoc.v:154670.7-154670.18" - process $proc$libresoc.v:154670$8236 + attribute \src "libresoc.v:156302.7-156302.18" + process $proc$libresoc.v:156302$8284 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:154942.7-154942.20" - process $proc$libresoc.v:154942$8237 + attribute \src "libresoc.v:156574.7-156574.20" + process $proc$libresoc.v:156574$8285 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154947.13-154947.26" - process $proc$libresoc.v:154947$8238 + attribute \src "libresoc.v:156579.13-156579.26" + process $proc$libresoc.v:156579$8286 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:154954.7-154954.23" - process $proc$libresoc.v:154954$8239 + attribute \src "libresoc.v:156586.7-156586.23" + process $proc$libresoc.v:156586$8287 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:154965.7-154965.25" - process $proc$libresoc.v:154965$8240 + attribute \src "libresoc.v:156597.7-156597.25" + process $proc$libresoc.v:156597$8288 assign { } { } - assign $0\xer_so$15[0:0]$8241 1'0 + assign $0\xer_so$15[0:0]$8289 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8241 + update \xer_so$15 $0\xer_so$15[0:0]$8289 end - attribute \src "libresoc.v:154972.7-154972.23" - process $proc$libresoc.v:154972$8242 + attribute \src "libresoc.v:156604.7-156604.23" + process $proc$libresoc.v:156604$8290 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:154980.3-154981.37" - process $proc$libresoc.v:154980$8106 + attribute \src "libresoc.v:156612.3-156613.37" + process $proc$libresoc.v:156612$8154 assign { } { } - assign $0\xer_so$15[0:0]$8107 \xer_so$15$next + assign $0\xer_so$15[0:0]$8155 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8107 + update \xer_so$15 $0\xer_so$15[0:0]$8155 end - attribute \src "libresoc.v:154982.3-154983.35" - process $proc$libresoc.v:154982$8108 + attribute \src "libresoc.v:156614.3-156615.35" + process $proc$libresoc.v:156614$8156 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:154984.3-154985.29" - process $proc$libresoc.v:154984$8109 + attribute \src "libresoc.v:156616.3-156617.29" + process $proc$libresoc.v:156616$8157 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:154986.3-154987.35" - process $proc$libresoc.v:154986$8110 + attribute \src "libresoc.v:156618.3-156619.35" + process $proc$libresoc.v:156618$8158 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:154988.3-154989.25" - process $proc$libresoc.v:154988$8111 + attribute \src "libresoc.v:156620.3-156621.25" + process $proc$libresoc.v:156620$8159 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:154990.3-154991.31" - process $proc$libresoc.v:154990$8112 + attribute \src "libresoc.v:156622.3-156623.31" + process $proc$libresoc.v:156622$8160 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:154992.3-154993.27" - process $proc$libresoc.v:154992$8113 + attribute \src "libresoc.v:156624.3-156625.27" + process $proc$libresoc.v:156624$8161 assign { } { } - assign $0\o$14[63:0]$8114 \o$14$next + assign $0\o$14[63:0]$8162 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8114 + update \o$14 $0\o$14[63:0]$8162 end - attribute \src "libresoc.v:154994.3-154995.25" - process $proc$libresoc.v:154994$8115 + attribute \src "libresoc.v:156626.3-156627.25" + process $proc$libresoc.v:156626$8163 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:154996.3-154997.57" - process $proc$libresoc.v:154996$8116 + attribute \src "libresoc.v:156628.3-156629.57" + process $proc$libresoc.v:156628$8164 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8117 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8117 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 end - attribute \src "libresoc.v:154998.3-154999.53" - process $proc$libresoc.v:154998$8118 + attribute \src "libresoc.v:156630.3-156631.53" + process $proc$libresoc.v:156630$8166 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8119 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8119 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 end - attribute \src "libresoc.v:155000.3-155001.67" - process $proc$libresoc.v:155000$8120 + attribute \src "libresoc.v:156632.3-156633.67" + process $proc$libresoc.v:156632$8168 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8121 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8121 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 end - attribute \src "libresoc.v:155002.3-155003.63" - process $proc$libresoc.v:155002$8122 + attribute \src "libresoc.v:156634.3-156635.63" + process $proc$libresoc.v:156634$8170 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8123 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8123 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 end - attribute \src "libresoc.v:155004.3-155005.51" - process $proc$libresoc.v:155004$8124 + attribute \src "libresoc.v:156636.3-156637.51" + process $proc$libresoc.v:156636$8172 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8125 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8125 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 end - attribute \src "libresoc.v:155006.3-155007.51" - process $proc$libresoc.v:155006$8126 + attribute \src "libresoc.v:156638.3-156639.51" + process $proc$libresoc.v:156638$8174 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8127 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8127 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 end - attribute \src "libresoc.v:155008.3-155009.51" - process $proc$libresoc.v:155008$8128 + attribute \src "libresoc.v:156640.3-156641.51" + process $proc$libresoc.v:156640$8176 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8129 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8129 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 end - attribute \src "libresoc.v:155010.3-155011.51" - process $proc$libresoc.v:155010$8130 + attribute \src "libresoc.v:156642.3-156643.51" + process $proc$libresoc.v:156642$8178 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8131 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8131 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 end - attribute \src "libresoc.v:155012.3-155013.59" - process $proc$libresoc.v:155012$8132 + attribute \src "libresoc.v:156644.3-156645.59" + process $proc$libresoc.v:156644$8180 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8133 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8133 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 end - attribute \src "libresoc.v:155014.3-155015.57" - process $proc$libresoc.v:155014$8134 + attribute \src "libresoc.v:156646.3-156647.57" + process $proc$libresoc.v:156646$8182 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8135 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8135 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 end - attribute \src "libresoc.v:155016.3-155017.59" - process $proc$libresoc.v:155016$8136 + attribute \src "libresoc.v:156648.3-156649.59" + process $proc$libresoc.v:156648$8184 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8137 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8137 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 end - attribute \src "libresoc.v:155018.3-155019.49" - process $proc$libresoc.v:155018$8138 + attribute \src "libresoc.v:156650.3-156651.49" + process $proc$libresoc.v:156650$8186 assign { } { } - assign $0\mul_op__insn$13[31:0]$8139 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8139 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 end - attribute \src "libresoc.v:155020.3-155021.33" - process $proc$libresoc.v:155020$8140 + attribute \src "libresoc.v:156652.3-156653.33" + process $proc$libresoc.v:156652$8188 assign { } { } - assign $0\muxid$1[1:0]$8141 \muxid$1$next + assign $0\muxid$1[1:0]$8189 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8141 + update \muxid$1 $0\muxid$1[1:0]$8189 end - attribute \src "libresoc.v:155022.3-155023.29" - process $proc$libresoc.v:155022$8142 + attribute \src "libresoc.v:156654.3-156655.29" + process $proc$libresoc.v:156654$8190 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155110.3-155127.6" - process $proc$libresoc.v:155110$8143 + attribute \src "libresoc.v:156742.3-156759.6" + process $proc$libresoc.v:156742$8191 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8144 $2\r_busy$next[0:0]$8146 - attribute \src "libresoc.v:155111.5-155111.29" + assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 + attribute \src "libresoc.v:156743.5-156743.29" switch \initial - attribute \src "libresoc.v:155111.9-155111.17" + attribute \src "libresoc.v:156743.9-156743.17" case 1'1 case end @@ -323296,34 +325793,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8145 1'1 + assign $1\r_busy$next[0:0]$8193 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8145 1'0 + assign $1\r_busy$next[0:0]$8193 1'0 case - assign $1\r_busy$next[0:0]$8145 \r_busy + assign $1\r_busy$next[0:0]$8193 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8146 1'0 + assign $2\r_busy$next[0:0]$8194 1'0 case - assign $2\r_busy$next[0:0]$8146 $1\r_busy$next[0:0]$8145 + assign $2\r_busy$next[0:0]$8194 $1\r_busy$next[0:0]$8193 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8144 + update \r_busy$next $0\r_busy$next[0:0]$8192 end - attribute \src "libresoc.v:155128.3-155140.6" - process $proc$libresoc.v:155128$8147 + attribute \src "libresoc.v:156760.3-156772.6" + process $proc$libresoc.v:156760$8195 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8148 $1\muxid$1$next[1:0]$8149 - attribute \src "libresoc.v:155129.5-155129.29" + assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 + attribute \src "libresoc.v:156761.5-156761.29" switch \initial - attribute \src "libresoc.v:155129.9-155129.17" + attribute \src "libresoc.v:156761.9-156761.17" case 1'1 case end @@ -323332,19 +325829,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8149 \muxid$58 + assign $1\muxid$1$next[1:0]$8197 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8149 \muxid$58 + assign $1\muxid$1$next[1:0]$8197 \muxid$58 case - assign $1\muxid$1$next[1:0]$8149 \muxid$1 + assign $1\muxid$1$next[1:0]$8197 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8148 + update \muxid$1$next $0\muxid$1$next[1:0]$8196 end - attribute \src "libresoc.v:155141.3-155176.6" - process $proc$libresoc.v:155141$8150 + attribute \src "libresoc.v:156773.3-156808.6" + process $proc$libresoc.v:156773$8198 assign { } { } assign { } { } assign { } { } @@ -323369,27 +325866,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8151 $1\mul_op__fn_unit$3$next[13:0]$8163 + assign $0\mul_op__fn_unit$3$next[13:0]$8199 $1\mul_op__fn_unit$3$next[13:0]$8211 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8154 $1\mul_op__insn$13$next[31:0]$8166 - assign $0\mul_op__insn_type$2$next[6:0]$8155 $1\mul_op__insn_type$2$next[6:0]$8167 - assign $0\mul_op__is_32bit$11$next[0:0]$8156 $1\mul_op__is_32bit$11$next[0:0]$8168 - assign $0\mul_op__is_signed$12$next[0:0]$8157 $1\mul_op__is_signed$12$next[0:0]$8169 + assign $0\mul_op__insn$13$next[31:0]$8202 $1\mul_op__insn$13$next[31:0]$8214 + assign $0\mul_op__insn_type$2$next[6:0]$8203 $1\mul_op__insn_type$2$next[6:0]$8215 + assign $0\mul_op__is_32bit$11$next[0:0]$8204 $1\mul_op__is_32bit$11$next[0:0]$8216 + assign $0\mul_op__is_signed$12$next[0:0]$8205 $1\mul_op__is_signed$12$next[0:0]$8217 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8162 $1\mul_op__write_cr0$10$next[0:0]$8174 - assign $0\mul_op__imm_data__data$4$next[63:0]$8152 $2\mul_op__imm_data__data$4$next[63:0]$8175 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8153 $2\mul_op__imm_data__ok$5$next[0:0]$8176 - assign $0\mul_op__oe__oe$8$next[0:0]$8158 $2\mul_op__oe__oe$8$next[0:0]$8177 - assign $0\mul_op__oe__ok$9$next[0:0]$8159 $2\mul_op__oe__ok$9$next[0:0]$8178 - assign $0\mul_op__rc__ok$7$next[0:0]$8160 $2\mul_op__rc__ok$7$next[0:0]$8179 - assign $0\mul_op__rc__rc$6$next[0:0]$8161 $2\mul_op__rc__rc$6$next[0:0]$8180 - attribute \src "libresoc.v:155142.5-155142.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8210 $1\mul_op__write_cr0$10$next[0:0]$8222 + assign $0\mul_op__imm_data__data$4$next[63:0]$8200 $2\mul_op__imm_data__data$4$next[63:0]$8223 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8201 $2\mul_op__imm_data__ok$5$next[0:0]$8224 + assign $0\mul_op__oe__oe$8$next[0:0]$8206 $2\mul_op__oe__oe$8$next[0:0]$8225 + assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 + assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 + assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 + attribute \src "libresoc.v:156774.5-156774.29" switch \initial - attribute \src "libresoc.v:155142.9-155142.17" + attribute \src "libresoc.v:156774.9-156774.17" case 1'1 case end @@ -323409,7 +325906,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -323424,20 +325921,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8166 $1\mul_op__is_signed$12$next[0:0]$8169 $1\mul_op__is_32bit$11$next[0:0]$8168 $1\mul_op__write_cr0$10$next[0:0]$8174 $1\mul_op__oe__ok$9$next[0:0]$8171 $1\mul_op__oe__oe$8$next[0:0]$8170 $1\mul_op__rc__ok$7$next[0:0]$8172 $1\mul_op__rc__rc$6$next[0:0]$8173 $1\mul_op__imm_data__ok$5$next[0:0]$8165 $1\mul_op__imm_data__data$4$next[63:0]$8164 $1\mul_op__fn_unit$3$next[13:0]$8163 $1\mul_op__insn_type$2$next[6:0]$8167 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8163 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8164 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8165 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8166 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8167 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8168 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8169 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8170 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8171 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8172 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8173 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8174 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8211 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8212 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8213 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8214 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8215 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8216 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8217 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8218 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8219 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8220 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8221 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8222 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -323449,46 +325946,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8175 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8180 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8179 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8177 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8178 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8175 $1\mul_op__imm_data__data$4$next[63:0]$8164 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8176 $1\mul_op__imm_data__ok$5$next[0:0]$8165 - assign $2\mul_op__oe__oe$8$next[0:0]$8177 $1\mul_op__oe__oe$8$next[0:0]$8170 - assign $2\mul_op__oe__ok$9$next[0:0]$8178 $1\mul_op__oe__ok$9$next[0:0]$8171 - assign $2\mul_op__rc__ok$7$next[0:0]$8179 $1\mul_op__rc__ok$7$next[0:0]$8172 - assign $2\mul_op__rc__rc$6$next[0:0]$8180 $1\mul_op__rc__rc$6$next[0:0]$8173 + assign $2\mul_op__imm_data__data$4$next[63:0]$8223 $1\mul_op__imm_data__data$4$next[63:0]$8212 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 $1\mul_op__imm_data__ok$5$next[0:0]$8213 + assign $2\mul_op__oe__oe$8$next[0:0]$8225 $1\mul_op__oe__oe$8$next[0:0]$8218 + assign $2\mul_op__oe__ok$9$next[0:0]$8226 $1\mul_op__oe__ok$9$next[0:0]$8219 + assign $2\mul_op__rc__ok$7$next[0:0]$8227 $1\mul_op__rc__ok$7$next[0:0]$8220 + assign $2\mul_op__rc__rc$6$next[0:0]$8228 $1\mul_op__rc__rc$6$next[0:0]$8221 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8151 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8152 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8153 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8154 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8155 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8156 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8157 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8158 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8159 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8160 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8161 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8162 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8199 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8200 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8201 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8202 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8203 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8204 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8205 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8206 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8207 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8208 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 end - attribute \src "libresoc.v:155177.3-155195.6" - process $proc$libresoc.v:155177$8181 + attribute \src "libresoc.v:156809.3-156827.6" + process $proc$libresoc.v:156809$8229 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$8183 $1\o$14$next[63:0]$8185 - assign $0\o_ok$next[0:0]$8182 $2\o_ok$next[0:0]$8186 - attribute \src "libresoc.v:155178.5-155178.29" + assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 + assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 + attribute \src "libresoc.v:156810.5-156810.29" switch \initial - attribute \src "libresoc.v:155178.9-155178.17" + attribute \src "libresoc.v:156810.9-156810.17" case 1'1 case end @@ -323498,41 +325995,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8184 $1\o$14$next[63:0]$8185 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$8184 \o_ok - assign $1\o$14$next[63:0]$8185 \o$14 + assign $1\o_ok$next[0:0]$8232 \o_ok + assign $1\o$14$next[63:0]$8233 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8186 1'0 + assign $2\o_ok$next[0:0]$8234 1'0 case - assign $2\o_ok$next[0:0]$8186 $1\o_ok$next[0:0]$8184 + assign $2\o_ok$next[0:0]$8234 $1\o_ok$next[0:0]$8232 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8182 - update \o$14$next $0\o$14$next[63:0]$8183 + update \o_ok$next $0\o_ok$next[0:0]$8230 + update \o$14$next $0\o$14$next[63:0]$8231 end - attribute \src "libresoc.v:155196.3-155214.6" - process $proc$libresoc.v:155196$8187 + attribute \src "libresoc.v:156828.3-156846.6" + process $proc$libresoc.v:156828$8235 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8188 $1\cr_a$next[3:0]$8190 + assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 assign { } { } - assign $0\cr_a_ok$next[0:0]$8189 $2\cr_a_ok$next[0:0]$8192 - attribute \src "libresoc.v:155197.5-155197.29" + assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 + attribute \src "libresoc.v:156829.5-156829.29" switch \initial - attribute \src "libresoc.v:155197.9-155197.17" + attribute \src "libresoc.v:156829.9-156829.17" case 1'1 case end @@ -323542,41 +326039,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8191 $1\cr_a$next[3:0]$8190 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$8190 \cr_a - assign $1\cr_a_ok$next[0:0]$8191 \cr_a_ok + assign $1\cr_a$next[3:0]$8238 \cr_a + assign $1\cr_a_ok$next[0:0]$8239 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8192 1'0 + assign $2\cr_a_ok$next[0:0]$8240 1'0 case - assign $2\cr_a_ok$next[0:0]$8192 $1\cr_a_ok$next[0:0]$8191 + assign $2\cr_a_ok$next[0:0]$8240 $1\cr_a_ok$next[0:0]$8239 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8188 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8189 + update \cr_a$next $0\cr_a$next[3:0]$8236 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 end - attribute \src "libresoc.v:155215.3-155233.6" - process $proc$libresoc.v:155215$8193 + attribute \src "libresoc.v:156847.3-156865.6" + process $proc$libresoc.v:156847$8241 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8194 $1\xer_ov$next[1:0]$8196 + assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8195 $2\xer_ov_ok$next[0:0]$8198 - attribute \src "libresoc.v:155216.5-155216.29" + assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 + attribute \src "libresoc.v:156848.5-156848.29" switch \initial - attribute \src "libresoc.v:155216.9-155216.17" + attribute \src "libresoc.v:156848.9-156848.17" case 1'1 case end @@ -323586,41 +326083,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8197 $1\xer_ov$next[1:0]$8196 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$8196 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8197 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8244 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8245 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8198 1'0 + assign $2\xer_ov_ok$next[0:0]$8246 1'0 case - assign $2\xer_ov_ok$next[0:0]$8198 $1\xer_ov_ok$next[0:0]$8197 + assign $2\xer_ov_ok$next[0:0]$8246 $1\xer_ov_ok$next[0:0]$8245 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8194 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8195 + update \xer_ov$next $0\xer_ov$next[1:0]$8242 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 end - attribute \src "libresoc.v:155234.3-155252.6" - process $proc$libresoc.v:155234$8199 + attribute \src "libresoc.v:156866.3-156884.6" + process $proc$libresoc.v:156866$8247 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8201 $1\xer_so$15$next[0:0]$8203 - assign $0\xer_so_ok$next[0:0]$8200 $2\xer_so_ok$next[0:0]$8204 - attribute \src "libresoc.v:155235.5-155235.29" + assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 + assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 + attribute \src "libresoc.v:156867.5-156867.29" switch \initial - attribute \src "libresoc.v:155235.9-155235.17" + attribute \src "libresoc.v:156867.9-156867.17" case 1'1 case end @@ -323630,30 +326127,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8202 $1\xer_so$15$next[0:0]$8203 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$8202 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8203 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8250 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8251 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8204 1'0 + assign $2\xer_so_ok$next[0:0]$8252 1'0 case - assign $2\xer_so_ok$next[0:0]$8204 $1\xer_so_ok$next[0:0]$8202 + assign $2\xer_so_ok$next[0:0]$8252 $1\xer_so_ok$next[0:0]$8250 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8200 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8201 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 end - connect \$56 $and$libresoc.v:154979$8105_Y + connect \$56 $and$libresoc.v:156611$8153_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -323680,13 +326177,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:155282.1-155293.10" +attribute \src "libresoc.v:156914.1-156925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:155291.17-155291.111" - wire $and$libresoc.v:155291$8243_Y + attribute \src "libresoc.v:156923.17-156923.111" + wire $and$libresoc.v:156923$8291_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323696,7 +326193,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155291$8243 + cell $and $and$libresoc.v:156923$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323704,18 +326201,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155291$8243_Y + connect \Y $and$libresoc.v:156923$8291_Y end - connect \$1 $and$libresoc.v:155291$8243_Y + connect \$1 $and$libresoc.v:156923$8291_Y connect \trigger \$1 end -attribute \src "libresoc.v:155297.1-155308.10" +attribute \src "libresoc.v:156929.1-156940.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:155306.17-155306.111" - wire $and$libresoc.v:155306$8244_Y + attribute \src "libresoc.v:156938.17-156938.111" + wire $and$libresoc.v:156938$8292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323725,7 +326222,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155306$8244 + cell $and $and$libresoc.v:156938$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323733,18 +326230,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155306$8244_Y + connect \Y $and$libresoc.v:156938$8292_Y end - connect \$1 $and$libresoc.v:155306$8244_Y + connect \$1 $and$libresoc.v:156938$8292_Y connect \trigger \$1 end -attribute \src "libresoc.v:155312.1-155323.10" +attribute \src "libresoc.v:156944.1-156955.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:155321.17-155321.111" - wire $and$libresoc.v:155321$8245_Y + attribute \src "libresoc.v:156953.17-156953.111" + wire $and$libresoc.v:156953$8293_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323754,7 +326251,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155321$8245 + cell $and $and$libresoc.v:156953$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323762,18 +326259,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155321$8245_Y + connect \Y $and$libresoc.v:156953$8293_Y end - connect \$1 $and$libresoc.v:155321$8245_Y + connect \$1 $and$libresoc.v:156953$8293_Y connect \trigger \$1 end -attribute \src "libresoc.v:155327.1-155338.10" +attribute \src "libresoc.v:156959.1-156970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:155336.17-155336.111" - wire $and$libresoc.v:155336$8246_Y + attribute \src "libresoc.v:156968.17-156968.111" + wire $and$libresoc.v:156968$8294_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323783,7 +326280,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155336$8246 + cell $and $and$libresoc.v:156968$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323791,18 +326288,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155336$8246_Y + connect \Y $and$libresoc.v:156968$8294_Y end - connect \$1 $and$libresoc.v:155336$8246_Y + connect \$1 $and$libresoc.v:156968$8294_Y connect \trigger \$1 end -attribute \src "libresoc.v:155342.1-155353.10" +attribute \src "libresoc.v:156974.1-156985.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:155351.17-155351.111" - wire $and$libresoc.v:155351$8247_Y + attribute \src "libresoc.v:156983.17-156983.111" + wire $and$libresoc.v:156983$8295_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323812,7 +326309,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155351$8247 + cell $and $and$libresoc.v:156983$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323820,18 +326317,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155351$8247_Y + connect \Y $and$libresoc.v:156983$8295_Y end - connect \$1 $and$libresoc.v:155351$8247_Y + connect \$1 $and$libresoc.v:156983$8295_Y connect \trigger \$1 end -attribute \src "libresoc.v:155357.1-155368.10" +attribute \src "libresoc.v:156989.1-157000.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:155366.17-155366.111" - wire $and$libresoc.v:155366$8248_Y + attribute \src "libresoc.v:156998.17-156998.111" + wire $and$libresoc.v:156998$8296_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323841,7 +326338,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155366$8248 + cell $and $and$libresoc.v:156998$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323849,18 +326346,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155366$8248_Y + connect \Y $and$libresoc.v:156998$8296_Y end - connect \$1 $and$libresoc.v:155366$8248_Y + connect \$1 $and$libresoc.v:156998$8296_Y connect \trigger \$1 end -attribute \src "libresoc.v:155372.1-155383.10" +attribute \src "libresoc.v:157004.1-157015.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:155381.17-155381.111" - wire $and$libresoc.v:155381$8249_Y + attribute \src "libresoc.v:157013.17-157013.111" + wire $and$libresoc.v:157013$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323870,7 +326367,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155381$8249 + cell $and $and$libresoc.v:157013$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323878,18 +326375,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155381$8249_Y + connect \Y $and$libresoc.v:157013$8297_Y end - connect \$1 $and$libresoc.v:155381$8249_Y + connect \$1 $and$libresoc.v:157013$8297_Y connect \trigger \$1 end -attribute \src "libresoc.v:155387.1-155398.10" +attribute \src "libresoc.v:157019.1-157030.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:155396.17-155396.111" - wire $and$libresoc.v:155396$8250_Y + attribute \src "libresoc.v:157028.17-157028.111" + wire $and$libresoc.v:157028$8298_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323899,7 +326396,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155396$8250 + cell $and $and$libresoc.v:157028$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323907,18 +326404,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155396$8250_Y + connect \Y $and$libresoc.v:157028$8298_Y end - connect \$1 $and$libresoc.v:155396$8250_Y + connect \$1 $and$libresoc.v:157028$8298_Y connect \trigger \$1 end -attribute \src "libresoc.v:155402.1-155413.10" +attribute \src "libresoc.v:157034.1-157045.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:155411.17-155411.111" - wire $and$libresoc.v:155411$8251_Y + attribute \src "libresoc.v:157043.17-157043.111" + wire $and$libresoc.v:157043$8299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323928,7 +326425,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155411$8251 + cell $and $and$libresoc.v:157043$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323936,18 +326433,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155411$8251_Y + connect \Y $and$libresoc.v:157043$8299_Y end - connect \$1 $and$libresoc.v:155411$8251_Y + connect \$1 $and$libresoc.v:157043$8299_Y connect \trigger \$1 end -attribute \src "libresoc.v:155417.1-155428.10" +attribute \src "libresoc.v:157049.1-157060.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:155426.17-155426.111" - wire $and$libresoc.v:155426$8252_Y + attribute \src "libresoc.v:157058.17-157058.111" + wire $and$libresoc.v:157058$8300_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323957,7 +326454,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155426$8252 + cell $and $and$libresoc.v:157058$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323965,18 +326462,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155426$8252_Y + connect \Y $and$libresoc.v:157058$8300_Y end - connect \$1 $and$libresoc.v:155426$8252_Y + connect \$1 $and$libresoc.v:157058$8300_Y connect \trigger \$1 end -attribute \src "libresoc.v:155432.1-155443.10" +attribute \src "libresoc.v:157064.1-157075.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:155441.17-155441.111" - wire $and$libresoc.v:155441$8253_Y + attribute \src "libresoc.v:157073.17-157073.111" + wire $and$libresoc.v:157073$8301_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323986,7 +326483,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155441$8253 + cell $and $and$libresoc.v:157073$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323994,18 +326491,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155441$8253_Y + connect \Y $and$libresoc.v:157073$8301_Y end - connect \$1 $and$libresoc.v:155441$8253_Y + connect \$1 $and$libresoc.v:157073$8301_Y connect \trigger \$1 end -attribute \src "libresoc.v:155447.1-155458.10" +attribute \src "libresoc.v:157079.1-157090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:155456.17-155456.111" - wire $and$libresoc.v:155456$8254_Y + attribute \src "libresoc.v:157088.17-157088.111" + wire $and$libresoc.v:157088$8302_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324015,7 +326512,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155456$8254 + cell $and $and$libresoc.v:157088$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324023,18 +326520,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155456$8254_Y + connect \Y $and$libresoc.v:157088$8302_Y end - connect \$1 $and$libresoc.v:155456$8254_Y + connect \$1 $and$libresoc.v:157088$8302_Y connect \trigger \$1 end -attribute \src "libresoc.v:155462.1-155473.10" +attribute \src "libresoc.v:157094.1-157105.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:155471.17-155471.111" - wire $and$libresoc.v:155471$8255_Y + attribute \src "libresoc.v:157103.17-157103.111" + wire $and$libresoc.v:157103$8303_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324044,7 +326541,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155471$8255 + cell $and $and$libresoc.v:157103$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324052,18 +326549,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155471$8255_Y + connect \Y $and$libresoc.v:157103$8303_Y end - connect \$1 $and$libresoc.v:155471$8255_Y + connect \$1 $and$libresoc.v:157103$8303_Y connect \trigger \$1 end -attribute \src "libresoc.v:155477.1-155488.10" +attribute \src "libresoc.v:157109.1-157120.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:155486.17-155486.111" - wire $and$libresoc.v:155486$8256_Y + attribute \src "libresoc.v:157118.17-157118.111" + wire $and$libresoc.v:157118$8304_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324073,7 +326570,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155486$8256 + cell $and $and$libresoc.v:157118$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324081,18 +326578,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155486$8256_Y + connect \Y $and$libresoc.v:157118$8304_Y end - connect \$1 $and$libresoc.v:155486$8256_Y + connect \$1 $and$libresoc.v:157118$8304_Y connect \trigger \$1 end -attribute \src "libresoc.v:155492.1-155503.10" +attribute \src "libresoc.v:157124.1-157135.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:155501.17-155501.111" - wire $and$libresoc.v:155501$8257_Y + attribute \src "libresoc.v:157133.17-157133.111" + wire $and$libresoc.v:157133$8305_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324102,7 +326599,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155501$8257 + cell $and $and$libresoc.v:157133$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324110,18 +326607,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155501$8257_Y + connect \Y $and$libresoc.v:157133$8305_Y end - connect \$1 $and$libresoc.v:155501$8257_Y + connect \$1 $and$libresoc.v:157133$8305_Y connect \trigger \$1 end -attribute \src "libresoc.v:155507.1-155518.10" +attribute \src "libresoc.v:157139.1-157150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:155516.17-155516.111" - wire $and$libresoc.v:155516$8258_Y + attribute \src "libresoc.v:157148.17-157148.111" + wire $and$libresoc.v:157148$8306_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324131,7 +326628,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155516$8258 + cell $and $and$libresoc.v:157148$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324139,18 +326636,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155516$8258_Y + connect \Y $and$libresoc.v:157148$8306_Y end - connect \$1 $and$libresoc.v:155516$8258_Y + connect \$1 $and$libresoc.v:157148$8306_Y connect \trigger \$1 end -attribute \src "libresoc.v:155522.1-155533.10" +attribute \src "libresoc.v:157154.1-157165.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:155531.17-155531.111" - wire $and$libresoc.v:155531$8259_Y + attribute \src "libresoc.v:157163.17-157163.111" + wire $and$libresoc.v:157163$8307_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324160,7 +326657,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155531$8259 + cell $and $and$libresoc.v:157163$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324168,18 +326665,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155531$8259_Y + connect \Y $and$libresoc.v:157163$8307_Y end - connect \$1 $and$libresoc.v:155531$8259_Y + connect \$1 $and$libresoc.v:157163$8307_Y connect \trigger \$1 end -attribute \src "libresoc.v:155537.1-155548.10" +attribute \src "libresoc.v:157169.1-157180.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:155546.17-155546.111" - wire $and$libresoc.v:155546$8260_Y + attribute \src "libresoc.v:157178.17-157178.111" + wire $and$libresoc.v:157178$8308_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324189,7 +326686,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155546$8260 + cell $and $and$libresoc.v:157178$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324197,18 +326694,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155546$8260_Y + connect \Y $and$libresoc.v:157178$8308_Y end - connect \$1 $and$libresoc.v:155546$8260_Y + connect \$1 $and$libresoc.v:157178$8308_Y connect \trigger \$1 end -attribute \src "libresoc.v:155552.1-155563.10" +attribute \src "libresoc.v:157184.1-157195.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:155561.17-155561.111" - wire $and$libresoc.v:155561$8261_Y + attribute \src "libresoc.v:157193.17-157193.111" + wire $and$libresoc.v:157193$8309_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324218,7 +326715,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155561$8261 + cell $and $and$libresoc.v:157193$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324226,18 +326723,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155561$8261_Y + connect \Y $and$libresoc.v:157193$8309_Y end - connect \$1 $and$libresoc.v:155561$8261_Y + connect \$1 $and$libresoc.v:157193$8309_Y connect \trigger \$1 end -attribute \src "libresoc.v:155567.1-155578.10" +attribute \src "libresoc.v:157199.1-157210.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:155576.17-155576.111" - wire $and$libresoc.v:155576$8262_Y + attribute \src "libresoc.v:157208.17-157208.111" + wire $and$libresoc.v:157208$8310_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324247,7 +326744,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155576$8262 + cell $and $and$libresoc.v:157208$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324255,18 +326752,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155576$8262_Y + connect \Y $and$libresoc.v:157208$8310_Y end - connect \$1 $and$libresoc.v:155576$8262_Y + connect \$1 $and$libresoc.v:157208$8310_Y connect \trigger \$1 end -attribute \src "libresoc.v:155582.1-155593.10" +attribute \src "libresoc.v:157214.1-157225.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:155591.17-155591.111" - wire $and$libresoc.v:155591$8263_Y + attribute \src "libresoc.v:157223.17-157223.111" + wire $and$libresoc.v:157223$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324276,7 +326773,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155591$8263 + cell $and $and$libresoc.v:157223$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324284,18 +326781,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155591$8263_Y + connect \Y $and$libresoc.v:157223$8311_Y end - connect \$1 $and$libresoc.v:155591$8263_Y + connect \$1 $and$libresoc.v:157223$8311_Y connect \trigger \$1 end -attribute \src "libresoc.v:155597.1-155608.10" +attribute \src "libresoc.v:157229.1-157240.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:155606.17-155606.111" - wire $and$libresoc.v:155606$8264_Y + attribute \src "libresoc.v:157238.17-157238.111" + wire $and$libresoc.v:157238$8312_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324305,7 +326802,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155606$8264 + cell $and $and$libresoc.v:157238$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324313,18 +326810,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155606$8264_Y + connect \Y $and$libresoc.v:157238$8312_Y end - connect \$1 $and$libresoc.v:155606$8264_Y + connect \$1 $and$libresoc.v:157238$8312_Y connect \trigger \$1 end -attribute \src "libresoc.v:155612.1-155623.10" +attribute \src "libresoc.v:157244.1-157255.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:155621.17-155621.111" - wire $and$libresoc.v:155621$8265_Y + attribute \src "libresoc.v:157253.17-157253.111" + wire $and$libresoc.v:157253$8313_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324334,7 +326831,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155621$8265 + cell $and $and$libresoc.v:157253$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324342,18 +326839,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155621$8265_Y + connect \Y $and$libresoc.v:157253$8313_Y end - connect \$1 $and$libresoc.v:155621$8265_Y + connect \$1 $and$libresoc.v:157253$8313_Y connect \trigger \$1 end -attribute \src "libresoc.v:155627.1-155638.10" +attribute \src "libresoc.v:157259.1-157270.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:155636.17-155636.111" - wire $and$libresoc.v:155636$8266_Y + attribute \src "libresoc.v:157268.17-157268.111" + wire $and$libresoc.v:157268$8314_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324363,7 +326860,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155636$8266 + cell $and $and$libresoc.v:157268$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324371,18 +326868,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155636$8266_Y + connect \Y $and$libresoc.v:157268$8314_Y end - connect \$1 $and$libresoc.v:155636$8266_Y + connect \$1 $and$libresoc.v:157268$8314_Y connect \trigger \$1 end -attribute \src "libresoc.v:155642.1-155653.10" +attribute \src "libresoc.v:157274.1-157285.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:155651.17-155651.111" - wire $and$libresoc.v:155651$8267_Y + attribute \src "libresoc.v:157283.17-157283.111" + wire $and$libresoc.v:157283$8315_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324392,7 +326889,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155651$8267 + cell $and $and$libresoc.v:157283$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324400,18 +326897,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155651$8267_Y + connect \Y $and$libresoc.v:157283$8315_Y end - connect \$1 $and$libresoc.v:155651$8267_Y + connect \$1 $and$libresoc.v:157283$8315_Y connect \trigger \$1 end -attribute \src "libresoc.v:155657.1-155668.10" +attribute \src "libresoc.v:157289.1-157300.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:155666.17-155666.111" - wire $and$libresoc.v:155666$8268_Y + attribute \src "libresoc.v:157298.17-157298.111" + wire $and$libresoc.v:157298$8316_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -324421,7 +326918,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:155666$8268 + cell $and $and$libresoc.v:157298$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324429,42 +326926,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:155666$8268_Y + connect \Y $and$libresoc.v:157298$8316_Y end - connect \$1 $and$libresoc.v:155666$8268_Y + connect \$1 $and$libresoc.v:157298$8316_Y connect \trigger \$1 end -attribute \src "libresoc.v:155672.1-155730.10" +attribute \src "libresoc.v:157304.1-157362.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:155673.7-155673.20" + attribute \src "libresoc.v:157305.7-157305.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155718.3-155726.6" - wire $0\q_int$next[0:0]$8279 - attribute \src "libresoc.v:155716.3-155717.27" + attribute \src "libresoc.v:157350.3-157358.6" + wire $0\q_int$next[0:0]$8327 + attribute \src "libresoc.v:157348.3-157349.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155718.3-155726.6" - wire $1\q_int$next[0:0]$8280 - attribute \src "libresoc.v:155695.7-155695.19" + attribute \src "libresoc.v:157350.3-157358.6" + wire $1\q_int$next[0:0]$8328 + attribute \src "libresoc.v:157327.7-157327.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155708.17-155708.96" - wire $and$libresoc.v:155708$8269_Y - attribute \src "libresoc.v:155713.17-155713.96" - wire $and$libresoc.v:155713$8274_Y - attribute \src "libresoc.v:155710.18-155710.93" - wire $not$libresoc.v:155710$8271_Y - attribute \src "libresoc.v:155712.17-155712.92" - wire $not$libresoc.v:155712$8273_Y - attribute \src "libresoc.v:155715.17-155715.92" - wire $not$libresoc.v:155715$8276_Y - attribute \src "libresoc.v:155709.18-155709.98" - wire $or$libresoc.v:155709$8270_Y - attribute \src "libresoc.v:155711.18-155711.99" - wire $or$libresoc.v:155711$8272_Y - attribute \src "libresoc.v:155714.17-155714.97" - wire $or$libresoc.v:155714$8275_Y + attribute \src "libresoc.v:157340.17-157340.96" + wire $and$libresoc.v:157340$8317_Y + attribute \src "libresoc.v:157345.17-157345.96" + wire $and$libresoc.v:157345$8322_Y + attribute \src "libresoc.v:157342.18-157342.93" + wire $not$libresoc.v:157342$8319_Y + attribute \src "libresoc.v:157344.17-157344.92" + wire $not$libresoc.v:157344$8321_Y + attribute \src "libresoc.v:157347.17-157347.92" + wire $not$libresoc.v:157347$8324_Y + attribute \src "libresoc.v:157341.18-157341.98" + wire $or$libresoc.v:157341$8318_Y + attribute \src "libresoc.v:157343.18-157343.99" + wire $or$libresoc.v:157343$8320_Y + attribute \src "libresoc.v:157346.17-157346.97" + wire $or$libresoc.v:157346$8323_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324481,11 +326978,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155673.7-155673.15" + attribute \src "libresoc.v:157305.7-157305.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324502,7 +326999,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155708$8269 + cell $and $and$libresoc.v:157340$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324510,10 +327007,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155708$8269_Y + connect \Y $and$libresoc.v:157340$8317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155713$8274 + cell $and $and$libresoc.v:157345$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324521,34 +327018,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155713$8274_Y + connect \Y $and$libresoc.v:157345$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155710$8271 + cell $not $not$libresoc.v:157342$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155710$8271_Y + connect \Y $not$libresoc.v:157342$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155712$8273 + cell $not $not$libresoc.v:157344$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155712$8273_Y + connect \Y $not$libresoc.v:157344$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155715$8276 + cell $not $not$libresoc.v:157347$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155715$8276_Y + connect \Y $not$libresoc.v:157347$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155709$8270 + cell $or $or$libresoc.v:157341$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324556,10 +327053,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155709$8270_Y + connect \Y $or$libresoc.v:157341$8318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155711$8272 + cell $or $or$libresoc.v:157343$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324567,10 +327064,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155711$8272_Y + connect \Y $or$libresoc.v:157343$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155714$8275 + cell $or $or$libresoc.v:157346$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324578,39 +327075,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155714$8275_Y + connect \Y $or$libresoc.v:157346$8323_Y end - attribute \src "libresoc.v:155673.7-155673.20" - process $proc$libresoc.v:155673$8281 + attribute \src "libresoc.v:157305.7-157305.20" + process $proc$libresoc.v:157305$8329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155695.7-155695.19" - process $proc$libresoc.v:155695$8282 + attribute \src "libresoc.v:157327.7-157327.19" + process $proc$libresoc.v:157327$8330 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155716.3-155717.27" - process $proc$libresoc.v:155716$8277 + attribute \src "libresoc.v:157348.3-157349.27" + process $proc$libresoc.v:157348$8325 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155718.3-155726.6" - process $proc$libresoc.v:155718$8278 + attribute \src "libresoc.v:157350.3-157358.6" + process $proc$libresoc.v:157350$8326 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8279 $1\q_int$next[0:0]$8280 - attribute \src "libresoc.v:155719.5-155719.29" + assign $0\q_int$next[0:0]$8327 $1\q_int$next[0:0]$8328 + attribute \src "libresoc.v:157351.5-157351.29" switch \initial - attribute \src "libresoc.v:155719.9-155719.17" + attribute \src "libresoc.v:157351.9-157351.17" case 1'1 case end @@ -324619,56 +327116,56 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8280 1'0 + assign $1\q_int$next[0:0]$8328 1'0 case - assign $1\q_int$next[0:0]$8280 \$5 + assign $1\q_int$next[0:0]$8328 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8279 + update \q_int$next $0\q_int$next[0:0]$8327 end - connect \$9 $and$libresoc.v:155708$8269_Y - connect \$11 $or$libresoc.v:155709$8270_Y - connect \$13 $not$libresoc.v:155710$8271_Y - connect \$15 $or$libresoc.v:155711$8272_Y - connect \$1 $not$libresoc.v:155712$8273_Y - connect \$3 $and$libresoc.v:155713$8274_Y - connect \$5 $or$libresoc.v:155714$8275_Y - connect \$7 $not$libresoc.v:155715$8276_Y + connect \$9 $and$libresoc.v:157340$8317_Y + connect \$11 $or$libresoc.v:157341$8318_Y + connect \$13 $not$libresoc.v:157342$8319_Y + connect \$15 $or$libresoc.v:157343$8320_Y + connect \$1 $not$libresoc.v:157344$8321_Y + connect \$3 $and$libresoc.v:157345$8322_Y + connect \$5 $or$libresoc.v:157346$8323_Y + connect \$7 $not$libresoc.v:157347$8324_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155734.1-155792.10" +attribute \src "libresoc.v:157366.1-157424.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:155735.7-155735.20" + attribute \src "libresoc.v:157367.7-157367.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155780.3-155788.6" - wire $0\q_int$next[0:0]$8293 - attribute \src "libresoc.v:155778.3-155779.27" + attribute \src "libresoc.v:157412.3-157420.6" + wire $0\q_int$next[0:0]$8341 + attribute \src "libresoc.v:157410.3-157411.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155780.3-155788.6" - wire $1\q_int$next[0:0]$8294 - attribute \src "libresoc.v:155757.7-155757.19" + attribute \src "libresoc.v:157412.3-157420.6" + wire $1\q_int$next[0:0]$8342 + attribute \src "libresoc.v:157389.7-157389.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155770.17-155770.96" - wire $and$libresoc.v:155770$8283_Y - attribute \src "libresoc.v:155775.17-155775.96" - wire $and$libresoc.v:155775$8288_Y - attribute \src "libresoc.v:155772.18-155772.93" - wire $not$libresoc.v:155772$8285_Y - attribute \src "libresoc.v:155774.17-155774.92" - wire $not$libresoc.v:155774$8287_Y - attribute \src "libresoc.v:155777.17-155777.92" - wire $not$libresoc.v:155777$8290_Y - attribute \src "libresoc.v:155771.18-155771.98" - wire $or$libresoc.v:155771$8284_Y - attribute \src "libresoc.v:155773.18-155773.99" - wire $or$libresoc.v:155773$8286_Y - attribute \src "libresoc.v:155776.17-155776.97" - wire $or$libresoc.v:155776$8289_Y + attribute \src "libresoc.v:157402.17-157402.96" + wire $and$libresoc.v:157402$8331_Y + attribute \src "libresoc.v:157407.17-157407.96" + wire $and$libresoc.v:157407$8336_Y + attribute \src "libresoc.v:157404.18-157404.93" + wire $not$libresoc.v:157404$8333_Y + attribute \src "libresoc.v:157406.17-157406.92" + wire $not$libresoc.v:157406$8335_Y + attribute \src "libresoc.v:157409.17-157409.92" + wire $not$libresoc.v:157409$8338_Y + attribute \src "libresoc.v:157403.18-157403.98" + wire $or$libresoc.v:157403$8332_Y + attribute \src "libresoc.v:157405.18-157405.99" + wire $or$libresoc.v:157405$8334_Y + attribute \src "libresoc.v:157408.17-157408.97" + wire $or$libresoc.v:157408$8337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324685,11 +327182,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155735.7-155735.15" + attribute \src "libresoc.v:157367.7-157367.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324706,7 +327203,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155770$8283 + cell $and $and$libresoc.v:157402$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324714,10 +327211,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155770$8283_Y + connect \Y $and$libresoc.v:157402$8331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155775$8288 + cell $and $and$libresoc.v:157407$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324725,34 +327222,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155775$8288_Y + connect \Y $and$libresoc.v:157407$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155772$8285 + cell $not $not$libresoc.v:157404$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155772$8285_Y + connect \Y $not$libresoc.v:157404$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155774$8287 + cell $not $not$libresoc.v:157406$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155774$8287_Y + connect \Y $not$libresoc.v:157406$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155777$8290 + cell $not $not$libresoc.v:157409$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155777$8290_Y + connect \Y $not$libresoc.v:157409$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155771$8284 + cell $or $or$libresoc.v:157403$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324760,10 +327257,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155771$8284_Y + connect \Y $or$libresoc.v:157403$8332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155773$8286 + cell $or $or$libresoc.v:157405$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324771,10 +327268,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155773$8286_Y + connect \Y $or$libresoc.v:157405$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155776$8289 + cell $or $or$libresoc.v:157408$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324782,39 +327279,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155776$8289_Y + connect \Y $or$libresoc.v:157408$8337_Y end - attribute \src "libresoc.v:155735.7-155735.20" - process $proc$libresoc.v:155735$8295 + attribute \src "libresoc.v:157367.7-157367.20" + process $proc$libresoc.v:157367$8343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155757.7-155757.19" - process $proc$libresoc.v:155757$8296 + attribute \src "libresoc.v:157389.7-157389.19" + process $proc$libresoc.v:157389$8344 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155778.3-155779.27" - process $proc$libresoc.v:155778$8291 + attribute \src "libresoc.v:157410.3-157411.27" + process $proc$libresoc.v:157410$8339 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155780.3-155788.6" - process $proc$libresoc.v:155780$8292 + attribute \src "libresoc.v:157412.3-157420.6" + process $proc$libresoc.v:157412$8340 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8293 $1\q_int$next[0:0]$8294 - attribute \src "libresoc.v:155781.5-155781.29" + assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 + attribute \src "libresoc.v:157413.5-157413.29" switch \initial - attribute \src "libresoc.v:155781.9-155781.17" + attribute \src "libresoc.v:157413.9-157413.17" case 1'1 case end @@ -324823,56 +327320,56 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8294 1'0 + assign $1\q_int$next[0:0]$8342 1'0 case - assign $1\q_int$next[0:0]$8294 \$5 + assign $1\q_int$next[0:0]$8342 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8293 + update \q_int$next $0\q_int$next[0:0]$8341 end - connect \$9 $and$libresoc.v:155770$8283_Y - connect \$11 $or$libresoc.v:155771$8284_Y - connect \$13 $not$libresoc.v:155772$8285_Y - connect \$15 $or$libresoc.v:155773$8286_Y - connect \$1 $not$libresoc.v:155774$8287_Y - connect \$3 $and$libresoc.v:155775$8288_Y - connect \$5 $or$libresoc.v:155776$8289_Y - connect \$7 $not$libresoc.v:155777$8290_Y + connect \$9 $and$libresoc.v:157402$8331_Y + connect \$11 $or$libresoc.v:157403$8332_Y + connect \$13 $not$libresoc.v:157404$8333_Y + connect \$15 $or$libresoc.v:157405$8334_Y + connect \$1 $not$libresoc.v:157406$8335_Y + connect \$3 $and$libresoc.v:157407$8336_Y + connect \$5 $or$libresoc.v:157408$8337_Y + connect \$7 $not$libresoc.v:157409$8338_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155796.1-155854.10" +attribute \src "libresoc.v:157428.1-157486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:155797.7-155797.20" + attribute \src "libresoc.v:157429.7-157429.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155842.3-155850.6" - wire $0\q_int$next[0:0]$8307 - attribute \src "libresoc.v:155840.3-155841.27" + attribute \src "libresoc.v:157474.3-157482.6" + wire $0\q_int$next[0:0]$8355 + attribute \src "libresoc.v:157472.3-157473.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155842.3-155850.6" - wire $1\q_int$next[0:0]$8308 - attribute \src "libresoc.v:155819.7-155819.19" + attribute \src "libresoc.v:157474.3-157482.6" + wire $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157451.7-157451.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155832.17-155832.96" - wire $and$libresoc.v:155832$8297_Y - attribute \src "libresoc.v:155837.17-155837.96" - wire $and$libresoc.v:155837$8302_Y - attribute \src "libresoc.v:155834.18-155834.93" - wire $not$libresoc.v:155834$8299_Y - attribute \src "libresoc.v:155836.17-155836.92" - wire $not$libresoc.v:155836$8301_Y - attribute \src "libresoc.v:155839.17-155839.92" - wire $not$libresoc.v:155839$8304_Y - attribute \src "libresoc.v:155833.18-155833.98" - wire $or$libresoc.v:155833$8298_Y - attribute \src "libresoc.v:155835.18-155835.99" - wire $or$libresoc.v:155835$8300_Y - attribute \src "libresoc.v:155838.17-155838.97" - wire $or$libresoc.v:155838$8303_Y + attribute \src "libresoc.v:157464.17-157464.96" + wire $and$libresoc.v:157464$8345_Y + attribute \src "libresoc.v:157469.17-157469.96" + wire $and$libresoc.v:157469$8350_Y + attribute \src "libresoc.v:157466.18-157466.93" + wire $not$libresoc.v:157466$8347_Y + attribute \src "libresoc.v:157468.17-157468.92" + wire $not$libresoc.v:157468$8349_Y + attribute \src "libresoc.v:157471.17-157471.92" + wire $not$libresoc.v:157471$8352_Y + attribute \src "libresoc.v:157465.18-157465.98" + wire $or$libresoc.v:157465$8346_Y + attribute \src "libresoc.v:157467.18-157467.99" + wire $or$libresoc.v:157467$8348_Y + attribute \src "libresoc.v:157470.17-157470.97" + wire $or$libresoc.v:157470$8351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324889,11 +327386,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155797.7-155797.15" + attribute \src "libresoc.v:157429.7-157429.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324910,7 +327407,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155832$8297 + cell $and $and$libresoc.v:157464$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324918,10 +327415,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155832$8297_Y + connect \Y $and$libresoc.v:157464$8345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155837$8302 + cell $and $and$libresoc.v:157469$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324929,34 +327426,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155837$8302_Y + connect \Y $and$libresoc.v:157469$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155834$8299 + cell $not $not$libresoc.v:157466$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155834$8299_Y + connect \Y $not$libresoc.v:157466$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155836$8301 + cell $not $not$libresoc.v:157468$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155836$8301_Y + connect \Y $not$libresoc.v:157468$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155839$8304 + cell $not $not$libresoc.v:157471$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155839$8304_Y + connect \Y $not$libresoc.v:157471$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155833$8298 + cell $or $or$libresoc.v:157465$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324964,10 +327461,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155833$8298_Y + connect \Y $or$libresoc.v:157465$8346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155835$8300 + cell $or $or$libresoc.v:157467$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324975,10 +327472,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155835$8300_Y + connect \Y $or$libresoc.v:157467$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155838$8303 + cell $or $or$libresoc.v:157470$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324986,39 +327483,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155838$8303_Y + connect \Y $or$libresoc.v:157470$8351_Y end - attribute \src "libresoc.v:155797.7-155797.20" - process $proc$libresoc.v:155797$8309 + attribute \src "libresoc.v:157429.7-157429.20" + process $proc$libresoc.v:157429$8357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155819.7-155819.19" - process $proc$libresoc.v:155819$8310 + attribute \src "libresoc.v:157451.7-157451.19" + process $proc$libresoc.v:157451$8358 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155840.3-155841.27" - process $proc$libresoc.v:155840$8305 + attribute \src "libresoc.v:157472.3-157473.27" + process $proc$libresoc.v:157472$8353 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155842.3-155850.6" - process $proc$libresoc.v:155842$8306 + attribute \src "libresoc.v:157474.3-157482.6" + process $proc$libresoc.v:157474$8354 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8307 $1\q_int$next[0:0]$8308 - attribute \src "libresoc.v:155843.5-155843.29" + assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 + attribute \src "libresoc.v:157475.5-157475.29" switch \initial - attribute \src "libresoc.v:155843.9-155843.17" + attribute \src "libresoc.v:157475.9-157475.17" case 1'1 case end @@ -325027,56 +327524,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8308 1'0 + assign $1\q_int$next[0:0]$8356 1'0 case - assign $1\q_int$next[0:0]$8308 \$5 + assign $1\q_int$next[0:0]$8356 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8307 + update \q_int$next $0\q_int$next[0:0]$8355 end - connect \$9 $and$libresoc.v:155832$8297_Y - connect \$11 $or$libresoc.v:155833$8298_Y - connect \$13 $not$libresoc.v:155834$8299_Y - connect \$15 $or$libresoc.v:155835$8300_Y - connect \$1 $not$libresoc.v:155836$8301_Y - connect \$3 $and$libresoc.v:155837$8302_Y - connect \$5 $or$libresoc.v:155838$8303_Y - connect \$7 $not$libresoc.v:155839$8304_Y + connect \$9 $and$libresoc.v:157464$8345_Y + connect \$11 $or$libresoc.v:157465$8346_Y + connect \$13 $not$libresoc.v:157466$8347_Y + connect \$15 $or$libresoc.v:157467$8348_Y + connect \$1 $not$libresoc.v:157468$8349_Y + connect \$3 $and$libresoc.v:157469$8350_Y + connect \$5 $or$libresoc.v:157470$8351_Y + connect \$7 $not$libresoc.v:157471$8352_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155858.1-155916.10" +attribute \src "libresoc.v:157490.1-157548.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:155859.7-155859.20" + attribute \src "libresoc.v:157491.7-157491.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155904.3-155912.6" - wire $0\q_int$next[0:0]$8321 - attribute \src "libresoc.v:155902.3-155903.27" + attribute \src "libresoc.v:157536.3-157544.6" + wire $0\q_int$next[0:0]$8369 + attribute \src "libresoc.v:157534.3-157535.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155904.3-155912.6" - wire $1\q_int$next[0:0]$8322 - attribute \src "libresoc.v:155881.7-155881.19" + attribute \src "libresoc.v:157536.3-157544.6" + wire $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157513.7-157513.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155894.17-155894.96" - wire $and$libresoc.v:155894$8311_Y - attribute \src "libresoc.v:155899.17-155899.96" - wire $and$libresoc.v:155899$8316_Y - attribute \src "libresoc.v:155896.18-155896.93" - wire $not$libresoc.v:155896$8313_Y - attribute \src "libresoc.v:155898.17-155898.92" - wire $not$libresoc.v:155898$8315_Y - attribute \src "libresoc.v:155901.17-155901.92" - wire $not$libresoc.v:155901$8318_Y - attribute \src "libresoc.v:155895.18-155895.98" - wire $or$libresoc.v:155895$8312_Y - attribute \src "libresoc.v:155897.18-155897.99" - wire $or$libresoc.v:155897$8314_Y - attribute \src "libresoc.v:155900.17-155900.97" - wire $or$libresoc.v:155900$8317_Y + attribute \src "libresoc.v:157526.17-157526.96" + wire $and$libresoc.v:157526$8359_Y + attribute \src "libresoc.v:157531.17-157531.96" + wire $and$libresoc.v:157531$8364_Y + attribute \src "libresoc.v:157528.18-157528.93" + wire $not$libresoc.v:157528$8361_Y + attribute \src "libresoc.v:157530.17-157530.92" + wire $not$libresoc.v:157530$8363_Y + attribute \src "libresoc.v:157533.17-157533.92" + wire $not$libresoc.v:157533$8366_Y + attribute \src "libresoc.v:157527.18-157527.98" + wire $or$libresoc.v:157527$8360_Y + attribute \src "libresoc.v:157529.18-157529.99" + wire $or$libresoc.v:157529$8362_Y + attribute \src "libresoc.v:157532.17-157532.97" + wire $or$libresoc.v:157532$8365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325093,11 +327590,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155859.7-155859.15" + attribute \src "libresoc.v:157491.7-157491.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325114,7 +327611,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155894$8311 + cell $and $and$libresoc.v:157526$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325122,10 +327619,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155894$8311_Y + connect \Y $and$libresoc.v:157526$8359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155899$8316 + cell $and $and$libresoc.v:157531$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325133,34 +327630,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155899$8316_Y + connect \Y $and$libresoc.v:157531$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155896$8313 + cell $not $not$libresoc.v:157528$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155896$8313_Y + connect \Y $not$libresoc.v:157528$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155898$8315 + cell $not $not$libresoc.v:157530$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155898$8315_Y + connect \Y $not$libresoc.v:157530$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155901$8318 + cell $not $not$libresoc.v:157533$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155901$8318_Y + connect \Y $not$libresoc.v:157533$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155895$8312 + cell $or $or$libresoc.v:157527$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325168,10 +327665,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155895$8312_Y + connect \Y $or$libresoc.v:157527$8360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155897$8314 + cell $or $or$libresoc.v:157529$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325179,10 +327676,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155897$8314_Y + connect \Y $or$libresoc.v:157529$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155900$8317 + cell $or $or$libresoc.v:157532$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325190,39 +327687,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155900$8317_Y + connect \Y $or$libresoc.v:157532$8365_Y end - attribute \src "libresoc.v:155859.7-155859.20" - process $proc$libresoc.v:155859$8323 + attribute \src "libresoc.v:157491.7-157491.20" + process $proc$libresoc.v:157491$8371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155881.7-155881.19" - process $proc$libresoc.v:155881$8324 + attribute \src "libresoc.v:157513.7-157513.19" + process $proc$libresoc.v:157513$8372 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155902.3-155903.27" - process $proc$libresoc.v:155902$8319 + attribute \src "libresoc.v:157534.3-157535.27" + process $proc$libresoc.v:157534$8367 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155904.3-155912.6" - process $proc$libresoc.v:155904$8320 + attribute \src "libresoc.v:157536.3-157544.6" + process $proc$libresoc.v:157536$8368 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8321 $1\q_int$next[0:0]$8322 - attribute \src "libresoc.v:155905.5-155905.29" + assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 + attribute \src "libresoc.v:157537.5-157537.29" switch \initial - attribute \src "libresoc.v:155905.9-155905.17" + attribute \src "libresoc.v:157537.9-157537.17" case 1'1 case end @@ -325231,56 +327728,56 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8322 1'0 + assign $1\q_int$next[0:0]$8370 1'0 case - assign $1\q_int$next[0:0]$8322 \$5 + assign $1\q_int$next[0:0]$8370 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8321 + update \q_int$next $0\q_int$next[0:0]$8369 end - connect \$9 $and$libresoc.v:155894$8311_Y - connect \$11 $or$libresoc.v:155895$8312_Y - connect \$13 $not$libresoc.v:155896$8313_Y - connect \$15 $or$libresoc.v:155897$8314_Y - connect \$1 $not$libresoc.v:155898$8315_Y - connect \$3 $and$libresoc.v:155899$8316_Y - connect \$5 $or$libresoc.v:155900$8317_Y - connect \$7 $not$libresoc.v:155901$8318_Y + connect \$9 $and$libresoc.v:157526$8359_Y + connect \$11 $or$libresoc.v:157527$8360_Y + connect \$13 $not$libresoc.v:157528$8361_Y + connect \$15 $or$libresoc.v:157529$8362_Y + connect \$1 $not$libresoc.v:157530$8363_Y + connect \$3 $and$libresoc.v:157531$8364_Y + connect \$5 $or$libresoc.v:157532$8365_Y + connect \$7 $not$libresoc.v:157533$8366_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155920.1-155978.10" +attribute \src "libresoc.v:157552.1-157610.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:155921.7-155921.20" + attribute \src "libresoc.v:157553.7-157553.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155966.3-155974.6" - wire $0\q_int$next[0:0]$8335 - attribute \src "libresoc.v:155964.3-155965.27" + attribute \src "libresoc.v:157598.3-157606.6" + wire $0\q_int$next[0:0]$8383 + attribute \src "libresoc.v:157596.3-157597.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:155966.3-155974.6" - wire $1\q_int$next[0:0]$8336 - attribute \src "libresoc.v:155943.7-155943.19" + attribute \src "libresoc.v:157598.3-157606.6" + wire $1\q_int$next[0:0]$8384 + attribute \src "libresoc.v:157575.7-157575.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:155956.17-155956.96" - wire $and$libresoc.v:155956$8325_Y - attribute \src "libresoc.v:155961.17-155961.96" - wire $and$libresoc.v:155961$8330_Y - attribute \src "libresoc.v:155958.18-155958.93" - wire $not$libresoc.v:155958$8327_Y - attribute \src "libresoc.v:155960.17-155960.92" - wire $not$libresoc.v:155960$8329_Y - attribute \src "libresoc.v:155963.17-155963.92" - wire $not$libresoc.v:155963$8332_Y - attribute \src "libresoc.v:155957.18-155957.98" - wire $or$libresoc.v:155957$8326_Y - attribute \src "libresoc.v:155959.18-155959.99" - wire $or$libresoc.v:155959$8328_Y - attribute \src "libresoc.v:155962.17-155962.97" - wire $or$libresoc.v:155962$8331_Y + attribute \src "libresoc.v:157588.17-157588.96" + wire $and$libresoc.v:157588$8373_Y + attribute \src "libresoc.v:157593.17-157593.96" + wire $and$libresoc.v:157593$8378_Y + attribute \src "libresoc.v:157590.18-157590.93" + wire $not$libresoc.v:157590$8375_Y + attribute \src "libresoc.v:157592.17-157592.92" + wire $not$libresoc.v:157592$8377_Y + attribute \src "libresoc.v:157595.17-157595.92" + wire $not$libresoc.v:157595$8380_Y + attribute \src "libresoc.v:157589.18-157589.98" + wire $or$libresoc.v:157589$8374_Y + attribute \src "libresoc.v:157591.18-157591.99" + wire $or$libresoc.v:157591$8376_Y + attribute \src "libresoc.v:157594.17-157594.97" + wire $or$libresoc.v:157594$8379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325297,11 +327794,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155921.7-155921.15" + attribute \src "libresoc.v:157553.7-157553.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325318,7 +327815,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:155956$8325 + cell $and $and$libresoc.v:157588$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325326,10 +327823,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:155956$8325_Y + connect \Y $and$libresoc.v:157588$8373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:155961$8330 + cell $and $and$libresoc.v:157593$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325337,34 +327834,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:155961$8330_Y + connect \Y $and$libresoc.v:157593$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:155958$8327 + cell $not $not$libresoc.v:157590$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:155958$8327_Y + connect \Y $not$libresoc.v:157590$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:155960$8329 + cell $not $not$libresoc.v:157592$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155960$8329_Y + connect \Y $not$libresoc.v:157592$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:155963$8332 + cell $not $not$libresoc.v:157595$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:155963$8332_Y + connect \Y $not$libresoc.v:157595$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:155957$8326 + cell $or $or$libresoc.v:157589$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325372,10 +327869,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:155957$8326_Y + connect \Y $or$libresoc.v:157589$8374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:155959$8328 + cell $or $or$libresoc.v:157591$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325383,10 +327880,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:155959$8328_Y + connect \Y $or$libresoc.v:157591$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:155962$8331 + cell $or $or$libresoc.v:157594$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325394,39 +327891,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:155962$8331_Y + connect \Y $or$libresoc.v:157594$8379_Y end - attribute \src "libresoc.v:155921.7-155921.20" - process $proc$libresoc.v:155921$8337 + attribute \src "libresoc.v:157553.7-157553.20" + process $proc$libresoc.v:157553$8385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155943.7-155943.19" - process $proc$libresoc.v:155943$8338 + attribute \src "libresoc.v:157575.7-157575.19" + process $proc$libresoc.v:157575$8386 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:155964.3-155965.27" - process $proc$libresoc.v:155964$8333 + attribute \src "libresoc.v:157596.3-157597.27" + process $proc$libresoc.v:157596$8381 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:155966.3-155974.6" - process $proc$libresoc.v:155966$8334 + attribute \src "libresoc.v:157598.3-157606.6" + process $proc$libresoc.v:157598$8382 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8335 $1\q_int$next[0:0]$8336 - attribute \src "libresoc.v:155967.5-155967.29" + assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 + attribute \src "libresoc.v:157599.5-157599.29" switch \initial - attribute \src "libresoc.v:155967.9-155967.17" + attribute \src "libresoc.v:157599.9-157599.17" case 1'1 case end @@ -325435,56 +327932,56 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8336 1'0 + assign $1\q_int$next[0:0]$8384 1'0 case - assign $1\q_int$next[0:0]$8336 \$5 + assign $1\q_int$next[0:0]$8384 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8335 + update \q_int$next $0\q_int$next[0:0]$8383 end - connect \$9 $and$libresoc.v:155956$8325_Y - connect \$11 $or$libresoc.v:155957$8326_Y - connect \$13 $not$libresoc.v:155958$8327_Y - connect \$15 $or$libresoc.v:155959$8328_Y - connect \$1 $not$libresoc.v:155960$8329_Y - connect \$3 $and$libresoc.v:155961$8330_Y - connect \$5 $or$libresoc.v:155962$8331_Y - connect \$7 $not$libresoc.v:155963$8332_Y + connect \$9 $and$libresoc.v:157588$8373_Y + connect \$11 $or$libresoc.v:157589$8374_Y + connect \$13 $not$libresoc.v:157590$8375_Y + connect \$15 $or$libresoc.v:157591$8376_Y + connect \$1 $not$libresoc.v:157592$8377_Y + connect \$3 $and$libresoc.v:157593$8378_Y + connect \$5 $or$libresoc.v:157594$8379_Y + connect \$7 $not$libresoc.v:157595$8380_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:155982.1-156040.10" +attribute \src "libresoc.v:157614.1-157672.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:155983.7-155983.20" + attribute \src "libresoc.v:157615.7-157615.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156028.3-156036.6" - wire $0\q_int$next[0:0]$8349 - attribute \src "libresoc.v:156026.3-156027.27" + attribute \src "libresoc.v:157660.3-157668.6" + wire $0\q_int$next[0:0]$8397 + attribute \src "libresoc.v:157658.3-157659.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156028.3-156036.6" - wire $1\q_int$next[0:0]$8350 - attribute \src "libresoc.v:156005.7-156005.19" + attribute \src "libresoc.v:157660.3-157668.6" + wire $1\q_int$next[0:0]$8398 + attribute \src "libresoc.v:157637.7-157637.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156018.17-156018.96" - wire $and$libresoc.v:156018$8339_Y - attribute \src "libresoc.v:156023.17-156023.96" - wire $and$libresoc.v:156023$8344_Y - attribute \src "libresoc.v:156020.18-156020.93" - wire $not$libresoc.v:156020$8341_Y - attribute \src "libresoc.v:156022.17-156022.92" - wire $not$libresoc.v:156022$8343_Y - attribute \src "libresoc.v:156025.17-156025.92" - wire $not$libresoc.v:156025$8346_Y - attribute \src "libresoc.v:156019.18-156019.98" - wire $or$libresoc.v:156019$8340_Y - attribute \src "libresoc.v:156021.18-156021.99" - wire $or$libresoc.v:156021$8342_Y - attribute \src "libresoc.v:156024.17-156024.97" - wire $or$libresoc.v:156024$8345_Y + attribute \src "libresoc.v:157650.17-157650.96" + wire $and$libresoc.v:157650$8387_Y + attribute \src "libresoc.v:157655.17-157655.96" + wire $and$libresoc.v:157655$8392_Y + attribute \src "libresoc.v:157652.18-157652.93" + wire $not$libresoc.v:157652$8389_Y + attribute \src "libresoc.v:157654.17-157654.92" + wire $not$libresoc.v:157654$8391_Y + attribute \src "libresoc.v:157657.17-157657.92" + wire $not$libresoc.v:157657$8394_Y + attribute \src "libresoc.v:157651.18-157651.98" + wire $or$libresoc.v:157651$8388_Y + attribute \src "libresoc.v:157653.18-157653.99" + wire $or$libresoc.v:157653$8390_Y + attribute \src "libresoc.v:157656.17-157656.97" + wire $or$libresoc.v:157656$8393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325501,11 +327998,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:155983.7-155983.15" + attribute \src "libresoc.v:157615.7-157615.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325522,7 +328019,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156018$8339 + cell $and $and$libresoc.v:157650$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325530,10 +328027,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156018$8339_Y + connect \Y $and$libresoc.v:157650$8387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156023$8344 + cell $and $and$libresoc.v:157655$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325541,34 +328038,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156023$8344_Y + connect \Y $and$libresoc.v:157655$8392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156020$8341 + cell $not $not$libresoc.v:157652$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156020$8341_Y + connect \Y $not$libresoc.v:157652$8389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156022$8343 + cell $not $not$libresoc.v:157654$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156022$8343_Y + connect \Y $not$libresoc.v:157654$8391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156025$8346 + cell $not $not$libresoc.v:157657$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156025$8346_Y + connect \Y $not$libresoc.v:157657$8394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156019$8340 + cell $or $or$libresoc.v:157651$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325576,10 +328073,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156019$8340_Y + connect \Y $or$libresoc.v:157651$8388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156021$8342 + cell $or $or$libresoc.v:157653$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325587,10 +328084,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156021$8342_Y + connect \Y $or$libresoc.v:157653$8390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156024$8345 + cell $or $or$libresoc.v:157656$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325598,39 +328095,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156024$8345_Y + connect \Y $or$libresoc.v:157656$8393_Y end - attribute \src "libresoc.v:155983.7-155983.20" - process $proc$libresoc.v:155983$8351 + attribute \src "libresoc.v:157615.7-157615.20" + process $proc$libresoc.v:157615$8399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156005.7-156005.19" - process $proc$libresoc.v:156005$8352 + attribute \src "libresoc.v:157637.7-157637.19" + process $proc$libresoc.v:157637$8400 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156026.3-156027.27" - process $proc$libresoc.v:156026$8347 + attribute \src "libresoc.v:157658.3-157659.27" + process $proc$libresoc.v:157658$8395 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156028.3-156036.6" - process $proc$libresoc.v:156028$8348 + attribute \src "libresoc.v:157660.3-157668.6" + process $proc$libresoc.v:157660$8396 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8349 $1\q_int$next[0:0]$8350 - attribute \src "libresoc.v:156029.5-156029.29" + assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 + attribute \src "libresoc.v:157661.5-157661.29" switch \initial - attribute \src "libresoc.v:156029.9-156029.17" + attribute \src "libresoc.v:157661.9-157661.17" case 1'1 case end @@ -325639,56 +328136,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8350 1'0 + assign $1\q_int$next[0:0]$8398 1'0 case - assign $1\q_int$next[0:0]$8350 \$5 + assign $1\q_int$next[0:0]$8398 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8349 + update \q_int$next $0\q_int$next[0:0]$8397 end - connect \$9 $and$libresoc.v:156018$8339_Y - connect \$11 $or$libresoc.v:156019$8340_Y - connect \$13 $not$libresoc.v:156020$8341_Y - connect \$15 $or$libresoc.v:156021$8342_Y - connect \$1 $not$libresoc.v:156022$8343_Y - connect \$3 $and$libresoc.v:156023$8344_Y - connect \$5 $or$libresoc.v:156024$8345_Y - connect \$7 $not$libresoc.v:156025$8346_Y + connect \$9 $and$libresoc.v:157650$8387_Y + connect \$11 $or$libresoc.v:157651$8388_Y + connect \$13 $not$libresoc.v:157652$8389_Y + connect \$15 $or$libresoc.v:157653$8390_Y + connect \$1 $not$libresoc.v:157654$8391_Y + connect \$3 $and$libresoc.v:157655$8392_Y + connect \$5 $or$libresoc.v:157656$8393_Y + connect \$7 $not$libresoc.v:157657$8394_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156044.1-156102.10" +attribute \src "libresoc.v:157676.1-157734.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:156045.7-156045.20" + attribute \src "libresoc.v:157677.7-157677.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156090.3-156098.6" - wire $0\q_int$next[0:0]$8363 - attribute \src "libresoc.v:156088.3-156089.27" + attribute \src "libresoc.v:157722.3-157730.6" + wire $0\q_int$next[0:0]$8411 + attribute \src "libresoc.v:157720.3-157721.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156090.3-156098.6" - wire $1\q_int$next[0:0]$8364 - attribute \src "libresoc.v:156067.7-156067.19" + attribute \src "libresoc.v:157722.3-157730.6" + wire $1\q_int$next[0:0]$8412 + attribute \src "libresoc.v:157699.7-157699.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156080.17-156080.96" - wire $and$libresoc.v:156080$8353_Y - attribute \src "libresoc.v:156085.17-156085.96" - wire $and$libresoc.v:156085$8358_Y - attribute \src "libresoc.v:156082.18-156082.93" - wire $not$libresoc.v:156082$8355_Y - attribute \src "libresoc.v:156084.17-156084.92" - wire $not$libresoc.v:156084$8357_Y - attribute \src "libresoc.v:156087.17-156087.92" - wire $not$libresoc.v:156087$8360_Y - attribute \src "libresoc.v:156081.18-156081.98" - wire $or$libresoc.v:156081$8354_Y - attribute \src "libresoc.v:156083.18-156083.99" - wire $or$libresoc.v:156083$8356_Y - attribute \src "libresoc.v:156086.17-156086.97" - wire $or$libresoc.v:156086$8359_Y + attribute \src "libresoc.v:157712.17-157712.96" + wire $and$libresoc.v:157712$8401_Y + attribute \src "libresoc.v:157717.17-157717.96" + wire $and$libresoc.v:157717$8406_Y + attribute \src "libresoc.v:157714.18-157714.93" + wire $not$libresoc.v:157714$8403_Y + attribute \src "libresoc.v:157716.17-157716.92" + wire $not$libresoc.v:157716$8405_Y + attribute \src "libresoc.v:157719.17-157719.92" + wire $not$libresoc.v:157719$8408_Y + attribute \src "libresoc.v:157713.18-157713.98" + wire $or$libresoc.v:157713$8402_Y + attribute \src "libresoc.v:157715.18-157715.99" + wire $or$libresoc.v:157715$8404_Y + attribute \src "libresoc.v:157718.17-157718.97" + wire $or$libresoc.v:157718$8407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325705,11 +328202,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156045.7-156045.15" + attribute \src "libresoc.v:157677.7-157677.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325726,7 +328223,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156080$8353 + cell $and $and$libresoc.v:157712$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325734,10 +328231,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156080$8353_Y + connect \Y $and$libresoc.v:157712$8401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156085$8358 + cell $and $and$libresoc.v:157717$8406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325745,34 +328242,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156085$8358_Y + connect \Y $and$libresoc.v:157717$8406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156082$8355 + cell $not $not$libresoc.v:157714$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156082$8355_Y + connect \Y $not$libresoc.v:157714$8403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156084$8357 + cell $not $not$libresoc.v:157716$8405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156084$8357_Y + connect \Y $not$libresoc.v:157716$8405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156087$8360 + cell $not $not$libresoc.v:157719$8408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156087$8360_Y + connect \Y $not$libresoc.v:157719$8408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156081$8354 + cell $or $or$libresoc.v:157713$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325780,10 +328277,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156081$8354_Y + connect \Y $or$libresoc.v:157713$8402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156083$8356 + cell $or $or$libresoc.v:157715$8404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325791,10 +328288,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156083$8356_Y + connect \Y $or$libresoc.v:157715$8404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156086$8359 + cell $or $or$libresoc.v:157718$8407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325802,39 +328299,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156086$8359_Y + connect \Y $or$libresoc.v:157718$8407_Y end - attribute \src "libresoc.v:156045.7-156045.20" - process $proc$libresoc.v:156045$8365 + attribute \src "libresoc.v:157677.7-157677.20" + process $proc$libresoc.v:157677$8413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156067.7-156067.19" - process $proc$libresoc.v:156067$8366 + attribute \src "libresoc.v:157699.7-157699.19" + process $proc$libresoc.v:157699$8414 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156088.3-156089.27" - process $proc$libresoc.v:156088$8361 + attribute \src "libresoc.v:157720.3-157721.27" + process $proc$libresoc.v:157720$8409 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156090.3-156098.6" - process $proc$libresoc.v:156090$8362 + attribute \src "libresoc.v:157722.3-157730.6" + process $proc$libresoc.v:157722$8410 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8363 $1\q_int$next[0:0]$8364 - attribute \src "libresoc.v:156091.5-156091.29" + assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 + attribute \src "libresoc.v:157723.5-157723.29" switch \initial - attribute \src "libresoc.v:156091.9-156091.17" + attribute \src "libresoc.v:157723.9-157723.17" case 1'1 case end @@ -325843,56 +328340,56 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8364 1'0 + assign $1\q_int$next[0:0]$8412 1'0 case - assign $1\q_int$next[0:0]$8364 \$5 + assign $1\q_int$next[0:0]$8412 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8363 + update \q_int$next $0\q_int$next[0:0]$8411 end - connect \$9 $and$libresoc.v:156080$8353_Y - connect \$11 $or$libresoc.v:156081$8354_Y - connect \$13 $not$libresoc.v:156082$8355_Y - connect \$15 $or$libresoc.v:156083$8356_Y - connect \$1 $not$libresoc.v:156084$8357_Y - connect \$3 $and$libresoc.v:156085$8358_Y - connect \$5 $or$libresoc.v:156086$8359_Y - connect \$7 $not$libresoc.v:156087$8360_Y + connect \$9 $and$libresoc.v:157712$8401_Y + connect \$11 $or$libresoc.v:157713$8402_Y + connect \$13 $not$libresoc.v:157714$8403_Y + connect \$15 $or$libresoc.v:157715$8404_Y + connect \$1 $not$libresoc.v:157716$8405_Y + connect \$3 $and$libresoc.v:157717$8406_Y + connect \$5 $or$libresoc.v:157718$8407_Y + connect \$7 $not$libresoc.v:157719$8408_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156106.1-156164.10" +attribute \src "libresoc.v:157738.1-157796.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:156107.7-156107.20" + attribute \src "libresoc.v:157739.7-157739.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156152.3-156160.6" - wire $0\q_int$next[0:0]$8377 - attribute \src "libresoc.v:156150.3-156151.27" + attribute \src "libresoc.v:157784.3-157792.6" + wire $0\q_int$next[0:0]$8425 + attribute \src "libresoc.v:157782.3-157783.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156152.3-156160.6" - wire $1\q_int$next[0:0]$8378 - attribute \src "libresoc.v:156129.7-156129.19" + attribute \src "libresoc.v:157784.3-157792.6" + wire $1\q_int$next[0:0]$8426 + attribute \src "libresoc.v:157761.7-157761.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156142.17-156142.96" - wire $and$libresoc.v:156142$8367_Y - attribute \src "libresoc.v:156147.17-156147.96" - wire $and$libresoc.v:156147$8372_Y - attribute \src "libresoc.v:156144.18-156144.93" - wire $not$libresoc.v:156144$8369_Y - attribute \src "libresoc.v:156146.17-156146.92" - wire $not$libresoc.v:156146$8371_Y - attribute \src "libresoc.v:156149.17-156149.92" - wire $not$libresoc.v:156149$8374_Y - attribute \src "libresoc.v:156143.18-156143.98" - wire $or$libresoc.v:156143$8368_Y - attribute \src "libresoc.v:156145.18-156145.99" - wire $or$libresoc.v:156145$8370_Y - attribute \src "libresoc.v:156148.17-156148.97" - wire $or$libresoc.v:156148$8373_Y + attribute \src "libresoc.v:157774.17-157774.96" + wire $and$libresoc.v:157774$8415_Y + attribute \src "libresoc.v:157779.17-157779.96" + wire $and$libresoc.v:157779$8420_Y + attribute \src "libresoc.v:157776.18-157776.93" + wire $not$libresoc.v:157776$8417_Y + attribute \src "libresoc.v:157778.17-157778.92" + wire $not$libresoc.v:157778$8419_Y + attribute \src "libresoc.v:157781.17-157781.92" + wire $not$libresoc.v:157781$8422_Y + attribute \src "libresoc.v:157775.18-157775.98" + wire $or$libresoc.v:157775$8416_Y + attribute \src "libresoc.v:157777.18-157777.99" + wire $or$libresoc.v:157777$8418_Y + attribute \src "libresoc.v:157780.17-157780.97" + wire $or$libresoc.v:157780$8421_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325909,11 +328406,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156107.7-156107.15" + attribute \src "libresoc.v:157739.7-157739.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325930,7 +328427,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156142$8367 + cell $and $and$libresoc.v:157774$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325938,10 +328435,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156142$8367_Y + connect \Y $and$libresoc.v:157774$8415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156147$8372 + cell $and $and$libresoc.v:157779$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325949,34 +328446,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156147$8372_Y + connect \Y $and$libresoc.v:157779$8420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156144$8369 + cell $not $not$libresoc.v:157776$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156144$8369_Y + connect \Y $not$libresoc.v:157776$8417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156146$8371 + cell $not $not$libresoc.v:157778$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156146$8371_Y + connect \Y $not$libresoc.v:157778$8419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156149$8374 + cell $not $not$libresoc.v:157781$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156149$8374_Y + connect \Y $not$libresoc.v:157781$8422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156143$8368 + cell $or $or$libresoc.v:157775$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325984,10 +328481,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156143$8368_Y + connect \Y $or$libresoc.v:157775$8416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156145$8370 + cell $or $or$libresoc.v:157777$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325995,10 +328492,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156145$8370_Y + connect \Y $or$libresoc.v:157777$8418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156148$8373 + cell $or $or$libresoc.v:157780$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326006,39 +328503,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156148$8373_Y + connect \Y $or$libresoc.v:157780$8421_Y end - attribute \src "libresoc.v:156107.7-156107.20" - process $proc$libresoc.v:156107$8379 + attribute \src "libresoc.v:157739.7-157739.20" + process $proc$libresoc.v:157739$8427 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156129.7-156129.19" - process $proc$libresoc.v:156129$8380 + attribute \src "libresoc.v:157761.7-157761.19" + process $proc$libresoc.v:157761$8428 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156150.3-156151.27" - process $proc$libresoc.v:156150$8375 + attribute \src "libresoc.v:157782.3-157783.27" + process $proc$libresoc.v:157782$8423 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156152.3-156160.6" - process $proc$libresoc.v:156152$8376 + attribute \src "libresoc.v:157784.3-157792.6" + process $proc$libresoc.v:157784$8424 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8377 $1\q_int$next[0:0]$8378 - attribute \src "libresoc.v:156153.5-156153.29" + assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 + attribute \src "libresoc.v:157785.5-157785.29" switch \initial - attribute \src "libresoc.v:156153.9-156153.17" + attribute \src "libresoc.v:157785.9-157785.17" case 1'1 case end @@ -326047,56 +328544,56 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8378 1'0 + assign $1\q_int$next[0:0]$8426 1'0 case - assign $1\q_int$next[0:0]$8378 \$5 + assign $1\q_int$next[0:0]$8426 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8377 + update \q_int$next $0\q_int$next[0:0]$8425 end - connect \$9 $and$libresoc.v:156142$8367_Y - connect \$11 $or$libresoc.v:156143$8368_Y - connect \$13 $not$libresoc.v:156144$8369_Y - connect \$15 $or$libresoc.v:156145$8370_Y - connect \$1 $not$libresoc.v:156146$8371_Y - connect \$3 $and$libresoc.v:156147$8372_Y - connect \$5 $or$libresoc.v:156148$8373_Y - connect \$7 $not$libresoc.v:156149$8374_Y + connect \$9 $and$libresoc.v:157774$8415_Y + connect \$11 $or$libresoc.v:157775$8416_Y + connect \$13 $not$libresoc.v:157776$8417_Y + connect \$15 $or$libresoc.v:157777$8418_Y + connect \$1 $not$libresoc.v:157778$8419_Y + connect \$3 $and$libresoc.v:157779$8420_Y + connect \$5 $or$libresoc.v:157780$8421_Y + connect \$7 $not$libresoc.v:157781$8422_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156168.1-156226.10" +attribute \src "libresoc.v:157800.1-157858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:156169.7-156169.20" + attribute \src "libresoc.v:157801.7-157801.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156214.3-156222.6" - wire $0\q_int$next[0:0]$8391 - attribute \src "libresoc.v:156212.3-156213.27" + attribute \src "libresoc.v:157846.3-157854.6" + wire $0\q_int$next[0:0]$8439 + attribute \src "libresoc.v:157844.3-157845.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156214.3-156222.6" - wire $1\q_int$next[0:0]$8392 - attribute \src "libresoc.v:156191.7-156191.19" + attribute \src "libresoc.v:157846.3-157854.6" + wire $1\q_int$next[0:0]$8440 + attribute \src "libresoc.v:157823.7-157823.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156204.17-156204.96" - wire $and$libresoc.v:156204$8381_Y - attribute \src "libresoc.v:156209.17-156209.96" - wire $and$libresoc.v:156209$8386_Y - attribute \src "libresoc.v:156206.18-156206.93" - wire $not$libresoc.v:156206$8383_Y - attribute \src "libresoc.v:156208.17-156208.92" - wire $not$libresoc.v:156208$8385_Y - attribute \src "libresoc.v:156211.17-156211.92" - wire $not$libresoc.v:156211$8388_Y - attribute \src "libresoc.v:156205.18-156205.98" - wire $or$libresoc.v:156205$8382_Y - attribute \src "libresoc.v:156207.18-156207.99" - wire $or$libresoc.v:156207$8384_Y - attribute \src "libresoc.v:156210.17-156210.97" - wire $or$libresoc.v:156210$8387_Y + attribute \src "libresoc.v:157836.17-157836.96" + wire $and$libresoc.v:157836$8429_Y + attribute \src "libresoc.v:157841.17-157841.96" + wire $and$libresoc.v:157841$8434_Y + attribute \src "libresoc.v:157838.18-157838.93" + wire $not$libresoc.v:157838$8431_Y + attribute \src "libresoc.v:157840.17-157840.92" + wire $not$libresoc.v:157840$8433_Y + attribute \src "libresoc.v:157843.17-157843.92" + wire $not$libresoc.v:157843$8436_Y + attribute \src "libresoc.v:157837.18-157837.98" + wire $or$libresoc.v:157837$8430_Y + attribute \src "libresoc.v:157839.18-157839.99" + wire $or$libresoc.v:157839$8432_Y + attribute \src "libresoc.v:157842.17-157842.97" + wire $or$libresoc.v:157842$8435_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -326113,11 +328610,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156169.7-156169.15" + attribute \src "libresoc.v:157801.7-157801.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -326134,7 +328631,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156204$8381 + cell $and $and$libresoc.v:157836$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326142,10 +328639,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156204$8381_Y + connect \Y $and$libresoc.v:157836$8429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156209$8386 + cell $and $and$libresoc.v:157841$8434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326153,34 +328650,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156209$8386_Y + connect \Y $and$libresoc.v:157841$8434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156206$8383 + cell $not $not$libresoc.v:157838$8431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156206$8383_Y + connect \Y $not$libresoc.v:157838$8431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156208$8385 + cell $not $not$libresoc.v:157840$8433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156208$8385_Y + connect \Y $not$libresoc.v:157840$8433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156211$8388 + cell $not $not$libresoc.v:157843$8436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156211$8388_Y + connect \Y $not$libresoc.v:157843$8436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156205$8382 + cell $or $or$libresoc.v:157837$8430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326188,10 +328685,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156205$8382_Y + connect \Y $or$libresoc.v:157837$8430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156207$8384 + cell $or $or$libresoc.v:157839$8432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326199,10 +328696,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156207$8384_Y + connect \Y $or$libresoc.v:157839$8432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156210$8387 + cell $or $or$libresoc.v:157842$8435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326210,39 +328707,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156210$8387_Y + connect \Y $or$libresoc.v:157842$8435_Y end - attribute \src "libresoc.v:156169.7-156169.20" - process $proc$libresoc.v:156169$8393 + attribute \src "libresoc.v:157801.7-157801.20" + process $proc$libresoc.v:157801$8441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156191.7-156191.19" - process $proc$libresoc.v:156191$8394 + attribute \src "libresoc.v:157823.7-157823.19" + process $proc$libresoc.v:157823$8442 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156212.3-156213.27" - process $proc$libresoc.v:156212$8389 + attribute \src "libresoc.v:157844.3-157845.27" + process $proc$libresoc.v:157844$8437 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156214.3-156222.6" - process $proc$libresoc.v:156214$8390 + attribute \src "libresoc.v:157846.3-157854.6" + process $proc$libresoc.v:157846$8438 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8391 $1\q_int$next[0:0]$8392 - attribute \src "libresoc.v:156215.5-156215.29" + assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 + attribute \src "libresoc.v:157847.5-157847.29" switch \initial - attribute \src "libresoc.v:156215.9-156215.17" + attribute \src "libresoc.v:157847.9-157847.17" case 1'1 case end @@ -326251,56 +328748,56 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8392 1'0 + assign $1\q_int$next[0:0]$8440 1'0 case - assign $1\q_int$next[0:0]$8392 \$5 + assign $1\q_int$next[0:0]$8440 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8391 + update \q_int$next $0\q_int$next[0:0]$8439 end - connect \$9 $and$libresoc.v:156204$8381_Y - connect \$11 $or$libresoc.v:156205$8382_Y - connect \$13 $not$libresoc.v:156206$8383_Y - connect \$15 $or$libresoc.v:156207$8384_Y - connect \$1 $not$libresoc.v:156208$8385_Y - connect \$3 $and$libresoc.v:156209$8386_Y - connect \$5 $or$libresoc.v:156210$8387_Y - connect \$7 $not$libresoc.v:156211$8388_Y + connect \$9 $and$libresoc.v:157836$8429_Y + connect \$11 $or$libresoc.v:157837$8430_Y + connect \$13 $not$libresoc.v:157838$8431_Y + connect \$15 $or$libresoc.v:157839$8432_Y + connect \$1 $not$libresoc.v:157840$8433_Y + connect \$3 $and$libresoc.v:157841$8434_Y + connect \$5 $or$libresoc.v:157842$8435_Y + connect \$7 $not$libresoc.v:157843$8436_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156230.1-156288.10" +attribute \src "libresoc.v:157862.1-157920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:156231.7-156231.20" + attribute \src "libresoc.v:157863.7-157863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156276.3-156284.6" - wire $0\q_int$next[0:0]$8405 - attribute \src "libresoc.v:156274.3-156275.27" + attribute \src "libresoc.v:157908.3-157916.6" + wire $0\q_int$next[0:0]$8453 + attribute \src "libresoc.v:157906.3-157907.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:156276.3-156284.6" - wire $1\q_int$next[0:0]$8406 - attribute \src "libresoc.v:156253.7-156253.19" + attribute \src "libresoc.v:157908.3-157916.6" + wire $1\q_int$next[0:0]$8454 + attribute \src "libresoc.v:157885.7-157885.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:156266.17-156266.96" - wire $and$libresoc.v:156266$8395_Y - attribute \src "libresoc.v:156271.17-156271.96" - wire $and$libresoc.v:156271$8400_Y - attribute \src "libresoc.v:156268.18-156268.93" - wire $not$libresoc.v:156268$8397_Y - attribute \src "libresoc.v:156270.17-156270.92" - wire $not$libresoc.v:156270$8399_Y - attribute \src "libresoc.v:156273.17-156273.92" - wire $not$libresoc.v:156273$8402_Y - attribute \src "libresoc.v:156267.18-156267.98" - wire $or$libresoc.v:156267$8396_Y - attribute \src "libresoc.v:156269.18-156269.99" - wire $or$libresoc.v:156269$8398_Y - attribute \src "libresoc.v:156272.17-156272.97" - wire $or$libresoc.v:156272$8401_Y + attribute \src "libresoc.v:157898.17-157898.96" + wire $and$libresoc.v:157898$8443_Y + attribute \src "libresoc.v:157903.17-157903.96" + wire $and$libresoc.v:157903$8448_Y + attribute \src "libresoc.v:157900.18-157900.93" + wire $not$libresoc.v:157900$8445_Y + attribute \src "libresoc.v:157902.17-157902.92" + wire $not$libresoc.v:157902$8447_Y + attribute \src "libresoc.v:157905.17-157905.92" + wire $not$libresoc.v:157905$8450_Y + attribute \src "libresoc.v:157899.18-157899.98" + wire $or$libresoc.v:157899$8444_Y + attribute \src "libresoc.v:157901.18-157901.99" + wire $or$libresoc.v:157901$8446_Y + attribute \src "libresoc.v:157904.17-157904.97" + wire $or$libresoc.v:157904$8449_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -326317,11 +328814,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:156231.7-156231.15" + attribute \src "libresoc.v:157863.7-157863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -326338,7 +328835,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:156266$8395 + cell $and $and$libresoc.v:157898$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326346,10 +328843,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:156266$8395_Y + connect \Y $and$libresoc.v:157898$8443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:156271$8400 + cell $and $and$libresoc.v:157903$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326357,34 +328854,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:156271$8400_Y + connect \Y $and$libresoc.v:157903$8448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:156268$8397 + cell $not $not$libresoc.v:157900$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:156268$8397_Y + connect \Y $not$libresoc.v:157900$8445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:156270$8399 + cell $not $not$libresoc.v:157902$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156270$8399_Y + connect \Y $not$libresoc.v:157902$8447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:156273$8402 + cell $not $not$libresoc.v:157905$8450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:156273$8402_Y + connect \Y $not$libresoc.v:157905$8450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:156267$8396 + cell $or $or$libresoc.v:157899$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326392,10 +328889,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:156267$8396_Y + connect \Y $or$libresoc.v:157899$8444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:156269$8398 + cell $or $or$libresoc.v:157901$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326403,10 +328900,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:156269$8398_Y + connect \Y $or$libresoc.v:157901$8446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:156272$8401 + cell $or $or$libresoc.v:157904$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326414,39 +328911,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:156272$8401_Y + connect \Y $or$libresoc.v:157904$8449_Y end - attribute \src "libresoc.v:156231.7-156231.20" - process $proc$libresoc.v:156231$8407 + attribute \src "libresoc.v:157863.7-157863.20" + process $proc$libresoc.v:157863$8455 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156253.7-156253.19" - process $proc$libresoc.v:156253$8408 + attribute \src "libresoc.v:157885.7-157885.19" + process $proc$libresoc.v:157885$8456 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:156274.3-156275.27" - process $proc$libresoc.v:156274$8403 + attribute \src "libresoc.v:157906.3-157907.27" + process $proc$libresoc.v:157906$8451 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:156276.3-156284.6" - process $proc$libresoc.v:156276$8404 + attribute \src "libresoc.v:157908.3-157916.6" + process $proc$libresoc.v:157908$8452 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8405 $1\q_int$next[0:0]$8406 - attribute \src "libresoc.v:156277.5-156277.29" + assign $0\q_int$next[0:0]$8453 $1\q_int$next[0:0]$8454 + attribute \src "libresoc.v:157909.5-157909.29" switch \initial - attribute \src "libresoc.v:156277.9-156277.17" + attribute \src "libresoc.v:157909.9-157909.17" case 1'1 case end @@ -326455,90 +328952,90 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8406 1'0 + assign $1\q_int$next[0:0]$8454 1'0 case - assign $1\q_int$next[0:0]$8406 \$5 + assign $1\q_int$next[0:0]$8454 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8405 + update \q_int$next $0\q_int$next[0:0]$8453 end - connect \$9 $and$libresoc.v:156266$8395_Y - connect \$11 $or$libresoc.v:156267$8396_Y - connect \$13 $not$libresoc.v:156268$8397_Y - connect \$15 $or$libresoc.v:156269$8398_Y - connect \$1 $not$libresoc.v:156270$8399_Y - connect \$3 $and$libresoc.v:156271$8400_Y - connect \$5 $or$libresoc.v:156272$8401_Y - connect \$7 $not$libresoc.v:156273$8402_Y + connect \$9 $and$libresoc.v:157898$8443_Y + connect \$11 $or$libresoc.v:157899$8444_Y + connect \$13 $not$libresoc.v:157900$8445_Y + connect \$15 $or$libresoc.v:157901$8446_Y + connect \$1 $not$libresoc.v:157902$8447_Y + connect \$3 $and$libresoc.v:157903$8448_Y + connect \$5 $or$libresoc.v:157904$8449_Y + connect \$7 $not$libresoc.v:157905$8450_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:156292.1-156750.10" +attribute \src "libresoc.v:157924.1-158382.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:156669.3-156680.6" + attribute \src "libresoc.v:158301.3-158312.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:156293.7-156293.20" + attribute \src "libresoc.v:157925.7-157925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156681.3-156692.6" - wire width 65 $0\o$28[64:0]$8427 - attribute \src "libresoc.v:156657.3-156668.6" + attribute \src "libresoc.v:158313.3-158324.6" + wire width 65 $0\o$28[64:0]$8475 + attribute \src "libresoc.v:158289.3-158300.6" wire $0\so[0:0] - attribute \src "libresoc.v:156713.3-156722.6" - wire width 2 $0\xer_ov$24[1:0]$8434 - attribute \src "libresoc.v:156723.3-156732.6" + attribute \src "libresoc.v:158345.3-158354.6" + wire width 2 $0\xer_ov$24[1:0]$8482 + attribute \src "libresoc.v:158355.3-158364.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156693.3-156702.6" - wire $0\xer_so$25[0:0]$8430 - attribute \src "libresoc.v:156703.3-156712.6" + attribute \src "libresoc.v:158325.3-158334.6" + wire $0\xer_so$25[0:0]$8478 + attribute \src "libresoc.v:158335.3-158344.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156669.3-156680.6" + attribute \src "libresoc.v:158301.3-158312.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:156681.3-156692.6" - wire width 65 $1\o$28[64:0]$8428 - attribute \src "libresoc.v:156657.3-156668.6" + attribute \src "libresoc.v:158313.3-158324.6" + wire width 65 $1\o$28[64:0]$8476 + attribute \src "libresoc.v:158289.3-158300.6" wire $1\so[0:0] - attribute \src "libresoc.v:156713.3-156722.6" - wire width 2 $1\xer_ov$24[1:0]$8435 - attribute \src "libresoc.v:156723.3-156732.6" + attribute \src "libresoc.v:158345.3-158354.6" + wire width 2 $1\xer_ov$24[1:0]$8483 + attribute \src "libresoc.v:158355.3-158364.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156693.3-156702.6" - wire $1\xer_so$25[0:0]$8431 - attribute \src "libresoc.v:156703.3-156712.6" + attribute \src "libresoc.v:158325.3-158334.6" + wire $1\xer_so$25[0:0]$8479 + attribute \src "libresoc.v:158335.3-158344.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156644.18-156644.128" - wire $and$libresoc.v:156644$8409_Y - attribute \src "libresoc.v:156652.18-156652.112" - wire $and$libresoc.v:156652$8419_Y - attribute \src "libresoc.v:156655.18-156655.125" - wire $and$libresoc.v:156655$8422_Y - attribute \src "libresoc.v:156648.18-156648.123" - wire $eq$libresoc.v:156648$8415_Y - attribute \src "libresoc.v:156649.18-156649.123" - wire $eq$libresoc.v:156649$8416_Y - attribute \src "libresoc.v:156646.18-156646.103" - wire width 65 $extend$libresoc.v:156646$8411_Y - attribute \src "libresoc.v:156647.18-156647.101" - wire width 65 $extend$libresoc.v:156647$8413_Y - attribute \src "libresoc.v:156645.18-156645.100" - wire width 64 $not$libresoc.v:156645$8410_Y - attribute \src "libresoc.v:156651.18-156651.107" - wire $not$libresoc.v:156651$8418_Y - attribute \src "libresoc.v:156654.18-156654.107" - wire $not$libresoc.v:156654$8421_Y - attribute \src "libresoc.v:156653.18-156653.115" - wire $or$libresoc.v:156653$8420_Y - attribute \src "libresoc.v:156656.18-156656.112" - wire $or$libresoc.v:156656$8423_Y - attribute \src "libresoc.v:156646.18-156646.103" - wire width 65 $pos$libresoc.v:156646$8412_Y - attribute \src "libresoc.v:156647.18-156647.101" - wire width 65 $pos$libresoc.v:156647$8414_Y - attribute \src "libresoc.v:156650.18-156650.105" - wire $reduce_or$libresoc.v:156650$8417_Y + attribute \src "libresoc.v:158276.18-158276.128" + wire $and$libresoc.v:158276$8457_Y + attribute \src "libresoc.v:158284.18-158284.112" + wire $and$libresoc.v:158284$8467_Y + attribute \src "libresoc.v:158287.18-158287.125" + wire $and$libresoc.v:158287$8470_Y + attribute \src "libresoc.v:158280.18-158280.123" + wire $eq$libresoc.v:158280$8463_Y + attribute \src "libresoc.v:158281.18-158281.123" + wire $eq$libresoc.v:158281$8464_Y + attribute \src "libresoc.v:158278.18-158278.103" + wire width 65 $extend$libresoc.v:158278$8459_Y + attribute \src "libresoc.v:158279.18-158279.101" + wire width 65 $extend$libresoc.v:158279$8461_Y + attribute \src "libresoc.v:158277.18-158277.100" + wire width 64 $not$libresoc.v:158277$8458_Y + attribute \src "libresoc.v:158283.18-158283.107" + wire $not$libresoc.v:158283$8466_Y + attribute \src "libresoc.v:158286.18-158286.107" + wire $not$libresoc.v:158286$8469_Y + attribute \src "libresoc.v:158285.18-158285.115" + wire $or$libresoc.v:158285$8468_Y + attribute \src "libresoc.v:158288.18-158288.112" + wire $or$libresoc.v:158288$8471_Y + attribute \src "libresoc.v:158278.18-158278.103" + wire width 65 $pos$libresoc.v:158278$8460_Y + attribute \src "libresoc.v:158279.18-158279.101" + wire width 65 $pos$libresoc.v:158279$8462_Y + attribute \src "libresoc.v:158282.18-158282.105" + wire $reduce_or$libresoc.v:158282$8465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -326833,7 +329330,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:156293.7-156293.15" + attribute \src "libresoc.v:157925.7-157925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -326888,7 +329385,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:156644$8409 + cell $and $and$libresoc.v:158276$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326896,10 +329393,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:156644$8409_Y + connect \Y $and$libresoc.v:158276$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:156652$8419 + cell $and $and$libresoc.v:158284$8467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326907,10 +329404,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:156652$8419_Y + connect \Y $and$libresoc.v:158284$8467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:156655$8422 + cell $and $and$libresoc.v:158287$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326918,10 +329415,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:156655$8422_Y + connect \Y $and$libresoc.v:158287$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:156648$8415 + cell $eq $eq$libresoc.v:158280$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326929,10 +329426,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:156648$8415_Y + connect \Y $eq$libresoc.v:158280$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:156649$8416 + cell $eq $eq$libresoc.v:158281$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326940,50 +329437,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:156649$8416_Y + connect \Y $eq$libresoc.v:158281$8464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:156646$8411 + cell $pos $extend$libresoc.v:158278$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:156646$8411_Y + connect \Y $extend$libresoc.v:158278$8459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:156647$8413 + cell $pos $extend$libresoc.v:158279$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:156647$8413_Y + connect \Y $extend$libresoc.v:158279$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:156645$8410 + cell $not $not$libresoc.v:158277$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:156645$8410_Y + connect \Y $not$libresoc.v:158277$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:156651$8418 + cell $not $not$libresoc.v:158283$8466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:156651$8418_Y + connect \Y $not$libresoc.v:158283$8466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:156654$8421 + cell $not $not$libresoc.v:158286$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:156654$8421_Y + connect \Y $not$libresoc.v:158286$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:156653$8420 + cell $or $or$libresoc.v:158285$8468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326991,10 +329488,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:156653$8420_Y + connect \Y $or$libresoc.v:158285$8468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:156656$8423 + cell $or $or$libresoc.v:158288$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327002,47 +329499,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:156656$8423_Y + connect \Y $or$libresoc.v:158288$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:156646$8412 + cell $pos $pos$libresoc.v:158278$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156646$8411_Y - connect \Y $pos$libresoc.v:156646$8412_Y + connect \A $extend$libresoc.v:158278$8459_Y + connect \Y $pos$libresoc.v:158278$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:156647$8414 + cell $pos $pos$libresoc.v:158279$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:156647$8413_Y - connect \Y $pos$libresoc.v:156647$8414_Y + connect \A $extend$libresoc.v:158279$8461_Y + connect \Y $pos$libresoc.v:158279$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:156650$8417 + cell $reduce_or $reduce_or$libresoc.v:158282$8465 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:156650$8417_Y + connect \Y $reduce_or$libresoc.v:158282$8465_Y end - attribute \src "libresoc.v:156293.7-156293.20" - process $proc$libresoc.v:156293$8437 + attribute \src "libresoc.v:157925.7-157925.20" + process $proc$libresoc.v:157925$8485 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156657.3-156668.6" - process $proc$libresoc.v:156657$8424 + attribute \src "libresoc.v:158289.3-158300.6" + process $proc$libresoc.v:158289$8472 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:156658.5-156658.29" + attribute \src "libresoc.v:158290.5-158290.29" switch \initial - attribute \src "libresoc.v:156658.9-156658.17" + attribute \src "libresoc.v:158290.9-158290.17" case 1'1 case end @@ -327060,13 +329557,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:156669.3-156680.6" - process $proc$libresoc.v:156669$8425 + attribute \src "libresoc.v:158301.3-158312.6" + process $proc$libresoc.v:158301$8473 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:156670.5-156670.29" + attribute \src "libresoc.v:158302.5-158302.29" switch \initial - attribute \src "libresoc.v:156670.9-156670.17" + attribute \src "libresoc.v:158302.9-158302.17" case 1'1 case end @@ -327084,13 +329581,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:156681.3-156692.6" - process $proc$libresoc.v:156681$8426 + attribute \src "libresoc.v:158313.3-158324.6" + process $proc$libresoc.v:158313$8474 assign { } { } - assign $0\o$28[64:0]$8427 $1\o$28[64:0]$8428 - attribute \src "libresoc.v:156682.5-156682.29" + assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 + attribute \src "libresoc.v:158314.5-158314.29" switch \initial - attribute \src "libresoc.v:156682.9-156682.17" + attribute \src "libresoc.v:158314.9-158314.17" case 1'1 case end @@ -327099,23 +329596,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8428 \$29 + assign $1\o$28[64:0]$8476 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8428 \$33 + assign $1\o$28[64:0]$8476 \$33 end sync always - update \o$28 $0\o$28[64:0]$8427 + update \o$28 $0\o$28[64:0]$8475 end - attribute \src "libresoc.v:156693.3-156702.6" - process $proc$libresoc.v:156693$8429 + attribute \src "libresoc.v:158325.3-158334.6" + process $proc$libresoc.v:158325$8477 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8430 $1\xer_so$25[0:0]$8431 - attribute \src "libresoc.v:156694.5-156694.29" + assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 + attribute \src "libresoc.v:158326.5-158326.29" switch \initial - attribute \src "libresoc.v:156694.9-156694.17" + attribute \src "libresoc.v:158326.9-158326.17" case 1'1 case end @@ -327124,21 +329621,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8431 \$52 + assign $1\xer_so$25[0:0]$8479 \$52 case - assign $1\xer_so$25[0:0]$8431 1'0 + assign $1\xer_so$25[0:0]$8479 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8430 + update \xer_so$25 $0\xer_so$25[0:0]$8478 end - attribute \src "libresoc.v:156703.3-156712.6" - process $proc$libresoc.v:156703$8432 + attribute \src "libresoc.v:158335.3-158344.6" + process $proc$libresoc.v:158335$8480 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156704.5-156704.29" + attribute \src "libresoc.v:158336.5-158336.29" switch \initial - attribute \src "libresoc.v:156704.9-156704.17" + attribute \src "libresoc.v:158336.9-158336.17" case 1'1 case end @@ -327154,14 +329651,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156713.3-156722.6" - process $proc$libresoc.v:156713$8433 + attribute \src "libresoc.v:158345.3-158354.6" + process $proc$libresoc.v:158345$8481 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8434 $1\xer_ov$24[1:0]$8435 - attribute \src "libresoc.v:156714.5-156714.29" + assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 + attribute \src "libresoc.v:158346.5-158346.29" switch \initial - attribute \src "libresoc.v:156714.9-156714.17" + attribute \src "libresoc.v:158346.9-158346.17" case 1'1 case end @@ -327170,21 +329667,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8435 \xer_ov + assign $1\xer_ov$24[1:0]$8483 \xer_ov case - assign $1\xer_ov$24[1:0]$8435 2'00 + assign $1\xer_ov$24[1:0]$8483 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8434 + update \xer_ov$24 $0\xer_ov$24[1:0]$8482 end - attribute \src "libresoc.v:156723.3-156732.6" - process $proc$libresoc.v:156723$8436 + attribute \src "libresoc.v:158355.3-158364.6" + process $proc$libresoc.v:158355$8484 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156724.5-156724.29" + attribute \src "libresoc.v:158356.5-158356.29" switch \initial - attribute \src "libresoc.v:156724.9-156724.17" + attribute \src "libresoc.v:158356.9-158356.17" case 1'1 case end @@ -327200,19 +329697,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:156644$8409_Y - connect \$30 $not$libresoc.v:156645$8410_Y - connect \$29 $pos$libresoc.v:156646$8412_Y - connect \$33 $pos$libresoc.v:156647$8414_Y - connect \$35 $eq$libresoc.v:156648$8415_Y - connect \$37 $eq$libresoc.v:156649$8416_Y - connect \$39 $reduce_or$libresoc.v:156650$8417_Y - connect \$41 $not$libresoc.v:156651$8418_Y - connect \$43 $and$libresoc.v:156652$8419_Y - connect \$45 $or$libresoc.v:156653$8420_Y - connect \$47 $not$libresoc.v:156654$8421_Y - connect \$50 $and$libresoc.v:156655$8422_Y - connect \$52 $or$libresoc.v:156656$8423_Y + connect \$26 $and$libresoc.v:158276$8457_Y + connect \$30 $not$libresoc.v:158277$8458_Y + connect \$29 $pos$libresoc.v:158278$8460_Y + connect \$33 $pos$libresoc.v:158279$8462_Y + connect \$35 $eq$libresoc.v:158280$8463_Y + connect \$37 $eq$libresoc.v:158281$8464_Y + connect \$39 $reduce_or$libresoc.v:158282$8465_Y + connect \$41 $not$libresoc.v:158283$8466_Y + connect \$43 $and$libresoc.v:158284$8467_Y + connect \$45 $or$libresoc.v:158285$8468_Y + connect \$47 $not$libresoc.v:158286$8469_Y + connect \$50 $and$libresoc.v:158287$8470_Y + connect \$52 $or$libresoc.v:158288$8471_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -327231,61 +329728,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:156754.1-157155.10" +attribute \src "libresoc.v:158386.1-158787.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:157087.3-157098.6" + attribute \src "libresoc.v:158719.3-158730.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:156755.7-156755.20" + attribute \src "libresoc.v:158387.7-158387.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157075.3-157086.6" + attribute \src "libresoc.v:158707.3-158718.6" wire $0\so[0:0] - attribute \src "libresoc.v:157119.3-157128.6" - wire width 2 $0\xer_ov$17[1:0]$8457 - attribute \src "libresoc.v:157129.3-157138.6" + attribute \src "libresoc.v:158751.3-158760.6" + wire width 2 $0\xer_ov$17[1:0]$8505 + attribute \src "libresoc.v:158761.3-158770.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:157099.3-157108.6" - wire $0\xer_so$18[0:0]$8453 - attribute \src "libresoc.v:157109.3-157118.6" + attribute \src "libresoc.v:158731.3-158740.6" + wire $0\xer_so$18[0:0]$8501 + attribute \src "libresoc.v:158741.3-158750.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:157087.3-157098.6" + attribute \src "libresoc.v:158719.3-158730.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157075.3-157086.6" + attribute \src "libresoc.v:158707.3-158718.6" wire $1\so[0:0] - attribute \src "libresoc.v:157119.3-157128.6" - wire width 2 $1\xer_ov$17[1:0]$8458 - attribute \src "libresoc.v:157129.3-157138.6" + attribute \src "libresoc.v:158751.3-158760.6" + wire width 2 $1\xer_ov$17[1:0]$8506 + attribute \src "libresoc.v:158761.3-158770.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157099.3-157108.6" - wire $1\xer_so$18[0:0]$8454 - attribute \src "libresoc.v:157109.3-157118.6" + attribute \src "libresoc.v:158731.3-158740.6" + wire $1\xer_so$18[0:0]$8502 + attribute \src "libresoc.v:158741.3-158750.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157064.18-157064.128" - wire $and$libresoc.v:157064$8438_Y - attribute \src "libresoc.v:157070.18-157070.112" - wire $and$libresoc.v:157070$8445_Y - attribute \src "libresoc.v:157073.18-157073.125" - wire $and$libresoc.v:157073$8448_Y - attribute \src "libresoc.v:157066.18-157066.123" - wire $eq$libresoc.v:157066$8441_Y - attribute \src "libresoc.v:157067.18-157067.123" - wire $eq$libresoc.v:157067$8442_Y - attribute \src "libresoc.v:157065.18-157065.101" - wire width 65 $extend$libresoc.v:157065$8439_Y - attribute \src "libresoc.v:157069.18-157069.107" - wire $not$libresoc.v:157069$8444_Y - attribute \src "libresoc.v:157072.18-157072.107" - wire $not$libresoc.v:157072$8447_Y - attribute \src "libresoc.v:157071.18-157071.115" - wire $or$libresoc.v:157071$8446_Y - attribute \src "libresoc.v:157074.18-157074.112" - wire $or$libresoc.v:157074$8449_Y - attribute \src "libresoc.v:157065.18-157065.101" - wire width 65 $pos$libresoc.v:157065$8440_Y - attribute \src "libresoc.v:157068.18-157068.105" - wire $reduce_or$libresoc.v:157068$8443_Y + attribute \src "libresoc.v:158696.18-158696.128" + wire $and$libresoc.v:158696$8486_Y + attribute \src "libresoc.v:158702.18-158702.112" + wire $and$libresoc.v:158702$8493_Y + attribute \src "libresoc.v:158705.18-158705.125" + wire $and$libresoc.v:158705$8496_Y + attribute \src "libresoc.v:158698.18-158698.123" + wire $eq$libresoc.v:158698$8489_Y + attribute \src "libresoc.v:158699.18-158699.123" + wire $eq$libresoc.v:158699$8490_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $extend$libresoc.v:158697$8487_Y + attribute \src "libresoc.v:158701.18-158701.107" + wire $not$libresoc.v:158701$8492_Y + attribute \src "libresoc.v:158704.18-158704.107" + wire $not$libresoc.v:158704$8495_Y + attribute \src "libresoc.v:158703.18-158703.115" + wire $or$libresoc.v:158703$8494_Y + attribute \src "libresoc.v:158706.18-158706.112" + wire $or$libresoc.v:158706$8497_Y + attribute \src "libresoc.v:158697.18-158697.101" + wire width 65 $pos$libresoc.v:158697$8488_Y + attribute \src "libresoc.v:158700.18-158700.105" + wire $reduce_or$libresoc.v:158700$8491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -327316,7 +329813,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:156755.7-156755.15" + attribute \src "libresoc.v:158387.7-158387.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -327593,7 +330090,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:157064$8438 + cell $and $and$libresoc.v:158696$8486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327601,10 +330098,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:157064$8438_Y + connect \Y $and$libresoc.v:158696$8486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157070$8445 + cell $and $and$libresoc.v:158702$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327612,10 +330109,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:157070$8445_Y + connect \Y $and$libresoc.v:158702$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:157073$8448 + cell $and $and$libresoc.v:158705$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327623,10 +330120,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:157073$8448_Y + connect \Y $and$libresoc.v:158705$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157066$8441 + cell $eq $eq$libresoc.v:158698$8489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327634,10 +330131,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157066$8441_Y + connect \Y $eq$libresoc.v:158698$8489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157067$8442 + cell $eq $eq$libresoc.v:158699$8490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327645,34 +330142,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157067$8442_Y + connect \Y $eq$libresoc.v:158699$8490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157065$8439 + cell $pos $extend$libresoc.v:158697$8487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157065$8439_Y + connect \Y $extend$libresoc.v:158697$8487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157069$8444 + cell $not $not$libresoc.v:158701$8492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157069$8444_Y + connect \Y $not$libresoc.v:158701$8492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157072$8447 + cell $not $not$libresoc.v:158704$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157072$8447_Y + connect \Y $not$libresoc.v:158704$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157071$8446 + cell $or $or$libresoc.v:158703$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327680,10 +330177,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157071$8446_Y + connect \Y $or$libresoc.v:158703$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:157074$8449 + cell $or $or$libresoc.v:158706$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327691,39 +330188,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:157074$8449_Y + connect \Y $or$libresoc.v:158706$8497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157065$8440 + cell $pos $pos$libresoc.v:158697$8488 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157065$8439_Y - connect \Y $pos$libresoc.v:157065$8440_Y + connect \A $extend$libresoc.v:158697$8487_Y + connect \Y $pos$libresoc.v:158697$8488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157068$8443 + cell $reduce_or $reduce_or$libresoc.v:158700$8491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157068$8443_Y + connect \Y $reduce_or$libresoc.v:158700$8491_Y end - attribute \src "libresoc.v:156755.7-156755.20" - process $proc$libresoc.v:156755$8460 + attribute \src "libresoc.v:158387.7-158387.20" + process $proc$libresoc.v:158387$8508 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157075.3-157086.6" - process $proc$libresoc.v:157075$8450 + attribute \src "libresoc.v:158707.3-158718.6" + process $proc$libresoc.v:158707$8498 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:157076.5-157076.29" + attribute \src "libresoc.v:158708.5-158708.29" switch \initial - attribute \src "libresoc.v:157076.9-157076.17" + attribute \src "libresoc.v:158708.9-158708.17" case 1'1 case end @@ -327741,13 +330238,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:157087.3-157098.6" - process $proc$libresoc.v:157087$8451 + attribute \src "libresoc.v:158719.3-158730.6" + process $proc$libresoc.v:158719$8499 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157088.5-157088.29" + attribute \src "libresoc.v:158720.5-158720.29" switch \initial - attribute \src "libresoc.v:157088.9-157088.17" + attribute \src "libresoc.v:158720.9-158720.17" case 1'1 case end @@ -327765,14 +330262,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:157099.3-157108.6" - process $proc$libresoc.v:157099$8452 + attribute \src "libresoc.v:158731.3-158740.6" + process $proc$libresoc.v:158731$8500 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8453 $1\xer_so$18[0:0]$8454 - attribute \src "libresoc.v:157100.5-157100.29" + assign $0\xer_so$18[0:0]$8501 $1\xer_so$18[0:0]$8502 + attribute \src "libresoc.v:158732.5-158732.29" switch \initial - attribute \src "libresoc.v:157100.9-157100.17" + attribute \src "libresoc.v:158732.9-158732.17" case 1'1 case end @@ -327781,21 +330278,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8454 \$41 + assign $1\xer_so$18[0:0]$8502 \$41 case - assign $1\xer_so$18[0:0]$8454 1'0 + assign $1\xer_so$18[0:0]$8502 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8453 + update \xer_so$18 $0\xer_so$18[0:0]$8501 end - attribute \src "libresoc.v:157109.3-157118.6" - process $proc$libresoc.v:157109$8455 + attribute \src "libresoc.v:158741.3-158750.6" + process $proc$libresoc.v:158741$8503 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157110.5-157110.29" + attribute \src "libresoc.v:158742.5-158742.29" switch \initial - attribute \src "libresoc.v:157110.9-157110.17" + attribute \src "libresoc.v:158742.9-158742.17" case 1'1 case end @@ -327811,14 +330308,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:157119.3-157128.6" - process $proc$libresoc.v:157119$8456 + attribute \src "libresoc.v:158751.3-158760.6" + process $proc$libresoc.v:158751$8504 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8457 $1\xer_ov$17[1:0]$8458 - attribute \src "libresoc.v:157120.5-157120.29" + assign $0\xer_ov$17[1:0]$8505 $1\xer_ov$17[1:0]$8506 + attribute \src "libresoc.v:158752.5-158752.29" switch \initial - attribute \src "libresoc.v:157120.9-157120.17" + attribute \src "libresoc.v:158752.9-158752.17" case 1'1 case end @@ -327827,21 +330324,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8458 \xer_ov + assign $1\xer_ov$17[1:0]$8506 \xer_ov case - assign $1\xer_ov$17[1:0]$8458 2'00 + assign $1\xer_ov$17[1:0]$8506 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8457 + update \xer_ov$17 $0\xer_ov$17[1:0]$8505 end - attribute \src "libresoc.v:157129.3-157138.6" - process $proc$libresoc.v:157129$8459 + attribute \src "libresoc.v:158761.3-158770.6" + process $proc$libresoc.v:158761$8507 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157130.5-157130.29" + attribute \src "libresoc.v:158762.5-158762.29" switch \initial - attribute \src "libresoc.v:157130.9-157130.17" + attribute \src "libresoc.v:158762.9-158762.17" case 1'1 case end @@ -327857,17 +330354,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:157064$8438_Y - connect \$22 $pos$libresoc.v:157065$8440_Y - connect \$24 $eq$libresoc.v:157066$8441_Y - connect \$26 $eq$libresoc.v:157067$8442_Y - connect \$28 $reduce_or$libresoc.v:157068$8443_Y - connect \$30 $not$libresoc.v:157069$8444_Y - connect \$32 $and$libresoc.v:157070$8445_Y - connect \$34 $or$libresoc.v:157071$8446_Y - connect \$36 $not$libresoc.v:157072$8447_Y - connect \$39 $and$libresoc.v:157073$8448_Y - connect \$41 $or$libresoc.v:157074$8449_Y + connect \$19 $and$libresoc.v:158696$8486_Y + connect \$22 $pos$libresoc.v:158697$8488_Y + connect \$24 $eq$libresoc.v:158698$8489_Y + connect \$26 $eq$libresoc.v:158699$8490_Y + connect \$28 $reduce_or$libresoc.v:158700$8491_Y + connect \$30 $not$libresoc.v:158701$8492_Y + connect \$32 $and$libresoc.v:158702$8493_Y + connect \$34 $or$libresoc.v:158703$8494_Y + connect \$36 $not$libresoc.v:158704$8495_Y + connect \$39 $and$libresoc.v:158705$8496_Y + connect \$41 $or$libresoc.v:158706$8497_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -327885,35 +330382,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:157159.1-157513.10" +attribute \src "libresoc.v:158791.1-159145.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:157485.3-157496.6" + attribute \src "libresoc.v:159117.3-159128.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157160.7-157160.20" + attribute \src "libresoc.v:158792.7-158792.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157485.3-157496.6" + attribute \src "libresoc.v:159117.3-159128.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157482.18-157482.112" - wire $and$libresoc.v:157482$8467_Y - attribute \src "libresoc.v:157478.18-157478.122" - wire $eq$libresoc.v:157478$8463_Y - attribute \src "libresoc.v:157479.18-157479.122" - wire $eq$libresoc.v:157479$8464_Y - attribute \src "libresoc.v:157477.18-157477.101" - wire width 65 $extend$libresoc.v:157477$8461_Y - attribute \src "libresoc.v:157481.18-157481.107" - wire $not$libresoc.v:157481$8466_Y - attribute \src "libresoc.v:157484.18-157484.107" - wire $not$libresoc.v:157484$8469_Y - attribute \src "libresoc.v:157483.18-157483.115" - wire $or$libresoc.v:157483$8468_Y - attribute \src "libresoc.v:157477.18-157477.101" - wire width 65 $pos$libresoc.v:157477$8462_Y - attribute \src "libresoc.v:157480.18-157480.105" - wire $reduce_or$libresoc.v:157480$8465_Y + attribute \src "libresoc.v:159114.18-159114.112" + wire $and$libresoc.v:159114$8515_Y + attribute \src "libresoc.v:159110.18-159110.122" + wire $eq$libresoc.v:159110$8511_Y + attribute \src "libresoc.v:159111.18-159111.122" + wire $eq$libresoc.v:159111$8512_Y + attribute \src "libresoc.v:159109.18-159109.101" + wire width 65 $extend$libresoc.v:159109$8509_Y + attribute \src "libresoc.v:159113.18-159113.107" + wire $not$libresoc.v:159113$8514_Y + attribute \src "libresoc.v:159116.18-159116.107" + wire $not$libresoc.v:159116$8517_Y + attribute \src "libresoc.v:159115.18-159115.115" + wire $or$libresoc.v:159115$8516_Y + attribute \src "libresoc.v:159109.18-159109.101" + wire width 65 $pos$libresoc.v:159109$8510_Y + attribute \src "libresoc.v:159112.18-159112.105" + wire $reduce_or$libresoc.v:159112$8513_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -327938,7 +330435,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:157160.7-157160.15" + attribute \src "libresoc.v:158792.7-158792.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328233,7 +330730,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157482$8467 + cell $and $and$libresoc.v:159114$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328241,10 +330738,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:157482$8467_Y + connect \Y $and$libresoc.v:159114$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157478$8463 + cell $eq $eq$libresoc.v:159110$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328252,10 +330749,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157478$8463_Y + connect \Y $eq$libresoc.v:159110$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157479$8464 + cell $eq $eq$libresoc.v:159111$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328263,34 +330760,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157479$8464_Y + connect \Y $eq$libresoc.v:159111$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157477$8461 + cell $pos $extend$libresoc.v:159109$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157477$8461_Y + connect \Y $extend$libresoc.v:159109$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157481$8466 + cell $not $not$libresoc.v:159113$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157481$8466_Y + connect \Y $not$libresoc.v:159113$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157484$8469 + cell $not $not$libresoc.v:159116$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157484$8469_Y + connect \Y $not$libresoc.v:159116$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157483$8468 + cell $or $or$libresoc.v:159115$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328298,39 +330795,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157483$8468_Y + connect \Y $or$libresoc.v:159115$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157477$8462 + cell $pos $pos$libresoc.v:159109$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157477$8461_Y - connect \Y $pos$libresoc.v:157477$8462_Y + connect \A $extend$libresoc.v:159109$8509_Y + connect \Y $pos$libresoc.v:159109$8510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157480$8465 + cell $reduce_or $reduce_or$libresoc.v:159112$8513 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157480$8465_Y + connect \Y $reduce_or$libresoc.v:159112$8513_Y end - attribute \src "libresoc.v:157160.7-157160.20" - process $proc$libresoc.v:157160$8471 + attribute \src "libresoc.v:158792.7-158792.20" + process $proc$libresoc.v:158792$8519 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157485.3-157496.6" - process $proc$libresoc.v:157485$8470 + attribute \src "libresoc.v:159117.3-159128.6" + process $proc$libresoc.v:159117$8518 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157486.5-157486.29" + attribute \src "libresoc.v:159118.5-159118.29" switch \initial - attribute \src "libresoc.v:157486.9-157486.17" + attribute \src "libresoc.v:159118.9-159118.17" case 1'1 case end @@ -328348,14 +330845,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:157477$8462_Y - connect \$26 $eq$libresoc.v:157478$8463_Y - connect \$28 $eq$libresoc.v:157479$8464_Y - connect \$30 $reduce_or$libresoc.v:157480$8465_Y - connect \$32 $not$libresoc.v:157481$8466_Y - connect \$34 $and$libresoc.v:157482$8467_Y - connect \$36 $or$libresoc.v:157483$8468_Y - connect \$38 $not$libresoc.v:157484$8469_Y + connect \$24 $pos$libresoc.v:159109$8510_Y + connect \$26 $eq$libresoc.v:159110$8511_Y + connect \$28 $eq$libresoc.v:159111$8512_Y + connect \$30 $reduce_or$libresoc.v:159112$8513_Y + connect \$32 $not$libresoc.v:159113$8514_Y + connect \$34 $and$libresoc.v:159114$8515_Y + connect \$36 $or$libresoc.v:159115$8516_Y + connect \$38 $not$libresoc.v:159116$8517_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -328373,45 +330870,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:157517.1-157884.10" +attribute \src "libresoc.v:159149.1-159516.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:157859.3-157870.6" + attribute \src "libresoc.v:159491.3-159502.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157518.7-157518.20" + attribute \src "libresoc.v:159150.7-159150.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157847.3-157858.6" - wire width 65 $0\o$23[64:0]$8485 - attribute \src "libresoc.v:157859.3-157870.6" + attribute \src "libresoc.v:159479.3-159490.6" + wire width 65 $0\o$23[64:0]$8533 + attribute \src "libresoc.v:159491.3-159502.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:157847.3-157858.6" - wire width 65 $1\o$23[64:0]$8486 - attribute \src "libresoc.v:157844.18-157844.112" - wire $and$libresoc.v:157844$8481_Y - attribute \src "libresoc.v:157840.18-157840.127" - wire $eq$libresoc.v:157840$8477_Y - attribute \src "libresoc.v:157841.18-157841.127" - wire $eq$libresoc.v:157841$8478_Y - attribute \src "libresoc.v:157838.18-157838.103" - wire width 65 $extend$libresoc.v:157838$8473_Y - attribute \src "libresoc.v:157839.18-157839.101" - wire width 65 $extend$libresoc.v:157839$8475_Y - attribute \src "libresoc.v:157837.18-157837.100" - wire width 64 $not$libresoc.v:157837$8472_Y - attribute \src "libresoc.v:157843.18-157843.107" - wire $not$libresoc.v:157843$8480_Y - attribute \src "libresoc.v:157846.18-157846.107" - wire $not$libresoc.v:157846$8483_Y - attribute \src "libresoc.v:157845.18-157845.115" - wire $or$libresoc.v:157845$8482_Y - attribute \src "libresoc.v:157838.18-157838.103" - wire width 65 $pos$libresoc.v:157838$8474_Y - attribute \src "libresoc.v:157839.18-157839.101" - wire width 65 $pos$libresoc.v:157839$8476_Y - attribute \src "libresoc.v:157842.18-157842.105" - wire $reduce_or$libresoc.v:157842$8479_Y + attribute \src "libresoc.v:159479.3-159490.6" + wire width 65 $1\o$23[64:0]$8534 + attribute \src "libresoc.v:159476.18-159476.112" + wire $and$libresoc.v:159476$8529_Y + attribute \src "libresoc.v:159472.18-159472.127" + wire $eq$libresoc.v:159472$8525_Y + attribute \src "libresoc.v:159473.18-159473.127" + wire $eq$libresoc.v:159473$8526_Y + attribute \src "libresoc.v:159470.18-159470.103" + wire width 65 $extend$libresoc.v:159470$8521_Y + attribute \src "libresoc.v:159471.18-159471.101" + wire width 65 $extend$libresoc.v:159471$8523_Y + attribute \src "libresoc.v:159469.18-159469.100" + wire width 64 $not$libresoc.v:159469$8520_Y + attribute \src "libresoc.v:159475.18-159475.107" + wire $not$libresoc.v:159475$8528_Y + attribute \src "libresoc.v:159478.18-159478.107" + wire $not$libresoc.v:159478$8531_Y + attribute \src "libresoc.v:159477.18-159477.115" + wire $or$libresoc.v:159477$8530_Y + attribute \src "libresoc.v:159470.18-159470.103" + wire width 65 $pos$libresoc.v:159470$8522_Y + attribute \src "libresoc.v:159471.18-159471.101" + wire width 65 $pos$libresoc.v:159471$8524_Y + attribute \src "libresoc.v:159474.18-159474.105" + wire $reduce_or$libresoc.v:159474$8527_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -328440,7 +330937,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:157518.7-157518.15" + attribute \src "libresoc.v:159150.7-159150.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328733,7 +331230,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:157844$8481 + cell $and $and$libresoc.v:159476$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328741,10 +331238,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:157844$8481_Y + connect \Y $and$libresoc.v:159476$8529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:157840$8477 + cell $eq $eq$libresoc.v:159472$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328752,10 +331249,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:157840$8477_Y + connect \Y $eq$libresoc.v:159472$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:157841$8478 + cell $eq $eq$libresoc.v:159473$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328763,50 +331260,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:157841$8478_Y + connect \Y $eq$libresoc.v:159473$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:157838$8473 + cell $pos $extend$libresoc.v:159470$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:157838$8473_Y + connect \Y $extend$libresoc.v:159470$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:157839$8475 + cell $pos $extend$libresoc.v:159471$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:157839$8475_Y + connect \Y $extend$libresoc.v:159471$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:157837$8472 + cell $not $not$libresoc.v:159469$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:157837$8472_Y + connect \Y $not$libresoc.v:159469$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:157843$8480 + cell $not $not$libresoc.v:159475$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:157843$8480_Y + connect \Y $not$libresoc.v:159475$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:157846$8483 + cell $not $not$libresoc.v:159478$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:157846$8483_Y + connect \Y $not$libresoc.v:159478$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:157845$8482 + cell $or $or$libresoc.v:159477$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328814,47 +331311,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:157845$8482_Y + connect \Y $or$libresoc.v:159477$8530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:157838$8474 + cell $pos $pos$libresoc.v:159470$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157838$8473_Y - connect \Y $pos$libresoc.v:157838$8474_Y + connect \A $extend$libresoc.v:159470$8521_Y + connect \Y $pos$libresoc.v:159470$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:157839$8476 + cell $pos $pos$libresoc.v:159471$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:157839$8475_Y - connect \Y $pos$libresoc.v:157839$8476_Y + connect \A $extend$libresoc.v:159471$8523_Y + connect \Y $pos$libresoc.v:159471$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:157842$8479 + cell $reduce_or $reduce_or$libresoc.v:159474$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:157842$8479_Y + connect \Y $reduce_or$libresoc.v:159474$8527_Y end - attribute \src "libresoc.v:157518.7-157518.20" - process $proc$libresoc.v:157518$8488 + attribute \src "libresoc.v:159150.7-159150.20" + process $proc$libresoc.v:159150$8536 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157847.3-157858.6" - process $proc$libresoc.v:157847$8484 + attribute \src "libresoc.v:159479.3-159490.6" + process $proc$libresoc.v:159479$8532 assign { } { } - assign $0\o$23[64:0]$8485 $1\o$23[64:0]$8486 - attribute \src "libresoc.v:157848.5-157848.29" + assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 + attribute \src "libresoc.v:159480.5-159480.29" switch \initial - attribute \src "libresoc.v:157848.9-157848.17" + attribute \src "libresoc.v:159480.9-159480.17" case 1'1 case end @@ -328863,22 +331360,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8486 \$24 + assign $1\o$23[64:0]$8534 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8486 \$28 + assign $1\o$23[64:0]$8534 \$28 end sync always - update \o$23 $0\o$23[64:0]$8485 + update \o$23 $0\o$23[64:0]$8533 end - attribute \src "libresoc.v:157859.3-157870.6" - process $proc$libresoc.v:157859$8487 + attribute \src "libresoc.v:159491.3-159502.6" + process $proc$libresoc.v:159491$8535 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:157860.5-157860.29" + attribute \src "libresoc.v:159492.5-159492.29" switch \initial - attribute \src "libresoc.v:157860.9-157860.17" + attribute \src "libresoc.v:159492.9-159492.17" case 1'1 case end @@ -328896,16 +331393,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:157837$8472_Y - connect \$24 $pos$libresoc.v:157838$8474_Y - connect \$28 $pos$libresoc.v:157839$8476_Y - connect \$30 $eq$libresoc.v:157840$8477_Y - connect \$32 $eq$libresoc.v:157841$8478_Y - connect \$34 $reduce_or$libresoc.v:157842$8479_Y - connect \$36 $not$libresoc.v:157843$8480_Y - connect \$38 $and$libresoc.v:157844$8481_Y - connect \$40 $or$libresoc.v:157845$8482_Y - connect \$42 $not$libresoc.v:157846$8483_Y + connect \$25 $not$libresoc.v:159469$8520_Y + connect \$24 $pos$libresoc.v:159470$8522_Y + connect \$28 $pos$libresoc.v:159471$8524_Y + connect \$30 $eq$libresoc.v:159472$8525_Y + connect \$32 $eq$libresoc.v:159473$8526_Y + connect \$34 $reduce_or$libresoc.v:159474$8527_Y + connect \$36 $not$libresoc.v:159475$8528_Y + connect \$38 $and$libresoc.v:159476$8529_Y + connect \$40 $or$libresoc.v:159477$8530_Y + connect \$42 $not$libresoc.v:159478$8531_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -328920,71 +331417,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:157888.1-158338.10" +attribute \src "libresoc.v:159520.1-159970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:158259.3-158270.6" + attribute \src "libresoc.v:159891.3-159902.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157889.7-157889.20" + attribute \src "libresoc.v:159521.7-159521.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158271.3-158282.6" - wire width 65 $0\o$27[64:0]$8507 - attribute \src "libresoc.v:158247.3-158258.6" + attribute \src "libresoc.v:159903.3-159914.6" + wire width 65 $0\o$27[64:0]$8555 + attribute \src "libresoc.v:159879.3-159890.6" wire $0\so[0:0] - attribute \src "libresoc.v:158303.3-158312.6" - wire width 2 $0\xer_ov$23[1:0]$8514 - attribute \src "libresoc.v:158313.3-158322.6" + attribute \src "libresoc.v:159935.3-159944.6" + wire width 2 $0\xer_ov$23[1:0]$8562 + attribute \src "libresoc.v:159945.3-159954.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158283.3-158292.6" - wire $0\xer_so$24[0:0]$8510 - attribute \src "libresoc.v:158293.3-158302.6" + attribute \src "libresoc.v:159915.3-159924.6" + wire $0\xer_so$24[0:0]$8558 + attribute \src "libresoc.v:159925.3-159934.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158259.3-158270.6" + attribute \src "libresoc.v:159891.3-159902.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158271.3-158282.6" - wire width 65 $1\o$27[64:0]$8508 - attribute \src "libresoc.v:158247.3-158258.6" + attribute \src "libresoc.v:159903.3-159914.6" + wire width 65 $1\o$27[64:0]$8556 + attribute \src "libresoc.v:159879.3-159890.6" wire $1\so[0:0] - attribute \src "libresoc.v:158303.3-158312.6" - wire width 2 $1\xer_ov$23[1:0]$8515 - attribute \src "libresoc.v:158313.3-158322.6" + attribute \src "libresoc.v:159935.3-159944.6" + wire width 2 $1\xer_ov$23[1:0]$8563 + attribute \src "libresoc.v:159945.3-159954.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158283.3-158292.6" - wire $1\xer_so$24[0:0]$8511 - attribute \src "libresoc.v:158293.3-158302.6" + attribute \src "libresoc.v:159915.3-159924.6" + wire $1\xer_so$24[0:0]$8559 + attribute \src "libresoc.v:159925.3-159934.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158234.18-158234.136" - wire $and$libresoc.v:158234$8489_Y - attribute \src "libresoc.v:158242.18-158242.112" - wire $and$libresoc.v:158242$8499_Y - attribute \src "libresoc.v:158245.18-158245.133" - wire $and$libresoc.v:158245$8502_Y - attribute \src "libresoc.v:158238.18-158238.127" - wire $eq$libresoc.v:158238$8495_Y - attribute \src "libresoc.v:158239.18-158239.127" - wire $eq$libresoc.v:158239$8496_Y - attribute \src "libresoc.v:158236.18-158236.103" - wire width 65 $extend$libresoc.v:158236$8491_Y - attribute \src "libresoc.v:158237.18-158237.101" - wire width 65 $extend$libresoc.v:158237$8493_Y - attribute \src "libresoc.v:158235.18-158235.100" - wire width 64 $not$libresoc.v:158235$8490_Y - attribute \src "libresoc.v:158241.18-158241.107" - wire $not$libresoc.v:158241$8498_Y - attribute \src "libresoc.v:158244.18-158244.107" - wire $not$libresoc.v:158244$8501_Y - attribute \src "libresoc.v:158243.18-158243.115" - wire $or$libresoc.v:158243$8500_Y - attribute \src "libresoc.v:158246.18-158246.112" - wire $or$libresoc.v:158246$8503_Y - attribute \src "libresoc.v:158236.18-158236.103" - wire width 65 $pos$libresoc.v:158236$8492_Y - attribute \src "libresoc.v:158237.18-158237.101" - wire width 65 $pos$libresoc.v:158237$8494_Y - attribute \src "libresoc.v:158240.18-158240.105" - wire $reduce_or$libresoc.v:158240$8497_Y + attribute \src "libresoc.v:159866.18-159866.136" + wire $and$libresoc.v:159866$8537_Y + attribute \src "libresoc.v:159874.18-159874.112" + wire $and$libresoc.v:159874$8547_Y + attribute \src "libresoc.v:159877.18-159877.133" + wire $and$libresoc.v:159877$8550_Y + attribute \src "libresoc.v:159870.18-159870.127" + wire $eq$libresoc.v:159870$8543_Y + attribute \src "libresoc.v:159871.18-159871.127" + wire $eq$libresoc.v:159871$8544_Y + attribute \src "libresoc.v:159868.18-159868.103" + wire width 65 $extend$libresoc.v:159868$8539_Y + attribute \src "libresoc.v:159869.18-159869.101" + wire width 65 $extend$libresoc.v:159869$8541_Y + attribute \src "libresoc.v:159867.18-159867.100" + wire width 64 $not$libresoc.v:159867$8538_Y + attribute \src "libresoc.v:159873.18-159873.107" + wire $not$libresoc.v:159873$8546_Y + attribute \src "libresoc.v:159876.18-159876.107" + wire $not$libresoc.v:159876$8549_Y + attribute \src "libresoc.v:159875.18-159875.115" + wire $or$libresoc.v:159875$8548_Y + attribute \src "libresoc.v:159878.18-159878.112" + wire $or$libresoc.v:159878$8551_Y + attribute \src "libresoc.v:159868.18-159868.103" + wire width 65 $pos$libresoc.v:159868$8540_Y + attribute \src "libresoc.v:159869.18-159869.101" + wire width 65 $pos$libresoc.v:159869$8542_Y + attribute \src "libresoc.v:159872.18-159872.105" + wire $reduce_or$libresoc.v:159872$8545_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -329019,7 +331516,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:157889.7-157889.15" + attribute \src "libresoc.v:159521.7-159521.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -329328,7 +331825,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158234$8489 + cell $and $and$libresoc.v:159866$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329336,10 +331833,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:158234$8489_Y + connect \Y $and$libresoc.v:159866$8537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158242$8499 + cell $and $and$libresoc.v:159874$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329347,10 +331844,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:158242$8499_Y + connect \Y $and$libresoc.v:159874$8547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158245$8502 + cell $and $and$libresoc.v:159877$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329358,10 +331855,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:158245$8502_Y + connect \Y $and$libresoc.v:159877$8550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158238$8495 + cell $eq $eq$libresoc.v:159870$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329369,10 +331866,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158238$8495_Y + connect \Y $eq$libresoc.v:159870$8543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158239$8496 + cell $eq $eq$libresoc.v:159871$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329380,50 +331877,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158239$8496_Y + connect \Y $eq$libresoc.v:159871$8544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:158236$8491 + cell $pos $extend$libresoc.v:159868$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:158236$8491_Y + connect \Y $extend$libresoc.v:159868$8539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158237$8493 + cell $pos $extend$libresoc.v:159869$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158237$8493_Y + connect \Y $extend$libresoc.v:159869$8541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:158235$8490 + cell $not $not$libresoc.v:159867$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:158235$8490_Y + connect \Y $not$libresoc.v:159867$8538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158241$8498 + cell $not $not$libresoc.v:159873$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158241$8498_Y + connect \Y $not$libresoc.v:159873$8546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158244$8501 + cell $not $not$libresoc.v:159876$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158244$8501_Y + connect \Y $not$libresoc.v:159876$8549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158243$8500 + cell $or $or$libresoc.v:159875$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329431,10 +331928,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158243$8500_Y + connect \Y $or$libresoc.v:159875$8548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158246$8503 + cell $or $or$libresoc.v:159878$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329442,47 +331939,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158246$8503_Y + connect \Y $or$libresoc.v:159878$8551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:158236$8492 + cell $pos $pos$libresoc.v:159868$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158236$8491_Y - connect \Y $pos$libresoc.v:158236$8492_Y + connect \A $extend$libresoc.v:159868$8539_Y + connect \Y $pos$libresoc.v:159868$8540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158237$8494 + cell $pos $pos$libresoc.v:159869$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158237$8493_Y - connect \Y $pos$libresoc.v:158237$8494_Y + connect \A $extend$libresoc.v:159869$8541_Y + connect \Y $pos$libresoc.v:159869$8542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158240$8497 + cell $reduce_or $reduce_or$libresoc.v:159872$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158240$8497_Y + connect \Y $reduce_or$libresoc.v:159872$8545_Y end - attribute \src "libresoc.v:157889.7-157889.20" - process $proc$libresoc.v:157889$8517 + attribute \src "libresoc.v:159521.7-159521.20" + process $proc$libresoc.v:159521$8565 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158247.3-158258.6" - process $proc$libresoc.v:158247$8504 + attribute \src "libresoc.v:159879.3-159890.6" + process $proc$libresoc.v:159879$8552 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158248.5-158248.29" + attribute \src "libresoc.v:159880.5-159880.29" switch \initial - attribute \src "libresoc.v:158248.9-158248.17" + attribute \src "libresoc.v:159880.9-159880.17" case 1'1 case end @@ -329500,13 +331997,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158259.3-158270.6" - process $proc$libresoc.v:158259$8505 + attribute \src "libresoc.v:159891.3-159902.6" + process $proc$libresoc.v:159891$8553 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158260.5-158260.29" + attribute \src "libresoc.v:159892.5-159892.29" switch \initial - attribute \src "libresoc.v:158260.9-158260.17" + attribute \src "libresoc.v:159892.9-159892.17" case 1'1 case end @@ -329524,13 +332021,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158271.3-158282.6" - process $proc$libresoc.v:158271$8506 + attribute \src "libresoc.v:159903.3-159914.6" + process $proc$libresoc.v:159903$8554 assign { } { } - assign $0\o$27[64:0]$8507 $1\o$27[64:0]$8508 - attribute \src "libresoc.v:158272.5-158272.29" + assign $0\o$27[64:0]$8555 $1\o$27[64:0]$8556 + attribute \src "libresoc.v:159904.5-159904.29" switch \initial - attribute \src "libresoc.v:158272.9-158272.17" + attribute \src "libresoc.v:159904.9-159904.17" case 1'1 case end @@ -329539,23 +332036,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8508 \$28 + assign $1\o$27[64:0]$8556 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8508 \$32 + assign $1\o$27[64:0]$8556 \$32 end sync always - update \o$27 $0\o$27[64:0]$8507 + update \o$27 $0\o$27[64:0]$8555 end - attribute \src "libresoc.v:158283.3-158292.6" - process $proc$libresoc.v:158283$8509 + attribute \src "libresoc.v:159915.3-159924.6" + process $proc$libresoc.v:159915$8557 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8510 $1\xer_so$24[0:0]$8511 - attribute \src "libresoc.v:158284.5-158284.29" + assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 + attribute \src "libresoc.v:159916.5-159916.29" switch \initial - attribute \src "libresoc.v:158284.9-158284.17" + attribute \src "libresoc.v:159916.9-159916.17" case 1'1 case end @@ -329564,21 +332061,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8511 \$51 + assign $1\xer_so$24[0:0]$8559 \$51 case - assign $1\xer_so$24[0:0]$8511 1'0 + assign $1\xer_so$24[0:0]$8559 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8510 + update \xer_so$24 $0\xer_so$24[0:0]$8558 end - attribute \src "libresoc.v:158293.3-158302.6" - process $proc$libresoc.v:158293$8512 + attribute \src "libresoc.v:159925.3-159934.6" + process $proc$libresoc.v:159925$8560 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158294.5-158294.29" + attribute \src "libresoc.v:159926.5-159926.29" switch \initial - attribute \src "libresoc.v:158294.9-158294.17" + attribute \src "libresoc.v:159926.9-159926.17" case 1'1 case end @@ -329594,14 +332091,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158303.3-158312.6" - process $proc$libresoc.v:158303$8513 + attribute \src "libresoc.v:159935.3-159944.6" + process $proc$libresoc.v:159935$8561 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8514 $1\xer_ov$23[1:0]$8515 - attribute \src "libresoc.v:158304.5-158304.29" + assign $0\xer_ov$23[1:0]$8562 $1\xer_ov$23[1:0]$8563 + attribute \src "libresoc.v:159936.5-159936.29" switch \initial - attribute \src "libresoc.v:158304.9-158304.17" + attribute \src "libresoc.v:159936.9-159936.17" case 1'1 case end @@ -329610,21 +332107,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8515 \xer_ov + assign $1\xer_ov$23[1:0]$8563 \xer_ov case - assign $1\xer_ov$23[1:0]$8515 2'00 + assign $1\xer_ov$23[1:0]$8563 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8514 + update \xer_ov$23 $0\xer_ov$23[1:0]$8562 end - attribute \src "libresoc.v:158313.3-158322.6" - process $proc$libresoc.v:158313$8516 + attribute \src "libresoc.v:159945.3-159954.6" + process $proc$libresoc.v:159945$8564 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158314.5-158314.29" + attribute \src "libresoc.v:159946.5-159946.29" switch \initial - attribute \src "libresoc.v:158314.9-158314.17" + attribute \src "libresoc.v:159946.9-159946.17" case 1'1 case end @@ -329640,19 +332137,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:158234$8489_Y - connect \$29 $not$libresoc.v:158235$8490_Y - connect \$28 $pos$libresoc.v:158236$8492_Y - connect \$32 $pos$libresoc.v:158237$8494_Y - connect \$34 $eq$libresoc.v:158238$8495_Y - connect \$36 $eq$libresoc.v:158239$8496_Y - connect \$38 $reduce_or$libresoc.v:158240$8497_Y - connect \$40 $not$libresoc.v:158241$8498_Y - connect \$42 $and$libresoc.v:158242$8499_Y - connect \$44 $or$libresoc.v:158243$8500_Y - connect \$46 $not$libresoc.v:158244$8501_Y - connect \$49 $and$libresoc.v:158245$8502_Y - connect \$51 $or$libresoc.v:158246$8503_Y + connect \$25 $and$libresoc.v:159866$8537_Y + connect \$29 $not$libresoc.v:159867$8538_Y + connect \$28 $pos$libresoc.v:159868$8540_Y + connect \$32 $pos$libresoc.v:159869$8542_Y + connect \$34 $eq$libresoc.v:159870$8543_Y + connect \$36 $eq$libresoc.v:159871$8544_Y + connect \$38 $reduce_or$libresoc.v:159872$8545_Y + connect \$40 $not$libresoc.v:159873$8546_Y + connect \$42 $and$libresoc.v:159874$8547_Y + connect \$44 $or$libresoc.v:159875$8548_Y + connect \$46 $not$libresoc.v:159876$8549_Y + connect \$49 $and$libresoc.v:159877$8550_Y + connect \$51 $or$libresoc.v:159878$8551_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -329669,93 +332166,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:158342.1-158824.10" +attribute \src "libresoc.v:159974.1-160456.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:158343.7-158343.20" + attribute \src "libresoc.v:159975.7-159975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $0\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $1\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $2\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:158777.3-158810.6" + attribute \src "libresoc.v:160409.3-160442.6" wire $3\ov[0:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:158705.3-158776.6" + attribute \src "libresoc.v:160337.3-160408.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:158696.18-158696.122" - wire $and$libresoc.v:158696$8531_Y - attribute \src "libresoc.v:158688.18-158688.109" - wire width 65 $extend$libresoc.v:158688$8519_Y - attribute \src "libresoc.v:158689.18-158689.100" - wire width 65 $extend$libresoc.v:158689$8521_Y - attribute \src "libresoc.v:158691.18-158691.113" - wire width 65 $extend$libresoc.v:158691$8524_Y - attribute \src "libresoc.v:158692.18-158692.104" - wire width 65 $extend$libresoc.v:158692$8526_Y - attribute \src "libresoc.v:158700.18-158700.114" - wire width 64 $extend$libresoc.v:158700$8535_Y - attribute \src "libresoc.v:158701.18-158701.114" - wire width 64 $extend$libresoc.v:158701$8537_Y - attribute \src "libresoc.v:158702.18-158702.114" - wire width 64 $extend$libresoc.v:158702$8539_Y - attribute \src "libresoc.v:158703.18-158703.114" - wire width 64 $extend$libresoc.v:158703$8541_Y - attribute \src "libresoc.v:158704.18-158704.115" - wire width 64 $extend$libresoc.v:158704$8543_Y - attribute \src "libresoc.v:158697.18-158697.128" - wire $ne$libresoc.v:158697$8532_Y - attribute \src "libresoc.v:158688.18-158688.109" - wire width 65 $neg$libresoc.v:158688$8520_Y - attribute \src "libresoc.v:158691.18-158691.113" - wire width 65 $neg$libresoc.v:158691$8525_Y - attribute \src "libresoc.v:158694.18-158694.116" - wire $not$libresoc.v:158694$8529_Y - attribute \src "libresoc.v:158699.18-158699.99" - wire $not$libresoc.v:158699$8534_Y - attribute \src "libresoc.v:158689.18-158689.100" - wire width 65 $pos$libresoc.v:158689$8522_Y - attribute \src "libresoc.v:158692.18-158692.104" - wire width 65 $pos$libresoc.v:158692$8527_Y - attribute \src "libresoc.v:158698.18-158698.118" - wire width 64 $pos$libresoc.v:158698$8533_Y - attribute \src "libresoc.v:158700.18-158700.114" - wire width 64 $pos$libresoc.v:158700$8536_Y - attribute \src "libresoc.v:158701.18-158701.114" - wire width 64 $pos$libresoc.v:158701$8538_Y - attribute \src "libresoc.v:158702.18-158702.114" - wire width 64 $pos$libresoc.v:158702$8540_Y - attribute \src "libresoc.v:158703.18-158703.114" - wire width 64 $pos$libresoc.v:158703$8542_Y - attribute \src "libresoc.v:158704.18-158704.115" - wire width 64 $pos$libresoc.v:158704$8544_Y - attribute \src "libresoc.v:158690.18-158690.121" - wire width 65 $ternary$libresoc.v:158690$8523_Y - attribute \src "libresoc.v:158693.18-158693.122" - wire width 65 $ternary$libresoc.v:158693$8528_Y - attribute \src "libresoc.v:158687.18-158687.120" - wire $xor$libresoc.v:158687$8518_Y - attribute \src "libresoc.v:158695.18-158695.127" - wire $xor$libresoc.v:158695$8530_Y + attribute \src "libresoc.v:160328.18-160328.122" + wire $and$libresoc.v:160328$8579_Y + attribute \src "libresoc.v:160320.18-160320.109" + wire width 65 $extend$libresoc.v:160320$8567_Y + attribute \src "libresoc.v:160321.18-160321.100" + wire width 65 $extend$libresoc.v:160321$8569_Y + attribute \src "libresoc.v:160323.18-160323.113" + wire width 65 $extend$libresoc.v:160323$8572_Y + attribute \src "libresoc.v:160324.18-160324.104" + wire width 65 $extend$libresoc.v:160324$8574_Y + attribute \src "libresoc.v:160332.18-160332.114" + wire width 64 $extend$libresoc.v:160332$8583_Y + attribute \src "libresoc.v:160333.18-160333.114" + wire width 64 $extend$libresoc.v:160333$8585_Y + attribute \src "libresoc.v:160334.18-160334.114" + wire width 64 $extend$libresoc.v:160334$8587_Y + attribute \src "libresoc.v:160335.18-160335.114" + wire width 64 $extend$libresoc.v:160335$8589_Y + attribute \src "libresoc.v:160336.18-160336.115" + wire width 64 $extend$libresoc.v:160336$8591_Y + attribute \src "libresoc.v:160329.18-160329.128" + wire $ne$libresoc.v:160329$8580_Y + attribute \src "libresoc.v:160320.18-160320.109" + wire width 65 $neg$libresoc.v:160320$8568_Y + attribute \src "libresoc.v:160323.18-160323.113" + wire width 65 $neg$libresoc.v:160323$8573_Y + attribute \src "libresoc.v:160326.18-160326.116" + wire $not$libresoc.v:160326$8577_Y + attribute \src "libresoc.v:160331.18-160331.99" + wire $not$libresoc.v:160331$8582_Y + attribute \src "libresoc.v:160321.18-160321.100" + wire width 65 $pos$libresoc.v:160321$8570_Y + attribute \src "libresoc.v:160324.18-160324.104" + wire width 65 $pos$libresoc.v:160324$8575_Y + attribute \src "libresoc.v:160330.18-160330.118" + wire width 64 $pos$libresoc.v:160330$8581_Y + attribute \src "libresoc.v:160332.18-160332.114" + wire width 64 $pos$libresoc.v:160332$8584_Y + attribute \src "libresoc.v:160333.18-160333.114" + wire width 64 $pos$libresoc.v:160333$8586_Y + attribute \src "libresoc.v:160334.18-160334.114" + wire width 64 $pos$libresoc.v:160334$8588_Y + attribute \src "libresoc.v:160335.18-160335.114" + wire width 64 $pos$libresoc.v:160335$8590_Y + attribute \src "libresoc.v:160336.18-160336.115" + wire width 64 $pos$libresoc.v:160336$8592_Y + attribute \src "libresoc.v:160322.18-160322.121" + wire width 65 $ternary$libresoc.v:160322$8571_Y + attribute \src "libresoc.v:160325.18-160325.122" + wire width 65 $ternary$libresoc.v:160325$8576_Y + attribute \src "libresoc.v:160319.18-160319.120" + wire $xor$libresoc.v:160319$8566_Y + attribute \src "libresoc.v:160327.18-160327.127" + wire $xor$libresoc.v:160327$8578_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -329804,7 +332301,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:158343.7-158343.15" + attribute \src "libresoc.v:159975.7-159975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -330101,7 +332598,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:158696$8531 + cell $and $and$libresoc.v:160328$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330109,82 +332606,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:158696$8531_Y + connect \Y $and$libresoc.v:160328$8579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:158688$8519 + cell $pos $extend$libresoc.v:160320$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:158688$8519_Y + connect \Y $extend$libresoc.v:160320$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:158689$8521 + cell $pos $extend$libresoc.v:160321$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:158689$8521_Y + connect \Y $extend$libresoc.v:160321$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:158691$8524 + cell $pos $extend$libresoc.v:160323$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:158691$8524_Y + connect \Y $extend$libresoc.v:160323$8572_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:158692$8526 + cell $pos $extend$libresoc.v:160324$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:158692$8526_Y + connect \Y $extend$libresoc.v:160324$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:158700$8535 + cell $pos $extend$libresoc.v:160332$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158700$8535_Y + connect \Y $extend$libresoc.v:160332$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:158701$8537 + cell $pos $extend$libresoc.v:160333$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158701$8537_Y + connect \Y $extend$libresoc.v:160333$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:158702$8539 + cell $pos $extend$libresoc.v:160334$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158702$8539_Y + connect \Y $extend$libresoc.v:160334$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:158703$8541 + cell $pos $extend$libresoc.v:160335$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:158703$8541_Y + connect \Y $extend$libresoc.v:160335$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:158704$8543 + cell $pos $extend$libresoc.v:160336$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:158704$8543_Y + connect \Y $extend$libresoc.v:160336$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:158697$8532 + cell $ne $ne$libresoc.v:160329$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330192,122 +332689,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:158697$8532_Y + connect \Y $ne$libresoc.v:160329$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:158688$8520 + cell $neg $neg$libresoc.v:160320$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158688$8519_Y - connect \Y $neg$libresoc.v:158688$8520_Y + connect \A $extend$libresoc.v:160320$8567_Y + connect \Y $neg$libresoc.v:160320$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:158691$8525 + cell $neg $neg$libresoc.v:160323$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158691$8524_Y - connect \Y $neg$libresoc.v:158691$8525_Y + connect \A $extend$libresoc.v:160323$8572_Y + connect \Y $neg$libresoc.v:160323$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:158694$8529 + cell $not $not$libresoc.v:160326$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:158694$8529_Y + connect \Y $not$libresoc.v:160326$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:158699$8534 + cell $not $not$libresoc.v:160331$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:158699$8534_Y + connect \Y $not$libresoc.v:160331$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:158689$8522 + cell $pos $pos$libresoc.v:160321$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158689$8521_Y - connect \Y $pos$libresoc.v:158689$8522_Y + connect \A $extend$libresoc.v:160321$8569_Y + connect \Y $pos$libresoc.v:160321$8570_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:158692$8527 + cell $pos $pos$libresoc.v:160324$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158692$8526_Y - connect \Y $pos$libresoc.v:158692$8527_Y + connect \A $extend$libresoc.v:160324$8574_Y + connect \Y $pos$libresoc.v:160324$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:158698$8533 + cell $pos $pos$libresoc.v:160330$8581 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:158698$8533_Y + connect \Y $pos$libresoc.v:160330$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:158700$8536 + cell $pos $pos$libresoc.v:160332$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158700$8535_Y - connect \Y $pos$libresoc.v:158700$8536_Y + connect \A $extend$libresoc.v:160332$8583_Y + connect \Y $pos$libresoc.v:160332$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:158701$8538 + cell $pos $pos$libresoc.v:160333$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158701$8537_Y - connect \Y $pos$libresoc.v:158701$8538_Y + connect \A $extend$libresoc.v:160333$8585_Y + connect \Y $pos$libresoc.v:160333$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:158702$8540 + cell $pos $pos$libresoc.v:160334$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158702$8539_Y - connect \Y $pos$libresoc.v:158702$8540_Y + connect \A $extend$libresoc.v:160334$8587_Y + connect \Y $pos$libresoc.v:160334$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:158703$8542 + cell $pos $pos$libresoc.v:160335$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158703$8541_Y - connect \Y $pos$libresoc.v:158703$8542_Y + connect \A $extend$libresoc.v:160335$8589_Y + connect \Y $pos$libresoc.v:160335$8590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:158704$8544 + cell $pos $pos$libresoc.v:160336$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:158704$8543_Y - connect \Y $pos$libresoc.v:158704$8544_Y + connect \A $extend$libresoc.v:160336$8591_Y + connect \Y $pos$libresoc.v:160336$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:158690$8523 + cell $mux $ternary$libresoc.v:160322$8571 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:158690$8523_Y + connect \Y $ternary$libresoc.v:160322$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:158693$8528 + cell $mux $ternary$libresoc.v:160325$8576 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:158693$8528_Y + connect \Y $ternary$libresoc.v:160325$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:158687$8518 + cell $xor $xor$libresoc.v:160319$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330315,10 +332812,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:158687$8518_Y + connect \Y $xor$libresoc.v:160319$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:158695$8530 + cell $xor $xor$libresoc.v:160327$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330326,24 +332823,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:158695$8530_Y + connect \Y $xor$libresoc.v:160327$8578_Y end - attribute \src "libresoc.v:158343.7-158343.20" - process $proc$libresoc.v:158343$8547 + attribute \src "libresoc.v:159975.7-159975.20" + process $proc$libresoc.v:159975$8595 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158705.3-158776.6" - process $proc$libresoc.v:158705$8545 + attribute \src "libresoc.v:160337.3-160408.6" + process $proc$libresoc.v:160337$8593 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:158706.5-158706.29" + attribute \src "libresoc.v:160338.5-160338.29" switch \initial - attribute \src "libresoc.v:158706.9-158706.17" + attribute \src "libresoc.v:160338.9-160338.17" case 1'1 case end @@ -330442,13 +332939,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:158777.3-158810.6" - process $proc$libresoc.v:158777$8546 + attribute \src "libresoc.v:160409.3-160442.6" + process $proc$libresoc.v:160409$8594 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:158778.5-158778.29" + attribute \src "libresoc.v:160410.5-160410.29" switch \initial - attribute \src "libresoc.v:158778.9-158778.17" + attribute \src "libresoc.v:160410.9-160410.17" case 1'1 case end @@ -330494,24 +332991,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:158687$8518_Y - connect \$23 $neg$libresoc.v:158688$8520_Y - connect \$25 $pos$libresoc.v:158689$8522_Y - connect \$27 $ternary$libresoc.v:158690$8523_Y - connect \$30 $neg$libresoc.v:158691$8525_Y - connect \$32 $pos$libresoc.v:158692$8527_Y - connect \$34 $ternary$libresoc.v:158693$8528_Y - connect \$36 $not$libresoc.v:158694$8529_Y - connect \$38 $xor$libresoc.v:158695$8530_Y - connect \$40 $and$libresoc.v:158696$8531_Y - connect \$42 $ne$libresoc.v:158697$8532_Y - connect \$44 $pos$libresoc.v:158698$8533_Y - connect \$46 $not$libresoc.v:158699$8534_Y - connect \$48 $pos$libresoc.v:158700$8536_Y - connect \$50 $pos$libresoc.v:158701$8538_Y - connect \$52 $pos$libresoc.v:158702$8540_Y - connect \$54 $pos$libresoc.v:158703$8542_Y - connect \$56 $pos$libresoc.v:158704$8544_Y + connect \$21 $xor$libresoc.v:160319$8566_Y + connect \$23 $neg$libresoc.v:160320$8568_Y + connect \$25 $pos$libresoc.v:160321$8570_Y + connect \$27 $ternary$libresoc.v:160322$8571_Y + connect \$30 $neg$libresoc.v:160323$8573_Y + connect \$32 $pos$libresoc.v:160324$8575_Y + connect \$34 $ternary$libresoc.v:160325$8576_Y + connect \$36 $not$libresoc.v:160326$8577_Y + connect \$38 $xor$libresoc.v:160327$8578_Y + connect \$40 $and$libresoc.v:160328$8579_Y + connect \$42 $ne$libresoc.v:160329$8580_Y + connect \$44 $pos$libresoc.v:160330$8581_Y + connect \$46 $not$libresoc.v:160331$8582_Y + connect \$48 $pos$libresoc.v:160332$8584_Y + connect \$50 $pos$libresoc.v:160333$8586_Y + connect \$52 $pos$libresoc.v:160334$8588_Y + connect \$54 $pos$libresoc.v:160335$8590_Y + connect \$56 $pos$libresoc.v:160336$8592_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -330526,13 +333023,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:158828.1-158839.10" +attribute \src "libresoc.v:160460.1-160471.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:158837.17-158837.111" - wire $and$libresoc.v:158837$8548_Y + attribute \src "libresoc.v:160469.17-160469.111" + wire $and$libresoc.v:160469$8596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330542,7 +333039,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158837$8548 + cell $and $and$libresoc.v:160469$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330550,18 +333047,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158837$8548_Y + connect \Y $and$libresoc.v:160469$8596_Y end - connect \$1 $and$libresoc.v:158837$8548_Y + connect \$1 $and$libresoc.v:160469$8596_Y connect \trigger \$1 end -attribute \src "libresoc.v:158843.1-158854.10" +attribute \src "libresoc.v:160475.1-160486.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:158852.17-158852.111" - wire $and$libresoc.v:158852$8549_Y + attribute \src "libresoc.v:160484.17-160484.111" + wire $and$libresoc.v:160484$8597_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330571,7 +333068,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158852$8549 + cell $and $and$libresoc.v:160484$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330579,18 +333076,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158852$8549_Y + connect \Y $and$libresoc.v:160484$8597_Y end - connect \$1 $and$libresoc.v:158852$8549_Y + connect \$1 $and$libresoc.v:160484$8597_Y connect \trigger \$1 end -attribute \src "libresoc.v:158858.1-158869.10" +attribute \src "libresoc.v:160490.1-160501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:158867.17-158867.111" - wire $and$libresoc.v:158867$8550_Y + attribute \src "libresoc.v:160499.17-160499.111" + wire $and$libresoc.v:160499$8598_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330600,7 +333097,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158867$8550 + cell $and $and$libresoc.v:160499$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330608,18 +333105,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158867$8550_Y + connect \Y $and$libresoc.v:160499$8598_Y end - connect \$1 $and$libresoc.v:158867$8550_Y + connect \$1 $and$libresoc.v:160499$8598_Y connect \trigger \$1 end -attribute \src "libresoc.v:158873.1-158884.10" +attribute \src "libresoc.v:160505.1-160516.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:158882.17-158882.111" - wire $and$libresoc.v:158882$8551_Y + attribute \src "libresoc.v:160514.17-160514.111" + wire $and$libresoc.v:160514$8599_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330629,7 +333126,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158882$8551 + cell $and $and$libresoc.v:160514$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330637,18 +333134,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158882$8551_Y + connect \Y $and$libresoc.v:160514$8599_Y end - connect \$1 $and$libresoc.v:158882$8551_Y + connect \$1 $and$libresoc.v:160514$8599_Y connect \trigger \$1 end -attribute \src "libresoc.v:158888.1-158899.10" +attribute \src "libresoc.v:160520.1-160531.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:158897.17-158897.111" - wire $and$libresoc.v:158897$8552_Y + attribute \src "libresoc.v:160529.17-160529.111" + wire $and$libresoc.v:160529$8600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330658,7 +333155,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158897$8552 + cell $and $and$libresoc.v:160529$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330666,18 +333163,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158897$8552_Y + connect \Y $and$libresoc.v:160529$8600_Y end - connect \$1 $and$libresoc.v:158897$8552_Y + connect \$1 $and$libresoc.v:160529$8600_Y connect \trigger \$1 end -attribute \src "libresoc.v:158903.1-158914.10" +attribute \src "libresoc.v:160535.1-160546.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:158912.17-158912.111" - wire $and$libresoc.v:158912$8553_Y + attribute \src "libresoc.v:160544.17-160544.111" + wire $and$libresoc.v:160544$8601_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330687,7 +333184,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158912$8553 + cell $and $and$libresoc.v:160544$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330695,18 +333192,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158912$8553_Y + connect \Y $and$libresoc.v:160544$8601_Y end - connect \$1 $and$libresoc.v:158912$8553_Y + connect \$1 $and$libresoc.v:160544$8601_Y connect \trigger \$1 end -attribute \src "libresoc.v:158918.1-158929.10" +attribute \src "libresoc.v:160550.1-160561.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:158927.17-158927.111" - wire $and$libresoc.v:158927$8554_Y + attribute \src "libresoc.v:160559.17-160559.111" + wire $and$libresoc.v:160559$8602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330716,7 +333213,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158927$8554 + cell $and $and$libresoc.v:160559$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330724,18 +333221,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158927$8554_Y + connect \Y $and$libresoc.v:160559$8602_Y end - connect \$1 $and$libresoc.v:158927$8554_Y + connect \$1 $and$libresoc.v:160559$8602_Y connect \trigger \$1 end -attribute \src "libresoc.v:158933.1-158944.10" +attribute \src "libresoc.v:160565.1-160576.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:158942.17-158942.111" - wire $and$libresoc.v:158942$8555_Y + attribute \src "libresoc.v:160574.17-160574.111" + wire $and$libresoc.v:160574$8603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330745,7 +333242,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158942$8555 + cell $and $and$libresoc.v:160574$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330753,18 +333250,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158942$8555_Y + connect \Y $and$libresoc.v:160574$8603_Y end - connect \$1 $and$libresoc.v:158942$8555_Y + connect \$1 $and$libresoc.v:160574$8603_Y connect \trigger \$1 end -attribute \src "libresoc.v:158948.1-158959.10" +attribute \src "libresoc.v:160580.1-160591.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:158957.17-158957.111" - wire $and$libresoc.v:158957$8556_Y + attribute \src "libresoc.v:160589.17-160589.111" + wire $and$libresoc.v:160589$8604_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330774,7 +333271,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158957$8556 + cell $and $and$libresoc.v:160589$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330782,18 +333279,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158957$8556_Y + connect \Y $and$libresoc.v:160589$8604_Y end - connect \$1 $and$libresoc.v:158957$8556_Y + connect \$1 $and$libresoc.v:160589$8604_Y connect \trigger \$1 end -attribute \src "libresoc.v:158963.1-158974.10" +attribute \src "libresoc.v:160595.1-160606.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:158972.17-158972.111" - wire $and$libresoc.v:158972$8557_Y + attribute \src "libresoc.v:160604.17-160604.111" + wire $and$libresoc.v:160604$8605_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330803,7 +333300,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158972$8557 + cell $and $and$libresoc.v:160604$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330811,18 +333308,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158972$8557_Y + connect \Y $and$libresoc.v:160604$8605_Y end - connect \$1 $and$libresoc.v:158972$8557_Y + connect \$1 $and$libresoc.v:160604$8605_Y connect \trigger \$1 end -attribute \src "libresoc.v:158978.1-158989.10" +attribute \src "libresoc.v:160610.1-160621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:158987.17-158987.111" - wire $and$libresoc.v:158987$8558_Y + attribute \src "libresoc.v:160619.17-160619.111" + wire $and$libresoc.v:160619$8606_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330832,7 +333329,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:158987$8558 + cell $and $and$libresoc.v:160619$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330840,18 +333337,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:158987$8558_Y + connect \Y $and$libresoc.v:160619$8606_Y end - connect \$1 $and$libresoc.v:158987$8558_Y + connect \$1 $and$libresoc.v:160619$8606_Y connect \trigger \$1 end -attribute \src "libresoc.v:158993.1-159004.10" +attribute \src "libresoc.v:160625.1-160636.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:159002.17-159002.111" - wire $and$libresoc.v:159002$8559_Y + attribute \src "libresoc.v:160634.17-160634.111" + wire $and$libresoc.v:160634$8607_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330861,7 +333358,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159002$8559 + cell $and $and$libresoc.v:160634$8607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330869,18 +333366,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159002$8559_Y + connect \Y $and$libresoc.v:160634$8607_Y end - connect \$1 $and$libresoc.v:159002$8559_Y + connect \$1 $and$libresoc.v:160634$8607_Y connect \trigger \$1 end -attribute \src "libresoc.v:159008.1-159019.10" +attribute \src "libresoc.v:160640.1-160651.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:159017.17-159017.111" - wire $and$libresoc.v:159017$8560_Y + attribute \src "libresoc.v:160649.17-160649.111" + wire $and$libresoc.v:160649$8608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330890,7 +333387,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159017$8560 + cell $and $and$libresoc.v:160649$8608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330898,18 +333395,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159017$8560_Y + connect \Y $and$libresoc.v:160649$8608_Y end - connect \$1 $and$libresoc.v:159017$8560_Y + connect \$1 $and$libresoc.v:160649$8608_Y connect \trigger \$1 end -attribute \src "libresoc.v:159023.1-159034.10" +attribute \src "libresoc.v:160655.1-160666.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:159032.17-159032.111" - wire $and$libresoc.v:159032$8561_Y + attribute \src "libresoc.v:160664.17-160664.111" + wire $and$libresoc.v:160664$8609_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330919,7 +333416,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159032$8561 + cell $and $and$libresoc.v:160664$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330927,18 +333424,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159032$8561_Y + connect \Y $and$libresoc.v:160664$8609_Y end - connect \$1 $and$libresoc.v:159032$8561_Y + connect \$1 $and$libresoc.v:160664$8609_Y connect \trigger \$1 end -attribute \src "libresoc.v:159038.1-159049.10" +attribute \src "libresoc.v:160670.1-160681.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:159047.17-159047.111" - wire $and$libresoc.v:159047$8562_Y + attribute \src "libresoc.v:160679.17-160679.111" + wire $and$libresoc.v:160679$8610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330948,7 +333445,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159047$8562 + cell $and $and$libresoc.v:160679$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330956,18 +333453,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159047$8562_Y + connect \Y $and$libresoc.v:160679$8610_Y end - connect \$1 $and$libresoc.v:159047$8562_Y + connect \$1 $and$libresoc.v:160679$8610_Y connect \trigger \$1 end -attribute \src "libresoc.v:159053.1-159064.10" +attribute \src "libresoc.v:160685.1-160696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:159062.17-159062.111" - wire $and$libresoc.v:159062$8563_Y + attribute \src "libresoc.v:160694.17-160694.111" + wire $and$libresoc.v:160694$8611_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330977,7 +333474,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159062$8563 + cell $and $and$libresoc.v:160694$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330985,18 +333482,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159062$8563_Y + connect \Y $and$libresoc.v:160694$8611_Y end - connect \$1 $and$libresoc.v:159062$8563_Y + connect \$1 $and$libresoc.v:160694$8611_Y connect \trigger \$1 end -attribute \src "libresoc.v:159068.1-159079.10" +attribute \src "libresoc.v:160700.1-160711.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:159077.17-159077.111" - wire $and$libresoc.v:159077$8564_Y + attribute \src "libresoc.v:160709.17-160709.111" + wire $and$libresoc.v:160709$8612_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331006,7 +333503,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159077$8564 + cell $and $and$libresoc.v:160709$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331014,18 +333511,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159077$8564_Y + connect \Y $and$libresoc.v:160709$8612_Y end - connect \$1 $and$libresoc.v:159077$8564_Y + connect \$1 $and$libresoc.v:160709$8612_Y connect \trigger \$1 end -attribute \src "libresoc.v:159083.1-159094.10" +attribute \src "libresoc.v:160715.1-160726.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:159092.17-159092.111" - wire $and$libresoc.v:159092$8565_Y + attribute \src "libresoc.v:160724.17-160724.111" + wire $and$libresoc.v:160724$8613_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331035,7 +333532,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159092$8565 + cell $and $and$libresoc.v:160724$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331043,18 +333540,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159092$8565_Y + connect \Y $and$libresoc.v:160724$8613_Y end - connect \$1 $and$libresoc.v:159092$8565_Y + connect \$1 $and$libresoc.v:160724$8613_Y connect \trigger \$1 end -attribute \src "libresoc.v:159098.1-159109.10" +attribute \src "libresoc.v:160730.1-160741.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:159107.17-159107.111" - wire $and$libresoc.v:159107$8566_Y + attribute \src "libresoc.v:160739.17-160739.111" + wire $and$libresoc.v:160739$8614_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331064,7 +333561,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159107$8566 + cell $and $and$libresoc.v:160739$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331072,18 +333569,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159107$8566_Y + connect \Y $and$libresoc.v:160739$8614_Y end - connect \$1 $and$libresoc.v:159107$8566_Y + connect \$1 $and$libresoc.v:160739$8614_Y connect \trigger \$1 end -attribute \src "libresoc.v:159113.1-159124.10" +attribute \src "libresoc.v:160745.1-160756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:159122.17-159122.111" - wire $and$libresoc.v:159122$8567_Y + attribute \src "libresoc.v:160754.17-160754.111" + wire $and$libresoc.v:160754$8615_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331093,7 +333590,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159122$8567 + cell $and $and$libresoc.v:160754$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331101,18 +333598,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159122$8567_Y + connect \Y $and$libresoc.v:160754$8615_Y end - connect \$1 $and$libresoc.v:159122$8567_Y + connect \$1 $and$libresoc.v:160754$8615_Y connect \trigger \$1 end -attribute \src "libresoc.v:159128.1-159139.10" +attribute \src "libresoc.v:160760.1-160771.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:159137.17-159137.111" - wire $and$libresoc.v:159137$8568_Y + attribute \src "libresoc.v:160769.17-160769.111" + wire $and$libresoc.v:160769$8616_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331122,7 +333619,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159137$8568 + cell $and $and$libresoc.v:160769$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331130,18 +333627,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159137$8568_Y + connect \Y $and$libresoc.v:160769$8616_Y end - connect \$1 $and$libresoc.v:159137$8568_Y + connect \$1 $and$libresoc.v:160769$8616_Y connect \trigger \$1 end -attribute \src "libresoc.v:159143.1-159154.10" +attribute \src "libresoc.v:160775.1-160786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:159152.17-159152.111" - wire $and$libresoc.v:159152$8569_Y + attribute \src "libresoc.v:160784.17-160784.111" + wire $and$libresoc.v:160784$8617_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331151,7 +333648,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159152$8569 + cell $and $and$libresoc.v:160784$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331159,18 +333656,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159152$8569_Y + connect \Y $and$libresoc.v:160784$8617_Y end - connect \$1 $and$libresoc.v:159152$8569_Y + connect \$1 $and$libresoc.v:160784$8617_Y connect \trigger \$1 end -attribute \src "libresoc.v:159158.1-159169.10" +attribute \src "libresoc.v:160790.1-160801.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:159167.17-159167.111" - wire $and$libresoc.v:159167$8570_Y + attribute \src "libresoc.v:160799.17-160799.111" + wire $and$libresoc.v:160799$8618_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331180,7 +333677,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159167$8570 + cell $and $and$libresoc.v:160799$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331188,18 +333685,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159167$8570_Y + connect \Y $and$libresoc.v:160799$8618_Y end - connect \$1 $and$libresoc.v:159167$8570_Y + connect \$1 $and$libresoc.v:160799$8618_Y connect \trigger \$1 end -attribute \src "libresoc.v:159173.1-159184.10" +attribute \src "libresoc.v:160805.1-160816.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:159182.17-159182.111" - wire $and$libresoc.v:159182$8571_Y + attribute \src "libresoc.v:160814.17-160814.111" + wire $and$libresoc.v:160814$8619_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331209,7 +333706,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159182$8571 + cell $and $and$libresoc.v:160814$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331217,18 +333714,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159182$8571_Y + connect \Y $and$libresoc.v:160814$8619_Y end - connect \$1 $and$libresoc.v:159182$8571_Y + connect \$1 $and$libresoc.v:160814$8619_Y connect \trigger \$1 end -attribute \src "libresoc.v:159188.1-159199.10" +attribute \src "libresoc.v:160820.1-160831.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:159197.17-159197.111" - wire $and$libresoc.v:159197$8572_Y + attribute \src "libresoc.v:160829.17-160829.111" + wire $and$libresoc.v:160829$8620_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331238,7 +333735,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159197$8572 + cell $and $and$libresoc.v:160829$8620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331246,18 +333743,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159197$8572_Y + connect \Y $and$libresoc.v:160829$8620_Y end - connect \$1 $and$libresoc.v:159197$8572_Y + connect \$1 $and$libresoc.v:160829$8620_Y connect \trigger \$1 end -attribute \src "libresoc.v:159203.1-159214.10" +attribute \src "libresoc.v:160835.1-160846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:159212.17-159212.111" - wire $and$libresoc.v:159212$8573_Y + attribute \src "libresoc.v:160844.17-160844.111" + wire $and$libresoc.v:160844$8621_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -331267,7 +333764,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:159212$8573 + cell $and $and$libresoc.v:160844$8621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331275,36 +333772,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:159212$8573_Y + connect \Y $and$libresoc.v:160844$8621_Y end - connect \$1 $and$libresoc.v:159212$8573_Y + connect \$1 $and$libresoc.v:160844$8621_Y connect \trigger \$1 end -attribute \src "libresoc.v:159218.1-159241.10" +attribute \src "libresoc.v:160850.1-160873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:159219.7-159219.20" + attribute \src "libresoc.v:160851.7-160851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159230.3-159239.6" + attribute \src "libresoc.v:160862.3-160871.6" wire $0\o[0:0] - attribute \src "libresoc.v:159230.3-159239.6" + attribute \src "libresoc.v:160862.3-160871.6" wire $1\o[0:0] - attribute \src "libresoc.v:159229.17-159229.95" - wire $eq$libresoc.v:159229$8574_Y + attribute \src "libresoc.v:160861.17-160861.95" + wire $eq$libresoc.v:160861$8622_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:159219.7-159219.15" + attribute \src "libresoc.v:160851.7-160851.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:159229$8574 + cell $eq $eq$libresoc.v:160861$8622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331312,24 +333809,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:159229$8574_Y + connect \Y $eq$libresoc.v:160861$8622_Y end - attribute \src "libresoc.v:159219.7-159219.20" - process $proc$libresoc.v:159219$8576 + attribute \src "libresoc.v:160851.7-160851.20" + process $proc$libresoc.v:160851$8624 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159230.3-159239.6" - process $proc$libresoc.v:159230$8575 + attribute \src "libresoc.v:160862.3-160871.6" + process $proc$libresoc.v:160862$8623 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:159231.5-159231.29" + attribute \src "libresoc.v:160863.5-160863.29" switch \initial - attribute \src "libresoc.v:159231.9-159231.17" + attribute \src "libresoc.v:160863.9-160863.17" case 1'1 case end @@ -331345,296 +333842,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:159229$8574_Y + connect \$1 $eq$libresoc.v:160861$8622_Y connect \n \$1 end -attribute \src "libresoc.v:159245.1-160059.10" +attribute \src "libresoc.v:160877.1-161691.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8666 - attribute \src "libresoc.v:159544.3-159545.57" + attribute \src "libresoc.v:161618.3-161653.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8714 + attribute \src "libresoc.v:161176.3-161177.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:159636.3-159644.6" - wire $0\busy_delay$next[0:0]$8634 - attribute \src "libresoc.v:159542.3-159543.37" + attribute \src "libresoc.v:161268.3-161276.6" + wire $0\busy_delay$next[0:0]$8682 + attribute \src "libresoc.v:161174.3-161175.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161602.3-161617.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159960.3-159969.6" + attribute \src "libresoc.v:161592.3-161601.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159950.3-159959.6" + attribute \src "libresoc.v:161582.3-161591.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159931.3-159940.6" + attribute \src "libresoc.v:161563.3-161572.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $0\fsm_state$next[1:0]$8652 - attribute \src "libresoc.v:159534.3-159535.35" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $0\fsm_state$next[1:0]$8700 + attribute \src "libresoc.v:161166.3-161167.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:159246.7-159246.20" + attribute \src "libresoc.v:160878.7-160878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159832.3-159841.6" + attribute \src "libresoc.v:161464.3-161473.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159540.3-159541.35" + attribute \src "libresoc.v:161172.3-161173.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161397.3-161427.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159822.3-159831.6" + attribute \src "libresoc.v:161454.3-161463.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159842.3-159851.6" + attribute \src "libresoc.v:161474.3-161483.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:159941.3-159949.6" - wire $0\lsui_active_dly$next[0:0]$8660 - attribute \src "libresoc.v:159532.3-159533.47" + attribute \src "libresoc.v:161573.3-161581.6" + wire $0\lsui_active_dly$next[0:0]$8708 + attribute \src "libresoc.v:161164.3-161165.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:159536.3-159537.36" + attribute \src "libresoc.v:161168.3-161169.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:159812.3-159821.6" + attribute \src "libresoc.v:161444.3-161453.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159645.3-159654.6" + attribute \src "libresoc.v:161277.3-161286.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159626.3-159635.6" + attribute \src "libresoc.v:161258.3-161267.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $0\st_done_s_st_done$next[0:0]$8629 - attribute \src "libresoc.v:159546.3-159547.51" + attribute \src "libresoc.v:161243.3-161257.6" + wire $0\st_done_s_st_done$next[0:0]$8677 + attribute \src "libresoc.v:161178.3-161179.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:159852.3-159861.6" + attribute \src "libresoc.v:161484.3-161493.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:159538.3-159539.35" + attribute \src "libresoc.v:161170.3-161171.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:159862.3-159871.6" + attribute \src "libresoc.v:161494.3-161503.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8667 - attribute \src "libresoc.v:159340.7-159340.34" + attribute \src "libresoc.v:161618.3-161653.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8715 + attribute \src "libresoc.v:160972.7-160972.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:159636.3-159644.6" - wire $1\busy_delay$next[0:0]$8635 - attribute \src "libresoc.v:159344.7-159344.24" + attribute \src "libresoc.v:161268.3-161276.6" + wire $1\busy_delay$next[0:0]$8683 + attribute \src "libresoc.v:160976.7-160976.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161602.3-161617.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159960.3-159969.6" + attribute \src "libresoc.v:161592.3-161601.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159950.3-159959.6" + attribute \src "libresoc.v:161582.3-161591.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159931.3-159940.6" + attribute \src "libresoc.v:161563.3-161572.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $1\fsm_state$next[1:0]$8653 - attribute \src "libresoc.v:159366.13-159366.29" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $1\fsm_state$next[1:0]$8701 + attribute \src "libresoc.v:160998.13-160998.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:159832.3-159841.6" + attribute \src "libresoc.v:161464.3-161473.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159380.7-159380.21" + attribute \src "libresoc.v:161012.7-161012.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161397.3-161427.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159822.3-159831.6" + attribute \src "libresoc.v:161454.3-161463.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159842.3-159851.6" + attribute \src "libresoc.v:161474.3-161483.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:159941.3-159949.6" - wire $1\lsui_active_dly$next[0:0]$8661 - attribute \src "libresoc.v:159423.7-159423.29" + attribute \src "libresoc.v:161573.3-161581.6" + wire $1\lsui_active_dly$next[0:0]$8709 + attribute \src "libresoc.v:161055.7-161055.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:159435.7-159435.25" + attribute \src "libresoc.v:161067.7-161067.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:159812.3-159821.6" + attribute \src "libresoc.v:161444.3-161453.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159645.3-159654.6" + attribute \src "libresoc.v:161277.3-161286.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159626.3-159635.6" + attribute \src "libresoc.v:161258.3-161267.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $1\st_done_s_st_done$next[0:0]$8630 - attribute \src "libresoc.v:159455.7-159455.31" + attribute \src "libresoc.v:161243.3-161257.6" + wire $1\st_done_s_st_done$next[0:0]$8678 + attribute \src "libresoc.v:161087.7-161087.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:159852.3-159861.6" + attribute \src "libresoc.v:161484.3-161493.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:159463.7-159463.21" + attribute \src "libresoc.v:161095.7-161095.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:159862.3-159871.6" + attribute \src "libresoc.v:161494.3-161503.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:160022.3-160037.6" + attribute \src "libresoc.v:161654.3-161669.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8668 - attribute \src "libresoc.v:159970.3-159985.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8716 + attribute \src "libresoc.v:161602.3-161617.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $2\fsm_state$next[1:0]$8654 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $2\fsm_state$next[1:0]$8702 + attribute \src "libresoc.v:161397.3-161427.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159671.3-159686.6" + attribute \src "libresoc.v:161303.3-161318.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159655.3-159670.6" + attribute \src "libresoc.v:161287.3-161302.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:159872.3-159891.6" + attribute \src "libresoc.v:161504.3-161523.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:159796.3-159811.6" + attribute \src "libresoc.v:161428.3-161443.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159611.3-159625.6" - wire $2\st_done_s_st_done$next[0:0]$8631 - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161243.3-161257.6" + wire $2\st_done_s_st_done$next[0:0]$8679 + attribute \src "libresoc.v:161319.3-161344.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8669 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $3\fsm_state$next[1:0]$8655 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8717 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $3\fsm_state$next[1:0]$8703 + attribute \src "libresoc.v:161397.3-161427.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8670 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $4\fsm_state$next[1:0]$8656 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8718 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $4\fsm_state$next[1:0]$8704 + attribute \src "libresoc.v:161397.3-161427.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159687.3-159712.6" + attribute \src "libresoc.v:161319.3-161344.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159739.3-159764.6" + attribute \src "libresoc.v:161371.3-161396.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:159713.3-159738.6" + attribute \src "libresoc.v:161345.3-161370.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8671 - attribute \src "libresoc.v:159892.3-159930.6" - wire width 2 $5\fsm_state$next[1:0]$8657 - attribute \src "libresoc.v:159765.3-159795.6" + attribute \src "libresoc.v:161618.3-161653.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8719 + attribute \src "libresoc.v:161524.3-161562.6" + wire width 2 $5\fsm_state$next[1:0]$8705 + attribute \src "libresoc.v:161397.3-161427.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159986.3-160021.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8672 - attribute \src "libresoc.v:159492.18-159492.115" - wire $and$libresoc.v:159492$8578_Y - attribute \src "libresoc.v:159494.18-159494.95" - wire $and$libresoc.v:159494$8580_Y - attribute \src "libresoc.v:159496.17-159496.138" - wire $and$libresoc.v:159496$8582_Y - attribute \src "libresoc.v:159497.18-159497.95" - wire $and$libresoc.v:159497$8583_Y - attribute \src "libresoc.v:159500.18-159500.136" - wire $and$libresoc.v:159500$8588_Y - attribute \src "libresoc.v:159501.18-159501.136" - wire $and$libresoc.v:159501$8589_Y - attribute \src "libresoc.v:159502.18-159502.136" - wire $and$libresoc.v:159502$8590_Y - attribute \src "libresoc.v:159503.18-159503.136" - wire $and$libresoc.v:159503$8591_Y - attribute \src "libresoc.v:159504.18-159504.136" - wire $and$libresoc.v:159504$8592_Y - attribute \src "libresoc.v:159509.18-159509.119" - wire width 176 $and$libresoc.v:159509$8597_Y - attribute \src "libresoc.v:159512.18-159512.136" - wire $and$libresoc.v:159512$8600_Y - attribute \src "libresoc.v:159513.18-159513.136" - wire $and$libresoc.v:159513$8601_Y - attribute \src "libresoc.v:159515.18-159515.139" - wire $and$libresoc.v:159515$8603_Y - attribute \src "libresoc.v:159519.18-159519.139" - wire $and$libresoc.v:159519$8607_Y - attribute \src "libresoc.v:159521.18-159521.114" - wire $and$libresoc.v:159521$8609_Y - attribute \src "libresoc.v:159523.18-159523.114" - wire $and$libresoc.v:159523$8611_Y - attribute \src "libresoc.v:159527.18-159527.103" - wire $and$libresoc.v:159527$8615_Y - attribute \src "libresoc.v:159528.17-159528.135" - wire $and$libresoc.v:159528$8616_Y - attribute \src "libresoc.v:159531.18-159531.103" - wire $and$libresoc.v:159531$8619_Y - attribute \src "libresoc.v:159498.18-159498.109" - wire width 4 $extend$libresoc.v:159498$8584_Y - attribute \src "libresoc.v:159499.18-159499.109" - wire width 4 $extend$libresoc.v:159499$8586_Y - attribute \src "libresoc.v:159510.18-159510.112" - wire width 8 $mul$libresoc.v:159510$8598_Y - attribute \src "libresoc.v:159516.18-159516.112" - wire width 8 $mul$libresoc.v:159516$8604_Y - attribute \src "libresoc.v:159491.17-159491.103" - wire $not$libresoc.v:159491$8577_Y - attribute \src "libresoc.v:159493.18-159493.94" - wire $not$libresoc.v:159493$8579_Y - attribute \src "libresoc.v:159495.18-159495.94" - wire $not$libresoc.v:159495$8581_Y - attribute \src "libresoc.v:159505.18-159505.102" - wire $not$libresoc.v:159505$8593_Y - attribute \src "libresoc.v:159508.18-159508.97" - wire $not$libresoc.v:159508$8596_Y - attribute \src "libresoc.v:159514.18-159514.102" - wire $not$libresoc.v:159514$8602_Y - attribute \src "libresoc.v:159517.17-159517.103" - wire $not$libresoc.v:159517$8605_Y - attribute \src "libresoc.v:159524.18-159524.101" - wire $not$libresoc.v:159524$8612_Y - attribute \src "libresoc.v:159525.18-159525.111" - wire $not$libresoc.v:159525$8613_Y - attribute \src "libresoc.v:159526.18-159526.110" - wire $not$libresoc.v:159526$8614_Y - attribute \src "libresoc.v:159529.18-159529.102" - wire $not$libresoc.v:159529$8617_Y - attribute \src "libresoc.v:159530.18-159530.102" - wire $not$libresoc.v:159530$8618_Y - attribute \src "libresoc.v:159506.18-159506.111" - wire $or$libresoc.v:159506$8594_Y - attribute \src "libresoc.v:159507.17-159507.130" - wire $or$libresoc.v:159507$8595_Y - attribute \src "libresoc.v:159520.18-159520.130" - wire $or$libresoc.v:159520$8608_Y - attribute \src "libresoc.v:159522.18-159522.130" - wire $or$libresoc.v:159522$8610_Y - attribute \src "libresoc.v:159498.18-159498.109" - wire width 4 $pos$libresoc.v:159498$8585_Y - attribute \src "libresoc.v:159499.18-159499.109" - wire width 4 $pos$libresoc.v:159499$8587_Y - attribute \src "libresoc.v:159518.18-159518.121" - wire width 319 $sshl$libresoc.v:159518$8606_Y - attribute \src "libresoc.v:159511.18-159511.106" - wire width 176 $sshr$libresoc.v:159511$8599_Y + attribute \src "libresoc.v:161618.3-161653.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "libresoc.v:161124.18-161124.115" + wire $and$libresoc.v:161124$8626_Y + attribute \src "libresoc.v:161126.18-161126.95" + wire $and$libresoc.v:161126$8628_Y + attribute \src "libresoc.v:161128.17-161128.138" + wire $and$libresoc.v:161128$8630_Y + attribute \src "libresoc.v:161129.18-161129.95" + wire $and$libresoc.v:161129$8631_Y + attribute \src "libresoc.v:161132.18-161132.136" + wire $and$libresoc.v:161132$8636_Y + attribute \src "libresoc.v:161133.18-161133.136" + wire $and$libresoc.v:161133$8637_Y + attribute \src "libresoc.v:161134.18-161134.136" + wire $and$libresoc.v:161134$8638_Y + attribute \src "libresoc.v:161135.18-161135.136" + wire $and$libresoc.v:161135$8639_Y + attribute \src "libresoc.v:161136.18-161136.136" + wire $and$libresoc.v:161136$8640_Y + attribute \src "libresoc.v:161141.18-161141.119" + wire width 176 $and$libresoc.v:161141$8645_Y + attribute \src "libresoc.v:161144.18-161144.136" + wire $and$libresoc.v:161144$8648_Y + attribute \src "libresoc.v:161145.18-161145.136" + wire $and$libresoc.v:161145$8649_Y + attribute \src "libresoc.v:161147.18-161147.139" + wire $and$libresoc.v:161147$8651_Y + attribute \src "libresoc.v:161151.18-161151.139" + wire $and$libresoc.v:161151$8655_Y + attribute \src "libresoc.v:161153.18-161153.114" + wire $and$libresoc.v:161153$8657_Y + attribute \src "libresoc.v:161155.18-161155.114" + wire $and$libresoc.v:161155$8659_Y + attribute \src "libresoc.v:161159.18-161159.103" + wire $and$libresoc.v:161159$8663_Y + attribute \src "libresoc.v:161160.17-161160.135" + wire $and$libresoc.v:161160$8664_Y + attribute \src "libresoc.v:161163.18-161163.103" + wire $and$libresoc.v:161163$8667_Y + attribute \src "libresoc.v:161130.18-161130.109" + wire width 4 $extend$libresoc.v:161130$8632_Y + attribute \src "libresoc.v:161131.18-161131.109" + wire width 4 $extend$libresoc.v:161131$8634_Y + attribute \src "libresoc.v:161142.18-161142.112" + wire width 8 $mul$libresoc.v:161142$8646_Y + attribute \src "libresoc.v:161148.18-161148.112" + wire width 8 $mul$libresoc.v:161148$8652_Y + attribute \src "libresoc.v:161123.17-161123.103" + wire $not$libresoc.v:161123$8625_Y + attribute \src "libresoc.v:161125.18-161125.94" + wire $not$libresoc.v:161125$8627_Y + attribute \src "libresoc.v:161127.18-161127.94" + wire $not$libresoc.v:161127$8629_Y + attribute \src "libresoc.v:161137.18-161137.102" + wire $not$libresoc.v:161137$8641_Y + attribute \src "libresoc.v:161140.18-161140.97" + wire $not$libresoc.v:161140$8644_Y + attribute \src "libresoc.v:161146.18-161146.102" + wire $not$libresoc.v:161146$8650_Y + attribute \src "libresoc.v:161149.17-161149.103" + wire $not$libresoc.v:161149$8653_Y + attribute \src "libresoc.v:161156.18-161156.101" + wire $not$libresoc.v:161156$8660_Y + attribute \src "libresoc.v:161157.18-161157.111" + wire $not$libresoc.v:161157$8661_Y + attribute \src "libresoc.v:161158.18-161158.110" + wire $not$libresoc.v:161158$8662_Y + attribute \src "libresoc.v:161161.18-161161.102" + wire $not$libresoc.v:161161$8665_Y + attribute \src "libresoc.v:161162.18-161162.102" + wire $not$libresoc.v:161162$8666_Y + attribute \src "libresoc.v:161138.18-161138.111" + wire $or$libresoc.v:161138$8642_Y + attribute \src "libresoc.v:161139.17-161139.130" + wire $or$libresoc.v:161139$8643_Y + attribute \src "libresoc.v:161152.18-161152.130" + wire $or$libresoc.v:161152$8656_Y + attribute \src "libresoc.v:161154.18-161154.130" + wire $or$libresoc.v:161154$8658_Y + attribute \src "libresoc.v:161130.18-161130.109" + wire width 4 $pos$libresoc.v:161130$8633_Y + attribute \src "libresoc.v:161131.18-161131.109" + wire width 4 $pos$libresoc.v:161131$8635_Y + attribute \src "libresoc.v:161150.18-161150.121" + wire width 319 $sshl$libresoc.v:161150$8654_Y + attribute \src "libresoc.v:161143.18-161143.106" + wire width 176 $sshr$libresoc.v:161143$8647_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -331743,9 +334240,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -331757,7 +334254,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:159246.7-159246.15" + attribute \src "libresoc.v:160878.7-160878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -331876,7 +334373,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:159492$8578 + cell $and $and$libresoc.v:161124$8626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331884,10 +334381,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:159492$8578_Y + connect \Y $and$libresoc.v:161124$8626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159494$8580 + cell $and $and$libresoc.v:161126$8628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331895,10 +334392,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:159494$8580_Y + connect \Y $and$libresoc.v:161126$8628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159496$8582 + cell $and $and$libresoc.v:161128$8630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331906,10 +334403,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159496$8582_Y + connect \Y $and$libresoc.v:161128$8630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159497$8583 + cell $and $and$libresoc.v:161129$8631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331917,10 +334414,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:159497$8583_Y + connect \Y $and$libresoc.v:161129$8631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159500$8588 + cell $and $and$libresoc.v:161132$8636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331928,10 +334425,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159500$8588_Y + connect \Y $and$libresoc.v:161132$8636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159501$8589 + cell $and $and$libresoc.v:161133$8637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331939,10 +334436,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159501$8589_Y + connect \Y $and$libresoc.v:161133$8637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159502$8590 + cell $and $and$libresoc.v:161134$8638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331950,10 +334447,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159502$8590_Y + connect \Y $and$libresoc.v:161134$8638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159503$8591 + cell $and $and$libresoc.v:161135$8639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331961,10 +334458,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159503$8591_Y + connect \Y $and$libresoc.v:161135$8639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159504$8592 + cell $and $and$libresoc.v:161136$8640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331972,10 +334469,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159504$8592_Y + connect \Y $and$libresoc.v:161136$8640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:159509$8597 + cell $and $and$libresoc.v:161141$8645 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -331983,10 +334480,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:159509$8597_Y + connect \Y $and$libresoc.v:161141$8645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159512$8600 + cell $and $and$libresoc.v:161144$8648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331994,10 +334491,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159512$8600_Y + connect \Y $and$libresoc.v:161144$8648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:159513$8601 + cell $and $and$libresoc.v:161145$8649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332005,10 +334502,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:159513$8601_Y + connect \Y $and$libresoc.v:161145$8649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159515$8603 + cell $and $and$libresoc.v:161147$8651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332016,10 +334513,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159515$8603_Y + connect \Y $and$libresoc.v:161147$8651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:159519$8607 + cell $and $and$libresoc.v:161151$8655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332027,10 +334524,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:159519$8607_Y + connect \Y $and$libresoc.v:161151$8655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:159521$8609 + cell $and $and$libresoc.v:161153$8657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332038,10 +334535,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:159521$8609_Y + connect \Y $and$libresoc.v:161153$8657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:159523$8611 + cell $and $and$libresoc.v:161155$8659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332049,10 +334546,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:159523$8611_Y + connect \Y $and$libresoc.v:161155$8659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:159527$8615 + cell $and $and$libresoc.v:161159$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332060,10 +334557,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:159527$8615_Y + connect \Y $and$libresoc.v:161159$8663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:159528$8616 + cell $and $and$libresoc.v:161160$8664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332071,10 +334568,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:159528$8616_Y + connect \Y $and$libresoc.v:161160$8664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:159531$8619 + cell $and $and$libresoc.v:161163$8667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332082,26 +334579,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:159531$8619_Y + connect \Y $and$libresoc.v:161163$8667_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:159498$8584 + cell $pos $extend$libresoc.v:161130$8632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:159498$8584_Y + connect \Y $extend$libresoc.v:161130$8632_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:159499$8586 + cell $pos $extend$libresoc.v:161131$8634 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:159499$8586_Y + connect \Y $extend$libresoc.v:161131$8634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:159510$8598 + cell $mul $mul$libresoc.v:161142$8646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -332109,10 +334606,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:159510$8598_Y + connect \Y $mul$libresoc.v:161142$8646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:159516$8604 + cell $mul $mul$libresoc.v:161148$8652 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -332120,106 +334617,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:159516$8604_Y + connect \Y $mul$libresoc.v:161148$8652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:159491$8577 + cell $not $not$libresoc.v:161123$8625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:159491$8577_Y + connect \Y $not$libresoc.v:161123$8625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159493$8579 + cell $not $not$libresoc.v:161125$8627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:159493$8579_Y + connect \Y $not$libresoc.v:161125$8627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159495$8581 + cell $not $not$libresoc.v:161127$8629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:159495$8581_Y + connect \Y $not$libresoc.v:161127$8629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:159505$8593 + cell $not $not$libresoc.v:161137$8641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:159505$8593_Y + connect \Y $not$libresoc.v:161137$8641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:159508$8596 + cell $not $not$libresoc.v:161140$8644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:159508$8596_Y + connect \Y $not$libresoc.v:161140$8644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:159514$8602 + cell $not $not$libresoc.v:161146$8650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:159514$8602_Y + connect \Y $not$libresoc.v:161146$8650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:159517$8605 + cell $not $not$libresoc.v:161149$8653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:159517$8605_Y + connect \Y $not$libresoc.v:161149$8653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:159524$8612 + cell $not $not$libresoc.v:161156$8660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:159524$8612_Y + connect \Y $not$libresoc.v:161156$8660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:159525$8613 + cell $not $not$libresoc.v:161157$8661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:159525$8613_Y + connect \Y $not$libresoc.v:161157$8661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:159526$8614 + cell $not $not$libresoc.v:161158$8662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:159526$8614_Y + connect \Y $not$libresoc.v:161158$8662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:159529$8617 + cell $not $not$libresoc.v:161161$8665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:159529$8617_Y + connect \Y $not$libresoc.v:161161$8665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:159530$8618 + cell $not $not$libresoc.v:161162$8666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:159530$8618_Y + connect \Y $not$libresoc.v:161162$8666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:159506$8594 + cell $or $or$libresoc.v:161138$8642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332227,10 +334724,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:159506$8594_Y + connect \Y $or$libresoc.v:161138$8642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:159507$8595 + cell $or $or$libresoc.v:161139$8643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332238,10 +334735,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159507$8595_Y + connect \Y $or$libresoc.v:161139$8643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:159520$8608 + cell $or $or$libresoc.v:161152$8656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332249,10 +334746,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159520$8608_Y + connect \Y $or$libresoc.v:161152$8656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:159522$8610 + cell $or $or$libresoc.v:161154$8658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332260,26 +334757,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:159522$8610_Y + connect \Y $or$libresoc.v:161154$8658_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:159498$8585 + cell $pos $pos$libresoc.v:161130$8633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:159498$8584_Y - connect \Y $pos$libresoc.v:159498$8585_Y + connect \A $extend$libresoc.v:161130$8632_Y + connect \Y $pos$libresoc.v:161130$8633_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:159499$8587 + cell $pos $pos$libresoc.v:161131$8635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:159499$8586_Y - connect \Y $pos$libresoc.v:159499$8587_Y + connect \A $extend$libresoc.v:161131$8634_Y + connect \Y $pos$libresoc.v:161131$8635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:159518$8606 + cell $sshl $sshl$libresoc.v:161150$8654 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -332287,10 +334784,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:159518$8606_Y + connect \Y $sshl$libresoc.v:161150$8654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:159511$8599 + cell $sshr $sshr$libresoc.v:161143$8647 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -332298,10 +334795,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:159511$8599_Y + connect \Y $sshr$libresoc.v:161143$8647_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:159548.11-159555.4" + attribute \src "libresoc.v:161180.11-161187.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332311,7 +334808,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:159556.10-159562.4" + attribute \src "libresoc.v:161188.10-161194.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332320,7 +334817,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:159563.9-159569.4" + attribute \src "libresoc.v:161195.9-161201.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332329,7 +334826,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:159570.13-159576.4" + attribute \src "libresoc.v:161202.13-161208.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332338,7 +334835,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:159577.10-159582.4" + attribute \src "libresoc.v:161209.10-161214.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -332346,7 +334843,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:159583.11-159589.4" + attribute \src "libresoc.v:161215.11-161221.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332355,7 +334852,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:159590.13-159596.4" + attribute \src "libresoc.v:161222.13-161228.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332364,7 +334861,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:159597.11-159603.4" + attribute \src "libresoc.v:161229.11-161235.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332373,7 +334870,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:159604.11-159610.4" + attribute \src "libresoc.v:161236.11-161242.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -332381,143 +334878,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:159246.7-159246.20" - process $proc$libresoc.v:159246$8674 + attribute \src "libresoc.v:160878.7-160878.20" + process $proc$libresoc.v:160878$8722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159340.7-159340.34" - process $proc$libresoc.v:159340$8675 + attribute \src "libresoc.v:160972.7-160972.34" + process $proc$libresoc.v:160972$8723 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:159344.7-159344.24" - process $proc$libresoc.v:159344$8676 + attribute \src "libresoc.v:160976.7-160976.24" + process $proc$libresoc.v:160976$8724 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:159366.13-159366.29" - process $proc$libresoc.v:159366$8677 + attribute \src "libresoc.v:160998.13-160998.29" + process $proc$libresoc.v:160998$8725 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:159380.7-159380.21" - process $proc$libresoc.v:159380$8678 + attribute \src "libresoc.v:161012.7-161012.21" + process $proc$libresoc.v:161012$8726 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:159423.7-159423.29" - process $proc$libresoc.v:159423$8679 + attribute \src "libresoc.v:161055.7-161055.29" + process $proc$libresoc.v:161055$8727 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:159435.7-159435.25" - process $proc$libresoc.v:159435$8680 + attribute \src "libresoc.v:161067.7-161067.25" + process $proc$libresoc.v:161067$8728 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:159455.7-159455.31" - process $proc$libresoc.v:159455$8681 + attribute \src "libresoc.v:161087.7-161087.31" + process $proc$libresoc.v:161087$8729 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:159463.7-159463.21" - process $proc$libresoc.v:159463$8682 + attribute \src "libresoc.v:161095.7-161095.21" + process $proc$libresoc.v:161095$8730 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:159532.3-159533.47" - process $proc$libresoc.v:159532$8620 + attribute \src "libresoc.v:161164.3-161165.47" + process $proc$libresoc.v:161164$8668 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:159534.3-159535.35" - process $proc$libresoc.v:159534$8621 + attribute \src "libresoc.v:161166.3-161167.35" + process $proc$libresoc.v:161166$8669 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:159536.3-159537.36" - process $proc$libresoc.v:159536$8622 + attribute \src "libresoc.v:161168.3-161169.36" + process $proc$libresoc.v:161168$8670 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:159538.3-159539.35" - process $proc$libresoc.v:159538$8623 + attribute \src "libresoc.v:161170.3-161171.35" + process $proc$libresoc.v:161170$8671 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:159540.3-159541.35" - process $proc$libresoc.v:159540$8624 + attribute \src "libresoc.v:161172.3-161173.35" + process $proc$libresoc.v:161172$8672 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:159542.3-159543.37" - process $proc$libresoc.v:159542$8625 + attribute \src "libresoc.v:161174.3-161175.37" + process $proc$libresoc.v:161174$8673 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:159544.3-159545.57" - process $proc$libresoc.v:159544$8626 + attribute \src "libresoc.v:161176.3-161177.57" + process $proc$libresoc.v:161176$8674 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:159546.3-159547.51" - process $proc$libresoc.v:159546$8627 + attribute \src "libresoc.v:161178.3-161179.51" + process $proc$libresoc.v:161178$8675 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:159611.3-159625.6" - process $proc$libresoc.v:159611$8628 + attribute \src "libresoc.v:161243.3-161257.6" + process $proc$libresoc.v:161243$8676 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8629 $2\st_done_s_st_done$next[0:0]$8631 - attribute \src "libresoc.v:159612.5-159612.29" + assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 + attribute \src "libresoc.v:161244.5-161244.29" switch \initial - attribute \src "libresoc.v:159612.9-159612.17" + attribute \src "libresoc.v:161244.9-161244.17" case 1'1 case end @@ -332526,30 +335023,30 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8630 1'1 + assign $1\st_done_s_st_done$next[0:0]$8678 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8630 1'0 + assign $1\st_done_s_st_done$next[0:0]$8678 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8631 1'0 + assign $2\st_done_s_st_done$next[0:0]$8679 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8631 $1\st_done_s_st_done$next[0:0]$8630 + assign $2\st_done_s_st_done$next[0:0]$8679 $1\st_done_s_st_done$next[0:0]$8678 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8629 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 end - attribute \src "libresoc.v:159626.3-159635.6" - process $proc$libresoc.v:159626$8632 + attribute \src "libresoc.v:161258.3-161267.6" + process $proc$libresoc.v:161258$8680 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:159627.5-159627.29" + attribute \src "libresoc.v:161259.5-161259.29" switch \initial - attribute \src "libresoc.v:159627.9-159627.17" + attribute \src "libresoc.v:161259.9-161259.17" case 1'1 case end @@ -332565,14 +335062,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:159636.3-159644.6" - process $proc$libresoc.v:159636$8633 + attribute \src "libresoc.v:161268.3-161276.6" + process $proc$libresoc.v:161268$8681 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8634 $1\busy_delay$next[0:0]$8635 - attribute \src "libresoc.v:159637.5-159637.29" + assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 + attribute \src "libresoc.v:161269.5-161269.29" switch \initial - attribute \src "libresoc.v:159637.9-159637.17" + attribute \src "libresoc.v:161269.9-161269.17" case 1'1 case end @@ -332581,21 +335078,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8635 1'0 + assign $1\busy_delay$next[0:0]$8683 1'0 case - assign $1\busy_delay$next[0:0]$8635 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8683 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8634 + update \busy_delay$next $0\busy_delay$next[0:0]$8682 end - attribute \src "libresoc.v:159645.3-159654.6" - process $proc$libresoc.v:159645$8636 + attribute \src "libresoc.v:161277.3-161286.6" + process $proc$libresoc.v:161277$8684 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:159646.5-159646.29" + attribute \src "libresoc.v:161278.5-161278.29" switch \initial - attribute \src "libresoc.v:159646.9-159646.17" + attribute \src "libresoc.v:161278.9-161278.17" case 1'1 case end @@ -332611,15 +335108,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:159655.3-159670.6" - process $proc$libresoc.v:159655$8637 + attribute \src "libresoc.v:161287.3-161302.6" + process $proc$libresoc.v:161287$8685 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:159656.5-159656.29" + attribute \src "libresoc.v:161288.5-161288.29" switch \initial - attribute \src "libresoc.v:159656.9-159656.17" + attribute \src "libresoc.v:161288.9-161288.17" case 1'1 case end @@ -332644,15 +335141,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:159671.3-159686.6" - process $proc$libresoc.v:159671$8638 + attribute \src "libresoc.v:161303.3-161318.6" + process $proc$libresoc.v:161303$8686 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:159672.5-159672.29" + attribute \src "libresoc.v:161304.5-161304.29" switch \initial - attribute \src "libresoc.v:159672.9-159672.17" + attribute \src "libresoc.v:161304.9-161304.17" case 1'1 case end @@ -332677,15 +335174,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:159687.3-159712.6" - process $proc$libresoc.v:159687$8639 + attribute \src "libresoc.v:161319.3-161344.6" + process $proc$libresoc.v:161319$8687 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:159688.5-159688.29" + attribute \src "libresoc.v:161320.5-161320.29" switch \initial - attribute \src "libresoc.v:159688.9-159688.17" + attribute \src "libresoc.v:161320.9-161320.17" case 1'1 case end @@ -332728,15 +335225,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:159713.3-159738.6" - process $proc$libresoc.v:159713$8640 + attribute \src "libresoc.v:161345.3-161370.6" + process $proc$libresoc.v:161345$8688 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:159714.5-159714.29" + attribute \src "libresoc.v:161346.5-161346.29" switch \initial - attribute \src "libresoc.v:159714.9-159714.17" + attribute \src "libresoc.v:161346.9-161346.17" case 1'1 case end @@ -332779,15 +335276,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:159739.3-159764.6" - process $proc$libresoc.v:159739$8641 + attribute \src "libresoc.v:161371.3-161396.6" + process $proc$libresoc.v:161371$8689 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:159740.5-159740.29" + attribute \src "libresoc.v:161372.5-161372.29" switch \initial - attribute \src "libresoc.v:159740.9-159740.17" + attribute \src "libresoc.v:161372.9-161372.17" case 1'1 case end @@ -332830,15 +335327,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:159765.3-159795.6" - process $proc$libresoc.v:159765$8642 + attribute \src "libresoc.v:161397.3-161427.6" + process $proc$libresoc.v:161397$8690 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:159766.5-159766.29" + attribute \src "libresoc.v:161398.5-161398.29" switch \initial - attribute \src "libresoc.v:159766.9-159766.17" + attribute \src "libresoc.v:161398.9-161398.17" case 1'1 case end @@ -332890,15 +335387,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:159796.3-159811.6" - process $proc$libresoc.v:159796$8643 + attribute \src "libresoc.v:161428.3-161443.6" + process $proc$libresoc.v:161428$8691 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:159797.5-159797.29" + attribute \src "libresoc.v:161429.5-161429.29" switch \initial - attribute \src "libresoc.v:159797.9-159797.17" + attribute \src "libresoc.v:161429.9-161429.17" case 1'1 case end @@ -332923,14 +335420,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:159812.3-159821.6" - process $proc$libresoc.v:159812$8644 + attribute \src "libresoc.v:161444.3-161453.6" + process $proc$libresoc.v:161444$8692 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:159813.5-159813.29" + attribute \src "libresoc.v:161445.5-161445.29" switch \initial - attribute \src "libresoc.v:159813.9-159813.17" + attribute \src "libresoc.v:161445.9-161445.17" case 1'1 case end @@ -332946,14 +335443,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:159822.3-159831.6" - process $proc$libresoc.v:159822$8645 + attribute \src "libresoc.v:161454.3-161463.6" + process $proc$libresoc.v:161454$8693 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:159823.5-159823.29" + attribute \src "libresoc.v:161455.5-161455.29" switch \initial - attribute \src "libresoc.v:159823.9-159823.17" + attribute \src "libresoc.v:161455.9-161455.17" case 1'1 case end @@ -332969,14 +335466,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:159832.3-159841.6" - process $proc$libresoc.v:159832$8646 + attribute \src "libresoc.v:161464.3-161473.6" + process $proc$libresoc.v:161464$8694 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:159833.5-159833.29" + attribute \src "libresoc.v:161465.5-161465.29" switch \initial - attribute \src "libresoc.v:159833.9-159833.17" + attribute \src "libresoc.v:161465.9-161465.17" case 1'1 case end @@ -332992,14 +335489,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:159842.3-159851.6" - process $proc$libresoc.v:159842$8647 + attribute \src "libresoc.v:161474.3-161483.6" + process $proc$libresoc.v:161474$8695 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:159843.5-159843.29" + attribute \src "libresoc.v:161475.5-161475.29" switch \initial - attribute \src "libresoc.v:159843.9-159843.17" + attribute \src "libresoc.v:161475.9-161475.17" case 1'1 case end @@ -333015,14 +335512,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:159852.3-159861.6" - process $proc$libresoc.v:159852$8648 + attribute \src "libresoc.v:161484.3-161493.6" + process $proc$libresoc.v:161484$8696 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:159853.5-159853.29" + attribute \src "libresoc.v:161485.5-161485.29" switch \initial - attribute \src "libresoc.v:159853.9-159853.17" + attribute \src "libresoc.v:161485.9-161485.17" case 1'1 case end @@ -333038,14 +335535,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:159862.3-159871.6" - process $proc$libresoc.v:159862$8649 + attribute \src "libresoc.v:161494.3-161503.6" + process $proc$libresoc.v:161494$8697 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:159863.5-159863.29" + attribute \src "libresoc.v:161495.5-161495.29" switch \initial - attribute \src "libresoc.v:159863.9-159863.17" + attribute \src "libresoc.v:161495.9-161495.17" case 1'1 case end @@ -333061,14 +335558,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:159872.3-159891.6" - process $proc$libresoc.v:159872$8650 + attribute \src "libresoc.v:161504.3-161523.6" + process $proc$libresoc.v:161504$8698 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:159873.5-159873.29" + attribute \src "libresoc.v:161505.5-161505.29" switch \initial - attribute \src "libresoc.v:159873.9-159873.17" + attribute \src "libresoc.v:161505.9-161505.17" case 1'1 case end @@ -333097,15 +335594,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:159892.3-159930.6" - process $proc$libresoc.v:159892$8651 + attribute \src "libresoc.v:161524.3-161562.6" + process $proc$libresoc.v:161524$8699 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8652 $5\fsm_state$next[1:0]$8657 - attribute \src "libresoc.v:159893.5-159893.29" + assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 + attribute \src "libresoc.v:161525.5-161525.29" switch \initial - attribute \src "libresoc.v:159893.9-159893.17" + attribute \src "libresoc.v:161525.9-161525.17" case 1'1 case end @@ -333114,65 +335611,65 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $2\fsm_state$next[1:0]$8654 + assign $1\fsm_state$next[1:0]$8701 $2\fsm_state$next[1:0]$8702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8654 2'01 + assign $2\fsm_state$next[1:0]$8702 2'01 case - assign $2\fsm_state$next[1:0]$8654 \fsm_state + assign $2\fsm_state$next[1:0]$8702 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $3\fsm_state$next[1:0]$8655 + assign $1\fsm_state$next[1:0]$8701 $3\fsm_state$next[1:0]$8703 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8655 2'10 + assign $3\fsm_state$next[1:0]$8703 2'10 case - assign $3\fsm_state$next[1:0]$8655 \fsm_state + assign $3\fsm_state$next[1:0]$8703 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8653 $4\fsm_state$next[1:0]$8656 + assign $1\fsm_state$next[1:0]$8701 $4\fsm_state$next[1:0]$8704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8656 2'00 + assign $4\fsm_state$next[1:0]$8704 2'00 case - assign $4\fsm_state$next[1:0]$8656 \fsm_state + assign $4\fsm_state$next[1:0]$8704 \fsm_state end case - assign $1\fsm_state$next[1:0]$8653 \fsm_state + assign $1\fsm_state$next[1:0]$8701 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8657 2'00 + assign $5\fsm_state$next[1:0]$8705 2'00 case - assign $5\fsm_state$next[1:0]$8657 $1\fsm_state$next[1:0]$8653 + assign $5\fsm_state$next[1:0]$8705 $1\fsm_state$next[1:0]$8701 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8652 + update \fsm_state$next $0\fsm_state$next[1:0]$8700 end - attribute \src "libresoc.v:159931.3-159940.6" - process $proc$libresoc.v:159931$8658 + attribute \src "libresoc.v:161563.3-161572.6" + process $proc$libresoc.v:161563$8706 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:159932.5-159932.29" + attribute \src "libresoc.v:161564.5-161564.29" switch \initial - attribute \src "libresoc.v:159932.9-159932.17" + attribute \src "libresoc.v:161564.9-161564.17" case 1'1 case end @@ -333188,14 +335685,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:159941.3-159949.6" - process $proc$libresoc.v:159941$8659 + attribute \src "libresoc.v:161573.3-161581.6" + process $proc$libresoc.v:161573$8707 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8660 $1\lsui_active_dly$next[0:0]$8661 - attribute \src "libresoc.v:159942.5-159942.29" + assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 + attribute \src "libresoc.v:161574.5-161574.29" switch \initial - attribute \src "libresoc.v:159942.9-159942.17" + attribute \src "libresoc.v:161574.9-161574.17" case 1'1 case end @@ -333204,21 +335701,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8661 1'0 + assign $1\lsui_active_dly$next[0:0]$8709 1'0 case - assign $1\lsui_active_dly$next[0:0]$8661 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8709 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8660 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 end - attribute \src "libresoc.v:159950.3-159959.6" - process $proc$libresoc.v:159950$8662 + attribute \src "libresoc.v:161582.3-161591.6" + process $proc$libresoc.v:161582$8710 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:159951.5-159951.29" + attribute \src "libresoc.v:161583.5-161583.29" switch \initial - attribute \src "libresoc.v:159951.9-159951.17" + attribute \src "libresoc.v:161583.9-161583.17" case 1'1 case end @@ -333234,14 +335731,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:159960.3-159969.6" - process $proc$libresoc.v:159960$8663 + attribute \src "libresoc.v:161592.3-161601.6" + process $proc$libresoc.v:161592$8711 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:159961.5-159961.29" + attribute \src "libresoc.v:161593.5-161593.29" switch \initial - attribute \src "libresoc.v:159961.9-159961.17" + attribute \src "libresoc.v:161593.9-161593.17" case 1'1 case end @@ -333257,15 +335754,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:159970.3-159985.6" - process $proc$libresoc.v:159970$8664 + attribute \src "libresoc.v:161602.3-161617.6" + process $proc$libresoc.v:161602$8712 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:159971.5-159971.29" + attribute \src "libresoc.v:161603.5-161603.29" switch \initial - attribute \src "libresoc.v:159971.9-159971.17" + attribute \src "libresoc.v:161603.9-161603.17" case 1'1 case end @@ -333290,16 +335787,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:159986.3-160021.6" - process $proc$libresoc.v:159986$8665 + attribute \src "libresoc.v:161618.3-161653.6" + process $proc$libresoc.v:161618$8713 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8666 $6\adrok_l_s_addr_acked$next[0:0]$8672 - attribute \src "libresoc.v:159987.5-159987.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "libresoc.v:161619.5-161619.29" switch \initial - attribute \src "libresoc.v:159987.9-159987.17" + attribute \src "libresoc.v:161619.9-161619.17" case 1'1 case end @@ -333308,67 +335805,67 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8667 $2\adrok_l_s_addr_acked$next[0:0]$8668 + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 $2\adrok_l_s_addr_acked$next[0:0]$8716 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8668 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8667 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8715 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $4\adrok_l_s_addr_acked$next[0:0]$8670 + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $4\adrok_l_s_addr_acked$next[0:0]$8718 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $5\adrok_l_s_addr_acked$next[0:0]$8671 + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $5\adrok_l_s_addr_acked$next[0:0]$8719 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8671 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8671 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $5\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8715 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8670 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $1\adrok_l_s_addr_acked$next[0:0]$8715 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8669 $1\adrok_l_s_addr_acked$next[0:0]$8667 + assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $1\adrok_l_s_addr_acked$next[0:0]$8715 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8672 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8672 $3\adrok_l_s_addr_acked$next[0:0]$8669 + assign $6\adrok_l_s_addr_acked$next[0:0]$8720 $3\adrok_l_s_addr_acked$next[0:0]$8717 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8666 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 end - attribute \src "libresoc.v:160022.3-160037.6" - process $proc$libresoc.v:160022$8673 + attribute \src "libresoc.v:161654.3-161669.6" + process $proc$libresoc.v:161654$8721 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:160023.5-160023.29" + attribute \src "libresoc.v:161655.5-161655.29" switch \initial - attribute \src "libresoc.v:160023.9-160023.17" + attribute \src "libresoc.v:161655.9-161655.17" case 1'1 case end @@ -333393,47 +335890,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:159491$8577_Y - connect \$11 $and$libresoc.v:159492$8578_Y - connect \$13 $not$libresoc.v:159493$8579_Y - connect \$15 $and$libresoc.v:159494$8580_Y - connect \$17 $not$libresoc.v:159495$8581_Y - connect \$1 $and$libresoc.v:159496$8582_Y - connect \$19 $and$libresoc.v:159497$8583_Y - connect \$21 $pos$libresoc.v:159498$8585_Y - connect \$23 $pos$libresoc.v:159499$8587_Y - connect \$25 $and$libresoc.v:159500$8588_Y - connect \$27 $and$libresoc.v:159501$8589_Y - connect \$29 $and$libresoc.v:159502$8590_Y - connect \$31 $and$libresoc.v:159503$8591_Y - connect \$33 $and$libresoc.v:159504$8592_Y - connect \$35 $not$libresoc.v:159505$8593_Y - connect \$38 $or$libresoc.v:159506$8594_Y - connect \$3 $or$libresoc.v:159507$8595_Y - connect \$37 $not$libresoc.v:159508$8596_Y - connect \$42 $and$libresoc.v:159509$8597_Y - connect \$44 $mul$libresoc.v:159510$8598_Y - connect \$46 $sshr$libresoc.v:159511$8599_Y - connect \$48 $and$libresoc.v:159512$8600_Y - connect \$50 $and$libresoc.v:159513$8601_Y - connect \$52 $not$libresoc.v:159514$8602_Y - connect \$54 $and$libresoc.v:159515$8603_Y - connect \$57 $mul$libresoc.v:159516$8604_Y - connect \$5 $not$libresoc.v:159517$8605_Y - connect \$59 $sshl$libresoc.v:159518$8606_Y - connect \$61 $and$libresoc.v:159519$8607_Y - connect \$63 $or$libresoc.v:159520$8608_Y - connect \$65 $and$libresoc.v:159521$8609_Y - connect \$67 $or$libresoc.v:159522$8610_Y - connect \$69 $and$libresoc.v:159523$8611_Y - connect \$71 $not$libresoc.v:159524$8612_Y - connect \$73 $not$libresoc.v:159525$8613_Y - connect \$75 $not$libresoc.v:159526$8614_Y - connect \$77 $and$libresoc.v:159527$8615_Y - connect \$7 $and$libresoc.v:159528$8616_Y - connect \$79 $not$libresoc.v:159529$8617_Y - connect \$81 $not$libresoc.v:159530$8618_Y - connect \$83 $and$libresoc.v:159531$8619_Y + connect \$9 $not$libresoc.v:161123$8625_Y + connect \$11 $and$libresoc.v:161124$8626_Y + connect \$13 $not$libresoc.v:161125$8627_Y + connect \$15 $and$libresoc.v:161126$8628_Y + connect \$17 $not$libresoc.v:161127$8629_Y + connect \$1 $and$libresoc.v:161128$8630_Y + connect \$19 $and$libresoc.v:161129$8631_Y + connect \$21 $pos$libresoc.v:161130$8633_Y + connect \$23 $pos$libresoc.v:161131$8635_Y + connect \$25 $and$libresoc.v:161132$8636_Y + connect \$27 $and$libresoc.v:161133$8637_Y + connect \$29 $and$libresoc.v:161134$8638_Y + connect \$31 $and$libresoc.v:161135$8639_Y + connect \$33 $and$libresoc.v:161136$8640_Y + connect \$35 $not$libresoc.v:161137$8641_Y + connect \$38 $or$libresoc.v:161138$8642_Y + connect \$3 $or$libresoc.v:161139$8643_Y + connect \$37 $not$libresoc.v:161140$8644_Y + connect \$42 $and$libresoc.v:161141$8645_Y + connect \$44 $mul$libresoc.v:161142$8646_Y + connect \$46 $sshr$libresoc.v:161143$8647_Y + connect \$48 $and$libresoc.v:161144$8648_Y + connect \$50 $and$libresoc.v:161145$8649_Y + connect \$52 $not$libresoc.v:161146$8650_Y + connect \$54 $and$libresoc.v:161147$8651_Y + connect \$57 $mul$libresoc.v:161148$8652_Y + connect \$5 $not$libresoc.v:161149$8653_Y + connect \$59 $sshl$libresoc.v:161150$8654_Y + connect \$61 $and$libresoc.v:161151$8655_Y + connect \$63 $or$libresoc.v:161152$8656_Y + connect \$65 $and$libresoc.v:161153$8657_Y + connect \$67 $or$libresoc.v:161154$8658_Y + connect \$69 $and$libresoc.v:161155$8659_Y + connect \$71 $not$libresoc.v:161156$8660_Y + connect \$73 $not$libresoc.v:161157$8661_Y + connect \$75 $not$libresoc.v:161158$8662_Y + connect \$77 $and$libresoc.v:161159$8663_Y + connect \$7 $and$libresoc.v:161160$8664_Y + connect \$79 $not$libresoc.v:161161$8665_Y + connect \$81 $not$libresoc.v:161162$8666_Y + connect \$83 $and$libresoc.v:161163$8667_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -333456,116 +335953,116 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:160063.1-160843.10" +attribute \src "libresoc.v:161695.1-162475.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:160806.3-160824.6" - wire width 4 $0\cr_a$6$next[3:0]$8729 - attribute \src "libresoc.v:160670.3-160671.31" - wire width 4 $0\cr_a$6[3:0]$8685 - attribute \src "libresoc.v:160077.13-160077.28" - wire width 4 $0\cr_a$6[3:0]$8735 - attribute \src "libresoc.v:160806.3-160824.6" - wire $0\cr_a_ok$next[0:0]$8728 - attribute \src "libresoc.v:160672.3-160673.31" + attribute \src "libresoc.v:162438.3-162456.6" + wire width 4 $0\cr_a$6$next[3:0]$8777 + attribute \src "libresoc.v:162302.3-162303.31" + wire width 4 $0\cr_a$6[3:0]$8733 + attribute \src "libresoc.v:161709.13-161709.28" + wire width 4 $0\cr_a$6[3:0]$8783 + attribute \src "libresoc.v:162438.3-162456.6" + wire $0\cr_a_ok$next[0:0]$8776 + attribute \src "libresoc.v:162304.3-162305.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:160753.3-160767.6" - wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8709 - attribute \src "libresoc.v:160684.3-160685.51" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8695 - attribute \src "libresoc.v:160142.14-160142.43" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8738 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8710 - attribute \src "libresoc.v:160686.3-160687.45" - wire width 32 $0\cr_op__insn$4[31:0]$8697 - attribute \src "libresoc.v:160151.14-160151.37" - wire width 32 $0\cr_op__insn$4[31:0]$8740 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8711 - attribute \src "libresoc.v:160682.3-160683.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8693 - attribute \src "libresoc.v:160385.13-160385.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8742 - attribute \src "libresoc.v:160787.3-160805.6" - wire width 32 $0\full_cr$5$next[31:0]$8722 - attribute \src "libresoc.v:160674.3-160675.37" - wire width 32 $0\full_cr$5[31:0]$8688 - attribute \src "libresoc.v:160394.14-160394.33" - wire width 32 $0\full_cr$5[31:0]$8744 - attribute \src "libresoc.v:160787.3-160805.6" - wire $0\full_cr_ok$next[0:0]$8723 - attribute \src "libresoc.v:160676.3-160677.37" + attribute \src "libresoc.v:162385.3-162399.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 + attribute \src "libresoc.v:162316.3-162317.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 + attribute \src "libresoc.v:161774.14-161774.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8758 + attribute \src "libresoc.v:162318.3-162319.45" + wire width 32 $0\cr_op__insn$4[31:0]$8745 + attribute \src "libresoc.v:161783.14-161783.37" + wire width 32 $0\cr_op__insn$4[31:0]$8788 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8759 + attribute \src "libresoc.v:162314.3-162315.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8741 + attribute \src "libresoc.v:162017.13-162017.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8790 + attribute \src "libresoc.v:162419.3-162437.6" + wire width 32 $0\full_cr$5$next[31:0]$8770 + attribute \src "libresoc.v:162306.3-162307.37" + wire width 32 $0\full_cr$5[31:0]$8736 + attribute \src "libresoc.v:162026.14-162026.33" + wire width 32 $0\full_cr$5[31:0]$8792 + attribute \src "libresoc.v:162419.3-162437.6" + wire $0\full_cr_ok$next[0:0]$8771 + attribute \src "libresoc.v:162308.3-162309.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:160064.7-160064.20" + attribute \src "libresoc.v:161696.7-161696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160740.3-160752.6" - wire width 2 $0\muxid$1$next[1:0]$8706 - attribute \src "libresoc.v:160688.3-160689.33" - wire width 2 $0\muxid$1[1:0]$8699 - attribute \src "libresoc.v:160628.13-160628.29" + attribute \src "libresoc.v:162372.3-162384.6" + wire width 2 $0\muxid$1$next[1:0]$8754 + attribute \src "libresoc.v:162320.3-162321.33" wire width 2 $0\muxid$1[1:0]$8747 - attribute \src "libresoc.v:160768.3-160786.6" - wire width 64 $0\o$next[63:0]$8716 - attribute \src "libresoc.v:160678.3-160679.19" + attribute \src "libresoc.v:162260.13-162260.29" + wire width 2 $0\muxid$1[1:0]$8795 + attribute \src "libresoc.v:162400.3-162418.6" + wire width 64 $0\o$next[63:0]$8764 + attribute \src "libresoc.v:162310.3-162311.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160768.3-160786.6" - wire $0\o_ok$next[0:0]$8717 - attribute \src "libresoc.v:160680.3-160681.25" + attribute \src "libresoc.v:162400.3-162418.6" + wire $0\o_ok$next[0:0]$8765 + attribute \src "libresoc.v:162312.3-162313.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:160722.3-160739.6" - wire $0\r_busy$next[0:0]$8702 - attribute \src "libresoc.v:160690.3-160691.29" + attribute \src "libresoc.v:162354.3-162371.6" + wire $0\r_busy$next[0:0]$8750 + attribute \src "libresoc.v:162322.3-162323.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:160806.3-160824.6" - wire width 4 $1\cr_a$6$next[3:0]$8731 - attribute \src "libresoc.v:160806.3-160824.6" - wire $1\cr_a_ok$next[0:0]$8730 - attribute \src "libresoc.v:160082.7-160082.21" + attribute \src "libresoc.v:162438.3-162456.6" + wire width 4 $1\cr_a$6$next[3:0]$8779 + attribute \src "libresoc.v:162438.3-162456.6" + wire $1\cr_a_ok$next[0:0]$8778 + attribute \src "libresoc.v:161714.7-161714.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:160753.3-160767.6" - wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8712 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8713 - attribute \src "libresoc.v:160753.3-160767.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8714 - attribute \src "libresoc.v:160787.3-160805.6" - wire width 32 $1\full_cr$5$next[31:0]$8724 - attribute \src "libresoc.v:160787.3-160805.6" - wire $1\full_cr_ok$next[0:0]$8725 - attribute \src "libresoc.v:160399.7-160399.24" + attribute \src "libresoc.v:162385.3-162399.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8760 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8761 + attribute \src "libresoc.v:162385.3-162399.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8762 + attribute \src "libresoc.v:162419.3-162437.6" + wire width 32 $1\full_cr$5$next[31:0]$8772 + attribute \src "libresoc.v:162419.3-162437.6" + wire $1\full_cr_ok$next[0:0]$8773 + attribute \src "libresoc.v:162031.7-162031.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:160740.3-160752.6" - wire width 2 $1\muxid$1$next[1:0]$8707 - attribute \src "libresoc.v:160768.3-160786.6" - wire width 64 $1\o$next[63:0]$8718 - attribute \src "libresoc.v:160641.14-160641.38" + attribute \src "libresoc.v:162372.3-162384.6" + wire width 2 $1\muxid$1$next[1:0]$8755 + attribute \src "libresoc.v:162400.3-162418.6" + wire width 64 $1\o$next[63:0]$8766 + attribute \src "libresoc.v:162273.14-162273.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160768.3-160786.6" - wire $1\o_ok$next[0:0]$8719 - attribute \src "libresoc.v:160648.7-160648.18" + attribute \src "libresoc.v:162400.3-162418.6" + wire $1\o_ok$next[0:0]$8767 + attribute \src "libresoc.v:162280.7-162280.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:160722.3-160739.6" - wire $1\r_busy$next[0:0]$8703 - attribute \src "libresoc.v:160662.7-160662.20" + attribute \src "libresoc.v:162354.3-162371.6" + wire $1\r_busy$next[0:0]$8751 + attribute \src "libresoc.v:162294.7-162294.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:160806.3-160824.6" - wire $2\cr_a_ok$next[0:0]$8732 - attribute \src "libresoc.v:160787.3-160805.6" - wire $2\full_cr_ok$next[0:0]$8726 - attribute \src "libresoc.v:160768.3-160786.6" - wire $2\o_ok$next[0:0]$8720 - attribute \src "libresoc.v:160722.3-160739.6" - wire $2\r_busy$next[0:0]$8704 - attribute \src "libresoc.v:160669.18-160669.118" - wire $and$libresoc.v:160669$8683_Y + attribute \src "libresoc.v:162438.3-162456.6" + wire $2\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:162419.3-162437.6" + wire $2\full_cr_ok$next[0:0]$8774 + attribute \src "libresoc.v:162400.3-162418.6" + wire $2\o_ok$next[0:0]$8768 + attribute \src "libresoc.v:162354.3-162371.6" + wire $2\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:162301.18-162301.118" + wire $and$libresoc.v:162301$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a @@ -333893,7 +336390,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:160064.7-160064.15" + attribute \src "libresoc.v:161696.7-161696.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -334158,7 +336655,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:160669$8683 + cell $and $and$libresoc.v:162301$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334166,10 +336663,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:160669$8683_Y + connect \Y $and$libresoc.v:162301$8731_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:160692.12-160713.4" + attribute \src "libresoc.v:162324.12-162345.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -334193,199 +336690,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:160714.9-160717.4" + attribute \src "libresoc.v:162346.9-162349.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:160718.9-160721.4" + attribute \src "libresoc.v:162350.9-162353.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160064.7-160064.20" - process $proc$libresoc.v:160064$8733 + attribute \src "libresoc.v:161696.7-161696.20" + process $proc$libresoc.v:161696$8781 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160077.13-160077.28" - process $proc$libresoc.v:160077$8734 + attribute \src "libresoc.v:161709.13-161709.28" + process $proc$libresoc.v:161709$8782 assign { } { } - assign $0\cr_a$6[3:0]$8735 4'0000 + assign $0\cr_a$6[3:0]$8783 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8735 + update \cr_a$6 $0\cr_a$6[3:0]$8783 end - attribute \src "libresoc.v:160082.7-160082.21" - process $proc$libresoc.v:160082$8736 + attribute \src "libresoc.v:161714.7-161714.21" + process $proc$libresoc.v:161714$8784 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:160142.14-160142.43" - process $proc$libresoc.v:160142$8737 + attribute \src "libresoc.v:161774.14-161774.43" + process $proc$libresoc.v:161774$8785 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8738 14'00000000000000 + assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8738 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 end - attribute \src "libresoc.v:160151.14-160151.37" - process $proc$libresoc.v:160151$8739 + attribute \src "libresoc.v:161783.14-161783.37" + process $proc$libresoc.v:161783$8787 assign { } { } - assign $0\cr_op__insn$4[31:0]$8740 0 + assign $0\cr_op__insn$4[31:0]$8788 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8740 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 end - attribute \src "libresoc.v:160385.13-160385.41" - process $proc$libresoc.v:160385$8741 + attribute \src "libresoc.v:162017.13-162017.41" + process $proc$libresoc.v:162017$8789 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8742 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8742 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 end - attribute \src "libresoc.v:160394.14-160394.33" - process $proc$libresoc.v:160394$8743 + attribute \src "libresoc.v:162026.14-162026.33" + process $proc$libresoc.v:162026$8791 assign { } { } - assign $0\full_cr$5[31:0]$8744 0 + assign $0\full_cr$5[31:0]$8792 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8744 + update \full_cr$5 $0\full_cr$5[31:0]$8792 end - attribute \src "libresoc.v:160399.7-160399.24" - process $proc$libresoc.v:160399$8745 + attribute \src "libresoc.v:162031.7-162031.24" + process $proc$libresoc.v:162031$8793 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:160628.13-160628.29" - process $proc$libresoc.v:160628$8746 + attribute \src "libresoc.v:162260.13-162260.29" + process $proc$libresoc.v:162260$8794 assign { } { } - assign $0\muxid$1[1:0]$8747 2'00 + assign $0\muxid$1[1:0]$8795 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8747 + update \muxid$1 $0\muxid$1[1:0]$8795 end - attribute \src "libresoc.v:160641.14-160641.38" - process $proc$libresoc.v:160641$8748 + attribute \src "libresoc.v:162273.14-162273.38" + process $proc$libresoc.v:162273$8796 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:160648.7-160648.18" - process $proc$libresoc.v:160648$8749 + attribute \src "libresoc.v:162280.7-162280.18" + process $proc$libresoc.v:162280$8797 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:160662.7-160662.20" - process $proc$libresoc.v:160662$8750 + attribute \src "libresoc.v:162294.7-162294.20" + process $proc$libresoc.v:162294$8798 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:160670.3-160671.31" - process $proc$libresoc.v:160670$8684 + attribute \src "libresoc.v:162302.3-162303.31" + process $proc$libresoc.v:162302$8732 assign { } { } - assign $0\cr_a$6[3:0]$8685 \cr_a$6$next + assign $0\cr_a$6[3:0]$8733 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8685 + update \cr_a$6 $0\cr_a$6[3:0]$8733 end - attribute \src "libresoc.v:160672.3-160673.31" - process $proc$libresoc.v:160672$8686 + attribute \src "libresoc.v:162304.3-162305.31" + process $proc$libresoc.v:162304$8734 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:160674.3-160675.37" - process $proc$libresoc.v:160674$8687 + attribute \src "libresoc.v:162306.3-162307.37" + process $proc$libresoc.v:162306$8735 assign { } { } - assign $0\full_cr$5[31:0]$8688 \full_cr$5$next + assign $0\full_cr$5[31:0]$8736 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8688 + update \full_cr$5 $0\full_cr$5[31:0]$8736 end - attribute \src "libresoc.v:160676.3-160677.37" - process $proc$libresoc.v:160676$8689 + attribute \src "libresoc.v:162308.3-162309.37" + process $proc$libresoc.v:162308$8737 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:160678.3-160679.19" - process $proc$libresoc.v:160678$8690 + attribute \src "libresoc.v:162310.3-162311.19" + process $proc$libresoc.v:162310$8738 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:160680.3-160681.25" - process $proc$libresoc.v:160680$8691 + attribute \src "libresoc.v:162312.3-162313.25" + process $proc$libresoc.v:162312$8739 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:160682.3-160683.55" - process $proc$libresoc.v:160682$8692 + attribute \src "libresoc.v:162314.3-162315.55" + process $proc$libresoc.v:162314$8740 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8693 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8693 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 end - attribute \src "libresoc.v:160684.3-160685.51" - process $proc$libresoc.v:160684$8694 + attribute \src "libresoc.v:162316.3-162317.51" + process $proc$libresoc.v:162316$8742 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8695 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8695 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 end - attribute \src "libresoc.v:160686.3-160687.45" - process $proc$libresoc.v:160686$8696 + attribute \src "libresoc.v:162318.3-162319.45" + process $proc$libresoc.v:162318$8744 assign { } { } - assign $0\cr_op__insn$4[31:0]$8697 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8697 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 end - attribute \src "libresoc.v:160688.3-160689.33" - process $proc$libresoc.v:160688$8698 + attribute \src "libresoc.v:162320.3-162321.33" + process $proc$libresoc.v:162320$8746 assign { } { } - assign $0\muxid$1[1:0]$8699 \muxid$1$next + assign $0\muxid$1[1:0]$8747 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8699 + update \muxid$1 $0\muxid$1[1:0]$8747 end - attribute \src "libresoc.v:160690.3-160691.29" - process $proc$libresoc.v:160690$8700 + attribute \src "libresoc.v:162322.3-162323.29" + process $proc$libresoc.v:162322$8748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160722.3-160739.6" - process $proc$libresoc.v:160722$8701 + attribute \src "libresoc.v:162354.3-162371.6" + process $proc$libresoc.v:162354$8749 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8702 $2\r_busy$next[0:0]$8704 - attribute \src "libresoc.v:160723.5-160723.29" + assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:162355.5-162355.29" switch \initial - attribute \src "libresoc.v:160723.9-160723.17" + attribute \src "libresoc.v:162355.9-162355.17" case 1'1 case end @@ -334394,34 +336891,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8703 1'1 + assign $1\r_busy$next[0:0]$8751 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8703 1'0 + assign $1\r_busy$next[0:0]$8751 1'0 case - assign $1\r_busy$next[0:0]$8703 \r_busy + assign $1\r_busy$next[0:0]$8751 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8704 1'0 + assign $2\r_busy$next[0:0]$8752 1'0 case - assign $2\r_busy$next[0:0]$8704 $1\r_busy$next[0:0]$8703 + assign $2\r_busy$next[0:0]$8752 $1\r_busy$next[0:0]$8751 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8702 + update \r_busy$next $0\r_busy$next[0:0]$8750 end - attribute \src "libresoc.v:160740.3-160752.6" - process $proc$libresoc.v:160740$8705 + attribute \src "libresoc.v:162372.3-162384.6" + process $proc$libresoc.v:162372$8753 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8706 $1\muxid$1$next[1:0]$8707 - attribute \src "libresoc.v:160741.5-160741.29" + assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 + attribute \src "libresoc.v:162373.5-162373.29" switch \initial - attribute \src "libresoc.v:160741.9-160741.17" + attribute \src "libresoc.v:162373.9-162373.17" case 1'1 case end @@ -334430,31 +336927,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8707 \muxid$16 + assign $1\muxid$1$next[1:0]$8755 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8707 \muxid$16 + assign $1\muxid$1$next[1:0]$8755 \muxid$16 case - assign $1\muxid$1$next[1:0]$8707 \muxid$1 + assign $1\muxid$1$next[1:0]$8755 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8706 + update \muxid$1$next $0\muxid$1$next[1:0]$8754 end - attribute \src "libresoc.v:160753.3-160767.6" - process $proc$libresoc.v:160753$8708 + attribute \src "libresoc.v:162385.3-162399.6" + process $proc$libresoc.v:162385$8756 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[13:0]$8709 $1\cr_op__fn_unit$3$next[13:0]$8712 - assign $0\cr_op__insn$4$next[31:0]$8710 $1\cr_op__insn$4$next[31:0]$8713 - assign $0\cr_op__insn_type$2$next[6:0]$8711 $1\cr_op__insn_type$2$next[6:0]$8714 - attribute \src "libresoc.v:160754.5-160754.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 + assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 + assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 + attribute \src "libresoc.v:162386.5-162386.29" switch \initial - attribute \src "libresoc.v:160754.9-160754.17" + attribute \src "libresoc.v:162386.9-162386.17" case 1'1 case end @@ -334465,35 +336962,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8713 $1\cr_op__fn_unit$3$next[13:0]$8712 $1\cr_op__insn_type$2$next[6:0]$8714 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[13:0]$8712 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8713 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8714 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[13:0]$8760 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8761 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8762 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8709 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8710 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8711 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8757 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 end - attribute \src "libresoc.v:160768.3-160786.6" - process $proc$libresoc.v:160768$8715 + attribute \src "libresoc.v:162400.3-162418.6" + process $proc$libresoc.v:162400$8763 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8716 $1\o$next[63:0]$8718 + assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 assign { } { } - assign $0\o_ok$next[0:0]$8717 $2\o_ok$next[0:0]$8720 - attribute \src "libresoc.v:160769.5-160769.29" + assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 + attribute \src "libresoc.v:162401.5-162401.29" switch \initial - attribute \src "libresoc.v:160769.9-160769.17" + attribute \src "libresoc.v:162401.9-162401.17" case 1'1 case end @@ -334503,41 +337000,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8719 $1\o$next[63:0]$8718 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8718 \o - assign $1\o_ok$next[0:0]$8719 \o_ok + assign $1\o$next[63:0]$8766 \o + assign $1\o_ok$next[0:0]$8767 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8720 1'0 + assign $2\o_ok$next[0:0]$8768 1'0 case - assign $2\o_ok$next[0:0]$8720 $1\o_ok$next[0:0]$8719 + assign $2\o_ok$next[0:0]$8768 $1\o_ok$next[0:0]$8767 end sync always - update \o$next $0\o$next[63:0]$8716 - update \o_ok$next $0\o_ok$next[0:0]$8717 + update \o$next $0\o$next[63:0]$8764 + update \o_ok$next $0\o_ok$next[0:0]$8765 end - attribute \src "libresoc.v:160787.3-160805.6" - process $proc$libresoc.v:160787$8721 + attribute \src "libresoc.v:162419.3-162437.6" + process $proc$libresoc.v:162419$8769 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8722 $1\full_cr$5$next[31:0]$8724 + assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 assign { } { } - assign $0\full_cr_ok$next[0:0]$8723 $2\full_cr_ok$next[0:0]$8726 - attribute \src "libresoc.v:160788.5-160788.29" + assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 + attribute \src "libresoc.v:162420.5-162420.29" switch \initial - attribute \src "libresoc.v:160788.9-160788.17" + attribute \src "libresoc.v:162420.9-162420.17" case 1'1 case end @@ -334547,41 +337044,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8725 $1\full_cr$5$next[31:0]$8724 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8724 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8725 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8772 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8773 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8726 1'0 + assign $2\full_cr_ok$next[0:0]$8774 1'0 case - assign $2\full_cr_ok$next[0:0]$8726 $1\full_cr_ok$next[0:0]$8725 + assign $2\full_cr_ok$next[0:0]$8774 $1\full_cr_ok$next[0:0]$8773 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8722 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8723 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 end - attribute \src "libresoc.v:160806.3-160824.6" - process $proc$libresoc.v:160806$8727 + attribute \src "libresoc.v:162438.3-162456.6" + process $proc$libresoc.v:162438$8775 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8729 $1\cr_a$6$next[3:0]$8731 - assign $0\cr_a_ok$next[0:0]$8728 $2\cr_a_ok$next[0:0]$8732 - attribute \src "libresoc.v:160807.5-160807.29" + assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 + assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:162439.5-162439.29" switch \initial - attribute \src "libresoc.v:160807.9-160807.17" + attribute \src "libresoc.v:162439.9-162439.17" case 1'1 case end @@ -334591,30 +337088,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8730 $1\cr_a$6$next[3:0]$8731 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8730 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8731 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8778 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8779 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8732 1'0 + assign $2\cr_a_ok$next[0:0]$8780 1'0 case - assign $2\cr_a_ok$next[0:0]$8732 $1\cr_a_ok$next[0:0]$8730 + assign $2\cr_a_ok$next[0:0]$8780 $1\cr_a_ok$next[0:0]$8778 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8728 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8729 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 end - connect \$14 $and$libresoc.v:160669$8683_Y + connect \$14 $and$libresoc.v:162301$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -334634,155 +337131,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:160847.1-161707.10" +attribute \src "libresoc.v:162479.1-163339.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8787 - attribute \src "libresoc.v:161519.3-161520.43" - wire width 64 $0\br_op__cia$2[63:0]$8761 - attribute \src "libresoc.v:160855.14-160855.51" - wire width 64 $0\br_op__cia$2[63:0]$8825 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 14 $0\br_op__fn_unit$4$next[13:0]$8788 - attribute \src "libresoc.v:161523.3-161524.51" - wire width 14 $0\br_op__fn_unit$4[13:0]$8765 - attribute \src "libresoc.v:160911.14-160911.43" - wire width 14 $0\br_op__fn_unit$4[13:0]$8827 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8789 - attribute \src "libresoc.v:161527.3-161528.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8769 - attribute \src "libresoc.v:160920.14-160920.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8829 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8790 - attribute \src "libresoc.v:161529.3-161530.61" - wire $0\br_op__imm_data__ok$7[0:0]$8771 - attribute \src "libresoc.v:160929.7-160929.37" - wire $0\br_op__imm_data__ok$7[0:0]$8831 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8791 - attribute \src "libresoc.v:161525.3-161526.45" - wire width 32 $0\br_op__insn$5[31:0]$8767 - attribute \src "libresoc.v:160938.14-160938.37" - wire width 32 $0\br_op__insn$5[31:0]$8833 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8792 - attribute \src "libresoc.v:161521.3-161522.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8763 - attribute \src "libresoc.v:161172.13-161172.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8835 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__is_32bit$9$next[0:0]$8793 - attribute \src "libresoc.v:161533.3-161534.53" - wire $0\br_op__is_32bit$9[0:0]$8775 - attribute \src "libresoc.v:161181.7-161181.33" - wire $0\br_op__is_32bit$9[0:0]$8837 - attribute \src "libresoc.v:161607.3-161634.6" - wire $0\br_op__lk$8$next[0:0]$8794 - attribute \src "libresoc.v:161531.3-161532.41" - wire $0\br_op__lk$8[0:0]$8773 - attribute \src "libresoc.v:161190.7-161190.27" - wire $0\br_op__lk$8[0:0]$8839 - attribute \src "libresoc.v:161635.3-161653.6" - wire width 64 $0\fast1$10$next[63:0]$8806 - attribute \src "libresoc.v:161515.3-161516.35" - wire width 64 $0\fast1$10[63:0]$8758 - attribute \src "libresoc.v:161203.14-161203.47" - wire width 64 $0\fast1$10[63:0]$8841 - attribute \src "libresoc.v:161635.3-161653.6" - wire $0\fast1_ok$next[0:0]$8807 - attribute \src "libresoc.v:161517.3-161518.33" + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8835 + attribute \src "libresoc.v:163151.3-163152.43" + wire width 64 $0\br_op__cia$2[63:0]$8809 + attribute \src "libresoc.v:162487.14-162487.51" + wire width 64 $0\br_op__cia$2[63:0]$8873 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 + attribute \src "libresoc.v:163155.3-163156.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8813 + attribute \src "libresoc.v:162543.14-162543.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8875 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 + attribute \src "libresoc.v:163159.3-163160.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 + attribute \src "libresoc.v:162552.14-162552.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8838 + attribute \src "libresoc.v:163161.3-163162.61" + wire $0\br_op__imm_data__ok$7[0:0]$8819 + attribute \src "libresoc.v:162561.7-162561.37" + wire $0\br_op__imm_data__ok$7[0:0]$8879 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8839 + attribute \src "libresoc.v:163157.3-163158.45" + wire width 32 $0\br_op__insn$5[31:0]$8815 + attribute \src "libresoc.v:162570.14-162570.37" + wire width 32 $0\br_op__insn$5[31:0]$8881 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 + attribute \src "libresoc.v:163153.3-163154.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8811 + attribute \src "libresoc.v:162804.13-162804.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8883 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__is_32bit$9$next[0:0]$8841 + attribute \src "libresoc.v:163165.3-163166.53" + wire $0\br_op__is_32bit$9[0:0]$8823 + attribute \src "libresoc.v:162813.7-162813.33" + wire $0\br_op__is_32bit$9[0:0]$8885 + attribute \src "libresoc.v:163239.3-163266.6" + wire $0\br_op__lk$8$next[0:0]$8842 + attribute \src "libresoc.v:163163.3-163164.41" + wire $0\br_op__lk$8[0:0]$8821 + attribute \src "libresoc.v:162822.7-162822.27" + wire $0\br_op__lk$8[0:0]$8887 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $0\fast1$10$next[63:0]$8854 + attribute \src "libresoc.v:163147.3-163148.35" + wire width 64 $0\fast1$10[63:0]$8806 + attribute \src "libresoc.v:162835.14-162835.47" + wire width 64 $0\fast1$10[63:0]$8889 + attribute \src "libresoc.v:163267.3-163285.6" + wire $0\fast1_ok$next[0:0]$8855 + attribute \src "libresoc.v:163149.3-163150.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:161654.3-161672.6" - wire width 64 $0\fast2$11$next[63:0]$8812 - attribute \src "libresoc.v:161511.3-161512.35" - wire width 64 $0\fast2$11[63:0]$8755 - attribute \src "libresoc.v:161219.14-161219.47" - wire width 64 $0\fast2$11[63:0]$8844 - attribute \src "libresoc.v:161654.3-161672.6" - wire $0\fast2_ok$next[0:0]$8813 - attribute \src "libresoc.v:161513.3-161514.33" + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $0\fast2$11$next[63:0]$8860 + attribute \src "libresoc.v:163143.3-163144.35" + wire width 64 $0\fast2$11[63:0]$8803 + attribute \src "libresoc.v:162851.14-162851.47" + wire width 64 $0\fast2$11[63:0]$8892 + attribute \src "libresoc.v:163286.3-163304.6" + wire $0\fast2_ok$next[0:0]$8861 + attribute \src "libresoc.v:163145.3-163146.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:160848.7-160848.20" + attribute \src "libresoc.v:162480.7-162480.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161594.3-161606.6" - wire width 2 $0\muxid$1$next[1:0]$8784 - attribute \src "libresoc.v:161535.3-161536.33" - wire width 2 $0\muxid$1[1:0]$8777 - attribute \src "libresoc.v:161469.13-161469.29" - wire width 2 $0\muxid$1[1:0]$8847 - attribute \src "libresoc.v:161673.3-161691.6" - wire width 64 $0\nia$next[63:0]$8818 - attribute \src "libresoc.v:161507.3-161508.23" + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $0\muxid$1$next[1:0]$8832 + attribute \src "libresoc.v:163167.3-163168.33" + wire width 2 $0\muxid$1[1:0]$8825 + attribute \src "libresoc.v:163101.13-163101.29" + wire width 2 $0\muxid$1[1:0]$8895 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $0\nia$next[63:0]$8866 + attribute \src "libresoc.v:163139.3-163140.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:161673.3-161691.6" - wire $0\nia_ok$next[0:0]$8819 - attribute \src "libresoc.v:161509.3-161510.29" + attribute \src "libresoc.v:163305.3-163323.6" + wire $0\nia_ok$next[0:0]$8867 + attribute \src "libresoc.v:163141.3-163142.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:161576.3-161593.6" - wire $0\r_busy$next[0:0]$8780 - attribute \src "libresoc.v:161537.3-161538.29" + attribute \src "libresoc.v:163208.3-163225.6" + wire $0\r_busy$next[0:0]$8828 + attribute \src "libresoc.v:163169.3-163170.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8795 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 14 $1\br_op__fn_unit$4$next[13:0]$8796 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8797 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8798 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8799 - attribute \src "libresoc.v:161607.3-161634.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8800 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__is_32bit$9$next[0:0]$8801 - attribute \src "libresoc.v:161607.3-161634.6" - wire $1\br_op__lk$8$next[0:0]$8802 - attribute \src "libresoc.v:161635.3-161653.6" - wire width 64 $1\fast1$10$next[63:0]$8808 - attribute \src "libresoc.v:161635.3-161653.6" - wire $1\fast1_ok$next[0:0]$8809 - attribute \src "libresoc.v:161210.7-161210.22" + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8843 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8846 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8847 + attribute \src "libresoc.v:163239.3-163266.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__is_32bit$9$next[0:0]$8849 + attribute \src "libresoc.v:163239.3-163266.6" + wire $1\br_op__lk$8$next[0:0]$8850 + attribute \src "libresoc.v:163267.3-163285.6" + wire width 64 $1\fast1$10$next[63:0]$8856 + attribute \src "libresoc.v:163267.3-163285.6" + wire $1\fast1_ok$next[0:0]$8857 + attribute \src "libresoc.v:162842.7-162842.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:161654.3-161672.6" - wire width 64 $1\fast2$11$next[63:0]$8814 - attribute \src "libresoc.v:161654.3-161672.6" - wire $1\fast2_ok$next[0:0]$8815 - attribute \src "libresoc.v:161226.7-161226.22" + attribute \src "libresoc.v:163286.3-163304.6" + wire width 64 $1\fast2$11$next[63:0]$8862 + attribute \src "libresoc.v:163286.3-163304.6" + wire $1\fast2_ok$next[0:0]$8863 + attribute \src "libresoc.v:162858.7-162858.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:161594.3-161606.6" - wire width 2 $1\muxid$1$next[1:0]$8785 - attribute \src "libresoc.v:161673.3-161691.6" - wire width 64 $1\nia$next[63:0]$8820 - attribute \src "libresoc.v:161482.14-161482.40" + attribute \src "libresoc.v:163226.3-163238.6" + wire width 2 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163305.3-163323.6" + wire width 64 $1\nia$next[63:0]$8868 + attribute \src "libresoc.v:163114.14-163114.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:161673.3-161691.6" - wire $1\nia_ok$next[0:0]$8821 - attribute \src "libresoc.v:161489.7-161489.20" + attribute \src "libresoc.v:163305.3-163323.6" + wire $1\nia_ok$next[0:0]$8869 + attribute \src "libresoc.v:163121.7-163121.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:161576.3-161593.6" - wire $1\r_busy$next[0:0]$8781 - attribute \src "libresoc.v:161503.7-161503.20" + attribute \src "libresoc.v:163208.3-163225.6" + wire $1\r_busy$next[0:0]$8829 + attribute \src "libresoc.v:163135.7-163135.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:161607.3-161634.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8803 - attribute \src "libresoc.v:161607.3-161634.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8804 - attribute \src "libresoc.v:161635.3-161653.6" - wire $2\fast1_ok$next[0:0]$8810 - attribute \src "libresoc.v:161654.3-161672.6" - wire $2\fast2_ok$next[0:0]$8816 - attribute \src "libresoc.v:161673.3-161691.6" - wire $2\nia_ok$next[0:0]$8822 - attribute \src "libresoc.v:161576.3-161593.6" - wire $2\r_busy$next[0:0]$8782 - attribute \src "libresoc.v:161506.18-161506.118" - wire $and$libresoc.v:161506$8751_Y + attribute \src "libresoc.v:163239.3-163266.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 + attribute \src "libresoc.v:163239.3-163266.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163267.3-163285.6" + wire $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163286.3-163304.6" + wire $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163305.3-163323.6" + wire $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163208.3-163225.6" + wire $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163138.18-163138.118" + wire $and$libresoc.v:163138$8799_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -335119,9 +337616,9 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a @@ -335153,7 +337650,7 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:160848.7-160848.15" + attribute \src "libresoc.v:162480.7-162480.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -335428,7 +337925,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:161506$8751 + cell $and $and$libresoc.v:163138$8799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -335436,10 +337933,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:161506$8751_Y + connect \Y $and$libresoc.v:163138$8799_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161539.13-161567.4" + attribute \src "libresoc.v:163171.13-163199.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -335470,274 +337967,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:161568.10-161571.4" + attribute \src "libresoc.v:163200.10-163203.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161572.10-161575.4" + attribute \src "libresoc.v:163204.10-163207.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160848.7-160848.20" - process $proc$libresoc.v:160848$8823 + attribute \src "libresoc.v:162480.7-162480.20" + process $proc$libresoc.v:162480$8871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160855.14-160855.51" - process $proc$libresoc.v:160855$8824 + attribute \src "libresoc.v:162487.14-162487.51" + process $proc$libresoc.v:162487$8872 assign { } { } - assign $0\br_op__cia$2[63:0]$8825 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8825 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 end - attribute \src "libresoc.v:160911.14-160911.43" - process $proc$libresoc.v:160911$8826 + attribute \src "libresoc.v:162543.14-162543.43" + process $proc$libresoc.v:162543$8874 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8827 14'00000000000000 + assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8827 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 end - attribute \src "libresoc.v:160920.14-160920.62" - process $proc$libresoc.v:160920$8828 + attribute \src "libresoc.v:162552.14-162552.62" + process $proc$libresoc.v:162552$8876 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8829 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8829 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 end - attribute \src "libresoc.v:160929.7-160929.37" - process $proc$libresoc.v:160929$8830 + attribute \src "libresoc.v:162561.7-162561.37" + process $proc$libresoc.v:162561$8878 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8831 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8831 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 end - attribute \src "libresoc.v:160938.14-160938.37" - process $proc$libresoc.v:160938$8832 + attribute \src "libresoc.v:162570.14-162570.37" + process $proc$libresoc.v:162570$8880 assign { } { } - assign $0\br_op__insn$5[31:0]$8833 0 + assign $0\br_op__insn$5[31:0]$8881 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8833 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 end - attribute \src "libresoc.v:161172.13-161172.41" - process $proc$libresoc.v:161172$8834 + attribute \src "libresoc.v:162804.13-162804.41" + process $proc$libresoc.v:162804$8882 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8835 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8835 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 end - attribute \src "libresoc.v:161181.7-161181.33" - process $proc$libresoc.v:161181$8836 + attribute \src "libresoc.v:162813.7-162813.33" + process $proc$libresoc.v:162813$8884 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8837 1'0 + assign $0\br_op__is_32bit$9[0:0]$8885 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8837 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 end - attribute \src "libresoc.v:161190.7-161190.27" - process $proc$libresoc.v:161190$8838 + attribute \src "libresoc.v:162822.7-162822.27" + process $proc$libresoc.v:162822$8886 assign { } { } - assign $0\br_op__lk$8[0:0]$8839 1'0 + assign $0\br_op__lk$8[0:0]$8887 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8839 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 end - attribute \src "libresoc.v:161203.14-161203.47" - process $proc$libresoc.v:161203$8840 + attribute \src "libresoc.v:162835.14-162835.47" + process $proc$libresoc.v:162835$8888 assign { } { } - assign $0\fast1$10[63:0]$8841 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8841 + update \fast1$10 $0\fast1$10[63:0]$8889 end - attribute \src "libresoc.v:161210.7-161210.22" - process $proc$libresoc.v:161210$8842 + attribute \src "libresoc.v:162842.7-162842.22" + process $proc$libresoc.v:162842$8890 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:161219.14-161219.47" - process $proc$libresoc.v:161219$8843 + attribute \src "libresoc.v:162851.14-162851.47" + process $proc$libresoc.v:162851$8891 assign { } { } - assign $0\fast2$11[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8844 + update \fast2$11 $0\fast2$11[63:0]$8892 end - attribute \src "libresoc.v:161226.7-161226.22" - process $proc$libresoc.v:161226$8845 + attribute \src "libresoc.v:162858.7-162858.22" + process $proc$libresoc.v:162858$8893 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:161469.13-161469.29" - process $proc$libresoc.v:161469$8846 + attribute \src "libresoc.v:163101.13-163101.29" + process $proc$libresoc.v:163101$8894 assign { } { } - assign $0\muxid$1[1:0]$8847 2'00 + assign $0\muxid$1[1:0]$8895 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8847 + update \muxid$1 $0\muxid$1[1:0]$8895 end - attribute \src "libresoc.v:161482.14-161482.40" - process $proc$libresoc.v:161482$8848 + attribute \src "libresoc.v:163114.14-163114.40" + process $proc$libresoc.v:163114$8896 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:161489.7-161489.20" - process $proc$libresoc.v:161489$8849 + attribute \src "libresoc.v:163121.7-163121.20" + process $proc$libresoc.v:163121$8897 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:161503.7-161503.20" - process $proc$libresoc.v:161503$8850 + attribute \src "libresoc.v:163135.7-163135.20" + process $proc$libresoc.v:163135$8898 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161507.3-161508.23" - process $proc$libresoc.v:161507$8752 + attribute \src "libresoc.v:163139.3-163140.23" + process $proc$libresoc.v:163139$8800 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:161509.3-161510.29" - process $proc$libresoc.v:161509$8753 + attribute \src "libresoc.v:163141.3-163142.29" + process $proc$libresoc.v:163141$8801 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:161511.3-161512.35" - process $proc$libresoc.v:161511$8754 + attribute \src "libresoc.v:163143.3-163144.35" + process $proc$libresoc.v:163143$8802 assign { } { } - assign $0\fast2$11[63:0]$8755 \fast2$11$next + assign $0\fast2$11[63:0]$8803 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8755 + update \fast2$11 $0\fast2$11[63:0]$8803 end - attribute \src "libresoc.v:161513.3-161514.33" - process $proc$libresoc.v:161513$8756 + attribute \src "libresoc.v:163145.3-163146.33" + process $proc$libresoc.v:163145$8804 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:161515.3-161516.35" - process $proc$libresoc.v:161515$8757 + attribute \src "libresoc.v:163147.3-163148.35" + process $proc$libresoc.v:163147$8805 assign { } { } - assign $0\fast1$10[63:0]$8758 \fast1$10$next + assign $0\fast1$10[63:0]$8806 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8758 + update \fast1$10 $0\fast1$10[63:0]$8806 end - attribute \src "libresoc.v:161517.3-161518.33" - process $proc$libresoc.v:161517$8759 + attribute \src "libresoc.v:163149.3-163150.33" + process $proc$libresoc.v:163149$8807 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:161519.3-161520.43" - process $proc$libresoc.v:161519$8760 + attribute \src "libresoc.v:163151.3-163152.43" + process $proc$libresoc.v:163151$8808 assign { } { } - assign $0\br_op__cia$2[63:0]$8761 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8761 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 end - attribute \src "libresoc.v:161521.3-161522.55" - process $proc$libresoc.v:161521$8762 + attribute \src "libresoc.v:163153.3-163154.55" + process $proc$libresoc.v:163153$8810 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8763 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8763 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 end - attribute \src "libresoc.v:161523.3-161524.51" - process $proc$libresoc.v:161523$8764 + attribute \src "libresoc.v:163155.3-163156.51" + process $proc$libresoc.v:163155$8812 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8765 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8765 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 end - attribute \src "libresoc.v:161525.3-161526.45" - process $proc$libresoc.v:161525$8766 + attribute \src "libresoc.v:163157.3-163158.45" + process $proc$libresoc.v:163157$8814 assign { } { } - assign $0\br_op__insn$5[31:0]$8767 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8767 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 end - attribute \src "libresoc.v:161527.3-161528.65" - process $proc$libresoc.v:161527$8768 + attribute \src "libresoc.v:163159.3-163160.65" + process $proc$libresoc.v:163159$8816 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8769 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8769 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 end - attribute \src "libresoc.v:161529.3-161530.61" - process $proc$libresoc.v:161529$8770 + attribute \src "libresoc.v:163161.3-163162.61" + process $proc$libresoc.v:163161$8818 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8771 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8771 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 end - attribute \src "libresoc.v:161531.3-161532.41" - process $proc$libresoc.v:161531$8772 + attribute \src "libresoc.v:163163.3-163164.41" + process $proc$libresoc.v:163163$8820 assign { } { } - assign $0\br_op__lk$8[0:0]$8773 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8773 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 end - attribute \src "libresoc.v:161533.3-161534.53" - process $proc$libresoc.v:161533$8774 + attribute \src "libresoc.v:163165.3-163166.53" + process $proc$libresoc.v:163165$8822 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8775 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8775 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 end - attribute \src "libresoc.v:161535.3-161536.33" - process $proc$libresoc.v:161535$8776 + attribute \src "libresoc.v:163167.3-163168.33" + process $proc$libresoc.v:163167$8824 assign { } { } - assign $0\muxid$1[1:0]$8777 \muxid$1$next + assign $0\muxid$1[1:0]$8825 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8777 + update \muxid$1 $0\muxid$1[1:0]$8825 end - attribute \src "libresoc.v:161537.3-161538.29" - process $proc$libresoc.v:161537$8778 + attribute \src "libresoc.v:163169.3-163170.29" + process $proc$libresoc.v:163169$8826 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:161576.3-161593.6" - process $proc$libresoc.v:161576$8779 + attribute \src "libresoc.v:163208.3-163225.6" + process $proc$libresoc.v:163208$8827 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8780 $2\r_busy$next[0:0]$8782 - attribute \src "libresoc.v:161577.5-161577.29" + assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:163209.5-163209.29" switch \initial - attribute \src "libresoc.v:161577.9-161577.17" + attribute \src "libresoc.v:163209.9-163209.17" case 1'1 case end @@ -335746,34 +338243,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8781 1'1 + assign $1\r_busy$next[0:0]$8829 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8781 1'0 + assign $1\r_busy$next[0:0]$8829 1'0 case - assign $1\r_busy$next[0:0]$8781 \r_busy + assign $1\r_busy$next[0:0]$8829 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8782 1'0 + assign $2\r_busy$next[0:0]$8830 1'0 case - assign $2\r_busy$next[0:0]$8782 $1\r_busy$next[0:0]$8781 + assign $2\r_busy$next[0:0]$8830 $1\r_busy$next[0:0]$8829 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8780 + update \r_busy$next $0\r_busy$next[0:0]$8828 end - attribute \src "libresoc.v:161594.3-161606.6" - process $proc$libresoc.v:161594$8783 + attribute \src "libresoc.v:163226.3-163238.6" + process $proc$libresoc.v:163226$8831 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8784 $1\muxid$1$next[1:0]$8785 - attribute \src "libresoc.v:161595.5-161595.29" + assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 + attribute \src "libresoc.v:163227.5-163227.29" switch \initial - attribute \src "libresoc.v:161595.9-161595.17" + attribute \src "libresoc.v:163227.9-163227.17" case 1'1 case end @@ -335782,19 +338279,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8785 \muxid$26 + assign $1\muxid$1$next[1:0]$8833 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8785 \muxid$26 + assign $1\muxid$1$next[1:0]$8833 \muxid$26 case - assign $1\muxid$1$next[1:0]$8785 \muxid$1 + assign $1\muxid$1$next[1:0]$8833 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8784 + update \muxid$1$next $0\muxid$1$next[1:0]$8832 end - attribute \src "libresoc.v:161607.3-161634.6" - process $proc$libresoc.v:161607$8786 + attribute \src "libresoc.v:163239.3-163266.6" + process $proc$libresoc.v:163239$8834 assign { } { } assign { } { } assign { } { } @@ -335811,19 +338308,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8787 $1\br_op__cia$2$next[63:0]$8795 - assign $0\br_op__fn_unit$4$next[13:0]$8788 $1\br_op__fn_unit$4$next[13:0]$8796 + assign $0\br_op__cia$2$next[63:0]$8835 $1\br_op__cia$2$next[63:0]$8843 + assign $0\br_op__fn_unit$4$next[13:0]$8836 $1\br_op__fn_unit$4$next[13:0]$8844 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8791 $1\br_op__insn$5$next[31:0]$8799 - assign $0\br_op__insn_type$3$next[6:0]$8792 $1\br_op__insn_type$3$next[6:0]$8800 - assign $0\br_op__is_32bit$9$next[0:0]$8793 $1\br_op__is_32bit$9$next[0:0]$8801 - assign $0\br_op__lk$8$next[0:0]$8794 $1\br_op__lk$8$next[0:0]$8802 - assign $0\br_op__imm_data__data$6$next[63:0]$8789 $2\br_op__imm_data__data$6$next[63:0]$8803 - assign $0\br_op__imm_data__ok$7$next[0:0]$8790 $2\br_op__imm_data__ok$7$next[0:0]$8804 - attribute \src "libresoc.v:161608.5-161608.29" + assign $0\br_op__insn$5$next[31:0]$8839 $1\br_op__insn$5$next[31:0]$8847 + assign $0\br_op__insn_type$3$next[6:0]$8840 $1\br_op__insn_type$3$next[6:0]$8848 + assign $0\br_op__is_32bit$9$next[0:0]$8841 $1\br_op__is_32bit$9$next[0:0]$8849 + assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 + assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 + assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 + attribute \src "libresoc.v:163240.5-163240.29" switch \initial - attribute \src "libresoc.v:161608.9-161608.17" + attribute \src "libresoc.v:163240.9-163240.17" case 1'1 case end @@ -335839,7 +338336,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -335850,16 +338347,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8801 $1\br_op__lk$8$next[0:0]$8802 $1\br_op__imm_data__ok$7$next[0:0]$8798 $1\br_op__imm_data__data$6$next[63:0]$8797 $1\br_op__insn$5$next[31:0]$8799 $1\br_op__fn_unit$4$next[13:0]$8796 $1\br_op__insn_type$3$next[6:0]$8800 $1\br_op__cia$2$next[63:0]$8795 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8795 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[13:0]$8796 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8797 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8798 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8799 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8800 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8801 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8802 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8843 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8844 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8845 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8846 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8847 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8848 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8849 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8850 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -335867,34 +338364,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8803 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8804 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8803 $1\br_op__imm_data__data$6$next[63:0]$8797 - assign $2\br_op__imm_data__ok$7$next[0:0]$8804 $1\br_op__imm_data__ok$7$next[0:0]$8798 + assign $2\br_op__imm_data__data$6$next[63:0]$8851 $1\br_op__imm_data__data$6$next[63:0]$8845 + assign $2\br_op__imm_data__ok$7$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8846 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8787 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8788 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8789 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8790 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8791 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8792 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8793 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8794 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8835 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8836 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8837 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8838 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8839 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8840 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 end - attribute \src "libresoc.v:161635.3-161653.6" - process $proc$libresoc.v:161635$8805 + attribute \src "libresoc.v:163267.3-163285.6" + process $proc$libresoc.v:163267$8853 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8806 $1\fast1$10$next[63:0]$8808 + assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 assign { } { } - assign $0\fast1_ok$next[0:0]$8807 $2\fast1_ok$next[0:0]$8810 - attribute \src "libresoc.v:161636.5-161636.29" + assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 + attribute \src "libresoc.v:163268.5-163268.29" switch \initial - attribute \src "libresoc.v:161636.9-161636.17" + attribute \src "libresoc.v:163268.9-163268.17" case 1'1 case end @@ -335904,41 +338401,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8809 $1\fast1$10$next[63:0]$8808 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8808 \fast1$10 - assign $1\fast1_ok$next[0:0]$8809 \fast1_ok + assign $1\fast1$10$next[63:0]$8856 \fast1$10 + assign $1\fast1_ok$next[0:0]$8857 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8810 1'0 + assign $2\fast1_ok$next[0:0]$8858 1'0 case - assign $2\fast1_ok$next[0:0]$8810 $1\fast1_ok$next[0:0]$8809 + assign $2\fast1_ok$next[0:0]$8858 $1\fast1_ok$next[0:0]$8857 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8806 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8807 + update \fast1$10$next $0\fast1$10$next[63:0]$8854 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 end - attribute \src "libresoc.v:161654.3-161672.6" - process $proc$libresoc.v:161654$8811 + attribute \src "libresoc.v:163286.3-163304.6" + process $proc$libresoc.v:163286$8859 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8812 $1\fast2$11$next[63:0]$8814 + assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 assign { } { } - assign $0\fast2_ok$next[0:0]$8813 $2\fast2_ok$next[0:0]$8816 - attribute \src "libresoc.v:161655.5-161655.29" + assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 + attribute \src "libresoc.v:163287.5-163287.29" switch \initial - attribute \src "libresoc.v:161655.9-161655.17" + attribute \src "libresoc.v:163287.9-163287.17" case 1'1 case end @@ -335948,41 +338445,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8815 $1\fast2$11$next[63:0]$8814 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8814 \fast2$11 - assign $1\fast2_ok$next[0:0]$8815 \fast2_ok + assign $1\fast2$11$next[63:0]$8862 \fast2$11 + assign $1\fast2_ok$next[0:0]$8863 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8816 1'0 + assign $2\fast2_ok$next[0:0]$8864 1'0 case - assign $2\fast2_ok$next[0:0]$8816 $1\fast2_ok$next[0:0]$8815 + assign $2\fast2_ok$next[0:0]$8864 $1\fast2_ok$next[0:0]$8863 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8812 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8813 + update \fast2$11$next $0\fast2$11$next[63:0]$8860 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 end - attribute \src "libresoc.v:161673.3-161691.6" - process $proc$libresoc.v:161673$8817 + attribute \src "libresoc.v:163305.3-163323.6" + process $proc$libresoc.v:163305$8865 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8818 $1\nia$next[63:0]$8820 + assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 assign { } { } - assign $0\nia_ok$next[0:0]$8819 $2\nia_ok$next[0:0]$8822 - attribute \src "libresoc.v:161674.5-161674.29" + assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 + attribute \src "libresoc.v:163306.5-163306.29" switch \initial - attribute \src "libresoc.v:161674.9-161674.17" + attribute \src "libresoc.v:163306.9-163306.17" case 1'1 case end @@ -335992,30 +338489,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8821 $1\nia$next[63:0]$8820 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8820 \nia - assign $1\nia_ok$next[0:0]$8821 \nia_ok + assign $1\nia$next[63:0]$8868 \nia + assign $1\nia_ok$next[0:0]$8869 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8822 1'0 + assign $2\nia_ok$next[0:0]$8870 1'0 case - assign $2\nia_ok$next[0:0]$8822 $1\nia_ok$next[0:0]$8821 + assign $2\nia_ok$next[0:0]$8870 $1\nia_ok$next[0:0]$8869 end sync always - update \nia$next $0\nia$next[63:0]$8818 - update \nia_ok$next $0\nia_ok$next[0:0]$8819 + update \nia$next $0\nia$next[63:0]$8866 + update \nia_ok$next $0\nia_ok$next[0:0]$8867 end - connect \$24 $and$libresoc.v:161506$8751_Y + connect \$24 $and$libresoc.v:163138$8799_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -336032,178 +338529,178 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:161711.1-162641.10" +attribute \src "libresoc.v:163343.1-164273.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:162544.3-162562.6" - wire width 64 $0\fast1$7$next[63:0]$8910 - attribute \src "libresoc.v:162397.3-162398.33" - wire width 64 $0\fast1$7[63:0]$8862 - attribute \src "libresoc.v:161725.14-161725.46" - wire width 64 $0\fast1$7[63:0]$8934 - attribute \src "libresoc.v:162544.3-162562.6" - wire $0\fast1_ok$next[0:0]$8909 - attribute \src "libresoc.v:162399.3-162400.33" + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $0\fast1$7$next[63:0]$8958 + attribute \src "libresoc.v:164029.3-164030.33" + wire width 64 $0\fast1$7[63:0]$8910 + attribute \src "libresoc.v:163357.14-163357.46" + wire width 64 $0\fast1$7[63:0]$8982 + attribute \src "libresoc.v:164176.3-164194.6" + wire $0\fast1_ok$next[0:0]$8957 + attribute \src "libresoc.v:164031.3-164032.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:161712.7-161712.20" + attribute \src "libresoc.v:163344.7-163344.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162477.3-162489.6" - wire width 2 $0\muxid$1$next[1:0]$8885 - attribute \src "libresoc.v:162417.3-162418.33" - wire width 2 $0\muxid$1[1:0]$8878 - attribute \src "libresoc.v:161739.13-161739.29" - wire width 2 $0\muxid$1[1:0]$8937 - attribute \src "libresoc.v:162506.3-162524.6" - wire width 64 $0\o$next[63:0]$8897 - attribute \src "libresoc.v:162405.3-162406.19" + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $0\muxid$1$next[1:0]$8933 + attribute \src "libresoc.v:164049.3-164050.33" + wire width 2 $0\muxid$1[1:0]$8926 + attribute \src "libresoc.v:163371.13-163371.29" + wire width 2 $0\muxid$1[1:0]$8985 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $0\o$next[63:0]$8945 + attribute \src "libresoc.v:164037.3-164038.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162506.3-162524.6" - wire $0\o_ok$next[0:0]$8898 - attribute \src "libresoc.v:162407.3-162408.25" + attribute \src "libresoc.v:164138.3-164156.6" + wire $0\o_ok$next[0:0]$8946 + attribute \src "libresoc.v:164039.3-164040.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162459.3-162476.6" - wire $0\r_busy$next[0:0]$8881 - attribute \src "libresoc.v:162419.3-162420.29" + attribute \src "libresoc.v:164091.3-164108.6" + wire $0\r_busy$next[0:0]$8929 + attribute \src "libresoc.v:164051.3-164052.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162525.3-162543.6" - wire width 64 $0\spr1$6$next[63:0]$8903 - attribute \src "libresoc.v:162401.3-162402.31" - wire width 64 $0\spr1$6[63:0]$8865 - attribute \src "libresoc.v:161784.14-161784.45" - wire width 64 $0\spr1$6[63:0]$8942 - attribute \src "libresoc.v:162525.3-162543.6" - wire $0\spr1_ok$next[0:0]$8904 - attribute \src "libresoc.v:162403.3-162404.31" + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $0\spr1$6$next[63:0]$8951 + attribute \src "libresoc.v:164033.3-164034.31" + wire width 64 $0\spr1$6[63:0]$8913 + attribute \src "libresoc.v:163416.14-163416.45" + wire width 64 $0\spr1$6[63:0]$8990 + attribute \src "libresoc.v:164157.3-164175.6" + wire $0\spr1_ok$next[0:0]$8952 + attribute \src "libresoc.v:164035.3-164036.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:162490.3-162505.6" - wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8888 - attribute \src "libresoc.v:162411.3-162412.53" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8872 - attribute \src "libresoc.v:162081.14-162081.44" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8945 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8889 - attribute \src "libresoc.v:162413.3-162414.47" - wire width 32 $0\spr_op__insn$4[31:0]$8874 - attribute \src "libresoc.v:162090.14-162090.38" - wire width 32 $0\spr_op__insn$4[31:0]$8947 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8890 - attribute \src "libresoc.v:162409.3-162410.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8870 - attribute \src "libresoc.v:162247.13-162247.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8949 - attribute \src "libresoc.v:162490.3-162505.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8891 - attribute \src "libresoc.v:162415.3-162416.55" - wire $0\spr_op__is_32bit$5[0:0]$8876 - attribute \src "libresoc.v:162333.7-162333.34" - wire $0\spr_op__is_32bit$5[0:0]$8951 - attribute \src "libresoc.v:162601.3-162619.6" - wire width 2 $0\xer_ca$10$next[1:0]$8927 - attribute \src "libresoc.v:162385.3-162386.37" - wire width 2 $0\xer_ca$10[1:0]$8853 - attribute \src "libresoc.v:162340.13-162340.31" - wire width 2 $0\xer_ca$10[1:0]$8953 - attribute \src "libresoc.v:162601.3-162619.6" - wire $0\xer_ca_ok$next[0:0]$8928 - attribute \src "libresoc.v:162387.3-162388.35" + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 + attribute \src "libresoc.v:164043.3-164044.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 + attribute \src "libresoc.v:163713.14-163713.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8937 + attribute \src "libresoc.v:164045.3-164046.47" + wire width 32 $0\spr_op__insn$4[31:0]$8922 + attribute \src "libresoc.v:163722.14-163722.38" + wire width 32 $0\spr_op__insn$4[31:0]$8995 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 + attribute \src "libresoc.v:164041.3-164042.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8918 + attribute \src "libresoc.v:163879.13-163879.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8997 + attribute \src "libresoc.v:164122.3-164137.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8939 + attribute \src "libresoc.v:164047.3-164048.55" + wire $0\spr_op__is_32bit$5[0:0]$8924 + attribute \src "libresoc.v:163965.7-163965.34" + wire $0\spr_op__is_32bit$5[0:0]$8999 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $0\xer_ca$10$next[1:0]$8975 + attribute \src "libresoc.v:164017.3-164018.37" + wire width 2 $0\xer_ca$10[1:0]$8901 + attribute \src "libresoc.v:163972.13-163972.31" + wire width 2 $0\xer_ca$10[1:0]$9001 + attribute \src "libresoc.v:164233.3-164251.6" + wire $0\xer_ca_ok$next[0:0]$8976 + attribute \src "libresoc.v:164019.3-164020.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:162582.3-162600.6" - wire width 2 $0\xer_ov$9$next[1:0]$8922 - attribute \src "libresoc.v:162389.3-162390.35" - wire width 2 $0\xer_ov$9[1:0]$8856 - attribute \src "libresoc.v:162358.13-162358.30" - wire width 2 $0\xer_ov$9[1:0]$8956 - attribute \src "libresoc.v:162582.3-162600.6" - wire $0\xer_ov_ok$next[0:0]$8921 - attribute \src "libresoc.v:162391.3-162392.35" + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $0\xer_ov$9$next[1:0]$8970 + attribute \src "libresoc.v:164021.3-164022.35" + wire width 2 $0\xer_ov$9[1:0]$8904 + attribute \src "libresoc.v:163990.13-163990.30" + wire width 2 $0\xer_ov$9[1:0]$9004 + attribute \src "libresoc.v:164214.3-164232.6" + wire $0\xer_ov_ok$next[0:0]$8969 + attribute \src "libresoc.v:164023.3-164024.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:162563.3-162581.6" - wire $0\xer_so$8$next[0:0]$8916 - attribute \src "libresoc.v:162393.3-162394.35" - wire $0\xer_so$8[0:0]$8859 - attribute \src "libresoc.v:162374.7-162374.24" - wire $0\xer_so$8[0:0]$8959 - attribute \src "libresoc.v:162563.3-162581.6" - wire $0\xer_so_ok$next[0:0]$8915 - attribute \src "libresoc.v:162395.3-162396.35" + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so$8$next[0:0]$8964 + attribute \src "libresoc.v:164025.3-164026.35" + wire $0\xer_so$8[0:0]$8907 + attribute \src "libresoc.v:164006.7-164006.24" + wire $0\xer_so$8[0:0]$9007 + attribute \src "libresoc.v:164195.3-164213.6" + wire $0\xer_so_ok$next[0:0]$8963 + attribute \src "libresoc.v:164027.3-164028.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:162544.3-162562.6" - wire width 64 $1\fast1$7$next[63:0]$8912 - attribute \src "libresoc.v:162544.3-162562.6" - wire $1\fast1_ok$next[0:0]$8911 - attribute \src "libresoc.v:161730.7-161730.22" + attribute \src "libresoc.v:164176.3-164194.6" + wire width 64 $1\fast1$7$next[63:0]$8960 + attribute \src "libresoc.v:164176.3-164194.6" + wire $1\fast1_ok$next[0:0]$8959 + attribute \src "libresoc.v:163362.7-163362.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:162477.3-162489.6" - wire width 2 $1\muxid$1$next[1:0]$8886 - attribute \src "libresoc.v:162506.3-162524.6" - wire width 64 $1\o$next[63:0]$8899 - attribute \src "libresoc.v:161752.14-161752.38" + attribute \src "libresoc.v:164109.3-164121.6" + wire width 2 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164138.3-164156.6" + wire width 64 $1\o$next[63:0]$8947 + attribute \src "libresoc.v:163384.14-163384.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162506.3-162524.6" - wire $1\o_ok$next[0:0]$8900 - attribute \src "libresoc.v:161759.7-161759.18" + attribute \src "libresoc.v:164138.3-164156.6" + wire $1\o_ok$next[0:0]$8948 + attribute \src "libresoc.v:163391.7-163391.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162459.3-162476.6" - wire $1\r_busy$next[0:0]$8882 - attribute \src "libresoc.v:161773.7-161773.20" + attribute \src "libresoc.v:164091.3-164108.6" + wire $1\r_busy$next[0:0]$8930 + attribute \src "libresoc.v:163405.7-163405.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162525.3-162543.6" - wire width 64 $1\spr1$6$next[63:0]$8905 - attribute \src "libresoc.v:162525.3-162543.6" - wire $1\spr1_ok$next[0:0]$8906 - attribute \src "libresoc.v:161789.7-161789.21" + attribute \src "libresoc.v:164157.3-164175.6" + wire width 64 $1\spr1$6$next[63:0]$8953 + attribute \src "libresoc.v:164157.3-164175.6" + wire $1\spr1_ok$next[0:0]$8954 + attribute \src "libresoc.v:163421.7-163421.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:162490.3-162505.6" - wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8892 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8893 - attribute \src "libresoc.v:162490.3-162505.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8894 - attribute \src "libresoc.v:162490.3-162505.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8895 - attribute \src "libresoc.v:162601.3-162619.6" - wire width 2 $1\xer_ca$10$next[1:0]$8929 - attribute \src "libresoc.v:162601.3-162619.6" - wire $1\xer_ca_ok$next[0:0]$8930 - attribute \src "libresoc.v:162347.7-162347.23" + attribute \src "libresoc.v:164122.3-164137.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8941 + attribute \src "libresoc.v:164122.3-164137.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 + attribute \src "libresoc.v:164122.3-164137.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164233.3-164251.6" + wire width 2 $1\xer_ca$10$next[1:0]$8977 + attribute \src "libresoc.v:164233.3-164251.6" + wire $1\xer_ca_ok$next[0:0]$8978 + attribute \src "libresoc.v:163979.7-163979.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:162582.3-162600.6" - wire width 2 $1\xer_ov$9$next[1:0]$8924 - attribute \src "libresoc.v:162582.3-162600.6" - wire $1\xer_ov_ok$next[0:0]$8923 - attribute \src "libresoc.v:162363.7-162363.23" + attribute \src "libresoc.v:164214.3-164232.6" + wire width 2 $1\xer_ov$9$next[1:0]$8972 + attribute \src "libresoc.v:164214.3-164232.6" + wire $1\xer_ov_ok$next[0:0]$8971 + attribute \src "libresoc.v:163995.7-163995.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:162563.3-162581.6" - wire $1\xer_so$8$next[0:0]$8918 - attribute \src "libresoc.v:162563.3-162581.6" - wire $1\xer_so_ok$next[0:0]$8917 - attribute \src "libresoc.v:162379.7-162379.23" + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so$8$next[0:0]$8966 + attribute \src "libresoc.v:164195.3-164213.6" + wire $1\xer_so_ok$next[0:0]$8965 + attribute \src "libresoc.v:164011.7-164011.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:162544.3-162562.6" - wire $2\fast1_ok$next[0:0]$8913 - attribute \src "libresoc.v:162506.3-162524.6" - wire $2\o_ok$next[0:0]$8901 - attribute \src "libresoc.v:162459.3-162476.6" - wire $2\r_busy$next[0:0]$8883 - attribute \src "libresoc.v:162525.3-162543.6" - wire $2\spr1_ok$next[0:0]$8907 - attribute \src "libresoc.v:162601.3-162619.6" - wire $2\xer_ca_ok$next[0:0]$8931 - attribute \src "libresoc.v:162582.3-162600.6" - wire $2\xer_ov_ok$next[0:0]$8925 - attribute \src "libresoc.v:162563.3-162581.6" - wire $2\xer_so_ok$next[0:0]$8919 - attribute \src "libresoc.v:162384.18-162384.118" - wire $and$libresoc.v:162384$8851_Y + attribute \src "libresoc.v:164176.3-164194.6" + wire $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164138.3-164156.6" + wire $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164091.3-164108.6" + wire $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164157.3-164175.6" + wire $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164233.3-164251.6" + wire $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164214.3-164232.6" + wire $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164195.3-164213.6" + wire $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164016.18-164016.118" + wire $and$libresoc.v:164016$8899_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 @@ -336219,7 +338716,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "libresoc.v:161712.7-161712.15" + attribute \src "libresoc.v:163344.7-163344.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -336856,7 +339353,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:162384$8851 + cell $and $and$libresoc.v:164016$8899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336864,22 +339361,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:162384$8851_Y + connect \Y $and$libresoc.v:164016$8899_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162421.10-162424.4" + attribute \src "libresoc.v:164053.10-164056.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162425.10-162428.4" + attribute \src "libresoc.v:164057.10-164060.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:162429.12-162458.4" + attribute \src "libresoc.v:164061.12-164090.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -336910,293 +339407,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:161712.7-161712.20" - process $proc$libresoc.v:161712$8932 + attribute \src "libresoc.v:163344.7-163344.20" + process $proc$libresoc.v:163344$8980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161725.14-161725.46" - process $proc$libresoc.v:161725$8933 + attribute \src "libresoc.v:163357.14-163357.46" + process $proc$libresoc.v:163357$8981 assign { } { } - assign $0\fast1$7[63:0]$8934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8934 + update \fast1$7 $0\fast1$7[63:0]$8982 end - attribute \src "libresoc.v:161730.7-161730.22" - process $proc$libresoc.v:161730$8935 + attribute \src "libresoc.v:163362.7-163362.22" + process $proc$libresoc.v:163362$8983 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:161739.13-161739.29" - process $proc$libresoc.v:161739$8936 + attribute \src "libresoc.v:163371.13-163371.29" + process $proc$libresoc.v:163371$8984 assign { } { } - assign $0\muxid$1[1:0]$8937 2'00 + assign $0\muxid$1[1:0]$8985 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8937 + update \muxid$1 $0\muxid$1[1:0]$8985 end - attribute \src "libresoc.v:161752.14-161752.38" - process $proc$libresoc.v:161752$8938 + attribute \src "libresoc.v:163384.14-163384.38" + process $proc$libresoc.v:163384$8986 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:161759.7-161759.18" - process $proc$libresoc.v:161759$8939 + attribute \src "libresoc.v:163391.7-163391.18" + process $proc$libresoc.v:163391$8987 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:161773.7-161773.20" - process $proc$libresoc.v:161773$8940 + attribute \src "libresoc.v:163405.7-163405.20" + process $proc$libresoc.v:163405$8988 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:161784.14-161784.45" - process $proc$libresoc.v:161784$8941 + attribute \src "libresoc.v:163416.14-163416.45" + process $proc$libresoc.v:163416$8989 assign { } { } - assign $0\spr1$6[63:0]$8942 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8942 + update \spr1$6 $0\spr1$6[63:0]$8990 end - attribute \src "libresoc.v:161789.7-161789.21" - process $proc$libresoc.v:161789$8943 + attribute \src "libresoc.v:163421.7-163421.21" + process $proc$libresoc.v:163421$8991 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:162081.14-162081.44" - process $proc$libresoc.v:162081$8944 + attribute \src "libresoc.v:163713.14-163713.44" + process $proc$libresoc.v:163713$8992 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8945 14'00000000000000 + assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8945 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 end - attribute \src "libresoc.v:162090.14-162090.38" - process $proc$libresoc.v:162090$8946 + attribute \src "libresoc.v:163722.14-163722.38" + process $proc$libresoc.v:163722$8994 assign { } { } - assign $0\spr_op__insn$4[31:0]$8947 0 + assign $0\spr_op__insn$4[31:0]$8995 0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8947 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 end - attribute \src "libresoc.v:162247.13-162247.42" - process $proc$libresoc.v:162247$8948 + attribute \src "libresoc.v:163879.13-163879.42" + process $proc$libresoc.v:163879$8996 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8949 7'0000000 + assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8949 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 end - attribute \src "libresoc.v:162333.7-162333.34" - process $proc$libresoc.v:162333$8950 + attribute \src "libresoc.v:163965.7-163965.34" + process $proc$libresoc.v:163965$8998 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8951 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8951 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 end - attribute \src "libresoc.v:162340.13-162340.31" - process $proc$libresoc.v:162340$8952 + attribute \src "libresoc.v:163972.13-163972.31" + process $proc$libresoc.v:163972$9000 assign { } { } - assign $0\xer_ca$10[1:0]$8953 2'00 + assign $0\xer_ca$10[1:0]$9001 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8953 + update \xer_ca$10 $0\xer_ca$10[1:0]$9001 end - attribute \src "libresoc.v:162347.7-162347.23" - process $proc$libresoc.v:162347$8954 + attribute \src "libresoc.v:163979.7-163979.23" + process $proc$libresoc.v:163979$9002 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:162358.13-162358.30" - process $proc$libresoc.v:162358$8955 + attribute \src "libresoc.v:163990.13-163990.30" + process $proc$libresoc.v:163990$9003 assign { } { } - assign $0\xer_ov$9[1:0]$8956 2'00 + assign $0\xer_ov$9[1:0]$9004 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8956 + update \xer_ov$9 $0\xer_ov$9[1:0]$9004 end - attribute \src "libresoc.v:162363.7-162363.23" - process $proc$libresoc.v:162363$8957 + attribute \src "libresoc.v:163995.7-163995.23" + process $proc$libresoc.v:163995$9005 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:162374.7-162374.24" - process $proc$libresoc.v:162374$8958 + attribute \src "libresoc.v:164006.7-164006.24" + process $proc$libresoc.v:164006$9006 assign { } { } - assign $0\xer_so$8[0:0]$8959 1'0 + assign $0\xer_so$8[0:0]$9007 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$8959 + update \xer_so$8 $0\xer_so$8[0:0]$9007 end - attribute \src "libresoc.v:162379.7-162379.23" - process $proc$libresoc.v:162379$8960 + attribute \src "libresoc.v:164011.7-164011.23" + process $proc$libresoc.v:164011$9008 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:162385.3-162386.37" - process $proc$libresoc.v:162385$8852 + attribute \src "libresoc.v:164017.3-164018.37" + process $proc$libresoc.v:164017$8900 assign { } { } - assign $0\xer_ca$10[1:0]$8853 \xer_ca$10$next + assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8853 + update \xer_ca$10 $0\xer_ca$10[1:0]$8901 end - attribute \src "libresoc.v:162387.3-162388.35" - process $proc$libresoc.v:162387$8854 + attribute \src "libresoc.v:164019.3-164020.35" + process $proc$libresoc.v:164019$8902 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:162389.3-162390.35" - process $proc$libresoc.v:162389$8855 + attribute \src "libresoc.v:164021.3-164022.35" + process $proc$libresoc.v:164021$8903 assign { } { } - assign $0\xer_ov$9[1:0]$8856 \xer_ov$9$next + assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8856 + update \xer_ov$9 $0\xer_ov$9[1:0]$8904 end - attribute \src "libresoc.v:162391.3-162392.35" - process $proc$libresoc.v:162391$8857 + attribute \src "libresoc.v:164023.3-164024.35" + process $proc$libresoc.v:164023$8905 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:162393.3-162394.35" - process $proc$libresoc.v:162393$8858 + attribute \src "libresoc.v:164025.3-164026.35" + process $proc$libresoc.v:164025$8906 assign { } { } - assign $0\xer_so$8[0:0]$8859 \xer_so$8$next + assign $0\xer_so$8[0:0]$8907 \xer_so$8$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8859 + update \xer_so$8 $0\xer_so$8[0:0]$8907 end - attribute \src "libresoc.v:162395.3-162396.35" - process $proc$libresoc.v:162395$8860 + attribute \src "libresoc.v:164027.3-164028.35" + process $proc$libresoc.v:164027$8908 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:162397.3-162398.33" - process $proc$libresoc.v:162397$8861 + attribute \src "libresoc.v:164029.3-164030.33" + process $proc$libresoc.v:164029$8909 assign { } { } - assign $0\fast1$7[63:0]$8862 \fast1$7$next + assign $0\fast1$7[63:0]$8910 \fast1$7$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8862 + update \fast1$7 $0\fast1$7[63:0]$8910 end - attribute \src "libresoc.v:162399.3-162400.33" - process $proc$libresoc.v:162399$8863 + attribute \src "libresoc.v:164031.3-164032.33" + process $proc$libresoc.v:164031$8911 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:162401.3-162402.31" - process $proc$libresoc.v:162401$8864 + attribute \src "libresoc.v:164033.3-164034.31" + process $proc$libresoc.v:164033$8912 assign { } { } - assign $0\spr1$6[63:0]$8865 \spr1$6$next + assign $0\spr1$6[63:0]$8913 \spr1$6$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8865 + update \spr1$6 $0\spr1$6[63:0]$8913 end - attribute \src "libresoc.v:162403.3-162404.31" - process $proc$libresoc.v:162403$8866 + attribute \src "libresoc.v:164035.3-164036.31" + process $proc$libresoc.v:164035$8914 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:162405.3-162406.19" - process $proc$libresoc.v:162405$8867 + attribute \src "libresoc.v:164037.3-164038.19" + process $proc$libresoc.v:164037$8915 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:162407.3-162408.25" - process $proc$libresoc.v:162407$8868 + attribute \src "libresoc.v:164039.3-164040.25" + process $proc$libresoc.v:164039$8916 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:162409.3-162410.57" - process $proc$libresoc.v:162409$8869 + attribute \src "libresoc.v:164041.3-164042.57" + process $proc$libresoc.v:164041$8917 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8870 \spr_op__insn_type$2$next + assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8870 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 end - attribute \src "libresoc.v:162411.3-162412.53" - process $proc$libresoc.v:162411$8871 + attribute \src "libresoc.v:164043.3-164044.53" + process $proc$libresoc.v:164043$8919 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8872 \spr_op__fn_unit$3$next + assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8872 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 end - attribute \src "libresoc.v:162413.3-162414.47" - process $proc$libresoc.v:162413$8873 + attribute \src "libresoc.v:164045.3-164046.47" + process $proc$libresoc.v:164045$8921 assign { } { } - assign $0\spr_op__insn$4[31:0]$8874 \spr_op__insn$4$next + assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8874 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 end - attribute \src "libresoc.v:162415.3-162416.55" - process $proc$libresoc.v:162415$8875 + attribute \src "libresoc.v:164047.3-164048.55" + process $proc$libresoc.v:164047$8923 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8876 \spr_op__is_32bit$5$next + assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8876 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 end - attribute \src "libresoc.v:162417.3-162418.33" - process $proc$libresoc.v:162417$8877 + attribute \src "libresoc.v:164049.3-164050.33" + process $proc$libresoc.v:164049$8925 assign { } { } - assign $0\muxid$1[1:0]$8878 \muxid$1$next + assign $0\muxid$1[1:0]$8926 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8878 + update \muxid$1 $0\muxid$1[1:0]$8926 end - attribute \src "libresoc.v:162419.3-162420.29" - process $proc$libresoc.v:162419$8879 + attribute \src "libresoc.v:164051.3-164052.29" + process $proc$libresoc.v:164051$8927 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:162459.3-162476.6" - process $proc$libresoc.v:162459$8880 + attribute \src "libresoc.v:164091.3-164108.6" + process $proc$libresoc.v:164091$8928 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8881 $2\r_busy$next[0:0]$8883 - attribute \src "libresoc.v:162460.5-162460.29" + assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:164092.5-164092.29" switch \initial - attribute \src "libresoc.v:162460.9-162460.17" + attribute \src "libresoc.v:164092.9-164092.17" case 1'1 case end @@ -337205,34 +339702,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8882 1'1 + assign $1\r_busy$next[0:0]$8930 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8882 1'0 + assign $1\r_busy$next[0:0]$8930 1'0 case - assign $1\r_busy$next[0:0]$8882 \r_busy + assign $1\r_busy$next[0:0]$8930 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8883 1'0 + assign $2\r_busy$next[0:0]$8931 1'0 case - assign $2\r_busy$next[0:0]$8883 $1\r_busy$next[0:0]$8882 + assign $2\r_busy$next[0:0]$8931 $1\r_busy$next[0:0]$8930 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8881 + update \r_busy$next $0\r_busy$next[0:0]$8929 end - attribute \src "libresoc.v:162477.3-162489.6" - process $proc$libresoc.v:162477$8884 + attribute \src "libresoc.v:164109.3-164121.6" + process $proc$libresoc.v:164109$8932 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8885 $1\muxid$1$next[1:0]$8886 - attribute \src "libresoc.v:162478.5-162478.29" + assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 + attribute \src "libresoc.v:164110.5-164110.29" switch \initial - attribute \src "libresoc.v:162478.9-162478.17" + attribute \src "libresoc.v:164110.9-164110.17" case 1'1 case end @@ -337241,19 +339738,19 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8886 \muxid$24 + assign $1\muxid$1$next[1:0]$8934 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8886 \muxid$24 + assign $1\muxid$1$next[1:0]$8934 \muxid$24 case - assign $1\muxid$1$next[1:0]$8886 \muxid$1 + assign $1\muxid$1$next[1:0]$8934 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8885 + update \muxid$1$next $0\muxid$1$next[1:0]$8933 end - attribute \src "libresoc.v:162490.3-162505.6" - process $proc$libresoc.v:162490$8887 + attribute \src "libresoc.v:164122.3-164137.6" + process $proc$libresoc.v:164122$8935 assign { } { } assign { } { } assign { } { } @@ -337262,13 +339759,13 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[13:0]$8888 $1\spr_op__fn_unit$3$next[13:0]$8892 - assign $0\spr_op__insn$4$next[31:0]$8889 $1\spr_op__insn$4$next[31:0]$8893 - assign $0\spr_op__insn_type$2$next[6:0]$8890 $1\spr_op__insn_type$2$next[6:0]$8894 - assign $0\spr_op__is_32bit$5$next[0:0]$8891 $1\spr_op__is_32bit$5$next[0:0]$8895 - attribute \src "libresoc.v:162491.5-162491.29" + assign $0\spr_op__fn_unit$3$next[13:0]$8936 $1\spr_op__fn_unit$3$next[13:0]$8940 + assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 + assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 + assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 + attribute \src "libresoc.v:164123.5-164123.29" switch \initial - attribute \src "libresoc.v:162491.9-162491.17" + attribute \src "libresoc.v:164123.9-164123.17" case 1'1 case end @@ -337280,38 +339777,38 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8895 $1\spr_op__insn$4$next[31:0]$8893 $1\spr_op__fn_unit$3$next[13:0]$8892 $1\spr_op__insn_type$2$next[6:0]$8894 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\spr_op__fn_unit$3$next[13:0]$8892 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8893 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8894 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8895 \spr_op__is_32bit$5 + assign $1\spr_op__fn_unit$3$next[13:0]$8940 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8941 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8942 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8943 \spr_op__is_32bit$5 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8888 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8889 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8890 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8891 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8936 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8937 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 end - attribute \src "libresoc.v:162506.3-162524.6" - process $proc$libresoc.v:162506$8896 + attribute \src "libresoc.v:164138.3-164156.6" + process $proc$libresoc.v:164138$8944 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8897 $1\o$next[63:0]$8899 + assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 assign { } { } - assign $0\o_ok$next[0:0]$8898 $2\o_ok$next[0:0]$8901 - attribute \src "libresoc.v:162507.5-162507.29" + assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 + attribute \src "libresoc.v:164139.5-164139.29" switch \initial - attribute \src "libresoc.v:162507.9-162507.17" + attribute \src "libresoc.v:164139.9-164139.17" case 1'1 case end @@ -337321,41 +339818,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8900 $1\o$next[63:0]$8899 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } case - assign $1\o$next[63:0]$8899 \o - assign $1\o_ok$next[0:0]$8900 \o_ok + assign $1\o$next[63:0]$8947 \o + assign $1\o_ok$next[0:0]$8948 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8901 1'0 + assign $2\o_ok$next[0:0]$8949 1'0 case - assign $2\o_ok$next[0:0]$8901 $1\o_ok$next[0:0]$8900 + assign $2\o_ok$next[0:0]$8949 $1\o_ok$next[0:0]$8948 end sync always - update \o$next $0\o$next[63:0]$8897 - update \o_ok$next $0\o_ok$next[0:0]$8898 + update \o$next $0\o$next[63:0]$8945 + update \o_ok$next $0\o_ok$next[0:0]$8946 end - attribute \src "libresoc.v:162525.3-162543.6" - process $proc$libresoc.v:162525$8902 + attribute \src "libresoc.v:164157.3-164175.6" + process $proc$libresoc.v:164157$8950 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8903 $1\spr1$6$next[63:0]$8905 + assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 assign { } { } - assign $0\spr1_ok$next[0:0]$8904 $2\spr1_ok$next[0:0]$8907 - attribute \src "libresoc.v:162526.5-162526.29" + assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 + attribute \src "libresoc.v:164158.5-164158.29" switch \initial - attribute \src "libresoc.v:162526.9-162526.17" + attribute \src "libresoc.v:164158.9-164158.17" case 1'1 case end @@ -337365,41 +339862,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8906 $1\spr1$6$next[63:0]$8905 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } case - assign $1\spr1$6$next[63:0]$8905 \spr1$6 - assign $1\spr1_ok$next[0:0]$8906 \spr1_ok + assign $1\spr1$6$next[63:0]$8953 \spr1$6 + assign $1\spr1_ok$next[0:0]$8954 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\spr1_ok$next[0:0]$8907 1'0 + assign $2\spr1_ok$next[0:0]$8955 1'0 case - assign $2\spr1_ok$next[0:0]$8907 $1\spr1_ok$next[0:0]$8906 + assign $2\spr1_ok$next[0:0]$8955 $1\spr1_ok$next[0:0]$8954 end sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8903 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8904 + update \spr1$6$next $0\spr1$6$next[63:0]$8951 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 end - attribute \src "libresoc.v:162544.3-162562.6" - process $proc$libresoc.v:162544$8908 + attribute \src "libresoc.v:164176.3-164194.6" + process $proc$libresoc.v:164176$8956 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8910 $1\fast1$7$next[63:0]$8912 - assign $0\fast1_ok$next[0:0]$8909 $2\fast1_ok$next[0:0]$8913 - attribute \src "libresoc.v:162545.5-162545.29" + assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 + assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:164177.5-164177.29" switch \initial - attribute \src "libresoc.v:162545.9-162545.17" + attribute \src "libresoc.v:164177.9-164177.17" case 1'1 case end @@ -337409,41 +339906,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8911 $1\fast1$7$next[63:0]$8912 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1_ok$next[0:0]$8911 \fast1_ok - assign $1\fast1$7$next[63:0]$8912 \fast1$7 + assign $1\fast1_ok$next[0:0]$8959 \fast1_ok + assign $1\fast1$7$next[63:0]$8960 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8913 1'0 + assign $2\fast1_ok$next[0:0]$8961 1'0 case - assign $2\fast1_ok$next[0:0]$8913 $1\fast1_ok$next[0:0]$8911 + assign $2\fast1_ok$next[0:0]$8961 $1\fast1_ok$next[0:0]$8959 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8909 - update \fast1$7$next $0\fast1$7$next[63:0]$8910 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 + update \fast1$7$next $0\fast1$7$next[63:0]$8958 end - attribute \src "libresoc.v:162563.3-162581.6" - process $proc$libresoc.v:162563$8914 + attribute \src "libresoc.v:164195.3-164213.6" + process $proc$libresoc.v:164195$8962 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$8$next[0:0]$8916 $1\xer_so$8$next[0:0]$8918 - assign $0\xer_so_ok$next[0:0]$8915 $2\xer_so_ok$next[0:0]$8919 - attribute \src "libresoc.v:162564.5-162564.29" + assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 + assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:164196.5-164196.29" switch \initial - attribute \src "libresoc.v:162564.9-162564.17" + attribute \src "libresoc.v:164196.9-164196.17" case 1'1 case end @@ -337453,41 +339950,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8917 $1\xer_so$8$next[0:0]$8918 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\xer_so_ok$next[0:0]$8917 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8918 \xer_so$8 + assign $1\xer_so_ok$next[0:0]$8965 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8966 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8919 1'0 + assign $2\xer_so_ok$next[0:0]$8967 1'0 case - assign $2\xer_so_ok$next[0:0]$8919 $1\xer_so_ok$next[0:0]$8917 + assign $2\xer_so_ok$next[0:0]$8967 $1\xer_so_ok$next[0:0]$8965 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8915 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8916 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 end - attribute \src "libresoc.v:162582.3-162600.6" - process $proc$libresoc.v:162582$8920 + attribute \src "libresoc.v:164214.3-164232.6" + process $proc$libresoc.v:164214$8968 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$9$next[1:0]$8922 $1\xer_ov$9$next[1:0]$8924 - assign $0\xer_ov_ok$next[0:0]$8921 $2\xer_ov_ok$next[0:0]$8925 - attribute \src "libresoc.v:162583.5-162583.29" + assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 + assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:164215.5-164215.29" switch \initial - attribute \src "libresoc.v:162583.9-162583.17" + attribute \src "libresoc.v:164215.9-164215.17" case 1'1 case end @@ -337497,41 +339994,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8923 $1\xer_ov$9$next[1:0]$8924 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\xer_ov_ok$next[0:0]$8923 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8924 \xer_ov$9 + assign $1\xer_ov_ok$next[0:0]$8971 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8972 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8925 1'0 + assign $2\xer_ov_ok$next[0:0]$8973 1'0 case - assign $2\xer_ov_ok$next[0:0]$8925 $1\xer_ov_ok$next[0:0]$8923 + assign $2\xer_ov_ok$next[0:0]$8973 $1\xer_ov_ok$next[0:0]$8971 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8921 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8922 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 end - attribute \src "libresoc.v:162601.3-162619.6" - process $proc$libresoc.v:162601$8926 + attribute \src "libresoc.v:164233.3-164251.6" + process $proc$libresoc.v:164233$8974 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8927 $1\xer_ca$10$next[1:0]$8929 + assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8928 $2\xer_ca_ok$next[0:0]$8931 - attribute \src "libresoc.v:162602.5-162602.29" + assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 + attribute \src "libresoc.v:164234.5-164234.29" switch \initial - attribute \src "libresoc.v:162602.9-162602.17" + attribute \src "libresoc.v:164234.9-164234.17" case 1'1 case end @@ -337541,30 +340038,30 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8930 $1\xer_ca$10$next[1:0]$8929 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_ca$10$next[1:0]$8929 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8930 \xer_ca_ok + assign $1\xer_ca$10$next[1:0]$8977 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8978 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8931 1'0 + assign $2\xer_ca_ok$next[0:0]$8979 1'0 case - assign $2\xer_ca_ok$next[0:0]$8931 $1\xer_ca_ok$next[0:0]$8930 + assign $2\xer_ca_ok$next[0:0]$8979 $1\xer_ca_ok$next[0:0]$8978 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8927 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8928 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 end - connect \$22 $and$libresoc.v:162384$8851_Y + connect \$22 $and$libresoc.v:164016$8899_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -337587,279 +340084,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:162645.1-164137.10" +attribute \src "libresoc.v:164277.1-165769.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:164051.3-164092.6" - wire width 4 $0\alu_op__data_len$next[3:0]$9024 - attribute \src "libresoc.v:163827.3-163828.49" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9072 + attribute \src "libresoc.v:165459.3-165460.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 14 $0\alu_op__fn_unit$next[13:0]$9025 - attribute \src "libresoc.v:163797.3-163798.47" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 + attribute \src "libresoc.v:165429.3-165430.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$9026 - attribute \src "libresoc.v:163799.3-163800.61" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 + attribute \src "libresoc.v:165431.3-165432.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__imm_data__ok$next[0:0]$9027 - attribute \src "libresoc.v:163801.3-163802.57" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9075 + attribute \src "libresoc.v:165433.3-165434.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$9028 - attribute \src "libresoc.v:163819.3-163820.55" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9076 + attribute \src "libresoc.v:165451.3-165452.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 32 $0\alu_op__insn$next[31:0]$9029 - attribute \src "libresoc.v:163829.3-163830.41" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $0\alu_op__insn$next[31:0]$9077 + attribute \src "libresoc.v:165461.3-165462.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$9030 - attribute \src "libresoc.v:163795.3-163796.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9078 + attribute \src "libresoc.v:165427.3-165428.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__invert_in$next[0:0]$9031 - attribute \src "libresoc.v:163811.3-163812.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_in$next[0:0]$9079 + attribute \src "libresoc.v:165443.3-165444.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__invert_out$next[0:0]$9032 - attribute \src "libresoc.v:163815.3-163816.53" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__invert_out$next[0:0]$9080 + attribute \src "libresoc.v:165447.3-165448.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__is_32bit$next[0:0]$9033 - attribute \src "libresoc.v:163823.3-163824.49" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_32bit$next[0:0]$9081 + attribute \src "libresoc.v:165455.3-165456.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__is_signed$next[0:0]$9034 - attribute \src "libresoc.v:163825.3-163826.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__is_signed$next[0:0]$9082 + attribute \src "libresoc.v:165457.3-165458.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__oe__oe$next[0:0]$9035 - attribute \src "libresoc.v:163807.3-163808.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__oe$next[0:0]$9083 + attribute \src "libresoc.v:165439.3-165440.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__oe__ok$next[0:0]$9036 - attribute \src "libresoc.v:163809.3-163810.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__oe__ok$next[0:0]$9084 + attribute \src "libresoc.v:165441.3-165442.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__output_carry$next[0:0]$9037 - attribute \src "libresoc.v:163821.3-163822.57" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__output_carry$next[0:0]$9085 + attribute \src "libresoc.v:165453.3-165454.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__rc__ok$next[0:0]$9038 - attribute \src "libresoc.v:163805.3-163806.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__ok$next[0:0]$9086 + attribute \src "libresoc.v:165437.3-165438.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__rc__rc$next[0:0]$9039 - attribute \src "libresoc.v:163803.3-163804.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__rc__rc$next[0:0]$9087 + attribute \src "libresoc.v:165435.3-165436.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__write_cr0$next[0:0]$9040 - attribute \src "libresoc.v:163817.3-163818.51" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__write_cr0$next[0:0]$9088 + attribute \src "libresoc.v:165449.3-165450.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $0\alu_op__zero_a$next[0:0]$9041 - attribute \src "libresoc.v:163813.3-163814.45" + attribute \src "libresoc.v:165683.3-165724.6" + wire $0\alu_op__zero_a$next[0:0]$9089 + attribute \src "libresoc.v:165445.3-165446.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire width 4 $0\cr_a$next[3:0]$8993 - attribute \src "libresoc.v:163787.3-163788.25" + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $0\cr_a$next[3:0]$9041 + attribute \src "libresoc.v:165419.3-165420.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire $0\cr_a_ok$next[0:0]$8994 - attribute \src "libresoc.v:163789.3-163790.31" + attribute \src "libresoc.v:165576.3-165594.6" + wire $0\cr_a_ok$next[0:0]$9042 + attribute \src "libresoc.v:165421.3-165422.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162646.7-162646.20" + attribute \src "libresoc.v:164278.7-164278.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164038.3-164050.6" - wire width 2 $0\muxid$next[1:0]$9021 - attribute \src "libresoc.v:163831.3-163832.27" + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $0\muxid$next[1:0]$9069 + attribute \src "libresoc.v:165463.3-165464.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire width 64 $0\o$next[63:0]$9067 - attribute \src "libresoc.v:163791.3-163792.19" + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $0\o$next[63:0]$9115 + attribute \src "libresoc.v:165423.3-165424.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire $0\o_ok$next[0:0]$9068 - attribute \src "libresoc.v:163793.3-163794.25" + attribute \src "libresoc.v:165725.3-165743.6" + wire $0\o_ok$next[0:0]$9116 + attribute \src "libresoc.v:165425.3-165426.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:164020.3-164037.6" - wire $0\r_busy$next[0:0]$9017 - attribute \src "libresoc.v:163833.3-163834.29" + attribute \src "libresoc.v:165652.3-165669.6" + wire $0\r_busy$next[0:0]$9065 + attribute \src "libresoc.v:165465.3-165466.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire width 2 $0\xer_ca$next[1:0]$9000 - attribute \src "libresoc.v:163783.3-163784.29" + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $0\xer_ca$next[1:0]$9048 + attribute \src "libresoc.v:165415.3-165416.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire $0\xer_ca_ok$next[0:0]$8999 - attribute \src "libresoc.v:163785.3-163786.35" + attribute \src "libresoc.v:165595.3-165613.6" + wire $0\xer_ca_ok$next[0:0]$9047 + attribute \src "libresoc.v:165417.3-165418.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire width 2 $0\xer_ov$next[1:0]$9005 - attribute \src "libresoc.v:163779.3-163780.29" + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $0\xer_ov$next[1:0]$9053 + attribute \src "libresoc.v:165411.3-165412.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire $0\xer_ov_ok$next[0:0]$9006 - attribute \src "libresoc.v:163781.3-163782.35" + attribute \src "libresoc.v:165614.3-165632.6" + wire $0\xer_ov_ok$next[0:0]$9054 + attribute \src "libresoc.v:165413.3-165414.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $0\xer_so$next[0:0]$9011 - attribute \src "libresoc.v:163775.3-163776.29" + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so$next[0:0]$9059 + attribute \src "libresoc.v:165407.3-165408.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $0\xer_so_ok$next[0:0]$9012 - attribute \src "libresoc.v:163777.3-163778.35" + attribute \src "libresoc.v:165633.3-165651.6" + wire $0\xer_so_ok$next[0:0]$9060 + attribute \src "libresoc.v:165409.3-165410.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 4 $1\alu_op__data_len$next[3:0]$9042 - attribute \src "libresoc.v:162651.13-162651.36" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9090 + attribute \src "libresoc.v:164283.13-164283.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 14 $1\alu_op__fn_unit$next[13:0]$9043 - attribute \src "libresoc.v:162675.14-162675.40" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 + attribute \src "libresoc.v:164307.14-164307.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$9044 - attribute \src "libresoc.v:162714.14-162714.59" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 + attribute \src "libresoc.v:164346.14-164346.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9045 - attribute \src "libresoc.v:162723.7-162723.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9093 + attribute \src "libresoc.v:164355.7-164355.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9046 - attribute \src "libresoc.v:162736.13-162736.39" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9094 + attribute \src "libresoc.v:164368.13-164368.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 32 $1\alu_op__insn$next[31:0]$9047 - attribute \src "libresoc.v:162753.14-162753.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 32 $1\alu_op__insn$next[31:0]$9095 + attribute \src "libresoc.v:164385.14-164385.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9048 - attribute \src "libresoc.v:162837.13-162837.38" + attribute \src "libresoc.v:165683.3-165724.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9096 + attribute \src "libresoc.v:164469.13-164469.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__invert_in$next[0:0]$9049 - attribute \src "libresoc.v:162996.7-162996.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_in$next[0:0]$9097 + attribute \src "libresoc.v:164628.7-164628.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__invert_out$next[0:0]$9050 - attribute \src "libresoc.v:163005.7-163005.32" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__invert_out$next[0:0]$9098 + attribute \src "libresoc.v:164637.7-164637.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__is_32bit$next[0:0]$9051 - attribute \src "libresoc.v:163014.7-163014.30" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_32bit$next[0:0]$9099 + attribute \src "libresoc.v:164646.7-164646.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__is_signed$next[0:0]$9052 - attribute \src "libresoc.v:163023.7-163023.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__is_signed$next[0:0]$9100 + attribute \src "libresoc.v:164655.7-164655.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__oe__oe$next[0:0]$9053 - attribute \src "libresoc.v:163032.7-163032.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__oe$next[0:0]$9101 + attribute \src "libresoc.v:164664.7-164664.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__oe__ok$next[0:0]$9054 - attribute \src "libresoc.v:163041.7-163041.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__oe__ok$next[0:0]$9102 + attribute \src "libresoc.v:164673.7-164673.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__output_carry$next[0:0]$9055 - attribute \src "libresoc.v:163050.7-163050.34" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__output_carry$next[0:0]$9103 + attribute \src "libresoc.v:164682.7-164682.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__rc__ok$next[0:0]$9056 - attribute \src "libresoc.v:163059.7-163059.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__ok$next[0:0]$9104 + attribute \src "libresoc.v:164691.7-164691.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__rc__rc$next[0:0]$9057 - attribute \src "libresoc.v:163068.7-163068.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__rc__rc$next[0:0]$9105 + attribute \src "libresoc.v:164700.7-164700.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__write_cr0$next[0:0]$9058 - attribute \src "libresoc.v:163077.7-163077.31" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__write_cr0$next[0:0]$9106 + attribute \src "libresoc.v:164709.7-164709.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire $1\alu_op__zero_a$next[0:0]$9059 - attribute \src "libresoc.v:163086.7-163086.28" + attribute \src "libresoc.v:165683.3-165724.6" + wire $1\alu_op__zero_a$next[0:0]$9107 + attribute \src "libresoc.v:164718.7-164718.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire width 4 $1\cr_a$next[3:0]$8995 - attribute \src "libresoc.v:163099.13-163099.24" + attribute \src "libresoc.v:165576.3-165594.6" + wire width 4 $1\cr_a$next[3:0]$9043 + attribute \src "libresoc.v:164731.13-164731.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:163944.3-163962.6" - wire $1\cr_a_ok$next[0:0]$8996 - attribute \src "libresoc.v:163106.7-163106.21" + attribute \src "libresoc.v:165576.3-165594.6" + wire $1\cr_a_ok$next[0:0]$9044 + attribute \src "libresoc.v:164738.7-164738.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:164038.3-164050.6" - wire width 2 $1\muxid$next[1:0]$9022 - attribute \src "libresoc.v:163683.13-163683.25" + attribute \src "libresoc.v:165670.3-165682.6" + wire width 2 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165315.13-165315.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire width 64 $1\o$next[63:0]$9069 - attribute \src "libresoc.v:163698.14-163698.38" + attribute \src "libresoc.v:165725.3-165743.6" + wire width 64 $1\o$next[63:0]$9117 + attribute \src "libresoc.v:165330.14-165330.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164093.3-164111.6" - wire $1\o_ok$next[0:0]$9070 - attribute \src "libresoc.v:163705.7-163705.18" + attribute \src "libresoc.v:165725.3-165743.6" + wire $1\o_ok$next[0:0]$9118 + attribute \src "libresoc.v:165337.7-165337.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:164020.3-164037.6" - wire $1\r_busy$next[0:0]$9018 - attribute \src "libresoc.v:163719.7-163719.20" + attribute \src "libresoc.v:165652.3-165669.6" + wire $1\r_busy$next[0:0]$9066 + attribute \src "libresoc.v:165351.7-165351.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire width 2 $1\xer_ca$next[1:0]$9002 - attribute \src "libresoc.v:163728.13-163728.26" + attribute \src "libresoc.v:165595.3-165613.6" + wire width 2 $1\xer_ca$next[1:0]$9050 + attribute \src "libresoc.v:165360.13-165360.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:163963.3-163981.6" - wire $1\xer_ca_ok$next[0:0]$9001 - attribute \src "libresoc.v:163737.7-163737.23" + attribute \src "libresoc.v:165595.3-165613.6" + wire $1\xer_ca_ok$next[0:0]$9049 + attribute \src "libresoc.v:165369.7-165369.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire width 2 $1\xer_ov$next[1:0]$9007 - attribute \src "libresoc.v:163744.13-163744.26" + attribute \src "libresoc.v:165614.3-165632.6" + wire width 2 $1\xer_ov$next[1:0]$9055 + attribute \src "libresoc.v:165376.13-165376.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:163982.3-164000.6" - wire $1\xer_ov_ok$next[0:0]$9008 - attribute \src "libresoc.v:163751.7-163751.23" + attribute \src "libresoc.v:165614.3-165632.6" + wire $1\xer_ov_ok$next[0:0]$9056 + attribute \src "libresoc.v:165383.7-165383.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $1\xer_so$next[0:0]$9013 - attribute \src "libresoc.v:163758.7-163758.20" + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so$next[0:0]$9061 + attribute \src "libresoc.v:165390.7-165390.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:164001.3-164019.6" - wire $1\xer_so_ok$next[0:0]$9014 - attribute \src "libresoc.v:163767.7-163767.23" + attribute \src "libresoc.v:165633.3-165651.6" + wire $1\xer_so_ok$next[0:0]$9062 + attribute \src "libresoc.v:165399.7-165399.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:164051.3-164092.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9060 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9061 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__oe__oe$next[0:0]$9062 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__oe__ok$next[0:0]$9063 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__rc__ok$next[0:0]$9064 - attribute \src "libresoc.v:164051.3-164092.6" - wire $2\alu_op__rc__rc$next[0:0]$9065 - attribute \src "libresoc.v:163944.3-163962.6" - wire $2\cr_a_ok$next[0:0]$8997 - attribute \src "libresoc.v:164093.3-164111.6" - wire $2\o_ok$next[0:0]$9071 - attribute \src "libresoc.v:164020.3-164037.6" - wire $2\r_busy$next[0:0]$9019 - attribute \src "libresoc.v:163963.3-163981.6" - wire $2\xer_ca_ok$next[0:0]$9003 - attribute \src "libresoc.v:163982.3-164000.6" - wire $2\xer_ov_ok$next[0:0]$9009 - attribute \src "libresoc.v:164001.3-164019.6" - wire $2\xer_so_ok$next[0:0]$9015 - attribute \src "libresoc.v:163774.18-163774.118" - wire $and$libresoc.v:163774$8961_Y + attribute \src "libresoc.v:165683.3-165724.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9109 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__oe$next[0:0]$9110 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__oe__ok$next[0:0]$9111 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__ok$next[0:0]$9112 + attribute \src "libresoc.v:165683.3-165724.6" + wire $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165576.3-165594.6" + wire $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165725.3-165743.6" + wire $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165652.3-165669.6" + wire $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165595.3-165613.6" + wire $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165614.3-165632.6" + wire $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165633.3-165651.6" + wire $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165406.18-165406.118" + wire $and$libresoc.v:165406$9009_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -338288,9 +340785,9 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -338304,7 +340801,7 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:162646.7-162646.15" + attribute \src "libresoc.v:164278.7-164278.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -338961,7 +341458,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163774$8961 + cell $and $and$libresoc.v:165406$9009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -338969,10 +341466,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:163774$8961_Y + connect \Y $and$libresoc.v:165406$9009_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163835.11-163882.4" + attribute \src "libresoc.v:165467.11-165514.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -339022,7 +341519,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163883.8-163935.4" + attribute \src "libresoc.v:165515.8-165567.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -339077,487 +341574,487 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:163936.9-163939.4" + attribute \src "libresoc.v:165568.9-165571.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163940.9-163943.4" + attribute \src "libresoc.v:165572.9-165575.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162646.7-162646.20" - process $proc$libresoc.v:162646$9072 + attribute \src "libresoc.v:164278.7-164278.20" + process $proc$libresoc.v:164278$9120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162651.13-162651.36" - process $proc$libresoc.v:162651$9073 + attribute \src "libresoc.v:164283.13-164283.36" + process $proc$libresoc.v:164283$9121 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:162675.14-162675.40" - process $proc$libresoc.v:162675$9074 + attribute \src "libresoc.v:164307.14-164307.40" + process $proc$libresoc.v:164307$9122 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:162714.14-162714.59" - process $proc$libresoc.v:162714$9075 + attribute \src "libresoc.v:164346.14-164346.59" + process $proc$libresoc.v:164346$9123 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:162723.7-162723.34" - process $proc$libresoc.v:162723$9076 + attribute \src "libresoc.v:164355.7-164355.34" + process $proc$libresoc.v:164355$9124 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:162736.13-162736.39" - process $proc$libresoc.v:162736$9077 + attribute \src "libresoc.v:164368.13-164368.39" + process $proc$libresoc.v:164368$9125 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:162753.14-162753.34" - process $proc$libresoc.v:162753$9078 + attribute \src "libresoc.v:164385.14-164385.34" + process $proc$libresoc.v:164385$9126 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:162837.13-162837.38" - process $proc$libresoc.v:162837$9079 + attribute \src "libresoc.v:164469.13-164469.38" + process $proc$libresoc.v:164469$9127 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:162996.7-162996.31" - process $proc$libresoc.v:162996$9080 + attribute \src "libresoc.v:164628.7-164628.31" + process $proc$libresoc.v:164628$9128 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:163005.7-163005.32" - process $proc$libresoc.v:163005$9081 + attribute \src "libresoc.v:164637.7-164637.32" + process $proc$libresoc.v:164637$9129 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:163014.7-163014.30" - process $proc$libresoc.v:163014$9082 + attribute \src "libresoc.v:164646.7-164646.30" + process $proc$libresoc.v:164646$9130 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:163023.7-163023.31" - process $proc$libresoc.v:163023$9083 + attribute \src "libresoc.v:164655.7-164655.31" + process $proc$libresoc.v:164655$9131 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:163032.7-163032.28" - process $proc$libresoc.v:163032$9084 + attribute \src "libresoc.v:164664.7-164664.28" + process $proc$libresoc.v:164664$9132 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:163041.7-163041.28" - process $proc$libresoc.v:163041$9085 + attribute \src "libresoc.v:164673.7-164673.28" + process $proc$libresoc.v:164673$9133 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:163050.7-163050.34" - process $proc$libresoc.v:163050$9086 + attribute \src "libresoc.v:164682.7-164682.34" + process $proc$libresoc.v:164682$9134 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:163059.7-163059.28" - process $proc$libresoc.v:163059$9087 + attribute \src "libresoc.v:164691.7-164691.28" + process $proc$libresoc.v:164691$9135 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:163068.7-163068.28" - process $proc$libresoc.v:163068$9088 + attribute \src "libresoc.v:164700.7-164700.28" + process $proc$libresoc.v:164700$9136 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:163077.7-163077.31" - process $proc$libresoc.v:163077$9089 + attribute \src "libresoc.v:164709.7-164709.31" + process $proc$libresoc.v:164709$9137 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:163086.7-163086.28" - process $proc$libresoc.v:163086$9090 + attribute \src "libresoc.v:164718.7-164718.28" + process $proc$libresoc.v:164718$9138 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:163099.13-163099.24" - process $proc$libresoc.v:163099$9091 + attribute \src "libresoc.v:164731.13-164731.24" + process $proc$libresoc.v:164731$9139 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:163106.7-163106.21" - process $proc$libresoc.v:163106$9092 + attribute \src "libresoc.v:164738.7-164738.21" + process $proc$libresoc.v:164738$9140 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:163683.13-163683.25" - process $proc$libresoc.v:163683$9093 + attribute \src "libresoc.v:165315.13-165315.25" + process $proc$libresoc.v:165315$9141 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:163698.14-163698.38" - process $proc$libresoc.v:163698$9094 + attribute \src "libresoc.v:165330.14-165330.38" + process $proc$libresoc.v:165330$9142 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163705.7-163705.18" - process $proc$libresoc.v:163705$9095 + attribute \src "libresoc.v:165337.7-165337.18" + process $proc$libresoc.v:165337$9143 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163719.7-163719.20" - process $proc$libresoc.v:163719$9096 + attribute \src "libresoc.v:165351.7-165351.20" + process $proc$libresoc.v:165351$9144 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163728.13-163728.26" - process $proc$libresoc.v:163728$9097 + attribute \src "libresoc.v:165360.13-165360.26" + process $proc$libresoc.v:165360$9145 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:163737.7-163737.23" - process $proc$libresoc.v:163737$9098 + attribute \src "libresoc.v:165369.7-165369.23" + process $proc$libresoc.v:165369$9146 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163744.13-163744.26" - process $proc$libresoc.v:163744$9099 + attribute \src "libresoc.v:165376.13-165376.26" + process $proc$libresoc.v:165376$9147 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:163751.7-163751.23" - process $proc$libresoc.v:163751$9100 + attribute \src "libresoc.v:165383.7-165383.23" + process $proc$libresoc.v:165383$9148 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:163758.7-163758.20" - process $proc$libresoc.v:163758$9101 + attribute \src "libresoc.v:165390.7-165390.20" + process $proc$libresoc.v:165390$9149 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:163767.7-163767.23" - process $proc$libresoc.v:163767$9102 + attribute \src "libresoc.v:165399.7-165399.23" + process $proc$libresoc.v:165399$9150 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:163775.3-163776.29" - process $proc$libresoc.v:163775$8962 + attribute \src "libresoc.v:165407.3-165408.29" + process $proc$libresoc.v:165407$9010 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:163777.3-163778.35" - process $proc$libresoc.v:163777$8963 + attribute \src "libresoc.v:165409.3-165410.35" + process $proc$libresoc.v:165409$9011 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:163779.3-163780.29" - process $proc$libresoc.v:163779$8964 + attribute \src "libresoc.v:165411.3-165412.29" + process $proc$libresoc.v:165411$9012 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:163781.3-163782.35" - process $proc$libresoc.v:163781$8965 + attribute \src "libresoc.v:165413.3-165414.35" + process $proc$libresoc.v:165413$9013 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:163783.3-163784.29" - process $proc$libresoc.v:163783$8966 + attribute \src "libresoc.v:165415.3-165416.29" + process $proc$libresoc.v:165415$9014 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:163785.3-163786.35" - process $proc$libresoc.v:163785$8967 + attribute \src "libresoc.v:165417.3-165418.35" + process $proc$libresoc.v:165417$9015 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163787.3-163788.25" - process $proc$libresoc.v:163787$8968 + attribute \src "libresoc.v:165419.3-165420.25" + process $proc$libresoc.v:165419$9016 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:163789.3-163790.31" - process $proc$libresoc.v:163789$8969 + attribute \src "libresoc.v:165421.3-165422.31" + process $proc$libresoc.v:165421$9017 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:163791.3-163792.19" - process $proc$libresoc.v:163791$8970 + attribute \src "libresoc.v:165423.3-165424.19" + process $proc$libresoc.v:165423$9018 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:163793.3-163794.25" - process $proc$libresoc.v:163793$8971 + attribute \src "libresoc.v:165425.3-165426.25" + process $proc$libresoc.v:165425$9019 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:163795.3-163796.51" - process $proc$libresoc.v:163795$8972 + attribute \src "libresoc.v:165427.3-165428.51" + process $proc$libresoc.v:165427$9020 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:163797.3-163798.47" - process $proc$libresoc.v:163797$8973 + attribute \src "libresoc.v:165429.3-165430.47" + process $proc$libresoc.v:165429$9021 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:163799.3-163800.61" - process $proc$libresoc.v:163799$8974 + attribute \src "libresoc.v:165431.3-165432.61" + process $proc$libresoc.v:165431$9022 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:163801.3-163802.57" - process $proc$libresoc.v:163801$8975 + attribute \src "libresoc.v:165433.3-165434.57" + process $proc$libresoc.v:165433$9023 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:163803.3-163804.45" - process $proc$libresoc.v:163803$8976 + attribute \src "libresoc.v:165435.3-165436.45" + process $proc$libresoc.v:165435$9024 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:163805.3-163806.45" - process $proc$libresoc.v:163805$8977 + attribute \src "libresoc.v:165437.3-165438.45" + process $proc$libresoc.v:165437$9025 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:163807.3-163808.45" - process $proc$libresoc.v:163807$8978 + attribute \src "libresoc.v:165439.3-165440.45" + process $proc$libresoc.v:165439$9026 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:163809.3-163810.45" - process $proc$libresoc.v:163809$8979 + attribute \src "libresoc.v:165441.3-165442.45" + process $proc$libresoc.v:165441$9027 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:163811.3-163812.51" - process $proc$libresoc.v:163811$8980 + attribute \src "libresoc.v:165443.3-165444.51" + process $proc$libresoc.v:165443$9028 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:163813.3-163814.45" - process $proc$libresoc.v:163813$8981 + attribute \src "libresoc.v:165445.3-165446.45" + process $proc$libresoc.v:165445$9029 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:163815.3-163816.53" - process $proc$libresoc.v:163815$8982 + attribute \src "libresoc.v:165447.3-165448.53" + process $proc$libresoc.v:165447$9030 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:163817.3-163818.51" - process $proc$libresoc.v:163817$8983 + attribute \src "libresoc.v:165449.3-165450.51" + process $proc$libresoc.v:165449$9031 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:163819.3-163820.55" - process $proc$libresoc.v:163819$8984 + attribute \src "libresoc.v:165451.3-165452.55" + process $proc$libresoc.v:165451$9032 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:163821.3-163822.57" - process $proc$libresoc.v:163821$8985 + attribute \src "libresoc.v:165453.3-165454.57" + process $proc$libresoc.v:165453$9033 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:163823.3-163824.49" - process $proc$libresoc.v:163823$8986 + attribute \src "libresoc.v:165455.3-165456.49" + process $proc$libresoc.v:165455$9034 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:163825.3-163826.51" - process $proc$libresoc.v:163825$8987 + attribute \src "libresoc.v:165457.3-165458.51" + process $proc$libresoc.v:165457$9035 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:163827.3-163828.49" - process $proc$libresoc.v:163827$8988 + attribute \src "libresoc.v:165459.3-165460.49" + process $proc$libresoc.v:165459$9036 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:163829.3-163830.41" - process $proc$libresoc.v:163829$8989 + attribute \src "libresoc.v:165461.3-165462.41" + process $proc$libresoc.v:165461$9037 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:163831.3-163832.27" - process $proc$libresoc.v:163831$8990 + attribute \src "libresoc.v:165463.3-165464.27" + process $proc$libresoc.v:165463$9038 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:163833.3-163834.29" - process $proc$libresoc.v:163833$8991 + attribute \src "libresoc.v:165465.3-165466.29" + process $proc$libresoc.v:165465$9039 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163944.3-163962.6" - process $proc$libresoc.v:163944$8992 + attribute \src "libresoc.v:165576.3-165594.6" + process $proc$libresoc.v:165576$9040 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8993 $1\cr_a$next[3:0]$8995 + assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 assign { } { } - assign $0\cr_a_ok$next[0:0]$8994 $2\cr_a_ok$next[0:0]$8997 - attribute \src "libresoc.v:163945.5-163945.29" + assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 + attribute \src "libresoc.v:165577.5-165577.29" switch \initial - attribute \src "libresoc.v:163945.9-163945.17" + attribute \src "libresoc.v:165577.9-165577.17" case 1'1 case end @@ -339567,41 +342064,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8996 $1\cr_a$next[3:0]$8995 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\cr_a$next[3:0]$8995 \cr_a - assign $1\cr_a_ok$next[0:0]$8996 \cr_a_ok + assign $1\cr_a$next[3:0]$9043 \cr_a + assign $1\cr_a_ok$next[0:0]$9044 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8997 1'0 + assign $2\cr_a_ok$next[0:0]$9045 1'0 case - assign $2\cr_a_ok$next[0:0]$8997 $1\cr_a_ok$next[0:0]$8996 + assign $2\cr_a_ok$next[0:0]$9045 $1\cr_a_ok$next[0:0]$9044 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8993 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8994 + update \cr_a$next $0\cr_a$next[3:0]$9041 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 end - attribute \src "libresoc.v:163963.3-163981.6" - process $proc$libresoc.v:163963$8998 + attribute \src "libresoc.v:165595.3-165613.6" + process $proc$libresoc.v:165595$9046 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9000 $1\xer_ca$next[1:0]$9002 - assign $0\xer_ca_ok$next[0:0]$8999 $2\xer_ca_ok$next[0:0]$9003 - attribute \src "libresoc.v:163964.5-163964.29" + assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 + assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:165596.5-165596.29" switch \initial - attribute \src "libresoc.v:163964.9-163964.17" + attribute \src "libresoc.v:165596.9-165596.17" case 1'1 case end @@ -339611,41 +342108,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9001 $1\xer_ca$next[1:0]$9002 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } case - assign $1\xer_ca_ok$next[0:0]$9001 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9002 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9049 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9050 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9003 1'0 + assign $2\xer_ca_ok$next[0:0]$9051 1'0 case - assign $2\xer_ca_ok$next[0:0]$9003 $1\xer_ca_ok$next[0:0]$9001 + assign $2\xer_ca_ok$next[0:0]$9051 $1\xer_ca_ok$next[0:0]$9049 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8999 - update \xer_ca$next $0\xer_ca$next[1:0]$9000 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 + update \xer_ca$next $0\xer_ca$next[1:0]$9048 end - attribute \src "libresoc.v:163982.3-164000.6" - process $proc$libresoc.v:163982$9004 + attribute \src "libresoc.v:165614.3-165632.6" + process $proc$libresoc.v:165614$9052 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9005 $1\xer_ov$next[1:0]$9007 + assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9006 $2\xer_ov_ok$next[0:0]$9009 - attribute \src "libresoc.v:163983.5-163983.29" + assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 + attribute \src "libresoc.v:165615.5-165615.29" switch \initial - attribute \src "libresoc.v:163983.9-163983.17" + attribute \src "libresoc.v:165615.9-165615.17" case 1'1 case end @@ -339655,41 +342152,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9008 $1\xer_ov$next[1:0]$9007 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } case - assign $1\xer_ov$next[1:0]$9007 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9008 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9055 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9056 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9009 1'0 + assign $2\xer_ov_ok$next[0:0]$9057 1'0 case - assign $2\xer_ov_ok$next[0:0]$9009 $1\xer_ov_ok$next[0:0]$9008 + assign $2\xer_ov_ok$next[0:0]$9057 $1\xer_ov_ok$next[0:0]$9056 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9005 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9006 + update \xer_ov$next $0\xer_ov$next[1:0]$9053 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 end - attribute \src "libresoc.v:164001.3-164019.6" - process $proc$libresoc.v:164001$9010 + attribute \src "libresoc.v:165633.3-165651.6" + process $proc$libresoc.v:165633$9058 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9011 $1\xer_so$next[0:0]$9013 + assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 assign { } { } - assign $0\xer_so_ok$next[0:0]$9012 $2\xer_so_ok$next[0:0]$9015 - attribute \src "libresoc.v:164002.5-164002.29" + assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 + attribute \src "libresoc.v:165634.5-165634.29" switch \initial - attribute \src "libresoc.v:164002.9-164002.17" + attribute \src "libresoc.v:165634.9-165634.17" case 1'1 case end @@ -339699,38 +342196,38 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9014 $1\xer_so$next[0:0]$9013 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } case - assign $1\xer_so$next[0:0]$9013 \xer_so - assign $1\xer_so_ok$next[0:0]$9014 \xer_so_ok + assign $1\xer_so$next[0:0]$9061 \xer_so + assign $1\xer_so_ok$next[0:0]$9062 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9015 1'0 + assign $2\xer_so_ok$next[0:0]$9063 1'0 case - assign $2\xer_so_ok$next[0:0]$9015 $1\xer_so_ok$next[0:0]$9014 + assign $2\xer_so_ok$next[0:0]$9063 $1\xer_so_ok$next[0:0]$9062 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9011 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9012 + update \xer_so$next $0\xer_so$next[0:0]$9059 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 end - attribute \src "libresoc.v:164020.3-164037.6" - process $proc$libresoc.v:164020$9016 + attribute \src "libresoc.v:165652.3-165669.6" + process $proc$libresoc.v:165652$9064 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9017 $2\r_busy$next[0:0]$9019 - attribute \src "libresoc.v:164021.5-164021.29" + assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:165653.5-165653.29" switch \initial - attribute \src "libresoc.v:164021.9-164021.17" + attribute \src "libresoc.v:165653.9-165653.17" case 1'1 case end @@ -339739,34 +342236,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9018 1'1 + assign $1\r_busy$next[0:0]$9066 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9018 1'0 + assign $1\r_busy$next[0:0]$9066 1'0 case - assign $1\r_busy$next[0:0]$9018 \r_busy + assign $1\r_busy$next[0:0]$9066 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9019 1'0 + assign $2\r_busy$next[0:0]$9067 1'0 case - assign $2\r_busy$next[0:0]$9019 $1\r_busy$next[0:0]$9018 + assign $2\r_busy$next[0:0]$9067 $1\r_busy$next[0:0]$9066 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9017 + update \r_busy$next $0\r_busy$next[0:0]$9065 end - attribute \src "libresoc.v:164038.3-164050.6" - process $proc$libresoc.v:164038$9020 + attribute \src "libresoc.v:165670.3-165682.6" + process $proc$libresoc.v:165670$9068 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9021 $1\muxid$next[1:0]$9022 - attribute \src "libresoc.v:164039.5-164039.29" + assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 + attribute \src "libresoc.v:165671.5-165671.29" switch \initial - attribute \src "libresoc.v:164039.9-164039.17" + attribute \src "libresoc.v:165671.9-165671.17" case 1'1 case end @@ -339775,19 +342272,19 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9022 \muxid$69 + assign $1\muxid$next[1:0]$9070 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9022 \muxid$69 + assign $1\muxid$next[1:0]$9070 \muxid$69 case - assign $1\muxid$next[1:0]$9022 \muxid + assign $1\muxid$next[1:0]$9070 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9021 + update \muxid$next $0\muxid$next[1:0]$9069 end - attribute \src "libresoc.v:164051.3-164092.6" - process $proc$libresoc.v:164051$9023 + attribute \src "libresoc.v:165683.3-165724.6" + process $proc$libresoc.v:165683$9071 assign { } { } assign { } { } assign { } { } @@ -339824,33 +342321,33 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$next[3:0]$9024 $1\alu_op__data_len$next[3:0]$9042 - assign $0\alu_op__fn_unit$next[13:0]$9025 $1\alu_op__fn_unit$next[13:0]$9043 + assign $0\alu_op__data_len$next[3:0]$9072 $1\alu_op__data_len$next[3:0]$9090 + assign $0\alu_op__fn_unit$next[13:0]$9073 $1\alu_op__fn_unit$next[13:0]$9091 assign { } { } assign { } { } - assign $0\alu_op__input_carry$next[1:0]$9028 $1\alu_op__input_carry$next[1:0]$9046 - assign $0\alu_op__insn$next[31:0]$9029 $1\alu_op__insn$next[31:0]$9047 - assign $0\alu_op__insn_type$next[6:0]$9030 $1\alu_op__insn_type$next[6:0]$9048 - assign $0\alu_op__invert_in$next[0:0]$9031 $1\alu_op__invert_in$next[0:0]$9049 - assign $0\alu_op__invert_out$next[0:0]$9032 $1\alu_op__invert_out$next[0:0]$9050 - assign $0\alu_op__is_32bit$next[0:0]$9033 $1\alu_op__is_32bit$next[0:0]$9051 - assign $0\alu_op__is_signed$next[0:0]$9034 $1\alu_op__is_signed$next[0:0]$9052 + assign $0\alu_op__input_carry$next[1:0]$9076 $1\alu_op__input_carry$next[1:0]$9094 + assign $0\alu_op__insn$next[31:0]$9077 $1\alu_op__insn$next[31:0]$9095 + assign $0\alu_op__insn_type$next[6:0]$9078 $1\alu_op__insn_type$next[6:0]$9096 + assign $0\alu_op__invert_in$next[0:0]$9079 $1\alu_op__invert_in$next[0:0]$9097 + assign $0\alu_op__invert_out$next[0:0]$9080 $1\alu_op__invert_out$next[0:0]$9098 + assign $0\alu_op__is_32bit$next[0:0]$9081 $1\alu_op__is_32bit$next[0:0]$9099 + assign $0\alu_op__is_signed$next[0:0]$9082 $1\alu_op__is_signed$next[0:0]$9100 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$9037 $1\alu_op__output_carry$next[0:0]$9055 + assign $0\alu_op__output_carry$next[0:0]$9085 $1\alu_op__output_carry$next[0:0]$9103 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$9040 $1\alu_op__write_cr0$next[0:0]$9058 - assign $0\alu_op__zero_a$next[0:0]$9041 $1\alu_op__zero_a$next[0:0]$9059 - assign $0\alu_op__imm_data__data$next[63:0]$9026 $2\alu_op__imm_data__data$next[63:0]$9060 - assign $0\alu_op__imm_data__ok$next[0:0]$9027 $2\alu_op__imm_data__ok$next[0:0]$9061 - assign $0\alu_op__oe__oe$next[0:0]$9035 $2\alu_op__oe__oe$next[0:0]$9062 - assign $0\alu_op__oe__ok$next[0:0]$9036 $2\alu_op__oe__ok$next[0:0]$9063 - assign $0\alu_op__rc__ok$next[0:0]$9038 $2\alu_op__rc__ok$next[0:0]$9064 - assign $0\alu_op__rc__rc$next[0:0]$9039 $2\alu_op__rc__rc$next[0:0]$9065 - attribute \src "libresoc.v:164052.5-164052.29" + assign $0\alu_op__write_cr0$next[0:0]$9088 $1\alu_op__write_cr0$next[0:0]$9106 + assign $0\alu_op__zero_a$next[0:0]$9089 $1\alu_op__zero_a$next[0:0]$9107 + assign $0\alu_op__imm_data__data$next[63:0]$9074 $2\alu_op__imm_data__data$next[63:0]$9108 + assign $0\alu_op__imm_data__ok$next[0:0]$9075 $2\alu_op__imm_data__ok$next[0:0]$9109 + assign $0\alu_op__oe__oe$next[0:0]$9083 $2\alu_op__oe__oe$next[0:0]$9110 + assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 + assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 + assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 + attribute \src "libresoc.v:165684.5-165684.29" switch \initial - attribute \src "libresoc.v:164052.9-164052.17" + attribute \src "libresoc.v:165684.9-165684.17" case 1'1 case end @@ -339876,7 +342373,7 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -339897,26 +342394,26 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9047 $1\alu_op__data_len$next[3:0]$9042 $1\alu_op__is_signed$next[0:0]$9052 $1\alu_op__is_32bit$next[0:0]$9051 $1\alu_op__output_carry$next[0:0]$9055 $1\alu_op__input_carry$next[1:0]$9046 $1\alu_op__write_cr0$next[0:0]$9058 $1\alu_op__invert_out$next[0:0]$9050 $1\alu_op__zero_a$next[0:0]$9059 $1\alu_op__invert_in$next[0:0]$9049 $1\alu_op__oe__ok$next[0:0]$9054 $1\alu_op__oe__oe$next[0:0]$9053 $1\alu_op__rc__ok$next[0:0]$9056 $1\alu_op__rc__rc$next[0:0]$9057 $1\alu_op__imm_data__ok$next[0:0]$9045 $1\alu_op__imm_data__data$next[63:0]$9044 $1\alu_op__fn_unit$next[13:0]$9043 $1\alu_op__insn_type$next[6:0]$9048 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case - assign $1\alu_op__data_len$next[3:0]$9042 \alu_op__data_len - assign $1\alu_op__fn_unit$next[13:0]$9043 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$9044 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9045 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9046 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9047 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9048 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9049 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9050 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9051 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9052 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9053 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9054 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9055 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9056 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9057 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9058 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9059 \alu_op__zero_a + assign $1\alu_op__data_len$next[3:0]$9090 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9091 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9092 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9093 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9094 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9095 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9096 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9097 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9098 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9099 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9100 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9101 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9102 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9103 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9104 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9105 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9106 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9107 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -339928,52 +342425,52 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9060 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9061 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9065 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9064 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9062 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9063 1'0 + assign $2\alu_op__imm_data__data$next[63:0]$9108 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9113 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9112 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9110 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9111 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9060 $1\alu_op__imm_data__data$next[63:0]$9044 - assign $2\alu_op__imm_data__ok$next[0:0]$9061 $1\alu_op__imm_data__ok$next[0:0]$9045 - assign $2\alu_op__oe__oe$next[0:0]$9062 $1\alu_op__oe__oe$next[0:0]$9053 - assign $2\alu_op__oe__ok$next[0:0]$9063 $1\alu_op__oe__ok$next[0:0]$9054 - assign $2\alu_op__rc__ok$next[0:0]$9064 $1\alu_op__rc__ok$next[0:0]$9056 - assign $2\alu_op__rc__rc$next[0:0]$9065 $1\alu_op__rc__rc$next[0:0]$9057 + assign $2\alu_op__imm_data__data$next[63:0]$9108 $1\alu_op__imm_data__data$next[63:0]$9092 + assign $2\alu_op__imm_data__ok$next[0:0]$9109 $1\alu_op__imm_data__ok$next[0:0]$9093 + assign $2\alu_op__oe__oe$next[0:0]$9110 $1\alu_op__oe__oe$next[0:0]$9101 + assign $2\alu_op__oe__ok$next[0:0]$9111 $1\alu_op__oe__ok$next[0:0]$9102 + assign $2\alu_op__rc__ok$next[0:0]$9112 $1\alu_op__rc__ok$next[0:0]$9104 + assign $2\alu_op__rc__rc$next[0:0]$9113 $1\alu_op__rc__rc$next[0:0]$9105 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9024 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9025 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9026 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9027 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9028 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9029 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9030 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9031 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9032 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9033 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9034 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9035 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9036 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9037 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9038 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9039 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9040 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9041 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9072 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9073 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9074 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9075 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9076 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9077 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9078 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9079 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9080 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9081 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9082 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9083 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9084 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9085 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9086 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9087 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 end - attribute \src "libresoc.v:164093.3-164111.6" - process $proc$libresoc.v:164093$9066 + attribute \src "libresoc.v:165725.3-165743.6" + process $proc$libresoc.v:165725$9114 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9067 $1\o$next[63:0]$9069 + assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 assign { } { } - assign $0\o_ok$next[0:0]$9068 $2\o_ok$next[0:0]$9071 - attribute \src "libresoc.v:164094.5-164094.29" + assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 + attribute \src "libresoc.v:165726.5-165726.29" switch \initial - attribute \src "libresoc.v:164094.9-164094.17" + attribute \src "libresoc.v:165726.9-165726.17" case 1'1 case end @@ -339983,30 +342480,30 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9070 $1\o$next[63:0]$9069 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } case - assign $1\o$next[63:0]$9069 \o - assign $1\o_ok$next[0:0]$9070 \o_ok + assign $1\o$next[63:0]$9117 \o + assign $1\o_ok$next[0:0]$9118 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9071 1'0 + assign $2\o_ok$next[0:0]$9119 1'0 case - assign $2\o_ok$next[0:0]$9071 $1\o_ok$next[0:0]$9070 + assign $2\o_ok$next[0:0]$9119 $1\o_ok$next[0:0]$9118 end sync always - update \o$next $0\o$next[63:0]$9067 - update \o_ok$next $0\o_ok$next[0:0]$9068 + update \o$next $0\o$next[63:0]$9115 + update \o_ok$next $0\o_ok$next[0:0]$9116 end - connect \$67 $and$libresoc.v:163774$8961_Y + connect \$67 $and$libresoc.v:165406$9009_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -340033,258 +342530,258 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:164141.1-165577.10" +attribute \src "libresoc.v:165773.1-167209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:165510.3-165528.6" - wire width 4 $0\cr_a$next[3:0]$9192 - attribute \src "libresoc.v:165252.3-165253.25" + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $0\cr_a$next[3:0]$9240 + attribute \src "libresoc.v:166884.3-166885.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $0\cr_a_ok$next[0:0]$9193 - attribute \src "libresoc.v:165254.3-165255.31" + attribute \src "libresoc.v:167142.3-167160.6" + wire $0\cr_a_ok$next[0:0]$9241 + attribute \src "libresoc.v:166886.3-166887.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:164142.7-164142.20" + attribute \src "libresoc.v:165774.7-165774.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165437.3-165449.6" - wire width 2 $0\muxid$next[1:0]$9142 - attribute \src "libresoc.v:165294.3-165295.27" + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $0\muxid$next[1:0]$9190 + attribute \src "libresoc.v:166926.3-166927.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire width 64 $0\o$next[63:0]$9186 - attribute \src "libresoc.v:165256.3-165257.19" + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $0\o$next[63:0]$9234 + attribute \src "libresoc.v:166888.3-166889.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire $0\o_ok$next[0:0]$9187 - attribute \src "libresoc.v:165258.3-165259.25" + attribute \src "libresoc.v:167123.3-167141.6" + wire $0\o_ok$next[0:0]$9235 + attribute \src "libresoc.v:166890.3-166891.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165419.3-165436.6" - wire $0\r_busy$next[0:0]$9138 - attribute \src "libresoc.v:165296.3-165297.29" + attribute \src "libresoc.v:167051.3-167068.6" + wire $0\r_busy$next[0:0]$9186 + attribute \src "libresoc.v:166928.3-166929.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 14 $0\sr_op__fn_unit$next[13:0]$9145 - attribute \src "libresoc.v:165262.3-165263.45" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 + attribute \src "libresoc.v:166894.3-166895.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9146 - attribute \src "libresoc.v:165264.3-165265.59" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 + attribute \src "libresoc.v:166896.3-166897.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9147 - attribute \src "libresoc.v:165266.3-165267.55" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9195 + attribute \src "libresoc.v:166898.3-166899.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9148 - attribute \src "libresoc.v:165280.3-165281.53" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9196 + attribute \src "libresoc.v:166912.3-166913.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__input_cr$next[0:0]$9149 - attribute \src "libresoc.v:165284.3-165285.47" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__input_cr$next[0:0]$9197 + attribute \src "libresoc.v:166916.3-166917.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 32 $0\sr_op__insn$next[31:0]$9150 - attribute \src "libresoc.v:165292.3-165293.39" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $0\sr_op__insn$next[31:0]$9198 + attribute \src "libresoc.v:166924.3-166925.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9151 - attribute \src "libresoc.v:165260.3-165261.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9199 + attribute \src "libresoc.v:166892.3-166893.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__invert_in$next[0:0]$9152 - attribute \src "libresoc.v:165278.3-165279.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__invert_in$next[0:0]$9200 + attribute \src "libresoc.v:166910.3-166911.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__is_32bit$next[0:0]$9153 - attribute \src "libresoc.v:165288.3-165289.47" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_32bit$next[0:0]$9201 + attribute \src "libresoc.v:166920.3-166921.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__is_signed$next[0:0]$9154 - attribute \src "libresoc.v:165290.3-165291.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__is_signed$next[0:0]$9202 + attribute \src "libresoc.v:166922.3-166923.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__oe__oe$next[0:0]$9155 - attribute \src "libresoc.v:165272.3-165273.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__oe$next[0:0]$9203 + attribute \src "libresoc.v:166904.3-166905.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__oe__ok$next[0:0]$9156 - attribute \src "libresoc.v:165274.3-165275.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__oe__ok$next[0:0]$9204 + attribute \src "libresoc.v:166906.3-166907.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__output_carry$next[0:0]$9157 - attribute \src "libresoc.v:165282.3-165283.55" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_carry$next[0:0]$9205 + attribute \src "libresoc.v:166914.3-166915.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__output_cr$next[0:0]$9158 - attribute \src "libresoc.v:165286.3-165287.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__output_cr$next[0:0]$9206 + attribute \src "libresoc.v:166918.3-166919.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__rc__ok$next[0:0]$9159 - attribute \src "libresoc.v:165270.3-165271.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__ok$next[0:0]$9207 + attribute \src "libresoc.v:166902.3-166903.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__rc__rc$next[0:0]$9160 - attribute \src "libresoc.v:165268.3-165269.43" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__rc__rc$next[0:0]$9208 + attribute \src "libresoc.v:166900.3-166901.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $0\sr_op__write_cr0$next[0:0]$9161 - attribute \src "libresoc.v:165276.3-165277.49" + attribute \src "libresoc.v:167082.3-167122.6" + wire $0\sr_op__write_cr0$next[0:0]$9209 + attribute \src "libresoc.v:166908.3-166909.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire width 2 $0\xer_ca$next[1:0]$9133 - attribute \src "libresoc.v:165244.3-165245.29" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $0\xer_ca$next[1:0]$9181 + attribute \src "libresoc.v:166876.3-166877.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire $0\xer_ca_ok$next[0:0]$9132 - attribute \src "libresoc.v:165246.3-165247.35" + attribute \src "libresoc.v:167032.3-167050.6" + wire $0\xer_ca_ok$next[0:0]$9180 + attribute \src "libresoc.v:166878.3-166879.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $0\xer_so$next[0:0]$9198 - attribute \src "libresoc.v:165248.3-165249.29" + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so$next[0:0]$9246 + attribute \src "libresoc.v:166880.3-166881.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $0\xer_so_ok$next[0:0]$9199 - attribute \src "libresoc.v:165250.3-165251.35" + attribute \src "libresoc.v:167161.3-167179.6" + wire $0\xer_so_ok$next[0:0]$9247 + attribute \src "libresoc.v:166882.3-166883.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire width 4 $1\cr_a$next[3:0]$9194 - attribute \src "libresoc.v:164151.13-164151.24" + attribute \src "libresoc.v:167142.3-167160.6" + wire width 4 $1\cr_a$next[3:0]$9242 + attribute \src "libresoc.v:165783.13-165783.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $1\cr_a_ok$next[0:0]$9195 - attribute \src "libresoc.v:164160.7-164160.21" + attribute \src "libresoc.v:167142.3-167160.6" + wire $1\cr_a_ok$next[0:0]$9243 + attribute \src "libresoc.v:165792.7-165792.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:165437.3-165449.6" - wire width 2 $1\muxid$next[1:0]$9143 - attribute \src "libresoc.v:164725.13-164725.25" + attribute \src "libresoc.v:167069.3-167081.6" + wire width 2 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:166357.13-166357.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire width 64 $1\o$next[63:0]$9188 - attribute \src "libresoc.v:164740.14-164740.38" + attribute \src "libresoc.v:167123.3-167141.6" + wire width 64 $1\o$next[63:0]$9236 + attribute \src "libresoc.v:166372.14-166372.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165491.3-165509.6" - wire $1\o_ok$next[0:0]$9189 - attribute \src "libresoc.v:164747.7-164747.18" + attribute \src "libresoc.v:167123.3-167141.6" + wire $1\o_ok$next[0:0]$9237 + attribute \src "libresoc.v:166379.7-166379.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165419.3-165436.6" - wire $1\r_busy$next[0:0]$9139 - attribute \src "libresoc.v:164761.7-164761.20" + attribute \src "libresoc.v:167051.3-167068.6" + wire $1\r_busy$next[0:0]$9187 + attribute \src "libresoc.v:166393.7-166393.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 14 $1\sr_op__fn_unit$next[13:0]$9162 - attribute \src "libresoc.v:164787.14-164787.39" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 + attribute \src "libresoc.v:166419.14-166419.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9163 - attribute \src "libresoc.v:164826.14-164826.58" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 + attribute \src "libresoc.v:166458.14-166458.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9164 - attribute \src "libresoc.v:164835.7-164835.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9212 + attribute \src "libresoc.v:166467.7-166467.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9165 - attribute \src "libresoc.v:164848.13-164848.38" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9213 + attribute \src "libresoc.v:166480.13-166480.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__input_cr$next[0:0]$9166 - attribute \src "libresoc.v:164865.7-164865.29" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__input_cr$next[0:0]$9214 + attribute \src "libresoc.v:166497.7-166497.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 32 $1\sr_op__insn$next[31:0]$9167 - attribute \src "libresoc.v:164874.14-164874.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 32 $1\sr_op__insn$next[31:0]$9215 + attribute \src "libresoc.v:166506.14-166506.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9168 - attribute \src "libresoc.v:164958.13-164958.37" + attribute \src "libresoc.v:167082.3-167122.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9216 + attribute \src "libresoc.v:166590.13-166590.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__invert_in$next[0:0]$9169 - attribute \src "libresoc.v:165117.7-165117.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__invert_in$next[0:0]$9217 + attribute \src "libresoc.v:166749.7-166749.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__is_32bit$next[0:0]$9170 - attribute \src "libresoc.v:165126.7-165126.29" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_32bit$next[0:0]$9218 + attribute \src "libresoc.v:166758.7-166758.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__is_signed$next[0:0]$9171 - attribute \src "libresoc.v:165135.7-165135.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__is_signed$next[0:0]$9219 + attribute \src "libresoc.v:166767.7-166767.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__oe__oe$next[0:0]$9172 - attribute \src "libresoc.v:165144.7-165144.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__oe$next[0:0]$9220 + attribute \src "libresoc.v:166776.7-166776.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__oe__ok$next[0:0]$9173 - attribute \src "libresoc.v:165153.7-165153.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__oe__ok$next[0:0]$9221 + attribute \src "libresoc.v:166785.7-166785.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__output_carry$next[0:0]$9174 - attribute \src "libresoc.v:165162.7-165162.33" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_carry$next[0:0]$9222 + attribute \src "libresoc.v:166794.7-166794.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__output_cr$next[0:0]$9175 - attribute \src "libresoc.v:165171.7-165171.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__output_cr$next[0:0]$9223 + attribute \src "libresoc.v:166803.7-166803.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__rc__ok$next[0:0]$9176 - attribute \src "libresoc.v:165180.7-165180.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__ok$next[0:0]$9224 + attribute \src "libresoc.v:166812.7-166812.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__rc__rc$next[0:0]$9177 - attribute \src "libresoc.v:165189.7-165189.27" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__rc__rc$next[0:0]$9225 + attribute \src "libresoc.v:166821.7-166821.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:165450.3-165490.6" - wire $1\sr_op__write_cr0$next[0:0]$9178 - attribute \src "libresoc.v:165198.7-165198.30" + attribute \src "libresoc.v:167082.3-167122.6" + wire $1\sr_op__write_cr0$next[0:0]$9226 + attribute \src "libresoc.v:166830.7-166830.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire width 2 $1\xer_ca$next[1:0]$9135 - attribute \src "libresoc.v:165207.13-165207.26" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 2 $1\xer_ca$next[1:0]$9183 + attribute \src "libresoc.v:166839.13-166839.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:165400.3-165418.6" - wire $1\xer_ca_ok$next[0:0]$9134 - attribute \src "libresoc.v:165218.7-165218.23" + attribute \src "libresoc.v:167032.3-167050.6" + wire $1\xer_ca_ok$next[0:0]$9182 + attribute \src "libresoc.v:166850.7-166850.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $1\xer_so$next[0:0]$9200 - attribute \src "libresoc.v:165227.7-165227.20" + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so$next[0:0]$9248 + attribute \src "libresoc.v:166859.7-166859.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:165529.3-165547.6" - wire $1\xer_so_ok$next[0:0]$9201 - attribute \src "libresoc.v:165236.7-165236.23" + attribute \src "libresoc.v:167161.3-167179.6" + wire $1\xer_so_ok$next[0:0]$9249 + attribute \src "libresoc.v:166868.7-166868.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165510.3-165528.6" - wire $2\cr_a_ok$next[0:0]$9196 - attribute \src "libresoc.v:165491.3-165509.6" - wire $2\o_ok$next[0:0]$9190 - attribute \src "libresoc.v:165419.3-165436.6" - wire $2\r_busy$next[0:0]$9140 - attribute \src "libresoc.v:165450.3-165490.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9179 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9180 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__oe__oe$next[0:0]$9181 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__oe__ok$next[0:0]$9182 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__rc__ok$next[0:0]$9183 - attribute \src "libresoc.v:165450.3-165490.6" - wire $2\sr_op__rc__rc$next[0:0]$9184 - attribute \src "libresoc.v:165400.3-165418.6" - wire $2\xer_ca_ok$next[0:0]$9136 - attribute \src "libresoc.v:165529.3-165547.6" - wire $2\xer_so_ok$next[0:0]$9202 - attribute \src "libresoc.v:165243.18-165243.118" - wire $and$libresoc.v:165243$9103_Y + attribute \src "libresoc.v:167142.3-167160.6" + wire $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167123.3-167141.6" + wire $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167051.3-167068.6" + wire $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167082.3-167122.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9228 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__oe$next[0:0]$9229 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__oe__ok$next[0:0]$9230 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__ok$next[0:0]$9231 + attribute \src "libresoc.v:167082.3-167122.6" + wire $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167032.3-167050.6" + wire $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167161.3-167179.6" + wire $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:166875.18-166875.118" + wire $and$libresoc.v:166875$9151_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 24 \cr_a @@ -340302,7 +342799,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:164142.7-164142.15" + attribute \src "libresoc.v:165774.7-165774.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -341357,7 +343854,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165243$9103 + cell $and $and$libresoc.v:166875$9151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -341365,10 +343862,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:165243$9103_Y + connect \Y $and$libresoc.v:166875$9151_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165298.15-165345.4" + attribute \src "libresoc.v:166930.15-166977.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -341418,7 +343915,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165346.14-165391.4" + attribute \src "libresoc.v:166978.14-167023.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -341466,442 +343963,442 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165392.11-165395.4" + attribute \src "libresoc.v:167024.11-167027.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165396.11-165399.4" + attribute \src "libresoc.v:167028.11-167031.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164142.7-164142.20" - process $proc$libresoc.v:164142$9203 + attribute \src "libresoc.v:165774.7-165774.20" + process $proc$libresoc.v:165774$9251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164151.13-164151.24" - process $proc$libresoc.v:164151$9204 + attribute \src "libresoc.v:165783.13-165783.24" + process $proc$libresoc.v:165783$9252 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:164160.7-164160.21" - process $proc$libresoc.v:164160$9205 + attribute \src "libresoc.v:165792.7-165792.21" + process $proc$libresoc.v:165792$9253 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:164725.13-164725.25" - process $proc$libresoc.v:164725$9206 + attribute \src "libresoc.v:166357.13-166357.25" + process $proc$libresoc.v:166357$9254 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:164740.14-164740.38" - process $proc$libresoc.v:164740$9207 + attribute \src "libresoc.v:166372.14-166372.38" + process $proc$libresoc.v:166372$9255 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:164747.7-164747.18" - process $proc$libresoc.v:164747$9208 + attribute \src "libresoc.v:166379.7-166379.18" + process $proc$libresoc.v:166379$9256 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:164761.7-164761.20" - process $proc$libresoc.v:164761$9209 + attribute \src "libresoc.v:166393.7-166393.20" + process $proc$libresoc.v:166393$9257 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:164787.14-164787.39" - process $proc$libresoc.v:164787$9210 + attribute \src "libresoc.v:166419.14-166419.39" + process $proc$libresoc.v:166419$9258 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:164826.14-164826.58" - process $proc$libresoc.v:164826$9211 + attribute \src "libresoc.v:166458.14-166458.58" + process $proc$libresoc.v:166458$9259 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:164835.7-164835.33" - process $proc$libresoc.v:164835$9212 + attribute \src "libresoc.v:166467.7-166467.33" + process $proc$libresoc.v:166467$9260 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:164848.13-164848.38" - process $proc$libresoc.v:164848$9213 + attribute \src "libresoc.v:166480.13-166480.38" + process $proc$libresoc.v:166480$9261 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:164865.7-164865.29" - process $proc$libresoc.v:164865$9214 + attribute \src "libresoc.v:166497.7-166497.29" + process $proc$libresoc.v:166497$9262 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:164874.14-164874.33" - process $proc$libresoc.v:164874$9215 + attribute \src "libresoc.v:166506.14-166506.33" + process $proc$libresoc.v:166506$9263 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:164958.13-164958.37" - process $proc$libresoc.v:164958$9216 + attribute \src "libresoc.v:166590.13-166590.37" + process $proc$libresoc.v:166590$9264 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:165117.7-165117.30" - process $proc$libresoc.v:165117$9217 + attribute \src "libresoc.v:166749.7-166749.30" + process $proc$libresoc.v:166749$9265 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:165126.7-165126.29" - process $proc$libresoc.v:165126$9218 + attribute \src "libresoc.v:166758.7-166758.29" + process $proc$libresoc.v:166758$9266 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:165135.7-165135.30" - process $proc$libresoc.v:165135$9219 + attribute \src "libresoc.v:166767.7-166767.30" + process $proc$libresoc.v:166767$9267 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:165144.7-165144.27" - process $proc$libresoc.v:165144$9220 + attribute \src "libresoc.v:166776.7-166776.27" + process $proc$libresoc.v:166776$9268 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:165153.7-165153.27" - process $proc$libresoc.v:165153$9221 + attribute \src "libresoc.v:166785.7-166785.27" + process $proc$libresoc.v:166785$9269 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:165162.7-165162.33" - process $proc$libresoc.v:165162$9222 + attribute \src "libresoc.v:166794.7-166794.33" + process $proc$libresoc.v:166794$9270 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:165171.7-165171.30" - process $proc$libresoc.v:165171$9223 + attribute \src "libresoc.v:166803.7-166803.30" + process $proc$libresoc.v:166803$9271 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:165180.7-165180.27" - process $proc$libresoc.v:165180$9224 + attribute \src "libresoc.v:166812.7-166812.27" + process $proc$libresoc.v:166812$9272 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:165189.7-165189.27" - process $proc$libresoc.v:165189$9225 + attribute \src "libresoc.v:166821.7-166821.27" + process $proc$libresoc.v:166821$9273 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:165198.7-165198.30" - process $proc$libresoc.v:165198$9226 + attribute \src "libresoc.v:166830.7-166830.30" + process $proc$libresoc.v:166830$9274 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:165207.13-165207.26" - process $proc$libresoc.v:165207$9227 + attribute \src "libresoc.v:166839.13-166839.26" + process $proc$libresoc.v:166839$9275 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:165218.7-165218.23" - process $proc$libresoc.v:165218$9228 + attribute \src "libresoc.v:166850.7-166850.23" + process $proc$libresoc.v:166850$9276 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165227.7-165227.20" - process $proc$libresoc.v:165227$9229 + attribute \src "libresoc.v:166859.7-166859.20" + process $proc$libresoc.v:166859$9277 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:165236.7-165236.23" - process $proc$libresoc.v:165236$9230 + attribute \src "libresoc.v:166868.7-166868.23" + process $proc$libresoc.v:166868$9278 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:165244.3-165245.29" - process $proc$libresoc.v:165244$9104 + attribute \src "libresoc.v:166876.3-166877.29" + process $proc$libresoc.v:166876$9152 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:165246.3-165247.35" - process $proc$libresoc.v:165246$9105 + attribute \src "libresoc.v:166878.3-166879.35" + process $proc$libresoc.v:166878$9153 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165248.3-165249.29" - process $proc$libresoc.v:165248$9106 + attribute \src "libresoc.v:166880.3-166881.29" + process $proc$libresoc.v:166880$9154 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:165250.3-165251.35" - process $proc$libresoc.v:165250$9107 + attribute \src "libresoc.v:166882.3-166883.35" + process $proc$libresoc.v:166882$9155 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165252.3-165253.25" - process $proc$libresoc.v:165252$9108 + attribute \src "libresoc.v:166884.3-166885.25" + process $proc$libresoc.v:166884$9156 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:165254.3-165255.31" - process $proc$libresoc.v:165254$9109 + attribute \src "libresoc.v:166886.3-166887.31" + process $proc$libresoc.v:166886$9157 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:165256.3-165257.19" - process $proc$libresoc.v:165256$9110 + attribute \src "libresoc.v:166888.3-166889.19" + process $proc$libresoc.v:166888$9158 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165258.3-165259.25" - process $proc$libresoc.v:165258$9111 + attribute \src "libresoc.v:166890.3-166891.25" + process $proc$libresoc.v:166890$9159 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165260.3-165261.49" - process $proc$libresoc.v:165260$9112 + attribute \src "libresoc.v:166892.3-166893.49" + process $proc$libresoc.v:166892$9160 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:165262.3-165263.45" - process $proc$libresoc.v:165262$9113 + attribute \src "libresoc.v:166894.3-166895.45" + process $proc$libresoc.v:166894$9161 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:165264.3-165265.59" - process $proc$libresoc.v:165264$9114 + attribute \src "libresoc.v:166896.3-166897.59" + process $proc$libresoc.v:166896$9162 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165266.3-165267.55" - process $proc$libresoc.v:165266$9115 + attribute \src "libresoc.v:166898.3-166899.55" + process $proc$libresoc.v:166898$9163 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165268.3-165269.43" - process $proc$libresoc.v:165268$9116 + attribute \src "libresoc.v:166900.3-166901.43" + process $proc$libresoc.v:166900$9164 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:165270.3-165271.43" - process $proc$libresoc.v:165270$9117 + attribute \src "libresoc.v:166902.3-166903.43" + process $proc$libresoc.v:166902$9165 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:165272.3-165273.43" - process $proc$libresoc.v:165272$9118 + attribute \src "libresoc.v:166904.3-166905.43" + process $proc$libresoc.v:166904$9166 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:165274.3-165275.43" - process $proc$libresoc.v:165274$9119 + attribute \src "libresoc.v:166906.3-166907.43" + process $proc$libresoc.v:166906$9167 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:165276.3-165277.49" - process $proc$libresoc.v:165276$9120 + attribute \src "libresoc.v:166908.3-166909.49" + process $proc$libresoc.v:166908$9168 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:165278.3-165279.49" - process $proc$libresoc.v:165278$9121 + attribute \src "libresoc.v:166910.3-166911.49" + process $proc$libresoc.v:166910$9169 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:165280.3-165281.53" - process $proc$libresoc.v:165280$9122 + attribute \src "libresoc.v:166912.3-166913.53" + process $proc$libresoc.v:166912$9170 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:165282.3-165283.55" - process $proc$libresoc.v:165282$9123 + attribute \src "libresoc.v:166914.3-166915.55" + process $proc$libresoc.v:166914$9171 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:165284.3-165285.47" - process $proc$libresoc.v:165284$9124 + attribute \src "libresoc.v:166916.3-166917.47" + process $proc$libresoc.v:166916$9172 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:165286.3-165287.49" - process $proc$libresoc.v:165286$9125 + attribute \src "libresoc.v:166918.3-166919.49" + process $proc$libresoc.v:166918$9173 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:165288.3-165289.47" - process $proc$libresoc.v:165288$9126 + attribute \src "libresoc.v:166920.3-166921.47" + process $proc$libresoc.v:166920$9174 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:165290.3-165291.49" - process $proc$libresoc.v:165290$9127 + attribute \src "libresoc.v:166922.3-166923.49" + process $proc$libresoc.v:166922$9175 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:165292.3-165293.39" - process $proc$libresoc.v:165292$9128 + attribute \src "libresoc.v:166924.3-166925.39" + process $proc$libresoc.v:166924$9176 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:165294.3-165295.27" - process $proc$libresoc.v:165294$9129 + attribute \src "libresoc.v:166926.3-166927.27" + process $proc$libresoc.v:166926$9177 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:165296.3-165297.29" - process $proc$libresoc.v:165296$9130 + attribute \src "libresoc.v:166928.3-166929.29" + process $proc$libresoc.v:166928$9178 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165400.3-165418.6" - process $proc$libresoc.v:165400$9131 + attribute \src "libresoc.v:167032.3-167050.6" + process $proc$libresoc.v:167032$9179 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9133 $1\xer_ca$next[1:0]$9135 - assign $0\xer_ca_ok$next[0:0]$9132 $2\xer_ca_ok$next[0:0]$9136 - attribute \src "libresoc.v:165401.5-165401.29" + assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 + assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:167033.5-167033.29" switch \initial - attribute \src "libresoc.v:165401.9-165401.17" + attribute \src "libresoc.v:167033.9-167033.17" case 1'1 case end @@ -341911,38 +344408,38 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9134 $1\xer_ca$next[1:0]$9135 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\xer_ca_ok$next[0:0]$9134 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9135 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9182 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9183 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9136 1'0 + assign $2\xer_ca_ok$next[0:0]$9184 1'0 case - assign $2\xer_ca_ok$next[0:0]$9136 $1\xer_ca_ok$next[0:0]$9134 + assign $2\xer_ca_ok$next[0:0]$9184 $1\xer_ca_ok$next[0:0]$9182 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9132 - update \xer_ca$next $0\xer_ca$next[1:0]$9133 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 + update \xer_ca$next $0\xer_ca$next[1:0]$9181 end - attribute \src "libresoc.v:165419.3-165436.6" - process $proc$libresoc.v:165419$9137 + attribute \src "libresoc.v:167051.3-167068.6" + process $proc$libresoc.v:167051$9185 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9138 $2\r_busy$next[0:0]$9140 - attribute \src "libresoc.v:165420.5-165420.29" + assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:167052.5-167052.29" switch \initial - attribute \src "libresoc.v:165420.9-165420.17" + attribute \src "libresoc.v:167052.9-167052.17" case 1'1 case end @@ -341951,34 +344448,34 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9139 1'1 + assign $1\r_busy$next[0:0]$9187 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9139 1'0 + assign $1\r_busy$next[0:0]$9187 1'0 case - assign $1\r_busy$next[0:0]$9139 \r_busy + assign $1\r_busy$next[0:0]$9187 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9140 1'0 + assign $2\r_busy$next[0:0]$9188 1'0 case - assign $2\r_busy$next[0:0]$9140 $1\r_busy$next[0:0]$9139 + assign $2\r_busy$next[0:0]$9188 $1\r_busy$next[0:0]$9187 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9138 + update \r_busy$next $0\r_busy$next[0:0]$9186 end - attribute \src "libresoc.v:165437.3-165449.6" - process $proc$libresoc.v:165437$9141 + attribute \src "libresoc.v:167069.3-167081.6" + process $proc$libresoc.v:167069$9189 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9142 $1\muxid$next[1:0]$9143 - attribute \src "libresoc.v:165438.5-165438.29" + assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 + attribute \src "libresoc.v:167070.5-167070.29" switch \initial - attribute \src "libresoc.v:165438.9-165438.17" + attribute \src "libresoc.v:167070.9-167070.17" case 1'1 case end @@ -341987,19 +344484,19 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9143 \muxid$67 + assign $1\muxid$next[1:0]$9191 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9143 \muxid$67 + assign $1\muxid$next[1:0]$9191 \muxid$67 case - assign $1\muxid$next[1:0]$9143 \muxid + assign $1\muxid$next[1:0]$9191 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9142 + update \muxid$next $0\muxid$next[1:0]$9190 end - attribute \src "libresoc.v:165450.3-165490.6" - process $proc$libresoc.v:165450$9144 + attribute \src "libresoc.v:167082.3-167122.6" + process $proc$libresoc.v:167082$9192 assign { } { } assign { } { } assign { } { } @@ -342034,32 +344531,32 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[13:0]$9145 $1\sr_op__fn_unit$next[13:0]$9162 + assign $0\sr_op__fn_unit$next[13:0]$9193 $1\sr_op__fn_unit$next[13:0]$9210 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9148 $1\sr_op__input_carry$next[1:0]$9165 - assign $0\sr_op__input_cr$next[0:0]$9149 $1\sr_op__input_cr$next[0:0]$9166 - assign $0\sr_op__insn$next[31:0]$9150 $1\sr_op__insn$next[31:0]$9167 - assign $0\sr_op__insn_type$next[6:0]$9151 $1\sr_op__insn_type$next[6:0]$9168 - assign $0\sr_op__invert_in$next[0:0]$9152 $1\sr_op__invert_in$next[0:0]$9169 - assign $0\sr_op__is_32bit$next[0:0]$9153 $1\sr_op__is_32bit$next[0:0]$9170 - assign $0\sr_op__is_signed$next[0:0]$9154 $1\sr_op__is_signed$next[0:0]$9171 + assign $0\sr_op__input_carry$next[1:0]$9196 $1\sr_op__input_carry$next[1:0]$9213 + assign $0\sr_op__input_cr$next[0:0]$9197 $1\sr_op__input_cr$next[0:0]$9214 + assign $0\sr_op__insn$next[31:0]$9198 $1\sr_op__insn$next[31:0]$9215 + assign $0\sr_op__insn_type$next[6:0]$9199 $1\sr_op__insn_type$next[6:0]$9216 + assign $0\sr_op__invert_in$next[0:0]$9200 $1\sr_op__invert_in$next[0:0]$9217 + assign $0\sr_op__is_32bit$next[0:0]$9201 $1\sr_op__is_32bit$next[0:0]$9218 + assign $0\sr_op__is_signed$next[0:0]$9202 $1\sr_op__is_signed$next[0:0]$9219 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9157 $1\sr_op__output_carry$next[0:0]$9174 - assign $0\sr_op__output_cr$next[0:0]$9158 $1\sr_op__output_cr$next[0:0]$9175 + assign $0\sr_op__output_carry$next[0:0]$9205 $1\sr_op__output_carry$next[0:0]$9222 + assign $0\sr_op__output_cr$next[0:0]$9206 $1\sr_op__output_cr$next[0:0]$9223 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9161 $1\sr_op__write_cr0$next[0:0]$9178 - assign $0\sr_op__imm_data__data$next[63:0]$9146 $2\sr_op__imm_data__data$next[63:0]$9179 - assign $0\sr_op__imm_data__ok$next[0:0]$9147 $2\sr_op__imm_data__ok$next[0:0]$9180 - assign $0\sr_op__oe__oe$next[0:0]$9155 $2\sr_op__oe__oe$next[0:0]$9181 - assign $0\sr_op__oe__ok$next[0:0]$9156 $2\sr_op__oe__ok$next[0:0]$9182 - assign $0\sr_op__rc__ok$next[0:0]$9159 $2\sr_op__rc__ok$next[0:0]$9183 - assign $0\sr_op__rc__rc$next[0:0]$9160 $2\sr_op__rc__rc$next[0:0]$9184 - attribute \src "libresoc.v:165451.5-165451.29" + assign $0\sr_op__write_cr0$next[0:0]$9209 $1\sr_op__write_cr0$next[0:0]$9226 + assign $0\sr_op__imm_data__data$next[63:0]$9194 $2\sr_op__imm_data__data$next[63:0]$9227 + assign $0\sr_op__imm_data__ok$next[0:0]$9195 $2\sr_op__imm_data__ok$next[0:0]$9228 + assign $0\sr_op__oe__oe$next[0:0]$9203 $2\sr_op__oe__oe$next[0:0]$9229 + assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 + assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 + assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 + attribute \src "libresoc.v:167083.5-167083.29" switch \initial - attribute \src "libresoc.v:165451.9-165451.17" + attribute \src "libresoc.v:167083.9-167083.17" case 1'1 case end @@ -342084,7 +344581,7 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -342104,25 +344601,25 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9167 $1\sr_op__is_signed$next[0:0]$9171 $1\sr_op__is_32bit$next[0:0]$9170 $1\sr_op__output_cr$next[0:0]$9175 $1\sr_op__input_cr$next[0:0]$9166 $1\sr_op__output_carry$next[0:0]$9174 $1\sr_op__input_carry$next[1:0]$9165 $1\sr_op__invert_in$next[0:0]$9169 $1\sr_op__write_cr0$next[0:0]$9178 $1\sr_op__oe__ok$next[0:0]$9173 $1\sr_op__oe__oe$next[0:0]$9172 $1\sr_op__rc__ok$next[0:0]$9176 $1\sr_op__rc__rc$next[0:0]$9177 $1\sr_op__imm_data__ok$next[0:0]$9164 $1\sr_op__imm_data__data$next[63:0]$9163 $1\sr_op__fn_unit$next[13:0]$9162 $1\sr_op__insn_type$next[6:0]$9168 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\sr_op__fn_unit$next[13:0]$9162 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9163 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9164 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9165 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9166 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9167 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9168 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9169 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9170 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9171 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9172 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9173 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9174 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9175 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9176 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9177 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9178 \sr_op__write_cr0 + assign $1\sr_op__fn_unit$next[13:0]$9210 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9211 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9212 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9213 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9214 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9215 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9216 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9217 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9218 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9219 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9220 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9221 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9222 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9223 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9224 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9225 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9226 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -342134,51 +344631,51 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9179 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9180 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9184 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9183 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9181 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9182 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9227 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9232 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9231 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9229 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9230 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9179 $1\sr_op__imm_data__data$next[63:0]$9163 - assign $2\sr_op__imm_data__ok$next[0:0]$9180 $1\sr_op__imm_data__ok$next[0:0]$9164 - assign $2\sr_op__oe__oe$next[0:0]$9181 $1\sr_op__oe__oe$next[0:0]$9172 - assign $2\sr_op__oe__ok$next[0:0]$9182 $1\sr_op__oe__ok$next[0:0]$9173 - assign $2\sr_op__rc__ok$next[0:0]$9183 $1\sr_op__rc__ok$next[0:0]$9176 - assign $2\sr_op__rc__rc$next[0:0]$9184 $1\sr_op__rc__rc$next[0:0]$9177 + assign $2\sr_op__imm_data__data$next[63:0]$9227 $1\sr_op__imm_data__data$next[63:0]$9211 + assign $2\sr_op__imm_data__ok$next[0:0]$9228 $1\sr_op__imm_data__ok$next[0:0]$9212 + assign $2\sr_op__oe__oe$next[0:0]$9229 $1\sr_op__oe__oe$next[0:0]$9220 + assign $2\sr_op__oe__ok$next[0:0]$9230 $1\sr_op__oe__ok$next[0:0]$9221 + assign $2\sr_op__rc__ok$next[0:0]$9231 $1\sr_op__rc__ok$next[0:0]$9224 + assign $2\sr_op__rc__rc$next[0:0]$9232 $1\sr_op__rc__rc$next[0:0]$9225 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9145 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9146 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9147 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9148 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9149 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9150 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9151 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9152 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9153 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9154 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9155 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9156 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9157 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9158 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9159 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9160 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9161 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9193 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9194 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9195 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9196 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9197 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9198 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9199 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9200 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9201 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9202 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9203 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9204 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9205 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9206 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9207 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 end - attribute \src "libresoc.v:165491.3-165509.6" - process $proc$libresoc.v:165491$9185 + attribute \src "libresoc.v:167123.3-167141.6" + process $proc$libresoc.v:167123$9233 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9186 $1\o$next[63:0]$9188 + assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 assign { } { } - assign $0\o_ok$next[0:0]$9187 $2\o_ok$next[0:0]$9190 - attribute \src "libresoc.v:165492.5-165492.29" + assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 + attribute \src "libresoc.v:167124.5-167124.29" switch \initial - attribute \src "libresoc.v:165492.9-165492.17" + attribute \src "libresoc.v:167124.9-167124.17" case 1'1 case end @@ -342188,41 +344685,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9189 $1\o$next[63:0]$9188 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$9188 \o - assign $1\o_ok$next[0:0]$9189 \o_ok + assign $1\o$next[63:0]$9236 \o + assign $1\o_ok$next[0:0]$9237 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9190 1'0 + assign $2\o_ok$next[0:0]$9238 1'0 case - assign $2\o_ok$next[0:0]$9190 $1\o_ok$next[0:0]$9189 + assign $2\o_ok$next[0:0]$9238 $1\o_ok$next[0:0]$9237 end sync always - update \o$next $0\o$next[63:0]$9186 - update \o_ok$next $0\o_ok$next[0:0]$9187 + update \o$next $0\o$next[63:0]$9234 + update \o_ok$next $0\o_ok$next[0:0]$9235 end - attribute \src "libresoc.v:165510.3-165528.6" - process $proc$libresoc.v:165510$9191 + attribute \src "libresoc.v:167142.3-167160.6" + process $proc$libresoc.v:167142$9239 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9192 $1\cr_a$next[3:0]$9194 + assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 assign { } { } - assign $0\cr_a_ok$next[0:0]$9193 $2\cr_a_ok$next[0:0]$9196 - attribute \src "libresoc.v:165511.5-165511.29" + assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 + attribute \src "libresoc.v:167143.5-167143.29" switch \initial - attribute \src "libresoc.v:165511.9-165511.17" + attribute \src "libresoc.v:167143.9-167143.17" case 1'1 case end @@ -342232,41 +344729,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9195 $1\cr_a$next[3:0]$9194 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$9194 \cr_a - assign $1\cr_a_ok$next[0:0]$9195 \cr_a_ok + assign $1\cr_a$next[3:0]$9242 \cr_a + assign $1\cr_a_ok$next[0:0]$9243 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9196 1'0 + assign $2\cr_a_ok$next[0:0]$9244 1'0 case - assign $2\cr_a_ok$next[0:0]$9196 $1\cr_a_ok$next[0:0]$9195 + assign $2\cr_a_ok$next[0:0]$9244 $1\cr_a_ok$next[0:0]$9243 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9192 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9193 + update \cr_a$next $0\cr_a$next[3:0]$9240 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 end - attribute \src "libresoc.v:165529.3-165547.6" - process $proc$libresoc.v:165529$9197 + attribute \src "libresoc.v:167161.3-167179.6" + process $proc$libresoc.v:167161$9245 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9198 $1\xer_so$next[0:0]$9200 + assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 assign { } { } - assign $0\xer_so_ok$next[0:0]$9199 $2\xer_so_ok$next[0:0]$9202 - attribute \src "libresoc.v:165530.5-165530.29" + assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 + attribute \src "libresoc.v:167162.5-167162.29" switch \initial - attribute \src "libresoc.v:165530.9-165530.17" + attribute \src "libresoc.v:167162.9-167162.17" case 1'1 case end @@ -342276,30 +344773,30 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9201 $1\xer_so$next[0:0]$9200 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$9200 \xer_so - assign $1\xer_so_ok$next[0:0]$9201 \xer_so_ok + assign $1\xer_so$next[0:0]$9248 \xer_so + assign $1\xer_so_ok$next[0:0]$9249 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9202 1'0 + assign $2\xer_so_ok$next[0:0]$9250 1'0 case - assign $2\xer_so_ok$next[0:0]$9202 $1\xer_so_ok$next[0:0]$9201 + assign $2\xer_so_ok$next[0:0]$9250 $1\xer_so_ok$next[0:0]$9249 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9198 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9199 + update \xer_so$next $0\xer_so$next[0:0]$9246 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 end - connect \$65 $and$libresoc.v:165243$9103_Y + connect \$65 $and$libresoc.v:166875$9151_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -342330,142 +344827,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165581.1-166429.10" +attribute \src "libresoc.v:167213.1-168061.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:166386.3-166398.6" - wire width 64 $0\fast1$next[63:0]$9280 - attribute \src "libresoc.v:166242.3-166243.27" + attribute \src "libresoc.v:168018.3-168030.6" + wire width 64 $0\fast1$next[63:0]$9328 + attribute \src "libresoc.v:167874.3-167875.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:166399.3-166411.6" - wire width 64 $0\fast2$next[63:0]$9283 - attribute \src "libresoc.v:166240.3-166241.27" + attribute \src "libresoc.v:168031.3-168043.6" + wire width 64 $0\fast2$next[63:0]$9331 + attribute \src "libresoc.v:167872.3-167873.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:165582.7-165582.20" + attribute \src "libresoc.v:167214.7-167214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166326.3-166338.6" - wire width 2 $0\muxid$next[1:0]$9252 - attribute \src "libresoc.v:166266.3-166267.27" + attribute \src "libresoc.v:167958.3-167970.6" + wire width 2 $0\muxid$next[1:0]$9300 + attribute \src "libresoc.v:167898.3-167899.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $0\r_busy$next[0:0]$9248 - attribute \src "libresoc.v:166268.3-166269.29" + attribute \src "libresoc.v:167940.3-167957.6" + wire $0\r_busy$next[0:0]$9296 + attribute \src "libresoc.v:167900.3-167901.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:166360.3-166372.6" - wire width 64 $0\ra$next[63:0]$9274 - attribute \src "libresoc.v:166246.3-166247.21" + attribute \src "libresoc.v:167992.3-168004.6" + wire width 64 $0\ra$next[63:0]$9322 + attribute \src "libresoc.v:167878.3-167879.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:166373.3-166385.6" - wire width 64 $0\rb$next[63:0]$9277 - attribute \src "libresoc.v:166244.3-166245.21" + attribute \src "libresoc.v:168005.3-168017.6" + wire width 64 $0\rb$next[63:0]$9325 + attribute \src "libresoc.v:167876.3-167877.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $0\trap_op__cia$next[63:0]$9255 - attribute \src "libresoc.v:166256.3-166257.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $0\trap_op__cia$next[63:0]$9303 + attribute \src "libresoc.v:167888.3-167889.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 14 $0\trap_op__fn_unit$next[13:0]$9256 - attribute \src "libresoc.v:166250.3-166251.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 + attribute \src "libresoc.v:167882.3-167883.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 32 $0\trap_op__insn$next[31:0]$9257 - attribute \src "libresoc.v:166252.3-166253.43" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 32 $0\trap_op__insn$next[31:0]$9305 + attribute \src "libresoc.v:167884.3-167885.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9258 - attribute \src "libresoc.v:166248.3-166249.53" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9306 + attribute \src "libresoc.v:167880.3-167881.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire $0\trap_op__is_32bit$next[0:0]$9259 - attribute \src "libresoc.v:166258.3-166259.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire $0\trap_op__is_32bit$next[0:0]$9307 + attribute \src "libresoc.v:167890.3-167891.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9260 - attribute \src "libresoc.v:166264.3-166265.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 + attribute \src "libresoc.v:167896.3-167897.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $0\trap_op__msr$next[63:0]$9261 - attribute \src "libresoc.v:166254.3-166255.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $0\trap_op__msr$next[63:0]$9309 + attribute \src "libresoc.v:167886.3-167887.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9262 - attribute \src "libresoc.v:166262.3-166263.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9310 + attribute \src "libresoc.v:167894.3-167895.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9263 - attribute \src "libresoc.v:166260.3-166261.51" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9311 + attribute \src "libresoc.v:167892.3-167893.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:166386.3-166398.6" - wire width 64 $1\fast1$next[63:0]$9281 - attribute \src "libresoc.v:165827.14-165827.42" + attribute \src "libresoc.v:168018.3-168030.6" + wire width 64 $1\fast1$next[63:0]$9329 + attribute \src "libresoc.v:167459.14-167459.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:166399.3-166411.6" - wire width 64 $1\fast2$next[63:0]$9284 - attribute \src "libresoc.v:165836.14-165836.42" + attribute \src "libresoc.v:168031.3-168043.6" + wire width 64 $1\fast2$next[63:0]$9332 + attribute \src "libresoc.v:167468.14-167468.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:166326.3-166338.6" - wire width 2 $1\muxid$next[1:0]$9253 - attribute \src "libresoc.v:165845.13-165845.25" + attribute \src "libresoc.v:167958.3-167970.6" + wire width 2 $1\muxid$next[1:0]$9301 + attribute \src "libresoc.v:167477.13-167477.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $1\r_busy$next[0:0]$9249 - attribute \src "libresoc.v:165867.7-165867.20" + attribute \src "libresoc.v:167940.3-167957.6" + wire $1\r_busy$next[0:0]$9297 + attribute \src "libresoc.v:167499.7-167499.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:166360.3-166372.6" - wire width 64 $1\ra$next[63:0]$9275 - attribute \src "libresoc.v:165872.14-165872.39" + attribute \src "libresoc.v:167992.3-168004.6" + wire width 64 $1\ra$next[63:0]$9323 + attribute \src "libresoc.v:167504.14-167504.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:166373.3-166385.6" - wire width 64 $1\rb$next[63:0]$9278 - attribute \src "libresoc.v:165881.14-165881.39" + attribute \src "libresoc.v:168005.3-168017.6" + wire width 64 $1\rb$next[63:0]$9326 + attribute \src "libresoc.v:167513.14-167513.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $1\trap_op__cia$next[63:0]$9264 - attribute \src "libresoc.v:165890.14-165890.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $1\trap_op__cia$next[63:0]$9312 + attribute \src "libresoc.v:167522.14-167522.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 14 $1\trap_op__fn_unit$next[13:0]$9265 - attribute \src "libresoc.v:165914.14-165914.41" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 14 $1\trap_op__fn_unit$next[13:0]$9313 + attribute \src "libresoc.v:167546.14-167546.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 32 $1\trap_op__insn$next[31:0]$9266 - attribute \src "libresoc.v:165953.14-165953.35" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 32 $1\trap_op__insn$next[31:0]$9314 + attribute \src "libresoc.v:167585.14-167585.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9267 - attribute \src "libresoc.v:166037.13-166037.39" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9315 + attribute \src "libresoc.v:167669.13-167669.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire $1\trap_op__is_32bit$next[0:0]$9268 - attribute \src "libresoc.v:166196.7-166196.31" + attribute \src "libresoc.v:167971.3-167991.6" + wire $1\trap_op__is_32bit$next[0:0]$9316 + attribute \src "libresoc.v:167828.7-167828.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9269 - attribute \src "libresoc.v:166205.13-166205.38" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9317 + attribute \src "libresoc.v:167837.13-167837.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 64 $1\trap_op__msr$next[63:0]$9270 - attribute \src "libresoc.v:166214.14-166214.49" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 64 $1\trap_op__msr$next[63:0]$9318 + attribute \src "libresoc.v:167846.14-167846.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9271 - attribute \src "libresoc.v:166223.14-166223.42" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9319 + attribute \src "libresoc.v:167855.14-167855.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:166339.3-166359.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9272 - attribute \src "libresoc.v:166232.13-166232.38" + attribute \src "libresoc.v:167971.3-167991.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9320 + attribute \src "libresoc.v:167864.13-167864.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:166308.3-166325.6" - wire $2\r_busy$next[0:0]$9250 - attribute \src "libresoc.v:166239.18-166239.118" - wire $and$libresoc.v:166239$9231_Y + attribute \src "libresoc.v:167940.3-167957.6" + wire $2\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:167871.18-167871.118" + wire $and$libresoc.v:167871$9279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -342719,7 +345216,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:165582.7-165582.15" + attribute \src "libresoc.v:167214.7-167214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -343106,7 +345603,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166239$9231 + cell $and $and$libresoc.v:167871$9279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -343114,10 +345611,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:166239$9231_Y + connect \Y $and$libresoc.v:167871$9279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166270.9-166299.4" + attribute \src "libresoc.v:167902.9-167931.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -343149,259 +345646,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166300.10-166303.4" + attribute \src "libresoc.v:167932.10-167935.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:166304.10-166307.4" + attribute \src "libresoc.v:167936.10-167939.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165582.7-165582.20" - process $proc$libresoc.v:165582$9285 + attribute \src "libresoc.v:167214.7-167214.20" + process $proc$libresoc.v:167214$9333 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165827.14-165827.42" - process $proc$libresoc.v:165827$9286 + attribute \src "libresoc.v:167459.14-167459.42" + process $proc$libresoc.v:167459$9334 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:165836.14-165836.42" - process $proc$libresoc.v:165836$9287 + attribute \src "libresoc.v:167468.14-167468.42" + process $proc$libresoc.v:167468$9335 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:165845.13-165845.25" - process $proc$libresoc.v:165845$9288 + attribute \src "libresoc.v:167477.13-167477.25" + process $proc$libresoc.v:167477$9336 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:165867.7-165867.20" - process $proc$libresoc.v:165867$9289 + attribute \src "libresoc.v:167499.7-167499.20" + process $proc$libresoc.v:167499$9337 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165872.14-165872.39" - process $proc$libresoc.v:165872$9290 + attribute \src "libresoc.v:167504.14-167504.39" + process $proc$libresoc.v:167504$9338 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:165881.14-165881.39" - process $proc$libresoc.v:165881$9291 + attribute \src "libresoc.v:167513.14-167513.39" + process $proc$libresoc.v:167513$9339 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:165890.14-165890.49" - process $proc$libresoc.v:165890$9292 + attribute \src "libresoc.v:167522.14-167522.49" + process $proc$libresoc.v:167522$9340 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:165914.14-165914.41" - process $proc$libresoc.v:165914$9293 + attribute \src "libresoc.v:167546.14-167546.41" + process $proc$libresoc.v:167546$9341 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:165953.14-165953.35" - process $proc$libresoc.v:165953$9294 + attribute \src "libresoc.v:167585.14-167585.35" + process $proc$libresoc.v:167585$9342 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:166037.13-166037.39" - process $proc$libresoc.v:166037$9295 + attribute \src "libresoc.v:167669.13-167669.39" + process $proc$libresoc.v:167669$9343 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:166196.7-166196.31" - process $proc$libresoc.v:166196$9296 + attribute \src "libresoc.v:167828.7-167828.31" + process $proc$libresoc.v:167828$9344 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:166205.13-166205.38" - process $proc$libresoc.v:166205$9297 + attribute \src "libresoc.v:167837.13-167837.38" + process $proc$libresoc.v:167837$9345 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:166214.14-166214.49" - process $proc$libresoc.v:166214$9298 + attribute \src "libresoc.v:167846.14-167846.49" + process $proc$libresoc.v:167846$9346 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:166223.14-166223.42" - process $proc$libresoc.v:166223$9299 + attribute \src "libresoc.v:167855.14-167855.42" + process $proc$libresoc.v:167855$9347 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:166232.13-166232.38" - process $proc$libresoc.v:166232$9300 + attribute \src "libresoc.v:167864.13-167864.38" + process $proc$libresoc.v:167864$9348 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:166240.3-166241.27" - process $proc$libresoc.v:166240$9232 + attribute \src "libresoc.v:167872.3-167873.27" + process $proc$libresoc.v:167872$9280 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:166242.3-166243.27" - process $proc$libresoc.v:166242$9233 + attribute \src "libresoc.v:167874.3-167875.27" + process $proc$libresoc.v:167874$9281 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:166244.3-166245.21" - process $proc$libresoc.v:166244$9234 + attribute \src "libresoc.v:167876.3-167877.21" + process $proc$libresoc.v:167876$9282 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:166246.3-166247.21" - process $proc$libresoc.v:166246$9235 + attribute \src "libresoc.v:167878.3-167879.21" + process $proc$libresoc.v:167878$9283 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:166248.3-166249.53" - process $proc$libresoc.v:166248$9236 + attribute \src "libresoc.v:167880.3-167881.53" + process $proc$libresoc.v:167880$9284 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:166250.3-166251.49" - process $proc$libresoc.v:166250$9237 + attribute \src "libresoc.v:167882.3-167883.49" + process $proc$libresoc.v:167882$9285 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:166252.3-166253.43" - process $proc$libresoc.v:166252$9238 + attribute \src "libresoc.v:167884.3-167885.43" + process $proc$libresoc.v:167884$9286 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:166254.3-166255.41" - process $proc$libresoc.v:166254$9239 + attribute \src "libresoc.v:167886.3-167887.41" + process $proc$libresoc.v:167886$9287 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:166256.3-166257.41" - process $proc$libresoc.v:166256$9240 + attribute \src "libresoc.v:167888.3-167889.41" + process $proc$libresoc.v:167888$9288 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:166258.3-166259.51" - process $proc$libresoc.v:166258$9241 + attribute \src "libresoc.v:167890.3-167891.51" + process $proc$libresoc.v:167890$9289 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:166260.3-166261.51" - process $proc$libresoc.v:166260$9242 + attribute \src "libresoc.v:167892.3-167893.51" + process $proc$libresoc.v:167892$9290 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:166262.3-166263.51" - process $proc$libresoc.v:166262$9243 + attribute \src "libresoc.v:167894.3-167895.51" + process $proc$libresoc.v:167894$9291 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:166264.3-166265.51" - process $proc$libresoc.v:166264$9244 + attribute \src "libresoc.v:167896.3-167897.51" + process $proc$libresoc.v:167896$9292 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:166266.3-166267.27" - process $proc$libresoc.v:166266$9245 + attribute \src "libresoc.v:167898.3-167899.27" + process $proc$libresoc.v:167898$9293 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166268.3-166269.29" - process $proc$libresoc.v:166268$9246 + attribute \src "libresoc.v:167900.3-167901.29" + process $proc$libresoc.v:167900$9294 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:166308.3-166325.6" - process $proc$libresoc.v:166308$9247 + attribute \src "libresoc.v:167940.3-167957.6" + process $proc$libresoc.v:167940$9295 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9248 $2\r_busy$next[0:0]$9250 - attribute \src "libresoc.v:166309.5-166309.29" + assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:167941.5-167941.29" switch \initial - attribute \src "libresoc.v:166309.9-166309.17" + attribute \src "libresoc.v:167941.9-167941.17" case 1'1 case end @@ -343410,34 +345907,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9249 1'1 + assign $1\r_busy$next[0:0]$9297 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9249 1'0 + assign $1\r_busy$next[0:0]$9297 1'0 case - assign $1\r_busy$next[0:0]$9249 \r_busy + assign $1\r_busy$next[0:0]$9297 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9250 1'0 + assign $2\r_busy$next[0:0]$9298 1'0 case - assign $2\r_busy$next[0:0]$9250 $1\r_busy$next[0:0]$9249 + assign $2\r_busy$next[0:0]$9298 $1\r_busy$next[0:0]$9297 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9248 + update \r_busy$next $0\r_busy$next[0:0]$9296 end - attribute \src "libresoc.v:166326.3-166338.6" - process $proc$libresoc.v:166326$9251 + attribute \src "libresoc.v:167958.3-167970.6" + process $proc$libresoc.v:167958$9299 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9252 $1\muxid$next[1:0]$9253 - attribute \src "libresoc.v:166327.5-166327.29" + assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 + attribute \src "libresoc.v:167959.5-167959.29" switch \initial - attribute \src "libresoc.v:166327.9-166327.17" + attribute \src "libresoc.v:167959.9-167959.17" case 1'1 case end @@ -343446,19 +345943,19 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9253 \muxid$32 + assign $1\muxid$next[1:0]$9301 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9253 \muxid$32 + assign $1\muxid$next[1:0]$9301 \muxid$32 case - assign $1\muxid$next[1:0]$9253 \muxid + assign $1\muxid$next[1:0]$9301 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9252 + update \muxid$next $0\muxid$next[1:0]$9300 end - attribute \src "libresoc.v:166339.3-166359.6" - process $proc$libresoc.v:166339$9254 + attribute \src "libresoc.v:167971.3-167991.6" + process $proc$libresoc.v:167971$9302 assign { } { } assign { } { } assign { } { } @@ -343477,18 +345974,18 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9255 $1\trap_op__cia$next[63:0]$9264 - assign $0\trap_op__fn_unit$next[13:0]$9256 $1\trap_op__fn_unit$next[13:0]$9265 - assign $0\trap_op__insn$next[31:0]$9257 $1\trap_op__insn$next[31:0]$9266 - assign $0\trap_op__insn_type$next[6:0]$9258 $1\trap_op__insn_type$next[6:0]$9267 - assign $0\trap_op__is_32bit$next[0:0]$9259 $1\trap_op__is_32bit$next[0:0]$9268 - assign $0\trap_op__ldst_exc$next[7:0]$9260 $1\trap_op__ldst_exc$next[7:0]$9269 - assign $0\trap_op__msr$next[63:0]$9261 $1\trap_op__msr$next[63:0]$9270 - assign $0\trap_op__trapaddr$next[12:0]$9262 $1\trap_op__trapaddr$next[12:0]$9271 - assign $0\trap_op__traptype$next[7:0]$9263 $1\trap_op__traptype$next[7:0]$9272 - attribute \src "libresoc.v:166340.5-166340.29" + assign $0\trap_op__cia$next[63:0]$9303 $1\trap_op__cia$next[63:0]$9312 + assign $0\trap_op__fn_unit$next[13:0]$9304 $1\trap_op__fn_unit$next[13:0]$9313 + assign $0\trap_op__insn$next[31:0]$9305 $1\trap_op__insn$next[31:0]$9314 + assign $0\trap_op__insn_type$next[6:0]$9306 $1\trap_op__insn_type$next[6:0]$9315 + assign $0\trap_op__is_32bit$next[0:0]$9307 $1\trap_op__is_32bit$next[0:0]$9316 + assign $0\trap_op__ldst_exc$next[7:0]$9308 $1\trap_op__ldst_exc$next[7:0]$9317 + assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 + assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 + assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 + attribute \src "libresoc.v:167972.5-167972.29" switch \initial - attribute \src "libresoc.v:166340.9-166340.17" + attribute \src "libresoc.v:167972.9-167972.17" case 1'1 case end @@ -343505,7 +346002,7 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -343517,37 +346014,37 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9269 $1\trap_op__trapaddr$next[12:0]$9271 $1\trap_op__traptype$next[7:0]$9272 $1\trap_op__is_32bit$next[0:0]$9268 $1\trap_op__cia$next[63:0]$9264 $1\trap_op__msr$next[63:0]$9270 $1\trap_op__insn$next[31:0]$9266 $1\trap_op__fn_unit$next[13:0]$9265 $1\trap_op__insn_type$next[6:0]$9267 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\trap_op__cia$next[63:0]$9264 \trap_op__cia - assign $1\trap_op__fn_unit$next[13:0]$9265 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9266 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9267 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9268 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9269 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9270 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9271 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9272 \trap_op__traptype + assign $1\trap_op__cia$next[63:0]$9312 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9313 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9314 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9315 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9316 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9317 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9318 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9319 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9320 \trap_op__traptype end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9255 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9256 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9257 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9258 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9259 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9260 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9261 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9262 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9263 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9303 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9304 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9305 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9306 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9307 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9308 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9309 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 end - attribute \src "libresoc.v:166360.3-166372.6" - process $proc$libresoc.v:166360$9273 + attribute \src "libresoc.v:167992.3-168004.6" + process $proc$libresoc.v:167992$9321 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9274 $1\ra$next[63:0]$9275 - attribute \src "libresoc.v:166361.5-166361.29" + assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 + attribute \src "libresoc.v:167993.5-167993.29" switch \initial - attribute \src "libresoc.v:166361.9-166361.17" + attribute \src "libresoc.v:167993.9-167993.17" case 1'1 case end @@ -343556,25 +346053,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9275 \ra$42 + assign $1\ra$next[63:0]$9323 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9275 \ra$42 + assign $1\ra$next[63:0]$9323 \ra$42 case - assign $1\ra$next[63:0]$9275 \ra + assign $1\ra$next[63:0]$9323 \ra end sync always - update \ra$next $0\ra$next[63:0]$9274 + update \ra$next $0\ra$next[63:0]$9322 end - attribute \src "libresoc.v:166373.3-166385.6" - process $proc$libresoc.v:166373$9276 + attribute \src "libresoc.v:168005.3-168017.6" + process $proc$libresoc.v:168005$9324 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9277 $1\rb$next[63:0]$9278 - attribute \src "libresoc.v:166374.5-166374.29" + assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 + attribute \src "libresoc.v:168006.5-168006.29" switch \initial - attribute \src "libresoc.v:166374.9-166374.17" + attribute \src "libresoc.v:168006.9-168006.17" case 1'1 case end @@ -343583,25 +346080,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9278 \rb$43 + assign $1\rb$next[63:0]$9326 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9278 \rb$43 + assign $1\rb$next[63:0]$9326 \rb$43 case - assign $1\rb$next[63:0]$9278 \rb + assign $1\rb$next[63:0]$9326 \rb end sync always - update \rb$next $0\rb$next[63:0]$9277 + update \rb$next $0\rb$next[63:0]$9325 end - attribute \src "libresoc.v:166386.3-166398.6" - process $proc$libresoc.v:166386$9279 + attribute \src "libresoc.v:168018.3-168030.6" + process $proc$libresoc.v:168018$9327 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9280 $1\fast1$next[63:0]$9281 - attribute \src "libresoc.v:166387.5-166387.29" + assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 + attribute \src "libresoc.v:168019.5-168019.29" switch \initial - attribute \src "libresoc.v:166387.9-166387.17" + attribute \src "libresoc.v:168019.9-168019.17" case 1'1 case end @@ -343610,25 +346107,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9281 \fast1$44 + assign $1\fast1$next[63:0]$9329 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9281 \fast1$44 + assign $1\fast1$next[63:0]$9329 \fast1$44 case - assign $1\fast1$next[63:0]$9281 \fast1 + assign $1\fast1$next[63:0]$9329 \fast1 end sync always - update \fast1$next $0\fast1$next[63:0]$9280 + update \fast1$next $0\fast1$next[63:0]$9328 end - attribute \src "libresoc.v:166399.3-166411.6" - process $proc$libresoc.v:166399$9282 + attribute \src "libresoc.v:168031.3-168043.6" + process $proc$libresoc.v:168031$9330 assign { } { } assign { } { } - assign $0\fast2$next[63:0]$9283 $1\fast2$next[63:0]$9284 - attribute \src "libresoc.v:166400.5-166400.29" + assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 + attribute \src "libresoc.v:168032.5-168032.29" switch \initial - attribute \src "libresoc.v:166400.9-166400.17" + attribute \src "libresoc.v:168032.9-168032.17" case 1'1 case end @@ -343637,18 +346134,18 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$9284 \fast2$45 + assign $1\fast2$next[63:0]$9332 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$9284 \fast2$45 + assign $1\fast2$next[63:0]$9332 \fast2$45 case - assign $1\fast2$next[63:0]$9284 \fast2 + assign $1\fast2$next[63:0]$9332 \fast2 end sync always - update \fast2$next $0\fast2$next[63:0]$9283 + update \fast2$next $0\fast2$next[63:0]$9331 end - connect \$30 $and$libresoc.v:166239$9231_Y + connect \$30 $and$libresoc.v:167871$9279_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -343667,279 +346164,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:166433.1-167618.10" +attribute \src "libresoc.v:168065.1-169250.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9369 - attribute \src "libresoc.v:167359.3-167360.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9355 - attribute \src "libresoc.v:166441.13-166441.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9443 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9370 - attribute \src "libresoc.v:167329.3-167330.53" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9325 - attribute \src "libresoc.v:166480.14-166480.44" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9445 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9371 - attribute \src "libresoc.v:167331.3-167332.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9327 - attribute \src "libresoc.v:166504.14-166504.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9447 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9372 - attribute \src "libresoc.v:167333.3-167334.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9329 - attribute \src "libresoc.v:166513.7-166513.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9449 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9373 - attribute \src "libresoc.v:167351.3-167352.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9347 - attribute \src "libresoc.v:166530.13-166530.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9451 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9374 - attribute \src "libresoc.v:167361.3-167362.49" - wire width 32 $0\alu_op__insn$19[31:0]$9357 - attribute \src "libresoc.v:166543.14-166543.39" - wire width 32 $0\alu_op__insn$19[31:0]$9453 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9375 - attribute \src "libresoc.v:167327.3-167328.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9323 - attribute \src "libresoc.v:166702.13-166702.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9455 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__invert_in$10$next[0:0]$9376 - attribute \src "libresoc.v:167343.3-167344.59" - wire $0\alu_op__invert_in$10[0:0]$9339 - attribute \src "libresoc.v:166786.7-166786.36" - wire $0\alu_op__invert_in$10[0:0]$9457 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__invert_out$12$next[0:0]$9377 - attribute \src "libresoc.v:167347.3-167348.61" - wire $0\alu_op__invert_out$12[0:0]$9343 - attribute \src "libresoc.v:166795.7-166795.37" - wire $0\alu_op__invert_out$12[0:0]$9459 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9378 - attribute \src "libresoc.v:167355.3-167356.57" - wire $0\alu_op__is_32bit$16[0:0]$9351 - attribute \src "libresoc.v:166804.7-166804.35" - wire $0\alu_op__is_32bit$16[0:0]$9461 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__is_signed$17$next[0:0]$9379 - attribute \src "libresoc.v:167357.3-167358.59" - wire $0\alu_op__is_signed$17[0:0]$9353 - attribute \src "libresoc.v:166813.7-166813.36" - wire $0\alu_op__is_signed$17[0:0]$9463 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9380 - attribute \src "libresoc.v:167339.3-167340.51" - wire $0\alu_op__oe__oe$8[0:0]$9335 - attribute \src "libresoc.v:166824.7-166824.32" - wire $0\alu_op__oe__oe$8[0:0]$9465 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9381 - attribute \src "libresoc.v:167341.3-167342.51" - wire $0\alu_op__oe__ok$9[0:0]$9337 - attribute \src "libresoc.v:166833.7-166833.32" - wire $0\alu_op__oe__ok$9[0:0]$9467 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__output_carry$15$next[0:0]$9382 - attribute \src "libresoc.v:167353.3-167354.65" - wire $0\alu_op__output_carry$15[0:0]$9349 - attribute \src "libresoc.v:166840.7-166840.39" - wire $0\alu_op__output_carry$15[0:0]$9469 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9383 - attribute \src "libresoc.v:167337.3-167338.51" - wire $0\alu_op__rc__ok$7[0:0]$9333 - attribute \src "libresoc.v:166851.7-166851.32" - wire $0\alu_op__rc__ok$7[0:0]$9471 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9384 - attribute \src "libresoc.v:167335.3-167336.51" - wire $0\alu_op__rc__rc$6[0:0]$9331 - attribute \src "libresoc.v:166858.7-166858.32" - wire $0\alu_op__rc__rc$6[0:0]$9473 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9385 - attribute \src "libresoc.v:167349.3-167350.59" - wire $0\alu_op__write_cr0$13[0:0]$9345 - attribute \src "libresoc.v:166867.7-166867.36" - wire $0\alu_op__write_cr0$13[0:0]$9475 - attribute \src "libresoc.v:167462.3-167503.6" - wire $0\alu_op__zero_a$11$next[0:0]$9386 - attribute \src "libresoc.v:167345.3-167346.53" - wire $0\alu_op__zero_a$11[0:0]$9341 - attribute \src "libresoc.v:166876.7-166876.33" - wire $0\alu_op__zero_a$11[0:0]$9477 - attribute \src "libresoc.v:167523.3-167541.6" - wire width 4 $0\cr_a$22$next[3:0]$9418 - attribute \src "libresoc.v:167319.3-167320.33" - wire width 4 $0\cr_a$22[3:0]$9315 - attribute \src "libresoc.v:166889.13-166889.29" - wire width 4 $0\cr_a$22[3:0]$9479 - attribute \src "libresoc.v:167523.3-167541.6" - wire $0\cr_a_ok$23$next[0:0]$9419 - attribute \src "libresoc.v:167321.3-167322.39" - wire $0\cr_a_ok$23[0:0]$9317 - attribute \src "libresoc.v:166898.7-166898.26" - wire $0\cr_a_ok$23[0:0]$9481 - attribute \src "libresoc.v:166434.7-166434.20" + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 + attribute \src "libresoc.v:168991.3-168992.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9403 + attribute \src "libresoc.v:168073.13-168073.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9491 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 + attribute \src "libresoc.v:168961.3-168962.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 + attribute \src "libresoc.v:168112.14-168112.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 + attribute \src "libresoc.v:168963.3-168964.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 + attribute \src "libresoc.v:168136.14-168136.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 + attribute \src "libresoc.v:168965.3-168966.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9377 + attribute \src "libresoc.v:168145.7-168145.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9497 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 + attribute \src "libresoc.v:168983.3-168984.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9395 + attribute \src "libresoc.v:168162.13-168162.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9499 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9422 + attribute \src "libresoc.v:168993.3-168994.49" + wire width 32 $0\alu_op__insn$19[31:0]$9405 + attribute \src "libresoc.v:168175.14-168175.39" + wire width 32 $0\alu_op__insn$19[31:0]$9501 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 + attribute \src "libresoc.v:168959.3-168960.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9371 + attribute \src "libresoc.v:168334.13-168334.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9503 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_in$10$next[0:0]$9424 + attribute \src "libresoc.v:168975.3-168976.59" + wire $0\alu_op__invert_in$10[0:0]$9387 + attribute \src "libresoc.v:168418.7-168418.36" + wire $0\alu_op__invert_in$10[0:0]$9505 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__invert_out$12$next[0:0]$9425 + attribute \src "libresoc.v:168979.3-168980.61" + wire $0\alu_op__invert_out$12[0:0]$9391 + attribute \src "libresoc.v:168427.7-168427.37" + wire $0\alu_op__invert_out$12[0:0]$9507 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9426 + attribute \src "libresoc.v:168987.3-168988.57" + wire $0\alu_op__is_32bit$16[0:0]$9399 + attribute \src "libresoc.v:168436.7-168436.35" + wire $0\alu_op__is_32bit$16[0:0]$9509 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__is_signed$17$next[0:0]$9427 + attribute \src "libresoc.v:168989.3-168990.59" + wire $0\alu_op__is_signed$17[0:0]$9401 + attribute \src "libresoc.v:168445.7-168445.36" + wire $0\alu_op__is_signed$17[0:0]$9511 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9428 + attribute \src "libresoc.v:168971.3-168972.51" + wire $0\alu_op__oe__oe$8[0:0]$9383 + attribute \src "libresoc.v:168456.7-168456.32" + wire $0\alu_op__oe__oe$8[0:0]$9513 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9429 + attribute \src "libresoc.v:168973.3-168974.51" + wire $0\alu_op__oe__ok$9[0:0]$9385 + attribute \src "libresoc.v:168465.7-168465.32" + wire $0\alu_op__oe__ok$9[0:0]$9515 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__output_carry$15$next[0:0]$9430 + attribute \src "libresoc.v:168985.3-168986.65" + wire $0\alu_op__output_carry$15[0:0]$9397 + attribute \src "libresoc.v:168472.7-168472.39" + wire $0\alu_op__output_carry$15[0:0]$9517 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9431 + attribute \src "libresoc.v:168969.3-168970.51" + wire $0\alu_op__rc__ok$7[0:0]$9381 + attribute \src "libresoc.v:168483.7-168483.32" + wire $0\alu_op__rc__ok$7[0:0]$9519 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9432 + attribute \src "libresoc.v:168967.3-168968.51" + wire $0\alu_op__rc__rc$6[0:0]$9379 + attribute \src "libresoc.v:168490.7-168490.32" + wire $0\alu_op__rc__rc$6[0:0]$9521 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9433 + attribute \src "libresoc.v:168981.3-168982.59" + wire $0\alu_op__write_cr0$13[0:0]$9393 + attribute \src "libresoc.v:168499.7-168499.36" + wire $0\alu_op__write_cr0$13[0:0]$9523 + attribute \src "libresoc.v:169094.3-169135.6" + wire $0\alu_op__zero_a$11$next[0:0]$9434 + attribute \src "libresoc.v:168977.3-168978.53" + wire $0\alu_op__zero_a$11[0:0]$9389 + attribute \src "libresoc.v:168508.7-168508.33" + wire $0\alu_op__zero_a$11[0:0]$9525 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $0\cr_a$22$next[3:0]$9466 + attribute \src "libresoc.v:168951.3-168952.33" + wire width 4 $0\cr_a$22[3:0]$9363 + attribute \src "libresoc.v:168521.13-168521.29" + wire width 4 $0\cr_a$22[3:0]$9527 + attribute \src "libresoc.v:169155.3-169173.6" + wire $0\cr_a_ok$23$next[0:0]$9467 + attribute \src "libresoc.v:168953.3-168954.39" + wire $0\cr_a_ok$23[0:0]$9365 + attribute \src "libresoc.v:168530.7-168530.26" + wire $0\cr_a_ok$23[0:0]$9529 + attribute \src "libresoc.v:168066.7-168066.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167449.3-167461.6" - wire width 2 $0\muxid$1$next[1:0]$9366 - attribute \src "libresoc.v:167363.3-167364.33" - wire width 2 $0\muxid$1[1:0]$9359 - attribute \src "libresoc.v:166909.13-166909.29" - wire width 2 $0\muxid$1[1:0]$9483 - attribute \src "libresoc.v:167504.3-167522.6" - wire width 64 $0\o$20$next[63:0]$9412 - attribute \src "libresoc.v:167323.3-167324.27" - wire width 64 $0\o$20[63:0]$9319 - attribute \src "libresoc.v:166924.14-166924.43" - wire width 64 $0\o$20[63:0]$9485 - attribute \src "libresoc.v:167504.3-167522.6" - wire $0\o_ok$21$next[0:0]$9413 - attribute \src "libresoc.v:167325.3-167326.33" - wire $0\o_ok$21[0:0]$9321 - attribute \src "libresoc.v:166933.7-166933.23" - wire $0\o_ok$21[0:0]$9487 - attribute \src "libresoc.v:167431.3-167448.6" - wire $0\r_busy$next[0:0]$9362 - attribute \src "libresoc.v:167365.3-167366.29" + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $0\muxid$1$next[1:0]$9414 + attribute \src "libresoc.v:168995.3-168996.33" + wire width 2 $0\muxid$1[1:0]$9407 + attribute \src "libresoc.v:168541.13-168541.29" + wire width 2 $0\muxid$1[1:0]$9531 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $0\o$20$next[63:0]$9460 + attribute \src "libresoc.v:168955.3-168956.27" + wire width 64 $0\o$20[63:0]$9367 + attribute \src "libresoc.v:168556.14-168556.43" + wire width 64 $0\o$20[63:0]$9533 + attribute \src "libresoc.v:169136.3-169154.6" + wire $0\o_ok$21$next[0:0]$9461 + attribute \src "libresoc.v:168957.3-168958.33" + wire $0\o_ok$21[0:0]$9369 + attribute \src "libresoc.v:168565.7-168565.23" + wire $0\o_ok$21[0:0]$9535 + attribute \src "libresoc.v:169063.3-169080.6" + wire $0\r_busy$next[0:0]$9410 + attribute \src "libresoc.v:168997.3-168998.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167542.3-167560.6" - wire width 2 $0\xer_ca$24$next[1:0]$9424 - attribute \src "libresoc.v:167315.3-167316.37" - wire width 2 $0\xer_ca$24[1:0]$9311 - attribute \src "libresoc.v:167250.13-167250.31" - wire width 2 $0\xer_ca$24[1:0]$9490 - attribute \src "libresoc.v:167542.3-167560.6" - wire $0\xer_ca_ok$25$next[0:0]$9425 - attribute \src "libresoc.v:167317.3-167318.43" - wire $0\xer_ca_ok$25[0:0]$9313 - attribute \src "libresoc.v:167259.7-167259.28" - wire $0\xer_ca_ok$25[0:0]$9492 - attribute \src "libresoc.v:167561.3-167579.6" - wire width 2 $0\xer_ov$26$next[1:0]$9430 - attribute \src "libresoc.v:167311.3-167312.37" - wire width 2 $0\xer_ov$26[1:0]$9307 - attribute \src "libresoc.v:167270.13-167270.31" - wire width 2 $0\xer_ov$26[1:0]$9494 - attribute \src "libresoc.v:167561.3-167579.6" - wire $0\xer_ov_ok$27$next[0:0]$9431 - attribute \src "libresoc.v:167313.3-167314.43" - wire $0\xer_ov_ok$27[0:0]$9309 - attribute \src "libresoc.v:167279.7-167279.28" - wire $0\xer_ov_ok$27[0:0]$9496 - attribute \src "libresoc.v:167580.3-167598.6" - wire $0\xer_so$28$next[0:0]$9436 - attribute \src "libresoc.v:167307.3-167308.37" - wire $0\xer_so$28[0:0]$9303 - attribute \src "libresoc.v:167290.7-167290.25" - wire $0\xer_so$28[0:0]$9498 - attribute \src "libresoc.v:167580.3-167598.6" - wire $0\xer_so_ok$29$next[0:0]$9437 - attribute \src "libresoc.v:167309.3-167310.43" - wire $0\xer_so_ok$29[0:0]$9305 - attribute \src "libresoc.v:167299.7-167299.28" - wire $0\xer_so_ok$29[0:0]$9500 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9387 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9388 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9389 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9390 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9391 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9392 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9393 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__invert_in$10$next[0:0]$9394 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__invert_out$12$next[0:0]$9395 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9396 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__is_signed$17$next[0:0]$9397 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9398 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9399 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__output_carry$15$next[0:0]$9400 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9401 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9402 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9403 - attribute \src "libresoc.v:167462.3-167503.6" - wire $1\alu_op__zero_a$11$next[0:0]$9404 - attribute \src "libresoc.v:167523.3-167541.6" - wire width 4 $1\cr_a$22$next[3:0]$9420 - attribute \src "libresoc.v:167523.3-167541.6" - wire $1\cr_a_ok$23$next[0:0]$9421 - attribute \src "libresoc.v:167449.3-167461.6" - wire width 2 $1\muxid$1$next[1:0]$9367 - attribute \src "libresoc.v:167504.3-167522.6" - wire width 64 $1\o$20$next[63:0]$9414 - attribute \src "libresoc.v:167504.3-167522.6" - wire $1\o_ok$21$next[0:0]$9415 - attribute \src "libresoc.v:167431.3-167448.6" - wire $1\r_busy$next[0:0]$9363 - attribute \src "libresoc.v:167243.7-167243.20" + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $0\xer_ca$24$next[1:0]$9472 + attribute \src "libresoc.v:168947.3-168948.37" + wire width 2 $0\xer_ca$24[1:0]$9359 + attribute \src "libresoc.v:168882.13-168882.31" + wire width 2 $0\xer_ca$24[1:0]$9538 + attribute \src "libresoc.v:169174.3-169192.6" + wire $0\xer_ca_ok$25$next[0:0]$9473 + attribute \src "libresoc.v:168949.3-168950.43" + wire $0\xer_ca_ok$25[0:0]$9361 + attribute \src "libresoc.v:168891.7-168891.28" + wire $0\xer_ca_ok$25[0:0]$9540 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $0\xer_ov$26$next[1:0]$9478 + attribute \src "libresoc.v:168943.3-168944.37" + wire width 2 $0\xer_ov$26[1:0]$9355 + attribute \src "libresoc.v:168902.13-168902.31" + wire width 2 $0\xer_ov$26[1:0]$9542 + attribute \src "libresoc.v:169193.3-169211.6" + wire $0\xer_ov_ok$27$next[0:0]$9479 + attribute \src "libresoc.v:168945.3-168946.43" + wire $0\xer_ov_ok$27[0:0]$9357 + attribute \src "libresoc.v:168911.7-168911.28" + wire $0\xer_ov_ok$27[0:0]$9544 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so$28$next[0:0]$9484 + attribute \src "libresoc.v:168939.3-168940.37" + wire $0\xer_so$28[0:0]$9351 + attribute \src "libresoc.v:168922.7-168922.25" + wire $0\xer_so$28[0:0]$9546 + attribute \src "libresoc.v:169212.3-169230.6" + wire $0\xer_so_ok$29$next[0:0]$9485 + attribute \src "libresoc.v:168941.3-168942.43" + wire $0\xer_so_ok$29[0:0]$9353 + attribute \src "libresoc.v:168931.7-168931.28" + wire $0\xer_so_ok$29[0:0]$9548 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9440 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_in$10$next[0:0]$9442 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__invert_out$12$next[0:0]$9443 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9444 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__is_signed$17$next[0:0]$9445 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9446 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9447 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__output_carry$15$next[0:0]$9448 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9449 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9450 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9451 + attribute \src "libresoc.v:169094.3-169135.6" + wire $1\alu_op__zero_a$11$next[0:0]$9452 + attribute \src "libresoc.v:169155.3-169173.6" + wire width 4 $1\cr_a$22$next[3:0]$9468 + attribute \src "libresoc.v:169155.3-169173.6" + wire $1\cr_a_ok$23$next[0:0]$9469 + attribute \src "libresoc.v:169081.3-169093.6" + wire width 2 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169136.3-169154.6" + wire width 64 $1\o$20$next[63:0]$9462 + attribute \src "libresoc.v:169136.3-169154.6" + wire $1\o_ok$21$next[0:0]$9463 + attribute \src "libresoc.v:169063.3-169080.6" + wire $1\r_busy$next[0:0]$9411 + attribute \src "libresoc.v:168875.7-168875.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167542.3-167560.6" - wire width 2 $1\xer_ca$24$next[1:0]$9426 - attribute \src "libresoc.v:167542.3-167560.6" - wire $1\xer_ca_ok$25$next[0:0]$9427 - attribute \src "libresoc.v:167561.3-167579.6" - wire width 2 $1\xer_ov$26$next[1:0]$9432 - attribute \src "libresoc.v:167561.3-167579.6" - wire $1\xer_ov_ok$27$next[0:0]$9433 - attribute \src "libresoc.v:167580.3-167598.6" - wire $1\xer_so$28$next[0:0]$9438 - attribute \src "libresoc.v:167580.3-167598.6" - wire $1\xer_so_ok$29$next[0:0]$9439 - attribute \src "libresoc.v:167462.3-167503.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9405 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9406 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9407 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9408 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9409 - attribute \src "libresoc.v:167462.3-167503.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9410 - attribute \src "libresoc.v:167523.3-167541.6" - wire $2\cr_a_ok$23$next[0:0]$9422 - attribute \src "libresoc.v:167504.3-167522.6" - wire $2\o_ok$21$next[0:0]$9416 - attribute \src "libresoc.v:167431.3-167448.6" - wire $2\r_busy$next[0:0]$9364 - attribute \src "libresoc.v:167542.3-167560.6" - wire $2\xer_ca_ok$25$next[0:0]$9428 - attribute \src "libresoc.v:167561.3-167579.6" - wire $2\xer_ov_ok$27$next[0:0]$9434 - attribute \src "libresoc.v:167580.3-167598.6" - wire $2\xer_so_ok$29$next[0:0]$9440 - attribute \src "libresoc.v:167306.18-167306.118" - wire $and$libresoc.v:167306$9301_Y + attribute \src "libresoc.v:169174.3-169192.6" + wire width 2 $1\xer_ca$24$next[1:0]$9474 + attribute \src "libresoc.v:169174.3-169192.6" + wire $1\xer_ca_ok$25$next[0:0]$9475 + attribute \src "libresoc.v:169193.3-169211.6" + wire width 2 $1\xer_ov$26$next[1:0]$9480 + attribute \src "libresoc.v:169193.3-169211.6" + wire $1\xer_ov_ok$27$next[0:0]$9481 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so$28$next[0:0]$9486 + attribute \src "libresoc.v:169212.3-169230.6" + wire $1\xer_so_ok$29$next[0:0]$9487 + attribute \src "libresoc.v:169094.3-169135.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9455 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9456 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9457 + attribute \src "libresoc.v:169094.3-169135.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169155.3-169173.6" + wire $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169136.3-169154.6" + wire $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169063.3-169080.6" + wire $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169174.3-169192.6" + wire $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169193.3-169211.6" + wire $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169212.3-169230.6" + wire $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:168938.18-168938.118" + wire $and$libresoc.v:168938$9349_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -344368,9 +346865,9 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -344390,7 +346887,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$84 - attribute \src "libresoc.v:166434.7-166434.15" + attribute \src "libresoc.v:168066.7-168066.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -344785,7 +347282,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167306$9301 + cell $and $and$libresoc.v:168938$9349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -344793,16 +347290,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:167306$9301_Y + connect \Y $and$libresoc.v:168938$9349_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167367.9-167370.4" + attribute \src "libresoc.v:168999.9-169002.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167371.12-167426.4" + attribute \src "libresoc.v:169003.12-169058.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -344860,478 +347357,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:167427.9-167430.4" + attribute \src "libresoc.v:169059.9-169062.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:166434.7-166434.20" - process $proc$libresoc.v:166434$9441 + attribute \src "libresoc.v:168066.7-168066.20" + process $proc$libresoc.v:168066$9489 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166441.13-166441.41" - process $proc$libresoc.v:166441$9442 + attribute \src "libresoc.v:168073.13-168073.41" + process $proc$libresoc.v:168073$9490 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9443 4'0000 + assign $0\alu_op__data_len$18[3:0]$9491 4'0000 sync always sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9443 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 end - attribute \src "libresoc.v:166480.14-166480.44" - process $proc$libresoc.v:166480$9444 + attribute \src "libresoc.v:168112.14-168112.44" + process $proc$libresoc.v:168112$9492 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9445 14'00000000000000 + assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 sync always sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9445 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 end - attribute \src "libresoc.v:166504.14-166504.63" - process $proc$libresoc.v:166504$9446 + attribute \src "libresoc.v:168136.14-168136.63" + process $proc$libresoc.v:168136$9494 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9447 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9447 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 end - attribute \src "libresoc.v:166513.7-166513.38" - process $proc$libresoc.v:166513$9448 + attribute \src "libresoc.v:168145.7-168145.38" + process $proc$libresoc.v:168145$9496 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9449 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9449 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 end - attribute \src "libresoc.v:166530.13-166530.44" - process $proc$libresoc.v:166530$9450 + attribute \src "libresoc.v:168162.13-168162.44" + process $proc$libresoc.v:168162$9498 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9451 2'00 + assign $0\alu_op__input_carry$14[1:0]$9499 2'00 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9451 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 end - attribute \src "libresoc.v:166543.14-166543.39" - process $proc$libresoc.v:166543$9452 + attribute \src "libresoc.v:168175.14-168175.39" + process $proc$libresoc.v:168175$9500 assign { } { } - assign $0\alu_op__insn$19[31:0]$9453 0 + assign $0\alu_op__insn$19[31:0]$9501 0 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9453 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 end - attribute \src "libresoc.v:166702.13-166702.42" - process $proc$libresoc.v:166702$9454 + attribute \src "libresoc.v:168334.13-168334.42" + process $proc$libresoc.v:168334$9502 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9455 7'0000000 + assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9455 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 end - attribute \src "libresoc.v:166786.7-166786.36" - process $proc$libresoc.v:166786$9456 + attribute \src "libresoc.v:168418.7-168418.36" + process $proc$libresoc.v:168418$9504 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9457 1'0 + assign $0\alu_op__invert_in$10[0:0]$9505 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9457 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 end - attribute \src "libresoc.v:166795.7-166795.37" - process $proc$libresoc.v:166795$9458 + attribute \src "libresoc.v:168427.7-168427.37" + process $proc$libresoc.v:168427$9506 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9459 1'0 + assign $0\alu_op__invert_out$12[0:0]$9507 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9459 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 end - attribute \src "libresoc.v:166804.7-166804.35" - process $proc$libresoc.v:166804$9460 + attribute \src "libresoc.v:168436.7-168436.35" + process $proc$libresoc.v:168436$9508 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9461 1'0 + assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9461 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 end - attribute \src "libresoc.v:166813.7-166813.36" - process $proc$libresoc.v:166813$9462 + attribute \src "libresoc.v:168445.7-168445.36" + process $proc$libresoc.v:168445$9510 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9463 1'0 + assign $0\alu_op__is_signed$17[0:0]$9511 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9463 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 end - attribute \src "libresoc.v:166824.7-166824.32" - process $proc$libresoc.v:166824$9464 + attribute \src "libresoc.v:168456.7-168456.32" + process $proc$libresoc.v:168456$9512 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9465 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9465 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 end - attribute \src "libresoc.v:166833.7-166833.32" - process $proc$libresoc.v:166833$9466 + attribute \src "libresoc.v:168465.7-168465.32" + process $proc$libresoc.v:168465$9514 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9467 1'0 + assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9467 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 end - attribute \src "libresoc.v:166840.7-166840.39" - process $proc$libresoc.v:166840$9468 + attribute \src "libresoc.v:168472.7-168472.39" + process $proc$libresoc.v:168472$9516 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9469 1'0 + assign $0\alu_op__output_carry$15[0:0]$9517 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9469 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 end - attribute \src "libresoc.v:166851.7-166851.32" - process $proc$libresoc.v:166851$9470 + attribute \src "libresoc.v:168483.7-168483.32" + process $proc$libresoc.v:168483$9518 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9471 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9471 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 end - attribute \src "libresoc.v:166858.7-166858.32" - process $proc$libresoc.v:166858$9472 + attribute \src "libresoc.v:168490.7-168490.32" + process $proc$libresoc.v:168490$9520 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9473 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9473 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 end - attribute \src "libresoc.v:166867.7-166867.36" - process $proc$libresoc.v:166867$9474 + attribute \src "libresoc.v:168499.7-168499.36" + process $proc$libresoc.v:168499$9522 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9475 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9475 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 end - attribute \src "libresoc.v:166876.7-166876.33" - process $proc$libresoc.v:166876$9476 + attribute \src "libresoc.v:168508.7-168508.33" + process $proc$libresoc.v:168508$9524 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9477 1'0 + assign $0\alu_op__zero_a$11[0:0]$9525 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9477 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 end - attribute \src "libresoc.v:166889.13-166889.29" - process $proc$libresoc.v:166889$9478 + attribute \src "libresoc.v:168521.13-168521.29" + process $proc$libresoc.v:168521$9526 assign { } { } - assign $0\cr_a$22[3:0]$9479 4'0000 + assign $0\cr_a$22[3:0]$9527 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9479 + update \cr_a$22 $0\cr_a$22[3:0]$9527 end - attribute \src "libresoc.v:166898.7-166898.26" - process $proc$libresoc.v:166898$9480 + attribute \src "libresoc.v:168530.7-168530.26" + process $proc$libresoc.v:168530$9528 assign { } { } - assign $0\cr_a_ok$23[0:0]$9481 1'0 + assign $0\cr_a_ok$23[0:0]$9529 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9481 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 end - attribute \src "libresoc.v:166909.13-166909.29" - process $proc$libresoc.v:166909$9482 + attribute \src "libresoc.v:168541.13-168541.29" + process $proc$libresoc.v:168541$9530 assign { } { } - assign $0\muxid$1[1:0]$9483 2'00 + assign $0\muxid$1[1:0]$9531 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9483 + update \muxid$1 $0\muxid$1[1:0]$9531 end - attribute \src "libresoc.v:166924.14-166924.43" - process $proc$libresoc.v:166924$9484 + attribute \src "libresoc.v:168556.14-168556.43" + process $proc$libresoc.v:168556$9532 assign { } { } - assign $0\o$20[63:0]$9485 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$9485 + update \o$20 $0\o$20[63:0]$9533 end - attribute \src "libresoc.v:166933.7-166933.23" - process $proc$libresoc.v:166933$9486 + attribute \src "libresoc.v:168565.7-168565.23" + process $proc$libresoc.v:168565$9534 assign { } { } - assign $0\o_ok$21[0:0]$9487 1'0 + assign $0\o_ok$21[0:0]$9535 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9487 + update \o_ok$21 $0\o_ok$21[0:0]$9535 end - attribute \src "libresoc.v:167243.7-167243.20" - process $proc$libresoc.v:167243$9488 + attribute \src "libresoc.v:168875.7-168875.20" + process $proc$libresoc.v:168875$9536 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167250.13-167250.31" - process $proc$libresoc.v:167250$9489 + attribute \src "libresoc.v:168882.13-168882.31" + process $proc$libresoc.v:168882$9537 assign { } { } - assign $0\xer_ca$24[1:0]$9490 2'00 + assign $0\xer_ca$24[1:0]$9538 2'00 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9490 + update \xer_ca$24 $0\xer_ca$24[1:0]$9538 end - attribute \src "libresoc.v:167259.7-167259.28" - process $proc$libresoc.v:167259$9491 + attribute \src "libresoc.v:168891.7-168891.28" + process $proc$libresoc.v:168891$9539 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9492 1'0 + assign $0\xer_ca_ok$25[0:0]$9540 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9492 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 end - attribute \src "libresoc.v:167270.13-167270.31" - process $proc$libresoc.v:167270$9493 + attribute \src "libresoc.v:168902.13-168902.31" + process $proc$libresoc.v:168902$9541 assign { } { } - assign $0\xer_ov$26[1:0]$9494 2'00 + assign $0\xer_ov$26[1:0]$9542 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9494 + update \xer_ov$26 $0\xer_ov$26[1:0]$9542 end - attribute \src "libresoc.v:167279.7-167279.28" - process $proc$libresoc.v:167279$9495 + attribute \src "libresoc.v:168911.7-168911.28" + process $proc$libresoc.v:168911$9543 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9496 1'0 + assign $0\xer_ov_ok$27[0:0]$9544 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9496 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 end - attribute \src "libresoc.v:167290.7-167290.25" - process $proc$libresoc.v:167290$9497 + attribute \src "libresoc.v:168922.7-168922.25" + process $proc$libresoc.v:168922$9545 assign { } { } - assign $0\xer_so$28[0:0]$9498 1'0 + assign $0\xer_so$28[0:0]$9546 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9498 + update \xer_so$28 $0\xer_so$28[0:0]$9546 end - attribute \src "libresoc.v:167299.7-167299.28" - process $proc$libresoc.v:167299$9499 + attribute \src "libresoc.v:168931.7-168931.28" + process $proc$libresoc.v:168931$9547 assign { } { } - assign $0\xer_so_ok$29[0:0]$9500 1'0 + assign $0\xer_so_ok$29[0:0]$9548 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9500 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 end - attribute \src "libresoc.v:167307.3-167308.37" - process $proc$libresoc.v:167307$9302 + attribute \src "libresoc.v:168939.3-168940.37" + process $proc$libresoc.v:168939$9350 assign { } { } - assign $0\xer_so$28[0:0]$9303 \xer_so$28$next + assign $0\xer_so$28[0:0]$9351 \xer_so$28$next sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9303 + update \xer_so$28 $0\xer_so$28[0:0]$9351 end - attribute \src "libresoc.v:167309.3-167310.43" - process $proc$libresoc.v:167309$9304 + attribute \src "libresoc.v:168941.3-168942.43" + process $proc$libresoc.v:168941$9352 assign { } { } - assign $0\xer_so_ok$29[0:0]$9305 \xer_so_ok$29$next + assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9305 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 end - attribute \src "libresoc.v:167311.3-167312.37" - process $proc$libresoc.v:167311$9306 + attribute \src "libresoc.v:168943.3-168944.37" + process $proc$libresoc.v:168943$9354 assign { } { } - assign $0\xer_ov$26[1:0]$9307 \xer_ov$26$next + assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9307 + update \xer_ov$26 $0\xer_ov$26[1:0]$9355 end - attribute \src "libresoc.v:167313.3-167314.43" - process $proc$libresoc.v:167313$9308 + attribute \src "libresoc.v:168945.3-168946.43" + process $proc$libresoc.v:168945$9356 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9309 \xer_ov_ok$27$next + assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9309 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 end - attribute \src "libresoc.v:167315.3-167316.37" - process $proc$libresoc.v:167315$9310 + attribute \src "libresoc.v:168947.3-168948.37" + process $proc$libresoc.v:168947$9358 assign { } { } - assign $0\xer_ca$24[1:0]$9311 \xer_ca$24$next + assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9311 + update \xer_ca$24 $0\xer_ca$24[1:0]$9359 end - attribute \src "libresoc.v:167317.3-167318.43" - process $proc$libresoc.v:167317$9312 + attribute \src "libresoc.v:168949.3-168950.43" + process $proc$libresoc.v:168949$9360 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9313 \xer_ca_ok$25$next + assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9313 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 end - attribute \src "libresoc.v:167319.3-167320.33" - process $proc$libresoc.v:167319$9314 + attribute \src "libresoc.v:168951.3-168952.33" + process $proc$libresoc.v:168951$9362 assign { } { } - assign $0\cr_a$22[3:0]$9315 \cr_a$22$next + assign $0\cr_a$22[3:0]$9363 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9315 + update \cr_a$22 $0\cr_a$22[3:0]$9363 end - attribute \src "libresoc.v:167321.3-167322.39" - process $proc$libresoc.v:167321$9316 + attribute \src "libresoc.v:168953.3-168954.39" + process $proc$libresoc.v:168953$9364 assign { } { } - assign $0\cr_a_ok$23[0:0]$9317 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9317 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 end - attribute \src "libresoc.v:167323.3-167324.27" - process $proc$libresoc.v:167323$9318 + attribute \src "libresoc.v:168955.3-168956.27" + process $proc$libresoc.v:168955$9366 assign { } { } - assign $0\o$20[63:0]$9319 \o$20$next + assign $0\o$20[63:0]$9367 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9319 + update \o$20 $0\o$20[63:0]$9367 end - attribute \src "libresoc.v:167325.3-167326.33" - process $proc$libresoc.v:167325$9320 + attribute \src "libresoc.v:168957.3-168958.33" + process $proc$libresoc.v:168957$9368 assign { } { } - assign $0\o_ok$21[0:0]$9321 \o_ok$21$next + assign $0\o_ok$21[0:0]$9369 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9321 + update \o_ok$21 $0\o_ok$21[0:0]$9369 end - attribute \src "libresoc.v:167327.3-167328.57" - process $proc$libresoc.v:167327$9322 + attribute \src "libresoc.v:168959.3-168960.57" + process $proc$libresoc.v:168959$9370 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9323 \alu_op__insn_type$2$next + assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9323 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 end - attribute \src "libresoc.v:167329.3-167330.53" - process $proc$libresoc.v:167329$9324 + attribute \src "libresoc.v:168961.3-168962.53" + process $proc$libresoc.v:168961$9372 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9325 \alu_op__fn_unit$3$next + assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9325 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 end - attribute \src "libresoc.v:167331.3-167332.67" - process $proc$libresoc.v:167331$9326 + attribute \src "libresoc.v:168963.3-168964.67" + process $proc$libresoc.v:168963$9374 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9327 \alu_op__imm_data__data$4$next + assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9327 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 end - attribute \src "libresoc.v:167333.3-167334.63" - process $proc$libresoc.v:167333$9328 + attribute \src "libresoc.v:168965.3-168966.63" + process $proc$libresoc.v:168965$9376 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9329 \alu_op__imm_data__ok$5$next + assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9329 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 end - attribute \src "libresoc.v:167335.3-167336.51" - process $proc$libresoc.v:167335$9330 + attribute \src "libresoc.v:168967.3-168968.51" + process $proc$libresoc.v:168967$9378 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9331 \alu_op__rc__rc$6$next + assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9331 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 end - attribute \src "libresoc.v:167337.3-167338.51" - process $proc$libresoc.v:167337$9332 + attribute \src "libresoc.v:168969.3-168970.51" + process $proc$libresoc.v:168969$9380 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9333 \alu_op__rc__ok$7$next + assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9333 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 end - attribute \src "libresoc.v:167339.3-167340.51" - process $proc$libresoc.v:167339$9334 + attribute \src "libresoc.v:168971.3-168972.51" + process $proc$libresoc.v:168971$9382 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9335 \alu_op__oe__oe$8$next + assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9335 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 end - attribute \src "libresoc.v:167341.3-167342.51" - process $proc$libresoc.v:167341$9336 + attribute \src "libresoc.v:168973.3-168974.51" + process $proc$libresoc.v:168973$9384 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9337 \alu_op__oe__ok$9$next + assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9337 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 end - attribute \src "libresoc.v:167343.3-167344.59" - process $proc$libresoc.v:167343$9338 + attribute \src "libresoc.v:168975.3-168976.59" + process $proc$libresoc.v:168975$9386 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9339 \alu_op__invert_in$10$next + assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9339 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 end - attribute \src "libresoc.v:167345.3-167346.53" - process $proc$libresoc.v:167345$9340 + attribute \src "libresoc.v:168977.3-168978.53" + process $proc$libresoc.v:168977$9388 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9341 \alu_op__zero_a$11$next + assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9341 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 end - attribute \src "libresoc.v:167347.3-167348.61" - process $proc$libresoc.v:167347$9342 + attribute \src "libresoc.v:168979.3-168980.61" + process $proc$libresoc.v:168979$9390 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9343 \alu_op__invert_out$12$next + assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9343 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 end - attribute \src "libresoc.v:167349.3-167350.59" - process $proc$libresoc.v:167349$9344 + attribute \src "libresoc.v:168981.3-168982.59" + process $proc$libresoc.v:168981$9392 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9345 \alu_op__write_cr0$13$next + assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9345 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 end - attribute \src "libresoc.v:167351.3-167352.63" - process $proc$libresoc.v:167351$9346 + attribute \src "libresoc.v:168983.3-168984.63" + process $proc$libresoc.v:168983$9394 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9347 \alu_op__input_carry$14$next + assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9347 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 end - attribute \src "libresoc.v:167353.3-167354.65" - process $proc$libresoc.v:167353$9348 + attribute \src "libresoc.v:168985.3-168986.65" + process $proc$libresoc.v:168985$9396 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9349 \alu_op__output_carry$15$next + assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9349 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 end - attribute \src "libresoc.v:167355.3-167356.57" - process $proc$libresoc.v:167355$9350 + attribute \src "libresoc.v:168987.3-168988.57" + process $proc$libresoc.v:168987$9398 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9351 \alu_op__is_32bit$16$next + assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9351 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 end - attribute \src "libresoc.v:167357.3-167358.59" - process $proc$libresoc.v:167357$9352 + attribute \src "libresoc.v:168989.3-168990.59" + process $proc$libresoc.v:168989$9400 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9353 \alu_op__is_signed$17$next + assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9353 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 end - attribute \src "libresoc.v:167359.3-167360.57" - process $proc$libresoc.v:167359$9354 + attribute \src "libresoc.v:168991.3-168992.57" + process $proc$libresoc.v:168991$9402 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9355 \alu_op__data_len$18$next + assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9355 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 end - attribute \src "libresoc.v:167361.3-167362.49" - process $proc$libresoc.v:167361$9356 + attribute \src "libresoc.v:168993.3-168994.49" + process $proc$libresoc.v:168993$9404 assign { } { } - assign $0\alu_op__insn$19[31:0]$9357 \alu_op__insn$19$next + assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9357 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 end - attribute \src "libresoc.v:167363.3-167364.33" - process $proc$libresoc.v:167363$9358 + attribute \src "libresoc.v:168995.3-168996.33" + process $proc$libresoc.v:168995$9406 assign { } { } - assign $0\muxid$1[1:0]$9359 \muxid$1$next + assign $0\muxid$1[1:0]$9407 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9359 + update \muxid$1 $0\muxid$1[1:0]$9407 end - attribute \src "libresoc.v:167365.3-167366.29" - process $proc$libresoc.v:167365$9360 + attribute \src "libresoc.v:168997.3-168998.29" + process $proc$libresoc.v:168997$9408 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167431.3-167448.6" - process $proc$libresoc.v:167431$9361 + attribute \src "libresoc.v:169063.3-169080.6" + process $proc$libresoc.v:169063$9409 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9362 $2\r_busy$next[0:0]$9364 - attribute \src "libresoc.v:167432.5-167432.29" + assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:169064.5-169064.29" switch \initial - attribute \src "libresoc.v:167432.9-167432.17" + attribute \src "libresoc.v:169064.9-169064.17" case 1'1 case end @@ -345340,34 +347837,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9363 1'1 + assign $1\r_busy$next[0:0]$9411 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9363 1'0 + assign $1\r_busy$next[0:0]$9411 1'0 case - assign $1\r_busy$next[0:0]$9363 \r_busy + assign $1\r_busy$next[0:0]$9411 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9364 1'0 + assign $2\r_busy$next[0:0]$9412 1'0 case - assign $2\r_busy$next[0:0]$9364 $1\r_busy$next[0:0]$9363 + assign $2\r_busy$next[0:0]$9412 $1\r_busy$next[0:0]$9411 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9362 + update \r_busy$next $0\r_busy$next[0:0]$9410 end - attribute \src "libresoc.v:167449.3-167461.6" - process $proc$libresoc.v:167449$9365 + attribute \src "libresoc.v:169081.3-169093.6" + process $proc$libresoc.v:169081$9413 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9366 $1\muxid$1$next[1:0]$9367 - attribute \src "libresoc.v:167450.5-167450.29" + assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 + attribute \src "libresoc.v:169082.5-169082.29" switch \initial - attribute \src "libresoc.v:167450.9-167450.17" + attribute \src "libresoc.v:169082.9-169082.17" case 1'1 case end @@ -345376,19 +347873,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9367 \muxid$62 + assign $1\muxid$1$next[1:0]$9415 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9367 \muxid$62 + assign $1\muxid$1$next[1:0]$9415 \muxid$62 case - assign $1\muxid$1$next[1:0]$9367 \muxid$1 + assign $1\muxid$1$next[1:0]$9415 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9366 + update \muxid$1$next $0\muxid$1$next[1:0]$9414 end - attribute \src "libresoc.v:167462.3-167503.6" - process $proc$libresoc.v:167462$9368 + attribute \src "libresoc.v:169094.3-169135.6" + process $proc$libresoc.v:169094$9416 assign { } { } assign { } { } assign { } { } @@ -345425,33 +347922,33 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9369 $1\alu_op__data_len$18$next[3:0]$9387 - assign $0\alu_op__fn_unit$3$next[13:0]$9370 $1\alu_op__fn_unit$3$next[13:0]$9388 + assign $0\alu_op__data_len$18$next[3:0]$9417 $1\alu_op__data_len$18$next[3:0]$9435 + assign $0\alu_op__fn_unit$3$next[13:0]$9418 $1\alu_op__fn_unit$3$next[13:0]$9436 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9373 $1\alu_op__input_carry$14$next[1:0]$9391 - assign $0\alu_op__insn$19$next[31:0]$9374 $1\alu_op__insn$19$next[31:0]$9392 - assign $0\alu_op__insn_type$2$next[6:0]$9375 $1\alu_op__insn_type$2$next[6:0]$9393 - assign $0\alu_op__invert_in$10$next[0:0]$9376 $1\alu_op__invert_in$10$next[0:0]$9394 - assign $0\alu_op__invert_out$12$next[0:0]$9377 $1\alu_op__invert_out$12$next[0:0]$9395 - assign $0\alu_op__is_32bit$16$next[0:0]$9378 $1\alu_op__is_32bit$16$next[0:0]$9396 - assign $0\alu_op__is_signed$17$next[0:0]$9379 $1\alu_op__is_signed$17$next[0:0]$9397 + assign $0\alu_op__input_carry$14$next[1:0]$9421 $1\alu_op__input_carry$14$next[1:0]$9439 + assign $0\alu_op__insn$19$next[31:0]$9422 $1\alu_op__insn$19$next[31:0]$9440 + assign $0\alu_op__insn_type$2$next[6:0]$9423 $1\alu_op__insn_type$2$next[6:0]$9441 + assign $0\alu_op__invert_in$10$next[0:0]$9424 $1\alu_op__invert_in$10$next[0:0]$9442 + assign $0\alu_op__invert_out$12$next[0:0]$9425 $1\alu_op__invert_out$12$next[0:0]$9443 + assign $0\alu_op__is_32bit$16$next[0:0]$9426 $1\alu_op__is_32bit$16$next[0:0]$9444 + assign $0\alu_op__is_signed$17$next[0:0]$9427 $1\alu_op__is_signed$17$next[0:0]$9445 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9382 $1\alu_op__output_carry$15$next[0:0]$9400 + assign $0\alu_op__output_carry$15$next[0:0]$9430 $1\alu_op__output_carry$15$next[0:0]$9448 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9385 $1\alu_op__write_cr0$13$next[0:0]$9403 - assign $0\alu_op__zero_a$11$next[0:0]$9386 $1\alu_op__zero_a$11$next[0:0]$9404 - assign $0\alu_op__imm_data__data$4$next[63:0]$9371 $2\alu_op__imm_data__data$4$next[63:0]$9405 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9372 $2\alu_op__imm_data__ok$5$next[0:0]$9406 - assign $0\alu_op__oe__oe$8$next[0:0]$9380 $2\alu_op__oe__oe$8$next[0:0]$9407 - assign $0\alu_op__oe__ok$9$next[0:0]$9381 $2\alu_op__oe__ok$9$next[0:0]$9408 - assign $0\alu_op__rc__ok$7$next[0:0]$9383 $2\alu_op__rc__ok$7$next[0:0]$9409 - assign $0\alu_op__rc__rc$6$next[0:0]$9384 $2\alu_op__rc__rc$6$next[0:0]$9410 - attribute \src "libresoc.v:167463.5-167463.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9433 $1\alu_op__write_cr0$13$next[0:0]$9451 + assign $0\alu_op__zero_a$11$next[0:0]$9434 $1\alu_op__zero_a$11$next[0:0]$9452 + assign $0\alu_op__imm_data__data$4$next[63:0]$9419 $2\alu_op__imm_data__data$4$next[63:0]$9453 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9420 $2\alu_op__imm_data__ok$5$next[0:0]$9454 + assign $0\alu_op__oe__oe$8$next[0:0]$9428 $2\alu_op__oe__oe$8$next[0:0]$9455 + assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 + assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 + assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 + attribute \src "libresoc.v:169095.5-169095.29" switch \initial - attribute \src "libresoc.v:167463.9-167463.17" + attribute \src "libresoc.v:169095.9-169095.17" case 1'1 case end @@ -345477,7 +347974,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -345498,26 +347995,26 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9392 $1\alu_op__data_len$18$next[3:0]$9387 $1\alu_op__is_signed$17$next[0:0]$9397 $1\alu_op__is_32bit$16$next[0:0]$9396 $1\alu_op__output_carry$15$next[0:0]$9400 $1\alu_op__input_carry$14$next[1:0]$9391 $1\alu_op__write_cr0$13$next[0:0]$9403 $1\alu_op__invert_out$12$next[0:0]$9395 $1\alu_op__zero_a$11$next[0:0]$9404 $1\alu_op__invert_in$10$next[0:0]$9394 $1\alu_op__oe__ok$9$next[0:0]$9399 $1\alu_op__oe__oe$8$next[0:0]$9398 $1\alu_op__rc__ok$7$next[0:0]$9401 $1\alu_op__rc__rc$6$next[0:0]$9402 $1\alu_op__imm_data__ok$5$next[0:0]$9390 $1\alu_op__imm_data__data$4$next[63:0]$9389 $1\alu_op__fn_unit$3$next[13:0]$9388 $1\alu_op__insn_type$2$next[6:0]$9393 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\alu_op__data_len$18$next[3:0]$9387 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[13:0]$9388 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9389 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9390 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9391 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9392 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9393 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9394 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9395 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9396 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9397 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9398 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9399 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9400 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9401 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9402 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9403 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9404 \alu_op__zero_a$11 + assign $1\alu_op__data_len$18$next[3:0]$9435 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9436 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9437 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9438 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9439 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9440 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9441 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9442 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9443 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9444 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9445 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9446 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9447 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9448 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9449 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9450 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9451 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9452 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -345529,52 +348026,52 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9405 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9410 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9409 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9407 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9408 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 1'0 case - assign $2\alu_op__imm_data__data$4$next[63:0]$9405 $1\alu_op__imm_data__data$4$next[63:0]$9389 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9406 $1\alu_op__imm_data__ok$5$next[0:0]$9390 - assign $2\alu_op__oe__oe$8$next[0:0]$9407 $1\alu_op__oe__oe$8$next[0:0]$9398 - assign $2\alu_op__oe__ok$9$next[0:0]$9408 $1\alu_op__oe__ok$9$next[0:0]$9399 - assign $2\alu_op__rc__ok$7$next[0:0]$9409 $1\alu_op__rc__ok$7$next[0:0]$9401 - assign $2\alu_op__rc__rc$6$next[0:0]$9410 $1\alu_op__rc__rc$6$next[0:0]$9402 + assign $2\alu_op__imm_data__data$4$next[63:0]$9453 $1\alu_op__imm_data__data$4$next[63:0]$9437 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 $1\alu_op__imm_data__ok$5$next[0:0]$9438 + assign $2\alu_op__oe__oe$8$next[0:0]$9455 $1\alu_op__oe__oe$8$next[0:0]$9446 + assign $2\alu_op__oe__ok$9$next[0:0]$9456 $1\alu_op__oe__ok$9$next[0:0]$9447 + assign $2\alu_op__rc__ok$7$next[0:0]$9457 $1\alu_op__rc__ok$7$next[0:0]$9449 + assign $2\alu_op__rc__rc$6$next[0:0]$9458 $1\alu_op__rc__rc$6$next[0:0]$9450 end sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9369 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9370 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9371 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9372 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9373 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9374 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9375 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9376 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9377 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9378 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9379 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9380 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9381 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9382 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9383 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9384 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9385 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9386 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9417 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9418 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9419 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9420 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9421 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9422 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9423 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9424 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9425 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9426 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9427 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9428 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9429 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9430 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9431 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9432 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 end - attribute \src "libresoc.v:167504.3-167522.6" - process $proc$libresoc.v:167504$9411 + attribute \src "libresoc.v:169136.3-169154.6" + process $proc$libresoc.v:169136$9459 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$9412 $1\o$20$next[63:0]$9414 + assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 assign { } { } - assign $0\o_ok$21$next[0:0]$9413 $2\o_ok$21$next[0:0]$9416 - attribute \src "libresoc.v:167505.5-167505.29" + assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 + attribute \src "libresoc.v:169137.5-169137.29" switch \initial - attribute \src "libresoc.v:167505.9-167505.17" + attribute \src "libresoc.v:169137.9-169137.17" case 1'1 case end @@ -345584,41 +348081,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9415 $1\o$20$next[63:0]$9414 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } case - assign $1\o$20$next[63:0]$9414 \o$20 - assign $1\o_ok$21$next[0:0]$9415 \o_ok$21 + assign $1\o$20$next[63:0]$9462 \o$20 + assign $1\o_ok$21$next[0:0]$9463 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9416 1'0 + assign $2\o_ok$21$next[0:0]$9464 1'0 case - assign $2\o_ok$21$next[0:0]$9416 $1\o_ok$21$next[0:0]$9415 + assign $2\o_ok$21$next[0:0]$9464 $1\o_ok$21$next[0:0]$9463 end sync always - update \o$20$next $0\o$20$next[63:0]$9412 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9413 + update \o$20$next $0\o$20$next[63:0]$9460 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 end - attribute \src "libresoc.v:167523.3-167541.6" - process $proc$libresoc.v:167523$9417 + attribute \src "libresoc.v:169155.3-169173.6" + process $proc$libresoc.v:169155$9465 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$9418 $1\cr_a$22$next[3:0]$9420 + assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9419 $2\cr_a_ok$23$next[0:0]$9422 - attribute \src "libresoc.v:167524.5-167524.29" + assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 + attribute \src "libresoc.v:169156.5-169156.29" switch \initial - attribute \src "libresoc.v:167524.9-167524.17" + attribute \src "libresoc.v:169156.9-169156.17" case 1'1 case end @@ -345628,41 +348125,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9421 $1\cr_a$22$next[3:0]$9420 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\cr_a$22$next[3:0]$9420 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9421 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$9468 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9469 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9422 1'0 + assign $2\cr_a_ok$23$next[0:0]$9470 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9422 $1\cr_a_ok$23$next[0:0]$9421 + assign $2\cr_a_ok$23$next[0:0]$9470 $1\cr_a_ok$23$next[0:0]$9469 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9418 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9419 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 end - attribute \src "libresoc.v:167542.3-167560.6" - process $proc$libresoc.v:167542$9423 + attribute \src "libresoc.v:169174.3-169192.6" + process $proc$libresoc.v:169174$9471 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9424 $1\xer_ca$24$next[1:0]$9426 + assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9425 $2\xer_ca_ok$25$next[0:0]$9428 - attribute \src "libresoc.v:167543.5-167543.29" + assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 + attribute \src "libresoc.v:169175.5-169175.29" switch \initial - attribute \src "libresoc.v:167543.9-167543.17" + attribute \src "libresoc.v:169175.9-169175.17" case 1'1 case end @@ -345672,41 +348169,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9427 $1\xer_ca$24$next[1:0]$9426 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\xer_ca$24$next[1:0]$9426 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9427 \xer_ca_ok$25 + assign $1\xer_ca$24$next[1:0]$9474 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9475 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9428 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9476 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9428 $1\xer_ca_ok$25$next[0:0]$9427 + assign $2\xer_ca_ok$25$next[0:0]$9476 $1\xer_ca_ok$25$next[0:0]$9475 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9424 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9425 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 end - attribute \src "libresoc.v:167561.3-167579.6" - process $proc$libresoc.v:167561$9429 + attribute \src "libresoc.v:169193.3-169211.6" + process $proc$libresoc.v:169193$9477 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9430 $1\xer_ov$26$next[1:0]$9432 + assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9431 $2\xer_ov_ok$27$next[0:0]$9434 - attribute \src "libresoc.v:167562.5-167562.29" + assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 + attribute \src "libresoc.v:169194.5-169194.29" switch \initial - attribute \src "libresoc.v:167562.9-167562.17" + attribute \src "libresoc.v:169194.9-169194.17" case 1'1 case end @@ -345716,41 +348213,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9433 $1\xer_ov$26$next[1:0]$9432 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_ov$26$next[1:0]$9432 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9433 \xer_ov_ok$27 + assign $1\xer_ov$26$next[1:0]$9480 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9481 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9434 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9482 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9434 $1\xer_ov_ok$27$next[0:0]$9433 + assign $2\xer_ov_ok$27$next[0:0]$9482 $1\xer_ov_ok$27$next[0:0]$9481 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9430 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9431 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 end - attribute \src "libresoc.v:167580.3-167598.6" - process $proc$libresoc.v:167580$9435 + attribute \src "libresoc.v:169212.3-169230.6" + process $proc$libresoc.v:169212$9483 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9436 $1\xer_so$28$next[0:0]$9438 + assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9437 $2\xer_so_ok$29$next[0:0]$9440 - attribute \src "libresoc.v:167581.5-167581.29" + assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 + attribute \src "libresoc.v:169213.5-169213.29" switch \initial - attribute \src "libresoc.v:167581.9-167581.17" + attribute \src "libresoc.v:169213.9-169213.17" case 1'1 case end @@ -345760,30 +348257,30 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9439 $1\xer_so$28$next[0:0]$9438 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_so$28$next[0:0]$9438 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9439 \xer_so_ok$29 + assign $1\xer_so$28$next[0:0]$9486 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9487 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9440 1'0 + assign $2\xer_so_ok$29$next[0:0]$9488 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9440 $1\xer_so_ok$29$next[0:0]$9439 + assign $2\xer_so_ok$29$next[0:0]$9488 $1\xer_so_ok$29$next[0:0]$9487 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9436 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9437 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 end - connect \$60 $and$libresoc.v:167306$9301_Y + connect \$60 $and$libresoc.v:168938$9349_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -345804,240 +348301,240 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:167622.1-168691.10" +attribute \src "libresoc.v:169254.1-170323.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:168637.3-168655.6" - wire width 4 $0\cr_a$21$next[3:0]$9606 - attribute \src "libresoc.v:168443.3-168444.33" - wire width 4 $0\cr_a$21[3:0]$9507 - attribute \src "libresoc.v:167634.13-167634.29" - wire width 4 $0\cr_a$21[3:0]$9619 - attribute \src "libresoc.v:168637.3-168655.6" - wire $0\cr_a_ok$22$next[0:0]$9607 - attribute \src "libresoc.v:168445.3-168446.39" - wire $0\cr_a_ok$22[0:0]$9509 - attribute \src "libresoc.v:167643.7-167643.26" - wire $0\cr_a_ok$22[0:0]$9621 - attribute \src "libresoc.v:167623.7-167623.20" + attribute \src "libresoc.v:170269.3-170287.6" + wire width 4 $0\cr_a$21$next[3:0]$9654 + attribute \src "libresoc.v:170075.3-170076.33" + wire width 4 $0\cr_a$21[3:0]$9555 + attribute \src "libresoc.v:169266.13-169266.29" + wire width 4 $0\cr_a$21[3:0]$9667 + attribute \src "libresoc.v:170269.3-170287.6" + wire $0\cr_a_ok$22$next[0:0]$9655 + attribute \src "libresoc.v:170077.3-170078.39" + wire $0\cr_a_ok$22[0:0]$9557 + attribute \src "libresoc.v:169275.7-169275.26" + wire $0\cr_a_ok$22[0:0]$9669 + attribute \src "libresoc.v:169255.7-169255.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168564.3-168576.6" - wire width 2 $0\muxid$1$next[1:0]$9556 - attribute \src "libresoc.v:168485.3-168486.33" - wire width 2 $0\muxid$1[1:0]$9549 - attribute \src "libresoc.v:167654.13-167654.29" - wire width 2 $0\muxid$1[1:0]$9623 - attribute \src "libresoc.v:168618.3-168636.6" - wire width 64 $0\o$19$next[63:0]$9600 - attribute \src "libresoc.v:168447.3-168448.27" - wire width 64 $0\o$19[63:0]$9511 - attribute \src "libresoc.v:167669.14-167669.43" - wire width 64 $0\o$19[63:0]$9625 - attribute \src "libresoc.v:168618.3-168636.6" - wire $0\o_ok$20$next[0:0]$9601 - attribute \src "libresoc.v:168449.3-168450.33" - wire $0\o_ok$20[0:0]$9513 - attribute \src "libresoc.v:167678.7-167678.23" - wire $0\o_ok$20[0:0]$9627 - attribute \src "libresoc.v:168546.3-168563.6" - wire $0\r_busy$next[0:0]$9552 - attribute \src "libresoc.v:168487.3-168488.29" + attribute \src "libresoc.v:170196.3-170208.6" + wire width 2 $0\muxid$1$next[1:0]$9604 + attribute \src "libresoc.v:170117.3-170118.33" + wire width 2 $0\muxid$1[1:0]$9597 + attribute \src "libresoc.v:169286.13-169286.29" + wire width 2 $0\muxid$1[1:0]$9671 + attribute \src "libresoc.v:170250.3-170268.6" + wire width 64 $0\o$19$next[63:0]$9648 + attribute \src "libresoc.v:170079.3-170080.27" + wire width 64 $0\o$19[63:0]$9559 + attribute \src "libresoc.v:169301.14-169301.43" + wire width 64 $0\o$19[63:0]$9673 + attribute \src "libresoc.v:170250.3-170268.6" + wire $0\o_ok$20$next[0:0]$9649 + attribute \src "libresoc.v:170081.3-170082.33" + wire $0\o_ok$20[0:0]$9561 + attribute \src "libresoc.v:169310.7-169310.23" + wire $0\o_ok$20[0:0]$9675 + attribute \src "libresoc.v:170178.3-170195.6" + wire $0\r_busy$next[0:0]$9600 + attribute \src "libresoc.v:170119.3-170120.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168577.3-168617.6" - wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9559 - attribute \src "libresoc.v:168453.3-168454.51" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9517 - attribute \src "libresoc.v:168011.14-168011.43" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9630 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9560 - attribute \src "libresoc.v:168455.3-168456.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9519 - attribute \src "libresoc.v:168035.14-168035.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9632 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9561 - attribute \src "libresoc.v:168457.3-168458.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9521 - attribute \src "libresoc.v:168044.7-168044.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9634 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9562 - attribute \src "libresoc.v:168471.3-168472.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9535 - attribute \src "libresoc.v:168061.13-168061.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9636 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__input_cr$14$next[0:0]$9563 - attribute \src "libresoc.v:168475.3-168476.55" - wire $0\sr_op__input_cr$14[0:0]$9539 - attribute \src "libresoc.v:168074.7-168074.34" - wire $0\sr_op__input_cr$14[0:0]$9638 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9564 - attribute \src "libresoc.v:168483.3-168484.47" - wire width 32 $0\sr_op__insn$18[31:0]$9547 - attribute \src "libresoc.v:168083.14-168083.38" - wire width 32 $0\sr_op__insn$18[31:0]$9640 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9565 - attribute \src "libresoc.v:168451.3-168452.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9515 - attribute \src "libresoc.v:168242.13-168242.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9642 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__invert_in$11$next[0:0]$9566 - attribute \src "libresoc.v:168469.3-168470.57" - wire $0\sr_op__invert_in$11[0:0]$9533 - attribute \src "libresoc.v:168326.7-168326.35" - wire $0\sr_op__invert_in$11[0:0]$9644 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9567 - attribute \src "libresoc.v:168479.3-168480.55" - wire $0\sr_op__is_32bit$16[0:0]$9543 - attribute \src "libresoc.v:168335.7-168335.34" - wire $0\sr_op__is_32bit$16[0:0]$9646 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__is_signed$17$next[0:0]$9568 - attribute \src "libresoc.v:168481.3-168482.57" - wire $0\sr_op__is_signed$17[0:0]$9545 - attribute \src "libresoc.v:168344.7-168344.35" - wire $0\sr_op__is_signed$17[0:0]$9648 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9569 - attribute \src "libresoc.v:168463.3-168464.49" - wire $0\sr_op__oe__oe$8[0:0]$9527 - attribute \src "libresoc.v:168355.7-168355.31" - wire $0\sr_op__oe__oe$8[0:0]$9650 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9570 - attribute \src "libresoc.v:168465.3-168466.49" - wire $0\sr_op__oe__ok$9[0:0]$9529 - attribute \src "libresoc.v:168364.7-168364.31" - wire $0\sr_op__oe__ok$9[0:0]$9652 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__output_carry$13$next[0:0]$9571 - attribute \src "libresoc.v:168473.3-168474.63" - wire $0\sr_op__output_carry$13[0:0]$9537 - attribute \src "libresoc.v:168371.7-168371.38" - wire $0\sr_op__output_carry$13[0:0]$9654 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__output_cr$15$next[0:0]$9572 - attribute \src "libresoc.v:168477.3-168478.57" - wire $0\sr_op__output_cr$15[0:0]$9541 - attribute \src "libresoc.v:168380.7-168380.35" - wire $0\sr_op__output_cr$15[0:0]$9656 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9573 - attribute \src "libresoc.v:168461.3-168462.49" - wire $0\sr_op__rc__ok$7[0:0]$9525 - attribute \src "libresoc.v:168391.7-168391.31" - wire $0\sr_op__rc__ok$7[0:0]$9658 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9574 - attribute \src "libresoc.v:168459.3-168460.49" - wire $0\sr_op__rc__rc$6[0:0]$9523 - attribute \src "libresoc.v:168400.7-168400.31" - wire $0\sr_op__rc__rc$6[0:0]$9660 - attribute \src "libresoc.v:168577.3-168617.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9575 - attribute \src "libresoc.v:168467.3-168468.57" - wire $0\sr_op__write_cr0$10[0:0]$9531 - attribute \src "libresoc.v:168407.7-168407.35" - wire $0\sr_op__write_cr0$10[0:0]$9662 - attribute \src "libresoc.v:168656.3-168674.6" - wire width 2 $0\xer_ca$23$next[1:0]$9612 - attribute \src "libresoc.v:168439.3-168440.37" - wire width 2 $0\xer_ca$23[1:0]$9503 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attribute \src "libresoc.v:170085.3-170086.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 + attribute \src "libresoc.v:169643.14-169643.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 + attribute \src "libresoc.v:170087.3-170088.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 + attribute \src "libresoc.v:169667.14-169667.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 + attribute \src "libresoc.v:170089.3-170090.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9569 + attribute \src "libresoc.v:169676.7-169676.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9682 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 + attribute \src "libresoc.v:170103.3-170104.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9583 + attribute \src "libresoc.v:169693.13-169693.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9684 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__input_cr$14$next[0:0]$9611 + attribute \src "libresoc.v:170107.3-170108.55" + wire $0\sr_op__input_cr$14[0:0]$9587 + attribute \src "libresoc.v:169706.7-169706.34" + wire $0\sr_op__input_cr$14[0:0]$9686 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9612 + attribute \src "libresoc.v:170115.3-170116.47" + wire width 32 $0\sr_op__insn$18[31:0]$9595 + attribute \src "libresoc.v:169715.14-169715.38" + wire width 32 $0\sr_op__insn$18[31:0]$9688 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9613 + attribute \src "libresoc.v:170083.3-170084.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9563 + attribute \src "libresoc.v:169874.13-169874.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9690 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__invert_in$11$next[0:0]$9614 + attribute \src "libresoc.v:170101.3-170102.57" + wire $0\sr_op__invert_in$11[0:0]$9581 + attribute \src "libresoc.v:169958.7-169958.35" + wire $0\sr_op__invert_in$11[0:0]$9692 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9615 + attribute \src "libresoc.v:170111.3-170112.55" + wire $0\sr_op__is_32bit$16[0:0]$9591 + attribute \src "libresoc.v:169967.7-169967.34" + wire $0\sr_op__is_32bit$16[0:0]$9694 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__is_signed$17$next[0:0]$9616 + attribute \src "libresoc.v:170113.3-170114.57" + wire $0\sr_op__is_signed$17[0:0]$9593 + attribute \src "libresoc.v:169976.7-169976.35" + wire $0\sr_op__is_signed$17[0:0]$9696 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9617 + attribute \src "libresoc.v:170095.3-170096.49" + wire $0\sr_op__oe__oe$8[0:0]$9575 + attribute \src "libresoc.v:169987.7-169987.31" + wire $0\sr_op__oe__oe$8[0:0]$9698 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9618 + attribute \src "libresoc.v:170097.3-170098.49" + wire $0\sr_op__oe__ok$9[0:0]$9577 + attribute \src "libresoc.v:169996.7-169996.31" + wire $0\sr_op__oe__ok$9[0:0]$9700 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__output_carry$13$next[0:0]$9619 + attribute \src "libresoc.v:170105.3-170106.63" + wire $0\sr_op__output_carry$13[0:0]$9585 + attribute \src "libresoc.v:170003.7-170003.38" + wire $0\sr_op__output_carry$13[0:0]$9702 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__output_cr$15$next[0:0]$9620 + attribute \src "libresoc.v:170109.3-170110.57" + wire $0\sr_op__output_cr$15[0:0]$9589 + attribute \src "libresoc.v:170012.7-170012.35" + wire $0\sr_op__output_cr$15[0:0]$9704 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9621 + attribute \src "libresoc.v:170093.3-170094.49" + wire $0\sr_op__rc__ok$7[0:0]$9573 + attribute \src "libresoc.v:170023.7-170023.31" + wire $0\sr_op__rc__ok$7[0:0]$9706 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9622 + attribute \src "libresoc.v:170091.3-170092.49" + wire $0\sr_op__rc__rc$6[0:0]$9571 + attribute \src "libresoc.v:170032.7-170032.31" + wire $0\sr_op__rc__rc$6[0:0]$9708 + attribute \src "libresoc.v:170209.3-170249.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9623 + attribute \src "libresoc.v:170099.3-170100.57" + wire $0\sr_op__write_cr0$10[0:0]$9579 + attribute \src "libresoc.v:170039.7-170039.35" + wire $0\sr_op__write_cr0$10[0:0]$9710 + attribute \src "libresoc.v:170288.3-170306.6" + wire width 2 $0\xer_ca$23$next[1:0]$9660 + attribute \src "libresoc.v:170071.3-170072.37" + wire width 2 $0\xer_ca$23[1:0]$9551 + attribute \src "libresoc.v:170048.13-170048.31" + wire width 2 $0\xer_ca$23[1:0]$9712 + attribute \src "libresoc.v:170288.3-170306.6" + wire $0\xer_ca_ok$24$next[0:0]$9661 + attribute \src "libresoc.v:170073.3-170074.43" + wire $0\xer_ca_ok$24[0:0]$9553 + attribute \src "libresoc.v:170057.7-170057.28" + wire $0\xer_ca_ok$24[0:0]$9714 + attribute \src "libresoc.v:170269.3-170287.6" + wire width 4 $1\cr_a$21$next[3:0]$9656 + attribute \src "libresoc.v:170269.3-170287.6" + wire $1\cr_a_ok$22$next[0:0]$9657 + attribute \src "libresoc.v:170196.3-170208.6" + wire width 2 $1\muxid$1$next[1:0]$9605 + attribute \src "libresoc.v:170250.3-170268.6" + wire width 64 $1\o$19$next[63:0]$9650 + attribute \src "libresoc.v:170250.3-170268.6" + wire $1\o_ok$20$next[0:0]$9651 + attribute \src "libresoc.v:170178.3-170195.6" + wire $1\r_busy$next[0:0]$9601 + attribute \src "libresoc.v:169606.7-169606.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168577.3-168617.6" - wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9576 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9577 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9578 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9579 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__input_cr$14$next[0:0]$9580 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9581 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9582 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__invert_in$11$next[0:0]$9583 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9584 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__is_signed$17$next[0:0]$9585 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9586 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9587 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__output_carry$13$next[0:0]$9588 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__output_cr$15$next[0:0]$9589 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9590 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9591 - attribute \src "libresoc.v:168577.3-168617.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9592 - attribute \src "libresoc.v:168656.3-168674.6" - wire width 2 $1\xer_ca$23$next[1:0]$9614 - attribute \src "libresoc.v:168656.3-168674.6" - wire $1\xer_ca_ok$24$next[0:0]$9615 - attribute \src "libresoc.v:168637.3-168655.6" - wire $2\cr_a_ok$22$next[0:0]$9610 - attribute \src "libresoc.v:168618.3-168636.6" - wire $2\o_ok$20$next[0:0]$9604 - attribute \src "libresoc.v:168546.3-168563.6" - wire $2\r_busy$next[0:0]$9554 - attribute \src "libresoc.v:168577.3-168617.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9593 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9594 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9595 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9596 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9597 - attribute \src "libresoc.v:168577.3-168617.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9598 - attribute \src "libresoc.v:168656.3-168674.6" - wire $2\xer_ca_ok$24$next[0:0]$9616 - attribute \src "libresoc.v:168438.18-168438.118" - wire $and$libresoc.v:168438$9501_Y + attribute \src "libresoc.v:170209.3-170249.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9624 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9625 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9626 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9627 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__input_cr$14$next[0:0]$9628 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9629 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9630 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__invert_in$11$next[0:0]$9631 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9632 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__is_signed$17$next[0:0]$9633 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9634 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9635 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__output_carry$13$next[0:0]$9636 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__output_cr$15$next[0:0]$9637 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9638 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9639 + attribute \src "libresoc.v:170209.3-170249.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9640 + attribute \src "libresoc.v:170288.3-170306.6" + wire width 2 $1\xer_ca$23$next[1:0]$9662 + attribute \src "libresoc.v:170288.3-170306.6" + wire $1\xer_ca_ok$24$next[0:0]$9663 + attribute \src "libresoc.v:170269.3-170287.6" + wire $2\cr_a_ok$22$next[0:0]$9658 + attribute \src "libresoc.v:170250.3-170268.6" + wire $2\o_ok$20$next[0:0]$9652 + attribute \src "libresoc.v:170178.3-170195.6" + wire $2\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:170209.3-170249.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9641 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9642 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9643 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9644 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9645 + attribute \src "libresoc.v:170209.3-170249.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9646 + attribute \src "libresoc.v:170288.3-170306.6" + wire $2\xer_ca_ok$24$next[0:0]$9664 + attribute \src "libresoc.v:170070.18-170070.118" + wire $and$libresoc.v:170070$9549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 24 \cr_a @@ -346057,7 +348554,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "libresoc.v:167623.7-167623.15" + attribute \src "libresoc.v:169255.7-169255.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -346826,7 +349323,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168438$9501 + cell $and $and$libresoc.v:170070$9549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -346834,16 +349331,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:168438$9501_Y + connect \Y $and$libresoc.v:170070$9549_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168489.11-168492.4" + attribute \src "libresoc.v:170121.11-170124.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:168493.16-168541.4" + attribute \src "libresoc.v:170125.16-170173.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -346894,403 +349391,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:168542.11-168545.4" + attribute \src "libresoc.v:170174.11-170177.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167623.7-167623.20" - process $proc$libresoc.v:167623$9617 + attribute \src "libresoc.v:169255.7-169255.20" + process $proc$libresoc.v:169255$9665 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167634.13-167634.29" - process $proc$libresoc.v:167634$9618 + attribute \src "libresoc.v:169266.13-169266.29" + process $proc$libresoc.v:169266$9666 assign { } { } - assign $0\cr_a$21[3:0]$9619 4'0000 + assign $0\cr_a$21[3:0]$9667 4'0000 sync always sync init - update \cr_a$21 $0\cr_a$21[3:0]$9619 + update \cr_a$21 $0\cr_a$21[3:0]$9667 end - attribute \src "libresoc.v:167643.7-167643.26" - process $proc$libresoc.v:167643$9620 + attribute \src "libresoc.v:169275.7-169275.26" + process $proc$libresoc.v:169275$9668 assign { } { } - assign $0\cr_a_ok$22[0:0]$9621 1'0 + assign $0\cr_a_ok$22[0:0]$9669 1'0 sync always sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9621 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 end - attribute \src "libresoc.v:167654.13-167654.29" - process $proc$libresoc.v:167654$9622 + attribute \src "libresoc.v:169286.13-169286.29" + process $proc$libresoc.v:169286$9670 assign { } { } - assign $0\muxid$1[1:0]$9623 2'00 + assign $0\muxid$1[1:0]$9671 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9623 + update \muxid$1 $0\muxid$1[1:0]$9671 end - attribute \src "libresoc.v:167669.14-167669.43" - process $proc$libresoc.v:167669$9624 + attribute \src "libresoc.v:169301.14-169301.43" + process $proc$libresoc.v:169301$9672 assign { } { } - assign $0\o$19[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9625 + update \o$19 $0\o$19[63:0]$9673 end - attribute \src "libresoc.v:167678.7-167678.23" - process $proc$libresoc.v:167678$9626 + attribute \src "libresoc.v:169310.7-169310.23" + process $proc$libresoc.v:169310$9674 assign { } { } - assign $0\o_ok$20[0:0]$9627 1'0 + assign $0\o_ok$20[0:0]$9675 1'0 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9627 + update \o_ok$20 $0\o_ok$20[0:0]$9675 end - attribute \src "libresoc.v:167974.7-167974.20" - process $proc$libresoc.v:167974$9628 + attribute \src "libresoc.v:169606.7-169606.20" + process $proc$libresoc.v:169606$9676 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168011.14-168011.43" - process $proc$libresoc.v:168011$9629 + attribute \src "libresoc.v:169643.14-169643.43" + process $proc$libresoc.v:169643$9677 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9630 14'00000000000000 + assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9630 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 end - attribute \src "libresoc.v:168035.14-168035.62" - process $proc$libresoc.v:168035$9631 + attribute \src "libresoc.v:169667.14-169667.62" + process $proc$libresoc.v:169667$9679 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9632 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9632 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 end - attribute \src "libresoc.v:168044.7-168044.37" - process $proc$libresoc.v:168044$9633 + attribute \src "libresoc.v:169676.7-169676.37" + process $proc$libresoc.v:169676$9681 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9634 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9634 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 end - attribute \src "libresoc.v:168061.13-168061.43" - process $proc$libresoc.v:168061$9635 + attribute \src "libresoc.v:169693.13-169693.43" + process $proc$libresoc.v:169693$9683 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9636 2'00 + assign $0\sr_op__input_carry$12[1:0]$9684 2'00 sync always sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9636 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 end - attribute \src "libresoc.v:168074.7-168074.34" - process $proc$libresoc.v:168074$9637 + attribute \src "libresoc.v:169706.7-169706.34" + process $proc$libresoc.v:169706$9685 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9638 1'0 + assign $0\sr_op__input_cr$14[0:0]$9686 1'0 sync always sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9638 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 end - attribute \src "libresoc.v:168083.14-168083.38" - process $proc$libresoc.v:168083$9639 + attribute \src "libresoc.v:169715.14-169715.38" + process $proc$libresoc.v:169715$9687 assign { } { } - assign $0\sr_op__insn$18[31:0]$9640 0 + assign $0\sr_op__insn$18[31:0]$9688 0 sync always sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9640 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 end - attribute \src "libresoc.v:168242.13-168242.41" - process $proc$libresoc.v:168242$9641 + attribute \src "libresoc.v:169874.13-169874.41" + process $proc$libresoc.v:169874$9689 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9642 7'0000000 + assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9642 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 end - attribute \src "libresoc.v:168326.7-168326.35" - process $proc$libresoc.v:168326$9643 + attribute \src "libresoc.v:169958.7-169958.35" + process $proc$libresoc.v:169958$9691 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9644 1'0 + assign $0\sr_op__invert_in$11[0:0]$9692 1'0 sync always sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9644 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 end - attribute \src "libresoc.v:168335.7-168335.34" - process $proc$libresoc.v:168335$9645 + attribute \src "libresoc.v:169967.7-169967.34" + process $proc$libresoc.v:169967$9693 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9646 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9646 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 end - attribute \src "libresoc.v:168344.7-168344.35" - process $proc$libresoc.v:168344$9647 + attribute \src "libresoc.v:169976.7-169976.35" + process $proc$libresoc.v:169976$9695 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9648 1'0 + assign $0\sr_op__is_signed$17[0:0]$9696 1'0 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9648 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 end - attribute \src "libresoc.v:168355.7-168355.31" - process $proc$libresoc.v:168355$9649 + attribute \src "libresoc.v:169987.7-169987.31" + process $proc$libresoc.v:169987$9697 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9650 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9650 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 end - attribute \src "libresoc.v:168364.7-168364.31" - process $proc$libresoc.v:168364$9651 + attribute \src "libresoc.v:169996.7-169996.31" + process $proc$libresoc.v:169996$9699 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9652 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9652 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 end - attribute \src "libresoc.v:168371.7-168371.38" - process $proc$libresoc.v:168371$9653 + attribute \src "libresoc.v:170003.7-170003.38" + process $proc$libresoc.v:170003$9701 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9654 1'0 + assign $0\sr_op__output_carry$13[0:0]$9702 1'0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9654 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 end - attribute \src "libresoc.v:168380.7-168380.35" - process $proc$libresoc.v:168380$9655 + attribute \src "libresoc.v:170012.7-170012.35" + process $proc$libresoc.v:170012$9703 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9656 1'0 + assign $0\sr_op__output_cr$15[0:0]$9704 1'0 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9656 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 end - attribute \src "libresoc.v:168391.7-168391.31" - process $proc$libresoc.v:168391$9657 + attribute \src "libresoc.v:170023.7-170023.31" + process $proc$libresoc.v:170023$9705 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9658 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9658 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 end - attribute \src "libresoc.v:168400.7-168400.31" - process $proc$libresoc.v:168400$9659 + attribute \src "libresoc.v:170032.7-170032.31" + process $proc$libresoc.v:170032$9707 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9660 1'0 + assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9660 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 end - attribute \src "libresoc.v:168407.7-168407.35" - process $proc$libresoc.v:168407$9661 + attribute \src "libresoc.v:170039.7-170039.35" + process $proc$libresoc.v:170039$9709 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9662 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9662 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 end - attribute \src "libresoc.v:168416.13-168416.31" - process $proc$libresoc.v:168416$9663 + attribute \src "libresoc.v:170048.13-170048.31" + process $proc$libresoc.v:170048$9711 assign { } { } - assign $0\xer_ca$23[1:0]$9664 2'00 + assign $0\xer_ca$23[1:0]$9712 2'00 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9664 + update \xer_ca$23 $0\xer_ca$23[1:0]$9712 end - attribute \src "libresoc.v:168425.7-168425.28" - process $proc$libresoc.v:168425$9665 + attribute \src "libresoc.v:170057.7-170057.28" + process $proc$libresoc.v:170057$9713 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9666 1'0 + assign $0\xer_ca_ok$24[0:0]$9714 1'0 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9666 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 end - attribute \src "libresoc.v:168439.3-168440.37" - process $proc$libresoc.v:168439$9502 + attribute \src "libresoc.v:170071.3-170072.37" + process $proc$libresoc.v:170071$9550 assign { } { } - assign $0\xer_ca$23[1:0]$9503 \xer_ca$23$next + assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9503 + update \xer_ca$23 $0\xer_ca$23[1:0]$9551 end - attribute \src "libresoc.v:168441.3-168442.43" - process $proc$libresoc.v:168441$9504 + attribute \src "libresoc.v:170073.3-170074.43" + process $proc$libresoc.v:170073$9552 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9505 \xer_ca_ok$24$next + assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9505 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 end - attribute \src "libresoc.v:168443.3-168444.33" - process $proc$libresoc.v:168443$9506 + attribute \src "libresoc.v:170075.3-170076.33" + process $proc$libresoc.v:170075$9554 assign { } { } - assign $0\cr_a$21[3:0]$9507 \cr_a$21$next + assign $0\cr_a$21[3:0]$9555 \cr_a$21$next sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9507 + update \cr_a$21 $0\cr_a$21[3:0]$9555 end - attribute \src "libresoc.v:168445.3-168446.39" - process $proc$libresoc.v:168445$9508 + attribute \src "libresoc.v:170077.3-170078.39" + process $proc$libresoc.v:170077$9556 assign { } { } - assign $0\cr_a_ok$22[0:0]$9509 \cr_a_ok$22$next + assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9509 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 end - attribute \src "libresoc.v:168447.3-168448.27" - process $proc$libresoc.v:168447$9510 + attribute \src "libresoc.v:170079.3-170080.27" + process $proc$libresoc.v:170079$9558 assign { } { } - assign $0\o$19[63:0]$9511 \o$19$next + assign $0\o$19[63:0]$9559 \o$19$next sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9511 + update \o$19 $0\o$19[63:0]$9559 end - attribute \src "libresoc.v:168449.3-168450.33" - process $proc$libresoc.v:168449$9512 + attribute \src "libresoc.v:170081.3-170082.33" + process $proc$libresoc.v:170081$9560 assign { } { } - assign $0\o_ok$20[0:0]$9513 \o_ok$20$next + assign $0\o_ok$20[0:0]$9561 \o_ok$20$next sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9513 + update \o_ok$20 $0\o_ok$20[0:0]$9561 end - attribute \src "libresoc.v:168451.3-168452.55" - process $proc$libresoc.v:168451$9514 + attribute \src "libresoc.v:170083.3-170084.55" + process $proc$libresoc.v:170083$9562 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9515 \sr_op__insn_type$2$next + assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9515 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 end - attribute \src "libresoc.v:168453.3-168454.51" - process $proc$libresoc.v:168453$9516 + attribute \src "libresoc.v:170085.3-170086.51" + process $proc$libresoc.v:170085$9564 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9517 \sr_op__fn_unit$3$next + assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9517 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 end - attribute \src "libresoc.v:168455.3-168456.65" - process $proc$libresoc.v:168455$9518 + attribute \src "libresoc.v:170087.3-170088.65" + process $proc$libresoc.v:170087$9566 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9519 \sr_op__imm_data__data$4$next + assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9519 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 end - attribute \src "libresoc.v:168457.3-168458.61" - process $proc$libresoc.v:168457$9520 + attribute \src "libresoc.v:170089.3-170090.61" + process $proc$libresoc.v:170089$9568 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9521 \sr_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9521 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 end - attribute \src "libresoc.v:168459.3-168460.49" - process $proc$libresoc.v:168459$9522 + attribute \src "libresoc.v:170091.3-170092.49" + process $proc$libresoc.v:170091$9570 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9523 \sr_op__rc__rc$6$next + assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9523 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 end - attribute \src "libresoc.v:168461.3-168462.49" - process $proc$libresoc.v:168461$9524 + attribute \src "libresoc.v:170093.3-170094.49" + process $proc$libresoc.v:170093$9572 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9525 \sr_op__rc__ok$7$next + assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9525 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 end - attribute \src "libresoc.v:168463.3-168464.49" - process $proc$libresoc.v:168463$9526 + attribute \src "libresoc.v:170095.3-170096.49" + process $proc$libresoc.v:170095$9574 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9527 \sr_op__oe__oe$8$next + assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9527 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 end - attribute \src "libresoc.v:168465.3-168466.49" - process $proc$libresoc.v:168465$9528 + attribute \src "libresoc.v:170097.3-170098.49" + process $proc$libresoc.v:170097$9576 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9529 \sr_op__oe__ok$9$next + assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9529 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 end - attribute \src "libresoc.v:168467.3-168468.57" - process $proc$libresoc.v:168467$9530 + attribute \src "libresoc.v:170099.3-170100.57" + process $proc$libresoc.v:170099$9578 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9531 \sr_op__write_cr0$10$next + assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9531 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 end - attribute \src "libresoc.v:168469.3-168470.57" - process $proc$libresoc.v:168469$9532 + attribute \src "libresoc.v:170101.3-170102.57" + process $proc$libresoc.v:170101$9580 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9533 \sr_op__invert_in$11$next + assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9533 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 end - attribute \src "libresoc.v:168471.3-168472.61" - process $proc$libresoc.v:168471$9534 + attribute \src "libresoc.v:170103.3-170104.61" + process $proc$libresoc.v:170103$9582 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9535 \sr_op__input_carry$12$next + assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9535 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 end - attribute \src "libresoc.v:168473.3-168474.63" - process $proc$libresoc.v:168473$9536 + attribute \src "libresoc.v:170105.3-170106.63" + process $proc$libresoc.v:170105$9584 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9537 \sr_op__output_carry$13$next + assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9537 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 end - attribute \src "libresoc.v:168475.3-168476.55" - process $proc$libresoc.v:168475$9538 + attribute \src "libresoc.v:170107.3-170108.55" + process $proc$libresoc.v:170107$9586 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9539 \sr_op__input_cr$14$next + assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9539 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 end - attribute \src "libresoc.v:168477.3-168478.57" - process $proc$libresoc.v:168477$9540 + attribute \src "libresoc.v:170109.3-170110.57" + process $proc$libresoc.v:170109$9588 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9541 \sr_op__output_cr$15$next + assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9541 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 end - attribute \src "libresoc.v:168479.3-168480.55" - process $proc$libresoc.v:168479$9542 + attribute \src "libresoc.v:170111.3-170112.55" + process $proc$libresoc.v:170111$9590 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9543 \sr_op__is_32bit$16$next + assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9543 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 end - attribute \src "libresoc.v:168481.3-168482.57" - process $proc$libresoc.v:168481$9544 + attribute \src "libresoc.v:170113.3-170114.57" + process $proc$libresoc.v:170113$9592 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9545 \sr_op__is_signed$17$next + assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9545 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 end - attribute \src "libresoc.v:168483.3-168484.47" - process $proc$libresoc.v:168483$9546 + attribute \src "libresoc.v:170115.3-170116.47" + process $proc$libresoc.v:170115$9594 assign { } { } - assign $0\sr_op__insn$18[31:0]$9547 \sr_op__insn$18$next + assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9547 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 end - attribute \src "libresoc.v:168485.3-168486.33" - process $proc$libresoc.v:168485$9548 + attribute \src "libresoc.v:170117.3-170118.33" + process $proc$libresoc.v:170117$9596 assign { } { } - assign $0\muxid$1[1:0]$9549 \muxid$1$next + assign $0\muxid$1[1:0]$9597 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9549 + update \muxid$1 $0\muxid$1[1:0]$9597 end - attribute \src "libresoc.v:168487.3-168488.29" - process $proc$libresoc.v:168487$9550 + attribute \src "libresoc.v:170119.3-170120.29" + process $proc$libresoc.v:170119$9598 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168546.3-168563.6" - process $proc$libresoc.v:168546$9551 + attribute \src "libresoc.v:170178.3-170195.6" + process $proc$libresoc.v:170178$9599 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9552 $2\r_busy$next[0:0]$9554 - attribute \src "libresoc.v:168547.5-168547.29" + assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:170179.5-170179.29" switch \initial - attribute \src "libresoc.v:168547.9-168547.17" + attribute \src "libresoc.v:170179.9-170179.17" case 1'1 case end @@ -347299,34 +349796,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9553 1'1 + assign $1\r_busy$next[0:0]$9601 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9553 1'0 + assign $1\r_busy$next[0:0]$9601 1'0 case - assign $1\r_busy$next[0:0]$9553 \r_busy + assign $1\r_busy$next[0:0]$9601 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9554 1'0 + assign $2\r_busy$next[0:0]$9602 1'0 case - assign $2\r_busy$next[0:0]$9554 $1\r_busy$next[0:0]$9553 + assign $2\r_busy$next[0:0]$9602 $1\r_busy$next[0:0]$9601 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9552 + update \r_busy$next $0\r_busy$next[0:0]$9600 end - attribute \src "libresoc.v:168564.3-168576.6" - process $proc$libresoc.v:168564$9555 + attribute \src "libresoc.v:170196.3-170208.6" + process $proc$libresoc.v:170196$9603 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9556 $1\muxid$1$next[1:0]$9557 - attribute \src "libresoc.v:168565.5-168565.29" + assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 + attribute \src "libresoc.v:170197.5-170197.29" switch \initial - attribute \src "libresoc.v:168565.9-168565.17" + attribute \src "libresoc.v:170197.9-170197.17" case 1'1 case end @@ -347335,19 +349832,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9557 \muxid$53 + assign $1\muxid$1$next[1:0]$9605 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9557 \muxid$53 + assign $1\muxid$1$next[1:0]$9605 \muxid$53 case - assign $1\muxid$1$next[1:0]$9557 \muxid$1 + assign $1\muxid$1$next[1:0]$9605 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9556 + update \muxid$1$next $0\muxid$1$next[1:0]$9604 end - attribute \src "libresoc.v:168577.3-168617.6" - process $proc$libresoc.v:168577$9558 + attribute \src "libresoc.v:170209.3-170249.6" + process $proc$libresoc.v:170209$9606 assign { } { } assign { } { } assign { } { } @@ -347382,32 +349879,32 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[13:0]$9559 $1\sr_op__fn_unit$3$next[13:0]$9576 + assign $0\sr_op__fn_unit$3$next[13:0]$9607 $1\sr_op__fn_unit$3$next[13:0]$9624 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9562 $1\sr_op__input_carry$12$next[1:0]$9579 - assign $0\sr_op__input_cr$14$next[0:0]$9563 $1\sr_op__input_cr$14$next[0:0]$9580 - assign $0\sr_op__insn$18$next[31:0]$9564 $1\sr_op__insn$18$next[31:0]$9581 - assign $0\sr_op__insn_type$2$next[6:0]$9565 $1\sr_op__insn_type$2$next[6:0]$9582 - assign $0\sr_op__invert_in$11$next[0:0]$9566 $1\sr_op__invert_in$11$next[0:0]$9583 - assign $0\sr_op__is_32bit$16$next[0:0]$9567 $1\sr_op__is_32bit$16$next[0:0]$9584 - assign $0\sr_op__is_signed$17$next[0:0]$9568 $1\sr_op__is_signed$17$next[0:0]$9585 + assign $0\sr_op__input_carry$12$next[1:0]$9610 $1\sr_op__input_carry$12$next[1:0]$9627 + assign $0\sr_op__input_cr$14$next[0:0]$9611 $1\sr_op__input_cr$14$next[0:0]$9628 + assign $0\sr_op__insn$18$next[31:0]$9612 $1\sr_op__insn$18$next[31:0]$9629 + assign $0\sr_op__insn_type$2$next[6:0]$9613 $1\sr_op__insn_type$2$next[6:0]$9630 + assign $0\sr_op__invert_in$11$next[0:0]$9614 $1\sr_op__invert_in$11$next[0:0]$9631 + assign $0\sr_op__is_32bit$16$next[0:0]$9615 $1\sr_op__is_32bit$16$next[0:0]$9632 + assign $0\sr_op__is_signed$17$next[0:0]$9616 $1\sr_op__is_signed$17$next[0:0]$9633 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9571 $1\sr_op__output_carry$13$next[0:0]$9588 - assign $0\sr_op__output_cr$15$next[0:0]$9572 $1\sr_op__output_cr$15$next[0:0]$9589 + assign $0\sr_op__output_carry$13$next[0:0]$9619 $1\sr_op__output_carry$13$next[0:0]$9636 + assign $0\sr_op__output_cr$15$next[0:0]$9620 $1\sr_op__output_cr$15$next[0:0]$9637 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9575 $1\sr_op__write_cr0$10$next[0:0]$9592 - assign $0\sr_op__imm_data__data$4$next[63:0]$9560 $2\sr_op__imm_data__data$4$next[63:0]$9593 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9561 $2\sr_op__imm_data__ok$5$next[0:0]$9594 - assign $0\sr_op__oe__oe$8$next[0:0]$9569 $2\sr_op__oe__oe$8$next[0:0]$9595 - assign $0\sr_op__oe__ok$9$next[0:0]$9570 $2\sr_op__oe__ok$9$next[0:0]$9596 - assign $0\sr_op__rc__ok$7$next[0:0]$9573 $2\sr_op__rc__ok$7$next[0:0]$9597 - assign $0\sr_op__rc__rc$6$next[0:0]$9574 $2\sr_op__rc__rc$6$next[0:0]$9598 - attribute \src "libresoc.v:168578.5-168578.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9623 $1\sr_op__write_cr0$10$next[0:0]$9640 + assign $0\sr_op__imm_data__data$4$next[63:0]$9608 $2\sr_op__imm_data__data$4$next[63:0]$9641 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9609 $2\sr_op__imm_data__ok$5$next[0:0]$9642 + assign $0\sr_op__oe__oe$8$next[0:0]$9617 $2\sr_op__oe__oe$8$next[0:0]$9643 + assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 + assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 + assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 + attribute \src "libresoc.v:170210.5-170210.29" switch \initial - attribute \src "libresoc.v:168578.9-168578.17" + attribute \src "libresoc.v:170210.9-170210.17" case 1'1 case end @@ -347432,7 +349929,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -347452,25 +349949,25 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9581 $1\sr_op__is_signed$17$next[0:0]$9585 $1\sr_op__is_32bit$16$next[0:0]$9584 $1\sr_op__output_cr$15$next[0:0]$9589 $1\sr_op__input_cr$14$next[0:0]$9580 $1\sr_op__output_carry$13$next[0:0]$9588 $1\sr_op__input_carry$12$next[1:0]$9579 $1\sr_op__invert_in$11$next[0:0]$9583 $1\sr_op__write_cr0$10$next[0:0]$9592 $1\sr_op__oe__ok$9$next[0:0]$9587 $1\sr_op__oe__oe$8$next[0:0]$9586 $1\sr_op__rc__ok$7$next[0:0]$9590 $1\sr_op__rc__rc$6$next[0:0]$9591 $1\sr_op__imm_data__ok$5$next[0:0]$9578 $1\sr_op__imm_data__data$4$next[63:0]$9577 $1\sr_op__fn_unit$3$next[13:0]$9576 $1\sr_op__insn_type$2$next[6:0]$9582 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\sr_op__fn_unit$3$next[13:0]$9576 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9577 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9578 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9579 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9580 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9581 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9582 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9583 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9584 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9585 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9586 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9587 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9588 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9589 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9590 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9591 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9592 \sr_op__write_cr0$10 + assign $1\sr_op__fn_unit$3$next[13:0]$9624 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9625 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9626 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9627 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9628 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9629 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9630 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9631 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9632 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9633 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9634 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9635 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9636 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9637 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9638 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9639 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9640 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -347482,51 +349979,51 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9593 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9598 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9597 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9595 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9596 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9593 $1\sr_op__imm_data__data$4$next[63:0]$9577 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9594 $1\sr_op__imm_data__ok$5$next[0:0]$9578 - assign $2\sr_op__oe__oe$8$next[0:0]$9595 $1\sr_op__oe__oe$8$next[0:0]$9586 - assign $2\sr_op__oe__ok$9$next[0:0]$9596 $1\sr_op__oe__ok$9$next[0:0]$9587 - assign $2\sr_op__rc__ok$7$next[0:0]$9597 $1\sr_op__rc__ok$7$next[0:0]$9590 - assign $2\sr_op__rc__rc$6$next[0:0]$9598 $1\sr_op__rc__rc$6$next[0:0]$9591 + assign $2\sr_op__imm_data__data$4$next[63:0]$9641 $1\sr_op__imm_data__data$4$next[63:0]$9625 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 $1\sr_op__imm_data__ok$5$next[0:0]$9626 + assign $2\sr_op__oe__oe$8$next[0:0]$9643 $1\sr_op__oe__oe$8$next[0:0]$9634 + assign $2\sr_op__oe__ok$9$next[0:0]$9644 $1\sr_op__oe__ok$9$next[0:0]$9635 + assign $2\sr_op__rc__ok$7$next[0:0]$9645 $1\sr_op__rc__ok$7$next[0:0]$9638 + assign $2\sr_op__rc__rc$6$next[0:0]$9646 $1\sr_op__rc__rc$6$next[0:0]$9639 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9559 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9560 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9561 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9562 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9563 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9564 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9565 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9566 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9567 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9568 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9569 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9570 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9571 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9572 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9573 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9574 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9575 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9607 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9608 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9609 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9610 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9611 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9612 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9613 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9614 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9615 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9616 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9617 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9618 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9619 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9620 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9621 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 end - attribute \src "libresoc.v:168618.3-168636.6" - process $proc$libresoc.v:168618$9599 + attribute \src "libresoc.v:170250.3-170268.6" + process $proc$libresoc.v:170250$9647 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$19$next[63:0]$9600 $1\o$19$next[63:0]$9602 + assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 assign { } { } - assign $0\o_ok$20$next[0:0]$9601 $2\o_ok$20$next[0:0]$9604 - attribute \src "libresoc.v:168619.5-168619.29" + assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 + attribute \src "libresoc.v:170251.5-170251.29" switch \initial - attribute \src "libresoc.v:168619.9-168619.17" + attribute \src "libresoc.v:170251.9-170251.17" case 1'1 case end @@ -347536,41 +350033,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9603 $1\o$19$next[63:0]$9602 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } case - assign $1\o$19$next[63:0]$9602 \o$19 - assign $1\o_ok$20$next[0:0]$9603 \o_ok$20 + assign $1\o$19$next[63:0]$9650 \o$19 + assign $1\o_ok$20$next[0:0]$9651 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$20$next[0:0]$9604 1'0 + assign $2\o_ok$20$next[0:0]$9652 1'0 case - assign $2\o_ok$20$next[0:0]$9604 $1\o_ok$20$next[0:0]$9603 + assign $2\o_ok$20$next[0:0]$9652 $1\o_ok$20$next[0:0]$9651 end sync always - update \o$19$next $0\o$19$next[63:0]$9600 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9601 + update \o$19$next $0\o$19$next[63:0]$9648 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 end - attribute \src "libresoc.v:168637.3-168655.6" - process $proc$libresoc.v:168637$9605 + attribute \src "libresoc.v:170269.3-170287.6" + process $proc$libresoc.v:170269$9653 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$21$next[3:0]$9606 $1\cr_a$21$next[3:0]$9608 + assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9607 $2\cr_a_ok$22$next[0:0]$9610 - attribute \src "libresoc.v:168638.5-168638.29" + assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 + attribute \src "libresoc.v:170270.5-170270.29" switch \initial - attribute \src "libresoc.v:168638.9-168638.17" + attribute \src "libresoc.v:170270.9-170270.17" case 1'1 case end @@ -347580,41 +350077,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9609 $1\cr_a$21$next[3:0]$9608 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$21$next[3:0]$9608 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9609 \cr_a_ok$22 + assign $1\cr_a$21$next[3:0]$9656 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9657 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9610 1'0 + assign $2\cr_a_ok$22$next[0:0]$9658 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9610 $1\cr_a_ok$22$next[0:0]$9609 + assign $2\cr_a_ok$22$next[0:0]$9658 $1\cr_a_ok$22$next[0:0]$9657 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9606 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9607 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 end - attribute \src "libresoc.v:168656.3-168674.6" - process $proc$libresoc.v:168656$9611 + attribute \src "libresoc.v:170288.3-170306.6" + process $proc$libresoc.v:170288$9659 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$23$next[1:0]$9612 $1\xer_ca$23$next[1:0]$9614 + assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9613 $2\xer_ca_ok$24$next[0:0]$9616 - attribute \src "libresoc.v:168657.5-168657.29" + assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 + attribute \src "libresoc.v:170289.5-170289.29" switch \initial - attribute \src "libresoc.v:168657.9-168657.17" + attribute \src "libresoc.v:170289.9-170289.17" case 1'1 case end @@ -347624,30 +350121,30 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9615 $1\xer_ca$23$next[1:0]$9614 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_ca$23$next[1:0]$9614 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9615 \xer_ca_ok$24 + assign $1\xer_ca$23$next[1:0]$9662 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9663 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9616 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9664 1'0 case - assign $2\xer_ca_ok$24$next[0:0]$9616 $1\xer_ca_ok$24$next[0:0]$9615 + assign $2\xer_ca_ok$24$next[0:0]$9664 $1\xer_ca_ok$24$next[0:0]$9663 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9612 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9613 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 end - connect \$51 $and$libresoc.v:168438$9501_Y + connect \$51 $and$libresoc.v:170070$9549_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -347665,200 +350162,200 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:168695.1-169659.10" +attribute \src "libresoc.v:170327.1-171291.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:169565.3-169583.6" - wire width 64 $0\fast1$11$next[63:0]$9735 - attribute \src "libresoc.v:169414.3-169415.35" - wire width 64 $0\fast1$11[63:0]$9673 - attribute \src "libresoc.v:168707.14-168707.47" - wire width 64 $0\fast1$11[63:0]$9759 - attribute \src "libresoc.v:169565.3-169583.6" - wire $0\fast1_ok$next[0:0]$9734 - attribute \src "libresoc.v:169416.3-169417.33" + attribute \src "libresoc.v:171197.3-171215.6" + wire width 64 $0\fast1$11$next[63:0]$9783 + attribute \src "libresoc.v:171052.3-171053.35" + wire width 64 $0\fast1$11[63:0]$9724 + attribute \src "libresoc.v:170339.14-170339.47" + wire width 64 $0\fast1$11[63:0]$9807 + attribute \src "libresoc.v:171197.3-171215.6" + wire $0\fast1_ok$next[0:0]$9782 + attribute \src "libresoc.v:171054.3-171055.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:169584.3-169602.6" - wire width 64 $0\fast2$12$next[63:0]$9741 - attribute \src "libresoc.v:169410.3-169411.35" - wire width 64 $0\fast2$12[63:0]$9670 - attribute \src "libresoc.v:168723.14-168723.47" - wire width 64 $0\fast2$12[63:0]$9762 - attribute \src "libresoc.v:169584.3-169602.6" - wire $0\fast2_ok$next[0:0]$9740 - attribute \src "libresoc.v:169412.3-169413.33" + attribute \src "libresoc.v:171216.3-171234.6" + wire width 64 $0\fast2$12$next[63:0]$9789 + attribute \src "libresoc.v:171048.3-171049.35" + wire width 64 $0\fast2$12[63:0]$9721 + attribute \src "libresoc.v:170355.14-170355.47" + wire width 64 $0\fast2$12[63:0]$9810 + attribute \src "libresoc.v:171216.3-171234.6" + wire $0\fast2_ok$next[0:0]$9788 + attribute \src "libresoc.v:171050.3-171051.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:168696.7-168696.20" + attribute \src "libresoc.v:170328.7-170328.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169622.3-169640.6" - wire width 64 $0\msr$next[63:0]$9752 - attribute \src "libresoc.v:169444.3-169445.23" + attribute \src "libresoc.v:171254.3-171272.6" + wire width 64 $0\msr$next[63:0]$9800 + attribute \src "libresoc.v:171040.3-171041.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:169622.3-169640.6" - wire $0\msr_ok$next[0:0]$9753 - attribute \src "libresoc.v:169446.3-169447.29" + attribute \src "libresoc.v:171254.3-171272.6" + wire $0\msr_ok$next[0:0]$9801 + attribute \src "libresoc.v:171042.3-171043.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:169512.3-169524.6" - wire width 2 $0\muxid$1$next[1:0]$9706 - attribute \src "libresoc.v:169440.3-169441.33" - wire width 2 $0\muxid$1[1:0]$9696 - attribute \src "libresoc.v:169001.13-169001.29" - wire width 2 $0\muxid$1[1:0]$9767 - attribute \src "libresoc.v:169603.3-169621.6" - wire width 64 $0\nia$next[63:0]$9746 - attribute \src "libresoc.v:169448.3-169449.23" + attribute \src "libresoc.v:171144.3-171156.6" + wire width 2 $0\muxid$1$next[1:0]$9754 + attribute \src "libresoc.v:171078.3-171079.33" + wire width 2 $0\muxid$1[1:0]$9747 + attribute \src "libresoc.v:170633.13-170633.29" + wire width 2 $0\muxid$1[1:0]$9815 + attribute \src "libresoc.v:171235.3-171253.6" + wire width 64 $0\nia$next[63:0]$9794 + attribute \src "libresoc.v:171044.3-171045.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:169603.3-169621.6" - wire $0\nia_ok$next[0:0]$9747 - attribute \src "libresoc.v:169408.3-169409.29" + attribute \src "libresoc.v:171235.3-171253.6" + wire $0\nia_ok$next[0:0]$9795 + attribute \src "libresoc.v:171046.3-171047.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:169546.3-169564.6" - wire width 64 $0\o$next[63:0]$9728 - attribute \src "libresoc.v:169418.3-169419.19" + attribute \src "libresoc.v:171178.3-171196.6" + wire width 64 $0\o$next[63:0]$9776 + attribute \src "libresoc.v:171056.3-171057.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:169546.3-169564.6" - wire $0\o_ok$next[0:0]$9729 - attribute \src "libresoc.v:169420.3-169421.25" + attribute \src "libresoc.v:171178.3-171196.6" + wire $0\o_ok$next[0:0]$9777 + attribute \src "libresoc.v:171058.3-171059.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:169494.3-169511.6" - wire $0\r_busy$next[0:0]$9702 - attribute \src "libresoc.v:169442.3-169443.29" + attribute \src "libresoc.v:171126.3-171143.6" + wire $0\r_busy$next[0:0]$9750 + attribute \src "libresoc.v:171080.3-171081.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169525.3-169545.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9709 - attribute \src "libresoc.v:169430.3-169431.47" - wire width 64 $0\trap_op__cia$6[63:0]$9686 - attribute \src "libresoc.v:169062.14-169062.53" - wire width 64 $0\trap_op__cia$6[63:0]$9774 - attribute \src "libresoc.v:169525.3-169545.6" - wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9710 - attribute \src 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$0\trap_op__traptype$8$next[7:0]$9717 - attribute \src "libresoc.v:169434.3-169435.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9690 - attribute \src "libresoc.v:169404.13-169404.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9790 - attribute \src "libresoc.v:169565.3-169583.6" - wire width 64 $1\fast1$11$next[63:0]$9737 - attribute \src "libresoc.v:169565.3-169583.6" - wire $1\fast1_ok$next[0:0]$9736 - attribute \src "libresoc.v:168714.7-168714.22" + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9757 + attribute \src "libresoc.v:171068.3-171069.47" + wire width 64 $0\trap_op__cia$6[63:0]$9737 + attribute \src "libresoc.v:170694.14-170694.53" + wire width 64 $0\trap_op__cia$6[63:0]$9822 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 + attribute \src "libresoc.v:171062.3-171063.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 + attribute \src "libresoc.v:170731.14-170731.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9759 + attribute \src "libresoc.v:171064.3-171065.49" + wire width 32 $0\trap_op__insn$4[31:0]$9733 + attribute \src "libresoc.v:170757.14-170757.39" + wire width 32 $0\trap_op__insn$4[31:0]$9826 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 + attribute \src "libresoc.v:171060.3-171061.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9729 + attribute \src "libresoc.v:170914.13-170914.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9828 + attribute \src "libresoc.v:171157.3-171177.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9761 + attribute \src "libresoc.v:171070.3-171071.57" + wire $0\trap_op__is_32bit$7[0:0]$9739 + attribute \src "libresoc.v:171000.7-171000.35" + wire $0\trap_op__is_32bit$7[0:0]$9830 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9762 + attribute \src "libresoc.v:171076.3-171077.59" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9745 + attribute \src "libresoc.v:171007.13-171007.43" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9832 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$9763 + attribute \src "libresoc.v:171066.3-171067.47" + wire width 64 $0\trap_op__msr$5[63:0]$9735 + attribute \src "libresoc.v:171018.14-171018.53" + wire width 64 $0\trap_op__msr$5[63:0]$9834 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9764 + attribute \src "libresoc.v:171074.3-171075.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 + attribute \src "libresoc.v:171027.14-171027.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9836 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $0\trap_op__traptype$8$next[7:0]$9765 + attribute \src "libresoc.v:171072.3-171073.57" + wire width 8 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wire $2\fast1_ok$next[0:0]$9738 - attribute \src "libresoc.v:169584.3-169602.6" - wire $2\fast2_ok$next[0:0]$9744 - attribute \src "libresoc.v:169622.3-169640.6" - wire $2\msr_ok$next[0:0]$9756 - attribute \src "libresoc.v:169603.3-169621.6" - wire $2\nia_ok$next[0:0]$9750 - attribute \src "libresoc.v:169546.3-169564.6" - wire $2\o_ok$next[0:0]$9732 - attribute \src "libresoc.v:169494.3-169511.6" - wire $2\r_busy$next[0:0]$9704 - attribute \src "libresoc.v:169407.18-169407.118" - wire $and$libresoc.v:169407$9667_Y + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$9766 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9767 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$9768 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$9769 + attribute \src "libresoc.v:171157.3-171177.6" + wire $1\trap_op__is_32bit$7$next[0:0]$9770 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9771 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$9772 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9773 + attribute \src "libresoc.v:171157.3-171177.6" + wire width 8 $1\trap_op__traptype$8$next[7:0]$9774 + attribute \src "libresoc.v:171197.3-171215.6" + wire $2\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:171216.3-171234.6" + wire $2\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:171254.3-171272.6" + wire $2\msr_ok$next[0:0]$9804 + attribute \src "libresoc.v:171235.3-171253.6" + wire $2\nia_ok$next[0:0]$9798 + attribute \src "libresoc.v:171178.3-171196.6" + wire $2\o_ok$next[0:0]$9780 + attribute \src "libresoc.v:171126.3-171143.6" + wire $2\r_busy$next[0:0]$9752 + attribute \src "libresoc.v:171039.18-171039.118" + wire $and$libresoc.v:171039$9715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 @@ -347888,7 +350385,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:168696.7-168696.15" + attribute \src "libresoc.v:170328.7-170328.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -348547,7 +351044,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:169407$9667 + cell $and $and$libresoc.v:171039$9715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -348555,10 +351052,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:169407$9667_Y + connect \Y $and$libresoc.v:171039$9715_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:169450.13-169485.4" + attribute \src "libresoc.v:171082.13-171117.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -348596,349 +351093,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:169486.10-169489.4" + attribute \src "libresoc.v:171118.10-171121.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169490.10-169493.4" + attribute \src "libresoc.v:171122.10-171125.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168696.7-168696.20" - process $proc$libresoc.v:168696$9757 + attribute \src "libresoc.v:170328.7-170328.20" + process $proc$libresoc.v:170328$9805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168707.14-168707.47" - process $proc$libresoc.v:168707$9758 + attribute \src "libresoc.v:170339.14-170339.47" + process $proc$libresoc.v:170339$9806 assign { } { } - assign $0\fast1$11[63:0]$9759 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9759 + update \fast1$11 $0\fast1$11[63:0]$9807 end - attribute \src "libresoc.v:168714.7-168714.22" - process $proc$libresoc.v:168714$9760 + attribute \src "libresoc.v:170346.7-170346.22" + process $proc$libresoc.v:170346$9808 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:168723.14-168723.47" - process $proc$libresoc.v:168723$9761 + attribute \src "libresoc.v:170355.14-170355.47" + process $proc$libresoc.v:170355$9809 assign { } { } - assign $0\fast2$12[63:0]$9762 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9762 + update \fast2$12 $0\fast2$12[63:0]$9810 end - attribute \src "libresoc.v:168730.7-168730.22" - process $proc$libresoc.v:168730$9763 + attribute \src "libresoc.v:170362.7-170362.22" + process $proc$libresoc.v:170362$9811 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:168985.14-168985.40" - process $proc$libresoc.v:168985$9764 + attribute \src "libresoc.v:170617.14-170617.40" + process $proc$libresoc.v:170617$9812 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:168992.7-168992.20" - process $proc$libresoc.v:168992$9765 + attribute \src "libresoc.v:170624.7-170624.20" + process $proc$libresoc.v:170624$9813 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:169001.13-169001.29" - process $proc$libresoc.v:169001$9766 + attribute \src "libresoc.v:170633.13-170633.29" + process $proc$libresoc.v:170633$9814 assign { } { } - assign $0\muxid$1[1:0]$9767 2'00 + assign $0\muxid$1[1:0]$9815 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9767 + update \muxid$1 $0\muxid$1[1:0]$9815 end - attribute \src "libresoc.v:169014.14-169014.40" - process $proc$libresoc.v:169014$9768 + attribute \src "libresoc.v:170646.14-170646.40" + process $proc$libresoc.v:170646$9816 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:169021.7-169021.20" - process $proc$libresoc.v:169021$9769 + attribute \src "libresoc.v:170653.7-170653.20" + process $proc$libresoc.v:170653$9817 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:169028.14-169028.38" - process $proc$libresoc.v:169028$9770 + attribute \src "libresoc.v:170660.14-170660.38" + process $proc$libresoc.v:170660$9818 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:169035.7-169035.18" - process $proc$libresoc.v:169035$9771 + attribute \src "libresoc.v:170667.7-170667.18" + process $proc$libresoc.v:170667$9819 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:169049.7-169049.20" - process $proc$libresoc.v:169049$9772 + attribute \src "libresoc.v:170681.7-170681.20" + process $proc$libresoc.v:170681$9820 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169062.14-169062.53" - process $proc$libresoc.v:169062$9773 + attribute \src "libresoc.v:170694.14-170694.53" + process $proc$libresoc.v:170694$9821 assign { } { } - assign $0\trap_op__cia$6[63:0]$9774 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9774 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 end - attribute \src "libresoc.v:169099.14-169099.45" - process $proc$libresoc.v:169099$9775 + attribute \src "libresoc.v:170731.14-170731.45" + process $proc$libresoc.v:170731$9823 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9776 14'00000000000000 + assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9776 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 end - attribute \src "libresoc.v:169125.14-169125.39" - process $proc$libresoc.v:169125$9777 + attribute \src "libresoc.v:170757.14-170757.39" + process $proc$libresoc.v:170757$9825 assign { } { } - assign $0\trap_op__insn$4[31:0]$9778 0 + assign $0\trap_op__insn$4[31:0]$9826 0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9778 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 end - attribute \src "libresoc.v:169282.13-169282.43" - process $proc$libresoc.v:169282$9779 + attribute \src "libresoc.v:170914.13-170914.43" + process $proc$libresoc.v:170914$9827 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9780 7'0000000 + assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9780 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 end - attribute \src "libresoc.v:169368.7-169368.35" - process $proc$libresoc.v:169368$9781 + attribute \src "libresoc.v:171000.7-171000.35" + process $proc$libresoc.v:171000$9829 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9782 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9782 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 end - attribute \src "libresoc.v:169375.13-169375.43" - process $proc$libresoc.v:169375$9783 + attribute \src "libresoc.v:171007.13-171007.43" + process $proc$libresoc.v:171007$9831 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9784 8'00000000 + assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9784 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 end - attribute \src "libresoc.v:169386.14-169386.53" - process $proc$libresoc.v:169386$9785 + attribute \src "libresoc.v:171018.14-171018.53" + process $proc$libresoc.v:171018$9833 assign { } { } - assign $0\trap_op__msr$5[63:0]$9786 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9786 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 end - attribute \src "libresoc.v:169395.14-169395.46" - process $proc$libresoc.v:169395$9787 + attribute \src "libresoc.v:171027.14-171027.46" + process $proc$libresoc.v:171027$9835 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9788 13'0000000000000 + assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9788 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 end - attribute \src "libresoc.v:169404.13-169404.42" - process $proc$libresoc.v:169404$9789 + attribute \src "libresoc.v:171036.13-171036.42" + process $proc$libresoc.v:171036$9837 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9790 8'00000000 + assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9790 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 end - attribute \src "libresoc.v:169408.3-169409.29" - process $proc$libresoc.v:169408$9668 + attribute \src "libresoc.v:171040.3-171041.23" + process $proc$libresoc.v:171040$9716 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:171042.3-171043.29" + process $proc$libresoc.v:171042$9717 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:171044.3-171045.23" + process $proc$libresoc.v:171044$9718 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:171046.3-171047.29" + process $proc$libresoc.v:171046$9719 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:169410.3-169411.35" - process $proc$libresoc.v:169410$9669 + attribute \src "libresoc.v:171048.3-171049.35" + process $proc$libresoc.v:171048$9720 assign { } { } - assign $0\fast2$12[63:0]$9670 \fast2$12$next + assign $0\fast2$12[63:0]$9721 \fast2$12$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9670 + update \fast2$12 $0\fast2$12[63:0]$9721 end - attribute \src "libresoc.v:169412.3-169413.33" - process $proc$libresoc.v:169412$9671 + attribute \src "libresoc.v:171050.3-171051.33" + process $proc$libresoc.v:171050$9722 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:169414.3-169415.35" - process $proc$libresoc.v:169414$9672 + attribute \src "libresoc.v:171052.3-171053.35" + process $proc$libresoc.v:171052$9723 assign { } { } - assign $0\fast1$11[63:0]$9673 \fast1$11$next + assign $0\fast1$11[63:0]$9724 \fast1$11$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9673 + update \fast1$11 $0\fast1$11[63:0]$9724 end - attribute \src "libresoc.v:169416.3-169417.33" - process $proc$libresoc.v:169416$9674 + attribute \src "libresoc.v:171054.3-171055.33" + process $proc$libresoc.v:171054$9725 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:169418.3-169419.19" - process $proc$libresoc.v:169418$9675 + attribute \src "libresoc.v:171056.3-171057.19" + process $proc$libresoc.v:171056$9726 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:169420.3-169421.25" - process $proc$libresoc.v:169420$9676 + attribute \src "libresoc.v:171058.3-171059.25" + process $proc$libresoc.v:171058$9727 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:169422.3-169423.59" - process $proc$libresoc.v:169422$9677 + attribute \src "libresoc.v:171060.3-171061.59" + process $proc$libresoc.v:171060$9728 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9678 \trap_op__insn_type$2$next + assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9678 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 end - attribute \src "libresoc.v:169424.3-169425.55" - process $proc$libresoc.v:169424$9679 + attribute \src "libresoc.v:171062.3-171063.55" + process $proc$libresoc.v:171062$9730 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9680 \trap_op__fn_unit$3$next + assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9680 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 end - attribute \src "libresoc.v:169426.3-169427.49" - process $proc$libresoc.v:169426$9681 + attribute \src "libresoc.v:171064.3-171065.49" + process $proc$libresoc.v:171064$9732 assign { } { } - assign $0\trap_op__insn$4[31:0]$9682 \trap_op__insn$4$next + assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9682 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 end - attribute \src "libresoc.v:169428.3-169429.47" - process $proc$libresoc.v:169428$9683 + attribute \src "libresoc.v:171066.3-171067.47" + process $proc$libresoc.v:171066$9734 assign { } { } - assign $0\trap_op__msr$5[63:0]$9684 \trap_op__msr$5$next + assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9684 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 end - attribute \src "libresoc.v:169430.3-169431.47" - process $proc$libresoc.v:169430$9685 + attribute \src "libresoc.v:171068.3-171069.47" + process $proc$libresoc.v:171068$9736 assign { } { } - assign $0\trap_op__cia$6[63:0]$9686 \trap_op__cia$6$next + assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9686 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 end - attribute \src "libresoc.v:169432.3-169433.57" - process $proc$libresoc.v:169432$9687 + attribute \src "libresoc.v:171070.3-171071.57" + process $proc$libresoc.v:171070$9738 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9688 \trap_op__is_32bit$7$next + assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9688 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 end - attribute \src "libresoc.v:169434.3-169435.57" - process $proc$libresoc.v:169434$9689 + attribute \src "libresoc.v:171072.3-171073.57" + process $proc$libresoc.v:171072$9740 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9690 \trap_op__traptype$8$next + assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9690 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 end - attribute \src "libresoc.v:169436.3-169437.57" - process $proc$libresoc.v:169436$9691 + attribute \src "libresoc.v:171074.3-171075.57" + process $proc$libresoc.v:171074$9742 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9692 \trap_op__trapaddr$9$next + assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9692 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 end - attribute \src "libresoc.v:169438.3-169439.59" - process $proc$libresoc.v:169438$9693 + attribute \src "libresoc.v:171076.3-171077.59" + process $proc$libresoc.v:171076$9744 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9694 \trap_op__ldst_exc$10$next + assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9694 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 end - attribute \src "libresoc.v:169440.3-169441.33" - process $proc$libresoc.v:169440$9695 + attribute \src "libresoc.v:171078.3-171079.33" + process $proc$libresoc.v:171078$9746 assign { } { } - assign $0\muxid$1[1:0]$9696 \muxid$1$next + assign $0\muxid$1[1:0]$9747 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9696 + update \muxid$1 $0\muxid$1[1:0]$9747 end - attribute \src "libresoc.v:169442.3-169443.29" - process $proc$libresoc.v:169442$9697 + attribute \src "libresoc.v:171080.3-171081.29" + process $proc$libresoc.v:171080$9748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169444.3-169445.23" - process $proc$libresoc.v:169444$9698 - assign { } { } - assign $0\msr[63:0] \msr$next - sync posedge \coresync_clk - update \msr $0\msr[63:0] - end - attribute \src "libresoc.v:169446.3-169447.29" - process $proc$libresoc.v:169446$9699 + attribute \src "libresoc.v:171126.3-171143.6" + process $proc$libresoc.v:171126$9749 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next - sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "libresoc.v:169448.3-169449.23" - process $proc$libresoc.v:169448$9700 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:169494.3-169511.6" - process $proc$libresoc.v:169494$9701 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9702 $2\r_busy$next[0:0]$9704 - attribute \src "libresoc.v:169495.5-169495.29" + assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 + attribute \src "libresoc.v:171127.5-171127.29" switch \initial - attribute \src "libresoc.v:169495.9-169495.17" + attribute \src "libresoc.v:171127.9-171127.17" case 1'1 case end @@ -348947,34 +351444,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9703 1'1 + assign $1\r_busy$next[0:0]$9751 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9703 1'0 + assign $1\r_busy$next[0:0]$9751 1'0 case - assign $1\r_busy$next[0:0]$9703 \r_busy + assign $1\r_busy$next[0:0]$9751 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9704 1'0 + assign $2\r_busy$next[0:0]$9752 1'0 case - assign $2\r_busy$next[0:0]$9704 $1\r_busy$next[0:0]$9703 + assign $2\r_busy$next[0:0]$9752 $1\r_busy$next[0:0]$9751 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9702 + update \r_busy$next $0\r_busy$next[0:0]$9750 end - attribute \src "libresoc.v:169512.3-169524.6" - process $proc$libresoc.v:169512$9705 + attribute \src "libresoc.v:171144.3-171156.6" + process $proc$libresoc.v:171144$9753 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9706 $1\muxid$1$next[1:0]$9707 - attribute \src "libresoc.v:169513.5-169513.29" + assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 + attribute \src "libresoc.v:171145.5-171145.29" switch \initial - attribute \src "libresoc.v:169513.9-169513.17" + attribute \src "libresoc.v:171145.9-171145.17" case 1'1 case end @@ -348983,19 +351480,19 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9707 \muxid$28 + assign $1\muxid$1$next[1:0]$9755 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9707 \muxid$28 + assign $1\muxid$1$next[1:0]$9755 \muxid$28 case - assign $1\muxid$1$next[1:0]$9707 \muxid$1 + assign $1\muxid$1$next[1:0]$9755 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9706 + update \muxid$1$next $0\muxid$1$next[1:0]$9754 end - attribute \src "libresoc.v:169525.3-169545.6" - process $proc$libresoc.v:169525$9708 + attribute \src "libresoc.v:171157.3-171177.6" + process $proc$libresoc.v:171157$9756 assign { } { } assign { } { } assign { } { } @@ -349014,18 +351511,18 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9709 $1\trap_op__cia$6$next[63:0]$9718 - assign $0\trap_op__fn_unit$3$next[13:0]$9710 $1\trap_op__fn_unit$3$next[13:0]$9719 - assign $0\trap_op__insn$4$next[31:0]$9711 $1\trap_op__insn$4$next[31:0]$9720 - assign $0\trap_op__insn_type$2$next[6:0]$9712 $1\trap_op__insn_type$2$next[6:0]$9721 - assign $0\trap_op__is_32bit$7$next[0:0]$9713 $1\trap_op__is_32bit$7$next[0:0]$9722 - assign $0\trap_op__ldst_exc$10$next[7:0]$9714 $1\trap_op__ldst_exc$10$next[7:0]$9723 - assign $0\trap_op__msr$5$next[63:0]$9715 $1\trap_op__msr$5$next[63:0]$9724 - assign $0\trap_op__trapaddr$9$next[12:0]$9716 $1\trap_op__trapaddr$9$next[12:0]$9725 - assign $0\trap_op__traptype$8$next[7:0]$9717 $1\trap_op__traptype$8$next[7:0]$9726 - attribute \src "libresoc.v:169526.5-169526.29" + assign $0\trap_op__cia$6$next[63:0]$9757 $1\trap_op__cia$6$next[63:0]$9766 + assign $0\trap_op__fn_unit$3$next[13:0]$9758 $1\trap_op__fn_unit$3$next[13:0]$9767 + assign $0\trap_op__insn$4$next[31:0]$9759 $1\trap_op__insn$4$next[31:0]$9768 + assign $0\trap_op__insn_type$2$next[6:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9769 + assign $0\trap_op__is_32bit$7$next[0:0]$9761 $1\trap_op__is_32bit$7$next[0:0]$9770 + assign $0\trap_op__ldst_exc$10$next[7:0]$9762 $1\trap_op__ldst_exc$10$next[7:0]$9771 + assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 + assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 + assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 + attribute \src "libresoc.v:171158.5-171158.29" switch \initial - attribute \src "libresoc.v:169526.9-169526.17" + attribute \src "libresoc.v:171158.9-171158.17" case 1'1 case end @@ -349042,7 +351539,7 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -349054,41 +351551,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9723 $1\trap_op__trapaddr$9$next[12:0]$9725 $1\trap_op__traptype$8$next[7:0]$9726 $1\trap_op__is_32bit$7$next[0:0]$9722 $1\trap_op__cia$6$next[63:0]$9718 $1\trap_op__msr$5$next[63:0]$9724 $1\trap_op__insn$4$next[31:0]$9720 $1\trap_op__fn_unit$3$next[13:0]$9719 $1\trap_op__insn_type$2$next[6:0]$9721 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $1\trap_op__cia$6$next[63:0]$9718 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[13:0]$9719 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9720 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9721 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9722 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9723 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9724 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9725 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9726 \trap_op__traptype$8 + assign $1\trap_op__cia$6$next[63:0]$9766 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9767 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9768 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9769 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9770 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9771 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9772 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9773 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9774 \trap_op__traptype$8 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9709 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9710 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9711 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9712 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9713 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9714 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9715 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9716 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9717 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9757 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9758 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9759 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9760 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9761 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9762 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9763 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 end - attribute \src "libresoc.v:169546.3-169564.6" - process $proc$libresoc.v:169546$9727 + attribute \src "libresoc.v:171178.3-171196.6" + process $proc$libresoc.v:171178$9775 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9728 $1\o$next[63:0]$9730 + assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 assign { } { } - assign $0\o_ok$next[0:0]$9729 $2\o_ok$next[0:0]$9732 - attribute \src "libresoc.v:169547.5-169547.29" + assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 + attribute \src "libresoc.v:171179.5-171179.29" switch \initial - attribute \src "libresoc.v:169547.9-169547.17" + attribute \src "libresoc.v:171179.9-171179.17" case 1'1 case end @@ -349098,41 +351595,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9731 $1\o$next[63:0]$9730 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } case - assign $1\o$next[63:0]$9730 \o - assign $1\o_ok$next[0:0]$9731 \o_ok + assign $1\o$next[63:0]$9778 \o + assign $1\o_ok$next[0:0]$9779 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9732 1'0 + assign $2\o_ok$next[0:0]$9780 1'0 case - assign $2\o_ok$next[0:0]$9732 $1\o_ok$next[0:0]$9731 + assign $2\o_ok$next[0:0]$9780 $1\o_ok$next[0:0]$9779 end sync always - update \o$next $0\o$next[63:0]$9728 - update \o_ok$next $0\o_ok$next[0:0]$9729 + update \o$next $0\o$next[63:0]$9776 + update \o_ok$next $0\o_ok$next[0:0]$9777 end - attribute \src "libresoc.v:169565.3-169583.6" - process $proc$libresoc.v:169565$9733 + attribute \src "libresoc.v:171197.3-171215.6" + process $proc$libresoc.v:171197$9781 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$11$next[63:0]$9735 $1\fast1$11$next[63:0]$9737 - assign $0\fast1_ok$next[0:0]$9734 $2\fast1_ok$next[0:0]$9738 - attribute \src "libresoc.v:169566.5-169566.29" + assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 + assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:171198.5-171198.29" switch \initial - attribute \src "libresoc.v:169566.9-169566.17" + attribute \src "libresoc.v:171198.9-171198.17" case 1'1 case end @@ -349142,41 +351639,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9736 $1\fast1$11$next[63:0]$9737 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } case - assign $1\fast1_ok$next[0:0]$9736 \fast1_ok - assign $1\fast1$11$next[63:0]$9737 \fast1$11 + assign $1\fast1_ok$next[0:0]$9784 \fast1_ok + assign $1\fast1$11$next[63:0]$9785 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9738 1'0 + assign $2\fast1_ok$next[0:0]$9786 1'0 case - assign $2\fast1_ok$next[0:0]$9738 $1\fast1_ok$next[0:0]$9736 + assign $2\fast1_ok$next[0:0]$9786 $1\fast1_ok$next[0:0]$9784 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9734 - update \fast1$11$next $0\fast1$11$next[63:0]$9735 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 + update \fast1$11$next $0\fast1$11$next[63:0]$9783 end - attribute \src "libresoc.v:169584.3-169602.6" - process $proc$libresoc.v:169584$9739 + attribute \src "libresoc.v:171216.3-171234.6" + process $proc$libresoc.v:171216$9787 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$12$next[63:0]$9741 $1\fast2$12$next[63:0]$9743 - assign $0\fast2_ok$next[0:0]$9740 $2\fast2_ok$next[0:0]$9744 - attribute \src "libresoc.v:169585.5-169585.29" + assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 + assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:171217.5-171217.29" switch \initial - attribute \src "libresoc.v:169585.9-169585.17" + attribute \src "libresoc.v:171217.9-171217.17" case 1'1 case end @@ -349186,41 +351683,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9742 $1\fast2$12$next[63:0]$9743 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } case - assign $1\fast2_ok$next[0:0]$9742 \fast2_ok - assign $1\fast2$12$next[63:0]$9743 \fast2$12 + assign $1\fast2_ok$next[0:0]$9790 \fast2_ok + assign $1\fast2$12$next[63:0]$9791 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9744 1'0 + assign $2\fast2_ok$next[0:0]$9792 1'0 case - assign $2\fast2_ok$next[0:0]$9744 $1\fast2_ok$next[0:0]$9742 + assign $2\fast2_ok$next[0:0]$9792 $1\fast2_ok$next[0:0]$9790 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9740 - update \fast2$12$next $0\fast2$12$next[63:0]$9741 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 + update \fast2$12$next $0\fast2$12$next[63:0]$9789 end - attribute \src "libresoc.v:169603.3-169621.6" - process $proc$libresoc.v:169603$9745 + attribute \src "libresoc.v:171235.3-171253.6" + process $proc$libresoc.v:171235$9793 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9746 $1\nia$next[63:0]$9748 + assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 assign { } { } - assign $0\nia_ok$next[0:0]$9747 $2\nia_ok$next[0:0]$9750 - attribute \src "libresoc.v:169604.5-169604.29" + assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 + attribute \src "libresoc.v:171236.5-171236.29" switch \initial - attribute \src "libresoc.v:169604.9-169604.17" + attribute \src "libresoc.v:171236.9-171236.17" case 1'1 case end @@ -349230,41 +351727,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9749 $1\nia$next[63:0]$9748 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } case - assign $1\nia$next[63:0]$9748 \nia - assign $1\nia_ok$next[0:0]$9749 \nia_ok + assign $1\nia$next[63:0]$9796 \nia + assign $1\nia_ok$next[0:0]$9797 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9750 1'0 + assign $2\nia_ok$next[0:0]$9798 1'0 case - assign $2\nia_ok$next[0:0]$9750 $1\nia_ok$next[0:0]$9749 + assign $2\nia_ok$next[0:0]$9798 $1\nia_ok$next[0:0]$9797 end sync always - update \nia$next $0\nia$next[63:0]$9746 - update \nia_ok$next $0\nia_ok$next[0:0]$9747 + update \nia$next $0\nia$next[63:0]$9794 + update \nia_ok$next $0\nia_ok$next[0:0]$9795 end - attribute \src "libresoc.v:169622.3-169640.6" - process $proc$libresoc.v:169622$9751 + attribute \src "libresoc.v:171254.3-171272.6" + process $proc$libresoc.v:171254$9799 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9752 $1\msr$next[63:0]$9754 + assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 assign { } { } - assign $0\msr_ok$next[0:0]$9753 $2\msr_ok$next[0:0]$9756 - attribute \src "libresoc.v:169623.5-169623.29" + assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 + attribute \src "libresoc.v:171255.5-171255.29" switch \initial - attribute \src "libresoc.v:169623.9-169623.17" + attribute \src "libresoc.v:171255.9-171255.17" case 1'1 case end @@ -349274,30 +351771,30 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9755 $1\msr$next[63:0]$9754 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } case - assign $1\msr$next[63:0]$9754 \msr - assign $1\msr_ok$next[0:0]$9755 \msr_ok + assign $1\msr$next[63:0]$9802 \msr + assign $1\msr_ok$next[0:0]$9803 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9756 1'0 + assign $2\msr_ok$next[0:0]$9804 1'0 case - assign $2\msr_ok$next[0:0]$9756 $1\msr_ok$next[0:0]$9755 + assign $2\msr_ok$next[0:0]$9804 $1\msr_ok$next[0:0]$9803 end sync always - update \msr$next $0\msr$next[63:0]$9752 - update \msr_ok$next $0\msr_ok$next[0:0]$9753 + update \msr$next $0\msr$next[63:0]$9800 + update \msr_ok$next $0\msr_ok$next[0:0]$9801 end - connect \$26 $and$libresoc.v:169407$9667_Y + connect \$26 $and$libresoc.v:171039$9715_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -349317,266 +351814,266 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:169663.1-171166.10" +attribute \src "libresoc.v:171295.1-172798.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:171004.3-171022.6" - wire width 4 $0\cr_a$next[3:0]$9847 - attribute \src "libresoc.v:170823.3-170824.25" + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $0\cr_a$next[3:0]$9895 + attribute \src "libresoc.v:172455.3-172456.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $0\cr_a_ok$next[0:0]$9848 - attribute \src "libresoc.v:170825.3-170826.31" + attribute \src "libresoc.v:172636.3-172654.6" + wire $0\cr_a_ok$next[0:0]$9896 + attribute \src "libresoc.v:172457.3-172458.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:169664.7-169664.20" + attribute \src "libresoc.v:171296.7-171296.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171092.3-171133.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9872 - attribute \src "libresoc.v:170863.3-170864.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9834 - attribute \src "libresoc.v:169705.13-169705.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9918 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9873 - attribute \src "libresoc.v:170833.3-170834.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9804 - attribute \src "libresoc.v:169744.14-169744.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9920 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9874 - attribute \src "libresoc.v:170835.3-170836.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9806 - attribute \src "libresoc.v:169768.14-169768.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9922 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9875 - attribute \src "libresoc.v:170837.3-170838.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9808 - attribute \src "libresoc.v:169777.7-169777.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9924 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9876 - attribute \src "libresoc.v:170851.3-170852.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9822 - attribute \src "libresoc.v:169794.13-169794.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9926 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9877 - attribute \src "libresoc.v:170865.3-170866.57" - wire width 32 $0\logical_op__insn$19[31:0]$9836 - attribute \src "libresoc.v:169807.14-169807.43" - wire width 32 $0\logical_op__insn$19[31:0]$9928 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9878 - attribute \src "libresoc.v:170831.3-170832.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9802 - attribute \src "libresoc.v:169966.13-169966.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9930 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__invert_in$10$next[0:0]$9879 - attribute \src "libresoc.v:170847.3-170848.67" - wire $0\logical_op__invert_in$10[0:0]$9818 - attribute \src "libresoc.v:170050.7-170050.40" - wire $0\logical_op__invert_in$10[0:0]$9932 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__invert_out$13$next[0:0]$9880 - attribute \src "libresoc.v:170853.3-170854.69" - wire $0\logical_op__invert_out$13[0:0]$9824 - attribute \src "libresoc.v:170059.7-170059.41" - wire $0\logical_op__invert_out$13[0:0]$9934 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9881 - attribute \src "libresoc.v:170859.3-170860.65" - wire $0\logical_op__is_32bit$16[0:0]$9830 - attribute \src "libresoc.v:170068.7-170068.39" - wire $0\logical_op__is_32bit$16[0:0]$9936 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__is_signed$17$next[0:0]$9882 - attribute \src "libresoc.v:170861.3-170862.67" - wire $0\logical_op__is_signed$17[0:0]$9832 - attribute \src "libresoc.v:170077.7-170077.40" - wire $0\logical_op__is_signed$17[0:0]$9938 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9883 - attribute \src "libresoc.v:170843.3-170844.59" - wire $0\logical_op__oe__oe$8[0:0]$9814 - attribute \src "libresoc.v:170086.7-170086.36" - wire $0\logical_op__oe__oe$8[0:0]$9940 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9884 - attribute \src "libresoc.v:170845.3-170846.59" - wire $0\logical_op__oe__ok$9[0:0]$9816 - attribute \src "libresoc.v:170097.7-170097.36" - wire $0\logical_op__oe__ok$9[0:0]$9942 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__output_carry$15$next[0:0]$9885 - attribute \src "libresoc.v:170857.3-170858.73" - wire $0\logical_op__output_carry$15[0:0]$9828 - attribute \src "libresoc.v:170104.7-170104.43" - wire $0\logical_op__output_carry$15[0:0]$9944 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9886 - attribute \src "libresoc.v:170841.3-170842.59" - wire $0\logical_op__rc__ok$7[0:0]$9812 - attribute \src "libresoc.v:170113.7-170113.36" - wire $0\logical_op__rc__ok$7[0:0]$9946 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9887 - attribute \src "libresoc.v:170839.3-170840.59" - wire $0\logical_op__rc__rc$6[0:0]$9810 - attribute \src "libresoc.v:170122.7-170122.36" - wire $0\logical_op__rc__rc$6[0:0]$9948 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9888 - attribute \src "libresoc.v:170855.3-170856.67" - wire $0\logical_op__write_cr0$14[0:0]$9826 - attribute \src "libresoc.v:170131.7-170131.40" - wire $0\logical_op__write_cr0$14[0:0]$9950 - attribute \src "libresoc.v:171092.3-171133.6" - wire $0\logical_op__zero_a$11$next[0:0]$9889 - attribute \src "libresoc.v:170849.3-170850.61" - wire $0\logical_op__zero_a$11[0:0]$9820 - attribute \src "libresoc.v:170140.7-170140.37" - wire $0\logical_op__zero_a$11[0:0]$9952 - attribute \src "libresoc.v:171079.3-171091.6" - wire width 2 $0\muxid$1$next[1:0]$9869 - attribute \src "libresoc.v:170867.3-170868.33" - wire width 2 $0\muxid$1[1:0]$9838 - attribute \src "libresoc.v:170149.13-170149.29" - wire width 2 $0\muxid$1[1:0]$9954 - attribute \src "libresoc.v:170985.3-171003.6" - wire width 64 $0\o$next[63:0]$9841 - attribute \src "libresoc.v:170827.3-170828.19" + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 + attribute \src "libresoc.v:172495.3-172496.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9882 + attribute \src "libresoc.v:171337.13-171337.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9966 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 + attribute \src "libresoc.v:172465.3-172466.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 + attribute \src "libresoc.v:171376.14-171376.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 + attribute \src "libresoc.v:172467.3-172468.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 + attribute \src "libresoc.v:171400.14-171400.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 + attribute \src "libresoc.v:172469.3-172470.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9856 + attribute \src "libresoc.v:171409.7-171409.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9972 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 + attribute \src "libresoc.v:172483.3-172484.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9870 + attribute \src "libresoc.v:171426.13-171426.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9974 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9925 + attribute \src "libresoc.v:172497.3-172498.57" + wire width 32 $0\logical_op__insn$19[31:0]$9884 + attribute \src "libresoc.v:171439.14-171439.43" + wire width 32 $0\logical_op__insn$19[31:0]$9976 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 + attribute \src "libresoc.v:172463.3-172464.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9850 + attribute \src "libresoc.v:171598.13-171598.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9978 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_in$10$next[0:0]$9927 + attribute \src "libresoc.v:172479.3-172480.67" + wire $0\logical_op__invert_in$10[0:0]$9866 + attribute \src "libresoc.v:171682.7-171682.40" + wire $0\logical_op__invert_in$10[0:0]$9980 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__invert_out$13$next[0:0]$9928 + attribute \src "libresoc.v:172485.3-172486.69" + wire $0\logical_op__invert_out$13[0:0]$9872 + attribute \src "libresoc.v:171691.7-171691.41" + wire $0\logical_op__invert_out$13[0:0]$9982 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9929 + attribute \src "libresoc.v:172491.3-172492.65" + wire $0\logical_op__is_32bit$16[0:0]$9878 + attribute \src "libresoc.v:171700.7-171700.39" + wire $0\logical_op__is_32bit$16[0:0]$9984 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__is_signed$17$next[0:0]$9930 + attribute \src "libresoc.v:172493.3-172494.67" + wire $0\logical_op__is_signed$17[0:0]$9880 + attribute \src "libresoc.v:171709.7-171709.40" + wire $0\logical_op__is_signed$17[0:0]$9986 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9931 + attribute \src "libresoc.v:172475.3-172476.59" + wire $0\logical_op__oe__oe$8[0:0]$9862 + attribute \src "libresoc.v:171718.7-171718.36" + wire $0\logical_op__oe__oe$8[0:0]$9988 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9932 + attribute \src "libresoc.v:172477.3-172478.59" + wire $0\logical_op__oe__ok$9[0:0]$9864 + attribute \src "libresoc.v:171729.7-171729.36" + wire $0\logical_op__oe__ok$9[0:0]$9990 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__output_carry$15$next[0:0]$9933 + attribute \src "libresoc.v:172489.3-172490.73" + wire $0\logical_op__output_carry$15[0:0]$9876 + attribute \src "libresoc.v:171736.7-171736.43" + wire $0\logical_op__output_carry$15[0:0]$9992 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9934 + attribute \src "libresoc.v:172473.3-172474.59" + wire $0\logical_op__rc__ok$7[0:0]$9860 + attribute \src "libresoc.v:171745.7-171745.36" + wire $0\logical_op__rc__ok$7[0:0]$9994 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9935 + attribute \src "libresoc.v:172471.3-172472.59" + wire $0\logical_op__rc__rc$6[0:0]$9858 + attribute \src "libresoc.v:171754.7-171754.36" + wire $0\logical_op__rc__rc$6[0:0]$9996 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9936 + attribute \src "libresoc.v:172487.3-172488.67" + wire $0\logical_op__write_cr0$14[0:0]$9874 + attribute \src "libresoc.v:171763.7-171763.40" + wire $0\logical_op__write_cr0$14[0:0]$9998 + attribute \src "libresoc.v:172724.3-172765.6" + wire $0\logical_op__zero_a$11$next[0:0]$9937 + attribute \src "libresoc.v:171772.7-171772.37" + wire $0\logical_op__zero_a$11[0:0]$10000 + attribute \src "libresoc.v:172481.3-172482.61" + wire $0\logical_op__zero_a$11[0:0]$9868 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $0\muxid$1$next[1:0]$9917 + attribute \src "libresoc.v:171781.13-171781.29" + wire width 2 $0\muxid$1[1:0]$10002 + attribute \src "libresoc.v:172499.3-172500.33" + wire width 2 $0\muxid$1[1:0]$9886 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $0\o$next[63:0]$9889 + attribute \src "libresoc.v:172459.3-172460.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:170985.3-171003.6" - wire $0\o_ok$next[0:0]$9842 - attribute \src "libresoc.v:170829.3-170830.25" + attribute \src "libresoc.v:172617.3-172635.6" + wire $0\o_ok$next[0:0]$9890 + attribute \src "libresoc.v:172461.3-172462.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:171061.3-171078.6" - wire $0\r_busy$next[0:0]$9865 - attribute \src "libresoc.v:170869.3-170870.29" + attribute \src "libresoc.v:172693.3-172710.6" + wire $0\r_busy$next[0:0]$9913 + attribute \src "libresoc.v:172501.3-172502.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire width 2 $0\xer_ov$next[1:0]$9853 - attribute \src "libresoc.v:170819.3-170820.29" + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $0\xer_ov$next[1:0]$9901 + attribute \src "libresoc.v:172451.3-172452.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire $0\xer_ov_ok$next[0:0]$9854 - attribute \src "libresoc.v:170821.3-170822.35" + attribute \src "libresoc.v:172655.3-172673.6" + wire $0\xer_ov_ok$next[0:0]$9902 + attribute \src "libresoc.v:172453.3-172454.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:171042.3-171060.6" - wire $0\xer_so$20$next[0:0]$9860 - attribute \src "libresoc.v:170815.3-170816.37" - wire $0\xer_so$20[0:0]$9793 - attribute \src "libresoc.v:170800.7-170800.25" - wire $0\xer_so$20[0:0]$9961 - attribute \src "libresoc.v:171042.3-171060.6" - wire $0\xer_so_ok$next[0:0]$9859 - attribute \src "libresoc.v:170817.3-170818.35" + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so$20$next[0:0]$9908 + attribute \src "libresoc.v:172432.7-172432.25" + wire $0\xer_so$20[0:0]$10009 + attribute \src "libresoc.v:172447.3-172448.37" + wire $0\xer_so$20[0:0]$9841 + attribute \src "libresoc.v:172674.3-172692.6" + wire $0\xer_so_ok$next[0:0]$9907 + attribute \src "libresoc.v:172449.3-172450.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire width 4 $1\cr_a$next[3:0]$9849 - attribute \src "libresoc.v:169673.13-169673.24" + attribute \src "libresoc.v:172636.3-172654.6" + wire width 4 $1\cr_a$next[3:0]$9897 + attribute \src "libresoc.v:171305.13-171305.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $1\cr_a_ok$next[0:0]$9850 - attribute \src "libresoc.v:169682.7-169682.21" + attribute \src "libresoc.v:172636.3-172654.6" + wire $1\cr_a_ok$next[0:0]$9898 + attribute \src "libresoc.v:171314.7-171314.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:171092.3-171133.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9890 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9891 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9892 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9893 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9894 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9895 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9896 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__invert_in$10$next[0:0]$9897 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__invert_out$13$next[0:0]$9898 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9899 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__is_signed$17$next[0:0]$9900 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9901 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9902 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__output_carry$15$next[0:0]$9903 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9904 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9905 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9906 - attribute \src "libresoc.v:171092.3-171133.6" - wire $1\logical_op__zero_a$11$next[0:0]$9907 - attribute \src "libresoc.v:171079.3-171091.6" - wire width 2 $1\muxid$1$next[1:0]$9870 - attribute \src "libresoc.v:170985.3-171003.6" - wire width 64 $1\o$next[63:0]$9843 - attribute \src "libresoc.v:170162.14-170162.38" + attribute \src "libresoc.v:172724.3-172765.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9943 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_in$10$next[0:0]$9945 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__invert_out$13$next[0:0]$9946 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9947 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__is_signed$17$next[0:0]$9948 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9949 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9950 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__output_carry$15$next[0:0]$9951 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9952 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9953 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9954 + attribute \src "libresoc.v:172724.3-172765.6" + wire $1\logical_op__zero_a$11$next[0:0]$9955 + attribute \src "libresoc.v:172711.3-172723.6" + wire width 2 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172617.3-172635.6" + wire width 64 $1\o$next[63:0]$9891 + attribute \src "libresoc.v:171794.14-171794.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:170985.3-171003.6" - wire $1\o_ok$next[0:0]$9844 - attribute \src "libresoc.v:170169.7-170169.18" + attribute \src "libresoc.v:172617.3-172635.6" + wire $1\o_ok$next[0:0]$9892 + attribute \src "libresoc.v:171801.7-171801.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:171061.3-171078.6" - wire $1\r_busy$next[0:0]$9866 - attribute \src "libresoc.v:170765.7-170765.20" + attribute \src "libresoc.v:172693.3-172710.6" + wire $1\r_busy$next[0:0]$9914 + attribute \src "libresoc.v:172397.7-172397.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire width 2 $1\xer_ov$next[1:0]$9855 - attribute \src "libresoc.v:170780.13-170780.26" + attribute \src "libresoc.v:172655.3-172673.6" + wire width 2 $1\xer_ov$next[1:0]$9903 + attribute \src "libresoc.v:172412.13-172412.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:171023.3-171041.6" - wire $1\xer_ov_ok$next[0:0]$9856 - attribute \src "libresoc.v:170787.7-170787.23" + attribute \src "libresoc.v:172655.3-172673.6" + wire $1\xer_ov_ok$next[0:0]$9904 + attribute \src "libresoc.v:172419.7-172419.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:171042.3-171060.6" - wire $1\xer_so$20$next[0:0]$9862 - attribute \src "libresoc.v:171042.3-171060.6" - wire $1\xer_so_ok$next[0:0]$9861 - attribute \src "libresoc.v:170805.7-170805.23" + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so$20$next[0:0]$9910 + attribute \src "libresoc.v:172674.3-172692.6" + wire $1\xer_so_ok$next[0:0]$9909 + attribute \src "libresoc.v:172437.7-172437.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:171004.3-171022.6" - wire $2\cr_a_ok$next[0:0]$9851 - attribute \src "libresoc.v:171092.3-171133.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9908 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9909 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9910 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9911 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9912 - attribute \src "libresoc.v:171092.3-171133.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9913 - attribute \src "libresoc.v:170985.3-171003.6" - wire $2\o_ok$next[0:0]$9845 - attribute \src "libresoc.v:171061.3-171078.6" - wire $2\r_busy$next[0:0]$9867 - attribute \src "libresoc.v:171023.3-171041.6" - wire $2\xer_ov_ok$next[0:0]$9857 - attribute \src "libresoc.v:171042.3-171060.6" - wire $2\xer_so_ok$next[0:0]$9863 - attribute \src "libresoc.v:170814.18-170814.118" - wire $and$libresoc.v:170814$9791_Y + attribute \src "libresoc.v:172636.3-172654.6" + wire $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172724.3-172765.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9958 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9959 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9960 + attribute \src "libresoc.v:172724.3-172765.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172617.3-172635.6" + wire $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172693.3-172710.6" + wire $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172655.3-172673.6" + wire $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172674.3-172692.6" + wire $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172446.18-172446.118" + wire $and$libresoc.v:172446$9839_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 56 \cr_a @@ -349606,7 +352103,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:169664.7-169664.15" + attribute \src "libresoc.v:171296.7-171296.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -350697,7 +353194,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170814$9791 + cell $and $and$libresoc.v:172446$9839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350705,16 +353202,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:170814$9791_Y + connect \Y $and$libresoc.v:172446$9839_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170871.10-170874.4" + attribute \src "libresoc.v:172503.10-172506.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170875.15-170927.4" + attribute \src "libresoc.v:172507.15-172559.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -350769,7 +353266,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:170928.16-170980.4" + attribute \src "libresoc.v:172560.16-172612.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -350824,451 +353321,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:170981.10-170984.4" + attribute \src "libresoc.v:172613.10-172616.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169664.7-169664.20" - process $proc$libresoc.v:169664$9914 + attribute \src "libresoc.v:171296.7-171296.20" + process $proc$libresoc.v:171296$9962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169673.13-169673.24" - process $proc$libresoc.v:169673$9915 + attribute \src "libresoc.v:171305.13-171305.24" + process $proc$libresoc.v:171305$9963 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:169682.7-169682.21" - process $proc$libresoc.v:169682$9916 + attribute \src "libresoc.v:171314.7-171314.21" + process $proc$libresoc.v:171314$9964 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:169705.13-169705.45" - process $proc$libresoc.v:169705$9917 + attribute \src "libresoc.v:171337.13-171337.45" + process $proc$libresoc.v:171337$9965 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9918 4'0000 + assign $0\logical_op__data_len$18[3:0]$9966 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9918 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 end - attribute \src "libresoc.v:169744.14-169744.48" - process $proc$libresoc.v:169744$9919 + attribute \src "libresoc.v:171376.14-171376.48" + process $proc$libresoc.v:171376$9967 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9920 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9920 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 end - attribute \src "libresoc.v:169768.14-169768.67" - process $proc$libresoc.v:169768$9921 + attribute \src "libresoc.v:171400.14-171400.67" + process $proc$libresoc.v:171400$9969 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9922 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9922 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 end - attribute \src "libresoc.v:169777.7-169777.42" - process $proc$libresoc.v:169777$9923 + attribute \src "libresoc.v:171409.7-171409.42" + process $proc$libresoc.v:171409$9971 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9924 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9924 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 end - attribute \src "libresoc.v:169794.13-169794.48" - process $proc$libresoc.v:169794$9925 + attribute \src "libresoc.v:171426.13-171426.48" + process $proc$libresoc.v:171426$9973 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9926 2'00 + assign $0\logical_op__input_carry$12[1:0]$9974 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9926 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 end - attribute \src "libresoc.v:169807.14-169807.43" - process $proc$libresoc.v:169807$9927 + attribute \src "libresoc.v:171439.14-171439.43" + process $proc$libresoc.v:171439$9975 assign { } { } - assign $0\logical_op__insn$19[31:0]$9928 0 + assign $0\logical_op__insn$19[31:0]$9976 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9928 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 end - attribute \src "libresoc.v:169966.13-169966.46" - process $proc$libresoc.v:169966$9929 + attribute \src "libresoc.v:171598.13-171598.46" + process $proc$libresoc.v:171598$9977 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9930 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9930 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 end - attribute \src "libresoc.v:170050.7-170050.40" - process $proc$libresoc.v:170050$9931 + attribute \src "libresoc.v:171682.7-171682.40" + process $proc$libresoc.v:171682$9979 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9932 1'0 + assign $0\logical_op__invert_in$10[0:0]$9980 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9932 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 end - attribute \src "libresoc.v:170059.7-170059.41" - process $proc$libresoc.v:170059$9933 + attribute \src "libresoc.v:171691.7-171691.41" + process $proc$libresoc.v:171691$9981 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9934 1'0 + assign $0\logical_op__invert_out$13[0:0]$9982 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9934 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 end - attribute \src "libresoc.v:170068.7-170068.39" - process $proc$libresoc.v:170068$9935 + attribute \src "libresoc.v:171700.7-171700.39" + process $proc$libresoc.v:171700$9983 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9936 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9936 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 end - attribute \src "libresoc.v:170077.7-170077.40" - process $proc$libresoc.v:170077$9937 + attribute \src "libresoc.v:171709.7-171709.40" + process $proc$libresoc.v:171709$9985 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9938 1'0 + assign $0\logical_op__is_signed$17[0:0]$9986 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9938 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 end - attribute \src "libresoc.v:170086.7-170086.36" - process $proc$libresoc.v:170086$9939 + attribute \src "libresoc.v:171718.7-171718.36" + process $proc$libresoc.v:171718$9987 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9940 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9940 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 end - attribute \src "libresoc.v:170097.7-170097.36" - process $proc$libresoc.v:170097$9941 + attribute \src "libresoc.v:171729.7-171729.36" + process $proc$libresoc.v:171729$9989 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9942 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9942 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 end - attribute \src "libresoc.v:170104.7-170104.43" - process $proc$libresoc.v:170104$9943 + attribute \src "libresoc.v:171736.7-171736.43" + process $proc$libresoc.v:171736$9991 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9944 1'0 + assign $0\logical_op__output_carry$15[0:0]$9992 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9944 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 end - attribute \src "libresoc.v:170113.7-170113.36" - process $proc$libresoc.v:170113$9945 + attribute \src "libresoc.v:171745.7-171745.36" + process $proc$libresoc.v:171745$9993 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9946 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9946 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 end - attribute \src "libresoc.v:170122.7-170122.36" - process $proc$libresoc.v:170122$9947 + attribute \src "libresoc.v:171754.7-171754.36" + process $proc$libresoc.v:171754$9995 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9948 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9948 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 end - attribute \src "libresoc.v:170131.7-170131.40" - process $proc$libresoc.v:170131$9949 + attribute \src "libresoc.v:171763.7-171763.40" + process $proc$libresoc.v:171763$9997 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9950 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9950 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 end - attribute \src "libresoc.v:170140.7-170140.37" - process $proc$libresoc.v:170140$9951 + attribute \src "libresoc.v:171772.7-171772.37" + process $proc$libresoc.v:171772$9999 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9952 1'0 + assign $0\logical_op__zero_a$11[0:0]$10000 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9952 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 end - attribute \src "libresoc.v:170149.13-170149.29" - process $proc$libresoc.v:170149$9953 + attribute \src "libresoc.v:171781.13-171781.29" + process $proc$libresoc.v:171781$10001 assign { } { } - assign $0\muxid$1[1:0]$9954 2'00 + assign $0\muxid$1[1:0]$10002 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9954 + update \muxid$1 $0\muxid$1[1:0]$10002 end - attribute \src "libresoc.v:170162.14-170162.38" - process $proc$libresoc.v:170162$9955 + attribute \src "libresoc.v:171794.14-171794.38" + process $proc$libresoc.v:171794$10003 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:170169.7-170169.18" - process $proc$libresoc.v:170169$9956 + attribute \src "libresoc.v:171801.7-171801.18" + process $proc$libresoc.v:171801$10004 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:170765.7-170765.20" - process $proc$libresoc.v:170765$9957 + attribute \src "libresoc.v:172397.7-172397.20" + process $proc$libresoc.v:172397$10005 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170780.13-170780.26" - process $proc$libresoc.v:170780$9958 + attribute \src "libresoc.v:172412.13-172412.26" + process $proc$libresoc.v:172412$10006 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:170787.7-170787.23" - process $proc$libresoc.v:170787$9959 + attribute \src "libresoc.v:172419.7-172419.23" + process $proc$libresoc.v:172419$10007 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:170800.7-170800.25" - process $proc$libresoc.v:170800$9960 + attribute \src "libresoc.v:172432.7-172432.25" + process $proc$libresoc.v:172432$10008 assign { } { } - assign $0\xer_so$20[0:0]$9961 1'0 + assign $0\xer_so$20[0:0]$10009 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$9961 + update \xer_so$20 $0\xer_so$20[0:0]$10009 end - attribute \src "libresoc.v:170805.7-170805.23" - process $proc$libresoc.v:170805$9962 + attribute \src "libresoc.v:172437.7-172437.23" + process $proc$libresoc.v:172437$10010 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:170815.3-170816.37" - process $proc$libresoc.v:170815$9792 + attribute \src "libresoc.v:172447.3-172448.37" + process $proc$libresoc.v:172447$9840 assign { } { } - assign $0\xer_so$20[0:0]$9793 \xer_so$20$next + assign $0\xer_so$20[0:0]$9841 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9793 + update \xer_so$20 $0\xer_so$20[0:0]$9841 end - attribute \src "libresoc.v:170817.3-170818.35" - process $proc$libresoc.v:170817$9794 + attribute \src "libresoc.v:172449.3-172450.35" + process $proc$libresoc.v:172449$9842 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:170819.3-170820.29" - process $proc$libresoc.v:170819$9795 + attribute \src "libresoc.v:172451.3-172452.29" + process $proc$libresoc.v:172451$9843 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:170821.3-170822.35" - process $proc$libresoc.v:170821$9796 + attribute \src "libresoc.v:172453.3-172454.35" + process $proc$libresoc.v:172453$9844 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:170823.3-170824.25" - process $proc$libresoc.v:170823$9797 + attribute \src "libresoc.v:172455.3-172456.25" + process $proc$libresoc.v:172455$9845 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:170825.3-170826.31" - process $proc$libresoc.v:170825$9798 + attribute \src "libresoc.v:172457.3-172458.31" + process $proc$libresoc.v:172457$9846 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:170827.3-170828.19" - process $proc$libresoc.v:170827$9799 + attribute \src "libresoc.v:172459.3-172460.19" + process $proc$libresoc.v:172459$9847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:170829.3-170830.25" - process $proc$libresoc.v:170829$9800 + attribute \src "libresoc.v:172461.3-172462.25" + process $proc$libresoc.v:172461$9848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:170831.3-170832.65" - process $proc$libresoc.v:170831$9801 + attribute \src "libresoc.v:172463.3-172464.65" + process $proc$libresoc.v:172463$9849 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9802 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9802 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 end - attribute \src "libresoc.v:170833.3-170834.61" - process $proc$libresoc.v:170833$9803 + attribute \src "libresoc.v:172465.3-172466.61" + process $proc$libresoc.v:172465$9851 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9804 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9804 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 end - attribute \src "libresoc.v:170835.3-170836.75" - process $proc$libresoc.v:170835$9805 + attribute \src "libresoc.v:172467.3-172468.75" + process $proc$libresoc.v:172467$9853 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9806 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9806 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 end - attribute \src "libresoc.v:170837.3-170838.71" - process $proc$libresoc.v:170837$9807 + attribute \src "libresoc.v:172469.3-172470.71" + process $proc$libresoc.v:172469$9855 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9808 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9808 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 end - attribute \src "libresoc.v:170839.3-170840.59" - process $proc$libresoc.v:170839$9809 + attribute \src "libresoc.v:172471.3-172472.59" + process $proc$libresoc.v:172471$9857 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9810 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9810 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 end - attribute \src "libresoc.v:170841.3-170842.59" - process $proc$libresoc.v:170841$9811 + attribute \src "libresoc.v:172473.3-172474.59" + process $proc$libresoc.v:172473$9859 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9812 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9812 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 end - attribute \src "libresoc.v:170843.3-170844.59" - process $proc$libresoc.v:170843$9813 + attribute \src "libresoc.v:172475.3-172476.59" + process $proc$libresoc.v:172475$9861 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9814 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9814 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 end - attribute \src "libresoc.v:170845.3-170846.59" - process $proc$libresoc.v:170845$9815 + attribute \src "libresoc.v:172477.3-172478.59" + process $proc$libresoc.v:172477$9863 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9816 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9816 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 end - attribute \src "libresoc.v:170847.3-170848.67" - process $proc$libresoc.v:170847$9817 + attribute \src "libresoc.v:172479.3-172480.67" + process $proc$libresoc.v:172479$9865 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9818 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9818 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 end - attribute \src "libresoc.v:170849.3-170850.61" - process $proc$libresoc.v:170849$9819 + attribute \src "libresoc.v:172481.3-172482.61" + process $proc$libresoc.v:172481$9867 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9820 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9820 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 end - attribute \src "libresoc.v:170851.3-170852.71" - process $proc$libresoc.v:170851$9821 + attribute \src "libresoc.v:172483.3-172484.71" + process $proc$libresoc.v:172483$9869 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9822 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9822 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 end - attribute \src "libresoc.v:170853.3-170854.69" - process $proc$libresoc.v:170853$9823 + attribute \src "libresoc.v:172485.3-172486.69" + process $proc$libresoc.v:172485$9871 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9824 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9824 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 end - attribute \src "libresoc.v:170855.3-170856.67" - process $proc$libresoc.v:170855$9825 + attribute \src "libresoc.v:172487.3-172488.67" + process $proc$libresoc.v:172487$9873 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9826 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9826 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 end - attribute \src "libresoc.v:170857.3-170858.73" - process $proc$libresoc.v:170857$9827 + attribute \src "libresoc.v:172489.3-172490.73" + process $proc$libresoc.v:172489$9875 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9828 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9828 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 end - attribute \src "libresoc.v:170859.3-170860.65" - process $proc$libresoc.v:170859$9829 + attribute \src "libresoc.v:172491.3-172492.65" + process $proc$libresoc.v:172491$9877 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9830 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9830 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 end - attribute \src "libresoc.v:170861.3-170862.67" - process $proc$libresoc.v:170861$9831 + attribute \src "libresoc.v:172493.3-172494.67" + process $proc$libresoc.v:172493$9879 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9832 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9832 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 end - attribute \src "libresoc.v:170863.3-170864.65" - process $proc$libresoc.v:170863$9833 + attribute \src "libresoc.v:172495.3-172496.65" + process $proc$libresoc.v:172495$9881 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9834 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9834 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 end - attribute \src "libresoc.v:170865.3-170866.57" - process $proc$libresoc.v:170865$9835 + attribute \src "libresoc.v:172497.3-172498.57" + process $proc$libresoc.v:172497$9883 assign { } { } - assign $0\logical_op__insn$19[31:0]$9836 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9836 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 end - attribute \src "libresoc.v:170867.3-170868.33" - process $proc$libresoc.v:170867$9837 + attribute \src "libresoc.v:172499.3-172500.33" + process $proc$libresoc.v:172499$9885 assign { } { } - assign $0\muxid$1[1:0]$9838 \muxid$1$next + assign $0\muxid$1[1:0]$9886 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9838 + update \muxid$1 $0\muxid$1[1:0]$9886 end - attribute \src "libresoc.v:170869.3-170870.29" - process $proc$libresoc.v:170869$9839 + attribute \src "libresoc.v:172501.3-172502.29" + process $proc$libresoc.v:172501$9887 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170985.3-171003.6" - process $proc$libresoc.v:170985$9840 + attribute \src "libresoc.v:172617.3-172635.6" + process $proc$libresoc.v:172617$9888 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9841 $1\o$next[63:0]$9843 + assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 assign { } { } - assign $0\o_ok$next[0:0]$9842 $2\o_ok$next[0:0]$9845 - attribute \src "libresoc.v:170986.5-170986.29" + assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 + attribute \src "libresoc.v:172618.5-172618.29" switch \initial - attribute \src "libresoc.v:170986.9-170986.17" + attribute \src "libresoc.v:172618.9-172618.17" case 1'1 case end @@ -351278,41 +353775,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9844 $1\o$next[63:0]$9843 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9843 \o - assign $1\o_ok$next[0:0]$9844 \o_ok + assign $1\o$next[63:0]$9891 \o + assign $1\o_ok$next[0:0]$9892 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9845 1'0 + assign $2\o_ok$next[0:0]$9893 1'0 case - assign $2\o_ok$next[0:0]$9845 $1\o_ok$next[0:0]$9844 + assign $2\o_ok$next[0:0]$9893 $1\o_ok$next[0:0]$9892 end sync always - update \o$next $0\o$next[63:0]$9841 - update \o_ok$next $0\o_ok$next[0:0]$9842 + update \o$next $0\o$next[63:0]$9889 + update \o_ok$next $0\o_ok$next[0:0]$9890 end - attribute \src "libresoc.v:171004.3-171022.6" - process $proc$libresoc.v:171004$9846 + attribute \src "libresoc.v:172636.3-172654.6" + process $proc$libresoc.v:172636$9894 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9847 $1\cr_a$next[3:0]$9849 + assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 assign { } { } - assign $0\cr_a_ok$next[0:0]$9848 $2\cr_a_ok$next[0:0]$9851 - attribute \src "libresoc.v:171005.5-171005.29" + assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 + attribute \src "libresoc.v:172637.5-172637.29" switch \initial - attribute \src "libresoc.v:171005.9-171005.17" + attribute \src "libresoc.v:172637.9-172637.17" case 1'1 case end @@ -351322,41 +353819,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9850 $1\cr_a$next[3:0]$9849 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9849 \cr_a - assign $1\cr_a_ok$next[0:0]$9850 \cr_a_ok + assign $1\cr_a$next[3:0]$9897 \cr_a + assign $1\cr_a_ok$next[0:0]$9898 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9851 1'0 + assign $2\cr_a_ok$next[0:0]$9899 1'0 case - assign $2\cr_a_ok$next[0:0]$9851 $1\cr_a_ok$next[0:0]$9850 + assign $2\cr_a_ok$next[0:0]$9899 $1\cr_a_ok$next[0:0]$9898 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9847 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9848 + update \cr_a$next $0\cr_a$next[3:0]$9895 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 end - attribute \src "libresoc.v:171023.3-171041.6" - process $proc$libresoc.v:171023$9852 + attribute \src "libresoc.v:172655.3-172673.6" + process $proc$libresoc.v:172655$9900 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9853 $1\xer_ov$next[1:0]$9855 + assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9854 $2\xer_ov_ok$next[0:0]$9857 - attribute \src "libresoc.v:171024.5-171024.29" + assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 + attribute \src "libresoc.v:172656.5-172656.29" switch \initial - attribute \src "libresoc.v:171024.9-171024.17" + attribute \src "libresoc.v:172656.9-172656.17" case 1'1 case end @@ -351366,41 +353863,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9856 $1\xer_ov$next[1:0]$9855 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9855 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9856 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9903 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9904 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9857 1'0 + assign $2\xer_ov_ok$next[0:0]$9905 1'0 case - assign $2\xer_ov_ok$next[0:0]$9857 $1\xer_ov_ok$next[0:0]$9856 + assign $2\xer_ov_ok$next[0:0]$9905 $1\xer_ov_ok$next[0:0]$9904 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9853 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9854 + update \xer_ov$next $0\xer_ov$next[1:0]$9901 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 end - attribute \src "libresoc.v:171042.3-171060.6" - process $proc$libresoc.v:171042$9858 + attribute \src "libresoc.v:172674.3-172692.6" + process $proc$libresoc.v:172674$9906 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9860 $1\xer_so$20$next[0:0]$9862 - assign $0\xer_so_ok$next[0:0]$9859 $2\xer_so_ok$next[0:0]$9863 - attribute \src "libresoc.v:171043.5-171043.29" + assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 + assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:172675.5-172675.29" switch \initial - attribute \src "libresoc.v:171043.9-171043.17" + attribute \src "libresoc.v:172675.9-172675.17" case 1'1 case end @@ -351410,38 +353907,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9861 $1\xer_so$20$next[0:0]$9862 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9861 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9862 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9909 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9910 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9863 1'0 + assign $2\xer_so_ok$next[0:0]$9911 1'0 case - assign $2\xer_so_ok$next[0:0]$9863 $1\xer_so_ok$next[0:0]$9861 + assign $2\xer_so_ok$next[0:0]$9911 $1\xer_so_ok$next[0:0]$9909 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9859 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9860 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 end - attribute \src "libresoc.v:171061.3-171078.6" - process $proc$libresoc.v:171061$9864 + attribute \src "libresoc.v:172693.3-172710.6" + process $proc$libresoc.v:172693$9912 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9865 $2\r_busy$next[0:0]$9867 - attribute \src "libresoc.v:171062.5-171062.29" + assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:172694.5-172694.29" switch \initial - attribute \src "libresoc.v:171062.9-171062.17" + attribute \src "libresoc.v:172694.9-172694.17" case 1'1 case end @@ -351450,34 +353947,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9866 1'1 + assign $1\r_busy$next[0:0]$9914 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9866 1'0 + assign $1\r_busy$next[0:0]$9914 1'0 case - assign $1\r_busy$next[0:0]$9866 \r_busy + assign $1\r_busy$next[0:0]$9914 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9867 1'0 + assign $2\r_busy$next[0:0]$9915 1'0 case - assign $2\r_busy$next[0:0]$9867 $1\r_busy$next[0:0]$9866 + assign $2\r_busy$next[0:0]$9915 $1\r_busy$next[0:0]$9914 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9865 + update \r_busy$next $0\r_busy$next[0:0]$9913 end - attribute \src "libresoc.v:171079.3-171091.6" - process $proc$libresoc.v:171079$9868 + attribute \src "libresoc.v:172711.3-172723.6" + process $proc$libresoc.v:172711$9916 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9869 $1\muxid$1$next[1:0]$9870 - attribute \src "libresoc.v:171080.5-171080.29" + assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 + attribute \src "libresoc.v:172712.5-172712.29" switch \initial - attribute \src "libresoc.v:171080.9-171080.17" + attribute \src "libresoc.v:172712.9-172712.17" case 1'1 case end @@ -351486,19 +353983,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9870 \muxid$76 + assign $1\muxid$1$next[1:0]$9918 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9870 \muxid$76 + assign $1\muxid$1$next[1:0]$9918 \muxid$76 case - assign $1\muxid$1$next[1:0]$9870 \muxid$1 + assign $1\muxid$1$next[1:0]$9918 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9869 + update \muxid$1$next $0\muxid$1$next[1:0]$9917 end - attribute \src "libresoc.v:171092.3-171133.6" - process $proc$libresoc.v:171092$9871 + attribute \src "libresoc.v:172724.3-172765.6" + process $proc$libresoc.v:172724$9919 assign { } { } assign { } { } assign { } { } @@ -351535,33 +354032,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9872 $1\logical_op__data_len$18$next[3:0]$9890 - assign $0\logical_op__fn_unit$3$next[13:0]$9873 $1\logical_op__fn_unit$3$next[13:0]$9891 + assign $0\logical_op__data_len$18$next[3:0]$9920 $1\logical_op__data_len$18$next[3:0]$9938 + assign $0\logical_op__fn_unit$3$next[13:0]$9921 $1\logical_op__fn_unit$3$next[13:0]$9939 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9876 $1\logical_op__input_carry$12$next[1:0]$9894 - assign $0\logical_op__insn$19$next[31:0]$9877 $1\logical_op__insn$19$next[31:0]$9895 - assign $0\logical_op__insn_type$2$next[6:0]$9878 $1\logical_op__insn_type$2$next[6:0]$9896 - assign $0\logical_op__invert_in$10$next[0:0]$9879 $1\logical_op__invert_in$10$next[0:0]$9897 - assign $0\logical_op__invert_out$13$next[0:0]$9880 $1\logical_op__invert_out$13$next[0:0]$9898 - assign $0\logical_op__is_32bit$16$next[0:0]$9881 $1\logical_op__is_32bit$16$next[0:0]$9899 - assign $0\logical_op__is_signed$17$next[0:0]$9882 $1\logical_op__is_signed$17$next[0:0]$9900 + assign $0\logical_op__input_carry$12$next[1:0]$9924 $1\logical_op__input_carry$12$next[1:0]$9942 + assign $0\logical_op__insn$19$next[31:0]$9925 $1\logical_op__insn$19$next[31:0]$9943 + assign $0\logical_op__insn_type$2$next[6:0]$9926 $1\logical_op__insn_type$2$next[6:0]$9944 + assign $0\logical_op__invert_in$10$next[0:0]$9927 $1\logical_op__invert_in$10$next[0:0]$9945 + assign $0\logical_op__invert_out$13$next[0:0]$9928 $1\logical_op__invert_out$13$next[0:0]$9946 + assign $0\logical_op__is_32bit$16$next[0:0]$9929 $1\logical_op__is_32bit$16$next[0:0]$9947 + assign $0\logical_op__is_signed$17$next[0:0]$9930 $1\logical_op__is_signed$17$next[0:0]$9948 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9885 $1\logical_op__output_carry$15$next[0:0]$9903 + assign $0\logical_op__output_carry$15$next[0:0]$9933 $1\logical_op__output_carry$15$next[0:0]$9951 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9888 $1\logical_op__write_cr0$14$next[0:0]$9906 - assign $0\logical_op__zero_a$11$next[0:0]$9889 $1\logical_op__zero_a$11$next[0:0]$9907 - assign $0\logical_op__imm_data__data$4$next[63:0]$9874 $2\logical_op__imm_data__data$4$next[63:0]$9908 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9875 $2\logical_op__imm_data__ok$5$next[0:0]$9909 - assign $0\logical_op__oe__oe$8$next[0:0]$9883 $2\logical_op__oe__oe$8$next[0:0]$9910 - assign $0\logical_op__oe__ok$9$next[0:0]$9884 $2\logical_op__oe__ok$9$next[0:0]$9911 - assign $0\logical_op__rc__ok$7$next[0:0]$9886 $2\logical_op__rc__ok$7$next[0:0]$9912 - assign $0\logical_op__rc__rc$6$next[0:0]$9887 $2\logical_op__rc__rc$6$next[0:0]$9913 - attribute \src "libresoc.v:171093.5-171093.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9936 $1\logical_op__write_cr0$14$next[0:0]$9954 + assign $0\logical_op__zero_a$11$next[0:0]$9937 $1\logical_op__zero_a$11$next[0:0]$9955 + assign $0\logical_op__imm_data__data$4$next[63:0]$9922 $2\logical_op__imm_data__data$4$next[63:0]$9956 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9923 $2\logical_op__imm_data__ok$5$next[0:0]$9957 + assign $0\logical_op__oe__oe$8$next[0:0]$9931 $2\logical_op__oe__oe$8$next[0:0]$9958 + assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 + assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 + assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 + attribute \src "libresoc.v:172725.5-172725.29" switch \initial - attribute \src "libresoc.v:171093.9-171093.17" + attribute \src "libresoc.v:172725.9-172725.17" case 1'1 case end @@ -351587,7 +354084,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -351608,26 +354105,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9895 $1\logical_op__data_len$18$next[3:0]$9890 $1\logical_op__is_signed$17$next[0:0]$9900 $1\logical_op__is_32bit$16$next[0:0]$9899 $1\logical_op__output_carry$15$next[0:0]$9903 $1\logical_op__write_cr0$14$next[0:0]$9906 $1\logical_op__invert_out$13$next[0:0]$9898 $1\logical_op__input_carry$12$next[1:0]$9894 $1\logical_op__zero_a$11$next[0:0]$9907 $1\logical_op__invert_in$10$next[0:0]$9897 $1\logical_op__oe__ok$9$next[0:0]$9902 $1\logical_op__oe__oe$8$next[0:0]$9901 $1\logical_op__rc__ok$7$next[0:0]$9904 $1\logical_op__rc__rc$6$next[0:0]$9905 $1\logical_op__imm_data__ok$5$next[0:0]$9893 $1\logical_op__imm_data__data$4$next[63:0]$9892 $1\logical_op__fn_unit$3$next[13:0]$9891 $1\logical_op__insn_type$2$next[6:0]$9896 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9890 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$9891 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9892 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9893 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9894 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9895 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9896 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9897 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9898 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9899 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9900 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9901 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9902 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9903 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9904 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9905 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9906 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9907 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9938 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9939 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9940 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9941 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9942 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9943 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9944 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9945 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9946 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9947 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9948 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9949 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9950 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9951 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9952 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9953 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9954 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9955 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -351639,41 +354136,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9908 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9913 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9912 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9910 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9911 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9908 $1\logical_op__imm_data__data$4$next[63:0]$9892 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9909 $1\logical_op__imm_data__ok$5$next[0:0]$9893 - assign $2\logical_op__oe__oe$8$next[0:0]$9910 $1\logical_op__oe__oe$8$next[0:0]$9901 - assign $2\logical_op__oe__ok$9$next[0:0]$9911 $1\logical_op__oe__ok$9$next[0:0]$9902 - assign $2\logical_op__rc__ok$7$next[0:0]$9912 $1\logical_op__rc__ok$7$next[0:0]$9904 - assign $2\logical_op__rc__rc$6$next[0:0]$9913 $1\logical_op__rc__rc$6$next[0:0]$9905 + assign $2\logical_op__imm_data__data$4$next[63:0]$9956 $1\logical_op__imm_data__data$4$next[63:0]$9940 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 $1\logical_op__imm_data__ok$5$next[0:0]$9941 + assign $2\logical_op__oe__oe$8$next[0:0]$9958 $1\logical_op__oe__oe$8$next[0:0]$9949 + assign $2\logical_op__oe__ok$9$next[0:0]$9959 $1\logical_op__oe__ok$9$next[0:0]$9950 + assign $2\logical_op__rc__ok$7$next[0:0]$9960 $1\logical_op__rc__ok$7$next[0:0]$9952 + assign $2\logical_op__rc__rc$6$next[0:0]$9961 $1\logical_op__rc__rc$6$next[0:0]$9953 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9872 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9873 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9874 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9875 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9876 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9877 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9878 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9879 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9880 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9881 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9882 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9883 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9884 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9885 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9886 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9887 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9888 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9889 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9920 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9921 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9922 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9923 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9924 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9925 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9926 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9927 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9928 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9929 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9930 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9931 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9932 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9933 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9934 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9935 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 end - connect \$74 $and$libresoc.v:170814$9791_Y + connect \$74 $and$libresoc.v:172446$9839_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -351707,381 +354204,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:171170.1-172157.10" +attribute \src "libresoc.v:172802.1-173789.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:172082.3-172096.6" - wire $0\div_by_zero$54$next[0:0]$10142 - attribute \src "libresoc.v:171193.7-171193.30" - wire $0\div_by_zero$54[0:0]$10159 - attribute \src "libresoc.v:171756.3-171757.47" - wire $0\div_by_zero$54[0:0]$9977 - attribute \src "libresoc.v:171878.3-171889.6" + attribute \src "libresoc.v:173714.3-173728.6" + wire $0\div_by_zero$54$next[0:0]$10190 + attribute \src "libresoc.v:173388.3-173389.47" + wire $0\div_by_zero$54[0:0]$10025 + attribute \src "libresoc.v:172825.7-172825.30" + wire $0\div_by_zero$54[0:0]$10207 + attribute \src "libresoc.v:173510.3-173521.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171866.3-171877.6" + attribute \src "libresoc.v:173498.3-173509.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171854.3-171865.6" + attribute \src "libresoc.v:173486.3-173497.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:172052.3-172066.6" - wire $0\dive_abs_ov32$52$next[0:0]$10134 - attribute \src "libresoc.v:171217.7-171217.32" - wire $0\dive_abs_ov32$52[0:0]$10161 - attribute \src "libresoc.v:171760.3-171761.51" - wire $0\dive_abs_ov32$52[0:0]$9981 - attribute \src "libresoc.v:172067.3-172081.6" - wire $0\dive_abs_ov64$53$next[0:0]$10138 - attribute \src "libresoc.v:171225.7-171225.32" - wire $0\dive_abs_ov64$53[0:0]$10163 - attribute \src "libresoc.v:171758.3-171759.51" - wire $0\dive_abs_ov64$53[0:0]$9979 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $0\dividend$68$next[127:0]$10146 - attribute \src "libresoc.v:171231.15-171231.68" - wire width 128 $0\dividend$68[127:0]$10165 - attribute \src "libresoc.v:171754.3-171755.41" - wire width 128 $0\dividend$68[127:0]$9975 - attribute \src "libresoc.v:172037.3-172051.6" - wire $0\dividend_neg$51$next[0:0]$10130 - attribute \src "libresoc.v:171239.7-171239.31" - wire $0\dividend_neg$51[0:0]$10167 - attribute \src "libresoc.v:171762.3-171763.49" - wire $0\dividend_neg$51[0:0]$9983 - attribute \src "libresoc.v:172022.3-172036.6" - wire $0\divisor_neg$50$next[0:0]$10126 - attribute \src "libresoc.v:171247.7-171247.30" - wire $0\divisor_neg$50[0:0]$10169 - attribute \src "libresoc.v:171764.3-171765.47" - wire $0\divisor_neg$50[0:0]$9985 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10150 - attribute \src "libresoc.v:171253.14-171253.58" - wire width 64 $0\divisor_radicand$65[63:0]$10171 - attribute \src "libresoc.v:171752.3-171753.57" - wire width 64 $0\divisor_radicand$65[63:0]$9973 - attribute \src "libresoc.v:171890.3-171917.6" - wire $0\empty$next[0:0]$10043 - attribute \src "libresoc.v:171810.3-171811.27" + attribute \src "libresoc.v:173684.3-173698.6" + wire $0\dive_abs_ov32$52$next[0:0]$10182 + attribute \src "libresoc.v:173392.3-173393.51" + wire $0\dive_abs_ov32$52[0:0]$10029 + attribute \src "libresoc.v:172849.7-172849.32" + wire $0\dive_abs_ov32$52[0:0]$10209 + attribute \src "libresoc.v:173699.3-173713.6" + wire $0\dive_abs_ov64$53$next[0:0]$10186 + attribute \src "libresoc.v:173390.3-173391.51" + wire $0\dive_abs_ov64$53[0:0]$10027 + attribute \src "libresoc.v:172857.7-172857.32" + wire $0\dive_abs_ov64$53[0:0]$10211 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $0\dividend$68$next[127:0]$10194 + attribute \src "libresoc.v:173386.3-173387.41" + wire width 128 $0\dividend$68[127:0]$10023 + attribute \src "libresoc.v:172863.15-172863.68" + wire width 128 $0\dividend$68[127:0]$10213 + attribute \src "libresoc.v:173669.3-173683.6" + wire $0\dividend_neg$51$next[0:0]$10178 + attribute \src "libresoc.v:173394.3-173395.49" + wire $0\dividend_neg$51[0:0]$10031 + attribute \src "libresoc.v:172871.7-172871.31" + wire $0\dividend_neg$51[0:0]$10215 + attribute \src "libresoc.v:173654.3-173668.6" + wire $0\divisor_neg$50$next[0:0]$10174 + attribute \src "libresoc.v:173396.3-173397.47" + wire $0\divisor_neg$50[0:0]$10033 + attribute \src "libresoc.v:172879.7-172879.30" + wire $0\divisor_neg$50[0:0]$10217 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10198 + attribute \src "libresoc.v:173384.3-173385.57" + wire width 64 $0\divisor_radicand$65[63:0]$10021 + attribute \src "libresoc.v:172885.14-172885.58" + wire width 64 $0\divisor_radicand$65[63:0]$10219 + attribute \src "libresoc.v:173522.3-173549.6" + wire $0\empty$next[0:0]$10091 + attribute \src "libresoc.v:173442.3-173443.27" wire $0\empty[0:0] - attribute \src "libresoc.v:171171.7-171171.20" + attribute \src "libresoc.v:172803.7-172803.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10053 - attribute \src "libresoc.v:171804.3-171805.65" - wire width 4 $0\logical_op__data_len$45[3:0]$10025 - attribute \src "libresoc.v:171265.13-171265.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10174 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10054 - attribute \src "libresoc.v:171318.14-171318.49" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10176 - attribute \src "libresoc.v:171774.3-171775.63" - wire width 14 $0\logical_op__fn_unit$30[13:0]$9995 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10055 - attribute \src "libresoc.v:171324.14-171324.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10178 - attribute \src "libresoc.v:171776.3-171777.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9997 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10056 - attribute \src "libresoc.v:171332.7-171332.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10180 - attribute \src "libresoc.v:171778.3-171779.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9999 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10057 - attribute \src "libresoc.v:171792.3-171793.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$10013 - attribute \src "libresoc.v:171354.13-171354.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10182 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10058 - attribute \src "libresoc.v:171806.3-171807.57" - wire width 32 $0\logical_op__insn$46[31:0]$10027 - attribute \src "libresoc.v:171362.14-171362.43" - wire width 32 $0\logical_op__insn$46[31:0]$10184 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10059 - attribute \src "libresoc.v:171595.13-171595.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10186 - attribute \src "libresoc.v:171772.3-171773.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9993 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__invert_in$37$next[0:0]$10060 - attribute \src "libresoc.v:171788.3-171789.67" - wire $0\logical_op__invert_in$37[0:0]$10009 - attribute \src "libresoc.v:171603.7-171603.40" - wire $0\logical_op__invert_in$37[0:0]$10188 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__invert_out$40$next[0:0]$10061 - attribute \src "libresoc.v:171794.3-171795.69" - wire $0\logical_op__invert_out$40[0:0]$10015 - attribute \src "libresoc.v:171611.7-171611.41" - wire $0\logical_op__invert_out$40[0:0]$10190 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10062 - attribute \src "libresoc.v:171800.3-171801.65" - wire $0\logical_op__is_32bit$43[0:0]$10021 - attribute \src "libresoc.v:171619.7-171619.39" - wire $0\logical_op__is_32bit$43[0:0]$10192 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__is_signed$44$next[0:0]$10063 - attribute \src "libresoc.v:171802.3-171803.67" - wire $0\logical_op__is_signed$44[0:0]$10023 - attribute \src "libresoc.v:171627.7-171627.40" - wire $0\logical_op__is_signed$44[0:0]$10194 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10064 - attribute \src "libresoc.v:171784.3-171785.61" - wire $0\logical_op__oe__oe$35[0:0]$10005 - attribute \src "libresoc.v:171633.7-171633.37" - wire $0\logical_op__oe__oe$35[0:0]$10196 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10065 - attribute \src "libresoc.v:171786.3-171787.61" - wire $0\logical_op__oe__ok$36[0:0]$10007 - attribute \src "libresoc.v:171641.7-171641.37" - wire $0\logical_op__oe__ok$36[0:0]$10198 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__output_carry$42$next[0:0]$10066 - attribute \src "libresoc.v:171798.3-171799.73" - wire $0\logical_op__output_carry$42[0:0]$10019 - attribute \src "libresoc.v:171651.7-171651.43" - wire $0\logical_op__output_carry$42[0:0]$10200 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10067 - attribute \src "libresoc.v:171782.3-171783.61" - wire $0\logical_op__rc__ok$34[0:0]$10003 - attribute \src "libresoc.v:171657.7-171657.37" - wire $0\logical_op__rc__ok$34[0:0]$10202 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10068 - attribute \src "libresoc.v:171780.3-171781.61" - wire $0\logical_op__rc__rc$33[0:0]$10001 - attribute \src "libresoc.v:171665.7-171665.37" - wire $0\logical_op__rc__rc$33[0:0]$10204 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10069 - attribute \src "libresoc.v:171796.3-171797.67" - wire $0\logical_op__write_cr0$41[0:0]$10017 - attribute \src "libresoc.v:171675.7-171675.40" - wire $0\logical_op__write_cr0$41[0:0]$10206 - attribute \src "libresoc.v:171933.3-171976.6" - wire $0\logical_op__zero_a$38$next[0:0]$10070 - attribute \src "libresoc.v:171790.3-171791.61" - wire $0\logical_op__zero_a$38[0:0]$10011 - attribute \src "libresoc.v:171683.7-171683.37" - wire $0\logical_op__zero_a$38[0:0]$10208 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $0\muxid$28$next[1:0]$10049 - attribute \src "libresoc.v:171808.3-171809.35" - wire width 2 $0\muxid$28[1:0]$10029 - attribute \src "libresoc.v:171691.13-171691.30" - wire width 2 $0\muxid$28[1:0]$10210 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $0\operation$69$next[1:0]$10154 - attribute \src "libresoc.v:171701.13-171701.34" - wire width 2 $0\operation$69[1:0]$10212 - attribute \src "libresoc.v:171750.3-171751.43" - wire width 2 $0\operation$69[1:0]$9971 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $0\ra$47$next[63:0]$10114 - attribute \src "libresoc.v:171715.14-171715.44" - wire width 64 $0\ra$47[63:0]$10214 - attribute \src "libresoc.v:171770.3-171771.29" - wire width 64 $0\ra$47[63:0]$9991 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $0\rb$48$next[63:0]$10118 - attribute \src "libresoc.v:171723.14-171723.44" - wire width 64 $0\rb$48[63:0]$10216 - attribute \src "libresoc.v:171768.3-171769.29" - wire width 64 $0\rb$48[63:0]$9989 - attribute \src "libresoc.v:171845.3-171853.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10037 - attribute \src "libresoc.v:171812.3-171813.75" + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 + attribute \src "libresoc.v:173436.3-173437.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10073 + attribute \src "libresoc.v:172897.13-172897.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10222 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 + attribute \src "libresoc.v:173406.3-173407.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 + attribute \src "libresoc.v:172950.14-172950.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 + attribute \src "libresoc.v:173408.3-173409.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 + attribute \src "libresoc.v:172956.14-172956.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 + attribute \src "libresoc.v:173410.3-173411.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10047 + attribute \src "libresoc.v:172964.7-172964.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10228 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 + attribute \src "libresoc.v:173424.3-173425.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10061 + attribute \src "libresoc.v:172986.13-172986.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10230 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10106 + attribute \src "libresoc.v:173438.3-173439.57" + wire width 32 $0\logical_op__insn$46[31:0]$10075 + attribute \src "libresoc.v:172994.14-172994.43" + wire width 32 $0\logical_op__insn$46[31:0]$10232 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 + attribute \src "libresoc.v:173404.3-173405.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10041 + attribute \src "libresoc.v:173227.13-173227.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10234 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_in$37$next[0:0]$10108 + attribute \src "libresoc.v:173420.3-173421.67" + wire $0\logical_op__invert_in$37[0:0]$10057 + attribute \src "libresoc.v:173235.7-173235.40" + wire $0\logical_op__invert_in$37[0:0]$10236 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__invert_out$40$next[0:0]$10109 + attribute \src "libresoc.v:173426.3-173427.69" + wire $0\logical_op__invert_out$40[0:0]$10063 + attribute \src "libresoc.v:173243.7-173243.41" + wire $0\logical_op__invert_out$40[0:0]$10238 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10110 + attribute \src "libresoc.v:173432.3-173433.65" + wire $0\logical_op__is_32bit$43[0:0]$10069 + attribute \src "libresoc.v:173251.7-173251.39" + wire $0\logical_op__is_32bit$43[0:0]$10240 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__is_signed$44$next[0:0]$10111 + attribute \src "libresoc.v:173434.3-173435.67" + wire $0\logical_op__is_signed$44[0:0]$10071 + attribute \src "libresoc.v:173259.7-173259.40" + wire $0\logical_op__is_signed$44[0:0]$10242 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10112 + attribute \src "libresoc.v:173416.3-173417.61" + wire $0\logical_op__oe__oe$35[0:0]$10053 + attribute \src "libresoc.v:173265.7-173265.37" + wire $0\logical_op__oe__oe$35[0:0]$10244 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10113 + attribute \src "libresoc.v:173418.3-173419.61" + wire $0\logical_op__oe__ok$36[0:0]$10055 + attribute \src "libresoc.v:173273.7-173273.37" + wire $0\logical_op__oe__ok$36[0:0]$10246 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__output_carry$42$next[0:0]$10114 + attribute \src "libresoc.v:173430.3-173431.73" + wire $0\logical_op__output_carry$42[0:0]$10067 + attribute \src "libresoc.v:173283.7-173283.43" + wire $0\logical_op__output_carry$42[0:0]$10248 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10115 + attribute \src "libresoc.v:173414.3-173415.61" + wire $0\logical_op__rc__ok$34[0:0]$10051 + attribute \src "libresoc.v:173289.7-173289.37" + wire $0\logical_op__rc__ok$34[0:0]$10250 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10116 + attribute \src "libresoc.v:173412.3-173413.61" + wire $0\logical_op__rc__rc$33[0:0]$10049 + attribute \src "libresoc.v:173297.7-173297.37" + wire $0\logical_op__rc__rc$33[0:0]$10252 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10117 + attribute \src "libresoc.v:173428.3-173429.67" + wire $0\logical_op__write_cr0$41[0:0]$10065 + attribute \src "libresoc.v:173307.7-173307.40" + wire $0\logical_op__write_cr0$41[0:0]$10254 + attribute \src "libresoc.v:173565.3-173608.6" + wire $0\logical_op__zero_a$38$next[0:0]$10118 + attribute \src "libresoc.v:173422.3-173423.61" + wire $0\logical_op__zero_a$38[0:0]$10059 + attribute \src "libresoc.v:173315.7-173315.37" + wire $0\logical_op__zero_a$38[0:0]$10256 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $0\muxid$28$next[1:0]$10097 + attribute \src "libresoc.v:173440.3-173441.35" + wire width 2 $0\muxid$28[1:0]$10077 + attribute \src "libresoc.v:173323.13-173323.30" + wire width 2 $0\muxid$28[1:0]$10258 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $0\operation$69$next[1:0]$10202 + attribute \src "libresoc.v:173382.3-173383.43" + wire width 2 $0\operation$69[1:0]$10019 + attribute \src "libresoc.v:173333.13-173333.34" + wire width 2 $0\operation$69[1:0]$10260 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $0\ra$47$next[63:0]$10162 + attribute \src "libresoc.v:173402.3-173403.29" + wire width 64 $0\ra$47[63:0]$10039 + attribute \src "libresoc.v:173347.14-173347.44" + wire width 64 $0\ra$47[63:0]$10262 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $0\rb$48$next[63:0]$10166 + attribute \src "libresoc.v:173400.3-173401.29" + wire width 64 $0\rb$48[63:0]$10037 + attribute \src "libresoc.v:173355.14-173355.44" + wire width 64 $0\rb$48[63:0]$10264 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 + attribute \src "libresoc.v:173444.3-173445.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:171836.3-171844.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$10034 - attribute \src "libresoc.v:171814.3-171815.65" + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 + attribute \src "libresoc.v:173446.3-173447.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:172007.3-172021.6" - wire $0\xer_so$49$next[0:0]$10122 - attribute \src "libresoc.v:171741.7-171741.25" - wire $0\xer_so$49[0:0]$10220 - attribute \src "libresoc.v:171766.3-171767.37" - wire $0\xer_so$49[0:0]$9987 - attribute \src "libresoc.v:172082.3-172096.6" - wire $1\div_by_zero$54$next[0:0]$10143 - attribute \src "libresoc.v:171878.3-171889.6" + attribute \src "libresoc.v:173639.3-173653.6" + wire $0\xer_so$49$next[0:0]$10170 + attribute \src "libresoc.v:173398.3-173399.37" + wire $0\xer_so$49[0:0]$10035 + attribute \src "libresoc.v:173373.7-173373.25" + wire $0\xer_so$49[0:0]$10268 + attribute \src "libresoc.v:173714.3-173728.6" + wire $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173510.3-173521.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171866.3-171877.6" + attribute \src "libresoc.v:173498.3-173509.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171854.3-171865.6" + attribute \src "libresoc.v:173486.3-173497.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:172052.3-172066.6" - wire $1\dive_abs_ov32$52$next[0:0]$10135 - attribute \src "libresoc.v:172067.3-172081.6" - wire $1\dive_abs_ov64$53$next[0:0]$10139 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $1\dividend$68$next[127:0]$10147 - attribute \src "libresoc.v:172037.3-172051.6" - wire $1\dividend_neg$51$next[0:0]$10131 - attribute \src "libresoc.v:172022.3-172036.6" - wire $1\divisor_neg$50$next[0:0]$10127 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10151 - attribute \src "libresoc.v:171890.3-171917.6" - wire $1\empty$next[0:0]$10044 - attribute \src "libresoc.v:171257.7-171257.19" + attribute \src "libresoc.v:173684.3-173698.6" + wire $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173699.3-173713.6" + wire $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173669.3-173683.6" + wire $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173654.3-173668.6" + wire $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173522.3-173549.6" + wire $1\empty$next[0:0]$10092 + attribute \src "libresoc.v:172889.7-172889.19" wire $1\empty[0:0] - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10071 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10072 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10073 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10074 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10075 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10076 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10077 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__invert_in$37$next[0:0]$10078 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__invert_out$40$next[0:0]$10079 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10080 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__is_signed$44$next[0:0]$10081 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10082 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10083 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__output_carry$42$next[0:0]$10084 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10085 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10086 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10087 - attribute \src "libresoc.v:171933.3-171976.6" - wire $1\logical_op__zero_a$38$next[0:0]$10088 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $1\muxid$28$next[1:0]$10050 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $1\operation$69$next[1:0]$10155 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $1\ra$47$next[63:0]$10115 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $1\rb$48$next[63:0]$10119 - attribute \src "libresoc.v:171845.3-171853.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10038 - attribute \src "libresoc.v:171729.15-171729.84" + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10124 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_in$37$next[0:0]$10126 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__invert_out$40$next[0:0]$10127 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10128 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__is_signed$44$next[0:0]$10129 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10130 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10131 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__output_carry$42$next[0:0]$10132 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10133 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10134 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10135 + attribute \src "libresoc.v:173565.3-173608.6" + wire $1\logical_op__zero_a$38$next[0:0]$10136 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173477.3-173485.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173361.15-173361.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:171836.3-171844.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$10035 - attribute \src "libresoc.v:171733.13-171733.45" + attribute \src "libresoc.v:173468.3-173476.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173365.13-173365.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:172007.3-172021.6" - wire $1\xer_so$49$next[0:0]$10123 - attribute \src "libresoc.v:172082.3-172096.6" - wire $2\div_by_zero$54$next[0:0]$10144 - attribute \src "libresoc.v:172052.3-172066.6" - wire $2\dive_abs_ov32$52$next[0:0]$10136 - attribute \src "libresoc.v:172067.3-172081.6" - wire $2\dive_abs_ov64$53$next[0:0]$10140 - attribute \src "libresoc.v:172097.3-172111.6" - wire width 128 $2\dividend$68$next[127:0]$10148 - attribute \src "libresoc.v:172037.3-172051.6" - wire $2\dividend_neg$51$next[0:0]$10132 - attribute \src "libresoc.v:172022.3-172036.6" - wire $2\divisor_neg$50$next[0:0]$10128 - attribute \src "libresoc.v:172112.3-172126.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10152 - attribute \src "libresoc.v:171890.3-171917.6" - wire $2\empty$next[0:0]$10045 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10089 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10090 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10091 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10092 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$10093 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$10094 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$10095 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__invert_in$37$next[0:0]$10096 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__invert_out$40$next[0:0]$10097 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__is_32bit$43$next[0:0]$10098 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__is_signed$44$next[0:0]$10099 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__oe__oe$35$next[0:0]$10100 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__oe__ok$36$next[0:0]$10101 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__output_carry$42$next[0:0]$10102 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__rc__ok$34$next[0:0]$10103 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__rc__rc$33$next[0:0]$10104 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__write_cr0$41$next[0:0]$10105 - attribute \src "libresoc.v:171933.3-171976.6" - wire $2\logical_op__zero_a$38$next[0:0]$10106 - attribute \src "libresoc.v:171918.3-171932.6" - wire width 2 $2\muxid$28$next[1:0]$10051 - attribute \src "libresoc.v:172127.3-172141.6" - wire width 2 $2\operation$69$next[1:0]$10156 - attribute \src "libresoc.v:171977.3-171991.6" - wire width 64 $2\ra$47$next[63:0]$10116 - attribute \src "libresoc.v:171992.3-172006.6" - wire width 64 $2\rb$48$next[63:0]$10120 - attribute \src "libresoc.v:172007.3-172021.6" - wire $2\xer_so$49$next[0:0]$10124 - attribute \src "libresoc.v:171890.3-171917.6" - wire $3\empty$next[0:0]$10046 - attribute \src "libresoc.v:171933.3-171976.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10107 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$10108 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__oe__oe$35$next[0:0]$10109 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__oe__ok$36$next[0:0]$10110 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__rc__ok$34$next[0:0]$10111 - attribute \src "libresoc.v:171933.3-171976.6" - wire $3\logical_op__rc__rc$33$next[0:0]$10112 - attribute \src "libresoc.v:171890.3-171917.6" - wire $4\empty$next[0:0]$10047 - attribute \src "libresoc.v:171748.18-171748.98" - wire $and$libresoc.v:171748$9968_Y - attribute \src "libresoc.v:171749.18-171749.107" - wire $and$libresoc.v:171749$9969_Y - attribute \src "libresoc.v:171745.18-171745.92" - wire width 192 $extend$libresoc.v:171745$9964_Y - attribute \src "libresoc.v:171747.18-171747.119" - wire $ge$libresoc.v:171747$9967_Y - attribute \src "libresoc.v:171746.18-171746.93" - wire $not$libresoc.v:171746$9966_Y - attribute \src "libresoc.v:171745.18-171745.92" - wire width 192 $pos$libresoc.v:171745$9965_Y - attribute \src "libresoc.v:171744.18-171744.138" - wire width 191 $sshl$libresoc.v:171744$9963_Y + attribute \src "libresoc.v:173639.3-173653.6" + wire $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173714.3-173728.6" + wire $2\div_by_zero$54$next[0:0]$10192 + attribute \src "libresoc.v:173684.3-173698.6" + wire $2\dive_abs_ov32$52$next[0:0]$10184 + attribute \src "libresoc.v:173699.3-173713.6" + wire $2\dive_abs_ov64$53$next[0:0]$10188 + attribute \src "libresoc.v:173729.3-173743.6" + wire width 128 $2\dividend$68$next[127:0]$10196 + attribute \src "libresoc.v:173669.3-173683.6" + wire $2\dividend_neg$51$next[0:0]$10180 + attribute \src "libresoc.v:173654.3-173668.6" + wire $2\divisor_neg$50$next[0:0]$10176 + attribute \src "libresoc.v:173744.3-173758.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10200 + attribute \src "libresoc.v:173522.3-173549.6" + wire $2\empty$next[0:0]$10093 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10142 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_in$37$next[0:0]$10144 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__invert_out$40$next[0:0]$10145 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10146 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__is_signed$44$next[0:0]$10147 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10148 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10149 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__output_carry$42$next[0:0]$10150 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10151 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10152 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10153 + attribute \src "libresoc.v:173565.3-173608.6" + wire $2\logical_op__zero_a$38$next[0:0]$10154 + attribute \src "libresoc.v:173550.3-173564.6" + wire width 2 $2\muxid$28$next[1:0]$10099 + attribute \src "libresoc.v:173759.3-173773.6" + wire width 2 $2\operation$69$next[1:0]$10204 + attribute \src "libresoc.v:173609.3-173623.6" + wire width 64 $2\ra$47$next[63:0]$10164 + attribute \src "libresoc.v:173624.3-173638.6" + wire width 64 $2\rb$48$next[63:0]$10168 + attribute \src "libresoc.v:173639.3-173653.6" + wire $2\xer_so$49$next[0:0]$10172 + attribute \src "libresoc.v:173522.3-173549.6" + wire $3\empty$next[0:0]$10094 + attribute \src "libresoc.v:173565.3-173608.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10157 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10158 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10159 + attribute \src "libresoc.v:173565.3-173608.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173522.3-173549.6" + wire $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173380.18-173380.98" + wire $and$libresoc.v:173380$10016_Y + attribute \src "libresoc.v:173381.18-173381.107" + wire $and$libresoc.v:173381$10017_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $extend$libresoc.v:173377$10012_Y + attribute \src "libresoc.v:173379.18-173379.119" + wire $ge$libresoc.v:173379$10015_Y + attribute \src "libresoc.v:173378.18-173378.93" + wire $not$libresoc.v:173378$10014_Y + attribute \src "libresoc.v:173377.18-173377.92" + wire width 192 $pos$libresoc.v:173377$10013_Y + attribute \src "libresoc.v:173376.18-173376.138" + wire width 191 $sshl$libresoc.v:173376$10011_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -352094,9 +354591,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -352170,7 +354667,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:171171.7-171171.15" + attribute \src "libresoc.v:172803.7-172803.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -352657,7 +355154,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:171748$9968 + cell $and $and$libresoc.v:173380$10016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352665,10 +355162,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:171748$9968_Y + connect \Y $and$libresoc.v:173380$10016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:171749$9969 + cell $and $and$libresoc.v:173381$10017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352676,18 +355173,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:171749$9969_Y + connect \Y $and$libresoc.v:173381$10017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:171745$9964 + cell $pos $extend$libresoc.v:173377$10012 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:171745$9964_Y + connect \Y $extend$libresoc.v:173377$10012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:171747$9967 + cell $ge $ge$libresoc.v:173379$10015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352695,26 +355192,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:171747$9967_Y + connect \Y $ge$libresoc.v:173379$10015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:171746$9966 + cell $not $not$libresoc.v:173378$10014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:171746$9966_Y + connect \Y $not$libresoc.v:173378$10014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:171745$9965 + cell $pos $pos$libresoc.v:173377$10013 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:171745$9964_Y - connect \Y $pos$libresoc.v:171745$9965_Y + connect \A $extend$libresoc.v:173377$10012_Y + connect \Y $pos$libresoc.v:173377$10013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:171744$9963 + cell $sshl $sshl$libresoc.v:173376$10011 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352722,17 +355219,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:171744$9963_Y + connect \Y $sshl$libresoc.v:173376$10011_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171816.18-171820.4" + attribute \src "libresoc.v:173448.18-173452.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:171821.18-171827.4" + attribute \src "libresoc.v:173453.18-173459.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -352741,528 +355238,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:171828.10-171831.4" + attribute \src "libresoc.v:173460.10-173463.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171832.10-171835.4" + attribute \src "libresoc.v:173464.10-173467.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171171.7-171171.20" - process $proc$libresoc.v:171171$10157 + attribute \src "libresoc.v:172803.7-172803.20" + process $proc$libresoc.v:172803$10205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171193.7-171193.30" - process $proc$libresoc.v:171193$10158 + attribute \src "libresoc.v:172825.7-172825.30" + process $proc$libresoc.v:172825$10206 assign { } { } - assign $0\div_by_zero$54[0:0]$10159 1'0 + assign $0\div_by_zero$54[0:0]$10207 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10159 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 end - attribute \src "libresoc.v:171217.7-171217.32" - process $proc$libresoc.v:171217$10160 + attribute \src "libresoc.v:172849.7-172849.32" + process $proc$libresoc.v:172849$10208 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10161 1'0 + assign $0\dive_abs_ov32$52[0:0]$10209 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10161 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 end - attribute \src "libresoc.v:171225.7-171225.32" - process $proc$libresoc.v:171225$10162 + attribute \src "libresoc.v:172857.7-172857.32" + process $proc$libresoc.v:172857$10210 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10163 1'0 + assign $0\dive_abs_ov64$53[0:0]$10211 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10163 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 end - attribute \src "libresoc.v:171231.15-171231.68" - process $proc$libresoc.v:171231$10164 + attribute \src "libresoc.v:172863.15-172863.68" + process $proc$libresoc.v:172863$10212 assign { } { } - assign $0\dividend$68[127:0]$10165 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$10165 + update \dividend$68 $0\dividend$68[127:0]$10213 end - attribute \src "libresoc.v:171239.7-171239.31" - process $proc$libresoc.v:171239$10166 + attribute \src "libresoc.v:172871.7-172871.31" + process $proc$libresoc.v:172871$10214 assign { } { } - assign $0\dividend_neg$51[0:0]$10167 1'0 + assign $0\dividend_neg$51[0:0]$10215 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10167 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 end - attribute \src "libresoc.v:171247.7-171247.30" - process $proc$libresoc.v:171247$10168 + attribute \src "libresoc.v:172879.7-172879.30" + process $proc$libresoc.v:172879$10216 assign { } { } - assign $0\divisor_neg$50[0:0]$10169 1'0 + assign $0\divisor_neg$50[0:0]$10217 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10169 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 end - attribute \src "libresoc.v:171253.14-171253.58" - process $proc$libresoc.v:171253$10170 + attribute \src "libresoc.v:172885.14-172885.58" + process $proc$libresoc.v:172885$10218 assign { } { } - assign $0\divisor_radicand$65[63:0]$10171 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10171 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 end - attribute \src "libresoc.v:171257.7-171257.19" - process $proc$libresoc.v:171257$10172 + attribute \src "libresoc.v:172889.7-172889.19" + process $proc$libresoc.v:172889$10220 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:171265.13-171265.45" - process $proc$libresoc.v:171265$10173 + attribute \src "libresoc.v:172897.13-172897.45" + process $proc$libresoc.v:172897$10221 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10174 4'0000 + assign $0\logical_op__data_len$45[3:0]$10222 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10174 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 end - attribute \src "libresoc.v:171318.14-171318.49" - process $proc$libresoc.v:171318$10175 + attribute \src "libresoc.v:172950.14-172950.49" + process $proc$libresoc.v:172950$10223 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10176 14'00000000000000 + assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10176 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 end - attribute \src "libresoc.v:171324.14-171324.68" - process $proc$libresoc.v:171324$10177 + attribute \src "libresoc.v:172956.14-172956.68" + process $proc$libresoc.v:172956$10225 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10178 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 end - attribute \src "libresoc.v:171332.7-171332.43" - process $proc$libresoc.v:171332$10179 + attribute \src "libresoc.v:172964.7-172964.43" + process $proc$libresoc.v:172964$10227 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10180 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10180 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 end - attribute \src "libresoc.v:171354.13-171354.48" - process $proc$libresoc.v:171354$10181 + attribute \src "libresoc.v:172986.13-172986.48" + process $proc$libresoc.v:172986$10229 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10182 2'00 + assign $0\logical_op__input_carry$39[1:0]$10230 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10182 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 end - attribute \src "libresoc.v:171362.14-171362.43" - process $proc$libresoc.v:171362$10183 + attribute \src "libresoc.v:172994.14-172994.43" + process $proc$libresoc.v:172994$10231 assign { } { } - assign $0\logical_op__insn$46[31:0]$10184 0 + assign $0\logical_op__insn$46[31:0]$10232 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10184 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 end - attribute \src "libresoc.v:171595.13-171595.47" - process $proc$libresoc.v:171595$10185 + attribute \src "libresoc.v:173227.13-173227.47" + process $proc$libresoc.v:173227$10233 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10186 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10186 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 end - attribute \src "libresoc.v:171603.7-171603.40" - process $proc$libresoc.v:171603$10187 + attribute \src "libresoc.v:173235.7-173235.40" + process $proc$libresoc.v:173235$10235 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10188 1'0 + assign $0\logical_op__invert_in$37[0:0]$10236 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10188 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 end - attribute \src "libresoc.v:171611.7-171611.41" - process $proc$libresoc.v:171611$10189 + attribute \src "libresoc.v:173243.7-173243.41" + process $proc$libresoc.v:173243$10237 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10190 1'0 + assign $0\logical_op__invert_out$40[0:0]$10238 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10190 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 end - attribute \src "libresoc.v:171619.7-171619.39" - process $proc$libresoc.v:171619$10191 + attribute \src "libresoc.v:173251.7-173251.39" + process $proc$libresoc.v:173251$10239 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10192 1'0 + assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10192 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 end - attribute \src "libresoc.v:171627.7-171627.40" - process $proc$libresoc.v:171627$10193 + attribute \src "libresoc.v:173259.7-173259.40" + process $proc$libresoc.v:173259$10241 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10194 1'0 + assign $0\logical_op__is_signed$44[0:0]$10242 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10194 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 end - attribute \src "libresoc.v:171633.7-171633.37" - process $proc$libresoc.v:171633$10195 + attribute \src "libresoc.v:173265.7-173265.37" + process $proc$libresoc.v:173265$10243 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10196 1'0 + assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10196 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 end - attribute \src "libresoc.v:171641.7-171641.37" - process $proc$libresoc.v:171641$10197 + attribute \src "libresoc.v:173273.7-173273.37" + process $proc$libresoc.v:173273$10245 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10198 1'0 + assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10198 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 end - attribute \src "libresoc.v:171651.7-171651.43" - process $proc$libresoc.v:171651$10199 + attribute \src "libresoc.v:173283.7-173283.43" + process $proc$libresoc.v:173283$10247 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10200 1'0 + assign $0\logical_op__output_carry$42[0:0]$10248 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10200 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 end - attribute \src "libresoc.v:171657.7-171657.37" - process $proc$libresoc.v:171657$10201 + attribute \src "libresoc.v:173289.7-173289.37" + process $proc$libresoc.v:173289$10249 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10202 1'0 + assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10202 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 end - attribute \src "libresoc.v:171665.7-171665.37" - process $proc$libresoc.v:171665$10203 + attribute \src "libresoc.v:173297.7-173297.37" + process $proc$libresoc.v:173297$10251 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10204 1'0 + assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10204 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 end - attribute \src "libresoc.v:171675.7-171675.40" - process $proc$libresoc.v:171675$10205 + attribute \src "libresoc.v:173307.7-173307.40" + process $proc$libresoc.v:173307$10253 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10206 1'0 + assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10206 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 end - attribute \src "libresoc.v:171683.7-171683.37" - process $proc$libresoc.v:171683$10207 + attribute \src "libresoc.v:173315.7-173315.37" + process $proc$libresoc.v:173315$10255 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10208 1'0 + assign $0\logical_op__zero_a$38[0:0]$10256 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10208 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 end - attribute \src "libresoc.v:171691.13-171691.30" - process $proc$libresoc.v:171691$10209 + attribute \src "libresoc.v:173323.13-173323.30" + process $proc$libresoc.v:173323$10257 assign { } { } - assign $0\muxid$28[1:0]$10210 2'00 + assign $0\muxid$28[1:0]$10258 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10210 + update \muxid$28 $0\muxid$28[1:0]$10258 end - attribute \src "libresoc.v:171701.13-171701.34" - process $proc$libresoc.v:171701$10211 + attribute \src "libresoc.v:173333.13-173333.34" + process $proc$libresoc.v:173333$10259 assign { } { } - assign $0\operation$69[1:0]$10212 2'00 + assign $0\operation$69[1:0]$10260 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$10212 + update \operation$69 $0\operation$69[1:0]$10260 end - attribute \src "libresoc.v:171715.14-171715.44" - process $proc$libresoc.v:171715$10213 + attribute \src "libresoc.v:173347.14-173347.44" + process $proc$libresoc.v:173347$10261 assign { } { } - assign $0\ra$47[63:0]$10214 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$10214 + update \ra$47 $0\ra$47[63:0]$10262 end - attribute \src "libresoc.v:171723.14-171723.44" - process $proc$libresoc.v:171723$10215 + attribute \src "libresoc.v:173355.14-173355.44" + process $proc$libresoc.v:173355$10263 assign { } { } - assign $0\rb$48[63:0]$10216 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10216 + update \rb$48 $0\rb$48[63:0]$10264 end - attribute \src "libresoc.v:171729.15-171729.84" - process $proc$libresoc.v:171729$10217 + attribute \src "libresoc.v:173361.15-173361.84" + process $proc$libresoc.v:173361$10265 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:171733.13-171733.45" - process $proc$libresoc.v:171733$10218 + attribute \src "libresoc.v:173365.13-173365.45" + process $proc$libresoc.v:173365$10266 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:171741.7-171741.25" - process $proc$libresoc.v:171741$10219 + attribute \src "libresoc.v:173373.7-173373.25" + process $proc$libresoc.v:173373$10267 assign { } { } - assign $0\xer_so$49[0:0]$10220 1'0 + assign $0\xer_so$49[0:0]$10268 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10220 + update \xer_so$49 $0\xer_so$49[0:0]$10268 end - attribute \src "libresoc.v:171750.3-171751.43" - process $proc$libresoc.v:171750$9970 + attribute \src "libresoc.v:173382.3-173383.43" + process $proc$libresoc.v:173382$10018 assign { } { } - assign $0\operation$69[1:0]$9971 \operation$69$next + assign $0\operation$69[1:0]$10019 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9971 + update \operation$69 $0\operation$69[1:0]$10019 end - attribute \src "libresoc.v:171752.3-171753.57" - process $proc$libresoc.v:171752$9972 + attribute \src "libresoc.v:173384.3-173385.57" + process $proc$libresoc.v:173384$10020 assign { } { } - assign $0\divisor_radicand$65[63:0]$9973 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9973 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 end - attribute \src "libresoc.v:171754.3-171755.41" - process $proc$libresoc.v:171754$9974 + attribute \src "libresoc.v:173386.3-173387.41" + process $proc$libresoc.v:173386$10022 assign { } { } - assign $0\dividend$68[127:0]$9975 \dividend$68$next + assign $0\dividend$68[127:0]$10023 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9975 + update \dividend$68 $0\dividend$68[127:0]$10023 end - attribute \src "libresoc.v:171756.3-171757.47" - process $proc$libresoc.v:171756$9976 + attribute \src "libresoc.v:173388.3-173389.47" + process $proc$libresoc.v:173388$10024 assign { } { } - assign $0\div_by_zero$54[0:0]$9977 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9977 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 end - attribute \src "libresoc.v:171758.3-171759.51" - process $proc$libresoc.v:171758$9978 + attribute \src "libresoc.v:173390.3-173391.51" + process $proc$libresoc.v:173390$10026 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9979 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9979 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 end - attribute \src "libresoc.v:171760.3-171761.51" - process $proc$libresoc.v:171760$9980 + attribute \src "libresoc.v:173392.3-173393.51" + process $proc$libresoc.v:173392$10028 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9981 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9981 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 end - attribute \src "libresoc.v:171762.3-171763.49" - process $proc$libresoc.v:171762$9982 + attribute \src "libresoc.v:173394.3-173395.49" + process $proc$libresoc.v:173394$10030 assign { } { } - assign $0\dividend_neg$51[0:0]$9983 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9983 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 end - attribute \src "libresoc.v:171764.3-171765.47" - process $proc$libresoc.v:171764$9984 + attribute \src "libresoc.v:173396.3-173397.47" + process $proc$libresoc.v:173396$10032 assign { } { } - assign $0\divisor_neg$50[0:0]$9985 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9985 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 end - attribute \src "libresoc.v:171766.3-171767.37" - process $proc$libresoc.v:171766$9986 + attribute \src "libresoc.v:173398.3-173399.37" + process $proc$libresoc.v:173398$10034 assign { } { } - assign $0\xer_so$49[0:0]$9987 \xer_so$49$next + assign $0\xer_so$49[0:0]$10035 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9987 + update \xer_so$49 $0\xer_so$49[0:0]$10035 end - attribute \src "libresoc.v:171768.3-171769.29" - process $proc$libresoc.v:171768$9988 + attribute \src "libresoc.v:173400.3-173401.29" + process $proc$libresoc.v:173400$10036 assign { } { } - assign $0\rb$48[63:0]$9989 \rb$48$next + assign $0\rb$48[63:0]$10037 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9989 + update \rb$48 $0\rb$48[63:0]$10037 end - attribute \src "libresoc.v:171770.3-171771.29" - process $proc$libresoc.v:171770$9990 + attribute \src "libresoc.v:173402.3-173403.29" + process $proc$libresoc.v:173402$10038 assign { } { } - assign $0\ra$47[63:0]$9991 \ra$47$next + assign $0\ra$47[63:0]$10039 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9991 + update \ra$47 $0\ra$47[63:0]$10039 end - attribute \src "libresoc.v:171772.3-171773.67" - process $proc$libresoc.v:171772$9992 + attribute \src "libresoc.v:173404.3-173405.67" + process $proc$libresoc.v:173404$10040 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9993 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9993 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 end - attribute \src "libresoc.v:171774.3-171775.63" - process $proc$libresoc.v:171774$9994 + attribute \src "libresoc.v:173406.3-173407.63" + process $proc$libresoc.v:173406$10042 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$9995 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9995 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 end - attribute \src "libresoc.v:171776.3-171777.77" - process $proc$libresoc.v:171776$9996 + attribute \src "libresoc.v:173408.3-173409.77" + process $proc$libresoc.v:173408$10044 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9997 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9997 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 end - attribute \src "libresoc.v:171778.3-171779.73" - process $proc$libresoc.v:171778$9998 + attribute \src "libresoc.v:173410.3-173411.73" + process $proc$libresoc.v:173410$10046 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9999 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9999 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 end - attribute \src "libresoc.v:171780.3-171781.61" - process $proc$libresoc.v:171780$10000 + attribute \src "libresoc.v:173412.3-173413.61" + process $proc$libresoc.v:173412$10048 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10001 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10001 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 end - attribute \src "libresoc.v:171782.3-171783.61" - process $proc$libresoc.v:171782$10002 + attribute \src "libresoc.v:173414.3-173415.61" + process $proc$libresoc.v:173414$10050 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10003 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10003 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 end - attribute \src "libresoc.v:171784.3-171785.61" - process $proc$libresoc.v:171784$10004 + attribute \src "libresoc.v:173416.3-173417.61" + process $proc$libresoc.v:173416$10052 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10005 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10005 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 end - attribute \src "libresoc.v:171786.3-171787.61" - process $proc$libresoc.v:171786$10006 + attribute \src "libresoc.v:173418.3-173419.61" + process $proc$libresoc.v:173418$10054 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10007 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10007 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 end - attribute \src "libresoc.v:171788.3-171789.67" - process $proc$libresoc.v:171788$10008 + attribute \src "libresoc.v:173420.3-173421.67" + process $proc$libresoc.v:173420$10056 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10009 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10009 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 end - attribute \src "libresoc.v:171790.3-171791.61" - process $proc$libresoc.v:171790$10010 + attribute \src "libresoc.v:173422.3-173423.61" + process $proc$libresoc.v:173422$10058 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10011 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10011 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 end - attribute \src "libresoc.v:171792.3-171793.71" - process $proc$libresoc.v:171792$10012 + attribute \src "libresoc.v:173424.3-173425.71" + process $proc$libresoc.v:173424$10060 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10013 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10013 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 end - attribute \src "libresoc.v:171794.3-171795.69" - process $proc$libresoc.v:171794$10014 + attribute \src "libresoc.v:173426.3-173427.69" + process $proc$libresoc.v:173426$10062 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10015 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10015 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 end - attribute \src "libresoc.v:171796.3-171797.67" - process $proc$libresoc.v:171796$10016 + attribute \src "libresoc.v:173428.3-173429.67" + process $proc$libresoc.v:173428$10064 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10017 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10017 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 end - attribute \src "libresoc.v:171798.3-171799.73" - process $proc$libresoc.v:171798$10018 + attribute \src "libresoc.v:173430.3-173431.73" + process $proc$libresoc.v:173430$10066 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10019 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10019 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 end - attribute \src "libresoc.v:171800.3-171801.65" - process $proc$libresoc.v:171800$10020 + attribute \src "libresoc.v:173432.3-173433.65" + process $proc$libresoc.v:173432$10068 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10021 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10021 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 end - attribute \src "libresoc.v:171802.3-171803.67" - process $proc$libresoc.v:171802$10022 + attribute \src "libresoc.v:173434.3-173435.67" + process $proc$libresoc.v:173434$10070 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10023 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10023 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 end - attribute \src "libresoc.v:171804.3-171805.65" - process $proc$libresoc.v:171804$10024 + attribute \src "libresoc.v:173436.3-173437.65" + process $proc$libresoc.v:173436$10072 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10025 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10025 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 end - attribute \src "libresoc.v:171806.3-171807.57" - process $proc$libresoc.v:171806$10026 + attribute \src "libresoc.v:173438.3-173439.57" + process $proc$libresoc.v:173438$10074 assign { } { } - assign $0\logical_op__insn$46[31:0]$10027 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10027 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 end - attribute \src "libresoc.v:171808.3-171809.35" - process $proc$libresoc.v:171808$10028 + attribute \src "libresoc.v:173440.3-173441.35" + process $proc$libresoc.v:173440$10076 assign { } { } - assign $0\muxid$28[1:0]$10029 \muxid$28$next + assign $0\muxid$28[1:0]$10077 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$10029 + update \muxid$28 $0\muxid$28[1:0]$10077 end - attribute \src "libresoc.v:171810.3-171811.27" - process $proc$libresoc.v:171810$10030 + attribute \src "libresoc.v:173442.3-173443.27" + process $proc$libresoc.v:173442$10078 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:171812.3-171813.75" - process $proc$libresoc.v:171812$10031 + attribute \src "libresoc.v:173444.3-173445.75" + process $proc$libresoc.v:173444$10079 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:171814.3-171815.65" - process $proc$libresoc.v:171814$10032 + attribute \src "libresoc.v:173446.3-173447.65" + process $proc$libresoc.v:173446$10080 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:171836.3-171844.6" - process $proc$libresoc.v:171836$10033 + attribute \src "libresoc.v:173468.3-173476.6" + process $proc$libresoc.v:173468$10081 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$10034 $1\saved_state_q_bits_known$next[6:0]$10035 - attribute \src "libresoc.v:171837.5-171837.29" + assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 + attribute \src "libresoc.v:173469.5-173469.29" switch \initial - attribute \src "libresoc.v:171837.9-171837.17" + attribute \src "libresoc.v:173469.9-173469.17" case 1'1 case end @@ -353271,21 +355768,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$10035 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$10083 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$10035 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$10083 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10034 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 end - attribute \src "libresoc.v:171845.3-171853.6" - process $proc$libresoc.v:171845$10036 + attribute \src "libresoc.v:173477.3-173485.6" + process $proc$libresoc.v:173477$10084 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$10037 $1\saved_state_dividend_quotient$next[127:0]$10038 - attribute \src "libresoc.v:171846.5-171846.29" + assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 + attribute \src "libresoc.v:173478.5-173478.29" switch \initial - attribute \src "libresoc.v:171846.9-171846.17" + attribute \src "libresoc.v:173478.9-173478.17" case 1'1 case end @@ -353294,20 +355791,20 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$10038 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$10086 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$10038 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$10086 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10037 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 end - attribute \src "libresoc.v:171854.3-171865.6" - process $proc$libresoc.v:171854$10039 + attribute \src "libresoc.v:173486.3-173497.6" + process $proc$libresoc.v:173486$10087 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:171855.5-171855.29" + attribute \src "libresoc.v:173487.5-173487.29" switch \initial - attribute \src "libresoc.v:171855.9-171855.17" + attribute \src "libresoc.v:173487.9-173487.17" case 1'1 case end @@ -353325,13 +355822,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:171866.3-171877.6" - process $proc$libresoc.v:171866$10040 + attribute \src "libresoc.v:173498.3-173509.6" + process $proc$libresoc.v:173498$10088 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:171867.5-171867.29" + attribute \src "libresoc.v:173499.5-173499.29" switch \initial - attribute \src "libresoc.v:171867.9-171867.17" + attribute \src "libresoc.v:173499.9-173499.17" case 1'1 case end @@ -353349,13 +355846,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:171878.3-171889.6" - process $proc$libresoc.v:171878$10041 + attribute \src "libresoc.v:173510.3-173521.6" + process $proc$libresoc.v:173510$10089 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:171879.5-171879.29" + attribute \src "libresoc.v:173511.5-173511.29" switch \initial - attribute \src "libresoc.v:171879.9-171879.17" + attribute \src "libresoc.v:173511.9-173511.17" case 1'1 case end @@ -353373,15 +355870,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:171890.3-171917.6" - process $proc$libresoc.v:171890$10042 + attribute \src "libresoc.v:173522.3-173549.6" + process $proc$libresoc.v:173522$10090 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$10043 $4\empty$next[0:0]$10047 - attribute \src "libresoc.v:171891.5-171891.29" + assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 + attribute \src "libresoc.v:173523.5-173523.29" switch \initial - attribute \src "libresoc.v:171891.9-171891.17" + attribute \src "libresoc.v:173523.9-173523.17" case 1'1 case end @@ -353390,28 +355887,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$10044 $2\empty$next[0:0]$10045 + assign $1\empty$next[0:0]$10092 $2\empty$next[0:0]$10093 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$10045 1'0 + assign $2\empty$next[0:0]$10093 1'0 case - assign $2\empty$next[0:0]$10045 \empty + assign $2\empty$next[0:0]$10093 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$10044 $3\empty$next[0:0]$10046 + assign $1\empty$next[0:0]$10092 $3\empty$next[0:0]$10094 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$10046 1'1 + assign $3\empty$next[0:0]$10094 1'1 case - assign $3\empty$next[0:0]$10046 \empty + assign $3\empty$next[0:0]$10094 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -353419,21 +355916,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10047 1'1 + assign $4\empty$next[0:0]$10095 1'1 case - assign $4\empty$next[0:0]$10047 $1\empty$next[0:0]$10044 + assign $4\empty$next[0:0]$10095 $1\empty$next[0:0]$10092 end sync always - update \empty$next $0\empty$next[0:0]$10043 + update \empty$next $0\empty$next[0:0]$10091 end - attribute \src "libresoc.v:171918.3-171932.6" - process $proc$libresoc.v:171918$10048 + attribute \src "libresoc.v:173550.3-173564.6" + process $proc$libresoc.v:173550$10096 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10049 $1\muxid$28$next[1:0]$10050 - attribute \src "libresoc.v:171919.5-171919.29" + assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 + attribute \src "libresoc.v:173551.5-173551.29" switch \initial - attribute \src "libresoc.v:171919.9-171919.17" + attribute \src "libresoc.v:173551.9-173551.17" case 1'1 case end @@ -353442,24 +355939,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$10050 $2\muxid$28$next[1:0]$10051 + assign $1\muxid$28$next[1:0]$10098 $2\muxid$28$next[1:0]$10099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$10051 \muxid + assign $2\muxid$28$next[1:0]$10099 \muxid case - assign $2\muxid$28$next[1:0]$10051 \muxid$28 + assign $2\muxid$28$next[1:0]$10099 \muxid$28 end case - assign $1\muxid$28$next[1:0]$10050 \muxid$28 + assign $1\muxid$28$next[1:0]$10098 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10049 + update \muxid$28$next $0\muxid$28$next[1:0]$10097 end - attribute \src "libresoc.v:171933.3-171976.6" - process $proc$libresoc.v:171933$10052 + attribute \src "libresoc.v:173565.3-173608.6" + process $proc$libresoc.v:173565$10100 assign { } { } assign { } { } assign { } { } @@ -353496,33 +355993,33 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10053 $1\logical_op__data_len$45$next[3:0]$10071 - assign $0\logical_op__fn_unit$30$next[13:0]$10054 $1\logical_op__fn_unit$30$next[13:0]$10072 + assign $0\logical_op__data_len$45$next[3:0]$10101 $1\logical_op__data_len$45$next[3:0]$10119 + assign $0\logical_op__fn_unit$30$next[13:0]$10102 $1\logical_op__fn_unit$30$next[13:0]$10120 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10057 $1\logical_op__input_carry$39$next[1:0]$10075 - assign $0\logical_op__insn$46$next[31:0]$10058 $1\logical_op__insn$46$next[31:0]$10076 - assign $0\logical_op__insn_type$29$next[6:0]$10059 $1\logical_op__insn_type$29$next[6:0]$10077 - assign $0\logical_op__invert_in$37$next[0:0]$10060 $1\logical_op__invert_in$37$next[0:0]$10078 - assign $0\logical_op__invert_out$40$next[0:0]$10061 $1\logical_op__invert_out$40$next[0:0]$10079 - assign $0\logical_op__is_32bit$43$next[0:0]$10062 $1\logical_op__is_32bit$43$next[0:0]$10080 - assign $0\logical_op__is_signed$44$next[0:0]$10063 $1\logical_op__is_signed$44$next[0:0]$10081 + assign $0\logical_op__input_carry$39$next[1:0]$10105 $1\logical_op__input_carry$39$next[1:0]$10123 + assign $0\logical_op__insn$46$next[31:0]$10106 $1\logical_op__insn$46$next[31:0]$10124 + assign $0\logical_op__insn_type$29$next[6:0]$10107 $1\logical_op__insn_type$29$next[6:0]$10125 + assign $0\logical_op__invert_in$37$next[0:0]$10108 $1\logical_op__invert_in$37$next[0:0]$10126 + assign $0\logical_op__invert_out$40$next[0:0]$10109 $1\logical_op__invert_out$40$next[0:0]$10127 + assign $0\logical_op__is_32bit$43$next[0:0]$10110 $1\logical_op__is_32bit$43$next[0:0]$10128 + assign $0\logical_op__is_signed$44$next[0:0]$10111 $1\logical_op__is_signed$44$next[0:0]$10129 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10066 $1\logical_op__output_carry$42$next[0:0]$10084 + assign $0\logical_op__output_carry$42$next[0:0]$10114 $1\logical_op__output_carry$42$next[0:0]$10132 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10069 $1\logical_op__write_cr0$41$next[0:0]$10087 - assign $0\logical_op__zero_a$38$next[0:0]$10070 $1\logical_op__zero_a$38$next[0:0]$10088 - assign $0\logical_op__imm_data__data$31$next[63:0]$10055 $3\logical_op__imm_data__data$31$next[63:0]$10107 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10056 $3\logical_op__imm_data__ok$32$next[0:0]$10108 - assign $0\logical_op__oe__oe$35$next[0:0]$10064 $3\logical_op__oe__oe$35$next[0:0]$10109 - assign $0\logical_op__oe__ok$36$next[0:0]$10065 $3\logical_op__oe__ok$36$next[0:0]$10110 - assign $0\logical_op__rc__ok$34$next[0:0]$10067 $3\logical_op__rc__ok$34$next[0:0]$10111 - assign $0\logical_op__rc__rc$33$next[0:0]$10068 $3\logical_op__rc__rc$33$next[0:0]$10112 - attribute \src "libresoc.v:171934.5-171934.29" + assign $0\logical_op__write_cr0$41$next[0:0]$10117 $1\logical_op__write_cr0$41$next[0:0]$10135 + assign $0\logical_op__zero_a$38$next[0:0]$10118 $1\logical_op__zero_a$38$next[0:0]$10136 + assign $0\logical_op__imm_data__data$31$next[63:0]$10103 $3\logical_op__imm_data__data$31$next[63:0]$10155 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10104 $3\logical_op__imm_data__ok$32$next[0:0]$10156 + assign $0\logical_op__oe__oe$35$next[0:0]$10112 $3\logical_op__oe__oe$35$next[0:0]$10157 + assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 + assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 + assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 + attribute \src "libresoc.v:173566.5-173566.29" switch \initial - attribute \src "libresoc.v:171934.9-171934.17" + attribute \src "libresoc.v:173566.9-173566.17" case 1'1 case end @@ -353548,24 +356045,24 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10071 $2\logical_op__data_len$45$next[3:0]$10089 - assign $1\logical_op__fn_unit$30$next[13:0]$10072 $2\logical_op__fn_unit$30$next[13:0]$10090 - assign $1\logical_op__imm_data__data$31$next[63:0]$10073 $2\logical_op__imm_data__data$31$next[63:0]$10091 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 $2\logical_op__imm_data__ok$32$next[0:0]$10092 - assign $1\logical_op__input_carry$39$next[1:0]$10075 $2\logical_op__input_carry$39$next[1:0]$10093 - assign $1\logical_op__insn$46$next[31:0]$10076 $2\logical_op__insn$46$next[31:0]$10094 - assign $1\logical_op__insn_type$29$next[6:0]$10077 $2\logical_op__insn_type$29$next[6:0]$10095 - assign $1\logical_op__invert_in$37$next[0:0]$10078 $2\logical_op__invert_in$37$next[0:0]$10096 - assign $1\logical_op__invert_out$40$next[0:0]$10079 $2\logical_op__invert_out$40$next[0:0]$10097 - assign $1\logical_op__is_32bit$43$next[0:0]$10080 $2\logical_op__is_32bit$43$next[0:0]$10098 - assign $1\logical_op__is_signed$44$next[0:0]$10081 $2\logical_op__is_signed$44$next[0:0]$10099 - assign $1\logical_op__oe__oe$35$next[0:0]$10082 $2\logical_op__oe__oe$35$next[0:0]$10100 - assign $1\logical_op__oe__ok$36$next[0:0]$10083 $2\logical_op__oe__ok$36$next[0:0]$10101 - assign $1\logical_op__output_carry$42$next[0:0]$10084 $2\logical_op__output_carry$42$next[0:0]$10102 - assign $1\logical_op__rc__ok$34$next[0:0]$10085 $2\logical_op__rc__ok$34$next[0:0]$10103 - assign $1\logical_op__rc__rc$33$next[0:0]$10086 $2\logical_op__rc__rc$33$next[0:0]$10104 - assign $1\logical_op__write_cr0$41$next[0:0]$10087 $2\logical_op__write_cr0$41$next[0:0]$10105 - assign $1\logical_op__zero_a$38$next[0:0]$10088 $2\logical_op__zero_a$38$next[0:0]$10106 + assign $1\logical_op__data_len$45$next[3:0]$10119 $2\logical_op__data_len$45$next[3:0]$10137 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 $2\logical_op__fn_unit$30$next[13:0]$10138 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 $2\logical_op__imm_data__data$31$next[63:0]$10139 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 $2\logical_op__imm_data__ok$32$next[0:0]$10140 + assign $1\logical_op__input_carry$39$next[1:0]$10123 $2\logical_op__input_carry$39$next[1:0]$10141 + assign $1\logical_op__insn$46$next[31:0]$10124 $2\logical_op__insn$46$next[31:0]$10142 + assign $1\logical_op__insn_type$29$next[6:0]$10125 $2\logical_op__insn_type$29$next[6:0]$10143 + assign $1\logical_op__invert_in$37$next[0:0]$10126 $2\logical_op__invert_in$37$next[0:0]$10144 + assign $1\logical_op__invert_out$40$next[0:0]$10127 $2\logical_op__invert_out$40$next[0:0]$10145 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 $2\logical_op__is_32bit$43$next[0:0]$10146 + assign $1\logical_op__is_signed$44$next[0:0]$10129 $2\logical_op__is_signed$44$next[0:0]$10147 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 $2\logical_op__oe__oe$35$next[0:0]$10148 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 $2\logical_op__oe__ok$36$next[0:0]$10149 + assign $1\logical_op__output_carry$42$next[0:0]$10132 $2\logical_op__output_carry$42$next[0:0]$10150 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 $2\logical_op__rc__ok$34$next[0:0]$10151 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 $2\logical_op__rc__rc$33$next[0:0]$10152 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 $2\logical_op__write_cr0$41$next[0:0]$10153 + assign $1\logical_op__zero_a$38$next[0:0]$10136 $2\logical_op__zero_a$38$next[0:0]$10154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -353588,46 +356085,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10094 $2\logical_op__data_len$45$next[3:0]$10089 $2\logical_op__is_signed$44$next[0:0]$10099 $2\logical_op__is_32bit$43$next[0:0]$10098 $2\logical_op__output_carry$42$next[0:0]$10102 $2\logical_op__write_cr0$41$next[0:0]$10105 $2\logical_op__invert_out$40$next[0:0]$10097 $2\logical_op__input_carry$39$next[1:0]$10093 $2\logical_op__zero_a$38$next[0:0]$10106 $2\logical_op__invert_in$37$next[0:0]$10096 $2\logical_op__oe__ok$36$next[0:0]$10101 $2\logical_op__oe__oe$35$next[0:0]$10100 $2\logical_op__rc__ok$34$next[0:0]$10103 $2\logical_op__rc__rc$33$next[0:0]$10104 $2\logical_op__imm_data__ok$32$next[0:0]$10092 $2\logical_op__imm_data__data$31$next[63:0]$10091 $2\logical_op__fn_unit$30$next[13:0]$10090 $2\logical_op__insn_type$29$next[6:0]$10095 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$10142 $2\logical_op__data_len$45$next[3:0]$10137 $2\logical_op__is_signed$44$next[0:0]$10147 $2\logical_op__is_32bit$43$next[0:0]$10146 $2\logical_op__output_carry$42$next[0:0]$10150 $2\logical_op__write_cr0$41$next[0:0]$10153 $2\logical_op__invert_out$40$next[0:0]$10145 $2\logical_op__input_carry$39$next[1:0]$10141 $2\logical_op__zero_a$38$next[0:0]$10154 $2\logical_op__invert_in$37$next[0:0]$10144 $2\logical_op__oe__ok$36$next[0:0]$10149 $2\logical_op__oe__oe$35$next[0:0]$10148 $2\logical_op__rc__ok$34$next[0:0]$10151 $2\logical_op__rc__rc$33$next[0:0]$10152 $2\logical_op__imm_data__ok$32$next[0:0]$10140 $2\logical_op__imm_data__data$31$next[63:0]$10139 $2\logical_op__fn_unit$30$next[13:0]$10138 $2\logical_op__insn_type$29$next[6:0]$10143 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$10089 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[13:0]$10090 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10091 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10092 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10093 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10094 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10095 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10096 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10097 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10098 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10099 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10100 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10101 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10102 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10103 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10104 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10105 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10106 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$10137 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10138 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10139 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10140 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10141 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10142 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10143 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10144 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10145 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10146 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10147 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10148 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10149 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10150 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10151 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10152 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10153 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10154 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$10071 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[13:0]$10072 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10073 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10074 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10075 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10076 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10077 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10078 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10079 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10080 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10081 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10082 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10083 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10084 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10085 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10086 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10087 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10088 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$10119 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10120 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10121 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10123 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10124 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10125 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10126 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10127 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10128 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10129 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10130 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10131 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10132 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10133 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10134 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10135 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10136 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -353639,48 +356136,48 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10107 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10112 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10111 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10109 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10110 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$10107 $1\logical_op__imm_data__data$31$next[63:0]$10073 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10108 $1\logical_op__imm_data__ok$32$next[0:0]$10074 - assign $3\logical_op__oe__oe$35$next[0:0]$10109 $1\logical_op__oe__oe$35$next[0:0]$10082 - assign $3\logical_op__oe__ok$36$next[0:0]$10110 $1\logical_op__oe__ok$36$next[0:0]$10083 - assign $3\logical_op__rc__ok$34$next[0:0]$10111 $1\logical_op__rc__ok$34$next[0:0]$10085 - assign $3\logical_op__rc__rc$33$next[0:0]$10112 $1\logical_op__rc__rc$33$next[0:0]$10086 + assign $3\logical_op__imm_data__data$31$next[63:0]$10155 $1\logical_op__imm_data__data$31$next[63:0]$10121 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 $1\logical_op__imm_data__ok$32$next[0:0]$10122 + assign $3\logical_op__oe__oe$35$next[0:0]$10157 $1\logical_op__oe__oe$35$next[0:0]$10130 + assign $3\logical_op__oe__ok$36$next[0:0]$10158 $1\logical_op__oe__ok$36$next[0:0]$10131 + assign $3\logical_op__rc__ok$34$next[0:0]$10159 $1\logical_op__rc__ok$34$next[0:0]$10133 + assign $3\logical_op__rc__rc$33$next[0:0]$10160 $1\logical_op__rc__rc$33$next[0:0]$10134 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10053 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10054 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10055 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10056 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10057 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10058 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10059 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10060 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10061 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10062 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10063 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10064 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10065 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10066 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10067 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10068 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10069 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10070 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10101 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10102 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10103 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10104 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10105 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10106 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10107 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10108 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10109 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10110 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10111 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10112 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10113 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10114 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10115 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10116 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 end - attribute \src "libresoc.v:171977.3-171991.6" - process $proc$libresoc.v:171977$10113 + attribute \src "libresoc.v:173609.3-173623.6" + process $proc$libresoc.v:173609$10161 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10114 $1\ra$47$next[63:0]$10115 - attribute \src "libresoc.v:171978.5-171978.29" + assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 + attribute \src "libresoc.v:173610.5-173610.29" switch \initial - attribute \src "libresoc.v:171978.9-171978.17" + attribute \src "libresoc.v:173610.9-173610.17" case 1'1 case end @@ -353689,30 +356186,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$10115 $2\ra$47$next[63:0]$10116 + assign $1\ra$47$next[63:0]$10163 $2\ra$47$next[63:0]$10164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$10116 \ra + assign $2\ra$47$next[63:0]$10164 \ra case - assign $2\ra$47$next[63:0]$10116 \ra$47 + assign $2\ra$47$next[63:0]$10164 \ra$47 end case - assign $1\ra$47$next[63:0]$10115 \ra$47 + assign $1\ra$47$next[63:0]$10163 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$10114 + update \ra$47$next $0\ra$47$next[63:0]$10162 end - attribute \src "libresoc.v:171992.3-172006.6" - process $proc$libresoc.v:171992$10117 + attribute \src "libresoc.v:173624.3-173638.6" + process $proc$libresoc.v:173624$10165 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$10118 $1\rb$48$next[63:0]$10119 - attribute \src "libresoc.v:171993.5-171993.29" + assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 + attribute \src "libresoc.v:173625.5-173625.29" switch \initial - attribute \src "libresoc.v:171993.9-171993.17" + attribute \src "libresoc.v:173625.9-173625.17" case 1'1 case end @@ -353721,30 +356218,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$10119 $2\rb$48$next[63:0]$10120 + assign $1\rb$48$next[63:0]$10167 $2\rb$48$next[63:0]$10168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$10120 \rb + assign $2\rb$48$next[63:0]$10168 \rb case - assign $2\rb$48$next[63:0]$10120 \rb$48 + assign $2\rb$48$next[63:0]$10168 \rb$48 end case - assign $1\rb$48$next[63:0]$10119 \rb$48 + assign $1\rb$48$next[63:0]$10167 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$10118 + update \rb$48$next $0\rb$48$next[63:0]$10166 end - attribute \src "libresoc.v:172007.3-172021.6" - process $proc$libresoc.v:172007$10121 + attribute \src "libresoc.v:173639.3-173653.6" + process $proc$libresoc.v:173639$10169 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$10122 $1\xer_so$49$next[0:0]$10123 - attribute \src "libresoc.v:172008.5-172008.29" + assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 + attribute \src "libresoc.v:173640.5-173640.29" switch \initial - attribute \src "libresoc.v:172008.9-172008.17" + attribute \src "libresoc.v:173640.9-173640.17" case 1'1 case end @@ -353753,30 +356250,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10123 $2\xer_so$49$next[0:0]$10124 + assign $1\xer_so$49$next[0:0]$10171 $2\xer_so$49$next[0:0]$10172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$10124 \xer_so + assign $2\xer_so$49$next[0:0]$10172 \xer_so case - assign $2\xer_so$49$next[0:0]$10124 \xer_so$49 + assign $2\xer_so$49$next[0:0]$10172 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$10123 \xer_so$49 + assign $1\xer_so$49$next[0:0]$10171 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10122 + update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 end - attribute \src "libresoc.v:172022.3-172036.6" - process $proc$libresoc.v:172022$10125 + attribute \src "libresoc.v:173654.3-173668.6" + process $proc$libresoc.v:173654$10173 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10126 $1\divisor_neg$50$next[0:0]$10127 - attribute \src "libresoc.v:172023.5-172023.29" + assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 + attribute \src "libresoc.v:173655.5-173655.29" switch \initial - attribute \src "libresoc.v:172023.9-172023.17" + attribute \src "libresoc.v:173655.9-173655.17" case 1'1 case end @@ -353785,30 +356282,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10127 $2\divisor_neg$50$next[0:0]$10128 + assign $1\divisor_neg$50$next[0:0]$10175 $2\divisor_neg$50$next[0:0]$10176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$10128 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$10127 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$10175 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10126 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 end - attribute \src "libresoc.v:172037.3-172051.6" - process $proc$libresoc.v:172037$10129 + attribute \src "libresoc.v:173669.3-173683.6" + process $proc$libresoc.v:173669$10177 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$10130 $1\dividend_neg$51$next[0:0]$10131 - attribute \src "libresoc.v:172038.5-172038.29" + assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 + attribute \src "libresoc.v:173670.5-173670.29" switch \initial - attribute \src "libresoc.v:172038.9-172038.17" + attribute \src "libresoc.v:173670.9-173670.17" case 1'1 case end @@ -353817,30 +356314,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10131 $2\dividend_neg$51$next[0:0]$10132 + assign $1\dividend_neg$51$next[0:0]$10179 $2\dividend_neg$51$next[0:0]$10180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$10132 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$10131 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$10179 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10130 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 end - attribute \src "libresoc.v:172052.3-172066.6" - process $proc$libresoc.v:172052$10133 + attribute \src "libresoc.v:173684.3-173698.6" + process $proc$libresoc.v:173684$10181 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10134 $1\dive_abs_ov32$52$next[0:0]$10135 - attribute \src "libresoc.v:172053.5-172053.29" + assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 + attribute \src "libresoc.v:173685.5-173685.29" switch \initial - attribute \src "libresoc.v:172053.9-172053.17" + attribute \src "libresoc.v:173685.9-173685.17" case 1'1 case end @@ -353849,30 +356346,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10135 $2\dive_abs_ov32$52$next[0:0]$10136 + assign $1\dive_abs_ov32$52$next[0:0]$10183 $2\dive_abs_ov32$52$next[0:0]$10184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$10136 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$10135 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$10183 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10134 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 end - attribute \src "libresoc.v:172067.3-172081.6" - process $proc$libresoc.v:172067$10137 + attribute \src "libresoc.v:173699.3-173713.6" + process $proc$libresoc.v:173699$10185 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10138 $1\dive_abs_ov64$53$next[0:0]$10139 - attribute \src "libresoc.v:172068.5-172068.29" + assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 + attribute \src "libresoc.v:173700.5-173700.29" switch \initial - attribute \src "libresoc.v:172068.9-172068.17" + attribute \src "libresoc.v:173700.9-173700.17" case 1'1 case end @@ -353881,30 +356378,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10139 $2\dive_abs_ov64$53$next[0:0]$10140 + assign $1\dive_abs_ov64$53$next[0:0]$10187 $2\dive_abs_ov64$53$next[0:0]$10188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$10140 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$10139 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$10187 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10138 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 end - attribute \src "libresoc.v:172082.3-172096.6" - process $proc$libresoc.v:172082$10141 + attribute \src "libresoc.v:173714.3-173728.6" + process $proc$libresoc.v:173714$10189 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10142 $1\div_by_zero$54$next[0:0]$10143 - attribute \src "libresoc.v:172083.5-172083.29" + assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 + attribute \src "libresoc.v:173715.5-173715.29" switch \initial - attribute \src "libresoc.v:172083.9-172083.17" + attribute \src "libresoc.v:173715.9-173715.17" case 1'1 case end @@ -353913,30 +356410,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10143 $2\div_by_zero$54$next[0:0]$10144 + assign $1\div_by_zero$54$next[0:0]$10191 $2\div_by_zero$54$next[0:0]$10192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$10144 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$10143 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$10191 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10142 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 end - attribute \src "libresoc.v:172097.3-172111.6" - process $proc$libresoc.v:172097$10145 + attribute \src "libresoc.v:173729.3-173743.6" + process $proc$libresoc.v:173729$10193 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$10146 $1\dividend$68$next[127:0]$10147 - attribute \src "libresoc.v:172098.5-172098.29" + assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 + attribute \src "libresoc.v:173730.5-173730.29" switch \initial - attribute \src "libresoc.v:172098.9-172098.17" + attribute \src "libresoc.v:173730.9-173730.17" case 1'1 case end @@ -353945,30 +356442,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10147 $2\dividend$68$next[127:0]$10148 + assign $1\dividend$68$next[127:0]$10195 $2\dividend$68$next[127:0]$10196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$10148 \dividend + assign $2\dividend$68$next[127:0]$10196 \dividend case - assign $2\dividend$68$next[127:0]$10148 \dividend$68 + assign $2\dividend$68$next[127:0]$10196 \dividend$68 end case - assign $1\dividend$68$next[127:0]$10147 \dividend$68 + assign $1\dividend$68$next[127:0]$10195 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10146 + update \dividend$68$next $0\dividend$68$next[127:0]$10194 end - attribute \src "libresoc.v:172112.3-172126.6" - process $proc$libresoc.v:172112$10149 + attribute \src "libresoc.v:173744.3-173758.6" + process $proc$libresoc.v:173744$10197 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10150 $1\divisor_radicand$65$next[63:0]$10151 - attribute \src "libresoc.v:172113.5-172113.29" + assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 + attribute \src "libresoc.v:173745.5-173745.29" switch \initial - attribute \src "libresoc.v:172113.9-172113.17" + attribute \src "libresoc.v:173745.9-173745.17" case 1'1 case end @@ -353977,30 +356474,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10151 $2\divisor_radicand$65$next[63:0]$10152 + assign $1\divisor_radicand$65$next[63:0]$10199 $2\divisor_radicand$65$next[63:0]$10200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$10152 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$10151 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$10199 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10150 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 end - attribute \src "libresoc.v:172127.3-172141.6" - process $proc$libresoc.v:172127$10153 + attribute \src "libresoc.v:173759.3-173773.6" + process $proc$libresoc.v:173759$10201 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$10154 $1\operation$69$next[1:0]$10155 - attribute \src "libresoc.v:172128.5-172128.29" + assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 + attribute \src "libresoc.v:173760.5-173760.29" switch \initial - attribute \src "libresoc.v:172128.9-172128.17" + attribute \src "libresoc.v:173760.9-173760.17" case 1'1 case end @@ -354009,28 +356506,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10155 $2\operation$69$next[1:0]$10156 + assign $1\operation$69$next[1:0]$10203 $2\operation$69$next[1:0]$10204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$10156 \operation + assign $2\operation$69$next[1:0]$10204 \operation case - assign $2\operation$69$next[1:0]$10156 \operation$69 + assign $2\operation$69$next[1:0]$10204 \operation$69 end case - assign $1\operation$69$next[1:0]$10155 \operation$69 + assign $1\operation$69$next[1:0]$10203 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10154 + update \operation$69$next $0\operation$69$next[1:0]$10202 end - connect \$56 $sshl$libresoc.v:171744$9963_Y - connect \$55 $pos$libresoc.v:171745$9965_Y - connect \$59 $not$libresoc.v:171746$9966_Y - connect \$61 $ge$libresoc.v:171747$9967_Y - connect \$63 $and$libresoc.v:171748$9968_Y - connect \$66 $and$libresoc.v:171749$9969_Y + connect \$56 $sshl$libresoc.v:173376$10011_Y + connect \$55 $pos$libresoc.v:173377$10013_Y + connect \$59 $not$libresoc.v:173378$10014_Y + connect \$61 $ge$libresoc.v:173379$10015_Y + connect \$63 $and$libresoc.v:173380$10016_Y + connect \$66 $and$libresoc.v:173381$10017_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -354047,282 +356544,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:172161.1-173706.10" +attribute \src "libresoc.v:173793.1-175338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:173512.3-173524.6" - wire $0\div_by_zero$next[0:0]$10266 - attribute \src "libresoc.v:173298.3-173299.39" + attribute \src "libresoc.v:175144.3-175156.6" + wire $0\div_by_zero$next[0:0]$10314 + attribute \src "libresoc.v:174930.3-174931.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:173486.3-173498.6" - wire $0\dive_abs_ov32$next[0:0]$10260 - attribute \src "libresoc.v:173302.3-173303.43" + attribute \src "libresoc.v:175118.3-175130.6" + wire $0\dive_abs_ov32$next[0:0]$10308 + attribute \src "libresoc.v:174934.3-174935.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:173499.3-173511.6" - wire $0\dive_abs_ov64$next[0:0]$10263 - attribute \src "libresoc.v:173300.3-173301.43" + attribute \src "libresoc.v:175131.3-175143.6" + wire $0\dive_abs_ov64$next[0:0]$10311 + attribute \src "libresoc.v:174932.3-174933.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:173525.3-173537.6" - wire width 128 $0\dividend$next[127:0]$10269 - attribute \src "libresoc.v:173296.3-173297.33" + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $0\dividend$next[127:0]$10317 + attribute \src "libresoc.v:174928.3-174929.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:173473.3-173485.6" - wire $0\dividend_neg$next[0:0]$10257 - attribute \src "libresoc.v:173304.3-173305.41" + attribute \src "libresoc.v:175105.3-175117.6" + wire $0\dividend_neg$next[0:0]$10305 + attribute \src "libresoc.v:174936.3-174937.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:173460.3-173472.6" - wire $0\divisor_neg$next[0:0]$10254 - attribute \src "libresoc.v:173306.3-173307.39" + attribute \src "libresoc.v:175092.3-175104.6" + wire $0\divisor_neg$next[0:0]$10302 + attribute \src "libresoc.v:174938.3-174939.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:173538.3-173550.6" - wire width 64 $0\divisor_radicand$next[63:0]$10272 - attribute \src "libresoc.v:173294.3-173295.49" + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $0\divisor_radicand$next[63:0]$10320 + attribute \src "libresoc.v:174926.3-174927.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:172162.7-172162.20" + attribute \src "libresoc.v:173794.7-173794.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10285 - attribute \src "libresoc.v:173346.3-173347.57" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10333 + attribute \src "libresoc.v:174978.3-174979.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$10286 - attribute \src "libresoc.v:173316.3-173317.55" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 + attribute \src "libresoc.v:174948.3-174949.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10287 - attribute \src "libresoc.v:173318.3-173319.69" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 + attribute \src "libresoc.v:174950.3-174951.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10288 - attribute \src "libresoc.v:173320.3-173321.65" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10336 + attribute \src "libresoc.v:174952.3-174953.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10289 - attribute \src "libresoc.v:173334.3-173335.63" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10337 + attribute \src "libresoc.v:174966.3-174967.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 32 $0\logical_op__insn$next[31:0]$10290 - attribute \src "libresoc.v:173348.3-173349.49" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $0\logical_op__insn$next[31:0]$10338 + attribute \src "libresoc.v:174980.3-174981.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10291 - attribute \src "libresoc.v:173314.3-173315.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10339 + attribute \src "libresoc.v:174946.3-174947.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__invert_in$next[0:0]$10292 - attribute \src "libresoc.v:173330.3-173331.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_in$next[0:0]$10340 + attribute \src "libresoc.v:174962.3-174963.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__invert_out$next[0:0]$10293 - attribute \src "libresoc.v:173336.3-173337.61" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__invert_out$next[0:0]$10341 + attribute \src "libresoc.v:174968.3-174969.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__is_32bit$next[0:0]$10294 - attribute \src "libresoc.v:173342.3-173343.57" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_32bit$next[0:0]$10342 + attribute \src "libresoc.v:174974.3-174975.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__is_signed$next[0:0]$10295 - attribute \src "libresoc.v:173344.3-173345.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__is_signed$next[0:0]$10343 + attribute \src "libresoc.v:174976.3-174977.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__oe__oe$next[0:0]$10296 - attribute \src "libresoc.v:173326.3-173327.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__oe$next[0:0]$10344 + attribute \src "libresoc.v:174958.3-174959.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__oe__ok$next[0:0]$10297 - attribute \src "libresoc.v:173328.3-173329.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__oe__ok$next[0:0]$10345 + attribute \src "libresoc.v:174960.3-174961.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__output_carry$next[0:0]$10298 - attribute \src "libresoc.v:173340.3-173341.65" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__output_carry$next[0:0]$10346 + attribute \src "libresoc.v:174972.3-174973.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__rc__ok$next[0:0]$10299 - attribute \src "libresoc.v:173324.3-173325.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__ok$next[0:0]$10347 + attribute \src "libresoc.v:174956.3-174957.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__rc__rc$next[0:0]$10300 - attribute \src "libresoc.v:173322.3-173323.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__rc__rc$next[0:0]$10348 + attribute \src "libresoc.v:174954.3-174955.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__write_cr0$next[0:0]$10301 - attribute \src "libresoc.v:173338.3-173339.59" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__write_cr0$next[0:0]$10349 + attribute \src "libresoc.v:174970.3-174971.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $0\logical_op__zero_a$next[0:0]$10302 - attribute \src "libresoc.v:173332.3-173333.53" + attribute \src "libresoc.v:175227.3-175268.6" + wire $0\logical_op__zero_a$next[0:0]$10350 + attribute \src "libresoc.v:174964.3-174965.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:173582.3-173594.6" - wire width 2 $0\muxid$next[1:0]$10282 - attribute \src "libresoc.v:173350.3-173351.27" + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $0\muxid$next[1:0]$10330 + attribute \src "libresoc.v:174982.3-174983.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:173551.3-173563.6" - wire width 2 $0\operation$next[1:0]$10275 - attribute \src "libresoc.v:173292.3-173293.35" + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $0\operation$next[1:0]$10323 + attribute \src "libresoc.v:174924.3-174925.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:173564.3-173581.6" - wire $0\r_busy$next[0:0]$10278 - attribute \src "libresoc.v:173352.3-173353.29" + attribute \src "libresoc.v:175196.3-175213.6" + wire $0\r_busy$next[0:0]$10326 + attribute \src "libresoc.v:174984.3-174985.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:173637.3-173649.6" - wire width 64 $0\ra$next[63:0]$10328 - attribute \src "libresoc.v:173312.3-173313.21" + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $0\ra$next[63:0]$10376 + attribute \src "libresoc.v:174944.3-174945.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:173650.3-173662.6" - wire width 64 $0\rb$next[63:0]$10331 - attribute \src "libresoc.v:173310.3-173311.21" + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $0\rb$next[63:0]$10379 + attribute \src "libresoc.v:174942.3-174943.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:173663.3-173675.6" - wire $0\xer_so$next[0:0]$10334 - attribute \src "libresoc.v:173308.3-173309.29" + attribute \src "libresoc.v:175295.3-175307.6" + wire $0\xer_so$next[0:0]$10382 + attribute \src "libresoc.v:174940.3-174941.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:173512.3-173524.6" - wire $1\div_by_zero$next[0:0]$10267 - attribute \src "libresoc.v:172171.7-172171.25" + attribute \src "libresoc.v:175144.3-175156.6" + wire $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:173803.7-173803.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:173486.3-173498.6" - wire $1\dive_abs_ov32$next[0:0]$10261 - attribute \src "libresoc.v:172178.7-172178.27" + attribute \src "libresoc.v:175118.3-175130.6" + wire $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:173810.7-173810.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:173499.3-173511.6" - wire $1\dive_abs_ov64$next[0:0]$10264 - attribute \src "libresoc.v:172185.7-172185.27" + attribute \src "libresoc.v:175131.3-175143.6" + wire $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:173817.7-173817.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:173525.3-173537.6" - wire width 128 $1\dividend$next[127:0]$10270 - attribute \src "libresoc.v:172192.15-172192.63" + attribute \src "libresoc.v:175157.3-175169.6" + wire width 128 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:173824.15-173824.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:173473.3-173485.6" - wire $1\dividend_neg$next[0:0]$10258 - attribute \src "libresoc.v:172199.7-172199.26" + attribute \src "libresoc.v:175105.3-175117.6" + wire $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:173831.7-173831.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:173460.3-173472.6" - wire $1\divisor_neg$next[0:0]$10255 - attribute \src "libresoc.v:172206.7-172206.25" + attribute \src "libresoc.v:175092.3-175104.6" + wire $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:173838.7-173838.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:173538.3-173550.6" - wire width 64 $1\divisor_radicand$next[63:0]$10273 - attribute \src "libresoc.v:172213.14-172213.53" + attribute \src "libresoc.v:175170.3-175182.6" + wire width 64 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:173845.14-173845.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10303 - attribute \src "libresoc.v:172496.13-172496.40" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10351 + attribute \src "libresoc.v:174128.13-174128.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$10304 - attribute \src "libresoc.v:172520.14-172520.44" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 + attribute \src "libresoc.v:174152.14-174152.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10305 - attribute \src "libresoc.v:172559.14-172559.63" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 + attribute \src "libresoc.v:174191.14-174191.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10306 - attribute \src "libresoc.v:172568.7-172568.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10354 + attribute \src "libresoc.v:174200.7-174200.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10307 - attribute \src "libresoc.v:172581.13-172581.43" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10355 + attribute \src "libresoc.v:174213.13-174213.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 32 $1\logical_op__insn$next[31:0]$10308 - attribute \src "libresoc.v:172598.14-172598.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 32 $1\logical_op__insn$next[31:0]$10356 + attribute \src "libresoc.v:174230.14-174230.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10309 - attribute \src "libresoc.v:172682.13-172682.42" + attribute \src "libresoc.v:175227.3-175268.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10357 + attribute \src "libresoc.v:174314.13-174314.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__invert_in$next[0:0]$10310 - attribute \src "libresoc.v:172841.7-172841.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_in$next[0:0]$10358 + attribute \src "libresoc.v:174473.7-174473.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__invert_out$next[0:0]$10311 - attribute \src "libresoc.v:172850.7-172850.36" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__invert_out$next[0:0]$10359 + attribute \src "libresoc.v:174482.7-174482.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__is_32bit$next[0:0]$10312 - attribute \src "libresoc.v:172859.7-172859.34" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_32bit$next[0:0]$10360 + attribute \src "libresoc.v:174491.7-174491.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__is_signed$next[0:0]$10313 - attribute \src "libresoc.v:172868.7-172868.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__is_signed$next[0:0]$10361 + attribute \src "libresoc.v:174500.7-174500.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__oe__oe$next[0:0]$10314 - attribute \src "libresoc.v:172877.7-172877.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__oe$next[0:0]$10362 + attribute \src "libresoc.v:174509.7-174509.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__oe__ok$next[0:0]$10315 - attribute \src "libresoc.v:172886.7-172886.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__oe__ok$next[0:0]$10363 + attribute \src "libresoc.v:174518.7-174518.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__output_carry$next[0:0]$10316 - attribute \src "libresoc.v:172895.7-172895.38" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__output_carry$next[0:0]$10364 + attribute \src "libresoc.v:174527.7-174527.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__rc__ok$next[0:0]$10317 - attribute \src "libresoc.v:172904.7-172904.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__ok$next[0:0]$10365 + attribute \src "libresoc.v:174536.7-174536.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__rc__rc$next[0:0]$10318 - attribute \src "libresoc.v:172913.7-172913.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__rc__rc$next[0:0]$10366 + attribute \src "libresoc.v:174545.7-174545.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__write_cr0$next[0:0]$10319 - attribute \src "libresoc.v:172922.7-172922.35" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__write_cr0$next[0:0]$10367 + attribute \src "libresoc.v:174554.7-174554.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire $1\logical_op__zero_a$next[0:0]$10320 - attribute \src "libresoc.v:172931.7-172931.32" + attribute \src "libresoc.v:175227.3-175268.6" + wire $1\logical_op__zero_a$next[0:0]$10368 + attribute \src "libresoc.v:174563.7-174563.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:173582.3-173594.6" - wire width 2 $1\muxid$next[1:0]$10283 - attribute \src "libresoc.v:172940.13-172940.25" + attribute \src "libresoc.v:175214.3-175226.6" + wire width 2 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:174572.13-174572.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:173551.3-173563.6" - wire width 2 $1\operation$next[1:0]$10276 - attribute \src "libresoc.v:172955.13-172955.29" + attribute \src "libresoc.v:175183.3-175195.6" + wire width 2 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:174587.13-174587.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:173564.3-173581.6" - wire $1\r_busy$next[0:0]$10279 - attribute \src "libresoc.v:172969.7-172969.20" + attribute \src "libresoc.v:175196.3-175213.6" + wire $1\r_busy$next[0:0]$10327 + attribute \src "libresoc.v:174601.7-174601.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:173637.3-173649.6" - wire width 64 $1\ra$next[63:0]$10329 - attribute \src "libresoc.v:172974.14-172974.39" + attribute \src "libresoc.v:175269.3-175281.6" + wire width 64 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:174606.14-174606.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:173650.3-173662.6" - wire width 64 $1\rb$next[63:0]$10332 - attribute \src "libresoc.v:172985.14-172985.39" + attribute \src "libresoc.v:175282.3-175294.6" + wire width 64 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:174617.14-174617.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:173663.3-173675.6" - wire $1\xer_so$next[0:0]$10335 - attribute \src "libresoc.v:173284.7-173284.20" + attribute \src "libresoc.v:175295.3-175307.6" + wire $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:174916.7-174916.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:173595.3-173636.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10321 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10322 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__oe__oe$next[0:0]$10323 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__oe__ok$next[0:0]$10324 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__rc__ok$next[0:0]$10325 - attribute \src "libresoc.v:173595.3-173636.6" - wire $2\logical_op__rc__rc$next[0:0]$10326 - attribute \src "libresoc.v:173564.3-173581.6" - wire $2\r_busy$next[0:0]$10280 - attribute \src "libresoc.v:173291.18-173291.118" - wire $and$libresoc.v:173291$10221_Y + attribute \src "libresoc.v:175227.3-175268.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10370 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__oe$next[0:0]$10371 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__oe__ok$next[0:0]$10372 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__ok$next[0:0]$10373 + attribute \src "libresoc.v:175227.3-175268.6" + wire $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175196.3-175213.6" + wire $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:174923.18-174923.118" + wire $and$libresoc.v:174923$10269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -354366,7 +356863,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:172162.7-172162.15" + attribute \src "libresoc.v:173794.7-173794.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -355419,7 +357916,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:173291$10221 + cell $and $and$libresoc.v:174923$10269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355427,10 +357924,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:173291$10221_Y + connect \Y $and$libresoc.v:174923$10269_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173354.14-173399.4" + attribute \src "libresoc.v:174986.14-175031.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -355478,19 +357975,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:173400.10-173403.4" + attribute \src "libresoc.v:175032.10-175035.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173404.10-173407.4" + attribute \src "libresoc.v:175036.10-175039.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:173408.15-173459.4" + attribute \src "libresoc.v:175040.15-175091.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -355543,487 +358040,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:172162.7-172162.20" - process $proc$libresoc.v:172162$10336 + attribute \src "libresoc.v:173794.7-173794.20" + process $proc$libresoc.v:173794$10384 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172171.7-172171.25" - process $proc$libresoc.v:172171$10337 + attribute \src "libresoc.v:173803.7-173803.25" + process $proc$libresoc.v:173803$10385 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:172178.7-172178.27" - process $proc$libresoc.v:172178$10338 + attribute \src "libresoc.v:173810.7-173810.27" + process $proc$libresoc.v:173810$10386 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:172185.7-172185.27" - process $proc$libresoc.v:172185$10339 + attribute \src "libresoc.v:173817.7-173817.27" + process $proc$libresoc.v:173817$10387 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:172192.15-172192.63" - process $proc$libresoc.v:172192$10340 + attribute \src "libresoc.v:173824.15-173824.63" + process $proc$libresoc.v:173824$10388 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:172199.7-172199.26" - process $proc$libresoc.v:172199$10341 + attribute \src "libresoc.v:173831.7-173831.26" + process $proc$libresoc.v:173831$10389 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:172206.7-172206.25" - process $proc$libresoc.v:172206$10342 + attribute \src "libresoc.v:173838.7-173838.25" + process $proc$libresoc.v:173838$10390 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:172213.14-172213.53" - process $proc$libresoc.v:172213$10343 + attribute \src "libresoc.v:173845.14-173845.53" + process $proc$libresoc.v:173845$10391 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:172496.13-172496.40" - process $proc$libresoc.v:172496$10344 + attribute \src "libresoc.v:174128.13-174128.40" + process $proc$libresoc.v:174128$10392 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:172520.14-172520.44" - process $proc$libresoc.v:172520$10345 + attribute \src "libresoc.v:174152.14-174152.44" + process $proc$libresoc.v:174152$10393 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:172559.14-172559.63" - process $proc$libresoc.v:172559$10346 + attribute \src "libresoc.v:174191.14-174191.63" + process $proc$libresoc.v:174191$10394 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:172568.7-172568.38" - process $proc$libresoc.v:172568$10347 + attribute \src "libresoc.v:174200.7-174200.38" + process $proc$libresoc.v:174200$10395 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:172581.13-172581.43" - process $proc$libresoc.v:172581$10348 + attribute \src "libresoc.v:174213.13-174213.43" + process $proc$libresoc.v:174213$10396 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:172598.14-172598.38" - process $proc$libresoc.v:172598$10349 + attribute \src "libresoc.v:174230.14-174230.38" + process $proc$libresoc.v:174230$10397 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:172682.13-172682.42" - process $proc$libresoc.v:172682$10350 + attribute \src "libresoc.v:174314.13-174314.42" + process $proc$libresoc.v:174314$10398 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:172841.7-172841.35" - process $proc$libresoc.v:172841$10351 + attribute \src "libresoc.v:174473.7-174473.35" + process $proc$libresoc.v:174473$10399 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:172850.7-172850.36" - process $proc$libresoc.v:172850$10352 + attribute \src "libresoc.v:174482.7-174482.36" + process $proc$libresoc.v:174482$10400 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:172859.7-172859.34" - process $proc$libresoc.v:172859$10353 + attribute \src "libresoc.v:174491.7-174491.34" + process $proc$libresoc.v:174491$10401 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:172868.7-172868.35" - process $proc$libresoc.v:172868$10354 + attribute \src "libresoc.v:174500.7-174500.35" + process $proc$libresoc.v:174500$10402 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:172877.7-172877.32" - process $proc$libresoc.v:172877$10355 + attribute \src "libresoc.v:174509.7-174509.32" + process $proc$libresoc.v:174509$10403 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:172886.7-172886.32" - process $proc$libresoc.v:172886$10356 + attribute \src "libresoc.v:174518.7-174518.32" + process $proc$libresoc.v:174518$10404 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:172895.7-172895.38" - process $proc$libresoc.v:172895$10357 + attribute \src "libresoc.v:174527.7-174527.38" + process $proc$libresoc.v:174527$10405 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:172904.7-172904.32" - process $proc$libresoc.v:172904$10358 + attribute \src "libresoc.v:174536.7-174536.32" + process $proc$libresoc.v:174536$10406 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:172913.7-172913.32" - process $proc$libresoc.v:172913$10359 + attribute \src "libresoc.v:174545.7-174545.32" + process $proc$libresoc.v:174545$10407 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:172922.7-172922.35" - process $proc$libresoc.v:172922$10360 + attribute \src "libresoc.v:174554.7-174554.35" + process $proc$libresoc.v:174554$10408 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:172931.7-172931.32" - process $proc$libresoc.v:172931$10361 + attribute \src "libresoc.v:174563.7-174563.32" + process $proc$libresoc.v:174563$10409 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:172940.13-172940.25" - process $proc$libresoc.v:172940$10362 + attribute \src "libresoc.v:174572.13-174572.25" + process $proc$libresoc.v:174572$10410 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:172955.13-172955.29" - process $proc$libresoc.v:172955$10363 + attribute \src "libresoc.v:174587.13-174587.29" + process $proc$libresoc.v:174587$10411 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:172969.7-172969.20" - process $proc$libresoc.v:172969$10364 + attribute \src "libresoc.v:174601.7-174601.20" + process $proc$libresoc.v:174601$10412 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172974.14-172974.39" - process $proc$libresoc.v:172974$10365 + attribute \src "libresoc.v:174606.14-174606.39" + process $proc$libresoc.v:174606$10413 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:172985.14-172985.39" - process $proc$libresoc.v:172985$10366 + attribute \src "libresoc.v:174617.14-174617.39" + process $proc$libresoc.v:174617$10414 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:173284.7-173284.20" - process $proc$libresoc.v:173284$10367 + attribute \src "libresoc.v:174916.7-174916.20" + process $proc$libresoc.v:174916$10415 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:173292.3-173293.35" - process $proc$libresoc.v:173292$10222 + attribute \src "libresoc.v:174924.3-174925.35" + process $proc$libresoc.v:174924$10270 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:173294.3-173295.49" - process $proc$libresoc.v:173294$10223 + attribute \src "libresoc.v:174926.3-174927.49" + process $proc$libresoc.v:174926$10271 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:173296.3-173297.33" - process $proc$libresoc.v:173296$10224 + attribute \src "libresoc.v:174928.3-174929.33" + process $proc$libresoc.v:174928$10272 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:173298.3-173299.39" - process $proc$libresoc.v:173298$10225 + attribute \src "libresoc.v:174930.3-174931.39" + process $proc$libresoc.v:174930$10273 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:173300.3-173301.43" - process $proc$libresoc.v:173300$10226 + attribute \src "libresoc.v:174932.3-174933.43" + process $proc$libresoc.v:174932$10274 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:173302.3-173303.43" - process $proc$libresoc.v:173302$10227 + attribute \src "libresoc.v:174934.3-174935.43" + process $proc$libresoc.v:174934$10275 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:173304.3-173305.41" - process $proc$libresoc.v:173304$10228 + attribute \src "libresoc.v:174936.3-174937.41" + process $proc$libresoc.v:174936$10276 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:173306.3-173307.39" - process $proc$libresoc.v:173306$10229 + attribute \src "libresoc.v:174938.3-174939.39" + process $proc$libresoc.v:174938$10277 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:173308.3-173309.29" - process $proc$libresoc.v:173308$10230 + attribute \src "libresoc.v:174940.3-174941.29" + process $proc$libresoc.v:174940$10278 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:173310.3-173311.21" - process $proc$libresoc.v:173310$10231 + attribute \src "libresoc.v:174942.3-174943.21" + process $proc$libresoc.v:174942$10279 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:173312.3-173313.21" - process $proc$libresoc.v:173312$10232 + attribute \src "libresoc.v:174944.3-174945.21" + process $proc$libresoc.v:174944$10280 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:173314.3-173315.59" - process $proc$libresoc.v:173314$10233 + attribute \src "libresoc.v:174946.3-174947.59" + process $proc$libresoc.v:174946$10281 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:173316.3-173317.55" - process $proc$libresoc.v:173316$10234 + attribute \src "libresoc.v:174948.3-174949.55" + process $proc$libresoc.v:174948$10282 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:173318.3-173319.69" - process $proc$libresoc.v:173318$10235 + attribute \src "libresoc.v:174950.3-174951.69" + process $proc$libresoc.v:174950$10283 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:173320.3-173321.65" - process $proc$libresoc.v:173320$10236 + attribute \src "libresoc.v:174952.3-174953.65" + process $proc$libresoc.v:174952$10284 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:173322.3-173323.53" - process $proc$libresoc.v:173322$10237 + attribute \src "libresoc.v:174954.3-174955.53" + process $proc$libresoc.v:174954$10285 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:173324.3-173325.53" - process $proc$libresoc.v:173324$10238 + attribute \src "libresoc.v:174956.3-174957.53" + process $proc$libresoc.v:174956$10286 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:173326.3-173327.53" - process $proc$libresoc.v:173326$10239 + attribute \src "libresoc.v:174958.3-174959.53" + process $proc$libresoc.v:174958$10287 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:173328.3-173329.53" - process $proc$libresoc.v:173328$10240 + attribute \src "libresoc.v:174960.3-174961.53" + process $proc$libresoc.v:174960$10288 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:173330.3-173331.59" - process $proc$libresoc.v:173330$10241 + attribute \src "libresoc.v:174962.3-174963.59" + process $proc$libresoc.v:174962$10289 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:173332.3-173333.53" - process $proc$libresoc.v:173332$10242 + attribute \src "libresoc.v:174964.3-174965.53" + process $proc$libresoc.v:174964$10290 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:173334.3-173335.63" - process $proc$libresoc.v:173334$10243 + attribute \src "libresoc.v:174966.3-174967.63" + process $proc$libresoc.v:174966$10291 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:173336.3-173337.61" - process $proc$libresoc.v:173336$10244 + attribute \src "libresoc.v:174968.3-174969.61" + process $proc$libresoc.v:174968$10292 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:173338.3-173339.59" - process $proc$libresoc.v:173338$10245 + attribute \src "libresoc.v:174970.3-174971.59" + process $proc$libresoc.v:174970$10293 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:173340.3-173341.65" - process $proc$libresoc.v:173340$10246 + attribute \src "libresoc.v:174972.3-174973.65" + process $proc$libresoc.v:174972$10294 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:173342.3-173343.57" - process $proc$libresoc.v:173342$10247 + attribute \src "libresoc.v:174974.3-174975.57" + process $proc$libresoc.v:174974$10295 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:173344.3-173345.59" - process $proc$libresoc.v:173344$10248 + attribute \src "libresoc.v:174976.3-174977.59" + process $proc$libresoc.v:174976$10296 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:173346.3-173347.57" - process $proc$libresoc.v:173346$10249 + attribute \src "libresoc.v:174978.3-174979.57" + process $proc$libresoc.v:174978$10297 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:173348.3-173349.49" - process $proc$libresoc.v:173348$10250 + attribute \src "libresoc.v:174980.3-174981.49" + process $proc$libresoc.v:174980$10298 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:173350.3-173351.27" - process $proc$libresoc.v:173350$10251 + attribute \src "libresoc.v:174982.3-174983.27" + process $proc$libresoc.v:174982$10299 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:173352.3-173353.29" - process $proc$libresoc.v:173352$10252 + attribute \src "libresoc.v:174984.3-174985.29" + process $proc$libresoc.v:174984$10300 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:173460.3-173472.6" - process $proc$libresoc.v:173460$10253 + attribute \src "libresoc.v:175092.3-175104.6" + process $proc$libresoc.v:175092$10301 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$10254 $1\divisor_neg$next[0:0]$10255 - attribute \src "libresoc.v:173461.5-173461.29" + assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 + attribute \src "libresoc.v:175093.5-175093.29" switch \initial - attribute \src "libresoc.v:173461.9-173461.17" + attribute \src "libresoc.v:175093.9-175093.17" case 1'1 case end @@ -356032,25 +358529,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$10255 \divisor_neg + assign $1\divisor_neg$next[0:0]$10303 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10254 + update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 end - attribute \src "libresoc.v:173473.3-173485.6" - process $proc$libresoc.v:173473$10256 + attribute \src "libresoc.v:175105.3-175117.6" + process $proc$libresoc.v:175105$10304 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$10257 $1\dividend_neg$next[0:0]$10258 - attribute \src "libresoc.v:173474.5-173474.29" + assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 + attribute \src "libresoc.v:175106.5-175106.29" switch \initial - attribute \src "libresoc.v:173474.9-173474.17" + attribute \src "libresoc.v:175106.9-175106.17" case 1'1 case end @@ -356059,25 +358556,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$10258 \dividend_neg + assign $1\dividend_neg$next[0:0]$10306 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10257 + update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 end - attribute \src "libresoc.v:173486.3-173498.6" - process $proc$libresoc.v:173486$10259 + attribute \src "libresoc.v:175118.3-175130.6" + process $proc$libresoc.v:175118$10307 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10260 $1\dive_abs_ov32$next[0:0]$10261 - attribute \src "libresoc.v:173487.5-173487.29" + assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 + attribute \src "libresoc.v:175119.5-175119.29" switch \initial - attribute \src "libresoc.v:173487.9-173487.17" + attribute \src "libresoc.v:175119.9-175119.17" case 1'1 case end @@ -356086,25 +358583,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$10261 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10260 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 end - attribute \src "libresoc.v:173499.3-173511.6" - process $proc$libresoc.v:173499$10262 + attribute \src "libresoc.v:175131.3-175143.6" + process $proc$libresoc.v:175131$10310 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10263 $1\dive_abs_ov64$next[0:0]$10264 - attribute \src "libresoc.v:173500.5-173500.29" + assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 + attribute \src "libresoc.v:175132.5-175132.29" switch \initial - attribute \src "libresoc.v:173500.9-173500.17" + attribute \src "libresoc.v:175132.9-175132.17" case 1'1 case end @@ -356113,25 +358610,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$10264 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10263 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 end - attribute \src "libresoc.v:173512.3-173524.6" - process $proc$libresoc.v:173512$10265 + attribute \src "libresoc.v:175144.3-175156.6" + process $proc$libresoc.v:175144$10313 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$10266 $1\div_by_zero$next[0:0]$10267 - attribute \src "libresoc.v:173513.5-173513.29" + assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 + attribute \src "libresoc.v:175145.5-175145.29" switch \initial - attribute \src "libresoc.v:173513.9-173513.17" + attribute \src "libresoc.v:175145.9-175145.17" case 1'1 case end @@ -356140,25 +358637,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$10267 \div_by_zero + assign $1\div_by_zero$next[0:0]$10315 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10266 + update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 end - attribute \src "libresoc.v:173525.3-173537.6" - process $proc$libresoc.v:173525$10268 + attribute \src "libresoc.v:175157.3-175169.6" + process $proc$libresoc.v:175157$10316 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$10269 $1\dividend$next[127:0]$10270 - attribute \src "libresoc.v:173526.5-173526.29" + assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 + attribute \src "libresoc.v:175158.5-175158.29" switch \initial - attribute \src "libresoc.v:173526.9-173526.17" + attribute \src "libresoc.v:175158.9-175158.17" case 1'1 case end @@ -356167,25 +358664,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$10270 \dividend$97 + assign $1\dividend$next[127:0]$10318 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$10270 \dividend$97 + assign $1\dividend$next[127:0]$10318 \dividend$97 case - assign $1\dividend$next[127:0]$10270 \dividend + assign $1\dividend$next[127:0]$10318 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$10269 + update \dividend$next $0\dividend$next[127:0]$10317 end - attribute \src "libresoc.v:173538.3-173550.6" - process $proc$libresoc.v:173538$10271 + attribute \src "libresoc.v:175170.3-175182.6" + process $proc$libresoc.v:175170$10319 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$10272 $1\divisor_radicand$next[63:0]$10273 - attribute \src "libresoc.v:173539.5-173539.29" + assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 + attribute \src "libresoc.v:175171.5-175171.29" switch \initial - attribute \src "libresoc.v:173539.9-173539.17" + attribute \src "libresoc.v:175171.9-175171.17" case 1'1 case end @@ -356194,25 +358691,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$10273 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10272 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 end - attribute \src "libresoc.v:173551.3-173563.6" - process $proc$libresoc.v:173551$10274 + attribute \src "libresoc.v:175183.3-175195.6" + process $proc$libresoc.v:175183$10322 assign { } { } assign { } { } - assign $0\operation$next[1:0]$10275 $1\operation$next[1:0]$10276 - attribute \src "libresoc.v:173552.5-173552.29" + assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 + attribute \src "libresoc.v:175184.5-175184.29" switch \initial - attribute \src "libresoc.v:173552.9-173552.17" + attribute \src "libresoc.v:175184.9-175184.17" case 1'1 case end @@ -356221,26 +358718,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$10276 \operation$99 + assign $1\operation$next[1:0]$10324 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$10276 \operation$99 + assign $1\operation$next[1:0]$10324 \operation$99 case - assign $1\operation$next[1:0]$10276 \operation + assign $1\operation$next[1:0]$10324 \operation end sync always - update \operation$next $0\operation$next[1:0]$10275 + update \operation$next $0\operation$next[1:0]$10323 end - attribute \src "libresoc.v:173564.3-173581.6" - process $proc$libresoc.v:173564$10277 + attribute \src "libresoc.v:175196.3-175213.6" + process $proc$libresoc.v:175196$10325 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$10278 $2\r_busy$next[0:0]$10280 - attribute \src "libresoc.v:173565.5-173565.29" + assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:175197.5-175197.29" switch \initial - attribute \src "libresoc.v:173565.9-173565.17" + attribute \src "libresoc.v:175197.9-175197.17" case 1'1 case end @@ -356249,34 +358746,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$10279 1'1 + assign $1\r_busy$next[0:0]$10327 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$10279 1'0 + assign $1\r_busy$next[0:0]$10327 1'0 case - assign $1\r_busy$next[0:0]$10279 \r_busy + assign $1\r_busy$next[0:0]$10327 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$10280 1'0 + assign $2\r_busy$next[0:0]$10328 1'0 case - assign $2\r_busy$next[0:0]$10280 $1\r_busy$next[0:0]$10279 + assign $2\r_busy$next[0:0]$10328 $1\r_busy$next[0:0]$10327 end sync always - update \r_busy$next $0\r_busy$next[0:0]$10278 + update \r_busy$next $0\r_busy$next[0:0]$10326 end - attribute \src "libresoc.v:173582.3-173594.6" - process $proc$libresoc.v:173582$10281 + attribute \src "libresoc.v:175214.3-175226.6" + process $proc$libresoc.v:175214$10329 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10282 $1\muxid$next[1:0]$10283 - attribute \src "libresoc.v:173583.5-173583.29" + assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 + attribute \src "libresoc.v:175215.5-175215.29" switch \initial - attribute \src "libresoc.v:173583.9-173583.17" + attribute \src "libresoc.v:175215.9-175215.17" case 1'1 case end @@ -356285,19 +358782,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$10283 \muxid$68 + assign $1\muxid$next[1:0]$10331 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$10283 \muxid$68 + assign $1\muxid$next[1:0]$10331 \muxid$68 case - assign $1\muxid$next[1:0]$10283 \muxid + assign $1\muxid$next[1:0]$10331 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$10282 + update \muxid$next $0\muxid$next[1:0]$10330 end - attribute \src "libresoc.v:173595.3-173636.6" - process $proc$libresoc.v:173595$10284 + attribute \src "libresoc.v:175227.3-175268.6" + process $proc$libresoc.v:175227$10332 assign { } { } assign { } { } assign { } { } @@ -356334,33 +358831,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$10285 $1\logical_op__data_len$next[3:0]$10303 - assign $0\logical_op__fn_unit$next[13:0]$10286 $1\logical_op__fn_unit$next[13:0]$10304 + assign $0\logical_op__data_len$next[3:0]$10333 $1\logical_op__data_len$next[3:0]$10351 + assign $0\logical_op__fn_unit$next[13:0]$10334 $1\logical_op__fn_unit$next[13:0]$10352 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10289 $1\logical_op__input_carry$next[1:0]$10307 - assign $0\logical_op__insn$next[31:0]$10290 $1\logical_op__insn$next[31:0]$10308 - assign $0\logical_op__insn_type$next[6:0]$10291 $1\logical_op__insn_type$next[6:0]$10309 - assign $0\logical_op__invert_in$next[0:0]$10292 $1\logical_op__invert_in$next[0:0]$10310 - assign $0\logical_op__invert_out$next[0:0]$10293 $1\logical_op__invert_out$next[0:0]$10311 - assign $0\logical_op__is_32bit$next[0:0]$10294 $1\logical_op__is_32bit$next[0:0]$10312 - assign $0\logical_op__is_signed$next[0:0]$10295 $1\logical_op__is_signed$next[0:0]$10313 + assign $0\logical_op__input_carry$next[1:0]$10337 $1\logical_op__input_carry$next[1:0]$10355 + assign $0\logical_op__insn$next[31:0]$10338 $1\logical_op__insn$next[31:0]$10356 + assign $0\logical_op__insn_type$next[6:0]$10339 $1\logical_op__insn_type$next[6:0]$10357 + assign $0\logical_op__invert_in$next[0:0]$10340 $1\logical_op__invert_in$next[0:0]$10358 + assign $0\logical_op__invert_out$next[0:0]$10341 $1\logical_op__invert_out$next[0:0]$10359 + assign $0\logical_op__is_32bit$next[0:0]$10342 $1\logical_op__is_32bit$next[0:0]$10360 + assign $0\logical_op__is_signed$next[0:0]$10343 $1\logical_op__is_signed$next[0:0]$10361 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10298 $1\logical_op__output_carry$next[0:0]$10316 + assign $0\logical_op__output_carry$next[0:0]$10346 $1\logical_op__output_carry$next[0:0]$10364 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10301 $1\logical_op__write_cr0$next[0:0]$10319 - assign $0\logical_op__zero_a$next[0:0]$10302 $1\logical_op__zero_a$next[0:0]$10320 - assign $0\logical_op__imm_data__data$next[63:0]$10287 $2\logical_op__imm_data__data$next[63:0]$10321 - assign $0\logical_op__imm_data__ok$next[0:0]$10288 $2\logical_op__imm_data__ok$next[0:0]$10322 - assign $0\logical_op__oe__oe$next[0:0]$10296 $2\logical_op__oe__oe$next[0:0]$10323 - assign $0\logical_op__oe__ok$next[0:0]$10297 $2\logical_op__oe__ok$next[0:0]$10324 - assign $0\logical_op__rc__ok$next[0:0]$10299 $2\logical_op__rc__ok$next[0:0]$10325 - assign $0\logical_op__rc__rc$next[0:0]$10300 $2\logical_op__rc__rc$next[0:0]$10326 - attribute \src "libresoc.v:173596.5-173596.29" + assign $0\logical_op__write_cr0$next[0:0]$10349 $1\logical_op__write_cr0$next[0:0]$10367 + assign $0\logical_op__zero_a$next[0:0]$10350 $1\logical_op__zero_a$next[0:0]$10368 + assign $0\logical_op__imm_data__data$next[63:0]$10335 $2\logical_op__imm_data__data$next[63:0]$10369 + assign $0\logical_op__imm_data__ok$next[0:0]$10336 $2\logical_op__imm_data__ok$next[0:0]$10370 + assign $0\logical_op__oe__oe$next[0:0]$10344 $2\logical_op__oe__oe$next[0:0]$10371 + assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 + assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 + assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 + attribute \src "libresoc.v:175228.5-175228.29" switch \initial - attribute \src "libresoc.v:173596.9-173596.17" + attribute \src "libresoc.v:175228.9-175228.17" case 1'1 case end @@ -356386,7 +358883,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -356407,26 +358904,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10308 $1\logical_op__data_len$next[3:0]$10303 $1\logical_op__is_signed$next[0:0]$10313 $1\logical_op__is_32bit$next[0:0]$10312 $1\logical_op__output_carry$next[0:0]$10316 $1\logical_op__write_cr0$next[0:0]$10319 $1\logical_op__invert_out$next[0:0]$10311 $1\logical_op__input_carry$next[1:0]$10307 $1\logical_op__zero_a$next[0:0]$10320 $1\logical_op__invert_in$next[0:0]$10310 $1\logical_op__oe__ok$next[0:0]$10315 $1\logical_op__oe__oe$next[0:0]$10314 $1\logical_op__rc__ok$next[0:0]$10317 $1\logical_op__rc__rc$next[0:0]$10318 $1\logical_op__imm_data__ok$next[0:0]$10306 $1\logical_op__imm_data__data$next[63:0]$10305 $1\logical_op__fn_unit$next[13:0]$10304 $1\logical_op__insn_type$next[6:0]$10309 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$10303 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$10304 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10305 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10306 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10307 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10308 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10309 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10310 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10311 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10312 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10313 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10314 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10315 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10316 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10317 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10318 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10319 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10320 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10351 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10352 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10353 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10354 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10355 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10356 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10357 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10358 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10359 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10360 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10361 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10362 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10363 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10364 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10365 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10366 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10367 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10368 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -356438,48 +358935,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10321 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10322 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10326 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10325 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10323 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10324 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10369 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10374 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10373 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10371 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10372 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10321 $1\logical_op__imm_data__data$next[63:0]$10305 - assign $2\logical_op__imm_data__ok$next[0:0]$10322 $1\logical_op__imm_data__ok$next[0:0]$10306 - assign $2\logical_op__oe__oe$next[0:0]$10323 $1\logical_op__oe__oe$next[0:0]$10314 - assign $2\logical_op__oe__ok$next[0:0]$10324 $1\logical_op__oe__ok$next[0:0]$10315 - assign $2\logical_op__rc__ok$next[0:0]$10325 $1\logical_op__rc__ok$next[0:0]$10317 - assign $2\logical_op__rc__rc$next[0:0]$10326 $1\logical_op__rc__rc$next[0:0]$10318 + assign $2\logical_op__imm_data__data$next[63:0]$10369 $1\logical_op__imm_data__data$next[63:0]$10353 + assign $2\logical_op__imm_data__ok$next[0:0]$10370 $1\logical_op__imm_data__ok$next[0:0]$10354 + assign $2\logical_op__oe__oe$next[0:0]$10371 $1\logical_op__oe__oe$next[0:0]$10362 + assign $2\logical_op__oe__ok$next[0:0]$10372 $1\logical_op__oe__ok$next[0:0]$10363 + assign $2\logical_op__rc__ok$next[0:0]$10373 $1\logical_op__rc__ok$next[0:0]$10365 + assign $2\logical_op__rc__rc$next[0:0]$10374 $1\logical_op__rc__rc$next[0:0]$10366 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10285 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10286 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10287 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10288 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10289 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10290 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10291 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10292 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10293 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10294 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10295 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10296 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10297 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10298 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10299 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10300 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10301 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10302 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10333 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10334 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10335 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10336 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10337 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10338 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10339 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10340 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10341 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10342 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10343 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10344 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10345 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10346 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10347 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10348 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 end - attribute \src "libresoc.v:173637.3-173649.6" - process $proc$libresoc.v:173637$10327 + attribute \src "libresoc.v:175269.3-175281.6" + process $proc$libresoc.v:175269$10375 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10328 $1\ra$next[63:0]$10329 - attribute \src "libresoc.v:173638.5-173638.29" + assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 + attribute \src "libresoc.v:175270.5-175270.29" switch \initial - attribute \src "libresoc.v:173638.9-173638.17" + attribute \src "libresoc.v:175270.9-175270.17" case 1'1 case end @@ -356488,25 +358985,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$10329 \ra$87 + assign $1\ra$next[63:0]$10377 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$10329 \ra$87 + assign $1\ra$next[63:0]$10377 \ra$87 case - assign $1\ra$next[63:0]$10329 \ra + assign $1\ra$next[63:0]$10377 \ra end sync always - update \ra$next $0\ra$next[63:0]$10328 + update \ra$next $0\ra$next[63:0]$10376 end - attribute \src "libresoc.v:173650.3-173662.6" - process $proc$libresoc.v:173650$10330 + attribute \src "libresoc.v:175282.3-175294.6" + process $proc$libresoc.v:175282$10378 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10331 $1\rb$next[63:0]$10332 - attribute \src "libresoc.v:173651.5-173651.29" + assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 + attribute \src "libresoc.v:175283.5-175283.29" switch \initial - attribute \src "libresoc.v:173651.9-173651.17" + attribute \src "libresoc.v:175283.9-175283.17" case 1'1 case end @@ -356515,25 +359012,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$10332 \rb$89 + assign $1\rb$next[63:0]$10380 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$10332 \rb$89 + assign $1\rb$next[63:0]$10380 \rb$89 case - assign $1\rb$next[63:0]$10332 \rb + assign $1\rb$next[63:0]$10380 \rb end sync always - update \rb$next $0\rb$next[63:0]$10331 + update \rb$next $0\rb$next[63:0]$10379 end - attribute \src "libresoc.v:173663.3-173675.6" - process $proc$libresoc.v:173663$10333 + attribute \src "libresoc.v:175295.3-175307.6" + process $proc$libresoc.v:175295$10381 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10334 $1\xer_so$next[0:0]$10335 - attribute \src "libresoc.v:173664.5-173664.29" + assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 + attribute \src "libresoc.v:175296.5-175296.29" switch \initial - attribute \src "libresoc.v:173664.9-173664.17" + attribute \src "libresoc.v:175296.9-175296.17" case 1'1 case end @@ -356542,18 +359039,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$10335 \xer_so$91 + assign $1\xer_so$next[0:0]$10383 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$10335 \xer_so$91 + assign $1\xer_so$next[0:0]$10383 \xer_so$91 case - assign $1\xer_so$next[0:0]$10335 \xer_so + assign $1\xer_so$next[0:0]$10383 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$10334 + update \xer_so$next $0\xer_so$next[0:0]$10382 end - connect \$66 $and$libresoc.v:173291$10221_Y + connect \$66 $and$libresoc.v:174923$10269_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -356585,27 +359082,27 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:173710.1-173754.10" +attribute \src "libresoc.v:175342.1-175386.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" module \pll - attribute \src "libresoc.v:173711.7-173711.20" + attribute \src "libresoc.v:175343.7-175343.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173743.3-173752.6" + attribute \src "libresoc.v:175375.3-175384.6" wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:173733.3-173742.6" + attribute \src "libresoc.v:175365.3-175374.6" wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:173743.3-173752.6" + attribute \src "libresoc.v:175375.3-175384.6" wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:173733.3-173742.6" + attribute \src "libresoc.v:175365.3-175374.6" wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:173730.17-173730.105" - wire $eq$libresoc.v:173730$10368_Y - attribute \src "libresoc.v:173731.17-173731.105" - wire $eq$libresoc.v:173731$10369_Y - attribute \src "libresoc.v:173732.17-173732.98" - wire $not$libresoc.v:173732$10370_Y + attribute \src "libresoc.v:175362.17-175362.105" + wire $eq$libresoc.v:175362$10416_Y + attribute \src "libresoc.v:175363.17-175363.105" + wire $eq$libresoc.v:175363$10417_Y + attribute \src "libresoc.v:175364.17-175364.98" + wire $not$libresoc.v:175364$10418_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" @@ -356618,14 +359115,14 @@ module \pll wire output 5 \clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:173711.7-173711.15" + attribute \src "libresoc.v:175343.7-175343.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire output 2 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" wire output 4 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:173730$10368 + cell $eq $eq$libresoc.v:175362$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -356633,10 +359130,10 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:173730$10368_Y + connect \Y $eq$libresoc.v:175362$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:173731$10369 + cell $eq $eq$libresoc.v:175363$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -356644,32 +359141,32 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:173731$10369_Y + connect \Y $eq$libresoc.v:175363$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:173732$10370 + cell $not $not$libresoc.v:175364$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clk_24_i - connect \Y $not$libresoc.v:173732$10370_Y + connect \Y $not$libresoc.v:175364$10418_Y end - attribute \src "libresoc.v:173711.7-173711.20" - process $proc$libresoc.v:173711$10373 + attribute \src "libresoc.v:175343.7-175343.20" + process $proc$libresoc.v:175343$10421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173733.3-173742.6" - process $proc$libresoc.v:173733$10371 + attribute \src "libresoc.v:175365.3-175374.6" + process $proc$libresoc.v:175365$10419 assign { } { } assign { } { } assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:173734.5-173734.29" + attribute \src "libresoc.v:175366.5-175366.29" switch \initial - attribute \src "libresoc.v:173734.9-173734.17" + attribute \src "libresoc.v:175366.9-175366.17" case 1'1 case end @@ -356685,14 +359182,14 @@ module \pll sync always update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:173743.3-173752.6" - process $proc$libresoc.v:173743$10372 + attribute \src "libresoc.v:175375.3-175384.6" + process $proc$libresoc.v:175375$10420 assign { } { } assign { } { } assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:173744.5-173744.29" + attribute \src "libresoc.v:175376.5-175376.29" switch \initial - attribute \src "libresoc.v:173744.9-173744.17" + attribute \src "libresoc.v:175376.9-175376.17" case 1'1 case end @@ -356708,196 +359205,196 @@ module \pll sync always update \pll_18_o $0\pll_18_o[0:0] end - connect \$1 $eq$libresoc.v:173730$10368_Y - connect \$3 $eq$libresoc.v:173731$10369_Y - connect \$5 $not$libresoc.v:173732$10370_Y + connect \$1 $eq$libresoc.v:175362$10416_Y + connect \$3 $eq$libresoc.v:175363$10417_Y + connect \$5 $not$libresoc.v:175364$10418_Y connect \clk_pll_o \clk_24_i end -attribute \src "libresoc.v:173758.1-174400.10" +attribute \src "libresoc.v:175390.1-176032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:173759.7-173759.20" + attribute \src "libresoc.v:175391.7-175391.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174247.3-174273.6" + attribute \src "libresoc.v:175879.3-175905.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:174247.3-174273.6" + attribute \src "libresoc.v:175879.3-175905.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:174171.19-174171.132" - wire width 4 $add$libresoc.v:174171$10374_Y - attribute \src "libresoc.v:174172.19-174172.132" - wire width 4 $add$libresoc.v:174172$10375_Y - attribute \src "libresoc.v:174173.19-174173.132" - wire width 4 $add$libresoc.v:174173$10376_Y - attribute \src "libresoc.v:174174.19-174174.132" - wire width 4 $add$libresoc.v:174174$10377_Y - attribute \src "libresoc.v:174175.19-174175.134" - wire width 4 $add$libresoc.v:174175$10378_Y - attribute \src "libresoc.v:174176.19-174176.134" - wire width 4 $add$libresoc.v:174176$10379_Y - attribute \src "libresoc.v:174177.18-174177.125" - wire width 3 $add$libresoc.v:174177$10380_Y - attribute \src "libresoc.v:174178.19-174178.134" - wire width 4 $add$libresoc.v:174178$10381_Y - attribute \src "libresoc.v:174179.19-174179.134" - wire width 4 $add$libresoc.v:174179$10382_Y - attribute \src "libresoc.v:174180.19-174180.134" - wire width 4 $add$libresoc.v:174180$10383_Y - attribute \src "libresoc.v:174181.19-174181.134" - wire width 4 $add$libresoc.v:174181$10384_Y - attribute \src "libresoc.v:174182.19-174182.134" - wire width 4 $add$libresoc.v:174182$10385_Y - attribute \src "libresoc.v:174183.19-174183.134" - wire width 4 $add$libresoc.v:174183$10386_Y - attribute \src "libresoc.v:174184.19-174184.134" - wire width 4 $add$libresoc.v:174184$10387_Y - attribute \src "libresoc.v:174185.19-174185.134" - wire width 4 $add$libresoc.v:174185$10388_Y - attribute \src "libresoc.v:174186.19-174186.134" - wire width 4 $add$libresoc.v:174186$10389_Y - attribute \src "libresoc.v:174187.19-174187.132" - wire width 5 $add$libresoc.v:174187$10390_Y - attribute \src "libresoc.v:174188.18-174188.125" - wire width 3 $add$libresoc.v:174188$10391_Y - attribute \src "libresoc.v:174189.19-174189.132" - wire width 5 $add$libresoc.v:174189$10392_Y - attribute \src "libresoc.v:174190.19-174190.132" - wire width 5 $add$libresoc.v:174190$10393_Y - attribute \src "libresoc.v:174191.19-174191.132" - wire width 5 $add$libresoc.v:174191$10394_Y - attribute \src "libresoc.v:174192.19-174192.132" - wire width 5 $add$libresoc.v:174192$10395_Y - attribute \src "libresoc.v:174193.19-174193.134" - wire width 5 $add$libresoc.v:174193$10396_Y - attribute \src "libresoc.v:174194.19-174194.134" - wire width 5 $add$libresoc.v:174194$10397_Y - attribute \src "libresoc.v:174195.19-174195.134" - wire width 5 $add$libresoc.v:174195$10398_Y - attribute \src "libresoc.v:174196.19-174196.132" - wire width 6 $add$libresoc.v:174196$10399_Y - attribute \src "libresoc.v:174197.19-174197.132" - wire width 6 $add$libresoc.v:174197$10400_Y - attribute \src "libresoc.v:174198.19-174198.132" - wire width 6 $add$libresoc.v:174198$10401_Y - attribute \src "libresoc.v:174199.18-174199.127" - wire width 3 $add$libresoc.v:174199$10402_Y - attribute \src "libresoc.v:174200.19-174200.132" - wire width 6 $add$libresoc.v:174200$10403_Y - attribute \src "libresoc.v:174201.19-174201.132" - wire width 7 $add$libresoc.v:174201$10404_Y - attribute \src "libresoc.v:174202.19-174202.132" - wire width 7 $add$libresoc.v:174202$10405_Y - attribute \src "libresoc.v:174203.19-174203.132" - wire width 8 $add$libresoc.v:174203$10406_Y - attribute \src "libresoc.v:174214.18-174214.127" - wire width 3 $add$libresoc.v:174214$10425_Y - attribute \src "libresoc.v:174218.18-174218.127" - wire width 3 $add$libresoc.v:174218$10432_Y - attribute \src "libresoc.v:174219.18-174219.127" - wire width 3 $add$libresoc.v:174219$10433_Y - attribute \src "libresoc.v:174220.17-174220.124" - wire width 3 $add$libresoc.v:174220$10434_Y - attribute \src "libresoc.v:174221.18-174221.127" - wire width 3 $add$libresoc.v:174221$10435_Y - attribute \src "libresoc.v:174222.18-174222.127" - wire width 3 $add$libresoc.v:174222$10436_Y - attribute \src "libresoc.v:174223.18-174223.127" - wire width 3 $add$libresoc.v:174223$10437_Y - attribute \src "libresoc.v:174224.18-174224.127" - wire width 3 $add$libresoc.v:174224$10438_Y - attribute \src "libresoc.v:174225.18-174225.127" - wire width 3 $add$libresoc.v:174225$10439_Y - attribute \src "libresoc.v:174226.18-174226.127" - wire width 3 $add$libresoc.v:174226$10440_Y - attribute \src "libresoc.v:174227.18-174227.127" - wire width 3 $add$libresoc.v:174227$10441_Y - attribute \src "libresoc.v:174228.18-174228.127" - wire width 3 $add$libresoc.v:174228$10442_Y - attribute \src "libresoc.v:174229.18-174229.127" - wire width 3 $add$libresoc.v:174229$10443_Y - attribute \src "libresoc.v:174230.18-174230.127" - wire width 3 $add$libresoc.v:174230$10444_Y - attribute \src "libresoc.v:174231.17-174231.124" - wire width 3 $add$libresoc.v:174231$10445_Y - attribute \src "libresoc.v:174232.18-174232.127" - wire width 3 $add$libresoc.v:174232$10446_Y - attribute \src "libresoc.v:174233.18-174233.127" - wire width 3 $add$libresoc.v:174233$10447_Y - attribute \src "libresoc.v:174234.18-174234.127" - wire width 3 $add$libresoc.v:174234$10448_Y - attribute \src "libresoc.v:174235.18-174235.127" - wire width 3 $add$libresoc.v:174235$10449_Y - attribute \src "libresoc.v:174236.18-174236.127" - wire width 3 $add$libresoc.v:174236$10450_Y - attribute \src "libresoc.v:174237.18-174237.127" - wire width 3 $add$libresoc.v:174237$10451_Y - attribute \src "libresoc.v:174238.18-174238.127" - wire width 3 $add$libresoc.v:174238$10452_Y - attribute \src "libresoc.v:174239.18-174239.127" - wire width 3 $add$libresoc.v:174239$10453_Y - attribute \src "libresoc.v:174240.18-174240.127" - wire width 3 $add$libresoc.v:174240$10454_Y - attribute \src "libresoc.v:174241.18-174241.127" - wire width 3 $add$libresoc.v:174241$10455_Y - attribute \src "libresoc.v:174242.17-174242.124" - wire width 3 $add$libresoc.v:174242$10456_Y - attribute \src "libresoc.v:174243.18-174243.127" - wire width 3 $add$libresoc.v:174243$10457_Y - attribute \src "libresoc.v:174244.18-174244.127" - wire width 3 $add$libresoc.v:174244$10458_Y - attribute \src "libresoc.v:174245.18-174245.127" - wire width 3 $add$libresoc.v:174245$10459_Y - attribute \src "libresoc.v:174246.18-174246.131" - wire width 4 $add$libresoc.v:174246$10460_Y - attribute \src "libresoc.v:174204.19-174204.111" - wire $eq$libresoc.v:174204$10407_Y - attribute \src "libresoc.v:174205.19-174205.111" - wire $eq$libresoc.v:174205$10408_Y - attribute \src "libresoc.v:174206.19-174206.104" - wire width 8 $extend$libresoc.v:174206$10409_Y - attribute \src "libresoc.v:174207.19-174207.104" - wire width 8 $extend$libresoc.v:174207$10411_Y - attribute \src "libresoc.v:174208.19-174208.104" - wire width 8 $extend$libresoc.v:174208$10413_Y - attribute \src "libresoc.v:174209.19-174209.104" - wire width 8 $extend$libresoc.v:174209$10415_Y - attribute \src "libresoc.v:174210.19-174210.104" - wire width 8 $extend$libresoc.v:174210$10417_Y - attribute \src "libresoc.v:174211.19-174211.104" - wire width 8 $extend$libresoc.v:174211$10419_Y - attribute \src "libresoc.v:174212.19-174212.104" - wire width 8 $extend$libresoc.v:174212$10421_Y - attribute \src "libresoc.v:174213.19-174213.104" - wire width 8 $extend$libresoc.v:174213$10423_Y - attribute \src "libresoc.v:174215.19-174215.104" - wire width 32 $extend$libresoc.v:174215$10426_Y - attribute \src "libresoc.v:174216.19-174216.104" - wire width 32 $extend$libresoc.v:174216$10428_Y - attribute \src "libresoc.v:174217.19-174217.104" - wire width 64 $extend$libresoc.v:174217$10430_Y - attribute \src "libresoc.v:174206.19-174206.104" - wire width 8 $pos$libresoc.v:174206$10410_Y - attribute \src "libresoc.v:174207.19-174207.104" - wire width 8 $pos$libresoc.v:174207$10412_Y - attribute \src "libresoc.v:174208.19-174208.104" - wire width 8 $pos$libresoc.v:174208$10414_Y - attribute \src "libresoc.v:174209.19-174209.104" - wire width 8 $pos$libresoc.v:174209$10416_Y - attribute \src "libresoc.v:174210.19-174210.104" - wire width 8 $pos$libresoc.v:174210$10418_Y - attribute \src "libresoc.v:174211.19-174211.104" - wire width 8 $pos$libresoc.v:174211$10420_Y - attribute \src "libresoc.v:174212.19-174212.104" - wire width 8 $pos$libresoc.v:174212$10422_Y - attribute \src "libresoc.v:174213.19-174213.104" - wire width 8 $pos$libresoc.v:174213$10424_Y - attribute \src "libresoc.v:174215.19-174215.104" - wire width 32 $pos$libresoc.v:174215$10427_Y - attribute \src "libresoc.v:174216.19-174216.104" - wire width 32 $pos$libresoc.v:174216$10429_Y - attribute \src "libresoc.v:174217.19-174217.104" - wire width 64 $pos$libresoc.v:174217$10431_Y + attribute \src "libresoc.v:175803.19-175803.132" + wire width 4 $add$libresoc.v:175803$10422_Y + attribute \src "libresoc.v:175804.19-175804.132" + wire width 4 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"libresoc.v:175825.19-175825.134" + wire width 5 $add$libresoc.v:175825$10444_Y + attribute \src "libresoc.v:175826.19-175826.134" + wire width 5 $add$libresoc.v:175826$10445_Y + attribute \src "libresoc.v:175827.19-175827.134" + wire width 5 $add$libresoc.v:175827$10446_Y + attribute \src "libresoc.v:175828.19-175828.132" + wire width 6 $add$libresoc.v:175828$10447_Y + attribute \src "libresoc.v:175829.19-175829.132" + wire width 6 $add$libresoc.v:175829$10448_Y + attribute \src "libresoc.v:175830.19-175830.132" + wire width 6 $add$libresoc.v:175830$10449_Y + attribute \src "libresoc.v:175831.18-175831.127" + wire width 3 $add$libresoc.v:175831$10450_Y + attribute \src "libresoc.v:175832.19-175832.132" + wire width 6 $add$libresoc.v:175832$10451_Y + attribute \src "libresoc.v:175833.19-175833.132" + wire width 7 $add$libresoc.v:175833$10452_Y + attribute \src "libresoc.v:175834.19-175834.132" + wire width 7 $add$libresoc.v:175834$10453_Y + attribute \src "libresoc.v:175835.19-175835.132" + wire width 8 $add$libresoc.v:175835$10454_Y + attribute \src "libresoc.v:175846.18-175846.127" + wire width 3 $add$libresoc.v:175846$10473_Y + attribute \src "libresoc.v:175850.18-175850.127" + wire width 3 $add$libresoc.v:175850$10480_Y + attribute \src "libresoc.v:175851.18-175851.127" + wire width 3 $add$libresoc.v:175851$10481_Y + attribute \src "libresoc.v:175852.17-175852.124" + wire width 3 $add$libresoc.v:175852$10482_Y + attribute \src "libresoc.v:175853.18-175853.127" + wire width 3 $add$libresoc.v:175853$10483_Y + attribute \src "libresoc.v:175854.18-175854.127" + wire width 3 $add$libresoc.v:175854$10484_Y + attribute \src "libresoc.v:175855.18-175855.127" + wire width 3 $add$libresoc.v:175855$10485_Y + attribute \src "libresoc.v:175856.18-175856.127" + wire width 3 $add$libresoc.v:175856$10486_Y + attribute \src "libresoc.v:175857.18-175857.127" + wire width 3 $add$libresoc.v:175857$10487_Y + attribute \src "libresoc.v:175858.18-175858.127" + wire width 3 $add$libresoc.v:175858$10488_Y + attribute \src "libresoc.v:175859.18-175859.127" + wire width 3 $add$libresoc.v:175859$10489_Y + attribute \src "libresoc.v:175860.18-175860.127" + wire width 3 $add$libresoc.v:175860$10490_Y + attribute \src "libresoc.v:175861.18-175861.127" + wire width 3 $add$libresoc.v:175861$10491_Y + attribute \src "libresoc.v:175862.18-175862.127" + wire width 3 $add$libresoc.v:175862$10492_Y + attribute \src "libresoc.v:175863.17-175863.124" + wire width 3 $add$libresoc.v:175863$10493_Y + attribute \src "libresoc.v:175864.18-175864.127" + wire width 3 $add$libresoc.v:175864$10494_Y + attribute \src "libresoc.v:175865.18-175865.127" + wire width 3 $add$libresoc.v:175865$10495_Y + attribute \src "libresoc.v:175866.18-175866.127" + wire width 3 $add$libresoc.v:175866$10496_Y + attribute \src "libresoc.v:175867.18-175867.127" + wire width 3 $add$libresoc.v:175867$10497_Y + attribute \src "libresoc.v:175868.18-175868.127" + wire width 3 $add$libresoc.v:175868$10498_Y + attribute \src "libresoc.v:175869.18-175869.127" + wire width 3 $add$libresoc.v:175869$10499_Y + attribute \src "libresoc.v:175870.18-175870.127" + wire width 3 $add$libresoc.v:175870$10500_Y + attribute \src "libresoc.v:175871.18-175871.127" + wire width 3 $add$libresoc.v:175871$10501_Y + attribute \src "libresoc.v:175872.18-175872.127" + wire width 3 $add$libresoc.v:175872$10502_Y + attribute \src "libresoc.v:175873.18-175873.127" + wire width 3 $add$libresoc.v:175873$10503_Y + attribute \src "libresoc.v:175874.17-175874.124" + wire width 3 $add$libresoc.v:175874$10504_Y + attribute \src "libresoc.v:175875.18-175875.127" + wire width 3 $add$libresoc.v:175875$10505_Y + attribute \src "libresoc.v:175876.18-175876.127" + wire width 3 $add$libresoc.v:175876$10506_Y + attribute \src "libresoc.v:175877.18-175877.127" + wire width 3 $add$libresoc.v:175877$10507_Y + attribute \src "libresoc.v:175878.18-175878.131" + wire width 4 $add$libresoc.v:175878$10508_Y + attribute \src "libresoc.v:175836.19-175836.111" + wire $eq$libresoc.v:175836$10455_Y + attribute \src "libresoc.v:175837.19-175837.111" + wire $eq$libresoc.v:175837$10456_Y + attribute \src "libresoc.v:175838.19-175838.104" + wire width 8 $extend$libresoc.v:175838$10457_Y + attribute \src "libresoc.v:175839.19-175839.104" + wire width 8 $extend$libresoc.v:175839$10459_Y + attribute \src "libresoc.v:175840.19-175840.104" + wire width 8 $extend$libresoc.v:175840$10461_Y + attribute \src "libresoc.v:175841.19-175841.104" + wire width 8 $extend$libresoc.v:175841$10463_Y + attribute \src "libresoc.v:175842.19-175842.104" + wire width 8 $extend$libresoc.v:175842$10465_Y + attribute \src "libresoc.v:175843.19-175843.104" + wire width 8 $extend$libresoc.v:175843$10467_Y + attribute \src "libresoc.v:175844.19-175844.104" + wire width 8 $extend$libresoc.v:175844$10469_Y + attribute \src "libresoc.v:175845.19-175845.104" + wire width 8 $extend$libresoc.v:175845$10471_Y + attribute \src "libresoc.v:175847.19-175847.104" + wire width 32 $extend$libresoc.v:175847$10474_Y + attribute \src "libresoc.v:175848.19-175848.104" + wire width 32 $extend$libresoc.v:175848$10476_Y + attribute \src "libresoc.v:175849.19-175849.104" + wire width 64 $extend$libresoc.v:175849$10478_Y + attribute \src "libresoc.v:175838.19-175838.104" + wire width 8 $pos$libresoc.v:175838$10458_Y + attribute \src "libresoc.v:175839.19-175839.104" + wire width 8 $pos$libresoc.v:175839$10460_Y + attribute \src "libresoc.v:175840.19-175840.104" + wire width 8 $pos$libresoc.v:175840$10462_Y + attribute \src "libresoc.v:175841.19-175841.104" + wire width 8 $pos$libresoc.v:175841$10464_Y + attribute \src "libresoc.v:175842.19-175842.104" + wire width 8 $pos$libresoc.v:175842$10466_Y + attribute \src "libresoc.v:175843.19-175843.104" + wire width 8 $pos$libresoc.v:175843$10468_Y + attribute \src "libresoc.v:175844.19-175844.104" + wire width 8 $pos$libresoc.v:175844$10470_Y + attribute \src "libresoc.v:175845.19-175845.104" + wire width 8 $pos$libresoc.v:175845$10472_Y + attribute \src "libresoc.v:175847.19-175847.104" + wire width 32 $pos$libresoc.v:175847$10475_Y + attribute \src "libresoc.v:175848.19-175848.104" + wire width 32 $pos$libresoc.v:175848$10477_Y + attribute \src "libresoc.v:175849.19-175849.104" + wire width 64 $pos$libresoc.v:175849$10479_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -357180,7 +359677,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:173759.7-173759.15" + attribute \src "libresoc.v:175391.7-175391.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -357311,7 +359808,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174171$10374 + cell $add $add$libresoc.v:175803$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357319,10 +359816,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:174171$10374_Y + connect \Y $add$libresoc.v:175803$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174172$10375 + cell $add $add$libresoc.v:175804$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357330,10 +359827,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:174172$10375_Y + connect \Y $add$libresoc.v:175804$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174173$10376 + cell $add $add$libresoc.v:175805$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357341,10 +359838,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:174173$10376_Y + connect \Y $add$libresoc.v:175805$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174174$10377 + cell $add $add$libresoc.v:175806$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357352,10 +359849,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:174174$10377_Y + connect \Y $add$libresoc.v:175806$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174175$10378 + cell $add $add$libresoc.v:175807$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357363,10 +359860,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:174175$10378_Y + connect \Y $add$libresoc.v:175807$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174176$10379 + cell $add $add$libresoc.v:175808$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357374,10 +359871,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:174176$10379_Y + connect \Y $add$libresoc.v:175808$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174177$10380 + cell $add $add$libresoc.v:175809$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357385,10 +359882,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:174177$10380_Y + connect \Y $add$libresoc.v:175809$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174178$10381 + cell $add $add$libresoc.v:175810$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357396,10 +359893,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:174178$10381_Y + connect \Y $add$libresoc.v:175810$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174179$10382 + cell $add $add$libresoc.v:175811$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357407,10 +359904,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:174179$10382_Y + connect \Y $add$libresoc.v:175811$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174180$10383 + cell $add $add$libresoc.v:175812$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357418,10 +359915,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:174180$10383_Y + connect \Y $add$libresoc.v:175812$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174181$10384 + cell $add $add$libresoc.v:175813$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357429,10 +359926,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:174181$10384_Y + connect \Y $add$libresoc.v:175813$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174182$10385 + cell $add $add$libresoc.v:175814$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357440,10 +359937,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:174182$10385_Y + connect \Y $add$libresoc.v:175814$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174183$10386 + cell $add $add$libresoc.v:175815$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357451,10 +359948,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:174183$10386_Y + connect \Y $add$libresoc.v:175815$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174184$10387 + cell $add $add$libresoc.v:175816$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357462,10 +359959,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:174184$10387_Y + connect \Y $add$libresoc.v:175816$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174185$10388 + cell $add $add$libresoc.v:175817$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357473,10 +359970,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:174185$10388_Y + connect \Y $add$libresoc.v:175817$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174186$10389 + cell $add $add$libresoc.v:175818$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357484,10 +359981,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:174186$10389_Y + connect \Y $add$libresoc.v:175818$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174187$10390 + cell $add $add$libresoc.v:175819$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357495,10 +359992,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:174187$10390_Y + connect \Y $add$libresoc.v:175819$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174188$10391 + cell $add $add$libresoc.v:175820$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357506,10 +360003,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:174188$10391_Y + connect \Y $add$libresoc.v:175820$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174189$10392 + cell $add $add$libresoc.v:175821$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357517,10 +360014,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:174189$10392_Y + connect \Y $add$libresoc.v:175821$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174190$10393 + cell $add $add$libresoc.v:175822$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357528,10 +360025,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:174190$10393_Y + connect \Y $add$libresoc.v:175822$10441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174191$10394 + cell $add $add$libresoc.v:175823$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357539,10 +360036,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:174191$10394_Y + connect \Y $add$libresoc.v:175823$10442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174192$10395 + cell $add $add$libresoc.v:175824$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357550,10 +360047,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:174192$10395_Y + connect \Y $add$libresoc.v:175824$10443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174193$10396 + cell $add $add$libresoc.v:175825$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357561,10 +360058,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:174193$10396_Y + connect \Y $add$libresoc.v:175825$10444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174194$10397 + cell $add $add$libresoc.v:175826$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357572,10 +360069,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:174194$10397_Y + connect \Y $add$libresoc.v:175826$10445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174195$10398 + cell $add $add$libresoc.v:175827$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -357583,10 +360080,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:174195$10398_Y + connect \Y $add$libresoc.v:175827$10446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174196$10399 + cell $add $add$libresoc.v:175828$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357594,10 +360091,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:174196$10399_Y + connect \Y $add$libresoc.v:175828$10447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174197$10400 + cell $add $add$libresoc.v:175829$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357605,10 +360102,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:174197$10400_Y + connect \Y $add$libresoc.v:175829$10448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174198$10401 + cell $add $add$libresoc.v:175830$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357616,10 +360113,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:174198$10401_Y + connect \Y $add$libresoc.v:175830$10449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174199$10402 + cell $add $add$libresoc.v:175831$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357627,10 +360124,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:174199$10402_Y + connect \Y $add$libresoc.v:175831$10450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174200$10403 + cell $add $add$libresoc.v:175832$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -357638,10 +360135,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:174200$10403_Y + connect \Y $add$libresoc.v:175832$10451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174201$10404 + cell $add $add$libresoc.v:175833$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -357649,10 +360146,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:174201$10404_Y + connect \Y $add$libresoc.v:175833$10452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174202$10405 + cell $add $add$libresoc.v:175834$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -357660,10 +360157,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:174202$10405_Y + connect \Y $add$libresoc.v:175834$10453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174203$10406 + cell $add $add$libresoc.v:175835$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -357671,10 +360168,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:174203$10406_Y + connect \Y $add$libresoc.v:175835$10454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174214$10425 + cell $add $add$libresoc.v:175846$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357682,10 +360179,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:174214$10425_Y + connect \Y $add$libresoc.v:175846$10473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174218$10432 + cell $add $add$libresoc.v:175850$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357693,10 +360190,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:174218$10432_Y + connect \Y $add$libresoc.v:175850$10480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174219$10433 + cell $add $add$libresoc.v:175851$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357704,10 +360201,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:174219$10433_Y + connect \Y $add$libresoc.v:175851$10481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174220$10434 + cell $add $add$libresoc.v:175852$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357715,10 +360212,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:174220$10434_Y + connect \Y $add$libresoc.v:175852$10482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174221$10435 + cell $add $add$libresoc.v:175853$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357726,10 +360223,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:174221$10435_Y + connect \Y $add$libresoc.v:175853$10483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174222$10436 + cell $add $add$libresoc.v:175854$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357737,10 +360234,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:174222$10436_Y + connect \Y $add$libresoc.v:175854$10484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174223$10437 + cell $add $add$libresoc.v:175855$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357748,10 +360245,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:174223$10437_Y + connect \Y $add$libresoc.v:175855$10485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174224$10438 + cell $add $add$libresoc.v:175856$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357759,10 +360256,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:174224$10438_Y + connect \Y $add$libresoc.v:175856$10486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174225$10439 + cell $add $add$libresoc.v:175857$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357770,10 +360267,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:174225$10439_Y + connect \Y $add$libresoc.v:175857$10487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174226$10440 + cell $add $add$libresoc.v:175858$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357781,10 +360278,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:174226$10440_Y + connect \Y $add$libresoc.v:175858$10488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174227$10441 + cell $add $add$libresoc.v:175859$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357792,10 +360289,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:174227$10441_Y + connect \Y $add$libresoc.v:175859$10489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174228$10442 + cell $add $add$libresoc.v:175860$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357803,10 +360300,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:174228$10442_Y + connect \Y $add$libresoc.v:175860$10490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174229$10443 + cell $add $add$libresoc.v:175861$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357814,10 +360311,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:174229$10443_Y + connect \Y $add$libresoc.v:175861$10491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174230$10444 + cell $add $add$libresoc.v:175862$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357825,10 +360322,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:174230$10444_Y + connect \Y $add$libresoc.v:175862$10492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174231$10445 + cell $add $add$libresoc.v:175863$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357836,10 +360333,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:174231$10445_Y + connect \Y $add$libresoc.v:175863$10493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174232$10446 + cell $add $add$libresoc.v:175864$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357847,10 +360344,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:174232$10446_Y + connect \Y $add$libresoc.v:175864$10494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174233$10447 + cell $add $add$libresoc.v:175865$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357858,10 +360355,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:174233$10447_Y + connect \Y $add$libresoc.v:175865$10495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174234$10448 + cell $add $add$libresoc.v:175866$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357869,10 +360366,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:174234$10448_Y + connect \Y $add$libresoc.v:175866$10496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174235$10449 + cell $add $add$libresoc.v:175867$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357880,10 +360377,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:174235$10449_Y + connect \Y $add$libresoc.v:175867$10497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174236$10450 + cell $add $add$libresoc.v:175868$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357891,10 +360388,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:174236$10450_Y + connect \Y $add$libresoc.v:175868$10498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174237$10451 + cell $add $add$libresoc.v:175869$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357902,10 +360399,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:174237$10451_Y + connect \Y $add$libresoc.v:175869$10499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174238$10452 + cell $add $add$libresoc.v:175870$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357913,10 +360410,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:174238$10452_Y + connect \Y $add$libresoc.v:175870$10500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174239$10453 + cell $add $add$libresoc.v:175871$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357924,10 +360421,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:174239$10453_Y + connect \Y $add$libresoc.v:175871$10501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174240$10454 + cell $add $add$libresoc.v:175872$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357935,10 +360432,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:174240$10454_Y + connect \Y $add$libresoc.v:175872$10502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174241$10455 + cell $add $add$libresoc.v:175873$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357946,10 +360443,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:174241$10455_Y + connect \Y $add$libresoc.v:175873$10503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174242$10456 + cell $add $add$libresoc.v:175874$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357957,10 +360454,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:174242$10456_Y + connect \Y $add$libresoc.v:175874$10504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174243$10457 + cell $add $add$libresoc.v:175875$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357968,10 +360465,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:174243$10457_Y + connect \Y $add$libresoc.v:175875$10505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174244$10458 + cell $add $add$libresoc.v:175876$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357979,10 +360476,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:174244$10458_Y + connect \Y $add$libresoc.v:175876$10506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174245$10459 + cell $add $add$libresoc.v:175877$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357990,10 +360487,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:174245$10459_Y + connect \Y $add$libresoc.v:175877$10507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:174246$10460 + cell $add $add$libresoc.v:175878$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -358001,10 +360498,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:174246$10460_Y + connect \Y $add$libresoc.v:175878$10508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:174204$10407 + cell $eq $eq$libresoc.v:175836$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -358012,10 +360509,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:174204$10407_Y + connect \Y $eq$libresoc.v:175836$10455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:174205$10408 + cell $eq $eq$libresoc.v:175837$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -358023,199 +360520,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:174205$10408_Y + connect \Y $eq$libresoc.v:175837$10456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174206$10409 + cell $pos $extend$libresoc.v:175838$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:174206$10409_Y + connect \Y $extend$libresoc.v:175838$10457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174207$10411 + cell $pos $extend$libresoc.v:175839$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:174207$10411_Y + connect \Y $extend$libresoc.v:175839$10459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174208$10413 + cell $pos $extend$libresoc.v:175840$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:174208$10413_Y + connect \Y $extend$libresoc.v:175840$10461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174209$10415 + cell $pos $extend$libresoc.v:175841$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:174209$10415_Y + connect \Y $extend$libresoc.v:175841$10463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174210$10417 + cell $pos $extend$libresoc.v:175842$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:174210$10417_Y + connect \Y $extend$libresoc.v:175842$10465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174211$10419 + cell $pos $extend$libresoc.v:175843$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:174211$10419_Y + connect \Y $extend$libresoc.v:175843$10467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174212$10421 + cell $pos $extend$libresoc.v:175844$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:174212$10421_Y + connect \Y $extend$libresoc.v:175844$10469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174213$10423 + cell $pos $extend$libresoc.v:175845$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:174213$10423_Y + connect \Y $extend$libresoc.v:175845$10471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174215$10426 + cell $pos $extend$libresoc.v:175847$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:174215$10426_Y + connect \Y $extend$libresoc.v:175847$10474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174216$10428 + cell $pos $extend$libresoc.v:175848$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:174216$10428_Y + connect \Y $extend$libresoc.v:175848$10476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:174217$10430 + cell $pos $extend$libresoc.v:175849$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:174217$10430_Y + connect \Y $extend$libresoc.v:175849$10478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174206$10410 + cell $pos $pos$libresoc.v:175838$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174206$10409_Y - connect \Y $pos$libresoc.v:174206$10410_Y + connect \A $extend$libresoc.v:175838$10457_Y + connect \Y $pos$libresoc.v:175838$10458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174207$10412 + cell $pos $pos$libresoc.v:175839$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174207$10411_Y - connect \Y $pos$libresoc.v:174207$10412_Y + connect \A $extend$libresoc.v:175839$10459_Y + connect \Y $pos$libresoc.v:175839$10460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174208$10414 + cell $pos $pos$libresoc.v:175840$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174208$10413_Y - connect \Y $pos$libresoc.v:174208$10414_Y + connect \A $extend$libresoc.v:175840$10461_Y + connect \Y $pos$libresoc.v:175840$10462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174209$10416 + cell $pos $pos$libresoc.v:175841$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174209$10415_Y - connect \Y $pos$libresoc.v:174209$10416_Y + connect \A $extend$libresoc.v:175841$10463_Y + connect \Y $pos$libresoc.v:175841$10464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174210$10418 + cell $pos $pos$libresoc.v:175842$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174210$10417_Y - connect \Y $pos$libresoc.v:174210$10418_Y + connect \A $extend$libresoc.v:175842$10465_Y + connect \Y $pos$libresoc.v:175842$10466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174211$10420 + cell $pos $pos$libresoc.v:175843$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174211$10419_Y - connect \Y $pos$libresoc.v:174211$10420_Y + connect \A $extend$libresoc.v:175843$10467_Y + connect \Y $pos$libresoc.v:175843$10468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174212$10422 + cell $pos $pos$libresoc.v:175844$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174212$10421_Y - connect \Y $pos$libresoc.v:174212$10422_Y + connect \A $extend$libresoc.v:175844$10469_Y + connect \Y $pos$libresoc.v:175844$10470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174213$10424 + cell $pos $pos$libresoc.v:175845$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:174213$10423_Y - connect \Y $pos$libresoc.v:174213$10424_Y + connect \A $extend$libresoc.v:175845$10471_Y + connect \Y $pos$libresoc.v:175845$10472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174215$10427 + cell $pos $pos$libresoc.v:175847$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:174215$10426_Y - connect \Y $pos$libresoc.v:174215$10427_Y + connect \A $extend$libresoc.v:175847$10474_Y + connect \Y $pos$libresoc.v:175847$10475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174216$10429 + cell $pos $pos$libresoc.v:175848$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:174216$10428_Y - connect \Y $pos$libresoc.v:174216$10429_Y + connect \A $extend$libresoc.v:175848$10476_Y + connect \Y $pos$libresoc.v:175848$10477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:174217$10431 + cell $pos $pos$libresoc.v:175849$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:174217$10430_Y - connect \Y $pos$libresoc.v:174217$10431_Y + connect \A $extend$libresoc.v:175849$10478_Y + connect \Y $pos$libresoc.v:175849$10479_Y end - attribute \src "libresoc.v:173759.7-173759.20" - process $proc$libresoc.v:173759$10462 + attribute \src "libresoc.v:175391.7-175391.20" + process $proc$libresoc.v:175391$10510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174247.3-174273.6" - process $proc$libresoc.v:174247$10461 + attribute \src "libresoc.v:175879.3-175905.6" + process $proc$libresoc.v:175879$10509 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:174248.5-174248.29" + attribute \src "libresoc.v:175880.5-175880.29" switch \initial - attribute \src "libresoc.v:174248.9-174248.17" + attribute \src "libresoc.v:175880.9-175880.17" case 1'1 case end @@ -358245,82 +360742,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:174171$10374_Y - connect \$104 $add$libresoc.v:174172$10375_Y - connect \$107 $add$libresoc.v:174173$10376_Y - connect \$110 $add$libresoc.v:174174$10377_Y - connect \$113 $add$libresoc.v:174175$10378_Y - connect \$116 $add$libresoc.v:174176$10379_Y - connect \$11 $add$libresoc.v:174177$10380_Y - connect \$119 $add$libresoc.v:174178$10381_Y - connect \$122 $add$libresoc.v:174179$10382_Y - connect \$125 $add$libresoc.v:174180$10383_Y - connect \$128 $add$libresoc.v:174181$10384_Y - connect \$131 $add$libresoc.v:174182$10385_Y - connect \$134 $add$libresoc.v:174183$10386_Y - connect \$137 $add$libresoc.v:174184$10387_Y - connect \$140 $add$libresoc.v:174185$10388_Y - connect \$143 $add$libresoc.v:174186$10389_Y - connect \$146 $add$libresoc.v:174187$10390_Y - connect \$14 $add$libresoc.v:174188$10391_Y - connect \$149 $add$libresoc.v:174189$10392_Y - connect \$152 $add$libresoc.v:174190$10393_Y - connect \$155 $add$libresoc.v:174191$10394_Y - connect \$158 $add$libresoc.v:174192$10395_Y - connect \$161 $add$libresoc.v:174193$10396_Y - connect \$164 $add$libresoc.v:174194$10397_Y - connect \$167 $add$libresoc.v:174195$10398_Y - connect \$170 $add$libresoc.v:174196$10399_Y - connect \$173 $add$libresoc.v:174197$10400_Y - connect \$176 $add$libresoc.v:174198$10401_Y - connect \$17 $add$libresoc.v:174199$10402_Y - connect \$179 $add$libresoc.v:174200$10403_Y - connect \$182 $add$libresoc.v:174201$10404_Y - connect \$185 $add$libresoc.v:174202$10405_Y - connect \$188 $add$libresoc.v:174203$10406_Y - connect \$190 $eq$libresoc.v:174204$10407_Y - connect \$192 $eq$libresoc.v:174205$10408_Y - connect \$194 $pos$libresoc.v:174206$10410_Y - connect \$196 $pos$libresoc.v:174207$10412_Y - connect \$198 $pos$libresoc.v:174208$10414_Y - connect \$200 $pos$libresoc.v:174209$10416_Y - connect \$202 $pos$libresoc.v:174210$10418_Y - connect \$204 $pos$libresoc.v:174211$10420_Y - connect \$206 $pos$libresoc.v:174212$10422_Y - connect \$208 $pos$libresoc.v:174213$10424_Y - connect \$20 $add$libresoc.v:174214$10425_Y - connect \$210 $pos$libresoc.v:174215$10427_Y - connect \$212 $pos$libresoc.v:174216$10429_Y - connect \$214 $pos$libresoc.v:174217$10431_Y - connect \$23 $add$libresoc.v:174218$10432_Y - connect \$26 $add$libresoc.v:174219$10433_Y - connect \$2 $add$libresoc.v:174220$10434_Y - connect \$29 $add$libresoc.v:174221$10435_Y - connect \$32 $add$libresoc.v:174222$10436_Y - connect \$35 $add$libresoc.v:174223$10437_Y - connect \$38 $add$libresoc.v:174224$10438_Y - connect \$41 $add$libresoc.v:174225$10439_Y - connect \$44 $add$libresoc.v:174226$10440_Y - connect \$47 $add$libresoc.v:174227$10441_Y - connect \$50 $add$libresoc.v:174228$10442_Y - connect \$53 $add$libresoc.v:174229$10443_Y - connect \$56 $add$libresoc.v:174230$10444_Y - connect \$5 $add$libresoc.v:174231$10445_Y - connect \$59 $add$libresoc.v:174232$10446_Y - connect \$62 $add$libresoc.v:174233$10447_Y - connect \$65 $add$libresoc.v:174234$10448_Y - connect \$68 $add$libresoc.v:174235$10449_Y - connect \$71 $add$libresoc.v:174236$10450_Y - connect \$74 $add$libresoc.v:174237$10451_Y - connect \$77 $add$libresoc.v:174238$10452_Y - connect \$80 $add$libresoc.v:174239$10453_Y - connect \$83 $add$libresoc.v:174240$10454_Y - connect \$86 $add$libresoc.v:174241$10455_Y - connect \$8 $add$libresoc.v:174242$10456_Y - connect \$89 $add$libresoc.v:174243$10457_Y - connect \$92 $add$libresoc.v:174244$10458_Y - connect \$95 $add$libresoc.v:174245$10459_Y - connect \$98 $add$libresoc.v:174246$10460_Y + connect \$101 $add$libresoc.v:175803$10422_Y + connect \$104 $add$libresoc.v:175804$10423_Y + connect \$107 $add$libresoc.v:175805$10424_Y + connect \$110 $add$libresoc.v:175806$10425_Y + connect \$113 $add$libresoc.v:175807$10426_Y + connect \$116 $add$libresoc.v:175808$10427_Y + connect \$11 $add$libresoc.v:175809$10428_Y + connect \$119 $add$libresoc.v:175810$10429_Y + connect \$122 $add$libresoc.v:175811$10430_Y + connect \$125 $add$libresoc.v:175812$10431_Y + connect \$128 $add$libresoc.v:175813$10432_Y + connect \$131 $add$libresoc.v:175814$10433_Y + connect \$134 $add$libresoc.v:175815$10434_Y + connect \$137 $add$libresoc.v:175816$10435_Y + connect \$140 $add$libresoc.v:175817$10436_Y + connect \$143 $add$libresoc.v:175818$10437_Y + connect \$146 $add$libresoc.v:175819$10438_Y + connect \$14 $add$libresoc.v:175820$10439_Y + connect \$149 $add$libresoc.v:175821$10440_Y + connect \$152 $add$libresoc.v:175822$10441_Y + connect \$155 $add$libresoc.v:175823$10442_Y + connect \$158 $add$libresoc.v:175824$10443_Y + connect \$161 $add$libresoc.v:175825$10444_Y + connect \$164 $add$libresoc.v:175826$10445_Y + connect \$167 $add$libresoc.v:175827$10446_Y + connect \$170 $add$libresoc.v:175828$10447_Y + connect \$173 $add$libresoc.v:175829$10448_Y + connect \$176 $add$libresoc.v:175830$10449_Y + connect \$17 $add$libresoc.v:175831$10450_Y + connect \$179 $add$libresoc.v:175832$10451_Y + connect \$182 $add$libresoc.v:175833$10452_Y + connect \$185 $add$libresoc.v:175834$10453_Y + connect \$188 $add$libresoc.v:175835$10454_Y + connect \$190 $eq$libresoc.v:175836$10455_Y + connect \$192 $eq$libresoc.v:175837$10456_Y + connect \$194 $pos$libresoc.v:175838$10458_Y + connect \$196 $pos$libresoc.v:175839$10460_Y + connect \$198 $pos$libresoc.v:175840$10462_Y + connect \$200 $pos$libresoc.v:175841$10464_Y + connect \$202 $pos$libresoc.v:175842$10466_Y + connect \$204 $pos$libresoc.v:175843$10468_Y + connect \$206 $pos$libresoc.v:175844$10470_Y + connect \$208 $pos$libresoc.v:175845$10472_Y + connect \$20 $add$libresoc.v:175846$10473_Y + connect \$210 $pos$libresoc.v:175847$10475_Y + connect \$212 $pos$libresoc.v:175848$10477_Y + connect \$214 $pos$libresoc.v:175849$10479_Y + connect \$23 $add$libresoc.v:175850$10480_Y + connect \$26 $add$libresoc.v:175851$10481_Y + connect \$2 $add$libresoc.v:175852$10482_Y + connect \$29 $add$libresoc.v:175853$10483_Y + connect \$32 $add$libresoc.v:175854$10484_Y + connect \$35 $add$libresoc.v:175855$10485_Y + connect \$38 $add$libresoc.v:175856$10486_Y + connect \$41 $add$libresoc.v:175857$10487_Y + connect \$44 $add$libresoc.v:175858$10488_Y + connect \$47 $add$libresoc.v:175859$10489_Y + connect \$50 $add$libresoc.v:175860$10490_Y + connect \$53 $add$libresoc.v:175861$10491_Y + connect \$56 $add$libresoc.v:175862$10492_Y + connect \$5 $add$libresoc.v:175863$10493_Y + connect \$59 $add$libresoc.v:175864$10494_Y + connect \$62 $add$libresoc.v:175865$10495_Y + connect \$65 $add$libresoc.v:175866$10496_Y + connect \$68 $add$libresoc.v:175867$10497_Y + connect \$71 $add$libresoc.v:175868$10498_Y + connect \$74 $add$libresoc.v:175869$10499_Y + connect \$77 $add$libresoc.v:175870$10500_Y + connect \$80 $add$libresoc.v:175871$10501_Y + connect \$83 $add$libresoc.v:175872$10502_Y + connect \$86 $add$libresoc.v:175873$10503_Y + connect \$8 $add$libresoc.v:175874$10504_Y + connect \$89 $add$libresoc.v:175875$10505_Y + connect \$92 $add$libresoc.v:175876$10506_Y + connect \$95 $add$libresoc.v:175877$10507_Y + connect \$98 $add$libresoc.v:175878$10508_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -358448,43 +360945,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:174404.1-174488.10" +attribute \src "libresoc.v:176036.1-176120.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:174461.17-174461.91" - wire $not$libresoc.v:174461$10463_Y - attribute \src "libresoc.v:174463.18-174463.93" - wire $not$libresoc.v:174463$10465_Y - attribute \src "libresoc.v:174465.18-174465.93" - wire $not$libresoc.v:174465$10467_Y - attribute \src "libresoc.v:174466.17-174466.138" - wire width 8 $not$libresoc.v:174466$10468_Y - attribute \src "libresoc.v:174468.18-174468.93" - wire $not$libresoc.v:174468$10470_Y - attribute \src "libresoc.v:174470.18-174470.93" - wire $not$libresoc.v:174470$10472_Y - attribute \src "libresoc.v:174472.18-174472.93" - wire $not$libresoc.v:174472$10474_Y - attribute \src "libresoc.v:174475.17-174475.91" - wire $not$libresoc.v:174475$10477_Y - attribute \src "libresoc.v:174462.18-174462.116" - wire $reduce_or$libresoc.v:174462$10464_Y - attribute \src "libresoc.v:174464.18-174464.122" - wire $reduce_or$libresoc.v:174464$10466_Y - attribute \src "libresoc.v:174467.18-174467.128" - wire $reduce_or$libresoc.v:174467$10469_Y - attribute \src "libresoc.v:174469.18-174469.134" - wire $reduce_or$libresoc.v:174469$10471_Y - attribute \src "libresoc.v:174471.18-174471.140" - wire $reduce_or$libresoc.v:174471$10473_Y - attribute \src "libresoc.v:174473.18-174473.90" - wire $reduce_or$libresoc.v:174473$10475_Y - attribute \src "libresoc.v:174474.17-174474.103" - wire $reduce_or$libresoc.v:174474$10476_Y - attribute \src "libresoc.v:174476.17-174476.109" - wire $reduce_or$libresoc.v:174476$10478_Y + attribute \src "libresoc.v:176093.17-176093.91" + wire $not$libresoc.v:176093$10511_Y + attribute \src "libresoc.v:176095.18-176095.93" + wire $not$libresoc.v:176095$10513_Y + attribute \src "libresoc.v:176097.18-176097.93" + wire $not$libresoc.v:176097$10515_Y + attribute \src "libresoc.v:176098.17-176098.138" + wire width 8 $not$libresoc.v:176098$10516_Y + attribute \src "libresoc.v:176100.18-176100.93" + wire $not$libresoc.v:176100$10518_Y + attribute \src "libresoc.v:176102.18-176102.93" + wire $not$libresoc.v:176102$10520_Y + attribute \src "libresoc.v:176104.18-176104.93" + wire $not$libresoc.v:176104$10522_Y + attribute \src "libresoc.v:176107.17-176107.91" + wire $not$libresoc.v:176107$10525_Y + attribute \src "libresoc.v:176094.18-176094.116" + wire $reduce_or$libresoc.v:176094$10512_Y + attribute \src "libresoc.v:176096.18-176096.122" + wire $reduce_or$libresoc.v:176096$10514_Y + attribute \src "libresoc.v:176099.18-176099.128" + wire $reduce_or$libresoc.v:176099$10517_Y + attribute \src "libresoc.v:176101.18-176101.134" + wire $reduce_or$libresoc.v:176101$10519_Y + attribute \src "libresoc.v:176103.18-176103.140" + wire $reduce_or$libresoc.v:176103$10521_Y + attribute \src "libresoc.v:176105.18-176105.90" + wire $reduce_or$libresoc.v:176105$10523_Y + attribute \src "libresoc.v:176106.17-176106.103" + wire $reduce_or$libresoc.v:176106$10524_Y + attribute \src "libresoc.v:176108.17-176108.109" + wire $reduce_or$libresoc.v:176108$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358542,149 +361039,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174461$10463 + cell $not $not$libresoc.v:176093$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174461$10463_Y + connect \Y $not$libresoc.v:176093$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174463$10465 + cell $not $not$libresoc.v:176095$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174463$10465_Y + connect \Y $not$libresoc.v:176095$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174465$10467 + cell $not $not$libresoc.v:176097$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174465$10467_Y + connect \Y $not$libresoc.v:176097$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174466$10468 + cell $not $not$libresoc.v:176098$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:174466$10468_Y + connect \Y $not$libresoc.v:176098$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174468$10470 + cell $not $not$libresoc.v:176100$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174468$10470_Y + connect \Y $not$libresoc.v:176100$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174470$10472 + cell $not $not$libresoc.v:176102$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174470$10472_Y + connect \Y $not$libresoc.v:176102$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174472$10474 + cell $not $not$libresoc.v:176104$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174472$10474_Y + connect \Y $not$libresoc.v:176104$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174475$10477 + cell $not $not$libresoc.v:176107$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174475$10477_Y + connect \Y $not$libresoc.v:176107$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174462$10464 + cell $reduce_or $reduce_or$libresoc.v:176094$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:174462$10464_Y + connect \Y $reduce_or$libresoc.v:176094$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174464$10466 + cell $reduce_or $reduce_or$libresoc.v:176096$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:174464$10466_Y + connect \Y $reduce_or$libresoc.v:176096$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174467$10469 + cell $reduce_or $reduce_or$libresoc.v:176099$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:174467$10469_Y + connect \Y $reduce_or$libresoc.v:176099$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174469$10471 + cell $reduce_or $reduce_or$libresoc.v:176101$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:174469$10471_Y + connect \Y $reduce_or$libresoc.v:176101$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174471$10473 + cell $reduce_or $reduce_or$libresoc.v:176103$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:174471$10473_Y + connect \Y $reduce_or$libresoc.v:176103$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174473$10475 + cell $reduce_or $reduce_or$libresoc.v:176105$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174473$10475_Y + connect \Y $reduce_or$libresoc.v:176105$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174474$10476 + cell $reduce_or $reduce_or$libresoc.v:176106$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:174474$10476_Y + connect \Y $reduce_or$libresoc.v:176106$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174476$10478 + cell $reduce_or $reduce_or$libresoc.v:176108$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:174476$10478_Y - end - connect \$7 $not$libresoc.v:174461$10463_Y - connect \$12 $reduce_or$libresoc.v:174462$10464_Y - connect \$11 $not$libresoc.v:174463$10465_Y - connect \$16 $reduce_or$libresoc.v:174464$10466_Y - connect \$15 $not$libresoc.v:174465$10467_Y - connect \$1 $not$libresoc.v:174466$10468_Y - connect \$20 $reduce_or$libresoc.v:174467$10469_Y - connect \$19 $not$libresoc.v:174468$10470_Y - connect \$24 $reduce_or$libresoc.v:174469$10471_Y - connect \$23 $not$libresoc.v:174470$10472_Y - connect \$28 $reduce_or$libresoc.v:174471$10473_Y - connect \$27 $not$libresoc.v:174472$10474_Y - connect \$31 $reduce_or$libresoc.v:174473$10475_Y - connect \$4 $reduce_or$libresoc.v:174474$10476_Y - connect \$3 $not$libresoc.v:174475$10477_Y - connect \$8 $reduce_or$libresoc.v:174476$10478_Y + connect \Y $reduce_or$libresoc.v:176108$10526_Y + end + connect \$7 $not$libresoc.v:176093$10511_Y + connect \$12 $reduce_or$libresoc.v:176094$10512_Y + connect \$11 $not$libresoc.v:176095$10513_Y + connect \$16 $reduce_or$libresoc.v:176096$10514_Y + connect \$15 $not$libresoc.v:176097$10515_Y + connect \$1 $not$libresoc.v:176098$10516_Y + connect \$20 $reduce_or$libresoc.v:176099$10517_Y + connect \$19 $not$libresoc.v:176100$10518_Y + connect \$24 $reduce_or$libresoc.v:176101$10519_Y + connect \$23 $not$libresoc.v:176102$10520_Y + connect \$28 $reduce_or$libresoc.v:176103$10521_Y + connect \$27 $not$libresoc.v:176104$10522_Y + connect \$31 $reduce_or$libresoc.v:176105$10523_Y + connect \$4 $reduce_or$libresoc.v:176106$10524_Y + connect \$3 $not$libresoc.v:176107$10525_Y + connect \$8 $reduce_or$libresoc.v:176108$10526_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358697,43 +361194,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:174492.1-174576.10" +attribute \src "libresoc.v:176124.1-176208.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:174549.17-174549.91" - wire $not$libresoc.v:174549$10479_Y - attribute \src "libresoc.v:174551.18-174551.93" - wire $not$libresoc.v:174551$10481_Y - attribute \src "libresoc.v:174553.18-174553.93" - wire $not$libresoc.v:174553$10483_Y - attribute \src "libresoc.v:174554.17-174554.138" - wire width 8 $not$libresoc.v:174554$10484_Y - attribute \src "libresoc.v:174556.18-174556.93" - wire $not$libresoc.v:174556$10486_Y - attribute \src "libresoc.v:174558.18-174558.93" - wire $not$libresoc.v:174558$10488_Y - attribute \src "libresoc.v:174560.18-174560.93" - wire $not$libresoc.v:174560$10490_Y - attribute \src "libresoc.v:174563.17-174563.91" - wire $not$libresoc.v:174563$10493_Y - attribute \src "libresoc.v:174550.18-174550.116" - wire $reduce_or$libresoc.v:174550$10480_Y - attribute \src "libresoc.v:174552.18-174552.122" - wire $reduce_or$libresoc.v:174552$10482_Y - attribute \src "libresoc.v:174555.18-174555.128" - wire $reduce_or$libresoc.v:174555$10485_Y - attribute \src "libresoc.v:174557.18-174557.134" - wire $reduce_or$libresoc.v:174557$10487_Y - attribute \src "libresoc.v:174559.18-174559.140" - wire $reduce_or$libresoc.v:174559$10489_Y - attribute \src "libresoc.v:174561.18-174561.90" - wire $reduce_or$libresoc.v:174561$10491_Y - attribute \src "libresoc.v:174562.17-174562.103" - wire $reduce_or$libresoc.v:174562$10492_Y - attribute \src "libresoc.v:174564.17-174564.109" - wire $reduce_or$libresoc.v:174564$10494_Y + attribute \src "libresoc.v:176181.17-176181.91" + wire $not$libresoc.v:176181$10527_Y + attribute \src "libresoc.v:176183.18-176183.93" + wire $not$libresoc.v:176183$10529_Y + attribute \src "libresoc.v:176185.18-176185.93" + wire $not$libresoc.v:176185$10531_Y + attribute \src "libresoc.v:176186.17-176186.138" + wire width 8 $not$libresoc.v:176186$10532_Y + attribute \src "libresoc.v:176188.18-176188.93" + wire $not$libresoc.v:176188$10534_Y + attribute \src "libresoc.v:176190.18-176190.93" + wire $not$libresoc.v:176190$10536_Y + attribute \src "libresoc.v:176192.18-176192.93" + wire $not$libresoc.v:176192$10538_Y + attribute \src "libresoc.v:176195.17-176195.91" + wire $not$libresoc.v:176195$10541_Y + attribute \src "libresoc.v:176182.18-176182.116" + wire $reduce_or$libresoc.v:176182$10528_Y + attribute \src "libresoc.v:176184.18-176184.122" + wire $reduce_or$libresoc.v:176184$10530_Y + attribute \src "libresoc.v:176187.18-176187.128" + wire $reduce_or$libresoc.v:176187$10533_Y + attribute \src "libresoc.v:176189.18-176189.134" + wire $reduce_or$libresoc.v:176189$10535_Y + attribute \src "libresoc.v:176191.18-176191.140" + wire $reduce_or$libresoc.v:176191$10537_Y + attribute \src "libresoc.v:176193.18-176193.90" + wire $reduce_or$libresoc.v:176193$10539_Y + attribute \src "libresoc.v:176194.17-176194.103" + wire $reduce_or$libresoc.v:176194$10540_Y + attribute \src "libresoc.v:176196.17-176196.109" + wire $reduce_or$libresoc.v:176196$10542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358791,149 +361288,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174549$10479 + cell $not $not$libresoc.v:176181$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174549$10479_Y + connect \Y $not$libresoc.v:176181$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174551$10481 + cell $not $not$libresoc.v:176183$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174551$10481_Y + connect \Y $not$libresoc.v:176183$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174553$10483 + cell $not $not$libresoc.v:176185$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174553$10483_Y + connect \Y $not$libresoc.v:176185$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174554$10484 + cell $not $not$libresoc.v:176186$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:174554$10484_Y + connect \Y $not$libresoc.v:176186$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174556$10486 + cell $not $not$libresoc.v:176188$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174556$10486_Y + connect \Y $not$libresoc.v:176188$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174558$10488 + cell $not $not$libresoc.v:176190$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174558$10488_Y + connect \Y $not$libresoc.v:176190$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174560$10490 + cell $not $not$libresoc.v:176192$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174560$10490_Y + connect \Y $not$libresoc.v:176192$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174563$10493 + cell $not $not$libresoc.v:176195$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174563$10493_Y + connect \Y $not$libresoc.v:176195$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174550$10480 + cell $reduce_or $reduce_or$libresoc.v:176182$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:174550$10480_Y + connect \Y $reduce_or$libresoc.v:176182$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174552$10482 + cell $reduce_or $reduce_or$libresoc.v:176184$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:174552$10482_Y + connect \Y $reduce_or$libresoc.v:176184$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174555$10485 + cell $reduce_or $reduce_or$libresoc.v:176187$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:174555$10485_Y + connect \Y $reduce_or$libresoc.v:176187$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174557$10487 + cell $reduce_or $reduce_or$libresoc.v:176189$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:174557$10487_Y + connect \Y $reduce_or$libresoc.v:176189$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174559$10489 + cell $reduce_or $reduce_or$libresoc.v:176191$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:174559$10489_Y + connect \Y $reduce_or$libresoc.v:176191$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174561$10491 + cell $reduce_or $reduce_or$libresoc.v:176193$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174561$10491_Y + connect \Y $reduce_or$libresoc.v:176193$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174562$10492 + cell $reduce_or $reduce_or$libresoc.v:176194$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:174562$10492_Y + connect \Y $reduce_or$libresoc.v:176194$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174564$10494 + cell $reduce_or $reduce_or$libresoc.v:176196$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:174564$10494_Y - end - connect \$7 $not$libresoc.v:174549$10479_Y - connect \$12 $reduce_or$libresoc.v:174550$10480_Y - connect \$11 $not$libresoc.v:174551$10481_Y - connect \$16 $reduce_or$libresoc.v:174552$10482_Y - connect \$15 $not$libresoc.v:174553$10483_Y - connect \$1 $not$libresoc.v:174554$10484_Y - connect \$20 $reduce_or$libresoc.v:174555$10485_Y - connect \$19 $not$libresoc.v:174556$10486_Y - connect \$24 $reduce_or$libresoc.v:174557$10487_Y - connect \$23 $not$libresoc.v:174558$10488_Y - connect \$28 $reduce_or$libresoc.v:174559$10489_Y - connect \$27 $not$libresoc.v:174560$10490_Y - connect \$31 $reduce_or$libresoc.v:174561$10491_Y - connect \$4 $reduce_or$libresoc.v:174562$10492_Y - connect \$3 $not$libresoc.v:174563$10493_Y - connect \$8 $reduce_or$libresoc.v:174564$10494_Y + connect \Y $reduce_or$libresoc.v:176196$10542_Y + end + connect \$7 $not$libresoc.v:176181$10527_Y + connect \$12 $reduce_or$libresoc.v:176182$10528_Y + connect \$11 $not$libresoc.v:176183$10529_Y + connect \$16 $reduce_or$libresoc.v:176184$10530_Y + connect \$15 $not$libresoc.v:176185$10531_Y + connect \$1 $not$libresoc.v:176186$10532_Y + connect \$20 $reduce_or$libresoc.v:176187$10533_Y + connect \$19 $not$libresoc.v:176188$10534_Y + connect \$24 $reduce_or$libresoc.v:176189$10535_Y + connect \$23 $not$libresoc.v:176190$10536_Y + connect \$28 $reduce_or$libresoc.v:176191$10537_Y + connect \$27 $not$libresoc.v:176192$10538_Y + connect \$31 $reduce_or$libresoc.v:176193$10539_Y + connect \$4 $reduce_or$libresoc.v:176194$10540_Y + connect \$3 $not$libresoc.v:176195$10541_Y + connect \$8 $reduce_or$libresoc.v:176196$10542_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358946,19 +361443,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:174580.1-174610.10" +attribute \src "libresoc.v:176212.1-176242.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:174601.17-174601.89" - wire width 2 $not$libresoc.v:174601$10495_Y - attribute \src "libresoc.v:174603.17-174603.91" - wire $not$libresoc.v:174603$10497_Y - attribute \src "libresoc.v:174602.17-174602.103" - wire $reduce_or$libresoc.v:174602$10496_Y - attribute \src "libresoc.v:174604.17-174604.89" - wire $reduce_or$libresoc.v:174604$10498_Y + attribute \src "libresoc.v:176233.17-176233.89" + wire width 2 $not$libresoc.v:176233$10543_Y + attribute \src "libresoc.v:176235.17-176235.91" + wire $not$libresoc.v:176235$10545_Y + attribute \src "libresoc.v:176234.17-176234.103" + wire $reduce_or$libresoc.v:176234$10544_Y + attribute \src "libresoc.v:176236.17-176236.89" + wire $reduce_or$libresoc.v:176236$10546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358980,56 +361477,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174601$10495 + cell $not $not$libresoc.v:176233$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174601$10495_Y + connect \Y $not$libresoc.v:176233$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174603$10497 + cell $not $not$libresoc.v:176235$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174603$10497_Y + connect \Y $not$libresoc.v:176235$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174602$10496 + cell $reduce_or $reduce_or$libresoc.v:176234$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174602$10496_Y + connect \Y $reduce_or$libresoc.v:176234$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174604$10498 + cell $reduce_or $reduce_or$libresoc.v:176236$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174604$10498_Y + connect \Y $reduce_or$libresoc.v:176236$10546_Y end - connect \$1 $not$libresoc.v:174601$10495_Y - connect \$4 $reduce_or$libresoc.v:174602$10496_Y - connect \$3 $not$libresoc.v:174603$10497_Y - connect \$7 $reduce_or$libresoc.v:174604$10498_Y + connect \$1 $not$libresoc.v:176233$10543_Y + connect \$4 $reduce_or$libresoc.v:176234$10544_Y + connect \$3 $not$libresoc.v:176235$10545_Y + connect \$7 $reduce_or$libresoc.v:176236$10546_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174614.1-174635.10" +attribute \src "libresoc.v:176246.1-176267.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:174629.17-174629.89" - wire $not$libresoc.v:174629$10499_Y - attribute \src "libresoc.v:174630.17-174630.89" - wire $reduce_or$libresoc.v:174630$10500_Y + attribute \src "libresoc.v:176261.17-176261.89" + wire $not$libresoc.v:176261$10547_Y + attribute \src "libresoc.v:176262.17-176262.89" + wire $reduce_or$libresoc.v:176262$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359045,37 +361542,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174629$10499 + cell $not $not$libresoc.v:176261$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174629$10499_Y + connect \Y $not$libresoc.v:176261$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174630$10500 + cell $reduce_or $reduce_or$libresoc.v:176262$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174630$10500_Y + connect \Y $reduce_or$libresoc.v:176262$10548_Y end - connect \$1 $not$libresoc.v:174629$10499_Y - connect \$3 $reduce_or$libresoc.v:174630$10500_Y + connect \$1 $not$libresoc.v:176261$10547_Y + connect \$3 $reduce_or$libresoc.v:176262$10548_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174639.1-174660.10" +attribute \src "libresoc.v:176271.1-176292.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:174654.17-174654.89" - wire $not$libresoc.v:174654$10501_Y - attribute \src "libresoc.v:174655.17-174655.89" - wire $reduce_or$libresoc.v:174655$10502_Y + attribute \src "libresoc.v:176286.17-176286.89" + wire $not$libresoc.v:176286$10549_Y + attribute \src "libresoc.v:176287.17-176287.89" + wire $reduce_or$libresoc.v:176287$10550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359091,37 +361588,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174654$10501 + cell $not $not$libresoc.v:176286$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174654$10501_Y + connect \Y $not$libresoc.v:176286$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174655$10502 + cell $reduce_or $reduce_or$libresoc.v:176287$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174655$10502_Y + connect \Y $reduce_or$libresoc.v:176287$10550_Y end - connect \$1 $not$libresoc.v:174654$10501_Y - connect \$3 $reduce_or$libresoc.v:174655$10502_Y + connect \$1 $not$libresoc.v:176286$10549_Y + connect \$3 $reduce_or$libresoc.v:176287$10550_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174664.1-174685.10" +attribute \src "libresoc.v:176296.1-176317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:174679.17-174679.89" - wire $not$libresoc.v:174679$10503_Y - attribute \src "libresoc.v:174680.17-174680.89" - wire $reduce_or$libresoc.v:174680$10504_Y + attribute \src "libresoc.v:176311.17-176311.89" + wire $not$libresoc.v:176311$10551_Y + attribute \src "libresoc.v:176312.17-176312.89" + wire $reduce_or$libresoc.v:176312$10552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359137,45 +361634,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174679$10503 + cell $not $not$libresoc.v:176311$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:174679$10503_Y + connect \Y $not$libresoc.v:176311$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174680$10504 + cell $reduce_or $reduce_or$libresoc.v:176312$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174680$10504_Y + connect \Y $reduce_or$libresoc.v:176312$10552_Y end - connect \$1 $not$libresoc.v:174679$10503_Y - connect \$3 $reduce_or$libresoc.v:174680$10504_Y + connect \$1 $not$libresoc.v:176311$10551_Y + connect \$3 $reduce_or$libresoc.v:176312$10552_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:174689.1-174728.10" +attribute \src "libresoc.v:176321.1-176360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:174716.17-174716.91" - wire $not$libresoc.v:174716$10505_Y - attribute \src "libresoc.v:174718.17-174718.89" - wire width 3 $not$libresoc.v:174718$10507_Y - attribute \src "libresoc.v:174720.17-174720.91" - wire $not$libresoc.v:174720$10509_Y - attribute \src "libresoc.v:174717.18-174717.90" - wire $reduce_or$libresoc.v:174717$10506_Y - attribute \src "libresoc.v:174719.17-174719.103" - wire $reduce_or$libresoc.v:174719$10508_Y - attribute \src "libresoc.v:174721.17-174721.105" - wire $reduce_or$libresoc.v:174721$10510_Y + attribute \src "libresoc.v:176348.17-176348.91" + wire $not$libresoc.v:176348$10553_Y + attribute \src "libresoc.v:176350.17-176350.89" + wire width 3 $not$libresoc.v:176350$10555_Y + attribute \src "libresoc.v:176352.17-176352.91" + wire $not$libresoc.v:176352$10557_Y + attribute \src "libresoc.v:176349.18-176349.90" + wire $reduce_or$libresoc.v:176349$10554_Y + attribute \src "libresoc.v:176351.17-176351.103" + wire $reduce_or$libresoc.v:176351$10556_Y + attribute \src "libresoc.v:176353.17-176353.105" + wire $reduce_or$libresoc.v:176353$10558_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359203,59 +361700,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174716$10505 + cell $not $not$libresoc.v:176348$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174716$10505_Y + connect \Y $not$libresoc.v:176348$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174718$10507 + cell $not $not$libresoc.v:176350$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:174718$10507_Y + connect \Y $not$libresoc.v:176350$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174720$10509 + cell $not $not$libresoc.v:176352$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174720$10509_Y + connect \Y $not$libresoc.v:176352$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174717$10506 + cell $reduce_or $reduce_or$libresoc.v:176349$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174717$10506_Y + connect \Y $reduce_or$libresoc.v:176349$10554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174719$10508 + cell $reduce_or $reduce_or$libresoc.v:176351$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174719$10508_Y + connect \Y $reduce_or$libresoc.v:176351$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174721$10510 + cell $reduce_or $reduce_or$libresoc.v:176353$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174721$10510_Y - end - connect \$7 $not$libresoc.v:174716$10505_Y - connect \$11 $reduce_or$libresoc.v:174717$10506_Y - connect \$1 $not$libresoc.v:174718$10507_Y - connect \$4 $reduce_or$libresoc.v:174719$10508_Y - connect \$3 $not$libresoc.v:174720$10509_Y - connect \$8 $reduce_or$libresoc.v:174721$10510_Y + connect \Y $reduce_or$libresoc.v:176353$10558_Y + end + connect \$7 $not$libresoc.v:176348$10553_Y + connect \$11 $reduce_or$libresoc.v:176349$10554_Y + connect \$1 $not$libresoc.v:176350$10555_Y + connect \$4 $reduce_or$libresoc.v:176351$10556_Y + connect \$3 $not$libresoc.v:176352$10557_Y + connect \$8 $reduce_or$libresoc.v:176353$10558_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -359263,19 +361760,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174732.1-174762.10" +attribute \src "libresoc.v:176364.1-176394.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:174753.17-174753.89" - wire width 2 $not$libresoc.v:174753$10511_Y - attribute \src "libresoc.v:174755.17-174755.91" - wire $not$libresoc.v:174755$10513_Y - attribute \src "libresoc.v:174754.17-174754.103" - wire $reduce_or$libresoc.v:174754$10512_Y - attribute \src "libresoc.v:174756.17-174756.89" - wire $reduce_or$libresoc.v:174756$10514_Y + attribute \src "libresoc.v:176385.17-176385.89" + wire width 2 $not$libresoc.v:176385$10559_Y + attribute \src "libresoc.v:176387.17-176387.91" + wire $not$libresoc.v:176387$10561_Y + attribute \src "libresoc.v:176386.17-176386.103" + wire $reduce_or$libresoc.v:176386$10560_Y + attribute \src "libresoc.v:176388.17-176388.89" + wire $reduce_or$libresoc.v:176388$10562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359297,88 +361794,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174753$10511 + cell $not $not$libresoc.v:176385$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174753$10511_Y + connect \Y $not$libresoc.v:176385$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174755$10513 + cell $not $not$libresoc.v:176387$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174755$10513_Y + connect \Y $not$libresoc.v:176387$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174754$10512 + cell $reduce_or $reduce_or$libresoc.v:176386$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174754$10512_Y + connect \Y $reduce_or$libresoc.v:176386$10560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174756$10514 + cell $reduce_or $reduce_or$libresoc.v:176388$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174756$10514_Y + connect \Y $reduce_or$libresoc.v:176388$10562_Y end - connect \$1 $not$libresoc.v:174753$10511_Y - connect \$4 $reduce_or$libresoc.v:174754$10512_Y - connect \$3 $not$libresoc.v:174755$10513_Y - connect \$7 $reduce_or$libresoc.v:174756$10514_Y + connect \$1 $not$libresoc.v:176385$10559_Y + connect \$4 $reduce_or$libresoc.v:176386$10560_Y + connect \$3 $not$libresoc.v:176387$10561_Y + connect \$7 $reduce_or$libresoc.v:176388$10562_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174766.1-174859.10" +attribute \src "libresoc.v:176398.1-176491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:174829.17-174829.91" - wire $not$libresoc.v:174829$10515_Y - attribute \src "libresoc.v:174831.18-174831.93" - wire $not$libresoc.v:174831$10517_Y - attribute \src "libresoc.v:174833.18-174833.93" - wire $not$libresoc.v:174833$10519_Y - attribute \src "libresoc.v:174834.17-174834.89" - wire width 9 $not$libresoc.v:174834$10520_Y - attribute \src "libresoc.v:174836.18-174836.93" - wire $not$libresoc.v:174836$10522_Y - attribute \src "libresoc.v:174838.18-174838.93" - wire $not$libresoc.v:174838$10524_Y - attribute \src "libresoc.v:174840.18-174840.93" - wire $not$libresoc.v:174840$10526_Y - attribute \src "libresoc.v:174842.18-174842.93" - wire $not$libresoc.v:174842$10528_Y - attribute \src "libresoc.v:174845.17-174845.91" - wire $not$libresoc.v:174845$10531_Y - attribute \src "libresoc.v:174830.18-174830.106" - wire $reduce_or$libresoc.v:174830$10516_Y - attribute \src "libresoc.v:174832.18-174832.106" - wire $reduce_or$libresoc.v:174832$10518_Y - attribute \src "libresoc.v:174835.18-174835.106" - wire $reduce_or$libresoc.v:174835$10521_Y - attribute \src "libresoc.v:174837.18-174837.106" - wire $reduce_or$libresoc.v:174837$10523_Y - attribute \src "libresoc.v:174839.18-174839.106" - wire $reduce_or$libresoc.v:174839$10525_Y - attribute \src "libresoc.v:174841.18-174841.106" - wire $reduce_or$libresoc.v:174841$10527_Y - attribute \src "libresoc.v:174843.18-174843.90" - wire $reduce_or$libresoc.v:174843$10529_Y - attribute \src "libresoc.v:174844.17-174844.103" - wire $reduce_or$libresoc.v:174844$10530_Y - attribute \src "libresoc.v:174846.17-174846.105" - wire $reduce_or$libresoc.v:174846$10532_Y + attribute \src "libresoc.v:176461.17-176461.91" + wire $not$libresoc.v:176461$10563_Y + attribute \src "libresoc.v:176463.18-176463.93" + wire $not$libresoc.v:176463$10565_Y + attribute \src "libresoc.v:176465.18-176465.93" + wire $not$libresoc.v:176465$10567_Y + attribute \src "libresoc.v:176466.17-176466.89" + wire width 9 $not$libresoc.v:176466$10568_Y + attribute \src "libresoc.v:176468.18-176468.93" + wire $not$libresoc.v:176468$10570_Y + attribute \src "libresoc.v:176470.18-176470.93" + wire $not$libresoc.v:176470$10572_Y + attribute \src "libresoc.v:176472.18-176472.93" + wire $not$libresoc.v:176472$10574_Y + attribute \src "libresoc.v:176474.18-176474.93" + wire $not$libresoc.v:176474$10576_Y + attribute \src "libresoc.v:176477.17-176477.91" + wire $not$libresoc.v:176477$10579_Y + attribute \src "libresoc.v:176462.18-176462.106" + wire $reduce_or$libresoc.v:176462$10564_Y + attribute \src "libresoc.v:176464.18-176464.106" + wire $reduce_or$libresoc.v:176464$10566_Y + attribute \src "libresoc.v:176467.18-176467.106" + wire $reduce_or$libresoc.v:176467$10569_Y + attribute \src "libresoc.v:176469.18-176469.106" + wire $reduce_or$libresoc.v:176469$10571_Y + attribute \src "libresoc.v:176471.18-176471.106" + wire $reduce_or$libresoc.v:176471$10573_Y + attribute \src "libresoc.v:176473.18-176473.106" + wire $reduce_or$libresoc.v:176473$10575_Y + attribute \src "libresoc.v:176475.18-176475.90" + wire $reduce_or$libresoc.v:176475$10577_Y + attribute \src "libresoc.v:176476.17-176476.103" + wire $reduce_or$libresoc.v:176476$10578_Y + attribute \src "libresoc.v:176478.17-176478.105" + wire $reduce_or$libresoc.v:176478$10580_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359442,167 +361939,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174829$10515 + cell $not $not$libresoc.v:176461$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174829$10515_Y + connect \Y $not$libresoc.v:176461$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174831$10517 + cell $not $not$libresoc.v:176463$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174831$10517_Y + connect \Y $not$libresoc.v:176463$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174833$10519 + cell $not $not$libresoc.v:176465$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174833$10519_Y + connect \Y $not$libresoc.v:176465$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174834$10520 + cell $not $not$libresoc.v:176466$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:174834$10520_Y + connect \Y $not$libresoc.v:176466$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174836$10522 + cell $not $not$libresoc.v:176468$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174836$10522_Y + connect \Y $not$libresoc.v:176468$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174838$10524 + cell $not $not$libresoc.v:176470$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174838$10524_Y + connect \Y $not$libresoc.v:176470$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174840$10526 + cell $not $not$libresoc.v:176472$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174840$10526_Y + connect \Y $not$libresoc.v:176472$10574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174842$10528 + cell $not $not$libresoc.v:176474$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:174842$10528_Y + connect \Y $not$libresoc.v:176474$10576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174845$10531 + cell $not $not$libresoc.v:176477$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174845$10531_Y + connect \Y $not$libresoc.v:176477$10579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174830$10516 + cell $reduce_or $reduce_or$libresoc.v:176462$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:174830$10516_Y + connect \Y $reduce_or$libresoc.v:176462$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174832$10518 + cell $reduce_or $reduce_or$libresoc.v:176464$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:174832$10518_Y + connect \Y $reduce_or$libresoc.v:176464$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174835$10521 + cell $reduce_or $reduce_or$libresoc.v:176467$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:174835$10521_Y + connect \Y $reduce_or$libresoc.v:176467$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174837$10523 + cell $reduce_or $reduce_or$libresoc.v:176469$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:174837$10523_Y + connect \Y $reduce_or$libresoc.v:176469$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174839$10525 + cell $reduce_or $reduce_or$libresoc.v:176471$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:174839$10525_Y + connect \Y $reduce_or$libresoc.v:176471$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174841$10527 + cell $reduce_or $reduce_or$libresoc.v:176473$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:174841$10527_Y + connect \Y $reduce_or$libresoc.v:176473$10575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174843$10529 + cell $reduce_or $reduce_or$libresoc.v:176475$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174843$10529_Y + connect \Y $reduce_or$libresoc.v:176475$10577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174844$10530 + cell $reduce_or $reduce_or$libresoc.v:176476$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174844$10530_Y + connect \Y $reduce_or$libresoc.v:176476$10578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174846$10532 + cell $reduce_or $reduce_or$libresoc.v:176478$10580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174846$10532_Y - end - connect \$7 $not$libresoc.v:174829$10515_Y - connect \$12 $reduce_or$libresoc.v:174830$10516_Y - connect \$11 $not$libresoc.v:174831$10517_Y - connect \$16 $reduce_or$libresoc.v:174832$10518_Y - connect \$15 $not$libresoc.v:174833$10519_Y - connect \$1 $not$libresoc.v:174834$10520_Y - connect \$20 $reduce_or$libresoc.v:174835$10521_Y - connect \$19 $not$libresoc.v:174836$10522_Y - connect \$24 $reduce_or$libresoc.v:174837$10523_Y - connect \$23 $not$libresoc.v:174838$10524_Y - connect \$28 $reduce_or$libresoc.v:174839$10525_Y - connect \$27 $not$libresoc.v:174840$10526_Y - connect \$32 $reduce_or$libresoc.v:174841$10527_Y - connect \$31 $not$libresoc.v:174842$10528_Y - connect \$35 $reduce_or$libresoc.v:174843$10529_Y - connect \$4 $reduce_or$libresoc.v:174844$10530_Y - connect \$3 $not$libresoc.v:174845$10531_Y - connect \$8 $reduce_or$libresoc.v:174846$10532_Y + connect \Y $reduce_or$libresoc.v:176478$10580_Y + end + connect \$7 $not$libresoc.v:176461$10563_Y + connect \$12 $reduce_or$libresoc.v:176462$10564_Y + connect \$11 $not$libresoc.v:176463$10565_Y + connect \$16 $reduce_or$libresoc.v:176464$10566_Y + connect \$15 $not$libresoc.v:176465$10567_Y + connect \$1 $not$libresoc.v:176466$10568_Y + connect \$20 $reduce_or$libresoc.v:176467$10569_Y + connect \$19 $not$libresoc.v:176468$10570_Y + connect \$24 $reduce_or$libresoc.v:176469$10571_Y + connect \$23 $not$libresoc.v:176470$10572_Y + connect \$28 $reduce_or$libresoc.v:176471$10573_Y + connect \$27 $not$libresoc.v:176472$10574_Y + connect \$32 $reduce_or$libresoc.v:176473$10575_Y + connect \$31 $not$libresoc.v:176474$10576_Y + connect \$35 $reduce_or$libresoc.v:176475$10577_Y + connect \$4 $reduce_or$libresoc.v:176476$10578_Y + connect \$3 $not$libresoc.v:176477$10579_Y + connect \$8 $reduce_or$libresoc.v:176478$10580_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -359616,43 +362113,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174863.1-174947.10" +attribute \src "libresoc.v:176495.1-176579.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:174920.17-174920.91" - wire $not$libresoc.v:174920$10533_Y - attribute \src "libresoc.v:174922.18-174922.93" - wire $not$libresoc.v:174922$10535_Y - attribute \src "libresoc.v:174924.18-174924.93" - wire $not$libresoc.v:174924$10537_Y - attribute \src "libresoc.v:174925.17-174925.89" - wire width 8 $not$libresoc.v:174925$10538_Y - attribute \src "libresoc.v:174927.18-174927.93" - wire $not$libresoc.v:174927$10540_Y - attribute \src "libresoc.v:174929.18-174929.93" - wire $not$libresoc.v:174929$10542_Y - attribute \src "libresoc.v:174931.18-174931.93" - wire $not$libresoc.v:174931$10544_Y - attribute \src "libresoc.v:174934.17-174934.91" - wire $not$libresoc.v:174934$10547_Y - attribute \src "libresoc.v:174921.18-174921.106" - wire $reduce_or$libresoc.v:174921$10534_Y - attribute \src "libresoc.v:174923.18-174923.106" - wire $reduce_or$libresoc.v:174923$10536_Y - attribute \src "libresoc.v:174926.18-174926.106" - wire $reduce_or$libresoc.v:174926$10539_Y - attribute \src "libresoc.v:174928.18-174928.106" - wire $reduce_or$libresoc.v:174928$10541_Y - attribute \src "libresoc.v:174930.18-174930.106" - wire $reduce_or$libresoc.v:174930$10543_Y - attribute \src "libresoc.v:174932.18-174932.90" - wire $reduce_or$libresoc.v:174932$10545_Y - attribute \src "libresoc.v:174933.17-174933.103" - wire $reduce_or$libresoc.v:174933$10546_Y - attribute \src "libresoc.v:174935.17-174935.105" - wire $reduce_or$libresoc.v:174935$10548_Y + attribute \src "libresoc.v:176552.17-176552.91" + wire $not$libresoc.v:176552$10581_Y + attribute \src "libresoc.v:176554.18-176554.93" + wire $not$libresoc.v:176554$10583_Y + attribute \src "libresoc.v:176556.18-176556.93" + wire $not$libresoc.v:176556$10585_Y + attribute \src "libresoc.v:176557.17-176557.89" + wire width 8 $not$libresoc.v:176557$10586_Y + attribute \src "libresoc.v:176559.18-176559.93" + wire $not$libresoc.v:176559$10588_Y + attribute \src "libresoc.v:176561.18-176561.93" + wire $not$libresoc.v:176561$10590_Y + attribute \src "libresoc.v:176563.18-176563.93" + wire $not$libresoc.v:176563$10592_Y + attribute \src "libresoc.v:176566.17-176566.91" + wire $not$libresoc.v:176566$10595_Y + attribute \src "libresoc.v:176553.18-176553.106" + wire $reduce_or$libresoc.v:176553$10582_Y + attribute \src "libresoc.v:176555.18-176555.106" + wire $reduce_or$libresoc.v:176555$10584_Y + attribute \src "libresoc.v:176558.18-176558.106" + wire $reduce_or$libresoc.v:176558$10587_Y + attribute \src "libresoc.v:176560.18-176560.106" + wire $reduce_or$libresoc.v:176560$10589_Y + attribute \src "libresoc.v:176562.18-176562.106" + wire $reduce_or$libresoc.v:176562$10591_Y + attribute \src "libresoc.v:176564.18-176564.90" + wire $reduce_or$libresoc.v:176564$10593_Y + attribute \src "libresoc.v:176565.17-176565.103" + wire $reduce_or$libresoc.v:176565$10594_Y + attribute \src "libresoc.v:176567.17-176567.105" + wire $reduce_or$libresoc.v:176567$10596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359710,149 +362207,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174920$10533 + cell $not $not$libresoc.v:176552$10581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:174920$10533_Y + connect \Y $not$libresoc.v:176552$10581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174922$10535 + cell $not $not$libresoc.v:176554$10583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:174922$10535_Y + connect \Y $not$libresoc.v:176554$10583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174924$10537 + cell $not $not$libresoc.v:176556$10585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:174924$10537_Y + connect \Y $not$libresoc.v:176556$10585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174925$10538 + cell $not $not$libresoc.v:176557$10586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:174925$10538_Y + connect \Y $not$libresoc.v:176557$10586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174927$10540 + cell $not $not$libresoc.v:176559$10588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:174927$10540_Y + connect \Y $not$libresoc.v:176559$10588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174929$10542 + cell $not $not$libresoc.v:176561$10590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:174929$10542_Y + connect \Y $not$libresoc.v:176561$10590_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174931$10544 + cell $not $not$libresoc.v:176563$10592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:174931$10544_Y + connect \Y $not$libresoc.v:176563$10592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174934$10547 + cell $not $not$libresoc.v:176566$10595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174934$10547_Y + connect \Y $not$libresoc.v:176566$10595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174921$10534 + cell $reduce_or $reduce_or$libresoc.v:176553$10582 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:174921$10534_Y + connect \Y $reduce_or$libresoc.v:176553$10582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174923$10536 + cell $reduce_or $reduce_or$libresoc.v:176555$10584 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:174923$10536_Y + connect \Y $reduce_or$libresoc.v:176555$10584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174926$10539 + cell $reduce_or $reduce_or$libresoc.v:176558$10587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:174926$10539_Y + connect \Y $reduce_or$libresoc.v:176558$10587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174928$10541 + cell $reduce_or $reduce_or$libresoc.v:176560$10589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:174928$10541_Y + connect \Y $reduce_or$libresoc.v:176560$10589_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174930$10543 + cell $reduce_or $reduce_or$libresoc.v:176562$10591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:174930$10543_Y + connect \Y $reduce_or$libresoc.v:176562$10591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174932$10545 + cell $reduce_or $reduce_or$libresoc.v:176564$10593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174932$10545_Y + connect \Y $reduce_or$libresoc.v:176564$10593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174933$10546 + cell $reduce_or $reduce_or$libresoc.v:176565$10594 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174933$10546_Y + connect \Y $reduce_or$libresoc.v:176565$10594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174935$10548 + cell $reduce_or $reduce_or$libresoc.v:176567$10596 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:174935$10548_Y - end - connect \$7 $not$libresoc.v:174920$10533_Y - connect \$12 $reduce_or$libresoc.v:174921$10534_Y - connect \$11 $not$libresoc.v:174922$10535_Y - connect \$16 $reduce_or$libresoc.v:174923$10536_Y - connect \$15 $not$libresoc.v:174924$10537_Y - connect \$1 $not$libresoc.v:174925$10538_Y - connect \$20 $reduce_or$libresoc.v:174926$10539_Y - connect \$19 $not$libresoc.v:174927$10540_Y - connect \$24 $reduce_or$libresoc.v:174928$10541_Y - connect \$23 $not$libresoc.v:174929$10542_Y - connect \$28 $reduce_or$libresoc.v:174930$10543_Y - connect \$27 $not$libresoc.v:174931$10544_Y - connect \$31 $reduce_or$libresoc.v:174932$10545_Y - connect \$4 $reduce_or$libresoc.v:174933$10546_Y - connect \$3 $not$libresoc.v:174934$10547_Y - connect \$8 $reduce_or$libresoc.v:174935$10548_Y + connect \Y $reduce_or$libresoc.v:176567$10596_Y + end + connect \$7 $not$libresoc.v:176552$10581_Y + connect \$12 $reduce_or$libresoc.v:176553$10582_Y + connect \$11 $not$libresoc.v:176554$10583_Y + connect \$16 $reduce_or$libresoc.v:176555$10584_Y + connect \$15 $not$libresoc.v:176556$10585_Y + connect \$1 $not$libresoc.v:176557$10586_Y + connect \$20 $reduce_or$libresoc.v:176558$10587_Y + connect \$19 $not$libresoc.v:176559$10588_Y + connect \$24 $reduce_or$libresoc.v:176560$10589_Y + connect \$23 $not$libresoc.v:176561$10590_Y + connect \$28 $reduce_or$libresoc.v:176562$10591_Y + connect \$27 $not$libresoc.v:176563$10592_Y + connect \$31 $reduce_or$libresoc.v:176564$10593_Y + connect \$4 $reduce_or$libresoc.v:176565$10594_Y + connect \$3 $not$libresoc.v:176566$10595_Y + connect \$8 $reduce_or$libresoc.v:176567$10596_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -359865,19 +362362,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174951.1-174981.10" +attribute \src "libresoc.v:176583.1-176613.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:174972.17-174972.89" - wire width 2 $not$libresoc.v:174972$10549_Y - attribute \src "libresoc.v:174974.17-174974.91" - wire $not$libresoc.v:174974$10551_Y - attribute \src "libresoc.v:174973.17-174973.103" - wire $reduce_or$libresoc.v:174973$10550_Y - attribute \src "libresoc.v:174975.17-174975.89" - wire $reduce_or$libresoc.v:174975$10552_Y + attribute \src "libresoc.v:176604.17-176604.89" + wire width 2 $not$libresoc.v:176604$10597_Y + attribute \src "libresoc.v:176606.17-176606.91" + wire $not$libresoc.v:176606$10599_Y + attribute \src "libresoc.v:176605.17-176605.103" + wire $reduce_or$libresoc.v:176605$10598_Y + attribute \src "libresoc.v:176607.17-176607.89" + wire $reduce_or$libresoc.v:176607$10600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359899,56 +362396,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:174972$10549 + cell $not $not$libresoc.v:176604$10597 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:174972$10549_Y + connect \Y $not$libresoc.v:176604$10597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:174974$10551 + cell $not $not$libresoc.v:176606$10599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:174974$10551_Y + connect \Y $not$libresoc.v:176606$10599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:174973$10550 + cell $reduce_or $reduce_or$libresoc.v:176605$10598 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:174973$10550_Y + connect \Y $reduce_or$libresoc.v:176605$10598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:174975$10552 + cell $reduce_or $reduce_or$libresoc.v:176607$10600 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:174975$10552_Y + connect \Y $reduce_or$libresoc.v:176607$10600_Y end - connect \$1 $not$libresoc.v:174972$10549_Y - connect \$4 $reduce_or$libresoc.v:174973$10550_Y - connect \$3 $not$libresoc.v:174974$10551_Y - connect \$7 $reduce_or$libresoc.v:174975$10552_Y + connect \$1 $not$libresoc.v:176604$10597_Y + connect \$4 $reduce_or$libresoc.v:176605$10598_Y + connect \$3 $not$libresoc.v:176606$10599_Y + connect \$7 $reduce_or$libresoc.v:176607$10600_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:174985.1-175006.10" +attribute \src "libresoc.v:176617.1-176638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:175000.17-175000.89" - wire $not$libresoc.v:175000$10553_Y - attribute \src "libresoc.v:175001.17-175001.89" - wire $reduce_or$libresoc.v:175001$10554_Y + attribute \src "libresoc.v:176632.17-176632.89" + wire $not$libresoc.v:176632$10601_Y + attribute \src "libresoc.v:176633.17-176633.89" + wire $reduce_or$libresoc.v:176633$10602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359964,45 +362461,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175000$10553 + cell $not $not$libresoc.v:176632$10601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:175000$10553_Y + connect \Y $not$libresoc.v:176632$10601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175001$10554 + cell $reduce_or $reduce_or$libresoc.v:176633$10602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175001$10554_Y + connect \Y $reduce_or$libresoc.v:176633$10602_Y end - connect \$1 $not$libresoc.v:175000$10553_Y - connect \$3 $reduce_or$libresoc.v:175001$10554_Y + connect \$1 $not$libresoc.v:176632$10601_Y + connect \$3 $reduce_or$libresoc.v:176633$10602_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:175010.1-175049.10" +attribute \src "libresoc.v:176642.1-176681.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:175037.17-175037.91" - wire $not$libresoc.v:175037$10555_Y - attribute \src "libresoc.v:175039.17-175039.89" - wire width 3 $not$libresoc.v:175039$10557_Y - attribute \src "libresoc.v:175041.17-175041.91" - wire $not$libresoc.v:175041$10559_Y - attribute \src "libresoc.v:175038.18-175038.90" - wire $reduce_or$libresoc.v:175038$10556_Y - attribute \src "libresoc.v:175040.17-175040.103" - wire $reduce_or$libresoc.v:175040$10558_Y - attribute \src "libresoc.v:175042.17-175042.105" - wire $reduce_or$libresoc.v:175042$10560_Y + attribute \src "libresoc.v:176669.17-176669.91" + wire $not$libresoc.v:176669$10603_Y + attribute \src "libresoc.v:176671.17-176671.89" + wire width 3 $not$libresoc.v:176671$10605_Y + attribute \src "libresoc.v:176673.17-176673.91" + wire $not$libresoc.v:176673$10607_Y + attribute \src "libresoc.v:176670.18-176670.90" + wire $reduce_or$libresoc.v:176670$10604_Y + attribute \src "libresoc.v:176672.17-176672.103" + wire $reduce_or$libresoc.v:176672$10606_Y + attribute \src "libresoc.v:176674.17-176674.105" + wire $reduce_or$libresoc.v:176674$10608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -360030,59 +362527,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175037$10555 + cell $not $not$libresoc.v:176669$10603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:175037$10555_Y + connect \Y $not$libresoc.v:176669$10603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175039$10557 + cell $not $not$libresoc.v:176671$10605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:175039$10557_Y + connect \Y $not$libresoc.v:176671$10605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175041$10559 + cell $not $not$libresoc.v:176673$10607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:175041$10559_Y + connect \Y $not$libresoc.v:176673$10607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175038$10556 + cell $reduce_or $reduce_or$libresoc.v:176670$10604 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175038$10556_Y + connect \Y $reduce_or$libresoc.v:176670$10604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175040$10558 + cell $reduce_or $reduce_or$libresoc.v:176672$10606 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:175040$10558_Y + connect \Y $reduce_or$libresoc.v:176672$10606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175042$10560 + cell $reduce_or $reduce_or$libresoc.v:176674$10608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:175042$10560_Y - end - connect \$7 $not$libresoc.v:175037$10555_Y - connect \$11 $reduce_or$libresoc.v:175038$10556_Y - connect \$1 $not$libresoc.v:175039$10557_Y - connect \$4 $reduce_or$libresoc.v:175040$10558_Y - connect \$3 $not$libresoc.v:175041$10559_Y - connect \$8 $reduce_or$libresoc.v:175042$10560_Y + connect \Y $reduce_or$libresoc.v:176674$10608_Y + end + connect \$7 $not$libresoc.v:176669$10603_Y + connect \$11 $reduce_or$libresoc.v:176670$10604_Y + connect \$1 $not$libresoc.v:176671$10605_Y + connect \$4 $reduce_or$libresoc.v:176672$10606_Y + connect \$3 $not$libresoc.v:176673$10607_Y + connect \$8 $reduce_or$libresoc.v:176674$10608_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -360090,15 +362587,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:175053.1-175074.10" +attribute \src "libresoc.v:176685.1-176706.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:175068.17-175068.89" - wire $not$libresoc.v:175068$10561_Y - attribute \src "libresoc.v:175069.17-175069.89" - wire $reduce_or$libresoc.v:175069$10562_Y + attribute \src "libresoc.v:176700.17-176700.89" + wire $not$libresoc.v:176700$10609_Y + attribute \src "libresoc.v:176701.17-176701.89" + wire $reduce_or$libresoc.v:176701$10610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -360114,57 +362611,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175068$10561 + cell $not $not$libresoc.v:176700$10609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:175068$10561_Y + connect \Y $not$libresoc.v:176700$10609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175069$10562 + cell $reduce_or $reduce_or$libresoc.v:176701$10610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175069$10562_Y + connect \Y $reduce_or$libresoc.v:176701$10610_Y end - connect \$1 $not$libresoc.v:175068$10561_Y - connect \$3 $reduce_or$libresoc.v:175069$10562_Y + connect \$1 $not$libresoc.v:176700$10609_Y + connect \$3 $reduce_or$libresoc.v:176701$10610_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:175078.1-175144.10" +attribute \src "libresoc.v:176710.1-176776.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:175123.17-175123.91" - wire $not$libresoc.v:175123$10563_Y - attribute \src "libresoc.v:175125.18-175125.93" - wire $not$libresoc.v:175125$10565_Y - attribute \src "libresoc.v:175127.18-175127.93" - wire $not$libresoc.v:175127$10567_Y - attribute \src "libresoc.v:175128.17-175128.89" - wire width 6 $not$libresoc.v:175128$10568_Y - attribute \src "libresoc.v:175130.18-175130.93" - wire $not$libresoc.v:175130$10570_Y - attribute \src "libresoc.v:175133.17-175133.91" - wire $not$libresoc.v:175133$10573_Y - attribute \src "libresoc.v:175124.18-175124.106" - wire $reduce_or$libresoc.v:175124$10564_Y - attribute \src "libresoc.v:175126.18-175126.106" - wire $reduce_or$libresoc.v:175126$10566_Y - attribute \src "libresoc.v:175129.18-175129.106" - wire $reduce_or$libresoc.v:175129$10569_Y - attribute \src "libresoc.v:175131.18-175131.90" - wire $reduce_or$libresoc.v:175131$10571_Y - attribute \src "libresoc.v:175132.17-175132.103" - wire $reduce_or$libresoc.v:175132$10572_Y - attribute \src "libresoc.v:175134.17-175134.105" - wire $reduce_or$libresoc.v:175134$10574_Y + attribute \src "libresoc.v:176755.17-176755.91" + wire $not$libresoc.v:176755$10611_Y + attribute \src "libresoc.v:176757.18-176757.93" + wire $not$libresoc.v:176757$10613_Y + attribute \src "libresoc.v:176759.18-176759.93" + wire $not$libresoc.v:176759$10615_Y + attribute \src "libresoc.v:176760.17-176760.89" + wire width 6 $not$libresoc.v:176760$10616_Y + attribute \src "libresoc.v:176762.18-176762.93" + wire $not$libresoc.v:176762$10618_Y + attribute \src "libresoc.v:176765.17-176765.91" + wire $not$libresoc.v:176765$10621_Y + attribute \src "libresoc.v:176756.18-176756.106" + wire $reduce_or$libresoc.v:176756$10612_Y + attribute \src "libresoc.v:176758.18-176758.106" + wire $reduce_or$libresoc.v:176758$10614_Y + attribute \src "libresoc.v:176761.18-176761.106" + wire $reduce_or$libresoc.v:176761$10617_Y + attribute \src "libresoc.v:176763.18-176763.90" + wire $reduce_or$libresoc.v:176763$10619_Y + attribute \src "libresoc.v:176764.17-176764.103" + wire $reduce_or$libresoc.v:176764$10620_Y + attribute \src "libresoc.v:176766.17-176766.105" + wire $reduce_or$libresoc.v:176766$10622_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -360210,113 +362707,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175123$10563 + cell $not $not$libresoc.v:176755$10611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:175123$10563_Y + connect \Y $not$libresoc.v:176755$10611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175125$10565 + cell $not $not$libresoc.v:176757$10613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:175125$10565_Y + connect \Y $not$libresoc.v:176757$10613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175127$10567 + cell $not $not$libresoc.v:176759$10615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:175127$10567_Y + connect \Y $not$libresoc.v:176759$10615_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:175128$10568 + cell $not $not$libresoc.v:176760$10616 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:175128$10568_Y + connect \Y $not$libresoc.v:176760$10616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175130$10570 + cell $not $not$libresoc.v:176762$10618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:175130$10570_Y + connect \Y $not$libresoc.v:176762$10618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:175133$10573 + cell $not $not$libresoc.v:176765$10621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:175133$10573_Y + connect \Y $not$libresoc.v:176765$10621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175124$10564 + cell $reduce_or $reduce_or$libresoc.v:176756$10612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:175124$10564_Y + connect \Y $reduce_or$libresoc.v:176756$10612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175126$10566 + cell $reduce_or $reduce_or$libresoc.v:176758$10614 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:175126$10566_Y + connect \Y $reduce_or$libresoc.v:176758$10614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175129$10569 + cell $reduce_or $reduce_or$libresoc.v:176761$10617 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:175129$10569_Y + connect \Y $reduce_or$libresoc.v:176761$10617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:175131$10571 + cell $reduce_or $reduce_or$libresoc.v:176763$10619 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:175131$10571_Y + connect \Y $reduce_or$libresoc.v:176763$10619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175132$10572 + cell $reduce_or $reduce_or$libresoc.v:176764$10620 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:175132$10572_Y + connect \Y $reduce_or$libresoc.v:176764$10620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:175134$10574 + cell $reduce_or $reduce_or$libresoc.v:176766$10622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:175134$10574_Y - end - connect \$7 $not$libresoc.v:175123$10563_Y - connect \$12 $reduce_or$libresoc.v:175124$10564_Y - connect \$11 $not$libresoc.v:175125$10565_Y - connect \$16 $reduce_or$libresoc.v:175126$10566_Y - connect \$15 $not$libresoc.v:175127$10567_Y - connect \$1 $not$libresoc.v:175128$10568_Y - connect \$20 $reduce_or$libresoc.v:175129$10569_Y - connect \$19 $not$libresoc.v:175130$10570_Y - connect \$23 $reduce_or$libresoc.v:175131$10571_Y - connect \$4 $reduce_or$libresoc.v:175132$10572_Y - connect \$3 $not$libresoc.v:175133$10573_Y - connect \$8 $reduce_or$libresoc.v:175134$10574_Y + connect \Y $reduce_or$libresoc.v:176766$10622_Y + end + connect \$7 $not$libresoc.v:176755$10611_Y + connect \$12 $reduce_or$libresoc.v:176756$10612_Y + connect \$11 $not$libresoc.v:176757$10613_Y + connect \$16 $reduce_or$libresoc.v:176758$10614_Y + connect \$15 $not$libresoc.v:176759$10615_Y + connect \$1 $not$libresoc.v:176760$10616_Y + connect \$20 $reduce_or$libresoc.v:176761$10617_Y + connect \$19 $not$libresoc.v:176762$10618_Y + connect \$23 $reduce_or$libresoc.v:176763$10619_Y + connect \$4 $reduce_or$libresoc.v:176764$10620_Y + connect \$3 $not$libresoc.v:176765$10621_Y + connect \$8 $reduce_or$libresoc.v:176766$10622_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -360327,239 +362824,277 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:175148.1-175619.10" +attribute \src "libresoc.v:176780.1-177335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:175149.7-175149.20" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 + attribute \src "libresoc.v:176886.3-176887.49" + wire width 4 $0\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:176781.7-176781.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $0\r0__data_o$next[3:0]$10630 - attribute \src "libresoc.v:175234.3-175235.37" + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $0\r0__data_o$next[3:0]$10708 + attribute \src "libresoc.v:176878.3-176879.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $0\r20__data_o$next[3:0]$10644 - attribute \src "libresoc.v:175232.3-175233.39" + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $0\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:176876.3-176877.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $0\reg$next[3:0]$10596 - attribute \src "libresoc.v:175230.3-175231.25" + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $0\reg$next[3:0]$10660 + attribute \src "libresoc.v:176874.3-176875.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $0\src10__data_o$next[3:0]$10587 - attribute \src "libresoc.v:175240.3-175241.43" + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $0\src10__data_o$next[3:0]$10666 + attribute \src "libresoc.v:176884.3-176885.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $0\src20__data_o$next[3:0]$10602 - attribute \src "libresoc.v:175238.3-175239.43" + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $0\src20__data_o$next[3:0]$10680 + attribute \src "libresoc.v:176882.3-176883.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $0\src30__data_o$next[3:0]$10616 - attribute \src "libresoc.v:175236.3-175237.43" + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $0\src30__data_o$next[3:0]$10694 + attribute \src "libresoc.v:176880.3-176881.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:175519.3-175548.6" - wire $0\wr_detect$10[0:0]$10638 - attribute \src "libresoc.v:175589.3-175618.6" - wire $0\wr_detect$13[0:0]$10652 - attribute \src "libresoc.v:175379.3-175408.6" - wire $0\wr_detect$4[0:0]$10610 - attribute \src "libresoc.v:175449.3-175478.6" - wire $0\wr_detect$7[0:0]$10624 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:177235.3-177264.6" + wire $0\wr_detect$10[0:0]$10702 + attribute \src "libresoc.v:177305.3-177334.6" + wire $0\wr_detect$13[0:0]$10716 + attribute \src "libresoc.v:176998.3-177027.6" + wire $0\wr_detect$16[0:0]$10654 + attribute \src "libresoc.v:177095.3-177124.6" + wire $0\wr_detect$4[0:0]$10674 + attribute \src "libresoc.v:177165.3-177194.6" + wire $0\wr_detect$7[0:0]$10688 + attribute \src "libresoc.v:176928.3-176957.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $1\r0__data_o$next[3:0]$10631 - attribute \src "libresoc.v:175174.13-175174.30" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 + attribute \src "libresoc.v:176800.13-176800.36" + wire width 4 $1\cr_pred0__data_o[3:0] + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $1\r0__data_o$next[3:0]$10709 + attribute \src "libresoc.v:176815.13-176815.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $1\r20__data_o$next[3:0]$10645 - attribute \src "libresoc.v:175181.13-175181.31" + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $1\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:176822.13-176822.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $1\reg$next[3:0]$10597 - attribute \src "libresoc.v:175187.13-175187.25" + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $1\reg$next[3:0]$10661 + attribute \src "libresoc.v:176828.13-176828.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $1\src10__data_o$next[3:0]$10588 - attribute \src "libresoc.v:175192.13-175192.33" + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $1\src10__data_o$next[3:0]$10667 + attribute \src "libresoc.v:176833.13-176833.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $1\src20__data_o$next[3:0]$10603 - attribute \src "libresoc.v:175199.13-175199.33" + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $1\src20__data_o$next[3:0]$10681 + attribute \src "libresoc.v:176840.13-176840.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $1\src30__data_o$next[3:0]$10617 - attribute \src "libresoc.v:175206.13-175206.33" + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $1\src30__data_o$next[3:0]$10695 + attribute \src "libresoc.v:176847.13-176847.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:175519.3-175548.6" - wire $1\wr_detect$10[0:0]$10639 - attribute \src "libresoc.v:175589.3-175618.6" - wire $1\wr_detect$13[0:0]$10653 - attribute \src "libresoc.v:175379.3-175408.6" - wire $1\wr_detect$4[0:0]$10611 - attribute \src "libresoc.v:175449.3-175478.6" - wire $1\wr_detect$7[0:0]$10625 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:177235.3-177264.6" + wire $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177305.3-177334.6" + wire $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:176998.3-177027.6" + wire $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:177095.3-177124.6" + wire $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177165.3-177194.6" + wire $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:176928.3-176957.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $2\r0__data_o$next[3:0]$10632 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $2\r20__data_o$next[3:0]$10646 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $2\reg$next[3:0]$10598 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $2\src10__data_o$next[3:0]$10589 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $2\src20__data_o$next[3:0]$10604 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $2\src30__data_o$next[3:0]$10618 - attribute \src "libresoc.v:175519.3-175548.6" - wire $2\wr_detect$10[0:0]$10640 - attribute \src "libresoc.v:175589.3-175618.6" - wire $2\wr_detect$13[0:0]$10654 - attribute \src "libresoc.v:175379.3-175408.6" - wire $2\wr_detect$4[0:0]$10612 - attribute \src "libresoc.v:175449.3-175478.6" - wire $2\wr_detect$7[0:0]$10626 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $2\r0__data_o$next[3:0]$10710 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $2\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $2\reg$next[3:0]$10662 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $2\src10__data_o$next[3:0]$10668 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $2\src20__data_o$next[3:0]$10682 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $2\src30__data_o$next[3:0]$10696 + attribute \src "libresoc.v:177235.3-177264.6" + wire $2\wr_detect$10[0:0]$10704 + attribute \src "libresoc.v:177305.3-177334.6" + wire $2\wr_detect$13[0:0]$10718 + attribute \src "libresoc.v:176998.3-177027.6" + wire $2\wr_detect$16[0:0]$10656 + attribute \src "libresoc.v:177095.3-177124.6" + wire $2\wr_detect$4[0:0]$10676 + attribute \src "libresoc.v:177165.3-177194.6" + wire $2\wr_detect$7[0:0]$10690 + attribute \src "libresoc.v:176928.3-176957.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $3\r0__data_o$next[3:0]$10633 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $3\r20__data_o$next[3:0]$10647 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $3\reg$next[3:0]$10599 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $3\src10__data_o$next[3:0]$10590 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $3\src20__data_o$next[3:0]$10605 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $3\src30__data_o$next[3:0]$10619 - attribute \src "libresoc.v:175519.3-175548.6" - wire $3\wr_detect$10[0:0]$10641 - attribute \src "libresoc.v:175589.3-175618.6" - wire $3\wr_detect$13[0:0]$10655 - attribute \src "libresoc.v:175379.3-175408.6" - wire $3\wr_detect$4[0:0]$10613 - attribute \src "libresoc.v:175449.3-175478.6" - wire $3\wr_detect$7[0:0]$10627 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $3\r0__data_o$next[3:0]$10711 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $3\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $3\reg$next[3:0]$10663 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $3\src10__data_o$next[3:0]$10669 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $3\src20__data_o$next[3:0]$10683 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $3\src30__data_o$next[3:0]$10697 + attribute \src "libresoc.v:177235.3-177264.6" + wire $3\wr_detect$10[0:0]$10705 + attribute \src "libresoc.v:177305.3-177334.6" + wire $3\wr_detect$13[0:0]$10719 + attribute \src "libresoc.v:176998.3-177027.6" + wire $3\wr_detect$16[0:0]$10657 + attribute \src "libresoc.v:177095.3-177124.6" + wire $3\wr_detect$4[0:0]$10677 + attribute \src "libresoc.v:177165.3-177194.6" + wire $3\wr_detect$7[0:0]$10691 + attribute \src "libresoc.v:176928.3-176957.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $4\r0__data_o$next[3:0]$10634 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $4\r20__data_o$next[3:0]$10648 - attribute \src "libresoc.v:175312.3-175338.6" - wire width 4 $4\reg$next[3:0]$10600 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $4\src10__data_o$next[3:0]$10591 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $4\src20__data_o$next[3:0]$10606 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $4\src30__data_o$next[3:0]$10620 - attribute \src "libresoc.v:175519.3-175548.6" - wire $4\wr_detect$10[0:0]$10642 - attribute \src "libresoc.v:175589.3-175618.6" - wire $4\wr_detect$13[0:0]$10656 - attribute \src "libresoc.v:175379.3-175408.6" - wire $4\wr_detect$4[0:0]$10614 - attribute \src "libresoc.v:175449.3-175478.6" - wire $4\wr_detect$7[0:0]$10628 - attribute \src "libresoc.v:175282.3-175311.6" + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $4\r0__data_o$next[3:0]$10712 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $4\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:177028.3-177054.6" + wire width 4 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $4\src10__data_o$next[3:0]$10670 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $4\src20__data_o$next[3:0]$10684 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $4\src30__data_o$next[3:0]$10698 + attribute \src "libresoc.v:177235.3-177264.6" + wire $4\wr_detect$10[0:0]$10706 + attribute \src "libresoc.v:177305.3-177334.6" + wire $4\wr_detect$13[0:0]$10720 + attribute \src "libresoc.v:176998.3-177027.6" + wire $4\wr_detect$16[0:0]$10658 + attribute \src "libresoc.v:177095.3-177124.6" + wire $4\wr_detect$4[0:0]$10678 + attribute \src "libresoc.v:177165.3-177194.6" + wire $4\wr_detect$7[0:0]$10692 + attribute \src "libresoc.v:176928.3-176957.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $5\r0__data_o$next[3:0]$10635 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $5\r20__data_o$next[3:0]$10649 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $5\src10__data_o$next[3:0]$10592 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $5\src20__data_o$next[3:0]$10607 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $5\src30__data_o$next[3:0]$10621 - attribute \src "libresoc.v:175479.3-175518.6" - wire width 4 $6\r0__data_o$next[3:0]$10636 - attribute \src "libresoc.v:175549.3-175588.6" - wire width 4 $6\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:175242.3-175281.6" - wire width 4 $6\src10__data_o$next[3:0]$10593 - attribute \src "libresoc.v:175339.3-175378.6" - wire width 4 $6\src20__data_o$next[3:0]$10608 - attribute \src "libresoc.v:175409.3-175448.6" - wire width 4 $6\src30__data_o$next[3:0]$10622 - attribute \src "libresoc.v:175225.17-175225.104" - wire $not$libresoc.v:175225$10575_Y - attribute \src "libresoc.v:175226.18-175226.105" - wire $not$libresoc.v:175226$10576_Y - attribute \src "libresoc.v:175227.17-175227.100" - wire $not$libresoc.v:175227$10577_Y - attribute \src "libresoc.v:175228.17-175228.103" - wire $not$libresoc.v:175228$10578_Y - attribute \src "libresoc.v:175229.17-175229.103" - wire $not$libresoc.v:175229$10579_Y + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $5\r0__data_o$next[3:0]$10713 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $5\r20__data_o$next[3:0]$10651 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $5\src10__data_o$next[3:0]$10671 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $5\src20__data_o$next[3:0]$10685 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $5\src30__data_o$next[3:0]$10699 + attribute \src "libresoc.v:176888.3-176927.6" + wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:177265.3-177304.6" + wire width 4 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:176958.3-176997.6" + wire width 4 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:177055.3-177094.6" + wire width 4 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177125.3-177164.6" + wire width 4 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177195.3-177234.6" + wire width 4 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:176868.17-176868.104" + wire $not$libresoc.v:176868$10623_Y + attribute \src "libresoc.v:176869.18-176869.105" + wire $not$libresoc.v:176869$10624_Y + attribute \src "libresoc.v:176870.18-176870.105" + wire $not$libresoc.v:176870$10625_Y + attribute \src "libresoc.v:176871.17-176871.100" + wire $not$libresoc.v:176871$10626_Y + attribute \src "libresoc.v:176872.17-176872.103" + wire $not$libresoc.v:176872$10627_Y + attribute \src "libresoc.v:176873.17-176873.103" + wire $not$libresoc.v:176873$10628_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest10__data_i + wire width 4 output 3 \cr_pred0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest10__wen + wire width 4 \cr_pred0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest20__data_i + wire input 2 \cr_pred0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest20__wen - attribute \src "libresoc.v:175149.7-175149.15" + wire width 4 input 11 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest20__wen + attribute \src "libresoc.v:176781.7-176781.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r0__data_o + wire width 4 output 14 \r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r0__ren + wire input 15 \r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r20__data_o + wire width 4 output 16 \r20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r20__ren + wire input 17 \r20__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src10__data_o + wire width 4 output 5 \src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src10__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src10__ren + wire input 4 \src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src20__data_o + wire width 4 output 7 \src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src20__ren + wire input 6 \src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src30__data_o + wire width 4 output 9 \src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src30__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src30__ren + wire input 8 \src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w0__data_i + wire width 4 input 18 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w0__wen + wire input 19 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -360567,232 +363102,257 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175225$10575 + cell $not $not$libresoc.v:176868$10623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:175225$10575_Y + connect \Y $not$libresoc.v:176868$10623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175226$10576 + cell $not $not$libresoc.v:176869$10624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:175226$10576_Y + connect \Y $not$libresoc.v:176869$10624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175227$10577 + cell $not $not$libresoc.v:176870$10625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:176870$10625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:176871$10626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175227$10577_Y + connect \Y $not$libresoc.v:176871$10626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175228$10578 + cell $not $not$libresoc.v:176872$10627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175228$10578_Y + connect \Y $not$libresoc.v:176872$10627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175229$10579 + cell $not $not$libresoc.v:176873$10628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175229$10579_Y + connect \Y $not$libresoc.v:176873$10628_Y end - attribute \src "libresoc.v:175149.7-175149.20" - process $proc$libresoc.v:175149$10657 + attribute \src "libresoc.v:176781.7-176781.20" + process $proc$libresoc.v:176781$10721 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175174.13-175174.30" - process $proc$libresoc.v:175174$10658 + attribute \src "libresoc.v:176800.13-176800.36" + process $proc$libresoc.v:176800$10722 + assign { } { } + assign $1\cr_pred0__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176815.13-176815.30" + process $proc$libresoc.v:176815$10723 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:175181.13-175181.31" - process $proc$libresoc.v:175181$10659 + attribute \src "libresoc.v:176822.13-176822.31" + process $proc$libresoc.v:176822$10724 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:175187.13-175187.25" - process $proc$libresoc.v:175187$10660 + attribute \src "libresoc.v:176828.13-176828.25" + process $proc$libresoc.v:176828$10725 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:175192.13-175192.33" - process $proc$libresoc.v:175192$10661 + attribute \src "libresoc.v:176833.13-176833.33" + process $proc$libresoc.v:176833$10726 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:175199.13-175199.33" - process $proc$libresoc.v:175199$10662 + attribute \src "libresoc.v:176840.13-176840.33" + process $proc$libresoc.v:176840$10727 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:175206.13-175206.33" - process $proc$libresoc.v:175206$10663 + attribute \src "libresoc.v:176847.13-176847.33" + process $proc$libresoc.v:176847$10728 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:175230.3-175231.25" - process $proc$libresoc.v:175230$10580 + attribute \src "libresoc.v:176874.3-176875.25" + process $proc$libresoc.v:176874$10629 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:175232.3-175233.39" - process $proc$libresoc.v:175232$10581 + attribute \src "libresoc.v:176876.3-176877.39" + process $proc$libresoc.v:176876$10630 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:175234.3-175235.37" - process $proc$libresoc.v:175234$10582 + attribute \src "libresoc.v:176878.3-176879.37" + process $proc$libresoc.v:176878$10631 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:175236.3-175237.43" - process $proc$libresoc.v:175236$10583 + attribute \src "libresoc.v:176880.3-176881.43" + process $proc$libresoc.v:176880$10632 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:175238.3-175239.43" - process $proc$libresoc.v:175238$10584 + attribute \src "libresoc.v:176882.3-176883.43" + process $proc$libresoc.v:176882$10633 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:175240.3-175241.43" - process $proc$libresoc.v:175240$10585 + attribute \src "libresoc.v:176884.3-176885.43" + process $proc$libresoc.v:176884$10634 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:175242.3-175281.6" - process $proc$libresoc.v:175242$10586 + attribute \src "libresoc.v:176886.3-176887.49" + process $proc$libresoc.v:176886$10635 + assign { } { } + assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next + sync posedge \coresync_clk + update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] + end + attribute \src "libresoc.v:176888.3-176927.6" + process $proc$libresoc.v:176888$10636 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 - attribute \src "libresoc.v:175243.5-175243.29" + assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 + attribute \src "libresoc.v:176889.5-176889.29" switch \initial - attribute \src "libresoc.v:175243.9-175243.17" + attribute \src "libresoc.v:176889.9-176889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \cr_pred0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 + assign $1\cr_pred0__data_o$next[3:0]$10638 $5\cr_pred0__data_o$next[3:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i + assign $2\cr_pred0__data_o$next[3:0]$10639 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10589 4'0000 + assign $2\cr_pred0__data_o$next[3:0]$10639 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i + assign $3\cr_pred0__data_o$next[3:0]$10640 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 + assign $3\cr_pred0__data_o$next[3:0]$10640 $2\cr_pred0__data_o$next[3:0]$10639 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10591 \w0__data_i + assign $4\cr_pred0__data_o$next[3:0]$10641 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 + assign $4\cr_pred0__data_o$next[3:0]$10641 $3\cr_pred0__data_o$next[3:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10592 \reg + assign $5\cr_pred0__data_o$next[3:0]$10642 \reg case - assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 + assign $5\cr_pred0__data_o$next[3:0]$10642 $4\cr_pred0__data_o$next[3:0]$10641 end case - assign $1\src10__data_o$next[3:0]$10588 4'0000 + assign $1\cr_pred0__data_o$next[3:0]$10638 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10593 4'0000 + assign $6\cr_pred0__data_o$next[3:0]$10643 4'0000 case - assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 + assign $6\cr_pred0__data_o$next[3:0]$10643 $1\cr_pred0__data_o$next[3:0]$10638 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 + update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 end - attribute \src "libresoc.v:175282.3-175311.6" - process $proc$libresoc.v:175282$10594 + attribute \src "libresoc.v:176928.3-176957.6" + process $proc$libresoc.v:176928$10644 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175283.5-175283.29" + attribute \src "libresoc.v:176929.5-176929.29" switch \initial - attribute \src "libresoc.v:175283.9-175283.17" + attribute \src "libresoc.v:176929.9-176929.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + switch \cr_pred0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -360833,724 +363393,850 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175312.3-175338.6" - process $proc$libresoc.v:175312$10595 - assign { } { } - assign { } { } + attribute \src "libresoc.v:176958.3-176997.6" + process $proc$libresoc.v:176958$10645 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 - attribute \src "libresoc.v:175313.5-175313.29" + assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 + attribute \src "libresoc.v:176959.5-176959.29" switch \initial - attribute \src "libresoc.v:175313.9-175313.17" + attribute \src "libresoc.v:176959.9-176959.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10597 \dest10__data_i - case - assign $1\reg$next[3:0]$10597 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$10598 \dest20__data_i - case - assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$10599 \w0__data_i + assign { } { } + assign $1\r20__data_o$next[3:0]$10647 $5\r20__data_o$next[3:0]$10651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10648 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10649 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10649 $2\r20__data_o$next[3:0]$10648 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10650 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10650 $3\r20__data_o$next[3:0]$10649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10651 \reg + case + assign $5\r20__data_o$next[3:0]$10651 $4\r20__data_o$next[3:0]$10650 + end case - assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 + assign $1\r20__data_o$next[3:0]$10647 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10600 4'0000 + assign $6\r20__data_o$next[3:0]$10652 4'0000 case - assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 + assign $6\r20__data_o$next[3:0]$10652 $1\r20__data_o$next[3:0]$10647 end sync always - update \reg$next $0\reg$next[3:0]$10596 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 end - attribute \src "libresoc.v:175339.3-175378.6" - process $proc$libresoc.v:175339$10601 - assign { } { } + attribute \src "libresoc.v:176998.3-177027.6" + process $proc$libresoc.v:176998$10653 assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 - attribute \src "libresoc.v:175340.5-175340.29" + assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 + attribute \src "libresoc.v:176999.5-176999.29" switch \initial - attribute \src "libresoc.v:175340.9-175340.17" + attribute \src "libresoc.v:176999.9-176999.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 + assign $1\wr_detect$16[0:0]$10655 $4\wr_detect$16[0:0]$10658 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i + assign $2\wr_detect$16[0:0]$10656 1'1 case - assign $2\src20__data_o$next[3:0]$10604 4'0000 + assign $2\wr_detect$16[0:0]$10656 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i + assign $3\wr_detect$16[0:0]$10657 1'1 case - assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 + assign $3\wr_detect$16[0:0]$10657 $2\wr_detect$16[0:0]$10656 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10606 \w0__data_i + assign $4\wr_detect$16[0:0]$10658 1'1 case - assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 + assign $4\wr_detect$16[0:0]$10658 $3\wr_detect$16[0:0]$10657 + end + case + assign $1\wr_detect$16[0:0]$10655 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10654 + end + attribute \src "libresoc.v:177028.3-177054.6" + process $proc$libresoc.v:177028$10659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 + attribute \src "libresoc.v:177029.5-177029.29" + switch \initial + attribute \src "libresoc.v:177029.9-177029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10661 \dest10__data_i + case + assign $1\reg$next[3:0]$10661 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10662 \dest20__data_i + case + assign $2\reg$next[3:0]$10662 $1\reg$next[3:0]$10661 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10663 \w0__data_i + case + assign $3\reg$next[3:0]$10663 $2\reg$next[3:0]$10662 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10664 4'0000 + case + assign $4\reg$next[3:0]$10664 $3\reg$next[3:0]$10663 + end + sync always + update \reg$next $0\reg$next[3:0]$10660 + end + attribute \src "libresoc.v:177055.3-177094.6" + process $proc$libresoc.v:177055$10665 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 + attribute \src "libresoc.v:177056.5-177056.29" + switch \initial + attribute \src "libresoc.v:177056.9-177056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10667 $5\src10__data_o$next[3:0]$10671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10668 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10668 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10669 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10669 $2\src10__data_o$next[3:0]$10668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10670 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10670 $3\src10__data_o$next[3:0]$10669 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10607 \reg + assign $5\src10__data_o$next[3:0]$10671 \reg case - assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 + assign $5\src10__data_o$next[3:0]$10671 $4\src10__data_o$next[3:0]$10670 end case - assign $1\src20__data_o$next[3:0]$10603 4'0000 + assign $1\src10__data_o$next[3:0]$10667 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10608 4'0000 + assign $6\src10__data_o$next[3:0]$10672 4'0000 case - assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 + assign $6\src10__data_o$next[3:0]$10672 $1\src10__data_o$next[3:0]$10667 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 end - attribute \src "libresoc.v:175379.3-175408.6" - process $proc$libresoc.v:175379$10609 + attribute \src "libresoc.v:177095.3-177124.6" + process $proc$libresoc.v:177095$10673 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 - attribute \src "libresoc.v:175380.5-175380.29" + assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 + attribute \src "libresoc.v:177096.5-177096.29" switch \initial - attribute \src "libresoc.v:175380.9-175380.17" + attribute \src "libresoc.v:177096.9-177096.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 + assign $1\wr_detect$4[0:0]$10675 $4\wr_detect$4[0:0]$10678 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10612 1'1 + assign $2\wr_detect$4[0:0]$10676 1'1 case - assign $2\wr_detect$4[0:0]$10612 1'0 + assign $2\wr_detect$4[0:0]$10676 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10613 1'1 + assign $3\wr_detect$4[0:0]$10677 1'1 case - assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 + assign $3\wr_detect$4[0:0]$10677 $2\wr_detect$4[0:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10614 1'1 + assign $4\wr_detect$4[0:0]$10678 1'1 case - assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 + assign $4\wr_detect$4[0:0]$10678 $3\wr_detect$4[0:0]$10677 end case - assign $1\wr_detect$4[0:0]$10611 1'0 + assign $1\wr_detect$4[0:0]$10675 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10610 + update \wr_detect$4 $0\wr_detect$4[0:0]$10674 end - attribute \src "libresoc.v:175409.3-175448.6" - process $proc$libresoc.v:175409$10615 + attribute \src "libresoc.v:177125.3-177164.6" + process $proc$libresoc.v:177125$10679 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 - attribute \src "libresoc.v:175410.5-175410.29" + assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:177126.5-177126.29" switch \initial - attribute \src "libresoc.v:175410.9-175410.17" + attribute \src "libresoc.v:177126.9-177126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 + assign $1\src20__data_o$next[3:0]$10681 $5\src20__data_o$next[3:0]$10685 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10682 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10618 4'0000 + assign $2\src20__data_o$next[3:0]$10682 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10683 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 + assign $3\src20__data_o$next[3:0]$10683 $2\src20__data_o$next[3:0]$10682 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10620 \w0__data_i + assign $4\src20__data_o$next[3:0]$10684 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 + assign $4\src20__data_o$next[3:0]$10684 $3\src20__data_o$next[3:0]$10683 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10621 \reg + assign $5\src20__data_o$next[3:0]$10685 \reg case - assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 + assign $5\src20__data_o$next[3:0]$10685 $4\src20__data_o$next[3:0]$10684 end case - assign $1\src30__data_o$next[3:0]$10617 4'0000 + assign $1\src20__data_o$next[3:0]$10681 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10622 4'0000 + assign $6\src20__data_o$next[3:0]$10686 4'0000 case - assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 + assign $6\src20__data_o$next[3:0]$10686 $1\src20__data_o$next[3:0]$10681 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 end - attribute \src "libresoc.v:175449.3-175478.6" - process $proc$libresoc.v:175449$10623 + attribute \src "libresoc.v:177165.3-177194.6" + process $proc$libresoc.v:177165$10687 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 - attribute \src "libresoc.v:175450.5-175450.29" + assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 + attribute \src "libresoc.v:177166.5-177166.29" switch \initial - attribute \src "libresoc.v:175450.9-175450.17" + attribute \src "libresoc.v:177166.9-177166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 + assign $1\wr_detect$7[0:0]$10689 $4\wr_detect$7[0:0]$10692 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10626 1'1 + assign $2\wr_detect$7[0:0]$10690 1'1 case - assign $2\wr_detect$7[0:0]$10626 1'0 + assign $2\wr_detect$7[0:0]$10690 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10627 1'1 + assign $3\wr_detect$7[0:0]$10691 1'1 case - assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 + assign $3\wr_detect$7[0:0]$10691 $2\wr_detect$7[0:0]$10690 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10628 1'1 + assign $4\wr_detect$7[0:0]$10692 1'1 case - assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 + assign $4\wr_detect$7[0:0]$10692 $3\wr_detect$7[0:0]$10691 end case - assign $1\wr_detect$7[0:0]$10625 1'0 + assign $1\wr_detect$7[0:0]$10689 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10624 + update \wr_detect$7 $0\wr_detect$7[0:0]$10688 end - attribute \src "libresoc.v:175479.3-175518.6" - process $proc$libresoc.v:175479$10629 + attribute \src "libresoc.v:177195.3-177234.6" + process $proc$libresoc.v:177195$10693 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 - attribute \src "libresoc.v:175480.5-175480.29" + assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 + attribute \src "libresoc.v:177196.5-177196.29" switch \initial - attribute \src "libresoc.v:175480.9-175480.17" + attribute \src "libresoc.v:177196.9-177196.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 + assign $1\src30__data_o$next[3:0]$10695 $5\src30__data_o$next[3:0]$10699 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10696 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10632 4'0000 + assign $2\src30__data_o$next[3:0]$10696 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10697 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 + assign $3\src30__data_o$next[3:0]$10697 $2\src30__data_o$next[3:0]$10696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10634 \w0__data_i + assign $4\src30__data_o$next[3:0]$10698 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 + assign $4\src30__data_o$next[3:0]$10698 $3\src30__data_o$next[3:0]$10697 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10635 \reg + assign $5\src30__data_o$next[3:0]$10699 \reg case - assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 + assign $5\src30__data_o$next[3:0]$10699 $4\src30__data_o$next[3:0]$10698 end case - assign $1\r0__data_o$next[3:0]$10631 4'0000 + assign $1\src30__data_o$next[3:0]$10695 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10636 4'0000 + assign $6\src30__data_o$next[3:0]$10700 4'0000 case - assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 + assign $6\src30__data_o$next[3:0]$10700 $1\src30__data_o$next[3:0]$10695 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 end - attribute \src "libresoc.v:175519.3-175548.6" - process $proc$libresoc.v:175519$10637 + attribute \src "libresoc.v:177235.3-177264.6" + process $proc$libresoc.v:177235$10701 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 - attribute \src "libresoc.v:175520.5-175520.29" + assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 + attribute \src "libresoc.v:177236.5-177236.29" switch \initial - attribute \src "libresoc.v:175520.9-175520.17" + attribute \src "libresoc.v:177236.9-177236.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 + assign $1\wr_detect$10[0:0]$10703 $4\wr_detect$10[0:0]$10706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10640 1'1 + assign $2\wr_detect$10[0:0]$10704 1'1 case - assign $2\wr_detect$10[0:0]$10640 1'0 + assign $2\wr_detect$10[0:0]$10704 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10641 1'1 + assign $3\wr_detect$10[0:0]$10705 1'1 case - assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 + assign $3\wr_detect$10[0:0]$10705 $2\wr_detect$10[0:0]$10704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10642 1'1 + assign $4\wr_detect$10[0:0]$10706 1'1 case - assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 + assign $4\wr_detect$10[0:0]$10706 $3\wr_detect$10[0:0]$10705 end case - assign $1\wr_detect$10[0:0]$10639 1'0 + assign $1\wr_detect$10[0:0]$10703 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10638 + update \wr_detect$10 $0\wr_detect$10[0:0]$10702 end - attribute \src "libresoc.v:175549.3-175588.6" - process $proc$libresoc.v:175549$10643 + attribute \src "libresoc.v:177265.3-177304.6" + process $proc$libresoc.v:177265$10707 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:175550.5-175550.29" + assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 + attribute \src "libresoc.v:177266.5-177266.29" switch \initial - attribute \src "libresoc.v:175550.9-175550.17" + attribute \src "libresoc.v:177266.9-177266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 + assign $1\r0__data_o$next[3:0]$10709 $5\r0__data_o$next[3:0]$10713 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10710 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10646 4'0000 + assign $2\r0__data_o$next[3:0]$10710 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10711 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 + assign $3\r0__data_o$next[3:0]$10711 $2\r0__data_o$next[3:0]$10710 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10648 \w0__data_i + assign $4\r0__data_o$next[3:0]$10712 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 + assign $4\r0__data_o$next[3:0]$10712 $3\r0__data_o$next[3:0]$10711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10649 \reg + assign $5\r0__data_o$next[3:0]$10713 \reg case - assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 + assign $5\r0__data_o$next[3:0]$10713 $4\r0__data_o$next[3:0]$10712 end case - assign $1\r20__data_o$next[3:0]$10645 4'0000 + assign $1\r0__data_o$next[3:0]$10709 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10650 4'0000 + assign $6\r0__data_o$next[3:0]$10714 4'0000 case - assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 + assign $6\r0__data_o$next[3:0]$10714 $1\r0__data_o$next[3:0]$10709 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 end - attribute \src "libresoc.v:175589.3-175618.6" - process $proc$libresoc.v:175589$10651 + attribute \src "libresoc.v:177305.3-177334.6" + process $proc$libresoc.v:177305$10715 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 - attribute \src "libresoc.v:175590.5-175590.29" + assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 + attribute \src "libresoc.v:177306.5-177306.29" switch \initial - attribute \src "libresoc.v:175590.9-175590.17" + attribute \src "libresoc.v:177306.9-177306.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 + assign $1\wr_detect$13[0:0]$10717 $4\wr_detect$13[0:0]$10720 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10654 1'1 + assign $2\wr_detect$13[0:0]$10718 1'1 case - assign $2\wr_detect$13[0:0]$10654 1'0 + assign $2\wr_detect$13[0:0]$10718 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10655 1'1 + assign $3\wr_detect$13[0:0]$10719 1'1 case - assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 + assign $3\wr_detect$13[0:0]$10719 $2\wr_detect$13[0:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10656 1'1 + assign $4\wr_detect$13[0:0]$10720 1'1 case - assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 + assign $4\wr_detect$13[0:0]$10720 $3\wr_detect$13[0:0]$10719 end case - assign $1\wr_detect$13[0:0]$10653 1'0 + assign $1\wr_detect$13[0:0]$10717 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10652 + update \wr_detect$13 $0\wr_detect$13[0:0]$10716 end - connect \$9 $not$libresoc.v:175225$10575_Y - connect \$12 $not$libresoc.v:175226$10576_Y - connect \$1 $not$libresoc.v:175227$10577_Y - connect \$3 $not$libresoc.v:175228$10578_Y - connect \$6 $not$libresoc.v:175229$10579_Y + connect \$9 $not$libresoc.v:176868$10623_Y + connect \$12 $not$libresoc.v:176869$10624_Y + connect \$15 $not$libresoc.v:176870$10625_Y + connect \$1 $not$libresoc.v:176871$10626_Y + connect \$3 $not$libresoc.v:176872$10627_Y + connect \$6 $not$libresoc.v:176873$10628_Y end -attribute \src "libresoc.v:175623.1-176068.10" +attribute \src "libresoc.v:177339.1-177784.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:175624.7-175624.20" + attribute \src "libresoc.v:177340.7-177340.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $0\r0__data_o$next[1:0]$10716 - attribute \src "libresoc.v:175699.3-175700.37" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $0\r0__data_o$next[1:0]$10781 + attribute \src "libresoc.v:177415.3-177416.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $0\reg$next[1:0]$10732 - attribute \src "libresoc.v:175697.3-175698.25" + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $0\reg$next[1:0]$10797 + attribute \src "libresoc.v:177413.3-177414.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $0\src10__data_o$next[1:0]$10674 - attribute \src "libresoc.v:175705.3-175706.43" + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $0\src10__data_o$next[1:0]$10739 + attribute \src "libresoc.v:177421.3-177422.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $0\src20__data_o$next[1:0]$10684 - attribute \src "libresoc.v:175703.3-175704.43" + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $0\src20__data_o$next[1:0]$10749 + attribute \src "libresoc.v:177419.3-177420.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $0\src30__data_o$next[1:0]$10700 - attribute \src "libresoc.v:175701.3-175702.43" + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $0\src30__data_o$next[1:0]$10765 + attribute \src "libresoc.v:177417.3-177418.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:175999.3-176034.6" - wire $0\wr_detect$10[0:0]$10725 - attribute \src "libresoc.v:175835.3-175870.6" - wire $0\wr_detect$4[0:0]$10693 - attribute \src "libresoc.v:175917.3-175952.6" - wire $0\wr_detect$7[0:0]$10709 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177715.3-177750.6" + wire $0\wr_detect$10[0:0]$10790 + attribute \src "libresoc.v:177551.3-177586.6" + wire $0\wr_detect$4[0:0]$10758 + attribute \src "libresoc.v:177633.3-177668.6" + wire $0\wr_detect$7[0:0]$10774 + attribute \src "libresoc.v:177469.3-177504.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $1\r0__data_o$next[1:0]$10717 - attribute \src "libresoc.v:175651.13-175651.30" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $1\r0__data_o$next[1:0]$10782 + attribute \src "libresoc.v:177367.13-177367.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $1\reg$next[1:0]$10733 - attribute \src "libresoc.v:175657.13-175657.25" + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $1\reg$next[1:0]$10798 + attribute \src "libresoc.v:177373.13-177373.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $1\src10__data_o$next[1:0]$10675 - attribute \src "libresoc.v:175662.13-175662.33" + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $1\src10__data_o$next[1:0]$10740 + attribute \src "libresoc.v:177378.13-177378.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $1\src20__data_o$next[1:0]$10685 - attribute \src "libresoc.v:175669.13-175669.33" + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $1\src20__data_o$next[1:0]$10750 + attribute \src "libresoc.v:177385.13-177385.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $1\src30__data_o$next[1:0]$10701 - attribute \src "libresoc.v:175676.13-175676.33" + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $1\src30__data_o$next[1:0]$10766 + attribute \src "libresoc.v:177392.13-177392.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:175999.3-176034.6" - wire $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:175835.3-175870.6" - wire $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:175917.3-175952.6" - wire $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177715.3-177750.6" + wire $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177551.3-177586.6" + wire $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177633.3-177668.6" + wire $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177469.3-177504.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $2\r0__data_o$next[1:0]$10718 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $2\reg$next[1:0]$10734 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $2\src10__data_o$next[1:0]$10676 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $2\src20__data_o$next[1:0]$10686 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $2\src30__data_o$next[1:0]$10702 - attribute \src "libresoc.v:175999.3-176034.6" - wire $2\wr_detect$10[0:0]$10727 - attribute \src "libresoc.v:175835.3-175870.6" - wire $2\wr_detect$4[0:0]$10695 - attribute \src "libresoc.v:175917.3-175952.6" - wire $2\wr_detect$7[0:0]$10711 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $2\r0__data_o$next[1:0]$10783 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $2\reg$next[1:0]$10799 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $2\src10__data_o$next[1:0]$10741 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $2\src20__data_o$next[1:0]$10751 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $2\src30__data_o$next[1:0]$10767 + attribute \src "libresoc.v:177715.3-177750.6" + wire $2\wr_detect$10[0:0]$10792 + attribute \src "libresoc.v:177551.3-177586.6" + wire $2\wr_detect$4[0:0]$10760 + attribute \src "libresoc.v:177633.3-177668.6" + wire $2\wr_detect$7[0:0]$10776 + attribute \src "libresoc.v:177469.3-177504.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $3\r0__data_o$next[1:0]$10719 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $3\reg$next[1:0]$10735 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $3\src10__data_o$next[1:0]$10677 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $3\src20__data_o$next[1:0]$10687 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $3\src30__data_o$next[1:0]$10703 - attribute \src "libresoc.v:175999.3-176034.6" - wire $3\wr_detect$10[0:0]$10728 - attribute \src "libresoc.v:175835.3-175870.6" - wire $3\wr_detect$4[0:0]$10696 - attribute \src "libresoc.v:175917.3-175952.6" - wire $3\wr_detect$7[0:0]$10712 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $3\r0__data_o$next[1:0]$10784 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $3\reg$next[1:0]$10800 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $3\src10__data_o$next[1:0]$10742 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $3\src20__data_o$next[1:0]$10752 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $3\src30__data_o$next[1:0]$10768 + attribute \src "libresoc.v:177715.3-177750.6" + wire $3\wr_detect$10[0:0]$10793 + attribute \src "libresoc.v:177551.3-177586.6" + wire $3\wr_detect$4[0:0]$10761 + attribute \src "libresoc.v:177633.3-177668.6" + wire $3\wr_detect$7[0:0]$10777 + attribute \src "libresoc.v:177469.3-177504.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $4\r0__data_o$next[1:0]$10720 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $4\reg$next[1:0]$10736 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $4\src10__data_o$next[1:0]$10678 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $4\src20__data_o$next[1:0]$10688 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $4\src30__data_o$next[1:0]$10704 - attribute \src "libresoc.v:175999.3-176034.6" - wire $4\wr_detect$10[0:0]$10729 - attribute \src "libresoc.v:175835.3-175870.6" - wire $4\wr_detect$4[0:0]$10697 - attribute \src "libresoc.v:175917.3-175952.6" - wire $4\wr_detect$7[0:0]$10713 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $4\r0__data_o$next[1:0]$10785 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $4\reg$next[1:0]$10801 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $4\src10__data_o$next[1:0]$10743 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $4\src20__data_o$next[1:0]$10753 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $4\src30__data_o$next[1:0]$10769 + attribute \src "libresoc.v:177715.3-177750.6" + wire $4\wr_detect$10[0:0]$10794 + attribute \src "libresoc.v:177551.3-177586.6" + wire $4\wr_detect$4[0:0]$10762 + attribute \src "libresoc.v:177633.3-177668.6" + wire $4\wr_detect$7[0:0]$10778 + attribute \src "libresoc.v:177469.3-177504.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $5\r0__data_o$next[1:0]$10721 - attribute \src "libresoc.v:176035.3-176067.6" - wire width 2 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $5\src10__data_o$next[1:0]$10679 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $5\src20__data_o$next[1:0]$10689 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $5\src30__data_o$next[1:0]$10705 - attribute \src "libresoc.v:175999.3-176034.6" - wire $5\wr_detect$10[0:0]$10730 - attribute \src "libresoc.v:175835.3-175870.6" - wire $5\wr_detect$4[0:0]$10698 - attribute \src "libresoc.v:175917.3-175952.6" - wire $5\wr_detect$7[0:0]$10714 - attribute \src "libresoc.v:175753.3-175788.6" + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $5\r0__data_o$next[1:0]$10786 + attribute \src "libresoc.v:177751.3-177783.6" + wire width 2 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $5\src10__data_o$next[1:0]$10744 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $5\src20__data_o$next[1:0]$10754 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $5\src30__data_o$next[1:0]$10770 + attribute \src "libresoc.v:177715.3-177750.6" + wire $5\wr_detect$10[0:0]$10795 + attribute \src "libresoc.v:177551.3-177586.6" + wire $5\wr_detect$4[0:0]$10763 + attribute \src "libresoc.v:177633.3-177668.6" + wire $5\wr_detect$7[0:0]$10779 + attribute \src "libresoc.v:177469.3-177504.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $6\r0__data_o$next[1:0]$10722 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $6\src10__data_o$next[1:0]$10680 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $6\src20__data_o$next[1:0]$10690 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $6\src30__data_o$next[1:0]$10706 - attribute \src "libresoc.v:175953.3-175998.6" - wire width 2 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:175707.3-175752.6" - wire width 2 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:175789.3-175834.6" - wire width 2 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:175871.3-175916.6" - wire width 2 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:175693.17-175693.104" - wire $not$libresoc.v:175693$10664_Y - attribute \src "libresoc.v:175694.17-175694.100" - wire $not$libresoc.v:175694$10665_Y - attribute \src "libresoc.v:175695.17-175695.103" - wire $not$libresoc.v:175695$10666_Y - attribute \src "libresoc.v:175696.17-175696.103" - wire $not$libresoc.v:175696$10667_Y + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $6\r0__data_o$next[1:0]$10787 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $6\src10__data_o$next[1:0]$10745 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $6\src20__data_o$next[1:0]$10755 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $6\src30__data_o$next[1:0]$10771 + attribute \src "libresoc.v:177669.3-177714.6" + wire width 2 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177423.3-177468.6" + wire width 2 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177505.3-177550.6" + wire width 2 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177587.3-177632.6" + wire width 2 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177409.17-177409.104" + wire $not$libresoc.v:177409$10729_Y + attribute \src "libresoc.v:177410.17-177410.100" + wire $not$libresoc.v:177410$10730_Y + attribute \src "libresoc.v:177411.17-177411.103" + wire $not$libresoc.v:177411$10731_Y + attribute \src "libresoc.v:177412.17-177412.103" + wire $not$libresoc.v:177412$10732_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -361559,9 +364245,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -361575,7 +364261,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:175624.7-175624.15" + attribute \src "libresoc.v:177340.7-177340.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -361618,129 +364304,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175693$10664 + cell $not $not$libresoc.v:177409$10729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:175693$10664_Y + connect \Y $not$libresoc.v:177409$10729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175694$10665 + cell $not $not$libresoc.v:177410$10730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:175694$10665_Y + connect \Y $not$libresoc.v:177410$10730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175695$10666 + cell $not $not$libresoc.v:177411$10731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:175695$10666_Y + connect \Y $not$libresoc.v:177411$10731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:175696$10667 + cell $not $not$libresoc.v:177412$10732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:175696$10667_Y + connect \Y $not$libresoc.v:177412$10732_Y end - attribute \src "libresoc.v:175624.7-175624.20" - process $proc$libresoc.v:175624$10738 + attribute \src "libresoc.v:177340.7-177340.20" + process $proc$libresoc.v:177340$10803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175651.13-175651.30" - process $proc$libresoc.v:175651$10739 + attribute \src "libresoc.v:177367.13-177367.30" + process $proc$libresoc.v:177367$10804 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:175657.13-175657.25" - process $proc$libresoc.v:175657$10740 + attribute \src "libresoc.v:177373.13-177373.25" + process $proc$libresoc.v:177373$10805 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:175662.13-175662.33" - process $proc$libresoc.v:175662$10741 + attribute \src "libresoc.v:177378.13-177378.33" + process $proc$libresoc.v:177378$10806 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:175669.13-175669.33" - process $proc$libresoc.v:175669$10742 + attribute \src "libresoc.v:177385.13-177385.33" + process $proc$libresoc.v:177385$10807 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:175676.13-175676.33" - process $proc$libresoc.v:175676$10743 + attribute \src "libresoc.v:177392.13-177392.33" + process $proc$libresoc.v:177392$10808 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:175697.3-175698.25" - process $proc$libresoc.v:175697$10668 + attribute \src "libresoc.v:177413.3-177414.25" + process $proc$libresoc.v:177413$10733 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:175699.3-175700.37" - process $proc$libresoc.v:175699$10669 + attribute \src "libresoc.v:177415.3-177416.37" + process $proc$libresoc.v:177415$10734 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:175701.3-175702.43" - process $proc$libresoc.v:175701$10670 + attribute \src "libresoc.v:177417.3-177418.43" + process $proc$libresoc.v:177417$10735 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:175703.3-175704.43" - process $proc$libresoc.v:175703$10671 + attribute \src "libresoc.v:177419.3-177420.43" + process $proc$libresoc.v:177419$10736 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:175705.3-175706.43" - process $proc$libresoc.v:175705$10672 + attribute \src "libresoc.v:177421.3-177422.43" + process $proc$libresoc.v:177421$10737 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:175707.3-175752.6" - process $proc$libresoc.v:175707$10673 + attribute \src "libresoc.v:177423.3-177468.6" + process $proc$libresoc.v:177423$10738 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:175708.5-175708.29" + assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 + attribute \src "libresoc.v:177424.5-177424.29" switch \initial - attribute \src "libresoc.v:175708.9-175708.17" + attribute \src "libresoc.v:177424.9-177424.17" case 1'1 case end @@ -361753,75 +364439,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 + assign $1\src10__data_o$next[1:0]$10740 $6\src10__data_o$next[1:0]$10745 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10741 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10676 2'00 + assign $2\src10__data_o$next[1:0]$10741 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10742 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 + assign $3\src10__data_o$next[1:0]$10742 $2\src10__data_o$next[1:0]$10741 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10743 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 + assign $4\src10__data_o$next[1:0]$10743 $3\src10__data_o$next[1:0]$10742 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10679 \w0__data_i + assign $5\src10__data_o$next[1:0]$10744 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 + assign $5\src10__data_o$next[1:0]$10744 $4\src10__data_o$next[1:0]$10743 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10680 \reg + assign $6\src10__data_o$next[1:0]$10745 \reg case - assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 + assign $6\src10__data_o$next[1:0]$10745 $5\src10__data_o$next[1:0]$10744 end case - assign $1\src10__data_o$next[1:0]$10675 2'00 + assign $1\src10__data_o$next[1:0]$10740 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10681 2'00 + assign $7\src10__data_o$next[1:0]$10746 2'00 case - assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 + assign $7\src10__data_o$next[1:0]$10746 $1\src10__data_o$next[1:0]$10740 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 end - attribute \src "libresoc.v:175753.3-175788.6" - process $proc$libresoc.v:175753$10682 + attribute \src "libresoc.v:177469.3-177504.6" + process $proc$libresoc.v:177469$10747 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:175754.5-175754.29" + attribute \src "libresoc.v:177470.5-177470.29" switch \initial - attribute \src "libresoc.v:175754.9-175754.17" + attribute \src "libresoc.v:177470.9-177470.17" case 1'1 case end @@ -361877,15 +364563,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:175789.3-175834.6" - process $proc$libresoc.v:175789$10683 + attribute \src "libresoc.v:177505.3-177550.6" + process $proc$libresoc.v:177505$10748 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:175790.5-175790.29" + assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 + attribute \src "libresoc.v:177506.5-177506.29" switch \initial - attribute \src "libresoc.v:175790.9-175790.17" + attribute \src "libresoc.v:177506.9-177506.17" case 1'1 case end @@ -361898,75 +364584,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 + assign $1\src20__data_o$next[1:0]$10750 $6\src20__data_o$next[1:0]$10755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10751 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10686 2'00 + assign $2\src20__data_o$next[1:0]$10751 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10752 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 + assign $3\src20__data_o$next[1:0]$10752 $2\src20__data_o$next[1:0]$10751 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10753 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 + assign $4\src20__data_o$next[1:0]$10753 $3\src20__data_o$next[1:0]$10752 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10689 \w0__data_i + assign $5\src20__data_o$next[1:0]$10754 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 + assign $5\src20__data_o$next[1:0]$10754 $4\src20__data_o$next[1:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10690 \reg + assign $6\src20__data_o$next[1:0]$10755 \reg case - assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 + assign $6\src20__data_o$next[1:0]$10755 $5\src20__data_o$next[1:0]$10754 end case - assign $1\src20__data_o$next[1:0]$10685 2'00 + assign $1\src20__data_o$next[1:0]$10750 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10691 2'00 + assign $7\src20__data_o$next[1:0]$10756 2'00 case - assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 + assign $7\src20__data_o$next[1:0]$10756 $1\src20__data_o$next[1:0]$10750 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 end - attribute \src "libresoc.v:175835.3-175870.6" - process $proc$libresoc.v:175835$10692 + attribute \src "libresoc.v:177551.3-177586.6" + process $proc$libresoc.v:177551$10757 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:175836.5-175836.29" + assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 + attribute \src "libresoc.v:177552.5-177552.29" switch \initial - attribute \src "libresoc.v:175836.9-175836.17" + attribute \src "libresoc.v:177552.9-177552.17" case 1'1 case end @@ -361979,58 +364665,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 + assign $1\wr_detect$4[0:0]$10759 $5\wr_detect$4[0:0]$10763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10695 1'1 + assign $2\wr_detect$4[0:0]$10760 1'1 case - assign $2\wr_detect$4[0:0]$10695 1'0 + assign $2\wr_detect$4[0:0]$10760 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10696 1'1 + assign $3\wr_detect$4[0:0]$10761 1'1 case - assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 + assign $3\wr_detect$4[0:0]$10761 $2\wr_detect$4[0:0]$10760 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10697 1'1 + assign $4\wr_detect$4[0:0]$10762 1'1 case - assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 + assign $4\wr_detect$4[0:0]$10762 $3\wr_detect$4[0:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10698 1'1 + assign $5\wr_detect$4[0:0]$10763 1'1 case - assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 + assign $5\wr_detect$4[0:0]$10763 $4\wr_detect$4[0:0]$10762 end case - assign $1\wr_detect$4[0:0]$10694 1'0 + assign $1\wr_detect$4[0:0]$10759 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10693 + update \wr_detect$4 $0\wr_detect$4[0:0]$10758 end - attribute \src "libresoc.v:175871.3-175916.6" - process $proc$libresoc.v:175871$10699 + attribute \src "libresoc.v:177587.3-177632.6" + process $proc$libresoc.v:177587$10764 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:175872.5-175872.29" + assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 + attribute \src "libresoc.v:177588.5-177588.29" switch \initial - attribute \src "libresoc.v:175872.9-175872.17" + attribute \src "libresoc.v:177588.9-177588.17" case 1'1 case end @@ -362043,75 +364729,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 + assign $1\src30__data_o$next[1:0]$10766 $6\src30__data_o$next[1:0]$10771 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10767 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10702 2'00 + assign $2\src30__data_o$next[1:0]$10767 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10768 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 + assign $3\src30__data_o$next[1:0]$10768 $2\src30__data_o$next[1:0]$10767 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10769 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 + assign $4\src30__data_o$next[1:0]$10769 $3\src30__data_o$next[1:0]$10768 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10705 \w0__data_i + assign $5\src30__data_o$next[1:0]$10770 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 + assign $5\src30__data_o$next[1:0]$10770 $4\src30__data_o$next[1:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10706 \reg + assign $6\src30__data_o$next[1:0]$10771 \reg case - assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 + assign $6\src30__data_o$next[1:0]$10771 $5\src30__data_o$next[1:0]$10770 end case - assign $1\src30__data_o$next[1:0]$10701 2'00 + assign $1\src30__data_o$next[1:0]$10766 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10707 2'00 + assign $7\src30__data_o$next[1:0]$10772 2'00 case - assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 + assign $7\src30__data_o$next[1:0]$10772 $1\src30__data_o$next[1:0]$10766 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 end - attribute \src "libresoc.v:175917.3-175952.6" - process $proc$libresoc.v:175917$10708 + attribute \src "libresoc.v:177633.3-177668.6" + process $proc$libresoc.v:177633$10773 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:175918.5-175918.29" + assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 + attribute \src "libresoc.v:177634.5-177634.29" switch \initial - attribute \src "libresoc.v:175918.9-175918.17" + attribute \src "libresoc.v:177634.9-177634.17" case 1'1 case end @@ -362124,58 +364810,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 + assign $1\wr_detect$7[0:0]$10775 $5\wr_detect$7[0:0]$10779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10711 1'1 + assign $2\wr_detect$7[0:0]$10776 1'1 case - assign $2\wr_detect$7[0:0]$10711 1'0 + assign $2\wr_detect$7[0:0]$10776 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10712 1'1 + assign $3\wr_detect$7[0:0]$10777 1'1 case - assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 + assign $3\wr_detect$7[0:0]$10777 $2\wr_detect$7[0:0]$10776 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10713 1'1 + assign $4\wr_detect$7[0:0]$10778 1'1 case - assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 + assign $4\wr_detect$7[0:0]$10778 $3\wr_detect$7[0:0]$10777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10714 1'1 + assign $5\wr_detect$7[0:0]$10779 1'1 case - assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 + assign $5\wr_detect$7[0:0]$10779 $4\wr_detect$7[0:0]$10778 end case - assign $1\wr_detect$7[0:0]$10710 1'0 + assign $1\wr_detect$7[0:0]$10775 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10709 + update \wr_detect$7 $0\wr_detect$7[0:0]$10774 end - attribute \src "libresoc.v:175953.3-175998.6" - process $proc$libresoc.v:175953$10715 + attribute \src "libresoc.v:177669.3-177714.6" + process $proc$libresoc.v:177669$10780 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:175954.5-175954.29" + assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 + attribute \src "libresoc.v:177670.5-177670.29" switch \initial - attribute \src "libresoc.v:175954.9-175954.17" + attribute \src "libresoc.v:177670.9-177670.17" case 1'1 case end @@ -362188,75 +364874,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 + assign $1\r0__data_o$next[1:0]$10782 $6\r0__data_o$next[1:0]$10787 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10783 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10718 2'00 + assign $2\r0__data_o$next[1:0]$10783 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10784 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 + assign $3\r0__data_o$next[1:0]$10784 $2\r0__data_o$next[1:0]$10783 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10785 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 + assign $4\r0__data_o$next[1:0]$10785 $3\r0__data_o$next[1:0]$10784 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10721 \w0__data_i + assign $5\r0__data_o$next[1:0]$10786 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 + assign $5\r0__data_o$next[1:0]$10786 $4\r0__data_o$next[1:0]$10785 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10722 \reg + assign $6\r0__data_o$next[1:0]$10787 \reg case - assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 + assign $6\r0__data_o$next[1:0]$10787 $5\r0__data_o$next[1:0]$10786 end case - assign $1\r0__data_o$next[1:0]$10717 2'00 + assign $1\r0__data_o$next[1:0]$10782 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10723 2'00 + assign $7\r0__data_o$next[1:0]$10788 2'00 case - assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 + assign $7\r0__data_o$next[1:0]$10788 $1\r0__data_o$next[1:0]$10782 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 end - attribute \src "libresoc.v:175999.3-176034.6" - process $proc$libresoc.v:175999$10724 + attribute \src "libresoc.v:177715.3-177750.6" + process $proc$libresoc.v:177715$10789 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:176000.5-176000.29" + assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 + attribute \src "libresoc.v:177716.5-177716.29" switch \initial - attribute \src "libresoc.v:176000.9-176000.17" + attribute \src "libresoc.v:177716.9-177716.17" case 1'1 case end @@ -362269,61 +364955,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 + assign $1\wr_detect$10[0:0]$10791 $5\wr_detect$10[0:0]$10795 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10727 1'1 + assign $2\wr_detect$10[0:0]$10792 1'1 case - assign $2\wr_detect$10[0:0]$10727 1'0 + assign $2\wr_detect$10[0:0]$10792 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10728 1'1 + assign $3\wr_detect$10[0:0]$10793 1'1 case - assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 + assign $3\wr_detect$10[0:0]$10793 $2\wr_detect$10[0:0]$10792 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10729 1'1 + assign $4\wr_detect$10[0:0]$10794 1'1 case - assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 + assign $4\wr_detect$10[0:0]$10794 $3\wr_detect$10[0:0]$10793 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10730 1'1 + assign $5\wr_detect$10[0:0]$10795 1'1 case - assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 + assign $5\wr_detect$10[0:0]$10795 $4\wr_detect$10[0:0]$10794 end case - assign $1\wr_detect$10[0:0]$10726 1'0 + assign $1\wr_detect$10[0:0]$10791 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10725 + update \wr_detect$10 $0\wr_detect$10[0:0]$10790 end - attribute \src "libresoc.v:176035.3-176067.6" - process $proc$libresoc.v:176035$10731 + attribute \src "libresoc.v:177751.3-177783.6" + process $proc$libresoc.v:177751$10796 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:176036.5-176036.29" + assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 + attribute \src "libresoc.v:177752.5-177752.29" switch \initial - attribute \src "libresoc.v:176036.9-176036.17" + attribute \src "libresoc.v:177752.9-177752.17" case 1'1 case end @@ -362332,179 +365018,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10733 \dest10__data_i + assign $1\reg$next[1:0]$10798 \dest10__data_i case - assign $1\reg$next[1:0]$10733 \reg + assign $1\reg$next[1:0]$10798 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10734 \dest20__data_i + assign $2\reg$next[1:0]$10799 \dest20__data_i case - assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 + assign $2\reg$next[1:0]$10799 $1\reg$next[1:0]$10798 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10735 \dest30__data_i + assign $3\reg$next[1:0]$10800 \dest30__data_i case - assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 + assign $3\reg$next[1:0]$10800 $2\reg$next[1:0]$10799 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10736 \w0__data_i + assign $4\reg$next[1:0]$10801 \w0__data_i case - assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 + assign $4\reg$next[1:0]$10801 $3\reg$next[1:0]$10800 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10737 2'00 + assign $5\reg$next[1:0]$10802 2'00 case - assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 + assign $5\reg$next[1:0]$10802 $4\reg$next[1:0]$10801 end sync always - update \reg$next $0\reg$next[1:0]$10732 + update \reg$next $0\reg$next[1:0]$10797 end - connect \$9 $not$libresoc.v:175693$10664_Y - connect \$1 $not$libresoc.v:175694$10665_Y - connect \$3 $not$libresoc.v:175695$10666_Y - connect \$6 $not$libresoc.v:175696$10667_Y + connect \$9 $not$libresoc.v:177409$10729_Y + connect \$1 $not$libresoc.v:177410$10730_Y + connect \$3 $not$libresoc.v:177411$10731_Y + connect \$6 $not$libresoc.v:177412$10732_Y end -attribute \src "libresoc.v:176072.1-176421.10" +attribute \src "libresoc.v:177788.1-178137.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $0\cia0__data_o$next[63:0]$10752 - attribute \src "libresoc.v:176140.3-176141.41" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $0\cia0__data_o$next[63:0]$10817 + attribute \src "libresoc.v:177856.3-177857.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:176073.7-176073.20" + attribute \src "libresoc.v:177789.7-177789.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $0\msr0__data_o$next[63:0]$10762 - attribute \src "libresoc.v:176138.3-176139.41" + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $0\msr0__data_o$next[63:0]$10827 + attribute \src "libresoc.v:177854.3-177855.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $0\reg$next[63:0]$10794 - attribute \src "libresoc.v:176134.3-176135.25" + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $0\reg$next[63:0]$10859 + attribute \src "libresoc.v:177850.3-177851.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $0\sv0__data_o$next[63:0]$10778 - attribute \src "libresoc.v:176136.3-176137.39" + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $0\sv0__data_o$next[63:0]$10843 + attribute \src "libresoc.v:177852.3-177853.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:176270.3-176305.6" - wire $0\wr_detect$4[0:0]$10771 - attribute \src "libresoc.v:176352.3-176387.6" - wire $0\wr_detect$7[0:0]$10787 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177986.3-178021.6" + wire $0\wr_detect$4[0:0]$10836 + attribute \src "libresoc.v:178068.3-178103.6" + wire $0\wr_detect$7[0:0]$10852 + attribute \src "libresoc.v:177904.3-177939.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $1\cia0__data_o$next[63:0]$10753 - attribute \src "libresoc.v:176082.14-176082.49" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $1\cia0__data_o$next[63:0]$10818 + attribute \src "libresoc.v:177798.14-177798.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $1\msr0__data_o$next[63:0]$10763 - attribute \src "libresoc.v:176099.14-176099.49" + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $1\msr0__data_o$next[63:0]$10828 + attribute \src "libresoc.v:177815.14-177815.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $1\reg$next[63:0]$10795 - attribute \src "libresoc.v:176111.14-176111.42" + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $1\reg$next[63:0]$10860 + attribute \src "libresoc.v:177827.14-177827.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $1\sv0__data_o$next[63:0]$10779 - attribute \src "libresoc.v:176118.14-176118.48" + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $1\sv0__data_o$next[63:0]$10844 + attribute \src "libresoc.v:177834.14-177834.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:176270.3-176305.6" - wire $1\wr_detect$4[0:0]$10772 - attribute \src "libresoc.v:176352.3-176387.6" - wire $1\wr_detect$7[0:0]$10788 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177986.3-178021.6" + wire $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:178068.3-178103.6" + wire $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:177904.3-177939.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $2\cia0__data_o$next[63:0]$10754 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $2\msr0__data_o$next[63:0]$10764 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $2\reg$next[63:0]$10796 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $2\sv0__data_o$next[63:0]$10780 - attribute \src "libresoc.v:176270.3-176305.6" - wire $2\wr_detect$4[0:0]$10773 - attribute \src "libresoc.v:176352.3-176387.6" - wire $2\wr_detect$7[0:0]$10789 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $2\cia0__data_o$next[63:0]$10819 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $2\msr0__data_o$next[63:0]$10829 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $2\reg$next[63:0]$10861 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $2\sv0__data_o$next[63:0]$10845 + attribute \src "libresoc.v:177986.3-178021.6" + wire $2\wr_detect$4[0:0]$10838 + attribute \src "libresoc.v:178068.3-178103.6" + wire $2\wr_detect$7[0:0]$10854 + attribute \src "libresoc.v:177904.3-177939.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $3\cia0__data_o$next[63:0]$10755 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $3\msr0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $3\reg$next[63:0]$10797 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $3\sv0__data_o$next[63:0]$10781 - attribute \src "libresoc.v:176270.3-176305.6" - wire $3\wr_detect$4[0:0]$10774 - attribute \src "libresoc.v:176352.3-176387.6" - wire $3\wr_detect$7[0:0]$10790 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $3\cia0__data_o$next[63:0]$10820 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $3\msr0__data_o$next[63:0]$10830 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $3\reg$next[63:0]$10862 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $3\sv0__data_o$next[63:0]$10846 + attribute \src "libresoc.v:177986.3-178021.6" + wire $3\wr_detect$4[0:0]$10839 + attribute \src "libresoc.v:178068.3-178103.6" + wire $3\wr_detect$7[0:0]$10855 + attribute \src "libresoc.v:177904.3-177939.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $4\cia0__data_o$next[63:0]$10756 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $4\msr0__data_o$next[63:0]$10766 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $4\reg$next[63:0]$10798 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $4\sv0__data_o$next[63:0]$10782 - attribute \src "libresoc.v:176270.3-176305.6" - wire $4\wr_detect$4[0:0]$10775 - attribute \src "libresoc.v:176352.3-176387.6" - wire $4\wr_detect$7[0:0]$10791 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $4\cia0__data_o$next[63:0]$10821 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $4\msr0__data_o$next[63:0]$10831 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $4\reg$next[63:0]$10863 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $4\sv0__data_o$next[63:0]$10847 + attribute \src "libresoc.v:177986.3-178021.6" + wire $4\wr_detect$4[0:0]$10840 + attribute \src "libresoc.v:178068.3-178103.6" + wire $4\wr_detect$7[0:0]$10856 + attribute \src "libresoc.v:177904.3-177939.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $5\cia0__data_o$next[63:0]$10757 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $5\msr0__data_o$next[63:0]$10767 - attribute \src "libresoc.v:176388.3-176420.6" - wire width 64 $5\reg$next[63:0]$10799 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $5\sv0__data_o$next[63:0]$10783 - attribute \src "libresoc.v:176270.3-176305.6" - wire $5\wr_detect$4[0:0]$10776 - attribute \src "libresoc.v:176352.3-176387.6" - wire $5\wr_detect$7[0:0]$10792 - attribute \src "libresoc.v:176188.3-176223.6" + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $5\cia0__data_o$next[63:0]$10822 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $5\msr0__data_o$next[63:0]$10832 + attribute \src "libresoc.v:178104.3-178136.6" + wire width 64 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $5\sv0__data_o$next[63:0]$10848 + attribute \src "libresoc.v:177986.3-178021.6" + wire $5\wr_detect$4[0:0]$10841 + attribute \src "libresoc.v:178068.3-178103.6" + wire $5\wr_detect$7[0:0]$10857 + attribute \src "libresoc.v:177904.3-177939.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $6\cia0__data_o$next[63:0]$10758 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $6\msr0__data_o$next[63:0]$10768 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $6\sv0__data_o$next[63:0]$10784 - attribute \src "libresoc.v:176142.3-176187.6" - wire width 64 $7\cia0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:176224.3-176269.6" - wire width 64 $7\msr0__data_o$next[63:0]$10769 - attribute \src "libresoc.v:176306.3-176351.6" - wire width 64 $7\sv0__data_o$next[63:0]$10785 - attribute \src "libresoc.v:176131.17-176131.100" - wire $not$libresoc.v:176131$10744_Y - attribute \src "libresoc.v:176132.17-176132.103" - wire $not$libresoc.v:176132$10745_Y - attribute \src "libresoc.v:176133.17-176133.103" - wire $not$libresoc.v:176133$10746_Y + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $6\cia0__data_o$next[63:0]$10823 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $6\msr0__data_o$next[63:0]$10833 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $6\sv0__data_o$next[63:0]$10849 + attribute \src "libresoc.v:177858.3-177903.6" + wire width 64 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177940.3-177985.6" + wire width 64 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:178022.3-178067.6" + wire width 64 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:177847.17-177847.100" + wire $not$libresoc.v:177847$10809_Y + attribute \src "libresoc.v:177848.17-177848.103" + wire $not$libresoc.v:177848$10810_Y + attribute \src "libresoc.v:177849.17-177849.103" + wire $not$libresoc.v:177849$10811_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -362517,15 +365203,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:176073.7-176073.15" + attribute \src "libresoc.v:177789.7-177789.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -362562,106 +365248,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176131$10744 + cell $not $not$libresoc.v:177847$10809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176131$10744_Y + connect \Y $not$libresoc.v:177847$10809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176132$10745 + cell $not $not$libresoc.v:177848$10810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176132$10745_Y + connect \Y $not$libresoc.v:177848$10810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176133$10746 + cell $not $not$libresoc.v:177849$10811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176133$10746_Y + connect \Y $not$libresoc.v:177849$10811_Y end - attribute \src "libresoc.v:176073.7-176073.20" - process $proc$libresoc.v:176073$10800 + attribute \src "libresoc.v:177789.7-177789.20" + process $proc$libresoc.v:177789$10865 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176082.14-176082.49" - process $proc$libresoc.v:176082$10801 + attribute \src "libresoc.v:177798.14-177798.49" + process $proc$libresoc.v:177798$10866 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:176099.14-176099.49" - process $proc$libresoc.v:176099$10802 + attribute \src "libresoc.v:177815.14-177815.49" + process $proc$libresoc.v:177815$10867 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:176111.14-176111.42" - process $proc$libresoc.v:176111$10803 + attribute \src "libresoc.v:177827.14-177827.42" + process $proc$libresoc.v:177827$10868 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:176118.14-176118.48" - process $proc$libresoc.v:176118$10804 + attribute \src "libresoc.v:177834.14-177834.48" + process $proc$libresoc.v:177834$10869 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:176134.3-176135.25" - process $proc$libresoc.v:176134$10747 + attribute \src "libresoc.v:177850.3-177851.25" + process $proc$libresoc.v:177850$10812 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:176136.3-176137.39" - process $proc$libresoc.v:176136$10748 + attribute \src "libresoc.v:177852.3-177853.39" + process $proc$libresoc.v:177852$10813 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:176138.3-176139.41" - process $proc$libresoc.v:176138$10749 + attribute \src "libresoc.v:177854.3-177855.41" + process $proc$libresoc.v:177854$10814 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:176140.3-176141.41" - process $proc$libresoc.v:176140$10750 + attribute \src "libresoc.v:177856.3-177857.41" + process $proc$libresoc.v:177856$10815 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:176142.3-176187.6" - process $proc$libresoc.v:176142$10751 + attribute \src "libresoc.v:177858.3-177903.6" + process $proc$libresoc.v:177858$10816 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10752 $7\cia0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:176143.5-176143.29" + assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:177859.5-177859.29" switch \initial - attribute \src "libresoc.v:176143.9-176143.17" + attribute \src "libresoc.v:177859.9-177859.17" case 1'1 case end @@ -362674,75 +365360,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10753 $6\cia0__data_o$next[63:0]$10758 + assign $1\cia0__data_o$next[63:0]$10818 $6\cia0__data_o$next[63:0]$10823 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10754 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10819 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10819 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10755 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10820 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10755 $2\cia0__data_o$next[63:0]$10754 + assign $3\cia0__data_o$next[63:0]$10820 $2\cia0__data_o$next[63:0]$10819 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10756 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10821 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10756 $3\cia0__data_o$next[63:0]$10755 + assign $4\cia0__data_o$next[63:0]$10821 $3\cia0__data_o$next[63:0]$10820 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10757 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10822 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10757 $4\cia0__data_o$next[63:0]$10756 + assign $5\cia0__data_o$next[63:0]$10822 $4\cia0__data_o$next[63:0]$10821 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10758 \reg + assign $6\cia0__data_o$next[63:0]$10823 \reg case - assign $6\cia0__data_o$next[63:0]$10758 $5\cia0__data_o$next[63:0]$10757 + assign $6\cia0__data_o$next[63:0]$10823 $5\cia0__data_o$next[63:0]$10822 end case - assign $1\cia0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10824 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10759 $1\cia0__data_o$next[63:0]$10753 + assign $7\cia0__data_o$next[63:0]$10824 $1\cia0__data_o$next[63:0]$10818 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10752 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 end - attribute \src "libresoc.v:176188.3-176223.6" - process $proc$libresoc.v:176188$10760 + attribute \src "libresoc.v:177904.3-177939.6" + process $proc$libresoc.v:177904$10825 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176189.5-176189.29" + attribute \src "libresoc.v:177905.5-177905.29" switch \initial - attribute \src "libresoc.v:176189.9-176189.17" + attribute \src "libresoc.v:177905.9-177905.17" case 1'1 case end @@ -362798,15 +365484,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176224.3-176269.6" - process $proc$libresoc.v:176224$10761 + attribute \src "libresoc.v:177940.3-177985.6" + process $proc$libresoc.v:177940$10826 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10762 $7\msr0__data_o$next[63:0]$10769 - attribute \src "libresoc.v:176225.5-176225.29" + assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:177941.5-177941.29" switch \initial - attribute \src "libresoc.v:176225.9-176225.17" + attribute \src "libresoc.v:177941.9-177941.17" case 1'1 case end @@ -362819,75 +365505,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10763 $6\msr0__data_o$next[63:0]$10768 + assign $1\msr0__data_o$next[63:0]$10828 $6\msr0__data_o$next[63:0]$10833 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10764 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10829 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10764 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10765 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10830 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10765 $2\msr0__data_o$next[63:0]$10764 + assign $3\msr0__data_o$next[63:0]$10830 $2\msr0__data_o$next[63:0]$10829 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10766 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10831 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10766 $3\msr0__data_o$next[63:0]$10765 + assign $4\msr0__data_o$next[63:0]$10831 $3\msr0__data_o$next[63:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10767 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10832 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10767 $4\msr0__data_o$next[63:0]$10766 + assign $5\msr0__data_o$next[63:0]$10832 $4\msr0__data_o$next[63:0]$10831 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10768 \reg + assign $6\msr0__data_o$next[63:0]$10833 \reg case - assign $6\msr0__data_o$next[63:0]$10768 $5\msr0__data_o$next[63:0]$10767 + assign $6\msr0__data_o$next[63:0]$10833 $5\msr0__data_o$next[63:0]$10832 end case - assign $1\msr0__data_o$next[63:0]$10763 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10769 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10769 $1\msr0__data_o$next[63:0]$10763 + assign $7\msr0__data_o$next[63:0]$10834 $1\msr0__data_o$next[63:0]$10828 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10762 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 end - attribute \src "libresoc.v:176270.3-176305.6" - process $proc$libresoc.v:176270$10770 + attribute \src "libresoc.v:177986.3-178021.6" + process $proc$libresoc.v:177986$10835 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10771 $1\wr_detect$4[0:0]$10772 - attribute \src "libresoc.v:176271.5-176271.29" + assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:177987.5-177987.29" switch \initial - attribute \src "libresoc.v:176271.9-176271.17" + attribute \src "libresoc.v:177987.9-177987.17" case 1'1 case end @@ -362900,58 +365586,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10772 $5\wr_detect$4[0:0]$10776 + assign $1\wr_detect$4[0:0]$10837 $5\wr_detect$4[0:0]$10841 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10773 1'1 + assign $2\wr_detect$4[0:0]$10838 1'1 case - assign $2\wr_detect$4[0:0]$10773 1'0 + assign $2\wr_detect$4[0:0]$10838 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10774 1'1 + assign $3\wr_detect$4[0:0]$10839 1'1 case - assign $3\wr_detect$4[0:0]$10774 $2\wr_detect$4[0:0]$10773 + assign $3\wr_detect$4[0:0]$10839 $2\wr_detect$4[0:0]$10838 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10775 1'1 + assign $4\wr_detect$4[0:0]$10840 1'1 case - assign $4\wr_detect$4[0:0]$10775 $3\wr_detect$4[0:0]$10774 + assign $4\wr_detect$4[0:0]$10840 $3\wr_detect$4[0:0]$10839 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10776 1'1 + assign $5\wr_detect$4[0:0]$10841 1'1 case - assign $5\wr_detect$4[0:0]$10776 $4\wr_detect$4[0:0]$10775 + assign $5\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10840 end case - assign $1\wr_detect$4[0:0]$10772 1'0 + assign $1\wr_detect$4[0:0]$10837 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10771 + update \wr_detect$4 $0\wr_detect$4[0:0]$10836 end - attribute \src "libresoc.v:176306.3-176351.6" - process $proc$libresoc.v:176306$10777 + attribute \src "libresoc.v:178022.3-178067.6" + process $proc$libresoc.v:178022$10842 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10778 $7\sv0__data_o$next[63:0]$10785 - attribute \src "libresoc.v:176307.5-176307.29" + assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 + attribute \src "libresoc.v:178023.5-178023.29" switch \initial - attribute \src "libresoc.v:176307.9-176307.17" + attribute \src "libresoc.v:178023.9-178023.17" case 1'1 case end @@ -362964,75 +365650,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10779 $6\sv0__data_o$next[63:0]$10784 + assign $1\sv0__data_o$next[63:0]$10844 $6\sv0__data_o$next[63:0]$10849 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10780 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10845 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10780 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10845 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10781 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10846 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10781 $2\sv0__data_o$next[63:0]$10780 + assign $3\sv0__data_o$next[63:0]$10846 $2\sv0__data_o$next[63:0]$10845 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10782 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10847 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10782 $3\sv0__data_o$next[63:0]$10781 + assign $4\sv0__data_o$next[63:0]$10847 $3\sv0__data_o$next[63:0]$10846 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10783 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10848 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10783 $4\sv0__data_o$next[63:0]$10782 + assign $5\sv0__data_o$next[63:0]$10848 $4\sv0__data_o$next[63:0]$10847 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10784 \reg + assign $6\sv0__data_o$next[63:0]$10849 \reg case - assign $6\sv0__data_o$next[63:0]$10784 $5\sv0__data_o$next[63:0]$10783 + assign $6\sv0__data_o$next[63:0]$10849 $5\sv0__data_o$next[63:0]$10848 end case - assign $1\sv0__data_o$next[63:0]$10779 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10844 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10785 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10850 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10785 $1\sv0__data_o$next[63:0]$10779 + assign $7\sv0__data_o$next[63:0]$10850 $1\sv0__data_o$next[63:0]$10844 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10778 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 end - attribute \src "libresoc.v:176352.3-176387.6" - process $proc$libresoc.v:176352$10786 + attribute \src "libresoc.v:178068.3-178103.6" + process $proc$libresoc.v:178068$10851 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10787 $1\wr_detect$7[0:0]$10788 - attribute \src "libresoc.v:176353.5-176353.29" + assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 + attribute \src "libresoc.v:178069.5-178069.29" switch \initial - attribute \src "libresoc.v:176353.9-176353.17" + attribute \src "libresoc.v:178069.9-178069.17" case 1'1 case end @@ -363045,61 +365731,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10788 $5\wr_detect$7[0:0]$10792 + assign $1\wr_detect$7[0:0]$10853 $5\wr_detect$7[0:0]$10857 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10789 1'1 + assign $2\wr_detect$7[0:0]$10854 1'1 case - assign $2\wr_detect$7[0:0]$10789 1'0 + assign $2\wr_detect$7[0:0]$10854 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10790 1'1 + assign $3\wr_detect$7[0:0]$10855 1'1 case - assign $3\wr_detect$7[0:0]$10790 $2\wr_detect$7[0:0]$10789 + assign $3\wr_detect$7[0:0]$10855 $2\wr_detect$7[0:0]$10854 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10791 1'1 + assign $4\wr_detect$7[0:0]$10856 1'1 case - assign $4\wr_detect$7[0:0]$10791 $3\wr_detect$7[0:0]$10790 + assign $4\wr_detect$7[0:0]$10856 $3\wr_detect$7[0:0]$10855 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10792 1'1 + assign $5\wr_detect$7[0:0]$10857 1'1 case - assign $5\wr_detect$7[0:0]$10792 $4\wr_detect$7[0:0]$10791 + assign $5\wr_detect$7[0:0]$10857 $4\wr_detect$7[0:0]$10856 end case - assign $1\wr_detect$7[0:0]$10788 1'0 + assign $1\wr_detect$7[0:0]$10853 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10787 + update \wr_detect$7 $0\wr_detect$7[0:0]$10852 end - attribute \src "libresoc.v:176388.3-176420.6" - process $proc$libresoc.v:176388$10793 + attribute \src "libresoc.v:178104.3-178136.6" + process $proc$libresoc.v:178104$10858 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10794 $5\reg$next[63:0]$10799 - attribute \src "libresoc.v:176389.5-176389.29" + assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 + attribute \src "libresoc.v:178105.5-178105.29" switch \initial - attribute \src "libresoc.v:176389.9-176389.17" + attribute \src "libresoc.v:178105.9-178105.17" case 1'1 case end @@ -363108,286 +365794,324 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10795 \nia0__data_i + assign $1\reg$next[63:0]$10860 \nia0__data_i case - assign $1\reg$next[63:0]$10795 \reg + assign $1\reg$next[63:0]$10860 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10796 \msr0__data_i + assign $2\reg$next[63:0]$10861 \msr0__data_i case - assign $2\reg$next[63:0]$10796 $1\reg$next[63:0]$10795 + assign $2\reg$next[63:0]$10861 $1\reg$next[63:0]$10860 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10797 \sv0__data_i + assign $3\reg$next[63:0]$10862 \sv0__data_i case - assign $3\reg$next[63:0]$10797 $2\reg$next[63:0]$10796 + assign $3\reg$next[63:0]$10862 $2\reg$next[63:0]$10861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10798 \d_wr10__data_i + assign $4\reg$next[63:0]$10863 \d_wr10__data_i case - assign $4\reg$next[63:0]$10798 $3\reg$next[63:0]$10797 + assign $4\reg$next[63:0]$10863 $3\reg$next[63:0]$10862 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10864 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10799 $4\reg$next[63:0]$10798 + assign $5\reg$next[63:0]$10864 $4\reg$next[63:0]$10863 end sync always - update \reg$next $0\reg$next[63:0]$10794 + update \reg$next $0\reg$next[63:0]$10859 end - connect \$1 $not$libresoc.v:176131$10744_Y - connect \$3 $not$libresoc.v:176132$10745_Y - connect \$6 $not$libresoc.v:176133$10746_Y + connect \$1 $not$libresoc.v:177847$10809_Y + connect \$3 $not$libresoc.v:177848$10810_Y + connect \$6 $not$libresoc.v:177849$10811_Y end -attribute \src "libresoc.v:176425.1-176896.10" +attribute \src "libresoc.v:178141.1-178696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:176426.7-176426.20" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 + attribute \src "libresoc.v:178247.3-178248.49" + wire width 4 $0\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178142.7-178142.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $0\r1__data_o$next[3:0]$10860 - attribute \src "libresoc.v:176511.3-176512.37" + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $0\r1__data_o$next[3:0]$10955 + attribute \src "libresoc.v:178239.3-178240.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $0\r21__data_o$next[3:0]$10874 - attribute \src "libresoc.v:176509.3-176510.39" + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $0\r21__data_o$next[3:0]$10893 + attribute \src "libresoc.v:178237.3-178238.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $0\reg$next[3:0]$10826 - attribute \src "libresoc.v:176507.3-176508.25" + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $0\reg$next[3:0]$10907 + attribute \src "libresoc.v:178235.3-178236.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $0\src11__data_o$next[3:0]$10817 - attribute \src "libresoc.v:176517.3-176518.43" + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $0\src11__data_o$next[3:0]$10913 + attribute \src "libresoc.v:178245.3-178246.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $0\src21__data_o$next[3:0]$10832 - attribute \src "libresoc.v:176515.3-176516.43" + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $0\src21__data_o$next[3:0]$10927 + attribute \src "libresoc.v:178243.3-178244.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $0\src31__data_o$next[3:0]$10846 - attribute \src "libresoc.v:176513.3-176514.43" + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $0\src31__data_o$next[3:0]$10941 + attribute \src "libresoc.v:178241.3-178242.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:176796.3-176825.6" - wire $0\wr_detect$10[0:0]$10868 - attribute \src "libresoc.v:176866.3-176895.6" - wire $0\wr_detect$13[0:0]$10882 - attribute \src "libresoc.v:176656.3-176685.6" - wire $0\wr_detect$4[0:0]$10840 - attribute \src "libresoc.v:176726.3-176755.6" - wire $0\wr_detect$7[0:0]$10854 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178596.3-178625.6" + wire $0\wr_detect$10[0:0]$10949 + attribute \src "libresoc.v:178666.3-178695.6" + wire $0\wr_detect$13[0:0]$10963 + attribute \src "libresoc.v:178359.3-178388.6" + wire $0\wr_detect$16[0:0]$10901 + attribute \src "libresoc.v:178456.3-178485.6" + wire $0\wr_detect$4[0:0]$10921 + attribute \src "libresoc.v:178526.3-178555.6" + wire $0\wr_detect$7[0:0]$10935 + attribute \src "libresoc.v:178289.3-178318.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $1\r1__data_o$next[3:0]$10861 - attribute \src "libresoc.v:176451.13-176451.30" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 + attribute \src "libresoc.v:178161.13-178161.36" + wire width 4 $1\cr_pred1__data_o[3:0] + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $1\r1__data_o$next[3:0]$10956 + attribute \src "libresoc.v:178176.13-178176.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $1\r21__data_o$next[3:0]$10875 - attribute \src "libresoc.v:176458.13-176458.31" + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $1\r21__data_o$next[3:0]$10894 + attribute \src "libresoc.v:178183.13-178183.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $1\reg$next[3:0]$10827 - attribute \src "libresoc.v:176464.13-176464.25" + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $1\reg$next[3:0]$10908 + attribute \src "libresoc.v:178189.13-178189.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $1\src11__data_o$next[3:0]$10818 - attribute \src "libresoc.v:176469.13-176469.33" + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $1\src11__data_o$next[3:0]$10914 + attribute \src "libresoc.v:178194.13-178194.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $1\src21__data_o$next[3:0]$10833 - attribute \src "libresoc.v:176476.13-176476.33" + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $1\src21__data_o$next[3:0]$10928 + attribute \src "libresoc.v:178201.13-178201.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $1\src31__data_o$next[3:0]$10847 - attribute \src "libresoc.v:176483.13-176483.33" + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $1\src31__data_o$next[3:0]$10942 + attribute \src "libresoc.v:178208.13-178208.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:176796.3-176825.6" - wire $1\wr_detect$10[0:0]$10869 - attribute \src "libresoc.v:176866.3-176895.6" - wire $1\wr_detect$13[0:0]$10883 - attribute \src "libresoc.v:176656.3-176685.6" - wire $1\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:176726.3-176755.6" - wire $1\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178596.3-178625.6" + wire $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178666.3-178695.6" + wire $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178359.3-178388.6" + wire $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178456.3-178485.6" + wire $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178526.3-178555.6" + wire $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178289.3-178318.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $2\r1__data_o$next[3:0]$10862 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $2\r21__data_o$next[3:0]$10876 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $2\reg$next[3:0]$10828 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $2\src11__data_o$next[3:0]$10819 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $2\src21__data_o$next[3:0]$10834 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $2\src31__data_o$next[3:0]$10848 - attribute \src "libresoc.v:176796.3-176825.6" - wire $2\wr_detect$10[0:0]$10870 - attribute \src "libresoc.v:176866.3-176895.6" - wire $2\wr_detect$13[0:0]$10884 - attribute \src "libresoc.v:176656.3-176685.6" - wire $2\wr_detect$4[0:0]$10842 - attribute \src "libresoc.v:176726.3-176755.6" - wire $2\wr_detect$7[0:0]$10856 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $2\r1__data_o$next[3:0]$10957 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $2\r21__data_o$next[3:0]$10895 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $2\reg$next[3:0]$10909 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $2\src11__data_o$next[3:0]$10915 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $2\src21__data_o$next[3:0]$10929 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $2\src31__data_o$next[3:0]$10943 + attribute \src "libresoc.v:178596.3-178625.6" + wire $2\wr_detect$10[0:0]$10951 + attribute \src "libresoc.v:178666.3-178695.6" + wire $2\wr_detect$13[0:0]$10965 + attribute \src "libresoc.v:178359.3-178388.6" + wire $2\wr_detect$16[0:0]$10903 + attribute \src "libresoc.v:178456.3-178485.6" + wire $2\wr_detect$4[0:0]$10923 + attribute \src "libresoc.v:178526.3-178555.6" + wire $2\wr_detect$7[0:0]$10937 + attribute \src "libresoc.v:178289.3-178318.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $3\r1__data_o$next[3:0]$10863 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $3\r21__data_o$next[3:0]$10877 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $3\reg$next[3:0]$10829 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $3\src11__data_o$next[3:0]$10820 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $3\src21__data_o$next[3:0]$10835 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $3\src31__data_o$next[3:0]$10849 - attribute \src "libresoc.v:176796.3-176825.6" - wire $3\wr_detect$10[0:0]$10871 - attribute \src "libresoc.v:176866.3-176895.6" - wire $3\wr_detect$13[0:0]$10885 - attribute \src "libresoc.v:176656.3-176685.6" - wire $3\wr_detect$4[0:0]$10843 - attribute \src "libresoc.v:176726.3-176755.6" - wire $3\wr_detect$7[0:0]$10857 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $3\r1__data_o$next[3:0]$10958 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $3\r21__data_o$next[3:0]$10896 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $3\reg$next[3:0]$10910 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $3\src11__data_o$next[3:0]$10916 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $3\src21__data_o$next[3:0]$10930 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $3\src31__data_o$next[3:0]$10944 + attribute \src "libresoc.v:178596.3-178625.6" + wire $3\wr_detect$10[0:0]$10952 + attribute \src "libresoc.v:178666.3-178695.6" + wire $3\wr_detect$13[0:0]$10966 + attribute \src "libresoc.v:178359.3-178388.6" + wire $3\wr_detect$16[0:0]$10904 + attribute \src "libresoc.v:178456.3-178485.6" + wire $3\wr_detect$4[0:0]$10924 + attribute \src "libresoc.v:178526.3-178555.6" + wire $3\wr_detect$7[0:0]$10938 + attribute \src "libresoc.v:178289.3-178318.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $4\r1__data_o$next[3:0]$10864 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $4\r21__data_o$next[3:0]$10878 - attribute \src "libresoc.v:176589.3-176615.6" - wire width 4 $4\reg$next[3:0]$10830 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $4\src11__data_o$next[3:0]$10821 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $4\src21__data_o$next[3:0]$10836 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $4\src31__data_o$next[3:0]$10850 - attribute \src "libresoc.v:176796.3-176825.6" - wire $4\wr_detect$10[0:0]$10872 - attribute \src "libresoc.v:176866.3-176895.6" - wire $4\wr_detect$13[0:0]$10886 - attribute \src "libresoc.v:176656.3-176685.6" - wire $4\wr_detect$4[0:0]$10844 - attribute \src "libresoc.v:176726.3-176755.6" - wire $4\wr_detect$7[0:0]$10858 - attribute \src "libresoc.v:176559.3-176588.6" + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $4\r1__data_o$next[3:0]$10959 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $4\r21__data_o$next[3:0]$10897 + attribute \src "libresoc.v:178389.3-178415.6" + wire width 4 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $4\src11__data_o$next[3:0]$10917 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $4\src21__data_o$next[3:0]$10931 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $4\src31__data_o$next[3:0]$10945 + attribute \src "libresoc.v:178596.3-178625.6" + wire $4\wr_detect$10[0:0]$10953 + attribute \src "libresoc.v:178666.3-178695.6" + wire $4\wr_detect$13[0:0]$10967 + attribute \src "libresoc.v:178359.3-178388.6" + wire $4\wr_detect$16[0:0]$10905 + attribute \src "libresoc.v:178456.3-178485.6" + wire $4\wr_detect$4[0:0]$10925 + attribute \src "libresoc.v:178526.3-178555.6" + wire $4\wr_detect$7[0:0]$10939 + attribute \src "libresoc.v:178289.3-178318.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $5\r1__data_o$next[3:0]$10865 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $5\r21__data_o$next[3:0]$10879 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $5\src11__data_o$next[3:0]$10822 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $5\src21__data_o$next[3:0]$10837 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $5\src31__data_o$next[3:0]$10851 - attribute \src "libresoc.v:176756.3-176795.6" - wire width 4 $6\r1__data_o$next[3:0]$10866 - attribute \src "libresoc.v:176826.3-176865.6" - wire width 4 $6\r21__data_o$next[3:0]$10880 - attribute \src "libresoc.v:176519.3-176558.6" - wire width 4 $6\src11__data_o$next[3:0]$10823 - attribute \src "libresoc.v:176616.3-176655.6" - wire width 4 $6\src21__data_o$next[3:0]$10838 - attribute \src "libresoc.v:176686.3-176725.6" - wire width 4 $6\src31__data_o$next[3:0]$10852 - attribute \src "libresoc.v:176502.17-176502.104" - wire $not$libresoc.v:176502$10805_Y - attribute \src "libresoc.v:176503.18-176503.105" - wire $not$libresoc.v:176503$10806_Y - attribute \src "libresoc.v:176504.17-176504.100" - wire $not$libresoc.v:176504$10807_Y - attribute \src "libresoc.v:176505.17-176505.103" - wire $not$libresoc.v:176505$10808_Y - attribute \src "libresoc.v:176506.17-176506.103" - wire $not$libresoc.v:176506$10809_Y + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $5\r1__data_o$next[3:0]$10960 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $5\r21__data_o$next[3:0]$10898 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $5\src11__data_o$next[3:0]$10918 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $5\src21__data_o$next[3:0]$10932 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $5\src31__data_o$next[3:0]$10946 + attribute \src "libresoc.v:178249.3-178288.6" + wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178626.3-178665.6" + wire width 4 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178319.3-178358.6" + wire width 4 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178416.3-178455.6" + wire width 4 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178486.3-178525.6" + wire width 4 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178556.3-178595.6" + wire width 4 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178229.17-178229.104" + wire $not$libresoc.v:178229$10870_Y + attribute \src "libresoc.v:178230.18-178230.105" + wire $not$libresoc.v:178230$10871_Y + attribute \src "libresoc.v:178231.18-178231.105" + wire $not$libresoc.v:178231$10872_Y + attribute \src "libresoc.v:178232.17-178232.100" + wire $not$libresoc.v:178232$10873_Y + attribute \src "libresoc.v:178233.17-178233.103" + wire $not$libresoc.v:178233$10874_Y + attribute \src "libresoc.v:178234.17-178234.103" + wire $not$libresoc.v:178234$10875_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest11__data_i + wire width 4 output 3 \cr_pred1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest11__wen + wire width 4 \cr_pred1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest21__data_i + wire input 2 \cr_pred1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest21__wen - attribute \src "libresoc.v:176426.7-176426.15" + wire width 4 input 11 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest21__wen + attribute \src "libresoc.v:178142.7-178142.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r1__data_o + wire width 4 output 14 \r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r1__ren + wire input 15 \r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r21__data_o + wire width 4 output 16 \r21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r21__ren + wire input 17 \r21__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src11__data_o + wire width 4 output 5 \src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src11__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src11__ren + wire input 4 \src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src21__data_o + wire width 4 output 7 \src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src21__ren + wire input 6 \src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src31__data_o + wire width 4 output 9 \src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src31__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src31__ren + wire input 8 \src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w1__data_i + wire width 4 input 18 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w1__wen + wire input 19 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -363395,232 +366119,257 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176502$10805 + cell $not $not$libresoc.v:178229$10870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176502$10805_Y + connect \Y $not$libresoc.v:178229$10870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176503$10806 + cell $not $not$libresoc.v:178230$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176503$10806_Y + connect \Y $not$libresoc.v:178230$10871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176504$10807 + cell $not $not$libresoc.v:178231$10872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:178231$10872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:178232$10873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176504$10807_Y + connect \Y $not$libresoc.v:178232$10873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176505$10808 + cell $not $not$libresoc.v:178233$10874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176505$10808_Y + connect \Y $not$libresoc.v:178233$10874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176506$10809 + cell $not $not$libresoc.v:178234$10875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176506$10809_Y + connect \Y $not$libresoc.v:178234$10875_Y end - attribute \src "libresoc.v:176426.7-176426.20" - process $proc$libresoc.v:176426$10887 + attribute \src "libresoc.v:178142.7-178142.20" + process $proc$libresoc.v:178142$10968 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176451.13-176451.30" - process $proc$libresoc.v:176451$10888 + attribute \src "libresoc.v:178161.13-178161.36" + process $proc$libresoc.v:178161$10969 + assign { } { } + assign $1\cr_pred1__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178176.13-178176.30" + process $proc$libresoc.v:178176$10970 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:176458.13-176458.31" - process $proc$libresoc.v:176458$10889 + attribute \src "libresoc.v:178183.13-178183.31" + process $proc$libresoc.v:178183$10971 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:176464.13-176464.25" - process $proc$libresoc.v:176464$10890 + attribute \src "libresoc.v:178189.13-178189.25" + process $proc$libresoc.v:178189$10972 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176469.13-176469.33" - process $proc$libresoc.v:176469$10891 + attribute \src "libresoc.v:178194.13-178194.33" + process $proc$libresoc.v:178194$10973 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:176476.13-176476.33" - process $proc$libresoc.v:176476$10892 + attribute \src "libresoc.v:178201.13-178201.33" + process $proc$libresoc.v:178201$10974 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:176483.13-176483.33" - process $proc$libresoc.v:176483$10893 + attribute \src "libresoc.v:178208.13-178208.33" + process $proc$libresoc.v:178208$10975 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:176507.3-176508.25" - process $proc$libresoc.v:176507$10810 + attribute \src "libresoc.v:178235.3-178236.25" + process $proc$libresoc.v:178235$10876 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176509.3-176510.39" - process $proc$libresoc.v:176509$10811 + attribute \src "libresoc.v:178237.3-178238.39" + process $proc$libresoc.v:178237$10877 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:176511.3-176512.37" - process $proc$libresoc.v:176511$10812 + attribute \src "libresoc.v:178239.3-178240.37" + process $proc$libresoc.v:178239$10878 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:176513.3-176514.43" - process $proc$libresoc.v:176513$10813 + attribute \src "libresoc.v:178241.3-178242.43" + process $proc$libresoc.v:178241$10879 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:176515.3-176516.43" - process $proc$libresoc.v:176515$10814 + attribute \src "libresoc.v:178243.3-178244.43" + process $proc$libresoc.v:178243$10880 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:176517.3-176518.43" - process $proc$libresoc.v:176517$10815 + attribute \src "libresoc.v:178245.3-178246.43" + process $proc$libresoc.v:178245$10881 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:176519.3-176558.6" - process $proc$libresoc.v:176519$10816 + attribute \src "libresoc.v:178247.3-178248.49" + process $proc$libresoc.v:178247$10882 + assign { } { } + assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next + sync posedge \coresync_clk + update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] + end + attribute \src "libresoc.v:178249.3-178288.6" + process $proc$libresoc.v:178249$10883 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10817 $6\src11__data_o$next[3:0]$10823 - attribute \src "libresoc.v:176520.5-176520.29" + assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 + attribute \src "libresoc.v:178250.5-178250.29" switch \initial - attribute \src "libresoc.v:176520.9-176520.17" + attribute \src "libresoc.v:178250.9-178250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \cr_pred1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10818 $5\src11__data_o$next[3:0]$10822 + assign $1\cr_pred1__data_o$next[3:0]$10885 $5\cr_pred1__data_o$next[3:0]$10889 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10819 \dest11__data_i + assign $2\cr_pred1__data_o$next[3:0]$10886 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10819 4'0000 + assign $2\cr_pred1__data_o$next[3:0]$10886 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10820 \dest21__data_i + assign $3\cr_pred1__data_o$next[3:0]$10887 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10820 $2\src11__data_o$next[3:0]$10819 + assign $3\cr_pred1__data_o$next[3:0]$10887 $2\cr_pred1__data_o$next[3:0]$10886 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10821 \w1__data_i + assign $4\cr_pred1__data_o$next[3:0]$10888 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10821 $3\src11__data_o$next[3:0]$10820 + assign $4\cr_pred1__data_o$next[3:0]$10888 $3\cr_pred1__data_o$next[3:0]$10887 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10822 \reg + assign $5\cr_pred1__data_o$next[3:0]$10889 \reg case - assign $5\src11__data_o$next[3:0]$10822 $4\src11__data_o$next[3:0]$10821 + assign $5\cr_pred1__data_o$next[3:0]$10889 $4\cr_pred1__data_o$next[3:0]$10888 end case - assign $1\src11__data_o$next[3:0]$10818 4'0000 + assign $1\cr_pred1__data_o$next[3:0]$10885 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10823 4'0000 + assign $6\cr_pred1__data_o$next[3:0]$10890 4'0000 case - assign $6\src11__data_o$next[3:0]$10823 $1\src11__data_o$next[3:0]$10818 + assign $6\cr_pred1__data_o$next[3:0]$10890 $1\cr_pred1__data_o$next[3:0]$10885 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10817 + update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 end - attribute \src "libresoc.v:176559.3-176588.6" - process $proc$libresoc.v:176559$10824 + attribute \src "libresoc.v:178289.3-178318.6" + process $proc$libresoc.v:178289$10891 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176560.5-176560.29" + attribute \src "libresoc.v:178290.5-178290.29" switch \initial - attribute \src "libresoc.v:176560.9-176560.17" + attribute \src "libresoc.v:178290.9-178290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + switch \cr_pred1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -363661,17 +366410,142 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176589.3-176615.6" - process $proc$libresoc.v:176589$10825 + attribute \src "libresoc.v:178319.3-178358.6" + process $proc$libresoc.v:178319$10892 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 + attribute \src "libresoc.v:178320.5-178320.29" + switch \initial + attribute \src "libresoc.v:178320.9-178320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10894 $5\r21__data_o$next[3:0]$10898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10895 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10895 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10896 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10896 $2\r21__data_o$next[3:0]$10895 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10897 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10897 $3\r21__data_o$next[3:0]$10896 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10898 \reg + case + assign $5\r21__data_o$next[3:0]$10898 $4\r21__data_o$next[3:0]$10897 + end + case + assign $1\r21__data_o$next[3:0]$10894 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10899 4'0000 + case + assign $6\r21__data_o$next[3:0]$10899 $1\r21__data_o$next[3:0]$10894 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 + end + attribute \src "libresoc.v:178359.3-178388.6" + process $proc$libresoc.v:178359$10900 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 + attribute \src "libresoc.v:178360.5-178360.29" + switch \initial + attribute \src "libresoc.v:178360.9-178360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$10902 $4\wr_detect$16[0:0]$10905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$10903 1'1 + case + assign $2\wr_detect$16[0:0]$10903 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$10904 1'1 + case + assign $3\wr_detect$16[0:0]$10904 $2\wr_detect$16[0:0]$10903 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$10905 1'1 + case + assign $4\wr_detect$16[0:0]$10905 $3\wr_detect$16[0:0]$10904 + end + case + assign $1\wr_detect$16[0:0]$10902 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$10901 + end + attribute \src "libresoc.v:178389.3-178415.6" + process $proc$libresoc.v:178389$10906 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10826 $4\reg$next[3:0]$10830 - attribute \src "libresoc.v:176590.5-176590.29" + assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 + attribute \src "libresoc.v:178390.5-178390.29" switch \initial - attribute \src "libresoc.v:176590.9-176590.17" + attribute \src "libresoc.v:178390.9-178390.17" case 1'1 case end @@ -363680,705 +366554,706 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10827 \dest11__data_i + assign $1\reg$next[3:0]$10908 \dest11__data_i case - assign $1\reg$next[3:0]$10827 \reg + assign $1\reg$next[3:0]$10908 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10828 \dest21__data_i + assign $2\reg$next[3:0]$10909 \dest21__data_i case - assign $2\reg$next[3:0]$10828 $1\reg$next[3:0]$10827 + assign $2\reg$next[3:0]$10909 $1\reg$next[3:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10829 \w1__data_i + assign $3\reg$next[3:0]$10910 \w1__data_i case - assign $3\reg$next[3:0]$10829 $2\reg$next[3:0]$10828 + assign $3\reg$next[3:0]$10910 $2\reg$next[3:0]$10909 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10830 4'0000 + assign $4\reg$next[3:0]$10911 4'0000 case - assign $4\reg$next[3:0]$10830 $3\reg$next[3:0]$10829 + assign $4\reg$next[3:0]$10911 $3\reg$next[3:0]$10910 end sync always - update \reg$next $0\reg$next[3:0]$10826 + update \reg$next $0\reg$next[3:0]$10907 end - attribute \src "libresoc.v:176616.3-176655.6" - process $proc$libresoc.v:176616$10831 + attribute \src "libresoc.v:178416.3-178455.6" + process $proc$libresoc.v:178416$10912 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10832 $6\src21__data_o$next[3:0]$10838 - attribute \src "libresoc.v:176617.5-176617.29" + assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 + attribute \src "libresoc.v:178417.5-178417.29" switch \initial - attribute \src "libresoc.v:176617.9-176617.17" + attribute \src "libresoc.v:178417.9-178417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10833 $5\src21__data_o$next[3:0]$10837 + assign $1\src11__data_o$next[3:0]$10914 $5\src11__data_o$next[3:0]$10918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10834 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10915 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10834 4'0000 + assign $2\src11__data_o$next[3:0]$10915 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10835 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10916 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10835 $2\src21__data_o$next[3:0]$10834 + assign $3\src11__data_o$next[3:0]$10916 $2\src11__data_o$next[3:0]$10915 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10836 \w1__data_i + assign $4\src11__data_o$next[3:0]$10917 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10836 $3\src21__data_o$next[3:0]$10835 + assign $4\src11__data_o$next[3:0]$10917 $3\src11__data_o$next[3:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10837 \reg + assign $5\src11__data_o$next[3:0]$10918 \reg case - assign $5\src21__data_o$next[3:0]$10837 $4\src21__data_o$next[3:0]$10836 + assign $5\src11__data_o$next[3:0]$10918 $4\src11__data_o$next[3:0]$10917 end case - assign $1\src21__data_o$next[3:0]$10833 4'0000 + assign $1\src11__data_o$next[3:0]$10914 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10838 4'0000 + assign $6\src11__data_o$next[3:0]$10919 4'0000 case - assign $6\src21__data_o$next[3:0]$10838 $1\src21__data_o$next[3:0]$10833 + assign $6\src11__data_o$next[3:0]$10919 $1\src11__data_o$next[3:0]$10914 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10832 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 end - attribute \src "libresoc.v:176656.3-176685.6" - process $proc$libresoc.v:176656$10839 + attribute \src "libresoc.v:178456.3-178485.6" + process $proc$libresoc.v:178456$10920 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10840 $1\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:176657.5-176657.29" + assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 + attribute \src "libresoc.v:178457.5-178457.29" switch \initial - attribute \src "libresoc.v:176657.9-176657.17" + attribute \src "libresoc.v:178457.9-178457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10844 + assign $1\wr_detect$4[0:0]$10922 $4\wr_detect$4[0:0]$10925 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10842 1'1 + assign $2\wr_detect$4[0:0]$10923 1'1 case - assign $2\wr_detect$4[0:0]$10842 1'0 + assign $2\wr_detect$4[0:0]$10923 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10843 1'1 + assign $3\wr_detect$4[0:0]$10924 1'1 case - assign $3\wr_detect$4[0:0]$10843 $2\wr_detect$4[0:0]$10842 + assign $3\wr_detect$4[0:0]$10924 $2\wr_detect$4[0:0]$10923 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10844 1'1 + assign $4\wr_detect$4[0:0]$10925 1'1 case - assign $4\wr_detect$4[0:0]$10844 $3\wr_detect$4[0:0]$10843 + assign $4\wr_detect$4[0:0]$10925 $3\wr_detect$4[0:0]$10924 end case - assign $1\wr_detect$4[0:0]$10841 1'0 + assign $1\wr_detect$4[0:0]$10922 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10840 + update \wr_detect$4 $0\wr_detect$4[0:0]$10921 end - attribute \src "libresoc.v:176686.3-176725.6" - process $proc$libresoc.v:176686$10845 + attribute \src "libresoc.v:178486.3-178525.6" + process $proc$libresoc.v:178486$10926 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10846 $6\src31__data_o$next[3:0]$10852 - attribute \src "libresoc.v:176687.5-176687.29" + assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 + attribute \src "libresoc.v:178487.5-178487.29" switch \initial - attribute \src "libresoc.v:176687.9-176687.17" + attribute \src "libresoc.v:178487.9-178487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10847 $5\src31__data_o$next[3:0]$10851 + assign $1\src21__data_o$next[3:0]$10928 $5\src21__data_o$next[3:0]$10932 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10848 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10929 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10848 4'0000 + assign $2\src21__data_o$next[3:0]$10929 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10849 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10930 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10849 $2\src31__data_o$next[3:0]$10848 + assign $3\src21__data_o$next[3:0]$10930 $2\src21__data_o$next[3:0]$10929 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10850 \w1__data_i + assign $4\src21__data_o$next[3:0]$10931 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10850 $3\src31__data_o$next[3:0]$10849 + assign $4\src21__data_o$next[3:0]$10931 $3\src21__data_o$next[3:0]$10930 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10851 \reg + assign $5\src21__data_o$next[3:0]$10932 \reg case - assign $5\src31__data_o$next[3:0]$10851 $4\src31__data_o$next[3:0]$10850 + assign $5\src21__data_o$next[3:0]$10932 $4\src21__data_o$next[3:0]$10931 end case - assign $1\src31__data_o$next[3:0]$10847 4'0000 + assign $1\src21__data_o$next[3:0]$10928 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10852 4'0000 + assign $6\src21__data_o$next[3:0]$10933 4'0000 case - assign $6\src31__data_o$next[3:0]$10852 $1\src31__data_o$next[3:0]$10847 + assign $6\src21__data_o$next[3:0]$10933 $1\src21__data_o$next[3:0]$10928 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10846 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 end - attribute \src "libresoc.v:176726.3-176755.6" - process $proc$libresoc.v:176726$10853 + attribute \src "libresoc.v:178526.3-178555.6" + process $proc$libresoc.v:178526$10934 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10854 $1\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:176727.5-176727.29" + assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 + attribute \src "libresoc.v:178527.5-178527.29" switch \initial - attribute \src "libresoc.v:176727.9-176727.17" + attribute \src "libresoc.v:178527.9-178527.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10855 $4\wr_detect$7[0:0]$10858 + assign $1\wr_detect$7[0:0]$10936 $4\wr_detect$7[0:0]$10939 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10856 1'1 + assign $2\wr_detect$7[0:0]$10937 1'1 case - assign $2\wr_detect$7[0:0]$10856 1'0 + assign $2\wr_detect$7[0:0]$10937 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10857 1'1 + assign $3\wr_detect$7[0:0]$10938 1'1 case - assign $3\wr_detect$7[0:0]$10857 $2\wr_detect$7[0:0]$10856 + assign $3\wr_detect$7[0:0]$10938 $2\wr_detect$7[0:0]$10937 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10858 1'1 + assign $4\wr_detect$7[0:0]$10939 1'1 case - assign $4\wr_detect$7[0:0]$10858 $3\wr_detect$7[0:0]$10857 + assign $4\wr_detect$7[0:0]$10939 $3\wr_detect$7[0:0]$10938 end case - assign $1\wr_detect$7[0:0]$10855 1'0 + assign $1\wr_detect$7[0:0]$10936 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10854 + update \wr_detect$7 $0\wr_detect$7[0:0]$10935 end - attribute \src "libresoc.v:176756.3-176795.6" - process $proc$libresoc.v:176756$10859 + attribute \src "libresoc.v:178556.3-178595.6" + process $proc$libresoc.v:178556$10940 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10860 $6\r1__data_o$next[3:0]$10866 - attribute \src "libresoc.v:176757.5-176757.29" + assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 + attribute \src "libresoc.v:178557.5-178557.29" switch \initial - attribute \src "libresoc.v:176757.9-176757.17" + attribute \src "libresoc.v:178557.9-178557.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10861 $5\r1__data_o$next[3:0]$10865 + assign $1\src31__data_o$next[3:0]$10942 $5\src31__data_o$next[3:0]$10946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10862 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10943 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10862 4'0000 + assign $2\src31__data_o$next[3:0]$10943 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10863 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10944 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10863 $2\r1__data_o$next[3:0]$10862 + assign $3\src31__data_o$next[3:0]$10944 $2\src31__data_o$next[3:0]$10943 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10864 \w1__data_i + assign $4\src31__data_o$next[3:0]$10945 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10864 $3\r1__data_o$next[3:0]$10863 + assign $4\src31__data_o$next[3:0]$10945 $3\src31__data_o$next[3:0]$10944 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10865 \reg + assign $5\src31__data_o$next[3:0]$10946 \reg case - assign $5\r1__data_o$next[3:0]$10865 $4\r1__data_o$next[3:0]$10864 + assign $5\src31__data_o$next[3:0]$10946 $4\src31__data_o$next[3:0]$10945 end case - assign $1\r1__data_o$next[3:0]$10861 4'0000 + assign $1\src31__data_o$next[3:0]$10942 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10866 4'0000 + assign $6\src31__data_o$next[3:0]$10947 4'0000 case - assign $6\r1__data_o$next[3:0]$10866 $1\r1__data_o$next[3:0]$10861 + assign $6\src31__data_o$next[3:0]$10947 $1\src31__data_o$next[3:0]$10942 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10860 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 end - attribute \src "libresoc.v:176796.3-176825.6" - process $proc$libresoc.v:176796$10867 + attribute \src "libresoc.v:178596.3-178625.6" + process $proc$libresoc.v:178596$10948 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10868 $1\wr_detect$10[0:0]$10869 - attribute \src "libresoc.v:176797.5-176797.29" + assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 + attribute \src "libresoc.v:178597.5-178597.29" switch \initial - attribute \src "libresoc.v:176797.9-176797.17" + attribute \src "libresoc.v:178597.9-178597.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10869 $4\wr_detect$10[0:0]$10872 + assign $1\wr_detect$10[0:0]$10950 $4\wr_detect$10[0:0]$10953 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10870 1'1 + assign $2\wr_detect$10[0:0]$10951 1'1 case - assign $2\wr_detect$10[0:0]$10870 1'0 + assign $2\wr_detect$10[0:0]$10951 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10871 1'1 + assign $3\wr_detect$10[0:0]$10952 1'1 case - assign $3\wr_detect$10[0:0]$10871 $2\wr_detect$10[0:0]$10870 + assign $3\wr_detect$10[0:0]$10952 $2\wr_detect$10[0:0]$10951 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10872 1'1 + assign $4\wr_detect$10[0:0]$10953 1'1 case - assign $4\wr_detect$10[0:0]$10872 $3\wr_detect$10[0:0]$10871 + assign $4\wr_detect$10[0:0]$10953 $3\wr_detect$10[0:0]$10952 end case - assign $1\wr_detect$10[0:0]$10869 1'0 + assign $1\wr_detect$10[0:0]$10950 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10868 + update \wr_detect$10 $0\wr_detect$10[0:0]$10949 end - attribute \src "libresoc.v:176826.3-176865.6" - process $proc$libresoc.v:176826$10873 + attribute \src "libresoc.v:178626.3-178665.6" + process $proc$libresoc.v:178626$10954 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10874 $6\r21__data_o$next[3:0]$10880 - attribute \src "libresoc.v:176827.5-176827.29" + assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 + attribute \src "libresoc.v:178627.5-178627.29" switch \initial - attribute \src "libresoc.v:176827.9-176827.17" + attribute \src "libresoc.v:178627.9-178627.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10875 $5\r21__data_o$next[3:0]$10879 + assign $1\r1__data_o$next[3:0]$10956 $5\r1__data_o$next[3:0]$10960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10876 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10957 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10876 4'0000 + assign $2\r1__data_o$next[3:0]$10957 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10877 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10958 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10877 $2\r21__data_o$next[3:0]$10876 + assign $3\r1__data_o$next[3:0]$10958 $2\r1__data_o$next[3:0]$10957 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10878 \w1__data_i + assign $4\r1__data_o$next[3:0]$10959 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10878 $3\r21__data_o$next[3:0]$10877 + assign $4\r1__data_o$next[3:0]$10959 $3\r1__data_o$next[3:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10879 \reg + assign $5\r1__data_o$next[3:0]$10960 \reg case - assign $5\r21__data_o$next[3:0]$10879 $4\r21__data_o$next[3:0]$10878 + assign $5\r1__data_o$next[3:0]$10960 $4\r1__data_o$next[3:0]$10959 end case - assign $1\r21__data_o$next[3:0]$10875 4'0000 + assign $1\r1__data_o$next[3:0]$10956 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10880 4'0000 + assign $6\r1__data_o$next[3:0]$10961 4'0000 case - assign $6\r21__data_o$next[3:0]$10880 $1\r21__data_o$next[3:0]$10875 + assign $6\r1__data_o$next[3:0]$10961 $1\r1__data_o$next[3:0]$10956 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10874 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 end - attribute \src "libresoc.v:176866.3-176895.6" - process $proc$libresoc.v:176866$10881 + attribute \src "libresoc.v:178666.3-178695.6" + process $proc$libresoc.v:178666$10962 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10882 $1\wr_detect$13[0:0]$10883 - attribute \src "libresoc.v:176867.5-176867.29" + assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 + attribute \src "libresoc.v:178667.5-178667.29" switch \initial - attribute \src "libresoc.v:176867.9-176867.17" + attribute \src "libresoc.v:178667.9-178667.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10883 $4\wr_detect$13[0:0]$10886 + assign $1\wr_detect$13[0:0]$10964 $4\wr_detect$13[0:0]$10967 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10884 1'1 + assign $2\wr_detect$13[0:0]$10965 1'1 case - assign $2\wr_detect$13[0:0]$10884 1'0 + assign $2\wr_detect$13[0:0]$10965 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10885 1'1 + assign $3\wr_detect$13[0:0]$10966 1'1 case - assign $3\wr_detect$13[0:0]$10885 $2\wr_detect$13[0:0]$10884 + assign $3\wr_detect$13[0:0]$10966 $2\wr_detect$13[0:0]$10965 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10886 1'1 + assign $4\wr_detect$13[0:0]$10967 1'1 case - assign $4\wr_detect$13[0:0]$10886 $3\wr_detect$13[0:0]$10885 + assign $4\wr_detect$13[0:0]$10967 $3\wr_detect$13[0:0]$10966 end case - assign $1\wr_detect$13[0:0]$10883 1'0 + assign $1\wr_detect$13[0:0]$10964 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10882 + update \wr_detect$13 $0\wr_detect$13[0:0]$10963 end - connect \$9 $not$libresoc.v:176502$10805_Y - connect \$12 $not$libresoc.v:176503$10806_Y - connect \$1 $not$libresoc.v:176504$10807_Y - connect \$3 $not$libresoc.v:176505$10808_Y - connect \$6 $not$libresoc.v:176506$10809_Y + connect \$9 $not$libresoc.v:178229$10870_Y + connect \$12 $not$libresoc.v:178230$10871_Y + connect \$15 $not$libresoc.v:178231$10872_Y + connect \$1 $not$libresoc.v:178232$10873_Y + connect \$3 $not$libresoc.v:178233$10874_Y + connect \$6 $not$libresoc.v:178234$10875_Y end -attribute \src "libresoc.v:176900.1-177345.10" +attribute \src "libresoc.v:178700.1-179145.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:176901.7-176901.20" + attribute \src "libresoc.v:178701.7-178701.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $0\r1__data_o$next[1:0]$10946 - attribute \src "libresoc.v:176976.3-176977.37" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $0\r1__data_o$next[1:0]$11028 + attribute \src "libresoc.v:178776.3-178777.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $0\reg$next[1:0]$10962 - attribute \src "libresoc.v:176974.3-176975.25" + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $0\reg$next[1:0]$11044 + attribute \src "libresoc.v:178774.3-178775.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $0\src11__data_o$next[1:0]$10904 - attribute \src "libresoc.v:176982.3-176983.43" + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $0\src11__data_o$next[1:0]$10986 + attribute \src "libresoc.v:178782.3-178783.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $0\src21__data_o$next[1:0]$10914 - attribute \src "libresoc.v:176980.3-176981.43" + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $0\src21__data_o$next[1:0]$10996 + attribute \src "libresoc.v:178780.3-178781.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $0\src31__data_o$next[1:0]$10930 - attribute \src "libresoc.v:176978.3-176979.43" + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $0\src31__data_o$next[1:0]$11012 + attribute \src "libresoc.v:178778.3-178779.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:177276.3-177311.6" - wire $0\wr_detect$10[0:0]$10955 - attribute \src "libresoc.v:177112.3-177147.6" - wire $0\wr_detect$4[0:0]$10923 - attribute \src "libresoc.v:177194.3-177229.6" - wire $0\wr_detect$7[0:0]$10939 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179076.3-179111.6" + wire $0\wr_detect$10[0:0]$11037 + attribute \src "libresoc.v:178912.3-178947.6" + wire $0\wr_detect$4[0:0]$11005 + attribute \src "libresoc.v:178994.3-179029.6" + wire $0\wr_detect$7[0:0]$11021 + attribute \src "libresoc.v:178830.3-178865.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $1\r1__data_o$next[1:0]$10947 - attribute \src "libresoc.v:176928.13-176928.30" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $1\r1__data_o$next[1:0]$11029 + attribute \src "libresoc.v:178728.13-178728.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $1\reg$next[1:0]$10963 - attribute \src "libresoc.v:176934.13-176934.25" + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $1\reg$next[1:0]$11045 + attribute \src "libresoc.v:178734.13-178734.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $1\src11__data_o$next[1:0]$10905 - attribute \src "libresoc.v:176939.13-176939.33" + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $1\src11__data_o$next[1:0]$10987 + attribute \src "libresoc.v:178739.13-178739.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $1\src21__data_o$next[1:0]$10915 - attribute \src "libresoc.v:176946.13-176946.33" + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $1\src21__data_o$next[1:0]$10997 + attribute \src "libresoc.v:178746.13-178746.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $1\src31__data_o$next[1:0]$10931 - attribute \src "libresoc.v:176953.13-176953.33" + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $1\src31__data_o$next[1:0]$11013 + attribute \src "libresoc.v:178753.13-178753.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:177276.3-177311.6" - wire $1\wr_detect$10[0:0]$10956 - attribute \src "libresoc.v:177112.3-177147.6" - wire $1\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:177194.3-177229.6" - wire $1\wr_detect$7[0:0]$10940 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179076.3-179111.6" + wire $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:178912.3-178947.6" + wire $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178994.3-179029.6" + wire $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178830.3-178865.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $2\r1__data_o$next[1:0]$10948 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $2\reg$next[1:0]$10964 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $2\src11__data_o$next[1:0]$10906 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $2\src21__data_o$next[1:0]$10916 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $2\src31__data_o$next[1:0]$10932 - attribute \src "libresoc.v:177276.3-177311.6" - wire $2\wr_detect$10[0:0]$10957 - attribute \src "libresoc.v:177112.3-177147.6" - wire $2\wr_detect$4[0:0]$10925 - attribute \src "libresoc.v:177194.3-177229.6" - wire $2\wr_detect$7[0:0]$10941 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $2\r1__data_o$next[1:0]$11030 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $2\reg$next[1:0]$11046 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $2\src11__data_o$next[1:0]$10988 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $2\src21__data_o$next[1:0]$10998 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $2\src31__data_o$next[1:0]$11014 + attribute \src "libresoc.v:179076.3-179111.6" + wire $2\wr_detect$10[0:0]$11039 + attribute \src "libresoc.v:178912.3-178947.6" + wire $2\wr_detect$4[0:0]$11007 + attribute \src "libresoc.v:178994.3-179029.6" + wire $2\wr_detect$7[0:0]$11023 + attribute \src "libresoc.v:178830.3-178865.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $3\r1__data_o$next[1:0]$10949 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $3\reg$next[1:0]$10965 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $3\src11__data_o$next[1:0]$10907 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $3\src21__data_o$next[1:0]$10917 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $3\src31__data_o$next[1:0]$10933 - attribute \src "libresoc.v:177276.3-177311.6" - wire $3\wr_detect$10[0:0]$10958 - attribute \src "libresoc.v:177112.3-177147.6" - wire $3\wr_detect$4[0:0]$10926 - attribute \src "libresoc.v:177194.3-177229.6" - wire $3\wr_detect$7[0:0]$10942 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $3\r1__data_o$next[1:0]$11031 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $3\reg$next[1:0]$11047 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $3\src11__data_o$next[1:0]$10989 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $3\src21__data_o$next[1:0]$10999 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $3\src31__data_o$next[1:0]$11015 + attribute \src "libresoc.v:179076.3-179111.6" + wire $3\wr_detect$10[0:0]$11040 + attribute \src "libresoc.v:178912.3-178947.6" + wire $3\wr_detect$4[0:0]$11008 + attribute \src "libresoc.v:178994.3-179029.6" + wire $3\wr_detect$7[0:0]$11024 + attribute \src "libresoc.v:178830.3-178865.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $4\r1__data_o$next[1:0]$10950 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $4\reg$next[1:0]$10966 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $4\src11__data_o$next[1:0]$10908 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $4\src21__data_o$next[1:0]$10918 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $4\src31__data_o$next[1:0]$10934 - attribute \src "libresoc.v:177276.3-177311.6" - wire $4\wr_detect$10[0:0]$10959 - attribute \src "libresoc.v:177112.3-177147.6" - wire $4\wr_detect$4[0:0]$10927 - attribute \src "libresoc.v:177194.3-177229.6" - wire $4\wr_detect$7[0:0]$10943 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $4\r1__data_o$next[1:0]$11032 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $4\reg$next[1:0]$11048 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $4\src11__data_o$next[1:0]$10990 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $4\src21__data_o$next[1:0]$11000 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $4\src31__data_o$next[1:0]$11016 + attribute \src "libresoc.v:179076.3-179111.6" + wire $4\wr_detect$10[0:0]$11041 + attribute \src "libresoc.v:178912.3-178947.6" + wire $4\wr_detect$4[0:0]$11009 + attribute \src "libresoc.v:178994.3-179029.6" + wire $4\wr_detect$7[0:0]$11025 + attribute \src "libresoc.v:178830.3-178865.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $5\r1__data_o$next[1:0]$10951 - attribute \src "libresoc.v:177312.3-177344.6" - wire width 2 $5\reg$next[1:0]$10967 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $5\src11__data_o$next[1:0]$10909 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $5\src21__data_o$next[1:0]$10919 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $5\src31__data_o$next[1:0]$10935 - attribute \src "libresoc.v:177276.3-177311.6" - wire $5\wr_detect$10[0:0]$10960 - attribute \src "libresoc.v:177112.3-177147.6" - wire $5\wr_detect$4[0:0]$10928 - attribute \src "libresoc.v:177194.3-177229.6" - wire $5\wr_detect$7[0:0]$10944 - attribute \src "libresoc.v:177030.3-177065.6" + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $5\r1__data_o$next[1:0]$11033 + attribute \src "libresoc.v:179112.3-179144.6" + wire width 2 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $5\src11__data_o$next[1:0]$10991 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $5\src21__data_o$next[1:0]$11001 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $5\src31__data_o$next[1:0]$11017 + attribute \src "libresoc.v:179076.3-179111.6" + wire $5\wr_detect$10[0:0]$11042 + attribute \src "libresoc.v:178912.3-178947.6" + wire $5\wr_detect$4[0:0]$11010 + attribute \src "libresoc.v:178994.3-179029.6" + wire $5\wr_detect$7[0:0]$11026 + attribute \src "libresoc.v:178830.3-178865.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $6\r1__data_o$next[1:0]$10952 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $6\src11__data_o$next[1:0]$10910 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $6\src21__data_o$next[1:0]$10920 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $6\src31__data_o$next[1:0]$10936 - attribute \src "libresoc.v:177230.3-177275.6" - wire width 2 $7\r1__data_o$next[1:0]$10953 - attribute \src "libresoc.v:176984.3-177029.6" - wire width 2 $7\src11__data_o$next[1:0]$10911 - attribute \src "libresoc.v:177066.3-177111.6" - wire width 2 $7\src21__data_o$next[1:0]$10921 - attribute \src "libresoc.v:177148.3-177193.6" - wire width 2 $7\src31__data_o$next[1:0]$10937 - attribute \src "libresoc.v:176970.17-176970.104" - wire $not$libresoc.v:176970$10894_Y - attribute \src "libresoc.v:176971.17-176971.100" - wire $not$libresoc.v:176971$10895_Y - attribute \src "libresoc.v:176972.17-176972.103" - wire $not$libresoc.v:176972$10896_Y - attribute \src "libresoc.v:176973.17-176973.103" - wire $not$libresoc.v:176973$10897_Y + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $6\r1__data_o$next[1:0]$11034 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $6\src11__data_o$next[1:0]$10992 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $6\src21__data_o$next[1:0]$11002 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $6\src31__data_o$next[1:0]$11018 + attribute \src "libresoc.v:179030.3-179075.6" + wire width 2 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:178784.3-178829.6" + wire width 2 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178866.3-178911.6" + wire width 2 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178948.3-178993.6" + wire width 2 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178770.17-178770.104" + wire $not$libresoc.v:178770$10976_Y + attribute \src "libresoc.v:178771.17-178771.100" + wire $not$libresoc.v:178771$10977_Y + attribute \src "libresoc.v:178772.17-178772.103" + wire $not$libresoc.v:178772$10978_Y + attribute \src "libresoc.v:178773.17-178773.103" + wire $not$libresoc.v:178773$10979_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364387,9 +367262,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -364403,7 +367278,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:176901.7-176901.15" + attribute \src "libresoc.v:178701.7-178701.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -364446,129 +367321,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176970$10894 + cell $not $not$libresoc.v:178770$10976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176970$10894_Y + connect \Y $not$libresoc.v:178770$10976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176971$10895 + cell $not $not$libresoc.v:178771$10977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176971$10895_Y + connect \Y $not$libresoc.v:178771$10977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176972$10896 + cell $not $not$libresoc.v:178772$10978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176972$10896_Y + connect \Y $not$libresoc.v:178772$10978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176973$10897 + cell $not $not$libresoc.v:178773$10979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176973$10897_Y + connect \Y $not$libresoc.v:178773$10979_Y end - attribute \src "libresoc.v:176901.7-176901.20" - process $proc$libresoc.v:176901$10968 + attribute \src "libresoc.v:178701.7-178701.20" + process $proc$libresoc.v:178701$11050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176928.13-176928.30" - process $proc$libresoc.v:176928$10969 + attribute \src "libresoc.v:178728.13-178728.30" + process $proc$libresoc.v:178728$11051 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:176934.13-176934.25" - process $proc$libresoc.v:176934$10970 + attribute \src "libresoc.v:178734.13-178734.25" + process $proc$libresoc.v:178734$11052 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:176939.13-176939.33" - process $proc$libresoc.v:176939$10971 + attribute \src "libresoc.v:178739.13-178739.33" + process $proc$libresoc.v:178739$11053 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:176946.13-176946.33" - process $proc$libresoc.v:176946$10972 + attribute \src "libresoc.v:178746.13-178746.33" + process $proc$libresoc.v:178746$11054 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:176953.13-176953.33" - process $proc$libresoc.v:176953$10973 + attribute \src "libresoc.v:178753.13-178753.33" + process $proc$libresoc.v:178753$11055 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:176974.3-176975.25" - process $proc$libresoc.v:176974$10898 + attribute \src "libresoc.v:178774.3-178775.25" + process $proc$libresoc.v:178774$10980 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:176976.3-176977.37" - process $proc$libresoc.v:176976$10899 + attribute \src "libresoc.v:178776.3-178777.37" + process $proc$libresoc.v:178776$10981 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:176978.3-176979.43" - process $proc$libresoc.v:176978$10900 + attribute \src "libresoc.v:178778.3-178779.43" + process $proc$libresoc.v:178778$10982 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:176980.3-176981.43" - process $proc$libresoc.v:176980$10901 + attribute \src "libresoc.v:178780.3-178781.43" + process $proc$libresoc.v:178780$10983 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:176982.3-176983.43" - process $proc$libresoc.v:176982$10902 + attribute \src "libresoc.v:178782.3-178783.43" + process $proc$libresoc.v:178782$10984 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:176984.3-177029.6" - process $proc$libresoc.v:176984$10903 + attribute \src "libresoc.v:178784.3-178829.6" + process $proc$libresoc.v:178784$10985 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10904 $7\src11__data_o$next[1:0]$10911 - attribute \src "libresoc.v:176985.5-176985.29" + assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 + attribute \src "libresoc.v:178785.5-178785.29" switch \initial - attribute \src "libresoc.v:176985.9-176985.17" + attribute \src "libresoc.v:178785.9-178785.17" case 1'1 case end @@ -364581,75 +367456,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10905 $6\src11__data_o$next[1:0]$10910 + assign $1\src11__data_o$next[1:0]$10987 $6\src11__data_o$next[1:0]$10992 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10906 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10988 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10906 2'00 + assign $2\src11__data_o$next[1:0]$10988 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10907 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10989 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10907 $2\src11__data_o$next[1:0]$10906 + assign $3\src11__data_o$next[1:0]$10989 $2\src11__data_o$next[1:0]$10988 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10908 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10990 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10908 $3\src11__data_o$next[1:0]$10907 + assign $4\src11__data_o$next[1:0]$10990 $3\src11__data_o$next[1:0]$10989 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10909 \w1__data_i + assign $5\src11__data_o$next[1:0]$10991 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10909 $4\src11__data_o$next[1:0]$10908 + assign $5\src11__data_o$next[1:0]$10991 $4\src11__data_o$next[1:0]$10990 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10910 \reg + assign $6\src11__data_o$next[1:0]$10992 \reg case - assign $6\src11__data_o$next[1:0]$10910 $5\src11__data_o$next[1:0]$10909 + assign $6\src11__data_o$next[1:0]$10992 $5\src11__data_o$next[1:0]$10991 end case - assign $1\src11__data_o$next[1:0]$10905 2'00 + assign $1\src11__data_o$next[1:0]$10987 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10911 2'00 + assign $7\src11__data_o$next[1:0]$10993 2'00 case - assign $7\src11__data_o$next[1:0]$10911 $1\src11__data_o$next[1:0]$10905 + assign $7\src11__data_o$next[1:0]$10993 $1\src11__data_o$next[1:0]$10987 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10904 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 end - attribute \src "libresoc.v:177030.3-177065.6" - process $proc$libresoc.v:177030$10912 + attribute \src "libresoc.v:178830.3-178865.6" + process $proc$libresoc.v:178830$10994 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177031.5-177031.29" + attribute \src "libresoc.v:178831.5-178831.29" switch \initial - attribute \src "libresoc.v:177031.9-177031.17" + attribute \src "libresoc.v:178831.9-178831.17" case 1'1 case end @@ -364705,15 +367580,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177066.3-177111.6" - process $proc$libresoc.v:177066$10913 + attribute \src "libresoc.v:178866.3-178911.6" + process $proc$libresoc.v:178866$10995 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10914 $7\src21__data_o$next[1:0]$10921 - attribute \src "libresoc.v:177067.5-177067.29" + assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 + attribute \src "libresoc.v:178867.5-178867.29" switch \initial - attribute \src "libresoc.v:177067.9-177067.17" + attribute \src "libresoc.v:178867.9-178867.17" case 1'1 case end @@ -364726,75 +367601,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10915 $6\src21__data_o$next[1:0]$10920 + assign $1\src21__data_o$next[1:0]$10997 $6\src21__data_o$next[1:0]$11002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10916 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10998 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10916 2'00 + assign $2\src21__data_o$next[1:0]$10998 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10917 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10999 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10917 $2\src21__data_o$next[1:0]$10916 + assign $3\src21__data_o$next[1:0]$10999 $2\src21__data_o$next[1:0]$10998 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10918 \dest31__data_i + assign $4\src21__data_o$next[1:0]$11000 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10918 $3\src21__data_o$next[1:0]$10917 + assign $4\src21__data_o$next[1:0]$11000 $3\src21__data_o$next[1:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10919 \w1__data_i + assign $5\src21__data_o$next[1:0]$11001 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10919 $4\src21__data_o$next[1:0]$10918 + assign $5\src21__data_o$next[1:0]$11001 $4\src21__data_o$next[1:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10920 \reg + assign $6\src21__data_o$next[1:0]$11002 \reg case - assign $6\src21__data_o$next[1:0]$10920 $5\src21__data_o$next[1:0]$10919 + assign $6\src21__data_o$next[1:0]$11002 $5\src21__data_o$next[1:0]$11001 end case - assign $1\src21__data_o$next[1:0]$10915 2'00 + assign $1\src21__data_o$next[1:0]$10997 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10921 2'00 + assign $7\src21__data_o$next[1:0]$11003 2'00 case - assign $7\src21__data_o$next[1:0]$10921 $1\src21__data_o$next[1:0]$10915 + assign $7\src21__data_o$next[1:0]$11003 $1\src21__data_o$next[1:0]$10997 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10914 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 end - attribute \src "libresoc.v:177112.3-177147.6" - process $proc$libresoc.v:177112$10922 + attribute \src "libresoc.v:178912.3-178947.6" + process $proc$libresoc.v:178912$11004 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10923 $1\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:177113.5-177113.29" + assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 + attribute \src "libresoc.v:178913.5-178913.29" switch \initial - attribute \src "libresoc.v:177113.9-177113.17" + attribute \src "libresoc.v:178913.9-178913.17" case 1'1 case end @@ -364807,58 +367682,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10924 $5\wr_detect$4[0:0]$10928 + assign $1\wr_detect$4[0:0]$11006 $5\wr_detect$4[0:0]$11010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10925 1'1 + assign $2\wr_detect$4[0:0]$11007 1'1 case - assign $2\wr_detect$4[0:0]$10925 1'0 + assign $2\wr_detect$4[0:0]$11007 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10926 1'1 + assign $3\wr_detect$4[0:0]$11008 1'1 case - assign $3\wr_detect$4[0:0]$10926 $2\wr_detect$4[0:0]$10925 + assign $3\wr_detect$4[0:0]$11008 $2\wr_detect$4[0:0]$11007 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10927 1'1 + assign $4\wr_detect$4[0:0]$11009 1'1 case - assign $4\wr_detect$4[0:0]$10927 $3\wr_detect$4[0:0]$10926 + assign $4\wr_detect$4[0:0]$11009 $3\wr_detect$4[0:0]$11008 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10928 1'1 + assign $5\wr_detect$4[0:0]$11010 1'1 case - assign $5\wr_detect$4[0:0]$10928 $4\wr_detect$4[0:0]$10927 + assign $5\wr_detect$4[0:0]$11010 $4\wr_detect$4[0:0]$11009 end case - assign $1\wr_detect$4[0:0]$10924 1'0 + assign $1\wr_detect$4[0:0]$11006 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10923 + update \wr_detect$4 $0\wr_detect$4[0:0]$11005 end - attribute \src "libresoc.v:177148.3-177193.6" - process $proc$libresoc.v:177148$10929 + attribute \src "libresoc.v:178948.3-178993.6" + process $proc$libresoc.v:178948$11011 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10930 $7\src31__data_o$next[1:0]$10937 - attribute \src "libresoc.v:177149.5-177149.29" + assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 + attribute \src "libresoc.v:178949.5-178949.29" switch \initial - attribute \src "libresoc.v:177149.9-177149.17" + attribute \src "libresoc.v:178949.9-178949.17" case 1'1 case end @@ -364871,75 +367746,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10931 $6\src31__data_o$next[1:0]$10936 + assign $1\src31__data_o$next[1:0]$11013 $6\src31__data_o$next[1:0]$11018 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10932 \dest11__data_i + assign $2\src31__data_o$next[1:0]$11014 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10932 2'00 + assign $2\src31__data_o$next[1:0]$11014 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10933 \dest21__data_i + assign $3\src31__data_o$next[1:0]$11015 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10933 $2\src31__data_o$next[1:0]$10932 + assign $3\src31__data_o$next[1:0]$11015 $2\src31__data_o$next[1:0]$11014 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10934 \dest31__data_i + assign $4\src31__data_o$next[1:0]$11016 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10934 $3\src31__data_o$next[1:0]$10933 + assign $4\src31__data_o$next[1:0]$11016 $3\src31__data_o$next[1:0]$11015 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10935 \w1__data_i + assign $5\src31__data_o$next[1:0]$11017 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10935 $4\src31__data_o$next[1:0]$10934 + assign $5\src31__data_o$next[1:0]$11017 $4\src31__data_o$next[1:0]$11016 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10936 \reg + assign $6\src31__data_o$next[1:0]$11018 \reg case - assign $6\src31__data_o$next[1:0]$10936 $5\src31__data_o$next[1:0]$10935 + assign $6\src31__data_o$next[1:0]$11018 $5\src31__data_o$next[1:0]$11017 end case - assign $1\src31__data_o$next[1:0]$10931 2'00 + assign $1\src31__data_o$next[1:0]$11013 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10937 2'00 + assign $7\src31__data_o$next[1:0]$11019 2'00 case - assign $7\src31__data_o$next[1:0]$10937 $1\src31__data_o$next[1:0]$10931 + assign $7\src31__data_o$next[1:0]$11019 $1\src31__data_o$next[1:0]$11013 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10930 + update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 end - attribute \src "libresoc.v:177194.3-177229.6" - process $proc$libresoc.v:177194$10938 + attribute \src "libresoc.v:178994.3-179029.6" + process $proc$libresoc.v:178994$11020 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10939 $1\wr_detect$7[0:0]$10940 - attribute \src "libresoc.v:177195.5-177195.29" + assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 + attribute \src "libresoc.v:178995.5-178995.29" switch \initial - attribute \src "libresoc.v:177195.9-177195.17" + attribute \src "libresoc.v:178995.9-178995.17" case 1'1 case end @@ -364952,58 +367827,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10940 $5\wr_detect$7[0:0]$10944 + assign $1\wr_detect$7[0:0]$11022 $5\wr_detect$7[0:0]$11026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10941 1'1 + assign $2\wr_detect$7[0:0]$11023 1'1 case - assign $2\wr_detect$7[0:0]$10941 1'0 + assign $2\wr_detect$7[0:0]$11023 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10942 1'1 + assign $3\wr_detect$7[0:0]$11024 1'1 case - assign $3\wr_detect$7[0:0]$10942 $2\wr_detect$7[0:0]$10941 + assign $3\wr_detect$7[0:0]$11024 $2\wr_detect$7[0:0]$11023 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10943 1'1 + assign $4\wr_detect$7[0:0]$11025 1'1 case - assign $4\wr_detect$7[0:0]$10943 $3\wr_detect$7[0:0]$10942 + assign $4\wr_detect$7[0:0]$11025 $3\wr_detect$7[0:0]$11024 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10944 1'1 + assign $5\wr_detect$7[0:0]$11026 1'1 case - assign $5\wr_detect$7[0:0]$10944 $4\wr_detect$7[0:0]$10943 + assign $5\wr_detect$7[0:0]$11026 $4\wr_detect$7[0:0]$11025 end case - assign $1\wr_detect$7[0:0]$10940 1'0 + assign $1\wr_detect$7[0:0]$11022 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10939 + update \wr_detect$7 $0\wr_detect$7[0:0]$11021 end - attribute \src "libresoc.v:177230.3-177275.6" - process $proc$libresoc.v:177230$10945 + attribute \src "libresoc.v:179030.3-179075.6" + process $proc$libresoc.v:179030$11027 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10946 $7\r1__data_o$next[1:0]$10953 - attribute \src "libresoc.v:177231.5-177231.29" + assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 + attribute \src "libresoc.v:179031.5-179031.29" switch \initial - attribute \src "libresoc.v:177231.9-177231.17" + attribute \src "libresoc.v:179031.9-179031.17" case 1'1 case end @@ -365016,75 +367891,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10947 $6\r1__data_o$next[1:0]$10952 + assign $1\r1__data_o$next[1:0]$11029 $6\r1__data_o$next[1:0]$11034 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10948 \dest11__data_i + assign $2\r1__data_o$next[1:0]$11030 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10948 2'00 + assign $2\r1__data_o$next[1:0]$11030 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10949 \dest21__data_i + assign $3\r1__data_o$next[1:0]$11031 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10949 $2\r1__data_o$next[1:0]$10948 + assign $3\r1__data_o$next[1:0]$11031 $2\r1__data_o$next[1:0]$11030 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10950 \dest31__data_i + assign $4\r1__data_o$next[1:0]$11032 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10950 $3\r1__data_o$next[1:0]$10949 + assign $4\r1__data_o$next[1:0]$11032 $3\r1__data_o$next[1:0]$11031 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10951 \w1__data_i + assign $5\r1__data_o$next[1:0]$11033 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10951 $4\r1__data_o$next[1:0]$10950 + assign $5\r1__data_o$next[1:0]$11033 $4\r1__data_o$next[1:0]$11032 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10952 \reg + assign $6\r1__data_o$next[1:0]$11034 \reg case - assign $6\r1__data_o$next[1:0]$10952 $5\r1__data_o$next[1:0]$10951 + assign $6\r1__data_o$next[1:0]$11034 $5\r1__data_o$next[1:0]$11033 end case - assign $1\r1__data_o$next[1:0]$10947 2'00 + assign $1\r1__data_o$next[1:0]$11029 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10953 2'00 + assign $7\r1__data_o$next[1:0]$11035 2'00 case - assign $7\r1__data_o$next[1:0]$10953 $1\r1__data_o$next[1:0]$10947 + assign $7\r1__data_o$next[1:0]$11035 $1\r1__data_o$next[1:0]$11029 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10946 + update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 end - attribute \src "libresoc.v:177276.3-177311.6" - process $proc$libresoc.v:177276$10954 + attribute \src "libresoc.v:179076.3-179111.6" + process $proc$libresoc.v:179076$11036 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10955 $1\wr_detect$10[0:0]$10956 - attribute \src "libresoc.v:177277.5-177277.29" + assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 + attribute \src "libresoc.v:179077.5-179077.29" switch \initial - attribute \src "libresoc.v:177277.9-177277.17" + attribute \src "libresoc.v:179077.9-179077.17" case 1'1 case end @@ -365097,61 +367972,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10956 $5\wr_detect$10[0:0]$10960 + assign $1\wr_detect$10[0:0]$11038 $5\wr_detect$10[0:0]$11042 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10957 1'1 + assign $2\wr_detect$10[0:0]$11039 1'1 case - assign $2\wr_detect$10[0:0]$10957 1'0 + assign $2\wr_detect$10[0:0]$11039 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10958 1'1 + assign $3\wr_detect$10[0:0]$11040 1'1 case - assign $3\wr_detect$10[0:0]$10958 $2\wr_detect$10[0:0]$10957 + assign $3\wr_detect$10[0:0]$11040 $2\wr_detect$10[0:0]$11039 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10959 1'1 + assign $4\wr_detect$10[0:0]$11041 1'1 case - assign $4\wr_detect$10[0:0]$10959 $3\wr_detect$10[0:0]$10958 + assign $4\wr_detect$10[0:0]$11041 $3\wr_detect$10[0:0]$11040 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10960 1'1 + assign $5\wr_detect$10[0:0]$11042 1'1 case - assign $5\wr_detect$10[0:0]$10960 $4\wr_detect$10[0:0]$10959 + assign $5\wr_detect$10[0:0]$11042 $4\wr_detect$10[0:0]$11041 end case - assign $1\wr_detect$10[0:0]$10956 1'0 + assign $1\wr_detect$10[0:0]$11038 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10955 + update \wr_detect$10 $0\wr_detect$10[0:0]$11037 end - attribute \src "libresoc.v:177312.3-177344.6" - process $proc$libresoc.v:177312$10961 + attribute \src "libresoc.v:179112.3-179144.6" + process $proc$libresoc.v:179112$11043 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10962 $5\reg$next[1:0]$10967 - attribute \src "libresoc.v:177313.5-177313.29" + assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 + attribute \src "libresoc.v:179113.5-179113.29" switch \initial - attribute \src "libresoc.v:177313.9-177313.17" + attribute \src "libresoc.v:179113.9-179113.17" case 1'1 case end @@ -365160,179 +368035,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10963 \dest11__data_i + assign $1\reg$next[1:0]$11045 \dest11__data_i case - assign $1\reg$next[1:0]$10963 \reg + assign $1\reg$next[1:0]$11045 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10964 \dest21__data_i + assign $2\reg$next[1:0]$11046 \dest21__data_i case - assign $2\reg$next[1:0]$10964 $1\reg$next[1:0]$10963 + assign $2\reg$next[1:0]$11046 $1\reg$next[1:0]$11045 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10965 \dest31__data_i + assign $3\reg$next[1:0]$11047 \dest31__data_i case - assign $3\reg$next[1:0]$10965 $2\reg$next[1:0]$10964 + assign $3\reg$next[1:0]$11047 $2\reg$next[1:0]$11046 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10966 \w1__data_i + assign $4\reg$next[1:0]$11048 \w1__data_i case - assign $4\reg$next[1:0]$10966 $3\reg$next[1:0]$10965 + assign $4\reg$next[1:0]$11048 $3\reg$next[1:0]$11047 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10967 2'00 + assign $5\reg$next[1:0]$11049 2'00 case - assign $5\reg$next[1:0]$10967 $4\reg$next[1:0]$10966 + assign $5\reg$next[1:0]$11049 $4\reg$next[1:0]$11048 end sync always - update \reg$next $0\reg$next[1:0]$10962 + update \reg$next $0\reg$next[1:0]$11044 end - connect \$9 $not$libresoc.v:176970$10894_Y - connect \$1 $not$libresoc.v:176971$10895_Y - connect \$3 $not$libresoc.v:176972$10896_Y - connect \$6 $not$libresoc.v:176973$10897_Y + connect \$9 $not$libresoc.v:178770$10976_Y + connect \$1 $not$libresoc.v:178771$10977_Y + connect \$3 $not$libresoc.v:178772$10978_Y + connect \$6 $not$libresoc.v:178773$10979_Y end -attribute \src "libresoc.v:177349.1-177698.10" +attribute \src "libresoc.v:179149.1-179498.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $0\cia1__data_o$next[63:0]$10982 - attribute \src "libresoc.v:177417.3-177418.41" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $0\cia1__data_o$next[63:0]$11064 + attribute \src "libresoc.v:179217.3-179218.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:177350.7-177350.20" + attribute \src "libresoc.v:179150.7-179150.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $0\msr1__data_o$next[63:0]$10992 - attribute \src "libresoc.v:177415.3-177416.41" + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $0\msr1__data_o$next[63:0]$11074 + attribute \src "libresoc.v:179215.3-179216.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $0\reg$next[63:0]$11024 - attribute \src "libresoc.v:177411.3-177412.25" + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $0\reg$next[63:0]$11106 + attribute \src "libresoc.v:179211.3-179212.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $0\sv1__data_o$next[63:0]$11008 - attribute \src "libresoc.v:177413.3-177414.39" + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $0\sv1__data_o$next[63:0]$11090 + attribute \src "libresoc.v:179213.3-179214.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:177547.3-177582.6" - wire $0\wr_detect$4[0:0]$11001 - attribute \src "libresoc.v:177629.3-177664.6" - wire $0\wr_detect$7[0:0]$11017 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179347.3-179382.6" + wire $0\wr_detect$4[0:0]$11083 + attribute \src "libresoc.v:179429.3-179464.6" + wire $0\wr_detect$7[0:0]$11099 + attribute \src "libresoc.v:179265.3-179300.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $1\cia1__data_o$next[63:0]$10983 - attribute \src "libresoc.v:177359.14-177359.49" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $1\cia1__data_o$next[63:0]$11065 + attribute \src "libresoc.v:179159.14-179159.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $1\msr1__data_o$next[63:0]$10993 - attribute \src "libresoc.v:177376.14-177376.49" + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $1\msr1__data_o$next[63:0]$11075 + attribute \src "libresoc.v:179176.14-179176.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $1\reg$next[63:0]$11025 - attribute \src "libresoc.v:177388.14-177388.42" + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $1\reg$next[63:0]$11107 + attribute \src "libresoc.v:179188.14-179188.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $1\sv1__data_o$next[63:0]$11009 - attribute \src "libresoc.v:177395.14-177395.48" + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $1\sv1__data_o$next[63:0]$11091 + attribute \src "libresoc.v:179195.14-179195.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:177547.3-177582.6" - wire $1\wr_detect$4[0:0]$11002 - attribute \src "libresoc.v:177629.3-177664.6" - wire $1\wr_detect$7[0:0]$11018 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179347.3-179382.6" + wire $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179429.3-179464.6" + wire $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179265.3-179300.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $2\cia1__data_o$next[63:0]$10984 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $2\msr1__data_o$next[63:0]$10994 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $2\reg$next[63:0]$11026 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $2\sv1__data_o$next[63:0]$11010 - attribute \src "libresoc.v:177547.3-177582.6" - wire $2\wr_detect$4[0:0]$11003 - attribute \src "libresoc.v:177629.3-177664.6" - wire $2\wr_detect$7[0:0]$11019 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $2\cia1__data_o$next[63:0]$11066 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $2\msr1__data_o$next[63:0]$11076 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $2\reg$next[63:0]$11108 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $2\sv1__data_o$next[63:0]$11092 + attribute \src "libresoc.v:179347.3-179382.6" + wire $2\wr_detect$4[0:0]$11085 + attribute \src "libresoc.v:179429.3-179464.6" + wire $2\wr_detect$7[0:0]$11101 + attribute \src "libresoc.v:179265.3-179300.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $3\cia1__data_o$next[63:0]$10985 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $3\msr1__data_o$next[63:0]$10995 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $3\reg$next[63:0]$11027 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $3\sv1__data_o$next[63:0]$11011 - attribute \src "libresoc.v:177547.3-177582.6" - wire $3\wr_detect$4[0:0]$11004 - attribute \src "libresoc.v:177629.3-177664.6" - wire $3\wr_detect$7[0:0]$11020 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $3\cia1__data_o$next[63:0]$11067 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $3\msr1__data_o$next[63:0]$11077 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $3\reg$next[63:0]$11109 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $3\sv1__data_o$next[63:0]$11093 + attribute \src "libresoc.v:179347.3-179382.6" + wire $3\wr_detect$4[0:0]$11086 + attribute \src "libresoc.v:179429.3-179464.6" + wire $3\wr_detect$7[0:0]$11102 + attribute \src "libresoc.v:179265.3-179300.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $4\cia1__data_o$next[63:0]$10986 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $4\msr1__data_o$next[63:0]$10996 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $4\reg$next[63:0]$11028 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $4\sv1__data_o$next[63:0]$11012 - attribute \src "libresoc.v:177547.3-177582.6" - wire $4\wr_detect$4[0:0]$11005 - attribute \src "libresoc.v:177629.3-177664.6" - wire $4\wr_detect$7[0:0]$11021 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $4\cia1__data_o$next[63:0]$11068 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $4\msr1__data_o$next[63:0]$11078 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $4\reg$next[63:0]$11110 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $4\sv1__data_o$next[63:0]$11094 + attribute \src "libresoc.v:179347.3-179382.6" + wire $4\wr_detect$4[0:0]$11087 + attribute \src "libresoc.v:179429.3-179464.6" + wire $4\wr_detect$7[0:0]$11103 + attribute \src "libresoc.v:179265.3-179300.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $5\cia1__data_o$next[63:0]$10987 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $5\msr1__data_o$next[63:0]$10997 - attribute \src "libresoc.v:177665.3-177697.6" - wire width 64 $5\reg$next[63:0]$11029 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $5\sv1__data_o$next[63:0]$11013 - attribute \src "libresoc.v:177547.3-177582.6" - wire $5\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:177629.3-177664.6" - wire $5\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:177465.3-177500.6" + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $5\cia1__data_o$next[63:0]$11069 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $5\msr1__data_o$next[63:0]$11079 + attribute \src "libresoc.v:179465.3-179497.6" + wire width 64 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $5\sv1__data_o$next[63:0]$11095 + attribute \src "libresoc.v:179347.3-179382.6" + wire $5\wr_detect$4[0:0]$11088 + attribute \src "libresoc.v:179429.3-179464.6" + wire $5\wr_detect$7[0:0]$11104 + attribute \src "libresoc.v:179265.3-179300.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $6\cia1__data_o$next[63:0]$10988 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $6\msr1__data_o$next[63:0]$10998 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $6\sv1__data_o$next[63:0]$11014 - attribute \src "libresoc.v:177419.3-177464.6" - wire width 64 $7\cia1__data_o$next[63:0]$10989 - attribute \src "libresoc.v:177501.3-177546.6" - wire width 64 $7\msr1__data_o$next[63:0]$10999 - attribute \src "libresoc.v:177583.3-177628.6" - wire width 64 $7\sv1__data_o$next[63:0]$11015 - attribute \src "libresoc.v:177408.17-177408.100" - wire $not$libresoc.v:177408$10974_Y - attribute \src "libresoc.v:177409.17-177409.103" - wire $not$libresoc.v:177409$10975_Y - attribute \src "libresoc.v:177410.17-177410.103" - wire $not$libresoc.v:177410$10976_Y + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $6\cia1__data_o$next[63:0]$11070 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $6\msr1__data_o$next[63:0]$11080 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $6\sv1__data_o$next[63:0]$11096 + attribute \src "libresoc.v:179219.3-179264.6" + wire width 64 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179301.3-179346.6" + wire width 64 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179383.3-179428.6" + wire width 64 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179208.17-179208.100" + wire $not$libresoc.v:179208$11056_Y + attribute \src "libresoc.v:179209.17-179209.103" + wire $not$libresoc.v:179209$11057_Y + attribute \src "libresoc.v:179210.17-179210.103" + wire $not$libresoc.v:179210$11058_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365345,15 +368220,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:177350.7-177350.15" + attribute \src "libresoc.v:179150.7-179150.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -365390,106 +368265,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177408$10974 + cell $not $not$libresoc.v:179208$11056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177408$10974_Y + connect \Y $not$libresoc.v:179208$11056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177409$10975 + cell $not $not$libresoc.v:179209$11057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177409$10975_Y + connect \Y $not$libresoc.v:179209$11057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177410$10976 + cell $not $not$libresoc.v:179210$11058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177410$10976_Y + connect \Y $not$libresoc.v:179210$11058_Y end - attribute \src "libresoc.v:177350.7-177350.20" - process $proc$libresoc.v:177350$11030 + attribute \src "libresoc.v:179150.7-179150.20" + process $proc$libresoc.v:179150$11112 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177359.14-177359.49" - process $proc$libresoc.v:177359$11031 + attribute \src "libresoc.v:179159.14-179159.49" + process $proc$libresoc.v:179159$11113 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:177376.14-177376.49" - process $proc$libresoc.v:177376$11032 + attribute \src "libresoc.v:179176.14-179176.49" + process $proc$libresoc.v:179176$11114 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:177388.14-177388.42" - process $proc$libresoc.v:177388$11033 + attribute \src "libresoc.v:179188.14-179188.42" + process $proc$libresoc.v:179188$11115 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:177395.14-177395.48" - process $proc$libresoc.v:177395$11034 + attribute \src "libresoc.v:179195.14-179195.48" + process $proc$libresoc.v:179195$11116 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:177411.3-177412.25" - process $proc$libresoc.v:177411$10977 + attribute \src "libresoc.v:179211.3-179212.25" + process $proc$libresoc.v:179211$11059 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:177413.3-177414.39" - process $proc$libresoc.v:177413$10978 + attribute \src "libresoc.v:179213.3-179214.39" + process $proc$libresoc.v:179213$11060 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:177415.3-177416.41" - process $proc$libresoc.v:177415$10979 + attribute \src "libresoc.v:179215.3-179216.41" + process $proc$libresoc.v:179215$11061 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:177417.3-177418.41" - process $proc$libresoc.v:177417$10980 + attribute \src "libresoc.v:179217.3-179218.41" + process $proc$libresoc.v:179217$11062 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:177419.3-177464.6" - process $proc$libresoc.v:177419$10981 + attribute \src "libresoc.v:179219.3-179264.6" + process $proc$libresoc.v:179219$11063 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10982 $7\cia1__data_o$next[63:0]$10989 - attribute \src "libresoc.v:177420.5-177420.29" + assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 + attribute \src "libresoc.v:179220.5-179220.29" switch \initial - attribute \src "libresoc.v:177420.9-177420.17" + attribute \src "libresoc.v:179220.9-179220.17" case 1'1 case end @@ -365502,75 +368377,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10983 $6\cia1__data_o$next[63:0]$10988 + assign $1\cia1__data_o$next[63:0]$11065 $6\cia1__data_o$next[63:0]$11070 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10984 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$11066 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$11066 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10985 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$11067 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$10985 $2\cia1__data_o$next[63:0]$10984 + assign $3\cia1__data_o$next[63:0]$11067 $2\cia1__data_o$next[63:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10986 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$11068 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$10986 $3\cia1__data_o$next[63:0]$10985 + assign $4\cia1__data_o$next[63:0]$11068 $3\cia1__data_o$next[63:0]$11067 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10987 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$11069 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$10987 $4\cia1__data_o$next[63:0]$10986 + assign $5\cia1__data_o$next[63:0]$11069 $4\cia1__data_o$next[63:0]$11068 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10988 \reg + assign $6\cia1__data_o$next[63:0]$11070 \reg case - assign $6\cia1__data_o$next[63:0]$10988 $5\cia1__data_o$next[63:0]$10987 + assign $6\cia1__data_o$next[63:0]$11070 $5\cia1__data_o$next[63:0]$11069 end case - assign $1\cia1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$11071 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$10989 $1\cia1__data_o$next[63:0]$10983 + assign $7\cia1__data_o$next[63:0]$11071 $1\cia1__data_o$next[63:0]$11065 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10982 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 end - attribute \src "libresoc.v:177465.3-177500.6" - process $proc$libresoc.v:177465$10990 + attribute \src "libresoc.v:179265.3-179300.6" + process $proc$libresoc.v:179265$11072 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177466.5-177466.29" + attribute \src "libresoc.v:179266.5-179266.29" switch \initial - attribute \src "libresoc.v:177466.9-177466.17" + attribute \src "libresoc.v:179266.9-179266.17" case 1'1 case end @@ -365626,15 +368501,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177501.3-177546.6" - process $proc$libresoc.v:177501$10991 + attribute \src "libresoc.v:179301.3-179346.6" + process $proc$libresoc.v:179301$11073 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10992 $7\msr1__data_o$next[63:0]$10999 - attribute \src "libresoc.v:177502.5-177502.29" + assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:179302.5-179302.29" switch \initial - attribute \src "libresoc.v:177502.9-177502.17" + attribute \src "libresoc.v:179302.9-179302.17" case 1'1 case end @@ -365647,75 +368522,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10993 $6\msr1__data_o$next[63:0]$10998 + assign $1\msr1__data_o$next[63:0]$11075 $6\msr1__data_o$next[63:0]$11080 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10994 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$11076 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10994 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10995 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$11077 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10995 $2\msr1__data_o$next[63:0]$10994 + assign $3\msr1__data_o$next[63:0]$11077 $2\msr1__data_o$next[63:0]$11076 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10996 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$11078 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$10996 $3\msr1__data_o$next[63:0]$10995 + assign $4\msr1__data_o$next[63:0]$11078 $3\msr1__data_o$next[63:0]$11077 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10997 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$11079 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$10997 $4\msr1__data_o$next[63:0]$10996 + assign $5\msr1__data_o$next[63:0]$11079 $4\msr1__data_o$next[63:0]$11078 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10998 \reg + assign $6\msr1__data_o$next[63:0]$11080 \reg case - assign $6\msr1__data_o$next[63:0]$10998 $5\msr1__data_o$next[63:0]$10997 + assign $6\msr1__data_o$next[63:0]$11080 $5\msr1__data_o$next[63:0]$11079 end case - assign $1\msr1__data_o$next[63:0]$10993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$10999 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$10999 $1\msr1__data_o$next[63:0]$10993 + assign $7\msr1__data_o$next[63:0]$11081 $1\msr1__data_o$next[63:0]$11075 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10992 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 end - attribute \src "libresoc.v:177547.3-177582.6" - process $proc$libresoc.v:177547$11000 + attribute \src "libresoc.v:179347.3-179382.6" + process $proc$libresoc.v:179347$11082 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11001 $1\wr_detect$4[0:0]$11002 - attribute \src "libresoc.v:177548.5-177548.29" + assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 + attribute \src "libresoc.v:179348.5-179348.29" switch \initial - attribute \src "libresoc.v:177548.9-177548.17" + attribute \src "libresoc.v:179348.9-179348.17" case 1'1 case end @@ -365728,58 +368603,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11002 $5\wr_detect$4[0:0]$11006 + assign $1\wr_detect$4[0:0]$11084 $5\wr_detect$4[0:0]$11088 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11003 1'1 + assign $2\wr_detect$4[0:0]$11085 1'1 case - assign $2\wr_detect$4[0:0]$11003 1'0 + assign $2\wr_detect$4[0:0]$11085 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11004 1'1 + assign $3\wr_detect$4[0:0]$11086 1'1 case - assign $3\wr_detect$4[0:0]$11004 $2\wr_detect$4[0:0]$11003 + assign $3\wr_detect$4[0:0]$11086 $2\wr_detect$4[0:0]$11085 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11005 1'1 + assign $4\wr_detect$4[0:0]$11087 1'1 case - assign $4\wr_detect$4[0:0]$11005 $3\wr_detect$4[0:0]$11004 + assign $4\wr_detect$4[0:0]$11087 $3\wr_detect$4[0:0]$11086 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11006 1'1 + assign $5\wr_detect$4[0:0]$11088 1'1 case - assign $5\wr_detect$4[0:0]$11006 $4\wr_detect$4[0:0]$11005 + assign $5\wr_detect$4[0:0]$11088 $4\wr_detect$4[0:0]$11087 end case - assign $1\wr_detect$4[0:0]$11002 1'0 + assign $1\wr_detect$4[0:0]$11084 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11001 + update \wr_detect$4 $0\wr_detect$4[0:0]$11083 end - attribute \src "libresoc.v:177583.3-177628.6" - process $proc$libresoc.v:177583$11007 + attribute \src "libresoc.v:179383.3-179428.6" + process $proc$libresoc.v:179383$11089 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$11008 $7\sv1__data_o$next[63:0]$11015 - attribute \src "libresoc.v:177584.5-177584.29" + assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 + attribute \src "libresoc.v:179384.5-179384.29" switch \initial - attribute \src "libresoc.v:177584.9-177584.17" + attribute \src "libresoc.v:179384.9-179384.17" case 1'1 case end @@ -365792,75 +368667,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$11009 $6\sv1__data_o$next[63:0]$11014 + assign $1\sv1__data_o$next[63:0]$11091 $6\sv1__data_o$next[63:0]$11096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$11010 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$11092 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$11010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$11011 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$11093 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$11011 $2\sv1__data_o$next[63:0]$11010 + assign $3\sv1__data_o$next[63:0]$11093 $2\sv1__data_o$next[63:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$11012 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$11094 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$11012 $3\sv1__data_o$next[63:0]$11011 + assign $4\sv1__data_o$next[63:0]$11094 $3\sv1__data_o$next[63:0]$11093 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$11013 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$11095 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$11013 $4\sv1__data_o$next[63:0]$11012 + assign $5\sv1__data_o$next[63:0]$11095 $4\sv1__data_o$next[63:0]$11094 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$11014 \reg + assign $6\sv1__data_o$next[63:0]$11096 \reg case - assign $6\sv1__data_o$next[63:0]$11014 $5\sv1__data_o$next[63:0]$11013 + assign $6\sv1__data_o$next[63:0]$11096 $5\sv1__data_o$next[63:0]$11095 end case - assign $1\sv1__data_o$next[63:0]$11009 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$11015 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$11015 $1\sv1__data_o$next[63:0]$11009 + assign $7\sv1__data_o$next[63:0]$11097 $1\sv1__data_o$next[63:0]$11091 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11008 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 end - attribute \src "libresoc.v:177629.3-177664.6" - process $proc$libresoc.v:177629$11016 + attribute \src "libresoc.v:179429.3-179464.6" + process $proc$libresoc.v:179429$11098 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11017 $1\wr_detect$7[0:0]$11018 - attribute \src "libresoc.v:177630.5-177630.29" + assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 + attribute \src "libresoc.v:179430.5-179430.29" switch \initial - attribute \src "libresoc.v:177630.9-177630.17" + attribute \src "libresoc.v:179430.9-179430.17" case 1'1 case end @@ -365873,61 +368748,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11018 $5\wr_detect$7[0:0]$11022 + assign $1\wr_detect$7[0:0]$11100 $5\wr_detect$7[0:0]$11104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11019 1'1 + assign $2\wr_detect$7[0:0]$11101 1'1 case - assign $2\wr_detect$7[0:0]$11019 1'0 + assign $2\wr_detect$7[0:0]$11101 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11020 1'1 + assign $3\wr_detect$7[0:0]$11102 1'1 case - assign $3\wr_detect$7[0:0]$11020 $2\wr_detect$7[0:0]$11019 + assign $3\wr_detect$7[0:0]$11102 $2\wr_detect$7[0:0]$11101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11021 1'1 + assign $4\wr_detect$7[0:0]$11103 1'1 case - assign $4\wr_detect$7[0:0]$11021 $3\wr_detect$7[0:0]$11020 + assign $4\wr_detect$7[0:0]$11103 $3\wr_detect$7[0:0]$11102 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11022 1'1 + assign $5\wr_detect$7[0:0]$11104 1'1 case - assign $5\wr_detect$7[0:0]$11022 $4\wr_detect$7[0:0]$11021 + assign $5\wr_detect$7[0:0]$11104 $4\wr_detect$7[0:0]$11103 end case - assign $1\wr_detect$7[0:0]$11018 1'0 + assign $1\wr_detect$7[0:0]$11100 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11017 + update \wr_detect$7 $0\wr_detect$7[0:0]$11099 end - attribute \src "libresoc.v:177665.3-177697.6" - process $proc$libresoc.v:177665$11023 + attribute \src "libresoc.v:179465.3-179497.6" + process $proc$libresoc.v:179465$11105 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11024 $5\reg$next[63:0]$11029 - attribute \src "libresoc.v:177666.5-177666.29" + assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 + attribute \src "libresoc.v:179466.5-179466.29" switch \initial - attribute \src "libresoc.v:177666.9-177666.17" + attribute \src "libresoc.v:179466.9-179466.17" case 1'1 case end @@ -365936,286 +368811,324 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11025 \nia1__data_i + assign $1\reg$next[63:0]$11107 \nia1__data_i case - assign $1\reg$next[63:0]$11025 \reg + assign $1\reg$next[63:0]$11107 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11026 \msr1__data_i + assign $2\reg$next[63:0]$11108 \msr1__data_i case - assign $2\reg$next[63:0]$11026 $1\reg$next[63:0]$11025 + assign $2\reg$next[63:0]$11108 $1\reg$next[63:0]$11107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11027 \sv1__data_i + assign $3\reg$next[63:0]$11109 \sv1__data_i case - assign $3\reg$next[63:0]$11027 $2\reg$next[63:0]$11026 + assign $3\reg$next[63:0]$11109 $2\reg$next[63:0]$11108 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11028 \d_wr11__data_i + assign $4\reg$next[63:0]$11110 \d_wr11__data_i case - assign $4\reg$next[63:0]$11028 $3\reg$next[63:0]$11027 + assign $4\reg$next[63:0]$11110 $3\reg$next[63:0]$11109 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11029 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11111 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11029 $4\reg$next[63:0]$11028 + assign $5\reg$next[63:0]$11111 $4\reg$next[63:0]$11110 end sync always - update \reg$next $0\reg$next[63:0]$11024 + update \reg$next $0\reg$next[63:0]$11106 end - connect \$1 $not$libresoc.v:177408$10974_Y - connect \$3 $not$libresoc.v:177409$10975_Y - connect \$6 $not$libresoc.v:177410$10976_Y + connect \$1 $not$libresoc.v:179208$11056_Y + connect \$3 $not$libresoc.v:179209$11057_Y + connect \$6 $not$libresoc.v:179210$11058_Y end -attribute \src "libresoc.v:177702.1-178173.10" +attribute \src "libresoc.v:179502.1-180057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:177703.7-177703.20" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 + attribute \src "libresoc.v:179608.3-179609.49" + wire width 4 $0\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179503.7-179503.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $0\r22__data_o$next[3:0]$11104 - attribute \src "libresoc.v:177786.3-177787.39" + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $0\r22__data_o$next[3:0]$11140 + attribute \src "libresoc.v:179598.3-179599.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $0\r2__data_o$next[3:0]$11090 - attribute \src "libresoc.v:177788.3-177789.37" + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $0\r2__data_o$next[3:0]$11202 + attribute \src "libresoc.v:179600.3-179601.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $0\reg$next[3:0]$11056 - attribute \src "libresoc.v:177784.3-177785.25" + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $0\reg$next[3:0]$11154 + attribute \src "libresoc.v:179596.3-179597.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $0\src12__data_o$next[3:0]$11047 - attribute \src "libresoc.v:177794.3-177795.43" + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $0\src12__data_o$next[3:0]$11160 + attribute \src "libresoc.v:179606.3-179607.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $0\src22__data_o$next[3:0]$11062 - attribute \src "libresoc.v:177792.3-177793.43" + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $0\src22__data_o$next[3:0]$11174 + attribute \src "libresoc.v:179604.3-179605.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $0\src32__data_o$next[3:0]$11076 - attribute \src "libresoc.v:177790.3-177791.43" + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $0\src32__data_o$next[3:0]$11188 + attribute \src "libresoc.v:179602.3-179603.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:178073.3-178102.6" - wire $0\wr_detect$10[0:0]$11098 - attribute \src "libresoc.v:178143.3-178172.6" - wire $0\wr_detect$13[0:0]$11112 - attribute \src "libresoc.v:177933.3-177962.6" - wire $0\wr_detect$4[0:0]$11070 - attribute \src "libresoc.v:178003.3-178032.6" - wire $0\wr_detect$7[0:0]$11084 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179957.3-179986.6" + wire $0\wr_detect$10[0:0]$11196 + attribute \src "libresoc.v:180027.3-180056.6" + wire $0\wr_detect$13[0:0]$11210 + attribute \src "libresoc.v:179720.3-179749.6" + wire $0\wr_detect$16[0:0]$11148 + attribute \src "libresoc.v:179817.3-179846.6" + wire $0\wr_detect$4[0:0]$11168 + attribute \src "libresoc.v:179887.3-179916.6" + wire $0\wr_detect$7[0:0]$11182 + attribute \src "libresoc.v:179650.3-179679.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $1\r22__data_o$next[3:0]$11105 - attribute \src "libresoc.v:177728.13-177728.31" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 + attribute \src "libresoc.v:179522.13-179522.36" + wire width 4 $1\cr_pred2__data_o[3:0] + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $1\r22__data_o$next[3:0]$11141 + attribute \src "libresoc.v:179537.13-179537.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $1\r2__data_o$next[3:0]$11091 - attribute \src "libresoc.v:177735.13-177735.30" + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $1\r2__data_o$next[3:0]$11203 + attribute \src "libresoc.v:179544.13-179544.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $1\reg$next[3:0]$11057 - attribute \src "libresoc.v:177741.13-177741.25" + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $1\reg$next[3:0]$11155 + attribute \src "libresoc.v:179550.13-179550.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $1\src12__data_o$next[3:0]$11048 - attribute \src "libresoc.v:177746.13-177746.33" + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $1\src12__data_o$next[3:0]$11161 + attribute \src "libresoc.v:179555.13-179555.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $1\src22__data_o$next[3:0]$11063 - attribute \src "libresoc.v:177753.13-177753.33" + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $1\src22__data_o$next[3:0]$11175 + attribute \src "libresoc.v:179562.13-179562.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $1\src32__data_o$next[3:0]$11077 - attribute \src "libresoc.v:177760.13-177760.33" + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $1\src32__data_o$next[3:0]$11189 + attribute \src "libresoc.v:179569.13-179569.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:178073.3-178102.6" - wire $1\wr_detect$10[0:0]$11099 - attribute \src "libresoc.v:178143.3-178172.6" - wire $1\wr_detect$13[0:0]$11113 - attribute \src "libresoc.v:177933.3-177962.6" - wire $1\wr_detect$4[0:0]$11071 - attribute \src "libresoc.v:178003.3-178032.6" - wire $1\wr_detect$7[0:0]$11085 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179957.3-179986.6" + wire $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:180027.3-180056.6" + wire $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:179720.3-179749.6" + wire $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179817.3-179846.6" + wire $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179887.3-179916.6" + wire $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179650.3-179679.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $2\r22__data_o$next[3:0]$11106 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $2\r2__data_o$next[3:0]$11092 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $2\reg$next[3:0]$11058 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $2\src12__data_o$next[3:0]$11049 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $2\src22__data_o$next[3:0]$11064 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $2\src32__data_o$next[3:0]$11078 - attribute \src "libresoc.v:178073.3-178102.6" - wire $2\wr_detect$10[0:0]$11100 - attribute \src "libresoc.v:178143.3-178172.6" - wire $2\wr_detect$13[0:0]$11114 - attribute \src "libresoc.v:177933.3-177962.6" - wire $2\wr_detect$4[0:0]$11072 - attribute \src "libresoc.v:178003.3-178032.6" - wire $2\wr_detect$7[0:0]$11086 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $2\r22__data_o$next[3:0]$11142 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $2\r2__data_o$next[3:0]$11204 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $2\reg$next[3:0]$11156 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $2\src12__data_o$next[3:0]$11162 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $2\src22__data_o$next[3:0]$11176 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $2\src32__data_o$next[3:0]$11190 + attribute \src "libresoc.v:179957.3-179986.6" + wire $2\wr_detect$10[0:0]$11198 + attribute \src "libresoc.v:180027.3-180056.6" + wire $2\wr_detect$13[0:0]$11212 + attribute \src "libresoc.v:179720.3-179749.6" + wire $2\wr_detect$16[0:0]$11150 + attribute \src "libresoc.v:179817.3-179846.6" + wire $2\wr_detect$4[0:0]$11170 + attribute \src "libresoc.v:179887.3-179916.6" + wire $2\wr_detect$7[0:0]$11184 + attribute \src "libresoc.v:179650.3-179679.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $3\r22__data_o$next[3:0]$11107 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $3\r2__data_o$next[3:0]$11093 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $3\reg$next[3:0]$11059 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $3\src12__data_o$next[3:0]$11050 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $3\src22__data_o$next[3:0]$11065 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $3\src32__data_o$next[3:0]$11079 - attribute \src "libresoc.v:178073.3-178102.6" - wire $3\wr_detect$10[0:0]$11101 - attribute \src "libresoc.v:178143.3-178172.6" - wire $3\wr_detect$13[0:0]$11115 - attribute \src "libresoc.v:177933.3-177962.6" - wire $3\wr_detect$4[0:0]$11073 - attribute \src "libresoc.v:178003.3-178032.6" - wire $3\wr_detect$7[0:0]$11087 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $3\cr_pred2__data_o$next[3:0]$11134 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $3\r22__data_o$next[3:0]$11143 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $3\r2__data_o$next[3:0]$11205 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $3\reg$next[3:0]$11157 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $3\src12__data_o$next[3:0]$11163 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $3\src22__data_o$next[3:0]$11177 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $3\src32__data_o$next[3:0]$11191 + attribute \src "libresoc.v:179957.3-179986.6" + wire $3\wr_detect$10[0:0]$11199 + attribute \src "libresoc.v:180027.3-180056.6" + wire $3\wr_detect$13[0:0]$11213 + attribute \src "libresoc.v:179720.3-179749.6" + wire $3\wr_detect$16[0:0]$11151 + attribute \src "libresoc.v:179817.3-179846.6" + wire $3\wr_detect$4[0:0]$11171 + attribute \src "libresoc.v:179887.3-179916.6" + wire $3\wr_detect$7[0:0]$11185 + attribute \src "libresoc.v:179650.3-179679.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $4\r22__data_o$next[3:0]$11108 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $4\r2__data_o$next[3:0]$11094 - attribute \src "libresoc.v:177866.3-177892.6" - wire width 4 $4\reg$next[3:0]$11060 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $4\src12__data_o$next[3:0]$11051 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $4\src22__data_o$next[3:0]$11066 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $4\src32__data_o$next[3:0]$11080 - attribute \src "libresoc.v:178073.3-178102.6" - wire $4\wr_detect$10[0:0]$11102 - attribute \src "libresoc.v:178143.3-178172.6" - wire $4\wr_detect$13[0:0]$11116 - attribute \src "libresoc.v:177933.3-177962.6" - wire $4\wr_detect$4[0:0]$11074 - attribute \src "libresoc.v:178003.3-178032.6" - wire $4\wr_detect$7[0:0]$11088 - attribute \src "libresoc.v:177836.3-177865.6" + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $4\cr_pred2__data_o$next[3:0]$11135 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $4\r22__data_o$next[3:0]$11144 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $4\r2__data_o$next[3:0]$11206 + attribute \src "libresoc.v:179750.3-179776.6" + wire width 4 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $4\src12__data_o$next[3:0]$11164 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $4\src22__data_o$next[3:0]$11178 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $4\src32__data_o$next[3:0]$11192 + attribute \src "libresoc.v:179957.3-179986.6" + wire $4\wr_detect$10[0:0]$11200 + attribute \src "libresoc.v:180027.3-180056.6" + wire $4\wr_detect$13[0:0]$11214 + attribute \src "libresoc.v:179720.3-179749.6" + wire $4\wr_detect$16[0:0]$11152 + attribute \src "libresoc.v:179817.3-179846.6" + wire $4\wr_detect$4[0:0]$11172 + attribute \src "libresoc.v:179887.3-179916.6" + wire $4\wr_detect$7[0:0]$11186 + attribute \src "libresoc.v:179650.3-179679.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $5\r22__data_o$next[3:0]$11109 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $5\r2__data_o$next[3:0]$11095 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $5\src12__data_o$next[3:0]$11052 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $5\src22__data_o$next[3:0]$11067 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $5\src32__data_o$next[3:0]$11081 - attribute \src "libresoc.v:178103.3-178142.6" - wire width 4 $6\r22__data_o$next[3:0]$11110 - attribute \src "libresoc.v:178033.3-178072.6" - wire width 4 $6\r2__data_o$next[3:0]$11096 - attribute \src "libresoc.v:177796.3-177835.6" - wire width 4 $6\src12__data_o$next[3:0]$11053 - attribute \src "libresoc.v:177893.3-177932.6" - wire width 4 $6\src22__data_o$next[3:0]$11068 - attribute \src "libresoc.v:177963.3-178002.6" - wire width 4 $6\src32__data_o$next[3:0]$11082 - attribute \src "libresoc.v:177779.17-177779.104" - wire $not$libresoc.v:177779$11035_Y - attribute \src "libresoc.v:177780.18-177780.105" - wire $not$libresoc.v:177780$11036_Y - attribute \src "libresoc.v:177781.17-177781.100" - wire $not$libresoc.v:177781$11037_Y - attribute \src "libresoc.v:177782.17-177782.103" - wire $not$libresoc.v:177782$11038_Y - attribute \src "libresoc.v:177783.17-177783.103" - wire $not$libresoc.v:177783$11039_Y + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $5\cr_pred2__data_o$next[3:0]$11136 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $5\r22__data_o$next[3:0]$11145 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $5\r2__data_o$next[3:0]$11207 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $5\src12__data_o$next[3:0]$11165 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $5\src22__data_o$next[3:0]$11179 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $5\src32__data_o$next[3:0]$11193 + attribute \src "libresoc.v:179610.3-179649.6" + wire width 4 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179680.3-179719.6" + wire width 4 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179987.3-180026.6" + wire width 4 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179777.3-179816.6" + wire width 4 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179847.3-179886.6" + wire width 4 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179917.3-179956.6" + wire width 4 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179590.17-179590.104" + wire $not$libresoc.v:179590$11117_Y + attribute \src "libresoc.v:179591.18-179591.105" + wire $not$libresoc.v:179591$11118_Y + attribute \src "libresoc.v:179592.18-179592.105" + wire $not$libresoc.v:179592$11119_Y + attribute \src "libresoc.v:179593.17-179593.100" + wire $not$libresoc.v:179593$11120_Y + attribute \src "libresoc.v:179594.17-179594.103" + wire $not$libresoc.v:179594$11121_Y + attribute \src "libresoc.v:179595.17-179595.103" + wire $not$libresoc.v:179595$11122_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest12__data_i + wire width 4 output 3 \cr_pred2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest12__wen + wire width 4 \cr_pred2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest22__data_i + wire input 2 \cr_pred2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest22__wen - attribute \src "libresoc.v:177703.7-177703.15" + wire width 4 input 11 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest22__wen + attribute \src "libresoc.v:179503.7-179503.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r22__data_o + wire width 4 output 16 \r22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r22__ren + wire input 17 \r22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r2__data_o + wire width 4 output 14 \r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r2__ren + wire input 15 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src12__data_o + wire width 4 output 5 \src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src12__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src12__ren + wire input 4 \src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src22__data_o + wire width 4 output 7 \src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src22__ren + wire input 6 \src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src32__data_o + wire width 4 output 9 \src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src32__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src32__ren + wire input 8 \src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w2__data_i + wire width 4 input 18 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w2__wen + wire input 19 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -366223,232 +369136,257 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177779$11035 + cell $not $not$libresoc.v:179590$11117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177779$11035_Y + connect \Y $not$libresoc.v:179590$11117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177780$11036 + cell $not $not$libresoc.v:179591$11118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:177780$11036_Y + connect \Y $not$libresoc.v:179591$11118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:179592$11119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:179592$11119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177781$11037 + cell $not $not$libresoc.v:179593$11120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177781$11037_Y + connect \Y $not$libresoc.v:179593$11120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177782$11038 + cell $not $not$libresoc.v:179594$11121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177782$11038_Y + connect \Y $not$libresoc.v:179594$11121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177783$11039 + cell $not $not$libresoc.v:179595$11122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177783$11039_Y + connect \Y $not$libresoc.v:179595$11122_Y end - attribute \src "libresoc.v:177703.7-177703.20" - process $proc$libresoc.v:177703$11117 + attribute \src "libresoc.v:179503.7-179503.20" + process $proc$libresoc.v:179503$11215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177728.13-177728.31" - process $proc$libresoc.v:177728$11118 + attribute \src "libresoc.v:179522.13-179522.36" + process $proc$libresoc.v:179522$11216 + assign { } { } + assign $1\cr_pred2__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179537.13-179537.31" + process $proc$libresoc.v:179537$11217 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:177735.13-177735.30" - process $proc$libresoc.v:177735$11119 + attribute \src "libresoc.v:179544.13-179544.30" + process $proc$libresoc.v:179544$11218 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:177741.13-177741.25" - process $proc$libresoc.v:177741$11120 + attribute \src "libresoc.v:179550.13-179550.25" + process $proc$libresoc.v:179550$11219 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:177746.13-177746.33" - process $proc$libresoc.v:177746$11121 + attribute \src "libresoc.v:179555.13-179555.33" + process $proc$libresoc.v:179555$11220 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:177753.13-177753.33" - process $proc$libresoc.v:177753$11122 + attribute \src "libresoc.v:179562.13-179562.33" + process $proc$libresoc.v:179562$11221 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:177760.13-177760.33" - process $proc$libresoc.v:177760$11123 + attribute \src "libresoc.v:179569.13-179569.33" + process $proc$libresoc.v:179569$11222 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:177784.3-177785.25" - process $proc$libresoc.v:177784$11040 + attribute \src "libresoc.v:179596.3-179597.25" + process $proc$libresoc.v:179596$11123 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:177786.3-177787.39" - process $proc$libresoc.v:177786$11041 + attribute \src "libresoc.v:179598.3-179599.39" + process $proc$libresoc.v:179598$11124 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:177788.3-177789.37" - process $proc$libresoc.v:177788$11042 + attribute \src "libresoc.v:179600.3-179601.37" + process $proc$libresoc.v:179600$11125 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:177790.3-177791.43" - process $proc$libresoc.v:177790$11043 + attribute \src "libresoc.v:179602.3-179603.43" + process $proc$libresoc.v:179602$11126 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:177792.3-177793.43" - process $proc$libresoc.v:177792$11044 + attribute \src "libresoc.v:179604.3-179605.43" + process $proc$libresoc.v:179604$11127 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:177794.3-177795.43" - process $proc$libresoc.v:177794$11045 + attribute \src "libresoc.v:179606.3-179607.43" + process $proc$libresoc.v:179606$11128 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:177796.3-177835.6" - process $proc$libresoc.v:177796$11046 + attribute \src "libresoc.v:179608.3-179609.49" + process $proc$libresoc.v:179608$11129 + assign { } { } + assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next + sync posedge \coresync_clk + update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] + end + attribute \src "libresoc.v:179610.3-179649.6" + process $proc$libresoc.v:179610$11130 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$11047 $6\src12__data_o$next[3:0]$11053 - attribute \src "libresoc.v:177797.5-177797.29" + assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:179611.5-179611.29" switch \initial - attribute \src "libresoc.v:177797.9-177797.17" + attribute \src "libresoc.v:179611.9-179611.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + switch \cr_pred2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$11048 $5\src12__data_o$next[3:0]$11052 + assign $1\cr_pred2__data_o$next[3:0]$11132 $5\cr_pred2__data_o$next[3:0]$11136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$11049 \dest12__data_i + assign $2\cr_pred2__data_o$next[3:0]$11133 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$11049 4'0000 + assign $2\cr_pred2__data_o$next[3:0]$11133 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$11050 \dest22__data_i + assign $3\cr_pred2__data_o$next[3:0]$11134 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$11050 $2\src12__data_o$next[3:0]$11049 + assign $3\cr_pred2__data_o$next[3:0]$11134 $2\cr_pred2__data_o$next[3:0]$11133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11051 \w2__data_i + assign $4\cr_pred2__data_o$next[3:0]$11135 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11051 $3\src12__data_o$next[3:0]$11050 + assign $4\cr_pred2__data_o$next[3:0]$11135 $3\cr_pred2__data_o$next[3:0]$11134 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11052 \reg + assign $5\cr_pred2__data_o$next[3:0]$11136 \reg case - assign $5\src12__data_o$next[3:0]$11052 $4\src12__data_o$next[3:0]$11051 + assign $5\cr_pred2__data_o$next[3:0]$11136 $4\cr_pred2__data_o$next[3:0]$11135 end case - assign $1\src12__data_o$next[3:0]$11048 4'0000 + assign $1\cr_pred2__data_o$next[3:0]$11132 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11053 4'0000 + assign $6\cr_pred2__data_o$next[3:0]$11137 4'0000 case - assign $6\src12__data_o$next[3:0]$11053 $1\src12__data_o$next[3:0]$11048 + assign $6\cr_pred2__data_o$next[3:0]$11137 $1\cr_pred2__data_o$next[3:0]$11132 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11047 + update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 end - attribute \src "libresoc.v:177836.3-177865.6" - process $proc$libresoc.v:177836$11054 + attribute \src "libresoc.v:179650.3-179679.6" + process $proc$libresoc.v:179650$11138 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177837.5-177837.29" + attribute \src "libresoc.v:179651.5-179651.29" switch \initial - attribute \src "libresoc.v:177837.9-177837.17" + attribute \src "libresoc.v:179651.9-179651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + switch \cr_pred2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -366489,724 +369427,850 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177866.3-177892.6" - process $proc$libresoc.v:177866$11055 - assign { } { } + attribute \src "libresoc.v:179680.3-179719.6" + process $proc$libresoc.v:179680$11139 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11056 $4\reg$next[3:0]$11060 - attribute \src "libresoc.v:177867.5-177867.29" + assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:179681.5-179681.29" switch \initial - attribute \src "libresoc.v:177867.9-177867.17" + attribute \src "libresoc.v:179681.9-179681.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11057 \dest12__data_i - case - assign $1\reg$next[3:0]$11057 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11058 \dest22__data_i - case - assign $2\reg$next[3:0]$11058 $1\reg$next[3:0]$11057 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11059 \w2__data_i + assign { } { } + assign $1\r22__data_o$next[3:0]$11141 $5\r22__data_o$next[3:0]$11145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11142 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11142 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11143 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11143 $2\r22__data_o$next[3:0]$11142 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11144 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11144 $3\r22__data_o$next[3:0]$11143 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11145 \reg + case + assign $5\r22__data_o$next[3:0]$11145 $4\r22__data_o$next[3:0]$11144 + end case - assign $3\reg$next[3:0]$11059 $2\reg$next[3:0]$11058 + assign $1\r22__data_o$next[3:0]$11141 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11060 4'0000 + assign $6\r22__data_o$next[3:0]$11146 4'0000 case - assign $4\reg$next[3:0]$11060 $3\reg$next[3:0]$11059 + assign $6\r22__data_o$next[3:0]$11146 $1\r22__data_o$next[3:0]$11141 end sync always - update \reg$next $0\reg$next[3:0]$11056 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 end - attribute \src "libresoc.v:177893.3-177932.6" - process $proc$libresoc.v:177893$11061 - assign { } { } + attribute \src "libresoc.v:179720.3-179749.6" + process $proc$libresoc.v:179720$11147 assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11062 $6\src22__data_o$next[3:0]$11068 - attribute \src "libresoc.v:177894.5-177894.29" + assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 + attribute \src "libresoc.v:179721.5-179721.29" switch \initial - attribute \src "libresoc.v:177894.9-177894.17" + attribute \src "libresoc.v:179721.9-179721.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11063 $5\src22__data_o$next[3:0]$11067 + assign $1\wr_detect$16[0:0]$11149 $4\wr_detect$16[0:0]$11152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11064 \dest12__data_i + assign $2\wr_detect$16[0:0]$11150 1'1 case - assign $2\src22__data_o$next[3:0]$11064 4'0000 + assign $2\wr_detect$16[0:0]$11150 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11065 \dest22__data_i + assign $3\wr_detect$16[0:0]$11151 1'1 case - assign $3\src22__data_o$next[3:0]$11065 $2\src22__data_o$next[3:0]$11064 + assign $3\wr_detect$16[0:0]$11151 $2\wr_detect$16[0:0]$11150 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11066 \w2__data_i + assign $4\wr_detect$16[0:0]$11152 1'1 case - assign $4\src22__data_o$next[3:0]$11066 $3\src22__data_o$next[3:0]$11065 + assign $4\wr_detect$16[0:0]$11152 $3\wr_detect$16[0:0]$11151 + end + case + assign $1\wr_detect$16[0:0]$11149 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11148 + end + attribute \src "libresoc.v:179750.3-179776.6" + process $proc$libresoc.v:179750$11153 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 + attribute \src "libresoc.v:179751.5-179751.29" + switch \initial + attribute \src "libresoc.v:179751.9-179751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11155 \dest12__data_i + case + assign $1\reg$next[3:0]$11155 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11156 \dest22__data_i + case + assign $2\reg$next[3:0]$11156 $1\reg$next[3:0]$11155 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11157 \w2__data_i + case + assign $3\reg$next[3:0]$11157 $2\reg$next[3:0]$11156 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11158 4'0000 + case + assign $4\reg$next[3:0]$11158 $3\reg$next[3:0]$11157 + end + sync always + update \reg$next $0\reg$next[3:0]$11154 + end + attribute \src "libresoc.v:179777.3-179816.6" + process $proc$libresoc.v:179777$11159 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 + attribute \src "libresoc.v:179778.5-179778.29" + switch \initial + attribute \src "libresoc.v:179778.9-179778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$11161 $5\src12__data_o$next[3:0]$11165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$11162 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$11162 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$11163 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$11163 $2\src12__data_o$next[3:0]$11162 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$11164 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$11164 $3\src12__data_o$next[3:0]$11163 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11067 \reg + assign $5\src12__data_o$next[3:0]$11165 \reg case - assign $5\src22__data_o$next[3:0]$11067 $4\src22__data_o$next[3:0]$11066 + assign $5\src12__data_o$next[3:0]$11165 $4\src12__data_o$next[3:0]$11164 end case - assign $1\src22__data_o$next[3:0]$11063 4'0000 + assign $1\src12__data_o$next[3:0]$11161 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11068 4'0000 + assign $6\src12__data_o$next[3:0]$11166 4'0000 case - assign $6\src22__data_o$next[3:0]$11068 $1\src22__data_o$next[3:0]$11063 + assign $6\src12__data_o$next[3:0]$11166 $1\src12__data_o$next[3:0]$11161 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11062 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 end - attribute \src "libresoc.v:177933.3-177962.6" - process $proc$libresoc.v:177933$11069 + attribute \src "libresoc.v:179817.3-179846.6" + process $proc$libresoc.v:179817$11167 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11070 $1\wr_detect$4[0:0]$11071 - attribute \src "libresoc.v:177934.5-177934.29" + assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 + attribute \src "libresoc.v:179818.5-179818.29" switch \initial - attribute \src "libresoc.v:177934.9-177934.17" + attribute \src "libresoc.v:179818.9-179818.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11071 $4\wr_detect$4[0:0]$11074 + assign $1\wr_detect$4[0:0]$11169 $4\wr_detect$4[0:0]$11172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11072 1'1 + assign $2\wr_detect$4[0:0]$11170 1'1 case - assign $2\wr_detect$4[0:0]$11072 1'0 + assign $2\wr_detect$4[0:0]$11170 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11073 1'1 + assign $3\wr_detect$4[0:0]$11171 1'1 case - assign $3\wr_detect$4[0:0]$11073 $2\wr_detect$4[0:0]$11072 + assign $3\wr_detect$4[0:0]$11171 $2\wr_detect$4[0:0]$11170 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11074 1'1 + assign $4\wr_detect$4[0:0]$11172 1'1 case - assign $4\wr_detect$4[0:0]$11074 $3\wr_detect$4[0:0]$11073 + assign $4\wr_detect$4[0:0]$11172 $3\wr_detect$4[0:0]$11171 end case - assign $1\wr_detect$4[0:0]$11071 1'0 + assign $1\wr_detect$4[0:0]$11169 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11070 + update \wr_detect$4 $0\wr_detect$4[0:0]$11168 end - attribute \src "libresoc.v:177963.3-178002.6" - process $proc$libresoc.v:177963$11075 + attribute \src "libresoc.v:179847.3-179886.6" + process $proc$libresoc.v:179847$11173 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11076 $6\src32__data_o$next[3:0]$11082 - attribute \src "libresoc.v:177964.5-177964.29" + assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 + attribute \src "libresoc.v:179848.5-179848.29" switch \initial - attribute \src "libresoc.v:177964.9-177964.17" + attribute \src "libresoc.v:179848.9-179848.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11077 $5\src32__data_o$next[3:0]$11081 + assign $1\src22__data_o$next[3:0]$11175 $5\src22__data_o$next[3:0]$11179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11078 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11176 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11078 4'0000 + assign $2\src22__data_o$next[3:0]$11176 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11079 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11177 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11079 $2\src32__data_o$next[3:0]$11078 + assign $3\src22__data_o$next[3:0]$11177 $2\src22__data_o$next[3:0]$11176 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11080 \w2__data_i + assign $4\src22__data_o$next[3:0]$11178 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11080 $3\src32__data_o$next[3:0]$11079 + assign $4\src22__data_o$next[3:0]$11178 $3\src22__data_o$next[3:0]$11177 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11081 \reg + assign $5\src22__data_o$next[3:0]$11179 \reg case - assign $5\src32__data_o$next[3:0]$11081 $4\src32__data_o$next[3:0]$11080 + assign $5\src22__data_o$next[3:0]$11179 $4\src22__data_o$next[3:0]$11178 end case - assign $1\src32__data_o$next[3:0]$11077 4'0000 + assign $1\src22__data_o$next[3:0]$11175 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11082 4'0000 + assign $6\src22__data_o$next[3:0]$11180 4'0000 case - assign $6\src32__data_o$next[3:0]$11082 $1\src32__data_o$next[3:0]$11077 + assign $6\src22__data_o$next[3:0]$11180 $1\src22__data_o$next[3:0]$11175 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11076 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 end - attribute \src "libresoc.v:178003.3-178032.6" - process $proc$libresoc.v:178003$11083 + attribute \src "libresoc.v:179887.3-179916.6" + process $proc$libresoc.v:179887$11181 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11084 $1\wr_detect$7[0:0]$11085 - attribute \src "libresoc.v:178004.5-178004.29" + assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 + attribute \src "libresoc.v:179888.5-179888.29" switch \initial - attribute \src "libresoc.v:178004.9-178004.17" + attribute \src "libresoc.v:179888.9-179888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11085 $4\wr_detect$7[0:0]$11088 + assign $1\wr_detect$7[0:0]$11183 $4\wr_detect$7[0:0]$11186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11086 1'1 + assign $2\wr_detect$7[0:0]$11184 1'1 case - assign $2\wr_detect$7[0:0]$11086 1'0 + assign $2\wr_detect$7[0:0]$11184 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11087 1'1 + assign $3\wr_detect$7[0:0]$11185 1'1 case - assign $3\wr_detect$7[0:0]$11087 $2\wr_detect$7[0:0]$11086 + assign $3\wr_detect$7[0:0]$11185 $2\wr_detect$7[0:0]$11184 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11088 1'1 + assign $4\wr_detect$7[0:0]$11186 1'1 case - assign $4\wr_detect$7[0:0]$11088 $3\wr_detect$7[0:0]$11087 + assign $4\wr_detect$7[0:0]$11186 $3\wr_detect$7[0:0]$11185 end case - assign $1\wr_detect$7[0:0]$11085 1'0 + assign $1\wr_detect$7[0:0]$11183 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11084 + update \wr_detect$7 $0\wr_detect$7[0:0]$11182 end - attribute \src "libresoc.v:178033.3-178072.6" - process $proc$libresoc.v:178033$11089 + attribute \src "libresoc.v:179917.3-179956.6" + process $proc$libresoc.v:179917$11187 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11090 $6\r2__data_o$next[3:0]$11096 - attribute \src "libresoc.v:178034.5-178034.29" + assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 + attribute \src "libresoc.v:179918.5-179918.29" switch \initial - attribute \src "libresoc.v:178034.9-178034.17" + attribute \src "libresoc.v:179918.9-179918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11091 $5\r2__data_o$next[3:0]$11095 + assign $1\src32__data_o$next[3:0]$11189 $5\src32__data_o$next[3:0]$11193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11092 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11190 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11092 4'0000 + assign $2\src32__data_o$next[3:0]$11190 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11093 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11191 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11093 $2\r2__data_o$next[3:0]$11092 + assign $3\src32__data_o$next[3:0]$11191 $2\src32__data_o$next[3:0]$11190 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11094 \w2__data_i + assign $4\src32__data_o$next[3:0]$11192 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11094 $3\r2__data_o$next[3:0]$11093 + assign $4\src32__data_o$next[3:0]$11192 $3\src32__data_o$next[3:0]$11191 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11095 \reg + assign $5\src32__data_o$next[3:0]$11193 \reg case - assign $5\r2__data_o$next[3:0]$11095 $4\r2__data_o$next[3:0]$11094 + assign $5\src32__data_o$next[3:0]$11193 $4\src32__data_o$next[3:0]$11192 end case - assign $1\r2__data_o$next[3:0]$11091 4'0000 + assign $1\src32__data_o$next[3:0]$11189 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11096 4'0000 + assign $6\src32__data_o$next[3:0]$11194 4'0000 case - assign $6\r2__data_o$next[3:0]$11096 $1\r2__data_o$next[3:0]$11091 + assign $6\src32__data_o$next[3:0]$11194 $1\src32__data_o$next[3:0]$11189 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11090 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 end - attribute \src "libresoc.v:178073.3-178102.6" - process $proc$libresoc.v:178073$11097 + attribute \src "libresoc.v:179957.3-179986.6" + process $proc$libresoc.v:179957$11195 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11098 $1\wr_detect$10[0:0]$11099 - attribute \src "libresoc.v:178074.5-178074.29" + assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 + attribute \src "libresoc.v:179958.5-179958.29" switch \initial - attribute \src "libresoc.v:178074.9-178074.17" + attribute \src "libresoc.v:179958.9-179958.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11099 $4\wr_detect$10[0:0]$11102 + assign $1\wr_detect$10[0:0]$11197 $4\wr_detect$10[0:0]$11200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11100 1'1 + assign $2\wr_detect$10[0:0]$11198 1'1 case - assign $2\wr_detect$10[0:0]$11100 1'0 + assign $2\wr_detect$10[0:0]$11198 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11101 1'1 + assign $3\wr_detect$10[0:0]$11199 1'1 case - assign $3\wr_detect$10[0:0]$11101 $2\wr_detect$10[0:0]$11100 + assign $3\wr_detect$10[0:0]$11199 $2\wr_detect$10[0:0]$11198 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11102 1'1 + assign $4\wr_detect$10[0:0]$11200 1'1 case - assign $4\wr_detect$10[0:0]$11102 $3\wr_detect$10[0:0]$11101 + assign $4\wr_detect$10[0:0]$11200 $3\wr_detect$10[0:0]$11199 end case - assign $1\wr_detect$10[0:0]$11099 1'0 + assign $1\wr_detect$10[0:0]$11197 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11098 + update \wr_detect$10 $0\wr_detect$10[0:0]$11196 end - attribute \src "libresoc.v:178103.3-178142.6" - process $proc$libresoc.v:178103$11103 + attribute \src "libresoc.v:179987.3-180026.6" + process $proc$libresoc.v:179987$11201 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11104 $6\r22__data_o$next[3:0]$11110 - attribute \src "libresoc.v:178104.5-178104.29" + assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 + attribute \src "libresoc.v:179988.5-179988.29" switch \initial - attribute \src "libresoc.v:178104.9-178104.17" + attribute \src "libresoc.v:179988.9-179988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11105 $5\r22__data_o$next[3:0]$11109 + assign $1\r2__data_o$next[3:0]$11203 $5\r2__data_o$next[3:0]$11207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11106 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11204 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11106 4'0000 + assign $2\r2__data_o$next[3:0]$11204 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11107 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11205 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11107 $2\r22__data_o$next[3:0]$11106 + assign $3\r2__data_o$next[3:0]$11205 $2\r2__data_o$next[3:0]$11204 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11108 \w2__data_i + assign $4\r2__data_o$next[3:0]$11206 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11108 $3\r22__data_o$next[3:0]$11107 + assign $4\r2__data_o$next[3:0]$11206 $3\r2__data_o$next[3:0]$11205 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11109 \reg + assign $5\r2__data_o$next[3:0]$11207 \reg case - assign $5\r22__data_o$next[3:0]$11109 $4\r22__data_o$next[3:0]$11108 + assign $5\r2__data_o$next[3:0]$11207 $4\r2__data_o$next[3:0]$11206 end case - assign $1\r22__data_o$next[3:0]$11105 4'0000 + assign $1\r2__data_o$next[3:0]$11203 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11110 4'0000 + assign $6\r2__data_o$next[3:0]$11208 4'0000 case - assign $6\r22__data_o$next[3:0]$11110 $1\r22__data_o$next[3:0]$11105 + assign $6\r2__data_o$next[3:0]$11208 $1\r2__data_o$next[3:0]$11203 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11104 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 end - attribute \src "libresoc.v:178143.3-178172.6" - process $proc$libresoc.v:178143$11111 + attribute \src "libresoc.v:180027.3-180056.6" + process $proc$libresoc.v:180027$11209 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11112 $1\wr_detect$13[0:0]$11113 - attribute \src "libresoc.v:178144.5-178144.29" + assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 + attribute \src "libresoc.v:180028.5-180028.29" switch \initial - attribute \src "libresoc.v:178144.9-178144.17" + attribute \src "libresoc.v:180028.9-180028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11113 $4\wr_detect$13[0:0]$11116 + assign $1\wr_detect$13[0:0]$11211 $4\wr_detect$13[0:0]$11214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11114 1'1 + assign $2\wr_detect$13[0:0]$11212 1'1 case - assign $2\wr_detect$13[0:0]$11114 1'0 + assign $2\wr_detect$13[0:0]$11212 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11115 1'1 + assign $3\wr_detect$13[0:0]$11213 1'1 case - assign $3\wr_detect$13[0:0]$11115 $2\wr_detect$13[0:0]$11114 + assign $3\wr_detect$13[0:0]$11213 $2\wr_detect$13[0:0]$11212 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11116 1'1 + assign $4\wr_detect$13[0:0]$11214 1'1 case - assign $4\wr_detect$13[0:0]$11116 $3\wr_detect$13[0:0]$11115 + assign $4\wr_detect$13[0:0]$11214 $3\wr_detect$13[0:0]$11213 end case - assign $1\wr_detect$13[0:0]$11113 1'0 + assign $1\wr_detect$13[0:0]$11211 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11112 + update \wr_detect$13 $0\wr_detect$13[0:0]$11210 end - connect \$9 $not$libresoc.v:177779$11035_Y - connect \$12 $not$libresoc.v:177780$11036_Y - connect \$1 $not$libresoc.v:177781$11037_Y - connect \$3 $not$libresoc.v:177782$11038_Y - connect \$6 $not$libresoc.v:177783$11039_Y + connect \$9 $not$libresoc.v:179590$11117_Y + connect \$12 $not$libresoc.v:179591$11118_Y + connect \$15 $not$libresoc.v:179592$11119_Y + connect \$1 $not$libresoc.v:179593$11120_Y + connect \$3 $not$libresoc.v:179594$11121_Y + connect \$6 $not$libresoc.v:179595$11122_Y end -attribute \src "libresoc.v:178177.1-178622.10" +attribute \src "libresoc.v:180061.1-180506.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:178178.7-178178.20" + attribute \src "libresoc.v:180062.7-180062.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $0\r2__data_o$next[1:0]$11176 - attribute \src "libresoc.v:178253.3-178254.37" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $0\r2__data_o$next[1:0]$11275 + attribute \src "libresoc.v:180137.3-180138.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $0\reg$next[1:0]$11192 - attribute \src "libresoc.v:178251.3-178252.25" + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $0\reg$next[1:0]$11291 + attribute \src "libresoc.v:180135.3-180136.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $0\src12__data_o$next[1:0]$11134 - attribute \src "libresoc.v:178259.3-178260.43" + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $0\src12__data_o$next[1:0]$11233 + attribute \src "libresoc.v:180143.3-180144.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $0\src22__data_o$next[1:0]$11144 - attribute \src "libresoc.v:178257.3-178258.43" + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $0\src22__data_o$next[1:0]$11243 + attribute \src "libresoc.v:180141.3-180142.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $0\src32__data_o$next[1:0]$11160 - attribute \src "libresoc.v:178255.3-178256.43" + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $0\src32__data_o$next[1:0]$11259 + attribute \src "libresoc.v:180139.3-180140.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:178553.3-178588.6" - wire $0\wr_detect$10[0:0]$11185 - attribute \src "libresoc.v:178389.3-178424.6" - wire $0\wr_detect$4[0:0]$11153 - attribute \src "libresoc.v:178471.3-178506.6" - wire $0\wr_detect$7[0:0]$11169 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180437.3-180472.6" + wire $0\wr_detect$10[0:0]$11284 + attribute \src "libresoc.v:180273.3-180308.6" + wire $0\wr_detect$4[0:0]$11252 + attribute \src "libresoc.v:180355.3-180390.6" + wire $0\wr_detect$7[0:0]$11268 + attribute \src "libresoc.v:180191.3-180226.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $1\r2__data_o$next[1:0]$11177 - attribute \src "libresoc.v:178205.13-178205.30" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $1\r2__data_o$next[1:0]$11276 + attribute \src "libresoc.v:180089.13-180089.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $1\reg$next[1:0]$11193 - attribute \src "libresoc.v:178211.13-178211.25" + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $1\reg$next[1:0]$11292 + attribute \src "libresoc.v:180095.13-180095.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $1\src12__data_o$next[1:0]$11135 - attribute \src "libresoc.v:178216.13-178216.33" + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $1\src12__data_o$next[1:0]$11234 + attribute \src "libresoc.v:180100.13-180100.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $1\src22__data_o$next[1:0]$11145 - attribute \src "libresoc.v:178223.13-178223.33" + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $1\src22__data_o$next[1:0]$11244 + attribute \src "libresoc.v:180107.13-180107.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $1\src32__data_o$next[1:0]$11161 - attribute \src "libresoc.v:178230.13-178230.33" + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $1\src32__data_o$next[1:0]$11260 + attribute \src "libresoc.v:180114.13-180114.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:178553.3-178588.6" - wire $1\wr_detect$10[0:0]$11186 - attribute \src "libresoc.v:178389.3-178424.6" - wire $1\wr_detect$4[0:0]$11154 - attribute \src "libresoc.v:178471.3-178506.6" - wire $1\wr_detect$7[0:0]$11170 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180437.3-180472.6" + wire $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180273.3-180308.6" + wire $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180355.3-180390.6" + wire $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180191.3-180226.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $2\r2__data_o$next[1:0]$11178 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $2\reg$next[1:0]$11194 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $2\src12__data_o$next[1:0]$11136 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $2\src22__data_o$next[1:0]$11146 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $2\src32__data_o$next[1:0]$11162 - attribute \src "libresoc.v:178553.3-178588.6" - wire $2\wr_detect$10[0:0]$11187 - attribute \src "libresoc.v:178389.3-178424.6" - wire $2\wr_detect$4[0:0]$11155 - attribute \src "libresoc.v:178471.3-178506.6" - wire $2\wr_detect$7[0:0]$11171 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $2\r2__data_o$next[1:0]$11277 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $2\reg$next[1:0]$11293 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $2\src12__data_o$next[1:0]$11235 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $2\src22__data_o$next[1:0]$11245 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $2\src32__data_o$next[1:0]$11261 + attribute \src "libresoc.v:180437.3-180472.6" + wire $2\wr_detect$10[0:0]$11286 + attribute \src "libresoc.v:180273.3-180308.6" + wire $2\wr_detect$4[0:0]$11254 + attribute \src "libresoc.v:180355.3-180390.6" + wire $2\wr_detect$7[0:0]$11270 + attribute \src "libresoc.v:180191.3-180226.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $3\r2__data_o$next[1:0]$11179 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $3\reg$next[1:0]$11195 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $3\src12__data_o$next[1:0]$11137 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $3\src22__data_o$next[1:0]$11147 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $3\src32__data_o$next[1:0]$11163 - attribute \src "libresoc.v:178553.3-178588.6" - wire $3\wr_detect$10[0:0]$11188 - attribute \src "libresoc.v:178389.3-178424.6" - wire $3\wr_detect$4[0:0]$11156 - attribute \src "libresoc.v:178471.3-178506.6" - wire $3\wr_detect$7[0:0]$11172 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $3\r2__data_o$next[1:0]$11278 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $3\reg$next[1:0]$11294 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $3\src12__data_o$next[1:0]$11236 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $3\src22__data_o$next[1:0]$11246 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $3\src32__data_o$next[1:0]$11262 + attribute \src "libresoc.v:180437.3-180472.6" + wire $3\wr_detect$10[0:0]$11287 + attribute \src "libresoc.v:180273.3-180308.6" + wire $3\wr_detect$4[0:0]$11255 + attribute \src "libresoc.v:180355.3-180390.6" + wire $3\wr_detect$7[0:0]$11271 + attribute \src "libresoc.v:180191.3-180226.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $4\r2__data_o$next[1:0]$11180 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $4\reg$next[1:0]$11196 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $4\src12__data_o$next[1:0]$11138 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $4\src22__data_o$next[1:0]$11148 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $4\src32__data_o$next[1:0]$11164 - attribute \src "libresoc.v:178553.3-178588.6" - wire $4\wr_detect$10[0:0]$11189 - attribute \src "libresoc.v:178389.3-178424.6" - wire $4\wr_detect$4[0:0]$11157 - attribute \src "libresoc.v:178471.3-178506.6" - wire $4\wr_detect$7[0:0]$11173 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $4\r2__data_o$next[1:0]$11279 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $4\reg$next[1:0]$11295 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $4\src12__data_o$next[1:0]$11237 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $4\src22__data_o$next[1:0]$11247 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $4\src32__data_o$next[1:0]$11263 + attribute \src "libresoc.v:180437.3-180472.6" + wire $4\wr_detect$10[0:0]$11288 + attribute \src "libresoc.v:180273.3-180308.6" + wire $4\wr_detect$4[0:0]$11256 + attribute \src "libresoc.v:180355.3-180390.6" + wire $4\wr_detect$7[0:0]$11272 + attribute \src "libresoc.v:180191.3-180226.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $5\r2__data_o$next[1:0]$11181 - attribute \src "libresoc.v:178589.3-178621.6" - wire width 2 $5\reg$next[1:0]$11197 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $5\src12__data_o$next[1:0]$11139 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $5\src22__data_o$next[1:0]$11149 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $5\src32__data_o$next[1:0]$11165 - attribute \src "libresoc.v:178553.3-178588.6" - wire $5\wr_detect$10[0:0]$11190 - attribute \src "libresoc.v:178389.3-178424.6" - wire $5\wr_detect$4[0:0]$11158 - attribute \src "libresoc.v:178471.3-178506.6" - wire $5\wr_detect$7[0:0]$11174 - attribute \src "libresoc.v:178307.3-178342.6" + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $5\r2__data_o$next[1:0]$11280 + attribute \src "libresoc.v:180473.3-180505.6" + wire width 2 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $5\src12__data_o$next[1:0]$11238 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $5\src22__data_o$next[1:0]$11248 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $5\src32__data_o$next[1:0]$11264 + attribute \src "libresoc.v:180437.3-180472.6" + wire $5\wr_detect$10[0:0]$11289 + attribute \src "libresoc.v:180273.3-180308.6" + wire $5\wr_detect$4[0:0]$11257 + attribute \src "libresoc.v:180355.3-180390.6" + wire $5\wr_detect$7[0:0]$11273 + attribute \src "libresoc.v:180191.3-180226.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $6\r2__data_o$next[1:0]$11182 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $6\src12__data_o$next[1:0]$11140 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $6\src22__data_o$next[1:0]$11150 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $6\src32__data_o$next[1:0]$11166 - attribute \src "libresoc.v:178507.3-178552.6" - wire width 2 $7\r2__data_o$next[1:0]$11183 - attribute \src "libresoc.v:178261.3-178306.6" - wire width 2 $7\src12__data_o$next[1:0]$11141 - attribute \src "libresoc.v:178343.3-178388.6" - wire width 2 $7\src22__data_o$next[1:0]$11151 - attribute \src "libresoc.v:178425.3-178470.6" - wire width 2 $7\src32__data_o$next[1:0]$11167 - attribute \src "libresoc.v:178247.17-178247.104" - wire $not$libresoc.v:178247$11124_Y - attribute \src "libresoc.v:178248.17-178248.100" - wire $not$libresoc.v:178248$11125_Y - attribute \src "libresoc.v:178249.17-178249.103" - wire $not$libresoc.v:178249$11126_Y - attribute \src "libresoc.v:178250.17-178250.103" - wire $not$libresoc.v:178250$11127_Y + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $6\r2__data_o$next[1:0]$11281 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $6\src12__data_o$next[1:0]$11239 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $6\src22__data_o$next[1:0]$11249 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $6\src32__data_o$next[1:0]$11265 + attribute \src "libresoc.v:180391.3-180436.6" + wire width 2 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180145.3-180190.6" + wire width 2 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180227.3-180272.6" + wire width 2 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180309.3-180354.6" + wire width 2 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180131.17-180131.104" + wire $not$libresoc.v:180131$11223_Y + attribute \src "libresoc.v:180132.17-180132.100" + wire $not$libresoc.v:180132$11224_Y + attribute \src "libresoc.v:180133.17-180133.103" + wire $not$libresoc.v:180133$11225_Y + attribute \src "libresoc.v:180134.17-180134.103" + wire $not$libresoc.v:180134$11226_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367215,9 +370279,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -367231,7 +370295,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:178178.7-178178.15" + attribute \src "libresoc.v:180062.7-180062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -367274,129 +370338,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178247$11124 + cell $not $not$libresoc.v:180131$11223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178247$11124_Y + connect \Y $not$libresoc.v:180131$11223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178248$11125 + cell $not $not$libresoc.v:180132$11224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178248$11125_Y + connect \Y $not$libresoc.v:180132$11224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178249$11126 + cell $not $not$libresoc.v:180133$11225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178249$11126_Y + connect \Y $not$libresoc.v:180133$11225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178250$11127 + cell $not $not$libresoc.v:180134$11226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178250$11127_Y + connect \Y $not$libresoc.v:180134$11226_Y end - attribute \src "libresoc.v:178178.7-178178.20" - process $proc$libresoc.v:178178$11198 + attribute \src "libresoc.v:180062.7-180062.20" + process $proc$libresoc.v:180062$11297 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178205.13-178205.30" - process $proc$libresoc.v:178205$11199 + attribute \src "libresoc.v:180089.13-180089.30" + process $proc$libresoc.v:180089$11298 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:178211.13-178211.25" - process $proc$libresoc.v:178211$11200 + attribute \src "libresoc.v:180095.13-180095.25" + process $proc$libresoc.v:180095$11299 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178216.13-178216.33" - process $proc$libresoc.v:178216$11201 + attribute \src "libresoc.v:180100.13-180100.33" + process $proc$libresoc.v:180100$11300 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:178223.13-178223.33" - process $proc$libresoc.v:178223$11202 + attribute \src "libresoc.v:180107.13-180107.33" + process $proc$libresoc.v:180107$11301 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:178230.13-178230.33" - process $proc$libresoc.v:178230$11203 + attribute \src "libresoc.v:180114.13-180114.33" + process $proc$libresoc.v:180114$11302 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:178251.3-178252.25" - process $proc$libresoc.v:178251$11128 + attribute \src "libresoc.v:180135.3-180136.25" + process $proc$libresoc.v:180135$11227 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178253.3-178254.37" - process $proc$libresoc.v:178253$11129 + attribute \src "libresoc.v:180137.3-180138.37" + process $proc$libresoc.v:180137$11228 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:178255.3-178256.43" - process $proc$libresoc.v:178255$11130 + attribute \src "libresoc.v:180139.3-180140.43" + process $proc$libresoc.v:180139$11229 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:178257.3-178258.43" - process $proc$libresoc.v:178257$11131 + attribute \src "libresoc.v:180141.3-180142.43" + process $proc$libresoc.v:180141$11230 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:178259.3-178260.43" - process $proc$libresoc.v:178259$11132 + attribute \src "libresoc.v:180143.3-180144.43" + process $proc$libresoc.v:180143$11231 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:178261.3-178306.6" - process $proc$libresoc.v:178261$11133 + attribute \src "libresoc.v:180145.3-180190.6" + process $proc$libresoc.v:180145$11232 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11134 $7\src12__data_o$next[1:0]$11141 - attribute \src "libresoc.v:178262.5-178262.29" + assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 + attribute \src "libresoc.v:180146.5-180146.29" switch \initial - attribute \src "libresoc.v:178262.9-178262.17" + attribute \src "libresoc.v:180146.9-180146.17" case 1'1 case end @@ -367409,75 +370473,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11135 $6\src12__data_o$next[1:0]$11140 + assign $1\src12__data_o$next[1:0]$11234 $6\src12__data_o$next[1:0]$11239 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11136 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11235 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11136 2'00 + assign $2\src12__data_o$next[1:0]$11235 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11137 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11236 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11137 $2\src12__data_o$next[1:0]$11136 + assign $3\src12__data_o$next[1:0]$11236 $2\src12__data_o$next[1:0]$11235 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11138 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11237 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11138 $3\src12__data_o$next[1:0]$11137 + assign $4\src12__data_o$next[1:0]$11237 $3\src12__data_o$next[1:0]$11236 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11139 \w2__data_i + assign $5\src12__data_o$next[1:0]$11238 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11139 $4\src12__data_o$next[1:0]$11138 + assign $5\src12__data_o$next[1:0]$11238 $4\src12__data_o$next[1:0]$11237 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11140 \reg + assign $6\src12__data_o$next[1:0]$11239 \reg case - assign $6\src12__data_o$next[1:0]$11140 $5\src12__data_o$next[1:0]$11139 + assign $6\src12__data_o$next[1:0]$11239 $5\src12__data_o$next[1:0]$11238 end case - assign $1\src12__data_o$next[1:0]$11135 2'00 + assign $1\src12__data_o$next[1:0]$11234 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11141 2'00 + assign $7\src12__data_o$next[1:0]$11240 2'00 case - assign $7\src12__data_o$next[1:0]$11141 $1\src12__data_o$next[1:0]$11135 + assign $7\src12__data_o$next[1:0]$11240 $1\src12__data_o$next[1:0]$11234 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11134 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 end - attribute \src "libresoc.v:178307.3-178342.6" - process $proc$libresoc.v:178307$11142 + attribute \src "libresoc.v:180191.3-180226.6" + process $proc$libresoc.v:180191$11241 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178308.5-178308.29" + attribute \src "libresoc.v:180192.5-180192.29" switch \initial - attribute \src "libresoc.v:178308.9-178308.17" + attribute \src "libresoc.v:180192.9-180192.17" case 1'1 case end @@ -367533,15 +370597,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178343.3-178388.6" - process $proc$libresoc.v:178343$11143 + attribute \src "libresoc.v:180227.3-180272.6" + process $proc$libresoc.v:180227$11242 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11144 $7\src22__data_o$next[1:0]$11151 - attribute \src "libresoc.v:178344.5-178344.29" + assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 + attribute \src "libresoc.v:180228.5-180228.29" switch \initial - attribute \src "libresoc.v:178344.9-178344.17" + attribute \src "libresoc.v:180228.9-180228.17" case 1'1 case end @@ -367554,75 +370618,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11145 $6\src22__data_o$next[1:0]$11150 + assign $1\src22__data_o$next[1:0]$11244 $6\src22__data_o$next[1:0]$11249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11146 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11245 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11146 2'00 + assign $2\src22__data_o$next[1:0]$11245 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11147 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11246 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11147 $2\src22__data_o$next[1:0]$11146 + assign $3\src22__data_o$next[1:0]$11246 $2\src22__data_o$next[1:0]$11245 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11148 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11247 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11148 $3\src22__data_o$next[1:0]$11147 + assign $4\src22__data_o$next[1:0]$11247 $3\src22__data_o$next[1:0]$11246 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11149 \w2__data_i + assign $5\src22__data_o$next[1:0]$11248 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11149 $4\src22__data_o$next[1:0]$11148 + assign $5\src22__data_o$next[1:0]$11248 $4\src22__data_o$next[1:0]$11247 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11150 \reg + assign $6\src22__data_o$next[1:0]$11249 \reg case - assign $6\src22__data_o$next[1:0]$11150 $5\src22__data_o$next[1:0]$11149 + assign $6\src22__data_o$next[1:0]$11249 $5\src22__data_o$next[1:0]$11248 end case - assign $1\src22__data_o$next[1:0]$11145 2'00 + assign $1\src22__data_o$next[1:0]$11244 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11151 2'00 + assign $7\src22__data_o$next[1:0]$11250 2'00 case - assign $7\src22__data_o$next[1:0]$11151 $1\src22__data_o$next[1:0]$11145 + assign $7\src22__data_o$next[1:0]$11250 $1\src22__data_o$next[1:0]$11244 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11144 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 end - attribute \src "libresoc.v:178389.3-178424.6" - process $proc$libresoc.v:178389$11152 + attribute \src "libresoc.v:180273.3-180308.6" + process $proc$libresoc.v:180273$11251 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11153 $1\wr_detect$4[0:0]$11154 - attribute \src "libresoc.v:178390.5-178390.29" + assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 + attribute \src "libresoc.v:180274.5-180274.29" switch \initial - attribute \src "libresoc.v:178390.9-178390.17" + attribute \src "libresoc.v:180274.9-180274.17" case 1'1 case end @@ -367635,58 +370699,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11154 $5\wr_detect$4[0:0]$11158 + assign $1\wr_detect$4[0:0]$11253 $5\wr_detect$4[0:0]$11257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11155 1'1 + assign $2\wr_detect$4[0:0]$11254 1'1 case - assign $2\wr_detect$4[0:0]$11155 1'0 + assign $2\wr_detect$4[0:0]$11254 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11156 1'1 + assign $3\wr_detect$4[0:0]$11255 1'1 case - assign $3\wr_detect$4[0:0]$11156 $2\wr_detect$4[0:0]$11155 + assign $3\wr_detect$4[0:0]$11255 $2\wr_detect$4[0:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11157 1'1 + assign $4\wr_detect$4[0:0]$11256 1'1 case - assign $4\wr_detect$4[0:0]$11157 $3\wr_detect$4[0:0]$11156 + assign $4\wr_detect$4[0:0]$11256 $3\wr_detect$4[0:0]$11255 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11158 1'1 + assign $5\wr_detect$4[0:0]$11257 1'1 case - assign $5\wr_detect$4[0:0]$11158 $4\wr_detect$4[0:0]$11157 + assign $5\wr_detect$4[0:0]$11257 $4\wr_detect$4[0:0]$11256 end case - assign $1\wr_detect$4[0:0]$11154 1'0 + assign $1\wr_detect$4[0:0]$11253 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11153 + update \wr_detect$4 $0\wr_detect$4[0:0]$11252 end - attribute \src "libresoc.v:178425.3-178470.6" - process $proc$libresoc.v:178425$11159 + attribute \src "libresoc.v:180309.3-180354.6" + process $proc$libresoc.v:180309$11258 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11160 $7\src32__data_o$next[1:0]$11167 - attribute \src "libresoc.v:178426.5-178426.29" + assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 + attribute \src "libresoc.v:180310.5-180310.29" switch \initial - attribute \src "libresoc.v:178426.9-178426.17" + attribute \src "libresoc.v:180310.9-180310.17" case 1'1 case end @@ -367699,75 +370763,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11161 $6\src32__data_o$next[1:0]$11166 + assign $1\src32__data_o$next[1:0]$11260 $6\src32__data_o$next[1:0]$11265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11162 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11261 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11162 2'00 + assign $2\src32__data_o$next[1:0]$11261 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11163 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11262 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11163 $2\src32__data_o$next[1:0]$11162 + assign $3\src32__data_o$next[1:0]$11262 $2\src32__data_o$next[1:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11164 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11263 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11164 $3\src32__data_o$next[1:0]$11163 + assign $4\src32__data_o$next[1:0]$11263 $3\src32__data_o$next[1:0]$11262 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11165 \w2__data_i + assign $5\src32__data_o$next[1:0]$11264 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11165 $4\src32__data_o$next[1:0]$11164 + assign $5\src32__data_o$next[1:0]$11264 $4\src32__data_o$next[1:0]$11263 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11166 \reg + assign $6\src32__data_o$next[1:0]$11265 \reg case - assign $6\src32__data_o$next[1:0]$11166 $5\src32__data_o$next[1:0]$11165 + assign $6\src32__data_o$next[1:0]$11265 $5\src32__data_o$next[1:0]$11264 end case - assign $1\src32__data_o$next[1:0]$11161 2'00 + assign $1\src32__data_o$next[1:0]$11260 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11167 2'00 + assign $7\src32__data_o$next[1:0]$11266 2'00 case - assign $7\src32__data_o$next[1:0]$11167 $1\src32__data_o$next[1:0]$11161 + assign $7\src32__data_o$next[1:0]$11266 $1\src32__data_o$next[1:0]$11260 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11160 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 end - attribute \src "libresoc.v:178471.3-178506.6" - process $proc$libresoc.v:178471$11168 + attribute \src "libresoc.v:180355.3-180390.6" + process $proc$libresoc.v:180355$11267 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11169 $1\wr_detect$7[0:0]$11170 - attribute \src "libresoc.v:178472.5-178472.29" + assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 + attribute \src "libresoc.v:180356.5-180356.29" switch \initial - attribute \src "libresoc.v:178472.9-178472.17" + attribute \src "libresoc.v:180356.9-180356.17" case 1'1 case end @@ -367780,58 +370844,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11170 $5\wr_detect$7[0:0]$11174 + assign $1\wr_detect$7[0:0]$11269 $5\wr_detect$7[0:0]$11273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11171 1'1 + assign $2\wr_detect$7[0:0]$11270 1'1 case - assign $2\wr_detect$7[0:0]$11171 1'0 + assign $2\wr_detect$7[0:0]$11270 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11172 1'1 + assign $3\wr_detect$7[0:0]$11271 1'1 case - assign $3\wr_detect$7[0:0]$11172 $2\wr_detect$7[0:0]$11171 + assign $3\wr_detect$7[0:0]$11271 $2\wr_detect$7[0:0]$11270 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11173 1'1 + assign $4\wr_detect$7[0:0]$11272 1'1 case - assign $4\wr_detect$7[0:0]$11173 $3\wr_detect$7[0:0]$11172 + assign $4\wr_detect$7[0:0]$11272 $3\wr_detect$7[0:0]$11271 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11174 1'1 + assign $5\wr_detect$7[0:0]$11273 1'1 case - assign $5\wr_detect$7[0:0]$11174 $4\wr_detect$7[0:0]$11173 + assign $5\wr_detect$7[0:0]$11273 $4\wr_detect$7[0:0]$11272 end case - assign $1\wr_detect$7[0:0]$11170 1'0 + assign $1\wr_detect$7[0:0]$11269 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11169 + update \wr_detect$7 $0\wr_detect$7[0:0]$11268 end - attribute \src "libresoc.v:178507.3-178552.6" - process $proc$libresoc.v:178507$11175 + attribute \src "libresoc.v:180391.3-180436.6" + process $proc$libresoc.v:180391$11274 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11176 $7\r2__data_o$next[1:0]$11183 - attribute \src "libresoc.v:178508.5-178508.29" + assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 + attribute \src "libresoc.v:180392.5-180392.29" switch \initial - attribute \src "libresoc.v:178508.9-178508.17" + attribute \src "libresoc.v:180392.9-180392.17" case 1'1 case end @@ -367844,75 +370908,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11177 $6\r2__data_o$next[1:0]$11182 + assign $1\r2__data_o$next[1:0]$11276 $6\r2__data_o$next[1:0]$11281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11178 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11277 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11178 2'00 + assign $2\r2__data_o$next[1:0]$11277 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11179 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11278 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11179 $2\r2__data_o$next[1:0]$11178 + assign $3\r2__data_o$next[1:0]$11278 $2\r2__data_o$next[1:0]$11277 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11180 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11279 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11180 $3\r2__data_o$next[1:0]$11179 + assign $4\r2__data_o$next[1:0]$11279 $3\r2__data_o$next[1:0]$11278 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11181 \w2__data_i + assign $5\r2__data_o$next[1:0]$11280 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11181 $4\r2__data_o$next[1:0]$11180 + assign $5\r2__data_o$next[1:0]$11280 $4\r2__data_o$next[1:0]$11279 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11182 \reg + assign $6\r2__data_o$next[1:0]$11281 \reg case - assign $6\r2__data_o$next[1:0]$11182 $5\r2__data_o$next[1:0]$11181 + assign $6\r2__data_o$next[1:0]$11281 $5\r2__data_o$next[1:0]$11280 end case - assign $1\r2__data_o$next[1:0]$11177 2'00 + assign $1\r2__data_o$next[1:0]$11276 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11183 2'00 + assign $7\r2__data_o$next[1:0]$11282 2'00 case - assign $7\r2__data_o$next[1:0]$11183 $1\r2__data_o$next[1:0]$11177 + assign $7\r2__data_o$next[1:0]$11282 $1\r2__data_o$next[1:0]$11276 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11176 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 end - attribute \src "libresoc.v:178553.3-178588.6" - process $proc$libresoc.v:178553$11184 + attribute \src "libresoc.v:180437.3-180472.6" + process $proc$libresoc.v:180437$11283 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11185 $1\wr_detect$10[0:0]$11186 - attribute \src "libresoc.v:178554.5-178554.29" + assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 + attribute \src "libresoc.v:180438.5-180438.29" switch \initial - attribute \src "libresoc.v:178554.9-178554.17" + attribute \src "libresoc.v:180438.9-180438.17" case 1'1 case end @@ -367925,61 +370989,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11186 $5\wr_detect$10[0:0]$11190 + assign $1\wr_detect$10[0:0]$11285 $5\wr_detect$10[0:0]$11289 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11187 1'1 + assign $2\wr_detect$10[0:0]$11286 1'1 case - assign $2\wr_detect$10[0:0]$11187 1'0 + assign $2\wr_detect$10[0:0]$11286 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11188 1'1 + assign $3\wr_detect$10[0:0]$11287 1'1 case - assign $3\wr_detect$10[0:0]$11188 $2\wr_detect$10[0:0]$11187 + assign $3\wr_detect$10[0:0]$11287 $2\wr_detect$10[0:0]$11286 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11189 1'1 + assign $4\wr_detect$10[0:0]$11288 1'1 case - assign $4\wr_detect$10[0:0]$11189 $3\wr_detect$10[0:0]$11188 + assign $4\wr_detect$10[0:0]$11288 $3\wr_detect$10[0:0]$11287 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11190 1'1 + assign $5\wr_detect$10[0:0]$11289 1'1 case - assign $5\wr_detect$10[0:0]$11190 $4\wr_detect$10[0:0]$11189 + assign $5\wr_detect$10[0:0]$11289 $4\wr_detect$10[0:0]$11288 end case - assign $1\wr_detect$10[0:0]$11186 1'0 + assign $1\wr_detect$10[0:0]$11285 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11185 + update \wr_detect$10 $0\wr_detect$10[0:0]$11284 end - attribute \src "libresoc.v:178589.3-178621.6" - process $proc$libresoc.v:178589$11191 + attribute \src "libresoc.v:180473.3-180505.6" + process $proc$libresoc.v:180473$11290 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11192 $5\reg$next[1:0]$11197 - attribute \src "libresoc.v:178590.5-178590.29" + assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 + attribute \src "libresoc.v:180474.5-180474.29" switch \initial - attribute \src "libresoc.v:178590.9-178590.17" + attribute \src "libresoc.v:180474.9-180474.17" case 1'1 case end @@ -367988,179 +371052,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11193 \dest12__data_i + assign $1\reg$next[1:0]$11292 \dest12__data_i case - assign $1\reg$next[1:0]$11193 \reg + assign $1\reg$next[1:0]$11292 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11194 \dest22__data_i + assign $2\reg$next[1:0]$11293 \dest22__data_i case - assign $2\reg$next[1:0]$11194 $1\reg$next[1:0]$11193 + assign $2\reg$next[1:0]$11293 $1\reg$next[1:0]$11292 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11195 \dest32__data_i + assign $3\reg$next[1:0]$11294 \dest32__data_i case - assign $3\reg$next[1:0]$11195 $2\reg$next[1:0]$11194 + assign $3\reg$next[1:0]$11294 $2\reg$next[1:0]$11293 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11196 \w2__data_i + assign $4\reg$next[1:0]$11295 \w2__data_i case - assign $4\reg$next[1:0]$11196 $3\reg$next[1:0]$11195 + assign $4\reg$next[1:0]$11295 $3\reg$next[1:0]$11294 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11197 2'00 + assign $5\reg$next[1:0]$11296 2'00 case - assign $5\reg$next[1:0]$11197 $4\reg$next[1:0]$11196 + assign $5\reg$next[1:0]$11296 $4\reg$next[1:0]$11295 end sync always - update \reg$next $0\reg$next[1:0]$11192 + update \reg$next $0\reg$next[1:0]$11291 end - connect \$9 $not$libresoc.v:178247$11124_Y - connect \$1 $not$libresoc.v:178248$11125_Y - connect \$3 $not$libresoc.v:178249$11126_Y - connect \$6 $not$libresoc.v:178250$11127_Y + connect \$9 $not$libresoc.v:180131$11223_Y + connect \$1 $not$libresoc.v:180132$11224_Y + connect \$3 $not$libresoc.v:180133$11225_Y + connect \$6 $not$libresoc.v:180134$11226_Y end -attribute \src "libresoc.v:178626.1-178975.10" +attribute \src "libresoc.v:180510.1-180859.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $0\cia2__data_o$next[63:0]$11212 - attribute \src "libresoc.v:178694.3-178695.41" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $0\cia2__data_o$next[63:0]$11311 + attribute \src "libresoc.v:180578.3-180579.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:178627.7-178627.20" + attribute \src "libresoc.v:180511.7-180511.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $0\msr2__data_o$next[63:0]$11222 - attribute \src "libresoc.v:178692.3-178693.41" + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $0\msr2__data_o$next[63:0]$11321 + attribute \src "libresoc.v:180576.3-180577.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $0\reg$next[63:0]$11254 - attribute \src "libresoc.v:178688.3-178689.25" + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $0\reg$next[63:0]$11353 + attribute \src "libresoc.v:180572.3-180573.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $0\sv2__data_o$next[63:0]$11238 - attribute \src "libresoc.v:178690.3-178691.39" + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $0\sv2__data_o$next[63:0]$11337 + attribute \src "libresoc.v:180574.3-180575.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:178824.3-178859.6" - wire $0\wr_detect$4[0:0]$11231 - attribute \src "libresoc.v:178906.3-178941.6" - wire $0\wr_detect$7[0:0]$11247 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180708.3-180743.6" + wire $0\wr_detect$4[0:0]$11330 + attribute \src "libresoc.v:180790.3-180825.6" + wire $0\wr_detect$7[0:0]$11346 + attribute \src "libresoc.v:180626.3-180661.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $1\cia2__data_o$next[63:0]$11213 - attribute \src "libresoc.v:178636.14-178636.49" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $1\cia2__data_o$next[63:0]$11312 + attribute \src "libresoc.v:180520.14-180520.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $1\msr2__data_o$next[63:0]$11223 - attribute \src "libresoc.v:178653.14-178653.49" + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $1\msr2__data_o$next[63:0]$11322 + attribute \src "libresoc.v:180537.14-180537.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $1\reg$next[63:0]$11255 - attribute \src "libresoc.v:178665.14-178665.42" + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $1\reg$next[63:0]$11354 + attribute \src "libresoc.v:180549.14-180549.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $1\sv2__data_o$next[63:0]$11239 - attribute \src "libresoc.v:178672.14-178672.48" + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $1\sv2__data_o$next[63:0]$11338 + attribute \src "libresoc.v:180556.14-180556.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:178824.3-178859.6" - wire $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:178906.3-178941.6" - wire $1\wr_detect$7[0:0]$11248 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180708.3-180743.6" + wire $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180790.3-180825.6" + wire $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180626.3-180661.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $2\cia2__data_o$next[63:0]$11214 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $2\msr2__data_o$next[63:0]$11224 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $2\reg$next[63:0]$11256 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $2\sv2__data_o$next[63:0]$11240 - attribute \src "libresoc.v:178824.3-178859.6" - wire $2\wr_detect$4[0:0]$11233 - attribute \src "libresoc.v:178906.3-178941.6" - wire $2\wr_detect$7[0:0]$11249 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $2\cia2__data_o$next[63:0]$11313 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $2\msr2__data_o$next[63:0]$11323 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $2\reg$next[63:0]$11355 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $2\sv2__data_o$next[63:0]$11339 + attribute \src "libresoc.v:180708.3-180743.6" + wire $2\wr_detect$4[0:0]$11332 + attribute \src "libresoc.v:180790.3-180825.6" + wire $2\wr_detect$7[0:0]$11348 + attribute \src "libresoc.v:180626.3-180661.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $3\cia2__data_o$next[63:0]$11215 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $3\msr2__data_o$next[63:0]$11225 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $3\reg$next[63:0]$11257 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $3\sv2__data_o$next[63:0]$11241 - attribute \src "libresoc.v:178824.3-178859.6" - wire $3\wr_detect$4[0:0]$11234 - attribute \src "libresoc.v:178906.3-178941.6" - wire $3\wr_detect$7[0:0]$11250 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $3\cia2__data_o$next[63:0]$11314 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $3\msr2__data_o$next[63:0]$11324 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $3\reg$next[63:0]$11356 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $3\sv2__data_o$next[63:0]$11340 + attribute \src "libresoc.v:180708.3-180743.6" + wire $3\wr_detect$4[0:0]$11333 + attribute \src "libresoc.v:180790.3-180825.6" + wire $3\wr_detect$7[0:0]$11349 + attribute \src "libresoc.v:180626.3-180661.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $4\cia2__data_o$next[63:0]$11216 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $4\msr2__data_o$next[63:0]$11226 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $4\reg$next[63:0]$11258 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $4\sv2__data_o$next[63:0]$11242 - attribute \src "libresoc.v:178824.3-178859.6" - wire $4\wr_detect$4[0:0]$11235 - attribute \src "libresoc.v:178906.3-178941.6" - wire $4\wr_detect$7[0:0]$11251 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $4\cia2__data_o$next[63:0]$11315 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $4\msr2__data_o$next[63:0]$11325 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $4\reg$next[63:0]$11357 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $4\sv2__data_o$next[63:0]$11341 + attribute \src "libresoc.v:180708.3-180743.6" + wire $4\wr_detect$4[0:0]$11334 + attribute \src "libresoc.v:180790.3-180825.6" + wire $4\wr_detect$7[0:0]$11350 + attribute \src "libresoc.v:180626.3-180661.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $5\cia2__data_o$next[63:0]$11217 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $5\msr2__data_o$next[63:0]$11227 - attribute \src "libresoc.v:178942.3-178974.6" - wire width 64 $5\reg$next[63:0]$11259 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $5\sv2__data_o$next[63:0]$11243 - attribute \src "libresoc.v:178824.3-178859.6" - wire $5\wr_detect$4[0:0]$11236 - attribute \src "libresoc.v:178906.3-178941.6" - wire $5\wr_detect$7[0:0]$11252 - attribute \src "libresoc.v:178742.3-178777.6" + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $5\cia2__data_o$next[63:0]$11316 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $5\msr2__data_o$next[63:0]$11326 + attribute \src "libresoc.v:180826.3-180858.6" + wire width 64 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $5\sv2__data_o$next[63:0]$11342 + attribute \src "libresoc.v:180708.3-180743.6" + wire $5\wr_detect$4[0:0]$11335 + attribute \src "libresoc.v:180790.3-180825.6" + wire $5\wr_detect$7[0:0]$11351 + attribute \src "libresoc.v:180626.3-180661.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $6\cia2__data_o$next[63:0]$11218 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $6\msr2__data_o$next[63:0]$11228 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $6\sv2__data_o$next[63:0]$11244 - attribute \src "libresoc.v:178696.3-178741.6" - wire width 64 $7\cia2__data_o$next[63:0]$11219 - attribute \src "libresoc.v:178778.3-178823.6" - wire width 64 $7\msr2__data_o$next[63:0]$11229 - attribute \src "libresoc.v:178860.3-178905.6" - wire width 64 $7\sv2__data_o$next[63:0]$11245 - attribute \src "libresoc.v:178685.17-178685.100" - wire $not$libresoc.v:178685$11204_Y - attribute \src "libresoc.v:178686.17-178686.103" - wire $not$libresoc.v:178686$11205_Y - attribute \src "libresoc.v:178687.17-178687.103" - wire $not$libresoc.v:178687$11206_Y + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $6\cia2__data_o$next[63:0]$11317 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $6\msr2__data_o$next[63:0]$11327 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $6\sv2__data_o$next[63:0]$11343 + attribute \src "libresoc.v:180580.3-180625.6" + wire width 64 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180662.3-180707.6" + wire width 64 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180744.3-180789.6" + wire width 64 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180569.17-180569.100" + wire $not$libresoc.v:180569$11303_Y + attribute \src "libresoc.v:180570.17-180570.103" + wire $not$libresoc.v:180570$11304_Y + attribute \src "libresoc.v:180571.17-180571.103" + wire $not$libresoc.v:180571$11305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368173,15 +371237,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:178627.7-178627.15" + attribute \src "libresoc.v:180511.7-180511.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -368218,106 +371282,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178685$11204 + cell $not $not$libresoc.v:180569$11303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178685$11204_Y + connect \Y $not$libresoc.v:180569$11303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178686$11205 + cell $not $not$libresoc.v:180570$11304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178686$11205_Y + connect \Y $not$libresoc.v:180570$11304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178687$11206 + cell $not $not$libresoc.v:180571$11305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178687$11206_Y + connect \Y $not$libresoc.v:180571$11305_Y end - attribute \src "libresoc.v:178627.7-178627.20" - process $proc$libresoc.v:178627$11260 + attribute \src "libresoc.v:180511.7-180511.20" + process $proc$libresoc.v:180511$11359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178636.14-178636.49" - process $proc$libresoc.v:178636$11261 + attribute \src "libresoc.v:180520.14-180520.49" + process $proc$libresoc.v:180520$11360 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:178653.14-178653.49" - process $proc$libresoc.v:178653$11262 + attribute \src "libresoc.v:180537.14-180537.49" + process $proc$libresoc.v:180537$11361 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:178665.14-178665.42" - process $proc$libresoc.v:178665$11263 + attribute \src "libresoc.v:180549.14-180549.42" + process $proc$libresoc.v:180549$11362 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:178672.14-178672.48" - process $proc$libresoc.v:178672$11264 + attribute \src "libresoc.v:180556.14-180556.48" + process $proc$libresoc.v:180556$11363 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:178688.3-178689.25" - process $proc$libresoc.v:178688$11207 + attribute \src "libresoc.v:180572.3-180573.25" + process $proc$libresoc.v:180572$11306 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:178690.3-178691.39" - process $proc$libresoc.v:178690$11208 + attribute \src "libresoc.v:180574.3-180575.39" + process $proc$libresoc.v:180574$11307 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:178692.3-178693.41" - process $proc$libresoc.v:178692$11209 + attribute \src "libresoc.v:180576.3-180577.41" + process $proc$libresoc.v:180576$11308 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:178694.3-178695.41" - process $proc$libresoc.v:178694$11210 + attribute \src "libresoc.v:180578.3-180579.41" + process $proc$libresoc.v:180578$11309 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:178696.3-178741.6" - process $proc$libresoc.v:178696$11211 + attribute \src "libresoc.v:180580.3-180625.6" + process $proc$libresoc.v:180580$11310 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11212 $7\cia2__data_o$next[63:0]$11219 - attribute \src "libresoc.v:178697.5-178697.29" + assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 + attribute \src "libresoc.v:180581.5-180581.29" switch \initial - attribute \src "libresoc.v:178697.9-178697.17" + attribute \src "libresoc.v:180581.9-180581.17" case 1'1 case end @@ -368330,75 +371394,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11213 $6\cia2__data_o$next[63:0]$11218 + assign $1\cia2__data_o$next[63:0]$11312 $6\cia2__data_o$next[63:0]$11317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11214 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11313 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11313 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11215 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11314 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11215 $2\cia2__data_o$next[63:0]$11214 + assign $3\cia2__data_o$next[63:0]$11314 $2\cia2__data_o$next[63:0]$11313 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11216 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11315 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11216 $3\cia2__data_o$next[63:0]$11215 + assign $4\cia2__data_o$next[63:0]$11315 $3\cia2__data_o$next[63:0]$11314 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11217 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11316 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11217 $4\cia2__data_o$next[63:0]$11216 + assign $5\cia2__data_o$next[63:0]$11316 $4\cia2__data_o$next[63:0]$11315 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11218 \reg + assign $6\cia2__data_o$next[63:0]$11317 \reg case - assign $6\cia2__data_o$next[63:0]$11218 $5\cia2__data_o$next[63:0]$11217 + assign $6\cia2__data_o$next[63:0]$11317 $5\cia2__data_o$next[63:0]$11316 end case - assign $1\cia2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11219 $1\cia2__data_o$next[63:0]$11213 + assign $7\cia2__data_o$next[63:0]$11318 $1\cia2__data_o$next[63:0]$11312 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11212 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 end - attribute \src "libresoc.v:178742.3-178777.6" - process $proc$libresoc.v:178742$11220 + attribute \src "libresoc.v:180626.3-180661.6" + process $proc$libresoc.v:180626$11319 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178743.5-178743.29" + attribute \src "libresoc.v:180627.5-180627.29" switch \initial - attribute \src "libresoc.v:178743.9-178743.17" + attribute \src "libresoc.v:180627.9-180627.17" case 1'1 case end @@ -368454,15 +371518,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178778.3-178823.6" - process $proc$libresoc.v:178778$11221 + attribute \src "libresoc.v:180662.3-180707.6" + process $proc$libresoc.v:180662$11320 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11222 $7\msr2__data_o$next[63:0]$11229 - attribute \src "libresoc.v:178779.5-178779.29" + assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:180663.5-180663.29" switch \initial - attribute \src "libresoc.v:178779.9-178779.17" + attribute \src "libresoc.v:180663.9-180663.17" case 1'1 case end @@ -368475,75 +371539,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11223 $6\msr2__data_o$next[63:0]$11228 + assign $1\msr2__data_o$next[63:0]$11322 $6\msr2__data_o$next[63:0]$11327 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11224 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11323 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11224 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11225 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11324 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11225 $2\msr2__data_o$next[63:0]$11224 + assign $3\msr2__data_o$next[63:0]$11324 $2\msr2__data_o$next[63:0]$11323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11226 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11325 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11226 $3\msr2__data_o$next[63:0]$11225 + assign $4\msr2__data_o$next[63:0]$11325 $3\msr2__data_o$next[63:0]$11324 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11227 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11326 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11227 $4\msr2__data_o$next[63:0]$11226 + assign $5\msr2__data_o$next[63:0]$11326 $4\msr2__data_o$next[63:0]$11325 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11228 \reg + assign $6\msr2__data_o$next[63:0]$11327 \reg case - assign $6\msr2__data_o$next[63:0]$11228 $5\msr2__data_o$next[63:0]$11227 + assign $6\msr2__data_o$next[63:0]$11327 $5\msr2__data_o$next[63:0]$11326 end case - assign $1\msr2__data_o$next[63:0]$11223 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11229 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11229 $1\msr2__data_o$next[63:0]$11223 + assign $7\msr2__data_o$next[63:0]$11328 $1\msr2__data_o$next[63:0]$11322 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11222 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 end - attribute \src "libresoc.v:178824.3-178859.6" - process $proc$libresoc.v:178824$11230 + attribute \src "libresoc.v:180708.3-180743.6" + process $proc$libresoc.v:180708$11329 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:178825.5-178825.29" + assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 + attribute \src "libresoc.v:180709.5-180709.29" switch \initial - attribute \src "libresoc.v:178825.9-178825.17" + attribute \src "libresoc.v:180709.9-180709.17" case 1'1 case end @@ -368556,58 +371620,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11232 $5\wr_detect$4[0:0]$11236 + assign $1\wr_detect$4[0:0]$11331 $5\wr_detect$4[0:0]$11335 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11233 1'1 + assign $2\wr_detect$4[0:0]$11332 1'1 case - assign $2\wr_detect$4[0:0]$11233 1'0 + assign $2\wr_detect$4[0:0]$11332 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11234 1'1 + assign $3\wr_detect$4[0:0]$11333 1'1 case - assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 + assign $3\wr_detect$4[0:0]$11333 $2\wr_detect$4[0:0]$11332 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11235 1'1 + assign $4\wr_detect$4[0:0]$11334 1'1 case - assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 + assign $4\wr_detect$4[0:0]$11334 $3\wr_detect$4[0:0]$11333 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11236 1'1 + assign $5\wr_detect$4[0:0]$11335 1'1 case - assign $5\wr_detect$4[0:0]$11236 $4\wr_detect$4[0:0]$11235 + assign $5\wr_detect$4[0:0]$11335 $4\wr_detect$4[0:0]$11334 end case - assign $1\wr_detect$4[0:0]$11232 1'0 + assign $1\wr_detect$4[0:0]$11331 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11231 + update \wr_detect$4 $0\wr_detect$4[0:0]$11330 end - attribute \src "libresoc.v:178860.3-178905.6" - process $proc$libresoc.v:178860$11237 + attribute \src "libresoc.v:180744.3-180789.6" + process $proc$libresoc.v:180744$11336 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11238 $7\sv2__data_o$next[63:0]$11245 - attribute \src "libresoc.v:178861.5-178861.29" + assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 + attribute \src "libresoc.v:180745.5-180745.29" switch \initial - attribute \src "libresoc.v:178861.9-178861.17" + attribute \src "libresoc.v:180745.9-180745.17" case 1'1 case end @@ -368620,75 +371684,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11239 $6\sv2__data_o$next[63:0]$11244 + assign $1\sv2__data_o$next[63:0]$11338 $6\sv2__data_o$next[63:0]$11343 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11240 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11339 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11240 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11339 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11241 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11340 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11241 $2\sv2__data_o$next[63:0]$11240 + assign $3\sv2__data_o$next[63:0]$11340 $2\sv2__data_o$next[63:0]$11339 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11242 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11341 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11242 $3\sv2__data_o$next[63:0]$11241 + assign $4\sv2__data_o$next[63:0]$11341 $3\sv2__data_o$next[63:0]$11340 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11243 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11342 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11243 $4\sv2__data_o$next[63:0]$11242 + assign $5\sv2__data_o$next[63:0]$11342 $4\sv2__data_o$next[63:0]$11341 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11244 \reg + assign $6\sv2__data_o$next[63:0]$11343 \reg case - assign $6\sv2__data_o$next[63:0]$11244 $5\sv2__data_o$next[63:0]$11243 + assign $6\sv2__data_o$next[63:0]$11343 $5\sv2__data_o$next[63:0]$11342 end case - assign $1\sv2__data_o$next[63:0]$11239 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11338 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11245 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11344 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11245 $1\sv2__data_o$next[63:0]$11239 + assign $7\sv2__data_o$next[63:0]$11344 $1\sv2__data_o$next[63:0]$11338 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11238 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 end - attribute \src "libresoc.v:178906.3-178941.6" - process $proc$libresoc.v:178906$11246 + attribute \src "libresoc.v:180790.3-180825.6" + process $proc$libresoc.v:180790$11345 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11247 $1\wr_detect$7[0:0]$11248 - attribute \src "libresoc.v:178907.5-178907.29" + assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 + attribute \src "libresoc.v:180791.5-180791.29" switch \initial - attribute \src "libresoc.v:178907.9-178907.17" + attribute \src "libresoc.v:180791.9-180791.17" case 1'1 case end @@ -368701,61 +371765,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11248 $5\wr_detect$7[0:0]$11252 + assign $1\wr_detect$7[0:0]$11347 $5\wr_detect$7[0:0]$11351 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11249 1'1 + assign $2\wr_detect$7[0:0]$11348 1'1 case - assign $2\wr_detect$7[0:0]$11249 1'0 + assign $2\wr_detect$7[0:0]$11348 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11250 1'1 + assign $3\wr_detect$7[0:0]$11349 1'1 case - assign $3\wr_detect$7[0:0]$11250 $2\wr_detect$7[0:0]$11249 + assign $3\wr_detect$7[0:0]$11349 $2\wr_detect$7[0:0]$11348 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11251 1'1 + assign $4\wr_detect$7[0:0]$11350 1'1 case - assign $4\wr_detect$7[0:0]$11251 $3\wr_detect$7[0:0]$11250 + assign $4\wr_detect$7[0:0]$11350 $3\wr_detect$7[0:0]$11349 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11252 1'1 + assign $5\wr_detect$7[0:0]$11351 1'1 case - assign $5\wr_detect$7[0:0]$11252 $4\wr_detect$7[0:0]$11251 + assign $5\wr_detect$7[0:0]$11351 $4\wr_detect$7[0:0]$11350 end case - assign $1\wr_detect$7[0:0]$11248 1'0 + assign $1\wr_detect$7[0:0]$11347 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11247 + update \wr_detect$7 $0\wr_detect$7[0:0]$11346 end - attribute \src "libresoc.v:178942.3-178974.6" - process $proc$libresoc.v:178942$11253 + attribute \src "libresoc.v:180826.3-180858.6" + process $proc$libresoc.v:180826$11352 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11254 $5\reg$next[63:0]$11259 - attribute \src "libresoc.v:178943.5-178943.29" + assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 + attribute \src "libresoc.v:180827.5-180827.29" switch \initial - attribute \src "libresoc.v:178943.9-178943.17" + attribute \src "libresoc.v:180827.9-180827.17" case 1'1 case end @@ -368764,286 +371828,324 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11255 \nia2__data_i + assign $1\reg$next[63:0]$11354 \nia2__data_i case - assign $1\reg$next[63:0]$11255 \reg + assign $1\reg$next[63:0]$11354 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11256 \msr2__data_i + assign $2\reg$next[63:0]$11355 \msr2__data_i case - assign $2\reg$next[63:0]$11256 $1\reg$next[63:0]$11255 + assign $2\reg$next[63:0]$11355 $1\reg$next[63:0]$11354 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11257 \sv2__data_i + assign $3\reg$next[63:0]$11356 \sv2__data_i case - assign $3\reg$next[63:0]$11257 $2\reg$next[63:0]$11256 + assign $3\reg$next[63:0]$11356 $2\reg$next[63:0]$11355 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11258 \d_wr12__data_i + assign $4\reg$next[63:0]$11357 \d_wr12__data_i case - assign $4\reg$next[63:0]$11258 $3\reg$next[63:0]$11257 + assign $4\reg$next[63:0]$11357 $3\reg$next[63:0]$11356 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11259 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11358 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11259 $4\reg$next[63:0]$11258 + assign $5\reg$next[63:0]$11358 $4\reg$next[63:0]$11357 end sync always - update \reg$next $0\reg$next[63:0]$11254 + update \reg$next $0\reg$next[63:0]$11353 end - connect \$1 $not$libresoc.v:178685$11204_Y - connect \$3 $not$libresoc.v:178686$11205_Y - connect \$6 $not$libresoc.v:178687$11206_Y + connect \$1 $not$libresoc.v:180569$11303_Y + connect \$3 $not$libresoc.v:180570$11304_Y + connect \$6 $not$libresoc.v:180571$11305_Y end -attribute \src "libresoc.v:178979.1-179450.10" +attribute \src "libresoc.v:180863.1-181418.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:178980.7-178980.20" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 + attribute \src "libresoc.v:180969.3-180970.49" + wire width 4 $0\cr_pred3__data_o[3:0] + attribute \src "libresoc.v:180864.7-180864.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $0\r23__data_o$next[3:0]$11334 - attribute \src "libresoc.v:179063.3-179064.39" + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $0\r23__data_o$next[3:0]$11387 + attribute \src "libresoc.v:180959.3-180960.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $0\r3__data_o$next[3:0]$11320 - attribute \src "libresoc.v:179065.3-179066.37" + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $0\r3__data_o$next[3:0]$11449 + attribute \src "libresoc.v:180961.3-180962.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $0\reg$next[3:0]$11286 - attribute \src "libresoc.v:179061.3-179062.25" + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $0\reg$next[3:0]$11401 + attribute \src "libresoc.v:180957.3-180958.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $0\src13__data_o$next[3:0]$11277 - attribute \src "libresoc.v:179071.3-179072.43" + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $0\src13__data_o$next[3:0]$11407 + attribute \src "libresoc.v:180967.3-180968.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $0\src23__data_o$next[3:0]$11292 - attribute \src "libresoc.v:179069.3-179070.43" + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $0\src23__data_o$next[3:0]$11421 + attribute \src "libresoc.v:180965.3-180966.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $0\src33__data_o$next[3:0]$11306 - attribute \src "libresoc.v:179067.3-179068.43" + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $0\src33__data_o$next[3:0]$11435 + attribute \src "libresoc.v:180963.3-180964.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:179350.3-179379.6" - wire $0\wr_detect$10[0:0]$11328 - attribute \src "libresoc.v:179420.3-179449.6" - wire $0\wr_detect$13[0:0]$11342 - attribute \src "libresoc.v:179210.3-179239.6" - wire $0\wr_detect$4[0:0]$11300 - attribute \src "libresoc.v:179280.3-179309.6" - wire $0\wr_detect$7[0:0]$11314 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:181318.3-181347.6" + wire $0\wr_detect$10[0:0]$11443 + attribute \src "libresoc.v:181388.3-181417.6" + wire $0\wr_detect$13[0:0]$11457 + attribute \src "libresoc.v:181081.3-181110.6" + wire $0\wr_detect$16[0:0]$11395 + attribute \src "libresoc.v:181178.3-181207.6" + wire $0\wr_detect$4[0:0]$11415 + attribute \src "libresoc.v:181248.3-181277.6" + wire $0\wr_detect$7[0:0]$11429 + attribute \src "libresoc.v:181011.3-181040.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $1\r23__data_o$next[3:0]$11335 - attribute \src "libresoc.v:179005.13-179005.31" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $1\cr_pred3__data_o$next[3:0]$11379 + attribute \src "libresoc.v:180883.13-180883.36" + wire width 4 $1\cr_pred3__data_o[3:0] + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $1\r23__data_o$next[3:0]$11388 + attribute \src "libresoc.v:180898.13-180898.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $1\r3__data_o$next[3:0]$11321 - attribute \src "libresoc.v:179012.13-179012.30" + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $1\r3__data_o$next[3:0]$11450 + attribute \src "libresoc.v:180905.13-180905.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $1\reg$next[3:0]$11287 - attribute \src "libresoc.v:179018.13-179018.25" + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $1\reg$next[3:0]$11402 + attribute \src "libresoc.v:180911.13-180911.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $1\src13__data_o$next[3:0]$11278 - attribute \src "libresoc.v:179023.13-179023.33" + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $1\src13__data_o$next[3:0]$11408 + attribute \src "libresoc.v:180916.13-180916.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $1\src23__data_o$next[3:0]$11293 - attribute \src "libresoc.v:179030.13-179030.33" + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $1\src23__data_o$next[3:0]$11422 + attribute \src "libresoc.v:180923.13-180923.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $1\src33__data_o$next[3:0]$11307 - attribute \src "libresoc.v:179037.13-179037.33" + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $1\src33__data_o$next[3:0]$11436 + attribute \src "libresoc.v:180930.13-180930.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:179350.3-179379.6" - wire $1\wr_detect$10[0:0]$11329 - attribute \src "libresoc.v:179420.3-179449.6" - wire $1\wr_detect$13[0:0]$11343 - attribute \src "libresoc.v:179210.3-179239.6" - wire $1\wr_detect$4[0:0]$11301 - attribute \src "libresoc.v:179280.3-179309.6" - wire $1\wr_detect$7[0:0]$11315 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:181318.3-181347.6" + wire $1\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:181388.3-181417.6" + wire $1\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:181081.3-181110.6" + wire $1\wr_detect$16[0:0]$11396 + attribute \src "libresoc.v:181178.3-181207.6" + wire $1\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:181248.3-181277.6" + wire $1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181011.3-181040.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $2\r23__data_o$next[3:0]$11336 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $2\r3__data_o$next[3:0]$11322 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $2\reg$next[3:0]$11288 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $2\src13__data_o$next[3:0]$11279 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $2\src23__data_o$next[3:0]$11294 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $2\src33__data_o$next[3:0]$11308 - attribute \src "libresoc.v:179350.3-179379.6" - wire $2\wr_detect$10[0:0]$11330 - attribute \src "libresoc.v:179420.3-179449.6" - wire $2\wr_detect$13[0:0]$11344 - attribute \src "libresoc.v:179210.3-179239.6" - wire $2\wr_detect$4[0:0]$11302 - attribute \src "libresoc.v:179280.3-179309.6" - wire $2\wr_detect$7[0:0]$11316 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $2\r23__data_o$next[3:0]$11389 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $2\r3__data_o$next[3:0]$11451 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $2\reg$next[3:0]$11403 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $2\src13__data_o$next[3:0]$11409 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $2\src23__data_o$next[3:0]$11423 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $2\src33__data_o$next[3:0]$11437 + attribute \src "libresoc.v:181318.3-181347.6" + wire $2\wr_detect$10[0:0]$11445 + attribute \src "libresoc.v:181388.3-181417.6" + wire $2\wr_detect$13[0:0]$11459 + attribute \src "libresoc.v:181081.3-181110.6" + wire $2\wr_detect$16[0:0]$11397 + attribute \src "libresoc.v:181178.3-181207.6" + wire $2\wr_detect$4[0:0]$11417 + attribute \src "libresoc.v:181248.3-181277.6" + wire $2\wr_detect$7[0:0]$11431 + attribute \src "libresoc.v:181011.3-181040.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $3\r23__data_o$next[3:0]$11337 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $3\r3__data_o$next[3:0]$11323 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $3\reg$next[3:0]$11289 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $3\src13__data_o$next[3:0]$11280 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $3\src23__data_o$next[3:0]$11295 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $3\src33__data_o$next[3:0]$11309 - attribute \src "libresoc.v:179350.3-179379.6" - wire $3\wr_detect$10[0:0]$11331 - attribute \src "libresoc.v:179420.3-179449.6" - wire $3\wr_detect$13[0:0]$11345 - attribute \src "libresoc.v:179210.3-179239.6" - wire $3\wr_detect$4[0:0]$11303 - attribute \src "libresoc.v:179280.3-179309.6" - wire $3\wr_detect$7[0:0]$11317 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $3\r23__data_o$next[3:0]$11390 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $3\r3__data_o$next[3:0]$11452 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $3\reg$next[3:0]$11404 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $3\src13__data_o$next[3:0]$11410 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $3\src23__data_o$next[3:0]$11424 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $3\src33__data_o$next[3:0]$11438 + attribute \src "libresoc.v:181318.3-181347.6" + wire $3\wr_detect$10[0:0]$11446 + attribute \src "libresoc.v:181388.3-181417.6" + wire $3\wr_detect$13[0:0]$11460 + attribute \src "libresoc.v:181081.3-181110.6" + wire $3\wr_detect$16[0:0]$11398 + attribute \src "libresoc.v:181178.3-181207.6" + wire $3\wr_detect$4[0:0]$11418 + attribute \src "libresoc.v:181248.3-181277.6" + wire $3\wr_detect$7[0:0]$11432 + attribute \src "libresoc.v:181011.3-181040.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $4\r23__data_o$next[3:0]$11338 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $4\r3__data_o$next[3:0]$11324 - attribute \src "libresoc.v:179143.3-179169.6" - wire width 4 $4\reg$next[3:0]$11290 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $4\src13__data_o$next[3:0]$11281 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $4\src23__data_o$next[3:0]$11296 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $4\src33__data_o$next[3:0]$11310 - attribute \src "libresoc.v:179350.3-179379.6" - wire $4\wr_detect$10[0:0]$11332 - attribute \src "libresoc.v:179420.3-179449.6" - wire $4\wr_detect$13[0:0]$11346 - attribute \src "libresoc.v:179210.3-179239.6" - wire $4\wr_detect$4[0:0]$11304 - attribute \src "libresoc.v:179280.3-179309.6" - wire $4\wr_detect$7[0:0]$11318 - attribute \src "libresoc.v:179113.3-179142.6" + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $4\r23__data_o$next[3:0]$11391 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $4\r3__data_o$next[3:0]$11453 + attribute \src "libresoc.v:181111.3-181137.6" + wire width 4 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $4\src13__data_o$next[3:0]$11411 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $4\src23__data_o$next[3:0]$11425 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $4\src33__data_o$next[3:0]$11439 + attribute \src "libresoc.v:181318.3-181347.6" + wire $4\wr_detect$10[0:0]$11447 + attribute \src "libresoc.v:181388.3-181417.6" + wire $4\wr_detect$13[0:0]$11461 + attribute \src "libresoc.v:181081.3-181110.6" + wire $4\wr_detect$16[0:0]$11399 + attribute \src "libresoc.v:181178.3-181207.6" + wire $4\wr_detect$4[0:0]$11419 + attribute \src "libresoc.v:181248.3-181277.6" + wire $4\wr_detect$7[0:0]$11433 + attribute \src "libresoc.v:181011.3-181040.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $5\r23__data_o$next[3:0]$11339 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $5\r3__data_o$next[3:0]$11325 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $5\src13__data_o$next[3:0]$11282 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $5\src23__data_o$next[3:0]$11297 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $5\src33__data_o$next[3:0]$11311 - attribute \src "libresoc.v:179380.3-179419.6" - wire width 4 $6\r23__data_o$next[3:0]$11340 - attribute \src "libresoc.v:179310.3-179349.6" - wire width 4 $6\r3__data_o$next[3:0]$11326 - attribute \src "libresoc.v:179073.3-179112.6" - wire width 4 $6\src13__data_o$next[3:0]$11283 - attribute \src "libresoc.v:179170.3-179209.6" - wire width 4 $6\src23__data_o$next[3:0]$11298 - attribute \src "libresoc.v:179240.3-179279.6" - wire width 4 $6\src33__data_o$next[3:0]$11312 - attribute \src "libresoc.v:179056.17-179056.104" - wire $not$libresoc.v:179056$11265_Y - attribute \src "libresoc.v:179057.18-179057.105" - wire $not$libresoc.v:179057$11266_Y - attribute \src "libresoc.v:179058.17-179058.100" - wire $not$libresoc.v:179058$11267_Y - attribute \src "libresoc.v:179059.17-179059.103" - wire $not$libresoc.v:179059$11268_Y - attribute \src "libresoc.v:179060.17-179060.103" - wire $not$libresoc.v:179060$11269_Y + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $5\r23__data_o$next[3:0]$11392 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $5\r3__data_o$next[3:0]$11454 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $5\src13__data_o$next[3:0]$11412 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $5\src23__data_o$next[3:0]$11426 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $5\src33__data_o$next[3:0]$11440 + attribute \src "libresoc.v:180971.3-181010.6" + wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:181041.3-181080.6" + wire width 4 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181348.3-181387.6" + wire width 4 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181138.3-181177.6" + wire width 4 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181208.3-181247.6" + wire width 4 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181278.3-181317.6" + wire width 4 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:180951.17-180951.104" + wire $not$libresoc.v:180951$11364_Y + attribute \src "libresoc.v:180952.18-180952.105" + wire $not$libresoc.v:180952$11365_Y + attribute \src "libresoc.v:180953.18-180953.105" + wire $not$libresoc.v:180953$11366_Y + attribute \src "libresoc.v:180954.17-180954.100" + wire $not$libresoc.v:180954$11367_Y + attribute \src "libresoc.v:180955.17-180955.103" + wire $not$libresoc.v:180955$11368_Y + attribute \src "libresoc.v:180956.17-180956.103" + wire $not$libresoc.v:180956$11369_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest13__data_i + wire width 4 output 3 \cr_pred3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest13__wen + wire width 4 input 11 \dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest23__data_i + wire input 10 \dest13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest23__wen - attribute \src "libresoc.v:178980.7-178980.15" + wire width 4 input 13 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest23__wen + attribute \src "libresoc.v:180864.7-180864.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r23__data_o + wire width 4 output 16 \r23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r23__ren + wire input 17 \r23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r3__data_o + wire width 4 output 14 \r3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r3__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r3__ren + wire input 15 \r3__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src13__data_o + wire width 4 output 5 \src13__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src13__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src13__ren + wire input 4 \src13__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src23__data_o + wire width 4 output 7 \src23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src23__ren + wire input 6 \src23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src33__data_o + wire width 4 output 9 \src33__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src33__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src33__ren + wire input 8 \src33__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w3__data_i + wire width 4 input 18 \w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w3__wen + wire input 19 \w3__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -369051,232 +372153,257 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179056$11265 + cell $not $not$libresoc.v:180951$11364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179056$11265_Y + connect \Y $not$libresoc.v:180951$11364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179057$11266 + cell $not $not$libresoc.v:180952$11365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179057$11266_Y + connect \Y $not$libresoc.v:180952$11365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179058$11267 + cell $not $not$libresoc.v:180953$11366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:180953$11366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:180954$11367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179058$11267_Y + connect \Y $not$libresoc.v:180954$11367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179059$11268 + cell $not $not$libresoc.v:180955$11368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179059$11268_Y + connect \Y $not$libresoc.v:180955$11368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179060$11269 + cell $not $not$libresoc.v:180956$11369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179060$11269_Y + connect \Y $not$libresoc.v:180956$11369_Y end - attribute \src "libresoc.v:178980.7-178980.20" - process $proc$libresoc.v:178980$11347 + attribute \src "libresoc.v:180864.7-180864.20" + process $proc$libresoc.v:180864$11462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179005.13-179005.31" - process $proc$libresoc.v:179005$11348 + attribute \src "libresoc.v:180883.13-180883.36" + process $proc$libresoc.v:180883$11463 + assign { } { } + assign $1\cr_pred3__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180898.13-180898.31" + process $proc$libresoc.v:180898$11464 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:179012.13-179012.30" - process $proc$libresoc.v:179012$11349 + attribute \src "libresoc.v:180905.13-180905.30" + process $proc$libresoc.v:180905$11465 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:179018.13-179018.25" - process $proc$libresoc.v:179018$11350 + attribute \src "libresoc.v:180911.13-180911.25" + process $proc$libresoc.v:180911$11466 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179023.13-179023.33" - process $proc$libresoc.v:179023$11351 + attribute \src "libresoc.v:180916.13-180916.33" + process $proc$libresoc.v:180916$11467 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:179030.13-179030.33" - process $proc$libresoc.v:179030$11352 + attribute \src "libresoc.v:180923.13-180923.33" + process $proc$libresoc.v:180923$11468 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:179037.13-179037.33" - process $proc$libresoc.v:179037$11353 + attribute \src "libresoc.v:180930.13-180930.33" + process $proc$libresoc.v:180930$11469 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:179061.3-179062.25" - process $proc$libresoc.v:179061$11270 + attribute \src "libresoc.v:180957.3-180958.25" + process $proc$libresoc.v:180957$11370 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179063.3-179064.39" - process $proc$libresoc.v:179063$11271 + attribute \src "libresoc.v:180959.3-180960.39" + process $proc$libresoc.v:180959$11371 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:179065.3-179066.37" - process $proc$libresoc.v:179065$11272 + attribute \src "libresoc.v:180961.3-180962.37" + process $proc$libresoc.v:180961$11372 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:179067.3-179068.43" - process $proc$libresoc.v:179067$11273 + attribute \src "libresoc.v:180963.3-180964.43" + process $proc$libresoc.v:180963$11373 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:179069.3-179070.43" - process $proc$libresoc.v:179069$11274 + attribute \src "libresoc.v:180965.3-180966.43" + process $proc$libresoc.v:180965$11374 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:179071.3-179072.43" - process $proc$libresoc.v:179071$11275 + attribute \src "libresoc.v:180967.3-180968.43" + process $proc$libresoc.v:180967$11375 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:179073.3-179112.6" - process $proc$libresoc.v:179073$11276 + attribute \src "libresoc.v:180969.3-180970.49" + process $proc$libresoc.v:180969$11376 + assign { } { } + assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next + sync posedge \coresync_clk + update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] + end + attribute \src "libresoc.v:180971.3-181010.6" + process $proc$libresoc.v:180971$11377 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11277 $6\src13__data_o$next[3:0]$11283 - attribute \src "libresoc.v:179074.5-179074.29" + assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 + attribute \src "libresoc.v:180972.5-180972.29" switch \initial - attribute \src "libresoc.v:179074.9-179074.17" + attribute \src "libresoc.v:180972.9-180972.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \cr_pred3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11278 $5\src13__data_o$next[3:0]$11282 + assign $1\cr_pred3__data_o$next[3:0]$11379 $5\cr_pred3__data_o$next[3:0]$11383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11279 \dest13__data_i + assign $2\cr_pred3__data_o$next[3:0]$11380 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11279 4'0000 + assign $2\cr_pred3__data_o$next[3:0]$11380 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11280 \dest23__data_i + assign $3\cr_pred3__data_o$next[3:0]$11381 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11280 $2\src13__data_o$next[3:0]$11279 + assign $3\cr_pred3__data_o$next[3:0]$11381 $2\cr_pred3__data_o$next[3:0]$11380 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11281 \w3__data_i + assign $4\cr_pred3__data_o$next[3:0]$11382 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11281 $3\src13__data_o$next[3:0]$11280 + assign $4\cr_pred3__data_o$next[3:0]$11382 $3\cr_pred3__data_o$next[3:0]$11381 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11282 \reg + assign $5\cr_pred3__data_o$next[3:0]$11383 \reg case - assign $5\src13__data_o$next[3:0]$11282 $4\src13__data_o$next[3:0]$11281 + assign $5\cr_pred3__data_o$next[3:0]$11383 $4\cr_pred3__data_o$next[3:0]$11382 end case - assign $1\src13__data_o$next[3:0]$11278 4'0000 + assign $1\cr_pred3__data_o$next[3:0]$11379 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11283 4'0000 + assign $6\cr_pred3__data_o$next[3:0]$11384 4'0000 case - assign $6\src13__data_o$next[3:0]$11283 $1\src13__data_o$next[3:0]$11278 + assign $6\cr_pred3__data_o$next[3:0]$11384 $1\cr_pred3__data_o$next[3:0]$11379 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11277 + update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 end - attribute \src "libresoc.v:179113.3-179142.6" - process $proc$libresoc.v:179113$11284 + attribute \src "libresoc.v:181011.3-181040.6" + process $proc$libresoc.v:181011$11385 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179114.5-179114.29" + attribute \src "libresoc.v:181012.5-181012.29" switch \initial - attribute \src "libresoc.v:179114.9-179114.17" + attribute \src "libresoc.v:181012.9-181012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + switch \cr_pred3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -369317,17 +372444,142 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179143.3-179169.6" - process $proc$libresoc.v:179143$11285 + attribute \src "libresoc.v:181041.3-181080.6" + process $proc$libresoc.v:181041$11386 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 + attribute \src "libresoc.v:181042.5-181042.29" + switch \initial + attribute \src "libresoc.v:181042.9-181042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$11388 $5\r23__data_o$next[3:0]$11392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$11389 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$11389 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$11390 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$11390 $2\r23__data_o$next[3:0]$11389 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$11391 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$11391 $3\r23__data_o$next[3:0]$11390 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$11392 \reg + case + assign $5\r23__data_o$next[3:0]$11392 $4\r23__data_o$next[3:0]$11391 + end + case + assign $1\r23__data_o$next[3:0]$11388 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$11393 4'0000 + case + assign $6\r23__data_o$next[3:0]$11393 $1\r23__data_o$next[3:0]$11388 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 + end + attribute \src "libresoc.v:181081.3-181110.6" + process $proc$libresoc.v:181081$11394 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 + attribute \src "libresoc.v:181082.5-181082.29" + switch \initial + attribute \src "libresoc.v:181082.9-181082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11396 $4\wr_detect$16[0:0]$11399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11397 1'1 + case + assign $2\wr_detect$16[0:0]$11397 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11398 1'1 + case + assign $3\wr_detect$16[0:0]$11398 $2\wr_detect$16[0:0]$11397 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11399 1'1 + case + assign $4\wr_detect$16[0:0]$11399 $3\wr_detect$16[0:0]$11398 + end + case + assign $1\wr_detect$16[0:0]$11396 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11395 + end + attribute \src "libresoc.v:181111.3-181137.6" + process $proc$libresoc.v:181111$11400 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11286 $4\reg$next[3:0]$11290 - attribute \src "libresoc.v:179144.5-179144.29" + assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 + attribute \src "libresoc.v:181112.5-181112.29" switch \initial - attribute \src "libresoc.v:179144.9-179144.17" + attribute \src "libresoc.v:181112.9-181112.17" case 1'1 case end @@ -369336,779 +372588,818 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11287 \dest13__data_i + assign $1\reg$next[3:0]$11402 \dest13__data_i case - assign $1\reg$next[3:0]$11287 \reg + assign $1\reg$next[3:0]$11402 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11288 \dest23__data_i + assign $2\reg$next[3:0]$11403 \dest23__data_i case - assign $2\reg$next[3:0]$11288 $1\reg$next[3:0]$11287 + assign $2\reg$next[3:0]$11403 $1\reg$next[3:0]$11402 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11289 \w3__data_i + assign $3\reg$next[3:0]$11404 \w3__data_i case - assign $3\reg$next[3:0]$11289 $2\reg$next[3:0]$11288 + assign $3\reg$next[3:0]$11404 $2\reg$next[3:0]$11403 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11290 4'0000 + assign $4\reg$next[3:0]$11405 4'0000 case - assign $4\reg$next[3:0]$11290 $3\reg$next[3:0]$11289 + assign $4\reg$next[3:0]$11405 $3\reg$next[3:0]$11404 end sync always - update \reg$next $0\reg$next[3:0]$11286 + update \reg$next $0\reg$next[3:0]$11401 end - attribute \src "libresoc.v:179170.3-179209.6" - process $proc$libresoc.v:179170$11291 + attribute \src "libresoc.v:181138.3-181177.6" + process $proc$libresoc.v:181138$11406 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11292 $6\src23__data_o$next[3:0]$11298 - attribute \src "libresoc.v:179171.5-179171.29" + assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 + attribute \src "libresoc.v:181139.5-181139.29" switch \initial - attribute \src "libresoc.v:179171.9-179171.17" + attribute \src "libresoc.v:181139.9-181139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11293 $5\src23__data_o$next[3:0]$11297 + assign $1\src13__data_o$next[3:0]$11408 $5\src13__data_o$next[3:0]$11412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11294 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11409 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11294 4'0000 + assign $2\src13__data_o$next[3:0]$11409 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11295 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11410 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11295 $2\src23__data_o$next[3:0]$11294 + assign $3\src13__data_o$next[3:0]$11410 $2\src13__data_o$next[3:0]$11409 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11296 \w3__data_i + assign $4\src13__data_o$next[3:0]$11411 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11296 $3\src23__data_o$next[3:0]$11295 + assign $4\src13__data_o$next[3:0]$11411 $3\src13__data_o$next[3:0]$11410 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11297 \reg + assign $5\src13__data_o$next[3:0]$11412 \reg case - assign $5\src23__data_o$next[3:0]$11297 $4\src23__data_o$next[3:0]$11296 + assign $5\src13__data_o$next[3:0]$11412 $4\src13__data_o$next[3:0]$11411 end case - assign $1\src23__data_o$next[3:0]$11293 4'0000 + assign $1\src13__data_o$next[3:0]$11408 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11298 4'0000 + assign $6\src13__data_o$next[3:0]$11413 4'0000 case - assign $6\src23__data_o$next[3:0]$11298 $1\src23__data_o$next[3:0]$11293 + assign $6\src13__data_o$next[3:0]$11413 $1\src13__data_o$next[3:0]$11408 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11292 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 end - attribute \src "libresoc.v:179210.3-179239.6" - process $proc$libresoc.v:179210$11299 + attribute \src "libresoc.v:181178.3-181207.6" + process $proc$libresoc.v:181178$11414 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11300 $1\wr_detect$4[0:0]$11301 - attribute \src "libresoc.v:179211.5-179211.29" + assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 + attribute \src "libresoc.v:181179.5-181179.29" switch \initial - attribute \src "libresoc.v:179211.9-179211.17" + attribute \src "libresoc.v:181179.9-181179.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11301 $4\wr_detect$4[0:0]$11304 + assign $1\wr_detect$4[0:0]$11416 $4\wr_detect$4[0:0]$11419 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11302 1'1 + assign $2\wr_detect$4[0:0]$11417 1'1 case - assign $2\wr_detect$4[0:0]$11302 1'0 + assign $2\wr_detect$4[0:0]$11417 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11303 1'1 + assign $3\wr_detect$4[0:0]$11418 1'1 case - assign $3\wr_detect$4[0:0]$11303 $2\wr_detect$4[0:0]$11302 + assign $3\wr_detect$4[0:0]$11418 $2\wr_detect$4[0:0]$11417 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11304 1'1 + assign $4\wr_detect$4[0:0]$11419 1'1 case - assign $4\wr_detect$4[0:0]$11304 $3\wr_detect$4[0:0]$11303 + assign $4\wr_detect$4[0:0]$11419 $3\wr_detect$4[0:0]$11418 end case - assign $1\wr_detect$4[0:0]$11301 1'0 + assign $1\wr_detect$4[0:0]$11416 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11300 + update \wr_detect$4 $0\wr_detect$4[0:0]$11415 end - attribute \src "libresoc.v:179240.3-179279.6" - process $proc$libresoc.v:179240$11305 + attribute \src "libresoc.v:181208.3-181247.6" + process $proc$libresoc.v:181208$11420 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11306 $6\src33__data_o$next[3:0]$11312 - attribute \src "libresoc.v:179241.5-179241.29" + assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 + attribute \src "libresoc.v:181209.5-181209.29" switch \initial - attribute \src "libresoc.v:179241.9-179241.17" + attribute \src "libresoc.v:181209.9-181209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11307 $5\src33__data_o$next[3:0]$11311 + assign $1\src23__data_o$next[3:0]$11422 $5\src23__data_o$next[3:0]$11426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11308 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11423 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11308 4'0000 + assign $2\src23__data_o$next[3:0]$11423 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11309 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11424 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11309 $2\src33__data_o$next[3:0]$11308 + assign $3\src23__data_o$next[3:0]$11424 $2\src23__data_o$next[3:0]$11423 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11310 \w3__data_i + assign $4\src23__data_o$next[3:0]$11425 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11310 $3\src33__data_o$next[3:0]$11309 + assign $4\src23__data_o$next[3:0]$11425 $3\src23__data_o$next[3:0]$11424 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11311 \reg + assign $5\src23__data_o$next[3:0]$11426 \reg case - assign $5\src33__data_o$next[3:0]$11311 $4\src33__data_o$next[3:0]$11310 + assign $5\src23__data_o$next[3:0]$11426 $4\src23__data_o$next[3:0]$11425 end case - assign $1\src33__data_o$next[3:0]$11307 4'0000 + assign $1\src23__data_o$next[3:0]$11422 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11312 4'0000 + assign $6\src23__data_o$next[3:0]$11427 4'0000 case - assign $6\src33__data_o$next[3:0]$11312 $1\src33__data_o$next[3:0]$11307 + assign $6\src23__data_o$next[3:0]$11427 $1\src23__data_o$next[3:0]$11422 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11306 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 end - attribute \src "libresoc.v:179280.3-179309.6" - process $proc$libresoc.v:179280$11313 + attribute \src "libresoc.v:181248.3-181277.6" + process $proc$libresoc.v:181248$11428 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11314 $1\wr_detect$7[0:0]$11315 - attribute \src "libresoc.v:179281.5-179281.29" + assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 + attribute \src "libresoc.v:181249.5-181249.29" switch \initial - attribute \src "libresoc.v:179281.9-179281.17" + attribute \src "libresoc.v:181249.9-181249.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11315 $4\wr_detect$7[0:0]$11318 + assign $1\wr_detect$7[0:0]$11430 $4\wr_detect$7[0:0]$11433 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11316 1'1 + assign $2\wr_detect$7[0:0]$11431 1'1 case - assign $2\wr_detect$7[0:0]$11316 1'0 + assign $2\wr_detect$7[0:0]$11431 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11317 1'1 + assign $3\wr_detect$7[0:0]$11432 1'1 case - assign $3\wr_detect$7[0:0]$11317 $2\wr_detect$7[0:0]$11316 + assign $3\wr_detect$7[0:0]$11432 $2\wr_detect$7[0:0]$11431 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11318 1'1 + assign $4\wr_detect$7[0:0]$11433 1'1 case - assign $4\wr_detect$7[0:0]$11318 $3\wr_detect$7[0:0]$11317 + assign $4\wr_detect$7[0:0]$11433 $3\wr_detect$7[0:0]$11432 end case - assign $1\wr_detect$7[0:0]$11315 1'0 + assign $1\wr_detect$7[0:0]$11430 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11314 + update \wr_detect$7 $0\wr_detect$7[0:0]$11429 end - attribute \src "libresoc.v:179310.3-179349.6" - process $proc$libresoc.v:179310$11319 + attribute \src "libresoc.v:181278.3-181317.6" + process $proc$libresoc.v:181278$11434 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11320 $6\r3__data_o$next[3:0]$11326 - attribute \src "libresoc.v:179311.5-179311.29" + assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 + attribute \src "libresoc.v:181279.5-181279.29" switch \initial - attribute \src "libresoc.v:179311.9-179311.17" + attribute \src "libresoc.v:181279.9-181279.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11321 $5\r3__data_o$next[3:0]$11325 + assign $1\src33__data_o$next[3:0]$11436 $5\src33__data_o$next[3:0]$11440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11322 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11437 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11322 4'0000 + assign $2\src33__data_o$next[3:0]$11437 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11323 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11438 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11323 $2\r3__data_o$next[3:0]$11322 + assign $3\src33__data_o$next[3:0]$11438 $2\src33__data_o$next[3:0]$11437 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11324 \w3__data_i + assign $4\src33__data_o$next[3:0]$11439 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11324 $3\r3__data_o$next[3:0]$11323 + assign $4\src33__data_o$next[3:0]$11439 $3\src33__data_o$next[3:0]$11438 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11325 \reg + assign $5\src33__data_o$next[3:0]$11440 \reg case - assign $5\r3__data_o$next[3:0]$11325 $4\r3__data_o$next[3:0]$11324 + assign $5\src33__data_o$next[3:0]$11440 $4\src33__data_o$next[3:0]$11439 end case - assign $1\r3__data_o$next[3:0]$11321 4'0000 + assign $1\src33__data_o$next[3:0]$11436 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11326 4'0000 + assign $6\src33__data_o$next[3:0]$11441 4'0000 case - assign $6\r3__data_o$next[3:0]$11326 $1\r3__data_o$next[3:0]$11321 + assign $6\src33__data_o$next[3:0]$11441 $1\src33__data_o$next[3:0]$11436 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11320 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 end - attribute \src "libresoc.v:179350.3-179379.6" - process $proc$libresoc.v:179350$11327 + attribute \src "libresoc.v:181318.3-181347.6" + process $proc$libresoc.v:181318$11442 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11328 $1\wr_detect$10[0:0]$11329 - attribute \src "libresoc.v:179351.5-179351.29" + assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 + attribute \src "libresoc.v:181319.5-181319.29" switch \initial - attribute \src "libresoc.v:179351.9-179351.17" + attribute \src "libresoc.v:181319.9-181319.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11329 $4\wr_detect$10[0:0]$11332 + assign $1\wr_detect$10[0:0]$11444 $4\wr_detect$10[0:0]$11447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11330 1'1 + assign $2\wr_detect$10[0:0]$11445 1'1 case - assign $2\wr_detect$10[0:0]$11330 1'0 + assign $2\wr_detect$10[0:0]$11445 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11331 1'1 + assign $3\wr_detect$10[0:0]$11446 1'1 case - assign $3\wr_detect$10[0:0]$11331 $2\wr_detect$10[0:0]$11330 + assign $3\wr_detect$10[0:0]$11446 $2\wr_detect$10[0:0]$11445 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11332 1'1 + assign $4\wr_detect$10[0:0]$11447 1'1 case - assign $4\wr_detect$10[0:0]$11332 $3\wr_detect$10[0:0]$11331 + assign $4\wr_detect$10[0:0]$11447 $3\wr_detect$10[0:0]$11446 end case - assign $1\wr_detect$10[0:0]$11329 1'0 + assign $1\wr_detect$10[0:0]$11444 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11328 + update \wr_detect$10 $0\wr_detect$10[0:0]$11443 end - attribute \src "libresoc.v:179380.3-179419.6" - process $proc$libresoc.v:179380$11333 + attribute \src "libresoc.v:181348.3-181387.6" + process $proc$libresoc.v:181348$11448 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11334 $6\r23__data_o$next[3:0]$11340 - attribute \src "libresoc.v:179381.5-179381.29" + assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 + attribute \src "libresoc.v:181349.5-181349.29" switch \initial - attribute \src "libresoc.v:179381.9-179381.17" + attribute \src "libresoc.v:181349.9-181349.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11335 $5\r23__data_o$next[3:0]$11339 + assign $1\r3__data_o$next[3:0]$11450 $5\r3__data_o$next[3:0]$11454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11336 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11451 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11336 4'0000 + assign $2\r3__data_o$next[3:0]$11451 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11337 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11452 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11337 $2\r23__data_o$next[3:0]$11336 + assign $3\r3__data_o$next[3:0]$11452 $2\r3__data_o$next[3:0]$11451 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11338 \w3__data_i + assign $4\r3__data_o$next[3:0]$11453 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11338 $3\r23__data_o$next[3:0]$11337 + assign $4\r3__data_o$next[3:0]$11453 $3\r3__data_o$next[3:0]$11452 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11339 \reg + assign $5\r3__data_o$next[3:0]$11454 \reg case - assign $5\r23__data_o$next[3:0]$11339 $4\r23__data_o$next[3:0]$11338 + assign $5\r3__data_o$next[3:0]$11454 $4\r3__data_o$next[3:0]$11453 end case - assign $1\r23__data_o$next[3:0]$11335 4'0000 + assign $1\r3__data_o$next[3:0]$11450 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11340 4'0000 + assign $6\r3__data_o$next[3:0]$11455 4'0000 case - assign $6\r23__data_o$next[3:0]$11340 $1\r23__data_o$next[3:0]$11335 + assign $6\r3__data_o$next[3:0]$11455 $1\r3__data_o$next[3:0]$11450 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11334 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 end - attribute \src "libresoc.v:179420.3-179449.6" - process $proc$libresoc.v:179420$11341 + attribute \src "libresoc.v:181388.3-181417.6" + process $proc$libresoc.v:181388$11456 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11342 $1\wr_detect$13[0:0]$11343 - attribute \src "libresoc.v:179421.5-179421.29" + assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 + attribute \src "libresoc.v:181389.5-181389.29" switch \initial - attribute \src "libresoc.v:179421.9-179421.17" + attribute \src "libresoc.v:181389.9-181389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11343 $4\wr_detect$13[0:0]$11346 + assign $1\wr_detect$13[0:0]$11458 $4\wr_detect$13[0:0]$11461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11344 1'1 + assign $2\wr_detect$13[0:0]$11459 1'1 case - assign $2\wr_detect$13[0:0]$11344 1'0 + assign $2\wr_detect$13[0:0]$11459 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11345 1'1 + assign $3\wr_detect$13[0:0]$11460 1'1 case - assign $3\wr_detect$13[0:0]$11345 $2\wr_detect$13[0:0]$11344 + assign $3\wr_detect$13[0:0]$11460 $2\wr_detect$13[0:0]$11459 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11346 1'1 + assign $4\wr_detect$13[0:0]$11461 1'1 case - assign $4\wr_detect$13[0:0]$11346 $3\wr_detect$13[0:0]$11345 + assign $4\wr_detect$13[0:0]$11461 $3\wr_detect$13[0:0]$11460 end case - assign $1\wr_detect$13[0:0]$11343 1'0 + assign $1\wr_detect$13[0:0]$11458 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11342 + update \wr_detect$13 $0\wr_detect$13[0:0]$11457 end - connect \$9 $not$libresoc.v:179056$11265_Y - connect \$12 $not$libresoc.v:179057$11266_Y - connect \$1 $not$libresoc.v:179058$11267_Y - connect \$3 $not$libresoc.v:179059$11268_Y - connect \$6 $not$libresoc.v:179060$11269_Y + connect \$9 $not$libresoc.v:180951$11364_Y + connect \$12 $not$libresoc.v:180952$11365_Y + connect \$15 $not$libresoc.v:180953$11366_Y + connect \$1 $not$libresoc.v:180954$11367_Y + connect \$3 $not$libresoc.v:180955$11368_Y + connect \$6 $not$libresoc.v:180956$11369_Y end -attribute \src "libresoc.v:179454.1-179925.10" +attribute \src "libresoc.v:181422.1-181977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:179455.7-179455.20" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 + attribute \src "libresoc.v:181528.3-181529.49" + wire width 4 $0\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181423.7-181423.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $0\r24__data_o$next[3:0]$11423 - attribute \src "libresoc.v:179538.3-179539.39" + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $0\r24__data_o$next[3:0]$11493 + attribute \src "libresoc.v:181518.3-181519.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $0\r4__data_o$next[3:0]$11409 - attribute \src "libresoc.v:179540.3-179541.37" + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $0\r4__data_o$next[3:0]$11555 + attribute \src "libresoc.v:181520.3-181521.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $0\reg$next[3:0]$11375 - attribute \src "libresoc.v:179536.3-179537.25" + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $0\reg$next[3:0]$11507 + attribute \src "libresoc.v:181516.3-181517.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $0\src14__data_o$next[3:0]$11366 - attribute \src "libresoc.v:179546.3-179547.43" + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $0\src14__data_o$next[3:0]$11513 + attribute \src "libresoc.v:181526.3-181527.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $0\src24__data_o$next[3:0]$11381 - attribute \src "libresoc.v:179544.3-179545.43" + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $0\src24__data_o$next[3:0]$11527 + attribute \src "libresoc.v:181524.3-181525.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $0\src34__data_o$next[3:0]$11395 - attribute \src "libresoc.v:179542.3-179543.43" + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $0\src34__data_o$next[3:0]$11541 + attribute \src "libresoc.v:181522.3-181523.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:179825.3-179854.6" - wire $0\wr_detect$10[0:0]$11417 - attribute \src "libresoc.v:179895.3-179924.6" - wire $0\wr_detect$13[0:0]$11431 - attribute \src "libresoc.v:179685.3-179714.6" - wire $0\wr_detect$4[0:0]$11389 - attribute \src "libresoc.v:179755.3-179784.6" - wire $0\wr_detect$7[0:0]$11403 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181877.3-181906.6" + wire $0\wr_detect$10[0:0]$11549 + attribute \src "libresoc.v:181947.3-181976.6" + wire $0\wr_detect$13[0:0]$11563 + attribute \src "libresoc.v:181640.3-181669.6" + wire $0\wr_detect$16[0:0]$11501 + attribute \src "libresoc.v:181737.3-181766.6" + wire $0\wr_detect$4[0:0]$11521 + attribute \src "libresoc.v:181807.3-181836.6" + wire $0\wr_detect$7[0:0]$11535 + attribute \src "libresoc.v:181570.3-181599.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $1\r24__data_o$next[3:0]$11424 - attribute \src "libresoc.v:179480.13-179480.31" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 + attribute \src "libresoc.v:181442.13-181442.36" + wire width 4 $1\cr_pred4__data_o[3:0] + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $1\r24__data_o$next[3:0]$11494 + attribute \src "libresoc.v:181457.13-181457.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $1\r4__data_o$next[3:0]$11410 - attribute \src "libresoc.v:179487.13-179487.30" + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $1\r4__data_o$next[3:0]$11556 + attribute \src "libresoc.v:181464.13-181464.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $1\reg$next[3:0]$11376 - attribute \src "libresoc.v:179493.13-179493.25" + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $1\reg$next[3:0]$11508 + attribute \src "libresoc.v:181470.13-181470.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $1\src14__data_o$next[3:0]$11367 - attribute \src "libresoc.v:179498.13-179498.33" + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $1\src14__data_o$next[3:0]$11514 + attribute \src "libresoc.v:181475.13-181475.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $1\src24__data_o$next[3:0]$11382 - attribute \src "libresoc.v:179505.13-179505.33" + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $1\src24__data_o$next[3:0]$11528 + attribute \src "libresoc.v:181482.13-181482.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $1\src34__data_o$next[3:0]$11396 - attribute \src "libresoc.v:179512.13-179512.33" + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $1\src34__data_o$next[3:0]$11542 + attribute \src "libresoc.v:181489.13-181489.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:179825.3-179854.6" - wire $1\wr_detect$10[0:0]$11418 - attribute \src "libresoc.v:179895.3-179924.6" - wire $1\wr_detect$13[0:0]$11432 - attribute \src "libresoc.v:179685.3-179714.6" - wire $1\wr_detect$4[0:0]$11390 - attribute \src "libresoc.v:179755.3-179784.6" - wire $1\wr_detect$7[0:0]$11404 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181877.3-181906.6" + wire $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181947.3-181976.6" + wire $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181640.3-181669.6" + wire $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181737.3-181766.6" + wire $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181807.3-181836.6" + wire $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181570.3-181599.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $2\r24__data_o$next[3:0]$11425 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $2\r4__data_o$next[3:0]$11411 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $2\reg$next[3:0]$11377 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $2\src14__data_o$next[3:0]$11368 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $2\src24__data_o$next[3:0]$11383 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $2\src34__data_o$next[3:0]$11397 - attribute \src "libresoc.v:179825.3-179854.6" - wire $2\wr_detect$10[0:0]$11419 - attribute \src "libresoc.v:179895.3-179924.6" - wire $2\wr_detect$13[0:0]$11433 - attribute \src "libresoc.v:179685.3-179714.6" - wire $2\wr_detect$4[0:0]$11391 - attribute \src "libresoc.v:179755.3-179784.6" - wire $2\wr_detect$7[0:0]$11405 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $2\r24__data_o$next[3:0]$11495 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $2\r4__data_o$next[3:0]$11557 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $2\reg$next[3:0]$11509 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $2\src14__data_o$next[3:0]$11515 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $2\src24__data_o$next[3:0]$11529 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $2\src34__data_o$next[3:0]$11543 + attribute \src "libresoc.v:181877.3-181906.6" + wire $2\wr_detect$10[0:0]$11551 + attribute \src "libresoc.v:181947.3-181976.6" + wire $2\wr_detect$13[0:0]$11565 + attribute \src "libresoc.v:181640.3-181669.6" + wire $2\wr_detect$16[0:0]$11503 + attribute \src "libresoc.v:181737.3-181766.6" + wire $2\wr_detect$4[0:0]$11523 + attribute \src "libresoc.v:181807.3-181836.6" + wire $2\wr_detect$7[0:0]$11537 + attribute \src "libresoc.v:181570.3-181599.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $3\r24__data_o$next[3:0]$11426 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $3\r4__data_o$next[3:0]$11412 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $3\reg$next[3:0]$11378 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $3\src14__data_o$next[3:0]$11369 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $3\src24__data_o$next[3:0]$11384 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $3\src34__data_o$next[3:0]$11398 - attribute \src "libresoc.v:179825.3-179854.6" - wire $3\wr_detect$10[0:0]$11420 - attribute \src "libresoc.v:179895.3-179924.6" - wire $3\wr_detect$13[0:0]$11434 - attribute \src "libresoc.v:179685.3-179714.6" - wire $3\wr_detect$4[0:0]$11392 - attribute \src "libresoc.v:179755.3-179784.6" - wire $3\wr_detect$7[0:0]$11406 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $3\r24__data_o$next[3:0]$11496 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $3\r4__data_o$next[3:0]$11558 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $3\reg$next[3:0]$11510 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $3\src14__data_o$next[3:0]$11516 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $3\src24__data_o$next[3:0]$11530 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $3\src34__data_o$next[3:0]$11544 + attribute \src "libresoc.v:181877.3-181906.6" + wire $3\wr_detect$10[0:0]$11552 + attribute \src "libresoc.v:181947.3-181976.6" + wire $3\wr_detect$13[0:0]$11566 + attribute \src "libresoc.v:181640.3-181669.6" + wire $3\wr_detect$16[0:0]$11504 + attribute \src "libresoc.v:181737.3-181766.6" + wire $3\wr_detect$4[0:0]$11524 + attribute \src "libresoc.v:181807.3-181836.6" + wire $3\wr_detect$7[0:0]$11538 + attribute \src "libresoc.v:181570.3-181599.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $4\r24__data_o$next[3:0]$11427 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $4\r4__data_o$next[3:0]$11413 - attribute \src "libresoc.v:179618.3-179644.6" - wire width 4 $4\reg$next[3:0]$11379 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $4\src14__data_o$next[3:0]$11370 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $4\src24__data_o$next[3:0]$11385 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $4\src34__data_o$next[3:0]$11399 - attribute \src "libresoc.v:179825.3-179854.6" - wire $4\wr_detect$10[0:0]$11421 - attribute \src "libresoc.v:179895.3-179924.6" - wire $4\wr_detect$13[0:0]$11435 - attribute \src "libresoc.v:179685.3-179714.6" - wire $4\wr_detect$4[0:0]$11393 - attribute \src "libresoc.v:179755.3-179784.6" - wire $4\wr_detect$7[0:0]$11407 - attribute \src "libresoc.v:179588.3-179617.6" + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $4\r24__data_o$next[3:0]$11497 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $4\r4__data_o$next[3:0]$11559 + attribute \src "libresoc.v:181670.3-181696.6" + wire width 4 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $4\src14__data_o$next[3:0]$11517 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $4\src24__data_o$next[3:0]$11531 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $4\src34__data_o$next[3:0]$11545 + attribute \src "libresoc.v:181877.3-181906.6" + wire $4\wr_detect$10[0:0]$11553 + attribute \src "libresoc.v:181947.3-181976.6" + wire $4\wr_detect$13[0:0]$11567 + attribute \src "libresoc.v:181640.3-181669.6" + wire $4\wr_detect$16[0:0]$11505 + attribute \src "libresoc.v:181737.3-181766.6" + wire $4\wr_detect$4[0:0]$11525 + attribute \src "libresoc.v:181807.3-181836.6" + wire $4\wr_detect$7[0:0]$11539 + attribute \src "libresoc.v:181570.3-181599.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $5\r24__data_o$next[3:0]$11428 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $5\r4__data_o$next[3:0]$11414 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $5\src14__data_o$next[3:0]$11371 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $5\src24__data_o$next[3:0]$11386 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $5\src34__data_o$next[3:0]$11400 - attribute \src "libresoc.v:179855.3-179894.6" - wire width 4 $6\r24__data_o$next[3:0]$11429 - attribute \src "libresoc.v:179785.3-179824.6" - wire width 4 $6\r4__data_o$next[3:0]$11415 - attribute \src "libresoc.v:179548.3-179587.6" - wire width 4 $6\src14__data_o$next[3:0]$11372 - attribute \src "libresoc.v:179645.3-179684.6" - wire width 4 $6\src24__data_o$next[3:0]$11387 - attribute \src "libresoc.v:179715.3-179754.6" - wire width 4 $6\src34__data_o$next[3:0]$11401 - attribute \src "libresoc.v:179531.17-179531.104" - wire $not$libresoc.v:179531$11354_Y - attribute \src "libresoc.v:179532.18-179532.105" - wire $not$libresoc.v:179532$11355_Y - attribute \src "libresoc.v:179533.17-179533.100" - wire $not$libresoc.v:179533$11356_Y - attribute \src "libresoc.v:179534.17-179534.103" - wire $not$libresoc.v:179534$11357_Y - attribute \src "libresoc.v:179535.17-179535.103" - wire $not$libresoc.v:179535$11358_Y + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $5\r24__data_o$next[3:0]$11498 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $5\r4__data_o$next[3:0]$11560 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $5\src14__data_o$next[3:0]$11518 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $5\src24__data_o$next[3:0]$11532 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $5\src34__data_o$next[3:0]$11546 + attribute \src "libresoc.v:181530.3-181569.6" + wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181600.3-181639.6" + wire width 4 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181907.3-181946.6" + wire width 4 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181697.3-181736.6" + wire width 4 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181767.3-181806.6" + wire width 4 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181837.3-181876.6" + wire width 4 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181510.17-181510.104" + wire $not$libresoc.v:181510$11470_Y + attribute \src "libresoc.v:181511.18-181511.105" + wire $not$libresoc.v:181511$11471_Y + attribute \src "libresoc.v:181512.18-181512.105" + wire $not$libresoc.v:181512$11472_Y + attribute \src "libresoc.v:181513.17-181513.100" + wire $not$libresoc.v:181513$11473_Y + attribute \src "libresoc.v:181514.17-181514.103" + wire $not$libresoc.v:181514$11474_Y + attribute \src "libresoc.v:181515.17-181515.103" + wire $not$libresoc.v:181515$11475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest14__data_i + wire width 4 output 3 \cr_pred4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest14__wen + wire input 10 \dest14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest24__data_i + wire width 4 input 13 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest24__wen - attribute \src "libresoc.v:179455.7-179455.15" + wire input 12 \dest24__wen + attribute \src "libresoc.v:181423.7-181423.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r24__data_o + wire width 4 output 16 \r24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r24__ren + wire input 17 \r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r4__data_o + wire width 4 output 14 \r4__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r4__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r4__ren + wire input 15 \r4__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src14__data_o + wire width 4 output 5 \src14__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src14__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src14__ren + wire input 4 \src14__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src24__data_o + wire width 4 output 7 \src24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src24__ren + wire input 6 \src24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src34__data_o + wire width 4 output 9 \src34__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src34__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src34__ren + wire input 8 \src34__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w4__data_i + wire width 4 input 18 \w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w4__wen + wire input 19 \w4__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -370116,232 +373407,257 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179531$11354 + cell $not $not$libresoc.v:181510$11470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179531$11354_Y + connect \Y $not$libresoc.v:181510$11470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179532$11355 + cell $not $not$libresoc.v:181511$11471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179532$11355_Y + connect \Y $not$libresoc.v:181511$11471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179533$11356 + cell $not $not$libresoc.v:181512$11472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:181512$11472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181513$11473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179533$11356_Y + connect \Y $not$libresoc.v:181513$11473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179534$11357 + cell $not $not$libresoc.v:181514$11474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179534$11357_Y + connect \Y $not$libresoc.v:181514$11474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179535$11358 + cell $not $not$libresoc.v:181515$11475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179535$11358_Y + connect \Y $not$libresoc.v:181515$11475_Y end - attribute \src "libresoc.v:179455.7-179455.20" - process $proc$libresoc.v:179455$11436 + attribute \src "libresoc.v:181423.7-181423.20" + process $proc$libresoc.v:181423$11568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179480.13-179480.31" - process $proc$libresoc.v:179480$11437 + attribute \src "libresoc.v:181442.13-181442.36" + process $proc$libresoc.v:181442$11569 + assign { } { } + assign $1\cr_pred4__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181457.13-181457.31" + process $proc$libresoc.v:181457$11570 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:179487.13-179487.30" - process $proc$libresoc.v:179487$11438 + attribute \src "libresoc.v:181464.13-181464.30" + process $proc$libresoc.v:181464$11571 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:179493.13-179493.25" - process $proc$libresoc.v:179493$11439 + attribute \src "libresoc.v:181470.13-181470.25" + process $proc$libresoc.v:181470$11572 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179498.13-179498.33" - process $proc$libresoc.v:179498$11440 + attribute \src "libresoc.v:181475.13-181475.33" + process $proc$libresoc.v:181475$11573 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:179505.13-179505.33" - process $proc$libresoc.v:179505$11441 + attribute \src "libresoc.v:181482.13-181482.33" + process $proc$libresoc.v:181482$11574 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:179512.13-179512.33" - process $proc$libresoc.v:179512$11442 + attribute \src "libresoc.v:181489.13-181489.33" + process $proc$libresoc.v:181489$11575 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:179536.3-179537.25" - process $proc$libresoc.v:179536$11359 + attribute \src "libresoc.v:181516.3-181517.25" + process $proc$libresoc.v:181516$11476 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179538.3-179539.39" - process $proc$libresoc.v:179538$11360 + attribute \src "libresoc.v:181518.3-181519.39" + process $proc$libresoc.v:181518$11477 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:179540.3-179541.37" - process $proc$libresoc.v:179540$11361 + attribute \src "libresoc.v:181520.3-181521.37" + process $proc$libresoc.v:181520$11478 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:179542.3-179543.43" - process $proc$libresoc.v:179542$11362 + attribute \src "libresoc.v:181522.3-181523.43" + process $proc$libresoc.v:181522$11479 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:179544.3-179545.43" - process $proc$libresoc.v:179544$11363 + attribute \src "libresoc.v:181524.3-181525.43" + process $proc$libresoc.v:181524$11480 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:179546.3-179547.43" - process $proc$libresoc.v:179546$11364 + attribute \src "libresoc.v:181526.3-181527.43" + process $proc$libresoc.v:181526$11481 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:179548.3-179587.6" - process $proc$libresoc.v:179548$11365 + attribute \src "libresoc.v:181528.3-181529.49" + process $proc$libresoc.v:181528$11482 assign { } { } + assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next + sync posedge \coresync_clk + update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] + end + attribute \src "libresoc.v:181530.3-181569.6" + process $proc$libresoc.v:181530$11483 assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11366 $6\src14__data_o$next[3:0]$11372 - attribute \src "libresoc.v:179549.5-179549.29" + assign { } { } + assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 + attribute \src "libresoc.v:181531.5-181531.29" switch \initial - attribute \src "libresoc.v:179549.9-179549.17" + attribute \src "libresoc.v:181531.9-181531.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + switch \cr_pred4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11367 $5\src14__data_o$next[3:0]$11371 + assign $1\cr_pred4__data_o$next[3:0]$11485 $5\cr_pred4__data_o$next[3:0]$11489 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11368 \dest14__data_i + assign $2\cr_pred4__data_o$next[3:0]$11486 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11368 4'0000 + assign $2\cr_pred4__data_o$next[3:0]$11486 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11369 \dest24__data_i + assign $3\cr_pred4__data_o$next[3:0]$11487 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11369 $2\src14__data_o$next[3:0]$11368 + assign $3\cr_pred4__data_o$next[3:0]$11487 $2\cr_pred4__data_o$next[3:0]$11486 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11370 \w4__data_i + assign $4\cr_pred4__data_o$next[3:0]$11488 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11370 $3\src14__data_o$next[3:0]$11369 + assign $4\cr_pred4__data_o$next[3:0]$11488 $3\cr_pred4__data_o$next[3:0]$11487 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11371 \reg + assign $5\cr_pred4__data_o$next[3:0]$11489 \reg case - assign $5\src14__data_o$next[3:0]$11371 $4\src14__data_o$next[3:0]$11370 + assign $5\cr_pred4__data_o$next[3:0]$11489 $4\cr_pred4__data_o$next[3:0]$11488 end case - assign $1\src14__data_o$next[3:0]$11367 4'0000 + assign $1\cr_pred4__data_o$next[3:0]$11485 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11372 4'0000 + assign $6\cr_pred4__data_o$next[3:0]$11490 4'0000 case - assign $6\src14__data_o$next[3:0]$11372 $1\src14__data_o$next[3:0]$11367 + assign $6\cr_pred4__data_o$next[3:0]$11490 $1\cr_pred4__data_o$next[3:0]$11485 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11366 + update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 end - attribute \src "libresoc.v:179588.3-179617.6" - process $proc$libresoc.v:179588$11373 + attribute \src "libresoc.v:181570.3-181599.6" + process $proc$libresoc.v:181570$11491 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179589.5-179589.29" + attribute \src "libresoc.v:181571.5-181571.29" switch \initial - attribute \src "libresoc.v:179589.9-179589.17" + attribute \src "libresoc.v:181571.9-181571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + switch \cr_pred4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -370382,798 +373698,962 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179618.3-179644.6" - process $proc$libresoc.v:179618$11374 - assign { } { } - assign { } { } + attribute \src "libresoc.v:181600.3-181639.6" + process $proc$libresoc.v:181600$11492 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11375 $4\reg$next[3:0]$11379 - attribute \src "libresoc.v:179619.5-179619.29" + assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 + attribute \src "libresoc.v:181601.5-181601.29" switch \initial - attribute \src "libresoc.v:179619.9-179619.17" + attribute \src "libresoc.v:181601.9-181601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest14__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11376 \dest14__data_i - case - assign $1\reg$next[3:0]$11376 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11377 \dest24__data_i - case - assign $2\reg$next[3:0]$11377 $1\reg$next[3:0]$11376 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11378 \w4__data_i + assign { } { } + assign $1\r24__data_o$next[3:0]$11494 $5\r24__data_o$next[3:0]$11498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$11495 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$11495 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$11496 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$11496 $2\r24__data_o$next[3:0]$11495 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$11497 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$11497 $3\r24__data_o$next[3:0]$11496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$11498 \reg + case + assign $5\r24__data_o$next[3:0]$11498 $4\r24__data_o$next[3:0]$11497 + end case - assign $3\reg$next[3:0]$11378 $2\reg$next[3:0]$11377 + assign $1\r24__data_o$next[3:0]$11494 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11379 4'0000 + assign $6\r24__data_o$next[3:0]$11499 4'0000 case - assign $4\reg$next[3:0]$11379 $3\reg$next[3:0]$11378 + assign $6\r24__data_o$next[3:0]$11499 $1\r24__data_o$next[3:0]$11494 end sync always - update \reg$next $0\reg$next[3:0]$11375 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 end - attribute \src "libresoc.v:179645.3-179684.6" - process $proc$libresoc.v:179645$11380 - assign { } { } + attribute \src "libresoc.v:181640.3-181669.6" + process $proc$libresoc.v:181640$11500 assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11381 $6\src24__data_o$next[3:0]$11387 - attribute \src "libresoc.v:179646.5-179646.29" + assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 + attribute \src "libresoc.v:181641.5-181641.29" switch \initial - attribute \src "libresoc.v:179646.9-179646.17" + attribute \src "libresoc.v:181641.9-181641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11382 $5\src24__data_o$next[3:0]$11386 + assign $1\wr_detect$16[0:0]$11502 $4\wr_detect$16[0:0]$11505 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11383 \dest14__data_i + assign $2\wr_detect$16[0:0]$11503 1'1 case - assign $2\src24__data_o$next[3:0]$11383 4'0000 + assign $2\wr_detect$16[0:0]$11503 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11384 \dest24__data_i + assign $3\wr_detect$16[0:0]$11504 1'1 case - assign $3\src24__data_o$next[3:0]$11384 $2\src24__data_o$next[3:0]$11383 + assign $3\wr_detect$16[0:0]$11504 $2\wr_detect$16[0:0]$11503 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11385 \w4__data_i + assign $4\wr_detect$16[0:0]$11505 1'1 case - assign $4\src24__data_o$next[3:0]$11385 $3\src24__data_o$next[3:0]$11384 + assign $4\wr_detect$16[0:0]$11505 $3\wr_detect$16[0:0]$11504 + end + case + assign $1\wr_detect$16[0:0]$11502 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11501 + end + attribute \src "libresoc.v:181670.3-181696.6" + process $proc$libresoc.v:181670$11506 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 + attribute \src "libresoc.v:181671.5-181671.29" + switch \initial + attribute \src "libresoc.v:181671.9-181671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11508 \dest14__data_i + case + assign $1\reg$next[3:0]$11508 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11509 \dest24__data_i + case + assign $2\reg$next[3:0]$11509 $1\reg$next[3:0]$11508 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11510 \w4__data_i + case + assign $3\reg$next[3:0]$11510 $2\reg$next[3:0]$11509 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11511 4'0000 + case + assign $4\reg$next[3:0]$11511 $3\reg$next[3:0]$11510 + end + sync always + update \reg$next $0\reg$next[3:0]$11507 + end + attribute \src "libresoc.v:181697.3-181736.6" + process $proc$libresoc.v:181697$11512 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 + attribute \src "libresoc.v:181698.5-181698.29" + switch \initial + attribute \src "libresoc.v:181698.9-181698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$11514 $5\src14__data_o$next[3:0]$11518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$11515 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$11515 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$11516 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$11516 $2\src14__data_o$next[3:0]$11515 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$11517 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$11517 $3\src14__data_o$next[3:0]$11516 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11386 \reg + assign $5\src14__data_o$next[3:0]$11518 \reg case - assign $5\src24__data_o$next[3:0]$11386 $4\src24__data_o$next[3:0]$11385 + assign $5\src14__data_o$next[3:0]$11518 $4\src14__data_o$next[3:0]$11517 end case - assign $1\src24__data_o$next[3:0]$11382 4'0000 + assign $1\src14__data_o$next[3:0]$11514 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11387 4'0000 + assign $6\src14__data_o$next[3:0]$11519 4'0000 case - assign $6\src24__data_o$next[3:0]$11387 $1\src24__data_o$next[3:0]$11382 + assign $6\src14__data_o$next[3:0]$11519 $1\src14__data_o$next[3:0]$11514 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11381 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 end - attribute \src "libresoc.v:179685.3-179714.6" - process $proc$libresoc.v:179685$11388 + attribute \src "libresoc.v:181737.3-181766.6" + process $proc$libresoc.v:181737$11520 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11389 $1\wr_detect$4[0:0]$11390 - attribute \src "libresoc.v:179686.5-179686.29" + assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:181738.5-181738.29" switch \initial - attribute \src "libresoc.v:179686.9-179686.17" + attribute \src "libresoc.v:181738.9-181738.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11390 $4\wr_detect$4[0:0]$11393 + assign $1\wr_detect$4[0:0]$11522 $4\wr_detect$4[0:0]$11525 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11391 1'1 + assign $2\wr_detect$4[0:0]$11523 1'1 case - assign $2\wr_detect$4[0:0]$11391 1'0 + assign $2\wr_detect$4[0:0]$11523 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11392 1'1 + assign $3\wr_detect$4[0:0]$11524 1'1 case - assign $3\wr_detect$4[0:0]$11392 $2\wr_detect$4[0:0]$11391 + assign $3\wr_detect$4[0:0]$11524 $2\wr_detect$4[0:0]$11523 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11393 1'1 + assign $4\wr_detect$4[0:0]$11525 1'1 case - assign $4\wr_detect$4[0:0]$11393 $3\wr_detect$4[0:0]$11392 + assign $4\wr_detect$4[0:0]$11525 $3\wr_detect$4[0:0]$11524 end case - assign $1\wr_detect$4[0:0]$11390 1'0 + assign $1\wr_detect$4[0:0]$11522 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11389 + update \wr_detect$4 $0\wr_detect$4[0:0]$11521 end - attribute \src "libresoc.v:179715.3-179754.6" - process $proc$libresoc.v:179715$11394 + attribute \src "libresoc.v:181767.3-181806.6" + process $proc$libresoc.v:181767$11526 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11395 $6\src34__data_o$next[3:0]$11401 - attribute \src "libresoc.v:179716.5-179716.29" + assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 + attribute \src "libresoc.v:181768.5-181768.29" switch \initial - attribute \src "libresoc.v:179716.9-179716.17" + attribute \src "libresoc.v:181768.9-181768.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11396 $5\src34__data_o$next[3:0]$11400 + assign $1\src24__data_o$next[3:0]$11528 $5\src24__data_o$next[3:0]$11532 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11397 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11529 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11397 4'0000 + assign $2\src24__data_o$next[3:0]$11529 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11398 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11530 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11398 $2\src34__data_o$next[3:0]$11397 + assign $3\src24__data_o$next[3:0]$11530 $2\src24__data_o$next[3:0]$11529 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11399 \w4__data_i + assign $4\src24__data_o$next[3:0]$11531 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11399 $3\src34__data_o$next[3:0]$11398 + assign $4\src24__data_o$next[3:0]$11531 $3\src24__data_o$next[3:0]$11530 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11400 \reg + assign $5\src24__data_o$next[3:0]$11532 \reg case - assign $5\src34__data_o$next[3:0]$11400 $4\src34__data_o$next[3:0]$11399 + assign $5\src24__data_o$next[3:0]$11532 $4\src24__data_o$next[3:0]$11531 end case - assign $1\src34__data_o$next[3:0]$11396 4'0000 + assign $1\src24__data_o$next[3:0]$11528 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11401 4'0000 + assign $6\src24__data_o$next[3:0]$11533 4'0000 case - assign $6\src34__data_o$next[3:0]$11401 $1\src34__data_o$next[3:0]$11396 + assign $6\src24__data_o$next[3:0]$11533 $1\src24__data_o$next[3:0]$11528 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11395 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 end - attribute \src "libresoc.v:179755.3-179784.6" - process $proc$libresoc.v:179755$11402 + attribute \src "libresoc.v:181807.3-181836.6" + process $proc$libresoc.v:181807$11534 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11403 $1\wr_detect$7[0:0]$11404 - attribute \src "libresoc.v:179756.5-179756.29" + assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:181808.5-181808.29" switch \initial - attribute \src "libresoc.v:179756.9-179756.17" + attribute \src "libresoc.v:181808.9-181808.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11404 $4\wr_detect$7[0:0]$11407 + assign $1\wr_detect$7[0:0]$11536 $4\wr_detect$7[0:0]$11539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11405 1'1 + assign $2\wr_detect$7[0:0]$11537 1'1 case - assign $2\wr_detect$7[0:0]$11405 1'0 + assign $2\wr_detect$7[0:0]$11537 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11406 1'1 + assign $3\wr_detect$7[0:0]$11538 1'1 case - assign $3\wr_detect$7[0:0]$11406 $2\wr_detect$7[0:0]$11405 + assign $3\wr_detect$7[0:0]$11538 $2\wr_detect$7[0:0]$11537 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11407 1'1 + assign $4\wr_detect$7[0:0]$11539 1'1 case - assign $4\wr_detect$7[0:0]$11407 $3\wr_detect$7[0:0]$11406 + assign $4\wr_detect$7[0:0]$11539 $3\wr_detect$7[0:0]$11538 end case - assign $1\wr_detect$7[0:0]$11404 1'0 + assign $1\wr_detect$7[0:0]$11536 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11403 + update \wr_detect$7 $0\wr_detect$7[0:0]$11535 end - attribute \src "libresoc.v:179785.3-179824.6" - process $proc$libresoc.v:179785$11408 + attribute \src "libresoc.v:181837.3-181876.6" + process $proc$libresoc.v:181837$11540 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11409 $6\r4__data_o$next[3:0]$11415 - attribute \src "libresoc.v:179786.5-179786.29" + assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 + attribute \src "libresoc.v:181838.5-181838.29" switch \initial - attribute \src "libresoc.v:179786.9-179786.17" + attribute \src "libresoc.v:181838.9-181838.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11410 $5\r4__data_o$next[3:0]$11414 + assign $1\src34__data_o$next[3:0]$11542 $5\src34__data_o$next[3:0]$11546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11411 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11543 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11411 4'0000 + assign $2\src34__data_o$next[3:0]$11543 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11412 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11544 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11412 $2\r4__data_o$next[3:0]$11411 + assign $3\src34__data_o$next[3:0]$11544 $2\src34__data_o$next[3:0]$11543 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11413 \w4__data_i + assign $4\src34__data_o$next[3:0]$11545 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11413 $3\r4__data_o$next[3:0]$11412 + assign $4\src34__data_o$next[3:0]$11545 $3\src34__data_o$next[3:0]$11544 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11414 \reg + assign $5\src34__data_o$next[3:0]$11546 \reg case - assign $5\r4__data_o$next[3:0]$11414 $4\r4__data_o$next[3:0]$11413 + assign $5\src34__data_o$next[3:0]$11546 $4\src34__data_o$next[3:0]$11545 end case - assign $1\r4__data_o$next[3:0]$11410 4'0000 + assign $1\src34__data_o$next[3:0]$11542 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11415 4'0000 + assign $6\src34__data_o$next[3:0]$11547 4'0000 case - assign $6\r4__data_o$next[3:0]$11415 $1\r4__data_o$next[3:0]$11410 + assign $6\src34__data_o$next[3:0]$11547 $1\src34__data_o$next[3:0]$11542 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11409 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 end - attribute \src "libresoc.v:179825.3-179854.6" - process $proc$libresoc.v:179825$11416 + attribute \src "libresoc.v:181877.3-181906.6" + process $proc$libresoc.v:181877$11548 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11417 $1\wr_detect$10[0:0]$11418 - attribute \src "libresoc.v:179826.5-179826.29" + assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:181878.5-181878.29" switch \initial - attribute \src "libresoc.v:179826.9-179826.17" + attribute \src "libresoc.v:181878.9-181878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11418 $4\wr_detect$10[0:0]$11421 + assign $1\wr_detect$10[0:0]$11550 $4\wr_detect$10[0:0]$11553 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11419 1'1 + assign $2\wr_detect$10[0:0]$11551 1'1 case - assign $2\wr_detect$10[0:0]$11419 1'0 + assign $2\wr_detect$10[0:0]$11551 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11420 1'1 + assign $3\wr_detect$10[0:0]$11552 1'1 case - assign $3\wr_detect$10[0:0]$11420 $2\wr_detect$10[0:0]$11419 + assign $3\wr_detect$10[0:0]$11552 $2\wr_detect$10[0:0]$11551 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11421 1'1 + assign $4\wr_detect$10[0:0]$11553 1'1 case - assign $4\wr_detect$10[0:0]$11421 $3\wr_detect$10[0:0]$11420 + assign $4\wr_detect$10[0:0]$11553 $3\wr_detect$10[0:0]$11552 end case - assign $1\wr_detect$10[0:0]$11418 1'0 + assign $1\wr_detect$10[0:0]$11550 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11417 + update \wr_detect$10 $0\wr_detect$10[0:0]$11549 end - attribute \src "libresoc.v:179855.3-179894.6" - process $proc$libresoc.v:179855$11422 + attribute \src "libresoc.v:181907.3-181946.6" + process $proc$libresoc.v:181907$11554 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11423 $6\r24__data_o$next[3:0]$11429 - attribute \src "libresoc.v:179856.5-179856.29" + assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 + attribute \src "libresoc.v:181908.5-181908.29" switch \initial - attribute \src "libresoc.v:179856.9-179856.17" + attribute \src "libresoc.v:181908.9-181908.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11424 $5\r24__data_o$next[3:0]$11428 + assign $1\r4__data_o$next[3:0]$11556 $5\r4__data_o$next[3:0]$11560 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11425 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11557 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11425 4'0000 + assign $2\r4__data_o$next[3:0]$11557 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11426 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11558 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11426 $2\r24__data_o$next[3:0]$11425 + assign $3\r4__data_o$next[3:0]$11558 $2\r4__data_o$next[3:0]$11557 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11427 \w4__data_i + assign $4\r4__data_o$next[3:0]$11559 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11427 $3\r24__data_o$next[3:0]$11426 + assign $4\r4__data_o$next[3:0]$11559 $3\r4__data_o$next[3:0]$11558 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11428 \reg + assign $5\r4__data_o$next[3:0]$11560 \reg case - assign $5\r24__data_o$next[3:0]$11428 $4\r24__data_o$next[3:0]$11427 + assign $5\r4__data_o$next[3:0]$11560 $4\r4__data_o$next[3:0]$11559 end case - assign $1\r24__data_o$next[3:0]$11424 4'0000 + assign $1\r4__data_o$next[3:0]$11556 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11429 4'0000 + assign $6\r4__data_o$next[3:0]$11561 4'0000 case - assign $6\r24__data_o$next[3:0]$11429 $1\r24__data_o$next[3:0]$11424 + assign $6\r4__data_o$next[3:0]$11561 $1\r4__data_o$next[3:0]$11556 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11423 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 end - attribute \src "libresoc.v:179895.3-179924.6" - process $proc$libresoc.v:179895$11430 + attribute \src "libresoc.v:181947.3-181976.6" + process $proc$libresoc.v:181947$11562 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11431 $1\wr_detect$13[0:0]$11432 - attribute \src "libresoc.v:179896.5-179896.29" + assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:181948.5-181948.29" switch \initial - attribute \src "libresoc.v:179896.9-179896.17" + attribute \src "libresoc.v:181948.9-181948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11432 $4\wr_detect$13[0:0]$11435 + assign $1\wr_detect$13[0:0]$11564 $4\wr_detect$13[0:0]$11567 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11433 1'1 + assign $2\wr_detect$13[0:0]$11565 1'1 case - assign $2\wr_detect$13[0:0]$11433 1'0 + assign $2\wr_detect$13[0:0]$11565 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11434 1'1 + assign $3\wr_detect$13[0:0]$11566 1'1 case - assign $3\wr_detect$13[0:0]$11434 $2\wr_detect$13[0:0]$11433 + assign $3\wr_detect$13[0:0]$11566 $2\wr_detect$13[0:0]$11565 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11435 1'1 + assign $4\wr_detect$13[0:0]$11567 1'1 case - assign $4\wr_detect$13[0:0]$11435 $3\wr_detect$13[0:0]$11434 + assign $4\wr_detect$13[0:0]$11567 $3\wr_detect$13[0:0]$11566 end case - assign $1\wr_detect$13[0:0]$11432 1'0 + assign $1\wr_detect$13[0:0]$11564 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11431 + update \wr_detect$13 $0\wr_detect$13[0:0]$11563 end - connect \$9 $not$libresoc.v:179531$11354_Y - connect \$12 $not$libresoc.v:179532$11355_Y - connect \$1 $not$libresoc.v:179533$11356_Y - connect \$3 $not$libresoc.v:179534$11357_Y - connect \$6 $not$libresoc.v:179535$11358_Y + connect \$9 $not$libresoc.v:181510$11470_Y + connect \$12 $not$libresoc.v:181511$11471_Y + connect \$15 $not$libresoc.v:181512$11472_Y + connect \$1 $not$libresoc.v:181513$11473_Y + connect \$3 $not$libresoc.v:181514$11474_Y + connect \$6 $not$libresoc.v:181515$11475_Y end -attribute \src "libresoc.v:179929.1-180400.10" +attribute \src "libresoc.v:181981.1-182536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:179930.7-179930.20" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 + attribute \src "libresoc.v:182087.3-182088.49" + wire width 4 $0\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:181982.7-181982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $0\r25__data_o$next[3:0]$11512 - attribute \src "libresoc.v:180013.3-180014.39" + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $0\r25__data_o$next[3:0]$11599 + attribute \src "libresoc.v:182077.3-182078.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $0\r5__data_o$next[3:0]$11498 - attribute \src "libresoc.v:180015.3-180016.37" + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $0\r5__data_o$next[3:0]$11661 + attribute \src "libresoc.v:182079.3-182080.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $0\reg$next[3:0]$11464 - attribute \src "libresoc.v:180011.3-180012.25" + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $0\reg$next[3:0]$11613 + attribute \src "libresoc.v:182075.3-182076.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $0\src15__data_o$next[3:0]$11455 - attribute \src "libresoc.v:180021.3-180022.43" + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $0\src15__data_o$next[3:0]$11619 + attribute \src "libresoc.v:182085.3-182086.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $0\src25__data_o$next[3:0]$11470 - attribute \src "libresoc.v:180019.3-180020.43" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $0\src25__data_o$next[3:0]$11633 + attribute \src "libresoc.v:182083.3-182084.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $0\src35__data_o$next[3:0]$11484 - attribute \src "libresoc.v:180017.3-180018.43" + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $0\src35__data_o$next[3:0]$11647 + attribute \src "libresoc.v:182081.3-182082.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:180300.3-180329.6" - wire $0\wr_detect$10[0:0]$11506 - attribute \src "libresoc.v:180370.3-180399.6" - wire $0\wr_detect$13[0:0]$11520 - attribute \src "libresoc.v:180160.3-180189.6" - wire $0\wr_detect$4[0:0]$11478 - attribute \src "libresoc.v:180230.3-180259.6" - wire $0\wr_detect$7[0:0]$11492 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182436.3-182465.6" + wire $0\wr_detect$10[0:0]$11655 + attribute \src "libresoc.v:182506.3-182535.6" + wire $0\wr_detect$13[0:0]$11669 + attribute \src "libresoc.v:182199.3-182228.6" + wire $0\wr_detect$16[0:0]$11607 + attribute \src "libresoc.v:182296.3-182325.6" + wire $0\wr_detect$4[0:0]$11627 + attribute \src "libresoc.v:182366.3-182395.6" + wire $0\wr_detect$7[0:0]$11641 + attribute \src "libresoc.v:182129.3-182158.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $1\r25__data_o$next[3:0]$11513 - attribute \src "libresoc.v:179955.13-179955.31" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 + attribute \src "libresoc.v:182001.13-182001.36" + wire width 4 $1\cr_pred5__data_o[3:0] + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $1\r25__data_o$next[3:0]$11600 + attribute \src "libresoc.v:182016.13-182016.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $1\r5__data_o$next[3:0]$11499 - attribute \src "libresoc.v:179962.13-179962.30" + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $1\r5__data_o$next[3:0]$11662 + attribute \src "libresoc.v:182023.13-182023.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $1\reg$next[3:0]$11465 - attribute \src "libresoc.v:179968.13-179968.25" + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $1\reg$next[3:0]$11614 + attribute \src "libresoc.v:182029.13-182029.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $1\src15__data_o$next[3:0]$11456 - attribute \src "libresoc.v:179973.13-179973.33" + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $1\src15__data_o$next[3:0]$11620 + attribute \src "libresoc.v:182034.13-182034.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $1\src25__data_o$next[3:0]$11471 - attribute \src "libresoc.v:179980.13-179980.33" + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $1\src25__data_o$next[3:0]$11634 + attribute \src "libresoc.v:182041.13-182041.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $1\src35__data_o$next[3:0]$11485 - attribute \src "libresoc.v:179987.13-179987.33" + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $1\src35__data_o$next[3:0]$11648 + attribute \src "libresoc.v:182048.13-182048.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:180300.3-180329.6" - wire $1\wr_detect$10[0:0]$11507 - attribute \src "libresoc.v:180370.3-180399.6" - wire $1\wr_detect$13[0:0]$11521 - attribute \src "libresoc.v:180160.3-180189.6" - wire $1\wr_detect$4[0:0]$11479 - attribute \src "libresoc.v:180230.3-180259.6" - wire $1\wr_detect$7[0:0]$11493 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182436.3-182465.6" + wire $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182506.3-182535.6" + wire $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182199.3-182228.6" + wire $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182296.3-182325.6" + wire $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182366.3-182395.6" + wire $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182129.3-182158.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $2\r25__data_o$next[3:0]$11514 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $2\r5__data_o$next[3:0]$11500 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $2\reg$next[3:0]$11466 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $2\src15__data_o$next[3:0]$11457 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $2\src25__data_o$next[3:0]$11472 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $2\src35__data_o$next[3:0]$11486 - attribute \src "libresoc.v:180300.3-180329.6" - wire $2\wr_detect$10[0:0]$11508 - attribute \src "libresoc.v:180370.3-180399.6" - wire $2\wr_detect$13[0:0]$11522 - attribute \src "libresoc.v:180160.3-180189.6" - wire $2\wr_detect$4[0:0]$11480 - attribute \src "libresoc.v:180230.3-180259.6" - wire $2\wr_detect$7[0:0]$11494 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $2\r25__data_o$next[3:0]$11601 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $2\r5__data_o$next[3:0]$11663 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $2\reg$next[3:0]$11615 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $2\src15__data_o$next[3:0]$11621 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $2\src25__data_o$next[3:0]$11635 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $2\src35__data_o$next[3:0]$11649 + attribute \src "libresoc.v:182436.3-182465.6" + wire $2\wr_detect$10[0:0]$11657 + attribute \src "libresoc.v:182506.3-182535.6" + wire $2\wr_detect$13[0:0]$11671 + attribute \src "libresoc.v:182199.3-182228.6" + wire $2\wr_detect$16[0:0]$11609 + attribute \src "libresoc.v:182296.3-182325.6" + wire $2\wr_detect$4[0:0]$11629 + attribute \src "libresoc.v:182366.3-182395.6" + wire $2\wr_detect$7[0:0]$11643 + attribute \src "libresoc.v:182129.3-182158.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $3\r25__data_o$next[3:0]$11515 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $3\r5__data_o$next[3:0]$11501 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $3\reg$next[3:0]$11467 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $3\src15__data_o$next[3:0]$11458 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $3\src25__data_o$next[3:0]$11473 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $3\src35__data_o$next[3:0]$11487 - attribute \src "libresoc.v:180300.3-180329.6" - wire $3\wr_detect$10[0:0]$11509 - attribute \src "libresoc.v:180370.3-180399.6" - wire $3\wr_detect$13[0:0]$11523 - attribute \src "libresoc.v:180160.3-180189.6" - wire $3\wr_detect$4[0:0]$11481 - attribute \src "libresoc.v:180230.3-180259.6" - wire $3\wr_detect$7[0:0]$11495 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $3\r25__data_o$next[3:0]$11602 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $3\r5__data_o$next[3:0]$11664 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $3\reg$next[3:0]$11616 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $3\src15__data_o$next[3:0]$11622 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $3\src25__data_o$next[3:0]$11636 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $3\src35__data_o$next[3:0]$11650 + attribute \src "libresoc.v:182436.3-182465.6" + wire $3\wr_detect$10[0:0]$11658 + attribute \src "libresoc.v:182506.3-182535.6" + wire $3\wr_detect$13[0:0]$11672 + attribute \src "libresoc.v:182199.3-182228.6" + wire $3\wr_detect$16[0:0]$11610 + attribute \src "libresoc.v:182296.3-182325.6" + wire $3\wr_detect$4[0:0]$11630 + attribute \src "libresoc.v:182366.3-182395.6" + wire $3\wr_detect$7[0:0]$11644 + attribute \src "libresoc.v:182129.3-182158.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $4\r25__data_o$next[3:0]$11516 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $4\r5__data_o$next[3:0]$11502 - attribute \src "libresoc.v:180093.3-180119.6" - wire width 4 $4\reg$next[3:0]$11468 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $4\src15__data_o$next[3:0]$11459 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $4\src25__data_o$next[3:0]$11474 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $4\src35__data_o$next[3:0]$11488 - attribute \src "libresoc.v:180300.3-180329.6" - wire $4\wr_detect$10[0:0]$11510 - attribute \src "libresoc.v:180370.3-180399.6" - wire $4\wr_detect$13[0:0]$11524 - attribute \src "libresoc.v:180160.3-180189.6" - wire $4\wr_detect$4[0:0]$11482 - attribute \src "libresoc.v:180230.3-180259.6" - wire $4\wr_detect$7[0:0]$11496 - attribute \src "libresoc.v:180063.3-180092.6" + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $4\cr_pred5__data_o$next[3:0]$11594 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $4\r25__data_o$next[3:0]$11603 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $4\r5__data_o$next[3:0]$11665 + attribute \src "libresoc.v:182229.3-182255.6" + wire width 4 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $4\src15__data_o$next[3:0]$11623 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $4\src25__data_o$next[3:0]$11637 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $4\src35__data_o$next[3:0]$11651 + attribute \src "libresoc.v:182436.3-182465.6" + wire $4\wr_detect$10[0:0]$11659 + attribute \src "libresoc.v:182506.3-182535.6" + wire $4\wr_detect$13[0:0]$11673 + attribute \src "libresoc.v:182199.3-182228.6" + wire $4\wr_detect$16[0:0]$11611 + attribute \src "libresoc.v:182296.3-182325.6" + wire $4\wr_detect$4[0:0]$11631 + attribute \src "libresoc.v:182366.3-182395.6" + wire $4\wr_detect$7[0:0]$11645 + attribute \src "libresoc.v:182129.3-182158.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $5\r25__data_o$next[3:0]$11517 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $5\r5__data_o$next[3:0]$11503 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $5\src15__data_o$next[3:0]$11460 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $5\src25__data_o$next[3:0]$11475 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $5\src35__data_o$next[3:0]$11489 - attribute \src "libresoc.v:180330.3-180369.6" - wire width 4 $6\r25__data_o$next[3:0]$11518 - attribute \src "libresoc.v:180260.3-180299.6" - wire width 4 $6\r5__data_o$next[3:0]$11504 - attribute \src "libresoc.v:180023.3-180062.6" - wire width 4 $6\src15__data_o$next[3:0]$11461 - attribute \src "libresoc.v:180120.3-180159.6" - wire width 4 $6\src25__data_o$next[3:0]$11476 - attribute \src "libresoc.v:180190.3-180229.6" - wire width 4 $6\src35__data_o$next[3:0]$11490 - attribute \src "libresoc.v:180006.17-180006.104" - wire $not$libresoc.v:180006$11443_Y - attribute \src "libresoc.v:180007.18-180007.105" - wire $not$libresoc.v:180007$11444_Y - attribute \src "libresoc.v:180008.17-180008.100" - wire $not$libresoc.v:180008$11445_Y - attribute \src "libresoc.v:180009.17-180009.103" - wire $not$libresoc.v:180009$11446_Y - attribute \src "libresoc.v:180010.17-180010.103" - wire $not$libresoc.v:180010$11447_Y + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $5\cr_pred5__data_o$next[3:0]$11595 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $5\r25__data_o$next[3:0]$11604 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $5\r5__data_o$next[3:0]$11666 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $5\src15__data_o$next[3:0]$11624 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $5\src25__data_o$next[3:0]$11638 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $5\src35__data_o$next[3:0]$11652 + attribute \src "libresoc.v:182089.3-182128.6" + wire width 4 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182159.3-182198.6" + wire width 4 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182466.3-182505.6" + wire width 4 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182256.3-182295.6" + wire width 4 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182326.3-182365.6" + wire width 4 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182396.3-182435.6" + wire width 4 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182069.17-182069.104" + wire $not$libresoc.v:182069$11576_Y + attribute \src "libresoc.v:182070.18-182070.105" + wire $not$libresoc.v:182070$11577_Y + attribute \src "libresoc.v:182071.18-182071.105" + wire $not$libresoc.v:182071$11578_Y + attribute \src "libresoc.v:182072.17-182072.100" + wire $not$libresoc.v:182072$11579_Y + attribute \src "libresoc.v:182073.17-182073.103" + wire $not$libresoc.v:182073$11580_Y + attribute \src "libresoc.v:182074.17-182074.103" + wire $not$libresoc.v:182074$11581_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest15__data_i + wire width 4 output 3 \cr_pred5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \cr_pred5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cr_pred5__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest15__wen + wire width 4 input 11 \dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest25__data_i + wire input 10 \dest15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest25__wen - attribute \src "libresoc.v:179930.7-179930.15" + wire width 4 input 13 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest25__wen + attribute \src "libresoc.v:181982.7-181982.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r25__data_o + wire width 4 output 16 \r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r25__ren + wire input 17 \r25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r5__data_o + wire width 4 output 14 \r5__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r5__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r5__ren + wire input 15 \r5__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src15__data_o + wire width 4 output 5 \src15__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src15__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src15__ren + wire input 4 \src15__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src25__data_o + wire width 4 output 7 \src25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src25__ren + wire input 6 \src25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src35__data_o + wire width 4 output 9 \src35__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src35__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src35__ren + wire input 8 \src35__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w5__data_i + wire width 4 input 18 \w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w5__wen + wire input 19 \w5__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -371181,232 +374661,257 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180006$11443 + cell $not $not$libresoc.v:182069$11576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180006$11443_Y + connect \Y $not$libresoc.v:182069$11576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180007$11444 + cell $not $not$libresoc.v:182070$11577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180007$11444_Y + connect \Y $not$libresoc.v:182070$11577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182071$11578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182071$11578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180008$11445 + cell $not $not$libresoc.v:182072$11579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180008$11445_Y + connect \Y $not$libresoc.v:182072$11579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180009$11446 + cell $not $not$libresoc.v:182073$11580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180009$11446_Y + connect \Y $not$libresoc.v:182073$11580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180010$11447 + cell $not $not$libresoc.v:182074$11581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180010$11447_Y + connect \Y $not$libresoc.v:182074$11581_Y end - attribute \src "libresoc.v:179930.7-179930.20" - process $proc$libresoc.v:179930$11525 + attribute \src "libresoc.v:181982.7-181982.20" + process $proc$libresoc.v:181982$11674 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179955.13-179955.31" - process $proc$libresoc.v:179955$11526 + attribute \src "libresoc.v:182001.13-182001.36" + process $proc$libresoc.v:182001$11675 + assign { } { } + assign $1\cr_pred5__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182016.13-182016.31" + process $proc$libresoc.v:182016$11676 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:179962.13-179962.30" - process $proc$libresoc.v:179962$11527 + attribute \src "libresoc.v:182023.13-182023.30" + process $proc$libresoc.v:182023$11677 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:179968.13-179968.25" - process $proc$libresoc.v:179968$11528 + attribute \src "libresoc.v:182029.13-182029.25" + process $proc$libresoc.v:182029$11678 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179973.13-179973.33" - process $proc$libresoc.v:179973$11529 + attribute \src "libresoc.v:182034.13-182034.33" + process $proc$libresoc.v:182034$11679 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:179980.13-179980.33" - process $proc$libresoc.v:179980$11530 + attribute \src "libresoc.v:182041.13-182041.33" + process $proc$libresoc.v:182041$11680 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:179987.13-179987.33" - process $proc$libresoc.v:179987$11531 + attribute \src "libresoc.v:182048.13-182048.33" + process $proc$libresoc.v:182048$11681 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:180011.3-180012.25" - process $proc$libresoc.v:180011$11448 + attribute \src "libresoc.v:182075.3-182076.25" + process $proc$libresoc.v:182075$11582 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180013.3-180014.39" - process $proc$libresoc.v:180013$11449 + attribute \src "libresoc.v:182077.3-182078.39" + process $proc$libresoc.v:182077$11583 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:180015.3-180016.37" - process $proc$libresoc.v:180015$11450 + attribute \src "libresoc.v:182079.3-182080.37" + process $proc$libresoc.v:182079$11584 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:180017.3-180018.43" - process $proc$libresoc.v:180017$11451 + attribute \src "libresoc.v:182081.3-182082.43" + process $proc$libresoc.v:182081$11585 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:180019.3-180020.43" - process $proc$libresoc.v:180019$11452 + attribute \src "libresoc.v:182083.3-182084.43" + process $proc$libresoc.v:182083$11586 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:180021.3-180022.43" - process $proc$libresoc.v:180021$11453 + attribute \src "libresoc.v:182085.3-182086.43" + process $proc$libresoc.v:182085$11587 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:180023.3-180062.6" - process $proc$libresoc.v:180023$11454 + attribute \src "libresoc.v:182087.3-182088.49" + process $proc$libresoc.v:182087$11588 assign { } { } + assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next + sync posedge \coresync_clk + update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] + end + attribute \src "libresoc.v:182089.3-182128.6" + process $proc$libresoc.v:182089$11589 assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11455 $6\src15__data_o$next[3:0]$11461 - attribute \src "libresoc.v:180024.5-180024.29" + assign { } { } + assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 + attribute \src "libresoc.v:182090.5-182090.29" switch \initial - attribute \src "libresoc.v:180024.9-180024.17" + attribute \src "libresoc.v:182090.9-182090.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \cr_pred5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11456 $5\src15__data_o$next[3:0]$11460 + assign $1\cr_pred5__data_o$next[3:0]$11591 $5\cr_pred5__data_o$next[3:0]$11595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11457 \dest15__data_i + assign $2\cr_pred5__data_o$next[3:0]$11592 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11457 4'0000 + assign $2\cr_pred5__data_o$next[3:0]$11592 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11458 \dest25__data_i + assign $3\cr_pred5__data_o$next[3:0]$11593 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11458 $2\src15__data_o$next[3:0]$11457 + assign $3\cr_pred5__data_o$next[3:0]$11593 $2\cr_pred5__data_o$next[3:0]$11592 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11459 \w5__data_i + assign $4\cr_pred5__data_o$next[3:0]$11594 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11459 $3\src15__data_o$next[3:0]$11458 + assign $4\cr_pred5__data_o$next[3:0]$11594 $3\cr_pred5__data_o$next[3:0]$11593 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11460 \reg + assign $5\cr_pred5__data_o$next[3:0]$11595 \reg case - assign $5\src15__data_o$next[3:0]$11460 $4\src15__data_o$next[3:0]$11459 + assign $5\cr_pred5__data_o$next[3:0]$11595 $4\cr_pred5__data_o$next[3:0]$11594 end case - assign $1\src15__data_o$next[3:0]$11456 4'0000 + assign $1\cr_pred5__data_o$next[3:0]$11591 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11461 4'0000 + assign $6\cr_pred5__data_o$next[3:0]$11596 4'0000 case - assign $6\src15__data_o$next[3:0]$11461 $1\src15__data_o$next[3:0]$11456 + assign $6\cr_pred5__data_o$next[3:0]$11596 $1\cr_pred5__data_o$next[3:0]$11591 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11455 + update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 end - attribute \src "libresoc.v:180063.3-180092.6" - process $proc$libresoc.v:180063$11462 + attribute \src "libresoc.v:182129.3-182158.6" + process $proc$libresoc.v:182129$11597 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180064.5-180064.29" + attribute \src "libresoc.v:182130.5-182130.29" switch \initial - attribute \src "libresoc.v:180064.9-180064.17" + attribute \src "libresoc.v:182130.9-182130.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + switch \cr_pred5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -371447,17 +374952,142 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180093.3-180119.6" - process $proc$libresoc.v:180093$11463 + attribute \src "libresoc.v:182159.3-182198.6" + process $proc$libresoc.v:182159$11598 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 + attribute \src "libresoc.v:182160.5-182160.29" + switch \initial + attribute \src "libresoc.v:182160.9-182160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11600 $5\r25__data_o$next[3:0]$11604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11601 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11601 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11602 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11602 $2\r25__data_o$next[3:0]$11601 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11603 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11603 $3\r25__data_o$next[3:0]$11602 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11604 \reg + case + assign $5\r25__data_o$next[3:0]$11604 $4\r25__data_o$next[3:0]$11603 + end + case + assign $1\r25__data_o$next[3:0]$11600 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11605 4'0000 + case + assign $6\r25__data_o$next[3:0]$11605 $1\r25__data_o$next[3:0]$11600 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 + end + attribute \src "libresoc.v:182199.3-182228.6" + process $proc$libresoc.v:182199$11606 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 + attribute \src "libresoc.v:182200.5-182200.29" + switch \initial + attribute \src "libresoc.v:182200.9-182200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11608 $4\wr_detect$16[0:0]$11611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11609 1'1 + case + assign $2\wr_detect$16[0:0]$11609 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11610 1'1 + case + assign $3\wr_detect$16[0:0]$11610 $2\wr_detect$16[0:0]$11609 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11611 1'1 + case + assign $4\wr_detect$16[0:0]$11611 $3\wr_detect$16[0:0]$11610 + end + case + assign $1\wr_detect$16[0:0]$11608 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11607 + end + attribute \src "libresoc.v:182229.3-182255.6" + process $proc$libresoc.v:182229$11612 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11464 $4\reg$next[3:0]$11468 - attribute \src "libresoc.v:180094.5-180094.29" + assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 + attribute \src "libresoc.v:182230.5-182230.29" switch \initial - attribute \src "libresoc.v:180094.9-180094.17" + attribute \src "libresoc.v:182230.9-182230.17" case 1'1 case end @@ -371466,779 +375096,818 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11465 \dest15__data_i + assign $1\reg$next[3:0]$11614 \dest15__data_i case - assign $1\reg$next[3:0]$11465 \reg + assign $1\reg$next[3:0]$11614 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11466 \dest25__data_i + assign $2\reg$next[3:0]$11615 \dest25__data_i case - assign $2\reg$next[3:0]$11466 $1\reg$next[3:0]$11465 + assign $2\reg$next[3:0]$11615 $1\reg$next[3:0]$11614 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11467 \w5__data_i + assign $3\reg$next[3:0]$11616 \w5__data_i case - assign $3\reg$next[3:0]$11467 $2\reg$next[3:0]$11466 + assign $3\reg$next[3:0]$11616 $2\reg$next[3:0]$11615 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11468 4'0000 + assign $4\reg$next[3:0]$11617 4'0000 case - assign $4\reg$next[3:0]$11468 $3\reg$next[3:0]$11467 + assign $4\reg$next[3:0]$11617 $3\reg$next[3:0]$11616 end sync always - update \reg$next $0\reg$next[3:0]$11464 + update \reg$next $0\reg$next[3:0]$11613 end - attribute \src "libresoc.v:180120.3-180159.6" - process $proc$libresoc.v:180120$11469 + attribute \src "libresoc.v:182256.3-182295.6" + process $proc$libresoc.v:182256$11618 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11470 $6\src25__data_o$next[3:0]$11476 - attribute \src "libresoc.v:180121.5-180121.29" + assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 + attribute \src "libresoc.v:182257.5-182257.29" switch \initial - attribute \src "libresoc.v:180121.9-180121.17" + attribute \src "libresoc.v:182257.9-182257.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11471 $5\src25__data_o$next[3:0]$11475 + assign $1\src15__data_o$next[3:0]$11620 $5\src15__data_o$next[3:0]$11624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11472 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11621 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11472 4'0000 + assign $2\src15__data_o$next[3:0]$11621 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11473 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11622 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11473 $2\src25__data_o$next[3:0]$11472 + assign $3\src15__data_o$next[3:0]$11622 $2\src15__data_o$next[3:0]$11621 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11474 \w5__data_i + assign $4\src15__data_o$next[3:0]$11623 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11474 $3\src25__data_o$next[3:0]$11473 + assign $4\src15__data_o$next[3:0]$11623 $3\src15__data_o$next[3:0]$11622 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11475 \reg + assign $5\src15__data_o$next[3:0]$11624 \reg case - assign $5\src25__data_o$next[3:0]$11475 $4\src25__data_o$next[3:0]$11474 + assign $5\src15__data_o$next[3:0]$11624 $4\src15__data_o$next[3:0]$11623 end case - assign $1\src25__data_o$next[3:0]$11471 4'0000 + assign $1\src15__data_o$next[3:0]$11620 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11476 4'0000 + assign $6\src15__data_o$next[3:0]$11625 4'0000 case - assign $6\src25__data_o$next[3:0]$11476 $1\src25__data_o$next[3:0]$11471 + assign $6\src15__data_o$next[3:0]$11625 $1\src15__data_o$next[3:0]$11620 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11470 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 end - attribute \src "libresoc.v:180160.3-180189.6" - process $proc$libresoc.v:180160$11477 + attribute \src "libresoc.v:182296.3-182325.6" + process $proc$libresoc.v:182296$11626 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11478 $1\wr_detect$4[0:0]$11479 - attribute \src "libresoc.v:180161.5-180161.29" + assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:182297.5-182297.29" switch \initial - attribute \src "libresoc.v:180161.9-180161.17" + attribute \src "libresoc.v:182297.9-182297.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11479 $4\wr_detect$4[0:0]$11482 + assign $1\wr_detect$4[0:0]$11628 $4\wr_detect$4[0:0]$11631 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11480 1'1 + assign $2\wr_detect$4[0:0]$11629 1'1 case - assign $2\wr_detect$4[0:0]$11480 1'0 + assign $2\wr_detect$4[0:0]$11629 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11481 1'1 + assign $3\wr_detect$4[0:0]$11630 1'1 case - assign $3\wr_detect$4[0:0]$11481 $2\wr_detect$4[0:0]$11480 + assign $3\wr_detect$4[0:0]$11630 $2\wr_detect$4[0:0]$11629 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11482 1'1 + assign $4\wr_detect$4[0:0]$11631 1'1 case - assign $4\wr_detect$4[0:0]$11482 $3\wr_detect$4[0:0]$11481 + assign $4\wr_detect$4[0:0]$11631 $3\wr_detect$4[0:0]$11630 end case - assign $1\wr_detect$4[0:0]$11479 1'0 + assign $1\wr_detect$4[0:0]$11628 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11478 + update \wr_detect$4 $0\wr_detect$4[0:0]$11627 end - attribute \src "libresoc.v:180190.3-180229.6" - process $proc$libresoc.v:180190$11483 + attribute \src "libresoc.v:182326.3-182365.6" + process $proc$libresoc.v:182326$11632 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11484 $6\src35__data_o$next[3:0]$11490 - attribute \src "libresoc.v:180191.5-180191.29" + assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 + attribute \src "libresoc.v:182327.5-182327.29" switch \initial - attribute \src "libresoc.v:180191.9-180191.17" + attribute \src "libresoc.v:182327.9-182327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11485 $5\src35__data_o$next[3:0]$11489 + assign $1\src25__data_o$next[3:0]$11634 $5\src25__data_o$next[3:0]$11638 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11486 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11635 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11486 4'0000 + assign $2\src25__data_o$next[3:0]$11635 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11487 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11636 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11487 $2\src35__data_o$next[3:0]$11486 + assign $3\src25__data_o$next[3:0]$11636 $2\src25__data_o$next[3:0]$11635 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11488 \w5__data_i + assign $4\src25__data_o$next[3:0]$11637 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11488 $3\src35__data_o$next[3:0]$11487 + assign $4\src25__data_o$next[3:0]$11637 $3\src25__data_o$next[3:0]$11636 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11489 \reg + assign $5\src25__data_o$next[3:0]$11638 \reg case - assign $5\src35__data_o$next[3:0]$11489 $4\src35__data_o$next[3:0]$11488 + assign $5\src25__data_o$next[3:0]$11638 $4\src25__data_o$next[3:0]$11637 end case - assign $1\src35__data_o$next[3:0]$11485 4'0000 + assign $1\src25__data_o$next[3:0]$11634 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11490 4'0000 + assign $6\src25__data_o$next[3:0]$11639 4'0000 case - assign $6\src35__data_o$next[3:0]$11490 $1\src35__data_o$next[3:0]$11485 + assign $6\src25__data_o$next[3:0]$11639 $1\src25__data_o$next[3:0]$11634 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11484 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 end - attribute \src "libresoc.v:180230.3-180259.6" - process $proc$libresoc.v:180230$11491 + attribute \src "libresoc.v:182366.3-182395.6" + process $proc$libresoc.v:182366$11640 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11492 $1\wr_detect$7[0:0]$11493 - attribute \src "libresoc.v:180231.5-180231.29" + assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:182367.5-182367.29" switch \initial - attribute \src "libresoc.v:180231.9-180231.17" + attribute \src "libresoc.v:182367.9-182367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11493 $4\wr_detect$7[0:0]$11496 + assign $1\wr_detect$7[0:0]$11642 $4\wr_detect$7[0:0]$11645 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11494 1'1 + assign $2\wr_detect$7[0:0]$11643 1'1 case - assign $2\wr_detect$7[0:0]$11494 1'0 + assign $2\wr_detect$7[0:0]$11643 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11495 1'1 + assign $3\wr_detect$7[0:0]$11644 1'1 case - assign $3\wr_detect$7[0:0]$11495 $2\wr_detect$7[0:0]$11494 + assign $3\wr_detect$7[0:0]$11644 $2\wr_detect$7[0:0]$11643 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11496 1'1 + assign $4\wr_detect$7[0:0]$11645 1'1 case - assign $4\wr_detect$7[0:0]$11496 $3\wr_detect$7[0:0]$11495 + assign $4\wr_detect$7[0:0]$11645 $3\wr_detect$7[0:0]$11644 end case - assign $1\wr_detect$7[0:0]$11493 1'0 + assign $1\wr_detect$7[0:0]$11642 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11492 + update \wr_detect$7 $0\wr_detect$7[0:0]$11641 end - attribute \src "libresoc.v:180260.3-180299.6" - process $proc$libresoc.v:180260$11497 + attribute \src "libresoc.v:182396.3-182435.6" + process $proc$libresoc.v:182396$11646 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11498 $6\r5__data_o$next[3:0]$11504 - attribute \src "libresoc.v:180261.5-180261.29" + assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 + attribute \src "libresoc.v:182397.5-182397.29" switch \initial - attribute \src "libresoc.v:180261.9-180261.17" + attribute \src "libresoc.v:182397.9-182397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11499 $5\r5__data_o$next[3:0]$11503 + assign $1\src35__data_o$next[3:0]$11648 $5\src35__data_o$next[3:0]$11652 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11500 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11649 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11500 4'0000 + assign $2\src35__data_o$next[3:0]$11649 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11501 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11650 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11501 $2\r5__data_o$next[3:0]$11500 + assign $3\src35__data_o$next[3:0]$11650 $2\src35__data_o$next[3:0]$11649 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11502 \w5__data_i + assign $4\src35__data_o$next[3:0]$11651 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11502 $3\r5__data_o$next[3:0]$11501 + assign $4\src35__data_o$next[3:0]$11651 $3\src35__data_o$next[3:0]$11650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11503 \reg + assign $5\src35__data_o$next[3:0]$11652 \reg case - assign $5\r5__data_o$next[3:0]$11503 $4\r5__data_o$next[3:0]$11502 + assign $5\src35__data_o$next[3:0]$11652 $4\src35__data_o$next[3:0]$11651 end case - assign $1\r5__data_o$next[3:0]$11499 4'0000 + assign $1\src35__data_o$next[3:0]$11648 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11504 4'0000 + assign $6\src35__data_o$next[3:0]$11653 4'0000 case - assign $6\r5__data_o$next[3:0]$11504 $1\r5__data_o$next[3:0]$11499 + assign $6\src35__data_o$next[3:0]$11653 $1\src35__data_o$next[3:0]$11648 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11498 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 end - attribute \src "libresoc.v:180300.3-180329.6" - process $proc$libresoc.v:180300$11505 + attribute \src "libresoc.v:182436.3-182465.6" + process $proc$libresoc.v:182436$11654 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11506 $1\wr_detect$10[0:0]$11507 - attribute \src "libresoc.v:180301.5-180301.29" + assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:182437.5-182437.29" switch \initial - attribute \src "libresoc.v:180301.9-180301.17" + attribute \src "libresoc.v:182437.9-182437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11507 $4\wr_detect$10[0:0]$11510 + assign $1\wr_detect$10[0:0]$11656 $4\wr_detect$10[0:0]$11659 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11508 1'1 + assign $2\wr_detect$10[0:0]$11657 1'1 case - assign $2\wr_detect$10[0:0]$11508 1'0 + assign $2\wr_detect$10[0:0]$11657 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11509 1'1 + assign $3\wr_detect$10[0:0]$11658 1'1 case - assign $3\wr_detect$10[0:0]$11509 $2\wr_detect$10[0:0]$11508 + assign $3\wr_detect$10[0:0]$11658 $2\wr_detect$10[0:0]$11657 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11510 1'1 + assign $4\wr_detect$10[0:0]$11659 1'1 case - assign $4\wr_detect$10[0:0]$11510 $3\wr_detect$10[0:0]$11509 + assign $4\wr_detect$10[0:0]$11659 $3\wr_detect$10[0:0]$11658 end case - assign $1\wr_detect$10[0:0]$11507 1'0 + assign $1\wr_detect$10[0:0]$11656 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11506 + update \wr_detect$10 $0\wr_detect$10[0:0]$11655 end - attribute \src "libresoc.v:180330.3-180369.6" - process $proc$libresoc.v:180330$11511 + attribute \src "libresoc.v:182466.3-182505.6" + process $proc$libresoc.v:182466$11660 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11512 $6\r25__data_o$next[3:0]$11518 - attribute \src "libresoc.v:180331.5-180331.29" + assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 + attribute \src "libresoc.v:182467.5-182467.29" switch \initial - attribute \src "libresoc.v:180331.9-180331.17" + attribute \src "libresoc.v:182467.9-182467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11513 $5\r25__data_o$next[3:0]$11517 + assign $1\r5__data_o$next[3:0]$11662 $5\r5__data_o$next[3:0]$11666 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11514 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11663 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11514 4'0000 + assign $2\r5__data_o$next[3:0]$11663 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11515 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11664 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11515 $2\r25__data_o$next[3:0]$11514 + assign $3\r5__data_o$next[3:0]$11664 $2\r5__data_o$next[3:0]$11663 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11516 \w5__data_i + assign $4\r5__data_o$next[3:0]$11665 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11516 $3\r25__data_o$next[3:0]$11515 + assign $4\r5__data_o$next[3:0]$11665 $3\r5__data_o$next[3:0]$11664 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11517 \reg + assign $5\r5__data_o$next[3:0]$11666 \reg case - assign $5\r25__data_o$next[3:0]$11517 $4\r25__data_o$next[3:0]$11516 + assign $5\r5__data_o$next[3:0]$11666 $4\r5__data_o$next[3:0]$11665 end case - assign $1\r25__data_o$next[3:0]$11513 4'0000 + assign $1\r5__data_o$next[3:0]$11662 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11518 4'0000 + assign $6\r5__data_o$next[3:0]$11667 4'0000 case - assign $6\r25__data_o$next[3:0]$11518 $1\r25__data_o$next[3:0]$11513 + assign $6\r5__data_o$next[3:0]$11667 $1\r5__data_o$next[3:0]$11662 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11512 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 end - attribute \src "libresoc.v:180370.3-180399.6" - process $proc$libresoc.v:180370$11519 + attribute \src "libresoc.v:182506.3-182535.6" + process $proc$libresoc.v:182506$11668 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11520 $1\wr_detect$13[0:0]$11521 - attribute \src "libresoc.v:180371.5-180371.29" + assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:182507.5-182507.29" switch \initial - attribute \src "libresoc.v:180371.9-180371.17" + attribute \src "libresoc.v:182507.9-182507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11521 $4\wr_detect$13[0:0]$11524 + assign $1\wr_detect$13[0:0]$11670 $4\wr_detect$13[0:0]$11673 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11522 1'1 + assign $2\wr_detect$13[0:0]$11671 1'1 case - assign $2\wr_detect$13[0:0]$11522 1'0 + assign $2\wr_detect$13[0:0]$11671 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11523 1'1 + assign $3\wr_detect$13[0:0]$11672 1'1 case - assign $3\wr_detect$13[0:0]$11523 $2\wr_detect$13[0:0]$11522 + assign $3\wr_detect$13[0:0]$11672 $2\wr_detect$13[0:0]$11671 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11524 1'1 + assign $4\wr_detect$13[0:0]$11673 1'1 case - assign $4\wr_detect$13[0:0]$11524 $3\wr_detect$13[0:0]$11523 + assign $4\wr_detect$13[0:0]$11673 $3\wr_detect$13[0:0]$11672 end case - assign $1\wr_detect$13[0:0]$11521 1'0 + assign $1\wr_detect$13[0:0]$11670 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11520 + update \wr_detect$13 $0\wr_detect$13[0:0]$11669 end - connect \$9 $not$libresoc.v:180006$11443_Y - connect \$12 $not$libresoc.v:180007$11444_Y - connect \$1 $not$libresoc.v:180008$11445_Y - connect \$3 $not$libresoc.v:180009$11446_Y - connect \$6 $not$libresoc.v:180010$11447_Y + connect \$9 $not$libresoc.v:182069$11576_Y + connect \$12 $not$libresoc.v:182070$11577_Y + connect \$15 $not$libresoc.v:182071$11578_Y + connect \$1 $not$libresoc.v:182072$11579_Y + connect \$3 $not$libresoc.v:182073$11580_Y + connect \$6 $not$libresoc.v:182074$11581_Y end -attribute \src "libresoc.v:180404.1-180875.10" +attribute \src "libresoc.v:182540.1-183095.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:180405.7-180405.20" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 + attribute \src "libresoc.v:182646.3-182647.49" + wire width 4 $0\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182541.7-182541.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $0\r26__data_o$next[3:0]$11601 - attribute \src "libresoc.v:180488.3-180489.39" + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $0\r26__data_o$next[3:0]$11705 + attribute \src "libresoc.v:182636.3-182637.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $0\r6__data_o$next[3:0]$11587 - attribute \src "libresoc.v:180490.3-180491.37" + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $0\r6__data_o$next[3:0]$11767 + attribute \src "libresoc.v:182638.3-182639.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $0\reg$next[3:0]$11553 - attribute \src "libresoc.v:180486.3-180487.25" + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $0\reg$next[3:0]$11719 + attribute \src "libresoc.v:182634.3-182635.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $0\src16__data_o$next[3:0]$11544 - attribute \src "libresoc.v:180496.3-180497.43" + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $0\src16__data_o$next[3:0]$11725 + attribute \src "libresoc.v:182644.3-182645.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $0\src26__data_o$next[3:0]$11559 - attribute \src "libresoc.v:180494.3-180495.43" + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $0\src26__data_o$next[3:0]$11739 + attribute \src "libresoc.v:182642.3-182643.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $0\src36__data_o$next[3:0]$11573 - attribute \src "libresoc.v:180492.3-180493.43" + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $0\src36__data_o$next[3:0]$11753 + attribute \src "libresoc.v:182640.3-182641.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:180775.3-180804.6" - wire $0\wr_detect$10[0:0]$11595 - attribute \src "libresoc.v:180845.3-180874.6" - wire $0\wr_detect$13[0:0]$11609 - attribute \src "libresoc.v:180635.3-180664.6" - wire $0\wr_detect$4[0:0]$11567 - attribute \src "libresoc.v:180705.3-180734.6" - wire $0\wr_detect$7[0:0]$11581 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182995.3-183024.6" + wire $0\wr_detect$10[0:0]$11761 + attribute \src "libresoc.v:183065.3-183094.6" + wire $0\wr_detect$13[0:0]$11775 + attribute \src "libresoc.v:182758.3-182787.6" + wire $0\wr_detect$16[0:0]$11713 + attribute \src "libresoc.v:182855.3-182884.6" + wire $0\wr_detect$4[0:0]$11733 + attribute \src "libresoc.v:182925.3-182954.6" + wire $0\wr_detect$7[0:0]$11747 + attribute \src "libresoc.v:182688.3-182717.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $1\r26__data_o$next[3:0]$11602 - attribute \src "libresoc.v:180430.13-180430.31" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 + attribute \src "libresoc.v:182560.13-182560.36" + wire width 4 $1\cr_pred6__data_o[3:0] + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $1\r26__data_o$next[3:0]$11706 + attribute \src "libresoc.v:182575.13-182575.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $1\r6__data_o$next[3:0]$11588 - attribute \src "libresoc.v:180437.13-180437.30" + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $1\r6__data_o$next[3:0]$11768 + attribute \src "libresoc.v:182582.13-182582.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $1\reg$next[3:0]$11554 - attribute \src "libresoc.v:180443.13-180443.25" + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $1\reg$next[3:0]$11720 + attribute \src "libresoc.v:182588.13-182588.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $1\src16__data_o$next[3:0]$11545 - attribute \src "libresoc.v:180448.13-180448.33" + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $1\src16__data_o$next[3:0]$11726 + attribute \src "libresoc.v:182593.13-182593.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $1\src26__data_o$next[3:0]$11560 - attribute \src "libresoc.v:180455.13-180455.33" + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $1\src26__data_o$next[3:0]$11740 + attribute \src "libresoc.v:182600.13-182600.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $1\src36__data_o$next[3:0]$11574 - attribute \src "libresoc.v:180462.13-180462.33" + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $1\src36__data_o$next[3:0]$11754 + attribute \src "libresoc.v:182607.13-182607.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:180775.3-180804.6" - wire $1\wr_detect$10[0:0]$11596 - attribute \src "libresoc.v:180845.3-180874.6" - wire $1\wr_detect$13[0:0]$11610 - attribute \src "libresoc.v:180635.3-180664.6" - wire $1\wr_detect$4[0:0]$11568 - attribute \src "libresoc.v:180705.3-180734.6" - wire $1\wr_detect$7[0:0]$11582 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182995.3-183024.6" + wire $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:183065.3-183094.6" + wire $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:182758.3-182787.6" + wire $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182855.3-182884.6" + wire $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182925.3-182954.6" + wire $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182688.3-182717.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $2\r26__data_o$next[3:0]$11603 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $2\r6__data_o$next[3:0]$11589 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $2\reg$next[3:0]$11555 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $2\src16__data_o$next[3:0]$11546 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $2\src26__data_o$next[3:0]$11561 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $2\src36__data_o$next[3:0]$11575 - attribute \src "libresoc.v:180775.3-180804.6" - wire $2\wr_detect$10[0:0]$11597 - attribute \src "libresoc.v:180845.3-180874.6" - wire $2\wr_detect$13[0:0]$11611 - attribute \src "libresoc.v:180635.3-180664.6" - wire $2\wr_detect$4[0:0]$11569 - attribute \src "libresoc.v:180705.3-180734.6" - wire $2\wr_detect$7[0:0]$11583 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $2\r26__data_o$next[3:0]$11707 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $2\r6__data_o$next[3:0]$11769 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $2\reg$next[3:0]$11721 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $2\src16__data_o$next[3:0]$11727 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $2\src26__data_o$next[3:0]$11741 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $2\src36__data_o$next[3:0]$11755 + attribute \src "libresoc.v:182995.3-183024.6" + wire $2\wr_detect$10[0:0]$11763 + attribute \src "libresoc.v:183065.3-183094.6" + wire $2\wr_detect$13[0:0]$11777 + attribute \src "libresoc.v:182758.3-182787.6" + wire $2\wr_detect$16[0:0]$11715 + attribute \src "libresoc.v:182855.3-182884.6" + wire $2\wr_detect$4[0:0]$11735 + attribute \src "libresoc.v:182925.3-182954.6" + wire $2\wr_detect$7[0:0]$11749 + attribute \src "libresoc.v:182688.3-182717.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $3\r26__data_o$next[3:0]$11604 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $3\r6__data_o$next[3:0]$11590 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $3\reg$next[3:0]$11556 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $3\src16__data_o$next[3:0]$11547 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $3\src26__data_o$next[3:0]$11562 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $3\src36__data_o$next[3:0]$11576 - attribute \src "libresoc.v:180775.3-180804.6" - wire $3\wr_detect$10[0:0]$11598 - attribute \src "libresoc.v:180845.3-180874.6" - wire $3\wr_detect$13[0:0]$11612 - attribute \src "libresoc.v:180635.3-180664.6" - wire $3\wr_detect$4[0:0]$11570 - attribute \src "libresoc.v:180705.3-180734.6" - wire $3\wr_detect$7[0:0]$11584 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $3\r26__data_o$next[3:0]$11708 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $3\r6__data_o$next[3:0]$11770 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $3\reg$next[3:0]$11722 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $3\src16__data_o$next[3:0]$11728 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $3\src26__data_o$next[3:0]$11742 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $3\src36__data_o$next[3:0]$11756 + attribute \src "libresoc.v:182995.3-183024.6" + wire $3\wr_detect$10[0:0]$11764 + attribute \src "libresoc.v:183065.3-183094.6" + wire $3\wr_detect$13[0:0]$11778 + attribute \src "libresoc.v:182758.3-182787.6" + wire $3\wr_detect$16[0:0]$11716 + attribute \src "libresoc.v:182855.3-182884.6" + wire $3\wr_detect$4[0:0]$11736 + attribute \src "libresoc.v:182925.3-182954.6" + wire $3\wr_detect$7[0:0]$11750 + attribute \src "libresoc.v:182688.3-182717.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $4\r26__data_o$next[3:0]$11605 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $4\r6__data_o$next[3:0]$11591 - attribute \src "libresoc.v:180568.3-180594.6" - wire width 4 $4\reg$next[3:0]$11557 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $4\src16__data_o$next[3:0]$11548 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $4\src26__data_o$next[3:0]$11563 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $4\src36__data_o$next[3:0]$11577 - attribute \src "libresoc.v:180775.3-180804.6" - wire $4\wr_detect$10[0:0]$11599 - attribute \src "libresoc.v:180845.3-180874.6" - wire $4\wr_detect$13[0:0]$11613 - attribute \src "libresoc.v:180635.3-180664.6" - wire $4\wr_detect$4[0:0]$11571 - attribute \src "libresoc.v:180705.3-180734.6" - wire $4\wr_detect$7[0:0]$11585 - attribute \src "libresoc.v:180538.3-180567.6" + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $4\r26__data_o$next[3:0]$11709 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $4\r6__data_o$next[3:0]$11771 + attribute \src "libresoc.v:182788.3-182814.6" + wire width 4 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $4\src16__data_o$next[3:0]$11729 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $4\src26__data_o$next[3:0]$11743 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $4\src36__data_o$next[3:0]$11757 + attribute \src "libresoc.v:182995.3-183024.6" + wire $4\wr_detect$10[0:0]$11765 + attribute \src "libresoc.v:183065.3-183094.6" + wire $4\wr_detect$13[0:0]$11779 + attribute \src "libresoc.v:182758.3-182787.6" + wire $4\wr_detect$16[0:0]$11717 + attribute \src "libresoc.v:182855.3-182884.6" + wire $4\wr_detect$4[0:0]$11737 + attribute \src "libresoc.v:182925.3-182954.6" + wire $4\wr_detect$7[0:0]$11751 + attribute \src "libresoc.v:182688.3-182717.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $5\r26__data_o$next[3:0]$11606 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $5\r6__data_o$next[3:0]$11592 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $5\src16__data_o$next[3:0]$11549 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $5\src26__data_o$next[3:0]$11564 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $5\src36__data_o$next[3:0]$11578 - attribute \src "libresoc.v:180805.3-180844.6" - wire width 4 $6\r26__data_o$next[3:0]$11607 - attribute \src "libresoc.v:180735.3-180774.6" - wire width 4 $6\r6__data_o$next[3:0]$11593 - attribute \src "libresoc.v:180498.3-180537.6" - wire width 4 $6\src16__data_o$next[3:0]$11550 - attribute \src "libresoc.v:180595.3-180634.6" - wire width 4 $6\src26__data_o$next[3:0]$11565 - attribute \src "libresoc.v:180665.3-180704.6" - wire width 4 $6\src36__data_o$next[3:0]$11579 - attribute \src "libresoc.v:180481.17-180481.104" - wire $not$libresoc.v:180481$11532_Y - attribute \src "libresoc.v:180482.18-180482.105" - wire $not$libresoc.v:180482$11533_Y - attribute \src "libresoc.v:180483.17-180483.100" - wire $not$libresoc.v:180483$11534_Y - attribute \src "libresoc.v:180484.17-180484.103" - wire $not$libresoc.v:180484$11535_Y - attribute \src "libresoc.v:180485.17-180485.103" - wire $not$libresoc.v:180485$11536_Y + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $5\r26__data_o$next[3:0]$11710 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $5\r6__data_o$next[3:0]$11772 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $5\src16__data_o$next[3:0]$11730 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $5\src26__data_o$next[3:0]$11744 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $5\src36__data_o$next[3:0]$11758 + attribute \src "libresoc.v:182648.3-182687.6" + wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182718.3-182757.6" + wire width 4 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:183025.3-183064.6" + wire width 4 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:182815.3-182854.6" + wire width 4 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182885.3-182924.6" + wire width 4 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182955.3-182994.6" + wire width 4 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182628.17-182628.104" + wire $not$libresoc.v:182628$11682_Y + attribute \src "libresoc.v:182629.18-182629.105" + wire $not$libresoc.v:182629$11683_Y + attribute \src "libresoc.v:182630.18-182630.105" + wire $not$libresoc.v:182630$11684_Y + attribute \src "libresoc.v:182631.17-182631.100" + wire $not$libresoc.v:182631$11685_Y + attribute \src "libresoc.v:182632.17-182632.103" + wire $not$libresoc.v:182632$11686_Y + attribute \src "libresoc.v:182633.17-182633.103" + wire $not$libresoc.v:182633$11687_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest16__data_i + wire width 4 output 3 \cr_pred6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest16__wen + wire width 4 \cr_pred6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest26__data_i + wire input 2 \cr_pred6__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest26__wen - attribute \src "libresoc.v:180405.7-180405.15" + wire width 4 input 11 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest26__wen + attribute \src "libresoc.v:182541.7-182541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r26__data_o + wire width 4 output 16 \r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r26__ren + wire input 17 \r26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r6__data_o + wire width 4 output 14 \r6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r6__ren + wire input 15 \r6__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src16__data_o + wire width 4 output 5 \src16__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src16__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src16__ren + wire input 4 \src16__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src26__data_o + wire width 4 output 7 \src26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src26__ren + wire input 6 \src26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src36__data_o + wire width 4 output 9 \src36__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src36__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src36__ren + wire input 8 \src36__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w6__data_i + wire width 4 input 18 \w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w6__wen + wire input 19 \w6__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -372246,232 +375915,257 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180481$11532 + cell $not $not$libresoc.v:182628$11682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180481$11532_Y + connect \Y $not$libresoc.v:182628$11682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180482$11533 + cell $not $not$libresoc.v:182629$11683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180482$11533_Y + connect \Y $not$libresoc.v:182629$11683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180483$11534 + cell $not $not$libresoc.v:182630$11684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:182630$11684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182631$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180483$11534_Y + connect \Y $not$libresoc.v:182631$11685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180484$11535 + cell $not $not$libresoc.v:182632$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180484$11535_Y + connect \Y $not$libresoc.v:182632$11686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180485$11536 + cell $not $not$libresoc.v:182633$11687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180485$11536_Y + connect \Y $not$libresoc.v:182633$11687_Y end - attribute \src "libresoc.v:180405.7-180405.20" - process $proc$libresoc.v:180405$11614 + attribute \src "libresoc.v:182541.7-182541.20" + process $proc$libresoc.v:182541$11780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180430.13-180430.31" - process $proc$libresoc.v:180430$11615 + attribute \src "libresoc.v:182560.13-182560.36" + process $proc$libresoc.v:182560$11781 + assign { } { } + assign $1\cr_pred6__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182575.13-182575.31" + process $proc$libresoc.v:182575$11782 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:180437.13-180437.30" - process $proc$libresoc.v:180437$11616 + attribute \src "libresoc.v:182582.13-182582.30" + process $proc$libresoc.v:182582$11783 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:180443.13-180443.25" - process $proc$libresoc.v:180443$11617 + attribute \src "libresoc.v:182588.13-182588.25" + process $proc$libresoc.v:182588$11784 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180448.13-180448.33" - process $proc$libresoc.v:180448$11618 + attribute \src "libresoc.v:182593.13-182593.33" + process $proc$libresoc.v:182593$11785 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:180455.13-180455.33" - process $proc$libresoc.v:180455$11619 + attribute \src "libresoc.v:182600.13-182600.33" + process $proc$libresoc.v:182600$11786 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:180462.13-180462.33" - process $proc$libresoc.v:180462$11620 + attribute \src "libresoc.v:182607.13-182607.33" + process $proc$libresoc.v:182607$11787 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:180486.3-180487.25" - process $proc$libresoc.v:180486$11537 + attribute \src "libresoc.v:182634.3-182635.25" + process $proc$libresoc.v:182634$11688 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180488.3-180489.39" - process $proc$libresoc.v:180488$11538 + attribute \src "libresoc.v:182636.3-182637.39" + process $proc$libresoc.v:182636$11689 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:180490.3-180491.37" - process $proc$libresoc.v:180490$11539 + attribute \src "libresoc.v:182638.3-182639.37" + process $proc$libresoc.v:182638$11690 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:180492.3-180493.43" - process $proc$libresoc.v:180492$11540 + attribute \src "libresoc.v:182640.3-182641.43" + process $proc$libresoc.v:182640$11691 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:180494.3-180495.43" - process $proc$libresoc.v:180494$11541 + attribute \src "libresoc.v:182642.3-182643.43" + process $proc$libresoc.v:182642$11692 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:180496.3-180497.43" - process $proc$libresoc.v:180496$11542 + attribute \src "libresoc.v:182644.3-182645.43" + process $proc$libresoc.v:182644$11693 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:180498.3-180537.6" - process $proc$libresoc.v:180498$11543 + attribute \src "libresoc.v:182646.3-182647.49" + process $proc$libresoc.v:182646$11694 + assign { } { } + assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next + sync posedge \coresync_clk + update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] + end + attribute \src "libresoc.v:182648.3-182687.6" + process $proc$libresoc.v:182648$11695 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11544 $6\src16__data_o$next[3:0]$11550 - attribute \src "libresoc.v:180499.5-180499.29" + assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 + attribute \src "libresoc.v:182649.5-182649.29" switch \initial - attribute \src "libresoc.v:180499.9-180499.17" + attribute \src "libresoc.v:182649.9-182649.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + switch \cr_pred6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11545 $5\src16__data_o$next[3:0]$11549 + assign $1\cr_pred6__data_o$next[3:0]$11697 $5\cr_pred6__data_o$next[3:0]$11701 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11546 \dest16__data_i + assign $2\cr_pred6__data_o$next[3:0]$11698 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11546 4'0000 + assign $2\cr_pred6__data_o$next[3:0]$11698 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11547 \dest26__data_i + assign $3\cr_pred6__data_o$next[3:0]$11699 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11547 $2\src16__data_o$next[3:0]$11546 + assign $3\cr_pred6__data_o$next[3:0]$11699 $2\cr_pred6__data_o$next[3:0]$11698 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11548 \w6__data_i + assign $4\cr_pred6__data_o$next[3:0]$11700 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11548 $3\src16__data_o$next[3:0]$11547 + assign $4\cr_pred6__data_o$next[3:0]$11700 $3\cr_pred6__data_o$next[3:0]$11699 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11549 \reg + assign $5\cr_pred6__data_o$next[3:0]$11701 \reg case - assign $5\src16__data_o$next[3:0]$11549 $4\src16__data_o$next[3:0]$11548 + assign $5\cr_pred6__data_o$next[3:0]$11701 $4\cr_pred6__data_o$next[3:0]$11700 end case - assign $1\src16__data_o$next[3:0]$11545 4'0000 + assign $1\cr_pred6__data_o$next[3:0]$11697 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11550 4'0000 + assign $6\cr_pred6__data_o$next[3:0]$11702 4'0000 case - assign $6\src16__data_o$next[3:0]$11550 $1\src16__data_o$next[3:0]$11545 + assign $6\cr_pred6__data_o$next[3:0]$11702 $1\cr_pred6__data_o$next[3:0]$11697 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11544 + update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 end - attribute \src "libresoc.v:180538.3-180567.6" - process $proc$libresoc.v:180538$11551 + attribute \src "libresoc.v:182688.3-182717.6" + process $proc$libresoc.v:182688$11703 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180539.5-180539.29" + attribute \src "libresoc.v:182689.5-182689.29" switch \initial - attribute \src "libresoc.v:180539.9-180539.17" + attribute \src "libresoc.v:182689.9-182689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + switch \cr_pred6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -372512,798 +376206,962 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180568.3-180594.6" - process $proc$libresoc.v:180568$11552 - assign { } { } + attribute \src "libresoc.v:182718.3-182757.6" + process $proc$libresoc.v:182718$11704 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11553 $4\reg$next[3:0]$11557 - attribute \src "libresoc.v:180569.5-180569.29" + assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 + attribute \src "libresoc.v:182719.5-182719.29" switch \initial - attribute \src "libresoc.v:180569.9-180569.17" + attribute \src "libresoc.v:182719.9-182719.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest16__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11554 \dest16__data_i - case - assign $1\reg$next[3:0]$11554 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\reg$next[3:0]$11555 \dest26__data_i - case - assign $2\reg$next[3:0]$11555 $1\reg$next[3:0]$11554 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $3\reg$next[3:0]$11556 \w6__data_i + assign { } { } + assign $1\r26__data_o$next[3:0]$11706 $5\r26__data_o$next[3:0]$11710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11707 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11707 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11708 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11708 $2\r26__data_o$next[3:0]$11707 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11709 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11709 $3\r26__data_o$next[3:0]$11708 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11710 \reg + case + assign $5\r26__data_o$next[3:0]$11710 $4\r26__data_o$next[3:0]$11709 + end case - assign $3\reg$next[3:0]$11556 $2\reg$next[3:0]$11555 + assign $1\r26__data_o$next[3:0]$11706 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11557 4'0000 + assign $6\r26__data_o$next[3:0]$11711 4'0000 case - assign $4\reg$next[3:0]$11557 $3\reg$next[3:0]$11556 + assign $6\r26__data_o$next[3:0]$11711 $1\r26__data_o$next[3:0]$11706 end sync always - update \reg$next $0\reg$next[3:0]$11553 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 end - attribute \src "libresoc.v:180595.3-180634.6" - process $proc$libresoc.v:180595$11558 - assign { } { } + attribute \src "libresoc.v:182758.3-182787.6" + process $proc$libresoc.v:182758$11712 assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11559 $6\src26__data_o$next[3:0]$11565 - attribute \src "libresoc.v:180596.5-180596.29" + assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 + attribute \src "libresoc.v:182759.5-182759.29" switch \initial - attribute \src "libresoc.v:180596.9-180596.17" + attribute \src "libresoc.v:182759.9-182759.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11560 $5\src26__data_o$next[3:0]$11564 + assign $1\wr_detect$16[0:0]$11714 $4\wr_detect$16[0:0]$11717 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11561 \dest16__data_i + assign $2\wr_detect$16[0:0]$11715 1'1 case - assign $2\src26__data_o$next[3:0]$11561 4'0000 + assign $2\wr_detect$16[0:0]$11715 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11562 \dest26__data_i + assign $3\wr_detect$16[0:0]$11716 1'1 case - assign $3\src26__data_o$next[3:0]$11562 $2\src26__data_o$next[3:0]$11561 + assign $3\wr_detect$16[0:0]$11716 $2\wr_detect$16[0:0]$11715 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11563 \w6__data_i + assign $4\wr_detect$16[0:0]$11717 1'1 case - assign $4\src26__data_o$next[3:0]$11563 $3\src26__data_o$next[3:0]$11562 + assign $4\wr_detect$16[0:0]$11717 $3\wr_detect$16[0:0]$11716 + end + case + assign $1\wr_detect$16[0:0]$11714 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11713 + end + attribute \src "libresoc.v:182788.3-182814.6" + process $proc$libresoc.v:182788$11718 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 + attribute \src "libresoc.v:182789.5-182789.29" + switch \initial + attribute \src "libresoc.v:182789.9-182789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11720 \dest16__data_i + case + assign $1\reg$next[3:0]$11720 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11721 \dest26__data_i + case + assign $2\reg$next[3:0]$11721 $1\reg$next[3:0]$11720 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11722 \w6__data_i + case + assign $3\reg$next[3:0]$11722 $2\reg$next[3:0]$11721 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11723 4'0000 + case + assign $4\reg$next[3:0]$11723 $3\reg$next[3:0]$11722 + end + sync always + update \reg$next $0\reg$next[3:0]$11719 + end + attribute \src "libresoc.v:182815.3-182854.6" + process $proc$libresoc.v:182815$11724 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 + attribute \src "libresoc.v:182816.5-182816.29" + switch \initial + attribute \src "libresoc.v:182816.9-182816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11726 $5\src16__data_o$next[3:0]$11730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11727 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11727 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11728 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11728 $2\src16__data_o$next[3:0]$11727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11729 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11729 $3\src16__data_o$next[3:0]$11728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11564 \reg + assign $5\src16__data_o$next[3:0]$11730 \reg case - assign $5\src26__data_o$next[3:0]$11564 $4\src26__data_o$next[3:0]$11563 + assign $5\src16__data_o$next[3:0]$11730 $4\src16__data_o$next[3:0]$11729 end case - assign $1\src26__data_o$next[3:0]$11560 4'0000 + assign $1\src16__data_o$next[3:0]$11726 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11565 4'0000 + assign $6\src16__data_o$next[3:0]$11731 4'0000 case - assign $6\src26__data_o$next[3:0]$11565 $1\src26__data_o$next[3:0]$11560 + assign $6\src16__data_o$next[3:0]$11731 $1\src16__data_o$next[3:0]$11726 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11559 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 end - attribute \src "libresoc.v:180635.3-180664.6" - process $proc$libresoc.v:180635$11566 + attribute \src "libresoc.v:182855.3-182884.6" + process $proc$libresoc.v:182855$11732 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11567 $1\wr_detect$4[0:0]$11568 - attribute \src "libresoc.v:180636.5-180636.29" + assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 + attribute \src "libresoc.v:182856.5-182856.29" switch \initial - attribute \src "libresoc.v:180636.9-180636.17" + attribute \src "libresoc.v:182856.9-182856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11568 $4\wr_detect$4[0:0]$11571 + assign $1\wr_detect$4[0:0]$11734 $4\wr_detect$4[0:0]$11737 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11569 1'1 + assign $2\wr_detect$4[0:0]$11735 1'1 case - assign $2\wr_detect$4[0:0]$11569 1'0 + assign $2\wr_detect$4[0:0]$11735 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11570 1'1 + assign $3\wr_detect$4[0:0]$11736 1'1 case - assign $3\wr_detect$4[0:0]$11570 $2\wr_detect$4[0:0]$11569 + assign $3\wr_detect$4[0:0]$11736 $2\wr_detect$4[0:0]$11735 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11571 1'1 + assign $4\wr_detect$4[0:0]$11737 1'1 case - assign $4\wr_detect$4[0:0]$11571 $3\wr_detect$4[0:0]$11570 + assign $4\wr_detect$4[0:0]$11737 $3\wr_detect$4[0:0]$11736 end case - assign $1\wr_detect$4[0:0]$11568 1'0 + assign $1\wr_detect$4[0:0]$11734 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11567 + update \wr_detect$4 $0\wr_detect$4[0:0]$11733 end - attribute \src "libresoc.v:180665.3-180704.6" - process $proc$libresoc.v:180665$11572 + attribute \src "libresoc.v:182885.3-182924.6" + process $proc$libresoc.v:182885$11738 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11573 $6\src36__data_o$next[3:0]$11579 - attribute \src "libresoc.v:180666.5-180666.29" + assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 + attribute \src "libresoc.v:182886.5-182886.29" switch \initial - attribute \src "libresoc.v:180666.9-180666.17" + attribute \src "libresoc.v:182886.9-182886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11574 $5\src36__data_o$next[3:0]$11578 + assign $1\src26__data_o$next[3:0]$11740 $5\src26__data_o$next[3:0]$11744 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11575 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11741 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11575 4'0000 + assign $2\src26__data_o$next[3:0]$11741 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11576 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11742 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11576 $2\src36__data_o$next[3:0]$11575 + assign $3\src26__data_o$next[3:0]$11742 $2\src26__data_o$next[3:0]$11741 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11577 \w6__data_i + assign $4\src26__data_o$next[3:0]$11743 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11577 $3\src36__data_o$next[3:0]$11576 + assign $4\src26__data_o$next[3:0]$11743 $3\src26__data_o$next[3:0]$11742 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11578 \reg + assign $5\src26__data_o$next[3:0]$11744 \reg case - assign $5\src36__data_o$next[3:0]$11578 $4\src36__data_o$next[3:0]$11577 + assign $5\src26__data_o$next[3:0]$11744 $4\src26__data_o$next[3:0]$11743 end case - assign $1\src36__data_o$next[3:0]$11574 4'0000 + assign $1\src26__data_o$next[3:0]$11740 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11579 4'0000 + assign $6\src26__data_o$next[3:0]$11745 4'0000 case - assign $6\src36__data_o$next[3:0]$11579 $1\src36__data_o$next[3:0]$11574 + assign $6\src26__data_o$next[3:0]$11745 $1\src26__data_o$next[3:0]$11740 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11573 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 end - attribute \src "libresoc.v:180705.3-180734.6" - process $proc$libresoc.v:180705$11580 + attribute \src "libresoc.v:182925.3-182954.6" + process $proc$libresoc.v:182925$11746 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11581 $1\wr_detect$7[0:0]$11582 - attribute \src "libresoc.v:180706.5-180706.29" + assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 + attribute \src "libresoc.v:182926.5-182926.29" switch \initial - attribute \src "libresoc.v:180706.9-180706.17" + attribute \src "libresoc.v:182926.9-182926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11582 $4\wr_detect$7[0:0]$11585 + assign $1\wr_detect$7[0:0]$11748 $4\wr_detect$7[0:0]$11751 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11583 1'1 + assign $2\wr_detect$7[0:0]$11749 1'1 case - assign $2\wr_detect$7[0:0]$11583 1'0 + assign $2\wr_detect$7[0:0]$11749 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11584 1'1 + assign $3\wr_detect$7[0:0]$11750 1'1 case - assign $3\wr_detect$7[0:0]$11584 $2\wr_detect$7[0:0]$11583 + assign $3\wr_detect$7[0:0]$11750 $2\wr_detect$7[0:0]$11749 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11585 1'1 + assign $4\wr_detect$7[0:0]$11751 1'1 case - assign $4\wr_detect$7[0:0]$11585 $3\wr_detect$7[0:0]$11584 + assign $4\wr_detect$7[0:0]$11751 $3\wr_detect$7[0:0]$11750 end case - assign $1\wr_detect$7[0:0]$11582 1'0 + assign $1\wr_detect$7[0:0]$11748 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11581 + update \wr_detect$7 $0\wr_detect$7[0:0]$11747 end - attribute \src "libresoc.v:180735.3-180774.6" - process $proc$libresoc.v:180735$11586 + attribute \src "libresoc.v:182955.3-182994.6" + process $proc$libresoc.v:182955$11752 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11587 $6\r6__data_o$next[3:0]$11593 - attribute \src "libresoc.v:180736.5-180736.29" + assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 + attribute \src "libresoc.v:182956.5-182956.29" switch \initial - attribute \src "libresoc.v:180736.9-180736.17" + attribute \src "libresoc.v:182956.9-182956.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11588 $5\r6__data_o$next[3:0]$11592 + assign $1\src36__data_o$next[3:0]$11754 $5\src36__data_o$next[3:0]$11758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11589 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11755 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11589 4'0000 + assign $2\src36__data_o$next[3:0]$11755 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11590 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11756 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11590 $2\r6__data_o$next[3:0]$11589 + assign $3\src36__data_o$next[3:0]$11756 $2\src36__data_o$next[3:0]$11755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11591 \w6__data_i + assign $4\src36__data_o$next[3:0]$11757 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11591 $3\r6__data_o$next[3:0]$11590 + assign $4\src36__data_o$next[3:0]$11757 $3\src36__data_o$next[3:0]$11756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11592 \reg + assign $5\src36__data_o$next[3:0]$11758 \reg case - assign $5\r6__data_o$next[3:0]$11592 $4\r6__data_o$next[3:0]$11591 + assign $5\src36__data_o$next[3:0]$11758 $4\src36__data_o$next[3:0]$11757 end case - assign $1\r6__data_o$next[3:0]$11588 4'0000 + assign $1\src36__data_o$next[3:0]$11754 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11593 4'0000 + assign $6\src36__data_o$next[3:0]$11759 4'0000 case - assign $6\r6__data_o$next[3:0]$11593 $1\r6__data_o$next[3:0]$11588 + assign $6\src36__data_o$next[3:0]$11759 $1\src36__data_o$next[3:0]$11754 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11587 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 end - attribute \src "libresoc.v:180775.3-180804.6" - process $proc$libresoc.v:180775$11594 + attribute \src "libresoc.v:182995.3-183024.6" + process $proc$libresoc.v:182995$11760 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11595 $1\wr_detect$10[0:0]$11596 - attribute \src "libresoc.v:180776.5-180776.29" + assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 + attribute \src "libresoc.v:182996.5-182996.29" switch \initial - attribute \src "libresoc.v:180776.9-180776.17" + attribute \src "libresoc.v:182996.9-182996.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11596 $4\wr_detect$10[0:0]$11599 + assign $1\wr_detect$10[0:0]$11762 $4\wr_detect$10[0:0]$11765 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11597 1'1 + assign $2\wr_detect$10[0:0]$11763 1'1 case - assign $2\wr_detect$10[0:0]$11597 1'0 + assign $2\wr_detect$10[0:0]$11763 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11598 1'1 + assign $3\wr_detect$10[0:0]$11764 1'1 case - assign $3\wr_detect$10[0:0]$11598 $2\wr_detect$10[0:0]$11597 + assign $3\wr_detect$10[0:0]$11764 $2\wr_detect$10[0:0]$11763 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11599 1'1 + assign $4\wr_detect$10[0:0]$11765 1'1 case - assign $4\wr_detect$10[0:0]$11599 $3\wr_detect$10[0:0]$11598 + assign $4\wr_detect$10[0:0]$11765 $3\wr_detect$10[0:0]$11764 end case - assign $1\wr_detect$10[0:0]$11596 1'0 + assign $1\wr_detect$10[0:0]$11762 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11595 + update \wr_detect$10 $0\wr_detect$10[0:0]$11761 end - attribute \src "libresoc.v:180805.3-180844.6" - process $proc$libresoc.v:180805$11600 + attribute \src "libresoc.v:183025.3-183064.6" + process $proc$libresoc.v:183025$11766 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11601 $6\r26__data_o$next[3:0]$11607 - attribute \src "libresoc.v:180806.5-180806.29" + assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 + attribute \src "libresoc.v:183026.5-183026.29" switch \initial - attribute \src "libresoc.v:180806.9-180806.17" + attribute \src "libresoc.v:183026.9-183026.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11602 $5\r26__data_o$next[3:0]$11606 + assign $1\r6__data_o$next[3:0]$11768 $5\r6__data_o$next[3:0]$11772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11603 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11769 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11603 4'0000 + assign $2\r6__data_o$next[3:0]$11769 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11604 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11770 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11604 $2\r26__data_o$next[3:0]$11603 + assign $3\r6__data_o$next[3:0]$11770 $2\r6__data_o$next[3:0]$11769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11605 \w6__data_i + assign $4\r6__data_o$next[3:0]$11771 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11605 $3\r26__data_o$next[3:0]$11604 + assign $4\r6__data_o$next[3:0]$11771 $3\r6__data_o$next[3:0]$11770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11606 \reg + assign $5\r6__data_o$next[3:0]$11772 \reg case - assign $5\r26__data_o$next[3:0]$11606 $4\r26__data_o$next[3:0]$11605 + assign $5\r6__data_o$next[3:0]$11772 $4\r6__data_o$next[3:0]$11771 end case - assign $1\r26__data_o$next[3:0]$11602 4'0000 + assign $1\r6__data_o$next[3:0]$11768 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11607 4'0000 + assign $6\r6__data_o$next[3:0]$11773 4'0000 case - assign $6\r26__data_o$next[3:0]$11607 $1\r26__data_o$next[3:0]$11602 + assign $6\r6__data_o$next[3:0]$11773 $1\r6__data_o$next[3:0]$11768 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11601 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 end - attribute \src "libresoc.v:180845.3-180874.6" - process $proc$libresoc.v:180845$11608 + attribute \src "libresoc.v:183065.3-183094.6" + process $proc$libresoc.v:183065$11774 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11609 $1\wr_detect$13[0:0]$11610 - attribute \src "libresoc.v:180846.5-180846.29" + assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 + attribute \src "libresoc.v:183066.5-183066.29" switch \initial - attribute \src "libresoc.v:180846.9-180846.17" + attribute \src "libresoc.v:183066.9-183066.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11610 $4\wr_detect$13[0:0]$11613 + assign $1\wr_detect$13[0:0]$11776 $4\wr_detect$13[0:0]$11779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11611 1'1 + assign $2\wr_detect$13[0:0]$11777 1'1 case - assign $2\wr_detect$13[0:0]$11611 1'0 + assign $2\wr_detect$13[0:0]$11777 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11612 1'1 + assign $3\wr_detect$13[0:0]$11778 1'1 case - assign $3\wr_detect$13[0:0]$11612 $2\wr_detect$13[0:0]$11611 + assign $3\wr_detect$13[0:0]$11778 $2\wr_detect$13[0:0]$11777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11613 1'1 + assign $4\wr_detect$13[0:0]$11779 1'1 case - assign $4\wr_detect$13[0:0]$11613 $3\wr_detect$13[0:0]$11612 + assign $4\wr_detect$13[0:0]$11779 $3\wr_detect$13[0:0]$11778 end case - assign $1\wr_detect$13[0:0]$11610 1'0 + assign $1\wr_detect$13[0:0]$11776 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11609 + update \wr_detect$13 $0\wr_detect$13[0:0]$11775 end - connect \$9 $not$libresoc.v:180481$11532_Y - connect \$12 $not$libresoc.v:180482$11533_Y - connect \$1 $not$libresoc.v:180483$11534_Y - connect \$3 $not$libresoc.v:180484$11535_Y - connect \$6 $not$libresoc.v:180485$11536_Y + connect \$9 $not$libresoc.v:182628$11682_Y + connect \$12 $not$libresoc.v:182629$11683_Y + connect \$15 $not$libresoc.v:182630$11684_Y + connect \$1 $not$libresoc.v:182631$11685_Y + connect \$3 $not$libresoc.v:182632$11686_Y + connect \$6 $not$libresoc.v:182633$11687_Y end -attribute \src "libresoc.v:180879.1-181350.10" +attribute \src "libresoc.v:183099.1-183654.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:180880.7-180880.20" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 + attribute \src "libresoc.v:183205.3-183206.49" + wire width 4 $0\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183100.7-183100.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $0\r27__data_o$next[3:0]$11690 - attribute \src "libresoc.v:180963.3-180964.39" + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $0\r27__data_o$next[3:0]$11811 + attribute \src "libresoc.v:183195.3-183196.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $0\r7__data_o$next[3:0]$11676 - attribute \src "libresoc.v:180965.3-180966.37" + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $0\r7__data_o$next[3:0]$11873 + attribute \src "libresoc.v:183197.3-183198.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $0\reg$next[3:0]$11642 - attribute \src "libresoc.v:180961.3-180962.25" + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $0\reg$next[3:0]$11825 + attribute \src "libresoc.v:183193.3-183194.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $0\src17__data_o$next[3:0]$11633 - attribute \src "libresoc.v:180971.3-180972.43" + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $0\src17__data_o$next[3:0]$11831 + attribute \src "libresoc.v:183203.3-183204.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $0\src27__data_o$next[3:0]$11648 - attribute \src "libresoc.v:180969.3-180970.43" + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $0\src27__data_o$next[3:0]$11845 + attribute \src "libresoc.v:183201.3-183202.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $0\src37__data_o$next[3:0]$11662 - attribute \src "libresoc.v:180967.3-180968.43" + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $0\src37__data_o$next[3:0]$11859 + attribute \src "libresoc.v:183199.3-183200.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:181250.3-181279.6" - wire $0\wr_detect$10[0:0]$11684 - attribute \src "libresoc.v:181320.3-181349.6" - wire $0\wr_detect$13[0:0]$11698 - attribute \src "libresoc.v:181110.3-181139.6" - wire $0\wr_detect$4[0:0]$11656 - attribute \src "libresoc.v:181180.3-181209.6" - wire $0\wr_detect$7[0:0]$11670 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183554.3-183583.6" + wire $0\wr_detect$10[0:0]$11867 + attribute \src "libresoc.v:183624.3-183653.6" + wire $0\wr_detect$13[0:0]$11881 + attribute \src "libresoc.v:183317.3-183346.6" + wire $0\wr_detect$16[0:0]$11819 + attribute \src "libresoc.v:183414.3-183443.6" + wire $0\wr_detect$4[0:0]$11839 + attribute \src "libresoc.v:183484.3-183513.6" + wire $0\wr_detect$7[0:0]$11853 + attribute \src "libresoc.v:183247.3-183276.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $1\r27__data_o$next[3:0]$11691 - attribute \src "libresoc.v:180905.13-180905.31" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 + attribute \src "libresoc.v:183119.13-183119.36" + wire width 4 $1\cr_pred7__data_o[3:0] + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $1\r27__data_o$next[3:0]$11812 + attribute \src "libresoc.v:183134.13-183134.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $1\r7__data_o$next[3:0]$11677 - attribute \src "libresoc.v:180912.13-180912.30" + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $1\r7__data_o$next[3:0]$11874 + attribute \src "libresoc.v:183141.13-183141.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $1\reg$next[3:0]$11643 - attribute \src "libresoc.v:180918.13-180918.25" + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $1\reg$next[3:0]$11826 + attribute \src "libresoc.v:183147.13-183147.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $1\src17__data_o$next[3:0]$11634 - attribute \src "libresoc.v:180923.13-180923.33" + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $1\src17__data_o$next[3:0]$11832 + attribute \src "libresoc.v:183152.13-183152.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $1\src27__data_o$next[3:0]$11649 - attribute \src "libresoc.v:180930.13-180930.33" + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $1\src27__data_o$next[3:0]$11846 + attribute \src "libresoc.v:183159.13-183159.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $1\src37__data_o$next[3:0]$11663 - attribute \src "libresoc.v:180937.13-180937.33" + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $1\src37__data_o$next[3:0]$11860 + attribute \src "libresoc.v:183166.13-183166.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:181250.3-181279.6" - wire $1\wr_detect$10[0:0]$11685 - attribute \src "libresoc.v:181320.3-181349.6" - wire $1\wr_detect$13[0:0]$11699 - attribute \src "libresoc.v:181110.3-181139.6" - wire $1\wr_detect$4[0:0]$11657 - attribute \src "libresoc.v:181180.3-181209.6" - wire $1\wr_detect$7[0:0]$11671 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183554.3-183583.6" + wire $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183624.3-183653.6" + wire $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183317.3-183346.6" + wire $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183414.3-183443.6" + wire $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183484.3-183513.6" + wire $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183247.3-183276.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $2\r27__data_o$next[3:0]$11692 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $2\r7__data_o$next[3:0]$11678 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $2\reg$next[3:0]$11644 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $2\src17__data_o$next[3:0]$11635 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $2\src27__data_o$next[3:0]$11650 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $2\src37__data_o$next[3:0]$11664 - attribute \src "libresoc.v:181250.3-181279.6" - wire $2\wr_detect$10[0:0]$11686 - attribute \src "libresoc.v:181320.3-181349.6" - wire $2\wr_detect$13[0:0]$11700 - attribute \src "libresoc.v:181110.3-181139.6" - wire $2\wr_detect$4[0:0]$11658 - attribute \src "libresoc.v:181180.3-181209.6" - wire $2\wr_detect$7[0:0]$11672 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $2\r27__data_o$next[3:0]$11813 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $2\r7__data_o$next[3:0]$11875 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $2\reg$next[3:0]$11827 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $2\src17__data_o$next[3:0]$11833 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $2\src27__data_o$next[3:0]$11847 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $2\src37__data_o$next[3:0]$11861 + attribute \src "libresoc.v:183554.3-183583.6" + wire $2\wr_detect$10[0:0]$11869 + attribute \src "libresoc.v:183624.3-183653.6" + wire $2\wr_detect$13[0:0]$11883 + attribute \src "libresoc.v:183317.3-183346.6" + wire $2\wr_detect$16[0:0]$11821 + attribute \src "libresoc.v:183414.3-183443.6" + wire $2\wr_detect$4[0:0]$11841 + attribute \src "libresoc.v:183484.3-183513.6" + wire $2\wr_detect$7[0:0]$11855 + attribute \src "libresoc.v:183247.3-183276.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $3\r27__data_o$next[3:0]$11693 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $3\r7__data_o$next[3:0]$11679 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $3\reg$next[3:0]$11645 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $3\src17__data_o$next[3:0]$11636 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $3\src27__data_o$next[3:0]$11651 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $3\src37__data_o$next[3:0]$11665 - attribute \src "libresoc.v:181250.3-181279.6" - wire $3\wr_detect$10[0:0]$11687 - attribute \src "libresoc.v:181320.3-181349.6" - wire $3\wr_detect$13[0:0]$11701 - attribute \src "libresoc.v:181110.3-181139.6" - wire $3\wr_detect$4[0:0]$11659 - attribute \src "libresoc.v:181180.3-181209.6" - wire $3\wr_detect$7[0:0]$11673 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $3\r27__data_o$next[3:0]$11814 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $3\r7__data_o$next[3:0]$11876 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $3\reg$next[3:0]$11828 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $3\src17__data_o$next[3:0]$11834 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $3\src27__data_o$next[3:0]$11848 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $3\src37__data_o$next[3:0]$11862 + attribute \src "libresoc.v:183554.3-183583.6" + wire $3\wr_detect$10[0:0]$11870 + attribute \src "libresoc.v:183624.3-183653.6" + wire $3\wr_detect$13[0:0]$11884 + attribute \src "libresoc.v:183317.3-183346.6" + wire $3\wr_detect$16[0:0]$11822 + attribute \src "libresoc.v:183414.3-183443.6" + wire $3\wr_detect$4[0:0]$11842 + attribute \src "libresoc.v:183484.3-183513.6" + wire $3\wr_detect$7[0:0]$11856 + attribute \src "libresoc.v:183247.3-183276.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $4\r27__data_o$next[3:0]$11694 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $4\r7__data_o$next[3:0]$11680 - attribute \src "libresoc.v:181043.3-181069.6" - wire width 4 $4\reg$next[3:0]$11646 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $4\src17__data_o$next[3:0]$11637 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $4\src27__data_o$next[3:0]$11652 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $4\src37__data_o$next[3:0]$11666 - attribute \src "libresoc.v:181250.3-181279.6" - wire $4\wr_detect$10[0:0]$11688 - attribute \src "libresoc.v:181320.3-181349.6" - wire $4\wr_detect$13[0:0]$11702 - attribute \src "libresoc.v:181110.3-181139.6" - wire $4\wr_detect$4[0:0]$11660 - attribute \src "libresoc.v:181180.3-181209.6" - wire $4\wr_detect$7[0:0]$11674 - attribute \src "libresoc.v:181013.3-181042.6" + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $4\r27__data_o$next[3:0]$11815 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $4\r7__data_o$next[3:0]$11877 + attribute \src "libresoc.v:183347.3-183373.6" + wire width 4 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $4\src17__data_o$next[3:0]$11835 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $4\src27__data_o$next[3:0]$11849 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $4\src37__data_o$next[3:0]$11863 + attribute \src "libresoc.v:183554.3-183583.6" + wire $4\wr_detect$10[0:0]$11871 + attribute \src "libresoc.v:183624.3-183653.6" + wire $4\wr_detect$13[0:0]$11885 + attribute \src "libresoc.v:183317.3-183346.6" + wire $4\wr_detect$16[0:0]$11823 + attribute \src "libresoc.v:183414.3-183443.6" + wire $4\wr_detect$4[0:0]$11843 + attribute \src "libresoc.v:183484.3-183513.6" + wire $4\wr_detect$7[0:0]$11857 + attribute \src "libresoc.v:183247.3-183276.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $5\r27__data_o$next[3:0]$11695 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $5\r7__data_o$next[3:0]$11681 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $5\src17__data_o$next[3:0]$11638 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $5\src27__data_o$next[3:0]$11653 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $5\src37__data_o$next[3:0]$11667 - attribute \src "libresoc.v:181280.3-181319.6" - wire width 4 $6\r27__data_o$next[3:0]$11696 - attribute \src "libresoc.v:181210.3-181249.6" - wire width 4 $6\r7__data_o$next[3:0]$11682 - attribute \src "libresoc.v:180973.3-181012.6" - wire width 4 $6\src17__data_o$next[3:0]$11639 - attribute \src "libresoc.v:181070.3-181109.6" - wire width 4 $6\src27__data_o$next[3:0]$11654 - attribute \src "libresoc.v:181140.3-181179.6" - wire width 4 $6\src37__data_o$next[3:0]$11668 - attribute \src "libresoc.v:180956.17-180956.104" - wire $not$libresoc.v:180956$11621_Y - attribute \src "libresoc.v:180957.18-180957.105" - wire $not$libresoc.v:180957$11622_Y - attribute \src "libresoc.v:180958.17-180958.100" - wire $not$libresoc.v:180958$11623_Y - attribute \src "libresoc.v:180959.17-180959.103" - wire $not$libresoc.v:180959$11624_Y - attribute \src "libresoc.v:180960.17-180960.103" - wire $not$libresoc.v:180960$11625_Y + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $5\r27__data_o$next[3:0]$11816 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $5\r7__data_o$next[3:0]$11878 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $5\src17__data_o$next[3:0]$11836 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $5\src27__data_o$next[3:0]$11850 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $5\src37__data_o$next[3:0]$11864 + attribute \src "libresoc.v:183207.3-183246.6" + wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183277.3-183316.6" + wire width 4 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183584.3-183623.6" + wire width 4 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183374.3-183413.6" + wire width 4 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183444.3-183483.6" + wire width 4 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183514.3-183553.6" + wire width 4 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183187.17-183187.104" + wire $not$libresoc.v:183187$11788_Y + attribute \src "libresoc.v:183188.18-183188.105" + wire $not$libresoc.v:183188$11789_Y + attribute \src "libresoc.v:183189.18-183189.105" + wire $not$libresoc.v:183189$11790_Y + attribute \src "libresoc.v:183190.17-183190.100" + wire $not$libresoc.v:183190$11791_Y + attribute \src "libresoc.v:183191.17-183191.103" + wire $not$libresoc.v:183191$11792_Y + attribute \src "libresoc.v:183192.17-183192.103" + wire $not$libresoc.v:183192$11793_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 9 \dest17__data_i + wire width 4 output 3 \cr_pred7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 8 \dest17__wen + wire width 4 \cr_pred7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 11 \dest27__data_i + wire input 2 \cr_pred7__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \dest27__wen - attribute \src "libresoc.v:180880.7-180880.15" + wire width 4 input 11 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 13 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest27__wen + attribute \src "libresoc.v:183100.7-183100.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 14 \r27__data_o + wire width 4 output 16 \r27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 15 \r27__ren + wire input 17 \r27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 12 \r7__data_o + wire width 4 output 14 \r7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \r7__ren + wire input 15 \r7__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 3 \src17__data_o + wire width 4 output 5 \src17__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src17__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 2 \src17__ren + wire input 4 \src17__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 5 \src27__data_o + wire width 4 output 7 \src27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 4 \src27__ren + wire input 6 \src27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 output 7 \src37__data_o + wire width 4 output 9 \src37__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src37__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \src37__ren + wire input 8 \src37__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 4 input 16 \w7__data_i + wire width 4 input 18 \w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 17 \w7__wen + wire input 19 \w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" @@ -373311,232 +377169,257 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180956$11621 + cell $not $not$libresoc.v:183187$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180956$11621_Y + connect \Y $not$libresoc.v:183187$11788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180957$11622 + cell $not $not$libresoc.v:183188$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180957$11622_Y + connect \Y $not$libresoc.v:183188$11789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183189$11790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$16 + connect \Y $not$libresoc.v:183189$11790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180958$11623 + cell $not $not$libresoc.v:183190$11791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180958$11623_Y + connect \Y $not$libresoc.v:183190$11791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180959$11624 + cell $not $not$libresoc.v:183191$11792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180959$11624_Y + connect \Y $not$libresoc.v:183191$11792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180960$11625 + cell $not $not$libresoc.v:183192$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180960$11625_Y + connect \Y $not$libresoc.v:183192$11793_Y end - attribute \src "libresoc.v:180880.7-180880.20" - process $proc$libresoc.v:180880$11703 + attribute \src "libresoc.v:183100.7-183100.20" + process $proc$libresoc.v:183100$11886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180905.13-180905.31" - process $proc$libresoc.v:180905$11704 + attribute \src "libresoc.v:183119.13-183119.36" + process $proc$libresoc.v:183119$11887 + assign { } { } + assign $1\cr_pred7__data_o[3:0] 4'0000 + sync always + sync init + update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183134.13-183134.31" + process $proc$libresoc.v:183134$11888 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:180912.13-180912.30" - process $proc$libresoc.v:180912$11705 + attribute \src "libresoc.v:183141.13-183141.30" + process $proc$libresoc.v:183141$11889 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:180918.13-180918.25" - process $proc$libresoc.v:180918$11706 + attribute \src "libresoc.v:183147.13-183147.25" + process $proc$libresoc.v:183147$11890 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180923.13-180923.33" - process $proc$libresoc.v:180923$11707 + attribute \src "libresoc.v:183152.13-183152.33" + process $proc$libresoc.v:183152$11891 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:180930.13-180930.33" - process $proc$libresoc.v:180930$11708 + attribute \src "libresoc.v:183159.13-183159.33" + process $proc$libresoc.v:183159$11892 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:180937.13-180937.33" - process $proc$libresoc.v:180937$11709 + attribute \src "libresoc.v:183166.13-183166.33" + process $proc$libresoc.v:183166$11893 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:180961.3-180962.25" - process $proc$libresoc.v:180961$11626 + attribute \src "libresoc.v:183193.3-183194.25" + process $proc$libresoc.v:183193$11794 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180963.3-180964.39" - process $proc$libresoc.v:180963$11627 + attribute \src "libresoc.v:183195.3-183196.39" + process $proc$libresoc.v:183195$11795 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:180965.3-180966.37" - process $proc$libresoc.v:180965$11628 + attribute \src "libresoc.v:183197.3-183198.37" + process $proc$libresoc.v:183197$11796 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:180967.3-180968.43" - process $proc$libresoc.v:180967$11629 + attribute \src "libresoc.v:183199.3-183200.43" + process $proc$libresoc.v:183199$11797 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:180969.3-180970.43" - process $proc$libresoc.v:180969$11630 + attribute \src "libresoc.v:183201.3-183202.43" + process $proc$libresoc.v:183201$11798 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:180971.3-180972.43" - process $proc$libresoc.v:180971$11631 + attribute \src "libresoc.v:183203.3-183204.43" + process $proc$libresoc.v:183203$11799 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:180973.3-181012.6" - process $proc$libresoc.v:180973$11632 + attribute \src "libresoc.v:183205.3-183206.49" + process $proc$libresoc.v:183205$11800 + assign { } { } + assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next + sync posedge \coresync_clk + update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] + end + attribute \src "libresoc.v:183207.3-183246.6" + process $proc$libresoc.v:183207$11801 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11633 $6\src17__data_o$next[3:0]$11639 - attribute \src "libresoc.v:180974.5-180974.29" + assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 + attribute \src "libresoc.v:183208.5-183208.29" switch \initial - attribute \src "libresoc.v:180974.9-180974.17" + attribute \src "libresoc.v:183208.9-183208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \cr_pred7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11634 $5\src17__data_o$next[3:0]$11638 + assign $1\cr_pred7__data_o$next[3:0]$11803 $5\cr_pred7__data_o$next[3:0]$11807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11635 \dest17__data_i + assign $2\cr_pred7__data_o$next[3:0]$11804 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11635 4'0000 + assign $2\cr_pred7__data_o$next[3:0]$11804 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11636 \dest27__data_i + assign $3\cr_pred7__data_o$next[3:0]$11805 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11636 $2\src17__data_o$next[3:0]$11635 + assign $3\cr_pred7__data_o$next[3:0]$11805 $2\cr_pred7__data_o$next[3:0]$11804 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11637 \w7__data_i + assign $4\cr_pred7__data_o$next[3:0]$11806 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11637 $3\src17__data_o$next[3:0]$11636 + assign $4\cr_pred7__data_o$next[3:0]$11806 $3\cr_pred7__data_o$next[3:0]$11805 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11638 \reg + assign $5\cr_pred7__data_o$next[3:0]$11807 \reg case - assign $5\src17__data_o$next[3:0]$11638 $4\src17__data_o$next[3:0]$11637 + assign $5\cr_pred7__data_o$next[3:0]$11807 $4\cr_pred7__data_o$next[3:0]$11806 end case - assign $1\src17__data_o$next[3:0]$11634 4'0000 + assign $1\cr_pred7__data_o$next[3:0]$11803 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11639 4'0000 + assign $6\cr_pred7__data_o$next[3:0]$11808 4'0000 case - assign $6\src17__data_o$next[3:0]$11639 $1\src17__data_o$next[3:0]$11634 + assign $6\cr_pred7__data_o$next[3:0]$11808 $1\cr_pred7__data_o$next[3:0]$11803 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11633 + update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 end - attribute \src "libresoc.v:181013.3-181042.6" - process $proc$libresoc.v:181013$11640 + attribute \src "libresoc.v:183247.3-183276.6" + process $proc$libresoc.v:183247$11809 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181014.5-181014.29" + attribute \src "libresoc.v:183248.5-183248.29" switch \initial - attribute \src "libresoc.v:181014.9-181014.17" + attribute \src "libresoc.v:183248.9-183248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + switch \cr_pred7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -373577,17 +377460,142 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181043.3-181069.6" - process $proc$libresoc.v:181043$11641 + attribute \src "libresoc.v:183277.3-183316.6" + process $proc$libresoc.v:183277$11810 assign { } { } assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 + attribute \src "libresoc.v:183278.5-183278.29" + switch \initial + attribute \src "libresoc.v:183278.9-183278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$11812 $5\r27__data_o$next[3:0]$11816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$11813 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$11813 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$11814 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$11814 $2\r27__data_o$next[3:0]$11813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$11815 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$11815 $3\r27__data_o$next[3:0]$11814 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$11816 \reg + case + assign $5\r27__data_o$next[3:0]$11816 $4\r27__data_o$next[3:0]$11815 + end + case + assign $1\r27__data_o$next[3:0]$11812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$11817 4'0000 + case + assign $6\r27__data_o$next[3:0]$11817 $1\r27__data_o$next[3:0]$11812 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 + end + attribute \src "libresoc.v:183317.3-183346.6" + process $proc$libresoc.v:183317$11818 + assign { } { } + assign { } { } + assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 + attribute \src "libresoc.v:183318.5-183318.29" + switch \initial + attribute \src "libresoc.v:183318.9-183318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$16[0:0]$11820 $4\wr_detect$16[0:0]$11823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$16[0:0]$11821 1'1 + case + assign $2\wr_detect$16[0:0]$11821 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$16[0:0]$11822 1'1 + case + assign $3\wr_detect$16[0:0]$11822 $2\wr_detect$16[0:0]$11821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$16[0:0]$11823 1'1 + case + assign $4\wr_detect$16[0:0]$11823 $3\wr_detect$16[0:0]$11822 + end + case + assign $1\wr_detect$16[0:0]$11820 1'0 + end + sync always + update \wr_detect$16 $0\wr_detect$16[0:0]$11819 + end + attribute \src "libresoc.v:183347.3-183373.6" + process $proc$libresoc.v:183347$11824 assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11642 $4\reg$next[3:0]$11646 - attribute \src "libresoc.v:181044.5-181044.29" + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 + attribute \src "libresoc.v:183348.5-183348.29" switch \initial - attribute \src "libresoc.v:181044.9-181044.17" + attribute \src "libresoc.v:183348.9-183348.17" case 1'1 case end @@ -373596,577 +377604,578 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11643 \dest17__data_i + assign $1\reg$next[3:0]$11826 \dest17__data_i case - assign $1\reg$next[3:0]$11643 \reg + assign $1\reg$next[3:0]$11826 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11644 \dest27__data_i + assign $2\reg$next[3:0]$11827 \dest27__data_i case - assign $2\reg$next[3:0]$11644 $1\reg$next[3:0]$11643 + assign $2\reg$next[3:0]$11827 $1\reg$next[3:0]$11826 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11645 \w7__data_i + assign $3\reg$next[3:0]$11828 \w7__data_i case - assign $3\reg$next[3:0]$11645 $2\reg$next[3:0]$11644 + assign $3\reg$next[3:0]$11828 $2\reg$next[3:0]$11827 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11646 4'0000 + assign $4\reg$next[3:0]$11829 4'0000 case - assign $4\reg$next[3:0]$11646 $3\reg$next[3:0]$11645 + assign $4\reg$next[3:0]$11829 $3\reg$next[3:0]$11828 end sync always - update \reg$next $0\reg$next[3:0]$11642 + update \reg$next $0\reg$next[3:0]$11825 end - attribute \src "libresoc.v:181070.3-181109.6" - process $proc$libresoc.v:181070$11647 + attribute \src "libresoc.v:183374.3-183413.6" + process $proc$libresoc.v:183374$11830 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11648 $6\src27__data_o$next[3:0]$11654 - attribute \src "libresoc.v:181071.5-181071.29" + assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 + attribute \src "libresoc.v:183375.5-183375.29" switch \initial - attribute \src "libresoc.v:181071.9-181071.17" + attribute \src "libresoc.v:183375.9-183375.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11649 $5\src27__data_o$next[3:0]$11653 + assign $1\src17__data_o$next[3:0]$11832 $5\src17__data_o$next[3:0]$11836 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11650 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11833 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11650 4'0000 + assign $2\src17__data_o$next[3:0]$11833 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11651 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11834 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11651 $2\src27__data_o$next[3:0]$11650 + assign $3\src17__data_o$next[3:0]$11834 $2\src17__data_o$next[3:0]$11833 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11652 \w7__data_i + assign $4\src17__data_o$next[3:0]$11835 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11652 $3\src27__data_o$next[3:0]$11651 + assign $4\src17__data_o$next[3:0]$11835 $3\src17__data_o$next[3:0]$11834 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11653 \reg + assign $5\src17__data_o$next[3:0]$11836 \reg case - assign $5\src27__data_o$next[3:0]$11653 $4\src27__data_o$next[3:0]$11652 + assign $5\src17__data_o$next[3:0]$11836 $4\src17__data_o$next[3:0]$11835 end case - assign $1\src27__data_o$next[3:0]$11649 4'0000 + assign $1\src17__data_o$next[3:0]$11832 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11654 4'0000 + assign $6\src17__data_o$next[3:0]$11837 4'0000 case - assign $6\src27__data_o$next[3:0]$11654 $1\src27__data_o$next[3:0]$11649 + assign $6\src17__data_o$next[3:0]$11837 $1\src17__data_o$next[3:0]$11832 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11648 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 end - attribute \src "libresoc.v:181110.3-181139.6" - process $proc$libresoc.v:181110$11655 + attribute \src "libresoc.v:183414.3-183443.6" + process $proc$libresoc.v:183414$11838 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11656 $1\wr_detect$4[0:0]$11657 - attribute \src "libresoc.v:181111.5-181111.29" + assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 + attribute \src "libresoc.v:183415.5-183415.29" switch \initial - attribute \src "libresoc.v:181111.9-181111.17" + attribute \src "libresoc.v:183415.9-183415.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11657 $4\wr_detect$4[0:0]$11660 + assign $1\wr_detect$4[0:0]$11840 $4\wr_detect$4[0:0]$11843 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11658 1'1 + assign $2\wr_detect$4[0:0]$11841 1'1 case - assign $2\wr_detect$4[0:0]$11658 1'0 + assign $2\wr_detect$4[0:0]$11841 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11659 1'1 + assign $3\wr_detect$4[0:0]$11842 1'1 case - assign $3\wr_detect$4[0:0]$11659 $2\wr_detect$4[0:0]$11658 + assign $3\wr_detect$4[0:0]$11842 $2\wr_detect$4[0:0]$11841 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11660 1'1 + assign $4\wr_detect$4[0:0]$11843 1'1 case - assign $4\wr_detect$4[0:0]$11660 $3\wr_detect$4[0:0]$11659 + assign $4\wr_detect$4[0:0]$11843 $3\wr_detect$4[0:0]$11842 end case - assign $1\wr_detect$4[0:0]$11657 1'0 + assign $1\wr_detect$4[0:0]$11840 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11656 + update \wr_detect$4 $0\wr_detect$4[0:0]$11839 end - attribute \src "libresoc.v:181140.3-181179.6" - process $proc$libresoc.v:181140$11661 + attribute \src "libresoc.v:183444.3-183483.6" + process $proc$libresoc.v:183444$11844 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11662 $6\src37__data_o$next[3:0]$11668 - attribute \src "libresoc.v:181141.5-181141.29" + assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 + attribute \src "libresoc.v:183445.5-183445.29" switch \initial - attribute \src "libresoc.v:181141.9-181141.17" + attribute \src "libresoc.v:183445.9-183445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11663 $5\src37__data_o$next[3:0]$11667 + assign $1\src27__data_o$next[3:0]$11846 $5\src27__data_o$next[3:0]$11850 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11664 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11847 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11664 4'0000 + assign $2\src27__data_o$next[3:0]$11847 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11665 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11848 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11665 $2\src37__data_o$next[3:0]$11664 + assign $3\src27__data_o$next[3:0]$11848 $2\src27__data_o$next[3:0]$11847 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11666 \w7__data_i + assign $4\src27__data_o$next[3:0]$11849 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11666 $3\src37__data_o$next[3:0]$11665 + assign $4\src27__data_o$next[3:0]$11849 $3\src27__data_o$next[3:0]$11848 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11667 \reg + assign $5\src27__data_o$next[3:0]$11850 \reg case - assign $5\src37__data_o$next[3:0]$11667 $4\src37__data_o$next[3:0]$11666 + assign $5\src27__data_o$next[3:0]$11850 $4\src27__data_o$next[3:0]$11849 end case - assign $1\src37__data_o$next[3:0]$11663 4'0000 + assign $1\src27__data_o$next[3:0]$11846 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11668 4'0000 + assign $6\src27__data_o$next[3:0]$11851 4'0000 case - assign $6\src37__data_o$next[3:0]$11668 $1\src37__data_o$next[3:0]$11663 + assign $6\src27__data_o$next[3:0]$11851 $1\src27__data_o$next[3:0]$11846 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11662 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 end - attribute \src "libresoc.v:181180.3-181209.6" - process $proc$libresoc.v:181180$11669 + attribute \src "libresoc.v:183484.3-183513.6" + process $proc$libresoc.v:183484$11852 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11670 $1\wr_detect$7[0:0]$11671 - attribute \src "libresoc.v:181181.5-181181.29" + assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 + attribute \src "libresoc.v:183485.5-183485.29" switch \initial - attribute \src "libresoc.v:181181.9-181181.17" + attribute \src "libresoc.v:183485.9-183485.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11671 $4\wr_detect$7[0:0]$11674 + assign $1\wr_detect$7[0:0]$11854 $4\wr_detect$7[0:0]$11857 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11672 1'1 + assign $2\wr_detect$7[0:0]$11855 1'1 case - assign $2\wr_detect$7[0:0]$11672 1'0 + assign $2\wr_detect$7[0:0]$11855 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11673 1'1 + assign $3\wr_detect$7[0:0]$11856 1'1 case - assign $3\wr_detect$7[0:0]$11673 $2\wr_detect$7[0:0]$11672 + assign $3\wr_detect$7[0:0]$11856 $2\wr_detect$7[0:0]$11855 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11674 1'1 + assign $4\wr_detect$7[0:0]$11857 1'1 case - assign $4\wr_detect$7[0:0]$11674 $3\wr_detect$7[0:0]$11673 + assign $4\wr_detect$7[0:0]$11857 $3\wr_detect$7[0:0]$11856 end case - assign $1\wr_detect$7[0:0]$11671 1'0 + assign $1\wr_detect$7[0:0]$11854 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11670 + update \wr_detect$7 $0\wr_detect$7[0:0]$11853 end - attribute \src "libresoc.v:181210.3-181249.6" - process $proc$libresoc.v:181210$11675 + attribute \src "libresoc.v:183514.3-183553.6" + process $proc$libresoc.v:183514$11858 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11676 $6\r7__data_o$next[3:0]$11682 - attribute \src "libresoc.v:181211.5-181211.29" + assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 + attribute \src "libresoc.v:183515.5-183515.29" switch \initial - attribute \src "libresoc.v:181211.9-181211.17" + attribute \src "libresoc.v:183515.9-183515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11677 $5\r7__data_o$next[3:0]$11681 + assign $1\src37__data_o$next[3:0]$11860 $5\src37__data_o$next[3:0]$11864 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11678 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11861 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11678 4'0000 + assign $2\src37__data_o$next[3:0]$11861 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11679 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11862 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11679 $2\r7__data_o$next[3:0]$11678 + assign $3\src37__data_o$next[3:0]$11862 $2\src37__data_o$next[3:0]$11861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11680 \w7__data_i + assign $4\src37__data_o$next[3:0]$11863 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11680 $3\r7__data_o$next[3:0]$11679 + assign $4\src37__data_o$next[3:0]$11863 $3\src37__data_o$next[3:0]$11862 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11681 \reg + assign $5\src37__data_o$next[3:0]$11864 \reg case - assign $5\r7__data_o$next[3:0]$11681 $4\r7__data_o$next[3:0]$11680 + assign $5\src37__data_o$next[3:0]$11864 $4\src37__data_o$next[3:0]$11863 end case - assign $1\r7__data_o$next[3:0]$11677 4'0000 + assign $1\src37__data_o$next[3:0]$11860 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11682 4'0000 + assign $6\src37__data_o$next[3:0]$11865 4'0000 case - assign $6\r7__data_o$next[3:0]$11682 $1\r7__data_o$next[3:0]$11677 + assign $6\src37__data_o$next[3:0]$11865 $1\src37__data_o$next[3:0]$11860 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11676 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 end - attribute \src "libresoc.v:181250.3-181279.6" - process $proc$libresoc.v:181250$11683 + attribute \src "libresoc.v:183554.3-183583.6" + process $proc$libresoc.v:183554$11866 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11684 $1\wr_detect$10[0:0]$11685 - attribute \src "libresoc.v:181251.5-181251.29" + assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 + attribute \src "libresoc.v:183555.5-183555.29" switch \initial - attribute \src "libresoc.v:181251.9-181251.17" + attribute \src "libresoc.v:183555.9-183555.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11685 $4\wr_detect$10[0:0]$11688 + assign $1\wr_detect$10[0:0]$11868 $4\wr_detect$10[0:0]$11871 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11686 1'1 + assign $2\wr_detect$10[0:0]$11869 1'1 case - assign $2\wr_detect$10[0:0]$11686 1'0 + assign $2\wr_detect$10[0:0]$11869 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11687 1'1 + assign $3\wr_detect$10[0:0]$11870 1'1 case - assign $3\wr_detect$10[0:0]$11687 $2\wr_detect$10[0:0]$11686 + assign $3\wr_detect$10[0:0]$11870 $2\wr_detect$10[0:0]$11869 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11688 1'1 + assign $4\wr_detect$10[0:0]$11871 1'1 case - assign $4\wr_detect$10[0:0]$11688 $3\wr_detect$10[0:0]$11687 + assign $4\wr_detect$10[0:0]$11871 $3\wr_detect$10[0:0]$11870 end case - assign $1\wr_detect$10[0:0]$11685 1'0 + assign $1\wr_detect$10[0:0]$11868 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11684 + update \wr_detect$10 $0\wr_detect$10[0:0]$11867 end - attribute \src "libresoc.v:181280.3-181319.6" - process $proc$libresoc.v:181280$11689 + attribute \src "libresoc.v:183584.3-183623.6" + process $proc$libresoc.v:183584$11872 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11690 $6\r27__data_o$next[3:0]$11696 - attribute \src "libresoc.v:181281.5-181281.29" + assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 + attribute \src "libresoc.v:183585.5-183585.29" switch \initial - attribute \src "libresoc.v:181281.9-181281.17" + attribute \src "libresoc.v:183585.9-183585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11691 $5\r27__data_o$next[3:0]$11695 + assign $1\r7__data_o$next[3:0]$11874 $5\r7__data_o$next[3:0]$11878 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11692 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11875 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11692 4'0000 + assign $2\r7__data_o$next[3:0]$11875 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11693 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11876 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11693 $2\r27__data_o$next[3:0]$11692 + assign $3\r7__data_o$next[3:0]$11876 $2\r7__data_o$next[3:0]$11875 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11694 \w7__data_i + assign $4\r7__data_o$next[3:0]$11877 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11694 $3\r27__data_o$next[3:0]$11693 + assign $4\r7__data_o$next[3:0]$11877 $3\r7__data_o$next[3:0]$11876 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11695 \reg + assign $5\r7__data_o$next[3:0]$11878 \reg case - assign $5\r27__data_o$next[3:0]$11695 $4\r27__data_o$next[3:0]$11694 + assign $5\r7__data_o$next[3:0]$11878 $4\r7__data_o$next[3:0]$11877 end case - assign $1\r27__data_o$next[3:0]$11691 4'0000 + assign $1\r7__data_o$next[3:0]$11874 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11696 4'0000 + assign $6\r7__data_o$next[3:0]$11879 4'0000 case - assign $6\r27__data_o$next[3:0]$11696 $1\r27__data_o$next[3:0]$11691 + assign $6\r7__data_o$next[3:0]$11879 $1\r7__data_o$next[3:0]$11874 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11690 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 end - attribute \src "libresoc.v:181320.3-181349.6" - process $proc$libresoc.v:181320$11697 + attribute \src "libresoc.v:183624.3-183653.6" + process $proc$libresoc.v:183624$11880 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11698 $1\wr_detect$13[0:0]$11699 - attribute \src "libresoc.v:181321.5-181321.29" + assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 + attribute \src "libresoc.v:183625.5-183625.29" switch \initial - attribute \src "libresoc.v:181321.9-181321.17" + attribute \src "libresoc.v:183625.9-183625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11699 $4\wr_detect$13[0:0]$11702 + assign $1\wr_detect$13[0:0]$11882 $4\wr_detect$13[0:0]$11885 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11700 1'1 + assign $2\wr_detect$13[0:0]$11883 1'1 case - assign $2\wr_detect$13[0:0]$11700 1'0 + assign $2\wr_detect$13[0:0]$11883 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11701 1'1 + assign $3\wr_detect$13[0:0]$11884 1'1 case - assign $3\wr_detect$13[0:0]$11701 $2\wr_detect$13[0:0]$11700 + assign $3\wr_detect$13[0:0]$11884 $2\wr_detect$13[0:0]$11883 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11702 1'1 + assign $4\wr_detect$13[0:0]$11885 1'1 case - assign $4\wr_detect$13[0:0]$11702 $3\wr_detect$13[0:0]$11701 + assign $4\wr_detect$13[0:0]$11885 $3\wr_detect$13[0:0]$11884 end case - assign $1\wr_detect$13[0:0]$11699 1'0 + assign $1\wr_detect$13[0:0]$11882 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11698 + update \wr_detect$13 $0\wr_detect$13[0:0]$11881 end - connect \$9 $not$libresoc.v:180956$11621_Y - connect \$12 $not$libresoc.v:180957$11622_Y - connect \$1 $not$libresoc.v:180958$11623_Y - connect \$3 $not$libresoc.v:180959$11624_Y - connect \$6 $not$libresoc.v:180960$11625_Y + connect \$9 $not$libresoc.v:183187$11788_Y + connect \$12 $not$libresoc.v:183188$11789_Y + connect \$15 $not$libresoc.v:183189$11790_Y + connect \$1 $not$libresoc.v:183190$11791_Y + connect \$3 $not$libresoc.v:183191$11792_Y + connect \$6 $not$libresoc.v:183192$11793_Y end -attribute \src "libresoc.v:181354.1-181412.10" +attribute \src "libresoc.v:183658.1-183716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:181355.7-181355.20" + attribute \src "libresoc.v:183659.7-183659.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181400.3-181408.6" - wire width 5 $0\q_int$next[4:0]$11720 - attribute \src "libresoc.v:181398.3-181399.27" + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $0\q_int$next[4:0]$11904 + attribute \src "libresoc.v:183702.3-183703.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:181400.3-181408.6" - wire width 5 $1\q_int$next[4:0]$11721 - attribute \src "libresoc.v:181377.13-181377.26" + attribute \src "libresoc.v:183704.3-183712.6" + wire width 5 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183681.13-183681.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:181390.17-181390.96" - wire width 5 $and$libresoc.v:181390$11710_Y - attribute \src "libresoc.v:181395.17-181395.96" - wire width 5 $and$libresoc.v:181395$11715_Y - attribute \src "libresoc.v:181392.18-181392.93" - wire width 5 $not$libresoc.v:181392$11712_Y - attribute \src "libresoc.v:181394.17-181394.92" - wire width 5 $not$libresoc.v:181394$11714_Y - attribute \src "libresoc.v:181397.17-181397.92" - wire width 5 $not$libresoc.v:181397$11717_Y - attribute \src "libresoc.v:181391.18-181391.98" - wire width 5 $or$libresoc.v:181391$11711_Y - attribute \src "libresoc.v:181393.18-181393.99" - wire width 5 $or$libresoc.v:181393$11713_Y - attribute \src "libresoc.v:181396.17-181396.97" - wire width 5 $or$libresoc.v:181396$11716_Y + attribute \src "libresoc.v:183694.17-183694.96" + wire width 5 $and$libresoc.v:183694$11894_Y + attribute \src "libresoc.v:183699.17-183699.96" + wire width 5 $and$libresoc.v:183699$11899_Y + attribute \src "libresoc.v:183696.18-183696.93" + wire width 5 $not$libresoc.v:183696$11896_Y + attribute \src "libresoc.v:183698.17-183698.92" + wire width 5 $not$libresoc.v:183698$11898_Y + attribute \src "libresoc.v:183701.17-183701.92" + wire width 5 $not$libresoc.v:183701$11901_Y + attribute \src "libresoc.v:183695.18-183695.98" + wire width 5 $or$libresoc.v:183695$11895_Y + attribute \src "libresoc.v:183697.18-183697.99" + wire width 5 $or$libresoc.v:183697$11897_Y + attribute \src "libresoc.v:183700.17-183700.97" + wire width 5 $or$libresoc.v:183700$11900_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374183,11 +378192,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181355.7-181355.15" + attribute \src "libresoc.v:183659.7-183659.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -374204,7 +378213,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181390$11710 + cell $and $and$libresoc.v:183694$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374212,10 +378221,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181390$11710_Y + connect \Y $and$libresoc.v:183694$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181395$11715 + cell $and $and$libresoc.v:183699$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374223,34 +378232,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181395$11715_Y + connect \Y $and$libresoc.v:183699$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181392$11712 + cell $not $not$libresoc.v:183696$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:181392$11712_Y + connect \Y $not$libresoc.v:183696$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181394$11714 + cell $not $not$libresoc.v:183698$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181394$11714_Y + connect \Y $not$libresoc.v:183698$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181397$11717 + cell $not $not$libresoc.v:183701$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181397$11717_Y + connect \Y $not$libresoc.v:183701$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181391$11711 + cell $or $or$libresoc.v:183695$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374258,10 +378267,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181391$11711_Y + connect \Y $or$libresoc.v:183695$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181393$11713 + cell $or $or$libresoc.v:183697$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374269,10 +378278,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181393$11713_Y + connect \Y $or$libresoc.v:183697$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181396$11716 + cell $or $or$libresoc.v:183700$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -374280,39 +378289,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181396$11716_Y + connect \Y $or$libresoc.v:183700$11900_Y end - attribute \src "libresoc.v:181355.7-181355.20" - process $proc$libresoc.v:181355$11722 + attribute \src "libresoc.v:183659.7-183659.20" + process $proc$libresoc.v:183659$11906 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181377.13-181377.26" - process $proc$libresoc.v:181377$11723 + attribute \src "libresoc.v:183681.13-183681.26" + process $proc$libresoc.v:183681$11907 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:181398.3-181399.27" - process $proc$libresoc.v:181398$11718 + attribute \src "libresoc.v:183702.3-183703.27" + process $proc$libresoc.v:183702$11902 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:181400.3-181408.6" - process $proc$libresoc.v:181400$11719 + attribute \src "libresoc.v:183704.3-183712.6" + process $proc$libresoc.v:183704$11903 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11720 $1\q_int$next[4:0]$11721 - attribute \src "libresoc.v:181401.5-181401.29" + assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 + attribute \src "libresoc.v:183705.5-183705.29" switch \initial - attribute \src "libresoc.v:181401.9-181401.17" + attribute \src "libresoc.v:183705.9-183705.17" case 1'1 case end @@ -374321,56 +378330,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11721 5'00000 + assign $1\q_int$next[4:0]$11905 5'00000 case - assign $1\q_int$next[4:0]$11721 \$5 + assign $1\q_int$next[4:0]$11905 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11720 + update \q_int$next $0\q_int$next[4:0]$11904 end - connect \$9 $and$libresoc.v:181390$11710_Y - connect \$11 $or$libresoc.v:181391$11711_Y - connect \$13 $not$libresoc.v:181392$11712_Y - connect \$15 $or$libresoc.v:181393$11713_Y - connect \$1 $not$libresoc.v:181394$11714_Y - connect \$3 $and$libresoc.v:181395$11715_Y - connect \$5 $or$libresoc.v:181396$11716_Y - connect \$7 $not$libresoc.v:181397$11717_Y + connect \$9 $and$libresoc.v:183694$11894_Y + connect \$11 $or$libresoc.v:183695$11895_Y + connect \$13 $not$libresoc.v:183696$11896_Y + connect \$15 $or$libresoc.v:183697$11897_Y + connect \$1 $not$libresoc.v:183698$11898_Y + connect \$3 $and$libresoc.v:183699$11899_Y + connect \$5 $or$libresoc.v:183700$11900_Y + connect \$7 $not$libresoc.v:183701$11901_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181416.1-181474.10" +attribute \src "libresoc.v:183720.1-183778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:181417.7-181417.20" + attribute \src "libresoc.v:183721.7-183721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181462.3-181470.6" - wire width 4 $0\q_int$next[3:0]$11734 - attribute \src "libresoc.v:181460.3-181461.27" + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $0\q_int$next[3:0]$11918 + attribute \src "libresoc.v:183764.3-183765.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181462.3-181470.6" - wire width 4 $1\q_int$next[3:0]$11735 - attribute \src "libresoc.v:181439.13-181439.25" + attribute \src "libresoc.v:183766.3-183774.6" + wire width 4 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183743.13-183743.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181452.17-181452.96" - wire width 4 $and$libresoc.v:181452$11724_Y - attribute \src "libresoc.v:181457.17-181457.96" - wire width 4 $and$libresoc.v:181457$11729_Y - attribute \src "libresoc.v:181454.18-181454.93" - wire width 4 $not$libresoc.v:181454$11726_Y - attribute \src "libresoc.v:181456.17-181456.92" - wire width 4 $not$libresoc.v:181456$11728_Y - attribute \src "libresoc.v:181459.17-181459.92" - wire width 4 $not$libresoc.v:181459$11731_Y - attribute \src "libresoc.v:181453.18-181453.98" - wire width 4 $or$libresoc.v:181453$11725_Y - attribute \src "libresoc.v:181455.18-181455.99" - wire width 4 $or$libresoc.v:181455$11727_Y - attribute \src "libresoc.v:181458.17-181458.97" - wire width 4 $or$libresoc.v:181458$11730_Y + attribute \src "libresoc.v:183756.17-183756.96" + wire width 4 $and$libresoc.v:183756$11908_Y + attribute \src "libresoc.v:183761.17-183761.96" + wire width 4 $and$libresoc.v:183761$11913_Y + attribute \src "libresoc.v:183758.18-183758.93" + wire width 4 $not$libresoc.v:183758$11910_Y + attribute \src "libresoc.v:183760.17-183760.92" + wire width 4 $not$libresoc.v:183760$11912_Y + attribute \src "libresoc.v:183763.17-183763.92" + wire width 4 $not$libresoc.v:183763$11915_Y + attribute \src "libresoc.v:183757.18-183757.98" + wire width 4 $or$libresoc.v:183757$11909_Y + attribute \src "libresoc.v:183759.18-183759.99" + wire width 4 $or$libresoc.v:183759$11911_Y + attribute \src "libresoc.v:183762.17-183762.97" + wire width 4 $or$libresoc.v:183762$11914_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374387,11 +378396,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181417.7-181417.15" + attribute \src "libresoc.v:183721.7-183721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -374408,7 +378417,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181452$11724 + cell $and $and$libresoc.v:183756$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374416,10 +378425,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181452$11724_Y + connect \Y $and$libresoc.v:183756$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181457$11729 + cell $and $and$libresoc.v:183761$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374427,34 +378436,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181457$11729_Y + connect \Y $and$libresoc.v:183761$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181454$11726 + cell $not $not$libresoc.v:183758$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:181454$11726_Y + connect \Y $not$libresoc.v:183758$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181456$11728 + cell $not $not$libresoc.v:183760$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181456$11728_Y + connect \Y $not$libresoc.v:183760$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181459$11731 + cell $not $not$libresoc.v:183763$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181459$11731_Y + connect \Y $not$libresoc.v:183763$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181453$11725 + cell $or $or$libresoc.v:183757$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374462,10 +378471,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181453$11725_Y + connect \Y $or$libresoc.v:183757$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181455$11727 + cell $or $or$libresoc.v:183759$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374473,10 +378482,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181455$11727_Y + connect \Y $or$libresoc.v:183759$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181458$11730 + cell $or $or$libresoc.v:183762$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -374484,39 +378493,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181458$11730_Y + connect \Y $or$libresoc.v:183762$11914_Y end - attribute \src "libresoc.v:181417.7-181417.20" - process $proc$libresoc.v:181417$11736 + attribute \src "libresoc.v:183721.7-183721.20" + process $proc$libresoc.v:183721$11920 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181439.13-181439.25" - process $proc$libresoc.v:181439$11737 + attribute \src "libresoc.v:183743.13-183743.25" + process $proc$libresoc.v:183743$11921 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:181460.3-181461.27" - process $proc$libresoc.v:181460$11732 + attribute \src "libresoc.v:183764.3-183765.27" + process $proc$libresoc.v:183764$11916 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:181462.3-181470.6" - process $proc$libresoc.v:181462$11733 + attribute \src "libresoc.v:183766.3-183774.6" + process $proc$libresoc.v:183766$11917 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11734 $1\q_int$next[3:0]$11735 - attribute \src "libresoc.v:181463.5-181463.29" + assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 + attribute \src "libresoc.v:183767.5-183767.29" switch \initial - attribute \src "libresoc.v:181463.9-181463.17" + attribute \src "libresoc.v:183767.9-183767.17" case 1'1 case end @@ -374525,56 +378534,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11735 4'0000 + assign $1\q_int$next[3:0]$11919 4'0000 case - assign $1\q_int$next[3:0]$11735 \$5 + assign $1\q_int$next[3:0]$11919 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11734 + update \q_int$next $0\q_int$next[3:0]$11918 end - connect \$9 $and$libresoc.v:181452$11724_Y - connect \$11 $or$libresoc.v:181453$11725_Y - connect \$13 $not$libresoc.v:181454$11726_Y - connect \$15 $or$libresoc.v:181455$11727_Y - connect \$1 $not$libresoc.v:181456$11728_Y - connect \$3 $and$libresoc.v:181457$11729_Y - connect \$5 $or$libresoc.v:181458$11730_Y - connect \$7 $not$libresoc.v:181459$11731_Y + connect \$9 $and$libresoc.v:183756$11908_Y + connect \$11 $or$libresoc.v:183757$11909_Y + connect \$13 $not$libresoc.v:183758$11910_Y + connect \$15 $or$libresoc.v:183759$11911_Y + connect \$1 $not$libresoc.v:183760$11912_Y + connect \$3 $and$libresoc.v:183761$11913_Y + connect \$5 $or$libresoc.v:183762$11914_Y + connect \$7 $not$libresoc.v:183763$11915_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181478.1-181536.10" +attribute \src "libresoc.v:183782.1-183840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:181479.7-181479.20" + attribute \src "libresoc.v:183783.7-183783.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181524.3-181532.6" - wire width 3 $0\q_int$next[2:0]$11748 - attribute \src "libresoc.v:181522.3-181523.27" + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $0\q_int$next[2:0]$11932 + attribute \src "libresoc.v:183826.3-183827.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181524.3-181532.6" - wire width 3 $1\q_int$next[2:0]$11749 - attribute \src "libresoc.v:181501.13-181501.25" + attribute \src "libresoc.v:183828.3-183836.6" + wire width 3 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183805.13-183805.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181514.17-181514.96" - wire width 3 $and$libresoc.v:181514$11738_Y - attribute \src "libresoc.v:181519.17-181519.96" - wire width 3 $and$libresoc.v:181519$11743_Y - attribute \src "libresoc.v:181516.18-181516.93" - wire width 3 $not$libresoc.v:181516$11740_Y - attribute \src "libresoc.v:181518.17-181518.92" - wire width 3 $not$libresoc.v:181518$11742_Y - attribute \src "libresoc.v:181521.17-181521.92" - wire width 3 $not$libresoc.v:181521$11745_Y - attribute \src "libresoc.v:181515.18-181515.98" - wire width 3 $or$libresoc.v:181515$11739_Y - attribute \src "libresoc.v:181517.18-181517.99" - wire width 3 $or$libresoc.v:181517$11741_Y - attribute \src "libresoc.v:181520.17-181520.97" - wire width 3 $or$libresoc.v:181520$11744_Y + attribute \src "libresoc.v:183818.17-183818.96" + wire width 3 $and$libresoc.v:183818$11922_Y + attribute \src "libresoc.v:183823.17-183823.96" + wire width 3 $and$libresoc.v:183823$11927_Y + attribute \src "libresoc.v:183820.18-183820.93" + wire width 3 $not$libresoc.v:183820$11924_Y + attribute \src "libresoc.v:183822.17-183822.92" + wire width 3 $not$libresoc.v:183822$11926_Y + attribute \src "libresoc.v:183825.17-183825.92" + wire width 3 $not$libresoc.v:183825$11929_Y + attribute \src "libresoc.v:183819.18-183819.98" + wire width 3 $or$libresoc.v:183819$11923_Y + attribute \src "libresoc.v:183821.18-183821.99" + wire width 3 $or$libresoc.v:183821$11925_Y + attribute \src "libresoc.v:183824.17-183824.97" + wire width 3 $or$libresoc.v:183824$11928_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374591,11 +378600,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181479.7-181479.15" + attribute \src "libresoc.v:183783.7-183783.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -374612,7 +378621,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181514$11738 + cell $and $and$libresoc.v:183818$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374620,10 +378629,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181514$11738_Y + connect \Y $and$libresoc.v:183818$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181519$11743 + cell $and $and$libresoc.v:183823$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374631,34 +378640,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181519$11743_Y + connect \Y $and$libresoc.v:183823$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181516$11740 + cell $not $not$libresoc.v:183820$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181516$11740_Y + connect \Y $not$libresoc.v:183820$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181518$11742 + cell $not $not$libresoc.v:183822$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181518$11742_Y + connect \Y $not$libresoc.v:183822$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181521$11745 + cell $not $not$libresoc.v:183825$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181521$11745_Y + connect \Y $not$libresoc.v:183825$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181515$11739 + cell $or $or$libresoc.v:183819$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374666,10 +378675,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181515$11739_Y + connect \Y $or$libresoc.v:183819$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181517$11741 + cell $or $or$libresoc.v:183821$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374677,10 +378686,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181517$11741_Y + connect \Y $or$libresoc.v:183821$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181520$11744 + cell $or $or$libresoc.v:183824$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374688,39 +378697,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181520$11744_Y + connect \Y $or$libresoc.v:183824$11928_Y end - attribute \src "libresoc.v:181479.7-181479.20" - process $proc$libresoc.v:181479$11750 + attribute \src "libresoc.v:183783.7-183783.20" + process $proc$libresoc.v:183783$11934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181501.13-181501.25" - process $proc$libresoc.v:181501$11751 + attribute \src "libresoc.v:183805.13-183805.25" + process $proc$libresoc.v:183805$11935 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181522.3-181523.27" - process $proc$libresoc.v:181522$11746 + attribute \src "libresoc.v:183826.3-183827.27" + process $proc$libresoc.v:183826$11930 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181524.3-181532.6" - process $proc$libresoc.v:181524$11747 + attribute \src "libresoc.v:183828.3-183836.6" + process $proc$libresoc.v:183828$11931 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11748 $1\q_int$next[2:0]$11749 - attribute \src "libresoc.v:181525.5-181525.29" + assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 + attribute \src "libresoc.v:183829.5-183829.29" switch \initial - attribute \src "libresoc.v:181525.9-181525.17" + attribute \src "libresoc.v:183829.9-183829.17" case 1'1 case end @@ -374729,56 +378738,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11749 3'000 + assign $1\q_int$next[2:0]$11933 3'000 case - assign $1\q_int$next[2:0]$11749 \$5 + assign $1\q_int$next[2:0]$11933 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11748 + update \q_int$next $0\q_int$next[2:0]$11932 end - connect \$9 $and$libresoc.v:181514$11738_Y - connect \$11 $or$libresoc.v:181515$11739_Y - connect \$13 $not$libresoc.v:181516$11740_Y - connect \$15 $or$libresoc.v:181517$11741_Y - connect \$1 $not$libresoc.v:181518$11742_Y - connect \$3 $and$libresoc.v:181519$11743_Y - connect \$5 $or$libresoc.v:181520$11744_Y - connect \$7 $not$libresoc.v:181521$11745_Y + connect \$9 $and$libresoc.v:183818$11922_Y + connect \$11 $or$libresoc.v:183819$11923_Y + connect \$13 $not$libresoc.v:183820$11924_Y + connect \$15 $or$libresoc.v:183821$11925_Y + connect \$1 $not$libresoc.v:183822$11926_Y + connect \$3 $and$libresoc.v:183823$11927_Y + connect \$5 $or$libresoc.v:183824$11928_Y + connect \$7 $not$libresoc.v:183825$11929_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181540.1-181598.10" +attribute \src "libresoc.v:183844.1-183902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:181541.7-181541.20" + attribute \src "libresoc.v:183845.7-183845.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181586.3-181594.6" - wire width 3 $0\q_int$next[2:0]$11762 - attribute \src "libresoc.v:181584.3-181585.27" + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $0\q_int$next[2:0]$11946 + attribute \src "libresoc.v:183888.3-183889.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181586.3-181594.6" - wire width 3 $1\q_int$next[2:0]$11763 - attribute \src "libresoc.v:181563.13-181563.25" + attribute \src "libresoc.v:183890.3-183898.6" + wire width 3 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183867.13-183867.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181576.17-181576.96" - wire width 3 $and$libresoc.v:181576$11752_Y - attribute \src "libresoc.v:181581.17-181581.96" - wire width 3 $and$libresoc.v:181581$11757_Y - attribute \src "libresoc.v:181578.18-181578.93" - wire width 3 $not$libresoc.v:181578$11754_Y - attribute \src "libresoc.v:181580.17-181580.92" - wire width 3 $not$libresoc.v:181580$11756_Y - attribute \src "libresoc.v:181583.17-181583.92" - wire width 3 $not$libresoc.v:181583$11759_Y - attribute \src "libresoc.v:181577.18-181577.98" - wire width 3 $or$libresoc.v:181577$11753_Y - attribute \src "libresoc.v:181579.18-181579.99" - wire width 3 $or$libresoc.v:181579$11755_Y - attribute \src "libresoc.v:181582.17-181582.97" - wire width 3 $or$libresoc.v:181582$11758_Y + attribute \src "libresoc.v:183880.17-183880.96" + wire width 3 $and$libresoc.v:183880$11936_Y + attribute \src "libresoc.v:183885.17-183885.96" + wire width 3 $and$libresoc.v:183885$11941_Y + attribute \src "libresoc.v:183882.18-183882.93" + wire width 3 $not$libresoc.v:183882$11938_Y + attribute \src "libresoc.v:183884.17-183884.92" + wire width 3 $not$libresoc.v:183884$11940_Y + attribute \src "libresoc.v:183887.17-183887.92" + wire width 3 $not$libresoc.v:183887$11943_Y + attribute \src "libresoc.v:183881.18-183881.98" + wire width 3 $or$libresoc.v:183881$11937_Y + attribute \src "libresoc.v:183883.18-183883.99" + wire width 3 $or$libresoc.v:183883$11939_Y + attribute \src "libresoc.v:183886.17-183886.97" + wire width 3 $or$libresoc.v:183886$11942_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374795,11 +378804,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181541.7-181541.15" + attribute \src "libresoc.v:183845.7-183845.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -374816,7 +378825,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181576$11752 + cell $and $and$libresoc.v:183880$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374824,10 +378833,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181576$11752_Y + connect \Y $and$libresoc.v:183880$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181581$11757 + cell $and $and$libresoc.v:183885$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374835,34 +378844,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181581$11757_Y + connect \Y $and$libresoc.v:183885$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181578$11754 + cell $not $not$libresoc.v:183882$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181578$11754_Y + connect \Y $not$libresoc.v:183882$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181580$11756 + cell $not $not$libresoc.v:183884$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181580$11756_Y + connect \Y $not$libresoc.v:183884$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181583$11759 + cell $not $not$libresoc.v:183887$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181583$11759_Y + connect \Y $not$libresoc.v:183887$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181577$11753 + cell $or $or$libresoc.v:183881$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374870,10 +378879,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181577$11753_Y + connect \Y $or$libresoc.v:183881$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181579$11755 + cell $or $or$libresoc.v:183883$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374881,10 +378890,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181579$11755_Y + connect \Y $or$libresoc.v:183883$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181582$11758 + cell $or $or$libresoc.v:183886$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -374892,39 +378901,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181582$11758_Y + connect \Y $or$libresoc.v:183886$11942_Y end - attribute \src "libresoc.v:181541.7-181541.20" - process $proc$libresoc.v:181541$11764 + attribute \src "libresoc.v:183845.7-183845.20" + process $proc$libresoc.v:183845$11948 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181563.13-181563.25" - process $proc$libresoc.v:181563$11765 + attribute \src "libresoc.v:183867.13-183867.25" + process $proc$libresoc.v:183867$11949 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181584.3-181585.27" - process $proc$libresoc.v:181584$11760 + attribute \src "libresoc.v:183888.3-183889.27" + process $proc$libresoc.v:183888$11944 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181586.3-181594.6" - process $proc$libresoc.v:181586$11761 + attribute \src "libresoc.v:183890.3-183898.6" + process $proc$libresoc.v:183890$11945 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11762 $1\q_int$next[2:0]$11763 - attribute \src "libresoc.v:181587.5-181587.29" + assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 + attribute \src "libresoc.v:183891.5-183891.29" switch \initial - attribute \src "libresoc.v:181587.9-181587.17" + attribute \src "libresoc.v:183891.9-183891.17" case 1'1 case end @@ -374933,56 +378942,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11763 3'000 + assign $1\q_int$next[2:0]$11947 3'000 case - assign $1\q_int$next[2:0]$11763 \$5 + assign $1\q_int$next[2:0]$11947 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11762 + update \q_int$next $0\q_int$next[2:0]$11946 end - connect \$9 $and$libresoc.v:181576$11752_Y - connect \$11 $or$libresoc.v:181577$11753_Y - connect \$13 $not$libresoc.v:181578$11754_Y - connect \$15 $or$libresoc.v:181579$11755_Y - connect \$1 $not$libresoc.v:181580$11756_Y - connect \$3 $and$libresoc.v:181581$11757_Y - connect \$5 $or$libresoc.v:181582$11758_Y - connect \$7 $not$libresoc.v:181583$11759_Y + connect \$9 $and$libresoc.v:183880$11936_Y + connect \$11 $or$libresoc.v:183881$11937_Y + connect \$13 $not$libresoc.v:183882$11938_Y + connect \$15 $or$libresoc.v:183883$11939_Y + connect \$1 $not$libresoc.v:183884$11940_Y + connect \$3 $and$libresoc.v:183885$11941_Y + connect \$5 $or$libresoc.v:183886$11942_Y + connect \$7 $not$libresoc.v:183887$11943_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181602.1-181660.10" +attribute \src "libresoc.v:183906.1-183964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:181603.7-181603.20" + attribute \src "libresoc.v:183907.7-183907.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181648.3-181656.6" - wire width 3 $0\q_int$next[2:0]$11776 - attribute \src "libresoc.v:181646.3-181647.27" + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $0\q_int$next[2:0]$11960 + attribute \src "libresoc.v:183950.3-183951.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181648.3-181656.6" - wire width 3 $1\q_int$next[2:0]$11777 - attribute \src "libresoc.v:181625.13-181625.25" + attribute \src "libresoc.v:183952.3-183960.6" + wire width 3 $1\q_int$next[2:0]$11961 + attribute \src "libresoc.v:183929.13-183929.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181638.17-181638.96" - wire width 3 $and$libresoc.v:181638$11766_Y - attribute \src "libresoc.v:181643.17-181643.96" - wire width 3 $and$libresoc.v:181643$11771_Y - attribute \src "libresoc.v:181640.18-181640.93" - wire width 3 $not$libresoc.v:181640$11768_Y - attribute \src "libresoc.v:181642.17-181642.92" - wire width 3 $not$libresoc.v:181642$11770_Y - attribute \src "libresoc.v:181645.17-181645.92" - wire width 3 $not$libresoc.v:181645$11773_Y - attribute \src "libresoc.v:181639.18-181639.98" - wire width 3 $or$libresoc.v:181639$11767_Y - attribute \src "libresoc.v:181641.18-181641.99" - wire width 3 $or$libresoc.v:181641$11769_Y - attribute \src "libresoc.v:181644.17-181644.97" - wire width 3 $or$libresoc.v:181644$11772_Y + attribute \src "libresoc.v:183942.17-183942.96" + wire width 3 $and$libresoc.v:183942$11950_Y + attribute \src "libresoc.v:183947.17-183947.96" + wire width 3 $and$libresoc.v:183947$11955_Y + attribute \src "libresoc.v:183944.18-183944.93" + wire width 3 $not$libresoc.v:183944$11952_Y + attribute \src "libresoc.v:183946.17-183946.92" + wire width 3 $not$libresoc.v:183946$11954_Y + attribute \src "libresoc.v:183949.17-183949.92" + wire width 3 $not$libresoc.v:183949$11957_Y + attribute \src "libresoc.v:183943.18-183943.98" + wire width 3 $or$libresoc.v:183943$11951_Y + attribute \src "libresoc.v:183945.18-183945.99" + wire width 3 $or$libresoc.v:183945$11953_Y + attribute \src "libresoc.v:183948.17-183948.97" + wire width 3 $or$libresoc.v:183948$11956_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -374999,11 +379008,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181603.7-181603.15" + attribute \src "libresoc.v:183907.7-183907.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -375020,7 +379029,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181638$11766 + cell $and $and$libresoc.v:183942$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375028,10 +379037,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181638$11766_Y + connect \Y $and$libresoc.v:183942$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181643$11771 + cell $and $and$libresoc.v:183947$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375039,34 +379048,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181643$11771_Y + connect \Y $and$libresoc.v:183947$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181640$11768 + cell $not $not$libresoc.v:183944$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:181640$11768_Y + connect \Y $not$libresoc.v:183944$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181642$11770 + cell $not $not$libresoc.v:183946$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181642$11770_Y + connect \Y $not$libresoc.v:183946$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181645$11773 + cell $not $not$libresoc.v:183949$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:181645$11773_Y + connect \Y $not$libresoc.v:183949$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181639$11767 + cell $or $or$libresoc.v:183943$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375074,10 +379083,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181639$11767_Y + connect \Y $or$libresoc.v:183943$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181641$11769 + cell $or $or$libresoc.v:183945$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375085,10 +379094,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181641$11769_Y + connect \Y $or$libresoc.v:183945$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181644$11772 + cell $or $or$libresoc.v:183948$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375096,39 +379105,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181644$11772_Y + connect \Y $or$libresoc.v:183948$11956_Y end - attribute \src "libresoc.v:181603.7-181603.20" - process $proc$libresoc.v:181603$11778 + attribute \src "libresoc.v:183907.7-183907.20" + process $proc$libresoc.v:183907$11962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181625.13-181625.25" - process $proc$libresoc.v:181625$11779 + attribute \src "libresoc.v:183929.13-183929.25" + process $proc$libresoc.v:183929$11963 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:181646.3-181647.27" - process $proc$libresoc.v:181646$11774 + attribute \src "libresoc.v:183950.3-183951.27" + process $proc$libresoc.v:183950$11958 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:181648.3-181656.6" - process $proc$libresoc.v:181648$11775 + attribute \src "libresoc.v:183952.3-183960.6" + process $proc$libresoc.v:183952$11959 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11776 $1\q_int$next[2:0]$11777 - attribute \src "libresoc.v:181649.5-181649.29" + assign $0\q_int$next[2:0]$11960 $1\q_int$next[2:0]$11961 + attribute \src "libresoc.v:183953.5-183953.29" switch \initial - attribute \src "libresoc.v:181649.9-181649.17" + attribute \src "libresoc.v:183953.9-183953.17" case 1'1 case end @@ -375137,56 +379146,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11777 3'000 + assign $1\q_int$next[2:0]$11961 3'000 case - assign $1\q_int$next[2:0]$11777 \$5 + assign $1\q_int$next[2:0]$11961 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11776 + update \q_int$next $0\q_int$next[2:0]$11960 end - connect \$9 $and$libresoc.v:181638$11766_Y - connect \$11 $or$libresoc.v:181639$11767_Y - connect \$13 $not$libresoc.v:181640$11768_Y - connect \$15 $or$libresoc.v:181641$11769_Y - connect \$1 $not$libresoc.v:181642$11770_Y - connect \$3 $and$libresoc.v:181643$11771_Y - connect \$5 $or$libresoc.v:181644$11772_Y - connect \$7 $not$libresoc.v:181645$11773_Y + connect \$9 $and$libresoc.v:183942$11950_Y + connect \$11 $or$libresoc.v:183943$11951_Y + connect \$13 $not$libresoc.v:183944$11952_Y + connect \$15 $or$libresoc.v:183945$11953_Y + connect \$1 $not$libresoc.v:183946$11954_Y + connect \$3 $and$libresoc.v:183947$11955_Y + connect \$5 $or$libresoc.v:183948$11956_Y + connect \$7 $not$libresoc.v:183949$11957_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181664.1-181722.10" +attribute \src "libresoc.v:183968.1-184026.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:181665.7-181665.20" + attribute \src "libresoc.v:183969.7-183969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181710.3-181718.6" - wire width 5 $0\q_int$next[4:0]$11790 - attribute \src "libresoc.v:181708.3-181709.27" + attribute \src "libresoc.v:184014.3-184022.6" + wire width 5 $0\q_int$next[4:0]$11974 + attribute \src "libresoc.v:184012.3-184013.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:181710.3-181718.6" - wire width 5 $1\q_int$next[4:0]$11791 - attribute \src "libresoc.v:181687.13-181687.26" + attribute \src "libresoc.v:184014.3-184022.6" + wire width 5 $1\q_int$next[4:0]$11975 + attribute \src "libresoc.v:183991.13-183991.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:181700.17-181700.96" - wire width 5 $and$libresoc.v:181700$11780_Y - attribute \src "libresoc.v:181705.17-181705.96" - wire width 5 $and$libresoc.v:181705$11785_Y - attribute \src "libresoc.v:181702.18-181702.93" - wire width 5 $not$libresoc.v:181702$11782_Y - attribute \src "libresoc.v:181704.17-181704.92" - wire width 5 $not$libresoc.v:181704$11784_Y - attribute \src "libresoc.v:181707.17-181707.92" - wire width 5 $not$libresoc.v:181707$11787_Y - attribute \src "libresoc.v:181701.18-181701.98" - wire width 5 $or$libresoc.v:181701$11781_Y - attribute \src "libresoc.v:181703.18-181703.99" - wire width 5 $or$libresoc.v:181703$11783_Y - attribute \src "libresoc.v:181706.17-181706.97" - wire width 5 $or$libresoc.v:181706$11786_Y + attribute \src "libresoc.v:184004.17-184004.96" + wire width 5 $and$libresoc.v:184004$11964_Y + attribute \src "libresoc.v:184009.17-184009.96" + wire width 5 $and$libresoc.v:184009$11969_Y + attribute \src "libresoc.v:184006.18-184006.93" + wire width 5 $not$libresoc.v:184006$11966_Y + attribute \src "libresoc.v:184008.17-184008.92" + wire width 5 $not$libresoc.v:184008$11968_Y + attribute \src "libresoc.v:184011.17-184011.92" + wire width 5 $not$libresoc.v:184011$11971_Y + attribute \src "libresoc.v:184005.18-184005.98" + wire width 5 $or$libresoc.v:184005$11965_Y + attribute \src "libresoc.v:184007.18-184007.99" + wire width 5 $or$libresoc.v:184007$11967_Y + attribute \src "libresoc.v:184010.17-184010.97" + wire width 5 $or$libresoc.v:184010$11970_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375203,11 +379212,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181665.7-181665.15" + attribute \src "libresoc.v:183969.7-183969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -375224,7 +379233,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181700$11780 + cell $and $and$libresoc.v:184004$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375232,10 +379241,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181700$11780_Y + connect \Y $and$libresoc.v:184004$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181705$11785 + cell $and $and$libresoc.v:184009$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375243,34 +379252,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181705$11785_Y + connect \Y $and$libresoc.v:184009$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181702$11782 + cell $not $not$libresoc.v:184006$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:181702$11782_Y + connect \Y $not$libresoc.v:184006$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181704$11784 + cell $not $not$libresoc.v:184008$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181704$11784_Y + connect \Y $not$libresoc.v:184008$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181707$11787 + cell $not $not$libresoc.v:184011$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:181707$11787_Y + connect \Y $not$libresoc.v:184011$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181701$11781 + cell $or $or$libresoc.v:184005$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375278,10 +379287,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181701$11781_Y + connect \Y $or$libresoc.v:184005$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181703$11783 + cell $or $or$libresoc.v:184007$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375289,10 +379298,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181703$11783_Y + connect \Y $or$libresoc.v:184007$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181706$11786 + cell $or $or$libresoc.v:184010$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375300,39 +379309,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181706$11786_Y + connect \Y $or$libresoc.v:184010$11970_Y end - attribute \src "libresoc.v:181665.7-181665.20" - process $proc$libresoc.v:181665$11792 + attribute \src "libresoc.v:183969.7-183969.20" + process $proc$libresoc.v:183969$11976 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181687.13-181687.26" - process $proc$libresoc.v:181687$11793 + attribute \src "libresoc.v:183991.13-183991.26" + process $proc$libresoc.v:183991$11977 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:181708.3-181709.27" - process $proc$libresoc.v:181708$11788 + attribute \src "libresoc.v:184012.3-184013.27" + process $proc$libresoc.v:184012$11972 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:181710.3-181718.6" - process $proc$libresoc.v:181710$11789 + attribute \src "libresoc.v:184014.3-184022.6" + process $proc$libresoc.v:184014$11973 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11790 $1\q_int$next[4:0]$11791 - attribute \src "libresoc.v:181711.5-181711.29" + assign $0\q_int$next[4:0]$11974 $1\q_int$next[4:0]$11975 + attribute \src "libresoc.v:184015.5-184015.29" switch \initial - attribute \src "libresoc.v:181711.9-181711.17" + attribute \src "libresoc.v:184015.9-184015.17" case 1'1 case end @@ -375341,56 +379350,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11791 5'00000 + assign $1\q_int$next[4:0]$11975 5'00000 case - assign $1\q_int$next[4:0]$11791 \$5 + assign $1\q_int$next[4:0]$11975 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11790 + update \q_int$next $0\q_int$next[4:0]$11974 end - connect \$9 $and$libresoc.v:181700$11780_Y - connect \$11 $or$libresoc.v:181701$11781_Y - connect \$13 $not$libresoc.v:181702$11782_Y - connect \$15 $or$libresoc.v:181703$11783_Y - connect \$1 $not$libresoc.v:181704$11784_Y - connect \$3 $and$libresoc.v:181705$11785_Y - connect \$5 $or$libresoc.v:181706$11786_Y - connect \$7 $not$libresoc.v:181707$11787_Y + connect \$9 $and$libresoc.v:184004$11964_Y + connect \$11 $or$libresoc.v:184005$11965_Y + connect \$13 $not$libresoc.v:184006$11966_Y + connect \$15 $or$libresoc.v:184007$11967_Y + connect \$1 $not$libresoc.v:184008$11968_Y + connect \$3 $and$libresoc.v:184009$11969_Y + connect \$5 $or$libresoc.v:184010$11970_Y + connect \$7 $not$libresoc.v:184011$11971_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181726.1-181784.10" +attribute \src "libresoc.v:184030.1-184088.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:181727.7-181727.20" + attribute \src "libresoc.v:184031.7-184031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181772.3-181780.6" - wire width 2 $0\q_int$next[1:0]$11804 - attribute \src "libresoc.v:181770.3-181771.27" + attribute \src "libresoc.v:184076.3-184084.6" + wire width 2 $0\q_int$next[1:0]$11988 + attribute \src "libresoc.v:184074.3-184075.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:181772.3-181780.6" - wire width 2 $1\q_int$next[1:0]$11805 - attribute \src "libresoc.v:181749.13-181749.25" + attribute \src "libresoc.v:184076.3-184084.6" + wire width 2 $1\q_int$next[1:0]$11989 + attribute \src "libresoc.v:184053.13-184053.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:181762.17-181762.96" - wire width 2 $and$libresoc.v:181762$11794_Y - attribute \src "libresoc.v:181767.17-181767.96" - wire width 2 $and$libresoc.v:181767$11799_Y - attribute \src "libresoc.v:181764.18-181764.93" - wire width 2 $not$libresoc.v:181764$11796_Y - attribute \src "libresoc.v:181766.17-181766.92" - wire width 2 $not$libresoc.v:181766$11798_Y - attribute \src "libresoc.v:181769.17-181769.92" - wire width 2 $not$libresoc.v:181769$11801_Y - attribute \src "libresoc.v:181763.18-181763.98" - wire width 2 $or$libresoc.v:181763$11795_Y - attribute \src "libresoc.v:181765.18-181765.99" - wire width 2 $or$libresoc.v:181765$11797_Y - attribute \src "libresoc.v:181768.17-181768.97" - wire width 2 $or$libresoc.v:181768$11800_Y + attribute \src "libresoc.v:184066.17-184066.96" + wire width 2 $and$libresoc.v:184066$11978_Y + attribute \src "libresoc.v:184071.17-184071.96" + wire width 2 $and$libresoc.v:184071$11983_Y + attribute \src "libresoc.v:184068.18-184068.93" + wire width 2 $not$libresoc.v:184068$11980_Y + attribute \src "libresoc.v:184070.17-184070.92" + wire width 2 $not$libresoc.v:184070$11982_Y + attribute \src "libresoc.v:184073.17-184073.92" + wire width 2 $not$libresoc.v:184073$11985_Y + attribute \src "libresoc.v:184067.18-184067.98" + wire width 2 $or$libresoc.v:184067$11979_Y + attribute \src "libresoc.v:184069.18-184069.99" + wire width 2 $or$libresoc.v:184069$11981_Y + attribute \src "libresoc.v:184072.17-184072.97" + wire width 2 $or$libresoc.v:184072$11984_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375407,11 +379416,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181727.7-181727.15" + attribute \src "libresoc.v:184031.7-184031.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -375428,7 +379437,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181762$11794 + cell $and $and$libresoc.v:184066$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375436,10 +379445,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181762$11794_Y + connect \Y $and$libresoc.v:184066$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181767$11799 + cell $and $and$libresoc.v:184071$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375447,34 +379456,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181767$11799_Y + connect \Y $and$libresoc.v:184071$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181764$11796 + cell $not $not$libresoc.v:184068$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:181764$11796_Y + connect \Y $not$libresoc.v:184068$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181766$11798 + cell $not $not$libresoc.v:184070$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:181766$11798_Y + connect \Y $not$libresoc.v:184070$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181769$11801 + cell $not $not$libresoc.v:184073$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:181769$11801_Y + connect \Y $not$libresoc.v:184073$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181763$11795 + cell $or $or$libresoc.v:184067$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375482,10 +379491,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181763$11795_Y + connect \Y $or$libresoc.v:184067$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181765$11797 + cell $or $or$libresoc.v:184069$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375493,10 +379502,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181765$11797_Y + connect \Y $or$libresoc.v:184069$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181768$11800 + cell $or $or$libresoc.v:184072$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -375504,39 +379513,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181768$11800_Y + connect \Y $or$libresoc.v:184072$11984_Y end - attribute \src "libresoc.v:181727.7-181727.20" - process $proc$libresoc.v:181727$11806 + attribute \src "libresoc.v:184031.7-184031.20" + process $proc$libresoc.v:184031$11990 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181749.13-181749.25" - process $proc$libresoc.v:181749$11807 + attribute \src "libresoc.v:184053.13-184053.25" + process $proc$libresoc.v:184053$11991 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:181770.3-181771.27" - process $proc$libresoc.v:181770$11802 + attribute \src "libresoc.v:184074.3-184075.27" + process $proc$libresoc.v:184074$11986 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:181772.3-181780.6" - process $proc$libresoc.v:181772$11803 + attribute \src "libresoc.v:184076.3-184084.6" + process $proc$libresoc.v:184076$11987 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11804 $1\q_int$next[1:0]$11805 - attribute \src "libresoc.v:181773.5-181773.29" + assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 + attribute \src "libresoc.v:184077.5-184077.29" switch \initial - attribute \src "libresoc.v:181773.9-181773.17" + attribute \src "libresoc.v:184077.9-184077.17" case 1'1 case end @@ -375545,56 +379554,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11805 2'00 + assign $1\q_int$next[1:0]$11989 2'00 case - assign $1\q_int$next[1:0]$11805 \$5 + assign $1\q_int$next[1:0]$11989 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11804 + update \q_int$next $0\q_int$next[1:0]$11988 end - connect \$9 $and$libresoc.v:181762$11794_Y - connect \$11 $or$libresoc.v:181763$11795_Y - connect \$13 $not$libresoc.v:181764$11796_Y - connect \$15 $or$libresoc.v:181765$11797_Y - connect \$1 $not$libresoc.v:181766$11798_Y - connect \$3 $and$libresoc.v:181767$11799_Y - connect \$5 $or$libresoc.v:181768$11800_Y - connect \$7 $not$libresoc.v:181769$11801_Y + connect \$9 $and$libresoc.v:184066$11978_Y + connect \$11 $or$libresoc.v:184067$11979_Y + connect \$13 $not$libresoc.v:184068$11980_Y + connect \$15 $or$libresoc.v:184069$11981_Y + connect \$1 $not$libresoc.v:184070$11982_Y + connect \$3 $and$libresoc.v:184071$11983_Y + connect \$5 $or$libresoc.v:184072$11984_Y + connect \$7 $not$libresoc.v:184073$11985_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181788.1-181846.10" +attribute \src "libresoc.v:184092.1-184150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:181789.7-181789.20" + attribute \src "libresoc.v:184093.7-184093.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181834.3-181842.6" - wire width 6 $0\q_int$next[5:0]$11818 - attribute \src "libresoc.v:181832.3-181833.27" + attribute \src "libresoc.v:184138.3-184146.6" + wire width 6 $0\q_int$next[5:0]$12002 + attribute \src "libresoc.v:184136.3-184137.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:181834.3-181842.6" - wire width 6 $1\q_int$next[5:0]$11819 - attribute \src "libresoc.v:181811.13-181811.26" + attribute \src "libresoc.v:184138.3-184146.6" + wire width 6 $1\q_int$next[5:0]$12003 + attribute \src "libresoc.v:184115.13-184115.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:181824.17-181824.96" - wire width 6 $and$libresoc.v:181824$11808_Y - attribute \src "libresoc.v:181829.17-181829.96" - wire width 6 $and$libresoc.v:181829$11813_Y - attribute \src "libresoc.v:181826.18-181826.93" - wire width 6 $not$libresoc.v:181826$11810_Y - attribute \src "libresoc.v:181828.17-181828.92" - wire width 6 $not$libresoc.v:181828$11812_Y - attribute \src "libresoc.v:181831.17-181831.92" - wire width 6 $not$libresoc.v:181831$11815_Y - attribute \src "libresoc.v:181825.18-181825.98" - wire width 6 $or$libresoc.v:181825$11809_Y - attribute \src "libresoc.v:181827.18-181827.99" - wire width 6 $or$libresoc.v:181827$11811_Y - attribute \src "libresoc.v:181830.17-181830.97" - wire width 6 $or$libresoc.v:181830$11814_Y + attribute \src "libresoc.v:184128.17-184128.96" + wire width 6 $and$libresoc.v:184128$11992_Y + attribute \src "libresoc.v:184133.17-184133.96" + wire width 6 $and$libresoc.v:184133$11997_Y + attribute \src "libresoc.v:184130.18-184130.93" + wire width 6 $not$libresoc.v:184130$11994_Y + attribute \src "libresoc.v:184132.17-184132.92" + wire width 6 $not$libresoc.v:184132$11996_Y + attribute \src "libresoc.v:184135.17-184135.92" + wire width 6 $not$libresoc.v:184135$11999_Y + attribute \src "libresoc.v:184129.18-184129.98" + wire width 6 $or$libresoc.v:184129$11993_Y + attribute \src "libresoc.v:184131.18-184131.99" + wire width 6 $or$libresoc.v:184131$11995_Y + attribute \src "libresoc.v:184134.17-184134.97" + wire width 6 $or$libresoc.v:184134$11998_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375611,11 +379620,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181789.7-181789.15" + attribute \src "libresoc.v:184093.7-184093.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -375632,7 +379641,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181824$11808 + cell $and $and$libresoc.v:184128$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375640,10 +379649,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181824$11808_Y + connect \Y $and$libresoc.v:184128$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181829$11813 + cell $and $and$libresoc.v:184133$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375651,34 +379660,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181829$11813_Y + connect \Y $and$libresoc.v:184133$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181826$11810 + cell $not $not$libresoc.v:184130$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:181826$11810_Y + connect \Y $not$libresoc.v:184130$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181828$11812 + cell $not $not$libresoc.v:184132$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:181828$11812_Y + connect \Y $not$libresoc.v:184132$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181831$11815 + cell $not $not$libresoc.v:184135$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:181831$11815_Y + connect \Y $not$libresoc.v:184135$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181825$11809 + cell $or $or$libresoc.v:184129$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375686,10 +379695,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181825$11809_Y + connect \Y $or$libresoc.v:184129$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181827$11811 + cell $or $or$libresoc.v:184131$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375697,10 +379706,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181827$11811_Y + connect \Y $or$libresoc.v:184131$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181830$11814 + cell $or $or$libresoc.v:184134$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -375708,39 +379717,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181830$11814_Y + connect \Y $or$libresoc.v:184134$11998_Y end - attribute \src "libresoc.v:181789.7-181789.20" - process $proc$libresoc.v:181789$11820 + attribute \src "libresoc.v:184093.7-184093.20" + process $proc$libresoc.v:184093$12004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181811.13-181811.26" - process $proc$libresoc.v:181811$11821 + attribute \src "libresoc.v:184115.13-184115.26" + process $proc$libresoc.v:184115$12005 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:181832.3-181833.27" - process $proc$libresoc.v:181832$11816 + attribute \src "libresoc.v:184136.3-184137.27" + process $proc$libresoc.v:184136$12000 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:181834.3-181842.6" - process $proc$libresoc.v:181834$11817 + attribute \src "libresoc.v:184138.3-184146.6" + process $proc$libresoc.v:184138$12001 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11818 $1\q_int$next[5:0]$11819 - attribute \src "libresoc.v:181835.5-181835.29" + assign $0\q_int$next[5:0]$12002 $1\q_int$next[5:0]$12003 + attribute \src "libresoc.v:184139.5-184139.29" switch \initial - attribute \src "libresoc.v:181835.9-181835.17" + attribute \src "libresoc.v:184139.9-184139.17" case 1'1 case end @@ -375749,56 +379758,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11819 6'000000 + assign $1\q_int$next[5:0]$12003 6'000000 case - assign $1\q_int$next[5:0]$11819 \$5 + assign $1\q_int$next[5:0]$12003 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11818 + update \q_int$next $0\q_int$next[5:0]$12002 end - connect \$9 $and$libresoc.v:181824$11808_Y - connect \$11 $or$libresoc.v:181825$11809_Y - connect \$13 $not$libresoc.v:181826$11810_Y - connect \$15 $or$libresoc.v:181827$11811_Y - connect \$1 $not$libresoc.v:181828$11812_Y - connect \$3 $and$libresoc.v:181829$11813_Y - connect \$5 $or$libresoc.v:181830$11814_Y - connect \$7 $not$libresoc.v:181831$11815_Y + connect \$9 $and$libresoc.v:184128$11992_Y + connect \$11 $or$libresoc.v:184129$11993_Y + connect \$13 $not$libresoc.v:184130$11994_Y + connect \$15 $or$libresoc.v:184131$11995_Y + connect \$1 $not$libresoc.v:184132$11996_Y + connect \$3 $and$libresoc.v:184133$11997_Y + connect \$5 $or$libresoc.v:184134$11998_Y + connect \$7 $not$libresoc.v:184135$11999_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181850.1-181908.10" +attribute \src "libresoc.v:184154.1-184212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:181851.7-181851.20" + attribute \src "libresoc.v:184155.7-184155.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181896.3-181904.6" - wire width 4 $0\q_int$next[3:0]$11832 - attribute \src "libresoc.v:181894.3-181895.27" + attribute \src "libresoc.v:184200.3-184208.6" + wire width 4 $0\q_int$next[3:0]$12016 + attribute \src "libresoc.v:184198.3-184199.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181896.3-181904.6" - wire width 4 $1\q_int$next[3:0]$11833 - attribute \src "libresoc.v:181873.13-181873.25" + attribute \src "libresoc.v:184200.3-184208.6" + wire width 4 $1\q_int$next[3:0]$12017 + attribute \src "libresoc.v:184177.13-184177.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181886.17-181886.96" - wire width 4 $and$libresoc.v:181886$11822_Y - attribute \src "libresoc.v:181891.17-181891.96" - wire width 4 $and$libresoc.v:181891$11827_Y - attribute \src "libresoc.v:181888.18-181888.93" - wire width 4 $not$libresoc.v:181888$11824_Y - attribute \src "libresoc.v:181890.17-181890.92" - wire width 4 $not$libresoc.v:181890$11826_Y - attribute \src "libresoc.v:181893.17-181893.92" - wire width 4 $not$libresoc.v:181893$11829_Y - attribute \src "libresoc.v:181887.18-181887.98" - wire width 4 $or$libresoc.v:181887$11823_Y - attribute \src "libresoc.v:181889.18-181889.99" - wire width 4 $or$libresoc.v:181889$11825_Y - attribute \src "libresoc.v:181892.17-181892.97" - wire width 4 $or$libresoc.v:181892$11828_Y + attribute \src "libresoc.v:184190.17-184190.96" + wire width 4 $and$libresoc.v:184190$12006_Y + attribute \src "libresoc.v:184195.17-184195.96" + wire width 4 $and$libresoc.v:184195$12011_Y + attribute \src "libresoc.v:184192.18-184192.93" + wire width 4 $not$libresoc.v:184192$12008_Y + attribute \src "libresoc.v:184194.17-184194.92" + wire width 4 $not$libresoc.v:184194$12010_Y + attribute \src "libresoc.v:184197.17-184197.92" + wire width 4 $not$libresoc.v:184197$12013_Y + attribute \src "libresoc.v:184191.18-184191.98" + wire width 4 $or$libresoc.v:184191$12007_Y + attribute \src "libresoc.v:184193.18-184193.99" + wire width 4 $or$libresoc.v:184193$12009_Y + attribute \src "libresoc.v:184196.17-184196.97" + wire width 4 $or$libresoc.v:184196$12012_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375815,11 +379824,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181851.7-181851.15" + attribute \src "libresoc.v:184155.7-184155.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -375836,7 +379845,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:181886$11822 + cell $and $and$libresoc.v:184190$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375844,10 +379853,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:181886$11822_Y + connect \Y $and$libresoc.v:184190$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181891$11827 + cell $and $and$libresoc.v:184195$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375855,34 +379864,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181891$11827_Y + connect \Y $and$libresoc.v:184195$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181888$11824 + cell $not $not$libresoc.v:184192$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:181888$11824_Y + connect \Y $not$libresoc.v:184192$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181890$11826 + cell $not $not$libresoc.v:184194$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181890$11826_Y + connect \Y $not$libresoc.v:184194$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:181893$11829 + cell $not $not$libresoc.v:184197$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:181893$11829_Y + connect \Y $not$libresoc.v:184197$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:181887$11823 + cell $or $or$libresoc.v:184191$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375890,10 +379899,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:181887$11823_Y + connect \Y $or$libresoc.v:184191$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181889$11825 + cell $or $or$libresoc.v:184193$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375901,10 +379910,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:181889$11825_Y + connect \Y $or$libresoc.v:184193$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181892$11828 + cell $or $or$libresoc.v:184196$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375912,39 +379921,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:181892$11828_Y + connect \Y $or$libresoc.v:184196$12012_Y end - attribute \src "libresoc.v:181851.7-181851.20" - process $proc$libresoc.v:181851$11834 + attribute \src "libresoc.v:184155.7-184155.20" + process $proc$libresoc.v:184155$12018 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181873.13-181873.25" - process $proc$libresoc.v:181873$11835 + attribute \src "libresoc.v:184177.13-184177.25" + process $proc$libresoc.v:184177$12019 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:181894.3-181895.27" - process $proc$libresoc.v:181894$11830 + attribute \src "libresoc.v:184198.3-184199.27" + process $proc$libresoc.v:184198$12014 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:181896.3-181904.6" - process $proc$libresoc.v:181896$11831 + attribute \src "libresoc.v:184200.3-184208.6" + process $proc$libresoc.v:184200$12015 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11832 $1\q_int$next[3:0]$11833 - attribute \src "libresoc.v:181897.5-181897.29" + assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 + attribute \src "libresoc.v:184201.5-184201.29" switch \initial - attribute \src "libresoc.v:181897.9-181897.17" + attribute \src "libresoc.v:184201.9-184201.17" case 1'1 case end @@ -375953,50 +379962,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11833 4'0000 + assign $1\q_int$next[3:0]$12017 4'0000 case - assign $1\q_int$next[3:0]$11833 \$5 + assign $1\q_int$next[3:0]$12017 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11832 + update \q_int$next $0\q_int$next[3:0]$12016 end - connect \$9 $and$libresoc.v:181886$11822_Y - connect \$11 $or$libresoc.v:181887$11823_Y - connect \$13 $not$libresoc.v:181888$11824_Y - connect \$15 $or$libresoc.v:181889$11825_Y - connect \$1 $not$libresoc.v:181890$11826_Y - connect \$3 $and$libresoc.v:181891$11827_Y - connect \$5 $or$libresoc.v:181892$11828_Y - connect \$7 $not$libresoc.v:181893$11829_Y + connect \$9 $and$libresoc.v:184190$12006_Y + connect \$11 $or$libresoc.v:184191$12007_Y + connect \$13 $not$libresoc.v:184192$12008_Y + connect \$15 $or$libresoc.v:184193$12009_Y + connect \$1 $not$libresoc.v:184194$12010_Y + connect \$3 $and$libresoc.v:184195$12011_Y + connect \$5 $or$libresoc.v:184196$12012_Y + connect \$7 $not$libresoc.v:184197$12013_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:181912.1-181961.10" +attribute \src "libresoc.v:184216.1-184265.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:181913.7-181913.20" + attribute \src "libresoc.v:184217.7-184217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181949.3-181957.6" - wire $0\q_int$next[0:0]$11843 - attribute \src "libresoc.v:181947.3-181948.27" + attribute \src "libresoc.v:184253.3-184261.6" + wire $0\q_int$next[0:0]$12027 + attribute \src "libresoc.v:184251.3-184252.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:181949.3-181957.6" - wire $1\q_int$next[0:0]$11844 - attribute \src "libresoc.v:181929.7-181929.19" + attribute \src "libresoc.v:184253.3-184261.6" + wire $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184233.7-184233.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181944.17-181944.96" - wire $and$libresoc.v:181944$11838_Y - attribute \src "libresoc.v:181943.17-181943.94" - wire $not$libresoc.v:181943$11837_Y - attribute \src "libresoc.v:181946.17-181946.94" - wire $not$libresoc.v:181946$11840_Y - attribute \src "libresoc.v:181942.17-181942.100" - wire $or$libresoc.v:181942$11836_Y - attribute \src "libresoc.v:181945.17-181945.99" - wire $or$libresoc.v:181945$11839_Y + attribute \src "libresoc.v:184248.17-184248.96" + wire $and$libresoc.v:184248$12022_Y + attribute \src "libresoc.v:184247.17-184247.94" + wire $not$libresoc.v:184247$12021_Y + attribute \src "libresoc.v:184250.17-184250.94" + wire $not$libresoc.v:184250$12024_Y + attribute \src "libresoc.v:184246.17-184246.100" + wire $or$libresoc.v:184246$12020_Y + attribute \src "libresoc.v:184249.17-184249.99" + wire $or$libresoc.v:184249$12023_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -376007,11 +380016,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181913.7-181913.15" + attribute \src "libresoc.v:184217.7-184217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376028,7 +380037,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181944$11838 + cell $and $and$libresoc.v:184248$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376036,26 +380045,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181944$11838_Y + connect \Y $and$libresoc.v:184248$12022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181943$11837 + cell $not $not$libresoc.v:184247$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:181943$11837_Y + connect \Y $not$libresoc.v:184247$12021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181946$11840 + cell $not $not$libresoc.v:184250$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:181946$11840_Y + connect \Y $not$libresoc.v:184250$12024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181942$11836 + cell $or $or$libresoc.v:184246$12020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376063,10 +380072,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:181942$11836_Y + connect \Y $or$libresoc.v:184246$12020_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181945$11839 + cell $or $or$libresoc.v:184249$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376074,39 +380083,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:181945$11839_Y + connect \Y $or$libresoc.v:184249$12023_Y end - attribute \src "libresoc.v:181913.7-181913.20" - process $proc$libresoc.v:181913$11845 + attribute \src "libresoc.v:184217.7-184217.20" + process $proc$libresoc.v:184217$12029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181929.7-181929.19" - process $proc$libresoc.v:181929$11846 + attribute \src "libresoc.v:184233.7-184233.19" + process $proc$libresoc.v:184233$12030 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:181947.3-181948.27" - process $proc$libresoc.v:181947$11841 + attribute \src "libresoc.v:184251.3-184252.27" + process $proc$libresoc.v:184251$12025 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:181949.3-181957.6" - process $proc$libresoc.v:181949$11842 + attribute \src "libresoc.v:184253.3-184261.6" + process $proc$libresoc.v:184253$12026 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11843 $1\q_int$next[0:0]$11844 - attribute \src "libresoc.v:181950.5-181950.29" + assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 + attribute \src "libresoc.v:184254.5-184254.29" switch \initial - attribute \src "libresoc.v:181950.9-181950.17" + attribute \src "libresoc.v:184254.9-184254.17" case 1'1 case end @@ -376115,47 +380124,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11844 1'0 + assign $1\q_int$next[0:0]$12028 1'0 case - assign $1\q_int$next[0:0]$11844 \$5 + assign $1\q_int$next[0:0]$12028 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11843 + update \q_int$next $0\q_int$next[0:0]$12027 end - connect \$9 $or$libresoc.v:181942$11836_Y - connect \$1 $not$libresoc.v:181943$11837_Y - connect \$3 $and$libresoc.v:181944$11838_Y - connect \$5 $or$libresoc.v:181945$11839_Y - connect \$7 $not$libresoc.v:181946$11840_Y + connect \$9 $or$libresoc.v:184246$12020_Y + connect \$1 $not$libresoc.v:184247$12021_Y + connect \$3 $and$libresoc.v:184248$12022_Y + connect \$5 $or$libresoc.v:184249$12023_Y + connect \$7 $not$libresoc.v:184250$12024_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:181965.1-182014.10" +attribute \src "libresoc.v:184269.1-184318.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:181966.7-181966.20" + attribute \src "libresoc.v:184270.7-184270.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182002.3-182010.6" - wire $0\q_int$next[0:0]$11854 - attribute \src "libresoc.v:182000.3-182001.27" + attribute \src "libresoc.v:184306.3-184314.6" + wire $0\q_int$next[0:0]$12038 + attribute \src "libresoc.v:184304.3-184305.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182002.3-182010.6" - wire $1\q_int$next[0:0]$11855 - attribute \src "libresoc.v:181982.7-181982.19" + attribute \src "libresoc.v:184306.3-184314.6" + wire $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184286.7-184286.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:181997.17-181997.96" - wire $and$libresoc.v:181997$11849_Y - attribute \src "libresoc.v:181996.17-181996.94" - wire $not$libresoc.v:181996$11848_Y - attribute \src "libresoc.v:181999.17-181999.94" - wire $not$libresoc.v:181999$11851_Y - attribute \src "libresoc.v:181995.17-181995.100" - wire $or$libresoc.v:181995$11847_Y - attribute \src "libresoc.v:181998.17-181998.99" - wire $or$libresoc.v:181998$11850_Y + attribute \src "libresoc.v:184301.17-184301.96" + wire $and$libresoc.v:184301$12033_Y + attribute \src "libresoc.v:184300.17-184300.94" + wire $not$libresoc.v:184300$12032_Y + attribute \src "libresoc.v:184303.17-184303.94" + wire $not$libresoc.v:184303$12035_Y + attribute \src "libresoc.v:184299.17-184299.100" + wire $or$libresoc.v:184299$12031_Y + attribute \src "libresoc.v:184302.17-184302.99" + wire $or$libresoc.v:184302$12034_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -376166,11 +380175,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:181966.7-181966.15" + attribute \src "libresoc.v:184270.7-184270.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376187,7 +380196,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:181997$11849 + cell $and $and$libresoc.v:184301$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376195,26 +380204,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:181997$11849_Y + connect \Y $and$libresoc.v:184301$12033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:181996$11848 + cell $not $not$libresoc.v:184300$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:181996$11848_Y + connect \Y $not$libresoc.v:184300$12032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:181999$11851 + cell $not $not$libresoc.v:184303$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:181999$11851_Y + connect \Y $not$libresoc.v:184303$12035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:181995$11847 + cell $or $or$libresoc.v:184299$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376222,10 +380231,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:181995$11847_Y + connect \Y $or$libresoc.v:184299$12031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:181998$11850 + cell $or $or$libresoc.v:184302$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376233,39 +380242,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:181998$11850_Y + connect \Y $or$libresoc.v:184302$12034_Y end - attribute \src "libresoc.v:181966.7-181966.20" - process $proc$libresoc.v:181966$11856 + attribute \src "libresoc.v:184270.7-184270.20" + process $proc$libresoc.v:184270$12040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181982.7-181982.19" - process $proc$libresoc.v:181982$11857 + attribute \src "libresoc.v:184286.7-184286.19" + process $proc$libresoc.v:184286$12041 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182000.3-182001.27" - process $proc$libresoc.v:182000$11852 + attribute \src "libresoc.v:184304.3-184305.27" + process $proc$libresoc.v:184304$12036 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182002.3-182010.6" - process $proc$libresoc.v:182002$11853 + attribute \src "libresoc.v:184306.3-184314.6" + process $proc$libresoc.v:184306$12037 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11854 $1\q_int$next[0:0]$11855 - attribute \src "libresoc.v:182003.5-182003.29" + assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 + attribute \src "libresoc.v:184307.5-184307.29" switch \initial - attribute \src "libresoc.v:182003.9-182003.17" + attribute \src "libresoc.v:184307.9-184307.17" case 1'1 case end @@ -376274,287 +380283,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11855 1'0 + assign $1\q_int$next[0:0]$12039 1'0 case - assign $1\q_int$next[0:0]$11855 \$5 + assign $1\q_int$next[0:0]$12039 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11854 + update \q_int$next $0\q_int$next[0:0]$12038 end - connect \$9 $or$libresoc.v:181995$11847_Y - connect \$1 $not$libresoc.v:181996$11848_Y - connect \$3 $and$libresoc.v:181997$11849_Y - connect \$5 $or$libresoc.v:181998$11850_Y - connect \$7 $not$libresoc.v:181999$11851_Y + connect \$9 $or$libresoc.v:184299$12031_Y + connect \$1 $not$libresoc.v:184300$12032_Y + connect \$3 $and$libresoc.v:184301$12033_Y + connect \$5 $or$libresoc.v:184302$12034_Y + connect \$7 $not$libresoc.v:184303$12035_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:182018.1-182605.10" +attribute \src "libresoc.v:184322.1-184909.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:182019.7-182019.20" + attribute \src "libresoc.v:184323.7-184323.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $10\mask[9:9] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $11\mask[10:10] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $12\mask[11:11] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $13\mask[12:12] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $14\mask[13:13] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $15\mask[14:14] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $16\mask[15:15] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $17\mask[16:16] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $18\mask[17:17] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $19\mask[18:18] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $1\mask[0:0] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $20\mask[19:19] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $21\mask[20:20] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $22\mask[21:21] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $23\mask[22:22] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $24\mask[23:23] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $25\mask[24:24] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $26\mask[25:25] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $27\mask[26:26] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $28\mask[27:27] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $29\mask[28:28] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $2\mask[1:1] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $30\mask[29:29] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $31\mask[30:30] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $32\mask[31:31] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $33\mask[32:32] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $34\mask[33:33] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $35\mask[34:34] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $36\mask[35:35] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $37\mask[36:36] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $38\mask[37:37] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $39\mask[38:38] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $3\mask[2:2] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $40\mask[39:39] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $41\mask[40:40] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $42\mask[41:41] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $43\mask[42:42] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $44\mask[43:43] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $45\mask[44:44] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $46\mask[45:45] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $47\mask[46:46] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $48\mask[47:47] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $49\mask[48:48] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $4\mask[3:3] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $50\mask[49:49] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $51\mask[50:50] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $52\mask[51:51] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $53\mask[52:52] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $54\mask[53:53] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $55\mask[54:54] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $56\mask[55:55] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $57\mask[56:56] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $58\mask[57:57] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $59\mask[58:58] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $5\mask[4:4] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $60\mask[59:59] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $61\mask[60:60] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $62\mask[61:61] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $63\mask[62:62] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $64\mask[63:63] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $6\mask[5:5] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $7\mask[6:6] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $8\mask[7:7] - attribute \src "libresoc.v:182217.3-182604.6" + attribute \src "libresoc.v:184521.3-184908.6" wire $9\mask[8:8] - attribute \src "libresoc.v:182153.17-182153.96" - wire $gt$libresoc.v:182153$11858_Y - attribute \src "libresoc.v:182154.18-182154.98" - wire $gt$libresoc.v:182154$11859_Y - attribute \src "libresoc.v:182155.19-182155.99" - wire $gt$libresoc.v:182155$11860_Y - attribute \src "libresoc.v:182156.19-182156.99" - wire $gt$libresoc.v:182156$11861_Y - attribute \src "libresoc.v:182157.19-182157.99" - wire $gt$libresoc.v:182157$11862_Y - attribute \src "libresoc.v:182158.19-182158.99" - wire $gt$libresoc.v:182158$11863_Y - attribute \src "libresoc.v:182159.19-182159.99" - wire $gt$libresoc.v:182159$11864_Y - attribute \src "libresoc.v:182160.19-182160.99" - wire $gt$libresoc.v:182160$11865_Y - attribute \src "libresoc.v:182161.19-182161.99" - wire $gt$libresoc.v:182161$11866_Y - attribute \src "libresoc.v:182162.19-182162.99" - wire $gt$libresoc.v:182162$11867_Y - attribute \src "libresoc.v:182163.19-182163.99" - wire $gt$libresoc.v:182163$11868_Y - attribute \src "libresoc.v:182164.18-182164.97" - wire $gt$libresoc.v:182164$11869_Y - attribute \src "libresoc.v:182165.19-182165.99" - wire $gt$libresoc.v:182165$11870_Y - attribute \src "libresoc.v:182166.19-182166.99" - wire $gt$libresoc.v:182166$11871_Y - attribute \src "libresoc.v:182167.19-182167.99" - wire $gt$libresoc.v:182167$11872_Y - attribute \src "libresoc.v:182168.19-182168.99" - wire $gt$libresoc.v:182168$11873_Y - attribute \src "libresoc.v:182169.19-182169.99" - wire $gt$libresoc.v:182169$11874_Y - attribute \src "libresoc.v:182170.18-182170.97" - wire $gt$libresoc.v:182170$11875_Y - attribute \src "libresoc.v:182171.18-182171.97" - wire $gt$libresoc.v:182171$11876_Y - attribute \src "libresoc.v:182172.18-182172.97" - wire $gt$libresoc.v:182172$11877_Y - attribute \src "libresoc.v:182173.17-182173.96" - wire $gt$libresoc.v:182173$11878_Y - attribute \src "libresoc.v:182174.18-182174.97" - wire $gt$libresoc.v:182174$11879_Y - attribute \src "libresoc.v:182175.18-182175.97" - wire $gt$libresoc.v:182175$11880_Y - attribute \src "libresoc.v:182176.18-182176.97" - wire $gt$libresoc.v:182176$11881_Y - attribute \src "libresoc.v:182177.18-182177.97" - wire $gt$libresoc.v:182177$11882_Y - attribute \src "libresoc.v:182178.18-182178.97" - wire $gt$libresoc.v:182178$11883_Y - attribute \src "libresoc.v:182179.18-182179.97" - wire $gt$libresoc.v:182179$11884_Y - attribute \src "libresoc.v:182180.18-182180.97" - wire $gt$libresoc.v:182180$11885_Y - attribute \src "libresoc.v:182181.18-182181.98" - wire $gt$libresoc.v:182181$11886_Y - attribute \src "libresoc.v:182182.18-182182.98" - wire $gt$libresoc.v:182182$11887_Y - attribute \src "libresoc.v:182183.18-182183.98" - wire $gt$libresoc.v:182183$11888_Y - attribute \src "libresoc.v:182184.17-182184.96" - wire $gt$libresoc.v:182184$11889_Y - attribute \src "libresoc.v:182185.18-182185.98" - wire $gt$libresoc.v:182185$11890_Y - attribute \src "libresoc.v:182186.18-182186.98" - wire $gt$libresoc.v:182186$11891_Y - attribute \src "libresoc.v:182187.18-182187.98" - wire $gt$libresoc.v:182187$11892_Y - attribute \src "libresoc.v:182188.18-182188.98" - wire $gt$libresoc.v:182188$11893_Y - attribute \src "libresoc.v:182189.18-182189.98" - wire $gt$libresoc.v:182189$11894_Y - attribute \src "libresoc.v:182190.18-182190.98" - wire $gt$libresoc.v:182190$11895_Y - attribute \src "libresoc.v:182191.18-182191.98" - wire $gt$libresoc.v:182191$11896_Y - attribute \src "libresoc.v:182192.18-182192.98" - wire $gt$libresoc.v:182192$11897_Y - attribute \src "libresoc.v:182193.18-182193.98" - wire $gt$libresoc.v:182193$11898_Y - attribute \src "libresoc.v:182194.18-182194.98" - wire $gt$libresoc.v:182194$11899_Y - attribute \src "libresoc.v:182195.17-182195.96" - wire $gt$libresoc.v:182195$11900_Y - attribute \src "libresoc.v:182196.18-182196.98" - wire $gt$libresoc.v:182196$11901_Y - attribute \src "libresoc.v:182197.18-182197.98" - wire $gt$libresoc.v:182197$11902_Y - attribute \src "libresoc.v:182198.18-182198.98" - wire $gt$libresoc.v:182198$11903_Y - attribute \src "libresoc.v:182199.18-182199.98" - wire $gt$libresoc.v:182199$11904_Y - attribute \src "libresoc.v:182200.18-182200.98" - wire $gt$libresoc.v:182200$11905_Y - attribute \src "libresoc.v:182201.18-182201.98" - wire $gt$libresoc.v:182201$11906_Y - attribute \src "libresoc.v:182202.18-182202.98" - wire $gt$libresoc.v:182202$11907_Y - attribute \src "libresoc.v:182203.18-182203.98" - wire $gt$libresoc.v:182203$11908_Y - attribute \src "libresoc.v:182204.18-182204.98" - wire $gt$libresoc.v:182204$11909_Y - attribute \src "libresoc.v:182205.18-182205.98" - wire $gt$libresoc.v:182205$11910_Y - attribute \src "libresoc.v:182206.17-182206.96" - wire $gt$libresoc.v:182206$11911_Y - attribute \src "libresoc.v:182207.18-182207.98" - wire $gt$libresoc.v:182207$11912_Y - attribute \src "libresoc.v:182208.18-182208.98" - wire $gt$libresoc.v:182208$11913_Y - attribute \src "libresoc.v:182209.18-182209.98" - wire $gt$libresoc.v:182209$11914_Y - attribute \src "libresoc.v:182210.18-182210.98" - wire $gt$libresoc.v:182210$11915_Y - attribute \src "libresoc.v:182211.18-182211.98" - wire $gt$libresoc.v:182211$11916_Y - attribute \src "libresoc.v:182212.18-182212.98" - wire $gt$libresoc.v:182212$11917_Y - attribute \src "libresoc.v:182213.18-182213.98" - wire $gt$libresoc.v:182213$11918_Y - attribute \src "libresoc.v:182214.18-182214.98" - wire $gt$libresoc.v:182214$11919_Y - attribute \src "libresoc.v:182215.18-182215.98" - wire $gt$libresoc.v:182215$11920_Y - attribute \src "libresoc.v:182216.18-182216.98" - wire $gt$libresoc.v:182216$11921_Y + attribute \src "libresoc.v:184457.17-184457.96" + wire $gt$libresoc.v:184457$12042_Y + attribute \src "libresoc.v:184458.18-184458.98" + wire $gt$libresoc.v:184458$12043_Y + attribute \src "libresoc.v:184459.19-184459.99" + wire $gt$libresoc.v:184459$12044_Y + attribute \src "libresoc.v:184460.19-184460.99" + wire $gt$libresoc.v:184460$12045_Y + attribute \src "libresoc.v:184461.19-184461.99" + wire $gt$libresoc.v:184461$12046_Y + attribute \src "libresoc.v:184462.19-184462.99" + wire $gt$libresoc.v:184462$12047_Y + attribute \src "libresoc.v:184463.19-184463.99" + wire $gt$libresoc.v:184463$12048_Y + attribute \src "libresoc.v:184464.19-184464.99" + wire $gt$libresoc.v:184464$12049_Y + attribute \src "libresoc.v:184465.19-184465.99" + wire $gt$libresoc.v:184465$12050_Y + attribute \src "libresoc.v:184466.19-184466.99" + wire $gt$libresoc.v:184466$12051_Y + attribute \src "libresoc.v:184467.19-184467.99" + wire $gt$libresoc.v:184467$12052_Y + attribute \src "libresoc.v:184468.18-184468.97" + wire $gt$libresoc.v:184468$12053_Y + attribute \src "libresoc.v:184469.19-184469.99" + wire $gt$libresoc.v:184469$12054_Y + attribute \src "libresoc.v:184470.19-184470.99" + wire $gt$libresoc.v:184470$12055_Y + attribute \src "libresoc.v:184471.19-184471.99" + wire $gt$libresoc.v:184471$12056_Y + attribute \src "libresoc.v:184472.19-184472.99" + wire $gt$libresoc.v:184472$12057_Y + attribute \src "libresoc.v:184473.19-184473.99" + wire $gt$libresoc.v:184473$12058_Y + attribute \src "libresoc.v:184474.18-184474.97" + wire $gt$libresoc.v:184474$12059_Y + attribute \src "libresoc.v:184475.18-184475.97" + wire $gt$libresoc.v:184475$12060_Y + attribute \src "libresoc.v:184476.18-184476.97" + wire $gt$libresoc.v:184476$12061_Y + attribute \src "libresoc.v:184477.17-184477.96" + wire $gt$libresoc.v:184477$12062_Y + attribute \src "libresoc.v:184478.18-184478.97" + wire $gt$libresoc.v:184478$12063_Y + attribute \src "libresoc.v:184479.18-184479.97" + wire $gt$libresoc.v:184479$12064_Y + attribute \src "libresoc.v:184480.18-184480.97" + wire $gt$libresoc.v:184480$12065_Y + attribute \src "libresoc.v:184481.18-184481.97" + wire $gt$libresoc.v:184481$12066_Y + attribute \src "libresoc.v:184482.18-184482.97" + wire $gt$libresoc.v:184482$12067_Y + attribute \src "libresoc.v:184483.18-184483.97" + wire $gt$libresoc.v:184483$12068_Y + attribute \src "libresoc.v:184484.18-184484.97" + wire $gt$libresoc.v:184484$12069_Y + attribute \src "libresoc.v:184485.18-184485.98" + wire $gt$libresoc.v:184485$12070_Y + attribute \src "libresoc.v:184486.18-184486.98" + wire $gt$libresoc.v:184486$12071_Y + attribute \src "libresoc.v:184487.18-184487.98" + wire $gt$libresoc.v:184487$12072_Y + attribute \src "libresoc.v:184488.17-184488.96" + wire $gt$libresoc.v:184488$12073_Y + attribute \src "libresoc.v:184489.18-184489.98" + wire $gt$libresoc.v:184489$12074_Y + attribute \src "libresoc.v:184490.18-184490.98" + wire $gt$libresoc.v:184490$12075_Y + attribute \src "libresoc.v:184491.18-184491.98" + wire $gt$libresoc.v:184491$12076_Y + attribute \src "libresoc.v:184492.18-184492.98" + wire $gt$libresoc.v:184492$12077_Y + attribute \src "libresoc.v:184493.18-184493.98" + wire $gt$libresoc.v:184493$12078_Y + attribute \src "libresoc.v:184494.18-184494.98" + wire $gt$libresoc.v:184494$12079_Y + attribute \src "libresoc.v:184495.18-184495.98" + wire $gt$libresoc.v:184495$12080_Y + attribute \src "libresoc.v:184496.18-184496.98" + wire $gt$libresoc.v:184496$12081_Y + attribute \src "libresoc.v:184497.18-184497.98" + wire $gt$libresoc.v:184497$12082_Y + attribute \src "libresoc.v:184498.18-184498.98" + wire $gt$libresoc.v:184498$12083_Y + attribute \src "libresoc.v:184499.17-184499.96" + wire $gt$libresoc.v:184499$12084_Y + attribute \src "libresoc.v:184500.18-184500.98" + wire $gt$libresoc.v:184500$12085_Y + attribute \src "libresoc.v:184501.18-184501.98" + wire $gt$libresoc.v:184501$12086_Y + attribute \src "libresoc.v:184502.18-184502.98" + wire $gt$libresoc.v:184502$12087_Y + attribute \src "libresoc.v:184503.18-184503.98" + wire $gt$libresoc.v:184503$12088_Y + attribute \src "libresoc.v:184504.18-184504.98" + wire $gt$libresoc.v:184504$12089_Y + attribute \src "libresoc.v:184505.18-184505.98" + wire $gt$libresoc.v:184505$12090_Y + attribute \src "libresoc.v:184506.18-184506.98" + wire $gt$libresoc.v:184506$12091_Y + attribute \src "libresoc.v:184507.18-184507.98" + wire $gt$libresoc.v:184507$12092_Y + attribute \src "libresoc.v:184508.18-184508.98" + wire $gt$libresoc.v:184508$12093_Y + attribute \src "libresoc.v:184509.18-184509.98" + wire $gt$libresoc.v:184509$12094_Y + attribute \src "libresoc.v:184510.17-184510.96" + wire $gt$libresoc.v:184510$12095_Y + attribute \src "libresoc.v:184511.18-184511.98" + wire $gt$libresoc.v:184511$12096_Y + attribute \src "libresoc.v:184512.18-184512.98" + wire $gt$libresoc.v:184512$12097_Y + attribute \src "libresoc.v:184513.18-184513.98" + wire $gt$libresoc.v:184513$12098_Y + attribute \src "libresoc.v:184514.18-184514.98" + wire $gt$libresoc.v:184514$12099_Y + attribute \src "libresoc.v:184515.18-184515.98" + wire $gt$libresoc.v:184515$12100_Y + attribute \src "libresoc.v:184516.18-184516.98" + wire $gt$libresoc.v:184516$12101_Y + attribute \src "libresoc.v:184517.18-184517.98" + wire $gt$libresoc.v:184517$12102_Y + attribute \src "libresoc.v:184518.18-184518.98" + wire $gt$libresoc.v:184518$12103_Y + attribute \src "libresoc.v:184519.18-184519.98" + wire $gt$libresoc.v:184519$12104_Y + attribute \src "libresoc.v:184520.18-184520.98" + wire $gt$libresoc.v:184520$12105_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -376683,14 +380692,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:182019.7-182019.15" + attribute \src "libresoc.v:184323.7-184323.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182153$11858 + cell $gt $gt$libresoc.v:184457$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376698,10 +380707,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:182153$11858_Y + connect \Y $gt$libresoc.v:184457$12042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182154$11859 + cell $gt $gt$libresoc.v:184458$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376709,10 +380718,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:182154$11859_Y + connect \Y $gt$libresoc.v:184458$12043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182155$11860 + cell $gt $gt$libresoc.v:184459$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376720,10 +380729,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:182155$11860_Y + connect \Y $gt$libresoc.v:184459$12044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182156$11861 + cell $gt $gt$libresoc.v:184460$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376731,10 +380740,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:182156$11861_Y + connect \Y $gt$libresoc.v:184460$12045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182157$11862 + cell $gt $gt$libresoc.v:184461$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376742,10 +380751,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:182157$11862_Y + connect \Y $gt$libresoc.v:184461$12046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182158$11863 + cell $gt $gt$libresoc.v:184462$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376753,10 +380762,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:182158$11863_Y + connect \Y $gt$libresoc.v:184462$12047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182159$11864 + cell $gt $gt$libresoc.v:184463$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376764,10 +380773,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:182159$11864_Y + connect \Y $gt$libresoc.v:184463$12048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182160$11865 + cell $gt $gt$libresoc.v:184464$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376775,10 +380784,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:182160$11865_Y + connect \Y $gt$libresoc.v:184464$12049_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182161$11866 + cell $gt $gt$libresoc.v:184465$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376786,10 +380795,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:182161$11866_Y + connect \Y $gt$libresoc.v:184465$12050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182162$11867 + cell $gt $gt$libresoc.v:184466$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376797,10 +380806,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:182162$11867_Y + connect \Y $gt$libresoc.v:184466$12051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182163$11868 + cell $gt $gt$libresoc.v:184467$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376808,10 +380817,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:182163$11868_Y + connect \Y $gt$libresoc.v:184467$12052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182164$11869 + cell $gt $gt$libresoc.v:184468$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376819,10 +380828,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:182164$11869_Y + connect \Y $gt$libresoc.v:184468$12053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182165$11870 + cell $gt $gt$libresoc.v:184469$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376830,10 +380839,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:182165$11870_Y + connect \Y $gt$libresoc.v:184469$12054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182166$11871 + cell $gt $gt$libresoc.v:184470$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376841,10 +380850,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:182166$11871_Y + connect \Y $gt$libresoc.v:184470$12055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182167$11872 + cell $gt $gt$libresoc.v:184471$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376852,10 +380861,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:182167$11872_Y + connect \Y $gt$libresoc.v:184471$12056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182168$11873 + cell $gt $gt$libresoc.v:184472$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376863,10 +380872,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:182168$11873_Y + connect \Y $gt$libresoc.v:184472$12057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182169$11874 + cell $gt $gt$libresoc.v:184473$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376874,10 +380883,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:182169$11874_Y + connect \Y $gt$libresoc.v:184473$12058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182170$11875 + cell $gt $gt$libresoc.v:184474$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376885,10 +380894,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:182170$11875_Y + connect \Y $gt$libresoc.v:184474$12059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182171$11876 + cell $gt $gt$libresoc.v:184475$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376896,10 +380905,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:182171$11876_Y + connect \Y $gt$libresoc.v:184475$12060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182172$11877 + cell $gt $gt$libresoc.v:184476$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376907,10 +380916,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:182172$11877_Y + connect \Y $gt$libresoc.v:184476$12061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182173$11878 + cell $gt $gt$libresoc.v:184477$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376918,10 +380927,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:182173$11878_Y + connect \Y $gt$libresoc.v:184477$12062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182174$11879 + cell $gt $gt$libresoc.v:184478$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376929,10 +380938,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:182174$11879_Y + connect \Y $gt$libresoc.v:184478$12063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182175$11880 + cell $gt $gt$libresoc.v:184479$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376940,10 +380949,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:182175$11880_Y + connect \Y $gt$libresoc.v:184479$12064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182176$11881 + cell $gt $gt$libresoc.v:184480$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376951,10 +380960,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:182176$11881_Y + connect \Y $gt$libresoc.v:184480$12065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182177$11882 + cell $gt $gt$libresoc.v:184481$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376962,10 +380971,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:182177$11882_Y + connect \Y $gt$libresoc.v:184481$12066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182178$11883 + cell $gt $gt$libresoc.v:184482$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376973,10 +380982,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:182178$11883_Y + connect \Y $gt$libresoc.v:184482$12067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182179$11884 + cell $gt $gt$libresoc.v:184483$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376984,10 +380993,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:182179$11884_Y + connect \Y $gt$libresoc.v:184483$12068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182180$11885 + cell $gt $gt$libresoc.v:184484$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -376995,10 +381004,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:182180$11885_Y + connect \Y $gt$libresoc.v:184484$12069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182181$11886 + cell $gt $gt$libresoc.v:184485$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377006,10 +381015,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:182181$11886_Y + connect \Y $gt$libresoc.v:184485$12070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182182$11887 + cell $gt $gt$libresoc.v:184486$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377017,10 +381026,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:182182$11887_Y + connect \Y $gt$libresoc.v:184486$12071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182183$11888 + cell $gt $gt$libresoc.v:184487$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377028,10 +381037,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:182183$11888_Y + connect \Y $gt$libresoc.v:184487$12072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182184$11889 + cell $gt $gt$libresoc.v:184488$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377039,10 +381048,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:182184$11889_Y + connect \Y $gt$libresoc.v:184488$12073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182185$11890 + cell $gt $gt$libresoc.v:184489$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377050,10 +381059,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:182185$11890_Y + connect \Y $gt$libresoc.v:184489$12074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182186$11891 + cell $gt $gt$libresoc.v:184490$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377061,10 +381070,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:182186$11891_Y + connect \Y $gt$libresoc.v:184490$12075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182187$11892 + cell $gt $gt$libresoc.v:184491$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377072,10 +381081,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:182187$11892_Y + connect \Y $gt$libresoc.v:184491$12076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182188$11893 + cell $gt $gt$libresoc.v:184492$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377083,10 +381092,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:182188$11893_Y + connect \Y $gt$libresoc.v:184492$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182189$11894 + cell $gt $gt$libresoc.v:184493$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377094,10 +381103,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:182189$11894_Y + connect \Y $gt$libresoc.v:184493$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182190$11895 + cell $gt $gt$libresoc.v:184494$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377105,10 +381114,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:182190$11895_Y + connect \Y $gt$libresoc.v:184494$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182191$11896 + cell $gt $gt$libresoc.v:184495$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377116,10 +381125,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:182191$11896_Y + connect \Y $gt$libresoc.v:184495$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182192$11897 + cell $gt $gt$libresoc.v:184496$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377127,10 +381136,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:182192$11897_Y + connect \Y $gt$libresoc.v:184496$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182193$11898 + cell $gt $gt$libresoc.v:184497$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377138,10 +381147,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:182193$11898_Y + connect \Y $gt$libresoc.v:184497$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182194$11899 + cell $gt $gt$libresoc.v:184498$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377149,10 +381158,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:182194$11899_Y + connect \Y $gt$libresoc.v:184498$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182195$11900 + cell $gt $gt$libresoc.v:184499$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377160,10 +381169,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:182195$11900_Y + connect \Y $gt$libresoc.v:184499$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182196$11901 + cell $gt $gt$libresoc.v:184500$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377171,10 +381180,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:182196$11901_Y + connect \Y $gt$libresoc.v:184500$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182197$11902 + cell $gt $gt$libresoc.v:184501$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377182,10 +381191,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:182197$11902_Y + connect \Y $gt$libresoc.v:184501$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182198$11903 + cell $gt $gt$libresoc.v:184502$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377193,10 +381202,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:182198$11903_Y + connect \Y $gt$libresoc.v:184502$12087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182199$11904 + cell $gt $gt$libresoc.v:184503$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377204,10 +381213,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:182199$11904_Y + connect \Y $gt$libresoc.v:184503$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182200$11905 + cell $gt $gt$libresoc.v:184504$12089 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377215,10 +381224,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:182200$11905_Y + connect \Y $gt$libresoc.v:184504$12089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182201$11906 + cell $gt $gt$libresoc.v:184505$12090 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377226,10 +381235,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:182201$11906_Y + connect \Y $gt$libresoc.v:184505$12090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182202$11907 + cell $gt $gt$libresoc.v:184506$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377237,10 +381246,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:182202$11907_Y + connect \Y $gt$libresoc.v:184506$12091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182203$11908 + cell $gt $gt$libresoc.v:184507$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377248,10 +381257,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:182203$11908_Y + connect \Y $gt$libresoc.v:184507$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182204$11909 + cell $gt $gt$libresoc.v:184508$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377259,10 +381268,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:182204$11909_Y + connect \Y $gt$libresoc.v:184508$12093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182205$11910 + cell $gt $gt$libresoc.v:184509$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377270,10 +381279,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:182205$11910_Y + connect \Y $gt$libresoc.v:184509$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182206$11911 + cell $gt $gt$libresoc.v:184510$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377281,10 +381290,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:182206$11911_Y + connect \Y $gt$libresoc.v:184510$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182207$11912 + cell $gt $gt$libresoc.v:184511$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377292,10 +381301,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:182207$11912_Y + connect \Y $gt$libresoc.v:184511$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182208$11913 + cell $gt $gt$libresoc.v:184512$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377303,10 +381312,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:182208$11913_Y + connect \Y $gt$libresoc.v:184512$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182209$11914 + cell $gt $gt$libresoc.v:184513$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377314,10 +381323,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:182209$11914_Y + connect \Y $gt$libresoc.v:184513$12098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182210$11915 + cell $gt $gt$libresoc.v:184514$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377325,10 +381334,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:182210$11915_Y + connect \Y $gt$libresoc.v:184514$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182211$11916 + cell $gt $gt$libresoc.v:184515$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377336,10 +381345,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:182211$11916_Y + connect \Y $gt$libresoc.v:184515$12100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182212$11917 + cell $gt $gt$libresoc.v:184516$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377347,10 +381356,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:182212$11917_Y + connect \Y $gt$libresoc.v:184516$12101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182213$11918 + cell $gt $gt$libresoc.v:184517$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377358,10 +381367,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:182213$11918_Y + connect \Y $gt$libresoc.v:184517$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182214$11919 + cell $gt $gt$libresoc.v:184518$12103 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377369,10 +381378,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:182214$11919_Y + connect \Y $gt$libresoc.v:184518$12103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182215$11920 + cell $gt $gt$libresoc.v:184519$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377380,10 +381389,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:182215$11920_Y + connect \Y $gt$libresoc.v:184519$12104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:182216$11921 + cell $gt $gt$libresoc.v:184520$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377391,18 +381400,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:182216$11921_Y + connect \Y $gt$libresoc.v:184520$12105_Y end - attribute \src "libresoc.v:182019.7-182019.20" - process $proc$libresoc.v:182019$11923 + attribute \src "libresoc.v:184323.7-184323.20" + process $proc$libresoc.v:184323$12107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182217.3-182604.6" - process $proc$libresoc.v:182217$11922 + attribute \src "libresoc.v:184521.3-184908.6" + process $proc$libresoc.v:184521$12106 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -377469,9 +381478,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:182218.5-182218.29" + attribute \src "libresoc.v:184522.5-184522.29" switch \initial - attribute \src "libresoc.v:182218.9-182218.17" + attribute \src "libresoc.v:184522.9-184522.17" case 1'1 case end @@ -378054,102 +382063,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:182153$11858_Y - connect \$99 $gt$libresoc.v:182154$11859_Y - connect \$101 $gt$libresoc.v:182155$11860_Y - connect \$103 $gt$libresoc.v:182156$11861_Y - connect \$105 $gt$libresoc.v:182157$11862_Y - connect \$107 $gt$libresoc.v:182158$11863_Y - connect \$109 $gt$libresoc.v:182159$11864_Y - connect \$111 $gt$libresoc.v:182160$11865_Y - connect \$113 $gt$libresoc.v:182161$11866_Y - connect \$115 $gt$libresoc.v:182162$11867_Y - connect \$117 $gt$libresoc.v:182163$11868_Y - connect \$11 $gt$libresoc.v:182164$11869_Y - connect \$119 $gt$libresoc.v:182165$11870_Y - connect \$121 $gt$libresoc.v:182166$11871_Y - connect \$123 $gt$libresoc.v:182167$11872_Y - connect \$125 $gt$libresoc.v:182168$11873_Y - connect \$127 $gt$libresoc.v:182169$11874_Y - connect \$13 $gt$libresoc.v:182170$11875_Y - connect \$15 $gt$libresoc.v:182171$11876_Y - connect \$17 $gt$libresoc.v:182172$11877_Y - connect \$1 $gt$libresoc.v:182173$11878_Y - connect \$19 $gt$libresoc.v:182174$11879_Y - connect \$21 $gt$libresoc.v:182175$11880_Y - connect \$23 $gt$libresoc.v:182176$11881_Y - connect \$25 $gt$libresoc.v:182177$11882_Y - connect \$27 $gt$libresoc.v:182178$11883_Y - connect \$29 $gt$libresoc.v:182179$11884_Y - connect \$31 $gt$libresoc.v:182180$11885_Y - connect \$33 $gt$libresoc.v:182181$11886_Y - connect \$35 $gt$libresoc.v:182182$11887_Y - connect \$37 $gt$libresoc.v:182183$11888_Y - connect \$3 $gt$libresoc.v:182184$11889_Y - connect \$39 $gt$libresoc.v:182185$11890_Y - connect \$41 $gt$libresoc.v:182186$11891_Y - connect \$43 $gt$libresoc.v:182187$11892_Y - connect \$45 $gt$libresoc.v:182188$11893_Y - connect \$47 $gt$libresoc.v:182189$11894_Y - connect \$49 $gt$libresoc.v:182190$11895_Y - connect \$51 $gt$libresoc.v:182191$11896_Y - connect \$53 $gt$libresoc.v:182192$11897_Y - connect \$55 $gt$libresoc.v:182193$11898_Y - connect \$57 $gt$libresoc.v:182194$11899_Y - connect \$5 $gt$libresoc.v:182195$11900_Y - connect \$59 $gt$libresoc.v:182196$11901_Y - connect \$61 $gt$libresoc.v:182197$11902_Y - connect \$63 $gt$libresoc.v:182198$11903_Y - connect \$65 $gt$libresoc.v:182199$11904_Y - connect \$67 $gt$libresoc.v:182200$11905_Y - connect \$69 $gt$libresoc.v:182201$11906_Y - connect \$71 $gt$libresoc.v:182202$11907_Y - connect \$73 $gt$libresoc.v:182203$11908_Y - connect \$75 $gt$libresoc.v:182204$11909_Y - connect \$77 $gt$libresoc.v:182205$11910_Y - connect \$7 $gt$libresoc.v:182206$11911_Y - connect \$79 $gt$libresoc.v:182207$11912_Y - connect \$81 $gt$libresoc.v:182208$11913_Y - connect \$83 $gt$libresoc.v:182209$11914_Y - connect \$85 $gt$libresoc.v:182210$11915_Y - connect \$87 $gt$libresoc.v:182211$11916_Y - connect \$89 $gt$libresoc.v:182212$11917_Y - connect \$91 $gt$libresoc.v:182213$11918_Y - connect \$93 $gt$libresoc.v:182214$11919_Y - connect \$95 $gt$libresoc.v:182215$11920_Y - connect \$97 $gt$libresoc.v:182216$11921_Y + connect \$9 $gt$libresoc.v:184457$12042_Y + connect \$99 $gt$libresoc.v:184458$12043_Y + connect \$101 $gt$libresoc.v:184459$12044_Y + connect \$103 $gt$libresoc.v:184460$12045_Y + connect \$105 $gt$libresoc.v:184461$12046_Y + connect \$107 $gt$libresoc.v:184462$12047_Y + connect \$109 $gt$libresoc.v:184463$12048_Y + connect \$111 $gt$libresoc.v:184464$12049_Y + connect \$113 $gt$libresoc.v:184465$12050_Y + connect \$115 $gt$libresoc.v:184466$12051_Y + connect \$117 $gt$libresoc.v:184467$12052_Y + connect \$11 $gt$libresoc.v:184468$12053_Y + connect \$119 $gt$libresoc.v:184469$12054_Y + connect \$121 $gt$libresoc.v:184470$12055_Y + connect \$123 $gt$libresoc.v:184471$12056_Y + connect \$125 $gt$libresoc.v:184472$12057_Y + connect \$127 $gt$libresoc.v:184473$12058_Y + connect \$13 $gt$libresoc.v:184474$12059_Y + connect \$15 $gt$libresoc.v:184475$12060_Y + connect \$17 $gt$libresoc.v:184476$12061_Y + connect \$1 $gt$libresoc.v:184477$12062_Y + connect \$19 $gt$libresoc.v:184478$12063_Y + connect \$21 $gt$libresoc.v:184479$12064_Y + connect \$23 $gt$libresoc.v:184480$12065_Y + connect \$25 $gt$libresoc.v:184481$12066_Y + connect \$27 $gt$libresoc.v:184482$12067_Y + connect \$29 $gt$libresoc.v:184483$12068_Y + connect \$31 $gt$libresoc.v:184484$12069_Y + connect \$33 $gt$libresoc.v:184485$12070_Y + connect \$35 $gt$libresoc.v:184486$12071_Y + connect \$37 $gt$libresoc.v:184487$12072_Y + connect \$3 $gt$libresoc.v:184488$12073_Y + connect \$39 $gt$libresoc.v:184489$12074_Y + connect \$41 $gt$libresoc.v:184490$12075_Y + connect \$43 $gt$libresoc.v:184491$12076_Y + connect \$45 $gt$libresoc.v:184492$12077_Y + connect \$47 $gt$libresoc.v:184493$12078_Y + connect \$49 $gt$libresoc.v:184494$12079_Y + connect \$51 $gt$libresoc.v:184495$12080_Y + connect \$53 $gt$libresoc.v:184496$12081_Y + connect \$55 $gt$libresoc.v:184497$12082_Y + connect \$57 $gt$libresoc.v:184498$12083_Y + connect \$5 $gt$libresoc.v:184499$12084_Y + connect \$59 $gt$libresoc.v:184500$12085_Y + connect \$61 $gt$libresoc.v:184501$12086_Y + connect \$63 $gt$libresoc.v:184502$12087_Y + connect \$65 $gt$libresoc.v:184503$12088_Y + connect \$67 $gt$libresoc.v:184504$12089_Y + connect \$69 $gt$libresoc.v:184505$12090_Y + connect \$71 $gt$libresoc.v:184506$12091_Y + connect \$73 $gt$libresoc.v:184507$12092_Y + connect \$75 $gt$libresoc.v:184508$12093_Y + connect \$77 $gt$libresoc.v:184509$12094_Y + connect \$7 $gt$libresoc.v:184510$12095_Y + connect \$79 $gt$libresoc.v:184511$12096_Y + connect \$81 $gt$libresoc.v:184512$12097_Y + connect \$83 $gt$libresoc.v:184513$12098_Y + connect \$85 $gt$libresoc.v:184514$12099_Y + connect \$87 $gt$libresoc.v:184515$12100_Y + connect \$89 $gt$libresoc.v:184516$12101_Y + connect \$91 $gt$libresoc.v:184517$12102_Y + connect \$93 $gt$libresoc.v:184518$12103_Y + connect \$95 $gt$libresoc.v:184519$12104_Y + connect \$97 $gt$libresoc.v:184520$12105_Y end -attribute \src "libresoc.v:182609.1-182667.10" +attribute \src "libresoc.v:184913.1-184971.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:182610.7-182610.20" + attribute \src "libresoc.v:184914.7-184914.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182655.3-182663.6" - wire $0\q_int$next[0:0]$11934 - attribute \src "libresoc.v:182653.3-182654.27" + attribute \src "libresoc.v:184959.3-184967.6" + wire $0\q_int$next[0:0]$12118 + attribute \src "libresoc.v:184957.3-184958.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182655.3-182663.6" - wire $1\q_int$next[0:0]$11935 - attribute \src "libresoc.v:182632.7-182632.19" + attribute \src "libresoc.v:184959.3-184967.6" + wire $1\q_int$next[0:0]$12119 + attribute \src "libresoc.v:184936.7-184936.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182645.17-182645.96" - wire $and$libresoc.v:182645$11924_Y - attribute \src "libresoc.v:182650.17-182650.96" - wire $and$libresoc.v:182650$11929_Y - attribute \src "libresoc.v:182647.18-182647.94" - wire $not$libresoc.v:182647$11926_Y - attribute \src "libresoc.v:182649.17-182649.93" - wire $not$libresoc.v:182649$11928_Y - attribute \src "libresoc.v:182652.17-182652.93" - wire $not$libresoc.v:182652$11931_Y - attribute \src "libresoc.v:182646.18-182646.99" - wire $or$libresoc.v:182646$11925_Y - attribute \src "libresoc.v:182648.18-182648.100" - wire $or$libresoc.v:182648$11927_Y - attribute \src "libresoc.v:182651.17-182651.98" - wire $or$libresoc.v:182651$11930_Y + attribute \src "libresoc.v:184949.17-184949.96" + wire $and$libresoc.v:184949$12108_Y + attribute \src "libresoc.v:184954.17-184954.96" + wire $and$libresoc.v:184954$12113_Y + attribute \src "libresoc.v:184951.18-184951.94" + wire $not$libresoc.v:184951$12110_Y + attribute \src "libresoc.v:184953.17-184953.93" + wire $not$libresoc.v:184953$12112_Y + attribute \src "libresoc.v:184956.17-184956.93" + wire $not$libresoc.v:184956$12115_Y + attribute \src "libresoc.v:184950.18-184950.99" + wire $or$libresoc.v:184950$12109_Y + attribute \src "libresoc.v:184952.18-184952.100" + wire $or$libresoc.v:184952$12111_Y + attribute \src "libresoc.v:184955.17-184955.98" + wire $or$libresoc.v:184955$12114_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378166,11 +382175,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182610.7-182610.15" + attribute \src "libresoc.v:184914.7-184914.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378187,7 +382196,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182645$11924 + cell $and $and$libresoc.v:184949$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378195,10 +382204,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182645$11924_Y + connect \Y $and$libresoc.v:184949$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182650$11929 + cell $and $and$libresoc.v:184954$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378206,34 +382215,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182650$11929_Y + connect \Y $and$libresoc.v:184954$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182647$11926 + cell $not $not$libresoc.v:184951$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182647$11926_Y + connect \Y $not$libresoc.v:184951$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182649$11928 + cell $not $not$libresoc.v:184953$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182649$11928_Y + connect \Y $not$libresoc.v:184953$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182652$11931 + cell $not $not$libresoc.v:184956$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182652$11931_Y + connect \Y $not$libresoc.v:184956$12115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182646$11925 + cell $or $or$libresoc.v:184950$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378241,10 +382250,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182646$11925_Y + connect \Y $or$libresoc.v:184950$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182648$11927 + cell $or $or$libresoc.v:184952$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378252,10 +382261,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182648$11927_Y + connect \Y $or$libresoc.v:184952$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182651$11930 + cell $or $or$libresoc.v:184955$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378263,39 +382272,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182651$11930_Y + connect \Y $or$libresoc.v:184955$12114_Y end - attribute \src "libresoc.v:182610.7-182610.20" - process $proc$libresoc.v:182610$11936 + attribute \src "libresoc.v:184914.7-184914.20" + process $proc$libresoc.v:184914$12120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182632.7-182632.19" - process $proc$libresoc.v:182632$11937 + attribute \src "libresoc.v:184936.7-184936.19" + process $proc$libresoc.v:184936$12121 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182653.3-182654.27" - process $proc$libresoc.v:182653$11932 + attribute \src "libresoc.v:184957.3-184958.27" + process $proc$libresoc.v:184957$12116 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182655.3-182663.6" - process $proc$libresoc.v:182655$11933 + attribute \src "libresoc.v:184959.3-184967.6" + process $proc$libresoc.v:184959$12117 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11934 $1\q_int$next[0:0]$11935 - attribute \src "libresoc.v:182656.5-182656.29" + assign $0\q_int$next[0:0]$12118 $1\q_int$next[0:0]$12119 + attribute \src "libresoc.v:184960.5-184960.29" switch \initial - attribute \src "libresoc.v:182656.9-182656.17" + attribute \src "libresoc.v:184960.9-184960.17" case 1'1 case end @@ -378304,56 +382313,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11935 1'0 + assign $1\q_int$next[0:0]$12119 1'0 case - assign $1\q_int$next[0:0]$11935 \$5 + assign $1\q_int$next[0:0]$12119 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11934 + update \q_int$next $0\q_int$next[0:0]$12118 end - connect \$9 $and$libresoc.v:182645$11924_Y - connect \$11 $or$libresoc.v:182646$11925_Y - connect \$13 $not$libresoc.v:182647$11926_Y - connect \$15 $or$libresoc.v:182648$11927_Y - connect \$1 $not$libresoc.v:182649$11928_Y - connect \$3 $and$libresoc.v:182650$11929_Y - connect \$5 $or$libresoc.v:182651$11930_Y - connect \$7 $not$libresoc.v:182652$11931_Y + connect \$9 $and$libresoc.v:184949$12108_Y + connect \$11 $or$libresoc.v:184950$12109_Y + connect \$13 $not$libresoc.v:184951$12110_Y + connect \$15 $or$libresoc.v:184952$12111_Y + connect \$1 $not$libresoc.v:184953$12112_Y + connect \$3 $and$libresoc.v:184954$12113_Y + connect \$5 $or$libresoc.v:184955$12114_Y + connect \$7 $not$libresoc.v:184956$12115_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182671.1-182729.10" +attribute \src "libresoc.v:184975.1-185033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:182672.7-182672.20" + attribute \src "libresoc.v:184976.7-184976.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182717.3-182725.6" - wire $0\q_int$next[0:0]$11948 - attribute \src "libresoc.v:182715.3-182716.27" + attribute \src "libresoc.v:185021.3-185029.6" + wire $0\q_int$next[0:0]$12132 + attribute \src "libresoc.v:185019.3-185020.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182717.3-182725.6" - wire $1\q_int$next[0:0]$11949 - attribute \src "libresoc.v:182694.7-182694.19" + attribute \src "libresoc.v:185021.3-185029.6" + wire $1\q_int$next[0:0]$12133 + attribute \src "libresoc.v:184998.7-184998.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182707.17-182707.96" - wire $and$libresoc.v:182707$11938_Y - attribute \src "libresoc.v:182712.17-182712.96" - wire $and$libresoc.v:182712$11943_Y - attribute \src "libresoc.v:182709.18-182709.94" - wire $not$libresoc.v:182709$11940_Y - attribute \src "libresoc.v:182711.17-182711.93" - wire $not$libresoc.v:182711$11942_Y - attribute \src "libresoc.v:182714.17-182714.93" - wire $not$libresoc.v:182714$11945_Y - attribute \src "libresoc.v:182708.18-182708.99" - wire $or$libresoc.v:182708$11939_Y - attribute \src "libresoc.v:182710.18-182710.100" - wire $or$libresoc.v:182710$11941_Y - attribute \src "libresoc.v:182713.17-182713.98" - wire $or$libresoc.v:182713$11944_Y + attribute \src "libresoc.v:185011.17-185011.96" + wire $and$libresoc.v:185011$12122_Y + attribute \src "libresoc.v:185016.17-185016.96" + wire $and$libresoc.v:185016$12127_Y + attribute \src "libresoc.v:185013.18-185013.94" + wire $not$libresoc.v:185013$12124_Y + attribute \src "libresoc.v:185015.17-185015.93" + wire $not$libresoc.v:185015$12126_Y + attribute \src "libresoc.v:185018.17-185018.93" + wire $not$libresoc.v:185018$12129_Y + attribute \src "libresoc.v:185012.18-185012.99" + wire $or$libresoc.v:185012$12123_Y + attribute \src "libresoc.v:185014.18-185014.100" + wire $or$libresoc.v:185014$12125_Y + attribute \src "libresoc.v:185017.17-185017.98" + wire $or$libresoc.v:185017$12128_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378370,11 +382379,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182672.7-182672.15" + attribute \src "libresoc.v:184976.7-184976.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378391,7 +382400,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182707$11938 + cell $and $and$libresoc.v:185011$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378399,10 +382408,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182707$11938_Y + connect \Y $and$libresoc.v:185011$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182712$11943 + cell $and $and$libresoc.v:185016$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378410,34 +382419,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182712$11943_Y + connect \Y $and$libresoc.v:185016$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182709$11940 + cell $not $not$libresoc.v:185013$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182709$11940_Y + connect \Y $not$libresoc.v:185013$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182711$11942 + cell $not $not$libresoc.v:185015$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182711$11942_Y + connect \Y $not$libresoc.v:185015$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182714$11945 + cell $not $not$libresoc.v:185018$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182714$11945_Y + connect \Y $not$libresoc.v:185018$12129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182708$11939 + cell $or $or$libresoc.v:185012$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378445,10 +382454,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182708$11939_Y + connect \Y $or$libresoc.v:185012$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182710$11941 + cell $or $or$libresoc.v:185014$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378456,10 +382465,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182710$11941_Y + connect \Y $or$libresoc.v:185014$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182713$11944 + cell $or $or$libresoc.v:185017$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378467,39 +382476,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182713$11944_Y + connect \Y $or$libresoc.v:185017$12128_Y end - attribute \src "libresoc.v:182672.7-182672.20" - process $proc$libresoc.v:182672$11950 + attribute \src "libresoc.v:184976.7-184976.20" + process $proc$libresoc.v:184976$12134 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182694.7-182694.19" - process $proc$libresoc.v:182694$11951 + attribute \src "libresoc.v:184998.7-184998.19" + process $proc$libresoc.v:184998$12135 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182715.3-182716.27" - process $proc$libresoc.v:182715$11946 + attribute \src "libresoc.v:185019.3-185020.27" + process $proc$libresoc.v:185019$12130 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182717.3-182725.6" - process $proc$libresoc.v:182717$11947 + attribute \src "libresoc.v:185021.3-185029.6" + process $proc$libresoc.v:185021$12131 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11948 $1\q_int$next[0:0]$11949 - attribute \src "libresoc.v:182718.5-182718.29" + assign $0\q_int$next[0:0]$12132 $1\q_int$next[0:0]$12133 + attribute \src "libresoc.v:185022.5-185022.29" switch \initial - attribute \src "libresoc.v:182718.9-182718.17" + attribute \src "libresoc.v:185022.9-185022.17" case 1'1 case end @@ -378508,56 +382517,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11949 1'0 + assign $1\q_int$next[0:0]$12133 1'0 case - assign $1\q_int$next[0:0]$11949 \$5 + assign $1\q_int$next[0:0]$12133 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11948 + update \q_int$next $0\q_int$next[0:0]$12132 end - connect \$9 $and$libresoc.v:182707$11938_Y - connect \$11 $or$libresoc.v:182708$11939_Y - connect \$13 $not$libresoc.v:182709$11940_Y - connect \$15 $or$libresoc.v:182710$11941_Y - connect \$1 $not$libresoc.v:182711$11942_Y - connect \$3 $and$libresoc.v:182712$11943_Y - connect \$5 $or$libresoc.v:182713$11944_Y - connect \$7 $not$libresoc.v:182714$11945_Y + connect \$9 $and$libresoc.v:185011$12122_Y + connect \$11 $or$libresoc.v:185012$12123_Y + connect \$13 $not$libresoc.v:185013$12124_Y + connect \$15 $or$libresoc.v:185014$12125_Y + connect \$1 $not$libresoc.v:185015$12126_Y + connect \$3 $and$libresoc.v:185016$12127_Y + connect \$5 $or$libresoc.v:185017$12128_Y + connect \$7 $not$libresoc.v:185018$12129_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182733.1-182791.10" +attribute \src "libresoc.v:185037.1-185095.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:182734.7-182734.20" + attribute \src "libresoc.v:185038.7-185038.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182779.3-182787.6" - wire $0\q_int$next[0:0]$11962 - attribute \src "libresoc.v:182777.3-182778.27" + attribute \src "libresoc.v:185083.3-185091.6" + wire $0\q_int$next[0:0]$12146 + attribute \src "libresoc.v:185081.3-185082.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182779.3-182787.6" - wire $1\q_int$next[0:0]$11963 - attribute \src "libresoc.v:182756.7-182756.19" + attribute \src "libresoc.v:185083.3-185091.6" + wire $1\q_int$next[0:0]$12147 + attribute \src "libresoc.v:185060.7-185060.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182769.17-182769.96" - wire $and$libresoc.v:182769$11952_Y - attribute \src "libresoc.v:182774.17-182774.96" - wire $and$libresoc.v:182774$11957_Y - attribute \src "libresoc.v:182771.18-182771.94" - wire $not$libresoc.v:182771$11954_Y - attribute \src "libresoc.v:182773.17-182773.93" - wire $not$libresoc.v:182773$11956_Y - attribute \src "libresoc.v:182776.17-182776.93" - wire $not$libresoc.v:182776$11959_Y - attribute \src "libresoc.v:182770.18-182770.99" - wire $or$libresoc.v:182770$11953_Y - attribute \src "libresoc.v:182772.18-182772.100" - wire $or$libresoc.v:182772$11955_Y - attribute \src "libresoc.v:182775.17-182775.98" - wire $or$libresoc.v:182775$11958_Y + attribute \src "libresoc.v:185073.17-185073.96" + wire $and$libresoc.v:185073$12136_Y + attribute \src "libresoc.v:185078.17-185078.96" + wire $and$libresoc.v:185078$12141_Y + attribute \src "libresoc.v:185075.18-185075.94" + wire $not$libresoc.v:185075$12138_Y + attribute \src "libresoc.v:185077.17-185077.93" + wire $not$libresoc.v:185077$12140_Y + attribute \src "libresoc.v:185080.17-185080.93" + wire $not$libresoc.v:185080$12143_Y + attribute \src "libresoc.v:185074.18-185074.99" + wire $or$libresoc.v:185074$12137_Y + attribute \src "libresoc.v:185076.18-185076.100" + wire $or$libresoc.v:185076$12139_Y + attribute \src "libresoc.v:185079.17-185079.98" + wire $or$libresoc.v:185079$12142_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378574,11 +382583,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182734.7-182734.15" + attribute \src "libresoc.v:185038.7-185038.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378595,7 +382604,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182769$11952 + cell $and $and$libresoc.v:185073$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378603,10 +382612,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182769$11952_Y + connect \Y $and$libresoc.v:185073$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182774$11957 + cell $and $and$libresoc.v:185078$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378614,34 +382623,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182774$11957_Y + connect \Y $and$libresoc.v:185078$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182771$11954 + cell $not $not$libresoc.v:185075$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182771$11954_Y + connect \Y $not$libresoc.v:185075$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182773$11956 + cell $not $not$libresoc.v:185077$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182773$11956_Y + connect \Y $not$libresoc.v:185077$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182776$11959 + cell $not $not$libresoc.v:185080$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182776$11959_Y + connect \Y $not$libresoc.v:185080$12143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182770$11953 + cell $or $or$libresoc.v:185074$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378649,10 +382658,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182770$11953_Y + connect \Y $or$libresoc.v:185074$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182772$11955 + cell $or $or$libresoc.v:185076$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378660,10 +382669,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182772$11955_Y + connect \Y $or$libresoc.v:185076$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182775$11958 + cell $or $or$libresoc.v:185079$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378671,39 +382680,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182775$11958_Y + connect \Y $or$libresoc.v:185079$12142_Y end - attribute \src "libresoc.v:182734.7-182734.20" - process $proc$libresoc.v:182734$11964 + attribute \src "libresoc.v:185038.7-185038.20" + process $proc$libresoc.v:185038$12148 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182756.7-182756.19" - process $proc$libresoc.v:182756$11965 + attribute \src "libresoc.v:185060.7-185060.19" + process $proc$libresoc.v:185060$12149 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182777.3-182778.27" - process $proc$libresoc.v:182777$11960 + attribute \src "libresoc.v:185081.3-185082.27" + process $proc$libresoc.v:185081$12144 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182779.3-182787.6" - process $proc$libresoc.v:182779$11961 + attribute \src "libresoc.v:185083.3-185091.6" + process $proc$libresoc.v:185083$12145 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11962 $1\q_int$next[0:0]$11963 - attribute \src "libresoc.v:182780.5-182780.29" + assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 + attribute \src "libresoc.v:185084.5-185084.29" switch \initial - attribute \src "libresoc.v:182780.9-182780.17" + attribute \src "libresoc.v:185084.9-185084.17" case 1'1 case end @@ -378712,56 +382721,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11963 1'0 + assign $1\q_int$next[0:0]$12147 1'0 case - assign $1\q_int$next[0:0]$11963 \$5 + assign $1\q_int$next[0:0]$12147 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11962 + update \q_int$next $0\q_int$next[0:0]$12146 end - connect \$9 $and$libresoc.v:182769$11952_Y - connect \$11 $or$libresoc.v:182770$11953_Y - connect \$13 $not$libresoc.v:182771$11954_Y - connect \$15 $or$libresoc.v:182772$11955_Y - connect \$1 $not$libresoc.v:182773$11956_Y - connect \$3 $and$libresoc.v:182774$11957_Y - connect \$5 $or$libresoc.v:182775$11958_Y - connect \$7 $not$libresoc.v:182776$11959_Y + connect \$9 $and$libresoc.v:185073$12136_Y + connect \$11 $or$libresoc.v:185074$12137_Y + connect \$13 $not$libresoc.v:185075$12138_Y + connect \$15 $or$libresoc.v:185076$12139_Y + connect \$1 $not$libresoc.v:185077$12140_Y + connect \$3 $and$libresoc.v:185078$12141_Y + connect \$5 $or$libresoc.v:185079$12142_Y + connect \$7 $not$libresoc.v:185080$12143_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182795.1-182853.10" +attribute \src "libresoc.v:185099.1-185157.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:182796.7-182796.20" + attribute \src "libresoc.v:185100.7-185100.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182841.3-182849.6" - wire $0\q_int$next[0:0]$11976 - attribute \src "libresoc.v:182839.3-182840.27" + attribute \src "libresoc.v:185145.3-185153.6" + wire $0\q_int$next[0:0]$12160 + attribute \src "libresoc.v:185143.3-185144.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182841.3-182849.6" - wire $1\q_int$next[0:0]$11977 - attribute \src "libresoc.v:182818.7-182818.19" + attribute \src "libresoc.v:185145.3-185153.6" + wire $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185122.7-185122.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182831.17-182831.96" - wire $and$libresoc.v:182831$11966_Y - attribute \src "libresoc.v:182836.17-182836.96" - wire $and$libresoc.v:182836$11971_Y - attribute \src "libresoc.v:182833.18-182833.94" - wire $not$libresoc.v:182833$11968_Y - attribute \src "libresoc.v:182835.17-182835.93" - wire $not$libresoc.v:182835$11970_Y - attribute \src "libresoc.v:182838.17-182838.93" - wire $not$libresoc.v:182838$11973_Y - attribute \src "libresoc.v:182832.18-182832.99" - wire $or$libresoc.v:182832$11967_Y - attribute \src "libresoc.v:182834.18-182834.100" - wire $or$libresoc.v:182834$11969_Y - attribute \src "libresoc.v:182837.17-182837.98" - wire $or$libresoc.v:182837$11972_Y + attribute \src "libresoc.v:185135.17-185135.96" + wire $and$libresoc.v:185135$12150_Y + attribute \src "libresoc.v:185140.17-185140.96" + wire $and$libresoc.v:185140$12155_Y + attribute \src "libresoc.v:185137.18-185137.94" + wire $not$libresoc.v:185137$12152_Y + attribute \src "libresoc.v:185139.17-185139.93" + wire $not$libresoc.v:185139$12154_Y + attribute \src "libresoc.v:185142.17-185142.93" + wire $not$libresoc.v:185142$12157_Y + attribute \src "libresoc.v:185136.18-185136.99" + wire $or$libresoc.v:185136$12151_Y + attribute \src "libresoc.v:185138.18-185138.100" + wire $or$libresoc.v:185138$12153_Y + attribute \src "libresoc.v:185141.17-185141.98" + wire $or$libresoc.v:185141$12156_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378778,11 +382787,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182796.7-182796.15" + attribute \src "libresoc.v:185100.7-185100.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -378799,7 +382808,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182831$11966 + cell $and $and$libresoc.v:185135$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378807,10 +382816,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182831$11966_Y + connect \Y $and$libresoc.v:185135$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182836$11971 + cell $and $and$libresoc.v:185140$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378818,34 +382827,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182836$11971_Y + connect \Y $and$libresoc.v:185140$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182833$11968 + cell $not $not$libresoc.v:185137$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182833$11968_Y + connect \Y $not$libresoc.v:185137$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182835$11970 + cell $not $not$libresoc.v:185139$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182835$11970_Y + connect \Y $not$libresoc.v:185139$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182838$11973 + cell $not $not$libresoc.v:185142$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182838$11973_Y + connect \Y $not$libresoc.v:185142$12157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182832$11967 + cell $or $or$libresoc.v:185136$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378853,10 +382862,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182832$11967_Y + connect \Y $or$libresoc.v:185136$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182834$11969 + cell $or $or$libresoc.v:185138$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378864,10 +382873,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182834$11969_Y + connect \Y $or$libresoc.v:185138$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182837$11972 + cell $or $or$libresoc.v:185141$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378875,39 +382884,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182837$11972_Y + connect \Y $or$libresoc.v:185141$12156_Y end - attribute \src "libresoc.v:182796.7-182796.20" - process $proc$libresoc.v:182796$11978 + attribute \src "libresoc.v:185100.7-185100.20" + process $proc$libresoc.v:185100$12162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182818.7-182818.19" - process $proc$libresoc.v:182818$11979 + attribute \src "libresoc.v:185122.7-185122.19" + process $proc$libresoc.v:185122$12163 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182839.3-182840.27" - process $proc$libresoc.v:182839$11974 + attribute \src "libresoc.v:185143.3-185144.27" + process $proc$libresoc.v:185143$12158 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182841.3-182849.6" - process $proc$libresoc.v:182841$11975 + attribute \src "libresoc.v:185145.3-185153.6" + process $proc$libresoc.v:185145$12159 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11976 $1\q_int$next[0:0]$11977 - attribute \src "libresoc.v:182842.5-182842.29" + assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 + attribute \src "libresoc.v:185146.5-185146.29" switch \initial - attribute \src "libresoc.v:182842.9-182842.17" + attribute \src "libresoc.v:185146.9-185146.17" case 1'1 case end @@ -378916,56 +382925,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11977 1'0 + assign $1\q_int$next[0:0]$12161 1'0 case - assign $1\q_int$next[0:0]$11977 \$5 + assign $1\q_int$next[0:0]$12161 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11976 + update \q_int$next $0\q_int$next[0:0]$12160 end - connect \$9 $and$libresoc.v:182831$11966_Y - connect \$11 $or$libresoc.v:182832$11967_Y - connect \$13 $not$libresoc.v:182833$11968_Y - connect \$15 $or$libresoc.v:182834$11969_Y - connect \$1 $not$libresoc.v:182835$11970_Y - connect \$3 $and$libresoc.v:182836$11971_Y - connect \$5 $or$libresoc.v:182837$11972_Y - connect \$7 $not$libresoc.v:182838$11973_Y + connect \$9 $and$libresoc.v:185135$12150_Y + connect \$11 $or$libresoc.v:185136$12151_Y + connect \$13 $not$libresoc.v:185137$12152_Y + connect \$15 $or$libresoc.v:185138$12153_Y + connect \$1 $not$libresoc.v:185139$12154_Y + connect \$3 $and$libresoc.v:185140$12155_Y + connect \$5 $or$libresoc.v:185141$12156_Y + connect \$7 $not$libresoc.v:185142$12157_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182857.1-182915.10" +attribute \src "libresoc.v:185161.1-185219.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:182858.7-182858.20" + attribute \src "libresoc.v:185162.7-185162.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182903.3-182911.6" - wire $0\q_int$next[0:0]$11990 - attribute \src "libresoc.v:182901.3-182902.27" + attribute \src "libresoc.v:185207.3-185215.6" + wire $0\q_int$next[0:0]$12174 + attribute \src "libresoc.v:185205.3-185206.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182903.3-182911.6" - wire $1\q_int$next[0:0]$11991 - attribute \src "libresoc.v:182880.7-182880.19" + attribute \src "libresoc.v:185207.3-185215.6" + wire $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185184.7-185184.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182893.17-182893.96" - wire $and$libresoc.v:182893$11980_Y - attribute \src "libresoc.v:182898.17-182898.96" - wire $and$libresoc.v:182898$11985_Y - attribute \src "libresoc.v:182895.18-182895.94" - wire $not$libresoc.v:182895$11982_Y - attribute \src "libresoc.v:182897.17-182897.93" - wire $not$libresoc.v:182897$11984_Y - attribute \src "libresoc.v:182900.17-182900.93" - wire $not$libresoc.v:182900$11987_Y - attribute \src "libresoc.v:182894.18-182894.99" - wire $or$libresoc.v:182894$11981_Y - attribute \src "libresoc.v:182896.18-182896.100" - wire $or$libresoc.v:182896$11983_Y - attribute \src "libresoc.v:182899.17-182899.98" - wire $or$libresoc.v:182899$11986_Y + attribute \src "libresoc.v:185197.17-185197.96" + wire $and$libresoc.v:185197$12164_Y + attribute \src "libresoc.v:185202.17-185202.96" + wire $and$libresoc.v:185202$12169_Y + attribute \src "libresoc.v:185199.18-185199.94" + wire $not$libresoc.v:185199$12166_Y + attribute \src "libresoc.v:185201.17-185201.93" + wire $not$libresoc.v:185201$12168_Y + attribute \src "libresoc.v:185204.17-185204.93" + wire $not$libresoc.v:185204$12171_Y + attribute \src "libresoc.v:185198.18-185198.99" + wire $or$libresoc.v:185198$12165_Y + attribute \src "libresoc.v:185200.18-185200.100" + wire $or$libresoc.v:185200$12167_Y + attribute \src "libresoc.v:185203.17-185203.98" + wire $or$libresoc.v:185203$12170_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378982,11 +382991,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182858.7-182858.15" + attribute \src "libresoc.v:185162.7-185162.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379003,7 +383012,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182893$11980 + cell $and $and$libresoc.v:185197$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379011,10 +383020,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182893$11980_Y + connect \Y $and$libresoc.v:185197$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182898$11985 + cell $and $and$libresoc.v:185202$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379022,34 +383031,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182898$11985_Y + connect \Y $and$libresoc.v:185202$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182895$11982 + cell $not $not$libresoc.v:185199$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182895$11982_Y + connect \Y $not$libresoc.v:185199$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182897$11984 + cell $not $not$libresoc.v:185201$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182897$11984_Y + connect \Y $not$libresoc.v:185201$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182900$11987 + cell $not $not$libresoc.v:185204$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182900$11987_Y + connect \Y $not$libresoc.v:185204$12171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182894$11981 + cell $or $or$libresoc.v:185198$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379057,10 +383066,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182894$11981_Y + connect \Y $or$libresoc.v:185198$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182896$11983 + cell $or $or$libresoc.v:185200$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379068,10 +383077,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182896$11983_Y + connect \Y $or$libresoc.v:185200$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182899$11986 + cell $or $or$libresoc.v:185203$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379079,39 +383088,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182899$11986_Y + connect \Y $or$libresoc.v:185203$12170_Y end - attribute \src "libresoc.v:182858.7-182858.20" - process $proc$libresoc.v:182858$11992 + attribute \src "libresoc.v:185162.7-185162.20" + process $proc$libresoc.v:185162$12176 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182880.7-182880.19" - process $proc$libresoc.v:182880$11993 + attribute \src "libresoc.v:185184.7-185184.19" + process $proc$libresoc.v:185184$12177 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182901.3-182902.27" - process $proc$libresoc.v:182901$11988 + attribute \src "libresoc.v:185205.3-185206.27" + process $proc$libresoc.v:185205$12172 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182903.3-182911.6" - process $proc$libresoc.v:182903$11989 + attribute \src "libresoc.v:185207.3-185215.6" + process $proc$libresoc.v:185207$12173 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11990 $1\q_int$next[0:0]$11991 - attribute \src "libresoc.v:182904.5-182904.29" + assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 + attribute \src "libresoc.v:185208.5-185208.29" switch \initial - attribute \src "libresoc.v:182904.9-182904.17" + attribute \src "libresoc.v:185208.9-185208.17" case 1'1 case end @@ -379120,56 +383129,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11991 1'0 + assign $1\q_int$next[0:0]$12175 1'0 case - assign $1\q_int$next[0:0]$11991 \$5 + assign $1\q_int$next[0:0]$12175 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11990 + update \q_int$next $0\q_int$next[0:0]$12174 end - connect \$9 $and$libresoc.v:182893$11980_Y - connect \$11 $or$libresoc.v:182894$11981_Y - connect \$13 $not$libresoc.v:182895$11982_Y - connect \$15 $or$libresoc.v:182896$11983_Y - connect \$1 $not$libresoc.v:182897$11984_Y - connect \$3 $and$libresoc.v:182898$11985_Y - connect \$5 $or$libresoc.v:182899$11986_Y - connect \$7 $not$libresoc.v:182900$11987_Y + connect \$9 $and$libresoc.v:185197$12164_Y + connect \$11 $or$libresoc.v:185198$12165_Y + connect \$13 $not$libresoc.v:185199$12166_Y + connect \$15 $or$libresoc.v:185200$12167_Y + connect \$1 $not$libresoc.v:185201$12168_Y + connect \$3 $and$libresoc.v:185202$12169_Y + connect \$5 $or$libresoc.v:185203$12170_Y + connect \$7 $not$libresoc.v:185204$12171_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182919.1-182977.10" +attribute \src "libresoc.v:185223.1-185281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:182920.7-182920.20" + attribute \src "libresoc.v:185224.7-185224.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182965.3-182973.6" - wire $0\q_int$next[0:0]$12004 - attribute \src "libresoc.v:182963.3-182964.27" + attribute \src "libresoc.v:185269.3-185277.6" + wire $0\q_int$next[0:0]$12188 + attribute \src "libresoc.v:185267.3-185268.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182965.3-182973.6" - wire $1\q_int$next[0:0]$12005 - attribute \src "libresoc.v:182942.7-182942.19" + attribute \src "libresoc.v:185269.3-185277.6" + wire $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185246.7-185246.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182955.17-182955.96" - wire $and$libresoc.v:182955$11994_Y - attribute \src "libresoc.v:182960.17-182960.96" - wire $and$libresoc.v:182960$11999_Y - attribute \src "libresoc.v:182957.18-182957.94" - wire $not$libresoc.v:182957$11996_Y - attribute \src "libresoc.v:182959.17-182959.93" - wire $not$libresoc.v:182959$11998_Y - attribute \src "libresoc.v:182962.17-182962.93" - wire $not$libresoc.v:182962$12001_Y - attribute \src "libresoc.v:182956.18-182956.99" - wire $or$libresoc.v:182956$11995_Y - attribute \src "libresoc.v:182958.18-182958.100" - wire $or$libresoc.v:182958$11997_Y - attribute \src "libresoc.v:182961.17-182961.98" - wire $or$libresoc.v:182961$12000_Y + attribute \src "libresoc.v:185259.17-185259.96" + wire $and$libresoc.v:185259$12178_Y + attribute \src "libresoc.v:185264.17-185264.96" + wire $and$libresoc.v:185264$12183_Y + attribute \src "libresoc.v:185261.18-185261.94" + wire $not$libresoc.v:185261$12180_Y + attribute \src "libresoc.v:185263.17-185263.93" + wire $not$libresoc.v:185263$12182_Y + attribute \src "libresoc.v:185266.17-185266.93" + wire $not$libresoc.v:185266$12185_Y + attribute \src "libresoc.v:185260.18-185260.99" + wire $or$libresoc.v:185260$12179_Y + attribute \src "libresoc.v:185262.18-185262.100" + wire $or$libresoc.v:185262$12181_Y + attribute \src "libresoc.v:185265.17-185265.98" + wire $or$libresoc.v:185265$12184_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379186,11 +383195,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182920.7-182920.15" + attribute \src "libresoc.v:185224.7-185224.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379207,7 +383216,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:182955$11994 + cell $and $and$libresoc.v:185259$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379215,10 +383224,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182955$11994_Y + connect \Y $and$libresoc.v:185259$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:182960$11999 + cell $and $and$libresoc.v:185264$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379226,34 +383235,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182960$11999_Y + connect \Y $and$libresoc.v:185264$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:182957$11996 + cell $not $not$libresoc.v:185261$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:182957$11996_Y + connect \Y $not$libresoc.v:185261$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:182959$11998 + cell $not $not$libresoc.v:185263$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182959$11998_Y + connect \Y $not$libresoc.v:185263$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:182962$12001 + cell $not $not$libresoc.v:185266$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:182962$12001_Y + connect \Y $not$libresoc.v:185266$12185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:182956$11995 + cell $or $or$libresoc.v:185260$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379261,10 +383270,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:182956$11995_Y + connect \Y $or$libresoc.v:185260$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:182958$11997 + cell $or $or$libresoc.v:185262$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379272,10 +383281,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:182958$11997_Y + connect \Y $or$libresoc.v:185262$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:182961$12000 + cell $or $or$libresoc.v:185265$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379283,39 +383292,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:182961$12000_Y + connect \Y $or$libresoc.v:185265$12184_Y end - attribute \src "libresoc.v:182920.7-182920.20" - process $proc$libresoc.v:182920$12006 + attribute \src "libresoc.v:185224.7-185224.20" + process $proc$libresoc.v:185224$12190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182942.7-182942.19" - process $proc$libresoc.v:182942$12007 + attribute \src "libresoc.v:185246.7-185246.19" + process $proc$libresoc.v:185246$12191 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182963.3-182964.27" - process $proc$libresoc.v:182963$12002 + attribute \src "libresoc.v:185267.3-185268.27" + process $proc$libresoc.v:185267$12186 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182965.3-182973.6" - process $proc$libresoc.v:182965$12003 + attribute \src "libresoc.v:185269.3-185277.6" + process $proc$libresoc.v:185269$12187 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12004 $1\q_int$next[0:0]$12005 - attribute \src "libresoc.v:182966.5-182966.29" + assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 + attribute \src "libresoc.v:185270.5-185270.29" switch \initial - attribute \src "libresoc.v:182966.9-182966.17" + attribute \src "libresoc.v:185270.9-185270.17" case 1'1 case end @@ -379324,56 +383333,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12005 1'0 + assign $1\q_int$next[0:0]$12189 1'0 case - assign $1\q_int$next[0:0]$12005 \$5 + assign $1\q_int$next[0:0]$12189 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12004 + update \q_int$next $0\q_int$next[0:0]$12188 end - connect \$9 $and$libresoc.v:182955$11994_Y - connect \$11 $or$libresoc.v:182956$11995_Y - connect \$13 $not$libresoc.v:182957$11996_Y - connect \$15 $or$libresoc.v:182958$11997_Y - connect \$1 $not$libresoc.v:182959$11998_Y - connect \$3 $and$libresoc.v:182960$11999_Y - connect \$5 $or$libresoc.v:182961$12000_Y - connect \$7 $not$libresoc.v:182962$12001_Y + connect \$9 $and$libresoc.v:185259$12178_Y + connect \$11 $or$libresoc.v:185260$12179_Y + connect \$13 $not$libresoc.v:185261$12180_Y + connect \$15 $or$libresoc.v:185262$12181_Y + connect \$1 $not$libresoc.v:185263$12182_Y + connect \$3 $and$libresoc.v:185264$12183_Y + connect \$5 $or$libresoc.v:185265$12184_Y + connect \$7 $not$libresoc.v:185266$12185_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:182981.1-183039.10" +attribute \src "libresoc.v:185285.1-185343.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:182982.7-182982.20" + attribute \src "libresoc.v:185286.7-185286.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183027.3-183035.6" - wire $0\q_int$next[0:0]$12018 - attribute \src "libresoc.v:183025.3-183026.27" + attribute \src "libresoc.v:185331.3-185339.6" + wire $0\q_int$next[0:0]$12202 + attribute \src "libresoc.v:185329.3-185330.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183027.3-183035.6" - wire $1\q_int$next[0:0]$12019 - attribute \src "libresoc.v:183004.7-183004.19" + attribute \src "libresoc.v:185331.3-185339.6" + wire $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185308.7-185308.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183017.17-183017.96" - wire $and$libresoc.v:183017$12008_Y - attribute \src "libresoc.v:183022.17-183022.96" - wire $and$libresoc.v:183022$12013_Y - attribute \src "libresoc.v:183019.18-183019.94" - wire $not$libresoc.v:183019$12010_Y - attribute \src "libresoc.v:183021.17-183021.93" - wire $not$libresoc.v:183021$12012_Y - attribute \src "libresoc.v:183024.17-183024.93" - wire $not$libresoc.v:183024$12015_Y - attribute \src "libresoc.v:183018.18-183018.99" - wire $or$libresoc.v:183018$12009_Y - attribute \src "libresoc.v:183020.18-183020.100" - wire $or$libresoc.v:183020$12011_Y - attribute \src "libresoc.v:183023.17-183023.98" - wire $or$libresoc.v:183023$12014_Y + attribute \src "libresoc.v:185321.17-185321.96" + wire $and$libresoc.v:185321$12192_Y + attribute \src "libresoc.v:185326.17-185326.96" + wire $and$libresoc.v:185326$12197_Y + attribute \src "libresoc.v:185323.18-185323.94" + wire $not$libresoc.v:185323$12194_Y + attribute \src "libresoc.v:185325.17-185325.93" + wire $not$libresoc.v:185325$12196_Y + attribute \src "libresoc.v:185328.17-185328.93" + wire $not$libresoc.v:185328$12199_Y + attribute \src "libresoc.v:185322.18-185322.99" + wire $or$libresoc.v:185322$12193_Y + attribute \src "libresoc.v:185324.18-185324.100" + wire $or$libresoc.v:185324$12195_Y + attribute \src "libresoc.v:185327.17-185327.98" + wire $or$libresoc.v:185327$12198_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379390,11 +383399,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:182982.7-182982.15" + attribute \src "libresoc.v:185286.7-185286.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379411,7 +383420,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183017$12008 + cell $and $and$libresoc.v:185321$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379419,10 +383428,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183017$12008_Y + connect \Y $and$libresoc.v:185321$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183022$12013 + cell $and $and$libresoc.v:185326$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379430,34 +383439,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183022$12013_Y + connect \Y $and$libresoc.v:185326$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183019$12010 + cell $not $not$libresoc.v:185323$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183019$12010_Y + connect \Y $not$libresoc.v:185323$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183021$12012 + cell $not $not$libresoc.v:185325$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183021$12012_Y + connect \Y $not$libresoc.v:185325$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183024$12015 + cell $not $not$libresoc.v:185328$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183024$12015_Y + connect \Y $not$libresoc.v:185328$12199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183018$12009 + cell $or $or$libresoc.v:185322$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379465,10 +383474,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183018$12009_Y + connect \Y $or$libresoc.v:185322$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183020$12011 + cell $or $or$libresoc.v:185324$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379476,10 +383485,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183020$12011_Y + connect \Y $or$libresoc.v:185324$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183023$12014 + cell $or $or$libresoc.v:185327$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379487,39 +383496,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183023$12014_Y + connect \Y $or$libresoc.v:185327$12198_Y end - attribute \src "libresoc.v:182982.7-182982.20" - process $proc$libresoc.v:182982$12020 + attribute \src "libresoc.v:185286.7-185286.20" + process $proc$libresoc.v:185286$12204 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183004.7-183004.19" - process $proc$libresoc.v:183004$12021 + attribute \src "libresoc.v:185308.7-185308.19" + process $proc$libresoc.v:185308$12205 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183025.3-183026.27" - process $proc$libresoc.v:183025$12016 + attribute \src "libresoc.v:185329.3-185330.27" + process $proc$libresoc.v:185329$12200 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183027.3-183035.6" - process $proc$libresoc.v:183027$12017 + attribute \src "libresoc.v:185331.3-185339.6" + process $proc$libresoc.v:185331$12201 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12018 $1\q_int$next[0:0]$12019 - attribute \src "libresoc.v:183028.5-183028.29" + assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 + attribute \src "libresoc.v:185332.5-185332.29" switch \initial - attribute \src "libresoc.v:183028.9-183028.17" + attribute \src "libresoc.v:185332.9-185332.17" case 1'1 case end @@ -379528,56 +383537,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12019 1'0 + assign $1\q_int$next[0:0]$12203 1'0 case - assign $1\q_int$next[0:0]$12019 \$5 + assign $1\q_int$next[0:0]$12203 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12018 + update \q_int$next $0\q_int$next[0:0]$12202 end - connect \$9 $and$libresoc.v:183017$12008_Y - connect \$11 $or$libresoc.v:183018$12009_Y - connect \$13 $not$libresoc.v:183019$12010_Y - connect \$15 $or$libresoc.v:183020$12011_Y - connect \$1 $not$libresoc.v:183021$12012_Y - connect \$3 $and$libresoc.v:183022$12013_Y - connect \$5 $or$libresoc.v:183023$12014_Y - connect \$7 $not$libresoc.v:183024$12015_Y + connect \$9 $and$libresoc.v:185321$12192_Y + connect \$11 $or$libresoc.v:185322$12193_Y + connect \$13 $not$libresoc.v:185323$12194_Y + connect \$15 $or$libresoc.v:185324$12195_Y + connect \$1 $not$libresoc.v:185325$12196_Y + connect \$3 $and$libresoc.v:185326$12197_Y + connect \$5 $or$libresoc.v:185327$12198_Y + connect \$7 $not$libresoc.v:185328$12199_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183043.1-183101.10" +attribute \src "libresoc.v:185347.1-185405.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:183044.7-183044.20" + attribute \src "libresoc.v:185348.7-185348.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183089.3-183097.6" - wire $0\q_int$next[0:0]$12032 - attribute \src "libresoc.v:183087.3-183088.27" + attribute \src "libresoc.v:185393.3-185401.6" + wire $0\q_int$next[0:0]$12216 + attribute \src "libresoc.v:185391.3-185392.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183089.3-183097.6" - wire $1\q_int$next[0:0]$12033 - attribute \src "libresoc.v:183066.7-183066.19" + attribute \src "libresoc.v:185393.3-185401.6" + wire $1\q_int$next[0:0]$12217 + attribute \src "libresoc.v:185370.7-185370.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183079.17-183079.96" - wire $and$libresoc.v:183079$12022_Y - attribute \src "libresoc.v:183084.17-183084.96" - wire $and$libresoc.v:183084$12027_Y - attribute \src "libresoc.v:183081.18-183081.94" - wire $not$libresoc.v:183081$12024_Y - attribute \src "libresoc.v:183083.17-183083.93" - wire $not$libresoc.v:183083$12026_Y - attribute \src "libresoc.v:183086.17-183086.93" - wire $not$libresoc.v:183086$12029_Y - attribute \src "libresoc.v:183080.18-183080.99" - wire $or$libresoc.v:183080$12023_Y - attribute \src "libresoc.v:183082.18-183082.100" - wire $or$libresoc.v:183082$12025_Y - attribute \src "libresoc.v:183085.17-183085.98" - wire $or$libresoc.v:183085$12028_Y + attribute \src "libresoc.v:185383.17-185383.96" + wire $and$libresoc.v:185383$12206_Y + attribute \src "libresoc.v:185388.17-185388.96" + wire $and$libresoc.v:185388$12211_Y + attribute \src "libresoc.v:185385.18-185385.94" + wire $not$libresoc.v:185385$12208_Y + attribute \src "libresoc.v:185387.17-185387.93" + wire $not$libresoc.v:185387$12210_Y + attribute \src "libresoc.v:185390.17-185390.93" + wire $not$libresoc.v:185390$12213_Y + attribute \src "libresoc.v:185384.18-185384.99" + wire $or$libresoc.v:185384$12207_Y + attribute \src "libresoc.v:185386.18-185386.100" + wire $or$libresoc.v:185386$12209_Y + attribute \src "libresoc.v:185389.17-185389.98" + wire $or$libresoc.v:185389$12212_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379594,11 +383603,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183044.7-183044.15" + attribute \src "libresoc.v:185348.7-185348.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379615,7 +383624,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183079$12022 + cell $and $and$libresoc.v:185383$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379623,10 +383632,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183079$12022_Y + connect \Y $and$libresoc.v:185383$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183084$12027 + cell $and $and$libresoc.v:185388$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379634,34 +383643,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183084$12027_Y + connect \Y $and$libresoc.v:185388$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183081$12024 + cell $not $not$libresoc.v:185385$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183081$12024_Y + connect \Y $not$libresoc.v:185385$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183083$12026 + cell $not $not$libresoc.v:185387$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183083$12026_Y + connect \Y $not$libresoc.v:185387$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183086$12029 + cell $not $not$libresoc.v:185390$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183086$12029_Y + connect \Y $not$libresoc.v:185390$12213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183080$12023 + cell $or $or$libresoc.v:185384$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379669,10 +383678,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183080$12023_Y + connect \Y $or$libresoc.v:185384$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183082$12025 + cell $or $or$libresoc.v:185386$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379680,10 +383689,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183082$12025_Y + connect \Y $or$libresoc.v:185386$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183085$12028 + cell $or $or$libresoc.v:185389$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379691,39 +383700,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183085$12028_Y + connect \Y $or$libresoc.v:185389$12212_Y end - attribute \src "libresoc.v:183044.7-183044.20" - process $proc$libresoc.v:183044$12034 + attribute \src "libresoc.v:185348.7-185348.20" + process $proc$libresoc.v:185348$12218 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183066.7-183066.19" - process $proc$libresoc.v:183066$12035 + attribute \src "libresoc.v:185370.7-185370.19" + process $proc$libresoc.v:185370$12219 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183087.3-183088.27" - process $proc$libresoc.v:183087$12030 + attribute \src "libresoc.v:185391.3-185392.27" + process $proc$libresoc.v:185391$12214 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183089.3-183097.6" - process $proc$libresoc.v:183089$12031 + attribute \src "libresoc.v:185393.3-185401.6" + process $proc$libresoc.v:185393$12215 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12032 $1\q_int$next[0:0]$12033 - attribute \src "libresoc.v:183090.5-183090.29" + assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 + attribute \src "libresoc.v:185394.5-185394.29" switch \initial - attribute \src "libresoc.v:183090.9-183090.17" + attribute \src "libresoc.v:185394.9-185394.17" case 1'1 case end @@ -379732,56 +383741,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12033 1'0 + assign $1\q_int$next[0:0]$12217 1'0 case - assign $1\q_int$next[0:0]$12033 \$5 + assign $1\q_int$next[0:0]$12217 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12032 + update \q_int$next $0\q_int$next[0:0]$12216 end - connect \$9 $and$libresoc.v:183079$12022_Y - connect \$11 $or$libresoc.v:183080$12023_Y - connect \$13 $not$libresoc.v:183081$12024_Y - connect \$15 $or$libresoc.v:183082$12025_Y - connect \$1 $not$libresoc.v:183083$12026_Y - connect \$3 $and$libresoc.v:183084$12027_Y - connect \$5 $or$libresoc.v:183085$12028_Y - connect \$7 $not$libresoc.v:183086$12029_Y + connect \$9 $and$libresoc.v:185383$12206_Y + connect \$11 $or$libresoc.v:185384$12207_Y + connect \$13 $not$libresoc.v:185385$12208_Y + connect \$15 $or$libresoc.v:185386$12209_Y + connect \$1 $not$libresoc.v:185387$12210_Y + connect \$3 $and$libresoc.v:185388$12211_Y + connect \$5 $or$libresoc.v:185389$12212_Y + connect \$7 $not$libresoc.v:185390$12213_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183105.1-183163.10" +attribute \src "libresoc.v:185409.1-185467.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:183106.7-183106.20" + attribute \src "libresoc.v:185410.7-185410.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183151.3-183159.6" - wire $0\q_int$next[0:0]$12046 - attribute \src "libresoc.v:183149.3-183150.27" + attribute \src "libresoc.v:185455.3-185463.6" + wire $0\q_int$next[0:0]$12230 + attribute \src "libresoc.v:185453.3-185454.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183151.3-183159.6" - wire $1\q_int$next[0:0]$12047 - attribute \src "libresoc.v:183128.7-183128.19" + attribute \src "libresoc.v:185455.3-185463.6" + wire $1\q_int$next[0:0]$12231 + attribute \src "libresoc.v:185432.7-185432.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183141.17-183141.96" - wire $and$libresoc.v:183141$12036_Y - attribute \src "libresoc.v:183146.17-183146.96" - wire $and$libresoc.v:183146$12041_Y - attribute \src "libresoc.v:183143.18-183143.94" - wire $not$libresoc.v:183143$12038_Y - attribute \src "libresoc.v:183145.17-183145.93" - wire $not$libresoc.v:183145$12040_Y - attribute \src "libresoc.v:183148.17-183148.93" - wire $not$libresoc.v:183148$12043_Y - attribute \src "libresoc.v:183142.18-183142.99" - wire $or$libresoc.v:183142$12037_Y - attribute \src "libresoc.v:183144.18-183144.100" - wire $or$libresoc.v:183144$12039_Y - attribute \src "libresoc.v:183147.17-183147.98" - wire $or$libresoc.v:183147$12042_Y + attribute \src "libresoc.v:185445.17-185445.96" + wire $and$libresoc.v:185445$12220_Y + attribute \src "libresoc.v:185450.17-185450.96" + wire $and$libresoc.v:185450$12225_Y + attribute \src "libresoc.v:185447.18-185447.94" + wire $not$libresoc.v:185447$12222_Y + attribute \src "libresoc.v:185449.17-185449.93" + wire $not$libresoc.v:185449$12224_Y + attribute \src "libresoc.v:185452.17-185452.93" + wire $not$libresoc.v:185452$12227_Y + attribute \src "libresoc.v:185446.18-185446.99" + wire $or$libresoc.v:185446$12221_Y + attribute \src "libresoc.v:185448.18-185448.100" + wire $or$libresoc.v:185448$12223_Y + attribute \src "libresoc.v:185451.17-185451.98" + wire $or$libresoc.v:185451$12226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379798,11 +383807,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183106.7-183106.15" + attribute \src "libresoc.v:185410.7-185410.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379819,7 +383828,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183141$12036 + cell $and $and$libresoc.v:185445$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379827,10 +383836,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183141$12036_Y + connect \Y $and$libresoc.v:185445$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183146$12041 + cell $and $and$libresoc.v:185450$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379838,34 +383847,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183146$12041_Y + connect \Y $and$libresoc.v:185450$12225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183143$12038 + cell $not $not$libresoc.v:185447$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:183143$12038_Y + connect \Y $not$libresoc.v:185447$12222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183145$12040 + cell $not $not$libresoc.v:185449$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183145$12040_Y + connect \Y $not$libresoc.v:185449$12224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183148$12043 + cell $not $not$libresoc.v:185452$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:183148$12043_Y + connect \Y $not$libresoc.v:185452$12227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183142$12037 + cell $or $or$libresoc.v:185446$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379873,10 +383882,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:183142$12037_Y + connect \Y $or$libresoc.v:185446$12221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183144$12039 + cell $or $or$libresoc.v:185448$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379884,10 +383893,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:183144$12039_Y + connect \Y $or$libresoc.v:185448$12223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183147$12042 + cell $or $or$libresoc.v:185451$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379895,39 +383904,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:183147$12042_Y + connect \Y $or$libresoc.v:185451$12226_Y end - attribute \src "libresoc.v:183106.7-183106.20" - process $proc$libresoc.v:183106$12048 + attribute \src "libresoc.v:185410.7-185410.20" + process $proc$libresoc.v:185410$12232 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183128.7-183128.19" - process $proc$libresoc.v:183128$12049 + attribute \src "libresoc.v:185432.7-185432.19" + process $proc$libresoc.v:185432$12233 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183149.3-183150.27" - process $proc$libresoc.v:183149$12044 + attribute \src "libresoc.v:185453.3-185454.27" + process $proc$libresoc.v:185453$12228 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183151.3-183159.6" - process $proc$libresoc.v:183151$12045 + attribute \src "libresoc.v:185455.3-185463.6" + process $proc$libresoc.v:185455$12229 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12046 $1\q_int$next[0:0]$12047 - attribute \src "libresoc.v:183152.5-183152.29" + assign $0\q_int$next[0:0]$12230 $1\q_int$next[0:0]$12231 + attribute \src "libresoc.v:185456.5-185456.29" switch \initial - attribute \src "libresoc.v:183152.9-183152.17" + attribute \src "libresoc.v:185456.9-185456.17" case 1'1 case end @@ -379936,150 +383945,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12047 1'0 + assign $1\q_int$next[0:0]$12231 1'0 case - assign $1\q_int$next[0:0]$12047 \$5 + assign $1\q_int$next[0:0]$12231 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12046 + update \q_int$next $0\q_int$next[0:0]$12230 end - connect \$9 $and$libresoc.v:183141$12036_Y - connect \$11 $or$libresoc.v:183142$12037_Y - connect \$13 $not$libresoc.v:183143$12038_Y - connect \$15 $or$libresoc.v:183144$12039_Y - connect \$1 $not$libresoc.v:183145$12040_Y - connect \$3 $and$libresoc.v:183146$12041_Y - connect \$5 $or$libresoc.v:183147$12042_Y - connect \$7 $not$libresoc.v:183148$12043_Y + connect \$9 $and$libresoc.v:185445$12220_Y + connect \$11 $or$libresoc.v:185446$12221_Y + connect \$13 $not$libresoc.v:185447$12222_Y + connect \$15 $or$libresoc.v:185448$12223_Y + connect \$1 $not$libresoc.v:185449$12224_Y + connect \$3 $and$libresoc.v:185450$12225_Y + connect \$5 $or$libresoc.v:185451$12226_Y + connect \$7 $not$libresoc.v:185452$12227_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:183167.1-183518.10" +attribute \src "libresoc.v:185471.1-185822.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:183436.3-183445.6" + attribute \src "libresoc.v:185740.3-185749.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:183368.3-183382.6" + attribute \src "libresoc.v:185672.3-185686.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:183168.7-183168.20" + attribute \src "libresoc.v:185472.7-185472.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 7 $0\mb$8[6:0]$12097 - attribute \src "libresoc.v:183492.3-183506.6" - wire width 7 $0\me$13[6:0]$12102 - attribute \src "libresoc.v:183393.3-183404.6" + attribute \src "libresoc.v:185762.3-185795.6" + wire width 7 $0\mb$8[6:0]$12281 + attribute \src "libresoc.v:185796.3-185810.6" + wire width 7 $0\me$13[6:0]$12286 + attribute \src "libresoc.v:185697.3-185708.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:183405.3-183416.6" + attribute \src "libresoc.v:185709.3-185720.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:183417.3-183435.6" + attribute \src "libresoc.v:185721.3-185739.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:183383.3-183392.6" + attribute \src "libresoc.v:185687.3-185696.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:183446.3-183457.6" + attribute \src "libresoc.v:185750.3-185761.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:183436.3-183445.6" + attribute \src "libresoc.v:185740.3-185749.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:183368.3-183382.6" + attribute \src "libresoc.v:185672.3-185686.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 7 $1\mb$8[6:0]$12098 - attribute \src "libresoc.v:183492.3-183506.6" - wire width 7 $1\me$13[6:0]$12103 - attribute \src "libresoc.v:183393.3-183404.6" + attribute \src "libresoc.v:185762.3-185795.6" + wire width 7 $1\mb$8[6:0]$12282 + attribute \src "libresoc.v:185796.3-185810.6" + wire width 7 $1\me$13[6:0]$12287 + attribute \src "libresoc.v:185697.3-185708.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:183405.3-183416.6" + attribute \src "libresoc.v:185709.3-185720.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:183417.3-183435.6" + attribute \src "libresoc.v:185721.3-185739.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:183383.3-183392.6" + attribute \src "libresoc.v:185687.3-185696.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:183446.3-183457.6" + attribute \src "libresoc.v:185750.3-185761.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:183458.3-183491.6" - wire width 2 $2\mb$8[6:5]$12099 - attribute \src "libresoc.v:183458.3-183491.6" - wire width 2 $3\mb$8[6:5]$12100 - attribute \src "libresoc.v:183319.18-183319.118" - wire $and$libresoc.v:183319$12053_Y - attribute \src "libresoc.v:183321.18-183321.114" - wire $and$libresoc.v:183321$12055_Y - attribute \src "libresoc.v:183330.18-183330.113" - wire $and$libresoc.v:183330$12064_Y - attribute \src "libresoc.v:183332.18-183332.114" - wire $and$libresoc.v:183332$12066_Y - attribute \src "libresoc.v:183334.18-183334.114" - wire $and$libresoc.v:183334$12068_Y - attribute \src "libresoc.v:183335.18-183335.103" - wire width 64 $and$libresoc.v:183335$12069_Y - attribute \src "libresoc.v:183336.18-183336.106" - wire width 64 $and$libresoc.v:183336$12070_Y - attribute \src "libresoc.v:183338.18-183338.103" - wire width 64 $and$libresoc.v:183338$12072_Y - attribute \src "libresoc.v:183340.18-183340.105" - wire width 64 $and$libresoc.v:183340$12074_Y - attribute \src "libresoc.v:183343.18-183343.106" - wire width 64 $and$libresoc.v:183343$12077_Y - attribute \src "libresoc.v:183346.18-183346.105" - wire width 64 $and$libresoc.v:183346$12080_Y - attribute \src "libresoc.v:183348.17-183348.109" - wire $and$libresoc.v:183348$12082_Y - attribute \src "libresoc.v:183349.18-183349.104" - wire width 64 $and$libresoc.v:183349$12083_Y - attribute \src "libresoc.v:183353.18-183353.105" - wire width 64 $and$libresoc.v:183353$12087_Y - attribute \src "libresoc.v:183317.17-183317.98" - wire width 7 $extend$libresoc.v:183317$12050_Y - attribute \src "libresoc.v:183333.18-183333.122" - wire $gt$libresoc.v:183333$12067_Y - attribute \src "libresoc.v:183323.18-183323.111" - wire $le$libresoc.v:183323$12057_Y - attribute \src "libresoc.v:183325.18-183325.111" - wire $le$libresoc.v:183325$12059_Y - attribute \src "libresoc.v:183326.17-183326.117" - wire width 7 $neg$libresoc.v:183326$12060_Y - attribute \src "libresoc.v:183318.18-183318.103" - wire $not$libresoc.v:183318$12052_Y - attribute \src "libresoc.v:183320.18-183320.108" - wire $not$libresoc.v:183320$12054_Y - attribute \src "libresoc.v:183322.18-183322.105" - wire width 6 $not$libresoc.v:183322$12056_Y - attribute \src "libresoc.v:183328.18-183328.112" - wire width 64 $not$libresoc.v:183328$12062_Y - attribute \src "libresoc.v:183329.18-183329.109" - wire $not$libresoc.v:183329$12063_Y - attribute \src "libresoc.v:183337.17-183337.105" - wire $not$libresoc.v:183337$12071_Y - attribute \src "libresoc.v:183339.18-183339.102" - wire width 64 $not$libresoc.v:183339$12073_Y - attribute \src "libresoc.v:183345.18-183345.102" - wire width 64 $not$libresoc.v:183345$12079_Y - attribute \src "libresoc.v:183350.18-183350.100" - wire width 64 $not$libresoc.v:183350$12084_Y - attribute \src "libresoc.v:183352.18-183352.100" - wire width 64 $not$libresoc.v:183352$12086_Y - attribute \src "libresoc.v:183331.18-183331.115" - wire $or$libresoc.v:183331$12065_Y - attribute \src "libresoc.v:183341.18-183341.108" - wire width 64 $or$libresoc.v:183341$12075_Y - attribute \src "libresoc.v:183342.18-183342.103" - wire width 64 $or$libresoc.v:183342$12076_Y - attribute \src "libresoc.v:183344.18-183344.103" - wire width 64 $or$libresoc.v:183344$12078_Y - attribute \src "libresoc.v:183347.18-183347.108" - wire width 64 $or$libresoc.v:183347$12081_Y - attribute \src "libresoc.v:183351.18-183351.106" - wire width 64 $or$libresoc.v:183351$12085_Y - attribute \src "libresoc.v:183317.17-183317.98" - wire width 7 $pos$libresoc.v:183317$12051_Y - attribute \src "libresoc.v:183354.18-183354.102" - wire $reduce_or$libresoc.v:183354$12088_Y - attribute \src "libresoc.v:183324.18-183324.109" - wire width 8 $sub$libresoc.v:183324$12058_Y - attribute \src "libresoc.v:183327.18-183327.110" - wire width 8 $sub$libresoc.v:183327$12061_Y + attribute \src "libresoc.v:185762.3-185795.6" + wire width 2 $2\mb$8[6:5]$12283 + attribute \src "libresoc.v:185762.3-185795.6" + wire width 2 $3\mb$8[6:5]$12284 + attribute \src "libresoc.v:185623.18-185623.118" + wire $and$libresoc.v:185623$12237_Y + attribute \src "libresoc.v:185625.18-185625.114" + wire $and$libresoc.v:185625$12239_Y + attribute \src "libresoc.v:185634.18-185634.113" + wire $and$libresoc.v:185634$12248_Y + attribute \src "libresoc.v:185636.18-185636.114" + wire $and$libresoc.v:185636$12250_Y + attribute \src "libresoc.v:185638.18-185638.114" + wire $and$libresoc.v:185638$12252_Y + attribute \src "libresoc.v:185639.18-185639.103" + wire width 64 $and$libresoc.v:185639$12253_Y + attribute \src "libresoc.v:185640.18-185640.106" + wire width 64 $and$libresoc.v:185640$12254_Y + attribute \src "libresoc.v:185642.18-185642.103" + wire width 64 $and$libresoc.v:185642$12256_Y + attribute \src "libresoc.v:185644.18-185644.105" + wire width 64 $and$libresoc.v:185644$12258_Y + attribute \src "libresoc.v:185647.18-185647.106" + wire width 64 $and$libresoc.v:185647$12261_Y + attribute \src "libresoc.v:185650.18-185650.105" + wire width 64 $and$libresoc.v:185650$12264_Y + attribute \src "libresoc.v:185652.17-185652.109" + wire $and$libresoc.v:185652$12266_Y + attribute \src "libresoc.v:185653.18-185653.104" + wire width 64 $and$libresoc.v:185653$12267_Y + attribute \src "libresoc.v:185657.18-185657.105" + wire width 64 $and$libresoc.v:185657$12271_Y + attribute \src "libresoc.v:185621.17-185621.98" + wire width 7 $extend$libresoc.v:185621$12234_Y + attribute \src "libresoc.v:185637.18-185637.122" + wire $gt$libresoc.v:185637$12251_Y + attribute \src "libresoc.v:185627.18-185627.111" + wire $le$libresoc.v:185627$12241_Y + attribute \src "libresoc.v:185629.18-185629.111" + wire $le$libresoc.v:185629$12243_Y + attribute \src "libresoc.v:185630.17-185630.117" + wire width 7 $neg$libresoc.v:185630$12244_Y + attribute \src "libresoc.v:185622.18-185622.103" + wire $not$libresoc.v:185622$12236_Y + attribute \src "libresoc.v:185624.18-185624.108" + wire $not$libresoc.v:185624$12238_Y + attribute \src "libresoc.v:185626.18-185626.105" + wire width 6 $not$libresoc.v:185626$12240_Y + attribute \src "libresoc.v:185632.18-185632.112" + wire width 64 $not$libresoc.v:185632$12246_Y + attribute \src "libresoc.v:185633.18-185633.109" + wire $not$libresoc.v:185633$12247_Y + attribute \src "libresoc.v:185641.17-185641.105" + wire $not$libresoc.v:185641$12255_Y + attribute \src "libresoc.v:185643.18-185643.102" + wire width 64 $not$libresoc.v:185643$12257_Y + attribute \src "libresoc.v:185649.18-185649.102" + wire width 64 $not$libresoc.v:185649$12263_Y + attribute \src "libresoc.v:185654.18-185654.100" + wire width 64 $not$libresoc.v:185654$12268_Y + attribute \src "libresoc.v:185656.18-185656.100" + wire width 64 $not$libresoc.v:185656$12270_Y + attribute \src "libresoc.v:185635.18-185635.115" + wire $or$libresoc.v:185635$12249_Y + attribute \src "libresoc.v:185645.18-185645.108" + wire width 64 $or$libresoc.v:185645$12259_Y + attribute \src "libresoc.v:185646.18-185646.103" + wire width 64 $or$libresoc.v:185646$12260_Y + attribute \src "libresoc.v:185648.18-185648.103" + wire width 64 $or$libresoc.v:185648$12262_Y + attribute \src "libresoc.v:185651.18-185651.108" + wire width 64 $or$libresoc.v:185651$12265_Y + attribute \src "libresoc.v:185655.18-185655.106" + wire width 64 $or$libresoc.v:185655$12269_Y + attribute \src "libresoc.v:185621.17-185621.98" + wire width 7 $pos$libresoc.v:185621$12235_Y + attribute \src "libresoc.v:185658.18-185658.102" + wire $reduce_or$libresoc.v:185658$12272_Y + attribute \src "libresoc.v:185628.18-185628.109" + wire width 8 $sub$libresoc.v:185628$12242_Y + attribute \src "libresoc.v:185631.18-185631.110" + wire width 8 $sub$libresoc.v:185631$12245_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -380172,7 +384181,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:183168.7-183168.15" + attribute \src "libresoc.v:185472.7-185472.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -380229,7 +384238,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:183319$12053 + cell $and $and$libresoc.v:185623$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380237,10 +384246,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:183319$12053_Y + connect \Y $and$libresoc.v:185623$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:183321$12055 + cell $and $and$libresoc.v:185625$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380248,10 +384257,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:183321$12055_Y + connect \Y $and$libresoc.v:185625$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:183330$12064 + cell $and $and$libresoc.v:185634$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380259,10 +384268,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:183330$12064_Y + connect \Y $and$libresoc.v:185634$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:183332$12066 + cell $and $and$libresoc.v:185636$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380270,10 +384279,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:183332$12066_Y + connect \Y $and$libresoc.v:185636$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:183334$12068 + cell $and $and$libresoc.v:185638$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380281,10 +384290,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:183334$12068_Y + connect \Y $and$libresoc.v:185638$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183335$12069 + cell $and $and$libresoc.v:185639$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380292,10 +384301,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:183335$12069_Y + connect \Y $and$libresoc.v:185639$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183336$12070 + cell $and $and$libresoc.v:185640$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380303,10 +384312,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:183336$12070_Y + connect \Y $and$libresoc.v:185640$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183338$12072 + cell $and $and$libresoc.v:185642$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380314,10 +384323,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:183338$12072_Y + connect \Y $and$libresoc.v:185642$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:183340$12074 + cell $and $and$libresoc.v:185644$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380325,10 +384334,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:183340$12074_Y + connect \Y $and$libresoc.v:185644$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:183343$12077 + cell $and $and$libresoc.v:185647$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380336,10 +384345,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:183343$12077_Y + connect \Y $and$libresoc.v:185647$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:183346$12080 + cell $and $and$libresoc.v:185650$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380347,10 +384356,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:183346$12080_Y + connect \Y $and$libresoc.v:185650$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:183348$12082 + cell $and $and$libresoc.v:185652$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380358,10 +384367,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:183348$12082_Y + connect \Y $and$libresoc.v:185652$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:183349$12083 + cell $and $and$libresoc.v:185653$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380369,10 +384378,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:183349$12083_Y + connect \Y $and$libresoc.v:185653$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:183353$12087 + cell $and $and$libresoc.v:185657$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380380,18 +384389,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:183353$12087_Y + connect \Y $and$libresoc.v:185657$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:183317$12050 + cell $pos $extend$libresoc.v:185621$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:183317$12050_Y + connect \Y $extend$libresoc.v:185621$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:183333$12067 + cell $gt $gt$libresoc.v:185637$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380399,10 +384408,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:183333$12067_Y + connect \Y $gt$libresoc.v:185637$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:183323$12057 + cell $le $le$libresoc.v:185627$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380410,10 +384419,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:183323$12057_Y + connect \Y $le$libresoc.v:185627$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:183325$12059 + cell $le $le$libresoc.v:185629$12243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380421,98 +384430,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:183325$12059_Y + connect \Y $le$libresoc.v:185629$12243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:183326$12060 + cell $neg $neg$libresoc.v:185630$12244 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:183326$12060_Y + connect \Y $neg$libresoc.v:185630$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:183318$12052 + cell $not $not$libresoc.v:185622$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:183318$12052_Y + connect \Y $not$libresoc.v:185622$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:183320$12054 + cell $not $not$libresoc.v:185624$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:183320$12054_Y + connect \Y $not$libresoc.v:185624$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:183322$12056 + cell $not $not$libresoc.v:185626$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:183322$12056_Y + connect \Y $not$libresoc.v:185626$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:183328$12062 + cell $not $not$libresoc.v:185632$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:183328$12062_Y + connect \Y $not$libresoc.v:185632$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:183329$12063 + cell $not $not$libresoc.v:185633$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:183329$12063_Y + connect \Y $not$libresoc.v:185633$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:183337$12071 + cell $not $not$libresoc.v:185641$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:183337$12071_Y + connect \Y $not$libresoc.v:185641$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:183339$12073 + cell $not $not$libresoc.v:185643$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:183339$12073_Y + connect \Y $not$libresoc.v:185643$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:183345$12079 + cell $not $not$libresoc.v:185649$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:183345$12079_Y + connect \Y $not$libresoc.v:185649$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:183350$12084 + cell $not $not$libresoc.v:185654$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:183350$12084_Y + connect \Y $not$libresoc.v:185654$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:183352$12086 + cell $not $not$libresoc.v:185656$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:183352$12086_Y + connect \Y $not$libresoc.v:185656$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:183331$12065 + cell $or $or$libresoc.v:185635$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380520,10 +384529,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:183331$12065_Y + connect \Y $or$libresoc.v:185635$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:183341$12075 + cell $or $or$libresoc.v:185645$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380531,10 +384540,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:183341$12075_Y + connect \Y $or$libresoc.v:185645$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183342$12076 + cell $or $or$libresoc.v:185646$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380542,10 +384551,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:183342$12076_Y + connect \Y $or$libresoc.v:185646$12260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183344$12078 + cell $or $or$libresoc.v:185648$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380553,10 +384562,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:183344$12078_Y + connect \Y $or$libresoc.v:185648$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:183347$12081 + cell $or $or$libresoc.v:185651$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380564,10 +384573,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:183347$12081_Y + connect \Y $or$libresoc.v:185651$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:183351$12085 + cell $or $or$libresoc.v:185655$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -380575,26 +384584,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:183351$12085_Y + connect \Y $or$libresoc.v:185655$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:183317$12051 + cell $pos $pos$libresoc.v:185621$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:183317$12050_Y - connect \Y $pos$libresoc.v:183317$12051_Y + connect \A $extend$libresoc.v:185621$12234_Y + connect \Y $pos$libresoc.v:185621$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:183354$12088 + cell $reduce_or $reduce_or$libresoc.v:185658$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:183354$12088_Y + connect \Y $reduce_or$libresoc.v:185658$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:183324$12058 + cell $sub $sub$libresoc.v:185628$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380602,10 +384611,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:183324$12058_Y + connect \Y $sub$libresoc.v:185628$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:183327$12061 + cell $sub $sub$libresoc.v:185631$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -380613,42 +384622,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:183327$12061_Y + connect \Y $sub$libresoc.v:185631$12245_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:183355.13-183358.4" + attribute \src "libresoc.v:185659.13-185662.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:183359.14-183362.4" + attribute \src "libresoc.v:185663.14-185666.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:183363.8-183367.4" + attribute \src "libresoc.v:185667.8-185671.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:183168.7-183168.20" - process $proc$libresoc.v:183168$12104 + attribute \src "libresoc.v:185472.7-185472.20" + process $proc$libresoc.v:185472$12288 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183368.3-183382.6" - process $proc$libresoc.v:183368$12089 + attribute \src "libresoc.v:185672.3-185686.6" + process $proc$libresoc.v:185672$12273 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:183369.5-183369.29" + attribute \src "libresoc.v:185673.5-185673.29" switch \initial - attribute \src "libresoc.v:183369.9-183369.17" + attribute \src "libresoc.v:185673.9-185673.17" case 1'1 case end @@ -380670,14 +384679,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:183383.3-183392.6" - process $proc$libresoc.v:183383$12090 + attribute \src "libresoc.v:185687.3-185696.6" + process $proc$libresoc.v:185687$12274 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:183384.5-183384.29" + attribute \src "libresoc.v:185688.5-185688.29" switch \initial - attribute \src "libresoc.v:183384.9-183384.17" + attribute \src "libresoc.v:185688.9-185688.17" case 1'1 case end @@ -380693,13 +384702,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:183393.3-183404.6" - process $proc$libresoc.v:183393$12091 + attribute \src "libresoc.v:185697.3-185708.6" + process $proc$libresoc.v:185697$12275 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:183394.5-183394.29" + attribute \src "libresoc.v:185698.5-185698.29" switch \initial - attribute \src "libresoc.v:183394.9-183394.17" + attribute \src "libresoc.v:185698.9-185698.17" case 1'1 case end @@ -380717,13 +384726,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:183405.3-183416.6" - process $proc$libresoc.v:183405$12092 + attribute \src "libresoc.v:185709.3-185720.6" + process $proc$libresoc.v:185709$12276 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:183406.5-183406.29" + attribute \src "libresoc.v:185710.5-185710.29" switch \initial - attribute \src "libresoc.v:183406.9-183406.17" + attribute \src "libresoc.v:185710.9-185710.17" case 1'1 case end @@ -380741,14 +384750,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:183417.3-183435.6" - process $proc$libresoc.v:183417$12093 + attribute \src "libresoc.v:185721.3-185739.6" + process $proc$libresoc.v:185721$12277 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:183418.5-183418.29" + attribute \src "libresoc.v:185722.5-185722.29" switch \initial - attribute \src "libresoc.v:183418.9-183418.17" + attribute \src "libresoc.v:185722.9-185722.17" case 1'1 case end @@ -380776,14 +384785,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:183436.3-183445.6" - process $proc$libresoc.v:183436$12094 + attribute \src "libresoc.v:185740.3-185749.6" + process $proc$libresoc.v:185740$12278 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:183437.5-183437.29" + attribute \src "libresoc.v:185741.5-185741.29" switch \initial - attribute \src "libresoc.v:183437.9-183437.17" + attribute \src "libresoc.v:185741.9-185741.17" case 1'1 case end @@ -380799,13 +384808,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:183446.3-183457.6" - process $proc$libresoc.v:183446$12095 + attribute \src "libresoc.v:185750.3-185761.6" + process $proc$libresoc.v:185750$12279 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:183447.5-183447.29" + attribute \src "libresoc.v:185751.5-185751.29" switch \initial - attribute \src "libresoc.v:183447.9-183447.17" + attribute \src "libresoc.v:185751.9-185751.17" case 1'1 case end @@ -380823,13 +384832,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:183458.3-183491.6" - process $proc$libresoc.v:183458$12096 + attribute \src "libresoc.v:185762.3-185795.6" + process $proc$libresoc.v:185762$12280 assign { } { } - assign $0\mb$8[6:0]$12097 $1\mb$8[6:0]$12098 - attribute \src "libresoc.v:183459.5-183459.29" + assign $0\mb$8[6:0]$12281 $1\mb$8[6:0]$12282 + attribute \src "libresoc.v:185763.5-185763.29" switch \initial - attribute \src "libresoc.v:183459.9-183459.17" + attribute \src "libresoc.v:185763.9-185763.17" case 1'1 case end @@ -380838,48 +384847,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12098 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12098 [6:5] $2\mb$8[6:5]$12099 + assign $1\mb$8[6:0]$12282 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12282 [6:5] $2\mb$8[6:5]$12283 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12099 2'01 + assign $2\mb$8[6:5]$12283 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12099 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12283 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12098 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12098 [6:5] $3\mb$8[6:5]$12100 + assign $1\mb$8[6:0]$12282 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12282 [6:5] $3\mb$8[6:5]$12284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12100 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12284 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12100 \sh [6:5] + assign $3\mb$8[6:5]$12284 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12098 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12282 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12097 + update \mb$8 $0\mb$8[6:0]$12281 end - attribute \src "libresoc.v:183492.3-183506.6" - process $proc$libresoc.v:183492$12101 + attribute \src "libresoc.v:185796.3-185810.6" + process $proc$libresoc.v:185796$12285 assign { } { } - assign $0\me$13[6:0]$12102 $1\me$13[6:0]$12103 - attribute \src "libresoc.v:183493.5-183493.29" + assign $0\me$13[6:0]$12286 $1\me$13[6:0]$12287 + attribute \src "libresoc.v:185797.5-185797.29" switch \initial - attribute \src "libresoc.v:183493.9-183493.17" + attribute \src "libresoc.v:185797.9-185797.17" case 1'1 case end @@ -380888,57 +384897,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12103 { 2'01 \me } + assign $1\me$13[6:0]$12287 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12103 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12103 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12102 - end - connect \$9 $pos$libresoc.v:183317$12051_Y - connect \$11 $not$libresoc.v:183318$12052_Y - connect \$14 $and$libresoc.v:183319$12053_Y - connect \$16 $not$libresoc.v:183320$12054_Y - connect \$18 $and$libresoc.v:183321$12055_Y - connect \$20 $not$libresoc.v:183322$12056_Y - connect \$22 $le$libresoc.v:183323$12057_Y - connect \$25 $sub$libresoc.v:183324$12058_Y - connect \$27 $le$libresoc.v:183325$12059_Y - connect \$2 $neg$libresoc.v:183326$12060_Y - connect \$30 $sub$libresoc.v:183327$12061_Y - connect \$32 $not$libresoc.v:183328$12062_Y - connect \$34 $not$libresoc.v:183329$12063_Y - connect \$36 $and$libresoc.v:183330$12064_Y - connect \$38 $or$libresoc.v:183331$12065_Y - connect \$40 $and$libresoc.v:183332$12066_Y - connect \$42 $gt$libresoc.v:183333$12067_Y - connect \$44 $and$libresoc.v:183334$12068_Y - connect \$46 $and$libresoc.v:183335$12069_Y - connect \$48 $and$libresoc.v:183336$12070_Y - connect \$4 $not$libresoc.v:183337$12071_Y - connect \$51 $and$libresoc.v:183338$12072_Y - connect \$50 $not$libresoc.v:183339$12073_Y - connect \$54 $and$libresoc.v:183340$12074_Y - connect \$56 $or$libresoc.v:183341$12075_Y - connect \$58 $or$libresoc.v:183342$12076_Y - connect \$60 $and$libresoc.v:183343$12077_Y - connect \$63 $or$libresoc.v:183344$12078_Y - connect \$62 $not$libresoc.v:183345$12079_Y - connect \$66 $and$libresoc.v:183346$12080_Y - connect \$68 $or$libresoc.v:183347$12081_Y - connect \$6 $and$libresoc.v:183348$12082_Y - connect \$70 $and$libresoc.v:183349$12083_Y - connect \$72 $not$libresoc.v:183350$12084_Y - connect \$74 $or$libresoc.v:183351$12085_Y - connect \$77 $not$libresoc.v:183352$12086_Y - connect \$79 $and$libresoc.v:183353$12087_Y - connect \$76 $reduce_or$libresoc.v:183354$12088_Y + assign $1\me$13[6:0]$12287 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12287 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12286 + end + connect \$9 $pos$libresoc.v:185621$12235_Y + connect \$11 $not$libresoc.v:185622$12236_Y + connect \$14 $and$libresoc.v:185623$12237_Y + connect \$16 $not$libresoc.v:185624$12238_Y + connect \$18 $and$libresoc.v:185625$12239_Y + connect \$20 $not$libresoc.v:185626$12240_Y + connect \$22 $le$libresoc.v:185627$12241_Y + connect \$25 $sub$libresoc.v:185628$12242_Y + connect \$27 $le$libresoc.v:185629$12243_Y + connect \$2 $neg$libresoc.v:185630$12244_Y + connect \$30 $sub$libresoc.v:185631$12245_Y + connect \$32 $not$libresoc.v:185632$12246_Y + connect \$34 $not$libresoc.v:185633$12247_Y + connect \$36 $and$libresoc.v:185634$12248_Y + connect \$38 $or$libresoc.v:185635$12249_Y + connect \$40 $and$libresoc.v:185636$12250_Y + connect \$42 $gt$libresoc.v:185637$12251_Y + connect \$44 $and$libresoc.v:185638$12252_Y + connect \$46 $and$libresoc.v:185639$12253_Y + connect \$48 $and$libresoc.v:185640$12254_Y + connect \$4 $not$libresoc.v:185641$12255_Y + connect \$51 $and$libresoc.v:185642$12256_Y + connect \$50 $not$libresoc.v:185643$12257_Y + connect \$54 $and$libresoc.v:185644$12258_Y + connect \$56 $or$libresoc.v:185645$12259_Y + connect \$58 $or$libresoc.v:185646$12260_Y + connect \$60 $and$libresoc.v:185647$12261_Y + connect \$63 $or$libresoc.v:185648$12262_Y + connect \$62 $not$libresoc.v:185649$12263_Y + connect \$66 $and$libresoc.v:185650$12264_Y + connect \$68 $or$libresoc.v:185651$12265_Y + connect \$6 $and$libresoc.v:185652$12266_Y + connect \$70 $and$libresoc.v:185653$12267_Y + connect \$72 $not$libresoc.v:185654$12268_Y + connect \$74 $or$libresoc.v:185655$12269_Y + connect \$77 $not$libresoc.v:185656$12270_Y + connect \$79 $and$libresoc.v:185657$12271_Y + connect \$76 $reduce_or$libresoc.v:185658$12272_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -380951,15 +384960,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:183522.1-183536.10" +attribute \src "libresoc.v:185826.1-185840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:183534.17-183534.32" - wire width 128 $shr$libresoc.v:183534$12106_Y - attribute \src "libresoc.v:183533.17-183533.100" - wire width 8 $sub$libresoc.v:183533$12105_Y + attribute \src "libresoc.v:185838.17-185838.32" + wire width 128 $shr$libresoc.v:185838$12290_Y + attribute \src "libresoc.v:185837.17-185837.100" + wire width 8 $sub$libresoc.v:185837$12289_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -380970,8 +384979,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:183534.17-183534.32" - cell $shr $shr$libresoc.v:183534$12106 + attribute \src "libresoc.v:185838.17-185838.32" + cell $shr $shr$libresoc.v:185838$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -380979,10 +384988,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:183534$12106_Y + connect \Y $shr$libresoc.v:185838$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:183533$12105 + cell $sub $sub$libresoc.v:185837$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380990,43 +384999,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:183533$12105_Y + connect \Y $sub$libresoc.v:185837$12289_Y end - connect \$2 $sub$libresoc.v:183533$12105_Y - connect \$1 $shr$libresoc.v:183534$12106_Y [63:0] + connect \$2 $sub$libresoc.v:185837$12289_Y + connect \$1 $shr$libresoc.v:185838$12290_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:183540.1-183598.10" +attribute \src "libresoc.v:185844.1-185902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:183541.7-183541.20" + attribute \src "libresoc.v:185845.7-185845.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183586.3-183594.6" - wire $0\q_int$next[0:0]$12117 - attribute \src "libresoc.v:183584.3-183585.27" + attribute \src "libresoc.v:185890.3-185898.6" + wire $0\q_int$next[0:0]$12301 + attribute \src "libresoc.v:185888.3-185889.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183586.3-183594.6" - wire $1\q_int$next[0:0]$12118 - attribute \src "libresoc.v:183563.7-183563.19" + attribute \src "libresoc.v:185890.3-185898.6" + wire $1\q_int$next[0:0]$12302 + attribute \src "libresoc.v:185867.7-185867.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183576.17-183576.96" - wire $and$libresoc.v:183576$12107_Y - attribute \src "libresoc.v:183581.17-183581.96" - wire $and$libresoc.v:183581$12112_Y - attribute \src "libresoc.v:183578.18-183578.93" - wire $not$libresoc.v:183578$12109_Y - attribute \src "libresoc.v:183580.17-183580.92" - wire $not$libresoc.v:183580$12111_Y - attribute \src "libresoc.v:183583.17-183583.92" - wire $not$libresoc.v:183583$12114_Y - attribute \src "libresoc.v:183577.18-183577.98" - wire $or$libresoc.v:183577$12108_Y - attribute \src "libresoc.v:183579.18-183579.99" - wire $or$libresoc.v:183579$12110_Y - attribute \src "libresoc.v:183582.17-183582.97" - wire $or$libresoc.v:183582$12113_Y + attribute \src "libresoc.v:185880.17-185880.96" + wire $and$libresoc.v:185880$12291_Y + attribute \src "libresoc.v:185885.17-185885.96" + wire $and$libresoc.v:185885$12296_Y + attribute \src "libresoc.v:185882.18-185882.93" + wire $not$libresoc.v:185882$12293_Y + attribute \src "libresoc.v:185884.17-185884.92" + wire $not$libresoc.v:185884$12295_Y + attribute \src "libresoc.v:185887.17-185887.92" + wire $not$libresoc.v:185887$12298_Y + attribute \src "libresoc.v:185881.18-185881.98" + wire $or$libresoc.v:185881$12292_Y + attribute \src "libresoc.v:185883.18-185883.99" + wire $or$libresoc.v:185883$12294_Y + attribute \src "libresoc.v:185886.17-185886.97" + wire $or$libresoc.v:185886$12297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381043,11 +385052,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183541.7-183541.15" + attribute \src "libresoc.v:185845.7-185845.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381064,7 +385073,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183576$12107 + cell $and $and$libresoc.v:185880$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381072,10 +385081,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183576$12107_Y + connect \Y $and$libresoc.v:185880$12291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183581$12112 + cell $and $and$libresoc.v:185885$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381083,34 +385092,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183581$12112_Y + connect \Y $and$libresoc.v:185885$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183578$12109 + cell $not $not$libresoc.v:185882$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183578$12109_Y + connect \Y $not$libresoc.v:185882$12293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183580$12111 + cell $not $not$libresoc.v:185884$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183580$12111_Y + connect \Y $not$libresoc.v:185884$12295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183583$12114 + cell $not $not$libresoc.v:185887$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183583$12114_Y + connect \Y $not$libresoc.v:185887$12298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183577$12108 + cell $or $or$libresoc.v:185881$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381118,10 +385127,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183577$12108_Y + connect \Y $or$libresoc.v:185881$12292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183579$12110 + cell $or $or$libresoc.v:185883$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381129,10 +385138,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183579$12110_Y + connect \Y $or$libresoc.v:185883$12294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183582$12113 + cell $or $or$libresoc.v:185886$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381140,39 +385149,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183582$12113_Y + connect \Y $or$libresoc.v:185886$12297_Y end - attribute \src "libresoc.v:183541.7-183541.20" - process $proc$libresoc.v:183541$12119 + attribute \src "libresoc.v:185845.7-185845.20" + process $proc$libresoc.v:185845$12303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183563.7-183563.19" - process $proc$libresoc.v:183563$12120 + attribute \src "libresoc.v:185867.7-185867.19" + process $proc$libresoc.v:185867$12304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183584.3-183585.27" - process $proc$libresoc.v:183584$12115 + attribute \src "libresoc.v:185888.3-185889.27" + process $proc$libresoc.v:185888$12299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183586.3-183594.6" - process $proc$libresoc.v:183586$12116 + attribute \src "libresoc.v:185890.3-185898.6" + process $proc$libresoc.v:185890$12300 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12117 $1\q_int$next[0:0]$12118 - attribute \src "libresoc.v:183587.5-183587.29" + assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 + attribute \src "libresoc.v:185891.5-185891.29" switch \initial - attribute \src "libresoc.v:183587.9-183587.17" + attribute \src "libresoc.v:185891.9-185891.17" case 1'1 case end @@ -381181,56 +385190,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12118 1'0 + assign $1\q_int$next[0:0]$12302 1'0 case - assign $1\q_int$next[0:0]$12118 \$5 + assign $1\q_int$next[0:0]$12302 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12117 + update \q_int$next $0\q_int$next[0:0]$12301 end - connect \$9 $and$libresoc.v:183576$12107_Y - connect \$11 $or$libresoc.v:183577$12108_Y - connect \$13 $not$libresoc.v:183578$12109_Y - connect \$15 $or$libresoc.v:183579$12110_Y - connect \$1 $not$libresoc.v:183580$12111_Y - connect \$3 $and$libresoc.v:183581$12112_Y - connect \$5 $or$libresoc.v:183582$12113_Y - connect \$7 $not$libresoc.v:183583$12114_Y + connect \$9 $and$libresoc.v:185880$12291_Y + connect \$11 $or$libresoc.v:185881$12292_Y + connect \$13 $not$libresoc.v:185882$12293_Y + connect \$15 $or$libresoc.v:185883$12294_Y + connect \$1 $not$libresoc.v:185884$12295_Y + connect \$3 $and$libresoc.v:185885$12296_Y + connect \$5 $or$libresoc.v:185886$12297_Y + connect \$7 $not$libresoc.v:185887$12298_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183602.1-183660.10" +attribute \src "libresoc.v:185906.1-185964.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:183603.7-183603.20" + attribute \src "libresoc.v:185907.7-185907.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183648.3-183656.6" - wire $0\q_int$next[0:0]$12131 - attribute \src "libresoc.v:183646.3-183647.27" + attribute \src "libresoc.v:185952.3-185960.6" + wire $0\q_int$next[0:0]$12315 + attribute \src "libresoc.v:185950.3-185951.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183648.3-183656.6" - wire $1\q_int$next[0:0]$12132 - attribute \src "libresoc.v:183625.7-183625.19" + attribute \src "libresoc.v:185952.3-185960.6" + wire $1\q_int$next[0:0]$12316 + attribute \src "libresoc.v:185929.7-185929.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183638.17-183638.96" - wire $and$libresoc.v:183638$12121_Y - attribute \src "libresoc.v:183643.17-183643.96" - wire $and$libresoc.v:183643$12126_Y - attribute \src "libresoc.v:183640.18-183640.93" - wire $not$libresoc.v:183640$12123_Y - attribute \src "libresoc.v:183642.17-183642.92" - wire $not$libresoc.v:183642$12125_Y - attribute \src "libresoc.v:183645.17-183645.92" - wire $not$libresoc.v:183645$12128_Y - attribute \src "libresoc.v:183639.18-183639.98" - wire $or$libresoc.v:183639$12122_Y - attribute \src "libresoc.v:183641.18-183641.99" - wire $or$libresoc.v:183641$12124_Y - attribute \src "libresoc.v:183644.17-183644.97" - wire $or$libresoc.v:183644$12127_Y + attribute \src "libresoc.v:185942.17-185942.96" + wire $and$libresoc.v:185942$12305_Y + attribute \src "libresoc.v:185947.17-185947.96" + wire $and$libresoc.v:185947$12310_Y + attribute \src "libresoc.v:185944.18-185944.93" + wire $not$libresoc.v:185944$12307_Y + attribute \src "libresoc.v:185946.17-185946.92" + wire $not$libresoc.v:185946$12309_Y + attribute \src "libresoc.v:185949.17-185949.92" + wire $not$libresoc.v:185949$12312_Y + attribute \src "libresoc.v:185943.18-185943.98" + wire $or$libresoc.v:185943$12306_Y + attribute \src "libresoc.v:185945.18-185945.99" + wire $or$libresoc.v:185945$12308_Y + attribute \src "libresoc.v:185948.17-185948.97" + wire $or$libresoc.v:185948$12311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381247,11 +385256,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183603.7-183603.15" + attribute \src "libresoc.v:185907.7-185907.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381268,7 +385277,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183638$12121 + cell $and $and$libresoc.v:185942$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381276,10 +385285,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183638$12121_Y + connect \Y $and$libresoc.v:185942$12305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183643$12126 + cell $and $and$libresoc.v:185947$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381287,34 +385296,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183643$12126_Y + connect \Y $and$libresoc.v:185947$12310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183640$12123 + cell $not $not$libresoc.v:185944$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183640$12123_Y + connect \Y $not$libresoc.v:185944$12307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183642$12125 + cell $not $not$libresoc.v:185946$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183642$12125_Y + connect \Y $not$libresoc.v:185946$12309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183645$12128 + cell $not $not$libresoc.v:185949$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183645$12128_Y + connect \Y $not$libresoc.v:185949$12312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183639$12122 + cell $or $or$libresoc.v:185943$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381322,10 +385331,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183639$12122_Y + connect \Y $or$libresoc.v:185943$12306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183641$12124 + cell $or $or$libresoc.v:185945$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381333,10 +385342,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183641$12124_Y + connect \Y $or$libresoc.v:185945$12308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183644$12127 + cell $or $or$libresoc.v:185948$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381344,39 +385353,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183644$12127_Y + connect \Y $or$libresoc.v:185948$12311_Y end - attribute \src "libresoc.v:183603.7-183603.20" - process $proc$libresoc.v:183603$12133 + attribute \src "libresoc.v:185907.7-185907.20" + process $proc$libresoc.v:185907$12317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183625.7-183625.19" - process $proc$libresoc.v:183625$12134 + attribute \src "libresoc.v:185929.7-185929.19" + process $proc$libresoc.v:185929$12318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183646.3-183647.27" - process $proc$libresoc.v:183646$12129 + attribute \src "libresoc.v:185950.3-185951.27" + process $proc$libresoc.v:185950$12313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183648.3-183656.6" - process $proc$libresoc.v:183648$12130 + attribute \src "libresoc.v:185952.3-185960.6" + process $proc$libresoc.v:185952$12314 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12131 $1\q_int$next[0:0]$12132 - attribute \src "libresoc.v:183649.5-183649.29" + assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 + attribute \src "libresoc.v:185953.5-185953.29" switch \initial - attribute \src "libresoc.v:183649.9-183649.17" + attribute \src "libresoc.v:185953.9-185953.17" case 1'1 case end @@ -381385,56 +385394,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12132 1'0 + assign $1\q_int$next[0:0]$12316 1'0 case - assign $1\q_int$next[0:0]$12132 \$5 + assign $1\q_int$next[0:0]$12316 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12131 + update \q_int$next $0\q_int$next[0:0]$12315 end - connect \$9 $and$libresoc.v:183638$12121_Y - connect \$11 $or$libresoc.v:183639$12122_Y - connect \$13 $not$libresoc.v:183640$12123_Y - connect \$15 $or$libresoc.v:183641$12124_Y - connect \$1 $not$libresoc.v:183642$12125_Y - connect \$3 $and$libresoc.v:183643$12126_Y - connect \$5 $or$libresoc.v:183644$12127_Y - connect \$7 $not$libresoc.v:183645$12128_Y + connect \$9 $and$libresoc.v:185942$12305_Y + connect \$11 $or$libresoc.v:185943$12306_Y + connect \$13 $not$libresoc.v:185944$12307_Y + connect \$15 $or$libresoc.v:185945$12308_Y + connect \$1 $not$libresoc.v:185946$12309_Y + connect \$3 $and$libresoc.v:185947$12310_Y + connect \$5 $or$libresoc.v:185948$12311_Y + connect \$7 $not$libresoc.v:185949$12312_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183664.1-183722.10" +attribute \src "libresoc.v:185968.1-186026.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:183665.7-183665.20" + attribute \src "libresoc.v:185969.7-185969.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183710.3-183718.6" - wire $0\q_int$next[0:0]$12145 - attribute \src "libresoc.v:183708.3-183709.27" + attribute \src "libresoc.v:186014.3-186022.6" + wire $0\q_int$next[0:0]$12329 + attribute \src "libresoc.v:186012.3-186013.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183710.3-183718.6" - wire $1\q_int$next[0:0]$12146 - attribute \src "libresoc.v:183687.7-183687.19" + attribute \src "libresoc.v:186014.3-186022.6" + wire $1\q_int$next[0:0]$12330 + attribute \src "libresoc.v:185991.7-185991.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183700.17-183700.96" - wire $and$libresoc.v:183700$12135_Y - attribute \src "libresoc.v:183705.17-183705.96" - wire $and$libresoc.v:183705$12140_Y - attribute \src "libresoc.v:183702.18-183702.93" - wire $not$libresoc.v:183702$12137_Y - attribute \src "libresoc.v:183704.17-183704.92" - wire $not$libresoc.v:183704$12139_Y - attribute \src "libresoc.v:183707.17-183707.92" - wire $not$libresoc.v:183707$12142_Y - attribute \src "libresoc.v:183701.18-183701.98" - wire $or$libresoc.v:183701$12136_Y - attribute \src "libresoc.v:183703.18-183703.99" - wire $or$libresoc.v:183703$12138_Y - attribute \src "libresoc.v:183706.17-183706.97" - wire $or$libresoc.v:183706$12141_Y + attribute \src "libresoc.v:186004.17-186004.96" + wire $and$libresoc.v:186004$12319_Y + attribute \src "libresoc.v:186009.17-186009.96" + wire $and$libresoc.v:186009$12324_Y + attribute \src "libresoc.v:186006.18-186006.93" + wire $not$libresoc.v:186006$12321_Y + attribute \src "libresoc.v:186008.17-186008.92" + wire $not$libresoc.v:186008$12323_Y + attribute \src "libresoc.v:186011.17-186011.92" + wire $not$libresoc.v:186011$12326_Y + attribute \src "libresoc.v:186005.18-186005.98" + wire $or$libresoc.v:186005$12320_Y + attribute \src "libresoc.v:186007.18-186007.99" + wire $or$libresoc.v:186007$12322_Y + attribute \src "libresoc.v:186010.17-186010.97" + wire $or$libresoc.v:186010$12325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381451,11 +385460,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183665.7-183665.15" + attribute \src "libresoc.v:185969.7-185969.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381472,7 +385481,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183700$12135 + cell $and $and$libresoc.v:186004$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381480,10 +385489,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183700$12135_Y + connect \Y $and$libresoc.v:186004$12319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183705$12140 + cell $and $and$libresoc.v:186009$12324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381491,34 +385500,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183705$12140_Y + connect \Y $and$libresoc.v:186009$12324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183702$12137 + cell $not $not$libresoc.v:186006$12321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183702$12137_Y + connect \Y $not$libresoc.v:186006$12321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183704$12139 + cell $not $not$libresoc.v:186008$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183704$12139_Y + connect \Y $not$libresoc.v:186008$12323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183707$12142 + cell $not $not$libresoc.v:186011$12326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183707$12142_Y + connect \Y $not$libresoc.v:186011$12326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183701$12136 + cell $or $or$libresoc.v:186005$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381526,10 +385535,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183701$12136_Y + connect \Y $or$libresoc.v:186005$12320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183703$12138 + cell $or $or$libresoc.v:186007$12322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381537,10 +385546,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183703$12138_Y + connect \Y $or$libresoc.v:186007$12322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183706$12141 + cell $or $or$libresoc.v:186010$12325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381548,39 +385557,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183706$12141_Y + connect \Y $or$libresoc.v:186010$12325_Y end - attribute \src "libresoc.v:183665.7-183665.20" - process $proc$libresoc.v:183665$12147 + attribute \src "libresoc.v:185969.7-185969.20" + process $proc$libresoc.v:185969$12331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183687.7-183687.19" - process $proc$libresoc.v:183687$12148 + attribute \src "libresoc.v:185991.7-185991.19" + process $proc$libresoc.v:185991$12332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183708.3-183709.27" - process $proc$libresoc.v:183708$12143 + attribute \src "libresoc.v:186012.3-186013.27" + process $proc$libresoc.v:186012$12327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183710.3-183718.6" - process $proc$libresoc.v:183710$12144 + attribute \src "libresoc.v:186014.3-186022.6" + process $proc$libresoc.v:186014$12328 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12145 $1\q_int$next[0:0]$12146 - attribute \src "libresoc.v:183711.5-183711.29" + assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 + attribute \src "libresoc.v:186015.5-186015.29" switch \initial - attribute \src "libresoc.v:183711.9-183711.17" + attribute \src "libresoc.v:186015.9-186015.17" case 1'1 case end @@ -381589,56 +385598,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12146 1'0 + assign $1\q_int$next[0:0]$12330 1'0 case - assign $1\q_int$next[0:0]$12146 \$5 + assign $1\q_int$next[0:0]$12330 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12145 + update \q_int$next $0\q_int$next[0:0]$12329 end - connect \$9 $and$libresoc.v:183700$12135_Y - connect \$11 $or$libresoc.v:183701$12136_Y - connect \$13 $not$libresoc.v:183702$12137_Y - connect \$15 $or$libresoc.v:183703$12138_Y - connect \$1 $not$libresoc.v:183704$12139_Y - connect \$3 $and$libresoc.v:183705$12140_Y - connect \$5 $or$libresoc.v:183706$12141_Y - connect \$7 $not$libresoc.v:183707$12142_Y + connect \$9 $and$libresoc.v:186004$12319_Y + connect \$11 $or$libresoc.v:186005$12320_Y + connect \$13 $not$libresoc.v:186006$12321_Y + connect \$15 $or$libresoc.v:186007$12322_Y + connect \$1 $not$libresoc.v:186008$12323_Y + connect \$3 $and$libresoc.v:186009$12324_Y + connect \$5 $or$libresoc.v:186010$12325_Y + connect \$7 $not$libresoc.v:186011$12326_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183726.1-183784.10" +attribute \src "libresoc.v:186030.1-186088.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:183727.7-183727.20" + attribute \src "libresoc.v:186031.7-186031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183772.3-183780.6" - wire $0\q_int$next[0:0]$12159 - attribute \src "libresoc.v:183770.3-183771.27" + attribute \src "libresoc.v:186076.3-186084.6" + wire $0\q_int$next[0:0]$12343 + attribute \src "libresoc.v:186074.3-186075.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183772.3-183780.6" - wire $1\q_int$next[0:0]$12160 - attribute \src "libresoc.v:183749.7-183749.19" + attribute \src "libresoc.v:186076.3-186084.6" + wire $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186053.7-186053.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183762.17-183762.96" - wire $and$libresoc.v:183762$12149_Y - attribute \src "libresoc.v:183767.17-183767.96" - wire $and$libresoc.v:183767$12154_Y - attribute \src "libresoc.v:183764.18-183764.93" - wire $not$libresoc.v:183764$12151_Y - attribute \src "libresoc.v:183766.17-183766.92" - wire $not$libresoc.v:183766$12153_Y - attribute \src "libresoc.v:183769.17-183769.92" - wire $not$libresoc.v:183769$12156_Y - attribute \src "libresoc.v:183763.18-183763.98" - wire $or$libresoc.v:183763$12150_Y - attribute \src "libresoc.v:183765.18-183765.99" - wire $or$libresoc.v:183765$12152_Y - attribute \src "libresoc.v:183768.17-183768.97" - wire $or$libresoc.v:183768$12155_Y + attribute \src "libresoc.v:186066.17-186066.96" + wire $and$libresoc.v:186066$12333_Y + attribute \src "libresoc.v:186071.17-186071.96" + wire $and$libresoc.v:186071$12338_Y + attribute \src "libresoc.v:186068.18-186068.93" + wire $not$libresoc.v:186068$12335_Y + attribute \src "libresoc.v:186070.17-186070.92" + wire $not$libresoc.v:186070$12337_Y + attribute \src "libresoc.v:186073.17-186073.92" + wire $not$libresoc.v:186073$12340_Y + attribute \src "libresoc.v:186067.18-186067.98" + wire $or$libresoc.v:186067$12334_Y + attribute \src "libresoc.v:186069.18-186069.99" + wire $or$libresoc.v:186069$12336_Y + attribute \src "libresoc.v:186072.17-186072.97" + wire $or$libresoc.v:186072$12339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381655,11 +385664,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183727.7-183727.15" + attribute \src "libresoc.v:186031.7-186031.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381676,7 +385685,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183762$12149 + cell $and $and$libresoc.v:186066$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381684,10 +385693,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183762$12149_Y + connect \Y $and$libresoc.v:186066$12333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183767$12154 + cell $and $and$libresoc.v:186071$12338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381695,34 +385704,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183767$12154_Y + connect \Y $and$libresoc.v:186071$12338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183764$12151 + cell $not $not$libresoc.v:186068$12335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183764$12151_Y + connect \Y $not$libresoc.v:186068$12335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183766$12153 + cell $not $not$libresoc.v:186070$12337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183766$12153_Y + connect \Y $not$libresoc.v:186070$12337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183769$12156 + cell $not $not$libresoc.v:186073$12340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183769$12156_Y + connect \Y $not$libresoc.v:186073$12340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183763$12150 + cell $or $or$libresoc.v:186067$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381730,10 +385739,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183763$12150_Y + connect \Y $or$libresoc.v:186067$12334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183765$12152 + cell $or $or$libresoc.v:186069$12336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381741,10 +385750,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183765$12152_Y + connect \Y $or$libresoc.v:186069$12336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183768$12155 + cell $or $or$libresoc.v:186072$12339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381752,39 +385761,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183768$12155_Y + connect \Y $or$libresoc.v:186072$12339_Y end - attribute \src "libresoc.v:183727.7-183727.20" - process $proc$libresoc.v:183727$12161 + attribute \src "libresoc.v:186031.7-186031.20" + process $proc$libresoc.v:186031$12345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183749.7-183749.19" - process $proc$libresoc.v:183749$12162 + attribute \src "libresoc.v:186053.7-186053.19" + process $proc$libresoc.v:186053$12346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183770.3-183771.27" - process $proc$libresoc.v:183770$12157 + attribute \src "libresoc.v:186074.3-186075.27" + process $proc$libresoc.v:186074$12341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183772.3-183780.6" - process $proc$libresoc.v:183772$12158 + attribute \src "libresoc.v:186076.3-186084.6" + process $proc$libresoc.v:186076$12342 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12159 $1\q_int$next[0:0]$12160 - attribute \src "libresoc.v:183773.5-183773.29" + assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 + attribute \src "libresoc.v:186077.5-186077.29" switch \initial - attribute \src "libresoc.v:183773.9-183773.17" + attribute \src "libresoc.v:186077.9-186077.17" case 1'1 case end @@ -381793,56 +385802,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12160 1'0 + assign $1\q_int$next[0:0]$12344 1'0 case - assign $1\q_int$next[0:0]$12160 \$5 + assign $1\q_int$next[0:0]$12344 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12159 + update \q_int$next $0\q_int$next[0:0]$12343 end - connect \$9 $and$libresoc.v:183762$12149_Y - connect \$11 $or$libresoc.v:183763$12150_Y - connect \$13 $not$libresoc.v:183764$12151_Y - connect \$15 $or$libresoc.v:183765$12152_Y - connect \$1 $not$libresoc.v:183766$12153_Y - connect \$3 $and$libresoc.v:183767$12154_Y - connect \$5 $or$libresoc.v:183768$12155_Y - connect \$7 $not$libresoc.v:183769$12156_Y + connect \$9 $and$libresoc.v:186066$12333_Y + connect \$11 $or$libresoc.v:186067$12334_Y + connect \$13 $not$libresoc.v:186068$12335_Y + connect \$15 $or$libresoc.v:186069$12336_Y + connect \$1 $not$libresoc.v:186070$12337_Y + connect \$3 $and$libresoc.v:186071$12338_Y + connect \$5 $or$libresoc.v:186072$12339_Y + connect \$7 $not$libresoc.v:186073$12340_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183788.1-183846.10" +attribute \src "libresoc.v:186092.1-186150.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:183789.7-183789.20" + attribute \src "libresoc.v:186093.7-186093.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183834.3-183842.6" - wire $0\q_int$next[0:0]$12173 - attribute \src "libresoc.v:183832.3-183833.27" + attribute \src "libresoc.v:186138.3-186146.6" + wire $0\q_int$next[0:0]$12357 + attribute \src "libresoc.v:186136.3-186137.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183834.3-183842.6" - wire $1\q_int$next[0:0]$12174 - attribute \src "libresoc.v:183811.7-183811.19" + attribute \src "libresoc.v:186138.3-186146.6" + wire $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186115.7-186115.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183824.17-183824.96" - wire $and$libresoc.v:183824$12163_Y - attribute \src "libresoc.v:183829.17-183829.96" - wire $and$libresoc.v:183829$12168_Y - attribute \src "libresoc.v:183826.18-183826.93" - wire $not$libresoc.v:183826$12165_Y - attribute \src "libresoc.v:183828.17-183828.92" - wire $not$libresoc.v:183828$12167_Y - attribute \src "libresoc.v:183831.17-183831.92" - wire $not$libresoc.v:183831$12170_Y - attribute \src "libresoc.v:183825.18-183825.98" - wire $or$libresoc.v:183825$12164_Y - attribute \src "libresoc.v:183827.18-183827.99" - wire $or$libresoc.v:183827$12166_Y - attribute \src "libresoc.v:183830.17-183830.97" - wire $or$libresoc.v:183830$12169_Y + attribute \src "libresoc.v:186128.17-186128.96" + wire $and$libresoc.v:186128$12347_Y + attribute \src "libresoc.v:186133.17-186133.96" + wire $and$libresoc.v:186133$12352_Y + attribute \src "libresoc.v:186130.18-186130.93" + wire $not$libresoc.v:186130$12349_Y + attribute \src "libresoc.v:186132.17-186132.92" + wire $not$libresoc.v:186132$12351_Y + attribute \src "libresoc.v:186135.17-186135.92" + wire $not$libresoc.v:186135$12354_Y + attribute \src "libresoc.v:186129.18-186129.98" + wire $or$libresoc.v:186129$12348_Y + attribute \src "libresoc.v:186131.18-186131.99" + wire $or$libresoc.v:186131$12350_Y + attribute \src "libresoc.v:186134.17-186134.97" + wire $or$libresoc.v:186134$12353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381859,11 +385868,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183789.7-183789.15" + attribute \src "libresoc.v:186093.7-186093.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381880,7 +385889,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183824$12163 + cell $and $and$libresoc.v:186128$12347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381888,10 +385897,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183824$12163_Y + connect \Y $and$libresoc.v:186128$12347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183829$12168 + cell $and $and$libresoc.v:186133$12352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381899,34 +385908,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183829$12168_Y + connect \Y $and$libresoc.v:186133$12352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183826$12165 + cell $not $not$libresoc.v:186130$12349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183826$12165_Y + connect \Y $not$libresoc.v:186130$12349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183828$12167 + cell $not $not$libresoc.v:186132$12351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183828$12167_Y + connect \Y $not$libresoc.v:186132$12351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183831$12170 + cell $not $not$libresoc.v:186135$12354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183831$12170_Y + connect \Y $not$libresoc.v:186135$12354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183825$12164 + cell $or $or$libresoc.v:186129$12348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381934,10 +385943,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183825$12164_Y + connect \Y $or$libresoc.v:186129$12348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183827$12166 + cell $or $or$libresoc.v:186131$12350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381945,10 +385954,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183827$12166_Y + connect \Y $or$libresoc.v:186131$12350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183830$12169 + cell $or $or$libresoc.v:186134$12353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381956,39 +385965,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183830$12169_Y + connect \Y $or$libresoc.v:186134$12353_Y end - attribute \src "libresoc.v:183789.7-183789.20" - process $proc$libresoc.v:183789$12175 + attribute \src "libresoc.v:186093.7-186093.20" + process $proc$libresoc.v:186093$12359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183811.7-183811.19" - process $proc$libresoc.v:183811$12176 + attribute \src "libresoc.v:186115.7-186115.19" + process $proc$libresoc.v:186115$12360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183832.3-183833.27" - process $proc$libresoc.v:183832$12171 + attribute \src "libresoc.v:186136.3-186137.27" + process $proc$libresoc.v:186136$12355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183834.3-183842.6" - process $proc$libresoc.v:183834$12172 + attribute \src "libresoc.v:186138.3-186146.6" + process $proc$libresoc.v:186138$12356 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12173 $1\q_int$next[0:0]$12174 - attribute \src "libresoc.v:183835.5-183835.29" + assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 + attribute \src "libresoc.v:186139.5-186139.29" switch \initial - attribute \src "libresoc.v:183835.9-183835.17" + attribute \src "libresoc.v:186139.9-186139.17" case 1'1 case end @@ -381997,56 +386006,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12174 1'0 + assign $1\q_int$next[0:0]$12358 1'0 case - assign $1\q_int$next[0:0]$12174 \$5 + assign $1\q_int$next[0:0]$12358 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12173 + update \q_int$next $0\q_int$next[0:0]$12357 end - connect \$9 $and$libresoc.v:183824$12163_Y - connect \$11 $or$libresoc.v:183825$12164_Y - connect \$13 $not$libresoc.v:183826$12165_Y - connect \$15 $or$libresoc.v:183827$12166_Y - connect \$1 $not$libresoc.v:183828$12167_Y - connect \$3 $and$libresoc.v:183829$12168_Y - connect \$5 $or$libresoc.v:183830$12169_Y - connect \$7 $not$libresoc.v:183831$12170_Y + connect \$9 $and$libresoc.v:186128$12347_Y + connect \$11 $or$libresoc.v:186129$12348_Y + connect \$13 $not$libresoc.v:186130$12349_Y + connect \$15 $or$libresoc.v:186131$12350_Y + connect \$1 $not$libresoc.v:186132$12351_Y + connect \$3 $and$libresoc.v:186133$12352_Y + connect \$5 $or$libresoc.v:186134$12353_Y + connect \$7 $not$libresoc.v:186135$12354_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183850.1-183908.10" +attribute \src "libresoc.v:186154.1-186212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:183851.7-183851.20" + attribute \src "libresoc.v:186155.7-186155.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183896.3-183904.6" - wire $0\q_int$next[0:0]$12187 - attribute \src "libresoc.v:183894.3-183895.27" + attribute \src "libresoc.v:186200.3-186208.6" + wire $0\q_int$next[0:0]$12371 + attribute \src "libresoc.v:186198.3-186199.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183896.3-183904.6" - wire $1\q_int$next[0:0]$12188 - attribute \src "libresoc.v:183873.7-183873.19" + attribute \src "libresoc.v:186200.3-186208.6" + wire $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186177.7-186177.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183886.17-183886.96" - wire $and$libresoc.v:183886$12177_Y - attribute \src "libresoc.v:183891.17-183891.96" - wire $and$libresoc.v:183891$12182_Y - attribute \src "libresoc.v:183888.18-183888.93" - wire $not$libresoc.v:183888$12179_Y - attribute \src "libresoc.v:183890.17-183890.92" - wire $not$libresoc.v:183890$12181_Y - attribute \src "libresoc.v:183893.17-183893.92" - wire $not$libresoc.v:183893$12184_Y - attribute \src "libresoc.v:183887.18-183887.98" - wire $or$libresoc.v:183887$12178_Y - attribute \src "libresoc.v:183889.18-183889.99" - wire $or$libresoc.v:183889$12180_Y - attribute \src "libresoc.v:183892.17-183892.97" - wire $or$libresoc.v:183892$12183_Y + attribute \src "libresoc.v:186190.17-186190.96" + wire $and$libresoc.v:186190$12361_Y + attribute \src "libresoc.v:186195.17-186195.96" + wire $and$libresoc.v:186195$12366_Y + attribute \src "libresoc.v:186192.18-186192.93" + wire $not$libresoc.v:186192$12363_Y + attribute \src "libresoc.v:186194.17-186194.92" + wire $not$libresoc.v:186194$12365_Y + attribute \src "libresoc.v:186197.17-186197.92" + wire $not$libresoc.v:186197$12368_Y + attribute \src "libresoc.v:186191.18-186191.98" + wire $or$libresoc.v:186191$12362_Y + attribute \src "libresoc.v:186193.18-186193.99" + wire $or$libresoc.v:186193$12364_Y + attribute \src "libresoc.v:186196.17-186196.97" + wire $or$libresoc.v:186196$12367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382063,11 +386072,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183851.7-183851.15" + attribute \src "libresoc.v:186155.7-186155.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382084,7 +386093,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183886$12177 + cell $and $and$libresoc.v:186190$12361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382092,10 +386101,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183886$12177_Y + connect \Y $and$libresoc.v:186190$12361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183891$12182 + cell $and $and$libresoc.v:186195$12366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382103,34 +386112,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183891$12182_Y + connect \Y $and$libresoc.v:186195$12366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183888$12179 + cell $not $not$libresoc.v:186192$12363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183888$12179_Y + connect \Y $not$libresoc.v:186192$12363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183890$12181 + cell $not $not$libresoc.v:186194$12365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183890$12181_Y + connect \Y $not$libresoc.v:186194$12365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183893$12184 + cell $not $not$libresoc.v:186197$12368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183893$12184_Y + connect \Y $not$libresoc.v:186197$12368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183887$12178 + cell $or $or$libresoc.v:186191$12362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382138,10 +386147,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183887$12178_Y + connect \Y $or$libresoc.v:186191$12362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183889$12180 + cell $or $or$libresoc.v:186193$12364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382149,10 +386158,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183889$12180_Y + connect \Y $or$libresoc.v:186193$12364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183892$12183 + cell $or $or$libresoc.v:186196$12367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382160,39 +386169,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183892$12183_Y + connect \Y $or$libresoc.v:186196$12367_Y end - attribute \src "libresoc.v:183851.7-183851.20" - process $proc$libresoc.v:183851$12189 + attribute \src "libresoc.v:186155.7-186155.20" + process $proc$libresoc.v:186155$12373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183873.7-183873.19" - process $proc$libresoc.v:183873$12190 + attribute \src "libresoc.v:186177.7-186177.19" + process $proc$libresoc.v:186177$12374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183894.3-183895.27" - process $proc$libresoc.v:183894$12185 + attribute \src "libresoc.v:186198.3-186199.27" + process $proc$libresoc.v:186198$12369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183896.3-183904.6" - process $proc$libresoc.v:183896$12186 + attribute \src "libresoc.v:186200.3-186208.6" + process $proc$libresoc.v:186200$12370 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12187 $1\q_int$next[0:0]$12188 - attribute \src "libresoc.v:183897.5-183897.29" + assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 + attribute \src "libresoc.v:186201.5-186201.29" switch \initial - attribute \src "libresoc.v:183897.9-183897.17" + attribute \src "libresoc.v:186201.9-186201.17" case 1'1 case end @@ -382201,56 +386210,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12188 1'0 + assign $1\q_int$next[0:0]$12372 1'0 case - assign $1\q_int$next[0:0]$12188 \$5 + assign $1\q_int$next[0:0]$12372 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12187 + update \q_int$next $0\q_int$next[0:0]$12371 end - connect \$9 $and$libresoc.v:183886$12177_Y - connect \$11 $or$libresoc.v:183887$12178_Y - connect \$13 $not$libresoc.v:183888$12179_Y - connect \$15 $or$libresoc.v:183889$12180_Y - connect \$1 $not$libresoc.v:183890$12181_Y - connect \$3 $and$libresoc.v:183891$12182_Y - connect \$5 $or$libresoc.v:183892$12183_Y - connect \$7 $not$libresoc.v:183893$12184_Y + connect \$9 $and$libresoc.v:186190$12361_Y + connect \$11 $or$libresoc.v:186191$12362_Y + connect \$13 $not$libresoc.v:186192$12363_Y + connect \$15 $or$libresoc.v:186193$12364_Y + connect \$1 $not$libresoc.v:186194$12365_Y + connect \$3 $and$libresoc.v:186195$12366_Y + connect \$5 $or$libresoc.v:186196$12367_Y + connect \$7 $not$libresoc.v:186197$12368_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183912.1-183970.10" +attribute \src "libresoc.v:186216.1-186274.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:183913.7-183913.20" + attribute \src "libresoc.v:186217.7-186217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183958.3-183966.6" - wire $0\q_int$next[0:0]$12201 - attribute \src "libresoc.v:183956.3-183957.27" + attribute \src "libresoc.v:186262.3-186270.6" + wire $0\q_int$next[0:0]$12385 + attribute \src "libresoc.v:186260.3-186261.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:183958.3-183966.6" - wire $1\q_int$next[0:0]$12202 - attribute \src "libresoc.v:183935.7-183935.19" + attribute \src "libresoc.v:186262.3-186270.6" + wire $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186239.7-186239.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:183948.17-183948.96" - wire $and$libresoc.v:183948$12191_Y - attribute \src "libresoc.v:183953.17-183953.96" - wire $and$libresoc.v:183953$12196_Y - attribute \src "libresoc.v:183950.18-183950.93" - wire $not$libresoc.v:183950$12193_Y - attribute \src "libresoc.v:183952.17-183952.92" - wire $not$libresoc.v:183952$12195_Y - attribute \src "libresoc.v:183955.17-183955.92" - wire $not$libresoc.v:183955$12198_Y - attribute \src "libresoc.v:183949.18-183949.98" - wire $or$libresoc.v:183949$12192_Y - attribute \src "libresoc.v:183951.18-183951.99" - wire $or$libresoc.v:183951$12194_Y - attribute \src "libresoc.v:183954.17-183954.97" - wire $or$libresoc.v:183954$12197_Y + attribute \src "libresoc.v:186252.17-186252.96" + wire $and$libresoc.v:186252$12375_Y + attribute \src "libresoc.v:186257.17-186257.96" + wire $and$libresoc.v:186257$12380_Y + attribute \src "libresoc.v:186254.18-186254.93" + wire $not$libresoc.v:186254$12377_Y + attribute \src "libresoc.v:186256.17-186256.92" + wire $not$libresoc.v:186256$12379_Y + attribute \src "libresoc.v:186259.17-186259.92" + wire $not$libresoc.v:186259$12382_Y + attribute \src "libresoc.v:186253.18-186253.98" + wire $or$libresoc.v:186253$12376_Y + attribute \src "libresoc.v:186255.18-186255.99" + wire $or$libresoc.v:186255$12378_Y + attribute \src "libresoc.v:186258.17-186258.97" + wire $or$libresoc.v:186258$12381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382267,11 +386276,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183913.7-183913.15" + attribute \src "libresoc.v:186217.7-186217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382288,7 +386297,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183948$12191 + cell $and $and$libresoc.v:186252$12375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382296,10 +386305,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183948$12191_Y + connect \Y $and$libresoc.v:186252$12375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183953$12196 + cell $and $and$libresoc.v:186257$12380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382307,34 +386316,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183953$12196_Y + connect \Y $and$libresoc.v:186257$12380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183950$12193 + cell $not $not$libresoc.v:186254$12377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:183950$12193_Y + connect \Y $not$libresoc.v:186254$12377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183952$12195 + cell $not $not$libresoc.v:186256$12379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183952$12195_Y + connect \Y $not$libresoc.v:186256$12379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183955$12198 + cell $not $not$libresoc.v:186259$12382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:183955$12198_Y + connect \Y $not$libresoc.v:186259$12382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183949$12192 + cell $or $or$libresoc.v:186253$12376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382342,10 +386351,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:183949$12192_Y + connect \Y $or$libresoc.v:186253$12376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183951$12194 + cell $or $or$libresoc.v:186255$12378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382353,10 +386362,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:183951$12194_Y + connect \Y $or$libresoc.v:186255$12378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183954$12197 + cell $or $or$libresoc.v:186258$12381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382364,39 +386373,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:183954$12197_Y + connect \Y $or$libresoc.v:186258$12381_Y end - attribute \src "libresoc.v:183913.7-183913.20" - process $proc$libresoc.v:183913$12203 + attribute \src "libresoc.v:186217.7-186217.20" + process $proc$libresoc.v:186217$12387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183935.7-183935.19" - process $proc$libresoc.v:183935$12204 + attribute \src "libresoc.v:186239.7-186239.19" + process $proc$libresoc.v:186239$12388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:183956.3-183957.27" - process $proc$libresoc.v:183956$12199 + attribute \src "libresoc.v:186260.3-186261.27" + process $proc$libresoc.v:186260$12383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:183958.3-183966.6" - process $proc$libresoc.v:183958$12200 + attribute \src "libresoc.v:186262.3-186270.6" + process $proc$libresoc.v:186262$12384 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12201 $1\q_int$next[0:0]$12202 - attribute \src "libresoc.v:183959.5-183959.29" + assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 + attribute \src "libresoc.v:186263.5-186263.29" switch \initial - attribute \src "libresoc.v:183959.9-183959.17" + attribute \src "libresoc.v:186263.9-186263.17" case 1'1 case end @@ -382405,56 +386414,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12202 1'0 + assign $1\q_int$next[0:0]$12386 1'0 case - assign $1\q_int$next[0:0]$12202 \$5 + assign $1\q_int$next[0:0]$12386 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12201 + update \q_int$next $0\q_int$next[0:0]$12385 end - connect \$9 $and$libresoc.v:183948$12191_Y - connect \$11 $or$libresoc.v:183949$12192_Y - connect \$13 $not$libresoc.v:183950$12193_Y - connect \$15 $or$libresoc.v:183951$12194_Y - connect \$1 $not$libresoc.v:183952$12195_Y - connect \$3 $and$libresoc.v:183953$12196_Y - connect \$5 $or$libresoc.v:183954$12197_Y - connect \$7 $not$libresoc.v:183955$12198_Y + connect \$9 $and$libresoc.v:186252$12375_Y + connect \$11 $or$libresoc.v:186253$12376_Y + connect \$13 $not$libresoc.v:186254$12377_Y + connect \$15 $or$libresoc.v:186255$12378_Y + connect \$1 $not$libresoc.v:186256$12379_Y + connect \$3 $and$libresoc.v:186257$12380_Y + connect \$5 $or$libresoc.v:186258$12381_Y + connect \$7 $not$libresoc.v:186259$12382_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:183974.1-184032.10" +attribute \src "libresoc.v:186278.1-186336.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:183975.7-183975.20" + attribute \src "libresoc.v:186279.7-186279.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184020.3-184028.6" - wire $0\q_int$next[0:0]$12215 - attribute \src "libresoc.v:184018.3-184019.27" + attribute \src "libresoc.v:186324.3-186332.6" + wire $0\q_int$next[0:0]$12399 + attribute \src "libresoc.v:186322.3-186323.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184020.3-184028.6" - wire $1\q_int$next[0:0]$12216 - attribute \src "libresoc.v:183997.7-183997.19" + attribute \src "libresoc.v:186324.3-186332.6" + wire $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186301.7-186301.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184010.17-184010.96" - wire $and$libresoc.v:184010$12205_Y - attribute \src "libresoc.v:184015.17-184015.96" - wire $and$libresoc.v:184015$12210_Y - attribute \src "libresoc.v:184012.18-184012.93" - wire $not$libresoc.v:184012$12207_Y - attribute \src "libresoc.v:184014.17-184014.92" - wire $not$libresoc.v:184014$12209_Y - attribute \src "libresoc.v:184017.17-184017.92" - wire $not$libresoc.v:184017$12212_Y - attribute \src "libresoc.v:184011.18-184011.98" - wire $or$libresoc.v:184011$12206_Y - attribute \src "libresoc.v:184013.18-184013.99" - wire $or$libresoc.v:184013$12208_Y - attribute \src "libresoc.v:184016.17-184016.97" - wire $or$libresoc.v:184016$12211_Y + attribute \src "libresoc.v:186314.17-186314.96" + wire $and$libresoc.v:186314$12389_Y + attribute \src "libresoc.v:186319.17-186319.96" + wire $and$libresoc.v:186319$12394_Y + attribute \src "libresoc.v:186316.18-186316.93" + wire $not$libresoc.v:186316$12391_Y + attribute \src "libresoc.v:186318.17-186318.92" + wire $not$libresoc.v:186318$12393_Y + attribute \src "libresoc.v:186321.17-186321.92" + wire $not$libresoc.v:186321$12396_Y + attribute \src "libresoc.v:186315.18-186315.98" + wire $or$libresoc.v:186315$12390_Y + attribute \src "libresoc.v:186317.18-186317.99" + wire $or$libresoc.v:186317$12392_Y + attribute \src "libresoc.v:186320.17-186320.97" + wire $or$libresoc.v:186320$12395_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382471,11 +386480,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183975.7-183975.15" + attribute \src "libresoc.v:186279.7-186279.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382492,7 +386501,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184010$12205 + cell $and $and$libresoc.v:186314$12389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382500,10 +386509,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184010$12205_Y + connect \Y $and$libresoc.v:186314$12389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184015$12210 + cell $and $and$libresoc.v:186319$12394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382511,34 +386520,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184015$12210_Y + connect \Y $and$libresoc.v:186319$12394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184012$12207 + cell $not $not$libresoc.v:186316$12391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184012$12207_Y + connect \Y $not$libresoc.v:186316$12391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184014$12209 + cell $not $not$libresoc.v:186318$12393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184014$12209_Y + connect \Y $not$libresoc.v:186318$12393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184017$12212 + cell $not $not$libresoc.v:186321$12396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184017$12212_Y + connect \Y $not$libresoc.v:186321$12396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184011$12206 + cell $or $or$libresoc.v:186315$12390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382546,10 +386555,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184011$12206_Y + connect \Y $or$libresoc.v:186315$12390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184013$12208 + cell $or $or$libresoc.v:186317$12392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382557,10 +386566,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184013$12208_Y + connect \Y $or$libresoc.v:186317$12392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184016$12211 + cell $or $or$libresoc.v:186320$12395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382568,39 +386577,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184016$12211_Y + connect \Y $or$libresoc.v:186320$12395_Y end - attribute \src "libresoc.v:183975.7-183975.20" - process $proc$libresoc.v:183975$12217 + attribute \src "libresoc.v:186279.7-186279.20" + process $proc$libresoc.v:186279$12401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183997.7-183997.19" - process $proc$libresoc.v:183997$12218 + attribute \src "libresoc.v:186301.7-186301.19" + process $proc$libresoc.v:186301$12402 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184018.3-184019.27" - process $proc$libresoc.v:184018$12213 + attribute \src "libresoc.v:186322.3-186323.27" + process $proc$libresoc.v:186322$12397 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184020.3-184028.6" - process $proc$libresoc.v:184020$12214 + attribute \src "libresoc.v:186324.3-186332.6" + process $proc$libresoc.v:186324$12398 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12215 $1\q_int$next[0:0]$12216 - attribute \src "libresoc.v:184021.5-184021.29" + assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 + attribute \src "libresoc.v:186325.5-186325.29" switch \initial - attribute \src "libresoc.v:184021.9-184021.17" + attribute \src "libresoc.v:186325.9-186325.17" case 1'1 case end @@ -382609,56 +386618,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12216 1'0 + assign $1\q_int$next[0:0]$12400 1'0 case - assign $1\q_int$next[0:0]$12216 \$5 + assign $1\q_int$next[0:0]$12400 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12215 + update \q_int$next $0\q_int$next[0:0]$12399 end - connect \$9 $and$libresoc.v:184010$12205_Y - connect \$11 $or$libresoc.v:184011$12206_Y - connect \$13 $not$libresoc.v:184012$12207_Y - connect \$15 $or$libresoc.v:184013$12208_Y - connect \$1 $not$libresoc.v:184014$12209_Y - connect \$3 $and$libresoc.v:184015$12210_Y - connect \$5 $or$libresoc.v:184016$12211_Y - connect \$7 $not$libresoc.v:184017$12212_Y + connect \$9 $and$libresoc.v:186314$12389_Y + connect \$11 $or$libresoc.v:186315$12390_Y + connect \$13 $not$libresoc.v:186316$12391_Y + connect \$15 $or$libresoc.v:186317$12392_Y + connect \$1 $not$libresoc.v:186318$12393_Y + connect \$3 $and$libresoc.v:186319$12394_Y + connect \$5 $or$libresoc.v:186320$12395_Y + connect \$7 $not$libresoc.v:186321$12396_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184036.1-184094.10" +attribute \src "libresoc.v:186340.1-186398.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:184037.7-184037.20" + attribute \src "libresoc.v:186341.7-186341.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184082.3-184090.6" - wire $0\q_int$next[0:0]$12229 - attribute \src "libresoc.v:184080.3-184081.27" + attribute \src "libresoc.v:186386.3-186394.6" + wire $0\q_int$next[0:0]$12413 + attribute \src "libresoc.v:186384.3-186385.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184082.3-184090.6" - wire $1\q_int$next[0:0]$12230 - attribute \src "libresoc.v:184059.7-184059.19" + attribute \src "libresoc.v:186386.3-186394.6" + wire $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186363.7-186363.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184072.17-184072.96" - wire $and$libresoc.v:184072$12219_Y - attribute \src "libresoc.v:184077.17-184077.96" - wire $and$libresoc.v:184077$12224_Y - attribute \src "libresoc.v:184074.18-184074.93" - wire $not$libresoc.v:184074$12221_Y - attribute \src "libresoc.v:184076.17-184076.92" - wire $not$libresoc.v:184076$12223_Y - attribute \src "libresoc.v:184079.17-184079.92" - wire $not$libresoc.v:184079$12226_Y - attribute \src "libresoc.v:184073.18-184073.98" - wire $or$libresoc.v:184073$12220_Y - attribute \src "libresoc.v:184075.18-184075.99" - wire $or$libresoc.v:184075$12222_Y - attribute \src "libresoc.v:184078.17-184078.97" - wire $or$libresoc.v:184078$12225_Y + attribute \src "libresoc.v:186376.17-186376.96" + wire $and$libresoc.v:186376$12403_Y + attribute \src "libresoc.v:186381.17-186381.96" + wire $and$libresoc.v:186381$12408_Y + attribute \src "libresoc.v:186378.18-186378.93" + wire $not$libresoc.v:186378$12405_Y + attribute \src "libresoc.v:186380.17-186380.92" + wire $not$libresoc.v:186380$12407_Y + attribute \src "libresoc.v:186383.17-186383.92" + wire $not$libresoc.v:186383$12410_Y + attribute \src "libresoc.v:186377.18-186377.98" + wire $or$libresoc.v:186377$12404_Y + attribute \src "libresoc.v:186379.18-186379.99" + wire $or$libresoc.v:186379$12406_Y + attribute \src "libresoc.v:186382.17-186382.97" + wire $or$libresoc.v:186382$12409_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382675,11 +386684,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184037.7-184037.15" + attribute \src "libresoc.v:186341.7-186341.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382696,7 +386705,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184072$12219 + cell $and $and$libresoc.v:186376$12403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382704,10 +386713,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184072$12219_Y + connect \Y $and$libresoc.v:186376$12403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184077$12224 + cell $and $and$libresoc.v:186381$12408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382715,34 +386724,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184077$12224_Y + connect \Y $and$libresoc.v:186381$12408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184074$12221 + cell $not $not$libresoc.v:186378$12405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184074$12221_Y + connect \Y $not$libresoc.v:186378$12405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184076$12223 + cell $not $not$libresoc.v:186380$12407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184076$12223_Y + connect \Y $not$libresoc.v:186380$12407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184079$12226 + cell $not $not$libresoc.v:186383$12410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184079$12226_Y + connect \Y $not$libresoc.v:186383$12410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184073$12220 + cell $or $or$libresoc.v:186377$12404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382750,10 +386759,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184073$12220_Y + connect \Y $or$libresoc.v:186377$12404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184075$12222 + cell $or $or$libresoc.v:186379$12406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382761,10 +386770,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184075$12222_Y + connect \Y $or$libresoc.v:186379$12406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184078$12225 + cell $or $or$libresoc.v:186382$12409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382772,39 +386781,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184078$12225_Y + connect \Y $or$libresoc.v:186382$12409_Y end - attribute \src "libresoc.v:184037.7-184037.20" - process $proc$libresoc.v:184037$12231 + attribute \src "libresoc.v:186341.7-186341.20" + process $proc$libresoc.v:186341$12415 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184059.7-184059.19" - process $proc$libresoc.v:184059$12232 + attribute \src "libresoc.v:186363.7-186363.19" + process $proc$libresoc.v:186363$12416 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184080.3-184081.27" - process $proc$libresoc.v:184080$12227 + attribute \src "libresoc.v:186384.3-186385.27" + process $proc$libresoc.v:186384$12411 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184082.3-184090.6" - process $proc$libresoc.v:184082$12228 + attribute \src "libresoc.v:186386.3-186394.6" + process $proc$libresoc.v:186386$12412 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12229 $1\q_int$next[0:0]$12230 - attribute \src "libresoc.v:184083.5-184083.29" + assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 + attribute \src "libresoc.v:186387.5-186387.29" switch \initial - attribute \src "libresoc.v:184083.9-184083.17" + attribute \src "libresoc.v:186387.9-186387.17" case 1'1 case end @@ -382813,56 +386822,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12230 1'0 + assign $1\q_int$next[0:0]$12414 1'0 case - assign $1\q_int$next[0:0]$12230 \$5 + assign $1\q_int$next[0:0]$12414 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12229 + update \q_int$next $0\q_int$next[0:0]$12413 end - connect \$9 $and$libresoc.v:184072$12219_Y - connect \$11 $or$libresoc.v:184073$12220_Y - connect \$13 $not$libresoc.v:184074$12221_Y - connect \$15 $or$libresoc.v:184075$12222_Y - connect \$1 $not$libresoc.v:184076$12223_Y - connect \$3 $and$libresoc.v:184077$12224_Y - connect \$5 $or$libresoc.v:184078$12225_Y - connect \$7 $not$libresoc.v:184079$12226_Y + connect \$9 $and$libresoc.v:186376$12403_Y + connect \$11 $or$libresoc.v:186377$12404_Y + connect \$13 $not$libresoc.v:186378$12405_Y + connect \$15 $or$libresoc.v:186379$12406_Y + connect \$1 $not$libresoc.v:186380$12407_Y + connect \$3 $and$libresoc.v:186381$12408_Y + connect \$5 $or$libresoc.v:186382$12409_Y + connect \$7 $not$libresoc.v:186383$12410_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184098.1-184156.10" +attribute \src "libresoc.v:186402.1-186460.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:184099.7-184099.20" + attribute \src "libresoc.v:186403.7-186403.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184144.3-184152.6" - wire $0\q_int$next[0:0]$12243 - attribute \src "libresoc.v:184142.3-184143.27" + attribute \src "libresoc.v:186448.3-186456.6" + wire $0\q_int$next[0:0]$12427 + attribute \src "libresoc.v:186446.3-186447.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184144.3-184152.6" - wire $1\q_int$next[0:0]$12244 - attribute \src "libresoc.v:184121.7-184121.19" + attribute \src "libresoc.v:186448.3-186456.6" + wire $1\q_int$next[0:0]$12428 + attribute \src "libresoc.v:186425.7-186425.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184134.17-184134.96" - wire $and$libresoc.v:184134$12233_Y - attribute \src "libresoc.v:184139.17-184139.96" - wire $and$libresoc.v:184139$12238_Y - attribute \src "libresoc.v:184136.18-184136.93" - wire $not$libresoc.v:184136$12235_Y - attribute \src "libresoc.v:184138.17-184138.92" - wire $not$libresoc.v:184138$12237_Y - attribute \src "libresoc.v:184141.17-184141.92" - wire $not$libresoc.v:184141$12240_Y - attribute \src "libresoc.v:184135.18-184135.98" - wire $or$libresoc.v:184135$12234_Y - attribute \src "libresoc.v:184137.18-184137.99" - wire $or$libresoc.v:184137$12236_Y - attribute \src "libresoc.v:184140.17-184140.97" - wire $or$libresoc.v:184140$12239_Y + attribute \src "libresoc.v:186438.17-186438.96" + wire $and$libresoc.v:186438$12417_Y + attribute \src "libresoc.v:186443.17-186443.96" + wire $and$libresoc.v:186443$12422_Y + attribute \src "libresoc.v:186440.18-186440.93" + wire $not$libresoc.v:186440$12419_Y + attribute \src "libresoc.v:186442.17-186442.92" + wire $not$libresoc.v:186442$12421_Y + attribute \src "libresoc.v:186445.17-186445.92" + wire $not$libresoc.v:186445$12424_Y + attribute \src "libresoc.v:186439.18-186439.98" + wire $or$libresoc.v:186439$12418_Y + attribute \src "libresoc.v:186441.18-186441.99" + wire $or$libresoc.v:186441$12420_Y + attribute \src "libresoc.v:186444.17-186444.97" + wire $or$libresoc.v:186444$12423_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382879,11 +386888,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184099.7-184099.15" + attribute \src "libresoc.v:186403.7-186403.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382900,7 +386909,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184134$12233 + cell $and $and$libresoc.v:186438$12417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382908,10 +386917,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184134$12233_Y + connect \Y $and$libresoc.v:186438$12417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184139$12238 + cell $and $and$libresoc.v:186443$12422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382919,34 +386928,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184139$12238_Y + connect \Y $and$libresoc.v:186443$12422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184136$12235 + cell $not $not$libresoc.v:186440$12419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:184136$12235_Y + connect \Y $not$libresoc.v:186440$12419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184138$12237 + cell $not $not$libresoc.v:186442$12421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184138$12237_Y + connect \Y $not$libresoc.v:186442$12421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184141$12240 + cell $not $not$libresoc.v:186445$12424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:184141$12240_Y + connect \Y $not$libresoc.v:186445$12424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184135$12234 + cell $or $or$libresoc.v:186439$12418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382954,10 +386963,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:184135$12234_Y + connect \Y $or$libresoc.v:186439$12418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184137$12236 + cell $or $or$libresoc.v:186441$12420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382965,10 +386974,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:184137$12236_Y + connect \Y $or$libresoc.v:186441$12420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184140$12239 + cell $or $or$libresoc.v:186444$12423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382976,39 +386985,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:184140$12239_Y + connect \Y $or$libresoc.v:186444$12423_Y end - attribute \src "libresoc.v:184099.7-184099.20" - process $proc$libresoc.v:184099$12245 + attribute \src "libresoc.v:186403.7-186403.20" + process $proc$libresoc.v:186403$12429 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184121.7-184121.19" - process $proc$libresoc.v:184121$12246 + attribute \src "libresoc.v:186425.7-186425.19" + process $proc$libresoc.v:186425$12430 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184142.3-184143.27" - process $proc$libresoc.v:184142$12241 + attribute \src "libresoc.v:186446.3-186447.27" + process $proc$libresoc.v:186446$12425 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184144.3-184152.6" - process $proc$libresoc.v:184144$12242 + attribute \src "libresoc.v:186448.3-186456.6" + process $proc$libresoc.v:186448$12426 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12243 $1\q_int$next[0:0]$12244 - attribute \src "libresoc.v:184145.5-184145.29" + assign $0\q_int$next[0:0]$12427 $1\q_int$next[0:0]$12428 + attribute \src "libresoc.v:186449.5-186449.29" switch \initial - attribute \src "libresoc.v:184145.9-184145.17" + attribute \src "libresoc.v:186449.9-186449.17" case 1'1 case end @@ -383017,92 +387026,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12244 1'0 + assign $1\q_int$next[0:0]$12428 1'0 case - assign $1\q_int$next[0:0]$12244 \$5 + assign $1\q_int$next[0:0]$12428 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12243 + update \q_int$next $0\q_int$next[0:0]$12427 end - connect \$9 $and$libresoc.v:184134$12233_Y - connect \$11 $or$libresoc.v:184135$12234_Y - connect \$13 $not$libresoc.v:184136$12235_Y - connect \$15 $or$libresoc.v:184137$12236_Y - connect \$1 $not$libresoc.v:184138$12237_Y - connect \$3 $and$libresoc.v:184139$12238_Y - connect \$5 $or$libresoc.v:184140$12239_Y - connect \$7 $not$libresoc.v:184141$12240_Y + connect \$9 $and$libresoc.v:186438$12417_Y + connect \$11 $or$libresoc.v:186439$12418_Y + connect \$13 $not$libresoc.v:186440$12419_Y + connect \$15 $or$libresoc.v:186441$12420_Y + connect \$1 $not$libresoc.v:186442$12421_Y + connect \$3 $and$libresoc.v:186443$12422_Y + connect \$5 $or$libresoc.v:186444$12423_Y + connect \$7 $not$libresoc.v:186445$12424_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:184160.1-184569.10" +attribute \src "libresoc.v:186464.1-186873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:184161.7-184161.20" + attribute \src "libresoc.v:186465.7-186465.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:184527.3-184552.6" + attribute \src "libresoc.v:186831.3-186856.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:184506.18-184506.122" - wire $and$libresoc.v:184506$12248_Y - attribute \src "libresoc.v:184508.18-184508.122" - wire $and$libresoc.v:184508$12250_Y - attribute \src "libresoc.v:184517.18-184517.105" - wire $and$libresoc.v:184517$12263_Y - attribute \src "libresoc.v:184520.18-184520.105" - wire $and$libresoc.v:184520$12266_Y - attribute \src "libresoc.v:184516.18-184516.123" - wire $eq$libresoc.v:184516$12262_Y - attribute \src "libresoc.v:184519.18-184519.123" - wire $eq$libresoc.v:184519$12265_Y - attribute \src "libresoc.v:184522.18-184522.117" - wire $eq$libresoc.v:184522$12268_Y - attribute \src "libresoc.v:184509.18-184509.97" - wire width 65 $extend$libresoc.v:184509$12251_Y - attribute \src "libresoc.v:184510.18-184510.91" - wire width 65 $extend$libresoc.v:184510$12253_Y - attribute \src "libresoc.v:184512.18-184512.97" - wire width 65 $extend$libresoc.v:184512$12256_Y - attribute \src "libresoc.v:184513.18-184513.91" - wire width 65 $extend$libresoc.v:184513$12258_Y - attribute \src "libresoc.v:184525.18-184525.99" - wire width 128 $extend$libresoc.v:184525$12271_Y - attribute \src "libresoc.v:184515.18-184515.112" - wire $ge$libresoc.v:184515$12261_Y - attribute \src "libresoc.v:184518.18-184518.124" - wire $ge$libresoc.v:184518$12264_Y - attribute \src "libresoc.v:184509.18-184509.97" - wire width 65 $neg$libresoc.v:184509$12252_Y - attribute \src "libresoc.v:184512.18-184512.97" - wire width 65 $neg$libresoc.v:184512$12257_Y - attribute \src "libresoc.v:184510.18-184510.91" - wire width 65 $pos$libresoc.v:184510$12254_Y - attribute \src "libresoc.v:184513.18-184513.91" - wire width 65 $pos$libresoc.v:184513$12259_Y - attribute \src "libresoc.v:184525.18-184525.99" - wire width 128 $pos$libresoc.v:184525$12272_Y - attribute \src "libresoc.v:184524.18-184524.117" - wire width 95 $sshl$libresoc.v:184524$12270_Y - attribute \src "libresoc.v:184526.18-184526.111" - wire width 191 $sshl$libresoc.v:184526$12273_Y - attribute \src "libresoc.v:184505.18-184505.131" - wire $ternary$libresoc.v:184505$12247_Y - attribute \src "libresoc.v:184507.18-184507.131" - wire $ternary$libresoc.v:184507$12249_Y - attribute \src "libresoc.v:184511.18-184511.119" - wire width 65 $ternary$libresoc.v:184511$12255_Y - attribute \src "libresoc.v:184514.18-184514.120" - wire width 65 $ternary$libresoc.v:184514$12260_Y - attribute \src "libresoc.v:184521.18-184521.130" - wire width 32 $ternary$libresoc.v:184521$12267_Y - attribute \src "libresoc.v:184523.18-184523.131" - wire width 32 $ternary$libresoc.v:184523$12269_Y + attribute \src "libresoc.v:186810.18-186810.122" + wire $and$libresoc.v:186810$12432_Y + attribute \src "libresoc.v:186812.18-186812.122" + wire $and$libresoc.v:186812$12434_Y + attribute \src "libresoc.v:186821.18-186821.105" + wire $and$libresoc.v:186821$12447_Y + attribute \src "libresoc.v:186824.18-186824.105" + wire $and$libresoc.v:186824$12450_Y + attribute \src "libresoc.v:186820.18-186820.123" + wire $eq$libresoc.v:186820$12446_Y + attribute \src "libresoc.v:186823.18-186823.123" + wire $eq$libresoc.v:186823$12449_Y + attribute \src "libresoc.v:186826.18-186826.117" + wire $eq$libresoc.v:186826$12452_Y + attribute \src "libresoc.v:186813.18-186813.97" + wire width 65 $extend$libresoc.v:186813$12435_Y + attribute \src "libresoc.v:186814.18-186814.91" + wire width 65 $extend$libresoc.v:186814$12437_Y + attribute \src "libresoc.v:186816.18-186816.97" + wire width 65 $extend$libresoc.v:186816$12440_Y + attribute \src "libresoc.v:186817.18-186817.91" + wire width 65 $extend$libresoc.v:186817$12442_Y + attribute \src "libresoc.v:186829.18-186829.99" + wire width 128 $extend$libresoc.v:186829$12455_Y + attribute \src "libresoc.v:186819.18-186819.112" + wire $ge$libresoc.v:186819$12445_Y + attribute \src "libresoc.v:186822.18-186822.124" + wire $ge$libresoc.v:186822$12448_Y + attribute \src "libresoc.v:186813.18-186813.97" + wire width 65 $neg$libresoc.v:186813$12436_Y + attribute \src "libresoc.v:186816.18-186816.97" + wire width 65 $neg$libresoc.v:186816$12441_Y + attribute \src "libresoc.v:186814.18-186814.91" + wire width 65 $pos$libresoc.v:186814$12438_Y + attribute \src "libresoc.v:186817.18-186817.91" + wire width 65 $pos$libresoc.v:186817$12443_Y + attribute \src "libresoc.v:186829.18-186829.99" + wire width 128 $pos$libresoc.v:186829$12456_Y + attribute \src "libresoc.v:186828.18-186828.117" + wire width 95 $sshl$libresoc.v:186828$12454_Y + attribute \src "libresoc.v:186830.18-186830.111" + wire width 191 $sshl$libresoc.v:186830$12457_Y + attribute \src "libresoc.v:186809.18-186809.131" + wire $ternary$libresoc.v:186809$12431_Y + attribute \src "libresoc.v:186811.18-186811.131" + wire $ternary$libresoc.v:186811$12433_Y + attribute \src "libresoc.v:186815.18-186815.119" + wire width 65 $ternary$libresoc.v:186815$12439_Y + attribute \src "libresoc.v:186818.18-186818.120" + wire width 65 $ternary$libresoc.v:186818$12444_Y + attribute \src "libresoc.v:186825.18-186825.130" + wire width 32 $ternary$libresoc.v:186825$12451_Y + attribute \src "libresoc.v:186827.18-186827.131" + wire width 32 $ternary$libresoc.v:186827$12453_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -383171,7 +387180,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:184161.7-184161.15" + attribute \src "libresoc.v:186465.7-186465.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -383448,7 +387457,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:184506$12248 + cell $and $and$libresoc.v:186810$12432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383456,10 +387465,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:184506$12248_Y + connect \Y $and$libresoc.v:186810$12432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:184508$12250 + cell $and $and$libresoc.v:186812$12434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383467,10 +387476,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:184508$12250_Y + connect \Y $and$libresoc.v:186812$12434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:184517$12263 + cell $and $and$libresoc.v:186821$12447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383478,10 +387487,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:184517$12263_Y + connect \Y $and$libresoc.v:186821$12447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:184520$12266 + cell $and $and$libresoc.v:186824$12450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383489,10 +387498,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:184520$12266_Y + connect \Y $and$libresoc.v:186824$12450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:184516$12262 + cell $eq $eq$libresoc.v:186820$12446 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -383500,10 +387509,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:184516$12262_Y + connect \Y $eq$libresoc.v:186820$12446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:184519$12265 + cell $eq $eq$libresoc.v:186823$12449 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -383511,10 +387520,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:184519$12265_Y + connect \Y $eq$libresoc.v:186823$12449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:184522$12268 + cell $eq $eq$libresoc.v:186826$12452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383522,50 +387531,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:184522$12268_Y + connect \Y $eq$libresoc.v:186826$12452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:184509$12251 + cell $pos $extend$libresoc.v:186813$12435 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:184509$12251_Y + connect \Y $extend$libresoc.v:186813$12435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:184510$12253 + cell $pos $extend$libresoc.v:186814$12437 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:184510$12253_Y + connect \Y $extend$libresoc.v:186814$12437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:184512$12256 + cell $pos $extend$libresoc.v:186816$12440 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:184512$12256_Y + connect \Y $extend$libresoc.v:186816$12440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:184513$12258 + cell $pos $extend$libresoc.v:186817$12442 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:184513$12258_Y + connect \Y $extend$libresoc.v:186817$12442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:184525$12271 + cell $pos $extend$libresoc.v:186829$12455 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:184525$12271_Y + connect \Y $extend$libresoc.v:186829$12455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:184515$12261 + cell $ge $ge$libresoc.v:186819$12445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383573,10 +387582,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:184515$12261_Y + connect \Y $ge$libresoc.v:186819$12445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:184518$12264 + cell $ge $ge$libresoc.v:186822$12448 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -383584,50 +387593,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:184518$12264_Y + connect \Y $ge$libresoc.v:186822$12448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:184509$12252 + cell $neg $neg$libresoc.v:186813$12436 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184509$12251_Y - connect \Y $neg$libresoc.v:184509$12252_Y + connect \A $extend$libresoc.v:186813$12435_Y + connect \Y $neg$libresoc.v:186813$12436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:184512$12257 + cell $neg $neg$libresoc.v:186816$12441 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184512$12256_Y - connect \Y $neg$libresoc.v:184512$12257_Y + connect \A $extend$libresoc.v:186816$12440_Y + connect \Y $neg$libresoc.v:186816$12441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:184510$12254 + cell $pos $pos$libresoc.v:186814$12438 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184510$12253_Y - connect \Y $pos$libresoc.v:184510$12254_Y + connect \A $extend$libresoc.v:186814$12437_Y + connect \Y $pos$libresoc.v:186814$12438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:184513$12259 + cell $pos $pos$libresoc.v:186817$12443 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:184513$12258_Y - connect \Y $pos$libresoc.v:184513$12259_Y + connect \A $extend$libresoc.v:186817$12442_Y + connect \Y $pos$libresoc.v:186817$12443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:184525$12272 + cell $pos $pos$libresoc.v:186829$12456 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:184525$12271_Y - connect \Y $pos$libresoc.v:184525$12272_Y + connect \A $extend$libresoc.v:186829$12455_Y + connect \Y $pos$libresoc.v:186829$12456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:184524$12270 + cell $sshl $sshl$libresoc.v:186828$12454 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -383635,10 +387644,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:184524$12270_Y + connect \Y $sshl$libresoc.v:186828$12454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:184526$12273 + cell $sshl $sshl$libresoc.v:186830$12457 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -383646,72 +387655,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:184526$12273_Y + connect \Y $sshl$libresoc.v:186830$12457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:184505$12247 + cell $mux $ternary$libresoc.v:186809$12431 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184505$12247_Y + connect \Y $ternary$libresoc.v:186809$12431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:184507$12249 + cell $mux $ternary$libresoc.v:186811$12433 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184507$12249_Y + connect \Y $ternary$libresoc.v:186811$12433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:184511$12255 + cell $mux $ternary$libresoc.v:186815$12439 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:184511$12255_Y + connect \Y $ternary$libresoc.v:186815$12439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:184514$12260 + cell $mux $ternary$libresoc.v:186818$12444 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:184514$12260_Y + connect \Y $ternary$libresoc.v:186818$12444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:184521$12267 + cell $mux $ternary$libresoc.v:186825$12451 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184521$12267_Y + connect \Y $ternary$libresoc.v:186825$12451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:184523$12269 + cell $mux $ternary$libresoc.v:186827$12453 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:184523$12269_Y + connect \Y $ternary$libresoc.v:186827$12453_Y end - attribute \src "libresoc.v:184161.7-184161.20" - process $proc$libresoc.v:184161$12275 + attribute \src "libresoc.v:186465.7-186465.20" + process $proc$libresoc.v:186465$12459 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184527.3-184552.6" - process $proc$libresoc.v:184527$12274 + attribute \src "libresoc.v:186831.3-186856.6" + process $proc$libresoc.v:186831$12458 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:184528.5-184528.29" + attribute \src "libresoc.v:186832.5-186832.29" switch \initial - attribute \src "libresoc.v:184528.9-184528.17" + attribute \src "libresoc.v:186832.9-186832.17" case 1'1 case end @@ -383743,28 +387752,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:184505$12247_Y - connect \$23 $and$libresoc.v:184506$12248_Y - connect \$25 $ternary$libresoc.v:184507$12249_Y - connect \$27 $and$libresoc.v:184508$12250_Y - connect \$30 $neg$libresoc.v:184509$12252_Y - connect \$32 $pos$libresoc.v:184510$12254_Y - connect \$34 $ternary$libresoc.v:184511$12255_Y - connect \$37 $neg$libresoc.v:184512$12257_Y - connect \$39 $pos$libresoc.v:184513$12259_Y - connect \$41 $ternary$libresoc.v:184514$12260_Y - connect \$43 $ge$libresoc.v:184515$12261_Y - connect \$45 $eq$libresoc.v:184516$12262_Y - connect \$47 $and$libresoc.v:184517$12263_Y - connect \$49 $ge$libresoc.v:184518$12264_Y - connect \$51 $eq$libresoc.v:184519$12265_Y - connect \$53 $and$libresoc.v:184520$12266_Y - connect \$55 $ternary$libresoc.v:184521$12267_Y - connect \$57 $eq$libresoc.v:184522$12268_Y - connect \$59 $ternary$libresoc.v:184523$12269_Y - connect \$62 $sshl$libresoc.v:184524$12270_Y - connect \$61 $pos$libresoc.v:184525$12272_Y - connect \$66 $sshl$libresoc.v:184526$12273_Y + connect \$21 $ternary$libresoc.v:186809$12431_Y + connect \$23 $and$libresoc.v:186810$12432_Y + connect \$25 $ternary$libresoc.v:186811$12433_Y + connect \$27 $and$libresoc.v:186812$12434_Y + connect \$30 $neg$libresoc.v:186813$12436_Y + connect \$32 $pos$libresoc.v:186814$12438_Y + connect \$34 $ternary$libresoc.v:186815$12439_Y + connect \$37 $neg$libresoc.v:186816$12441_Y + connect \$39 $pos$libresoc.v:186817$12443_Y + connect \$41 $ternary$libresoc.v:186818$12444_Y + connect \$43 $ge$libresoc.v:186819$12445_Y + connect \$45 $eq$libresoc.v:186820$12446_Y + connect \$47 $and$libresoc.v:186821$12447_Y + connect \$49 $ge$libresoc.v:186822$12448_Y + connect \$51 $eq$libresoc.v:186823$12449_Y + connect \$53 $and$libresoc.v:186824$12450_Y + connect \$55 $ternary$libresoc.v:186825$12451_Y + connect \$57 $eq$libresoc.v:186826$12452_Y + connect \$59 $ternary$libresoc.v:186827$12453_Y + connect \$62 $sshl$libresoc.v:186828$12454_Y + connect \$61 $pos$libresoc.v:186829$12456_Y + connect \$66 $sshl$libresoc.v:186830$12457_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -383782,513 +387791,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:184573.1-185780.10" +attribute \src "libresoc.v:186877.1-188084.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:185351.3-185352.25" + attribute \src "libresoc.v:187655.3-187656.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:185349.3-185350.46" + attribute \src "libresoc.v:187653.3-187654.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:185700.3-185708.6" - wire $0\alu_l_r_alu$next[0:0]$12493 - attribute \src "libresoc.v:185267.3-185268.39" + attribute \src "libresoc.v:188004.3-188012.6" + wire $0\alu_l_r_alu$next[0:0]$12677 + attribute \src "libresoc.v:187571.3-187572.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 - attribute \src "libresoc.v:185295.3-185296.75" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + attribute \src "libresoc.v:187599.3-187600.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 - attribute \src "libresoc.v:185297.3-185298.89" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + attribute \src "libresoc.v:187601.3-187602.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 - attribute \src "libresoc.v:185299.3-185300.85" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + attribute \src "libresoc.v:187603.3-187604.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 - attribute \src "libresoc.v:185313.3-185314.83" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + attribute \src "libresoc.v:187617.3-187618.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 - attribute \src "libresoc.v:185317.3-185318.77" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + attribute \src "libresoc.v:187621.3-187622.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 - attribute \src "libresoc.v:185325.3-185326.69" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + attribute \src "libresoc.v:187629.3-187630.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 - attribute \src "libresoc.v:185293.3-185294.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + attribute \src "libresoc.v:187597.3-187598.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 - attribute \src "libresoc.v:185311.3-185312.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + attribute \src "libresoc.v:187615.3-187616.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 - attribute \src "libresoc.v:185321.3-185322.77" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + attribute \src "libresoc.v:187625.3-187626.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 - attribute \src "libresoc.v:185323.3-185324.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + attribute \src "libresoc.v:187627.3-187628.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 - attribute \src "libresoc.v:185305.3-185306.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + attribute \src "libresoc.v:187609.3-187610.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 - attribute \src "libresoc.v:185307.3-185308.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + attribute \src "libresoc.v:187611.3-187612.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 - attribute \src "libresoc.v:185315.3-185316.85" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + attribute \src "libresoc.v:187619.3-187620.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 - attribute \src "libresoc.v:185319.3-185320.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + attribute \src "libresoc.v:187623.3-187624.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 - attribute \src "libresoc.v:185303.3-185304.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + attribute \src "libresoc.v:187607.3-187608.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 - attribute \src "libresoc.v:185301.3-185302.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + attribute \src "libresoc.v:187605.3-187606.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 - attribute \src "libresoc.v:185309.3-185310.79" + attribute \src "libresoc.v:187841.3-187878.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + attribute \src "libresoc.v:187613.3-187614.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:185691.3-185699.6" - wire $0\alui_l_r_alui$next[0:0]$12490 - attribute \src "libresoc.v:185269.3-185270.43" + attribute \src "libresoc.v:187995.3-188003.6" + wire $0\alui_l_r_alui$next[0:0]$12674 + attribute \src "libresoc.v:187573.3-187574.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $0\data_r0__o$next[63:0]$12451 - attribute \src "libresoc.v:185289.3-185290.37" + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $0\data_r0__o$next[63:0]$12635 + attribute \src "libresoc.v:187593.3-187594.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire $0\data_r0__o_ok$next[0:0]$12452 - attribute \src "libresoc.v:185291.3-185292.43" + attribute \src "libresoc.v:187879.3-187900.6" + wire $0\data_r0__o_ok$next[0:0]$12636 + attribute \src "libresoc.v:187595.3-187596.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12459 - attribute \src "libresoc.v:185285.3-185286.43" + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12643 + attribute \src "libresoc.v:187589.3-187590.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12460 - attribute \src "libresoc.v:185287.3-185288.49" + attribute \src "libresoc.v:187901.3-187922.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12644 + attribute \src "libresoc.v:187591.3-187592.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12467 - attribute \src "libresoc.v:185281.3-185282.47" + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 + attribute \src "libresoc.v:187585.3-187586.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12468 - attribute \src "libresoc.v:185283.3-185284.53" + attribute \src "libresoc.v:187923.3-187944.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12652 + attribute \src "libresoc.v:187587.3-187588.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:185709.3-185718.6" + attribute \src "libresoc.v:188013.3-188022.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:185719.3-185728.6" + attribute \src "libresoc.v:188023.3-188032.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:185729.3-185738.6" + attribute \src "libresoc.v:188033.3-188042.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:184574.7-184574.20" + attribute \src "libresoc.v:186878.7-186878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185492.3-185500.6" - wire $0\opc_l_r_opc$next[0:0]$12395 - attribute \src "libresoc.v:185335.3-185336.39" + attribute \src "libresoc.v:187796.3-187804.6" + wire $0\opc_l_r_opc$next[0:0]$12579 + attribute \src "libresoc.v:187639.3-187640.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:185483.3-185491.6" - wire $0\opc_l_s_opc$next[0:0]$12392 - attribute \src "libresoc.v:185337.3-185338.39" + attribute \src "libresoc.v:187787.3-187795.6" + wire $0\opc_l_s_opc$next[0:0]$12576 + attribute \src "libresoc.v:187641.3-187642.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire width 3 $0\prev_wr_go$next[2:0]$12499 - attribute \src "libresoc.v:185347.3-185348.37" + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $0\prev_wr_go$next[2:0]$12683 + attribute \src "libresoc.v:187651.3-187652.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:185437.3-185446.6" + attribute \src "libresoc.v:187741.3-187750.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:185528.3-185536.6" - wire width 3 $0\req_l_r_req$next[2:0]$12407 - attribute \src "libresoc.v:185327.3-185328.39" + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $0\req_l_r_req$next[2:0]$12591 + attribute \src "libresoc.v:187631.3-187632.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:185519.3-185527.6" - wire width 3 $0\req_l_s_req$next[2:0]$12404 - attribute \src "libresoc.v:185329.3-185330.39" + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $0\req_l_s_req$next[2:0]$12588 + attribute \src "libresoc.v:187633.3-187634.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:185456.3-185464.6" - wire $0\rok_l_r_rdok$next[0:0]$12383 - attribute \src "libresoc.v:185343.3-185344.41" + attribute \src "libresoc.v:187760.3-187768.6" + wire $0\rok_l_r_rdok$next[0:0]$12567 + attribute \src "libresoc.v:187647.3-187648.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:185447.3-185455.6" - wire $0\rok_l_s_rdok$next[0:0]$12380 - attribute \src "libresoc.v:185345.3-185346.41" + attribute \src "libresoc.v:187751.3-187759.6" + wire $0\rok_l_s_rdok$next[0:0]$12564 + attribute \src "libresoc.v:187649.3-187650.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:185474.3-185482.6" - wire $0\rst_l_r_rst$next[0:0]$12389 - attribute \src "libresoc.v:185339.3-185340.39" + attribute \src "libresoc.v:187778.3-187786.6" + wire $0\rst_l_r_rst$next[0:0]$12573 + attribute \src "libresoc.v:187643.3-187644.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:185465.3-185473.6" - wire $0\rst_l_s_rst$next[0:0]$12386 - attribute \src "libresoc.v:185341.3-185342.39" + attribute \src "libresoc.v:187769.3-187777.6" + wire $0\rst_l_s_rst$next[0:0]$12570 + attribute \src "libresoc.v:187645.3-187646.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:185510.3-185518.6" - wire width 5 $0\src_l_r_src$next[4:0]$12401 - attribute \src "libresoc.v:185331.3-185332.39" + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $0\src_l_r_src$next[4:0]$12585 + attribute \src "libresoc.v:187635.3-187636.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:185501.3-185509.6" - wire width 5 $0\src_l_s_src$next[4:0]$12398 - attribute \src "libresoc.v:185333.3-185334.39" + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $0\src_l_s_src$next[4:0]$12582 + attribute \src "libresoc.v:187637.3-187638.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:185641.3-185650.6" - wire width 64 $0\src_r0$next[63:0]$12475 - attribute \src "libresoc.v:185279.3-185280.29" + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $0\src_r0$next[63:0]$12659 + attribute \src "libresoc.v:187583.3-187584.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:185651.3-185660.6" - wire width 64 $0\src_r1$next[63:0]$12478 - attribute \src "libresoc.v:185277.3-185278.29" + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $0\src_r1$next[63:0]$12662 + attribute \src "libresoc.v:187581.3-187582.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:185661.3-185670.6" - wire width 64 $0\src_r2$next[63:0]$12481 - attribute \src "libresoc.v:185275.3-185276.29" + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $0\src_r2$next[63:0]$12665 + attribute \src "libresoc.v:187579.3-187580.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:185671.3-185680.6" - wire $0\src_r3$next[0:0]$12484 - attribute \src "libresoc.v:185273.3-185274.29" + attribute \src "libresoc.v:187975.3-187984.6" + wire $0\src_r3$next[0:0]$12668 + attribute \src "libresoc.v:187577.3-187578.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:185681.3-185690.6" - wire width 2 $0\src_r4$next[1:0]$12487 - attribute \src "libresoc.v:185271.3-185272.29" + attribute \src "libresoc.v:187985.3-187994.6" + wire width 2 $0\src_r4$next[1:0]$12671 + attribute \src "libresoc.v:187575.3-187576.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:184696.7-184696.24" + attribute \src "libresoc.v:187000.7-187000.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:184706.7-184706.26" + attribute \src "libresoc.v:187010.7-187010.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:185700.3-185708.6" - wire $1\alu_l_r_alu$next[0:0]$12494 - attribute \src "libresoc.v:184714.7-184714.25" + attribute \src "libresoc.v:188004.3-188012.6" + wire $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:187018.7-187018.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 - attribute \src "libresoc.v:184757.14-184757.54" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + attribute \src "libresoc.v:187061.14-187061.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 - attribute \src "libresoc.v:184761.14-184761.73" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + attribute \src "libresoc.v:187065.14-187065.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 - attribute \src "libresoc.v:184765.7-184765.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + attribute \src "libresoc.v:187069.7-187069.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 - attribute \src "libresoc.v:184773.13-184773.53" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + attribute \src "libresoc.v:187077.13-187077.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 - attribute \src "libresoc.v:184777.7-184777.44" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + attribute \src "libresoc.v:187081.7-187081.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 - attribute \src "libresoc.v:184781.14-184781.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + attribute \src "libresoc.v:187085.14-187085.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 - attribute \src "libresoc.v:184860.13-184860.52" + attribute \src "libresoc.v:187841.3-187878.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + attribute \src "libresoc.v:187164.13-187164.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 - attribute \src "libresoc.v:184864.7-184864.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + attribute \src "libresoc.v:187168.7-187168.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 - attribute \src "libresoc.v:184868.7-184868.44" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + attribute \src "libresoc.v:187172.7-187172.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 - attribute \src "libresoc.v:184872.7-184872.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + attribute \src "libresoc.v:187176.7-187176.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 - attribute \src "libresoc.v:184876.7-184876.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + attribute \src "libresoc.v:187180.7-187180.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 - attribute \src "libresoc.v:184880.7-184880.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + attribute \src "libresoc.v:187184.7-187184.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 - attribute \src "libresoc.v:184884.7-184884.48" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + attribute \src "libresoc.v:187188.7-187188.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 - attribute \src "libresoc.v:184888.7-184888.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + attribute \src "libresoc.v:187192.7-187192.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 - attribute \src "libresoc.v:184892.7-184892.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + attribute \src "libresoc.v:187196.7-187196.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 - attribute \src "libresoc.v:184896.7-184896.42" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + attribute \src "libresoc.v:187200.7-187200.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 - attribute \src "libresoc.v:184900.7-184900.45" + attribute \src "libresoc.v:187841.3-187878.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + attribute \src "libresoc.v:187204.7-187204.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:185691.3-185699.6" - wire $1\alui_l_r_alui$next[0:0]$12491 - attribute \src "libresoc.v:184912.7-184912.27" + attribute \src "libresoc.v:187995.3-188003.6" + wire $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187216.7-187216.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $1\data_r0__o$next[63:0]$12453 - attribute \src "libresoc.v:184946.14-184946.47" + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $1\data_r0__o$next[63:0]$12637 + attribute \src "libresoc.v:187250.14-187250.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:185575.3-185596.6" - wire $1\data_r0__o_ok$next[0:0]$12454 - attribute \src "libresoc.v:184950.7-184950.27" + attribute \src "libresoc.v:187879.3-187900.6" + wire $1\data_r0__o_ok$next[0:0]$12638 + attribute \src "libresoc.v:187254.7-187254.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12461 - attribute \src "libresoc.v:184954.13-184954.33" + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12645 + attribute \src "libresoc.v:187258.13-187258.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:185597.3-185618.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12462 - attribute \src "libresoc.v:184958.7-184958.30" + attribute \src "libresoc.v:187901.3-187922.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12646 + attribute \src "libresoc.v:187262.7-187262.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12469 - attribute \src "libresoc.v:184962.13-184962.35" + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 + attribute \src "libresoc.v:187266.13-187266.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:185619.3-185640.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12470 - attribute \src "libresoc.v:184966.7-184966.32" + attribute \src "libresoc.v:187923.3-187944.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12654 + attribute \src "libresoc.v:187270.7-187270.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:185709.3-185718.6" + attribute \src "libresoc.v:188013.3-188022.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:185719.3-185728.6" + attribute \src "libresoc.v:188023.3-188032.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:185729.3-185738.6" + attribute \src "libresoc.v:188033.3-188042.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:185492.3-185500.6" - wire $1\opc_l_r_opc$next[0:0]$12396 - attribute \src "libresoc.v:184983.7-184983.25" + attribute \src "libresoc.v:187796.3-187804.6" + wire $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187287.7-187287.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:185483.3-185491.6" - wire $1\opc_l_s_opc$next[0:0]$12393 - attribute \src "libresoc.v:184987.7-184987.25" + attribute \src "libresoc.v:187787.3-187795.6" + wire $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187291.7-187291.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:185739.3-185747.6" - wire width 3 $1\prev_wr_go$next[2:0]$12500 - attribute \src "libresoc.v:185119.13-185119.30" + attribute \src "libresoc.v:188043.3-188051.6" + wire width 3 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:187423.13-187423.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:185437.3-185446.6" + attribute \src "libresoc.v:187741.3-187750.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:185528.3-185536.6" - wire width 3 $1\req_l_r_req$next[2:0]$12408 - attribute \src "libresoc.v:185127.13-185127.31" + attribute \src "libresoc.v:187832.3-187840.6" + wire width 3 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187431.13-187431.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:185519.3-185527.6" - wire width 3 $1\req_l_s_req$next[2:0]$12405 - attribute \src "libresoc.v:185131.13-185131.31" + attribute \src "libresoc.v:187823.3-187831.6" + wire width 3 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187435.13-187435.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:185456.3-185464.6" - wire $1\rok_l_r_rdok$next[0:0]$12384 - attribute \src "libresoc.v:185143.7-185143.26" + attribute \src "libresoc.v:187760.3-187768.6" + wire $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187447.7-187447.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:185447.3-185455.6" - wire $1\rok_l_s_rdok$next[0:0]$12381 - attribute \src "libresoc.v:185147.7-185147.26" + attribute \src "libresoc.v:187751.3-187759.6" + wire $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187451.7-187451.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:185474.3-185482.6" - wire $1\rst_l_r_rst$next[0:0]$12390 - attribute \src "libresoc.v:185151.7-185151.25" + attribute \src "libresoc.v:187778.3-187786.6" + wire $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187455.7-187455.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:185465.3-185473.6" - wire $1\rst_l_s_rst$next[0:0]$12387 - attribute \src "libresoc.v:185155.7-185155.25" + attribute \src "libresoc.v:187769.3-187777.6" + wire $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187459.7-187459.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:185510.3-185518.6" - wire width 5 $1\src_l_r_src$next[4:0]$12402 - attribute \src "libresoc.v:185173.13-185173.32" + attribute \src "libresoc.v:187814.3-187822.6" + wire width 5 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187477.13-187477.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:185501.3-185509.6" - wire width 5 $1\src_l_s_src$next[4:0]$12399 - attribute \src "libresoc.v:185177.13-185177.32" + attribute \src "libresoc.v:187805.3-187813.6" + wire width 5 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187481.13-187481.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:185641.3-185650.6" - wire width 64 $1\src_r0$next[63:0]$12476 - attribute \src "libresoc.v:185183.14-185183.43" + attribute \src "libresoc.v:187945.3-187954.6" + wire width 64 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187487.14-187487.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:185651.3-185660.6" - wire width 64 $1\src_r1$next[63:0]$12479 - attribute \src "libresoc.v:185187.14-185187.43" + attribute \src "libresoc.v:187955.3-187964.6" + wire width 64 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187491.14-187491.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:185661.3-185670.6" - wire width 64 $1\src_r2$next[63:0]$12482 - attribute \src "libresoc.v:185191.14-185191.43" + attribute \src "libresoc.v:187965.3-187974.6" + wire width 64 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187495.14-187495.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:185671.3-185680.6" - wire $1\src_r3$next[0:0]$12485 - attribute \src "libresoc.v:185195.7-185195.20" + attribute \src "libresoc.v:187975.3-187984.6" + wire $1\src_r3$next[0:0]$12669 + attribute \src "libresoc.v:187499.7-187499.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:185681.3-185690.6" - wire width 2 $1\src_r4$next[1:0]$12488 - attribute \src "libresoc.v:185199.13-185199.26" + attribute \src "libresoc.v:187985.3-187994.6" + wire width 2 $1\src_r4$next[1:0]$12672 + attribute \src "libresoc.v:187503.13-187503.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:185537.3-185574.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 - attribute \src "libresoc.v:185537.3-185574.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 - attribute \src "libresoc.v:185575.3-185596.6" - wire width 64 $2\data_r0__o$next[63:0]$12455 - attribute \src "libresoc.v:185575.3-185596.6" - wire $2\data_r0__o_ok$next[0:0]$12456 - attribute \src "libresoc.v:185597.3-185618.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12463 - attribute \src "libresoc.v:185597.3-185618.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12464 - attribute \src "libresoc.v:185619.3-185640.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12471 - attribute \src "libresoc.v:185619.3-185640.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12472 - attribute \src "libresoc.v:185575.3-185596.6" - wire $3\data_r0__o_ok$next[0:0]$12457 - attribute \src "libresoc.v:185597.3-185618.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12465 - attribute \src "libresoc.v:185619.3-185640.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12473 - attribute \src "libresoc.v:185209.19-185209.114" - wire width 5 $and$libresoc.v:185209$12277_Y - attribute \src "libresoc.v:185210.19-185210.125" - wire $and$libresoc.v:185210$12278_Y - attribute \src "libresoc.v:185211.19-185211.125" - wire $and$libresoc.v:185211$12279_Y - attribute \src "libresoc.v:185212.19-185212.125" - wire $and$libresoc.v:185212$12280_Y - attribute \src "libresoc.v:185213.18-185213.110" - wire $and$libresoc.v:185213$12281_Y - attribute \src "libresoc.v:185214.19-185214.141" - wire width 3 $and$libresoc.v:185214$12282_Y - attribute \src "libresoc.v:185215.19-185215.121" - wire width 3 $and$libresoc.v:185215$12283_Y - attribute \src "libresoc.v:185216.19-185216.127" - wire $and$libresoc.v:185216$12284_Y - attribute \src "libresoc.v:185217.19-185217.127" - wire $and$libresoc.v:185217$12285_Y - attribute \src "libresoc.v:185218.19-185218.127" - wire $and$libresoc.v:185218$12286_Y - attribute \src "libresoc.v:185220.18-185220.98" - wire $and$libresoc.v:185220$12288_Y - attribute \src "libresoc.v:185222.18-185222.100" - wire $and$libresoc.v:185222$12290_Y - attribute \src "libresoc.v:185223.18-185223.149" - wire width 3 $and$libresoc.v:185223$12291_Y - attribute \src "libresoc.v:185225.18-185225.119" - wire width 3 $and$libresoc.v:185225$12293_Y - attribute \src "libresoc.v:185228.17-185228.123" - wire $and$libresoc.v:185228$12296_Y - attribute \src "libresoc.v:185229.18-185229.116" - wire $and$libresoc.v:185229$12297_Y - attribute \src "libresoc.v:185234.18-185234.113" - wire $and$libresoc.v:185234$12302_Y - attribute \src "libresoc.v:185235.18-185235.125" - wire width 3 $and$libresoc.v:185235$12303_Y - attribute \src "libresoc.v:185237.18-185237.112" - wire $and$libresoc.v:185237$12305_Y - attribute \src "libresoc.v:185239.18-185239.132" - wire $and$libresoc.v:185239$12307_Y - attribute \src "libresoc.v:185240.18-185240.132" - wire $and$libresoc.v:185240$12308_Y - attribute \src "libresoc.v:185241.18-185241.117" - wire $and$libresoc.v:185241$12309_Y - attribute \src "libresoc.v:185247.18-185247.136" - wire $and$libresoc.v:185247$12315_Y - attribute \src "libresoc.v:185248.18-185248.124" - wire width 3 $and$libresoc.v:185248$12316_Y - attribute \src "libresoc.v:185250.18-185250.116" - wire $and$libresoc.v:185250$12318_Y - attribute \src "libresoc.v:185251.18-185251.119" - wire $and$libresoc.v:185251$12319_Y - attribute \src "libresoc.v:185252.18-185252.121" - wire $and$libresoc.v:185252$12320_Y - attribute \src "libresoc.v:185262.18-185262.140" - wire $and$libresoc.v:185262$12330_Y - attribute \src "libresoc.v:185263.18-185263.138" - wire $and$libresoc.v:185263$12331_Y - attribute \src "libresoc.v:185264.18-185264.171" - wire width 5 $and$libresoc.v:185264$12332_Y - attribute \src "libresoc.v:185266.18-185266.129" - wire width 5 $and$libresoc.v:185266$12334_Y - attribute \src "libresoc.v:185236.18-185236.113" - wire $eq$libresoc.v:185236$12304_Y - attribute \src "libresoc.v:185238.18-185238.119" - wire $eq$libresoc.v:185238$12306_Y - attribute \src "libresoc.v:185208.19-185208.115" - wire width 5 $not$libresoc.v:185208$12276_Y - attribute \src "libresoc.v:185219.18-185219.97" - wire $not$libresoc.v:185219$12287_Y - attribute \src "libresoc.v:185221.18-185221.99" - wire $not$libresoc.v:185221$12289_Y - attribute \src "libresoc.v:185224.18-185224.113" - wire width 3 $not$libresoc.v:185224$12292_Y - attribute \src "libresoc.v:185227.18-185227.106" - wire $not$libresoc.v:185227$12295_Y - attribute \src "libresoc.v:185233.18-185233.126" - wire $not$libresoc.v:185233$12301_Y - attribute \src "libresoc.v:185244.17-185244.113" - wire width 5 $not$libresoc.v:185244$12312_Y - attribute \src "libresoc.v:185265.18-185265.136" - wire $not$libresoc.v:185265$12333_Y - attribute \src "libresoc.v:185232.18-185232.112" - wire $or$libresoc.v:185232$12300_Y - attribute \src "libresoc.v:185242.18-185242.122" - wire $or$libresoc.v:185242$12310_Y - attribute \src "libresoc.v:185243.18-185243.124" - wire $or$libresoc.v:185243$12311_Y - attribute \src "libresoc.v:185245.18-185245.155" - wire width 3 $or$libresoc.v:185245$12313_Y - attribute \src "libresoc.v:185246.18-185246.181" - wire width 5 $or$libresoc.v:185246$12314_Y - attribute \src "libresoc.v:185249.18-185249.120" - wire width 3 $or$libresoc.v:185249$12317_Y - attribute \src "libresoc.v:185255.17-185255.117" - wire width 5 $or$libresoc.v:185255$12323_Y - attribute \src "libresoc.v:185261.17-185261.104" - wire $reduce_and$libresoc.v:185261$12329_Y - attribute \src "libresoc.v:185226.18-185226.106" - wire $reduce_or$libresoc.v:185226$12294_Y - attribute \src "libresoc.v:185230.18-185230.113" - wire $reduce_or$libresoc.v:185230$12298_Y - attribute \src "libresoc.v:185231.18-185231.112" - wire $reduce_or$libresoc.v:185231$12299_Y - attribute \src "libresoc.v:185253.18-185253.165" - wire $ternary$libresoc.v:185253$12321_Y - attribute \src "libresoc.v:185254.18-185254.182" - wire width 64 $ternary$libresoc.v:185254$12322_Y - attribute \src "libresoc.v:185256.18-185256.118" - wire width 64 $ternary$libresoc.v:185256$12324_Y - attribute \src "libresoc.v:185257.18-185257.115" - wire width 64 $ternary$libresoc.v:185257$12325_Y - attribute \src "libresoc.v:185258.18-185258.118" - wire width 64 $ternary$libresoc.v:185258$12326_Y - attribute \src "libresoc.v:185259.18-185259.118" - wire $ternary$libresoc.v:185259$12327_Y - attribute \src "libresoc.v:185260.18-185260.118" - wire width 2 $ternary$libresoc.v:185260$12328_Y + attribute \src "libresoc.v:187841.3-187878.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 + attribute \src "libresoc.v:187841.3-187878.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 + attribute \src "libresoc.v:187879.3-187900.6" + wire width 64 $2\data_r0__o$next[63:0]$12639 + attribute \src "libresoc.v:187879.3-187900.6" + wire $2\data_r0__o_ok$next[0:0]$12640 + attribute \src "libresoc.v:187901.3-187922.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12647 + attribute \src "libresoc.v:187901.3-187922.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12648 + attribute \src "libresoc.v:187923.3-187944.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12655 + attribute \src "libresoc.v:187923.3-187944.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12656 + attribute \src "libresoc.v:187879.3-187900.6" + wire $3\data_r0__o_ok$next[0:0]$12641 + attribute \src "libresoc.v:187901.3-187922.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12649 + attribute \src "libresoc.v:187923.3-187944.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12657 + attribute \src "libresoc.v:187513.19-187513.114" + wire width 5 $and$libresoc.v:187513$12461_Y + attribute \src "libresoc.v:187514.19-187514.125" + wire $and$libresoc.v:187514$12462_Y + attribute \src "libresoc.v:187515.19-187515.125" + wire $and$libresoc.v:187515$12463_Y + attribute \src "libresoc.v:187516.19-187516.125" + wire $and$libresoc.v:187516$12464_Y + attribute \src "libresoc.v:187517.18-187517.110" + wire $and$libresoc.v:187517$12465_Y + attribute \src "libresoc.v:187518.19-187518.141" + wire width 3 $and$libresoc.v:187518$12466_Y + attribute \src "libresoc.v:187519.19-187519.121" + wire width 3 $and$libresoc.v:187519$12467_Y + attribute \src "libresoc.v:187520.19-187520.127" + wire $and$libresoc.v:187520$12468_Y + attribute \src "libresoc.v:187521.19-187521.127" + wire $and$libresoc.v:187521$12469_Y + attribute \src "libresoc.v:187522.19-187522.127" + wire $and$libresoc.v:187522$12470_Y + attribute \src "libresoc.v:187524.18-187524.98" + wire $and$libresoc.v:187524$12472_Y + attribute \src "libresoc.v:187526.18-187526.100" + wire $and$libresoc.v:187526$12474_Y + attribute \src "libresoc.v:187527.18-187527.149" + wire width 3 $and$libresoc.v:187527$12475_Y + attribute \src "libresoc.v:187529.18-187529.119" + wire width 3 $and$libresoc.v:187529$12477_Y + attribute \src "libresoc.v:187532.17-187532.123" + wire $and$libresoc.v:187532$12480_Y + attribute \src "libresoc.v:187533.18-187533.116" + wire $and$libresoc.v:187533$12481_Y + attribute \src "libresoc.v:187538.18-187538.113" + wire $and$libresoc.v:187538$12486_Y + attribute \src "libresoc.v:187539.18-187539.125" + wire width 3 $and$libresoc.v:187539$12487_Y + attribute \src "libresoc.v:187541.18-187541.112" + wire $and$libresoc.v:187541$12489_Y + attribute \src "libresoc.v:187543.18-187543.132" + wire $and$libresoc.v:187543$12491_Y + attribute \src "libresoc.v:187544.18-187544.132" + wire $and$libresoc.v:187544$12492_Y + attribute \src "libresoc.v:187545.18-187545.117" + wire $and$libresoc.v:187545$12493_Y + attribute \src "libresoc.v:187551.18-187551.136" + wire $and$libresoc.v:187551$12499_Y + attribute \src "libresoc.v:187552.18-187552.124" + wire width 3 $and$libresoc.v:187552$12500_Y + attribute \src "libresoc.v:187554.18-187554.116" + wire $and$libresoc.v:187554$12502_Y + attribute \src "libresoc.v:187555.18-187555.119" + wire $and$libresoc.v:187555$12503_Y + attribute \src "libresoc.v:187556.18-187556.121" + wire $and$libresoc.v:187556$12504_Y + attribute \src "libresoc.v:187566.18-187566.140" + wire $and$libresoc.v:187566$12514_Y + attribute \src "libresoc.v:187567.18-187567.138" + wire $and$libresoc.v:187567$12515_Y + attribute \src "libresoc.v:187568.18-187568.171" + wire width 5 $and$libresoc.v:187568$12516_Y + attribute \src "libresoc.v:187570.18-187570.129" + wire width 5 $and$libresoc.v:187570$12518_Y + attribute \src "libresoc.v:187540.18-187540.113" + wire $eq$libresoc.v:187540$12488_Y + attribute \src "libresoc.v:187542.18-187542.119" + wire $eq$libresoc.v:187542$12490_Y + attribute \src "libresoc.v:187512.19-187512.115" + wire width 5 $not$libresoc.v:187512$12460_Y + attribute \src "libresoc.v:187523.18-187523.97" + wire $not$libresoc.v:187523$12471_Y + attribute \src "libresoc.v:187525.18-187525.99" + wire $not$libresoc.v:187525$12473_Y + attribute \src "libresoc.v:187528.18-187528.113" + wire width 3 $not$libresoc.v:187528$12476_Y + attribute \src "libresoc.v:187531.18-187531.106" + wire $not$libresoc.v:187531$12479_Y + attribute \src "libresoc.v:187537.18-187537.126" + wire $not$libresoc.v:187537$12485_Y + attribute \src "libresoc.v:187548.17-187548.113" + wire width 5 $not$libresoc.v:187548$12496_Y + attribute \src "libresoc.v:187569.18-187569.136" + wire $not$libresoc.v:187569$12517_Y + attribute \src "libresoc.v:187536.18-187536.112" + wire $or$libresoc.v:187536$12484_Y + attribute \src "libresoc.v:187546.18-187546.122" + wire $or$libresoc.v:187546$12494_Y + attribute \src "libresoc.v:187547.18-187547.124" + wire $or$libresoc.v:187547$12495_Y + attribute \src "libresoc.v:187549.18-187549.155" + wire width 3 $or$libresoc.v:187549$12497_Y + attribute \src "libresoc.v:187550.18-187550.181" + wire width 5 $or$libresoc.v:187550$12498_Y + attribute \src "libresoc.v:187553.18-187553.120" + wire width 3 $or$libresoc.v:187553$12501_Y + attribute \src "libresoc.v:187559.17-187559.117" + wire width 5 $or$libresoc.v:187559$12507_Y + attribute \src "libresoc.v:187565.17-187565.104" + wire $reduce_and$libresoc.v:187565$12513_Y + attribute \src "libresoc.v:187530.18-187530.106" + wire $reduce_or$libresoc.v:187530$12478_Y + attribute \src "libresoc.v:187534.18-187534.113" + wire $reduce_or$libresoc.v:187534$12482_Y + attribute \src "libresoc.v:187535.18-187535.112" + wire $reduce_or$libresoc.v:187535$12483_Y + attribute \src "libresoc.v:187557.18-187557.165" + wire $ternary$libresoc.v:187557$12505_Y + attribute \src "libresoc.v:187558.18-187558.182" + wire width 64 $ternary$libresoc.v:187558$12506_Y + attribute \src "libresoc.v:187560.18-187560.118" + wire width 64 $ternary$libresoc.v:187560$12508_Y + attribute \src "libresoc.v:187561.18-187561.115" + wire width 64 $ternary$libresoc.v:187561$12509_Y + attribute \src "libresoc.v:187562.18-187562.118" + wire width 64 $ternary$libresoc.v:187562$12510_Y + attribute \src "libresoc.v:187563.18-187563.118" + wire $ternary$libresoc.v:187563$12511_Y + attribute \src "libresoc.v:187564.18-187564.118" + wire width 2 $ternary$libresoc.v:187564$12512_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -384631,9 +388640,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -384689,7 +388698,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:184574.7-184574.15" + attribute \src "libresoc.v:186878.7-186878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -384922,7 +388931,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185209$12277 + cell $and $and$libresoc.v:187513$12461 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384930,10 +388939,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:185209$12277_Y + connect \Y $and$libresoc.v:187513$12461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185210$12278 + cell $and $and$libresoc.v:187514$12462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384941,10 +388950,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185210$12278_Y + connect \Y $and$libresoc.v:187514$12462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185211$12279 + cell $and $and$libresoc.v:187515$12463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384952,10 +388961,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185211$12279_Y + connect \Y $and$libresoc.v:187515$12463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:185212$12280 + cell $and $and$libresoc.v:187516$12464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384963,10 +388972,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:185212$12280_Y + connect \Y $and$libresoc.v:187516$12464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:185213$12281 + cell $and $and$libresoc.v:187517$12465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384974,10 +388983,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:185213$12281_Y + connect \Y $and$libresoc.v:187517$12465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:185214$12282 + cell $and $and$libresoc.v:187518$12466 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384985,10 +388994,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:185214$12282_Y + connect \Y $and$libresoc.v:187518$12466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:185215$12283 + cell $and $and$libresoc.v:187519$12467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384996,10 +389005,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185215$12283_Y + connect \Y $and$libresoc.v:187519$12467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185216$12284 + cell $and $and$libresoc.v:187520$12468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385007,10 +389016,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185216$12284_Y + connect \Y $and$libresoc.v:187520$12468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185217$12285 + cell $and $and$libresoc.v:187521$12469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385018,10 +389027,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185217$12285_Y + connect \Y $and$libresoc.v:187521$12469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:185218$12286 + cell $and $and$libresoc.v:187522$12470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385029,10 +389038,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:185218$12286_Y + connect \Y $and$libresoc.v:187522$12470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:185220$12288 + cell $and $and$libresoc.v:187524$12472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385040,10 +389049,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:185220$12288_Y + connect \Y $and$libresoc.v:187524$12472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:185222$12290 + cell $and $and$libresoc.v:187526$12474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385051,10 +389060,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:185222$12290_Y + connect \Y $and$libresoc.v:187526$12474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:185223$12291 + cell $and $and$libresoc.v:187527$12475 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385062,10 +389071,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:185223$12291_Y + connect \Y $and$libresoc.v:187527$12475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:185225$12293 + cell $and $and$libresoc.v:187529$12477 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385073,10 +389082,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:185225$12293_Y + connect \Y $and$libresoc.v:187529$12477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:185228$12296 + cell $and $and$libresoc.v:187532$12480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385084,10 +389093,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:185228$12296_Y + connect \Y $and$libresoc.v:187532$12480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:185229$12297 + cell $and $and$libresoc.v:187533$12481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385095,10 +389104,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:185229$12297_Y + connect \Y $and$libresoc.v:187533$12481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:185234$12302 + cell $and $and$libresoc.v:187538$12486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385106,10 +389115,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:185234$12302_Y + connect \Y $and$libresoc.v:187538$12486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:185235$12303 + cell $and $and$libresoc.v:187539$12487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385117,10 +389126,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185235$12303_Y + connect \Y $and$libresoc.v:187539$12487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:185237$12305 + cell $and $and$libresoc.v:187541$12489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385128,10 +389137,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:185237$12305_Y + connect \Y $and$libresoc.v:187541$12489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185239$12307 + cell $and $and$libresoc.v:187543$12491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385139,10 +389148,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:185239$12307_Y + connect \Y $and$libresoc.v:187543$12491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185240$12308 + cell $and $and$libresoc.v:187544$12492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385150,10 +389159,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:185240$12308_Y + connect \Y $and$libresoc.v:187544$12492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:185241$12309 + cell $and $and$libresoc.v:187545$12493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385161,10 +389170,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:185241$12309_Y + connect \Y $and$libresoc.v:187545$12493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:185247$12315 + cell $and $and$libresoc.v:187551$12499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385172,10 +389181,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:185247$12315_Y + connect \Y $and$libresoc.v:187551$12499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:185248$12316 + cell $and $and$libresoc.v:187552$12500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385183,10 +389192,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:185248$12316_Y + connect \Y $and$libresoc.v:187552$12500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185250$12318 + cell $and $and$libresoc.v:187554$12502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385194,10 +389203,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185250$12318_Y + connect \Y $and$libresoc.v:187554$12502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185251$12319 + cell $and $and$libresoc.v:187555$12503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385205,10 +389214,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185251$12319_Y + connect \Y $and$libresoc.v:187555$12503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:185252$12320 + cell $and $and$libresoc.v:187556$12504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385216,10 +389225,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:185252$12320_Y + connect \Y $and$libresoc.v:187556$12504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:185262$12330 + cell $and $and$libresoc.v:187566$12514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385227,10 +389236,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:185262$12330_Y + connect \Y $and$libresoc.v:187566$12514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:185263$12331 + cell $and $and$libresoc.v:187567$12515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385238,10 +389247,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:185263$12331_Y + connect \Y $and$libresoc.v:187567$12515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185264$12332 + cell $and $and$libresoc.v:187568$12516 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385249,10 +389258,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:185264$12332_Y + connect \Y $and$libresoc.v:187568$12516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:185266$12334 + cell $and $and$libresoc.v:187570$12518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385260,10 +389269,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:185266$12334_Y + connect \Y $and$libresoc.v:187570$12518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:185236$12304 + cell $eq $eq$libresoc.v:187540$12488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385271,10 +389280,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:185236$12304_Y + connect \Y $eq$libresoc.v:187540$12488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:185238$12306 + cell $eq $eq$libresoc.v:187542$12490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385282,74 +389291,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:185238$12306_Y + connect \Y $eq$libresoc.v:187542$12490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:185208$12276 + cell $not $not$libresoc.v:187512$12460 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:185208$12276_Y + connect \Y $not$libresoc.v:187512$12460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:185219$12287 + cell $not $not$libresoc.v:187523$12471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:185219$12287_Y + connect \Y $not$libresoc.v:187523$12471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:185221$12289 + cell $not $not$libresoc.v:187525$12473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:185221$12289_Y + connect \Y $not$libresoc.v:187525$12473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:185224$12292 + cell $not $not$libresoc.v:187528$12476 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:185224$12292_Y + connect \Y $not$libresoc.v:187528$12476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:185227$12295 + cell $not $not$libresoc.v:187531$12479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:185227$12295_Y + connect \Y $not$libresoc.v:187531$12479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:185233$12301 + cell $not $not$libresoc.v:187537$12485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:185233$12301_Y + connect \Y $not$libresoc.v:187537$12485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:185244$12312 + cell $not $not$libresoc.v:187548$12496 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:185244$12312_Y + connect \Y $not$libresoc.v:187548$12496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:185265$12333 + cell $not $not$libresoc.v:187569$12517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:185265$12333_Y + connect \Y $not$libresoc.v:187569$12517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:185232$12300 + cell $or $or$libresoc.v:187536$12484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385357,10 +389366,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:185232$12300_Y + connect \Y $or$libresoc.v:187536$12484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:185242$12310 + cell $or $or$libresoc.v:187546$12494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385368,10 +389377,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:185242$12310_Y + connect \Y $or$libresoc.v:187546$12494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:185243$12311 + cell $or $or$libresoc.v:187547$12495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385379,10 +389388,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:185243$12311_Y + connect \Y $or$libresoc.v:187547$12495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:185245$12313 + cell $or $or$libresoc.v:187549$12497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385390,10 +389399,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:185245$12313_Y + connect \Y $or$libresoc.v:187549$12497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:185246$12314 + cell $or $or$libresoc.v:187550$12498 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385401,10 +389410,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:185246$12314_Y + connect \Y $or$libresoc.v:187550$12498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:185249$12317 + cell $or $or$libresoc.v:187553$12501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385412,10 +389421,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:185249$12317_Y + connect \Y $or$libresoc.v:187553$12501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:185255$12323 + cell $or $or$libresoc.v:187559$12507 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385423,98 +389432,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:185255$12323_Y + connect \Y $or$libresoc.v:187559$12507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:185261$12329 + cell $reduce_and $reduce_and$libresoc.v:187565$12513 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:185261$12329_Y + connect \Y $reduce_and$libresoc.v:187565$12513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:185226$12294 + cell $reduce_or $reduce_or$libresoc.v:187530$12478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:185226$12294_Y + connect \Y $reduce_or$libresoc.v:187530$12478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:185230$12298 + cell $reduce_or $reduce_or$libresoc.v:187534$12482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:185230$12298_Y + connect \Y $reduce_or$libresoc.v:187534$12482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:185231$12299 + cell $reduce_or $reduce_or$libresoc.v:187535$12483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:185231$12299_Y + connect \Y $reduce_or$libresoc.v:187535$12483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:185253$12321 + cell $mux $ternary$libresoc.v:187557$12505 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:185253$12321_Y + connect \Y $ternary$libresoc.v:187557$12505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:185254$12322 + cell $mux $ternary$libresoc.v:187558$12506 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:185254$12322_Y + connect \Y $ternary$libresoc.v:187558$12506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185256$12324 + cell $mux $ternary$libresoc.v:187560$12508 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:185256$12324_Y + connect \Y $ternary$libresoc.v:187560$12508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185257$12325 + cell $mux $ternary$libresoc.v:187561$12509 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:185257$12325_Y + connect \Y $ternary$libresoc.v:187561$12509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185258$12326 + cell $mux $ternary$libresoc.v:187562$12510 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:185258$12326_Y + connect \Y $ternary$libresoc.v:187562$12510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185259$12327 + cell $mux $ternary$libresoc.v:187563$12511 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:185259$12327_Y + connect \Y $ternary$libresoc.v:187563$12511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:185260$12328 + cell $mux $ternary$libresoc.v:187564$12512 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:185260$12328_Y + connect \Y $ternary$libresoc.v:187564$12512_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185353.15-185359.4" + attribute \src "libresoc.v:187657.15-187663.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385523,7 +389532,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:185360.18-185395.4" + attribute \src "libresoc.v:187664.18-187699.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385561,7 +389570,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:185396.16-185402.4" + attribute \src "libresoc.v:187700.16-187706.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385570,7 +389579,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:185403.15-185409.4" + attribute \src "libresoc.v:187707.15-187713.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385579,7 +389588,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:185410.15-185416.4" + attribute \src "libresoc.v:187714.15-187720.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385588,7 +389597,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:185417.15-185423.4" + attribute \src "libresoc.v:187721.15-187727.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385597,7 +389606,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:185424.15-185429.4" + attribute \src "libresoc.v:187728.15-187733.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385605,7 +389614,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:185430.15-185436.4" + attribute \src "libresoc.v:187734.15-187740.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -385613,667 +389622,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:184574.7-184574.20" - process $proc$libresoc.v:184574$12501 + attribute \src "libresoc.v:186878.7-186878.20" + process $proc$libresoc.v:186878$12685 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184696.7-184696.24" - process $proc$libresoc.v:184696$12502 + attribute \src "libresoc.v:187000.7-187000.24" + process $proc$libresoc.v:187000$12686 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:184706.7-184706.26" - process $proc$libresoc.v:184706$12503 + attribute \src "libresoc.v:187010.7-187010.26" + process $proc$libresoc.v:187010$12687 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:184714.7-184714.25" - process $proc$libresoc.v:184714$12504 + attribute \src "libresoc.v:187018.7-187018.25" + process $proc$libresoc.v:187018$12688 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:184757.14-184757.54" - process $proc$libresoc.v:184757$12505 + attribute \src "libresoc.v:187061.14-187061.54" + process $proc$libresoc.v:187061$12689 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:184761.14-184761.73" - process $proc$libresoc.v:184761$12506 + attribute \src "libresoc.v:187065.14-187065.73" + process $proc$libresoc.v:187065$12690 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:184765.7-184765.48" - process $proc$libresoc.v:184765$12507 + attribute \src "libresoc.v:187069.7-187069.48" + process $proc$libresoc.v:187069$12691 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:184773.13-184773.53" - process $proc$libresoc.v:184773$12508 + attribute \src "libresoc.v:187077.13-187077.53" + process $proc$libresoc.v:187077$12692 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:184777.7-184777.44" - process $proc$libresoc.v:184777$12509 + attribute \src "libresoc.v:187081.7-187081.44" + process $proc$libresoc.v:187081$12693 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:184781.14-184781.48" - process $proc$libresoc.v:184781$12510 + attribute \src "libresoc.v:187085.14-187085.48" + process $proc$libresoc.v:187085$12694 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:184860.13-184860.52" - process $proc$libresoc.v:184860$12511 + attribute \src "libresoc.v:187164.13-187164.52" + process $proc$libresoc.v:187164$12695 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:184864.7-184864.45" - process $proc$libresoc.v:184864$12512 + attribute \src "libresoc.v:187168.7-187168.45" + process $proc$libresoc.v:187168$12696 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:184868.7-184868.44" - process $proc$libresoc.v:184868$12513 + attribute \src "libresoc.v:187172.7-187172.44" + process $proc$libresoc.v:187172$12697 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:184872.7-184872.45" - process $proc$libresoc.v:184872$12514 + attribute \src "libresoc.v:187176.7-187176.45" + process $proc$libresoc.v:187176$12698 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:184876.7-184876.42" - process $proc$libresoc.v:184876$12515 + attribute \src "libresoc.v:187180.7-187180.42" + process $proc$libresoc.v:187180$12699 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:184880.7-184880.42" - process $proc$libresoc.v:184880$12516 + attribute \src "libresoc.v:187184.7-187184.42" + process $proc$libresoc.v:187184$12700 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:184884.7-184884.48" - process $proc$libresoc.v:184884$12517 + attribute \src "libresoc.v:187188.7-187188.48" + process $proc$libresoc.v:187188$12701 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:184888.7-184888.45" - process $proc$libresoc.v:184888$12518 + attribute \src "libresoc.v:187192.7-187192.45" + process $proc$libresoc.v:187192$12702 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:184892.7-184892.42" - process $proc$libresoc.v:184892$12519 + attribute \src "libresoc.v:187196.7-187196.42" + process $proc$libresoc.v:187196$12703 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:184896.7-184896.42" - process $proc$libresoc.v:184896$12520 + attribute \src "libresoc.v:187200.7-187200.42" + process $proc$libresoc.v:187200$12704 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:184900.7-184900.45" - process $proc$libresoc.v:184900$12521 + attribute \src "libresoc.v:187204.7-187204.45" + process $proc$libresoc.v:187204$12705 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:184912.7-184912.27" - process $proc$libresoc.v:184912$12522 + attribute \src "libresoc.v:187216.7-187216.27" + process $proc$libresoc.v:187216$12706 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:184946.14-184946.47" - process $proc$libresoc.v:184946$12523 + attribute \src "libresoc.v:187250.14-187250.47" + process $proc$libresoc.v:187250$12707 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:184950.7-184950.27" - process $proc$libresoc.v:184950$12524 + attribute \src "libresoc.v:187254.7-187254.27" + process $proc$libresoc.v:187254$12708 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:184954.13-184954.33" - process $proc$libresoc.v:184954$12525 + attribute \src "libresoc.v:187258.13-187258.33" + process $proc$libresoc.v:187258$12709 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:184958.7-184958.30" - process $proc$libresoc.v:184958$12526 + attribute \src "libresoc.v:187262.7-187262.30" + process $proc$libresoc.v:187262$12710 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:184962.13-184962.35" - process $proc$libresoc.v:184962$12527 + attribute \src "libresoc.v:187266.13-187266.35" + process $proc$libresoc.v:187266$12711 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:184966.7-184966.32" - process $proc$libresoc.v:184966$12528 + attribute \src "libresoc.v:187270.7-187270.32" + process $proc$libresoc.v:187270$12712 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:184983.7-184983.25" - process $proc$libresoc.v:184983$12529 + attribute \src "libresoc.v:187287.7-187287.25" + process $proc$libresoc.v:187287$12713 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:184987.7-184987.25" - process $proc$libresoc.v:184987$12530 + attribute \src "libresoc.v:187291.7-187291.25" + process $proc$libresoc.v:187291$12714 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:185119.13-185119.30" - process $proc$libresoc.v:185119$12531 + attribute \src "libresoc.v:187423.13-187423.30" + process $proc$libresoc.v:187423$12715 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:185127.13-185127.31" - process $proc$libresoc.v:185127$12532 + attribute \src "libresoc.v:187431.13-187431.31" + process $proc$libresoc.v:187431$12716 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:185131.13-185131.31" - process $proc$libresoc.v:185131$12533 + attribute \src "libresoc.v:187435.13-187435.31" + process $proc$libresoc.v:187435$12717 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:185143.7-185143.26" - process $proc$libresoc.v:185143$12534 + attribute \src "libresoc.v:187447.7-187447.26" + process $proc$libresoc.v:187447$12718 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:185147.7-185147.26" - process $proc$libresoc.v:185147$12535 + attribute \src "libresoc.v:187451.7-187451.26" + process $proc$libresoc.v:187451$12719 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:185151.7-185151.25" - process $proc$libresoc.v:185151$12536 + attribute \src "libresoc.v:187455.7-187455.25" + process $proc$libresoc.v:187455$12720 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:185155.7-185155.25" - process $proc$libresoc.v:185155$12537 + attribute \src "libresoc.v:187459.7-187459.25" + process $proc$libresoc.v:187459$12721 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:185173.13-185173.32" - process $proc$libresoc.v:185173$12538 + attribute \src "libresoc.v:187477.13-187477.32" + process $proc$libresoc.v:187477$12722 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:185177.13-185177.32" - process $proc$libresoc.v:185177$12539 + attribute \src "libresoc.v:187481.13-187481.32" + process $proc$libresoc.v:187481$12723 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:185183.14-185183.43" - process $proc$libresoc.v:185183$12540 + attribute \src "libresoc.v:187487.14-187487.43" + process $proc$libresoc.v:187487$12724 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:185187.14-185187.43" - process $proc$libresoc.v:185187$12541 + attribute \src "libresoc.v:187491.14-187491.43" + process $proc$libresoc.v:187491$12725 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:185191.14-185191.43" - process $proc$libresoc.v:185191$12542 + attribute \src "libresoc.v:187495.14-187495.43" + process $proc$libresoc.v:187495$12726 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:185195.7-185195.20" - process $proc$libresoc.v:185195$12543 + attribute \src "libresoc.v:187499.7-187499.20" + process $proc$libresoc.v:187499$12727 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:185199.13-185199.26" - process $proc$libresoc.v:185199$12544 + attribute \src "libresoc.v:187503.13-187503.26" + process $proc$libresoc.v:187503$12728 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:185267.3-185268.39" - process $proc$libresoc.v:185267$12335 + attribute \src "libresoc.v:187571.3-187572.39" + process $proc$libresoc.v:187571$12519 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:185269.3-185270.43" - process $proc$libresoc.v:185269$12336 + attribute \src "libresoc.v:187573.3-187574.43" + process $proc$libresoc.v:187573$12520 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:185271.3-185272.29" - process $proc$libresoc.v:185271$12337 + attribute \src "libresoc.v:187575.3-187576.29" + process $proc$libresoc.v:187575$12521 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:185273.3-185274.29" - process $proc$libresoc.v:185273$12338 + attribute \src "libresoc.v:187577.3-187578.29" + process $proc$libresoc.v:187577$12522 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:185275.3-185276.29" - process $proc$libresoc.v:185275$12339 + attribute \src "libresoc.v:187579.3-187580.29" + process $proc$libresoc.v:187579$12523 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:185277.3-185278.29" - process $proc$libresoc.v:185277$12340 + attribute \src "libresoc.v:187581.3-187582.29" + process $proc$libresoc.v:187581$12524 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:185279.3-185280.29" - process $proc$libresoc.v:185279$12341 + attribute \src "libresoc.v:187583.3-187584.29" + process $proc$libresoc.v:187583$12525 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:185281.3-185282.47" - process $proc$libresoc.v:185281$12342 + attribute \src "libresoc.v:187585.3-187586.47" + process $proc$libresoc.v:187585$12526 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:185283.3-185284.53" - process $proc$libresoc.v:185283$12343 + attribute \src "libresoc.v:187587.3-187588.53" + process $proc$libresoc.v:187587$12527 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:185285.3-185286.43" - process $proc$libresoc.v:185285$12344 + attribute \src "libresoc.v:187589.3-187590.43" + process $proc$libresoc.v:187589$12528 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:185287.3-185288.49" - process $proc$libresoc.v:185287$12345 + attribute \src "libresoc.v:187591.3-187592.49" + process $proc$libresoc.v:187591$12529 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:185289.3-185290.37" - process $proc$libresoc.v:185289$12346 + attribute \src "libresoc.v:187593.3-187594.37" + process $proc$libresoc.v:187593$12530 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:185291.3-185292.43" - process $proc$libresoc.v:185291$12347 + attribute \src "libresoc.v:187595.3-187596.43" + process $proc$libresoc.v:187595$12531 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:185293.3-185294.79" - process $proc$libresoc.v:185293$12348 + attribute \src "libresoc.v:187597.3-187598.79" + process $proc$libresoc.v:187597$12532 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:185295.3-185296.75" - process $proc$libresoc.v:185295$12349 + attribute \src "libresoc.v:187599.3-187600.75" + process $proc$libresoc.v:187599$12533 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:185297.3-185298.89" - process $proc$libresoc.v:185297$12350 + attribute \src "libresoc.v:187601.3-187602.89" + process $proc$libresoc.v:187601$12534 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:185299.3-185300.85" - process $proc$libresoc.v:185299$12351 + attribute \src "libresoc.v:187603.3-187604.85" + process $proc$libresoc.v:187603$12535 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:185301.3-185302.73" - process $proc$libresoc.v:185301$12352 + attribute \src "libresoc.v:187605.3-187606.73" + process $proc$libresoc.v:187605$12536 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:185303.3-185304.73" - process $proc$libresoc.v:185303$12353 + attribute \src "libresoc.v:187607.3-187608.73" + process $proc$libresoc.v:187607$12537 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:185305.3-185306.73" - process $proc$libresoc.v:185305$12354 + attribute \src "libresoc.v:187609.3-187610.73" + process $proc$libresoc.v:187609$12538 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:185307.3-185308.73" - process $proc$libresoc.v:185307$12355 + attribute \src "libresoc.v:187611.3-187612.73" + process $proc$libresoc.v:187611$12539 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:185309.3-185310.79" - process $proc$libresoc.v:185309$12356 + attribute \src "libresoc.v:187613.3-187614.79" + process $proc$libresoc.v:187613$12540 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:185311.3-185312.79" - process $proc$libresoc.v:185311$12357 + attribute \src "libresoc.v:187615.3-187616.79" + process $proc$libresoc.v:187615$12541 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:185313.3-185314.83" - process $proc$libresoc.v:185313$12358 + attribute \src "libresoc.v:187617.3-187618.83" + process $proc$libresoc.v:187617$12542 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:185315.3-185316.85" - process $proc$libresoc.v:185315$12359 + attribute \src "libresoc.v:187619.3-187620.85" + process $proc$libresoc.v:187619$12543 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:185317.3-185318.77" - process $proc$libresoc.v:185317$12360 + attribute \src "libresoc.v:187621.3-187622.77" + process $proc$libresoc.v:187621$12544 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:185319.3-185320.79" - process $proc$libresoc.v:185319$12361 + attribute \src "libresoc.v:187623.3-187624.79" + process $proc$libresoc.v:187623$12545 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:185321.3-185322.77" - process $proc$libresoc.v:185321$12362 + attribute \src "libresoc.v:187625.3-187626.77" + process $proc$libresoc.v:187625$12546 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:185323.3-185324.79" - process $proc$libresoc.v:185323$12363 + attribute \src "libresoc.v:187627.3-187628.79" + process $proc$libresoc.v:187627$12547 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:185325.3-185326.69" - process $proc$libresoc.v:185325$12364 + attribute \src "libresoc.v:187629.3-187630.69" + process $proc$libresoc.v:187629$12548 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:185327.3-185328.39" - process $proc$libresoc.v:185327$12365 + attribute \src "libresoc.v:187631.3-187632.39" + process $proc$libresoc.v:187631$12549 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:185329.3-185330.39" - process $proc$libresoc.v:185329$12366 + attribute \src "libresoc.v:187633.3-187634.39" + process $proc$libresoc.v:187633$12550 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:185331.3-185332.39" - process $proc$libresoc.v:185331$12367 + attribute \src "libresoc.v:187635.3-187636.39" + process $proc$libresoc.v:187635$12551 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:185333.3-185334.39" - process $proc$libresoc.v:185333$12368 + attribute \src "libresoc.v:187637.3-187638.39" + process $proc$libresoc.v:187637$12552 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:185335.3-185336.39" - process $proc$libresoc.v:185335$12369 + attribute \src "libresoc.v:187639.3-187640.39" + process $proc$libresoc.v:187639$12553 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:185337.3-185338.39" - process $proc$libresoc.v:185337$12370 + attribute \src "libresoc.v:187641.3-187642.39" + process $proc$libresoc.v:187641$12554 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:185339.3-185340.39" - process $proc$libresoc.v:185339$12371 + attribute \src "libresoc.v:187643.3-187644.39" + process $proc$libresoc.v:187643$12555 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:185341.3-185342.39" - process $proc$libresoc.v:185341$12372 + attribute \src "libresoc.v:187645.3-187646.39" + process $proc$libresoc.v:187645$12556 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:185343.3-185344.41" - process $proc$libresoc.v:185343$12373 + attribute \src "libresoc.v:187647.3-187648.41" + process $proc$libresoc.v:187647$12557 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:185345.3-185346.41" - process $proc$libresoc.v:185345$12374 + attribute \src "libresoc.v:187649.3-187650.41" + process $proc$libresoc.v:187649$12558 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:185347.3-185348.37" - process $proc$libresoc.v:185347$12375 + attribute \src "libresoc.v:187651.3-187652.37" + process $proc$libresoc.v:187651$12559 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:185349.3-185350.46" - process $proc$libresoc.v:185349$12376 + attribute \src "libresoc.v:187653.3-187654.46" + process $proc$libresoc.v:187653$12560 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:185351.3-185352.25" - process $proc$libresoc.v:185351$12377 + attribute \src "libresoc.v:187655.3-187656.25" + process $proc$libresoc.v:187655$12561 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:185437.3-185446.6" - process $proc$libresoc.v:185437$12378 + attribute \src "libresoc.v:187741.3-187750.6" + process $proc$libresoc.v:187741$12562 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:185438.5-185438.29" + attribute \src "libresoc.v:187742.5-187742.29" switch \initial - attribute \src "libresoc.v:185438.9-185438.17" + attribute \src "libresoc.v:187742.9-187742.17" case 1'1 case end @@ -386289,14 +390298,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:185447.3-185455.6" - process $proc$libresoc.v:185447$12379 + attribute \src "libresoc.v:187751.3-187759.6" + process $proc$libresoc.v:187751$12563 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12380 $1\rok_l_s_rdok$next[0:0]$12381 - attribute \src "libresoc.v:185448.5-185448.29" + assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 + attribute \src "libresoc.v:187752.5-187752.29" switch \initial - attribute \src "libresoc.v:185448.9-185448.17" + attribute \src "libresoc.v:187752.9-187752.17" case 1'1 case end @@ -386305,21 +390314,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12381 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12565 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12381 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12565 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12380 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 end - attribute \src "libresoc.v:185456.3-185464.6" - process $proc$libresoc.v:185456$12382 + attribute \src "libresoc.v:187760.3-187768.6" + process $proc$libresoc.v:187760$12566 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12383 $1\rok_l_r_rdok$next[0:0]$12384 - attribute \src "libresoc.v:185457.5-185457.29" + assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 + attribute \src "libresoc.v:187761.5-187761.29" switch \initial - attribute \src "libresoc.v:185457.9-185457.17" + attribute \src "libresoc.v:187761.9-187761.17" case 1'1 case end @@ -386328,21 +390337,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12384 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12568 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12384 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12568 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12383 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 end - attribute \src "libresoc.v:185465.3-185473.6" - process $proc$libresoc.v:185465$12385 + attribute \src "libresoc.v:187769.3-187777.6" + process $proc$libresoc.v:187769$12569 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12386 $1\rst_l_s_rst$next[0:0]$12387 - attribute \src "libresoc.v:185466.5-185466.29" + assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 + attribute \src "libresoc.v:187770.5-187770.29" switch \initial - attribute \src "libresoc.v:185466.9-185466.17" + attribute \src "libresoc.v:187770.9-187770.17" case 1'1 case end @@ -386351,21 +390360,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12387 1'0 + assign $1\rst_l_s_rst$next[0:0]$12571 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12387 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12571 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12386 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 end - attribute \src "libresoc.v:185474.3-185482.6" - process $proc$libresoc.v:185474$12388 + attribute \src "libresoc.v:187778.3-187786.6" + process $proc$libresoc.v:187778$12572 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12389 $1\rst_l_r_rst$next[0:0]$12390 - attribute \src "libresoc.v:185475.5-185475.29" + assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 + attribute \src "libresoc.v:187779.5-187779.29" switch \initial - attribute \src "libresoc.v:185475.9-185475.17" + attribute \src "libresoc.v:187779.9-187779.17" case 1'1 case end @@ -386374,21 +390383,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12390 1'1 + assign $1\rst_l_r_rst$next[0:0]$12574 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12390 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12574 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12389 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 end - attribute \src "libresoc.v:185483.3-185491.6" - process $proc$libresoc.v:185483$12391 + attribute \src "libresoc.v:187787.3-187795.6" + process $proc$libresoc.v:187787$12575 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12392 $1\opc_l_s_opc$next[0:0]$12393 - attribute \src "libresoc.v:185484.5-185484.29" + assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 + attribute \src "libresoc.v:187788.5-187788.29" switch \initial - attribute \src "libresoc.v:185484.9-185484.17" + attribute \src "libresoc.v:187788.9-187788.17" case 1'1 case end @@ -386397,21 +390406,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12393 1'0 + assign $1\opc_l_s_opc$next[0:0]$12577 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12393 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12577 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12392 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 end - attribute \src "libresoc.v:185492.3-185500.6" - process $proc$libresoc.v:185492$12394 + attribute \src "libresoc.v:187796.3-187804.6" + process $proc$libresoc.v:187796$12578 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12395 $1\opc_l_r_opc$next[0:0]$12396 - attribute \src "libresoc.v:185493.5-185493.29" + assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 + attribute \src "libresoc.v:187797.5-187797.29" switch \initial - attribute \src "libresoc.v:185493.9-185493.17" + attribute \src "libresoc.v:187797.9-187797.17" case 1'1 case end @@ -386420,21 +390429,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12396 1'1 + assign $1\opc_l_r_opc$next[0:0]$12580 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12396 \req_done + assign $1\opc_l_r_opc$next[0:0]$12580 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12395 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 end - attribute \src "libresoc.v:185501.3-185509.6" - process $proc$libresoc.v:185501$12397 + attribute \src "libresoc.v:187805.3-187813.6" + process $proc$libresoc.v:187805$12581 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12398 $1\src_l_s_src$next[4:0]$12399 - attribute \src "libresoc.v:185502.5-185502.29" + assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 + attribute \src "libresoc.v:187806.5-187806.29" switch \initial - attribute \src "libresoc.v:185502.9-185502.17" + attribute \src "libresoc.v:187806.9-187806.17" case 1'1 case end @@ -386443,21 +390452,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12399 5'00000 + assign $1\src_l_s_src$next[4:0]$12583 5'00000 case - assign $1\src_l_s_src$next[4:0]$12399 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12583 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12398 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 end - attribute \src "libresoc.v:185510.3-185518.6" - process $proc$libresoc.v:185510$12400 + attribute \src "libresoc.v:187814.3-187822.6" + process $proc$libresoc.v:187814$12584 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12401 $1\src_l_r_src$next[4:0]$12402 - attribute \src "libresoc.v:185511.5-185511.29" + assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 + attribute \src "libresoc.v:187815.5-187815.29" switch \initial - attribute \src "libresoc.v:185511.9-185511.17" + attribute \src "libresoc.v:187815.9-187815.17" case 1'1 case end @@ -386466,21 +390475,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12402 5'11111 + assign $1\src_l_r_src$next[4:0]$12586 5'11111 case - assign $1\src_l_r_src$next[4:0]$12402 \reset_r + assign $1\src_l_r_src$next[4:0]$12586 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12401 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 end - attribute \src "libresoc.v:185519.3-185527.6" - process $proc$libresoc.v:185519$12403 + attribute \src "libresoc.v:187823.3-187831.6" + process $proc$libresoc.v:187823$12587 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12404 $1\req_l_s_req$next[2:0]$12405 - attribute \src "libresoc.v:185520.5-185520.29" + assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 + attribute \src "libresoc.v:187824.5-187824.29" switch \initial - attribute \src "libresoc.v:185520.9-185520.17" + attribute \src "libresoc.v:187824.9-187824.17" case 1'1 case end @@ -386489,21 +390498,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12405 3'000 + assign $1\req_l_s_req$next[2:0]$12589 3'000 case - assign $1\req_l_s_req$next[2:0]$12405 \$66 + assign $1\req_l_s_req$next[2:0]$12589 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12404 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 end - attribute \src "libresoc.v:185528.3-185536.6" - process $proc$libresoc.v:185528$12406 + attribute \src "libresoc.v:187832.3-187840.6" + process $proc$libresoc.v:187832$12590 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12407 $1\req_l_r_req$next[2:0]$12408 - attribute \src "libresoc.v:185529.5-185529.29" + assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 + attribute \src "libresoc.v:187833.5-187833.29" switch \initial - attribute \src "libresoc.v:185529.9-185529.17" + attribute \src "libresoc.v:187833.9-187833.17" case 1'1 case end @@ -386512,15 +390521,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12408 3'111 + assign $1\req_l_r_req$next[2:0]$12592 3'111 case - assign $1\req_l_r_req$next[2:0]$12408 \$68 + assign $1\req_l_r_req$next[2:0]$12592 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12407 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 end - attribute \src "libresoc.v:185537.3-185574.6" - process $proc$libresoc.v:185537$12409 + attribute \src "libresoc.v:187841.3-187878.6" + process $proc$libresoc.v:187841$12593 assign { } { } assign { } { } assign { } { } @@ -386555,32 +390564,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 - attribute \src "libresoc.v:185538.5-185538.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 + attribute \src "libresoc.v:187842.5-187842.29" switch \initial - attribute \src "libresoc.v:185538.9-185538.17" + attribute \src "libresoc.v:187842.9-187842.17" case 1'1 case end @@ -386605,25 +390614,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12427 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12430 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12431 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12432 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12433 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12434 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12435 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12436 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12439 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12440 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12443 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -386635,53 +390644,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12444 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12428 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12445 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12429 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12446 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12437 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12447 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12438 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12448 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12441 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12449 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12442 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12410 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12411 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12412 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12413 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12414 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12415 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12416 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12417 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12418 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12419 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12422 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12423 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12424 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12425 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12426 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 end - attribute \src "libresoc.v:185575.3-185596.6" - process $proc$libresoc.v:185575$12450 + attribute \src "libresoc.v:187879.3-187900.6" + process $proc$libresoc.v:187879$12634 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12451 $2\data_r0__o$next[63:0]$12455 + assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12452 $3\data_r0__o_ok$next[0:0]$12457 - attribute \src "libresoc.v:185576.5-185576.29" + assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 + attribute \src "libresoc.v:187880.5-187880.29" switch \initial - attribute \src "libresoc.v:185576.9-185576.17" + attribute \src "libresoc.v:187880.9-187880.17" case 1'1 case end @@ -386691,10 +390700,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12454 $1\data_r0__o$next[63:0]$12453 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12638 $1\data_r0__o$next[63:0]$12637 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12453 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12454 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12637 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12638 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386702,38 +390711,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12456 $2\data_r0__o$next[63:0]$12455 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12640 $2\data_r0__o$next[63:0]$12639 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12455 $1\data_r0__o$next[63:0]$12453 - assign $2\data_r0__o_ok$next[0:0]$12456 $1\data_r0__o_ok$next[0:0]$12454 + assign $2\data_r0__o$next[63:0]$12639 $1\data_r0__o$next[63:0]$12637 + assign $2\data_r0__o_ok$next[0:0]$12640 $1\data_r0__o_ok$next[0:0]$12638 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12457 1'0 + assign $3\data_r0__o_ok$next[0:0]$12641 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12457 $2\data_r0__o_ok$next[0:0]$12456 + assign $3\data_r0__o_ok$next[0:0]$12641 $2\data_r0__o_ok$next[0:0]$12640 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12451 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12452 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 end - attribute \src "libresoc.v:185597.3-185618.6" - process $proc$libresoc.v:185597$12458 + attribute \src "libresoc.v:187901.3-187922.6" + process $proc$libresoc.v:187901$12642 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12459 $2\data_r1__cr_a$next[3:0]$12463 + assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12460 $3\data_r1__cr_a_ok$next[0:0]$12465 - attribute \src "libresoc.v:185598.5-185598.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 + attribute \src "libresoc.v:187902.5-187902.29" switch \initial - attribute \src "libresoc.v:185598.9-185598.17" + attribute \src "libresoc.v:187902.9-187902.17" case 1'1 case end @@ -386743,10 +390752,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12462 $1\data_r1__cr_a$next[3:0]$12461 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12646 $1\data_r1__cr_a$next[3:0]$12645 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12461 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12462 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12645 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12646 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386754,38 +390763,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12464 $2\data_r1__cr_a$next[3:0]$12463 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12648 $2\data_r1__cr_a$next[3:0]$12647 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12463 $1\data_r1__cr_a$next[3:0]$12461 - assign $2\data_r1__cr_a_ok$next[0:0]$12464 $1\data_r1__cr_a_ok$next[0:0]$12462 + assign $2\data_r1__cr_a$next[3:0]$12647 $1\data_r1__cr_a$next[3:0]$12645 + assign $2\data_r1__cr_a_ok$next[0:0]$12648 $1\data_r1__cr_a_ok$next[0:0]$12646 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12465 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12649 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12465 $2\data_r1__cr_a_ok$next[0:0]$12464 + assign $3\data_r1__cr_a_ok$next[0:0]$12649 $2\data_r1__cr_a_ok$next[0:0]$12648 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12459 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12460 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 end - attribute \src "libresoc.v:185619.3-185640.6" - process $proc$libresoc.v:185619$12466 + attribute \src "libresoc.v:187923.3-187944.6" + process $proc$libresoc.v:187923$12650 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12467 $2\data_r2__xer_ca$next[1:0]$12471 + assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12468 $3\data_r2__xer_ca_ok$next[0:0]$12473 - attribute \src "libresoc.v:185620.5-185620.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 + attribute \src "libresoc.v:187924.5-187924.29" switch \initial - attribute \src "libresoc.v:185620.9-185620.17" + attribute \src "libresoc.v:187924.9-187924.17" case 1'1 case end @@ -386795,10 +390804,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12470 $1\data_r2__xer_ca$next[1:0]$12469 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12654 $1\data_r2__xer_ca$next[1:0]$12653 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12469 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12470 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12653 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12654 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -386806,32 +390815,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12472 $2\data_r2__xer_ca$next[1:0]$12471 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12656 $2\data_r2__xer_ca$next[1:0]$12655 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12471 $1\data_r2__xer_ca$next[1:0]$12469 - assign $2\data_r2__xer_ca_ok$next[0:0]$12472 $1\data_r2__xer_ca_ok$next[0:0]$12470 + assign $2\data_r2__xer_ca$next[1:0]$12655 $1\data_r2__xer_ca$next[1:0]$12653 + assign $2\data_r2__xer_ca_ok$next[0:0]$12656 $1\data_r2__xer_ca_ok$next[0:0]$12654 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12473 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12473 $2\data_r2__xer_ca_ok$next[0:0]$12472 + assign $3\data_r2__xer_ca_ok$next[0:0]$12657 $2\data_r2__xer_ca_ok$next[0:0]$12656 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12467 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12468 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 end - attribute \src "libresoc.v:185641.3-185650.6" - process $proc$libresoc.v:185641$12474 + attribute \src "libresoc.v:187945.3-187954.6" + process $proc$libresoc.v:187945$12658 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12475 $1\src_r0$next[63:0]$12476 - attribute \src "libresoc.v:185642.5-185642.29" + assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 + attribute \src "libresoc.v:187946.5-187946.29" switch \initial - attribute \src "libresoc.v:185642.9-185642.17" + attribute \src "libresoc.v:187946.9-187946.17" case 1'1 case end @@ -386840,21 +390849,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12476 \src1_i + assign $1\src_r0$next[63:0]$12660 \src1_i case - assign $1\src_r0$next[63:0]$12476 \src_r0 + assign $1\src_r0$next[63:0]$12660 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12475 + update \src_r0$next $0\src_r0$next[63:0]$12659 end - attribute \src "libresoc.v:185651.3-185660.6" - process $proc$libresoc.v:185651$12477 + attribute \src "libresoc.v:187955.3-187964.6" + process $proc$libresoc.v:187955$12661 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12478 $1\src_r1$next[63:0]$12479 - attribute \src "libresoc.v:185652.5-185652.29" + assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 + attribute \src "libresoc.v:187956.5-187956.29" switch \initial - attribute \src "libresoc.v:185652.9-185652.17" + attribute \src "libresoc.v:187956.9-187956.17" case 1'1 case end @@ -386863,21 +390872,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12479 \src_or_imm + assign $1\src_r1$next[63:0]$12663 \src_or_imm case - assign $1\src_r1$next[63:0]$12479 \src_r1 + assign $1\src_r1$next[63:0]$12663 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12478 + update \src_r1$next $0\src_r1$next[63:0]$12662 end - attribute \src "libresoc.v:185661.3-185670.6" - process $proc$libresoc.v:185661$12480 + attribute \src "libresoc.v:187965.3-187974.6" + process $proc$libresoc.v:187965$12664 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12481 $1\src_r2$next[63:0]$12482 - attribute \src "libresoc.v:185662.5-185662.29" + assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 + attribute \src "libresoc.v:187966.5-187966.29" switch \initial - attribute \src "libresoc.v:185662.9-185662.17" + attribute \src "libresoc.v:187966.9-187966.17" case 1'1 case end @@ -386886,21 +390895,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12482 \src3_i + assign $1\src_r2$next[63:0]$12666 \src3_i case - assign $1\src_r2$next[63:0]$12482 \src_r2 + assign $1\src_r2$next[63:0]$12666 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12481 + update \src_r2$next $0\src_r2$next[63:0]$12665 end - attribute \src "libresoc.v:185671.3-185680.6" - process $proc$libresoc.v:185671$12483 + attribute \src "libresoc.v:187975.3-187984.6" + process $proc$libresoc.v:187975$12667 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12484 $1\src_r3$next[0:0]$12485 - attribute \src "libresoc.v:185672.5-185672.29" + assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 + attribute \src "libresoc.v:187976.5-187976.29" switch \initial - attribute \src "libresoc.v:185672.9-185672.17" + attribute \src "libresoc.v:187976.9-187976.17" case 1'1 case end @@ -386909,21 +390918,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12485 \src4_i + assign $1\src_r3$next[0:0]$12669 \src4_i case - assign $1\src_r3$next[0:0]$12485 \src_r3 + assign $1\src_r3$next[0:0]$12669 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12484 + update \src_r3$next $0\src_r3$next[0:0]$12668 end - attribute \src "libresoc.v:185681.3-185690.6" - process $proc$libresoc.v:185681$12486 + attribute \src "libresoc.v:187985.3-187994.6" + process $proc$libresoc.v:187985$12670 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12487 $1\src_r4$next[1:0]$12488 - attribute \src "libresoc.v:185682.5-185682.29" + assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 + attribute \src "libresoc.v:187986.5-187986.29" switch \initial - attribute \src "libresoc.v:185682.9-185682.17" + attribute \src "libresoc.v:187986.9-187986.17" case 1'1 case end @@ -386932,21 +390941,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12488 \src5_i + assign $1\src_r4$next[1:0]$12672 \src5_i case - assign $1\src_r4$next[1:0]$12488 \src_r4 + assign $1\src_r4$next[1:0]$12672 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12487 + update \src_r4$next $0\src_r4$next[1:0]$12671 end - attribute \src "libresoc.v:185691.3-185699.6" - process $proc$libresoc.v:185691$12489 + attribute \src "libresoc.v:187995.3-188003.6" + process $proc$libresoc.v:187995$12673 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12490 $1\alui_l_r_alui$next[0:0]$12491 - attribute \src "libresoc.v:185692.5-185692.29" + assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 + attribute \src "libresoc.v:187996.5-187996.29" switch \initial - attribute \src "libresoc.v:185692.9-185692.17" + attribute \src "libresoc.v:187996.9-187996.17" case 1'1 case end @@ -386955,21 +390964,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12491 1'1 + assign $1\alui_l_r_alui$next[0:0]$12675 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12491 \$90 + assign $1\alui_l_r_alui$next[0:0]$12675 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12490 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 end - attribute \src "libresoc.v:185700.3-185708.6" - process $proc$libresoc.v:185700$12492 + attribute \src "libresoc.v:188004.3-188012.6" + process $proc$libresoc.v:188004$12676 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12493 $1\alu_l_r_alu$next[0:0]$12494 - attribute \src "libresoc.v:185701.5-185701.29" + assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 + attribute \src "libresoc.v:188005.5-188005.29" switch \initial - attribute \src "libresoc.v:185701.9-185701.17" + attribute \src "libresoc.v:188005.9-188005.17" case 1'1 case end @@ -386978,21 +390987,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12494 1'1 + assign $1\alu_l_r_alu$next[0:0]$12678 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12494 \$92 + assign $1\alu_l_r_alu$next[0:0]$12678 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12493 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 end - attribute \src "libresoc.v:185709.3-185718.6" - process $proc$libresoc.v:185709$12495 + attribute \src "libresoc.v:188013.3-188022.6" + process $proc$libresoc.v:188013$12679 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:185710.5-185710.29" + attribute \src "libresoc.v:188014.5-188014.29" switch \initial - attribute \src "libresoc.v:185710.9-185710.17" + attribute \src "libresoc.v:188014.9-188014.17" case 1'1 case end @@ -387008,14 +391017,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:185719.3-185728.6" - process $proc$libresoc.v:185719$12496 + attribute \src "libresoc.v:188023.3-188032.6" + process $proc$libresoc.v:188023$12680 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:185720.5-185720.29" + attribute \src "libresoc.v:188024.5-188024.29" switch \initial - attribute \src "libresoc.v:185720.9-185720.17" + attribute \src "libresoc.v:188024.9-188024.17" case 1'1 case end @@ -387031,14 +391040,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:185729.3-185738.6" - process $proc$libresoc.v:185729$12497 + attribute \src "libresoc.v:188033.3-188042.6" + process $proc$libresoc.v:188033$12681 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:185730.5-185730.29" + attribute \src "libresoc.v:188034.5-188034.29" switch \initial - attribute \src "libresoc.v:185730.9-185730.17" + attribute \src "libresoc.v:188034.9-188034.17" case 1'1 case end @@ -387054,14 +391063,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:185739.3-185747.6" - process $proc$libresoc.v:185739$12498 + attribute \src "libresoc.v:188043.3-188051.6" + process $proc$libresoc.v:188043$12682 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12499 $1\prev_wr_go$next[2:0]$12500 - attribute \src "libresoc.v:185740.5-185740.29" + assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 + attribute \src "libresoc.v:188044.5-188044.29" switch \initial - attribute \src "libresoc.v:185740.9-185740.17" + attribute \src "libresoc.v:188044.9-188044.17" case 1'1 case end @@ -387070,72 +391079,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12500 3'000 - case - assign $1\prev_wr_go$next[2:0]$12500 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12499 - end - connect \$100 $not$libresoc.v:185208$12276_Y - connect \$102 $and$libresoc.v:185209$12277_Y - connect \$104 $and$libresoc.v:185210$12278_Y - connect \$106 $and$libresoc.v:185211$12279_Y - connect \$108 $and$libresoc.v:185212$12280_Y - connect \$10 $and$libresoc.v:185213$12281_Y - connect \$110 $and$libresoc.v:185214$12282_Y - connect \$112 $and$libresoc.v:185215$12283_Y - connect \$114 $and$libresoc.v:185216$12284_Y - connect \$116 $and$libresoc.v:185217$12285_Y - connect \$118 $and$libresoc.v:185218$12286_Y - connect \$12 $not$libresoc.v:185219$12287_Y - connect \$14 $and$libresoc.v:185220$12288_Y - connect \$16 $not$libresoc.v:185221$12289_Y - connect \$18 $and$libresoc.v:185222$12290_Y - connect \$20 $and$libresoc.v:185223$12291_Y - connect \$24 $not$libresoc.v:185224$12292_Y - connect \$26 $and$libresoc.v:185225$12293_Y - connect \$23 $reduce_or$libresoc.v:185226$12294_Y - connect \$22 $not$libresoc.v:185227$12295_Y - connect \$2 $and$libresoc.v:185228$12296_Y - connect \$30 $and$libresoc.v:185229$12297_Y - connect \$32 $reduce_or$libresoc.v:185230$12298_Y - connect \$34 $reduce_or$libresoc.v:185231$12299_Y - connect \$36 $or$libresoc.v:185232$12300_Y - connect \$38 $not$libresoc.v:185233$12301_Y - connect \$40 $and$libresoc.v:185234$12302_Y - connect \$42 $and$libresoc.v:185235$12303_Y - connect \$44 $eq$libresoc.v:185236$12304_Y - connect \$46 $and$libresoc.v:185237$12305_Y - connect \$48 $eq$libresoc.v:185238$12306_Y - connect \$50 $and$libresoc.v:185239$12307_Y - connect \$52 $and$libresoc.v:185240$12308_Y - connect \$54 $and$libresoc.v:185241$12309_Y - connect \$56 $or$libresoc.v:185242$12310_Y - connect \$58 $or$libresoc.v:185243$12311_Y - connect \$5 $not$libresoc.v:185244$12312_Y - connect \$60 $or$libresoc.v:185245$12313_Y - connect \$62 $or$libresoc.v:185246$12314_Y - connect \$64 $and$libresoc.v:185247$12315_Y - connect \$66 $and$libresoc.v:185248$12316_Y - connect \$68 $or$libresoc.v:185249$12317_Y - connect \$70 $and$libresoc.v:185250$12318_Y - connect \$72 $and$libresoc.v:185251$12319_Y - connect \$74 $and$libresoc.v:185252$12320_Y - connect \$76 $ternary$libresoc.v:185253$12321_Y - connect \$78 $ternary$libresoc.v:185254$12322_Y - connect \$7 $or$libresoc.v:185255$12323_Y - connect \$80 $ternary$libresoc.v:185256$12324_Y - connect \$82 $ternary$libresoc.v:185257$12325_Y - connect \$84 $ternary$libresoc.v:185258$12326_Y - connect \$86 $ternary$libresoc.v:185259$12327_Y - connect \$88 $ternary$libresoc.v:185260$12328_Y - connect \$4 $reduce_and$libresoc.v:185261$12329_Y - connect \$90 $and$libresoc.v:185262$12330_Y - connect \$92 $and$libresoc.v:185263$12331_Y - connect \$94 $and$libresoc.v:185264$12332_Y - connect \$96 $not$libresoc.v:185265$12333_Y - connect \$98 $and$libresoc.v:185266$12334_Y + assign $1\prev_wr_go$next[2:0]$12684 3'000 + case + assign $1\prev_wr_go$next[2:0]$12684 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 + end + connect \$100 $not$libresoc.v:187512$12460_Y + connect \$102 $and$libresoc.v:187513$12461_Y + connect \$104 $and$libresoc.v:187514$12462_Y + connect \$106 $and$libresoc.v:187515$12463_Y + connect \$108 $and$libresoc.v:187516$12464_Y + connect \$10 $and$libresoc.v:187517$12465_Y + connect \$110 $and$libresoc.v:187518$12466_Y + connect \$112 $and$libresoc.v:187519$12467_Y + connect \$114 $and$libresoc.v:187520$12468_Y + connect \$116 $and$libresoc.v:187521$12469_Y + connect \$118 $and$libresoc.v:187522$12470_Y + connect \$12 $not$libresoc.v:187523$12471_Y + connect \$14 $and$libresoc.v:187524$12472_Y + connect \$16 $not$libresoc.v:187525$12473_Y + connect \$18 $and$libresoc.v:187526$12474_Y + connect \$20 $and$libresoc.v:187527$12475_Y + connect \$24 $not$libresoc.v:187528$12476_Y + connect \$26 $and$libresoc.v:187529$12477_Y + connect \$23 $reduce_or$libresoc.v:187530$12478_Y + connect \$22 $not$libresoc.v:187531$12479_Y + connect \$2 $and$libresoc.v:187532$12480_Y + connect \$30 $and$libresoc.v:187533$12481_Y + connect \$32 $reduce_or$libresoc.v:187534$12482_Y + connect \$34 $reduce_or$libresoc.v:187535$12483_Y + connect \$36 $or$libresoc.v:187536$12484_Y + connect \$38 $not$libresoc.v:187537$12485_Y + connect \$40 $and$libresoc.v:187538$12486_Y + connect \$42 $and$libresoc.v:187539$12487_Y + connect \$44 $eq$libresoc.v:187540$12488_Y + connect \$46 $and$libresoc.v:187541$12489_Y + connect \$48 $eq$libresoc.v:187542$12490_Y + connect \$50 $and$libresoc.v:187543$12491_Y + connect \$52 $and$libresoc.v:187544$12492_Y + connect \$54 $and$libresoc.v:187545$12493_Y + connect \$56 $or$libresoc.v:187546$12494_Y + connect \$58 $or$libresoc.v:187547$12495_Y + connect \$5 $not$libresoc.v:187548$12496_Y + connect \$60 $or$libresoc.v:187549$12497_Y + connect \$62 $or$libresoc.v:187550$12498_Y + connect \$64 $and$libresoc.v:187551$12499_Y + connect \$66 $and$libresoc.v:187552$12500_Y + connect \$68 $or$libresoc.v:187553$12501_Y + connect \$70 $and$libresoc.v:187554$12502_Y + connect \$72 $and$libresoc.v:187555$12503_Y + connect \$74 $and$libresoc.v:187556$12504_Y + connect \$76 $ternary$libresoc.v:187557$12505_Y + connect \$78 $ternary$libresoc.v:187558$12506_Y + connect \$7 $or$libresoc.v:187559$12507_Y + connect \$80 $ternary$libresoc.v:187560$12508_Y + connect \$82 $ternary$libresoc.v:187561$12509_Y + connect \$84 $ternary$libresoc.v:187562$12510_Y + connect \$86 $ternary$libresoc.v:187563$12511_Y + connect \$88 $ternary$libresoc.v:187564$12512_Y + connect \$4 $reduce_and$libresoc.v:187565$12513_Y + connect \$90 $and$libresoc.v:187566$12514_Y + connect \$92 $and$libresoc.v:187567$12515_Y + connect \$94 $and$libresoc.v:187568$12516_Y + connect \$96 $not$libresoc.v:187569$12517_Y + connect \$98 $and$libresoc.v:187570$12518_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -387169,48 +391178,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:185784.1-185964.10" +attribute \src "libresoc.v:188088.1-188268.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:185936.3-185939.6" - wire width 7 $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 - attribute \src "libresoc.v:185936.3-185939.6" - wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 - attribute \src "libresoc.v:185936.3-185939.6" - wire width 64 $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 - attribute \src "libresoc.v:185936.3-185939.6" + attribute \src "libresoc.v:188240.3-188243.6" + wire width 7 $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + attribute \src "libresoc.v:188240.3-188243.6" + wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + attribute \src "libresoc.v:188240.3-188243.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:185785.7-185785.20" + attribute \src "libresoc.v:188089.7-188089.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185941.3-185949.6" - wire $0\ren_delay$next[0:0]$12666 - attribute \src "libresoc.v:185817.3-185818.35" + attribute \src "libresoc.v:188245.3-188253.6" + wire $0\ren_delay$next[0:0]$12850 + attribute \src "libresoc.v:188121.3-188122.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:185950.3-185959.6" + attribute \src "libresoc.v:188254.3-188263.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:185941.3-185949.6" - wire $1\ren_delay$next[0:0]$12667 - attribute \src "libresoc.v:185801.7-185801.23" + attribute \src "libresoc.v:188245.3-188253.6" + wire $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188105.7-188105.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:185950.3-185959.6" + attribute \src "libresoc.v:188254.3-188263.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:185940.26-185940.32" - wire width 64 $memrd$\memory$libresoc.v:185940$12664_DATA + attribute \src "libresoc.v:188244.26-188244.32" + wire width 64 $memrd$\memory$libresoc.v:188244$12848_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:185938$12658_ADDR + wire width 7 $memwr$\memory$libresoc.v:188242$12842_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:185938$12658_DATA + wire width 64 $memwr$\memory$libresoc.v:188242$12842_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:185938$12658_EN - attribute \src "libresoc.v:185935.13-185935.16" + wire width 64 $memwr$\memory$libresoc.v:188242$12842_EN + attribute \src "libresoc.v:188239.13-188239.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185785.7-185785.15" + attribute \src "libresoc.v:188089.7-188089.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -387238,1140 +391247,1140 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:185819.14-185819.20" + attribute \src "libresoc.v:188123.14-188123.20" memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12669 + cell $meminit $meminit$\memory$libresoc.v:0$12853 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12669 + parameter \PRIORITY 12853 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12670 + cell $meminit $meminit$\memory$libresoc.v:0$12854 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12670 + parameter \PRIORITY 12854 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12671 + cell $meminit $meminit$\memory$libresoc.v:0$12855 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12671 + parameter \PRIORITY 12855 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12672 + cell $meminit $meminit$\memory$libresoc.v:0$12856 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12672 + parameter \PRIORITY 12856 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12673 + cell $meminit $meminit$\memory$libresoc.v:0$12857 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12673 + parameter \PRIORITY 12857 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12674 + cell $meminit $meminit$\memory$libresoc.v:0$12858 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12674 + parameter \PRIORITY 12858 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12675 + cell $meminit $meminit$\memory$libresoc.v:0$12859 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12675 + parameter \PRIORITY 12859 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12676 + cell $meminit $meminit$\memory$libresoc.v:0$12860 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12676 + parameter \PRIORITY 12860 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12677 + cell $meminit $meminit$\memory$libresoc.v:0$12861 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12677 + parameter \PRIORITY 12861 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12678 + cell $meminit $meminit$\memory$libresoc.v:0$12862 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12678 + parameter \PRIORITY 12862 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12679 + cell $meminit $meminit$\memory$libresoc.v:0$12863 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12679 + parameter \PRIORITY 12863 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12680 + cell $meminit $meminit$\memory$libresoc.v:0$12864 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12680 + parameter \PRIORITY 12864 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12681 + cell $meminit $meminit$\memory$libresoc.v:0$12865 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12681 + parameter \PRIORITY 12865 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12682 + cell $meminit $meminit$\memory$libresoc.v:0$12866 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12682 + parameter \PRIORITY 12866 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12683 + cell $meminit $meminit$\memory$libresoc.v:0$12867 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12683 + parameter \PRIORITY 12867 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12684 + cell $meminit $meminit$\memory$libresoc.v:0$12868 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12684 + parameter \PRIORITY 12868 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12685 + cell $meminit $meminit$\memory$libresoc.v:0$12869 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12685 + parameter \PRIORITY 12869 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12686 + cell $meminit $meminit$\memory$libresoc.v:0$12870 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12686 + parameter \PRIORITY 12870 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12687 + cell $meminit $meminit$\memory$libresoc.v:0$12871 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12687 + parameter \PRIORITY 12871 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12688 + cell $meminit $meminit$\memory$libresoc.v:0$12872 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12688 + parameter \PRIORITY 12872 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12689 + cell $meminit $meminit$\memory$libresoc.v:0$12873 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12689 + parameter \PRIORITY 12873 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12690 + cell $meminit $meminit$\memory$libresoc.v:0$12874 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12690 + parameter \PRIORITY 12874 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12691 + cell $meminit $meminit$\memory$libresoc.v:0$12875 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12691 + parameter \PRIORITY 12875 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12692 + cell $meminit $meminit$\memory$libresoc.v:0$12876 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12692 + parameter \PRIORITY 12876 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12693 + cell $meminit $meminit$\memory$libresoc.v:0$12877 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12693 + parameter \PRIORITY 12877 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12694 + cell $meminit $meminit$\memory$libresoc.v:0$12878 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12694 + parameter \PRIORITY 12878 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12695 + cell $meminit $meminit$\memory$libresoc.v:0$12879 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12695 + parameter \PRIORITY 12879 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12696 + cell $meminit $meminit$\memory$libresoc.v:0$12880 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12696 + parameter \PRIORITY 12880 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12697 + cell $meminit $meminit$\memory$libresoc.v:0$12881 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12697 + parameter \PRIORITY 12881 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12698 + cell $meminit $meminit$\memory$libresoc.v:0$12882 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12698 + parameter \PRIORITY 12882 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12699 + cell $meminit $meminit$\memory$libresoc.v:0$12883 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12699 + parameter \PRIORITY 12883 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12700 + cell $meminit $meminit$\memory$libresoc.v:0$12884 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12700 + parameter \PRIORITY 12884 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12701 + cell $meminit $meminit$\memory$libresoc.v:0$12885 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12701 + parameter \PRIORITY 12885 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12702 + cell $meminit $meminit$\memory$libresoc.v:0$12886 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12702 + parameter \PRIORITY 12886 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12703 + cell $meminit $meminit$\memory$libresoc.v:0$12887 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12703 + parameter \PRIORITY 12887 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12704 + cell $meminit $meminit$\memory$libresoc.v:0$12888 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12704 + parameter \PRIORITY 12888 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12705 + cell $meminit $meminit$\memory$libresoc.v:0$12889 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12705 + parameter \PRIORITY 12889 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12706 + cell $meminit $meminit$\memory$libresoc.v:0$12890 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12706 + parameter \PRIORITY 12890 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12707 + cell $meminit $meminit$\memory$libresoc.v:0$12891 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12707 + parameter \PRIORITY 12891 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12708 + cell $meminit $meminit$\memory$libresoc.v:0$12892 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12708 + parameter \PRIORITY 12892 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12709 + cell $meminit $meminit$\memory$libresoc.v:0$12893 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12709 + parameter \PRIORITY 12893 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12710 + cell $meminit $meminit$\memory$libresoc.v:0$12894 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12710 + parameter \PRIORITY 12894 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12711 + cell $meminit $meminit$\memory$libresoc.v:0$12895 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12711 + parameter \PRIORITY 12895 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12712 + cell $meminit $meminit$\memory$libresoc.v:0$12896 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12712 + parameter \PRIORITY 12896 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12713 + cell $meminit $meminit$\memory$libresoc.v:0$12897 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12713 + parameter \PRIORITY 12897 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12714 + cell $meminit $meminit$\memory$libresoc.v:0$12898 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12714 + parameter \PRIORITY 12898 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12715 + cell $meminit $meminit$\memory$libresoc.v:0$12899 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12715 + parameter \PRIORITY 12899 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12716 + cell $meminit $meminit$\memory$libresoc.v:0$12900 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12716 + parameter \PRIORITY 12900 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12717 + cell $meminit $meminit$\memory$libresoc.v:0$12901 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12717 + parameter \PRIORITY 12901 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12718 + cell $meminit $meminit$\memory$libresoc.v:0$12902 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12718 + parameter \PRIORITY 12902 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12719 + cell $meminit $meminit$\memory$libresoc.v:0$12903 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12719 + parameter \PRIORITY 12903 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12720 + cell $meminit $meminit$\memory$libresoc.v:0$12904 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12720 + parameter \PRIORITY 12904 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12721 + cell $meminit $meminit$\memory$libresoc.v:0$12905 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12721 + parameter \PRIORITY 12905 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12722 + cell $meminit $meminit$\memory$libresoc.v:0$12906 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12722 + parameter \PRIORITY 12906 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12723 + cell $meminit $meminit$\memory$libresoc.v:0$12907 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12723 + parameter \PRIORITY 12907 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12724 + cell $meminit $meminit$\memory$libresoc.v:0$12908 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12724 + parameter \PRIORITY 12908 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12725 + cell $meminit $meminit$\memory$libresoc.v:0$12909 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12725 + parameter \PRIORITY 12909 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12726 + cell $meminit $meminit$\memory$libresoc.v:0$12910 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12726 + parameter \PRIORITY 12910 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12727 + cell $meminit $meminit$\memory$libresoc.v:0$12911 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12727 + parameter \PRIORITY 12911 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12728 + cell $meminit $meminit$\memory$libresoc.v:0$12912 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12728 + parameter \PRIORITY 12912 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12729 + cell $meminit $meminit$\memory$libresoc.v:0$12913 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12729 + parameter \PRIORITY 12913 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12730 + cell $meminit $meminit$\memory$libresoc.v:0$12914 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12730 + parameter \PRIORITY 12914 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12731 + cell $meminit $meminit$\memory$libresoc.v:0$12915 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12731 + parameter \PRIORITY 12915 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12732 + cell $meminit $meminit$\memory$libresoc.v:0$12916 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12732 + parameter \PRIORITY 12916 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12733 + cell $meminit $meminit$\memory$libresoc.v:0$12917 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12733 + parameter \PRIORITY 12917 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12734 + cell $meminit $meminit$\memory$libresoc.v:0$12918 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12734 + parameter \PRIORITY 12918 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12735 + cell $meminit $meminit$\memory$libresoc.v:0$12919 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12735 + parameter \PRIORITY 12919 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12736 + cell $meminit $meminit$\memory$libresoc.v:0$12920 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12736 + parameter \PRIORITY 12920 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12737 + cell $meminit $meminit$\memory$libresoc.v:0$12921 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12737 + parameter \PRIORITY 12921 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12738 + cell $meminit $meminit$\memory$libresoc.v:0$12922 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12738 + parameter \PRIORITY 12922 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12739 + cell $meminit $meminit$\memory$libresoc.v:0$12923 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12739 + parameter \PRIORITY 12923 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12740 + cell $meminit $meminit$\memory$libresoc.v:0$12924 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12740 + parameter \PRIORITY 12924 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12741 + cell $meminit $meminit$\memory$libresoc.v:0$12925 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12741 + parameter \PRIORITY 12925 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12742 + cell $meminit $meminit$\memory$libresoc.v:0$12926 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12742 + parameter \PRIORITY 12926 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12743 + cell $meminit $meminit$\memory$libresoc.v:0$12927 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12743 + parameter \PRIORITY 12927 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12744 + cell $meminit $meminit$\memory$libresoc.v:0$12928 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12744 + parameter \PRIORITY 12928 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12745 + cell $meminit $meminit$\memory$libresoc.v:0$12929 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12745 + parameter \PRIORITY 12929 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12746 + cell $meminit $meminit$\memory$libresoc.v:0$12930 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12746 + parameter \PRIORITY 12930 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12747 + cell $meminit $meminit$\memory$libresoc.v:0$12931 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12747 + parameter \PRIORITY 12931 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12748 + cell $meminit $meminit$\memory$libresoc.v:0$12932 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12748 + parameter \PRIORITY 12932 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12749 + cell $meminit $meminit$\memory$libresoc.v:0$12933 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12749 + parameter \PRIORITY 12933 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12750 + cell $meminit $meminit$\memory$libresoc.v:0$12934 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12750 + parameter \PRIORITY 12934 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12751 + cell $meminit $meminit$\memory$libresoc.v:0$12935 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12751 + parameter \PRIORITY 12935 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12752 + cell $meminit $meminit$\memory$libresoc.v:0$12936 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12752 + parameter \PRIORITY 12936 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12753 + cell $meminit $meminit$\memory$libresoc.v:0$12937 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12753 + parameter \PRIORITY 12937 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12754 + cell $meminit $meminit$\memory$libresoc.v:0$12938 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12754 + parameter \PRIORITY 12938 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12755 + cell $meminit $meminit$\memory$libresoc.v:0$12939 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12755 + parameter \PRIORITY 12939 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12756 + cell $meminit $meminit$\memory$libresoc.v:0$12940 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12756 + parameter \PRIORITY 12940 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12757 + cell $meminit $meminit$\memory$libresoc.v:0$12941 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12757 + parameter \PRIORITY 12941 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12758 + cell $meminit $meminit$\memory$libresoc.v:0$12942 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12758 + parameter \PRIORITY 12942 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12759 + cell $meminit $meminit$\memory$libresoc.v:0$12943 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12759 + parameter \PRIORITY 12943 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12760 + cell $meminit $meminit$\memory$libresoc.v:0$12944 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12760 + parameter \PRIORITY 12944 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12761 + cell $meminit $meminit$\memory$libresoc.v:0$12945 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12761 + parameter \PRIORITY 12945 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12762 + cell $meminit $meminit$\memory$libresoc.v:0$12946 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12762 + parameter \PRIORITY 12946 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12763 + cell $meminit $meminit$\memory$libresoc.v:0$12947 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12763 + parameter \PRIORITY 12947 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12764 + cell $meminit $meminit$\memory$libresoc.v:0$12948 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12764 + parameter \PRIORITY 12948 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12765 + cell $meminit $meminit$\memory$libresoc.v:0$12949 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12765 + parameter \PRIORITY 12949 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12766 + cell $meminit $meminit$\memory$libresoc.v:0$12950 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12766 + parameter \PRIORITY 12950 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12767 + cell $meminit $meminit$\memory$libresoc.v:0$12951 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12767 + parameter \PRIORITY 12951 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12768 + cell $meminit $meminit$\memory$libresoc.v:0$12952 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12768 + parameter \PRIORITY 12952 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12769 + cell $meminit $meminit$\memory$libresoc.v:0$12953 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12769 + parameter \PRIORITY 12953 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12770 + cell $meminit $meminit$\memory$libresoc.v:0$12954 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12770 + parameter \PRIORITY 12954 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12771 + cell $meminit $meminit$\memory$libresoc.v:0$12955 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12771 + parameter \PRIORITY 12955 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12772 + cell $meminit $meminit$\memory$libresoc.v:0$12956 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12772 + parameter \PRIORITY 12956 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12773 + cell $meminit $meminit$\memory$libresoc.v:0$12957 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12773 + parameter \PRIORITY 12957 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12774 + cell $meminit $meminit$\memory$libresoc.v:0$12958 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12774 + parameter \PRIORITY 12958 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12775 + cell $meminit $meminit$\memory$libresoc.v:0$12959 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12775 + parameter \PRIORITY 12959 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12776 + cell $meminit $meminit$\memory$libresoc.v:0$12960 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12776 + parameter \PRIORITY 12960 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12777 + cell $meminit $meminit$\memory$libresoc.v:0$12961 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12777 + parameter \PRIORITY 12961 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12778 + cell $meminit $meminit$\memory$libresoc.v:0$12962 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12778 + parameter \PRIORITY 12962 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12779 + cell $meminit $meminit$\memory$libresoc.v:0$12963 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12779 + parameter \PRIORITY 12963 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 110 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12780 + cell $meminit $meminit$\memory$libresoc.v:0$12964 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12780 + parameter \PRIORITY 12964 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 111 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12781 + cell $meminit $meminit$\memory$libresoc.v:0$12965 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12781 + parameter \PRIORITY 12965 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 112 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:185940.26-185940.32" - cell $memrd $memrd$\memory$libresoc.v:185940$12664 + attribute \src "libresoc.v:188244.26-188244.32" + cell $memrd $memrd$\memory$libresoc.v:188244$12848 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -388380,83 +392389,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:185940$12664_DATA + connect \DATA $memrd$\memory$libresoc.v:188244$12848_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12782 + cell $memwr $memwr$\memory$libresoc.v:0$12966 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 12782 + parameter \PRIORITY 12966 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:185938$12658_ADDR + connect \ADDR $memwr$\memory$libresoc.v:188242$12842_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:185938$12658_DATA - connect \EN $memwr$\memory$libresoc.v:185938$12658_EN + connect \DATA $memwr$\memory$libresoc.v:188242$12842_DATA + connect \EN $memwr$\memory$libresoc.v:188242$12842_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12785 + process $proc$libresoc.v:0$12969 sync always sync init end - attribute \src "libresoc.v:185785.7-185785.20" - process $proc$libresoc.v:185785$12783 + attribute \src "libresoc.v:188089.7-188089.20" + process $proc$libresoc.v:188089$12967 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185801.7-185801.23" - process $proc$libresoc.v:185801$12784 + attribute \src "libresoc.v:188105.7-188105.23" + process $proc$libresoc.v:188105$12968 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:185817.3-185818.35" - process $proc$libresoc.v:185817$12659 + attribute \src "libresoc.v:188121.3-188122.35" + process $proc$libresoc.v:188121$12843 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:185936.3-185939.6" - process $proc$libresoc.v:185936$12660 + attribute \src "libresoc.v:188240.3-188243.6" + process $proc$libresoc.v:188240$12844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:185938.5-185938.59" + attribute \src "libresoc.v:188242.5-188242.59" switch \spr1__wen - attribute \src "libresoc.v:185938.9-185938.18" + attribute \src "libresoc.v:188242.9-188242.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:185938$12658_ADDR $0$memwr$\memory$libresoc.v:185938$12658_ADDR[6:0]$12661 - update $memwr$\memory$libresoc.v:185938$12658_DATA $0$memwr$\memory$libresoc.v:185938$12658_DATA[63:0]$12662 - update $memwr$\memory$libresoc.v:185938$12658_EN $0$memwr$\memory$libresoc.v:185938$12658_EN[63:0]$12663 + update $memwr$\memory$libresoc.v:188242$12842_ADDR $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 + update $memwr$\memory$libresoc.v:188242$12842_DATA $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 + update $memwr$\memory$libresoc.v:188242$12842_EN $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 end - attribute \src "libresoc.v:185941.3-185949.6" - process $proc$libresoc.v:185941$12665 + attribute \src "libresoc.v:188245.3-188253.6" + process $proc$libresoc.v:188245$12849 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12666 $1\ren_delay$next[0:0]$12667 - attribute \src "libresoc.v:185942.5-185942.29" + assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 + attribute \src "libresoc.v:188246.5-188246.29" switch \initial - attribute \src "libresoc.v:185942.9-185942.17" + attribute \src "libresoc.v:188246.9-188246.17" case 1'1 case end @@ -388465,21 +392474,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12667 1'0 + assign $1\ren_delay$next[0:0]$12851 1'0 case - assign $1\ren_delay$next[0:0]$12667 \spr1__ren + assign $1\ren_delay$next[0:0]$12851 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12666 + update \ren_delay$next $0\ren_delay$next[0:0]$12850 end - attribute \src "libresoc.v:185950.3-185959.6" - process $proc$libresoc.v:185950$12668 + attribute \src "libresoc.v:188254.3-188263.6" + process $proc$libresoc.v:188254$12852 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:185951.5-185951.29" + attribute \src "libresoc.v:188255.5-188255.29" switch \initial - attribute \src "libresoc.v:185951.9-185951.17" + attribute \src "libresoc.v:188255.9-188255.17" case 1'1 case end @@ -388495,503 +392504,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:185940$12664_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:188244$12848_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:185968.1-187221.10" +attribute \src "libresoc.v:188272.1-189525.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:186718.3-186719.25" + attribute \src "libresoc.v:189022.3-189023.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:186716.3-186717.40" + attribute \src "libresoc.v:189020.3-189021.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:187112.3-187120.6" - wire $0\alu_l_r_alu$next[0:0]$12999 - attribute \src "libresoc.v:186646.3-186647.39" + attribute \src "libresoc.v:189416.3-189424.6" + wire $0\alu_l_r_alu$next[0:0]$13183 + attribute \src "libresoc.v:188950.3-188951.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 - attribute \src "libresoc.v:186688.3-186689.65" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + attribute \src "libresoc.v:188992.3-188993.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12922 - attribute \src "libresoc.v:186690.3-186691.59" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 + attribute \src "libresoc.v:188994.3-188995.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 - attribute \src "libresoc.v:186686.3-186687.69" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + attribute \src "libresoc.v:188990.3-188991.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 - attribute \src "libresoc.v:186692.3-186693.67" + attribute \src "libresoc.v:189202.3-189214.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + attribute \src "libresoc.v:188996.3-188997.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:187103.3-187111.6" - wire $0\alui_l_r_alui$next[0:0]$12996 - attribute \src "libresoc.v:186648.3-186649.43" + attribute \src "libresoc.v:189407.3-189415.6" + wire $0\alui_l_r_alui$next[0:0]$13180 + attribute \src "libresoc.v:188952.3-188953.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $0\data_r0__o$next[63:0]$12930 - attribute \src "libresoc.v:186682.3-186683.37" + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $0\data_r0__o$next[63:0]$13114 + attribute \src "libresoc.v:188986.3-188987.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire $0\data_r0__o_ok$next[0:0]$12931 - attribute \src "libresoc.v:186684.3-186685.43" + attribute \src "libresoc.v:189215.3-189236.6" + wire $0\data_r0__o_ok$next[0:0]$13115 + attribute \src "libresoc.v:188988.3-188989.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12938 - attribute \src "libresoc.v:186678.3-186679.43" + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $0\data_r1__spr1$next[63:0]$13122 + attribute \src "libresoc.v:188982.3-188983.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire $0\data_r1__spr1_ok$next[0:0]$12939 - attribute \src "libresoc.v:186680.3-186681.49" + attribute \src "libresoc.v:189237.3-189258.6" + wire $0\data_r1__spr1_ok$next[0:0]$13123 + attribute \src "libresoc.v:188984.3-188985.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12946 - attribute \src "libresoc.v:186674.3-186675.45" + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $0\data_r2__fast1$next[63:0]$13130 + attribute \src "libresoc.v:188978.3-188979.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire $0\data_r2__fast1_ok$next[0:0]$12947 - attribute \src "libresoc.v:186676.3-186677.51" + attribute \src "libresoc.v:189259.3-189280.6" + wire $0\data_r2__fast1_ok$next[0:0]$13131 + attribute \src "libresoc.v:188980.3-188981.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $0\data_r3__xer_so$next[0:0]$12954 - attribute \src "libresoc.v:186670.3-186671.47" + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so$next[0:0]$13138 + attribute \src "libresoc.v:188974.3-188975.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12955 - attribute \src "libresoc.v:186672.3-186673.53" + attribute \src "libresoc.v:189281.3-189302.6" + wire $0\data_r3__xer_so_ok$next[0:0]$13139 + attribute \src "libresoc.v:188976.3-188977.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12962 - attribute \src "libresoc.v:186666.3-186667.47" + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 + attribute \src "libresoc.v:188970.3-188971.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12963 - attribute \src "libresoc.v:186668.3-186669.53" + attribute \src "libresoc.v:189303.3-189324.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13147 + attribute \src "libresoc.v:188972.3-188973.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12970 - attribute \src "libresoc.v:186662.3-186663.47" + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 + attribute \src "libresoc.v:188966.3-188967.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12971 - attribute \src "libresoc.v:186664.3-186665.53" + attribute \src "libresoc.v:189325.3-189346.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13155 + attribute \src "libresoc.v:188968.3-188969.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:187121.3-187130.6" + attribute \src "libresoc.v:189425.3-189434.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:187131.3-187140.6" + attribute \src "libresoc.v:189435.3-189444.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:187141.3-187150.6" + attribute \src "libresoc.v:189445.3-189454.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:187151.3-187160.6" + attribute \src "libresoc.v:189455.3-189464.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:187161.3-187170.6" + attribute \src "libresoc.v:189465.3-189474.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:187171.3-187180.6" + attribute \src "libresoc.v:189475.3-189484.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:185969.7-185969.20" + attribute \src "libresoc.v:188273.7-188273.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186853.3-186861.6" - wire $0\opc_l_r_opc$next[0:0]$12906 - attribute \src "libresoc.v:186702.3-186703.39" + attribute \src "libresoc.v:189157.3-189165.6" + wire $0\opc_l_r_opc$next[0:0]$13090 + attribute \src "libresoc.v:189006.3-189007.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:186844.3-186852.6" - wire $0\opc_l_s_opc$next[0:0]$12903 - attribute \src "libresoc.v:186704.3-186705.39" + attribute \src "libresoc.v:189148.3-189156.6" + wire $0\opc_l_s_opc$next[0:0]$13087 + attribute \src "libresoc.v:189008.3-189009.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187181.3-187189.6" - wire width 6 $0\prev_wr_go$next[5:0]$13008 - attribute \src "libresoc.v:186714.3-186715.37" + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $0\prev_wr_go$next[5:0]$13192 + attribute \src "libresoc.v:189018.3-189019.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:186798.3-186807.6" + attribute \src "libresoc.v:189102.3-189111.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:186889.3-186897.6" - wire width 6 $0\req_l_r_req$next[5:0]$12918 - attribute \src "libresoc.v:186694.3-186695.39" + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $0\req_l_r_req$next[5:0]$13102 + attribute \src "libresoc.v:188998.3-188999.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:186880.3-186888.6" - wire width 6 $0\req_l_s_req$next[5:0]$12915 - attribute \src "libresoc.v:186696.3-186697.39" + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $0\req_l_s_req$next[5:0]$13099 + attribute \src "libresoc.v:189000.3-189001.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:186817.3-186825.6" - wire $0\rok_l_r_rdok$next[0:0]$12894 - attribute \src "libresoc.v:186710.3-186711.41" + attribute \src "libresoc.v:189121.3-189129.6" + wire $0\rok_l_r_rdok$next[0:0]$13078 + attribute \src "libresoc.v:189014.3-189015.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:186808.3-186816.6" - wire $0\rok_l_s_rdok$next[0:0]$12891 - attribute \src "libresoc.v:186712.3-186713.41" + attribute \src "libresoc.v:189112.3-189120.6" + wire $0\rok_l_s_rdok$next[0:0]$13075 + attribute \src "libresoc.v:189016.3-189017.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:186835.3-186843.6" - wire $0\rst_l_r_rst$next[0:0]$12900 - attribute \src "libresoc.v:186706.3-186707.39" + attribute \src "libresoc.v:189139.3-189147.6" + wire $0\rst_l_r_rst$next[0:0]$13084 + attribute \src "libresoc.v:189010.3-189011.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:186826.3-186834.6" - wire $0\rst_l_s_rst$next[0:0]$12897 - attribute \src "libresoc.v:186708.3-186709.39" + attribute \src "libresoc.v:189130.3-189138.6" + wire $0\rst_l_s_rst$next[0:0]$13081 + attribute \src "libresoc.v:189012.3-189013.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:186871.3-186879.6" - wire width 6 $0\src_l_r_src$next[5:0]$12912 - attribute \src "libresoc.v:186698.3-186699.39" + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $0\src_l_r_src$next[5:0]$13096 + attribute \src "libresoc.v:189002.3-189003.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:186862.3-186870.6" - wire width 6 $0\src_l_s_src$next[5:0]$12909 - attribute \src "libresoc.v:186700.3-186701.39" + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $0\src_l_s_src$next[5:0]$13093 + attribute \src "libresoc.v:189004.3-189005.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:187043.3-187052.6" - wire width 64 $0\src_r0$next[63:0]$12978 - attribute \src "libresoc.v:186660.3-186661.29" + attribute \src "libresoc.v:189347.3-189356.6" + wire width 64 $0\src_r0$next[63:0]$13162 + attribute \src "libresoc.v:188964.3-188965.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187053.3-187062.6" - wire width 64 $0\src_r1$next[63:0]$12981 - attribute \src "libresoc.v:186658.3-186659.29" + attribute \src "libresoc.v:189357.3-189366.6" + wire width 64 $0\src_r1$next[63:0]$13165 + attribute \src "libresoc.v:188962.3-188963.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187063.3-187072.6" - wire width 64 $0\src_r2$next[63:0]$12984 - attribute \src "libresoc.v:186656.3-186657.29" + attribute \src "libresoc.v:189367.3-189376.6" + wire width 64 $0\src_r2$next[63:0]$13168 + attribute \src "libresoc.v:188960.3-188961.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187073.3-187082.6" - wire $0\src_r3$next[0:0]$12987 - attribute \src "libresoc.v:186654.3-186655.29" + attribute \src "libresoc.v:189377.3-189386.6" + wire $0\src_r3$next[0:0]$13171 + attribute \src "libresoc.v:188958.3-188959.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:187083.3-187092.6" - wire width 2 $0\src_r4$next[1:0]$12990 - attribute \src "libresoc.v:186652.3-186653.29" + attribute \src "libresoc.v:189387.3-189396.6" + wire width 2 $0\src_r4$next[1:0]$13174 + attribute \src "libresoc.v:188956.3-188957.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:187093.3-187102.6" - wire width 2 $0\src_r5$next[1:0]$12993 - attribute \src "libresoc.v:186650.3-186651.29" + attribute \src "libresoc.v:189397.3-189406.6" + wire width 2 $0\src_r5$next[1:0]$13177 + attribute \src "libresoc.v:188954.3-188955.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:186105.7-186105.24" + attribute \src "libresoc.v:188409.7-188409.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:186115.7-186115.26" + attribute \src "libresoc.v:188419.7-188419.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:187112.3-187120.6" - wire $1\alu_l_r_alu$next[0:0]$13000 - attribute \src "libresoc.v:186123.7-186123.25" + attribute \src "libresoc.v:189416.3-189424.6" + wire $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:188427.7-188427.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 - attribute \src "libresoc.v:186168.14-186168.49" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + attribute \src "libresoc.v:188472.14-188472.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12926 - attribute \src "libresoc.v:186172.14-186172.43" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + attribute \src "libresoc.v:188476.14-188476.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 - attribute \src "libresoc.v:186251.13-186251.47" + attribute \src "libresoc.v:189202.3-189214.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + attribute \src "libresoc.v:188555.13-188555.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:186898.3-186910.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 - attribute \src "libresoc.v:186255.7-186255.39" + attribute \src "libresoc.v:189202.3-189214.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:188559.7-188559.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:187103.3-187111.6" - wire $1\alui_l_r_alui$next[0:0]$12997 - attribute \src "libresoc.v:186273.7-186273.27" + attribute \src "libresoc.v:189407.3-189415.6" + wire $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:188577.7-188577.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $1\data_r0__o$next[63:0]$12932 - attribute \src "libresoc.v:186305.14-186305.47" + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $1\data_r0__o$next[63:0]$13116 + attribute \src "libresoc.v:188609.14-188609.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire $1\data_r0__o_ok$next[0:0]$12933 - attribute \src "libresoc.v:186309.7-186309.27" + attribute \src "libresoc.v:189215.3-189236.6" + wire $1\data_r0__o_ok$next[0:0]$13117 + attribute \src "libresoc.v:188613.7-188613.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12940 - attribute \src "libresoc.v:186313.14-186313.50" + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $1\data_r1__spr1$next[63:0]$13124 + attribute \src "libresoc.v:188617.14-188617.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:186933.3-186954.6" - wire $1\data_r1__spr1_ok$next[0:0]$12941 - attribute \src "libresoc.v:186317.7-186317.30" + attribute \src "libresoc.v:189237.3-189258.6" + wire $1\data_r1__spr1_ok$next[0:0]$13125 + attribute \src "libresoc.v:188621.7-188621.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12948 - attribute \src "libresoc.v:186321.14-186321.51" + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $1\data_r2__fast1$next[63:0]$13132 + attribute \src "libresoc.v:188625.14-188625.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:186955.3-186976.6" - wire $1\data_r2__fast1_ok$next[0:0]$12949 - attribute \src "libresoc.v:186325.7-186325.31" + attribute \src "libresoc.v:189259.3-189280.6" + wire $1\data_r2__fast1_ok$next[0:0]$13133 + attribute \src "libresoc.v:188629.7-188629.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $1\data_r3__xer_so$next[0:0]$12956 - attribute \src "libresoc.v:186329.7-186329.29" + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so$next[0:0]$13140 + attribute \src "libresoc.v:188633.7-188633.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:186977.3-186998.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12957 - attribute \src "libresoc.v:186333.7-186333.32" + attribute \src "libresoc.v:189281.3-189302.6" + wire $1\data_r3__xer_so_ok$next[0:0]$13141 + attribute \src "libresoc.v:188637.7-188637.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12964 - attribute \src "libresoc.v:186337.13-186337.35" + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 + attribute \src "libresoc.v:188641.13-188641.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:186999.3-187020.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12965 - attribute \src "libresoc.v:186341.7-186341.32" + attribute \src "libresoc.v:189303.3-189324.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13149 + attribute \src "libresoc.v:188645.7-188645.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12972 - attribute \src "libresoc.v:186345.13-186345.35" + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 + attribute \src "libresoc.v:188649.13-188649.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:187021.3-187042.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12973 - attribute \src "libresoc.v:186349.7-186349.32" + attribute \src "libresoc.v:189325.3-189346.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13157 + attribute \src "libresoc.v:188653.7-188653.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:187121.3-187130.6" + attribute \src "libresoc.v:189425.3-189434.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:187131.3-187140.6" + attribute \src "libresoc.v:189435.3-189444.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:187141.3-187150.6" + attribute \src "libresoc.v:189445.3-189454.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:187151.3-187160.6" + attribute \src "libresoc.v:189455.3-189464.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:187161.3-187170.6" + attribute \src "libresoc.v:189465.3-189474.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:187171.3-187180.6" + attribute \src "libresoc.v:189475.3-189484.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:186853.3-186861.6" - wire $1\opc_l_r_opc$next[0:0]$12907 - attribute \src "libresoc.v:186377.7-186377.25" + attribute \src "libresoc.v:189157.3-189165.6" + wire $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:188681.7-188681.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:186844.3-186852.6" - wire $1\opc_l_s_opc$next[0:0]$12904 - attribute \src "libresoc.v:186381.7-186381.25" + attribute \src "libresoc.v:189148.3-189156.6" + wire $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:188685.7-188685.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:187181.3-187189.6" - wire width 6 $1\prev_wr_go$next[5:0]$13009 - attribute \src "libresoc.v:186483.13-186483.31" + attribute \src "libresoc.v:189485.3-189493.6" + wire width 6 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:188787.13-188787.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:186798.3-186807.6" + attribute \src "libresoc.v:189102.3-189111.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:186889.3-186897.6" - wire width 6 $1\req_l_r_req$next[5:0]$12919 - attribute \src "libresoc.v:186491.13-186491.32" + attribute \src "libresoc.v:189193.3-189201.6" + wire width 6 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:188795.13-188795.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:186880.3-186888.6" - wire width 6 $1\req_l_s_req$next[5:0]$12916 - attribute \src "libresoc.v:186495.13-186495.32" + attribute \src "libresoc.v:189184.3-189192.6" + wire width 6 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:188799.13-188799.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:186817.3-186825.6" - wire $1\rok_l_r_rdok$next[0:0]$12895 - attribute \src "libresoc.v:186507.7-186507.26" + attribute \src "libresoc.v:189121.3-189129.6" + wire $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:188811.7-188811.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:186808.3-186816.6" - wire $1\rok_l_s_rdok$next[0:0]$12892 - attribute \src "libresoc.v:186511.7-186511.26" + attribute \src "libresoc.v:189112.3-189120.6" + wire $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:188815.7-188815.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:186835.3-186843.6" - wire $1\rst_l_r_rst$next[0:0]$12901 - attribute \src "libresoc.v:186515.7-186515.25" + attribute \src "libresoc.v:189139.3-189147.6" + wire $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:188819.7-188819.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:186826.3-186834.6" - wire $1\rst_l_s_rst$next[0:0]$12898 - attribute \src "libresoc.v:186519.7-186519.25" + attribute \src "libresoc.v:189130.3-189138.6" + wire $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:188823.7-188823.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:186871.3-186879.6" - wire width 6 $1\src_l_r_src$next[5:0]$12913 - attribute \src "libresoc.v:186541.13-186541.32" + attribute \src "libresoc.v:189175.3-189183.6" + wire width 6 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:188845.13-188845.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:186862.3-186870.6" - wire width 6 $1\src_l_s_src$next[5:0]$12910 - attribute \src "libresoc.v:186545.13-186545.32" + attribute \src "libresoc.v:189166.3-189174.6" + wire width 6 $1\src_l_s_src$next[5:0]$13094 + attribute \src "libresoc.v:188849.13-188849.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:187043.3-187052.6" - wire width 64 $1\src_r0$next[63:0]$12979 - attribute \src "libresoc.v:186549.14-186549.43" + attribute \src "libresoc.v:189347.3-189356.6" + wire width 64 $1\src_r0$next[63:0]$13163 + attribute \src "libresoc.v:188853.14-188853.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187053.3-187062.6" - wire width 64 $1\src_r1$next[63:0]$12982 - attribute \src "libresoc.v:186553.14-186553.43" + attribute \src "libresoc.v:189357.3-189366.6" + wire width 64 $1\src_r1$next[63:0]$13166 + attribute \src "libresoc.v:188857.14-188857.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187063.3-187072.6" - wire width 64 $1\src_r2$next[63:0]$12985 - attribute \src "libresoc.v:186557.14-186557.43" + attribute \src "libresoc.v:189367.3-189376.6" + wire width 64 $1\src_r2$next[63:0]$13169 + attribute \src "libresoc.v:188861.14-188861.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187073.3-187082.6" - wire $1\src_r3$next[0:0]$12988 - attribute \src "libresoc.v:186561.7-186561.20" + attribute \src "libresoc.v:189377.3-189386.6" + wire $1\src_r3$next[0:0]$13172 + attribute \src "libresoc.v:188865.7-188865.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:187083.3-187092.6" - wire width 2 $1\src_r4$next[1:0]$12991 - attribute \src "libresoc.v:186565.13-186565.26" + attribute \src "libresoc.v:189387.3-189396.6" + wire width 2 $1\src_r4$next[1:0]$13175 + attribute \src "libresoc.v:188869.13-188869.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:187093.3-187102.6" - wire width 2 $1\src_r5$next[1:0]$12994 - attribute \src "libresoc.v:186569.13-186569.26" + attribute \src "libresoc.v:189397.3-189406.6" + wire width 2 $1\src_r5$next[1:0]$13178 + attribute \src "libresoc.v:188873.13-188873.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:186911.3-186932.6" - wire width 64 $2\data_r0__o$next[63:0]$12934 - attribute \src "libresoc.v:186911.3-186932.6" - wire $2\data_r0__o_ok$next[0:0]$12935 - attribute \src "libresoc.v:186933.3-186954.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12942 - attribute \src "libresoc.v:186933.3-186954.6" - wire $2\data_r1__spr1_ok$next[0:0]$12943 - attribute \src "libresoc.v:186955.3-186976.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12950 - attribute \src "libresoc.v:186955.3-186976.6" - wire $2\data_r2__fast1_ok$next[0:0]$12951 - attribute \src "libresoc.v:186977.3-186998.6" - wire $2\data_r3__xer_so$next[0:0]$12958 - attribute \src "libresoc.v:186977.3-186998.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12959 - attribute \src "libresoc.v:186999.3-187020.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12966 - attribute \src "libresoc.v:186999.3-187020.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12967 - attribute \src "libresoc.v:187021.3-187042.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12974 - attribute \src "libresoc.v:187021.3-187042.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12975 - attribute \src "libresoc.v:186911.3-186932.6" - wire $3\data_r0__o_ok$next[0:0]$12936 - attribute \src "libresoc.v:186933.3-186954.6" - wire $3\data_r1__spr1_ok$next[0:0]$12944 - attribute \src "libresoc.v:186955.3-186976.6" - wire $3\data_r2__fast1_ok$next[0:0]$12952 - attribute \src "libresoc.v:186977.3-186998.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12960 - attribute \src "libresoc.v:186999.3-187020.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12968 - attribute \src "libresoc.v:187021.3-187042.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12976 - attribute \src "libresoc.v:186581.19-186581.133" - wire $and$libresoc.v:186581$12787_Y - attribute \src "libresoc.v:186582.19-186582.183" - wire width 6 $and$libresoc.v:186582$12788_Y - attribute \src "libresoc.v:186583.19-186583.115" - wire width 6 $and$libresoc.v:186583$12789_Y - attribute \src "libresoc.v:186585.19-186585.115" - wire width 6 $and$libresoc.v:186585$12791_Y - attribute \src "libresoc.v:186586.19-186586.125" - wire $and$libresoc.v:186586$12792_Y - attribute \src "libresoc.v:186587.19-186587.125" - wire $and$libresoc.v:186587$12793_Y - attribute \src "libresoc.v:186588.19-186588.125" - wire $and$libresoc.v:186588$12794_Y - attribute \src "libresoc.v:186589.19-186589.125" - wire $and$libresoc.v:186589$12795_Y - attribute \src "libresoc.v:186590.19-186590.125" - wire $and$libresoc.v:186590$12796_Y - attribute \src "libresoc.v:186592.19-186592.125" - wire $and$libresoc.v:186592$12798_Y - attribute \src "libresoc.v:186593.19-186593.165" - wire width 6 $and$libresoc.v:186593$12799_Y - attribute \src "libresoc.v:186594.19-186594.121" - wire width 6 $and$libresoc.v:186594$12800_Y - attribute \src "libresoc.v:186595.19-186595.127" - wire $and$libresoc.v:186595$12801_Y - attribute \src "libresoc.v:186596.19-186596.127" - wire $and$libresoc.v:186596$12802_Y - attribute \src "libresoc.v:186598.19-186598.127" - wire $and$libresoc.v:186598$12804_Y - attribute \src "libresoc.v:186599.19-186599.127" - wire $and$libresoc.v:186599$12805_Y - attribute \src "libresoc.v:186600.19-186600.127" - wire $and$libresoc.v:186600$12806_Y - attribute \src "libresoc.v:186601.19-186601.127" - wire $and$libresoc.v:186601$12807_Y - attribute \src "libresoc.v:186602.18-186602.110" - wire $and$libresoc.v:186602$12808_Y - attribute \src "libresoc.v:186604.18-186604.98" - wire $and$libresoc.v:186604$12810_Y - attribute \src "libresoc.v:186606.18-186606.100" - wire $and$libresoc.v:186606$12812_Y - attribute \src "libresoc.v:186607.18-186607.182" - wire width 6 $and$libresoc.v:186607$12813_Y - attribute \src "libresoc.v:186609.18-186609.119" - wire width 6 $and$libresoc.v:186609$12815_Y - attribute \src "libresoc.v:186612.18-186612.116" - wire $and$libresoc.v:186612$12818_Y - attribute \src "libresoc.v:186617.18-186617.113" - wire $and$libresoc.v:186617$12823_Y - attribute \src "libresoc.v:186618.18-186618.125" - wire width 6 $and$libresoc.v:186618$12824_Y - attribute \src "libresoc.v:186620.18-186620.112" - wire $and$libresoc.v:186620$12826_Y - attribute \src "libresoc.v:186622.18-186622.126" - wire $and$libresoc.v:186622$12828_Y - attribute \src "libresoc.v:186623.18-186623.126" - wire $and$libresoc.v:186623$12829_Y - attribute \src "libresoc.v:186624.18-186624.117" - wire $and$libresoc.v:186624$12830_Y - attribute \src "libresoc.v:186629.18-186629.130" - wire $and$libresoc.v:186629$12835_Y - attribute \src "libresoc.v:186630.17-186630.123" - wire $and$libresoc.v:186630$12836_Y - attribute \src "libresoc.v:186631.18-186631.124" - wire width 6 $and$libresoc.v:186631$12837_Y - attribute \src "libresoc.v:186633.18-186633.116" - wire $and$libresoc.v:186633$12839_Y - attribute \src "libresoc.v:186634.18-186634.119" - wire $and$libresoc.v:186634$12840_Y - attribute \src "libresoc.v:186635.18-186635.120" - wire $and$libresoc.v:186635$12841_Y - attribute \src "libresoc.v:186636.18-186636.121" - wire $and$libresoc.v:186636$12842_Y - attribute \src "libresoc.v:186637.18-186637.121" - wire $and$libresoc.v:186637$12843_Y - attribute \src "libresoc.v:186638.18-186638.121" - wire $and$libresoc.v:186638$12844_Y - attribute \src "libresoc.v:186645.18-186645.134" - wire $and$libresoc.v:186645$12851_Y - attribute \src "libresoc.v:186619.18-186619.113" - wire $eq$libresoc.v:186619$12825_Y - attribute \src "libresoc.v:186621.18-186621.119" - wire $eq$libresoc.v:186621$12827_Y - attribute \src "libresoc.v:186580.17-186580.113" - wire width 6 $not$libresoc.v:186580$12786_Y - attribute \src "libresoc.v:186584.19-186584.115" - wire width 6 $not$libresoc.v:186584$12790_Y - attribute \src "libresoc.v:186603.18-186603.97" - wire $not$libresoc.v:186603$12809_Y - attribute \src "libresoc.v:186605.18-186605.99" - wire $not$libresoc.v:186605$12811_Y - attribute \src "libresoc.v:186608.18-186608.113" - wire width 6 $not$libresoc.v:186608$12814_Y - attribute \src "libresoc.v:186611.18-186611.106" - wire $not$libresoc.v:186611$12817_Y - attribute \src "libresoc.v:186616.18-186616.120" - wire $not$libresoc.v:186616$12822_Y - attribute \src "libresoc.v:186591.18-186591.118" - wire width 6 $or$libresoc.v:186591$12797_Y - attribute \src "libresoc.v:186615.18-186615.112" - wire $or$libresoc.v:186615$12821_Y - attribute \src "libresoc.v:186625.18-186625.122" - wire $or$libresoc.v:186625$12831_Y - attribute \src "libresoc.v:186626.18-186626.124" - wire $or$libresoc.v:186626$12832_Y - attribute \src "libresoc.v:186627.18-186627.194" - wire width 6 $or$libresoc.v:186627$12833_Y - attribute \src "libresoc.v:186628.18-186628.194" - wire width 6 $or$libresoc.v:186628$12834_Y - attribute \src "libresoc.v:186632.18-186632.120" - wire width 6 $or$libresoc.v:186632$12838_Y - attribute \src "libresoc.v:186597.17-186597.105" - wire $reduce_and$libresoc.v:186597$12803_Y - attribute \src "libresoc.v:186610.18-186610.106" - wire $reduce_or$libresoc.v:186610$12816_Y - attribute \src "libresoc.v:186613.18-186613.113" - wire $reduce_or$libresoc.v:186613$12819_Y - attribute \src "libresoc.v:186614.18-186614.112" - wire $reduce_or$libresoc.v:186614$12820_Y - attribute \src "libresoc.v:186639.18-186639.118" - wire width 64 $ternary$libresoc.v:186639$12845_Y - attribute \src "libresoc.v:186640.18-186640.118" - wire width 64 $ternary$libresoc.v:186640$12846_Y - attribute \src "libresoc.v:186641.18-186641.118" - wire width 64 $ternary$libresoc.v:186641$12847_Y - attribute \src "libresoc.v:186642.18-186642.118" - wire $ternary$libresoc.v:186642$12848_Y - attribute \src "libresoc.v:186643.18-186643.118" - wire width 2 $ternary$libresoc.v:186643$12849_Y - attribute \src "libresoc.v:186644.18-186644.118" - wire width 2 $ternary$libresoc.v:186644$12850_Y + attribute \src "libresoc.v:189215.3-189236.6" + wire width 64 $2\data_r0__o$next[63:0]$13118 + attribute \src "libresoc.v:189215.3-189236.6" + wire $2\data_r0__o_ok$next[0:0]$13119 + attribute \src "libresoc.v:189237.3-189258.6" + wire width 64 $2\data_r1__spr1$next[63:0]$13126 + attribute \src "libresoc.v:189237.3-189258.6" + wire $2\data_r1__spr1_ok$next[0:0]$13127 + attribute \src "libresoc.v:189259.3-189280.6" + wire width 64 $2\data_r2__fast1$next[63:0]$13134 + attribute \src "libresoc.v:189259.3-189280.6" + wire $2\data_r2__fast1_ok$next[0:0]$13135 + attribute \src "libresoc.v:189281.3-189302.6" + wire $2\data_r3__xer_so$next[0:0]$13142 + attribute \src "libresoc.v:189281.3-189302.6" + wire $2\data_r3__xer_so_ok$next[0:0]$13143 + attribute \src "libresoc.v:189303.3-189324.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$13150 + attribute \src "libresoc.v:189303.3-189324.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$13151 + attribute \src "libresoc.v:189325.3-189346.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$13158 + attribute \src "libresoc.v:189325.3-189346.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$13159 + attribute \src "libresoc.v:189215.3-189236.6" + wire $3\data_r0__o_ok$next[0:0]$13120 + attribute \src "libresoc.v:189237.3-189258.6" + wire $3\data_r1__spr1_ok$next[0:0]$13128 + attribute \src "libresoc.v:189259.3-189280.6" + wire $3\data_r2__fast1_ok$next[0:0]$13136 + attribute \src "libresoc.v:189281.3-189302.6" + wire $3\data_r3__xer_so_ok$next[0:0]$13144 + attribute \src "libresoc.v:189303.3-189324.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$13152 + attribute \src "libresoc.v:189325.3-189346.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$13160 + attribute \src "libresoc.v:188885.19-188885.133" + wire $and$libresoc.v:188885$12971_Y + attribute \src "libresoc.v:188886.19-188886.183" + wire width 6 $and$libresoc.v:188886$12972_Y + attribute \src "libresoc.v:188887.19-188887.115" + wire width 6 $and$libresoc.v:188887$12973_Y + attribute \src "libresoc.v:188889.19-188889.115" + wire width 6 $and$libresoc.v:188889$12975_Y + attribute \src "libresoc.v:188890.19-188890.125" + wire $and$libresoc.v:188890$12976_Y + attribute \src "libresoc.v:188891.19-188891.125" + wire $and$libresoc.v:188891$12977_Y + attribute \src "libresoc.v:188892.19-188892.125" + wire $and$libresoc.v:188892$12978_Y + attribute \src "libresoc.v:188893.19-188893.125" + wire $and$libresoc.v:188893$12979_Y + attribute \src "libresoc.v:188894.19-188894.125" + wire $and$libresoc.v:188894$12980_Y + attribute \src "libresoc.v:188896.19-188896.125" + wire $and$libresoc.v:188896$12982_Y + attribute \src "libresoc.v:188897.19-188897.165" + wire width 6 $and$libresoc.v:188897$12983_Y + attribute \src "libresoc.v:188898.19-188898.121" + wire width 6 $and$libresoc.v:188898$12984_Y + attribute \src "libresoc.v:188899.19-188899.127" + wire $and$libresoc.v:188899$12985_Y + attribute \src "libresoc.v:188900.19-188900.127" + wire $and$libresoc.v:188900$12986_Y + attribute \src "libresoc.v:188902.19-188902.127" + wire $and$libresoc.v:188902$12988_Y + attribute \src "libresoc.v:188903.19-188903.127" + wire $and$libresoc.v:188903$12989_Y + attribute \src "libresoc.v:188904.19-188904.127" + wire $and$libresoc.v:188904$12990_Y + attribute \src "libresoc.v:188905.19-188905.127" + wire $and$libresoc.v:188905$12991_Y + attribute \src "libresoc.v:188906.18-188906.110" + wire $and$libresoc.v:188906$12992_Y + attribute \src "libresoc.v:188908.18-188908.98" + wire $and$libresoc.v:188908$12994_Y + attribute \src "libresoc.v:188910.18-188910.100" + wire $and$libresoc.v:188910$12996_Y + attribute \src "libresoc.v:188911.18-188911.182" + wire width 6 $and$libresoc.v:188911$12997_Y + attribute \src "libresoc.v:188913.18-188913.119" + wire width 6 $and$libresoc.v:188913$12999_Y + attribute \src "libresoc.v:188916.18-188916.116" + wire $and$libresoc.v:188916$13002_Y + attribute \src "libresoc.v:188921.18-188921.113" + wire $and$libresoc.v:188921$13007_Y + attribute \src "libresoc.v:188922.18-188922.125" + wire width 6 $and$libresoc.v:188922$13008_Y + attribute \src "libresoc.v:188924.18-188924.112" + wire $and$libresoc.v:188924$13010_Y + attribute \src "libresoc.v:188926.18-188926.126" + wire $and$libresoc.v:188926$13012_Y + attribute \src "libresoc.v:188927.18-188927.126" + wire $and$libresoc.v:188927$13013_Y + attribute \src "libresoc.v:188928.18-188928.117" + wire $and$libresoc.v:188928$13014_Y + attribute \src "libresoc.v:188933.18-188933.130" + wire $and$libresoc.v:188933$13019_Y + attribute \src "libresoc.v:188934.17-188934.123" + wire $and$libresoc.v:188934$13020_Y + attribute \src "libresoc.v:188935.18-188935.124" + wire width 6 $and$libresoc.v:188935$13021_Y + attribute \src "libresoc.v:188937.18-188937.116" + wire $and$libresoc.v:188937$13023_Y + attribute \src "libresoc.v:188938.18-188938.119" + wire $and$libresoc.v:188938$13024_Y + attribute \src "libresoc.v:188939.18-188939.120" + wire $and$libresoc.v:188939$13025_Y + attribute \src "libresoc.v:188940.18-188940.121" + wire $and$libresoc.v:188940$13026_Y + attribute \src "libresoc.v:188941.18-188941.121" + wire $and$libresoc.v:188941$13027_Y + attribute \src "libresoc.v:188942.18-188942.121" + wire $and$libresoc.v:188942$13028_Y + attribute \src "libresoc.v:188949.18-188949.134" + wire $and$libresoc.v:188949$13035_Y + attribute \src "libresoc.v:188923.18-188923.113" + wire $eq$libresoc.v:188923$13009_Y + attribute \src "libresoc.v:188925.18-188925.119" + wire $eq$libresoc.v:188925$13011_Y + attribute \src "libresoc.v:188884.17-188884.113" + wire width 6 $not$libresoc.v:188884$12970_Y + attribute \src "libresoc.v:188888.19-188888.115" + wire width 6 $not$libresoc.v:188888$12974_Y + attribute \src "libresoc.v:188907.18-188907.97" + wire $not$libresoc.v:188907$12993_Y + attribute \src "libresoc.v:188909.18-188909.99" + wire $not$libresoc.v:188909$12995_Y + attribute \src "libresoc.v:188912.18-188912.113" + wire width 6 $not$libresoc.v:188912$12998_Y + attribute \src "libresoc.v:188915.18-188915.106" + wire $not$libresoc.v:188915$13001_Y + attribute \src "libresoc.v:188920.18-188920.120" + wire $not$libresoc.v:188920$13006_Y + attribute \src "libresoc.v:188895.18-188895.118" + wire width 6 $or$libresoc.v:188895$12981_Y + attribute \src "libresoc.v:188919.18-188919.112" + wire $or$libresoc.v:188919$13005_Y + attribute \src "libresoc.v:188929.18-188929.122" + wire $or$libresoc.v:188929$13015_Y + attribute \src "libresoc.v:188930.18-188930.124" + wire $or$libresoc.v:188930$13016_Y + attribute \src "libresoc.v:188931.18-188931.194" + wire width 6 $or$libresoc.v:188931$13017_Y + attribute \src "libresoc.v:188932.18-188932.194" + wire width 6 $or$libresoc.v:188932$13018_Y + attribute \src "libresoc.v:188936.18-188936.120" + wire width 6 $or$libresoc.v:188936$13022_Y + attribute \src "libresoc.v:188901.17-188901.105" + wire $reduce_and$libresoc.v:188901$12987_Y + attribute \src "libresoc.v:188914.18-188914.106" + wire $reduce_or$libresoc.v:188914$13000_Y + attribute \src "libresoc.v:188917.18-188917.113" + wire $reduce_or$libresoc.v:188917$13003_Y + attribute \src "libresoc.v:188918.18-188918.112" + wire $reduce_or$libresoc.v:188918$13004_Y + attribute \src "libresoc.v:188943.18-188943.118" + wire width 64 $ternary$libresoc.v:188943$13029_Y + attribute \src "libresoc.v:188944.18-188944.118" + wire width 64 $ternary$libresoc.v:188944$13030_Y + attribute \src "libresoc.v:188945.18-188945.118" + wire width 64 $ternary$libresoc.v:188945$13031_Y + attribute \src "libresoc.v:188946.18-188946.118" + wire $ternary$libresoc.v:188946$13032_Y + attribute \src "libresoc.v:188947.18-188947.118" + wire width 2 $ternary$libresoc.v:188947$13033_Y + attribute \src "libresoc.v:188948.18-188948.118" + wire width 2 $ternary$libresoc.v:188948$13034_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -389300,9 +393309,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -389388,7 +393397,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:185969.7-185969.15" + attribute \src "libresoc.v:188273.7-188273.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -389599,7 +393608,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:186581$12787 + cell $and $and$libresoc.v:188885$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389607,10 +393616,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:186581$12787_Y + connect \Y $and$libresoc.v:188885$12971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186582$12788 + cell $and $and$libresoc.v:188886$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389618,10 +393627,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:186582$12788_Y + connect \Y $and$libresoc.v:188886$12972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186583$12789 + cell $and $and$libresoc.v:188887$12973 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389629,10 +393638,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:186583$12789_Y + connect \Y $and$libresoc.v:188887$12973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:186585$12791 + cell $and $and$libresoc.v:188889$12975 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389640,10 +393649,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:186585$12791_Y + connect \Y $and$libresoc.v:188889$12975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186586$12792 + cell $and $and$libresoc.v:188890$12976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389651,10 +393660,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186586$12792_Y + connect \Y $and$libresoc.v:188890$12976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186587$12793 + cell $and $and$libresoc.v:188891$12977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389662,10 +393671,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186587$12793_Y + connect \Y $and$libresoc.v:188891$12977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186588$12794 + cell $and $and$libresoc.v:188892$12978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389673,10 +393682,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186588$12794_Y + connect \Y $and$libresoc.v:188892$12978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186589$12795 + cell $and $and$libresoc.v:188893$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389684,10 +393693,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186589$12795_Y + connect \Y $and$libresoc.v:188893$12979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186590$12796 + cell $and $and$libresoc.v:188894$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389695,10 +393704,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186590$12796_Y + connect \Y $and$libresoc.v:188894$12980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:186592$12798 + cell $and $and$libresoc.v:188896$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389706,10 +393715,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:186592$12798_Y + connect \Y $and$libresoc.v:188896$12982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:186593$12799 + cell $and $and$libresoc.v:188897$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389717,10 +393726,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:186593$12799_Y + connect \Y $and$libresoc.v:188897$12983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:186594$12800 + cell $and $and$libresoc.v:188898$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389728,10 +393737,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186594$12800_Y + connect \Y $and$libresoc.v:188898$12984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186595$12801 + cell $and $and$libresoc.v:188899$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389739,10 +393748,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186595$12801_Y + connect \Y $and$libresoc.v:188899$12985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186596$12802 + cell $and $and$libresoc.v:188900$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389750,10 +393759,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186596$12802_Y + connect \Y $and$libresoc.v:188900$12986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186598$12804 + cell $and $and$libresoc.v:188902$12988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389761,10 +393770,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186598$12804_Y + connect \Y $and$libresoc.v:188902$12988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186599$12805 + cell $and $and$libresoc.v:188903$12989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389772,10 +393781,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186599$12805_Y + connect \Y $and$libresoc.v:188903$12989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186600$12806 + cell $and $and$libresoc.v:188904$12990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389783,10 +393792,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186600$12806_Y + connect \Y $and$libresoc.v:188904$12990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:186601$12807 + cell $and $and$libresoc.v:188905$12991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389794,10 +393803,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:186601$12807_Y + connect \Y $and$libresoc.v:188905$12991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:186602$12808 + cell $and $and$libresoc.v:188906$12992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389805,10 +393814,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:186602$12808_Y + connect \Y $and$libresoc.v:188906$12992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:186604$12810 + cell $and $and$libresoc.v:188908$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389816,10 +393825,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:186604$12810_Y + connect \Y $and$libresoc.v:188908$12994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:186606$12812 + cell $and $and$libresoc.v:188910$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389827,10 +393836,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:186606$12812_Y + connect \Y $and$libresoc.v:188910$12996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:186607$12813 + cell $and $and$libresoc.v:188911$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389838,10 +393847,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:186607$12813_Y + connect \Y $and$libresoc.v:188911$12997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:186609$12815 + cell $and $and$libresoc.v:188913$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389849,10 +393858,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:186609$12815_Y + connect \Y $and$libresoc.v:188913$12999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:186612$12818 + cell $and $and$libresoc.v:188916$13002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389860,10 +393869,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:186612$12818_Y + connect \Y $and$libresoc.v:188916$13002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:186617$12823 + cell $and $and$libresoc.v:188921$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389871,10 +393880,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:186617$12823_Y + connect \Y $and$libresoc.v:188921$13007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:186618$12824 + cell $and $and$libresoc.v:188922$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389882,10 +393891,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186618$12824_Y + connect \Y $and$libresoc.v:188922$13008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:186620$12826 + cell $and $and$libresoc.v:188924$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389893,10 +393902,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:186620$12826_Y + connect \Y $and$libresoc.v:188924$13010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186622$12828 + cell $and $and$libresoc.v:188926$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389904,10 +393913,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:186622$12828_Y + connect \Y $and$libresoc.v:188926$13012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186623$12829 + cell $and $and$libresoc.v:188927$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389915,10 +393924,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:186623$12829_Y + connect \Y $and$libresoc.v:188927$13013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:186624$12830 + cell $and $and$libresoc.v:188928$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389926,10 +393935,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:186624$12830_Y + connect \Y $and$libresoc.v:188928$13014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:186629$12835 + cell $and $and$libresoc.v:188933$13019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389937,10 +393946,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:186629$12835_Y + connect \Y $and$libresoc.v:188933$13019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:186630$12836 + cell $and $and$libresoc.v:188934$13020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389948,10 +393957,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:186630$12836_Y + connect \Y $and$libresoc.v:188934$13020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:186631$12837 + cell $and $and$libresoc.v:188935$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -389959,10 +393968,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:186631$12837_Y + connect \Y $and$libresoc.v:188935$13021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186633$12839 + cell $and $and$libresoc.v:188937$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389970,10 +393979,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186633$12839_Y + connect \Y $and$libresoc.v:188937$13023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186634$12840 + cell $and $and$libresoc.v:188938$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389981,10 +393990,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186634$12840_Y + connect \Y $and$libresoc.v:188938$13024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186635$12841 + cell $and $and$libresoc.v:188939$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389992,10 +394001,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186635$12841_Y + connect \Y $and$libresoc.v:188939$13025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186636$12842 + cell $and $and$libresoc.v:188940$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390003,10 +394012,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186636$12842_Y + connect \Y $and$libresoc.v:188940$13026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186637$12843 + cell $and $and$libresoc.v:188941$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390014,10 +394023,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186637$12843_Y + connect \Y $and$libresoc.v:188941$13027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:186638$12844 + cell $and $and$libresoc.v:188942$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390025,10 +394034,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:186638$12844_Y + connect \Y $and$libresoc.v:188942$13028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:186645$12851 + cell $and $and$libresoc.v:188949$13035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390036,10 +394045,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:186645$12851_Y + connect \Y $and$libresoc.v:188949$13035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:186619$12825 + cell $eq $eq$libresoc.v:188923$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390047,10 +394056,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:186619$12825_Y + connect \Y $eq$libresoc.v:188923$13009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:186621$12827 + cell $eq $eq$libresoc.v:188925$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390058,66 +394067,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:186621$12827_Y + connect \Y $eq$libresoc.v:188925$13011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:186580$12786 + cell $not $not$libresoc.v:188884$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:186580$12786_Y + connect \Y $not$libresoc.v:188884$12970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:186584$12790 + cell $not $not$libresoc.v:188888$12974 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:186584$12790_Y + connect \Y $not$libresoc.v:188888$12974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:186603$12809 + cell $not $not$libresoc.v:188907$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:186603$12809_Y + connect \Y $not$libresoc.v:188907$12993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:186605$12811 + cell $not $not$libresoc.v:188909$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:186605$12811_Y + connect \Y $not$libresoc.v:188909$12995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:186608$12814 + cell $not $not$libresoc.v:188912$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:186608$12814_Y + connect \Y $not$libresoc.v:188912$12998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:186611$12817 + cell $not $not$libresoc.v:188915$13001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:186611$12817_Y + connect \Y $not$libresoc.v:188915$13001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:186616$12822 + cell $not $not$libresoc.v:188920$13006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:186616$12822_Y + connect \Y $not$libresoc.v:188920$13006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:186591$12797 + cell $or $or$libresoc.v:188895$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390125,10 +394134,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:186591$12797_Y + connect \Y $or$libresoc.v:188895$12981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:186615$12821 + cell $or $or$libresoc.v:188919$13005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390136,10 +394145,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:186615$12821_Y + connect \Y $or$libresoc.v:188919$13005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:186625$12831 + cell $or $or$libresoc.v:188929$13015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390147,10 +394156,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:186625$12831_Y + connect \Y $or$libresoc.v:188929$13015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:186626$12832 + cell $or $or$libresoc.v:188930$13016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390158,10 +394167,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:186626$12832_Y + connect \Y $or$libresoc.v:188930$13016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:186627$12833 + cell $or $or$libresoc.v:188931$13017 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390169,10 +394178,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:186627$12833_Y + connect \Y $or$libresoc.v:188931$13017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:186628$12834 + cell $or $or$libresoc.v:188932$13018 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390180,10 +394189,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:186628$12834_Y + connect \Y $or$libresoc.v:188932$13018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:186632$12838 + cell $or $or$libresoc.v:188936$13022 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390191,90 +394200,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:186632$12838_Y + connect \Y $or$libresoc.v:188936$13022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:186597$12803 + cell $reduce_and $reduce_and$libresoc.v:188901$12987 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:186597$12803_Y + connect \Y $reduce_and$libresoc.v:188901$12987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:186610$12816 + cell $reduce_or $reduce_or$libresoc.v:188914$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:186610$12816_Y + connect \Y $reduce_or$libresoc.v:188914$13000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:186613$12819 + cell $reduce_or $reduce_or$libresoc.v:188917$13003 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:186613$12819_Y + connect \Y $reduce_or$libresoc.v:188917$13003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:186614$12820 + cell $reduce_or $reduce_or$libresoc.v:188918$13004 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:186614$12820_Y + connect \Y $reduce_or$libresoc.v:188918$13004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186639$12845 + cell $mux $ternary$libresoc.v:188943$13029 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:186639$12845_Y + connect \Y $ternary$libresoc.v:188943$13029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186640$12846 + cell $mux $ternary$libresoc.v:188944$13030 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:186640$12846_Y + connect \Y $ternary$libresoc.v:188944$13030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186641$12847 + cell $mux $ternary$libresoc.v:188945$13031 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:186641$12847_Y + connect \Y $ternary$libresoc.v:188945$13031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186642$12848 + cell $mux $ternary$libresoc.v:188946$13032 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:186642$12848_Y + connect \Y $ternary$libresoc.v:188946$13032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186643$12849 + cell $mux $ternary$libresoc.v:188947$13033 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:186643$12849_Y + connect \Y $ternary$libresoc.v:188947$13033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:186644$12850 + cell $mux $ternary$libresoc.v:188948$13034 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:186644$12850_Y + connect \Y $ternary$libresoc.v:188948$13034_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:186720.14-186726.4" + attribute \src "libresoc.v:189024.14-189030.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390283,7 +394292,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:186727.12-186756.4" + attribute \src "libresoc.v:189031.12-189060.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390315,7 +394324,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:186757.15-186763.4" + attribute \src "libresoc.v:189061.15-189067.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390324,7 +394333,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:186764.14-186770.4" + attribute \src "libresoc.v:189068.14-189074.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390333,7 +394342,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:186771.14-186777.4" + attribute \src "libresoc.v:189075.14-189081.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390342,7 +394351,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:186778.14-186784.4" + attribute \src "libresoc.v:189082.14-189088.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390351,7 +394360,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:186785.14-186790.4" + attribute \src "libresoc.v:189089.14-189094.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390359,7 +394368,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:186791.14-186797.4" + attribute \src "libresoc.v:189095.14-189101.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -390367,577 +394376,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:185969.7-185969.20" - process $proc$libresoc.v:185969$13010 + attribute \src "libresoc.v:188273.7-188273.20" + process $proc$libresoc.v:188273$13194 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186105.7-186105.24" - process $proc$libresoc.v:186105$13011 + attribute \src "libresoc.v:188409.7-188409.24" + process $proc$libresoc.v:188409$13195 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:186115.7-186115.26" - process $proc$libresoc.v:186115$13012 + attribute \src "libresoc.v:188419.7-188419.26" + process $proc$libresoc.v:188419$13196 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:186123.7-186123.25" - process $proc$libresoc.v:186123$13013 + attribute \src "libresoc.v:188427.7-188427.25" + process $proc$libresoc.v:188427$13197 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:186168.14-186168.49" - process $proc$libresoc.v:186168$13014 + attribute \src "libresoc.v:188472.14-188472.49" + process $proc$libresoc.v:188472$13198 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:186172.14-186172.43" - process $proc$libresoc.v:186172$13015 + attribute \src "libresoc.v:188476.14-188476.43" + process $proc$libresoc.v:188476$13199 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:186251.13-186251.47" - process $proc$libresoc.v:186251$13016 + attribute \src "libresoc.v:188555.13-188555.47" + process $proc$libresoc.v:188555$13200 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:186255.7-186255.39" - process $proc$libresoc.v:186255$13017 + attribute \src "libresoc.v:188559.7-188559.39" + process $proc$libresoc.v:188559$13201 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:186273.7-186273.27" - process $proc$libresoc.v:186273$13018 + attribute \src "libresoc.v:188577.7-188577.27" + process $proc$libresoc.v:188577$13202 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:186305.14-186305.47" - process $proc$libresoc.v:186305$13019 + attribute \src "libresoc.v:188609.14-188609.47" + process $proc$libresoc.v:188609$13203 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:186309.7-186309.27" - process $proc$libresoc.v:186309$13020 + attribute \src "libresoc.v:188613.7-188613.27" + process $proc$libresoc.v:188613$13204 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:186313.14-186313.50" - process $proc$libresoc.v:186313$13021 + attribute \src "libresoc.v:188617.14-188617.50" + process $proc$libresoc.v:188617$13205 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:186317.7-186317.30" - process $proc$libresoc.v:186317$13022 + attribute \src "libresoc.v:188621.7-188621.30" + process $proc$libresoc.v:188621$13206 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:186321.14-186321.51" - process $proc$libresoc.v:186321$13023 + attribute \src "libresoc.v:188625.14-188625.51" + process $proc$libresoc.v:188625$13207 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:186325.7-186325.31" - process $proc$libresoc.v:186325$13024 + attribute \src "libresoc.v:188629.7-188629.31" + process $proc$libresoc.v:188629$13208 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:186329.7-186329.29" - process $proc$libresoc.v:186329$13025 + attribute \src "libresoc.v:188633.7-188633.29" + process $proc$libresoc.v:188633$13209 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:186333.7-186333.32" - process $proc$libresoc.v:186333$13026 + attribute \src "libresoc.v:188637.7-188637.32" + process $proc$libresoc.v:188637$13210 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:186337.13-186337.35" - process $proc$libresoc.v:186337$13027 + attribute \src "libresoc.v:188641.13-188641.35" + process $proc$libresoc.v:188641$13211 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:186341.7-186341.32" - process $proc$libresoc.v:186341$13028 + attribute \src "libresoc.v:188645.7-188645.32" + process $proc$libresoc.v:188645$13212 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:186345.13-186345.35" - process $proc$libresoc.v:186345$13029 + attribute \src "libresoc.v:188649.13-188649.35" + process $proc$libresoc.v:188649$13213 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:186349.7-186349.32" - process $proc$libresoc.v:186349$13030 + attribute \src "libresoc.v:188653.7-188653.32" + process $proc$libresoc.v:188653$13214 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:186377.7-186377.25" - process $proc$libresoc.v:186377$13031 + attribute \src "libresoc.v:188681.7-188681.25" + process $proc$libresoc.v:188681$13215 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:186381.7-186381.25" - process $proc$libresoc.v:186381$13032 + attribute \src "libresoc.v:188685.7-188685.25" + process $proc$libresoc.v:188685$13216 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:186483.13-186483.31" - process $proc$libresoc.v:186483$13033 + attribute \src "libresoc.v:188787.13-188787.31" + process $proc$libresoc.v:188787$13217 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:186491.13-186491.32" - process $proc$libresoc.v:186491$13034 + attribute \src "libresoc.v:188795.13-188795.32" + process $proc$libresoc.v:188795$13218 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:186495.13-186495.32" - process $proc$libresoc.v:186495$13035 + attribute \src "libresoc.v:188799.13-188799.32" + process $proc$libresoc.v:188799$13219 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:186507.7-186507.26" - process $proc$libresoc.v:186507$13036 + attribute \src "libresoc.v:188811.7-188811.26" + process $proc$libresoc.v:188811$13220 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:186511.7-186511.26" - process $proc$libresoc.v:186511$13037 + attribute \src "libresoc.v:188815.7-188815.26" + process $proc$libresoc.v:188815$13221 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:186515.7-186515.25" - process $proc$libresoc.v:186515$13038 + attribute \src "libresoc.v:188819.7-188819.25" + process $proc$libresoc.v:188819$13222 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:186519.7-186519.25" - process $proc$libresoc.v:186519$13039 + attribute \src "libresoc.v:188823.7-188823.25" + process $proc$libresoc.v:188823$13223 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:186541.13-186541.32" - process $proc$libresoc.v:186541$13040 + attribute \src "libresoc.v:188845.13-188845.32" + process $proc$libresoc.v:188845$13224 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:186545.13-186545.32" - process $proc$libresoc.v:186545$13041 + attribute \src "libresoc.v:188849.13-188849.32" + process $proc$libresoc.v:188849$13225 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:186549.14-186549.43" - process $proc$libresoc.v:186549$13042 + attribute \src "libresoc.v:188853.14-188853.43" + process $proc$libresoc.v:188853$13226 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:186553.14-186553.43" - process $proc$libresoc.v:186553$13043 + attribute \src "libresoc.v:188857.14-188857.43" + process $proc$libresoc.v:188857$13227 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:186557.14-186557.43" - process $proc$libresoc.v:186557$13044 + attribute \src "libresoc.v:188861.14-188861.43" + process $proc$libresoc.v:188861$13228 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:186561.7-186561.20" - process $proc$libresoc.v:186561$13045 + attribute \src "libresoc.v:188865.7-188865.20" + process $proc$libresoc.v:188865$13229 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:186565.13-186565.26" - process $proc$libresoc.v:186565$13046 + attribute \src "libresoc.v:188869.13-188869.26" + process $proc$libresoc.v:188869$13230 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:186569.13-186569.26" - process $proc$libresoc.v:186569$13047 + attribute \src "libresoc.v:188873.13-188873.26" + process $proc$libresoc.v:188873$13231 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:186646.3-186647.39" - process $proc$libresoc.v:186646$12852 + attribute \src "libresoc.v:188950.3-188951.39" + process $proc$libresoc.v:188950$13036 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:186648.3-186649.43" - process $proc$libresoc.v:186648$12853 + attribute \src "libresoc.v:188952.3-188953.43" + process $proc$libresoc.v:188952$13037 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:186650.3-186651.29" - process $proc$libresoc.v:186650$12854 + attribute \src "libresoc.v:188954.3-188955.29" + process $proc$libresoc.v:188954$13038 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:186652.3-186653.29" - process $proc$libresoc.v:186652$12855 + attribute \src "libresoc.v:188956.3-188957.29" + process $proc$libresoc.v:188956$13039 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:186654.3-186655.29" - process $proc$libresoc.v:186654$12856 + attribute \src "libresoc.v:188958.3-188959.29" + process $proc$libresoc.v:188958$13040 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:186656.3-186657.29" - process $proc$libresoc.v:186656$12857 + attribute \src "libresoc.v:188960.3-188961.29" + process $proc$libresoc.v:188960$13041 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:186658.3-186659.29" - process $proc$libresoc.v:186658$12858 + attribute \src "libresoc.v:188962.3-188963.29" + process $proc$libresoc.v:188962$13042 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:186660.3-186661.29" - process $proc$libresoc.v:186660$12859 + attribute \src "libresoc.v:188964.3-188965.29" + process $proc$libresoc.v:188964$13043 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:186662.3-186663.47" - process $proc$libresoc.v:186662$12860 + attribute \src "libresoc.v:188966.3-188967.47" + process $proc$libresoc.v:188966$13044 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:186664.3-186665.53" - process $proc$libresoc.v:186664$12861 + attribute \src "libresoc.v:188968.3-188969.53" + process $proc$libresoc.v:188968$13045 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:186666.3-186667.47" - process $proc$libresoc.v:186666$12862 + attribute \src "libresoc.v:188970.3-188971.47" + process $proc$libresoc.v:188970$13046 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:186668.3-186669.53" - process $proc$libresoc.v:186668$12863 + attribute \src "libresoc.v:188972.3-188973.53" + process $proc$libresoc.v:188972$13047 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:186670.3-186671.47" - process $proc$libresoc.v:186670$12864 + attribute \src "libresoc.v:188974.3-188975.47" + process $proc$libresoc.v:188974$13048 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:186672.3-186673.53" - process $proc$libresoc.v:186672$12865 + attribute \src "libresoc.v:188976.3-188977.53" + process $proc$libresoc.v:188976$13049 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:186674.3-186675.45" - process $proc$libresoc.v:186674$12866 + attribute \src "libresoc.v:188978.3-188979.45" + process $proc$libresoc.v:188978$13050 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:186676.3-186677.51" - process $proc$libresoc.v:186676$12867 + attribute \src "libresoc.v:188980.3-188981.51" + process $proc$libresoc.v:188980$13051 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:186678.3-186679.43" - process $proc$libresoc.v:186678$12868 + attribute \src "libresoc.v:188982.3-188983.43" + process $proc$libresoc.v:188982$13052 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:186680.3-186681.49" - process $proc$libresoc.v:186680$12869 + attribute \src "libresoc.v:188984.3-188985.49" + process $proc$libresoc.v:188984$13053 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:186682.3-186683.37" - process $proc$libresoc.v:186682$12870 + attribute \src "libresoc.v:188986.3-188987.37" + process $proc$libresoc.v:188986$13054 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:186684.3-186685.43" - process $proc$libresoc.v:186684$12871 + attribute \src "libresoc.v:188988.3-188989.43" + process $proc$libresoc.v:188988$13055 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:186686.3-186687.69" - process $proc$libresoc.v:186686$12872 + attribute \src "libresoc.v:188990.3-188991.69" + process $proc$libresoc.v:188990$13056 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:186688.3-186689.65" - process $proc$libresoc.v:186688$12873 + attribute \src "libresoc.v:188992.3-188993.65" + process $proc$libresoc.v:188992$13057 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:186690.3-186691.59" - process $proc$libresoc.v:186690$12874 + attribute \src "libresoc.v:188994.3-188995.59" + process $proc$libresoc.v:188994$13058 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:186692.3-186693.67" - process $proc$libresoc.v:186692$12875 + attribute \src "libresoc.v:188996.3-188997.67" + process $proc$libresoc.v:188996$13059 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:186694.3-186695.39" - process $proc$libresoc.v:186694$12876 + attribute \src "libresoc.v:188998.3-188999.39" + process $proc$libresoc.v:188998$13060 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:186696.3-186697.39" - process $proc$libresoc.v:186696$12877 + attribute \src "libresoc.v:189000.3-189001.39" + process $proc$libresoc.v:189000$13061 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:186698.3-186699.39" - process $proc$libresoc.v:186698$12878 + attribute \src "libresoc.v:189002.3-189003.39" + process $proc$libresoc.v:189002$13062 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:186700.3-186701.39" - process $proc$libresoc.v:186700$12879 + attribute \src "libresoc.v:189004.3-189005.39" + process $proc$libresoc.v:189004$13063 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:186702.3-186703.39" - process $proc$libresoc.v:186702$12880 + attribute \src "libresoc.v:189006.3-189007.39" + process $proc$libresoc.v:189006$13064 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:186704.3-186705.39" - process $proc$libresoc.v:186704$12881 + attribute \src "libresoc.v:189008.3-189009.39" + process $proc$libresoc.v:189008$13065 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:186706.3-186707.39" - process $proc$libresoc.v:186706$12882 + attribute \src "libresoc.v:189010.3-189011.39" + process $proc$libresoc.v:189010$13066 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:186708.3-186709.39" - process $proc$libresoc.v:186708$12883 + attribute \src "libresoc.v:189012.3-189013.39" + process $proc$libresoc.v:189012$13067 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:186710.3-186711.41" - process $proc$libresoc.v:186710$12884 + attribute \src "libresoc.v:189014.3-189015.41" + process $proc$libresoc.v:189014$13068 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:186712.3-186713.41" - process $proc$libresoc.v:186712$12885 + attribute \src "libresoc.v:189016.3-189017.41" + process $proc$libresoc.v:189016$13069 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:186714.3-186715.37" - process $proc$libresoc.v:186714$12886 + attribute \src "libresoc.v:189018.3-189019.37" + process $proc$libresoc.v:189018$13070 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:186716.3-186717.40" - process $proc$libresoc.v:186716$12887 + attribute \src "libresoc.v:189020.3-189021.40" + process $proc$libresoc.v:189020$13071 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:186718.3-186719.25" - process $proc$libresoc.v:186718$12888 + attribute \src "libresoc.v:189022.3-189023.25" + process $proc$libresoc.v:189022$13072 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:186798.3-186807.6" - process $proc$libresoc.v:186798$12889 + attribute \src "libresoc.v:189102.3-189111.6" + process $proc$libresoc.v:189102$13073 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:186799.5-186799.29" + attribute \src "libresoc.v:189103.5-189103.29" switch \initial - attribute \src "libresoc.v:186799.9-186799.17" + attribute \src "libresoc.v:189103.9-189103.17" case 1'1 case end @@ -390953,14 +394962,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:186808.3-186816.6" - process $proc$libresoc.v:186808$12890 + attribute \src "libresoc.v:189112.3-189120.6" + process $proc$libresoc.v:189112$13074 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12891 $1\rok_l_s_rdok$next[0:0]$12892 - attribute \src "libresoc.v:186809.5-186809.29" + assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 + attribute \src "libresoc.v:189113.5-189113.29" switch \initial - attribute \src "libresoc.v:186809.9-186809.17" + attribute \src "libresoc.v:189113.9-189113.17" case 1'1 case end @@ -390969,21 +394978,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12892 1'0 + assign $1\rok_l_s_rdok$next[0:0]$13076 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12892 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$13076 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12891 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 end - attribute \src "libresoc.v:186817.3-186825.6" - process $proc$libresoc.v:186817$12893 + attribute \src "libresoc.v:189121.3-189129.6" + process $proc$libresoc.v:189121$13077 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12894 $1\rok_l_r_rdok$next[0:0]$12895 - attribute \src "libresoc.v:186818.5-186818.29" + assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 + attribute \src "libresoc.v:189122.5-189122.29" switch \initial - attribute \src "libresoc.v:186818.9-186818.17" + attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end @@ -390992,21 +395001,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12895 1'1 + assign $1\rok_l_r_rdok$next[0:0]$13079 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12895 \$68 + assign $1\rok_l_r_rdok$next[0:0]$13079 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12894 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 end - attribute \src "libresoc.v:186826.3-186834.6" - process $proc$libresoc.v:186826$12896 + attribute \src "libresoc.v:189130.3-189138.6" + process $proc$libresoc.v:189130$13080 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12897 $1\rst_l_s_rst$next[0:0]$12898 - attribute \src "libresoc.v:186827.5-186827.29" + assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 + attribute \src "libresoc.v:189131.5-189131.29" switch \initial - attribute \src "libresoc.v:186827.9-186827.17" + attribute \src "libresoc.v:189131.9-189131.17" case 1'1 case end @@ -391015,21 +395024,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12898 1'0 + assign $1\rst_l_s_rst$next[0:0]$13082 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12898 \all_rd + assign $1\rst_l_s_rst$next[0:0]$13082 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12897 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 end - attribute \src "libresoc.v:186835.3-186843.6" - process $proc$libresoc.v:186835$12899 + attribute \src "libresoc.v:189139.3-189147.6" + process $proc$libresoc.v:189139$13083 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12900 $1\rst_l_r_rst$next[0:0]$12901 - attribute \src "libresoc.v:186836.5-186836.29" + assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 + attribute \src "libresoc.v:189140.5-189140.29" switch \initial - attribute \src "libresoc.v:186836.9-186836.17" + attribute \src "libresoc.v:189140.9-189140.17" case 1'1 case end @@ -391038,21 +395047,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12901 1'1 + assign $1\rst_l_r_rst$next[0:0]$13085 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12901 \rst_r + assign $1\rst_l_r_rst$next[0:0]$13085 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12900 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 end - attribute \src "libresoc.v:186844.3-186852.6" - process $proc$libresoc.v:186844$12902 + attribute \src "libresoc.v:189148.3-189156.6" + process $proc$libresoc.v:189148$13086 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12903 $1\opc_l_s_opc$next[0:0]$12904 - attribute \src "libresoc.v:186845.5-186845.29" + assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 + attribute \src "libresoc.v:189149.5-189149.29" switch \initial - attribute \src "libresoc.v:186845.9-186845.17" + attribute \src "libresoc.v:189149.9-189149.17" case 1'1 case end @@ -391061,21 +395070,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12904 1'0 + assign $1\opc_l_s_opc$next[0:0]$13088 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12904 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$13088 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12903 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 end - attribute \src "libresoc.v:186853.3-186861.6" - process $proc$libresoc.v:186853$12905 + attribute \src "libresoc.v:189157.3-189165.6" + process $proc$libresoc.v:189157$13089 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12906 $1\opc_l_r_opc$next[0:0]$12907 - attribute \src "libresoc.v:186854.5-186854.29" + assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 + attribute \src "libresoc.v:189158.5-189158.29" switch \initial - attribute \src "libresoc.v:186854.9-186854.17" + attribute \src "libresoc.v:189158.9-189158.17" case 1'1 case end @@ -391084,21 +395093,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12907 1'1 + assign $1\opc_l_r_opc$next[0:0]$13091 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12907 \req_done + assign $1\opc_l_r_opc$next[0:0]$13091 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12906 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 end - attribute \src "libresoc.v:186862.3-186870.6" - process $proc$libresoc.v:186862$12908 + attribute \src "libresoc.v:189166.3-189174.6" + process $proc$libresoc.v:189166$13092 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12909 $1\src_l_s_src$next[5:0]$12910 - attribute \src "libresoc.v:186863.5-186863.29" + assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 + attribute \src "libresoc.v:189167.5-189167.29" switch \initial - attribute \src "libresoc.v:186863.9-186863.17" + attribute \src "libresoc.v:189167.9-189167.17" case 1'1 case end @@ -391107,21 +395116,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12910 6'000000 + assign $1\src_l_s_src$next[5:0]$13094 6'000000 case - assign $1\src_l_s_src$next[5:0]$12910 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$13094 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12909 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 end - attribute \src "libresoc.v:186871.3-186879.6" - process $proc$libresoc.v:186871$12911 + attribute \src "libresoc.v:189175.3-189183.6" + process $proc$libresoc.v:189175$13095 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12912 $1\src_l_r_src$next[5:0]$12913 - attribute \src "libresoc.v:186872.5-186872.29" + assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 + attribute \src "libresoc.v:189176.5-189176.29" switch \initial - attribute \src "libresoc.v:186872.9-186872.17" + attribute \src "libresoc.v:189176.9-189176.17" case 1'1 case end @@ -391130,21 +395139,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12913 6'111111 + assign $1\src_l_r_src$next[5:0]$13097 6'111111 case - assign $1\src_l_r_src$next[5:0]$12913 \reset_r + assign $1\src_l_r_src$next[5:0]$13097 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12912 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 end - attribute \src "libresoc.v:186880.3-186888.6" - process $proc$libresoc.v:186880$12914 + attribute \src "libresoc.v:189184.3-189192.6" + process $proc$libresoc.v:189184$13098 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12915 $1\req_l_s_req$next[5:0]$12916 - attribute \src "libresoc.v:186881.5-186881.29" + assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 + attribute \src "libresoc.v:189185.5-189185.29" switch \initial - attribute \src "libresoc.v:186881.9-186881.17" + attribute \src "libresoc.v:189185.9-189185.17" case 1'1 case end @@ -391153,21 +395162,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12916 6'000000 + assign $1\req_l_s_req$next[5:0]$13100 6'000000 case - assign $1\req_l_s_req$next[5:0]$12916 \$70 + assign $1\req_l_s_req$next[5:0]$13100 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12915 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 end - attribute \src "libresoc.v:186889.3-186897.6" - process $proc$libresoc.v:186889$12917 + attribute \src "libresoc.v:189193.3-189201.6" + process $proc$libresoc.v:189193$13101 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12918 $1\req_l_r_req$next[5:0]$12919 - attribute \src "libresoc.v:186890.5-186890.29" + assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 + attribute \src "libresoc.v:189194.5-189194.29" switch \initial - attribute \src "libresoc.v:186890.9-186890.17" + attribute \src "libresoc.v:189194.9-189194.17" case 1'1 case end @@ -391176,15 +395185,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12919 6'111111 + assign $1\req_l_r_req$next[5:0]$13103 6'111111 case - assign $1\req_l_r_req$next[5:0]$12919 \$72 + assign $1\req_l_r_req$next[5:0]$13103 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12918 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 end - attribute \src "libresoc.v:186898.3-186910.6" - process $proc$libresoc.v:186898$12920 + attribute \src "libresoc.v:189202.3-189214.6" + process $proc$libresoc.v:189202$13104 assign { } { } assign { } { } assign { } { } @@ -391193,13 +395202,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12922 $1\alu_spr0_spr_op__insn$next[31:0]$12926 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 - attribute \src "libresoc.v:186899.5-186899.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 + assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 + attribute \src "libresoc.v:189203.5-189203.29" switch \initial - attribute \src "libresoc.v:186899.9-186899.17" + attribute \src "libresoc.v:189203.9-189203.17" case 1'1 case end @@ -391211,33 +395220,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 $1\alu_spr0_spr_op__insn$next[31:0]$12926 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 $1\alu_spr0_spr_op__insn$next[31:0]$13110 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12925 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12926 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12927 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12928 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$13110 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12921 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12922 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12923 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12924 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13106 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 end - attribute \src "libresoc.v:186911.3-186932.6" - process $proc$libresoc.v:186911$12929 + attribute \src "libresoc.v:189215.3-189236.6" + process $proc$libresoc.v:189215$13113 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12930 $2\data_r0__o$next[63:0]$12934 + assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12931 $3\data_r0__o_ok$next[0:0]$12936 - attribute \src "libresoc.v:186912.5-186912.29" + assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 + attribute \src "libresoc.v:189216.5-189216.29" switch \initial - attribute \src "libresoc.v:186912.9-186912.17" + attribute \src "libresoc.v:189216.9-189216.17" case 1'1 case end @@ -391247,10 +395256,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12933 $1\data_r0__o$next[63:0]$12932 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$13117 $1\data_r0__o$next[63:0]$13116 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12932 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12933 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$13116 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13117 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391258,38 +395267,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12935 $2\data_r0__o$next[63:0]$12934 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$13119 $2\data_r0__o$next[63:0]$13118 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12934 $1\data_r0__o$next[63:0]$12932 - assign $2\data_r0__o_ok$next[0:0]$12935 $1\data_r0__o_ok$next[0:0]$12933 + assign $2\data_r0__o$next[63:0]$13118 $1\data_r0__o$next[63:0]$13116 + assign $2\data_r0__o_ok$next[0:0]$13119 $1\data_r0__o_ok$next[0:0]$13117 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12936 1'0 + assign $3\data_r0__o_ok$next[0:0]$13120 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12936 $2\data_r0__o_ok$next[0:0]$12935 + assign $3\data_r0__o_ok$next[0:0]$13120 $2\data_r0__o_ok$next[0:0]$13119 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12930 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12931 + update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 end - attribute \src "libresoc.v:186933.3-186954.6" - process $proc$libresoc.v:186933$12937 + attribute \src "libresoc.v:189237.3-189258.6" + process $proc$libresoc.v:189237$13121 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12938 $2\data_r1__spr1$next[63:0]$12942 + assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12939 $3\data_r1__spr1_ok$next[0:0]$12944 - attribute \src "libresoc.v:186934.5-186934.29" + assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 + attribute \src "libresoc.v:189238.5-189238.29" switch \initial - attribute \src "libresoc.v:186934.9-186934.17" + attribute \src "libresoc.v:189238.9-189238.17" case 1'1 case end @@ -391299,10 +395308,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12941 $1\data_r1__spr1$next[63:0]$12940 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$13125 $1\data_r1__spr1$next[63:0]$13124 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12940 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12941 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$13124 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$13125 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391310,38 +395319,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12943 $2\data_r1__spr1$next[63:0]$12942 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$13127 $2\data_r1__spr1$next[63:0]$13126 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12942 $1\data_r1__spr1$next[63:0]$12940 - assign $2\data_r1__spr1_ok$next[0:0]$12943 $1\data_r1__spr1_ok$next[0:0]$12941 + assign $2\data_r1__spr1$next[63:0]$13126 $1\data_r1__spr1$next[63:0]$13124 + assign $2\data_r1__spr1_ok$next[0:0]$13127 $1\data_r1__spr1_ok$next[0:0]$13125 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12944 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$13128 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12944 $2\data_r1__spr1_ok$next[0:0]$12943 + assign $3\data_r1__spr1_ok$next[0:0]$13128 $2\data_r1__spr1_ok$next[0:0]$13127 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12938 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12939 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 end - attribute \src "libresoc.v:186955.3-186976.6" - process $proc$libresoc.v:186955$12945 + attribute \src "libresoc.v:189259.3-189280.6" + process $proc$libresoc.v:189259$13129 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12946 $2\data_r2__fast1$next[63:0]$12950 + assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12947 $3\data_r2__fast1_ok$next[0:0]$12952 - attribute \src "libresoc.v:186956.5-186956.29" + assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 + attribute \src "libresoc.v:189260.5-189260.29" switch \initial - attribute \src "libresoc.v:186956.9-186956.17" + attribute \src "libresoc.v:189260.9-189260.17" case 1'1 case end @@ -391351,10 +395360,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12949 $1\data_r2__fast1$next[63:0]$12948 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$13133 $1\data_r2__fast1$next[63:0]$13132 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12948 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12949 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$13132 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$13133 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391362,38 +395371,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12951 $2\data_r2__fast1$next[63:0]$12950 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$13135 $2\data_r2__fast1$next[63:0]$13134 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12950 $1\data_r2__fast1$next[63:0]$12948 - assign $2\data_r2__fast1_ok$next[0:0]$12951 $1\data_r2__fast1_ok$next[0:0]$12949 + assign $2\data_r2__fast1$next[63:0]$13134 $1\data_r2__fast1$next[63:0]$13132 + assign $2\data_r2__fast1_ok$next[0:0]$13135 $1\data_r2__fast1_ok$next[0:0]$13133 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12952 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$13136 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12952 $2\data_r2__fast1_ok$next[0:0]$12951 + assign $3\data_r2__fast1_ok$next[0:0]$13136 $2\data_r2__fast1_ok$next[0:0]$13135 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12946 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12947 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 end - attribute \src "libresoc.v:186977.3-186998.6" - process $proc$libresoc.v:186977$12953 + attribute \src "libresoc.v:189281.3-189302.6" + process $proc$libresoc.v:189281$13137 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12954 $2\data_r3__xer_so$next[0:0]$12958 + assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12955 $3\data_r3__xer_so_ok$next[0:0]$12960 - attribute \src "libresoc.v:186978.5-186978.29" + assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 + attribute \src "libresoc.v:189282.5-189282.29" switch \initial - attribute \src "libresoc.v:186978.9-186978.17" + attribute \src "libresoc.v:189282.9-189282.17" case 1'1 case end @@ -391403,10 +395412,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12957 $1\data_r3__xer_so$next[0:0]$12956 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$13141 $1\data_r3__xer_so$next[0:0]$13140 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12956 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12957 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$13140 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$13141 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391414,38 +395423,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12959 $2\data_r3__xer_so$next[0:0]$12958 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$13143 $2\data_r3__xer_so$next[0:0]$13142 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12958 $1\data_r3__xer_so$next[0:0]$12956 - assign $2\data_r3__xer_so_ok$next[0:0]$12959 $1\data_r3__xer_so_ok$next[0:0]$12957 + assign $2\data_r3__xer_so$next[0:0]$13142 $1\data_r3__xer_so$next[0:0]$13140 + assign $2\data_r3__xer_so_ok$next[0:0]$13143 $1\data_r3__xer_so_ok$next[0:0]$13141 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12960 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$13144 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12960 $2\data_r3__xer_so_ok$next[0:0]$12959 + assign $3\data_r3__xer_so_ok$next[0:0]$13144 $2\data_r3__xer_so_ok$next[0:0]$13143 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12954 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12955 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 end - attribute \src "libresoc.v:186999.3-187020.6" - process $proc$libresoc.v:186999$12961 + attribute \src "libresoc.v:189303.3-189324.6" + process $proc$libresoc.v:189303$13145 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12962 $2\data_r4__xer_ov$next[1:0]$12966 + assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12963 $3\data_r4__xer_ov_ok$next[0:0]$12968 - attribute \src "libresoc.v:187000.5-187000.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 + attribute \src "libresoc.v:189304.5-189304.29" switch \initial - attribute \src "libresoc.v:187000.9-187000.17" + attribute \src "libresoc.v:189304.9-189304.17" case 1'1 case end @@ -391455,10 +395464,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12965 $1\data_r4__xer_ov$next[1:0]$12964 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13149 $1\data_r4__xer_ov$next[1:0]$13148 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12964 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12965 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$13148 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13149 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391466,38 +395475,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12967 $2\data_r4__xer_ov$next[1:0]$12966 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$13151 $2\data_r4__xer_ov$next[1:0]$13150 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12966 $1\data_r4__xer_ov$next[1:0]$12964 - assign $2\data_r4__xer_ov_ok$next[0:0]$12967 $1\data_r4__xer_ov_ok$next[0:0]$12965 + assign $2\data_r4__xer_ov$next[1:0]$13150 $1\data_r4__xer_ov$next[1:0]$13148 + assign $2\data_r4__xer_ov_ok$next[0:0]$13151 $1\data_r4__xer_ov_ok$next[0:0]$13149 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12968 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12968 $2\data_r4__xer_ov_ok$next[0:0]$12967 + assign $3\data_r4__xer_ov_ok$next[0:0]$13152 $2\data_r4__xer_ov_ok$next[0:0]$13151 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12962 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12963 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 end - attribute \src "libresoc.v:187021.3-187042.6" - process $proc$libresoc.v:187021$12969 + attribute \src "libresoc.v:189325.3-189346.6" + process $proc$libresoc.v:189325$13153 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12970 $2\data_r5__xer_ca$next[1:0]$12974 + assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12971 $3\data_r5__xer_ca_ok$next[0:0]$12976 - attribute \src "libresoc.v:187022.5-187022.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 + attribute \src "libresoc.v:189326.5-189326.29" switch \initial - attribute \src "libresoc.v:187022.9-187022.17" + attribute \src "libresoc.v:189326.9-189326.17" case 1'1 case end @@ -391507,10 +395516,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12973 $1\data_r5__xer_ca$next[1:0]$12972 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13157 $1\data_r5__xer_ca$next[1:0]$13156 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12972 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12973 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$13156 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13157 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -391518,32 +395527,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12975 $2\data_r5__xer_ca$next[1:0]$12974 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$13159 $2\data_r5__xer_ca$next[1:0]$13158 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12974 $1\data_r5__xer_ca$next[1:0]$12972 - assign $2\data_r5__xer_ca_ok$next[0:0]$12975 $1\data_r5__xer_ca_ok$next[0:0]$12973 + assign $2\data_r5__xer_ca$next[1:0]$13158 $1\data_r5__xer_ca$next[1:0]$13156 + assign $2\data_r5__xer_ca_ok$next[0:0]$13159 $1\data_r5__xer_ca_ok$next[0:0]$13157 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12976 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12976 $2\data_r5__xer_ca_ok$next[0:0]$12975 + assign $3\data_r5__xer_ca_ok$next[0:0]$13160 $2\data_r5__xer_ca_ok$next[0:0]$13159 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12970 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12971 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 end - attribute \src "libresoc.v:187043.3-187052.6" - process $proc$libresoc.v:187043$12977 + attribute \src "libresoc.v:189347.3-189356.6" + process $proc$libresoc.v:189347$13161 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12978 $1\src_r0$next[63:0]$12979 - attribute \src "libresoc.v:187044.5-187044.29" + assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 + attribute \src "libresoc.v:189348.5-189348.29" switch \initial - attribute \src "libresoc.v:187044.9-187044.17" + attribute \src "libresoc.v:189348.9-189348.17" case 1'1 case end @@ -391552,21 +395561,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12979 \src1_i + assign $1\src_r0$next[63:0]$13163 \src1_i case - assign $1\src_r0$next[63:0]$12979 \src_r0 + assign $1\src_r0$next[63:0]$13163 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12978 + update \src_r0$next $0\src_r0$next[63:0]$13162 end - attribute \src "libresoc.v:187053.3-187062.6" - process $proc$libresoc.v:187053$12980 + attribute \src "libresoc.v:189357.3-189366.6" + process $proc$libresoc.v:189357$13164 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12981 $1\src_r1$next[63:0]$12982 - attribute \src "libresoc.v:187054.5-187054.29" + assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 + attribute \src "libresoc.v:189358.5-189358.29" switch \initial - attribute \src "libresoc.v:187054.9-187054.17" + attribute \src "libresoc.v:189358.9-189358.17" case 1'1 case end @@ -391575,21 +395584,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12982 \src2_i + assign $1\src_r1$next[63:0]$13166 \src2_i case - assign $1\src_r1$next[63:0]$12982 \src_r1 + assign $1\src_r1$next[63:0]$13166 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12981 + update \src_r1$next $0\src_r1$next[63:0]$13165 end - attribute \src "libresoc.v:187063.3-187072.6" - process $proc$libresoc.v:187063$12983 + attribute \src "libresoc.v:189367.3-189376.6" + process $proc$libresoc.v:189367$13167 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12984 $1\src_r2$next[63:0]$12985 - attribute \src "libresoc.v:187064.5-187064.29" + assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 + attribute \src "libresoc.v:189368.5-189368.29" switch \initial - attribute \src "libresoc.v:187064.9-187064.17" + attribute \src "libresoc.v:189368.9-189368.17" case 1'1 case end @@ -391598,21 +395607,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12985 \src3_i + assign $1\src_r2$next[63:0]$13169 \src3_i case - assign $1\src_r2$next[63:0]$12985 \src_r2 + assign $1\src_r2$next[63:0]$13169 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12984 + update \src_r2$next $0\src_r2$next[63:0]$13168 end - attribute \src "libresoc.v:187073.3-187082.6" - process $proc$libresoc.v:187073$12986 + attribute \src "libresoc.v:189377.3-189386.6" + process $proc$libresoc.v:189377$13170 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12987 $1\src_r3$next[0:0]$12988 - attribute \src "libresoc.v:187074.5-187074.29" + assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 + attribute \src "libresoc.v:189378.5-189378.29" switch \initial - attribute \src "libresoc.v:187074.9-187074.17" + attribute \src "libresoc.v:189378.9-189378.17" case 1'1 case end @@ -391621,21 +395630,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12988 \src4_i + assign $1\src_r3$next[0:0]$13172 \src4_i case - assign $1\src_r3$next[0:0]$12988 \src_r3 + assign $1\src_r3$next[0:0]$13172 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12987 + update \src_r3$next $0\src_r3$next[0:0]$13171 end - attribute \src "libresoc.v:187083.3-187092.6" - process $proc$libresoc.v:187083$12989 + attribute \src "libresoc.v:189387.3-189396.6" + process $proc$libresoc.v:189387$13173 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12990 $1\src_r4$next[1:0]$12991 - attribute \src "libresoc.v:187084.5-187084.29" + assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 + attribute \src "libresoc.v:189388.5-189388.29" switch \initial - attribute \src "libresoc.v:187084.9-187084.17" + attribute \src "libresoc.v:189388.9-189388.17" case 1'1 case end @@ -391644,21 +395653,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12991 \src5_i + assign $1\src_r4$next[1:0]$13175 \src5_i case - assign $1\src_r4$next[1:0]$12991 \src_r4 + assign $1\src_r4$next[1:0]$13175 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12990 + update \src_r4$next $0\src_r4$next[1:0]$13174 end - attribute \src "libresoc.v:187093.3-187102.6" - process $proc$libresoc.v:187093$12992 + attribute \src "libresoc.v:189397.3-189406.6" + process $proc$libresoc.v:189397$13176 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12993 $1\src_r5$next[1:0]$12994 - attribute \src "libresoc.v:187094.5-187094.29" + assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 + attribute \src "libresoc.v:189398.5-189398.29" switch \initial - attribute \src "libresoc.v:187094.9-187094.17" + attribute \src "libresoc.v:189398.9-189398.17" case 1'1 case end @@ -391667,21 +395676,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12994 \src6_i + assign $1\src_r5$next[1:0]$13178 \src6_i case - assign $1\src_r5$next[1:0]$12994 \src_r5 + assign $1\src_r5$next[1:0]$13178 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12993 + update \src_r5$next $0\src_r5$next[1:0]$13177 end - attribute \src "libresoc.v:187103.3-187111.6" - process $proc$libresoc.v:187103$12995 + attribute \src "libresoc.v:189407.3-189415.6" + process $proc$libresoc.v:189407$13179 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12996 $1\alui_l_r_alui$next[0:0]$12997 - attribute \src "libresoc.v:187104.5-187104.29" + assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 + attribute \src "libresoc.v:189408.5-189408.29" switch \initial - attribute \src "libresoc.v:187104.9-187104.17" + attribute \src "libresoc.v:189408.9-189408.17" case 1'1 case end @@ -391690,21 +395699,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12997 1'1 + assign $1\alui_l_r_alui$next[0:0]$13181 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12997 \$98 + assign $1\alui_l_r_alui$next[0:0]$13181 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12996 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 end - attribute \src "libresoc.v:187112.3-187120.6" - process $proc$libresoc.v:187112$12998 + attribute \src "libresoc.v:189416.3-189424.6" + process $proc$libresoc.v:189416$13182 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12999 $1\alu_l_r_alu$next[0:0]$13000 - attribute \src "libresoc.v:187113.5-187113.29" + assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 + attribute \src "libresoc.v:189417.5-189417.29" switch \initial - attribute \src "libresoc.v:187113.9-187113.17" + attribute \src "libresoc.v:189417.9-189417.17" case 1'1 case end @@ -391713,21 +395722,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13000 1'1 + assign $1\alu_l_r_alu$next[0:0]$13184 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13000 \$100 + assign $1\alu_l_r_alu$next[0:0]$13184 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12999 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 end - attribute \src "libresoc.v:187121.3-187130.6" - process $proc$libresoc.v:187121$13001 + attribute \src "libresoc.v:189425.3-189434.6" + process $proc$libresoc.v:189425$13185 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:187122.5-187122.29" + attribute \src "libresoc.v:189426.5-189426.29" switch \initial - attribute \src "libresoc.v:187122.9-187122.17" + attribute \src "libresoc.v:189426.9-189426.17" case 1'1 case end @@ -391743,14 +395752,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:187131.3-187140.6" - process $proc$libresoc.v:187131$13002 + attribute \src "libresoc.v:189435.3-189444.6" + process $proc$libresoc.v:189435$13186 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:187132.5-187132.29" + attribute \src "libresoc.v:189436.5-189436.29" switch \initial - attribute \src "libresoc.v:187132.9-187132.17" + attribute \src "libresoc.v:189436.9-189436.17" case 1'1 case end @@ -391766,14 +395775,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:187141.3-187150.6" - process $proc$libresoc.v:187141$13003 + attribute \src "libresoc.v:189445.3-189454.6" + process $proc$libresoc.v:189445$13187 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:187142.5-187142.29" + attribute \src "libresoc.v:189446.5-189446.29" switch \initial - attribute \src "libresoc.v:187142.9-187142.17" + attribute \src "libresoc.v:189446.9-189446.17" case 1'1 case end @@ -391789,14 +395798,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:187151.3-187160.6" - process $proc$libresoc.v:187151$13004 + attribute \src "libresoc.v:189455.3-189464.6" + process $proc$libresoc.v:189455$13188 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:187152.5-187152.29" + attribute \src "libresoc.v:189456.5-189456.29" switch \initial - attribute \src "libresoc.v:187152.9-187152.17" + attribute \src "libresoc.v:189456.9-189456.17" case 1'1 case end @@ -391812,14 +395821,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:187161.3-187170.6" - process $proc$libresoc.v:187161$13005 + attribute \src "libresoc.v:189465.3-189474.6" + process $proc$libresoc.v:189465$13189 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:187162.5-187162.29" + attribute \src "libresoc.v:189466.5-189466.29" switch \initial - attribute \src "libresoc.v:187162.9-187162.17" + attribute \src "libresoc.v:189466.9-189466.17" case 1'1 case end @@ -391835,14 +395844,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:187171.3-187180.6" - process $proc$libresoc.v:187171$13006 + attribute \src "libresoc.v:189475.3-189484.6" + process $proc$libresoc.v:189475$13190 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:187172.5-187172.29" + attribute \src "libresoc.v:189476.5-189476.29" switch \initial - attribute \src "libresoc.v:187172.9-187172.17" + attribute \src "libresoc.v:189476.9-189476.17" case 1'1 case end @@ -391858,14 +395867,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:187181.3-187189.6" - process $proc$libresoc.v:187181$13007 + attribute \src "libresoc.v:189485.3-189493.6" + process $proc$libresoc.v:189485$13191 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$13008 $1\prev_wr_go$next[5:0]$13009 - attribute \src "libresoc.v:187182.5-187182.29" + assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 + attribute \src "libresoc.v:189486.5-189486.29" switch \initial - attribute \src "libresoc.v:187182.9-187182.17" + attribute \src "libresoc.v:189486.9-189486.17" case 1'1 case end @@ -391874,79 +395883,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$13009 6'000000 - case - assign $1\prev_wr_go$next[5:0]$13009 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13008 - end - connect \$9 $not$libresoc.v:186580$12786_Y - connect \$100 $and$libresoc.v:186581$12787_Y - connect \$102 $and$libresoc.v:186582$12788_Y - connect \$104 $and$libresoc.v:186583$12789_Y - connect \$106 $not$libresoc.v:186584$12790_Y - connect \$108 $and$libresoc.v:186585$12791_Y - connect \$110 $and$libresoc.v:186586$12792_Y - connect \$112 $and$libresoc.v:186587$12793_Y - connect \$114 $and$libresoc.v:186588$12794_Y - connect \$116 $and$libresoc.v:186589$12795_Y - connect \$118 $and$libresoc.v:186590$12796_Y - connect \$11 $or$libresoc.v:186591$12797_Y - connect \$120 $and$libresoc.v:186592$12798_Y - connect \$122 $and$libresoc.v:186593$12799_Y - connect \$124 $and$libresoc.v:186594$12800_Y - connect \$126 $and$libresoc.v:186595$12801_Y - connect \$128 $and$libresoc.v:186596$12802_Y - connect \$8 $reduce_and$libresoc.v:186597$12803_Y - connect \$130 $and$libresoc.v:186598$12804_Y - connect \$132 $and$libresoc.v:186599$12805_Y - connect \$134 $and$libresoc.v:186600$12806_Y - connect \$136 $and$libresoc.v:186601$12807_Y - connect \$14 $and$libresoc.v:186602$12808_Y - connect \$16 $not$libresoc.v:186603$12809_Y - connect \$18 $and$libresoc.v:186604$12810_Y - connect \$20 $not$libresoc.v:186605$12811_Y - connect \$22 $and$libresoc.v:186606$12812_Y - connect \$24 $and$libresoc.v:186607$12813_Y - connect \$28 $not$libresoc.v:186608$12814_Y - connect \$30 $and$libresoc.v:186609$12815_Y - connect \$27 $reduce_or$libresoc.v:186610$12816_Y - connect \$26 $not$libresoc.v:186611$12817_Y - connect \$34 $and$libresoc.v:186612$12818_Y - connect \$36 $reduce_or$libresoc.v:186613$12819_Y - connect \$38 $reduce_or$libresoc.v:186614$12820_Y - connect \$40 $or$libresoc.v:186615$12821_Y - connect \$42 $not$libresoc.v:186616$12822_Y - connect \$44 $and$libresoc.v:186617$12823_Y - connect \$46 $and$libresoc.v:186618$12824_Y - connect \$48 $eq$libresoc.v:186619$12825_Y - connect \$50 $and$libresoc.v:186620$12826_Y - connect \$52 $eq$libresoc.v:186621$12827_Y - connect \$54 $and$libresoc.v:186622$12828_Y - connect \$56 $and$libresoc.v:186623$12829_Y - connect \$58 $and$libresoc.v:186624$12830_Y - connect \$60 $or$libresoc.v:186625$12831_Y - connect \$62 $or$libresoc.v:186626$12832_Y - connect \$64 $or$libresoc.v:186627$12833_Y - connect \$66 $or$libresoc.v:186628$12834_Y - connect \$68 $and$libresoc.v:186629$12835_Y - connect \$6 $and$libresoc.v:186630$12836_Y - connect \$70 $and$libresoc.v:186631$12837_Y - connect \$72 $or$libresoc.v:186632$12838_Y - connect \$74 $and$libresoc.v:186633$12839_Y - connect \$76 $and$libresoc.v:186634$12840_Y - connect \$78 $and$libresoc.v:186635$12841_Y - connect \$80 $and$libresoc.v:186636$12842_Y - connect \$82 $and$libresoc.v:186637$12843_Y - connect \$84 $and$libresoc.v:186638$12844_Y - connect \$86 $ternary$libresoc.v:186639$12845_Y - connect \$88 $ternary$libresoc.v:186640$12846_Y - connect \$90 $ternary$libresoc.v:186641$12847_Y - connect \$92 $ternary$libresoc.v:186642$12848_Y - connect \$94 $ternary$libresoc.v:186643$12849_Y - connect \$96 $ternary$libresoc.v:186644$12850_Y - connect \$98 $and$libresoc.v:186645$12851_Y + assign $1\prev_wr_go$next[5:0]$13193 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13193 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 + end + connect \$9 $not$libresoc.v:188884$12970_Y + connect \$100 $and$libresoc.v:188885$12971_Y + connect \$102 $and$libresoc.v:188886$12972_Y + connect \$104 $and$libresoc.v:188887$12973_Y + connect \$106 $not$libresoc.v:188888$12974_Y + connect \$108 $and$libresoc.v:188889$12975_Y + connect \$110 $and$libresoc.v:188890$12976_Y + connect \$112 $and$libresoc.v:188891$12977_Y + connect \$114 $and$libresoc.v:188892$12978_Y + connect \$116 $and$libresoc.v:188893$12979_Y + connect \$118 $and$libresoc.v:188894$12980_Y + connect \$11 $or$libresoc.v:188895$12981_Y + connect \$120 $and$libresoc.v:188896$12982_Y + connect \$122 $and$libresoc.v:188897$12983_Y + connect \$124 $and$libresoc.v:188898$12984_Y + connect \$126 $and$libresoc.v:188899$12985_Y + connect \$128 $and$libresoc.v:188900$12986_Y + connect \$8 $reduce_and$libresoc.v:188901$12987_Y + connect \$130 $and$libresoc.v:188902$12988_Y + connect \$132 $and$libresoc.v:188903$12989_Y + connect \$134 $and$libresoc.v:188904$12990_Y + connect \$136 $and$libresoc.v:188905$12991_Y + connect \$14 $and$libresoc.v:188906$12992_Y + connect \$16 $not$libresoc.v:188907$12993_Y + connect \$18 $and$libresoc.v:188908$12994_Y + connect \$20 $not$libresoc.v:188909$12995_Y + connect \$22 $and$libresoc.v:188910$12996_Y + connect \$24 $and$libresoc.v:188911$12997_Y + connect \$28 $not$libresoc.v:188912$12998_Y + connect \$30 $and$libresoc.v:188913$12999_Y + connect \$27 $reduce_or$libresoc.v:188914$13000_Y + connect \$26 $not$libresoc.v:188915$13001_Y + connect \$34 $and$libresoc.v:188916$13002_Y + connect \$36 $reduce_or$libresoc.v:188917$13003_Y + connect \$38 $reduce_or$libresoc.v:188918$13004_Y + connect \$40 $or$libresoc.v:188919$13005_Y + connect \$42 $not$libresoc.v:188920$13006_Y + connect \$44 $and$libresoc.v:188921$13007_Y + connect \$46 $and$libresoc.v:188922$13008_Y + connect \$48 $eq$libresoc.v:188923$13009_Y + connect \$50 $and$libresoc.v:188924$13010_Y + connect \$52 $eq$libresoc.v:188925$13011_Y + connect \$54 $and$libresoc.v:188926$13012_Y + connect \$56 $and$libresoc.v:188927$13013_Y + connect \$58 $and$libresoc.v:188928$13014_Y + connect \$60 $or$libresoc.v:188929$13015_Y + connect \$62 $or$libresoc.v:188930$13016_Y + connect \$64 $or$libresoc.v:188931$13017_Y + connect \$66 $or$libresoc.v:188932$13018_Y + connect \$68 $and$libresoc.v:188933$13019_Y + connect \$6 $and$libresoc.v:188934$13020_Y + connect \$70 $and$libresoc.v:188935$13021_Y + connect \$72 $or$libresoc.v:188936$13022_Y + connect \$74 $and$libresoc.v:188937$13023_Y + connect \$76 $and$libresoc.v:188938$13024_Y + connect \$78 $and$libresoc.v:188939$13025_Y + connect \$80 $and$libresoc.v:188940$13026_Y + connect \$82 $and$libresoc.v:188941$13027_Y + connect \$84 $and$libresoc.v:188942$13028_Y + connect \$86 $ternary$libresoc.v:188943$13029_Y + connect \$88 $ternary$libresoc.v:188944$13030_Y + connect \$90 $ternary$libresoc.v:188945$13031_Y + connect \$92 $ternary$libresoc.v:188946$13032_Y + connect \$94 $ternary$libresoc.v:188947$13033_Y + connect \$96 $ternary$libresoc.v:188948$13034_Y + connect \$98 $and$libresoc.v:188949$13035_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -391979,111 +395988,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:187225.1-187745.10" +attribute \src "libresoc.v:189529.1-190049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $0\fast1$7[63:0]$13056 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $0\fast1$7[63:0]$13240 + attribute \src "libresoc.v:189879.3-189894.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:187226.7-187226.20" + attribute \src "libresoc.v:189530.7-189530.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $0\spr1$6[63:0]$13081 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $0\spr1$6[63:0]$13265 + attribute \src "libresoc.v:189818.3-189836.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $0\xer_ca$10[1:0]$13075 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $0\xer_ca$10[1:0]$13259 + attribute \src "libresoc.v:190006.3-190026.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $0\xer_ov$9[1:0]$13069 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $0\xer_ov$9[1:0]$13253 + attribute \src "libresoc.v:189961.3-189981.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $0\xer_so$8[0:0]$13063 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $0\xer_so$8[0:0]$13247 + attribute \src "libresoc.v:189916.3-189936.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $1\fast1$7[63:0]$13057 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189879.3-189894.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $1\spr1$6[63:0]$13082 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:189818.3-189836.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $1\xer_ca$10[1:0]$13076 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:190006.3-190026.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $1\xer_ov$9[1:0]$13070 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189961.3-189981.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $1\xer_so$8[0:0]$13064 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $1\xer_so$8[0:0]$13248 + attribute \src "libresoc.v:189916.3-189936.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:187498.3-187513.6" - wire width 64 $2\fast1$7[63:0]$13058 - attribute \src "libresoc.v:187575.3-187590.6" + attribute \src "libresoc.v:189802.3-189817.6" + wire width 64 $2\fast1$7[63:0]$13242 + attribute \src "libresoc.v:189879.3-189894.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:187723.3-187741.6" - wire width 64 $2\spr1$6[63:0]$13083 - attribute \src "libresoc.v:187514.3-187532.6" + attribute \src "libresoc.v:190027.3-190045.6" + wire width 64 $2\spr1$6[63:0]$13267 + attribute \src "libresoc.v:189818.3-189836.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $2\xer_ca$10[1:0]$13077 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $2\xer_ca$10[1:0]$13261 + attribute \src "libresoc.v:190006.3-190026.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $2\xer_ov$9[1:0]$13071 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $2\xer_ov$9[1:0]$13255 + attribute \src "libresoc.v:189961.3-189981.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $2\xer_so$8[0:0]$13065 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $2\xer_so$8[0:0]$13249 + attribute \src "libresoc.v:189916.3-189936.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:187533.3-187574.6" + attribute \src "libresoc.v:189837.3-189878.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:187678.3-187701.6" - wire width 2 $3\xer_ca$10[1:0]$13078 - attribute \src "libresoc.v:187702.3-187722.6" + attribute \src "libresoc.v:189982.3-190005.6" + wire width 2 $3\xer_ca$10[1:0]$13262 + attribute \src "libresoc.v:190006.3-190026.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:187633.3-187656.6" - wire width 2 $3\xer_ov$9[1:0]$13072 - attribute \src "libresoc.v:187657.3-187677.6" + attribute \src "libresoc.v:189937.3-189960.6" + wire width 2 $3\xer_ov$9[1:0]$13256 + attribute \src "libresoc.v:189961.3-189981.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:187591.3-187611.6" - wire $3\xer_so$8[0:0]$13066 - attribute \src "libresoc.v:187612.3-187632.6" + attribute \src "libresoc.v:189895.3-189915.6" + wire $3\xer_so$8[0:0]$13250 + attribute \src "libresoc.v:189916.3-189936.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:187491.18-187491.106" - wire $eq$libresoc.v:187491$13048_Y - attribute \src "libresoc.v:187492.18-187492.106" - wire $eq$libresoc.v:187492$13049_Y - attribute \src "libresoc.v:187493.18-187493.106" - wire $eq$libresoc.v:187493$13050_Y - attribute \src "libresoc.v:187494.18-187494.106" - wire $eq$libresoc.v:187494$13051_Y - attribute \src "libresoc.v:187495.18-187495.106" - wire $eq$libresoc.v:187495$13052_Y - attribute \src "libresoc.v:187496.18-187496.106" - wire $eq$libresoc.v:187496$13053_Y - attribute \src "libresoc.v:187497.18-187497.106" - wire $eq$libresoc.v:187497$13054_Y + attribute \src "libresoc.v:189795.18-189795.106" + wire $eq$libresoc.v:189795$13232_Y + attribute \src "libresoc.v:189796.18-189796.106" + wire $eq$libresoc.v:189796$13233_Y + attribute \src "libresoc.v:189797.18-189797.106" + wire $eq$libresoc.v:189797$13234_Y + attribute \src "libresoc.v:189798.18-189798.106" + wire $eq$libresoc.v:189798$13235_Y + attribute \src "libresoc.v:189799.18-189799.106" + wire $eq$libresoc.v:189799$13236_Y + attribute \src "libresoc.v:189800.18-189800.106" + wire $eq$libresoc.v:189800$13237_Y + attribute \src "libresoc.v:189801.18-189801.106" + wire $eq$libresoc.v:189801$13238_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -392104,7 +396113,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:187226.7-187226.15" + attribute \src "libresoc.v:189530.7-189530.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -392339,7 +396348,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187491$13048 + cell $eq $eq$libresoc.v:189795$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392347,10 +396356,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187491$13048_Y + connect \Y $eq$libresoc.v:189795$13232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187492$13049 + cell $eq $eq$libresoc.v:189796$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392358,10 +396367,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187492$13049_Y + connect \Y $eq$libresoc.v:189796$13233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187493$13050 + cell $eq $eq$libresoc.v:189797$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392369,10 +396378,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187493$13050_Y + connect \Y $eq$libresoc.v:189797$13234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187494$13051 + cell $eq $eq$libresoc.v:189798$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392380,10 +396389,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187494$13051_Y + connect \Y $eq$libresoc.v:189798$13235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187495$13052 + cell $eq $eq$libresoc.v:189799$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392391,10 +396400,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187495$13052_Y + connect \Y $eq$libresoc.v:189799$13236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:187496$13053 + cell $eq $eq$libresoc.v:189800$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392402,10 +396411,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187496$13053_Y + connect \Y $eq$libresoc.v:189800$13237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:187497$13054 + cell $eq $eq$libresoc.v:189801$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -392413,24 +396422,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:187497$13054_Y + connect \Y $eq$libresoc.v:189801$13238_Y end - attribute \src "libresoc.v:187226.7-187226.20" - process $proc$libresoc.v:187226$13084 + attribute \src "libresoc.v:189530.7-189530.20" + process $proc$libresoc.v:189530$13268 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187498.3-187513.6" - process $proc$libresoc.v:187498$13055 + attribute \src "libresoc.v:189802.3-189817.6" + process $proc$libresoc.v:189802$13239 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13056 $1\fast1$7[63:0]$13057 - attribute \src "libresoc.v:187499.5-187499.29" + assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 + attribute \src "libresoc.v:189803.5-189803.29" switch \initial - attribute \src "libresoc.v:187499.9-187499.17" + attribute \src "libresoc.v:189803.9-189803.17" case 1'1 case end @@ -392439,30 +396448,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13057 $2\fast1$7[63:0]$13058 + assign $1\fast1$7[63:0]$13241 $2\fast1$7[63:0]$13242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13058 \ra + assign $2\fast1$7[63:0]$13242 \ra case - assign $2\fast1$7[63:0]$13058 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13242 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13241 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13056 + update \fast1$7 $0\fast1$7[63:0]$13240 end - attribute \src "libresoc.v:187514.3-187532.6" - process $proc$libresoc.v:187514$13059 + attribute \src "libresoc.v:189818.3-189836.6" + process $proc$libresoc.v:189818$13243 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:187515.5-187515.29" + attribute \src "libresoc.v:189819.5-189819.29" switch \initial - attribute \src "libresoc.v:187515.9-187515.17" + attribute \src "libresoc.v:189819.9-189819.17" case 1'1 case end @@ -392488,17 +396497,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:187533.3-187574.6" - process $proc$libresoc.v:187533$13060 + attribute \src "libresoc.v:189837.3-189878.6" + process $proc$libresoc.v:189837$13244 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:187534.5-187534.29" + attribute \src "libresoc.v:189838.5-189838.29" switch \initial - attribute \src "libresoc.v:187534.9-187534.17" + attribute \src "libresoc.v:189838.9-189838.17" case 1'1 case end @@ -392549,14 +396558,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:187575.3-187590.6" - process $proc$libresoc.v:187575$13061 + attribute \src "libresoc.v:189879.3-189894.6" + process $proc$libresoc.v:189879$13245 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:187576.5-187576.29" + attribute \src "libresoc.v:189880.5-189880.29" switch \initial - attribute \src "libresoc.v:187576.9-187576.17" + attribute \src "libresoc.v:189880.9-189880.17" case 1'1 case end @@ -392581,14 +396590,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:187591.3-187611.6" - process $proc$libresoc.v:187591$13062 + attribute \src "libresoc.v:189895.3-189915.6" + process $proc$libresoc.v:189895$13246 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13063 $1\xer_so$8[0:0]$13064 - attribute \src "libresoc.v:187592.5-187592.29" + assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 + attribute \src "libresoc.v:189896.5-189896.29" switch \initial - attribute \src "libresoc.v:187592.9-187592.17" + attribute \src "libresoc.v:189896.9-189896.17" case 1'1 case end @@ -392597,39 +396606,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13064 $2\xer_so$8[0:0]$13065 + assign $1\xer_so$8[0:0]$13248 $2\xer_so$8[0:0]$13249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13065 $3\xer_so$8[0:0]$13066 + assign $2\xer_so$8[0:0]$13249 $3\xer_so$8[0:0]$13250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13066 \ra [31] + assign $3\xer_so$8[0:0]$13250 \ra [31] case - assign $3\xer_so$8[0:0]$13066 1'0 + assign $3\xer_so$8[0:0]$13250 1'0 end case - assign $2\xer_so$8[0:0]$13065 1'0 + assign $2\xer_so$8[0:0]$13249 1'0 end case - assign $1\xer_so$8[0:0]$13064 1'0 + assign $1\xer_so$8[0:0]$13248 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13063 + update \xer_so$8 $0\xer_so$8[0:0]$13247 end - attribute \src "libresoc.v:187612.3-187632.6" - process $proc$libresoc.v:187612$13067 + attribute \src "libresoc.v:189916.3-189936.6" + process $proc$libresoc.v:189916$13251 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:187613.5-187613.29" + attribute \src "libresoc.v:189917.5-189917.29" switch \initial - attribute \src "libresoc.v:187613.9-187613.17" + attribute \src "libresoc.v:189917.9-189917.17" case 1'1 case end @@ -392663,14 +396672,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:187633.3-187656.6" - process $proc$libresoc.v:187633$13068 + attribute \src "libresoc.v:189937.3-189960.6" + process $proc$libresoc.v:189937$13252 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13069 $1\xer_ov$9[1:0]$13070 - attribute \src "libresoc.v:187634.5-187634.29" + assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 + attribute \src "libresoc.v:189938.5-189938.29" switch \initial - attribute \src "libresoc.v:187634.9-187634.17" + attribute \src "libresoc.v:189938.9-189938.17" case 1'1 case end @@ -392679,40 +396688,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13070 $2\xer_ov$9[1:0]$13071 + assign $1\xer_ov$9[1:0]$13254 $2\xer_ov$9[1:0]$13255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13071 $3\xer_ov$9[1:0]$13072 + assign $2\xer_ov$9[1:0]$13255 $3\xer_ov$9[1:0]$13256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13072 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13072 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13256 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13256 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13072 2'00 + assign $3\xer_ov$9[1:0]$13256 2'00 end case - assign $2\xer_ov$9[1:0]$13071 2'00 + assign $2\xer_ov$9[1:0]$13255 2'00 end case - assign $1\xer_ov$9[1:0]$13070 2'00 + assign $1\xer_ov$9[1:0]$13254 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13069 + update \xer_ov$9 $0\xer_ov$9[1:0]$13253 end - attribute \src "libresoc.v:187657.3-187677.6" - process $proc$libresoc.v:187657$13073 + attribute \src "libresoc.v:189961.3-189981.6" + process $proc$libresoc.v:189961$13257 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:187658.5-187658.29" + attribute \src "libresoc.v:189962.5-189962.29" switch \initial - attribute \src "libresoc.v:187658.9-187658.17" + attribute \src "libresoc.v:189962.9-189962.17" case 1'1 case end @@ -392746,14 +396755,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:187678.3-187701.6" - process $proc$libresoc.v:187678$13074 + attribute \src "libresoc.v:189982.3-190005.6" + process $proc$libresoc.v:189982$13258 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13075 $1\xer_ca$10[1:0]$13076 - attribute \src "libresoc.v:187679.5-187679.29" + assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 + attribute \src "libresoc.v:189983.5-189983.29" switch \initial - attribute \src "libresoc.v:187679.9-187679.17" + attribute \src "libresoc.v:189983.9-189983.17" case 1'1 case end @@ -392762,40 +396771,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13076 $2\xer_ca$10[1:0]$13077 + assign $1\xer_ca$10[1:0]$13260 $2\xer_ca$10[1:0]$13261 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13077 $3\xer_ca$10[1:0]$13078 + assign $2\xer_ca$10[1:0]$13261 $3\xer_ca$10[1:0]$13262 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13078 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13078 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13262 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13262 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13078 2'00 + assign $3\xer_ca$10[1:0]$13262 2'00 end case - assign $2\xer_ca$10[1:0]$13077 2'00 + assign $2\xer_ca$10[1:0]$13261 2'00 end case - assign $1\xer_ca$10[1:0]$13076 2'00 + assign $1\xer_ca$10[1:0]$13260 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13075 + update \xer_ca$10 $0\xer_ca$10[1:0]$13259 end - attribute \src "libresoc.v:187702.3-187722.6" - process $proc$libresoc.v:187702$13079 + attribute \src "libresoc.v:190006.3-190026.6" + process $proc$libresoc.v:190006$13263 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:187703.5-187703.29" + attribute \src "libresoc.v:190007.5-190007.29" switch \initial - attribute \src "libresoc.v:187703.9-187703.17" + attribute \src "libresoc.v:190007.9-190007.17" case 1'1 case end @@ -392829,14 +396838,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:187723.3-187741.6" - process $proc$libresoc.v:187723$13080 + attribute \src "libresoc.v:190027.3-190045.6" + process $proc$libresoc.v:190027$13264 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13081 $1\spr1$6[63:0]$13082 - attribute \src "libresoc.v:187724.5-187724.29" + assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 + attribute \src "libresoc.v:190028.5-190028.29" switch \initial - attribute \src "libresoc.v:187724.9-187724.17" + attribute \src "libresoc.v:190028.9-190028.17" case 1'1 case end @@ -392845,64 +396854,64 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13082 $2\spr1$6[63:0]$13083 + assign $1\spr1$6[63:0]$13266 $2\spr1$6[63:0]$13267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13083 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13267 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13083 \ra + assign $2\spr1$6[63:0]$13267 \ra end case - assign $1\spr1$6[63:0]$13082 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13266 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13081 + update \spr1$6 $0\spr1$6[63:0]$13265 end - connect \$11 $eq$libresoc.v:187491$13048_Y - connect \$13 $eq$libresoc.v:187492$13049_Y - connect \$15 $eq$libresoc.v:187493$13050_Y - connect \$17 $eq$libresoc.v:187494$13051_Y - connect \$19 $eq$libresoc.v:187495$13052_Y - connect \$21 $eq$libresoc.v:187496$13053_Y - connect \$23 $eq$libresoc.v:187497$13054_Y + connect \$11 $eq$libresoc.v:189795$13232_Y + connect \$13 $eq$libresoc.v:189796$13233_Y + connect \$15 $eq$libresoc.v:189797$13234_Y + connect \$17 $eq$libresoc.v:189798$13235_Y + connect \$19 $eq$libresoc.v:189799$13236_Y + connect \$21 $eq$libresoc.v:189800$13237_Y + connect \$23 $eq$libresoc.v:189801$13238_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:187749.1-188585.10" +attribute \src "libresoc.v:190053.1-190889.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:187879.3-187909.6" + attribute \src "libresoc.v:190183.3-190213.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:187910.3-187940.6" + attribute \src "libresoc.v:190214.3-190244.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:187750.7-187750.20" + attribute \src "libresoc.v:190054.7-190054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187941.3-188262.6" + attribute \src "libresoc.v:190245.3-190566.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:188263.3-188584.6" + attribute \src "libresoc.v:190567.3-190888.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:187879.3-187909.6" + attribute \src "libresoc.v:190183.3-190213.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:187910.3-187940.6" + attribute \src "libresoc.v:190214.3-190244.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:187941.3-188262.6" + attribute \src "libresoc.v:190245.3-190566.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:188263.3-188584.6" + attribute \src "libresoc.v:190567.3-190888.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:187750.7-187750.15" + attribute \src "libresoc.v:190054.7-190054.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -393022,26 +397031,26 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:187750.7-187750.20" - process $proc$libresoc.v:187750$13089 + attribute \src "libresoc.v:190054.7-190054.20" + process $proc$libresoc.v:190054$13273 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187879.3-187909.6" - process $proc$libresoc.v:187879$13085 + attribute \src "libresoc.v:190183.3-190213.6" + process $proc$libresoc.v:190183$13269 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:187880.5-187880.29" + attribute \src "libresoc.v:190184.5-190184.29" switch \initial - attribute \src "libresoc.v:187880.9-187880.17" + attribute \src "libresoc.v:190184.9-190184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -393081,18 +397090,18 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:187910.3-187940.6" - process $proc$libresoc.v:187910$13086 + attribute \src "libresoc.v:190214.3-190244.6" + process $proc$libresoc.v:190214$13270 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:187911.5-187911.29" + attribute \src "libresoc.v:190215.5-190215.29" switch \initial - attribute \src "libresoc.v:187911.9-187911.17" + attribute \src "libresoc.v:190215.9-190215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -393132,18 +397141,18 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:187941.3-188262.6" - process $proc$libresoc.v:187941$13087 + attribute \src "libresoc.v:190245.3-190566.6" + process $proc$libresoc.v:190245$13271 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:187942.5-187942.29" + attribute \src "libresoc.v:190246.5-190246.29" switch \initial - attribute \src "libresoc.v:187942.9-187942.17" + attribute \src "libresoc.v:190246.9-190246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -393571,18 +397580,18 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:188263.3-188584.6" - process $proc$libresoc.v:188263$13088 + attribute \src "libresoc.v:190567.3-190888.6" + process $proc$libresoc.v:190567$13272 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:188264.5-188264.29" + attribute \src "libresoc.v:190568.5-190568.29" switch \initial - attribute \src "libresoc.v:188264.9-188264.17" + attribute \src "libresoc.v:190568.9-190568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -394011,36 +398020,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:188589.1-189425.10" +attribute \src "libresoc.v:190893.1-191729.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:188719.3-188749.6" + attribute \src "libresoc.v:191023.3-191053.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:188750.3-188780.6" + attribute \src "libresoc.v:191054.3-191084.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:188590.7-188590.20" + attribute \src "libresoc.v:190894.7-190894.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188781.3-189102.6" + attribute \src "libresoc.v:191085.3-191406.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:189103.3-189424.6" + attribute \src "libresoc.v:191407.3-191728.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:188719.3-188749.6" + attribute \src "libresoc.v:191023.3-191053.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:188750.3-188780.6" + attribute \src "libresoc.v:191054.3-191084.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:188781.3-189102.6" + attribute \src "libresoc.v:191085.3-191406.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:189103.3-189424.6" + attribute \src "libresoc.v:191407.3-191728.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:188590.7-188590.15" + attribute \src "libresoc.v:190894.7-190894.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -394160,26 +398169,26 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:188590.7-188590.20" - process $proc$libresoc.v:188590$13094 + attribute \src "libresoc.v:190894.7-190894.20" + process $proc$libresoc.v:190894$13278 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188719.3-188749.6" - process $proc$libresoc.v:188719$13090 + attribute \src "libresoc.v:191023.3-191053.6" + process $proc$libresoc.v:191023$13274 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:188720.5-188720.29" + attribute \src "libresoc.v:191024.5-191024.29" switch \initial - attribute \src "libresoc.v:188720.9-188720.17" + attribute \src "libresoc.v:191024.9-191024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -394219,18 +398228,18 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:188750.3-188780.6" - process $proc$libresoc.v:188750$13091 + attribute \src "libresoc.v:191054.3-191084.6" + process $proc$libresoc.v:191054$13275 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:188751.5-188751.29" + attribute \src "libresoc.v:191055.5-191055.29" switch \initial - attribute \src "libresoc.v:188751.9-188751.17" + attribute \src "libresoc.v:191055.9-191055.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -394270,18 +398279,18 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:188781.3-189102.6" - process $proc$libresoc.v:188781$13092 + attribute \src "libresoc.v:191085.3-191406.6" + process $proc$libresoc.v:191085$13276 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:188782.5-188782.29" + attribute \src "libresoc.v:191086.5-191086.29" switch \initial - attribute \src "libresoc.v:188782.9-188782.17" + attribute \src "libresoc.v:191086.9-191086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -394709,18 +398718,18 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:189103.3-189424.6" - process $proc$libresoc.v:189103$13093 + attribute \src "libresoc.v:191407.3-191728.6" + process $proc$libresoc.v:191407$13277 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:189104.5-189104.29" + attribute \src "libresoc.v:191408.5-191408.29" switch \initial - attribute \src "libresoc.v:189104.9-189104.17" + attribute \src "libresoc.v:191408.9-191408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -395149,70 +399158,70 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:189429.1-189569.10" +attribute \src "libresoc.v:191733.1-191873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" attribute \generator "nMigen" module \sram4k_0 - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189430.7-189430.20" + attribute \src "libresoc.v:191734.7-191734.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $0\sram4k_0_wb__ack$next[0:0]$13099 - attribute \src "libresoc.v:189470.3-189471.49" + attribute \src "libresoc.v:191793.3-191807.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13283 + attribute \src "libresoc.v:191774.3-191775.49" wire $0\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $0\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189479.3-189488.6" + attribute \src "libresoc.v:191783.3-191792.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $0\we[0:0] - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $1\sram4k_0_wb__ack$next[0:0]$13100 - attribute \src "libresoc.v:189447.7-189447.30" + attribute \src "libresoc.v:191793.3-191807.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13284 + attribute \src "libresoc.v:191751.7-191751.30" wire $1\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189479.3-189488.6" + attribute \src "libresoc.v:191783.3-191792.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $1\we[0:0] - attribute \src "libresoc.v:189504.3-189518.6" + attribute \src "libresoc.v:191808.3-191822.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189534.3-189548.6" + attribute \src "libresoc.v:191838.3-191852.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189489.3-189503.6" - wire $2\sram4k_0_wb__ack$next[0:0]$13101 - attribute \src "libresoc.v:189519.3-189533.6" + attribute \src "libresoc.v:191793.3-191807.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191823.3-191837.6" wire width 64 $2\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $2\we[0:0] - attribute \src "libresoc.v:189549.3-189568.6" + attribute \src "libresoc.v:191853.3-191872.6" wire $3\we[0:0] - attribute \src "libresoc.v:189469.17-189469.129" - wire $and$libresoc.v:189469$13095_Y + attribute \src "libresoc.v:191773.17-191773.129" + wire $and$libresoc.v:191773$13279_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189430.7-189430.15" + attribute \src "libresoc.v:191734.7-191734.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_0_wb__ack @@ -395237,7 +399246,7 @@ module \sram4k_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189469$13095 + cell $and $and$libresoc.v:191773$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395245,10 +399254,10 @@ module \sram4k_0 parameter \Y_WIDTH 1 connect \A \sram4k_0_wb__cyc connect \B \sram4k_0_wb__stb - connect \Y $and$libresoc.v:189469$13095_Y + connect \Y $and$libresoc.v:191773$13279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189472.21-189478.4" + attribute \src "libresoc.v:191776.21-191782.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395256,37 +399265,37 @@ module \sram4k_0 connect \q \q connect \we \we end - attribute \src "libresoc.v:189430.7-189430.20" - process $proc$libresoc.v:189430$13106 + attribute \src "libresoc.v:191734.7-191734.20" + process $proc$libresoc.v:191734$13290 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189447.7-189447.30" - process $proc$libresoc.v:189447$13107 + attribute \src "libresoc.v:191751.7-191751.30" + process $proc$libresoc.v:191751$13291 assign { } { } assign $1\sram4k_0_wb__ack[0:0] 1'0 sync always sync init update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:189470.3-189471.49" - process $proc$libresoc.v:189470$13096 + attribute \src "libresoc.v:191774.3-191775.49" + process $proc$libresoc.v:191774$13280 assign { } { } assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next sync posedge \clk update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:189479.3-189488.6" - process $proc$libresoc.v:189479$13097 + attribute \src "libresoc.v:191783.3-191792.6" + process $proc$libresoc.v:191783$13281 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189480.5-189480.29" + attribute \src "libresoc.v:191784.5-191784.29" switch \initial - attribute \src "libresoc.v:189480.9-189480.17" + attribute \src "libresoc.v:191784.9-191784.17" case 1'1 case end @@ -395302,15 +399311,15 @@ module \sram4k_0 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189489.3-189503.6" - process $proc$libresoc.v:189489$13098 + attribute \src "libresoc.v:191793.3-191807.6" + process $proc$libresoc.v:191793$13282 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_0_wb__ack$next[0:0]$13099 $2\sram4k_0_wb__ack$next[0:0]$13101 - attribute \src "libresoc.v:189490.5-189490.29" + assign $0\sram4k_0_wb__ack$next[0:0]$13283 $2\sram4k_0_wb__ack$next[0:0]$13285 + attribute \src "libresoc.v:191794.5-191794.29" switch \initial - attribute \src "libresoc.v:189490.9-189490.17" + attribute \src "libresoc.v:191794.9-191794.17" case 1'1 case end @@ -395319,30 +399328,30 @@ module \sram4k_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_0_wb__ack$next[0:0]$13100 \wb_active + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \wb_active case - assign $1\sram4k_0_wb__ack$next[0:0]$13100 \sram4k_0_wb__ack + assign $1\sram4k_0_wb__ack$next[0:0]$13284 \sram4k_0_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_0_wb__ack$next[0:0]$13101 1'0 + assign $2\sram4k_0_wb__ack$next[0:0]$13285 1'0 case - assign $2\sram4k_0_wb__ack$next[0:0]$13101 $1\sram4k_0_wb__ack$next[0:0]$13100 + assign $2\sram4k_0_wb__ack$next[0:0]$13285 $1\sram4k_0_wb__ack$next[0:0]$13284 end sync always - update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13099 + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13283 end - attribute \src "libresoc.v:189504.3-189518.6" - process $proc$libresoc.v:189504$13102 + attribute \src "libresoc.v:191808.3-191822.6" + process $proc$libresoc.v:191808$13286 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189505.5-189505.29" + attribute \src "libresoc.v:191809.5-191809.29" switch \initial - attribute \src "libresoc.v:189505.9-189505.17" + attribute \src "libresoc.v:191809.9-191809.17" case 1'1 case end @@ -395367,14 +399376,14 @@ module \sram4k_0 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189519.3-189533.6" - process $proc$libresoc.v:189519$13103 + attribute \src "libresoc.v:191823.3-191837.6" + process $proc$libresoc.v:191823$13287 assign { } { } assign { } { } assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:189520.5-189520.29" + attribute \src "libresoc.v:191824.5-191824.29" switch \initial - attribute \src "libresoc.v:189520.9-189520.17" + attribute \src "libresoc.v:191824.9-191824.17" case 1'1 case end @@ -395399,14 +399408,14 @@ module \sram4k_0 sync always update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] end - attribute \src "libresoc.v:189534.3-189548.6" - process $proc$libresoc.v:189534$13104 + attribute \src "libresoc.v:191838.3-191852.6" + process $proc$libresoc.v:191838$13288 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189535.5-189535.29" + attribute \src "libresoc.v:191839.5-191839.29" switch \initial - attribute \src "libresoc.v:189535.9-189535.17" + attribute \src "libresoc.v:191839.9-191839.17" case 1'1 case end @@ -395431,14 +399440,14 @@ module \sram4k_0 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189549.3-189568.6" - process $proc$libresoc.v:189549$13105 + attribute \src "libresoc.v:191853.3-191872.6" + process $proc$libresoc.v:191853$13289 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189550.5-189550.29" + attribute \src "libresoc.v:191854.5-191854.29" switch \initial - attribute \src "libresoc.v:189550.9-189550.17" + attribute \src "libresoc.v:191854.9-191854.17" case 1'1 case end @@ -395472,72 +399481,72 @@ module \sram4k_0 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189469$13095_Y + connect \$1 $and$libresoc.v:191773$13279_Y end -attribute \src "libresoc.v:189573.1-189713.10" +attribute \src "libresoc.v:191877.1-192017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" attribute \generator "nMigen" module \sram4k_1 - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189574.7-189574.20" + attribute \src "libresoc.v:191878.7-191878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $0\sram4k_1_wb__ack$next[0:0]$13112 - attribute \src "libresoc.v:189614.3-189615.49" + attribute \src "libresoc.v:191937.3-191951.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13296 + attribute \src "libresoc.v:191918.3-191919.49" wire $0\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $0\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189623.3-189632.6" + attribute \src "libresoc.v:191927.3-191936.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $0\we[0:0] - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $1\sram4k_1_wb__ack$next[0:0]$13113 - attribute \src "libresoc.v:189591.7-189591.30" + attribute \src "libresoc.v:191937.3-191951.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13297 + attribute \src "libresoc.v:191895.7-191895.30" wire $1\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189623.3-189632.6" + attribute \src "libresoc.v:191927.3-191936.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $1\we[0:0] - attribute \src "libresoc.v:189648.3-189662.6" + attribute \src "libresoc.v:191952.3-191966.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189678.3-189692.6" + attribute \src "libresoc.v:191982.3-191996.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189633.3-189647.6" - wire $2\sram4k_1_wb__ack$next[0:0]$13114 - attribute \src "libresoc.v:189663.3-189677.6" + attribute \src "libresoc.v:191937.3-191951.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191967.3-191981.6" wire width 64 $2\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $2\we[0:0] - attribute \src "libresoc.v:189693.3-189712.6" + attribute \src "libresoc.v:191997.3-192016.6" wire $3\we[0:0] - attribute \src "libresoc.v:189613.17-189613.129" - wire $and$libresoc.v:189613$13108_Y + attribute \src "libresoc.v:191917.17-191917.129" + wire $and$libresoc.v:191917$13292_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189574.7-189574.15" + attribute \src "libresoc.v:191878.7-191878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_1_wb__ack @@ -395562,7 +399571,7 @@ module \sram4k_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189613$13108 + cell $and $and$libresoc.v:191917$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395570,10 +399579,10 @@ module \sram4k_1 parameter \Y_WIDTH 1 connect \A \sram4k_1_wb__cyc connect \B \sram4k_1_wb__stb - connect \Y $and$libresoc.v:189613$13108_Y + connect \Y $and$libresoc.v:191917$13292_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189616.21-189622.4" + attribute \src "libresoc.v:191920.21-191926.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395581,37 +399590,37 @@ module \sram4k_1 connect \q \q connect \we \we end - attribute \src "libresoc.v:189574.7-189574.20" - process $proc$libresoc.v:189574$13119 + attribute \src "libresoc.v:191878.7-191878.20" + process $proc$libresoc.v:191878$13303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189591.7-189591.30" - process $proc$libresoc.v:189591$13120 + attribute \src "libresoc.v:191895.7-191895.30" + process $proc$libresoc.v:191895$13304 assign { } { } assign $1\sram4k_1_wb__ack[0:0] 1'0 sync always sync init update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:189614.3-189615.49" - process $proc$libresoc.v:189614$13109 + attribute \src "libresoc.v:191918.3-191919.49" + process $proc$libresoc.v:191918$13293 assign { } { } assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next sync posedge \clk update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:189623.3-189632.6" - process $proc$libresoc.v:189623$13110 + attribute \src "libresoc.v:191927.3-191936.6" + process $proc$libresoc.v:191927$13294 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189624.5-189624.29" + attribute \src "libresoc.v:191928.5-191928.29" switch \initial - attribute \src "libresoc.v:189624.9-189624.17" + attribute \src "libresoc.v:191928.9-191928.17" case 1'1 case end @@ -395627,15 +399636,15 @@ module \sram4k_1 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189633.3-189647.6" - process $proc$libresoc.v:189633$13111 + attribute \src "libresoc.v:191937.3-191951.6" + process $proc$libresoc.v:191937$13295 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_1_wb__ack$next[0:0]$13112 $2\sram4k_1_wb__ack$next[0:0]$13114 - attribute \src "libresoc.v:189634.5-189634.29" + assign $0\sram4k_1_wb__ack$next[0:0]$13296 $2\sram4k_1_wb__ack$next[0:0]$13298 + attribute \src "libresoc.v:191938.5-191938.29" switch \initial - attribute \src "libresoc.v:189634.9-189634.17" + attribute \src "libresoc.v:191938.9-191938.17" case 1'1 case end @@ -395644,30 +399653,30 @@ module \sram4k_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_1_wb__ack$next[0:0]$13113 \wb_active + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \wb_active case - assign $1\sram4k_1_wb__ack$next[0:0]$13113 \sram4k_1_wb__ack + assign $1\sram4k_1_wb__ack$next[0:0]$13297 \sram4k_1_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_1_wb__ack$next[0:0]$13114 1'0 + assign $2\sram4k_1_wb__ack$next[0:0]$13298 1'0 case - assign $2\sram4k_1_wb__ack$next[0:0]$13114 $1\sram4k_1_wb__ack$next[0:0]$13113 + assign $2\sram4k_1_wb__ack$next[0:0]$13298 $1\sram4k_1_wb__ack$next[0:0]$13297 end sync always - update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13112 + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13296 end - attribute \src "libresoc.v:189648.3-189662.6" - process $proc$libresoc.v:189648$13115 + attribute \src "libresoc.v:191952.3-191966.6" + process $proc$libresoc.v:191952$13299 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189649.5-189649.29" + attribute \src "libresoc.v:191953.5-191953.29" switch \initial - attribute \src "libresoc.v:189649.9-189649.17" + attribute \src "libresoc.v:191953.9-191953.17" case 1'1 case end @@ -395692,14 +399701,14 @@ module \sram4k_1 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189663.3-189677.6" - process $proc$libresoc.v:189663$13116 + attribute \src "libresoc.v:191967.3-191981.6" + process $proc$libresoc.v:191967$13300 assign { } { } assign { } { } assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:189664.5-189664.29" + attribute \src "libresoc.v:191968.5-191968.29" switch \initial - attribute \src "libresoc.v:189664.9-189664.17" + attribute \src "libresoc.v:191968.9-191968.17" case 1'1 case end @@ -395724,14 +399733,14 @@ module \sram4k_1 sync always update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] end - attribute \src "libresoc.v:189678.3-189692.6" - process $proc$libresoc.v:189678$13117 + attribute \src "libresoc.v:191982.3-191996.6" + process $proc$libresoc.v:191982$13301 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189679.5-189679.29" + attribute \src "libresoc.v:191983.5-191983.29" switch \initial - attribute \src "libresoc.v:189679.9-189679.17" + attribute \src "libresoc.v:191983.9-191983.17" case 1'1 case end @@ -395756,14 +399765,14 @@ module \sram4k_1 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189693.3-189712.6" - process $proc$libresoc.v:189693$13118 + attribute \src "libresoc.v:191997.3-192016.6" + process $proc$libresoc.v:191997$13302 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189694.5-189694.29" + attribute \src "libresoc.v:191998.5-191998.29" switch \initial - attribute \src "libresoc.v:189694.9-189694.17" + attribute \src "libresoc.v:191998.9-191998.17" case 1'1 case end @@ -395797,72 +399806,72 @@ module \sram4k_1 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189613$13108_Y + connect \$1 $and$libresoc.v:191917$13292_Y end -attribute \src "libresoc.v:189717.1-189857.10" +attribute \src "libresoc.v:192021.1-192161.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" attribute \generator "nMigen" module \sram4k_2 - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189718.7-189718.20" + attribute \src "libresoc.v:192022.7-192022.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $0\sram4k_2_wb__ack$next[0:0]$13125 - attribute \src "libresoc.v:189758.3-189759.49" + attribute \src "libresoc.v:192081.3-192095.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13309 + attribute \src "libresoc.v:192062.3-192063.49" wire $0\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $0\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189767.3-189776.6" + attribute \src "libresoc.v:192071.3-192080.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $0\we[0:0] - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $1\sram4k_2_wb__ack$next[0:0]$13126 - attribute \src "libresoc.v:189735.7-189735.30" + attribute \src "libresoc.v:192081.3-192095.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13310 + attribute \src "libresoc.v:192039.7-192039.30" wire $1\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189767.3-189776.6" + attribute \src "libresoc.v:192071.3-192080.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $1\we[0:0] - attribute \src "libresoc.v:189792.3-189806.6" + attribute \src "libresoc.v:192096.3-192110.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189822.3-189836.6" + attribute \src "libresoc.v:192126.3-192140.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189777.3-189791.6" - wire $2\sram4k_2_wb__ack$next[0:0]$13127 - attribute \src "libresoc.v:189807.3-189821.6" + attribute \src "libresoc.v:192081.3-192095.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192111.3-192125.6" wire width 64 $2\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $2\we[0:0] - attribute \src "libresoc.v:189837.3-189856.6" + attribute \src "libresoc.v:192141.3-192160.6" wire $3\we[0:0] - attribute \src "libresoc.v:189757.17-189757.129" - wire $and$libresoc.v:189757$13121_Y + attribute \src "libresoc.v:192061.17-192061.129" + wire $and$libresoc.v:192061$13305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189718.7-189718.15" + attribute \src "libresoc.v:192022.7-192022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_2_wb__ack @@ -395887,7 +399896,7 @@ module \sram4k_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189757$13121 + cell $and $and$libresoc.v:192061$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395895,10 +399904,10 @@ module \sram4k_2 parameter \Y_WIDTH 1 connect \A \sram4k_2_wb__cyc connect \B \sram4k_2_wb__stb - connect \Y $and$libresoc.v:189757$13121_Y + connect \Y $and$libresoc.v:192061$13305_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189760.21-189766.4" + attribute \src "libresoc.v:192064.21-192070.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -395906,37 +399915,37 @@ module \sram4k_2 connect \q \q connect \we \we end - attribute \src "libresoc.v:189718.7-189718.20" - process $proc$libresoc.v:189718$13132 + attribute \src "libresoc.v:192022.7-192022.20" + process $proc$libresoc.v:192022$13316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189735.7-189735.30" - process $proc$libresoc.v:189735$13133 + attribute \src "libresoc.v:192039.7-192039.30" + process $proc$libresoc.v:192039$13317 assign { } { } assign $1\sram4k_2_wb__ack[0:0] 1'0 sync always sync init update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:189758.3-189759.49" - process $proc$libresoc.v:189758$13122 + attribute \src "libresoc.v:192062.3-192063.49" + process $proc$libresoc.v:192062$13306 assign { } { } assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next sync posedge \clk update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:189767.3-189776.6" - process $proc$libresoc.v:189767$13123 + attribute \src "libresoc.v:192071.3-192080.6" + process $proc$libresoc.v:192071$13307 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189768.5-189768.29" + attribute \src "libresoc.v:192072.5-192072.29" switch \initial - attribute \src "libresoc.v:189768.9-189768.17" + attribute \src "libresoc.v:192072.9-192072.17" case 1'1 case end @@ -395952,15 +399961,15 @@ module \sram4k_2 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189777.3-189791.6" - process $proc$libresoc.v:189777$13124 + attribute \src "libresoc.v:192081.3-192095.6" + process $proc$libresoc.v:192081$13308 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_2_wb__ack$next[0:0]$13125 $2\sram4k_2_wb__ack$next[0:0]$13127 - attribute \src "libresoc.v:189778.5-189778.29" + assign $0\sram4k_2_wb__ack$next[0:0]$13309 $2\sram4k_2_wb__ack$next[0:0]$13311 + attribute \src "libresoc.v:192082.5-192082.29" switch \initial - attribute \src "libresoc.v:189778.9-189778.17" + attribute \src "libresoc.v:192082.9-192082.17" case 1'1 case end @@ -395969,30 +399978,30 @@ module \sram4k_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_2_wb__ack$next[0:0]$13126 \wb_active + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \wb_active case - assign $1\sram4k_2_wb__ack$next[0:0]$13126 \sram4k_2_wb__ack + assign $1\sram4k_2_wb__ack$next[0:0]$13310 \sram4k_2_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_2_wb__ack$next[0:0]$13127 1'0 + assign $2\sram4k_2_wb__ack$next[0:0]$13311 1'0 case - assign $2\sram4k_2_wb__ack$next[0:0]$13127 $1\sram4k_2_wb__ack$next[0:0]$13126 + assign $2\sram4k_2_wb__ack$next[0:0]$13311 $1\sram4k_2_wb__ack$next[0:0]$13310 end sync always - update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13125 + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13309 end - attribute \src "libresoc.v:189792.3-189806.6" - process $proc$libresoc.v:189792$13128 + attribute \src "libresoc.v:192096.3-192110.6" + process $proc$libresoc.v:192096$13312 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189793.5-189793.29" + attribute \src "libresoc.v:192097.5-192097.29" switch \initial - attribute \src "libresoc.v:189793.9-189793.17" + attribute \src "libresoc.v:192097.9-192097.17" case 1'1 case end @@ -396017,14 +400026,14 @@ module \sram4k_2 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189807.3-189821.6" - process $proc$libresoc.v:189807$13129 + attribute \src "libresoc.v:192111.3-192125.6" + process $proc$libresoc.v:192111$13313 assign { } { } assign { } { } assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:189808.5-189808.29" + attribute \src "libresoc.v:192112.5-192112.29" switch \initial - attribute \src "libresoc.v:189808.9-189808.17" + attribute \src "libresoc.v:192112.9-192112.17" case 1'1 case end @@ -396049,14 +400058,14 @@ module \sram4k_2 sync always update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] end - attribute \src "libresoc.v:189822.3-189836.6" - process $proc$libresoc.v:189822$13130 + attribute \src "libresoc.v:192126.3-192140.6" + process $proc$libresoc.v:192126$13314 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189823.5-189823.29" + attribute \src "libresoc.v:192127.5-192127.29" switch \initial - attribute \src "libresoc.v:189823.9-189823.17" + attribute \src "libresoc.v:192127.9-192127.17" case 1'1 case end @@ -396081,14 +400090,14 @@ module \sram4k_2 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189837.3-189856.6" - process $proc$libresoc.v:189837$13131 + attribute \src "libresoc.v:192141.3-192160.6" + process $proc$libresoc.v:192141$13315 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189838.5-189838.29" + attribute \src "libresoc.v:192142.5-192142.29" switch \initial - attribute \src "libresoc.v:189838.9-189838.17" + attribute \src "libresoc.v:192142.9-192142.17" case 1'1 case end @@ -396122,72 +400131,72 @@ module \sram4k_2 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189757$13121_Y + connect \$1 $and$libresoc.v:192061$13305_Y end -attribute \src "libresoc.v:189861.1-190001.10" +attribute \src "libresoc.v:192165.1-192305.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" attribute \generator "nMigen" module \sram4k_3 - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:189862.7-189862.20" + attribute \src "libresoc.v:192166.7-192166.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $0\sram4k_3_wb__ack$next[0:0]$13138 - attribute \src "libresoc.v:189902.3-189903.49" + attribute \src "libresoc.v:192225.3-192239.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13322 + attribute \src "libresoc.v:192206.3-192207.49" wire $0\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $0\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189911.3-189920.6" + attribute \src "libresoc.v:192215.3-192224.6" wire $0\wb_active[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $0\we[0:0] - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $1\sram4k_3_wb__ack$next[0:0]$13139 - attribute \src "libresoc.v:189879.7-189879.30" + attribute \src "libresoc.v:192225.3-192239.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13323 + attribute \src "libresoc.v:192183.7-192183.30" wire $1\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189911.3-189920.6" + attribute \src "libresoc.v:192215.3-192224.6" wire $1\wb_active[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $1\we[0:0] - attribute \src "libresoc.v:189936.3-189950.6" + attribute \src "libresoc.v:192240.3-192254.6" wire width 9 $2\a[8:0] - attribute \src "libresoc.v:189966.3-189980.6" + attribute \src "libresoc.v:192270.3-192284.6" wire width 64 $2\d[63:0] - attribute \src "libresoc.v:189921.3-189935.6" - wire $2\sram4k_3_wb__ack$next[0:0]$13140 - attribute \src "libresoc.v:189951.3-189965.6" + attribute \src "libresoc.v:192225.3-192239.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192255.3-192269.6" wire width 64 $2\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $2\we[0:0] - attribute \src "libresoc.v:189981.3-190000.6" + attribute \src "libresoc.v:192285.3-192304.6" wire $3\we[0:0] - attribute \src "libresoc.v:189901.17-189901.129" - wire $and$libresoc.v:189901$13134_Y + attribute \src "libresoc.v:192205.17-192205.129" + wire $and$libresoc.v:192205$13318_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 11 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire input 2 \enable - attribute \src "libresoc.v:189862.7-189862.15" + attribute \src "libresoc.v:192166.7-192166.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" wire output 5 \sram4k_3_wb__ack @@ -396212,7 +400221,7 @@ module \sram4k_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:189901$13134 + cell $and $and$libresoc.v:192205$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -396220,10 +400229,10 @@ module \sram4k_3 parameter \Y_WIDTH 1 connect \A \sram4k_3_wb__cyc connect \B \sram4k_3_wb__stb - connect \Y $and$libresoc.v:189901$13134_Y + connect \Y $and$libresoc.v:192205$13318_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189904.21-189910.4" + attribute \src "libresoc.v:192208.21-192214.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -396231,37 +400240,37 @@ module \sram4k_3 connect \q \q connect \we \we end - attribute \src "libresoc.v:189862.7-189862.20" - process $proc$libresoc.v:189862$13145 + attribute \src "libresoc.v:192166.7-192166.20" + process $proc$libresoc.v:192166$13329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189879.7-189879.30" - process $proc$libresoc.v:189879$13146 + attribute \src "libresoc.v:192183.7-192183.30" + process $proc$libresoc.v:192183$13330 assign { } { } assign $1\sram4k_3_wb__ack[0:0] 1'0 sync always sync init update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:189902.3-189903.49" - process $proc$libresoc.v:189902$13135 + attribute \src "libresoc.v:192206.3-192207.49" + process $proc$libresoc.v:192206$13319 assign { } { } assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next sync posedge \clk update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:189911.3-189920.6" - process $proc$libresoc.v:189911$13136 + attribute \src "libresoc.v:192215.3-192224.6" + process $proc$libresoc.v:192215$13320 assign { } { } assign { } { } assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:189912.5-189912.29" + attribute \src "libresoc.v:192216.5-192216.29" switch \initial - attribute \src "libresoc.v:189912.9-189912.17" + attribute \src "libresoc.v:192216.9-192216.17" case 1'1 case end @@ -396277,15 +400286,15 @@ module \sram4k_3 sync always update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:189921.3-189935.6" - process $proc$libresoc.v:189921$13137 + attribute \src "libresoc.v:192225.3-192239.6" + process $proc$libresoc.v:192225$13321 assign { } { } assign { } { } assign { } { } - assign $0\sram4k_3_wb__ack$next[0:0]$13138 $2\sram4k_3_wb__ack$next[0:0]$13140 - attribute \src "libresoc.v:189922.5-189922.29" + assign $0\sram4k_3_wb__ack$next[0:0]$13322 $2\sram4k_3_wb__ack$next[0:0]$13324 + attribute \src "libresoc.v:192226.5-192226.29" switch \initial - attribute \src "libresoc.v:189922.9-189922.17" + attribute \src "libresoc.v:192226.9-192226.17" case 1'1 case end @@ -396294,30 +400303,30 @@ module \sram4k_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_3_wb__ack$next[0:0]$13139 \wb_active + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \wb_active case - assign $1\sram4k_3_wb__ack$next[0:0]$13139 \sram4k_3_wb__ack + assign $1\sram4k_3_wb__ack$next[0:0]$13323 \sram4k_3_wb__ack end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_3_wb__ack$next[0:0]$13140 1'0 + assign $2\sram4k_3_wb__ack$next[0:0]$13324 1'0 case - assign $2\sram4k_3_wb__ack$next[0:0]$13140 $1\sram4k_3_wb__ack$next[0:0]$13139 + assign $2\sram4k_3_wb__ack$next[0:0]$13324 $1\sram4k_3_wb__ack$next[0:0]$13323 end sync always - update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13138 + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13322 end - attribute \src "libresoc.v:189936.3-189950.6" - process $proc$libresoc.v:189936$13141 + attribute \src "libresoc.v:192240.3-192254.6" + process $proc$libresoc.v:192240$13325 assign { } { } assign { } { } assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:189937.5-189937.29" + attribute \src "libresoc.v:192241.5-192241.29" switch \initial - attribute \src "libresoc.v:189937.9-189937.17" + attribute \src "libresoc.v:192241.9-192241.17" case 1'1 case end @@ -396342,14 +400351,14 @@ module \sram4k_3 sync always update \a $0\a[8:0] end - attribute \src "libresoc.v:189951.3-189965.6" - process $proc$libresoc.v:189951$13142 + attribute \src "libresoc.v:192255.3-192269.6" + process $proc$libresoc.v:192255$13326 assign { } { } assign { } { } assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:189952.5-189952.29" + attribute \src "libresoc.v:192256.5-192256.29" switch \initial - attribute \src "libresoc.v:189952.9-189952.17" + attribute \src "libresoc.v:192256.9-192256.17" case 1'1 case end @@ -396374,14 +400383,14 @@ module \sram4k_3 sync always update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] end - attribute \src "libresoc.v:189966.3-189980.6" - process $proc$libresoc.v:189966$13143 + attribute \src "libresoc.v:192270.3-192284.6" + process $proc$libresoc.v:192270$13327 assign { } { } assign { } { } assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:189967.5-189967.29" + attribute \src "libresoc.v:192271.5-192271.29" switch \initial - attribute \src "libresoc.v:189967.9-189967.17" + attribute \src "libresoc.v:192271.9-192271.17" case 1'1 case end @@ -396406,14 +400415,14 @@ module \sram4k_3 sync always update \d $0\d[63:0] end - attribute \src "libresoc.v:189981.3-190000.6" - process $proc$libresoc.v:189981$13144 + attribute \src "libresoc.v:192285.3-192304.6" + process $proc$libresoc.v:192285$13328 assign { } { } assign { } { } assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:189982.5-189982.29" + attribute \src "libresoc.v:192286.5-192286.29" switch \initial - attribute \src "libresoc.v:189982.9-189982.17" + attribute \src "libresoc.v:192286.9-192286.17" case 1'1 case end @@ -396447,39 +400456,39 @@ module \sram4k_3 sync always update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:189901$13134_Y + connect \$1 $and$libresoc.v:192205$13318_Y end -attribute \src "libresoc.v:190005.1-190063.10" +attribute \src "libresoc.v:192309.1-192367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:190006.7-190006.20" + attribute \src "libresoc.v:192310.7-192310.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190051.3-190059.6" - wire width 4 $0\q_int$next[3:0]$13157 - attribute \src "libresoc.v:190049.3-190050.27" + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $0\q_int$next[3:0]$13341 + attribute \src "libresoc.v:192353.3-192354.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:190051.3-190059.6" - wire width 4 $1\q_int$next[3:0]$13158 - attribute \src "libresoc.v:190028.13-190028.25" + attribute \src "libresoc.v:192355.3-192363.6" + wire width 4 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192332.13-192332.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:190041.17-190041.96" - wire width 4 $and$libresoc.v:190041$13147_Y - attribute \src "libresoc.v:190046.17-190046.96" - wire width 4 $and$libresoc.v:190046$13152_Y - attribute \src "libresoc.v:190043.18-190043.93" - wire width 4 $not$libresoc.v:190043$13149_Y - attribute \src "libresoc.v:190045.17-190045.92" - wire width 4 $not$libresoc.v:190045$13151_Y - attribute \src "libresoc.v:190048.17-190048.92" - wire width 4 $not$libresoc.v:190048$13154_Y - attribute \src "libresoc.v:190042.18-190042.98" - wire width 4 $or$libresoc.v:190042$13148_Y - attribute \src "libresoc.v:190044.18-190044.99" - wire width 4 $or$libresoc.v:190044$13150_Y - attribute \src "libresoc.v:190047.17-190047.97" - wire width 4 $or$libresoc.v:190047$13153_Y + attribute \src "libresoc.v:192345.17-192345.96" + wire width 4 $and$libresoc.v:192345$13331_Y + attribute \src "libresoc.v:192350.17-192350.96" + wire width 4 $and$libresoc.v:192350$13336_Y + attribute \src "libresoc.v:192347.18-192347.93" + wire width 4 $not$libresoc.v:192347$13333_Y + attribute \src "libresoc.v:192349.17-192349.92" + wire width 4 $not$libresoc.v:192349$13335_Y + attribute \src "libresoc.v:192352.17-192352.92" + wire width 4 $not$libresoc.v:192352$13338_Y + attribute \src "libresoc.v:192346.18-192346.98" + wire width 4 $or$libresoc.v:192346$13332_Y + attribute \src "libresoc.v:192348.18-192348.99" + wire width 4 $or$libresoc.v:192348$13334_Y + attribute \src "libresoc.v:192351.17-192351.97" + wire width 4 $or$libresoc.v:192351$13337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396496,11 +400505,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190006.7-190006.15" + attribute \src "libresoc.v:192310.7-192310.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -396517,7 +400526,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190041$13147 + cell $and $and$libresoc.v:192345$13331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396525,10 +400534,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190041$13147_Y + connect \Y $and$libresoc.v:192345$13331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190046$13152 + cell $and $and$libresoc.v:192350$13336 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396536,34 +400545,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190046$13152_Y + connect \Y $and$libresoc.v:192350$13336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190043$13149 + cell $not $not$libresoc.v:192347$13333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:190043$13149_Y + connect \Y $not$libresoc.v:192347$13333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190045$13151 + cell $not $not$libresoc.v:192349$13335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190045$13151_Y + connect \Y $not$libresoc.v:192349$13335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190048$13154 + cell $not $not$libresoc.v:192352$13338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190048$13154_Y + connect \Y $not$libresoc.v:192352$13338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190042$13148 + cell $or $or$libresoc.v:192346$13332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396571,10 +400580,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190042$13148_Y + connect \Y $or$libresoc.v:192346$13332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190044$13150 + cell $or $or$libresoc.v:192348$13334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396582,10 +400591,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190044$13150_Y + connect \Y $or$libresoc.v:192348$13334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190047$13153 + cell $or $or$libresoc.v:192351$13337 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396593,39 +400602,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190047$13153_Y + connect \Y $or$libresoc.v:192351$13337_Y end - attribute \src "libresoc.v:190006.7-190006.20" - process $proc$libresoc.v:190006$13159 + attribute \src "libresoc.v:192310.7-192310.20" + process $proc$libresoc.v:192310$13343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190028.13-190028.25" - process $proc$libresoc.v:190028$13160 + attribute \src "libresoc.v:192332.13-192332.25" + process $proc$libresoc.v:192332$13344 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:190049.3-190050.27" - process $proc$libresoc.v:190049$13155 + attribute \src "libresoc.v:192353.3-192354.27" + process $proc$libresoc.v:192353$13339 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:190051.3-190059.6" - process $proc$libresoc.v:190051$13156 + attribute \src "libresoc.v:192355.3-192363.6" + process $proc$libresoc.v:192355$13340 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13157 $1\q_int$next[3:0]$13158 - attribute \src "libresoc.v:190052.5-190052.29" + assign $0\q_int$next[3:0]$13341 $1\q_int$next[3:0]$13342 + attribute \src "libresoc.v:192356.5-192356.29" switch \initial - attribute \src "libresoc.v:190052.9-190052.17" + attribute \src "libresoc.v:192356.9-192356.17" case 1'1 case end @@ -396634,56 +400643,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13158 4'0000 + assign $1\q_int$next[3:0]$13342 4'0000 case - assign $1\q_int$next[3:0]$13158 \$5 + assign $1\q_int$next[3:0]$13342 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13157 + update \q_int$next $0\q_int$next[3:0]$13341 end - connect \$9 $and$libresoc.v:190041$13147_Y - connect \$11 $or$libresoc.v:190042$13148_Y - connect \$13 $not$libresoc.v:190043$13149_Y - connect \$15 $or$libresoc.v:190044$13150_Y - connect \$1 $not$libresoc.v:190045$13151_Y - connect \$3 $and$libresoc.v:190046$13152_Y - connect \$5 $or$libresoc.v:190047$13153_Y - connect \$7 $not$libresoc.v:190048$13154_Y + connect \$9 $and$libresoc.v:192345$13331_Y + connect \$11 $or$libresoc.v:192346$13332_Y + connect \$13 $not$libresoc.v:192347$13333_Y + connect \$15 $or$libresoc.v:192348$13334_Y + connect \$1 $not$libresoc.v:192349$13335_Y + connect \$3 $and$libresoc.v:192350$13336_Y + connect \$5 $or$libresoc.v:192351$13337_Y + connect \$7 $not$libresoc.v:192352$13338_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190067.1-190125.10" +attribute \src "libresoc.v:192371.1-192429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:190068.7-190068.20" + attribute \src "libresoc.v:192372.7-192372.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190113.3-190121.6" - wire width 6 $0\q_int$next[5:0]$13171 - attribute \src "libresoc.v:190111.3-190112.27" + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $0\q_int$next[5:0]$13355 + attribute \src "libresoc.v:192415.3-192416.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:190113.3-190121.6" - wire width 6 $1\q_int$next[5:0]$13172 - attribute \src "libresoc.v:190090.13-190090.26" + attribute \src "libresoc.v:192417.3-192425.6" + wire width 6 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192394.13-192394.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:190103.17-190103.96" - wire width 6 $and$libresoc.v:190103$13161_Y - attribute \src "libresoc.v:190108.17-190108.96" - wire width 6 $and$libresoc.v:190108$13166_Y - attribute \src "libresoc.v:190105.18-190105.93" - wire width 6 $not$libresoc.v:190105$13163_Y - attribute \src "libresoc.v:190107.17-190107.92" - wire width 6 $not$libresoc.v:190107$13165_Y - attribute \src "libresoc.v:190110.17-190110.92" - wire width 6 $not$libresoc.v:190110$13168_Y - attribute \src "libresoc.v:190104.18-190104.98" - wire width 6 $or$libresoc.v:190104$13162_Y - attribute \src "libresoc.v:190106.18-190106.99" - wire width 6 $or$libresoc.v:190106$13164_Y - attribute \src "libresoc.v:190109.17-190109.97" - wire width 6 $or$libresoc.v:190109$13167_Y + attribute \src "libresoc.v:192407.17-192407.96" + wire width 6 $and$libresoc.v:192407$13345_Y + attribute \src "libresoc.v:192412.17-192412.96" + wire width 6 $and$libresoc.v:192412$13350_Y + attribute \src "libresoc.v:192409.18-192409.93" + wire width 6 $not$libresoc.v:192409$13347_Y + attribute \src "libresoc.v:192411.17-192411.92" + wire width 6 $not$libresoc.v:192411$13349_Y + attribute \src "libresoc.v:192414.17-192414.92" + wire width 6 $not$libresoc.v:192414$13352_Y + attribute \src "libresoc.v:192408.18-192408.98" + wire width 6 $or$libresoc.v:192408$13346_Y + attribute \src "libresoc.v:192410.18-192410.99" + wire width 6 $or$libresoc.v:192410$13348_Y + attribute \src "libresoc.v:192413.17-192413.97" + wire width 6 $or$libresoc.v:192413$13351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396700,11 +400709,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190068.7-190068.15" + attribute \src "libresoc.v:192372.7-192372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -396721,7 +400730,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190103$13161 + cell $and $and$libresoc.v:192407$13345 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396729,10 +400738,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190103$13161_Y + connect \Y $and$libresoc.v:192407$13345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190108$13166 + cell $and $and$libresoc.v:192412$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396740,34 +400749,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190108$13166_Y + connect \Y $and$libresoc.v:192412$13350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190105$13163 + cell $not $not$libresoc.v:192409$13347 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:190105$13163_Y + connect \Y $not$libresoc.v:192409$13347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190107$13165 + cell $not $not$libresoc.v:192411$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190107$13165_Y + connect \Y $not$libresoc.v:192411$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190110$13168 + cell $not $not$libresoc.v:192414$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190110$13168_Y + connect \Y $not$libresoc.v:192414$13352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190104$13162 + cell $or $or$libresoc.v:192408$13346 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396775,10 +400784,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190104$13162_Y + connect \Y $or$libresoc.v:192408$13346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190106$13164 + cell $or $or$libresoc.v:192410$13348 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396786,10 +400795,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190106$13164_Y + connect \Y $or$libresoc.v:192410$13348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190109$13167 + cell $or $or$libresoc.v:192413$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396797,39 +400806,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190109$13167_Y + connect \Y $or$libresoc.v:192413$13351_Y end - attribute \src "libresoc.v:190068.7-190068.20" - process $proc$libresoc.v:190068$13173 + attribute \src "libresoc.v:192372.7-192372.20" + process $proc$libresoc.v:192372$13357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190090.13-190090.26" - process $proc$libresoc.v:190090$13174 + attribute \src "libresoc.v:192394.13-192394.26" + process $proc$libresoc.v:192394$13358 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:190111.3-190112.27" - process $proc$libresoc.v:190111$13169 + attribute \src "libresoc.v:192415.3-192416.27" + process $proc$libresoc.v:192415$13353 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:190113.3-190121.6" - process $proc$libresoc.v:190113$13170 + attribute \src "libresoc.v:192417.3-192425.6" + process $proc$libresoc.v:192417$13354 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13171 $1\q_int$next[5:0]$13172 - attribute \src "libresoc.v:190114.5-190114.29" + assign $0\q_int$next[5:0]$13355 $1\q_int$next[5:0]$13356 + attribute \src "libresoc.v:192418.5-192418.29" switch \initial - attribute \src "libresoc.v:190114.9-190114.17" + attribute \src "libresoc.v:192418.9-192418.17" case 1'1 case end @@ -396838,56 +400847,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13172 6'000000 + assign $1\q_int$next[5:0]$13356 6'000000 case - assign $1\q_int$next[5:0]$13172 \$5 + assign $1\q_int$next[5:0]$13356 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13171 + update \q_int$next $0\q_int$next[5:0]$13355 end - connect \$9 $and$libresoc.v:190103$13161_Y - connect \$11 $or$libresoc.v:190104$13162_Y - connect \$13 $not$libresoc.v:190105$13163_Y - connect \$15 $or$libresoc.v:190106$13164_Y - connect \$1 $not$libresoc.v:190107$13165_Y - connect \$3 $and$libresoc.v:190108$13166_Y - connect \$5 $or$libresoc.v:190109$13167_Y - connect \$7 $not$libresoc.v:190110$13168_Y + connect \$9 $and$libresoc.v:192407$13345_Y + connect \$11 $or$libresoc.v:192408$13346_Y + connect \$13 $not$libresoc.v:192409$13347_Y + connect \$15 $or$libresoc.v:192410$13348_Y + connect \$1 $not$libresoc.v:192411$13349_Y + connect \$3 $and$libresoc.v:192412$13350_Y + connect \$5 $or$libresoc.v:192413$13351_Y + connect \$7 $not$libresoc.v:192414$13352_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190129.1-190187.10" +attribute \src "libresoc.v:192433.1-192491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:190130.7-190130.20" + attribute \src "libresoc.v:192434.7-192434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190175.3-190183.6" - wire width 3 $0\q_int$next[2:0]$13185 - attribute \src "libresoc.v:190173.3-190174.27" + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $0\q_int$next[2:0]$13369 + attribute \src "libresoc.v:192477.3-192478.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190175.3-190183.6" - wire width 3 $1\q_int$next[2:0]$13186 - attribute \src "libresoc.v:190152.13-190152.25" + attribute \src "libresoc.v:192479.3-192487.6" + wire width 3 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192456.13-192456.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190165.17-190165.96" - wire width 3 $and$libresoc.v:190165$13175_Y - attribute \src "libresoc.v:190170.17-190170.96" - wire width 3 $and$libresoc.v:190170$13180_Y - attribute \src "libresoc.v:190167.18-190167.93" - wire width 3 $not$libresoc.v:190167$13177_Y - attribute \src "libresoc.v:190169.17-190169.92" - wire width 3 $not$libresoc.v:190169$13179_Y - attribute \src "libresoc.v:190172.17-190172.92" - wire width 3 $not$libresoc.v:190172$13182_Y - attribute \src "libresoc.v:190166.18-190166.98" - wire width 3 $or$libresoc.v:190166$13176_Y - attribute \src "libresoc.v:190168.18-190168.99" - wire width 3 $or$libresoc.v:190168$13178_Y - attribute \src "libresoc.v:190171.17-190171.97" - wire width 3 $or$libresoc.v:190171$13181_Y + attribute \src "libresoc.v:192469.17-192469.96" + wire width 3 $and$libresoc.v:192469$13359_Y + attribute \src "libresoc.v:192474.17-192474.96" + wire width 3 $and$libresoc.v:192474$13364_Y + attribute \src "libresoc.v:192471.18-192471.93" + wire width 3 $not$libresoc.v:192471$13361_Y + attribute \src "libresoc.v:192473.17-192473.92" + wire width 3 $not$libresoc.v:192473$13363_Y + attribute \src "libresoc.v:192476.17-192476.92" + wire width 3 $not$libresoc.v:192476$13366_Y + attribute \src "libresoc.v:192470.18-192470.98" + wire width 3 $or$libresoc.v:192470$13360_Y + attribute \src "libresoc.v:192472.18-192472.99" + wire width 3 $or$libresoc.v:192472$13362_Y + attribute \src "libresoc.v:192475.17-192475.97" + wire width 3 $or$libresoc.v:192475$13365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396904,11 +400913,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190130.7-190130.15" + attribute \src "libresoc.v:192434.7-192434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -396925,7 +400934,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190165$13175 + cell $and $and$libresoc.v:192469$13359 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396933,10 +400942,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190165$13175_Y + connect \Y $and$libresoc.v:192469$13359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190170$13180 + cell $and $and$libresoc.v:192474$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396944,34 +400953,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190170$13180_Y + connect \Y $and$libresoc.v:192474$13364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190167$13177 + cell $not $not$libresoc.v:192471$13361 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190167$13177_Y + connect \Y $not$libresoc.v:192471$13361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190169$13179 + cell $not $not$libresoc.v:192473$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190169$13179_Y + connect \Y $not$libresoc.v:192473$13363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190172$13182 + cell $not $not$libresoc.v:192476$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190172$13182_Y + connect \Y $not$libresoc.v:192476$13366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190166$13176 + cell $or $or$libresoc.v:192470$13360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396979,10 +400988,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190166$13176_Y + connect \Y $or$libresoc.v:192470$13360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190168$13178 + cell $or $or$libresoc.v:192472$13362 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396990,10 +400999,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190168$13178_Y + connect \Y $or$libresoc.v:192472$13362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190171$13181 + cell $or $or$libresoc.v:192475$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397001,39 +401010,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190171$13181_Y + connect \Y $or$libresoc.v:192475$13365_Y end - attribute \src "libresoc.v:190130.7-190130.20" - process $proc$libresoc.v:190130$13187 + attribute \src "libresoc.v:192434.7-192434.20" + process $proc$libresoc.v:192434$13371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190152.13-190152.25" - process $proc$libresoc.v:190152$13188 + attribute \src "libresoc.v:192456.13-192456.25" + process $proc$libresoc.v:192456$13372 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190173.3-190174.27" - process $proc$libresoc.v:190173$13183 + attribute \src "libresoc.v:192477.3-192478.27" + process $proc$libresoc.v:192477$13367 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190175.3-190183.6" - process $proc$libresoc.v:190175$13184 + attribute \src "libresoc.v:192479.3-192487.6" + process $proc$libresoc.v:192479$13368 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186 - attribute \src "libresoc.v:190176.5-190176.29" + assign $0\q_int$next[2:0]$13369 $1\q_int$next[2:0]$13370 + attribute \src "libresoc.v:192480.5-192480.29" switch \initial - attribute \src "libresoc.v:190176.9-190176.17" + attribute \src "libresoc.v:192480.9-192480.17" case 1'1 case end @@ -397042,56 +401051,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13186 3'000 + assign $1\q_int$next[2:0]$13370 3'000 case - assign $1\q_int$next[2:0]$13186 \$5 + assign $1\q_int$next[2:0]$13370 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13185 + update \q_int$next $0\q_int$next[2:0]$13369 end - connect \$9 $and$libresoc.v:190165$13175_Y - connect \$11 $or$libresoc.v:190166$13176_Y - connect \$13 $not$libresoc.v:190167$13177_Y - connect \$15 $or$libresoc.v:190168$13178_Y - connect \$1 $not$libresoc.v:190169$13179_Y - connect \$3 $and$libresoc.v:190170$13180_Y - connect \$5 $or$libresoc.v:190171$13181_Y - connect \$7 $not$libresoc.v:190172$13182_Y + connect \$9 $and$libresoc.v:192469$13359_Y + connect \$11 $or$libresoc.v:192470$13360_Y + connect \$13 $not$libresoc.v:192471$13361_Y + connect \$15 $or$libresoc.v:192472$13362_Y + connect \$1 $not$libresoc.v:192473$13363_Y + connect \$3 $and$libresoc.v:192474$13364_Y + connect \$5 $or$libresoc.v:192475$13365_Y + connect \$7 $not$libresoc.v:192476$13366_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190191.1-190249.10" +attribute \src "libresoc.v:192495.1-192553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:190192.7-190192.20" + attribute \src "libresoc.v:192496.7-192496.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190237.3-190245.6" - wire width 5 $0\q_int$next[4:0]$13199 - attribute \src "libresoc.v:190235.3-190236.27" + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $0\q_int$next[4:0]$13383 + attribute \src "libresoc.v:192539.3-192540.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:190237.3-190245.6" - wire width 5 $1\q_int$next[4:0]$13200 - attribute \src "libresoc.v:190214.13-190214.26" + attribute \src "libresoc.v:192541.3-192549.6" + wire width 5 $1\q_int$next[4:0]$13384 + attribute \src "libresoc.v:192518.13-192518.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:190227.17-190227.96" - wire width 5 $and$libresoc.v:190227$13189_Y - attribute \src "libresoc.v:190232.17-190232.96" - wire width 5 $and$libresoc.v:190232$13194_Y - attribute \src "libresoc.v:190229.18-190229.93" - wire width 5 $not$libresoc.v:190229$13191_Y - attribute \src "libresoc.v:190231.17-190231.92" - wire width 5 $not$libresoc.v:190231$13193_Y - attribute \src "libresoc.v:190234.17-190234.92" - wire width 5 $not$libresoc.v:190234$13196_Y - attribute \src "libresoc.v:190228.18-190228.98" - wire width 5 $or$libresoc.v:190228$13190_Y - attribute \src "libresoc.v:190230.18-190230.99" - wire width 5 $or$libresoc.v:190230$13192_Y - attribute \src "libresoc.v:190233.17-190233.97" - wire width 5 $or$libresoc.v:190233$13195_Y + attribute \src "libresoc.v:192531.17-192531.96" + wire width 5 $and$libresoc.v:192531$13373_Y + attribute \src "libresoc.v:192536.17-192536.96" + wire width 5 $and$libresoc.v:192536$13378_Y + attribute \src "libresoc.v:192533.18-192533.93" + wire width 5 $not$libresoc.v:192533$13375_Y + attribute \src "libresoc.v:192535.17-192535.92" + wire width 5 $not$libresoc.v:192535$13377_Y + attribute \src "libresoc.v:192538.17-192538.92" + wire width 5 $not$libresoc.v:192538$13380_Y + attribute \src "libresoc.v:192532.18-192532.98" + wire width 5 $or$libresoc.v:192532$13374_Y + attribute \src "libresoc.v:192534.18-192534.99" + wire width 5 $or$libresoc.v:192534$13376_Y + attribute \src "libresoc.v:192537.17-192537.97" + wire width 5 $or$libresoc.v:192537$13379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397108,11 +401117,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190192.7-190192.15" + attribute \src "libresoc.v:192496.7-192496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -397129,7 +401138,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190227$13189 + cell $and $and$libresoc.v:192531$13373 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397137,10 +401146,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190227$13189_Y + connect \Y $and$libresoc.v:192531$13373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190232$13194 + cell $and $and$libresoc.v:192536$13378 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397148,34 +401157,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190232$13194_Y + connect \Y $and$libresoc.v:192536$13378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190229$13191 + cell $not $not$libresoc.v:192533$13375 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:190229$13191_Y + connect \Y $not$libresoc.v:192533$13375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190231$13193 + cell $not $not$libresoc.v:192535$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:190231$13193_Y + connect \Y $not$libresoc.v:192535$13377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190234$13196 + cell $not $not$libresoc.v:192538$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:190234$13196_Y + connect \Y $not$libresoc.v:192538$13380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190228$13190 + cell $or $or$libresoc.v:192532$13374 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397183,10 +401192,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190228$13190_Y + connect \Y $or$libresoc.v:192532$13374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190230$13192 + cell $or $or$libresoc.v:192534$13376 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397194,10 +401203,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190230$13192_Y + connect \Y $or$libresoc.v:192534$13376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190233$13195 + cell $or $or$libresoc.v:192537$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -397205,39 +401214,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190233$13195_Y + connect \Y $or$libresoc.v:192537$13379_Y end - attribute \src "libresoc.v:190192.7-190192.20" - process $proc$libresoc.v:190192$13201 + attribute \src "libresoc.v:192496.7-192496.20" + process $proc$libresoc.v:192496$13385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190214.13-190214.26" - process $proc$libresoc.v:190214$13202 + attribute \src "libresoc.v:192518.13-192518.26" + process $proc$libresoc.v:192518$13386 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:190235.3-190236.27" - process $proc$libresoc.v:190235$13197 + attribute \src "libresoc.v:192539.3-192540.27" + process $proc$libresoc.v:192539$13381 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:190237.3-190245.6" - process $proc$libresoc.v:190237$13198 + attribute \src "libresoc.v:192541.3-192549.6" + process $proc$libresoc.v:192541$13382 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13199 $1\q_int$next[4:0]$13200 - attribute \src "libresoc.v:190238.5-190238.29" + assign $0\q_int$next[4:0]$13383 $1\q_int$next[4:0]$13384 + attribute \src "libresoc.v:192542.5-192542.29" switch \initial - attribute \src "libresoc.v:190238.9-190238.17" + attribute \src "libresoc.v:192542.9-192542.17" case 1'1 case end @@ -397246,56 +401255,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13200 5'00000 + assign $1\q_int$next[4:0]$13384 5'00000 case - assign $1\q_int$next[4:0]$13200 \$5 + assign $1\q_int$next[4:0]$13384 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13199 + update \q_int$next $0\q_int$next[4:0]$13383 end - connect \$9 $and$libresoc.v:190227$13189_Y - connect \$11 $or$libresoc.v:190228$13190_Y - connect \$13 $not$libresoc.v:190229$13191_Y - connect \$15 $or$libresoc.v:190230$13192_Y - connect \$1 $not$libresoc.v:190231$13193_Y - connect \$3 $and$libresoc.v:190232$13194_Y - connect \$5 $or$libresoc.v:190233$13195_Y - connect \$7 $not$libresoc.v:190234$13196_Y + connect \$9 $and$libresoc.v:192531$13373_Y + connect \$11 $or$libresoc.v:192532$13374_Y + connect \$13 $not$libresoc.v:192533$13375_Y + connect \$15 $or$libresoc.v:192534$13376_Y + connect \$1 $not$libresoc.v:192535$13377_Y + connect \$3 $and$libresoc.v:192536$13378_Y + connect \$5 $or$libresoc.v:192537$13379_Y + connect \$7 $not$libresoc.v:192538$13380_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190253.1-190311.10" +attribute \src "libresoc.v:192557.1-192615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:190254.7-190254.20" + attribute \src "libresoc.v:192558.7-192558.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190299.3-190307.6" - wire width 3 $0\q_int$next[2:0]$13213 - attribute \src "libresoc.v:190297.3-190298.27" + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $0\q_int$next[2:0]$13397 + attribute \src "libresoc.v:192601.3-192602.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190299.3-190307.6" - wire width 3 $1\q_int$next[2:0]$13214 - attribute \src "libresoc.v:190276.13-190276.25" + attribute \src "libresoc.v:192603.3-192611.6" + wire width 3 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192580.13-192580.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190289.17-190289.96" - wire width 3 $and$libresoc.v:190289$13203_Y - attribute \src "libresoc.v:190294.17-190294.96" - wire width 3 $and$libresoc.v:190294$13208_Y - attribute \src "libresoc.v:190291.18-190291.93" - wire width 3 $not$libresoc.v:190291$13205_Y - attribute \src "libresoc.v:190293.17-190293.92" - wire width 3 $not$libresoc.v:190293$13207_Y - attribute \src "libresoc.v:190296.17-190296.92" - wire width 3 $not$libresoc.v:190296$13210_Y - attribute \src "libresoc.v:190290.18-190290.98" - wire width 3 $or$libresoc.v:190290$13204_Y - attribute \src "libresoc.v:190292.18-190292.99" - wire width 3 $or$libresoc.v:190292$13206_Y - attribute \src "libresoc.v:190295.17-190295.97" - wire width 3 $or$libresoc.v:190295$13209_Y + attribute \src "libresoc.v:192593.17-192593.96" + wire width 3 $and$libresoc.v:192593$13387_Y + attribute \src "libresoc.v:192598.17-192598.96" + wire width 3 $and$libresoc.v:192598$13392_Y + attribute \src "libresoc.v:192595.18-192595.93" + wire width 3 $not$libresoc.v:192595$13389_Y + attribute \src "libresoc.v:192597.17-192597.92" + wire width 3 $not$libresoc.v:192597$13391_Y + attribute \src "libresoc.v:192600.17-192600.92" + wire width 3 $not$libresoc.v:192600$13394_Y + attribute \src "libresoc.v:192594.18-192594.98" + wire width 3 $or$libresoc.v:192594$13388_Y + attribute \src "libresoc.v:192596.18-192596.99" + wire width 3 $or$libresoc.v:192596$13390_Y + attribute \src "libresoc.v:192599.17-192599.97" + wire width 3 $or$libresoc.v:192599$13393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397312,11 +401321,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190254.7-190254.15" + attribute \src "libresoc.v:192558.7-192558.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397333,7 +401342,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190289$13203 + cell $and $and$libresoc.v:192593$13387 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397341,10 +401350,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190289$13203_Y + connect \Y $and$libresoc.v:192593$13387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190294$13208 + cell $and $and$libresoc.v:192598$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397352,34 +401361,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190294$13208_Y + connect \Y $and$libresoc.v:192598$13392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190291$13205 + cell $not $not$libresoc.v:192595$13389 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190291$13205_Y + connect \Y $not$libresoc.v:192595$13389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190293$13207 + cell $not $not$libresoc.v:192597$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190293$13207_Y + connect \Y $not$libresoc.v:192597$13391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190296$13210 + cell $not $not$libresoc.v:192600$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190296$13210_Y + connect \Y $not$libresoc.v:192600$13394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190290$13204 + cell $or $or$libresoc.v:192594$13388 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397387,10 +401396,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190290$13204_Y + connect \Y $or$libresoc.v:192594$13388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190292$13206 + cell $or $or$libresoc.v:192596$13390 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397398,10 +401407,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190292$13206_Y + connect \Y $or$libresoc.v:192596$13390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190295$13209 + cell $or $or$libresoc.v:192599$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397409,39 +401418,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190295$13209_Y + connect \Y $or$libresoc.v:192599$13393_Y end - attribute \src "libresoc.v:190254.7-190254.20" - process $proc$libresoc.v:190254$13215 + attribute \src "libresoc.v:192558.7-192558.20" + process $proc$libresoc.v:192558$13399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190276.13-190276.25" - process $proc$libresoc.v:190276$13216 + attribute \src "libresoc.v:192580.13-192580.25" + process $proc$libresoc.v:192580$13400 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190297.3-190298.27" - process $proc$libresoc.v:190297$13211 + attribute \src "libresoc.v:192601.3-192602.27" + process $proc$libresoc.v:192601$13395 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190299.3-190307.6" - process $proc$libresoc.v:190299$13212 + attribute \src "libresoc.v:192603.3-192611.6" + process $proc$libresoc.v:192603$13396 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214 - attribute \src "libresoc.v:190300.5-190300.29" + assign $0\q_int$next[2:0]$13397 $1\q_int$next[2:0]$13398 + attribute \src "libresoc.v:192604.5-192604.29" switch \initial - attribute \src "libresoc.v:190300.9-190300.17" + attribute \src "libresoc.v:192604.9-192604.17" case 1'1 case end @@ -397450,56 +401459,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13214 3'000 + assign $1\q_int$next[2:0]$13398 3'000 case - assign $1\q_int$next[2:0]$13214 \$5 + assign $1\q_int$next[2:0]$13398 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13213 + update \q_int$next $0\q_int$next[2:0]$13397 end - connect \$9 $and$libresoc.v:190289$13203_Y - connect \$11 $or$libresoc.v:190290$13204_Y - connect \$13 $not$libresoc.v:190291$13205_Y - connect \$15 $or$libresoc.v:190292$13206_Y - connect \$1 $not$libresoc.v:190293$13207_Y - connect \$3 $and$libresoc.v:190294$13208_Y - connect \$5 $or$libresoc.v:190295$13209_Y - connect \$7 $not$libresoc.v:190296$13210_Y + connect \$9 $and$libresoc.v:192593$13387_Y + connect \$11 $or$libresoc.v:192594$13388_Y + connect \$13 $not$libresoc.v:192595$13389_Y + connect \$15 $or$libresoc.v:192596$13390_Y + connect \$1 $not$libresoc.v:192597$13391_Y + connect \$3 $and$libresoc.v:192598$13392_Y + connect \$5 $or$libresoc.v:192599$13393_Y + connect \$7 $not$libresoc.v:192600$13394_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190315.1-190373.10" +attribute \src "libresoc.v:192619.1-192677.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:190316.7-190316.20" + attribute \src "libresoc.v:192620.7-192620.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190361.3-190369.6" - wire width 3 $0\q_int$next[2:0]$13227 - attribute \src "libresoc.v:190359.3-190360.27" + attribute \src "libresoc.v:192665.3-192673.6" + wire width 3 $0\q_int$next[2:0]$13411 + attribute \src "libresoc.v:192663.3-192664.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190361.3-190369.6" - wire width 3 $1\q_int$next[2:0]$13228 - attribute \src "libresoc.v:190338.13-190338.25" + attribute \src "libresoc.v:192665.3-192673.6" + wire width 3 $1\q_int$next[2:0]$13412 + attribute \src "libresoc.v:192642.13-192642.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190351.17-190351.96" - wire width 3 $and$libresoc.v:190351$13217_Y - attribute \src "libresoc.v:190356.17-190356.96" - wire width 3 $and$libresoc.v:190356$13222_Y - attribute \src "libresoc.v:190353.18-190353.93" - wire width 3 $not$libresoc.v:190353$13219_Y - attribute \src "libresoc.v:190355.17-190355.92" - wire width 3 $not$libresoc.v:190355$13221_Y - attribute \src "libresoc.v:190358.17-190358.92" - wire width 3 $not$libresoc.v:190358$13224_Y - attribute \src "libresoc.v:190352.18-190352.98" - wire width 3 $or$libresoc.v:190352$13218_Y - attribute \src "libresoc.v:190354.18-190354.99" - wire width 3 $or$libresoc.v:190354$13220_Y - attribute \src "libresoc.v:190357.17-190357.97" - wire width 3 $or$libresoc.v:190357$13223_Y + attribute \src "libresoc.v:192655.17-192655.96" + wire width 3 $and$libresoc.v:192655$13401_Y + attribute \src "libresoc.v:192660.17-192660.96" + wire width 3 $and$libresoc.v:192660$13406_Y + attribute \src "libresoc.v:192657.18-192657.93" + wire width 3 $not$libresoc.v:192657$13403_Y + attribute \src "libresoc.v:192659.17-192659.92" + wire width 3 $not$libresoc.v:192659$13405_Y + attribute \src "libresoc.v:192662.17-192662.92" + wire width 3 $not$libresoc.v:192662$13408_Y + attribute \src "libresoc.v:192656.18-192656.98" + wire width 3 $or$libresoc.v:192656$13402_Y + attribute \src "libresoc.v:192658.18-192658.99" + wire width 3 $or$libresoc.v:192658$13404_Y + attribute \src "libresoc.v:192661.17-192661.97" + wire width 3 $or$libresoc.v:192661$13407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397516,11 +401525,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190316.7-190316.15" + attribute \src "libresoc.v:192620.7-192620.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397537,7 +401546,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190351$13217 + cell $and $and$libresoc.v:192655$13401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397545,10 +401554,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190351$13217_Y + connect \Y $and$libresoc.v:192655$13401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190356$13222 + cell $and $and$libresoc.v:192660$13406 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397556,34 +401565,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190356$13222_Y + connect \Y $and$libresoc.v:192660$13406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190353$13219 + cell $not $not$libresoc.v:192657$13403 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190353$13219_Y + connect \Y $not$libresoc.v:192657$13403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190355$13221 + cell $not $not$libresoc.v:192659$13405 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190355$13221_Y + connect \Y $not$libresoc.v:192659$13405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190358$13224 + cell $not $not$libresoc.v:192662$13408 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190358$13224_Y + connect \Y $not$libresoc.v:192662$13408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190352$13218 + cell $or $or$libresoc.v:192656$13402 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397591,10 +401600,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190352$13218_Y + connect \Y $or$libresoc.v:192656$13402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190354$13220 + cell $or $or$libresoc.v:192658$13404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397602,10 +401611,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190354$13220_Y + connect \Y $or$libresoc.v:192658$13404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190357$13223 + cell $or $or$libresoc.v:192661$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397613,39 +401622,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190357$13223_Y + connect \Y $or$libresoc.v:192661$13407_Y end - attribute \src "libresoc.v:190316.7-190316.20" - process $proc$libresoc.v:190316$13229 + attribute \src "libresoc.v:192620.7-192620.20" + process $proc$libresoc.v:192620$13413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190338.13-190338.25" - process $proc$libresoc.v:190338$13230 + attribute \src "libresoc.v:192642.13-192642.25" + process $proc$libresoc.v:192642$13414 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190359.3-190360.27" - process $proc$libresoc.v:190359$13225 + attribute \src "libresoc.v:192663.3-192664.27" + process $proc$libresoc.v:192663$13409 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190361.3-190369.6" - process $proc$libresoc.v:190361$13226 + attribute \src "libresoc.v:192665.3-192673.6" + process $proc$libresoc.v:192665$13410 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13227 $1\q_int$next[2:0]$13228 - attribute \src "libresoc.v:190362.5-190362.29" + assign $0\q_int$next[2:0]$13411 $1\q_int$next[2:0]$13412 + attribute \src "libresoc.v:192666.5-192666.29" switch \initial - attribute \src "libresoc.v:190362.9-190362.17" + attribute \src "libresoc.v:192666.9-192666.17" case 1'1 case end @@ -397654,56 +401663,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13228 3'000 + assign $1\q_int$next[2:0]$13412 3'000 case - assign $1\q_int$next[2:0]$13228 \$5 + assign $1\q_int$next[2:0]$13412 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13227 + update \q_int$next $0\q_int$next[2:0]$13411 end - connect \$9 $and$libresoc.v:190351$13217_Y - connect \$11 $or$libresoc.v:190352$13218_Y - connect \$13 $not$libresoc.v:190353$13219_Y - connect \$15 $or$libresoc.v:190354$13220_Y - connect \$1 $not$libresoc.v:190355$13221_Y - connect \$3 $and$libresoc.v:190356$13222_Y - connect \$5 $or$libresoc.v:190357$13223_Y - connect \$7 $not$libresoc.v:190358$13224_Y + connect \$9 $and$libresoc.v:192655$13401_Y + connect \$11 $or$libresoc.v:192656$13402_Y + connect \$13 $not$libresoc.v:192657$13403_Y + connect \$15 $or$libresoc.v:192658$13404_Y + connect \$1 $not$libresoc.v:192659$13405_Y + connect \$3 $and$libresoc.v:192660$13406_Y + connect \$5 $or$libresoc.v:192661$13407_Y + connect \$7 $not$libresoc.v:192662$13408_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190377.1-190435.10" +attribute \src "libresoc.v:192681.1-192739.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:190378.7-190378.20" + attribute \src "libresoc.v:192682.7-192682.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190423.3-190431.6" - wire width 4 $0\q_int$next[3:0]$13241 - attribute \src "libresoc.v:190421.3-190422.27" + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $0\q_int$next[3:0]$13425 + attribute \src "libresoc.v:192725.3-192726.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:190423.3-190431.6" - wire width 4 $1\q_int$next[3:0]$13242 - attribute \src "libresoc.v:190400.13-190400.25" + attribute \src "libresoc.v:192727.3-192735.6" + wire width 4 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192704.13-192704.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:190413.17-190413.96" - wire width 4 $and$libresoc.v:190413$13231_Y - attribute \src "libresoc.v:190418.17-190418.96" - wire width 4 $and$libresoc.v:190418$13236_Y - attribute \src "libresoc.v:190415.18-190415.93" - wire width 4 $not$libresoc.v:190415$13233_Y - attribute \src "libresoc.v:190417.17-190417.92" - wire width 4 $not$libresoc.v:190417$13235_Y - attribute \src "libresoc.v:190420.17-190420.92" - wire width 4 $not$libresoc.v:190420$13238_Y - attribute \src "libresoc.v:190414.18-190414.98" - wire width 4 $or$libresoc.v:190414$13232_Y - attribute \src "libresoc.v:190416.18-190416.99" - wire width 4 $or$libresoc.v:190416$13234_Y - attribute \src "libresoc.v:190419.17-190419.97" - wire width 4 $or$libresoc.v:190419$13237_Y + attribute \src "libresoc.v:192717.17-192717.96" + wire width 4 $and$libresoc.v:192717$13415_Y + attribute \src "libresoc.v:192722.17-192722.96" + wire width 4 $and$libresoc.v:192722$13420_Y + attribute \src "libresoc.v:192719.18-192719.93" + wire width 4 $not$libresoc.v:192719$13417_Y + attribute \src "libresoc.v:192721.17-192721.92" + wire width 4 $not$libresoc.v:192721$13419_Y + attribute \src "libresoc.v:192724.17-192724.92" + wire width 4 $not$libresoc.v:192724$13422_Y + attribute \src "libresoc.v:192718.18-192718.98" + wire width 4 $or$libresoc.v:192718$13416_Y + attribute \src "libresoc.v:192720.18-192720.99" + wire width 4 $or$libresoc.v:192720$13418_Y + attribute \src "libresoc.v:192723.17-192723.97" + wire width 4 $or$libresoc.v:192723$13421_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397720,11 +401729,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190378.7-190378.15" + attribute \src "libresoc.v:192682.7-192682.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -397741,7 +401750,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190413$13231 + cell $and $and$libresoc.v:192717$13415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397749,10 +401758,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190413$13231_Y + connect \Y $and$libresoc.v:192717$13415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190418$13236 + cell $and $and$libresoc.v:192722$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397760,34 +401769,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190418$13236_Y + connect \Y $and$libresoc.v:192722$13420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190415$13233 + cell $not $not$libresoc.v:192719$13417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:190415$13233_Y + connect \Y $not$libresoc.v:192719$13417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190417$13235 + cell $not $not$libresoc.v:192721$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190417$13235_Y + connect \Y $not$libresoc.v:192721$13419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190420$13238 + cell $not $not$libresoc.v:192724$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:190420$13238_Y + connect \Y $not$libresoc.v:192724$13422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190414$13232 + cell $or $or$libresoc.v:192718$13416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397795,10 +401804,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190414$13232_Y + connect \Y $or$libresoc.v:192718$13416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190416$13234 + cell $or $or$libresoc.v:192720$13418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397806,10 +401815,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190416$13234_Y + connect \Y $or$libresoc.v:192720$13418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190419$13237 + cell $or $or$libresoc.v:192723$13421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397817,39 +401826,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190419$13237_Y + connect \Y $or$libresoc.v:192723$13421_Y end - attribute \src "libresoc.v:190378.7-190378.20" - process $proc$libresoc.v:190378$13243 + attribute \src "libresoc.v:192682.7-192682.20" + process $proc$libresoc.v:192682$13427 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190400.13-190400.25" - process $proc$libresoc.v:190400$13244 + attribute \src "libresoc.v:192704.13-192704.25" + process $proc$libresoc.v:192704$13428 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:190421.3-190422.27" - process $proc$libresoc.v:190421$13239 + attribute \src "libresoc.v:192725.3-192726.27" + process $proc$libresoc.v:192725$13423 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:190423.3-190431.6" - process $proc$libresoc.v:190423$13240 + attribute \src "libresoc.v:192727.3-192735.6" + process $proc$libresoc.v:192727$13424 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13241 $1\q_int$next[3:0]$13242 - attribute \src "libresoc.v:190424.5-190424.29" + assign $0\q_int$next[3:0]$13425 $1\q_int$next[3:0]$13426 + attribute \src "libresoc.v:192728.5-192728.29" switch \initial - attribute \src "libresoc.v:190424.9-190424.17" + attribute \src "libresoc.v:192728.9-192728.17" case 1'1 case end @@ -397858,56 +401867,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13242 4'0000 + assign $1\q_int$next[3:0]$13426 4'0000 case - assign $1\q_int$next[3:0]$13242 \$5 + assign $1\q_int$next[3:0]$13426 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13241 + update \q_int$next $0\q_int$next[3:0]$13425 end - connect \$9 $and$libresoc.v:190413$13231_Y - connect \$11 $or$libresoc.v:190414$13232_Y - connect \$13 $not$libresoc.v:190415$13233_Y - connect \$15 $or$libresoc.v:190416$13234_Y - connect \$1 $not$libresoc.v:190417$13235_Y - connect \$3 $and$libresoc.v:190418$13236_Y - connect \$5 $or$libresoc.v:190419$13237_Y - connect \$7 $not$libresoc.v:190420$13238_Y + connect \$9 $and$libresoc.v:192717$13415_Y + connect \$11 $or$libresoc.v:192718$13416_Y + connect \$13 $not$libresoc.v:192719$13417_Y + connect \$15 $or$libresoc.v:192720$13418_Y + connect \$1 $not$libresoc.v:192721$13419_Y + connect \$3 $and$libresoc.v:192722$13420_Y + connect \$5 $or$libresoc.v:192723$13421_Y + connect \$7 $not$libresoc.v:192724$13422_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190439.1-190497.10" +attribute \src "libresoc.v:192743.1-192801.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:190440.7-190440.20" + attribute \src "libresoc.v:192744.7-192744.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190485.3-190493.6" - wire width 3 $0\q_int$next[2:0]$13255 - attribute \src "libresoc.v:190483.3-190484.27" + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $0\q_int$next[2:0]$13439 + attribute \src "libresoc.v:192787.3-192788.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190485.3-190493.6" - wire width 3 $1\q_int$next[2:0]$13256 - attribute \src "libresoc.v:190462.13-190462.25" + attribute \src "libresoc.v:192789.3-192797.6" + wire width 3 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192766.13-192766.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190475.17-190475.96" - wire width 3 $and$libresoc.v:190475$13245_Y - attribute \src "libresoc.v:190480.17-190480.96" - wire width 3 $and$libresoc.v:190480$13250_Y - attribute \src "libresoc.v:190477.18-190477.93" - wire width 3 $not$libresoc.v:190477$13247_Y - attribute \src "libresoc.v:190479.17-190479.92" - wire width 3 $not$libresoc.v:190479$13249_Y - attribute \src "libresoc.v:190482.17-190482.92" - wire width 3 $not$libresoc.v:190482$13252_Y - attribute \src "libresoc.v:190476.18-190476.98" - wire width 3 $or$libresoc.v:190476$13246_Y - attribute \src "libresoc.v:190478.18-190478.99" - wire width 3 $or$libresoc.v:190478$13248_Y - attribute \src "libresoc.v:190481.17-190481.97" - wire width 3 $or$libresoc.v:190481$13251_Y + attribute \src "libresoc.v:192779.17-192779.96" + wire width 3 $and$libresoc.v:192779$13429_Y + attribute \src "libresoc.v:192784.17-192784.96" + wire width 3 $and$libresoc.v:192784$13434_Y + attribute \src "libresoc.v:192781.18-192781.93" + wire width 3 $not$libresoc.v:192781$13431_Y + attribute \src "libresoc.v:192783.17-192783.92" + wire width 3 $not$libresoc.v:192783$13433_Y + attribute \src "libresoc.v:192786.17-192786.92" + wire width 3 $not$libresoc.v:192786$13436_Y + attribute \src "libresoc.v:192780.18-192780.98" + wire width 3 $or$libresoc.v:192780$13430_Y + attribute \src "libresoc.v:192782.18-192782.99" + wire width 3 $or$libresoc.v:192782$13432_Y + attribute \src "libresoc.v:192785.17-192785.97" + wire width 3 $or$libresoc.v:192785$13435_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397924,11 +401933,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190440.7-190440.15" + attribute \src "libresoc.v:192744.7-192744.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397945,7 +401954,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190475$13245 + cell $and $and$libresoc.v:192779$13429 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397953,10 +401962,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190475$13245_Y + connect \Y $and$libresoc.v:192779$13429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190480$13250 + cell $and $and$libresoc.v:192784$13434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397964,34 +401973,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190480$13250_Y + connect \Y $and$libresoc.v:192784$13434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190477$13247 + cell $not $not$libresoc.v:192781$13431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190477$13247_Y + connect \Y $not$libresoc.v:192781$13431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190479$13249 + cell $not $not$libresoc.v:192783$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190479$13249_Y + connect \Y $not$libresoc.v:192783$13433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190482$13252 + cell $not $not$libresoc.v:192786$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190482$13252_Y + connect \Y $not$libresoc.v:192786$13436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190476$13246 + cell $or $or$libresoc.v:192780$13430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397999,10 +402008,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190476$13246_Y + connect \Y $or$libresoc.v:192780$13430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190478$13248 + cell $or $or$libresoc.v:192782$13432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398010,10 +402019,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190478$13248_Y + connect \Y $or$libresoc.v:192782$13432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190481$13251 + cell $or $or$libresoc.v:192785$13435 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398021,39 +402030,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190481$13251_Y + connect \Y $or$libresoc.v:192785$13435_Y end - attribute \src "libresoc.v:190440.7-190440.20" - process $proc$libresoc.v:190440$13257 + attribute \src "libresoc.v:192744.7-192744.20" + process $proc$libresoc.v:192744$13441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190462.13-190462.25" - process $proc$libresoc.v:190462$13258 + attribute \src "libresoc.v:192766.13-192766.25" + process $proc$libresoc.v:192766$13442 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190483.3-190484.27" - process $proc$libresoc.v:190483$13253 + attribute \src "libresoc.v:192787.3-192788.27" + process $proc$libresoc.v:192787$13437 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190485.3-190493.6" - process $proc$libresoc.v:190485$13254 + attribute \src "libresoc.v:192789.3-192797.6" + process $proc$libresoc.v:192789$13438 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13255 $1\q_int$next[2:0]$13256 - attribute \src "libresoc.v:190486.5-190486.29" + assign $0\q_int$next[2:0]$13439 $1\q_int$next[2:0]$13440 + attribute \src "libresoc.v:192790.5-192790.29" switch \initial - attribute \src "libresoc.v:190486.9-190486.17" + attribute \src "libresoc.v:192790.9-192790.17" case 1'1 case end @@ -398062,56 +402071,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13256 3'000 + assign $1\q_int$next[2:0]$13440 3'000 case - assign $1\q_int$next[2:0]$13256 \$5 + assign $1\q_int$next[2:0]$13440 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13255 + update \q_int$next $0\q_int$next[2:0]$13439 end - connect \$9 $and$libresoc.v:190475$13245_Y - connect \$11 $or$libresoc.v:190476$13246_Y - connect \$13 $not$libresoc.v:190477$13247_Y - connect \$15 $or$libresoc.v:190478$13248_Y - connect \$1 $not$libresoc.v:190479$13249_Y - connect \$3 $and$libresoc.v:190480$13250_Y - connect \$5 $or$libresoc.v:190481$13251_Y - connect \$7 $not$libresoc.v:190482$13252_Y + connect \$9 $and$libresoc.v:192779$13429_Y + connect \$11 $or$libresoc.v:192780$13430_Y + connect \$13 $not$libresoc.v:192781$13431_Y + connect \$15 $or$libresoc.v:192782$13432_Y + connect \$1 $not$libresoc.v:192783$13433_Y + connect \$3 $and$libresoc.v:192784$13434_Y + connect \$5 $or$libresoc.v:192785$13435_Y + connect \$7 $not$libresoc.v:192786$13436_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190501.1-190559.10" +attribute \src "libresoc.v:192805.1-192863.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:190502.7-190502.20" + attribute \src "libresoc.v:192806.7-192806.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190547.3-190555.6" - wire width 6 $0\q_int$next[5:0]$13269 - attribute \src "libresoc.v:190545.3-190546.27" + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $0\q_int$next[5:0]$13453 + attribute \src "libresoc.v:192849.3-192850.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:190547.3-190555.6" - wire width 6 $1\q_int$next[5:0]$13270 - attribute \src "libresoc.v:190524.13-190524.26" + attribute \src "libresoc.v:192851.3-192859.6" + wire width 6 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192828.13-192828.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:190537.17-190537.96" - wire width 6 $and$libresoc.v:190537$13259_Y - attribute \src "libresoc.v:190542.17-190542.96" - wire width 6 $and$libresoc.v:190542$13264_Y - attribute \src "libresoc.v:190539.18-190539.93" - wire width 6 $not$libresoc.v:190539$13261_Y - attribute \src "libresoc.v:190541.17-190541.92" - wire width 6 $not$libresoc.v:190541$13263_Y - attribute \src "libresoc.v:190544.17-190544.92" - wire width 6 $not$libresoc.v:190544$13266_Y - attribute \src "libresoc.v:190538.18-190538.98" - wire width 6 $or$libresoc.v:190538$13260_Y - attribute \src "libresoc.v:190540.18-190540.99" - wire width 6 $or$libresoc.v:190540$13262_Y - attribute \src "libresoc.v:190543.17-190543.97" - wire width 6 $or$libresoc.v:190543$13265_Y + attribute \src "libresoc.v:192841.17-192841.96" + wire width 6 $and$libresoc.v:192841$13443_Y + attribute \src "libresoc.v:192846.17-192846.96" + wire width 6 $and$libresoc.v:192846$13448_Y + attribute \src "libresoc.v:192843.18-192843.93" + wire width 6 $not$libresoc.v:192843$13445_Y + attribute \src "libresoc.v:192845.17-192845.92" + wire width 6 $not$libresoc.v:192845$13447_Y + attribute \src "libresoc.v:192848.17-192848.92" + wire width 6 $not$libresoc.v:192848$13450_Y + attribute \src "libresoc.v:192842.18-192842.98" + wire width 6 $or$libresoc.v:192842$13444_Y + attribute \src "libresoc.v:192844.18-192844.99" + wire width 6 $or$libresoc.v:192844$13446_Y + attribute \src "libresoc.v:192847.17-192847.97" + wire width 6 $or$libresoc.v:192847$13449_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398128,11 +402137,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190502.7-190502.15" + attribute \src "libresoc.v:192806.7-192806.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -398149,7 +402158,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190537$13259 + cell $and $and$libresoc.v:192841$13443 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398157,10 +402166,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190537$13259_Y + connect \Y $and$libresoc.v:192841$13443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190542$13264 + cell $and $and$libresoc.v:192846$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398168,34 +402177,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190542$13264_Y + connect \Y $and$libresoc.v:192846$13448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190539$13261 + cell $not $not$libresoc.v:192843$13445 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:190539$13261_Y + connect \Y $not$libresoc.v:192843$13445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190541$13263 + cell $not $not$libresoc.v:192845$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190541$13263_Y + connect \Y $not$libresoc.v:192845$13447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190544$13266 + cell $not $not$libresoc.v:192848$13450 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:190544$13266_Y + connect \Y $not$libresoc.v:192848$13450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190538$13260 + cell $or $or$libresoc.v:192842$13444 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398203,10 +402212,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190538$13260_Y + connect \Y $or$libresoc.v:192842$13444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190540$13262 + cell $or $or$libresoc.v:192844$13446 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398214,10 +402223,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190540$13262_Y + connect \Y $or$libresoc.v:192844$13446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190543$13265 + cell $or $or$libresoc.v:192847$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -398225,39 +402234,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190543$13265_Y + connect \Y $or$libresoc.v:192847$13449_Y end - attribute \src "libresoc.v:190502.7-190502.20" - process $proc$libresoc.v:190502$13271 + attribute \src "libresoc.v:192806.7-192806.20" + process $proc$libresoc.v:192806$13455 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190524.13-190524.26" - process $proc$libresoc.v:190524$13272 + attribute \src "libresoc.v:192828.13-192828.26" + process $proc$libresoc.v:192828$13456 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:190545.3-190546.27" - process $proc$libresoc.v:190545$13267 + attribute \src "libresoc.v:192849.3-192850.27" + process $proc$libresoc.v:192849$13451 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:190547.3-190555.6" - process $proc$libresoc.v:190547$13268 + attribute \src "libresoc.v:192851.3-192859.6" + process $proc$libresoc.v:192851$13452 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13269 $1\q_int$next[5:0]$13270 - attribute \src "libresoc.v:190548.5-190548.29" + assign $0\q_int$next[5:0]$13453 $1\q_int$next[5:0]$13454 + attribute \src "libresoc.v:192852.5-192852.29" switch \initial - attribute \src "libresoc.v:190548.9-190548.17" + attribute \src "libresoc.v:192852.9-192852.17" case 1'1 case end @@ -398266,56 +402275,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13270 6'000000 + assign $1\q_int$next[5:0]$13454 6'000000 case - assign $1\q_int$next[5:0]$13270 \$5 + assign $1\q_int$next[5:0]$13454 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13269 + update \q_int$next $0\q_int$next[5:0]$13453 end - connect \$9 $and$libresoc.v:190537$13259_Y - connect \$11 $or$libresoc.v:190538$13260_Y - connect \$13 $not$libresoc.v:190539$13261_Y - connect \$15 $or$libresoc.v:190540$13262_Y - connect \$1 $not$libresoc.v:190541$13263_Y - connect \$3 $and$libresoc.v:190542$13264_Y - connect \$5 $or$libresoc.v:190543$13265_Y - connect \$7 $not$libresoc.v:190544$13266_Y + connect \$9 $and$libresoc.v:192841$13443_Y + connect \$11 $or$libresoc.v:192842$13444_Y + connect \$13 $not$libresoc.v:192843$13445_Y + connect \$15 $or$libresoc.v:192844$13446_Y + connect \$1 $not$libresoc.v:192845$13447_Y + connect \$3 $and$libresoc.v:192846$13448_Y + connect \$5 $or$libresoc.v:192847$13449_Y + connect \$7 $not$libresoc.v:192848$13450_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190563.1-190621.10" +attribute \src "libresoc.v:192867.1-192925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:190564.7-190564.20" + attribute \src "libresoc.v:192868.7-192868.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190609.3-190617.6" - wire width 3 $0\q_int$next[2:0]$13283 - attribute \src "libresoc.v:190607.3-190608.27" + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $0\q_int$next[2:0]$13467 + attribute \src "libresoc.v:192911.3-192912.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:190609.3-190617.6" - wire width 3 $1\q_int$next[2:0]$13284 - attribute \src "libresoc.v:190586.13-190586.25" + attribute \src "libresoc.v:192913.3-192921.6" + wire width 3 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192890.13-192890.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:190599.17-190599.96" - wire width 3 $and$libresoc.v:190599$13273_Y - attribute \src "libresoc.v:190604.17-190604.96" - wire width 3 $and$libresoc.v:190604$13278_Y - attribute \src "libresoc.v:190601.18-190601.93" - wire width 3 $not$libresoc.v:190601$13275_Y - attribute \src "libresoc.v:190603.17-190603.92" - wire width 3 $not$libresoc.v:190603$13277_Y - attribute \src "libresoc.v:190606.17-190606.92" - wire width 3 $not$libresoc.v:190606$13280_Y - attribute \src "libresoc.v:190600.18-190600.98" - wire width 3 $or$libresoc.v:190600$13274_Y - attribute \src "libresoc.v:190602.18-190602.99" - wire width 3 $or$libresoc.v:190602$13276_Y - attribute \src "libresoc.v:190605.17-190605.97" - wire width 3 $or$libresoc.v:190605$13279_Y + attribute \src "libresoc.v:192903.17-192903.96" + wire width 3 $and$libresoc.v:192903$13457_Y + attribute \src "libresoc.v:192908.17-192908.96" + wire width 3 $and$libresoc.v:192908$13462_Y + attribute \src "libresoc.v:192905.18-192905.93" + wire width 3 $not$libresoc.v:192905$13459_Y + attribute \src "libresoc.v:192907.17-192907.92" + wire width 3 $not$libresoc.v:192907$13461_Y + attribute \src "libresoc.v:192910.17-192910.92" + wire width 3 $not$libresoc.v:192910$13464_Y + attribute \src "libresoc.v:192904.18-192904.98" + wire width 3 $or$libresoc.v:192904$13458_Y + attribute \src "libresoc.v:192906.18-192906.99" + wire width 3 $or$libresoc.v:192906$13460_Y + attribute \src "libresoc.v:192909.17-192909.97" + wire width 3 $or$libresoc.v:192909$13463_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398332,11 +402341,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190564.7-190564.15" + attribute \src "libresoc.v:192868.7-192868.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -398353,7 +402362,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190599$13273 + cell $and $and$libresoc.v:192903$13457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398361,10 +402370,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190599$13273_Y + connect \Y $and$libresoc.v:192903$13457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190604$13278 + cell $and $and$libresoc.v:192908$13462 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398372,34 +402381,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190604$13278_Y + connect \Y $and$libresoc.v:192908$13462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190601$13275 + cell $not $not$libresoc.v:192905$13459 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:190601$13275_Y + connect \Y $not$libresoc.v:192905$13459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190603$13277 + cell $not $not$libresoc.v:192907$13461 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190603$13277_Y + connect \Y $not$libresoc.v:192907$13461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190606$13280 + cell $not $not$libresoc.v:192910$13464 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:190606$13280_Y + connect \Y $not$libresoc.v:192910$13464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190600$13274 + cell $or $or$libresoc.v:192904$13458 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398407,10 +402416,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:190600$13274_Y + connect \Y $or$libresoc.v:192904$13458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190602$13276 + cell $or $or$libresoc.v:192906$13460 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398418,10 +402427,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:190602$13276_Y + connect \Y $or$libresoc.v:192906$13460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190605$13279 + cell $or $or$libresoc.v:192909$13463 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -398429,39 +402438,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:190605$13279_Y + connect \Y $or$libresoc.v:192909$13463_Y end - attribute \src "libresoc.v:190564.7-190564.20" - process $proc$libresoc.v:190564$13285 + attribute \src "libresoc.v:192868.7-192868.20" + process $proc$libresoc.v:192868$13469 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190586.13-190586.25" - process $proc$libresoc.v:190586$13286 + attribute \src "libresoc.v:192890.13-192890.25" + process $proc$libresoc.v:192890$13470 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:190607.3-190608.27" - process $proc$libresoc.v:190607$13281 + attribute \src "libresoc.v:192911.3-192912.27" + process $proc$libresoc.v:192911$13465 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:190609.3-190617.6" - process $proc$libresoc.v:190609$13282 + attribute \src "libresoc.v:192913.3-192921.6" + process $proc$libresoc.v:192913$13466 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13283 $1\q_int$next[2:0]$13284 - attribute \src "libresoc.v:190610.5-190610.29" + assign $0\q_int$next[2:0]$13467 $1\q_int$next[2:0]$13468 + attribute \src "libresoc.v:192914.5-192914.29" switch \initial - attribute \src "libresoc.v:190610.9-190610.17" + attribute \src "libresoc.v:192914.9-192914.17" case 1'1 case end @@ -398470,56 +402479,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13284 3'000 + assign $1\q_int$next[2:0]$13468 3'000 case - assign $1\q_int$next[2:0]$13284 \$5 + assign $1\q_int$next[2:0]$13468 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13283 + update \q_int$next $0\q_int$next[2:0]$13467 end - connect \$9 $and$libresoc.v:190599$13273_Y - connect \$11 $or$libresoc.v:190600$13274_Y - connect \$13 $not$libresoc.v:190601$13275_Y - connect \$15 $or$libresoc.v:190602$13276_Y - connect \$1 $not$libresoc.v:190603$13277_Y - connect \$3 $and$libresoc.v:190604$13278_Y - connect \$5 $or$libresoc.v:190605$13279_Y - connect \$7 $not$libresoc.v:190606$13280_Y + connect \$9 $and$libresoc.v:192903$13457_Y + connect \$11 $or$libresoc.v:192904$13458_Y + connect \$13 $not$libresoc.v:192905$13459_Y + connect \$15 $or$libresoc.v:192906$13460_Y + connect \$1 $not$libresoc.v:192907$13461_Y + connect \$3 $and$libresoc.v:192908$13462_Y + connect \$5 $or$libresoc.v:192909$13463_Y + connect \$7 $not$libresoc.v:192910$13464_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:190625.1-190683.10" +attribute \src "libresoc.v:192929.1-192987.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:190626.7-190626.20" + attribute \src "libresoc.v:192930.7-192930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190671.3-190679.6" - wire $0\q_int$next[0:0]$13297 - attribute \src "libresoc.v:190669.3-190670.27" + attribute \src "libresoc.v:192975.3-192983.6" + wire $0\q_int$next[0:0]$13481 + attribute \src "libresoc.v:192973.3-192974.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190671.3-190679.6" - wire $1\q_int$next[0:0]$13298 - attribute \src "libresoc.v:190648.7-190648.19" + attribute \src "libresoc.v:192975.3-192983.6" + wire $1\q_int$next[0:0]$13482 + attribute \src "libresoc.v:192952.7-192952.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190661.17-190661.96" - wire $and$libresoc.v:190661$13287_Y - attribute \src "libresoc.v:190666.17-190666.96" - wire $and$libresoc.v:190666$13292_Y - attribute \src "libresoc.v:190663.18-190663.99" - wire $not$libresoc.v:190663$13289_Y - attribute \src "libresoc.v:190665.17-190665.98" - wire $not$libresoc.v:190665$13291_Y - attribute \src "libresoc.v:190668.17-190668.98" - wire $not$libresoc.v:190668$13294_Y - attribute \src "libresoc.v:190662.18-190662.104" - wire $or$libresoc.v:190662$13288_Y - attribute \src "libresoc.v:190664.18-190664.105" - wire $or$libresoc.v:190664$13290_Y - attribute \src "libresoc.v:190667.17-190667.103" - wire $or$libresoc.v:190667$13293_Y + attribute \src "libresoc.v:192965.17-192965.96" + wire $and$libresoc.v:192965$13471_Y + attribute \src "libresoc.v:192970.17-192970.96" + wire $and$libresoc.v:192970$13476_Y + attribute \src "libresoc.v:192967.18-192967.99" + wire $not$libresoc.v:192967$13473_Y + attribute \src "libresoc.v:192969.17-192969.98" + wire $not$libresoc.v:192969$13475_Y + attribute \src "libresoc.v:192972.17-192972.98" + wire $not$libresoc.v:192972$13478_Y + attribute \src "libresoc.v:192966.18-192966.104" + wire $or$libresoc.v:192966$13472_Y + attribute \src "libresoc.v:192968.18-192968.105" + wire $or$libresoc.v:192968$13474_Y + attribute \src "libresoc.v:192971.17-192971.103" + wire $or$libresoc.v:192971$13477_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398536,11 +402545,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190626.7-190626.15" + attribute \src "libresoc.v:192930.7-192930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398557,7 +402566,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190661$13287 + cell $and $and$libresoc.v:192965$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398565,10 +402574,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190661$13287_Y + connect \Y $and$libresoc.v:192965$13471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190666$13292 + cell $and $and$libresoc.v:192970$13476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398576,34 +402585,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190666$13292_Y + connect \Y $and$libresoc.v:192970$13476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190663$13289 + cell $not $not$libresoc.v:192967$13473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:190663$13289_Y + connect \Y $not$libresoc.v:192967$13473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190665$13291 + cell $not $not$libresoc.v:192969$13475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:190665$13291_Y + connect \Y $not$libresoc.v:192969$13475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190668$13294 + cell $not $not$libresoc.v:192972$13478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:190668$13294_Y + connect \Y $not$libresoc.v:192972$13478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190662$13288 + cell $or $or$libresoc.v:192966$13472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398611,10 +402620,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:190662$13288_Y + connect \Y $or$libresoc.v:192966$13472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190664$13290 + cell $or $or$libresoc.v:192968$13474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398622,10 +402631,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:190664$13290_Y + connect \Y $or$libresoc.v:192968$13474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190667$13293 + cell $or $or$libresoc.v:192971$13477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398633,39 +402642,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:190667$13293_Y + connect \Y $or$libresoc.v:192971$13477_Y end - attribute \src "libresoc.v:190626.7-190626.20" - process $proc$libresoc.v:190626$13299 + attribute \src "libresoc.v:192930.7-192930.20" + process $proc$libresoc.v:192930$13483 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190648.7-190648.19" - process $proc$libresoc.v:190648$13300 + attribute \src "libresoc.v:192952.7-192952.19" + process $proc$libresoc.v:192952$13484 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190669.3-190670.27" - process $proc$libresoc.v:190669$13295 + attribute \src "libresoc.v:192973.3-192974.27" + process $proc$libresoc.v:192973$13479 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190671.3-190679.6" - process $proc$libresoc.v:190671$13296 + attribute \src "libresoc.v:192975.3-192983.6" + process $proc$libresoc.v:192975$13480 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13297 $1\q_int$next[0:0]$13298 - attribute \src "libresoc.v:190672.5-190672.29" + assign $0\q_int$next[0:0]$13481 $1\q_int$next[0:0]$13482 + attribute \src "libresoc.v:192976.5-192976.29" switch \initial - attribute \src "libresoc.v:190672.9-190672.17" + attribute \src "libresoc.v:192976.9-192976.17" case 1'1 case end @@ -398674,56 +402683,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13298 1'0 + assign $1\q_int$next[0:0]$13482 1'0 case - assign $1\q_int$next[0:0]$13298 \$5 + assign $1\q_int$next[0:0]$13482 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13297 + update \q_int$next $0\q_int$next[0:0]$13481 end - connect \$9 $and$libresoc.v:190661$13287_Y - connect \$11 $or$libresoc.v:190662$13288_Y - connect \$13 $not$libresoc.v:190663$13289_Y - connect \$15 $or$libresoc.v:190664$13290_Y - connect \$1 $not$libresoc.v:190665$13291_Y - connect \$3 $and$libresoc.v:190666$13292_Y - connect \$5 $or$libresoc.v:190667$13293_Y - connect \$7 $not$libresoc.v:190668$13294_Y + connect \$9 $and$libresoc.v:192965$13471_Y + connect \$11 $or$libresoc.v:192966$13472_Y + connect \$13 $not$libresoc.v:192967$13473_Y + connect \$15 $or$libresoc.v:192968$13474_Y + connect \$1 $not$libresoc.v:192969$13475_Y + connect \$3 $and$libresoc.v:192970$13476_Y + connect \$5 $or$libresoc.v:192971$13477_Y + connect \$7 $not$libresoc.v:192972$13478_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:190687.1-190745.10" +attribute \src "libresoc.v:192991.1-193049.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:190688.7-190688.20" + attribute \src "libresoc.v:192992.7-192992.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190733.3-190741.6" - wire $0\q_int$next[0:0]$13311 - attribute \src "libresoc.v:190731.3-190732.27" + attribute \src "libresoc.v:193037.3-193045.6" + wire $0\q_int$next[0:0]$13495 + attribute \src "libresoc.v:193035.3-193036.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190733.3-190741.6" - wire $1\q_int$next[0:0]$13312 - attribute \src "libresoc.v:190710.7-190710.19" + attribute \src "libresoc.v:193037.3-193045.6" + wire $1\q_int$next[0:0]$13496 + attribute \src "libresoc.v:193014.7-193014.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190723.17-190723.96" - wire $and$libresoc.v:190723$13301_Y - attribute \src "libresoc.v:190728.17-190728.96" - wire $and$libresoc.v:190728$13306_Y - attribute \src "libresoc.v:190725.18-190725.97" - wire $not$libresoc.v:190725$13303_Y - attribute \src "libresoc.v:190727.17-190727.96" - wire $not$libresoc.v:190727$13305_Y - attribute \src "libresoc.v:190730.17-190730.96" - wire $not$libresoc.v:190730$13308_Y - attribute \src "libresoc.v:190724.18-190724.102" - wire $or$libresoc.v:190724$13302_Y - attribute \src "libresoc.v:190726.18-190726.103" - wire $or$libresoc.v:190726$13304_Y - attribute \src "libresoc.v:190729.17-190729.101" - wire $or$libresoc.v:190729$13307_Y + attribute \src "libresoc.v:193027.17-193027.96" + wire $and$libresoc.v:193027$13485_Y + attribute \src "libresoc.v:193032.17-193032.96" + wire $and$libresoc.v:193032$13490_Y + attribute \src "libresoc.v:193029.18-193029.97" + wire $not$libresoc.v:193029$13487_Y + attribute \src "libresoc.v:193031.17-193031.96" + wire $not$libresoc.v:193031$13489_Y + attribute \src "libresoc.v:193034.17-193034.96" + wire $not$libresoc.v:193034$13492_Y + attribute \src "libresoc.v:193028.18-193028.102" + wire $or$libresoc.v:193028$13486_Y + attribute \src "libresoc.v:193030.18-193030.103" + wire $or$libresoc.v:193030$13488_Y + attribute \src "libresoc.v:193033.17-193033.101" + wire $or$libresoc.v:193033$13491_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398740,11 +402749,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:190688.7-190688.15" + attribute \src "libresoc.v:192992.7-192992.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398761,7 +402770,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190723$13301 + cell $and $and$libresoc.v:193027$13485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398769,10 +402778,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190723$13301_Y + connect \Y $and$libresoc.v:193027$13485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190728$13306 + cell $and $and$libresoc.v:193032$13490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398780,34 +402789,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190728$13306_Y + connect \Y $and$libresoc.v:193032$13490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190725$13303 + cell $not $not$libresoc.v:193029$13487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:190725$13303_Y + connect \Y $not$libresoc.v:193029$13487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190727$13305 + cell $not $not$libresoc.v:193031$13489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:190727$13305_Y + connect \Y $not$libresoc.v:193031$13489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190730$13308 + cell $not $not$libresoc.v:193034$13492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:190730$13308_Y + connect \Y $not$libresoc.v:193034$13492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190724$13302 + cell $or $or$libresoc.v:193028$13486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398815,10 +402824,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:190724$13302_Y + connect \Y $or$libresoc.v:193028$13486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190726$13304 + cell $or $or$libresoc.v:193030$13488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398826,10 +402835,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:190726$13304_Y + connect \Y $or$libresoc.v:193030$13488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190729$13307 + cell $or $or$libresoc.v:193033$13491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398837,39 +402846,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:190729$13307_Y + connect \Y $or$libresoc.v:193033$13491_Y end - attribute \src "libresoc.v:190688.7-190688.20" - process $proc$libresoc.v:190688$13313 + attribute \src "libresoc.v:192992.7-192992.20" + process $proc$libresoc.v:192992$13497 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190710.7-190710.19" - process $proc$libresoc.v:190710$13314 + attribute \src "libresoc.v:193014.7-193014.19" + process $proc$libresoc.v:193014$13498 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190731.3-190732.27" - process $proc$libresoc.v:190731$13309 + attribute \src "libresoc.v:193035.3-193036.27" + process $proc$libresoc.v:193035$13493 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190733.3-190741.6" - process $proc$libresoc.v:190733$13310 + attribute \src "libresoc.v:193037.3-193045.6" + process $proc$libresoc.v:193037$13494 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13311 $1\q_int$next[0:0]$13312 - attribute \src "libresoc.v:190734.5-190734.29" + assign $0\q_int$next[0:0]$13495 $1\q_int$next[0:0]$13496 + attribute \src "libresoc.v:193038.5-193038.29" switch \initial - attribute \src "libresoc.v:190734.9-190734.17" + attribute \src "libresoc.v:193038.9-193038.17" case 1'1 case end @@ -398878,86 +402887,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13312 1'0 + assign $1\q_int$next[0:0]$13496 1'0 case - assign $1\q_int$next[0:0]$13312 \$5 + assign $1\q_int$next[0:0]$13496 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13311 + update \q_int$next $0\q_int$next[0:0]$13495 end - connect \$9 $and$libresoc.v:190723$13301_Y - connect \$11 $or$libresoc.v:190724$13302_Y - connect \$13 $not$libresoc.v:190725$13303_Y - connect \$15 $or$libresoc.v:190726$13304_Y - connect \$1 $not$libresoc.v:190727$13305_Y - connect \$3 $and$libresoc.v:190728$13306_Y - connect \$5 $or$libresoc.v:190729$13307_Y - connect \$7 $not$libresoc.v:190730$13308_Y + connect \$9 $and$libresoc.v:193027$13485_Y + connect \$11 $or$libresoc.v:193028$13486_Y + connect \$13 $not$libresoc.v:193029$13487_Y + connect \$15 $or$libresoc.v:193030$13488_Y + connect \$1 $not$libresoc.v:193031$13489_Y + connect \$3 $and$libresoc.v:193032$13490_Y + connect \$5 $or$libresoc.v:193033$13491_Y + connect \$7 $not$libresoc.v:193034$13492_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:190749.1-191045.10" +attribute \src "libresoc.v:193053.1-193349.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:190997.3-191006.6" + attribute \src "libresoc.v:193301.3-193310.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:190750.7-190750.20" + attribute \src "libresoc.v:193054.7-193054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191016.3-191025.6" + attribute \src "libresoc.v:193320.3-193329.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:191007.3-191015.6" - wire width 3 $0\ren_delay$12$next[2:0]$13338 - attribute \src "libresoc.v:190911.3-190912.43" - wire width 3 $0\ren_delay$12[2:0]$13327 - attribute \src "libresoc.v:190878.13-190878.34" - wire width 3 $0\ren_delay$12[2:0]$13344 - attribute \src "libresoc.v:190969.3-190977.6" - wire width 3 $0\ren_delay$19$next[2:0]$13330 - attribute \src "libresoc.v:190909.3-190910.43" - wire width 3 $0\ren_delay$19[2:0]$13325 - attribute \src "libresoc.v:190882.13-190882.34" - wire width 3 $0\ren_delay$19[2:0]$13346 - attribute \src "libresoc.v:190988.3-190996.6" - wire width 3 $0\ren_delay$next[2:0]$13334 - attribute \src "libresoc.v:190913.3-190914.35" + attribute \src "libresoc.v:193311.3-193319.6" + wire width 3 $0\ren_delay$12$next[2:0]$13522 + attribute \src "libresoc.v:193215.3-193216.43" + wire width 3 $0\ren_delay$12[2:0]$13511 + attribute \src "libresoc.v:193182.13-193182.34" + wire width 3 $0\ren_delay$12[2:0]$13528 + attribute \src "libresoc.v:193273.3-193281.6" + wire width 3 $0\ren_delay$19$next[2:0]$13514 + attribute \src "libresoc.v:193213.3-193214.43" + wire width 3 $0\ren_delay$19[2:0]$13509 + attribute \src "libresoc.v:193186.13-193186.34" + wire width 3 $0\ren_delay$19[2:0]$13530 + attribute \src "libresoc.v:193292.3-193300.6" + wire width 3 $0\ren_delay$next[2:0]$13518 + attribute \src "libresoc.v:193217.3-193218.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:190978.3-190987.6" + attribute \src "libresoc.v:193282.3-193291.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:190997.3-191006.6" + attribute \src "libresoc.v:193301.3-193310.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:191016.3-191025.6" + attribute \src "libresoc.v:193320.3-193329.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:191007.3-191015.6" - wire width 3 $1\ren_delay$12$next[2:0]$13339 - attribute \src "libresoc.v:190969.3-190977.6" - wire width 3 $1\ren_delay$19$next[2:0]$13331 - attribute \src "libresoc.v:190988.3-190996.6" - wire width 3 $1\ren_delay$next[2:0]$13335 - attribute \src "libresoc.v:190876.13-190876.29" + attribute \src "libresoc.v:193311.3-193319.6" + wire width 3 $1\ren_delay$12$next[2:0]$13523 + attribute \src "libresoc.v:193273.3-193281.6" + wire width 3 $1\ren_delay$19$next[2:0]$13515 + attribute \src "libresoc.v:193292.3-193300.6" + wire width 3 $1\ren_delay$next[2:0]$13519 + attribute \src "libresoc.v:193180.13-193180.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:190978.3-190987.6" + attribute \src "libresoc.v:193282.3-193291.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:190900.18-190900.109" - wire width 64 $or$libresoc.v:190900$13315_Y - attribute \src "libresoc.v:190902.18-190902.124" - wire width 64 $or$libresoc.v:190902$13317_Y - attribute \src "libresoc.v:190903.18-190903.110" - wire width 64 $or$libresoc.v:190903$13318_Y - attribute \src "libresoc.v:190905.18-190905.122" - wire width 64 $or$libresoc.v:190905$13320_Y - attribute \src "libresoc.v:190906.18-190906.109" - wire width 64 $or$libresoc.v:190906$13321_Y - attribute \src "libresoc.v:190908.17-190908.123" - wire width 64 $or$libresoc.v:190908$13323_Y - attribute \src "libresoc.v:190901.18-190901.100" - wire $reduce_or$libresoc.v:190901$13316_Y - attribute \src "libresoc.v:190904.18-190904.100" - wire $reduce_or$libresoc.v:190904$13319_Y - attribute \src "libresoc.v:190907.17-190907.95" - wire $reduce_or$libresoc.v:190907$13322_Y + attribute \src "libresoc.v:193204.18-193204.109" + wire width 64 $or$libresoc.v:193204$13499_Y + attribute \src "libresoc.v:193206.18-193206.124" + wire width 64 $or$libresoc.v:193206$13501_Y + attribute \src "libresoc.v:193207.18-193207.110" + wire width 64 $or$libresoc.v:193207$13502_Y + attribute \src "libresoc.v:193209.18-193209.122" + wire width 64 $or$libresoc.v:193209$13504_Y + attribute \src "libresoc.v:193210.18-193210.109" + wire width 64 $or$libresoc.v:193210$13505_Y + attribute \src "libresoc.v:193212.17-193212.123" + wire width 64 $or$libresoc.v:193212$13507_Y + attribute \src "libresoc.v:193205.18-193205.100" + wire $reduce_or$libresoc.v:193205$13500_Y + attribute \src "libresoc.v:193208.18-193208.100" + wire $reduce_or$libresoc.v:193208$13503_Y + attribute \src "libresoc.v:193211.17-193211.95" + wire $reduce_or$libresoc.v:193211$13506_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -398980,9 +402989,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -398992,7 +403001,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:190750.7-190750.15" + attribute \src "libresoc.v:193054.7-193054.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -399107,7 +403116,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190900$13315 + cell $or $or$libresoc.v:193204$13499 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399115,10 +403124,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:190900$13315_Y + connect \Y $or$libresoc.v:193204$13499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190902$13317 + cell $or $or$libresoc.v:193206$13501 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399126,10 +403135,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:190902$13317_Y + connect \Y $or$libresoc.v:193206$13501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190903$13318 + cell $or $or$libresoc.v:193207$13502 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399137,10 +403146,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:190903$13318_Y + connect \Y $or$libresoc.v:193207$13502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190905$13320 + cell $or $or$libresoc.v:193209$13504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399148,10 +403157,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:190905$13320_Y + connect \Y $or$libresoc.v:193209$13504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:190906$13321 + cell $or $or$libresoc.v:193210$13505 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399159,10 +403168,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:190906$13321_Y + connect \Y $or$libresoc.v:193210$13505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:190908$13323 + cell $or $or$libresoc.v:193212$13507 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -399170,34 +403179,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:190908$13323_Y + connect \Y $or$libresoc.v:193212$13507_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190901$13316 + cell $reduce_or $reduce_or$libresoc.v:193205$13500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:190901$13316_Y + connect \Y $reduce_or$libresoc.v:193205$13500_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190904$13319 + cell $reduce_or $reduce_or$libresoc.v:193208$13503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:190904$13319_Y + connect \Y $reduce_or$libresoc.v:193208$13503_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:190907$13322 + cell $reduce_or $reduce_or$libresoc.v:193211$13506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:190907$13322_Y + connect \Y $reduce_or$libresoc.v:193211$13506_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:190915.15-190932.4" + attribute \src "libresoc.v:193219.15-193236.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -399217,7 +403226,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:190933.15-190950.4" + attribute \src "libresoc.v:193237.15-193254.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -399237,7 +403246,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:190951.15-190968.4" + attribute \src "libresoc.v:193255.15-193272.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -399256,67 +403265,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:190750.7-190750.20" - process $proc$libresoc.v:190750$13341 + attribute \src "libresoc.v:193054.7-193054.20" + process $proc$libresoc.v:193054$13525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190876.13-190876.29" - process $proc$libresoc.v:190876$13342 + attribute \src "libresoc.v:193180.13-193180.29" + process $proc$libresoc.v:193180$13526 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:190878.13-190878.34" - process $proc$libresoc.v:190878$13343 + attribute \src "libresoc.v:193182.13-193182.34" + process $proc$libresoc.v:193182$13527 assign { } { } - assign $0\ren_delay$12[2:0]$13344 3'000 + assign $0\ren_delay$12[2:0]$13528 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13344 + update \ren_delay$12 $0\ren_delay$12[2:0]$13528 end - attribute \src "libresoc.v:190882.13-190882.34" - process $proc$libresoc.v:190882$13345 + attribute \src "libresoc.v:193186.13-193186.34" + process $proc$libresoc.v:193186$13529 assign { } { } - assign $0\ren_delay$19[2:0]$13346 3'000 + assign $0\ren_delay$19[2:0]$13530 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13346 + update \ren_delay$19 $0\ren_delay$19[2:0]$13530 end - attribute \src "libresoc.v:190909.3-190910.43" - process $proc$libresoc.v:190909$13324 + attribute \src "libresoc.v:193213.3-193214.43" + process $proc$libresoc.v:193213$13508 assign { } { } - assign $0\ren_delay$19[2:0]$13325 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13509 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13325 + update \ren_delay$19 $0\ren_delay$19[2:0]$13509 end - attribute \src "libresoc.v:190911.3-190912.43" - process $proc$libresoc.v:190911$13326 + attribute \src "libresoc.v:193215.3-193216.43" + process $proc$libresoc.v:193215$13510 assign { } { } - assign $0\ren_delay$12[2:0]$13327 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13511 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13327 + update \ren_delay$12 $0\ren_delay$12[2:0]$13511 end - attribute \src "libresoc.v:190913.3-190914.35" - process $proc$libresoc.v:190913$13328 + attribute \src "libresoc.v:193217.3-193218.35" + process $proc$libresoc.v:193217$13512 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:190969.3-190977.6" - process $proc$libresoc.v:190969$13329 + attribute \src "libresoc.v:193273.3-193281.6" + process $proc$libresoc.v:193273$13513 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13330 $1\ren_delay$19$next[2:0]$13331 - attribute \src "libresoc.v:190970.5-190970.29" + assign $0\ren_delay$19$next[2:0]$13514 $1\ren_delay$19$next[2:0]$13515 + attribute \src "libresoc.v:193274.5-193274.29" switch \initial - attribute \src "libresoc.v:190970.9-190970.17" + attribute \src "libresoc.v:193274.9-193274.17" case 1'1 case end @@ -399325,21 +403334,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13331 3'000 + assign $1\ren_delay$19$next[2:0]$13515 3'000 case - assign $1\ren_delay$19$next[2:0]$13331 \sv__ren + assign $1\ren_delay$19$next[2:0]$13515 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13330 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13514 end - attribute \src "libresoc.v:190978.3-190987.6" - process $proc$libresoc.v:190978$13332 + attribute \src "libresoc.v:193282.3-193291.6" + process $proc$libresoc.v:193282$13516 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:190979.5-190979.29" + attribute \src "libresoc.v:193283.5-193283.29" switch \initial - attribute \src "libresoc.v:190979.9-190979.17" + attribute \src "libresoc.v:193283.9-193283.17" case 1'1 case end @@ -399355,14 +403364,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:190988.3-190996.6" - process $proc$libresoc.v:190988$13333 + attribute \src "libresoc.v:193292.3-193300.6" + process $proc$libresoc.v:193292$13517 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13334 $1\ren_delay$next[2:0]$13335 - attribute \src "libresoc.v:190989.5-190989.29" + assign $0\ren_delay$next[2:0]$13518 $1\ren_delay$next[2:0]$13519 + attribute \src "libresoc.v:193293.5-193293.29" switch \initial - attribute \src "libresoc.v:190989.9-190989.17" + attribute \src "libresoc.v:193293.9-193293.17" case 1'1 case end @@ -399371,21 +403380,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13335 3'000 + assign $1\ren_delay$next[2:0]$13519 3'000 case - assign $1\ren_delay$next[2:0]$13335 \cia__ren + assign $1\ren_delay$next[2:0]$13519 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13334 + update \ren_delay$next $0\ren_delay$next[2:0]$13518 end - attribute \src "libresoc.v:190997.3-191006.6" - process $proc$libresoc.v:190997$13336 + attribute \src "libresoc.v:193301.3-193310.6" + process $proc$libresoc.v:193301$13520 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:190998.5-190998.29" + attribute \src "libresoc.v:193302.5-193302.29" switch \initial - attribute \src "libresoc.v:190998.9-190998.17" + attribute \src "libresoc.v:193302.9-193302.17" case 1'1 case end @@ -399401,14 +403410,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:191007.3-191015.6" - process $proc$libresoc.v:191007$13337 + attribute \src "libresoc.v:193311.3-193319.6" + process $proc$libresoc.v:193311$13521 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13338 $1\ren_delay$12$next[2:0]$13339 - attribute \src "libresoc.v:191008.5-191008.29" + assign $0\ren_delay$12$next[2:0]$13522 $1\ren_delay$12$next[2:0]$13523 + attribute \src "libresoc.v:193312.5-193312.29" switch \initial - attribute \src "libresoc.v:191008.9-191008.17" + attribute \src "libresoc.v:193312.9-193312.17" case 1'1 case end @@ -399417,21 +403426,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13339 3'000 + assign $1\ren_delay$12$next[2:0]$13523 3'000 case - assign $1\ren_delay$12$next[2:0]$13339 \msr__ren + assign $1\ren_delay$12$next[2:0]$13523 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13338 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13522 end - attribute \src "libresoc.v:191016.3-191025.6" - process $proc$libresoc.v:191016$13340 + attribute \src "libresoc.v:193320.3-193329.6" + process $proc$libresoc.v:193320$13524 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:191017.5-191017.29" + attribute \src "libresoc.v:193321.5-193321.29" switch \initial - attribute \src "libresoc.v:191017.9-191017.17" + attribute \src "libresoc.v:193321.9-193321.17" case 1'1 case end @@ -399447,15 +403456,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:190900$13315_Y - connect \$13 $reduce_or$libresoc.v:190901$13316_Y - connect \$15 $or$libresoc.v:190902$13317_Y - connect \$17 $or$libresoc.v:190903$13318_Y - connect \$20 $reduce_or$libresoc.v:190904$13319_Y - connect \$22 $or$libresoc.v:190905$13320_Y - connect \$24 $or$libresoc.v:190906$13321_Y - connect \$6 $reduce_or$libresoc.v:190907$13322_Y - connect \$8 $or$libresoc.v:190908$13323_Y + connect \$10 $or$libresoc.v:193204$13499_Y + connect \$13 $reduce_or$libresoc.v:193205$13500_Y + connect \$15 $or$libresoc.v:193206$13501_Y + connect \$17 $or$libresoc.v:193207$13502_Y + connect \$20 $reduce_or$libresoc.v:193208$13503_Y + connect \$22 $or$libresoc.v:193209$13504_Y + connect \$24 $or$libresoc.v:193210$13505_Y + connect \$6 $reduce_or$libresoc.v:193211$13506_Y + connect \$8 $or$libresoc.v:193212$13507_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -399476,37 +403485,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:191049.1-191107.10" +attribute \src "libresoc.v:193353.1-193411.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:191050.7-191050.20" + attribute \src "libresoc.v:193354.7-193354.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191095.3-191103.6" - wire $0\q_int$next[0:0]$13357 - attribute \src "libresoc.v:191093.3-191094.27" + attribute \src "libresoc.v:193399.3-193407.6" + wire $0\q_int$next[0:0]$13541 + attribute \src "libresoc.v:193397.3-193398.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:191095.3-191103.6" - wire $1\q_int$next[0:0]$13358 - attribute \src "libresoc.v:191072.7-191072.19" + attribute \src "libresoc.v:193399.3-193407.6" + wire $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193376.7-193376.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:191085.17-191085.96" - wire $and$libresoc.v:191085$13347_Y - attribute \src "libresoc.v:191090.17-191090.96" - wire $and$libresoc.v:191090$13352_Y - attribute \src "libresoc.v:191087.18-191087.93" - wire $not$libresoc.v:191087$13349_Y - attribute \src "libresoc.v:191089.17-191089.92" - wire $not$libresoc.v:191089$13351_Y - attribute \src "libresoc.v:191092.17-191092.92" - wire $not$libresoc.v:191092$13354_Y - attribute \src "libresoc.v:191086.18-191086.98" - wire $or$libresoc.v:191086$13348_Y - attribute \src "libresoc.v:191088.18-191088.99" - wire $or$libresoc.v:191088$13350_Y - attribute \src "libresoc.v:191091.17-191091.97" - wire $or$libresoc.v:191091$13353_Y + attribute \src "libresoc.v:193389.17-193389.96" + wire $and$libresoc.v:193389$13531_Y + attribute \src "libresoc.v:193394.17-193394.96" + wire $and$libresoc.v:193394$13536_Y + attribute \src "libresoc.v:193391.18-193391.93" + wire $not$libresoc.v:193391$13533_Y + attribute \src "libresoc.v:193393.17-193393.92" + wire $not$libresoc.v:193393$13535_Y + attribute \src "libresoc.v:193396.17-193396.92" + wire $not$libresoc.v:193396$13538_Y + attribute \src "libresoc.v:193390.18-193390.98" + wire $or$libresoc.v:193390$13532_Y + attribute \src "libresoc.v:193392.18-193392.99" + wire $or$libresoc.v:193392$13534_Y + attribute \src "libresoc.v:193395.17-193395.97" + wire $or$libresoc.v:193395$13537_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -399523,11 +403532,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:191050.7-191050.15" + attribute \src "libresoc.v:193354.7-193354.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -399544,7 +403553,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191085$13347 + cell $and $and$libresoc.v:193389$13531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399552,10 +403561,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191085$13347_Y + connect \Y $and$libresoc.v:193389$13531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191090$13352 + cell $and $and$libresoc.v:193394$13536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399563,34 +403572,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191090$13352_Y + connect \Y $and$libresoc.v:193394$13536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191087$13349 + cell $not $not$libresoc.v:193391$13533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:191087$13349_Y + connect \Y $not$libresoc.v:193391$13533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191089$13351 + cell $not $not$libresoc.v:193393$13535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:191089$13351_Y + connect \Y $not$libresoc.v:193393$13535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191092$13354 + cell $not $not$libresoc.v:193396$13538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:191092$13354_Y + connect \Y $not$libresoc.v:193396$13538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191086$13348 + cell $or $or$libresoc.v:193390$13532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399598,10 +403607,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:191086$13348_Y + connect \Y $or$libresoc.v:193390$13532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191088$13350 + cell $or $or$libresoc.v:193392$13534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399609,10 +403618,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:191088$13350_Y + connect \Y $or$libresoc.v:193392$13534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191091$13353 + cell $or $or$libresoc.v:193395$13537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399620,39 +403629,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:191091$13353_Y + connect \Y $or$libresoc.v:193395$13537_Y end - attribute \src "libresoc.v:191050.7-191050.20" - process $proc$libresoc.v:191050$13359 + attribute \src "libresoc.v:193354.7-193354.20" + process $proc$libresoc.v:193354$13543 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191072.7-191072.19" - process $proc$libresoc.v:191072$13360 + attribute \src "libresoc.v:193376.7-193376.19" + process $proc$libresoc.v:193376$13544 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:191093.3-191094.27" - process $proc$libresoc.v:191093$13355 + attribute \src "libresoc.v:193397.3-193398.27" + process $proc$libresoc.v:193397$13539 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:191095.3-191103.6" - process $proc$libresoc.v:191095$13356 + attribute \src "libresoc.v:193399.3-193407.6" + process $proc$libresoc.v:193399$13540 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13357 $1\q_int$next[0:0]$13358 - attribute \src "libresoc.v:191096.5-191096.29" + assign $0\q_int$next[0:0]$13541 $1\q_int$next[0:0]$13542 + attribute \src "libresoc.v:193400.5-193400.29" switch \initial - attribute \src "libresoc.v:191096.9-191096.17" + attribute \src "libresoc.v:193400.9-193400.17" case 1'1 case end @@ -399661,26 +403670,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13358 1'0 + assign $1\q_int$next[0:0]$13542 1'0 case - assign $1\q_int$next[0:0]$13358 \$5 + assign $1\q_int$next[0:0]$13542 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13357 + update \q_int$next $0\q_int$next[0:0]$13541 end - connect \$9 $and$libresoc.v:191085$13347_Y - connect \$11 $or$libresoc.v:191086$13348_Y - connect \$13 $not$libresoc.v:191087$13349_Y - connect \$15 $or$libresoc.v:191088$13350_Y - connect \$1 $not$libresoc.v:191089$13351_Y - connect \$3 $and$libresoc.v:191090$13352_Y - connect \$5 $or$libresoc.v:191091$13353_Y - connect \$7 $not$libresoc.v:191092$13354_Y + connect \$9 $and$libresoc.v:193389$13531_Y + connect \$11 $or$libresoc.v:193390$13532_Y + connect \$13 $not$libresoc.v:193391$13533_Y + connect \$15 $or$libresoc.v:193392$13534_Y + connect \$1 $not$libresoc.v:193393$13535_Y + connect \$3 $and$libresoc.v:193394$13536_Y + connect \$5 $or$libresoc.v:193395$13537_Y + connect \$7 $not$libresoc.v:193396$13538_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:191112.1-192349.10" +attribute \src "libresoc.v:193416.1-194641.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -399694,36 +403703,36 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 404 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 400 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 406 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" + wire width 2 input 402 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 344 \dbus__ack + wire input 340 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 338 \dbus__adr + wire width 45 output 334 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 348 \dbus__bte + wire width 2 input 344 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 347 \dbus__cti + wire width 3 input 343 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 342 \dbus__cyc + wire output 338 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 340 \dbus__dat_r + wire width 64 input 336 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 339 \dbus__dat_w + wire width 64 output 335 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 346 \dbus__err + wire input 342 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 341 \dbus__sel + wire width 8 output 337 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 343 \dbus__stb + wire output 339 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 345 \dbus__we + wire output 341 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 19 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -399929,65 +403938,65 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 120 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 333 \ibus__ack + wire input 329 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 327 \ibus__adr + wire width 45 output 323 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 337 \ibus__bte + wire width 2 input 333 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 336 \ibus__cti + wire width 3 input 332 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 331 \ibus__cyc + wire output 327 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 329 \ibus__dat_r + wire width 64 input 325 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 328 \ibus__dat_w + wire width 64 input 324 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 335 \ibus__err + wire input 331 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 330 \ibus__sel + wire width 8 output 326 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 332 \ibus__stb + wire output 328 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 334 \ibus__we + wire input 330 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 391 \icp_wb__ack + wire output 387 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 385 \icp_wb__adr + wire width 28 input 381 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 389 \icp_wb__cyc + wire input 385 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 387 \icp_wb__dat_r + wire width 32 output 383 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 386 \icp_wb__dat_w + wire width 32 input 382 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 393 \icp_wb__err + wire input 389 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 388 \icp_wb__sel + wire width 4 input 384 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 390 \icp_wb__stb + wire input 386 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 392 \icp_wb__we + wire input 388 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 400 \ics_wb__ack + wire output 396 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 394 \ics_wb__adr + wire width 28 input 390 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 398 \ics_wb__cyc + wire input 394 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 396 \ics_wb__dat_r + wire width 32 output 392 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 395 \ics_wb__dat_w + wire width 32 input 391 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 402 \ics_wb__err + wire input 398 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 397 \ics_wb__sel + wire width 4 input 393 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 399 \ics_wb__stb + wire input 395 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 401 \ics_wb__we + wire input 397 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 403 \int_level_i + wire width 16 input 399 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -400006,7 +404015,7 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:134" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \mspi0_clk__core__o @@ -400057,24 +404066,24 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 409 \pc_i + wire width 64 input 405 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795" - wire output 407 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" + wire output 403 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 408 \pll_lck_o + wire output 404 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:810" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" wire \pllclk_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \pwm_0__core__o @@ -400084,8 +404093,8 @@ module \test_issuer wire input 147 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 405 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 401 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400231,17 +404240,9 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 182 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 274 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 275 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dm_1__pad__i + wire input 273 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dm_1__pad__oe + wire output 274 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 183 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400255,77 +404256,77 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__core__i + wire output 287 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 292 \sdr_dq_10__core__o + wire input 288 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 293 \sdr_dq_10__core__oe + wire input 289 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_10__pad__i + wire input 290 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_10__pad__o + wire output 291 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_10__pad__oe + wire output 292 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__core__i + wire output 293 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 298 \sdr_dq_11__core__o + wire input 294 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 299 \sdr_dq_11__core__oe + wire input 295 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_11__pad__i + wire input 296 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__pad__o + wire output 297 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__oe + wire output 298 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__core__i + wire output 299 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 304 \sdr_dq_12__core__o + wire input 300 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 305 \sdr_dq_12__core__oe + wire input 301 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_12__pad__i + wire input 302 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__pad__o + wire output 303 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__oe + wire output 304 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__core__i + wire output 305 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 310 \sdr_dq_13__core__o + wire input 306 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 311 \sdr_dq_13__core__oe + wire input 307 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_13__pad__i + wire input 308 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__o + wire output 309 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_13__pad__oe + wire output 310 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__core__i + wire output 311 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 316 \sdr_dq_14__core__o + wire input 312 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 317 \sdr_dq_14__core__oe + wire input 313 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_14__pad__i + wire input 314 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_14__pad__o + wire output 315 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_14__pad__oe + wire output 316 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__core__i + wire output 317 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 322 \sdr_dq_15__core__o + wire input 318 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 323 \sdr_dq_15__core__oe + wire input 319 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 324 \sdr_dq_15__pad__i + wire input 320 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_15__pad__o + wire output 321 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__pad__oe + wire output 322 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 189 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400411,29 +404412,29 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 230 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__core__i + wire output 275 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 280 \sdr_dq_8__core__o + wire input 276 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 281 \sdr_dq_8__core__oe + wire input 277 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_8__pad__i + wire input 278 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_8__pad__o + wire output 279 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_8__pad__oe + wire output 280 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__core__i + wire output 281 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 286 \sdr_dq_9__core__o + wire input 282 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 287 \sdr_dq_9__core__oe + wire input 283 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_9__pad__i + wire input 284 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_dq_9__pad__o + wire output 285 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_dq_9__pad__oe + wire output 286 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 259 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -400443,81 +404444,81 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 356 \sram4k_0_wb__ack + wire output 352 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 349 \sram4k_0_wb__adr + wire width 9 input 345 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_0_wb__cyc + wire input 349 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 351 \sram4k_0_wb__dat_r + wire width 64 output 347 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 350 \sram4k_0_wb__dat_w + wire width 64 input 346 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 357 \sram4k_0_wb__err + wire input 353 \sram4k_0_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 352 \sram4k_0_wb__sel + wire width 8 input 348 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 354 \sram4k_0_wb__stb + wire input 350 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 355 \sram4k_0_wb__we + wire input 351 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 365 \sram4k_1_wb__ack + wire output 361 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 358 \sram4k_1_wb__adr + wire width 9 input 354 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_1_wb__cyc + wire input 358 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 360 \sram4k_1_wb__dat_r + wire width 64 output 356 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 359 \sram4k_1_wb__dat_w + wire width 64 input 355 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 366 \sram4k_1_wb__err + wire input 362 \sram4k_1_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 361 \sram4k_1_wb__sel + wire width 8 input 357 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 363 \sram4k_1_wb__stb + wire input 359 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 364 \sram4k_1_wb__we + wire input 360 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 374 \sram4k_2_wb__ack + wire output 370 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 367 \sram4k_2_wb__adr + wire width 9 input 363 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 371 \sram4k_2_wb__cyc + wire input 367 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 369 \sram4k_2_wb__dat_r + wire width 64 output 365 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 368 \sram4k_2_wb__dat_w + wire width 64 input 364 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 375 \sram4k_2_wb__err + wire input 371 \sram4k_2_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 370 \sram4k_2_wb__sel + wire width 8 input 366 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 372 \sram4k_2_wb__stb + wire input 368 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 373 \sram4k_2_wb__we + wire input 369 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 383 \sram4k_3_wb__ack + wire output 379 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 376 \sram4k_3_wb__adr + wire width 9 input 372 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 380 \sram4k_3_wb__cyc + wire input 376 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 378 \sram4k_3_wb__dat_r + wire width 64 output 374 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 377 \sram4k_3_wb__dat_w + wire width 64 input 373 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 384 \sram4k_3_wb__err + wire input 380 \sram4k_3_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 379 \sram4k_3_wb__sel + wire width 8 input 375 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 381 \sram4k_3_wb__stb + wire input 377 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 382 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + wire input 378 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:191943.7-191949.4" + attribute \src "libresoc.v:194239.7-194245.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -400526,7 +404527,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:191950.6-192343.4" + attribute \src "libresoc.v:194246.6-194635.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -400782,12 +404783,8 @@ module \test_issuer connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe @@ -400927,2064 +404924,2066 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:192353.1-197545.10" +attribute \src "libresoc.v:194645.1-199858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_asmcode$next[7:0]$13857 - attribute \src "libresoc.v:194947.3-194948.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_asmcode$next[7:0]$14042 + attribute \src "libresoc.v:197237.3-197238.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $0\core_bigendian_i$10$next[0:0]$13655 - attribute \src "libresoc.v:195077.3-195078.57" - wire $0\core_bigendian_i$10[0:0]$13574 - attribute \src "libresoc.v:192630.7-192630.35" - wire $0\core_bigendian_i$10[0:0]$14064 - attribute \src "libresoc.v:196436.3-196448.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $0\core_bigendian_i$10$next[0:0]$13837 + attribute \src "libresoc.v:197367.3-197368.57" + wire $0\core_bigendian_i$10[0:0]$13756 + attribute \src "libresoc.v:194920.7-194920.35" + wire $0\core_bigendian_i$10[0:0]$14249 + attribute \src "libresoc.v:198723.3-198735.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13858 - attribute \src "libresoc.v:195021.3-195022.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_cia$next[63:0]$14043 + attribute \src "libresoc.v:197311.3-197312.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13859 - attribute \src "libresoc.v:195065.3-195066.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$14044 + attribute \src "libresoc.v:197355.3-197356.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13860 - attribute \src "libresoc.v:195067.3-195068.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$14045 + attribute \src "libresoc.v:197357.3-197358.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13861 - attribute \src "libresoc.v:195069.3-195070.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$14046 + attribute \src "libresoc.v:197359.3-197360.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13862 - attribute \src "libresoc.v:195047.3-195048.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13552 - attribute \src "libresoc.v:192656.7-192656.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14072 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13863 - attribute \src "libresoc.v:195049.3-195050.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13554 - attribute \src "libresoc.v:192660.7-192660.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14074 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13864 - attribute \src "libresoc.v:195051.3-195052.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13556 - attribute \src "libresoc.v:192664.7-192664.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14076 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13865 - attribute \src "libresoc.v:195053.3-195054.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13558 - attribute \src "libresoc.v:192668.7-192668.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14078 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13866 - attribute \src "libresoc.v:195057.3-195058.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13561 - attribute \src "libresoc.v:192672.7-192672.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14080 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13867 - attribute \src "libresoc.v:195059.3-195060.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13563 - attribute \src "libresoc.v:192676.7-192676.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14082 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13868 - attribute \src "libresoc.v:195061.3-195062.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13565 - attribute \src "libresoc.v:192680.7-192680.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14084 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13869 - attribute \src "libresoc.v:195045.3-195046.71" - wire $0\core_core_core_exc_$signal[0:0]$13550 - attribute \src "libresoc.v:192654.7-192654.42" - wire $0\core_core_core_exc_$signal[0:0]$14070 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$13870 - attribute \src "libresoc.v:195027.3-195028.61" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$14047 + attribute \src "libresoc.v:197337.3-197338.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13734 + attribute \src "libresoc.v:194946.7-194946.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14257 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$14048 + attribute \src "libresoc.v:197339.3-197340.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13736 + attribute \src "libresoc.v:194950.7-194950.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14259 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$14049 + attribute \src "libresoc.v:197341.3-197342.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13738 + attribute \src "libresoc.v:194954.7-194954.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14261 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$14050 + attribute \src "libresoc.v:197343.3-197344.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13740 + attribute \src "libresoc.v:194958.7-194958.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14263 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$14051 + attribute \src "libresoc.v:197347.3-197348.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13743 + attribute \src "libresoc.v:194962.7-194962.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14265 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$14052 + attribute \src "libresoc.v:197349.3-197350.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13745 + attribute \src "libresoc.v:194966.7-194966.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14267 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$14053 + attribute \src "libresoc.v:197351.3-197352.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13747 + attribute \src "libresoc.v:194970.7-194970.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14269 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_exc_$signal$next[0:0]$14054 + attribute \src "libresoc.v:197335.3-197336.71" + wire $0\core_core_core_exc_$signal[0:0]$13732 + attribute \src "libresoc.v:194944.7-194944.42" + wire $0\core_core_core_exc_$signal[0:0]$14255 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$14055 + attribute \src "libresoc.v:197317.3-197318.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13871 - attribute \src "libresoc.v:195041.3-195042.69" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$14056 + attribute \src "libresoc.v:197331.3-197332.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13872 - attribute \src "libresoc.v:195023.3-195024.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $0\core_core_core_insn$next[31:0]$14057 + attribute \src "libresoc.v:197313.3-197314.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13873 - attribute \src "libresoc.v:195025.3-195026.65" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$14058 + attribute \src "libresoc.v:197315.3-197316.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_is_32bit$next[0:0]$13874 - attribute \src "libresoc.v:195073.3-195074.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_is_32bit$next[0:0]$14059 + attribute \src "libresoc.v:197363.3-197364.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13875 - attribute \src "libresoc.v:195019.3-195020.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $0\core_core_core_msr$next[63:0]$14060 + attribute \src "libresoc.v:197309.3-197310.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_oe$next[0:0]$13876 - attribute \src "libresoc.v:195037.3-195038.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe$next[0:0]$14061 + attribute \src "libresoc.v:197327.3-197328.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_oe_ok$next[0:0]$13877 - attribute \src "libresoc.v:195039.3-195040.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_oe_ok$next[0:0]$14062 + attribute \src "libresoc.v:197329.3-197330.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_rc$next[0:0]$13878 - attribute \src "libresoc.v:195031.3-195032.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc$next[0:0]$14063 + attribute \src "libresoc.v:197321.3-197322.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_core_rc_ok$next[0:0]$13879 - attribute \src "libresoc.v:195035.3-195036.57" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_core_rc_ok$next[0:0]$14064 + attribute \src "libresoc.v:197325.3-197326.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13880 - attribute \src "libresoc.v:195063.3-195064.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$14065 + attribute \src "libresoc.v:197353.3-197354.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13881 - attribute \src "libresoc.v:195043.3-195044.63" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$14066 + attribute \src "libresoc.v:197333.3-197334.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$13882 - attribute \src "libresoc.v:195001.3-195002.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$14067 + attribute \src "libresoc.v:197291.3-197292.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13883 - attribute \src "libresoc.v:195003.3-195004.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in1_ok$next[0:0]$14068 + attribute \src "libresoc.v:197293.3-197294.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$13884 - attribute \src "libresoc.v:195009.3-195010.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13530 - attribute \src "libresoc.v:192838.13-192838.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14101 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$13885 - attribute \src "libresoc.v:195005.3-195006.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$14069 + attribute \src "libresoc.v:197299.3-197300.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13712 + attribute \src "libresoc.v:195128.13-195128.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14286 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$14070 + attribute \src "libresoc.v:197295.3-197296.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13886 - attribute \src "libresoc.v:195013.3-195014.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13533 - attribute \src "libresoc.v:192846.7-192846.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14104 - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13887 - attribute \src "libresoc.v:195007.3-195008.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$14071 + attribute \src "libresoc.v:197303.3-197304.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13715 + attribute \src "libresoc.v:195136.7-195136.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14289 + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14072 + attribute \src "libresoc.v:197297.3-197298.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_cr_out$next[6:0]$13888 - attribute \src "libresoc.v:195015.3-195016.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14073 + attribute \src "libresoc.v:197305.3-197306.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13889 - attribute \src "libresoc.v:195071.3-195072.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14074 + attribute \src "libresoc.v:197361.3-197362.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_dststep$next[6:0]$13609 - attribute \src "libresoc.v:194937.3-194938.51" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_dststep$next[6:0]$13791 + attribute \src "libresoc.v:197227.3-197228.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_ea$next[6:0]$13890 - attribute \src "libresoc.v:194953.3-194954.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_ea$next[6:0]$14075 + attribute \src "libresoc.v:197243.3-197244.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fast1$next[2:0]$13891 - attribute \src "libresoc.v:194983.3-194984.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast1$next[2:0]$14076 + attribute \src "libresoc.v:197273.3-197274.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_fast1_ok$next[0:0]$13892 - attribute \src "libresoc.v:194985.3-194986.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast1_ok$next[0:0]$14077 + attribute \src "libresoc.v:197275.3-197276.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fast2$next[2:0]$13893 - attribute \src "libresoc.v:194987.3-194988.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fast2$next[2:0]$14078 + attribute \src "libresoc.v:197277.3-197278.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_fast2_ok$next[0:0]$13894 - attribute \src "libresoc.v:194991.3-194992.53" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_fast2_ok$next[0:0]$14079 + attribute \src "libresoc.v:197281.3-197282.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13895 - attribute \src "libresoc.v:194993.3-194994.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14080 + attribute \src "libresoc.v:197283.3-197284.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13896 - attribute \src "libresoc.v:194997.3-194998.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14081 + attribute \src "libresoc.v:197287.3-197288.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_lk$next[0:0]$13897 - attribute \src "libresoc.v:195029.3-195030.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_lk$next[0:0]$14082 + attribute \src "libresoc.v:197319.3-197320.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13610 - attribute \src "libresoc.v:194943.3-194944.47" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13792 + attribute \src "libresoc.v:197233.3-197234.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_core_pc$next[63:0]$13611 - attribute \src "libresoc.v:194915.3-194916.41" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_core_pc$next[63:0]$13793 + attribute \src "libresoc.v:197205.3-197206.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg1$next[6:0]$13898 - attribute \src "libresoc.v:194957.3-194958.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg1$next[6:0]$14083 + attribute \src "libresoc.v:197247.3-197248.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg1_ok$next[0:0]$13899 - attribute \src "libresoc.v:194959.3-194960.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg1_ok$next[0:0]$14084 + attribute \src "libresoc.v:197249.3-197250.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg2$next[6:0]$13900 - attribute \src "libresoc.v:194961.3-194962.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg2$next[6:0]$14085 + attribute \src "libresoc.v:197251.3-197252.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg2_ok$next[0:0]$13901 - attribute \src "libresoc.v:194963.3-194964.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg2_ok$next[0:0]$14086 + attribute \src "libresoc.v:197253.3-197254.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_reg3$next[6:0]$13902 - attribute \src "libresoc.v:194965.3-194966.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_reg3$next[6:0]$14087 + attribute \src "libresoc.v:197255.3-197256.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_reg3_ok$next[0:0]$13903 - attribute \src "libresoc.v:194969.3-194970.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_reg3_ok$next[0:0]$14088 + attribute \src "libresoc.v:197259.3-197260.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $0\core_core_rego$next[6:0]$13904 - attribute \src "libresoc.v:194949.3-194950.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $0\core_core_rego$next[6:0]$14089 + attribute \src "libresoc.v:197239.3-197240.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $0\core_core_spr1$next[9:0]$13905 - attribute \src "libresoc.v:194975.3-194976.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spr1$next[9:0]$14090 + attribute \src "libresoc.v:197265.3-197266.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_core_spr1_ok$next[0:0]$13906 - attribute \src "libresoc.v:194977.3-194978.51" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_core_spr1_ok$next[0:0]$14091 + attribute \src "libresoc.v:197267.3-197268.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $0\core_core_spro$next[9:0]$13907 - attribute \src "libresoc.v:194971.3-194972.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $0\core_core_spro$next[9:0]$14092 + attribute \src "libresoc.v:197261.3-197262.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13612 - attribute \src "libresoc.v:194939.3-194940.51" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13794 + attribute \src "libresoc.v:197229.3-197230.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $0\core_core_subvl$next[1:0]$13613 - attribute \src "libresoc.v:194935.3-194936.47" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_subvl$next[1:0]$13795 + attribute \src "libresoc.v:197225.3-197226.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $0\core_core_svstep$next[1:0]$13614 - attribute \src "libresoc.v:194933.3-194934.49" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $0\core_core_svstep$next[1:0]$13796 + attribute \src "libresoc.v:197223.3-197224.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $0\core_core_vl$next[6:0]$13615 - attribute \src "libresoc.v:194941.3-194942.41" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $0\core_core_vl$next[6:0]$13797 + attribute \src "libresoc.v:197231.3-197232.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13908 - attribute \src "libresoc.v:194979.3-194980.49" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14093 + attribute \src "libresoc.v:197269.3-197270.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_cr_out_ok$next[0:0]$13909 - attribute \src "libresoc.v:195017.3-195018.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_cr_out_ok$next[0:0]$14094 + attribute \src "libresoc.v:197307.3-197308.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:196021.3-196030.6" - wire width 64 $0\core_data_i$12[63:0]$13673 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $0\core_data_i$12[63:0]$13856 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_dec$next[63:0]$13616 - attribute \src "libresoc.v:194931.3-194932.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_dec$next[63:0]$13798 + attribute \src "libresoc.v:197221.3-197222.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:196134.3-196143.6" + attribute \src "libresoc.v:198421.3-198430.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:196144.3-196153.6" + attribute \src "libresoc.v:198431.3-198440.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_ea_ok$next[0:0]$13910 - attribute \src "libresoc.v:194955.3-194956.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_ea_ok$next[0:0]$14095 + attribute \src "libresoc.v:197245.3-197246.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire $0\core_eint$next[0:0]$13617 - attribute \src "libresoc.v:194929.3-194930.35" + attribute \src "libresoc.v:198074.3-198118.6" + wire $0\core_eint$next[0:0]$13799 + attribute \src "libresoc.v:197219.3-197220.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_fasto1_ok$next[0:0]$13911 - attribute \src "libresoc.v:194995.3-194996.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto1_ok$next[0:0]$14096 + attribute \src "libresoc.v:197285.3-197286.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_fasto2_ok$next[0:0]$13912 - attribute \src "libresoc.v:194999.3-195000.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_fasto2_ok$next[0:0]$14097 + attribute \src "libresoc.v:197289.3-197290.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:196183.3-196192.6" + attribute \src "libresoc.v:198470.3-198479.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196222.3-196231.6" + attribute \src "libresoc.v:198509.3-198518.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196330.3-196344.6" - wire width 3 $0\core_issue__addr$13[2:0]$13713 - attribute \src "libresoc.v:196261.3-196275.6" + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $0\core_issue__addr$13[2:0]$13896 + attribute \src "libresoc.v:198548.3-198562.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:196360.3-196374.6" + attribute \src "libresoc.v:198647.3-198661.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:196276.3-196290.6" + attribute \src "libresoc.v:198563.3-198577.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:196345.3-196359.6" + attribute \src "libresoc.v:198632.3-198646.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198354.3-198369.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $0\core_msr$next[63:0]$13618 - attribute \src "libresoc.v:194927.3-194928.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $0\core_msr$next[63:0]$13800 + attribute \src "libresoc.v:197217.3-197218.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13650 - attribute \src "libresoc.v:195099.3-195100.47" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13832 + attribute \src "libresoc.v:197389.3-197390.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_rego_ok$next[0:0]$13913 - attribute \src "libresoc.v:194951.3-194952.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_rego_ok$next[0:0]$14098 + attribute \src "libresoc.v:197241.3-197242.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_spro_ok$next[0:0]$13914 - attribute \src "libresoc.v:194973.3-194974.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_spro_ok$next[0:0]$14099 + attribute \src "libresoc.v:197263.3-197264.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:199449.3-199479.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:196474.3-196486.6" + attribute \src "libresoc.v:198761.3-198773.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $0\core_sv_a_nz$next[0:0]$13660 - attribute \src "libresoc.v:195055.3-195056.41" + attribute \src "libresoc.v:198165.3-198189.6" + wire $0\core_sv_a_nz$next[0:0]$13842 + attribute \src "libresoc.v:197345.3-197346.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:196011.3-196020.6" - wire width 3 $0\core_wen$11[2:0]$13670 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $0\core_wen$11[2:0]$13853 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $0\core_xer_out$next[0:0]$13915 - attribute \src "libresoc.v:194981.3-194982.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire $0\core_xer_out$next[0:0]$14100 + attribute \src "libresoc.v:197271.3-197272.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:195113.3-195114.43" + attribute \src "libresoc.v:197403.3-197404.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13754 - attribute \src "libresoc.v:195097.3-195098.47" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13937 + attribute \src "libresoc.v:197387.3-197388.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13755 - attribute \src "libresoc.v:195105.3-195106.43" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13938 + attribute \src "libresoc.v:197395.3-197396.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13756 - attribute \src "libresoc.v:195101.3-195102.47" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13939 + attribute \src "libresoc.v:197391.3-197392.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13757 - attribute \src "libresoc.v:195095.3-195096.43" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13940 + attribute \src "libresoc.v:197385.3-197386.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13758 - attribute \src "libresoc.v:195093.3-195094.45" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13941 + attribute \src "libresoc.v:197383.3-197384.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13759 - attribute \src "libresoc.v:195103.3-195104.37" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13942 + attribute \src "libresoc.v:197393.3-197394.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:196193.3-196201.6" - wire $0\d_cr_delay$next[0:0]$13695 - attribute \src "libresoc.v:194989.3-194990.37" + attribute \src "libresoc.v:198480.3-198488.6" + wire $0\d_cr_delay$next[0:0]$13878 + attribute \src "libresoc.v:197279.3-197280.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:196154.3-196162.6" - wire $0\d_reg_delay$next[0:0]$13689 - attribute \src "libresoc.v:195011.3-195012.39" + attribute \src "libresoc.v:198441.3-198449.6" + wire $0\d_reg_delay$next[0:0]$13872 + attribute \src "libresoc.v:197301.3-197302.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:196232.3-196240.6" - wire $0\d_xer_delay$next[0:0]$13701 - attribute \src "libresoc.v:194967.3-194968.39" + attribute \src "libresoc.v:198519.3-198527.6" + wire $0\d_xer_delay$next[0:0]$13884 + attribute \src "libresoc.v:197257.3-197258.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199480.3-199510.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196212.3-196221.6" + attribute \src "libresoc.v:198499.3-198508.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196202.3-196211.6" + attribute \src "libresoc.v:198489.3-198498.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196173.3-196182.6" + attribute \src "libresoc.v:198460.3-198469.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196163.3-196172.6" + attribute \src "libresoc.v:198450.3-198459.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196251.3-196260.6" + attribute \src "libresoc.v:198538.3-198547.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196241.3-196250.6" + attribute \src "libresoc.v:198528.3-198537.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:195751.3-195759.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13597 - attribute \src "libresoc.v:194925.3-194926.45" + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13779 + attribute \src "libresoc.v:197215.3-197216.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:196487.3-196495.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13736 - attribute \src "libresoc.v:194919.3-194920.39" + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13919 + attribute \src "libresoc.v:197209.3-197210.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:195760.3-195768.6" - wire $0\dbg_dmi_req_i$next[0:0]$13600 - attribute \src "libresoc.v:194923.3-194924.43" + attribute \src "libresoc.v:198046.3-198054.6" + wire $0\dbg_dmi_req_i$next[0:0]$13782 + attribute \src "libresoc.v:197213.3-197214.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:196402.3-196410.6" - wire $0\dbg_dmi_we_i$next[0:0]$13723 - attribute \src "libresoc.v:194921.3-194922.41" + attribute \src "libresoc.v:198689.3-198697.6" + wire $0\dbg_dmi_we_i$next[0:0]$13906 + attribute \src "libresoc.v:197211.3-197212.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13718 - attribute \src "libresoc.v:194913.3-194914.41" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13901 + attribute \src "libresoc.v:197203.3-197204.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:195769.3-195777.6" - wire $0\dec2_cur_eint$next[0:0]$13603 - attribute \src "libresoc.v:195117.3-195118.43" + attribute \src "libresoc.v:198055.3-198063.6" + wire $0\dec2_cur_eint$next[0:0]$13785 + attribute \src "libresoc.v:197407.3-197408.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13802 - attribute \src "libresoc.v:195087.3-195088.41" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13985 + attribute \src "libresoc.v:197377.3-197378.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13749 - attribute \src "libresoc.v:195107.3-195108.39" + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13932 + attribute \src "libresoc.v:197397.3-197398.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13811 - attribute \src "libresoc.v:195083.3-195084.53" + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13994 + attribute \src "libresoc.v:197373.3-197374.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:195778.3-195787.6" - wire width 2 $0\delay$next[1:0]$13606 - attribute \src "libresoc.v:195115.3-195116.27" + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $0\delay$next[1:0]$13788 + attribute \src "libresoc.v:197405.3-197406.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $0\exec_fsm_state$next[0:0]$13679 - attribute \src "libresoc.v:195033.3-195034.45" + attribute \src "libresoc.v:198370.3-198404.6" + wire $0\exec_fsm_state$next[0:0]$13862 + attribute \src "libresoc.v:197323.3-197324.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:196031.3-196041.6" + attribute \src "libresoc.v:198318.3-198328.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:195942.3-195952.6" + attribute \src "libresoc.v:198250.3-198260.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198261.3-198276.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13794 - attribute \src "libresoc.v:195089.3-195090.47" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13977 + attribute \src "libresoc.v:197379.3-197380.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:197394.3-197404.6" + attribute \src "libresoc.v:199702.3-199712.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:196976.3-196986.6" + attribute \src "libresoc.v:199263.3-199273.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196657.3-196667.6" + attribute \src "libresoc.v:198944.3-198954.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199334.3-199349.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $0\fsm_state$next[1:0]$13708 - attribute \src "libresoc.v:194945.3-194946.35" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $0\fsm_state$next[1:0]$13891 + attribute \src "libresoc.v:197235.3-197236.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:192354.7-192354.20" + attribute \src "libresoc.v:194646.7-194646.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $0\issue_fsm_state$next[2:0]$13819 - attribute \src "libresoc.v:195081.3-195082.47" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $0\issue_fsm_state$next[2:0]$14002 + attribute \src "libresoc.v:197371.3-197372.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:196648.3-196656.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13742 - attribute \src "libresoc.v:194917.3-194918.49" + attribute \src "libresoc.v:198935.3-198943.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13925 + attribute \src "libresoc.v:197207.3-197208.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:196812.3-196820.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13785 - attribute \src "libresoc.v:195119.3-195120.47" + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13968 + attribute \src "libresoc.v:197409.3-197410.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:196821.3-196850.6" - wire $0\msr_read$next[0:0]$13788 - attribute \src "libresoc.v:195091.3-195092.33" + attribute \src "libresoc.v:199108.3-199137.6" + wire $0\msr_read$next[0:0]$13971 + attribute \src "libresoc.v:197381.3-197382.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:196319.3-196329.6" + attribute \src "libresoc.v:198606.3-198616.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:196391.3-196401.6" + attribute \src "libresoc.v:198678.3-198688.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $0\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $0\nia$next[63:0]$13807 - attribute \src "libresoc.v:195085.3-195086.23" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $0\nia$next[63:0]$13990 + attribute \src "libresoc.v:197375.3-197376.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $0\pc_changed$next[0:0]$13833 - attribute \src "libresoc.v:195079.3-195080.37" + attribute \src "libresoc.v:199511.3-199577.6" + wire $0\pc_changed$next[0:0]$14018 + attribute \src "libresoc.v:197369.3-197370.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:196411.3-196419.6" - wire $0\pc_ok_delay$next[0:0]$13726 - attribute \src "libresoc.v:195111.3-195112.39" + attribute \src "libresoc.v:198698.3-198706.6" + wire $0\pc_ok_delay$next[0:0]$13909 + attribute \src "libresoc.v:197401.3-197402.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:197327.3-197393.6" - wire $0\sv_changed$next[0:0]$13845 - attribute \src "libresoc.v:195075.3-195076.37" + attribute \src "libresoc.v:198228.3-198238.6" + wire $0\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $0\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $0\sv_changed$next[0:0]$14030 + attribute \src "libresoc.v:197365.3-197366.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:196449.3-196457.6" - wire $0\svstate_ok_delay$next[0:0]$13731 - attribute \src "libresoc.v:195109.3-195110.49" + attribute \src "libresoc.v:198736.3-198744.6" + wire $0\svstate_ok_delay$next[0:0]$13914 + attribute \src "libresoc.v:197399.3-197400.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $10\issue_fsm_state$next[2:0]$13829 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_asmcode$next[7:0]$13916 - attribute \src "libresoc.v:192624.13-192624.33" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_asmcode$next[7:0]$14101 + attribute \src "libresoc.v:194914.13-194914.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $1\core_bigendian_i$10$next[0:0]$13656 - attribute \src "libresoc.v:196436.3-196448.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $1\core_bigendian_i$10$next[0:0]$13838 + attribute \src "libresoc.v:198723.3-198735.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13917 - attribute \src "libresoc.v:192638.14-192638.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14102 + attribute \src "libresoc.v:194928.14-194928.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13918 - attribute \src "libresoc.v:192642.13-192642.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14103 + attribute \src "libresoc.v:194932.13-194932.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13919 - attribute \src "libresoc.v:192646.7-192646.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14104 + attribute \src "libresoc.v:194936.7-194936.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13920 - attribute \src "libresoc.v:192650.13-192650.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14105 + attribute \src "libresoc.v:194940.13-194940.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13921 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13922 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13923 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13924 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13925 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13926 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13927 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13928 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$13929 - attribute \src "libresoc.v:192701.14-192701.47" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14106 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14107 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14108 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14109 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14110 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14111 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14112 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14113 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$14114 + attribute \src "libresoc.v:194991.14-194991.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13930 - attribute \src "libresoc.v:192709.13-192709.46" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14115 + attribute \src "libresoc.v:194999.13-194999.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13931 - attribute \src "libresoc.v:192713.14-192713.41" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14116 + attribute \src "libresoc.v:195003.14-195003.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13932 - attribute \src "libresoc.v:192792.13-192792.45" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14117 + attribute \src "libresoc.v:195082.13-195082.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_is_32bit$next[0:0]$13933 - attribute \src "libresoc.v:192796.7-192796.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_is_32bit$next[0:0]$14118 + attribute \src "libresoc.v:195086.7-195086.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13934 - attribute \src "libresoc.v:192800.14-192800.55" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14119 + attribute \src "libresoc.v:195090.14-195090.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_oe$next[0:0]$13935 - attribute \src "libresoc.v:192804.7-192804.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe$next[0:0]$14120 + attribute \src "libresoc.v:195094.7-195094.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_oe_ok$next[0:0]$13936 - attribute \src "libresoc.v:192808.7-192808.34" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_oe_ok$next[0:0]$14121 + attribute \src "libresoc.v:195098.7-195098.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_rc$next[0:0]$13937 - attribute \src "libresoc.v:192812.7-192812.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc$next[0:0]$14122 + attribute \src "libresoc.v:195102.7-195102.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_core_rc_ok$next[0:0]$13938 - attribute \src "libresoc.v:192816.7-192816.34" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_core_rc_ok$next[0:0]$14123 + attribute \src "libresoc.v:195106.7-195106.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13939 - attribute \src "libresoc.v:192820.14-192820.48" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14124 + attribute \src "libresoc.v:195110.14-195110.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13940 - attribute \src "libresoc.v:192824.13-192824.44" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14125 + attribute \src "libresoc.v:195114.13-195114.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$13941 - attribute \src "libresoc.v:192828.13-192828.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14126 + attribute \src "libresoc.v:195118.13-195118.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13942 - attribute \src "libresoc.v:192832.7-192832.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14127 + attribute \src "libresoc.v:195122.7-195122.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$13943 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$13944 - attribute \src "libresoc.v:192836.13-192836.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14128 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14129 + attribute \src "libresoc.v:195126.13-195126.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13945 - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13946 - attribute \src "libresoc.v:192844.7-192844.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14130 + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14131 + attribute \src "libresoc.v:195134.7-195134.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_cr_out$next[6:0]$13947 - attribute \src "libresoc.v:192852.13-192852.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14132 + attribute \src "libresoc.v:195142.13-195142.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13948 - attribute \src "libresoc.v:192856.7-192856.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14133 + attribute \src "libresoc.v:195146.7-195146.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_dststep$next[6:0]$13619 - attribute \src "libresoc.v:192860.13-192860.38" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_dststep$next[6:0]$13801 + attribute \src "libresoc.v:195150.13-195150.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_ea$next[6:0]$13949 - attribute \src "libresoc.v:192864.13-192864.33" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_ea$next[6:0]$14134 + attribute \src "libresoc.v:195154.13-195154.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fast1$next[2:0]$13950 - attribute \src "libresoc.v:192868.13-192868.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast1$next[2:0]$14135 + attribute \src "libresoc.v:195158.13-195158.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_fast1_ok$next[0:0]$13951 - attribute \src "libresoc.v:192872.7-192872.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast1_ok$next[0:0]$14136 + attribute \src "libresoc.v:195162.7-195162.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fast2$next[2:0]$13952 - attribute \src "libresoc.v:192876.13-192876.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fast2$next[2:0]$14137 + attribute \src "libresoc.v:195166.13-195166.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_fast2_ok$next[0:0]$13953 - attribute \src "libresoc.v:192880.7-192880.32" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_fast2_ok$next[0:0]$14138 + attribute \src "libresoc.v:195170.7-195170.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13954 - attribute \src "libresoc.v:192884.13-192884.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14139 + attribute \src "libresoc.v:195174.13-195174.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13955 - attribute \src "libresoc.v:192888.13-192888.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14140 + attribute \src "libresoc.v:195178.13-195178.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_lk$next[0:0]$13956 - attribute \src "libresoc.v:192892.7-192892.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_lk$next[0:0]$14141 + attribute \src "libresoc.v:195182.7-195182.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13620 - attribute \src "libresoc.v:192896.13-192896.36" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13802 + attribute \src "libresoc.v:195186.13-195186.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_core_pc$next[63:0]$13621 - attribute \src "libresoc.v:192900.14-192900.49" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_core_pc$next[63:0]$13803 + attribute \src "libresoc.v:195190.14-195190.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg1$next[6:0]$13957 - attribute \src "libresoc.v:192904.13-192904.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg1$next[6:0]$14142 + attribute \src "libresoc.v:195194.13-195194.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg1_ok$next[0:0]$13958 - attribute \src "libresoc.v:192908.7-192908.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg1_ok$next[0:0]$14143 + attribute \src "libresoc.v:195198.7-195198.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg2$next[6:0]$13959 - attribute \src "libresoc.v:192912.13-192912.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg2$next[6:0]$14144 + attribute \src "libresoc.v:195202.13-195202.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg2_ok$next[0:0]$13960 - attribute \src "libresoc.v:192916.7-192916.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg2_ok$next[0:0]$14145 + attribute \src "libresoc.v:195206.7-195206.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_reg3$next[6:0]$13961 - attribute \src "libresoc.v:192920.13-192920.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_reg3$next[6:0]$14146 + attribute \src "libresoc.v:195210.13-195210.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_reg3_ok$next[0:0]$13962 - attribute \src "libresoc.v:192924.7-192924.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_reg3_ok$next[0:0]$14147 + attribute \src "libresoc.v:195214.7-195214.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $1\core_core_rego$next[6:0]$13963 - attribute \src "libresoc.v:192928.13-192928.35" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $1\core_core_rego$next[6:0]$14148 + attribute \src "libresoc.v:195218.13-195218.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $1\core_core_spr1$next[9:0]$13964 - attribute \src "libresoc.v:193046.13-193046.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spr1$next[9:0]$14149 + attribute \src "libresoc.v:195336.13-195336.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_core_spr1_ok$next[0:0]$13965 - attribute \src "libresoc.v:193050.7-193050.31" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_core_spr1_ok$next[0:0]$14150 + attribute \src "libresoc.v:195340.7-195340.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $1\core_core_spro$next[9:0]$13966 - attribute \src "libresoc.v:193168.13-193168.37" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $1\core_core_spro$next[9:0]$14151 + attribute \src "libresoc.v:195458.13-195458.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13622 - attribute \src "libresoc.v:193172.13-193172.38" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13804 + attribute \src "libresoc.v:195462.13-195462.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $1\core_core_subvl$next[1:0]$13623 - attribute \src "libresoc.v:193176.13-193176.35" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_subvl$next[1:0]$13805 + attribute \src "libresoc.v:195466.13-195466.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $1\core_core_svstep$next[1:0]$13624 - attribute \src "libresoc.v:193180.13-193180.36" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $1\core_core_svstep$next[1:0]$13806 + attribute \src "libresoc.v:195470.13-195470.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $1\core_core_vl$next[6:0]$13625 - attribute \src "libresoc.v:193186.13-193186.33" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $1\core_core_vl$next[6:0]$13807 + attribute \src "libresoc.v:195476.13-195476.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13967 - attribute \src "libresoc.v:193190.13-193190.36" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14152 + attribute \src "libresoc.v:195480.13-195480.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_cr_out_ok$next[0:0]$13968 - attribute \src "libresoc.v:193198.7-193198.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_cr_out_ok$next[0:0]$14153 + attribute \src "libresoc.v:195488.7-195488.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:196021.3-196030.6" - wire width 64 $1\core_data_i$12[63:0]$13674 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198308.3-198317.6" + wire width 64 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_dec$next[63:0]$13626 - attribute \src "libresoc.v:193214.14-193214.45" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_dec$next[63:0]$13808 + attribute \src "libresoc.v:195504.14-195504.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:196134.3-196143.6" + attribute \src "libresoc.v:198421.3-198430.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:196144.3-196153.6" + attribute \src "libresoc.v:198431.3-198440.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_ea_ok$next[0:0]$13969 - attribute \src "libresoc.v:193224.7-193224.24" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_ea_ok$next[0:0]$14154 + attribute \src "libresoc.v:195514.7-195514.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire $1\core_eint$next[0:0]$13627 - attribute \src "libresoc.v:193228.7-193228.23" + attribute \src "libresoc.v:198074.3-198118.6" + wire $1\core_eint$next[0:0]$13809 + attribute \src "libresoc.v:195518.7-195518.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_fasto1_ok$next[0:0]$13970 - attribute \src "libresoc.v:193232.7-193232.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto1_ok$next[0:0]$14155 + attribute \src "libresoc.v:195522.7-195522.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_fasto2_ok$next[0:0]$13971 - attribute \src "libresoc.v:193236.7-193236.28" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_fasto2_ok$next[0:0]$14156 + attribute \src "libresoc.v:195526.7-195526.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:196183.3-196192.6" + attribute \src "libresoc.v:198470.3-198479.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196222.3-196231.6" + attribute \src "libresoc.v:198509.3-198518.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196330.3-196344.6" - wire width 3 $1\core_issue__addr$13[2:0]$13714 - attribute \src "libresoc.v:196261.3-196275.6" + attribute \src "libresoc.v:198617.3-198631.6" + wire width 3 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198548.3-198562.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:196360.3-196374.6" + attribute \src "libresoc.v:198647.3-198661.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:196276.3-196290.6" + attribute \src "libresoc.v:198563.3-198577.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:196345.3-196359.6" + attribute \src "libresoc.v:198632.3-198646.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198354.3-198369.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $1\core_msr$next[63:0]$13628 - attribute \src "libresoc.v:193264.14-193264.45" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $1\core_msr$next[63:0]$13810 + attribute \src "libresoc.v:195554.14-195554.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13651 - attribute \src "libresoc.v:193272.14-193272.37" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13833 + attribute \src "libresoc.v:195562.14-195562.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_rego_ok$next[0:0]$13972 - attribute \src "libresoc.v:193276.7-193276.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_rego_ok$next[0:0]$14157 + attribute \src "libresoc.v:195566.7-195566.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_spro_ok$next[0:0]$13973 - attribute \src "libresoc.v:193280.7-193280.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_spro_ok$next[0:0]$14158 + attribute \src "libresoc.v:195570.7-195570.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:199449.3-199479.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:196474.3-196486.6" + attribute \src "libresoc.v:198761.3-198773.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $1\core_sv_a_nz$next[0:0]$13661 - attribute \src "libresoc.v:193292.7-193292.26" + attribute \src "libresoc.v:198165.3-198189.6" + wire $1\core_sv_a_nz$next[0:0]$13843 + attribute \src "libresoc.v:195582.7-195582.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:196011.3-196020.6" - wire width 3 $1\core_wen$11[2:0]$13671 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198298.3-198307.6" + wire width 3 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $1\core_xer_out$next[0:0]$13974 - attribute \src "libresoc.v:193302.7-193302.26" + attribute \src "libresoc.v:199713.3-199823.6" + wire $1\core_xer_out$next[0:0]$14159 + attribute \src "libresoc.v:195592.7-195592.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:193308.7-193308.30" + attribute \src "libresoc.v:195598.7-195598.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13760 - attribute \src "libresoc.v:193314.13-193314.36" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13943 + attribute \src "libresoc.v:195604.13-195604.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13761 - attribute \src "libresoc.v:193318.13-193318.34" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13944 + attribute \src "libresoc.v:195608.13-195608.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13762 - attribute \src "libresoc.v:193322.13-193322.36" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13945 + attribute \src "libresoc.v:195612.13-195612.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13763 - attribute \src "libresoc.v:193326.13-193326.33" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13946 + attribute \src "libresoc.v:195616.13-195616.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13764 - attribute \src "libresoc.v:193330.13-193330.34" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13947 + attribute \src "libresoc.v:195620.13-195620.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13765 - attribute \src "libresoc.v:193334.13-193334.31" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13948 + attribute \src "libresoc.v:195624.13-195624.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:196193.3-196201.6" - wire $1\d_cr_delay$next[0:0]$13696 - attribute \src "libresoc.v:193338.7-193338.24" + attribute \src "libresoc.v:198480.3-198488.6" + wire $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:195628.7-195628.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:196154.3-196162.6" - wire $1\d_reg_delay$next[0:0]$13690 - attribute \src "libresoc.v:193342.7-193342.25" + attribute \src "libresoc.v:198441.3-198449.6" + wire $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:195632.7-195632.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:196232.3-196240.6" - wire $1\d_xer_delay$next[0:0]$13702 - attribute \src "libresoc.v:193346.7-193346.25" + attribute \src "libresoc.v:198519.3-198527.6" + wire $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:195636.7-195636.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199480.3-199510.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196212.3-196221.6" + attribute \src "libresoc.v:198499.3-198508.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196202.3-196211.6" + attribute \src "libresoc.v:198489.3-198498.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196173.3-196182.6" + attribute \src "libresoc.v:198460.3-198469.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196163.3-196172.6" + attribute \src "libresoc.v:198450.3-198459.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196251.3-196260.6" + attribute \src "libresoc.v:198538.3-198547.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196241.3-196250.6" + attribute \src "libresoc.v:198528.3-198537.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:195751.3-195759.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13598 - attribute \src "libresoc.v:193394.13-193394.34" + attribute \src "libresoc.v:198037.3-198045.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:195684.13-195684.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:196487.3-196495.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13737 - attribute \src "libresoc.v:193398.14-193398.48" + attribute \src "libresoc.v:198774.3-198782.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:195688.14-195688.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:195760.3-195768.6" - wire $1\dbg_dmi_req_i$next[0:0]$13601 - attribute \src "libresoc.v:193404.7-193404.27" + attribute \src "libresoc.v:198046.3-198054.6" + wire $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:195694.7-195694.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:196402.3-196410.6" - wire $1\dbg_dmi_we_i$next[0:0]$13724 - attribute \src "libresoc.v:193408.7-193408.26" + attribute \src "libresoc.v:198689.3-198697.6" + wire $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:195698.7-195698.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13719 - attribute \src "libresoc.v:193462.14-193462.49" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13902 + attribute \src "libresoc.v:195752.14-195752.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:195769.3-195777.6" - wire $1\dec2_cur_eint$next[0:0]$13604 - attribute \src "libresoc.v:193466.7-193466.27" + attribute \src "libresoc.v:198055.3-198063.6" + wire $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:195756.7-195756.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13803 - attribute \src "libresoc.v:193470.14-193470.49" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13986 + attribute \src "libresoc.v:195760.14-195760.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13750 - attribute \src "libresoc.v:193474.14-193474.48" + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13933 + attribute \src "libresoc.v:195764.14-195764.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13812 - attribute \src "libresoc.v:193626.14-193626.40" + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:195916.14-195916.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:195778.3-195787.6" - wire width 2 $1\delay$next[1:0]$13607 - attribute \src "libresoc.v:193896.13-193896.25" + attribute \src "libresoc.v:198064.3-198073.6" + wire width 2 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:196186.13-196186.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $1\exec_fsm_state$next[0:0]$13680 - attribute \src "libresoc.v:193912.7-193912.28" + attribute \src "libresoc.v:198370.3-198404.6" + wire $1\exec_fsm_state$next[0:0]$13863 + attribute \src "libresoc.v:196202.7-196202.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:196031.3-196041.6" + attribute \src "libresoc.v:198318.3-198328.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:195942.3-195952.6" + attribute \src "libresoc.v:198250.3-198260.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198261.3-198276.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13795 - attribute \src "libresoc.v:193924.13-193924.35" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13978 + attribute \src "libresoc.v:196214.13-196214.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:197394.3-197404.6" + attribute \src "libresoc.v:199702.3-199712.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:196976.3-196986.6" + attribute \src "libresoc.v:199263.3-199273.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196657.3-196667.6" + attribute \src "libresoc.v:198944.3-198954.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199334.3-199349.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $1\fsm_state$next[1:0]$13709 - attribute \src "libresoc.v:193936.13-193936.29" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $1\fsm_state$next[1:0]$13892 + attribute \src "libresoc.v:196226.13-196226.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $1\issue_fsm_state$next[2:0]$13820 - attribute \src "libresoc.v:194196.13-194196.35" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $1\issue_fsm_state$next[2:0]$14003 + attribute \src "libresoc.v:196486.13-196486.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:196648.3-196656.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:194200.7-194200.30" + attribute \src "libresoc.v:198935.3-198943.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:196490.7-196490.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:196812.3-196820.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13786 - attribute \src "libresoc.v:194208.14-194208.52" + attribute \src "libresoc.v:199099.3-199107.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:196498.14-196498.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:196821.3-196850.6" - wire $1\msr_read$next[0:0]$13789 - attribute \src "libresoc.v:194266.7-194266.22" + attribute \src "libresoc.v:199108.3-199137.6" + wire $1\msr_read$next[0:0]$13972 + attribute \src "libresoc.v:196556.7-196556.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:196319.3-196329.6" + attribute \src "libresoc.v:198606.3-198616.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:196391.3-196401.6" + attribute \src "libresoc.v:198678.3-198688.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $1\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $1\nia$next[63:0]$13808 - attribute \src "libresoc.v:194304.14-194304.40" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:196596.14-196596.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $1\pc_changed$next[0:0]$13834 - attribute \src "libresoc.v:194310.7-194310.24" + attribute \src "libresoc.v:199511.3-199577.6" + wire $1\pc_changed$next[0:0]$14019 + attribute \src "libresoc.v:196602.7-196602.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:196411.3-196419.6" - wire $1\pc_ok_delay$next[0:0]$13727 - attribute \src "libresoc.v:194320.7-194320.25" + attribute \src "libresoc.v:198698.3-198706.6" + wire $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:196612.7-196612.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:197327.3-197393.6" - wire $1\sv_changed$next[0:0]$13846 - attribute \src "libresoc.v:194764.7-194764.24" + attribute \src "libresoc.v:198228.3-198238.6" + wire $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198239.3-198249.6" + wire $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:199635.3-199701.6" + wire $1\sv_changed$next[0:0]$14031 + attribute \src "libresoc.v:197056.7-197056.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:196449.3-196457.6" - wire $1\svstate_ok_delay$next[0:0]$13732 - attribute \src "libresoc.v:194774.7-194774.30" + attribute \src "libresoc.v:198736.3-198744.6" + wire $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:197066.7-197066.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_asmcode$next[7:0]$13975 - attribute \src "libresoc.v:195854.3-195878.6" - wire $2\core_bigendian_i$10$next[0:0]$13657 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13976 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13977 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13978 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13979 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13980 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13981 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13982 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13983 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13984 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13985 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13986 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13987 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$13988 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13989 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13990 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13991 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_is_32bit$next[0:0]$13992 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13993 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_oe$next[0:0]$13994 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_oe_ok$next[0:0]$13995 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_rc$next[0:0]$13996 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_core_rc_ok$next[0:0]$13997 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13998 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13999 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14000 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14001 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14002 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14003 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14004 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14005 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14006 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14007 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_dststep$next[6:0]$13629 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_ea$next[6:0]$14008 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fast1$next[2:0]$14009 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_fast1_ok$next[0:0]$14010 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fast2$next[2:0]$14011 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_fast2_ok$next[0:0]$14012 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14013 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14014 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_lk$next[0:0]$14015 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13630 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_core_pc$next[63:0]$13631 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg1$next[6:0]$14016 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg1_ok$next[0:0]$14017 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg2$next[6:0]$14018 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg2_ok$next[0:0]$14019 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_reg3$next[6:0]$14020 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_reg3_ok$next[0:0]$14021 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 7 $2\core_core_rego$next[6:0]$14022 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $2\core_core_spr1$next[9:0]$14023 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_core_spr1_ok$next[0:0]$14024 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 10 $2\core_core_spro$next[9:0]$14025 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13632 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $2\core_core_subvl$next[1:0]$13633 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $2\core_core_svstep$next[1:0]$13634 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $2\core_core_vl$next[6:0]$13635 - attribute \src "libresoc.v:197405.3-197515.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14026 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_cr_out_ok$next[0:0]$14027 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_asmcode$next[7:0]$14160 + attribute \src "libresoc.v:198140.3-198164.6" + wire $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14161 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14162 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14163 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14164 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14165 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14166 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14167 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14168 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14169 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14170 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14171 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14172 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$14173 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14174 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14175 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14176 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_is_32bit$next[0:0]$14177 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14178 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe$next[0:0]$14179 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_oe_ok$next[0:0]$14180 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc$next[0:0]$14181 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_core_rc_ok$next[0:0]$14182 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14183 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14184 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14185 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14186 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14187 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14188 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14189 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14190 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14191 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14192 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_dststep$next[6:0]$13811 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_ea$next[6:0]$14193 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast1$next[2:0]$14194 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast1_ok$next[0:0]$14195 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fast2$next[2:0]$14196 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_fast2_ok$next[0:0]$14197 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14198 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14199 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_lk$next[0:0]$14200 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13812 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_core_pc$next[63:0]$13813 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg1$next[6:0]$14201 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg1_ok$next[0:0]$14202 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg2$next[6:0]$14203 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg2_ok$next[0:0]$14204 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_reg3$next[6:0]$14205 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_reg3_ok$next[0:0]$14206 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 7 $2\core_core_rego$next[6:0]$14207 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spr1$next[9:0]$14208 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_core_spr1_ok$next[0:0]$14209 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 10 $2\core_core_spro$next[9:0]$14210 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13814 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_subvl$next[1:0]$13815 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $2\core_core_svstep$next[1:0]$13816 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $2\core_core_vl$next[6:0]$13817 + attribute \src "libresoc.v:199713.3-199823.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14211 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_cr_out_ok$next[0:0]$14212 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_dec$next[63:0]$13636 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_ea_ok$next[0:0]$14028 - attribute \src "libresoc.v:195788.3-195832.6" - wire $2\core_eint$next[0:0]$13637 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_fasto1_ok$next[0:0]$14029 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_fasto2_ok$next[0:0]$14030 - attribute \src "libresoc.v:196067.3-196082.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_dec$next[63:0]$13818 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_ea_ok$next[0:0]$14213 + attribute \src "libresoc.v:198074.3-198118.6" + wire $2\core_eint$next[0:0]$13819 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto1_ok$next[0:0]$14214 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_fasto2_ok$next[0:0]$14215 + attribute \src "libresoc.v:198354.3-198369.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198329.3-198353.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $2\core_msr$next[63:0]$13638 - attribute \src "libresoc.v:196632.3-196647.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $2\core_msr$next[63:0]$13820 + attribute \src "libresoc.v:198919.3-198934.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13652 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_rego_ok$next[0:0]$14031 - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_spro_ok$next[0:0]$14032 - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_rego_ok$next[0:0]$14216 + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_spro_ok$next[0:0]$14217 + attribute \src "libresoc.v:199449.3-199479.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $2\core_sv_a_nz$next[0:0]$13662 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198165.3-198189.6" + wire $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:197405.3-197515.6" - wire $2\core_xer_out$next[0:0]$14033 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13766 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13767 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13768 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13769 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13770 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13771 - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199713.3-199823.6" + wire $2\core_xer_out$next[0:0]$14218 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13949 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13950 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13951 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13952 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13953 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "libresoc.v:199480.3-199510.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196375.3-196390.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13720 - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13804 - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13751 - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13813 - attribute \src "libresoc.v:196083.3-196117.6" - wire $2\exec_fsm_state$next[0:0]$13681 - attribute \src "libresoc.v:195953.3-195968.6" + attribute \src "libresoc.v:198662.3-198677.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "libresoc.v:198370.3-198404.6" + wire $2\exec_fsm_state$next[0:0]$13864 + attribute \src "libresoc.v:198261.3-198276.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:196118.3-196133.6" + attribute \src "libresoc.v:198405.3-198420.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13796 - attribute \src "libresoc.v:197044.3-197059.6" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "libresoc.v:199334.3-199349.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:196291.3-196318.6" - wire width 2 $2\fsm_state$next[1:0]$13710 - attribute \src "libresoc.v:196668.3-196683.6" + attribute \src "libresoc.v:198578.3-198605.6" + wire width 2 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198955.3-198970.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:198971.3-199004.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $2\issue_fsm_state$next[2:0]$13821 - attribute \src "libresoc.v:196821.3-196850.6" - wire $2\msr_read$next[0:0]$13790 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "libresoc.v:199108.3-199137.6" + wire $2\msr_read$next[0:0]$13973 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $2\next_srcstep[6:0] - attribute \src "libresoc.v:196926.3-196944.6" - wire width 64 $2\nia$next[63:0]$13809 - attribute \src "libresoc.v:196420.3-196435.6" + attribute \src "libresoc.v:199213.3-199231.6" + wire width 64 $2\nia$next[63:0]$13992 + attribute \src "libresoc.v:198707.3-198722.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $2\pc_changed$next[0:0]$13835 - attribute \src "libresoc.v:197327.3-197393.6" - wire $2\sv_changed$next[0:0]$13847 - attribute \src "libresoc.v:196458.3-196473.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $2\pc_changed$next[0:0]$14020 + attribute \src "libresoc.v:199635.3-199701.6" + wire $2\sv_changed$next[0:0]$14032 + attribute \src "libresoc.v:198745.3-198760.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199578.3-199634.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:195854.3-195878.6" - wire $3\core_bigendian_i$10$next[0:0]$13658 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14034 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14035 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14036 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14037 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14038 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14039 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14040 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14041 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14042 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_oe_ok$next[0:0]$14043 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_core_rc_ok$next[0:0]$14044 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14045 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14046 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14047 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14048 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_dststep$next[6:0]$13639 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_fast1_ok$next[0:0]$14049 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_fast2_ok$next[0:0]$14050 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13640 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_core_pc$next[63:0]$13641 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg1_ok$next[0:0]$14051 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg2_ok$next[0:0]$14052 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_reg3_ok$next[0:0]$14053 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_core_spr1_ok$next[0:0]$14054 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13642 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $3\core_core_subvl$next[1:0]$13643 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 2 $3\core_core_svstep$next[1:0]$13644 - attribute \src "libresoc.v:195788.3-195832.6" - wire width 7 $3\core_core_vl$next[6:0]$13645 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_cr_out_ok$next[0:0]$14055 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198140.3-198164.6" + wire $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14219 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14220 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14221 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14222 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14223 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14224 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14225 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14226 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14227 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_oe_ok$next[0:0]$14228 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_core_rc_ok$next[0:0]$14229 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14230 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14231 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14232 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14233 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_dststep$next[6:0]$13821 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast1_ok$next[0:0]$14234 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_fast2_ok$next[0:0]$14235 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13822 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_core_pc$next[63:0]$13823 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg1_ok$next[0:0]$14236 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg2_ok$next[0:0]$14237 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_reg3_ok$next[0:0]$14238 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_core_spr1_ok$next[0:0]$14239 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13824 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_subvl$next[1:0]$13825 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 2 $3\core_core_svstep$next[1:0]$13826 + attribute \src "libresoc.v:198074.3-198118.6" + wire width 7 $3\core_core_vl$next[6:0]$13827 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_cr_out_ok$next[0:0]$14240 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_dec$next[63:0]$13646 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_ea_ok$next[0:0]$14056 - attribute \src "libresoc.v:195788.3-195832.6" - wire $3\core_eint$next[0:0]$13647 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_fasto1_ok$next[0:0]$14057 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_fasto2_ok$next[0:0]$14058 - attribute \src "libresoc.v:196042.3-196066.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_dec$next[63:0]$13828 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_ea_ok$next[0:0]$14241 + attribute \src "libresoc.v:198074.3-198118.6" + wire $3\core_eint$next[0:0]$13829 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto1_ok$next[0:0]$14242 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_fasto2_ok$next[0:0]$14243 + attribute \src "libresoc.v:198329.3-198353.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:195788.3-195832.6" - wire width 64 $3\core_msr$next[63:0]$13648 - attribute \src "libresoc.v:195833.3-195853.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13653 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_rego_ok$next[0:0]$14059 - attribute \src "libresoc.v:197405.3-197515.6" - wire $3\core_spro_ok$next[0:0]$14060 - attribute \src "libresoc.v:197141.3-197171.6" + attribute \src "libresoc.v:198074.3-198118.6" + wire width 64 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198119.3-198139.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_rego_ok$next[0:0]$14244 + attribute \src "libresoc.v:199713.3-199823.6" + wire $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199449.3-199479.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:195879.3-195903.6" - wire $3\core_sv_a_nz$next[0:0]$13663 - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198165.3-198189.6" + wire $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13772 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13773 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13774 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13775 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13776 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13777 - attribute \src "libresoc.v:197172.3-197202.6" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13955 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13956 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13957 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13958 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13959 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13960 + attribute \src "libresoc.v:199480.3-199510.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:196905.3-196925.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13805 - attribute \src "libresoc.v:196752.3-196772.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13752 - attribute \src "libresoc.v:196945.3-196975.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13814 - attribute \src "libresoc.v:196083.3-196117.6" - wire $3\exec_fsm_state$next[0:0]$13682 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13797 - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:199192.3-199212.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199039.3-199059.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199232.3-199262.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "libresoc.v:198370.3-198404.6" + wire $3\exec_fsm_state$next[0:0]$13865 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "libresoc.v:198971.3-199004.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:195990.3-196010.6" + attribute \src "libresoc.v:198277.3-198297.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $3\issue_fsm_state$next[2:0]$13822 - attribute \src "libresoc.v:196821.3-196850.6" - wire $3\msr_read$next[0:0]$13791 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "libresoc.v:199108.3-199137.6" + wire $3\msr_read$next[0:0]$13974 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:195969.3-195989.6" - wire width 7 $3\next_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $3\pc_changed$next[0:0]$13836 - attribute \src "libresoc.v:197327.3-197393.6" - wire $3\sv_changed$next[0:0]$13848 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $3\pc_changed$next[0:0]$14021 + attribute \src "libresoc.v:199635.3-199701.6" + wire $3\sv_changed$next[0:0]$14033 + attribute \src "libresoc.v:199578.3-199634.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13778 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13779 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13780 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13781 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13782 - attribute \src "libresoc.v:196773.3-196811.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13783 - attribute \src "libresoc.v:196083.3-196117.6" - wire $4\exec_fsm_state$next[0:0]$13683 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13798 - attribute \src "libresoc.v:196684.3-196717.6" + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13961 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13962 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13963 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13964 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13965 + attribute \src "libresoc.v:199060.3-199098.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:198370.3-198404.6" + wire $4\exec_fsm_state$next[0:0]$13866 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "libresoc.v:198971.3-199004.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196718.3-196751.6" + attribute \src "libresoc.v:199005.3-199038.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198190.3-198227.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $4\issue_fsm_state$next[2:0]$13823 - attribute \src "libresoc.v:196821.3-196850.6" - wire $4\msr_read$next[0:0]$13792 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "libresoc.v:199108.3-199137.6" + wire $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $4\pc_changed$next[0:0]$13837 - attribute \src "libresoc.v:197327.3-197393.6" - wire $4\sv_changed$next[0:0]$13849 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $4\pc_changed$next[0:0]$14022 + attribute \src "libresoc.v:199635.3-199701.6" + wire $4\sv_changed$next[0:0]$14034 + attribute \src "libresoc.v:199578.3-199634.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:196083.3-196117.6" - wire $5\exec_fsm_state$next[0:0]$13684 - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13799 - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:198370.3-198404.6" + wire $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "libresoc.v:198190.3-198227.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $5\issue_fsm_state$next[2:0]$13824 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $5\pc_changed$next[0:0]$13838 - attribute \src "libresoc.v:197327.3-197393.6" - wire $5\sv_changed$next[0:0]$13850 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $5\pc_changed$next[0:0]$14023 + attribute \src "libresoc.v:199635.3-199701.6" + wire $5\sv_changed$next[0:0]$14035 + attribute \src "libresoc.v:199578.3-199634.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:196851.3-196904.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13800 - attribute \src "libresoc.v:195904.3-195941.6" + attribute \src "libresoc.v:199138.3-199191.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:198190.3-198227.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $6\issue_fsm_state$next[2:0]$13825 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $6\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $6\pc_changed$next[0:0]$13839 - attribute \src "libresoc.v:197327.3-197393.6" - wire $6\sv_changed$next[0:0]$13851 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $6\pc_changed$next[0:0]$14024 + attribute \src "libresoc.v:199635.3-199701.6" + wire $6\sv_changed$next[0:0]$14036 + attribute \src "libresoc.v:199578.3-199634.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $7\issue_fsm_state$next[2:0]$13826 - attribute \src "libresoc.v:196987.3-197043.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "libresoc.v:199274.3-199333.6" + wire width 7 $7\new_svstate_dststep[6:0] + attribute \src "libresoc.v:199274.3-199333.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:197203.3-197269.6" - wire $7\pc_changed$next[0:0]$13840 - attribute \src "libresoc.v:197327.3-197393.6" - wire $7\sv_changed$next[0:0]$13852 - attribute \src "libresoc.v:197270.3-197326.6" + attribute \src "libresoc.v:199511.3-199577.6" + wire $7\pc_changed$next[0:0]$14025 + attribute \src "libresoc.v:199635.3-199701.6" + wire $7\sv_changed$next[0:0]$14037 + attribute \src "libresoc.v:199578.3-199634.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $8\issue_fsm_state$next[2:0]$13827 - attribute \src "libresoc.v:197203.3-197269.6" - wire $8\pc_changed$next[0:0]$13841 - attribute \src "libresoc.v:197327.3-197393.6" - wire $8\sv_changed$next[0:0]$13853 - attribute \src "libresoc.v:196564.3-196631.6" + attribute \src "libresoc.v:199350.3-199448.6" + wire width 3 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "libresoc.v:199511.3-199577.6" + wire $8\pc_changed$next[0:0]$14026 + attribute \src "libresoc.v:199635.3-199701.6" + wire $8\sv_changed$next[0:0]$14038 + attribute \src "libresoc.v:198851.3-198918.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:196496.3-196563.6" + attribute \src "libresoc.v:198783.3-198850.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:197060.3-197140.6" - wire width 3 $9\issue_fsm_state$next[2:0]$13828 - attribute \src "libresoc.v:197203.3-197269.6" - wire $9\pc_changed$next[0:0]$13842 - attribute \src "libresoc.v:197327.3-197393.6" - wire $9\sv_changed$next[0:0]$13854 - attribute \src "libresoc.v:194791.19-194791.108" - wire width 65 $add$libresoc.v:194791$13361_Y - attribute \src "libresoc.v:194864.19-194864.112" - wire width 8 $add$libresoc.v:194864$13431_Y - attribute \src "libresoc.v:194877.19-194877.115" - wire width 65 $add$libresoc.v:194877$13446_Y - attribute \src "libresoc.v:194910.18-194910.107" - wire width 65 $add$libresoc.v:194910$13478_Y - attribute \src "libresoc.v:194796.19-194796.104" - wire $and$libresoc.v:194796$13366_Y - attribute \src "libresoc.v:194799.19-194799.104" - wire $and$libresoc.v:194799$13369_Y - attribute \src "libresoc.v:194805.19-194805.104" - wire $and$libresoc.v:194805$13374_Y - attribute \src "libresoc.v:194808.19-194808.104" - wire $and$libresoc.v:194808$13377_Y - attribute \src "libresoc.v:194810.19-194810.111" - wire $and$libresoc.v:194810$13379_Y - attribute \src "libresoc.v:194813.19-194813.104" - wire $and$libresoc.v:194813$13382_Y - attribute \src "libresoc.v:194819.19-194819.104" - wire $and$libresoc.v:194819$13387_Y - attribute \src "libresoc.v:194822.19-194822.104" - wire $and$libresoc.v:194822$13390_Y - attribute \src "libresoc.v:194825.19-194825.104" - wire $and$libresoc.v:194825$13393_Y - attribute \src "libresoc.v:194828.19-194828.104" - wire $and$libresoc.v:194828$13396_Y - attribute \src "libresoc.v:194831.19-194831.104" - wire $and$libresoc.v:194831$13399_Y - attribute \src "libresoc.v:194834.19-194834.104" - wire $and$libresoc.v:194834$13402_Y - attribute \src "libresoc.v:194835.19-194835.115" - wire width 3 $and$libresoc.v:194835$13403_Y - attribute \src "libresoc.v:194839.19-194839.104" - wire $and$libresoc.v:194839$13407_Y - attribute \src "libresoc.v:194842.19-194842.104" - wire $and$libresoc.v:194842$13410_Y - attribute \src "libresoc.v:194848.19-194848.104" - wire $and$libresoc.v:194848$13415_Y - attribute \src "libresoc.v:194851.19-194851.104" - wire $and$libresoc.v:194851$13418_Y - attribute \src "libresoc.v:194852.19-194852.115" - wire width 3 $and$libresoc.v:194852$13419_Y - attribute \src "libresoc.v:194855.19-194855.111" - wire $and$libresoc.v:194855$13422_Y - attribute \src "libresoc.v:194859.19-194859.104" - wire $and$libresoc.v:194859$13426_Y - attribute \src "libresoc.v:194863.19-194863.104" - wire $and$libresoc.v:194863$13430_Y - attribute \src "libresoc.v:194867.19-194867.104" - wire $and$libresoc.v:194867$13434_Y - attribute \src "libresoc.v:194882.18-194882.109" - wire $and$libresoc.v:194882$13451_Y - attribute \src "libresoc.v:194888.18-194888.101" - wire $and$libresoc.v:194888$13458_Y - attribute \src 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"libresoc.v:194874.19-194874.113" - wire width 64 $extend$libresoc.v:194874$13442_Y - attribute \src "libresoc.v:194885.18-194885.109" - wire width 64 $extend$libresoc.v:194885$13454_Y - attribute \src "libresoc.v:194792.19-194792.106" - wire width 7 $mul$libresoc.v:194792$13362_Y - attribute \src "libresoc.v:194911.18-194911.110" - wire width 7 $mul$libresoc.v:194911$13479_Y - attribute \src "libresoc.v:194861.18-194861.102" - wire $ne$libresoc.v:194861$13428_Y - attribute \src "libresoc.v:194870.19-194870.123" - wire $ne$libresoc.v:194870$13437_Y - attribute \src "libresoc.v:194880.18-194880.102" - wire $ne$libresoc.v:194880$13449_Y - attribute \src "libresoc.v:194794.19-194794.107" - wire $not$libresoc.v:194794$13364_Y - attribute \src "libresoc.v:194795.19-194795.109" - wire $not$libresoc.v:194795$13365_Y - attribute \src "libresoc.v:194797.19-194797.107" - wire $not$libresoc.v:194797$13367_Y - attribute \src "libresoc.v:194798.19-194798.109" - wire $not$libresoc.v:194798$13368_Y - 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width 64 $pos$libresoc.v:197175$13637_Y + attribute \src "libresoc.v:197130.19-197130.93" + wire $reduce_or$libresoc.v:197130$13590_Y + attribute \src "libresoc.v:197147.19-197147.93" + wire $reduce_or$libresoc.v:197147$13606_Y + attribute \src "libresoc.v:197085.18-197085.41" + wire width 64 $shr$libresoc.v:197085$13547_Y + attribute \src "libresoc.v:197202.18-197202.40" + wire width 64 $shr$libresoc.v:197202$13662_Y + attribute \src "libresoc.v:197165.19-197165.116" + wire width 65 $sub$libresoc.v:197165$13626_Y + attribute \src "libresoc.v:197167.18-197167.101" + wire width 3 $sub$libresoc.v:197167$13628_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + wire width 8 \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + wire width 8 \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + wire width 8 \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + wire width 8 \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$186 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - wire width 3 \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + wire width 3 \$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$220 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - wire width 3 \$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + wire width 3 \$229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$232 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - wire width 8 \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - wire width 8 \$245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + wire \$248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - wire \$251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - wire \$253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + wire \$250 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - wire \$257 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" + wire width 64 \$252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + wire \$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + wire \$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + wire \$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire width 3 \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - wire \$261 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$263 + wire width 64 \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + wire width 64 \$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + wire width 65 \$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + wire width 65 \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" wire width 65 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" wire width 65 \$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - wire width 65 \$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - wire width 65 \$271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" wire width 65 \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" wire width 65 \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 342 \TAP_bus__tck + wire input 338 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 178 \TAP_bus__tdi + wire input 176 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 333 \TAP_bus__tdo + wire output 329 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 343 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:133" + wire input 339 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" - wire input 392 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + wire input 388 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \core_bigendian_i$10 @@ -403552,7 +407551,7 @@ module \ti wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -403662,7 +407661,7 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly @@ -403694,17 +407693,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:672" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:682" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -403790,7 +407789,7 @@ module \ti wire output 15 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec2_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_cia @@ -403982,9 +407981,9 @@ module \ti wire \dec2_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc @@ -404242,7 +408241,7 @@ module \ti wire width 10 \dec2_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:691" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire \dec2_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \dec2_trapaddr @@ -404252,52 +408251,52 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \eint_0__core__i + wire output 177 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \eint_1__core__i + wire output 178 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \eint_2__core__i + wire output 179 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883" wire \exec_pc_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:863" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e10__core__i + wire output 186 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404305,11 +408304,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e10__pad__o + wire output 187 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e10__pad__oe + wire output 188 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e11__core__i + wire output 189 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404317,11 +408316,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e11__pad__o + wire output 190 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e11__pad__oe + wire output 191 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e12__core__i + wire output 192 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404329,11 +408328,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e12__pad__o + wire output 193 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e12__pad__oe + wire output 194 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_e13__core__i + wire output 195 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404341,11 +408340,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_e13__pad__o + wire output 196 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_e13__pad__oe + wire output 197 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_e14__core__i + wire output 198 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404353,11 +408352,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_e14__pad__o + wire output 199 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_e14__pad__oe + wire output 200 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_e15__core__i + wire output 201 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404365,11 +408364,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_e15__pad__o + wire output 202 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_e15__pad__oe + wire output 203 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e8__core__i + wire output 180 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404377,11 +408376,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e8__pad__o + wire output 181 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e8__pad__oe + wire output 182 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e9__core__i + wire output 183 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404389,11 +408388,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e9__pad__o + wire output 184 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e9__pad__oe + wire output 185 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s0__core__i + wire output 204 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404401,11 +408400,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s0__pad__o + wire output 205 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s0__pad__oe + wire output 206 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s1__core__i + wire output 207 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404413,11 +408412,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s1__pad__o + wire output 208 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s1__pad__oe + wire output 209 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s2__core__i + wire output 210 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404425,11 +408424,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s2__pad__o + wire output 211 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s2__pad__oe + wire output 212 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s3__core__i + wire output 213 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404437,11 +408436,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s3__pad__o + wire output 214 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s3__pad__oe + wire output 215 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s4__core__i + wire output 216 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404449,11 +408448,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s4__pad__o + wire output 217 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s4__pad__oe + wire output 218 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \gpio_s5__core__i + wire output 219 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404461,11 +408460,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \gpio_s5__pad__o + wire output 220 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \gpio_s5__pad__oe + wire output 221 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \gpio_s6__core__i + wire output 222 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404473,11 +408472,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \gpio_s6__pad__o + wire output 223 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \gpio_s6__pad__oe + wire output 224 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \gpio_s7__core__i + wire output 225 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404485,9 +408484,9 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \gpio_s7__pad__o + wire output 226 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \gpio_s7__pad__oe + wire output 227 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -404503,35 +408502,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 376 \icp_wb__ack + wire output 372 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 382 \icp_wb__adr + wire width 28 input 378 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 377 \icp_wb__cyc + wire input 373 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 378 \icp_wb__dat_r + wire width 32 output 374 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 379 \icp_wb__dat_w + wire width 32 input 375 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 383 \icp_wb__sel + wire width 4 input 379 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 380 \icp_wb__stb + wire input 376 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 381 \icp_wb__we + wire input 377 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 389 \ics_wb__ack + wire output 385 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 384 \ics_wb__adr + wire width 28 input 380 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 386 \ics_wb__cyc + wire input 382 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 388 \ics_wb__dat_r + wire width 32 output 384 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 390 \ics_wb__dat_w + wire width 32 input 386 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 387 \ics_wb__stb + wire input 383 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 391 \ics_wb__we + wire input 387 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -404544,19 +408543,19 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:192354.7-192354.15" + attribute \src "libresoc.v:194646.7-194646.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 385 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + wire width 16 input 381 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" wire \is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" wire width 3 \issue_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o @@ -404575,65 +408574,65 @@ module \ti attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 340 \jtag_wb__ack + wire input 336 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 334 \jtag_wb__adr + wire width 29 output 330 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 336 \jtag_wb__cyc + wire output 332 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 341 \jtag_wb__dat_r + wire width 64 input 337 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 339 \jtag_wb__dat_w + wire width 64 output 335 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 335 \jtag_wb__sel + wire output 331 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 337 \jtag_wb__stb + wire output 333 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 338 \jtag_wb__we + wire output 334 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mspi0_clk__pad__o + wire output 228 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mspi0_cs_n__pad__o + wire output 229 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \mspi0_miso__core__i + wire output 231 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mspi0_mosi__pad__o + wire output 230 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \mspi1_clk__pad__o + wire output 232 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \mspi1_cs_n__pad__o + wire output 233 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \mspi1_miso__core__i + wire output 235 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 82 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire output 234 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \mtwi_scl__pad__o + wire output 239 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \mtwi_sda__core__i + wire output 236 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404641,10 +408640,10 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \mtwi_sda__pad__o + wire output 237 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" + wire output 238 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -404658,48 +408657,58 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" + wire width 7 \next_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + wire \pred_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" + wire \pred_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + wire \pred_mask_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" + wire \pred_mask_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \pwm_0__pad__o + wire output 240 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 88 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + wire output 241 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_clk__pad__o + wire output 245 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_cmd__core__i + wire output 242 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404707,11 +408716,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_cmd__pad__o + wire output 243 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_cmd__pad__oe + wire output 244 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data0__core__i + wire output 246 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404719,11 +408728,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data0__pad__o + wire output 247 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data0__pad__oe + wire output 248 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sd0_data1__core__i + wire output 249 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404731,11 +408740,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sd0_data1__pad__o + wire output 250 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sd0_data1__pad__oe + wire output 251 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sd0_data2__core__i + wire output 252 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404743,11 +408752,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sd0_data2__pad__o + wire output 253 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sd0_data2__pad__oe + wire output 254 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sd0_data3__core__i + wire output 255 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404755,103 +408764,95 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sd0_data3__pad__o + wire output 256 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sd0_data3__pad__oe + wire output 257 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_0__pad__o + wire output 283 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 148 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_a_10__pad__o + wire output 301 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 149 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_a_11__pad__o + wire output 302 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 150 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_a_12__pad__o + wire output 303 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_a_1__pad__o + wire output 284 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_2__pad__o + wire output 285 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_3__pad__o + wire output 286 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_4__pad__o + wire output 287 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_5__pad__o + wire output 288 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_6__pad__o + wire output 289 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_7__pad__o + wire output 290 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 138 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_a_8__pad__o + wire output 291 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 139 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_a_9__pad__o + wire output 292 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 140 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_ba_0__pad__o + wire output 293 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 141 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_ba_1__pad__o + wire output 294 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_cas_n__pad__o + wire output 298 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 143 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_cke__pad__o + wire output 296 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 142 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_clock__pad__o + wire output 295 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 147 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_cs_n__pad__o + wire output 300 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dm_0__pad__o + wire output 258 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dm_1__core__i + wire input 151 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dm_1__core__o + wire output 304 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_0__core__i + wire output 259 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 107 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404859,83 +408860,83 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_0__pad__o + wire output 260 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_0__pad__oe + wire output 261 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_10__core__i + wire output 311 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_10__core__o + wire input 159 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_10__core__oe + wire input 160 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_10__pad__i + wire input 158 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_10__pad__o + wire output 312 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_10__pad__oe + wire output 313 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_11__core__i + wire output 314 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_11__core__o + wire input 162 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_11__core__oe + wire input 163 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_11__pad__i + wire input 161 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_11__pad__o + wire output 315 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_11__pad__oe + wire output 316 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_12__core__i + wire output 317 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_12__core__o + wire input 165 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_12__core__oe + wire input 166 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_12__pad__i + wire input 164 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_12__pad__o + wire output 318 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_12__pad__oe + wire output 319 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 324 \sdr_dq_13__core__i + wire output 320 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_13__core__o + wire input 168 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_13__core__oe + wire input 169 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 169 \sdr_dq_13__pad__i + wire input 167 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_13__pad__o + wire output 321 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_13__pad__oe + wire output 322 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 327 \sdr_dq_14__core__i + wire output 323 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 173 \sdr_dq_14__core__o + wire input 171 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 174 \sdr_dq_14__core__oe + wire input 172 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_14__pad__i + wire input 170 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 328 \sdr_dq_14__pad__o + wire output 324 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 329 \sdr_dq_14__pad__oe + wire output 325 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 330 \sdr_dq_15__core__i + wire output 326 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sdr_dq_15__core__o + wire input 174 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sdr_dq_15__core__oe + wire input 175 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 175 \sdr_dq_15__pad__i + wire input 173 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 331 \sdr_dq_15__pad__o + wire output 327 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 332 \sdr_dq_15__pad__oe + wire output 328 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_1__core__i + wire output 262 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 110 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404943,11 +408944,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_1__pad__o + wire output 263 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_1__pad__oe + wire output 264 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_2__core__i + wire output 265 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 113 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404955,11 +408956,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_2__pad__o + wire output 266 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_2__pad__oe + wire output 267 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_3__core__i + wire output 268 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 116 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404967,11 +408968,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_3__pad__o + wire output 269 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_3__pad__oe + wire output 270 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_4__core__i + wire output 271 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404979,11 +408980,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_4__pad__o + wire output 272 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_4__pad__oe + wire output 273 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_5__core__i + wire output 274 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404991,11 +408992,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_5__pad__o + wire output 275 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_5__pad__oe + wire output 276 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_6__core__i + wire output 277 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -405003,11 +409004,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_6__pad__o + wire output 278 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_6__pad__oe + wire output 279 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_7__core__i + wire output 280 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -405015,130 +409016,130 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_7__pad__o + wire output 281 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_7__pad__oe + wire output 282 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_8__core__i + wire output 305 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_8__core__o + wire input 153 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_8__core__oe + wire input 154 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_8__pad__i + wire input 152 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_8__pad__o + wire output 306 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_8__pad__oe + wire output 307 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_9__core__i + wire output 308 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_9__core__o + wire input 156 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_9__core__oe + wire input 157 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_9__pad__i + wire input 155 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_9__pad__o + wire output 309 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_9__pad__oe + wire output 310 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 144 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_ras_n__pad__o + wire output 297 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_we_n__pad__o + wire output 299 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_0_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 346 \sram4k_0_wb__ack + wire output 342 \sram4k_0_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 347 \sram4k_0_wb__adr + wire width 9 input 343 \sram4k_0_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 344 \sram4k_0_wb__cyc + wire input 340 \sram4k_0_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 348 \sram4k_0_wb__dat_r + wire width 64 output 344 \sram4k_0_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 349 \sram4k_0_wb__dat_w + wire width 64 input 345 \sram4k_0_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 351 \sram4k_0_wb__sel + wire width 8 input 347 \sram4k_0_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 345 \sram4k_0_wb__stb + wire input 341 \sram4k_0_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 350 \sram4k_0_wb__we + wire input 346 \sram4k_0_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_1_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 354 \sram4k_1_wb__ack + wire output 350 \sram4k_1_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 355 \sram4k_1_wb__adr + wire width 9 input 351 \sram4k_1_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 352 \sram4k_1_wb__cyc + wire input 348 \sram4k_1_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 356 \sram4k_1_wb__dat_r + wire width 64 output 352 \sram4k_1_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 357 \sram4k_1_wb__dat_w + wire width 64 input 353 \sram4k_1_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 359 \sram4k_1_wb__sel + wire width 8 input 355 \sram4k_1_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_1_wb__stb + wire input 349 \sram4k_1_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 358 \sram4k_1_wb__we + wire input 354 \sram4k_1_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_2_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 362 \sram4k_2_wb__ack + wire output 358 \sram4k_2_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 363 \sram4k_2_wb__adr + wire width 9 input 359 \sram4k_2_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 360 \sram4k_2_wb__cyc + wire input 356 \sram4k_2_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 364 \sram4k_2_wb__dat_r + wire width 64 output 360 \sram4k_2_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 365 \sram4k_2_wb__dat_w + wire width 64 input 361 \sram4k_2_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 367 \sram4k_2_wb__sel + wire width 8 input 363 \sram4k_2_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 361 \sram4k_2_wb__stb + wire input 357 \sram4k_2_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 366 \sram4k_2_wb__we + wire input 362 \sram4k_2_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" wire \sram4k_3_enable attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 370 \sram4k_3_wb__ack + wire output 366 \sram4k_3_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 371 \sram4k_3_wb__adr + wire width 9 input 367 \sram4k_3_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 368 \sram4k_3_wb__cyc + wire input 364 \sram4k_3_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 372 \sram4k_3_wb__dat_r + wire width 64 output 368 \sram4k_3_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 373 \sram4k_3_wb__dat_w + wire width 64 input 369 \sram4k_3_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 375 \sram4k_3_wb__sel + wire width 8 input 371 \sram4k_3_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 369 \sram4k_3_wb__stb + wire input 365 \sram4k_3_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 374 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + wire input 370 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \sv_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \svstate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \svstate_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:498" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -405150,8 +409151,8 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - cell $add $add$libresoc.v:194791$13361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" + cell $add $add$libresoc.v:197083$13545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405159,10 +409160,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:194791$13361_Y + connect \Y $add$libresoc.v:197083$13545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" - cell $add $add$libresoc.v:194864$13431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" + cell $add $add$libresoc.v:197095$13556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405170,10 +409171,21 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:194864$13431_Y + connect \Y $add$libresoc.v:197095$13556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" - cell $add $add$libresoc.v:194877$13446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" + cell $add $add$libresoc.v:197096$13557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \cur_cur_dststep + connect \B 1'1 + connect \Y $add$libresoc.v:197096$13557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + cell $add $add$libresoc.v:197166$13627 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405181,10 +409193,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:194877$13446_Y + connect \Y $add$libresoc.v:197166$13627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" - cell $add $add$libresoc.v:194910$13478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" + cell $add $add$libresoc.v:197200$13660 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405192,10 +409204,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:194910$13478_Y + connect \Y $add$libresoc.v:197200$13660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194796$13366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197088$13550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405203,10 +409215,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:194796$13366_Y + connect \Y $and$libresoc.v:197088$13550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194799$13369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197091$13553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405214,21 +409226,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:194799$13369_Y + connect \Y $and$libresoc.v:197091$13553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194805$13374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$124 - connect \B \$126 - connect \Y $and$libresoc.v:194805$13374_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194808$13377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197099$13560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405236,43 +409237,43 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:194808$13377_Y + connect \Y $and$libresoc.v:197099$13560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194810$13379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197102$13563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_svp64_mode - connect \B \$136 - connect \Y $and$libresoc.v:194810$13379_Y + connect \A \$136 + connect \B \$138 + connect \Y $and$libresoc.v:197102$13563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194813$13382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197104$13565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$140 + connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:194813$13382_Y + connect \Y $and$libresoc.v:197104$13565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194819$13387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197107$13568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$152 - connect \B \$154 - connect \Y $and$libresoc.v:194819$13387_Y + connect \A \$146 + connect \B \$148 + connect \Y $and$libresoc.v:197107$13568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194822$13390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197113$13573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405280,10 +409281,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:194822$13390_Y + connect \Y $and$libresoc.v:197113$13573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194825$13393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197116$13576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405291,10 +409292,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:194825$13393_Y + connect \Y $and$libresoc.v:197116$13576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194828$13396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197119$13579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405302,10 +409303,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:194828$13396_Y + connect \Y $and$libresoc.v:197119$13579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194831$13399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197122$13582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405313,10 +409314,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:194831$13399_Y + connect \Y $and$libresoc.v:197122$13582_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194834$13402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197125$13585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405324,10 +409325,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:194834$13402_Y + connect \Y $and$libresoc.v:197125$13585_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - cell $and $and$libresoc.v:194835$13403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197128$13588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$188 + connect \B \$190 + connect \Y $and$libresoc.v:197128$13588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + cell $and $and$libresoc.v:197129$13589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -405335,54 +409347,54 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:194835$13403_Y + connect \Y $and$libresoc.v:197129$13589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194839$13407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197133$13593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$192 - connect \B \$194 - connect \Y $and$libresoc.v:194839$13407_Y + connect \A \$198 + connect \B \$200 + connect \Y $and$libresoc.v:197133$13593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194842$13410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197136$13596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$198 - connect \B \$200 - connect \Y $and$libresoc.v:194842$13410_Y + connect \A \$204 + connect \B \$206 + connect \Y $and$libresoc.v:197136$13596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194848$13415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197142$13601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$210 - connect \B \$212 - connect \Y $and$libresoc.v:194848$13415_Y + connect \A \$216 + connect \B \$218 + connect \Y $and$libresoc.v:197142$13601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194851$13418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197145$13604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$216 - connect \B \$218 - connect \Y $and$libresoc.v:194851$13418_Y + connect \A \$222 + connect \B \$224 + connect \Y $and$libresoc.v:197145$13604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - cell $and $and$libresoc.v:194852$13419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + cell $and $and$libresoc.v:197146$13605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -405390,32 +409402,21 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:194852$13419_Y + connect \Y $and$libresoc.v:197146$13605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194855$13422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197149$13608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode - connect \B \$226 - connect \Y $and$libresoc.v:194855$13422_Y + connect \B \$232 + connect \Y $and$libresoc.v:197149$13608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194859$13426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$232 - connect \B \$234 - connect \Y $and$libresoc.v:194859$13426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194863$13430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197154$13613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405423,21 +409424,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \$238 connect \B \$240 - connect \Y $and$libresoc.v:194863$13430_Y + connect \Y $and$libresoc.v:197154$13613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194867$13434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197157$13616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$247 - connect \B \$249 - connect \Y $and$libresoc.v:194867$13434_Y + connect \A \$244 + connect \B \$246 + connect \Y $and$libresoc.v:197157$13616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:194882$13451 + cell $and $and$libresoc.v:197172$13633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405445,10 +409446,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:194882$13451_Y + connect \Y $and$libresoc.v:197172$13633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194888$13458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197178$13640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405456,10 +409457,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:194888$13458_Y + connect \Y $and$libresoc.v:197178$13640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194890$13460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197180$13642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405467,10 +409468,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:194890$13460_Y + connect \Y $and$libresoc.v:197180$13642_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194893$13463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197183$13645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405478,10 +409479,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:194893$13463_Y + connect \Y $and$libresoc.v:197183$13645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $and $and$libresoc.v:194899$13468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $and $and$libresoc.v:197189$13650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405489,10 +409490,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:194899$13468_Y + connect \Y $and$libresoc.v:197189$13650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $and $and$libresoc.v:194901$13470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $and $and$libresoc.v:197191$13652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405500,10 +409501,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:194901$13470_Y + connect \Y $and$libresoc.v:197191$13652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $and $and$libresoc.v:194904$13473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $and $and$libresoc.v:197194$13655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405511,10 +409512,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:194904$13473_Y + connect \Y $and$libresoc.v:197194$13655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194809$13378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197103$13564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405522,10 +409523,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194809$13378_Y + connect \Y $eq$libresoc.v:197103$13564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194854$13421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197148$13607 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405533,10 +409534,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194854$13421_Y + connect \Y $eq$libresoc.v:197148$13607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" - cell $eq $eq$libresoc.v:194868$13435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + cell $eq $eq$libresoc.v:197158$13617 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405544,10 +409545,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:194868$13435_Y + connect \Y $eq$libresoc.v:197158$13617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194889$13459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197179$13641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405555,10 +409556,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194889$13459_Y + connect \Y $eq$libresoc.v:197179$13641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - cell $eq $eq$libresoc.v:194900$13469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + cell $eq $eq$libresoc.v:197190$13651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405566,34 +409567,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:194900$13469_Y + connect \Y $eq$libresoc.v:197190$13651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:194873$13440 + cell $pos $extend$libresoc.v:197163$13622 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:194873$13440_Y + connect \Y $extend$libresoc.v:197163$13622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:194874$13442 + cell $pos $extend$libresoc.v:197164$13624 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:194874$13442_Y + connect \Y $extend$libresoc.v:197164$13624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:194885$13454 + cell $pos $extend$libresoc.v:197175$13636 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:194885$13454_Y + connect \Y $extend$libresoc.v:197175$13636_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:194792$13362 + cell $mul $mul$libresoc.v:197084$13546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405601,10 +409602,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:194792$13362_Y + connect \Y $mul$libresoc.v:197084$13546_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:194911$13479 + cell $mul $mul$libresoc.v:197201$13661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405612,10 +409613,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:194911$13479_Y + connect \Y $mul$libresoc.v:197201$13661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" - cell $ne $ne$libresoc.v:194861$13428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + cell $ne $ne$libresoc.v:197152$13611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405623,10 +409624,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:194861$13428_Y + connect \Y $ne$libresoc.v:197152$13611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - cell $ne $ne$libresoc.v:194870$13437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + cell $ne $ne$libresoc.v:197160$13619 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -405634,10 +409635,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:194870$13437_Y + connect \Y $ne$libresoc.v:197160$13619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $ne $ne$libresoc.v:194880$13449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $ne $ne$libresoc.v:197170$13631 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405645,426 +409646,410 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:194880$13449_Y + connect \Y $ne$libresoc.v:197170$13631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194794$13364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197086$13548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194794$13364_Y + connect \Y $not$libresoc.v:197086$13548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194795$13365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197087$13549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194795$13365_Y + connect \Y $not$libresoc.v:197087$13549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194797$13367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197089$13551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194797$13367_Y + connect \Y $not$libresoc.v:197089$13551_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194798$13368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197090$13552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194798$13368_Y + connect \Y $not$libresoc.v:197090$13552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194803$13372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197097$13558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194803$13372_Y + connect \Y $not$libresoc.v:197097$13558_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194804$13373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197098$13559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194804$13373_Y + connect \Y $not$libresoc.v:197098$13559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194806$13375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197100$13561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194806$13375_Y + connect \Y $not$libresoc.v:197100$13561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194807$13376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197101$13562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194807$13376_Y + connect \Y $not$libresoc.v:197101$13562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194811$13380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197105$13566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194811$13380_Y + connect \Y $not$libresoc.v:197105$13566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194812$13381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197106$13567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194812$13381_Y + connect \Y $not$libresoc.v:197106$13567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194817$13385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197111$13571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194817$13385_Y + connect \Y $not$libresoc.v:197111$13571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194818$13386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197112$13572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194818$13386_Y + connect \Y $not$libresoc.v:197112$13572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194820$13388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197114$13574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194820$13388_Y + connect \Y $not$libresoc.v:197114$13574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194821$13389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197115$13575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194821$13389_Y + connect \Y $not$libresoc.v:197115$13575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194823$13391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197117$13577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194823$13391_Y + connect \Y $not$libresoc.v:197117$13577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194824$13392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197118$13578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194824$13392_Y + connect \Y $not$libresoc.v:197118$13578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194826$13394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197120$13580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194826$13394_Y + connect \Y $not$libresoc.v:197120$13580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194827$13395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197121$13581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194827$13395_Y + connect \Y $not$libresoc.v:197121$13581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194829$13397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197123$13583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194829$13397_Y + connect \Y $not$libresoc.v:197123$13583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194830$13398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197124$13584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194830$13398_Y + connect \Y $not$libresoc.v:197124$13584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194832$13400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197126$13586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194832$13400_Y + connect \Y $not$libresoc.v:197126$13586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194833$13401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197127$13587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194833$13401_Y + connect \Y $not$libresoc.v:197127$13587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194837$13405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197131$13591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194837$13405_Y + connect \Y $not$libresoc.v:197131$13591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194838$13406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197132$13592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194838$13406_Y + connect \Y $not$libresoc.v:197132$13592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194840$13408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197134$13594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194840$13408_Y + connect \Y $not$libresoc.v:197134$13594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194841$13409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197135$13595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194841$13409_Y + connect \Y $not$libresoc.v:197135$13595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194846$13413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197140$13599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194846$13413_Y + connect \Y $not$libresoc.v:197140$13599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194847$13414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197141$13600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194847$13414_Y + connect \Y $not$libresoc.v:197141$13600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194849$13416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197143$13602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194849$13416_Y + connect \Y $not$libresoc.v:197143$13602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194850$13417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197144$13603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194850$13417_Y + connect \Y $not$libresoc.v:197144$13603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194856$13423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197150$13609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194856$13423_Y + connect \Y $not$libresoc.v:197150$13609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194857$13424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197151$13610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194857$13424_Y + connect \Y $not$libresoc.v:197151$13610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194858$13425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197153$13612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194858$13425_Y + connect \Y $not$libresoc.v:197153$13612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194860$13427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197155$13614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194860$13427_Y + connect \Y $not$libresoc.v:197155$13614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194862$13429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197156$13615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194862$13429_Y + connect \Y $not$libresoc.v:197156$13615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194865$13432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194865$13432_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194866$13433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194866$13433_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194871$13438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197161$13620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194871$13438_Y + connect \Y $not$libresoc.v:197161$13620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - cell $not $not$libresoc.v:194872$13439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + cell $not $not$libresoc.v:197162$13621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:194872$13439_Y + connect \Y $not$libresoc.v:197162$13621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:194881$13450 + cell $not $not$libresoc.v:197171$13632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:194881$13450_Y + connect \Y $not$libresoc.v:197171$13632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" - cell $not $not$libresoc.v:194883$13452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + cell $not $not$libresoc.v:197173$13634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:194883$13452_Y + connect \Y $not$libresoc.v:197173$13634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:562" - cell $not $not$libresoc.v:194884$13453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" + cell $not $not$libresoc.v:197174$13635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:194884$13453_Y + connect \Y $not$libresoc.v:197174$13635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194886$13456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197176$13638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194886$13456_Y + connect \Y $not$libresoc.v:197176$13638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194887$13457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197177$13639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194887$13457_Y + connect \Y $not$libresoc.v:197177$13639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194891$13461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197181$13643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194891$13461_Y + connect \Y $not$libresoc.v:197181$13643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194892$13462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197182$13644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194892$13462_Y + connect \Y $not$libresoc.v:197182$13644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194897$13466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197187$13648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194897$13466_Y + connect \Y $not$libresoc.v:197187$13648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:194898$13467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + cell $not $not$libresoc.v:197188$13649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194898$13467_Y + connect \Y $not$libresoc.v:197188$13649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194902$13471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197192$13653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:194902$13471_Y + connect \Y $not$libresoc.v:197192$13653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - cell $not $not$libresoc.v:194903$13472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + cell $not $not$libresoc.v:197193$13654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:194903$13472_Y + connect \Y $not$libresoc.v:197193$13654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $not $not$libresoc.v:194908$13476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + cell $not $not$libresoc.v:197198$13658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:194908$13476_Y + connect \Y $not$libresoc.v:197198$13658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $not $not$libresoc.v:194909$13477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" + cell $not $not$libresoc.v:197199$13659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:194909$13477_Y + connect \Y $not$libresoc.v:197199$13659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194800$13370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197092$13554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406072,10 +410057,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194800$13370_Y + connect \Y $or$libresoc.v:197092$13554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194802$13371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197094$13555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406083,10 +410068,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:194802$13371_Y + connect \Y $or$libresoc.v:197094$13555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194814$13383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197108$13569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406094,21 +410079,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194814$13383_Y + connect \Y $or$libresoc.v:197108$13569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194816$13384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197110$13570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$148 + connect \A \$154 connect \B \is_last - connect \Y $or$libresoc.v:194816$13384_Y + connect \Y $or$libresoc.v:197110$13570_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194843$13411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197137$13597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406116,21 +410101,21 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194843$13411_Y + connect \Y $or$libresoc.v:197137$13597_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194845$13412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197139$13598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$206 + connect \A \$212 connect \B \is_last - connect \Y $or$libresoc.v:194845$13412_Y + connect \Y $or$libresoc.v:197139$13598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $or $or$libresoc.v:194878$13447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $or $or$libresoc.v:197168$13629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406138,10 +410123,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:194878$13447_Y + connect \Y $or$libresoc.v:197168$13629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" - cell $or $or$libresoc.v:194879$13448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + cell $or $or$libresoc.v:197169$13630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406149,10 +410134,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:194879$13448_Y + connect \Y $or$libresoc.v:197169$13630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194894$13464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197184$13646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406160,10 +410145,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194894$13464_Y + connect \Y $or$libresoc.v:197184$13646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194896$13465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197186$13647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406171,10 +410156,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:194896$13465_Y + connect \Y $or$libresoc.v:197186$13647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $or $or$libresoc.v:194905$13474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + cell $or $or$libresoc.v:197195$13656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406182,10 +410167,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:194905$13474_Y + connect \Y $or$libresoc.v:197195$13656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" - cell $or $or$libresoc.v:194907$13475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + cell $or $or$libresoc.v:197197$13657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -406193,58 +410178,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:194907$13475_Y + connect \Y $or$libresoc.v:197197$13657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194869$13436 + cell $pos $pos$libresoc.v:197159$13618 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:194869$13436_Y + connect \Y $pos$libresoc.v:197159$13618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194873$13441 + cell $pos $pos$libresoc.v:197163$13623 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194873$13440_Y - connect \Y $pos$libresoc.v:194873$13441_Y + connect \A $extend$libresoc.v:197163$13622_Y + connect \Y $pos$libresoc.v:197163$13623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:194874$13443 + cell $pos $pos$libresoc.v:197164$13625 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194874$13442_Y - connect \Y $pos$libresoc.v:194874$13443_Y + connect \A $extend$libresoc.v:197164$13624_Y + connect \Y $pos$libresoc.v:197164$13625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:194885$13455 + cell $pos $pos$libresoc.v:197175$13637 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:194885$13454_Y - connect \Y $pos$libresoc.v:194885$13455_Y + connect \A $extend$libresoc.v:197175$13636_Y + connect \Y $pos$libresoc.v:197175$13637_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194836$13404 + cell $reduce_or $reduce_or$libresoc.v:197130$13590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$189 - connect \Y $reduce_or$libresoc.v:194836$13404_Y + connect \A \$195 + connect \Y $reduce_or$libresoc.v:197130$13590_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:194853$13420 + cell $reduce_or $reduce_or$libresoc.v:197147$13606 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$223 - connect \Y $reduce_or$libresoc.v:194853$13420_Y + connect \A \$229 + connect \Y $reduce_or$libresoc.v:197147$13606_Y end - attribute \src "libresoc.v:194793.18-194793.41" - cell $shr $shr$libresoc.v:194793$13363 + attribute \src "libresoc.v:197085.18-197085.41" + cell $shr $shr$libresoc.v:197085$13547 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406252,10 +410237,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:194793$13363_Y + connect \Y $shr$libresoc.v:197085$13547_Y end - attribute \src "libresoc.v:194912.18-194912.40" - cell $shr $shr$libresoc.v:194912$13480 + attribute \src "libresoc.v:197202.18-197202.40" + cell $shr $shr$libresoc.v:197202$13662 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406263,10 +410248,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:194912$13480_Y + connect \Y $shr$libresoc.v:197202$13662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:717" - cell $sub $sub$libresoc.v:194875$13444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + cell $sub $sub$libresoc.v:197165$13626 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -406274,10 +410259,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:194875$13444_Y + connect \Y $sub$libresoc.v:197165$13626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" - cell $sub $sub$libresoc.v:194876$13445 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + cell $sub $sub$libresoc.v:197167$13628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -406285,10 +410270,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:194876$13445_Y + connect \Y $sub$libresoc.v:197167$13628_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:195121.8-195219.4" + attribute \src "libresoc.v:197411.8-197509.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -406389,7 +410374,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:195220.7-195251.4" + attribute \src "libresoc.v:197510.7-197541.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -406423,7 +410408,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:195252.8-195319.4" + attribute \src "libresoc.v:197542.8-197609.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -406493,7 +410478,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:195320.8-195336.4" + attribute \src "libresoc.v:197610.8-197626.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -406512,7 +410497,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:195337.8-195669.4" + attribute \src "libresoc.v:197627.8-197955.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -406736,12 +410721,8 @@ module \ti connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe @@ -406847,7 +410828,7 @@ module \ti connect \wb_sram_en \jtag_wb_sram_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:195670.12-195682.4" + attribute \src "libresoc.v:197956.12-197968.4" cell \sram4k_0 \sram4k_0 connect \clk \clk connect \enable \sram4k_0_enable @@ -406862,7 +410843,7 @@ module \ti connect \sram4k_0_wb__we \sram4k_0_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195683.12-195695.4" + attribute \src "libresoc.v:197969.12-197981.4" cell \sram4k_1 \sram4k_1 connect \clk \clk connect \enable \sram4k_1_enable @@ -406877,7 +410858,7 @@ module \ti connect \sram4k_1_wb__we \sram4k_1_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195696.12-195708.4" + attribute \src "libresoc.v:197982.12-197994.4" cell \sram4k_2 \sram4k_2 connect \clk \clk connect \enable \sram4k_2_enable @@ -406892,7 +410873,7 @@ module \ti connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195709.12-195721.4" + attribute \src "libresoc.v:197995.12-198007.4" cell \sram4k_3 \sram4k_3 connect \clk \clk connect \enable \sram4k_3_enable @@ -406907,7 +410888,7 @@ module \ti connect \sram4k_3_wb__we \sram4k_3_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:195722.12-195736.4" + attribute \src "libresoc.v:198008.12-198022.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -406924,7 +410905,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:195737.12-195750.4" + attribute \src "libresoc.v:198023.12-198036.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -406939,1582 +410920,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:192354.7-192354.20" - process $proc$libresoc.v:192354$14061 + attribute \src "libresoc.v:194646.7-194646.20" + process $proc$libresoc.v:194646$14246 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192624.13-192624.33" - process $proc$libresoc.v:192624$14062 + attribute \src "libresoc.v:194914.13-194914.33" + process $proc$libresoc.v:194914$14247 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:192630.7-192630.35" - process $proc$libresoc.v:192630$14063 + attribute \src "libresoc.v:194920.7-194920.35" + process $proc$libresoc.v:194920$14248 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14064 1'0 + assign $0\core_bigendian_i$10[0:0]$14249 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14064 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14249 end - attribute \src "libresoc.v:192638.14-192638.55" - process $proc$libresoc.v:192638$14065 + attribute \src "libresoc.v:194928.14-194928.55" + process $proc$libresoc.v:194928$14250 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:192642.13-192642.41" - process $proc$libresoc.v:192642$14066 + attribute \src "libresoc.v:194932.13-194932.41" + process $proc$libresoc.v:194932$14251 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:192646.7-192646.37" - process $proc$libresoc.v:192646$14067 + attribute \src "libresoc.v:194936.7-194936.37" + process $proc$libresoc.v:194936$14252 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:192650.13-192650.41" - process $proc$libresoc.v:192650$14068 + attribute \src "libresoc.v:194940.13-194940.41" + process $proc$libresoc.v:194940$14253 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:192654.7-192654.42" - process $proc$libresoc.v:192654$14069 + attribute \src "libresoc.v:194944.7-194944.42" + process $proc$libresoc.v:194944$14254 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14070 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14255 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14070 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14255 end - attribute \src "libresoc.v:192656.7-192656.44" - process $proc$libresoc.v:192656$14071 + attribute \src "libresoc.v:194946.7-194946.44" + process $proc$libresoc.v:194946$14256 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14072 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14257 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14072 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14257 end - attribute \src "libresoc.v:192660.7-192660.44" - process $proc$libresoc.v:192660$14073 + attribute \src "libresoc.v:194950.7-194950.44" + process $proc$libresoc.v:194950$14258 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14074 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14259 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14074 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14259 end - attribute \src "libresoc.v:192664.7-192664.44" - process $proc$libresoc.v:192664$14075 + attribute \src "libresoc.v:194954.7-194954.44" + process $proc$libresoc.v:194954$14260 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14076 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14261 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14076 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14261 end - attribute \src "libresoc.v:192668.7-192668.44" - process $proc$libresoc.v:192668$14077 + attribute \src "libresoc.v:194958.7-194958.44" + process $proc$libresoc.v:194958$14262 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14078 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14263 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14078 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14263 end - attribute \src "libresoc.v:192672.7-192672.44" - process $proc$libresoc.v:192672$14079 + attribute \src "libresoc.v:194962.7-194962.44" + process $proc$libresoc.v:194962$14264 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14080 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14265 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14080 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14265 end - attribute \src "libresoc.v:192676.7-192676.44" - process $proc$libresoc.v:192676$14081 + attribute \src "libresoc.v:194966.7-194966.44" + process $proc$libresoc.v:194966$14266 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14082 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14267 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14082 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14267 end - attribute \src "libresoc.v:192680.7-192680.44" - process $proc$libresoc.v:192680$14083 + attribute \src "libresoc.v:194970.7-194970.44" + process $proc$libresoc.v:194970$14268 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14084 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14269 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14084 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14269 end - attribute \src "libresoc.v:192701.14-192701.47" - process $proc$libresoc.v:192701$14085 + attribute \src "libresoc.v:194991.14-194991.47" + process $proc$libresoc.v:194991$14270 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:192709.13-192709.46" - process $proc$libresoc.v:192709$14086 + attribute \src "libresoc.v:194999.13-194999.46" + process $proc$libresoc.v:194999$14271 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:192713.14-192713.41" - process $proc$libresoc.v:192713$14087 + attribute \src "libresoc.v:195003.14-195003.41" + process $proc$libresoc.v:195003$14272 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:192792.13-192792.45" - process $proc$libresoc.v:192792$14088 + attribute \src "libresoc.v:195082.13-195082.45" + process $proc$libresoc.v:195082$14273 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:192796.7-192796.37" - process $proc$libresoc.v:192796$14089 + attribute \src "libresoc.v:195086.7-195086.37" + process $proc$libresoc.v:195086$14274 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:192800.14-192800.55" - process $proc$libresoc.v:192800$14090 + attribute \src "libresoc.v:195090.14-195090.55" + process $proc$libresoc.v:195090$14275 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:192804.7-192804.31" - process $proc$libresoc.v:192804$14091 + attribute \src "libresoc.v:195094.7-195094.31" + process $proc$libresoc.v:195094$14276 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:192808.7-192808.34" - process $proc$libresoc.v:192808$14092 + attribute \src "libresoc.v:195098.7-195098.34" + process $proc$libresoc.v:195098$14277 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:192812.7-192812.31" - process $proc$libresoc.v:192812$14093 + attribute \src "libresoc.v:195102.7-195102.31" + process $proc$libresoc.v:195102$14278 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:192816.7-192816.34" - process $proc$libresoc.v:192816$14094 + attribute \src "libresoc.v:195106.7-195106.34" + process $proc$libresoc.v:195106$14279 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:192820.14-192820.48" - process $proc$libresoc.v:192820$14095 + attribute \src "libresoc.v:195110.14-195110.48" + process $proc$libresoc.v:195110$14280 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:192824.13-192824.44" - process $proc$libresoc.v:192824$14096 + attribute \src "libresoc.v:195114.13-195114.44" + process $proc$libresoc.v:195114$14281 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:192828.13-192828.37" - process $proc$libresoc.v:192828$14097 + attribute \src "libresoc.v:195118.13-195118.37" + process $proc$libresoc.v:195118$14282 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:192832.7-192832.33" - process $proc$libresoc.v:192832$14098 + attribute \src "libresoc.v:195122.7-195122.33" + process $proc$libresoc.v:195122$14283 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:192836.13-192836.37" - process $proc$libresoc.v:192836$14099 + attribute \src "libresoc.v:195126.13-195126.37" + process $proc$libresoc.v:195126$14284 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:192838.13-192838.41" - process $proc$libresoc.v:192838$14100 + attribute \src "libresoc.v:195128.13-195128.41" + process $proc$libresoc.v:195128$14285 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14101 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14286 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14101 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14286 end - attribute \src "libresoc.v:192844.7-192844.33" - process $proc$libresoc.v:192844$14102 + attribute \src "libresoc.v:195134.7-195134.33" + process $proc$libresoc.v:195134$14287 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:192846.7-192846.37" - process $proc$libresoc.v:192846$14103 + attribute \src "libresoc.v:195136.7-195136.37" + process $proc$libresoc.v:195136$14288 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14104 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14289 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14104 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14289 end - attribute \src "libresoc.v:192852.13-192852.37" - process $proc$libresoc.v:192852$14105 + attribute \src "libresoc.v:195142.13-195142.37" + process $proc$libresoc.v:195142$14290 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:192856.7-192856.32" - process $proc$libresoc.v:192856$14106 + attribute \src "libresoc.v:195146.7-195146.32" + process $proc$libresoc.v:195146$14291 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:192860.13-192860.38" - process $proc$libresoc.v:192860$14107 + attribute \src "libresoc.v:195150.13-195150.38" + process $proc$libresoc.v:195150$14292 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:192864.13-192864.33" - process $proc$libresoc.v:192864$14108 + attribute \src "libresoc.v:195154.13-195154.33" + process $proc$libresoc.v:195154$14293 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:192868.13-192868.35" - process $proc$libresoc.v:192868$14109 + attribute \src "libresoc.v:195158.13-195158.35" + process $proc$libresoc.v:195158$14294 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:192872.7-192872.32" - process $proc$libresoc.v:192872$14110 + attribute \src "libresoc.v:195162.7-195162.32" + process $proc$libresoc.v:195162$14295 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:192876.13-192876.35" - process $proc$libresoc.v:192876$14111 + attribute \src "libresoc.v:195166.13-195166.35" + process $proc$libresoc.v:195166$14296 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:192880.7-192880.32" - process $proc$libresoc.v:192880$14112 + attribute \src "libresoc.v:195170.7-195170.32" + process $proc$libresoc.v:195170$14297 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:192884.13-192884.36" - process $proc$libresoc.v:192884$14113 + attribute \src "libresoc.v:195174.13-195174.36" + process $proc$libresoc.v:195174$14298 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:192888.13-192888.36" - process $proc$libresoc.v:192888$14114 + attribute \src "libresoc.v:195178.13-195178.36" + process $proc$libresoc.v:195178$14299 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:192892.7-192892.26" - process $proc$libresoc.v:192892$14115 + attribute \src "libresoc.v:195182.7-195182.26" + process $proc$libresoc.v:195182$14300 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:192896.13-192896.36" - process $proc$libresoc.v:192896$14116 + attribute \src "libresoc.v:195186.13-195186.36" + process $proc$libresoc.v:195186$14301 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:192900.14-192900.49" - process $proc$libresoc.v:192900$14117 + attribute \src "libresoc.v:195190.14-195190.49" + process $proc$libresoc.v:195190$14302 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:192904.13-192904.35" - process $proc$libresoc.v:192904$14118 + attribute \src "libresoc.v:195194.13-195194.35" + process $proc$libresoc.v:195194$14303 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:192908.7-192908.31" - process $proc$libresoc.v:192908$14119 + attribute \src "libresoc.v:195198.7-195198.31" + process $proc$libresoc.v:195198$14304 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:192912.13-192912.35" - process $proc$libresoc.v:192912$14120 + attribute \src "libresoc.v:195202.13-195202.35" + process $proc$libresoc.v:195202$14305 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:192916.7-192916.31" - process $proc$libresoc.v:192916$14121 + attribute \src "libresoc.v:195206.7-195206.31" + process $proc$libresoc.v:195206$14306 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:192920.13-192920.35" - process $proc$libresoc.v:192920$14122 + attribute \src "libresoc.v:195210.13-195210.35" + process $proc$libresoc.v:195210$14307 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:192924.7-192924.31" - process $proc$libresoc.v:192924$14123 + attribute \src "libresoc.v:195214.7-195214.31" + process $proc$libresoc.v:195214$14308 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:192928.13-192928.35" - process $proc$libresoc.v:192928$14124 + attribute \src "libresoc.v:195218.13-195218.35" + process $proc$libresoc.v:195218$14309 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:193046.13-193046.37" - process $proc$libresoc.v:193046$14125 + attribute \src "libresoc.v:195336.13-195336.37" + process $proc$libresoc.v:195336$14310 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:193050.7-193050.31" - process $proc$libresoc.v:193050$14126 + attribute \src "libresoc.v:195340.7-195340.31" + process $proc$libresoc.v:195340$14311 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:193168.13-193168.37" - process $proc$libresoc.v:193168$14127 + attribute \src "libresoc.v:195458.13-195458.37" + process $proc$libresoc.v:195458$14312 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:193172.13-193172.38" - process $proc$libresoc.v:193172$14128 + attribute \src "libresoc.v:195462.13-195462.38" + process $proc$libresoc.v:195462$14313 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:193176.13-193176.35" - process $proc$libresoc.v:193176$14129 + attribute \src "libresoc.v:195466.13-195466.35" + process $proc$libresoc.v:195466$14314 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:193180.13-193180.36" - process $proc$libresoc.v:193180$14130 + attribute \src "libresoc.v:195470.13-195470.36" + process $proc$libresoc.v:195470$14315 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:193186.13-193186.33" - process $proc$libresoc.v:193186$14131 + attribute \src "libresoc.v:195476.13-195476.33" + process $proc$libresoc.v:195476$14316 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:193190.13-193190.36" - process $proc$libresoc.v:193190$14132 + attribute \src "libresoc.v:195480.13-195480.36" + process $proc$libresoc.v:195480$14317 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:193198.7-193198.28" - process $proc$libresoc.v:193198$14133 + attribute \src "libresoc.v:195488.7-195488.28" + process $proc$libresoc.v:195488$14318 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:193214.14-193214.45" - process $proc$libresoc.v:193214$14134 + attribute \src "libresoc.v:195504.14-195504.45" + process $proc$libresoc.v:195504$14319 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:193224.7-193224.24" - process $proc$libresoc.v:193224$14135 + attribute \src "libresoc.v:195514.7-195514.24" + process $proc$libresoc.v:195514$14320 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:193228.7-193228.23" - process $proc$libresoc.v:193228$14136 + attribute \src "libresoc.v:195518.7-195518.23" + process $proc$libresoc.v:195518$14321 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:193232.7-193232.28" - process $proc$libresoc.v:193232$14137 + attribute \src "libresoc.v:195522.7-195522.28" + process $proc$libresoc.v:195522$14322 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:193236.7-193236.28" - process $proc$libresoc.v:193236$14138 + attribute \src "libresoc.v:195526.7-195526.28" + process $proc$libresoc.v:195526$14323 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:193264.14-193264.45" - process $proc$libresoc.v:193264$14139 + attribute \src "libresoc.v:195554.14-195554.45" + process $proc$libresoc.v:195554$14324 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:193272.14-193272.37" - process $proc$libresoc.v:193272$14140 + attribute \src "libresoc.v:195562.14-195562.37" + process $proc$libresoc.v:195562$14325 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:193276.7-193276.26" - process $proc$libresoc.v:193276$14141 + attribute \src "libresoc.v:195566.7-195566.26" + process $proc$libresoc.v:195566$14326 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:193280.7-193280.26" - process $proc$libresoc.v:193280$14142 + attribute \src "libresoc.v:195570.7-195570.26" + process $proc$libresoc.v:195570$14327 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:193292.7-193292.26" - process $proc$libresoc.v:193292$14143 + attribute \src "libresoc.v:195582.7-195582.26" + process $proc$libresoc.v:195582$14328 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:193302.7-193302.26" - process $proc$libresoc.v:193302$14144 + attribute \src "libresoc.v:195592.7-195592.26" + process $proc$libresoc.v:195592$14329 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:193308.7-193308.30" - process $proc$libresoc.v:193308$14145 + attribute \src "libresoc.v:195598.7-195598.30" + process $proc$libresoc.v:195598$14330 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:193314.13-193314.36" - process $proc$libresoc.v:193314$14146 + attribute \src "libresoc.v:195604.13-195604.36" + process $proc$libresoc.v:195604$14331 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:193318.13-193318.34" - process $proc$libresoc.v:193318$14147 + attribute \src "libresoc.v:195608.13-195608.34" + process $proc$libresoc.v:195608$14332 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:193322.13-193322.36" - process $proc$libresoc.v:193322$14148 + attribute \src "libresoc.v:195612.13-195612.36" + process $proc$libresoc.v:195612$14333 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:193326.13-193326.33" - process $proc$libresoc.v:193326$14149 + attribute \src "libresoc.v:195616.13-195616.33" + process $proc$libresoc.v:195616$14334 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:193330.13-193330.34" - process $proc$libresoc.v:193330$14150 + attribute \src "libresoc.v:195620.13-195620.34" + process $proc$libresoc.v:195620$14335 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:193334.13-193334.31" - process $proc$libresoc.v:193334$14151 + attribute \src "libresoc.v:195624.13-195624.31" + process $proc$libresoc.v:195624$14336 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:193338.7-193338.24" - process $proc$libresoc.v:193338$14152 + attribute \src "libresoc.v:195628.7-195628.24" + process $proc$libresoc.v:195628$14337 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:193342.7-193342.25" - process $proc$libresoc.v:193342$14153 + attribute \src "libresoc.v:195632.7-195632.25" + process $proc$libresoc.v:195632$14338 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:193346.7-193346.25" - process $proc$libresoc.v:193346$14154 + attribute \src "libresoc.v:195636.7-195636.25" + process $proc$libresoc.v:195636$14339 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:193394.13-193394.34" - process $proc$libresoc.v:193394$14155 + attribute \src "libresoc.v:195684.13-195684.34" + process $proc$libresoc.v:195684$14340 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:193398.14-193398.48" - process $proc$libresoc.v:193398$14156 + attribute \src "libresoc.v:195688.14-195688.48" + process $proc$libresoc.v:195688$14341 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:193404.7-193404.27" - process $proc$libresoc.v:193404$14157 + attribute \src "libresoc.v:195694.7-195694.27" + process $proc$libresoc.v:195694$14342 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:193408.7-193408.26" - process $proc$libresoc.v:193408$14158 + attribute \src "libresoc.v:195698.7-195698.26" + process $proc$libresoc.v:195698$14343 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:193462.14-193462.49" - process $proc$libresoc.v:193462$14159 + attribute \src "libresoc.v:195752.14-195752.49" + process $proc$libresoc.v:195752$14344 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:193466.7-193466.27" - process $proc$libresoc.v:193466$14160 + attribute \src "libresoc.v:195756.7-195756.27" + process $proc$libresoc.v:195756$14345 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:193470.14-193470.49" - process $proc$libresoc.v:193470$14161 + attribute \src "libresoc.v:195760.14-195760.49" + process $proc$libresoc.v:195760$14346 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:193474.14-193474.48" - process $proc$libresoc.v:193474$14162 + attribute \src "libresoc.v:195764.14-195764.48" + process $proc$libresoc.v:195764$14347 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:193626.14-193626.40" - process $proc$libresoc.v:193626$14163 + attribute \src "libresoc.v:195916.14-195916.40" + process $proc$libresoc.v:195916$14348 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:193896.13-193896.25" - process $proc$libresoc.v:193896$14164 + attribute \src "libresoc.v:196186.13-196186.25" + process $proc$libresoc.v:196186$14349 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:193912.7-193912.28" - process $proc$libresoc.v:193912$14165 + attribute \src "libresoc.v:196202.7-196202.28" + process $proc$libresoc.v:196202$14350 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:193924.13-193924.35" - process $proc$libresoc.v:193924$14166 + attribute \src "libresoc.v:196214.13-196214.35" + process $proc$libresoc.v:196214$14351 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:193936.13-193936.29" - process $proc$libresoc.v:193936$14167 + attribute \src "libresoc.v:196226.13-196226.29" + process $proc$libresoc.v:196226$14352 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:194196.13-194196.35" - process $proc$libresoc.v:194196$14168 + attribute \src "libresoc.v:196486.13-196486.35" + process $proc$libresoc.v:196486$14353 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:194200.7-194200.30" - process $proc$libresoc.v:194200$14169 + attribute \src "libresoc.v:196490.7-196490.30" + process $proc$libresoc.v:196490$14354 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:194208.14-194208.52" - process $proc$libresoc.v:194208$14170 + attribute \src "libresoc.v:196498.14-196498.52" + process $proc$libresoc.v:196498$14355 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:194266.7-194266.22" - process $proc$libresoc.v:194266$14171 + attribute \src "libresoc.v:196556.7-196556.22" + process $proc$libresoc.v:196556$14356 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:194304.14-194304.40" - process $proc$libresoc.v:194304$14172 + attribute \src "libresoc.v:196596.14-196596.40" + process $proc$libresoc.v:196596$14357 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:194310.7-194310.24" - process $proc$libresoc.v:194310$14173 + attribute \src "libresoc.v:196602.7-196602.24" + process $proc$libresoc.v:196602$14358 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:194320.7-194320.25" - process $proc$libresoc.v:194320$14174 + attribute \src "libresoc.v:196612.7-196612.25" + process $proc$libresoc.v:196612$14359 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:194764.7-194764.24" - process $proc$libresoc.v:194764$14175 + attribute \src "libresoc.v:197056.7-197056.24" + process $proc$libresoc.v:197056$14360 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:194774.7-194774.30" - process $proc$libresoc.v:194774$14176 + attribute \src "libresoc.v:197066.7-197066.30" + process $proc$libresoc.v:197066$14361 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:194913.3-194914.41" - process $proc$libresoc.v:194913$13481 + attribute \src "libresoc.v:197203.3-197204.41" + process $proc$libresoc.v:197203$13663 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:194915.3-194916.41" - process $proc$libresoc.v:194915$13482 + attribute \src "libresoc.v:197205.3-197206.41" + process $proc$libresoc.v:197205$13664 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:194917.3-194918.49" - process $proc$libresoc.v:194917$13483 + attribute \src "libresoc.v:197207.3-197208.49" + process $proc$libresoc.v:197207$13665 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:194919.3-194920.39" - process $proc$libresoc.v:194919$13484 + attribute \src "libresoc.v:197209.3-197210.39" + process $proc$libresoc.v:197209$13666 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:194921.3-194922.41" - process $proc$libresoc.v:194921$13485 + attribute \src "libresoc.v:197211.3-197212.41" + process $proc$libresoc.v:197211$13667 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:194923.3-194924.43" - process $proc$libresoc.v:194923$13486 + attribute \src "libresoc.v:197213.3-197214.43" + process $proc$libresoc.v:197213$13668 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:194925.3-194926.45" - process $proc$libresoc.v:194925$13487 + attribute \src "libresoc.v:197215.3-197216.45" + process $proc$libresoc.v:197215$13669 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:194927.3-194928.33" - process $proc$libresoc.v:194927$13488 + attribute \src "libresoc.v:197217.3-197218.33" + process $proc$libresoc.v:197217$13670 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:194929.3-194930.35" - process $proc$libresoc.v:194929$13489 + attribute \src "libresoc.v:197219.3-197220.35" + process $proc$libresoc.v:197219$13671 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:194931.3-194932.33" - process $proc$libresoc.v:194931$13490 + attribute \src "libresoc.v:197221.3-197222.33" + process $proc$libresoc.v:197221$13672 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:194933.3-194934.49" - process $proc$libresoc.v:194933$13491 + attribute \src "libresoc.v:197223.3-197224.49" + process $proc$libresoc.v:197223$13673 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:194935.3-194936.47" - process $proc$libresoc.v:194935$13492 + attribute \src "libresoc.v:197225.3-197226.47" + process $proc$libresoc.v:197225$13674 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:194937.3-194938.51" - process $proc$libresoc.v:194937$13493 + attribute \src "libresoc.v:197227.3-197228.51" + process $proc$libresoc.v:197227$13675 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:194939.3-194940.51" - process $proc$libresoc.v:194939$13494 + attribute \src "libresoc.v:197229.3-197230.51" + process $proc$libresoc.v:197229$13676 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:194941.3-194942.41" - process $proc$libresoc.v:194941$13495 + attribute \src "libresoc.v:197231.3-197232.41" + process $proc$libresoc.v:197231$13677 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:194943.3-194944.47" - process $proc$libresoc.v:194943$13496 + attribute \src "libresoc.v:197233.3-197234.47" + process $proc$libresoc.v:197233$13678 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:194945.3-194946.35" - process $proc$libresoc.v:194945$13497 + attribute \src "libresoc.v:197235.3-197236.35" + process $proc$libresoc.v:197235$13679 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:194947.3-194948.41" - process $proc$libresoc.v:194947$13498 + attribute \src "libresoc.v:197237.3-197238.41" + process $proc$libresoc.v:197237$13680 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:194949.3-194950.45" - process $proc$libresoc.v:194949$13499 + attribute \src "libresoc.v:197239.3-197240.45" + process $proc$libresoc.v:197239$13681 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:194951.3-194952.41" - process $proc$libresoc.v:194951$13500 + attribute \src "libresoc.v:197241.3-197242.41" + process $proc$libresoc.v:197241$13682 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:194953.3-194954.41" - process $proc$libresoc.v:194953$13501 + attribute \src "libresoc.v:197243.3-197244.41" + process $proc$libresoc.v:197243$13683 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:194955.3-194956.37" - process $proc$libresoc.v:194955$13502 + attribute \src "libresoc.v:197245.3-197246.37" + process $proc$libresoc.v:197245$13684 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:194957.3-194958.45" - process $proc$libresoc.v:194957$13503 + attribute \src "libresoc.v:197247.3-197248.45" + process $proc$libresoc.v:197247$13685 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:194959.3-194960.51" - process $proc$libresoc.v:194959$13504 + attribute \src "libresoc.v:197249.3-197250.51" + process $proc$libresoc.v:197249$13686 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:194961.3-194962.45" - process $proc$libresoc.v:194961$13505 + attribute \src "libresoc.v:197251.3-197252.45" + process $proc$libresoc.v:197251$13687 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:194963.3-194964.51" - process $proc$libresoc.v:194963$13506 + attribute \src "libresoc.v:197253.3-197254.51" + process $proc$libresoc.v:197253$13688 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:194965.3-194966.45" - process $proc$libresoc.v:194965$13507 + attribute \src "libresoc.v:197255.3-197256.45" + process $proc$libresoc.v:197255$13689 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:194967.3-194968.39" - process $proc$libresoc.v:194967$13508 + attribute \src "libresoc.v:197257.3-197258.39" + process $proc$libresoc.v:197257$13690 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:194969.3-194970.51" - process $proc$libresoc.v:194969$13509 + attribute \src "libresoc.v:197259.3-197260.51" + process $proc$libresoc.v:197259$13691 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:194971.3-194972.45" - process $proc$libresoc.v:194971$13510 + attribute \src "libresoc.v:197261.3-197262.45" + process $proc$libresoc.v:197261$13692 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:194973.3-194974.41" - process $proc$libresoc.v:194973$13511 + attribute \src "libresoc.v:197263.3-197264.41" + process $proc$libresoc.v:197263$13693 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:194975.3-194976.45" - process $proc$libresoc.v:194975$13512 + attribute \src "libresoc.v:197265.3-197266.45" + process $proc$libresoc.v:197265$13694 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:194977.3-194978.51" - process $proc$libresoc.v:194977$13513 + attribute \src "libresoc.v:197267.3-197268.51" + process $proc$libresoc.v:197267$13695 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:194979.3-194980.49" - process $proc$libresoc.v:194979$13514 + attribute \src "libresoc.v:197269.3-197270.49" + process $proc$libresoc.v:197269$13696 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:194981.3-194982.41" - process $proc$libresoc.v:194981$13515 + attribute \src "libresoc.v:197271.3-197272.41" + process $proc$libresoc.v:197271$13697 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:194983.3-194984.47" - process $proc$libresoc.v:194983$13516 + attribute \src "libresoc.v:197273.3-197274.47" + process $proc$libresoc.v:197273$13698 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:194985.3-194986.53" - process $proc$libresoc.v:194985$13517 + attribute \src "libresoc.v:197275.3-197276.53" + process $proc$libresoc.v:197275$13699 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:194987.3-194988.47" - process $proc$libresoc.v:194987$13518 + attribute \src "libresoc.v:197277.3-197278.47" + process $proc$libresoc.v:197277$13700 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:194989.3-194990.37" - process $proc$libresoc.v:194989$13519 + attribute \src "libresoc.v:197279.3-197280.37" + process $proc$libresoc.v:197279$13701 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:194991.3-194992.53" - process $proc$libresoc.v:194991$13520 + attribute \src "libresoc.v:197281.3-197282.53" + process $proc$libresoc.v:197281$13702 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:194993.3-194994.49" - process $proc$libresoc.v:194993$13521 + attribute \src "libresoc.v:197283.3-197284.49" + process $proc$libresoc.v:197283$13703 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:194995.3-194996.45" - process $proc$libresoc.v:194995$13522 + attribute \src "libresoc.v:197285.3-197286.45" + process $proc$libresoc.v:197285$13704 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:194997.3-194998.49" - process $proc$libresoc.v:194997$13523 + attribute \src "libresoc.v:197287.3-197288.49" + process $proc$libresoc.v:197287$13705 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:194999.3-195000.45" - process $proc$libresoc.v:194999$13524 + attribute \src "libresoc.v:197289.3-197290.45" + process $proc$libresoc.v:197289$13706 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:195001.3-195002.49" - process $proc$libresoc.v:195001$13525 + attribute \src "libresoc.v:197291.3-197292.49" + process $proc$libresoc.v:197291$13707 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:195003.3-195004.55" - process $proc$libresoc.v:195003$13526 + attribute \src "libresoc.v:197293.3-197294.55" + process $proc$libresoc.v:197293$13708 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:195005.3-195006.49" - process $proc$libresoc.v:195005$13527 + attribute \src "libresoc.v:197295.3-197296.49" + process $proc$libresoc.v:197295$13709 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:195007.3-195008.55" - process $proc$libresoc.v:195007$13528 + attribute \src "libresoc.v:197297.3-197298.55" + process $proc$libresoc.v:197297$13710 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:195009.3-195010.55" - process $proc$libresoc.v:195009$13529 + attribute \src "libresoc.v:197299.3-197300.55" + process $proc$libresoc.v:197299$13711 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13530 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13712 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13530 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13712 end - attribute \src "libresoc.v:195011.3-195012.39" - process $proc$libresoc.v:195011$13531 + attribute \src "libresoc.v:197301.3-197302.39" + process $proc$libresoc.v:197301$13713 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:195013.3-195014.61" - process $proc$libresoc.v:195013$13532 + attribute \src "libresoc.v:197303.3-197304.61" + process $proc$libresoc.v:197303$13714 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13533 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13715 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13533 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13715 end - attribute \src "libresoc.v:195015.3-195016.49" - process $proc$libresoc.v:195015$13534 + attribute \src "libresoc.v:197305.3-197306.49" + process $proc$libresoc.v:197305$13716 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:195017.3-195018.45" - process $proc$libresoc.v:195017$13535 + attribute \src "libresoc.v:197307.3-197308.45" + process $proc$libresoc.v:197307$13717 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:195019.3-195020.53" - process $proc$libresoc.v:195019$13536 + attribute \src "libresoc.v:197309.3-197310.53" + process $proc$libresoc.v:197309$13718 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:195021.3-195022.53" - process $proc$libresoc.v:195021$13537 + attribute \src "libresoc.v:197311.3-197312.53" + process $proc$libresoc.v:197311$13719 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:195023.3-195024.55" - process $proc$libresoc.v:195023$13538 + attribute \src "libresoc.v:197313.3-197314.55" + process $proc$libresoc.v:197313$13720 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:195025.3-195026.65" - process $proc$libresoc.v:195025$13539 + attribute \src "libresoc.v:197315.3-197316.65" + process $proc$libresoc.v:197315$13721 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:195027.3-195028.61" - process $proc$libresoc.v:195027$13540 + attribute \src "libresoc.v:197317.3-197318.61" + process $proc$libresoc.v:197317$13722 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:195029.3-195030.41" - process $proc$libresoc.v:195029$13541 + attribute \src "libresoc.v:197319.3-197320.41" + process $proc$libresoc.v:197319$13723 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:195031.3-195032.51" - process $proc$libresoc.v:195031$13542 + attribute \src "libresoc.v:197321.3-197322.51" + process $proc$libresoc.v:197321$13724 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:195033.3-195034.45" - process $proc$libresoc.v:195033$13543 + attribute \src "libresoc.v:197323.3-197324.45" + process $proc$libresoc.v:197323$13725 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:195035.3-195036.57" - process $proc$libresoc.v:195035$13544 + attribute \src "libresoc.v:197325.3-197326.57" + process $proc$libresoc.v:197325$13726 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:195037.3-195038.51" - process $proc$libresoc.v:195037$13545 + attribute \src "libresoc.v:197327.3-197328.51" + process $proc$libresoc.v:197327$13727 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:195039.3-195040.57" - process $proc$libresoc.v:195039$13546 + attribute \src "libresoc.v:197329.3-197330.57" + process $proc$libresoc.v:197329$13728 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:195041.3-195042.69" - process $proc$libresoc.v:195041$13547 + attribute \src "libresoc.v:197331.3-197332.69" + process $proc$libresoc.v:197331$13729 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:195043.3-195044.63" - process $proc$libresoc.v:195043$13548 + attribute \src "libresoc.v:197333.3-197334.63" + process $proc$libresoc.v:197333$13730 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:195045.3-195046.71" - process $proc$libresoc.v:195045$13549 + attribute \src "libresoc.v:197335.3-197336.71" + process $proc$libresoc.v:197335$13731 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13550 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13732 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13550 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13732 end - attribute \src "libresoc.v:195047.3-195048.75" - process $proc$libresoc.v:195047$13551 + attribute \src "libresoc.v:197337.3-197338.75" + process $proc$libresoc.v:197337$13733 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13552 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13734 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13552 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13734 end - attribute \src "libresoc.v:195049.3-195050.75" - process $proc$libresoc.v:195049$13553 + attribute \src "libresoc.v:197339.3-197340.75" + process $proc$libresoc.v:197339$13735 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13554 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13736 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13554 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13736 end - attribute \src "libresoc.v:195051.3-195052.75" - process $proc$libresoc.v:195051$13555 + attribute \src "libresoc.v:197341.3-197342.75" + process $proc$libresoc.v:197341$13737 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13556 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13738 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13556 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13738 end - attribute \src "libresoc.v:195053.3-195054.75" - process $proc$libresoc.v:195053$13557 + attribute \src "libresoc.v:197343.3-197344.75" + process $proc$libresoc.v:197343$13739 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13558 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13740 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13558 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13740 end - attribute \src "libresoc.v:195055.3-195056.41" - process $proc$libresoc.v:195055$13559 + attribute \src "libresoc.v:197345.3-197346.41" + process $proc$libresoc.v:197345$13741 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:195057.3-195058.75" - process $proc$libresoc.v:195057$13560 + attribute \src "libresoc.v:197347.3-197348.75" + process $proc$libresoc.v:197347$13742 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13561 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13743 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13561 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13743 end - attribute \src "libresoc.v:195059.3-195060.75" - process $proc$libresoc.v:195059$13562 + attribute \src "libresoc.v:197349.3-197350.75" + process $proc$libresoc.v:197349$13744 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13563 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13745 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13563 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13745 end - attribute \src "libresoc.v:195061.3-195062.75" - process $proc$libresoc.v:195061$13564 + attribute \src "libresoc.v:197351.3-197352.75" + process $proc$libresoc.v:197351$13746 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13565 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13747 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13565 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13747 end - attribute \src "libresoc.v:195063.3-195064.63" - process $proc$libresoc.v:195063$13566 + attribute \src "libresoc.v:197353.3-197354.63" + process $proc$libresoc.v:197353$13748 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:195065.3-195066.57" - process $proc$libresoc.v:195065$13567 + attribute \src "libresoc.v:197355.3-197356.57" + process $proc$libresoc.v:197355$13749 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:195067.3-195068.63" - process $proc$libresoc.v:195067$13568 + attribute \src "libresoc.v:197357.3-197358.63" + process $proc$libresoc.v:197357$13750 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:195069.3-195070.57" - process $proc$libresoc.v:195069$13569 + attribute \src "libresoc.v:197359.3-197360.57" + process $proc$libresoc.v:197359$13751 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:195071.3-195072.53" - process $proc$libresoc.v:195071$13570 + attribute \src "libresoc.v:197361.3-197362.53" + process $proc$libresoc.v:197361$13752 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:195073.3-195074.63" - process $proc$libresoc.v:195073$13571 + attribute \src "libresoc.v:197363.3-197364.63" + process $proc$libresoc.v:197363$13753 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:195075.3-195076.37" - process $proc$libresoc.v:195075$13572 + attribute \src "libresoc.v:197365.3-197366.37" + process $proc$libresoc.v:197365$13754 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:195077.3-195078.57" - process $proc$libresoc.v:195077$13573 + attribute \src "libresoc.v:197367.3-197368.57" + process $proc$libresoc.v:197367$13755 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13574 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13756 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13574 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13756 end - attribute \src "libresoc.v:195079.3-195080.37" - process $proc$libresoc.v:195079$13575 + attribute \src "libresoc.v:197369.3-197370.37" + process $proc$libresoc.v:197369$13757 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:195081.3-195082.47" - process $proc$libresoc.v:195081$13576 + attribute \src "libresoc.v:197371.3-197372.47" + process $proc$libresoc.v:197371$13758 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:195083.3-195084.53" - process $proc$libresoc.v:195083$13577 + attribute \src "libresoc.v:197373.3-197374.53" + process $proc$libresoc.v:197373$13759 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:195085.3-195086.23" - process $proc$libresoc.v:195085$13578 + attribute \src "libresoc.v:197375.3-197376.23" + process $proc$libresoc.v:197375$13760 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:195087.3-195088.41" - process $proc$libresoc.v:195087$13579 + attribute \src "libresoc.v:197377.3-197378.41" + process $proc$libresoc.v:197377$13761 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:195089.3-195090.47" - process $proc$libresoc.v:195089$13580 + attribute \src "libresoc.v:197379.3-197380.47" + process $proc$libresoc.v:197379$13762 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:195091.3-195092.33" - process $proc$libresoc.v:195091$13581 + attribute \src "libresoc.v:197381.3-197382.33" + process $proc$libresoc.v:197381$13763 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:195093.3-195094.45" - process $proc$libresoc.v:195093$13582 + attribute \src "libresoc.v:197383.3-197384.45" + process $proc$libresoc.v:197383$13764 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:195095.3-195096.43" - process $proc$libresoc.v:195095$13583 + attribute \src "libresoc.v:197385.3-197386.43" + process $proc$libresoc.v:197385$13765 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:195097.3-195098.47" - process $proc$libresoc.v:195097$13584 + attribute \src "libresoc.v:197387.3-197388.47" + process $proc$libresoc.v:197387$13766 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:195099.3-195100.47" - process $proc$libresoc.v:195099$13585 + attribute \src "libresoc.v:197389.3-197390.47" + process $proc$libresoc.v:197389$13767 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:195101.3-195102.47" - process $proc$libresoc.v:195101$13586 + attribute \src "libresoc.v:197391.3-197392.47" + process $proc$libresoc.v:197391$13768 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:195103.3-195104.37" - process $proc$libresoc.v:195103$13587 + attribute \src "libresoc.v:197393.3-197394.37" + process $proc$libresoc.v:197393$13769 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:195105.3-195106.43" - process $proc$libresoc.v:195105$13588 + attribute \src "libresoc.v:197395.3-197396.43" + process $proc$libresoc.v:197395$13770 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:195107.3-195108.39" - process $proc$libresoc.v:195107$13589 + attribute \src "libresoc.v:197397.3-197398.39" + process $proc$libresoc.v:197397$13771 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:195109.3-195110.49" - process $proc$libresoc.v:195109$13590 + attribute \src "libresoc.v:197399.3-197400.49" + process $proc$libresoc.v:197399$13772 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:195111.3-195112.39" - process $proc$libresoc.v:195111$13591 + attribute \src "libresoc.v:197401.3-197402.39" + process $proc$libresoc.v:197401$13773 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:195113.3-195114.43" - process $proc$libresoc.v:195113$13592 + attribute \src "libresoc.v:197403.3-197404.43" + process $proc$libresoc.v:197403$13774 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:195115.3-195116.27" - process $proc$libresoc.v:195115$13593 + attribute \src "libresoc.v:197405.3-197406.27" + process $proc$libresoc.v:197405$13775 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:195117.3-195118.43" - process $proc$libresoc.v:195117$13594 + attribute \src "libresoc.v:197407.3-197408.43" + process $proc$libresoc.v:197407$13776 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:195119.3-195120.47" - process $proc$libresoc.v:195119$13595 + attribute \src "libresoc.v:197409.3-197410.47" + process $proc$libresoc.v:197409$13777 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:195751.3-195759.6" - process $proc$libresoc.v:195751$13596 + attribute \src "libresoc.v:198037.3-198045.6" + process $proc$libresoc.v:198037$13778 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13597 $1\dbg_dmi_addr_i$next[3:0]$13598 - attribute \src "libresoc.v:195752.5-195752.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13779 $1\dbg_dmi_addr_i$next[3:0]$13780 + attribute \src "libresoc.v:198038.5-198038.29" switch \initial - attribute \src "libresoc.v:195752.9-195752.17" + attribute \src "libresoc.v:198038.9-198038.17" case 1'1 case end @@ -408523,21 +412504,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13598 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13780 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13598 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13780 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13597 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13779 end - attribute \src "libresoc.v:195760.3-195768.6" - process $proc$libresoc.v:195760$13599 + attribute \src "libresoc.v:198046.3-198054.6" + process $proc$libresoc.v:198046$13781 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13600 $1\dbg_dmi_req_i$next[0:0]$13601 - attribute \src "libresoc.v:195761.5-195761.29" + assign $0\dbg_dmi_req_i$next[0:0]$13782 $1\dbg_dmi_req_i$next[0:0]$13783 + attribute \src "libresoc.v:198047.5-198047.29" switch \initial - attribute \src "libresoc.v:195761.9-195761.17" + attribute \src "libresoc.v:198047.9-198047.17" case 1'1 case end @@ -408546,21 +412527,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13601 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13783 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13601 \jtag_dmi0__req_i + assign $1\dbg_dmi_req_i$next[0:0]$13783 \jtag_dmi0__req_i end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13600 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13782 end - attribute \src "libresoc.v:195769.3-195777.6" - process $proc$libresoc.v:195769$13602 + attribute \src "libresoc.v:198055.3-198063.6" + process $proc$libresoc.v:198055$13784 assign { } { } assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13603 $1\dec2_cur_eint$next[0:0]$13604 - attribute \src "libresoc.v:195770.5-195770.29" + assign $0\dec2_cur_eint$next[0:0]$13785 $1\dec2_cur_eint$next[0:0]$13786 + attribute \src "libresoc.v:198056.5-198056.29" switch \initial - attribute \src "libresoc.v:195770.9-195770.17" + attribute \src "libresoc.v:198056.9-198056.17" case 1'1 case end @@ -408569,38 +412550,38 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13604 1'0 + assign $1\dec2_cur_eint$next[0:0]$13786 1'0 case - assign $1\dec2_cur_eint$next[0:0]$13604 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$13786 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13603 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13785 end - attribute \src "libresoc.v:195778.3-195787.6" - process $proc$libresoc.v:195778$13605 + attribute \src "libresoc.v:198064.3-198073.6" + process $proc$libresoc.v:198064$13787 assign { } { } assign { } { } - assign $0\delay$next[1:0]$13606 $1\delay$next[1:0]$13607 - attribute \src "libresoc.v:195779.5-195779.29" + assign $0\delay$next[1:0]$13788 $1\delay$next[1:0]$13789 + attribute \src "libresoc.v:198065.5-198065.29" switch \initial - attribute \src "libresoc.v:195779.9-195779.17" + attribute \src "libresoc.v:198065.9-198065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\delay$next[1:0]$13607 \$25 [1:0] + assign $1\delay$next[1:0]$13789 \$25 [1:0] case - assign $1\delay$next[1:0]$13607 \delay + assign $1\delay$next[1:0]$13789 \delay end sync always - update \delay$next $0\delay$next[1:0]$13606 + update \delay$next $0\delay$next[1:0]$13788 end - attribute \src "libresoc.v:195788.3-195832.6" - process $proc$libresoc.v:195788$13608 + attribute \src "libresoc.v:198074.3-198118.6" + process $proc$libresoc.v:198074$13790 assign { } { } assign { } { } assign { } { } @@ -408631,23 +412612,23 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13609 $3\core_core_dststep$next[6:0]$13639 - assign $0\core_core_maxvl$next[6:0]$13610 $3\core_core_maxvl$next[6:0]$13640 - assign $0\core_core_pc$next[63:0]$13611 $3\core_core_pc$next[63:0]$13641 - assign $0\core_core_srcstep$next[6:0]$13612 $3\core_core_srcstep$next[6:0]$13642 - assign $0\core_core_subvl$next[1:0]$13613 $3\core_core_subvl$next[1:0]$13643 - assign $0\core_core_svstep$next[1:0]$13614 $3\core_core_svstep$next[1:0]$13644 - assign $0\core_core_vl$next[6:0]$13615 $3\core_core_vl$next[6:0]$13645 - assign $0\core_dec$next[63:0]$13616 $3\core_dec$next[63:0]$13646 - assign $0\core_eint$next[0:0]$13617 $3\core_eint$next[0:0]$13647 - assign $0\core_msr$next[63:0]$13618 $3\core_msr$next[63:0]$13648 - attribute \src "libresoc.v:195789.5-195789.29" + assign $0\core_core_dststep$next[6:0]$13791 $3\core_core_dststep$next[6:0]$13821 + assign $0\core_core_maxvl$next[6:0]$13792 $3\core_core_maxvl$next[6:0]$13822 + assign $0\core_core_pc$next[63:0]$13793 $3\core_core_pc$next[63:0]$13823 + assign $0\core_core_srcstep$next[6:0]$13794 $3\core_core_srcstep$next[6:0]$13824 + assign $0\core_core_subvl$next[1:0]$13795 $3\core_core_subvl$next[1:0]$13825 + assign $0\core_core_svstep$next[1:0]$13796 $3\core_core_svstep$next[1:0]$13826 + assign $0\core_core_vl$next[6:0]$13797 $3\core_core_vl$next[6:0]$13827 + assign $0\core_dec$next[63:0]$13798 $3\core_dec$next[63:0]$13828 + assign $0\core_eint$next[0:0]$13799 $3\core_eint$next[0:0]$13829 + assign $0\core_msr$next[63:0]$13800 $3\core_msr$next[63:0]$13830 + attribute \src "libresoc.v:198075.5-198075.29" switch \initial - attribute \src "libresoc.v:195789.9-195789.17" + attribute \src "libresoc.v:198075.9-198075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -408661,17 +412642,17 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13619 $2\core_core_dststep$next[6:0]$13629 - assign $1\core_core_maxvl$next[6:0]$13620 $2\core_core_maxvl$next[6:0]$13630 - assign $1\core_core_pc$next[63:0]$13621 $2\core_core_pc$next[63:0]$13631 - assign $1\core_core_srcstep$next[6:0]$13622 $2\core_core_srcstep$next[6:0]$13632 - assign $1\core_core_subvl$next[1:0]$13623 $2\core_core_subvl$next[1:0]$13633 - assign $1\core_core_svstep$next[1:0]$13624 $2\core_core_svstep$next[1:0]$13634 - assign $1\core_core_vl$next[6:0]$13625 $2\core_core_vl$next[6:0]$13635 - assign $1\core_dec$next[63:0]$13626 $2\core_dec$next[63:0]$13636 - assign $1\core_eint$next[0:0]$13627 $2\core_eint$next[0:0]$13637 - assign $1\core_msr$next[63:0]$13628 $2\core_msr$next[63:0]$13638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_core_dststep$next[6:0]$13801 $2\core_core_dststep$next[6:0]$13811 + assign $1\core_core_maxvl$next[6:0]$13802 $2\core_core_maxvl$next[6:0]$13812 + assign $1\core_core_pc$next[63:0]$13803 $2\core_core_pc$next[63:0]$13813 + assign $1\core_core_srcstep$next[6:0]$13804 $2\core_core_srcstep$next[6:0]$13814 + assign $1\core_core_subvl$next[1:0]$13805 $2\core_core_subvl$next[1:0]$13815 + assign $1\core_core_svstep$next[1:0]$13806 $2\core_core_svstep$next[1:0]$13816 + assign $1\core_core_vl$next[6:0]$13807 $2\core_core_vl$next[6:0]$13817 + assign $1\core_dec$next[63:0]$13808 $2\core_dec$next[63:0]$13818 + assign $1\core_eint$next[0:0]$13809 $2\core_eint$next[0:0]$13819 + assign $1\core_msr$next[63:0]$13810 $2\core_msr$next[63:0]$13820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408685,21 +412666,21 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13630 $2\core_core_vl$next[6:0]$13635 $2\core_core_srcstep$next[6:0]$13632 $2\core_core_dststep$next[6:0]$13629 $2\core_core_subvl$next[1:0]$13633 $2\core_core_svstep$next[1:0]$13634 $2\core_dec$next[63:0]$13636 $2\core_eint$next[0:0]$13637 $2\core_msr$next[63:0]$13638 $2\core_core_pc$next[63:0]$13631 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13812 $2\core_core_vl$next[6:0]$13817 $2\core_core_srcstep$next[6:0]$13814 $2\core_core_dststep$next[6:0]$13811 $2\core_core_subvl$next[1:0]$13815 $2\core_core_svstep$next[1:0]$13816 $2\core_dec$next[63:0]$13818 $2\core_eint$next[0:0]$13819 $2\core_msr$next[63:0]$13820 $2\core_core_pc$next[63:0]$13813 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13629 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13630 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13631 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13632 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13633 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13634 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13635 \core_core_vl - assign $2\core_dec$next[63:0]$13636 \core_dec - assign $2\core_eint$next[0:0]$13637 \core_eint - assign $2\core_msr$next[63:0]$13638 \core_msr + assign $2\core_core_dststep$next[6:0]$13811 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13812 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13813 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13814 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13815 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13816 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13817 \core_core_vl + assign $2\core_dec$next[63:0]$13818 \core_dec + assign $2\core_eint$next[0:0]$13819 \core_eint + assign $2\core_msr$next[63:0]$13820 \core_msr end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } assign { } { } assign { } { } @@ -408710,18 +412691,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13620 $1\core_core_vl$next[6:0]$13625 $1\core_core_srcstep$next[6:0]$13622 $1\core_core_dststep$next[6:0]$13619 $1\core_core_subvl$next[1:0]$13623 $1\core_core_svstep$next[1:0]$13624 $1\core_dec$next[63:0]$13626 $1\core_eint$next[0:0]$13627 $1\core_msr$next[63:0]$13628 $1\core_core_pc$next[63:0]$13621 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13802 $1\core_core_vl$next[6:0]$13807 $1\core_core_srcstep$next[6:0]$13804 $1\core_core_dststep$next[6:0]$13801 $1\core_core_subvl$next[1:0]$13805 $1\core_core_svstep$next[1:0]$13806 $1\core_dec$next[63:0]$13808 $1\core_eint$next[0:0]$13809 $1\core_msr$next[63:0]$13810 $1\core_core_pc$next[63:0]$13803 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13619 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13620 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13621 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13622 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13623 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13624 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13625 \core_core_vl - assign $1\core_dec$next[63:0]$13626 \core_dec - assign $1\core_eint$next[0:0]$13627 \core_eint - assign $1\core_msr$next[63:0]$13628 \core_msr + assign $1\core_core_dststep$next[6:0]$13801 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13802 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13803 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13804 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13805 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13806 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13807 \core_core_vl + assign $1\core_dec$next[63:0]$13808 \core_dec + assign $1\core_eint$next[0:0]$13809 \core_eint + assign $1\core_msr$next[63:0]$13810 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -408737,200 +412718,200 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13641 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13648 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13647 1'0 - assign $3\core_dec$next[63:0]$13646 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13644 2'00 - assign $3\core_core_subvl$next[1:0]$13643 2'00 - assign $3\core_core_dststep$next[6:0]$13639 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13642 7'0000000 - assign $3\core_core_vl$next[6:0]$13645 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13640 7'0000000 + assign $3\core_core_pc$next[63:0]$13823 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13830 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13829 1'0 + assign $3\core_dec$next[63:0]$13828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13826 2'00 + assign $3\core_core_subvl$next[1:0]$13825 2'00 + assign $3\core_core_dststep$next[6:0]$13821 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13824 7'0000000 + assign $3\core_core_vl$next[6:0]$13827 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13822 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13639 $1\core_core_dststep$next[6:0]$13619 - assign $3\core_core_maxvl$next[6:0]$13640 $1\core_core_maxvl$next[6:0]$13620 - assign $3\core_core_pc$next[63:0]$13641 $1\core_core_pc$next[63:0]$13621 - assign $3\core_core_srcstep$next[6:0]$13642 $1\core_core_srcstep$next[6:0]$13622 - assign $3\core_core_subvl$next[1:0]$13643 $1\core_core_subvl$next[1:0]$13623 - assign $3\core_core_svstep$next[1:0]$13644 $1\core_core_svstep$next[1:0]$13624 - assign $3\core_core_vl$next[6:0]$13645 $1\core_core_vl$next[6:0]$13625 - assign $3\core_dec$next[63:0]$13646 $1\core_dec$next[63:0]$13626 - assign $3\core_eint$next[0:0]$13647 $1\core_eint$next[0:0]$13627 - assign $3\core_msr$next[63:0]$13648 $1\core_msr$next[63:0]$13628 + assign $3\core_core_dststep$next[6:0]$13821 $1\core_core_dststep$next[6:0]$13801 + assign $3\core_core_maxvl$next[6:0]$13822 $1\core_core_maxvl$next[6:0]$13802 + assign $3\core_core_pc$next[63:0]$13823 $1\core_core_pc$next[63:0]$13803 + assign $3\core_core_srcstep$next[6:0]$13824 $1\core_core_srcstep$next[6:0]$13804 + assign $3\core_core_subvl$next[1:0]$13825 $1\core_core_subvl$next[1:0]$13805 + assign $3\core_core_svstep$next[1:0]$13826 $1\core_core_svstep$next[1:0]$13806 + assign $3\core_core_vl$next[6:0]$13827 $1\core_core_vl$next[6:0]$13807 + assign $3\core_dec$next[63:0]$13828 $1\core_dec$next[63:0]$13808 + assign $3\core_eint$next[0:0]$13829 $1\core_eint$next[0:0]$13809 + assign $3\core_msr$next[63:0]$13830 $1\core_msr$next[63:0]$13810 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13609 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13610 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13611 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13612 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13613 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13614 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13615 - update \core_dec$next $0\core_dec$next[63:0]$13616 - update \core_eint$next $0\core_eint$next[0:0]$13617 - update \core_msr$next $0\core_msr$next[63:0]$13618 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13791 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13792 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13793 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13794 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13795 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13796 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13797 + update \core_dec$next $0\core_dec$next[63:0]$13798 + update \core_eint$next $0\core_eint$next[0:0]$13799 + update \core_msr$next $0\core_msr$next[63:0]$13800 end - attribute \src "libresoc.v:195833.3-195853.6" - process $proc$libresoc.v:195833$13649 + attribute \src "libresoc.v:198119.3-198139.6" + process $proc$libresoc.v:198119$13831 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13650 $3\core_raw_insn_i$next[31:0]$13653 - attribute \src "libresoc.v:195834.5-195834.29" + assign $0\core_raw_insn_i$next[31:0]$13832 $3\core_raw_insn_i$next[31:0]$13835 + attribute \src "libresoc.v:198120.5-198120.29" switch \initial - attribute \src "libresoc.v:195834.9-195834.17" + attribute \src "libresoc.v:198120.9-198120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13651 $2\core_raw_insn_i$next[31:0]$13652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_raw_insn_i$next[31:0]$13833 $2\core_raw_insn_i$next[31:0]$13834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13652 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13834 \dec2_raw_opcode_in case - assign $2\core_raw_insn_i$next[31:0]$13652 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13834 \core_raw_insn_i end case - assign $1\core_raw_insn_i$next[31:0]$13651 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13833 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13653 0 + assign $3\core_raw_insn_i$next[31:0]$13835 0 case - assign $3\core_raw_insn_i$next[31:0]$13653 $1\core_raw_insn_i$next[31:0]$13651 + assign $3\core_raw_insn_i$next[31:0]$13835 $1\core_raw_insn_i$next[31:0]$13833 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13650 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13832 end - attribute \src "libresoc.v:195854.3-195878.6" - process $proc$libresoc.v:195854$13654 + attribute \src "libresoc.v:198140.3-198164.6" + process $proc$libresoc.v:198140$13836 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13655 $3\core_bigendian_i$10$next[0:0]$13658 - attribute \src "libresoc.v:195855.5-195855.29" + assign $0\core_bigendian_i$10$next[0:0]$13837 $3\core_bigendian_i$10$next[0:0]$13840 + attribute \src "libresoc.v:198141.5-198141.29" switch \initial - attribute \src "libresoc.v:195855.9-195855.17" + attribute \src "libresoc.v:198141.9-198141.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13656 $2\core_bigendian_i$10$next[0:0]$13657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_bigendian_i$10$next[0:0]$13838 $2\core_bigendian_i$10$next[0:0]$13839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i case - assign $2\core_bigendian_i$10$next[0:0]$13657 \core_bigendian_i$10 + assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i$10 end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13656 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13658 1'0 + assign $3\core_bigendian_i$10$next[0:0]$13840 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13658 $1\core_bigendian_i$10$next[0:0]$13656 + assign $3\core_bigendian_i$10$next[0:0]$13840 $1\core_bigendian_i$10$next[0:0]$13838 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13655 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13837 end - attribute \src "libresoc.v:195879.3-195903.6" - process $proc$libresoc.v:195879$13659 + attribute \src "libresoc.v:198165.3-198189.6" + process $proc$libresoc.v:198165$13841 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13660 $3\core_sv_a_nz$next[0:0]$13663 - attribute \src "libresoc.v:195880.5-195880.29" + assign $0\core_sv_a_nz$next[0:0]$13842 $3\core_sv_a_nz$next[0:0]$13845 + attribute \src "libresoc.v:198166.5-198166.29" switch \initial - attribute \src "libresoc.v:195880.9-195880.17" + attribute \src "libresoc.v:198166.9-198166.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13661 $2\core_sv_a_nz$next[0:0]$13662 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_sv_a_nz$next[0:0]$13843 $2\core_sv_a_nz$next[0:0]$13844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13662 \dec2_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13844 \dec2_sv_a_nz case - assign $2\core_sv_a_nz$next[0:0]$13662 \core_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13844 \core_sv_a_nz end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13661 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13843 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13661 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13843 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13663 1'0 + assign $3\core_sv_a_nz$next[0:0]$13845 1'0 case - assign $3\core_sv_a_nz$next[0:0]$13663 $1\core_sv_a_nz$next[0:0]$13661 + assign $3\core_sv_a_nz$next[0:0]$13845 $1\core_sv_a_nz$next[0:0]$13843 end sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13660 + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13842 end - attribute \src "libresoc.v:195904.3-195941.6" - process $proc$libresoc.v:195904$13664 + attribute \src "libresoc.v:198190.3-198227.6" + process $proc$libresoc.v:198190$13846 assign { } { } assign { } { } assign { } { } assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:195905.5-195905.29" + attribute \src "libresoc.v:198191.5-198191.29" switch \initial - attribute \src "libresoc.v:195905.9-195905.17" + attribute \src "libresoc.v:198191.9-198191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\insn_done[0:0] $2\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\insn_done[0:0] $3\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \$228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$234 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -408944,19 +412925,19 @@ module \ti case assign $1\insn_done[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\insn_done[0:0] $5\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$236 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\insn_done[0:0] $6\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408974,131 +412955,136 @@ module \ti sync always update \insn_done $0\insn_done[0:0] end - attribute \src "libresoc.v:195942.3-195952.6" - process $proc$libresoc.v:195942$13665 + attribute \src "libresoc.v:198228.3-198238.6" + process $proc$libresoc.v:198228$13847 assign { } { } assign { } { } - assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:195943.5-195943.29" + assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] + attribute \src "libresoc.v:198229.5-198229.29" switch \initial - attribute \src "libresoc.v:195943.9-195943.17" + attribute \src "libresoc.v:198229.9-198229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 3'011 assign { } { } - assign $1\exec_insn_valid_i[0:0] 1'1 + assign $1\pred_insn_valid_i[0:0] 1'1 case - assign $1\exec_insn_valid_i[0:0] 1'0 + assign $1\pred_insn_valid_i[0:0] 1'0 end sync always - update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] end - attribute \src "libresoc.v:195953.3-195968.6" - process $proc$libresoc.v:195953$13666 + attribute \src "libresoc.v:198239.3-198249.6" + process $proc$libresoc.v:198239$13848 assign { } { } assign { } { } - assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:195954.5-195954.29" + assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] + attribute \src "libresoc.v:198240.5-198240.29" switch \initial - attribute \src "libresoc.v:195954.9-195954.17" + attribute \src "libresoc.v:198240.9-198240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'100 assign { } { } - assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$236 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\exec_pc_ready_i[0:0] 1'1 - case - assign $2\exec_pc_ready_i[0:0] 1'0 - end + assign $1\pred_mask_ready_i[0:0] 1'1 case - assign $1\exec_pc_ready_i[0:0] 1'0 + assign $1\pred_mask_ready_i[0:0] 1'0 end sync always - update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] + update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] end - attribute \src "libresoc.v:195969.3-195989.6" - process $proc$libresoc.v:195969$13667 + attribute \src "libresoc.v:198250.3-198260.6" + process $proc$libresoc.v:198250$13849 assign { } { } assign { } { } - assign $0\next_srcstep[6:0] $1\next_srcstep[6:0] - attribute \src "libresoc.v:195970.5-195970.29" + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:198251.5-198251.29" switch \initial - attribute \src "libresoc.v:195970.9-195970.17" + attribute \src "libresoc.v:198251.9-198251.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'010 assign { } { } - assign $1\next_srcstep[6:0] $2\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + assign $1\exec_insn_valid_i[0:0] 1'1 + case + assign $1\exec_insn_valid_i[0:0] 1'0 + end + sync always + update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + end + attribute \src "libresoc.v:198261.3-198276.6" + process $proc$libresoc.v:198261$13850 + assign { } { } + assign { } { } + assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:198262.5-198262.29" + switch \initial + attribute \src "libresoc.v:198262.9-198262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$242 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\next_srcstep[6:0] $3\next_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" - switch \exec_pc_valid_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\next_srcstep[6:0] \$244 [6:0] - case - assign $3\next_srcstep[6:0] 7'0000000 - end + assign $2\exec_pc_ready_i[0:0] 1'1 case - assign $2\next_srcstep[6:0] 7'0000000 + assign $2\exec_pc_ready_i[0:0] 1'0 end case - assign $1\next_srcstep[6:0] 7'0000000 + assign $1\exec_pc_ready_i[0:0] 1'0 end sync always - update \next_srcstep $0\next_srcstep[6:0] + update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:195990.3-196010.6" - process $proc$libresoc.v:195990$13668 + attribute \src "libresoc.v:198277.3-198297.6" + process $proc$libresoc.v:198277$13851 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:195991.5-195991.29" + attribute \src "libresoc.v:198278.5-198278.29" switch \initial - attribute \src "libresoc.v:195991.9-195991.17" + attribute \src "libresoc.v:198278.9-198278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$248 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\is_last[0:0] \$253 + assign $3\is_last[0:0] \$250 case assign $3\is_last[0:0] 1'0 end @@ -409111,64 +413097,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:196011.3-196020.6" - process $proc$libresoc.v:196011$13669 + attribute \src "libresoc.v:198298.3-198307.6" + process $proc$libresoc.v:198298$13852 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13670 $1\core_wen$11[2:0]$13671 - attribute \src "libresoc.v:196012.5-196012.29" + assign $0\core_wen$11[2:0]$13853 $1\core_wen$11[2:0]$13854 + attribute \src "libresoc.v:198299.5-198299.29" switch \initial - attribute \src "libresoc.v:196012.9-196012.17" + attribute \src "libresoc.v:198299.9-198299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13671 3'100 + assign $1\core_wen$11[2:0]$13854 3'100 case - assign $1\core_wen$11[2:0]$13671 3'000 + assign $1\core_wen$11[2:0]$13854 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13670 + update \core_wen$11 $0\core_wen$11[2:0]$13853 end - attribute \src "libresoc.v:196021.3-196030.6" - process $proc$libresoc.v:196021$13672 + attribute \src "libresoc.v:198308.3-198317.6" + process $proc$libresoc.v:198308$13855 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13673 $1\core_data_i$12[63:0]$13674 - attribute \src "libresoc.v:196022.5-196022.29" + assign $0\core_data_i$12[63:0]$13856 $1\core_data_i$12[63:0]$13857 + attribute \src "libresoc.v:198309.5-198309.29" switch \initial - attribute \src "libresoc.v:196022.9-196022.17" + attribute \src "libresoc.v:198309.9-198309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13674 \$255 + assign $1\core_data_i$12[63:0]$13857 \$252 case - assign $1\core_data_i$12[63:0]$13674 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13857 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13673 + update \core_data_i$12 $0\core_data_i$12[63:0]$13856 end - attribute \src "libresoc.v:196031.3-196041.6" - process $proc$libresoc.v:196031$13675 + attribute \src "libresoc.v:198318.3-198328.6" + process $proc$libresoc.v:198318$13858 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:196032.5-196032.29" + attribute \src "libresoc.v:198319.5-198319.29" switch \initial - attribute \src "libresoc.v:196032.9-196032.17" + attribute \src "libresoc.v:198319.9-198319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -409180,24 +413166,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:196042.3-196066.6" - process $proc$libresoc.v:196042$13676 + attribute \src "libresoc.v:198329.3-198353.6" + process $proc$libresoc.v:198329$13859 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:196043.5-196043.29" + attribute \src "libresoc.v:198330.5-198330.29" switch \initial - attribute \src "libresoc.v:196043.9-196043.17" + attribute \src "libresoc.v:198330.9-198330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409210,8 +413196,8 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" - switch \$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + switch \$254 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -409225,24 +413211,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:196067.3-196082.6" - process $proc$libresoc.v:196067$13677 + attribute \src "libresoc.v:198354.3-198369.6" + process $proc$libresoc.v:198354$13860 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:196068.5-196068.29" + attribute \src "libresoc.v:198355.5-198355.29" switch \initial - attribute \src "libresoc.v:196068.9-196068.17" + attribute \src "libresoc.v:198355.9-198355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409257,89 +413243,89 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:196083.3-196117.6" - process $proc$libresoc.v:196083$13678 + attribute \src "libresoc.v:198370.3-198404.6" + process $proc$libresoc.v:198370$13861 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13679 $5\exec_fsm_state$next[0:0]$13684 - attribute \src "libresoc.v:196084.5-196084.29" + assign $0\exec_fsm_state$next[0:0]$13862 $5\exec_fsm_state$next[0:0]$13867 + attribute \src "libresoc.v:198371.5-198371.29" switch \initial - attribute \src "libresoc.v:196084.9-196084.17" + attribute \src "libresoc.v:198371.9-198371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13680 $2\exec_fsm_state$next[0:0]$13681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $1\exec_fsm_state$next[0:0]$13863 $2\exec_fsm_state$next[0:0]$13864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13681 1'1 + assign $2\exec_fsm_state$next[0:0]$13864 1'1 case - assign $2\exec_fsm_state$next[0:0]$13681 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13864 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13680 $3\exec_fsm_state$next[0:0]$13682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$259 + assign $1\exec_fsm_state$next[0:0]$13863 $3\exec_fsm_state$next[0:0]$13865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13682 $4\exec_fsm_state$next[0:0]$13683 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:460" + assign $3\exec_fsm_state$next[0:0]$13865 $4\exec_fsm_state$next[0:0]$13866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13683 1'0 + assign $4\exec_fsm_state$next[0:0]$13866 1'0 case - assign $4\exec_fsm_state$next[0:0]$13683 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13866 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13682 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13865 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13680 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13863 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13684 1'0 + assign $5\exec_fsm_state$next[0:0]$13867 1'0 case - assign $5\exec_fsm_state$next[0:0]$13684 $1\exec_fsm_state$next[0:0]$13680 + assign $5\exec_fsm_state$next[0:0]$13867 $1\exec_fsm_state$next[0:0]$13863 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13679 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13862 end - attribute \src "libresoc.v:196118.3-196133.6" - process $proc$libresoc.v:196118$13685 + attribute \src "libresoc.v:198405.3-198420.6" + process $proc$libresoc.v:198405$13868 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:196119.5-196119.29" + attribute \src "libresoc.v:198406.5-198406.29" switch \initial - attribute \src "libresoc.v:196119.9-196119.17" + attribute \src "libresoc.v:198406.9-198406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" - switch \$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -409353,18 +413339,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:196134.3-196143.6" - process $proc$libresoc.v:196134$13686 + attribute \src "libresoc.v:198421.3-198430.6" + process $proc$libresoc.v:198421$13869 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:196135.5-196135.29" + attribute \src "libresoc.v:198422.5-198422.29" switch \initial - attribute \src "libresoc.v:196135.9-196135.17" + attribute \src "libresoc.v:198422.9-198422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409376,18 +413362,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:196144.3-196153.6" - process $proc$libresoc.v:196144$13687 + attribute \src "libresoc.v:198431.3-198440.6" + process $proc$libresoc.v:198431$13870 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:196145.5-196145.29" + attribute \src "libresoc.v:198432.5-198432.29" switch \initial - attribute \src "libresoc.v:196145.9-196145.17" + attribute \src "libresoc.v:198432.9-198432.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409399,14 +413385,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:196154.3-196162.6" - process $proc$libresoc.v:196154$13688 + attribute \src "libresoc.v:198441.3-198449.6" + process $proc$libresoc.v:198441$13871 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13689 $1\d_reg_delay$next[0:0]$13690 - attribute \src "libresoc.v:196155.5-196155.29" + assign $0\d_reg_delay$next[0:0]$13872 $1\d_reg_delay$next[0:0]$13873 + attribute \src "libresoc.v:198442.5-198442.29" switch \initial - attribute \src "libresoc.v:196155.9-196155.17" + attribute \src "libresoc.v:198442.9-198442.17" case 1'1 case end @@ -409415,25 +413401,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13690 1'0 + assign $1\d_reg_delay$next[0:0]$13873 1'0 case - assign $1\d_reg_delay$next[0:0]$13690 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13873 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13689 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13872 end - attribute \src "libresoc.v:196163.3-196172.6" - process $proc$libresoc.v:196163$13691 + attribute \src "libresoc.v:198450.3-198459.6" + process $proc$libresoc.v:198450$13874 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:196164.5-196164.29" + attribute \src "libresoc.v:198451.5-198451.29" switch \initial - attribute \src "libresoc.v:196164.9-196164.17" + attribute \src "libresoc.v:198451.9-198451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409445,18 +413431,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:196173.3-196182.6" - process $proc$libresoc.v:196173$13692 + attribute \src "libresoc.v:198460.3-198469.6" + process $proc$libresoc.v:198460$13875 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:196174.5-196174.29" + attribute \src "libresoc.v:198461.5-198461.29" switch \initial - attribute \src "libresoc.v:196174.9-196174.17" + attribute \src "libresoc.v:198461.9-198461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409468,18 +413454,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:196183.3-196192.6" - process $proc$libresoc.v:196183$13693 + attribute \src "libresoc.v:198470.3-198479.6" + process $proc$libresoc.v:198470$13876 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:196184.5-196184.29" + attribute \src "libresoc.v:198471.5-198471.29" switch \initial - attribute \src "libresoc.v:196184.9-196184.17" + attribute \src "libresoc.v:198471.9-198471.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409491,14 +413477,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:196193.3-196201.6" - process $proc$libresoc.v:196193$13694 + attribute \src "libresoc.v:198480.3-198488.6" + process $proc$libresoc.v:198480$13877 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13695 $1\d_cr_delay$next[0:0]$13696 - attribute \src "libresoc.v:196194.5-196194.29" + assign $0\d_cr_delay$next[0:0]$13878 $1\d_cr_delay$next[0:0]$13879 + attribute \src "libresoc.v:198481.5-198481.29" switch \initial - attribute \src "libresoc.v:196194.9-196194.17" + attribute \src "libresoc.v:198481.9-198481.17" case 1'1 case end @@ -409507,48 +413493,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13696 1'0 + assign $1\d_cr_delay$next[0:0]$13879 1'0 case - assign $1\d_cr_delay$next[0:0]$13696 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13879 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13695 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13878 end - attribute \src "libresoc.v:196202.3-196211.6" - process $proc$libresoc.v:196202$13697 + attribute \src "libresoc.v:198489.3-198498.6" + process $proc$libresoc.v:198489$13880 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:196203.5-196203.29" + attribute \src "libresoc.v:198490.5-198490.29" switch \initial - attribute \src "libresoc.v:196203.9-196203.17" + attribute \src "libresoc.v:198490.9-198490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$263 + assign $1\dbg_d_cr_data[63:0] \$260 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:196212.3-196221.6" - process $proc$libresoc.v:196212$13698 + attribute \src "libresoc.v:198499.3-198508.6" + process $proc$libresoc.v:198499$13881 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:196213.5-196213.29" + attribute \src "libresoc.v:198500.5-198500.29" switch \initial - attribute \src "libresoc.v:196213.9-196213.17" + attribute \src "libresoc.v:198500.9-198500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409560,18 +413546,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:196222.3-196231.6" - process $proc$libresoc.v:196222$13699 + attribute \src "libresoc.v:198509.3-198518.6" + process $proc$libresoc.v:198509$13882 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:196223.5-196223.29" + attribute \src "libresoc.v:198510.5-198510.29" switch \initial - attribute \src "libresoc.v:196223.9-196223.17" + attribute \src "libresoc.v:198510.9-198510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:964" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409583,14 +413569,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:196232.3-196240.6" - process $proc$libresoc.v:196232$13700 + attribute \src "libresoc.v:198519.3-198527.6" + process $proc$libresoc.v:198519$13883 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13701 $1\d_xer_delay$next[0:0]$13702 - attribute \src "libresoc.v:196233.5-196233.29" + assign $0\d_xer_delay$next[0:0]$13884 $1\d_xer_delay$next[0:0]$13885 + attribute \src "libresoc.v:198520.5-198520.29" switch \initial - attribute \src "libresoc.v:196233.9-196233.17" + attribute \src "libresoc.v:198520.9-198520.17" case 1'1 case end @@ -409599,48 +413585,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13702 1'0 + assign $1\d_xer_delay$next[0:0]$13885 1'0 case - assign $1\d_xer_delay$next[0:0]$13702 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13885 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13701 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13884 end - attribute \src "libresoc.v:196241.3-196250.6" - process $proc$libresoc.v:196241$13703 + attribute \src "libresoc.v:198528.3-198537.6" + process $proc$libresoc.v:198528$13886 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:196242.5-196242.29" + attribute \src "libresoc.v:198529.5-198529.29" switch \initial - attribute \src "libresoc.v:196242.9-196242.17" + attribute \src "libresoc.v:198529.9-198529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$265 + assign $1\dbg_d_xer_data[63:0] \$262 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:196251.3-196260.6" - process $proc$libresoc.v:196251$13704 + attribute \src "libresoc.v:198538.3-198547.6" + process $proc$libresoc.v:198538$13887 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:196252.5-196252.29" + attribute \src "libresoc.v:198539.5-198539.29" switch \initial - attribute \src "libresoc.v:196252.9-196252.17" + attribute \src "libresoc.v:198539.9-198539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409652,18 +413638,18 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:196261.3-196275.6" - process $proc$libresoc.v:196261$13705 + attribute \src "libresoc.v:198548.3-198562.6" + process $proc$libresoc.v:198548$13888 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:196262.5-196262.29" + attribute \src "libresoc.v:198549.5-198549.29" switch \initial - attribute \src "libresoc.v:196262.9-196262.17" + attribute \src "libresoc.v:198549.9-198549.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -409679,18 +413665,18 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:196276.3-196290.6" - process $proc$libresoc.v:196276$13706 + attribute \src "libresoc.v:198563.3-198577.6" + process $proc$libresoc.v:198563$13889 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:196277.5-196277.29" + attribute \src "libresoc.v:198564.5-198564.29" switch \initial - attribute \src "libresoc.v:196277.9-196277.17" + attribute \src "libresoc.v:198564.9-198564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -409706,113 +413692,113 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:196291.3-196318.6" - process $proc$libresoc.v:196291$13707 + attribute \src "libresoc.v:198578.3-198605.6" + process $proc$libresoc.v:198578$13890 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13708 $2\fsm_state$next[1:0]$13710 - attribute \src "libresoc.v:196292.5-196292.29" + assign $0\fsm_state$next[1:0]$13891 $2\fsm_state$next[1:0]$13893 + attribute \src "libresoc.v:198579.5-198579.29" switch \initial - attribute \src "libresoc.v:196292.9-196292.17" + attribute \src "libresoc.v:198579.9-198579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'01 + assign $1\fsm_state$next[1:0]$13892 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'10 + assign $1\fsm_state$next[1:0]$13892 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'11 + assign $1\fsm_state$next[1:0]$13892 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13709 2'00 + assign $1\fsm_state$next[1:0]$13892 2'00 case - assign $1\fsm_state$next[1:0]$13709 \fsm_state + assign $1\fsm_state$next[1:0]$13892 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13710 2'00 + assign $2\fsm_state$next[1:0]$13893 2'00 case - assign $2\fsm_state$next[1:0]$13710 $1\fsm_state$next[1:0]$13709 + assign $2\fsm_state$next[1:0]$13893 $1\fsm_state$next[1:0]$13892 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13708 + update \fsm_state$next $0\fsm_state$next[1:0]$13891 end - attribute \src "libresoc.v:196319.3-196329.6" - process $proc$libresoc.v:196319$13711 + attribute \src "libresoc.v:198606.3-198616.6" + process $proc$libresoc.v:198606$13894 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:196320.5-196320.29" + attribute \src "libresoc.v:198607.5-198607.29" switch \initial - attribute \src "libresoc.v:196320.9-196320.17" + attribute \src "libresoc.v:198607.9-198607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$267 [63:0] + assign $1\new_dec[63:0] \$264 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:196330.3-196344.6" - process $proc$libresoc.v:196330$13712 + attribute \src "libresoc.v:198617.3-198631.6" + process $proc$libresoc.v:198617$13895 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13713 $1\core_issue__addr$13[2:0]$13714 - attribute \src "libresoc.v:196331.5-196331.29" + assign $0\core_issue__addr$13[2:0]$13896 $1\core_issue__addr$13[2:0]$13897 + attribute \src "libresoc.v:198618.5-198618.29" switch \initial - attribute \src "libresoc.v:196331.9-196331.17" + attribute \src "libresoc.v:198618.9-198618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13714 3'110 + assign $1\core_issue__addr$13[2:0]$13897 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13714 3'111 + assign $1\core_issue__addr$13[2:0]$13897 3'111 case - assign $1\core_issue__addr$13[2:0]$13714 3'000 + assign $1\core_issue__addr$13[2:0]$13897 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13713 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13896 end - attribute \src "libresoc.v:196345.3-196359.6" - process $proc$libresoc.v:196345$13715 + attribute \src "libresoc.v:198632.3-198646.6" + process $proc$libresoc.v:198632$13898 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:196346.5-196346.29" + attribute \src "libresoc.v:198633.5-198633.29" switch \initial - attribute \src "libresoc.v:196346.9-196346.17" + attribute \src "libresoc.v:198633.9-198633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -409828,18 +413814,18 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:196360.3-196374.6" - process $proc$libresoc.v:196360$13716 + attribute \src "libresoc.v:198647.3-198661.6" + process $proc$libresoc.v:198647$13899 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:196361.5-196361.29" + attribute \src "libresoc.v:198648.5-198648.29" switch \initial - attribute \src "libresoc.v:196361.9-196361.17" + attribute \src "libresoc.v:198648.9-198648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -409855,70 +413841,70 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:196375.3-196390.6" - process $proc$libresoc.v:196375$13717 + attribute \src "libresoc.v:198662.3-198677.6" + process $proc$libresoc.v:198662$13900 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13718 $2\dec2_cur_dec$next[63:0]$13720 - attribute \src "libresoc.v:196376.5-196376.29" + assign $0\dec2_cur_dec$next[63:0]$13901 $2\dec2_cur_dec$next[63:0]$13903 + attribute \src "libresoc.v:198663.5-198663.29" switch \initial - attribute \src "libresoc.v:196376.9-196376.17" + attribute \src "libresoc.v:198663.9-198663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13719 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13902 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13719 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13902 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13720 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13720 $1\dec2_cur_dec$next[63:0]$13719 + assign $2\dec2_cur_dec$next[63:0]$13903 $1\dec2_cur_dec$next[63:0]$13902 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13718 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13901 end - attribute \src "libresoc.v:196391.3-196401.6" - process $proc$libresoc.v:196391$13721 + attribute \src "libresoc.v:198678.3-198688.6" + process $proc$libresoc.v:198678$13904 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:196392.5-196392.29" + attribute \src "libresoc.v:198679.5-198679.29" switch \initial - attribute \src "libresoc.v:196392.9-196392.17" + attribute \src "libresoc.v:198679.9-198679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$270 [63:0] + assign $1\new_tb[63:0] \$267 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:196402.3-196410.6" - process $proc$libresoc.v:196402$13722 + attribute \src "libresoc.v:198689.3-198697.6" + process $proc$libresoc.v:198689$13905 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13723 $1\dbg_dmi_we_i$next[0:0]$13724 - attribute \src "libresoc.v:196403.5-196403.29" + assign $0\dbg_dmi_we_i$next[0:0]$13906 $1\dbg_dmi_we_i$next[0:0]$13907 + attribute \src "libresoc.v:198690.5-198690.29" switch \initial - attribute \src "libresoc.v:196403.9-196403.17" + attribute \src "libresoc.v:198690.9-198690.17" case 1'1 case end @@ -409927,21 +413913,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13724 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13907 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13724 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13907 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13723 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13906 end - attribute \src "libresoc.v:196411.3-196419.6" - process $proc$libresoc.v:196411$13725 + attribute \src "libresoc.v:198698.3-198706.6" + process $proc$libresoc.v:198698$13908 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13726 $1\pc_ok_delay$next[0:0]$13727 - attribute \src "libresoc.v:196412.5-196412.29" + assign $0\pc_ok_delay$next[0:0]$13909 $1\pc_ok_delay$next[0:0]$13910 + attribute \src "libresoc.v:198699.5-198699.29" switch \initial - attribute \src "libresoc.v:196412.9-196412.17" + attribute \src "libresoc.v:198699.9-198699.17" case 1'1 case end @@ -409950,26 +413936,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13727 1'0 + assign $1\pc_ok_delay$next[0:0]$13910 1'0 case - assign $1\pc_ok_delay$next[0:0]$13727 \$38 + assign $1\pc_ok_delay$next[0:0]$13910 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13726 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13909 end - attribute \src "libresoc.v:196420.3-196435.6" - process $proc$libresoc.v:196420$13728 + attribute \src "libresoc.v:198707.3-198722.6" + process $proc$libresoc.v:198707$13911 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:196421.5-196421.29" + attribute \src "libresoc.v:198708.5-198708.29" switch \initial - attribute \src "libresoc.v:196421.9-196421.17" + attribute \src "libresoc.v:198708.9-198708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409978,7 +413964,7 @@ module \ti case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409990,18 +413976,18 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:196436.3-196448.6" - process $proc$libresoc.v:196436$13729 + attribute \src "libresoc.v:198723.3-198735.6" + process $proc$libresoc.v:198723$13912 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:196437.5-196437.29" + attribute \src "libresoc.v:198724.5-198724.29" switch \initial - attribute \src "libresoc.v:196437.9-196437.17" + attribute \src "libresoc.v:198724.9-198724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410014,14 +414000,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:196449.3-196457.6" - process $proc$libresoc.v:196449$13730 + attribute \src "libresoc.v:198736.3-198744.6" + process $proc$libresoc.v:198736$13913 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13731 $1\svstate_ok_delay$next[0:0]$13732 - attribute \src "libresoc.v:196450.5-196450.29" + assign $0\svstate_ok_delay$next[0:0]$13914 $1\svstate_ok_delay$next[0:0]$13915 + attribute \src "libresoc.v:198737.5-198737.29" switch \initial - attribute \src "libresoc.v:196450.9-196450.17" + attribute \src "libresoc.v:198737.9-198737.17" case 1'1 case end @@ -410030,26 +414016,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13732 1'0 + assign $1\svstate_ok_delay$next[0:0]$13915 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13732 \$40 + assign $1\svstate_ok_delay$next[0:0]$13915 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13731 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13914 end - attribute \src "libresoc.v:196458.3-196473.6" - process $proc$libresoc.v:196458$13733 + attribute \src "libresoc.v:198745.3-198760.6" + process $proc$libresoc.v:198745$13916 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:196459.5-196459.29" + attribute \src "libresoc.v:198746.5-198746.29" switch \initial - attribute \src "libresoc.v:196459.9-196459.17" + attribute \src "libresoc.v:198746.9-198746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410058,7 +414044,7 @@ module \ti case assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" switch \svstate_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410070,18 +414056,18 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:196474.3-196486.6" - process $proc$libresoc.v:196474$13734 + attribute \src "libresoc.v:198761.3-198773.6" + process $proc$libresoc.v:198761$13917 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:196475.5-196475.29" + attribute \src "libresoc.v:198762.5-198762.29" switch \initial - attribute \src "libresoc.v:196475.9-196475.17" + attribute \src "libresoc.v:198762.9-198762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410094,14 +414080,14 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:196487.3-196495.6" - process $proc$libresoc.v:196487$13735 + attribute \src "libresoc.v:198774.3-198782.6" + process $proc$libresoc.v:198774$13918 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13736 $1\dbg_dmi_din$next[63:0]$13737 - attribute \src "libresoc.v:196488.5-196488.29" + assign $0\dbg_dmi_din$next[63:0]$13919 $1\dbg_dmi_din$next[63:0]$13920 + attribute \src "libresoc.v:198775.5-198775.29" switch \initial - attribute \src "libresoc.v:196488.9-196488.17" + attribute \src "libresoc.v:198775.9-198775.17" case 1'1 case end @@ -410110,31 +414096,31 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13737 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13920 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13737 \jtag_dmi0__din + assign $1\dbg_dmi_din$next[63:0]$13920 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13736 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13919 end - attribute \src "libresoc.v:196496.3-196563.6" - process $proc$libresoc.v:196496$13738 + attribute \src "libresoc.v:198783.3-198850.6" + process $proc$libresoc.v:198783$13921 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:196497.5-196497.29" + attribute \src "libresoc.v:198784.5-198784.29" switch \initial - attribute \src "libresoc.v:196497.9-196497.17" + attribute \src "libresoc.v:198784.9-198784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410143,7 +414129,7 @@ module \ti case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410157,13 +414143,13 @@ module \ti case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410176,22 +414162,22 @@ module \ti assign $4\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410210,7 +414196,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410226,24 +414212,24 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:196564.3-196631.6" - process $proc$libresoc.v:196564$13739 + attribute \src "libresoc.v:198851.3-198918.6" + process $proc$libresoc.v:198851$13922 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:196565.5-196565.29" + attribute \src "libresoc.v:198852.5-198852.29" switch \initial - attribute \src "libresoc.v:196565.9-196565.17" + attribute \src "libresoc.v:198852.9-198852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410252,7 +414238,7 @@ module \ti case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410266,13 +414252,13 @@ module \ti case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410285,22 +414271,22 @@ module \ti assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410319,7 +414305,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410335,24 +414321,24 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:196632.3-196647.6" - process $proc$libresoc.v:196632$13740 + attribute \src "libresoc.v:198919.3-198934.6" + process $proc$libresoc.v:198919$13923 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:196633.5-196633.29" + attribute \src "libresoc.v:198920.5-198920.29" switch \initial - attribute \src "libresoc.v:196633.9-196633.17" + attribute \src "libresoc.v:198920.9-198920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410367,14 +414353,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:196648.3-196656.6" - process $proc$libresoc.v:196648$13741 + attribute \src "libresoc.v:198935.3-198943.6" + process $proc$libresoc.v:198935$13924 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13742 $1\jtag_dmi0__ack_o$next[0:0]$13743 - attribute \src "libresoc.v:196649.5-196649.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13925 $1\jtag_dmi0__ack_o$next[0:0]$13926 + attribute \src "libresoc.v:198936.5-198936.29" switch \initial - attribute \src "libresoc.v:196649.9-196649.17" + attribute \src "libresoc.v:198936.9-198936.17" case 1'1 case end @@ -410383,25 +414369,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 1'0 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13743 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13926 \dbg_dmi_ack_o end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13742 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13925 end - attribute \src "libresoc.v:196657.3-196667.6" - process $proc$libresoc.v:196657$13744 + attribute \src "libresoc.v:198944.3-198954.6" + process $proc$libresoc.v:198944$13927 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:196658.5-196658.29" + attribute \src "libresoc.v:198945.5-198945.29" switch \initial - attribute \src "libresoc.v:196658.9-196658.17" + attribute \src "libresoc.v:198945.9-198945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -410413,24 +414399,24 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:196668.3-196683.6" - process $proc$libresoc.v:196668$13745 + attribute \src "libresoc.v:198955.3-198970.6" + process $proc$libresoc.v:198955$13928 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:196669.5-196669.29" + attribute \src "libresoc.v:198956.5-198956.29" switch \initial - attribute \src "libresoc.v:196669.9-196669.17" + attribute \src "libresoc.v:198956.9-198956.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410445,24 +414431,24 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:196684.3-196717.6" - process $proc$libresoc.v:196684$13746 + attribute \src "libresoc.v:198971.3-199004.6" + process $proc$libresoc.v:198971$13929 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:196685.5-196685.29" + attribute \src "libresoc.v:198972.5-198972.29" switch \initial - attribute \src "libresoc.v:196685.9-196685.17" + attribute \src "libresoc.v:198972.9-198972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410475,7 +414461,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410488,7 +414474,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410503,24 +414489,24 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:196718.3-196751.6" - process $proc$libresoc.v:196718$13747 + attribute \src "libresoc.v:199005.3-199038.6" + process $proc$libresoc.v:199005$13930 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:196719.5-196719.29" + attribute \src "libresoc.v:199006.5-199006.29" switch \initial - attribute \src "libresoc.v:196719.9-196719.17" + attribute \src "libresoc.v:199006.9-199006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410533,7 +414519,7 @@ module \ti case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410546,7 +414532,7 @@ module \ti case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410561,50 +414547,50 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:196752.3-196772.6" - process $proc$libresoc.v:196752$13748 + attribute \src "libresoc.v:199039.3-199059.6" + process $proc$libresoc.v:199039$13931 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13749 $3\dec2_cur_pc$next[63:0]$13752 - attribute \src "libresoc.v:196753.5-196753.29" + assign $0\dec2_cur_pc$next[63:0]$13932 $3\dec2_cur_pc$next[63:0]$13935 + attribute \src "libresoc.v:199040.5-199040.29" switch \initial - attribute \src "libresoc.v:196753.9-196753.17" + attribute \src "libresoc.v:199040.9-199040.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13750 $2\dec2_cur_pc$next[63:0]$13751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\dec2_cur_pc$next[63:0]$13933 $2\dec2_cur_pc$next[63:0]$13934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13751 \pc + assign $2\dec2_cur_pc$next[63:0]$13934 \pc case - assign $2\dec2_cur_pc$next[63:0]$13751 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13934 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13750 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13933 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13752 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13935 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13752 $1\dec2_cur_pc$next[63:0]$13750 + assign $3\dec2_cur_pc$next[63:0]$13935 $1\dec2_cur_pc$next[63:0]$13933 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13749 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13932 end - attribute \src "libresoc.v:196773.3-196811.6" - process $proc$libresoc.v:196773$13753 + attribute \src "libresoc.v:199060.3-199098.6" + process $proc$libresoc.v:199060$13936 assign { } { } assign { } { } assign { } { } @@ -410629,19 +414615,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13754 $4\cur_cur_dststep$next[6:0]$13778 - assign $0\cur_cur_maxvl$next[6:0]$13755 $4\cur_cur_maxvl$next[6:0]$13779 - assign $0\cur_cur_srcstep$next[6:0]$13756 $4\cur_cur_srcstep$next[6:0]$13780 - assign $0\cur_cur_subvl$next[1:0]$13757 $4\cur_cur_subvl$next[1:0]$13781 - assign $0\cur_cur_svstep$next[1:0]$13758 $4\cur_cur_svstep$next[1:0]$13782 - assign $0\cur_cur_vl$next[6:0]$13759 $4\cur_cur_vl$next[6:0]$13783 - attribute \src "libresoc.v:196774.5-196774.29" + assign $0\cur_cur_dststep$next[6:0]$13937 $4\cur_cur_dststep$next[6:0]$13961 + assign $0\cur_cur_maxvl$next[6:0]$13938 $4\cur_cur_maxvl$next[6:0]$13962 + assign $0\cur_cur_srcstep$next[6:0]$13939 $4\cur_cur_srcstep$next[6:0]$13963 + assign $0\cur_cur_subvl$next[1:0]$13940 $4\cur_cur_subvl$next[1:0]$13964 + assign $0\cur_cur_svstep$next[1:0]$13941 $4\cur_cur_svstep$next[1:0]$13965 + assign $0\cur_cur_vl$next[6:0]$13942 $4\cur_cur_vl$next[6:0]$13966 + attribute \src "libresoc.v:199061.5-199061.29" switch \initial - attribute \src "libresoc.v:196774.9-196774.17" + attribute \src "libresoc.v:199061.9-199061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -410651,13 +414637,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13760 $2\cur_cur_dststep$next[6:0]$13766 - assign $1\cur_cur_maxvl$next[6:0]$13761 $2\cur_cur_maxvl$next[6:0]$13767 - assign $1\cur_cur_srcstep$next[6:0]$13762 $2\cur_cur_srcstep$next[6:0]$13768 - assign $1\cur_cur_subvl$next[1:0]$13763 $2\cur_cur_subvl$next[1:0]$13769 - assign $1\cur_cur_svstep$next[1:0]$13764 $2\cur_cur_svstep$next[1:0]$13770 - assign $1\cur_cur_vl$next[6:0]$13765 $2\cur_cur_vl$next[6:0]$13771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\cur_cur_dststep$next[6:0]$13943 $2\cur_cur_dststep$next[6:0]$13949 + assign $1\cur_cur_maxvl$next[6:0]$13944 $2\cur_cur_maxvl$next[6:0]$13950 + assign $1\cur_cur_srcstep$next[6:0]$13945 $2\cur_cur_srcstep$next[6:0]$13951 + assign $1\cur_cur_subvl$next[1:0]$13946 $2\cur_cur_subvl$next[1:0]$13952 + assign $1\cur_cur_svstep$next[1:0]$13947 $2\cur_cur_svstep$next[1:0]$13953 + assign $1\cur_cur_vl$next[6:0]$13948 $2\cur_cur_vl$next[6:0]$13954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410667,24 +414653,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13767 $2\cur_cur_vl$next[6:0]$13771 $2\cur_cur_srcstep$next[6:0]$13768 $2\cur_cur_dststep$next[6:0]$13766 $2\cur_cur_subvl$next[1:0]$13769 $2\cur_cur_svstep$next[1:0]$13770 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13950 $2\cur_cur_vl$next[6:0]$13954 $2\cur_cur_srcstep$next[6:0]$13951 $2\cur_cur_dststep$next[6:0]$13949 $2\cur_cur_subvl$next[1:0]$13952 $2\cur_cur_svstep$next[1:0]$13953 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13766 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13767 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13768 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13769 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13770 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13771 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13949 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13950 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13951 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13952 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13953 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13954 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13760 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13761 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13762 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13763 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13764 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13765 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13943 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13944 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13945 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13946 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13947 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13948 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410694,14 +414680,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13773 $3\cur_cur_vl$next[6:0]$13777 $3\cur_cur_srcstep$next[6:0]$13774 $3\cur_cur_dststep$next[6:0]$13772 $3\cur_cur_subvl$next[1:0]$13775 $3\cur_cur_svstep$next[1:0]$13776 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13956 $3\cur_cur_vl$next[6:0]$13960 $3\cur_cur_srcstep$next[6:0]$13957 $3\cur_cur_dststep$next[6:0]$13955 $3\cur_cur_subvl$next[1:0]$13958 $3\cur_cur_svstep$next[1:0]$13959 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13772 $1\cur_cur_dststep$next[6:0]$13760 - assign $3\cur_cur_maxvl$next[6:0]$13773 $1\cur_cur_maxvl$next[6:0]$13761 - assign $3\cur_cur_srcstep$next[6:0]$13774 $1\cur_cur_srcstep$next[6:0]$13762 - assign $3\cur_cur_subvl$next[1:0]$13775 $1\cur_cur_subvl$next[1:0]$13763 - assign $3\cur_cur_svstep$next[1:0]$13776 $1\cur_cur_svstep$next[1:0]$13764 - assign $3\cur_cur_vl$next[6:0]$13777 $1\cur_cur_vl$next[6:0]$13765 + assign $3\cur_cur_dststep$next[6:0]$13955 $1\cur_cur_dststep$next[6:0]$13943 + assign $3\cur_cur_maxvl$next[6:0]$13956 $1\cur_cur_maxvl$next[6:0]$13944 + assign $3\cur_cur_srcstep$next[6:0]$13957 $1\cur_cur_srcstep$next[6:0]$13945 + assign $3\cur_cur_subvl$next[1:0]$13958 $1\cur_cur_subvl$next[1:0]$13946 + assign $3\cur_cur_svstep$next[1:0]$13959 $1\cur_cur_svstep$next[1:0]$13947 + assign $3\cur_cur_vl$next[6:0]$13960 $1\cur_cur_vl$next[6:0]$13948 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -410713,36 +414699,36 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13782 2'00 - assign $4\cur_cur_subvl$next[1:0]$13781 2'00 - assign $4\cur_cur_dststep$next[6:0]$13778 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13780 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13783 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13779 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13965 2'00 + assign $4\cur_cur_subvl$next[1:0]$13964 2'00 + assign $4\cur_cur_dststep$next[6:0]$13961 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13963 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13966 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13962 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13778 $3\cur_cur_dststep$next[6:0]$13772 - assign $4\cur_cur_maxvl$next[6:0]$13779 $3\cur_cur_maxvl$next[6:0]$13773 - assign $4\cur_cur_srcstep$next[6:0]$13780 $3\cur_cur_srcstep$next[6:0]$13774 - assign $4\cur_cur_subvl$next[1:0]$13781 $3\cur_cur_subvl$next[1:0]$13775 - assign $4\cur_cur_svstep$next[1:0]$13782 $3\cur_cur_svstep$next[1:0]$13776 - assign $4\cur_cur_vl$next[6:0]$13783 $3\cur_cur_vl$next[6:0]$13777 + assign $4\cur_cur_dststep$next[6:0]$13961 $3\cur_cur_dststep$next[6:0]$13955 + assign $4\cur_cur_maxvl$next[6:0]$13962 $3\cur_cur_maxvl$next[6:0]$13956 + assign $4\cur_cur_srcstep$next[6:0]$13963 $3\cur_cur_srcstep$next[6:0]$13957 + assign $4\cur_cur_subvl$next[1:0]$13964 $3\cur_cur_subvl$next[1:0]$13958 + assign $4\cur_cur_svstep$next[1:0]$13965 $3\cur_cur_svstep$next[1:0]$13959 + assign $4\cur_cur_vl$next[6:0]$13966 $3\cur_cur_vl$next[6:0]$13960 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13754 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13755 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13756 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13757 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13758 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13759 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13937 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13938 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13939 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13940 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13941 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13942 end - attribute \src "libresoc.v:196812.3-196820.6" - process $proc$libresoc.v:196812$13784 + attribute \src "libresoc.v:199099.3-199107.6" + process $proc$libresoc.v:199099$13967 assign { } { } assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13785 $1\jtag_dmi0__dout$next[63:0]$13786 - attribute \src "libresoc.v:196813.5-196813.29" + assign $0\jtag_dmi0__dout$next[63:0]$13968 $1\jtag_dmi0__dout$next[63:0]$13969 + attribute \src "libresoc.v:199100.5-199100.29" switch \initial - attribute \src "libresoc.v:196813.9-196813.17" + attribute \src "libresoc.v:199100.9-199100.17" case 1'1 case end @@ -410751,285 +414737,285 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13786 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13969 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__dout$next[63:0]$13786 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13969 \dbg_dmi_dout end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13785 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13968 end - attribute \src "libresoc.v:196821.3-196850.6" - process $proc$libresoc.v:196821$13787 + attribute \src "libresoc.v:199108.3-199137.6" + process $proc$libresoc.v:199108$13970 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13788 $4\msr_read$next[0:0]$13792 - attribute \src "libresoc.v:196822.5-196822.29" + assign $0\msr_read$next[0:0]$13971 $4\msr_read$next[0:0]$13975 + attribute \src "libresoc.v:199109.5-199109.29" switch \initial - attribute \src "libresoc.v:196822.9-196822.17" + attribute \src "libresoc.v:199109.9-199109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13789 $2\msr_read$next[0:0]$13790 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\msr_read$next[0:0]$13972 $2\msr_read$next[0:0]$13973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13790 1'0 + assign $2\msr_read$next[0:0]$13973 1'0 case - assign $2\msr_read$next[0:0]$13790 \msr_read + assign $2\msr_read$next[0:0]$13973 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13789 $3\msr_read$next[0:0]$13791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\msr_read$next[0:0]$13972 $3\msr_read$next[0:0]$13974 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13791 1'1 + assign $3\msr_read$next[0:0]$13974 1'1 case - assign $3\msr_read$next[0:0]$13791 \msr_read + assign $3\msr_read$next[0:0]$13974 \msr_read end case - assign $1\msr_read$next[0:0]$13789 \msr_read + assign $1\msr_read$next[0:0]$13972 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13792 1'1 + assign $4\msr_read$next[0:0]$13975 1'1 case - assign $4\msr_read$next[0:0]$13792 $1\msr_read$next[0:0]$13789 + assign $4\msr_read$next[0:0]$13975 $1\msr_read$next[0:0]$13972 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13788 + update \msr_read$next $0\msr_read$next[0:0]$13971 end - attribute \src "libresoc.v:196851.3-196904.6" - process $proc$libresoc.v:196851$13793 + attribute \src "libresoc.v:199138.3-199191.6" + process $proc$libresoc.v:199138$13976 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13794 $6\fetch_fsm_state$next[1:0]$13800 - attribute \src "libresoc.v:196852.5-196852.29" + assign $0\fetch_fsm_state$next[1:0]$13977 $6\fetch_fsm_state$next[1:0]$13983 + attribute \src "libresoc.v:199139.5-199139.29" switch \initial - attribute \src "libresoc.v:196852.9-196852.17" + attribute \src "libresoc.v:199139.9-199139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $2\fetch_fsm_state$next[1:0]$13796 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + assign $1\fetch_fsm_state$next[1:0]$13978 $2\fetch_fsm_state$next[1:0]$13979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13796 2'01 + assign $2\fetch_fsm_state$next[1:0]$13979 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13796 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13979 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $3\fetch_fsm_state$next[1:0]$13797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\fetch_fsm_state$next[1:0]$13978 $3\fetch_fsm_state$next[1:0]$13980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13797 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13980 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13797 2'10 + assign $3\fetch_fsm_state$next[1:0]$13980 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $4\fetch_fsm_state$next[1:0]$13798 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + assign $1\fetch_fsm_state$next[1:0]$13978 $4\fetch_fsm_state$next[1:0]$13981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13798 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13981 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13798 2'10 + assign $4\fetch_fsm_state$next[1:0]$13981 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13795 $5\fetch_fsm_state$next[1:0]$13799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254" + assign $1\fetch_fsm_state$next[1:0]$13978 $5\fetch_fsm_state$next[1:0]$13982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13799 2'00 + assign $5\fetch_fsm_state$next[1:0]$13982 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13799 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13982 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13795 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13978 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13800 2'00 + assign $6\fetch_fsm_state$next[1:0]$13983 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13800 $1\fetch_fsm_state$next[1:0]$13795 + assign $6\fetch_fsm_state$next[1:0]$13983 $1\fetch_fsm_state$next[1:0]$13978 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13794 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13977 end - attribute \src "libresoc.v:196905.3-196925.6" - process $proc$libresoc.v:196905$13801 + attribute \src "libresoc.v:199192.3-199212.6" + process $proc$libresoc.v:199192$13984 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13802 $3\dec2_cur_msr$next[63:0]$13805 - attribute \src "libresoc.v:196906.5-196906.29" + assign $0\dec2_cur_msr$next[63:0]$13985 $3\dec2_cur_msr$next[63:0]$13988 + attribute \src "libresoc.v:199193.5-199193.29" switch \initial - attribute \src "libresoc.v:196906.9-196906.17" + attribute \src "libresoc.v:199193.9-199193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13803 $2\dec2_cur_msr$next[63:0]$13804 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + assign $1\dec2_cur_msr$next[63:0]$13986 $2\dec2_cur_msr$next[63:0]$13987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13804 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13987 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13804 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13987 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13803 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13986 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13805 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13988 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13805 $1\dec2_cur_msr$next[63:0]$13803 + assign $3\dec2_cur_msr$next[63:0]$13988 $1\dec2_cur_msr$next[63:0]$13986 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13802 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13985 end - attribute \src "libresoc.v:196926.3-196944.6" - process $proc$libresoc.v:196926$13806 + attribute \src "libresoc.v:199213.3-199231.6" + process $proc$libresoc.v:199213$13989 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13807 $1\nia$next[63:0]$13808 - attribute \src "libresoc.v:196927.5-196927.29" + assign $0\nia$next[63:0]$13990 $1\nia$next[63:0]$13991 + attribute \src "libresoc.v:199214.5-199214.29" switch \initial - attribute \src "libresoc.v:196927.9-196927.17" + attribute \src "libresoc.v:199214.9-199214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13808 $2\nia$next[63:0]$13809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\nia$next[63:0]$13991 $2\nia$next[63:0]$13992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13809 \nia + assign $2\nia$next[63:0]$13992 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13809 \$92 [63:0] + assign $2\nia$next[63:0]$13992 \$92 [63:0] end case - assign $1\nia$next[63:0]$13808 \nia + assign $1\nia$next[63:0]$13991 \nia end sync always - update \nia$next $0\nia$next[63:0]$13807 + update \nia$next $0\nia$next[63:0]$13990 end - attribute \src "libresoc.v:196945.3-196975.6" - process $proc$libresoc.v:196945$13810 + attribute \src "libresoc.v:199232.3-199262.6" + process $proc$libresoc.v:199232$13993 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13811 $1\dec2_raw_opcode_in$next[31:0]$13812 - attribute \src "libresoc.v:196946.5-196946.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13994 $1\dec2_raw_opcode_in$next[31:0]$13995 + attribute \src "libresoc.v:199233.5-199233.29" switch \initial - attribute \src "libresoc.v:196946.9-196946.17" + attribute \src "libresoc.v:199233.9-199233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13812 $2\dec2_raw_opcode_in$next[31:0]$13813 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $2\dec2_raw_opcode_in$next[31:0]$13996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13813 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13813 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13996 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13812 $3\dec2_raw_opcode_in$next[31:0]$13814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" + assign $1\dec2_raw_opcode_in$next[31:0]$13995 $3\dec2_raw_opcode_in$next[31:0]$13997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13814 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13814 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13997 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13812 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13995 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13811 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13994 end - attribute \src "libresoc.v:196976.3-196986.6" - process $proc$libresoc.v:196976$13815 + attribute \src "libresoc.v:199263.3-199273.6" + process $proc$libresoc.v:199263$13998 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:196977.5-196977.29" + attribute \src "libresoc.v:199264.5-199264.29" switch \initial - attribute \src "libresoc.v:196977.9-196977.17" + attribute \src "libresoc.v:199264.9-199264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -411041,8 +415027,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:196987.3-197043.6" - process $proc$libresoc.v:196987$13816 + attribute \src "libresoc.v:199274.3-199333.6" + process $proc$libresoc.v:199274$13999 assign { } { } assign { } { } assign { } { } @@ -411056,13 +415042,13 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:196988.5-196988.29" + attribute \src "libresoc.v:199275.5-199275.29" switch \initial - attribute \src "libresoc.v:196988.9-196988.17" + attribute \src "libresoc.v:199275.9-199275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 @@ -411078,7 +415064,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411102,7 +415088,7 @@ module \ti assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411123,7 +415109,7 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign { } { } assign { } { } @@ -411136,37 +415122,45 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\new_svstate_dststep[6:0] \cur_cur_dststep + assign { } { } assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl assign { } { } assign $4\new_svstate_subvl[1:0] \cur_cur_subvl assign $4\new_svstate_svstep[1:0] \cur_cur_svstep assign $4\new_svstate_vl[6:0] \cur_cur_vl + assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign { } { } + assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case 2'1- + assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case + assign { } { } assign { } { } assign $6\new_svstate_srcstep[6:0] \next_srcstep + assign $6\new_svstate_dststep[6:0] \next_dststep end case + assign $5\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep end attribute \src "libresoc.v:0.0-0.0" @@ -411177,13 +415171,13 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] + assign $4\new_svstate_dststep[6:0] $7\new_svstate_dststep[6:0] assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411193,9 +415187,9 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $5\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i + assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $7\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i case - assign $5\new_svstate_dststep[6:0] \cur_cur_dststep + assign $7\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $5\new_svstate_subvl[1:0] \cur_cur_subvl @@ -411219,25 +415213,25 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:197044.3-197059.6" - process $proc$libresoc.v:197044$13817 + attribute \src "libresoc.v:199334.3-199349.6" + process $proc$libresoc.v:199334$14000 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:197045.5-197045.29" + attribute \src "libresoc.v:199335.5-199335.29" switch \initial - attribute \src "libresoc.v:197045.9-197045.17" + attribute \src "libresoc.v:199335.9-199335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -411251,154 +415245,180 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:197060.3-197140.6" - process $proc$libresoc.v:197060$13818 + attribute \src "libresoc.v:199350.3-199448.6" + process $proc$libresoc.v:199350$14001 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$13819 $10\issue_fsm_state$next[2:0]$13829 - attribute \src "libresoc.v:197061.5-197061.29" + assign $0\issue_fsm_state$next[2:0]$14002 $12\issue_fsm_state$next[2:0]$14014 + attribute \src "libresoc.v:199351.5-199351.29" switch \initial - attribute \src "libresoc.v:197061.9-197061.17" + attribute \src "libresoc.v:199351.9-199351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $2\issue_fsm_state$next[2:0]$13821 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$134 + assign $1\issue_fsm_state$next[2:0]$14003 $2\issue_fsm_state$next[2:0]$14004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$13821 $3\issue_fsm_state$next[2:0]$13822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" + assign $2\issue_fsm_state$next[2:0]$14004 $3\issue_fsm_state$next[2:0]$14005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$13822 3'001 + assign $3\issue_fsm_state$next[2:0]$14005 3'001 case - assign $3\issue_fsm_state$next[2:0]$13822 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$14005 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$13821 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$14004 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $4\issue_fsm_state$next[2:0]$13823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\issue_fsm_state$next[2:0]$14003 $4\issue_fsm_state$next[2:0]$14006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$13823 $5\issue_fsm_state$next[2:0]$13824 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:327" - switch \$138 + assign $4\issue_fsm_state$next[2:0]$14006 $5\issue_fsm_state$next[2:0]$14007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" + switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$13824 3'000 + assign $5\issue_fsm_state$next[2:0]$14007 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$13824 3'010 + assign $5\issue_fsm_state$next[2:0]$14007 3'010 end case - assign $4\issue_fsm_state$next[2:0]$13823 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$14006 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $6\issue_fsm_state$next[2:0]$14008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" + switch \pred_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\issue_fsm_state$next[2:0]$14008 3'100 + case + assign $6\issue_fsm_state$next[2:0]$14008 \issue_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\issue_fsm_state$next[2:0]$14003 $7\issue_fsm_state$next[2:0]$14009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" + switch \pred_mask_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\issue_fsm_state$next[2:0]$14009 3'010 + case + assign $7\issue_fsm_state$next[2:0]$14009 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $6\issue_fsm_state$next[2:0]$13825 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + assign $1\issue_fsm_state$next[2:0]$14003 $8\issue_fsm_state$next[2:0]$14010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$13825 3'011 + assign $8\issue_fsm_state$next[2:0]$14010 3'101 case - assign $6\issue_fsm_state$next[2:0]$13825 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$14010 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 $7\issue_fsm_state$next[2:0]$13826 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$144 + assign $1\issue_fsm_state$next[2:0]$14003 $9\issue_fsm_state$next[2:0]$14011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$150 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$13826 $8\issue_fsm_state$next[2:0]$13827 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + assign $9\issue_fsm_state$next[2:0]$14011 $10\issue_fsm_state$next[2:0]$14012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$13827 $9\issue_fsm_state$next[2:0]$13828 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - switch { \$150 \$146 } + assign $10\issue_fsm_state$next[2:0]$14012 $11\issue_fsm_state$next[2:0]$14013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$156 \$152 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'000 + assign $11\issue_fsm_state$next[2:0]$14013 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'000 + assign $11\issue_fsm_state$next[2:0]$14013 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $9\issue_fsm_state$next[2:0]$13828 3'100 + assign $11\issue_fsm_state$next[2:0]$14013 3'110 end case - assign $8\issue_fsm_state$next[2:0]$13827 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$14012 \issue_fsm_state end case - assign $7\issue_fsm_state$next[2:0]$13826 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$14011 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13820 3'010 + assign $1\issue_fsm_state$next[2:0]$14003 3'010 case - assign $1\issue_fsm_state$next[2:0]$13820 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$14003 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$13829 3'000 + assign $12\issue_fsm_state$next[2:0]$14014 3'000 case - assign $10\issue_fsm_state$next[2:0]$13829 $1\issue_fsm_state$next[2:0]$13820 + assign $12\issue_fsm_state$next[2:0]$14014 $1\issue_fsm_state$next[2:0]$14003 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13819 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$14002 end - attribute \src "libresoc.v:197141.3-197171.6" - process $proc$libresoc.v:197141$13830 + attribute \src "libresoc.v:199449.3-199479.6" + process $proc$libresoc.v:199449$14015 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:197142.5-197142.29" + attribute \src "libresoc.v:199450.5-199450.29" switch \initial - attribute \src "libresoc.v:197142.9-197142.17" + attribute \src "libresoc.v:199450.9-199450.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$162 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_stopped_i[0:0] 1'0 @@ -411408,11 +415428,11 @@ module \ti assign $2\core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\core_stopped_i[0:0] 1'0 @@ -411427,25 +415447,25 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:197172.3-197202.6" - process $proc$libresoc.v:197172$13831 + attribute \src "libresoc.v:199480.3-199510.6" + process $proc$libresoc.v:199480$14016 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:197173.5-197173.29" + attribute \src "libresoc.v:199481.5-199481.29" switch \initial - attribute \src "libresoc.v:197173.9-197173.17" + attribute \src "libresoc.v:199481.9-199481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$174 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dbg_core_stopped_i[0:0] 1'0 @@ -411455,11 +415475,11 @@ module \ti assign $2\dbg_core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$180 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\dbg_core_stopped_i[0:0] 1'0 @@ -411474,132 +415494,132 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:197203.3-197269.6" - process $proc$libresoc.v:197203$13832 + attribute \src "libresoc.v:199511.3-199577.6" + process $proc$libresoc.v:199511$14017 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13833 $9\pc_changed$next[0:0]$13842 - attribute \src "libresoc.v:197204.5-197204.29" + assign $0\pc_changed$next[0:0]$14018 $9\pc_changed$next[0:0]$14027 + attribute \src "libresoc.v:199512.5-199512.29" switch \initial - attribute \src "libresoc.v:197204.9-197204.17" + attribute \src "libresoc.v:199512.9-199512.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13834 $2\pc_changed$next[0:0]$13835 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$180 + assign $1\pc_changed$next[0:0]$14019 $2\pc_changed$next[0:0]$14020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$13835 \pc_changed + assign $2\pc_changed$next[0:0]$14020 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$13835 $3\pc_changed$next[0:0]$13836 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303" + assign $2\pc_changed$next[0:0]$14020 $3\pc_changed$next[0:0]$14021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13836 1'1 + assign $3\pc_changed$next[0:0]$14021 1'1 case - assign $3\pc_changed$next[0:0]$13836 \pc_changed + assign $3\pc_changed$next[0:0]$14021 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\pc_changed$next[0:0]$13834 $4\pc_changed$next[0:0]$13837 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$186 + assign $1\pc_changed$next[0:0]$14019 $4\pc_changed$next[0:0]$14022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$13837 \pc_changed + assign $4\pc_changed$next[0:0]$14022 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$13837 $5\pc_changed$next[0:0]$13838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" + assign $4\pc_changed$next[0:0]$14022 $5\pc_changed$next[0:0]$14023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$13838 1'1 + assign $5\pc_changed$next[0:0]$14023 1'1 case - assign $5\pc_changed$next[0:0]$13838 \pc_changed + assign $5\pc_changed$next[0:0]$14023 \pc_changed end end case - assign $1\pc_changed$next[0:0]$13834 \pc_changed + assign $1\pc_changed$next[0:0]$14019 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$13839 $7\pc_changed$next[0:0]$13840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $6\pc_changed$next[0:0]$14024 $7\pc_changed$next[0:0]$14025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$13840 1'0 + assign $7\pc_changed$next[0:0]$14025 1'0 case - assign $7\pc_changed$next[0:0]$13840 $1\pc_changed$next[0:0]$13834 + assign $7\pc_changed$next[0:0]$14025 $1\pc_changed$next[0:0]$14019 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$13839 $8\pc_changed$next[0:0]$13841 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:456" - switch \$188 + assign $6\pc_changed$next[0:0]$14024 $8\pc_changed$next[0:0]$14026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$13841 1'1 + assign $8\pc_changed$next[0:0]$14026 1'1 case - assign $8\pc_changed$next[0:0]$13841 $1\pc_changed$next[0:0]$13834 + assign $8\pc_changed$next[0:0]$14026 $1\pc_changed$next[0:0]$14019 end case - assign $6\pc_changed$next[0:0]$13839 $1\pc_changed$next[0:0]$13834 + assign $6\pc_changed$next[0:0]$14024 $1\pc_changed$next[0:0]$14019 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$13842 1'0 + assign $9\pc_changed$next[0:0]$14027 1'0 case - assign $9\pc_changed$next[0:0]$13842 $6\pc_changed$next[0:0]$13839 + assign $9\pc_changed$next[0:0]$14027 $6\pc_changed$next[0:0]$14024 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13833 + update \pc_changed$next $0\pc_changed$next[0:0]$14018 end - attribute \src "libresoc.v:197270.3-197326.6" - process $proc$libresoc.v:197270$13843 + attribute \src "libresoc.v:199578.3-199634.6" + process $proc$libresoc.v:199578$14028 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:197271.5-197271.29" + attribute \src "libresoc.v:199579.5-199579.29" switch \initial - attribute \src "libresoc.v:197271.9-197271.17" + attribute \src "libresoc.v:199579.9-199579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$202 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\update_svstate[0:0] 1'0 @@ -411607,7 +415627,7 @@ module \ti case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411618,23 +415638,23 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$208 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - switch { \$208 \$204 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + switch { \$214 \$210 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\update_svstate[0:0] 1'0 @@ -411653,7 +415673,7 @@ module \ti case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -411669,125 +415689,125 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:197327.3-197393.6" - process $proc$libresoc.v:197327$13844 + attribute \src "libresoc.v:199635.3-199701.6" + process $proc$libresoc.v:199635$14029 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$13845 $9\sv_changed$next[0:0]$13854 - attribute \src "libresoc.v:197328.5-197328.29" + assign $0\sv_changed$next[0:0]$14030 $9\sv_changed$next[0:0]$14039 + attribute \src "libresoc.v:199636.5-199636.29" switch \initial - attribute \src "libresoc.v:197328.9-197328.17" + attribute \src "libresoc.v:199636.9-199636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$13846 $2\sv_changed$next[0:0]$13847 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$214 + assign $1\sv_changed$next[0:0]$14031 $2\sv_changed$next[0:0]$14032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" + switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$13847 \sv_changed + assign $2\sv_changed$next[0:0]$14032 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$13847 $3\sv_changed$next[0:0]$13848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + assign $2\sv_changed$next[0:0]$14032 $3\sv_changed$next[0:0]$14033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$13848 1'1 + assign $3\sv_changed$next[0:0]$14033 1'1 case - assign $3\sv_changed$next[0:0]$13848 \sv_changed + assign $3\sv_changed$next[0:0]$14033 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\sv_changed$next[0:0]$13846 $4\sv_changed$next[0:0]$13849 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:346" - switch \$220 + assign $1\sv_changed$next[0:0]$14031 $4\sv_changed$next[0:0]$14034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$13849 \sv_changed + assign $4\sv_changed$next[0:0]$14034 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$13849 $5\sv_changed$next[0:0]$13850 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + assign $4\sv_changed$next[0:0]$14034 $5\sv_changed$next[0:0]$14035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$13850 1'1 + assign $5\sv_changed$next[0:0]$14035 1'1 case - assign $5\sv_changed$next[0:0]$13850 \sv_changed + assign $5\sv_changed$next[0:0]$14035 \sv_changed end end case - assign $1\sv_changed$next[0:0]$13846 \sv_changed + assign $1\sv_changed$next[0:0]$14031 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:437" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$13851 $7\sv_changed$next[0:0]$13852 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:442" + assign $6\sv_changed$next[0:0]$14036 $7\sv_changed$next[0:0]$14037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$13852 1'0 + assign $7\sv_changed$next[0:0]$14037 1'0 case - assign $7\sv_changed$next[0:0]$13852 $1\sv_changed$next[0:0]$13846 + assign $7\sv_changed$next[0:0]$14037 $1\sv_changed$next[0:0]$14031 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$13851 $8\sv_changed$next[0:0]$13853 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:454" - switch \$222 + assign $6\sv_changed$next[0:0]$14036 $8\sv_changed$next[0:0]$14038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$13853 1'1 + assign $8\sv_changed$next[0:0]$14038 1'1 case - assign $8\sv_changed$next[0:0]$13853 $1\sv_changed$next[0:0]$13846 + assign $8\sv_changed$next[0:0]$14038 $1\sv_changed$next[0:0]$14031 end case - assign $6\sv_changed$next[0:0]$13851 $1\sv_changed$next[0:0]$13846 + assign $6\sv_changed$next[0:0]$14036 $1\sv_changed$next[0:0]$14031 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$13854 1'0 + assign $9\sv_changed$next[0:0]$14039 1'0 case - assign $9\sv_changed$next[0:0]$13854 $6\sv_changed$next[0:0]$13851 + assign $9\sv_changed$next[0:0]$14039 $6\sv_changed$next[0:0]$14036 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$13845 + update \sv_changed$next $0\sv_changed$next[0:0]$14030 end - attribute \src "libresoc.v:197394.3-197404.6" - process $proc$libresoc.v:197394$13855 + attribute \src "libresoc.v:199702.3-199712.6" + process $proc$libresoc.v:199702$14040 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:197395.5-197395.29" + attribute \src "libresoc.v:199703.5-199703.29" switch \initial - attribute \src "libresoc.v:197395.9-197395.17" + attribute \src "libresoc.v:199703.9-199703.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -411799,8 +415819,8 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:197405.3-197515.6" - process $proc$libresoc.v:197405$13856 + attribute \src "libresoc.v:199713.3-199823.6" + process $proc$libresoc.v:199713$14041 assign { } { } assign { } { } assign { } { } @@ -411919,11 +415939,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13857 $1\core_asmcode$next[7:0]$13916 - assign $0\core_core_core_cia$next[63:0]$13858 $1\core_core_core_cia$next[63:0]$13917 - assign $0\core_core_core_cr_rd$next[7:0]$13859 $1\core_core_core_cr_rd$next[7:0]$13918 + assign $0\core_asmcode$next[7:0]$14042 $1\core_asmcode$next[7:0]$14101 + assign $0\core_core_core_cia$next[63:0]$14043 $1\core_core_core_cia$next[63:0]$14102 + assign $0\core_core_core_cr_rd$next[7:0]$14044 $1\core_core_core_cr_rd$next[7:0]$14103 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13861 $1\core_core_core_cr_wr$next[7:0]$13920 + assign $0\core_core_core_cr_wr$next[7:0]$14046 $1\core_core_core_cr_wr$next[7:0]$14105 assign { } { } assign { } { } assign { } { } @@ -411932,86 +415952,86 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$13870 $1\core_core_core_fn_unit$next[13:0]$13929 - assign $0\core_core_core_input_carry$next[1:0]$13871 $1\core_core_core_input_carry$next[1:0]$13930 - assign $0\core_core_core_insn$next[31:0]$13872 $1\core_core_core_insn$next[31:0]$13931 - assign $0\core_core_core_insn_type$next[6:0]$13873 $1\core_core_core_insn_type$next[6:0]$13932 - assign $0\core_core_core_is_32bit$next[0:0]$13874 $1\core_core_core_is_32bit$next[0:0]$13933 - assign $0\core_core_core_msr$next[63:0]$13875 $1\core_core_core_msr$next[63:0]$13934 - assign $0\core_core_core_oe$next[0:0]$13876 $1\core_core_core_oe$next[0:0]$13935 + assign $0\core_core_core_fn_unit$next[13:0]$14055 $1\core_core_core_fn_unit$next[13:0]$14114 + assign $0\core_core_core_input_carry$next[1:0]$14056 $1\core_core_core_input_carry$next[1:0]$14115 + assign $0\core_core_core_insn$next[31:0]$14057 $1\core_core_core_insn$next[31:0]$14116 + assign $0\core_core_core_insn_type$next[6:0]$14058 $1\core_core_core_insn_type$next[6:0]$14117 + assign $0\core_core_core_is_32bit$next[0:0]$14059 $1\core_core_core_is_32bit$next[0:0]$14118 + assign $0\core_core_core_msr$next[63:0]$14060 $1\core_core_core_msr$next[63:0]$14119 + assign $0\core_core_core_oe$next[0:0]$14061 $1\core_core_core_oe$next[0:0]$14120 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13878 $1\core_core_core_rc$next[0:0]$13937 + assign $0\core_core_core_rc$next[0:0]$14063 $1\core_core_core_rc$next[0:0]$14122 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13880 $1\core_core_core_trapaddr$next[12:0]$13939 - assign $0\core_core_core_traptype$next[7:0]$13881 $1\core_core_core_traptype$next[7:0]$13940 - assign $0\core_core_cr_in1$next[6:0]$13882 $1\core_core_cr_in1$next[6:0]$13941 + assign $0\core_core_core_trapaddr$next[12:0]$14065 $1\core_core_core_trapaddr$next[12:0]$14124 + assign $0\core_core_core_traptype$next[7:0]$14066 $1\core_core_core_traptype$next[7:0]$14125 + assign $0\core_core_cr_in1$next[6:0]$14067 $1\core_core_cr_in1$next[6:0]$14126 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$13884 $1\core_core_cr_in2$1$next[6:0]$13943 - assign $0\core_core_cr_in2$next[6:0]$13885 $1\core_core_cr_in2$next[6:0]$13944 + assign $0\core_core_cr_in2$1$next[6:0]$14069 $1\core_core_cr_in2$1$next[6:0]$14128 + assign $0\core_core_cr_in2$next[6:0]$14070 $1\core_core_cr_in2$next[6:0]$14129 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$13888 $1\core_core_cr_out$next[6:0]$13947 + assign $0\core_core_cr_out$next[6:0]$14073 $1\core_core_cr_out$next[6:0]$14132 assign { } { } - assign $0\core_core_ea$next[6:0]$13890 $1\core_core_ea$next[6:0]$13949 - assign $0\core_core_fast1$next[2:0]$13891 $1\core_core_fast1$next[2:0]$13950 + assign $0\core_core_ea$next[6:0]$14075 $1\core_core_ea$next[6:0]$14134 + assign $0\core_core_fast1$next[2:0]$14076 $1\core_core_fast1$next[2:0]$14135 assign { } { } - assign $0\core_core_fast2$next[2:0]$13893 $1\core_core_fast2$next[2:0]$13952 + assign $0\core_core_fast2$next[2:0]$14078 $1\core_core_fast2$next[2:0]$14137 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13895 $1\core_core_fasto1$next[2:0]$13954 - assign $0\core_core_fasto2$next[2:0]$13896 $1\core_core_fasto2$next[2:0]$13955 - assign $0\core_core_lk$next[0:0]$13897 $1\core_core_lk$next[0:0]$13956 - assign $0\core_core_reg1$next[6:0]$13898 $1\core_core_reg1$next[6:0]$13957 + assign $0\core_core_fasto1$next[2:0]$14080 $1\core_core_fasto1$next[2:0]$14139 + assign $0\core_core_fasto2$next[2:0]$14081 $1\core_core_fasto2$next[2:0]$14140 + assign $0\core_core_lk$next[0:0]$14082 $1\core_core_lk$next[0:0]$14141 + assign $0\core_core_reg1$next[6:0]$14083 $1\core_core_reg1$next[6:0]$14142 assign { } { } - assign $0\core_core_reg2$next[6:0]$13900 $1\core_core_reg2$next[6:0]$13959 + assign $0\core_core_reg2$next[6:0]$14085 $1\core_core_reg2$next[6:0]$14144 assign { } { } - assign $0\core_core_reg3$next[6:0]$13902 $1\core_core_reg3$next[6:0]$13961 + assign $0\core_core_reg3$next[6:0]$14087 $1\core_core_reg3$next[6:0]$14146 assign { } { } - assign $0\core_core_rego$next[6:0]$13904 $1\core_core_rego$next[6:0]$13963 - assign $0\core_core_spr1$next[9:0]$13905 $1\core_core_spr1$next[9:0]$13964 + assign $0\core_core_rego$next[6:0]$14089 $1\core_core_rego$next[6:0]$14148 + assign $0\core_core_spr1$next[9:0]$14090 $1\core_core_spr1$next[9:0]$14149 assign { } { } - assign $0\core_core_spro$next[9:0]$13907 $1\core_core_spro$next[9:0]$13966 - assign $0\core_core_xer_in$next[2:0]$13908 $1\core_core_xer_in$next[2:0]$13967 + assign $0\core_core_spro$next[9:0]$14092 $1\core_core_spro$next[9:0]$14151 + assign $0\core_core_xer_in$next[2:0]$14093 $1\core_core_xer_in$next[2:0]$14152 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$13915 $1\core_xer_out$next[0:0]$13974 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13860 $3\core_core_core_cr_rd_ok$next[0:0]$14034 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13862 $3\core_core_core_exc_$signal$3$next[0:0]$14035 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13863 $3\core_core_core_exc_$signal$4$next[0:0]$14036 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13864 $3\core_core_core_exc_$signal$5$next[0:0]$14037 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13865 $3\core_core_core_exc_$signal$6$next[0:0]$14038 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13866 $3\core_core_core_exc_$signal$7$next[0:0]$14039 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13867 $3\core_core_core_exc_$signal$8$next[0:0]$14040 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13868 $3\core_core_core_exc_$signal$9$next[0:0]$14041 - assign $0\core_core_core_exc_$signal$next[0:0]$13869 $3\core_core_core_exc_$signal$next[0:0]$14042 - assign $0\core_core_core_oe_ok$next[0:0]$13877 $3\core_core_core_oe_ok$next[0:0]$14043 - assign $0\core_core_core_rc_ok$next[0:0]$13879 $3\core_core_core_rc_ok$next[0:0]$14044 - assign $0\core_core_cr_in1_ok$next[0:0]$13883 $3\core_core_cr_in1_ok$next[0:0]$14045 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13886 $3\core_core_cr_in2_ok$2$next[0:0]$14046 - assign $0\core_core_cr_in2_ok$next[0:0]$13887 $3\core_core_cr_in2_ok$next[0:0]$14047 - assign $0\core_core_cr_wr_ok$next[0:0]$13889 $3\core_core_cr_wr_ok$next[0:0]$14048 - assign $0\core_core_fast1_ok$next[0:0]$13892 $3\core_core_fast1_ok$next[0:0]$14049 - assign $0\core_core_fast2_ok$next[0:0]$13894 $3\core_core_fast2_ok$next[0:0]$14050 - assign $0\core_core_reg1_ok$next[0:0]$13899 $3\core_core_reg1_ok$next[0:0]$14051 - assign $0\core_core_reg2_ok$next[0:0]$13901 $3\core_core_reg2_ok$next[0:0]$14052 - assign $0\core_core_reg3_ok$next[0:0]$13903 $3\core_core_reg3_ok$next[0:0]$14053 - assign $0\core_core_spr1_ok$next[0:0]$13906 $3\core_core_spr1_ok$next[0:0]$14054 - assign $0\core_cr_out_ok$next[0:0]$13909 $3\core_cr_out_ok$next[0:0]$14055 - assign $0\core_ea_ok$next[0:0]$13910 $3\core_ea_ok$next[0:0]$14056 - assign $0\core_fasto1_ok$next[0:0]$13911 $3\core_fasto1_ok$next[0:0]$14057 - assign $0\core_fasto2_ok$next[0:0]$13912 $3\core_fasto2_ok$next[0:0]$14058 - assign $0\core_rego_ok$next[0:0]$13913 $3\core_rego_ok$next[0:0]$14059 - assign $0\core_spro_ok$next[0:0]$13914 $3\core_spro_ok$next[0:0]$14060 - attribute \src "libresoc.v:197406.5-197406.29" + assign $0\core_xer_out$next[0:0]$14100 $1\core_xer_out$next[0:0]$14159 + assign $0\core_core_core_cr_rd_ok$next[0:0]$14045 $3\core_core_core_cr_rd_ok$next[0:0]$14219 + assign $0\core_core_core_exc_$signal$3$next[0:0]$14047 $3\core_core_core_exc_$signal$3$next[0:0]$14220 + assign $0\core_core_core_exc_$signal$4$next[0:0]$14048 $3\core_core_core_exc_$signal$4$next[0:0]$14221 + assign $0\core_core_core_exc_$signal$5$next[0:0]$14049 $3\core_core_core_exc_$signal$5$next[0:0]$14222 + assign $0\core_core_core_exc_$signal$6$next[0:0]$14050 $3\core_core_core_exc_$signal$6$next[0:0]$14223 + assign $0\core_core_core_exc_$signal$7$next[0:0]$14051 $3\core_core_core_exc_$signal$7$next[0:0]$14224 + assign $0\core_core_core_exc_$signal$8$next[0:0]$14052 $3\core_core_core_exc_$signal$8$next[0:0]$14225 + assign $0\core_core_core_exc_$signal$9$next[0:0]$14053 $3\core_core_core_exc_$signal$9$next[0:0]$14226 + assign $0\core_core_core_exc_$signal$next[0:0]$14054 $3\core_core_core_exc_$signal$next[0:0]$14227 + assign $0\core_core_core_oe_ok$next[0:0]$14062 $3\core_core_core_oe_ok$next[0:0]$14228 + assign $0\core_core_core_rc_ok$next[0:0]$14064 $3\core_core_core_rc_ok$next[0:0]$14229 + assign $0\core_core_cr_in1_ok$next[0:0]$14068 $3\core_core_cr_in1_ok$next[0:0]$14230 + assign $0\core_core_cr_in2_ok$2$next[0:0]$14071 $3\core_core_cr_in2_ok$2$next[0:0]$14231 + assign $0\core_core_cr_in2_ok$next[0:0]$14072 $3\core_core_cr_in2_ok$next[0:0]$14232 + assign $0\core_core_cr_wr_ok$next[0:0]$14074 $3\core_core_cr_wr_ok$next[0:0]$14233 + assign $0\core_core_fast1_ok$next[0:0]$14077 $3\core_core_fast1_ok$next[0:0]$14234 + assign $0\core_core_fast2_ok$next[0:0]$14079 $3\core_core_fast2_ok$next[0:0]$14235 + assign $0\core_core_reg1_ok$next[0:0]$14084 $3\core_core_reg1_ok$next[0:0]$14236 + assign $0\core_core_reg2_ok$next[0:0]$14086 $3\core_core_reg2_ok$next[0:0]$14237 + assign $0\core_core_reg3_ok$next[0:0]$14088 $3\core_core_reg3_ok$next[0:0]$14238 + assign $0\core_core_spr1_ok$next[0:0]$14091 $3\core_core_spr1_ok$next[0:0]$14239 + assign $0\core_cr_out_ok$next[0:0]$14094 $3\core_cr_out_ok$next[0:0]$14240 + assign $0\core_ea_ok$next[0:0]$14095 $3\core_ea_ok$next[0:0]$14241 + assign $0\core_fasto1_ok$next[0:0]$14096 $3\core_fasto1_ok$next[0:0]$14242 + assign $0\core_fasto2_ok$next[0:0]$14097 $3\core_fasto2_ok$next[0:0]$14243 + assign $0\core_rego_ok$next[0:0]$14098 $3\core_rego_ok$next[0:0]$14244 + assign $0\core_spro_ok$next[0:0]$14099 $3\core_spro_ok$next[0:0]$14245 + attribute \src "libresoc.v:199714.5-199714.29" switch \initial - attribute \src "libresoc.v:197406.9-197406.17" + attribute \src "libresoc.v:199714.9-199714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -412074,66 +416094,66 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13916 $2\core_asmcode$next[7:0]$13975 - assign $1\core_core_core_cia$next[63:0]$13917 $2\core_core_core_cia$next[63:0]$13976 - assign $1\core_core_core_cr_rd$next[7:0]$13918 $2\core_core_core_cr_rd$next[7:0]$13977 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 $2\core_core_core_cr_rd_ok$next[0:0]$13978 - assign $1\core_core_core_cr_wr$next[7:0]$13920 $2\core_core_core_cr_wr$next[7:0]$13979 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 $2\core_core_core_exc_$signal$3$next[0:0]$13980 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 $2\core_core_core_exc_$signal$4$next[0:0]$13981 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 $2\core_core_core_exc_$signal$5$next[0:0]$13982 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 $2\core_core_core_exc_$signal$6$next[0:0]$13983 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 $2\core_core_core_exc_$signal$7$next[0:0]$13984 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 $2\core_core_core_exc_$signal$8$next[0:0]$13985 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 $2\core_core_core_exc_$signal$9$next[0:0]$13986 - assign $1\core_core_core_exc_$signal$next[0:0]$13928 $2\core_core_core_exc_$signal$next[0:0]$13987 - assign $1\core_core_core_fn_unit$next[13:0]$13929 $2\core_core_core_fn_unit$next[13:0]$13988 - assign $1\core_core_core_input_carry$next[1:0]$13930 $2\core_core_core_input_carry$next[1:0]$13989 - assign $1\core_core_core_insn$next[31:0]$13931 $2\core_core_core_insn$next[31:0]$13990 - assign $1\core_core_core_insn_type$next[6:0]$13932 $2\core_core_core_insn_type$next[6:0]$13991 - assign $1\core_core_core_is_32bit$next[0:0]$13933 $2\core_core_core_is_32bit$next[0:0]$13992 - assign $1\core_core_core_msr$next[63:0]$13934 $2\core_core_core_msr$next[63:0]$13993 - assign $1\core_core_core_oe$next[0:0]$13935 $2\core_core_core_oe$next[0:0]$13994 - assign $1\core_core_core_oe_ok$next[0:0]$13936 $2\core_core_core_oe_ok$next[0:0]$13995 - assign $1\core_core_core_rc$next[0:0]$13937 $2\core_core_core_rc$next[0:0]$13996 - assign $1\core_core_core_rc_ok$next[0:0]$13938 $2\core_core_core_rc_ok$next[0:0]$13997 - assign $1\core_core_core_trapaddr$next[12:0]$13939 $2\core_core_core_trapaddr$next[12:0]$13998 - assign $1\core_core_core_traptype$next[7:0]$13940 $2\core_core_core_traptype$next[7:0]$13999 - assign $1\core_core_cr_in1$next[6:0]$13941 $2\core_core_cr_in1$next[6:0]$14000 - assign $1\core_core_cr_in1_ok$next[0:0]$13942 $2\core_core_cr_in1_ok$next[0:0]$14001 - assign $1\core_core_cr_in2$1$next[6:0]$13943 $2\core_core_cr_in2$1$next[6:0]$14002 - assign $1\core_core_cr_in2$next[6:0]$13944 $2\core_core_cr_in2$next[6:0]$14003 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 $2\core_core_cr_in2_ok$2$next[0:0]$14004 - assign $1\core_core_cr_in2_ok$next[0:0]$13946 $2\core_core_cr_in2_ok$next[0:0]$14005 - assign $1\core_core_cr_out$next[6:0]$13947 $2\core_core_cr_out$next[6:0]$14006 - assign $1\core_core_cr_wr_ok$next[0:0]$13948 $2\core_core_cr_wr_ok$next[0:0]$14007 - assign $1\core_core_ea$next[6:0]$13949 $2\core_core_ea$next[6:0]$14008 - assign $1\core_core_fast1$next[2:0]$13950 $2\core_core_fast1$next[2:0]$14009 - assign $1\core_core_fast1_ok$next[0:0]$13951 $2\core_core_fast1_ok$next[0:0]$14010 - assign $1\core_core_fast2$next[2:0]$13952 $2\core_core_fast2$next[2:0]$14011 - assign $1\core_core_fast2_ok$next[0:0]$13953 $2\core_core_fast2_ok$next[0:0]$14012 - assign $1\core_core_fasto1$next[2:0]$13954 $2\core_core_fasto1$next[2:0]$14013 - assign $1\core_core_fasto2$next[2:0]$13955 $2\core_core_fasto2$next[2:0]$14014 - assign $1\core_core_lk$next[0:0]$13956 $2\core_core_lk$next[0:0]$14015 - assign $1\core_core_reg1$next[6:0]$13957 $2\core_core_reg1$next[6:0]$14016 - assign $1\core_core_reg1_ok$next[0:0]$13958 $2\core_core_reg1_ok$next[0:0]$14017 - assign $1\core_core_reg2$next[6:0]$13959 $2\core_core_reg2$next[6:0]$14018 - assign $1\core_core_reg2_ok$next[0:0]$13960 $2\core_core_reg2_ok$next[0:0]$14019 - assign $1\core_core_reg3$next[6:0]$13961 $2\core_core_reg3$next[6:0]$14020 - assign $1\core_core_reg3_ok$next[0:0]$13962 $2\core_core_reg3_ok$next[0:0]$14021 - assign $1\core_core_rego$next[6:0]$13963 $2\core_core_rego$next[6:0]$14022 - assign $1\core_core_spr1$next[9:0]$13964 $2\core_core_spr1$next[9:0]$14023 - assign $1\core_core_spr1_ok$next[0:0]$13965 $2\core_core_spr1_ok$next[0:0]$14024 - assign $1\core_core_spro$next[9:0]$13966 $2\core_core_spro$next[9:0]$14025 - assign $1\core_core_xer_in$next[2:0]$13967 $2\core_core_xer_in$next[2:0]$14026 - assign $1\core_cr_out_ok$next[0:0]$13968 $2\core_cr_out_ok$next[0:0]$14027 - assign $1\core_ea_ok$next[0:0]$13969 $2\core_ea_ok$next[0:0]$14028 - assign $1\core_fasto1_ok$next[0:0]$13970 $2\core_fasto1_ok$next[0:0]$14029 - assign $1\core_fasto2_ok$next[0:0]$13971 $2\core_fasto2_ok$next[0:0]$14030 - assign $1\core_rego_ok$next[0:0]$13972 $2\core_rego_ok$next[0:0]$14031 - assign $1\core_spro_ok$next[0:0]$13973 $2\core_spro_ok$next[0:0]$14032 - assign $1\core_xer_out$next[0:0]$13974 $2\core_xer_out$next[0:0]$14033 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + assign $1\core_asmcode$next[7:0]$14101 $2\core_asmcode$next[7:0]$14160 + assign $1\core_core_core_cia$next[63:0]$14102 $2\core_core_core_cia$next[63:0]$14161 + assign $1\core_core_core_cr_rd$next[7:0]$14103 $2\core_core_core_cr_rd$next[7:0]$14162 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 $2\core_core_core_cr_rd_ok$next[0:0]$14163 + assign $1\core_core_core_cr_wr$next[7:0]$14105 $2\core_core_core_cr_wr$next[7:0]$14164 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 $2\core_core_core_exc_$signal$3$next[0:0]$14165 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 $2\core_core_core_exc_$signal$4$next[0:0]$14166 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 $2\core_core_core_exc_$signal$5$next[0:0]$14167 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 $2\core_core_core_exc_$signal$6$next[0:0]$14168 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 $2\core_core_core_exc_$signal$7$next[0:0]$14169 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 $2\core_core_core_exc_$signal$8$next[0:0]$14170 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 $2\core_core_core_exc_$signal$9$next[0:0]$14171 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 $2\core_core_core_exc_$signal$next[0:0]$14172 + assign $1\core_core_core_fn_unit$next[13:0]$14114 $2\core_core_core_fn_unit$next[13:0]$14173 + assign $1\core_core_core_input_carry$next[1:0]$14115 $2\core_core_core_input_carry$next[1:0]$14174 + assign $1\core_core_core_insn$next[31:0]$14116 $2\core_core_core_insn$next[31:0]$14175 + assign $1\core_core_core_insn_type$next[6:0]$14117 $2\core_core_core_insn_type$next[6:0]$14176 + assign $1\core_core_core_is_32bit$next[0:0]$14118 $2\core_core_core_is_32bit$next[0:0]$14177 + assign $1\core_core_core_msr$next[63:0]$14119 $2\core_core_core_msr$next[63:0]$14178 + assign $1\core_core_core_oe$next[0:0]$14120 $2\core_core_core_oe$next[0:0]$14179 + assign $1\core_core_core_oe_ok$next[0:0]$14121 $2\core_core_core_oe_ok$next[0:0]$14180 + assign $1\core_core_core_rc$next[0:0]$14122 $2\core_core_core_rc$next[0:0]$14181 + assign $1\core_core_core_rc_ok$next[0:0]$14123 $2\core_core_core_rc_ok$next[0:0]$14182 + assign $1\core_core_core_trapaddr$next[12:0]$14124 $2\core_core_core_trapaddr$next[12:0]$14183 + assign $1\core_core_core_traptype$next[7:0]$14125 $2\core_core_core_traptype$next[7:0]$14184 + assign $1\core_core_cr_in1$next[6:0]$14126 $2\core_core_cr_in1$next[6:0]$14185 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 $2\core_core_cr_in1_ok$next[0:0]$14186 + assign $1\core_core_cr_in2$1$next[6:0]$14128 $2\core_core_cr_in2$1$next[6:0]$14187 + assign $1\core_core_cr_in2$next[6:0]$14129 $2\core_core_cr_in2$next[6:0]$14188 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 $2\core_core_cr_in2_ok$2$next[0:0]$14189 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 $2\core_core_cr_in2_ok$next[0:0]$14190 + assign $1\core_core_cr_out$next[6:0]$14132 $2\core_core_cr_out$next[6:0]$14191 + assign $1\core_core_cr_wr_ok$next[0:0]$14133 $2\core_core_cr_wr_ok$next[0:0]$14192 + assign $1\core_core_ea$next[6:0]$14134 $2\core_core_ea$next[6:0]$14193 + assign $1\core_core_fast1$next[2:0]$14135 $2\core_core_fast1$next[2:0]$14194 + assign $1\core_core_fast1_ok$next[0:0]$14136 $2\core_core_fast1_ok$next[0:0]$14195 + assign $1\core_core_fast2$next[2:0]$14137 $2\core_core_fast2$next[2:0]$14196 + assign $1\core_core_fast2_ok$next[0:0]$14138 $2\core_core_fast2_ok$next[0:0]$14197 + assign $1\core_core_fasto1$next[2:0]$14139 $2\core_core_fasto1$next[2:0]$14198 + assign $1\core_core_fasto2$next[2:0]$14140 $2\core_core_fasto2$next[2:0]$14199 + assign $1\core_core_lk$next[0:0]$14141 $2\core_core_lk$next[0:0]$14200 + assign $1\core_core_reg1$next[6:0]$14142 $2\core_core_reg1$next[6:0]$14201 + assign $1\core_core_reg1_ok$next[0:0]$14143 $2\core_core_reg1_ok$next[0:0]$14202 + assign $1\core_core_reg2$next[6:0]$14144 $2\core_core_reg2$next[6:0]$14203 + assign $1\core_core_reg2_ok$next[0:0]$14145 $2\core_core_reg2_ok$next[0:0]$14204 + assign $1\core_core_reg3$next[6:0]$14146 $2\core_core_reg3$next[6:0]$14205 + assign $1\core_core_reg3_ok$next[0:0]$14147 $2\core_core_reg3_ok$next[0:0]$14206 + assign $1\core_core_rego$next[6:0]$14148 $2\core_core_rego$next[6:0]$14207 + assign $1\core_core_spr1$next[9:0]$14149 $2\core_core_spr1$next[9:0]$14208 + assign $1\core_core_spr1_ok$next[0:0]$14150 $2\core_core_spr1_ok$next[0:0]$14209 + assign $1\core_core_spro$next[9:0]$14151 $2\core_core_spro$next[9:0]$14210 + assign $1\core_core_xer_in$next[2:0]$14152 $2\core_core_xer_in$next[2:0]$14211 + assign $1\core_cr_out_ok$next[0:0]$14153 $2\core_cr_out_ok$next[0:0]$14212 + assign $1\core_ea_ok$next[0:0]$14154 $2\core_ea_ok$next[0:0]$14213 + assign $1\core_fasto1_ok$next[0:0]$14155 $2\core_fasto1_ok$next[0:0]$14214 + assign $1\core_fasto2_ok$next[0:0]$14156 $2\core_fasto2_ok$next[0:0]$14215 + assign $1\core_rego_ok$next[0:0]$14157 $2\core_rego_ok$next[0:0]$14216 + assign $1\core_spro_ok$next[0:0]$14158 $2\core_spro_ok$next[0:0]$14217 + assign $1\core_xer_out$next[0:0]$14159 $2\core_xer_out$next[0:0]$14218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -412196,70 +416216,70 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13992 $2\core_core_cr_wr_ok$next[0:0]$14007 $2\core_core_core_cr_wr$next[7:0]$13979 $2\core_core_core_cr_rd_ok$next[0:0]$13978 $2\core_core_core_cr_rd$next[7:0]$13977 $2\core_core_core_trapaddr$next[12:0]$13998 $2\core_core_core_exc_$signal$9$next[0:0]$13986 $2\core_core_core_exc_$signal$8$next[0:0]$13985 $2\core_core_core_exc_$signal$7$next[0:0]$13984 $2\core_core_core_exc_$signal$6$next[0:0]$13983 $2\core_core_core_exc_$signal$5$next[0:0]$13982 $2\core_core_core_exc_$signal$4$next[0:0]$13981 $2\core_core_core_exc_$signal$3$next[0:0]$13980 $2\core_core_core_exc_$signal$next[0:0]$13987 $2\core_core_core_traptype$next[7:0]$13999 $2\core_core_core_input_carry$next[1:0]$13989 $2\core_core_core_oe_ok$next[0:0]$13995 $2\core_core_core_oe$next[0:0]$13994 $2\core_core_core_rc_ok$next[0:0]$13997 $2\core_core_core_rc$next[0:0]$13996 $2\core_core_lk$next[0:0]$14015 $2\core_core_core_fn_unit$next[13:0]$13988 $2\core_core_core_insn_type$next[6:0]$13991 $2\core_core_core_insn$next[31:0]$13990 $2\core_core_core_cia$next[63:0]$13976 $2\core_core_core_msr$next[63:0]$13993 $2\core_cr_out_ok$next[0:0]$14027 $2\core_core_cr_out$next[6:0]$14006 $2\core_core_cr_in2_ok$2$next[0:0]$14004 $2\core_core_cr_in2$1$next[6:0]$14002 $2\core_core_cr_in2_ok$next[0:0]$14005 $2\core_core_cr_in2$next[6:0]$14003 $2\core_core_cr_in1_ok$next[0:0]$14001 $2\core_core_cr_in1$next[6:0]$14000 $2\core_fasto2_ok$next[0:0]$14030 $2\core_core_fasto2$next[2:0]$14014 $2\core_fasto1_ok$next[0:0]$14029 $2\core_core_fasto1$next[2:0]$14013 $2\core_core_fast2_ok$next[0:0]$14012 $2\core_core_fast2$next[2:0]$14011 $2\core_core_fast1_ok$next[0:0]$14010 $2\core_core_fast1$next[2:0]$14009 $2\core_xer_out$next[0:0]$14033 $2\core_core_xer_in$next[2:0]$14026 $2\core_core_spr1_ok$next[0:0]$14024 $2\core_core_spr1$next[9:0]$14023 $2\core_spro_ok$next[0:0]$14032 $2\core_core_spro$next[9:0]$14025 $2\core_core_reg3_ok$next[0:0]$14021 $2\core_core_reg3$next[6:0]$14020 $2\core_core_reg2_ok$next[0:0]$14019 $2\core_core_reg2$next[6:0]$14018 $2\core_core_reg1_ok$next[0:0]$14017 $2\core_core_reg1$next[6:0]$14016 $2\core_ea_ok$next[0:0]$14028 $2\core_core_ea$next[6:0]$14008 $2\core_rego_ok$next[0:0]$14031 $2\core_core_rego$next[6:0]$14022 $2\core_asmcode$next[7:0]$13975 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$14177 $2\core_core_cr_wr_ok$next[0:0]$14192 $2\core_core_core_cr_wr$next[7:0]$14164 $2\core_core_core_cr_rd_ok$next[0:0]$14163 $2\core_core_core_cr_rd$next[7:0]$14162 $2\core_core_core_trapaddr$next[12:0]$14183 $2\core_core_core_exc_$signal$9$next[0:0]$14171 $2\core_core_core_exc_$signal$8$next[0:0]$14170 $2\core_core_core_exc_$signal$7$next[0:0]$14169 $2\core_core_core_exc_$signal$6$next[0:0]$14168 $2\core_core_core_exc_$signal$5$next[0:0]$14167 $2\core_core_core_exc_$signal$4$next[0:0]$14166 $2\core_core_core_exc_$signal$3$next[0:0]$14165 $2\core_core_core_exc_$signal$next[0:0]$14172 $2\core_core_core_traptype$next[7:0]$14184 $2\core_core_core_input_carry$next[1:0]$14174 $2\core_core_core_oe_ok$next[0:0]$14180 $2\core_core_core_oe$next[0:0]$14179 $2\core_core_core_rc_ok$next[0:0]$14182 $2\core_core_core_rc$next[0:0]$14181 $2\core_core_lk$next[0:0]$14200 $2\core_core_core_fn_unit$next[13:0]$14173 $2\core_core_core_insn_type$next[6:0]$14176 $2\core_core_core_insn$next[31:0]$14175 $2\core_core_core_cia$next[63:0]$14161 $2\core_core_core_msr$next[63:0]$14178 $2\core_cr_out_ok$next[0:0]$14212 $2\core_core_cr_out$next[6:0]$14191 $2\core_core_cr_in2_ok$2$next[0:0]$14189 $2\core_core_cr_in2$1$next[6:0]$14187 $2\core_core_cr_in2_ok$next[0:0]$14190 $2\core_core_cr_in2$next[6:0]$14188 $2\core_core_cr_in1_ok$next[0:0]$14186 $2\core_core_cr_in1$next[6:0]$14185 $2\core_fasto2_ok$next[0:0]$14215 $2\core_core_fasto2$next[2:0]$14199 $2\core_fasto1_ok$next[0:0]$14214 $2\core_core_fasto1$next[2:0]$14198 $2\core_core_fast2_ok$next[0:0]$14197 $2\core_core_fast2$next[2:0]$14196 $2\core_core_fast1_ok$next[0:0]$14195 $2\core_core_fast1$next[2:0]$14194 $2\core_xer_out$next[0:0]$14218 $2\core_core_xer_in$next[2:0]$14211 $2\core_core_spr1_ok$next[0:0]$14209 $2\core_core_spr1$next[9:0]$14208 $2\core_spro_ok$next[0:0]$14217 $2\core_core_spro$next[9:0]$14210 $2\core_core_reg3_ok$next[0:0]$14206 $2\core_core_reg3$next[6:0]$14205 $2\core_core_reg2_ok$next[0:0]$14204 $2\core_core_reg2$next[6:0]$14203 $2\core_core_reg1_ok$next[0:0]$14202 $2\core_core_reg1$next[6:0]$14201 $2\core_ea_ok$next[0:0]$14213 $2\core_core_ea$next[6:0]$14193 $2\core_rego_ok$next[0:0]$14216 $2\core_core_rego$next[6:0]$14207 $2\core_asmcode$next[7:0]$14160 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$13975 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13976 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13977 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13978 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13979 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13980 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13981 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13982 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13983 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13984 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13985 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13986 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13987 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$13988 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13989 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13990 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13991 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13992 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13993 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13994 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13995 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13996 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13997 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13998 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13999 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14000 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14001 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14002 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14003 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14004 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14005 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14006 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14007 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14008 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14009 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14010 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14011 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14012 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14013 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14014 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14015 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14016 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14017 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14018 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14019 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14020 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14021 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14022 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14023 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14024 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14025 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14026 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14027 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14028 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14029 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14030 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14031 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14032 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14033 \core_xer_out + assign $2\core_asmcode$next[7:0]$14160 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14161 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14162 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14163 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14164 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14165 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14166 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14167 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14168 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14169 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14170 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14171 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14172 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$14173 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14174 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14175 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14176 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14177 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14178 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14179 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14180 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14181 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14182 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14183 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14184 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14185 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14186 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14187 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14188 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14189 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14190 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14191 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14192 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14193 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14194 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14195 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14196 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14197 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14198 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14199 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14200 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14201 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14202 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14203 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14204 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14205 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14206 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14207 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14208 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14209 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14210 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14211 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14212 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14213 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14214 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14215 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14216 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14217 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14218 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } assign { } { } assign { } { } @@ -412319,67 +416339,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13933 $1\core_core_cr_wr_ok$next[0:0]$13948 $1\core_core_core_cr_wr$next[7:0]$13920 $1\core_core_core_cr_rd_ok$next[0:0]$13919 $1\core_core_core_cr_rd$next[7:0]$13918 $1\core_core_core_trapaddr$next[12:0]$13939 $1\core_core_core_exc_$signal$9$next[0:0]$13927 $1\core_core_core_exc_$signal$8$next[0:0]$13926 $1\core_core_core_exc_$signal$7$next[0:0]$13925 $1\core_core_core_exc_$signal$6$next[0:0]$13924 $1\core_core_core_exc_$signal$5$next[0:0]$13923 $1\core_core_core_exc_$signal$4$next[0:0]$13922 $1\core_core_core_exc_$signal$3$next[0:0]$13921 $1\core_core_core_exc_$signal$next[0:0]$13928 $1\core_core_core_traptype$next[7:0]$13940 $1\core_core_core_input_carry$next[1:0]$13930 $1\core_core_core_oe_ok$next[0:0]$13936 $1\core_core_core_oe$next[0:0]$13935 $1\core_core_core_rc_ok$next[0:0]$13938 $1\core_core_core_rc$next[0:0]$13937 $1\core_core_lk$next[0:0]$13956 $1\core_core_core_fn_unit$next[13:0]$13929 $1\core_core_core_insn_type$next[6:0]$13932 $1\core_core_core_insn$next[31:0]$13931 $1\core_core_core_cia$next[63:0]$13917 $1\core_core_core_msr$next[63:0]$13934 $1\core_cr_out_ok$next[0:0]$13968 $1\core_core_cr_out$next[6:0]$13947 $1\core_core_cr_in2_ok$2$next[0:0]$13945 $1\core_core_cr_in2$1$next[6:0]$13943 $1\core_core_cr_in2_ok$next[0:0]$13946 $1\core_core_cr_in2$next[6:0]$13944 $1\core_core_cr_in1_ok$next[0:0]$13942 $1\core_core_cr_in1$next[6:0]$13941 $1\core_fasto2_ok$next[0:0]$13971 $1\core_core_fasto2$next[2:0]$13955 $1\core_fasto1_ok$next[0:0]$13970 $1\core_core_fasto1$next[2:0]$13954 $1\core_core_fast2_ok$next[0:0]$13953 $1\core_core_fast2$next[2:0]$13952 $1\core_core_fast1_ok$next[0:0]$13951 $1\core_core_fast1$next[2:0]$13950 $1\core_xer_out$next[0:0]$13974 $1\core_core_xer_in$next[2:0]$13967 $1\core_core_spr1_ok$next[0:0]$13965 $1\core_core_spr1$next[9:0]$13964 $1\core_spro_ok$next[0:0]$13973 $1\core_core_spro$next[9:0]$13966 $1\core_core_reg3_ok$next[0:0]$13962 $1\core_core_reg3$next[6:0]$13961 $1\core_core_reg2_ok$next[0:0]$13960 $1\core_core_reg2$next[6:0]$13959 $1\core_core_reg1_ok$next[0:0]$13958 $1\core_core_reg1$next[6:0]$13957 $1\core_ea_ok$next[0:0]$13969 $1\core_core_ea$next[6:0]$13949 $1\core_rego_ok$next[0:0]$13972 $1\core_core_rego$next[6:0]$13963 $1\core_asmcode$next[7:0]$13916 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$14118 $1\core_core_cr_wr_ok$next[0:0]$14133 $1\core_core_core_cr_wr$next[7:0]$14105 $1\core_core_core_cr_rd_ok$next[0:0]$14104 $1\core_core_core_cr_rd$next[7:0]$14103 $1\core_core_core_trapaddr$next[12:0]$14124 $1\core_core_core_exc_$signal$9$next[0:0]$14112 $1\core_core_core_exc_$signal$8$next[0:0]$14111 $1\core_core_core_exc_$signal$7$next[0:0]$14110 $1\core_core_core_exc_$signal$6$next[0:0]$14109 $1\core_core_core_exc_$signal$5$next[0:0]$14108 $1\core_core_core_exc_$signal$4$next[0:0]$14107 $1\core_core_core_exc_$signal$3$next[0:0]$14106 $1\core_core_core_exc_$signal$next[0:0]$14113 $1\core_core_core_traptype$next[7:0]$14125 $1\core_core_core_input_carry$next[1:0]$14115 $1\core_core_core_oe_ok$next[0:0]$14121 $1\core_core_core_oe$next[0:0]$14120 $1\core_core_core_rc_ok$next[0:0]$14123 $1\core_core_core_rc$next[0:0]$14122 $1\core_core_lk$next[0:0]$14141 $1\core_core_core_fn_unit$next[13:0]$14114 $1\core_core_core_insn_type$next[6:0]$14117 $1\core_core_core_insn$next[31:0]$14116 $1\core_core_core_cia$next[63:0]$14102 $1\core_core_core_msr$next[63:0]$14119 $1\core_cr_out_ok$next[0:0]$14153 $1\core_core_cr_out$next[6:0]$14132 $1\core_core_cr_in2_ok$2$next[0:0]$14130 $1\core_core_cr_in2$1$next[6:0]$14128 $1\core_core_cr_in2_ok$next[0:0]$14131 $1\core_core_cr_in2$next[6:0]$14129 $1\core_core_cr_in1_ok$next[0:0]$14127 $1\core_core_cr_in1$next[6:0]$14126 $1\core_fasto2_ok$next[0:0]$14156 $1\core_core_fasto2$next[2:0]$14140 $1\core_fasto1_ok$next[0:0]$14155 $1\core_core_fasto1$next[2:0]$14139 $1\core_core_fast2_ok$next[0:0]$14138 $1\core_core_fast2$next[2:0]$14137 $1\core_core_fast1_ok$next[0:0]$14136 $1\core_core_fast1$next[2:0]$14135 $1\core_xer_out$next[0:0]$14159 $1\core_core_xer_in$next[2:0]$14152 $1\core_core_spr1_ok$next[0:0]$14150 $1\core_core_spr1$next[9:0]$14149 $1\core_spro_ok$next[0:0]$14158 $1\core_core_spro$next[9:0]$14151 $1\core_core_reg3_ok$next[0:0]$14147 $1\core_core_reg3$next[6:0]$14146 $1\core_core_reg2_ok$next[0:0]$14145 $1\core_core_reg2$next[6:0]$14144 $1\core_core_reg1_ok$next[0:0]$14143 $1\core_core_reg1$next[6:0]$14142 $1\core_ea_ok$next[0:0]$14154 $1\core_core_ea$next[6:0]$14134 $1\core_rego_ok$next[0:0]$14157 $1\core_core_rego$next[6:0]$14148 $1\core_asmcode$next[7:0]$14101 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$13916 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13917 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13918 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13919 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13920 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13921 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13922 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13923 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13924 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13925 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13926 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13927 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13928 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$13929 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13930 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13931 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13932 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13933 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13934 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13935 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13936 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13937 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13938 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13939 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13940 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$13941 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13942 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$13943 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$13944 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13945 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13946 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$13947 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13948 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$13949 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13950 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13951 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13952 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13953 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13954 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13955 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13956 \core_core_lk - assign $1\core_core_reg1$next[6:0]$13957 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13958 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$13959 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13960 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$13961 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13962 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$13963 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13964 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13965 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13966 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13967 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13968 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13969 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13970 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13971 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13972 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13973 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13974 \core_xer_out + assign $1\core_asmcode$next[7:0]$14101 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14102 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14103 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14105 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14113 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14114 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14115 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14116 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14117 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14118 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14119 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14120 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14121 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14122 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14123 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14124 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14125 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14126 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14127 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14128 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14129 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14131 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14132 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14133 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14134 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14135 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14136 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14137 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14138 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14139 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14140 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14141 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14142 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14143 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14144 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14145 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14146 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14147 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14148 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14149 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14150 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14151 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14152 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14153 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14154 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14155 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14156 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14157 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14158 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14159 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -412412,255 +416432,258 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$14059 1'0 - assign $3\core_ea_ok$next[0:0]$14056 1'0 - assign $3\core_core_reg1_ok$next[0:0]$14051 1'0 - assign $3\core_core_reg2_ok$next[0:0]$14052 1'0 - assign $3\core_core_reg3_ok$next[0:0]$14053 1'0 - assign $3\core_spro_ok$next[0:0]$14060 1'0 - assign $3\core_core_spr1_ok$next[0:0]$14054 1'0 - assign $3\core_core_fast1_ok$next[0:0]$14049 1'0 - assign $3\core_core_fast2_ok$next[0:0]$14050 1'0 - assign $3\core_fasto1_ok$next[0:0]$14057 1'0 - assign $3\core_fasto2_ok$next[0:0]$14058 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$14045 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$14047 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 1'0 - assign $3\core_cr_out_ok$next[0:0]$14055 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$14044 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$14043 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$14042 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$14048 1'0 - case - assign $3\core_core_core_cr_rd_ok$next[0:0]$14034 $1\core_core_core_cr_rd_ok$next[0:0]$13919 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$13921 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$13922 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$13923 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$13924 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$13925 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$13926 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14041 $1\core_core_core_exc_$signal$9$next[0:0]$13927 - assign $3\core_core_core_exc_$signal$next[0:0]$14042 $1\core_core_core_exc_$signal$next[0:0]$13928 - assign $3\core_core_core_oe_ok$next[0:0]$14043 $1\core_core_core_oe_ok$next[0:0]$13936 - assign $3\core_core_core_rc_ok$next[0:0]$14044 $1\core_core_core_rc_ok$next[0:0]$13938 - assign $3\core_core_cr_in1_ok$next[0:0]$14045 $1\core_core_cr_in1_ok$next[0:0]$13942 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14046 $1\core_core_cr_in2_ok$2$next[0:0]$13945 - assign $3\core_core_cr_in2_ok$next[0:0]$14047 $1\core_core_cr_in2_ok$next[0:0]$13946 - assign $3\core_core_cr_wr_ok$next[0:0]$14048 $1\core_core_cr_wr_ok$next[0:0]$13948 - assign $3\core_core_fast1_ok$next[0:0]$14049 $1\core_core_fast1_ok$next[0:0]$13951 - assign $3\core_core_fast2_ok$next[0:0]$14050 $1\core_core_fast2_ok$next[0:0]$13953 - assign $3\core_core_reg1_ok$next[0:0]$14051 $1\core_core_reg1_ok$next[0:0]$13958 - assign $3\core_core_reg2_ok$next[0:0]$14052 $1\core_core_reg2_ok$next[0:0]$13960 - assign $3\core_core_reg3_ok$next[0:0]$14053 $1\core_core_reg3_ok$next[0:0]$13962 - assign $3\core_core_spr1_ok$next[0:0]$14054 $1\core_core_spr1_ok$next[0:0]$13965 - assign $3\core_cr_out_ok$next[0:0]$14055 $1\core_cr_out_ok$next[0:0]$13968 - assign $3\core_ea_ok$next[0:0]$14056 $1\core_ea_ok$next[0:0]$13969 - assign $3\core_fasto1_ok$next[0:0]$14057 $1\core_fasto1_ok$next[0:0]$13970 - assign $3\core_fasto2_ok$next[0:0]$14058 $1\core_fasto2_ok$next[0:0]$13971 - assign $3\core_rego_ok$next[0:0]$14059 $1\core_rego_ok$next[0:0]$13972 - assign $3\core_spro_ok$next[0:0]$14060 $1\core_spro_ok$next[0:0]$13973 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13857 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13858 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13859 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13860 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13861 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13862 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13863 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13864 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13865 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13866 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13867 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13868 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13869 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13870 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13871 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13872 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13873 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13874 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13875 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13876 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13877 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13878 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13879 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13880 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13881 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13882 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13883 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13884 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13885 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13886 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13887 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13888 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13889 - update \core_core_ea$next $0\core_core_ea$next[6:0]$13890 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13891 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13892 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13893 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13894 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13895 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13896 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13897 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13898 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13899 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13900 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13901 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13902 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13903 - update \core_core_rego$next $0\core_core_rego$next[6:0]$13904 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13905 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13906 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13907 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13908 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13909 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13910 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13911 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13912 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13913 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13914 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13915 - end - connect \$101 $add$libresoc.v:194791$13361_Y - connect \$103 $mul$libresoc.v:194792$13362_Y - connect \$99 $shr$libresoc.v:194793$13363_Y [31:0] - connect \$106 $not$libresoc.v:194794$13364_Y - connect \$108 $not$libresoc.v:194795$13365_Y - connect \$110 $and$libresoc.v:194796$13366_Y - connect \$112 $not$libresoc.v:194797$13367_Y - connect \$114 $not$libresoc.v:194798$13368_Y - connect \$116 $and$libresoc.v:194799$13369_Y - connect \$118 $or$libresoc.v:194800$13370_Y + assign $3\core_rego_ok$next[0:0]$14244 1'0 + assign $3\core_ea_ok$next[0:0]$14241 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14236 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14237 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14238 1'0 + assign $3\core_spro_ok$next[0:0]$14245 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14239 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14234 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14235 1'0 + assign $3\core_fasto1_ok$next[0:0]$14242 1'0 + assign $3\core_fasto2_ok$next[0:0]$14243 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 1'0 + assign $3\core_cr_out_ok$next[0:0]$14240 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14229 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14228 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 $1\core_core_core_cr_rd_ok$next[0:0]$14104 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 $1\core_core_core_exc_$signal$3$next[0:0]$14106 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 $1\core_core_core_exc_$signal$4$next[0:0]$14107 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 $1\core_core_core_exc_$signal$5$next[0:0]$14108 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 $1\core_core_core_exc_$signal$6$next[0:0]$14109 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 $1\core_core_core_exc_$signal$7$next[0:0]$14110 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 $1\core_core_core_exc_$signal$8$next[0:0]$14111 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 $1\core_core_core_exc_$signal$9$next[0:0]$14112 + assign $3\core_core_core_exc_$signal$next[0:0]$14227 $1\core_core_core_exc_$signal$next[0:0]$14113 + assign $3\core_core_core_oe_ok$next[0:0]$14228 $1\core_core_core_oe_ok$next[0:0]$14121 + assign $3\core_core_core_rc_ok$next[0:0]$14229 $1\core_core_core_rc_ok$next[0:0]$14123 + assign $3\core_core_cr_in1_ok$next[0:0]$14230 $1\core_core_cr_in1_ok$next[0:0]$14127 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 $1\core_core_cr_in2_ok$2$next[0:0]$14130 + assign $3\core_core_cr_in2_ok$next[0:0]$14232 $1\core_core_cr_in2_ok$next[0:0]$14131 + assign $3\core_core_cr_wr_ok$next[0:0]$14233 $1\core_core_cr_wr_ok$next[0:0]$14133 + assign $3\core_core_fast1_ok$next[0:0]$14234 $1\core_core_fast1_ok$next[0:0]$14136 + assign $3\core_core_fast2_ok$next[0:0]$14235 $1\core_core_fast2_ok$next[0:0]$14138 + assign $3\core_core_reg1_ok$next[0:0]$14236 $1\core_core_reg1_ok$next[0:0]$14143 + assign $3\core_core_reg2_ok$next[0:0]$14237 $1\core_core_reg2_ok$next[0:0]$14145 + assign $3\core_core_reg3_ok$next[0:0]$14238 $1\core_core_reg3_ok$next[0:0]$14147 + assign $3\core_core_spr1_ok$next[0:0]$14239 $1\core_core_spr1_ok$next[0:0]$14150 + assign $3\core_cr_out_ok$next[0:0]$14240 $1\core_cr_out_ok$next[0:0]$14153 + assign $3\core_ea_ok$next[0:0]$14241 $1\core_ea_ok$next[0:0]$14154 + assign $3\core_fasto1_ok$next[0:0]$14242 $1\core_fasto1_ok$next[0:0]$14155 + assign $3\core_fasto2_ok$next[0:0]$14243 $1\core_fasto2_ok$next[0:0]$14156 + assign $3\core_rego_ok$next[0:0]$14244 $1\core_rego_ok$next[0:0]$14157 + assign $3\core_spro_ok$next[0:0]$14245 $1\core_spro_ok$next[0:0]$14158 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$14042 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14043 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14044 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14045 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14046 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14047 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14048 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14049 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14050 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14051 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14052 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14053 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14054 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$14055 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14056 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14057 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14058 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14059 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14060 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14061 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14062 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14063 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14064 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14065 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14066 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14067 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14068 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14069 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14070 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14071 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14072 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14073 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14074 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14075 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14076 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14077 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14078 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14079 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14080 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14081 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14082 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14083 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14084 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14085 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14086 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14087 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14088 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14089 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14090 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14091 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14092 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14093 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14094 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14095 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14096 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14097 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14098 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14099 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14100 + end + connect \$101 $add$libresoc.v:197083$13545_Y + connect \$103 $mul$libresoc.v:197084$13546_Y + connect \$99 $shr$libresoc.v:197085$13547_Y [31:0] + connect \$106 $not$libresoc.v:197086$13548_Y + connect \$108 $not$libresoc.v:197087$13549_Y + connect \$110 $and$libresoc.v:197088$13550_Y + connect \$112 $not$libresoc.v:197089$13551_Y + connect \$114 $not$libresoc.v:197090$13552_Y + connect \$116 $and$libresoc.v:197091$13553_Y + connect \$118 $or$libresoc.v:197092$13554_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:194802$13371_Y - connect \$124 $not$libresoc.v:194803$13372_Y - connect \$126 $not$libresoc.v:194804$13373_Y - connect \$128 $and$libresoc.v:194805$13374_Y - connect \$130 $not$libresoc.v:194806$13375_Y - connect \$132 $not$libresoc.v:194807$13376_Y - connect \$134 $and$libresoc.v:194808$13377_Y - connect \$136 $eq$libresoc.v:194809$13378_Y - connect \$138 $and$libresoc.v:194810$13379_Y - connect \$140 $not$libresoc.v:194811$13380_Y - connect \$142 $not$libresoc.v:194812$13381_Y - connect \$144 $and$libresoc.v:194813$13382_Y - connect \$146 $or$libresoc.v:194814$13383_Y - connect \$148 1'1 - connect \$150 $or$libresoc.v:194816$13384_Y - connect \$152 $not$libresoc.v:194817$13385_Y - connect \$154 $not$libresoc.v:194818$13386_Y - connect \$156 $and$libresoc.v:194819$13387_Y - connect \$158 $not$libresoc.v:194820$13388_Y - connect \$160 $not$libresoc.v:194821$13389_Y - connect \$162 $and$libresoc.v:194822$13390_Y - connect \$164 $not$libresoc.v:194823$13391_Y - connect \$166 $not$libresoc.v:194824$13392_Y - connect \$168 $and$libresoc.v:194825$13393_Y - connect \$170 $not$libresoc.v:194826$13394_Y - connect \$172 $not$libresoc.v:194827$13395_Y - connect \$174 $and$libresoc.v:194828$13396_Y - connect \$176 $not$libresoc.v:194829$13397_Y - connect \$178 $not$libresoc.v:194830$13398_Y - connect \$180 $and$libresoc.v:194831$13399_Y - connect \$182 $not$libresoc.v:194832$13400_Y - connect \$184 $not$libresoc.v:194833$13401_Y - connect \$186 $and$libresoc.v:194834$13402_Y - connect \$189 $and$libresoc.v:194835$13403_Y - connect \$188 $reduce_or$libresoc.v:194836$13404_Y - connect \$192 $not$libresoc.v:194837$13405_Y - connect \$194 $not$libresoc.v:194838$13406_Y - connect \$196 $and$libresoc.v:194839$13407_Y - connect \$198 $not$libresoc.v:194840$13408_Y - connect \$200 $not$libresoc.v:194841$13409_Y - connect \$202 $and$libresoc.v:194842$13410_Y - connect \$204 $or$libresoc.v:194843$13411_Y - connect \$206 1'1 - connect \$208 $or$libresoc.v:194845$13412_Y - connect \$210 $not$libresoc.v:194846$13413_Y - connect \$212 $not$libresoc.v:194847$13414_Y - connect \$214 $and$libresoc.v:194848$13415_Y - connect \$216 $not$libresoc.v:194849$13416_Y - connect \$218 $not$libresoc.v:194850$13417_Y - connect \$220 $and$libresoc.v:194851$13418_Y - connect \$223 $and$libresoc.v:194852$13419_Y - connect \$222 $reduce_or$libresoc.v:194853$13420_Y - connect \$226 $eq$libresoc.v:194854$13421_Y - connect \$228 $and$libresoc.v:194855$13422_Y - connect \$230 $not$libresoc.v:194856$13423_Y - connect \$232 $not$libresoc.v:194857$13424_Y - connect \$234 $not$libresoc.v:194858$13425_Y - connect \$236 $and$libresoc.v:194859$13426_Y - connect \$238 $not$libresoc.v:194860$13427_Y - connect \$23 $ne$libresoc.v:194861$13428_Y - connect \$240 $not$libresoc.v:194862$13429_Y - connect \$242 $and$libresoc.v:194863$13430_Y - connect \$245 $add$libresoc.v:194864$13431_Y - connect \$247 $not$libresoc.v:194865$13432_Y - connect \$249 $not$libresoc.v:194866$13433_Y - connect \$251 $and$libresoc.v:194867$13434_Y - connect \$253 $eq$libresoc.v:194868$13435_Y - connect \$255 $pos$libresoc.v:194869$13436_Y - connect \$257 $ne$libresoc.v:194870$13437_Y - connect \$259 $not$libresoc.v:194871$13438_Y - connect \$261 $not$libresoc.v:194872$13439_Y - connect \$263 $pos$libresoc.v:194873$13441_Y - connect \$265 $pos$libresoc.v:194874$13443_Y - connect \$268 $sub$libresoc.v:194875$13444_Y - connect \$26 $sub$libresoc.v:194876$13445_Y - connect \$271 $add$libresoc.v:194877$13446_Y - connect \$28 $or$libresoc.v:194878$13447_Y - connect \$30 $or$libresoc.v:194879$13448_Y - connect \$32 $ne$libresoc.v:194880$13449_Y - connect \$34 $not$libresoc.v:194881$13450_Y - connect \$36 $and$libresoc.v:194882$13451_Y - connect \$38 $not$libresoc.v:194883$13452_Y - connect \$40 $not$libresoc.v:194884$13453_Y - connect \$42 $pos$libresoc.v:194885$13455_Y - connect \$44 $not$libresoc.v:194886$13456_Y - connect \$46 $not$libresoc.v:194887$13457_Y - connect \$48 $and$libresoc.v:194888$13458_Y - connect \$50 $eq$libresoc.v:194889$13459_Y - connect \$52 $and$libresoc.v:194890$13460_Y - connect \$54 $not$libresoc.v:194891$13461_Y - connect \$56 $not$libresoc.v:194892$13462_Y - connect \$58 $and$libresoc.v:194893$13463_Y - connect \$60 $or$libresoc.v:194894$13464_Y + connect \$122 $or$libresoc.v:197094$13555_Y + connect \$125 $add$libresoc.v:197095$13556_Y + connect \$128 $add$libresoc.v:197096$13557_Y + connect \$130 $not$libresoc.v:197097$13558_Y + connect \$132 $not$libresoc.v:197098$13559_Y + connect \$134 $and$libresoc.v:197099$13560_Y + connect \$136 $not$libresoc.v:197100$13561_Y + connect \$138 $not$libresoc.v:197101$13562_Y + connect \$140 $and$libresoc.v:197102$13563_Y + connect \$142 $eq$libresoc.v:197103$13564_Y + connect \$144 $and$libresoc.v:197104$13565_Y + connect \$146 $not$libresoc.v:197105$13566_Y + connect \$148 $not$libresoc.v:197106$13567_Y + connect \$150 $and$libresoc.v:197107$13568_Y + connect \$152 $or$libresoc.v:197108$13569_Y + connect \$154 1'1 + connect \$156 $or$libresoc.v:197110$13570_Y + connect \$158 $not$libresoc.v:197111$13571_Y + connect \$160 $not$libresoc.v:197112$13572_Y + connect \$162 $and$libresoc.v:197113$13573_Y + connect \$164 $not$libresoc.v:197114$13574_Y + connect \$166 $not$libresoc.v:197115$13575_Y + connect \$168 $and$libresoc.v:197116$13576_Y + connect \$170 $not$libresoc.v:197117$13577_Y + connect \$172 $not$libresoc.v:197118$13578_Y + connect \$174 $and$libresoc.v:197119$13579_Y + connect \$176 $not$libresoc.v:197120$13580_Y + connect \$178 $not$libresoc.v:197121$13581_Y + connect \$180 $and$libresoc.v:197122$13582_Y + connect \$182 $not$libresoc.v:197123$13583_Y + connect \$184 $not$libresoc.v:197124$13584_Y + connect \$186 $and$libresoc.v:197125$13585_Y + connect \$188 $not$libresoc.v:197126$13586_Y + connect \$190 $not$libresoc.v:197127$13587_Y + connect \$192 $and$libresoc.v:197128$13588_Y + connect \$195 $and$libresoc.v:197129$13589_Y + connect \$194 $reduce_or$libresoc.v:197130$13590_Y + connect \$198 $not$libresoc.v:197131$13591_Y + connect \$200 $not$libresoc.v:197132$13592_Y + connect \$202 $and$libresoc.v:197133$13593_Y + connect \$204 $not$libresoc.v:197134$13594_Y + connect \$206 $not$libresoc.v:197135$13595_Y + connect \$208 $and$libresoc.v:197136$13596_Y + connect \$210 $or$libresoc.v:197137$13597_Y + connect \$212 1'1 + connect \$214 $or$libresoc.v:197139$13598_Y + connect \$216 $not$libresoc.v:197140$13599_Y + connect \$218 $not$libresoc.v:197141$13600_Y + connect \$220 $and$libresoc.v:197142$13601_Y + connect \$222 $not$libresoc.v:197143$13602_Y + connect \$224 $not$libresoc.v:197144$13603_Y + connect \$226 $and$libresoc.v:197145$13604_Y + connect \$229 $and$libresoc.v:197146$13605_Y + connect \$228 $reduce_or$libresoc.v:197147$13606_Y + connect \$232 $eq$libresoc.v:197148$13607_Y + connect \$234 $and$libresoc.v:197149$13608_Y + connect \$236 $not$libresoc.v:197150$13609_Y + connect \$238 $not$libresoc.v:197151$13610_Y + connect \$23 $ne$libresoc.v:197152$13611_Y + connect \$240 $not$libresoc.v:197153$13612_Y + connect \$242 $and$libresoc.v:197154$13613_Y + connect \$244 $not$libresoc.v:197155$13614_Y + connect \$246 $not$libresoc.v:197156$13615_Y + connect \$248 $and$libresoc.v:197157$13616_Y + connect \$250 $eq$libresoc.v:197158$13617_Y + connect \$252 $pos$libresoc.v:197159$13618_Y + connect \$254 $ne$libresoc.v:197160$13619_Y + connect \$256 $not$libresoc.v:197161$13620_Y + connect \$258 $not$libresoc.v:197162$13621_Y + connect \$260 $pos$libresoc.v:197163$13623_Y + connect \$262 $pos$libresoc.v:197164$13625_Y + connect \$265 $sub$libresoc.v:197165$13626_Y + connect \$268 $add$libresoc.v:197166$13627_Y + connect \$26 $sub$libresoc.v:197167$13628_Y + connect \$28 $or$libresoc.v:197168$13629_Y + connect \$30 $or$libresoc.v:197169$13630_Y + connect \$32 $ne$libresoc.v:197170$13631_Y + connect \$34 $not$libresoc.v:197171$13632_Y + connect \$36 $and$libresoc.v:197172$13633_Y + connect \$38 $not$libresoc.v:197173$13634_Y + connect \$40 $not$libresoc.v:197174$13635_Y + connect \$42 $pos$libresoc.v:197175$13637_Y + connect \$44 $not$libresoc.v:197176$13638_Y + connect \$46 $not$libresoc.v:197177$13639_Y + connect \$48 $and$libresoc.v:197178$13640_Y + connect \$50 $eq$libresoc.v:197179$13641_Y + connect \$52 $and$libresoc.v:197180$13642_Y + connect \$54 $not$libresoc.v:197181$13643_Y + connect \$56 $not$libresoc.v:197182$13644_Y + connect \$58 $and$libresoc.v:197183$13645_Y + connect \$60 $or$libresoc.v:197184$13646_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:194896$13465_Y - connect \$66 $not$libresoc.v:194897$13466_Y - connect \$68 $not$libresoc.v:194898$13467_Y - connect \$70 $and$libresoc.v:194899$13468_Y - connect \$72 $eq$libresoc.v:194900$13469_Y - connect \$74 $and$libresoc.v:194901$13470_Y - connect \$76 $not$libresoc.v:194902$13471_Y - connect \$78 $not$libresoc.v:194903$13472_Y - connect \$80 $and$libresoc.v:194904$13473_Y - connect \$82 $or$libresoc.v:194905$13474_Y + connect \$64 $or$libresoc.v:197186$13647_Y + connect \$66 $not$libresoc.v:197187$13648_Y + connect \$68 $not$libresoc.v:197188$13649_Y + connect \$70 $and$libresoc.v:197189$13650_Y + connect \$72 $eq$libresoc.v:197190$13651_Y + connect \$74 $and$libresoc.v:197191$13652_Y + connect \$76 $not$libresoc.v:197192$13653_Y + connect \$78 $not$libresoc.v:197193$13654_Y + connect \$80 $and$libresoc.v:197194$13655_Y + connect \$82 $or$libresoc.v:197195$13656_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:194907$13475_Y - connect \$88 $not$libresoc.v:194908$13476_Y - connect \$90 $not$libresoc.v:194909$13477_Y - connect \$93 $add$libresoc.v:194910$13478_Y - connect \$96 $mul$libresoc.v:194911$13479_Y - connect \$95 $shr$libresoc.v:194912$13480_Y [31:0] + connect \$86 $or$libresoc.v:197197$13657_Y + connect \$88 $not$libresoc.v:197198$13658_Y + connect \$90 $not$libresoc.v:197199$13659_Y + connect \$93 $add$libresoc.v:197200$13660_Y + connect \$96 $mul$libresoc.v:197201$13661_Y + connect \$95 $shr$libresoc.v:197202$13662_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 - connect \$244 \$245 + connect \$124 \$125 + connect \$127 \$128 + connect \$264 \$265 connect \$267 \$268 - connect \$270 \$271 connect \dec2_sv_a_nz 1'0 connect \svstate_i_ok 1'0 connect \svstate_i 0 connect \is_svp64_mode 1'0 + connect \pred_insn_ready_o 1'0 + connect \pred_mask_valid_o 1'0 + connect \next_dststep \$128 [6:0] + connect \next_srcstep \$125 [6:0] connect \dbg_core_dbg_msr \dec2_cur_msr connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc @@ -412681,485 +416704,485 @@ module \ti connect \sram4k_1_enable \jtag_wb_sram_en connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:197549.1-198740.10" +attribute \src "libresoc.v:199862.1-201053.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:198285.3-198286.25" + attribute \src "libresoc.v:200598.3-200599.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:198283.3-198284.41" + attribute \src "libresoc.v:200596.3-200597.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:198643.3-198651.6" - wire $0\alu_l_r_alu$next[0:0]$14382 - attribute \src "libresoc.v:198211.3-198212.39" + attribute \src "libresoc.v:200956.3-200964.6" + wire $0\alu_l_r_alu$next[0:0]$14567 + attribute \src "libresoc.v:200524.3-200525.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14308 - attribute \src "libresoc.v:198251.3-198252.61" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14493 + attribute \src "libresoc.v:200564.3-200565.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 - attribute \src "libresoc.v:198245.3-198246.69" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + attribute \src "libresoc.v:200558.3-200559.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14310 - attribute \src "libresoc.v:198247.3-198248.63" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14495 + attribute \src "libresoc.v:200560.3-200561.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 - attribute \src "libresoc.v:198243.3-198244.73" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + attribute \src "libresoc.v:200556.3-200557.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 - attribute \src "libresoc.v:198253.3-198254.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + attribute \src "libresoc.v:200566.3-200567.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 - attribute \src "libresoc.v:198259.3-198260.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + attribute \src "libresoc.v:200572.3-200573.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14314 - attribute \src "libresoc.v:198249.3-198250.61" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14499 + attribute \src "libresoc.v:200562.3-200563.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 - attribute \src "libresoc.v:198257.3-198258.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + attribute \src "libresoc.v:200570.3-200571.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14316 - attribute \src "libresoc.v:198255.3-198256.71" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + attribute \src "libresoc.v:200568.3-200569.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:198634.3-198642.6" - wire $0\alui_l_r_alui$next[0:0]$14379 - attribute \src "libresoc.v:198213.3-198214.43" + attribute \src "libresoc.v:200947.3-200955.6" + wire $0\alui_l_r_alui$next[0:0]$14564 + attribute \src "libresoc.v:200526.3-200527.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $0\data_r0__o$next[63:0]$14327 - attribute \src "libresoc.v:198239.3-198240.37" + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $0\data_r0__o$next[63:0]$14512 + attribute \src "libresoc.v:200552.3-200553.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire $0\data_r0__o_ok$next[0:0]$14328 - attribute \src "libresoc.v:198241.3-198242.43" + attribute \src "libresoc.v:200797.3-200818.6" + wire $0\data_r0__o_ok$next[0:0]$14513 + attribute \src "libresoc.v:200554.3-200555.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14335 - attribute \src "libresoc.v:198235.3-198236.45" + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14520 + attribute \src "libresoc.v:200548.3-200549.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire $0\data_r1__fast1_ok$next[0:0]$14336 - attribute \src "libresoc.v:198237.3-198238.51" + attribute \src "libresoc.v:200819.3-200840.6" + wire $0\data_r1__fast1_ok$next[0:0]$14521 + attribute \src "libresoc.v:200550.3-200551.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14343 - attribute \src "libresoc.v:198231.3-198232.45" + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14528 + attribute \src "libresoc.v:200544.3-200545.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire $0\data_r2__fast2_ok$next[0:0]$14344 - attribute \src "libresoc.v:198233.3-198234.51" + attribute \src "libresoc.v:200841.3-200862.6" + wire $0\data_r2__fast2_ok$next[0:0]$14529 + attribute \src "libresoc.v:200546.3-200547.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $0\data_r3__nia$next[63:0]$14351 - attribute \src "libresoc.v:198227.3-198228.41" + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $0\data_r3__nia$next[63:0]$14536 + attribute \src "libresoc.v:200540.3-200541.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire $0\data_r3__nia_ok$next[0:0]$14352 - attribute \src "libresoc.v:198229.3-198230.47" + attribute \src "libresoc.v:200863.3-200884.6" + wire $0\data_r3__nia_ok$next[0:0]$14537 + attribute \src "libresoc.v:200542.3-200543.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $0\data_r4__msr$next[63:0]$14359 - attribute \src "libresoc.v:198223.3-198224.41" + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $0\data_r4__msr$next[63:0]$14544 + attribute \src "libresoc.v:200536.3-200537.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire $0\data_r4__msr_ok$next[0:0]$14360 - attribute \src "libresoc.v:198225.3-198226.47" + attribute \src "libresoc.v:200885.3-200906.6" + wire $0\data_r4__msr_ok$next[0:0]$14545 + attribute \src "libresoc.v:200538.3-200539.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:198652.3-198661.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:198662.3-198671.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:198672.3-198681.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:198682.3-198691.6" + attribute \src "libresoc.v:200995.3-201004.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:198692.3-198701.6" + attribute \src "libresoc.v:201005.3-201014.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:197550.7-197550.20" + attribute \src "libresoc.v:199863.7-199863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198421.3-198429.6" - wire $0\opc_l_r_opc$next[0:0]$14293 - attribute \src "libresoc.v:198269.3-198270.39" + attribute \src "libresoc.v:200734.3-200742.6" + wire $0\opc_l_r_opc$next[0:0]$14478 + attribute \src "libresoc.v:200582.3-200583.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:198412.3-198420.6" - wire $0\opc_l_s_opc$next[0:0]$14290 - attribute \src "libresoc.v:198271.3-198272.39" + attribute \src "libresoc.v:200725.3-200733.6" + wire $0\opc_l_s_opc$next[0:0]$14475 + attribute \src "libresoc.v:200584.3-200585.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:198702.3-198710.6" - wire width 5 $0\prev_wr_go$next[4:0]$14390 - attribute \src "libresoc.v:198281.3-198282.37" + attribute \src "libresoc.v:201015.3-201023.6" + wire width 5 $0\prev_wr_go$next[4:0]$14575 + attribute \src "libresoc.v:200594.3-200595.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:198366.3-198375.6" + attribute \src "libresoc.v:200679.3-200688.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:198457.3-198465.6" - wire width 5 $0\req_l_r_req$next[4:0]$14305 - attribute \src "libresoc.v:198261.3-198262.39" + attribute \src "libresoc.v:200770.3-200778.6" + wire width 5 $0\req_l_r_req$next[4:0]$14490 + attribute \src "libresoc.v:200574.3-200575.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:198448.3-198456.6" - wire width 5 $0\req_l_s_req$next[4:0]$14302 - attribute \src "libresoc.v:198263.3-198264.39" + attribute \src "libresoc.v:200761.3-200769.6" + wire width 5 $0\req_l_s_req$next[4:0]$14487 + attribute \src "libresoc.v:200576.3-200577.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:198385.3-198393.6" - wire $0\rok_l_r_rdok$next[0:0]$14281 - attribute \src "libresoc.v:198277.3-198278.41" + attribute \src "libresoc.v:200698.3-200706.6" + wire $0\rok_l_r_rdok$next[0:0]$14466 + attribute \src "libresoc.v:200590.3-200591.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:198376.3-198384.6" - wire $0\rok_l_s_rdok$next[0:0]$14278 - attribute \src "libresoc.v:198279.3-198280.41" + attribute \src "libresoc.v:200689.3-200697.6" + wire $0\rok_l_s_rdok$next[0:0]$14463 + attribute \src "libresoc.v:200592.3-200593.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:198403.3-198411.6" - wire $0\rst_l_r_rst$next[0:0]$14287 - attribute \src "libresoc.v:198273.3-198274.39" + attribute \src "libresoc.v:200716.3-200724.6" + wire $0\rst_l_r_rst$next[0:0]$14472 + attribute \src "libresoc.v:200586.3-200587.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:198394.3-198402.6" - wire $0\rst_l_s_rst$next[0:0]$14284 - attribute \src "libresoc.v:198275.3-198276.39" + attribute \src "libresoc.v:200707.3-200715.6" + wire $0\rst_l_s_rst$next[0:0]$14469 + attribute \src "libresoc.v:200588.3-200589.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:198439.3-198447.6" - wire width 4 $0\src_l_r_src$next[3:0]$14299 - attribute \src "libresoc.v:198265.3-198266.39" + attribute \src "libresoc.v:200752.3-200760.6" + wire width 4 $0\src_l_r_src$next[3:0]$14484 + attribute \src "libresoc.v:200578.3-200579.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:198430.3-198438.6" - wire width 4 $0\src_l_s_src$next[3:0]$14296 - attribute \src "libresoc.v:198267.3-198268.39" + attribute \src "libresoc.v:200743.3-200751.6" + wire width 4 $0\src_l_s_src$next[3:0]$14481 + attribute \src "libresoc.v:200580.3-200581.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:198594.3-198603.6" - wire width 64 $0\src_r0$next[63:0]$14367 - attribute \src "libresoc.v:198221.3-198222.29" + attribute \src "libresoc.v:200907.3-200916.6" + wire width 64 $0\src_r0$next[63:0]$14552 + attribute \src "libresoc.v:200534.3-200535.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:198604.3-198613.6" - wire width 64 $0\src_r1$next[63:0]$14370 - attribute \src "libresoc.v:198219.3-198220.29" + attribute \src "libresoc.v:200917.3-200926.6" + wire width 64 $0\src_r1$next[63:0]$14555 + attribute \src "libresoc.v:200532.3-200533.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:198614.3-198623.6" - wire width 64 $0\src_r2$next[63:0]$14373 - attribute \src "libresoc.v:198217.3-198218.29" + attribute \src "libresoc.v:200927.3-200936.6" + wire width 64 $0\src_r2$next[63:0]$14558 + attribute \src "libresoc.v:200530.3-200531.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:198624.3-198633.6" - wire width 64 $0\src_r3$next[63:0]$14376 - attribute \src "libresoc.v:198215.3-198216.29" + attribute \src "libresoc.v:200937.3-200946.6" + wire width 64 $0\src_r3$next[63:0]$14561 + attribute \src "libresoc.v:200528.3-200529.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:197676.7-197676.24" + attribute \src "libresoc.v:199989.7-199989.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:197686.7-197686.26" + attribute \src "libresoc.v:199999.7-199999.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:198643.3-198651.6" - wire $1\alu_l_r_alu$next[0:0]$14383 - attribute \src "libresoc.v:197694.7-197694.25" + attribute \src "libresoc.v:200956.3-200964.6" + wire $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200007.7-200007.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14317 - attribute \src "libresoc.v:197730.14-197730.59" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + attribute \src "libresoc.v:200043.14-200043.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 - attribute \src "libresoc.v:197749.14-197749.51" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + attribute \src "libresoc.v:200062.14-200062.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14319 - attribute \src "libresoc.v:197753.14-197753.45" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + attribute \src "libresoc.v:200066.14-200066.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 - attribute \src "libresoc.v:197832.13-197832.49" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + attribute \src "libresoc.v:200145.13-200145.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 - attribute \src "libresoc.v:197836.7-197836.41" + attribute \src "libresoc.v:200779.3-200796.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + attribute \src "libresoc.v:200149.7-200149.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 - attribute \src "libresoc.v:197840.13-197840.48" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + attribute \src "libresoc.v:200153.13-200153.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14323 - attribute \src "libresoc.v:197844.14-197844.59" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + attribute \src "libresoc.v:200157.14-200157.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 - attribute \src "libresoc.v:197848.14-197848.52" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 + attribute \src "libresoc.v:200161.14-200161.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:198466.3-198483.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 - attribute \src "libresoc.v:197852.13-197852.48" + attribute \src "libresoc.v:200779.3-200796.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 + attribute \src "libresoc.v:200165.13-200165.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:198634.3-198642.6" - wire $1\alui_l_r_alui$next[0:0]$14380 - attribute \src "libresoc.v:197858.7-197858.27" + attribute \src "libresoc.v:200947.3-200955.6" + wire $1\alui_l_r_alui$next[0:0]$14565 + attribute \src "libresoc.v:200171.7-200171.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $1\data_r0__o$next[63:0]$14329 - attribute \src "libresoc.v:197890.14-197890.47" + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $1\data_r0__o$next[63:0]$14514 + attribute \src "libresoc.v:200203.14-200203.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire $1\data_r0__o_ok$next[0:0]$14330 - attribute \src "libresoc.v:197894.7-197894.27" + attribute \src "libresoc.v:200797.3-200818.6" + wire $1\data_r0__o_ok$next[0:0]$14515 + attribute \src "libresoc.v:200207.7-200207.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14337 - attribute \src "libresoc.v:197898.14-197898.51" + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14522 + attribute \src "libresoc.v:200211.14-200211.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:198506.3-198527.6" - wire $1\data_r1__fast1_ok$next[0:0]$14338 - attribute \src "libresoc.v:197902.7-197902.31" + attribute \src "libresoc.v:200819.3-200840.6" + wire $1\data_r1__fast1_ok$next[0:0]$14523 + attribute \src "libresoc.v:200215.7-200215.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14345 - attribute \src "libresoc.v:197906.14-197906.51" + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14530 + attribute \src "libresoc.v:200219.14-200219.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:198528.3-198549.6" - wire $1\data_r2__fast2_ok$next[0:0]$14346 - attribute \src "libresoc.v:197910.7-197910.31" + attribute \src "libresoc.v:200841.3-200862.6" + wire $1\data_r2__fast2_ok$next[0:0]$14531 + attribute \src "libresoc.v:200223.7-200223.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $1\data_r3__nia$next[63:0]$14353 - attribute \src "libresoc.v:197914.14-197914.49" + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $1\data_r3__nia$next[63:0]$14538 + attribute \src "libresoc.v:200227.14-200227.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:198550.3-198571.6" - wire $1\data_r3__nia_ok$next[0:0]$14354 - attribute \src "libresoc.v:197918.7-197918.29" + attribute \src "libresoc.v:200863.3-200884.6" + wire $1\data_r3__nia_ok$next[0:0]$14539 + attribute \src "libresoc.v:200231.7-200231.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $1\data_r4__msr$next[63:0]$14361 - attribute \src "libresoc.v:197922.14-197922.49" + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $1\data_r4__msr$next[63:0]$14546 + attribute \src "libresoc.v:200235.14-200235.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:198572.3-198593.6" - wire $1\data_r4__msr_ok$next[0:0]$14362 - attribute \src "libresoc.v:197926.7-197926.29" + attribute \src "libresoc.v:200885.3-200906.6" + wire $1\data_r4__msr_ok$next[0:0]$14547 + attribute \src "libresoc.v:200239.7-200239.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:198652.3-198661.6" + attribute \src "libresoc.v:200965.3-200974.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:198662.3-198671.6" + attribute \src "libresoc.v:200975.3-200984.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:198672.3-198681.6" + attribute \src "libresoc.v:200985.3-200994.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:198682.3-198691.6" + attribute \src "libresoc.v:200995.3-201004.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:198692.3-198701.6" + attribute \src "libresoc.v:201005.3-201014.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:198421.3-198429.6" - wire $1\opc_l_r_opc$next[0:0]$14294 - attribute \src "libresoc.v:197957.7-197957.25" + attribute \src "libresoc.v:200734.3-200742.6" + wire $1\opc_l_r_opc$next[0:0]$14479 + attribute \src "libresoc.v:200270.7-200270.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:198412.3-198420.6" - wire $1\opc_l_s_opc$next[0:0]$14291 - attribute \src "libresoc.v:197961.7-197961.25" + attribute \src "libresoc.v:200725.3-200733.6" + wire $1\opc_l_s_opc$next[0:0]$14476 + attribute \src "libresoc.v:200274.7-200274.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:198702.3-198710.6" - wire width 5 $1\prev_wr_go$next[4:0]$14391 - attribute \src "libresoc.v:198073.13-198073.31" + attribute \src "libresoc.v:201015.3-201023.6" + wire width 5 $1\prev_wr_go$next[4:0]$14576 + attribute \src "libresoc.v:200386.13-200386.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:198366.3-198375.6" + attribute \src "libresoc.v:200679.3-200688.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:198457.3-198465.6" - wire width 5 $1\req_l_r_req$next[4:0]$14306 - attribute \src "libresoc.v:198081.13-198081.32" + attribute \src "libresoc.v:200770.3-200778.6" + wire width 5 $1\req_l_r_req$next[4:0]$14491 + attribute \src "libresoc.v:200394.13-200394.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:198448.3-198456.6" - wire width 5 $1\req_l_s_req$next[4:0]$14303 - attribute \src "libresoc.v:198085.13-198085.32" + attribute \src "libresoc.v:200761.3-200769.6" + wire width 5 $1\req_l_s_req$next[4:0]$14488 + attribute \src "libresoc.v:200398.13-200398.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:198385.3-198393.6" - wire $1\rok_l_r_rdok$next[0:0]$14282 - attribute \src "libresoc.v:198097.7-198097.26" + attribute \src "libresoc.v:200698.3-200706.6" + wire $1\rok_l_r_rdok$next[0:0]$14467 + attribute \src "libresoc.v:200410.7-200410.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:198376.3-198384.6" - wire $1\rok_l_s_rdok$next[0:0]$14279 - attribute \src "libresoc.v:198101.7-198101.26" + attribute \src "libresoc.v:200689.3-200697.6" + wire $1\rok_l_s_rdok$next[0:0]$14464 + attribute \src "libresoc.v:200414.7-200414.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:198403.3-198411.6" - wire $1\rst_l_r_rst$next[0:0]$14288 - attribute \src "libresoc.v:198105.7-198105.25" + attribute \src "libresoc.v:200716.3-200724.6" + wire $1\rst_l_r_rst$next[0:0]$14473 + attribute \src "libresoc.v:200418.7-200418.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:198394.3-198402.6" - wire $1\rst_l_s_rst$next[0:0]$14285 - attribute \src "libresoc.v:198109.7-198109.25" + attribute \src "libresoc.v:200707.3-200715.6" + wire $1\rst_l_s_rst$next[0:0]$14470 + attribute \src "libresoc.v:200422.7-200422.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:198439.3-198447.6" - wire width 4 $1\src_l_r_src$next[3:0]$14300 - attribute \src "libresoc.v:198125.13-198125.31" + attribute \src "libresoc.v:200752.3-200760.6" + wire width 4 $1\src_l_r_src$next[3:0]$14485 + attribute \src "libresoc.v:200438.13-200438.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:198430.3-198438.6" - wire width 4 $1\src_l_s_src$next[3:0]$14297 - attribute \src "libresoc.v:198129.13-198129.31" + attribute \src "libresoc.v:200743.3-200751.6" + wire width 4 $1\src_l_s_src$next[3:0]$14482 + attribute \src "libresoc.v:200442.13-200442.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:198594.3-198603.6" - wire width 64 $1\src_r0$next[63:0]$14368 - attribute \src "libresoc.v:198133.14-198133.43" + attribute \src "libresoc.v:200907.3-200916.6" + wire width 64 $1\src_r0$next[63:0]$14553 + attribute \src "libresoc.v:200446.14-200446.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:198604.3-198613.6" - wire width 64 $1\src_r1$next[63:0]$14371 - attribute \src "libresoc.v:198137.14-198137.43" + attribute \src "libresoc.v:200917.3-200926.6" + wire width 64 $1\src_r1$next[63:0]$14556 + attribute \src "libresoc.v:200450.14-200450.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:198614.3-198623.6" - wire width 64 $1\src_r2$next[63:0]$14374 - attribute \src "libresoc.v:198141.14-198141.43" + attribute \src "libresoc.v:200927.3-200936.6" + wire width 64 $1\src_r2$next[63:0]$14559 + attribute \src "libresoc.v:200454.14-200454.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:198624.3-198633.6" - wire width 64 $1\src_r3$next[63:0]$14377 - attribute \src "libresoc.v:198145.14-198145.43" + attribute \src "libresoc.v:200937.3-200946.6" + wire width 64 $1\src_r3$next[63:0]$14562 + attribute \src "libresoc.v:200458.14-200458.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:198484.3-198505.6" - wire width 64 $2\data_r0__o$next[63:0]$14331 - attribute \src "libresoc.v:198484.3-198505.6" - wire $2\data_r0__o_ok$next[0:0]$14332 - attribute \src "libresoc.v:198506.3-198527.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14339 - attribute \src "libresoc.v:198506.3-198527.6" - wire $2\data_r1__fast1_ok$next[0:0]$14340 - attribute \src "libresoc.v:198528.3-198549.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14347 - attribute \src "libresoc.v:198528.3-198549.6" - wire $2\data_r2__fast2_ok$next[0:0]$14348 - attribute \src "libresoc.v:198550.3-198571.6" - wire width 64 $2\data_r3__nia$next[63:0]$14355 - attribute \src "libresoc.v:198550.3-198571.6" - wire $2\data_r3__nia_ok$next[0:0]$14356 - attribute \src "libresoc.v:198572.3-198593.6" - wire width 64 $2\data_r4__msr$next[63:0]$14363 - attribute \src "libresoc.v:198572.3-198593.6" - wire $2\data_r4__msr_ok$next[0:0]$14364 - attribute \src "libresoc.v:198484.3-198505.6" - wire $3\data_r0__o_ok$next[0:0]$14333 - attribute \src "libresoc.v:198506.3-198527.6" - wire $3\data_r1__fast1_ok$next[0:0]$14341 - attribute \src "libresoc.v:198528.3-198549.6" - wire $3\data_r2__fast2_ok$next[0:0]$14349 - attribute \src "libresoc.v:198550.3-198571.6" - wire $3\data_r3__nia_ok$next[0:0]$14357 - attribute \src "libresoc.v:198572.3-198593.6" - wire $3\data_r4__msr_ok$next[0:0]$14365 - attribute \src "libresoc.v:198151.18-198151.112" - wire width 4 $and$libresoc.v:198151$14178_Y - attribute \src "libresoc.v:198152.19-198152.125" - wire $and$libresoc.v:198152$14179_Y - attribute \src "libresoc.v:198153.19-198153.125" - wire $and$libresoc.v:198153$14180_Y - attribute \src "libresoc.v:198154.19-198154.125" - wire $and$libresoc.v:198154$14181_Y - attribute \src "libresoc.v:198155.19-198155.125" - wire $and$libresoc.v:198155$14182_Y - attribute \src "libresoc.v:198156.19-198156.125" - wire $and$libresoc.v:198156$14183_Y - attribute \src "libresoc.v:198157.19-198157.157" - wire width 5 $and$libresoc.v:198157$14184_Y - attribute \src "libresoc.v:198158.19-198158.121" - wire width 5 $and$libresoc.v:198158$14185_Y - attribute \src "libresoc.v:198159.19-198159.127" - wire $and$libresoc.v:198159$14186_Y - attribute \src "libresoc.v:198160.19-198160.127" - wire $and$libresoc.v:198160$14187_Y - attribute \src "libresoc.v:198161.18-198161.110" - wire $and$libresoc.v:198161$14188_Y - attribute \src "libresoc.v:198162.19-198162.127" - wire $and$libresoc.v:198162$14189_Y - attribute \src "libresoc.v:198163.19-198163.127" - wire $and$libresoc.v:198163$14190_Y - attribute \src "libresoc.v:198164.19-198164.127" - wire $and$libresoc.v:198164$14191_Y - attribute \src "libresoc.v:198166.18-198166.98" - wire $and$libresoc.v:198166$14193_Y - attribute \src "libresoc.v:198168.18-198168.100" - wire $and$libresoc.v:198168$14195_Y - attribute \src "libresoc.v:198169.18-198169.171" - wire width 5 $and$libresoc.v:198169$14196_Y - attribute \src "libresoc.v:198171.18-198171.119" - wire width 5 $and$libresoc.v:198171$14198_Y - attribute \src "libresoc.v:198174.18-198174.116" - wire $and$libresoc.v:198174$14201_Y - attribute \src "libresoc.v:198178.17-198178.123" - wire $and$libresoc.v:198178$14205_Y - attribute \src "libresoc.v:198180.18-198180.113" - wire $and$libresoc.v:198180$14207_Y - attribute \src "libresoc.v:198181.18-198181.125" - wire width 5 $and$libresoc.v:198181$14208_Y - attribute \src "libresoc.v:198183.18-198183.112" - wire $and$libresoc.v:198183$14210_Y - attribute \src "libresoc.v:198185.18-198185.127" - wire $and$libresoc.v:198185$14212_Y - attribute \src "libresoc.v:198186.18-198186.127" - wire $and$libresoc.v:198186$14213_Y - attribute \src "libresoc.v:198187.18-198187.117" - wire $and$libresoc.v:198187$14214_Y - attribute \src "libresoc.v:198192.18-198192.131" - wire $and$libresoc.v:198192$14219_Y - attribute \src "libresoc.v:198193.18-198193.124" - wire width 5 $and$libresoc.v:198193$14220_Y - attribute \src "libresoc.v:198196.18-198196.116" - wire $and$libresoc.v:198196$14223_Y - attribute \src "libresoc.v:198197.18-198197.120" - wire $and$libresoc.v:198197$14224_Y - attribute \src "libresoc.v:198198.18-198198.120" - wire $and$libresoc.v:198198$14225_Y - attribute \src "libresoc.v:198199.18-198199.118" - wire $and$libresoc.v:198199$14226_Y - attribute \src "libresoc.v:198200.18-198200.118" - wire $and$libresoc.v:198200$14227_Y - attribute \src "libresoc.v:198206.18-198206.135" - wire $and$libresoc.v:198206$14233_Y - attribute \src "libresoc.v:198207.18-198207.133" - wire $and$libresoc.v:198207$14234_Y - attribute \src "libresoc.v:198208.18-198208.160" - wire width 4 $and$libresoc.v:198208$14235_Y - attribute \src "libresoc.v:198209.18-198209.112" - wire width 4 $and$libresoc.v:198209$14236_Y - attribute \src "libresoc.v:198182.18-198182.113" - wire $eq$libresoc.v:198182$14209_Y - attribute \src "libresoc.v:198184.18-198184.119" - wire $eq$libresoc.v:198184$14211_Y - attribute \src "libresoc.v:198165.18-198165.97" - wire $not$libresoc.v:198165$14192_Y - attribute \src "libresoc.v:198167.18-198167.99" - wire $not$libresoc.v:198167$14194_Y - attribute \src "libresoc.v:198170.18-198170.113" - wire width 5 $not$libresoc.v:198170$14197_Y - attribute \src "libresoc.v:198173.18-198173.106" - wire $not$libresoc.v:198173$14200_Y - attribute \src "libresoc.v:198179.18-198179.121" - wire $not$libresoc.v:198179$14206_Y - attribute \src "libresoc.v:198194.17-198194.113" - wire width 4 $not$libresoc.v:198194$14221_Y - attribute \src "libresoc.v:198210.18-198210.114" - wire width 4 $not$libresoc.v:198210$14237_Y - attribute \src "libresoc.v:198177.18-198177.112" - wire $or$libresoc.v:198177$14204_Y - attribute \src "libresoc.v:198188.18-198188.122" - wire $or$libresoc.v:198188$14215_Y - attribute \src "libresoc.v:198189.18-198189.124" - wire $or$libresoc.v:198189$14216_Y - attribute \src "libresoc.v:198190.18-198190.181" - wire width 5 $or$libresoc.v:198190$14217_Y - attribute \src "libresoc.v:198191.18-198191.168" - wire width 4 $or$libresoc.v:198191$14218_Y - attribute \src "libresoc.v:198195.18-198195.120" - wire width 5 $or$libresoc.v:198195$14222_Y - attribute \src "libresoc.v:198205.17-198205.117" - wire width 4 $or$libresoc.v:198205$14232_Y - attribute \src "libresoc.v:198150.17-198150.104" - wire $reduce_and$libresoc.v:198150$14177_Y - attribute \src "libresoc.v:198172.18-198172.106" - wire $reduce_or$libresoc.v:198172$14199_Y - attribute \src "libresoc.v:198175.18-198175.113" - wire $reduce_or$libresoc.v:198175$14202_Y - attribute \src "libresoc.v:198176.18-198176.112" - wire $reduce_or$libresoc.v:198176$14203_Y - attribute \src "libresoc.v:198201.18-198201.118" - wire width 64 $ternary$libresoc.v:198201$14228_Y - attribute \src "libresoc.v:198202.18-198202.118" - wire width 64 $ternary$libresoc.v:198202$14229_Y - attribute \src "libresoc.v:198203.18-198203.118" - wire width 64 $ternary$libresoc.v:198203$14230_Y - attribute \src "libresoc.v:198204.18-198204.118" - wire width 64 $ternary$libresoc.v:198204$14231_Y + attribute \src "libresoc.v:200797.3-200818.6" + wire width 64 $2\data_r0__o$next[63:0]$14516 + attribute \src "libresoc.v:200797.3-200818.6" + wire $2\data_r0__o_ok$next[0:0]$14517 + attribute \src "libresoc.v:200819.3-200840.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14524 + attribute \src "libresoc.v:200819.3-200840.6" + wire $2\data_r1__fast1_ok$next[0:0]$14525 + attribute \src "libresoc.v:200841.3-200862.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14532 + attribute \src "libresoc.v:200841.3-200862.6" + wire $2\data_r2__fast2_ok$next[0:0]$14533 + attribute \src "libresoc.v:200863.3-200884.6" + wire width 64 $2\data_r3__nia$next[63:0]$14540 + attribute \src "libresoc.v:200863.3-200884.6" + wire $2\data_r3__nia_ok$next[0:0]$14541 + attribute \src "libresoc.v:200885.3-200906.6" + wire width 64 $2\data_r4__msr$next[63:0]$14548 + attribute \src "libresoc.v:200885.3-200906.6" + wire $2\data_r4__msr_ok$next[0:0]$14549 + attribute \src "libresoc.v:200797.3-200818.6" + wire $3\data_r0__o_ok$next[0:0]$14518 + attribute \src "libresoc.v:200819.3-200840.6" + wire $3\data_r1__fast1_ok$next[0:0]$14526 + attribute \src "libresoc.v:200841.3-200862.6" + wire $3\data_r2__fast2_ok$next[0:0]$14534 + attribute \src "libresoc.v:200863.3-200884.6" + wire $3\data_r3__nia_ok$next[0:0]$14542 + attribute \src "libresoc.v:200885.3-200906.6" + wire $3\data_r4__msr_ok$next[0:0]$14550 + attribute \src "libresoc.v:200464.18-200464.112" + wire width 4 $and$libresoc.v:200464$14363_Y + attribute \src "libresoc.v:200465.19-200465.125" + wire $and$libresoc.v:200465$14364_Y + attribute \src "libresoc.v:200466.19-200466.125" + wire $and$libresoc.v:200466$14365_Y + attribute \src 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\src "libresoc.v:200500.18-200500.117" + wire $and$libresoc.v:200500$14399_Y + attribute \src "libresoc.v:200505.18-200505.131" + wire $and$libresoc.v:200505$14404_Y + attribute \src "libresoc.v:200506.18-200506.124" + wire width 5 $and$libresoc.v:200506$14405_Y + attribute \src "libresoc.v:200509.18-200509.116" + wire $and$libresoc.v:200509$14408_Y + attribute \src "libresoc.v:200510.18-200510.120" + wire $and$libresoc.v:200510$14409_Y + attribute \src "libresoc.v:200511.18-200511.120" + wire $and$libresoc.v:200511$14410_Y + attribute \src "libresoc.v:200512.18-200512.118" + wire $and$libresoc.v:200512$14411_Y + attribute \src "libresoc.v:200513.18-200513.118" + wire $and$libresoc.v:200513$14412_Y + attribute \src "libresoc.v:200519.18-200519.135" + wire $and$libresoc.v:200519$14418_Y + attribute \src "libresoc.v:200520.18-200520.133" + wire $and$libresoc.v:200520$14419_Y + attribute \src "libresoc.v:200521.18-200521.160" + wire width 4 $and$libresoc.v:200521$14420_Y + attribute \src "libresoc.v:200522.18-200522.112" + wire width 4 $and$libresoc.v:200522$14421_Y + attribute \src "libresoc.v:200495.18-200495.113" + wire $eq$libresoc.v:200495$14394_Y + attribute \src "libresoc.v:200497.18-200497.119" + wire $eq$libresoc.v:200497$14396_Y + attribute \src "libresoc.v:200478.18-200478.97" + wire $not$libresoc.v:200478$14377_Y + attribute \src "libresoc.v:200480.18-200480.99" + wire $not$libresoc.v:200480$14379_Y + attribute \src "libresoc.v:200483.18-200483.113" + wire width 5 $not$libresoc.v:200483$14382_Y + attribute \src "libresoc.v:200486.18-200486.106" + wire $not$libresoc.v:200486$14385_Y + attribute \src "libresoc.v:200492.18-200492.121" + wire $not$libresoc.v:200492$14391_Y + attribute \src "libresoc.v:200507.17-200507.113" + wire width 4 $not$libresoc.v:200507$14406_Y + attribute \src "libresoc.v:200523.18-200523.114" + wire width 4 $not$libresoc.v:200523$14422_Y + attribute \src "libresoc.v:200490.18-200490.112" + wire $or$libresoc.v:200490$14389_Y + attribute \src "libresoc.v:200501.18-200501.122" + wire $or$libresoc.v:200501$14400_Y + attribute \src "libresoc.v:200502.18-200502.124" + wire $or$libresoc.v:200502$14401_Y + attribute \src "libresoc.v:200503.18-200503.181" + wire width 5 $or$libresoc.v:200503$14402_Y + attribute \src "libresoc.v:200504.18-200504.168" + wire width 4 $or$libresoc.v:200504$14403_Y + attribute \src "libresoc.v:200508.18-200508.120" + wire width 5 $or$libresoc.v:200508$14407_Y + attribute \src "libresoc.v:200518.17-200518.117" + wire width 4 $or$libresoc.v:200518$14417_Y + attribute \src "libresoc.v:200463.17-200463.104" + wire $reduce_and$libresoc.v:200463$14362_Y + attribute \src "libresoc.v:200485.18-200485.106" + wire $reduce_or$libresoc.v:200485$14384_Y + attribute \src "libresoc.v:200488.18-200488.113" + wire $reduce_or$libresoc.v:200488$14387_Y + attribute \src "libresoc.v:200489.18-200489.112" + wire $reduce_or$libresoc.v:200489$14388_Y + attribute \src "libresoc.v:200514.18-200514.118" + wire width 64 $ternary$libresoc.v:200514$14413_Y + attribute \src "libresoc.v:200515.18-200515.118" + wire width 64 $ternary$libresoc.v:200515$14414_Y + attribute \src "libresoc.v:200516.18-200516.118" + wire width 64 $ternary$libresoc.v:200516$14415_Y + attribute \src "libresoc.v:200517.18-200517.118" + wire width 64 $ternary$libresoc.v:200517$14416_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -413472,9 +417495,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -413552,7 +417575,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:197550.7-197550.15" + attribute \src "libresoc.v:199863.7-199863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -413757,7 +417780,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198151$14178 + cell $and $and$libresoc.v:200464$14363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413765,10 +417788,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:198151$14178_Y + connect \Y $and$libresoc.v:200464$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198152$14179 + cell $and $and$libresoc.v:200465$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413776,10 +417799,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198152$14179_Y + connect \Y $and$libresoc.v:200465$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198153$14180 + cell $and $and$libresoc.v:200466$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413787,10 +417810,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198153$14180_Y + connect \Y $and$libresoc.v:200466$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198154$14181 + cell $and $and$libresoc.v:200467$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413798,10 +417821,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198154$14181_Y + connect \Y $and$libresoc.v:200467$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198155$14182 + cell $and $and$libresoc.v:200468$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413809,10 +417832,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198155$14182_Y + connect \Y $and$libresoc.v:200468$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:198156$14183 + cell $and $and$libresoc.v:200469$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413820,10 +417843,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:198156$14183_Y + connect \Y $and$libresoc.v:200469$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:198157$14184 + cell $and $and$libresoc.v:200470$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413831,10 +417854,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:198157$14184_Y + connect \Y $and$libresoc.v:200470$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:198158$14185 + cell $and $and$libresoc.v:200471$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413842,10 +417865,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198158$14185_Y + connect \Y $and$libresoc.v:200471$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198159$14186 + cell $and $and$libresoc.v:200472$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413853,10 +417876,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198159$14186_Y + connect \Y $and$libresoc.v:200472$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198160$14187 + cell $and $and$libresoc.v:200473$14372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413864,10 +417887,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198160$14187_Y + connect \Y $and$libresoc.v:200473$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:198161$14188 + cell $and $and$libresoc.v:200474$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413875,10 +417898,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:198161$14188_Y + connect \Y $and$libresoc.v:200474$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198162$14189 + cell $and $and$libresoc.v:200475$14374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413886,10 +417909,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198162$14189_Y + connect \Y $and$libresoc.v:200475$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198163$14190 + cell $and $and$libresoc.v:200476$14375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413897,10 +417920,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198163$14190_Y + connect \Y $and$libresoc.v:200476$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:198164$14191 + cell $and $and$libresoc.v:200477$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413908,10 +417931,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:198164$14191_Y + connect \Y $and$libresoc.v:200477$14376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:198166$14193 + cell $and $and$libresoc.v:200479$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413919,10 +417942,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:198166$14193_Y + connect \Y $and$libresoc.v:200479$14378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:198168$14195 + cell $and $and$libresoc.v:200481$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413930,10 +417953,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:198168$14195_Y + connect \Y $and$libresoc.v:200481$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:198169$14196 + cell $and $and$libresoc.v:200482$14381 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413941,10 +417964,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:198169$14196_Y + connect \Y $and$libresoc.v:200482$14381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:198171$14198 + cell $and $and$libresoc.v:200484$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413952,10 +417975,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:198171$14198_Y + connect \Y $and$libresoc.v:200484$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:198174$14201 + cell $and $and$libresoc.v:200487$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413963,10 +417986,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:198174$14201_Y + connect \Y $and$libresoc.v:200487$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:198178$14205 + cell $and $and$libresoc.v:200491$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413974,10 +417997,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:198178$14205_Y + connect \Y $and$libresoc.v:200491$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:198180$14207 + cell $and $and$libresoc.v:200493$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413985,10 +418008,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:198180$14207_Y + connect \Y $and$libresoc.v:200493$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:198181$14208 + cell $and $and$libresoc.v:200494$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413996,10 +418019,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198181$14208_Y + connect \Y $and$libresoc.v:200494$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:198183$14210 + cell $and $and$libresoc.v:200496$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414007,10 +418030,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:198183$14210_Y + connect \Y $and$libresoc.v:200496$14395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198185$14212 + cell $and $and$libresoc.v:200498$14397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414018,10 +418041,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:198185$14212_Y + connect \Y $and$libresoc.v:200498$14397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198186$14213 + cell $and $and$libresoc.v:200499$14398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414029,10 +418052,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:198186$14213_Y + connect \Y $and$libresoc.v:200499$14398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:198187$14214 + cell $and $and$libresoc.v:200500$14399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414040,10 +418063,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:198187$14214_Y + connect \Y $and$libresoc.v:200500$14399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:198192$14219 + cell $and $and$libresoc.v:200505$14404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414051,10 +418074,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:198192$14219_Y + connect \Y $and$libresoc.v:200505$14404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:198193$14220 + cell $and $and$libresoc.v:200506$14405 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414062,10 +418085,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:198193$14220_Y + connect \Y $and$libresoc.v:200506$14405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198196$14223 + cell $and $and$libresoc.v:200509$14408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414073,10 +418096,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198196$14223_Y + connect \Y $and$libresoc.v:200509$14408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198197$14224 + cell $and $and$libresoc.v:200510$14409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414084,10 +418107,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198197$14224_Y + connect \Y $and$libresoc.v:200510$14409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198198$14225 + cell $and $and$libresoc.v:200511$14410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414095,10 +418118,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198198$14225_Y + connect \Y $and$libresoc.v:200511$14410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198199$14226 + cell $and $and$libresoc.v:200512$14411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414106,10 +418129,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198199$14226_Y + connect \Y $and$libresoc.v:200512$14411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:198200$14227 + cell $and $and$libresoc.v:200513$14412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414117,10 +418140,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:198200$14227_Y + connect \Y $and$libresoc.v:200513$14412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:198206$14233 + cell $and $and$libresoc.v:200519$14418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414128,10 +418151,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:198206$14233_Y + connect \Y $and$libresoc.v:200519$14418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:198207$14234 + cell $and $and$libresoc.v:200520$14419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414139,10 +418162,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:198207$14234_Y + connect \Y $and$libresoc.v:200520$14419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198208$14235 + cell $and $and$libresoc.v:200521$14420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414150,10 +418173,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:198208$14235_Y + connect \Y $and$libresoc.v:200521$14420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:198209$14236 + cell $and $and$libresoc.v:200522$14421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414161,10 +418184,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:198209$14236_Y + connect \Y $and$libresoc.v:200522$14421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:198182$14209 + cell $eq $eq$libresoc.v:200495$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414172,10 +418195,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:198182$14209_Y + connect \Y $eq$libresoc.v:200495$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:198184$14211 + cell $eq $eq$libresoc.v:200497$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414183,66 +418206,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:198184$14211_Y + connect \Y $eq$libresoc.v:200497$14396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:198165$14192 + cell $not $not$libresoc.v:200478$14377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:198165$14192_Y + connect \Y $not$libresoc.v:200478$14377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:198167$14194 + cell $not $not$libresoc.v:200480$14379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:198167$14194_Y + connect \Y $not$libresoc.v:200480$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:198170$14197 + cell $not $not$libresoc.v:200483$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:198170$14197_Y + connect \Y $not$libresoc.v:200483$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:198173$14200 + cell $not $not$libresoc.v:200486$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:198173$14200_Y + connect \Y $not$libresoc.v:200486$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:198179$14206 + cell $not $not$libresoc.v:200492$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:198179$14206_Y + connect \Y $not$libresoc.v:200492$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:198194$14221 + cell $not $not$libresoc.v:200507$14406 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:198194$14221_Y + connect \Y $not$libresoc.v:200507$14406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:198210$14237 + cell $not $not$libresoc.v:200523$14422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:198210$14237_Y + connect \Y $not$libresoc.v:200523$14422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:198177$14204 + cell $or $or$libresoc.v:200490$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414250,10 +418273,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:198177$14204_Y + connect \Y $or$libresoc.v:200490$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:198188$14215 + cell $or $or$libresoc.v:200501$14400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414261,10 +418284,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:198188$14215_Y + connect \Y $or$libresoc.v:200501$14400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:198189$14216 + cell $or $or$libresoc.v:200502$14401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -414272,10 +418295,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:198189$14216_Y + connect \Y $or$libresoc.v:200502$14401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:198190$14217 + cell $or $or$libresoc.v:200503$14402 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414283,10 +418306,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:198190$14217_Y + connect \Y $or$libresoc.v:200503$14402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:198191$14218 + cell $or $or$libresoc.v:200504$14403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414294,10 +418317,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:198191$14218_Y + connect \Y $or$libresoc.v:200504$14403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:198195$14222 + cell $or $or$libresoc.v:200508$14407 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -414305,10 +418328,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:198195$14222_Y + connect \Y $or$libresoc.v:200508$14407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:198205$14232 + cell $or $or$libresoc.v:200518$14417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -414316,74 +418339,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:198205$14232_Y + connect \Y $or$libresoc.v:200518$14417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:198150$14177 + cell $reduce_and $reduce_and$libresoc.v:200463$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:198150$14177_Y + connect \Y $reduce_and$libresoc.v:200463$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:198172$14199 + cell $reduce_or $reduce_or$libresoc.v:200485$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:198172$14199_Y + connect \Y $reduce_or$libresoc.v:200485$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:198175$14202 + cell $reduce_or $reduce_or$libresoc.v:200488$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:198175$14202_Y + connect \Y $reduce_or$libresoc.v:200488$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:198176$14203 + cell $reduce_or $reduce_or$libresoc.v:200489$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:198176$14203_Y + connect \Y $reduce_or$libresoc.v:200489$14388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198201$14228 + cell $mux $ternary$libresoc.v:200514$14413 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:198201$14228_Y + connect \Y $ternary$libresoc.v:200514$14413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198202$14229 + cell $mux $ternary$libresoc.v:200515$14414 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:198202$14229_Y + connect \Y $ternary$libresoc.v:200515$14414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198203$14230 + cell $mux $ternary$libresoc.v:200516$14415 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:198203$14230_Y + connect \Y $ternary$libresoc.v:200516$14415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:198204$14231 + cell $mux $ternary$libresoc.v:200517$14416 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:198204$14231_Y + connect \Y $ternary$libresoc.v:200517$14416_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:198287.14-198293.4" + attribute \src "libresoc.v:200600.14-200606.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414392,7 +418415,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:198294.13-198324.4" + attribute \src "libresoc.v:200607.13-200637.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414425,7 +418448,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:198325.15-198331.4" + attribute \src "libresoc.v:200638.15-200644.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414434,7 +418457,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:198332.14-198338.4" + attribute \src "libresoc.v:200645.14-200651.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414443,7 +418466,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:198339.14-198345.4" + attribute \src "libresoc.v:200652.14-200658.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414452,7 +418475,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:198346.14-198352.4" + attribute \src "libresoc.v:200659.14-200665.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414461,7 +418484,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:198353.14-198358.4" + attribute \src "libresoc.v:200666.14-200671.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414469,7 +418492,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:198359.14-198365.4" + attribute \src "libresoc.v:200672.14-200678.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -414477,592 +418500,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:197550.7-197550.20" - process $proc$libresoc.v:197550$14392 + attribute \src "libresoc.v:199863.7-199863.20" + process $proc$libresoc.v:199863$14577 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:197676.7-197676.24" - process $proc$libresoc.v:197676$14393 + attribute \src "libresoc.v:199989.7-199989.24" + process $proc$libresoc.v:199989$14578 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:197686.7-197686.26" - process $proc$libresoc.v:197686$14394 + attribute \src "libresoc.v:199999.7-199999.26" + process $proc$libresoc.v:199999$14579 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:197694.7-197694.25" - process $proc$libresoc.v:197694$14395 + attribute \src "libresoc.v:200007.7-200007.25" + process $proc$libresoc.v:200007$14580 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:197730.14-197730.59" - process $proc$libresoc.v:197730$14396 + attribute \src "libresoc.v:200043.14-200043.59" + process $proc$libresoc.v:200043$14581 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:197749.14-197749.51" - process $proc$libresoc.v:197749$14397 + attribute \src "libresoc.v:200062.14-200062.51" + process $proc$libresoc.v:200062$14582 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:197753.14-197753.45" - process $proc$libresoc.v:197753$14398 + attribute \src "libresoc.v:200066.14-200066.45" + process $proc$libresoc.v:200066$14583 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:197832.13-197832.49" - process $proc$libresoc.v:197832$14399 + attribute \src "libresoc.v:200145.13-200145.49" + process $proc$libresoc.v:200145$14584 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:197836.7-197836.41" - process $proc$libresoc.v:197836$14400 + attribute \src "libresoc.v:200149.7-200149.41" + process $proc$libresoc.v:200149$14585 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:197840.13-197840.48" - process $proc$libresoc.v:197840$14401 + attribute \src "libresoc.v:200153.13-200153.48" + process $proc$libresoc.v:200153$14586 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:197844.14-197844.59" - process $proc$libresoc.v:197844$14402 + attribute \src "libresoc.v:200157.14-200157.59" + process $proc$libresoc.v:200157$14587 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:197848.14-197848.52" - process $proc$libresoc.v:197848$14403 + attribute \src "libresoc.v:200161.14-200161.52" + process $proc$libresoc.v:200161$14588 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:197852.13-197852.48" - process $proc$libresoc.v:197852$14404 + attribute \src "libresoc.v:200165.13-200165.48" + process $proc$libresoc.v:200165$14589 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:197858.7-197858.27" - process $proc$libresoc.v:197858$14405 + attribute \src "libresoc.v:200171.7-200171.27" + process $proc$libresoc.v:200171$14590 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:197890.14-197890.47" - process $proc$libresoc.v:197890$14406 + attribute \src "libresoc.v:200203.14-200203.47" + process $proc$libresoc.v:200203$14591 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:197894.7-197894.27" - process $proc$libresoc.v:197894$14407 + attribute \src "libresoc.v:200207.7-200207.27" + process $proc$libresoc.v:200207$14592 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:197898.14-197898.51" - process $proc$libresoc.v:197898$14408 + attribute \src "libresoc.v:200211.14-200211.51" + process $proc$libresoc.v:200211$14593 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:197902.7-197902.31" - process $proc$libresoc.v:197902$14409 + attribute \src "libresoc.v:200215.7-200215.31" + process $proc$libresoc.v:200215$14594 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:197906.14-197906.51" - process $proc$libresoc.v:197906$14410 + attribute \src "libresoc.v:200219.14-200219.51" + process $proc$libresoc.v:200219$14595 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:197910.7-197910.31" - process $proc$libresoc.v:197910$14411 + attribute \src "libresoc.v:200223.7-200223.31" + process $proc$libresoc.v:200223$14596 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:197914.14-197914.49" - process $proc$libresoc.v:197914$14412 + attribute \src "libresoc.v:200227.14-200227.49" + process $proc$libresoc.v:200227$14597 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:197918.7-197918.29" - process $proc$libresoc.v:197918$14413 + attribute \src "libresoc.v:200231.7-200231.29" + process $proc$libresoc.v:200231$14598 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:197922.14-197922.49" - process $proc$libresoc.v:197922$14414 + attribute \src "libresoc.v:200235.14-200235.49" + process $proc$libresoc.v:200235$14599 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:197926.7-197926.29" - process $proc$libresoc.v:197926$14415 + attribute \src "libresoc.v:200239.7-200239.29" + process $proc$libresoc.v:200239$14600 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:197957.7-197957.25" - process $proc$libresoc.v:197957$14416 + attribute \src "libresoc.v:200270.7-200270.25" + process $proc$libresoc.v:200270$14601 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:197961.7-197961.25" - process $proc$libresoc.v:197961$14417 + attribute \src "libresoc.v:200274.7-200274.25" + process $proc$libresoc.v:200274$14602 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:198073.13-198073.31" - process $proc$libresoc.v:198073$14418 + attribute \src "libresoc.v:200386.13-200386.31" + process $proc$libresoc.v:200386$14603 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:198081.13-198081.32" - process $proc$libresoc.v:198081$14419 + attribute \src "libresoc.v:200394.13-200394.32" + process $proc$libresoc.v:200394$14604 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:198085.13-198085.32" - process $proc$libresoc.v:198085$14420 + attribute \src "libresoc.v:200398.13-200398.32" + process $proc$libresoc.v:200398$14605 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:198097.7-198097.26" - process $proc$libresoc.v:198097$14421 + attribute \src "libresoc.v:200410.7-200410.26" + process $proc$libresoc.v:200410$14606 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:198101.7-198101.26" - process $proc$libresoc.v:198101$14422 + attribute \src "libresoc.v:200414.7-200414.26" + process $proc$libresoc.v:200414$14607 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:198105.7-198105.25" - process $proc$libresoc.v:198105$14423 + attribute \src "libresoc.v:200418.7-200418.25" + process $proc$libresoc.v:200418$14608 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:198109.7-198109.25" - process $proc$libresoc.v:198109$14424 + attribute \src "libresoc.v:200422.7-200422.25" + process $proc$libresoc.v:200422$14609 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:198125.13-198125.31" - process $proc$libresoc.v:198125$14425 + attribute \src "libresoc.v:200438.13-200438.31" + process $proc$libresoc.v:200438$14610 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:198129.13-198129.31" - process $proc$libresoc.v:198129$14426 + attribute \src "libresoc.v:200442.13-200442.31" + process $proc$libresoc.v:200442$14611 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:198133.14-198133.43" - process $proc$libresoc.v:198133$14427 + attribute \src "libresoc.v:200446.14-200446.43" + process $proc$libresoc.v:200446$14612 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:198137.14-198137.43" - process $proc$libresoc.v:198137$14428 + attribute \src "libresoc.v:200450.14-200450.43" + process $proc$libresoc.v:200450$14613 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:198141.14-198141.43" - process $proc$libresoc.v:198141$14429 + attribute \src "libresoc.v:200454.14-200454.43" + process $proc$libresoc.v:200454$14614 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:198145.14-198145.43" - process $proc$libresoc.v:198145$14430 + attribute \src "libresoc.v:200458.14-200458.43" + process $proc$libresoc.v:200458$14615 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:198211.3-198212.39" - process $proc$libresoc.v:198211$14238 + attribute \src "libresoc.v:200524.3-200525.39" + process $proc$libresoc.v:200524$14423 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:198213.3-198214.43" - process $proc$libresoc.v:198213$14239 + attribute \src "libresoc.v:200526.3-200527.43" + process $proc$libresoc.v:200526$14424 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:198215.3-198216.29" - process $proc$libresoc.v:198215$14240 + attribute \src "libresoc.v:200528.3-200529.29" + process $proc$libresoc.v:200528$14425 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:198217.3-198218.29" - process $proc$libresoc.v:198217$14241 + attribute \src "libresoc.v:200530.3-200531.29" + process $proc$libresoc.v:200530$14426 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:198219.3-198220.29" - process $proc$libresoc.v:198219$14242 + attribute \src "libresoc.v:200532.3-200533.29" + process $proc$libresoc.v:200532$14427 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:198221.3-198222.29" - process $proc$libresoc.v:198221$14243 + attribute \src "libresoc.v:200534.3-200535.29" + process $proc$libresoc.v:200534$14428 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:198223.3-198224.41" - process $proc$libresoc.v:198223$14244 + attribute \src "libresoc.v:200536.3-200537.41" + process $proc$libresoc.v:200536$14429 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:198225.3-198226.47" - process $proc$libresoc.v:198225$14245 + attribute \src "libresoc.v:200538.3-200539.47" + process $proc$libresoc.v:200538$14430 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:198227.3-198228.41" - process $proc$libresoc.v:198227$14246 + attribute \src "libresoc.v:200540.3-200541.41" + process $proc$libresoc.v:200540$14431 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:198229.3-198230.47" - process $proc$libresoc.v:198229$14247 + attribute \src "libresoc.v:200542.3-200543.47" + process $proc$libresoc.v:200542$14432 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:198231.3-198232.45" - process $proc$libresoc.v:198231$14248 + attribute \src "libresoc.v:200544.3-200545.45" + process $proc$libresoc.v:200544$14433 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:198233.3-198234.51" - process $proc$libresoc.v:198233$14249 + attribute \src "libresoc.v:200546.3-200547.51" + process $proc$libresoc.v:200546$14434 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:198235.3-198236.45" - process $proc$libresoc.v:198235$14250 + attribute \src "libresoc.v:200548.3-200549.45" + process $proc$libresoc.v:200548$14435 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:198237.3-198238.51" - process $proc$libresoc.v:198237$14251 + attribute \src "libresoc.v:200550.3-200551.51" + process $proc$libresoc.v:200550$14436 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:198239.3-198240.37" - process $proc$libresoc.v:198239$14252 + attribute \src "libresoc.v:200552.3-200553.37" + process $proc$libresoc.v:200552$14437 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:198241.3-198242.43" - process $proc$libresoc.v:198241$14253 + attribute \src "libresoc.v:200554.3-200555.43" + process $proc$libresoc.v:200554$14438 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:198243.3-198244.73" - process $proc$libresoc.v:198243$14254 + attribute \src "libresoc.v:200556.3-200557.73" + process $proc$libresoc.v:200556$14439 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:198245.3-198246.69" - process $proc$libresoc.v:198245$14255 + attribute \src "libresoc.v:200558.3-200559.69" + process $proc$libresoc.v:200558$14440 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:198247.3-198248.63" - process $proc$libresoc.v:198247$14256 + attribute \src "libresoc.v:200560.3-200561.63" + process $proc$libresoc.v:200560$14441 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:198249.3-198250.61" - process $proc$libresoc.v:198249$14257 + attribute \src "libresoc.v:200562.3-200563.61" + process $proc$libresoc.v:200562$14442 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:198251.3-198252.61" - process $proc$libresoc.v:198251$14258 + attribute \src "libresoc.v:200564.3-200565.61" + process $proc$libresoc.v:200564$14443 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:198253.3-198254.71" - process $proc$libresoc.v:198253$14259 + attribute \src "libresoc.v:200566.3-200567.71" + process $proc$libresoc.v:200566$14444 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:198255.3-198256.71" - process $proc$libresoc.v:198255$14260 + attribute \src "libresoc.v:200568.3-200569.71" + process $proc$libresoc.v:200568$14445 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:198257.3-198258.71" - process $proc$libresoc.v:198257$14261 + attribute \src "libresoc.v:200570.3-200571.71" + process $proc$libresoc.v:200570$14446 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:198259.3-198260.71" - process $proc$libresoc.v:198259$14262 + attribute \src "libresoc.v:200572.3-200573.71" + process $proc$libresoc.v:200572$14447 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:198261.3-198262.39" - process $proc$libresoc.v:198261$14263 + attribute \src "libresoc.v:200574.3-200575.39" + process $proc$libresoc.v:200574$14448 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:198263.3-198264.39" - process $proc$libresoc.v:198263$14264 + attribute \src "libresoc.v:200576.3-200577.39" + process $proc$libresoc.v:200576$14449 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:198265.3-198266.39" - process $proc$libresoc.v:198265$14265 + attribute \src "libresoc.v:200578.3-200579.39" + process $proc$libresoc.v:200578$14450 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:198267.3-198268.39" - process $proc$libresoc.v:198267$14266 + attribute \src "libresoc.v:200580.3-200581.39" + process $proc$libresoc.v:200580$14451 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:198269.3-198270.39" - process $proc$libresoc.v:198269$14267 + attribute \src "libresoc.v:200582.3-200583.39" + process $proc$libresoc.v:200582$14452 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:198271.3-198272.39" - process $proc$libresoc.v:198271$14268 + attribute \src "libresoc.v:200584.3-200585.39" + process $proc$libresoc.v:200584$14453 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:198273.3-198274.39" - process $proc$libresoc.v:198273$14269 + attribute \src "libresoc.v:200586.3-200587.39" + process $proc$libresoc.v:200586$14454 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:198275.3-198276.39" - process $proc$libresoc.v:198275$14270 + attribute \src "libresoc.v:200588.3-200589.39" + process $proc$libresoc.v:200588$14455 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:198277.3-198278.41" - process $proc$libresoc.v:198277$14271 + attribute \src "libresoc.v:200590.3-200591.41" + process $proc$libresoc.v:200590$14456 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:198279.3-198280.41" - process $proc$libresoc.v:198279$14272 + attribute \src "libresoc.v:200592.3-200593.41" + process $proc$libresoc.v:200592$14457 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:198281.3-198282.37" - process $proc$libresoc.v:198281$14273 + attribute \src "libresoc.v:200594.3-200595.37" + process $proc$libresoc.v:200594$14458 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:198283.3-198284.41" - process $proc$libresoc.v:198283$14274 + attribute \src "libresoc.v:200596.3-200597.41" + process $proc$libresoc.v:200596$14459 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:198285.3-198286.25" - process $proc$libresoc.v:198285$14275 + attribute \src "libresoc.v:200598.3-200599.25" + process $proc$libresoc.v:200598$14460 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:198366.3-198375.6" - process $proc$libresoc.v:198366$14276 + attribute \src "libresoc.v:200679.3-200688.6" + process $proc$libresoc.v:200679$14461 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:198367.5-198367.29" + attribute \src "libresoc.v:200680.5-200680.29" switch \initial - attribute \src "libresoc.v:198367.9-198367.17" + attribute \src "libresoc.v:200680.9-200680.17" case 1'1 case end @@ -415078,14 +419101,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:198376.3-198384.6" - process $proc$libresoc.v:198376$14277 + attribute \src "libresoc.v:200689.3-200697.6" + process $proc$libresoc.v:200689$14462 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14278 $1\rok_l_s_rdok$next[0:0]$14279 - attribute \src "libresoc.v:198377.5-198377.29" + assign $0\rok_l_s_rdok$next[0:0]$14463 $1\rok_l_s_rdok$next[0:0]$14464 + attribute \src "libresoc.v:200690.5-200690.29" switch \initial - attribute \src "libresoc.v:198377.9-198377.17" + attribute \src "libresoc.v:200690.9-200690.17" case 1'1 case end @@ -415094,21 +419117,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14279 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14464 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14279 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14464 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14278 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14463 end - attribute \src "libresoc.v:198385.3-198393.6" - process $proc$libresoc.v:198385$14280 + attribute \src "libresoc.v:200698.3-200706.6" + process $proc$libresoc.v:200698$14465 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14281 $1\rok_l_r_rdok$next[0:0]$14282 - attribute \src "libresoc.v:198386.5-198386.29" + assign $0\rok_l_r_rdok$next[0:0]$14466 $1\rok_l_r_rdok$next[0:0]$14467 + attribute \src "libresoc.v:200699.5-200699.29" switch \initial - attribute \src "libresoc.v:198386.9-198386.17" + attribute \src "libresoc.v:200699.9-200699.17" case 1'1 case end @@ -415117,21 +419140,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14282 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14467 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14282 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14467 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14281 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14466 end - attribute \src "libresoc.v:198394.3-198402.6" - process $proc$libresoc.v:198394$14283 + attribute \src "libresoc.v:200707.3-200715.6" + process $proc$libresoc.v:200707$14468 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14284 $1\rst_l_s_rst$next[0:0]$14285 - attribute \src "libresoc.v:198395.5-198395.29" + assign $0\rst_l_s_rst$next[0:0]$14469 $1\rst_l_s_rst$next[0:0]$14470 + attribute \src "libresoc.v:200708.5-200708.29" switch \initial - attribute \src "libresoc.v:198395.9-198395.17" + attribute \src "libresoc.v:200708.9-200708.17" case 1'1 case end @@ -415140,21 +419163,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14285 1'0 + assign $1\rst_l_s_rst$next[0:0]$14470 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14285 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14470 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14284 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14469 end - attribute \src "libresoc.v:198403.3-198411.6" - process $proc$libresoc.v:198403$14286 + attribute \src "libresoc.v:200716.3-200724.6" + process $proc$libresoc.v:200716$14471 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14287 $1\rst_l_r_rst$next[0:0]$14288 - attribute \src "libresoc.v:198404.5-198404.29" + assign $0\rst_l_r_rst$next[0:0]$14472 $1\rst_l_r_rst$next[0:0]$14473 + attribute \src "libresoc.v:200717.5-200717.29" switch \initial - attribute \src "libresoc.v:198404.9-198404.17" + attribute \src "libresoc.v:200717.9-200717.17" case 1'1 case end @@ -415163,21 +419186,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14288 1'1 + assign $1\rst_l_r_rst$next[0:0]$14473 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14288 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14473 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14287 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14472 end - attribute \src "libresoc.v:198412.3-198420.6" - process $proc$libresoc.v:198412$14289 + attribute \src "libresoc.v:200725.3-200733.6" + process $proc$libresoc.v:200725$14474 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14290 $1\opc_l_s_opc$next[0:0]$14291 - attribute \src "libresoc.v:198413.5-198413.29" + assign $0\opc_l_s_opc$next[0:0]$14475 $1\opc_l_s_opc$next[0:0]$14476 + attribute \src "libresoc.v:200726.5-200726.29" switch \initial - attribute \src "libresoc.v:198413.9-198413.17" + attribute \src "libresoc.v:200726.9-200726.17" case 1'1 case end @@ -415186,21 +419209,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14291 1'0 + assign $1\opc_l_s_opc$next[0:0]$14476 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14291 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14476 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14290 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14475 end - attribute \src "libresoc.v:198421.3-198429.6" - process $proc$libresoc.v:198421$14292 + attribute \src "libresoc.v:200734.3-200742.6" + process $proc$libresoc.v:200734$14477 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14293 $1\opc_l_r_opc$next[0:0]$14294 - attribute \src "libresoc.v:198422.5-198422.29" + assign $0\opc_l_r_opc$next[0:0]$14478 $1\opc_l_r_opc$next[0:0]$14479 + attribute \src "libresoc.v:200735.5-200735.29" switch \initial - attribute \src "libresoc.v:198422.9-198422.17" + attribute \src "libresoc.v:200735.9-200735.17" case 1'1 case end @@ -415209,21 +419232,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14294 1'1 + assign $1\opc_l_r_opc$next[0:0]$14479 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14294 \req_done + assign $1\opc_l_r_opc$next[0:0]$14479 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14293 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14478 end - attribute \src "libresoc.v:198430.3-198438.6" - process $proc$libresoc.v:198430$14295 + attribute \src "libresoc.v:200743.3-200751.6" + process $proc$libresoc.v:200743$14480 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14296 $1\src_l_s_src$next[3:0]$14297 - attribute \src "libresoc.v:198431.5-198431.29" + assign $0\src_l_s_src$next[3:0]$14481 $1\src_l_s_src$next[3:0]$14482 + attribute \src "libresoc.v:200744.5-200744.29" switch \initial - attribute \src "libresoc.v:198431.9-198431.17" + attribute \src "libresoc.v:200744.9-200744.17" case 1'1 case end @@ -415232,21 +419255,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14297 4'0000 + assign $1\src_l_s_src$next[3:0]$14482 4'0000 case - assign $1\src_l_s_src$next[3:0]$14297 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14482 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14296 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14481 end - attribute \src "libresoc.v:198439.3-198447.6" - process $proc$libresoc.v:198439$14298 + attribute \src "libresoc.v:200752.3-200760.6" + process $proc$libresoc.v:200752$14483 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14299 $1\src_l_r_src$next[3:0]$14300 - attribute \src "libresoc.v:198440.5-198440.29" + assign $0\src_l_r_src$next[3:0]$14484 $1\src_l_r_src$next[3:0]$14485 + attribute \src "libresoc.v:200753.5-200753.29" switch \initial - attribute \src "libresoc.v:198440.9-198440.17" + attribute \src "libresoc.v:200753.9-200753.17" case 1'1 case end @@ -415255,21 +419278,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14300 4'1111 + assign $1\src_l_r_src$next[3:0]$14485 4'1111 case - assign $1\src_l_r_src$next[3:0]$14300 \reset_r + assign $1\src_l_r_src$next[3:0]$14485 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14299 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14484 end - attribute \src "libresoc.v:198448.3-198456.6" - process $proc$libresoc.v:198448$14301 + attribute \src "libresoc.v:200761.3-200769.6" + process $proc$libresoc.v:200761$14486 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14302 $1\req_l_s_req$next[4:0]$14303 - attribute \src "libresoc.v:198449.5-198449.29" + assign $0\req_l_s_req$next[4:0]$14487 $1\req_l_s_req$next[4:0]$14488 + attribute \src "libresoc.v:200762.5-200762.29" switch \initial - attribute \src "libresoc.v:198449.9-198449.17" + attribute \src "libresoc.v:200762.9-200762.17" case 1'1 case end @@ -415278,21 +419301,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14303 5'00000 + assign $1\req_l_s_req$next[4:0]$14488 5'00000 case - assign $1\req_l_s_req$next[4:0]$14303 \$67 + assign $1\req_l_s_req$next[4:0]$14488 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14302 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14487 end - attribute \src "libresoc.v:198457.3-198465.6" - process $proc$libresoc.v:198457$14304 + attribute \src "libresoc.v:200770.3-200778.6" + process $proc$libresoc.v:200770$14489 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14305 $1\req_l_r_req$next[4:0]$14306 - attribute \src "libresoc.v:198458.5-198458.29" + assign $0\req_l_r_req$next[4:0]$14490 $1\req_l_r_req$next[4:0]$14491 + attribute \src "libresoc.v:200771.5-200771.29" switch \initial - attribute \src "libresoc.v:198458.9-198458.17" + attribute \src "libresoc.v:200771.9-200771.17" case 1'1 case end @@ -415301,15 +419324,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14306 5'11111 + assign $1\req_l_r_req$next[4:0]$14491 5'11111 case - assign $1\req_l_r_req$next[4:0]$14306 \$69 + assign $1\req_l_r_req$next[4:0]$14491 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14305 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14490 end - attribute \src "libresoc.v:198466.3-198483.6" - process $proc$libresoc.v:198466$14307 + attribute \src "libresoc.v:200779.3-200796.6" + process $proc$libresoc.v:200779$14492 assign { } { } assign { } { } assign { } { } @@ -415328,18 +419351,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14308 $1\alu_trap0_trap_op__cia$next[63:0]$14317 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14310 $1\alu_trap0_trap_op__insn$next[31:0]$14319 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14314 $1\alu_trap0_trap_op__msr$next[63:0]$14323 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14316 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 - attribute \src "libresoc.v:198467.5-198467.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14493 $1\alu_trap0_trap_op__cia$next[63:0]$14502 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14495 $1\alu_trap0_trap_op__insn$next[31:0]$14504 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14499 $1\alu_trap0_trap_op__msr$next[63:0]$14508 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14501 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 + attribute \src "libresoc.v:200780.5-200780.29" switch \initial - attribute \src "libresoc.v:198467.9-198467.17" + attribute \src "libresoc.v:200780.9-200780.17" case 1'1 case end @@ -415356,43 +419379,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 $1\alu_trap0_trap_op__traptype$next[7:0]$14325 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 $1\alu_trap0_trap_op__cia$next[63:0]$14317 $1\alu_trap0_trap_op__msr$next[63:0]$14323 $1\alu_trap0_trap_op__insn$next[31:0]$14319 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 $1\alu_trap0_trap_op__cia$next[63:0]$14502 $1\alu_trap0_trap_op__msr$next[63:0]$14508 $1\alu_trap0_trap_op__insn$next[31:0]$14504 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14317 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14318 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14319 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14320 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14321 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14322 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14323 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14324 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14325 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14502 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14504 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14508 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14510 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14308 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14309 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14310 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14311 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14312 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14313 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14314 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14315 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14316 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14493 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14495 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14499 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14501 end - attribute \src "libresoc.v:198484.3-198505.6" - process $proc$libresoc.v:198484$14326 + attribute \src "libresoc.v:200797.3-200818.6" + process $proc$libresoc.v:200797$14511 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14327 $2\data_r0__o$next[63:0]$14331 + assign $0\data_r0__o$next[63:0]$14512 $2\data_r0__o$next[63:0]$14516 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14328 $3\data_r0__o_ok$next[0:0]$14333 - attribute \src "libresoc.v:198485.5-198485.29" + assign $0\data_r0__o_ok$next[0:0]$14513 $3\data_r0__o_ok$next[0:0]$14518 + attribute \src "libresoc.v:200798.5-200798.29" switch \initial - attribute \src "libresoc.v:198485.9-198485.17" + attribute \src "libresoc.v:200798.9-200798.17" case 1'1 case end @@ -415402,10 +419425,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14330 $1\data_r0__o$next[63:0]$14329 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14515 $1\data_r0__o$next[63:0]$14514 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14329 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14330 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14514 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14515 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415413,38 +419436,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14332 $2\data_r0__o$next[63:0]$14331 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14517 $2\data_r0__o$next[63:0]$14516 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14331 $1\data_r0__o$next[63:0]$14329 - assign $2\data_r0__o_ok$next[0:0]$14332 $1\data_r0__o_ok$next[0:0]$14330 + assign $2\data_r0__o$next[63:0]$14516 $1\data_r0__o$next[63:0]$14514 + assign $2\data_r0__o_ok$next[0:0]$14517 $1\data_r0__o_ok$next[0:0]$14515 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14333 1'0 + assign $3\data_r0__o_ok$next[0:0]$14518 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14333 $2\data_r0__o_ok$next[0:0]$14332 + assign $3\data_r0__o_ok$next[0:0]$14518 $2\data_r0__o_ok$next[0:0]$14517 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14327 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14328 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14512 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14513 end - attribute \src "libresoc.v:198506.3-198527.6" - process $proc$libresoc.v:198506$14334 + attribute \src "libresoc.v:200819.3-200840.6" + process $proc$libresoc.v:200819$14519 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14335 $2\data_r1__fast1$next[63:0]$14339 + assign $0\data_r1__fast1$next[63:0]$14520 $2\data_r1__fast1$next[63:0]$14524 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14336 $3\data_r1__fast1_ok$next[0:0]$14341 - attribute \src "libresoc.v:198507.5-198507.29" + assign $0\data_r1__fast1_ok$next[0:0]$14521 $3\data_r1__fast1_ok$next[0:0]$14526 + attribute \src "libresoc.v:200820.5-200820.29" switch \initial - attribute \src "libresoc.v:198507.9-198507.17" + attribute \src "libresoc.v:200820.9-200820.17" case 1'1 case end @@ -415454,10 +419477,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14338 $1\data_r1__fast1$next[63:0]$14337 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14523 $1\data_r1__fast1$next[63:0]$14522 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14337 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14338 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14522 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14523 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415465,38 +419488,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14340 $2\data_r1__fast1$next[63:0]$14339 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14525 $2\data_r1__fast1$next[63:0]$14524 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14339 $1\data_r1__fast1$next[63:0]$14337 - assign $2\data_r1__fast1_ok$next[0:0]$14340 $1\data_r1__fast1_ok$next[0:0]$14338 + assign $2\data_r1__fast1$next[63:0]$14524 $1\data_r1__fast1$next[63:0]$14522 + assign $2\data_r1__fast1_ok$next[0:0]$14525 $1\data_r1__fast1_ok$next[0:0]$14523 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14341 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14526 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14341 $2\data_r1__fast1_ok$next[0:0]$14340 + assign $3\data_r1__fast1_ok$next[0:0]$14526 $2\data_r1__fast1_ok$next[0:0]$14525 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14335 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14336 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14520 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14521 end - attribute \src "libresoc.v:198528.3-198549.6" - process $proc$libresoc.v:198528$14342 + attribute \src "libresoc.v:200841.3-200862.6" + process $proc$libresoc.v:200841$14527 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14343 $2\data_r2__fast2$next[63:0]$14347 + assign $0\data_r2__fast2$next[63:0]$14528 $2\data_r2__fast2$next[63:0]$14532 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14344 $3\data_r2__fast2_ok$next[0:0]$14349 - attribute \src "libresoc.v:198529.5-198529.29" + assign $0\data_r2__fast2_ok$next[0:0]$14529 $3\data_r2__fast2_ok$next[0:0]$14534 + attribute \src "libresoc.v:200842.5-200842.29" switch \initial - attribute \src "libresoc.v:198529.9-198529.17" + attribute \src "libresoc.v:200842.9-200842.17" case 1'1 case end @@ -415506,10 +419529,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14346 $1\data_r2__fast2$next[63:0]$14345 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14531 $1\data_r2__fast2$next[63:0]$14530 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14345 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14346 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14530 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14531 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415517,38 +419540,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14348 $2\data_r2__fast2$next[63:0]$14347 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14533 $2\data_r2__fast2$next[63:0]$14532 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14347 $1\data_r2__fast2$next[63:0]$14345 - assign $2\data_r2__fast2_ok$next[0:0]$14348 $1\data_r2__fast2_ok$next[0:0]$14346 + assign $2\data_r2__fast2$next[63:0]$14532 $1\data_r2__fast2$next[63:0]$14530 + assign $2\data_r2__fast2_ok$next[0:0]$14533 $1\data_r2__fast2_ok$next[0:0]$14531 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14349 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14534 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14349 $2\data_r2__fast2_ok$next[0:0]$14348 + assign $3\data_r2__fast2_ok$next[0:0]$14534 $2\data_r2__fast2_ok$next[0:0]$14533 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14343 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14344 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14528 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14529 end - attribute \src "libresoc.v:198550.3-198571.6" - process $proc$libresoc.v:198550$14350 + attribute \src "libresoc.v:200863.3-200884.6" + process $proc$libresoc.v:200863$14535 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14351 $2\data_r3__nia$next[63:0]$14355 + assign $0\data_r3__nia$next[63:0]$14536 $2\data_r3__nia$next[63:0]$14540 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14352 $3\data_r3__nia_ok$next[0:0]$14357 - attribute \src "libresoc.v:198551.5-198551.29" + assign $0\data_r3__nia_ok$next[0:0]$14537 $3\data_r3__nia_ok$next[0:0]$14542 + attribute \src "libresoc.v:200864.5-200864.29" switch \initial - attribute \src "libresoc.v:198551.9-198551.17" + attribute \src "libresoc.v:200864.9-200864.17" case 1'1 case end @@ -415558,10 +419581,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14354 $1\data_r3__nia$next[63:0]$14353 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14539 $1\data_r3__nia$next[63:0]$14538 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14353 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14354 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14538 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14539 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415569,38 +419592,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14356 $2\data_r3__nia$next[63:0]$14355 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14541 $2\data_r3__nia$next[63:0]$14540 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14355 $1\data_r3__nia$next[63:0]$14353 - assign $2\data_r3__nia_ok$next[0:0]$14356 $1\data_r3__nia_ok$next[0:0]$14354 + assign $2\data_r3__nia$next[63:0]$14540 $1\data_r3__nia$next[63:0]$14538 + assign $2\data_r3__nia_ok$next[0:0]$14541 $1\data_r3__nia_ok$next[0:0]$14539 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14357 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14542 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14357 $2\data_r3__nia_ok$next[0:0]$14356 + assign $3\data_r3__nia_ok$next[0:0]$14542 $2\data_r3__nia_ok$next[0:0]$14541 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14351 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14352 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14536 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14537 end - attribute \src "libresoc.v:198572.3-198593.6" - process $proc$libresoc.v:198572$14358 + attribute \src "libresoc.v:200885.3-200906.6" + process $proc$libresoc.v:200885$14543 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14359 $2\data_r4__msr$next[63:0]$14363 + assign $0\data_r4__msr$next[63:0]$14544 $2\data_r4__msr$next[63:0]$14548 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14360 $3\data_r4__msr_ok$next[0:0]$14365 - attribute \src "libresoc.v:198573.5-198573.29" + assign $0\data_r4__msr_ok$next[0:0]$14545 $3\data_r4__msr_ok$next[0:0]$14550 + attribute \src "libresoc.v:200886.5-200886.29" switch \initial - attribute \src "libresoc.v:198573.9-198573.17" + attribute \src "libresoc.v:200886.9-200886.17" case 1'1 case end @@ -415610,10 +419633,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14362 $1\data_r4__msr$next[63:0]$14361 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14547 $1\data_r4__msr$next[63:0]$14546 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14361 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14362 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14546 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14547 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -415621,32 +419644,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14364 $2\data_r4__msr$next[63:0]$14363 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14549 $2\data_r4__msr$next[63:0]$14548 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14363 $1\data_r4__msr$next[63:0]$14361 - assign $2\data_r4__msr_ok$next[0:0]$14364 $1\data_r4__msr_ok$next[0:0]$14362 + assign $2\data_r4__msr$next[63:0]$14548 $1\data_r4__msr$next[63:0]$14546 + assign $2\data_r4__msr_ok$next[0:0]$14549 $1\data_r4__msr_ok$next[0:0]$14547 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14365 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14550 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14365 $2\data_r4__msr_ok$next[0:0]$14364 + assign $3\data_r4__msr_ok$next[0:0]$14550 $2\data_r4__msr_ok$next[0:0]$14549 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14359 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14360 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14544 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14545 end - attribute \src "libresoc.v:198594.3-198603.6" - process $proc$libresoc.v:198594$14366 + attribute \src "libresoc.v:200907.3-200916.6" + process $proc$libresoc.v:200907$14551 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14367 $1\src_r0$next[63:0]$14368 - attribute \src "libresoc.v:198595.5-198595.29" + assign $0\src_r0$next[63:0]$14552 $1\src_r0$next[63:0]$14553 + attribute \src "libresoc.v:200908.5-200908.29" switch \initial - attribute \src "libresoc.v:198595.9-198595.17" + attribute \src "libresoc.v:200908.9-200908.17" case 1'1 case end @@ -415655,21 +419678,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14368 \src1_i + assign $1\src_r0$next[63:0]$14553 \src1_i case - assign $1\src_r0$next[63:0]$14368 \src_r0 + assign $1\src_r0$next[63:0]$14553 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14367 + update \src_r0$next $0\src_r0$next[63:0]$14552 end - attribute \src "libresoc.v:198604.3-198613.6" - process $proc$libresoc.v:198604$14369 + attribute \src "libresoc.v:200917.3-200926.6" + process $proc$libresoc.v:200917$14554 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14370 $1\src_r1$next[63:0]$14371 - attribute \src "libresoc.v:198605.5-198605.29" + assign $0\src_r1$next[63:0]$14555 $1\src_r1$next[63:0]$14556 + attribute \src "libresoc.v:200918.5-200918.29" switch \initial - attribute \src "libresoc.v:198605.9-198605.17" + attribute \src "libresoc.v:200918.9-200918.17" case 1'1 case end @@ -415678,21 +419701,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14371 \src2_i + assign $1\src_r1$next[63:0]$14556 \src2_i case - assign $1\src_r1$next[63:0]$14371 \src_r1 + assign $1\src_r1$next[63:0]$14556 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14370 + update \src_r1$next $0\src_r1$next[63:0]$14555 end - attribute \src "libresoc.v:198614.3-198623.6" - process $proc$libresoc.v:198614$14372 + attribute \src "libresoc.v:200927.3-200936.6" + process $proc$libresoc.v:200927$14557 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14373 $1\src_r2$next[63:0]$14374 - attribute \src "libresoc.v:198615.5-198615.29" + assign $0\src_r2$next[63:0]$14558 $1\src_r2$next[63:0]$14559 + attribute \src "libresoc.v:200928.5-200928.29" switch \initial - attribute \src "libresoc.v:198615.9-198615.17" + attribute \src "libresoc.v:200928.9-200928.17" case 1'1 case end @@ -415701,21 +419724,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14374 \src3_i + assign $1\src_r2$next[63:0]$14559 \src3_i case - assign $1\src_r2$next[63:0]$14374 \src_r2 + assign $1\src_r2$next[63:0]$14559 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14373 + update \src_r2$next $0\src_r2$next[63:0]$14558 end - attribute \src "libresoc.v:198624.3-198633.6" - process $proc$libresoc.v:198624$14375 + attribute \src "libresoc.v:200937.3-200946.6" + process $proc$libresoc.v:200937$14560 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14376 $1\src_r3$next[63:0]$14377 - attribute \src "libresoc.v:198625.5-198625.29" + assign $0\src_r3$next[63:0]$14561 $1\src_r3$next[63:0]$14562 + attribute \src "libresoc.v:200938.5-200938.29" switch \initial - attribute \src "libresoc.v:198625.9-198625.17" + attribute \src "libresoc.v:200938.9-200938.17" case 1'1 case end @@ -415724,21 +419747,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14377 \src4_i + assign $1\src_r3$next[63:0]$14562 \src4_i case - assign $1\src_r3$next[63:0]$14377 \src_r3 + assign $1\src_r3$next[63:0]$14562 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14376 + update \src_r3$next $0\src_r3$next[63:0]$14561 end - attribute \src "libresoc.v:198634.3-198642.6" - process $proc$libresoc.v:198634$14378 + attribute \src "libresoc.v:200947.3-200955.6" + process $proc$libresoc.v:200947$14563 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14379 $1\alui_l_r_alui$next[0:0]$14380 - attribute \src "libresoc.v:198635.5-198635.29" + assign $0\alui_l_r_alui$next[0:0]$14564 $1\alui_l_r_alui$next[0:0]$14565 + attribute \src "libresoc.v:200948.5-200948.29" switch \initial - attribute \src "libresoc.v:198635.9-198635.17" + attribute \src "libresoc.v:200948.9-200948.17" case 1'1 case end @@ -415747,21 +419770,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14380 1'1 + assign $1\alui_l_r_alui$next[0:0]$14565 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14380 \$89 + assign $1\alui_l_r_alui$next[0:0]$14565 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14379 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14564 end - attribute \src "libresoc.v:198643.3-198651.6" - process $proc$libresoc.v:198643$14381 + attribute \src "libresoc.v:200956.3-200964.6" + process $proc$libresoc.v:200956$14566 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14382 $1\alu_l_r_alu$next[0:0]$14383 - attribute \src "libresoc.v:198644.5-198644.29" + assign $0\alu_l_r_alu$next[0:0]$14567 $1\alu_l_r_alu$next[0:0]$14568 + attribute \src "libresoc.v:200957.5-200957.29" switch \initial - attribute \src "libresoc.v:198644.9-198644.17" + attribute \src "libresoc.v:200957.9-200957.17" case 1'1 case end @@ -415770,21 +419793,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14383 1'1 + assign $1\alu_l_r_alu$next[0:0]$14568 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14383 \$91 + assign $1\alu_l_r_alu$next[0:0]$14568 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14382 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14567 end - attribute \src "libresoc.v:198652.3-198661.6" - process $proc$libresoc.v:198652$14384 + attribute \src "libresoc.v:200965.3-200974.6" + process $proc$libresoc.v:200965$14569 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:198653.5-198653.29" + attribute \src "libresoc.v:200966.5-200966.29" switch \initial - attribute \src "libresoc.v:198653.9-198653.17" + attribute \src "libresoc.v:200966.9-200966.17" case 1'1 case end @@ -415800,14 +419823,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:198662.3-198671.6" - process $proc$libresoc.v:198662$14385 + attribute \src "libresoc.v:200975.3-200984.6" + process $proc$libresoc.v:200975$14570 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:198663.5-198663.29" + attribute \src "libresoc.v:200976.5-200976.29" switch \initial - attribute \src "libresoc.v:198663.9-198663.17" + attribute \src "libresoc.v:200976.9-200976.17" case 1'1 case end @@ -415823,14 +419846,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:198672.3-198681.6" - process $proc$libresoc.v:198672$14386 + attribute \src "libresoc.v:200985.3-200994.6" + process $proc$libresoc.v:200985$14571 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:198673.5-198673.29" + attribute \src "libresoc.v:200986.5-200986.29" switch \initial - attribute \src "libresoc.v:198673.9-198673.17" + attribute \src "libresoc.v:200986.9-200986.17" case 1'1 case end @@ -415846,14 +419869,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:198682.3-198691.6" - process $proc$libresoc.v:198682$14387 + attribute \src "libresoc.v:200995.3-201004.6" + process $proc$libresoc.v:200995$14572 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:198683.5-198683.29" + attribute \src "libresoc.v:200996.5-200996.29" switch \initial - attribute \src "libresoc.v:198683.9-198683.17" + attribute \src "libresoc.v:200996.9-200996.17" case 1'1 case end @@ -415869,14 +419892,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:198692.3-198701.6" - process $proc$libresoc.v:198692$14388 + attribute \src "libresoc.v:201005.3-201014.6" + process $proc$libresoc.v:201005$14573 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:198693.5-198693.29" + attribute \src "libresoc.v:201006.5-201006.29" switch \initial - attribute \src "libresoc.v:198693.9-198693.17" + attribute \src "libresoc.v:201006.9-201006.17" case 1'1 case end @@ -415892,14 +419915,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:198702.3-198710.6" - process $proc$libresoc.v:198702$14389 + attribute \src "libresoc.v:201015.3-201023.6" + process $proc$libresoc.v:201015$14574 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14390 $1\prev_wr_go$next[4:0]$14391 - attribute \src "libresoc.v:198703.5-198703.29" + assign $0\prev_wr_go$next[4:0]$14575 $1\prev_wr_go$next[4:0]$14576 + attribute \src "libresoc.v:201016.5-201016.29" switch \initial - attribute \src "libresoc.v:198703.9-198703.17" + attribute \src "libresoc.v:201016.9-201016.17" case 1'1 case end @@ -415908,74 +419931,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14391 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14391 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14390 - end - connect \$5 $reduce_and$libresoc.v:198150$14177_Y - connect \$99 $and$libresoc.v:198151$14178_Y - connect \$101 $and$libresoc.v:198152$14179_Y - connect \$103 $and$libresoc.v:198153$14180_Y - connect \$105 $and$libresoc.v:198154$14181_Y - connect \$107 $and$libresoc.v:198155$14182_Y - connect \$109 $and$libresoc.v:198156$14183_Y - connect \$111 $and$libresoc.v:198157$14184_Y - connect \$113 $and$libresoc.v:198158$14185_Y - connect \$115 $and$libresoc.v:198159$14186_Y - connect \$117 $and$libresoc.v:198160$14187_Y - connect \$11 $and$libresoc.v:198161$14188_Y - connect \$119 $and$libresoc.v:198162$14189_Y - connect \$121 $and$libresoc.v:198163$14190_Y - connect \$123 $and$libresoc.v:198164$14191_Y - connect \$13 $not$libresoc.v:198165$14192_Y - connect \$15 $and$libresoc.v:198166$14193_Y - connect \$17 $not$libresoc.v:198167$14194_Y - connect \$19 $and$libresoc.v:198168$14195_Y - connect \$21 $and$libresoc.v:198169$14196_Y - connect \$25 $not$libresoc.v:198170$14197_Y - connect \$27 $and$libresoc.v:198171$14198_Y - connect \$24 $reduce_or$libresoc.v:198172$14199_Y - connect \$23 $not$libresoc.v:198173$14200_Y - connect \$31 $and$libresoc.v:198174$14201_Y - connect \$33 $reduce_or$libresoc.v:198175$14202_Y - connect \$35 $reduce_or$libresoc.v:198176$14203_Y - connect \$37 $or$libresoc.v:198177$14204_Y - connect \$3 $and$libresoc.v:198178$14205_Y - connect \$39 $not$libresoc.v:198179$14206_Y - connect \$41 $and$libresoc.v:198180$14207_Y - connect \$43 $and$libresoc.v:198181$14208_Y - connect \$45 $eq$libresoc.v:198182$14209_Y - connect \$47 $and$libresoc.v:198183$14210_Y - connect \$49 $eq$libresoc.v:198184$14211_Y - connect \$51 $and$libresoc.v:198185$14212_Y - connect \$53 $and$libresoc.v:198186$14213_Y - connect \$55 $and$libresoc.v:198187$14214_Y - connect \$57 $or$libresoc.v:198188$14215_Y - connect \$59 $or$libresoc.v:198189$14216_Y - connect \$61 $or$libresoc.v:198190$14217_Y - connect \$63 $or$libresoc.v:198191$14218_Y - connect \$65 $and$libresoc.v:198192$14219_Y - connect \$67 $and$libresoc.v:198193$14220_Y - connect \$6 $not$libresoc.v:198194$14221_Y - connect \$69 $or$libresoc.v:198195$14222_Y - connect \$71 $and$libresoc.v:198196$14223_Y - connect \$73 $and$libresoc.v:198197$14224_Y - connect \$75 $and$libresoc.v:198198$14225_Y - connect \$77 $and$libresoc.v:198199$14226_Y - connect \$79 $and$libresoc.v:198200$14227_Y - connect \$81 $ternary$libresoc.v:198201$14228_Y - connect \$83 $ternary$libresoc.v:198202$14229_Y - connect \$85 $ternary$libresoc.v:198203$14230_Y - connect \$87 $ternary$libresoc.v:198204$14231_Y - connect \$8 $or$libresoc.v:198205$14232_Y - connect \$89 $and$libresoc.v:198206$14233_Y - connect \$91 $and$libresoc.v:198207$14234_Y - connect \$93 $and$libresoc.v:198208$14235_Y - connect \$95 $and$libresoc.v:198209$14236_Y - connect \$97 $not$libresoc.v:198210$14237_Y + assign $1\prev_wr_go$next[4:0]$14576 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14576 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14575 + end + connect \$5 $reduce_and$libresoc.v:200463$14362_Y + connect \$99 $and$libresoc.v:200464$14363_Y + connect \$101 $and$libresoc.v:200465$14364_Y + connect \$103 $and$libresoc.v:200466$14365_Y + connect \$105 $and$libresoc.v:200467$14366_Y + connect \$107 $and$libresoc.v:200468$14367_Y + connect \$109 $and$libresoc.v:200469$14368_Y + connect \$111 $and$libresoc.v:200470$14369_Y + connect \$113 $and$libresoc.v:200471$14370_Y + connect \$115 $and$libresoc.v:200472$14371_Y + connect \$117 $and$libresoc.v:200473$14372_Y + connect \$11 $and$libresoc.v:200474$14373_Y + connect \$119 $and$libresoc.v:200475$14374_Y + connect \$121 $and$libresoc.v:200476$14375_Y + connect \$123 $and$libresoc.v:200477$14376_Y + connect \$13 $not$libresoc.v:200478$14377_Y + connect \$15 $and$libresoc.v:200479$14378_Y + connect \$17 $not$libresoc.v:200480$14379_Y + connect \$19 $and$libresoc.v:200481$14380_Y + connect \$21 $and$libresoc.v:200482$14381_Y + connect \$25 $not$libresoc.v:200483$14382_Y + connect \$27 $and$libresoc.v:200484$14383_Y + connect \$24 $reduce_or$libresoc.v:200485$14384_Y + connect \$23 $not$libresoc.v:200486$14385_Y + connect \$31 $and$libresoc.v:200487$14386_Y + connect \$33 $reduce_or$libresoc.v:200488$14387_Y + connect \$35 $reduce_or$libresoc.v:200489$14388_Y + connect \$37 $or$libresoc.v:200490$14389_Y + connect \$3 $and$libresoc.v:200491$14390_Y + connect \$39 $not$libresoc.v:200492$14391_Y + connect \$41 $and$libresoc.v:200493$14392_Y + connect \$43 $and$libresoc.v:200494$14393_Y + connect \$45 $eq$libresoc.v:200495$14394_Y + connect \$47 $and$libresoc.v:200496$14395_Y + connect \$49 $eq$libresoc.v:200497$14396_Y + connect \$51 $and$libresoc.v:200498$14397_Y + connect \$53 $and$libresoc.v:200499$14398_Y + connect \$55 $and$libresoc.v:200500$14399_Y + connect \$57 $or$libresoc.v:200501$14400_Y + connect \$59 $or$libresoc.v:200502$14401_Y + connect \$61 $or$libresoc.v:200503$14402_Y + connect \$63 $or$libresoc.v:200504$14403_Y + connect \$65 $and$libresoc.v:200505$14404_Y + connect \$67 $and$libresoc.v:200506$14405_Y + connect \$6 $not$libresoc.v:200507$14406_Y + connect \$69 $or$libresoc.v:200508$14407_Y + connect \$71 $and$libresoc.v:200509$14408_Y + connect \$73 $and$libresoc.v:200510$14409_Y + connect \$75 $and$libresoc.v:200511$14410_Y + connect \$77 $and$libresoc.v:200512$14411_Y + connect \$79 $and$libresoc.v:200513$14412_Y + connect \$81 $ternary$libresoc.v:200514$14413_Y + connect \$83 $ternary$libresoc.v:200515$14414_Y + connect \$85 $ternary$libresoc.v:200516$14415_Y + connect \$87 $ternary$libresoc.v:200517$14416_Y + connect \$8 $or$libresoc.v:200518$14417_Y + connect \$89 $and$libresoc.v:200519$14418_Y + connect \$91 $and$libresoc.v:200520$14419_Y + connect \$93 $and$libresoc.v:200521$14420_Y + connect \$95 $and$libresoc.v:200522$14421_Y + connect \$97 $not$libresoc.v:200523$14422_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -416006,37 +420029,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:198744.1-198802.10" +attribute \src "libresoc.v:201057.1-201115.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:198745.7-198745.20" + attribute \src "libresoc.v:201058.7-201058.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198790.3-198798.6" - wire $0\q_int$next[0:0]$14441 - attribute \src "libresoc.v:198788.3-198789.27" + attribute \src "libresoc.v:201103.3-201111.6" + wire $0\q_int$next[0:0]$14626 + attribute \src "libresoc.v:201101.3-201102.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198790.3-198798.6" - wire $1\q_int$next[0:0]$14442 - attribute \src "libresoc.v:198767.7-198767.19" + attribute \src "libresoc.v:201103.3-201111.6" + wire $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201080.7-201080.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198780.17-198780.96" - wire $and$libresoc.v:198780$14431_Y - attribute \src "libresoc.v:198785.17-198785.96" - wire $and$libresoc.v:198785$14436_Y - attribute \src "libresoc.v:198782.18-198782.93" - wire $not$libresoc.v:198782$14433_Y - attribute \src "libresoc.v:198784.17-198784.92" - wire $not$libresoc.v:198784$14435_Y - attribute \src "libresoc.v:198787.17-198787.92" - wire $not$libresoc.v:198787$14438_Y - attribute \src "libresoc.v:198781.18-198781.98" - wire $or$libresoc.v:198781$14432_Y - attribute \src "libresoc.v:198783.18-198783.99" - wire $or$libresoc.v:198783$14434_Y - attribute \src "libresoc.v:198786.17-198786.97" - wire $or$libresoc.v:198786$14437_Y + attribute \src "libresoc.v:201093.17-201093.96" + wire $and$libresoc.v:201093$14616_Y + attribute \src "libresoc.v:201098.17-201098.96" + wire $and$libresoc.v:201098$14621_Y + attribute \src "libresoc.v:201095.18-201095.93" + wire $not$libresoc.v:201095$14618_Y + attribute \src "libresoc.v:201097.17-201097.92" + wire $not$libresoc.v:201097$14620_Y + attribute \src "libresoc.v:201100.17-201100.92" + wire $not$libresoc.v:201100$14623_Y + attribute \src "libresoc.v:201094.18-201094.98" + wire $or$libresoc.v:201094$14617_Y + attribute \src "libresoc.v:201096.18-201096.99" + wire $or$libresoc.v:201096$14619_Y + attribute \src "libresoc.v:201099.17-201099.97" + wire $or$libresoc.v:201099$14622_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416053,11 +420076,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198745.7-198745.15" + attribute \src "libresoc.v:201058.7-201058.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416074,7 +420097,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198780$14431 + cell $and $and$libresoc.v:201093$14616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416082,10 +420105,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198780$14431_Y + connect \Y $and$libresoc.v:201093$14616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198785$14436 + cell $and $and$libresoc.v:201098$14621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416093,34 +420116,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198785$14436_Y + connect \Y $and$libresoc.v:201098$14621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198782$14433 + cell $not $not$libresoc.v:201095$14618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:198782$14433_Y + connect \Y $not$libresoc.v:201095$14618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198784$14435 + cell $not $not$libresoc.v:201097$14620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:198784$14435_Y + connect \Y $not$libresoc.v:201097$14620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198787$14438 + cell $not $not$libresoc.v:201100$14623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:198787$14438_Y + connect \Y $not$libresoc.v:201100$14623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198781$14432 + cell $or $or$libresoc.v:201094$14617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416128,10 +420151,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:198781$14432_Y + connect \Y $or$libresoc.v:201094$14617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198783$14434 + cell $or $or$libresoc.v:201096$14619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416139,10 +420162,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:198783$14434_Y + connect \Y $or$libresoc.v:201096$14619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198786$14437 + cell $or $or$libresoc.v:201099$14622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416150,39 +420173,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:198786$14437_Y + connect \Y $or$libresoc.v:201099$14622_Y end - attribute \src "libresoc.v:198745.7-198745.20" - process $proc$libresoc.v:198745$14443 + attribute \src "libresoc.v:201058.7-201058.20" + process $proc$libresoc.v:201058$14628 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198767.7-198767.19" - process $proc$libresoc.v:198767$14444 + attribute \src "libresoc.v:201080.7-201080.19" + process $proc$libresoc.v:201080$14629 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198788.3-198789.27" - process $proc$libresoc.v:198788$14439 + attribute \src "libresoc.v:201101.3-201102.27" + process $proc$libresoc.v:201101$14624 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198790.3-198798.6" - process $proc$libresoc.v:198790$14440 + attribute \src "libresoc.v:201103.3-201111.6" + process $proc$libresoc.v:201103$14625 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14441 $1\q_int$next[0:0]$14442 - attribute \src "libresoc.v:198791.5-198791.29" + assign $0\q_int$next[0:0]$14626 $1\q_int$next[0:0]$14627 + attribute \src "libresoc.v:201104.5-201104.29" switch \initial - attribute \src "libresoc.v:198791.9-198791.17" + attribute \src "libresoc.v:201104.9-201104.17" case 1'1 case end @@ -416191,56 +420214,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14442 1'0 + assign $1\q_int$next[0:0]$14627 1'0 case - assign $1\q_int$next[0:0]$14442 \$5 + assign $1\q_int$next[0:0]$14627 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14441 + update \q_int$next $0\q_int$next[0:0]$14626 end - connect \$9 $and$libresoc.v:198780$14431_Y - connect \$11 $or$libresoc.v:198781$14432_Y - connect \$13 $not$libresoc.v:198782$14433_Y - connect \$15 $or$libresoc.v:198783$14434_Y - connect \$1 $not$libresoc.v:198784$14435_Y - connect \$3 $and$libresoc.v:198785$14436_Y - connect \$5 $or$libresoc.v:198786$14437_Y - connect \$7 $not$libresoc.v:198787$14438_Y + connect \$9 $and$libresoc.v:201093$14616_Y + connect \$11 $or$libresoc.v:201094$14617_Y + connect \$13 $not$libresoc.v:201095$14618_Y + connect \$15 $or$libresoc.v:201096$14619_Y + connect \$1 $not$libresoc.v:201097$14620_Y + connect \$3 $and$libresoc.v:201098$14621_Y + connect \$5 $or$libresoc.v:201099$14622_Y + connect \$7 $not$libresoc.v:201100$14623_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:198806.1-198864.10" +attribute \src "libresoc.v:201119.1-201177.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:198807.7-198807.20" + attribute \src "libresoc.v:201120.7-201120.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198852.3-198860.6" - wire $0\q_int$next[0:0]$14455 - attribute \src "libresoc.v:198850.3-198851.27" + attribute \src "libresoc.v:201165.3-201173.6" + wire $0\q_int$next[0:0]$14640 + attribute \src "libresoc.v:201163.3-201164.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198852.3-198860.6" - wire $1\q_int$next[0:0]$14456 - attribute \src "libresoc.v:198829.7-198829.19" + attribute \src "libresoc.v:201165.3-201173.6" + wire $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201142.7-201142.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198842.17-198842.96" - wire $and$libresoc.v:198842$14445_Y - attribute \src "libresoc.v:198847.17-198847.96" - wire $and$libresoc.v:198847$14450_Y - attribute \src "libresoc.v:198844.18-198844.95" - wire $not$libresoc.v:198844$14447_Y - attribute \src "libresoc.v:198846.17-198846.94" - wire $not$libresoc.v:198846$14449_Y - attribute \src "libresoc.v:198849.17-198849.94" - wire $not$libresoc.v:198849$14452_Y - attribute \src "libresoc.v:198843.18-198843.100" - wire $or$libresoc.v:198843$14446_Y - attribute \src "libresoc.v:198845.18-198845.101" - wire $or$libresoc.v:198845$14448_Y - attribute \src "libresoc.v:198848.17-198848.99" - wire $or$libresoc.v:198848$14451_Y + attribute \src "libresoc.v:201155.17-201155.96" + wire $and$libresoc.v:201155$14630_Y + attribute \src "libresoc.v:201160.17-201160.96" + wire $and$libresoc.v:201160$14635_Y + attribute \src "libresoc.v:201157.18-201157.95" + wire $not$libresoc.v:201157$14632_Y + attribute \src "libresoc.v:201159.17-201159.94" + wire $not$libresoc.v:201159$14634_Y + attribute \src "libresoc.v:201162.17-201162.94" + wire $not$libresoc.v:201162$14637_Y + attribute \src "libresoc.v:201156.18-201156.100" + wire $or$libresoc.v:201156$14631_Y + attribute \src "libresoc.v:201158.18-201158.101" + wire $or$libresoc.v:201158$14633_Y + attribute \src "libresoc.v:201161.17-201161.99" + wire $or$libresoc.v:201161$14636_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416257,11 +420280,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198807.7-198807.15" + attribute \src "libresoc.v:201120.7-201120.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416278,7 +420301,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198842$14445 + cell $and $and$libresoc.v:201155$14630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416286,10 +420309,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198842$14445_Y + connect \Y $and$libresoc.v:201155$14630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198847$14450 + cell $and $and$libresoc.v:201160$14635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416297,34 +420320,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198847$14450_Y + connect \Y $and$libresoc.v:201160$14635_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198844$14447 + cell $not $not$libresoc.v:201157$14632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:198844$14447_Y + connect \Y $not$libresoc.v:201157$14632_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198846$14449 + cell $not $not$libresoc.v:201159$14634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:198846$14449_Y + connect \Y $not$libresoc.v:201159$14634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198849$14452 + cell $not $not$libresoc.v:201162$14637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:198849$14452_Y + connect \Y $not$libresoc.v:201162$14637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198843$14446 + cell $or $or$libresoc.v:201156$14631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416332,10 +420355,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:198843$14446_Y + connect \Y $or$libresoc.v:201156$14631_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198845$14448 + cell $or $or$libresoc.v:201158$14633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416343,10 +420366,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:198845$14448_Y + connect \Y $or$libresoc.v:201158$14633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198848$14451 + cell $or $or$libresoc.v:201161$14636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416354,39 +420377,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:198848$14451_Y + connect \Y $or$libresoc.v:201161$14636_Y end - attribute \src "libresoc.v:198807.7-198807.20" - process $proc$libresoc.v:198807$14457 + attribute \src "libresoc.v:201120.7-201120.20" + process $proc$libresoc.v:201120$14642 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198829.7-198829.19" - process $proc$libresoc.v:198829$14458 + attribute \src "libresoc.v:201142.7-201142.19" + process $proc$libresoc.v:201142$14643 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198850.3-198851.27" - process $proc$libresoc.v:198850$14453 + attribute \src "libresoc.v:201163.3-201164.27" + process $proc$libresoc.v:201163$14638 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198852.3-198860.6" - process $proc$libresoc.v:198852$14454 + attribute \src "libresoc.v:201165.3-201173.6" + process $proc$libresoc.v:201165$14639 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14455 $1\q_int$next[0:0]$14456 - attribute \src "libresoc.v:198853.5-198853.29" + assign $0\q_int$next[0:0]$14640 $1\q_int$next[0:0]$14641 + attribute \src "libresoc.v:201166.5-201166.29" switch \initial - attribute \src "libresoc.v:198853.9-198853.17" + attribute \src "libresoc.v:201166.9-201166.17" case 1'1 case end @@ -416395,56 +420418,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14456 1'0 + assign $1\q_int$next[0:0]$14641 1'0 case - assign $1\q_int$next[0:0]$14456 \$5 + assign $1\q_int$next[0:0]$14641 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14455 + update \q_int$next $0\q_int$next[0:0]$14640 end - connect \$9 $and$libresoc.v:198842$14445_Y - connect \$11 $or$libresoc.v:198843$14446_Y - connect \$13 $not$libresoc.v:198844$14447_Y - connect \$15 $or$libresoc.v:198845$14448_Y - connect \$1 $not$libresoc.v:198846$14449_Y - connect \$3 $and$libresoc.v:198847$14450_Y - connect \$5 $or$libresoc.v:198848$14451_Y - connect \$7 $not$libresoc.v:198849$14452_Y + connect \$9 $and$libresoc.v:201155$14630_Y + connect \$11 $or$libresoc.v:201156$14631_Y + connect \$13 $not$libresoc.v:201157$14632_Y + connect \$15 $or$libresoc.v:201158$14633_Y + connect \$1 $not$libresoc.v:201159$14634_Y + connect \$3 $and$libresoc.v:201160$14635_Y + connect \$5 $or$libresoc.v:201161$14636_Y + connect \$7 $not$libresoc.v:201162$14637_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:198868.1-198926.10" +attribute \src "libresoc.v:201181.1-201239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:198869.7-198869.20" + attribute \src "libresoc.v:201182.7-201182.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198914.3-198922.6" - wire $0\q_int$next[0:0]$14469 - attribute \src "libresoc.v:198912.3-198913.27" + attribute \src "libresoc.v:201227.3-201235.6" + wire $0\q_int$next[0:0]$14654 + attribute \src "libresoc.v:201225.3-201226.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:198914.3-198922.6" - wire $1\q_int$next[0:0]$14470 - attribute \src "libresoc.v:198891.7-198891.19" + attribute \src "libresoc.v:201227.3-201235.6" + wire $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201204.7-201204.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:198904.17-198904.96" - wire $and$libresoc.v:198904$14459_Y - attribute \src "libresoc.v:198909.17-198909.96" - wire $and$libresoc.v:198909$14464_Y - attribute \src "libresoc.v:198906.18-198906.93" - wire $not$libresoc.v:198906$14461_Y - attribute \src "libresoc.v:198908.17-198908.92" - wire $not$libresoc.v:198908$14463_Y - attribute \src "libresoc.v:198911.17-198911.92" - wire $not$libresoc.v:198911$14466_Y - attribute \src "libresoc.v:198905.18-198905.98" - wire $or$libresoc.v:198905$14460_Y - attribute \src "libresoc.v:198907.18-198907.99" - wire $or$libresoc.v:198907$14462_Y - attribute \src "libresoc.v:198910.17-198910.97" - wire $or$libresoc.v:198910$14465_Y + attribute \src "libresoc.v:201217.17-201217.96" + wire $and$libresoc.v:201217$14644_Y + attribute \src "libresoc.v:201222.17-201222.96" + wire $and$libresoc.v:201222$14649_Y + attribute \src "libresoc.v:201219.18-201219.93" + wire $not$libresoc.v:201219$14646_Y + attribute \src "libresoc.v:201221.17-201221.92" + wire $not$libresoc.v:201221$14648_Y + attribute \src "libresoc.v:201224.17-201224.92" + wire $not$libresoc.v:201224$14651_Y + attribute \src "libresoc.v:201218.18-201218.98" + wire $or$libresoc.v:201218$14645_Y + attribute \src "libresoc.v:201220.18-201220.99" + wire $or$libresoc.v:201220$14647_Y + attribute \src "libresoc.v:201223.17-201223.97" + wire $or$libresoc.v:201223$14650_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -416461,11 +420484,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:198869.7-198869.15" + attribute \src "libresoc.v:201182.7-201182.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -416482,7 +420505,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:198904$14459 + cell $and $and$libresoc.v:201217$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416490,10 +420513,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:198904$14459_Y + connect \Y $and$libresoc.v:201217$14644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:198909$14464 + cell $and $and$libresoc.v:201222$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416501,34 +420524,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:198909$14464_Y + connect \Y $and$libresoc.v:201222$14649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:198906$14461 + cell $not $not$libresoc.v:201219$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:198906$14461_Y + connect \Y $not$libresoc.v:201219$14646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:198908$14463 + cell $not $not$libresoc.v:201221$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:198908$14463_Y + connect \Y $not$libresoc.v:201221$14648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:198911$14466 + cell $not $not$libresoc.v:201224$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:198911$14466_Y + connect \Y $not$libresoc.v:201224$14651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:198905$14460 + cell $or $or$libresoc.v:201218$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416536,10 +420559,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:198905$14460_Y + connect \Y $or$libresoc.v:201218$14645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:198907$14462 + cell $or $or$libresoc.v:201220$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416547,10 +420570,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:198907$14462_Y + connect \Y $or$libresoc.v:201220$14647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:198910$14465 + cell $or $or$libresoc.v:201223$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -416558,39 +420581,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:198910$14465_Y + connect \Y $or$libresoc.v:201223$14650_Y end - attribute \src "libresoc.v:198869.7-198869.20" - process $proc$libresoc.v:198869$14471 + attribute \src "libresoc.v:201182.7-201182.20" + process $proc$libresoc.v:201182$14656 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198891.7-198891.19" - process $proc$libresoc.v:198891$14472 + attribute \src "libresoc.v:201204.7-201204.19" + process $proc$libresoc.v:201204$14657 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:198912.3-198913.27" - process $proc$libresoc.v:198912$14467 + attribute \src "libresoc.v:201225.3-201226.27" + process $proc$libresoc.v:201225$14652 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:198914.3-198922.6" - process $proc$libresoc.v:198914$14468 + attribute \src "libresoc.v:201227.3-201235.6" + process $proc$libresoc.v:201227$14653 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14469 $1\q_int$next[0:0]$14470 - attribute \src "libresoc.v:198915.5-198915.29" + assign $0\q_int$next[0:0]$14654 $1\q_int$next[0:0]$14655 + attribute \src "libresoc.v:201228.5-201228.29" switch \initial - attribute \src "libresoc.v:198915.9-198915.17" + attribute \src "libresoc.v:201228.9-201228.17" case 1'1 case end @@ -416599,54 +420622,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14470 1'0 + assign $1\q_int$next[0:0]$14655 1'0 case - assign $1\q_int$next[0:0]$14470 \$5 + assign $1\q_int$next[0:0]$14655 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14469 + update \q_int$next $0\q_int$next[0:0]$14654 end - connect \$9 $and$libresoc.v:198904$14459_Y - connect \$11 $or$libresoc.v:198905$14460_Y - connect \$13 $not$libresoc.v:198906$14461_Y - connect \$15 $or$libresoc.v:198907$14462_Y - connect \$1 $not$libresoc.v:198908$14463_Y - connect \$3 $and$libresoc.v:198909$14464_Y - connect \$5 $or$libresoc.v:198910$14465_Y - connect \$7 $not$libresoc.v:198911$14466_Y + connect \$9 $and$libresoc.v:201217$14644_Y + connect \$11 $or$libresoc.v:201218$14645_Y + connect \$13 $not$libresoc.v:201219$14646_Y + connect \$15 $or$libresoc.v:201220$14647_Y + connect \$1 $not$libresoc.v:201221$14648_Y + connect \$3 $and$libresoc.v:201222$14649_Y + connect \$5 $or$libresoc.v:201223$14650_Y + connect \$7 $not$libresoc.v:201224$14651_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:198930.1-198996.10" +attribute \src "libresoc.v:201243.1-201309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:198975.17-198975.91" - wire $not$libresoc.v:198975$14473_Y - attribute \src "libresoc.v:198977.18-198977.93" - wire $not$libresoc.v:198977$14475_Y - attribute \src "libresoc.v:198979.18-198979.93" - wire $not$libresoc.v:198979$14477_Y - attribute \src "libresoc.v:198980.17-198980.89" - wire width 6 $not$libresoc.v:198980$14478_Y - attribute \src "libresoc.v:198982.18-198982.93" - wire $not$libresoc.v:198982$14480_Y - attribute \src "libresoc.v:198985.17-198985.91" - wire $not$libresoc.v:198985$14483_Y - attribute \src "libresoc.v:198976.18-198976.106" - wire $reduce_or$libresoc.v:198976$14474_Y - attribute \src "libresoc.v:198978.18-198978.106" - wire $reduce_or$libresoc.v:198978$14476_Y - attribute \src "libresoc.v:198981.18-198981.106" - wire $reduce_or$libresoc.v:198981$14479_Y - attribute \src "libresoc.v:198983.18-198983.90" - wire $reduce_or$libresoc.v:198983$14481_Y - attribute \src "libresoc.v:198984.17-198984.103" - wire $reduce_or$libresoc.v:198984$14482_Y - attribute \src "libresoc.v:198986.17-198986.105" - wire $reduce_or$libresoc.v:198986$14484_Y + attribute \src "libresoc.v:201288.17-201288.91" + wire $not$libresoc.v:201288$14658_Y + attribute \src "libresoc.v:201290.18-201290.93" + wire $not$libresoc.v:201290$14660_Y + attribute \src "libresoc.v:201292.18-201292.93" + wire $not$libresoc.v:201292$14662_Y + attribute \src "libresoc.v:201293.17-201293.89" + wire width 6 $not$libresoc.v:201293$14663_Y + attribute \src "libresoc.v:201295.18-201295.93" + wire $not$libresoc.v:201295$14665_Y + attribute \src "libresoc.v:201298.17-201298.91" + wire $not$libresoc.v:201298$14668_Y + attribute \src "libresoc.v:201289.18-201289.106" + wire $reduce_or$libresoc.v:201289$14659_Y + attribute \src "libresoc.v:201291.18-201291.106" + wire $reduce_or$libresoc.v:201291$14661_Y + attribute \src "libresoc.v:201294.18-201294.106" + wire $reduce_or$libresoc.v:201294$14664_Y + attribute \src "libresoc.v:201296.18-201296.90" + wire $reduce_or$libresoc.v:201296$14666_Y + attribute \src "libresoc.v:201297.17-201297.103" + wire $reduce_or$libresoc.v:201297$14667_Y + attribute \src "libresoc.v:201299.17-201299.105" + wire $reduce_or$libresoc.v:201299$14669_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416692,113 +420715,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198975$14473 + cell $not $not$libresoc.v:201288$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:198975$14473_Y + connect \Y $not$libresoc.v:201288$14658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198977$14475 + cell $not $not$libresoc.v:201290$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:198977$14475_Y + connect \Y $not$libresoc.v:201290$14660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198979$14477 + cell $not $not$libresoc.v:201292$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:198979$14477_Y + connect \Y $not$libresoc.v:201292$14662_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:198980$14478 + cell $not $not$libresoc.v:201293$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:198980$14478_Y + connect \Y $not$libresoc.v:201293$14663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198982$14480 + cell $not $not$libresoc.v:201295$14665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:198982$14480_Y + connect \Y $not$libresoc.v:201295$14665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:198985$14483 + cell $not $not$libresoc.v:201298$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:198985$14483_Y + connect \Y $not$libresoc.v:201298$14668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198976$14474 + cell $reduce_or $reduce_or$libresoc.v:201289$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:198976$14474_Y + connect \Y $reduce_or$libresoc.v:201289$14659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198978$14476 + cell $reduce_or $reduce_or$libresoc.v:201291$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:198978$14476_Y + connect \Y $reduce_or$libresoc.v:201291$14661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198981$14479 + cell $reduce_or $reduce_or$libresoc.v:201294$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:198981$14479_Y + connect \Y $reduce_or$libresoc.v:201294$14664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:198983$14481 + cell $reduce_or $reduce_or$libresoc.v:201296$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:198983$14481_Y + connect \Y $reduce_or$libresoc.v:201296$14666_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198984$14482 + cell $reduce_or $reduce_or$libresoc.v:201297$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:198984$14482_Y + connect \Y $reduce_or$libresoc.v:201297$14667_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:198986$14484 + cell $reduce_or $reduce_or$libresoc.v:201299$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:198986$14484_Y - end - connect \$7 $not$libresoc.v:198975$14473_Y - connect \$12 $reduce_or$libresoc.v:198976$14474_Y - connect \$11 $not$libresoc.v:198977$14475_Y - connect \$16 $reduce_or$libresoc.v:198978$14476_Y - connect \$15 $not$libresoc.v:198979$14477_Y - connect \$1 $not$libresoc.v:198980$14478_Y - connect \$20 $reduce_or$libresoc.v:198981$14479_Y - connect \$19 $not$libresoc.v:198982$14480_Y - connect \$23 $reduce_or$libresoc.v:198983$14481_Y - connect \$4 $reduce_or$libresoc.v:198984$14482_Y - connect \$3 $not$libresoc.v:198985$14483_Y - connect \$8 $reduce_or$libresoc.v:198986$14484_Y + connect \Y $reduce_or$libresoc.v:201299$14669_Y + end + connect \$7 $not$libresoc.v:201288$14658_Y + connect \$12 $reduce_or$libresoc.v:201289$14659_Y + connect \$11 $not$libresoc.v:201290$14660_Y + connect \$16 $reduce_or$libresoc.v:201291$14661_Y + connect \$15 $not$libresoc.v:201292$14662_Y + connect \$1 $not$libresoc.v:201293$14663_Y + connect \$20 $reduce_or$libresoc.v:201294$14664_Y + connect \$19 $not$libresoc.v:201295$14665_Y + connect \$23 $reduce_or$libresoc.v:201296$14666_Y + connect \$4 $reduce_or$libresoc.v:201297$14667_Y + connect \$3 $not$libresoc.v:201298$14668_Y + connect \$8 $reduce_or$libresoc.v:201299$14669_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -416809,15 +420832,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199000.1-199021.10" +attribute \src "libresoc.v:201313.1-201334.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:199015.17-199015.89" - wire $not$libresoc.v:199015$14485_Y - attribute \src "libresoc.v:199016.17-199016.89" - wire $reduce_or$libresoc.v:199016$14486_Y + attribute \src "libresoc.v:201328.17-201328.89" + wire $not$libresoc.v:201328$14670_Y + attribute \src "libresoc.v:201329.17-201329.89" + wire $reduce_or$libresoc.v:201329$14671_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416833,53 +420856,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199015$14485 + cell $not $not$libresoc.v:201328$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199015$14485_Y + connect \Y $not$libresoc.v:201328$14670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199016$14486 + cell $reduce_or $reduce_or$libresoc.v:201329$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199016$14486_Y + connect \Y $reduce_or$libresoc.v:201329$14671_Y end - connect \$1 $not$libresoc.v:199015$14485_Y - connect \$3 $reduce_or$libresoc.v:199016$14486_Y + connect \$1 $not$libresoc.v:201328$14670_Y + connect \$3 $reduce_or$libresoc.v:201329$14671_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199025.1-199082.10" +attribute \src "libresoc.v:201338.1-201395.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:199064.17-199064.91" - wire $not$libresoc.v:199064$14487_Y - attribute \src "libresoc.v:199066.18-199066.93" - wire $not$libresoc.v:199066$14489_Y - attribute \src "libresoc.v:199068.18-199068.93" - wire $not$libresoc.v:199068$14491_Y - attribute \src "libresoc.v:199069.17-199069.89" - wire width 5 $not$libresoc.v:199069$14492_Y - attribute \src "libresoc.v:199072.17-199072.91" - wire $not$libresoc.v:199072$14495_Y - attribute \src "libresoc.v:199065.18-199065.106" - wire $reduce_or$libresoc.v:199065$14488_Y - attribute \src "libresoc.v:199067.18-199067.106" - wire $reduce_or$libresoc.v:199067$14490_Y - attribute \src "libresoc.v:199070.18-199070.90" - wire $reduce_or$libresoc.v:199070$14493_Y - attribute \src "libresoc.v:199071.17-199071.103" - wire $reduce_or$libresoc.v:199071$14494_Y - attribute \src "libresoc.v:199073.17-199073.105" - wire $reduce_or$libresoc.v:199073$14496_Y + attribute \src "libresoc.v:201377.17-201377.91" + wire $not$libresoc.v:201377$14672_Y + attribute \src "libresoc.v:201379.18-201379.93" + wire $not$libresoc.v:201379$14674_Y + attribute \src "libresoc.v:201381.18-201381.93" + wire $not$libresoc.v:201381$14676_Y + attribute \src "libresoc.v:201382.17-201382.89" + wire width 5 $not$libresoc.v:201382$14677_Y + attribute \src "libresoc.v:201385.17-201385.91" + wire $not$libresoc.v:201385$14680_Y + attribute \src "libresoc.v:201378.18-201378.106" + wire $reduce_or$libresoc.v:201378$14673_Y + attribute \src "libresoc.v:201380.18-201380.106" + wire $reduce_or$libresoc.v:201380$14675_Y + attribute \src "libresoc.v:201383.18-201383.90" + wire $reduce_or$libresoc.v:201383$14678_Y + attribute \src "libresoc.v:201384.17-201384.103" + wire $reduce_or$libresoc.v:201384$14679_Y + attribute \src "libresoc.v:201386.17-201386.105" + wire $reduce_or$libresoc.v:201386$14681_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416919,95 +420942,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199064$14487 + cell $not $not$libresoc.v:201377$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199064$14487_Y + connect \Y $not$libresoc.v:201377$14672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199066$14489 + cell $not $not$libresoc.v:201379$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199066$14489_Y + connect \Y $not$libresoc.v:201379$14674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199068$14491 + cell $not $not$libresoc.v:201381$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:199068$14491_Y + connect \Y $not$libresoc.v:201381$14676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199069$14492 + cell $not $not$libresoc.v:201382$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:199069$14492_Y + connect \Y $not$libresoc.v:201382$14677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199072$14495 + cell $not $not$libresoc.v:201385$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199072$14495_Y + connect \Y $not$libresoc.v:201385$14680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199065$14488 + cell $reduce_or $reduce_or$libresoc.v:201378$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199065$14488_Y + connect \Y $reduce_or$libresoc.v:201378$14673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199067$14490 + cell $reduce_or $reduce_or$libresoc.v:201380$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:199067$14490_Y + connect \Y $reduce_or$libresoc.v:201380$14675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199070$14493 + cell $reduce_or $reduce_or$libresoc.v:201383$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199070$14493_Y + connect \Y $reduce_or$libresoc.v:201383$14678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199071$14494 + cell $reduce_or $reduce_or$libresoc.v:201384$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199071$14494_Y + connect \Y $reduce_or$libresoc.v:201384$14679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199073$14496 + cell $reduce_or $reduce_or$libresoc.v:201386$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199073$14496_Y - end - connect \$7 $not$libresoc.v:199064$14487_Y - connect \$12 $reduce_or$libresoc.v:199065$14488_Y - connect \$11 $not$libresoc.v:199066$14489_Y - connect \$16 $reduce_or$libresoc.v:199067$14490_Y - connect \$15 $not$libresoc.v:199068$14491_Y - connect \$1 $not$libresoc.v:199069$14492_Y - connect \$19 $reduce_or$libresoc.v:199070$14493_Y - connect \$4 $reduce_or$libresoc.v:199071$14494_Y - connect \$3 $not$libresoc.v:199072$14495_Y - connect \$8 $reduce_or$libresoc.v:199073$14496_Y + connect \Y $reduce_or$libresoc.v:201386$14681_Y + end + connect \$7 $not$libresoc.v:201377$14672_Y + connect \$12 $reduce_or$libresoc.v:201378$14673_Y + connect \$11 $not$libresoc.v:201379$14674_Y + connect \$16 $reduce_or$libresoc.v:201380$14675_Y + connect \$15 $not$libresoc.v:201381$14676_Y + connect \$1 $not$libresoc.v:201382$14677_Y + connect \$19 $reduce_or$libresoc.v:201383$14678_Y + connect \$4 $reduce_or$libresoc.v:201384$14679_Y + connect \$3 $not$libresoc.v:201385$14680_Y + connect \$8 $reduce_or$libresoc.v:201386$14681_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -417017,51 +421040,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199086.1-199188.10" +attribute \src "libresoc.v:201399.1-201501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:199155.17-199155.91" - wire $not$libresoc.v:199155$14497_Y - attribute \src "libresoc.v:199157.18-199157.93" - wire $not$libresoc.v:199157$14499_Y - attribute \src "libresoc.v:199159.18-199159.93" - wire $not$libresoc.v:199159$14501_Y - attribute \src "libresoc.v:199160.17-199160.89" - wire width 10 $not$libresoc.v:199160$14502_Y - attribute \src "libresoc.v:199162.18-199162.93" - wire $not$libresoc.v:199162$14504_Y - attribute \src "libresoc.v:199164.18-199164.93" - wire $not$libresoc.v:199164$14506_Y - attribute \src "libresoc.v:199166.18-199166.93" - wire $not$libresoc.v:199166$14508_Y - attribute \src "libresoc.v:199168.18-199168.93" - wire $not$libresoc.v:199168$14510_Y - attribute \src "libresoc.v:199170.18-199170.93" - wire $not$libresoc.v:199170$14512_Y - attribute \src "libresoc.v:199173.17-199173.91" - wire $not$libresoc.v:199173$14515_Y - attribute \src "libresoc.v:199156.18-199156.106" - wire $reduce_or$libresoc.v:199156$14498_Y - attribute \src "libresoc.v:199158.18-199158.106" - wire $reduce_or$libresoc.v:199158$14500_Y - attribute \src "libresoc.v:199161.18-199161.106" - wire $reduce_or$libresoc.v:199161$14503_Y - attribute \src "libresoc.v:199163.18-199163.106" - wire $reduce_or$libresoc.v:199163$14505_Y - attribute \src "libresoc.v:199165.18-199165.106" - wire $reduce_or$libresoc.v:199165$14507_Y - attribute \src "libresoc.v:199167.18-199167.106" - wire $reduce_or$libresoc.v:199167$14509_Y - attribute \src "libresoc.v:199169.18-199169.106" - wire $reduce_or$libresoc.v:199169$14511_Y - attribute \src "libresoc.v:199171.18-199171.90" - wire $reduce_or$libresoc.v:199171$14513_Y - attribute \src "libresoc.v:199172.17-199172.103" - wire $reduce_or$libresoc.v:199172$14514_Y - attribute \src "libresoc.v:199174.17-199174.105" - wire $reduce_or$libresoc.v:199174$14516_Y + attribute \src "libresoc.v:201468.17-201468.91" + wire $not$libresoc.v:201468$14682_Y + attribute \src "libresoc.v:201470.18-201470.93" + wire $not$libresoc.v:201470$14684_Y + attribute \src "libresoc.v:201472.18-201472.93" + wire $not$libresoc.v:201472$14686_Y + attribute \src "libresoc.v:201473.17-201473.89" + wire width 10 $not$libresoc.v:201473$14687_Y + attribute \src "libresoc.v:201475.18-201475.93" + wire $not$libresoc.v:201475$14689_Y + attribute \src "libresoc.v:201477.18-201477.93" + wire $not$libresoc.v:201477$14691_Y + attribute \src "libresoc.v:201479.18-201479.93" + wire $not$libresoc.v:201479$14693_Y + attribute \src "libresoc.v:201481.18-201481.93" + wire $not$libresoc.v:201481$14695_Y + attribute \src "libresoc.v:201483.18-201483.93" + wire $not$libresoc.v:201483$14697_Y + attribute \src "libresoc.v:201486.17-201486.91" + wire $not$libresoc.v:201486$14700_Y + attribute \src "libresoc.v:201469.18-201469.106" + wire $reduce_or$libresoc.v:201469$14683_Y + attribute \src "libresoc.v:201471.18-201471.106" + wire $reduce_or$libresoc.v:201471$14685_Y + attribute \src "libresoc.v:201474.18-201474.106" + wire $reduce_or$libresoc.v:201474$14688_Y + attribute \src "libresoc.v:201476.18-201476.106" + wire $reduce_or$libresoc.v:201476$14690_Y + attribute \src "libresoc.v:201478.18-201478.106" + wire $reduce_or$libresoc.v:201478$14692_Y + attribute \src "libresoc.v:201480.18-201480.106" + wire $reduce_or$libresoc.v:201480$14694_Y + attribute \src "libresoc.v:201482.18-201482.106" + wire $reduce_or$libresoc.v:201482$14696_Y + attribute \src "libresoc.v:201484.18-201484.90" + wire $reduce_or$libresoc.v:201484$14698_Y + attribute \src "libresoc.v:201485.17-201485.103" + wire $reduce_or$libresoc.v:201485$14699_Y + attribute \src "libresoc.v:201487.17-201487.105" + wire $reduce_or$libresoc.v:201487$14701_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417131,185 +421154,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199155$14497 + cell $not $not$libresoc.v:201468$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199155$14497_Y + connect \Y $not$libresoc.v:201468$14682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199157$14499 + cell $not $not$libresoc.v:201470$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199157$14499_Y + connect \Y $not$libresoc.v:201470$14684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199159$14501 + cell $not $not$libresoc.v:201472$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:199159$14501_Y + connect \Y $not$libresoc.v:201472$14686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199160$14502 + cell $not $not$libresoc.v:201473$14687 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:199160$14502_Y + connect \Y $not$libresoc.v:201473$14687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199162$14504 + cell $not $not$libresoc.v:201475$14689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:199162$14504_Y + connect \Y $not$libresoc.v:201475$14689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199164$14506 + cell $not $not$libresoc.v:201477$14691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:199164$14506_Y + connect \Y $not$libresoc.v:201477$14691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199166$14508 + cell $not $not$libresoc.v:201479$14693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:199166$14508_Y + connect \Y $not$libresoc.v:201479$14693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199168$14510 + cell $not $not$libresoc.v:201481$14695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:199168$14510_Y + connect \Y $not$libresoc.v:201481$14695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199170$14512 + cell $not $not$libresoc.v:201483$14697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:199170$14512_Y + connect \Y $not$libresoc.v:201483$14697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199173$14515 + cell $not $not$libresoc.v:201486$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199173$14515_Y + connect \Y $not$libresoc.v:201486$14700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199156$14498 + cell $reduce_or $reduce_or$libresoc.v:201469$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199156$14498_Y + connect \Y $reduce_or$libresoc.v:201469$14683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199158$14500 + cell $reduce_or $reduce_or$libresoc.v:201471$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:199158$14500_Y + connect \Y $reduce_or$libresoc.v:201471$14685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199161$14503 + cell $reduce_or $reduce_or$libresoc.v:201474$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:199161$14503_Y + connect \Y $reduce_or$libresoc.v:201474$14688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199163$14505 + cell $reduce_or $reduce_or$libresoc.v:201476$14690 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:199163$14505_Y + connect \Y $reduce_or$libresoc.v:201476$14690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199165$14507 + cell $reduce_or $reduce_or$libresoc.v:201478$14692 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:199165$14507_Y + connect \Y $reduce_or$libresoc.v:201478$14692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199167$14509 + cell $reduce_or $reduce_or$libresoc.v:201480$14694 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:199167$14509_Y + connect \Y $reduce_or$libresoc.v:201480$14694_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199169$14511 + cell $reduce_or $reduce_or$libresoc.v:201482$14696 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:199169$14511_Y + connect \Y $reduce_or$libresoc.v:201482$14696_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199171$14513 + cell $reduce_or $reduce_or$libresoc.v:201484$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199171$14513_Y + connect \Y $reduce_or$libresoc.v:201484$14698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199172$14514 + cell $reduce_or $reduce_or$libresoc.v:201485$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199172$14514_Y + connect \Y $reduce_or$libresoc.v:201485$14699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199174$14516 + cell $reduce_or $reduce_or$libresoc.v:201487$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199174$14516_Y - end - connect \$7 $not$libresoc.v:199155$14497_Y - connect \$12 $reduce_or$libresoc.v:199156$14498_Y - connect \$11 $not$libresoc.v:199157$14499_Y - connect \$16 $reduce_or$libresoc.v:199158$14500_Y - connect \$15 $not$libresoc.v:199159$14501_Y - connect \$1 $not$libresoc.v:199160$14502_Y - connect \$20 $reduce_or$libresoc.v:199161$14503_Y - connect \$19 $not$libresoc.v:199162$14504_Y - connect \$24 $reduce_or$libresoc.v:199163$14505_Y - connect \$23 $not$libresoc.v:199164$14506_Y - connect \$28 $reduce_or$libresoc.v:199165$14507_Y - connect \$27 $not$libresoc.v:199166$14508_Y - connect \$32 $reduce_or$libresoc.v:199167$14509_Y - connect \$31 $not$libresoc.v:199168$14510_Y - connect \$36 $reduce_or$libresoc.v:199169$14511_Y - connect \$35 $not$libresoc.v:199170$14512_Y - connect \$39 $reduce_or$libresoc.v:199171$14513_Y - connect \$4 $reduce_or$libresoc.v:199172$14514_Y - connect \$3 $not$libresoc.v:199173$14515_Y - connect \$8 $reduce_or$libresoc.v:199174$14516_Y + connect \Y $reduce_or$libresoc.v:201487$14701_Y + end + connect \$7 $not$libresoc.v:201468$14682_Y + connect \$12 $reduce_or$libresoc.v:201469$14683_Y + connect \$11 $not$libresoc.v:201470$14684_Y + connect \$16 $reduce_or$libresoc.v:201471$14685_Y + connect \$15 $not$libresoc.v:201472$14686_Y + connect \$1 $not$libresoc.v:201473$14687_Y + connect \$20 $reduce_or$libresoc.v:201474$14688_Y + connect \$19 $not$libresoc.v:201475$14689_Y + connect \$24 $reduce_or$libresoc.v:201476$14690_Y + connect \$23 $not$libresoc.v:201477$14691_Y + connect \$28 $reduce_or$libresoc.v:201478$14692_Y + connect \$27 $not$libresoc.v:201479$14693_Y + connect \$32 $reduce_or$libresoc.v:201480$14694_Y + connect \$31 $not$libresoc.v:201481$14695_Y + connect \$36 $reduce_or$libresoc.v:201482$14696_Y + connect \$35 $not$libresoc.v:201483$14697_Y + connect \$39 $reduce_or$libresoc.v:201484$14698_Y + connect \$4 $reduce_or$libresoc.v:201485$14699_Y + connect \$3 $not$libresoc.v:201486$14700_Y + connect \$8 $reduce_or$libresoc.v:201487$14701_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -417324,15 +421347,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199192.1-199213.10" +attribute \src "libresoc.v:201505.1-201526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:199207.17-199207.89" - wire $not$libresoc.v:199207$14517_Y - attribute \src "libresoc.v:199208.17-199208.89" - wire $reduce_or$libresoc.v:199208$14518_Y + attribute \src "libresoc.v:201520.17-201520.89" + wire $not$libresoc.v:201520$14702_Y + attribute \src "libresoc.v:201521.17-201521.89" + wire $reduce_or$libresoc.v:201521$14703_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417348,37 +421371,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199207$14517 + cell $not $not$libresoc.v:201520$14702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199207$14517_Y + connect \Y $not$libresoc.v:201520$14702_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199208$14518 + cell $reduce_or $reduce_or$libresoc.v:201521$14703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199208$14518_Y + connect \Y $reduce_or$libresoc.v:201521$14703_Y end - connect \$1 $not$libresoc.v:199207$14517_Y - connect \$3 $reduce_or$libresoc.v:199208$14518_Y + connect \$1 $not$libresoc.v:201520$14702_Y + connect \$3 $reduce_or$libresoc.v:201521$14703_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199217.1-199238.10" +attribute \src "libresoc.v:201530.1-201551.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:199232.17-199232.89" - wire $not$libresoc.v:199232$14519_Y - attribute \src "libresoc.v:199233.17-199233.89" - wire $reduce_or$libresoc.v:199233$14520_Y + attribute \src "libresoc.v:201545.17-201545.89" + wire $not$libresoc.v:201545$14704_Y + attribute \src "libresoc.v:201546.17-201546.89" + wire $reduce_or$libresoc.v:201546$14705_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417394,41 +421417,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199232$14519 + cell $not $not$libresoc.v:201545$14704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:199232$14519_Y + connect \Y $not$libresoc.v:201545$14704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199233$14520 + cell $reduce_or $reduce_or$libresoc.v:201546$14705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199233$14520_Y + connect \Y $reduce_or$libresoc.v:201546$14705_Y end - connect \$1 $not$libresoc.v:199232$14519_Y - connect \$3 $reduce_or$libresoc.v:199233$14520_Y + connect \$1 $not$libresoc.v:201545$14704_Y + connect \$3 $reduce_or$libresoc.v:201546$14705_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:199242.1-199272.10" +attribute \src "libresoc.v:201555.1-201585.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:199263.17-199263.89" - wire width 2 $not$libresoc.v:199263$14521_Y - attribute \src "libresoc.v:199265.17-199265.91" - wire $not$libresoc.v:199265$14523_Y - attribute \src "libresoc.v:199264.17-199264.103" - wire $reduce_or$libresoc.v:199264$14522_Y - attribute \src "libresoc.v:199266.17-199266.89" - wire $reduce_or$libresoc.v:199266$14524_Y + attribute \src "libresoc.v:201576.17-201576.89" + wire width 2 $not$libresoc.v:201576$14706_Y + attribute \src "libresoc.v:201578.17-201578.91" + wire $not$libresoc.v:201578$14708_Y + attribute \src "libresoc.v:201577.17-201577.103" + wire $reduce_or$libresoc.v:201577$14707_Y + attribute \src "libresoc.v:201579.17-201579.89" + wire $reduce_or$libresoc.v:201579$14709_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417450,64 +421473,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199263$14521 + cell $not $not$libresoc.v:201576$14706 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:199263$14521_Y + connect \Y $not$libresoc.v:201576$14706_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199265$14523 + cell $not $not$libresoc.v:201578$14708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199265$14523_Y + connect \Y $not$libresoc.v:201578$14708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199264$14522 + cell $reduce_or $reduce_or$libresoc.v:201577$14707 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199264$14522_Y + connect \Y $reduce_or$libresoc.v:201577$14707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199266$14524 + cell $reduce_or $reduce_or$libresoc.v:201579$14709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199266$14524_Y + connect \Y $reduce_or$libresoc.v:201579$14709_Y end - connect \$1 $not$libresoc.v:199263$14521_Y - connect \$4 $reduce_or$libresoc.v:199264$14522_Y - connect \$3 $not$libresoc.v:199265$14523_Y - connect \$7 $reduce_or$libresoc.v:199266$14524_Y + connect \$1 $not$libresoc.v:201576$14706_Y + connect \$4 $reduce_or$libresoc.v:201577$14707_Y + connect \$3 $not$libresoc.v:201578$14708_Y + connect \$7 $reduce_or$libresoc.v:201579$14709_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199276.1-199315.10" +attribute \src "libresoc.v:201589.1-201628.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:199303.17-199303.91" - wire $not$libresoc.v:199303$14525_Y - attribute \src "libresoc.v:199305.17-199305.89" - wire width 3 $not$libresoc.v:199305$14527_Y - attribute \src "libresoc.v:199307.17-199307.91" - wire $not$libresoc.v:199307$14529_Y - attribute \src "libresoc.v:199304.18-199304.90" - wire $reduce_or$libresoc.v:199304$14526_Y - attribute \src "libresoc.v:199306.17-199306.103" - wire $reduce_or$libresoc.v:199306$14528_Y - attribute \src "libresoc.v:199308.17-199308.105" - wire $reduce_or$libresoc.v:199308$14530_Y + attribute \src "libresoc.v:201616.17-201616.91" + wire $not$libresoc.v:201616$14710_Y + attribute \src "libresoc.v:201618.17-201618.89" + wire width 3 $not$libresoc.v:201618$14712_Y + attribute \src "libresoc.v:201620.17-201620.91" + wire $not$libresoc.v:201620$14714_Y + attribute \src "libresoc.v:201617.18-201617.90" + wire $reduce_or$libresoc.v:201617$14711_Y + attribute \src "libresoc.v:201619.17-201619.103" + wire $reduce_or$libresoc.v:201619$14713_Y + attribute \src "libresoc.v:201621.17-201621.105" + wire $reduce_or$libresoc.v:201621$14715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -417535,59 +421558,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199303$14525 + cell $not $not$libresoc.v:201616$14710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199303$14525_Y + connect \Y $not$libresoc.v:201616$14710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199305$14527 + cell $not $not$libresoc.v:201618$14712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:199305$14527_Y + connect \Y $not$libresoc.v:201618$14712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199307$14529 + cell $not $not$libresoc.v:201620$14714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199307$14529_Y + connect \Y $not$libresoc.v:201620$14714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199304$14526 + cell $reduce_or $reduce_or$libresoc.v:201617$14711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199304$14526_Y + connect \Y $reduce_or$libresoc.v:201617$14711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199306$14528 + cell $reduce_or $reduce_or$libresoc.v:201619$14713 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199306$14528_Y + connect \Y $reduce_or$libresoc.v:201619$14713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199308$14530 + cell $reduce_or $reduce_or$libresoc.v:201621$14715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199308$14530_Y - end - connect \$7 $not$libresoc.v:199303$14525_Y - connect \$11 $reduce_or$libresoc.v:199304$14526_Y - connect \$1 $not$libresoc.v:199305$14527_Y - connect \$4 $reduce_or$libresoc.v:199306$14528_Y - connect \$3 $not$libresoc.v:199307$14529_Y - connect \$8 $reduce_or$libresoc.v:199308$14530_Y + connect \Y $reduce_or$libresoc.v:201621$14715_Y + end + connect \$7 $not$libresoc.v:201616$14710_Y + connect \$11 $reduce_or$libresoc.v:201617$14711_Y + connect \$1 $not$libresoc.v:201618$14712_Y + connect \$4 $reduce_or$libresoc.v:201619$14713_Y + connect \$3 $not$libresoc.v:201620$14714_Y + connect \$8 $reduce_or$libresoc.v:201621$14715_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -417595,27 +421618,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199319.1-199367.10" +attribute \src "libresoc.v:201632.1-201680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:199352.17-199352.91" - wire $not$libresoc.v:199352$14531_Y - attribute \src "libresoc.v:199354.18-199354.93" - wire $not$libresoc.v:199354$14533_Y - attribute \src "libresoc.v:199356.17-199356.89" - wire width 4 $not$libresoc.v:199356$14535_Y - attribute \src "libresoc.v:199358.17-199358.91" - wire $not$libresoc.v:199358$14537_Y - attribute \src "libresoc.v:199353.18-199353.106" - wire $reduce_or$libresoc.v:199353$14532_Y - attribute \src "libresoc.v:199355.18-199355.90" - wire $reduce_or$libresoc.v:199355$14534_Y - attribute \src "libresoc.v:199357.17-199357.103" - wire $reduce_or$libresoc.v:199357$14536_Y - attribute \src "libresoc.v:199359.17-199359.105" - wire $reduce_or$libresoc.v:199359$14538_Y + attribute \src "libresoc.v:201665.17-201665.91" + wire $not$libresoc.v:201665$14716_Y + attribute \src "libresoc.v:201667.18-201667.93" + wire $not$libresoc.v:201667$14718_Y + attribute \src "libresoc.v:201669.17-201669.89" + wire width 4 $not$libresoc.v:201669$14720_Y + attribute \src "libresoc.v:201671.17-201671.91" + wire $not$libresoc.v:201671$14722_Y + attribute \src "libresoc.v:201666.18-201666.106" + wire $reduce_or$libresoc.v:201666$14717_Y + attribute \src "libresoc.v:201668.18-201668.90" + wire $reduce_or$libresoc.v:201668$14719_Y + attribute \src "libresoc.v:201670.17-201670.103" + wire $reduce_or$libresoc.v:201670$14721_Y + attribute \src "libresoc.v:201672.17-201672.105" + wire $reduce_or$libresoc.v:201672$14723_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417649,77 +421672,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199352$14531 + cell $not $not$libresoc.v:201665$14716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199352$14531_Y + connect \Y $not$libresoc.v:201665$14716_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199354$14533 + cell $not $not$libresoc.v:201667$14718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199354$14533_Y + connect \Y $not$libresoc.v:201667$14718_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199356$14535 + cell $not $not$libresoc.v:201669$14720 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:199356$14535_Y + connect \Y $not$libresoc.v:201669$14720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199358$14537 + cell $not $not$libresoc.v:201671$14722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199358$14537_Y + connect \Y $not$libresoc.v:201671$14722_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199353$14532 + cell $reduce_or $reduce_or$libresoc.v:201666$14717 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199353$14532_Y + connect \Y $reduce_or$libresoc.v:201666$14717_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199355$14534 + cell $reduce_or $reduce_or$libresoc.v:201668$14719 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199355$14534_Y + connect \Y $reduce_or$libresoc.v:201668$14719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199357$14536 + cell $reduce_or $reduce_or$libresoc.v:201670$14721 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199357$14536_Y + connect \Y $reduce_or$libresoc.v:201670$14721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199359$14538 + cell $reduce_or $reduce_or$libresoc.v:201672$14723 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199359$14538_Y - end - connect \$7 $not$libresoc.v:199352$14531_Y - connect \$12 $reduce_or$libresoc.v:199353$14532_Y - connect \$11 $not$libresoc.v:199354$14533_Y - connect \$15 $reduce_or$libresoc.v:199355$14534_Y - connect \$1 $not$libresoc.v:199356$14535_Y - connect \$4 $reduce_or$libresoc.v:199357$14536_Y - connect \$3 $not$libresoc.v:199358$14537_Y - connect \$8 $reduce_or$libresoc.v:199359$14538_Y + connect \Y $reduce_or$libresoc.v:201672$14723_Y + end + connect \$7 $not$libresoc.v:201665$14716_Y + connect \$12 $reduce_or$libresoc.v:201666$14717_Y + connect \$11 $not$libresoc.v:201667$14718_Y + connect \$15 $reduce_or$libresoc.v:201668$14719_Y + connect \$1 $not$libresoc.v:201669$14720_Y + connect \$4 $reduce_or$libresoc.v:201670$14721_Y + connect \$3 $not$libresoc.v:201671$14722_Y + connect \$8 $reduce_or$libresoc.v:201672$14723_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417728,27 +421751,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199371.1-199419.10" +attribute \src "libresoc.v:201684.1-201732.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:199404.17-199404.91" - wire $not$libresoc.v:199404$14539_Y - attribute \src "libresoc.v:199406.18-199406.93" - wire $not$libresoc.v:199406$14541_Y - attribute \src "libresoc.v:199408.17-199408.89" - wire width 4 $not$libresoc.v:199408$14543_Y - attribute \src "libresoc.v:199410.17-199410.91" - wire $not$libresoc.v:199410$14545_Y - attribute \src "libresoc.v:199405.18-199405.106" - wire $reduce_or$libresoc.v:199405$14540_Y - attribute \src "libresoc.v:199407.18-199407.90" - wire $reduce_or$libresoc.v:199407$14542_Y - attribute \src "libresoc.v:199409.17-199409.103" - wire $reduce_or$libresoc.v:199409$14544_Y - attribute \src "libresoc.v:199411.17-199411.105" - wire $reduce_or$libresoc.v:199411$14546_Y + attribute \src "libresoc.v:201717.17-201717.91" + wire $not$libresoc.v:201717$14724_Y + attribute \src "libresoc.v:201719.18-201719.93" + wire $not$libresoc.v:201719$14726_Y + attribute \src "libresoc.v:201721.17-201721.89" + wire width 4 $not$libresoc.v:201721$14728_Y + attribute \src "libresoc.v:201723.17-201723.91" + wire $not$libresoc.v:201723$14730_Y + attribute \src "libresoc.v:201718.18-201718.106" + wire $reduce_or$libresoc.v:201718$14725_Y + attribute \src "libresoc.v:201720.18-201720.90" + wire $reduce_or$libresoc.v:201720$14727_Y + attribute \src "libresoc.v:201722.17-201722.103" + wire $reduce_or$libresoc.v:201722$14729_Y + attribute \src "libresoc.v:201724.17-201724.105" + wire $reduce_or$libresoc.v:201724$14731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417782,77 +421805,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199404$14539 + cell $not $not$libresoc.v:201717$14724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:199404$14539_Y + connect \Y $not$libresoc.v:201717$14724_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199406$14541 + cell $not $not$libresoc.v:201719$14726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:199406$14541_Y + connect \Y $not$libresoc.v:201719$14726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:199408$14543 + cell $not $not$libresoc.v:201721$14728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:199408$14543_Y + connect \Y $not$libresoc.v:201721$14728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:199410$14545 + cell $not $not$libresoc.v:201723$14730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:199410$14545_Y + connect \Y $not$libresoc.v:201723$14730_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199405$14540 + cell $reduce_or $reduce_or$libresoc.v:201718$14725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:199405$14540_Y + connect \Y $reduce_or$libresoc.v:201718$14725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:199407$14542 + cell $reduce_or $reduce_or$libresoc.v:201720$14727 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:199407$14542_Y + connect \Y $reduce_or$libresoc.v:201720$14727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199409$14544 + cell $reduce_or $reduce_or$libresoc.v:201722$14729 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:199409$14544_Y + connect \Y $reduce_or$libresoc.v:201722$14729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:199411$14546 + cell $reduce_or $reduce_or$libresoc.v:201724$14731 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:199411$14546_Y - end - connect \$7 $not$libresoc.v:199404$14539_Y - connect \$12 $reduce_or$libresoc.v:199405$14540_Y - connect \$11 $not$libresoc.v:199406$14541_Y - connect \$15 $reduce_or$libresoc.v:199407$14542_Y - connect \$1 $not$libresoc.v:199408$14543_Y - connect \$4 $reduce_or$libresoc.v:199409$14544_Y - connect \$3 $not$libresoc.v:199410$14545_Y - connect \$8 $reduce_or$libresoc.v:199411$14546_Y + connect \Y $reduce_or$libresoc.v:201724$14731_Y + end + connect \$7 $not$libresoc.v:201717$14724_Y + connect \$12 $reduce_or$libresoc.v:201718$14725_Y + connect \$11 $not$libresoc.v:201719$14726_Y + connect \$15 $reduce_or$libresoc.v:201720$14727_Y + connect \$1 $not$libresoc.v:201721$14728_Y + connect \$4 $reduce_or$libresoc.v:201722$14729_Y + connect \$3 $not$libresoc.v:201723$14730_Y + connect \$8 $reduce_or$libresoc.v:201724$14731_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417861,67 +421884,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:199423.1-199743.10" +attribute \src "libresoc.v:201736.1-202056.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:199424.7-199424.20" + attribute \src "libresoc.v:201737.7-201737.20" wire $0\initial[0:0] - attribute \src "libresoc.v:199703.3-199711.6" - wire width 3 $0\ren_delay$11$next[2:0]$14570 - attribute \src "libresoc.v:199601.3-199602.43" - wire width 3 $0\ren_delay$11[2:0]$14559 - attribute \src "libresoc.v:199560.13-199560.34" - wire width 3 $0\ren_delay$11[2:0]$14576 - attribute \src "libresoc.v:199665.3-199673.6" - wire width 3 $0\ren_delay$18$next[2:0]$14562 - attribute \src "libresoc.v:199599.3-199600.43" - wire width 3 $0\ren_delay$18[2:0]$14557 - attribute \src "libresoc.v:199564.13-199564.34" - wire width 3 $0\ren_delay$18[2:0]$14578 - attribute \src "libresoc.v:199684.3-199692.6" - wire width 3 $0\ren_delay$next[2:0]$14566 - attribute \src "libresoc.v:199603.3-199604.35" + attribute \src "libresoc.v:202016.3-202024.6" + wire width 3 $0\ren_delay$11$next[2:0]$14755 + attribute \src "libresoc.v:201914.3-201915.43" + wire width 3 $0\ren_delay$11[2:0]$14744 + attribute \src "libresoc.v:201873.13-201873.34" + wire width 3 $0\ren_delay$11[2:0]$14761 + attribute \src "libresoc.v:201978.3-201986.6" + wire width 3 $0\ren_delay$18$next[2:0]$14747 + attribute \src "libresoc.v:201912.3-201913.43" + wire width 3 $0\ren_delay$18[2:0]$14742 + attribute \src "libresoc.v:201877.13-201877.34" + wire width 3 $0\ren_delay$18[2:0]$14763 + attribute \src "libresoc.v:201997.3-202005.6" + wire width 3 $0\ren_delay$next[2:0]$14751 + attribute \src "libresoc.v:201916.3-201917.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:199693.3-199702.6" + attribute \src "libresoc.v:202006.3-202015.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:199712.3-199721.6" + attribute \src "libresoc.v:202025.3-202034.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:199674.3-199683.6" + attribute \src "libresoc.v:201987.3-201996.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:199703.3-199711.6" - wire width 3 $1\ren_delay$11$next[2:0]$14571 - attribute \src "libresoc.v:199665.3-199673.6" - wire width 3 $1\ren_delay$18$next[2:0]$14563 - attribute \src "libresoc.v:199684.3-199692.6" - wire width 3 $1\ren_delay$next[2:0]$14567 - attribute \src "libresoc.v:199558.13-199558.29" + attribute \src "libresoc.v:202016.3-202024.6" + wire width 3 $1\ren_delay$11$next[2:0]$14756 + attribute \src "libresoc.v:201978.3-201986.6" + wire width 3 $1\ren_delay$18$next[2:0]$14748 + attribute \src "libresoc.v:201997.3-202005.6" + wire width 3 $1\ren_delay$next[2:0]$14752 + attribute \src "libresoc.v:201871.13-201871.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:199693.3-199702.6" + attribute \src "libresoc.v:202006.3-202015.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:199712.3-199721.6" + attribute \src "libresoc.v:202025.3-202034.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:199674.3-199683.6" + attribute \src "libresoc.v:201987.3-201996.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:199590.17-199590.109" - wire width 2 $or$libresoc.v:199590$14547_Y - attribute \src "libresoc.v:199592.18-199592.126" - wire width 2 $or$libresoc.v:199592$14549_Y - attribute \src "libresoc.v:199593.18-199593.111" - wire width 2 $or$libresoc.v:199593$14550_Y - attribute \src "libresoc.v:199595.18-199595.126" - wire width 2 $or$libresoc.v:199595$14552_Y - attribute \src "libresoc.v:199596.18-199596.111" - wire width 2 $or$libresoc.v:199596$14553_Y - attribute \src "libresoc.v:199598.17-199598.125" - wire width 2 $or$libresoc.v:199598$14555_Y - attribute \src "libresoc.v:199591.18-199591.100" - wire $reduce_or$libresoc.v:199591$14548_Y - attribute \src "libresoc.v:199594.18-199594.100" - wire $reduce_or$libresoc.v:199594$14551_Y - attribute \src "libresoc.v:199597.17-199597.95" - wire $reduce_or$libresoc.v:199597$14554_Y + attribute \src "libresoc.v:201903.17-201903.109" + wire width 2 $or$libresoc.v:201903$14732_Y + attribute \src "libresoc.v:201905.18-201905.126" + wire width 2 $or$libresoc.v:201905$14734_Y + attribute \src "libresoc.v:201906.18-201906.111" + wire width 2 $or$libresoc.v:201906$14735_Y + attribute \src "libresoc.v:201908.18-201908.126" + wire width 2 $or$libresoc.v:201908$14737_Y + attribute \src "libresoc.v:201909.18-201909.111" + wire width 2 $or$libresoc.v:201909$14738_Y + attribute \src "libresoc.v:201911.17-201911.125" + wire width 2 $or$libresoc.v:201911$14740_Y + attribute \src "libresoc.v:201904.18-201904.100" + wire $reduce_or$libresoc.v:201904$14733_Y + attribute \src "libresoc.v:201907.18-201907.100" + wire $reduce_or$libresoc.v:201907$14736_Y + attribute \src "libresoc.v:201910.17-201910.95" + wire $reduce_or$libresoc.v:201910$14739_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -417940,9 +421963,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -417958,7 +421981,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:199424.7-199424.15" + attribute \src "libresoc.v:201737.7-201737.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -418087,7 +422110,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199590$14547 + cell $or $or$libresoc.v:201903$14732 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418095,10 +422118,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:199590$14547_Y + connect \Y $or$libresoc.v:201903$14732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199592$14549 + cell $or $or$libresoc.v:201905$14734 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418106,10 +422129,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:199592$14549_Y + connect \Y $or$libresoc.v:201905$14734_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199593$14550 + cell $or $or$libresoc.v:201906$14735 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418117,10 +422140,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:199593$14550_Y + connect \Y $or$libresoc.v:201906$14735_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199595$14552 + cell $or $or$libresoc.v:201908$14737 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418128,10 +422151,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:199595$14552_Y + connect \Y $or$libresoc.v:201908$14737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:199596$14553 + cell $or $or$libresoc.v:201909$14738 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418139,10 +422162,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:199596$14553_Y + connect \Y $or$libresoc.v:201909$14738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:199598$14555 + cell $or $or$libresoc.v:201911$14740 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -418150,34 +422173,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:199598$14555_Y + connect \Y $or$libresoc.v:201911$14740_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199591$14548 + cell $reduce_or $reduce_or$libresoc.v:201904$14733 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:199591$14548_Y + connect \Y $reduce_or$libresoc.v:201904$14733_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199594$14551 + cell $reduce_or $reduce_or$libresoc.v:201907$14736 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:199594$14551_Y + connect \Y $reduce_or$libresoc.v:201907$14736_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:199597$14554 + cell $reduce_or $reduce_or$libresoc.v:201910$14739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:199597$14554_Y + connect \Y $reduce_or$libresoc.v:201910$14739_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:199605.15-199624.4" + attribute \src "libresoc.v:201918.15-201937.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418199,7 +422222,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:199625.15-199644.4" + attribute \src "libresoc.v:201938.15-201957.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418221,7 +422244,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:199645.15-199664.4" + attribute \src "libresoc.v:201958.15-201977.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418242,67 +422265,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:199424.7-199424.20" - process $proc$libresoc.v:199424$14573 + attribute \src "libresoc.v:201737.7-201737.20" + process $proc$libresoc.v:201737$14758 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199558.13-199558.29" - process $proc$libresoc.v:199558$14574 + attribute \src "libresoc.v:201871.13-201871.29" + process $proc$libresoc.v:201871$14759 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:199560.13-199560.34" - process $proc$libresoc.v:199560$14575 + attribute \src "libresoc.v:201873.13-201873.34" + process $proc$libresoc.v:201873$14760 assign { } { } - assign $0\ren_delay$11[2:0]$14576 3'000 + assign $0\ren_delay$11[2:0]$14761 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14576 + update \ren_delay$11 $0\ren_delay$11[2:0]$14761 end - attribute \src "libresoc.v:199564.13-199564.34" - process $proc$libresoc.v:199564$14577 + attribute \src "libresoc.v:201877.13-201877.34" + process $proc$libresoc.v:201877$14762 assign { } { } - assign $0\ren_delay$18[2:0]$14578 3'000 + assign $0\ren_delay$18[2:0]$14763 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14578 + update \ren_delay$18 $0\ren_delay$18[2:0]$14763 end - attribute \src "libresoc.v:199599.3-199600.43" - process $proc$libresoc.v:199599$14556 + attribute \src "libresoc.v:201912.3-201913.43" + process $proc$libresoc.v:201912$14741 assign { } { } - assign $0\ren_delay$18[2:0]$14557 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14742 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14557 + update \ren_delay$18 $0\ren_delay$18[2:0]$14742 end - attribute \src "libresoc.v:199601.3-199602.43" - process $proc$libresoc.v:199601$14558 + attribute \src "libresoc.v:201914.3-201915.43" + process $proc$libresoc.v:201914$14743 assign { } { } - assign $0\ren_delay$11[2:0]$14559 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14744 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14559 + update \ren_delay$11 $0\ren_delay$11[2:0]$14744 end - attribute \src "libresoc.v:199603.3-199604.35" - process $proc$libresoc.v:199603$14560 + attribute \src "libresoc.v:201916.3-201917.35" + process $proc$libresoc.v:201916$14745 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:199665.3-199673.6" - process $proc$libresoc.v:199665$14561 + attribute \src "libresoc.v:201978.3-201986.6" + process $proc$libresoc.v:201978$14746 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14562 $1\ren_delay$18$next[2:0]$14563 - attribute \src "libresoc.v:199666.5-199666.29" + assign $0\ren_delay$18$next[2:0]$14747 $1\ren_delay$18$next[2:0]$14748 + attribute \src "libresoc.v:201979.5-201979.29" switch \initial - attribute \src "libresoc.v:199666.9-199666.17" + attribute \src "libresoc.v:201979.9-201979.17" case 1'1 case end @@ -418311,21 +422334,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14563 3'000 + assign $1\ren_delay$18$next[2:0]$14748 3'000 case - assign $1\ren_delay$18$next[2:0]$14563 \src3__ren + assign $1\ren_delay$18$next[2:0]$14748 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14562 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14747 end - attribute \src "libresoc.v:199674.3-199683.6" - process $proc$libresoc.v:199674$14564 + attribute \src "libresoc.v:201987.3-201996.6" + process $proc$libresoc.v:201987$14749 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:199675.5-199675.29" + attribute \src "libresoc.v:201988.5-201988.29" switch \initial - attribute \src "libresoc.v:199675.9-199675.17" + attribute \src "libresoc.v:201988.9-201988.17" case 1'1 case end @@ -418341,14 +422364,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:199684.3-199692.6" - process $proc$libresoc.v:199684$14565 + attribute \src "libresoc.v:201997.3-202005.6" + process $proc$libresoc.v:201997$14750 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14566 $1\ren_delay$next[2:0]$14567 - attribute \src "libresoc.v:199685.5-199685.29" + assign $0\ren_delay$next[2:0]$14751 $1\ren_delay$next[2:0]$14752 + attribute \src "libresoc.v:201998.5-201998.29" switch \initial - attribute \src "libresoc.v:199685.9-199685.17" + attribute \src "libresoc.v:201998.9-201998.17" case 1'1 case end @@ -418357,21 +422380,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14567 3'000 + assign $1\ren_delay$next[2:0]$14752 3'000 case - assign $1\ren_delay$next[2:0]$14567 \src1__ren + assign $1\ren_delay$next[2:0]$14752 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14566 + update \ren_delay$next $0\ren_delay$next[2:0]$14751 end - attribute \src "libresoc.v:199693.3-199702.6" - process $proc$libresoc.v:199693$14568 + attribute \src "libresoc.v:202006.3-202015.6" + process $proc$libresoc.v:202006$14753 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:199694.5-199694.29" + attribute \src "libresoc.v:202007.5-202007.29" switch \initial - attribute \src "libresoc.v:199694.9-199694.17" + attribute \src "libresoc.v:202007.9-202007.17" case 1'1 case end @@ -418387,14 +422410,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:199703.3-199711.6" - process $proc$libresoc.v:199703$14569 + attribute \src "libresoc.v:202016.3-202024.6" + process $proc$libresoc.v:202016$14754 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14570 $1\ren_delay$11$next[2:0]$14571 - attribute \src "libresoc.v:199704.5-199704.29" + assign $0\ren_delay$11$next[2:0]$14755 $1\ren_delay$11$next[2:0]$14756 + attribute \src "libresoc.v:202017.5-202017.29" switch \initial - attribute \src "libresoc.v:199704.9-199704.17" + attribute \src "libresoc.v:202017.9-202017.17" case 1'1 case end @@ -418403,21 +422426,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14571 3'000 + assign $1\ren_delay$11$next[2:0]$14756 3'000 case - assign $1\ren_delay$11$next[2:0]$14571 \src2__ren + assign $1\ren_delay$11$next[2:0]$14756 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14570 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14755 end - attribute \src "libresoc.v:199712.3-199721.6" - process $proc$libresoc.v:199712$14572 + attribute \src "libresoc.v:202025.3-202034.6" + process $proc$libresoc.v:202025$14757 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:199713.5-199713.29" + attribute \src "libresoc.v:202026.5-202026.29" switch \initial - attribute \src "libresoc.v:199713.9-199713.17" + attribute \src "libresoc.v:202026.9-202026.17" case 1'1 case end @@ -418433,15 +422456,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:199590$14547_Y - connect \$12 $reduce_or$libresoc.v:199591$14548_Y - connect \$14 $or$libresoc.v:199592$14549_Y - connect \$16 $or$libresoc.v:199593$14550_Y - connect \$19 $reduce_or$libresoc.v:199594$14551_Y - connect \$21 $or$libresoc.v:199595$14552_Y - connect \$23 $or$libresoc.v:199596$14553_Y - connect \$5 $reduce_or$libresoc.v:199597$14554_Y - connect \$7 $or$libresoc.v:199598$14555_Y + connect \$9 $or$libresoc.v:201903$14732_Y + connect \$12 $reduce_or$libresoc.v:201904$14733_Y + connect \$14 $or$libresoc.v:201905$14734_Y + connect \$16 $or$libresoc.v:201906$14735_Y + connect \$19 $reduce_or$libresoc.v:201907$14736_Y + connect \$21 $or$libresoc.v:201908$14737_Y + connect \$23 $or$libresoc.v:201909$14738_Y + connect \$5 $reduce_or$libresoc.v:201910$14739_Y + connect \$7 $or$libresoc.v:201911$14740_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -418464,153 +422487,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:199747.1-200061.10" +attribute \src "libresoc.v:202060.1-202374.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:199976.3-199984.6" - wire $0\core_irq_o$next[0:0]$14614 - attribute \src "libresoc.v:199867.3-199868.37" + attribute \src "libresoc.v:202289.3-202297.6" + wire $0\core_irq_o$next[0:0]$14799 + attribute \src "libresoc.v:202180.3-202181.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $0\cppr$10[7:0]$14618 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $0\cppr$next[7:0]$14597 - attribute \src "libresoc.v:199871.3-199872.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\cppr$10[7:0]$14803 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\cppr$next[7:0]$14782 + attribute \src "libresoc.v:202184.3-202185.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:199985.3-199994.6" + attribute \src "libresoc.v:202298.3-202307.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199748.7-199748.20" + attribute \src "libresoc.v:202061.7-202061.20" wire $0\initial[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $0\irq$12[0:0]$14619 - attribute \src "libresoc.v:199881.3-199896.6" - wire $0\irq$next[0:0]$14598 - attribute \src "libresoc.v:199875.3-199876.23" + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\irq$12[0:0]$14804 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\irq$next[0:0]$14783 + attribute \src "libresoc.v:202188.3-202189.23" wire $0\irq[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $0\mfrr$11[7:0]$14620 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $0\mfrr$next[7:0]$14599 - attribute \src "libresoc.v:199873.3-199874.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $0\mfrr$11[7:0]$14805 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $0\mfrr$next[7:0]$14784 + attribute \src "libresoc.v:202186.3-202187.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:199964.3-199975.6" + attribute \src "libresoc.v:202277.3-202288.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:199954.3-199963.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $0\wb_ack$14[0:0]$14621 - attribute \src "libresoc.v:199881.3-199896.6" - wire $0\wb_ack$next[0:0]$14600 - attribute \src "libresoc.v:199879.3-199880.29" + attribute \src "libresoc.v:202308.3-202370.6" + wire $0\wb_ack$14[0:0]$14806 + attribute \src "libresoc.v:202194.3-202209.6" + wire $0\wb_ack$next[0:0]$14785 + attribute \src "libresoc.v:202192.3-202193.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 32 $0\wb_rd_data$13[31:0]$14622 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 32 $0\wb_rd_data$next[31:0]$14601 - attribute \src "libresoc.v:199877.3-199878.37" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 32 $0\wb_rd_data$13[31:0]$14807 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $0\wb_rd_data$next[31:0]$14786 + attribute \src "libresoc.v:202190.3-202191.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202210.3-202237.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $0\xisr$9[23:0]$14623 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 24 $0\xisr$next[23:0]$14602 - attribute \src "libresoc.v:199869.3-199870.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $0\xisr$9[23:0]$14808 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $0\xisr$next[23:0]$14787 + attribute \src "libresoc.v:202182.3-202183.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:199976.3-199984.6" - wire $1\core_irq_o$next[0:0]$14615 - attribute \src "libresoc.v:199777.7-199777.24" + attribute \src "libresoc.v:202289.3-202297.6" + wire $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202090.7-202090.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $1\cppr$10[7:0]$14624 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $1\cppr$next[7:0]$14603 - attribute \src "libresoc.v:199781.13-199781.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\cppr$10[7:0]$14809 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\cppr$next[7:0]$14788 + attribute \src "libresoc.v:202094.13-202094.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:199985.3-199994.6" + attribute \src "libresoc.v:202298.3-202307.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $1\irq$12[0:0]$14634 - attribute \src "libresoc.v:199881.3-199896.6" - wire $1\irq$next[0:0]$14604 - attribute \src "libresoc.v:199810.7-199810.17" + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\irq$next[0:0]$14789 + attribute \src "libresoc.v:202123.7-202123.17" wire $1\irq[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $1\mfrr$11[7:0]$14625 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 8 $1\mfrr$next[7:0]$14605 - attribute \src "libresoc.v:199818.13-199818.25" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $1\mfrr$11[7:0]$14810 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 8 $1\mfrr$next[7:0]$14790 + attribute \src "libresoc.v:202131.13-202131.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:199964.3-199975.6" + attribute \src "libresoc.v:202277.3-202288.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:199954.3-199963.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire $1\wb_ack$14[0:0]$14626 - attribute \src "libresoc.v:199881.3-199896.6" - wire $1\wb_ack$next[0:0]$14606 - attribute \src "libresoc.v:199832.7-199832.20" + attribute \src "libresoc.v:202308.3-202370.6" + wire $1\wb_ack$14[0:0]$14811 + attribute \src "libresoc.v:202194.3-202209.6" + wire $1\wb_ack$next[0:0]$14791 + attribute \src "libresoc.v:202145.7-202145.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:199881.3-199896.6" - wire width 32 $1\wb_rd_data$next[31:0]$14607 - attribute \src "libresoc.v:199840.14-199840.32" + attribute \src "libresoc.v:202194.3-202209.6" + wire width 32 $1\wb_rd_data$next[31:0]$14792 + attribute \src "libresoc.v:202153.14-202153.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202210.3-202237.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $1\xisr$9[23:0]$14631 - attribute \src "libresoc.v:199881.3-199896.6" - wire width 24 $1\xisr$next[23:0]$14608 - attribute \src "libresoc.v:199850.14-199850.31" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $1\xisr$9[23:0]$14816 + attribute \src "libresoc.v:202194.3-202209.6" + wire width 24 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202163.14-202163.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $2\cppr$10[7:0]$14627 - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $2\mfrr$11[7:0]$14628 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\cppr$10[7:0]$14812 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $2\mfrr$11[7:0]$14813 + attribute \src "libresoc.v:202210.3-202237.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 24 $2\xisr$9[23:0]$14632 - attribute \src "libresoc.v:199925.3-199953.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 24 $2\xisr$9[23:0]$14817 + attribute \src "libresoc.v:202238.3-202266.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $3\cppr$10[7:0]$14629 - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $3\mfrr$11[7:0]$14630 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\cppr$10[7:0]$14814 + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $3\mfrr$11[7:0]$14815 + attribute \src "libresoc.v:202210.3-202237.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199995.3-200057.6" - wire width 8 $4\cppr$10[7:0]$14633 - attribute \src "libresoc.v:199897.3-199924.6" + attribute \src "libresoc.v:202308.3-202370.6" + wire width 8 $4\cppr$10[7:0]$14818 + attribute \src "libresoc.v:202210.3-202237.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199857.18-199857.116" - wire $and$libresoc.v:199857$14579_Y - attribute \src "libresoc.v:199861.18-199861.116" - wire $and$libresoc.v:199861$14583_Y - attribute \src "libresoc.v:199863.18-199863.116" - wire $and$libresoc.v:199863$14585_Y - attribute \src "libresoc.v:199866.17-199866.109" - wire $and$libresoc.v:199866$14588_Y - attribute \src "libresoc.v:199862.18-199862.110" - wire $eq$libresoc.v:199862$14584_Y - attribute \src "libresoc.v:199859.18-199859.114" - wire $lt$libresoc.v:199859$14581_Y - attribute \src "libresoc.v:199860.18-199860.109" - wire $lt$libresoc.v:199860$14582_Y - attribute \src "libresoc.v:199865.18-199865.114" - wire $lt$libresoc.v:199865$14587_Y - attribute \src "libresoc.v:199858.18-199858.109" - wire $ne$libresoc.v:199858$14580_Y - attribute \src "libresoc.v:199864.18-199864.109" - wire $ne$libresoc.v:199864$14586_Y + attribute \src "libresoc.v:202170.18-202170.116" + wire $and$libresoc.v:202170$14764_Y + attribute \src "libresoc.v:202174.18-202174.116" + wire $and$libresoc.v:202174$14768_Y + attribute \src "libresoc.v:202176.18-202176.116" + wire $and$libresoc.v:202176$14770_Y + attribute \src "libresoc.v:202179.17-202179.109" + wire $and$libresoc.v:202179$14773_Y + attribute \src "libresoc.v:202175.18-202175.110" + wire $eq$libresoc.v:202175$14769_Y + attribute \src "libresoc.v:202172.18-202172.114" + wire $lt$libresoc.v:202172$14766_Y + attribute \src "libresoc.v:202173.18-202173.109" + wire $lt$libresoc.v:202173$14767_Y + attribute \src "libresoc.v:202178.18-202178.114" + wire $lt$libresoc.v:202178$14772_Y + attribute \src "libresoc.v:202171.18-202171.109" + wire $ne$libresoc.v:202171$14765_Y + attribute \src "libresoc.v:202177.18-202177.109" + wire $ne$libresoc.v:202177$14771_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -418635,7 +422658,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -418669,7 +422692,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:199748.7-199748.15" + attribute \src "libresoc.v:202061.7-202061.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -418691,7 +422714,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -418720,7 +422743,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199857$14579 + cell $and $and$libresoc.v:202170$14764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418728,10 +422751,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199857$14579_Y + connect \Y $and$libresoc.v:202170$14764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199861$14583 + cell $and $and$libresoc.v:202174$14768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418739,10 +422762,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199861$14583_Y + connect \Y $and$libresoc.v:202174$14768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:199863$14585 + cell $and $and$libresoc.v:202176$14770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418750,10 +422773,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:199863$14585_Y + connect \Y $and$libresoc.v:202176$14770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:199866$14588 + cell $and $and$libresoc.v:202179$14773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418761,10 +422784,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:199866$14588_Y + connect \Y $and$libresoc.v:202179$14773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:199862$14584 + cell $eq $eq$libresoc.v:202175$14769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418772,10 +422795,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:199862$14584_Y + connect \Y $eq$libresoc.v:202175$14769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:199859$14581 + cell $lt $lt$libresoc.v:202172$14766 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418783,10 +422806,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:199859$14581_Y + connect \Y $lt$libresoc.v:202172$14766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:199860$14582 + cell $lt $lt$libresoc.v:202173$14767 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418794,10 +422817,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:199860$14582_Y + connect \Y $lt$libresoc.v:202173$14767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:199865$14587 + cell $lt $lt$libresoc.v:202178$14772 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418805,10 +422828,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:199865$14587_Y + connect \Y $lt$libresoc.v:202178$14772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:199858$14580 + cell $ne $ne$libresoc.v:202171$14765 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418816,10 +422839,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:199858$14580_Y + connect \Y $ne$libresoc.v:202171$14765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:199864$14586 + cell $ne $ne$libresoc.v:202177$14771 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418827,123 +422850,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:199864$14586_Y + connect \Y $ne$libresoc.v:202177$14771_Y end - attribute \src "libresoc.v:199748.7-199748.20" - process $proc$libresoc.v:199748$14635 + attribute \src "libresoc.v:202061.7-202061.20" + process $proc$libresoc.v:202061$14820 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199777.7-199777.24" - process $proc$libresoc.v:199777$14636 + attribute \src "libresoc.v:202090.7-202090.24" + process $proc$libresoc.v:202090$14821 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:199781.13-199781.25" - process $proc$libresoc.v:199781$14637 + attribute \src "libresoc.v:202094.13-202094.25" + process $proc$libresoc.v:202094$14822 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:199810.7-199810.17" - process $proc$libresoc.v:199810$14638 + attribute \src "libresoc.v:202123.7-202123.17" + process $proc$libresoc.v:202123$14823 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:199818.13-199818.25" - process $proc$libresoc.v:199818$14639 + attribute \src "libresoc.v:202131.13-202131.25" + process $proc$libresoc.v:202131$14824 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:199832.7-199832.20" - process $proc$libresoc.v:199832$14640 + attribute \src "libresoc.v:202145.7-202145.20" + process $proc$libresoc.v:202145$14825 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:199840.14-199840.32" - process $proc$libresoc.v:199840$14641 + attribute \src "libresoc.v:202153.14-202153.32" + process $proc$libresoc.v:202153$14826 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:199850.14-199850.31" - process $proc$libresoc.v:199850$14642 + attribute \src "libresoc.v:202163.14-202163.31" + process $proc$libresoc.v:202163$14827 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:199867.3-199868.37" - process $proc$libresoc.v:199867$14589 + attribute \src "libresoc.v:202180.3-202181.37" + process $proc$libresoc.v:202180$14774 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:199869.3-199870.25" - process $proc$libresoc.v:199869$14590 + attribute \src "libresoc.v:202182.3-202183.25" + process $proc$libresoc.v:202182$14775 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:199871.3-199872.25" - process $proc$libresoc.v:199871$14591 + attribute \src "libresoc.v:202184.3-202185.25" + process $proc$libresoc.v:202184$14776 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:199873.3-199874.25" - process $proc$libresoc.v:199873$14592 + attribute \src "libresoc.v:202186.3-202187.25" + process $proc$libresoc.v:202186$14777 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:199875.3-199876.23" - process $proc$libresoc.v:199875$14593 + attribute \src "libresoc.v:202188.3-202189.23" + process $proc$libresoc.v:202188$14778 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:199877.3-199878.37" - process $proc$libresoc.v:199877$14594 + attribute \src "libresoc.v:202190.3-202191.37" + process $proc$libresoc.v:202190$14779 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:199879.3-199880.29" - process $proc$libresoc.v:199879$14595 + attribute \src "libresoc.v:202192.3-202193.29" + process $proc$libresoc.v:202192$14780 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:199881.3-199896.6" - process $proc$libresoc.v:199881$14596 + attribute \src "libresoc.v:202194.3-202209.6" + process $proc$libresoc.v:202194$14781 assign { } { } assign { } { } assign { } { } @@ -418951,15 +422974,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14597 $1\cppr$next[7:0]$14603 - assign $0\irq$next[0:0]$14598 $1\irq$next[0:0]$14604 - assign $0\mfrr$next[7:0]$14599 $1\mfrr$next[7:0]$14605 - assign $0\wb_ack$next[0:0]$14600 $1\wb_ack$next[0:0]$14606 - assign $0\wb_rd_data$next[31:0]$14601 $1\wb_rd_data$next[31:0]$14607 - assign $0\xisr$next[23:0]$14602 $1\xisr$next[23:0]$14608 - attribute \src "libresoc.v:199882.5-199882.29" + assign $0\cppr$next[7:0]$14782 $1\cppr$next[7:0]$14788 + assign $0\irq$next[0:0]$14783 $1\irq$next[0:0]$14789 + assign $0\mfrr$next[7:0]$14784 $1\mfrr$next[7:0]$14790 + assign $0\wb_ack$next[0:0]$14785 $1\wb_ack$next[0:0]$14791 + assign $0\wb_rd_data$next[31:0]$14786 $1\wb_rd_data$next[31:0]$14792 + assign $0\xisr$next[23:0]$14787 $1\xisr$next[23:0]$14793 + attribute \src "libresoc.v:202195.5-202195.29" switch \initial - attribute \src "libresoc.v:199882.9-199882.17" + attribute \src "libresoc.v:202195.9-202195.17" case 1'1 case end @@ -418973,36 +422996,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14608 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14603 8'00000000 - assign $1\mfrr$next[7:0]$14605 8'11111111 - assign $1\irq$next[0:0]$14604 1'0 - assign $1\wb_rd_data$next[31:0]$14607 0 - assign $1\wb_ack$next[0:0]$14606 1'0 + assign $1\xisr$next[23:0]$14793 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14788 8'00000000 + assign $1\mfrr$next[7:0]$14790 8'11111111 + assign $1\irq$next[0:0]$14789 1'0 + assign $1\wb_rd_data$next[31:0]$14792 0 + assign $1\wb_ack$next[0:0]$14791 1'0 case - assign $1\cppr$next[7:0]$14603 \cppr$2 - assign $1\irq$next[0:0]$14604 \irq$4 - assign $1\mfrr$next[7:0]$14605 \mfrr$3 - assign $1\wb_ack$next[0:0]$14606 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14607 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14608 \xisr$1 + assign $1\cppr$next[7:0]$14788 \cppr$2 + assign $1\irq$next[0:0]$14789 \irq$4 + assign $1\mfrr$next[7:0]$14790 \mfrr$3 + assign $1\wb_ack$next[0:0]$14791 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14792 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14793 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14597 - update \irq$next $0\irq$next[0:0]$14598 - update \mfrr$next $0\mfrr$next[7:0]$14599 - update \wb_ack$next $0\wb_ack$next[0:0]$14600 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14601 - update \xisr$next $0\xisr$next[23:0]$14602 + update \cppr$next $0\cppr$next[7:0]$14782 + update \irq$next $0\irq$next[0:0]$14783 + update \mfrr$next $0\mfrr$next[7:0]$14784 + update \wb_ack$next $0\wb_ack$next[0:0]$14785 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14786 + update \xisr$next $0\xisr$next[23:0]$14787 end - attribute \src "libresoc.v:199897.3-199924.6" - process $proc$libresoc.v:199897$14609 + attribute \src "libresoc.v:202210.3-202237.6" + process $proc$libresoc.v:202210$14794 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:199898.5-199898.29" + attribute \src "libresoc.v:202211.5-202211.29" switch \initial - attribute \src "libresoc.v:199898.9-199898.17" + attribute \src "libresoc.v:202211.9-202211.17" case 1'1 case end @@ -419046,14 +423069,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:199925.3-199953.6" - process $proc$libresoc.v:199925$14610 + attribute \src "libresoc.v:202238.3-202266.6" + process $proc$libresoc.v:202238$14795 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:199926.5-199926.29" + attribute \src "libresoc.v:202239.5-202239.29" switch \initial - attribute \src "libresoc.v:199926.9-199926.17" + attribute \src "libresoc.v:202239.9-202239.17" case 1'1 case end @@ -419096,14 +423119,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:199954.3-199963.6" - process $proc$libresoc.v:199954$14611 + attribute \src "libresoc.v:202267.3-202276.6" + process $proc$libresoc.v:202267$14796 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:199955.5-199955.29" + attribute \src "libresoc.v:202268.5-202268.29" switch \initial - attribute \src "libresoc.v:199955.9-199955.17" + attribute \src "libresoc.v:202268.9-202268.17" case 1'1 case end @@ -419119,13 +423142,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:199964.3-199975.6" - process $proc$libresoc.v:199964$14612 + attribute \src "libresoc.v:202277.3-202288.6" + process $proc$libresoc.v:202277$14797 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:199965.5-199965.29" + attribute \src "libresoc.v:202278.5-202278.29" switch \initial - attribute \src "libresoc.v:199965.9-199965.17" + attribute \src "libresoc.v:202278.9-202278.17" case 1'1 case end @@ -419143,14 +423166,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:199976.3-199984.6" - process $proc$libresoc.v:199976$14613 + attribute \src "libresoc.v:202289.3-202297.6" + process $proc$libresoc.v:202289$14798 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14614 $1\core_irq_o$next[0:0]$14615 - attribute \src "libresoc.v:199977.5-199977.29" + assign $0\core_irq_o$next[0:0]$14799 $1\core_irq_o$next[0:0]$14800 + attribute \src "libresoc.v:202290.5-202290.29" switch \initial - attribute \src "libresoc.v:199977.9-199977.17" + attribute \src "libresoc.v:202290.9-202290.17" case 1'1 case end @@ -419159,21 +423182,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14615 1'0 + assign $1\core_irq_o$next[0:0]$14800 1'0 case - assign $1\core_irq_o$next[0:0]$14615 \irq + assign $1\core_irq_o$next[0:0]$14800 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14614 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14799 end - attribute \src "libresoc.v:199985.3-199994.6" - process $proc$libresoc.v:199985$14616 + attribute \src "libresoc.v:202298.3-202307.6" + process $proc$libresoc.v:202298$14801 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:199986.5-199986.29" + attribute \src "libresoc.v:202299.5-202299.29" switch \initial - attribute \src "libresoc.v:199986.9-199986.17" + attribute \src "libresoc.v:202299.9-202299.17" case 1'1 case end @@ -419189,8 +423212,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:199995.3-200057.6" - process $proc$libresoc.v:199995$14617 + attribute \src "libresoc.v:202308.3-202370.6" + process $proc$libresoc.v:202308$14802 assign { } { } assign { } { } assign { } { } @@ -419200,18 +423223,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14620 $1\mfrr$11[7:0]$14625 - assign $0\wb_ack$14[0:0]$14621 $1\wb_ack$14[0:0]$14626 + assign $0\mfrr$11[7:0]$14805 $1\mfrr$11[7:0]$14810 + assign $0\wb_ack$14[0:0]$14806 $1\wb_ack$14[0:0]$14811 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14623 $2\xisr$9[23:0]$14632 - assign $0\cppr$10[7:0]$14618 $4\cppr$10[7:0]$14633 - assign $0\wb_rd_data$13[31:0]$14622 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14619 $1\irq$12[0:0]$14634 - attribute \src "libresoc.v:199996.5-199996.29" + assign $0\xisr$9[23:0]$14808 $2\xisr$9[23:0]$14817 + assign $0\cppr$10[7:0]$14803 $4\cppr$10[7:0]$14818 + assign $0\wb_rd_data$13[31:0]$14807 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14804 $1\irq$12[0:0]$14819 + attribute \src "libresoc.v:202309.5-202309.29" switch \initial - attribute \src "libresoc.v:199996.9-199996.17" + attribute \src "libresoc.v:202309.9-202309.17" case 1'1 case end @@ -419222,712 +423245,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14626 1'1 - assign $1\cppr$10[7:0]$14624 $2\cppr$10[7:0]$14627 - assign $1\mfrr$11[7:0]$14625 $2\mfrr$11[7:0]$14628 + assign $1\wb_ack$14[0:0]$14811 1'1 + assign $1\cppr$10[7:0]$14809 $2\cppr$10[7:0]$14812 + assign $1\mfrr$11[7:0]$14810 $2\mfrr$11[7:0]$14813 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14627 $3\cppr$10[7:0]$14629 - assign $2\mfrr$11[7:0]$14628 $3\mfrr$11[7:0]$14630 + assign $2\cppr$10[7:0]$14812 $3\cppr$10[7:0]$14814 + assign $2\mfrr$11[7:0]$14813 $3\mfrr$11[7:0]$14815 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14630 \mfrr - assign $3\cppr$10[7:0]$14629 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14630 \mfrr - assign $3\cppr$10[7:0]$14629 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14814 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14629 \cppr + assign $3\cppr$10[7:0]$14814 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14630 \be_in [31:24] + assign $3\mfrr$11[7:0]$14815 \be_in [31:24] case - assign $3\cppr$10[7:0]$14629 \cppr - assign $3\mfrr$11[7:0]$14630 \mfrr + assign $3\cppr$10[7:0]$14814 \cppr + assign $3\mfrr$11[7:0]$14815 \mfrr end case - assign $2\cppr$10[7:0]$14627 \cppr - assign $2\mfrr$11[7:0]$14628 \mfrr + assign $2\cppr$10[7:0]$14812 \cppr + assign $2\mfrr$11[7:0]$14813 \mfrr end case - assign $1\cppr$10[7:0]$14624 \cppr - assign $1\mfrr$11[7:0]$14625 \mfrr - assign $1\wb_ack$14[0:0]$14626 1'0 + assign $1\cppr$10[7:0]$14809 \cppr + assign $1\mfrr$11[7:0]$14810 \mfrr + assign $1\wb_ack$14[0:0]$14811 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14631 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14816 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14631 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14816 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14632 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14817 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14632 $1\xisr$9[23:0]$14631 + assign $2\xisr$9[23:0]$14817 $1\xisr$9[23:0]$14816 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14633 \min_pri + assign $4\cppr$10[7:0]$14818 \min_pri case - assign $4\cppr$10[7:0]$14633 $1\cppr$10[7:0]$14624 + assign $4\cppr$10[7:0]$14818 $1\cppr$10[7:0]$14809 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14634 1'1 + assign $1\irq$12[0:0]$14819 1'1 case - assign $1\irq$12[0:0]$14634 1'0 + assign $1\irq$12[0:0]$14819 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14618 - update \irq$12 $0\irq$12[0:0]$14619 - update \mfrr$11 $0\mfrr$11[7:0]$14620 - update \wb_ack$14 $0\wb_ack$14[0:0]$14621 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14622 - update \xisr$9 $0\xisr$9[23:0]$14623 + update \cppr$10 $0\cppr$10[7:0]$14803 + update \irq$12 $0\irq$12[0:0]$14804 + update \mfrr$11 $0\mfrr$11[7:0]$14805 + update \wb_ack$14 $0\wb_ack$14[0:0]$14806 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14807 + update \xisr$9 $0\xisr$9[23:0]$14808 end - connect \$15 $and$libresoc.v:199857$14579_Y - connect \$17 $ne$libresoc.v:199858$14580_Y - connect \$19 $lt$libresoc.v:199859$14581_Y - connect \$21 $lt$libresoc.v:199860$14582_Y - connect \$23 $and$libresoc.v:199861$14583_Y - connect \$25 $eq$libresoc.v:199862$14584_Y - connect \$27 $and$libresoc.v:199863$14585_Y - connect \$29 $ne$libresoc.v:199864$14586_Y - connect \$31 $lt$libresoc.v:199865$14587_Y - connect \$7 $and$libresoc.v:199866$14588_Y + connect \$15 $and$libresoc.v:202170$14764_Y + connect \$17 $ne$libresoc.v:202171$14765_Y + connect \$19 $lt$libresoc.v:202172$14766_Y + connect \$21 $lt$libresoc.v:202173$14767_Y + connect \$23 $and$libresoc.v:202174$14768_Y + connect \$25 $eq$libresoc.v:202175$14769_Y + connect \$27 $and$libresoc.v:202176$14770_Y + connect \$29 $ne$libresoc.v:202177$14771_Y + connect \$31 $lt$libresoc.v:202178$14772_Y + connect \$7 $and$libresoc.v:202179$14773_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:200065.1-201114.10" +attribute \src "libresoc.v:202378.1-203427.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:200706.3-200715.6" + attribute \src "libresoc.v:203019.3-203028.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:200915.3-200924.6" + attribute \src "libresoc.v:203228.3-203237.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:200935.3-200944.6" + attribute \src "libresoc.v:203248.3-203257.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:200955.3-200964.6" + attribute \src "libresoc.v:203268.3-203277.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:203288.3-203297.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:201045.3-201054.6" + attribute \src "libresoc.v:203358.3-203367.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:201065.3-201074.6" + attribute \src "libresoc.v:203378.3-203387.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:200726.3-200735.6" + attribute \src "libresoc.v:203039.3-203048.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:200746.3-200755.6" + attribute \src "libresoc.v:203059.3-203068.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:200766.3-200775.6" + attribute \src "libresoc.v:203079.3-203088.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:200795.3-200804.6" + attribute \src "libresoc.v:203108.3-203117.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:200815.3-200824.6" + attribute \src "libresoc.v:203128.3-203137.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:200835.3-200844.6" + attribute \src "libresoc.v:203148.3-203157.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:200855.3-200864.6" + attribute \src "libresoc.v:203168.3-203177.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:200875.3-200884.6" + attribute \src "libresoc.v:203188.3-203197.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:200895.3-200904.6" + attribute \src "libresoc.v:203208.3-203217.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:200696.3-200705.6" + attribute \src "libresoc.v:203009.3-203018.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:200905.3-200914.6" + attribute \src "libresoc.v:203218.3-203227.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:200925.3-200934.6" + attribute \src "libresoc.v:203238.3-203247.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:200945.3-200954.6" + attribute \src "libresoc.v:203258.3-203267.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:203278.3-203287.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:203298.3-203307.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:201055.3-201064.6" + attribute \src "libresoc.v:203368.3-203377.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:200716.3-200725.6" + attribute \src "libresoc.v:203029.3-203038.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:200736.3-200745.6" + attribute \src "libresoc.v:203049.3-203058.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:200756.3-200765.6" + attribute \src "libresoc.v:203069.3-203078.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:200776.3-200785.6" + attribute \src "libresoc.v:203089.3-203098.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:200805.3-200814.6" + attribute \src "libresoc.v:203118.3-203127.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:200825.3-200834.6" + attribute \src "libresoc.v:203138.3-203147.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:200845.3-200854.6" + attribute \src "libresoc.v:203158.3-203167.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:200865.3-200874.6" + attribute \src "libresoc.v:203178.3-203187.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:200885.3-200894.6" + attribute \src "libresoc.v:203198.3-203207.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:201075.3-201084.6" + attribute \src "libresoc.v:203388.3-203397.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:200570.3-200571.25" + attribute \src "libresoc.v:202883.3-202884.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:200568.3-200569.28" + attribute \src "libresoc.v:202881.3-202882.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:201094.3-201102.6" - wire $0\ics_wb__ack$next[0:0]$14889 - attribute \src "libresoc.v:200604.3-200605.39" + attribute \src "libresoc.v:203407.3-203415.6" + wire $0\ics_wb__ack$next[0:0]$15074 + attribute \src "libresoc.v:202917.3-202918.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:201085.3-201093.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14886 - attribute \src "libresoc.v:200606.3-200607.43" + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15071 + attribute \src "libresoc.v:202919.3-202920.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:200066.7-200066.20" + attribute \src "libresoc.v:202379.7-202379.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200786.3-200794.6" - wire width 16 $0\int_level_l$next[15:0]$14858 - attribute \src "libresoc.v:200608.3-200609.39" + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $0\int_level_l$next[15:0]$15043 + attribute \src "libresoc.v:202921.3-202922.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive0_pri$next[7:0]$14768 - attribute \src "libresoc.v:200572.3-200573.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive0_pri$next[7:0]$14953 + attribute \src "libresoc.v:202885.3-202886.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive10_pri$next[7:0]$14769 - attribute \src "libresoc.v:200592.3-200593.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive10_pri$next[7:0]$14954 + attribute \src "libresoc.v:202905.3-202906.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive11_pri$next[7:0]$14770 - attribute \src "libresoc.v:200594.3-200595.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive11_pri$next[7:0]$14955 + attribute \src "libresoc.v:202907.3-202908.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive12_pri$next[7:0]$14771 - attribute \src "libresoc.v:200596.3-200597.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive12_pri$next[7:0]$14956 + attribute \src "libresoc.v:202909.3-202910.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive13_pri$next[7:0]$14772 - attribute \src "libresoc.v:200598.3-200599.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive13_pri$next[7:0]$14957 + attribute \src "libresoc.v:202911.3-202912.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive14_pri$next[7:0]$14773 - attribute \src "libresoc.v:200600.3-200601.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive14_pri$next[7:0]$14958 + attribute \src "libresoc.v:202913.3-202914.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive15_pri$next[7:0]$14774 - attribute \src "libresoc.v:200602.3-200603.37" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive15_pri$next[7:0]$14959 + attribute \src "libresoc.v:202915.3-202916.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive1_pri$next[7:0]$14775 - attribute \src "libresoc.v:200574.3-200575.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive1_pri$next[7:0]$14960 + attribute \src "libresoc.v:202887.3-202888.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive2_pri$next[7:0]$14776 - attribute \src "libresoc.v:200576.3-200577.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive2_pri$next[7:0]$14961 + attribute \src "libresoc.v:202889.3-202890.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive3_pri$next[7:0]$14777 - attribute \src "libresoc.v:200578.3-200579.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive3_pri$next[7:0]$14962 + attribute \src "libresoc.v:202891.3-202892.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive4_pri$next[7:0]$14778 - attribute \src "libresoc.v:200580.3-200581.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive4_pri$next[7:0]$14963 + attribute \src "libresoc.v:202893.3-202894.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive5_pri$next[7:0]$14779 - attribute \src "libresoc.v:200582.3-200583.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive5_pri$next[7:0]$14964 + attribute \src "libresoc.v:202895.3-202896.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive6_pri$next[7:0]$14780 - attribute \src "libresoc.v:200584.3-200585.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive6_pri$next[7:0]$14965 + attribute \src "libresoc.v:202897.3-202898.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive7_pri$next[7:0]$14781 - attribute \src "libresoc.v:200586.3-200587.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive7_pri$next[7:0]$14966 + attribute \src "libresoc.v:202899.3-202900.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive8_pri$next[7:0]$14782 - attribute \src "libresoc.v:200588.3-200589.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive8_pri$next[7:0]$14967 + attribute \src "libresoc.v:202901.3-202902.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $0\xive9_pri$next[7:0]$14783 - attribute \src "libresoc.v:200590.3-200591.35" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $0\xive9_pri$next[7:0]$14968 + attribute \src "libresoc.v:202903.3-202904.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:200706.3-200715.6" + attribute \src "libresoc.v:203019.3-203028.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:200915.3-200924.6" + attribute \src "libresoc.v:203228.3-203237.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:200935.3-200944.6" + attribute \src "libresoc.v:203248.3-203257.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:200955.3-200964.6" + attribute \src "libresoc.v:203268.3-203277.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:203288.3-203297.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:201045.3-201054.6" + attribute \src "libresoc.v:203358.3-203367.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:201065.3-201074.6" + attribute \src "libresoc.v:203378.3-203387.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:200726.3-200735.6" + attribute \src "libresoc.v:203039.3-203048.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:200746.3-200755.6" + attribute \src "libresoc.v:203059.3-203068.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:200766.3-200775.6" + attribute \src "libresoc.v:203079.3-203088.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:200795.3-200804.6" + attribute \src "libresoc.v:203108.3-203117.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:200815.3-200824.6" + attribute \src "libresoc.v:203128.3-203137.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:200835.3-200844.6" + attribute \src "libresoc.v:203148.3-203157.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:200855.3-200864.6" + attribute \src "libresoc.v:203168.3-203177.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:200875.3-200884.6" + attribute \src "libresoc.v:203188.3-203197.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:200895.3-200904.6" + attribute \src "libresoc.v:203208.3-203217.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:200696.3-200705.6" + attribute \src "libresoc.v:203009.3-203018.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:200905.3-200914.6" + attribute \src "libresoc.v:203218.3-203227.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:200925.3-200934.6" + attribute \src "libresoc.v:203238.3-203247.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:200945.3-200954.6" + attribute \src "libresoc.v:203258.3-203267.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:203278.3-203287.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:203298.3-203307.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:201055.3-201064.6" + attribute \src "libresoc.v:203368.3-203377.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:200716.3-200725.6" + attribute \src "libresoc.v:203029.3-203038.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:200736.3-200745.6" + attribute \src "libresoc.v:203049.3-203058.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:200756.3-200765.6" + attribute \src "libresoc.v:203069.3-203078.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:200776.3-200785.6" + attribute \src "libresoc.v:203089.3-203098.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:200805.3-200814.6" + attribute \src "libresoc.v:203118.3-203127.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:200825.3-200834.6" + attribute \src "libresoc.v:203138.3-203147.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:200845.3-200854.6" + attribute \src "libresoc.v:203158.3-203167.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:200865.3-200874.6" + attribute \src "libresoc.v:203178.3-203187.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:200885.3-200894.6" + attribute \src "libresoc.v:203198.3-203207.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:201075.3-201084.6" + attribute \src "libresoc.v:203388.3-203397.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:200347.13-200347.30" + attribute \src "libresoc.v:202660.13-202660.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:200352.13-200352.29" + attribute \src "libresoc.v:202665.13-202665.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:201094.3-201102.6" - wire $1\ics_wb__ack$next[0:0]$14890 - attribute \src "libresoc.v:200361.7-200361.25" + attribute \src "libresoc.v:203407.3-203415.6" + wire $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:202674.7-202674.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:201085.3-201093.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14887 - attribute \src "libresoc.v:200370.14-200370.35" + attribute \src "libresoc.v:203398.3-203406.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:202683.14-202683.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:200786.3-200794.6" - wire width 16 $1\int_level_l$next[15:0]$14859 - attribute \src "libresoc.v:200382.14-200382.36" + attribute \src "libresoc.v:203099.3-203107.6" + wire width 16 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:202695.14-202695.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive0_pri$next[7:0]$14784 - attribute \src "libresoc.v:200402.13-200402.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive0_pri$next[7:0]$14969 + attribute \src "libresoc.v:202715.13-202715.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive10_pri$next[7:0]$14785 - attribute \src "libresoc.v:200406.13-200406.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive10_pri$next[7:0]$14970 + attribute \src "libresoc.v:202719.13-202719.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive11_pri$next[7:0]$14786 - attribute \src "libresoc.v:200410.13-200410.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive11_pri$next[7:0]$14971 + attribute \src "libresoc.v:202723.13-202723.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive12_pri$next[7:0]$14787 - attribute \src "libresoc.v:200414.13-200414.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive12_pri$next[7:0]$14972 + attribute \src "libresoc.v:202727.13-202727.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive13_pri$next[7:0]$14788 - attribute \src "libresoc.v:200418.13-200418.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive13_pri$next[7:0]$14973 + attribute \src "libresoc.v:202731.13-202731.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive14_pri$next[7:0]$14789 - attribute \src "libresoc.v:200422.13-200422.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive14_pri$next[7:0]$14974 + attribute \src "libresoc.v:202735.13-202735.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive15_pri$next[7:0]$14790 - attribute \src "libresoc.v:200426.13-200426.31" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive15_pri$next[7:0]$14975 + attribute \src "libresoc.v:202739.13-202739.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive1_pri$next[7:0]$14791 - attribute \src "libresoc.v:200430.13-200430.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive1_pri$next[7:0]$14976 + attribute \src "libresoc.v:202743.13-202743.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive2_pri$next[7:0]$14792 - attribute \src "libresoc.v:200434.13-200434.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive2_pri$next[7:0]$14977 + attribute \src "libresoc.v:202747.13-202747.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive3_pri$next[7:0]$14793 - attribute \src "libresoc.v:200438.13-200438.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive3_pri$next[7:0]$14978 + attribute \src "libresoc.v:202751.13-202751.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive4_pri$next[7:0]$14794 - attribute \src "libresoc.v:200442.13-200442.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive4_pri$next[7:0]$14979 + attribute \src "libresoc.v:202755.13-202755.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive5_pri$next[7:0]$14795 - attribute \src "libresoc.v:200446.13-200446.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive5_pri$next[7:0]$14980 + attribute \src "libresoc.v:202759.13-202759.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive6_pri$next[7:0]$14796 - attribute \src "libresoc.v:200450.13-200450.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive6_pri$next[7:0]$14981 + attribute \src "libresoc.v:202763.13-202763.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive7_pri$next[7:0]$14797 - attribute \src "libresoc.v:200454.13-200454.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive7_pri$next[7:0]$14982 + attribute \src "libresoc.v:202767.13-202767.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive8_pri$next[7:0]$14798 - attribute \src "libresoc.v:200458.13-200458.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive8_pri$next[7:0]$14983 + attribute \src "libresoc.v:202771.13-202771.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $1\xive9_pri$next[7:0]$14799 - attribute \src "libresoc.v:200462.13-200462.30" + attribute \src "libresoc.v:202923.3-203008.6" + wire width 8 $1\xive9_pri$next[7:0]$14984 + attribute \src "libresoc.v:202775.13-202775.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:200995.3-201044.6" + attribute \src "libresoc.v:203308.3-203357.6" wire width 32 $2\be_out[31:0] - attribute \src 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$3\xive14_pri$next[7:0]$14821 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive15_pri$next[7:0]$14822 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive1_pri$next[7:0]$14823 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive2_pri$next[7:0]$14824 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive3_pri$next[7:0]$14825 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive4_pri$next[7:0]$14826 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive5_pri$next[7:0]$14827 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive6_pri$next[7:0]$14828 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive7_pri$next[7:0]$14829 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive8_pri$next[7:0]$14830 - attribute \src "libresoc.v:200610.3-200695.6" - wire width 8 $3\xive9_pri$next[7:0]$14831 - attribute \src "libresoc.v:200610.3-200695.6" - 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"libresoc.v:202845.18-202845.116" + wire width 8 $ternary$libresoc.v:202845$14895_Y + attribute \src "libresoc.v:202847.18-202847.116" + wire width 8 $ternary$libresoc.v:202847$14897_Y + attribute \src "libresoc.v:202850.18-202850.116" + wire width 8 $ternary$libresoc.v:202850$14900_Y + attribute \src "libresoc.v:202852.18-202852.116" + wire width 8 $ternary$libresoc.v:202852$14902_Y + attribute \src "libresoc.v:202854.18-202854.117" + wire width 8 $ternary$libresoc.v:202854$14904_Y + attribute \src "libresoc.v:202856.18-202856.117" + wire width 8 $ternary$libresoc.v:202856$14906_Y + attribute \src "libresoc.v:202858.18-202858.117" + wire width 8 $ternary$libresoc.v:202858$14908_Y + attribute \src "libresoc.v:202861.18-202861.117" + wire width 8 $ternary$libresoc.v:202861$14911_Y + attribute \src "libresoc.v:202863.18-202863.117" + wire width 8 $ternary$libresoc.v:202863$14913_Y + attribute \src "libresoc.v:202865.18-202865.117" + wire width 8 $ternary$libresoc.v:202865$14915_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -420138,7 +424161,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -420236,7 +424259,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:200066.7-200066.15" + attribute \src "libresoc.v:202379.7-202379.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -420256,7 +424279,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -420325,7 +424348,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200467$14645 + cell $and $and$libresoc.v:202780$14830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420333,10 +424356,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:200467$14645_Y + connect \Y $and$libresoc.v:202780$14830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200469$14647 + cell $and $and$libresoc.v:202782$14832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420344,10 +424367,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:200469$14647_Y + connect \Y $and$libresoc.v:202782$14832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200471$14649 + cell $and $and$libresoc.v:202784$14834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420355,10 +424378,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:200471$14649_Y + connect \Y $and$libresoc.v:202784$14834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200473$14651 + cell $and $and$libresoc.v:202786$14836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420366,10 +424389,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:200473$14651_Y + connect \Y $and$libresoc.v:202786$14836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200475$14653 + cell $and $and$libresoc.v:202788$14838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420377,10 +424400,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:200475$14653_Y + connect \Y $and$libresoc.v:202788$14838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200477$14655 + cell $and $and$libresoc.v:202790$14840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420388,10 +424411,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:200477$14655_Y + connect \Y $and$libresoc.v:202790$14840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200479$14657 + cell $and $and$libresoc.v:202792$14842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420399,10 +424422,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:200479$14657_Y + connect \Y $and$libresoc.v:202792$14842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200482$14660 + cell $and $and$libresoc.v:202795$14845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420410,10 +424433,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:200482$14660_Y + connect \Y $and$libresoc.v:202795$14845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200484$14662 + cell $and $and$libresoc.v:202797$14847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420421,10 +424444,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:200484$14662_Y + connect \Y $and$libresoc.v:202797$14847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200486$14664 + cell $and $and$libresoc.v:202799$14849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420432,10 +424455,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:200486$14664_Y + connect \Y $and$libresoc.v:202799$14849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200489$14667 + cell $and $and$libresoc.v:202802$14852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420443,10 +424466,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:200489$14667_Y + connect \Y $and$libresoc.v:202802$14852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200491$14669 + cell $and $and$libresoc.v:202804$14854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420454,10 +424477,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:200491$14669_Y + connect \Y $and$libresoc.v:202804$14854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200493$14671 + cell $and $and$libresoc.v:202806$14856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420465,10 +424488,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:200493$14671_Y + connect \Y $and$libresoc.v:202806$14856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200495$14673 + cell $and $and$libresoc.v:202808$14858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420476,10 +424499,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:200495$14673_Y + connect \Y $and$libresoc.v:202808$14858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200497$14675 + cell $and $and$libresoc.v:202810$14860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420487,10 +424510,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:200497$14675_Y + connect \Y $and$libresoc.v:202810$14860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200499$14677 + cell $and $and$libresoc.v:202812$14862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420498,10 +424521,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:200499$14677_Y + connect \Y $and$libresoc.v:202812$14862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200501$14679 + cell $and $and$libresoc.v:202814$14864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420509,10 +424532,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:200501$14679_Y + connect \Y $and$libresoc.v:202814$14864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200504$14682 + cell $and $and$libresoc.v:202817$14867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420520,10 +424543,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:200504$14682_Y + connect \Y $and$libresoc.v:202817$14867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200506$14684 + cell $and $and$libresoc.v:202819$14869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420531,10 +424554,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:200506$14684_Y + connect \Y $and$libresoc.v:202819$14869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200508$14686 + cell $and $and$libresoc.v:202821$14871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420542,10 +424565,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:200508$14686_Y + connect \Y $and$libresoc.v:202821$14871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200511$14689 + cell $and $and$libresoc.v:202824$14874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420553,10 +424576,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:200511$14689_Y + connect \Y $and$libresoc.v:202824$14874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200513$14691 + cell $and $and$libresoc.v:202826$14876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420564,10 +424587,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:200513$14691_Y + connect \Y $and$libresoc.v:202826$14876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200515$14693 + cell $and $and$libresoc.v:202828$14878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420575,10 +424598,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:200515$14693_Y + connect \Y $and$libresoc.v:202828$14878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200517$14695 + cell $and $and$libresoc.v:202830$14880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420586,10 +424609,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:200517$14695_Y + connect \Y $and$libresoc.v:202830$14880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200519$14697 + cell $and $and$libresoc.v:202832$14882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420597,10 +424620,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:200519$14697_Y + connect \Y $and$libresoc.v:202832$14882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200522$14700 + cell $and $and$libresoc.v:202835$14885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420608,10 +424631,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:200522$14700_Y + connect \Y $and$libresoc.v:202835$14885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:200546$14724 + cell $and $and$libresoc.v:202859$14909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420619,10 +424642,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:200546$14724_Y + connect \Y $and$libresoc.v:202859$14909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:200554$14732 + cell $and $and$libresoc.v:202867$14917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420630,10 +424653,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:200554$14732_Y + connect \Y $and$libresoc.v:202867$14917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200556$14734 + cell $and $and$libresoc.v:202869$14919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420641,10 +424664,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:200556$14734_Y + connect \Y $and$libresoc.v:202869$14919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200558$14736 + cell $and $and$libresoc.v:202871$14921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420652,10 +424675,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:200558$14736_Y + connect \Y $and$libresoc.v:202871$14921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200560$14738 + cell $and $and$libresoc.v:202873$14923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420663,10 +424686,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:200560$14738_Y + connect \Y $and$libresoc.v:202873$14923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200563$14741 + cell $and $and$libresoc.v:202876$14926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420674,10 +424697,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:200563$14741_Y + connect \Y $and$libresoc.v:202876$14926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200565$14743 + cell $and $and$libresoc.v:202878$14928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420685,10 +424708,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:200565$14743_Y + connect \Y $and$libresoc.v:202878$14928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:200567$14745 + cell $and $and$libresoc.v:202880$14930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420696,10 +424719,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:200567$14745_Y + connect \Y $and$libresoc.v:202880$14930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200481$14659 + cell $eq $eq$libresoc.v:202794$14844 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420707,10 +424730,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200481$14659_Y + connect \Y $eq$libresoc.v:202794$14844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200503$14681 + cell $eq $eq$libresoc.v:202816$14866 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420718,10 +424741,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200503$14681_Y + connect \Y $eq$libresoc.v:202816$14866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:200520$14698 + cell $eq $eq$libresoc.v:202833$14883 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420729,10 +424752,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:200520$14698_Y + connect \Y $eq$libresoc.v:202833$14883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200523$14701 + cell $eq $eq$libresoc.v:202836$14886 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420740,10 +424763,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:200523$14701_Y + connect \Y $eq$libresoc.v:202836$14886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200525$14703 + cell $eq $eq$libresoc.v:202838$14888 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420751,10 +424774,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200525$14703_Y + connect \Y $eq$libresoc.v:202838$14888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200527$14705 + cell $eq $eq$libresoc.v:202840$14890 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420762,10 +424785,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200527$14705_Y + connect \Y $eq$libresoc.v:202840$14890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200529$14707 + cell $eq $eq$libresoc.v:202842$14892 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420773,10 +424796,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200529$14707_Y + connect \Y $eq$libresoc.v:202842$14892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200531$14709 + cell $eq $eq$libresoc.v:202844$14894 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420784,10 +424807,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200531$14709_Y + connect \Y $eq$libresoc.v:202844$14894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200533$14711 + cell $eq $eq$libresoc.v:202846$14896 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420795,10 +424818,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200533$14711_Y + connect \Y $eq$libresoc.v:202846$14896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:200535$14713 + cell $eq $eq$libresoc.v:202848$14898 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420806,10 +424829,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:200535$14713_Y + connect \Y $eq$libresoc.v:202848$14898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200536$14714 + cell $eq $eq$libresoc.v:202849$14899 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420817,10 +424840,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200536$14714_Y + connect \Y $eq$libresoc.v:202849$14899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200538$14716 + cell $eq $eq$libresoc.v:202851$14901 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420828,10 +424851,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200538$14716_Y + connect \Y $eq$libresoc.v:202851$14901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200540$14718 + cell $eq $eq$libresoc.v:202853$14903 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420839,10 +424862,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200540$14718_Y + connect \Y $eq$libresoc.v:202853$14903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200542$14720 + cell $eq $eq$libresoc.v:202855$14905 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420850,10 +424873,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200542$14720_Y + connect \Y $eq$libresoc.v:202855$14905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200544$14722 + cell $eq $eq$libresoc.v:202857$14907 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420861,10 +424884,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200544$14722_Y + connect \Y $eq$libresoc.v:202857$14907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200547$14725 + cell $eq $eq$libresoc.v:202860$14910 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420872,10 +424895,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200547$14725_Y + connect \Y $eq$libresoc.v:202860$14910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200549$14727 + cell $eq $eq$libresoc.v:202862$14912 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420883,10 +424906,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200549$14727_Y + connect \Y $eq$libresoc.v:202862$14912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200551$14729 + cell $eq $eq$libresoc.v:202864$14914 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420894,10 +424917,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200551$14729_Y + connect \Y $eq$libresoc.v:202864$14914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:200562$14740 + cell $eq $eq$libresoc.v:202875$14925 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420905,10 +424928,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:200562$14740_Y + connect \Y $eq$libresoc.v:202875$14925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200466$14644 + cell $lt $lt$libresoc.v:202779$14829 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420916,10 +424939,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:200466$14644_Y + connect \Y $lt$libresoc.v:202779$14829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200468$14646 + cell $lt $lt$libresoc.v:202781$14831 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420927,10 +424950,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:200468$14646_Y + connect \Y $lt$libresoc.v:202781$14831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200470$14648 + cell $lt $lt$libresoc.v:202783$14833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420938,10 +424961,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:200470$14648_Y + connect \Y $lt$libresoc.v:202783$14833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200472$14650 + cell $lt $lt$libresoc.v:202785$14835 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420949,10 +424972,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:200472$14650_Y + connect \Y $lt$libresoc.v:202785$14835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200474$14652 + cell $lt $lt$libresoc.v:202787$14837 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420960,10 +424983,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:200474$14652_Y + connect \Y $lt$libresoc.v:202787$14837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200476$14654 + cell $lt $lt$libresoc.v:202789$14839 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420971,10 +424994,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:200476$14654_Y + connect \Y $lt$libresoc.v:202789$14839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200478$14656 + cell $lt $lt$libresoc.v:202791$14841 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420982,10 +425005,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:200478$14656_Y + connect \Y $lt$libresoc.v:202791$14841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200480$14658 + cell $lt $lt$libresoc.v:202793$14843 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420993,10 +425016,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:200480$14658_Y + connect \Y $lt$libresoc.v:202793$14843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200483$14661 + cell $lt $lt$libresoc.v:202796$14846 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421004,10 +425027,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:200483$14661_Y + connect \Y $lt$libresoc.v:202796$14846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200485$14663 + cell $lt $lt$libresoc.v:202798$14848 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421015,10 +425038,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:200485$14663_Y + connect \Y $lt$libresoc.v:202798$14848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200488$14666 + cell $lt $lt$libresoc.v:202801$14851 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421026,10 +425049,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:200488$14666_Y + connect \Y $lt$libresoc.v:202801$14851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200490$14668 + cell $lt $lt$libresoc.v:202803$14853 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421037,10 +425060,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:200490$14668_Y + connect \Y $lt$libresoc.v:202803$14853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200492$14670 + cell $lt $lt$libresoc.v:202805$14855 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421048,10 +425071,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:200492$14670_Y + connect \Y $lt$libresoc.v:202805$14855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200494$14672 + cell $lt $lt$libresoc.v:202807$14857 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421059,10 +425082,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:200494$14672_Y + connect \Y $lt$libresoc.v:202807$14857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200496$14674 + cell $lt $lt$libresoc.v:202809$14859 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421070,10 +425093,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:200496$14674_Y + connect \Y $lt$libresoc.v:202809$14859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200498$14676 + cell $lt $lt$libresoc.v:202811$14861 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421081,10 +425104,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:200498$14676_Y + connect \Y $lt$libresoc.v:202811$14861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200500$14678 + cell $lt $lt$libresoc.v:202813$14863 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421092,10 +425115,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:200500$14678_Y + connect \Y $lt$libresoc.v:202813$14863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200502$14680 + cell $lt $lt$libresoc.v:202815$14865 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421103,10 +425126,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:200502$14680_Y + connect \Y $lt$libresoc.v:202815$14865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200505$14683 + cell $lt $lt$libresoc.v:202818$14868 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421114,10 +425137,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:200505$14683_Y + connect \Y $lt$libresoc.v:202818$14868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200507$14685 + cell $lt $lt$libresoc.v:202820$14870 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421125,10 +425148,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:200507$14685_Y + connect \Y $lt$libresoc.v:202820$14870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200510$14688 + cell $lt $lt$libresoc.v:202823$14873 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421136,10 +425159,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:200510$14688_Y + connect \Y $lt$libresoc.v:202823$14873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200512$14690 + cell $lt $lt$libresoc.v:202825$14875 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421147,10 +425170,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:200512$14690_Y + connect \Y $lt$libresoc.v:202825$14875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200514$14692 + cell $lt $lt$libresoc.v:202827$14877 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421158,10 +425181,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:200514$14692_Y + connect \Y $lt$libresoc.v:202827$14877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200516$14694 + cell $lt $lt$libresoc.v:202829$14879 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421169,10 +425192,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:200516$14694_Y + connect \Y $lt$libresoc.v:202829$14879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200518$14696 + cell $lt $lt$libresoc.v:202831$14881 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421180,10 +425203,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:200518$14696_Y + connect \Y $lt$libresoc.v:202831$14881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200521$14699 + cell $lt $lt$libresoc.v:202834$14884 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421191,10 +425214,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:200521$14699_Y + connect \Y $lt$libresoc.v:202834$14884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200555$14733 + cell $lt $lt$libresoc.v:202868$14918 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421202,10 +425225,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:200555$14733_Y + connect \Y $lt$libresoc.v:202868$14918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200557$14735 + cell $lt $lt$libresoc.v:202870$14920 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421213,10 +425236,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:200557$14735_Y + connect \Y $lt$libresoc.v:202870$14920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200559$14737 + cell $lt $lt$libresoc.v:202872$14922 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421224,10 +425247,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:200559$14737_Y + connect \Y $lt$libresoc.v:202872$14922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200561$14739 + cell $lt $lt$libresoc.v:202874$14924 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421235,10 +425258,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:200561$14739_Y + connect \Y $lt$libresoc.v:202874$14924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200564$14742 + cell $lt $lt$libresoc.v:202877$14927 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421246,10 +425269,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:200564$14742_Y + connect \Y $lt$libresoc.v:202877$14927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:200566$14744 + cell $lt $lt$libresoc.v:202879$14929 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -421257,10 +425280,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:200566$14744_Y + connect \Y $lt$libresoc.v:202879$14929_Y end - attribute \src "libresoc.v:200553.18-200553.40" - cell $shr $shr$libresoc.v:200553$14731 + attribute \src "libresoc.v:202866.18-202866.40" + cell $shr $shr$libresoc.v:202866$14916 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -421268,469 +425291,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:200553$14731_Y + connect \Y $shr$libresoc.v:202866$14916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200465$14643 + cell $mux $ternary$libresoc.v:202778$14828 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:200465$14643_Y + connect \Y $ternary$libresoc.v:202778$14828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200487$14665 + cell $mux $ternary$libresoc.v:202800$14850 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:200487$14665_Y + connect \Y $ternary$libresoc.v:202800$14850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200509$14687 + cell $mux $ternary$libresoc.v:202822$14872 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:200509$14687_Y + connect \Y $ternary$libresoc.v:202822$14872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200524$14702 + cell $mux $ternary$libresoc.v:202837$14887 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:200524$14702_Y + connect \Y $ternary$libresoc.v:202837$14887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200526$14704 + cell $mux $ternary$libresoc.v:202839$14889 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:200526$14704_Y + connect \Y $ternary$libresoc.v:202839$14889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200528$14706 + cell $mux $ternary$libresoc.v:202841$14891 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:200528$14706_Y + connect \Y $ternary$libresoc.v:202841$14891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200530$14708 + cell $mux $ternary$libresoc.v:202843$14893 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:200530$14708_Y + connect \Y $ternary$libresoc.v:202843$14893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200532$14710 + cell $mux $ternary$libresoc.v:202845$14895 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:200532$14710_Y + connect \Y $ternary$libresoc.v:202845$14895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200534$14712 + cell $mux $ternary$libresoc.v:202847$14897 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:200534$14712_Y + connect \Y $ternary$libresoc.v:202847$14897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200537$14715 + cell $mux $ternary$libresoc.v:202850$14900 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:200537$14715_Y + connect \Y $ternary$libresoc.v:202850$14900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200539$14717 + cell $mux $ternary$libresoc.v:202852$14902 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:200539$14717_Y + connect \Y $ternary$libresoc.v:202852$14902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200541$14719 + cell $mux $ternary$libresoc.v:202854$14904 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:200541$14719_Y + connect \Y $ternary$libresoc.v:202854$14904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200543$14721 + cell $mux $ternary$libresoc.v:202856$14906 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:200543$14721_Y + connect \Y $ternary$libresoc.v:202856$14906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200545$14723 + cell $mux $ternary$libresoc.v:202858$14908 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:200545$14723_Y + connect \Y $ternary$libresoc.v:202858$14908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200548$14726 + cell $mux $ternary$libresoc.v:202861$14911 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:200548$14726_Y + connect \Y $ternary$libresoc.v:202861$14911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200550$14728 + cell $mux $ternary$libresoc.v:202863$14913 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:200550$14728_Y + connect \Y $ternary$libresoc.v:202863$14913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:200552$14730 + cell $mux $ternary$libresoc.v:202865$14915 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:200552$14730_Y + connect \Y $ternary$libresoc.v:202865$14915_Y end - attribute \src "libresoc.v:200066.7-200066.20" - process $proc$libresoc.v:200066$14891 + attribute \src "libresoc.v:202379.7-202379.20" + process $proc$libresoc.v:202379$15076 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200347.13-200347.30" - process $proc$libresoc.v:200347$14892 + attribute \src "libresoc.v:202660.13-202660.30" + process $proc$libresoc.v:202660$15077 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:200352.13-200352.29" - process $proc$libresoc.v:200352$14893 + attribute \src "libresoc.v:202665.13-202665.29" + process $proc$libresoc.v:202665$15078 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:200361.7-200361.25" - process $proc$libresoc.v:200361$14894 + attribute \src "libresoc.v:202674.7-202674.25" + process $proc$libresoc.v:202674$15079 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:200370.14-200370.35" - process $proc$libresoc.v:200370$14895 + attribute \src "libresoc.v:202683.14-202683.35" + process $proc$libresoc.v:202683$15080 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:200382.14-200382.36" - process $proc$libresoc.v:200382$14896 + attribute \src "libresoc.v:202695.14-202695.36" + process $proc$libresoc.v:202695$15081 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:200402.13-200402.30" - process $proc$libresoc.v:200402$14897 + attribute \src "libresoc.v:202715.13-202715.30" + process $proc$libresoc.v:202715$15082 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:200406.13-200406.31" - process $proc$libresoc.v:200406$14898 + attribute \src "libresoc.v:202719.13-202719.31" + process $proc$libresoc.v:202719$15083 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:200410.13-200410.31" - process $proc$libresoc.v:200410$14899 + attribute \src "libresoc.v:202723.13-202723.31" + process $proc$libresoc.v:202723$15084 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:200414.13-200414.31" - process $proc$libresoc.v:200414$14900 + attribute \src "libresoc.v:202727.13-202727.31" + process $proc$libresoc.v:202727$15085 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:200418.13-200418.31" - process $proc$libresoc.v:200418$14901 + attribute \src "libresoc.v:202731.13-202731.31" + process $proc$libresoc.v:202731$15086 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:200422.13-200422.31" - process $proc$libresoc.v:200422$14902 + attribute \src "libresoc.v:202735.13-202735.31" + process $proc$libresoc.v:202735$15087 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:200426.13-200426.31" - process $proc$libresoc.v:200426$14903 + attribute \src "libresoc.v:202739.13-202739.31" + process $proc$libresoc.v:202739$15088 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:200430.13-200430.30" - process $proc$libresoc.v:200430$14904 + attribute \src "libresoc.v:202743.13-202743.30" + process $proc$libresoc.v:202743$15089 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:200434.13-200434.30" - process $proc$libresoc.v:200434$14905 + attribute \src "libresoc.v:202747.13-202747.30" + process $proc$libresoc.v:202747$15090 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:200438.13-200438.30" - process $proc$libresoc.v:200438$14906 + attribute \src "libresoc.v:202751.13-202751.30" + process $proc$libresoc.v:202751$15091 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:200442.13-200442.30" - process $proc$libresoc.v:200442$14907 + attribute \src "libresoc.v:202755.13-202755.30" + process $proc$libresoc.v:202755$15092 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:200446.13-200446.30" - process $proc$libresoc.v:200446$14908 + attribute \src "libresoc.v:202759.13-202759.30" + process $proc$libresoc.v:202759$15093 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:200450.13-200450.30" - process $proc$libresoc.v:200450$14909 + attribute \src "libresoc.v:202763.13-202763.30" + process $proc$libresoc.v:202763$15094 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:200454.13-200454.30" - process $proc$libresoc.v:200454$14910 + attribute \src "libresoc.v:202767.13-202767.30" + process $proc$libresoc.v:202767$15095 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:200458.13-200458.30" - process $proc$libresoc.v:200458$14911 + attribute \src "libresoc.v:202771.13-202771.30" + process $proc$libresoc.v:202771$15096 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:200462.13-200462.30" - process $proc$libresoc.v:200462$14912 + attribute \src "libresoc.v:202775.13-202775.30" + process $proc$libresoc.v:202775$15097 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:200568.3-200569.28" - process $proc$libresoc.v:200568$14746 + attribute \src "libresoc.v:202881.3-202882.28" + process $proc$libresoc.v:202881$14931 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:200570.3-200571.25" - process $proc$libresoc.v:200570$14747 + attribute \src "libresoc.v:202883.3-202884.25" + process $proc$libresoc.v:202883$14932 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:200572.3-200573.35" - process $proc$libresoc.v:200572$14748 + attribute \src "libresoc.v:202885.3-202886.35" + process $proc$libresoc.v:202885$14933 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:200574.3-200575.35" - process $proc$libresoc.v:200574$14749 + attribute \src "libresoc.v:202887.3-202888.35" + process $proc$libresoc.v:202887$14934 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:200576.3-200577.35" - process $proc$libresoc.v:200576$14750 + attribute \src "libresoc.v:202889.3-202890.35" + process $proc$libresoc.v:202889$14935 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:200578.3-200579.35" - process $proc$libresoc.v:200578$14751 + attribute \src "libresoc.v:202891.3-202892.35" + process $proc$libresoc.v:202891$14936 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:200580.3-200581.35" - process $proc$libresoc.v:200580$14752 + attribute \src "libresoc.v:202893.3-202894.35" + process $proc$libresoc.v:202893$14937 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:200582.3-200583.35" - process $proc$libresoc.v:200582$14753 + attribute \src "libresoc.v:202895.3-202896.35" + process $proc$libresoc.v:202895$14938 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:200584.3-200585.35" - process $proc$libresoc.v:200584$14754 + attribute \src "libresoc.v:202897.3-202898.35" + process $proc$libresoc.v:202897$14939 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:200586.3-200587.35" - process $proc$libresoc.v:200586$14755 + attribute \src "libresoc.v:202899.3-202900.35" + process $proc$libresoc.v:202899$14940 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:200588.3-200589.35" - process $proc$libresoc.v:200588$14756 + attribute \src "libresoc.v:202901.3-202902.35" + process $proc$libresoc.v:202901$14941 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:200590.3-200591.35" - process $proc$libresoc.v:200590$14757 + attribute \src "libresoc.v:202903.3-202904.35" + process $proc$libresoc.v:202903$14942 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:200592.3-200593.37" - process $proc$libresoc.v:200592$14758 + attribute \src "libresoc.v:202905.3-202906.37" + process $proc$libresoc.v:202905$14943 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:200594.3-200595.37" - process $proc$libresoc.v:200594$14759 + attribute \src "libresoc.v:202907.3-202908.37" + process $proc$libresoc.v:202907$14944 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:200596.3-200597.37" - process $proc$libresoc.v:200596$14760 + attribute \src "libresoc.v:202909.3-202910.37" + process $proc$libresoc.v:202909$14945 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:200598.3-200599.37" - process $proc$libresoc.v:200598$14761 + attribute \src "libresoc.v:202911.3-202912.37" + process $proc$libresoc.v:202911$14946 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:200600.3-200601.37" - process $proc$libresoc.v:200600$14762 + attribute \src "libresoc.v:202913.3-202914.37" + process $proc$libresoc.v:202913$14947 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:200602.3-200603.37" - process $proc$libresoc.v:200602$14763 + attribute \src "libresoc.v:202915.3-202916.37" + process $proc$libresoc.v:202915$14948 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:200604.3-200605.39" - process $proc$libresoc.v:200604$14764 + attribute \src "libresoc.v:202917.3-202918.39" + process $proc$libresoc.v:202917$14949 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:200606.3-200607.43" - process $proc$libresoc.v:200606$14765 + attribute \src "libresoc.v:202919.3-202920.43" + process $proc$libresoc.v:202919$14950 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:200608.3-200609.39" - process $proc$libresoc.v:200608$14766 + attribute \src "libresoc.v:202921.3-202922.39" + process $proc$libresoc.v:202921$14951 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:200610.3-200695.6" - process $proc$libresoc.v:200610$14767 + attribute \src "libresoc.v:202923.3-203008.6" + process $proc$libresoc.v:202923$14952 assign { } { } assign { } { } assign { } { } @@ -421779,25 +425802,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14768 $4\xive0_pri$next[7:0]$14832 - assign $0\xive10_pri$next[7:0]$14769 $4\xive10_pri$next[7:0]$14833 - assign $0\xive11_pri$next[7:0]$14770 $4\xive11_pri$next[7:0]$14834 - assign $0\xive12_pri$next[7:0]$14771 $4\xive12_pri$next[7:0]$14835 - assign $0\xive13_pri$next[7:0]$14772 $4\xive13_pri$next[7:0]$14836 - assign $0\xive14_pri$next[7:0]$14773 $4\xive14_pri$next[7:0]$14837 - assign $0\xive15_pri$next[7:0]$14774 $4\xive15_pri$next[7:0]$14838 - assign $0\xive1_pri$next[7:0]$14775 $4\xive1_pri$next[7:0]$14839 - assign $0\xive2_pri$next[7:0]$14776 $4\xive2_pri$next[7:0]$14840 - assign $0\xive3_pri$next[7:0]$14777 $4\xive3_pri$next[7:0]$14841 - assign $0\xive4_pri$next[7:0]$14778 $4\xive4_pri$next[7:0]$14842 - assign $0\xive5_pri$next[7:0]$14779 $4\xive5_pri$next[7:0]$14843 - assign $0\xive6_pri$next[7:0]$14780 $4\xive6_pri$next[7:0]$14844 - assign $0\xive7_pri$next[7:0]$14781 $4\xive7_pri$next[7:0]$14845 - assign $0\xive8_pri$next[7:0]$14782 $4\xive8_pri$next[7:0]$14846 - assign $0\xive9_pri$next[7:0]$14783 $4\xive9_pri$next[7:0]$14847 - attribute \src "libresoc.v:200611.5-200611.29" + assign $0\xive0_pri$next[7:0]$14953 $4\xive0_pri$next[7:0]$15017 + assign $0\xive10_pri$next[7:0]$14954 $4\xive10_pri$next[7:0]$15018 + assign $0\xive11_pri$next[7:0]$14955 $4\xive11_pri$next[7:0]$15019 + assign $0\xive12_pri$next[7:0]$14956 $4\xive12_pri$next[7:0]$15020 + assign $0\xive13_pri$next[7:0]$14957 $4\xive13_pri$next[7:0]$15021 + assign $0\xive14_pri$next[7:0]$14958 $4\xive14_pri$next[7:0]$15022 + assign $0\xive15_pri$next[7:0]$14959 $4\xive15_pri$next[7:0]$15023 + assign $0\xive1_pri$next[7:0]$14960 $4\xive1_pri$next[7:0]$15024 + assign $0\xive2_pri$next[7:0]$14961 $4\xive2_pri$next[7:0]$15025 + assign $0\xive3_pri$next[7:0]$14962 $4\xive3_pri$next[7:0]$15026 + assign $0\xive4_pri$next[7:0]$14963 $4\xive4_pri$next[7:0]$15027 + assign $0\xive5_pri$next[7:0]$14964 $4\xive5_pri$next[7:0]$15028 + assign $0\xive6_pri$next[7:0]$14965 $4\xive6_pri$next[7:0]$15029 + assign $0\xive7_pri$next[7:0]$14966 $4\xive7_pri$next[7:0]$15030 + assign $0\xive8_pri$next[7:0]$14967 $4\xive8_pri$next[7:0]$15031 + assign $0\xive9_pri$next[7:0]$14968 $4\xive9_pri$next[7:0]$15032 + attribute \src "libresoc.v:202924.5-202924.29" switch \initial - attribute \src "libresoc.v:200611.9-200611.17" + attribute \src "libresoc.v:202924.9-202924.17" case 1'1 case end @@ -421821,22 +425844,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14784 $2\xive0_pri$next[7:0]$14800 - assign $1\xive10_pri$next[7:0]$14785 $2\xive10_pri$next[7:0]$14801 - assign $1\xive11_pri$next[7:0]$14786 $2\xive11_pri$next[7:0]$14802 - assign $1\xive12_pri$next[7:0]$14787 $2\xive12_pri$next[7:0]$14803 - assign $1\xive13_pri$next[7:0]$14788 $2\xive13_pri$next[7:0]$14804 - assign $1\xive14_pri$next[7:0]$14789 $2\xive14_pri$next[7:0]$14805 - assign $1\xive15_pri$next[7:0]$14790 $2\xive15_pri$next[7:0]$14806 - assign $1\xive1_pri$next[7:0]$14791 $2\xive1_pri$next[7:0]$14807 - assign $1\xive2_pri$next[7:0]$14792 $2\xive2_pri$next[7:0]$14808 - assign $1\xive3_pri$next[7:0]$14793 $2\xive3_pri$next[7:0]$14809 - assign $1\xive4_pri$next[7:0]$14794 $2\xive4_pri$next[7:0]$14810 - assign $1\xive5_pri$next[7:0]$14795 $2\xive5_pri$next[7:0]$14811 - assign $1\xive6_pri$next[7:0]$14796 $2\xive6_pri$next[7:0]$14812 - assign $1\xive7_pri$next[7:0]$14797 $2\xive7_pri$next[7:0]$14813 - assign $1\xive8_pri$next[7:0]$14798 $2\xive8_pri$next[7:0]$14814 - assign $1\xive9_pri$next[7:0]$14799 $2\xive9_pri$next[7:0]$14815 + assign $1\xive0_pri$next[7:0]$14969 $2\xive0_pri$next[7:0]$14985 + assign $1\xive10_pri$next[7:0]$14970 $2\xive10_pri$next[7:0]$14986 + assign $1\xive11_pri$next[7:0]$14971 $2\xive11_pri$next[7:0]$14987 + assign $1\xive12_pri$next[7:0]$14972 $2\xive12_pri$next[7:0]$14988 + assign $1\xive13_pri$next[7:0]$14973 $2\xive13_pri$next[7:0]$14989 + assign $1\xive14_pri$next[7:0]$14974 $2\xive14_pri$next[7:0]$14990 + assign $1\xive15_pri$next[7:0]$14975 $2\xive15_pri$next[7:0]$14991 + assign $1\xive1_pri$next[7:0]$14976 $2\xive1_pri$next[7:0]$14992 + assign $1\xive2_pri$next[7:0]$14977 $2\xive2_pri$next[7:0]$14993 + assign $1\xive3_pri$next[7:0]$14978 $2\xive3_pri$next[7:0]$14994 + assign $1\xive4_pri$next[7:0]$14979 $2\xive4_pri$next[7:0]$14995 + assign $1\xive5_pri$next[7:0]$14980 $2\xive5_pri$next[7:0]$14996 + assign $1\xive6_pri$next[7:0]$14981 $2\xive6_pri$next[7:0]$14997 + assign $1\xive7_pri$next[7:0]$14982 $2\xive7_pri$next[7:0]$14998 + assign $1\xive8_pri$next[7:0]$14983 $2\xive8_pri$next[7:0]$14999 + assign $1\xive9_pri$next[7:0]$14984 $2\xive9_pri$next[7:0]$15000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -421857,381 +425880,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14800 $3\xive0_pri$next[7:0]$14816 - assign $2\xive10_pri$next[7:0]$14801 $3\xive10_pri$next[7:0]$14817 - assign $2\xive11_pri$next[7:0]$14802 $3\xive11_pri$next[7:0]$14818 - assign $2\xive12_pri$next[7:0]$14803 $3\xive12_pri$next[7:0]$14819 - assign $2\xive13_pri$next[7:0]$14804 $3\xive13_pri$next[7:0]$14820 - assign $2\xive14_pri$next[7:0]$14805 $3\xive14_pri$next[7:0]$14821 - assign $2\xive15_pri$next[7:0]$14806 $3\xive15_pri$next[7:0]$14822 - assign $2\xive1_pri$next[7:0]$14807 $3\xive1_pri$next[7:0]$14823 - assign $2\xive2_pri$next[7:0]$14808 $3\xive2_pri$next[7:0]$14824 - assign $2\xive3_pri$next[7:0]$14809 $3\xive3_pri$next[7:0]$14825 - assign $2\xive4_pri$next[7:0]$14810 $3\xive4_pri$next[7:0]$14826 - assign $2\xive5_pri$next[7:0]$14811 $3\xive5_pri$next[7:0]$14827 - assign $2\xive6_pri$next[7:0]$14812 $3\xive6_pri$next[7:0]$14828 - assign $2\xive7_pri$next[7:0]$14813 $3\xive7_pri$next[7:0]$14829 - assign $2\xive8_pri$next[7:0]$14814 $3\xive8_pri$next[7:0]$14830 - assign $2\xive9_pri$next[7:0]$14815 $3\xive9_pri$next[7:0]$14831 + assign $2\xive0_pri$next[7:0]$14985 $3\xive0_pri$next[7:0]$15001 + assign $2\xive10_pri$next[7:0]$14986 $3\xive10_pri$next[7:0]$15002 + assign $2\xive11_pri$next[7:0]$14987 $3\xive11_pri$next[7:0]$15003 + assign $2\xive12_pri$next[7:0]$14988 $3\xive12_pri$next[7:0]$15004 + assign $2\xive13_pri$next[7:0]$14989 $3\xive13_pri$next[7:0]$15005 + assign $2\xive14_pri$next[7:0]$14990 $3\xive14_pri$next[7:0]$15006 + assign $2\xive15_pri$next[7:0]$14991 $3\xive15_pri$next[7:0]$15007 + assign $2\xive1_pri$next[7:0]$14992 $3\xive1_pri$next[7:0]$15008 + assign $2\xive2_pri$next[7:0]$14993 $3\xive2_pri$next[7:0]$15009 + assign $2\xive3_pri$next[7:0]$14994 $3\xive3_pri$next[7:0]$15010 + assign $2\xive4_pri$next[7:0]$14995 $3\xive4_pri$next[7:0]$15011 + assign $2\xive5_pri$next[7:0]$14996 $3\xive5_pri$next[7:0]$15012 + assign $2\xive6_pri$next[7:0]$14997 $3\xive6_pri$next[7:0]$15013 + assign $2\xive7_pri$next[7:0]$14998 $3\xive7_pri$next[7:0]$15014 + assign $2\xive8_pri$next[7:0]$14999 $3\xive8_pri$next[7:0]$15015 + assign $2\xive9_pri$next[7:0]$15000 $3\xive9_pri$next[7:0]$15016 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive0_pri$next[7:0]$14816 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive0_pri$next[7:0]$15001 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive1_pri$next[7:0]$14823 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive1_pri$next[7:0]$15008 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive2_pri$next[7:0]$14824 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive2_pri$next[7:0]$15009 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive3_pri$next[7:0]$14825 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive3_pri$next[7:0]$15010 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive4_pri$next[7:0]$14826 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive4_pri$next[7:0]$15011 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive5_pri$next[7:0]$14827 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive5_pri$next[7:0]$15012 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive6_pri$next[7:0]$14828 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive6_pri$next[7:0]$15013 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive7_pri$next[7:0]$14829 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive7_pri$next[7:0]$15014 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive8_pri$next[7:0]$14830 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive8_pri$next[7:0]$15015 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14831 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$15016 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive10_pri$next[7:0]$14817 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive10_pri$next[7:0]$15002 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive11_pri$next[7:0]$14818 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive11_pri$next[7:0]$15003 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive12_pri$next[7:0]$14819 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive12_pri$next[7:0]$15004 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive13_pri$next[7:0]$14820 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive13_pri$next[7:0]$15005 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive14_pri$next[7:0]$14821 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive14_pri$next[7:0]$15006 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri - assign $3\xive15_pri$next[7:0]$14822 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive15_pri$next[7:0]$15007 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14816 \xive0_pri - assign $3\xive10_pri$next[7:0]$14817 \xive10_pri - assign $3\xive11_pri$next[7:0]$14818 \xive11_pri - assign $3\xive12_pri$next[7:0]$14819 \xive12_pri - assign $3\xive13_pri$next[7:0]$14820 \xive13_pri - assign $3\xive14_pri$next[7:0]$14821 \xive14_pri - assign $3\xive15_pri$next[7:0]$14822 \xive15_pri - assign $3\xive1_pri$next[7:0]$14823 \xive1_pri - assign $3\xive2_pri$next[7:0]$14824 \xive2_pri - assign $3\xive3_pri$next[7:0]$14825 \xive3_pri - assign $3\xive4_pri$next[7:0]$14826 \xive4_pri - assign $3\xive5_pri$next[7:0]$14827 \xive5_pri - assign $3\xive6_pri$next[7:0]$14828 \xive6_pri - assign $3\xive7_pri$next[7:0]$14829 \xive7_pri - assign $3\xive8_pri$next[7:0]$14830 \xive8_pri - assign $3\xive9_pri$next[7:0]$14831 \xive9_pri + assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive9_pri$next[7:0]$15016 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14800 \xive0_pri - assign $2\xive10_pri$next[7:0]$14801 \xive10_pri - assign $2\xive11_pri$next[7:0]$14802 \xive11_pri - assign $2\xive12_pri$next[7:0]$14803 \xive12_pri - assign $2\xive13_pri$next[7:0]$14804 \xive13_pri - assign $2\xive14_pri$next[7:0]$14805 \xive14_pri - assign $2\xive15_pri$next[7:0]$14806 \xive15_pri - assign $2\xive1_pri$next[7:0]$14807 \xive1_pri - assign $2\xive2_pri$next[7:0]$14808 \xive2_pri - assign $2\xive3_pri$next[7:0]$14809 \xive3_pri - assign $2\xive4_pri$next[7:0]$14810 \xive4_pri - assign $2\xive5_pri$next[7:0]$14811 \xive5_pri - assign $2\xive6_pri$next[7:0]$14812 \xive6_pri - assign $2\xive7_pri$next[7:0]$14813 \xive7_pri - assign $2\xive8_pri$next[7:0]$14814 \xive8_pri - assign $2\xive9_pri$next[7:0]$14815 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14784 \xive0_pri - assign $1\xive10_pri$next[7:0]$14785 \xive10_pri - assign $1\xive11_pri$next[7:0]$14786 \xive11_pri - assign $1\xive12_pri$next[7:0]$14787 \xive12_pri - assign $1\xive13_pri$next[7:0]$14788 \xive13_pri - assign $1\xive14_pri$next[7:0]$14789 \xive14_pri - assign $1\xive15_pri$next[7:0]$14790 \xive15_pri - assign $1\xive1_pri$next[7:0]$14791 \xive1_pri - assign $1\xive2_pri$next[7:0]$14792 \xive2_pri - assign $1\xive3_pri$next[7:0]$14793 \xive3_pri - assign $1\xive4_pri$next[7:0]$14794 \xive4_pri - assign $1\xive5_pri$next[7:0]$14795 \xive5_pri - assign $1\xive6_pri$next[7:0]$14796 \xive6_pri - assign $1\xive7_pri$next[7:0]$14797 \xive7_pri - assign $1\xive8_pri$next[7:0]$14798 \xive8_pri - assign $1\xive9_pri$next[7:0]$14799 \xive9_pri + assign $2\xive0_pri$next[7:0]$14985 \xive0_pri + assign $2\xive10_pri$next[7:0]$14986 \xive10_pri + assign $2\xive11_pri$next[7:0]$14987 \xive11_pri + assign $2\xive12_pri$next[7:0]$14988 \xive12_pri + assign $2\xive13_pri$next[7:0]$14989 \xive13_pri + assign $2\xive14_pri$next[7:0]$14990 \xive14_pri + assign $2\xive15_pri$next[7:0]$14991 \xive15_pri + assign $2\xive1_pri$next[7:0]$14992 \xive1_pri + assign $2\xive2_pri$next[7:0]$14993 \xive2_pri + assign $2\xive3_pri$next[7:0]$14994 \xive3_pri + assign $2\xive4_pri$next[7:0]$14995 \xive4_pri + assign $2\xive5_pri$next[7:0]$14996 \xive5_pri + assign $2\xive6_pri$next[7:0]$14997 \xive6_pri + assign $2\xive7_pri$next[7:0]$14998 \xive7_pri + assign $2\xive8_pri$next[7:0]$14999 \xive8_pri + assign $2\xive9_pri$next[7:0]$15000 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14969 \xive0_pri + assign $1\xive10_pri$next[7:0]$14970 \xive10_pri + assign $1\xive11_pri$next[7:0]$14971 \xive11_pri + assign $1\xive12_pri$next[7:0]$14972 \xive12_pri + assign $1\xive13_pri$next[7:0]$14973 \xive13_pri + assign $1\xive14_pri$next[7:0]$14974 \xive14_pri + assign $1\xive15_pri$next[7:0]$14975 \xive15_pri + assign $1\xive1_pri$next[7:0]$14976 \xive1_pri + assign $1\xive2_pri$next[7:0]$14977 \xive2_pri + assign $1\xive3_pri$next[7:0]$14978 \xive3_pri + assign $1\xive4_pri$next[7:0]$14979 \xive4_pri + assign $1\xive5_pri$next[7:0]$14980 \xive5_pri + assign $1\xive6_pri$next[7:0]$14981 \xive6_pri + assign $1\xive7_pri$next[7:0]$14982 \xive7_pri + assign $1\xive8_pri$next[7:0]$14983 \xive8_pri + assign $1\xive9_pri$next[7:0]$14984 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -422253,66 +426276,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14832 8'11111111 - assign $4\xive1_pri$next[7:0]$14839 8'11111111 - assign $4\xive2_pri$next[7:0]$14840 8'11111111 - assign $4\xive3_pri$next[7:0]$14841 8'11111111 - assign $4\xive4_pri$next[7:0]$14842 8'11111111 - assign $4\xive5_pri$next[7:0]$14843 8'11111111 - assign $4\xive6_pri$next[7:0]$14844 8'11111111 - assign $4\xive7_pri$next[7:0]$14845 8'11111111 - assign $4\xive8_pri$next[7:0]$14846 8'11111111 - assign $4\xive9_pri$next[7:0]$14847 8'11111111 - assign $4\xive10_pri$next[7:0]$14833 8'11111111 - assign $4\xive11_pri$next[7:0]$14834 8'11111111 - assign $4\xive12_pri$next[7:0]$14835 8'11111111 - assign $4\xive13_pri$next[7:0]$14836 8'11111111 - assign $4\xive14_pri$next[7:0]$14837 8'11111111 - assign $4\xive15_pri$next[7:0]$14838 8'11111111 + assign $4\xive0_pri$next[7:0]$15017 8'11111111 + assign $4\xive1_pri$next[7:0]$15024 8'11111111 + assign $4\xive2_pri$next[7:0]$15025 8'11111111 + assign $4\xive3_pri$next[7:0]$15026 8'11111111 + assign $4\xive4_pri$next[7:0]$15027 8'11111111 + assign $4\xive5_pri$next[7:0]$15028 8'11111111 + assign $4\xive6_pri$next[7:0]$15029 8'11111111 + assign $4\xive7_pri$next[7:0]$15030 8'11111111 + assign $4\xive8_pri$next[7:0]$15031 8'11111111 + assign $4\xive9_pri$next[7:0]$15032 8'11111111 + assign $4\xive10_pri$next[7:0]$15018 8'11111111 + assign $4\xive11_pri$next[7:0]$15019 8'11111111 + assign $4\xive12_pri$next[7:0]$15020 8'11111111 + assign $4\xive13_pri$next[7:0]$15021 8'11111111 + assign $4\xive14_pri$next[7:0]$15022 8'11111111 + assign $4\xive15_pri$next[7:0]$15023 8'11111111 case - assign $4\xive0_pri$next[7:0]$14832 $1\xive0_pri$next[7:0]$14784 - assign $4\xive10_pri$next[7:0]$14833 $1\xive10_pri$next[7:0]$14785 - assign $4\xive11_pri$next[7:0]$14834 $1\xive11_pri$next[7:0]$14786 - assign $4\xive12_pri$next[7:0]$14835 $1\xive12_pri$next[7:0]$14787 - assign $4\xive13_pri$next[7:0]$14836 $1\xive13_pri$next[7:0]$14788 - assign $4\xive14_pri$next[7:0]$14837 $1\xive14_pri$next[7:0]$14789 - assign $4\xive15_pri$next[7:0]$14838 $1\xive15_pri$next[7:0]$14790 - assign $4\xive1_pri$next[7:0]$14839 $1\xive1_pri$next[7:0]$14791 - assign $4\xive2_pri$next[7:0]$14840 $1\xive2_pri$next[7:0]$14792 - assign $4\xive3_pri$next[7:0]$14841 $1\xive3_pri$next[7:0]$14793 - assign $4\xive4_pri$next[7:0]$14842 $1\xive4_pri$next[7:0]$14794 - assign $4\xive5_pri$next[7:0]$14843 $1\xive5_pri$next[7:0]$14795 - assign $4\xive6_pri$next[7:0]$14844 $1\xive6_pri$next[7:0]$14796 - assign $4\xive7_pri$next[7:0]$14845 $1\xive7_pri$next[7:0]$14797 - assign $4\xive8_pri$next[7:0]$14846 $1\xive8_pri$next[7:0]$14798 - assign $4\xive9_pri$next[7:0]$14847 $1\xive9_pri$next[7:0]$14799 + assign $4\xive0_pri$next[7:0]$15017 $1\xive0_pri$next[7:0]$14969 + assign $4\xive10_pri$next[7:0]$15018 $1\xive10_pri$next[7:0]$14970 + assign $4\xive11_pri$next[7:0]$15019 $1\xive11_pri$next[7:0]$14971 + assign $4\xive12_pri$next[7:0]$15020 $1\xive12_pri$next[7:0]$14972 + assign $4\xive13_pri$next[7:0]$15021 $1\xive13_pri$next[7:0]$14973 + assign $4\xive14_pri$next[7:0]$15022 $1\xive14_pri$next[7:0]$14974 + assign $4\xive15_pri$next[7:0]$15023 $1\xive15_pri$next[7:0]$14975 + assign $4\xive1_pri$next[7:0]$15024 $1\xive1_pri$next[7:0]$14976 + assign $4\xive2_pri$next[7:0]$15025 $1\xive2_pri$next[7:0]$14977 + assign $4\xive3_pri$next[7:0]$15026 $1\xive3_pri$next[7:0]$14978 + assign $4\xive4_pri$next[7:0]$15027 $1\xive4_pri$next[7:0]$14979 + assign $4\xive5_pri$next[7:0]$15028 $1\xive5_pri$next[7:0]$14980 + assign $4\xive6_pri$next[7:0]$15029 $1\xive6_pri$next[7:0]$14981 + assign $4\xive7_pri$next[7:0]$15030 $1\xive7_pri$next[7:0]$14982 + assign $4\xive8_pri$next[7:0]$15031 $1\xive8_pri$next[7:0]$14983 + assign $4\xive9_pri$next[7:0]$15032 $1\xive9_pri$next[7:0]$14984 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14768 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14769 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14770 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14771 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14772 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14773 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14774 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14775 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14776 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14777 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14778 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14779 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14780 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14781 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14782 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14783 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14953 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14954 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14955 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14956 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14957 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14958 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14959 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14960 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14961 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14962 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14963 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14964 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14965 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14966 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14967 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14968 end - attribute \src "libresoc.v:200696.3-200705.6" - process $proc$libresoc.v:200696$14848 + attribute \src "libresoc.v:203009.3-203018.6" + process $proc$libresoc.v:203009$15033 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:200697.5-200697.29" + attribute \src "libresoc.v:203010.5-203010.29" switch \initial - attribute \src "libresoc.v:200697.9-200697.17" + attribute \src "libresoc.v:203010.9-203010.17" case 1'1 case end @@ -422328,14 +426351,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:200706.3-200715.6" - process $proc$libresoc.v:200706$14849 + attribute \src "libresoc.v:203019.3-203028.6" + process $proc$libresoc.v:203019$15034 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:200707.5-200707.29" + attribute \src "libresoc.v:203020.5-203020.29" switch \initial - attribute \src "libresoc.v:200707.9-200707.17" + attribute \src "libresoc.v:203020.9-203020.17" case 1'1 case end @@ -422351,14 +426374,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:200716.3-200725.6" - process $proc$libresoc.v:200716$14850 + attribute \src "libresoc.v:203029.3-203038.6" + process $proc$libresoc.v:203029$15035 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:200717.5-200717.29" + attribute \src "libresoc.v:203030.5-203030.29" switch \initial - attribute \src "libresoc.v:200717.9-200717.17" + attribute \src "libresoc.v:203030.9-203030.17" case 1'1 case end @@ -422374,14 +426397,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:200726.3-200735.6" - process $proc$libresoc.v:200726$14851 + attribute \src "libresoc.v:203039.3-203048.6" + process $proc$libresoc.v:203039$15036 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:200727.5-200727.29" + attribute \src "libresoc.v:203040.5-203040.29" switch \initial - attribute \src "libresoc.v:200727.9-200727.17" + attribute \src "libresoc.v:203040.9-203040.17" case 1'1 case end @@ -422397,14 +426420,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:200736.3-200745.6" - process $proc$libresoc.v:200736$14852 + attribute \src "libresoc.v:203049.3-203058.6" + process $proc$libresoc.v:203049$15037 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:200737.5-200737.29" + attribute \src "libresoc.v:203050.5-203050.29" switch \initial - attribute \src "libresoc.v:200737.9-200737.17" + attribute \src "libresoc.v:203050.9-203050.17" case 1'1 case end @@ -422420,14 +426443,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:200746.3-200755.6" - process $proc$libresoc.v:200746$14853 + attribute \src "libresoc.v:203059.3-203068.6" + process $proc$libresoc.v:203059$15038 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:200747.5-200747.29" + attribute \src "libresoc.v:203060.5-203060.29" switch \initial - attribute \src "libresoc.v:200747.9-200747.17" + attribute \src "libresoc.v:203060.9-203060.17" case 1'1 case end @@ -422443,14 +426466,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:200756.3-200765.6" - process $proc$libresoc.v:200756$14854 + attribute \src "libresoc.v:203069.3-203078.6" + process $proc$libresoc.v:203069$15039 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:200757.5-200757.29" + attribute \src "libresoc.v:203070.5-203070.29" switch \initial - attribute \src "libresoc.v:200757.9-200757.17" + attribute \src "libresoc.v:203070.9-203070.17" case 1'1 case end @@ -422466,14 +426489,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:200766.3-200775.6" - process $proc$libresoc.v:200766$14855 + attribute \src "libresoc.v:203079.3-203088.6" + process $proc$libresoc.v:203079$15040 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:200767.5-200767.29" + attribute \src "libresoc.v:203080.5-203080.29" switch \initial - attribute \src "libresoc.v:200767.9-200767.17" + attribute \src "libresoc.v:203080.9-203080.17" case 1'1 case end @@ -422489,14 +426512,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:200776.3-200785.6" - process $proc$libresoc.v:200776$14856 + attribute \src "libresoc.v:203089.3-203098.6" + process $proc$libresoc.v:203089$15041 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:200777.5-200777.29" + attribute \src "libresoc.v:203090.5-203090.29" switch \initial - attribute \src "libresoc.v:200777.9-200777.17" + attribute \src "libresoc.v:203090.9-203090.17" case 1'1 case end @@ -422512,14 +426535,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:200786.3-200794.6" - process $proc$libresoc.v:200786$14857 + attribute \src "libresoc.v:203099.3-203107.6" + process $proc$libresoc.v:203099$15042 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14858 $1\int_level_l$next[15:0]$14859 - attribute \src "libresoc.v:200787.5-200787.29" + assign $0\int_level_l$next[15:0]$15043 $1\int_level_l$next[15:0]$15044 + attribute \src "libresoc.v:203100.5-203100.29" switch \initial - attribute \src "libresoc.v:200787.9-200787.17" + attribute \src "libresoc.v:203100.9-203100.17" case 1'1 case end @@ -422528,21 +426551,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14859 16'0000000000000000 + assign $1\int_level_l$next[15:0]$15044 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14859 \int_level_i + assign $1\int_level_l$next[15:0]$15044 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14858 + update \int_level_l$next $0\int_level_l$next[15:0]$15043 end - attribute \src "libresoc.v:200795.3-200804.6" - process $proc$libresoc.v:200795$14860 + attribute \src "libresoc.v:203108.3-203117.6" + process $proc$libresoc.v:203108$15045 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:200796.5-200796.29" + attribute \src "libresoc.v:203109.5-203109.29" switch \initial - attribute \src "libresoc.v:200796.9-200796.17" + attribute \src "libresoc.v:203109.9-203109.17" case 1'1 case end @@ -422558,14 +426581,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:200805.3-200814.6" - process $proc$libresoc.v:200805$14861 + attribute \src "libresoc.v:203118.3-203127.6" + process $proc$libresoc.v:203118$15046 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:200806.5-200806.29" + attribute \src "libresoc.v:203119.5-203119.29" switch \initial - attribute \src "libresoc.v:200806.9-200806.17" + attribute \src "libresoc.v:203119.9-203119.17" case 1'1 case end @@ -422581,14 +426604,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:200815.3-200824.6" - process $proc$libresoc.v:200815$14862 + attribute \src "libresoc.v:203128.3-203137.6" + process $proc$libresoc.v:203128$15047 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:200816.5-200816.29" + attribute \src "libresoc.v:203129.5-203129.29" switch \initial - attribute \src "libresoc.v:200816.9-200816.17" + attribute \src "libresoc.v:203129.9-203129.17" case 1'1 case end @@ -422604,14 +426627,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:200825.3-200834.6" - process $proc$libresoc.v:200825$14863 + attribute \src "libresoc.v:203138.3-203147.6" + process $proc$libresoc.v:203138$15048 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:200826.5-200826.29" + attribute \src "libresoc.v:203139.5-203139.29" switch \initial - attribute \src "libresoc.v:200826.9-200826.17" + attribute \src "libresoc.v:203139.9-203139.17" case 1'1 case end @@ -422627,14 +426650,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:200835.3-200844.6" - process $proc$libresoc.v:200835$14864 + attribute \src "libresoc.v:203148.3-203157.6" + process $proc$libresoc.v:203148$15049 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:200836.5-200836.29" + attribute \src "libresoc.v:203149.5-203149.29" switch \initial - attribute \src "libresoc.v:200836.9-200836.17" + attribute \src "libresoc.v:203149.9-203149.17" case 1'1 case end @@ -422650,14 +426673,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:200845.3-200854.6" - process $proc$libresoc.v:200845$14865 + attribute \src "libresoc.v:203158.3-203167.6" + process $proc$libresoc.v:203158$15050 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:200846.5-200846.29" + attribute \src "libresoc.v:203159.5-203159.29" switch \initial - attribute \src "libresoc.v:200846.9-200846.17" + attribute \src "libresoc.v:203159.9-203159.17" case 1'1 case end @@ -422673,14 +426696,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:200855.3-200864.6" - process $proc$libresoc.v:200855$14866 + attribute \src "libresoc.v:203168.3-203177.6" + process $proc$libresoc.v:203168$15051 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:200856.5-200856.29" + attribute \src "libresoc.v:203169.5-203169.29" switch \initial - attribute \src "libresoc.v:200856.9-200856.17" + attribute \src "libresoc.v:203169.9-203169.17" case 1'1 case end @@ -422696,14 +426719,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:200865.3-200874.6" - process $proc$libresoc.v:200865$14867 + attribute \src "libresoc.v:203178.3-203187.6" + process $proc$libresoc.v:203178$15052 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:200866.5-200866.29" + attribute \src "libresoc.v:203179.5-203179.29" switch \initial - attribute \src "libresoc.v:200866.9-200866.17" + attribute \src "libresoc.v:203179.9-203179.17" case 1'1 case end @@ -422719,14 +426742,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:200875.3-200884.6" - process $proc$libresoc.v:200875$14868 + attribute \src "libresoc.v:203188.3-203197.6" + process $proc$libresoc.v:203188$15053 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:200876.5-200876.29" + attribute \src "libresoc.v:203189.5-203189.29" switch \initial - attribute \src "libresoc.v:200876.9-200876.17" + attribute \src "libresoc.v:203189.9-203189.17" case 1'1 case end @@ -422742,14 +426765,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:200885.3-200894.6" - process $proc$libresoc.v:200885$14869 + attribute \src "libresoc.v:203198.3-203207.6" + process $proc$libresoc.v:203198$15054 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:200886.5-200886.29" + attribute \src "libresoc.v:203199.5-203199.29" switch \initial - attribute \src "libresoc.v:200886.9-200886.17" + attribute \src "libresoc.v:203199.9-203199.17" case 1'1 case end @@ -422765,14 +426788,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:200895.3-200904.6" - process $proc$libresoc.v:200895$14870 + attribute \src "libresoc.v:203208.3-203217.6" + process $proc$libresoc.v:203208$15055 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:200896.5-200896.29" + attribute \src "libresoc.v:203209.5-203209.29" switch \initial - attribute \src "libresoc.v:200896.9-200896.17" + attribute \src "libresoc.v:203209.9-203209.17" case 1'1 case end @@ -422788,14 +426811,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:200905.3-200914.6" - process $proc$libresoc.v:200905$14871 + attribute \src "libresoc.v:203218.3-203227.6" + process $proc$libresoc.v:203218$15056 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:200906.5-200906.29" + attribute \src "libresoc.v:203219.5-203219.29" switch \initial - attribute \src "libresoc.v:200906.9-200906.17" + attribute \src "libresoc.v:203219.9-203219.17" case 1'1 case end @@ -422811,14 +426834,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:200915.3-200924.6" - process $proc$libresoc.v:200915$14872 + attribute \src "libresoc.v:203228.3-203237.6" + process $proc$libresoc.v:203228$15057 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:200916.5-200916.29" + attribute \src "libresoc.v:203229.5-203229.29" switch \initial - attribute \src "libresoc.v:200916.9-200916.17" + attribute \src "libresoc.v:203229.9-203229.17" case 1'1 case end @@ -422834,14 +426857,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:200925.3-200934.6" - process $proc$libresoc.v:200925$14873 + attribute \src "libresoc.v:203238.3-203247.6" + process $proc$libresoc.v:203238$15058 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:200926.5-200926.29" + attribute \src "libresoc.v:203239.5-203239.29" switch \initial - attribute \src "libresoc.v:200926.9-200926.17" + attribute \src "libresoc.v:203239.9-203239.17" case 1'1 case end @@ -422857,14 +426880,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:200935.3-200944.6" - process $proc$libresoc.v:200935$14874 + attribute \src "libresoc.v:203248.3-203257.6" + process $proc$libresoc.v:203248$15059 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:200936.5-200936.29" + attribute \src "libresoc.v:203249.5-203249.29" switch \initial - attribute \src "libresoc.v:200936.9-200936.17" + attribute \src "libresoc.v:203249.9-203249.17" case 1'1 case end @@ -422880,14 +426903,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:200945.3-200954.6" - process $proc$libresoc.v:200945$14875 + attribute \src "libresoc.v:203258.3-203267.6" + process $proc$libresoc.v:203258$15060 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:200946.5-200946.29" + attribute \src "libresoc.v:203259.5-203259.29" switch \initial - attribute \src "libresoc.v:200946.9-200946.17" + attribute \src "libresoc.v:203259.9-203259.17" case 1'1 case end @@ -422903,14 +426926,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:200955.3-200964.6" - process $proc$libresoc.v:200955$14876 + attribute \src "libresoc.v:203268.3-203277.6" + process $proc$libresoc.v:203268$15061 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:200956.5-200956.29" + attribute \src "libresoc.v:203269.5-203269.29" switch \initial - attribute \src "libresoc.v:200956.9-200956.17" + attribute \src "libresoc.v:203269.9-203269.17" case 1'1 case end @@ -422926,14 +426949,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:200965.3-200974.6" - process $proc$libresoc.v:200965$14877 + attribute \src "libresoc.v:203278.3-203287.6" + process $proc$libresoc.v:203278$15062 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:200966.5-200966.29" + attribute \src "libresoc.v:203279.5-203279.29" switch \initial - attribute \src "libresoc.v:200966.9-200966.17" + attribute \src "libresoc.v:203279.9-203279.17" case 1'1 case end @@ -422949,14 +426972,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:200975.3-200984.6" - process $proc$libresoc.v:200975$14878 + attribute \src "libresoc.v:203288.3-203297.6" + process $proc$libresoc.v:203288$15063 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:200976.5-200976.29" + attribute \src "libresoc.v:203289.5-203289.29" switch \initial - attribute \src "libresoc.v:200976.9-200976.17" + attribute \src "libresoc.v:203289.9-203289.17" case 1'1 case end @@ -422972,14 +426995,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:200985.3-200994.6" - process $proc$libresoc.v:200985$14879 + attribute \src "libresoc.v:203298.3-203307.6" + process $proc$libresoc.v:203298$15064 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:200986.5-200986.29" + attribute \src "libresoc.v:203299.5-203299.29" switch \initial - attribute \src "libresoc.v:200986.9-200986.17" + attribute \src "libresoc.v:203299.9-203299.17" case 1'1 case end @@ -422995,14 +427018,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:200995.3-201044.6" - process $proc$libresoc.v:200995$14880 + attribute \src "libresoc.v:203308.3-203357.6" + process $proc$libresoc.v:203308$15065 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:200996.5-200996.29" + attribute \src "libresoc.v:203309.5-203309.29" switch \initial - attribute \src "libresoc.v:200996.9-200996.17" + attribute \src "libresoc.v:203309.9-203309.17" case 1'1 case end @@ -423095,14 +427118,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:201045.3-201054.6" - process $proc$libresoc.v:201045$14881 + attribute \src "libresoc.v:203358.3-203367.6" + process $proc$libresoc.v:203358$15066 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:201046.5-201046.29" + attribute \src "libresoc.v:203359.5-203359.29" switch \initial - attribute \src "libresoc.v:201046.9-201046.17" + attribute \src "libresoc.v:203359.9-203359.17" case 1'1 case end @@ -423118,14 +427141,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:201055.3-201064.6" - process $proc$libresoc.v:201055$14882 + attribute \src "libresoc.v:203368.3-203377.6" + process $proc$libresoc.v:203368$15067 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:201056.5-201056.29" + attribute \src "libresoc.v:203369.5-203369.29" switch \initial - attribute \src "libresoc.v:201056.9-201056.17" + attribute \src "libresoc.v:203369.9-203369.17" case 1'1 case end @@ -423141,14 +427164,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:201065.3-201074.6" - process $proc$libresoc.v:201065$14883 + attribute \src "libresoc.v:203378.3-203387.6" + process $proc$libresoc.v:203378$15068 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:201066.5-201066.29" + attribute \src "libresoc.v:203379.5-203379.29" switch \initial - attribute \src "libresoc.v:201066.9-201066.17" + attribute \src "libresoc.v:203379.9-203379.17" case 1'1 case end @@ -423164,14 +427187,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:201075.3-201084.6" - process $proc$libresoc.v:201075$14884 + attribute \src "libresoc.v:203388.3-203397.6" + process $proc$libresoc.v:203388$15069 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:201076.5-201076.29" + attribute \src "libresoc.v:203389.5-203389.29" switch \initial - attribute \src "libresoc.v:201076.9-201076.17" + attribute \src "libresoc.v:203389.9-203389.17" case 1'1 case end @@ -423187,14 +427210,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:201085.3-201093.6" - process $proc$libresoc.v:201085$14885 + attribute \src "libresoc.v:203398.3-203406.6" + process $proc$libresoc.v:203398$15070 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14886 $1\ics_wb__dat_r$next[31:0]$14887 - attribute \src "libresoc.v:201086.5-201086.29" + assign $0\ics_wb__dat_r$next[31:0]$15071 $1\ics_wb__dat_r$next[31:0]$15072 + attribute \src "libresoc.v:203399.5-203399.29" switch \initial - attribute \src "libresoc.v:201086.9-201086.17" + attribute \src "libresoc.v:203399.9-203399.17" case 1'1 case end @@ -423203,21 +427226,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14887 0 + assign $1\ics_wb__dat_r$next[31:0]$15072 0 case - assign $1\ics_wb__dat_r$next[31:0]$14887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$15072 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14886 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15071 end - attribute \src "libresoc.v:201094.3-201102.6" - process $proc$libresoc.v:201094$14888 + attribute \src "libresoc.v:203407.3-203415.6" + process $proc$libresoc.v:203407$15073 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14889 $1\ics_wb__ack$next[0:0]$14890 - attribute \src "libresoc.v:201095.5-201095.29" + assign $0\ics_wb__ack$next[0:0]$15074 $1\ics_wb__ack$next[0:0]$15075 + attribute \src "libresoc.v:203408.5-203408.29" switch \initial - attribute \src "libresoc.v:201095.9-201095.17" + attribute \src "libresoc.v:203408.9-203408.17" case 1'1 case end @@ -423226,116 +427249,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14890 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14890 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14889 - end - connect \$7 $ternary$libresoc.v:200465$14643_Y - connect \$99 $lt$libresoc.v:200466$14644_Y - connect \$101 $and$libresoc.v:200467$14645_Y - connect \$103 $lt$libresoc.v:200468$14646_Y - connect \$105 $and$libresoc.v:200469$14647_Y - connect \$107 $lt$libresoc.v:200470$14648_Y - connect \$109 $and$libresoc.v:200471$14649_Y - connect \$111 $lt$libresoc.v:200472$14650_Y - connect \$113 $and$libresoc.v:200473$14651_Y - connect \$115 $lt$libresoc.v:200474$14652_Y - connect \$117 $and$libresoc.v:200475$14653_Y - connect \$119 $lt$libresoc.v:200476$14654_Y - connect \$121 $and$libresoc.v:200477$14655_Y - connect \$123 $lt$libresoc.v:200478$14656_Y - connect \$125 $and$libresoc.v:200479$14657_Y - connect \$127 $lt$libresoc.v:200480$14658_Y - connect \$12 $eq$libresoc.v:200481$14659_Y - connect \$129 $and$libresoc.v:200482$14660_Y - connect \$131 $lt$libresoc.v:200483$14661_Y - connect \$133 $and$libresoc.v:200484$14662_Y - connect \$135 $lt$libresoc.v:200485$14663_Y - connect \$137 $and$libresoc.v:200486$14664_Y - connect \$11 $ternary$libresoc.v:200487$14665_Y - connect \$139 $lt$libresoc.v:200488$14666_Y - connect \$141 $and$libresoc.v:200489$14667_Y - connect \$143 $lt$libresoc.v:200490$14668_Y - connect \$145 $and$libresoc.v:200491$14669_Y - connect \$147 $lt$libresoc.v:200492$14670_Y - connect \$149 $and$libresoc.v:200493$14671_Y - connect \$151 $lt$libresoc.v:200494$14672_Y - connect \$153 $and$libresoc.v:200495$14673_Y - connect \$155 $lt$libresoc.v:200496$14674_Y - connect \$157 $and$libresoc.v:200497$14675_Y - connect \$159 $lt$libresoc.v:200498$14676_Y - connect \$161 $and$libresoc.v:200499$14677_Y - connect \$163 $lt$libresoc.v:200500$14678_Y - connect \$165 $and$libresoc.v:200501$14679_Y - connect \$167 $lt$libresoc.v:200502$14680_Y - connect \$16 $eq$libresoc.v:200503$14681_Y - connect \$169 $and$libresoc.v:200504$14682_Y - connect \$171 $lt$libresoc.v:200505$14683_Y - connect \$173 $and$libresoc.v:200506$14684_Y - connect \$175 $lt$libresoc.v:200507$14685_Y - connect \$177 $and$libresoc.v:200508$14686_Y - connect \$15 $ternary$libresoc.v:200509$14687_Y - connect \$179 $lt$libresoc.v:200510$14688_Y - connect \$181 $and$libresoc.v:200511$14689_Y - connect \$183 $lt$libresoc.v:200512$14690_Y - connect \$185 $and$libresoc.v:200513$14691_Y - connect \$187 $lt$libresoc.v:200514$14692_Y - connect \$189 $and$libresoc.v:200515$14693_Y - connect \$191 $lt$libresoc.v:200516$14694_Y - connect \$193 $and$libresoc.v:200517$14695_Y - connect \$195 $lt$libresoc.v:200518$14696_Y - connect \$197 $and$libresoc.v:200519$14697_Y - connect \$1 $eq$libresoc.v:200520$14698_Y - connect \$199 $lt$libresoc.v:200521$14699_Y - connect \$201 $and$libresoc.v:200522$14700_Y - connect \$204 $eq$libresoc.v:200523$14701_Y - connect \$203 $ternary$libresoc.v:200524$14702_Y - connect \$20 $eq$libresoc.v:200525$14703_Y - connect \$19 $ternary$libresoc.v:200526$14704_Y - connect \$24 $eq$libresoc.v:200527$14705_Y - connect \$23 $ternary$libresoc.v:200528$14706_Y - connect \$28 $eq$libresoc.v:200529$14707_Y - connect \$27 $ternary$libresoc.v:200530$14708_Y - connect \$32 $eq$libresoc.v:200531$14709_Y - connect \$31 $ternary$libresoc.v:200532$14710_Y - connect \$36 $eq$libresoc.v:200533$14711_Y - connect \$35 $ternary$libresoc.v:200534$14712_Y - connect \$3 $eq$libresoc.v:200535$14713_Y - connect \$40 $eq$libresoc.v:200536$14714_Y - connect \$39 $ternary$libresoc.v:200537$14715_Y - connect \$44 $eq$libresoc.v:200538$14716_Y - connect \$43 $ternary$libresoc.v:200539$14717_Y - connect \$48 $eq$libresoc.v:200540$14718_Y - connect \$47 $ternary$libresoc.v:200541$14719_Y - connect \$52 $eq$libresoc.v:200542$14720_Y - connect \$51 $ternary$libresoc.v:200543$14721_Y - connect \$56 $eq$libresoc.v:200544$14722_Y - connect \$55 $ternary$libresoc.v:200545$14723_Y - connect \$5 $and$libresoc.v:200546$14724_Y - connect \$60 $eq$libresoc.v:200547$14725_Y - connect \$59 $ternary$libresoc.v:200548$14726_Y - connect \$64 $eq$libresoc.v:200549$14727_Y - connect \$63 $ternary$libresoc.v:200550$14728_Y - connect \$68 $eq$libresoc.v:200551$14729_Y - connect \$67 $ternary$libresoc.v:200552$14730_Y - connect \$71 $shr$libresoc.v:200553$14731_Y [0] - connect \$73 $and$libresoc.v:200554$14732_Y - connect \$75 $lt$libresoc.v:200555$14733_Y - connect \$77 $and$libresoc.v:200556$14734_Y - connect \$79 $lt$libresoc.v:200557$14735_Y - connect \$81 $and$libresoc.v:200558$14736_Y - connect \$83 $lt$libresoc.v:200559$14737_Y - connect \$85 $and$libresoc.v:200560$14738_Y - connect \$87 $lt$libresoc.v:200561$14739_Y - connect \$8 $eq$libresoc.v:200562$14740_Y - connect \$89 $and$libresoc.v:200563$14741_Y - connect \$91 $lt$libresoc.v:200564$14742_Y - connect \$93 $and$libresoc.v:200565$14743_Y - connect \$95 $lt$libresoc.v:200566$14744_Y - connect \$97 $and$libresoc.v:200567$14745_Y + assign $1\ics_wb__ack$next[0:0]$15075 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15075 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15074 + end + connect \$7 $ternary$libresoc.v:202778$14828_Y + connect \$99 $lt$libresoc.v:202779$14829_Y + connect \$101 $and$libresoc.v:202780$14830_Y + connect \$103 $lt$libresoc.v:202781$14831_Y + connect \$105 $and$libresoc.v:202782$14832_Y + connect \$107 $lt$libresoc.v:202783$14833_Y + connect \$109 $and$libresoc.v:202784$14834_Y + connect \$111 $lt$libresoc.v:202785$14835_Y + connect \$113 $and$libresoc.v:202786$14836_Y + connect \$115 $lt$libresoc.v:202787$14837_Y + connect \$117 $and$libresoc.v:202788$14838_Y + connect \$119 $lt$libresoc.v:202789$14839_Y + connect \$121 $and$libresoc.v:202790$14840_Y + connect \$123 $lt$libresoc.v:202791$14841_Y + connect \$125 $and$libresoc.v:202792$14842_Y + connect \$127 $lt$libresoc.v:202793$14843_Y + connect \$12 $eq$libresoc.v:202794$14844_Y + connect \$129 $and$libresoc.v:202795$14845_Y + connect \$131 $lt$libresoc.v:202796$14846_Y + connect \$133 $and$libresoc.v:202797$14847_Y + connect \$135 $lt$libresoc.v:202798$14848_Y + connect \$137 $and$libresoc.v:202799$14849_Y + connect \$11 $ternary$libresoc.v:202800$14850_Y + connect \$139 $lt$libresoc.v:202801$14851_Y + connect \$141 $and$libresoc.v:202802$14852_Y + connect \$143 $lt$libresoc.v:202803$14853_Y + connect \$145 $and$libresoc.v:202804$14854_Y + connect \$147 $lt$libresoc.v:202805$14855_Y + connect \$149 $and$libresoc.v:202806$14856_Y + connect \$151 $lt$libresoc.v:202807$14857_Y + connect \$153 $and$libresoc.v:202808$14858_Y + connect \$155 $lt$libresoc.v:202809$14859_Y + connect \$157 $and$libresoc.v:202810$14860_Y + connect \$159 $lt$libresoc.v:202811$14861_Y + connect \$161 $and$libresoc.v:202812$14862_Y + connect \$163 $lt$libresoc.v:202813$14863_Y + connect \$165 $and$libresoc.v:202814$14864_Y + connect \$167 $lt$libresoc.v:202815$14865_Y + connect \$16 $eq$libresoc.v:202816$14866_Y + connect \$169 $and$libresoc.v:202817$14867_Y + connect \$171 $lt$libresoc.v:202818$14868_Y + connect \$173 $and$libresoc.v:202819$14869_Y + connect \$175 $lt$libresoc.v:202820$14870_Y + connect \$177 $and$libresoc.v:202821$14871_Y + connect \$15 $ternary$libresoc.v:202822$14872_Y + connect \$179 $lt$libresoc.v:202823$14873_Y + connect \$181 $and$libresoc.v:202824$14874_Y + connect \$183 $lt$libresoc.v:202825$14875_Y + connect \$185 $and$libresoc.v:202826$14876_Y + connect \$187 $lt$libresoc.v:202827$14877_Y + connect \$189 $and$libresoc.v:202828$14878_Y + connect \$191 $lt$libresoc.v:202829$14879_Y + connect \$193 $and$libresoc.v:202830$14880_Y + connect \$195 $lt$libresoc.v:202831$14881_Y + connect \$197 $and$libresoc.v:202832$14882_Y + connect \$1 $eq$libresoc.v:202833$14883_Y + connect \$199 $lt$libresoc.v:202834$14884_Y + connect \$201 $and$libresoc.v:202835$14885_Y + connect \$204 $eq$libresoc.v:202836$14886_Y + connect \$203 $ternary$libresoc.v:202837$14887_Y + connect \$20 $eq$libresoc.v:202838$14888_Y + connect \$19 $ternary$libresoc.v:202839$14889_Y + connect \$24 $eq$libresoc.v:202840$14890_Y + connect \$23 $ternary$libresoc.v:202841$14891_Y + connect \$28 $eq$libresoc.v:202842$14892_Y + connect \$27 $ternary$libresoc.v:202843$14893_Y + connect \$32 $eq$libresoc.v:202844$14894_Y + connect \$31 $ternary$libresoc.v:202845$14895_Y + connect \$36 $eq$libresoc.v:202846$14896_Y + connect \$35 $ternary$libresoc.v:202847$14897_Y + connect \$3 $eq$libresoc.v:202848$14898_Y + connect \$40 $eq$libresoc.v:202849$14899_Y + connect \$39 $ternary$libresoc.v:202850$14900_Y + connect \$44 $eq$libresoc.v:202851$14901_Y + connect \$43 $ternary$libresoc.v:202852$14902_Y + connect \$48 $eq$libresoc.v:202853$14903_Y + connect \$47 $ternary$libresoc.v:202854$14904_Y + connect \$52 $eq$libresoc.v:202855$14905_Y + connect \$51 $ternary$libresoc.v:202856$14906_Y + connect \$56 $eq$libresoc.v:202857$14907_Y + connect \$55 $ternary$libresoc.v:202858$14908_Y + connect \$5 $and$libresoc.v:202859$14909_Y + connect \$60 $eq$libresoc.v:202860$14910_Y + connect \$59 $ternary$libresoc.v:202861$14911_Y + connect \$64 $eq$libresoc.v:202862$14912_Y + connect \$63 $ternary$libresoc.v:202863$14913_Y + connect \$68 $eq$libresoc.v:202864$14914_Y + connect \$67 $ternary$libresoc.v:202865$14915_Y + connect \$71 $shr$libresoc.v:202866$14916_Y [0] + connect \$73 $and$libresoc.v:202867$14917_Y + connect \$75 $lt$libresoc.v:202868$14918_Y + connect \$77 $and$libresoc.v:202869$14919_Y + connect \$79 $lt$libresoc.v:202870$14920_Y + connect \$81 $and$libresoc.v:202871$14921_Y + connect \$83 $lt$libresoc.v:202872$14922_Y + connect \$85 $and$libresoc.v:202873$14923_Y + connect \$87 $lt$libresoc.v:202874$14924_Y + connect \$8 $eq$libresoc.v:202875$14925_Y + connect \$89 $and$libresoc.v:202876$14926_Y + connect \$91 $lt$libresoc.v:202877$14927_Y + connect \$93 $and$libresoc.v:202878$14928_Y + connect \$95 $lt$libresoc.v:202879$14929_Y + connect \$97 $and$libresoc.v:202880$14930_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2